From 8708cddde16863c86d15b8781db40739d64ff4bb Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Thu, 16 Jun 2016 13:44:14 +0200 Subject: [PATCH 001/734] mmc1 copy + dcache --- arch/arm/src/stm32f7/Make.defs | 4 + arch/arm/src/stm32f7/chip/stm32_sdmmc.h | 52 + .../src/stm32f7/chip/stm32f74xx75xx_sdmmc.h | 268 ++ arch/arm/src/stm32f7/stm32_sdmmc.c | 2977 +++++++++++++++++ arch/arm/src/stm32f7/stm32_sdmmc.h | 129 + configs/stm32f746-ws/include/board.h | 42 + configs/stm32f746-ws/nsh/defconfig | 41 +- configs/stm32f746-ws/src/stm32_spi.c | 12 +- 8 files changed, 3507 insertions(+), 18 deletions(-) create mode 100644 arch/arm/src/stm32f7/chip/stm32_sdmmc.h create mode 100644 arch/arm/src/stm32f7/chip/stm32f74xx75xx_sdmmc.h create mode 100644 arch/arm/src/stm32f7/stm32_sdmmc.c create mode 100644 arch/arm/src/stm32f7/stm32_sdmmc.h diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index 07aa380ebd..123c70ffc2 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -147,6 +147,10 @@ ifeq ($(CONFIG_STM32F7_SPI),y) CHIP_CSRCS += stm32_spi.c endif +ifeq ($(CONFIG_STM32F7_SDMMC1),y) +CHIP_CSRCS += stm32_sdmmc.c +endif + ifeq ($(CONFIG_STM32F7_TIM),y) CHIP_CSRCS += stm32_tim.c endif diff --git a/arch/arm/src/stm32f7/chip/stm32_sdmmc.h b/arch/arm/src/stm32f7/chip/stm32_sdmmc.h new file mode 100644 index 0000000000..e04bdddc1e --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32_sdmmc.h @@ -0,0 +1,52 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/chip/stm32_i2c.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SDMMC_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SDMMC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +# include "stm32f74xx75xx_sdmmc.h" +#else +# error "Unsupported STM32 F7 part" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SDMMC_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_sdmmc.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_sdmmc.h new file mode 100644 index 0000000000..e40990ec16 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_sdmmc.h @@ -0,0 +1,268 @@ +/************************************************************************************ + * arch/arm/src/stm32/chip/stm32_sdio.h + * + * Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SDMMC_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SDMMC_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_SDMMC1_POWER_OFFSET 0x0000 /* SDIO power control register */ +#define STM32_SDMMC1_CLKCR_OFFSET 0x0004 /* SDI clock control register */ +#define STM32_SDMMC1_ARG_OFFSET 0x0008 /* SDIO argument register */ +#define STM32_SDMMC1_CMD_OFFSET 0x000c /* SDIO command register */ +#define STM32_SDMMC1_RESPCMD_OFFSET 0x0010 /* SDIO command response register */ +#define STM32_SDMMC1_RESP_OFFSET(n) (0x0010+4*(n)) +#define STM32_SDMMC1_RESP1_OFFSET 0x0014 /* SDIO response 1 register */ +#define STM32_SDMMC1_RESP2_OFFSET 0x0018 /* SDIO response 2 register */ +#define STM32_SDMMC1_RESP3_OFFSET 0x001c /* SDIO response 3 register */ +#define STM32_SDMMC1_RESP4_OFFSET 0x0020 /* SDIO response 4 register */ +#define STM32_SDMMC1_DTIMER_OFFSET 0x0024 /* SDIO data timer register */ +#define STM32_SDMMC1_DLEN_OFFSET 0x0028 /* SDIO data length register */ +#define STM32_SDMMC1_DCTRL_OFFSET 0x002c /* SDIO data control register */ +#define STM32_SDMMC1_DCOUNT_OFFSET 0x0030 /* SDIO data counter register */ +#define STM32_SDMMC1_STA_OFFSET 0x0034 /* SDIO status register */ +#define STM32_SDMMC1_ICR_OFFSET 0x0038 /* SDIO interrupt clear register */ +#define STM32_SDMMC1_MASK_OFFSET 0x003c /* SDIO mask register */ +#define STM32_SDMMC1_FIFOCNT_OFFSET 0x0048 /* SDIO FIFO counter register */ +#define STM32_SDMMC1_FIFO_OFFSET 0x0080 /* SDIO data FIFO register */ + +/* Register Addresses ***************************************************************/ + +#define STM32_SDMMC1_POWER (STM32_SDMMC1_BASE+STM32_SDMMC1_POWER_OFFSET) +#define STM32_SDMMC1_CLKCR (STM32_SDMMC1_BASE+STM32_SDMMC1_CLKCR_OFFSET) +#define STM32_SDMMC1_ARG (STM32_SDMMC1_BASE+STM32_SDMMC1_ARG_OFFSET) +#define STM32_SDMMC1_CMD (STM32_SDMMC1_BASE+STM32_SDMMC1_CMD_OFFSET) +#define STM32_SDMMC1_RESPCMD (STM32_SDMMC1_BASE+STM32_SDMMC1_RESPCMD_OFFSET) +#define STM32_SDMMC1_RESP(n) (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP_OFFSET(n)) +#define STM32_SDMMC1_RESP1 (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP1_OFFSET) +#define STM32_SDMMC1_RESP2 (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP2_OFFSET) +#define STM32_SDMMC1_RESP3 (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP3_OFFSET) +#define STM32_SDMMC1_RESP4 (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP4_OFFSET) +#define STM32_SDMMC1_DTIMER (STM32_SDMMC1_BASE+STM32_SDMMC1_DTIMER_OFFSET) +#define STM32_SDMMC1_DLEN (STM32_SDMMC1_BASE+STM32_SDMMC1_DLEN_OFFSET) +#define STM32_SDMMC1_DCTRL (STM32_SDMMC1_BASE+STM32_SDMMC1_DCTRL_OFFSET) +#define STM32_SDMMC1_DCOUNT (STM32_SDMMC1_BASE+STM32_SDMMC1_DCOUNT_OFFSET) +#define STM32_SDMMC1_STA (STM32_SDMMC1_BASE+STM32_SDMMC1_STA_OFFSET) +#define STM32_SDMMC1_ICR (STM32_SDMMC1_BASE+STM32_SDMMC1_ICR_OFFSET) +#define STM32_SDMMC1_MASK (STM32_SDMMC1_BASE+STM32_SDMMC1_MASK_OFFSET) +#define STM32_SDMMC1_FIFOCNT (STM32_SDMMC1_BASE+STM32_SDMMC1_FIFOCNT_OFFSET) +#define STM32_SDMMC1_FIFO (STM32_SDMMC1_BASE+STM32_SDMMC1_FIFO_OFFSET) + + +/* Register Bitfield Definitions ****************************************************/ + +#define SDIO_POWER_PWRCTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */ +#define SDIO_POWER_PWRCTRL_MASK (3 << SDIO_POWER_PWRCTRL_SHIFT) +# define SDIO_POWER_PWRCTRL_OFF (0 << SDIO_POWER_PWRCTRL_SHIFT) /* 00: Power-off: card clock stopped */ +# define SDIO_POWER_PWRCTRL_PWRUP (2 << SDIO_POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */ +# define SDIO_POWER_PWRCTRL_ON (3 << SDIO_POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */ + +#define SDIO_POWER_RESET (0) /* Reset value */ + +#define SDIO_CLKCR_CLKDIV_SHIFT (0) /* Bits 7-0: Clock divide factor */ +#define SDIO_CLKCR_CLKDIV_MASK (0xff << SDIO_CLKCR_CLKDIV_SHIFT) +#define SDIO_CLKCR_CLKEN (1 << 8) /* Bit 8: Clock enable bit */ +#define SDIO_CLKCR_PWRSAV (1 << 9) /* Bit 9: Power saving configuration bit */ +#define SDIO_CLKCR_BYPASS (1 << 10) /* Bit 10: Clock divider bypass enable bit */ +#define SDIO_CLKCR_WIDBUS_SHIFT (11) /* Bits 12-11: Wide bus mode enable bits */ +#define SDIO_CLKCR_WIDBUS_MASK (3 << SDIO_CLKCR_WIDBUS_SHIFT) +# define SDIO_CLKCR_WIDBUS_D1 (0 << SDIO_CLKCR_WIDBUS_SHIFT) /* 00: Default (SDIO_D0) */ +# define SDIO_CLKCR_WIDBUS_D4 (1 << SDIO_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (SDIO_D[3:0]) */ +# define SDIO_CLKCR_WIDBUS_D8 (2 << SDIO_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (SDIO_D[7:0]) */ +#define SDIO_CLKCR_NEGEDGE (1 << 13) /* Bit 13: SDIO_CK dephasing selection bit */ +#define SDIO_CLKCR_HWFC_EN (1 << 14) /* Bit 14: HW Flow Control enable */ + +#define SDIO_CLKCR_RESET (0) /* Reset value */ +#define SDIO_ARG_RESET (0) /* Reset value */ + +#define SDIO_CLKCR_CLKEN_BB (STM32_SDMMC1_CLKCR_BB + (8 * 4)) +#define SDIO_CLKCR_PWRSAV_BB (STM32_SDMMC1_CLKCR_BB + (9 * 4)) +#define SDIO_CLKCR_BYPASS_BB (STM32_SDMMC1_CLKCR_BB + (10 * 4)) +#define SDIO_CLKCR_NEGEDGE_BB (STM32_SDMMC1_CLKCR_BB + (13 * 4)) +#define SDIO_CLKCR_HWFC_EN_BB (STM32_SDMMC1_CLKCR_BB + (14 * 4)) + +#define SDIO_CMD_CMDINDEX_SHIFT (0) +#define SDIO_CMD_CMDINDEX_MASK (0x3f << SDIO_CMD_CMDINDEX_SHIFT) +#define SDIO_CMD_WAITRESP_SHIFT (6) /* Bits 7-6: Wait for response bits */ +#define SDIO_CMD_WAITRESP_MASK (3 << SDIO_CMD_WAITRESP_SHIFT) +# define SDIO_CMD_NORESPONSE (0 << SDIO_CMD_WAITRESP_SHIFT) /* 00/10: No response */ +# define SDIO_CMD_SHORTRESPONSE (1 << SDIO_CMD_WAITRESP_SHIFT) /* 01: Short response */ +# define SDIO_CMD_LONGRESPONSE (3 << SDIO_CMD_WAITRESP_SHIFT) /* 11: Long response */ +#define SDIO_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */ +#define SDIO_CMD_WAITPEND (1 << 9) /* Bit 9: CPSM Waits for ends of data transfer */ +#define SDIO_CMD_CPSMEN (1 << 10) /* Bit 10: Command path state machine enable */ +#define SDIO_CMD_SUSPEND (1 << 11) /* Bit 11: SD I/O suspend command */ +#define SDIO_CMD_ENDCMD (1 << 12) /* Bit 12: Enable CMD completion */ +#define SDIO_CMD_NIEN (1 << 13) /* Bit 13: not Interrupt Enable */ +#define SDIO_CMD_ATACMD (1 << 14) /* Bit 14: CE-ATA command */ + +#define SDIO_CMD_RESET (0) /* Reset value */ + +#define SDIO_CMD_WAITINT_BB (STM32_SDMMC1_CMD_BB + (8 * 4)) +#define SDIO_CMD_WAITPEND_BB (STM32_SDMMC1_CMD_BB + (9 * 4)) +#define SDIO_CMD_CPSMEN_BB (STM32_SDMMC1_CMD_BB + (10 * 4)) +#define SDIO_CMD_SUSPEND_BB (STM32_SDMMC1_CMD_BB + (11 * 4)) +#define SDIO_CMD_ENCMD_BB (STM32_SDMMC1_CMD_BB + (12 * 4)) +#define SDIO_CMD_NIEN_BB (STM32_SDMMC1_CMD_BB + (13 * 4)) +#define SDIO_CMD_ATACMD_BB (STM32_SDMMC1_CMD_BB + (14 * 4)) + +#define SDIO_RESPCMD_SHIFT (0) +#define SDIO_RESPCMD_MASK (0x3f << SDIO_RESPCMD_SHIFT) + +#define SDIO_DTIMER_RESET (0) /* Reset value */ + +#define SDIO_DLEN_SHIFT (0) +#define SDIO_DLEN_MASK (0x01ffffff << SDIO_DLEN_SHIFT) + +#define SDIO_DLEN_RESET (0) /* Reset value */ + +#define SDIO_DCTRL_DTEN (1 << 0) /* Bit 0: Data transfer enabled bit */ +#define SDIO_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */ +#define SDIO_DCTRL_DTMODE (1 << 2) /* Bit 2: Data transfer mode */ +#define SDIO_DCTRL_DMAEN (1 << 3) /* Bit 3: DMA enable bit */ +#define SDIO_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 7-4: Data block size */ +#define SDIO_DCTRL_DBLOCKSIZE_MASK (15 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_1BYTE (0 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_2BYTES (1 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_4BYTES (2 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_8BYTES (3 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_16BYTES (4 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_32BYTES (5 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_64BYTES (6 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_128BYTES (7 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_256BYTES (8 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_512BYTES (9 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_1KBYTE (10 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_2KBYTES (11 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_4KBYTES (12 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_8KBYTES (13 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_16KBYTES (14 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +#define SDIO_DCTRL_RWSTART (1 << 8) /* Bit 8: Read wait start */ +#define SDIO_DCTRL_RWSTOP (1 << 9) /* Bit 9: Read wait stop */ +#define SDIO_DCTRL_RWMOD (1 << 10) /* Bit 10: Read wait mode */ +#define SDIO_DCTRL_SDIOEN (1 << 11) /* Bit 11: SD I/O enable functions */ + +#define SDIO_DCTRL_RESET (0) /* Reset value */ + +#define SDIO_DCTRL_DTEN_BB (STM32_SDMMC1_DCTRL_BB + (0 * 4)) +#define SDIO_DCTRL_DTDIR_BB (STM32_SDMMC1_DCTRL_BB + (1 * 4)) +#define SDIO_DCTRL_DTMODE_BB (STM32_SDMMC1_DCTRL_BB + (2 * 4)) +#define SDIO_DCTRL_DMAEN_BB (STM32_SDMMC1_DCTRL_BB + (3 * 4)) +#define SDIO_DCTRL_RWSTART_BB (STM32_SDMMC1_DCTRL_BB + (8 * 4)) +#define SDIO_DCTRL_RWSTOP_BB (STM32_SDMMC1_DCTRL_BB + (9 * 4)) +#define SDIO_DCTRL_RWMOD_BB (STM32_SDMMC1_DCTRL_BB + (10 * 4)) +#define SDIO_DCTRL_SDIOEN_BB (STM32_SDMMC1_DCTRL_BB + (11 * 4)) + +#define SDIO_DATACOUNT_SHIFT (0) +#define SDIO_DATACOUNT_MASK (0x01ffffff << SDIO_DATACOUNT_SHIFT) + +#define SDIO_STA_CCRCFAIL (1 << 0) /* Bit 0: Command response CRC fail */ +#define SDIO_STA_DCRCFAIL (1 << 1) /* Bit 1: Data block CRC fail */ +#define SDIO_STA_CTIMEOUT (1 << 2) /* Bit 2: Command response timeout */ +#define SDIO_STA_DTIMEOUT (1 << 3) /* Bit 3: Data timeout */ +#define SDIO_STA_TXUNDERR (1 << 4) /* Bit 4: Transmit FIFO underrun error */ +#define SDIO_STA_RXOVERR (1 << 5) /* Bit 5: Received FIFO overrun error */ +#define SDIO_STA_CMDREND (1 << 6) /* Bit 6: Command response received */ +#define SDIO_STA_CMDSENT (1 << 7) /* Bit 7: Command sent */ +#define SDIO_STA_DATAEND (1 << 8) /* Bit 8: Data end */ +#define SDIO_STA_STBITERR (1 << 9) /* Bit 9: Start bit not detected */ +#define SDIO_STA_DBCKEND (1 << 10) /* Bit 10: Data block sent/received */ +#define SDIO_STA_CMDACT (1 << 11) /* Bit 11: Command transfer in progress */ +#define SDIO_STA_TXACT (1 << 12) /* Bit 12: Data transmit in progress */ +#define SDIO_STA_RXACT (1 << 13) /* Bit 13: Data receive in progress */ +#define SDIO_STA_TXFIFOHE (1 << 14) /* Bit 14: Transmit FIFO half empty */ +#define SDIO_STA_RXFIFOHF (1 << 15) /* Bit 15: Receive FIFO half full */ +#define SDIO_STA_TXFIFOF (1 << 16) /* Bit 16: Transmit FIFO full */ +#define SDIO_STA_RXFIFOF (1 << 17) /* Bit 17: Receive FIFO full */ +#define SDIO_STA_TXFIFOE (1 << 18) /* Bit 18: Transmit FIFO empty */ +#define SDIO_STA_RXFIFOE (1 << 19) /* Bit 19: Receive FIFO empty */ +#define SDIO_STA_TXDAVL (1 << 20) /* Bit 20: Data available in transmit FIFO */ +#define SDIO_STA_RXDAVL (1 << 21) /* Bit 21: Data available in receive FIFO */ +#define SDIO_STA_SDIOIT (1 << 22) /* Bit 22: SDIO interrupt received */ +#define SDIO_STA_CEATAEND (1 << 23) /* Bit 23: CMD6 CE-ATA command completion */ + +#define SDIO_ICR_CCRCFAILC (1 << 0) /* Bit 0: CCRCFAIL flag clear bit */ +#define SDIO_ICR_DCRCFAILC (1 << 1) /* Bit 1: DCRCFAIL flag clear bit */ +#define SDIO_ICR_CTIMEOUTC (1 << 2) /* Bit 2: CTIMEOUT flag clear bit */ +#define SDIO_ICR_DTIMEOUTC (1 << 3) /* Bit 3: DTIMEOUT flag clear bit */ +#define SDIO_ICR_TXUNDERRC (1 << 4) /* Bit 4: TXUNDERR flag clear bit */ +#define SDIO_ICR_RXOVERRC (1 << 5) /* Bit 5: RXOVERR flag clear bit */ +#define SDIO_ICR_CMDRENDC (1 << 6) /* Bit 6: CMDREND flag clear bit */ +#define SDIO_ICR_CMDSENTC (1 << 7) /* Bit 7: CMDSENT flag clear bit */ +#define SDIO_ICR_DATAENDC (1 << 8) /* Bit 8: DATAEND flag clear bit */ +#define SDIO_ICR_STBITERRC (1 << 9) /* Bit 9: STBITERR flag clear bit */ +#define SDIO_ICR_DBCKENDC (1 << 10) /* Bit 10: DBCKEND flag clear bit */ +#define SDIO_ICR_SDIOITC (1 << 22) /* Bit 22: SDIOIT flag clear bit */ +#define SDIO_ICR_CEATAENDC (1 << 23) /* Bit 23: CEATAEND flag clear bit */ + +#define SDIO_ICR_RESET 0x00c007ff +#define SDIO_ICR_STATICFLAGS 0x000005ff + +#define SDIO_MASK_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */ +#define SDIO_MASK_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */ +#define SDIO_MASK_CTIMEOUTIE (1 << 2) /* Bit 2: Command timeout interrupt enable */ +#define SDIO_MASK_DTIMEOUTIE (1 << 3) /* Bit 3: Data timeout interrupt enable */ +#define SDIO_MASK_TXUNDERRIE (1 << 4) /* Bit 4: Tx FIFO underrun error interrupt enable */ +#define SDIO_MASK_RXOVERRIE (1 << 5) /* Bit 5: Rx FIFO overrun error interrupt enable */ +#define SDIO_MASK_CMDRENDIE (1 << 6) /* Bit 6: Command response received interrupt enable */ +#define SDIO_MASK_CMDSENTIE (1 << 7) /* Bit 7: Command sent interrupt enable */ +#define SDIO_MASK_DATAENDIE (1 << 8) /* Bit 8: Data end interrupt enable */ +#define SDIO_MASK_STBITERRIE (1 << 9) /* Bit 9: Start bit error interrupt enable */ +#define SDIO_MASK_DBCKENDIE (1 << 10) /* Bit 10: Data block end interrupt enable */ +#define SDIO_MASK_CMDACTIE (1 << 11) /* Bit 11: Command acting interrupt enable */ +#define SDIO_MASK_TXACTIE (1 << 12) /* Bit 12: Data transmit acting interrupt enable */ +#define SDIO_MASK_RXACTIE (1 << 13) /* Bit 13: Data receive acting interrupt enable */ +#define SDIO_MASK_TXFIFOHEIE (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */ +#define SDIO_MASK_RXFIFOHFIE (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */ +#define SDIO_MASK_TXFIFOFIE (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */ +#define SDIO_MASK_RXFIFOFIE (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */ +#define SDIO_MASK_TXFIFOEIE (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */ +#define SDIO_MASK_RXFIFOEIE (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */ +#define SDIO_MASK_TXDAVLIE (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */ +#define SDIO_MASK_RXDAVLIE (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */ +#define SDIO_MASK_SDIOITIE (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */ +#define SDIO_MASK_CEATAENDIE (1 << 23) /* Bit 23: CE-ATA command completion interrupt enable */ + +#define SDIO_MASK_RESET (0) + +#define SDIO_FIFOCNT_SHIFT (0) +#define SDIO_FIFOCNT_MASK (0x01ffffff << SDIO_FIFOCNT_SHIFT) + +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SDMMC_H */ + diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c new file mode 100644 index 0000000000..58f7b7318d --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -0,0 +1,2977 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/stm32_sdio.c + * + * Copyright (C) 2009, 2011-2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "stm32_sdmmc.h" + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "cache.h" +#include "chip.h" +#include "up_arch.h" + +#include "stm32_dma.h" +#include "stm32_gpio.h" + + +/* TODO STM32F7_SDMMC2 + */ + +#ifdef CONFIG_STM32F7_SDMMC1 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ +/* Required system configuration options: + * + * CONFIG_ARCH_DMA - Enable architecture-specific DMA subsystem + * initialization. Required if CONFIG_SDIO_DMA is enabled. + * CONFIG_STM32F7_DMA2 - Enable STM32 DMA2 support. Required if + * CONFIG_SDIO_DMA is enabled + * CONFIG_SCHED_WORKQUEUE -- Callback support requires work queue support. + * + * Driver-specific configuration options: + * + * CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking + * APIs to manage concurrent accesses on the SDIO bus. This is not + * needed for the simple case of a single SD card, for example. + * CONFIG_SDIO_DMA - Enable SDIO. This is a marginally optional. For + * most usages, SDIO will cause data overruns if used without DMA. + * NOTE the above system DMA configuration options. + * CONFIG_SDIO_WIDTH_D1_ONLY - This may be selected to force the driver + * operate with only a single data line (the default is to use all + * 4 SD data lines). + * CONFIG_SDIO_PRI - SDIO interrupt priority. This setting is not very + * important since interrupt nesting is not currently supported. + * CONFIG_SDM_DMAPRIO - SDIO DMA priority. This can be selecte if + * CONFIG_SDIO_DMA is enabled. + * CONFIG_SDIO_XFRDEBUG - Enables some very low-level debug output + * This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_INFO + */ + +#if defined(CONFIG_SDIO_DMA) && !defined(CONFIG_STM32F7_DMA2) +# warning "CONFIG_SDIO_DMA support requires CONFIG_STM32F7_DMA2" +#endif + +#ifndef CONFIG_SDIO_DMA +# warning "Large Non-DMA transfer may result in RX overrun failures" +#endif + +#ifndef CONFIG_SCHED_WORKQUEUE +# error "Callback support requires CONFIG_SCHED_WORKQUEUE" +#endif + +#ifndef CONFIG_SDIO_PRI +# define CONFIG_SDIO_PRI NVIC_SYSH_PRIORITY_DEFAULT +#endif + +#ifdef CONFIG_SDIO_DMA +# ifndef CONFIG_SDIO_DMAPRIO +# define CONFIG_SDIO_DMAPRIO DMA_SCR_PRIVERYHI +# endif +# if (CONFIG_SDIO_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_SDIO_DMAPRIO" +# endif +#else +# undef CONFIG_SDIO_DMAPRIO +#endif + +#if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_FEATURES) +# undef CONFIG_SDIO_XFRDEBUG +#endif + +/* Friendly CLKCR bit re-definitions ****************************************/ + +#define SDIO_CLKCR_RISINGEDGE (0) +#define SDIO_CLKCR_FALLINGEDGE SDIO_CLKCR_NEGEDGE + +/* Mode dependent settings. These depend on clock devisor settings that must + * be defined in the board-specific board.h header file: SDIO_INIT_CLKDIV, + * SDIO_MMCXFR_CLKDIV, and SDIO_SDXFR_CLKDIV. + */ + +#define STM32_CLCKCR_INIT (SDMMC1_INIT_CLKDIV | SDIO_CLKCR_RISINGEDGE | \ + SDIO_CLKCR_WIDBUS_D1) +#define SDIO_CLKCR_MMCXFR (SDMMC1_MMCXFR_CLKDIV | SDIO_CLKCR_RISINGEDGE | \ + SDIO_CLKCR_WIDBUS_D1) +#define SDIO_CLCKR_SDXFR (SDMMC1_SDXFR_CLKDIV | SDIO_CLKCR_RISINGEDGE | \ + SDIO_CLKCR_WIDBUS_D1) +#define SDIO_CLCKR_SDWIDEXFR (SDMMC1_SDXFR_CLKDIV | SDIO_CLKCR_RISINGEDGE | \ + SDIO_CLKCR_WIDBUS_D4) + +/* Timing */ + +#define SDIO_CMDTIMEOUT (100000) +#define SDIO_LONGTIMEOUT (0x7fffffff) + +/* Big DTIMER setting */ + +#define SDIO_DTIMER_DATATIMEOUT (0x000fffff) + +/* DMA channel/stream configuration register settings. The following + * must be selected. The DMA driver will select the remaining fields. + * + * - 32-bit DMA + * - Memory increment + * - Direction (memory-to-peripheral, peripheral-to-memory) + * - Memory burst size (F4 only) + */ + + +/* STM32 stream configuration register (SCR) settings. */ + +#define SDIO_RXDMA32_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_P2M|DMA_SCR_MINC | \ + DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \ + CONFIG_SDIO_DMAPRIO | DMA_SCR_PBURST_INCR4 | \ + DMA_SCR_MBURST_INCR4) +#define SDIO_TXDMA32_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_M2P | DMA_SCR_MINC | \ + DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \ + CONFIG_SDIO_DMAPRIO | DMA_SCR_PBURST_INCR4 | \ + DMA_SCR_MBURST_INCR4) + +/* SDIO DMA Channel/Stream selection. There + * are multiple DMA stream options that must be dis-ambiguated in the board.h + * file. + */ + +#define SDIO_DMACHAN DMAMAP_SDMMC1 + +/* FIFO sizes */ + +#define SDIO_HALFFIFO_WORDS (8) +#define SDIO_HALFFIFO_BYTES (8*4) + +/* Data transfer interrupt mask bits */ + +#define SDIO_RECV_MASK (SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | \ + SDIO_MASK_DATAENDIE | SDIO_MASK_RXOVERRIE | \ + SDIO_MASK_RXFIFOHFIE | SDIO_MASK_STBITERRIE) +#define SDIO_SEND_MASK (SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | \ + SDIO_MASK_DATAENDIE | SDIO_MASK_TXUNDERRIE | \ + SDIO_MASK_TXFIFOHEIE | SDIO_MASK_STBITERRIE) +#define SDIO_DMARECV_MASK (SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | \ + SDIO_MASK_DATAENDIE | SDIO_MASK_RXOVERRIE | \ + SDIO_MASK_STBITERRIE) +#define SDIO_DMASEND_MASK (SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | \ + SDIO_MASK_DATAENDIE | SDIO_MASK_TXUNDERRIE | \ + SDIO_MASK_STBITERRIE) + +/* Event waiting interrupt mask bits */ + +#define SDIO_CMDDONE_STA (SDIO_STA_CMDSENT) +#define SDIO_RESPDONE_STA (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL | \ + SDIO_STA_CMDREND) +#define SDIO_XFRDONE_STA (0) + +#define SDIO_CMDDONE_MASK (SDIO_MASK_CMDSENTIE) +#define SDIO_RESPDONE_MASK (SDIO_MASK_CCRCFAILIE | SDIO_MASK_CTIMEOUTIE | \ + SDIO_MASK_CMDRENDIE) +#define SDIO_XFRDONE_MASK (0) + +#define SDIO_CMDDONE_ICR (SDIO_ICR_CMDSENTC | SDIO_ICR_DBCKENDC) +#define SDIO_RESPDONE_ICR (SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC | \ + SDIO_ICR_CMDRENDC | SDIO_ICR_DBCKENDC) +#define SDIO_XFRDONE_ICR (SDIO_ICR_DATAENDC | SDIO_ICR_DCRCFAILC | \ + SDIO_ICR_DTIMEOUTC | SDIO_ICR_RXOVERRC | \ + SDIO_ICR_TXUNDERRC | SDIO_ICR_STBITERRC | \ + SDIO_ICR_DBCKENDC) + +#define SDIO_WAITALL_ICR (SDIO_CMDDONE_ICR | SDIO_RESPDONE_ICR | \ + SDIO_XFRDONE_ICR | SDIO_ICR_DBCKENDC) + +/* Let's wait until we have both SDIO transfer complete and DMA complete. */ + +#define SDIO_XFRDONE_FLAG (1) +#define SDIO_DMADONE_FLAG (2) +#define SDIO_ALLDONE (3) + +/* Register logging support */ + +#ifdef CONFIG_SDIO_XFRDEBUG +# ifdef CONFIG_SDIO_DMA +# define SAMPLENDX_BEFORE_SETUP 0 +# define SAMPLENDX_BEFORE_ENABLE 1 +# define SAMPLENDX_AFTER_SETUP 2 +# define SAMPLENDX_END_TRANSFER 3 +# define SAMPLENDX_DMA_CALLBACK 4 +# define DEBUG_NSAMPLES 5 +# else +# define SAMPLENDX_BEFORE_SETUP 0 +# define SAMPLENDX_AFTER_SETUP 1 +# define SAMPLENDX_END_TRANSFER 2 +# define DEBUG_NSAMPLES 3 +# endif +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure defines the state of the STM32 SDIO interface */ + +struct stm32_dev_s +{ + struct sdio_dev_s dev; /* Standard, base SDIO interface */ + + /* STM32-specific extensions */ + /* Event support */ + + sem_t waitsem; /* Implements event waiting */ + sdio_eventset_t waitevents; /* Set of events to be waited for */ + uint32_t waitmask; /* Interrupt enables for event waiting */ + volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */ + WDOG_ID waitwdog; /* Watchdog that handles event timeouts */ + + /* Callback support */ + + uint8_t cdstatus; /* Card status */ + sdio_eventset_t cbevents; /* Set of events to be cause callbacks */ + worker_t callback; /* Registered callback function */ + void *cbarg; /* Registered callback argument */ + struct work_s cbwork; /* Callback work queue structure */ + + /* Interrupt mode data transfer support */ + + uint32_t *buffer; /* Address of current R/W buffer */ + size_t remaining; /* Number of bytes remaining in the transfer */ + uint32_t xfrmask; /* Interrupt enables for data transfer */ + + /* DMA data transfer support */ + + bool widebus; /* Required for DMA support */ +#ifdef CONFIG_SDIO_DMA + volatile uint8_t xfrflags; /* Used to synchronize SDIO and DMA completion events */ + bool dmamode; /* true: DMA mode transfer */ + DMA_HANDLE dma; /* Handle for DMA channel */ +#endif +}; + +/* Register logging support */ + +#ifdef CONFIG_SDIO_XFRDEBUG +struct stm32_sdioregs_s +{ + uint8_t power; + uint16_t clkcr; + uint16_t dctrl; + uint32_t dtimer; + uint32_t dlen; + uint32_t dcount; + uint32_t sta; + uint32_t mask; + uint32_t fifocnt; +}; + +struct stm32_sampleregs_s +{ + struct stm32_sdioregs_s sdio; +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA) + struct stm32_dmaregs_s dma; +#endif +}; +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Low-level helpers ********************************************************/ + +static void stm32_takesem(struct stm32_dev_s *priv); +#define stm32_givesem(priv) (sem_post(&priv->waitsem)) +static inline void stm32_setclkcr(uint32_t clkcr); +static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, + sdio_eventset_t waitevents, sdio_eventset_t wkupevents); +static void stm32_configxfrints(struct stm32_dev_s *priv, uint32_t xfrmask); +static void stm32_setpwrctrl(uint32_t pwrctrl); +static inline uint32_t stm32_getpwrctrl(void); + +/* DMA Helpers **************************************************************/ + +#ifdef CONFIG_SDIO_XFRDEBUG +static void stm32_sampleinit(void); +static void stm32_sdiosample(struct stm32_sdioregs_s *regs); +static void stm32_sample(struct stm32_dev_s *priv, int index); +static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg); +static void stm32_dumpsample(struct stm32_dev_s *priv, + struct stm32_sampleregs_s *regs, const char *msg); +static void stm32_dumpsamples(struct stm32_dev_s *priv); +#else +# define stm32_sampleinit() +# define stm32_sample(priv,index) +# define stm32_dumpsamples(priv) +#endif + +#ifdef CONFIG_SDIO_DMA +static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg); +#endif + +/* Data Transfer Helpers ****************************************************/ + +static uint8_t stm32_log2(uint16_t value); +static void stm32_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl); +static void stm32_datadisable(void); +static void stm32_sendfifo(struct stm32_dev_s *priv); +static void stm32_recvfifo(struct stm32_dev_s *priv); +static void stm32_eventtimeout(int argc, uint32_t arg); +static void stm32_endwait(struct stm32_dev_s *priv, sdio_eventset_t wkupevent); +static void stm32_endtransfer(struct stm32_dev_s *priv, sdio_eventset_t wkupevent); + +/* Interrupt Handling *******************************************************/ + +static int stm32_interrupt(int irq, void *context); +#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE +static int stm32_rdyinterrupt(int irq, void *context); +#endif + +/* SDIO interface methods ***************************************************/ + +/* Mutual exclusion */ + +#ifdef CONFIG_SDIO_MUXBUS +static int stm32_lock(FAR struct sdio_dev_s *dev, bool lock); +#endif + +/* Initialization/setup */ + +static void stm32_reset(FAR struct sdio_dev_s *dev); +static uint8_t stm32_status(FAR struct sdio_dev_s *dev); +static void stm32_widebus(FAR struct sdio_dev_s *dev, bool enable); +static void stm32_clock(FAR struct sdio_dev_s *dev, + enum sdio_clock_e rate); +static int stm32_attach(FAR struct sdio_dev_s *dev); + +/* Command/Status/Data Transfer */ + +static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t arg); +static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, + size_t nbytes); +static int stm32_sendsetup(FAR struct sdio_dev_s *dev, + FAR const uint8_t *buffer, uint32_t nbytes); +static int stm32_cancel(FAR struct sdio_dev_s *dev); + +static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd); +static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rshort); +static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t rlong[4]); +static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rshort); +static int stm32_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rnotimpl); + +/* EVENT handler */ + +static void stm32_waitenable(FAR struct sdio_dev_s *dev, + sdio_eventset_t eventset); +static sdio_eventset_t + stm32_eventwait(FAR struct sdio_dev_s *dev, uint32_t timeout); +static void stm32_callbackenable(FAR struct sdio_dev_s *dev, + sdio_eventset_t eventset); +static int stm32_registercallback(FAR struct sdio_dev_s *dev, + worker_t callback, void *arg); + +/* DMA */ + +#ifdef CONFIG_SDIO_DMA +static bool stm32_dmasupported(FAR struct sdio_dev_s *dev); +#ifdef CONFIG_SDIO_PREFLIGHT +static int stm32_dmapreflight(FAR struct sdio_dev_s *dev, + FAR const uint8_t *buffer, size_t buflen); +#endif +static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, + FAR uint8_t *buffer, size_t buflen); +static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, + FAR const uint8_t *buffer, size_t buflen); +#endif + +/* Initialization/uninitialization/reset ************************************/ + +static void stm32_callback(void *arg); +static void stm32_default(void); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct stm32_dev_s g_sdiodev = +{ + .dev = + { +#ifdef CONFIG_SDIO_MUXBUS + .lock = stm32_lock, +#endif + .reset = stm32_reset, + .status = stm32_status, + .widebus = stm32_widebus, + .clock = stm32_clock, + .attach = stm32_attach, + .sendcmd = stm32_sendcmd, +#ifdef CONFIG_SDIO_BLOCKSETUP + .blocksetup = stm32_blocksetup, /* Not implemented yet */ +#endif + .recvsetup = stm32_recvsetup, + .sendsetup = stm32_sendsetup, + .cancel = stm32_cancel, + .waitresponse = stm32_waitresponse, + .recvR1 = stm32_recvshortcrc, + .recvR2 = stm32_recvlong, + .recvR3 = stm32_recvshort, + .recvR4 = stm32_recvnotimpl, + .recvR5 = stm32_recvnotimpl, + .recvR6 = stm32_recvshortcrc, + .recvR7 = stm32_recvshort, + .waitenable = stm32_waitenable, + .eventwait = stm32_eventwait, + .callbackenable = stm32_callbackenable, + .registercallback = stm32_registercallback, +#ifdef CONFIG_SDIO_DMA + .dmasupported = stm32_dmasupported, +#ifdef CONFIG_SDIO_PREFLIGHT + .dmapreflight = stm32_dmapreflight, +#endif + .dmarecvsetup = stm32_dmarecvsetup, + .dmasendsetup = stm32_dmasendsetup, +#endif + }, +}; + +/* Register logging support */ + +#ifdef CONFIG_SDIO_XFRDEBUG +static struct stm32_sampleregs_s g_sampleregs[DEBUG_NSAMPLES]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Low-level Helpers + ****************************************************************************/ +/**************************************************************************** + * Name: stm32_takesem + * + * Description: + * Take the wait semaphore (handling false alarm wakeups due to the receipt + * of signals). + * + * Input Parameters: + * dev - Instance of the SDIO device driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_takesem(struct stm32_dev_s *priv) +{ + /* Take the semaphore (perhaps waiting) */ + + while (sem_wait(&priv->waitsem) != 0) + { + /* The only case that an error should occr here is if the wait was + * awakened by a signal. + */ + + ASSERT(errno == EINTR); + } +} + +/**************************************************************************** + * Name: stm32_setclkcr + * + * Description: + * Modify oft-changed bits in the CLKCR register. Only the following bit- + * fields are changed: + * + * CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, and HWFC_EN + * + * Input Parameters: + * clkcr - A new CLKCR setting for the above mentions bits (other bits + * are ignored. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void stm32_setclkcr(uint32_t clkcr) +{ + uint32_t regval = getreg32(STM32_SDMMC1_CLKCR); + + /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ + + regval &= ~(SDIO_CLKCR_CLKDIV_MASK | SDIO_CLKCR_PWRSAV | SDIO_CLKCR_BYPASS | + SDIO_CLKCR_WIDBUS_MASK | SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN | + SDIO_CLKCR_CLKEN); + + /* Replace with user provided settings */ + + clkcr &= (SDIO_CLKCR_CLKDIV_MASK | SDIO_CLKCR_PWRSAV | SDIO_CLKCR_BYPASS | + SDIO_CLKCR_WIDBUS_MASK | SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN | + SDIO_CLKCR_CLKEN); + + regval |= clkcr; + putreg32(regval, STM32_SDMMC1_CLKCR); + + finfo("CLKCR: %08x PWR: %08x\n", + getreg32(STM32_SDMMC1_CLKCR), getreg32(STM32_SDMMC1_POWER)); +} + +/**************************************************************************** + * Name: stm32_configwaitints + * + * Description: + * Enable/disable SDIO interrupts needed to suport the wait function + * + * Input Parameters: + * priv - A reference to the SDIO device state structure + * waitmask - The set of bits in the SDIO MASK register to set + * waitevents - Waited for events + * wkupevent - Wake-up events + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, + sdio_eventset_t waitevents, + sdio_eventset_t wkupevent) +{ + irqstate_t flags; +#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE + int pinset; +#endif + + /* Save all of the data and set the new interrupt mask in one, atomic + * operation. + */ + flags = enter_critical_section(); + +#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE + if ((waitmask & SDIOWAIT_WRCOMPLETE) != 0) + { + /* Do not use this in STM32_SDMMC1_MASK register */ + + waitmask &= !SDIOWAIT_WRCOMPLETE; + + pinset = GPIO_SDMMC1_D0 & (GPIO_PORT_MASK | GPIO_PIN_MASK); + pinset |= (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI); + + /* Arm the SDIO_D Ready and install Isr */ + + stm32_gpiosetevent(pinset, true, false, false, stm32_rdyinterrupt); + } + + /* Disarm SDIO_D ready */ + + if ((wkupevent & SDIOWAIT_WRCOMPLETE) != 0) + { + stm32_gpiosetevent(GPIO_SDMMC1_D0, false, false, false , NULL); + stm32_configgpio(GPIO_SDMMC1_D0); + } +#endif + + priv->waitevents = waitevents; + priv->wkupevent = wkupevent; + priv->waitmask = waitmask; +#ifdef CONFIG_SDIO_DMA + priv->xfrflags = 0; +#endif + putreg32(priv->xfrmask | priv->waitmask, STM32_SDMMC1_MASK); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: stm32_configxfrints + * + * Description: + * Enable SDIO interrupts needed to support the data transfer event + * + * Input Parameters: + * priv - A reference to the SDIO device state structure + * xfrmask - The set of bits in the SDIO MASK register to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_configxfrints(struct stm32_dev_s *priv, uint32_t xfrmask) +{ + irqstate_t flags; + flags = enter_critical_section(); + priv->xfrmask = xfrmask; + putreg32(priv->xfrmask | priv->waitmask, STM32_SDMMC1_MASK); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: stm32_setpwrctrl + * + * Description: + * Change the PWRCTRL field of the SDIO POWER register to turn the SDIO + * ON or OFF + * + * Input Parameters: + * clkcr - A new PWRCTRL setting + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_setpwrctrl(uint32_t pwrctrl) +{ + uint32_t regval; + + regval = getreg32(STM32_SDMMC1_POWER); + regval &= ~SDIO_POWER_PWRCTRL_MASK; + regval |= pwrctrl; + putreg32(regval, STM32_SDMMC1_POWER); +} + +/**************************************************************************** + * Name: stm32_getpwrctrl + * + * Description: + * Return the current value of the the PWRCTRL field of the SDIO POWER + * register. This function can be used to see if the SDIO is powered ON + * or OFF + * + * Input Parameters: + * None + * + * Returned Value: + * The current value of the the PWRCTRL field of the SDIO POWER register. + * + ****************************************************************************/ + +static inline uint32_t stm32_getpwrctrl(void) +{ + return getreg32(STM32_SDMMC1_POWER) & SDIO_POWER_PWRCTRL_MASK; +} + +/**************************************************************************** + * DMA Helpers + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sampleinit + * + * Description: + * Setup prior to collecting DMA samples + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_XFRDEBUG +static void stm32_sampleinit(void) +{ + memset(g_sampleregs, 0xff, DEBUG_NSAMPLES * sizeof(struct stm32_sampleregs_s)); +} +#endif + +/**************************************************************************** + * Name: stm32_sdiosample + * + * Description: + * Sample SDIO registers + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_XFRDEBUG +static void stm32_sdiosample(struct stm32_sdioregs_s *regs) +{ + regs->power = (uint8_t)getreg32(STM32_SDMMC1_POWER); + regs->clkcr = (uint16_t)getreg32(STM32_SDMMC1_CLKCR); + regs->dctrl = (uint16_t)getreg32(STM32_SDMMC1_DCTRL); + regs->dtimer = getreg32(STM32_SDMMC1_DTIMER); + regs->dlen = getreg32(STM32_SDMMC1_DLEN); + regs->dcount = getreg32(STM32_SDMMC1_DCOUNT); + regs->sta = getreg32(STM32_SDMMC1_STA); + regs->mask = getreg32(STM32_SDMMC1_MASK); + regs->fifocnt = getreg32(STM32_SDMMC1_FIFOCNT); +} +#endif + +/**************************************************************************** + * Name: stm32_sample + * + * Description: + * Sample SDIO/DMA registers + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_XFRDEBUG +static void stm32_sample(struct stm32_dev_s *priv, int index) +{ + struct stm32_sampleregs_s *regs = &g_sampleregs[index]; + +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA) + if (priv->dmamode) + { + stm32_dmasample(priv->dma, ®s->dma); + } +#endif + + stm32_sdiosample(®s->sdio); +} +#endif + +/**************************************************************************** + * Name: stm32_sdiodump + * + * Description: + * Dump one register sample + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_XFRDEBUG +static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) +{ + ferr("SDIO Registers: %s\n", msg); + ferr(" POWER[%08x]: %08x\n", STM32_SDMMC1_POWER, regs->power); + ferr(" CLKCR[%08x]: %08x\n", STM32_SDMMC1_CLKCR, regs->clkcr); + ferr(" DCTRL[%08x]: %08x\n", STM32_SDMMC1_DCTRL, regs->dctrl); + ferr(" DTIMER[%08x]: %08x\n", STM32_SDMMC1_DTIMER, regs->dtimer); + ferr(" DLEN[%08x]: %08x\n", STM32_SDMMC1_DLEN, regs->dlen); + ferr(" DCOUNT[%08x]: %08x\n", STM32_SDMMC1_DCOUNT, regs->dcount); + ferr(" STA[%08x]: %08x\n", STM32_SDMMC1_STA, regs->sta); + ferr(" MASK[%08x]: %08x\n", STM32_SDMMC1_MASK, regs->mask); + ferr("FIFOCNT[%08x]: %08x\n", STM32_SDMMC1_FIFOCNT, regs->fifocnt); +} +#endif + +/**************************************************************************** + * Name: stm32_dumpsample + * + * Description: + * Dump one register sample + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_XFRDEBUG +static void stm32_dumpsample(struct stm32_dev_s *priv, + struct stm32_sampleregs_s *regs, const char *msg) +{ +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA) + if (priv->dmamode) + { + stm32_dmadump(priv->dma, ®s->dma, msg); + } +#endif + + stm32_sdiodump(®s->sdio, msg); +} +#endif + +/**************************************************************************** + * Name: stm32_dumpsamples + * + * Description: + * Dump all sampled register data + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_XFRDEBUG +static void stm32_dumpsamples(struct stm32_dev_s *priv) +{ + stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], "Before setup"); + +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA) + if (priv->dmamode) + { + stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_ENABLE], "Before DMA enable"); + } +#endif + + stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_AFTER_SETUP], "After setup"); + stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_END_TRANSFER], "End of transfer"); + +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA) + if (priv->dmamode) + { + stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_DMA_CALLBACK], "DMA Callback"); + } +#endif +} +#endif + +/**************************************************************************** + * Name: stm32_dmacallback + * + * Description: + * Called when SDIO DMA completes + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_DMA +static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg) +{ + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)arg; + DEBUGASSERT(priv->dmamode); + sdio_eventset_t result; + + /* In the normal case, SDIO appears to handle the End-Of-Transfer interrupt + * first with the End-Of-DMA event occurring significantly later. On + * transfer errors, however, the DMA error will occur before the End-of- + * Transfer. + */ + + stm32_sample((struct stm32_dev_s *)arg, SAMPLENDX_DMA_CALLBACK); + + /* Get the result of the DMA transfer */ + + if ((status & DMA_STATUS_ERROR) != 0) + { + fllerr("DMA error %02x, remaining: %d\n", status, priv->remaining); + result = SDIOWAIT_ERROR; + } + else + { + result = SDIOWAIT_TRANSFERDONE; + } + + /* Then terminate the transfer if this completes all of the steps in the + * transfer OR if a DMA error occurred. In the non-error case, we should + * already have the SDIO transfer done interrupt. If not, the transfer + * will appropriately time out. + */ + + priv->xfrflags |= SDIO_DMADONE_FLAG; + if (priv->xfrflags == SDIO_ALLDONE || result == SDIOWAIT_ERROR) + { + stm32_endtransfer(priv, result); + } +} +#endif + +/**************************************************************************** + * Data Transfer Helpers + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_log2 + * + * Description: + * Take (approximate) log base 2 of the provided number (Only works if the + * provided number is a power of 2). + * + ****************************************************************************/ + +static uint8_t stm32_log2(uint16_t value) +{ + uint8_t log2 = 0; + + /* 0000 0000 0000 0001 -> return 0, + * 0000 0000 0000 001x -> return 1, + * 0000 0000 0000 01xx -> return 2, + * 0000 0000 0000 1xxx -> return 3, + * ... + * 1xxx xxxx xxxx xxxx -> return 15, + */ + + DEBUGASSERT(value > 0); + while (value != 1) + { + value >>= 1; + log2++; + } + + return log2; +} + +/**************************************************************************** + * Name: stm32_dataconfig + * + * Description: + * Configure the SDIO data path for the next data transfer + * + ****************************************************************************/ + +static void stm32_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl) +{ + uint32_t regval = 0; + + /* Enable data path */ + + putreg32(timeout, STM32_SDMMC1_DTIMER); /* Set DTIMER */ + putreg32(dlen, STM32_SDMMC1_DLEN); /* Set DLEN */ + + /* Configure DCTRL DTDIR, DTMODE, and DBLOCKSIZE fields and set the DTEN + * field + */ + + regval = getreg32(STM32_SDMMC1_DCTRL); + regval &= ~(SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE_MASK); + dctrl &= (SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE_MASK); + regval |= (dctrl | SDIO_DCTRL_DTEN); + putreg32(regval, STM32_SDMMC1_DCTRL); +} + +/**************************************************************************** + * Name: stm32_datadisable + * + * Description: + * Disable the SDIO data path setup by stm32_dataconfig() and + * disable DMA. + * + ****************************************************************************/ + +static void stm32_datadisable(void) +{ + uint32_t regval; + + /* Disable the data path */ + + putreg32(SDIO_DTIMER_DATATIMEOUT, STM32_SDMMC1_DTIMER); /* Reset DTIMER */ + putreg32(0, STM32_SDMMC1_DLEN); /* Reset DLEN */ + + /* Reset DCTRL DTEN, DTDIR, DTMODE, DMAEN, and DBLOCKSIZE fields */ + + regval = getreg32(STM32_SDMMC1_DCTRL); + regval &= ~(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTMODE | + SDIO_DCTRL_DMAEN | SDIO_DCTRL_DBLOCKSIZE_MASK); + putreg32(regval, STM32_SDMMC1_DCTRL); +} + +/**************************************************************************** + * Name: stm32_sendfifo + * + * Description: + * Send SDIO data in interrupt mode + * + * Input Parameters: + * priv - An instance of the SDIO device interface + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_sendfifo(struct stm32_dev_s *priv) +{ + union + { + uint32_t w; + uint8_t b[4]; + } data; + + /* Loop while there is more data to be sent and the RX FIFO is not full */ + + while (priv->remaining > 0 && + (getreg32(STM32_SDMMC1_STA) & SDIO_STA_TXFIFOF) == 0) + { + /* Is there a full word remaining in the user buffer? */ + + if (priv->remaining >= sizeof(uint32_t)) + { + /* Yes, transfer the word to the TX FIFO */ + + data.w = *priv->buffer++; + priv->remaining -= sizeof(uint32_t); + } + else + { + /* No.. transfer just the bytes remaining in the user buffer, + * padding with zero as necessary to extend to a full word. + */ + + uint8_t *ptr = (uint8_t *)priv->remaining; + int i; + + data.w = 0; + for (i = 0; i < (int)priv->remaining; i++) + { + data.b[i] = *ptr++; + } + + /* Now the transfer is finished */ + + priv->remaining = 0; + } + + /* Put the word in the FIFO */ + + putreg32(data.w, STM32_SDMMC1_FIFO); + } +} + +/**************************************************************************** + * Name: stm32_recvfifo + * + * Description: + * Receive SDIO data in interrupt mode + * + * Input Parameters: + * priv - An instance of the SDIO device interface + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_recvfifo(struct stm32_dev_s *priv) +{ + union + { + uint32_t w; + uint8_t b[4]; + } data; + + /* Loop while there is space to store the data and there is more + * data available in the RX FIFO. + */ + + while (priv->remaining > 0 && + (getreg32(STM32_SDMMC1_STA) & SDIO_STA_RXDAVL) != 0) + { + /* Read the next word from the RX FIFO */ + + data.w = getreg32(STM32_SDMMC1_FIFO); + if (priv->remaining >= sizeof(uint32_t)) + { + /* Transfer the whole word to the user buffer */ + + *priv->buffer++ = data.w; + priv->remaining -= sizeof(uint32_t); + } + else + { + /* Transfer any trailing fractional word */ + + uint8_t *ptr = (uint8_t *)priv->buffer; + int i; + + for (i = 0; i < (int)priv->remaining; i++) + { + *ptr++ = data.b[i]; + } + + /* Now the transfer is finished */ + + priv->remaining = 0; + } + } +} + +/**************************************************************************** + * Name: stm32_eventtimeout + * + * Description: + * The watchdog timeout setup when the event wait start has expired without + * any other waited-for event occurring. + * + * Input Parameters: + * argc - The number of arguments (should be 1) + * arg - The argument (state structure reference cast to uint32_t) + * + * Returned Value: + * None + * + * Assumptions: + * Always called from the interrupt level with interrupts disabled. + * + ****************************************************************************/ + +static void stm32_eventtimeout(int argc, uint32_t arg) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; + + /* There is always race conditions with timer expirations. */ + + DEBUGASSERT((priv->waitevents & SDIOWAIT_TIMEOUT) != 0 || priv->wkupevent != 0); + + /* Is a data transfer complete event expected? */ + + if ((priv->waitevents & SDIOWAIT_TIMEOUT) != 0) + { + /* Yes.. wake up any waiting threads */ + + stm32_endwait(priv, SDIOWAIT_TIMEOUT); + fllerr("Timeout: remaining: %d\n", priv->remaining); + } +} + +/**************************************************************************** + * Name: stm32_endwait + * + * Description: + * Wake up a waiting thread if the waited-for event has occurred. + * + * Input Parameters: + * priv - An instance of the SDIO device interface + * wkupevent - The event that caused the wait to end + * + * Returned Value: + * None + * + * Assumptions: + * Always called from the interrupt level with interrupts disabled. + * + ****************************************************************************/ + +static void stm32_endwait(struct stm32_dev_s *priv, sdio_eventset_t wkupevent) +{ + /* Cancel the watchdog timeout */ + + (void)wd_cancel(priv->waitwdog); + + /* Disable event-related interrupts */ + + stm32_configwaitints(priv, 0, 0, wkupevent); + + /* Wake up the waiting thread */ + + stm32_givesem(priv); +} + +/**************************************************************************** + * Name: stm32_endtransfer + * + * Description: + * Terminate a transfer with the provided status. This function is called + * only from the SDIO interrupt handler when end-of-transfer conditions + * are detected. + * + * Input Parameters: + * priv - An instance of the SDIO device interface + * wkupevent - The event that caused the transfer to end + * + * Returned Value: + * None + * + * Assumptions: + * Always called from the interrupt level with interrupts disabled. + * + ****************************************************************************/ + +static void stm32_endtransfer(struct stm32_dev_s *priv, sdio_eventset_t wkupevent) +{ + /* Disable all transfer related interrupts */ + + stm32_configxfrints(priv, 0); + + /* Clearing pending interrupt status on all transfer related interrupts */ + + putreg32(SDIO_XFRDONE_ICR, STM32_SDMMC1_ICR); + + /* If this was a DMA transfer, make sure that DMA is stopped */ + +#ifdef CONFIG_SDIO_DMA + if (priv->dmamode) + { + /* DMA debug instrumentation */ + + stm32_sample(priv, SAMPLENDX_END_TRANSFER); + + /* Make sure that the DMA is stopped (it will be stopped automatically + * on normal transfers, but not necessarily when the transfer terminates + * on an error condition). + */ + + stm32_dmastop(priv->dma); + } +#endif + + /* Mark the transfer finished */ + + priv->remaining = 0; + + /* Is a thread wait for these data transfer complete events? */ + + if ((priv->waitevents & wkupevent) != 0) + { + /* Yes.. wake up any waiting threads */ + + stm32_endwait(priv, wkupevent); + } +} + +/**************************************************************************** + * Interrupt Handling + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rdyinterrupt + * + * Description: + * SDIO ready interrupt handler + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE +static int stm32_rdyinterrupt(int irq, void *context) +{ + struct stm32_dev_s *priv = &g_sdiodev; + stm32_endwait(priv, SDIOWAIT_WRCOMPLETE); + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_interrupt + * + * Description: + * SDIO interrupt handler + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int stm32_interrupt(int irq, void *context) +{ + struct stm32_dev_s *priv = &g_sdiodev; + uint32_t enabled; + uint32_t pending; + + /* Loop while there are pending interrupts. Check the SDIO status + * register. Mask out all bits that don't correspond to enabled + * interrupts. (This depends on the fact that bits are ordered + * the same in both the STA and MASK register). If there are non-zero + * bits remaining, then we have work to do here. + */ + + while ((enabled = getreg32(STM32_SDMMC1_STA) & getreg32(STM32_SDMMC1_MASK)) != 0) + { + /* Handle in progress, interrupt driven data transfers ****************/ + + pending = enabled & priv->xfrmask; + if (pending != 0) + { +#ifdef CONFIG_SDIO_DMA + if (!priv->dmamode) +#endif + { + /* Is the RX FIFO half full or more? Is so then we must be + * processing a receive transaction. + */ + + if ((pending & SDIO_STA_RXFIFOHF) != 0) + { + /* Receive data from the RX FIFO */ + + stm32_recvfifo(priv); + } + + /* Otherwise, Is the transmit FIFO half empty or less? If so we must + * be processing a send transaction. NOTE: We can't be processing + * both! + */ + + else if ((pending & SDIO_STA_TXFIFOHE) != 0) + { + /* Send data via the TX FIFO */ + + stm32_sendfifo(priv); + } + } + + /* Handle data end events */ + + if ((pending & SDIO_STA_DATAEND) != 0) + { + /* Handle any data remaining the RX FIFO. If the RX FIFO is + * less than half full at the end of the transfer, then no + * half-full interrupt will be received. + */ + + /* Was this transfer performed in DMA mode? */ + +#ifdef CONFIG_SDIO_DMA + if (priv->dmamode) + { + /* Yes.. Terminate the transfers only if the DMA has also + * finished. + */ + + priv->xfrflags |= SDIO_XFRDONE_FLAG; + if (priv->xfrflags == SDIO_ALLDONE) + { + stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE); + } + + /* Otherwise, just disable futher transfer interrupts and + * wait for the DMA complete event. + */ + + else + { + stm32_configxfrints(priv, 0); + } + } + else +#endif + { + /* Receive data from the RX FIFO */ + + stm32_recvfifo(priv); + + /* Then terminate the transfer */ + + stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE); + } + } + + /* Handle data block send/receive CRC failure */ + + else if ((pending & SDIO_STA_DCRCFAIL) != 0) + { + /* Terminate the transfer with an error */ + + fllerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining); + stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + } + + /* Handle data timeout error */ + + else if ((pending & SDIO_STA_DTIMEOUT) != 0) + { + /* Terminate the transfer with an error */ + + fllerr("ERROR: Data timeout, remaining: %d\n", priv->remaining); + stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT); + } + + /* Handle RX FIFO overrun error */ + + else if ((pending & SDIO_STA_RXOVERR) != 0) + { + /* Terminate the transfer with an error */ + + fllerr("ERROR: RX FIFO overrun, remaining: %d\n", priv->remaining); + stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + } + + /* Handle TX FIFO underrun error */ + + else if ((pending & SDIO_STA_TXUNDERR) != 0) + { + /* Terminate the transfer with an error */ + + fllerr("ERROR: TX FIFO underrun, remaining: %d\n", priv->remaining); + stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + } + + /* Handle start bit error */ + + else if ((pending & SDIO_STA_STBITERR) != 0) + { + /* Terminate the transfer with an error */ + + fllerr("ERROR: Start bit, remaining: %d\n", priv->remaining); + stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + } + } + + /* Handle wait events *************************************************/ + + pending = enabled & priv->waitmask; + if (pending != 0) + { + /* Is this a response completion event? */ + + if ((pending & SDIO_RESPDONE_STA) != 0) + { + /* Yes.. Is their a thread waiting for response done? */ + + if ((priv->waitevents & SDIOWAIT_RESPONSEDONE) != 0) + { + /* Yes.. wake the thread up */ + + putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDMMC1_ICR); + stm32_endwait(priv, SDIOWAIT_RESPONSEDONE); + } + } + + /* Is this a command completion event? */ + + if ((pending & SDIO_CMDDONE_STA) != 0) + { + /* Yes.. Is their a thread waiting for command done? */ + + if ((priv->waitevents & SDIOWAIT_RESPONSEDONE) != 0) + { + /* Yes.. wake the thread up */ + + putreg32(SDIO_CMDDONE_ICR, STM32_SDMMC1_ICR); + stm32_endwait(priv, SDIOWAIT_CMDDONE); + } + } + } + } + + return OK; +} + +/**************************************************************************** + * SDIO Interface Methods + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_lock + * + * Description: + * Locks the bus. Function calls low-level multiplexed bus routines to + * resolve bus requests and acknowledgment issues. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * lock - TRUE to lock, FALSE to unlock. + * + * Returned Value: + * OK on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_MUXBUS +static int stm32_lock(FAR struct sdio_dev_s *dev, bool lock) +{ + /* Single SDIO instance so there is only one possibility. The multiplex + * bus is part of board support package. + */ + + stm32_muxbus_sdio_lock(lock); + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_reset + * + * Description: + * Reset the SDIO controller. Undo all setup and initialization. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_reset(FAR struct sdio_dev_s *dev) +{ + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev; + irqstate_t flags; + + /* Disable clocking */ + + flags = enter_critical_section(); + stm32_setpwrctrl(SDIO_POWER_PWRCTRL_OFF); + + /* Put SDIO registers in their default, reset state */ + + stm32_default(); + + /* Reset data */ + + priv->waitevents = 0; /* Set of events to be waited for */ + priv->waitmask = 0; /* Interrupt enables for event waiting */ + priv->wkupevent = 0; /* The event that caused the wakeup */ +#ifdef CONFIG_SDIO_DMA + priv->xfrflags = 0; /* Used to synchronize SDIO and DMA completion events */ +#endif + + wd_cancel(priv->waitwdog); /* Cancel any timeouts */ + + /* Interrupt mode data transfer support */ + + priv->buffer = 0; /* Address of current R/W buffer */ + priv->remaining = 0; /* Number of bytes remaining in the transfer */ + priv->xfrmask = 0; /* Interrupt enables for data transfer */ + + /* DMA data transfer support */ + + priv->widebus = false; /* Required for DMA support */ +#ifdef CONFIG_SDIO_DMA + priv->dmamode = false; /* true: DMA mode transfer */ +#endif + + /* Configure the SDIO peripheral */ + + stm32_setclkcr(STM32_CLCKCR_INIT | SDIO_CLKCR_CLKEN); + stm32_setpwrctrl(SDIO_POWER_PWRCTRL_ON); + leave_critical_section(flags); + + finfo("CLCKR: %08x POWER: %08x\n", + getreg32(STM32_SDMMC1_CLKCR), getreg32(STM32_SDMMC1_POWER)); +} + +/**************************************************************************** + * Name: stm32_status + * + * Description: + * Get SDIO status. + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * Returns a bitset of status values (see stm32_status_* defines) + * + ****************************************************************************/ + +static uint8_t stm32_status(FAR struct sdio_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + return priv->cdstatus; +} + +/**************************************************************************** + * Name: stm32_widebus + * + * Description: + * Called after change in Bus width has been selected (via ACMD6). Most + * controllers will need to perform some special operations to work + * correctly in the new bus mode. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * wide - true: wide bus (4-bit) bus mode enabled + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_widebus(FAR struct sdio_dev_s *dev, bool wide) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + priv->widebus = wide; +} + +/**************************************************************************** + * Name: stm32_clock + * + * Description: + * Enable/disable SDIO clocking + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * rate - Specifies the clocking to use (see enum sdio_clock_e) + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate) +{ + uint32_t clckr; + + switch (rate) + { + /* Disable clocking (with default ID mode divisor) */ + + default: + case CLOCK_SDIO_DISABLED: + clckr = STM32_CLCKCR_INIT; + return; + + /* Enable in initial ID mode clocking (<400KHz) */ + + case CLOCK_IDMODE: + clckr = (STM32_CLCKCR_INIT | SDIO_CLKCR_CLKEN); + break; + + /* Enable in MMC normal operation clocking */ + + case CLOCK_MMC_TRANSFER: + clckr = (SDIO_CLKCR_MMCXFR | SDIO_CLKCR_CLKEN); + break; + + /* SD normal operation clocking (wide 4-bit mode) */ + + case CLOCK_SD_TRANSFER_4BIT: +#ifndef CONFIG_SDIO_WIDTH_D1_ONLY + clckr = (SDIO_CLCKR_SDWIDEXFR | SDIO_CLKCR_CLKEN); + break; +#endif + + /* SD normal operation clocking (narrow 1-bit mode) */ + + case CLOCK_SD_TRANSFER_1BIT: + clckr = (SDIO_CLCKR_SDXFR | SDIO_CLKCR_CLKEN); + break; + } + + /* Set the new clock frequency along with the clock enable/disable bit */ + + stm32_setclkcr(clckr); +} + +/**************************************************************************** + * Name: stm32_attach + * + * Description: + * Attach and prepare interrupts + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * + * Returned Value: + * OK on success; A negated errno on failure. + * + ****************************************************************************/ + +static int stm32_attach(FAR struct sdio_dev_s *dev) +{ + int ret; + + /* Attach the SDIO interrupt handler */ + + ret = irq_attach(STM32_IRQ_SDMMC1, stm32_interrupt); + if (ret == OK) + { + + /* Disable all interrupts at the SDIO controller and clear static + * interrupt flags + */ + + putreg32(SDIO_MASK_RESET, STM32_SDMMC1_MASK); + putreg32(SDIO_ICR_STATICFLAGS, STM32_SDMMC1_ICR); + + /* Enable SDIO interrupts at the NVIC. They can now be enabled at + * the SDIO controller as needed. + */ + + up_enable_irq(STM32_IRQ_SDMMC1); + +#ifdef CONFIG_ARCH_IRQPRIO + /* Set the interrupt priority */ + + up_prioritize_irq(STM32_IRQ_SDIO, CONFIG_SDIO_PRI); +#endif + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_sendcmd + * + * Description: + * Send the SDIO command + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * cmd - The command to send (32-bits, encoded) + * arg - 32-bit argument required with some commands + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg) +{ + uint32_t regval; + uint32_t cmdidx; + + /* Set the SDIO Argument value */ + + putreg32(arg, STM32_SDMMC1_ARG); + + /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, and CPSMEN bits */ + + regval = getreg32(STM32_SDMMC1_CMD); + regval &= ~(SDIO_CMD_CMDINDEX_MASK | SDIO_CMD_WAITRESP_MASK | + SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND | SDIO_CMD_CPSMEN); + + /* Set WAITRESP bits */ + + switch (cmd & MMCSD_RESPONSE_MASK) + { + case MMCSD_NO_RESPONSE: + regval |= SDIO_CMD_NORESPONSE; + break; + + case MMCSD_R1_RESPONSE: + case MMCSD_R1B_RESPONSE: + case MMCSD_R3_RESPONSE: + case MMCSD_R4_RESPONSE: + case MMCSD_R5_RESPONSE: + case MMCSD_R6_RESPONSE: + case MMCSD_R7_RESPONSE: + regval |= SDIO_CMD_SHORTRESPONSE; + break; + + case MMCSD_R2_RESPONSE: + regval |= SDIO_CMD_LONGRESPONSE; + break; + } + + /* Set CPSMEN and the command index */ + + cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT; + regval |= cmdidx | SDIO_CMD_CPSMEN; + + finfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval); + + /* Write the SDIO CMD */ + + putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDMMC1_ICR); + putreg32(regval, STM32_SDMMC1_CMD); + return OK; +} + +/**************************************************************************** + * Name: stm32_recvsetup + * + * Description: + * Setup hardware in preparation for data transfer from the card in non-DMA + * (interrupt driven mode). This method will do whatever controller setup + * is necessary. This would be called for SD memory just BEFORE sending + * CMD13 (SEND_STATUS), CMD17 (READ_SINGLE_BLOCK), CMD18 + * (READ_MULTIPLE_BLOCKS), ACMD51 (SEND_SCR), etc. Normally, SDIO_WAITEVENT + * will be called to receive the indication that the transfer is complete. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * buffer - Address of the buffer in which to receive the data + * nbytes - The number of bytes in the transfer + * + * Returned Value: + * Number of bytes sent on success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, + size_t nbytes) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + uint32_t dblocksize; + + DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0); + DEBUGASSERT(((uint32_t)buffer & 3) == 0); + + /* Reset the DPSM configuration */ + + stm32_datadisable(); + stm32_sampleinit(); + stm32_sample(priv, SAMPLENDX_BEFORE_SETUP); + + /* Save the destination buffer information for use by the interrupt handler */ + + priv->buffer = (uint32_t *)buffer; + priv->remaining = nbytes; +#ifdef CONFIG_SDIO_DMA + priv->dmamode = false; +#endif + + /* Then set up the SDIO data path */ + + dblocksize = stm32_log2(nbytes) << SDIO_DCTRL_DBLOCKSIZE_SHIFT; + stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, nbytes, dblocksize | SDIO_DCTRL_DTDIR); + + /* And enable interrupts */ + + stm32_configxfrints(priv, SDIO_RECV_MASK); + stm32_sample(priv, SAMPLENDX_AFTER_SETUP); + return OK; +} + +/**************************************************************************** + * Name: stm32_sendsetup + * + * Description: + * Setup hardware in preparation for data transfer from the card. This method + * will do whatever controller setup is necessary. This would be called + * for SD memory just AFTER sending CMD24 (WRITE_BLOCK), CMD25 + * (WRITE_MULTIPLE_BLOCK), ... and before SDIO_SENDDATA is called. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * buffer - Address of the buffer containing the data to send + * nbytes - The number of bytes in the transfer + * + * Returned Value: + * Number of bytes sent on success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, + size_t nbytes) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + uint32_t dblocksize; + + DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0); + DEBUGASSERT(((uint32_t)buffer & 3) == 0); + + /* Reset the DPSM configuration */ + + stm32_datadisable(); + stm32_sampleinit(); + stm32_sample(priv, SAMPLENDX_BEFORE_SETUP); + + /* Save the source buffer information for use by the interrupt handler */ + + priv->buffer = (uint32_t *)buffer; + priv->remaining = nbytes; +#ifdef CONFIG_SDIO_DMA + priv->dmamode = false; +#endif + + /* Then set up the SDIO data path */ + + dblocksize = stm32_log2(nbytes) << SDIO_DCTRL_DBLOCKSIZE_SHIFT; + stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, nbytes, dblocksize); + + /* Enable TX interrupts */ + + stm32_configxfrints(priv, SDIO_SEND_MASK); + stm32_sample(priv, SAMPLENDX_AFTER_SETUP); + return OK; +} + +/**************************************************************************** + * Name: stm32_cancel + * + * Description: + * Cancel the data transfer setup of SDIO_RECVSETUP, SDIO_SENDSETUP, + * SDIO_DMARECVSETUP or SDIO_DMASENDSETUP. This must be called to cancel + * the data transfer setup if, for some reason, you cannot perform the + * transfer. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * + * Returned Value: + * OK is success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32_cancel(FAR struct sdio_dev_s *dev) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + /* Disable all transfer- and event- related interrupts */ + + stm32_configxfrints(priv, 0); + stm32_configwaitints(priv, 0, 0, 0); + + /* Clearing pending interrupt status on all transfer- and event- related + * interrupts + */ + + putreg32(SDIO_WAITALL_ICR, STM32_SDMMC1_ICR); + + /* Cancel any watchdog timeout */ + + (void)wd_cancel(priv->waitwdog); + + /* If this was a DMA transfer, make sure that DMA is stopped */ + +#ifdef CONFIG_SDIO_DMA + if (priv->dmamode) + { + /* Make sure that the DMA is stopped (it will be stopped automatically + * on normal transfers, but not necessarily when the transfer terminates + * on an error condition. + */ + + stm32_dmastop(priv->dma); + } +#endif + + /* Mark no transfer in progress */ + + priv->remaining = 0; + return OK; +} + +/**************************************************************************** + * Name: stm32_waitresponse + * + * Description: + * Poll-wait for the response to the last command to be ready. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * cmd - The command that was sent. See 32-bit command definitions above. + * + * Returned Value: + * OK is success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) +{ + int32_t timeout; + uint32_t events; + + switch (cmd & MMCSD_RESPONSE_MASK) + { + case MMCSD_NO_RESPONSE: + events = SDIO_CMDDONE_STA; + timeout = SDIO_CMDTIMEOUT; + break; + + case MMCSD_R1_RESPONSE: + case MMCSD_R1B_RESPONSE: + case MMCSD_R2_RESPONSE: + case MMCSD_R6_RESPONSE: + events = SDIO_RESPDONE_STA; + timeout = SDIO_LONGTIMEOUT; + break; + + case MMCSD_R4_RESPONSE: + case MMCSD_R5_RESPONSE: + return -ENOSYS; + + case MMCSD_R3_RESPONSE: + case MMCSD_R7_RESPONSE: + events = SDIO_RESPDONE_STA; + timeout = SDIO_CMDTIMEOUT; + break; + + default: + return -EINVAL; + } + + /* Then wait for the response (or timeout) */ + + while ((getreg32(STM32_SDMMC1_STA) & events) == 0) + { + if (--timeout <= 0) + { + ferr("ERROR: Timeout cmd: %08x events: %08x STA: %08x\n", + cmd, events, getreg32(STM32_SDMMC1_STA)); + + return -ETIMEDOUT; + } + } + + putreg32(SDIO_CMDDONE_ICR, STM32_SDMMC1_ICR); + return OK; +} + +/**************************************************************************** + * Name: stm32_recvRx + * + * Description: + * Receive response to SDIO command. Only the critical payload is + * returned -- that is 32 bits for 48 bit status and 128 bits for 136 bit + * status. The driver implementation should verify the correctness of + * the remaining, non-returned bits (CRCs, CMD index, etc.). + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * Rx - Buffer in which to receive the response + * + * Returned Value: + * Number of bytes sent on success; a negated errno on failure. Here a + * failure means only a faiure to obtain the requested reponse (due to + * transport problem -- timeout, CRC, etc.). The implementation only + * assures that the response is returned intacta and does not check errors + * within the response itself. + * + ****************************************************************************/ + +static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort) +{ +#ifdef CONFIG_DEBUG_FEATURES + uint32_t respcmd; +#endif + uint32_t regval; + int ret = OK; + + /* R1 Command response (48-bit) + * 47 0 Start bit + * 46 0 Transmission bit (0=from card) + * 45:40 bit5 - bit0 Command index (0-63) + * 39:8 bit31 - bit0 32-bit card status + * 7:1 bit6 - bit0 CRC7 + * 0 1 End bit + * + * R1b Identical to R1 with the additional busy signaling via the data + * line. + * + * R6 Published RCA Response (48-bit, SD card only) + * 47 0 Start bit + * 46 0 Transmission bit (0=from card) + * 45:40 bit5 - bit0 Command index (0-63) + * 39:8 bit31 - bit0 32-bit Argument Field, consisting of: + * [31:16] New published RCA of card + * [15:0] Card status bits {23,22,19,12:0} + * 7:1 bit6 - bit0 CRC7 + * 0 1 End bit + */ + + +#ifdef CONFIG_DEBUG_FEATURES + if (!rshort) + { + ferr("ERROR: rshort=NULL\n"); + ret = -EINVAL; + } + + /* Check that this is the correct response to this command */ + + else if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1_RESPONSE && + (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1B_RESPONSE && + (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE) + { + ferr("ERROR: Wrong response CMD=%08x\n", cmd); + ret = -EINVAL; + } + else +#endif + { + /* Check if a timeout or CRC error occurred */ + + regval = getreg32(STM32_SDMMC1_STA); + if ((regval & SDIO_STA_CTIMEOUT) != 0) + { + ferr("ERROR: Command timeout: %08x\n", regval); + ret = -ETIMEDOUT; + } + else if ((regval & SDIO_STA_CCRCFAIL) != 0) + { + ferr("ERROR: CRC failure: %08x\n", regval); + ret = -EIO; + } +#ifdef CONFIG_DEBUG_FEATURES + else + { + /* Check response received is of desired command */ + + respcmd = getreg32(STM32_SDMMC1_RESPCMD); + if ((uint8_t)(respcmd & SDIO_RESPCMD_MASK) != (cmd & MMCSD_CMDIDX_MASK)) + { + ferr("ERROR: RESCMD=%02x CMD=%08x\n", respcmd, cmd); + ret = -EINVAL; + } + } +#endif + } + + /* Clear all pending message completion events and return the R1/R6 response */ + + putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDMMC1_ICR); + *rshort = getreg32(STM32_SDMMC1_RESP1); + return ret; +} + +static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong[4]) +{ + uint32_t regval; + int ret = OK; + + /* R2 CID, CSD register (136-bit) + * 135 0 Start bit + * 134 0 Transmission bit (0=from card) + * 133:128 bit5 - bit0 Reserved + * 127:1 bit127 - bit1 127-bit CID or CSD register + * (including internal CRC) + * 0 1 End bit + */ + +#ifdef CONFIG_DEBUG_FEATURES + /* Check that R1 is the correct response to this command */ + + if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE) + { + ferr("ERROR: Wrong response CMD=%08x\n", cmd); + ret = -EINVAL; + } + else +#endif + { + /* Check if a timeout or CRC error occurred */ + + regval = getreg32(STM32_SDMMC1_STA); + if (regval & SDIO_STA_CTIMEOUT) + { + ferr("ERROR: Timeout STA: %08x\n", regval); + ret = -ETIMEDOUT; + } + else if (regval & SDIO_STA_CCRCFAIL) + { + ferr("ERROR: CRC fail STA: %08x\n", regval); + ret = -EIO; + } + } + + /* Return the long response */ + + putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDMMC1_ICR); + if (rlong) + { + rlong[0] = getreg32(STM32_SDMMC1_RESP1); + rlong[1] = getreg32(STM32_SDMMC1_RESP2); + rlong[2] = getreg32(STM32_SDMMC1_RESP3); + rlong[3] = getreg32(STM32_SDMMC1_RESP4); + } + return ret; +} + +static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort) +{ + uint32_t regval; + int ret = OK; + + /* R3 OCR (48-bit) + * 47 0 Start bit + * 46 0 Transmission bit (0=from card) + * 45:40 bit5 - bit0 Reserved + * 39:8 bit31 - bit0 32-bit OCR register + * 7:1 bit6 - bit0 Reserved + * 0 1 End bit + */ + + /* Check that this is the correct response to this command */ + +#ifdef CONFIG_DEBUG_FEATURES + if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE && + (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE) + { + ferr("ERROR: Wrong response CMD=%08x\n", cmd); + ret = -EINVAL; + } + else +#endif + { + /* Check if a timeout occurred (Apparently a CRC error can terminate + * a good response) + */ + + regval = getreg32(STM32_SDMMC1_STA); + if (regval & SDIO_STA_CTIMEOUT) + { + ferr("ERROR: Timeout STA: %08x\n", regval); + ret = -ETIMEDOUT; + } + } + + putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDMMC1_ICR); + if (rshort) + { + *rshort = getreg32(STM32_SDMMC1_RESP1); + } + return ret; +} + +/* MMC responses not supported */ + +static int stm32_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rnotimpl) +{ + putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDMMC1_ICR); + return -ENOSYS; +} + +/**************************************************************************** + * Name: stm32_waitenable + * + * Description: + * Enable/disable of a set of SDIO wait events. This is part of the + * the SDIO_WAITEVENT sequence. The set of to-be-waited-for events is + * configured before calling stm32_eventwait. This is done in this way + * to help the driver to eliminate race conditions between the command + * setup and the subsequent events. + * + * The enabled events persist until either (1) SDIO_WAITENABLE is called + * again specifying a different set of wait events, or (2) SDIO_EVENTWAIT + * returns. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * eventset - A bitset of events to enable or disable (see SDIOWAIT_* + * definitions). 0=disable; 1=enable. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_waitenable(FAR struct sdio_dev_s *dev, + sdio_eventset_t eventset) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + uint32_t waitmask; + + DEBUGASSERT(priv != NULL); + + /* Disable event-related interrupts */ + + stm32_configwaitints(priv, 0, 0, 0); + + /* Select the interrupt mask that will give us the appropriate wakeup + * interrupts. + */ + +#if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE) + if ((eventset & SDIOWAIT_WRCOMPLETE) != 0) + { + waitmask = SDIOWAIT_WRCOMPLETE; + } + else +#endif + { + waitmask = 0; + if ((eventset & SDIOWAIT_CMDDONE) != 0) + { + waitmask |= SDIO_CMDDONE_MASK; + } + + if ((eventset & SDIOWAIT_RESPONSEDONE) != 0) + { + waitmask |= SDIO_RESPDONE_MASK; + } + + if ((eventset & SDIOWAIT_TRANSFERDONE) != 0) + { + waitmask |= SDIO_XFRDONE_MASK; + } + + /* Enable event-related interrupts */ + + putreg32(SDIO_WAITALL_ICR, STM32_SDMMC1_ICR); + } + + stm32_configwaitints(priv, waitmask, eventset, 0); +} + +/**************************************************************************** + * Name: stm32_eventwait + * + * Description: + * Wait for one of the enabled events to occur (or a timeout). Note that + * all events enabled by SDIO_WAITEVENTS are disabled when stm32_eventwait + * returns. SDIO_WAITEVENTS must be called again before stm32_eventwait + * can be used again. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * timeout - Maximum time in milliseconds to wait. Zero means immediate + * timeout with no wait. The timeout value is ignored if + * SDIOWAIT_TIMEOUT is not included in the waited-for eventset. + * + * Returned Value: + * Event set containing the event(s) that ended the wait. Should always + * be non-zero. All events are disabled after the wait concludes. + * + ****************************************************************************/ + +static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev, + uint32_t timeout) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + sdio_eventset_t wkupevent = 0; + irqstate_t flags; + int ret; + + /* There is a race condition here... the event may have completed before + * we get here. In this case waitevents will be zero, but wkupevents will + * be non-zero (and, hopefully, the semaphore count will also be non-zero. + */ + + flags = enter_critical_section(); + DEBUGASSERT(priv->waitevents != 0 || priv->wkupevent != 0); + + /* Check if the timeout event is specified in the event set */ + + if ((priv->waitevents & SDIOWAIT_TIMEOUT) != 0) + { + int delay; + + /* Yes.. Handle a cornercase: The user request a timeout event but + * with timeout == 0? + */ + + if (!timeout) + { + /* Then just tell the caller that we already timed out */ + + wkupevent = SDIOWAIT_TIMEOUT; + goto errout; + } + + /* Start the watchdog timer */ + + delay = MSEC2TICK(timeout); + ret = wd_start(priv->waitwdog, delay, (wdentry_t)stm32_eventtimeout, + 1, (uint32_t)priv); + if (ret != OK) + { + ferr("ERROR: wd_start failed: %d\n", ret); + } + } + +#if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE) + if ((priv->waitevents & SDIOWAIT_WRCOMPLETE) != 0) + { + /* Atomically read pin to see if ready (true) and determine if ISR fired + * If Pin is ready and if ISR did NOT fire end the wait here + */ + + if (stm32_gpioread(GPIO_SDMMC1_D0) && + (priv->wkupevent & SDIOWAIT_WRCOMPLETE) == 0) + { + stm32_endwait(priv, SDIOWAIT_WRCOMPLETE); + } + } +#endif + + /* Loop until the event (or the timeout occurs). Race conditions are avoided + * by calling stm32_waitenable prior to triggering the logic that will cause + * the wait to terminate. Under certain race conditions, the waited-for + * may have already occurred before this function was called! + */ + + for (; ; ) + { + /* Wait for an event in event set to occur. If this the event has already + * occurred, then the semaphore will already have been incremented and + * there will be no wait. + */ + + stm32_takesem(priv); + wkupevent = priv->wkupevent; + + /* Check if the event has occurred. When the event has occurred, then + * evenset will be set to 0 and wkupevent will be set to a nonzero value. + */ + + if (wkupevent != 0) + { + /* Yes... break out of the loop with wkupevent non-zero */ + + break; + } + } + + /* Disable event-related interrupts */ + + stm32_configwaitints(priv, 0, 0, 0); +#ifdef CONFIG_SDIO_DMA + priv->xfrflags = 0; +#endif + +errout: + leave_critical_section(flags); + stm32_dumpsamples(priv); + return wkupevent; +} + +/**************************************************************************** + * Name: stm32_callbackenable + * + * Description: + * Enable/disable of a set of SDIO callback events. This is part of the + * the SDIO callback sequence. The set of events is configured to enabled + * callbacks to the function provided in stm32_registercallback. + * + * Events are automatically disabled once the callback is performed and no + * further callback events will occur until they are again enabled by + * calling this methos. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * eventset - A bitset of events to enable or disable (see SDIOMEDIA_* + * definitions). 0=disable; 1=enable. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_callbackenable(FAR struct sdio_dev_s *dev, + sdio_eventset_t eventset) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + finfo("eventset: %02x\n", eventset); + DEBUGASSERT(priv != NULL); + + priv->cbevents = eventset; + stm32_callback(priv); +} + +/**************************************************************************** + * Name: stm32_registercallback + * + * Description: + * Register a callback that that will be invoked on any media status + * change. Callbacks should not be made from interrupt handlers, rather + * interrupt level events should be handled by calling back on the work + * thread. + * + * When this method is called, all callbacks should be disabled until they + * are enabled via a call to SDIO_CALLBACKENABLE + * + * Input Parameters: + * dev - Device-specific state data + * callback - The funtion to call on the media change + * arg - A caller provided value to return with the callback + * + * Returned Value: + * 0 on success; negated errno on failure. + * + ****************************************************************************/ + +static int stm32_registercallback(FAR struct sdio_dev_s *dev, + worker_t callback, void *arg) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + /* Disable callbacks and register this callback and is argument */ + + finfo("Register %p(%p)\n", callback, arg); + DEBUGASSERT(priv != NULL); + + priv->cbevents = 0; + priv->cbarg = arg; + priv->callback = callback; + return OK; +} + +/**************************************************************************** + * Name: stm32_dmasupported + * + * Description: + * Return true if the hardware can support DMA + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * + * Returned Value: + * true if DMA is supported. + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_DMA +static bool stm32_dmasupported(FAR struct sdio_dev_s *dev) +{ + return true; +} +#endif + +/**************************************************************************** + * Name: stm32_dmapreflight + * + * Description: + * Preflight an SDIO DMA operation. If the buffer is not well-formed for + * SDIO DMA transfer (alignment, size, etc.) returns an error. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * buffer - The memory to DMA to/from + * buflen - The size of the DMA transfer in bytes + * + * Returned Value: + * OK on success; a negated errno on failure + ****************************************************************************/ + +#if defined(CONFIG_SDIO_DMA) && defined(CONFIG_SDIO_PREFLIGHT) +static int stm32_dmapreflight(FAR struct sdio_dev_s *dev, + FAR const uint8_t *buffer, size_t buflen) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + + DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); + + /* Wide bus operation is required for DMA */ + + if (!priv->widebus) + { + return -EINVAL; + } + + /* DMA must be possible to the buffer */ + + if (!stm32_dmacapable((uintptr_t)buffer, (buflen + 3) >> 2, SDIO_RXDMA32_CONFIG)) + { + return -EFAULT; + } + + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_dmarecvsetup + * + * Description: + * Setup to perform a read DMA. If the processor supports a data cache, + * then this method will also make sure that the contents of the DMA memory + * and the data cache are coherent. For read transfers this may mean + * invalidating the data cache. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * buffer - The memory to DMA from + * buflen - The size of the DMA transfer in bytes + * + * Returned Value: + * OK on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_DMA +static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, + size_t buflen) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + uint32_t dblocksize; + + DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); +#ifdef CONFIG_SDIO_PREFLIGHT + DEBUGASSERT(stm32_dmapreflight(dev, buffer, buflen) == 0); +#endif + +#ifdef CONFIG_ARMV7M_DCACHE + /* buffer alignment is required for DMA transfers with dcache */ + + if (((uintptr_t)buffer & (ARMV7M_DCACHE_LINESIZE-1)) != 0 || (buflen & (ARMV7M_DCACHE_LINESIZE-1)) != 0) + { + return -EFAULT; + } +#endif + + /* Reset the DPSM configuration */ + + stm32_datadisable(); + + /* Initialize register sampling */ + + stm32_sampleinit(); + stm32_sample(priv, SAMPLENDX_BEFORE_SETUP); + + /* Save the destination buffer information for use by the interrupt handler */ + + priv->buffer = (uint32_t *)buffer; + priv->remaining = buflen; + priv->dmamode = true; + + /* Then set up the SDIO data path */ + + dblocksize = stm32_log2(buflen) << SDIO_DCTRL_DBLOCKSIZE_SHIFT; + stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, buflen, dblocksize | SDIO_DCTRL_DTDIR); + + /* Configure the RX DMA */ + + stm32_configxfrints(priv, SDIO_DMARECV_MASK); + + stm32_dmasetup(priv->dma, STM32_SDMMC1_FIFO, (uint32_t)buffer, + (buflen + 3) >> 2, SDIO_RXDMA32_CONFIG); + + /* Force RAM reread */ + + arch_invalidate_dcache((uintptr_t)buffer,(uintptr_t)buffer + buflen); + + /* Start the DMA */ + + stm32_sample(priv, SAMPLENDX_BEFORE_ENABLE); + stm32_dmastart(priv->dma, stm32_dmacallback, priv, false); + stm32_sample(priv, SAMPLENDX_AFTER_SETUP); + + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_dmasendsetup + * + * Description: + * Setup to perform a write DMA. If the processor supports a data cache, + * then this method will also make sure that the contents of the DMA memory + * and the data cache are coherent. For write transfers, this may mean + * flushing the data cache. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * buffer - The memory to DMA into + * buflen - The size of the DMA transfer in bytes + * + * Returned Value: + * OK on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_DMA +static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, + FAR const uint8_t *buffer, size_t buflen) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + uint32_t dblocksize; + + DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); +#ifdef CONFIG_SDIO_PREFLIGHT + DEBUGASSERT(stm32_dmapreflight(dev, buffer, buflen) == 0); +#endif + +#ifdef CONFIG_ARMV7M_DCACHE + /* buffer alignment is required for DMA transfers with dcache */ + + if (((uintptr_t)buffer & (ARMV7M_DCACHE_LINESIZE-1)) != 0 || (buflen & (ARMV7M_DCACHE_LINESIZE-1)) != 0) + { + return -EFAULT; + } +#endif + + /* Reset the DPSM configuration */ + + stm32_datadisable(); + + /* Initialize register sampling */ + + stm32_sampleinit(); + stm32_sample(priv, SAMPLENDX_BEFORE_SETUP); + + /* Save the source buffer information for use by the interrupt handler */ + + priv->buffer = (uint32_t *)buffer; + priv->remaining = buflen; + priv->dmamode = true; + + /* Then set up the SDIO data path */ + + dblocksize = stm32_log2(buflen) << SDIO_DCTRL_DBLOCKSIZE_SHIFT; + stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, buflen, dblocksize); + + /* Configure the TX DMA */ + + stm32_dmasetup(priv->dma, STM32_SDMMC1_FIFO, (uint32_t)buffer, + (buflen + 3) >> 2, SDIO_TXDMA32_CONFIG); + + stm32_sample(priv, SAMPLENDX_BEFORE_ENABLE); + + /* Flush cache to physical memory */ + + arch_flush_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); + + /* Start the DMA */ + + stm32_dmastart(priv->dma, stm32_dmacallback, priv, false); + stm32_sample(priv, SAMPLENDX_AFTER_SETUP); + + /* Enable TX interrupts */ + + stm32_configxfrints(priv, SDIO_DMASEND_MASK); + + return OK; +} +#endif + +/**************************************************************************** + * Initialization/uninitialization/reset + ****************************************************************************/ +/**************************************************************************** + * Name: stm32_callback + * + * Description: + * Perform callback. + * + * Assumptions: + * This function does not execute in the context of an interrupt handler. + * It may be invoked on any user thread or scheduled on the work thread + * from an interrupt handler. + * + ****************************************************************************/ + +static void stm32_callback(void *arg) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; + + /* Is a callback registered? */ + + DEBUGASSERT(priv != NULL); + finfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n", + priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus); + + if (priv->callback) + { + /* Yes.. Check for enabled callback events */ + + if ((priv->cdstatus & SDIO_STATUS_PRESENT) != 0) + { + /* Media is present. Is the media inserted event enabled? */ + + if ((priv->cbevents & SDIOMEDIA_INSERTED) == 0) + { + /* No... return without performing the callback */ + + return; + } + } + else + { + /* Media is not present. Is the media eject event enabled? */ + + if ((priv->cbevents & SDIOMEDIA_EJECTED) == 0) + { + /* No... return without performing the callback */ + + return; + } + } + + /* Perform the callback, disabling further callbacks. Of course, the + * the callback can (and probably should) re-enable callbacks. + */ + + priv->cbevents = 0; + + /* Callbacks cannot be performed in the context of an interrupt handler. + * If we are in an interrupt handler, then queue the callback to be + * performed later on the work thread. + */ + + if (up_interrupt_context()) + { + /* Yes.. queue it */ + + finfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg); + (void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0); + } + else + { + /* No.. then just call the callback here */ + + finfo("Callback to %p(%p)\n", priv->callback, priv->cbarg); + priv->callback(priv->cbarg); + } + } +} + +/**************************************************************************** + * Name: stm32_default + * + * Description: + * Restore SDIO registers to their default, reset values + * + ****************************************************************************/ + +static void stm32_default(void) +{ + putreg32(SDIO_POWER_RESET, STM32_SDMMC1_POWER); + putreg32(SDIO_CLKCR_RESET, STM32_SDMMC1_CLKCR); + putreg32(SDIO_ARG_RESET, STM32_SDMMC1_ARG); + putreg32(SDIO_CMD_RESET, STM32_SDMMC1_CMD); + putreg32(SDIO_DTIMER_RESET, STM32_SDMMC1_DTIMER); + putreg32(SDIO_DLEN_RESET, STM32_SDMMC1_DLEN); + putreg32(SDIO_DCTRL_RESET, STM32_SDMMC1_DCTRL); + putreg32(SDIO_ICR_RESET, STM32_SDMMC1_ICR); + putreg32(SDIO_MASK_RESET, STM32_SDMMC1_MASK); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sdio_initialize + * + * Description: + * Initialize SDIO for operation. + * + * Input Parameters: + * slotno - Not used. + * + * Returned Values: + * A reference to an SDIO interface structure. NULL is returned on failures. + * + ****************************************************************************/ + +FAR struct sdio_dev_s *sdio_initialize(int slotno) +{ + /* There is only one slot */ + + struct stm32_dev_s *priv = &g_sdiodev; + + /* Initialize the SDIO slot structure */ + + sem_init(&priv->waitsem, 0, 0); + priv->waitwdog = wd_create(); + DEBUGASSERT(priv->waitwdog); + + /* Allocate a DMA channel */ + +#ifdef CONFIG_SDIO_DMA + priv->dma = stm32_dmachannel(SDIO_DMACHAN); + DEBUGASSERT(priv->dma); +#endif + + /* Configure GPIOs for 4-bit, wide-bus operation (the chip is capable of + * 8-bit wide bus operation but D4-D7 are not configured). + * + * If bus is multiplexed then there is a custom bus configuration utility + * in the scope of the board support package. + */ + +#ifndef CONFIG_SDIO_MUXBUS + stm32_configgpio(GPIO_SDMMC1_D0); +#ifndef CONFIG_SDIO_WIDTH_D1_ONLY + stm32_configgpio(GPIO_SDMMC1_D1); + stm32_configgpio(GPIO_SDMMC1_D2); + stm32_configgpio(GPIO_SDMMC1_D3); +#endif + stm32_configgpio(GPIO_SDMMC1_CK); + stm32_configgpio(GPIO_SDMMC1_CMD); +#endif + + /* Reset the card and assure that it is in the initial, unconfigured + * state. + */ + + stm32_reset(&priv->dev); + return &g_sdiodev.dev; +} + +/**************************************************************************** + * Name: sdio_mediachange + * + * Description: + * Called by board-specific logic -- posssible from an interrupt handler -- + * in order to signal to the driver that a card has been inserted or + * removed from the slot + * + * Input Parameters: + * dev - An instance of the SDIO driver device state structure. + * cardinslot - true is a card has been detected in the slot; false if a + * card has been removed from the slot. Only transitions + * (inserted->removed or removed->inserted should be reported) + * + * Returned Values: + * None + * + ****************************************************************************/ + +void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + uint8_t cdstatus; + irqstate_t flags; + + /* Update card status */ + + flags = enter_critical_section(); + cdstatus = priv->cdstatus; + if (cardinslot) + { + priv->cdstatus |= SDIO_STATUS_PRESENT; + } + else + { + priv->cdstatus &= ~SDIO_STATUS_PRESENT; + } + + leave_critical_section(flags); + + finfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus); + + /* Perform any requested callback if the status has changed */ + + if (cdstatus != priv->cdstatus) + { + stm32_callback(priv); + } +} + +/**************************************************************************** + * Name: sdio_wrprotect + * + * Description: + * Called by board-specific logic to report if the card in the slot is + * mechanically write protected. + * + * Input Parameters: + * dev - An instance of the SDIO driver device state structure. + * wrprotect - true is a card is writeprotected. + * + * Returned Values: + * None + * + ****************************************************************************/ + +void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect) +{ + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + irqstate_t flags; + + /* Update card status */ + + flags = enter_critical_section(); + if (wrprotect) + { + priv->cdstatus |= SDIO_STATUS_WRPROTECTED; + } + else + { + priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED; + } + finfo("cdstatus: %02x\n", priv->cdstatus); + leave_critical_section(flags); +} +#endif /* CONFIG_STM32F7_SDMMC1 */ diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.h b/arch/arm/src/stm32f7/stm32_sdmmc.h new file mode 100644 index 0000000000..29e14683ce --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_sdmmc.h @@ -0,0 +1,129 @@ +/************************************************************************************ + * arch/arm/src/stm32/stm32_sdio.h + * + * Copyright (C) 2009, 2011, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_STM32_SDMMC_H +#define __ARCH_ARM_SRC_STM32F7_STM32_SDMMC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include "chip/stm32_sdmmc.h" + +#include +#include +#include + +#include "chip.h" + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: sdio_initialize + * + * Description: + * Initialize SDIO for operation. + * + * Input Parameters: + * slotno - Not used. + * + * Returned Values: + * A reference to an SDIO interface structure. NULL is returned on failures. + * + ****************************************************************************/ + +struct sdio_dev_s; /* See include/nuttx/sdio.h */ +FAR struct sdio_dev_s *sdio_initialize(int slotno); + +/**************************************************************************** + * Name: sdio_mediachange + * + * Description: + * Called by board-specific logic -- posssible from an interrupt handler -- + * in order to signal to the driver that a card has been inserted or + * removed from the slot + * + * Input Parameters: + * dev - An instance of the SDIO driver device state structure. + * cardinslot - true is a card has been detected in the slot; false if a + * card has been removed from the slot. Only transitions + * (inserted->removed or removed->inserted should be reported) + * + * Returned Values: + * None + * + ****************************************************************************/ + +void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot); + +/**************************************************************************** + * Name: sdio_wrprotect + * + * Description: + * Called by board-specific logic to report if the card in the slot is + * mechanically write protected. + * + * Input Parameters: + * dev - An instance of the SDIO driver device state structure. + * wrprotect - true is a card is writeprotected. + * + * Returned Values: + * None + * + ****************************************************************************/ + +void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_STM32F7_STM32_SDMMC_H */ + diff --git a/configs/stm32f746-ws/include/board.h b/configs/stm32f746-ws/include/board.h index 1f5e3f030c..df3474497a 100644 --- a/configs/stm32f746-ws/include/board.h +++ b/configs/stm32f746-ws/include/board.h @@ -213,6 +213,48 @@ #define GPIO_I2C1_SCL GPIO_I2C1_SCL_1 #define GPIO_I2C1_SDA GPIO_I2C1_SDA_1 +/* SDMMC */ + +/* Stream selections are arbitrary for now but might become important in the future + * if we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDMMC1_1 = Channel 4, Stream 3 + * DMAMAP_SDMMC1_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1 + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define SDMMC1_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDMMC1_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDMMC1_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDMMC1_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDMMC1_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + /************************************************************************************ * Public Data ************************************************************************************/ diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig index df3654343f..c282d9ee49 100644 --- a/configs/stm32f746-ws/nsh/defconfig +++ b/configs/stm32f746-ws/nsh/defconfig @@ -170,7 +170,7 @@ CONFIG_STM32F7_HAVE_LTDC=y # CONFIG_STM32F7_ADC is not set # CONFIG_STM32F7_CAN is not set # CONFIG_STM32F7_DAC is not set -# CONFIG_STM32F7_DMA is not set +CONFIG_STM32F7_DMA=y CONFIG_STM32F7_I2C=y # CONFIG_STM32F7_SAI is not set CONFIG_STM32F7_SPI=y @@ -185,7 +185,7 @@ CONFIG_STM32F7_ADC1=y # CONFIG_STM32F7_CRC is not set # CONFIG_STM32F7_CRYP is not set # CONFIG_STM32F7_DMA1 is not set -# CONFIG_STM32F7_DMA2 is not set +CONFIG_STM32F7_DMA2=y # CONFIG_STM32F7_DAC1 is not set # CONFIG_STM32F7_DAC2 is not set # CONFIG_STM32F7_DCMI is not set @@ -203,7 +203,7 @@ CONFIG_STM32F7_I2C1=y # CONFIG_STM32F7_SAI1 is not set # CONFIG_STM32F7_RNG is not set # CONFIG_STM32F7_SAI2 is not set -# CONFIG_STM32F7_SDMMC1 is not set +CONFIG_STM32F7_SDMMC1=y # CONFIG_STM32F7_SPDIFRX is not set CONFIG_STM32F7_SPI1=y # CONFIG_STM32F7_SPI2 is not set @@ -243,7 +243,7 @@ CONFIG_STM32F7_USART6=y # # CONFIG_ARCH_NOINTC is not set # CONFIG_ARCH_VECNOTIRQ is not set -# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_DMA=y CONFIG_ARCH_HAVE_IRQPRIO=y # CONFIG_ARCH_L2CACHE is not set # CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set @@ -464,6 +464,7 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CRCGENERATION is not set # CONFIG_I2S is not set CONFIG_ADC=y +CONFIG_SDIO_DMA=y # # Timer Driver Support @@ -485,7 +486,15 @@ CONFIG_WATCHDOG_DEVPATH="/dev/watchdog0" # CONFIG_USERLED is not set # CONFIG_RGBLED is not set # CONFIG_PCA9635PW is not set -# CONFIG_MMCSD is not set + +CONFIG_MMCSD=y +CONFIG_MMCSD_NSLOTS=1 +CONFIG_MMCSD_MULTIBLOCK_DISABLE=y +CONFIG_ARCH_HAVE_SDIO=y +CONFIG_ARCH_HAVE_SDIOWAIT_WRCOMPLETE=y +CONFIG_MMCSD_SDIO=y +CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE=y + # CONFIG_MODEM is not set # CONFIG_MTD is not set # CONFIG_EEPROM is not set @@ -578,19 +587,27 @@ CONFIG_USART6_2STOP=0 # CONFIG_DISABLE_MOUNTPOINT is not set # CONFIG_FS_AUTOMOUNTER is not set # CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_FS_READABLE is not set -# CONFIG_FS_WRITABLE is not set +CONFIG_FS_READABLE=y +CONFIG_FS_WRITABLE=y # CONFIG_FS_NAMED_SEMAPHORES is not set CONFIG_FS_MQUEUE_MPATH="/var/mqueue" # CONFIG_FS_RAMMAP is not set -# CONFIG_FS_FAT is not set +CONFIG_FS_FAT=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=32 # CONFIG_FS_NXFFS is not set -# CONFIG_FS_ROMFS is not set -# CONFIG_FS_TMPFS is not set +CONFIG_FS_ROMFS=y +CONFIG_FS_TMPFS=y +CONFIG_FS_TMPFS_BLOCKSIZE=512 +CONFIG_FS_TMPFS_DIRECTORY_ALLOCGUARD=64 +CONFIG_FS_TMPFS_DIRECTORY_FREEGUARD=128 +CONFIG_FS_TMPFS_FILE_ALLOCGUARD=512 +CONFIG_FS_TMPFS_FILE_FREEGUARD=1024 # CONFIG_FS_SMARTFS is not set # CONFIG_FS_BINFS is not set -# CONFIG_FS_PROCFS is not set -# CONFIG_FS_UNIONFS is not set +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y # # System Logging diff --git a/configs/stm32f746-ws/src/stm32_spi.c b/configs/stm32f746-ws/src/stm32_spi.c index e973ca9b82..517ea3761b 100644 --- a/configs/stm32f746-ws/src/stm32_spi.c +++ b/configs/stm32f746-ws/src/stm32_spi.c @@ -101,7 +101,7 @@ void weak_function stm32_spidev_initialize(void) #ifdef CONFIG_STM32F7_SPI1 void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { - spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) @@ -113,7 +113,7 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) #ifdef CONFIG_STM32F7_SPI2 void stm32_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { - spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) @@ -125,7 +125,7 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) #ifdef CONFIG_STM32F7_SPI3 void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { - spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) @@ -137,7 +137,7 @@ uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) #ifdef CONFIG_STM32F7_SPI4 void stm32_spi4select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { - spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) @@ -149,7 +149,7 @@ uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) #ifdef CONFIG_STM32F7_SPI5 void stm32_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { - spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) @@ -161,7 +161,7 @@ uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) #ifdef CONFIG_STM32F7_SPI6 void stm32_spi6select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { - spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi6status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) -- GitLab From 98e7e5c402aa79ca07a6a8f8766e6aed3ff9eb04 Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Fri, 17 Jun 2016 17:47:23 +0200 Subject: [PATCH 002/734] usb copy --- arch/arm/src/stm32f7/Make.defs | 8 + arch/arm/src/stm32f7/chip/stm32_otg.h | 1022 +++ .../src/stm32f7/chip/stm32f74xx75xx_sdmmc.h | 2 +- arch/arm/src/stm32f7/stm32_i2c.c | 2 +- arch/arm/src/stm32f7/stm32_otg.h | 139 + arch/arm/src/stm32f7/stm32_otgdev.c | 5666 +++++++++++++++++ arch/arm/src/stm32f7/stm32_otghost.c | 5306 +++++++++++++++ arch/arm/src/stm32f7/stm32_sdmmc.h | 2 +- 8 files changed, 12144 insertions(+), 3 deletions(-) create mode 100644 arch/arm/src/stm32f7/chip/stm32_otg.h create mode 100644 arch/arm/src/stm32f7/stm32_otg.h create mode 100644 arch/arm/src/stm32f7/stm32_otgdev.c create mode 100644 arch/arm/src/stm32f7/stm32_otghost.c diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index 123c70ffc2..1474c0b57d 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -151,6 +151,14 @@ ifeq ($(CONFIG_STM32F7_SDMMC1),y) CHIP_CSRCS += stm32_sdmmc.c endif +ifeq ($(CONFIG_USBDEV),y) +CHIP_CSRCS += stm32_otgdev.c +endif + +ifeq ($(CONFIG_USBHOST),y) +CHIP_CSRCS += stm32_otghost.c +endif + ifeq ($(CONFIG_STM32F7_TIM),y) CHIP_CSRCS += stm32_tim.c endif diff --git a/arch/arm/src/stm32f7/chip/stm32_otg.h b/arch/arm/src/stm32f7/chip/stm32_otg.h new file mode 100644 index 0000000000..ee06497102 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32_otg.h @@ -0,0 +1,1022 @@ +/**************************************************************************************************** + * arch/arm/src/stm32f7/chip/stm32f_otgfs.h + * + * Copyright (C) 2012, 2014-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Gregory Nutt + * Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_OTG_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_OTG_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ +/* General definitions */ + +#define OTG_EPTYPE_CTRL (0) /* Control */ +#define OTG_EPTYPE_ISOC (1) /* Isochronous */ +#define OTG_EPTYPE_BULK (2) /* Bulk */ +#define OTG_EPTYPE_INTR (3) /* Interrupt */ + +#define OTG_PID_DATA0 (0) +#define OTG_PID_DATA2 (1) +#define OTG_PID_DATA1 (2) +#define OTG_PID_MDATA (3) /* Non-control */ +#define OTG_PID_SETUP (3) /* Control */ + +/* Register Offsets *********************************************************************************/ +/* Core global control and status registers */ + +#define STM32_OTG_GOTGCTL_OFFSET 0x0000 /* Control and status register */ +#define STM32_OTG_GOTGINT_OFFSET 0x0004 /* Interrupt register */ +#define STM32_OTG_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ +#define STM32_OTG_GUSBCFG_OFFSET 0x000c /* USB configuration register */ +#define STM32_OTG_GRSTCTL_OFFSET 0x0010 /* Reset register */ +#define STM32_OTG_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ +#define STM32_OTG_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ +#define STM32_OTG_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ +#define STM32_OTG_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ +#define STM32_OTG_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ +#define STM32_OTG_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ +#define STM32_OTG_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ +#define STM32_OTG_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ +#define STM32_OTG_GCCFG_OFFSET 0x0038 /* General core configuration register */ +#define STM32_OTG_CID_OFFSET 0x003c /* Core ID register */ +#define STM32_OTG_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ + +#define STM32_OTG_DIEPTXF_OFFSET(n) (104+(((n)-1) << 2)) +#define STM32_OTG_DIEPTXF1_OFFSET 0x0104 /* Device IN endpoint transmit FIFO1 size register */ +#define STM32_OTG_DIEPTXF2_OFFSET 0x0108 /* Device IN endpoint transmit FIFO2 size register */ +#define STM32_OTG_DIEPTXF3_OFFSET 0x010c /* Device IN endpoint transmit FIFO3 size register */ + +/* Host-mode control and status registers */ + +#define STM32_OTG_HCFG_OFFSET 0x0400 /* Host configuration register */ +#define STM32_OTG_HFIR_OFFSET 0x0404 /* Host frame interval register */ +#define STM32_OTG_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ +#define STM32_OTG_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ +#define STM32_OTG_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ +#define STM32_OTG_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ +#define STM32_OTG_HPRT_OFFSET 0x0440 /* Host port control and status register */ + +#define STM32_OTG_CHAN_OFFSET(n) (0x500 + ((n) << 5) +#define STM32_OTG_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ +#define STM32_OTG_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ +#define STM32_OTG_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ +#define STM32_OTG_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ + +#define STM32_OTG_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) +#define STM32_OTG_HCCHAR0_OFFSET 0x0500 /* Host channel-0 characteristics register */ +#define STM32_OTG_HCCHAR1_OFFSET 0x0520 /* Host channel-1 characteristics register */ +#define STM32_OTG_HCCHAR2_OFFSET 0x0540 /* Host channel-2 characteristics register */ +#define STM32_OTG_HCCHAR3_OFFSET 0x0560 /* Host channel-3 characteristics register */ +#define STM32_OTG_HCCHAR4_OFFSET 0x0580 /* Host channel-4 characteristics register */ +#define STM32_OTG_HCCHAR5_OFFSET 0x05a0 /* Host channel-5 characteristics register */ +#define STM32_OTG_HCCHAR6_OFFSET 0x05c0 /* Host channel-6 characteristics register */ +#define STM32_OTG_HCCHAR7_OFFSET 0x05e0 /* Host channel-7 characteristics register */ + +#define STM32_OTG_HCINT_OFFSET(n) (0x508 + ((n) << 5)) +#define STM32_OTG_HCINT0_OFFSET 0x0508 /* Host channel-0 interrupt register */ +#define STM32_OTG_HCINT1_OFFSET 0x0528 /* Host channel-1 interrupt register */ +#define STM32_OTG_HCINT2_OFFSET 0x0548 /* Host channel-2 interrupt register */ +#define STM32_OTG_HCINT3_OFFSET 0x0568 /* Host channel-3 interrupt register */ +#define STM32_OTG_HCINT4_OFFSET 0x0588 /* Host channel-4 interrupt register */ +#define STM32_OTG_HCINT5_OFFSET 0x05a8 /* Host channel-5 interrupt register */ +#define STM32_OTG_HCINT6_OFFSET 0x05c8 /* Host channel-6 interrupt register */ +#define STM32_OTG_HCINT7_OFFSET 0x05e8 /* Host channel-7 interrupt register */ + +#define STM32_OTG_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) +#define STM32_OTG_HCINTMSK0_OFFSET 0x050c /* Host channel-0 interrupt mask register */ +#define STM32_OTG_HCINTMSK1_OFFSET 0x052c /* Host channel-1 interrupt mask register */ +#define STM32_OTG_HCINTMSK2_OFFSET 0x054c /* Host channel-2 interrupt mask register */ +#define STM32_OTG_HCINTMSK3_OFFSET 0x056c /* Host channel-3 interrupt mask register */ +#define STM32_OTG_HCINTMSK4_OFFSET 0x058c /* Host channel-4 interrupt mask register */ +#define STM32_OTG_HCINTMSK5_OFFSET 0x05ac /* Host channel-5 interrupt mask register */ +#define STM32_OTG_HCINTMSK6_OFFSET 0x05cc /* Host channel-6 interrupt mask register */ +#define STM32_OTG_HCINTMSK7_OFFSET 0x05ec /* Host channel-7 interrupt mask register */ + +#define STM32_OTG_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) +#define STM32_OTG_HCTSIZ0_OFFSET 0x0510 /* Host channel-0 interrupt register */ +#define STM32_OTG_HCTSIZ1_OFFSET 0x0530 /* Host channel-1 interrupt register */ +#define STM32_OTG_HCTSIZ2_OFFSET 0x0550 /* Host channel-2 interrupt register */ +#define STM32_OTG_HCTSIZ3_OFFSET 0x0570 /* Host channel-3 interrupt register */ +#define STM32_OTG_HCTSIZ4_OFFSET 0x0590 /* Host channel-4 interrupt register */ +#define STM32_OTG_HCTSIZ5_OFFSET 0x05b0 /* Host channel-5 interrupt register */ +#define STM32_OTG_HCTSIZ6_OFFSET 0x05d0 /* Host channel-6 interrupt register */ +#define STM32_OTG_HCTSIZ7_OFFSET 0x05f0 /* Host channel-7 interrupt register */ + +/* Device-mode control and status registers */ + +#define STM32_OTG_DCFG_OFFSET 0x0800 /* Device configuration register */ +#define STM32_OTG_DCTL_OFFSET 0x0804 /* Device control register */ +#define STM32_OTG_DSTS_OFFSET 0x0808 /* Device status register */ +#define STM32_OTG_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ +#define STM32_OTG_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ +#define STM32_OTG_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ +#define STM32_OTG_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ +#define STM32_OTG_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ +#define STM32_OTG_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ +#define STM32_OTG_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ + +#define STM32_OTG_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTG_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ +#define STM32_OTG_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ +#define STM32_OTG_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ +#define STM32_OTG_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ + +#define STM32_OTG_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTG_DIEPCTL0_OFFSET 0x0900 /* Device control IN endpoint 0 control register */ +#define STM32_OTG_DIEPCTL1_OFFSET 0x0920 /* Device control IN endpoint 2 control register */ +#define STM32_OTG_DIEPCTL2_OFFSET 0x0940 /* Device control IN endpoint 3 control register */ +#define STM32_OTG_DIEPCTL3_OFFSET 0x0960 /* Device control IN endpoint 4 control register */ + +#define STM32_OTG_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) +#define STM32_OTG_DIEPINT0_OFFSET 0x0908 /* Device endpoint-0 interrupt register */ +#define STM32_OTG_DIEPINT1_OFFSET 0x0928 /* Device endpoint-1 interrupt register */ +#define STM32_OTG_DIEPINT2_OFFSET 0x0948 /* Device endpoint-2 interrupt register */ +#define STM32_OTG_DIEPINT3_OFFSET 0x0968 /* Device endpoint-3 interrupt register */ + +#define STM32_OTG_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) +#define STM32_OTG_DIEPTSIZ0_OFFSET 0x0910 /* Device IN endpoint 0 transfer size register */ +#define STM32_OTG_DIEPTSIZ1_OFFSET 0x0930 /* Device IN endpoint 1 transfer size register */ +#define STM32_OTG_DIEPTSIZ2_OFFSET 0x0950 /* Device IN endpoint 2 transfer size register */ +#define STM32_OTG_DIEPTSIZ3_OFFSET 0x0970 /* Device IN endpoint 3 transfer size register */ + +#define STM32_OTG_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) +#define STM32_OTG_DTXFSTS0_OFFSET 0x0918 /* Device OUT endpoint-0 TxFIFO status register */ +#define STM32_OTG_DTXFSTS1_OFFSET 0x0938 /* Device OUT endpoint-1 TxFIFO status register */ +#define STM32_OTG_DTXFSTS2_OFFSET 0x0958 /* Device OUT endpoint-2 TxFIFO status register */ +#define STM32_OTG_DTXFSTS3_OFFSET 0x0978 /* Device OUT endpoint-3 TxFIFO status register */ + +#define STM32_OTG_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTG_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ +#define STM32_OTG_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ + +#define STM32_OTG_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTG_DOEPCTL0_OFFSET 0x00b00 /* Device OUT endpoint 0 control register */ +#define STM32_OTG_DOEPCTL1_OFFSET 0x00b20 /* Device OUT endpoint 1 control register */ +#define STM32_OTG_DOEPCTL2_OFFSET 0x00b40 /* Device OUT endpoint 2 control register */ +#define STM32_OTG_DOEPCTL3_OFFSET 0x00b60 /* Device OUT endpoint 3 control register */ + +#define STM32_OTG_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) +#define STM32_OTG_DOEPINT0_OFFSET 0x00b08 /* Device endpoint-0 interrupt register */ +#define STM32_OTG_DOEPINT1_OFFSET 0x00b28 /* Device endpoint-1 interrupt register */ +#define STM32_OTG_DOEPINT2_OFFSET 0x00b48 /* Device endpoint-2 interrupt register */ +#define STM32_OTG_DOEPINT3_OFFSET 0x00b68 /* Device endpoint-3 interrupt register */ + +#define STM32_OTG_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) +#define STM32_OTG_DOEPTSIZ0_OFFSET 0x00b10 /* Device OUT endpoint-0 transfer size register */ +#define STM32_OTG_DOEPTSIZ1_OFFSET 0x00b30 /* Device OUT endpoint-1 transfer size register */ +#define STM32_OTG_DOEPTSIZ2_OFFSET 0x00b50 /* Device OUT endpoint-2 transfer size register */ +#define STM32_OTG_DOEPTSIZ3_OFFSET 0x00b70 /* Device OUT endpoint-3 transfer size register */ + +/* Power and clock gating registers */ + +#define STM32_OTG_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ + +/* Data FIFO (DFIFO) access registers */ + +#define STM32_OTG_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) +#define STM32_OTG_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) + +#define STM32_OTG_DFIFO_DEP0_OFFSET 0x1000 /* 0x1000-0x1ffc Device IN/OUT Endpoint 0 DFIFO Write/Read Access */ +#define STM32_OTG_DFIFO_HCH0_OFFSET 0x1000 /* 0x1000-0x1ffc Host OUT/IN Channel 0 DFIFO Read/Write Access */ + +#define STM32_OTG_DFIFO_DEP1_OFFSET 0x2000 /* 0x2000-0x2ffc Device IN/OUT Endpoint 1 DFIFO Write/Read Access */ +#define STM32_OTG_DFIFO_HCH1_OFFSET 0x2000 /* 0x2000-0x2ffc Host OUT/IN Channel 1 DFIFO Read/Write Access */ + +#define STM32_OTG_DFIFO_DEP2_OFFSET 0x3000 /* 0x3000-0x3ffc Device IN/OUT Endpoint 2 DFIFO Write/Read Access */ +#define STM32_OTG_DFIFO_HCH2_OFFSET 0x3000 /* 0x3000-0x3ffc Host OUT/IN Channel 2 DFIFO Read/Write Access */ + +#define STM32_OTG_DFIFO_DEP3_OFFSET 0x4000 /* 0x4000-0x4ffc Device IN/OUT Endpoint 3 DFIFO Write/Read Access */ +#define STM32_OTG_DFIFO_HCH3_OFFSET 0x4000 /* 0x4000-0x4ffc Host OUT/IN Channel 3 DFIFO Read/Write Access */ + +/* Register Addresses *******************************************************************************/ + +#define STM32_OTG_GOTGCTL (STM32_OTG_BASE+STM32_OTG_GOTGCTL_OFFSET) +#define STM32_OTG_GOTGINT (STM32_OTG_BASE+STM32_OTG_GOTGINT_OFFSET) +#define STM32_OTG_GAHBCFG (STM32_OTG_BASE+STM32_OTG_GAHBCFG_OFFSET) +#define STM32_OTG_GUSBCFG (STM32_OTG_BASE+STM32_OTG_GUSBCFG_OFFSET) +#define STM32_OTG_GRSTCTL (STM32_OTG_BASE+STM32_OTG_GRSTCTL_OFFSET) +#define STM32_OTG_GINTSTS (STM32_OTG_BASE+STM32_OTG_GINTSTS_OFFSET) +#define STM32_OTG_GINTMSK (STM32_OTG_BASE+STM32_OTG_GINTMSK_OFFSET) +#define STM32_OTG_GRXSTSR (STM32_OTG_BASE+STM32_OTG_GRXSTSR_OFFSET) +#define STM32_OTG_GRXSTSP (STM32_OTG_BASE+STM32_OTG_GRXSTSP_OFFSET) +#define STM32_OTG_GRXFSIZ (STM32_OTG_BASE+STM32_OTG_GRXFSIZ_OFFSET) +#define STM32_OTG_HNPTXFSIZ (STM32_OTG_BASE+STM32_OTG_HNPTXFSIZ_OFFSET) +#define STM32_OTG_DIEPTXF0 (STM32_OTG_BASE+STM32_OTG_DIEPTXF0_OFFSET) +#define STM32_OTG_HNPTXSTS (STM32_OTG_BASE+STM32_OTG_HNPTXSTS_OFFSET) +#define STM32_OTG_GCCFG (STM32_OTG_BASE+STM32_OTG_GCCFG_OFFSET) +#define STM32_OTG_CID (STM32_OTG_BASE+STM32_OTG_CID_OFFSET) +#define STM32_OTG_HPTXFSIZ (STM32_OTG_BASE+STM32_OTG_HPTXFSIZ_OFFSET) + +#define STM32_OTG_DIEPTXF(n) (STM32_OTG_BASE+STM32_OTG_DIEPTXF_OFFSET(n)) +#define STM32_OTG_DIEPTXF1 (STM32_OTG_BASE+STM32_OTG_DIEPTXF1_OFFSET) +#define STM32_OTG_DIEPTXF2 (STM32_OTG_BASE+STM32_OTG_DIEPTXF2_OFFSET) +#define STM32_OTG_DIEPTXF3 (STM32_OTG_BASE+STM32_OTG_DIEPTXF3_OFFSET) + +/* Host-mode control and status registers */ + +#define STM32_OTG_HCFG (STM32_OTG_BASE+STM32_OTG_HCFG_OFFSET) +#define STM32_OTG_HFIR (STM32_OTG_BASE+STM32_OTG_HFIR_OFFSET) +#define STM32_OTG_HFNUM (STM32_OTG_BASE+STM32_OTG_HFNUM_OFFSET) +#define STM32_OTG_HPTXSTS (STM32_OTG_BASE+STM32_OTG_HPTXSTS_OFFSET) +#define STM32_OTG_HAINT (STM32_OTG_BASE+STM32_OTG_HAINT_OFFSET) +#define STM32_OTG_HAINTMSK (STM32_OTG_BASE+STM32_OTG_HAINTMSK_OFFSET) +#define STM32_OTG_HPRT (STM32_OTG_BASE+STM32_OTG_HPRT_OFFSET) + +#define STM32_OTG_CHAN(n) (STM32_OTG_BASE+STM32_OTG_CHAN_OFFSET(n)) + +#define STM32_OTG_HCCHAR(n) (STM32_OTG_BASE+STM32_OTG_HCCHAR_OFFSET(n)) +#define STM32_OTG_HCCHAR0 (STM32_OTG_BASE+STM32_OTG_HCCHAR0_OFFSET) +#define STM32_OTG_HCCHAR1 (STM32_OTG_BASE+STM32_OTG_HCCHAR1_OFFSET) +#define STM32_OTG_HCCHAR2 (STM32_OTG_BASE+STM32_OTG_HCCHAR2_OFFSET) +#define STM32_OTG_HCCHAR3 (STM32_OTG_BASE+STM32_OTG_HCCHAR3_OFFSET) +#define STM32_OTG_HCCHAR4 (STM32_OTG_BASE+STM32_OTG_HCCHAR4_OFFSET) +#define STM32_OTG_HCCHAR5 (STM32_OTG_BASE+STM32_OTG_HCCHAR5_OFFSET) +#define STM32_OTG_HCCHAR6 (STM32_OTG_BASE+STM32_OTG_HCCHAR6_OFFSET) +#define STM32_OTG_HCCHAR7 (STM32_OTG_BASE+STM32_OTG_HCCHAR7_OFFSET) + +#define STM32_OTG_HCINT(n) (STM32_OTG_BASE+STM32_OTG_HCINT_OFFSET(n)) +#define STM32_OTG_HCINT0 (STM32_OTG_BASE+STM32_OTG_HCINT0_OFFSET) +#define STM32_OTG_HCINT1 (STM32_OTG_BASE+STM32_OTG_HCINT1_OFFSET) +#define STM32_OTG_HCINT2 (STM32_OTG_BASE+STM32_OTG_HCINT2_OFFSET) +#define STM32_OTG_HCINT3 (STM32_OTG_BASE+STM32_OTG_HCINT3_OFFSET) +#define STM32_OTG_HCINT4 (STM32_OTG_BASE+STM32_OTG_HCINT4_OFFSET) +#define STM32_OTG_HCINT5 (STM32_OTG_BASE+STM32_OTG_HCINT5_OFFSET) +#define STM32_OTG_HCINT6 (STM32_OTG_BASE+STM32_OTG_HCINT6_OFFSET) +#define STM32_OTG_HCINT7 (STM32_OTG_BASE+STM32_OTG_HCINT7_OFFSET) + +#define STM32_OTG_HCINTMSK(n) (STM32_OTG_BASE+STM32_OTG_HCINTMSK_OFFSET(n)) +#define STM32_OTG_HCINTMSK0 (STM32_OTG_BASE+STM32_OTG_HCINTMSK0_OFFSET) +#define STM32_OTG_HCINTMSK1 (STM32_OTG_BASE+STM32_OTG_HCINTMSK1_OFFSET) +#define STM32_OTG_HCINTMSK2 (STM32_OTG_BASE+STM32_OTG_HCINTMSK2_OFFSET) +#define STM32_OTG_HCINTMSK3 (STM32_OTG_BASE+STM32_OTG_HCINTMSK3_OFFSET) +#define STM32_OTG_HCINTMSK4 (STM32_OTG_BASE+STM32_OTG_HCINTMSK4_OFFSET) +#define STM32_OTG_HCINTMSK5 (STM32_OTG_BASE+STM32_OTG_HCINTMSK5_OFFSET) +#define STM32_OTG_HCINTMSK6 (STM32_OTG_BASE+STM32_OTG_HCINTMSK6_OFFSET) +#define STM32_OTG_HCINTMSK7 (STM32_OTG_BASE+STM32_OTG_HCINTMSK7_OFFSET)_ + +#define STM32_OTG_HCTSIZ(n) (STM32_OTG_BASE+STM32_OTG_HCTSIZ_OFFSET(n)) +#define STM32_OTG_HCTSIZ0 (STM32_OTG_BASE+STM32_OTG_HCTSIZ0_OFFSET) +#define STM32_OTG_HCTSIZ1 (STM32_OTG_BASE+STM32_OTG_HCTSIZ1_OFFSET) +#define STM32_OTG_HCTSIZ2 (STM32_OTG_BASE+STM32_OTG_HCTSIZ2_OFFSET) +#define STM32_OTG_HCTSIZ3 (STM32_OTG_BASE+STM32_OTG_HCTSIZ3_OFFSET) +#define STM32_OTG_HCTSIZ4 (STM32_OTG_BASE+STM32_OTG_HCTSIZ4_OFFSET) +#define STM32_OTG_HCTSIZ5 (STM32_OTG_BASE+STM32_OTG_HCTSIZ5_OFFSET) +#define STM32_OTG_HCTSIZ6 (STM32_OTG_BASE+STM32_OTG_HCTSIZ6_OFFSET) +#define STM32_OTG_HCTSIZ7 (STM32_OTG_BASE+STM32_OTG_HCTSIZ7_OFFSET) + +/* Device-mode control and status registers */ + +#define STM32_OTG_DCFG (STM32_OTG_BASE+STM32_OTG_DCFG_OFFSET) +#define STM32_OTG_DCTL (STM32_OTG_BASE+STM32_OTG_DCTL_OFFSET) +#define STM32_OTG_DSTS (STM32_OTG_BASE+STM32_OTG_DSTS_OFFSET) +#define STM32_OTG_DIEPMSK (STM32_OTG_BASE+STM32_OTG_DIEPMSK_OFFSET) +#define STM32_OTG_DOEPMSK (STM32_OTG_BASE+STM32_OTG_DOEPMSK_OFFSET) +#define STM32_OTG_DAINT (STM32_OTG_BASE+STM32_OTG_DAINT_OFFSET) +#define STM32_OTG_DAINTMSK (STM32_OTG_BASE+STM32_OTG_DAINTMSK_OFFSET) +#define STM32_OTG_DVBUSDIS (STM32_OTG_BASE+STM32_OTG_DVBUSDIS_OFFSET) +#define STM32_OTG_DVBUSPULSE (STM32_OTG_BASE+STM32_OTG_DVBUSPULSE_OFFSET) +#define STM32_OTG_DIEPEMPMSK (STM32_OTG_BASE+STM32_OTG_DIEPEMPMSK_OFFSET) + +#define STM32_OTG_DIEP(n) (STM32_OTG_BASE+STM32_OTG_DIEP_OFFSET(n)) + +#define STM32_OTG_DIEPCTL(n) (STM32_OTG_BASE+STM32_OTG_DIEPCTL_OFFSET(n)) +#define STM32_OTG_DIEPCTL0 (STM32_OTG_BASE+STM32_OTG_DIEPCTL0_OFFSET) +#define STM32_OTG_DIEPCTL1 (STM32_OTG_BASE+STM32_OTG_DIEPCTL1_OFFSET) +#define STM32_OTG_DIEPCTL2 (STM32_OTG_BASE+STM32_OTG_DIEPCTL2_OFFSET) +#define STM32_OTG_DIEPCTL3 (STM32_OTG_BASE+STM32_OTG_DIEPCTL3_OFFSET) + +#define STM32_OTG_DIEPINT(n) (STM32_OTG_BASE+STM32_OTG_DIEPINT_OFFSET(n)) +#define STM32_OTG_DIEPINT0 (STM32_OTG_BASE+STM32_OTG_DIEPINT0_OFFSET) +#define STM32_OTG_DIEPINT1 (STM32_OTG_BASE+STM32_OTG_DIEPINT1_OFFSET) +#define STM32_OTG_DIEPINT2 (STM32_OTG_BASE+STM32_OTG_DIEPINT2_OFFSET) +#define STM32_OTG_DIEPINT3 (STM32_OTG_BASE+STM32_OTG_DIEPINT3_OFFSET) + +#define STM32_OTG_DIEPTSIZ(n) (STM32_OTG_BASE+STM32_OTG_DIEPTSIZ_OFFSET(n)) +#define STM32_OTG_DIEPTSIZ0 (STM32_OTG_BASE+STM32_OTG_DIEPTSIZ0_OFFSET) +#define STM32_OTG_DIEPTSIZ1 (STM32_OTG_BASE+STM32_OTG_DIEPTSIZ1_OFFSET) +#define STM32_OTG_DIEPTSIZ2 (STM32_OTG_BASE+STM32_OTG_DIEPTSIZ2_OFFSET) +#define STM32_OTG_DIEPTSIZ3 (STM32_OTG_BASE+STM32_OTG_DIEPTSIZ3_OFFSET) + +#define STM32_OTG_DTXFSTS(n) (STM32_OTG_BASE+STM32_OTG_DTXFSTS_OFFSET(n)) +#define STM32_OTG_DTXFSTS0 (STM32_OTG_BASE+STM32_OTG_DTXFSTS0_OFFSET) +#define STM32_OTG_DTXFSTS1 (STM32_OTG_BASE+STM32_OTG_DTXFSTS1_OFFSET) +#define STM32_OTG_DTXFSTS2 (STM32_OTG_BASE+STM32_OTG_DTXFSTS2_OFFSET) +#define STM32_OTG_DTXFSTS3 (STM32_OTG_BASE+STM32_OTG_DTXFSTS3_OFFSET) + +#define STM32_OTG_DOEP(n) (STM32_OTG_BASE+STM32_OTG_DOEP_OFFSET(n)) + +#define STM32_OTG_DOEPCTL(n) (STM32_OTG_BASE+STM32_OTG_DOEPCTL_OFFSET(n)) +#define STM32_OTG_DOEPCTL0 (STM32_OTG_BASE+STM32_OTG_DOEPCTL0_OFFSET) +#define STM32_OTG_DOEPCTL1 (STM32_OTG_BASE+STM32_OTG_DOEPCTL1_OFFSET) +#define STM32_OTG_DOEPCTL2 (STM32_OTG_BASE+STM32_OTG_DOEPCTL2_OFFSET) +#define STM32_OTG_DOEPCTL3 (STM32_OTG_BASE+STM32_OTG_DOEPCTL3_OFFSET) + +#define STM32_OTG_DOEPINT(n) (STM32_OTG_BASE+STM32_OTG_DOEPINT_OFFSET(n)) +#define STM32_OTG_DOEPINT0 (STM32_OTG_BASE+STM32_OTG_DOEPINT0_OFFSET) +#define STM32_OTG_DOEPINT1 (STM32_OTG_BASE+STM32_OTG_DOEPINT1_OFFSET) +#define STM32_OTG_DOEPINT2 (STM32_OTG_BASE+STM32_OTG_DOEPINT2_OFFSET) +#define STM32_OTG_DOEPINT3 (STM32_OTG_BASE+STM32_OTG_DOEPINT3_OFFSET) + +#define STM32_OTG_DOEPTSIZ(n) (STM32_OTG_BASE+STM32_OTG_DOEPTSIZ_OFFSET(n)) +#define STM32_OTG_DOEPTSIZ0 (STM32_OTG_BASE+STM32_OTG_DOEPTSIZ0_OFFSET) +#define STM32_OTG_DOEPTSIZ1 (STM32_OTG_BASE+STM32_OTG_DOEPTSIZ1_OFFSET) +#define STM32_OTG_DOEPTSIZ2 (STM32_OTG_BASE+STM32_OTG_DOEPTSIZ2_OFFSET) +#define STM32_OTG_DOEPTSIZ3 (STM32_OTG_BASE+STM32_OTG_DOEPTSIZ3_OFFSET) + +/* Power and clock gating registers */ + +#define STM32_OTG_PCGCCTL (STM32_OTG_BASE+STM32_OTG_PCGCCTL_OFFSET) + +/* Data FIFO (DFIFO) access registers */ + +#define STM32_OTG_DFIFO_DEP(n) (STM32_OTG_BASE+STM32_OTG_DFIFO_DEP_OFFSET(n)) +#define STM32_OTG_DFIFO_HCH(n) (STM32_OTG_BASE+STM32_OTG_DFIFO_HCH_OFFSET(n)) + +#define STM32_OTG_DFIFO_DEP0 (STM32_OTG_BASE+STM32_OTG_DFIFO_DEP0_OFFSET) +#define STM32_OTG_DFIFO_HCH0 (STM32_OTG_BASE+STM32_OTG_DFIFO_HCH0_OFFSET) + +#define STM32_OTG_DFIFO_DEP1 (STM32_OTG_BASE+STM32_OTG_DFIFO_DEP1_OFFSET) +#define STM32_OTG_DFIFO_HCH1 (STM32_OTG_BASE+STM32_OTG_DFIFO_HCH1_OFFSET) + +#define STM32_OTG_DFIFO_DEP2 (STM32_OTG_BASE+STM32_OTG_DFIFO_DEP2_OFFSET) +#define STM32_OTG_DFIFO_HCH2 (STM32_OTG_BASE+STM32_OTG_DFIFO_HCH2_OFFSET) + +#define STM32_OTG_DFIFO_DEP3 (STM32_OTG_BASE+STM32_OTG_DFIFO_DEP3_OFFSET) +#define STM32_OTG_DFIFO_HCH3 (STM32_OTG_BASE+STM32_OTG_DFIFO_HCH3_OFFSET) + +/* Register Bitfield Definitions ********************************************************************/ +/* Core global control and status registers */ + +/* Control and status register */ + +#define OTG_GOTGCTL_SRQSCS (1 << 0) /* Bit 0: Session request success */ +#define OTG_GOTGCTL_SRQ (1 << 1) /* Bit 1: Session request */ +#define OTG_GOTGCTL_VBVALOEN (1 << 2) /* Bit 2: VBUS valid override enable */ +#define OTG_GOTGCTL_VBVALOVAL (1 << 3) /* Bit 3: VBUS valid override value */ +#define OTG_GOTGCTL_AVALOEN (1 << 4) /* Bit 4: A-peripheral session valid override enable */ +#define OTG_GOTGCTL_AVALOVAL (1 << 5) /* Bit 5: A-peripheral session valid override value */ +#define OTG_GOTGCTL_BVALOEN (1 << 6) /* Bit 6: B-peripheral session valid override enable */ +#define OTG_GOTGCTL_BVALOVAL (1 << 7) /* Bit 7: B-peripheral session valid override value */ +#define OTG_GOTGCTL_HNGSCS (1 << 8) /* Bit 8: Host negotiation success */ +#define OTG_GOTGCTL_HNPRQ (1 << 9) /* Bit 9: HNP request */ +#define OTG_GOTGCTL_HSHNPEN (1 << 10) /* Bit 10: host set HNP enable */ +#define OTG_GOTGCTL_DHNPEN (1 << 11) /* Bit 11: Device HNP enabled */ +#define OTG_GOTGCTL_EHEN (1 << 12) /* Bit 12: Embedded host enable */ + /* Bits 13-15: Reserved, must be kept at reset value */ +#define OTG_GOTGCTL_CIDSTS (1 << 16) /* Bit 16: Connector ID status */ +#define OTG_GOTGCTL_DBCT (1 << 17) /* Bit 17: Long/short debounce time */ +#define OTG_GOTGCTL_ASVLD (1 << 18) /* Bit 18: A-session valid */ +#define OTG_GOTGCTL_BSVLD (1 << 19) /* Bit 19: B-session valid */ +#define OTG_GOTGCTL_OTGVER (1 << 20) /* Bit 20: OTG version */ + /* Bits 21-31: Reserved, must be kept at reset value */ +/* Interrupt register */ + /* Bits 1:0 Reserved, must be kept at reset value */ +#define OTG_GOTGINT_SEDET (1 << 2) /* Bit 2: Session end detected */ + /* Bits 3-7: Reserved, must be kept at reset value */ +#define OTG_GOTGINT_SRSSCHG (1 << 8) /* Bit 8: Session request success status change */ +#define OTG_GOTGINT_HNSSCHG (1 << 9) /* Bit 9: Host negotiation success status change */ + /* Bits 16:10 Reserved, must be kept at reset value */ +#define OTG_GOTGINT_HNGDET (1 << 17) /* Bit 17: Host negotiation detected */ +#define OTG_GOTGINT_ADTOCHG (1 << 18) /* Bit 18: A-device timeout change */ +#define OTG_GOTGINT_DBCDNE (1 << 19) /* Bit 19: Debounce done */ +#define OTG_GOTGINT_IDCHNG (1 << 20) /* Bit 20: Change in ID pin input value */ + /* Bits 21-31: Reserved, must be kept at reset value */ + +/* AHB configuration register */ + +#define OTG_GAHBCFG_GINTMSK (1 << 0) /* Bit 0: Global interrupt mask */ + /* Bits 1-6: Reserved, must be kept at reset value */ +#define OTG_GAHBCFG_TXFELVL (1 << 7) /* Bit 7: TxFIFO empty level */ +#define OTG_GAHBCFG_PTXFELVL (1 << 8) /* Bit 8: Periodic TxFIFO empty level */ + /* Bits 20-31: Reserved, must be kept at reset value */ +/* USB configuration register */ + +#define OTG_GUSBCFG_TOCAL_SHIFT (0) /* Bits 0-2: FS timeout calibration */ +#define OTG_GUSBCFG_TOCAL_MASK (7 << OTG_GUSBCFG_TOCAL_SHIFT) + /* Bits 3-5: Reserved, must be kept at reset value */ +#define OTG_GUSBCFG_PHYSEL (1 << 6) /* Bit 6: Full Speed serial transceiver select */ + /* Bit 7: Reserved, must be kept at reset value */ +#define OTG_GUSBCFG_SRPCAP (1 << 8) /* Bit 8: SRP-capable */ +#define OTG_GUSBCFG_HNPCAP (1 << 9) /* Bit 9: HNP-capable */ +#define OTG_GUSBCFG_TRDT_SHIFT (10) /* Bits 10-13: USB turnaround time */ +#define OTG_GUSBCFG_TRDT_MASK (15 << OTG_GUSBCFG_TRDT_SHIFT) +# define OTG_GUSBCFG_TRDT(n) ((n) << OTG_GUSBCFG_TRDT_SHIFT) + /* Bits 14-28: Reserved, must be kept at reset value */ +#define OTG_GUSBCFG_FHMOD (1 << 29) /* Bit 29: Force host mode */ +#define OTG_GUSBCFG_FDMOD (1 << 30) /* Bit 30: Force device mode */ +#define OTG_GUSBCFG_CTXPKT (1 << 31) /* Bit 31: Corrupt Tx packet */ + /* Bits 20-31: Reserved, must be kept at reset value */ +/* Reset register */ + +#define OTG_GRSTCTL_CSRST (1 << 0) /* Bit 0: Core soft reset */ +#define OTG_GRSTCTL_HSRST (1 << 1) /* Bit 1: HCLK soft reset */ +#define OTG_GRSTCTL_FCRST (1 << 2) /* Bit 2: Host frame counter reset */ + /* Bit 3 Reserved, must be kept at reset value */ +#define OTG_GRSTCTL_RXFFLSH (1 << 4) /* Bit 4: RxFIFO flush */ +#define OTG_GRSTCTL_TXFFLSH (1 << 5) /* Bit 5: TxFIFO flush */ +#define OTG_GRSTCTL_TXFNUM_SHIFT (6) /* Bits 6-10: TxFIFO number */ +#define OTG_GRSTCTL_TXFNUM_MASK (31 << OTG_GRSTCTL_TXFNUM_SHIFT) +# define OTG_GRSTCTL_TXFNUM_HNONPER (0 << OTG_GRSTCTL_TXFNUM_SHIFT) /* Non-periodic TxFIFO flush in host mode */ +# define OTG_GRSTCTL_TXFNUM_HPER (1 << OTG_GRSTCTL_TXFNUM_SHIFT) /* Periodic TxFIFO flush in host mode */ +# define OTG_GRSTCTL_TXFNUM_HALL (16 << OTG_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in host mode.*/ +# define OTG_GRSTCTL_TXFNUM_D(n) ((n) << OTG_GRSTCTL_TXFNUM_SHIFT) /* TXFIFO n flush in device mode, n=0-15 */ +# define OTG_GRSTCTL_TXFNUM_DALL (16 << OTG_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in device mode.*/ + /* Bits 11-31: Reserved, must be kept at reset value */ +#define OTG_GRSTCTL_AHBIDL (1 << 31) /* Bit 31: AHB master idle */ + +/* Core interrupt and Interrupt mask registers */ + +#define OTG_GINTSTS_CMOD (1 << 0) /* Bit 0: Current mode of operation */ +# define OTG_GINTSTS_DEVMODE (0) +# define OTG_GINTSTS_HOSTMODE (OTG_GINTSTS_CMOD) +#define OTG_GINT_MMIS (1 << 1) /* Bit 1: Mode mismatch interrupt */ +#define OTG_GINT_OTG (1 << 2) /* Bit 2: OTG interrupt */ +#define OTG_GINT_SOF (1 << 3) /* Bit 3: Start of frame */ +#define OTG_GINT_RXFLVL (1 << 4) /* Bit 4: RxFIFO non-empty */ +#define OTG_GINT_NPTXFE (1 << 5) /* Bit 5: Non-periodic TxFIFO empty */ +#define OTG_GINT_GINAKEFF (1 << 6) /* Bit 6: Global IN non-periodic NAK effective */ +#define OTG_GINT_GONAKEFF (1 << 7) /* Bit 7: Global OUT NAK effective */ + /* Bits 8-9: Reserved, must be kept at reset value */ +#define OTG_GINT_ESUSP (1 << 10) /* Bit 10: Early suspend */ +#define OTG_GINT_USBSUSP (1 << 11) /* Bit 11: USB suspend */ +#define OTG_GINT_USBRST (1 << 12) /* Bit 12: USB reset */ +#define OTG_GINT_ENUMDNE (1 << 13) /* Bit 13: Enumeration done */ +#define OTG_GINT_ISOODRP (1 << 14) /* Bit 14: Isochronous OUT packet dropped interrupt */ +#define OTG_GINT_EOPF (1 << 15) /* Bit 15: End of periodic frame interrupt */ + /* Bits 16 Reserved, must be kept at reset value */ +#define OTG_GINTMSK_EPMISM (1 << 17) /* Bit 17: Endpoint mismatch interrupt mask */ +#define OTG_GINT_IEP (1 << 18) /* Bit 18: IN endpoint interrupt */ +#define OTG_GINT_OEP (1 << 19) /* Bit 19: OUT endpoint interrupt */ +#define OTG_GINT_IISOIXFR (1 << 20) /* Bit 20: Incomplete isochronous IN transfer */ +#define OTG_GINT_IISOOXFR (1 << 21) /* Bit 21: Incomplete isochronous OUT transfer (device) */ +#define OTG_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */ + /* Bit 22: Reserved, must be kept at reset value */ +#define OTG_GINT_RSTDET (1 << 23) /* Bit 23: Reset detected interrupt */ +#define OTG_GINT_HPRT (1 << 24) /* Bit 24: Host port interrupt */ +#define OTG_GINT_HC (1 << 25) /* Bit 25: Host channels interrupt */ +#define OTG_GINT_PTXFE (1 << 26) /* Bit 26: Periodic TxFIFO empty */ +#define OTG_GINT_LPMINT (1 << 27) /* Bit 27: LPM interrupt */ +#define OTG_GINT_CIDSCHG (1 << 28) /* Bit 28: Connector ID status change */ +#define OTG_GINT_DISC (1 << 29) /* Bit 29: Disconnect detected interrupt */ +#define OTG_GINT_SRQ (1 << 30) /* Bit 30: Session request/new session detected interrupt */ +#define OTG_GINT_WKUP (1 << 31) /* Bit 31: Resume/remote wakeup detected interrupt */ + +/* Receive status debug read/OTG status read and pop registers (host mode) */ + +#define OTG_GRXSTSH_CHNUM_SHIFT (0) /* Bits 0-3: Channel number */ +#define OTG_GRXSTSH_CHNUM_MASK (15 << OTG_GRXSTSH_CHNUM_SHIFT) +#define OTG_GRXSTSH_BCNT_SHIFT (4) /* Bits 4-14: Byte count */ +#define OTG_GRXSTSH_BCNT_MASK (0x7ff << OTG_GRXSTSH_BCNT_SHIFT) +#define OTG_GRXSTSH_DPID_SHIFT (15) /* Bits 15-16: Data PID */ +#define OTG_GRXSTSH_DPID_MASK (3 << OTG_GRXSTSH_DPID_SHIFT) +# define OTG_GRXSTSH_DPID_DATA0 (0 << OTG_GRXSTSH_DPID_SHIFT) +# define OTG_GRXSTSH_DPID_DATA2 (1 << OTG_GRXSTSH_DPID_SHIFT) +# define OTG_GRXSTSH_DPID_DATA1 (2 << OTG_GRXSTSH_DPID_SHIFT) +# define OTG_GRXSTSH_DPID_MDATA (3 << OTG_GRXSTSH_DPID_SHIFT) +#define OTG_GRXSTSH_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */ +#define OTG_GRXSTSH_PKTSTS_MASK (15 << OTG_GRXSTSH_PKTSTS_SHIFT) +# define OTG_GRXSTSH_PKTSTS_INRECVD (2 << OTG_GRXSTSH_PKTSTS_SHIFT) /* IN data packet received */ +# define OTG_GRXSTSH_PKTSTS_INDONE (3 << OTG_GRXSTSH_PKTSTS_SHIFT) /* IN transfer completed */ +# define OTG_GRXSTSH_PKTSTS_DTOGERR (5 << OTG_GRXSTSH_PKTSTS_SHIFT) /* Data toggle error */ +# define OTG_GRXSTSH_PKTSTS_HALTED (7 << OTG_GRXSTSH_PKTSTS_SHIFT) /* Channel halted */ + /* Bits 21-31: Reserved, must be kept at reset value */ +/* Receive status debug read/OTG status read and pop registers (device mode) */ + +#define OTG_GRXSTSD_EPNUM_SHIFT (0) /* Bits 0-3: Endpoint number */ +#define OTG_GRXSTSD_EPNUM_MASK (15 << OTG_GRXSTSD_EPNUM_SHIFT) +#define OTG_GRXSTSD_BCNT_SHIFT (4) /* Bits 4-14: Byte count */ +#define OTG_GRXSTSD_BCNT_MASK (0x7ff << OTG_GRXSTSD_BCNT_SHIFT) +#define OTG_GRXSTSD_DPID_SHIFT (15) /* Bits 15-16: Data PID */ +#define OTG_GRXSTSD_DPID_MASK (3 << OTG_GRXSTSD_DPID_SHIFT) +# define OTG_GRXSTSD_DPID_DATA0 (0 << OTG_GRXSTSD_DPID_SHIFT) +# define OTG_GRXSTSD_DPID_DATA2 (1 << OTG_GRXSTSD_DPID_SHIFT) +# define OTG_GRXSTSD_DPID_DATA1 (2 << OTG_GRXSTSD_DPID_SHIFT) +# define OTG_GRXSTSD_DPID_MDATA (3 << OTG_GRXSTSD_DPID_SHIFT) +#define OTG_GRXSTSD_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */ +#define OTG_GRXSTSD_PKTSTS_MASK (15 << OTG_GRXSTSD_PKTSTS_SHIFT) +# define OTG_GRXSTSD_PKTSTS_OUTNAK (1 << OTG_GRXSTSD_PKTSTS_SHIFT) /* Global OUT NAK */ +# define OTG_GRXSTSD_PKTSTS_OUTRECVD (2 << OTG_GRXSTSD_PKTSTS_SHIFT) /* OUT data packet received */ +# define OTG_GRXSTSD_PKTSTS_OUTDONE (3 << OTG_GRXSTSD_PKTSTS_SHIFT) /* OUT transfer completed */ +# define OTG_GRXSTSD_PKTSTS_SETUPDONE (4 << OTG_GRXSTSD_PKTSTS_SHIFT) /* SETUP transaction completed */ +# define OTG_GRXSTSD_PKTSTS_SETUPRECVD (6 << OTG_GRXSTSD_PKTSTS_SHIFT) /* SETUP data packet received */ +#define OTG_GRXSTSD_FRMNUM_SHIFT (21) /* Bits 21-24: Frame number */ +#define OTG_GRXSTSD_FRMNUM_MASK (15 << OTG_GRXSTSD_FRMNUM_SHIFT) + /* Bits 25-31: Reserved, must be kept at reset value */ +/* Receive FIFO size register */ + +#define OTG_GRXFSIZ_MASK (0xffff) + +/* Host non-periodic transmit FIFO size register */ + +#define OTG_HNPTXFSIZ_NPTXFSA_SHIFT (0) /* Bits 0-15: Non-periodic transmit RAM start address */ +#define OTG_HNPTXFSIZ_NPTXFSA_MASK (0xffff << OTG_HNPTXFSIZ_NPTXFSA_SHIFT) +#define OTG_HNPTXFSIZ_NPTXFD_SHIFT (16) /* Bits 16-31: Non-periodic TxFIFO depth */ +#define OTG_HNPTXFSIZ_NPTXFD_MASK (0xffff << OTG_HNPTXFSIZ_NPTXFD_SHIFT) +# define OTG_HNPTXFSIZ_NPTXFD_MIN (16 << OTG_HNPTXFSIZ_NPTXFD_SHIFT) +# define OTG_HNPTXFSIZ_NPTXFD_MAX (256 << OTG_HNPTXFSIZ_NPTXFD_SHIFT) + +/* Endpoint 0 Transmit FIFO size */ + +#define OTG_DIEPTXF0_TX0FD_SHIFT (0) /* Bits 0-15: Endpoint 0 transmit RAM start address */ +#define OTG_DIEPTXF0_TX0FD_MASK (0xffff << OTG_DIEPTXF0_TX0FD_SHIFT) +#define OTG_DIEPTXF0_TX0FSA_SHIFT (16) /* Bits 16-31: Endpoint 0 TxFIFO depth */ +#define OTG_DIEPTXF0_TX0FSA_MASK (0xffff << OTG_DIEPTXF0_TX0FSA_SHIFT) +# define OTG_DIEPTXF0_TX0FSA_MIN (16 << OTG_DIEPTXF0_TX0FSA_SHIFT) +# define OTG_DIEPTXF0_TX0FSA_MAX (256 << OTG_DIEPTXF0_TX0FSA_SHIFT) + +/* Non-periodic transmit FIFO/queue status register */ + +#define OTG_HNPTXSTS_NPTXFSAV_SHIFT (0) /* Bits 0-15: Non-periodic TxFIFO space available */ +#define OTG_HNPTXSTS_NPTXFSAV_MASK (0xffff << OTG_HNPTXSTS_NPTXFSAV_SHIFT) +# define OTG_HNPTXSTS_NPTXFSAV_FULL (0 << OTG_HNPTXSTS_NPTXFSAV_SHIFT) +#define OTG_HNPTXSTS_NPTQXSAV_SHIFT (16) /* Bits 16-23: Non-periodic transmit request queue space available */ +#define OTG_HNPTXSTS_NPTQXSAV_MASK (0xff << OTG_HNPTXSTS_NPTQXSAV_SHIFT) +# define OTG_HNPTXSTS_NPTQXSAV_FULL (0 << OTG_HNPTXSTS_NPTQXSAV_SHIFT) +#define OTG_HNPTXSTS_NPTXQTOP_SHIFT (24) /* Bits 24-30: Top of the non-periodic transmit request queue */ +#define OTG_HNPTXSTS_NPTXQTOP_MASK (0x7f << OTG_HNPTXSTS_NPTXQTOP_SHIFT) +# define OTG_HNPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */ +# define OTG_HNPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Status */ +# define OTG_HNPTXSTS_TYPE_MASK (3 << OTG_HNPTXSTS_TYPE_SHIFT) +# define OTG_HNPTXSTS_TYPE_INOUT (0 << OTG_HNPTXSTS_TYPE_SHIFT) /* IN/OUT token */ +# define OTG_HNPTXSTS_TYPE_ZLP (1 << OTG_HNPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet (device IN/host OUT) */ +# define OTG_HNPTXSTS_TYPE_HALT (3 << OTG_HNPTXSTS_TYPE_SHIFT) /* Channel halt command */ +# define OTG_HNPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */ +# define OTG_HNPTXSTS_CHNUM_MASK (15 << OTG_HNPTXSTS_CHNUM_SHIFT) +# define OTG_HNPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */ +# define OTG_HNPTXSTS_EPNUM_MASK (15 << OTG_HNPTXSTS_EPNUM_SHIFT) + /* Bit 31 Reserved, must be kept at reset value */ +/* General core configuration register */ + /* Bits 0-15: Reserved, must be kept at reset value */ +#define OTG_GCCFG_PWRDWN (1 << 16) /* Bit 16: Power down */ + /* Bit 17 Reserved, must be kept at reset value */ +#define OTG_GCCFG_VBDEN (1 << 21) /* Bit 21: USB VBUS detection enable */ + /* Bits 22-31: Reserved, must be kept at reset value */ +/* Core ID register (32-bit product ID) */ + +/* Host periodic transmit FIFO size register */ + +#define OTG_HPTXFSIZ_PTXSA_SHIFT (0) /* Bits 0-15: Host periodic TxFIFO start address */ +#define OTG_HPTXFSIZ_PTXSA_MASK (0xffff << OTG_HPTXFSIZ_PTXSA_SHIFT) +#define OTG_HPTXFSIZ_PTXFD_SHIFT (16) /* Bits 16-31: Host periodic TxFIFO depth */ +#define OTG_HPTXFSIZ_PTXFD_MASK (0xffff << OTG_HPTXFSIZ_PTXFD_SHIFT) + +/* Device IN endpoint transmit FIFOn size register */ + +#define OTG_DIEPTXF_INEPTXSA_SHIFT (0) /* Bits 0-15: IN endpoint FIFOx transmit RAM start address */ +#define OTG_DIEPTXF_INEPTXSA_MASK (0xffff << OTG_DIEPTXF_INEPTXSA_SHIFT) +#define OTG_DIEPTXF_INEPTXFD_SHIFT (16) /* Bits 16-31: IN endpoint TxFIFO depth */ +#define OTG_DIEPTXF_INEPTXFD_MASK (0xffff << OTG_DIEPTXF_INEPTXFD_SHIFT) +# define OTG_DIEPTXF_INEPTXFD_MIN (16 << OTG_DIEPTXF_INEPTXFD_MASK) + +/* Host-mode control and status registers */ + +/* Host configuration register */ + +#define OTG_HCFG_FSLSPCS_SHIFT (0) /* Bits 0-1: FS/LS PHY clock select */ +#define OTG_HCFG_FSLSPCS_MASK (3 << OTG_HCFG_FSLSPCS_SHIFT) +# define OTG_HCFG_FSLSPCS_FS48MHz (1 << OTG_HCFG_FSLSPCS_SHIFT) /* FS host mode, PHY clock is running at 48 MHz */ +# define OTG_HCFG_FSLSPCS_LS48MHz (1 << OTG_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 48 MHz PHY clock frequency */ +# define OTG_HCFG_FSLSPCS_LS6MHz (2 << OTG_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 6 MHz PHY clock frequency */ +#define OTG_HCFG_FSLSS (1 << 2) /* Bit 2: FS- and LS-only support */ + /* Bits 31:3 Reserved, must be kept at reset value */ +/* Host frame interval register */ + +#define OTG_HFIR_MASK (0xffff) + +/* Host frame number/frame time remaining register */ + +#define OTG_HFNUM_FRNUM_SHIFT (0) /* Bits 0-15: Frame number */ +#define OTG_HFNUM_FRNUM_MASK (0xffff << OTG_HFNUM_FRNUM_SHIFT) +#define OTG_HFNUM_FTREM_SHIFT (16) /* Bits 16-31: Frame time remaining */ +#define OTG_HFNUM_FTREM_MASK (0xffff << OTG_HFNUM_FTREM_SHIFT) + +/* Host periodic transmit FIFO/queue status register */ + +#define OTG_HPTXSTS_PTXFSAVL_SHIFT (0) /* Bits 0-15: Periodic transmit data FIFO space available */ +#define OTG_HPTXSTS_PTXFSAVL_MASK (0xffff << OTG_HPTXSTS_PTXFSAVL_SHIFT) +# define OTG_HPTXSTS_PTXFSAVL_FULL (0 << OTG_HPTXSTS_PTXFSAVL_SHIFT) +#define OTG_HPTXSTS_PTXQSAV_SHIFT (16) /* Bits 16-23: Periodic transmit request queue space available */ +#define OTG_HPTXSTS_PTXQSAV_MASK (0xff << OTG_HPTXSTS_PTXQSAV_SHIFT) +# define OTG_HPTXSTS_PTXQSAV_FULL (0 << OTG_HPTXSTS_PTXQSAV_SHIFT) +#define OTG_HPTXSTS_PTXQTOP_SHIFT (24) /* Bits 24-31: Top of the periodic transmit request queue */ +#define OTG_HPTXSTS_PTXQTOP_MASK (0x7f << OTG_HPTXSTS_PTXQTOP_SHIFT) +# define OTG_HPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */ +# define OTG_HPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Type */ +# define OTG_HPTXSTS_TYPE_MASK (3 << OTG_HPTXSTS_TYPE_SHIFT) +# define OTG_HPTXSTS_TYPE_INOUT (0 << OTG_HPTXSTS_TYPE_SHIFT) /* IN/OUT token */ +# define OTG_HPTXSTS_TYPE_ZLP (1 << OTG_HPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet */ +# define OTG_HPTXSTS_TYPE_HALT (3 << OTG_HPTXSTS_TYPE_SHIFT) /* Disable channel command */ +# define OTG_HPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */ +# define OTG_HPTXSTS_EPNUM_MASK (15 << OTG_HPTXSTS_EPNUM_SHIFT) +# define OTG_HPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */ +# define OTG_HPTXSTS_CHNUM_MASK (15 << OTG_HPTXSTS_CHNUM_SHIFT) +# define OTG_HPTXSTS_ODD (1 << 24) /* Bit 31: Send in odd (vs even) frame */ + +/* Host all channels interrupt and all channels interrupt mask registers */ + +#define OTG_HAINT(n) (1 << (n)) /* Bits 15:0 HAINTM: Channel interrupt */ + +/* Host port control and status register */ + +#define OTG_HPRT_PCSTS (1 << 0) /* Bit 0: Port connect status */ +#define OTG_HPRT_PCDET (1 << 1) /* Bit 1: Port connect detected */ +#define OTG_HPRT_PENA (1 << 2) /* Bit 2: Port enable */ +#define OTG_HPRT_PENCHNG (1 << 3) /* Bit 3: Port enable/disable change */ +#define OTG_HPRT_POCA (1 << 4) /* Bit 4: Port overcurrent active */ +#define OTG_HPRT_POCCHNG (1 << 5) /* Bit 5: Port overcurrent change */ +#define OTG_HPRT_PRES (1 << 6) /* Bit 6: Port resume */ +#define OTG_HPRT_PSUSP (1 << 7) /* Bit 7: Port suspend */ +#define OTG_HPRT_PRST (1 << 8) /* Bit 8: Port reset */ + /* Bit 9: Reserved, must be kept at reset value */ +#define OTG_HPRT_PLSTS_SHIFT (10) /* Bits 10-11: Port line status */ +#define OTG_HPRT_PLSTS_MASK (3 << OTG_HPRT_PLSTS_SHIFT) +# define OTG_HPRT_PLSTS_DP (1 << 10) /* Bit 10: Logic level of OTG_FS_FS_DP */ +# define OTG_HPRT_PLSTS_DM (1 << 11) /* Bit 11: Logic level of OTG_FS_FS_DM */ +#define OTG_HPRT_PPWR (1 << 12) /* Bit 12: Port power */ +#define OTG_HPRT_PTCTL_SHIFT (13) /* Bits 13-16: Port test control */ +#define OTG_HPRT_PTCTL_MASK (15 << OTG_HPRT_PTCTL_SHIFT) +# define OTG_HPRT_PTCTL_DISABLED (0 << OTG_HPRT_PTCTL_SHIFT) /* Test mode disabled */ +# define OTG_HPRT_PTCTL_J (1 << OTG_HPRT_PTCTL_SHIFT) /* Test_J mode */ +# define OTG_HPRT_PTCTL_L (2 << OTG_HPRT_PTCTL_SHIFT) /* Test_K mode */ +# define OTG_HPRT_PTCTL_SE0_NAK (3 << OTG_HPRT_PTCTL_SHIFT) /* Test_SE0_NAK mode */ +# define OTG_HPRT_PTCTL_PACKET (4 << OTG_HPRT_PTCTL_SHIFT) /* Test_Packet mode */ +# define OTG_HPRT_PTCTL_FORCE (5 << OTG_HPRT_PTCTL_SHIFT) /* Test_Force_Enable */ +#define OTG_HPRT_PSPD_SHIFT (17) /* Bits 17-18: Port speed */ +#define OTG_HPRT_PSPD_MASK (3 << OTG_HPRT_PSPD_SHIFT) +# define OTG_HPRT_PSPD_FS (1 << OTG_HPRT_PSPD_SHIFT) /* Full speed */ +# define OTG_HPRT_PSPD_LS (2 << OTG_HPRT_PSPD_SHIFT) /* Low speed */ + /* Bits 19-31: Reserved, must be kept at reset value */ + +/* Host channel-n characteristics register */ + +#define OTG_HCCHAR_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ +#define OTG_HCCHAR_MPSIZ_MASK (0x7ff << OTG_HCCHAR_MPSIZ_SHIFT) +#define OTG_HCCHAR_EPNUM_SHIFT (11) /* Bits 11-14: Endpoint number */ +#define OTG_HCCHAR_EPNUM_MASK (15 << OTG_HCCHAR_EPNUM_SHIFT) +#define OTG_HCCHAR_EPDIR (1 << 15) /* Bit 15: Endpoint direction */ +# define OTG_HCCHAR_EPDIR_OUT (0) +# define OTG_HCCHAR_EPDIR_IN OTG_HCCHAR_EPDIR + /* Bit 16 Reserved, must be kept at reset value */ +#define OTG_HCCHAR_LSDEV (1 << 17) /* Bit 17: Low-speed device */ +#define OTG_HCCHAR_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTG_HCCHAR_EPTYP_MASK (3 << OTG_HCCHAR_EPTYP_SHIFT) +# define OTG_HCCHAR_EPTYP_CTRL (0 << OTG_HCCHAR_EPTYP_SHIFT) /* Control */ +# define OTG_HCCHAR_EPTYP_ISOC (1 << OTG_HCCHAR_EPTYP_SHIFT) /* Isochronous */ +# define OTG_HCCHAR_EPTYP_BULK (2 << OTG_HCCHAR_EPTYP_SHIFT) /* Bulk */ +# define OTG_HCCHAR_EPTYP_INTR (3 << OTG_HCCHAR_EPTYP_SHIFT) /* Interrupt */ +#define OTG_HCCHAR_MCNT_SHIFT (20) /* Bits 20-21: Multicount */ +#define OTG_HCCHAR_MCNT_MASK (3 << OTG_HCCHAR_MCNT_SHIFT) +#define OTG_HCCHAR_DAD_SHIFT (22) /* Bits 22-28: Device address */ +#define OTG_HCCHAR_DAD_MASK (0x7f << OTG_HCCHAR_DAD_SHIFT) +#define OTG_HCCHAR_ODDFRM (1 << 29) /* Bit 29: Odd frame */ +#define OTG_HCCHAR_CHDIS (1 << 30) /* Bit 30: Channel disable */ +#define OTG_HCCHAR_CHENA (1 << 31) /* Bit 31: Channel enable */ + +/* Host channel-n interrupt and Host channel-0 interrupt mask registers */ + +#define OTG_HCINT_XFRC (1 << 0) /* Bit 0: Transfer completed */ +#define OTG_HCINT_CHH (1 << 1) /* Bit 1: Channel halted */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTG_HCINT_STALL (1 << 3) /* Bit 3: STALL response received interrupt */ +#define OTG_HCINT_NAK (1 << 4) /* Bit 4: NAK response received interrupt */ +#define OTG_HCINT_ACK (1 << 5) /* Bit 5: ACK response received/transmitted interrupt */ +#define OTG_HCINT_NYET (1 << 6) /* Bit 6: Response received interrupt */ +#define OTG_HCINT_TXERR (1 << 7) /* Bit 7: Transaction error */ +#define OTG_HCINT_BBERR (1 << 8) /* Bit 8: Babble error */ +#define OTG_HCINT_FRMOR (1 << 9) /* Bit 9: Frame overrun */ +#define OTG_HCINT_DTERR (1 << 10) /* Bit 10: Data toggle error */ + /* Bits 11-31 Reserved, must be kept at reset value */ +/* Host channel-n interrupt register */ + +#define OTG_HCTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ +#define OTG_HCTSIZ_XFRSIZ_MASK (0x7ffff << OTG_HCTSIZ_XFRSIZ_SHIFT) +#define OTG_HCTSIZ_PKTCNT_SHIFT (19) /* Bits 19-28: Packet count */ +#define OTG_HCTSIZ_PKTCNT_MASK (0x3ff << OTG_HCTSIZ_PKTCNT_SHIFT) +#define OTG_HCTSIZ_DPID_SHIFT (29) /* Bits 29-30: Data PID */ +#define OTG_HCTSIZ_DPID_MASK (3 << OTG_HCTSIZ_DPID_SHIFT) +# define OTG_HCTSIZ_DPID_DATA0 (0 << OTG_HCTSIZ_DPID_SHIFT) +# define OTG_HCTSIZ_DPID_DATA2 (1 << OTG_HCTSIZ_DPID_SHIFT) +# define OTG_HCTSIZ_DPID_DATA1 (2 << OTG_HCTSIZ_DPID_SHIFT) +# define OTG_HCTSIZ_DPID_MDATA (3 << OTG_HCTSIZ_DPID_SHIFT) /* Non-control */ +# define OTG_HCTSIZ_PID_SETUP (3 << OTG_HCTSIZ_DPID_SHIFT) /* Control */ + /* Bit 31 Reserved, must be kept at reset value */ +/* Device-mode control and status registers */ + +/* Device configuration register */ + +#define OTG_DCFG_DSPD_SHIFT (0) /* Bits 0-1: Device speed */ +#define OTG_DCFG_DSPD_MASK (3 << OTG_DCFG_DSPD_SHIFT) +# define OTG_DCFG_DSPD_FS (3 << OTG_DCFG_DSPD_SHIFT) /* Full speed */ +#define OTG_DCFG_NZLSOHSK (1 << 2) /* Bit 2: Non-zero-length status OUT handshake */ + /* Bit 3: Reserved, must be kept at reset value */ +#define OTG_DCFG_DAD_SHIFT (4) /* Bits 4-10: Device address */ +#define OTG_DCFG_DAD_MASK (0x7f << OTG_DCFG_DAD_SHIFT) +#define OTG_DCFG_PFIVL_SHIFT (11) /* Bits 11-12: Periodic frame interval */ +#define OTG_DCFG_PFIVL_MASK (3 << OTG_DCFG_PFIVL_SHIFT) +# define OTG_DCFG_PFIVL_80PCT (0 << OTG_DCFG_PFIVL_SHIFT) /* 80% of the frame interval */ +# define OTG_DCFG_PFIVL_85PCT (1 << OTG_DCFG_PFIVL_SHIFT) /* 85% of the frame interval */ +# define OTG_DCFG_PFIVL_90PCT (2 << OTG_DCFG_PFIVL_SHIFT) /* 90% of the frame interval */ +# define OTG_DCFG_PFIVL_95PCT (3 << OTG_DCFG_PFIVL_SHIFT) /* 95% of the frame interval */ + /* Bits 13-31 Reserved, must be kept at reset value */ +/* Device control register */ + +#define OTG_TESTMODE_DISABLED (0) /* Test mode disabled */ +#define OTG_TESTMODE_J (1) /* Test_J mode */ +#define OTG_TESTMODE_K (2) /* Test_K mode */ +#define OTG_TESTMODE_SE0_NAK (3) /* Test_SE0_NAK mode */ +#define OTG_TESTMODE_PACKET (4) /* Test_Packet mode */ +#define OTG_TESTMODE_FORCE (5) /* Test_Force_Enable */ + +#define OTG_DCTL_RWUSIG (1 << 0) /* Bit 0: Remote wakeup signaling */ +#define OTG_DCTL_SDIS (1 << 1) /* Bit 1: Soft disconnect */ +#define OTG_DCTL_GINSTS (1 << 2) /* Bit 2: Global IN NAK status */ +#define OTG_DCTL_GONSTS (1 << 3) /* Bit 3: Global OUT NAK status */ +#define OTG_DCTL_TCTL_SHIFT (4) /* Bits 4-6: Test control */ +#define OTG_DCTL_TCTL_MASK (7 << OTG_DCTL_TCTL_SHIFT) +# define OTG_DCTL_TCTL_DISABLED (0 << OTG_DCTL_TCTL_SHIFT) /* Test mode disabled */ +# define OTG_DCTL_TCTL_J (1 << OTG_DCTL_TCTL_SHIFT) /* Test_J mode */ +# define OTG_DCTL_TCTL_K (2 << OTG_DCTL_TCTL_SHIFT) /* Test_K mode */ +# define OTG_DCTL_TCTL_SE0_NAK (3 << OTG_DCTL_TCTL_SHIFT) /* Test_SE0_NAK mode */ +# define OTG_DCTL_TCTL_PACKET (4 << OTG_DCTL_TCTL_SHIFT) /* Test_Packet mode */ +# define OTG_DCTL_TCTL_FORCE (5 << OTG_DCTL_TCTL_SHIFT) /* Test_Force_Enable */ +#define OTG_DCTL_SGINAK (1 << 7) /* Bit 7: Set global IN NAK */ +#define OTG_DCTL_CGINAK (1 << 8) /* Bit 8: Clear global IN NAK */ +#define OTG_DCTL_SGONAK (1 << 9) /* Bit 9: Set global OUT NAK */ +#define OTG_DCTL_CGONAK (1 << 10) /* Bit 10: Clear global OUT NAK */ +#define OTG_DCTL_POPRGDNE (1 << 11) /* Bit 11: Power-on programming done */ + /* Bits 12-31: Reserved, must be kept at reset value */ +/* Device status register */ + +#define OTG_DSTS_SUSPSTS (1 << 0) /* Bit 0: Suspend status */ +#define OTG_DSTS_ENUMSPD_SHIFT (1) /* Bits 1-2: Enumerated speed */ +#define OTG_DSTS_ENUMSPD_MASK (3 << OTG_DSTS_ENUMSPD_SHIFT) +# define OTG_DSTS_ENUMSPD_FS (3 << OTG_DSTS_ENUMSPD_MASK) /* Full speed */ + /* Bits 4-7: Reserved, must be kept at reset value */ +#define OTG_DSTS_EERR (1 << 3) /* Bit 3: Erratic error */ +#define OTG_DSTS_SOFFN_SHIFT (8) /* Bits 8-21: Frame number of the received SOF */ +#define OTG_DSTS_SOFFN_MASK (0x3fff << OTG_DSTS_SOFFN_SHIFT) +#define OTG_DSTS_SOFFN0 (1 << 8) /* Bits 8: Frame number even/odd bit */ +#define OTG_DSTS_SOFFN_EVEN 0 +#define OTG_DSTS_SOFFN_ODD OTG_DSTS_SOFFN0 + /* Bits 22-31: Reserved, must be kept at reset value */ +/* Device IN endpoint common interrupt mask register */ + +#define OTG_DIEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */ +#define OTG_DIEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTG_DIEPMSK_TOM (1 << 3) /* Bit 3: Timeout condition mask (Non-isochronous endpoints) */ +#define OTG_DIEPMSK_ITTXFEMSK (1 << 4) /* Bit 4: IN token received when TxFIFO empty mask */ +#define OTG_DIEPMSK_INEPNMM (1 << 5) /* Bit 5: IN token received with EP mismatch mask */ +#define OTG_DIEPMSK_INEPNEM (1 << 6) /* Bit 6: IN endpoint NAK effective mask */ + /* Bits 7-31: Reserved, must be kept at reset value */ +/* Device OUT endpoint common interrupt mask register */ + +#define OTG_DOEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */ +#define OTG_DOEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTG_DOEPMSK_STUPM (1 << 3) /* Bit 3: SETUP phase done mask */ +#define OTG_DOEPMSK_OTEPDM (1 << 4) /* Bit 4: OUT token received when endpoint disabled mask */ + /* Bits 5-31: Reserved, must be kept at reset value */ +/* Device all endpoints interrupt and All endpoints interrupt mask registers */ + +#define OTG_DAINT_IEP_SHIFT (0) /* Bits 0-15: IN endpoint interrupt bits */ +#define OTG_DAINT_IEP_MASK (0xffff << OTG_DAINT_IEP_SHIFT) +# define OTG_DAINT_IEP(n) (1 << (n)) +#define OTG_DAINT_OEP_SHIFT (16) /* Bits 16-31: OUT endpoint interrupt bits */ +#define OTG_DAINT_OEP_MASK (0xffff << OTG_DAINT_OEP_SHIFT) +# define OTG_DAINT_OEP(n) (1 << ((n)+16)) + +/* Device VBUS discharge time register */ + +#define OTG_DVBUSDIS_MASK (0xffff) + +/* Device VBUS pulsing time register */ + +#define OTG_DVBUSPULSE_MASK (0xfff) + +/* Device IN endpoint FIFO empty interrupt mask register */ + +#define OTG_DIEPEMPMSK(n) (1 << (n)) + +/* Device control IN endpoint 0 control register */ + +#define OTG_DIEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */ +#define OTG_DIEPCTL0_MPSIZ_MASK (3 << OTG_DIEPCTL0_MPSIZ_SHIFT) +# define OTG_DIEPCTL0_MPSIZ_64 (0 << OTG_DIEPCTL0_MPSIZ_SHIFT) /* 64 bytes */ +# define OTG_DIEPCTL0_MPSIZ_32 (1 << OTG_DIEPCTL0_MPSIZ_SHIFT) /* 32 bytes */ +# define OTG_DIEPCTL0_MPSIZ_16 (2 << OTG_DIEPCTL0_MPSIZ_SHIFT) /* 16 bytes */ +# define OTG_DIEPCTL0_MPSIZ_8 (3 << OTG_DIEPCTL0_MPSIZ_SHIFT) /* 8 bytes */ + /* Bits 2-14: Reserved, must be kept at reset value */ +#define OTG_DIEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ + /* Bit 16: Reserved, must be kept at reset value */ +#define OTG_DIEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */ +#define OTG_DIEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTG_DIEPCTL0_EPTYP_MASK (3 << OTG_DIEPCTL0_EPTYP_SHIFT) +# define OTG_DIEPCTL0_EPTYP_CTRL (0 << OTG_DIEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */ + /* Bit 20: Reserved, must be kept at reset value */ +#define OTG_DIEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */ +#define OTG_DIEPCTL0_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */ +#define OTG_DIEPCTL0_TXFNUM_MASK (15 << OTG_DIEPCTL0_TXFNUM_SHIFT) +#define OTG_DIEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */ +#define OTG_DIEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */ + /* Bits 28-29: Reserved, must be kept at reset value */ +#define OTG_DIEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ +#define OTG_DIEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */ + +/* Device control IN endpoint n control register */ + +#define OTG_DIEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ +#define OTG_DIEPCTL_MPSIZ_MASK (0x7ff << OTG_DIEPCTL_MPSIZ_SHIFT) + /* Bits 11-14: Reserved, must be kept at reset value */ +#define OTG_DIEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ +#define OTG_DIEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame */ +# define OTG_DIEPCTL_EVEN (0) +# define OTG_DIEPCTL_ODD OTG_DIEPCTL_EONUM +# define OTG_DIEPCTL_DATA0 (0) +# define OTG_DIEPCTL_DATA1 OTG_DIEPCTL_EONUM +#define OTG_DIEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */ +#define OTG_DIEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTG_DIEPCTL_EPTYP_MASK (3 << OTG_DIEPCTL_EPTYP_SHIFT) +# define OTG_DIEPCTL_EPTYP_CTRL (0 << OTG_DIEPCTL_EPTYP_SHIFT) /* Control */ +# define OTG_DIEPCTL_EPTYP_ISOC (1 << OTG_DIEPCTL_EPTYP_SHIFT) /* Isochronous */ +# define OTG_DIEPCTL_EPTYP_BULK (2 << OTG_DIEPCTL_EPTYP_SHIFT) /* Bulk */ +# define OTG_DIEPCTL_EPTYP_INTR (3 << OTG_DIEPCTL_EPTYP_SHIFT) /* Interrupt */ + /* Bit 20: Reserved, must be kept at reset value */ +#define OTG_DIEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */ +#define OTG_DIEPCTL_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */ +#define OTG_DIEPCTL_TXFNUM_MASK (15 << OTG_DIEPCTL_TXFNUM_SHIFT) +#define OTG_DIEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */ +#define OTG_DIEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */ +#define OTG_DIEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */ +#define OTG_DIEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous)) */ +#define OTG_DIEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous) */ +#define OTG_DIEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ +#define OTG_DIEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */ + +/* Device endpoint-n interrupt register */ + +#define OTG_DIEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */ +#define OTG_DIEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTG_DIEPINT_TOC (1 << 3) /* Bit 3: Timeout condition */ +#define OTG_DIEPINT_ITTXFE (1 << 4) /* Bit 4: IN token received when TxFIFO is empty */ + /* Bit 5: Reserved, must be kept at reset value */ +#define OTG_DIEPINT_INEPNE (1 << 6) /* Bit 6: IN endpoint NAK effective */ +#define OTG_DIEPINT_TXFE (1 << 7) /* Bit 7: Transmit FIFO empty */ + /* Bits 8-31: Reserved, must be kept at reset value */ +/* Device IN endpoint 0 transfer size register */ + +#define OTG_DIEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */ +#define OTG_DIEPTSIZ0_XFRSIZ_MASK (0x7f << OTG_DIEPTSIZ0_XFRSIZ_SHIFT) + /* Bits 7-18: Reserved, must be kept at reset value */ +#define OTG_DIEPTSIZ0_PKTCNT_SHIFT (19) /* Bits 19-20: Packet count */ +#define OTG_DIEPTSIZ0_PKTCNT_MASK (3 << OTG_DIEPTSIZ0_PKTCNT_SHIFT) + /* Bits 21-31: Reserved, must be kept at reset value */ +/* Device IN endpoint n transfer size register */ + +#define OTG_DIEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ +#define OTG_DIEPTSIZ_XFRSIZ_MASK (0x7ffff << OTG_DIEPTSIZ_XFRSIZ_SHIFT) +#define OTG_DIEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */ +#define OTG_DIEPTSIZ_PKTCNT_MASK (0x3ff << OTG_DIEPTSIZ_PKTCNT_SHIFT) +#define OTG_DIEPTSIZ_MCNT_SHIFT (29) /* Bits 29-30: Multi count */ +#define OTG_DIEPTSIZ_MCNT_MASK (3 << OTG_DIEPTSIZ_MCNT_SHIFT) + /* Bit 31: Reserved, must be kept at reset value */ +/* Device OUT endpoint TxFIFO status register */ + +#define OTG_DTXFSTS_MASK (0xffff) + +/* Device OUT endpoint 0 control register */ + +#define OTG_DOEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */ +#define OTG_DOEPCTL0_MPSIZ_MASK (3 << OTG_DOEPCTL0_MPSIZ_SHIFT) +# define OTG_DOEPCTL0_MPSIZ_64 (0 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 64 bytes */ +# define OTG_DOEPCTL0_MPSIZ_32 (1 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 32 bytes */ +# define OTG_DOEPCTL0_MPSIZ_16 (2 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 16 bytes */ +# define OTG_DOEPCTL0_MPSIZ_8 (3 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 8 bytes */ + /* Bits 2-14: Reserved, must be kept at reset value */ +#define OTG_DOEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ + /* Bit 16: Reserved, must be kept at reset value */ +#define OTG_DOEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */ +#define OTG_DOEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTG_DOEPCTL0_EPTYP_MASK (3 << OTG_DOEPCTL0_EPTYP_SHIFT) +# define OTG_DOEPCTL0_EPTYP_CTRL (0 << OTG_DOEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */ +#define OTG_DOEPCTL0_SNPM (1 << 20) /* Bit 20: Snoop mode */ +#define OTG_DOEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */ + /* Bits 22-25: Reserved, must be kept at reset value */ +#define OTG_DOEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */ +#define OTG_DOEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */ + /* Bits 28-29: Reserved, must be kept at reset value */ +#define OTG_DOEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ +#define OTG_DOEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */ + +/* Device OUT endpoint n control register */ + +#define OTG_DOEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ +#define OTG_DOEPCTL_MPSIZ_MASK (0x7ff << OTG_DOEPCTL_MPSIZ_SHIFT) + /* Bits 11-14: Reserved, must be kept at reset value */ +#define OTG_DOEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ +#define OTG_DOEPCTL_DPID (1 << 16) /* Bit 16: Endpoint data PID (interrupt/buld) */ +# define OTG_DOEPCTL_DATA0 (0) +# define OTG_DOEPCTL_DATA1 OTG_DOEPCTL_DPID +#define OTG_DOEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame (isochronous) */ +# define OTG_DOEPCTL_EVEN (0) +# define OTG_DOEPCTL_ODD OTG_DOEPCTL_EONUM +#define OTG_DOEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */ +#define OTG_DOEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTG_DOEPCTL_EPTYP_MASK (3 << OTG_DOEPCTL_EPTYP_SHIFT) +# define OTG_DOEPCTL_EPTYP_CTRL (0 << OTG_DOEPCTL_EPTYP_SHIFT) /* Control */ +# define OTG_DOEPCTL_EPTYP_ISOC (1 << OTG_DOEPCTL_EPTYP_SHIFT) /* Isochronous */ +# define OTG_DOEPCTL_EPTYP_BULK (2 << OTG_DOEPCTL_EPTYP_SHIFT) /* Bulk */ +# define OTG_DOEPCTL_EPTYP_INTR (3 << OTG_DOEPCTL_EPTYP_SHIFT) /* Interrupt */ +#define OTG_DOEPCTL_SNPM (1 << 20) /* Bit 20: Snoop mode */ +#define OTG_DOEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */ + /* Bits 22-25: Reserved, must be kept at reset value */ +#define OTG_DOEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */ +#define OTG_DOEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */ +#define OTG_DOEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */ +#define OTG_DOEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous) */ +#define OTG_DOEPCTL_SD1PID (1 << 29) /* Bit 29: Set DATA1 PID (interrupt/bulk) */ +#define OTG_DOEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous */ +#define OTG_DOEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ +#define OTG_DOEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */ + +/* Device endpoint-n interrupt register */ + +#define OTG_DOEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */ +#define OTG_DOEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTG_DOEPINT_SETUP (1 << 3) /* Bit 3: SETUP phase done */ +#define OTG_DOEPINT_OTEPDIS (1 << 4) /* Bit 4: OUT token received when endpoint disabled */ + /* Bit 5: Reserved, must be kept at reset value */ +#define OTG_DOEPINT_B2BSTUP (1 << 6) /* Bit 6: Back-to-back SETUP packets received */ + /* Bits 7-31: Reserved, must be kept at reset value */ +/* Device OUT endpoint-0 transfer size register */ + +#define OTG_DOEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */ +#define OTG_DOEPTSIZ0_XFRSIZ_MASK (0x7f << OTG_DOEPTSIZ0_XFRSIZ_SHIFT) + /* Bits 7-18: Reserved, must be kept at reset value */ +#define OTG_DOEPTSIZ0_PKTCNT (1 << 19) /* Bit 19 PKTCNT: Packet count */ + /* Bits 20-28: Reserved, must be kept at reset value */ +#define OTG_DOEPTSIZ0_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */ +#define OTG_DOEPTSIZ0_STUPCNT_MASK (3 << OTG_DOEPTSIZ0_STUPCNT_SHIFT) + /* Bit 31: Reserved, must be kept at reset value */ +/* Device OUT endpoint-n transfer size register */ + +#define OTG_DOEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ +#define OTG_DOEPTSIZ_XFRSIZ_MASK (0x7ffff << OTG_DOEPTSIZ_XFRSIZ_SHIFT) +#define OTG_DOEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */ +#define OTG_DOEPTSIZ_PKTCNT_MASK (0x3ff << OTG_DOEPTSIZ_PKTCNT_SHIFT) +#define OTG_DOEPTSIZ_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */ +#define OTG_DOEPTSIZ_STUPCNT_MASK (3 << OTG_DOEPTSIZ_STUPCNT_SHIFT) +#define OTG_DOEPTSIZ_RXDPID_SHIFT (29) /* Bits 29-30: Received data PID */ +#define OTG_DOEPTSIZ_RXDPID_MASK (3 << OTG_DOEPTSIZ_RXDPID_SHIFT) +# define OTG_DOEPTSIZ_RXDPID_DATA0 (0 << OTG_DOEPTSIZ_RXDPID_SHIFT) +# define OTG_DOEPTSIZ_RXDPID_DATA2 (1 << OTG_DOEPTSIZ_RXDPID_SHIFT) +# define OTG_DOEPTSIZ_RXDPID_DATA1 (2 << OTG_DOEPTSIZ_RXDPID_SHIFT) +# define OTG_DOEPTSIZ_RXDPID_MDATA (3 << OTG_DOEPTSIZ_RXDPID_SHIFT) + /* Bit 31: Reserved, must be kept at reset value */ +/* Power and clock gating control register */ + +#define OTG_PCGCCTL_STPPCLK (1 << 0) /* Bit 0: Stop PHY clock */ +#define OTG_PCGCCTL_GATEHCLK (1 << 1) /* Bit 1: Gate HCLK */ + /* Bits 2-3: Reserved, must be kept at reset value */ +#define OTG_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */ + /* Bits 5-31: Reserved, must be kept at reset value */ + +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_OTG_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_sdmmc.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_sdmmc.h index e40990ec16..f710aed6d1 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_sdmmc.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_sdmmc.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32/chip/stm32_sdio.h + * arch/arm/src/stm32f7/chip/stm32_sdio.h * * Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c index bc34aa25aa..6bd842263d 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.c +++ b/arch/arm/src/stm32f7/stm32_i2c.c @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32/stm32f3xx_i2c.c + * arch/arm/src/stm32f7/stm32f3xx_i2c.c * STM32 F3 I2C Hardware Layer - Device Driver * * Copyright (C) 2011 Uros Platise. All rights reserved. diff --git a/arch/arm/src/stm32f7/stm32_otg.h b/arch/arm/src/stm32f7/stm32_otg.h new file mode 100644 index 0000000000..69def14608 --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_otg.h @@ -0,0 +1,139 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/stm32_otg.h + * + * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_STM32_OTG_H +#define __ARCH_ARM_SRC_STM32F7_STM32_OTG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + + +#include "chip/stm32_otg.h" + +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Configuration ********************************************************************/ + +#ifndef CONFIG_OTG_PRI +# define CONFIG_OTG_PRI NVIC_SYSH_PRIORITY_DEFAULT +#endif + +#if defined(CONFIG_STM32_OTGFS) +# define STM32_IRQ_OTG STM32_IRQ_OTGFS +# define STM32_OTG_BASE STM32_USBOTGFS_BASE +# define STM32_NENDPOINTS (6) /* ep0-5 x 2 for IN and OUT */ +#endif + +#if defined(CONFIG_STM32_OTGHS) +# define STM32_IRQ_OTG STM32_IRQ_OTGHS +# define STM32_OTG_BASE STM32_USBOTGHS_BASE +# define STM32_NENDPOINTS (8) /* ep0-7 x 2 for IN and OUT */ +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_otghost_initialize + * + * Description: + * Initialize USB host device controller hardware. + * + * Input Parameters: + * controller -- If the device supports more than USB host controller, then + * this identifies which controller is being initializeed. Normally, this + * is just zero. + * + * Returned Value: + * And instance of the USB host interface. The controlling task should + * use this interface to (1) call the wait() method to wait for a device + * to be connected, and (2) call the enumerate() method to bind the device + * to a class driver. + * + * Assumptions: + * - This function should called in the initialization sequence in order + * to initialize the USB device functionality. + * - Class drivers should be initialized prior to calling this function. + * Otherwise, there is a race condition if the device is already connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +struct usbhost_connection_s; +FAR struct usbhost_connection_s *stm32_otghost_initialize(int controller); +#endif + +/************************************************************************************ + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the OTG FS device driver + * is used. This function is called whenever the USB enters or leaves suspend + * mode. This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. + * + ************************************************************************************/ + +void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_STM32_OTGFS */ +#endif /* __ARCH_ARM_SRC_STM32F7_STM32_OTG_H */ + diff --git a/arch/arm/src/stm32f7/stm32_otgdev.c b/arch/arm/src/stm32f7/stm32_otgdev.c new file mode 100644 index 0000000000..e362ef2b45 --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_otgdev.c @@ -0,0 +1,5666 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/stm32_otgdev.c + * + * Copyright (C) 2012-2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "stm32_otg.h" +#include "up_arch.h" +#include "up_internal.h" + + +#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ***************************************************************/ + +#ifndef CONFIG_USBDEV_EP0_MAXSIZE +# define CONFIG_USBDEV_EP0_MAXSIZE 64 +#endif + +#ifndef CONFIG_USBDEV_SETUP_MAXDATASIZE +# define CONFIG_USBDEV_SETUP_MAXDATASIZE CONFIG_USBDEV_EP0_MAXSIZE +#endif + +#ifndef CONFIG_USBDEV_MAXPOWER +# define CONFIG_USBDEV_MAXPOWER 100 /* mA */ +#endif + +/* There is 1.25Kb of FIFO memory. The default partitions this memory + * so that there is a TxFIFO allocated for each endpoint and with more + * memory provided for the common RxFIFO. A more knowledge-able + * configuration would not allocate any TxFIFO space to OUT endpoints. + */ + +#ifndef CONFIG_USBDEV_RXFIFO_SIZE +# define CONFIG_USBDEV_RXFIFO_SIZE 512 +#endif + +#ifndef CONFIG_USBDEV_EP0_TXFIFO_SIZE +# define CONFIG_USBDEV_EP0_TXFIFO_SIZE 192 +#endif + +#ifndef CONFIG_USBDEV_EP1_TXFIFO_SIZE +# define CONFIG_USBDEV_EP1_TXFIFO_SIZE 192 +#endif + +#ifndef CONFIG_USBDEV_EP2_TXFIFO_SIZE +# define CONFIG_USBDEV_EP2_TXFIFO_SIZE 192 +#endif + +#ifndef CONFIG_USBDEV_EP3_TXFIFO_SIZE +# define CONFIG_USBDEV_EP3_TXFIFO_SIZE 192 +#endif + +#if (CONFIG_USBDEV_RXFIFO_SIZE + CONFIG_USBDEV_EP0_TXFIFO_SIZE + \ + CONFIG_USBDEV_EP2_TXFIFO_SIZE + CONFIG_USBDEV_EP3_TXFIFO_SIZE) > 1280 +# error "FIFO allocations exceed FIFO memory size" +#endif + +/* The actual FIFO addresses that we use must be aligned to 4-byte boundaries; + * FIFO sizes must be provided in units of 32-bit words. + */ + +#define STM32_RXFIFO_BYTES ((CONFIG_USBDEV_RXFIFO_SIZE + 3) & ~3) +#define STM32_RXFIFO_WORDS ((CONFIG_USBDEV_RXFIFO_SIZE + 3) >> 2) + +#define STM32_EP0_TXFIFO_BYTES ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP0_TXFIFO_WORDS ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) >> 2) + +#if STM32_EP0_TXFIFO_WORDS < 16 || STM32_EP0_TXFIFO_WORDS > 256 +# error "CONFIG_USBDEV_EP0_TXFIFO_SIZE is out of range" +#endif + +#define STM32_EP1_TXFIFO_BYTES ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP1_TXFIFO_WORDS ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) >> 2) + +#if STM32_EP1_TXFIFO_WORDS < 16 +# error "CONFIG_USBDEV_EP1_TXFIFO_SIZE is out of range" +#endif + +#define STM32_EP2_TXFIFO_BYTES ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP2_TXFIFO_WORDS ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) >> 2) + +#if STM32_EP2_TXFIFO_WORDS < 16 +# error "CONFIG_USBDEV_EP2_TXFIFO_SIZE is out of range" +#endif + +#define STM32_EP3_TXFIFO_BYTES ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP3_TXFIFO_WORDS ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) >> 2) + +#if STM32_EP3_TXFIFO_WORDS < 16 +# error "CONFIG_USBDEV_EP3_TXFIFO_SIZE is out of range" +#endif + +/* Debug ***********************************************************************/ +/* Trace error codes */ + +#define STM32_TRACEERR_ALLOCFAIL 0x01 +#define STM32_TRACEERR_BADCLEARFEATURE 0x02 +#define STM32_TRACEERR_BADDEVGETSTATUS 0x03 +#define STM32_TRACEERR_BADEPNO 0x04 +#define STM32_TRACEERR_BADEPGETSTATUS 0x05 +#define STM32_TRACEERR_BADGETCONFIG 0x06 +#define STM32_TRACEERR_BADGETSETDESC 0x07 +#define STM32_TRACEERR_BADGETSTATUS 0x08 +#define STM32_TRACEERR_BADSETADDRESS 0x09 +#define STM32_TRACEERR_BADSETCONFIG 0x0a +#define STM32_TRACEERR_BADSETFEATURE 0x0b +#define STM32_TRACEERR_BADTESTMODE 0x0c +#define STM32_TRACEERR_BINDFAILED 0x0d +#define STM32_TRACEERR_DISPATCHSTALL 0x0e +#define STM32_TRACEERR_DRIVER 0x0f +#define STM32_TRACEERR_DRIVERREGISTERED 0x10 +#define STM32_TRACEERR_EP0NOSETUP 0x11 +#define STM32_TRACEERR_EP0SETUPSTALLED 0x12 +#define STM32_TRACEERR_EPINNULLPACKET 0x13 +#define STM32_TRACEERR_EPINUNEXPECTED 0x14 +#define STM32_TRACEERR_EPOUTNULLPACKET 0x15 +#define STM32_TRACEERR_EPOUTUNEXPECTED 0x16 +#define STM32_TRACEERR_INVALIDCTRLREQ 0x17 +#define STM32_TRACEERR_INVALIDPARMS 0x18 +#define STM32_TRACEERR_IRQREGISTRATION 0x19 +#define STM32_TRACEERR_NOEP 0x1a +#define STM32_TRACEERR_NOTCONFIGURED 0x1b +#define STM32_TRACEERR_EPOUTQEMPTY 0x1c +#define STM32_TRACEERR_EPINREQEMPTY 0x1d +#define STM32_TRACEERR_NOOUTSETUP 0x1e +#define STM32_TRACEERR_POLLTIMEOUT 0x1f + +/* Trace interrupt codes */ + +#define STM32_TRACEINTID_USB 1 /* USB Interrupt entry/exit */ +#define STM32_TRACEINTID_INTPENDING 2 /* On each pass through the loop */ + +#define STM32_TRACEINTID_EPOUT (10 + 0) /* First level interrupt decode */ +#define STM32_TRACEINTID_EPIN (10 + 1) +#define STM32_TRACEINTID_MISMATCH (10 + 2) +#define STM32_TRACEINTID_WAKEUP (10 + 3) +#define STM32_TRACEINTID_SUSPEND (10 + 4) +#define STM32_TRACEINTID_SOF (10 + 5) +#define STM32_TRACEINTID_RXFIFO (10 + 6) +#define STM32_TRACEINTID_DEVRESET (10 + 7) +#define STM32_TRACEINTID_ENUMDNE (10 + 8) +#define STM32_TRACEINTID_IISOIXFR (10 + 9) +#define STM32_TRACEINTID_IISOOXFR (10 + 10) +#define STM32_TRACEINTID_SRQ (10 + 11) +#define STM32_TRACEINTID_OTG (10 + 12) + +#define STM32_TRACEINTID_EPOUT_XFRC (40 + 0) /* EPOUT second level decode */ +#define STM32_TRACEINTID_EPOUT_EPDISD (40 + 1) +#define STM32_TRACEINTID_EPOUT_SETUP (40 + 2) +#define STM32_TRACEINTID_DISPATCH (40 + 3) + +#define STM32_TRACEINTID_GETSTATUS (50 + 0) /* EPOUT third level decode */ +#define STM32_TRACEINTID_EPGETSTATUS (50 + 1) +#define STM32_TRACEINTID_DEVGETSTATUS (50 + 2) +#define STM32_TRACEINTID_IFGETSTATUS (50 + 3) +#define STM32_TRACEINTID_CLEARFEATURE (50 + 4) +#define STM32_TRACEINTID_SETFEATURE (50 + 5) +#define STM32_TRACEINTID_SETADDRESS (50 + 6) +#define STM32_TRACEINTID_GETSETDESC (50 + 7) +#define STM32_TRACEINTID_GETCONFIG (50 + 8) +#define STM32_TRACEINTID_SETCONFIG (50 + 9) +#define STM32_TRACEINTID_GETSETIF (50 + 10) +#define STM32_TRACEINTID_SYNCHFRAME (50 + 11) + +#define STM32_TRACEINTID_EPIN_XFRC (70 + 0) /* EPIN second level decode */ +#define STM32_TRACEINTID_EPIN_TOC (70 + 1) +#define STM32_TRACEINTID_EPIN_ITTXFE (70 + 2) +#define STM32_TRACEINTID_EPIN_EPDISD (70 + 3) +#define STM32_TRACEINTID_EPIN_TXFE (70 + 4) + +#define STM32_TRACEINTID_EPIN_EMPWAIT (80 + 0) /* EPIN second level decode */ + +#define STM32_TRACEINTID_OUTNAK (90 + 0) /* RXFLVL second level decode */ +#define STM32_TRACEINTID_OUTRECVD (90 + 1) +#define STM32_TRACEINTID_OUTDONE (90 + 2) +#define STM32_TRACEINTID_SETUPDONE (90 + 3) +#define STM32_TRACEINTID_SETUPRECVD (90 + 4) + +/* Endpoints ******************************************************************/ + + +/* Odd physical endpoint numbers are IN; even are OUT */ + +#define STM32_EPPHYIN2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_IN) +#define STM32_EPPHYOUT2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_OUT) + +/* Endpoint 0 */ + +#define EP0 (0) + +/* The set of all enpoints available to the class implementation (1-3) */ + +#define STM32_EP_AVAILABLE (0x0e) /* All available endpoints */ + +/* Maximum packet sizes for full speed endpoints */ + +#define STM32_MAXPACKET (64) /* Max packet size (1-64) */ + +/* Delays **********************************************************************/ + +#define STM32_READY_DELAY 200000 +#define STM32_FLUSH_DELAY 200000 + +/* Request queue operations ****************************************************/ + +#define stm32_rqempty(ep) ((ep)->head == NULL) +#define stm32_rqpeek(ep) ((ep)->head) + +/* Standard stuff **************************************************************/ + +#ifndef MIN +# define MIN(a,b) ((a) < (b) ? (a) : (b)) +#endif + +#ifndef MAX +# define MAX(a,b) ((a) > (b) ? (a) : (b)) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Overall device state */ + +enum stm32_devstate_e +{ + DEVSTATE_DEFAULT = 0, /* Power-up, unconfigured state. This state simply + * means that the device is not yet been given an + * address. + * SET: At initialization, uninitialization, + * reset, and whenever the device address + * is set to zero + * TESTED: Never + */ + DEVSTATE_ADDRESSED, /* Device address has been assigned, not no + * configuration has yet been selected. + * SET: When either a non-zero device address + * is first assigned or when the device + * is unconfigured (with configuration == 0) + * TESTED: never + */ + DEVSTATE_CONFIGURED, /* Address assigned and configured: + * SET: When the device has been addressed and + * an non-zero configuration has been selected. + * TESTED: In many places to assure that the USB device + * has been properly configured by the host. + */ +}; + +/* Endpoint 0 states */ + +enum stm32_ep0state_e +{ + EP0STATE_IDLE = 0, /* Idle State, leave on receiving a SETUP packet or + * epsubmit: + * SET: In stm32_epin() and stm32_epout() when + * we revert from request processing to + * SETUP processing. + * TESTED: Never + */ + EP0STATE_SETUP_OUT, /* OUT SETUP packet received. Waiting for the DATA + * OUT phase of SETUP Packet to complete before + * processing a SETUP command (without a USB request): + * SET: Set in stm32_rxinterrupt() when SETUP OUT + * packet is received. + * TESTED: In stm32_ep0out_receive() + */ + EP0STATE_SETUP_READY, /* IN SETUP packet received -OR- OUT SETUP packet and + * accompanying data have been received. Processing + * of SETUP command will happen soon. + * SET: (1) stm32_ep0out_receive() when the OUT + * SETUP data phase completes, or (2) + * stm32_rxinterrupt() when an IN SETUP is + * packet received. + * TESTED: Tested in stm32_epout_interrupt() when + * SETUP phase is done to see if the SETUP + * command is ready to be processed. Also + * tested in stm32_ep0out_setup() just to + * double-check that we have a SETUP request + * and any accompanying data. + */ + EP0STATE_SETUP_PROCESS, /* SETUP Packet is being processed by stm32_ep0out_setup(): + * SET: When SETUP packet received in EP0 OUT + * TESTED: Never + */ + EP0STATE_SETUPRESPONSE, /* Short SETUP response write (without a USB request): + * SET: When SETUP response is sent by + * stm32_ep0in_setupresponse() + * TESTED: Never + */ + EP0STATE_DATA_IN, /* Waiting for data out stage (with a USB request): + * SET: In stm32_epin_request() when a write + * request is processed on EP0. + * TESTED: In stm32_epin() to see if we should + * revert to SETUP processing. + */ + EP0STATE_DATA_OUT /* Waiting for data in phase to complete ( with a + * USB request) + * SET: In stm32_epout_request() when a read + * request is processed on EP0. + * TESTED: In stm32_epout() to see if we should + * revert to SETUP processing + */ +}; + +/* Parsed control request */ + +struct stm32_ctrlreq_s +{ + uint8_t type; + uint8_t req; + uint16_t value; + uint16_t index; + uint16_t len; +}; + +/* A container for a request so that the request may be retained in a list */ + +struct stm32_req_s +{ + struct usbdev_req_s req; /* Standard USB request */ + struct stm32_req_s *flink; /* Supports a singly linked list */ +}; + +/* This is the internal representation of an endpoint */ + +struct stm32_ep_s +{ + /* Common endpoint fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbdev_ep_s + * to struct stm32_ep_s. + */ + + struct usbdev_ep_s ep; /* Standard endpoint structure */ + + /* STM32-specific fields */ + + struct stm32_usbdev_s *dev; /* Reference to private driver data */ + struct stm32_req_s *head; /* Request list for this endpoint */ + struct stm32_req_s *tail; + uint8_t epphy; /* Physical EP address */ + uint8_t eptype:2; /* Endpoint type */ + uint8_t active:1; /* 1: A request is being processed */ + uint8_t stalled:1; /* 1: Endpoint is stalled */ + uint8_t isin:1; /* 1: IN Endpoint */ + uint8_t odd:1; /* 1: Odd frame */ + uint8_t zlp:1; /* 1: Transmit a zero-length-packet (IN EPs only) */ +}; + +/* This structure retains the state of the USB device controller */ + +struct stm32_usbdev_s +{ + /* Common device fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbdev_s + * to struct stm32_usbdev_s. + */ + + struct usbdev_s usbdev; + + /* The bound device class driver */ + + struct usbdevclass_driver_s *driver; + + /* STM32-specific fields */ + + uint8_t stalled:1; /* 1: Protocol stalled */ + uint8_t selfpowered:1; /* 1: Device is self powered */ + uint8_t addressed:1; /* 1: Peripheral address has been set */ + uint8_t configured:1; /* 1: Class driver has been configured */ + uint8_t wakeup:1; /* 1: Device remote wake-up */ + uint8_t dotest:1; /* 1: Test mode selected */ + + uint8_t devstate:4; /* See enum stm32_devstate_e */ + uint8_t ep0state:4; /* See enum stm32_ep0state_e */ + uint8_t testmode:4; /* Selected test mode */ + uint8_t epavail[2]; /* Bitset of available OUT/IN endpoints */ + + /* E0 SETUP data buffering. + * + * ctrlreq: + * The 8-byte SETUP request is received on the EP0 OUT endpoint and is + * saved. + * + * ep0data + * For OUT SETUP requests, the SETUP data phase must also complete before + * the SETUP command can be processed. The pack receipt logic will save + * the accompanying EP0 IN data in ep0data[] before the SETUP command is + * processed. + * + * For IN SETUP requests, the DATA phase will occur AFTER the SETUP + * control request is processed. In that case, ep0data[] may be used as + * the response buffer. + * + * ep0datlen + * Length of OUT DATA received in ep0data[] (Not used with OUT data) + */ + + struct usb_ctrlreq_s ctrlreq; + uint8_t ep0data[CONFIG_USBDEV_SETUP_MAXDATASIZE]; + uint16_t ep0datlen; + + /* The endpoint lists */ + + struct stm32_ep_s epin[STM32_NENDPOINTS]; + struct stm32_ep_s epout[STM32_NENDPOINTS]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register operations ********************************************************/ + +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +static uint32_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint32_t val, uint32_t addr); +#else +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(val,addr) putreg32(val,addr) +#endif + +/* Request queue operations ****************************************************/ + +static FAR struct stm32_req_s *stm32_req_remfirst(FAR struct stm32_ep_s *privep); +static bool stm32_req_addlast(FAR struct stm32_ep_s *privep, + FAR struct stm32_req_s *req); + +/* Low level data transfers and request operations *****************************/ +/* Special endpoint 0 data transfer logic */ + +static void stm32_ep0in_setupresponse(FAR struct stm32_usbdev_s *priv, + FAR uint8_t *data, uint32_t nbytes); +static inline void stm32_ep0in_transmitzlp(FAR struct stm32_usbdev_s *priv); +static void stm32_ep0in_activate(void); + +static void stm32_ep0out_ctrlsetup(FAR struct stm32_usbdev_s *priv); + +/* IN request and TxFIFO handling */ + +static void stm32_txfifo_write(FAR struct stm32_ep_s *privep, + FAR uint8_t *buf, int nbytes); +static void stm32_epin_transfer(FAR struct stm32_ep_s *privep, + FAR uint8_t *buf, int nbytes); +static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, + FAR struct stm32_ep_s *privep); + +/* OUT request and RxFIFO handling */ + +static void stm32_rxfifo_read(FAR struct stm32_ep_s *privep, + FAR uint8_t *dest, uint16_t len); +static void stm32_rxfifo_discard(FAR struct stm32_ep_s *privep, int len); +static void stm32_epout_complete(FAR struct stm32_usbdev_s *priv, + FAR struct stm32_ep_s *privep); +static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, int bcnt); +static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt); +static void stm32_epout_request(FAR struct stm32_usbdev_s *priv, + FAR struct stm32_ep_s *privep); + +/* General request handling */ + +static void stm32_ep_flush(FAR struct stm32_ep_s *privep); +static void stm32_req_complete(FAR struct stm32_ep_s *privep, + int16_t result); +static void stm32_req_cancel(FAR struct stm32_ep_s *privep, + int16_t status); + +/* Interrupt handling **********************************************************/ + +static struct stm32_ep_s *stm32_ep_findbyaddr(struct stm32_usbdev_s *priv, + uint16_t eplog); +static int stm32_req_dispatch(FAR struct stm32_usbdev_s *priv, + FAR const struct usb_ctrlreq_s *ctrl); +static void stm32_usbreset(FAR struct stm32_usbdev_s *priv); + +/* Second level OUT endpoint interrupt processing */ + +static inline void stm32_ep0out_testmode(FAR struct stm32_usbdev_s *priv, + uint16_t index); +static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, + FAR struct stm32_ctrlreq_s *ctrlreq); +static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv); +static inline void stm32_epout(FAR struct stm32_usbdev_s *priv, + uint8_t epno); +static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv); + +/* Second level IN endpoint interrupt processing */ + +static inline void stm32_epin_runtestmode(FAR struct stm32_usbdev_s *priv); +static inline void stm32_epin(FAR struct stm32_usbdev_s *priv, uint8_t epno); +static inline void stm32_epin_txfifoempty(FAR struct stm32_usbdev_s *priv, int epno); +static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv); + +/* Other second level interrupt processing */ + +static inline void stm32_resumeinterrupt(FAR struct stm32_usbdev_s *priv); +static inline void stm32_suspendinterrupt(FAR struct stm32_usbdev_s *priv); +static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv); +static inline void stm32_enuminterrupt(FAR struct stm32_usbdev_s *priv); +#ifdef CONFIG_USBDEV_ISOCHRONOUS +static inline void stm32_isocininterrupt(FAR struct stm32_usbdev_s *priv); +static inline void stm32_isocoutinterrupt(FAR struct stm32_usbdev_s *priv); +#endif +#ifdef CONFIG_USBDEV_VBUSSENSING +static inline void stm32_sessioninterrupt(FAR struct stm32_usbdev_s *priv); +static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv); +#endif + +/* First level interrupt processing */ + +static int stm32_usbinterrupt(int irq, FAR void *context); + +/* Endpoint operations *********************************************************/ +/* Global OUT NAK controls */ + +static void stm32_enablegonak(FAR struct stm32_ep_s *privep); +static void stm32_disablegonak(FAR struct stm32_ep_s *privep); + +/* Endpoint configuration */ + +static int stm32_epout_configure(FAR struct stm32_ep_s *privep, + uint8_t eptype, uint16_t maxpacket); +static int stm32_epin_configure(FAR struct stm32_ep_s *privep, + uint8_t eptype, uint16_t maxpacket); +static int stm32_ep_configure(FAR struct usbdev_ep_s *ep, + FAR const struct usb_epdesc_s *desc, bool last); +static void stm32_ep0_configure(FAR struct stm32_usbdev_s *priv); + +/* Endpoint disable */ + +static void stm32_epout_disable(FAR struct stm32_ep_s *privep); +static void stm32_epin_disable(FAR struct stm32_ep_s *privep); +static int stm32_ep_disable(FAR struct usbdev_ep_s *ep); + +/* Endpoint request management */ + +static FAR struct usbdev_req_s *stm32_ep_allocreq(FAR struct usbdev_ep_s *ep); +static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep, + FAR struct usbdev_req_s *); + +/* Endpoint buffer management */ + +#ifdef CONFIG_USBDEV_DMA +static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes); +static void stm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf); +#endif + +/* Endpoint request submission */ + +static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, + struct usbdev_req_s *req); + +/* Endpoint request cancellation */ + +static int stm32_ep_cancel(FAR struct usbdev_ep_s *ep, + struct usbdev_req_s *req); + +/* Stall handling */ + +static int stm32_epout_setstall(FAR struct stm32_ep_s *privep); +static int stm32_epin_setstall(FAR struct stm32_ep_s *privep); +static int stm32_ep_setstall(FAR struct stm32_ep_s *privep); +static int stm32_ep_clrstall(FAR struct stm32_ep_s *privep); +static int stm32_ep_stall(FAR struct usbdev_ep_s *ep, bool resume); +static void stm32_ep0_stall(FAR struct stm32_usbdev_s *priv); + +/* Endpoint allocation */ + +static FAR struct usbdev_ep_s *stm32_ep_alloc(FAR struct usbdev_s *dev, + uint8_t epno, bool in, uint8_t eptype); +static void stm32_ep_free(FAR struct usbdev_s *dev, + FAR struct usbdev_ep_s *ep); + +/* USB device controller operations ********************************************/ + +static int stm32_getframe(struct usbdev_s *dev); +static int stm32_wakeup(struct usbdev_s *dev); +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered); +static int stm32_pullup(struct usbdev_s *dev, bool enable); +static void stm32_setaddress(struct stm32_usbdev_s *priv, + uint16_t address); +static int stm32_txfifo_flush(uint32_t txfnum); +static int stm32_rxfifo_flush(void); + +/* Initialization **************************************************************/ + +static void stm32_swinitialize(FAR struct stm32_usbdev_s *priv); +static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ +/* Since there is only a single USB interface, all status information can be + * be simply retained in a single global instance. + */ + +static struct stm32_usbdev_s g_otghsdev; + +static const struct usbdev_epops_s g_epops = +{ + .configure = stm32_ep_configure, + .disable = stm32_ep_disable, + .allocreq = stm32_ep_allocreq, + .freereq = stm32_ep_freereq, +#ifdef CONFIG_USBDEV_DMA + .allocbuffer = stm32_ep_allocbuffer, + .freebuffer = stm32_ep_freebuffer, +#endif + .submit = stm32_ep_submit, + .cancel = stm32_ep_cancel, + .stall = stm32_ep_stall, +}; + +static const struct usbdev_ops_s g_devops = +{ + .allocep = stm32_ep_alloc, + .freeep = stm32_ep_free, + .getframe = stm32_getframe, + .wakeup = stm32_wakeup, + .selfpowered = stm32_selfpowered, + .pullup = stm32_pullup, +}; + +/* Device error strings that may be enabled for more descriptive USB trace + * output. + */ + +#ifdef CONFIG_USBDEV_TRACE_STRINGS +const struct trace_msg_t g_usb_trace_strings_deverror[] = +{ + TRACE_STR(STM32_TRACEERR_ALLOCFAIL ), + TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE ), + TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS ), + TRACE_STR(STM32_TRACEERR_BADEPNO ), + TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS ), + TRACE_STR(STM32_TRACEERR_BADGETCONFIG ), + TRACE_STR(STM32_TRACEERR_BADGETSETDESC ), + TRACE_STR(STM32_TRACEERR_BADGETSTATUS ), + TRACE_STR(STM32_TRACEERR_BADSETADDRESS ), + TRACE_STR(STM32_TRACEERR_BADSETCONFIG ), + TRACE_STR(STM32_TRACEERR_BADSETFEATURE ), + TRACE_STR(STM32_TRACEERR_BADTESTMODE ), + TRACE_STR(STM32_TRACEERR_BINDFAILED ), + TRACE_STR(STM32_TRACEERR_DISPATCHSTALL ), + TRACE_STR(STM32_TRACEERR_DRIVER ), + TRACE_STR(STM32_TRACEERR_DRIVERREGISTERED), + TRACE_STR(STM32_TRACEERR_EP0NOSETUP ), + TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED ), + TRACE_STR(STM32_TRACEERR_EPINNULLPACKET ), + TRACE_STR(STM32_TRACEERR_EPINUNEXPECTED ), + TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET ), + TRACE_STR(STM32_TRACEERR_EPOUTUNEXPECTED ), + TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ ), + TRACE_STR(STM32_TRACEERR_INVALIDPARMS ), + TRACE_STR(STM32_TRACEERR_IRQREGISTRATION ), + TRACE_STR(STM32_TRACEERR_NOEP ), + TRACE_STR(STM32_TRACEERR_NOTCONFIGURED ), + TRACE_STR(STM32_TRACEERR_EPOUTQEMPTY ), + TRACE_STR(STM32_TRACEERR_EPINREQEMPTY ), + TRACE_STR(STM32_TRACEERR_NOOUTSETUP ), + TRACE_STR(STM32_TRACEERR_POLLTIMEOUT ), + TRACE_STR_END +}; +#endif + +/* Interrupt event strings that may be enabled for more descriptive USB trace + * output. + */ + +#ifdef CONFIG_USBDEV_TRACE_STRINGS +const struct trace_msg_t g_usb_trace_strings_intdecode[] = +{ + TRACE_STR(STM32_TRACEINTID_USB ), + TRACE_STR(STM32_TRACEINTID_INTPENDING ), + TRACE_STR(STM32_TRACEINTID_EPOUT ), + TRACE_STR(STM32_TRACEINTID_EPIN ), + TRACE_STR(STM32_TRACEINTID_MISMATCH ), + TRACE_STR(STM32_TRACEINTID_WAKEUP ), + TRACE_STR(STM32_TRACEINTID_SUSPEND ), + TRACE_STR(STM32_TRACEINTID_SOF ), + TRACE_STR(STM32_TRACEINTID_RXFIFO ), + TRACE_STR(STM32_TRACEINTID_DEVRESET ), + TRACE_STR(STM32_TRACEINTID_ENUMDNE ), + TRACE_STR(STM32_TRACEINTID_IISOIXFR ), + TRACE_STR(STM32_TRACEINTID_IISOOXFR ), + TRACE_STR(STM32_TRACEINTID_SRQ ), + TRACE_STR(STM32_TRACEINTID_OTG ), + TRACE_STR(STM32_TRACEINTID_EPOUT_XFRC ), + TRACE_STR(STM32_TRACEINTID_EPOUT_EPDISD), + TRACE_STR(STM32_TRACEINTID_EPOUT_SETUP ), + TRACE_STR(STM32_TRACEINTID_DISPATCH ), + TRACE_STR(STM32_TRACEINTID_GETSTATUS ), + TRACE_STR(STM32_TRACEINTID_EPGETSTATUS ), + TRACE_STR(STM32_TRACEINTID_DEVGETSTATUS), + TRACE_STR(STM32_TRACEINTID_IFGETSTATUS ), + TRACE_STR(STM32_TRACEINTID_CLEARFEATURE), + TRACE_STR(STM32_TRACEINTID_SETFEATURE ), + TRACE_STR(STM32_TRACEINTID_SETADDRESS ), + TRACE_STR(STM32_TRACEINTID_GETSETDESC ), + TRACE_STR(STM32_TRACEINTID_GETCONFIG ), + TRACE_STR(STM32_TRACEINTID_SETCONFIG ), + TRACE_STR(STM32_TRACEINTID_GETSETIF ), + TRACE_STR(STM32_TRACEINTID_SYNCHFRAME ), + TRACE_STR(STM32_TRACEINTID_EPIN_XFRC ), + TRACE_STR(STM32_TRACEINTID_EPIN_TOC ), + TRACE_STR(STM32_TRACEINTID_EPIN_ITTXFE ), + TRACE_STR(STM32_TRACEINTID_EPIN_EPDISD ), + TRACE_STR(STM32_TRACEINTID_EPIN_TXFE ), + TRACE_STR(STM32_TRACEINTID_EPIN_EMPWAIT), + TRACE_STR(STM32_TRACEINTID_OUTNAK ), + TRACE_STR(STM32_TRACEINTID_OUTRECVD ), + TRACE_STR(STM32_TRACEINTID_OUTDONE ), + TRACE_STR(STM32_TRACEINTID_SETUPDONE ), + TRACE_STR(STM32_TRACEINTID_SETUPRECVD ), + TRACE_STR_END +}; +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_getreg + * + * Description: + * Get the contents of an STM32 register + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +static uint32_t stm32_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t preval = 0; + static uint32_t count = 0; + + /* Read the value from the register */ + + uint32_t val = getreg32(addr); + + /* Is this the same value that we read from the same register last time? Are + * we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + llerr("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + llerr("[repeats %d more times]\n", count-3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + llerr("%08x->%08x\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: stm32_putreg + * + * Description: + * Set the contents of an STM32 register to a value + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +static void stm32_putreg(uint32_t val, uint32_t addr) +{ + /* Show the register value being written */ + + llerr("%08x<-%08x\n", addr, val); + + /* Write the value */ + + putreg32(val, addr); +} +#endif + +/**************************************************************************** + * Name: stm32_req_remfirst + * + * Description: + * Remove a request from the head of an endpoint request queue + * + ****************************************************************************/ + +static FAR struct stm32_req_s *stm32_req_remfirst(FAR struct stm32_ep_s *privep) +{ + FAR struct stm32_req_s *ret = privep->head; + + if (ret) + { + privep->head = ret->flink; + if (!privep->head) + { + privep->tail = NULL; + } + + ret->flink = NULL; + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_req_addlast + * + * Description: + * Add a request to the end of an endpoint request queue + * + ****************************************************************************/ + +static bool stm32_req_addlast(FAR struct stm32_ep_s *privep, + FAR struct stm32_req_s *req) +{ + bool is_empty = !privep->head; + + req->flink = NULL; + if (is_empty) + { + privep->head = req; + privep->tail = req; + } + else + { + privep->tail->flink = req; + privep->tail = req; + } + return is_empty; +} + +/**************************************************************************** + * Name: stm32_ep0in_setupresponse + * + * Description: + * Schedule a short transfer on Endpoint 0 (IN or OUT) + * + ****************************************************************************/ + +static void stm32_ep0in_setupresponse(FAR struct stm32_usbdev_s *priv, + FAR uint8_t *buf, uint32_t nbytes) +{ + stm32_epin_transfer(&priv->epin[EP0], buf, nbytes); + priv->ep0state = EP0STATE_SETUPRESPONSE; + stm32_ep0out_ctrlsetup(priv); +} + +/**************************************************************************** + * Name: stm32_ep0in_transmitzlp + * + * Description: + * Send a zero length packet (ZLP) on endpoint 0 IN + * + ****************************************************************************/ + +static inline void stm32_ep0in_transmitzlp(FAR struct stm32_usbdev_s *priv) +{ + stm32_ep0in_setupresponse(priv, NULL, 0); +} + +/**************************************************************************** + * Name: stm32_ep0in_activate + * + * Description: + * Activate the endpoint 0 IN endpoint. + * + ****************************************************************************/ + +static void stm32_ep0in_activate(void) +{ + uint32_t regval; + + /* Set the max packet size of the IN EP. */ + + regval = stm32_getreg(STM32_OTG_DIEPCTL0); + regval &= ~OTG_DIEPCTL0_MPSIZ_MASK; + +#if CONFIG_USBDEV_EP0_MAXSIZE == 8 + regval |= OTG_DIEPCTL0_MPSIZ_8; +#elif CONFIG_USBDEV_EP0_MAXSIZE == 16 + regval |= OTG_DIEPCTL0_MPSIZ_16; +#elif CONFIG_USBDEV_EP0_MAXSIZE == 32 + regval |= OTG_DIEPCTL0_MPSIZ_32; +#elif CONFIG_USBDEV_EP0_MAXSIZE == 64 + regval |= OTG_DIEPCTL0_MPSIZ_64; +#else +# error "Unsupported value of CONFIG_USBDEV_EP0_MAXSIZE" +#endif + + stm32_putreg(regval, STM32_OTG_DIEPCTL0); + + /* Clear global IN NAK */ + + regval = stm32_getreg(STM32_OTG_DCTL); + regval |= OTG_DCTL_CGINAK; + stm32_putreg(regval, STM32_OTG_DCTL); +} + +/**************************************************************************** + * Name: stm32_ep0out_ctrlsetup + * + * Description: + * Setup to receive a SETUP packet. + * + ****************************************************************************/ + +static void stm32_ep0out_ctrlsetup(FAR struct stm32_usbdev_s *priv) +{ + uint32_t regval; + + /* Setup the hardware to perform the SETUP transfer */ + + regval = (USB_SIZEOF_CTRLREQ * 3 << OTG_DOEPTSIZ0_XFRSIZ_SHIFT) | + (OTG_DOEPTSIZ0_PKTCNT) | + (3 << OTG_DOEPTSIZ0_STUPCNT_SHIFT); + stm32_putreg(regval, STM32_OTG_DOEPTSIZ0); + + /* Then clear NAKing and enable the transfer */ + + regval = stm32_getreg(STM32_OTG_DOEPCTL0); + regval |= (OTG_DOEPCTL0_CNAK | OTG_DOEPCTL0_EPENA); + stm32_putreg(regval, STM32_OTG_DOEPCTL0); +} + +/**************************************************************************** + * Name: stm32_txfifo_write + * + * Description: + * Send data to the endpoint's TxFIFO. + * + ****************************************************************************/ + +static void stm32_txfifo_write(FAR struct stm32_ep_s *privep, + FAR uint8_t *buf, int nbytes) +{ + uint32_t regaddr; + uint32_t regval; + int nwords; + int i; + + /* Convert the number of bytes to words */ + + nwords = (nbytes + 3) >> 2; + + /* Get the TxFIFO for this endpoint (same as the endpoint number) */ + + regaddr = STM32_OTG_DFIFO_DEP(privep->epphy); + + /* Then transfer each word to the TxFIFO */ + + for (i = 0; i < nwords; i++) + { + /* Read four bytes from the source buffer (to avoid unaligned accesses) + * and pack these into one 32-bit word (little endian). + */ + + regval = (uint32_t)*buf++; + regval |= ((uint32_t)*buf++) << 8; + regval |= ((uint32_t)*buf++) << 16; + regval |= ((uint32_t)*buf++) << 24; + + /* Then write the packet data to the TxFIFO */ + + stm32_putreg(regval, regaddr); + } +} + +/**************************************************************************** + * Name: stm32_epin_transfer + * + * Description: + * Start the Tx data transfer + * + ****************************************************************************/ + +static void stm32_epin_transfer(FAR struct stm32_ep_s *privep, + FAR uint8_t *buf, int nbytes) +{ + uint32_t pktcnt; + uint32_t regval; + + /* Read the DIEPSIZx register */ + + regval = stm32_getreg(STM32_OTG_DIEPTSIZ(privep->epphy)); + + /* Clear the XFRSIZ, PKTCNT, and MCNT field of the DIEPSIZx register */ + + regval &= ~(OTG_DIEPTSIZ_XFRSIZ_MASK | OTG_DIEPTSIZ_PKTCNT_MASK | + OTG_DIEPTSIZ_MCNT_MASK); + + /* Are we sending a zero length packet (ZLP) */ + + if (nbytes == 0) + { + /* Yes.. leave the transfer size at zero and set the packet count to 1 */ + + pktcnt = 1; + } + else + { + /* No.. Program the transfer size and packet count . First calculate: + * + * xfrsize = The total number of bytes to be sent. + * pktcnt = the number of packets (of maxpacket bytes) required to + * perform the transfer. + */ + + pktcnt = ((uint32_t)nbytes + (privep->ep.maxpacket - 1)) / privep->ep.maxpacket; + } + + /* Set the XFRSIZ and PKTCNT */ + + regval |= (pktcnt << OTG_DIEPTSIZ_PKTCNT_SHIFT); + regval |= ((uint32_t)nbytes << OTG_DIEPTSIZ_XFRSIZ_SHIFT); + + /* If this is an isochronous endpoint, then set the multi-count field to + * the PKTCNT as well. + */ + + if (privep->eptype == USB_EP_ATTR_XFER_ISOC) + { + regval |= (pktcnt << OTG_DIEPTSIZ_MCNT_SHIFT); + } + + /* Save DIEPSIZx register value */ + + stm32_putreg(regval, STM32_OTG_DIEPTSIZ(privep->epphy)); + + /* Read the DIEPCTLx register */ + + regval = stm32_getreg(STM32_OTG_DIEPCTL(privep->epphy)); + + /* If this is an isochronous endpoint, then set the even/odd frame bit + * the DIEPCTLx register. + */ + + if (privep->eptype == USB_EP_ATTR_XFER_ISOC) + { + /* Check bit 0 of the frame number of the received SOF and set the + * even/odd frame to match. + */ + + uint32_t status = stm32_getreg(STM32_OTG_DSTS); + if ((status & OTG_DSTS_SOFFN0) == OTG_DSTS_SOFFN_EVEN) + { + regval |= OTG_DIEPCTL_SEVNFRM; + } + else + { + regval |= OTG_DIEPCTL_SODDFRM; + } + } + + /* EP enable, IN data in FIFO */ + + regval &= ~OTG_DIEPCTL_EPDIS; + regval |= (OTG_DIEPCTL_CNAK | OTG_DIEPCTL_EPENA); + stm32_putreg(regval, STM32_OTG_DIEPCTL(privep->epphy)); + + /* Transfer the data to the TxFIFO. At this point, the caller has already + * assured that there is sufficient space in the TxFIFO to hold the transfer + * we can just blindly continue. + */ + + stm32_txfifo_write(privep, buf, nbytes); +} + +/**************************************************************************** + * Name: stm32_epin_request + * + * Description: + * Begin or continue write request processing. + * + ****************************************************************************/ + +static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, + FAR struct stm32_ep_s *privep) +{ + struct stm32_req_s *privreq; + uint32_t regaddr; + uint32_t regval; + uint8_t *buf; + int nbytes; + int nwords; + int bytesleft; + + /* We get here in one of four possible ways. From three interrupting + * events: + * + * 1. From stm32_epin as part of the transfer complete interrupt processing + * This interrupt indicates that the last transfer has completed. + * 2. As part of the ITTXFE interrupt processing. That interrupt indicates + * that an IN token was received when the associated TxFIFO was empty. + * 3. From stm32_epin_txfifoempty as part of the TXFE interrupt processing. + * The TXFE interrupt is only enabled when the TxFIFO is full and the + * software must wait for space to become available in the TxFIFO. + * + * And this function may be called immediately when the write request is + * queue to start up the next transaction. + * + * 4. From stm32_ep_submit when a new write request is received WHILE the + * endpoint is not active (privep->active == false). + */ + + /* Check the request from the head of the endpoint request queue */ + + privreq = stm32_rqpeek(privep); + if (!privreq) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINREQEMPTY), privep->epphy); + + /* There is no TX transfer in progress and no new pending TX + * requests to send. To stop transmitting any data on a particular + * IN endpoint, the application must set the IN NAK bit. To set this + * bit, the following field must be programmed. + */ + + regaddr = STM32_OTG_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval |= OTG_DIEPCTL_SNAK; + stm32_putreg(regval, regaddr); + + /* The endpoint is no longer active */ + + privep->active = false; + return; + } + + ullinfo("EP%d req=%p: len=%d xfrd=%d zlp=%d\n", + privep->epphy, privreq, privreq->req.len, + privreq->req.xfrd, privep->zlp); + + /* Check for a special case: If we are just starting a request (xfrd==0) and + * the class driver is trying to send a zero-length packet (len==0). Then set + * the ZLP flag so that the packet will be sent. + */ + + if (privreq->req.len == 0) + { + /* The ZLP flag is set TRUE whenever we want to force the driver to + * send a zero-length-packet on the next pass through the loop (below). + * The flag is cleared whenever a packet is sent in the loop below. + */ + + privep->zlp = true; + } + + /* Add one more packet to the TxFIFO. We will wait for the transfer + * complete event before we add the next packet (or part of a packet + * to the TxFIFO). + * + * The documentation says that we can can multiple packets to the TxFIFO, + * but it seems that we need to get the transfer complete event before + * we can add the next (or maybe I have got something wrong?) + */ + +#if 0 + while (privreq->req.xfrd < privreq->req.len || privep->zlp) +#else + if (privreq->req.xfrd < privreq->req.len || privep->zlp) +#endif + { + /* Get the number of bytes left to be sent in the request */ + + bytesleft = privreq->req.len - privreq->req.xfrd; + nbytes = bytesleft; + + /* Assume no zero-length-packet on the next pass through this loop */ + + privep->zlp = false; + + /* Limit the size of the transfer to one full packet and handle + * zero-length packets (ZLPs). + */ + + if (nbytes > 0) + { + /* Either send the maxpacketsize or all of the remaining data in + * the request. + */ + + if (nbytes >= privep->ep.maxpacket) + { + nbytes = privep->ep.maxpacket; + + /* Handle the case where this packet is exactly the + * maxpacketsize. Do we need to send a zero-length packet + * in this case? + */ + + if (bytesleft == privep->ep.maxpacket && + (privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0) + { + /* The ZLP flag is set TRUE whenever we want to force + * the driver to send a zero-length-packet on the next + * pass through this loop. The flag is cleared (above) + * whenever we are committed to sending any packet and + * set here when we want to force one more pass through + * the loop. + */ + + privep->zlp = true; + } + } + } + + /* Get the transfer size in 32-bit words */ + + nwords = (nbytes + 3) >> 2; + + /* Get the number of 32-bit words available in the TxFIFO. The + * DXTFSTS indicates the amount of free space available in the + * endpoint TxFIFO. Values are in terms of 32-bit words: + * + * 0: Endpoint TxFIFO is full + * 1: 1 word available + * 2: 2 words available + * n: n words available + */ + + regaddr = STM32_OTG_DTXFSTS(privep->epphy); + + /* Check for space in the TxFIFO. If space in the TxFIFO is not + * available, then set up an interrupt to resume the transfer when + * the TxFIFO is empty. + */ + + regval = stm32_getreg(regaddr); + if ((int)(regval & OTG_DTXFSTS_MASK) < nwords) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EMPWAIT), (uint16_t)regval); + + /* There is insufficient space in the TxFIFO. Wait for a TxFIFO + * empty interrupt and try again. + */ + + uint32_t empmsk = stm32_getreg(STM32_OTG_DIEPEMPMSK); + empmsk |= OTG_DIEPEMPMSK(privep->epphy); + stm32_putreg(empmsk, STM32_OTG_DIEPEMPMSK); + + /* Terminate the transfer. We will try again when the TxFIFO empty + * interrupt is received. + */ + + return; + } + + /* Transfer data to the TxFIFO */ + + buf = privreq->req.buf + privreq->req.xfrd; + stm32_epin_transfer(privep, buf, nbytes); + + /* If it was not before, the OUT endpoint is now actively transferring + * data. + */ + + privep->active = true; + + /* EP0 is a special case */ + + if (privep->epphy == EP0) + { + priv->ep0state = EP0STATE_DATA_IN; + } + + /* Update for the next time through the loop */ + + privreq->req.xfrd += nbytes; + } + + /* Note that the ZLP, if any, must be sent as a separate transfer. The need + * for a ZLP is indicated by privep->zlp. If all of the bytes were sent + * (including any final null packet) then we are finished with the transfer + */ + + if (privreq->req.xfrd >= privreq->req.len && !privep->zlp) + { + usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); + + /* We are finished with the request (although the transfer has not + * yet completed). + */ + + stm32_req_complete(privep, OK); + } +} + +/**************************************************************************** + * Name: stm32_rxfifo_read + * + * Description: + * Read packet from the RxFIFO into a read request. + * + ****************************************************************************/ + +static void stm32_rxfifo_read(FAR struct stm32_ep_s *privep, + FAR uint8_t *dest, uint16_t len) +{ + uint32_t regaddr; + int i; + + /* Get the address of the RxFIFO. Note: there is only one RxFIFO so + * we might as well use the address associated with EP0. + */ + + regaddr = STM32_OTG_DFIFO_DEP(EP0); + + /* Read 32-bits and write 4 x 8-bits at time (to avoid unaligned accesses) */ + + for (i = 0; i < len; i += 4) + { + union + { + uint32_t w; + uint8_t b[4]; + } data; + + /* Read 1 x 32-bits of EP0 packet data */ + + data.w = stm32_getreg(regaddr); + + /* Write 4 x 8-bits of EP0 packet data */ + + *dest++ = data.b[0]; + *dest++ = data.b[1]; + *dest++ = data.b[2]; + *dest++ = data.b[3]; + } +} + +/**************************************************************************** + * Name: stm32_rxfifo_discard + * + * Description: + * Discard packet data from the RxFIFO. + * + ****************************************************************************/ + +static void stm32_rxfifo_discard(FAR struct stm32_ep_s *privep, int len) +{ + if (len > 0) + { + uint32_t regaddr; + int i; + + /* Get the address of the RxFIFO Note: there is only one RxFIFO so + * we might as well use the address associated with EP0. + */ + + regaddr = STM32_OTG_DFIFO_DEP(EP0); + + /* Read 32-bits at time */ + + for (i = 0; i < len; i += 4) + { + volatile uint32_t data = stm32_getreg(regaddr); + (void)data; + } + } +} + +/**************************************************************************** + * Name: stm32_epout_complete + * + * Description: + * This function is called when an OUT transfer complete interrupt is + * received. It completes the read request at the head of the endpoint's + * request queue. + * + ****************************************************************************/ + +static void stm32_epout_complete(FAR struct stm32_usbdev_s *priv, + FAR struct stm32_ep_s *privep) +{ + struct stm32_req_s *privreq; + + /* Since a transfer just completed, there must be a read request at the head of + * the endpoint request queue. + */ + + privreq = stm32_rqpeek(privep); + DEBUGASSERT(privreq); + + if (!privreq) + { + /* An OUT transfer completed, but no packet to receive the data. This + * should not happen. + */ + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); + privep->active = false; + return; + } + + ullinfo("EP%d: len=%d xfrd=%d\n", + privep->epphy, privreq->req.len, privreq->req.xfrd); + + /* Return the completed read request to the class driver and mark the state + * IDLE. + */ + + usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); + stm32_req_complete(privep, OK); + privep->active = false; + + /* Now set up the next read request (if any) */ + + stm32_epout_request(priv, privep); +} + +/**************************************************************************** + * Name: stm32_ep0out_receive + * + * Description: + * This function is called from the RXFLVL interrupt handler when new incoming + * data is available in the endpoint's RxFIFO. This function will simply + * copy the incoming data into pending request's data buffer. + * + ****************************************************************************/ + +static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, int bcnt) +{ + FAR struct stm32_usbdev_s *priv; + + /* Sanity Checking */ + + DEBUGASSERT(privep && privep->ep.priv); + priv = (FAR struct stm32_usbdev_s *)privep->ep.priv; + + ullinfo("EP0: bcnt=%d\n", bcnt); + usbtrace(TRACE_READ(EP0), bcnt); + + /* Verify that an OUT SETUP request as received before this data was + * received in the RxFIFO. + */ + + if (priv->ep0state == EP0STATE_SETUP_OUT) + { + /* Read the data into our special buffer for SETUP data */ + + int readlen = MIN(CONFIG_USBDEV_SETUP_MAXDATASIZE, bcnt); + stm32_rxfifo_read(privep, priv->ep0data, readlen); + + /* Do we have to discard any excess bytes? */ + + stm32_rxfifo_discard(privep, bcnt - readlen); + + /* Now we can process the setup command */ + + privep->active = false; + priv->ep0state = EP0STATE_SETUP_READY; + priv->ep0datlen = readlen; + + stm32_ep0out_setup(priv); + } + else + { + /* This is an error. We don't have any idea what to do with the EP0 + * data in this case. Just read and discard it so that the RxFIFO + * does not become constipated. + */ + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOOUTSETUP), priv->ep0state); + stm32_rxfifo_discard(privep, bcnt); + privep->active = false; + } +} + +/**************************************************************************** + * Name: stm32_epout_receive + * + * Description: + * This function is called from the RXFLVL interrupt handler when new incoming + * data is available in the endpoint's RxFIFO. This function will simply + * copy the incoming data into pending request's data buffer. + * + ****************************************************************************/ + +static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt) +{ + struct stm32_req_s *privreq; + uint8_t *dest; + int buflen; + int readlen; + + /* Get a reference to the request at the head of the endpoint's request + * queue. + */ + + privreq = stm32_rqpeek(privep); + if (!privreq) + { + /* Incoming data is available in the RxFIFO, but there is no read setup + * to receive the receive the data. This should not happen for data + * endpoints; those endpoints should have been NAKing any OUT data tokens. + * + * We should get here normally on OUT data phase following an OUT + * SETUP command. EP0 data will still receive data in this case and it + * should not be NAKing. + */ + + if (privep->epphy == 0) + { + stm32_ep0out_receive(privep, bcnt); + } + else + { + /* Otherwise, the data is lost. This really should not happen if + * NAKing is working as expected. + */ + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); + + /* Discard the data in the RxFIFO */ + + stm32_rxfifo_discard(privep, bcnt); + } + + privep->active = false; + return; + } + + ullinfo("EP%d: len=%d xfrd=%d\n", privep->epphy, privreq->req.len, privreq->req.xfrd); + usbtrace(TRACE_READ(privep->epphy), bcnt); + + /* Get the number of bytes to transfer from the RxFIFO */ + + buflen = privreq->req.len - privreq->req.xfrd; + DEBUGASSERT(buflen > 0 && buflen >= bcnt); + readlen = MIN(buflen, bcnt); + + /* Get the destination of the data transfer */ + + dest = privreq->req.buf + privreq->req.xfrd; + + /* Transfer the data from the RxFIFO to the request's data buffer */ + + stm32_rxfifo_read(privep, dest, readlen); + + /* If there were more bytes in the RxFIFO than could be held in the read + * request, then we will have to discard those. + */ + + stm32_rxfifo_discard(privep, bcnt - readlen); + + /* Update the number of bytes transferred */ + + privreq->req.xfrd += readlen; +} + +/**************************************************************************** + * Name: stm32_epout_request + * + * Description: + * This function is called when either (1) new read request is received, or + * (2) a pending receive request completes. If there is no read in pending, + * then this function will initiate the next OUT (read) operation. + * + ****************************************************************************/ + +static void stm32_epout_request(FAR struct stm32_usbdev_s *priv, + FAR struct stm32_ep_s *privep) +{ + struct stm32_req_s *privreq; + uint32_t regaddr; + uint32_t regval; + uint32_t xfrsize; + uint32_t pktcnt; + + /* Make sure that there is not already a pending request request. If there is, + * just return, leaving the newly received request in the request queue. + */ + + if (!privep->active) + { + /* Loop until a valid request is found (or the request queue is empty). + * The loop is only need to look at the request queue again is an invalid + * read request is encountered. + */ + + for (; ; ) + { + /* Get a reference to the request at the head of the endpoint's request queue */ + + privreq = stm32_rqpeek(privep); + if (!privreq) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); + + /* There are no read requests to be setup. Configure the hardware to + * NAK any incoming packets. (This should already be the case. I + * think that the hardware will automatically NAK after a transfer is + * completed until SNAK is cleared). + */ + + regaddr = STM32_OTG_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval |= OTG_DOEPCTL_SNAK; + stm32_putreg(regval, regaddr); + + /* This endpoint is no longer actively transferring */ + + privep->active = false; + return; + } + + ullinfo("EP%d: len=%d\n", privep->epphy, privreq->req.len); + + /* Ignore any attempt to receive a zero length packet (this really + * should not happen. + */ + + if (privreq->req.len <= 0) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); + stm32_req_complete(privep, OK); + } + + /* Otherwise, we have a usable read request... break out of the loop */ + + else + { + break; + } + } + + /* Setup the pending read into the request buffer. First calculate: + * + * pktcnt = the number of packets (of maxpacket bytes) required to + * perform the transfer. + * xfrsize = The total number of bytes required (in units of + * maxpacket bytes). + */ + + pktcnt = (privreq->req.len + (privep->ep.maxpacket - 1)) / privep->ep.maxpacket; + xfrsize = pktcnt * privep->ep.maxpacket; + + /* Then setup the hardware to perform this transfer */ + + regaddr = STM32_OTG_DOEPTSIZ(privep->epphy); + regval = stm32_getreg(regaddr); + regval &= ~(OTG_DOEPTSIZ_XFRSIZ_MASK | OTG_DOEPTSIZ_PKTCNT_MASK); + regval |= (xfrsize << OTG_DOEPTSIZ_XFRSIZ_SHIFT); + regval |= (pktcnt << OTG_DOEPTSIZ_PKTCNT_SHIFT); + stm32_putreg(regval, regaddr); + + /* Then enable the transfer */ + + regaddr = STM32_OTG_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + + /* When an isochronous transfer is enabled the Even/Odd frame bit must + * also be set appropriately. + */ + +#ifdef CONFIG_USBDEV_ISOCHRONOUS + if (privep->eptype == USB_EP_ATTR_XFER_ISOC) + { + if (privep->odd) + { + regval |= OTG_DOEPCTL_SODDFRM; + } + else + { + regval |= OTG_DOEPCTL_SEVNFRM; + } + } +#endif + + /* Clearing NAKing and enable the transfer. */ + + regval |= (OTG_DOEPCTL_CNAK | OTG_DOEPCTL_EPENA); + stm32_putreg(regval, regaddr); + + /* A transfer is now active on this endpoint */ + + privep->active = true; + + /* EP0 is a special case. We need to know when to switch back to + * normal SETUP processing. + */ + + if (privep->epphy == EP0) + { + priv->ep0state = EP0STATE_DATA_OUT; + } + } +} + +/**************************************************************************** + * Name: stm32_ep_flush + * + * Description: + * Flush any primed descriptors from this ep + * + ****************************************************************************/ + +static void stm32_ep_flush(struct stm32_ep_s *privep) +{ + if (privep->isin) + { + stm32_txfifo_flush(OTG_GRSTCTL_TXFNUM_D(privep->epphy)); + } + else + { + stm32_rxfifo_flush(); + } +} + +/**************************************************************************** + * Name: stm32_req_complete + * + * Description: + * Handle termination of the request at the head of the endpoint request queue. + * + ****************************************************************************/ + +static void stm32_req_complete(struct stm32_ep_s *privep, int16_t result) +{ + FAR struct stm32_req_s *privreq; + + /* Remove the request at the head of the request list */ + + privreq = stm32_req_remfirst(privep); + DEBUGASSERT(privreq != NULL); + + /* If endpoint 0, temporarily reflect the state of protocol stalled + * in the callback. + */ + + bool stalled = privep->stalled; + if (privep->epphy == EP0) + { + privep->stalled = privep->dev->stalled; + } + + /* Save the result in the request structure */ + + privreq->req.result = result; + + /* Callback to the request completion handler */ + + privreq->req.callback(&privep->ep, &privreq->req); + + /* Restore the stalled indication */ + + privep->stalled = stalled; +} + +/**************************************************************************** + * Name: stm32_req_cancel + * + * Description: + * Cancel all pending requests for an endpoint + * + ****************************************************************************/ + +static void stm32_req_cancel(struct stm32_ep_s *privep, int16_t status) +{ + if (!stm32_rqempty(privep)) + { + stm32_ep_flush(privep); + } + + while (!stm32_rqempty(privep)) + { + usbtrace(TRACE_COMPLETE(privep->epphy), + (stm32_rqpeek(privep))->req.xfrd); + stm32_req_complete(privep, status); + } +} + +/**************************************************************************** + * Name: stm32_ep_findbyaddr + * + * Description: + * Find the physical endpoint structure corresponding to a logic endpoint + * address + * + ****************************************************************************/ + +static struct stm32_ep_s *stm32_ep_findbyaddr(struct stm32_usbdev_s *priv, + uint16_t eplog) +{ + struct stm32_ep_s *privep; + uint8_t epphy = USB_EPNO(eplog); + + if (epphy >= STM32_NENDPOINTS) + { + return NULL; + } + + /* Is this an IN or an OUT endpoint? */ + + if (USB_ISEPIN(eplog)) + { + privep = &priv->epin[epphy]; + } + else + { + privep = &priv->epout[epphy]; + } + + /* Return endpoint reference */ + + DEBUGASSERT(privep->epphy == epphy); + return privep; +} + +/**************************************************************************** + * Name: stm32_req_dispatch + * + * Description: + * Provide unhandled setup actions to the class driver. This is logically part + * of the USB interrupt handler. + * + ****************************************************************************/ + +static int stm32_req_dispatch(struct stm32_usbdev_s *priv, + const struct usb_ctrlreq_s *ctrl) +{ + int ret = -EIO; + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DISPATCH), 0); + if (priv->driver) + { + /* Forward to the control request to the class driver implementation */ + + ret = CLASS_SETUP(priv->driver, &priv->usbdev, ctrl, + priv->ep0data, priv->ep0datlen); + } + + if (ret < 0) + { + /* Stall on failure */ + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DISPATCHSTALL), 0); + priv->stalled = true; + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_usbreset + * + * Description: + * Reset Usb engine + * + ****************************************************************************/ + +static void stm32_usbreset(struct stm32_usbdev_s *priv) +{ + FAR struct stm32_ep_s *privep; + uint32_t regval; + int i; + + /* Clear the Remote Wake-up Signaling */ + + regval = stm32_getreg(STM32_OTG_DCTL); + regval &= ~OTG_DCTL_RWUSIG; + stm32_putreg(regval, STM32_OTG_DCTL); + + /* Flush the EP0 Tx FIFO */ + + stm32_txfifo_flush(OTG_GRSTCTL_TXFNUM_D(EP0)); + + /* Tell the class driver that we are disconnected. The class + * driver should then accept any new configurations. + */ + + if (priv->driver) + { + CLASS_DISCONNECT(priv->driver, &priv->usbdev); + } + + /* Mark all endpoints as available */ + + priv->epavail[0] = STM32_EP_AVAILABLE; + priv->epavail[1] = STM32_EP_AVAILABLE; + + /* Disable all end point interrupts */ + + for (i = 0; i < STM32_NENDPOINTS ; i++) + { + /* Disable endpoint interrupts */ + + stm32_putreg(0xff, STM32_OTG_DIEPINT(i)); + stm32_putreg(0xff, STM32_OTG_DOEPINT(i)); + + /* Return write requests to the class implementation */ + + privep = &priv->epin[i]; + stm32_req_cancel(privep, -ESHUTDOWN); + + /* Reset IN endpoint status */ + + privep->stalled = false; + + /* Return read requests to the class implementation */ + + privep = &priv->epout[i]; + stm32_req_cancel(privep, -ESHUTDOWN); + + /* Reset endpoint status */ + + privep->stalled = false; + } + + stm32_putreg(0xffffffff, STM32_OTG_DAINT); + + /* Mask all device endpoint interrupts except EP0 */ + + regval = (OTG_DAINT_IEP(EP0) | OTG_DAINT_OEP(EP0)); + stm32_putreg(regval, STM32_OTG_DAINTMSK); + + /* Unmask OUT interrupts */ + + regval = (OTG_DOEPMSK_XFRCM | OTG_DOEPMSK_STUPM | OTG_DOEPMSK_EPDM); + stm32_putreg(regval, STM32_OTG_DOEPMSK); + + /* Unmask IN interrupts */ + + regval = (OTG_DIEPMSK_XFRCM | OTG_DIEPMSK_EPDM | OTG_DIEPMSK_TOM); + stm32_putreg(regval, STM32_OTG_DIEPMSK); + + /* Reset device address to 0 */ + + stm32_setaddress(priv, 0); + priv->devstate = DEVSTATE_DEFAULT; + priv->usbdev.speed = USB_SPEED_FULL; + + /* Re-configure EP0 */ + + stm32_ep0_configure(priv); + + /* Setup EP0 to receive SETUP packets */ + + stm32_ep0out_ctrlsetup(priv); +} + +/**************************************************************************** + * Name: stm32_ep0out_testmode + * + * Description: + * Select test mode + * + ****************************************************************************/ + +static inline void stm32_ep0out_testmode(FAR struct stm32_usbdev_s *priv, + uint16_t index) +{ + uint8_t testmode; + + testmode = index >> 8; + switch (testmode) + { + case 1: + priv->testmode = OTG_TESTMODE_J; + break; + + case 2: + priv->testmode = OTG_TESTMODE_K; + break; + + case 3: + priv->testmode = OTG_TESTMODE_SE0_NAK; + break; + + case 4: + priv->testmode = OTG_TESTMODE_PACKET; + break; + + case 5: + priv->testmode = OTG_TESTMODE_FORCE; + break; + + default: + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADTESTMODE), testmode); + priv->dotest = false; + priv->testmode = OTG_TESTMODE_DISABLED; + priv->stalled = true; + } + + priv->dotest = true; + stm32_ep0in_transmitzlp(priv); +} + +/**************************************************************************** + * Name: stm32_ep0out_stdrequest + * + * Description: + * Handle a stanard request on EP0. Pick off the things of interest to the + * USB device controller driver; pass what is left to the class driver. + * + ****************************************************************************/ + +static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, + FAR struct stm32_ctrlreq_s *ctrlreq) +{ + FAR struct stm32_ep_s *privep; + + /* Handle standard request */ + + switch (ctrlreq->req) + { + case USB_REQ_GETSTATUS: + { + /* type: device-to-host; recipient = device, interface, endpoint + * value: 0 + * index: zero interface endpoint + * len: 2; data = status + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), 0); + if (!priv->addressed || + ctrlreq->len != 2 || + USB_REQ_ISOUT(ctrlreq->type) || + ctrlreq->value != 0) + { + priv->stalled = true; + } + else + { + switch (ctrlreq->type & USB_REQ_RECIPIENT_MASK) + { + case USB_REQ_RECIPIENT_ENDPOINT: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPGETSTATUS), 0); + privep = stm32_ep_findbyaddr(priv, ctrlreq->index); + if (!privep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), 0); + priv->stalled = true; + } + else + { + if (privep->stalled) + { + priv->ep0data[0] = (1 << USB_FEATURE_ENDPOINTHALT); + } + else + { + priv->ep0data[0] = 0; /* Not stalled */ + } + + priv->ep0data[1] = 0; + stm32_ep0in_setupresponse(priv, priv->ep0data, 2); + } + } + break; + + case USB_REQ_RECIPIENT_DEVICE: + { + if (ctrlreq->index == 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVGETSTATUS), 0); + + /* Features: Remote Wakeup and self-powered */ + + priv->ep0data[0] = (priv->selfpowered << USB_FEATURE_SELFPOWERED); + priv->ep0data[0] |= (priv->wakeup << USB_FEATURE_REMOTEWAKEUP); + priv->ep0data[1] = 0; + + stm32_ep0in_setupresponse(priv, priv->ep0data, 2); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADDEVGETSTATUS), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_RECIPIENT_INTERFACE: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IFGETSTATUS), 0); + priv->ep0data[0] = 0; + priv->ep0data[1] = 0; + + stm32_ep0in_setupresponse(priv, priv->ep0data, 2); + } + break; + + default: + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSTATUS), 0); + priv->stalled = true; + } + break; + } + } + } + break; + + case USB_REQ_CLEARFEATURE: + { + /* type: host-to-device; recipient = device, interface or endpoint + * value: feature selector + * index: zero interface endpoint; + * len: zero, data = none + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), 0); + if (priv->addressed != 0 && ctrlreq->len == 0) + { + uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; + if (recipient == USB_REQ_RECIPIENT_ENDPOINT && + ctrlreq->value == USB_FEATURE_ENDPOINTHALT && + (privep = stm32_ep_findbyaddr(priv, ctrlreq->index)) != NULL) + { + stm32_ep_clrstall(privep); + stm32_ep0in_transmitzlp(priv); + } + else if (recipient == USB_REQ_RECIPIENT_DEVICE && + ctrlreq->value == USB_FEATURE_REMOTEWAKEUP) + { + priv->wakeup = 0; + stm32_ep0in_transmitzlp(priv); + } + else + { + /* Actually, I think we could just stall here. */ + + (void)stm32_req_dispatch(priv, &priv->ctrlreq); + } + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADCLEARFEATURE), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_SETFEATURE: + { + /* type: host-to-device; recipient = device, interface, endpoint + * value: feature selector + * index: zero interface endpoint; + * len: 0; data = none + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), 0); + if (priv->addressed != 0 && ctrlreq->len == 0) + { + uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; + if (recipient == USB_REQ_RECIPIENT_ENDPOINT && + ctrlreq->value == USB_FEATURE_ENDPOINTHALT && + (privep = stm32_ep_findbyaddr(priv, ctrlreq->index)) != NULL) + { + stm32_ep_setstall(privep); + stm32_ep0in_transmitzlp(priv); + } + else if (recipient == USB_REQ_RECIPIENT_DEVICE && + ctrlreq->value == USB_FEATURE_REMOTEWAKEUP) + { + priv->wakeup = 1; + stm32_ep0in_transmitzlp(priv); + } + else if (recipient == USB_REQ_RECIPIENT_DEVICE && + ctrlreq->value == USB_FEATURE_TESTMODE && + ((ctrlreq->index & 0xff) == 0)) + { + stm32_ep0out_testmode(priv, ctrlreq->index); + } + else if (priv->configured) + { + /* Actually, I think we could just stall here. */ + + (void)stm32_req_dispatch(priv, &priv->ctrlreq); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); + priv->stalled = true; + } + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_SETADDRESS: + { + /* type: host-to-device; recipient = device + * value: device address + * index: 0 + * len: 0; data = none + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETADDRESS), ctrlreq->value); + if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && + ctrlreq->index == 0 && + ctrlreq->len == 0 && + ctrlreq->value < 128 && + priv->devstate != DEVSTATE_CONFIGURED) + { + /* Save the address. We cannot actually change to the next address until + * the completion of the status phase. + */ + + stm32_setaddress(priv, (uint16_t)priv->ctrlreq.value[0]); + stm32_ep0in_transmitzlp(priv); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETADDRESS), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_GETDESCRIPTOR: + /* type: device-to-host; recipient = device + * value: descriptor type and index + * index: 0 or language ID; + * len: descriptor len; data = descriptor + */ + + case USB_REQ_SETDESCRIPTOR: + /* type: host-to-device; recipient = device + * value: descriptor type and index + * index: 0 or language ID; + * len: descriptor len; data = descriptor + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), 0); + if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) + { + (void)stm32_req_dispatch(priv, &priv->ctrlreq); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSETDESC), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_GETCONFIGURATION: + /* type: device-to-host; recipient = device + * value: 0; + * index: 0; + * len: 1; data = configuration value + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), 0); + if (priv->addressed && + (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && + ctrlreq->value == 0 && + ctrlreq->index == 0 && + ctrlreq->len == 1) + { + (void)stm32_req_dispatch(priv, &priv->ctrlreq); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETCONFIG), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_SETCONFIGURATION: + /* type: host-to-device; recipient = device + * value: configuration value + * index: 0; + * len: 0; data = none + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), 0); + if (priv->addressed && + (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && + ctrlreq->index == 0 && + ctrlreq->len == 0) + { + /* Give the configuration to the class driver */ + + int ret = stm32_req_dispatch(priv, &priv->ctrlreq); + + /* If the class driver accepted the configuration, then mark the + * device state as configured (or not, depending on the + * configuration). + */ + + if (ret == OK) + { + uint8_t cfg = (uint8_t)ctrlreq->value; + if (cfg != 0) + { + priv->devstate = DEVSTATE_CONFIGURED; + priv->configured = true; + } + else + { + priv->devstate = DEVSTATE_ADDRESSED; + priv->configured = false; + } + } + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETCONFIG), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_GETINTERFACE: + /* type: device-to-host; recipient = interface + * value: 0 + * index: interface; + * len: 1; data = alt interface + */ + + case USB_REQ_SETINTERFACE: + /* type: host-to-device; recipient = interface + * value: alternate setting + * index: interface; + * len: 0; data = none + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), 0); + (void)stm32_req_dispatch(priv, &priv->ctrlreq); + } + break; + + case USB_REQ_SYNCHFRAME: + /* type: device-to-host; recipient = endpoint + * value: 0 + * index: endpoint; + * len: 2; data = frame number + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SYNCHFRAME), 0); + } + break; + + default: + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDCTRLREQ), 0); + priv->stalled = true; + } + break; + } +} + +/**************************************************************************** + * Name: stm32_ep0out_setup + * + * Description: + * USB Ctrl EP Setup Event. This is logically part of the USB interrupt + * handler. This event occurs when a setup packet is receive on EP0 OUT. + * + ****************************************************************************/ + +static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv) +{ + struct stm32_ctrlreq_s ctrlreq; + + /* Verify that a SETUP was received */ + + if (priv->ep0state != EP0STATE_SETUP_READY) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0NOSETUP), priv->ep0state); + return; + } + + /* Terminate any pending requests */ + + stm32_req_cancel(&priv->epout[EP0], -EPROTO); + stm32_req_cancel(&priv->epin[EP0], -EPROTO); + + /* Assume NOT stalled */ + + priv->epout[EP0].stalled = false; + priv->epin[EP0].stalled = false; + priv->stalled = false; + + /* Starting to process a control request - update state */ + + priv->ep0state = EP0STATE_SETUP_PROCESS; + + /* And extract the little-endian 16-bit values to host order */ + + ctrlreq.type = priv->ctrlreq.type; + ctrlreq.req = priv->ctrlreq.req; + ctrlreq.value = GETUINT16(priv->ctrlreq.value); + ctrlreq.index = GETUINT16(priv->ctrlreq.index); + ctrlreq.len = GETUINT16(priv->ctrlreq.len); + + ullinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n", + ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len); + + /* Check for a standard request */ + + if ((ctrlreq.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD) + { + /* Dispatch any non-standard requests */ + + (void)stm32_req_dispatch(priv, &priv->ctrlreq); + } + else + { + /* Handle standard requests. */ + + stm32_ep0out_stdrequest(priv, &ctrlreq); + } + + /* Check if the setup processing resulted in a STALL */ + + if (priv->stalled) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), priv->ep0state); + stm32_ep0_stall(priv); + } + + /* Reset state/data associated with thie SETUP request */ + + priv->ep0datlen = 0; +} + +/**************************************************************************** + * Name: stm32_epout + * + * Description: + * This is part of the OUT endpoint interrupt processing. This function + * handles the OUT event for a single endpoint. + * + ****************************************************************************/ + +static inline void stm32_epout(FAR struct stm32_usbdev_s *priv, uint8_t epno) +{ + FAR struct stm32_ep_s *privep; + + /* Endpoint 0 is a special case. */ + + if (epno == 0) + { + privep = &priv->epout[EP0]; + + /* In the EP0STATE_DATA_OUT state, we are receiving data into the + * request buffer. In that case, we must continue the request + * processing. + */ + + if (priv->ep0state == EP0STATE_DATA_OUT) + { + /* Continue processing data from the EP0 OUT request queue */ + + stm32_epout_complete(priv, privep); + + /* If we are not actively processing an OUT request, then we + * need to setup to receive the next control request. + */ + + if (!privep->active) + { + stm32_ep0out_ctrlsetup(priv); + priv->ep0state = EP0STATE_IDLE; + } + } + } + + /* For other endpoints, the only possibility is that we are continuing + * or finishing an OUT request. + */ + + else if (priv->devstate == DEVSTATE_CONFIGURED) + { + stm32_epout_complete(priv, &priv->epout[epno]); + } +} + +/**************************************************************************** + * Name: stm32_epout_interrupt + * + * Description: + * USB OUT endpoint interrupt handler. The core generates this interrupt when + * there is an interrupt is pending on one of the OUT endpoints of the core. + * The driver must read the OTG DAINT register to determine the exact number + * of the OUT endpoint on which the interrupt occurred, and then read the + * corresponding OTG DOEPINTx register to determine the exact cause of the + * interrupt. + * + ****************************************************************************/ + +static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv) +{ + uint32_t daint; + uint32_t regval; + uint32_t doepint; + int epno; + + /* Get the pending, enabled interrupts for the OUT endpoint from the endpoint + * interrupt status register. + */ + + regval = stm32_getreg(STM32_OTG_DAINT); + regval &= stm32_getreg(STM32_OTG_DAINTMSK); + daint = (regval & OTG_DAINT_OEP_MASK) >> OTG_DAINT_OEP_SHIFT; + + if (daint == 0) + { + /* We got an interrupt, but there is no unmasked endpoint that caused + * it ?! When this happens, the interrupt flag never gets cleared and + * we are stuck in infinite interrupt loop. + * + * This shouldn't happen if we are diligent about handling timing + * issues when masking endpoint interrupts. However, this workaround + * avoids infinite loop and allows operation to continue normally. It + * works by clearing each endpoint flags, masked or not. + */ + + regval = stm32_getreg(STM32_OTG_DAINT); + daint = (regval & OTG_DAINT_OEP_MASK) >> OTG_DAINT_OEP_SHIFT; + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTUNEXPECTED), + (uint16_t)regval); + + epno = 0; + while (daint) + { + if ((daint & 1) != 0) + { + regval = stm32_getreg(STM32_OTG_DOEPINT(epno)); + ullerr("DOEPINT(%d) = %08x\n", epno, regval); + stm32_putreg(0xFF, STM32_OTG_DOEPINT(epno)); + } + + epno++; + daint >>= 1; + } + + return; + } + + /* Process each pending IN endpoint interrupt */ + + epno = 0; + while (daint) + { + /* Is an OUT interrupt pending for this endpoint? */ + + if ((daint & 1) != 0) + { + /* Yes.. get the OUT endpoint interrupt status */ + + doepint = stm32_getreg(STM32_OTG_DOEPINT(epno)); + doepint &= stm32_getreg(STM32_OTG_DOEPMSK); + + /* Transfer completed interrupt. This interrupt is trigged when + * stm32_rxinterrupt() removes the last packet data from the RxFIFO. + * In this case, core internally sets the NAK bit for this endpoint to + * prevent it from receiving any more packets. + */ + + if ((doepint & OTG_DOEPINT_XFRC) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_XFRC), (uint16_t)doepint); + + /* Clear the bit in DOEPINTn for this interrupt */ + + stm32_putreg(OTG_DOEPINT_XFRC, STM32_OTG_DOEPINT(epno)); + + /* Handle the RX transfer data ready event */ + + stm32_epout(priv, epno); + } + + /* Endpoint disabled interrupt (ignored because this interrupt is + * used in polled mode by the endpoint disable logic). + */ +#if 1 + /* REVISIT: */ + if ((doepint & OTG_DOEPINT_EPDISD) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_EPDISD), (uint16_t)doepint); + + /* Clear the bit in DOEPINTn for this interrupt */ + + stm32_putreg(OTG_DOEPINT_EPDISD, STM32_OTG_DOEPINT(epno)); + } +#endif + /* Setup Phase Done (control EPs) */ + + if ((doepint & OTG_DOEPINT_SETUP) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_SETUP), priv->ep0state); + + /* Handle the receipt of the IN SETUP packets now (OUT setup + * packet processing may be delayed until the accompanying + * OUT DATA is received) + */ + + if (priv->ep0state == EP0STATE_SETUP_READY) + { + stm32_ep0out_setup(priv); + } + stm32_putreg(OTG_DOEPINT_SETUP, STM32_OTG_DOEPINT(epno)); + } + } + + epno++; + daint >>= 1; + } +} + +/**************************************************************************** + * Name: stm32_epin_runtestmode + * + * Description: + * Execute the test mode setup by the SET FEATURE request + * + ****************************************************************************/ + +static inline void stm32_epin_runtestmode(FAR struct stm32_usbdev_s *priv) +{ + uint32_t regval = stm32_getreg(STM32_OTG_DCTL); + regval &= OTG_DCTL_TCTL_MASK; + regval |= (uint32_t)priv->testmode << OTG_DCTL_TCTL_SHIFT; + stm32_putreg(regval , STM32_OTG_DCTL); + + priv->dotest = 0; + priv->testmode = OTG_TESTMODE_DISABLED; +} + +/**************************************************************************** + * Name: stm32_epin + * + * Description: + * This is part of the IN endpoint interrupt processing. This function + * handles the IN event for a single endpoint. + * + ****************************************************************************/ + +static inline void stm32_epin(FAR struct stm32_usbdev_s *priv, uint8_t epno) +{ + FAR struct stm32_ep_s *privep = &priv->epin[epno]; + + /* Endpoint 0 is a special case. */ + + if (epno == 0) + { + /* In the EP0STATE_DATA_IN state, we are sending data from request + * buffer. In that case, we must continue the request processing. + */ + + if (priv->ep0state == EP0STATE_DATA_IN) + { + /* Continue processing data from the EP0 OUT request queue */ + + stm32_epin_request(priv, privep); + + /* If we are not actively processing an OUT request, then we + * need to setup to receive the next control request. + */ + + if (!privep->active) + { + stm32_ep0out_ctrlsetup(priv); + priv->ep0state = EP0STATE_IDLE; + } + } + + /* Test mode is another special case */ + + if (priv->dotest) + { + stm32_epin_runtestmode(priv); + } + } + + /* For other endpoints, the only possibility is that we are continuing + * or finishing an IN request. + */ + + else if (priv->devstate == DEVSTATE_CONFIGURED) + { + /* Continue processing data from the endpoint write request queue */ + + stm32_epin_request(priv, privep); + } +} + +/**************************************************************************** + * Name: stm32_epin_txfifoempty + * + * Description: + * TxFIFO empty interrupt handling + * + ****************************************************************************/ + +static inline void stm32_epin_txfifoempty(FAR struct stm32_usbdev_s *priv, int epno) +{ + FAR struct stm32_ep_s *privep = &priv->epin[epno]; + + /* Continue processing the write request queue. This may mean sending + * more data from the existing request or terminating the current requests + * and (perhaps) starting the IN transfer from the next write request. + */ + + stm32_epin_request(priv, privep); +} + +/**************************************************************************** + * Name: stm32_epin_interrupt + * + * Description: + * USB IN endpoint interrupt handler. The core generates this interrupt when + * an interrupt is pending on one of the IN endpoints of the core. The driver + * must read the OTG DAINT register to determine the exact number of the IN + * endpoint on which the interrupt occurred, and then read the corresponding + * OTG DIEPINTx register to determine the exact cause of the interrupt. + * + ****************************************************************************/ + +static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) +{ + uint32_t diepint; + uint32_t daint; + uint32_t mask; + uint32_t empty; + int epno; + + /* Get the pending, enabled interrupts for the IN endpoint from the endpoint + * interrupt status register. + */ + + daint = stm32_getreg(STM32_OTG_DAINT); + daint &= stm32_getreg(STM32_OTG_DAINTMSK); + daint &= OTG_DAINT_IEP_MASK; + + if (daint == 0) + { + /* We got an interrupt, but there is no unmasked endpoint that caused + * it ?! When this happens, the interrupt flag never gets cleared and + * we are stuck in infinite interrupt loop. + * + * This shouldn't happen if we are diligent about handling timing + * issues when masking endpoint interrupts. However, this workaround + * avoids infinite loop and allows operation to continue normally. It + * works by clearing each endpoint flags, masked or not. + */ + + daint = stm32_getreg(STM32_OTG_DAINT); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINUNEXPECTED), + (uint16_t)daint); + + daint &= OTG_DAINT_IEP_MASK; + epno = 0; + + while (daint) + { + if ((daint & 1) != 0) + { + ullerr("DIEPINT(%d) = %08x\n", + epno, stm32_getreg(STM32_OTG_DIEPINT(epno))); + stm32_putreg(0xFF, STM32_OTG_DIEPINT(epno)); + } + + epno++; + daint >>= 1; + } + + return; + } + + /* Process each pending IN endpoint interrupt */ + + epno = 0; + while (daint) + { + /* Is an IN interrupt pending for this endpoint? */ + + if ((daint & 1) != 0) + { + /* Get IN interrupt mask register. Bits 0-6 correspond to enabled + * interrupts as will be found in the DIEPINT interrupt status + * register. + */ + + mask = stm32_getreg(STM32_OTG_DIEPMSK); + + /* Check if the TxFIFO not empty interrupt is enabled for this + * endpoint in the DIEPMSK register. Bits n corresponds to + * endpoint n in the register. That condition corresponds to + * bit 7 of the DIEPINT interrupt status register. There is + * no TXFE bit in the mask register, so we fake one here. + */ + + empty = stm32_getreg(STM32_OTG_DIEPEMPMSK); + if ((empty & OTG_DIEPEMPMSK(epno)) != 0) + { + mask |= OTG_DIEPINT_TXFE; + } + + /* Now, read the interrupt status and mask out all disabled + * interrupts. + */ + + diepint = stm32_getreg(STM32_OTG_DIEPINT(epno)) & mask; + + /* Decode and process the enabled, pending interrupts */ + /* Transfer completed interrupt */ + + if ((diepint & OTG_DIEPINT_XFRC) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_XFRC), + (uint16_t)diepint); + + /* It is possible that logic may be waiting for a the + * TxFIFO to become empty. We disable the TxFIFO empty + * interrupt here; it will be re-enabled if there is still + * insufficient space in the TxFIFO. + */ + + empty &= ~OTG_DIEPEMPMSK(epno); + stm32_putreg(empty, STM32_OTG_DIEPEMPMSK); + stm32_putreg(OTG_DIEPINT_XFRC, STM32_OTG_DIEPINT(epno)); + + /* IN transfer complete */ + + stm32_epin(priv, epno); + } + + /* Timeout condition */ + + if ((diepint & OTG_DIEPINT_TOC) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TOC), (uint16_t)diepint); + stm32_putreg(OTG_DIEPINT_TOC, STM32_OTG_DIEPINT(epno)); + } + + /* IN token received when TxFIFO is empty. Applies to non-periodic IN + * endpoints only. This interrupt indicates that an IN token was received + * when the associated TxFIFO (periodic/non-periodic) was empty. This + * interrupt is asserted on the endpoint for which the IN token was + * received. + */ + + if ((diepint & OTG_DIEPINT_ITTXFE) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_ITTXFE), (uint16_t)diepint); + stm32_epin_request(priv, &priv->epin[epno]); + stm32_putreg(OTG_DIEPINT_ITTXFE, STM32_OTG_DIEPINT(epno)); + } + + /* IN endpoint NAK effective (ignored as this used only in polled + * mode) + */ +#if 0 + if ((diepint & OTG_DIEPINT_INEPNE) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_INEPNE), (uint16_t)diepint); + stm32_putreg(OTG_DIEPINT_INEPNE, STM32_OTG_DIEPINT(epno)); + } +#endif + /* Endpoint disabled interrupt (ignored as this used only in polled + * mode) + */ +#if 0 + if ((diepint & OTG_DIEPINT_EPDISD) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EPDISD), (uint16_t)diepint); + stm32_putreg(OTG_DIEPINT_EPDISD, STM32_OTG_DIEPINT(epno)); + } +#endif + /* Transmit FIFO empty */ + + if ((diepint & OTG_DIEPINT_TXFE) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TXFE), (uint16_t)diepint); + + /* If we were waiting for TxFIFO to become empty, the we might have both + * XFRC and TXFE interrupts pending. Since we do the same thing for both + * cases, ignore the TXFE if we have already processed the XFRC. + */ + + if ((diepint & OTG_DIEPINT_XFRC) == 0) + { + /* Mask further FIFO empty interrupts. This will be re-enabled + * whenever we need to wait for a FIFO event. + */ + + empty &= ~OTG_DIEPEMPMSK(epno); + stm32_putreg(empty, STM32_OTG_DIEPEMPMSK); + + /* Handle TxFIFO empty */ + + stm32_epin_txfifoempty(priv, epno); + } + + /* Clear the pending TxFIFO empty interrupt */ + + stm32_putreg(OTG_DIEPINT_TXFE, STM32_OTG_DIEPINT(epno)); + } + } + + epno++; + daint >>= 1; + } +} + +/**************************************************************************** + * Name: stm32_resumeinterrupt + * + * Description: + * Resume/remote wakeup detected interrupt + * + ****************************************************************************/ + +static inline void stm32_resumeinterrupt(FAR struct stm32_usbdev_s *priv) +{ + uint32_t regval; + + /* Restart the PHY clock and un-gate USB core clock (HCLK) */ + +#ifdef CONFIG_USBDEV_LOWPOWER + regval = stm32_getreg(STM32_OTG_PCGCCTL); + regval &= ~(OTG_PCGCCTL_STPPCLK | OTG_PCGCCTL_GATEHCLK); + stm32_putreg(regval, STM32_OTG_PCGCCTL); +#endif + + /* Clear remote wake-up signaling */ + + regval = stm32_getreg(STM32_OTG_DCTL); + regval &= ~OTG_DCTL_RWUSIG; + stm32_putreg(regval, STM32_OTG_DCTL); + + /* Restore full power -- whatever that means for this particular board */ + + stm32_usbsuspend((struct usbdev_s *)priv, true); + + /* Notify the class driver of the resume event */ + + if (priv->driver) + { + CLASS_RESUME(priv->driver, &priv->usbdev); + } +} + +/**************************************************************************** + * Name: stm32_suspendinterrupt + * + * Description: + * USB suspend interrupt + * + ****************************************************************************/ + +static inline void stm32_suspendinterrupt(FAR struct stm32_usbdev_s *priv) +{ +#ifdef CONFIG_USBDEV_LOWPOWER + uint32_t regval; +#endif + + /* Notify the class driver of the suspend event */ + + if (priv->driver) + { + CLASS_SUSPEND(priv->driver, &priv->usbdev); + } + +#ifdef CONFIG_USBDEV_LOWPOWER + /* OTG_DSTS_SUSPSTS is set as long as the suspend condition is detected + * on USB. Check if we are still have the suspend condition, that we are + * connected to the host, and that we have been configured. + */ + + regval = stm32_getreg(STM32_OTG_DSTS); + + if ((regval & OTG_DSTS_SUSPSTS) != 0 && devstate == DEVSTATE_CONFIGURED) + { + /* Switch off OTG clocking. Setting OTG_PCGCCTL_STPPCLK stops the + * PHY clock. + */ + + regval = stm32_getreg(STM32_OTG_PCGCCTL); + regval |= OTG_PCGCCTL_STPPCLK; + stm32_putreg(regval, STM32_OTG_PCGCCTL); + + /* Setting OTG_PCGCCTL_GATEHCLK gate HCLK to modules other than + * the AHB Slave and Master and wakeup logic. + */ + + regval |= OTG_PCGCCTL_GATEHCLK; + stm32_putreg(regval, STM32_OTG_PCGCCTL); + } +#endif + + /* Let the board-specific logic know that we have entered the suspend + * state + */ + + stm32_usbsuspend((FAR struct usbdev_s *)priv, false); +} + +/**************************************************************************** + * Name: stm32_rxinterrupt + * + * Description: + * RxFIFO non-empty interrupt. This interrupt indicates that there is at + * least one packet pending to be read from the RxFIFO. + * + ****************************************************************************/ + +static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) +{ + FAR struct stm32_ep_s *privep; + uint32_t regval; + int bcnt; + int epphy; + + /* Disable the Rx status queue level interrupt */ + + regval = stm32_getreg(STM32_OTG_GINTMSK); + regval &= ~OTG_GINT_RXFLVL; + stm32_putreg(regval, STM32_OTG_GINTMSK); + + /* Get the status from the top of the FIFO */ + + regval = stm32_getreg(STM32_OTG_GRXSTSP); + + /* Decode status fields */ + + epphy = (regval & OTG_GRXSTSD_EPNUM_MASK) >> OTG_GRXSTSD_EPNUM_SHIFT; + + if (epphy < STM32_NENDPOINTS) + { + privep = &priv->epout[epphy]; + + /* Handle the RX event according to the packet status field */ + + switch (regval & OTG_GRXSTSD_PKTSTS_MASK) + { + /* Global OUT NAK. This indicate that the global OUT NAK bit has taken + * effect. + * + * PKTSTS = Global OUT NAK, BCNT = 0, EPNUM = Don't Care, DPID = Don't + * Care. + */ + + case OTG_GRXSTSD_PKTSTS_OUTNAK: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTNAK), 0); + } + break; + + /* OUT data packet received. + * + * PKTSTS = DataOUT, BCNT = size of the received data OUT packet, + * EPNUM = EPNUM on which the packet was received, DPID = Actual Data PID. + */ + + case OTG_GRXSTSD_PKTSTS_OUTRECVD: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTRECVD), epphy); + bcnt = (regval & OTG_GRXSTSD_BCNT_MASK) >> OTG_GRXSTSD_BCNT_SHIFT; + if (bcnt > 0) + { + stm32_epout_receive(privep, bcnt); + } + } + break; + + /* OUT transfer completed. This indicates that an OUT data transfer for + * the specified OUT endpoint has completed. After this entry is popped + * from the receive FIFO, the core asserts a Transfer Completed interrupt + * on the specified OUT endpoint. + * + * PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP Num on + * which the data transfer is complete, DPID = Don't Care. + */ + + case OTG_GRXSTSD_PKTSTS_OUTDONE: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTDONE), epphy); + } + break; + + /* SETUP transaction completed. This indicates that the Setup stage for + * the specified endpoint has completed and the Data stage has started. + * After this entry is popped from the receive FIFO, the core asserts a + * Setup interrupt on the specified control OUT endpoint (triggers an + * interrupt). + * + * PKTSTS = Setup Stage Done, BCNT = 0, EPNUM = Control EP Num, + * DPID = Don't Care. + */ + + case OTG_GRXSTSD_PKTSTS_SETUPDONE: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy); + } + break; + + /* SETUP data packet received. This indicates that a SETUP packet for the + * specified endpoint is now available for reading from the receive FIFO. + * + * PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0. + */ + + case OTG_GRXSTSD_PKTSTS_SETUPRECVD: + { + uint16_t datlen; + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), epphy); + + /* Read EP0 setup data. NOTE: If multiple SETUP packets are received, + * the last one overwrites the previous setup packets and only that + * last SETUP packet will be processed. + */ + + stm32_rxfifo_read(&priv->epout[EP0], (FAR uint8_t *)&priv->ctrlreq, + USB_SIZEOF_CTRLREQ); + + /* Was this an IN or an OUT SETUP packet. If it is an OUT SETUP, + * then we need to wait for the completion of the data phase to + * process the setup command. If it is an IN SETUP packet, then + * we must processing the command BEFORE we enter the DATA phase. + * + * If the data associated with the OUT SETUP packet is zero length, + * then, of course, we don't need to wait. + */ + + datlen = GETUINT16(priv->ctrlreq.len); + if (USB_REQ_ISOUT(priv->ctrlreq.type) && datlen > 0) + { + /* Clear NAKSTS so that we can receive the data */ + + regval = stm32_getreg(STM32_OTG_DOEPCTL0); + regval |= OTG_DOEPCTL0_CNAK; + stm32_putreg(regval, STM32_OTG_DOEPCTL0); + + /* Wait for the data phase. */ + + priv->ep0state = EP0STATE_SETUP_OUT; + } + else + { + /* We can process the setup data as soon as SETUP done word is + * popped of the RxFIFO. + */ + + priv->ep0state = EP0STATE_SETUP_READY; + } + } + break; + + default: + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), + (regval & OTG_GRXSTSD_PKTSTS_MASK) >> OTG_GRXSTSD_PKTSTS_SHIFT); + } + break; + } + } + + /* Enable the Rx Status Queue Level interrupt */ + + regval = stm32_getreg(STM32_OTG_GINTMSK); + regval |= OTG_GINT_RXFLVL; + stm32_putreg(regval, STM32_OTG_GINTMSK); +} + +/**************************************************************************** + * Name: stm32_enuminterrupt + * + * Description: + * Enumeration done interrupt + * + ****************************************************************************/ + +static inline void stm32_enuminterrupt(FAR struct stm32_usbdev_s *priv) +{ + uint32_t regval; + + /* Activate EP0 */ + + stm32_ep0in_activate(); + + /* Set USB turn-around time for the full speed device with internal PHY interface. */ + + regval = stm32_getreg(STM32_OTG_GUSBCFG); + regval &= ~OTG_GUSBCFG_TRDT_MASK; + regval |= OTG_GUSBCFG_TRDT(5); + stm32_putreg(regval, STM32_OTG_GUSBCFG); +} + +/**************************************************************************** + * Name: stm32_isocininterrupt + * + * Description: + * Incomplete isochronous IN transfer interrupt. Assertion of the incomplete + * isochronous IN transfer interrupt indicates an incomplete isochronous IN + * transfer on at least one of the isochronous IN endpoints. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_ISOCHRONOUS +static inline void stm32_isocininterrupt(FAR struct stm32_usbdev_s *priv) +{ + int i; + + /* The application must read the endpoint control register for all isochronous + * IN endpoints to detect endpoints with incomplete IN data transfers. + */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + /* Is this an isochronous IN endpoint? */ + + privep = &priv->epin[i]; + if (privep->eptype != USB_EP_ATTR_XFER_ISOC) + { + /* No... keep looking */ + + continue; + } + + /* Is there an active read request on the isochronous OUT endpoint? */ + + if (!privep->active) + { + /* No.. the endpoint is not actively transmitting data */ + + continue; + } + + /* Check if this is the endpoint that had the incomplete transfer */ + + regaddr = STM32_OTG_DIEPCTL(privep->epphy); + doepctl = stm32_getreg(regaddr); + dsts = stm32_getreg(STM32_OTG_DSTS); + + /* EONUM = 0:even frame, 1:odd frame + * SOFFN = Frame number of the received SOF + */ + + eonum = ((doepctl & OTG_DIEPCTL_EONUM) != 0); + soffn = ((dsts & OTG_DSTS_SOFFN0) != 0); + + if (eonum != soffn) + { + /* Not this endpoint */ + + continue; + } + + /* For isochronous IN endpoints with incomplete transfers, + * the application must discard the data in the memory and + * disable the endpoint. + */ + + stm32_req_complete(privep, -EIO); +#warning "Will clear OTG_DIEPCTL_USBAEP too" + stm32_epin_disable(privep); + break; + } +} +#endif + +/**************************************************************************** + * Name: stm32_isocoutinterrupt + * + * Description: + * Incomplete periodic transfer interrupt + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_ISOCHRONOUS +static inline void stm32_isocoutinterrupt(FAR struct stm32_usbdev_s *priv) +{ + FAR struct stm32_ep_s *privep; + FAR struct stm32_req_s *privreq; + uint32_t regaddr; + uint32_t doepctl; + uint32_t dsts; + bool eonum; + bool soffn; + + /* When it receives an IISOOXFR interrupt, the application must read the + * control registers of all isochronous OUT endpoints to determine which + * endpoints had an incomplete transfer in the current microframe. An + * endpoint transfer is incomplete if both the following conditions are true: + * + * DOEPCTLx:EONUM = DSTS:SOFFN[0], and + * DOEPCTLx:EPENA = 1 + */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + /* Is this an isochronous OUT endpoint? */ + + privep = &priv->epout[i]; + if (privep->eptype != USB_EP_ATTR_XFER_ISOC) + { + /* No... keep looking */ + + continue; + } + + /* Is there an active read request on the isochronous OUT endpoint? */ + + if (!privep->active) + { + /* No.. the endpoint is not actively transmitting data */ + + continue; + } + + /* Check if this is the endpoint that had the incomplete transfer */ + + regaddr = STM32_OTG_DOEPCTL(privep->epphy); + doepctl = stm32_getreg(regaddr); + dsts = stm32_getreg(STM32_OTG_DSTS); + + /* EONUM = 0:even frame, 1:odd frame + * SOFFN = Frame number of the received SOF + */ + + eonum = ((doepctl & OTG_DOEPCTL_EONUM) != 0); + soffn = ((dsts & OTG_DSTS_SOFFN0) != 0); + + if (eonum != soffn) + { + /* Not this endpoint */ + + continue; + } + + /* For isochronous OUT endpoints with incomplete transfers, + * the application must discard the data in the memory and + * disable the endpoint. + */ + + stm32_req_complete(privep, -EIO); +#warning "Will clear OTG_DOEPCTL_USBAEP too" + stm32_epout_disable(privep); + break; + } +} +#endif + +/**************************************************************************** + * Name: stm32_sessioninterrupt + * + * Description: + * Session request/new session detected interrupt + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_VBUSSENSING +static inline void stm32_sessioninterrupt(FAR struct stm32_usbdev_s *priv) +{ +#warning "Missing logic" +} +#endif + +/**************************************************************************** + * Name: stm32_otginterrupt + * + * Description: + * OTG interrupt + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_VBUSSENSING +static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv) +{ + uint32_t regval; + + /* Check for session end detected */ + + regval = stm32_getreg(STM32_OTG_GOTGINT); + if ((regval & OTG_GOTGINT_SEDET) != 0) + { +#warning "Missing logic" + } + + /* Clear OTG interrupt */ + + stm32_putreg(retval, STM32_OTG_GOTGINT); +} +#endif + +/**************************************************************************** + * Name: stm32_usbinterrupt + * + * Description: + * USB interrupt handler + * + ****************************************************************************/ + +static int stm32_usbinterrupt(int irq, FAR void *context) +{ + /* At present, there is only a single OTG device support. Hence it is + * pre-allocated as g_otghsdev. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple devices. + */ + + FAR struct stm32_usbdev_s *priv = &g_otghsdev; + uint32_t regval; + + usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_USB), 0); + + /* Assure that we are in device mode */ + + DEBUGASSERT((stm32_getreg(STM32_OTG_GINTSTS) & OTG_GINTSTS_CMOD) == OTG_GINTSTS_DEVMODE); + + /* Get the state of all enabled interrupts. We will do this repeatedly + * some interrupts (like RXFLVL) will generate additional interrupting + * events. + */ + + for (; ; ) + { + /* Get the set of pending, un-masked interrupts */ + + regval = stm32_getreg(STM32_OTG_GINTSTS); + regval &= stm32_getreg(STM32_OTG_GINTMSK); + + /* Break out of the loop when there are no further pending (and + * unmasked) interrupts to be processes. + */ + + if (regval == 0) + { + break; + } + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_INTPENDING), (uint16_t)regval); + + /* OUT endpoint interrupt. The core sets this bit to indicate that an + * interrupt is pending on one of the OUT endpoints of the core. + */ + + if ((regval & OTG_GINT_OEP) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT), (uint16_t)regval); + stm32_epout_interrupt(priv); + stm32_putreg(OTG_GINT_OEP, STM32_OTG_GINTSTS); + } + + /* IN endpoint interrupt. The core sets this bit to indicate that + * an interrupt is pending on one of the IN endpoints of the core. + */ + + if ((regval & OTG_GINT_IEP) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN), (uint16_t)regval); + stm32_epin_interrupt(priv); + stm32_putreg(OTG_GINT_IEP, STM32_OTG_GINTSTS); + } + + /* Host/device mode mismatch error interrupt */ + +#ifdef CONFIG_DEBUG_USB + if ((regval & OTG_GINT_MMIS) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_MISMATCH), (uint16_t)regval); + stm32_putreg(OTG_GINT_MMIS, STM32_OTG_GINTSTS); + } +#endif + + /* Resume/remote wakeup detected interrupt */ + + if ((regval & OTG_GINT_WKUP) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WAKEUP), (uint16_t)regval); + stm32_resumeinterrupt(priv); + stm32_putreg(OTG_GINT_WKUP, STM32_OTG_GINTSTS); + } + + /* USB suspend interrupt */ + + if ((regval & OTG_GINT_USBSUSP) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSPEND), (uint16_t)regval); + stm32_suspendinterrupt(priv); + stm32_putreg(OTG_GINT_USBSUSP, STM32_OTG_GINTSTS); + } + + /* Start of frame interrupt */ + +#ifdef CONFIG_USBDEV_SOFINTERRUPT + if ((regval & OTG_GINT_SOF) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SOF), (uint16_t)regval); + stm32_putreg(OTG_GINT_SOF, STM32_OTG_GINTSTS); + } +#endif + + /* RxFIFO non-empty interrupt. Indicates that there is at least one + * packet pending to be read from the RxFIFO. + */ + + if ((regval & OTG_GINT_RXFLVL) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RXFIFO), (uint16_t)regval); + stm32_rxinterrupt(priv); + stm32_putreg(OTG_GINT_RXFLVL, STM32_OTG_GINTSTS); + } + + /* USB reset interrupt */ + + if ((regval & OTG_GINT_USBRST) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVRESET), (uint16_t)regval); + + /* Perform the device reset */ + + stm32_usbreset(priv); + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), 0); + stm32_putreg(OTG_GINT_USBRST, STM32_OTG_GINTSTS); + return OK; + } + + /* Enumeration done interrupt */ + + if ((regval & OTG_GINT_ENUMDNE) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ENUMDNE), (uint16_t)regval); + stm32_enuminterrupt(priv); + stm32_putreg(OTG_GINT_ENUMDNE, STM32_OTG_GINTSTS); + } + + /* Incomplete isochronous IN transfer interrupt. When the core finds + * non-empty any of the isochronous IN endpoint FIFOs scheduled for + * the current frame non-empty, the core generates an IISOIXFR + * interrupt. + */ + +#ifdef CONFIG_USBDEV_ISOCHRONOUS + if ((regval & OTG_GINT_IISOIXFR) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOIXFR), (uint16_t)regval); + stm32_isocininterrupt(priv); + stm32_putreg(OTG_GINT_IISOIXFR, STM32_OTG_GINTSTS); + } + + /* Incomplete isochronous OUT transfer. For isochronous OUT + * endpoints, the XFRC interrupt may not always be asserted. If the + * core drops isochronous OUT data packets, the application could fail + * to detect the XFRC interrupt. The incomplete Isochronous OUT data + * interrupt indicates that an XFRC interrupt was not asserted on at + * least one of the isochronous OUT endpoints. At this point, the + * endpoint with the incomplete transfer remains enabled, but no active + * transfers remain in progress on this endpoint on the USB. + */ + + if ((regval & OTG_GINT_IISOOXFR) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOOXFR), (uint16_t)regval); + stm32_isocoutinterrupt(priv); + stm32_putreg(OTG_GINT_IISOOXFR, STM32_OTG_GINTSTS); + } +#endif + + /* Session request/new session detected interrupt */ + +#ifdef CONFIG_USBDEV_VBUSSENSING + if ((regval & OTG_GINT_SRQ) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SRQ), (uint16_t)regval); + stm32_sessioninterrupt(priv); + stm32_putreg(OTG_GINT_SRQ, STM32_OTG_GINTSTS); + } + + /* OTG interrupt */ + + if ((regval & OTG_GINT_OTG) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OTG), (uint16_t)regval); + stm32_otginterrupt(priv); + stm32_putreg(OTG_GINT_OTG, STM32_OTG_GINTSTS); + } +#endif + } + + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), 0); + return OK; +} + +/**************************************************************************** + * Endpoint operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_enablegonak + * + * Description: + * Enable global OUT NAK mode + * + ****************************************************************************/ + +static void stm32_enablegonak(FAR struct stm32_ep_s *privep) +{ + uint32_t regval; + + /* First, make sure that there is no GNOAKEFF interrupt pending. */ + +#if 0 + stm32_putreg(OTG_GINT_GONAKEFF, STM32_OTG_GINTSTS); +#endif + + /* Enable Global OUT NAK mode in the core. */ + + regval = stm32_getreg(STM32_OTG_DCTL); + regval |= OTG_DCTL_SGONAK; + stm32_putreg(regval, STM32_OTG_DCTL); + +#if 0 + /* Wait for the GONAKEFF interrupt that indicates that the OUT NAK + * mode is in effect. When the interrupt handler pops the OUTNAK word + * from the RxFIFO, the core sets the GONAKEFF interrupt. + */ + + while ((stm32_getreg(STM32_OTG_GINTSTS) & OTG_GINT_GONAKEFF) == 0); + stm32_putreg(OTG_GINT_GONAKEFF, STM32_OTG_GINTSTS); + +#else + /* Since we are in the interrupt handler, we cannot wait inline for the + * GONAKEFF because it cannot occur until service the RXFLVL global interrupt + * and pop the OUTNAK word from the RxFIFO. + * + * Perhaps it is sufficient to wait for Global OUT NAK status to be reported + * in OTG DCTL register? + */ + + while ((stm32_getreg(STM32_OTG_DCTL) & OTG_DCTL_GONSTS) == 0); +#endif +} + +/**************************************************************************** + * Name: stm32_disablegonak + * + * Description: + * Disable global OUT NAK mode + * + ****************************************************************************/ + +static void stm32_disablegonak(FAR struct stm32_ep_s *privep) +{ + uint32_t regval; + + /* Set the "Clear the Global OUT NAK bit" to disable global OUT NAK mode */ + + regval = stm32_getreg(STM32_OTG_DCTL); + regval |= OTG_DCTL_CGONAK; + stm32_putreg(regval, STM32_OTG_DCTL); +} + +/**************************************************************************** + * Name: stm32_epout_configure + * + * Description: + * Configure an OUT endpoint, making it usable + * + * Input Parameters: + * privep - a pointer to an internal endpoint structure + * eptype - The type of the endpoint + * maxpacket - The max packet size of the endpoint + * + ****************************************************************************/ + +static int stm32_epout_configure(FAR struct stm32_ep_s *privep, uint8_t eptype, + uint16_t maxpacket) +{ + uint32_t mpsiz; + uint32_t regaddr; + uint32_t regval; + + usbtrace(TRACE_EPCONFIGURE, privep->epphy); + + /* For EP0, the packet size is encoded */ + + if (privep->epphy == EP0) + { + DEBUGASSERT(eptype == USB_EP_ATTR_XFER_CONTROL); + + /* Map the size in bytes to the encoded value in the register */ + + switch (maxpacket) + { + case 8: + mpsiz = OTG_DOEPCTL0_MPSIZ_8; + break; + + case 16: + mpsiz = OTG_DOEPCTL0_MPSIZ_16; + break; + + case 32: + mpsiz = OTG_DOEPCTL0_MPSIZ_32; + break; + + case 64: + mpsiz = OTG_DOEPCTL0_MPSIZ_64; + break; + + default: + uerr("Unsupported maxpacket: %d\n", maxpacket); + return -EINVAL; + } + } + + /* For other endpoints, the packet size is in bytes */ + + else + { + mpsiz = (maxpacket << OTG_DOEPCTL_MPSIZ_SHIFT); + } + + /* If the endpoint is already active don't change the endpoint control + * register. + */ + + regaddr = STM32_OTG_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + if ((regval & OTG_DOEPCTL_USBAEP) == 0) + { + if (regval & OTG_DOEPCTL_NAKSTS) + { + regval |= OTG_DOEPCTL_CNAK; + } + + regval &= ~(OTG_DOEPCTL_MPSIZ_MASK | OTG_DOEPCTL_EPTYP_MASK); + regval |= mpsiz; + regval |= (eptype << OTG_DOEPCTL_EPTYP_SHIFT); + regval |= (OTG_DOEPCTL_SD0PID | OTG_DOEPCTL_USBAEP); + stm32_putreg(regval, regaddr); + + /* Save the endpoint configuration */ + + privep->ep.maxpacket = maxpacket; + privep->eptype = eptype; + privep->stalled = false; + } + + /* Enable the interrupt for this endpoint */ + + regval = stm32_getreg(STM32_OTG_DAINTMSK); + regval |= OTG_DAINT_OEP(privep->epphy); + stm32_putreg(regval, STM32_OTG_DAINTMSK); + return OK; +} + +/**************************************************************************** + * Name: stm32_epin_configure + * + * Description: + * Configure an IN endpoint, making it usable + * + * Input Parameters: + * privep - a pointer to an internal endpoint structure + * eptype - The type of the endpoint + * maxpacket - The max packet size of the endpoint + * + ****************************************************************************/ + +static int stm32_epin_configure(FAR struct stm32_ep_s *privep, uint8_t eptype, + uint16_t maxpacket) +{ + uint32_t mpsiz; + uint32_t regaddr; + uint32_t regval; + + usbtrace(TRACE_EPCONFIGURE, privep->epphy); + + /* For EP0, the packet size is encoded */ + + if (privep->epphy == EP0) + { + DEBUGASSERT(eptype == USB_EP_ATTR_XFER_CONTROL); + + /* Map the size in bytes to the encoded value in the register */ + + switch (maxpacket) + { + case 8: + mpsiz = OTG_DIEPCTL0_MPSIZ_8; + break; + + case 16: + mpsiz = OTG_DIEPCTL0_MPSIZ_16; + break; + + case 32: + mpsiz = OTG_DIEPCTL0_MPSIZ_32; + break; + + case 64: + mpsiz = OTG_DIEPCTL0_MPSIZ_64; + break; + + default: + uerr("Unsupported maxpacket: %d\n", maxpacket); + return -EINVAL; + } + } + + /* For other endpoints, the packet size is in bytes */ + + else + { + mpsiz = (maxpacket << OTG_DIEPCTL_MPSIZ_SHIFT); + } + + + /* If the endpoint is already active don't change the endpoint control + * register. + */ + + regaddr = STM32_OTG_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + if ((regval & OTG_DIEPCTL_USBAEP) == 0) + { + if (regval & OTG_DIEPCTL_NAKSTS) + { + regval |= OTG_DIEPCTL_CNAK; + } + + regval &= ~(OTG_DIEPCTL_MPSIZ_MASK | OTG_DIEPCTL_EPTYP_MASK | OTG_DIEPCTL_TXFNUM_MASK); + regval |= mpsiz; + regval |= (eptype << OTG_DIEPCTL_EPTYP_SHIFT); + regval |= (eptype << OTG_DIEPCTL_TXFNUM_SHIFT); + regval |= (OTG_DIEPCTL_SD0PID | OTG_DIEPCTL_USBAEP); + stm32_putreg(regval, regaddr); + + /* Save the endpoint configuration */ + + privep->ep.maxpacket = maxpacket; + privep->eptype = eptype; + privep->stalled = false; + } + + /* Enable the interrupt for this endpoint */ + + regval = stm32_getreg(STM32_OTG_DAINTMSK); + regval |= OTG_DAINT_IEP(privep->epphy); + stm32_putreg(regval, STM32_OTG_DAINTMSK); + + return OK; +} + +/**************************************************************************** + * Name: stm32_ep_configure + * + * Description: + * Configure endpoint, making it usable + * + * Input Parameters: + * ep - the struct usbdev_ep_s instance obtained from allocep() + * desc - A struct usb_epdesc_s instance describing the endpoint + * last - true if this this last endpoint to be configured. Some hardware + * needs to take special action when all of the endpoints have been + * configured. + * + ****************************************************************************/ + +static int stm32_ep_configure(FAR struct usbdev_ep_s *ep, + FAR const struct usb_epdesc_s *desc, + bool last) +{ + FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep; + uint16_t maxpacket; + uint8_t eptype; + int ret; + + usbtrace(TRACE_EPCONFIGURE, privep->epphy); + DEBUGASSERT(desc->addr == ep->eplog); + + /* Initialize EP capabilities */ + + maxpacket = GETUINT16(desc->mxpacketsize); + eptype = desc->attr & USB_EP_ATTR_XFERTYPE_MASK; + + /* Setup Endpoint Control Register */ + + if (privep->isin) + { + ret = stm32_epin_configure(privep, eptype, maxpacket); + } + else + { + ret = stm32_epout_configure(privep, eptype, maxpacket); + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_ep0_configure + * + * Description: + * Reset Usb engine + * + ****************************************************************************/ + +static void stm32_ep0_configure(FAR struct stm32_usbdev_s *priv) +{ + /* Enable EP0 IN and OUT */ + + (void)stm32_epin_configure(&priv->epin[EP0], USB_EP_ATTR_XFER_CONTROL, + CONFIG_USBDEV_EP0_MAXSIZE); + (void)stm32_epout_configure(&priv->epout[EP0], USB_EP_ATTR_XFER_CONTROL, + CONFIG_USBDEV_EP0_MAXSIZE); +} + +/**************************************************************************** + * Name: stm32_epout_disable + * + * Description: + * Diable an OUT endpoint will no longer be used + * + ****************************************************************************/ + +static void stm32_epout_disable(FAR struct stm32_ep_s *privep) +{ + uint32_t regaddr; + uint32_t regval; + irqstate_t flags; + + usbtrace(TRACE_EPDISABLE, privep->epphy); + + /* Is this an IN or an OUT endpoint */ + + /* Before disabling any OUT endpoint, the application must enable + * Global OUT NAK mode in the core. + */ + + flags = enter_critical_section(); + stm32_enablegonak(privep); + + /* Disable the required OUT endpoint by setting the EPDIS and SNAK bits + * int DOECPTL register. + */ + + regaddr = STM32_OTG_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval &= ~OTG_DOEPCTL_USBAEP; + regval |= (OTG_DOEPCTL_EPDIS | OTG_DOEPCTL_SNAK); + stm32_putreg(regval, regaddr); + + /* Wait for the EPDISD interrupt which indicates that the OUT + * endpoint is completely disabled. + */ + +#if 0 /* Doesn't happen */ + regaddr = STM32_OTG_DOEPINT(privep->epphy); + while ((stm32_getreg(regaddr) & OTG_DOEPINT_EPDISD) == 0); +#else + /* REVISIT: */ + up_udelay(10); +#endif + + /* Clear the EPDISD interrupt indication */ + + stm32_putreg(OTG_DOEPINT_EPDISD, STM32_OTG_DOEPINT(privep->epphy)); + + /* Then disable the Global OUT NAK mode to continue receiving data + * from other non-disabled OUT endpoints. + */ + + stm32_disablegonak(privep); + + /* Disable endpoint interrupts */ + + regval = stm32_getreg(STM32_OTG_DAINTMSK); + regval &= ~OTG_DAINT_OEP(privep->epphy); + stm32_putreg(regval, STM32_OTG_DAINTMSK); + + /* Cancel any queued read requests */ + + stm32_req_cancel(privep, -ESHUTDOWN); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: stm32_epin_disable + * + * Description: + * Disable an IN endpoint when it will no longer be used + * + ****************************************************************************/ + +static void stm32_epin_disable(FAR struct stm32_ep_s *privep) +{ + uint32_t regaddr; + uint32_t regval; + irqstate_t flags; + + usbtrace(TRACE_EPDISABLE, privep->epphy); + + /* After USB reset, the endpoint will already be deactivated by the + * hardware. Trying to disable again will just hang in the wait. + */ + + regaddr = STM32_OTG_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + if ((regval & OTG_DIEPCTL_USBAEP) == 0) + { + return; + } + + /* This INEPNE wait logic is suggested by reference manual, but seems + * to get stuck to infinite loop. + */ + +#if 0 + /* Make sure that there is no pending IPEPNE interrupt (because we are + * to poll this bit below). + */ + + stm32_putreg(OTG_DIEPINT_INEPNE, STM32_OTG_DIEPINT(privep->epphy)); + + /* Set the endpoint in NAK mode */ + + regaddr = STM32_OTG_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval &= ~OTG_DIEPCTL_USBAEP; + regval |= (OTG_DIEPCTL_EPDIS | OTG_DIEPCTL_SNAK); + stm32_putreg(regval, regaddr); + + /* Wait for the INEPNE interrupt that indicates that we are now in NAK mode */ + + regaddr = STM32_OTG_DIEPINT(privep->epphy); + while ((stm32_getreg(regaddr) & OTG_DIEPINT_INEPNE) == 0); + + /* Clear the INEPNE interrupt indication */ + + stm32_putreg(OTG_DIEPINT_INEPNE, regaddr); +#endif + + /* Deactivate and disable the endpoint by setting the EPDIS and SNAK bits + * the DIEPCTLx register. + */ + + flags = enter_critical_section(); + regaddr = STM32_OTG_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval &= ~OTG_DIEPCTL_USBAEP; + regval |= (OTG_DIEPCTL_EPDIS | OTG_DIEPCTL_SNAK); + stm32_putreg(regval, regaddr); + + /* Wait for the EPDISD interrupt which indicates that the IN + * endpoint is completely disabled. + */ + + regaddr = STM32_OTG_DIEPINT(privep->epphy); + while ((stm32_getreg(regaddr) & OTG_DIEPINT_EPDISD) == 0); + + /* Clear the EPDISD interrupt indication */ + + stm32_putreg(OTG_DIEPINT_EPDISD, stm32_getreg(regaddr)); + + /* Flush any data remaining in the TxFIFO */ + + stm32_txfifo_flush(OTG_GRSTCTL_TXFNUM_D(privep->epphy)); + + /* Disable endpoint interrupts */ + + regval = stm32_getreg(STM32_OTG_DAINTMSK); + regval &= ~OTG_DAINT_IEP(privep->epphy); + stm32_putreg(regval, STM32_OTG_DAINTMSK); + + /* Cancel any queued write requests */ + + stm32_req_cancel(privep, -ESHUTDOWN); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: stm32_ep_disable + * + * Description: + * The endpoint will no longer be used + * + ****************************************************************************/ + +static int stm32_ep_disable(FAR struct usbdev_ep_s *ep) +{ + FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPDISABLE, privep->epphy); + + /* Is this an IN or an OUT endpoint */ + + if (privep->isin) + { + /* Disable the IN endpoint */ + + stm32_epin_disable(privep); + } + else + { + /* Disable the OUT endpoint */ + + stm32_epout_disable(privep); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_ep_allocreq + * + * Description: + * Allocate an I/O request + * + ****************************************************************************/ + +static FAR struct usbdev_req_s *stm32_ep_allocreq(FAR struct usbdev_ep_s *ep) +{ + FAR struct stm32_req_s *privreq; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return NULL; + } +#endif + + usbtrace(TRACE_EPALLOCREQ, ((FAR struct stm32_ep_s *)ep)->epphy); + + privreq = (FAR struct stm32_req_s *)kmm_malloc(sizeof(struct stm32_req_s)); + if (!privreq) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); + return NULL; + } + + memset(privreq, 0, sizeof(struct stm32_req_s)); + return &privreq->req; +} + +/**************************************************************************** + * Name: stm32_ep_freereq + * + * Description: + * Free an I/O request + * + ****************************************************************************/ + +static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) +{ + FAR struct stm32_req_s *privreq = (FAR struct stm32_req_s *)req; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep || !req) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return; + } +#endif + + usbtrace(TRACE_EPFREEREQ, ((FAR struct stm32_ep_s *)ep)->epphy); + kmm_free(privreq); +} + +/**************************************************************************** + * Name: stm32_ep_allocbuffer + * + * Description: + * Allocate an I/O buffer + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_DMA +static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes) +{ + usbtrace(TRACE_EPALLOCBUFFER, privep->epphy); + +#ifdef CONFIG_USBDEV_DMAMEMORY + return usbdev_dma_alloc(bytes); +#else + return kmm_malloc(bytes); +#endif +} +#endif + +/**************************************************************************** + * Name: stm32_ep_freebuffer + * + * Description: + * Free an I/O buffer + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_DMA +static void stm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf) +{ + usbtrace(TRACE_EPFREEBUFFER, privep->epphy); + +#ifdef CONFIG_USBDEV_DMAMEMORY + usbdev_dma_free(buf); +#else + kmm_free(buf); +#endif +} +#endif + +/**************************************************************************** + * Name: stm32_ep_submit + * + * Description: + * Submit an I/O request to the endpoint + * + ****************************************************************************/ + +static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) +{ + FAR struct stm32_req_s *privreq = (FAR struct stm32_req_s *)req; + FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep; + FAR struct stm32_usbdev_s *priv; + irqstate_t flags; + int ret = OK; + + /* Some sanity checking */ + +#ifdef CONFIG_DEBUG_FEATURES + if (!req || !req->callback || !req->buf || !ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + ullinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPSUBMIT, privep->epphy); + priv = privep->dev; + +#ifdef CONFIG_DEBUG_FEATURES + if (!priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); + return -ESHUTDOWN; + } +#endif + + /* Handle the request from the class driver */ + + req->result = -EINPROGRESS; + req->xfrd = 0; + + /* Disable Interrupts */ + + flags = enter_critical_section(); + + /* If we are stalled, then drop all requests on the floor */ + + if (privep->stalled) + { + ret = -EBUSY; + } + else + { + /* Add the new request to the request queue for the endpoint. */ + + if (stm32_req_addlast(privep, privreq) && !privep->active) + { + /* If a request was added to an IN endpoint, then attempt to send + * the request data buffer now. + */ + + if (privep->isin) + { + usbtrace(TRACE_INREQQUEUED(privep->epphy), privreq->req.len); + + /* If the endpoint is not busy with another write request, + * then process the newly received write request now. + */ + + if (!privep->active) + { + stm32_epin_request(priv, privep); + } + } + + /* If the request was added to an OUT endpoint, then attempt to + * setup a read into the request data buffer now (this will, of + * course, fail if there is already a read in place). + */ + + else + { + usbtrace(TRACE_OUTREQQUEUED(privep->epphy), privreq->req.len); + stm32_epout_request(priv, privep); + } + } + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: stm32_ep_cancel + * + * Description: + * Cancel an I/O request previously sent to an endpoint + * + ****************************************************************************/ + +static int stm32_ep_cancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) +{ + FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep; + irqstate_t flags; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep || !req) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPCANCEL, privep->epphy); + + flags = enter_critical_section(); + + /* FIXME: if the request is the first, then we need to flush the EP + * otherwise just remove it from the list + * + * but ... all other implementations cancel all requests ... + */ + + stm32_req_cancel(privep, -ESHUTDOWN); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_epout_setstall + * + * Description: + * Stall an OUT endpoint + * + ****************************************************************************/ + +static int stm32_epout_setstall(FAR struct stm32_ep_s *privep) +{ +#if 1 + /* This implementation follows the requirements from the STM32 F4 reference + * manual. + */ + + uint32_t regaddr; + uint32_t regval; + + /* Put the core in the Global OUT NAK mode */ + + stm32_enablegonak(privep); + + /* Disable and STALL the OUT endpoint by setting the EPDIS and STALL bits + * in the DOECPTL register. + */ + + regaddr = STM32_OTG_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval |= (OTG_DOEPCTL_EPDIS | OTG_DOEPCTL_STALL); + stm32_putreg(regval, regaddr); + + /* Wait for the EPDISD interrupt which indicates that the OUT + * endpoint is completely disabled. + */ + +#if 0 /* Doesn't happen */ + regaddr = STM32_OTG_DOEPINT(privep->epphy); + while ((stm32_getreg(regaddr) & OTG_DOEPINT_EPDISD) == 0); +#else + /* REVISIT: */ + up_udelay(10); +#endif + + /* Disable Global OUT NAK mode */ + + stm32_disablegonak(privep); + + /* The endpoint is now stalled */ + + privep->stalled = true; + return OK; +#else + /* This implementation follows the STMicro code example. */ + /* REVISIT: */ + + uint32_t regaddr; + uint32_t regval; + + /* Stall the OUT endpoint by setting the STALL bit in the DOECPTL register. */ + + regaddr = STM32_OTG_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval |= OTG_DOEPCTL_STALL; + stm32_putreg(regval, regaddr); + + /* The endpoint is now stalled */ + + privep->stalled = true; + return OK; +#endif +} + +/**************************************************************************** + * Name: stm32_epin_setstall + * + * Description: + * Stall an IN endpoint + * + ****************************************************************************/ + +static int stm32_epin_setstall(FAR struct stm32_ep_s *privep) +{ + uint32_t regaddr; + uint32_t regval; + + /* Get the IN endpoint device control register */ + + regaddr = STM32_OTG_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + + /* Then stall the endpoint */ + + regval |= OTG_DIEPCTL_STALL; + stm32_putreg(regval, regaddr); + + /* The endpoint is now stalled */ + + privep->stalled = true; + return OK; +} + +/**************************************************************************** + * Name: stm32_ep_setstall + * + * Description: + * Stall an endpoint + * + ****************************************************************************/ + +static int stm32_ep_setstall(FAR struct stm32_ep_s *privep) +{ + usbtrace(TRACE_EPSTALL, privep->epphy); + + /* Is this an IN endpoint? */ + + if (privep->isin == 1) + { + return stm32_epin_setstall(privep); + } + else + { + return stm32_epout_setstall(privep); + } +} + +/**************************************************************************** + * Name: stm32_ep_clrstall + * + * Description: + * Resume a stalled endpoint + * + ****************************************************************************/ + +static int stm32_ep_clrstall(FAR struct stm32_ep_s *privep) +{ + uint32_t regaddr; + uint32_t regval; + uint32_t stallbit; + uint32_t data0bit; + + usbtrace(TRACE_EPRESUME, privep->epphy); + + /* Is this an IN endpoint? */ + + if (privep->isin == 1) + { + /* Clear the stall bit in the IN endpoint device control register */ + + regaddr = STM32_OTG_DIEPCTL(privep->epphy); + stallbit = OTG_DIEPCTL_STALL; + data0bit = OTG_DIEPCTL_SD0PID; + } + else + { + /* Clear the stall bit in the IN endpoint device control register */ + + regaddr = STM32_OTG_DOEPCTL(privep->epphy); + stallbit = OTG_DOEPCTL_STALL; + data0bit = OTG_DOEPCTL_SD0PID; + } + + /* Clear the stall bit */ + + regval = stm32_getreg(regaddr); + regval &= ~stallbit; + + /* Set the DATA0 pid for interrupt and bulk endpoints */ + + if (privep->eptype == USB_EP_ATTR_XFER_INT || + privep->eptype == USB_EP_ATTR_XFER_BULK) + { + /* Writing this bit sets the DATA0 PID */ + + regval |= data0bit; + } + + stm32_putreg(regval, regaddr); + + /* The endpoint is no longer stalled */ + + privep->stalled = false; + return OK; +} + +/**************************************************************************** + * Name: stm32_ep_stall + * + * Description: + * Stall or resume an endpoint + * + ****************************************************************************/ + +static int stm32_ep_stall(FAR struct usbdev_ep_s *ep, bool resume) +{ + FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep; + irqstate_t flags; + int ret; + + /* Set or clear the stall condition as requested */ + + flags = enter_critical_section(); + if (resume) + { + ret = stm32_ep_clrstall(privep); + } + else + { + ret = stm32_ep_setstall(privep); + } + leave_critical_section(flags); + + return ret; +} + +/**************************************************************************** + * Name: stm32_ep0_stall + * + * Description: + * Stall endpoint 0 + * + ****************************************************************************/ + +static void stm32_ep0_stall(FAR struct stm32_usbdev_s *priv) +{ + stm32_epin_setstall(&priv->epin[EP0]); + stm32_epout_setstall(&priv->epout[EP0]); + priv->stalled = true; + stm32_ep0out_ctrlsetup(priv); +} + +/**************************************************************************** + * Device operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_ep_alloc + * + * Description: + * Allocate an endpoint matching the parameters. + * + * Input Parameters: + * eplog - 7-bit logical endpoint number (direction bit ignored). Zero means + * that any endpoint matching the other requirements will suffice. The + * assigned endpoint can be found in the eplog field. + * in - true: IN (device-to-host) endpoint requested + * eptype - Endpoint type. One of {USB_EP_ATTR_XFER_ISOC, USB_EP_ATTR_XFER_BULK, + * USB_EP_ATTR_XFER_INT} + * + ****************************************************************************/ + +static FAR struct usbdev_ep_s *stm32_ep_alloc(FAR struct usbdev_s *dev, + uint8_t eplog, bool in, + uint8_t eptype) +{ + FAR struct stm32_usbdev_s *priv = (FAR struct stm32_usbdev_s *)dev; + uint8_t epavail; + irqstate_t flags; + int epphy; + int epno = 0; + + usbtrace(TRACE_DEVALLOCEP, (uint16_t)eplog); + + /* Ignore any direction bits in the logical address */ + + epphy = USB_EPNO(eplog); + + /* Get the set of available endpoints depending on the direction */ + + flags = enter_critical_section(); + epavail = priv->epavail[in]; + + /* A physical address of 0 means that any endpoint will do */ + + if (epphy > 0) + { + /* Otherwise, we will return the endpoint structure only for the requested + * 'logical' endpoint. All of the other checks will still be performed. + * + * First, verify that the logical endpoint is in the range supported by + * by the hardware. + */ + + if (epphy >= STM32_NENDPOINTS) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epphy); + return NULL; + } + + /* Remove all of the candidate endpoints from the bitset except for the + * this physical endpoint number. + */ + + epavail &= (1 << epphy); + } + + /* Is there an available endpoint? */ + + if (epavail) + { + /* Yes.. Select the lowest numbered endpoint in the set of available + * endpoints. + */ + + for (epno = 1; epno < STM32_NENDPOINTS; epno++) + { + uint8_t bit = 1 << epno; + if ((epavail & bit) != 0) + { + /* Mark the endpoint no longer available */ + + priv->epavail[in] &= ~(1 << epno); + + /* And return the pointer to the standard endpoint structure */ + + leave_critical_section(flags); + return in ? &priv->epin[epno].ep : &priv->epout[epno].ep; + } + } + + /* We should not get here */ + } + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOEP), (uint16_t)eplog); + leave_critical_section(flags); + return NULL; +} + +/**************************************************************************** + * Name: stm32_ep_free + * + * Description: + * Free the previously allocated endpoint + * + ****************************************************************************/ + +static void stm32_ep_free(FAR struct usbdev_s *dev, FAR struct usbdev_ep_s *ep) +{ + FAR struct stm32_usbdev_s *priv = (FAR struct stm32_usbdev_s *)dev; + FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep; + irqstate_t flags; + + usbtrace(TRACE_DEVFREEEP, (uint16_t)privep->epphy); + + if (priv && privep) + { + /* Mark the endpoint as available */ + + flags = enter_critical_section(); + priv->epavail[privep->isin] |= (1 << privep->epphy); + leave_critical_section(flags); + } +} + +/**************************************************************************** + * Name: stm32_getframe + * + * Description: + * Returns the current frame number + * + ****************************************************************************/ + +static int stm32_getframe(struct usbdev_s *dev) +{ + uint32_t regval; + + usbtrace(TRACE_DEVGETFRAME, 0); + + /* Return the last frame number of the last SOF detected by the hardware */ + + regval = stm32_getreg(STM32_OTG_DSTS); + return (int)((regval & OTG_DSTS_SOFFN_MASK) >> OTG_DSTS_SOFFN_SHIFT); +} + +/**************************************************************************** + * Name: stm32_wakeup + * + * Description: + * Exit suspend mode. + * + ****************************************************************************/ + +static int stm32_wakeup(struct usbdev_s *dev) +{ + FAR struct stm32_usbdev_s *priv = (FAR struct stm32_usbdev_s *)dev; + uint32_t regval; + irqstate_t flags; + + usbtrace(TRACE_DEVWAKEUP, 0); + + /* Is wakeup enabled? */ + + flags = enter_critical_section(); + if (priv->wakeup) + { + /* Yes... is the core suspended? */ + + regval = stm32_getreg(STM32_OTG_DSTS); + if ((regval & OTG_DSTS_SUSPSTS) != 0) + { + /* Re-start the PHY clock and un-gate USB core clock (HCLK) */ + +#ifdef CONFIG_USBDEV_LOWPOWER + regval = stm32_getreg(STM32_OTG_PCGCCTL); + regval &= ~(OTG_PCGCCTL_STPPCLK | OTG_PCGCCTL_GATEHCLK); + stm32_putreg(regval, STM32_OTG_PCGCCTL); +#endif + /* Activate Remote wakeup signaling */ + + regval = stm32_getreg(STM32_OTG_DCTL); + regval |= OTG_DCTL_RWUSIG; + stm32_putreg(regval, STM32_OTG_DCTL); + up_mdelay(5); + regval &= ~OTG_DCTL_RWUSIG; + stm32_putreg(regval, STM32_OTG_DCTL); + } + } + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_selfpowered + * + * Description: + * Sets/clears the device self-powered feature + * + ****************************************************************************/ + +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered) +{ + FAR struct stm32_usbdev_s *priv = (FAR struct stm32_usbdev_s *)dev; + + usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); + +#ifdef CONFIG_DEBUG_FEATURES + if (!dev) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -ENODEV; + } +#endif + + priv->selfpowered = selfpowered; + return OK; +} + +/**************************************************************************** + * Name: stm32_pullup + * + * Description: + * Software-controlled connect to/disconnect from USB host + * + ****************************************************************************/ + +static int stm32_pullup(struct usbdev_s *dev, bool enable) +{ + uint32_t regval; + + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + + irqstate_t flags = enter_critical_section(); + regval = stm32_getreg(STM32_OTG_DCTL); + if (enable) + { + /* Connect the device by clearing the soft disconnect bit in the DCTL + * register + */ + + regval &= ~OTG_DCTL_SDIS; + } + else + { + /* Connect the device by setting the soft disconnect bit in the DCTL + * register + */ + + regval |= OTG_DCTL_SDIS; + } + + stm32_putreg(regval, STM32_OTG_DCTL); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_setaddress + * + * Description: + * Set the devices USB address + * + ****************************************************************************/ + +static void stm32_setaddress(struct stm32_usbdev_s *priv, uint16_t address) +{ + uint32_t regval; + + /* Set the device address in the DCFG register */ + + regval = stm32_getreg(STM32_OTG_DCFG); + regval &= ~OTG_DCFG_DAD_MASK; + regval |= ((uint32_t)address << OTG_DCFG_DAD_SHIFT); + stm32_putreg(regval, STM32_OTG_DCFG); + + /* Are we now addressed? (i.e., do we have a non-NULL device + * address?) + */ + + if (address != 0) + { + priv->devstate = DEVSTATE_ADDRESSED; + priv->addressed = true; + } + else + { + priv->devstate = DEVSTATE_DEFAULT; + priv->addressed = false; + } +} + +/**************************************************************************** + * Name: stm32_txfifo_flush + * + * Description: + * Flush the specific TX fifo. + * + ****************************************************************************/ + +static int stm32_txfifo_flush(uint32_t txfnum) +{ + uint32_t regval; + uint32_t timeout; + + /* Initiate the TX FIFO flush operation */ + + regval = OTG_GRSTCTL_TXFFLSH | txfnum; + stm32_putreg(regval, STM32_OTG_GRSTCTL); + + /* Wait for the FLUSH to complete */ + + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTG_GRSTCTL); + if ((regval & OTG_GRSTCTL_TXFFLSH) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); + return OK; +} + +/**************************************************************************** + * Name: stm32_rxfifo_flush + * + * Description: + * Flush the RX fifo. + * + ****************************************************************************/ + +static int stm32_rxfifo_flush(void) +{ + uint32_t regval; + uint32_t timeout; + + /* Initiate the RX FIFO flush operation */ + + stm32_putreg(OTG_GRSTCTL_RXFFLSH, STM32_OTG_GRSTCTL); + + /* Wait for the FLUSH to complete */ + + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTG_GRSTCTL); + if ((regval & OTG_GRSTCTL_RXFFLSH) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); + return OK; +} + +/**************************************************************************** + * Name: stm32_swinitialize + * + * Description: + * Initialize all driver data structures. + * + ****************************************************************************/ + +static void stm32_swinitialize(FAR struct stm32_usbdev_s *priv) +{ + FAR struct stm32_ep_s *privep; + int i; + + /* Initialize the device state structure */ + + memset(priv, 0, sizeof(struct stm32_usbdev_s)); + + priv->usbdev.ops = &g_devops; + priv->usbdev.ep0 = &priv->epin[EP0].ep; + + priv->epavail[0] = STM32_EP_AVAILABLE; + priv->epavail[1] = STM32_EP_AVAILABLE; + + priv->epin[EP0].ep.priv = priv; + priv->epout[EP0].ep.priv = priv; + + /* Initialize the endpoint lists */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + /* Set endpoint operations, reference to driver structure (not + * really necessary because there is only one controller), and + * the physical endpoint number (which is just the index to the + * endpoint). + */ + + privep = &priv->epin[i]; + privep->ep.ops = &g_epops; + privep->dev = priv; + privep->isin = 1; + + /* The index, i, is the physical endpoint address; Map this + * to a logical endpoint address usable by the class driver. + */ + + privep->epphy = i; + privep->ep.eplog = STM32_EPPHYIN2LOG(i); + + /* Control until endpoint is activated */ + + privep->eptype = USB_EP_ATTR_XFER_CONTROL; + privep->ep.maxpacket = CONFIG_USBDEV_EP0_MAXSIZE; + } + + /* Initialize the endpoint lists */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + /* Set endpoint operations, reference to driver structure (not + * really necessary because there is only one controller), and + * the physical endpoint number (which is just the index to the + * endpoint). + */ + + privep = &priv->epout[i]; + privep->ep.ops = &g_epops; + privep->dev = priv; + + /* The index, i, is the physical endpoint address; Map this + * to a logical endpoint address usable by the class driver. + */ + + privep->epphy = i; + privep->ep.eplog = STM32_EPPHYOUT2LOG(i); + + /* Control until endpoint is activated */ + + privep->eptype = USB_EP_ATTR_XFER_CONTROL; + privep->ep.maxpacket = CONFIG_USBDEV_EP0_MAXSIZE; + } +} + +/**************************************************************************** + * Name: stm32_hwinitialize + * + * Description: + * Configure the OTG core for operation. + * + ****************************************************************************/ + +static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) +{ + uint32_t regval; + uint32_t timeout; + uint32_t address; + int i; + + /* At start-up the core is in FS/HS mode. */ + + /* Disable global interrupts by clearing the GINTMASK bit in the GAHBCFG + * register; Set the TXFELVL bit in the GAHBCFG register so that TxFIFO + * interrupts will occur when the TxFIFO is truly empty (not just half full). + */ + + stm32_putreg(OTG_GAHBCFG_TXFELVL, STM32_OTG_GAHBCFG); + +#if defined(CONFIG_STM32_OTGHS) + /* Set the PHYSEL bit in the GUSBCFG register to select the OTG HS serial + * transceiver: "This bit is always 1 with write-only access" + */ + + regval = stm32_getreg(STM32_OTG_GUSBCFG); + regval |= OTG_GUSBCFG_PHYSEL; + stm32_putreg(regval, STM32_OTG_GUSBCFG); +#endif + + /* Common USB OTG core initialization */ + /* Reset after a PHY select and set Host mode. First, wait for AHB master + * IDLE state. + */ + + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) + { + up_udelay(3); + regval = stm32_getreg(STM32_OTG_GRSTCTL); + if ((regval & OTG_GRSTCTL_AHBIDL) != 0) + { + break; + } + } + + /* Then perform the core soft reset. */ + + stm32_putreg(OTG_GRSTCTL_CSRST, STM32_OTG_GRSTCTL); + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTG_GRSTCTL); + if ((regval & OTG_GRSTCTL_CSRST) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); + + /* Deactivate the power down */ + + + /* Detection Enable when set + */ + + regval = OTG_GCCFG_PWRDWN; + +# ifdef CONFIG_USBDEV_VBUSSENSING + regval |= OTG_GCCFG_VBDEN; +# endif + + + stm32_putreg(regval, STM32_OTG_GCCFG); + up_mdelay(20); + + /* When VBUS sensing is not used we + * need to force the B session valid + */ + + +# ifndef CONFIG_USBDEV_VBUSSENSING + regval = stm32_getreg(STM32_OTG_GOTGCTL); + regval |= (OTG_GOTGCTL_BVALOEN | OTG_GOTGCTL_BVALOVAL); + stm32_putreg(regval, STM32_OTG_GOTGCTL); +# endif + + + /* Force Device Mode */ + + regval = stm32_getreg(STM32_OTG_GUSBCFG); + regval &= ~OTG_GUSBCFG_FHMOD; + regval |= OTG_GUSBCFG_FDMOD; + stm32_putreg(regval, STM32_OTG_GUSBCFG); + up_mdelay(50); + + /* Initialize device mode */ + /* Restart the PHY Clock */ + + stm32_putreg(0, STM32_OTG_PCGCCTL); + + /* Device configuration register */ + + regval = stm32_getreg(STM32_OTG_DCFG); + regval &= ~OTG_DCFG_PFIVL_MASK; + regval |= OTG_DCFG_PFIVL_80PCT; + stm32_putreg(regval, STM32_OTG_DCFG); + + /* Set full speed PHY */ + + regval = stm32_getreg(STM32_OTG_DCFG); + regval &= ~OTG_DCFG_DSPD_MASK; + regval |= OTG_DCFG_DSPD_FS; + stm32_putreg(regval, STM32_OTG_DCFG); + + /* Set Rx FIFO size */ + + stm32_putreg(STM32_RXFIFO_WORDS, STM32_OTG_GRXFSIZ); + + /* EP0 TX */ + + address = STM32_RXFIFO_WORDS; + regval = (address << OTG_DIEPTXF0_TX0FD_SHIFT) | + (STM32_EP0_TXFIFO_WORDS << OTG_DIEPTXF0_TX0FSA_SHIFT); + stm32_putreg(regval, STM32_OTG_DIEPTXF0); + + /* EP1 TX */ + + address += STM32_EP0_TXFIFO_WORDS; + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP1_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTG_DIEPTXF1); + + /* EP2 TX */ + + address += STM32_EP1_TXFIFO_WORDS; + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP2_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTG_DIEPTXF2); + + /* EP3 TX */ + + address += STM32_EP2_TXFIFO_WORDS; + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP3_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTG_DIEPTXF3); + + /* Flush the FIFOs */ + + stm32_txfifo_flush(OTG_GRSTCTL_TXFNUM_DALL); + stm32_rxfifo_flush(); + + /* Clear all pending Device Interrupts */ + + stm32_putreg(0, STM32_OTG_DIEPMSK); + stm32_putreg(0, STM32_OTG_DOEPMSK); + stm32_putreg(0, STM32_OTG_DIEPEMPMSK); + stm32_putreg(0xffffffff, STM32_OTG_DAINT); + stm32_putreg(0, STM32_OTG_DAINTMSK); + + /* Configure all IN endpoints */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + regval = stm32_getreg(STM32_OTG_DIEPCTL(i)); + if ((regval & OTG_DIEPCTL_EPENA) != 0) + { + /* The endpoint is already enabled */ + + regval = OTG_DIEPCTL_EPENA | OTG_DIEPCTL_SNAK; + } + else + { + regval = 0; + } + + stm32_putreg(regval, STM32_OTG_DIEPCTL(i)); + stm32_putreg(0, STM32_OTG_DIEPTSIZ(i)); + stm32_putreg(0xff, STM32_OTG_DIEPINT(i)); + } + + /* Configure all OUT endpoints */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + regval = stm32_getreg(STM32_OTG_DOEPCTL(i)); + if ((regval & OTG_DOEPCTL_EPENA) != 0) + { + /* The endpoint is already enabled */ + + regval = OTG_DOEPCTL_EPENA | OTG_DOEPCTL_SNAK; + } + else + { + regval = 0; + } + + stm32_putreg(regval, STM32_OTG_DOEPCTL(i)); + stm32_putreg(0, STM32_OTG_DOEPTSIZ(i)); + stm32_putreg(0xff, STM32_OTG_DOEPINT(i)); + } + + /* Disable all interrupts. */ + + stm32_putreg(0, STM32_OTG_GINTMSK); + + /* Clear any pending USB_OTG Interrupts */ + + stm32_putreg(0xffffffff, STM32_OTG_GOTGINT); + + /* Clear any pending interrupts */ + + stm32_putreg(0xbfffffff, STM32_OTG_GINTSTS); + +#ifdef defined(CONFIG_STM32_OTGHS) + /* Disable the ULPI Clock enable in RCC AHB1 Register. This must + * be done because if both the ULPI and the FS PHY clock enable bits + * are set at the same time, the ARM never awakens from WFI due to + * some bug / errata in the chip. + */ + + regval = stm32_getreg(STM32_RCC_AHB1LPENR); + regval &= ~RCC_AHB1ENR_OTGULPIEN; + stm32_putreg(regval, STM32_RCC_AHB1LPENR); +#endif + + /* Enable the interrupts in the INTMSK */ + + regval = (OTG_GINT_RXFLVL | OTG_GINT_USBSUSP | OTG_GINT_ENUMDNE | + OTG_GINT_IEP | OTG_GINT_OEP | OTG_GINT_USBRST); + +#ifdef CONFIG_USBDEV_ISOCHRONOUS + regval |= (OTG_GINT_IISOIXFR | OTG_GINT_IISOOXFR); +#endif + +#ifdef CONFIG_USBDEV_SOFINTERRUPT + regval |= OTG_GINT_SOF; +#endif + +#ifdef CONFIG_USBDEV_VBUSSENSING + regval |= (OTG_GINT_OTG | OTG_GINT_SRQ); +#endif + +#ifdef CONFIG_DEBUG_USB + regval |= OTG_GINT_MMIS; +#endif + + stm32_putreg(regval, STM32_OTG_GINTMSK); + + /* Enable the USB global interrupt by setting GINTMSK in the global OTG + * AHB configuration register; Set the TXFELVL bit in the GAHBCFG + * register so that TxFIFO interrupts will occur when the TxFIFO is truly + * empty (not just half full). + */ + + stm32_putreg(OTG_GAHBCFG_GINTMSK | OTG_GAHBCFG_TXFELVL, + STM32_OTG_GAHBCFG); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_usbinitialize + * + * Description: + * Initialize USB hardware. + * + * Assumptions: + * - This function is called very early in the initialization sequence + * - PLL and GIO pin initialization is not performed here but should been in + * the low-level boot logic: PLL1 must be configured for operation at 48MHz + * and P0.23 and PO.31 in PINSEL1 must be configured for Vbus and USB connect + * LED. + * + ****************************************************************************/ + +void up_usbinitialize(void) +{ + /* At present, there is only a single OTG device support. Hence it is + * pre-allocated as g_otghsdev. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple devices. + */ + + FAR struct stm32_usbdev_s *priv = &g_otghsdev; + int ret; + + usbtrace(TRACE_DEVINIT, 0); + + /* Here we assume that: + * + * 1. GPIOA and OTG peripheral clocking has already been enabled as part + * of the boot sequence. + * 2. Board-specific logic has already enabled other board specific GPIOs + * for things like soft pull-up, VBUS sensing, power controls, and over- + * current detection. + */ + + /* Configure OTG alternate function pins + */ + + stm32_configgpio(GPIO_OTG_DM); + stm32_configgpio(GPIO_OTG_DP); + stm32_configgpio(GPIO_OTG_ID); /* Only needed for OTG */ + + /* SOF output pin configuration is configurable. */ + +#ifdef CONFIG_STM32_OTG_SOFOUTPUT + stm32_configgpio(GPIO_OTG_SOF); +#endif + + /* Uninitialize the hardware so that we know that we are starting from a + * known state. */ + + up_usbuninitialize(); + + /* Initialie the driver data structure */ + + stm32_swinitialize(priv); + + /* Attach the OTG interrupt handler */ + + ret = irq_attach(STM32_IRQ_OTG, stm32_usbinterrupt); + if (ret < 0) + { + uerr("irq_attach failed\n", ret); + goto errout; + } + + /* Initialize the USB OTG core */ + + stm32_hwinitialize(priv); + + /* Disconnect device */ + + stm32_pullup(&priv->usbdev, false); + + /* Reset/Re-initialize the USB hardware */ + + stm32_usbreset(priv); + + /* Enable USB controller interrupts at the NVIC */ + + up_enable_irq(STM32_IRQ_OTG); + +#ifdef CONFIG_ARCH_IRQPRIO + /* Set the interrupt priority */ + + up_prioritize_irq(STM32_IRQ_OTG, CONFIG_OTG_PRI); +#endif + return; + +errout: + up_usbuninitialize(); +} + +/**************************************************************************** + * Name: up_usbuninitialize + ****************************************************************************/ + +void up_usbuninitialize(void) +{ + /* At present, there is only a single OTG device support. Hence it is + * pre-allocated as g_otghsdev. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple devices. + */ + + FAR struct stm32_usbdev_s *priv = &g_otghsdev; + irqstate_t flags; + int i; + + usbtrace(TRACE_DEVUNINIT, 0); + + if (priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVERREGISTERED), 0); + usbdev_unregister(priv->driver); + } + + /* Disconnect device */ + + flags = enter_critical_section(); + stm32_pullup(&priv->usbdev, false); + priv->usbdev.speed = USB_SPEED_UNKNOWN; + + /* Disable and detach IRQs */ + + up_disable_irq(STM32_IRQ_OTG); + irq_detach(STM32_IRQ_OTG); + + /* Disable all endpoint interrupts */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + stm32_putreg(0xff, STM32_OTG_DIEPINT(i)); + stm32_putreg(0xff, STM32_OTG_DOEPINT(i)); + } + + stm32_putreg(0, STM32_OTG_DIEPMSK); + stm32_putreg(0, STM32_OTG_DOEPMSK); + stm32_putreg(0, STM32_OTG_DIEPEMPMSK); + stm32_putreg(0, STM32_OTG_DAINTMSK); + stm32_putreg(0xffffffff, STM32_OTG_DAINT); + + /* Flush the FIFOs */ + + stm32_txfifo_flush(OTG_GRSTCTL_TXFNUM_DALL); + stm32_rxfifo_flush(); + + /* TODO: Turn off USB power and clocking */ + + priv->devstate = DEVSTATE_DEFAULT; + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: usbdev_register + * + * Description: + * Register a USB device class driver. The class driver's bind() method will be + * called to bind it to a USB device driver. + * + ****************************************************************************/ + +int usbdev_register(struct usbdevclass_driver_s *driver) +{ + /* At present, there is only a single OTG device support. Hence it is + * pre-allocated as g_otghsdev. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple devices. + */ + + FAR struct stm32_usbdev_s *priv = &g_otghsdev; + int ret; + + usbtrace(TRACE_DEVREGISTER, 0); + +#ifdef CONFIG_DEBUG_FEATURES + if (!driver || !driver->ops->bind || !driver->ops->unbind || + !driver->ops->disconnect || !driver->ops->setup) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } + + if (priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0); + return -EBUSY; + } +#endif + + /* First hook up the driver */ + + priv->driver = driver; + + /* Then bind the class driver */ + + ret = CLASS_BIND(driver, &priv->usbdev); + if (ret) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t)-ret); + priv->driver = NULL; + } + else + { + /* Enable USB controller interrupts */ + + up_enable_irq(STM32_IRQ_OTG); + + /* FIXME: nothing seems to call DEV_CONNECT(), but we need to set + * the RS bit to enable the controller. It kind of makes sense + * to do this after the class has bound to us... + * GEN: This bug is really in the class driver. It should make the + * soft connect when it is ready to be enumerated. I have added + * that logic to the class drivers but left this logic here. + */ + + stm32_pullup(&priv->usbdev, true); + priv->usbdev.speed = USB_SPEED_FULL; + } + + return ret; +} + +/**************************************************************************** + * Name: usbdev_unregister + * + * Description: + * Un-register usbdev class driver.If the USB device is connected to a USB host, + * it will first disconnect(). The driver is also requested to unbind() and clean + * up any device state, before this procedure finally returns. + * + ****************************************************************************/ + +int usbdev_unregister(struct usbdevclass_driver_s *driver) +{ + /* At present, there is only a single OTG device support. Hence it is + * pre-allocated as g_otghsdev. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple devices. + */ + + FAR struct stm32_usbdev_s *priv = &g_otghsdev; + irqstate_t flags; + + usbtrace(TRACE_DEVUNREGISTER, 0); + +#ifdef CONFIG_DEBUG_FEATURES + if (driver != priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + /* Reset the hardware and cancel all requests. All requests must be + * canceled while the class driver is still bound. + */ + + flags = enter_critical_section(); + stm32_usbreset(priv); + leave_critical_section(flags); + + /* Unbind the class driver */ + + CLASS_UNBIND(driver, &priv->usbdev); + + /* Disable USB controller interrupts */ + + flags = enter_critical_section(); + up_disable_irq(STM32_IRQ_OTG); + + /* Disconnect device */ + + stm32_pullup(&priv->usbdev, false); + + /* Unhook the driver */ + + priv->driver = NULL; + leave_critical_section(flags); + + return OK; +} + +#endif /* CONFIG_USBDEV && CONFIG_STM32_OTGDEV */ diff --git a/arch/arm/src/stm32f7/stm32_otghost.c b/arch/arm/src/stm32f7/stm32_otghost.c new file mode 100644 index 0000000000..cc00b1336f --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_otghost.c @@ -0,0 +1,5306 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/stm32_otghost.c + * + * Copyright (C) 2012-2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "chip.h" /* Includes default GPIO settings */ +#include /* May redefine GPIO settings */ + +#include "up_arch.h" +#include "up_internal.h" + +#include "stm32_otg.h" + +#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32_OTGFS) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ***************************************************************/ +/* STM32 USB OTG FS Host Driver Support + * + * Pre-requisites + * + * CONFIG_USBHOST - Enable general USB host support + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_SYSCFG - Needed + * + * Options: + * + * CONFIG_STM32_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * Default 128 (512 bytes) + * CONFIG_STM32_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * in 32-bit words. Default 96 (384 bytes) + * CONFIG_STM32_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit + * words. Default 96 (384 bytes) + * CONFIG_STM32_OTG_DESCSIZE - Maximum size of a descriptor. Default: 128 + * CONFIG_STM32_OTG_SOFINTR - Enable SOF interrupts. Why would you ever + * want to do that? + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access + * debug. Depends on CONFIG_DEBUG_FEATURES. + * CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB + * packets. Depends on CONFIG_DEBUG_FEATURES. + */ + +/* Pre-requisites (partial) */ + +#ifndef CONFIG_STM32_SYSCFG +# error "CONFIG_STM32_SYSCFG is required" +#endif + +/* Default RxFIFO size */ + +#ifndef CONFIG_STM32_OTG_RXFIFO_SIZE +# define CONFIG_STM32_OTG_RXFIFO_SIZE 128 +#endif + +/* Default host non-periodic Tx FIFO size */ + +#ifndef CONFIG_STM32_OTG_NPTXFIFO_SIZE +# define CONFIG_STM32_OTG_NPTXFIFO_SIZE 96 +#endif + +/* Default host periodic Tx fifo size register */ + +#ifndef CONFIG_STM32_OTG_PTXFIFO_SIZE +# define CONFIG_STM32_OTG_PTXFIFO_SIZE 96 +#endif + +/* Maximum size of a descriptor */ + +#ifndef CONFIG_STM32_OTG_DESCSIZE +# define CONFIG_STM32_OTG_DESCSIZE 128 +#endif + +/* Register/packet debug depends on CONFIG_DEBUG_FEATURES */ + +#ifndef CONFIG_DEBUG_FEATURES +# undef CONFIG_STM32_USBHOST_REGDEBUG +# undef CONFIG_STM32_USBHOST_PKTDUMP +#endif + +/* HCD Setup *******************************************************************/ +/* Hardware capabilities */ + +#define STM32_NHOST_CHANNELS 8 /* Number of host channels */ +#define STM32_MAX_PACKET_SIZE 64 /* Full speed max packet size */ +#define STM32_EP0_DEF_PACKET_SIZE 8 /* EP0 default packet size */ +#define STM32_EP0_MAX_PACKET_SIZE 64 /* EP0 FS max packet size */ +#define STM32_MAX_TX_FIFOS 15 /* Max number of TX FIFOs */ +#define STM32_MAX_PKTCOUNT 256 /* Max packet count */ +#define STM32_RETRY_COUNT 3 /* Number of ctrl transfer retries */ + +/* Delays **********************************************************************/ + +#define STM32_READY_DELAY 200000 /* In loop counts */ +#define STM32_FLUSH_DELAY 200000 /* In loop counts */ +#define STM32_SETUP_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ +#define STM32_DATANAK_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ + +/* Ever-present MIN/MAX macros */ + +#ifndef MIN +# define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef MAX +# define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* The following enumeration represents the various states of the USB host + * state machine (for debug purposes only) + */ + +enum stm32_smstate_e +{ + SMSTATE_DETACHED = 0, /* Not attached to a device */ + SMSTATE_ATTACHED, /* Attached to a device */ + SMSTATE_ENUM, /* Attached, enumerating */ + SMSTATE_CLASS_BOUND, /* Enumeration complete, class bound */ +}; + +/* This enumeration provides the reason for the channel halt. */ + +enum stm32_chreason_e +{ + CHREASON_IDLE = 0, /* Inactive (initial state) */ + CHREASON_FREED, /* Channel is no longer in use */ + CHREASON_XFRC, /* Transfer complete */ + CHREASON_NAK, /* NAK received */ + CHREASON_NYET, /* NotYet received */ + CHREASON_STALL, /* Endpoint stalled */ + CHREASON_TXERR, /* Transfer error received */ + CHREASON_DTERR, /* Data toggle error received */ + CHREASON_FRMOR, /* Frame overrun */ + CHREASON_CANCELLED /* Transfer cancelled */ +}; + +/* This structure retains the state of one host channel. NOTE: Since there + * is only one channel operation active at a time, some of the fields in + * in the structure could be moved in struct stm32_ubhost_s to achieve + * some memory savings. + */ + +struct stm32_chan_s +{ + sem_t waitsem; /* Channel wait semaphore */ + volatile uint8_t result; /* The result of the transfer */ + volatile uint8_t chreason; /* Channel halt reason. See enum stm32_chreason_e */ + uint8_t chidx; /* Channel index */ + uint8_t epno; /* Device endpoint number (0-127) */ + uint8_t eptype; /* See OTG_EPTYPE_* definitions */ + uint8_t funcaddr; /* Device function address */ + uint8_t speed; /* Device speed */ + uint8_t pid; /* Data PID */ + uint8_t npackets; /* Number of packets (for data toggle) */ + bool inuse; /* True: This channel is "in use" */ + volatile bool indata1; /* IN data toggle. True: DATA01 (Bulk and INTR only) */ + volatile bool outdata1; /* OUT data toggle. True: DATA01 */ + bool in; /* True: IN endpoint */ + volatile bool waiter; /* True: Thread is waiting for a channel event */ + uint16_t maxpacket; /* Max packet size */ + uint16_t buflen; /* Buffer length (at start of transfer) */ + volatile uint16_t xfrd; /* Bytes transferred (at end of transfer) */ + volatile uint16_t inflight; /* Number of Tx bytes "in-flight" */ + FAR uint8_t *buffer; /* Transfer buffer pointer */ +#ifdef CONFIG_USBHOST_ASYNCH + usbhost_asynch_t callback; /* Transfer complete callback */ + FAR void *arg; /* Argument that accompanies the callback */ +#endif +}; + +/* A channel represents on uni-directional endpoint. So, in the case of the + * bi-directional, control endpoint, there must be two channels to represent + * the endpoint. + */ + +struct stm32_ctrlinfo_s +{ + uint8_t inndx; /* EP0 IN control channel index */ + uint8_t outndx; /* EP0 OUT control channel index */ +}; + +/* This structure retains the state of the USB host controller */ + +struct stm32_usbhost_s +{ + /* Common device fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbhost_s + * to structstm32_usbhost_s. + */ + + struct usbhost_driver_s drvr; + + /* This is the hub port description understood by class drivers */ + + struct usbhost_roothubport_s rhport; + + /* Overall driver status */ + + volatile uint8_t smstate; /* The state of the USB host state machine */ + uint8_t chidx; /* ID of channel waiting for space in Tx FIFO */ + volatile bool connected; /* Connected to device */ + volatile bool change; /* Connection change */ + volatile bool pscwait; /* True: Thread is waiting for a port event */ + sem_t exclsem; /* Support mutually exclusive access */ + sem_t pscsem; /* Semaphore to wait for a port event */ + struct stm32_ctrlinfo_s ep0; /* Root hub port EP0 description */ + +#ifdef CONFIG_USBHOST_HUB + /* Used to pass external hub port events */ + + volatile struct usbhost_hubport_s *hport; +#endif + + /* The state of each host channel */ + + struct stm32_chan_s chan[STM32_MAX_TX_FIFOS]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register operations ********************************************************/ + +#ifdef CONFIG_STM32_USBHOST_REGDEBUG +static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite); +static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); +static uint32_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint32_t addr, uint32_t value); +#else +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(addr,val) putreg32(val,addr) +#endif + +static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, + uint32_t setbits); + +#ifdef CONFIG_STM32_USBHOST_PKTDUMP +# define stm32_pktdump(m,b,n) lib_dumpbuffer(m,b,n) +#else +# define stm32_pktdump(m,b,n) +#endif + +/* Semaphores ******************************************************************/ + +static void stm32_takesem(sem_t *sem); +#define stm32_givesem(s) sem_post(s); + +/* Byte stream access helper functions *****************************************/ + +static inline uint16_t stm32_getle16(const uint8_t *val); + +/* Channel management **********************************************************/ + +static int stm32_chan_alloc(FAR struct stm32_usbhost_s *priv); +static inline void stm32_chan_free(FAR struct stm32_usbhost_s *priv, int chidx); +static inline void stm32_chan_freeall(FAR struct stm32_usbhost_s *priv); +static void stm32_chan_configure(FAR struct stm32_usbhost_s *priv, int chidx); +static void stm32_chan_halt(FAR struct stm32_usbhost_s *priv, int chidx, + enum stm32_chreason_e chreason); +static int stm32_chan_waitsetup(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan); +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_chan_asynchsetup(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan, + usbhost_asynch_t callback, FAR void *arg); +#endif +static int stm32_chan_wait(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan); +static void stm32_chan_wakeup(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan); +static int stm32_ctrlchan_alloc(FAR struct stm32_usbhost_s *priv, + uint8_t epno, uint8_t funcaddr, uint8_t speed, + FAR struct stm32_ctrlinfo_s *ctrlep); +static int stm32_ctrlep_alloc(FAR struct stm32_usbhost_s *priv, + FAR const struct usbhost_epdesc_s *epdesc, + FAR usbhost_ep_t *ep); +static int stm32_xfrep_alloc(FAR struct stm32_usbhost_s *priv, + FAR const struct usbhost_epdesc_s *epdesc, + FAR usbhost_ep_t *ep); + +/* Control/data transfer logic *************************************************/ + +static void stm32_transfer_start(FAR struct stm32_usbhost_s *priv, int chidx); +#if 0 /* Not used */ +static inline uint16_t stm32_getframe(void); +#endif +static int stm32_ctrl_sendsetup(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_ctrlinfo_s *ep0, + FAR const struct usb_ctrlreq_s *req); +static int stm32_ctrl_senddata(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_ctrlinfo_s *ep0, + FAR uint8_t *buffer, unsigned int buflen); +static int stm32_ctrl_recvdata(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_ctrlinfo_s *ep0, + FAR uint8_t *buffer, unsigned int buflen); +static int stm32_in_setup(FAR struct stm32_usbhost_s *priv, int chidx); +static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx, + FAR uint8_t *buffer, size_t buflen); +#ifdef CONFIG_USBHOST_ASYNCH +static void stm32_in_next(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan); +static int stm32_in_asynch(FAR struct stm32_usbhost_s *priv, int chidx, + FAR uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, FAR void *arg); +#endif +static int stm32_out_setup(FAR struct stm32_usbhost_s *priv, int chidx); +static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx, + FAR uint8_t *buffer, size_t buflen); +#ifdef CONFIG_USBHOST_ASYNCH +static void stm32_out_next(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan); +static int stm32_out_asynch(FAR struct stm32_usbhost_s *priv, int chidx, + FAR uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, FAR void *arg); +#endif + +/* Interrupt handling **********************************************************/ +/* Lower level interrupt handlers */ + +static void stm32_gint_wrpacket(FAR struct stm32_usbhost_s *priv, + FAR uint8_t *buffer, int chidx, int buflen); +static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv, + int chidx); +static inline void stm32_gint_hcoutisr(FAR struct stm32_usbhost_s *priv, + int chidx); +static void stm32_gint_connected(FAR struct stm32_usbhost_s *priv); +static void stm32_gint_disconnected(FAR struct stm32_usbhost_s *priv); + +/* Second level interrupt handlers */ + +#ifdef CONFIG_STM32_OTG_SOFINTR +static inline void stm32_gint_sofisr(FAR struct stm32_usbhost_s *priv); +#endif +static inline void stm32_gint_rxflvlisr(FAR struct stm32_usbhost_s *priv); +static inline void stm32_gint_nptxfeisr(FAR struct stm32_usbhost_s *priv); +static inline void stm32_gint_ptxfeisr(FAR struct stm32_usbhost_s *priv); +static inline void stm32_gint_hcisr(FAR struct stm32_usbhost_s *priv); +static inline void stm32_gint_hprtisr(FAR struct stm32_usbhost_s *priv); +static inline void stm32_gint_discisr(FAR struct stm32_usbhost_s *priv); +static inline void stm32_gint_ipxfrisr(FAR struct stm32_usbhost_s *priv); + +/* First level, global interrupt handler */ + +static int stm32_gint_isr(int irq, FAR void *context); + +/* Interrupt controls */ + +static void stm32_gint_enable(void); +static void stm32_gint_disable(void); +static inline void stm32_hostinit_enable(void); +static void stm32_txfe_enable(FAR struct stm32_usbhost_s *priv, int chidx); + +/* USB host controller operations **********************************************/ + +static int stm32_wait(FAR struct usbhost_connection_s *conn, + FAR struct usbhost_hubport_s **hport); +static int stm32_rh_enumerate(FAR struct stm32_usbhost_s *priv, + FAR struct usbhost_connection_s *conn, + FAR struct usbhost_hubport_s *hport); +static int stm32_enumerate(FAR struct usbhost_connection_s *conn, + FAR struct usbhost_hubport_s *hport); + +static int stm32_ep0configure(FAR struct usbhost_driver_s *drvr, + usbhost_ep_t ep0, uint8_t funcaddr, uint8_t speed, + uint16_t maxpacketsize); +static int stm32_epalloc(FAR struct usbhost_driver_s *drvr, + FAR const FAR struct usbhost_epdesc_s *epdesc, + FAR usbhost_ep_t *ep); +static int stm32_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep); +static int stm32_alloc(FAR struct usbhost_driver_s *drvr, + FAR uint8_t **buffer, FAR size_t *maxlen); +static int stm32_free(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer); +static int stm32_ioalloc(FAR struct usbhost_driver_s *drvr, + FAR uint8_t **buffer, size_t buflen); +static int stm32_iofree(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer); +static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0, + const struct usb_ctrlreq_s *req, + FAR uint8_t *buffer); +static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0, + FAR const struct usb_ctrlreq_s *req, + FAR const uint8_t *buffer); +static ssize_t stm32_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep, + FAR uint8_t *buffer, size_t buflen); +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep, + FAR uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, FAR void *arg); +#endif +static int stm32_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep); +#ifdef CONFIG_USBHOST_HUB +static int stm32_connect(FAR struct usbhost_driver_s *drvr, + FAR struct usbhost_hubport_s *hport, + bool connected); +#endif +static void stm32_disconnect(FAR struct usbhost_driver_s *drvr, + FAR struct usbhost_hubport_s *hport); + +/* Initialization **************************************************************/ + +static void stm32_portreset(FAR struct stm32_usbhost_s *priv); +static void stm32_flush_txfifos(uint32_t txfnum); +static void stm32_flush_rxfifo(void); +static void stm32_vbusdrive(FAR struct stm32_usbhost_s *priv, bool state); +static void stm32_host_initialize(FAR struct stm32_usbhost_s *priv); + +static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv); +static inline int stm32_hw_initialize(FAR struct stm32_usbhost_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* In this driver implementation, support is provided for only a single a single + * USB device. All status information can be simply retained in a single global + * instance. + */ + +static struct stm32_usbhost_s g_usbhost; + +/* This is the connection/enumeration interface */ + +static struct usbhost_connection_s g_usbconn = +{ + .wait = stm32_wait, + .enumerate = stm32_enumerate, +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_printreg + * + * Description: + * Print the contents of an STM32xx register operation + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST_REGDEBUG +static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) +{ + llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); +} +#endif + +/**************************************************************************** + * Name: stm32_checkreg + * + * Description: + * Get the contents of an STM32 register + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST_REGDEBUG +static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) +{ + static uint32_t prevaddr = 0; + static uint32_t preval = 0; + static uint32_t count = 0; + static bool prevwrite = false; + + /* Is this the same value that we read from/wrote to the same register last time? + * Are we polling the register? If so, suppress the output. + */ + + if (addr == prevaddr && val == preval && prevwrite == iswrite) + { + /* Yes.. Just increment the count */ + + count++; + } + else + { + /* No this is a new address or value or operation. Were there any + * duplicate accesses before this one? + */ + + if (count > 0) + { + /* Yes.. Just one? */ + + if (count == 1) + { + /* Yes.. Just one */ + + stm32_printreg(prevaddr, preval, prevwrite); + } + else + { + /* No.. More than one. */ + + llerr("[repeats %d more times]\n", count); + } + } + + /* Save the new address, value, count, and operation for next time */ + + prevaddr = addr; + preval = val; + count = 0; + prevwrite = iswrite; + + /* Show the new regisgter access */ + + stm32_printreg(addr, val, iswrite); + } +} +#endif + +/**************************************************************************** + * Name: stm32_getreg + * + * Description: + * Get the contents of an STM32 register + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST_REGDEBUG +static uint32_t stm32_getreg(uint32_t addr) +{ + /* Read the value from the register */ + + uint32_t val = getreg32(addr); + + /* Check if we need to print this value */ + + stm32_checkreg(addr, val, false); + return val; +} +#endif + +/**************************************************************************** + * Name: stm32_putreg + * + * Description: + * Set the contents of an STM32 register to a value + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST_REGDEBUG +static void stm32_putreg(uint32_t addr, uint32_t val) +{ + /* Check if we need to print this value */ + + stm32_checkreg(addr, val, true); + + /* Write the value */ + + putreg32(val, addr); +} +#endif + +/**************************************************************************** + * Name: stm32_modifyreg + * + * Description: + * Modify selected bits of an STM32 register. + * + ****************************************************************************/ + +static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, uint32_t setbits) +{ + stm32_putreg(addr, (((stm32_getreg(addr)) & ~clrbits) | setbits)); +} + +/**************************************************************************** + * Name: stm32_takesem + * + * Description: + * This is just a wrapper to handle the annoying behavior of semaphore + * waits that return due to the receipt of a signal. + * + ****************************************************************************/ + +static void stm32_takesem(sem_t *sem) +{ + /* Take the semaphore (perhaps waiting) */ + + while (sem_wait(sem) != 0) + { + /* The only case that an error should occr here is if the wait was + * awakened by a signal. + */ + + ASSERT(errno == EINTR); + } +} + +/**************************************************************************** + * Name: stm32_getle16 + * + * Description: + * Get a (possibly unaligned) 16-bit little endian value. + * + ****************************************************************************/ + +static inline uint16_t stm32_getle16(const uint8_t *val) +{ + return (uint16_t)val[1] << 8 | (uint16_t)val[0]; +} + +/**************************************************************************** + * Name: stm32_chan_alloc + * + * Description: + * Allocate a channel. + * + ****************************************************************************/ + +static int stm32_chan_alloc(FAR struct stm32_usbhost_s *priv) +{ + int chidx; + + /* Search the table of channels */ + + for (chidx = 0; chidx < STM32_NHOST_CHANNELS; chidx++) + { + /* Is this channel available? */ + + if (!priv->chan[chidx].inuse) + { + /* Yes... make it "in use" and return the index */ + + priv->chan[chidx].inuse = true; + return chidx; + } + } + + /* All of the channels are "in-use" */ + + return -EBUSY; +} + +/**************************************************************************** + * Name: stm32_chan_free + * + * Description: + * Free a previoiusly allocated channel. + * + ****************************************************************************/ + +static void stm32_chan_free(FAR struct stm32_usbhost_s *priv, int chidx) +{ + DEBUGASSERT((unsigned)chidx < STM32_NHOST_CHANNELS); + + /* Halt the channel */ + + stm32_chan_halt(priv, chidx, CHREASON_FREED); + + /* Mark the channel available */ + + priv->chan[chidx].inuse = false; +} + +/**************************************************************************** + * Name: stm32_chan_freeall + * + * Description: + * Free all channels. + * + ****************************************************************************/ + +static inline void stm32_chan_freeall(FAR struct stm32_usbhost_s *priv) +{ + uint8_t chidx; + + /* Free all host channels */ + + for (chidx = 2; chidx < STM32_NHOST_CHANNELS; chidx ++) + { + stm32_chan_free(priv, chidx); + } +} + +/**************************************************************************** + * Name: stm32_chan_configure + * + * Description: + * Configure or re-configure a host channel. Host channels are configured + * when endpoint is allocated and EP0 (only) is re-configured with the + * max packet size or device address changes. + * + ****************************************************************************/ + +static void stm32_chan_configure(FAR struct stm32_usbhost_s *priv, int chidx) +{ + FAR struct stm32_chan_s *chan = &priv->chan[chidx]; + uint32_t regval; + + /* Clear any old pending interrupts for this host channel. */ + + stm32_putreg(STM32_OTG_HCINT(chidx), 0xffffffff); + + /* Enable channel interrupts required for transfers on this channel. */ + + regval = 0; + + switch (chan->eptype) + { + case OTG_EPTYPE_CTRL: + case OTG_EPTYPE_BULK: + { +#ifdef HAVE_USBHOST_TRACE_VERBOSE + uint16_t intrace; + uint16_t outtrace; + + /* Determine the definitive trace ID to use below */ + + if (chan->eptype == OTG_EPTYPE_CTRL) + { + intrace = OTG_VTRACE2_CHANCONF_CTRL_IN; + outtrace = OTG_VTRACE2_CHANCONF_CTRL_OUT; + } + else + { + intrace = OTG_VTRACE2_CHANCONF_BULK_IN; + outtrace = OTG_VTRACE2_CHANCONF_BULK_OUT; + } +#endif + + /* Interrupts required for CTRL and BULK endpoints */ + + regval |= (OTG_HCINT_XFRC | OTG_HCINT_STALL | OTG_HCINT_NAK | + OTG_HCINT_TXERR | OTG_HCINT_DTERR); + + /* Additional setting for IN/OUT endpoints */ + + if (chan->in) + { + usbhost_vtrace2(intrace, chidx, chan->epno); + regval |= OTG_HCINT_BBERR; + } + else + { + usbhost_vtrace2(outtrace, chidx, chan->epno); + regval |= OTG_HCINT_NYET; + } + } + break; + + case OTG_EPTYPE_INTR: + { + /* Interrupts required for INTR endpoints */ + + regval |= (OTG_HCINT_XFRC | OTG_HCINT_STALL | OTG_HCINT_NAK | + OTG_HCINT_TXERR | OTG_HCINT_FRMOR | OTG_HCINT_DTERR); + + /* Additional setting for IN endpoints */ + + if (chan->in) + { + usbhost_vtrace2(OTG_VTRACE2_CHANCONF_INTR_IN, chidx, + chan->epno); + regval |= OTG_HCINT_BBERR; + } +#ifdef HAVE_USBHOST_TRACE_VERBOSE + else + { + usbhost_vtrace2(OTG_VTRACE2_CHANCONF_INTR_OUT, chidx, + chan->epno); + } +#endif + } + break; + + case OTG_EPTYPE_ISOC: + { + /* Interrupts required for ISOC endpoints */ + + regval |= (OTG_HCINT_XFRC | OTG_HCINT_ACK | OTG_HCINT_FRMOR); + + /* Additional setting for IN endpoints */ + + if (chan->in) + { + usbhost_vtrace2(OTG_VTRACE2_CHANCONF_ISOC_IN, chidx, + chan->epno); + regval |= (OTG_HCINT_TXERR | OTG_HCINT_BBERR); + } +#ifdef HAVE_USBHOST_TRACE_VERBOSE + else + { + usbhost_vtrace2(OTG_VTRACE2_CHANCONF_ISOC_OUT, chidx, + chan->epno); + } +#endif + } + break; + } + + stm32_putreg(STM32_OTG_HCINTMSK(chidx), regval); + + /* Enable the top level host channel interrupt. */ + + stm32_modifyreg(STM32_OTG_HAINTMSK, 0, OTG_HAINT(chidx)); + + /* Make sure host channel interrupts are enabled. */ + + stm32_modifyreg(STM32_OTG_GINTMSK, 0, OTG_GINT_HC); + + /* Program the HCCHAR register */ + + regval = ((uint32_t)chan->maxpacket << OTG_HCCHAR_MPSIZ_SHIFT) | + ((uint32_t)chan->epno << OTG_HCCHAR_EPNUM_SHIFT) | + ((uint32_t)chan->eptype << OTG_HCCHAR_EPTYP_SHIFT) | + ((uint32_t)chan->funcaddr << OTG_HCCHAR_DAD_SHIFT); + + /* Special case settings for low speed devices */ + + if (chan->speed == USB_SPEED_LOW) + { + regval |= OTG_HCCHAR_LSDEV; + } + + /* Special case settings for IN endpoints */ + + if (chan->in) + { + regval |= OTG_HCCHAR_EPDIR_IN; + } + + /* Special case settings for INTR endpoints */ + + if (chan->eptype == OTG_EPTYPE_INTR) + { + regval |= OTG_HCCHAR_ODDFRM; + } + + /* Write the channel configuration */ + + stm32_putreg(STM32_OTG_HCCHAR(chidx), regval); +} + +/**************************************************************************** + * Name: stm32_chan_halt + * + * Description: + * Halt the channel associated with 'chidx' by setting the CHannel DISable + * (CHDIS) bit in in the HCCHAR register. + * + ****************************************************************************/ + +static void stm32_chan_halt(FAR struct stm32_usbhost_s *priv, int chidx, + enum stm32_chreason_e chreason) +{ + uint32_t hcchar; + uint32_t intmsk; + uint32_t eptype; + unsigned int avail; + + /* Save the reason for the halt. We need this in the channel halt interrupt + * handling logic to know what to do next. + */ + + usbhost_vtrace2(OTG_VTRACE2_CHANHALT, chidx, chreason); + + priv->chan[chidx].chreason = (uint8_t)chreason; + + /* "The application can disable any channel by programming the OTG_FS_HCCHARx + * register with the CHDIS and CHENA bits set to 1. This enables the OTG_FS + * host to flush the posted requests (if any) and generates a channel halted + * interrupt. The application must wait for the CHH interrupt in OTG_FS_HCINTx + * before reallocating the channel for other transactions. The OTG_FS host + * does not interrupt the transaction that has already been started on the + * USB." + */ + + hcchar = stm32_getreg(STM32_OTG_HCCHAR(chidx)); + hcchar |= (OTG_HCCHAR_CHDIS | OTG_HCCHAR_CHENA); + + /* Get the endpoint type from the HCCHAR register */ + + eptype = hcchar & OTG_HCCHAR_EPTYP_MASK; + + /* Check for space in the Tx FIFO to issue the halt. + * + * "Before disabling a channel, the application must ensure that there is at + * least one free space available in the non-periodic request queue (when + * disabling a non-periodic channel) or the periodic request queue (when + * disabling a periodic channel). The application can simply flush the + * posted requests when the Request queue is full (before disabling the + * channel), by programming the OTG_FS_HCCHARx register with the CHDIS bit + * set to 1, and the CHENA bit cleared to 0. + */ + + if (eptype == OTG_HCCHAR_EPTYP_CTRL || eptype == OTG_HCCHAR_EPTYP_BULK) + { + /* Get the number of words available in the non-periodic Tx FIFO. */ + + avail = stm32_getreg(STM32_OTG_HNPTXSTS) & OTG_HNPTXSTS_NPTXFSAV_MASK; + } + else /* if (eptype == OTG_HCCHAR_EPTYP_ISOC || eptype == OTG_HCCHAR_EPTYP_INTR) */ + { + /* Get the number of words available in the non-periodic Tx FIFO. */ + + avail = stm32_getreg(STM32_OTG_HPTXSTS) & OTG_HPTXSTS_PTXFSAVL_MASK; + } + + /* Check if there is any space available in the Tx FIFO. */ + + if (avail == 0) + { + /* The Tx FIFO is full... disable the channel to flush the requests */ + + hcchar &= ~OTG_HCCHAR_CHENA; + } + + /* Unmask the CHannel Halted (CHH) interrupt */ + + intmsk = stm32_getreg(STM32_OTG_HCINTMSK(chidx)); + intmsk |= OTG_HCINT_CHH; + stm32_putreg(STM32_OTG_HCINTMSK(chidx), intmsk); + + /* Halt the channel by setting CHDIS (and maybe CHENA) in the HCCHAR */ + + stm32_putreg(STM32_OTG_HCCHAR(chidx), hcchar); +} + +/**************************************************************************** + * Name: stm32_chan_waitsetup + * + * Description: + * Set the request for the transfer complete event well BEFORE enabling the + * transfer (as soon as we are absolutely committed to the to avoid transfer). + * We do this to minimize race conditions. This logic would have to be expanded + * if we want to have more than one packet in flight at a time! + * + * Assumptions: + * Called from a normal thread context BEFORE the transfer has been started. + * + ****************************************************************************/ + +static int stm32_chan_waitsetup(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan) +{ + irqstate_t flags = enter_critical_section(); + int ret = -ENODEV; + + /* Is the device still connected? */ + + if (priv->connected) + { + /* Yes.. then set waiter to indicate that we expect to be informed when + * either (1) the device is disconnected, or (2) the transfer completed. + */ + + chan->waiter = true; +#ifdef CONFIG_USBHOST_ASYNCH + chan->callback = NULL; + chan->arg = NULL; +#endif + ret = OK; + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: stm32_chan_asynchsetup + * + * Description: + * Set the request for the transfer complete event well BEFORE enabling the + * transfer (as soon as we are absolutely committed to the to avoid transfer). + * We do this to minimize race conditions. This logic would have to be expanded + * if we want to have more than one packet in flight at a time! + * + * Assumptions: + * Might be called from the level of an interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_chan_asynchsetup(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan, + usbhost_asynch_t callback, FAR void *arg) +{ + irqstate_t flags = enter_critical_section(); + int ret = -ENODEV; + + /* Is the device still connected? */ + + if (priv->connected) + { + /* Yes.. then set waiter to indicate that we expect to be informed when + * either (1) the device is disconnected, or (2) the transfer completed. + */ + + chan->waiter = false; + chan->callback = callback; + chan->arg = arg; + ret = OK; + } + + leave_critical_section(flags); + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_chan_wait + * + * Description: + * Wait for a transfer on a channel to complete. + * + * Assumptions: + * Called from a normal thread context + * + ****************************************************************************/ + +static int stm32_chan_wait(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan) +{ + irqstate_t flags; + int ret; + + /* Disable interrupts so that the following operations will be atomic. On + * the OTG FS global interrupt needs to be disabled. However, here we disable + * all interrupts to exploit that fact that interrupts will be re-enabled + * while we wait. + */ + + flags = enter_critical_section(); + + /* Loop, testing for an end of transfer condition. The channel 'result' + * was set to EBUSY and 'waiter' was set to true before the transfer; 'waiter' + * will be set to false and 'result' will be set appropriately when the + * transfer is completed. + */ + + do + { + /* Wait for the transfer to complete. NOTE the transfer may already + * completed before we get here or the transfer may complete while we + * wait here. + */ + + ret = sem_wait(&chan->waitsem); + + /* sem_wait should succeed. But it is possible that we could be + * awakened by a signal too. + */ + + DEBUGASSERT(ret == OK || get_errno() == EINTR); + } + while (chan->waiter); + + /* The transfer is complete re-enable interrupts and return the result */ + + ret = -(int)chan->result; + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: stm32_chan_wakeup + * + * Description: + * A channel transfer has completed... wakeup any threads waiting for the + * transfer to complete. + * + * Assumptions: + * This function is called from the transfer complete interrupt handler for + * the channel. Interrupts are disabled. + * + ****************************************************************************/ + +static void stm32_chan_wakeup(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan) +{ + /* Is the transfer complete? */ + + if (chan->result != EBUSY) + { + /* Is there a thread waiting for this transfer to complete? */ + + if (chan->waiter) + { +#ifdef CONFIG_USBHOST_ASYNCH + /* Yes.. there should not also be a callback scheduled */ + + DEBUGASSERT(chan->callback == NULL); +#endif + /* Wake'em up! */ + + usbhost_vtrace2(chan->in ? OTG_VTRACE2_CHANWAKEUP_IN : + OTG_VTRACE2_CHANWAKEUP_OUT, + chan->epno, chan->result); + + stm32_givesem(&chan->waitsem); + chan->waiter = false; + } + +#ifdef CONFIG_USBHOST_ASYNCH + /* No.. is an asynchronous callback expected when the transfer + * completes? + */ + + else if (chan->callback) + { + /* Handle continuation of IN/OUT pipes */ + + if (chan->in) + { + stm32_in_next(priv, chan); + } + else + { + stm32_out_next(priv, chan); + } + } +#endif + } +} + +/**************************************************************************** + * Name: stm32_ctrlchan_alloc + * + * Description: + * Allocate and configured channels for a control pipe. + * + ****************************************************************************/ + +static int stm32_ctrlchan_alloc(FAR struct stm32_usbhost_s *priv, + uint8_t epno, uint8_t funcaddr, uint8_t speed, + FAR struct stm32_ctrlinfo_s *ctrlep) +{ + FAR struct stm32_chan_s *chan; + int inndx; + int outndx; + + outndx = stm32_chan_alloc(priv); + if (outndx < 0) + { + return -ENOMEM; + } + + ctrlep->outndx = outndx; + chan = &priv->chan[outndx]; + chan->epno = epno; + chan->in = false; + chan->eptype = OTG_EPTYPE_CTRL; + chan->funcaddr = funcaddr; + chan->speed = speed; + chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE; + chan->indata1 = false; + chan->outdata1 = false; + + /* Configure control OUT channels */ + + stm32_chan_configure(priv, outndx); + + /* Allocate and initialize the control IN channel */ + + inndx = stm32_chan_alloc(priv); + if (inndx < 0) + { + stm32_chan_free(priv, outndx); + return -ENOMEM; + } + + ctrlep->inndx = inndx; + chan = &priv->chan[inndx]; + chan->epno = epno; + chan->in = true; + chan->eptype = OTG_EPTYPE_CTRL; + chan->funcaddr = funcaddr; + chan->speed = speed; + chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE; + chan->indata1 = false; + chan->outdata1 = false; + + /* Configure control IN channels */ + + stm32_chan_configure(priv, inndx); + return OK; +} + +/**************************************************************************** + * Name: stm32_ctrlep_alloc + * + * Description: + * Allocate a container and channels for control pipe. + * + * Input Parameters: + * priv - The private USB host driver state. + * epdesc - Describes the endpoint to be allocated. + * ep - A memory location provided by the caller in which to receive the + * allocated endpoint descriptor. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_ctrlep_alloc(FAR struct stm32_usbhost_s *priv, + FAR const struct usbhost_epdesc_s *epdesc, + FAR usbhost_ep_t *ep) +{ + FAR struct usbhost_hubport_s *hport; + FAR struct stm32_ctrlinfo_s *ctrlep; + int ret; + + /* Sanity check. NOTE that this method should only be called if a device is + * connected (because we need a valid low speed indication). + */ + + DEBUGASSERT(epdesc->hport != NULL); + hport = epdesc->hport; + + /* Allocate a container for the control endpoint */ + + ctrlep = (FAR struct stm32_ctrlinfo_s *)kmm_malloc(sizeof(struct stm32_ctrlinfo_s)); + if (ctrlep == NULL) + { + uerr("ERROR: Failed to allocate control endpoint container\n"); + return -ENOMEM; + } + + /* Then allocate and configure the IN/OUT channnels */ + + ret = stm32_ctrlchan_alloc(priv, epdesc->addr & USB_EPNO_MASK, + hport->funcaddr, hport->speed, ctrlep); + if (ret < 0) + { + uerr("ERROR: stm32_ctrlchan_alloc failed: %d\n", ret); + kmm_free(ctrlep); + return ret; + } + + /* Return a pointer to the control pipe container as the pipe "handle" */ + + *ep = (usbhost_ep_t)ctrlep; + return OK; +} + +/************************************************************************************ + * Name: stm32_xfrep_alloc + * + * Description: + * Allocate and configure one unidirectional endpoint. + * + * Input Parameters: + * priv - The private USB host driver state. + * epdesc - Describes the endpoint to be allocated. + * ep - A memory location provided by the caller in which to receive the + * allocated endpoint descriptor. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ************************************************************************************/ + +static int stm32_xfrep_alloc(FAR struct stm32_usbhost_s *priv, + FAR const struct usbhost_epdesc_s *epdesc, + FAR usbhost_ep_t *ep) +{ + struct usbhost_hubport_s *hport; + FAR struct stm32_chan_s *chan; + int chidx; + + /* Sanity check. NOTE that this method should only be called if a device is + * connected (because we need a valid low speed indication). + */ + + DEBUGASSERT(epdesc->hport != NULL); + hport = epdesc->hport; + + /* Allocate a host channel for the endpoint */ + + chidx = stm32_chan_alloc(priv); + if (chidx < 0) + { + uerr("ERROR: Failed to allocate a host channel\n"); + return -ENOMEM; + } + + /* Decode the endpoint descriptor to initialize the channel data structures. + * Note: Here we depend on the fact that the endpoint point type is + * encoded in the same way in the endpoint descriptor as it is in the OTG + * HS hardware. + */ + + chan = &priv->chan[chidx]; + chan->epno = epdesc->addr & USB_EPNO_MASK; + chan->in = epdesc->in; + chan->eptype = epdesc->xfrtype; + chan->funcaddr = hport->funcaddr; + chan->speed = hport->speed; + chan->maxpacket = epdesc->mxpacketsize; + chan->indata1 = false; + chan->outdata1 = false; + + /* Then configure the endpoint */ + + stm32_chan_configure(priv, chidx); + + /* Return the index to the allocated channel as the endpoint "handle" */ + + *ep = (usbhost_ep_t)chidx; + return OK; +} + +/**************************************************************************** + * Name: stm32_transfer_start + * + * Description: + * Start at transfer on the select IN or OUT channel. + * + ****************************************************************************/ + +static void stm32_transfer_start(FAR struct stm32_usbhost_s *priv, int chidx) +{ + FAR struct stm32_chan_s *chan; + uint32_t regval; + unsigned int npackets; + unsigned int maxpacket; + unsigned int avail; + unsigned int wrsize; + unsigned int minsize; + + /* Set up the initial state of the transfer */ + + chan = &priv->chan[chidx]; + + usbhost_vtrace2(OTG_VTRACE2_STARTTRANSFER, chidx, chan->buflen); + + chan->result = EBUSY; + chan->inflight = 0; + chan->xfrd = 0; + priv->chidx = chidx; + + /* Compute the expected number of packets associated to the transfer. + * If the transfer length is zero (or less than the size of one maximum + * size packet), then one packet is expected. + */ + + /* If the transfer size is greater than one packet, then calculate the + * number of packets that will be received/sent, including any partial + * final packet. + */ + + maxpacket = chan->maxpacket; + + if (chan->buflen > maxpacket) + { + npackets = (chan->buflen + maxpacket - 1) / maxpacket; + + /* Clip if the buffer length if it exceeds the maximum number of + * packets that can be transferred (this should not happen). + */ + + if (npackets > STM32_MAX_PKTCOUNT) + { + npackets = STM32_MAX_PKTCOUNT; + chan->buflen = STM32_MAX_PKTCOUNT * maxpacket; + usbhost_trace2(OTG_TRACE2_CLIP, chidx, chan->buflen); + } + } + else + { + /* One packet will be sent/received (might be a zero length packet) */ + + npackets = 1; + } + + /* If it is an IN transfer, then adjust the size of the buffer UP to + * a full number of packets. Hmmm... couldn't this cause an overrun + * into unallocated memory? + */ + +#if 0 /* Think about this */ + if (chan->in) + { + /* Force the buffer length to an even multiple of maxpacket */ + + chan->buflen = npackets * maxpacket; + } +#endif + + /* Save the number of packets in the transfer. We will need this in + * order to set the next data toggle correctly when the transfer + * completes. + */ + + chan->npackets = (uint8_t)npackets; + + /* Setup the HCTSIZn register */ + + regval = ((uint32_t)chan->buflen << OTG_HCTSIZ_XFRSIZ_SHIFT) | + ((uint32_t)npackets << OTG_HCTSIZ_PKTCNT_SHIFT) | + ((uint32_t)chan->pid << OTG_HCTSIZ_DPID_SHIFT); + stm32_putreg(STM32_OTG_HCTSIZ(chidx), regval); + + /* Setup the HCCHAR register: Frame oddness and host channel enable */ + + regval = stm32_getreg(STM32_OTG_HCCHAR(chidx)); + + /* Set/clear the Odd Frame bit. Check for an even frame; if so set Odd + * Frame. This field is applicable for only periodic (isochronous and + * interrupt) channels. + */ + + if ((stm32_getreg(STM32_OTG_HFNUM) & 1) == 0) + { + regval |= OTG_HCCHAR_ODDFRM; + } + else + { + regval &= ~OTG_HCCHAR_ODDFRM; + } + + regval &= ~OTG_HCCHAR_CHDIS; + regval |= OTG_HCCHAR_CHENA; + stm32_putreg(STM32_OTG_HCCHAR(chidx), regval); + + /* If this is an out transfer, then we need to do more.. we need to copy + * the outgoing data into the correct TxFIFO. + */ + + if (!chan->in && chan->buflen > 0) + { + /* Handle non-periodic (CTRL and BULK) OUT transfers differently than + * periodic (INTR and ISOC) OUT transfers. + */ + + minsize = MIN(chan->buflen, chan->maxpacket); + + switch (chan->eptype) + { + case OTG_EPTYPE_CTRL: /* Non periodic transfer */ + case OTG_EPTYPE_BULK: + { + /* Read the Non-periodic Tx FIFO status register */ + + regval = stm32_getreg(STM32_OTG_HNPTXSTS); + avail = ((regval & OTG_HNPTXSTS_NPTXFSAV_MASK) >> OTG_HNPTXSTS_NPTXFSAV_SHIFT) << 2; + } + break; + + /* Periodic transfer */ + + case OTG_EPTYPE_INTR: + case OTG_EPTYPE_ISOC: + { + /* Read the Non-periodic Tx FIFO status register */ + + regval = stm32_getreg(STM32_OTG_HPTXSTS); + avail = ((regval & OTG_HPTXSTS_PTXFSAVL_MASK) >> OTG_HPTXSTS_PTXFSAVL_SHIFT) << 2; + } + break; + + default: + DEBUGASSERT(false); + return; + } + + /* Is there space in the TxFIFO to hold the minimum size packet? */ + + if (minsize <= avail) + { + /* Yes.. Get the size of the biggest thing that we can put in the Tx FIFO now */ + + wrsize = chan->buflen; + if (wrsize > avail) + { + /* Clip the write size to the number of full, max sized packets + * that will fit in the Tx FIFO. + */ + + unsigned int wrpackets = avail / chan->maxpacket; + wrsize = wrpackets * chan->maxpacket; + } + + /* Write packet into the Tx FIFO. */ + + stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); + } + + /* Did we put the entire buffer into the Tx FIFO? */ + + if (chan->buflen > avail) + { + /* No, there was insufficient space to hold the entire transfer ... + * Enable the Tx FIFO interrupt to handle the transfer when the Tx + * FIFO becomes empty. + */ + + stm32_txfe_enable(priv, chidx); + } + } +} + +/**************************************************************************** + * Name: stm32_getframe + * + * Description: + * Get the current frame number. The frame number (FRNUM) field increments + * when a new SOF is transmitted on the USB, and is cleared to 0 when it + * reaches 0x3fff. + * + ****************************************************************************/ + +#if 0 /* Not used */ +static inline uint16_t stm32_getframe(void) +{ + return (uint16_t)(stm32_getreg(STM32_OTG_HFNUM) & OTG_HFNUM_FRNUM_MASK); +} +#endif + +/**************************************************************************** + * Name: stm32_ctrl_sendsetup + * + * Description: + * Send an IN/OUT SETUP packet. + * + ****************************************************************************/ + +static int stm32_ctrl_sendsetup(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_ctrlinfo_s *ep0, + FAR const struct usb_ctrlreq_s *req) +{ + FAR struct stm32_chan_s *chan; + systime_t start; + systime_t elapsed; + int ret; + + /* Loop while the device reports NAK (and a timeout is not exceeded */ + + chan = &priv->chan[ep0->outndx]; + start = clock_systimer(); + + do + { + /* Send the SETUP packet */ + + chan->pid = OTG_PID_SETUP; + chan->buffer = (FAR uint8_t *)req; + chan->buflen = USB_SIZEOF_CTRLREQ; + chan->xfrd = 0; + + /* Set up for the wait BEFORE starting the transfer */ + + ret = stm32_chan_waitsetup(priv, chan); + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_DEVDISCONN, 0); + return ret; + } + + /* Start the transfer */ + + stm32_transfer_start(priv, ep0->outndx); + + /* Wait for the transfer to complete */ + + ret = stm32_chan_wait(priv, chan); + + /* Return on success and for all failures other than EAGAIN. EAGAIN + * means that the device NAKed the SETUP command and that we should + * try a few more times. + */ + + if (ret != -EAGAIN) + { + /* Output some debug information if the transfer failed */ + + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_TRNSFRFAILED, ret); + } + + /* Return the result in any event */ + + return ret; + } + + /* Get the elapsed time (in frames) */ + + elapsed = clock_systimer() - start; + } + while (elapsed < STM32_SETUP_DELAY); + + return -ETIMEDOUT; +} + +/**************************************************************************** + * Name: stm32_ctrl_senddata + * + * Description: + * Send data in the data phase of an OUT control transfer. Or send status + * in the status phase of an IN control transfer + * + ****************************************************************************/ + +static int stm32_ctrl_senddata(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_ctrlinfo_s *ep0, + FAR uint8_t *buffer, unsigned int buflen) +{ + FAR struct stm32_chan_s *chan = &priv->chan[ep0->outndx]; + int ret; + + /* Save buffer information */ + + chan->buffer = buffer; + chan->buflen = buflen; + chan->xfrd = 0; + + /* Set the DATA PID */ + + if (buflen == 0) + { + /* For status OUT stage with buflen == 0, set PID DATA1 */ + + chan->outdata1 = true; + } + + /* Set the Data PID as per the outdata1 boolean */ + + chan->pid = chan->outdata1 ? OTG_PID_DATA1 : OTG_PID_DATA0; + + /* Set up for the wait BEFORE starting the transfer */ + + ret = stm32_chan_waitsetup(priv, chan); + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_DEVDISCONN, 0); + return ret; + } + + /* Start the transfer */ + + stm32_transfer_start(priv, ep0->outndx); + + /* Wait for the transfer to complete and return the result */ + + return stm32_chan_wait(priv, chan); +} + +/**************************************************************************** + * Name: stm32_ctrl_recvdata + * + * Description: + * Receive data in the data phase of an IN control transfer. Or receive status + * in the status phase of an OUT control transfer + * + ****************************************************************************/ + +static int stm32_ctrl_recvdata(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_ctrlinfo_s *ep0, + FAR uint8_t *buffer, unsigned int buflen) +{ + FAR struct stm32_chan_s *chan = &priv->chan[ep0->inndx]; + int ret; + + /* Save buffer information */ + + chan->pid = OTG_PID_DATA1; + chan->buffer = buffer; + chan->buflen = buflen; + chan->xfrd = 0; + + /* Set up for the wait BEFORE starting the transfer */ + + ret = stm32_chan_waitsetup(priv, chan); + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_DEVDISCONN, 0); + return ret; + } + + /* Start the transfer */ + + stm32_transfer_start(priv, ep0->inndx); + + /* Wait for the transfer to complete and return the result */ + + return stm32_chan_wait(priv, chan); +} + +/**************************************************************************** + * Name: stm32_in_setup + * + * Description: + * Initiate an IN transfer on an bulk, interrupt, or isochronous pipe. + * + ****************************************************************************/ + +static int stm32_in_setup(FAR struct stm32_usbhost_s *priv, int chidx) +{ + FAR struct stm32_chan_s *chan; + + /* Set up for the transfer based on the direction and the endpoint type */ + + chan = &priv->chan[chidx]; + switch (chan->eptype) + { + default: + case OTG_EPTYPE_CTRL: /* Control */ + { + /* This kind of transfer on control endpoints other than EP0 are not + * currently supported + */ + + return -ENOSYS; + } + + case OTG_EPTYPE_ISOC: /* Isochronous */ + { + /* Set up the IN data PID */ + + usbhost_vtrace2(OTG_VTRACE2_ISOCIN, chidx, chan->buflen); + chan->pid = OTG_PID_DATA0; + } + break; + + case OTG_EPTYPE_BULK: /* Bulk */ + { + /* Setup the IN data PID */ + + usbhost_vtrace2(OTG_VTRACE2_BULKIN, chidx, chan->buflen); + chan->pid = chan->indata1 ? OTG_PID_DATA1 : OTG_PID_DATA0; + } + break; + + case OTG_EPTYPE_INTR: /* Interrupt */ + { + /* Setup the IN data PID */ + + usbhost_vtrace2(OTG_VTRACE2_INTRIN, chidx, chan->buflen); + chan->pid = chan->indata1 ? OTG_PID_DATA1 : OTG_PID_DATA0; + } + break; + } + + /* Start the transfer */ + + stm32_transfer_start(priv, chidx); + return OK; +} + +/**************************************************************************** + * Name: stm32_in_transfer + * + * Description: + * Transfer 'buflen' bytes into 'buffer' from an IN channel. + * + ****************************************************************************/ + +static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx, + FAR uint8_t *buffer, size_t buflen) +{ + FAR struct stm32_chan_s *chan; + systime_t start; + systime_t elapsed; + int ret; + + /* Loop until the transfer completes (i.e., buflen is decremented to zero) + * or a fatal error occurs (any error other than a simple NAK) + */ + + chan = &priv->chan[chidx]; + chan->buffer = buffer; + chan->buflen = buflen; + chan->xfrd = 0; + + start = clock_systimer(); + while (chan->xfrd < chan->buflen) + { + /* Set up for the wait BEFORE starting the transfer */ + + ret = stm32_chan_waitsetup(priv, chan); + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_DEVDISCONN, 0); + return (ssize_t)ret; + } + + /* Set up for the transfer based on the direction and the endpoint type */ + + ret = stm32_in_setup(priv, chidx); + if (ret < 0) + { + uerr("ERROR: stm32_in_setup failed: %d\n", ret); + return (ssize_t)ret; + } + + /* Wait for the transfer to complete and get the result */ + + ret = stm32_chan_wait(priv, chan); + + /* EAGAIN indicates that the device NAKed the transfer and we need + * do try again. Anything else (success or other errors) will + * cause use to return + */ + + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_TRNSFRFAILED, ret); + + /* Check for a special case: If (1) the transfer was NAKed and (2) + * no Tx FIFO empty or Rx FIFO not-empty event occurred, then we + * should be able to just flush the Rx and Tx FIFOs and try again. + * We can detect this latter case because the then the transfer + * buffer pointer and buffer size will be unaltered. + */ + + elapsed = clock_systimer() - start; + if (ret != -EAGAIN || /* Not a NAK condition OR */ + elapsed >= STM32_DATANAK_DELAY || /* Timeout has elapsed OR */ + chan->xfrd > 0) /* Data has been partially transferred */ + { + /* Break out and return the error */ + + uerr("ERROR: stm32_chan_wait failed: %d\n", ret); + return (ssize_t)ret; + } + } + } + + return (ssize_t)chan->xfrd; +} + +/**************************************************************************** + * Name: stm32_in_next + * + * Description: + * Initiate the next of a sequence of asynchronous transfers. + * + * Assumptions: + * This function is always called from an interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static void stm32_in_next(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan) +{ + usbhost_asynch_t callback; + FAR void *arg; + ssize_t nbytes; + int result; + int ret; + + /* Is the full transfer complete? Did the last chunk transfer complete OK? */ + + result = -(int)chan->result; + if (chan->xfrd < chan->buflen && result == OK) + { + /* Yes.. Set up for the next transfer based on the direction and the + * endpoint type + */ + + ret = stm32_in_setup(priv, chan->chidx); + if (ret >= 0) + { + return; + } + + uerr("ERROR: stm32_in_setup failed: %d\n", ret); + result = ret; + } + + /* The transfer is complete, with or without an error */ + + uinfo("Transfer complete: %d\n", result); + + /* Extract the callback information */ + + callback = chan->callback; + arg = chan->arg; + nbytes = chan->xfrd; + + chan->callback = NULL; + chan->arg = NULL; + chan->xfrd = 0; + + /* Then perform the callback */ + + if (result < 0) + { + nbytes = (ssize_t)result; + } + + callback(arg, nbytes); +} +#endif + +/**************************************************************************** + * Name: stm32_in_asynch + * + * Description: + * Initiate the first of a sequence of asynchronous transfers. + * + * Assumptions: + * This function is never called from an interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_in_asynch(FAR struct stm32_usbhost_s *priv, int chidx, + FAR uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, FAR void *arg) +{ + FAR struct stm32_chan_s *chan; + int ret; + + /* Set up for the transfer data and callback BEFORE starting the first transfer */ + + chan = &priv->chan[chidx]; + chan->buffer = buffer; + chan->buflen = buflen; + chan->xfrd = 0; + + ret = stm32_chan_asynchsetup(priv, chan, callback, arg); + if (ret < 0) + { + uerr("ERROR: stm32_chan_asynchsetup failed: %d\n", ret); + return ret; + } + + /* Set up for the transfer based on the direction and the endpoint type */ + + ret = stm32_in_setup(priv, chidx); + if (ret < 0) + { + uerr("ERROR: stm32_in_setup failed: %d\n", ret); + } + + /* And return with the transfer pending */ + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_out_setup + * + * Description: + * Initiate an OUT transfer on an bulk, interrupt, or isochronous pipe. + * + ****************************************************************************/ + +static int stm32_out_setup(FAR struct stm32_usbhost_s *priv, int chidx) +{ + FAR struct stm32_chan_s *chan; + + /* Set up for the transfer based on the direction and the endpoint type */ + + chan = &priv->chan[chidx]; + switch (chan->eptype) + { + default: + case OTG_EPTYPE_CTRL: /* Control */ + { + /* This kind of transfer on control endpoints other than EP0 are not + * currently supported + */ + + return -ENOSYS; + } + + case OTG_EPTYPE_ISOC: /* Isochronous */ + { + /* Set up the OUT data PID */ + + usbhost_vtrace2(OTG_VTRACE2_ISOCOUT, chidx, chan->buflen); + chan->pid = OTG_PID_DATA0; + } + break; + + case OTG_EPTYPE_BULK: /* Bulk */ + { + /* Setup the OUT data PID */ + + usbhost_vtrace2(OTG_VTRACE2_BULKOUT, chidx, chan->buflen); + chan->pid = chan->outdata1 ? OTG_PID_DATA1 : OTG_PID_DATA0; + } + break; + + case OTG_EPTYPE_INTR: /* Interrupt */ + { + /* Setup the OUT data PID */ + + usbhost_vtrace2(OTG_VTRACE2_INTROUT, chidx, chan->buflen); + chan->pid = chan->outdata1 ? OTG_PID_DATA1 : OTG_PID_DATA0; + + /* Toggle the OUT data PID for the next transfer */ + + chan->outdata1 ^= true; + } + break; + } + + /* Start the transfer */ + + stm32_transfer_start(priv, chidx); + return OK; +} + +/**************************************************************************** + * Name: stm32_out_transfer + * + * Description: + * Transfer the 'buflen' bytes in 'buffer' through an OUT channel. + * + ****************************************************************************/ + +static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx, + FAR uint8_t *buffer, size_t buflen) +{ + FAR struct stm32_chan_s *chan; + systime_t start; + systime_t elapsed; + size_t xfrlen; + ssize_t xfrd; + int ret; + + /* Loop until the transfer completes (i.e., buflen is decremented to zero) + * or a fatal error occurs (any error other than a simple NAK) + */ + + chan = &priv->chan[chidx]; + start = clock_systimer(); + xfrd = 0; + + while (buflen > 0) + { + /* Transfer one packet at a time. The hardware is capable of queueing + * multiple OUT packets, but I just haven't figured out how to handle + * the case where a single OUT packet in the group is NAKed. + */ + + xfrlen = MIN(chan->maxpacket, buflen); + chan->buffer = buffer; + chan->buflen = xfrlen; + chan->xfrd = 0; + + /* Set up for the wait BEFORE starting the transfer */ + + ret = stm32_chan_waitsetup(priv, chan); + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_DEVDISCONN, 0); + return (ssize_t)ret; + } + + /* Set up for the transfer based on the direction and the endpoint type */ + + ret = stm32_out_setup(priv, chidx); + if (ret < 0) + { + uerr("ERROR: stm32_out_setup failed: %d\n", ret); + return (ssize_t)ret; + } + + /* Wait for the transfer to complete and get the result */ + + ret = stm32_chan_wait(priv, chan); + + /* Handle transfer failures */ + + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_TRNSFRFAILED, ret); + + /* Check for a special case: If (1) the transfer was NAKed and (2) + * no Tx FIFO empty or Rx FIFO not-empty event occurred, then we + * should be able to just flush the Rx and Tx FIFOs and try again. + * We can detect this latter case because the then the transfer + * buffer pointer and buffer size will be unaltered. + */ + + elapsed = clock_systimer() - start; + if (ret != -EAGAIN || /* Not a NAK condition OR */ + elapsed >= STM32_DATANAK_DELAY || /* Timeout has elapsed OR */ + chan->xfrd > 0) /* Data has been partially transferred */ + { + /* Break out and return the error */ + + uerr("ERROR: stm32_chan_wait failed: %d\n", ret); + return (ssize_t)ret; + } + + /* Is this flush really necessary? What does the hardware do with the + * data in the FIFO when the NAK occurs? Does it discard it? + */ + + stm32_flush_txfifos(OTG_GRSTCTL_TXFNUM_HALL); + + /* Get the device a little time to catch up. Then retry the transfer + * using the same buffer pointer and length. + */ + + usleep(20*1000); + } + else + { + /* Successfully transferred. Update the buffer pointer and length */ + + buffer += xfrlen; + buflen -= xfrlen; + xfrd += chan->xfrd; + } + } + + return xfrd; +} + +/**************************************************************************** + * Name: stm32_out_next + * + * Description: + * Initiate the next of a sequence of asynchronous transfers. + * + * Assumptions: + * This function is always called from an interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static void stm32_out_next(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan) +{ + usbhost_asynch_t callback; + FAR void *arg; + ssize_t nbytes; + int result; + int ret; + + /* Is the full transfer complete? Did the last chunk transfer complete OK? */ + + result = -(int)chan->result; + if (chan->xfrd < chan->buflen && result == OK) + { + /* Yes.. Set up for the next transfer based on the direction and the + * endpoint type + */ + + ret = stm32_out_setup(priv, chan->chidx); + if (ret >= 0) + { + return; + } + + uerr("ERROR: stm32_out_setup failed: %d\n", ret); + result = ret; + } + + /* The transfer is complete, with or without an error */ + + uinfo("Transfer complete: %d\n", result); + + /* Extract the callback information */ + + callback = chan->callback; + arg = chan->arg; + nbytes = chan->xfrd; + + chan->callback = NULL; + chan->arg = NULL; + chan->xfrd = 0; + + /* Then perform the callback */ + + if (result < 0) + { + nbytes = (ssize_t)result; + } + + callback(arg, nbytes); +} +#endif + +/**************************************************************************** + * Name: stm32_out_asynch + * + * Description: + * Initiate the first of a sequence of asynchronous transfers. + * + * Assumptions: + * This function is never called from an interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_out_asynch(FAR struct stm32_usbhost_s *priv, int chidx, + FAR uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, FAR void *arg) +{ + FAR struct stm32_chan_s *chan; + int ret; + + /* Set up for the transfer data and callback BEFORE starting the first transfer */ + + chan = &priv->chan[chidx]; + chan->buffer = buffer; + chan->buflen = buflen; + chan->xfrd = 0; + + ret = stm32_chan_asynchsetup(priv, chan, callback, arg); + if (ret < 0) + { + uerr("ERROR: stm32_chan_asynchsetup failed: %d\n", ret); + return ret; + } + + /* Set up for the transfer based on the direction and the endpoint type */ + + ret = stm32_out_setup(priv, chidx); + if (ret < 0) + { + uerr("ERROR: stm32_out_setup failed: %d\n", ret); + } + + /* And return with the transfer pending */ + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_gint_wrpacket + * + * Description: + * Transfer the 'buflen' bytes in 'buffer' to the Tx FIFO associated with + * 'chidx' (non-DMA). + * + ****************************************************************************/ + +static void stm32_gint_wrpacket(FAR struct stm32_usbhost_s *priv, + FAR uint8_t *buffer, int chidx, int buflen) +{ + FAR uint32_t *src; + uint32_t fifo; + int buflen32; + + stm32_pktdump("Sending", buffer, buflen); + + /* Get the number of 32-byte words associated with this byte size */ + + buflen32 = (buflen + 3) >> 2; + + /* Get the address of the Tx FIFO associated with this channel */ + + fifo = STM32_OTG_DFIFO_HCH(chidx); + + /* Transfer all of the data into the Tx FIFO */ + + src = (FAR uint32_t *)buffer; + for (; buflen32 > 0; buflen32--) + { + uint32_t data = *src++; + stm32_putreg(fifo, data); + } + + /* Increment the count of bytes "in-flight" in the Tx FIFO */ + + priv->chan[chidx].inflight += buflen; +} + +/**************************************************************************** + * Name: stm32_gint_hcinisr + * + * Description: + * USB OTG FS host IN channels interrupt handler + * + * One the completion of the transfer, the channel result byte may be set as + * follows: + * + * OK - Transfer completed successfully + * EAGAIN - If devices NAKs the transfer or NYET occurs + * EPERM - If the endpoint stalls + * EIO - On a TX or data toggle error + * EPIPE - Frame overrun + * + * EBUSY in the result field indicates that the transfer has not completed. + * + ****************************************************************************/ + +static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv, + int chidx) +{ + FAR struct stm32_chan_s *chan = &priv->chan[chidx]; + uint32_t regval; + uint32_t pending; + + /* Read the HCINT register to get the pending HC interrupts. Read the + * HCINTMSK register to get the set of enabled HC interrupts. + */ + + pending = stm32_getreg(STM32_OTG_HCINT(chidx)); + regval = stm32_getreg(STM32_OTG_HCINTMSK(chidx)); + + /* AND the two to get the set of enabled, pending HC interrupts */ + + pending &= regval; + ullinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending); + + /* Check for a pending ACK response received/transmitted (ACK) interrupt */ + + if ((pending & OTG_HCINT_ACK) != 0) + { + /* Clear the pending the ACK response received/transmitted (ACK) interrupt */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_ACK); + } + + /* Check for a pending STALL response receive (STALL) interrupt */ + + else if ((pending & OTG_HCINT_STALL) != 0) + { + /* Clear the NAK and STALL Conditions. */ + + stm32_putreg(STM32_OTG_HCINT(chidx), (OTG_HCINT_NAK | OTG_HCINT_STALL)); + + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_STALL); + + /* When there is a STALL, clear any pending NAK so that it is not + * processed below. + */ + + pending &= ~OTG_HCINT_NAK; + } + + /* Check for a pending Data Toggle ERRor (DTERR) interrupt */ + + else if ((pending & OTG_HCINT_DTERR) != 0) + { + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_DTERR); + + /* Clear the NAK and data toggle error conditions */ + + stm32_putreg(STM32_OTG_HCINT(chidx), (OTG_HCINT_NAK | OTG_HCINT_DTERR)); + } + + /* Check for a pending FRaMe OverRun (FRMOR) interrupt */ + + if ((pending & OTG_HCINT_FRMOR) != 0) + { + /* Halt the channel -- the CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_FRMOR); + + /* Clear the FRaMe OverRun (FRMOR) condition */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_FRMOR); + } + + /* Check for a pending TransFeR Completed (XFRC) interrupt */ + + else if ((pending & OTG_HCINT_XFRC) != 0) + { + /* Clear the TransFeR Completed (XFRC) condition */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_XFRC); + + /* Then handle the transfer completion event based on the endpoint type */ + + if (chan->eptype == OTG_EPTYPE_CTRL || chan->eptype == OTG_EPTYPE_BULK) + { + /* Halt the channel -- the CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_XFRC); + + /* Clear any pending NAK condition. The 'indata1' data toggle + * should have been appropriately updated by the RxFIFO + * logic as each packet was received. + */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_NAK); + } + else if (chan->eptype == OTG_EPTYPE_INTR) + { + /* Force the next transfer on an ODD frame */ + + regval = stm32_getreg(STM32_OTG_HCCHAR(chidx)); + regval |= OTG_HCCHAR_ODDFRM; + stm32_putreg(STM32_OTG_HCCHAR(chidx), regval); + + /* Set the request done state */ + + chan->result = OK; + } + } + + /* Check for a pending CHannel Halted (CHH) interrupt */ + + else if ((pending & OTG_HCINT_CHH) != 0) + { + /* Mask the CHannel Halted (CHH) interrupt */ + + regval = stm32_getreg(STM32_OTG_HCINTMSK(chidx)); + regval &= ~OTG_HCINT_CHH; + stm32_putreg(STM32_OTG_HCINTMSK(chidx), regval); + + /* Update the request state based on the host state machine state */ + + if (chan->chreason == CHREASON_XFRC) + { + /* Set the request done result */ + + chan->result = OK; + } + else if (chan->chreason == CHREASON_STALL) + { + /* Set the request stall result */ + + chan->result = EPERM; + } + else if ((chan->chreason == CHREASON_TXERR) || + (chan->chreason == CHREASON_DTERR)) + { + /* Set the request I/O error result */ + + chan->result = EIO; + } + else if (chan->chreason == CHREASON_NAK) + { + /* Halt on NAK only happens on an INTR channel. Fetch the HCCHAR register + * and check for an interrupt endpoint. + */ + + regval = stm32_getreg(STM32_OTG_HCCHAR(chidx)); + if ((regval & OTG_HCCHAR_EPTYP_MASK) == OTG_HCCHAR_EPTYP_INTR) + { + /* Toggle the IN data toggle (Used by Bulk and INTR only) */ + + chan->indata1 ^= true; + } + + /* Set the NAK error result */ + + chan->result = EAGAIN; + } + else /* if (chan->chreason == CHREASON_FRMOR) */ + { + /* Set the frame overrun error result */ + + chan->result = EPIPE; + } + + /* Clear the CHannel Halted (CHH) condition */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_CHH); + } + + /* Check for a pending Transaction ERror (TXERR) interrupt */ + + else if ((pending & OTG_HCINT_TXERR) != 0) + { + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_TXERR); + + /* Clear the Transaction ERror (TXERR) condition */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_TXERR); + } + + /* Check for a pending NAK response received (NAK) interrupt */ + + else if ((pending & OTG_HCINT_NAK) != 0) + { + /* For a BULK transfer, the hardware is capable of retrying + * automatically on a NAK. However, this is not always + * what we need to do. So we always halt the transfer and + * return control to high level logic in the event of a NAK. + */ + +#if 1 + /* Halt the interrupt channel */ + + if (chan->eptype == OTG_EPTYPE_INTR) + { + /* Halt the channel -- the CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_NAK); + } + + /* Re-activate CTRL and BULK channels. + * REVISIT: This can cause a lot of interrupts! + */ + + else if (chan->eptype == OTG_EPTYPE_CTRL || + chan->eptype == OTG_EPTYPE_BULK) + { + /* Re-activate the channel by clearing CHDIS and assuring that + * CHENA is set + */ + + regval = stm32_getreg(STM32_OTG_HCCHAR(chidx)); + regval |= OTG_HCCHAR_CHENA; + regval &= ~OTG_HCCHAR_CHDIS; + stm32_putreg(STM32_OTG_HCCHAR(chidx), regval); + } +#else + /* Halt all transfers on the NAK -- the CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_NAK); +#endif + + /* Clear the NAK condition */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_NAK); + } + + /* Check for a transfer complete event */ + + stm32_chan_wakeup(priv, chan); +} + +/**************************************************************************** + * Name: stm32_gint_hcoutisr + * + * Description: + * USB OTG FS host OUT channels interrupt handler + * + * One the completion of the transfer, the channel result byte may be set as + * follows: + * + * OK - Transfer completed successfully + * EAGAIN - If devices NAKs the transfer or NYET occurs + * EPERM - If the endpoint stalls + * EIO - On a TX or data toggle error + * EPIPE - Frame overrun + * + * EBUSY in the result field indicates that the transfer has not completed. + * + ****************************************************************************/ + +static inline void stm32_gint_hcoutisr(FAR struct stm32_usbhost_s *priv, + int chidx) +{ + FAR struct stm32_chan_s *chan = &priv->chan[chidx]; + uint32_t regval; + uint32_t pending; + + /* Read the HCINT register to get the pending HC interrupts. Read the + * HCINTMSK register to get the set of enabled HC interrupts. + */ + + pending = stm32_getreg(STM32_OTG_HCINT(chidx)); + regval = stm32_getreg(STM32_OTG_HCINTMSK(chidx)); + + /* AND the two to get the set of enabled, pending HC interrupts */ + + pending &= regval; + ullinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending); + + /* Check for a pending ACK response received/transmitted (ACK) interrupt */ + + if ((pending & OTG_HCINT_ACK) != 0) + { + /* Clear the pending the ACK response received/transmitted (ACK) interrupt */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_ACK); + } + + /* Check for a pending FRaMe OverRun (FRMOR) interrupt */ + + else if ((pending & OTG_HCINT_FRMOR) != 0) + { + /* Halt the channel (probably not necessary for FRMOR) */ + + stm32_chan_halt(priv, chidx, CHREASON_FRMOR); + + /* Clear the pending the FRaMe OverRun (FRMOR) interrupt */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_FRMOR); + } + + /* Check for a pending TransFeR Completed (XFRC) interrupt */ + + else if ((pending & OTG_HCINT_XFRC) != 0) + { + /* Decrement the number of bytes remaining by the number of + * bytes that were "in-flight". + */ + + priv->chan[chidx].buffer += priv->chan[chidx].inflight; + priv->chan[chidx].xfrd += priv->chan[chidx].inflight; + priv->chan[chidx].inflight = 0; + + /* Halt the channel -- the CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_XFRC); + + /* Clear the pending the TransFeR Completed (XFRC) interrupt */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_XFRC); + } + + /* Check for a pending STALL response receive (STALL) interrupt */ + + else if ((pending & OTG_HCINT_STALL) != 0) + { + /* Clear the pending the STALL response receiv (STALL) interrupt */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_STALL); + + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_STALL); + } + + /* Check for a pending NAK response received (NAK) interrupt */ + + else if ((pending & OTG_HCINT_NAK) != 0) + { + /* Halt the channel -- the CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_NAK); + + /* Clear the pending the NAK response received (NAK) interrupt */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_NAK); + } + + /* Check for a pending Transaction ERror (TXERR) interrupt */ + + else if ((pending & OTG_HCINT_TXERR) != 0) + { + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_TXERR); + + /* Clear the pending the Transaction ERror (TXERR) interrupt */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_TXERR); + } + + /* Check for a NYET interrupt */ + +#if 0 /* NYET is a reserved bit in the HCINT register */ + else if ((pending & OTG_HCINT_NYET) != 0) + { + /* Halt the channel */ + + stm32_chan_halt(priv, chidx, CHREASON_NYET); + + /* Clear the pending the NYET interrupt */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_NYET); + } +#endif + + /* Check for a pending Data Toggle ERRor (DTERR) interrupt */ + + else if (pending & OTG_HCINT_DTERR) + { + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_DTERR); + + /* Clear the pending the Data Toggle ERRor (DTERR) and NAK interrupts */ + + stm32_putreg(STM32_OTG_HCINT(chidx), (OTG_HCINT_DTERR | OTG_HCINT_NAK)); + } + + /* Check for a pending CHannel Halted (CHH) interrupt */ + + else if ((pending & OTG_HCINT_CHH) != 0) + { + /* Mask the CHannel Halted (CHH) interrupt */ + + regval = stm32_getreg(STM32_OTG_HCINTMSK(chidx)); + regval &= ~OTG_HCINT_CHH; + stm32_putreg(STM32_OTG_HCINTMSK(chidx), regval); + + if (chan->chreason == CHREASON_XFRC) + { + /* Set the request done result */ + + chan->result = OK; + + /* Read the HCCHAR register to get the HCCHAR register to get + * the endpoint type. + */ + + regval = stm32_getreg(STM32_OTG_HCCHAR(chidx)); + + /* Is it a bulk endpoint? Were an odd number of packets + * transferred? + */ + + if ((regval & OTG_HCCHAR_EPTYP_MASK) == OTG_HCCHAR_EPTYP_BULK && + (chan->npackets & 1) != 0) + { + /* Yes to both... toggle the data out PID */ + + chan->outdata1 ^= true; + } + } + else if (chan->chreason == CHREASON_NAK || + chan->chreason == CHREASON_NYET) + { + /* Set the try again later result */ + + chan->result = EAGAIN; + } + else if (chan->chreason == CHREASON_STALL) + { + /* Set the request stall result */ + + chan->result = EPERM; + } + else if ((chan->chreason == CHREASON_TXERR) || + (chan->chreason == CHREASON_DTERR)) + { + /* Set the I/O failure result */ + + chan->result = EIO; + } + else /* if (chan->chreason == CHREASON_FRMOR) */ + { + /* Set the frame error result */ + + chan->result = EPIPE; + } + + /* Clear the pending the CHannel Halted (CHH) interrupt */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_CHH); + } + + /* Check for a transfer complete event */ + + stm32_chan_wakeup(priv, chan); +} + +/**************************************************************************** + * Name: stm32_gint_connected + * + * Description: + * Handle a connection event. + * + ****************************************************************************/ + +static void stm32_gint_connected(FAR struct stm32_usbhost_s *priv) +{ + /* We we previously disconnected? */ + + if (!priv->connected) + { + /* Yes.. then now we are connected */ + + usbhost_vtrace1(OTG_VTRACE1_CONNECTED, 0); + priv->connected = true; + priv->change = true; + DEBUGASSERT(priv->smstate == SMSTATE_DETACHED); + + /* Notify any waiters */ + + priv->smstate = SMSTATE_ATTACHED; + if (priv->pscwait) + { + stm32_givesem(&priv->pscsem); + priv->pscwait = false; + } + } +} + +/**************************************************************************** + * Name: stm32_gint_disconnected + * + * Description: + * Handle a disconnection event. + * + ****************************************************************************/ + +static void stm32_gint_disconnected(FAR struct stm32_usbhost_s *priv) +{ + /* Were we previously connected? */ + + if (priv->connected) + { + /* Yes.. then we no longer connected */ + + usbhost_vtrace1(OTG_VTRACE1_DISCONNECTED, 0); + + /* Are we bound to a class driver? */ + + if (priv->rhport.hport.devclass) + { + /* Yes.. Disconnect the class driver */ + + CLASS_DISCONNECTED(priv->rhport.hport.devclass); + priv->rhport.hport.devclass = NULL; + } + + /* Re-Initialize Host for new Enumeration */ + + priv->smstate = SMSTATE_DETACHED; + priv->connected = false; + priv->change = true; + stm32_chan_freeall(priv); + + priv->rhport.hport.speed = USB_SPEED_FULL; + + /* Notify any waiters that there is a change in the connection state */ + + if (priv->pscwait) + { + stm32_givesem(&priv->pscsem); + priv->pscwait = false; + } + } +} + +/**************************************************************************** + * Name: stm32_gint_sofisr + * + * Description: + * USB OTG FS start-of-frame interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_OTG_SOFINTR +static inline void stm32_gint_sofisr(FAR struct stm32_usbhost_s *priv) +{ + /* Handle SOF interrupt */ +#warning "Do what?" + + /* Clear pending SOF interrupt */ + + stm32_putreg(STM32_OTG_GINTSTS, OTG_GINT_SOF); +} +#endif + +/**************************************************************************** + * Name: stm32_gint_rxflvlisr + * + * Description: + * USB OTG FS RxFIFO non-empty interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_rxflvlisr(FAR struct stm32_usbhost_s *priv) +{ + FAR uint32_t *dest; + uint32_t grxsts; + uint32_t intmsk; + uint32_t hcchar; + uint32_t hctsiz; + uint32_t fifo; + int bcnt; + int bcnt32; + int chidx; + int i; + + /* Disable the RxFIFO non-empty interrupt */ + + intmsk = stm32_getreg(STM32_OTG_GINTMSK); + intmsk &= ~OTG_GINT_RXFLVL; + stm32_putreg(STM32_OTG_GINTMSK, intmsk); + + /* Read and pop the next status from the Rx FIFO */ + + grxsts = stm32_getreg(STM32_OTG_GRXSTSP); + ullinfo("GRXSTS: %08x\n", grxsts); + + /* Isolate the channel number/index in the status word */ + + chidx = (grxsts & OTG_GRXSTSH_CHNUM_MASK) >> OTG_GRXSTSH_CHNUM_SHIFT; + + /* Get the host channel characteristics register (HCCHAR) for this channel */ + + hcchar = stm32_getreg(STM32_OTG_HCCHAR(chidx)); + + /* Then process the interrupt according to the packet status */ + + switch (grxsts & OTG_GRXSTSH_PKTSTS_MASK) + { + case OTG_GRXSTSH_PKTSTS_INRECVD: /* IN data packet received */ + { + /* Read the data into the host buffer. */ + + bcnt = (grxsts & OTG_GRXSTSH_BCNT_MASK) >> OTG_GRXSTSH_BCNT_SHIFT; + if (bcnt > 0 && priv->chan[chidx].buffer != NULL) + { + /* Transfer the packet from the Rx FIFO into the user buffer */ + + dest = (FAR uint32_t *)priv->chan[chidx].buffer; + fifo = STM32_OTG_DFIFO_HCH(0); + bcnt32 = (bcnt + 3) >> 2; + + for (i = 0; i < bcnt32; i++) + { + *dest++ = stm32_getreg(fifo); + } + + stm32_pktdump("Received", priv->chan[chidx].buffer, bcnt); + + /* Toggle the IN data pid (Used by Bulk and INTR only) */ + + priv->chan[chidx].indata1 ^= true; + + /* Manage multiple packet transfers */ + + priv->chan[chidx].buffer += bcnt; + priv->chan[chidx].xfrd += bcnt; + + /* Check if more packets are expected */ + + hctsiz = stm32_getreg(STM32_OTG_HCTSIZ(chidx)); + if ((hctsiz & OTG_HCTSIZ_PKTCNT_MASK) != 0) + { + /* Re-activate the channel when more packets are expected */ + + hcchar |= OTG_HCCHAR_CHENA; + hcchar &= ~OTG_HCCHAR_CHDIS; + stm32_putreg(STM32_OTG_HCCHAR(chidx), hcchar); + } + } + } + break; + + case OTG_GRXSTSH_PKTSTS_INDONE: /* IN transfer completed */ + case OTG_GRXSTSH_PKTSTS_DTOGERR: /* Data toggle error */ + case OTG_GRXSTSH_PKTSTS_HALTED: /* Channel halted */ + default: + break; + } + + /* Re-enable the RxFIFO non-empty interrupt */ + + intmsk |= OTG_GINT_RXFLVL; + stm32_putreg(STM32_OTG_GINTMSK, intmsk); +} + +/**************************************************************************** + * Name: stm32_gint_nptxfeisr + * + * Description: + * USB OTG FS non-periodic TxFIFO empty interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_nptxfeisr(FAR struct stm32_usbhost_s *priv) +{ + FAR struct stm32_chan_s *chan; + uint32_t regval; + unsigned int wrsize; + unsigned int avail; + unsigned int chidx; + + /* Recover the index of the channel that is waiting for space in the Tx + * FIFO. + */ + + chidx = priv->chidx; + chan = &priv->chan[chidx]; + + /* Reduce the buffer size by the number of bytes that were previously placed + * in the Tx FIFO. + */ + + chan->buffer += chan->inflight; + chan->xfrd += chan->inflight; + chan->inflight = 0; + + /* If we have now transferred the entire buffer, then this transfer is + * complete (this case really should never happen because we disable + * the NPTXFE interrupt on the final packet). + */ + + if (chan->xfrd >= chan->buflen) + { + /* Disable further Tx FIFO empty interrupts and bail. */ + + stm32_modifyreg(STM32_OTG_GINTMSK, OTG_GINT_NPTXFE, 0); + return; + } + + /* Read the status from the top of the non-periodic TxFIFO */ + + regval = stm32_getreg(STM32_OTG_HNPTXSTS); + + /* Extract the number of bytes available in the non-periodic Tx FIFO. */ + + avail = ((regval & OTG_HNPTXSTS_NPTXFSAV_MASK) >> OTG_HNPTXSTS_NPTXFSAV_SHIFT) << 2; + + /* Get the size to put in the Tx FIFO now */ + + wrsize = chan->buflen - chan->xfrd; + + /* Get minimal size packet that can be sent. Something is seriously + * configured wrong if one packet will not fit into the empty Tx FIFO. + */ + + DEBUGASSERT(wrsize > 0 && avail >= MIN(wrsize, chan->maxpacket)); + if (wrsize > avail) + { + /* Clip the write size to the number of full, max sized packets + * that will fit in the Tx FIFO. + */ + + unsigned int wrpackets = avail / chan->maxpacket; + wrsize = wrpackets * chan->maxpacket; + } + + /* Otherwise, this will be the last packet to be sent in this transaction. + * We now need to disable further NPTXFE interrupts. + */ + + else + { + stm32_modifyreg(STM32_OTG_GINTMSK, OTG_GINT_NPTXFE, 0); + } + + /* Write the next group of packets into the Tx FIFO */ + + ullinfo("HNPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n", + regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); + + stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); +} + +/**************************************************************************** + * Name: stm32_gint_ptxfeisr + * + * Description: + * USB OTG FS periodic TxFIFO empty interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_ptxfeisr(FAR struct stm32_usbhost_s *priv) +{ + FAR struct stm32_chan_s *chan; + uint32_t regval; + unsigned int wrsize; + unsigned int avail; + unsigned int chidx; + + /* Recover the index of the channel that is waiting for space in the Tx + * FIFO. + */ + + chidx = priv->chidx; + chan = &priv->chan[chidx]; + + /* Reduce the buffer size by the number of bytes that were previously placed + * in the Tx FIFO. + */ + + chan->buffer += chan->inflight; + chan->xfrd += chan->inflight; + chan->inflight = 0; + + /* If we have now transfered the entire buffer, then this transfer is + * complete (this case really should never happen because we disable + * the PTXFE interrupt on the final packet). + */ + + if (chan->xfrd >= chan->buflen) + { + /* Disable further Tx FIFO empty interrupts and bail. */ + + stm32_modifyreg(STM32_OTG_GINTMSK, OTG_GINT_PTXFE, 0); + return; + } + + /* Read the status from the top of the periodic TxFIFO */ + + regval = stm32_getreg(STM32_OTG_HPTXSTS); + + /* Extract the number of bytes available in the periodic Tx FIFO. */ + + avail = ((regval & OTG_HPTXSTS_PTXFSAVL_MASK) >> OTG_HPTXSTS_PTXFSAVL_SHIFT) << 2; + + /* Get the size to put in the Tx FIFO now */ + + wrsize = chan->buflen - chan->xfrd; + + /* Get minimal size packet that can be sent. Something is seriously + * configured wrong if one packet will not fit into the empty Tx FIFO. + */ + + DEBUGASSERT(wrsize && avail >= MIN(wrsize, chan->maxpacket)); + if (wrsize > avail) + { + /* Clip the write size to the number of full, max sized packets + * that will fit in the Tx FIFO. + */ + + unsigned int wrpackets = avail / chan->maxpacket; + wrsize = wrpackets * chan->maxpacket; + } + + /* Otherwise, this will be the last packet to be sent in this transaction. + * We now need to disable further PTXFE interrupts. + */ + + else + { + stm32_modifyreg(STM32_OTG_GINTMSK, OTG_GINT_PTXFE, 0); + } + + /* Write the next group of packets into the Tx FIFO */ + + ullinfo("HPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n", + regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); + + stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); +} + +/**************************************************************************** + * Name: stm32_gint_hcisr + * + * Description: + * USB OTG FS host channels interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_hcisr(FAR struct stm32_usbhost_s *priv) +{ + uint32_t haint; + uint32_t hcchar; + int i = 0; + + /* Read the Host all channels interrupt register and test each bit in the + * register. Each bit i, i=0...(STM32_NHOST_CHANNELS-1), corresponds to + * a pending interrupt on channel i. + */ + + haint = stm32_getreg(STM32_OTG_HAINT); + for (i = 0; i < STM32_NHOST_CHANNELS; i++) + { + /* Is an interrupt pending on this channel? */ + + if ((haint & OTG_HAINT(i)) != 0) + { + /* Yes... read the HCCHAR register to get the direction bit */ + + hcchar = stm32_getreg(STM32_OTG_HCCHAR(i)); + + /* Was this an interrupt on an IN or an OUT channel? */ + + if ((hcchar & OTG_HCCHAR_EPDIR) != 0) + { + /* Handle the HC IN channel interrupt */ + + stm32_gint_hcinisr(priv, i); + } + else + { + /* Handle the HC OUT channel interrupt */ + + stm32_gint_hcoutisr(priv, i); + } + } + } +} + +/**************************************************************************** + * Name: stm32_gint_hprtisr + * + * Description: + * USB OTG FS host port interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_hprtisr(FAR struct stm32_usbhost_s *priv) +{ + uint32_t hprt; + uint32_t newhprt; + uint32_t hcfg; + + usbhost_vtrace1(OTG_VTRACE1_GINT_HPRT, 0); + /* Read the port status and control register (HPRT) */ + + hprt = stm32_getreg(STM32_OTG_HPRT); + + /* Setup to clear the interrupt bits in GINTSTS by setting the corresponding + * bits in the HPRT. The HCINT interrupt bit is cleared when the appropriate + * status bits in the HPRT register are cleared. + */ + + newhprt = hprt & ~(OTG_HPRT_PENA | OTG_HPRT_PCDET | + OTG_HPRT_PENCHNG | OTG_HPRT_POCCHNG); + + /* Check for Port Overcurrent CHaNGe (POCCHNG) */ + + if ((hprt & OTG_HPRT_POCCHNG) != 0) + { + /* Set up to clear the POCCHNG status in the new HPRT contents. */ + + usbhost_vtrace1(OTG_VTRACE1_GINT_HPRT_POCCHNG, 0); + newhprt |= OTG_HPRT_POCCHNG; + } + + /* Check for Port Connect DETected (PCDET). The core sets this bit when a + * device connection is detected. + */ + + if ((hprt & OTG_HPRT_PCDET) != 0) + { + /* Set up to clear the PCDET status in the new HPRT contents. Then + * process the new connection event. + */ + + usbhost_vtrace1(OTG_VTRACE1_GINT_HPRT_PCDET, 0); + newhprt |= OTG_HPRT_PCDET; + stm32_portreset(priv); + stm32_gint_connected(priv); + } + + /* Check for Port Enable CHaNGed (PENCHNG) */ + + if ((hprt & OTG_HPRT_PENCHNG) != 0) + { + /* Set up to clear the PENCHNG status in the new HPRT contents. */ + + usbhost_vtrace1(OTG_VTRACE1_GINT_HPRT_PENCHNG, 0); + newhprt |= OTG_HPRT_PENCHNG; + + /* Was the port enabled? */ + + if ((hprt & OTG_HPRT_PENA) != 0) + { + /* Yes.. handle the new connection event */ + + stm32_gint_connected(priv); + + /* Check the Host ConFiGuration register (HCFG) */ + + hcfg = stm32_getreg(STM32_OTG_HCFG); + + /* Is this a low speed or full speed connection (OTG FS does not + * support high speed) + */ + + if ((hprt & OTG_HPRT_PSPD_MASK) == OTG_HPRT_PSPD_LS) + { + /* Set the Host Frame Interval Register for the 6KHz speed */ + + usbhost_vtrace1(OTG_VTRACE1_GINT_HPRT_LSDEV, 0); + stm32_putreg(STM32_OTG_HFIR, 6000); + + /* Are we switching from FS to LS? */ + + if ((hcfg & OTG_HCFG_FSLSPCS_MASK) != OTG_HCFG_FSLSPCS_LS6MHz) + { + usbhost_vtrace1(OTG_VTRACE1_GINT_HPRT_FSLSSW, 0); + + /* Yes... configure for LS */ + + hcfg &= ~OTG_HCFG_FSLSPCS_MASK; + hcfg |= OTG_HCFG_FSLSPCS_LS6MHz; + stm32_putreg(STM32_OTG_HCFG, hcfg); + + /* And reset the port */ + + stm32_portreset(priv); + } + } + else /* if ((hprt & OTG_HPRT_PSPD_MASK) == OTG_HPRT_PSPD_FS) */ + { + + usbhost_vtrace1(OTG_VTRACE1_GINT_HPRT_FSDEV, 0); + stm32_putreg(STM32_OTG_HFIR, 48000); + + /* Are we switching from LS to FS? */ + + if ((hcfg & OTG_HCFG_FSLSPCS_MASK) != OTG_HCFG_FSLSPCS_FS48MHz) + { + + usbhost_vtrace1(OTG_VTRACE1_GINT_HPRT_LSFSSW, 0); + /* Yes... configure for FS */ + + hcfg &= ~OTG_HCFG_FSLSPCS_MASK; + hcfg |= OTG_HCFG_FSLSPCS_FS48MHz; + stm32_putreg(STM32_OTG_HCFG, hcfg); + + /* And reset the port */ + + stm32_portreset(priv); + } + } + } + } + + /* Clear port interrupts by setting bits in the HPRT */ + + stm32_putreg(STM32_OTG_HPRT, newhprt); +} + +/**************************************************************************** + * Name: stm32_gint_discisr + * + * Description: + * USB OTG FS disconnect detected interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_discisr(FAR struct stm32_usbhost_s *priv) +{ + /* Handle the disconnection event */ + + stm32_gint_disconnected(priv); + + /* Clear the dicsonnect interrupt */ + + stm32_putreg(STM32_OTG_GINTSTS, OTG_GINT_DISC); +} + +/**************************************************************************** + * Name: stm32_gint_ipxfrisr + * + * Description: + * USB OTG FS incomplete periodic interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_ipxfrisr(FAR struct stm32_usbhost_s *priv) +{ + uint32_t regval; + + /* CHENA : Set to enable the channel + * CHDIS : Set to stop transmitting/receiving data on a channel + */ + + regval = stm32_getreg(STM32_OTG_HCCHAR(0)); + regval |= (OTG_HCCHAR_CHDIS | OTG_HCCHAR_CHENA); + stm32_putreg(STM32_OTG_HCCHAR(0), regval); + + /* Clear the incomplete isochronous OUT interrupt */ + + stm32_putreg(STM32_OTG_GINTSTS, OTG_GINT_IPXFR); +} + +/**************************************************************************** + * Name: stm32_gint_isr + * + * Description: + * USB OTG FS global interrupt handler + * + ****************************************************************************/ + +static int stm32_gint_isr(int irq, FAR void *context) +{ + /* At present, there is only support for a single OTG FS host. Hence it is + * pre-allocated as g_usbhost. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple devices. + */ + + FAR struct stm32_usbhost_s *priv = &g_usbhost; + uint32_t pending; + + /* If OTG were supported, we would need to check if we are in host or + * device mode when the global interrupt occurs. Here we support only + * host mode + */ + + /* Loop while there are pending interrupts to process. This loop may save a + * little interrupt handling overhead. + */ + + for (; ; ) + { + /* Get the unmasked bits in the GINT status */ + + pending = stm32_getreg(STM32_OTG_GINTSTS); + pending &= stm32_getreg(STM32_OTG_GINTMSK); + + /* Return from the interrupt when there are no further pending + * interrupts. + */ + + if (pending == 0) + { + return OK; + } + + /* Otherwise, process each pending, unmasked GINT interrupts */ + + /* Handle the start of frame interrupt */ + +#ifdef CONFIG_STM32_OTG_SOFINTR + if ((pending & OTG_GINT_SOF) != 0) + { + usbhost_vtrace1(OTG_VTRACE1_GINT_SOF, 0); + stm32_gint_sofisr(priv); + } +#endif + + /* Handle the RxFIFO non-empty interrupt */ + + if ((pending & OTG_GINT_RXFLVL) != 0) + { + usbhost_vtrace1(OTG_VTRACE1_GINT_RXFLVL, 0); + stm32_gint_rxflvlisr(priv); + } + + /* Handle the non-periodic TxFIFO empty interrupt */ + + if ((pending & OTG_GINT_NPTXFE) != 0) + { + usbhost_vtrace1(OTG_VTRACE1_GINT_NPTXFE, 0); + stm32_gint_nptxfeisr(priv); + } + + /* Handle the periodic TxFIFO empty interrupt */ + + if ((pending & OTG_GINT_PTXFE) != 0) + { + usbhost_vtrace1(OTG_VTRACE1_GINT_PTXFE, 0); + stm32_gint_ptxfeisr(priv); + } + + /* Handle the host channels interrupt */ + + if ((pending & OTG_GINT_HC) != 0) + { + usbhost_vtrace1(OTG_VTRACE1_GINT_HC, 0); + stm32_gint_hcisr(priv); + } + + /* Handle the host port interrupt */ + + if ((pending & OTG_GINT_HPRT) != 0) + { + stm32_gint_hprtisr(priv); + } + + /* Handle the disconnect detected interrupt */ + + if ((pending & OTG_GINT_DISC) != 0) + { + usbhost_vtrace1(OTG_VTRACE1_GINT_DISC, 0); + stm32_gint_discisr(priv); + } + + /* Handle the incomplete periodic transfer */ + + if ((pending & OTG_GINT_IPXFR) != 0) + { + usbhost_vtrace1(OTG_VTRACE1_GINT_IPXFR, 0); + stm32_gint_ipxfrisr(priv); + } + } + + /* We won't get here */ + + return OK; +} + +/**************************************************************************** + * Name: stm32_gint_enable and stm32_gint_disable + * + * Description: + * Respectively enable or disable the global OTG FS interrupt. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_gint_enable(void) +{ + uint32_t regval; + + /* Set the GINTMSK bit to unmask the interrupt */ + + regval = stm32_getreg(STM32_OTG_GAHBCFG); + regval |= OTG_GAHBCFG_GINTMSK; + stm32_putreg(STM32_OTG_GAHBCFG, regval); +} + +static void stm32_gint_disable(void) +{ + uint32_t regval; + + /* Clear the GINTMSK bit to mask the interrupt */ + + regval = stm32_getreg(STM32_OTG_GAHBCFG); + regval &= ~OTG_GAHBCFG_GINTMSK; + stm32_putreg(STM32_OTG_GAHBCFG, regval); +} + +/**************************************************************************** + * Name: stm32_hostinit_enable + * + * Description: + * Enable host interrupts. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void stm32_hostinit_enable(void) +{ + uint32_t regval; + + /* Disable all interrupts. */ + + stm32_putreg(STM32_OTG_GINTMSK, 0); + + /* Clear any pending interrupts. */ + + stm32_putreg(STM32_OTG_GINTSTS, 0xffffffff); + + /* Clear any pending USB OTG Interrupts (should be done elsewhere if OTG is supported) */ + + stm32_putreg(STM32_OTG_GOTGINT, 0xffffffff); + + /* Clear any pending USB OTG interrupts */ + + stm32_putreg(STM32_OTG_GINTSTS, 0xbfffffff); + + /* Enable the host interrupts */ + /* Common interrupts: + * + * OTG_GINT_WKUP : Resume/remote wakeup detected interrupt + * OTG_GINT_USBSUSP : USB suspend + */ + + regval = (OTG_GINT_WKUP | OTG_GINT_USBSUSP); + + /* If OTG were supported, we would need to enable the following as well: + * + * OTG_GINT_OTG : OTG interrupt + * OTG_GINT_SRQ : Session request/new session detected interrupt + * OTG_GINT_CIDSCHG : Connector ID status change + */ + + /* Host-specific interrupts + * + * OTG_GINT_SOF : Start of frame + * OTG_GINT_RXFLVL : RxFIFO non-empty + * OTG_GINT_IISOOXFR : Incomplete isochronous OUT transfer + * OTG_GINT_HPRT : Host port interrupt + * OTG_GINT_HC : Host channels interrupt + * OTG_GINT_DISC : Disconnect detected interrupt + */ + +#ifdef CONFIG_STM32_OTG_SOFINTR + regval |= (OTG_GINT_SOF | OTG_GINT_RXFLVL | OTG_GINT_IISOOXFR | + OTG_GINT_HPRT | OTG_GINT_HC | OTG_GINT_DISC); +#else + regval |= (OTG_GINT_RXFLVL | OTG_GINT_IPXFR | OTG_GINT_HPRT | + OTG_GINT_HC | OTG_GINT_DISC); +#endif + stm32_putreg(STM32_OTG_GINTMSK, regval); +} + +/**************************************************************************** + * Name: stm32_txfe_enable + * + * Description: + * Enable Tx FIFO empty interrupts. This is necessary when the entire + * transfer will not fit into Tx FIFO. The transfer will then be completed + * when the Tx FIFO is empty. NOTE: The Tx FIFO interrupt is disabled + * the fifo empty interrupt handler when the transfer is complete. + * + * Input Parameters: + * priv - Driver state structure reference + * chidx - The channel that requires the Tx FIFO empty interrupt + * + * Returned Value: + * None + * + * Assumptions: + * Called from user task context. Interrupts must be disabled to assure + * exclusive access to the GINTMSK register. + * + ****************************************************************************/ + +static void stm32_txfe_enable(FAR struct stm32_usbhost_s *priv, int chidx) +{ + FAR struct stm32_chan_s *chan = &priv->chan[chidx]; + irqstate_t flags; + uint32_t regval; + + /* Disable all interrupts so that we have exclusive access to the GINTMSK + * (it would be sufficent just to disable the GINT interrupt). + */ + + flags = enter_critical_section(); + + /* Should we enable the periodic or non-peridic Tx FIFO empty interrupts */ + + regval = stm32_getreg(STM32_OTG_GINTMSK); + switch (chan->eptype) + { + default: + case OTG_EPTYPE_CTRL: /* Non periodic transfer */ + case OTG_EPTYPE_BULK: + regval |= OTG_GINT_NPTXFE; + break; + + case OTG_EPTYPE_INTR: /* Periodic transfer */ + case OTG_EPTYPE_ISOC: + regval |= OTG_GINT_PTXFE; + break; + } + + /* Enable interrupts */ + + stm32_putreg(STM32_OTG_GINTMSK, regval); + leave_critical_section(flags); +} + +/**************************************************************************** + * USB Host Controller Operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_wait + * + * Description: + * Wait for a device to be connected or disconnected to/from a hub port. + * + * Input Parameters: + * conn - The USB host connection instance obtained as a parameter from the call to + * the USB driver initialization logic. + * hport - The location to return the hub port descriptor that detected the + * connection related event. + * + * Returned Values: + * Zero (OK) is returned on success when a device in connected or + * disconnected. This function will not return until either (1) a device is + * connected or disconnect to/from any hub port or until (2) some failure + * occurs. On a failure, a negated errno value is returned indicating the + * nature of the failure + * + * Assumptions: + * - Called from a single thread so no mutual exclusion is required. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_wait(FAR struct usbhost_connection_s *conn, + FAR struct usbhost_hubport_s **hport) +{ + FAR struct stm32_usbhost_s *priv = &g_usbhost; + struct usbhost_hubport_s *connport; + irqstate_t flags; + + /* Loop until a change in connection state is detected */ + + flags = enter_critical_section(); + for (; ; ) + { + /* Is there a change in the connection state of the single root hub + * port? + */ + + if (priv->change) + { + connport = &priv->rhport.hport; + + /* Yes. Remember the new state */ + + connport->connected = priv->connected; + priv->change = false; + + /* And return the root hub port */ + + *hport = connport; + leave_critical_section(flags); + + uinfo("RHport Connected: %s\n", connport->connected ? "YES" : "NO"); + return OK; + } + +#ifdef CONFIG_USBHOST_HUB + /* Is a device connected to an external hub? */ + + if (priv->hport) + { + /* Yes.. return the external hub port */ + + connport = (struct usbhost_hubport_s *)priv->hport; + priv->hport = NULL; + + *hport = connport; + leave_critical_section(flags); + + uinfo("Hub port Connected: %s\n", connport->connected ? "YES" : "NO"); + return OK; + } +#endif + + /* Wait for the next connection event */ + + priv->pscwait = true; + stm32_takesem(&priv->pscsem); + } +} + +/**************************************************************************** + * Name: stm32_enumerate + * + * Description: + * Enumerate the connected device. As part of this enumeration process, + * the driver will (1) get the device's configuration descriptor, (2) + * extract the class ID info from the configuration descriptor, (3) call + * usbhost_findclass() to find the class that supports this device, (4) + * call the create() method on the struct usbhost_registry_s interface + * to get a class instance, and finally (5) call the connect() method + * of the struct usbhost_class_s interface. After that, the class is in + * charge of the sequence of operations. + * + * Input Parameters: + * conn - The USB host connection instance obtained as a parameter from + * the call to the USB driver initialization logic. + * hport - The descriptor of the hub port that has the newly connected + * device. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_rh_enumerate(FAR struct stm32_usbhost_s *priv, + FAR struct usbhost_connection_s *conn, + FAR struct usbhost_hubport_s *hport) +{ + uint32_t regval; + int ret; + + DEBUGASSERT(conn != NULL && hport != NULL && hport->port == 0); + + /* Are we connected to a device? The caller should have called the wait() + * method first to be assured that a device is connected. + */ + + while (!priv->connected) + { + /* No, return an error */ + + usbhost_trace1(OTG_TRACE1_DEVDISCONN, 0); + return -ENODEV; + } + + DEBUGASSERT(priv->smstate == SMSTATE_ATTACHED); + + /* USB 2.0 spec says at least 50ms delay before port reset. We wait 100ms. */ + + usleep(100*1000); + + /* Reset the host port */ + + stm32_portreset(priv); + + /* Get the current device speed */ + + regval = stm32_getreg(STM32_OTG_HPRT); + if ((regval & OTG_HPRT_PSPD_MASK) == OTG_HPRT_PSPD_LS) + { + priv->rhport.hport.speed = USB_SPEED_LOW; + } + else + { + priv->rhport.hport.speed = USB_SPEED_FULL; + } + + /* Allocate and initialize the root hub port EP0 channels */ + + ret = stm32_ctrlchan_alloc(priv, 0, 0, priv->rhport.hport.speed, &priv->ep0); + if (ret < 0) + { + uerr("ERROR: Failed to allocate a control endpoint: %d\n", ret); + } + + return ret; +} + +static int stm32_enumerate(FAR struct usbhost_connection_s *conn, + FAR struct usbhost_hubport_s *hport) +{ + FAR struct stm32_usbhost_s *priv = &g_usbhost; + int ret; + + DEBUGASSERT(hport); + + /* If this is a connection on the root hub, then we need to go to + * little more effort to get the device speed. If it is a connection + * on an external hub, then we already have that information. + */ + +#ifdef CONFIG_USBHOST_HUB + if (ROOTHUB(hport)) +#endif + { + ret = stm32_rh_enumerate(priv, conn, hport); + if (ret < 0) + { + return ret; + } + } + + /* Then let the common usbhost_enumerate do the real enumeration. */ + + uinfo("Enumerate the device\n"); + priv->smstate = SMSTATE_ENUM; + ret = usbhost_enumerate(hport, &hport->devclass); + + /* The enumeration may fail either because of some HCD interfaces failure + * or because the device class is not supported. In either case, we just + * need to perform the disconnection operation and make ready for a new + * enumeration. + */ + + if (ret < 0) + { + /* Return to the disconnected state */ + + uerr("ERROR: Enumeration failed: %d\n", ret); + stm32_gint_disconnected(priv); + } + + return ret; +} + +/************************************************************************************ + * Name: stm32_ep0configure + * + * Description: + * Configure endpoint 0. This method is normally used internally by the + * enumerate() method but is made available at the interface to support an + * external implementation of the enumeration logic. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * ep0 - The (opaque) EP0 endpoint instance + * funcaddr - The USB address of the function containing the endpoint that EP0 + * controls + * speed - The speed of the port USB_SPEED_LOW, _FULL, or _HIGH + * maxpacketsize - The maximum number of bytes that can be sent to or + * received from the endpoint in a single data packet + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ************************************************************************************/ + +static int stm32_ep0configure(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0, + uint8_t funcaddr, uint8_t speed, + uint16_t maxpacketsize) +{ + FAR struct stm32_usbhost_s *priv = (FAR struct stm32_usbhost_s *)drvr; + FAR struct stm32_ctrlinfo_s *ep0info = (FAR struct stm32_ctrlinfo_s *)ep0; + FAR struct stm32_chan_s *chan; + + DEBUGASSERT(drvr != NULL && ep0info != NULL && funcaddr < 128 && + maxpacketsize <= 64); + + /* We must have exclusive access to the USB host hardware and state structures */ + + stm32_takesem(&priv->exclsem); + + /* Configure the EP0 OUT channel */ + + chan = &priv->chan[ep0info->outndx]; + chan->funcaddr = funcaddr; + chan->speed = speed; + chan->maxpacket = maxpacketsize; + + stm32_chan_configure(priv, ep0info->outndx); + + /* Configure the EP0 IN channel */ + + chan = &priv->chan[ep0info->inndx]; + chan->funcaddr = funcaddr; + chan->speed = speed; + chan->maxpacket = maxpacketsize; + + stm32_chan_configure(priv, ep0info->inndx); + + stm32_givesem(&priv->exclsem); + return OK; +} + +/************************************************************************************ + * Name: stm32_epalloc + * + * Description: + * Allocate and configure one endpoint. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * epdesc - Describes the endpoint to be allocated. + * ep - A memory location provided by the caller in which to receive the + * allocated endpoint descriptor. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ************************************************************************************/ + +static int stm32_epalloc(FAR struct usbhost_driver_s *drvr, + FAR const struct usbhost_epdesc_s *epdesc, + FAR usbhost_ep_t *ep) +{ + FAR struct stm32_usbhost_s *priv = (FAR struct stm32_usbhost_s *)drvr; + int ret; + + /* Sanity check. NOTE that this method should only be called if a device is + * connected (because we need a valid low speed indication). + */ + + DEBUGASSERT(drvr != 0 && epdesc != NULL && ep != NULL); + + /* We must have exclusive access to the USB host hardware and state structures */ + + stm32_takesem(&priv->exclsem); + + /* Handler control pipes differently from other endpoint types. This is + * because the normal, "transfer" endpoints are unidirectional an require + * only a single channel. Control endpoints, however, are bi-diretional + * and require two channels, one for the IN and one for the OUT direction. + */ + + if (epdesc->xfrtype == OTG_EPTYPE_CTRL) + { + ret = stm32_ctrlep_alloc(priv, epdesc, ep); + } + else + { + ret = stm32_xfrep_alloc(priv, epdesc, ep); + } + + stm32_givesem(&priv->exclsem); + return ret; +} + +/************************************************************************************ + * Name: stm32_epfree + * + * Description: + * Free and endpoint previously allocated by DRVR_EPALLOC. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * ep - The endpoint to be freed. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ************************************************************************************/ + +static int stm32_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) +{ + FAR struct stm32_usbhost_s *priv = (FAR struct stm32_usbhost_s *)drvr; + + DEBUGASSERT(priv); + + /* We must have exclusive access to the USB host hardware and state structures */ + + stm32_takesem(&priv->exclsem); + + /* A single channel is represent by an index in the range of 0 to STM32_MAX_TX_FIFOS. + * Otherwise, the ep must be a pointer to an allocated control endpoint structure. + */ + + if ((uintptr_t)ep < STM32_MAX_TX_FIFOS) + { + /* Halt the channel and mark the channel available */ + + stm32_chan_free(priv, (int)ep); + } + else + { + /* Halt both control channel and mark the channels available */ + + FAR struct stm32_ctrlinfo_s *ctrlep = (FAR struct stm32_ctrlinfo_s *)ep; + stm32_chan_free(priv, ctrlep->inndx); + stm32_chan_free(priv, ctrlep->outndx); + + /* And free the control endpoint container */ + + kmm_free(ctrlep); + } + + stm32_givesem(&priv->exclsem); + return OK; +} + +/**************************************************************************** + * Name: stm32_alloc + * + * Description: + * Some hardware supports special memory in which request and descriptor data can + * be accessed more efficiently. This method provides a mechanism to allocate + * the request/descriptor memory. If the underlying hardware does not support + * such "special" memory, this functions may simply map to kmm_malloc. + * + * This interface was optimized under a particular assumption. It was assumed + * that the driver maintains a pool of small, pre-allocated buffers for descriptor + * traffic. NOTE that size is not an input, but an output: The size of the + * pre-allocated buffer is returned. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * buffer - The address of a memory location provided by the caller in which to + * return the allocated buffer memory address. + * maxlen - The address of a memory location provided by the caller in which to + * return the maximum size of the allocated buffer memory. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * - Called from a single thread so no mutual exclusion is required. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_alloc(FAR struct usbhost_driver_s *drvr, + FAR uint8_t **buffer, FAR size_t *maxlen) +{ + FAR uint8_t *alloc; + + DEBUGASSERT(drvr && buffer && maxlen); + + /* There is no special memory requirement for the STM32. */ + + alloc = (FAR uint8_t *)kmm_malloc(CONFIG_STM32_OTG_DESCSIZE); + if (!alloc) + { + return -ENOMEM; + } + + /* Return the allocated address and size of the descriptor buffer */ + + *buffer = alloc; + *maxlen = CONFIG_STM32_OTG_DESCSIZE; + return OK; +} + +/**************************************************************************** + * Name: stm32_free + * + * Description: + * Some hardware supports special memory in which request and descriptor data can + * be accessed more efficiently. This method provides a mechanism to free that + * request/descriptor memory. If the underlying hardware does not support + * such "special" memory, this functions may simply map to kmm_free(). + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * buffer - The address of the allocated buffer memory to be freed. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_free(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer) +{ + /* There is no special memory requirement */ + + DEBUGASSERT(drvr && buffer); + kmm_free(buffer); + return OK; +} + +/************************************************************************************ + * Name: stm32_ioalloc + * + * Description: + * Some hardware supports special memory in which larger IO buffers can + * be accessed more efficiently. This method provides a mechanism to allocate + * the request/descriptor memory. If the underlying hardware does not support + * such "special" memory, this functions may simply map to kmm_malloc. + * + * This interface differs from DRVR_ALLOC in that the buffers are variable-sized. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * buffer - The address of a memory location provided by the caller in which to + * return the allocated buffer memory address. + * buflen - The size of the buffer required. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ************************************************************************************/ + +static int stm32_ioalloc(FAR struct usbhost_driver_s *drvr, + FAR uint8_t **buffer, size_t buflen) +{ + FAR uint8_t *alloc; + + DEBUGASSERT(drvr && buffer && buflen > 0); + + /* There is no special memory requirement */ + + alloc = (FAR uint8_t *)kmm_malloc(buflen); + if (!alloc) + { + return -ENOMEM; + } + + /* Return the allocated buffer */ + + *buffer = alloc; + return OK; +} + +/************************************************************************************ + * Name: stm32_iofree + * + * Description: + * Some hardware supports special memory in which IO data can be accessed more + * efficiently. This method provides a mechanism to free that IO buffer + * memory. If the underlying hardware does not support such "special" memory, + * this functions may simply map to kmm_free(). + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * buffer - The address of the allocated buffer memory to be freed. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ************************************************************************************/ + +static int stm32_iofree(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer) +{ + /* There is no special memory requirement */ + + DEBUGASSERT(drvr && buffer); + kmm_free(buffer); + return OK; +} + +/**************************************************************************** + * Name: stm32_ctrlin and stm32_ctrlout + * + * Description: + * Process a IN or OUT request on the control endpoint. These methods + * will enqueue the request and wait for it to complete. Only one transfer may be + * queued; Neither these methods nor the transfer() method can be called again + * until the control transfer functions returns. + * + * These are blocking methods; these functions will not return until the + * control transfer has completed. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * ep0 - The control endpoint to send/receive the control request. + * req - Describes the request to be sent. This request must lie in memory + * created by DRVR_ALLOC. + * buffer - A buffer used for sending the request and for returning any + * responses. This buffer must be large enough to hold the length value + * in the request description. buffer must have been allocated using DRVR_ALLOC. + * + * NOTE: On an IN transaction, req and buffer may refer to the same allocated + * memory. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * - Called from a single thread so no mutual exclusion is required. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0, + FAR const struct usb_ctrlreq_s *req, + FAR uint8_t *buffer) +{ + FAR struct stm32_usbhost_s *priv = (FAR struct stm32_usbhost_s *)drvr; + FAR struct stm32_ctrlinfo_s *ep0info = (FAR struct stm32_ctrlinfo_s *)ep0; + uint16_t buflen; + systime_t start; + systime_t elapsed; + int retries; + int ret; + + DEBUGASSERT(priv != NULL && ep0info != NULL && req != NULL); + usbhost_vtrace2(OTG_VTRACE2_CTRLIN, req->type, req->req); + uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n", + req->type, req->req, req->value[1], req->value[0], + req->index[1], req->index[0], req->len[1], req->len[0]); + + /* Extract values from the request */ + + buflen = stm32_getle16(req->len); + + /* We must have exclusive access to the USB host hardware and state structures */ + + stm32_takesem(&priv->exclsem); + + /* Loop, retrying until the retry time expires */ + + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) + { + /* Send the SETUP request */ + + ret = stm32_ctrl_sendsetup(priv, ep0info, req); + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_SENDSETUP, -ret); + continue; + } + + /* Get the start time. Loop again until the timeout expires */ + + start = clock_systimer(); + do + { + /* Handle the IN data phase (if any) */ + + if (buflen > 0) + { + ret = stm32_ctrl_recvdata(priv, ep0info, buffer, buflen); + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_RECVDATA, -ret); + } + } + + /* Handle the status OUT phase */ + + if (ret == OK) + { + priv->chan[ep0info->outndx].outdata1 ^= true; + ret = stm32_ctrl_senddata(priv, ep0info, NULL, 0); + if (ret == OK) + { + /* All success transactions exit here */ + + stm32_givesem(&priv->exclsem); + return OK; + } + + usbhost_trace1(OTG_TRACE1_SENDDATA, ret < 0 ? -ret : ret); + } + + /* Get the elapsed time (in frames) */ + + elapsed = clock_systimer() - start; + } + while (elapsed < STM32_DATANAK_DELAY); + } + + /* All failures exit here after all retries and timeouts have been exhausted */ + + stm32_givesem(&priv->exclsem); + return -ETIMEDOUT; +} + +static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0, + FAR const struct usb_ctrlreq_s *req, + FAR const uint8_t *buffer) +{ + FAR struct stm32_usbhost_s *priv = (FAR struct stm32_usbhost_s *)drvr; + FAR struct stm32_ctrlinfo_s *ep0info = (FAR struct stm32_ctrlinfo_s *)ep0; + uint16_t buflen; + systime_t start; + systime_t elapsed; + int retries; + int ret; + + DEBUGASSERT(priv != NULL && ep0info != NULL && req != NULL); + usbhost_vtrace2(OTG_VTRACE2_CTRLOUT, req->type, req->req); + uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n", + req->type, req->req, req->value[1], req->value[0], + req->index[1], req->index[0], req->len[1], req->len[0]); + + /* Extract values from the request */ + + buflen = stm32_getle16(req->len); + + /* We must have exclusive access to the USB host hardware and state structures */ + + stm32_takesem(&priv->exclsem); + + /* Loop, retrying until the retry time expires */ + + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) + { + /* Send the SETUP request */ + + ret = stm32_ctrl_sendsetup(priv, ep0info, req); + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_SENDSETUP, -ret); + continue; + } + + /* Get the start time. Loop again until the timeout expires */ + + start = clock_systimer(); + do + { + /* Handle the data OUT phase (if any) */ + + if (buflen > 0) + { + /* Start DATA out transfer (only one DATA packet) */ + + priv->chan[ep0info->outndx].outdata1 = true; + ret = stm32_ctrl_senddata(priv, ep0info, NULL, 0); + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_SENDDATA, -ret); + } + } + + /* Handle the status IN phase */ + + if (ret == OK) + { + ret = stm32_ctrl_recvdata(priv, ep0info, NULL, 0); + if (ret == OK) + { + /* All success transactins exit here */ + + stm32_givesem(&priv->exclsem); + return OK; + } + + usbhost_trace1(OTG_TRACE1_RECVDATA, ret < 0 ? -ret : ret); + } + + /* Get the elapsed time (in frames) */ + + elapsed = clock_systimer() - start; + } + while (elapsed < STM32_DATANAK_DELAY); + } + + /* All failures exit here after all retries and timeouts have been exhausted */ + + stm32_givesem(&priv->exclsem); + return -ETIMEDOUT; +} + +/**************************************************************************** + * Name: stm32_transfer + * + * Description: + * Process a request to handle a transfer descriptor. This method will + * enqueue the transfer request, blocking until the transfer completes. Only + * one transfer may be queued; Neither this method nor the ctrlin or + * ctrlout methods can be called again until this function returns. + * + * This is a blocking method; this functions will not return until the + * transfer has completed. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * ep - The IN or OUT endpoint descriptor for the device endpoint on which to + * perform the transfer. + * buffer - A buffer containing the data to be sent (OUT endpoint) or received + * (IN endpoint). buffer must have been allocated using DRVR_ALLOC + * buflen - The length of the data to be sent or received. + * + * Returned Values: + * On success, a non-negative value is returned that indicates the number + * of bytes successfully transferred. On a failure, a negated errno value is + * returned that indicates the nature of the failure: + * + * EAGAIN - If devices NAKs the transfer (or NYET or other error where + * it may be appropriate to restart the entire transaction). + * EPERM - If the endpoint stalls + * EIO - On a TX or data toggle error + * EPIPE - Overrun errors + * + * Assumptions: + * - Called from a single thread so no mutual exclusion is required. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static ssize_t stm32_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep, + FAR uint8_t *buffer, size_t buflen) +{ + FAR struct stm32_usbhost_s *priv = (FAR struct stm32_usbhost_s *)drvr; + unsigned int chidx = (unsigned int)ep; + ssize_t nbytes; + + uinfo("chidx: %d buflen: %d\n", (unsigned int)ep, buflen); + + DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0); + + /* We must have exclusive access to the USB host hardware and state structures */ + + stm32_takesem(&priv->exclsem); + + /* Handle IN and OUT transfer slightly differently */ + + if (priv->chan[chidx].in) + { + nbytes = stm32_in_transfer(priv, chidx, buffer, buflen); + } + else + { + nbytes = stm32_out_transfer(priv, chidx, buffer, buflen); + } + + stm32_givesem(&priv->exclsem); + return nbytes; +} + +/**************************************************************************** + * Name: stm32_asynch + * + * Description: + * Process a request to handle a transfer descriptor. This method will + * enqueue the transfer request and return immediately. When the transfer + * completes, the the callback will be invoked with the provided transfer. + * This method is useful for receiving interrupt transfers which may come + * infrequently. + * + * Only one transfer may be queued; Neither this method nor the ctrlin or + * ctrlout methods can be called again until the transfer completes. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * ep - The IN or OUT endpoint descriptor for the device endpoint on which to + * perform the transfer. + * buffer - A buffer containing the data to be sent (OUT endpoint) or received + * (IN endpoint). buffer must have been allocated using DRVR_ALLOC + * buflen - The length of the data to be sent or received. + * callback - This function will be called when the transfer completes. + * arg - The arbitrary parameter that will be passed to the callback function + * when the transfer completes. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * - Called from a single thread so no mutual exclusion is required. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep, + FAR uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, FAR void *arg) +{ + FAR struct stm32_usbhost_s *priv = (FAR struct stm32_usbhost_s *)drvr; + unsigned int chidx = (unsigned int)ep; + int ret; + + uinfo("chidx: %d buflen: %d\n", (unsigned int)ep, buflen); + + DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0); + + /* We must have exclusive access to the USB host hardware and state structures */ + + stm32_takesem(&priv->exclsem); + + /* Handle IN and OUT transfer slightly differently */ + + if (priv->chan[chidx].in) + { + ret = stm32_in_asynch(priv, chidx, buffer, buflen, callback, arg); + } + else + { + ret = stm32_out_asynch(priv, chidx, buffer, buflen, callback, arg); + } + + stm32_givesem(&priv->exclsem); + return ret; +} +#endif /* CONFIG_USBHOST_ASYNCH */ + +/************************************************************************************ + * Name: stm32_cancel + * + * Description: + * Cancel a pending transfer on an endpoint. Cancelled synchronous or + * asynchronous transfer will complete normally with the error -ESHUTDOWN. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * ep - The IN or OUT endpoint descriptor for the device endpoint on which an + * asynchronous transfer should be transferred. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure. + * + ************************************************************************************/ + +static int stm32_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) +{ + FAR struct stm32_usbhost_s *priv = (FAR struct stm32_usbhost_s *)drvr; + FAR struct stm32_chan_s *chan; + unsigned int chidx = (unsigned int)ep; + irqstate_t flags; + + uinfo("chidx: %u: %d\n", chidx); + + DEBUGASSERT(priv && chidx < STM32_MAX_TX_FIFOS); + chan = &priv->chan[chidx]; + + /* We need to disable interrupts to avoid race conditions with the asynchronous + * completion of the transfer being cancelled. + */ + + flags = enter_critical_section(); + + /* Halt the channel */ + + stm32_chan_halt(priv, chidx, CHREASON_CANCELLED); + chan->result = -ESHUTDOWN; + + /* Is there a thread waiting for this transfer to complete? */ + + if (chan->waiter) + { +#ifdef CONFIG_USBHOST_ASYNCH + /* Yes.. there should not also be a callback scheduled */ + + DEBUGASSERT(chan->callback == NULL); +#endif + + /* Wake'em up! */ + + stm32_givesem(&chan->waitsem); + chan->waiter = false; + } + +#ifdef CONFIG_USBHOST_ASYNCH + /* No.. is an asynchronous callback expected when the transfer + * completes? + */ + + else if (chan->callback) + { + usbhost_asynch_t callback; + FAR void *arg; + + /* Extract the callback information */ + + callback = chan->callback; + arg = chan->arg; + + chan->callback = NULL; + chan->arg = NULL; + chan->xfrd = 0; + + /* Then perform the callback */ + + callback(arg, -ESHUTDOWN); + } +#endif + + leave_critical_section(flags); + return OK; +} + +/************************************************************************************ + * Name: stm32_connect + * + * Description: + * New connections may be detected by an attached hub. This method is the + * mechanism that is used by the hub class to introduce a new connection + * and port description to the system. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * hport - The descriptor of the hub port that detected the connection + * related event + * connected - True: device connected; false: device disconnected + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure. + * + ************************************************************************************/ + +#ifdef CONFIG_USBHOST_HUB +static int stm32_connect(FAR struct usbhost_driver_s *drvr, + FAR struct usbhost_hubport_s *hport, + bool connected) +{ + FAR struct stm32_usbhost_s *priv = (FAR struct stm32_usbhost_s *)drvr; + irqstate_t flags; + + DEBUGASSERT(priv != NULL && hport != NULL); + + /* Set the connected/disconnected flag */ + + hport->connected = connected; + ullinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO"); + + /* Report the connection event */ + + flags = enter_critical_section(); + priv->hport = hport; + if (priv->pscwait) + { + priv->pscwait = false; + stm32_givesem(&priv->pscsem); + } + + leave_critical_section(flags); + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_disconnect + * + * Description: + * Called by the class when an error occurs and driver has been disconnected. + * The USB host driver should discard the handle to the class instance (it is + * stale) and not attempt any further interaction with the class driver instance + * (until a new instance is received from the create() method). The driver + * should not called the class' disconnected() method. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * hport - The port from which the device is being disconnected. Might be a port + * on a hub. + * + * Returned Values: + * None + * + * Assumptions: + * - Only a single class bound to a single device is supported. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static void stm32_disconnect(FAR struct usbhost_driver_s *drvr, + FAR struct usbhost_hubport_s *hport) +{ + DEBUGASSERT(hport != NULL); + hport->devclass = NULL; +} + +/**************************************************************************** + * Initialization + ****************************************************************************/ +/**************************************************************************** + * Name: stm32_portreset + * + * Description: + * Reset the USB host port. + * + * NOTE: "Before starting to drive a USB reset, the application waits for the + * OTG interrupt triggered by the debounce done bit (DBCDNE bit in + * OTG_FS_GOTGINT), which indicates that the bus is stable again after the + * electrical debounce caused by the attachment of a pull-up resistor on DP + * (FS) or DM (LS). + * + * Input Parameters: + * priv -- USB host driver private data structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_portreset(FAR struct stm32_usbhost_s *priv) +{ + uint32_t regval; + + regval = stm32_getreg(STM32_OTG_HPRT); + regval &= ~(OTG_HPRT_PENA | OTG_HPRT_PCDET | OTG_HPRT_PENCHNG | + OTG_HPRT_POCCHNG); + regval |= OTG_HPRT_PRST; + stm32_putreg(STM32_OTG_HPRT, regval); + + up_mdelay(20); + + regval &= ~OTG_HPRT_PRST; + stm32_putreg(STM32_OTG_HPRT, regval); + + up_mdelay(20); +} + +/**************************************************************************** + * Name: stm32_flush_txfifos + * + * Description: + * Flush the selected Tx FIFO. + * + * Input Parameters: + * txfnum -- USB host driver private data structure. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void stm32_flush_txfifos(uint32_t txfnum) +{ + uint32_t regval; + uint32_t timeout; + + /* Initiate the TX FIFO flush operation */ + + regval = OTG_GRSTCTL_TXFFLSH | txfnum; + stm32_putreg(STM32_OTG_GRSTCTL, regval); + + /* Wait for the FLUSH to complete */ + + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTG_GRSTCTL); + if ((regval & OTG_GRSTCTL_TXFFLSH) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); +} + +/**************************************************************************** + * Name: stm32_flush_rxfifo + * + * Description: + * Flush the Rx FIFO. + * + * Input Parameters: + * priv -- USB host driver private data structure. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void stm32_flush_rxfifo(void) +{ + uint32_t regval; + uint32_t timeout; + + /* Initiate the RX FIFO flush operation */ + + stm32_putreg(STM32_OTG_GRSTCTL, OTG_GRSTCTL_RXFFLSH); + + /* Wait for the FLUSH to complete */ + + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTG_GRSTCTL); + if ((regval & OTG_GRSTCTL_RXFFLSH) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); +} + +/**************************************************************************** + * Name: stm32_vbusdrive + * + * Description: + * Drive the Vbus +5V. + * + * Input Parameters: + * priv - USB host driver private data structure. + * state - True: Drive, False: Don't drive + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void stm32_vbusdrive(FAR struct stm32_usbhost_s *priv, bool state) +{ + uint32_t regval; + + /* Enable/disable the external charge pump */ + + stm32_usbhost_vbusdrive(0, state); + + /* Turn on the Host port power. */ + + regval = stm32_getreg(STM32_OTG_HPRT); + regval &= ~(OTG_HPRT_PENA | OTG_HPRT_PCDET | OTG_HPRT_PENCHNG | + OTG_HPRT_POCCHNG); + + if (((regval & OTG_HPRT_PPWR) == 0) && state) + { + regval |= OTG_HPRT_PPWR; + stm32_putreg(STM32_OTG_HPRT, regval); + } + + if (((regval & OTG_HPRT_PPWR) != 0) && !state) + { + regval &= ~OTG_HPRT_PPWR; + stm32_putreg(STM32_OTG_HPRT, regval); + } + + up_mdelay(200); +} + +/**************************************************************************** + * Name: stm32_host_initialize + * + * Description: + * Initialize/re-initialize hardware for host mode operation. At present, + * this function is called only from stm32_hw_initialize(). But if OTG mode + * were supported, this function would also be called to swtich between + * host and device modes on a connector ID change interrupt. + * + * Input Parameters: + * priv -- USB host driver private data structure. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void stm32_host_initialize(FAR struct stm32_usbhost_s *priv) +{ + uint32_t regval; + uint32_t offset; + int i; + + /* Restart the PHY Clock */ + + stm32_putreg(STM32_OTG_PCGCCTL, 0); + + /* Initialize Host Configuration (HCFG) register */ + + regval = stm32_getreg(STM32_OTG_HCFG); + regval &= ~OTG_HCFG_FSLSPCS_MASK; + regval |= OTG_HCFG_FSLSPCS_FS48MHz; + stm32_putreg(STM32_OTG_HCFG, regval); + + /* Reset the host port */ + + stm32_portreset(priv); + + /* Clear the FS-/LS-only support bit in the HCFG register */ + + regval = stm32_getreg(STM32_OTG_HCFG); + regval &= ~OTG_HCFG_FSLSS; + stm32_putreg(STM32_OTG_HCFG, regval); + + /* Carve up FIFO memory for the Rx FIFO and the periodic and non-periodic Tx FIFOs */ + /* Configure Rx FIFO size (GRXFSIZ) */ + + stm32_putreg(STM32_OTG_GRXFSIZ, CONFIG_STM32_OTG_RXFIFO_SIZE); + offset = CONFIG_STM32_OTG_RXFIFO_SIZE; + + /* Setup the host non-periodic Tx FIFO size (HNPTXFSIZ) */ + + regval = (offset | (CONFIG_STM32_OTG_NPTXFIFO_SIZE << OTG_HNPTXFSIZ_NPTXFD_SHIFT)); + stm32_putreg(STM32_OTG_HNPTXFSIZ, regval); + offset += CONFIG_STM32_OTG_NPTXFIFO_SIZE; + + /* Set up the host periodic Tx fifo size register (HPTXFSIZ) */ + + regval = (offset | (CONFIG_STM32_OTG_PTXFIFO_SIZE << OTG_HPTXFSIZ_PTXFD_SHIFT)); + stm32_putreg(STM32_OTG_HPTXFSIZ, regval); + + /* If OTG were supported, we sould need to clear HNP enable bit in the + * USB_OTG control register about here. + */ + + /* Flush all FIFOs */ + + stm32_flush_txfifos(OTG_GRSTCTL_TXFNUM_HALL); + stm32_flush_rxfifo(); + + /* Clear all pending HC Interrupts */ + + for (i = 0; i < STM32_NHOST_CHANNELS; i++) + { + stm32_putreg(STM32_OTG_HCINT(i), 0xffffffff); + stm32_putreg(STM32_OTG_HCINTMSK(i), 0); + } + + /* Driver Vbus +5V (the smoke test). Should be done elsewhere in OTG + * mode. + */ + + stm32_vbusdrive(priv, true); + + /* Enable host interrupts */ + + stm32_hostinit_enable(); +} + +/**************************************************************************** + * Name: stm32_sw_initialize + * + * Description: + * One-time setup of the host driver state structure. + * + * Input Parameters: + * priv -- USB host driver private data structure. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv) +{ + FAR struct usbhost_driver_s *drvr; + FAR struct usbhost_hubport_s *hport; + int i; + + /* Initialize the device operations */ + + drvr = &priv->drvr; + drvr->ep0configure = stm32_ep0configure; + drvr->epalloc = stm32_epalloc; + drvr->epfree = stm32_epfree; + drvr->alloc = stm32_alloc; + drvr->free = stm32_free; + drvr->ioalloc = stm32_ioalloc; + drvr->iofree = stm32_iofree; + drvr->ctrlin = stm32_ctrlin; + drvr->ctrlout = stm32_ctrlout; + drvr->transfer = stm32_transfer; +#ifdef CONFIG_USBHOST_ASYNCH + drvr->asynch = stm32_asynch; +#endif + drvr->cancel = stm32_cancel; +#ifdef CONFIG_USBHOST_HUB + drvr->connect = stm32_connect; +#endif + drvr->disconnect = stm32_disconnect; + + /* Initialize the public port representation */ + + hport = &priv->rhport.hport; + hport->drvr = drvr; +#ifdef CONFIG_USBHOST_HUB + hport->parent = NULL; +#endif + hport->ep0 = (usbhost_ep_t)&priv->ep0; + hport->speed = USB_SPEED_FULL; + + /* Initialize function address generation logic */ + + usbhost_devaddr_initialize(&priv->rhport); + + /* Initialize semaphores */ + + sem_init(&priv->pscsem, 0, 0); + sem_init(&priv->exclsem, 0, 1); + + /* Initialize the driver state data */ + + priv->smstate = SMSTATE_DETACHED; + priv->connected = false; + priv->change = false; + + /* Put all of the channels back in their initial, allocated state */ + + memset(priv->chan, 0, STM32_MAX_TX_FIFOS * sizeof(struct stm32_chan_s)); + + /* Initialize each channel */ + + for (i = 0; i < STM32_MAX_TX_FIFOS; i++) + { + FAR struct stm32_chan_s *chan = &priv->chan[i]; + chan->chidx = i; + sem_init(&chan->waitsem, 0, 0); + } +} + +/**************************************************************************** + * Name: stm32_hw_initialize + * + * Description: + * One-time setup of the host controller harware for normal operations. + * + * Input Parameters: + * priv -- USB host driver private data structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static inline int stm32_hw_initialize(FAR struct stm32_usbhost_s *priv) +{ + uint32_t regval; + unsigned long timeout; + + /* Set the PHYSEL bit in the GUSBCFG register to select the OTG FS serial + * transceiver: "This bit is always 1 with write-only access" + */ + + regval = stm32_getreg(STM32_OTG_GUSBCFG); + regval |= OTG_GUSBCFG_PHYSEL; + stm32_putreg(STM32_OTG_GUSBCFG, regval); + + /* Reset after a PHY select and set Host mode. First, wait for AHB master + * IDLE state. + */ + + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) + { + up_udelay(3); + regval = stm32_getreg(STM32_OTG_GRSTCTL); + if ((regval & OTG_GRSTCTL_AHBIDL) != 0) + { + break; + } + } + + /* Then perform the core soft reset. */ + + stm32_putreg(STM32_OTG_GRSTCTL, OTG_GRSTCTL_CSRST); + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTG_GRSTCTL); + if ((regval & OTG_GRSTCTL_CSRST) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); + + /* Deactivate the power down */ + + regval = (OTG_GCCFG_PWRDWN | OTG_GCCFG_VBUSASEN | OTG_GCCFG_VBUSBSEN); +#ifndef CONFIG_USBDEV_VBUSSENSING + regval |= OTG_GCCFG_NOVBUSSENS; +#endif +#ifdef CONFIG_STM32_OTG_SOFOUTPUT + regval |= OTG_GCCFG_SOFOUTEN; +#endif + stm32_putreg(STM32_OTG_GCCFG, regval); + up_mdelay(20); + + /* Initialize OTG features: In order to support OTP, the HNPCAP and SRPCAP + * bits would need to be set in the GUSBCFG register about here. + */ + + /* Force Host Mode */ + + regval = stm32_getreg(STM32_OTG_GUSBCFG); + regval &= ~OTG_GUSBCFG_FDMOD; + regval |= OTG_GUSBCFG_FHMOD; + stm32_putreg(STM32_OTG_GUSBCFG, regval); + up_mdelay(50); + + /* Initialize host mode and return success */ + + stm32_host_initialize(priv); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_otgfshost_initialize + * + * Description: + * Initialize USB host device controller hardware. + * + * Input Parameters: + * controller -- If the device supports more than USB host controller, then + * this identifies which controller is being initialized. Normally, this + * is just zero. + * + * Returned Value: + * And instance of the USB host interface. The controlling task should + * use this interface to (1) call the wait() method to wait for a device + * to be connected, and (2) call the enumerate() method to bind the device + * to a class driver. + * + * Assumptions: + * - This function should called in the initialization sequence in order + * to initialize the USB device functionality. + * - Class drivers should be initialized prior to calling this function. + * Otherwise, there is a race condition if the device is already connected. + * + ****************************************************************************/ + +FAR struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) +{ + /* At present, there is only support for a single OTG FS host. Hence it is + * pre-allocated as g_usbhost. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple devices. + */ + + FAR struct stm32_usbhost_s *priv = &g_usbhost; + + /* Sanity checks */ + + DEBUGASSERT(controller == 0); + + /* Make sure that interrupts from the OTG FS core are disabled */ + + stm32_gint_disable(); + + /* Reset the state of the host driver */ + + stm32_sw_initialize(priv); + + /* Alternate function pin configuration. Here we assume that: + * + * 1. GPIOA, SYSCFG, and OTG FS peripheral clocking have already been\ + * enabled as part of the boot sequence. + * 2. Board-specific logic has already enabled other board specific GPIOs + * for things like soft pull-up, VBUS sensing, power controls, and over- + * current detection. + */ + + /* Configure OTG FS alternate function pins for DM, DP, ID, and SOF. + * + * PIN* SIGNAL DIRECTION + * ---- ----------- ---------- + * PA8 OTG_FS_SOF SOF clock output + * PA9 OTG_FS_VBUS VBUS input for device, Driven by external regulator by + * host (not an alternate function) + * PA10 OTG_FS_ID OTG ID pin (only needed in Dual mode) + * PA11 OTG_FS_DM D- I/O + * PA12 OTG_FS_DP D+ I/O + * + * *Pins may vary from device-to-device. + */ + + stm32_configgpio(GPIO_OTG_DM); + stm32_configgpio(GPIO_OTG_DP); + stm32_configgpio(GPIO_OTG_ID); /* Only needed for OTG */ + + /* SOF output pin configuration is configurable */ + +#ifdef CONFIG_STM32_OTG_SOFOUTPUT + stm32_configgpio(GPIO_OTG_SOF); +#endif + + /* Initialize the USB OTG FS core */ + + stm32_hw_initialize(priv); + + /* Attach USB host controller interrupt handler */ + + if (irq_attach(STM32_IRQ_OTGFS, stm32_gint_isr) != 0) + { + usbhost_trace1(OTG_TRACE1_IRQATTACH, 0); + return NULL; + } + + /* Enable USB OTG FS global interrupts */ + + stm32_gint_enable(); + + /* Enable interrupts at the interrupt controller */ + + up_enable_irq(STM32_IRQ_OTGFS); + return &g_usbconn; +} + +#endif /* CONFIG_USBHOST && CONFIG_STM32_OTGFS */ diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.h b/arch/arm/src/stm32f7/stm32_sdmmc.h index 29e14683ce..18e6c44601 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.h +++ b/arch/arm/src/stm32f7/stm32_sdmmc.h @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/arm/src/stm32/stm32_sdio.h + * arch/arm/src/stm32f7/stm32_sdio.h * * Copyright (C) 2009, 2011, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt -- GitLab From 6f2e37e3adb3da2bcb3a7fe0bacfc23b7dd9707d Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Sun, 19 Jun 2016 23:06:21 +0200 Subject: [PATCH 003/734] mmc + usb --- arch/arm/src/stm32f7/stm32_otg.h | 32 +- arch/arm/src/stm32f7/stm32_otgdev.c | 17 +- arch/arm/src/stm32f7/stm32_otghost.c | 84 ++--- arch/arm/src/stm32f7/stm32_sdmmc.c | 5 + configs/stm32f746-ws/nsh/defconfig | 86 ++++- configs/stm32f746-ws/src/Makefile | 10 +- .../stm32f746-ws/src/stm32_appinitialize.c | 18 + configs/stm32f746-ws/src/stm32_dma_alloc.c | 117 ++++++ configs/stm32f746-ws/src/stm32_sdmmc.c | 171 +++++++++ configs/stm32f746-ws/src/stm32_usb.c | 340 ++++++++++++++++++ configs/stm32f746-ws/src/stm32f746-ws.h | 33 ++ 11 files changed, 842 insertions(+), 71 deletions(-) create mode 100644 configs/stm32f746-ws/src/stm32_dma_alloc.c create mode 100644 configs/stm32f746-ws/src/stm32_sdmmc.c create mode 100644 configs/stm32f746-ws/src/stm32_usb.c diff --git a/arch/arm/src/stm32f7/stm32_otg.h b/arch/arm/src/stm32f7/stm32_otg.h index 69def14608..0bb6b9b393 100644 --- a/arch/arm/src/stm32f7/stm32_otg.h +++ b/arch/arm/src/stm32f7/stm32_otg.h @@ -44,10 +44,10 @@ #include - +#include "chip.h" #include "chip/stm32_otg.h" -#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS) +#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGHS) /************************************************************************************ * Pre-processor Definitions @@ -58,16 +58,26 @@ # define CONFIG_OTG_PRI NVIC_SYSH_PRIORITY_DEFAULT #endif -#if defined(CONFIG_STM32_OTGFS) -# define STM32_IRQ_OTG STM32_IRQ_OTGFS -# define STM32_OTG_BASE STM32_USBOTGFS_BASE -# define STM32_NENDPOINTS (6) /* ep0-5 x 2 for IN and OUT */ +#if defined(CONFIG_STM32F7_OTGFS) +# define STM32_IRQ_OTG STM32_IRQ_OTGFS +# define STM32_OTG_BASE STM32_USBOTGFS_BASE +# define STM32_NENDPOINTS (6) /* ep0-5 x 2 for IN and OUT */ +# define GPIO_OTG_DM GPIO_OTGFS_DM +# define GPIO_OTG_DP GPIO_OTGFS_DP +# define GPIO_OTG_ID GPIO_OTGFS_ID +# define GPIO_OTG_SOF GPIO_OTGFS_SOF + #endif -#if defined(CONFIG_STM32_OTGHS) -# define STM32_IRQ_OTG STM32_IRQ_OTGHS -# define STM32_OTG_BASE STM32_USBOTGHS_BASE -# define STM32_NENDPOINTS (8) /* ep0-7 x 2 for IN and OUT */ +#if defined(CONFIG_STM32F7_OTGHS) +# define STM32_IRQ_OTG STM32_IRQ_OTGHS +# define STM32_OTG_BASE STM32_USBOTGHS_BASE +# define STM32_NENDPOINTS (8) /* ep0-7 x 2 for IN and OUT */ +# define GPIO_OTG_DM GPIO_OTGHS_DM +# define GPIO_OTG_DP GPIO_OTGHS_DP +# define GPIO_OTG_ID GPIO_OTGHS_ID +# define GPIO_OTG_SOF GPIO_OTGHS_SOF + #endif /************************************************************************************ @@ -134,6 +144,6 @@ void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32_OTGFS */ +#endif /* CONFIG_STM32F7_OTGFS */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_OTG_H */ diff --git a/arch/arm/src/stm32f7/stm32_otgdev.c b/arch/arm/src/stm32f7/stm32_otgdev.c index e362ef2b45..d4d46c4efb 100644 --- a/arch/arm/src/stm32f7/stm32_otgdev.c +++ b/arch/arm/src/stm32f7/stm32_otgdev.c @@ -57,12 +57,13 @@ #include #include "chip.h" +#include "stm32_gpio.h" #include "stm32_otg.h" #include "up_arch.h" #include "up_internal.h" -#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS)) +#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGHS)) /**************************************************************************** * Pre-processor Definitions @@ -469,7 +470,7 @@ struct stm32_usbdev_s /* Register operations ********************************************************/ -#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); #else @@ -789,7 +790,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = * ****************************************************************************/ -#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -852,7 +853,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -5134,7 +5135,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) stm32_putreg(OTG_GAHBCFG_TXFELVL, STM32_OTG_GAHBCFG); -#if defined(CONFIG_STM32_OTGHS) +#if defined(CONFIG_STM32F7_OTGHS) /* Set the PHYSEL bit in the GUSBCFG register to select the OTG HS serial * transceiver: "This bit is always 1 with write-only access" */ @@ -5329,7 +5330,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) stm32_putreg(0xbfffffff, STM32_OTG_GINTSTS); -#ifdef defined(CONFIG_STM32_OTGHS) +#if defined(CONFIG_STM32F7_OTGHS) /* Disable the ULPI Clock enable in RCC AHB1 Register. This must * be done because if both the ULPI and the FS PHY clock enable bits * are set at the same time, the ARM never awakens from WFI due to @@ -5424,7 +5425,7 @@ void up_usbinitialize(void) /* SOF output pin configuration is configurable. */ -#ifdef CONFIG_STM32_OTG_SOFOUTPUT +#ifdef CONFIG_STM32F7_OTG_SOFOUTPUT stm32_configgpio(GPIO_OTG_SOF); #endif @@ -5663,4 +5664,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) return OK; } -#endif /* CONFIG_USBDEV && CONFIG_STM32_OTGDEV */ +#endif /* CONFIG_USBDEV && CONFIG_STM32F7_OTGDEV */ diff --git a/arch/arm/src/stm32f7/stm32_otghost.c b/arch/arm/src/stm32f7/stm32_otghost.c index cc00b1336f..0feb6c98da 100644 --- a/arch/arm/src/stm32f7/stm32_otghost.c +++ b/arch/arm/src/stm32f7/stm32_otghost.c @@ -67,7 +67,7 @@ #include "stm32_otg.h" -#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32_OTGFS) +#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32F7_OTGFS) /**************************************************************************** * Pre-processor Definitions @@ -78,61 +78,61 @@ * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block - * CONFIG_STM32_SYSCFG - Needed + * CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32F7_SYSCFG - Needed * * Options: * - * CONFIG_STM32_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * CONFIG_STM32F7_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. * Default 128 (512 bytes) - * CONFIG_STM32_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * CONFIG_STM32F7_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO * in 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit + * CONFIG_STM32F7_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit * words. Default 96 (384 bytes) - * CONFIG_STM32_OTG_DESCSIZE - Maximum size of a descriptor. Default: 128 - * CONFIG_STM32_OTG_SOFINTR - Enable SOF interrupts. Why would you ever + * CONFIG_STM32F7_OTG_DESCSIZE - Maximum size of a descriptor. Default: 128 + * CONFIG_STM32F7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? - * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32F7_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG_FEATURES. - * CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB + * CONFIG_STM32F7_USBHOST_PKTDUMP - Dump all incoming and outgoing USB * packets. Depends on CONFIG_DEBUG_FEATURES. */ /* Pre-requisites (partial) */ -#ifndef CONFIG_STM32_SYSCFG -# error "CONFIG_STM32_SYSCFG is required" +#ifndef CONFIG_STM32F7_SYSCFG +# error "CONFIG_STM32F7_SYSCFG is required" #endif /* Default RxFIFO size */ -#ifndef CONFIG_STM32_OTG_RXFIFO_SIZE -# define CONFIG_STM32_OTG_RXFIFO_SIZE 128 +#ifndef CONFIG_STM32F7_OTG_RXFIFO_SIZE +# define CONFIG_STM32F7_OTG_RXFIFO_SIZE 128 #endif /* Default host non-periodic Tx FIFO size */ -#ifndef CONFIG_STM32_OTG_NPTXFIFO_SIZE -# define CONFIG_STM32_OTG_NPTXFIFO_SIZE 96 +#ifndef CONFIG_STM32F7_OTG_NPTXFIFO_SIZE +# define CONFIG_STM32F7_OTG_NPTXFIFO_SIZE 96 #endif /* Default host periodic Tx fifo size register */ -#ifndef CONFIG_STM32_OTG_PTXFIFO_SIZE -# define CONFIG_STM32_OTG_PTXFIFO_SIZE 96 +#ifndef CONFIG_STM32F7_OTG_PTXFIFO_SIZE +# define CONFIG_STM32F7_OTG_PTXFIFO_SIZE 96 #endif /* Maximum size of a descriptor */ -#ifndef CONFIG_STM32_OTG_DESCSIZE -# define CONFIG_STM32_OTG_DESCSIZE 128 +#ifndef CONFIG_STM32F7_OTG_DESCSIZE +# define CONFIG_STM32F7_OTG_DESCSIZE 128 #endif /* Register/packet debug depends on CONFIG_DEBUG_FEATURES */ #ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_STM32_USBHOST_REGDEBUG -# undef CONFIG_STM32_USBHOST_PKTDUMP +# undef CONFIG_STM32F7_USBHOST_REGDEBUG +# undef CONFIG_STM32F7_USBHOST_PKTDUMP #endif /* HCD Setup *******************************************************************/ @@ -283,7 +283,7 @@ struct stm32_usbhost_s /* Register operations ********************************************************/ -#ifdef CONFIG_STM32_USBHOST_REGDEBUG +#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite); static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t stm32_getreg(uint32_t addr); @@ -296,7 +296,7 @@ static void stm32_putreg(uint32_t addr, uint32_t value); static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, uint32_t setbits); -#ifdef CONFIG_STM32_USBHOST_PKTDUMP +#ifdef CONFIG_STM32F7_USBHOST_PKTDUMP # define stm32_pktdump(m,b,n) lib_dumpbuffer(m,b,n) #else # define stm32_pktdump(m,b,n) @@ -390,7 +390,7 @@ static void stm32_gint_disconnected(FAR struct stm32_usbhost_s *priv); /* Second level interrupt handlers */ -#ifdef CONFIG_STM32_OTG_SOFINTR +#ifdef CONFIG_STM32F7_OTG_SOFINTR static inline void stm32_gint_sofisr(FAR struct stm32_usbhost_s *priv); #endif static inline void stm32_gint_rxflvlisr(FAR struct stm32_usbhost_s *priv); @@ -503,7 +503,7 @@ static struct usbhost_connection_s g_usbconn = * ****************************************************************************/ -#ifdef CONFIG_STM32_USBHOST_REGDEBUG +#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) { llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); @@ -518,7 +518,7 @@ static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_STM32_USBHOST_REGDEBUG +#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) { static uint32_t prevaddr = 0; @@ -582,7 +582,7 @@ static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_STM32_USBHOST_REGDEBUG +#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { /* Read the value from the register */ @@ -604,7 +604,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32_USBHOST_REGDEBUG +#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG static void stm32_putreg(uint32_t addr, uint32_t val) { /* Check if we need to print this value */ @@ -2907,7 +2907,7 @@ static void stm32_gint_disconnected(FAR struct stm32_usbhost_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32_OTG_SOFINTR +#ifdef CONFIG_STM32F7_OTG_SOFINTR static inline void stm32_gint_sofisr(FAR struct stm32_usbhost_s *priv) { /* Handle SOF interrupt */ @@ -3469,7 +3469,7 @@ static int stm32_gint_isr(int irq, FAR void *context) /* Handle the start of frame interrupt */ -#ifdef CONFIG_STM32_OTG_SOFINTR +#ifdef CONFIG_STM32F7_OTG_SOFINTR if ((pending & OTG_GINT_SOF) != 0) { usbhost_vtrace1(OTG_VTRACE1_GINT_SOF, 0); @@ -3634,7 +3634,7 @@ static inline void stm32_hostinit_enable(void) * OTG_GINT_DISC : Disconnect detected interrupt */ -#ifdef CONFIG_STM32_OTG_SOFINTR +#ifdef CONFIG_STM32F7_OTG_SOFINTR regval |= (OTG_GINT_SOF | OTG_GINT_RXFLVL | OTG_GINT_IISOOXFR | OTG_GINT_HPRT | OTG_GINT_HC | OTG_GINT_DISC); #else @@ -4138,7 +4138,7 @@ static int stm32_alloc(FAR struct usbhost_driver_s *drvr, /* There is no special memory requirement for the STM32. */ - alloc = (FAR uint8_t *)kmm_malloc(CONFIG_STM32_OTG_DESCSIZE); + alloc = (FAR uint8_t *)kmm_malloc(CONFIG_STM32F7_OTG_DESCSIZE); if (!alloc) { return -ENOMEM; @@ -4147,7 +4147,7 @@ static int stm32_alloc(FAR struct usbhost_driver_s *drvr, /* Return the allocated address and size of the descriptor buffer */ *buffer = alloc; - *maxlen = CONFIG_STM32_OTG_DESCSIZE; + *maxlen = CONFIG_STM32F7_OTG_DESCSIZE; return OK; } @@ -4987,18 +4987,18 @@ static void stm32_host_initialize(FAR struct stm32_usbhost_s *priv) /* Carve up FIFO memory for the Rx FIFO and the periodic and non-periodic Tx FIFOs */ /* Configure Rx FIFO size (GRXFSIZ) */ - stm32_putreg(STM32_OTG_GRXFSIZ, CONFIG_STM32_OTG_RXFIFO_SIZE); - offset = CONFIG_STM32_OTG_RXFIFO_SIZE; + stm32_putreg(STM32_OTG_GRXFSIZ, CONFIG_STM32F7_OTG_RXFIFO_SIZE); + offset = CONFIG_STM32F7_OTG_RXFIFO_SIZE; /* Setup the host non-periodic Tx FIFO size (HNPTXFSIZ) */ - regval = (offset | (CONFIG_STM32_OTG_NPTXFIFO_SIZE << OTG_HNPTXFSIZ_NPTXFD_SHIFT)); + regval = (offset | (CONFIG_STM32F7_OTG_NPTXFIFO_SIZE << OTG_HNPTXFSIZ_NPTXFD_SHIFT)); stm32_putreg(STM32_OTG_HNPTXFSIZ, regval); - offset += CONFIG_STM32_OTG_NPTXFIFO_SIZE; + offset += CONFIG_STM32F7_OTG_NPTXFIFO_SIZE; /* Set up the host periodic Tx fifo size register (HPTXFSIZ) */ - regval = (offset | (CONFIG_STM32_OTG_PTXFIFO_SIZE << OTG_HPTXFSIZ_PTXFD_SHIFT)); + regval = (offset | (CONFIG_STM32F7_OTG_PTXFIFO_SIZE << OTG_HPTXFSIZ_PTXFD_SHIFT)); stm32_putreg(STM32_OTG_HPTXFSIZ, regval); /* If OTG were supported, we sould need to clear HNP enable bit in the @@ -5173,7 +5173,7 @@ static inline int stm32_hw_initialize(FAR struct stm32_usbhost_s *priv) #ifndef CONFIG_USBDEV_VBUSSENSING regval |= OTG_GCCFG_NOVBUSSENS; #endif -#ifdef CONFIG_STM32_OTG_SOFOUTPUT +#ifdef CONFIG_STM32F7_OTG_SOFOUTPUT regval |= OTG_GCCFG_SOFOUTEN; #endif stm32_putreg(STM32_OTG_GCCFG, regval); @@ -5277,7 +5277,7 @@ FAR struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) /* SOF output pin configuration is configurable */ -#ifdef CONFIG_STM32_OTG_SOFOUTPUT +#ifdef CONFIG_STM32F7_OTG_SOFOUTPUT stm32_configgpio(GPIO_OTG_SOF); #endif @@ -5303,4 +5303,4 @@ FAR struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) return &g_usbconn; } -#endif /* CONFIG_USBHOST && CONFIG_STM32_OTGFS */ +#endif /* CONFIG_USBHOST && CONFIG_STM32F7_OTGFS */ diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index 58f7b7318d..4f2b7a8d01 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -964,6 +964,11 @@ static void stm32_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl) regval &= ~(SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE_MASK); dctrl &= (SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE_MASK); regval |= (dctrl | SDIO_DCTRL_DTEN); + +#ifdef CONFIG_SDIO_DMA + regval |= SDIO_DCTRL_DMAEN; +#endif + putreg32(regval, STM32_SDMMC1_DCTRL); } diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig index 97b867c160..44a25aec95 100644 --- a/configs/stm32f746-ws/nsh/defconfig +++ b/configs/stm32f746-ws/nsh/defconfig @@ -52,6 +52,12 @@ CONFIG_ARCH_HAVE_CUSTOMOPT=y CONFIG_DEBUG_NOOPT=y # CONFIG_DEBUG_CUSTOMOPT is not set # CONFIG_DEBUG_FULLOPT is not set +CONFIG_DEBUG_ERROR=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_WARN=y +CONFIG_DEBUG_FS_INFO=y +CONFIG_DEBUG_FS_ERROR=y +CONFIG_DEBUG_FS_WARN=y # # System Type @@ -267,7 +273,7 @@ CONFIG_STM32F7_HAVE_DMA2D=y CONFIG_STM32F7_ADC=y # CONFIG_STM32F7_CAN is not set # CONFIG_STM32F7_DAC is not set -# CONFIG_STM32F7_DMA is not set +CONFIG_STM32F7_DMA=y CONFIG_STM32F7_I2C=y # CONFIG_STM32F7_SAI is not set CONFIG_STM32F7_SPI=y @@ -282,7 +288,7 @@ CONFIG_STM32F7_ADC1=y # CONFIG_STM32F7_CEC is not set # CONFIG_STM32F7_CRC is not set # CONFIG_STM32F7_DMA1 is not set -# CONFIG_STM32F7_DMA2 is not set +CONFIG_STM32F7_DMA2=y # CONFIG_STM32F7_DAC1 is not set # CONFIG_STM32F7_DAC2 is not set # CONFIG_STM32F7_DCMI is not set @@ -294,13 +300,13 @@ CONFIG_STM32F7_I2C1=y # CONFIG_STM32F7_I2C3 is not set # CONFIG_STM32F7_LPTIM1 is not set # CONFIG_STM32F7_LTDC is not set -# CONFIG_STM32F7_OTGFS is not set +##CONFIG_STM32F7_OTGFS=y # CONFIG_STM32F7_OTGHS is not set # CONFIG_STM32F7_QUADSPI is not set # CONFIG_STM32F7_RNG is not set # CONFIG_STM32F7_SAI1 is not set # CONFIG_STM32F7_SAI2 is not set -# CONFIG_STM32F7_SDMMC1 is not set +CONFIG_STM32F7_SDMMC1=y # CONFIG_STM32F7_SPDIFRX is not set CONFIG_STM32F7_SPI1=y # CONFIG_STM32F7_SPI2 is not set @@ -352,7 +358,7 @@ CONFIG_STM32F7_USART6=y # # CONFIG_ARCH_NOINTC is not set # CONFIG_ARCH_VECNOTIRQ is not set -# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_DMA=y CONFIG_ARCH_HAVE_IRQPRIO=y # CONFIG_ARCH_L2CACHE is not set # CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set @@ -416,6 +422,7 @@ CONFIG_ARCH_BOARD="stm32f746-ws" # Common Board Options # CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 # # Board-Specific Options @@ -427,6 +434,7 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set +##CONFIG_BOARDCTL_USBDEVCTRL=y # # RTOS Features @@ -550,6 +558,17 @@ CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set # CONFIG_DEV_LOOP is not set +CONFIG_MMCSD=y +CONFIG_MMCSD_NSLOTS=1 +# CONFIG_MMCSD_READONLY is not set +CONFIG_MMCSD_MULTIBLOCK_DISABLE=y +# CONFIG_MMCSD_MMCSUPPORT is not set +CONFIG_MMCSD_HAVECARDDETECT=y +# CONFIG_MMCSD_SPI is not set +CONFIG_ARCH_HAVE_SDIO=y +CONFIG_ARCH_HAVE_SDIOWAIT_WRCOMPLETE=y +CONFIG_MMCSD_SDIO=y + # # Buffering # @@ -579,6 +598,8 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_I2S is not set +CONFIG_SDIO_DMA=y + # # Timer Driver Support # @@ -669,7 +690,50 @@ CONFIG_USART6_2STOP=0 # CONFIG_USART6_IFLOWCONTROL is not set # CONFIG_USART6_OFLOWCONTROL is not set # CONFIG_USART6_DMA is not set -# CONFIG_USBDEV is not set +##CONFIG_USBDEV=y +# CONFIG_USBHOST is not set +# CONFIG_DRIVERS_WIRELESS is not set + + +# +# USB Device Controller Driver Options +# +# CONFIG_USBDEV_ISOCHRONOUS is not set +# CONFIG_USBDEV_DUALSPEED is not set +##CONFIG_USBDEV_SELFPOWERED=y +# CONFIG_USBDEV_BUSPOWERED is not set +##CONFIG_USBDEV_MAXPOWER=100 +# CONFIG_USBDEV_DMA is not set +# CONFIG_ARCH_USBDEV_STALLQUEUE is not set +# CONFIG_USBDEV_TRACE is not set + +# +# USB Device Class Driver Options +# +# CONFIG_USBDEV_COMPOSITE is not set +# CONFIG_PL2303 is not set +##CONFIG_CDCACM=y +##CONFIG_CDCACM_CONSOLE=y +##CONFIG_CDCACM_EP0MAXPACKET=64 +##CONFIG_CDCACM_EPINTIN=1 +##CONFIG_CDCACM_EPINTIN_FSSIZE=64 +##CONFIG_CDCACM_EPINTIN_HSSIZE=64 +##CONFIG_CDCACM_EPBULKOUT=3 +##CONFIG_CDCACM_EPBULKOUT_FSSIZE=64 +##CONFIG_CDCACM_EPBULKOUT_HSSIZE=512 +##CONFIG_CDCACM_EPBULKIN=2 +##CONFIG_CDCACM_EPBULKIN_FSSIZE=64 +##CONFIG_CDCACM_EPBULKIN_HSSIZE=512 +##CONFIG_CDCACM_NRDREQS=4 +##CONFIG_CDCACM_NWRREQS=4 +##CONFIG_CDCACM_BULKIN_REQLEN=96 +##CONFIG_CDCACM_RXBUFSIZE=256 +##CONFIG_CDCACM_TXBUFSIZE=256 +##CONFIG_CDCACM_VENDORID=0x0525 +##CONFIG_CDCACM_PRODUCTID=0xa4a7 +##CONFIG_CDCACM_VENDORSTR="NuttX" +##CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial" +# CONFIG_USBMSC is not set # CONFIG_USBHOST is not set # CONFIG_DRIVERS_WIRELESS is not set @@ -706,13 +770,17 @@ CONFIG_USART6_2STOP=0 # CONFIG_DISABLE_MOUNTPOINT is not set # CONFIG_FS_AUTOMOUNTER is not set # CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_FS_READABLE is not set -# CONFIG_FS_WRITABLE is not set +CONFIG_FS_READABLE=y +CONFIG_FS_WRITABLE=y # CONFIG_FS_AIO is not set # CONFIG_FS_NAMED_SEMAPHORES is not set CONFIG_FS_MQUEUE_MPATH="/var/mqueue" # CONFIG_FS_RAMMAP is not set -# CONFIG_FS_FAT is not set +CONFIG_FS_FAT=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=32 +CONFIG_FAT_DMAMEMORY=y # CONFIG_FS_NXFFS is not set # CONFIG_FS_ROMFS is not set # CONFIG_FS_TMPFS is not set diff --git a/configs/stm32f746-ws/src/Makefile b/configs/stm32f746-ws/src/Makefile index b20f916b7e..4096729548 100644 --- a/configs/stm32f746-ws/src/Makefile +++ b/configs/stm32f746-ws/src/Makefile @@ -36,10 +36,18 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = stm32_boot.c stm32_spi.c +CSRCS = stm32_boot.c stm32_spi.c stm32_dma_alloc.c ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += stm32_appinitialize.c endif +ifeq ($(CONFIG_STM32F7_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_STM32F7_SDMMC1),y) +CSRCS += stm32_sdmmc.c +endif + include $(TOPDIR)/configs/Board.mk diff --git a/configs/stm32f746-ws/src/stm32_appinitialize.c b/configs/stm32f746-ws/src/stm32_appinitialize.c index 734e35957a..689bea75fe 100644 --- a/configs/stm32f746-ws/src/stm32_appinitialize.c +++ b/configs/stm32f746-ws/src/stm32_appinitialize.c @@ -93,5 +93,23 @@ int board_app_initialize(void) stm32_i2ctool(); +#if defined(CONFIG_FAT_DMAMEMORY) + if (stm32_dma_alloc_init() < 0) + { + syslog(LOG_ERR, "DMA alloc FAILED"); + } +#endif + + /* Initialize the SDIO block driver */ + + int ret = OK; + + ret = stm32_sdio_initialize(); + if (ret != OK) + { + ferr("ERROR: Failed to initialize MMC/SD driver: %d\n", ret); + return ret; + } + return OK; } diff --git a/configs/stm32f746-ws/src/stm32_dma_alloc.c b/configs/stm32f746-ws/src/stm32_dma_alloc.c new file mode 100644 index 0000000000..e6d2744529 --- /dev/null +++ b/configs/stm32f746-ws/src/stm32_dma_alloc.c @@ -0,0 +1,117 @@ +/**************************************************************************** + * configs/nucleo-144/stc/stm32_dma_alloc.c + * + * Copyright (C) 2016 PX4 Development Team. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name PX4 nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include +#include +#include +#include + +#include "stm32f746-ws.h" + +#if defined(CONFIG_FAT_DMAMEMORY) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#if !defined(CONFIG_GRAN) +# error microSD DMA support requires CONFIG_GRAN +#endif + +#define BOARD_DMA_ALLOC_POOL_SIZE (8*512) + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +static GRAN_HANDLE dma_allocator; + +/* The DMA heap size constrains the total number of things that can be + * ready to do DMA at a time. + * + * For example, FAT DMA depends on one sector-sized buffer per filesystem plus + * one sector-sized buffer per file. + * + * We use a fundamental alignment / granule size of 64B; this is sufficient + * to guarantee alignment for the largest STM32 DMA burst (16 beats x 32bits). + */ + +static uint8_t g_dma_heap[BOARD_DMA_ALLOC_POOL_SIZE] __attribute__((aligned(64))); + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_dma_alloc_init + * + * Description: + * All boards may optionally provide this API to instantiate a pool of + * memory for uses with FAST FS DMA operations. + * + ************************************************************************************/ + +int stm32_dma_alloc_init(void) +{ + dma_allocator = gran_initialize(g_dma_heap, + sizeof(g_dma_heap), + 7, /* 128B granule - must be > alignment (XXX bug?) */ + 6); /* 64B alignment */ + + if (dma_allocator == NULL) + { + return -ENOMEM; + } + + return OK; +} + +/* DMA-aware allocator stubs for the FAT filesystem. */ + +void *fat_dma_alloc(size_t size) +{ + return gran_alloc(dma_allocator, size); +} + +void fat_dma_free(FAR void *memory, size_t size) +{ + gran_free(dma_allocator, memory, size); +} + +#endif /* CONFIG_FAT_DMAMEMORY */ diff --git a/configs/stm32f746-ws/src/stm32_sdmmc.c b/configs/stm32f746-ws/src/stm32_sdmmc.c new file mode 100644 index 0000000000..bdbe7a7f65 --- /dev/null +++ b/configs/stm32f746-ws/src/stm32_sdmmc.c @@ -0,0 +1,171 @@ +/**************************************************************************** + * config/stm32f746-ws/src/stm32_sdio.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "stm32_sdmmc.h" +#include "stm32f746-ws.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +/* Card detections requires card support and a card detection GPIO */ + +#define HAVE_NCD 1 +#if !defined(HAVE_SDIO) || !defined(GPIO_SDIO_NCD) +# undef HAVE_NCD +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static FAR struct sdio_dev_s *g_sdio_dev; +#ifdef HAVE_NCD +static bool g_sd_inserted = 0xff; /* Impossible value */ +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_ncd_interrupt + * + * Description: + * Card detect interrupt handler. + * + ****************************************************************************/ + +#ifdef HAVE_NCD +static int stm32_ncd_interrupt(int irq, FAR void *context) +{ + bool present; + + present = !stm32_gpioread(GPIO_SDIO_NCD); + if (present != g_sd_inserted) + { + sdio_mediachange(g_sdio_dev, present); + g_sd_inserted = present; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdio_initialize + * + * Description: + * Initialize SDIO-based MMC/SD card support + * + ****************************************************************************/ + +int stm32_sdio_initialize(void) +{ + int ret; + +#ifdef HAVE_NCD + /* Card detect */ + + bool cd_status; + + /* Configure the card detect GPIO */ + + stm32_configgpio(GPIO_SDIO_NCD); + + /* Register an interrupt handler for the card detect pin */ + + stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, stm32_ncd_interrupt); +#endif + + /* Mount the SDIO-based MMC/SD block driver */ + /* First, get an instance of the SDIO interface */ + + finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); + + g_sdio_dev = sdio_initialize(SDIO_SLOTNO); + if (!g_sdio_dev) + { + ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); + + ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); + if (ret != OK) + { + ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return ret; + } + + finfo("Successfully bound SDIO to the MMC/SD driver\n"); + +#ifdef HAVE_NCD + /* Use SD card detect pin to check if a card is g_sd_inserted */ + + cd_status = !stm32_gpioread(GPIO_SDIO_NCD); + finfo("Card detect : %d\n", cd_status); + + sdio_mediachange(g_sdio_dev, cd_status); +#else + /* Assume that the SD card is inserted. What choice do we have? */ + + sdio_mediachange(g_sdio_dev, true); +#endif + + return OK; +} diff --git a/configs/stm32f746-ws/src/stm32_usb.c b/configs/stm32f746-ws/src/stm32_usb.c new file mode 100644 index 0000000000..b81aacd6ca --- /dev/null +++ b/configs/stm32f746-ws/src/stm32_usb.c @@ -0,0 +1,340 @@ +/************************************************************************************ + * configs/stm32f4discovery/src/stm32_usb.c + * + * Copyright (C) 2012-2013, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "up_arch.h" +#include "stm32_otg.h" +#include "stm32_gpio.h" +#include "stm32f746-ws.h" + +#ifdef CONFIG_STM32F7_OTGFS + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32F7_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_STM32F7F4DISCO_USBHOST_PRIO +# define CONFIG_STM32F7F4DISCO_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_STM32F7F4DISCO_USBHOST_STACKSIZE +# define CONFIG_STM32F7F4DISCO_USBHOST_STACKSIZE 1024 +#endif + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ************************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (;;) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + (void)CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in inialization to setup USB-related + * GPIO pins for the STM32F4Discovery board. + * + ************************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. No GPIO configuration is required */ + + /* Configure the OTG FS VBUS sensing GPIO, Power On, and Overcurrent GPIOs */ + +#ifdef CONFIG_STM32F7_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + +#ifdef CONFIG_USBHOST + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif + +#endif +} + +/*********************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ***********************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int pid; +#if defined(CONFIG_USBHOST_HUB) || defined(CONFIG_USBHOST_MSC) || \ + defined(CONFIG_USBHOST_HIDKBD) || defined(CONFIG_USBHOST_HIDMOUSE) + int ret; +#endif + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + pid = task_create("usbhost", CONFIG_STM32F7F4DISCO_USBHOST_PRIO, + CONFIG_STM32F7F4DISCO_USBHOST_STACKSIZE, + (main_t)usbhost_waiter, (FAR char * const *)NULL); + return pid < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/*********************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be provided be + * each platform that implements the STM32 OTG FS host interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a charge pump + * or, if 5 V are available on the application board, a basic power switch, must + * be added externally to drive the 5 V VBUS line. The external charge pump can + * be driven by any GPIO output. When the application decides to power on VBUS + * using the chosen GPIO, it must also set the port power bit in the host port + * control and status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, and the core + * clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ***********************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/************************************************************************************ + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent condition is + * detected. + * + * Input Parameter: + * handler - New overcurrent interrupt handler + * + * Returned value: + * Old overcurrent interrupt handler + * + ************************************************************************************/ + +#ifdef CONFIG_USBHOST +xcpt_t stm32_setup_overcurrent(xcpt_t handler) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler); +} +#endif + +/************************************************************************************ + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is + * used. This function is called whenever the USB enters or leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, etc. + * while the USB is suspended. + * + ************************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume) +{ + ullinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32F7_OTGFS */ diff --git a/configs/stm32f746-ws/src/stm32f746-ws.h b/configs/stm32f746-ws/src/stm32f746-ws.h index 07d2c6c11f..0a61a7b162 100644 --- a/configs/stm32f746-ws/src/stm32f746-ws.h +++ b/configs/stm32f746-ws/src/stm32f746-ws.h @@ -82,6 +82,12 @@ #define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | GPIO_PIN13) +#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|\ + GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9) + +#define SDIO_SLOTNO 0 +#define SDIO_MINOR 0 + /**************************************************************************************************** * Public data ****************************************************************************************************/ @@ -102,5 +108,32 @@ void weak_function stm32_spidev_initialize(void); + /**************************************************************************** + * Name: stm32_sdio_initialize + * + * Description: + * Initialize SDIO-based MMC/SD card support + * + ****************************************************************************/ + + #if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32F7_SDMMC1) + int stm32_sdio_initialize(void); + #endif + + /************************************************************************************ + * Name: stm32_dma_alloc_init + * + * Description: + * Called to create a FAT DMA allocator + * + * Returned Value: + * 0 on success or -ENOMEM + * + ************************************************************************************/ + + #if defined (CONFIG_FAT_DMAMEMORY) + int stm32_dma_alloc_init(void); + #endif + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_STM32F746_WS_SRC_STM32F746_WS_H */ -- GitLab From 495e475357d8cf0e2219b116ee5fc935d108b216 Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Mon, 20 Jun 2016 10:55:38 +0200 Subject: [PATCH 004/734] ignore CRC for SD_CMD55 --- arch/arm/src/stm32f7/stm32_sdmmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index 4f2b7a8d01..c1eb3542d7 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -2093,7 +2093,7 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t else #endif { - /* Check if a timeout or CRC error occurred */ + /* Check if a timeout or CRC error occurred (not for SD_CMD55 - see ERRATA) */ regval = getreg32(STM32_SDMMC1_STA); if ((regval & SDIO_STA_CTIMEOUT) != 0) @@ -2101,7 +2101,7 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t ferr("ERROR: Command timeout: %08x\n", regval); ret = -ETIMEDOUT; } - else if ((regval & SDIO_STA_CCRCFAIL) != 0) + else if (cmd != SD_CMD55 && (regval & SDIO_STA_CCRCFAIL) != 0) { ferr("ERROR: CRC failure: %08x\n", regval); ret = -EIO; -- GitLab From e70ac97cef06b86b54af3e2c199b40695b8874b3 Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Tue, 21 Jun 2016 13:17:50 +0200 Subject: [PATCH 005/734] should be cmd5 not cmd55 --- arch/arm/src/stm32f7/stm32_sdmmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index c1eb3542d7..4f2b7a8d01 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -2093,7 +2093,7 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t else #endif { - /* Check if a timeout or CRC error occurred (not for SD_CMD55 - see ERRATA) */ + /* Check if a timeout or CRC error occurred */ regval = getreg32(STM32_SDMMC1_STA); if ((regval & SDIO_STA_CTIMEOUT) != 0) @@ -2101,7 +2101,7 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t ferr("ERROR: Command timeout: %08x\n", regval); ret = -ETIMEDOUT; } - else if (cmd != SD_CMD55 && (regval & SDIO_STA_CCRCFAIL) != 0) + else if ((regval & SDIO_STA_CCRCFAIL) != 0) { ferr("ERROR: CRC failure: %08x\n", regval); ret = -EIO; -- GitLab From bdfd3e824834b1faf47ffcb5b32a8a2bed202617 Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Tue, 21 Jun 2016 14:02:53 +0200 Subject: [PATCH 006/734] flush cache before setup --- arch/arm/src/stm32f7/stm32_sdmmc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index 4f2b7a8d01..dbeb880f93 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -2694,6 +2694,10 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, stm32_sampleinit(); stm32_sample(priv, SAMPLENDX_BEFORE_SETUP); + /* Flush cache to physical memory */ + + arch_flush_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); + /* Save the source buffer information for use by the interrupt handler */ priv->buffer = (uint32_t *)buffer; @@ -2712,10 +2716,6 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, stm32_sample(priv, SAMPLENDX_BEFORE_ENABLE); - /* Flush cache to physical memory */ - - arch_flush_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); - /* Start the DMA */ stm32_dmastart(priv->dma, stm32_dmacallback, priv, false); -- GitLab From 0369bbff508bf93fad3413e839f7c7e33ecb9a9d Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Wed, 22 Jun 2016 10:54:06 +0200 Subject: [PATCH 007/734] styling --- arch/arm/src/stm32f7/chip/stm32_sdmmc.h | 4 ++-- arch/arm/src/stm32f7/chip/stm32f74xx75xx_sdmmc.h | 4 ++-- arch/arm/src/stm32f7/stm32_sdmmc.c | 2 +- arch/arm/src/stm32f7/stm32_sdmmc.h | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/src/stm32f7/chip/stm32_sdmmc.h b/arch/arm/src/stm32f7/chip/stm32_sdmmc.h index e04bdddc1e..10ed29f238 100644 --- a/arch/arm/src/stm32f7/chip/stm32_sdmmc.h +++ b/arch/arm/src/stm32f7/chip/stm32_sdmmc.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/stm32f7/chip/stm32_i2c.h + * arch/arm/src/stm32f7/chip/stm32_sdmmc.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_sdmmc.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_sdmmc.h index f710aed6d1..117c4da2fa 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_sdmmc.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_sdmmc.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/stm32f7/chip/stm32_sdio.h + * arch/arm/src/stm32f7/chip/stm32_sdmmc.h * - * Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2011-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index dbeb880f93..16473094b5 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f7/stm32_sdio.c + * arch/arm/src/stm32f7/stm32_sdmmc.c * * Copyright (C) 2009, 2011-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.h b/arch/arm/src/stm32f7/stm32_sdmmc.h index 18e6c44601..12b6348559 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.h +++ b/arch/arm/src/stm32f7/stm32_sdmmc.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/stm32f7/stm32_sdio.h + * arch/arm/src/stm32f7/stm32_sdmmc.h * - * Copyright (C) 2009, 2011, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without -- GitLab From 47a5f81a63bb408f691550283c844bd6f86c0c83 Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Sat, 25 Jun 2016 17:55:33 +0200 Subject: [PATCH 008/734] mmc1 --- configs/stm32f746-ws/src/stm32_appinitialize.c | 2 ++ configs/stm32f746-ws/src/stm32_sdmmc.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/stm32f746-ws/src/stm32_appinitialize.c b/configs/stm32f746-ws/src/stm32_appinitialize.c index 689bea75fe..0a58e61e36 100644 --- a/configs/stm32f746-ws/src/stm32_appinitialize.c +++ b/configs/stm32f746-ws/src/stm32_appinitialize.c @@ -100,6 +100,7 @@ int board_app_initialize(void) } #endif +#ifdef CONFIG_STM32F7_SDMMC1 /* Initialize the SDIO block driver */ int ret = OK; @@ -110,6 +111,7 @@ int board_app_initialize(void) ferr("ERROR: Failed to initialize MMC/SD driver: %d\n", ret); return ret; } +#endif return OK; } diff --git a/configs/stm32f746-ws/src/stm32_sdmmc.c b/configs/stm32f746-ws/src/stm32_sdmmc.c index bdbe7a7f65..4169d511a2 100644 --- a/configs/stm32f746-ws/src/stm32_sdmmc.c +++ b/configs/stm32f746-ws/src/stm32_sdmmc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * config/stm32f746-ws/src/stm32_sdio.c + * config/stm32f746-ws/src/stm32_sdmmc.c * * Copyright (C) 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt -- GitLab From 2723de9a09a1a16d1135afef193308dd27a11cff Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Sat, 25 Jun 2016 18:31:37 +0200 Subject: [PATCH 009/734] usb ep 0-8 --- arch/arm/src/stm32f7/chip/stm32_otg.h | 148 --------------------- arch/arm/src/stm32f7/stm32_otg.h | 6 +- arch/arm/src/stm32f7/stm32_otgdev.c | 182 +++++++++++++++++++------- configs/stm32f746-ws/nsh/defconfig | 56 ++++---- 4 files changed, 170 insertions(+), 222 deletions(-) diff --git a/arch/arm/src/stm32f7/chip/stm32_otg.h b/arch/arm/src/stm32f7/chip/stm32_otg.h index ee06497102..474d063026 100644 --- a/arch/arm/src/stm32f7/chip/stm32_otg.h +++ b/arch/arm/src/stm32f7/chip/stm32_otg.h @@ -78,9 +78,6 @@ #define STM32_OTG_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ #define STM32_OTG_DIEPTXF_OFFSET(n) (104+(((n)-1) << 2)) -#define STM32_OTG_DIEPTXF1_OFFSET 0x0104 /* Device IN endpoint transmit FIFO1 size register */ -#define STM32_OTG_DIEPTXF2_OFFSET 0x0108 /* Device IN endpoint transmit FIFO2 size register */ -#define STM32_OTG_DIEPTXF3_OFFSET 0x010c /* Device IN endpoint transmit FIFO3 size register */ /* Host-mode control and status registers */ @@ -99,44 +96,12 @@ #define STM32_OTG_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ #define STM32_OTG_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) -#define STM32_OTG_HCCHAR0_OFFSET 0x0500 /* Host channel-0 characteristics register */ -#define STM32_OTG_HCCHAR1_OFFSET 0x0520 /* Host channel-1 characteristics register */ -#define STM32_OTG_HCCHAR2_OFFSET 0x0540 /* Host channel-2 characteristics register */ -#define STM32_OTG_HCCHAR3_OFFSET 0x0560 /* Host channel-3 characteristics register */ -#define STM32_OTG_HCCHAR4_OFFSET 0x0580 /* Host channel-4 characteristics register */ -#define STM32_OTG_HCCHAR5_OFFSET 0x05a0 /* Host channel-5 characteristics register */ -#define STM32_OTG_HCCHAR6_OFFSET 0x05c0 /* Host channel-6 characteristics register */ -#define STM32_OTG_HCCHAR7_OFFSET 0x05e0 /* Host channel-7 characteristics register */ #define STM32_OTG_HCINT_OFFSET(n) (0x508 + ((n) << 5)) -#define STM32_OTG_HCINT0_OFFSET 0x0508 /* Host channel-0 interrupt register */ -#define STM32_OTG_HCINT1_OFFSET 0x0528 /* Host channel-1 interrupt register */ -#define STM32_OTG_HCINT2_OFFSET 0x0548 /* Host channel-2 interrupt register */ -#define STM32_OTG_HCINT3_OFFSET 0x0568 /* Host channel-3 interrupt register */ -#define STM32_OTG_HCINT4_OFFSET 0x0588 /* Host channel-4 interrupt register */ -#define STM32_OTG_HCINT5_OFFSET 0x05a8 /* Host channel-5 interrupt register */ -#define STM32_OTG_HCINT6_OFFSET 0x05c8 /* Host channel-6 interrupt register */ -#define STM32_OTG_HCINT7_OFFSET 0x05e8 /* Host channel-7 interrupt register */ #define STM32_OTG_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) -#define STM32_OTG_HCINTMSK0_OFFSET 0x050c /* Host channel-0 interrupt mask register */ -#define STM32_OTG_HCINTMSK1_OFFSET 0x052c /* Host channel-1 interrupt mask register */ -#define STM32_OTG_HCINTMSK2_OFFSET 0x054c /* Host channel-2 interrupt mask register */ -#define STM32_OTG_HCINTMSK3_OFFSET 0x056c /* Host channel-3 interrupt mask register */ -#define STM32_OTG_HCINTMSK4_OFFSET 0x058c /* Host channel-4 interrupt mask register */ -#define STM32_OTG_HCINTMSK5_OFFSET 0x05ac /* Host channel-5 interrupt mask register */ -#define STM32_OTG_HCINTMSK6_OFFSET 0x05cc /* Host channel-6 interrupt mask register */ -#define STM32_OTG_HCINTMSK7_OFFSET 0x05ec /* Host channel-7 interrupt mask register */ #define STM32_OTG_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) -#define STM32_OTG_HCTSIZ0_OFFSET 0x0510 /* Host channel-0 interrupt register */ -#define STM32_OTG_HCTSIZ1_OFFSET 0x0530 /* Host channel-1 interrupt register */ -#define STM32_OTG_HCTSIZ2_OFFSET 0x0550 /* Host channel-2 interrupt register */ -#define STM32_OTG_HCTSIZ3_OFFSET 0x0570 /* Host channel-3 interrupt register */ -#define STM32_OTG_HCTSIZ4_OFFSET 0x0590 /* Host channel-4 interrupt register */ -#define STM32_OTG_HCTSIZ5_OFFSET 0x05b0 /* Host channel-5 interrupt register */ -#define STM32_OTG_HCTSIZ6_OFFSET 0x05d0 /* Host channel-6 interrupt register */ -#define STM32_OTG_HCTSIZ7_OFFSET 0x05f0 /* Host channel-7 interrupt register */ /* Device-mode control and status registers */ @@ -158,50 +123,22 @@ #define STM32_OTG_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ #define STM32_OTG_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32_OTG_DIEPCTL0_OFFSET 0x0900 /* Device control IN endpoint 0 control register */ -#define STM32_OTG_DIEPCTL1_OFFSET 0x0920 /* Device control IN endpoint 2 control register */ -#define STM32_OTG_DIEPCTL2_OFFSET 0x0940 /* Device control IN endpoint 3 control register */ -#define STM32_OTG_DIEPCTL3_OFFSET 0x0960 /* Device control IN endpoint 4 control register */ #define STM32_OTG_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) -#define STM32_OTG_DIEPINT0_OFFSET 0x0908 /* Device endpoint-0 interrupt register */ -#define STM32_OTG_DIEPINT1_OFFSET 0x0928 /* Device endpoint-1 interrupt register */ -#define STM32_OTG_DIEPINT2_OFFSET 0x0948 /* Device endpoint-2 interrupt register */ -#define STM32_OTG_DIEPINT3_OFFSET 0x0968 /* Device endpoint-3 interrupt register */ #define STM32_OTG_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) -#define STM32_OTG_DIEPTSIZ0_OFFSET 0x0910 /* Device IN endpoint 0 transfer size register */ -#define STM32_OTG_DIEPTSIZ1_OFFSET 0x0930 /* Device IN endpoint 1 transfer size register */ -#define STM32_OTG_DIEPTSIZ2_OFFSET 0x0950 /* Device IN endpoint 2 transfer size register */ -#define STM32_OTG_DIEPTSIZ3_OFFSET 0x0970 /* Device IN endpoint 3 transfer size register */ #define STM32_OTG_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) -#define STM32_OTG_DTXFSTS0_OFFSET 0x0918 /* Device OUT endpoint-0 TxFIFO status register */ -#define STM32_OTG_DTXFSTS1_OFFSET 0x0938 /* Device OUT endpoint-1 TxFIFO status register */ -#define STM32_OTG_DTXFSTS2_OFFSET 0x0958 /* Device OUT endpoint-2 TxFIFO status register */ -#define STM32_OTG_DTXFSTS3_OFFSET 0x0978 /* Device OUT endpoint-3 TxFIFO status register */ #define STM32_OTG_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) #define STM32_OTG_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ #define STM32_OTG_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ #define STM32_OTG_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32_OTG_DOEPCTL0_OFFSET 0x00b00 /* Device OUT endpoint 0 control register */ -#define STM32_OTG_DOEPCTL1_OFFSET 0x00b20 /* Device OUT endpoint 1 control register */ -#define STM32_OTG_DOEPCTL2_OFFSET 0x00b40 /* Device OUT endpoint 2 control register */ -#define STM32_OTG_DOEPCTL3_OFFSET 0x00b60 /* Device OUT endpoint 3 control register */ #define STM32_OTG_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) -#define STM32_OTG_DOEPINT0_OFFSET 0x00b08 /* Device endpoint-0 interrupt register */ -#define STM32_OTG_DOEPINT1_OFFSET 0x00b28 /* Device endpoint-1 interrupt register */ -#define STM32_OTG_DOEPINT2_OFFSET 0x00b48 /* Device endpoint-2 interrupt register */ -#define STM32_OTG_DOEPINT3_OFFSET 0x00b68 /* Device endpoint-3 interrupt register */ #define STM32_OTG_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) -#define STM32_OTG_DOEPTSIZ0_OFFSET 0x00b10 /* Device OUT endpoint-0 transfer size register */ -#define STM32_OTG_DOEPTSIZ1_OFFSET 0x00b30 /* Device OUT endpoint-1 transfer size register */ -#define STM32_OTG_DOEPTSIZ2_OFFSET 0x00b50 /* Device OUT endpoint-2 transfer size register */ -#define STM32_OTG_DOEPTSIZ3_OFFSET 0x00b70 /* Device OUT endpoint-3 transfer size register */ /* Power and clock gating registers */ @@ -212,17 +149,6 @@ #define STM32_OTG_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) #define STM32_OTG_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) -#define STM32_OTG_DFIFO_DEP0_OFFSET 0x1000 /* 0x1000-0x1ffc Device IN/OUT Endpoint 0 DFIFO Write/Read Access */ -#define STM32_OTG_DFIFO_HCH0_OFFSET 0x1000 /* 0x1000-0x1ffc Host OUT/IN Channel 0 DFIFO Read/Write Access */ - -#define STM32_OTG_DFIFO_DEP1_OFFSET 0x2000 /* 0x2000-0x2ffc Device IN/OUT Endpoint 1 DFIFO Write/Read Access */ -#define STM32_OTG_DFIFO_HCH1_OFFSET 0x2000 /* 0x2000-0x2ffc Host OUT/IN Channel 1 DFIFO Read/Write Access */ - -#define STM32_OTG_DFIFO_DEP2_OFFSET 0x3000 /* 0x3000-0x3ffc Device IN/OUT Endpoint 2 DFIFO Write/Read Access */ -#define STM32_OTG_DFIFO_HCH2_OFFSET 0x3000 /* 0x3000-0x3ffc Host OUT/IN Channel 2 DFIFO Read/Write Access */ - -#define STM32_OTG_DFIFO_DEP3_OFFSET 0x4000 /* 0x4000-0x4ffc Device IN/OUT Endpoint 3 DFIFO Write/Read Access */ -#define STM32_OTG_DFIFO_HCH3_OFFSET 0x4000 /* 0x4000-0x4ffc Host OUT/IN Channel 3 DFIFO Read/Write Access */ /* Register Addresses *******************************************************************************/ @@ -244,9 +170,6 @@ #define STM32_OTG_HPTXFSIZ (STM32_OTG_BASE+STM32_OTG_HPTXFSIZ_OFFSET) #define STM32_OTG_DIEPTXF(n) (STM32_OTG_BASE+STM32_OTG_DIEPTXF_OFFSET(n)) -#define STM32_OTG_DIEPTXF1 (STM32_OTG_BASE+STM32_OTG_DIEPTXF1_OFFSET) -#define STM32_OTG_DIEPTXF2 (STM32_OTG_BASE+STM32_OTG_DIEPTXF2_OFFSET) -#define STM32_OTG_DIEPTXF3 (STM32_OTG_BASE+STM32_OTG_DIEPTXF3_OFFSET) /* Host-mode control and status registers */ @@ -261,44 +184,12 @@ #define STM32_OTG_CHAN(n) (STM32_OTG_BASE+STM32_OTG_CHAN_OFFSET(n)) #define STM32_OTG_HCCHAR(n) (STM32_OTG_BASE+STM32_OTG_HCCHAR_OFFSET(n)) -#define STM32_OTG_HCCHAR0 (STM32_OTG_BASE+STM32_OTG_HCCHAR0_OFFSET) -#define STM32_OTG_HCCHAR1 (STM32_OTG_BASE+STM32_OTG_HCCHAR1_OFFSET) -#define STM32_OTG_HCCHAR2 (STM32_OTG_BASE+STM32_OTG_HCCHAR2_OFFSET) -#define STM32_OTG_HCCHAR3 (STM32_OTG_BASE+STM32_OTG_HCCHAR3_OFFSET) -#define STM32_OTG_HCCHAR4 (STM32_OTG_BASE+STM32_OTG_HCCHAR4_OFFSET) -#define STM32_OTG_HCCHAR5 (STM32_OTG_BASE+STM32_OTG_HCCHAR5_OFFSET) -#define STM32_OTG_HCCHAR6 (STM32_OTG_BASE+STM32_OTG_HCCHAR6_OFFSET) -#define STM32_OTG_HCCHAR7 (STM32_OTG_BASE+STM32_OTG_HCCHAR7_OFFSET) #define STM32_OTG_HCINT(n) (STM32_OTG_BASE+STM32_OTG_HCINT_OFFSET(n)) -#define STM32_OTG_HCINT0 (STM32_OTG_BASE+STM32_OTG_HCINT0_OFFSET) -#define STM32_OTG_HCINT1 (STM32_OTG_BASE+STM32_OTG_HCINT1_OFFSET) -#define STM32_OTG_HCINT2 (STM32_OTG_BASE+STM32_OTG_HCINT2_OFFSET) -#define STM32_OTG_HCINT3 (STM32_OTG_BASE+STM32_OTG_HCINT3_OFFSET) -#define STM32_OTG_HCINT4 (STM32_OTG_BASE+STM32_OTG_HCINT4_OFFSET) -#define STM32_OTG_HCINT5 (STM32_OTG_BASE+STM32_OTG_HCINT5_OFFSET) -#define STM32_OTG_HCINT6 (STM32_OTG_BASE+STM32_OTG_HCINT6_OFFSET) -#define STM32_OTG_HCINT7 (STM32_OTG_BASE+STM32_OTG_HCINT7_OFFSET) #define STM32_OTG_HCINTMSK(n) (STM32_OTG_BASE+STM32_OTG_HCINTMSK_OFFSET(n)) -#define STM32_OTG_HCINTMSK0 (STM32_OTG_BASE+STM32_OTG_HCINTMSK0_OFFSET) -#define STM32_OTG_HCINTMSK1 (STM32_OTG_BASE+STM32_OTG_HCINTMSK1_OFFSET) -#define STM32_OTG_HCINTMSK2 (STM32_OTG_BASE+STM32_OTG_HCINTMSK2_OFFSET) -#define STM32_OTG_HCINTMSK3 (STM32_OTG_BASE+STM32_OTG_HCINTMSK3_OFFSET) -#define STM32_OTG_HCINTMSK4 (STM32_OTG_BASE+STM32_OTG_HCINTMSK4_OFFSET) -#define STM32_OTG_HCINTMSK5 (STM32_OTG_BASE+STM32_OTG_HCINTMSK5_OFFSET) -#define STM32_OTG_HCINTMSK6 (STM32_OTG_BASE+STM32_OTG_HCINTMSK6_OFFSET) -#define STM32_OTG_HCINTMSK7 (STM32_OTG_BASE+STM32_OTG_HCINTMSK7_OFFSET)_ #define STM32_OTG_HCTSIZ(n) (STM32_OTG_BASE+STM32_OTG_HCTSIZ_OFFSET(n)) -#define STM32_OTG_HCTSIZ0 (STM32_OTG_BASE+STM32_OTG_HCTSIZ0_OFFSET) -#define STM32_OTG_HCTSIZ1 (STM32_OTG_BASE+STM32_OTG_HCTSIZ1_OFFSET) -#define STM32_OTG_HCTSIZ2 (STM32_OTG_BASE+STM32_OTG_HCTSIZ2_OFFSET) -#define STM32_OTG_HCTSIZ3 (STM32_OTG_BASE+STM32_OTG_HCTSIZ3_OFFSET) -#define STM32_OTG_HCTSIZ4 (STM32_OTG_BASE+STM32_OTG_HCTSIZ4_OFFSET) -#define STM32_OTG_HCTSIZ5 (STM32_OTG_BASE+STM32_OTG_HCTSIZ5_OFFSET) -#define STM32_OTG_HCTSIZ6 (STM32_OTG_BASE+STM32_OTG_HCTSIZ6_OFFSET) -#define STM32_OTG_HCTSIZ7 (STM32_OTG_BASE+STM32_OTG_HCTSIZ7_OFFSET) /* Device-mode control and status registers */ @@ -316,48 +207,20 @@ #define STM32_OTG_DIEP(n) (STM32_OTG_BASE+STM32_OTG_DIEP_OFFSET(n)) #define STM32_OTG_DIEPCTL(n) (STM32_OTG_BASE+STM32_OTG_DIEPCTL_OFFSET(n)) -#define STM32_OTG_DIEPCTL0 (STM32_OTG_BASE+STM32_OTG_DIEPCTL0_OFFSET) -#define STM32_OTG_DIEPCTL1 (STM32_OTG_BASE+STM32_OTG_DIEPCTL1_OFFSET) -#define STM32_OTG_DIEPCTL2 (STM32_OTG_BASE+STM32_OTG_DIEPCTL2_OFFSET) -#define STM32_OTG_DIEPCTL3 (STM32_OTG_BASE+STM32_OTG_DIEPCTL3_OFFSET) #define STM32_OTG_DIEPINT(n) (STM32_OTG_BASE+STM32_OTG_DIEPINT_OFFSET(n)) -#define STM32_OTG_DIEPINT0 (STM32_OTG_BASE+STM32_OTG_DIEPINT0_OFFSET) -#define STM32_OTG_DIEPINT1 (STM32_OTG_BASE+STM32_OTG_DIEPINT1_OFFSET) -#define STM32_OTG_DIEPINT2 (STM32_OTG_BASE+STM32_OTG_DIEPINT2_OFFSET) -#define STM32_OTG_DIEPINT3 (STM32_OTG_BASE+STM32_OTG_DIEPINT3_OFFSET) #define STM32_OTG_DIEPTSIZ(n) (STM32_OTG_BASE+STM32_OTG_DIEPTSIZ_OFFSET(n)) -#define STM32_OTG_DIEPTSIZ0 (STM32_OTG_BASE+STM32_OTG_DIEPTSIZ0_OFFSET) -#define STM32_OTG_DIEPTSIZ1 (STM32_OTG_BASE+STM32_OTG_DIEPTSIZ1_OFFSET) -#define STM32_OTG_DIEPTSIZ2 (STM32_OTG_BASE+STM32_OTG_DIEPTSIZ2_OFFSET) -#define STM32_OTG_DIEPTSIZ3 (STM32_OTG_BASE+STM32_OTG_DIEPTSIZ3_OFFSET) #define STM32_OTG_DTXFSTS(n) (STM32_OTG_BASE+STM32_OTG_DTXFSTS_OFFSET(n)) -#define STM32_OTG_DTXFSTS0 (STM32_OTG_BASE+STM32_OTG_DTXFSTS0_OFFSET) -#define STM32_OTG_DTXFSTS1 (STM32_OTG_BASE+STM32_OTG_DTXFSTS1_OFFSET) -#define STM32_OTG_DTXFSTS2 (STM32_OTG_BASE+STM32_OTG_DTXFSTS2_OFFSET) -#define STM32_OTG_DTXFSTS3 (STM32_OTG_BASE+STM32_OTG_DTXFSTS3_OFFSET) #define STM32_OTG_DOEP(n) (STM32_OTG_BASE+STM32_OTG_DOEP_OFFSET(n)) #define STM32_OTG_DOEPCTL(n) (STM32_OTG_BASE+STM32_OTG_DOEPCTL_OFFSET(n)) -#define STM32_OTG_DOEPCTL0 (STM32_OTG_BASE+STM32_OTG_DOEPCTL0_OFFSET) -#define STM32_OTG_DOEPCTL1 (STM32_OTG_BASE+STM32_OTG_DOEPCTL1_OFFSET) -#define STM32_OTG_DOEPCTL2 (STM32_OTG_BASE+STM32_OTG_DOEPCTL2_OFFSET) -#define STM32_OTG_DOEPCTL3 (STM32_OTG_BASE+STM32_OTG_DOEPCTL3_OFFSET) #define STM32_OTG_DOEPINT(n) (STM32_OTG_BASE+STM32_OTG_DOEPINT_OFFSET(n)) -#define STM32_OTG_DOEPINT0 (STM32_OTG_BASE+STM32_OTG_DOEPINT0_OFFSET) -#define STM32_OTG_DOEPINT1 (STM32_OTG_BASE+STM32_OTG_DOEPINT1_OFFSET) -#define STM32_OTG_DOEPINT2 (STM32_OTG_BASE+STM32_OTG_DOEPINT2_OFFSET) -#define STM32_OTG_DOEPINT3 (STM32_OTG_BASE+STM32_OTG_DOEPINT3_OFFSET) #define STM32_OTG_DOEPTSIZ(n) (STM32_OTG_BASE+STM32_OTG_DOEPTSIZ_OFFSET(n)) -#define STM32_OTG_DOEPTSIZ0 (STM32_OTG_BASE+STM32_OTG_DOEPTSIZ0_OFFSET) -#define STM32_OTG_DOEPTSIZ1 (STM32_OTG_BASE+STM32_OTG_DOEPTSIZ1_OFFSET) -#define STM32_OTG_DOEPTSIZ2 (STM32_OTG_BASE+STM32_OTG_DOEPTSIZ2_OFFSET) -#define STM32_OTG_DOEPTSIZ3 (STM32_OTG_BASE+STM32_OTG_DOEPTSIZ3_OFFSET) /* Power and clock gating registers */ @@ -368,17 +231,6 @@ #define STM32_OTG_DFIFO_DEP(n) (STM32_OTG_BASE+STM32_OTG_DFIFO_DEP_OFFSET(n)) #define STM32_OTG_DFIFO_HCH(n) (STM32_OTG_BASE+STM32_OTG_DFIFO_HCH_OFFSET(n)) -#define STM32_OTG_DFIFO_DEP0 (STM32_OTG_BASE+STM32_OTG_DFIFO_DEP0_OFFSET) -#define STM32_OTG_DFIFO_HCH0 (STM32_OTG_BASE+STM32_OTG_DFIFO_HCH0_OFFSET) - -#define STM32_OTG_DFIFO_DEP1 (STM32_OTG_BASE+STM32_OTG_DFIFO_DEP1_OFFSET) -#define STM32_OTG_DFIFO_HCH1 (STM32_OTG_BASE+STM32_OTG_DFIFO_HCH1_OFFSET) - -#define STM32_OTG_DFIFO_DEP2 (STM32_OTG_BASE+STM32_OTG_DFIFO_DEP2_OFFSET) -#define STM32_OTG_DFIFO_HCH2 (STM32_OTG_BASE+STM32_OTG_DFIFO_HCH2_OFFSET) - -#define STM32_OTG_DFIFO_DEP3 (STM32_OTG_BASE+STM32_OTG_DFIFO_DEP3_OFFSET) -#define STM32_OTG_DFIFO_HCH3 (STM32_OTG_BASE+STM32_OTG_DFIFO_HCH3_OFFSET) /* Register Bitfield Definitions ********************************************************************/ /* Core global control and status registers */ diff --git a/arch/arm/src/stm32f7/stm32_otg.h b/arch/arm/src/stm32f7/stm32_otg.h index 0bb6b9b393..3c60683ea3 100644 --- a/arch/arm/src/stm32f7/stm32_otg.h +++ b/arch/arm/src/stm32f7/stm32_otg.h @@ -66,18 +66,18 @@ # define GPIO_OTG_DP GPIO_OTGFS_DP # define GPIO_OTG_ID GPIO_OTGFS_ID # define GPIO_OTG_SOF GPIO_OTGFS_SOF - +# define STM32_OTG_FIFO_SIZE 1280 #endif #if defined(CONFIG_STM32F7_OTGHS) # define STM32_IRQ_OTG STM32_IRQ_OTGHS # define STM32_OTG_BASE STM32_USBOTGHS_BASE -# define STM32_NENDPOINTS (8) /* ep0-7 x 2 for IN and OUT */ +# define STM32_NENDPOINTS (7) /* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one bit for direction */ # define GPIO_OTG_DM GPIO_OTGHS_DM # define GPIO_OTG_DP GPIO_OTGHS_DP # define GPIO_OTG_ID GPIO_OTGHS_ID # define GPIO_OTG_SOF GPIO_OTGHS_SOF - +# define STM32_OTG_FIFO_SIZE 4096 #endif /************************************************************************************ diff --git a/arch/arm/src/stm32f7/stm32_otgdev.c b/arch/arm/src/stm32f7/stm32_otgdev.c index d4d46c4efb..7b9db010ad 100644 --- a/arch/arm/src/stm32f7/stm32_otgdev.c +++ b/arch/arm/src/stm32f7/stm32_otgdev.c @@ -89,30 +89,82 @@ */ #ifndef CONFIG_USBDEV_RXFIFO_SIZE -# define CONFIG_USBDEV_RXFIFO_SIZE 512 +# define CONFIG_USBDEV_RXFIFO_SIZE (STM32_OTG_FIFO_SIZE - STM32_OTG_FIFO_SIZE/4/2/STM32_NENDPOINTS*4*STM32_NENDPOINTS) #endif -#ifndef CONFIG_USBDEV_EP0_TXFIFO_SIZE -# define CONFIG_USBDEV_EP0_TXFIFO_SIZE 192 +#if STM32_NENDPOINTS > 0 +# ifndef CONFIG_USBDEV_EP0_TXFIFO_SIZE +# define CONFIG_USBDEV_EP0_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +#else +# define CONFIG_USBDEV_EP0_TXFIFO_SIZE 0 #endif -#ifndef CONFIG_USBDEV_EP1_TXFIFO_SIZE -# define CONFIG_USBDEV_EP1_TXFIFO_SIZE 192 +#if STM32_NENDPOINTS > 1 +# ifndef CONFIG_USBDEV_EP1_TXFIFO_SIZE +# define CONFIG_USBDEV_EP1_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +#else +# define CONFIG_USBDEV_EP1_TXFIFO_SIZE 0 #endif -#ifndef CONFIG_USBDEV_EP2_TXFIFO_SIZE -# define CONFIG_USBDEV_EP2_TXFIFO_SIZE 192 +#if STM32_NENDPOINTS > 2 +# ifndef CONFIG_USBDEV_EP2_TXFIFO_SIZE +# define CONFIG_USBDEV_EP2_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +#else +# define CONFIG_USBDEV_EP2_TXFIFO_SIZE 0 #endif -#ifndef CONFIG_USBDEV_EP3_TXFIFO_SIZE -# define CONFIG_USBDEV_EP3_TXFIFO_SIZE 192 +#if STM32_NENDPOINTS > 3 +# ifndef CONFIG_USBDEV_EP3_TXFIFO_SIZE +# define CONFIG_USBDEV_EP3_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +#else +# define CONFIG_USBDEV_EP3_TXFIFO_SIZE 0 #endif -#if (CONFIG_USBDEV_RXFIFO_SIZE + CONFIG_USBDEV_EP0_TXFIFO_SIZE + \ - CONFIG_USBDEV_EP2_TXFIFO_SIZE + CONFIG_USBDEV_EP3_TXFIFO_SIZE) > 1280 -# error "FIFO allocations exceed FIFO memory size" +#if STM32_NENDPOINTS > 4 +# ifndef CONFIG_USBDEV_EP4_TXFIFO_SIZE +# define CONFIG_USBDEV_EP4_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +#else +# define CONFIG_USBDEV_EP4_TXFIFO_SIZE 0 +#endif + +#if STM32_NENDPOINTS > 5 +# ifndef CONFIG_USBDEV_EP5_TXFIFO_SIZE +# define CONFIG_USBDEV_EP5_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +#else +# define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0 +#endif + +#if STM32_NENDPOINTS > 6 +# ifndef CONFIG_USBDEV_EP6_TXFIFO_SIZE +# define CONFIG_USBDEV_EP6_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +#else +# define CONFIG_USBDEV_EP6_TXFIFO_SIZE 0 +#endif + +#if STM32_NENDPOINTS > 7 +# ifndef CONFIG_USBDEV_EP7_TXFIFO_SIZE +# define CONFIG_USBDEV_EP7_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +#else +# define CONFIG_USBDEV_EP7_TXFIFO_SIZE 0 +#endif + +#if STM32_NENDPOINTS > 8 +# ifndef CONFIG_USBDEV_EP8_TXFIFO_SIZE +# define CONFIG_USBDEV_EP8_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +#else +# define CONFIG_USBDEV_EP8_TXFIFO_SIZE 0 #endif + /* The actual FIFO addresses that we use must be aligned to 4-byte boundaries; * FIFO sizes must be provided in units of 32-bit words. */ @@ -123,29 +175,36 @@ #define STM32_EP0_TXFIFO_BYTES ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) & ~3) #define STM32_EP0_TXFIFO_WORDS ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) >> 2) -#if STM32_EP0_TXFIFO_WORDS < 16 || STM32_EP0_TXFIFO_WORDS > 256 -# error "CONFIG_USBDEV_EP0_TXFIFO_SIZE is out of range" -#endif - #define STM32_EP1_TXFIFO_BYTES ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) & ~3) #define STM32_EP1_TXFIFO_WORDS ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) >> 2) -#if STM32_EP1_TXFIFO_WORDS < 16 -# error "CONFIG_USBDEV_EP1_TXFIFO_SIZE is out of range" -#endif - #define STM32_EP2_TXFIFO_BYTES ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) & ~3) #define STM32_EP2_TXFIFO_WORDS ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) >> 2) -#if STM32_EP2_TXFIFO_WORDS < 16 -# error "CONFIG_USBDEV_EP2_TXFIFO_SIZE is out of range" -#endif - #define STM32_EP3_TXFIFO_BYTES ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) & ~3) #define STM32_EP3_TXFIFO_WORDS ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) >> 2) -#if STM32_EP3_TXFIFO_WORDS < 16 -# error "CONFIG_USBDEV_EP3_TXFIFO_SIZE is out of range" +#define STM32_EP4_TXFIFO_BYTES ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP4_TXFIFO_WORDS ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) >> 2) + +#define STM32_EP5_TXFIFO_BYTES ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP5_TXFIFO_WORDS ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) >> 2) + +#define STM32_EP6_TXFIFO_BYTES ((CONFIG_USBDEV_EP6_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP6_TXFIFO_WORDS ((CONFIG_USBDEV_EP6_TXFIFO_SIZE + 3) >> 2) + +#define STM32_EP7_TXFIFO_BYTES ((CONFIG_USBDEV_EP7_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP7_TXFIFO_WORDS ((CONFIG_USBDEV_EP7_TXFIFO_SIZE + 3) >> 2) + +#define STM32_EP8_TXFIFO_BYTES ((CONFIG_USBDEV_EP8_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP8_TXFIFO_WORDS ((CONFIG_USBDEV_EP8_TXFIFO_SIZE + 3) >> 2) + + +#if (STM32_RXFIFO_BYTES + \ + STM32_EP0_TXFIFO_BYTES + STM32_EP1_TXFIFO_BYTES + STM32_EP2_TXFIFO_BYTES + STM32_EP3_TXFIFO_BYTES + \ + STM32_EP4_TXFIFO_BYTES + STM32_EP5_TXFIFO_BYTES + STM32_EP6_TXFIFO_BYTES + STM32_EP7_TXFIFO_BYTES + CONFIG_USBDEV_EP8_TXFIFO_SIZE \ + ) > STM32_OTG_FIFO_SIZE +# error "FIFO allocations exceed FIFO memory size" #endif /* Debug ***********************************************************************/ @@ -962,7 +1021,7 @@ static void stm32_ep0in_activate(void) /* Set the max packet size of the IN EP. */ - regval = stm32_getreg(STM32_OTG_DIEPCTL0); + regval = stm32_getreg(STM32_OTG_DIEPCTL(0)); regval &= ~OTG_DIEPCTL0_MPSIZ_MASK; #if CONFIG_USBDEV_EP0_MAXSIZE == 8 @@ -977,7 +1036,7 @@ static void stm32_ep0in_activate(void) # error "Unsupported value of CONFIG_USBDEV_EP0_MAXSIZE" #endif - stm32_putreg(regval, STM32_OTG_DIEPCTL0); + stm32_putreg(regval, STM32_OTG_DIEPCTL(0)); /* Clear global IN NAK */ @@ -1003,13 +1062,13 @@ static void stm32_ep0out_ctrlsetup(FAR struct stm32_usbdev_s *priv) regval = (USB_SIZEOF_CTRLREQ * 3 << OTG_DOEPTSIZ0_XFRSIZ_SHIFT) | (OTG_DOEPTSIZ0_PKTCNT) | (3 << OTG_DOEPTSIZ0_STUPCNT_SHIFT); - stm32_putreg(regval, STM32_OTG_DOEPTSIZ0); + stm32_putreg(regval, STM32_OTG_DOEPTSIZ(0)); /* Then clear NAKing and enable the transfer */ - regval = stm32_getreg(STM32_OTG_DOEPCTL0); + regval = stm32_getreg(STM32_OTG_DOEPCTL(0)); regval |= (OTG_DOEPCTL0_CNAK | OTG_DOEPCTL0_EPENA); - stm32_putreg(regval, STM32_OTG_DOEPCTL0); + stm32_putreg(regval, STM32_OTG_DOEPCTL(0)); } /**************************************************************************** @@ -3227,9 +3286,9 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) { /* Clear NAKSTS so that we can receive the data */ - regval = stm32_getreg(STM32_OTG_DOEPCTL0); + regval = stm32_getreg(STM32_OTG_DOEPCTL(0)); regval |= OTG_DOEPCTL0_CNAK; - stm32_putreg(regval, STM32_OTG_DOEPCTL0); + stm32_putreg(regval, STM32_OTG_DOEPCTL(0)); /* Wait for the data phase. */ @@ -5235,33 +5294,68 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) stm32_putreg(STM32_RXFIFO_WORDS, STM32_OTG_GRXFSIZ); - /* EP0 TX */ - +#if STM32_NENDPOINTS > 0 address = STM32_RXFIFO_WORDS; regval = (address << OTG_DIEPTXF0_TX0FD_SHIFT) | (STM32_EP0_TXFIFO_WORDS << OTG_DIEPTXF0_TX0FSA_SHIFT); stm32_putreg(regval, STM32_OTG_DIEPTXF0); +#endif - /* EP1 TX */ - +#if STM32_NENDPOINTS > 1 address += STM32_EP0_TXFIFO_WORDS; regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | (STM32_EP1_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); - stm32_putreg(regval, STM32_OTG_DIEPTXF1); - - /* EP2 TX */ + stm32_putreg(regval, STM32_OTG_DIEPTXF(1)); +#endif +#if STM32_NENDPOINTS > 2 address += STM32_EP1_TXFIFO_WORDS; regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | (STM32_EP2_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); - stm32_putreg(regval, STM32_OTG_DIEPTXF2); - - /* EP3 TX */ + stm32_putreg(regval, STM32_OTG_DIEPTXF(2)); +#endif +#if STM32_NENDPOINTS > 3 address += STM32_EP2_TXFIFO_WORDS; regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | (STM32_EP3_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); - stm32_putreg(regval, STM32_OTG_DIEPTXF3); + stm32_putreg(regval, STM32_OTG_DIEPTXF(3)); +#endif + +#if STM32_NENDPOINTS > 4 + address += STM32_EP3_TXFIFO_WORDS; + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP4_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTG_DIEPTXF(4)); +#endif + +#if STM32_NENDPOINTS > 5 + address += STM32_EP4_TXFIFO_WORDS; + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP5_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTG_DIEPTXF(5)); +#endif + +#if STM32_NENDPOINTS > 6 + address += STM32_EP5_TXFIFO_WORDS; + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP6_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTG_DIEPTXF(6)); +#endif + +#if STM32_NENDPOINTS > 7 + address += STM32_EP6_TXFIFO_WORDS; + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP7_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTG_DIEPTXF(7)); +#endif + +#if STM32_NENDPOINTS > 8 + address += STM32_EP7_TXFIFO_WORDS; + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP8_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTG_DIEPTXF(8)); +#endif /* Flush the FIFOs */ diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig index 44a25aec95..653cccf1e6 100644 --- a/configs/stm32f746-ws/nsh/defconfig +++ b/configs/stm32f746-ws/nsh/defconfig @@ -300,13 +300,13 @@ CONFIG_STM32F7_I2C1=y # CONFIG_STM32F7_I2C3 is not set # CONFIG_STM32F7_LPTIM1 is not set # CONFIG_STM32F7_LTDC is not set -##CONFIG_STM32F7_OTGFS=y +CONFIG_STM32F7_OTGFS=y # CONFIG_STM32F7_OTGHS is not set # CONFIG_STM32F7_QUADSPI is not set # CONFIG_STM32F7_RNG is not set # CONFIG_STM32F7_SAI1 is not set # CONFIG_STM32F7_SAI2 is not set -CONFIG_STM32F7_SDMMC1=y +##CONFIG_STM32F7_SDMMC1=y # CONFIG_STM32F7_SPDIFRX is not set CONFIG_STM32F7_SPI1=y # CONFIG_STM32F7_SPI2 is not set @@ -434,7 +434,7 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set -##CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARDCTL_USBDEVCTRL=y # # RTOS Features @@ -690,7 +690,7 @@ CONFIG_USART6_2STOP=0 # CONFIG_USART6_IFLOWCONTROL is not set # CONFIG_USART6_OFLOWCONTROL is not set # CONFIG_USART6_DMA is not set -##CONFIG_USBDEV=y +CONFIG_USBDEV=y # CONFIG_USBHOST is not set # CONFIG_DRIVERS_WIRELESS is not set @@ -700,9 +700,9 @@ CONFIG_USART6_2STOP=0 # # CONFIG_USBDEV_ISOCHRONOUS is not set # CONFIG_USBDEV_DUALSPEED is not set -##CONFIG_USBDEV_SELFPOWERED=y +CONFIG_USBDEV_SELFPOWERED=y # CONFIG_USBDEV_BUSPOWERED is not set -##CONFIG_USBDEV_MAXPOWER=100 +CONFIG_USBDEV_MAXPOWER=100 # CONFIG_USBDEV_DMA is not set # CONFIG_ARCH_USBDEV_STALLQUEUE is not set # CONFIG_USBDEV_TRACE is not set @@ -712,27 +712,26 @@ CONFIG_USART6_2STOP=0 # # CONFIG_USBDEV_COMPOSITE is not set # CONFIG_PL2303 is not set -##CONFIG_CDCACM=y -##CONFIG_CDCACM_CONSOLE=y -##CONFIG_CDCACM_EP0MAXPACKET=64 -##CONFIG_CDCACM_EPINTIN=1 -##CONFIG_CDCACM_EPINTIN_FSSIZE=64 -##CONFIG_CDCACM_EPINTIN_HSSIZE=64 -##CONFIG_CDCACM_EPBULKOUT=3 -##CONFIG_CDCACM_EPBULKOUT_FSSIZE=64 -##CONFIG_CDCACM_EPBULKOUT_HSSIZE=512 -##CONFIG_CDCACM_EPBULKIN=2 -##CONFIG_CDCACM_EPBULKIN_FSSIZE=64 -##CONFIG_CDCACM_EPBULKIN_HSSIZE=512 -##CONFIG_CDCACM_NRDREQS=4 -##CONFIG_CDCACM_NWRREQS=4 -##CONFIG_CDCACM_BULKIN_REQLEN=96 -##CONFIG_CDCACM_RXBUFSIZE=256 -##CONFIG_CDCACM_TXBUFSIZE=256 -##CONFIG_CDCACM_VENDORID=0x0525 -##CONFIG_CDCACM_PRODUCTID=0xa4a7 -##CONFIG_CDCACM_VENDORSTR="NuttX" -##CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial" +CONFIG_CDCACM=y +CONFIG_CDCACM_EP0MAXPACKET=64 +CONFIG_CDCACM_EPINTIN=1 +CONFIG_CDCACM_EPINTIN_FSSIZE=64 +CONFIG_CDCACM_EPINTIN_HSSIZE=64 +CONFIG_CDCACM_EPBULKOUT=2 +CONFIG_CDCACM_EPBULKOUT_FSSIZE=64 +CONFIG_CDCACM_EPBULKOUT_HSSIZE=512 +CONFIG_CDCACM_EPBULKIN=2 +CONFIG_CDCACM_EPBULKIN_FSSIZE=64 +CONFIG_CDCACM_EPBULKIN_HSSIZE=512 +CONFIG_CDCACM_NRDREQS=4 +CONFIG_CDCACM_NWRREQS=4 +CONFIG_CDCACM_BULKIN_REQLEN=96 +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_CDCACM_VENDORID=0x03EB +CONFIG_CDCACM_PRODUCTID=0x2044 +CONFIG_CDCACM_VENDORSTR="NuttX" +CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial" # CONFIG_USBMSC is not set # CONFIG_USBHOST is not set # CONFIG_DRIVERS_WIRELESS is not set @@ -1128,3 +1127,6 @@ CONFIG_READLINE_ECHO=y # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set + +CONFIG_SYSTEM_CDCACM=y +CONFIG_SYSTEM_CDCACM_DEVMINOR=0 -- GitLab From 1905cb94a09d9f1d7cb8e247691382f817277c00 Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Tue, 27 Sep 2016 16:43:41 +0200 Subject: [PATCH 010/734] to uinfo --- configs/stm32f746-ws/src/stm32_usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/stm32f746-ws/src/stm32_usb.c b/configs/stm32f746-ws/src/stm32_usb.c index b81aacd6ca..d0c118af89 100644 --- a/configs/stm32f746-ws/src/stm32_usb.c +++ b/configs/stm32f746-ws/src/stm32_usb.c @@ -333,7 +333,7 @@ xcpt_t stm32_setup_overcurrent(xcpt_t handler) #ifdef CONFIG_USBDEV void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume) { - ullinfo("resume: %d\n", resume); + uinfo("resume: %d\n", resume); } #endif -- GitLab From 9b7341b670194815d09713025c85cb2113b7d878 Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Tue, 27 Sep 2016 16:47:49 +0200 Subject: [PATCH 011/734] ignore eclipse .project --- .gitignore | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index 3ec700458d..839c74cb5e 100644 --- a/.gitignore +++ b/.gitignore @@ -28,3 +28,5 @@ cscope.out /*.hex /pcode /tags +.cproject +.project \ No newline at end of file -- GitLab From 1cbd7a0e5972ee6bf4d5fb04613de0278a494fd2 Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Fri, 30 Sep 2016 16:00:18 +0200 Subject: [PATCH 012/734] CONFIG_ARCH_IRQPRIO check --- arch/arm/src/stm32f7/stm32_sdmmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index 3e6aff9620..9fa8d00b07 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -113,7 +113,7 @@ #endif #ifdef CONFIG_STM32F7_SDMMC1 -# ifndef CONFIG_SDMMC1_PRI +# if defined(CONFIG_ARCH_IRQPRIO) && !defined(CONFIG_SDMMC1_PRI) # define CONFIG_SDMMC1_PRI NVIC_SYSH_PRIORITY_DEFAULT # endif @@ -130,7 +130,7 @@ #endif #ifdef CONFIG_STM32F7_SDMMC2 -# ifndef CONFIG_SDMMC2_PRI +# if defined(CONFIG_ARCH_IRQPRIO) && !defined(CONFIG_SDMMC2_PRI) # define CONFIG_SDMMC2_PRI NVIC_SYSH_PRIORITY_DEFAULT # endif -- GitLab From 4cb1ba493b64eb567e7b33261e4df18c15d55cfb Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Fri, 30 Sep 2016 16:00:28 +0200 Subject: [PATCH 013/734] mmc renames --- configs/stm32f746-ws/include/board.h | 10 +++++----- configs/stm32f746-ws/nsh/defconfig | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/configs/stm32f746-ws/include/board.h b/configs/stm32f746-ws/include/board.h index ea5072ce20..17ca38417e 100644 --- a/configs/stm32f746-ws/include/board.h +++ b/configs/stm32f746-ws/include/board.h @@ -274,16 +274,16 @@ * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz */ -#define SDMMC1_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) +#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) /* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz */ #ifdef CONFIG_SDIO_DMA -# define SDMMC1_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +# define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) #else -# define SDMMC1_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +# define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) #endif /* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz @@ -291,9 +291,9 @@ */ #ifdef CONFIG_SDIO_DMA -# define SDMMC1_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +# define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) #else -# define SDMMC1_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) #endif /************************************************************************************ diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig index c9598479e3..6fafd45558 100644 --- a/configs/stm32f746-ws/nsh/defconfig +++ b/configs/stm32f746-ws/nsh/defconfig @@ -312,7 +312,7 @@ CONFIG_STM32F7_OTGFS=y # CONFIG_STM32F7_RNG is not set # CONFIG_STM32F7_SAI1 is not set # CONFIG_STM32F7_SAI2 is not set -##CONFIG_STM32F7_SDMMC1=y +CONFIG_STM32F7_SDMMC1=y # CONFIG_STM32F7_SPDIFRX is not set CONFIG_STM32F7_SPI1=y # CONFIG_STM32F7_SPI2 is not set -- GitLab From fd1de920160304667a4edc9a4407486af9e3e90d Mon Sep 17 00:00:00 2001 From: Vytautas Lukenskas Date: Fri, 30 Sep 2016 07:45:39 -0600 Subject: [PATCH 014/734] There are some small problems in LPC43xx RS485 mode configuration. In particular: 1. UART0,2,3 do not have DTR pins (different from UART1), so, Kconfig needs to be adjusted. 2. lpc43_uart.c in RS485 mode only configures DIR pin, but doesn't enable pin output for UART0,2,3. 3. should be option to reverse DIR control pin output polarity. 4. lpc43xx/chip/lpc43_uart.h doesn't have USART3 definitions. NOTE: I didn't modified and didn't tested USART1, as it has different hardware. From Vytautas Lukenskas. --- arch/arm/src/lpc43xx/Kconfig | 31 +++++++--- arch/arm/src/lpc43xx/chip/lpc43_uart.h | 22 ++++++++ arch/arm/src/lpc43xx/lpc43_config.h | 3 - arch/arm/src/lpc43xx/lpc43_serial.c | 9 --- arch/arm/src/lpc43xx/lpc43_uart.c | 78 +++++++++++++++++++++++++- 5 files changed, 119 insertions(+), 24 deletions(-) diff --git a/arch/arm/src/lpc43xx/Kconfig b/arch/arm/src/lpc43xx/Kconfig index 80da35c00c..7c9a89c49d 100644 --- a/arch/arm/src/lpc43xx/Kconfig +++ b/arch/arm/src/lpc43xx/Kconfig @@ -638,11 +638,16 @@ config USART0_RS485MODE ---help--- Enable RS-485 interface on USART0. -config USART0_RS485_DTRDIR - bool "USART0 DTR for DIR" +if USART0_RS485_MODE + config USART0_RS485DIROIN + bool "Invert direction control pin polarity" default n ---help--- - Use the USART DTR pin for the DIR pin + If disabled, control pin will be driven to logic 0 when the + transmitter has data to be sent. It will be driven to logic 1 after + the last bit of data has been transmitted. + +endif # USART0_RS485MODE endif # LPC43_USART0 @@ -670,11 +675,15 @@ config USART2_RS485MODE ---help--- Enable RS-485 interface on USART2. -config USART2_RS485_DTRDIR - bool "USART2 DTR for DIR" +if USART2_RS485MODE + config USART0_RS485DIROIN + bool "Invert direction control pin polarity" default n ---help--- - Use the USART DTR pin for the DIR pin + If disabled, control pin will be driven to logic 0 when the transmitter has data to be sent. + It will be driven to logic 1 after the last bit of data has been transmitted. + +endif # USART2_RS485MODE endif # LPC43_USART2 @@ -686,11 +695,15 @@ config USART3_RS485MODE ---help--- Enable RS-485 interface on USART3. -config USART3_RS485_DTRDIR - bool "USART3 DTR for DIR" +if USART3_RS485MODE +config USART3_RS485DIROIN + bool "Invert direction control pin polarity" default n ---help--- - Use the USART DTR pin for the DIR pin + If disabled, control pin will be driven to logic 0 when the transmitter has data to be sent. + It will be driven to logic 1 after the last bit of data has been transmitted. + +endif # USART3_RS485MODE endif # LPC43_USART3 endmenu # RS-485 Configuration diff --git a/arch/arm/src/lpc43xx/chip/lpc43_uart.h b/arch/arm/src/lpc43xx/chip/lpc43_uart.h index a0ea29718a..de6944030e 100644 --- a/arch/arm/src/lpc43xx/chip/lpc43_uart.h +++ b/arch/arm/src/lpc43xx/chip/lpc43_uart.h @@ -168,6 +168,28 @@ #define LPC43_USART2_SYNCCTRL (LPC43_USART2_BASE+LPC43_USART_SYNCCTRL_OFFSET) #define LPC43_USART2_TER (LPC43_USART2_BASE+LPC43_USART_TER_OFFSET) +#define LPC43_USART3_RBR (LPC43_USART3_BASE+LPC43_UART_RBR_OFFSET) +#define LPC43_USART3_THR (LPC43_USART3_BASE+LPC43_UART_THR_OFFSET) +#define LPC43_USART3_DLL (LPC43_USART3_BASE+LPC43_UART_DLL_OFFSET) +#define LPC43_USART3_DLM (LPC43_USART3_BASE+LPC43_UART_DLM_OFFSET) +#define LPC43_USART3_IER (LPC43_USART3_BASE+LPC43_UART_IER_OFFSET) +#define LPC43_USART3_IIR (LPC43_USART3_BASE+LPC43_UART_IIR_OFFSET) +#define LPC43_USART3_FCR (LPC43_USART3_BASE+LPC43_UART_FCR_OFFSET) +#define LPC43_USART3_LCR (LPC43_USART3_BASE+LPC43_UART_LCR_OFFSET) +#define LPC43_USART3_LSR (LPC43_USART3_BASE+LPC43_UART_LSR_OFFSET) +#define LPC43_USART3_SCR (LPC43_USART3_BASE+LPC43_UART_SCR_OFFSET) +#define LPC43_USART3_ACR (LPC43_USART3_BASE+LPC43_UART_ACR_OFFSET) +#define LPC43_USART3_ICR (LPC43_USART3_BASE+LPC43_USART_ICR_OFFSET) +#define LPC43_USART3_FDR (LPC43_USART3_BASE+LPC43_UART_FDR_OFFSET) +#define LPC43_USART3_OSR (LPC43_USART3_BASE+LPC43_USART_OSR_OFFSET) +#define LPC43_USART3_HDEM (LPC43_USART3_BASE+LPC43_USART_HDEN_OFFSET) +#define LPC43_USART3_SCICTRL (LPC43_USART3_BASE+LPC43_USART_SCICTRL_OFFSET) +#define LPC43_USART3_RS485CTRL (LPC43_USART3_BASE+LPC43_UART_RS485CTRL_OFFSET) +#define LPC43_USART3_ADRMATCH (LPC43_USART3_BASE+LPC43_UART_ADRMATCH_OFFSET) +#define LPC43_USART3_RS485DLY (LPC43_USART3_BASE+LPC43_UART_RS485DLY_OFFSET) +#define LPC43_USART3_SYNCCTRL (LPC43_USART3_BASE+LPC43_USART_SYNCCTRL_OFFSET) +#define LPC43_USART3_TER (LPC43_USART3_BASE+LPC43_USART_TER_OFFSET) + /* Register bit definitions *****************************************************************/ /* RBR (DLAB =0) Receiver Buffer Register */ diff --git a/arch/arm/src/lpc43xx/lpc43_config.h b/arch/arm/src/lpc43xx/lpc43_config.h index 8a4509b8f0..528c900252 100644 --- a/arch/arm/src/lpc43xx/lpc43_config.h +++ b/arch/arm/src/lpc43xx/lpc43_config.h @@ -73,7 +73,6 @@ #ifndef CONFIG_LPC43_USART0 # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART0_RS485MODE -# undef CONFIG_USART0_RS485_DTRDIR #endif #ifndef CONFIG_LPC43_UART1 @@ -85,13 +84,11 @@ #ifndef CONFIG_LPC43_USART2 # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART2_RS485MODE -# undef CONFIG_USART2_RS485_DTRDIR #endif #ifndef CONFIG_LPC43_USART3 # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_USART3_RS485MODE -# undef CONFIG_USART3_RS485_DTRDIR #endif /* Is there a serial console? There should be at most one defined. It could be on diff --git a/arch/arm/src/lpc43xx/lpc43_serial.c b/arch/arm/src/lpc43xx/lpc43_serial.c index 82ec6d690e..3fa30e87e2 100644 --- a/arch/arm/src/lpc43xx/lpc43_serial.c +++ b/arch/arm/src/lpc43xx/lpc43_serial.c @@ -169,9 +169,6 @@ static struct up_dev_s g_uart0priv = .parity = CONFIG_USART0_PARITY, .bits = CONFIG_USART0_BITS, .stopbits2 = CONFIG_USART0_2STOP, -#if defined(CONFIG_USART0_RS485MODE) && defined(CONFIG_USART0_RS485_DTRDIR) - .dtrdir = true, -#endif }; static uart_dev_t g_uart0port = @@ -239,9 +236,6 @@ static struct up_dev_s g_uart2priv = .parity = CONFIG_USART2_PARITY, .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, -#if defined(CONFIG_USART2_RS485MODE) && defined(CONFIG_USART2_RS485_DTRDIR) - .dtrdir = true, -#endif }; static uart_dev_t g_uart2port = @@ -274,9 +268,6 @@ static struct up_dev_s g_uart3priv = .parity = CONFIG_USART3_PARITY, .bits = CONFIG_USART3_BITS, .stopbits2 = CONFIG_USART3_2STOP, -#if defined(CONFIG_USART3_RS485MODE) && defined(CONFIG_USART3_RS485_DTRDIR) - .dtrdir = true, -#endif }; static uart_dev_t g_uart3port = diff --git a/arch/arm/src/lpc43xx/lpc43_uart.c b/arch/arm/src/lpc43xx/lpc43_uart.c index 88d7950e6a..0aa983de90 100644 --- a/arch/arm/src/lpc43xx/lpc43_uart.c +++ b/arch/arm/src/lpc43xx/lpc43_uart.c @@ -364,7 +364,31 @@ void lpc43_usart0_setup(void) #ifdef CONFIG_USART0_RS485MODE lpc43_pin_config(PINCONF_U0_DIR); -#endif + + /* Enable direction output pin */ + + regval = getreg32(LPC43_USART0_RS485CTRL); + regval |= UART_RS485CTRL_DCTRL; + putreg32(regval, LPC43_USART0_RS485CTRL); + +#ifdef CONFIG_USART0_RS485DIROIN + + /* Invert direction control output pin polarity */ + + regval = getreg32(LPC43_USART0_RS485CTRL); + regval |= UART_RS485CTRL_OINV; + putreg32(regval, LPC43_USART0_RS485CTRL); + +#else + + /* Do not invert direction countrol output pin polarity */ + + regval = getreg32(LPC43_USART0_RS485CTRL); + regval &= ~(UART_RS485CTRL_OINV); + putreg32(regval, LPC43_USART0_RS485CTRL); + +#endif /* CONFIG_USART0_RS485DIROIN */ +#endif /* CONFIG_USART0_RS485MODE */ leave_critical_section(flags); }; @@ -467,7 +491,31 @@ void lpc43_usart2_setup(void) #ifdef CONFIG_USART2_RS485MODE lpc43_pin_config(PINCONF_U2_DIR); -#endif + + /* Enable direction output pin */ + + regval = getreg32(LPC43_USART2_RS485CTRL); + regval |= UART_RS485CTRL_DCTRL; + putreg32(regval, LPC43_USART2_RS485CTRL); + +#ifdef CONFIG_USART2_RS485DIROIN + + /* Invert direction control output pin polarity */ + + regval = getreg32(LPC43_USART2_RS485CTRL); + regval |= UART_RS485CTRL_OINV; + putreg32(regval, LPC43_USART2_RS485CTRL); + +#else + + /* Do not invert direction countrol output pin polarity */ + + regval = getreg32(LPC43_USART2_RS485CTRL); + regval &= ~(UART_RS485CTRL_OINV); + putreg32(regval, LPC43_USART2_RS485CTRL); + +#endif /* CONFIG_USART2_RS485DIROIN */ +#endif /* CONFIG_USART2_RS485MODE */ leave_critical_section(flags); }; @@ -516,7 +564,31 @@ void lpc43_usart3_setup(void) #ifdef CONFIG_USART3_RS485MODE lpc43_pin_config(PINCONF_U3_DIR); -#endif + + /* Enable direction output pin */ + + regval = getreg32(LPC43_USART3_RS485CTRL); + regval |= UART_RS485CTRL_DCTRL; + putreg32(regval, LPC43_USART3_RS485CTRL); + +#ifdef CONFIG_USART3_RS485DIROIN + + /* Invert direction control output pin polarity */ + + regval = getreg32(LPC43_USART3_RS485CTRL); + regval |= UART_RS485CTRL_OINV; + putreg32(regval, LPC43_USART3_RS485CTRL); + +#else + + /* Do not invert direction countrol output pin polarity */ + + regval = getreg32(LPC43_USART3_RS485CTRL); + regval &= ~(UART_RS485CTRL_OINV); + putreg32(regval, LPC43_USART3_RS485CTRL); + +#endif /* CONFIG_USART3_RS485DIROIN */ +#endif /* CONFIG_USART3_RS485MODE */ leave_critical_section(flags); }; -- GitLab From ef475eb6a98850c82bbcc69d1e26ffcc6d4885af Mon Sep 17 00:00:00 2001 From: Neil Hancock Date: Sat, 1 Oct 2016 07:32:41 -0600 Subject: [PATCH 015/734] STM32 Ethernet: Correct typo in conditional logic --- arch/arm/src/stm32/stm32_eth.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/stm32/stm32_eth.c index a7f6eaa26f..abf911f7ac 100644 --- a/arch/arm/src/stm32/stm32_eth.c +++ b/arch/arm/src/stm32/stm32_eth.c @@ -3278,7 +3278,7 @@ static inline int stm32_dm9161(FAR struct stm32_ethmac_s *priv) static int stm32_phyinit(FAR struct stm32_ethmac_s *priv) { -#ifdef CONFIG_STM32_AUTOGEN +#ifdef CONFIG_STM32_AUTONEG volatile uint32_t timeout; #endif -- GitLab From 0f7b9d643f30c26217575f1ae78cf6fa936aba07 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 1 Oct 2016 10:13:37 -0600 Subject: [PATCH 016/734] Correct statment in a document --- Documentation/NuttX.html | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/Documentation/NuttX.html b/Documentation/NuttX.html index 700876be65..4d6823305e 100644 --- a/Documentation/NuttX.html +++ b/Documentation/NuttX.html @@ -8,7 +8,7 @@

NuttX RTOS

-

Last Updated: July 25, 2016

+

Last Updated: September 30, 2016

@@ -146,13 +146,11 @@ to support a rich, multi-threaded development environment for deeply embedded processors.

- NON-GOALS: (1) It is not a goal to provide the level of OS features like those provided by Linux. + NON-GOALS: It is not a goal to provide the level of OS features like those provided by Linux. In order to work with smaller MCUs, small footprint must be more important than an extensive feature set. But standard compliance is more important than small footprint. Surely a smaller RTOS could be produced by ignoring standards. Think of NuttX is a tiny Linux work-alike with a much reduced feature set. - (2) There is no MMU-based support for processes. - At present, NuttX assumes a flat address space.

-- GitLab From 75104b080801a62dcf829a1c2b1cdc1be9f9fc6a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 1 Oct 2016 10:56:42 -0600 Subject: [PATCH 017/734] Remove duplicate function prototype from wrong header file --- sched/task/task.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/sched/task/task.h b/sched/task/task.h index b4967c799a..e81f0eaefc 100644 --- a/sched/task/task.h +++ b/sched/task/task.h @@ -80,8 +80,4 @@ int task_terminate(pid_t pid, bool nonblocking); void task_exithook(FAR struct tcb_s *tcb, int status, bool nonblocking); void task_recover(FAR struct tcb_s *tcb); -/* Misc. */ - -bool sched_addreadytorun(FAR struct tcb_s *rtrtcb); - #endif /* __SCHED_TASK_TASK_H */ -- GitLab From 8669183852845f527d7761f6582bcc4d997eb812 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 1 Oct 2016 11:38:22 -0600 Subject: [PATCH 018/734] sched/pthread and task: When a pthread is started, there is a small bit of logic that will run on the thread of execution of the new pthread. In the case where the new pthread has a lower priority than the parent thread, then this could cause both the parent thread and the new pthread to be blocked at the priority of the lower priority pthread (assuming that CONFIG_PRIORITY_INHERITANCE is not selected). This change temporarily boosts the priority of the new pthread to at least the priority of the new pthread to at least the priority of the parent thread. When that bit of logic has executed on the thread of execution of the new pthread, it will then drop to the correct priority (if necessary) before calling into the new pthread's entry point. --- include/nuttx/sched.h | 4 ++-- sched/pthread/pthread_create.c | 32 +++++++++++++++++++++++++++++++- sched/task/task_restart.c | 4 ++-- sched/task/task_setup.c | 15 +++------------ 4 files changed, 38 insertions(+), 17 deletions(-) diff --git a/include/nuttx/sched.h b/include/nuttx/sched.h index 4d7bb88f11..ec438727f8 100644 --- a/include/nuttx/sched.h +++ b/include/nuttx/sched.h @@ -551,6 +551,7 @@ struct tcb_s start_t start; /* Thread start function */ entry_t entry; /* Entry Point into the thread */ uint8_t sched_priority; /* Current priority of the thread */ + uint8_t init_priority; /* Initial priority of the thread */ #ifdef CONFIG_PRIORITY_INHERITANCE #if CONFIG_SEM_NNESTPRIO > 0 @@ -654,9 +655,8 @@ struct task_tcb_s FAR void *starthookarg; /* The argument passed to the function */ #endif - /* Values needed to restart a task ********************************************/ + /* [Re-]start name + start-up parameters **************************************/ - uint8_t init_priority; /* Initial priority of the task */ FAR char **argv; /* Name+start-up parameters */ }; diff --git a/sched/pthread/pthread_create.c b/sched/pthread/pthread_create.c index 487827fbcb..be81a5f0ff 100644 --- a/sched/pthread/pthread_create.c +++ b/sched/pthread/pthread_create.c @@ -183,6 +183,16 @@ static void pthread_start(void) pjoin->started = true; (void)pthread_givesemaphore(&pjoin->data_sem); + /* The priority of this thread may have been boosted to avoid priority + * inversion problems. If that is the case, then drop to the correct + * execution priority. + */ + + if (ptcb->cmn.sched_priority > ptcb->cmn.init_priority) + { + DEBUGVERIFY(sched_setpriority(&ptcb->cmn, ptcb->cmn.init_priority)); + } + /* Pass control to the thread entry point. In the kernel build this has to * be handled differently if we are starting a user-space pthread; we have * to switch to user-mode before calling into the pthread. @@ -488,7 +498,27 @@ int pthread_create(FAR pthread_t *thread, FAR const pthread_attr_t *attr, ret = sem_init(&pjoin->exit_sem, 0, 0); } - /* Activate the task */ + /* If the priority of the new pthread is lower than the priority of the + * parent thread, then starting the pthread could result in both the + * parent and the pthread to be blocked. This is a recipe for priority + * inversion issues. + * + * We avoid this here by boosting the priority of the (inactive) pthread + * so it has the same priority as the parent thread. + */ + + if (ret == OK) + { + FAR struct tcb_s *parent = this_task(); + DEBUGASSERT(parent != NULL); + + if (ptcb->cmn.sched_priority < parent->sched_priority) + { + ret = sched_setpriority(&ptcb->cmn, parent->sched_priority); + } + } + + /* Then activate the task */ sched_lock(); if (ret == OK) diff --git a/sched/task/task_restart.c b/sched/task/task_restart.c index 5f3b76958f..70da24df57 100644 --- a/sched/task/task_restart.c +++ b/sched/task/task_restart.c @@ -169,12 +169,12 @@ int task_restart(pid_t pid) /* Reset the current task priority */ - tcb->cmn.sched_priority = tcb->init_priority; + tcb->cmn.sched_priority = tcb->cmn.init_priority; /* Reset the base task priority and the number of pending reprioritizations */ #ifdef CONFIG_PRIORITY_INHERITANCE - tcb->cmn.base_priority = tcb->init_priority; + tcb->cmn.base_priority = tcb->cmn.init_priority; # if CONFIG_SEM_NNESTPRIO > 0 tcb->cmn.npend_reprio = 0; # endif diff --git a/sched/task/task_setup.c b/sched/task/task_setup.c index 0819049785..7b8b086434 100644 --- a/sched/task/task_setup.c +++ b/sched/task/task_setup.c @@ -363,6 +363,7 @@ static int thread_schedsetup(FAR struct tcb_s *tcb, int priority, /* Save task priority and entry point in the TCB */ tcb->sched_priority = (uint8_t)priority; + tcb->init_priority = (uint8_t)priority; #ifdef CONFIG_PRIORITY_INHERITANCE tcb->base_priority = (uint8_t)priority; #endif @@ -633,20 +634,10 @@ static inline int task_stackargsetup(FAR struct task_tcb_s *tcb, int task_schedsetup(FAR struct task_tcb_s *tcb, int priority, start_t start, main_t main, uint8_t ttype) { - int ret; - /* Perform common thread setup */ - ret = thread_schedsetup((FAR struct tcb_s *)tcb, priority, start, - (CODE void *)main, ttype); - if (ret == OK) - { - /* Save task restart priority */ - - tcb->init_priority = (uint8_t)priority; - } - - return ret; + return thread_schedsetup((FAR struct tcb_s *)tcb, priority, start, + (CODE void *)main, ttype); } /**************************************************************************** -- GitLab From 33cea5038f516d1b2bf57fe3badbafb6b3069d29 Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Sat, 1 Oct 2016 19:38:43 +0200 Subject: [PATCH 019/734] memory corruption, typo addr-value --- arch/arm/src/stm32f7/stm32_otgdev.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/stm32f7/stm32_otgdev.c b/arch/arm/src/stm32f7/stm32_otgdev.c index f06175cb5b..54a0232cdf 100644 --- a/arch/arm/src/stm32f7/stm32_otgdev.c +++ b/arch/arm/src/stm32f7/stm32_otgdev.c @@ -4230,7 +4230,10 @@ static void stm32_epin_disable(FAR struct stm32_ep_s *privep) /* Clear the EPDISD interrupt indication */ - stm32_putreg(OTG_DIEPINT_EPDISD, stm32_getreg(regaddr)); + regval = stm32_getreg(regaddr); + regval |= OTG_DIEPINT_EPDISD; + stm32_putreg(OTG_DIEPINT_EPDISD, regaddr); + /* Flush any data remaining in the TxFIFO */ -- GitLab From a196f2968c9fe8697ca58717bb1ee56008055108 Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Sat, 1 Oct 2016 19:39:33 +0200 Subject: [PATCH 020/734] more stack size for Idle thread --- configs/stm32f746-ws/nsh/defconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig index 6fafd45558..5c0a529820 100644 --- a/configs/stm32f746-ws/nsh/defconfig +++ b/configs/stm32f746-ws/nsh/defconfig @@ -312,7 +312,7 @@ CONFIG_STM32F7_OTGFS=y # CONFIG_STM32F7_RNG is not set # CONFIG_STM32F7_SAI1 is not set # CONFIG_STM32F7_SAI2 is not set -CONFIG_STM32F7_SDMMC1=y +##CONFIG_STM32F7_SDMMC1=y # CONFIG_STM32F7_SPDIFRX is not set CONFIG_STM32F7_SPI1=y # CONFIG_STM32F7_SPI2 is not set @@ -416,7 +416,7 @@ CONFIG_BOARD_LOOPSPERMSEC=43103 # Interrupt options # CONFIG_ARCH_HAVE_INTERRUPTSTACK=y -CONFIG_ARCH_INTERRUPTSTACK=600 +CONFIG_ARCH_INTERRUPTSTACK=2600 CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y # CONFIG_ARCH_HIPRI_INTERRUPT is not set @@ -571,7 +571,7 @@ CONFIG_SCHED_LPWORKSTACKSIZE=1800 # # Stack and heap information # -CONFIG_IDLETHREAD_STACKSIZE=500 +CONFIG_IDLETHREAD_STACKSIZE=2500 CONFIG_USERMAIN_STACKSIZE=2500 CONFIG_PTHREAD_STACK_MIN=512 CONFIG_PTHREAD_STACK_DEFAULT=2048 -- GitLab From 53fa8b72965420c4e2ee1fa42b8ca44bd609fd12 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Sun, 2 Oct 2016 14:45:44 -0600 Subject: [PATCH 021/734] configs/stm32f103-minimum: Add stm32_bringup support and userled example to STM32F103 Minimum board --- configs/stm32f103-minimum/include/board.h | 15 +- configs/stm32f103-minimum/src/Makefile | 8 +- configs/stm32f103-minimum/src/stm32_appinit.c | 25 +- .../stm32f103-minimum/src/stm32_autoleds.c | 4 +- configs/stm32f103-minimum/src/stm32_boot.c | 24 + configs/stm32f103-minimum/src/stm32_bringup.c | 142 ++ .../stm32f103-minimum/src/stm32_userleds.c | 112 ++ .../stm32f103-minimum/src/stm32f103_minimum.h | 22 +- configs/stm32f103-minimum/userled/Make.defs | 113 ++ configs/stm32f103-minimum/userled/defconfig | 1143 +++++++++++++++++ configs/stm32f103-minimum/userled/setenv.sh | 100 ++ 11 files changed, 1677 insertions(+), 31 deletions(-) create mode 100644 configs/stm32f103-minimum/src/stm32_bringup.c create mode 100644 configs/stm32f103-minimum/src/stm32_userleds.c create mode 100644 configs/stm32f103-minimum/userled/Make.defs create mode 100644 configs/stm32f103-minimum/userled/defconfig create mode 100644 configs/stm32f103-minimum/userled/setenv.sh diff --git a/configs/stm32f103-minimum/include/board.h b/configs/stm32f103-minimum/include/board.h index 217e4dfd89..85bdf23464 100644 --- a/configs/stm32f103-minimum/include/board.h +++ b/configs/stm32f103-minimum/include/board.h @@ -43,11 +43,14 @@ #include #ifndef __ASSEMBLY__ -# include +# include +#endif + +#ifdef __KERNEL__ +# include "stm32_rcc.h" +# include "stm32_sdio.h" +# include "stm32.h" #endif -#include "stm32_rcc.h" -#include "stm32_sdio.h" -#include "stm32.h" /************************************************************************************ * Pre-processor Definitions @@ -151,6 +154,10 @@ /* LED definitions ******************************************************************/ +/* Define how many LEDs this board has (needed by userleds) */ + +#define BOARD_NLEDS 1 + /* The board has only one controllable LED */ #define LED_STARTED 0 /* No LEDs */ diff --git a/configs/stm32f103-minimum/src/Makefile b/configs/stm32f103-minimum/src/Makefile index 0e07041715..5876a6df68 100644 --- a/configs/stm32f103-minimum/src/Makefile +++ b/configs/stm32f103-minimum/src/Makefile @@ -37,12 +37,18 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = stm32_boot.c stm32_autoleds.c stm32_spi.c stm32_usbdev.c +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c stm32_usbdev.c ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += stm32_appinit.c endif +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + ifeq ($(CONFIG_AUDIO_TONE),y) CSRCS += stm32_tone.c endif diff --git a/configs/stm32f103-minimum/src/stm32_appinit.c b/configs/stm32f103-minimum/src/stm32_appinit.c index a5fe60b616..e8d545ff66 100644 --- a/configs/stm32f103-minimum/src/stm32_appinit.c +++ b/configs/stm32f103-minimum/src/stm32_appinit.c @@ -81,28 +81,7 @@ int board_app_initialize(uintptr_t arg) { -#ifdef CONFIG_ONESHOT - struct oneshot_lowerhalf_s *os = NULL; -#endif - int ret = OK; + /* Perform board initialization here */ -#ifdef CONFIG_AUDIO_TONE - /* Configure and initialize the tone generator. */ - - ret = stm32_tone_setup(); -#endif - -#ifdef CONFIG_WL_MFRC522 - ret = stm32_mfrc522initialize("/dev/rfid0"); -#endif - -#ifdef CONFIG_ONESHOT - os = oneshot_initialize(1, 10); - if (os) - { - ret = oneshot_register("/dev/oneshot", os); - } -#endif - - return ret; + return stm32_bringup(); } diff --git a/configs/stm32f103-minimum/src/stm32_autoleds.c b/configs/stm32f103-minimum/src/stm32_autoleds.c index b851c44053..b2c8b33576 100644 --- a/configs/stm32f103-minimum/src/stm32_autoleds.c +++ b/configs/stm32f103-minimum/src/stm32_autoleds.c @@ -59,7 +59,7 @@ static inline void set_led(bool v) { ledinfo("Turn LED %s\n", v? "on":"off"); - stm32_gpiowrite(GPIO_LED, !v); + stm32_gpiowrite(GPIO_LED1, !v); } /**************************************************************************** @@ -75,7 +75,7 @@ void board_autoled_initialize(void) { /* Configure LED GPIO for output */ - stm32_configgpio(GPIO_LED); + stm32_configgpio(GPIO_LED1); } /**************************************************************************** diff --git a/configs/stm32f103-minimum/src/stm32_boot.c b/configs/stm32f103-minimum/src/stm32_boot.c index c7b9b4df99..92f321fbcb 100644 --- a/configs/stm32f103-minimum/src/stm32_boot.c +++ b/configs/stm32f103-minimum/src/stm32_boot.c @@ -87,3 +87,27 @@ void stm32_boardinitialize(void) stm32_usbinitialize(); #endif } + +/************************************************************************************ + * Name: board_initialize + * + * Description: + * If CONFIG_BOARD_INITIALIZE is selected, then an additional initialization call + * will be performed in the boot-up sequence to a function called + * board_initialize(). board_initialize() will be called immediately after + * up_initialize() is called and just before the initial application is started. + * This additional initialization phase may be used, for example, to initialize + * board-specific device drivers. + * + ************************************************************************************/ + +#ifdef CONFIG_BOARD_INITIALIZE +void board_initialize(void) +{ +#ifndef CONFIG_LIB_BOARDCTL + /* Perform board initialization here instead of from the board_app_initialize(). */ + + (void)stm32_bringup(); +#endif +} +#endif diff --git a/configs/stm32f103-minimum/src/stm32_bringup.c b/configs/stm32f103-minimum/src/stm32_bringup.c new file mode 100644 index 0000000000..ec7d33db3f --- /dev/null +++ b/configs/stm32f103-minimum/src/stm32_bringup.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * config/stm32f103-minimum/src/stm32_bringup.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#include + +#include "stm32.h" + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#include "stm32f103_minimum.h" + +/* Conditional logic in stm32f103_minimum.h will determine if certain features + * are supported. Tests for these features need to be made after including + * stm32f103_minimum.h. + */ + +#ifdef HAVE_RTC_DRIVER +# include +# include "stm32_rtc.h" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#ifdef CONFIG_ONESHOT + struct oneshot_lowerhalf_s *os = NULL; +#endif + int ret = OK; + +#ifdef CONFIG_AUDIO_TONE + /* Configure and initialize the tone generator. */ + + ret = stm32_tone_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_tone_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_WL_MFRC522 + ret = stm32_mfrc522initialize("/dev/rfid0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mfrc522initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ONESHOT + os = oneshot_initialize(1, 10); + if (os) + { + ret = oneshot_register("/dev/oneshot", os); + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + + return ret; +} diff --git a/configs/stm32f103-minimum/src/stm32_userleds.c b/configs/stm32f103-minimum/src/stm32_userleds.c new file mode 100644 index 0000000000..ac26d4d4d0 --- /dev/null +++ b/configs/stm32f103-minimum/src/stm32_userleds.c @@ -0,0 +1,112 @@ +/**************************************************************************** + * configs/stm32f103-minimum/src/stm32_userleds.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32f103_minimum.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ +/* This array maps an LED number to GPIO pin configuration */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ + int i; + + /* Configure LED1-8 GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_configgpio(g_ledcfg[i]); + } +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ + int i; + + /* Configure LED1-8 GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + } +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/configs/stm32f103-minimum/src/stm32f103_minimum.h b/configs/stm32f103-minimum/src/stm32f103_minimum.h index c023d22dc9..f3c083ac6b 100644 --- a/configs/stm32f103-minimum/src/stm32f103_minimum.h +++ b/configs/stm32f103-minimum/src/stm32f103_minimum.h @@ -63,7 +63,7 @@ /* GPIOs **************************************************************/ /* LEDs */ -#define GPIO_LED (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ +#define GPIO_LED1 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN13) /* SPI chip selects */ @@ -91,6 +91,26 @@ #ifndef __ASSEMBLY__ +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture specific initialization + * + * CONFIG_LIB_BOARDCTL=y: + * If CONFIG_NSH_ARCHINITIALIZE=y: + * Called from the NSH library (or other application) + * Otherse, assumed to be called from some other application. + * + * Otherwise CONFIG_BOARD_INITIALIZE=y: + * Called from board_initialize(). + * + * Otherise, bad news: Never called + * + ****************************************************************************/ + +int stm32_bringup(void); + /************************************************************************************ * Name: stm32_spidev_initialize * diff --git a/configs/stm32f103-minimum/userled/Make.defs b/configs/stm32f103-minimum/userled/Make.defs new file mode 100644 index 0000000000..d7974b005f --- /dev/null +++ b/configs/stm32f103-minimum/userled/Make.defs @@ -0,0 +1,113 @@ +############################################################################ +# configs/stm32f103-minimum/userled/Make.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/stm32f103-minimum/userled/defconfig b/configs/stm32f103-minimum/userled/defconfig new file mode 100644 index 0000000000..39ef59233b --- /dev/null +++ b/configs/stm32f103-minimum/userled/defconfig @@ -0,0 +1,1143 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_DEFAULT_SMALL=y +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +CONFIG_ARCH_HAVE_HEAPCHECK=y +# CONFIG_HEAP_COLORATION is not set +# CONFIG_DEBUG_SYMBOLS is not set +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +CONFIG_ARCH_CHIP_STM32=y +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +CONFIG_ARCH_CORTEXM3=y +# CONFIG_ARCH_CORTEXM4 is not set +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="stm32" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARMV7M_LAZYFPU is not set +# CONFIG_ARCH_HAVE_FPU is not set +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y +CONFIG_ARMV7M_HAVE_STACKCHECK=y +# CONFIG_ARMV7M_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set +CONFIG_SERIAL_TERMIOS=y + +# +# STM32 Configuration Options +# +# CONFIG_ARCH_CHIP_STM32L151C6 is not set +# CONFIG_ARCH_CHIP_STM32L151C8 is not set +# CONFIG_ARCH_CHIP_STM32L151CB is not set +# CONFIG_ARCH_CHIP_STM32L151R6 is not set +# CONFIG_ARCH_CHIP_STM32L151R8 is not set +# CONFIG_ARCH_CHIP_STM32L151RB is not set +# CONFIG_ARCH_CHIP_STM32L151V6 is not set +# CONFIG_ARCH_CHIP_STM32L151V8 is not set +# CONFIG_ARCH_CHIP_STM32L151VB is not set +# CONFIG_ARCH_CHIP_STM32L152C6 is not set +# CONFIG_ARCH_CHIP_STM32L152C8 is not set +# CONFIG_ARCH_CHIP_STM32L152CB is not set +# CONFIG_ARCH_CHIP_STM32L152R6 is not set +# CONFIG_ARCH_CHIP_STM32L152R8 is not set +# CONFIG_ARCH_CHIP_STM32L152RB is not set +# CONFIG_ARCH_CHIP_STM32L152V6 is not set +# CONFIG_ARCH_CHIP_STM32L152V8 is not set +# CONFIG_ARCH_CHIP_STM32L152VB is not set +# CONFIG_ARCH_CHIP_STM32L162ZD is not set +# CONFIG_ARCH_CHIP_STM32L162VE is not set +# CONFIG_ARCH_CHIP_STM32F100C8 is not set +# CONFIG_ARCH_CHIP_STM32F100CB is not set +# CONFIG_ARCH_CHIP_STM32F100R8 is not set +# CONFIG_ARCH_CHIP_STM32F100RB is not set +# CONFIG_ARCH_CHIP_STM32F100RC is not set +# CONFIG_ARCH_CHIP_STM32F100RD is not set +# CONFIG_ARCH_CHIP_STM32F100RE is not set +# CONFIG_ARCH_CHIP_STM32F100V8 is not set +# CONFIG_ARCH_CHIP_STM32F100VB is not set +# CONFIG_ARCH_CHIP_STM32F100VC is not set +# CONFIG_ARCH_CHIP_STM32F100VD is not set +# CONFIG_ARCH_CHIP_STM32F100VE is not set +# CONFIG_ARCH_CHIP_STM32F102CB is not set +# CONFIG_ARCH_CHIP_STM32F103T8 is not set +# CONFIG_ARCH_CHIP_STM32F103TB is not set +# CONFIG_ARCH_CHIP_STM32F103C4 is not set +CONFIG_ARCH_CHIP_STM32F103C8=y +# CONFIG_ARCH_CHIP_STM32F103CB is not set +# CONFIG_ARCH_CHIP_STM32F103R8 is not set +# CONFIG_ARCH_CHIP_STM32F103RB is not set +# CONFIG_ARCH_CHIP_STM32F103RC is not set +# CONFIG_ARCH_CHIP_STM32F103RD is not set +# CONFIG_ARCH_CHIP_STM32F103RE is not set +# CONFIG_ARCH_CHIP_STM32F103RG is not set +# CONFIG_ARCH_CHIP_STM32F103V8 is not set +# CONFIG_ARCH_CHIP_STM32F103VB is not set +# CONFIG_ARCH_CHIP_STM32F103VC is not set +# CONFIG_ARCH_CHIP_STM32F103VE is not set +# CONFIG_ARCH_CHIP_STM32F103ZE is not set +# CONFIG_ARCH_CHIP_STM32F105VB is not set +# CONFIG_ARCH_CHIP_STM32F105RB is not set +# CONFIG_ARCH_CHIP_STM32F107VC is not set +# CONFIG_ARCH_CHIP_STM32F205RG is not set +# CONFIG_ARCH_CHIP_STM32F207IG is not set +# CONFIG_ARCH_CHIP_STM32F207ZE is not set +# CONFIG_ARCH_CHIP_STM32F302K6 is not set +# CONFIG_ARCH_CHIP_STM32F302K8 is not set +# CONFIG_ARCH_CHIP_STM32F302CB is not set +# CONFIG_ARCH_CHIP_STM32F302CC is not set +# CONFIG_ARCH_CHIP_STM32F302RB is not set +# CONFIG_ARCH_CHIP_STM32F302RC is not set +# CONFIG_ARCH_CHIP_STM32F302VB is not set +# CONFIG_ARCH_CHIP_STM32F302VC is not set +# CONFIG_ARCH_CHIP_STM32F303K6 is not set +# CONFIG_ARCH_CHIP_STM32F303K8 is not set +# CONFIG_ARCH_CHIP_STM32F303C6 is not set +# CONFIG_ARCH_CHIP_STM32F303C8 is not set +# CONFIG_ARCH_CHIP_STM32F303CB is not set +# CONFIG_ARCH_CHIP_STM32F303CC is not set +# CONFIG_ARCH_CHIP_STM32F303RB is not set +# CONFIG_ARCH_CHIP_STM32F303RC is not set +# CONFIG_ARCH_CHIP_STM32F303RD is not set +# CONFIG_ARCH_CHIP_STM32F303RE is not set +# CONFIG_ARCH_CHIP_STM32F303VB is not set +# CONFIG_ARCH_CHIP_STM32F303VC is not set +# CONFIG_ARCH_CHIP_STM32F372C8 is not set +# CONFIG_ARCH_CHIP_STM32F372R8 is not set +# CONFIG_ARCH_CHIP_STM32F372V8 is not set +# CONFIG_ARCH_CHIP_STM32F372CB is not set +# CONFIG_ARCH_CHIP_STM32F372RB is not set +# CONFIG_ARCH_CHIP_STM32F372VB is not set +# CONFIG_ARCH_CHIP_STM32F372CC is not set +# CONFIG_ARCH_CHIP_STM32F372RC is not set +# CONFIG_ARCH_CHIP_STM32F372VC is not set +# CONFIG_ARCH_CHIP_STM32F373C8 is not set +# CONFIG_ARCH_CHIP_STM32F373R8 is not set +# CONFIG_ARCH_CHIP_STM32F373V8 is not set +# CONFIG_ARCH_CHIP_STM32F373CB is not set +# CONFIG_ARCH_CHIP_STM32F373RB is not set +# CONFIG_ARCH_CHIP_STM32F373VB is not set +# CONFIG_ARCH_CHIP_STM32F373CC is not set +# CONFIG_ARCH_CHIP_STM32F373RC is not set +# CONFIG_ARCH_CHIP_STM32F373VC is not set +# CONFIG_ARCH_CHIP_STM32F401RE is not set +# CONFIG_ARCH_CHIP_STM32F411RE is not set +# CONFIG_ARCH_CHIP_STM32F411VE is not set +# CONFIG_ARCH_CHIP_STM32F405RG is not set +# CONFIG_ARCH_CHIP_STM32F405VG is not set +# CONFIG_ARCH_CHIP_STM32F405ZG is not set +# CONFIG_ARCH_CHIP_STM32F407VE is not set +# CONFIG_ARCH_CHIP_STM32F407VG is not set +# CONFIG_ARCH_CHIP_STM32F407ZE is not set +# CONFIG_ARCH_CHIP_STM32F407ZG is not set +# CONFIG_ARCH_CHIP_STM32F407IE is not set +# CONFIG_ARCH_CHIP_STM32F407IG is not set +# CONFIG_ARCH_CHIP_STM32F427V is not set +# CONFIG_ARCH_CHIP_STM32F427Z is not set +# CONFIG_ARCH_CHIP_STM32F427I is not set +# CONFIG_ARCH_CHIP_STM32F429V is not set +# CONFIG_ARCH_CHIP_STM32F429Z is not set +# CONFIG_ARCH_CHIP_STM32F429I is not set +# CONFIG_ARCH_CHIP_STM32F429B is not set +# CONFIG_ARCH_CHIP_STM32F429N is not set +# CONFIG_ARCH_CHIP_STM32F446M is not set +# CONFIG_ARCH_CHIP_STM32F446R is not set +# CONFIG_ARCH_CHIP_STM32F446V is not set +# CONFIG_ARCH_CHIP_STM32F446Z is not set +# CONFIG_ARCH_CHIP_STM32F469A is not set +# CONFIG_ARCH_CHIP_STM32F469I is not set +# CONFIG_ARCH_CHIP_STM32F469B is not set +# CONFIG_ARCH_CHIP_STM32F469N is not set +CONFIG_STM32_FLASH_CONFIG_DEFAULT=y +# CONFIG_STM32_FLASH_CONFIG_4 is not set +# CONFIG_STM32_FLASH_CONFIG_6 is not set +# CONFIG_STM32_FLASH_CONFIG_8 is not set +# CONFIG_STM32_FLASH_CONFIG_B is not set +# CONFIG_STM32_FLASH_CONFIG_C is not set +# CONFIG_STM32_FLASH_CONFIG_D is not set +# CONFIG_STM32_FLASH_CONFIG_E is not set +# CONFIG_STM32_FLASH_CONFIG_F is not set +# CONFIG_STM32_FLASH_CONFIG_G is not set +# CONFIG_STM32_FLASH_CONFIG_I is not set +# CONFIG_STM32_STM32L15XX is not set +# CONFIG_STM32_ENERGYLITE is not set +CONFIG_STM32_STM32F10XX=y +# CONFIG_STM32_VALUELINE is not set +# CONFIG_STM32_CONNECTIVITYLINE is not set +CONFIG_STM32_PERFORMANCELINE=y +# CONFIG_STM32_USBACCESSLINE is not set +# CONFIG_STM32_HIGHDENSITY is not set +CONFIG_STM32_MEDIUMDENSITY=y +# CONFIG_STM32_LOWDENSITY is not set +# CONFIG_STM32_STM32F20XX is not set +# CONFIG_STM32_STM32F205 is not set +# CONFIG_STM32_STM32F207 is not set +# CONFIG_STM32_STM32F30XX is not set +# CONFIG_STM32_STM32F302 is not set +# CONFIG_STM32_STM32F303 is not set +# CONFIG_STM32_STM32F37XX is not set +# CONFIG_STM32_STM32F40XX is not set +# CONFIG_STM32_STM32F401 is not set +# CONFIG_STM32_STM32F411 is not set +# CONFIG_STM32_STM32F405 is not set +# CONFIG_STM32_STM32F407 is not set +# CONFIG_STM32_STM32F427 is not set +# CONFIG_STM32_STM32F429 is not set +# CONFIG_STM32_STM32F446 is not set +# CONFIG_STM32_STM32F469 is not set +# CONFIG_STM32_DFU is not set + +# +# STM32 Peripheral Support +# +# CONFIG_STM32_HAVE_CCM is not set +CONFIG_STM32_HAVE_USBDEV=y +# CONFIG_STM32_HAVE_OTGFS is not set +# CONFIG_STM32_HAVE_FSMC is not set +# CONFIG_STM32_HAVE_LTDC is not set +CONFIG_STM32_HAVE_USART3=y +CONFIG_STM32_HAVE_UART4=y +CONFIG_STM32_HAVE_UART5=y +# CONFIG_STM32_HAVE_USART6 is not set +# CONFIG_STM32_HAVE_UART7 is not set +# CONFIG_STM32_HAVE_UART8 is not set +CONFIG_STM32_HAVE_TIM1=y +# CONFIG_STM32_HAVE_TIM2 is not set +CONFIG_STM32_HAVE_TIM3=y +CONFIG_STM32_HAVE_TIM4=y +CONFIG_STM32_HAVE_TIM5=y +CONFIG_STM32_HAVE_TIM6=y +CONFIG_STM32_HAVE_TIM7=y +CONFIG_STM32_HAVE_TIM8=y +# CONFIG_STM32_HAVE_TIM9 is not set +# CONFIG_STM32_HAVE_TIM10 is not set +# CONFIG_STM32_HAVE_TIM11 is not set +# CONFIG_STM32_HAVE_TIM12 is not set +# CONFIG_STM32_HAVE_TIM13 is not set +# CONFIG_STM32_HAVE_TIM14 is not set +# CONFIG_STM32_HAVE_TIM15 is not set +# CONFIG_STM32_HAVE_TIM16 is not set +# CONFIG_STM32_HAVE_TIM17 is not set +CONFIG_STM32_HAVE_ADC2=y +CONFIG_STM32_HAVE_ADC3=y +# CONFIG_STM32_HAVE_ADC4 is not set +# CONFIG_STM32_HAVE_ADC1_DMA is not set +# CONFIG_STM32_HAVE_ADC2_DMA is not set +# CONFIG_STM32_HAVE_ADC3_DMA is not set +# CONFIG_STM32_HAVE_ADC4_DMA is not set +CONFIG_STM32_HAVE_CAN1=y +# CONFIG_STM32_HAVE_CAN2 is not set +# CONFIG_STM32_HAVE_DAC1 is not set +# CONFIG_STM32_HAVE_DAC2 is not set +# CONFIG_STM32_HAVE_RNG is not set +# CONFIG_STM32_HAVE_ETHMAC is not set +CONFIG_STM32_HAVE_I2C2=y +# CONFIG_STM32_HAVE_I2C3 is not set +CONFIG_STM32_HAVE_SPI2=y +CONFIG_STM32_HAVE_SPI3=y +# CONFIG_STM32_HAVE_SPI4 is not set +# CONFIG_STM32_HAVE_SPI5 is not set +# CONFIG_STM32_HAVE_SPI6 is not set +# CONFIG_STM32_HAVE_SAIPLL is not set +# CONFIG_STM32_HAVE_I2SPLL is not set +# CONFIG_STM32_ADC1 is not set +# CONFIG_STM32_ADC2 is not set +# CONFIG_STM32_ADC3 is not set +# CONFIG_STM32_BKP is not set +# CONFIG_STM32_CAN1 is not set +# CONFIG_STM32_CRC is not set +# CONFIG_STM32_DMA1 is not set +# CONFIG_STM32_DMA2 is not set +# CONFIG_STM32_I2C1 is not set +# CONFIG_STM32_I2C2 is not set +# CONFIG_STM32_PWR is not set +# CONFIG_STM32_SDIO is not set +# CONFIG_STM32_SPI1 is not set +# CONFIG_STM32_SPI2 is not set +# CONFIG_STM32_SPI3 is not set +# CONFIG_STM32_TIM1 is not set +# CONFIG_STM32_TIM2 is not set +# CONFIG_STM32_TIM3 is not set +# CONFIG_STM32_TIM4 is not set +# CONFIG_STM32_TIM5 is not set +# CONFIG_STM32_TIM6 is not set +# CONFIG_STM32_TIM7 is not set +# CONFIG_STM32_TIM8 is not set +CONFIG_STM32_USART1=y +# CONFIG_STM32_USART2 is not set +# CONFIG_STM32_USART3 is not set +# CONFIG_STM32_UART4 is not set +# CONFIG_STM32_UART5 is not set +# CONFIG_STM32_USB is not set +# CONFIG_STM32_IWDG is not set +# CONFIG_STM32_WWDG is not set +# CONFIG_STM32_NOEXT_VECTORS is not set + +# +# Alternate Pin Mapping +# +# CONFIG_STM32_USART1_REMAP is not set +# CONFIG_STM32_JTAG_DISABLE is not set +CONFIG_STM32_JTAG_FULL_ENABLE=y +# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set +# CONFIG_STM32_JTAG_SW_ENABLE is not set +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +# CONFIG_STM32_FORCEPOWER is not set +# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set + +# +# Timer Configuration +# +# CONFIG_STM32_ONESHOT is not set +# CONFIG_STM32_FREERUN is not set +# CONFIG_STM32_TIM1_CAP is not set +# CONFIG_STM32_TIM3_CAP is not set +# CONFIG_STM32_TIM4_CAP is not set +# CONFIG_STM32_TIM5_CAP is not set +# CONFIG_STM32_TIM8_CAP is not set +CONFIG_STM32_USART=y +CONFIG_STM32_SERIALDRIVER=y + +# +# U[S]ART Configuration +# + +# +# U[S]ART Device Configuration +# +CONFIG_STM32_USART1_SERIALDRIVER=y +# CONFIG_STM32_USART1_1WIREDRIVER is not set +# CONFIG_USART1_RS485 is not set + +# +# Serial Driver Configuration +# +# CONFIG_SERIAL_DISABLE_REORDERING is not set +# CONFIG_STM32_FLOWCONTROL_BROKEN is not set +# CONFIG_STM32_USART_BREAKS is not set +# CONFIG_STM32_USART_SINGLEWIRE is not set +CONFIG_STM32_HAVE_RTC_COUNTER=y +# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set + +# +# USB FS Host Configuration +# + +# +# USB HS Host Configuration +# + +# +# USB Host Debug Configuration +# + +# +# USB Device Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=5483 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_SIZE=20480 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +# CONFIG_ARCH_BOARD_STM32_TINY is not set +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="stm32f103-minimum" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +# CONFIG_ARCH_LEDS is not set + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_RESET is not set +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_ADCTEST is not set +# CONFIG_BOARDCTL_PWMTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set + +# +# RTOS Features +# +# CONFIG_DISABLE_OS_API is not set + +# +# Clocks and Timers +# +CONFIG_ARCH_HAVE_TICKLESS=y +# CONFIG_SCHED_TICKLESS is not set +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +CONFIG_ARCH_HAVE_TIMEKEEPING=y +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2011 +CONFIG_START_MONTH=7 +CONFIG_START_DAY=5 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=0 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +CONFIG_BOARD_INITIALIZE=y +# CONFIG_BOARD_INITTHREAD is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +# CONFIG_DISABLE_POLL is not set +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +CONFIG_ARCH_HAVE_I2CRESET=y +# CONFIG_I2C is not set +# CONFIG_SPI is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +CONFIG_USART1_SERIALDRIVER=y +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_SERIAL_NPOLLWAITERS=2 +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +CONFIG_USART1_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# USART1 Configuration +# +CONFIG_USART1_RXBUFSIZE=256 +CONFIG_USART1_TXBUFSIZE=256 +CONFIG_USART1_BAUD=115200 +CONFIG_USART1_BITS=8 +CONFIG_USART1_PARITY=0 +CONFIG_USART1_2STOP=0 +# CONFIG_USART1_IFLOWCONTROL is not set +# CONFIG_USART1_OFLOWCONTROL is not set +# CONFIG_USART1_DMA is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +# CONFIG_FS_READABLE is not set +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +CONFIG_SYMTAB_ORDEREDBYNAME=y + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_LIBC_LONG_LONG is not set +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set +# CONFIG_LIBC_NETDB is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +CONFIG_EXAMPLES_LEDS=y +CONFIG_EXAMPLES_LEDS_PRIORITY=100 +CONFIG_EXAMPLES_LEDS_STACKSIZE=2048 +CONFIG_EXAMPLES_LEDS_DEVPATH="/dev/userleds" +CONFIG_EXAMPLES_LEDS_LEDSET=0x0f +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CHAT is not set +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=80 +CONFIG_NSH_DISABLE_SEMICOLON=y +# CONFIG_NSH_CMDPARMS is not set +CONFIG_NSH_MAXARGUMENTS=6 +# CONFIG_NSH_ARGCAT is not set +CONFIG_NSH_NESTDEPTH=3 +CONFIG_NSH_DISABLEBG=y +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +CONFIG_NSH_DISABLE_ADDROUTE=y +CONFIG_NSH_DISABLE_BASENAME=y +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +CONFIG_NSH_DISABLE_DF=y +CONFIG_NSH_DISABLE_DELROUTE=y +CONFIG_NSH_DISABLE_DIRNAME=y +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +CONFIG_NSH_DISABLE_IFCONFIG=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_KILL is not set +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +CONFIG_NSH_DISABLE_TIME=y +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +CONFIG_NSH_DISABLE_UNAME=y +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Configure Command Options +# +CONFIG_NSH_CODECS_BUFSIZE=128 +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_NSH_FILEIOSIZE=1024 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +CONFIG_NSH_DISABLE_ITEF=y +CONFIG_NSH_DISABLE_LOOPS=y + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm32f103-minimum/userled/setenv.sh b/configs/stm32f103-minimum/userled/setenv.sh new file mode 100644 index 0000000000..73dfab5a4d --- /dev/null +++ b/configs/stm32f103-minimum/userled/setenv.sh @@ -0,0 +1,100 @@ +#!/bin/bash +# configs//stm32f103-minimum/nsh/setenv.sh +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" +# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" +# You can this free toolchain here https://launchpad.net/gcc-arm-embedded +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" + +# This is the path to the location where I installed the devkitARM toolchain +# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/ +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" -- GitLab From d5ef349d9a555c307de0bb726c74e311acc6313d Mon Sep 17 00:00:00 2001 From: Sebastien Lorquet Date: Sun, 2 Oct 2016 23:26:16 +0200 Subject: [PATCH 022/734] Add support for quadrature encoders on STM32L4 --- arch/arm/src/stm32l4/Kconfig | 303 +++- arch/arm/src/stm32l4/Make.defs | 4 + .../arm/src/stm32l4/chip/stm32l4x6xx_pinmap.h | 195 ++- arch/arm/src/stm32l4/stm32l4_qencoder.c | 1248 +++++++++++++++++ arch/arm/src/stm32l4/stm32l4_qencoder.h | 141 ++ 5 files changed, 1760 insertions(+), 131 deletions(-) create mode 100644 arch/arm/src/stm32l4/stm32l4_qencoder.c create mode 100644 arch/arm/src/stm32l4/stm32l4_qencoder.h diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index c511faaae6..83dbffe78c 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -721,8 +721,8 @@ if STM32L4_TIM1_CHANNEL1 config STM32L4_TIM1_CH1MODE int "TIM1 Channel 1 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -745,8 +745,8 @@ if STM32L4_TIM1_CHANNEL2 config STM32L4_TIM1_CH2MODE int "TIM1 Channel 2 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -769,8 +769,8 @@ if STM32L4_TIM1_CHANNEL3 config STM32L4_TIM1_CH3MODE int "TIM1 Channel 3 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -793,8 +793,8 @@ if STM32L4_TIM1_CHANNEL4 config STM32L4_TIM1_CH4MODE int "TIM1 Channel 4 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -821,8 +821,8 @@ config STM32L4_TIM1_CHANNEL config STM32L4_TIM1_CHMODE int "TIM1 Channel Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -865,8 +865,8 @@ if STM32L4_TIM2_CHANNEL1 config STM32L4_TIM2_CH1MODE int "TIM2 Channel 1 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -889,8 +889,8 @@ if STM32L4_TIM2_CHANNEL2 config STM32L4_TIM2_CH2MODE int "TIM2 Channel 2 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -913,8 +913,8 @@ if STM32L4_TIM2_CHANNEL3 config STM32L4_TIM2_CH3MODE int "TIM2 Channel 3 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -937,8 +937,8 @@ if STM32L4_TIM2_CHANNEL4 config STM32L4_TIM2_CH4MODE int "TIM2 Channel 4 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -965,8 +965,8 @@ config STM32L4_TIM2_CHANNEL config STM32L4_TIM2_CHMODE int "TIM2 Channel Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1009,8 +1009,8 @@ if STM32L4_TIM3_CHANNEL1 config STM32L4_TIM3_CH1MODE int "TIM3 Channel 1 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1033,8 +1033,8 @@ if STM32L4_TIM3_CHANNEL2 config STM32L4_TIM3_CH2MODE int "TIM3 Channel 2 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1057,8 +1057,8 @@ if STM32L4_TIM3_CHANNEL3 config STM32L4_TIM3_CH3MODE int "TIM3 Channel 3 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1081,8 +1081,8 @@ if STM32L4_TIM3_CHANNEL4 config STM32L4_TIM3_CH4MODE int "TIM3 Channel 4 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1109,8 +1109,8 @@ config STM32L4_TIM3_CHANNEL config STM32L4_TIM3_CHMODE int "TIM3 Channel Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1153,8 +1153,8 @@ if STM32L4_TIM4_CHANNEL1 config STM32L4_TIM4_CH1MODE int "TIM4 Channel 1 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1177,8 +1177,8 @@ if STM32L4_TIM4_CHANNEL2 config STM32L4_TIM4_CH2MODE int "TIM4 Channel 2 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1201,8 +1201,8 @@ if STM32L4_TIM4_CHANNEL3 config STM32L4_TIM4_CH3MODE int "TIM4 Channel 3 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1225,8 +1225,8 @@ if STM32L4_TIM4_CHANNEL4 config STM32L4_TIM4_CH4MODE int "TIM4 Channel 4 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1253,8 +1253,8 @@ config STM32L4_TIM4_CHANNEL config STM32L4_TIM4_CHMODE int "TIM4 Channel Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1297,8 +1297,8 @@ if STM32L4_TIM5_CHANNEL1 config STM32L4_TIM5_CH1MODE int "TIM5 Channel 1 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1321,8 +1321,8 @@ if STM32L4_TIM5_CHANNEL2 config STM32L4_TIM5_CH2MODE int "TIM5 Channel 2 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1345,8 +1345,8 @@ if STM32L4_TIM5_CHANNEL3 config STM32L4_TIM5_CH3MODE int "TIM5 Channel 3 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1369,8 +1369,8 @@ if STM32L4_TIM5_CHANNEL4 config STM32L4_TIM5_CH4MODE int "TIM5 Channel 4 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1397,8 +1397,8 @@ config STM32L4_TIM5_CHANNEL config STM32L4_TIM5_CHMODE int "TIM5 Channel Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1441,8 +1441,8 @@ if STM32L4_TIM8_CHANNEL1 config STM32L4_TIM8_CH1MODE int "TIM8 Channel 1 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1465,8 +1465,8 @@ if STM32L4_TIM8_CHANNEL2 config STM32L4_TIM8_CH2MODE int "TIM8 Channel 2 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1489,8 +1489,8 @@ if STM32L4_TIM8_CHANNEL3 config STM32L4_TIM8_CH3MODE int "TIM8 Channel 3 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1513,8 +1513,8 @@ if STM32L4_TIM8_CHANNEL4 config STM32L4_TIM8_CH4MODE int "TIM8 Channel 4 Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1541,8 +1541,8 @@ config STM32L4_TIM8_CHANNEL config STM32L4_TIM8_CHMODE int "TIM8 Channel Mode" default 0 - range 0 5 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 5 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1577,8 +1577,8 @@ if STM32L4_TIM15_CHANNEL1 config STM32L4_TIM15_CH1MODE int "TIM15 Channel 1 Mode" default 0 - range 0 3 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 3 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1601,8 +1601,8 @@ if STM32L4_TIM15_CHANNEL2 config STM32L4_TIM15_CH2MODE int "TIM15 Channel 2 Mode" default 0 - range 0 3 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 3 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -1629,8 +1629,8 @@ config STM32L4_TIM15_CHANNEL config STM32L4_TIM15_CHMODE int "TIM15 Channel Mode" default 0 - range 0 3 if STM32_STM32F30XX - range 0 1 if !STM32_STM32F30XX + range 0 3 if STM32L4_STM32F30XX + range 0 1 if !STM32L4_STM32F30XX ---help--- Specifies the channel mode. @@ -2750,4 +2750,175 @@ config STM32L4_CAN_REGDEBUG endmenu +menu "QEncoder Driver" + depends on QENCODER + depends on STM32L4_TIM1 || STM32L4_TIM2 || STM32L4_TIM3 || STM32L4_TIM4 || STM32L4_TIM5 || STM32L4_TIM8 + +config STM32L4_TIM1_QE + bool "TIM1" + default n + depends on STM32L4_TIM1 + ---help--- + Reserve TIM1 for use by QEncoder. + +if STM32L4_TIM1_QE + +config STM32L4_TIM1_QECLKOUT + int "TIM1 output clock" + default 2800000 + ---help--- + The output clock of TIM1. + +endif + +config STM32L4_TIM2_QE + bool "TIM2" + default n + depends on STM32L4_TIM2 + ---help--- + Reserve TIM2 for use by QEncoder. + +if STM32L4_TIM2_QE + +config STM32L4_TIM2_QECLKOUT + int "TIM2 output clock" + default 2800000 + ---help--- + The output clock of TIM2. + +endif + +config STM32L4_TIM3_QE + bool "TIM3" + default n + depends on STM32L4_TIM3 + ---help--- + Reserve TIM3 for use by QEncoder. + +if STM32L4_TIM3_QE + +config STM32L4_TIM3_QECLKOUT + int "TIM3 output clock" + default 2800000 + ---help--- + The output clock of TIM3. + +endif + +config STM32L4_TIM4_QE + bool "TIM4" + default n + depends on STM32L4_TIM4 + ---help--- + Reserve TIM4 for use by QEncoder. + +if STM32L4_TIM4_QE + +config STM32L4_TIM4_QECLKOUT + int "TIM4 output clock" + default 2800000 + ---help--- + The output clock of TIM4. + +endif + +config STM32L4_TIM5_QE + bool "TIM5" + default n + depends on STM32L4_TIM5 + ---help--- + Reserve TIM5 for use by QEncoder. + +if STM32L4_TIM5_QE + +config STM32L4_TIM5_QECLKOUT + int "TIM5 output clock" + default 2800000 + ---help--- + The output clock of TIM5. + +endif + +config STM32L4_TIM8_QE + bool "TIM8" + default n + depends on STM32L4_TIM8 + ---help--- + Reserve TIM8 for use by QEncoder. + +if STM32L4_TIM8_QE + +config STM32L4_TIM8_QECLKOUT + int "TIM8 output clock" + default 2800000 + ---help--- + The output clock of TIM8. + +endif + +config STM32L4_QENCODER_FILTER + bool "Enable filtering on STM32 QEncoder input" + default y + +choice + depends on STM32L4_QENCODER_FILTER + prompt "Input channel sampling frequency" + default STM32L4_QENCODER_SAMPLE_FDTS_4 + +config STM32L4_QENCODER_SAMPLE_FDTS + bool "fDTS" + +config STM32L4_QENCODER_SAMPLE_CKINT + bool "fCK_INT" + +config STM32L4_QENCODER_SAMPLE_FDTS_2 + bool "fDTS/2" + +config STM32L4_QENCODER_SAMPLE_FDTS_4 + bool "fDTS/4" + +config STM32L4_QENCODER_SAMPLE_FDTS_8 + bool "fDTS/8" + +config STM32L4_QENCODER_SAMPLE_FDTS_16 + bool "fDTS/16" + +config STM32L4_QENCODER_SAMPLE_FDTS_32 + bool "fDTS/32" + +endchoice + +choice + depends on STM32L4_QENCODER_FILTER + prompt "Input channel event count" + default STM32L4_QENCODER_SAMPLE_EVENT_6 + +config STM32L4_QENCODER_SAMPLE_EVENT_1 + depends on STM32L4_QENCODER_SAMPLE_FDTS + bool "1" + +config STM32L4_QENCODER_SAMPLE_EVENT_2 + depends on STM32L4_QENCODER_SAMPLE_CKINT + bool "2" + +config STM32L4_QENCODER_SAMPLE_EVENT_4 + depends on STM32L4_QENCODER_SAMPLE_CKINT + bool "4" + +config STM32L4_QENCODER_SAMPLE_EVENT_5 + depends on STM32L4_QENCODER_SAMPLE_FDTS_16 || STM32L4_QENCODER_SAMPLE_FDTS_32 + bool "5" + +config STM32L4_QENCODER_SAMPLE_EVENT_6 + depends on !STM32L4_QENCODER_SAMPLE_FDTS && !STM32L4_QENCODER_SAMPLE_CKINT + bool "6" + +config STM32L4_QENCODER_SAMPLE_EVENT_8 + depends on !STM32L4_QENCODER_SAMPLE_FDTS + bool "8" + +endchoice + +endmenu + endif # ARCH_CHIP_STM32L4 diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index d265c2a4f5..70199cceee 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -195,6 +195,10 @@ ifeq ($(CONFIG_PWM),y) CHIP_CSRCS += stm32l4_pwm.c endif +ifeq ($(CONFIG_QENCODER),y) +CHIP_CSRCS += stm32l4_qencoder.c +endif + ifeq ($(CONFIG_STM32L4_QSPI),y) CHIP_CSRCS += stm32l4_qspi.c endif diff --git a/arch/arm/src/stm32l4/chip/stm32l4x6xx_pinmap.h b/arch/arm/src/stm32l4/chip/stm32l4x6xx_pinmap.h index c4ebc1413c..00fa2fa37a 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4x6xx_pinmap.h +++ b/arch/arm/src/stm32l4/chip/stm32l4x6xx_pinmap.h @@ -500,14 +500,22 @@ /* Timers */ -#define GPIO_TIM1_CH1_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN8) -#define GPIO_TIM1_CH1_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTE|GPIO_PIN9) -#define GPIO_TIM1_CH2_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN9) -#define GPIO_TIM1_CH2_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTE|GPIO_PIN11) -#define GPIO_TIM1_CH3_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN10) -#define GPIO_TIM1_CH3_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTE|GPIO_PIN13) -#define GPIO_TIM1_CH4_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN11) -#define GPIO_TIM1_CH4_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTE|GPIO_PIN14) +#define GPIO_TIM1_CH1IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN8) +#define GPIO_TIM1_CH1IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN9) +#define GPIO_TIM1_CH1OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) +#define GPIO_TIM1_CH1OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN9) +#define GPIO_TIM1_CH2IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN9) +#define GPIO_TIM1_CH2IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN11) +#define GPIO_TIM1_CH2OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9) +#define GPIO_TIM1_CH2OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN11) +#define GPIO_TIM1_CH3IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN10) +#define GPIO_TIM1_CH3IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN13) +#define GPIO_TIM1_CH3OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10) +#define GPIO_TIM1_CH3OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN13) +#define GPIO_TIM1_CH4IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11) +#define GPIO_TIM1_CH4IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN14) +#define GPIO_TIM1_CH4OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) +#define GPIO_TIM1_CH4OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN14) #define GPIO_TIM1_CH1N_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN7) #define GPIO_TIM1_CH1N_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN13) #define GPIO_TIM1_CH1N_3 (GPIO_ALT|GPIO_AF1 |GPIO_PORTE|GPIO_PIN8) @@ -529,61 +537,104 @@ #define GPIO_TIM1_ETR_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN12) #define GPIO_TIM1_ETR_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTE|GPIO_PIN7) -#define GPIO_TIM2_CH1_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN0) -#define GPIO_TIM2_CH1_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN5) -#define GPIO_TIM2_CH1_3 (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN15) -#define GPIO_TIM2_CH2_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN1) -#define GPIO_TIM2_CH2_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN3) -#define GPIO_TIM2_CH3_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN2) -#define GPIO_TIM2_CH3_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN10) -#define GPIO_TIM2_CH4_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN3) -#define GPIO_TIM2_CH4_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN11) +#define GPIO_TIM2_CH1IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM2_CH1IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN5) +#define GPIO_TIM2_CH1IN_3 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN15) +#define GPIO_TIM2_CH1OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM2_CH1OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5) +#define GPIO_TIM2_CH1OUT_3 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15) +#define GPIO_TIM2_CH2IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM2_CH2IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN3) +#define GPIO_TIM2_CH2OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM2_CH2OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3) +#define GPIO_TIM2_CH3IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM2_CH3IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN10) +#define GPIO_TIM2_CH3OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM2_CH3OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10) +#define GPIO_TIM2_CH4IN_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM2_CH4IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN11) +#define GPIO_TIM2_CH4OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM2_CH4OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11) #define GPIO_TIM2_BKIN (GPIO_ALT|GPIO_AF2 |GPIO_PORTE|GPIO_PIN14) #define GPIO_TIM2_ETR_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN0) #define GPIO_TIM2_ETR_2 (GPIO_ALT|GPIO_AF2 |GPIO_PORTA|GPIO_PIN5) #define GPIO_TIM2_ETR_3 (GPIO_ALT|GPIO_AF2 |GPIO_PORTA|GPIO_PIN15) -#define GPIO_TIM3_CH1_1 (GPIO_ALT|GPIO_AF2 |GPIO_PORTA|GPIO_PIN6) -#define GPIO_TIM3_CH1_2 (GPIO_ALT|GPIO_AF2 |GPIO_PORTB|GPIO_PIN4) -#define GPIO_TIM3_CH1_3 (GPIO_ALT|GPIO_AF2 |GPIO_PORTC|GPIO_PIN6) -#define GPIO_TIM3_CH1_4 (GPIO_ALT|GPIO_AF2 |GPIO_PORTE|GPIO_PIN3) -#define GPIO_TIM3_CH2_1 (GPIO_ALT|GPIO_AF2 |GPIO_PORTA|GPIO_PIN7) -#define GPIO_TIM3_CH2_2 (GPIO_ALT|GPIO_AF2 |GPIO_PORTB|GPIO_PIN5) -#define GPIO_TIM3_CH2_3 (GPIO_ALT|GPIO_AF2 |GPIO_PORTC|GPIO_PIN7) -#define GPIO_TIM3_CH2_4 (GPIO_ALT|GPIO_AF2 |GPIO_PORTE|GPIO_PIN4) -#define GPIO_TIM3_CH3_1 (GPIO_ALT|GPIO_AF2 |GPIO_PORTB|GPIO_PIN0) -#define GPIO_TIM3_CH3_2 (GPIO_ALT|GPIO_AF2 |GPIO_PORTC|GPIO_PIN8) -#define GPIO_TIM3_CH3_3 (GPIO_ALT|GPIO_AF2 |GPIO_PORTE|GPIO_PIN5) -#define GPIO_TIM3_CH4_1 (GPIO_ALT|GPIO_AF2 |GPIO_PORTB|GPIO_PIN1) -#define GPIO_TIM3_CH4_2 (GPIO_ALT|GPIO_AF2 |GPIO_PORTC|GPIO_PIN9) -#define GPIO_TIM3_CH4_3 (GPIO_ALT|GPIO_AF2 |GPIO_PORTE|GPIO_PIN6) +#define GPIO_TIM3_CH1IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM3_CH1IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN4) +#define GPIO_TIM3_CH1IN_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM3_CH1IN_4 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN3) +#define GPIO_TIM3_CH1OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM3_CH1OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4) +#define GPIO_TIM3_CH1OUT_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM3_CH1OUT_4 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN3) +#define GPIO_TIM3_CH2IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM3_CH2IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN5) +#define GPIO_TIM3_CH2IN_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM3_CH2IN_4 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN4) +#define GPIO_TIM3_CH2OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM3_CH2OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) +#define GPIO_TIM3_CH2OUT_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM3_CH2OUT_4 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN4) +#define GPIO_TIM3_CH3IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM3_CH3IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM3_CH3IN_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN5) +#define GPIO_TIM3_CH3OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM3_CH3OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM3_CH3OUT_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5) +#define GPIO_TIM3_CH4IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM3_CH4IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM3_CH4IN_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN6) +#define GPIO_TIM3_CH4OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM3_CH4OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM3_CH4OUT_3 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN6) #define GPIO_TIM3_ETR_1 (GPIO_ALT|GPIO_AF2 |GPIO_PORTD|GPIO_PIN2) #define GPIO_TIM3_ETR_2 (GPIO_ALT|GPIO_AF2 |GPIO_PORTE|GPIO_PIN2) -#define GPIO_TIM4_CH1_1 (GPIO_ALT|GPIO_AF2 |GPIO_PORTB|GPIO_PIN6) -#define GPIO_TIM4_CH1_2 (GPIO_ALT|GPIO_AF2 |GPIO_PORTD|GPIO_PIN12) -#define GPIO_TIM4_CH2_1 (GPIO_ALT|GPIO_AF2 |GPIO_PORTB|GPIO_PIN7) -#define GPIO_TIM4_CH2_2 (GPIO_ALT|GPIO_AF2 |GPIO_PORTD|GPIO_PIN13) -#define GPIO_TIM4_CH3_1 (GPIO_ALT|GPIO_AF2 |GPIO_PORTB|GPIO_PIN8) -#define GPIO_TIM4_CH3_2 (GPIO_ALT|GPIO_AF2 |GPIO_PORTD|GPIO_PIN14) -#define GPIO_TIM4_CH4_1 (GPIO_ALT|GPIO_AF2 |GPIO_PORTB|GPIO_PIN9) -#define GPIO_TIM4_CH4_2 (GPIO_ALT|GPIO_AF2 |GPIO_PORTD|GPIO_PIN15) +#define GPIO_TIM4_CH1IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN6) +#define GPIO_TIM4_CH1IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN12) +#define GPIO_TIM4_CH1OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6) +#define GPIO_TIM4_CH1OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN12) +#define GPIO_TIM4_CH2IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM4_CH2IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN13) +#define GPIO_TIM4_CH2OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM4_CH2OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN13) +#define GPIO_TIM4_CH3IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM4_CH3IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN14) +#define GPIO_TIM4_CH3OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM4_CH3OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN14) +#define GPIO_TIM4_CH4IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM4_CH4IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTD|GPIO_PIN15) +#define GPIO_TIM4_CH4OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM4_CH4OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN15) #define GPIO_TIM4_ETR (GPIO_ALT|GPIO_AF2 |GPIO_PORTE|GPIO_PIN0) -#define GPIO_TIM5_CH1_1 (GPIO_ALT|GPIO_AF2 |GPIO_PORTA|GPIO_PIN0) -#define GPIO_TIM5_CH1_2 (GPIO_ALT|GPIO_AF2 |GPIO_PORTF|GPIO_PIN6) -#define GPIO_TIM5_CH2_1 (GPIO_ALT|GPIO_AF2 |GPIO_PORTA|GPIO_PIN1) -#define GPIO_TIM5_CH2_2 (GPIO_ALT|GPIO_AF2 |GPIO_PORTF|GPIO_PIN7) -#define GPIO_TIM5_CH3_1 (GPIO_ALT|GPIO_AF2 |GPIO_PORTA|GPIO_PIN2) -#define GPIO_TIM5_CH3_2 (GPIO_ALT|GPIO_AF2 |GPIO_PORTF|GPIO_PIN8) -#define GPIO_TIM5_CH4_1 (GPIO_ALT|GPIO_AF2 |GPIO_PORTA|GPIO_PIN3) -#define GPIO_TIM5_CH4_2 (GPIO_ALT|GPIO_AF2 |GPIO_PORTF|GPIO_PIN9) +#define GPIO_TIM5_CH1IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM5_CH1IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN6) +#define GPIO_TIM5_CH1OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM5_CH1OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN6) +#define GPIO_TIM5_CH2IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM5_CH2IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN7) +#define GPIO_TIM5_CH2OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM5_CH2OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN7) +#define GPIO_TIM5_CH3IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM5_CH3IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN8) +#define GPIO_TIM5_CH3OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM5_CH3OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN8) +#define GPIO_TIM5_CH4IN_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM5_CH4IN_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9) +#define GPIO_TIM5_CH4OUT_1 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM5_CH4OUT_2 (GPIO_ALT|GPIO_AF2 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9) #define GPIO_TIM5_ETR (GPIO_ALT|GPIO_AF1 |GPIO_PORTF|GPIO_PIN6) -#define GPIO_TIM8_CH1 (GPIO_ALT|GPIO_AF3 |GPIO_PORTC|GPIO_PIN6) -#define GPIO_TIM8_CH2 (GPIO_ALT|GPIO_AF3 |GPIO_PORTC|GPIO_PIN7) -#define GPIO_TIM8_CH3 (GPIO_ALT|GPIO_AF3 |GPIO_PORTC|GPIO_PIN8) -#define GPIO_TIM8_CH4 (GPIO_ALT|GPIO_AF3 |GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM8_CH1IN (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM8_CH1OUT (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM8_CH2IN (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM8_CH2OUT (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM8_CH3IN (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM8_CH3OUT (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM8_CH4IN (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM8_CH4OUT (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) #define GPIO_TIM8_CH1N_1 (GPIO_ALT|GPIO_AF3 |GPIO_PORTA|GPIO_PIN5) #define GPIO_TIM8_CH1N_2 (GPIO_ALT|GPIO_AF3 |GPIO_PORTA|GPIO_PIN7) #define GPIO_TIM8_CH2N_1 (GPIO_ALT|GPIO_AF3 |GPIO_PORTB|GPIO_PIN0) @@ -600,29 +651,43 @@ #define GPIO_TIM8_BKIN2_COMP2 (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN6) #define GPIO_TIM8_ETR (GPIO_ALT|GPIO_AF3 |GPIO_PORTA|GPIO_PIN0) -#define GPIO_TIM15_CH1_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN2) -#define GPIO_TIM15_CH1_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN14) -#define GPIO_TIM15_CH1_3 (GPIO_ALT|GPIO_AF14|GPIO_PORTF|GPIO_PIN9) -#define GPIO_TIM15_CH1_4 (GPIO_ALT|GPIO_AF14|GPIO_PORTG|GPIO_PIN10) -#define GPIO_TIM15_CH2_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN3) -#define GPIO_TIM15_CH2_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN15) -#define GPIO_TIM15_CH2_3 (GPIO_ALT|GPIO_AF14|GPIO_PORTF|GPIO_PIN10) -#define GPIO_TIM15_CH2_4 (GPIO_ALT|GPIO_AF14|GPIO_PORTG|GPIO_PIN11) +#define GPIO_TIM15_CH1IN_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM15_CH1IN_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM15_CH1IN_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN9) +#define GPIO_TIM15_CH1IN_4 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTG|GPIO_PIN10) +#define GPIO_TIM15_CH1OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) +#define GPIO_TIM15_CH1OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM15_CH1OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN9) +#define GPIO_TIM15_CH1OUT_4 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN10) +#define GPIO_TIM15_CH2IN_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM15_CH2IN_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM15_CH2IN_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN10) +#define GPIO_TIM15_CH2IN_4 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTG|GPIO_PIN11) +#define GPIO_TIM15_CH2OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM15_CH2OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM15_CH2OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN10) +#define GPIO_TIM15_CH2OUT_4 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11) #define GPIO_TIM15_CH1N_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN1) #define GPIO_TIM15_CH1N_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN13) #define GPIO_TIM15_CH1N_3 (GPIO_ALT|GPIO_AF14|GPIO_PORTG|GPIO_PIN9) #define GPIO_TIM15_BKIN_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN9) #define GPIO_TIM15_BKIN_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN12) -#define GPIO_TIM16_CH1_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN6) -#define GPIO_TIM16_CH1_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN8) -#define GPIO_TIM16_CH1_3 (GPIO_ALT|GPIO_AF14|GPIO_PORTE|GPIO_PIN0) +#define GPIO_TIM16_CH1IN_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM16_CH1IN_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM16_CH1IN_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN0) +#define GPIO_TIM16_CH1OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM16_CH1OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) +#define GPIO_TIM16_CH1OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0) #define GPIO_TIM16_CH1N (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN6) #define GPIO_TIM16_BKIN (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN5) -#define GPIO_TIM17_CH1_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN7) -#define GPIO_TIM17_CH1_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN9) -#define GPIO_TIM17_CH1_3 (GPIO_ALT|GPIO_AF14|GPIO_PORTE|GPIO_PIN1) +#define GPIO_TIM17_CH1IN_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM17_CH1IN_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM17_CH1IN_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN1) +#define GPIO_TIM17_CH1OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM17_CH1OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) +#define GPIO_TIM17_CH1OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1) #define GPIO_TIM17_CH1N (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN7) #define GPIO_TIM17_BKIN_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN10) #define GPIO_TIM17_BKIN_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN4) diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.c b/arch/arm/src/stm32l4/stm32l4_qencoder.c new file mode 100644 index 0000000000..7c9426de29 --- /dev/null +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.c @@ -0,0 +1,1248 @@ +/************************************************************************************ + * arch/arm/src/stm32l4/stm32;4_qencoder.c + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * Diego Sanchez + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "up_internal.h" +#include "up_arch.h" + +#include "stm32l4.h" +#include "stm32l4_gpio.h" +#include "stm32l4_tim.h" +#include "stm32l4_qencoder.h" + +#ifdef CONFIG_QENCODER + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Clocking *************************************************************************/ +/* The CLKOUT value should not exceed the CLKIN value */ + +#if defined(CONFIG_STM32L4_TIM1_QE) && CONFIG_STM32L4_TIM1_QECLKOUT > STM32L4_APB2_TIM1_CLKIN +# warning "CONFIG_STM32L4_TIM1_QECLKOUT exceeds STM32L4_APB2_TIM1_CLKIN" +#endif + +#if defined(CONFIG_STM32L4_TIM2_QE) && CONFIG_STM32L4_TIM2_QECLKOUT > STM32L4_APB1_TIM2_CLKIN +# warning "CONFIG_STM32L4_TIM2_QECLKOUT exceeds STM32L4_APB2_TIM2_CLKIN" +#endif + +#if defined(CONFIG_STM32L4_TIM3_QE) && CONFIG_STM32L4_TIM3_QECLKOUT > STM32L4_APB1_TIM3_CLKIN +# warning "CONFIG_STM32L4_TIM3_QECLKOUT exceeds STM32L4_APB2_TIM3_CLKIN" +#endif + +#if defined(CONFIG_STM32L4_TIM4_QE) && CONFIG_STM32L4_TIM4_QECLKOUT > STM32L4_APB1_TIM4_CLKIN +# warning "CONFIG_STM32L4_TIM4_QECLKOUT exceeds STM32L4_APB2_TIM4_CLKIN" +#endif + +#if defined(CONFIG_STM32L4_TIM5_QE) && CONFIG_STM32L4_TIM5_QECLKOUT > STM32L4_APB1_TIM5_CLKIN +# warning "CONFIG_STM32L4_TIM5_QECLKOUT exceeds STM32L4_APB2_TIM5_CLKIN" +#endif + +#if defined(CONFIG_STM32L4_TIM8_QE) && CONFIG_STM32L4_TIM8_QECLKOUT > STM32L4_APB2_TIM8_CLKIN +# warning "CONFIG_STM32L4_TIM8_QECLKOUT exceeds STM32L4_APB2_TIM8_CLKIN" +#endif + +/* Timers ***************************************************************************/ + +#undef HAVE_32BIT_TIMERS +#undef HAVE_16BIT_TIMERS + +/* On the L4 series, TIM2 and TIM5 are 32-bit. All of the rest are 16-bit */ + +/* If TIM2 or TIM5 are enabled, then we have 32-bit timers */ + +#if defined(CONFIG_STM32L4_TIM2_QE) || defined(CONFIG_STM32L4_TIM5_QE) +# define HAVE_32BIT_TIMERS 1 +#endif + +/* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */ + +#if defined(CONFIG_STM32L4_TIM1_QE) || defined(CONFIG_STM32L4_TIM3_QE) || \ + defined(CONFIG_STM32L4_TIM4_QE) || defined(CONFIG_STM32L4_TIM8_QE) +# define HAVE_16BIT_TIMERS 1 +#endif + + /* The width in bits of each timer */ + +#define TIM1_BITWIDTH 16 +#define TIM2_BITWIDTH 32 +#define TIM3_BITWIDTH 16 +#define TIM4_BITWIDTH 16 +#define TIM5_BITWIDTH 32 +#define TIM8_BITWIDTH 16 + +/* Do we need to support mixed 16- and 32-bit timers */ + +#undef HAVE_MIXEDWIDTH_TIMERS +#if defined(HAVE_16BIT_TIMERS) && defined(HAVE_32BIT_TIMERS) +# define HAVE_MIXEDWIDTH_TIMERS 1 +#endif + +/* Input filter *********************************************************************/ + +#ifdef CONFIG_STM32L4_QENCODER_FILTER +# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS) +# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_1) +# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_NOFILT +# endif +# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_CKINT) +# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_2) +# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 +# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_4) +# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 +# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) +# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 +# endif +# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_2) +# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) +# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 +# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) +# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 +# endif +# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_4) +# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) +# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 +# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) +# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 +# endif +# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_8) +# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) +# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 +# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) +# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 +# endif +# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_16) +# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_5) +# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 +# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) +# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 +# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) +# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 +# endif +# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_32) +# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_5) +# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 +# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) +# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 +# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) +# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 +# endif +# endif + +# ifndef STM32L4_QENCODER_ICF +# warning "Invalid encoder filter combination, filter disabled" +# endif +#endif + +#ifndef STM32L4_QENCODER_ICF +# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_NOFILT +#endif + +#define STM32L4_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) + +/* Debug ****************************************************************************/ +/* Non-standard debug that may be enabled just for testing the quadrature encoder */ + +#ifndef CONFIG_DEBUG_FEATURES +# undef CONFIG_DEBUG_SENSORS +#endif + +#ifdef CONFIG_DEBUG_SENSORS +# ifdef CONFIG_DEBUG_INFO +# define qe_dumpgpio(p,m) stm32l4_dumpgpio(p,m) +# else +# define qe_dumpgpio(p,m) +# endif +#else +# define qe_dumpgpio(p,m) +#endif + +/************************************************************************************ + * Private Types + ************************************************************************************/ + +/* Constant configuration structure that is retained in FLASH */ + +struct stm32l4_qeconfig_s +{ + uint8_t timid; /* Timer ID {1,2,3,4,5,8} */ + uint8_t irq; /* Timer update IRQ */ +#ifdef HAVE_MIXEDWIDTH_TIMERS + uint8_t width; /* Timer width (16- or 32-bits) */ +#endif + uint32_t ti1cfg; /* TI1 input pin configuration (20-bit encoding) */ + uint32_t ti2cfg; /* TI2 input pin configuration (20-bit encoding) */ + uint32_t base; /* Register base address */ + uint32_t psc; /* Timer input clock prescaler */ + xcpt_t handler; /* Interrupt handler for this IRQ */ +}; + +/* Overall, RAM-based state structure */ + +struct stm32l4_lowerhalf_s +{ + /* The first field of this state structure must be a pointer to the lower- + * half callback structure: + */ + + FAR const struct qe_ops_s *ops; /* Lower half callback structure */ + + /* STM32 driver-specific fields: */ + + FAR const struct stm32l4_qeconfig_s *config; /* static onfiguration */ + + bool inuse; /* True: The lower-half driver is in-use */ + +#ifdef HAVE_16BIT_TIMERS + volatile int32_t position; /* The current position offset */ +#endif +}; + +/************************************************************************************ + * Private Function Prototypes + ************************************************************************************/ +/* Helper functions */ + +static uint16_t stm32l4_getreg16(FAR struct stm32l4_lowerhalf_s *priv, int offset); +static void stm32l4_putreg16(FAR struct stm32l4_lowerhalf_s *priv, int offset, uint16_t value); +static uint32_t stm32l4_getreg32(FAR struct stm32l4_lowerhalf_s *priv, int offset); +static void stm32l4_putreg32(FAR struct stm32l4_lowerhalf_s *priv, int offset, uint32_t value); + +#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) +static void stm32l4_dumpregs(FAR struct stm32l4_lowerhalf_s *priv, FAR const char *msg); +#else +# define stm32l4_dumpregs(priv,msg) +#endif + +static FAR struct stm32l4_lowerhalf_s *stm32l4_tim2lower(int tim); + +/* Interrupt handling */ + +#ifdef HAVE_16BIT_TIMERS +static int stm32l4_interrupt(FAR struct stm32l4_lowerhalf_s *priv); +#if defined(CONFIG_STM32L4_TIM1_QE) && TIM1_BITWIDTH == 16 +static int stm32l4_tim1interrupt(int irq, FAR void *context); +#endif +#if defined(CONFIG_STM32L4_TIM2_QE) && TIM2_BITWIDTH == 16 +static int stm32l4_tim2interrupt(int irq, FAR void *context); +#endif +#if defined(CONFIG_STM32L4_TIM3_QE) && TIM3_BITWIDTH == 16 +static int stm32l4_tim3interrupt(int irq, FAR void *context); +#endif +#if defined(CONFIG_STM32L4_TIM4_QE) && TIM4_BITWIDTH == 16 +static int stm32l4_tim4interrupt(int irq, FAR void *context); +#endif +#if defined(CONFIG_STM32L4_TIM5_QE) && TIM5_BITWIDTH == 16 +static int stm32l4_tim5interrupt(int irq, FAR void *context); +#endif +#if defined(CONFIG_STM32L4_TIM8_QE) && TIM8_BITWIDTH == 16 +static int stm32l4_tim8interrupt(int irq, FAR void *context); +#endif +#endif + +/* Lower-half Quadrature Encoder Driver Methods */ + +static int stm32l4_setup(FAR struct qe_lowerhalf_s *lower); +static int stm32l4_shutdown(FAR struct qe_lowerhalf_s *lower); +static int stm32l4_position(FAR struct qe_lowerhalf_s *lower, FAR int32_t *pos); +static int stm32l4_reset(FAR struct qe_lowerhalf_s *lower); +static int stm32l4_ioctl(FAR struct qe_lowerhalf_s *lower, int cmd, unsigned long arg); + +/************************************************************************************ + * Private Data + ************************************************************************************/ +/* The lower half callback structure */ + +static const struct qe_ops_s g_qecallbacks = +{ + .setup = stm32l4_setup, + .shutdown = stm32l4_shutdown, + .position = stm32l4_position, + .reset = stm32l4_reset, + .ioctl = stm32l4_ioctl, +}; + +/* Per-timer state structures */ + +#ifdef CONFIG_STM32L4_TIM1_QE +static const struct stm32l4_qeconfig_s g_tim1config = +{ + .timid = 1, + .irq = STM32L4_IRQ_TIM1UP, +#ifdef HAVE_MIXEDWIDTH_TIMERS + .width = TIM1_BITWIDTH, +#endif + .base = STM32L4_TIM1_BASE, + .psc = (STM32L4_APB2_TIM1_CLKIN / CONFIG_STM32L4_TIM1_QECLKOUT) - 1, + .ti1cfg = GPIO_TIM1_CH1IN, + .ti2cfg = GPIO_TIM1_CH2IN, +#if TIM1_BITWIDTH == 16 + .handler = stm32l4_tim1interrupt, +#endif +}; + +static struct stm32l4_lowerhalf_s g_tim1lower = +{ + .ops = &g_qecallbacks, + .config = &g_tim1config, + .inuse = false, +}; + +#endif + +#ifdef CONFIG_STM32L4_TIM2_QE +static const struct stm32l4_qeconfig_s g_tim2config = +{ + .timid = 2, + .irq = STM32L4_IRQ_TIM2, +#ifdef HAVE_MIXEDWIDTH_TIMERS + .width = TIM2_BITWIDTH, +#endif + .base = STM32L4_TIM2_BASE, + .psc = (STM32L4_APB1_TIM2_CLKIN / CONFIG_STM32L4_TIM2_QECLKOUT) - 1, + .ti1cfg = GPIO_TIM2_CH1IN, + .ti2cfg = GPIO_TIM2_CH2IN, +#if TIM2_BITWIDTH == 16 + .handler = stm32l4_tim2interrupt, +#endif +}; + +static struct stm32l4_lowerhalf_s g_tim2lower = +{ + .ops = &g_qecallbacks, + .config = &g_tim2config, + .inuse = false, +}; + +#endif + +#ifdef CONFIG_STM32L4_TIM3_QE +static const struct stm32l4_qeconfig_s g_tim3config = +{ + .timid = 3, + .irq = STM32L4_IRQ_TIM3, +#ifdef HAVE_MIXEDWIDTH_TIMERS + .width = TIM3_BITWIDTH, +#endif + .base = STM32L4_TIM3_BASE, + .psc = (STM32L4_APB1_TIM3_CLKIN / CONFIG_STM32L4_TIM3_QECLKOUT) - 1, + .ti1cfg = GPIO_TIM3_CH1IN, + .ti2cfg = GPIO_TIM3_CH2IN, +#if TIM3_BITWIDTH == 16 + .handler = stm32l4_tim3interrupt, +#endif +}; + +static struct stm32l4_lowerhalf_s g_tim3lower = +{ + .ops = &g_qecallbacks, + .config = &g_tim3config, + .inuse = false, +}; + +#endif + +#ifdef CONFIG_STM32L4_TIM4_QE +static const struct stm32l4_qeconfig_s g_tim4config = +{ + .timid = 4, + .irq = STM32L4_IRQ_TIM4, +#ifdef HAVE_MIXEDWIDTH_TIMERS + .width = TIM4_BITWIDTH, +#endif + .base = STM32L4_TIM4_BASE, + .psc = (STM32L4_APB1_TIM4_CLKIN / CONFIG_STM32L4_TIM4_QECLKOUT) - 1, + .ti1cfg = GPIO_TIM4_CH1IN, + .ti2cfg = GPIO_TIM4_CH2IN, +#if TIM4_BITWIDTH == 16 + .handler = stm32l4_tim4interrupt, +#endif +}; + +static struct stm32l4_lowerhalf_s g_tim4lower = +{ + .ops = &g_qecallbacks, + .config = &g_tim4config, + .inuse = false, +}; + +#endif + +#ifdef CONFIG_STM32L4_TIM5_QE +static const struct stm32l4_qeconfig_s g_tim5config = +{ + .timid = 5, + .irq = STM32L4_IRQ_TIM5, +#ifdef HAVE_MIXEDWIDTH_TIMERS + .width = TIM5_BITWIDTH, +#endif + .base = STM32L4_TIM5_BASE, + .psc = (STM32L4_APB1_TIM5_CLKIN / CONFIG_STM32L4_TIM5_QECLKOUT) - 1, + .ti1cfg = GPIO_TIM5_CH1IN, + .ti2cfg = GPIO_TIM5_CH2IN, +#if TIM5_BITWIDTH == 16 + .handler = stm32l4_tim5interrupt, +#endif +}; + +static struct stm32l4_lowerhalf_s g_tim5lower = +{ + .ops = &g_qecallbacks, + .config = &g_tim5config, + .inuse = false, +}; + +#endif + +#ifdef CONFIG_STM32L4_TIM8_QE +static const struct stm32l4_qeconfig_s g_tim8config = +{ + .timid = 8, + .irq = STM32L4_IRQ_TIM8UP, +#ifdef HAVE_MIXEDWIDTH_TIMERS + .width = TIM8_BITWIDTH, +#endif + .base = STM32L4_TIM8_BASE, + .psc = (STM32L4_APB2_TIM8_CLKIN / CONFIG_STM32L4_TIM8_QECLKOUT) - 1, + .ti1cfg = GPIO_TIM8_CH1IN, + .ti2cfg = GPIO_TIM8_CH2IN, +#if TIM8_BITWIDTH == 16 + .handler = stm32l4_tim8interrupt, +#endif +}; + +static struct stm32l4_lowerhalf_s g_tim8lower = +{ + .ops = &g_qecallbacks, + .config = &g_tim8config, + .inuse = false, +}; + +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32l4_getreg16 + * + * Description: + * Read the value of a 16-bit timer register. + * + * Input Parameters: + * priv - A reference to the lower half status + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ************************************************************************************/ + +static uint16_t stm32l4_getreg16(struct stm32l4_lowerhalf_s *priv, int offset) +{ + return getreg16(priv->config->base + offset); +} + +/************************************************************************************ + * Name: stm32l4_putreg16 + * + * Description: + * Write a value to a 16-bit timer register. + * + * Input Parameters: + * priv - A reference to the lower half status + * offset - The offset to the register to read + * + * Returned Value: + * None + * + ************************************************************************************/ + +static void stm32l4_putreg16(FAR struct stm32l4_lowerhalf_s *priv, int offset, + uint16_t value) +{ + putreg16(value, priv->config->base + offset); +} + +/************************************************************************************ + * Name: stm32l4_getreg32 + * + * Description: + * Read the value of a 32-bit timer register. This applies only for the STM32 F4 + * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5 (but works OK + * with the 16-bit TIM1,8 and F1 registers as well). + * + * Input Parameters: + * priv - A reference to the lower half status + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ************************************************************************************/ + +static uint32_t stm32l4_getreg32(FAR struct stm32l4_lowerhalf_s *priv, int offset) +{ + return getreg32(priv->config->base + offset); +} + +/************************************************************************************ + * Name: stm32l4_putreg16 + * + * Description: + * Write a value to a 32-bit timer register. This applies only for the STM32 F4 + * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5 (but works OK + * with the 16-bit TIM1,8 and F1 registers). + * + * Input Parameters: + * priv - A reference to the lower half status + * offset - The offset to the register to read + * + * Returned Value: + * None + * + ************************************************************************************/ + +static void stm32l4_putreg32(FAR struct stm32l4_lowerhalf_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->config->base + offset); +} + +/**************************************************************************** + * Name: stm32l4_dumpregs + * + * Description: + * Dump all timer registers. + * + * Input parameters: + * priv - A reference to the QENCODER block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) +static void stm32l4_dumpregs(FAR struct stm32l4_lowerhalf_s *priv, + FAR const char *msg) +{ + sninfo("%s:\n", msg); + sninfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", + stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET), + stm32l4_getreg16(priv, STM32L4_GTIM_CR2_OFFSET), + stm32l4_getreg16(priv, STM32L4_GTIM_SMCR_OFFSET), + stm32l4_getreg16(priv, STM32L4_GTIM_DIER_OFFSET)); + sninfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", + stm32l4_getreg16(priv, STM32L4_GTIM_SR_OFFSET), + stm32l4_getreg16(priv, STM32L4_GTIM_EGR_OFFSET), + stm32l4_getreg16(priv, STM32L4_GTIM_CCMR1_OFFSET), + stm32l4_getreg16(priv, STM32L4_GTIM_CCMR2_OFFSET)); + sninfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", + stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET), + stm32l4_getreg16(priv, STM32L4_GTIM_CNT_OFFSET), + stm32l4_getreg16(priv, STM32L4_GTIM_PSC_OFFSET), + stm32l4_getreg16(priv, STM32L4_GTIM_ARR_OFFSET)); + sninfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", + stm32l4_getreg16(priv, STM32L4_GTIM_CCR1_OFFSET), + stm32l4_getreg16(priv, STM32L4_GTIM_CCR2_OFFSET), + stm32l4_getreg16(priv, STM32L4_GTIM_CCR3_OFFSET), + stm32l4_getreg16(priv, STM32L4_GTIM_CCR4_OFFSET)); +#if defined(CONFIG_STM32L4_TIM1_QE) || defined(CONFIG_STM32L4_TIM8_QE) + if (priv->config->timid == 1 || priv->config->timid == 8) + { + sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", + stm32l4_getreg16(priv, STM32L4_ATIM_RCR_OFFSET), + stm32l4_getreg16(priv, STM32L4_ATIM_BDTR_OFFSET), + stm32l4_getreg16(priv, STM32L4_ATIM_DCR_OFFSET), + stm32l4_getreg16(priv, STM32L4_ATIM_DMAR_OFFSET)); + } + else +#endif + { + sninfo(" DCR: %04x DMAR: %04x\n", + stm32l4_getreg16(priv, STM32L4_GTIM_DCR_OFFSET), + stm32l4_getreg16(priv, STM32L4_GTIM_DMAR_OFFSET)); + } +} +#endif + +/************************************************************************************ + * Name: stm32l4_tim2lower + * + * Description: + * Map a timer number to a device structure + * + ************************************************************************************/ + +static FAR struct stm32l4_lowerhalf_s *stm32l4_tim2lower(int tim) +{ + switch (tim) + { +#ifdef CONFIG_STM32L4_TIM1_QE + case 1: + return &g_tim1lower; +#endif +#ifdef CONFIG_STM32L4_TIM2_QE + case 2: + return &g_tim2lower; +#endif +#ifdef CONFIG_STM32L4_TIM3_QE + case 3: + return &g_tim3lower; +#endif +#ifdef CONFIG_STM32L4_TIM4_QE + case 4: + return &g_tim4lower; +#endif +#ifdef CONFIG_STM32L4_TIM5_QE + case 5: + return &g_tim5lower; +#endif +#ifdef CONFIG_STM32L4_TIM8_QE + case 8: + return &g_tim8lower; +#endif + default: + return NULL; + } +} + +/************************************************************************************ + * Name: stm32l4_interrupt + * + * Description: + * Common timer interrupt handling. NOTE: Only 16-bit timers require timer + * interrupts. + * + ************************************************************************************/ + +#ifdef HAVE_16BIT_TIMERS +static int stm32l4_interrupt(FAR struct stm32l4_lowerhalf_s *priv) +{ + uint16_t regval; + + /* Verify that this is an update interrupt. Nothing else is expected. */ + + regval = stm32l4_getreg16(priv, STM32L4_GTIM_SR_OFFSET); + DEBUGASSERT((regval & ATIM_SR_UIF) != 0); + + /* Clear the UIF interrupt bit */ + + stm32l4_putreg16(priv, STM32L4_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); + + /* Check the direction bit in the CR1 register and add or subtract the + * maximum value, as appropriate. + */ + + regval = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET); + if ((regval & ATIM_CR1_DIR) != 0) + { + priv->position -= (int32_t)0x0000ffff; + } + else + { + priv->position += (int32_t)0x0000ffff; + } + + return OK; +} +#endif + +/************************************************************************************ + * Name: stm32l4_timNinterrupt + * + * Description: + * TIMN interrupt handler + * + ************************************************************************************/ + +#if defined(CONFIG_STM32L4_TIM1_QE) && TIM1_BITWIDTH == 16 +static int stm32l4_tim1interrupt(int irq, FAR void *context) +{ + return stm32l4_interrupt(&g_tim1lower); +} +#endif + +#if defined(CONFIG_STM32L4_TIM2_QE) && TIM2_BITWIDTH == 16 +static int stm32l4_tim2interrupt(int irq, FAR void *context) +{ + return stm32l4_interrupt(&g_tim2lower); +} +#endif + +#if defined(CONFIG_STM32L4_TIM3_QE) && TIM3_BITWIDTH == 16 +static int stm32l4_tim3interrupt(int irq, FAR void *context) +{ + return stm32l4_interrupt(&g_tim3lower); +} +#endif + +#if defined(CONFIG_STM32L4_TIM4_QE) && TIM4_BITWIDTH == 16 +static int stm32l4_tim4interrupt(int irq, FAR void *context) +{ + return stm32l4_interrupt(&g_tim4lower); +} +#endif + +#if defined(CONFIG_STM32L4_TIM5_QE) && TIM5_BITWIDTH == 16 +static int stm32l4_tim5interrupt(int irq, FAR void *context) +{ + return stm32l4_interrupt(&g_tim5lower); +} +#endif + +#if defined(CONFIG_STM32L4_TIM8_QE) && TIM8_BITWIDTH == 16 +static int stm32l4_tim8interrupt(int irq, FAR void *context) +{ + return stm32l4_interrupt(&g_tim8lower); +} +#endif + +/************************************************************************************ + * Name: stm32l4_setup + * + * Description: + * This method is called when the driver is opened. The lower half driver + * should configure and initialize the device so that it is ready for use. + * The initial position value should be zero. * + * + ************************************************************************************/ + +static int stm32l4_setup(FAR struct qe_lowerhalf_s *lower) +{ + FAR struct stm32l4_lowerhalf_s *priv = (FAR struct stm32l4_lowerhalf_s *)lower; + uint16_t dier; + uint16_t smcr; + uint16_t ccmr1; + uint16_t ccer; + uint16_t cr1; +#ifdef HAVE_16BIT_TIMERS + uint16_t regval; + int ret; +#endif + + /* NOTE: Clocking should have been enabled in the low-level RCC logic at boot-up */ + + /* Timer base configuration */ + + cr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET); + + /* Clear the direction bit (0=count up) and select the Counter Mode (0=Edge aligned) + * (Timers 2-5 and 1-8 only) + */ + + cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); + stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + + /* Set the Autoreload value */ + +#if defined(HAVE_MIXEDWIDTH_TIMERS) + if (priv->config->width == 32) + { + stm32l4_putreg32(priv, STM32L4_GTIM_ARR_OFFSET, 0xffffffff); + } + else + { + stm32l4_putreg16(priv, STM32L4_GTIM_ARR_OFFSET, 0xffff); + } +#elif defined(HAVE_32BIT_TIMERS) + stm32l4_putreg32(priv, STM32L4_GTIM_ARR_OFFSET, 0xffffffff); +#else + stm32l4_putreg16(priv, STM32L4_GTIM_ARR_OFFSET, 0xffff); +#endif + + /* Set the timer prescaler value. The clock input value (CLKIN) is based on the + * peripheral clock (PCLK) and a multiplier. These CLKIN values are provided in + * the board.h file. The prescaler value is then that CLKIN value divided by the + * configured CLKOUT value (minus one) + */ + + stm32l4_putreg16(priv, STM32L4_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); + +#if defined(CONFIG_STM32L4_TIM1_QE) || defined(CONFIG_STM32L4_TIM8_QE) + if (priv->config->timid == 1 || priv->config->timid == 8) + { + /* Clear the Repetition Counter value */ + + stm32l4_putreg16(priv, STM32L4_ATIM_RCR_OFFSET, 0); + } +#endif + + /* Generate an update event to reload the Prescaler + * and the repetition counter (only for TIM1 and TIM8) value immediately + */ + + stm32l4_putreg16(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG); + + /* GPIO pin configuration */ + + stm32l4_configgpio(priv->config->ti1cfg); + stm32l4_configgpio(priv->config->ti2cfg); + + /* Set the encoder Mode 3 */ + + smcr = stm32l4_getreg16(priv, STM32L4_GTIM_SMCR_OFFSET); + smcr &= ~GTIM_SMCR_SMS_MASK; + smcr |= GTIM_SMCR_ENCMD3; + stm32l4_putreg16(priv, STM32L4_GTIM_SMCR_OFFSET, smcr); + + /* TI1 Channel Configuration */ + /* Disable the Channel 1: Reset the CC1E Bit */ + + ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET); + ccer &= ~GTIM_CCER_CC1E; + stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + + ccmr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CCMR1_OFFSET); + ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET); + + /* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */ + + ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK); + ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT; + ccmr1 |= STM32L4_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; + + /* Select the Polarity=rising and set the CC1E Bit */ + + ccer &= ~(GTIM_CCER_CC1P | GTIM_CCER_CC1NP); + ccer |= GTIM_CCER_CC1E; + + /* Write to TIM CCMR1 and CCER registers */ + + stm32l4_putreg16(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); + stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + + /* Set the Input Capture Prescaler value: Capture performed each time an + * edge is detected on the capture input. + */ + + ccmr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CCMR1_OFFSET); + ccmr1 &= ~GTIM_CCMR1_IC1PSC_MASK; + ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC1PSC_SHIFT); + stm32l4_putreg16(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); + + /* TI2 Channel Configuration */ + /* Disable the Channel 2: Reset the CC2E Bit */ + + ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET); + ccer &= ~GTIM_CCER_CC2E; + stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + + ccmr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CCMR1_OFFSET); + ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET); + + /* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */ + + ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK); + ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT; + ccmr1 |= STM32L4_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; + + /* Select the Polarity=rising and set the CC2E Bit */ + + ccer &= ~(GTIM_CCER_CC2P | GTIM_CCER_CC2NP); + ccer |= GTIM_CCER_CC2E; + + /* Write to TIM CCMR1 and CCER registers */ + + stm32l4_putreg16(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); + stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + + /* Set the Input Capture Prescaler value: Capture performed each time an + * edge is detected on the capture input. + */ + + ccmr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CCMR1_OFFSET); + ccmr1 &= ~GTIM_CCMR1_IC2PSC_MASK; + ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC2PSC_SHIFT); + stm32l4_putreg16(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); + + /* Disable the update interrupt */ + + dier = stm32l4_getreg16(priv, STM32L4_GTIM_DIER_OFFSET); + dier &= ~GTIM_DIER_UIE; + stm32l4_putreg16(priv, STM32L4_GTIM_DIER_OFFSET, dier); + + /* There is no need for interrupts with 32-bit timers */ + +#ifdef HAVE_16BIT_TIMERS +#ifdef HAVE_MIXEDWIDTH_TIMERS + if (priv->config->width != 32) +#endif + { + /* Attach the interrupt handler */ + + ret = irq_attach(priv->config->irq, priv->config->handler); + if (ret < 0) + { + stm32l4_shutdown(lower); + return ret; + } + + /* Enable the update/global interrupt at the NVIC */ + + up_enable_irq(priv->config->irq); + } +#endif + + /* Reset the Update Disable Bit */ + + cr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET); + cr1 &= ~GTIM_CR1_UDIS; + stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + + /* Reset the URS Bit */ + + cr1 &= ~GTIM_CR1_URS; + stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + + /* There is no need for interrupts with 32-bit timers */ + +#ifdef HAVE_16BIT_TIMERS +#ifdef HAVE_MIXEDWIDTH_TIMERS + if (priv->config->width != 32) +#endif + { + /* Clear any pending update interrupts */ + + regval = stm32l4_getreg16(priv, STM32L4_GTIM_SR_OFFSET); + stm32l4_putreg16(priv, STM32L4_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); + + /* Then enable the update interrupt */ + + dier = stm32l4_getreg16(priv, STM32L4_GTIM_DIER_OFFSET); + dier |= GTIM_DIER_UIE; + stm32l4_putreg16(priv, STM32L4_GTIM_DIER_OFFSET, dier); + } +#endif + + /* Enable the TIM Counter */ + + cr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET); + cr1 |= GTIM_CR1_CEN; + stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + + return OK; +} + +/************************************************************************************ + * Name: stm32l4_shutdown + * + * Description: + * This method is called when the driver is closed. The lower half driver + * should stop data collection, free any resources, disable timer hardware, and + * put the system into the lowest possible power usage state * + * + ************************************************************************************/ + +static int stm32l4_shutdown(FAR struct qe_lowerhalf_s *lower) +{ + FAR struct stm32l4_lowerhalf_s *priv = (FAR struct stm32l4_lowerhalf_s *)lower; + irqstate_t flags; + uint32_t regaddr; + uint32_t regval; + uint32_t resetbit; + uint32_t pincfg; + + /* Disable the update/global interrupt at the NVIC */ + + flags = enter_critical_section(); + up_disable_irq(priv->config->irq); + + /* Detach the interrupt handler */ + + (void)irq_detach(priv->config->irq); + + /* Disable interrupts momentary to stop any ongoing timer processing and + * to prevent any concurrent access to the reset register. + */ + + /* Disable further interrupts and stop the timer */ + + stm32l4_putreg16(priv, STM32L4_GTIM_DIER_OFFSET, 0); + stm32l4_putreg16(priv, STM32L4_GTIM_SR_OFFSET, 0); + + /* Determine which timer to reset */ + + switch (priv->config->timid) + { +#ifdef CONFIG_STM32L4_TIM1_QE + case 1: + regaddr = STM32L4_RCC_APB2RSTR; + resetbit = RCC_APB2RSTR_TIM1RST; + break; +#endif +#ifdef CONFIG_STM32L4_TIM2_QE + case 2: + regaddr = STM32L4_RCC_APB1RSTR1; + resetbit = RCC_APB1RSTR1_TIM2RST; + break; +#endif +#ifdef CONFIG_STM32L4_TIM3_QE + case 3: + regaddr = STM32L4_RCC_APB1RSTR1; + resetbit = RCC_APB1RSTR1_TIM3RST; + break; +#endif +#ifdef CONFIG_STM32L4_TIM4_QE + case 4: + regaddr = STM32L4_RCC_APB1RSTR1; + resetbit = RCC_APB1RSTR1_TIM4RST; + break; +#endif +#ifdef CONFIG_STM32L4_TIM5_QE + case 5: + regaddr = STM32L4_RCC_APB1RSTR1; + resetbit = RCC_APB1RSTR1_TIM5RST; + break; +#endif +#ifdef CONFIG_STM32L4_TIM8_QE + case 8: + regaddr = STM32L4_RCC_APB2RSTR; + resetbit = RCC_APB2RSTR_TIM8RST; + break; +#endif + default: + return -EINVAL; + } + + /* Reset the timer - stopping the output and putting the timer back + * into a state where stm32l4_start() can be called. + */ + + regval = getreg32(regaddr); + regval |= resetbit; + putreg32(regval, regaddr); + + regval &= ~resetbit; + putreg32(regval, regaddr); + leave_critical_section(flags); + + sninfo("regaddr: %08x resetbit: %08x\n", regaddr, resetbit); + stm32l4_dumpregs(priv, "After stop"); + + /* Put the TI1 GPIO pin back to its default state */ + + pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); + pincfg |= STM32L4_GPIO_INPUT_FLOAT; + + stm32l4_configgpio(pincfg); + + /* Put the TI2 GPIO pin back to its default state */ + + pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); + pincfg |= STM32L4_GPIO_INPUT_FLOAT; + + stm32l4_configgpio(pincfg); + return OK; +} + +/************************************************************************************ + * Name: stm32l4_position + * + * Description: + * Return the current position measurement. + * + ************************************************************************************/ + +static int stm32l4_position(FAR struct qe_lowerhalf_s *lower, FAR int32_t *pos) +{ + FAR struct stm32l4_lowerhalf_s *priv = (FAR struct stm32l4_lowerhalf_s *)lower; +#ifdef HAVE_16BIT_TIMERS + int32_t position; + int32_t verify; + uint32_t count; + + DEBUGASSERT(lower && priv->inuse); + + /* Loop until we are certain that no interrupt occurred between samples */ + + do + { + /* Don't let another task pre-empt us until we get the measurement. The timer + * interrupt may still be processed + */ + + sched_lock(); + position = priv->position; + count = stm32l4_getreg32(priv, STM32L4_GTIM_CNT_OFFSET); + verify = priv->position; + sched_unlock(); + } + while (position != verify); + + /* Return the position measurement */ + + *pos = position + (int32_t)count; +#else + /* Return the counter value */ + + *pos = (int32_t)stm32l4_getreg32(priv, STM32L4_GTIM_CNT_OFFSET); +#endif + return OK; +} + +/************************************************************************************ + * Name: stm32l4_reset + * + * Description: + * Reset the position measurement to zero. + * + ************************************************************************************/ + +static int stm32l4_reset(FAR struct qe_lowerhalf_s *lower) +{ + FAR struct stm32l4_lowerhalf_s *priv = (FAR struct stm32l4_lowerhalf_s *)lower; +#ifdef HAVE_16BIT_TIMERS + irqstate_t flags; + + sninfo("Resetting position to zero\n"); + DEBUGASSERT(lower && priv->inuse); + + /* Reset the timer and the counter. Interrupts are disabled to make this atomic + * (if possible) + */ + + flags = enter_critical_section(); + stm32l4_putreg32(priv, STM32L4_GTIM_CNT_OFFSET, 0); + priv->position = 0; + leave_critical_section(flags); +#else + sninfo("Resetting position to zero\n"); + DEBUGASSERT(lower && priv->inuse); + + /* Reset the counter to zero */ + + stm32l4_putreg32(priv, STM32L4_GTIM_CNT_OFFSET, 0); +#endif + return OK; +} + +/************************************************************************************ + * Name: stm32l4_ioctl + * + * Description: + * Lower-half logic may support platform-specific ioctl commands + * + ************************************************************************************/ + +static int stm32l4_ioctl(FAR struct qe_lowerhalf_s *lower, int cmd, unsigned long arg) +{ + /* No ioctl commands supported */ + + return -ENOTTY; +} + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32l4_qeinitialize + * + * Description: + * Initialize a quadrature encoder interface. This function must be called from + * board-specific logic. + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/qe0" + * tim - The timer number to used. 'tim' must be an element of {1,2,3,4,5,8} + * + * Returned Values: + * Zero on success; A negated errno value is returned on failure. + * + ************************************************************************************/ + +int stm32l4_qeinitialize(FAR const char *devpath, int tim) +{ + FAR struct stm32l4_lowerhalf_s *priv; + int ret; + + /* Find the pre-allocated timer state structure corresponding to this timer */ + + priv = stm32l4_tim2lower(tim); + if (!priv) + { + snerr("ERROR: TIM%d support not configured\n", tim); + return -ENXIO; + } + + /* Make sure that it is available */ + + if (priv->inuse) + { + snerr("ERROR: TIM%d is in-use\n", tim); + return -EBUSY; + } + + /* Register the priv-half driver */ + + ret = qe_register(devpath, (FAR struct qe_lowerhalf_s *)priv); + if (ret < 0) + { + snerr("ERROR: qe_register failed: %d\n", ret); + return ret; + } + + /* Make sure that the timer is in the shutdown state */ + + stm32l4_shutdown((FAR struct qe_lowerhalf_s *)priv); + + /* The driver is now in-use */ + + priv->inuse = true; + return OK; +} + +#endif /* CONFIG_QENCODER */ diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.h b/arch/arm/src/stm32l4/stm32l4_qencoder.h new file mode 100644 index 0000000000..fca0b88b8b --- /dev/null +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.h @@ -0,0 +1,141 @@ +/************************************************************************************ + * arch/arm/src/stm32l4/stm32l4_qencoder.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_QENCODER_H +#define __ARCH_ARM_SRC_STM32L4_STM32L4_QENCODER_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +#ifdef CONFIG_QENCODER + +/************************************************************************************ + * Included Files + ************************************************************************************/ +/* Timer devices may be used for different purposes. One special purpose is as + * a quadrature encoder input device. If CONFIG_STM32L4_TIMn is defined then the + * CONFIG_STM32L4_TIMn_QE must also be defined to indicate that timer "n" is intended + * to be used for as a quadrature encoder. + */ + +#ifndef CONFIG_STM32L4_TIM1 +# undef CONFIG_STM32L4_TIM1_QE +#endif +#ifndef CONFIG_STM32L4_TIM2 +# undef CONFIG_STM32L4_TIM2_QE +#endif +#ifndef CONFIG_STM32L4_TIM3 +# undef CONFIG_STM32L4_TIM3_QE +#endif +#ifndef CONFIG_STM32L4_TIM4 +# undef CONFIG_STM32L4_TIM4_QE +#endif +#ifndef CONFIG_STM32L4_TIM5 +# undef CONFIG_STM32L4_TIM5_QE +#endif +#ifndef CONFIG_STM32L4_TIM8 +# undef CONFIG_STM32L4_TIM8_QE +#endif + +/* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder + */ + +#undef CONFIG_STM32L4_TIM6_QE +#undef CONFIG_STM32L4_TIM7_QE +#undef CONFIG_STM32L4_TIM9_QE +#undef CONFIG_STM32L4_TIM10_QE +#undef CONFIG_STM32L4_TIM11_QE +#undef CONFIG_STM32L4_TIM12_QE +#undef CONFIG_STM32L4_TIM13_QE +#undef CONFIG_STM32L4_TIM14_QE + +/* Clock out frequency. This value is used to calculation the timer CLKIN in + * prescaler value. + */ + +#ifndef CONFIG_STM32L4_TIM1_QECLKOUT +# define CONFIG_STM32L4_TIM1_QECLKOUT 28000000 +#endif + +#ifndef CONFIG_STM32L4_TIM2_QECLKOUT +# define CONFIG_STM32L4_TIM2_QECLKOUT 28000000 +#endif + +#ifndef CONFIG_STM32L4_TIM3_QECLKOUT +# define CONFIG_STM32L4_TIM3_QECLKOUT 28000000 +#endif + +#ifndef CONFIG_STM32L4_TIM4_QECLKOUT +# define CONFIG_STM32L4_TIM4_QECLKOUT 28000000 +#endif + +#ifndef CONFIG_STM32L4_TIM5_QECLKOUT +# define CONFIG_STM32L4_TIM5_QECLKOUT 28000000 +#endif + +#ifndef CONFIG_STM32L4_TIM8_QECLKOUT +# define CONFIG_STM32L4_TIM8_QECLKOUT 28000000 +#endif + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32l4_qeinitialize + * + * Description: + * Initialize a quadrature encoder interface. This function must be called from + * board-specific logic.. + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/qe0" + * tim - The timer number to used. 'tim' must be an element of {1,2,3,4,5,8} + * + * Returned Values: + * Zero on success; A negated errno value is returned on failure. + * + ************************************************************************************/ + +int stm32l4_qeinitialize(FAR const char *devpath, int tim); + +#endif /* CONFIG_QENCODER */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_QENCODER_H */ + -- GitLab From 06c70129ed0bc9f6db4c30b0fa9adf870982c198 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 2 Oct 2016 16:05:13 -0600 Subject: [PATCH 023/734] STM32L4: Remove dependencies on STM32 F3 from Kconfig --- arch/arm/src/stm32l4/Kconfig | 99 ++++++++++++------------------------ 1 file changed, 33 insertions(+), 66 deletions(-) diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index 83dbffe78c..3ccbfff8af 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -721,8 +721,7 @@ if STM32L4_TIM1_CHANNEL1 config STM32L4_TIM1_CH1MODE int "TIM1 Channel 1 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -745,8 +744,7 @@ if STM32L4_TIM1_CHANNEL2 config STM32L4_TIM1_CH2MODE int "TIM1 Channel 2 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -769,8 +767,7 @@ if STM32L4_TIM1_CHANNEL3 config STM32L4_TIM1_CH3MODE int "TIM1 Channel 3 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -793,8 +790,7 @@ if STM32L4_TIM1_CHANNEL4 config STM32L4_TIM1_CH4MODE int "TIM1 Channel 4 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -821,8 +817,7 @@ config STM32L4_TIM1_CHANNEL config STM32L4_TIM1_CHMODE int "TIM1 Channel Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -865,8 +860,7 @@ if STM32L4_TIM2_CHANNEL1 config STM32L4_TIM2_CH1MODE int "TIM2 Channel 1 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -889,8 +883,7 @@ if STM32L4_TIM2_CHANNEL2 config STM32L4_TIM2_CH2MODE int "TIM2 Channel 2 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -913,8 +906,7 @@ if STM32L4_TIM2_CHANNEL3 config STM32L4_TIM2_CH3MODE int "TIM2 Channel 3 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -937,8 +929,7 @@ if STM32L4_TIM2_CHANNEL4 config STM32L4_TIM2_CH4MODE int "TIM2 Channel 4 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -965,8 +956,7 @@ config STM32L4_TIM2_CHANNEL config STM32L4_TIM2_CHMODE int "TIM2 Channel Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -1009,8 +999,7 @@ if STM32L4_TIM3_CHANNEL1 config STM32L4_TIM3_CH1MODE int "TIM3 Channel 1 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -1033,8 +1022,7 @@ if STM32L4_TIM3_CHANNEL2 config STM32L4_TIM3_CH2MODE int "TIM3 Channel 2 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -1057,8 +1045,7 @@ if STM32L4_TIM3_CHANNEL3 config STM32L4_TIM3_CH3MODE int "TIM3 Channel 3 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -1081,8 +1068,7 @@ if STM32L4_TIM3_CHANNEL4 config STM32L4_TIM3_CH4MODE int "TIM3 Channel 4 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -1109,8 +1095,7 @@ config STM32L4_TIM3_CHANNEL config STM32L4_TIM3_CHMODE int "TIM3 Channel Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -1153,8 +1138,7 @@ if STM32L4_TIM4_CHANNEL1 config STM32L4_TIM4_CH1MODE int "TIM4 Channel 1 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -1177,8 +1161,7 @@ if STM32L4_TIM4_CHANNEL2 config STM32L4_TIM4_CH2MODE int "TIM4 Channel 2 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -1201,8 +1184,7 @@ if STM32L4_TIM4_CHANNEL3 config STM32L4_TIM4_CH3MODE int "TIM4 Channel 3 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -1225,8 +1207,7 @@ if STM32L4_TIM4_CHANNEL4 config STM32L4_TIM4_CH4MODE int "TIM4 Channel 4 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -1253,8 +1234,7 @@ config STM32L4_TIM4_CHANNEL config STM32L4_TIM4_CHMODE int "TIM4 Channel Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -1297,8 +1277,7 @@ if STM32L4_TIM5_CHANNEL1 config STM32L4_TIM5_CH1MODE int "TIM5 Channel 1 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -1321,8 +1300,7 @@ if STM32L4_TIM5_CHANNEL2 config STM32L4_TIM5_CH2MODE int "TIM5 Channel 2 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -1345,8 +1323,7 @@ if STM32L4_TIM5_CHANNEL3 config STM32L4_TIM5_CH3MODE int "TIM5 Channel 3 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -1369,8 +1346,7 @@ if STM32L4_TIM5_CHANNEL4 config STM32L4_TIM5_CH4MODE int "TIM5 Channel 4 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -1397,8 +1373,7 @@ config STM32L4_TIM5_CHANNEL config STM32L4_TIM5_CHMODE int "TIM5 Channel Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -1441,8 +1416,7 @@ if STM32L4_TIM8_CHANNEL1 config STM32L4_TIM8_CH1MODE int "TIM8 Channel 1 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -1465,8 +1439,7 @@ if STM32L4_TIM8_CHANNEL2 config STM32L4_TIM8_CH2MODE int "TIM8 Channel 2 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -1489,8 +1462,7 @@ if STM32L4_TIM8_CHANNEL3 config STM32L4_TIM8_CH3MODE int "TIM8 Channel 3 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -1513,8 +1485,7 @@ if STM32L4_TIM8_CHANNEL4 config STM32L4_TIM8_CH4MODE int "TIM8 Channel 4 Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -1541,8 +1512,7 @@ config STM32L4_TIM8_CHANNEL config STM32L4_TIM8_CHMODE int "TIM8 Channel Mode" default 0 - range 0 5 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 5 ---help--- Specifies the channel mode. @@ -1577,8 +1547,7 @@ if STM32L4_TIM15_CHANNEL1 config STM32L4_TIM15_CH1MODE int "TIM15 Channel 1 Mode" default 0 - range 0 3 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 3 ---help--- Specifies the channel mode. @@ -1601,8 +1570,7 @@ if STM32L4_TIM15_CHANNEL2 config STM32L4_TIM15_CH2MODE int "TIM15 Channel 2 Mode" default 0 - range 0 3 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 3 ---help--- Specifies the channel mode. @@ -1629,8 +1597,7 @@ config STM32L4_TIM15_CHANNEL config STM32L4_TIM15_CHMODE int "TIM15 Channel Mode" default 0 - range 0 3 if STM32L4_STM32F30XX - range 0 1 if !STM32L4_STM32F30XX + range 0 3 ---help--- Specifies the channel mode. -- GitLab From 9dcecd4b152c2575fd21a9f5b2a0f1c8aeb6ee88 Mon Sep 17 00:00:00 2001 From: Sebastien Lorquet Date: Mon, 3 Oct 2016 16:07:20 +0200 Subject: [PATCH 024/734] Add support for qencoders on various nucleo boards --- arch/arm/src/stm32/stm32_qencoder.c | 2 + arch/arm/src/stm32l4/stm32l4_qencoder.c | 53 +++---- configs/nucleo-f4x1re/include/board.h | 3 + configs/nucleo-f4x1re/src/Makefile | 4 + configs/nucleo-f4x1re/src/stm32_qencoder.c | 158 ++++++++++++++++++++ configs/nucleo-l476rg/include/board.h | 10 ++ configs/nucleo-l476rg/src/Makefile | 4 + configs/nucleo-l476rg/src/stm32_qencoder.c | 161 +++++++++++++++++++++ 8 files changed, 370 insertions(+), 25 deletions(-) create mode 100644 configs/nucleo-f4x1re/src/stm32_qencoder.c create mode 100644 configs/nucleo-l476rg/src/stm32_qencoder.c diff --git a/arch/arm/src/stm32/stm32_qencoder.c b/arch/arm/src/stm32/stm32_qencoder.c index 7d87debe33..69b0f9b2e0 100644 --- a/arch/arm/src/stm32/stm32_qencoder.c +++ b/arch/arm/src/stm32/stm32_qencoder.c @@ -1029,6 +1029,8 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) cr1 |= GTIM_CR1_CEN; stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); + stm32_dumpregs(priv, "After setup"); + return OK; } diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.c b/arch/arm/src/stm32l4/stm32l4_qencoder.c index 7c9426de29..19436b2e18 100644 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.c +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.c @@ -579,26 +579,27 @@ static void stm32l4_dumpregs(FAR struct stm32l4_lowerhalf_s *priv, FAR const char *msg) { sninfo("%s:\n", msg); - sninfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", + sninfo(" CR1: %04x CR2: %04x SMCR: %08x DIER: %04x\n", stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET), stm32l4_getreg16(priv, STM32L4_GTIM_CR2_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_SMCR_OFFSET), + stm32l4_getreg32(priv, STM32L4_GTIM_SMCR_OFFSET), stm32l4_getreg16(priv, STM32L4_GTIM_DIER_OFFSET)); - sninfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", + sninfo(" SR: %04x EGR: %04x CCMR1: %08x CCMR2: %08x\n", stm32l4_getreg16(priv, STM32L4_GTIM_SR_OFFSET), stm32l4_getreg16(priv, STM32L4_GTIM_EGR_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_CCMR1_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_CCMR2_OFFSET)); - sninfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", + stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET), + stm32l4_getreg32(priv, STM32L4_GTIM_CCMR2_OFFSET)); + sninfo(" CCER: %04x CNT: %08x PSC: %04x ARR: %08x\n", stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_CNT_OFFSET), + stm32l4_getreg32(priv, STM32L4_GTIM_CNT_OFFSET), stm32l4_getreg16(priv, STM32L4_GTIM_PSC_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_ARR_OFFSET)); - sninfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32l4_getreg16(priv, STM32L4_GTIM_CCR1_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_CCR2_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_CCR3_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_CCR4_OFFSET)); + stm32l4_getreg32(priv, STM32L4_GTIM_ARR_OFFSET)); + sninfo(" CCR1: %08x CCR2: %08x\n", + stm32l4_getreg32(priv, STM32L4_GTIM_CCR1_OFFSET), + stm32l4_getreg32(priv, STM32L4_GTIM_CCR2_OFFSET)); + sninfo(" CCR3: %08x CCR4: %08x\n", + stm32l4_getreg32(priv, STM32L4_GTIM_CCR3_OFFSET), + stm32l4_getreg32(priv, STM32L4_GTIM_CCR4_OFFSET)); #if defined(CONFIG_STM32L4_TIM1_QE) || defined(CONFIG_STM32L4_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { @@ -764,8 +765,8 @@ static int stm32l4_setup(FAR struct qe_lowerhalf_s *lower) { FAR struct stm32l4_lowerhalf_s *priv = (FAR struct stm32l4_lowerhalf_s *)lower; uint16_t dier; - uint16_t smcr; - uint16_t ccmr1; + uint32_t smcr; + uint32_t ccmr1; uint16_t ccer; uint16_t cr1; #ifdef HAVE_16BIT_TIMERS @@ -833,10 +834,10 @@ static int stm32l4_setup(FAR struct qe_lowerhalf_s *lower) /* Set the encoder Mode 3 */ - smcr = stm32l4_getreg16(priv, STM32L4_GTIM_SMCR_OFFSET); + smcr = stm32l4_getreg32(priv, STM32L4_GTIM_SMCR_OFFSET); smcr &= ~GTIM_SMCR_SMS_MASK; smcr |= GTIM_SMCR_ENCMD3; - stm32l4_putreg16(priv, STM32L4_GTIM_SMCR_OFFSET, smcr); + stm32l4_putreg32(priv, STM32L4_GTIM_SMCR_OFFSET, smcr); /* TI1 Channel Configuration */ /* Disable the Channel 1: Reset the CC1E Bit */ @@ -845,7 +846,7 @@ static int stm32l4_setup(FAR struct qe_lowerhalf_s *lower) ccer &= ~GTIM_CCER_CC1E; stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); - ccmr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CCMR1_OFFSET); + ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET); ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET); /* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */ @@ -861,17 +862,17 @@ static int stm32l4_setup(FAR struct qe_lowerhalf_s *lower) /* Write to TIM CCMR1 and CCER registers */ - stm32l4_putreg16(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); + stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); /* Set the Input Capture Prescaler value: Capture performed each time an * edge is detected on the capture input. */ - ccmr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CCMR1_OFFSET); + ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET); ccmr1 &= ~GTIM_CCMR1_IC1PSC_MASK; ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC1PSC_SHIFT); - stm32l4_putreg16(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); + stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); /* TI2 Channel Configuration */ /* Disable the Channel 2: Reset the CC2E Bit */ @@ -880,7 +881,7 @@ static int stm32l4_setup(FAR struct qe_lowerhalf_s *lower) ccer &= ~GTIM_CCER_CC2E; stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); - ccmr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CCMR1_OFFSET); + ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET); ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET); /* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */ @@ -896,17 +897,17 @@ static int stm32l4_setup(FAR struct qe_lowerhalf_s *lower) /* Write to TIM CCMR1 and CCER registers */ - stm32l4_putreg16(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); + stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); /* Set the Input Capture Prescaler value: Capture performed each time an * edge is detected on the capture input. */ - ccmr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CCMR1_OFFSET); + ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET); ccmr1 &= ~GTIM_CCMR1_IC2PSC_MASK; ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC2PSC_SHIFT); - stm32l4_putreg16(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); + stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); /* Disable the update interrupt */ @@ -973,6 +974,8 @@ static int stm32l4_setup(FAR struct qe_lowerhalf_s *lower) cr1 |= GTIM_CR1_CEN; stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + stm32l4_dumpregs(priv, "After setup"); + return OK; } diff --git a/configs/nucleo-f4x1re/include/board.h b/configs/nucleo-f4x1re/include/board.h index 8580b8045a..888e79c9a5 100644 --- a/configs/nucleo-f4x1re/include/board.h +++ b/configs/nucleo-f4x1re/include/board.h @@ -216,6 +216,9 @@ #define BUTTON_USER_BIT (1 << BUTTON_USER) +#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1 | GPIO_PULLUP) +#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1 | GPIO_PULLUP) + /************************************************************************************ * Public Data ************************************************************************************/ diff --git a/configs/nucleo-f4x1re/src/Makefile b/configs/nucleo-f4x1re/src/Makefile index c5d250f03d..7778dd7f00 100644 --- a/configs/nucleo-f4x1re/src/Makefile +++ b/configs/nucleo-f4x1re/src/Makefile @@ -62,6 +62,10 @@ CSRCS += stm32_ajoystick.c endif endif +ifeq ($(CONFIG_QENCODER),y) +CSRCS += stm32_qencoder.c +endif + ifeq ($(CONFIG_NSH_LIBRARY),y) CSRCS += stm32_appinit.c endif diff --git a/configs/nucleo-f4x1re/src/stm32_qencoder.c b/configs/nucleo-f4x1re/src/stm32_qencoder.c new file mode 100644 index 0000000000..6d72932844 --- /dev/null +++ b/configs/nucleo-f4x1re/src/stm32_qencoder.c @@ -0,0 +1,158 @@ +/************************************************************************************ + * configs/stm32f4discovery/src/stm32_qencoder.c + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "stm32_qencoder.h" +#include "nucleo-f4x1re.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Configuration *******************************************************************/ +/* Check if we have a timer configured for quadrature encoder -- assume YES. */ + +#define HAVE_QENCODER 1 + +/* If TIMn is not enabled (via CONFIG_STM32_TIMn), then the configuration cannot + * specify TIMn as a quadrature encoder (via CONFIG_STM32_TIMn_QE). + */ + +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_QE +#endif +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_QE +#endif +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_QE +#endif +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_QE +#endif +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_QE +#endif +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_QE +#endif + +/* If the upper-half quadrature encoder driver is not enabled, then we cannot + * support the quadrature encoder. + */ + +#ifndef CONFIG_QENCODER +# undef HAVE_QENCODER +#endif + +/* Which Timer should we use, TIMID={1,2,3,4,5,8}. If multiple timers are + * configured as quadrature encoders, this logic will arbitrarily select + * the lowest numbered timer. + * + * At least one TIMn, n={1,2,3,4,5,8}, must be both enabled and configured + * as a quadrature encoder in order to support the lower half quadrature + * encoder driver. The above check assures that if CONFIG_STM32_TIMn_QE + * is defined, then the correspdonding TIMn is also enabled. + */ + +#if defined CONFIG_STM32_TIM1_QE +# define TIMID 1 +#elif defined CONFIG_STM32_TIM2_QE +# define TIMID 2 +#elif defined CONFIG_STM32_TIM3_QE +# define TIMID 3 +#elif defined CONFIG_STM32_TIM4_QE +# define TIMID 4 +#elif defined CONFIG_STM32_TIM5_QE +# define TIMID 5 +#elif defined CONFIG_STM32_TIM8_QE +# define TIMID 8 +#else +# undef HAVE_QENCODER +#endif + +#ifdef HAVE_QENCODER + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: qe_devinit + * + * Description: + * All STM32 architectures must provide the following interface to work with + * examples/qencoder. + * + ************************************************************************************/ + +int qe_devinit(void) +{ + static bool initialized = false; + int ret; + + /* Check if we are already initialized */ + + if (!initialized) + { + /* Initialize a quadrature encoder interface. */ + + sninfo("Initializing the quadrature encoder using TIM%d\n", TIMID); + ret = stm32_qeinitialize("/dev/qe0", TIMID); + if (ret < 0) + { + snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} + +#endif /* HAVE_QENCODER */ diff --git a/configs/nucleo-l476rg/include/board.h b/configs/nucleo-l476rg/include/board.h index f9ca1ada74..a7a983221d 100644 --- a/configs/nucleo-l476rg/include/board.h +++ b/configs/nucleo-l476rg/include/board.h @@ -202,6 +202,16 @@ #define BUTTON_USER_BIT (1 << BUTTON_USER) +/* Quadrature encoder + * Default is to use timer 5 (32-bit) and encoder on PA0/PA1 + */ + +#define GPIO_TIM5_CH1IN GPIO_TIM5_CH1IN_1 +#define GPIO_TIM5_CH2IN GPIO_TIM5_CH2IN_1 + +#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_1 +#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_1 + /************************************************************************************ * Public Data ************************************************************************************/ diff --git a/configs/nucleo-l476rg/src/Makefile b/configs/nucleo-l476rg/src/Makefile index 46faa0d565..771a34ffd6 100644 --- a/configs/nucleo-l476rg/src/Makefile +++ b/configs/nucleo-l476rg/src/Makefile @@ -62,6 +62,10 @@ CSRCS += stm32_ajoystick.c endif endif +ifeq ($(CONFIG_QENCODER),y) +CSRCS += stm32_qencoder.c +endif + ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += stm32_appinit.c endif diff --git a/configs/nucleo-l476rg/src/stm32_qencoder.c b/configs/nucleo-l476rg/src/stm32_qencoder.c new file mode 100644 index 0000000000..308b674477 --- /dev/null +++ b/configs/nucleo-l476rg/src/stm32_qencoder.c @@ -0,0 +1,161 @@ +/************************************************************************************ + * configs/nucleo-l476rg/src/stm32_qencoder.c + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Copyright (C) 2016 Sebastien Lorquet. All rights reserved. + * Author: Sebastien Lorquet + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "stm32l4_qencoder.h" +#include "nucleo-l476rg.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Configuration *******************************************************************/ +/* Check if we have a timer configured for quadrature encoder -- assume YES. */ + +#define HAVE_QENCODER 1 + +/* If TIMn is not enabled (via CONFIG_STM32L4_TIMn), then the configuration cannot + * specify TIMn as a quadrature encoder (via CONFIG_STM32L4_TIMn_QE). + */ + +#ifndef CONFIG_STM32L4_TIM1 +# undef CONFIG_STM32L4_TIM1_QE +#endif +#ifndef CONFIG_STM32L4_TIM2 +# undef CONFIG_STM32L4_TIM2_QE +#endif +#ifndef CONFIG_STM32L4_TIM3 +# undef CONFIG_STM32L4_TIM3_QE +#endif +#ifndef CONFIG_STM32L4_TIM4 +# undef CONFIG_STM32L4_TIM4_QE +#endif +#ifndef CONFIG_STM32L4_TIM5 +# undef CONFIG_STM32L4_TIM5_QE +#endif +#ifndef CONFIG_STM32L4_TIM8 +# undef CONFIG_STM32L4_TIM8_QE +#endif + +/* If the upper-half quadrature encoder driver is not enabled, then we cannot + * support the quadrature encoder. + */ + +#ifndef CONFIG_QENCODER +# undef HAVE_QENCODER +#endif + +/* Which Timer should we use, TIMID={1,2,3,4,5,8}. If multiple timers are + * configured as quadrature encoders, this logic will arbitrarily select + * the lowest numbered timer. + * + * At least one TIMn, n={1,2,3,4,5,8}, must be both enabled and configured + * as a quadrature encoder in order to support the lower half quadrature + * encoder driver. The above check assures that if CONFIG_STM32L4_TIMn_QE + * is defined, then the correspdonding TIMn is also enabled. + */ + +#if defined CONFIG_STM32L4_TIM1_QE +# define TIMID 1 +#elif defined CONFIG_STM32L4_TIM2_QE +# define TIMID 2 +#elif defined CONFIG_STM32L4_TIM3_QE +# define TIMID 3 +#elif defined CONFIG_STM32L4_TIM4_QE +# define TIMID 4 +#elif defined CONFIG_STM32L4_TIM5_QE +# define TIMID 5 +#elif defined CONFIG_STM32L4_TIM8_QE +# define TIMID 8 +#else +# undef HAVE_QENCODER +#endif + +#ifdef HAVE_QENCODER + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: qe_devinit + * + * Description: + * All STM32L4 architectures must provide the following interface to work with + * examples/qencoder. + * + ************************************************************************************/ + +int qe_devinit(void) +{ + static bool initialized = false; + int ret; + + /* Check if we are already initialized */ + + if (!initialized) + { + /* Initialize a quadrature encoder interface. */ + + sninfo("Initializing the quadrature encoder using TIM%d\n", TIMID); + ret = stm32l4_qeinitialize("/dev/qe0", TIMID); + if (ret < 0) + { + snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} + +#endif /* HAVE_QENCODER */ -- GitLab From e54a0cd3d0828add29a990323c036554296dc91f Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Thu, 29 Sep 2016 15:01:59 -1000 Subject: [PATCH 025/734] Header cleanup --- arch/arm/src/stm32l4/chip/stm32l4x6xx_otgfs.h | 238 +----------------- 1 file changed, 7 insertions(+), 231 deletions(-) diff --git a/arch/arm/src/stm32l4/chip/stm32l4x6xx_otgfs.h b/arch/arm/src/stm32l4/chip/stm32l4x6xx_otgfs.h index 39065c0570..49874d7233 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4x6xx_otgfs.h +++ b/arch/arm/src/stm32l4/chip/stm32l4x6xx_otgfs.h @@ -82,11 +82,6 @@ #define STM32L4_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ #define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (104+(((n)-1) << 2)) -#define STM32L4_OTGFS_DIEPTXF1_OFFSET 0x0104 /* Device IN endpoint transmit FIFO1 size register */ -#define STM32L4_OTGFS_DIEPTXF2_OFFSET 0x0108 /* Device IN endpoint transmit FIFO2 size register */ -#define STM32L4_OTGFS_DIEPTXF3_OFFSET 0x010c /* Device IN endpoint transmit FIFO3 size register */ -#define STM32L4_OTGFS_DIEPTXF4_OFFSET 0x0110 /* Device IN endpoint transmit FIFO4 size register */ -#define STM32L4_OTGFS_DIEPTXF5_OFFSET 0x0114 /* Device IN endpoint transmit FIFO5 size register */ /* Host-mode control and status registers */ @@ -105,60 +100,12 @@ #define STM32L4_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ #define STM32L4_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) -#define STM32L4_OTGFS_HCCHAR0_OFFSET 0x0500 /* Host channel-0 characteristics register */ -#define STM32L4_OTGFS_HCCHAR1_OFFSET 0x0520 /* Host channel-1 characteristics register */ -#define STM32L4_OTGFS_HCCHAR2_OFFSET 0x0540 /* Host channel-2 characteristics register */ -#define STM32L4_OTGFS_HCCHAR3_OFFSET 0x0560 /* Host channel-3 characteristics register */ -#define STM32L4_OTGFS_HCCHAR4_OFFSET 0x0580 /* Host channel-4 characteristics register */ -#define STM32L4_OTGFS_HCCHAR5_OFFSET 0x05a0 /* Host channel-5 characteristics register */ -#define STM32L4_OTGFS_HCCHAR6_OFFSET 0x05c0 /* Host channel-6 characteristics register */ -#define STM32L4_OTGFS_HCCHAR7_OFFSET 0x05e0 /* Host channel-7 characteristics register */ -#define STM32L4_OTGFS_HCCHAR8_OFFSET 0x0600 /* Host channel-8 characteristics register */ -#define STM32L4_OTGFS_HCCHAR9_OFFSET 0x0620 /* Host channel-9 characteristics register */ -#define STM32L4_OTGFS_HCCHAR10_OFFSET 0x0640 /* Host channel-10 characteristics register */ -#define STM32L4_OTGFS_HCCHAR11_OFFSET 0x0660 /* Host channel-11 characteristics register */ #define STM32L4_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) -#define STM32L4_OTGFS_HCINT0_OFFSET 0x0508 /* Host channel-0 interrupt register */ -#define STM32L4_OTGFS_HCINT1_OFFSET 0x0528 /* Host channel-1 interrupt register */ -#define STM32L4_OTGFS_HCINT2_OFFSET 0x0548 /* Host channel-2 interrupt register */ -#define STM32L4_OTGFS_HCINT3_OFFSET 0x0568 /* Host channel-3 interrupt register */ -#define STM32L4_OTGFS_HCINT4_OFFSET 0x0588 /* Host channel-4 interrupt register */ -#define STM32L4_OTGFS_HCINT5_OFFSET 0x05a8 /* Host channel-5 interrupt register */ -#define STM32L4_OTGFS_HCINT6_OFFSET 0x05c8 /* Host channel-6 interrupt register */ -#define STM32L4_OTGFS_HCINT7_OFFSET 0x05e8 /* Host channel-7 interrupt register */ -#define STM32L4_OTGFS_HCINT8_OFFSET 0x0608 /* Host channel-8 interrupt register */ -#define STM32L4_OTGFS_HCINT9_OFFSET 0x0628 /* Host channel-9 interrupt register */ -#define STM32L4_OTGFS_HCINT10_OFFSET 0x0648 /* Host channel-10 interrupt register */ -#define STM32L4_OTGFS_HCINT11_OFFSET 0x0668 /* Host channel-11 interrupt register */ #define STM32L4_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) -#define STM32L4_OTGFS_HCINTMSK0_OFFSET 0x050c /* Host channel-0 interrupt mask register */ -#define STM32L4_OTGFS_HCINTMSK1_OFFSET 0x052c /* Host channel-1 interrupt mask register */ -#define STM32L4_OTGFS_HCINTMSK2_OFFSET 0x054c /* Host channel-2 interrupt mask register */ -#define STM32L4_OTGFS_HCINTMSK3_OFFSET 0x056c /* Host channel-3 interrupt mask register */ -#define STM32L4_OTGFS_HCINTMSK4_OFFSET 0x058c /* Host channel-4 interrupt mask register */ -#define STM32L4_OTGFS_HCINTMSK5_OFFSET 0x05ac /* Host channel-5 interrupt mask register */ -#define STM32L4_OTGFS_HCINTMSK6_OFFSET 0x05cc /* Host channel-6 interrupt mask register */ -#define STM32L4_OTGFS_HCINTMSK7_OFFSET 0x05ec /* Host channel-7 interrupt mask register */ -#define STM32L4_OTGFS_HCINTMSK8_OFFSET 0x060c /* Host channel-8 interrupt mask register */ -#define STM32L4_OTGFS_HCINTMSK9_OFFSET 0x062c /* Host channel-9 interrupt mask register */ -#define STM32L4_OTGFS_HCINTMSK10_OFFSET 0x064c /* Host channel-10 interrupt mask register */ -#define STM32L4_OTGFS_HCINTMSK11_OFFSET 0x066c /* Host channel-11 interrupt mask register */ #define STM32L4_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) -#define STM32L4_OTGFS_HCTSIZ0_OFFSET 0x0510 /* Host channel-0 interrupt register */ -#define STM32L4_OTGFS_HCTSIZ1_OFFSET 0x0530 /* Host channel-1 interrupt register */ -#define STM32L4_OTGFS_HCTSIZ2_OFFSET 0x0550 /* Host channel-2 interrupt register */ -#define STM32L4_OTGFS_HCTSIZ3_OFFSET 0x0570 /* Host channel-3 interrupt register */ -#define STM32L4_OTGFS_HCTSIZ4_OFFSET 0x0590 /* Host channel-4 interrupt register */ -#define STM32L4_OTGFS_HCTSIZ5_OFFSET 0x05b0 /* Host channel-5 interrupt register */ -#define STM32L4_OTGFS_HCTSIZ6_OFFSET 0x05d0 /* Host channel-6 interrupt register */ -#define STM32L4_OTGFS_HCTSIZ7_OFFSET 0x05f0 /* Host channel-7 interrupt register */ -#define STM32L4_OTGFS_HCTSIZ8_OFFSET 0x0610 /* Host channel-8 interrupt register */ -#define STM32L4_OTGFS_HCTSIZ9_OFFSET 0x0630 /* Host channel-9 interrupt register */ -#define STM32L4_OTGFS_HCTSIZ10_OFFSET 0x0650 /* Host channel-10 interrupt register */ -#define STM32L4_OTGFS_HCTSIZ11_OFFSET 0x0670 /* Host channel-11 interrupt register */ /* Device-mode control and status registers */ @@ -180,36 +127,12 @@ #define STM32L4_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ #define STM32L4_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPCTL0_OFFSET 0x0900 /* Device control IN endpoint 0 control register */ -#define STM32L4_OTGFS_DIEPCTL1_OFFSET 0x0920 /* Device control IN endpoint 2 control register */ -#define STM32L4_OTGFS_DIEPCTL2_OFFSET 0x0940 /* Device control IN endpoint 3 control register */ -#define STM32L4_OTGFS_DIEPCTL3_OFFSET 0x0960 /* Device control IN endpoint 4 control register */ -#define STM32L4_OTGFS_DIEPCTL4_OFFSET 0x0980 /* Device control IN endpoint 4 control register */ -#define STM32L4_OTGFS_DIEPCTL5_OFFSET 0x09a0 /* Device control IN endpoint 4 control register */ #define STM32L4_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPINT0_OFFSET 0x0908 /* Device endpoint-0 interrupt register */ -#define STM32L4_OTGFS_DIEPINT1_OFFSET 0x0928 /* Device endpoint-1 interrupt register */ -#define STM32L4_OTGFS_DIEPINT2_OFFSET 0x0948 /* Device endpoint-2 interrupt register */ -#define STM32L4_OTGFS_DIEPINT3_OFFSET 0x0968 /* Device endpoint-3 interrupt register */ -#define STM32L4_OTGFS_DIEPINT4_OFFSET 0x0988 /* Device endpoint-3 interrupt register */ -#define STM32L4_OTGFS_DIEPINT5_OFFSET 0x09a8 /* Device endpoint-3 interrupt register */ #define STM32L4_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPTSIZ0_OFFSET 0x0910 /* Device IN endpoint 0 transfer size register */ -#define STM32L4_OTGFS_DIEPTSIZ1_OFFSET 0x0930 /* Device IN endpoint 1 transfer size register */ -#define STM32L4_OTGFS_DIEPTSIZ2_OFFSET 0x0950 /* Device IN endpoint 2 transfer size register */ -#define STM32L4_OTGFS_DIEPTSIZ3_OFFSET 0x0970 /* Device IN endpoint 3 transfer size register */ -#define STM32L4_OTGFS_DIEPTSIZ4_OFFSET 0x0990 /* Device IN endpoint 3 transfer size register */ -#define STM32L4_OTGFS_DIEPTSIZ5_OFFSET 0x09b0 /* Device IN endpoint 3 transfer size register */ #define STM32L4_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) -#define STM32L4_OTGFS_DTXFSTS0_OFFSET 0x0918 /* Device OUT endpoint-0 TxFIFO status register */ -#define STM32L4_OTGFS_DTXFSTS1_OFFSET 0x0938 /* Device OUT endpoint-1 TxFIFO status register */ -#define STM32L4_OTGFS_DTXFSTS2_OFFSET 0x0958 /* Device OUT endpoint-2 TxFIFO status register */ -#define STM32L4_OTGFS_DTXFSTS3_OFFSET 0x0978 /* Device OUT endpoint-3 TxFIFO status register */ -#define STM32L4_OTGFS_DTXFSTS4_OFFSET 0x0998 /* Device OUT endpoint-3 TxFIFO status register */ -#define STM32L4_OTGFS_DTXFSTS5_OFFSET 0x09b8 /* Device OUT endpoint-3 TxFIFO status register */ #define STM32L4_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) #define STM32L4_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ @@ -217,28 +140,10 @@ #define STM32L4_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */ #define STM32L4_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPCTL0_OFFSET 0x00b00 /* Device OUT endpoint 0 control register */ -#define STM32L4_OTGFS_DOEPCTL1_OFFSET 0x00b20 /* Device OUT endpoint 1 control register */ -#define STM32L4_OTGFS_DOEPCTL2_OFFSET 0x00b40 /* Device OUT endpoint 2 control register */ -#define STM32L4_OTGFS_DOEPCTL3_OFFSET 0x00b60 /* Device OUT endpoint 3 control register */ -#define STM32L4_OTGFS_DOEPCTL4_OFFSET 0x00b80 /* Device OUT endpoint 4 control register */ -#define STM32L4_OTGFS_DOEPCTL5_OFFSET 0x00ba0 /* Device OUT endpoint 5 control register */ #define STM32L4_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPINT0_OFFSET 0x00b08 /* Device endpoint-0 interrupt register */ -#define STM32L4_OTGFS_DOEPINT1_OFFSET 0x00b28 /* Device endpoint-1 interrupt register */ -#define STM32L4_OTGFS_DOEPINT2_OFFSET 0x00b48 /* Device endpoint-2 interrupt register */ -#define STM32L4_OTGFS_DOEPINT3_OFFSET 0x00b68 /* Device endpoint-3 interrupt register */ -#define STM32L4_OTGFS_DOEPINT4_OFFSET 0x00b88 /* Device endpoint-4 interrupt register */ -#define STM32L4_OTGFS_DOEPINT5_OFFSET 0x00ba8 /* Device endpoint-5 interrupt register */ #define STM32L4_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPTSIZ0_OFFSET 0x00b10 /* Device OUT endpoint-0 transfer size register */ -#define STM32L4_OTGFS_DOEPTSIZ1_OFFSET 0x00b30 /* Device OUT endpoint-1 transfer size register */ -#define STM32L4_OTGFS_DOEPTSIZ2_OFFSET 0x00b50 /* Device OUT endpoint-2 transfer size register */ -#define STM32L4_OTGFS_DOEPTSIZ3_OFFSET 0x00b70 /* Device OUT endpoint-3 transfer size register */ -#define STM32L4_OTGFS_DOEPTSIZ4_OFFSET 0x00b90 /* Device OUT endpoint-4 transfer size register */ -#define STM32L4_OTGFS_DOEPTSIZ5_OFFSET 0x00bb0 /* Device OUT endpoint-5 transfer size register */ /* Power and clock gating registers */ @@ -249,24 +154,6 @@ #define STM32L4_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) #define STM32L4_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) -#define STM32L4_OTGFS_DFIFO_DEP0_OFFSET 0x1000 /* 0x1000-0x1ffc Device IN/OUT Endpoint 0 DFIFO Write/Read Access */ -#define STM32L4_OTGFS_DFIFO_HCH0_OFFSET 0x1000 /* 0x1000-0x1ffc Host OUT/IN Channel 0 DFIFO Read/Write Access */ - -#define STM32L4_OTGFS_DFIFO_DEP1_OFFSET 0x2000 /* 0x2000-0x2ffc Device IN/OUT Endpoint 1 DFIFO Write/Read Access */ -#define STM32L4_OTGFS_DFIFO_HCH1_OFFSET 0x2000 /* 0x2000-0x2ffc Host OUT/IN Channel 1 DFIFO Read/Write Access */ - -#define STM32L4_OTGFS_DFIFO_DEP2_OFFSET 0x3000 /* 0x3000-0x3ffc Device IN/OUT Endpoint 2 DFIFO Write/Read Access */ -#define STM32L4_OTGFS_DFIFO_HCH2_OFFSET 0x3000 /* 0x3000-0x3ffc Host OUT/IN Channel 2 DFIFO Read/Write Access */ - -#define STM32L4_OTGFS_DFIFO_DEP3_OFFSET 0x4000 /* 0x4000-0x4ffc Device IN/OUT Endpoint 3 DFIFO Write/Read Access */ -#define STM32L4_OTGFS_DFIFO_HCH3_OFFSET 0x4000 /* 0x4000-0x4ffc Host OUT/IN Channel 3 DFIFO Read/Write Access */ - -#define STM32L4_OTGFS_DFIFO_DEP4_OFFSET 0x5000 /* 0x5000-0x5ffc Device IN/OUT Endpoint 4 DFIFO Write/Read Access */ -#define STM32L4_OTGFS_DFIFO_HCH4_OFFSET 0x5000 /* 0x5000-0x5ffc Host OUT/IN Channel 4 DFIFO Read/Write Access */ - -#define STM32L4_OTGFS_DFIFO_DEP5_OFFSET 0x6000 /* 0x6000-0x6ffc Device IN/OUT Endpoint 5 DFIFO Write/Read Access */ -#define STM32L4_OTGFS_DFIFO_HCH5_OFFSET 0x6000 /* 0x6000-0x6ffc Host OUT/IN Channel 5 DFIFO Read/Write Access */ - /* Register Addresses *******************************************************************************/ #define STM32L4_OTGFS_GOTGCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGCTL_OFFSET) @@ -290,11 +177,6 @@ #define STM32L4_OTGFS_HPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXFSIZ_OFFSET) #define STM32L4_OTGFS_DIEPTXF(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF_OFFSET(n)) -#define STM32L4_OTGFS_DIEPTXF1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF1_OFFSET) -#define STM32L4_OTGFS_DIEPTXF2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF2_OFFSET) -#define STM32L4_OTGFS_DIEPTXF3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF3_OFFSET) -#define STM32L4_OTGFS_DIEPTXF4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF4_OFFSET) -#define STM32L4_OTGFS_DIEPTXF5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF5_OFFSET) /* Host-mode control and status registers */ @@ -309,60 +191,12 @@ #define STM32L4_OTGFS_CHAN(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CHAN_OFFSET(n)) #define STM32L4_OTGFS_HCCHAR(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR_OFFSET(n)) -#define STM32L4_OTGFS_HCCHAR0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR0_OFFSET) -#define STM32L4_OTGFS_HCCHAR1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR1_OFFSET) -#define STM32L4_OTGFS_HCCHAR2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR2_OFFSET) -#define STM32L4_OTGFS_HCCHAR3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR3_OFFSET) -#define STM32L4_OTGFS_HCCHAR4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR4_OFFSET) -#define STM32L4_OTGFS_HCCHAR5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR5_OFFSET) -#define STM32L4_OTGFS_HCCHAR6 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR6_OFFSET) -#define STM32L4_OTGFS_HCCHAR7 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR7_OFFSET) -#define STM32L4_OTGFS_HCCHAR8 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR8_OFFSET) -#define STM32L4_OTGFS_HCCHAR9 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR9_OFFSET) -#define STM32L4_OTGFS_HCCHAR10 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR10_OFFSET) -#define STM32L4_OTGFS_HCCHAR11 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR11_OFFSET) #define STM32L4_OTGFS_HCINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT_OFFSET(n)) -#define STM32L4_OTGFS_HCINT0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT0_OFFSET) -#define STM32L4_OTGFS_HCINT1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT1_OFFSET) -#define STM32L4_OTGFS_HCINT2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT2_OFFSET) -#define STM32L4_OTGFS_HCINT3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT3_OFFSET) -#define STM32L4_OTGFS_HCINT4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT4_OFFSET) -#define STM32L4_OTGFS_HCINT5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT5_OFFSET) -#define STM32L4_OTGFS_HCINT6 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT6_OFFSET) -#define STM32L4_OTGFS_HCINT7 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT7_OFFSET) -#define STM32L4_OTGFS_HCINT8 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT8_OFFSET) -#define STM32L4_OTGFS_HCINT9 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT9_OFFSET) -#define STM32L4_OTGFS_HCINT10 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT10_OFFSET) -#define STM32L4_OTGFS_HCINT11 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT11_OFFSET) #define STM32L4_OTGFS_HCINTMSK(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK_OFFSET(n)) -#define STM32L4_OTGFS_HCINTMSK0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK0_OFFSET) -#define STM32L4_OTGFS_HCINTMSK1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK1_OFFSET) -#define STM32L4_OTGFS_HCINTMSK2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK2_OFFSET) -#define STM32L4_OTGFS_HCINTMSK3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK3_OFFSET) -#define STM32L4_OTGFS_HCINTMSK4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK4_OFFSET) -#define STM32L4_OTGFS_HCINTMSK5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK5_OFFSET) -#define STM32L4_OTGFS_HCINTMSK6 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK6_OFFSET) -#define STM32L4_OTGFS_HCINTMSK7 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK7_OFFSET) -#define STM32L4_OTGFS_HCINTMSK8 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK8_OFFSET) -#define STM32L4_OTGFS_HCINTMSK9 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK9_OFFSET) -#define STM32L4_OTGFS_HCINTMSK10 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK10_OFFSET) -#define STM32L4_OTGFS_HCINTMSK11 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK11_OFFSET) #define STM32L4_OTGFS_HCTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ_OFFSET(n)) -#define STM32L4_OTGFS_HCTSIZ0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ0_OFFSET) -#define STM32L4_OTGFS_HCTSIZ1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ1_OFFSET) -#define STM32L4_OTGFS_HCTSIZ2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ2_OFFSET) -#define STM32L4_OTGFS_HCTSIZ3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ3_OFFSET) -#define STM32L4_OTGFS_HCTSIZ4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ4_OFFSET) -#define STM32L4_OTGFS_HCTSIZ5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ5_OFFSET) -#define STM32L4_OTGFS_HCTSIZ6 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ6_OFFSET) -#define STM32L4_OTGFS_HCTSIZ7 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ7_OFFSET) -#define STM32L4_OTGFS_HCTSIZ8 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ8_OFFSET) -#define STM32L4_OTGFS_HCTSIZ9 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ9_OFFSET) -#define STM32L4_OTGFS_HCTSIZ10 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ10_OFFSET) -#define STM32L4_OTGFS_HCTSIZ11 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ11_OFFSET) /* Device-mode control and status registers */ @@ -380,62 +214,20 @@ #define STM32L4_OTGFS_DIEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEP_OFFSET(n)) #define STM32L4_OTGFS_DIEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL_OFFSET(n)) -#define STM32L4_OTGFS_DIEPCTL0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL0_OFFSET) -#define STM32L4_OTGFS_DIEPCTL1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL1_OFFSET) -#define STM32L4_OTGFS_DIEPCTL2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL2_OFFSET) -#define STM32L4_OTGFS_DIEPCTL3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL3_OFFSET) -#define STM32L4_OTGFS_DIEPCTL4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL4_OFFSET) -#define STM32L4_OTGFS_DIEPCTL5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL5_OFFSET) #define STM32L4_OTGFS_DIEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT_OFFSET(n)) -#define STM32L4_OTGFS_DIEPINT0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT0_OFFSET) -#define STM32L4_OTGFS_DIEPINT1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT1_OFFSET) -#define STM32L4_OTGFS_DIEPINT2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT2_OFFSET) -#define STM32L4_OTGFS_DIEPINT3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT3_OFFSET) -#define STM32L4_OTGFS_DIEPINT4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT4_OFFSET) -#define STM32L4_OTGFS_DIEPINT5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT5_OFFSET) #define STM32L4_OTGFS_DIEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ_OFFSET(n)) -#define STM32L4_OTGFS_DIEPTSIZ0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ0_OFFSET) -#define STM32L4_OTGFS_DIEPTSIZ1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ1_OFFSET) -#define STM32L4_OTGFS_DIEPTSIZ2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ2_OFFSET) -#define STM32L4_OTGFS_DIEPTSIZ3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ3_OFFSET) -#define STM32L4_OTGFS_DIEPTSIZ4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ4_OFFSET) -#define STM32L4_OTGFS_DIEPTSIZ5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ5_OFFSET) #define STM32L4_OTGFS_DTXFSTS(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS_OFFSET(n)) -#define STM32L4_OTGFS_DTXFSTS0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS0_OFFSET) -#define STM32L4_OTGFS_DTXFSTS1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS1_OFFSET) -#define STM32L4_OTGFS_DTXFSTS2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS2_OFFSET) -#define STM32L4_OTGFS_DTXFSTS3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS3_OFFSET) -#define STM32L4_OTGFS_DTXFSTS4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS4_OFFSET) -#define STM32L4_OTGFS_DTXFSTS5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS5_OFFSET) #define STM32L4_OTGFS_DOEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEP_OFFSET(n)) #define STM32L4_OTGFS_DOEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL_OFFSET(n)) -#define STM32L4_OTGFS_DOEPCTL0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL0_OFFSET) -#define STM32L4_OTGFS_DOEPCTL1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL1_OFFSET) -#define STM32L4_OTGFS_DOEPCTL2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL2_OFFSET) -#define STM32L4_OTGFS_DOEPCTL3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL3_OFFSET) -#define STM32L4_OTGFS_DOEPCTL4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL4_OFFSET) -#define STM32L4_OTGFS_DOEPCTL5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL5_OFFSET) #define STM32L4_OTGFS_DOEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT_OFFSET(n)) -#define STM32L4_OTGFS_DOEPINT0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT0_OFFSET) -#define STM32L4_OTGFS_DOEPINT1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT1_OFFSET) -#define STM32L4_OTGFS_DOEPINT2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT2_OFFSET) -#define STM32L4_OTGFS_DOEPINT3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT3_OFFSET) -#define STM32L4_OTGFS_DOEPINT4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT4_OFFSET) -#define STM32L4_OTGFS_DOEPINT5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT5_OFFSET) #define STM32L4_OTGFS_DOEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ_OFFSET(n)) -#define STM32L4_OTGFS_DOEPTSIZ0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ0_OFFSET) -#define STM32L4_OTGFS_DOEPTSIZ1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ1_OFFSET) -#define STM32L4_OTGFS_DOEPTSIZ2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ2_OFFSET) -#define STM32L4_OTGFS_DOEPTSIZ3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ3_OFFSET) -#define STM32L4_OTGFS_DOEPTSIZ4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ4_OFFSET) -#define STM32L4_OTGFS_DOEPTSIZ5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ5_OFFSET) /* Power and clock gating registers */ @@ -446,23 +238,7 @@ #define STM32L4_OTGFS_DFIFO_DEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP_OFFSET(n)) #define STM32L4_OTGFS_DFIFO_HCH(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH_OFFSET(n)) -#define STM32L4_OTGFS_DFIFO_DEP0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP0_OFFSET) -#define STM32L4_OTGFS_DFIFO_HCH0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH0_OFFSET) - -#define STM32L4_OTGFS_DFIFO_DEP1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP1_OFFSET) -#define STM32L4_OTGFS_DFIFO_HCH1 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH1_OFFSET) - -#define STM32L4_OTGFS_DFIFO_DEP2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP2_OFFSET) -#define STM32L4_OTGFS_DFIFO_HCH2 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH2_OFFSET) - -#define STM32L4_OTGFS_DFIFO_DEP3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP3_OFFSET) -#define STM32L4_OTGFS_DFIFO_HCH3 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH3_OFFSET) - -#define STM32L4_OTGFS_DFIFO_DEP4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP4_OFFSET) -#define STM32L4_OTGFS_DFIFO_HCH4 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH4_OFFSET) -#define STM32L4_OTGFS_DFIFO_DEP5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP5_OFFSET) -#define STM32L4_OTGFS_DFIFO_HCH5 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH5_OFFSET) /* Register Bitfield Definitions ********************************************************************/ /* Core global control and status registers */ @@ -911,7 +687,7 @@ #define OTGFS_DCTL_CGONAK (1 << 10) /* Bit 10: Clear global OUT NAK */ #define OTGFS_DCTL_POPRGDNE (1 << 11) /* Bit 11: Power-on programming done */ /* Bits 12-17: Reserved, must be kept at reset value */ -#define OTGFS_DCTL_DSBESLRJCT (1 << 18) /* Bit 18: XXX */ +#define OTGFS_DCTL_DSBESLRJCT (1 << 18) /* Bit 18: Deep sleep BESL reject */ /* Bits 19-31: Reserved, must be kept at reset value */ /* Device status register */ @@ -939,9 +715,9 @@ #define OTGFS_DIEPMSK_ITTXFEMSK (1 << 4) /* Bit 4: IN token received when TxFIFO empty mask */ #define OTGFS_DIEPMSK_INEPNMM (1 << 5) /* Bit 5: IN token received with EP mismatch mask */ #define OTGFS_DIEPMSK_INEPNEM (1 << 6) /* Bit 6: IN endpoint NAK effective mask */ - /* Bits 7-11: Reserved, must be kept at reset value */ -#define OTGFS_DIEPMSK_NAKM (1 << 12) /* Bit 12: XXX mask */ - /* Bits 13-31: Reserved, must be kept at reset value */ + /* Bits 7-12: Reserved, must be kept at reset value */ +#define OTGFS_DIEPMSK_NAKM (1 << 13) /* Bit 13: NAK interrupt mask */ + /* Bits 14-31: Reserved, must be kept at reset value */ /* Device OUT endpoint common interrupt mask register */ #define OTGFS_DOEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */ @@ -1154,9 +930,9 @@ #define OTGFS_PCGCCTL_GATEHCLK (1 << 1) /* Bit 1: Gate HCLK */ /* Bits 2-3: Reserved, must be kept at reset value */ #define OTGFS_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */ -#define OTGFS_PCGCCTL_ENL1GTG (1 << 5) /* Bit 5: XXX */ -#define OTGFS_PCGCCTL_PHYSLEEP (1 << 6) /* Bit 6: XXX */ -#define OTGFS_PCGCCTL_SUSP (1 << 7) /* Bit 7: XXX */ +#define OTGFS_PCGCCTL_ENL1GTG (1 << 5) /* Bit 5: Enable Sleep clock gating */ +#define OTGFS_PCGCCTL_PHYSLEEP (1 << 6) /* Bit 6: PHY in Sleep */ +#define OTGFS_PCGCCTL_SUSP (1 << 7) /* Bit 7: Deep Sleep */ /* Bits 8-31: Reserved, must be kept at reset value */ #endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_OTGFS_H */ -- GitLab From a416b304a3bc79104664552f6437177a5d764833 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Fri, 30 Sep 2016 08:49:32 -1000 Subject: [PATCH 026/734] Code Cleanup and conform to upstrem debug config --- arch/arm/src/stm32l4/stm32l4_otgfsdev.c | 79 ++++++++++++------------- 1 file changed, 37 insertions(+), 42 deletions(-) diff --git a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c index 06bab127d3..e7c33c256b 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c @@ -336,7 +336,7 @@ #define CONFIG_USB_DUMPBUFFER -#if !defined(CONFIG_DEBUG_INFO) || !defined(CONFIG_DEBUG_USB) +#if !defined(CONFIG_DEBUG_INFO) || !defined(CONFIG_DEBUG_FEATURES) # undef CONFIG_USB_DUMPBUFFER #endif #ifdef CONFIG_USB_DUMPBUFFER @@ -582,7 +582,7 @@ struct stm32l4_usbdev_s /* Register operations ********************************************************/ -#if defined(CONFIG_STM32L4_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_USB) +#if defined(CONFIG_STM32L4_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32l4_getreg(uint32_t addr); static void stm32l4_putreg(uint32_t val, uint32_t addr); #else @@ -902,7 +902,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = * ****************************************************************************/ -#if defined(CONFIG_STM32L4_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_USB) +#if defined(CONFIG_STM32L4_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32l4_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -923,7 +923,7 @@ static uint32_t stm32l4_getreg(uint32_t addr) { if (count == 4) { - lldbg("...\n"); + uinfo("...\n"); } return val; @@ -940,7 +940,7 @@ static uint32_t stm32l4_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - lldbg("[repeats %d more times]\n", count-3); + uinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -952,7 +952,7 @@ static uint32_t stm32l4_getreg(uint32_t addr) /* Show the register value read */ - lldbg("%08x->%08x\n", addr, val); + uinfo("%08x->%08x\n", addr, val); return val; } #endif @@ -965,12 +965,12 @@ static uint32_t stm32l4_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_STM32L4_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_USB) +#if defined(CONFIG_STM32L4_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static void stm32l4_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ - lldbg("%08x<-%08x\n", addr, val); + uinfo("%08x<-%08x\n", addr, val); /* Write the value */ @@ -1075,7 +1075,7 @@ static void stm32l4_ep0in_activate(void) /* Set the max packet size of the IN EP. */ - regval = stm32l4_getreg(STM32L4_OTGFS_DIEPCTL0); + regval = stm32l4_getreg(STM32L4_OTGFS_DIEPCTL(0)); regval &= ~OTGFS_DIEPCTL0_MPSIZ_MASK; #if CONFIG_USBDEV_EP0_MAXSIZE == 8 @@ -1090,7 +1090,7 @@ static void stm32l4_ep0in_activate(void) # error "Unsupported value of CONFIG_USBDEV_EP0_MAXSIZE" #endif - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPCTL0); + stm32l4_putreg(regval, STM32L4_OTGFS_DIEPCTL(0)); /* Clear global IN NAK */ @@ -1116,13 +1116,13 @@ static void stm32l4_ep0out_ctrlsetup(FAR struct stm32l4_usbdev_s *priv) regval = (USB_SIZEOF_CTRLREQ * 3 << OTGFS_DOEPTSIZ0_XFRSIZ_SHIFT) | (OTGFS_DOEPTSIZ0_PKTCNT) | (3 << OTGFS_DOEPTSIZ0_STUPCNT_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DOEPTSIZ0); + stm32l4_putreg(regval, STM32L4_OTGFS_DOEPTSIZ(0)); /* Then clear NAKing and enable the transfer */ - regval = stm32l4_getreg(STM32L4_OTGFS_DOEPCTL0); + regval = stm32l4_getreg(STM32L4_OTGFS_DOEPCTL(0)); regval |= (OTGFS_DOEPCTL0_CNAK | OTGFS_DOEPCTL0_EPENA); - stm32l4_putreg(regval, STM32L4_OTGFS_DOEPCTL0); + stm32l4_putreg(regval, STM32L4_OTGFS_DOEPCTL(0)); } /**************************************************************************** @@ -2416,8 +2416,6 @@ static inline void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, stm32l4_setaddress(priv, (uint16_t)priv->ctrlreq.value[0]); stm32l4_ep0in_transmitzlp(priv); - - uinfo("USB_REQ_SETADDRESS %02x\n",(uint16_t)priv->ctrlreq.value[0]); } else { @@ -2983,7 +2981,7 @@ static inline void stm32l4_epin_interrupt(FAR struct stm32l4_usbdev_s *priv) { if ((daint & 1) != 0) { - uinfo("DIEPINT(%d) = %08x\n", + uerr("DIEPINT(%d) = %08x\n", epno, stm32l4_getreg(STM32L4_OTGFS_DIEPINT(epno))); stm32l4_putreg(0xFF, STM32L4_OTGFS_DIEPINT(epno)); } @@ -3240,8 +3238,6 @@ static inline void stm32l4_rxinterrupt(FAR struct stm32l4_usbdev_s *priv) int bcnt; int epphy; - /* Disable the Rx status queue level interrupt */ - while(0 != (stm32l4_getreg(STM32L4_OTGFS_GINTSTS) & OTGFS_GINT_RXFLVL)) { @@ -3334,12 +3330,11 @@ static inline void stm32l4_rxinterrupt(FAR struct stm32l4_usbdev_s *priv) { /* Clear NAKSTS so that we can receive the data */ - - regval = stm32l4_getreg(STM32L4_OTGFS_DOEPCTL0); + regval = stm32l4_getreg(STM32L4_OTGFS_DOEPCTL(0)); regval |= OTGFS_DOEPCTL0_CNAK; - stm32l4_putreg(regval, STM32L4_OTGFS_DOEPCTL0); + stm32l4_putreg(regval, STM32L4_OTGFS_DOEPCTL(0)); - } + } } break; @@ -3642,7 +3637,7 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context) uint32_t regval; uint32_t reserved; - usbtrace(TRACE_INTENTRY(STM32L4_TRACEINTID_USB), 0); + usbtrace(TRACE_INTENTRY(STM32L4_TRACEINTID_USB), priv->ep0state); /* Assure that we are in device mode */ @@ -3699,7 +3694,7 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context) /* Host/device mode mismatch error interrupt */ -#ifdef CONFIG_DEBUG_USB +#ifdef CONFIG_DEBUG_FEATURES if ((regval & OTGFS_GINT_MMIS) != 0) { usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_MISMATCH), (uint16_t)regval); @@ -3750,7 +3745,7 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context) /* Perform the device reset */ stm32l4_usbreset(priv); - usbtrace(TRACE_INTEXIT(STM32L4_TRACEINTID_USB), 0); + usbtrace(TRACE_INTEXIT(STM32L4_TRACEINTID_USB), priv->ep0state); return OK; } @@ -3811,7 +3806,7 @@ static int stm32l4_usbinterrupt(int irq, FAR void *context) #endif } - usbtrace(TRACE_INTEXIT(STM32L4_TRACEINTID_USB), 0); + usbtrace(TRACE_INTEXIT(STM32L4_TRACEINTID_USB), priv->ep0state); return OK; } @@ -4317,7 +4312,7 @@ static int stm32l4_ep_disable(FAR struct usbdev_ep_s *ep) { FAR struct stm32l4_ep_s *privep = (FAR struct stm32l4_ep_s *)ep; -#ifdef CONFIG_DEBUG_USB +#ifdef CONFIG_DEBUG_FEATURES if (!ep) { usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); @@ -4357,7 +4352,7 @@ static FAR struct usbdev_req_s *stm32l4_ep_allocreq(FAR struct usbdev_ep_s *ep) { FAR struct stm32l4_req_s *privreq; -#ifdef CONFIG_DEBUG_USB +#ifdef CONFIG_DEBUG_FEATURES if (!ep) { usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); @@ -4390,7 +4385,7 @@ static void stm32l4_ep_freereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req { FAR struct stm32l4_req_s *privreq = (FAR struct stm32l4_req_s *)req; -#ifdef CONFIG_DEBUG_USB +#ifdef CONFIG_DEBUG_FEATURES if (!ep || !req) { usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); @@ -4463,7 +4458,7 @@ static int stm32l4_ep_submit(FAR struct usbdev_ep_s *ep, /* Some sanity checking */ -#ifdef CONFIG_DEBUG_USB +#ifdef CONFIG_DEBUG_FEATURES if (!req || !req->callback || !req->buf || !ep) { usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); @@ -4475,7 +4470,7 @@ static int stm32l4_ep_submit(FAR struct usbdev_ep_s *ep, usbtrace(TRACE_EPSUBMIT, privep->epphy); priv = privep->dev; -#ifdef CONFIG_DEBUG_USB +#ifdef CONFIG_DEBUG_FEATURES if (!priv->driver) { usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); @@ -4553,7 +4548,7 @@ static int stm32l4_ep_cancel(FAR struct usbdev_ep_s *ep, FAR struct stm32l4_ep_s *privep = (FAR struct stm32l4_ep_s *)ep; irqstate_t flags; -#ifdef CONFIG_DEBUG_USB +#ifdef CONFIG_DEBUG_FEATURES if (!ep || !req) { usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); @@ -5012,7 +5007,7 @@ static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered) usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); -#ifdef CONFIG_DEBUG_USB +#ifdef CONFIG_DEBUG_FEATURES if (!dev) { usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); @@ -5366,7 +5361,7 @@ static void stm32l4_hwinitialize(FAR struct stm32l4_usbdev_s *priv) address = STM32L4_RXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF0_TX0FD_SHIFT) | (STM32L4_EP0_TXFIFO_WORDS << OTGFS_DIEPTXF0_TX0FSA_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF0); + stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(0)); #endif #if STM32L4_NENDPOINTS > 1 @@ -5375,7 +5370,7 @@ static void stm32l4_hwinitialize(FAR struct stm32l4_usbdev_s *priv) address += STM32L4_EP0_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | (STM32L4_EP1_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF1); + stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(1)); #endif #if STM32L4_NENDPOINTS > 2 @@ -5384,7 +5379,7 @@ static void stm32l4_hwinitialize(FAR struct stm32l4_usbdev_s *priv) address += STM32L4_EP1_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | (STM32L4_EP2_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF2); + stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(2)); #endif #if STM32L4_NENDPOINTS > 3 @@ -5393,7 +5388,7 @@ static void stm32l4_hwinitialize(FAR struct stm32l4_usbdev_s *priv) address += STM32L4_EP2_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | (STM32L4_EP3_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF3); + stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(3)); #endif #if STM32L4_NENDPOINTS > 4 @@ -5402,7 +5397,7 @@ static void stm32l4_hwinitialize(FAR struct stm32l4_usbdev_s *priv) address += STM32L4_EP3_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | (STM32L4_EP4_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF4); + stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(4)); #endif #if STM32L4_NENDPOINTS > 5 @@ -5411,7 +5406,7 @@ static void stm32l4_hwinitialize(FAR struct stm32l4_usbdev_s *priv) address += STM32L4_EP4_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | (STM32L4_EP5_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF5); + stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(5)); #endif @@ -5501,7 +5496,7 @@ static void stm32l4_hwinitialize(FAR struct stm32l4_usbdev_s *priv) regval |= (OTGFS_GINT_OTG | OTGFS_GINT_SRQ); #endif -#ifdef CONFIG_DEBUG_USB +#ifdef CONFIG_DEBUG_FEATURES regval |= OTGFS_GINT_MMIS; #endif @@ -5709,7 +5704,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) usbtrace(TRACE_DEVREGISTER, 0); -#ifdef CONFIG_DEBUG_USB +#ifdef CONFIG_DEBUG_FEATURES if (!driver || !driver->ops->bind || !driver->ops->unbind || !driver->ops->disconnect || !driver->ops->setup) { @@ -5780,7 +5775,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) usbtrace(TRACE_DEVUNREGISTER, 0); -#ifdef CONFIG_DEBUG_USB +#ifdef CONFIG_DEBUG_FEATURES if (driver != priv->driver) { usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); -- GitLab From d4a8585d6f2819f4c4b2c92262542219801ee652 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Tue, 4 Oct 2016 16:35:59 -1000 Subject: [PATCH 027/734] Fixed L4 USB Driver by avoiding SETUPDONE and EPOUT_SETUP --- arch/arm/src/stm32l4/stm32l4_otgfsdev.c | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c index e7c33c256b..407534f4fb 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c @@ -3321,20 +3321,10 @@ static inline void stm32l4_rxinterrupt(FAR struct stm32l4_usbdev_s *priv) { usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETUPDONE), epphy); - /* Now that the Setup Phase is complete if it was an OUT enable - * the endpoint - * (Doing this here prevents the loss of the first FIFO word) + /* On the L4 This event does not occur on the next SETUP + * after a SETUP OUT. */ - if (priv->ep0state == EP0STATE_SETUP_OUT) - { - - /* Clear NAKSTS so that we can receive the data */ - regval = stm32l4_getreg(STM32L4_OTGFS_DOEPCTL(0)); - regval |= OTGFS_DOEPCTL0_CNAK; - stm32l4_putreg(regval, STM32L4_OTGFS_DOEPCTL(0)); - - } } break; @@ -3370,17 +3360,23 @@ static inline void stm32l4_rxinterrupt(FAR struct stm32l4_usbdev_s *priv) datlen = GETUINT16(priv->ctrlreq.len); if (USB_REQ_ISOUT(priv->ctrlreq.type) && datlen > 0) { + /* Reset the endpoint and Stop NAK-ing */ + + stm32l4_ep0out_ctrlsetup(priv); + /* Wait for the data phase. */ priv->ep0state = EP0STATE_SETUP_OUT; } else { - /* We can process the setup data as soon as SETUP done word is - * popped of the RxFIFO. + /* We can process the setup data Now no need to wait for SETUP done word + * to be popped of the RxFIFO. */ priv->ep0state = EP0STATE_SETUP_READY; + stm32l4_ep0out_setup(priv); + } } break; -- GitLab From 796fbe834a6a181848fbedb18d71d74a4b60af25 Mon Sep 17 00:00:00 2001 From: Mateusz Szafoni Date: Thu, 6 Oct 2016 11:13:10 +0200 Subject: [PATCH 028/734] configs/olimex-stm32-e407: Add some networking configurations --- configs/olimex-stm32-e407/discover/Make.defs | 112 ++ configs/olimex-stm32-e407/discover/defconfig | 1298 +++++++++++++++ configs/olimex-stm32-e407/discover/setenv.sh | 80 + configs/olimex-stm32-e407/include/board.h | 2 +- configs/olimex-stm32-e407/netnsh/Make.defs | 112 ++ configs/olimex-stm32-e407/netnsh/defconfig | 1429 +++++++++++++++++ configs/olimex-stm32-e407/netnsh/setenv.sh | 80 + .../olimex-stm32-e407/src/olimex-stm32-e407.h | 37 +- configs/olimex-stm32-e407/telnetd/Make.defs | 112 ++ configs/olimex-stm32-e407/telnetd/defconfig | 1304 +++++++++++++++ configs/olimex-stm32-e407/telnetd/setenv.sh | 80 + configs/olimex-stm32-e407/webserver/Make.defs | 112 ++ configs/olimex-stm32-e407/webserver/defconfig | 1309 +++++++++++++++ configs/olimex-stm32-e407/webserver/setenv.sh | 80 + 14 files changed, 6135 insertions(+), 12 deletions(-) create mode 100644 configs/olimex-stm32-e407/discover/Make.defs create mode 100644 configs/olimex-stm32-e407/discover/defconfig create mode 100755 configs/olimex-stm32-e407/discover/setenv.sh create mode 100644 configs/olimex-stm32-e407/netnsh/Make.defs create mode 100644 configs/olimex-stm32-e407/netnsh/defconfig create mode 100755 configs/olimex-stm32-e407/netnsh/setenv.sh create mode 100644 configs/olimex-stm32-e407/telnetd/Make.defs create mode 100644 configs/olimex-stm32-e407/telnetd/defconfig create mode 100755 configs/olimex-stm32-e407/telnetd/setenv.sh create mode 100644 configs/olimex-stm32-e407/webserver/Make.defs create mode 100644 configs/olimex-stm32-e407/webserver/defconfig create mode 100755 configs/olimex-stm32-e407/webserver/setenv.sh diff --git a/configs/olimex-stm32-e407/discover/Make.defs b/configs/olimex-stm32-e407/discover/Make.defs new file mode 100644 index 0000000000..968dc2167b --- /dev/null +++ b/configs/olimex-stm32-e407/discover/Make.defs @@ -0,0 +1,112 @@ +############################################################################ +# configs/olimex-stm32-e407/discover/Make.defs +# +# Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = diff --git a/configs/olimex-stm32-e407/discover/defconfig b/configs/olimex-stm32-e407/discover/defconfig new file mode 100644 index 0000000000..681313aec8 --- /dev/null +++ b/configs/olimex-stm32-e407/discover/defconfig @@ -0,0 +1,1298 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +CONFIG_ARCH_HAVE_HEAPCHECK=y +# CONFIG_HEAP_COLORATION is not set +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +CONFIG_ARCH_CHIP_STM32=y +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM3 is not set +CONFIG_ARCH_CORTEXM4=y +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="stm32" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARMV7M_LAZYFPU is not set +CONFIG_ARCH_HAVE_FPU=y +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set +# CONFIG_ARMV7M_OABI_TOOLCHAIN is not set +CONFIG_ARMV7M_HAVE_STACKCHECK=y +# CONFIG_ARMV7M_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set +# CONFIG_SERIAL_TERMIOS is not set + +# +# STM32 Configuration Options +# +# CONFIG_ARCH_CHIP_STM32L151C6 is not set +# CONFIG_ARCH_CHIP_STM32L151C8 is not set +# CONFIG_ARCH_CHIP_STM32L151CB is not set +# CONFIG_ARCH_CHIP_STM32L151R6 is not set +# CONFIG_ARCH_CHIP_STM32L151R8 is not set +# CONFIG_ARCH_CHIP_STM32L151RB is not set +# CONFIG_ARCH_CHIP_STM32L151V6 is not set +# CONFIG_ARCH_CHIP_STM32L151V8 is not set +# CONFIG_ARCH_CHIP_STM32L151VB is not set +# CONFIG_ARCH_CHIP_STM32L152C6 is not set +# CONFIG_ARCH_CHIP_STM32L152C8 is not set +# CONFIG_ARCH_CHIP_STM32L152CB is not set +# CONFIG_ARCH_CHIP_STM32L152R6 is not set +# CONFIG_ARCH_CHIP_STM32L152R8 is not set +# CONFIG_ARCH_CHIP_STM32L152RB is not set +# CONFIG_ARCH_CHIP_STM32L152V6 is not set +# CONFIG_ARCH_CHIP_STM32L152V8 is not set +# CONFIG_ARCH_CHIP_STM32L152VB is not set +# CONFIG_ARCH_CHIP_STM32L162ZD is not set +# CONFIG_ARCH_CHIP_STM32L162VE is not set +# CONFIG_ARCH_CHIP_STM32F100C8 is not set +# CONFIG_ARCH_CHIP_STM32F100CB is not set +# CONFIG_ARCH_CHIP_STM32F100R8 is not set +# CONFIG_ARCH_CHIP_STM32F100RB is not set +# CONFIG_ARCH_CHIP_STM32F100RC is not set +# CONFIG_ARCH_CHIP_STM32F100RD is not set +# CONFIG_ARCH_CHIP_STM32F100RE is not set +# CONFIG_ARCH_CHIP_STM32F100V8 is not set +# CONFIG_ARCH_CHIP_STM32F100VB is not set +# CONFIG_ARCH_CHIP_STM32F100VC is not set +# CONFIG_ARCH_CHIP_STM32F100VD is not set +# CONFIG_ARCH_CHIP_STM32F100VE is not set +# CONFIG_ARCH_CHIP_STM32F102CB is not set +# CONFIG_ARCH_CHIP_STM32F103T8 is not set +# CONFIG_ARCH_CHIP_STM32F103TB is not set +# CONFIG_ARCH_CHIP_STM32F103C4 is not set +# CONFIG_ARCH_CHIP_STM32F103C8 is not set +# CONFIG_ARCH_CHIP_STM32F103CB is not set +# CONFIG_ARCH_CHIP_STM32F103R8 is not set +# CONFIG_ARCH_CHIP_STM32F103RB is not set +# CONFIG_ARCH_CHIP_STM32F103RC is not set +# CONFIG_ARCH_CHIP_STM32F103RD is not set +# CONFIG_ARCH_CHIP_STM32F103RE is not set +# CONFIG_ARCH_CHIP_STM32F103RG is not set +# CONFIG_ARCH_CHIP_STM32F103V8 is not set +# CONFIG_ARCH_CHIP_STM32F103VB is not set +# CONFIG_ARCH_CHIP_STM32F103VC is not set +# CONFIG_ARCH_CHIP_STM32F103VE is not set +# CONFIG_ARCH_CHIP_STM32F103ZE is not set +# CONFIG_ARCH_CHIP_STM32F105VB is not set +# CONFIG_ARCH_CHIP_STM32F105RB is not set +# CONFIG_ARCH_CHIP_STM32F107VC is not set +# CONFIG_ARCH_CHIP_STM32F205RG is not set +# CONFIG_ARCH_CHIP_STM32F207IG is not set +# CONFIG_ARCH_CHIP_STM32F207ZE is not set +# CONFIG_ARCH_CHIP_STM32F302K6 is not set +# CONFIG_ARCH_CHIP_STM32F302K8 is not set +# CONFIG_ARCH_CHIP_STM32F302CB is not set +# CONFIG_ARCH_CHIP_STM32F302CC is not set +# CONFIG_ARCH_CHIP_STM32F302RB is not set +# CONFIG_ARCH_CHIP_STM32F302RC is not set +# CONFIG_ARCH_CHIP_STM32F302VB is not set +# CONFIG_ARCH_CHIP_STM32F302VC is not set +# CONFIG_ARCH_CHIP_STM32F303K6 is not set +# CONFIG_ARCH_CHIP_STM32F303K8 is not set +# CONFIG_ARCH_CHIP_STM32F303C6 is not set +# CONFIG_ARCH_CHIP_STM32F303C8 is not set +# CONFIG_ARCH_CHIP_STM32F303CB is not set +# CONFIG_ARCH_CHIP_STM32F303CC is not set +# CONFIG_ARCH_CHIP_STM32F303RB is not set +# CONFIG_ARCH_CHIP_STM32F303RC is not set +# CONFIG_ARCH_CHIP_STM32F303RD is not set +# CONFIG_ARCH_CHIP_STM32F303RE is not set +# CONFIG_ARCH_CHIP_STM32F303VB is not set +# CONFIG_ARCH_CHIP_STM32F303VC is not set +# CONFIG_ARCH_CHIP_STM32F372C8 is not set +# CONFIG_ARCH_CHIP_STM32F372R8 is not set +# CONFIG_ARCH_CHIP_STM32F372V8 is not set +# CONFIG_ARCH_CHIP_STM32F372CB is not set +# CONFIG_ARCH_CHIP_STM32F372RB is not set +# CONFIG_ARCH_CHIP_STM32F372VB is not set +# CONFIG_ARCH_CHIP_STM32F372CC is not set +# CONFIG_ARCH_CHIP_STM32F372RC is not set +# CONFIG_ARCH_CHIP_STM32F372VC is not set +# CONFIG_ARCH_CHIP_STM32F373C8 is not set +# CONFIG_ARCH_CHIP_STM32F373R8 is not set +# CONFIG_ARCH_CHIP_STM32F373V8 is not set +# CONFIG_ARCH_CHIP_STM32F373CB is not set +# CONFIG_ARCH_CHIP_STM32F373RB is not set +# CONFIG_ARCH_CHIP_STM32F373VB is not set +# CONFIG_ARCH_CHIP_STM32F373CC is not set +# CONFIG_ARCH_CHIP_STM32F373RC is not set +# CONFIG_ARCH_CHIP_STM32F373VC is not set +# CONFIG_ARCH_CHIP_STM32F401RE is not set +# CONFIG_ARCH_CHIP_STM32F411RE is not set +# CONFIG_ARCH_CHIP_STM32F411VE is not set +# CONFIG_ARCH_CHIP_STM32F405RG is not set +# CONFIG_ARCH_CHIP_STM32F405VG is not set +# CONFIG_ARCH_CHIP_STM32F405ZG is not set +# CONFIG_ARCH_CHIP_STM32F407VE is not set +# CONFIG_ARCH_CHIP_STM32F407VG is not set +# CONFIG_ARCH_CHIP_STM32F407ZE is not set +CONFIG_ARCH_CHIP_STM32F407ZG=y +# CONFIG_ARCH_CHIP_STM32F407IE is not set +# CONFIG_ARCH_CHIP_STM32F407IG is not set +# CONFIG_ARCH_CHIP_STM32F427V is not set +# CONFIG_ARCH_CHIP_STM32F427Z is not set +# CONFIG_ARCH_CHIP_STM32F427I is not set +# CONFIG_ARCH_CHIP_STM32F429V is not set +# CONFIG_ARCH_CHIP_STM32F429Z is not set +# CONFIG_ARCH_CHIP_STM32F429I is not set +# CONFIG_ARCH_CHIP_STM32F429B is not set +# CONFIG_ARCH_CHIP_STM32F429N is not set +# CONFIG_ARCH_CHIP_STM32F446M is not set +# CONFIG_ARCH_CHIP_STM32F446R is not set +# CONFIG_ARCH_CHIP_STM32F446V is not set +# CONFIG_ARCH_CHIP_STM32F446Z is not set +# CONFIG_ARCH_CHIP_STM32F469A is not set +# CONFIG_ARCH_CHIP_STM32F469I is not set +# CONFIG_ARCH_CHIP_STM32F469B is not set +# CONFIG_ARCH_CHIP_STM32F469N is not set +CONFIG_STM32_FLASH_CONFIG_DEFAULT=y +# CONFIG_STM32_FLASH_CONFIG_4 is not set +# CONFIG_STM32_FLASH_CONFIG_6 is not set +# CONFIG_STM32_FLASH_CONFIG_8 is not set +# CONFIG_STM32_FLASH_CONFIG_B is not set +# CONFIG_STM32_FLASH_CONFIG_C is not set +# CONFIG_STM32_FLASH_CONFIG_D is not set +# CONFIG_STM32_FLASH_CONFIG_E is not set +# CONFIG_STM32_FLASH_CONFIG_F is not set +# CONFIG_STM32_FLASH_CONFIG_G is not set +# CONFIG_STM32_FLASH_CONFIG_I is not set +# CONFIG_STM32_STM32L15XX is not set +# CONFIG_STM32_ENERGYLITE is not set +# CONFIG_STM32_STM32F10XX is not set +# CONFIG_STM32_VALUELINE is not set +# CONFIG_STM32_CONNECTIVITYLINE is not set +# CONFIG_STM32_PERFORMANCELINE is not set +# CONFIG_STM32_USBACCESSLINE is not set +# CONFIG_STM32_HIGHDENSITY is not set +# CONFIG_STM32_MEDIUMDENSITY is not set +# CONFIG_STM32_LOWDENSITY is not set +# CONFIG_STM32_STM32F20XX is not set +# CONFIG_STM32_STM32F205 is not set +# CONFIG_STM32_STM32F207 is not set +# CONFIG_STM32_STM32F30XX is not set +# CONFIG_STM32_STM32F302 is not set +# CONFIG_STM32_STM32F303 is not set +# CONFIG_STM32_STM32F37XX is not set +CONFIG_STM32_STM32F40XX=y +# CONFIG_STM32_STM32F401 is not set +# CONFIG_STM32_STM32F411 is not set +# CONFIG_STM32_STM32F405 is not set +CONFIG_STM32_STM32F407=y +# CONFIG_STM32_STM32F427 is not set +# CONFIG_STM32_STM32F429 is not set +# CONFIG_STM32_STM32F446 is not set +# CONFIG_STM32_STM32F469 is not set +# CONFIG_STM32_DFU is not set + +# +# STM32 Peripheral Support +# +CONFIG_STM32_HAVE_CCM=y +# CONFIG_STM32_HAVE_USBDEV is not set +CONFIG_STM32_HAVE_OTGFS=y +CONFIG_STM32_HAVE_FSMC=y +# CONFIG_STM32_HAVE_LTDC is not set +CONFIG_STM32_HAVE_USART3=y +CONFIG_STM32_HAVE_UART4=y +CONFIG_STM32_HAVE_UART5=y +CONFIG_STM32_HAVE_USART6=y +# CONFIG_STM32_HAVE_UART7 is not set +# CONFIG_STM32_HAVE_UART8 is not set +CONFIG_STM32_HAVE_TIM1=y +CONFIG_STM32_HAVE_TIM2=y +CONFIG_STM32_HAVE_TIM3=y +CONFIG_STM32_HAVE_TIM4=y +CONFIG_STM32_HAVE_TIM5=y +CONFIG_STM32_HAVE_TIM6=y +CONFIG_STM32_HAVE_TIM7=y +CONFIG_STM32_HAVE_TIM8=y +CONFIG_STM32_HAVE_TIM9=y +CONFIG_STM32_HAVE_TIM10=y +CONFIG_STM32_HAVE_TIM11=y +CONFIG_STM32_HAVE_TIM12=y +CONFIG_STM32_HAVE_TIM13=y +CONFIG_STM32_HAVE_TIM14=y +# CONFIG_STM32_HAVE_TIM15 is not set +# CONFIG_STM32_HAVE_TIM16 is not set +# CONFIG_STM32_HAVE_TIM17 is not set +CONFIG_STM32_HAVE_ADC2=y +CONFIG_STM32_HAVE_ADC3=y +# CONFIG_STM32_HAVE_ADC4 is not set +# CONFIG_STM32_HAVE_ADC1_DMA is not set +# CONFIG_STM32_HAVE_ADC2_DMA is not set +# CONFIG_STM32_HAVE_ADC3_DMA is not set +# CONFIG_STM32_HAVE_ADC4_DMA is not set +CONFIG_STM32_HAVE_CAN1=y +CONFIG_STM32_HAVE_CAN2=y +CONFIG_STM32_HAVE_DAC1=y +CONFIG_STM32_HAVE_DAC2=y +CONFIG_STM32_HAVE_RNG=y +CONFIG_STM32_HAVE_ETHMAC=y +CONFIG_STM32_HAVE_I2C2=y +CONFIG_STM32_HAVE_I2C3=y +CONFIG_STM32_HAVE_SPI2=y +CONFIG_STM32_HAVE_SPI3=y +# CONFIG_STM32_HAVE_SPI4 is not set +# CONFIG_STM32_HAVE_SPI5 is not set +# CONFIG_STM32_HAVE_SPI6 is not set +# CONFIG_STM32_HAVE_SAIPLL is not set +# CONFIG_STM32_HAVE_I2SPLL is not set +# CONFIG_STM32_ADC1 is not set +# CONFIG_STM32_ADC2 is not set +# CONFIG_STM32_ADC3 is not set +# CONFIG_STM32_BKPSRAM is not set +# CONFIG_STM32_CAN1 is not set +# CONFIG_STM32_CAN2 is not set +# CONFIG_STM32_CCMDATARAM is not set +# CONFIG_STM32_CRC is not set +# CONFIG_STM32_CRYP is not set +# CONFIG_STM32_DMA1 is not set +# CONFIG_STM32_DMA2 is not set +# CONFIG_STM32_DAC1 is not set +# CONFIG_STM32_DAC2 is not set +# CONFIG_STM32_DCMI is not set +CONFIG_STM32_ETHMAC=y +# CONFIG_STM32_FSMC is not set +# CONFIG_STM32_HASH is not set +# CONFIG_STM32_I2C1 is not set +# CONFIG_STM32_I2C2 is not set +# CONFIG_STM32_I2C3 is not set +# CONFIG_STM32_OTGFS is not set +# CONFIG_STM32_OTGHS is not set +CONFIG_STM32_PWR=y +# CONFIG_STM32_RNG is not set +# CONFIG_STM32_SDIO is not set +# CONFIG_STM32_SPI1 is not set +# CONFIG_STM32_SPI2 is not set +# CONFIG_STM32_SPI3 is not set +CONFIG_STM32_SYSCFG=y +# CONFIG_STM32_TIM1 is not set +# CONFIG_STM32_TIM2 is not set +# CONFIG_STM32_TIM3 is not set +# CONFIG_STM32_TIM4 is not set +# CONFIG_STM32_TIM5 is not set +# CONFIG_STM32_TIM6 is not set +# CONFIG_STM32_TIM7 is not set +# CONFIG_STM32_TIM8 is not set +# CONFIG_STM32_TIM9 is not set +# CONFIG_STM32_TIM10 is not set +# CONFIG_STM32_TIM11 is not set +# CONFIG_STM32_TIM12 is not set +# CONFIG_STM32_TIM13 is not set +# CONFIG_STM32_TIM14 is not set +# CONFIG_STM32_USART1 is not set +CONFIG_STM32_USART2=y +# CONFIG_STM32_USART3 is not set +# CONFIG_STM32_UART4 is not set +# CONFIG_STM32_UART5 is not set +# CONFIG_STM32_USART6 is not set +# CONFIG_STM32_IWDG is not set +# CONFIG_STM32_WWDG is not set +# CONFIG_STM32_NOEXT_VECTORS is not set + +# +# Alternate Pin Mapping +# +# CONFIG_STM32_FLASH_PREFETCH is not set +# CONFIG_STM32_JTAG_DISABLE is not set +CONFIG_STM32_JTAG_FULL_ENABLE=y +# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set +# CONFIG_STM32_JTAG_SW_ENABLE is not set +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +# CONFIG_STM32_FORCEPOWER is not set +# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set +# CONFIG_STM32_CCMEXCLUDE is not set + +# +# Timer Configuration +# +# CONFIG_STM32_ONESHOT is not set +# CONFIG_STM32_FREERUN is not set +# CONFIG_STM32_TIM1_CAP is not set +# CONFIG_STM32_TIM2_CAP is not set +# CONFIG_STM32_TIM3_CAP is not set +# CONFIG_STM32_TIM4_CAP is not set +# CONFIG_STM32_TIM5_CAP is not set +# CONFIG_STM32_TIM8_CAP is not set +# CONFIG_STM32_TIM9_CAP is not set +# CONFIG_STM32_TIM10_CAP is not set +# CONFIG_STM32_TIM11_CAP is not set +# CONFIG_STM32_TIM12_CAP is not set +# CONFIG_STM32_TIM13_CAP is not set +# CONFIG_STM32_TIM14_CAP is not set +CONFIG_STM32_USART=y +CONFIG_STM32_SERIALDRIVER=y + +# +# U[S]ART Configuration +# + +# +# U[S]ART Device Configuration +# +CONFIG_STM32_USART2_SERIALDRIVER=y +# CONFIG_STM32_USART2_1WIREDRIVER is not set +# CONFIG_USART2_RS485 is not set + +# +# Serial Driver Configuration +# +# CONFIG_SERIAL_DISABLE_REORDERING is not set +# CONFIG_STM32_FLOWCONTROL_BROKEN is not set +# CONFIG_STM32_USART_BREAKS is not set +# CONFIG_STM32_USART_SINGLEWIRE is not set +# CONFIG_STM32_HAVE_RTC_COUNTER is not set +# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set + +# +# Ethernet MAC configuration +# +CONFIG_STM32_PHYADDR=0 +# CONFIG_STM32_PHYINIT is not set +# CONFIG_STM32_MII is not set +CONFIG_STM32_AUTONEG=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_100FD=0x0018 +# CONFIG_STM32_ETH_PTP is not set +CONFIG_STM32_RMII=y +# CONFIG_STM32_RMII_MCO1 is not set +# CONFIG_STM32_RMII_MCO2 is not set +CONFIG_STM32_RMII_EXTCLK=y + +# +# USB FS Host Configuration +# + +# +# USB HS Host Configuration +# + +# +# USB Host Debug Configuration +# + +# +# USB Device Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=16717 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_SIZE=114688 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +# CONFIG_ARCH_BOARD_OLIMEX_STM32H407 is not set +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="olimex-stm32-e407" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_HAVE_IRQBUTTONS=y +# CONFIG_ARCH_IRQBUTTONS is not set + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +# CONFIG_LIB_BOARDCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Clocks and Timers +# +CONFIG_ARCH_HAVE_TICKLESS=y +# CONFIG_SCHED_TICKLESS is not set +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +CONFIG_ARCH_HAVE_TIMEKEEPING=y +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2011 +CONFIG_START_MONTH=12 +CONFIG_START_DAY=6 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_WDOG_INTRESERVE=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="discover_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=31 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_HPWORK is not set +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +# CONFIG_DISABLE_POLL is not set +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +CONFIG_ARCH_HAVE_I2CRESET=y +# CONFIG_I2C is not set +CONFIG_SPI=y +# CONFIG_SPI_SLAVE is not set +CONFIG_SPI_EXCHANGE=y +# CONFIG_SPI_CMDDATA is not set +# CONFIG_SPI_CALLBACK is not set +# CONFIG_SPI_HWFEATURES is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y +# CONFIG_SPI_BITORDER is not set +# CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +CONFIG_NETDEVICES=y + +# +# General Ethernet MAC Driver Options +# +# CONFIG_NETDEV_LOOPBACK is not set +# CONFIG_NETDEV_TELNET is not set +# CONFIG_NETDEV_MULTINIC is not set +# CONFIG_ARCH_HAVE_NETDEV_STATISTICS is not set +# CONFIG_NETDEV_LATEINIT is not set + +# +# External Ethernet MAC Device Support +# +# CONFIG_NET_DM90x0 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ENCX24J600 is not set +# CONFIG_NET_E1000 is not set +# CONFIG_NET_SLIP is not set +# CONFIG_NET_FTMAC100 is not set +# CONFIG_NET_VNET is not set + +# +# External Ethernet PHY Device Support +# +# CONFIG_ARCH_PHY_INTERRUPT is not set +# CONFIG_ETH0_PHY_NONE is not set +# CONFIG_ETH0_PHY_AM79C874 is not set +# CONFIG_ETH0_PHY_KS8721 is not set +# CONFIG_ETH0_PHY_KSZ8041 is not set +# CONFIG_ETH0_PHY_KSZ8051 is not set +# CONFIG_ETH0_PHY_KSZ8061 is not set +# CONFIG_ETH0_PHY_KSZ8081 is not set +# CONFIG_ETH0_PHY_KSZ90x1 is not set +# CONFIG_ETH0_PHY_DP83848C is not set +CONFIG_ETH0_PHY_LAN8720=y +# CONFIG_ETH0_PHY_LAN8740 is not set +# CONFIG_ETH0_PHY_LAN8740A is not set +# CONFIG_ETH0_PHY_LAN8742A is not set +# CONFIG_ETH0_PHY_DM9161 is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +CONFIG_USART2_SERIALDRIVER=y +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_SERIAL_NPOLLWAITERS=2 +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +CONFIG_USART2_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# USART2 Configuration +# +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_USART2_BAUD=115200 +CONFIG_USART2_BITS=8 +CONFIG_USART2_PARITY=0 +CONFIG_USART2_2STOP=0 +# CONFIG_USART2_IFLOWCONTROL is not set +# CONFIG_USART2_OFLOWCONTROL is not set +# CONFIG_USART2_DMA is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +CONFIG_ARCH_HAVE_NET=y +CONFIG_ARCH_HAVE_PHY=y +CONFIG_NET=y +# CONFIG_NET_NOINTS is not set +# CONFIG_NET_PROMISCUOUS is not set + +# +# Driver buffer configuration +# +CONFIG_NET_MULTIBUFFER=y +CONFIG_NET_ETH_MTU=590 +CONFIG_NET_ETH_TCP_RECVWNDO=536 +CONFIG_NET_GUARDSIZE=2 + +# +# Data link support +# +# CONFIG_NET_MULTILINK is not set +CONFIG_NET_ETHERNET=y +# CONFIG_NET_LOOPBACK is not set +# CONFIG_NET_TUN is not set + +# +# Network Device Operations +# +# CONFIG_NETDEV_PHY_IOCTL is not set + +# +# Internet Protocol Selection +# +CONFIG_NET_IPv4=y +# CONFIG_NET_IPv6 is not set + +# +# Socket Support +# +CONFIG_NSOCKET_DESCRIPTORS=10 +CONFIG_NET_NACTIVESOCKETS=16 +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_SOLINGER=y + +# +# Raw Socket Support +# +# CONFIG_NET_PKT is not set + +# +# Unix Domain Socket Support +# +# CONFIG_NET_LOCAL is not set + +# +# TCP/IP Networking +# +CONFIG_NET_TCP=y +# CONFIG_NET_TCPURGDATA is not set +CONFIG_NET_TCP_CONNS=40 +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_TCP_READAHEAD=y +# CONFIG_NET_TCP_WRITE_BUFFERS is not set +CONFIG_NET_TCP_RECVDELAY=0 +CONFIG_NET_TCPBACKLOG=y +# CONFIG_NET_TCP_SPLIT is not set +# CONFIG_NET_SENDFILE is not set + +# +# UDP Networking +# +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NET_UDP_CONNS=8 +CONFIG_NET_BROADCAST=y +# CONFIG_NET_RXAVAIL is not set +CONFIG_NET_UDP_READAHEAD=y + +# +# ICMP Networking Support +# +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_PING=y + +# +# IGMPv2 Client Support +# +# CONFIG_NET_IGMP is not set + +# +# ARP Configuration +# +CONFIG_NET_ARP=y +CONFIG_NET_ARPTAB_SIZE=16 +CONFIG_NET_ARP_MAXAGE=120 +CONFIG_NET_ARP_IPIN=y +# CONFIG_NET_ARP_SEND is not set + +# +# Network I/O Buffer Support +# +CONFIG_NET_IOB=y +CONFIG_IOB_NBUFFERS=24 +CONFIG_IOB_BUFSIZE=196 +CONFIG_IOB_NCHAINS=8 +# CONFIG_NET_ARCH_INCR32 is not set +# CONFIG_NET_ARCH_CHKSUM is not set +CONFIG_NET_STATISTICS=y + +# +# Routing Table Configuration +# +# CONFIG_NET_ROUTE is not set +CONFIG_NET_HOSTNAME="" + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_FS_READABLE is not set +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_NFS is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=2 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set +CONFIG_LIBC_NETDB=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSCLIENT_ENTRIES=8 +CONFIG_NETDB_DNSCLIENT_NAMESIZE=32 +CONFIG_NETDB_DNSCLIENT_LIFESEC=3600 +CONFIG_NETDB_DNSCLIENT_MAXRESPONSE=96 +# CONFIG_NETDB_DNSSERVER_NOADDR is not set +CONFIG_NETDB_DNSSERVER_IPv4=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0a000001 + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +# CONFIG_CXX_NEWLONG is not set + +# +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set + +# +# Application Configuration +# + +# +# NxWidgets/NxWM +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_CXXTEST is not set +# CONFIG_EXAMPLES_DHCPD is not set +CONFIG_EXAMPLES_DISCOVER=y +CONFIG_EXAMPLES_DISCOVER_DHCPC=y +CONFIG_EXAMPLES_DISCOVER_NOMAC=y +CONFIG_EXAMPLES_DISCOVER_DRIPADDR=0xc0a80101 +CONFIG_EXAMPLES_DISCOVER_NETMASK=0xffffff00 +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NETTEST is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +# CONFIG_EXAMPLES_NSH is not set +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UDPBLASTER is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set +# CONFIG_EXAMPLES_WGET is not set +# CONFIG_EXAMPLES_XMLRPC is not set + +# +# External +# + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CHAT is not set +# CONFIG_NETUTILS_CODECS is not set +CONFIG_NETUTILS_DHCPC=y +# CONFIG_NETUTILS_DHCPD is not set +CONFIG_NETUTILS_DISCOVER=y +CONFIG_DISCOVER_STACK_SIZE=1024 +CONFIG_DISCOVER_PRIORITY=50 +CONFIG_DISCOVER_PORT=96 +CONFIG_DISCOVER_INTERFACE="eth0" +CONFIG_DISCOVER_DEVICE_CLASS=0xff +CONFIG_DISCOVER_DESCR="NuttX" +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +CONFIG_NETUTILS_NETLIB=y +# CONFIG_NETUTILS_NTPCLIENT is not set +# CONFIG_NETUTILS_PPPD is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TELNETD is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_WEBCLIENT is not set +# CONFIG_NETUTILS_WEBSERVER is not set +# CONFIG_NETUTILS_XMLRPC is not set + +# +# NSH Library +# +# CONFIG_NSH_LIBRARY is not set + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_NETDB is not set +# CONFIG_SYSTEM_RAMTEST is not set +# CONFIG_READLINE_HAVE_EXTMATCH is not set +# CONFIG_SYSTEM_READLINE is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/olimex-stm32-e407/discover/setenv.sh b/configs/olimex-stm32-e407/discover/setenv.sh new file mode 100755 index 0000000000..528a4978e8 --- /dev/null +++ b/configs/olimex-stm32-e407/discover/setenv.sh @@ -0,0 +1,80 @@ +#!/bin/bash +# configs/olimex-stm32-e407/discover/setenv.sh +# +# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the RIDE +# toolchain under windows. You will also have to edit this if you install +# the RIDE toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Raisonance/Ride/arm-gcc/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +#export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" +# You can this free toolchain here https://launchpad.net/gcc-arm-embedded +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" + +# These are the Cygwin paths to the locations where I installed the Atollic +# toolchain under windows. You will also have to edit this if you install +# the Atollic toolchain in any other location. /usr/bin is added before +# the Atollic bin path because there is are binaries named gcc.exe and g++.exe +# at those locations as well. +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +#export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH variable +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/configs/olimex-stm32-e407/include/board.h b/configs/olimex-stm32-e407/include/board.h index d74fd06f76..b1dff5e69a 100644 --- a/configs/olimex-stm32-e407/include/board.h +++ b/configs/olimex-stm32-e407/include/board.h @@ -228,7 +228,7 @@ /* Ethernet *************************************************************************/ #if defined(CONFIG_STM32_ETHMAC) -/* RMII interface to the LAN8720 PHY */ +/* RMII interface to the LAN8710 PHY (works with LAN8720 driver)*/ # ifndef CONFIG_STM32_RMII # error CONFIG_STM32_RMII must be defined diff --git a/configs/olimex-stm32-e407/netnsh/Make.defs b/configs/olimex-stm32-e407/netnsh/Make.defs new file mode 100644 index 0000000000..78d74cf656 --- /dev/null +++ b/configs/olimex-stm32-e407/netnsh/Make.defs @@ -0,0 +1,112 @@ +############################################################################ +# configs/olimex-stm32-e407/netnsh/Make.defs +# +# Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = diff --git a/configs/olimex-stm32-e407/netnsh/defconfig b/configs/olimex-stm32-e407/netnsh/defconfig new file mode 100644 index 0000000000..4ee6b4b742 --- /dev/null +++ b/configs/olimex-stm32-e407/netnsh/defconfig @@ -0,0 +1,1429 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +CONFIG_ARCH_HAVE_HEAPCHECK=y +# CONFIG_HEAP_COLORATION is not set +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +CONFIG_ARCH_CHIP_STM32=y +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM3 is not set +CONFIG_ARCH_CORTEXM4=y +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="stm32" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARMV7M_LAZYFPU is not set +CONFIG_ARCH_HAVE_FPU=y +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set +# CONFIG_ARMV7M_OABI_TOOLCHAIN is not set +CONFIG_ARMV7M_HAVE_STACKCHECK=y +# CONFIG_ARMV7M_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set +# CONFIG_SERIAL_TERMIOS is not set + +# +# STM32 Configuration Options +# +# CONFIG_ARCH_CHIP_STM32L151C6 is not set +# CONFIG_ARCH_CHIP_STM32L151C8 is not set +# CONFIG_ARCH_CHIP_STM32L151CB is not set +# CONFIG_ARCH_CHIP_STM32L151R6 is not set +# CONFIG_ARCH_CHIP_STM32L151R8 is not set +# CONFIG_ARCH_CHIP_STM32L151RB is not set +# CONFIG_ARCH_CHIP_STM32L151V6 is not set +# CONFIG_ARCH_CHIP_STM32L151V8 is not set +# CONFIG_ARCH_CHIP_STM32L151VB is not set +# CONFIG_ARCH_CHIP_STM32L152C6 is not set +# CONFIG_ARCH_CHIP_STM32L152C8 is not set +# CONFIG_ARCH_CHIP_STM32L152CB is not set +# CONFIG_ARCH_CHIP_STM32L152R6 is not set +# CONFIG_ARCH_CHIP_STM32L152R8 is not set +# CONFIG_ARCH_CHIP_STM32L152RB is not set +# CONFIG_ARCH_CHIP_STM32L152V6 is not set +# CONFIG_ARCH_CHIP_STM32L152V8 is not set +# CONFIG_ARCH_CHIP_STM32L152VB is not set +# CONFIG_ARCH_CHIP_STM32L162ZD is not set +# CONFIG_ARCH_CHIP_STM32L162VE is not set +# CONFIG_ARCH_CHIP_STM32F100C8 is not set +# CONFIG_ARCH_CHIP_STM32F100CB is not set +# CONFIG_ARCH_CHIP_STM32F100R8 is not set +# CONFIG_ARCH_CHIP_STM32F100RB is not set +# CONFIG_ARCH_CHIP_STM32F100RC is not set +# CONFIG_ARCH_CHIP_STM32F100RD is not set +# CONFIG_ARCH_CHIP_STM32F100RE is not set +# CONFIG_ARCH_CHIP_STM32F100V8 is not set +# CONFIG_ARCH_CHIP_STM32F100VB is not set +# CONFIG_ARCH_CHIP_STM32F100VC is not set +# CONFIG_ARCH_CHIP_STM32F100VD is not set +# CONFIG_ARCH_CHIP_STM32F100VE is not set +# CONFIG_ARCH_CHIP_STM32F102CB is not set +# CONFIG_ARCH_CHIP_STM32F103T8 is not set +# CONFIG_ARCH_CHIP_STM32F103TB is not set +# CONFIG_ARCH_CHIP_STM32F103C4 is not set +# CONFIG_ARCH_CHIP_STM32F103C8 is not set +# CONFIG_ARCH_CHIP_STM32F103CB is not set +# CONFIG_ARCH_CHIP_STM32F103R8 is not set +# CONFIG_ARCH_CHIP_STM32F103RB is not set +# CONFIG_ARCH_CHIP_STM32F103RC is not set +# CONFIG_ARCH_CHIP_STM32F103RD is not set +# CONFIG_ARCH_CHIP_STM32F103RE is not set +# CONFIG_ARCH_CHIP_STM32F103RG is not set +# CONFIG_ARCH_CHIP_STM32F103V8 is not set +# CONFIG_ARCH_CHIP_STM32F103VB is not set +# CONFIG_ARCH_CHIP_STM32F103VC is not set +# CONFIG_ARCH_CHIP_STM32F103VE is not set +# CONFIG_ARCH_CHIP_STM32F103ZE is not set +# CONFIG_ARCH_CHIP_STM32F105VB is not set +# CONFIG_ARCH_CHIP_STM32F105RB is not set +# CONFIG_ARCH_CHIP_STM32F107VC is not set +# CONFIG_ARCH_CHIP_STM32F205RG is not set +# CONFIG_ARCH_CHIP_STM32F207IG is not set +# CONFIG_ARCH_CHIP_STM32F207ZE is not set +# CONFIG_ARCH_CHIP_STM32F302K6 is not set +# CONFIG_ARCH_CHIP_STM32F302K8 is not set +# CONFIG_ARCH_CHIP_STM32F302CB is not set +# CONFIG_ARCH_CHIP_STM32F302CC is not set +# CONFIG_ARCH_CHIP_STM32F302RB is not set +# CONFIG_ARCH_CHIP_STM32F302RC is not set +# CONFIG_ARCH_CHIP_STM32F302VB is not set +# CONFIG_ARCH_CHIP_STM32F302VC is not set +# CONFIG_ARCH_CHIP_STM32F303K6 is not set +# CONFIG_ARCH_CHIP_STM32F303K8 is not set +# CONFIG_ARCH_CHIP_STM32F303C6 is not set +# CONFIG_ARCH_CHIP_STM32F303C8 is not set +# CONFIG_ARCH_CHIP_STM32F303CB is not set +# CONFIG_ARCH_CHIP_STM32F303CC is not set +# CONFIG_ARCH_CHIP_STM32F303RB is not set +# CONFIG_ARCH_CHIP_STM32F303RC is not set +# CONFIG_ARCH_CHIP_STM32F303RD is not set +# CONFIG_ARCH_CHIP_STM32F303RE is not set +# CONFIG_ARCH_CHIP_STM32F303VB is not set +# CONFIG_ARCH_CHIP_STM32F303VC is not set +# CONFIG_ARCH_CHIP_STM32F372C8 is not set +# CONFIG_ARCH_CHIP_STM32F372R8 is not set +# CONFIG_ARCH_CHIP_STM32F372V8 is not set +# CONFIG_ARCH_CHIP_STM32F372CB is not set +# CONFIG_ARCH_CHIP_STM32F372RB is not set +# CONFIG_ARCH_CHIP_STM32F372VB is not set +# CONFIG_ARCH_CHIP_STM32F372CC is not set +# CONFIG_ARCH_CHIP_STM32F372RC is not set +# CONFIG_ARCH_CHIP_STM32F372VC is not set +# CONFIG_ARCH_CHIP_STM32F373C8 is not set +# CONFIG_ARCH_CHIP_STM32F373R8 is not set +# CONFIG_ARCH_CHIP_STM32F373V8 is not set +# CONFIG_ARCH_CHIP_STM32F373CB is not set +# CONFIG_ARCH_CHIP_STM32F373RB is not set +# CONFIG_ARCH_CHIP_STM32F373VB is not set +# CONFIG_ARCH_CHIP_STM32F373CC is not set +# CONFIG_ARCH_CHIP_STM32F373RC is not set +# CONFIG_ARCH_CHIP_STM32F373VC is not set +# CONFIG_ARCH_CHIP_STM32F401RE is not set +# CONFIG_ARCH_CHIP_STM32F411RE is not set +# CONFIG_ARCH_CHIP_STM32F411VE is not set +# CONFIG_ARCH_CHIP_STM32F405RG is not set +# CONFIG_ARCH_CHIP_STM32F405VG is not set +# CONFIG_ARCH_CHIP_STM32F405ZG is not set +# CONFIG_ARCH_CHIP_STM32F407VE is not set +# CONFIG_ARCH_CHIP_STM32F407VG is not set +# CONFIG_ARCH_CHIP_STM32F407ZE is not set +CONFIG_ARCH_CHIP_STM32F407ZG=y +# CONFIG_ARCH_CHIP_STM32F407IE is not set +# CONFIG_ARCH_CHIP_STM32F407IG is not set +# CONFIG_ARCH_CHIP_STM32F427V is not set +# CONFIG_ARCH_CHIP_STM32F427Z is not set +# CONFIG_ARCH_CHIP_STM32F427I is not set +# CONFIG_ARCH_CHIP_STM32F429V is not set +# CONFIG_ARCH_CHIP_STM32F429Z is not set +# CONFIG_ARCH_CHIP_STM32F429I is not set +# CONFIG_ARCH_CHIP_STM32F429B is not set +# CONFIG_ARCH_CHIP_STM32F429N is not set +# CONFIG_ARCH_CHIP_STM32F446M is not set +# CONFIG_ARCH_CHIP_STM32F446R is not set +# CONFIG_ARCH_CHIP_STM32F446V is not set +# CONFIG_ARCH_CHIP_STM32F446Z is not set +# CONFIG_ARCH_CHIP_STM32F469A is not set +# CONFIG_ARCH_CHIP_STM32F469I is not set +# CONFIG_ARCH_CHIP_STM32F469B is not set +# CONFIG_ARCH_CHIP_STM32F469N is not set +CONFIG_STM32_FLASH_CONFIG_DEFAULT=y +# CONFIG_STM32_FLASH_CONFIG_4 is not set +# CONFIG_STM32_FLASH_CONFIG_6 is not set +# CONFIG_STM32_FLASH_CONFIG_8 is not set +# CONFIG_STM32_FLASH_CONFIG_B is not set +# CONFIG_STM32_FLASH_CONFIG_C is not set +# CONFIG_STM32_FLASH_CONFIG_D is not set +# CONFIG_STM32_FLASH_CONFIG_E is not set +# CONFIG_STM32_FLASH_CONFIG_F is not set +# CONFIG_STM32_FLASH_CONFIG_G is not set +# CONFIG_STM32_FLASH_CONFIG_I is not set +# CONFIG_STM32_STM32L15XX is not set +# CONFIG_STM32_ENERGYLITE is not set +# CONFIG_STM32_STM32F10XX is not set +# CONFIG_STM32_VALUELINE is not set +# CONFIG_STM32_CONNECTIVITYLINE is not set +# CONFIG_STM32_PERFORMANCELINE is not set +# CONFIG_STM32_USBACCESSLINE is not set +# CONFIG_STM32_HIGHDENSITY is not set +# CONFIG_STM32_MEDIUMDENSITY is not set +# CONFIG_STM32_LOWDENSITY is not set +# CONFIG_STM32_STM32F20XX is not set +# CONFIG_STM32_STM32F205 is not set +# CONFIG_STM32_STM32F207 is not set +# CONFIG_STM32_STM32F30XX is not set +# CONFIG_STM32_STM32F302 is not set +# CONFIG_STM32_STM32F303 is not set +# CONFIG_STM32_STM32F37XX is not set +CONFIG_STM32_STM32F40XX=y +# CONFIG_STM32_STM32F401 is not set +# CONFIG_STM32_STM32F411 is not set +# CONFIG_STM32_STM32F405 is not set +CONFIG_STM32_STM32F407=y +# CONFIG_STM32_STM32F427 is not set +# CONFIG_STM32_STM32F429 is not set +# CONFIG_STM32_STM32F446 is not set +# CONFIG_STM32_STM32F469 is not set +# CONFIG_STM32_DFU is not set + +# +# STM32 Peripheral Support +# +CONFIG_STM32_HAVE_CCM=y +# CONFIG_STM32_HAVE_USBDEV is not set +CONFIG_STM32_HAVE_OTGFS=y +CONFIG_STM32_HAVE_FSMC=y +# CONFIG_STM32_HAVE_LTDC is not set +CONFIG_STM32_HAVE_USART3=y +CONFIG_STM32_HAVE_UART4=y +CONFIG_STM32_HAVE_UART5=y +CONFIG_STM32_HAVE_USART6=y +# CONFIG_STM32_HAVE_UART7 is not set +# CONFIG_STM32_HAVE_UART8 is not set +CONFIG_STM32_HAVE_TIM1=y +CONFIG_STM32_HAVE_TIM2=y +CONFIG_STM32_HAVE_TIM3=y +CONFIG_STM32_HAVE_TIM4=y +CONFIG_STM32_HAVE_TIM5=y +CONFIG_STM32_HAVE_TIM6=y +CONFIG_STM32_HAVE_TIM7=y +CONFIG_STM32_HAVE_TIM8=y +CONFIG_STM32_HAVE_TIM9=y +CONFIG_STM32_HAVE_TIM10=y +CONFIG_STM32_HAVE_TIM11=y +CONFIG_STM32_HAVE_TIM12=y +CONFIG_STM32_HAVE_TIM13=y +CONFIG_STM32_HAVE_TIM14=y +# CONFIG_STM32_HAVE_TIM15 is not set +# CONFIG_STM32_HAVE_TIM16 is not set +# CONFIG_STM32_HAVE_TIM17 is not set +CONFIG_STM32_HAVE_ADC2=y +CONFIG_STM32_HAVE_ADC3=y +# CONFIG_STM32_HAVE_ADC4 is not set +# CONFIG_STM32_HAVE_ADC1_DMA is not set +# CONFIG_STM32_HAVE_ADC2_DMA is not set +# CONFIG_STM32_HAVE_ADC3_DMA is not set +# CONFIG_STM32_HAVE_ADC4_DMA is not set +CONFIG_STM32_HAVE_CAN1=y +CONFIG_STM32_HAVE_CAN2=y +CONFIG_STM32_HAVE_DAC1=y +CONFIG_STM32_HAVE_DAC2=y +CONFIG_STM32_HAVE_RNG=y +CONFIG_STM32_HAVE_ETHMAC=y +CONFIG_STM32_HAVE_I2C2=y +CONFIG_STM32_HAVE_I2C3=y +CONFIG_STM32_HAVE_SPI2=y +CONFIG_STM32_HAVE_SPI3=y +# CONFIG_STM32_HAVE_SPI4 is not set +# CONFIG_STM32_HAVE_SPI5 is not set +# CONFIG_STM32_HAVE_SPI6 is not set +# CONFIG_STM32_HAVE_SAIPLL is not set +# CONFIG_STM32_HAVE_I2SPLL is not set +# CONFIG_STM32_ADC1 is not set +# CONFIG_STM32_ADC2 is not set +# CONFIG_STM32_ADC3 is not set +# CONFIG_STM32_BKPSRAM is not set +# CONFIG_STM32_CAN1 is not set +# CONFIG_STM32_CAN2 is not set +# CONFIG_STM32_CCMDATARAM is not set +# CONFIG_STM32_CRC is not set +# CONFIG_STM32_CRYP is not set +# CONFIG_STM32_DMA1 is not set +# CONFIG_STM32_DMA2 is not set +# CONFIG_STM32_DAC1 is not set +# CONFIG_STM32_DAC2 is not set +# CONFIG_STM32_DCMI is not set +CONFIG_STM32_ETHMAC=y +# CONFIG_STM32_FSMC is not set +# CONFIG_STM32_HASH is not set +# CONFIG_STM32_I2C1 is not set +# CONFIG_STM32_I2C2 is not set +# CONFIG_STM32_I2C3 is not set +# CONFIG_STM32_OTGFS is not set +# CONFIG_STM32_OTGHS is not set +CONFIG_STM32_PWR=y +# CONFIG_STM32_RNG is not set +# CONFIG_STM32_SDIO is not set +# CONFIG_STM32_SPI1 is not set +# CONFIG_STM32_SPI2 is not set +# CONFIG_STM32_SPI3 is not set +CONFIG_STM32_SYSCFG=y +# CONFIG_STM32_TIM1 is not set +# CONFIG_STM32_TIM2 is not set +# CONFIG_STM32_TIM3 is not set +# CONFIG_STM32_TIM4 is not set +# CONFIG_STM32_TIM5 is not set +# CONFIG_STM32_TIM6 is not set +# CONFIG_STM32_TIM7 is not set +# CONFIG_STM32_TIM8 is not set +# CONFIG_STM32_TIM9 is not set +# CONFIG_STM32_TIM10 is not set +# CONFIG_STM32_TIM11 is not set +# CONFIG_STM32_TIM12 is not set +# CONFIG_STM32_TIM13 is not set +# CONFIG_STM32_TIM14 is not set +# CONFIG_STM32_USART1 is not set +CONFIG_STM32_USART2=y +# CONFIG_STM32_USART3 is not set +# CONFIG_STM32_UART4 is not set +# CONFIG_STM32_UART5 is not set +# CONFIG_STM32_USART6 is not set +# CONFIG_STM32_IWDG is not set +# CONFIG_STM32_WWDG is not set +# CONFIG_STM32_NOEXT_VECTORS is not set + +# +# Alternate Pin Mapping +# +# CONFIG_STM32_FLASH_PREFETCH is not set +# CONFIG_STM32_JTAG_DISABLE is not set +CONFIG_STM32_JTAG_FULL_ENABLE=y +# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set +# CONFIG_STM32_JTAG_SW_ENABLE is not set +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +# CONFIG_STM32_FORCEPOWER is not set +# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set +# CONFIG_STM32_CCMEXCLUDE is not set + +# +# Timer Configuration +# +# CONFIG_STM32_ONESHOT is not set +# CONFIG_STM32_FREERUN is not set +# CONFIG_STM32_TIM1_CAP is not set +# CONFIG_STM32_TIM2_CAP is not set +# CONFIG_STM32_TIM3_CAP is not set +# CONFIG_STM32_TIM4_CAP is not set +# CONFIG_STM32_TIM5_CAP is not set +# CONFIG_STM32_TIM8_CAP is not set +# CONFIG_STM32_TIM9_CAP is not set +# CONFIG_STM32_TIM10_CAP is not set +# CONFIG_STM32_TIM11_CAP is not set +# CONFIG_STM32_TIM12_CAP is not set +# CONFIG_STM32_TIM13_CAP is not set +# CONFIG_STM32_TIM14_CAP is not set +CONFIG_STM32_USART=y +CONFIG_STM32_SERIALDRIVER=y + +# +# U[S]ART Configuration +# + +# +# U[S]ART Device Configuration +# +CONFIG_STM32_USART2_SERIALDRIVER=y +# CONFIG_STM32_USART2_1WIREDRIVER is not set +# CONFIG_USART2_RS485 is not set + +# +# Serial Driver Configuration +# +# CONFIG_SERIAL_DISABLE_REORDERING is not set +# CONFIG_STM32_FLOWCONTROL_BROKEN is not set +# CONFIG_STM32_USART_BREAKS is not set +# CONFIG_STM32_USART_SINGLEWIRE is not set +# CONFIG_STM32_HAVE_RTC_COUNTER is not set +# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set + +# +# Ethernet MAC configuration +# +CONFIG_STM32_PHYADDR=0 +# CONFIG_STM32_PHYINIT is not set +# CONFIG_STM32_MII is not set +CONFIG_STM32_AUTONEG=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_100FD=0x0018 +# CONFIG_STM32_ETH_PTP is not set +CONFIG_STM32_RMII=y +# CONFIG_STM32_RMII_MCO1 is not set +# CONFIG_STM32_RMII_MCO2 is not set +CONFIG_STM32_RMII_EXTCLK=y + +# +# USB FS Host Configuration +# + +# +# USB HS Host Configuration +# + +# +# USB Host Debug Configuration +# + +# +# USB Device Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=16717 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_SIZE=114688 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +# CONFIG_ARCH_BOARD_OLIMEX_STM32H407 is not set +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="olimex-stm32-e407" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_HAVE_IRQBUTTONS=y +# CONFIG_ARCH_IRQBUTTONS is not set + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +# CONFIG_LIB_BOARDCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Clocks and Timers +# +CONFIG_ARCH_HAVE_TICKLESS=y +# CONFIG_SCHED_TICKLESS is not set +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +CONFIG_ARCH_HAVE_TIMEKEEPING=y +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2011 +CONFIG_START_MONTH=12 +CONFIG_START_DAY=6 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_WDOG_INTRESERVE=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=31 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_HPWORK is not set +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +# CONFIG_DISABLE_POLL is not set +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +CONFIG_ARCH_HAVE_I2CRESET=y +# CONFIG_I2C is not set +CONFIG_SPI=y +# CONFIG_SPI_SLAVE is not set +CONFIG_SPI_EXCHANGE=y +# CONFIG_SPI_CMDDATA is not set +# CONFIG_SPI_CALLBACK is not set +# CONFIG_SPI_HWFEATURES is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y +# CONFIG_SPI_BITORDER is not set +# CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +CONFIG_NETDEVICES=y + +# +# General Ethernet MAC Driver Options +# +# CONFIG_NETDEV_LOOPBACK is not set +CONFIG_NETDEV_TELNET=y +CONFIG_TELNET_RXBUFFER_SIZE=256 +CONFIG_TELNET_TXBUFFER_SIZE=256 +# CONFIG_NETDEV_MULTINIC is not set +# CONFIG_ARCH_HAVE_NETDEV_STATISTICS is not set +# CONFIG_NETDEV_LATEINIT is not set + +# +# External Ethernet MAC Device Support +# +# CONFIG_NET_DM90x0 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ENCX24J600 is not set +# CONFIG_NET_E1000 is not set +# CONFIG_NET_SLIP is not set +# CONFIG_NET_FTMAC100 is not set +# CONFIG_NET_VNET is not set + +# +# External Ethernet PHY Device Support +# +# CONFIG_ARCH_PHY_INTERRUPT is not set +# CONFIG_ETH0_PHY_NONE is not set +# CONFIG_ETH0_PHY_AM79C874 is not set +# CONFIG_ETH0_PHY_KS8721 is not set +# CONFIG_ETH0_PHY_KSZ8041 is not set +# CONFIG_ETH0_PHY_KSZ8051 is not set +# CONFIG_ETH0_PHY_KSZ8061 is not set +# CONFIG_ETH0_PHY_KSZ8081 is not set +# CONFIG_ETH0_PHY_KSZ90x1 is not set +# CONFIG_ETH0_PHY_DP83848C is not set +CONFIG_ETH0_PHY_LAN8720=y +# CONFIG_ETH0_PHY_LAN8740 is not set +# CONFIG_ETH0_PHY_LAN8740A is not set +# CONFIG_ETH0_PHY_LAN8742A is not set +# CONFIG_ETH0_PHY_DM9161 is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +CONFIG_USART2_SERIALDRIVER=y +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_SERIAL_NPOLLWAITERS=2 +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +CONFIG_USART2_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# USART2 Configuration +# +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_USART2_BAUD=115200 +CONFIG_USART2_BITS=8 +CONFIG_USART2_PARITY=0 +CONFIG_USART2_2STOP=0 +# CONFIG_USART2_IFLOWCONTROL is not set +# CONFIG_USART2_OFLOWCONTROL is not set +# CONFIG_USART2_DMA is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +CONFIG_ARCH_HAVE_NET=y +CONFIG_ARCH_HAVE_PHY=y +CONFIG_NET=y +# CONFIG_NET_NOINTS is not set +# CONFIG_NET_PROMISCUOUS is not set + +# +# Driver buffer configuration +# +CONFIG_NET_MULTIBUFFER=y +CONFIG_NET_ETH_MTU=590 +CONFIG_NET_ETH_TCP_RECVWNDO=536 +CONFIG_NET_GUARDSIZE=2 + +# +# Data link support +# +# CONFIG_NET_MULTILINK is not set +CONFIG_NET_ETHERNET=y +# CONFIG_NET_LOOPBACK is not set +# CONFIG_NET_TUN is not set + +# +# Network Device Operations +# +# CONFIG_NETDEV_PHY_IOCTL is not set + +# +# Internet Protocol Selection +# +CONFIG_NET_IPv4=y +# CONFIG_NET_IPv6 is not set + +# +# Socket Support +# +CONFIG_NSOCKET_DESCRIPTORS=10 +CONFIG_NET_NACTIVESOCKETS=16 +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_SOLINGER=y + +# +# Raw Socket Support +# +# CONFIG_NET_PKT is not set + +# +# Unix Domain Socket Support +# +# CONFIG_NET_LOCAL is not set + +# +# TCP/IP Networking +# +CONFIG_NET_TCP=y +# CONFIG_NET_TCPURGDATA is not set +CONFIG_NET_TCP_CONNS=40 +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_TCP_READAHEAD=y +# CONFIG_NET_TCP_WRITE_BUFFERS is not set +CONFIG_NET_TCP_RECVDELAY=0 +CONFIG_NET_TCPBACKLOG=y +# CONFIG_NET_TCP_SPLIT is not set +# CONFIG_NET_SENDFILE is not set + +# +# UDP Networking +# +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NET_UDP_CONNS=8 +CONFIG_NET_BROADCAST=y +# CONFIG_NET_RXAVAIL is not set +CONFIG_NET_UDP_READAHEAD=y + +# +# ICMP Networking Support +# +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_PING=y + +# +# IGMPv2 Client Support +# +# CONFIG_NET_IGMP is not set + +# +# ARP Configuration +# +CONFIG_NET_ARP=y +CONFIG_NET_ARPTAB_SIZE=16 +CONFIG_NET_ARP_MAXAGE=120 +CONFIG_NET_ARP_IPIN=y +# CONFIG_NET_ARP_SEND is not set + +# +# Network I/O Buffer Support +# +CONFIG_NET_IOB=y +CONFIG_IOB_NBUFFERS=24 +CONFIG_IOB_BUFSIZE=196 +CONFIG_IOB_NCHAINS=8 +# CONFIG_NET_ARCH_INCR32 is not set +# CONFIG_NET_ARCH_CHKSUM is not set +CONFIG_NET_STATISTICS=y + +# +# Routing Table Configuration +# +# CONFIG_NET_ROUTE is not set +CONFIG_NET_HOSTNAME="" + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_FS_READABLE is not set +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_NFS is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=2 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set +CONFIG_LIBC_NETDB=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSCLIENT_ENTRIES=8 +CONFIG_NETDB_DNSCLIENT_NAMESIZE=32 +CONFIG_NETDB_DNSCLIENT_LIFESEC=3600 +CONFIG_NETDB_DNSCLIENT_MAXRESPONSE=96 +# CONFIG_NETDB_DNSSERVER_NOADDR is not set +CONFIG_NETDB_DNSSERVER_IPv4=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0a000001 + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +# CONFIG_CXX_NEWLONG is not set + +# +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set + +# +# Application Configuration +# + +# +# NxWidgets/NxWM +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_CXXTEST is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_DISCOVER is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NETTEST is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UDPBLASTER is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set +# CONFIG_EXAMPLES_XMLRPC is not set + +# +# External +# + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CHAT is not set +# CONFIG_NETUTILS_CODECS is not set +CONFIG_NETUTILS_DHCPC=y +# CONFIG_NETUTILS_DHCPD is not set +CONFIG_NETUTILS_DISCOVER=y +CONFIG_DISCOVER_STACK_SIZE=1024 +CONFIG_DISCOVER_PRIORITY=50 +CONFIG_DISCOVER_PORT=96 +CONFIG_DISCOVER_INTERFACE="eth0" +CONFIG_DISCOVER_DEVICE_CLASS=0xff +CONFIG_DISCOVER_DESCR="NuttX" +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +CONFIG_NETUTILS_NETLIB=y +# CONFIG_NETUTILS_NTPCLIENT is not set +# CONFIG_NETUTILS_PPPD is not set +# CONFIG_NETUTILS_SMTP is not set +CONFIG_NETUTILS_TELNETD=y +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_WEBCLIENT is not set +# CONFIG_NETUTILS_WEBSERVER is not set +# CONFIG_NETUTILS_XMLRPC is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +# CONFIG_NSH_READLINE is not set +CONFIG_NSH_CLE=y +CONFIG_NSH_LINELEN=80 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +CONFIG_NSH_CMDPARMS=y +CONFIG_NSH_MAXARGUMENTS=6 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_ARP is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +CONFIG_NSH_DISABLE_IFCONFIG=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PS=y +# CONFIG_NSH_DISABLE_PING is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Configure Command Options +# +CONFIG_NSH_CMDOPT_DF_H=y +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_CMDOPT_HEXDUMP=y +CONFIG_NSH_FILEIOSIZE=1024 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ARCHINIT is not set + +# +# Networking Configuration +# +CONFIG_NSH_NETINIT=y +# CONFIG_NSH_NETINIT_THREAD is not set + +# +# IP Address Configuration +# +CONFIG_NSH_DHCPC=y + +# +# IPv4 Addresses +# +CONFIG_NSH_DRIPADDR=0xc0a80101 +CONFIG_NSH_NETMASK=0xffffff00 +# CONFIG_NSH_DNS is not set +CONFIG_NSH_NOMAC=y +CONFIG_NSH_SWMAC=y +CONFIG_NSH_MACADDR=0x00e0deadbeef +CONFIG_NSH_MAX_ROUNDTRIP=20 + +# +# Telnet Configuration +# +CONFIG_NSH_TELNET=y +CONFIG_NSH_TELNETD_PORT=23 +CONFIG_NSH_TELNETD_DAEMONPRIO=100 +CONFIG_NSH_TELNETD_DAEMONSTACKSIZE=2048 +CONFIG_NSH_TELNETD_CLIENTPRIO=100 +CONFIG_NSH_TELNETD_CLIENTSTACKSIZE=2048 +CONFIG_NSH_IOBUFFER_SIZE=512 +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set +# CONFIG_NSH_TELNET_LOGIN is not set + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +CONFIG_SYSTEM_CLE=y +CONFIG_SYSTEM_CLE_DEBUGLEVEL=0 +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_NETDB is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set \ No newline at end of file diff --git a/configs/olimex-stm32-e407/netnsh/setenv.sh b/configs/olimex-stm32-e407/netnsh/setenv.sh new file mode 100755 index 0000000000..d6f071c221 --- /dev/null +++ b/configs/olimex-stm32-e407/netnsh/setenv.sh @@ -0,0 +1,80 @@ +#!/bin/bash +# configs/olimex-stm32-e407/netnsh/setenv.sh +# +# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the RIDE +# toolchain under windows. You will also have to edit this if you install +# the RIDE toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Raisonance/Ride/arm-gcc/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +#export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" +# You can this free toolchain here https://launchpad.net/gcc-arm-embedded +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" + +# These are the Cygwin paths to the locations where I installed the Atollic +# toolchain under windows. You will also have to edit this if you install +# the Atollic toolchain in any other location. /usr/bin is added before +# the Atollic bin path because there is are binaries named gcc.exe and g++.exe +# at those locations as well. +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +#export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH variable +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/configs/olimex-stm32-e407/src/olimex-stm32-e407.h b/configs/olimex-stm32-e407/src/olimex-stm32-e407.h index 3294e189e4..cc3eff460d 100644 --- a/configs/olimex-stm32-e407/src/olimex-stm32-e407.h +++ b/configs/olimex-stm32-e407/src/olimex-stm32-e407.h @@ -49,7 +49,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Configuration from stm32f4discovert*/ +/* Configuration from stm32f4discovery */ /* Assume that we have everything */ @@ -106,16 +106,6 @@ # undef HAVE_NETMONITOR #endif -/* The NSH Network Monitor cannot be used with the STM32F4DIS-BB base board. - * That is because the LAN8720 is configured in REF_CLK OUT mode. In that - * mode, the PHY interrupt is not supported. The NINT pin serves instead as - * REFLCK0. - */ - -#ifdef CONFIG_STM32F4DISBB -# undef HAVE_NETMONITOR -#endif - /* procfs File System */ #ifdef CONFIG_FS_PROCFS @@ -179,6 +169,31 @@ # define GPIO_OTGHS_OVER (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN11) #endif +/* LAN8710 works with LAN8720 driver + * + * ---------- ------------- ------------ + * PIO SIGNAL Comments + * ---------- ------------- ------------ + * PG11 TXEN + * PG13 TXD0 + * PG14 TXD1 + * PC4 RXD0/MODE0 + * PC5 RXD1/MODE1 + * PA7 CRS_DIV/MODE2 + * PA2 MDIO + * PC1 MDC + * PA3 NINT/REFCLK0 + * PG6 NRST + * ---------- ------------- ------------ + */ + +#if defined(CONFIG_STM32_ETHMAC) +# define GPIO_EMAC_NINT (GPIO_INPUT|GPIO_PULLUP|GPIO_EXTI| \ + GPIO_PORTA|GPIO_PIN3) +# define GPIO_EMAC_NRST (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_SET|GPIO_PORTG|GPIO_PIN6) +#endif + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/configs/olimex-stm32-e407/telnetd/Make.defs b/configs/olimex-stm32-e407/telnetd/Make.defs new file mode 100644 index 0000000000..efcd1c954b --- /dev/null +++ b/configs/olimex-stm32-e407/telnetd/Make.defs @@ -0,0 +1,112 @@ +############################################################################ +# configs/olimex-stm32-e407/telnetd/Make.defs +# +# Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = diff --git a/configs/olimex-stm32-e407/telnetd/defconfig b/configs/olimex-stm32-e407/telnetd/defconfig new file mode 100644 index 0000000000..70071a6b4f --- /dev/null +++ b/configs/olimex-stm32-e407/telnetd/defconfig @@ -0,0 +1,1304 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +CONFIG_ARCH_HAVE_HEAPCHECK=y +# CONFIG_HEAP_COLORATION is not set +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +CONFIG_ARCH_CHIP_STM32=y +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM3 is not set +CONFIG_ARCH_CORTEXM4=y +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="stm32" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARMV7M_LAZYFPU is not set +CONFIG_ARCH_HAVE_FPU=y +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set +# CONFIG_ARMV7M_OABI_TOOLCHAIN is not set +CONFIG_ARMV7M_HAVE_STACKCHECK=y +# CONFIG_ARMV7M_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set +# CONFIG_SERIAL_TERMIOS is not set + +# +# STM32 Configuration Options +# +# CONFIG_ARCH_CHIP_STM32L151C6 is not set +# CONFIG_ARCH_CHIP_STM32L151C8 is not set +# CONFIG_ARCH_CHIP_STM32L151CB is not set +# CONFIG_ARCH_CHIP_STM32L151R6 is not set +# CONFIG_ARCH_CHIP_STM32L151R8 is not set +# CONFIG_ARCH_CHIP_STM32L151RB is not set +# CONFIG_ARCH_CHIP_STM32L151V6 is not set +# CONFIG_ARCH_CHIP_STM32L151V8 is not set +# CONFIG_ARCH_CHIP_STM32L151VB is not set +# CONFIG_ARCH_CHIP_STM32L152C6 is not set +# CONFIG_ARCH_CHIP_STM32L152C8 is not set +# CONFIG_ARCH_CHIP_STM32L152CB is not set +# CONFIG_ARCH_CHIP_STM32L152R6 is not set +# CONFIG_ARCH_CHIP_STM32L152R8 is not set +# CONFIG_ARCH_CHIP_STM32L152RB is not set +# CONFIG_ARCH_CHIP_STM32L152V6 is not set +# CONFIG_ARCH_CHIP_STM32L152V8 is not set +# CONFIG_ARCH_CHIP_STM32L152VB is not set +# CONFIG_ARCH_CHIP_STM32L162ZD is not set +# CONFIG_ARCH_CHIP_STM32L162VE is not set +# CONFIG_ARCH_CHIP_STM32F100C8 is not set +# CONFIG_ARCH_CHIP_STM32F100CB is not set +# CONFIG_ARCH_CHIP_STM32F100R8 is not set +# CONFIG_ARCH_CHIP_STM32F100RB is not set +# CONFIG_ARCH_CHIP_STM32F100RC is not set +# CONFIG_ARCH_CHIP_STM32F100RD is not set +# CONFIG_ARCH_CHIP_STM32F100RE is not set +# CONFIG_ARCH_CHIP_STM32F100V8 is not set +# CONFIG_ARCH_CHIP_STM32F100VB is not set +# CONFIG_ARCH_CHIP_STM32F100VC is not set +# CONFIG_ARCH_CHIP_STM32F100VD is not set +# CONFIG_ARCH_CHIP_STM32F100VE is not set +# CONFIG_ARCH_CHIP_STM32F102CB is not set +# CONFIG_ARCH_CHIP_STM32F103T8 is not set +# CONFIG_ARCH_CHIP_STM32F103TB is not set +# CONFIG_ARCH_CHIP_STM32F103C4 is not set +# CONFIG_ARCH_CHIP_STM32F103C8 is not set +# CONFIG_ARCH_CHIP_STM32F103CB is not set +# CONFIG_ARCH_CHIP_STM32F103R8 is not set +# CONFIG_ARCH_CHIP_STM32F103RB is not set +# CONFIG_ARCH_CHIP_STM32F103RC is not set +# CONFIG_ARCH_CHIP_STM32F103RD is not set +# CONFIG_ARCH_CHIP_STM32F103RE is not set +# CONFIG_ARCH_CHIP_STM32F103RG is not set +# CONFIG_ARCH_CHIP_STM32F103V8 is not set +# CONFIG_ARCH_CHIP_STM32F103VB is not set +# CONFIG_ARCH_CHIP_STM32F103VC is not set +# CONFIG_ARCH_CHIP_STM32F103VE is not set +# CONFIG_ARCH_CHIP_STM32F103ZE is not set +# CONFIG_ARCH_CHIP_STM32F105VB is not set +# CONFIG_ARCH_CHIP_STM32F105RB is not set +# CONFIG_ARCH_CHIP_STM32F107VC is not set +# CONFIG_ARCH_CHIP_STM32F205RG is not set +# CONFIG_ARCH_CHIP_STM32F207IG is not set +# CONFIG_ARCH_CHIP_STM32F207ZE is not set +# CONFIG_ARCH_CHIP_STM32F302K6 is not set +# CONFIG_ARCH_CHIP_STM32F302K8 is not set +# CONFIG_ARCH_CHIP_STM32F302CB is not set +# CONFIG_ARCH_CHIP_STM32F302CC is not set +# CONFIG_ARCH_CHIP_STM32F302RB is not set +# CONFIG_ARCH_CHIP_STM32F302RC is not set +# CONFIG_ARCH_CHIP_STM32F302VB is not set +# CONFIG_ARCH_CHIP_STM32F302VC is not set +# CONFIG_ARCH_CHIP_STM32F303K6 is not set +# CONFIG_ARCH_CHIP_STM32F303K8 is not set +# CONFIG_ARCH_CHIP_STM32F303C6 is not set +# CONFIG_ARCH_CHIP_STM32F303C8 is not set +# CONFIG_ARCH_CHIP_STM32F303CB is not set +# CONFIG_ARCH_CHIP_STM32F303CC is not set +# CONFIG_ARCH_CHIP_STM32F303RB is not set +# CONFIG_ARCH_CHIP_STM32F303RC is not set +# CONFIG_ARCH_CHIP_STM32F303RD is not set +# CONFIG_ARCH_CHIP_STM32F303RE is not set +# CONFIG_ARCH_CHIP_STM32F303VB is not set +# CONFIG_ARCH_CHIP_STM32F303VC is not set +# CONFIG_ARCH_CHIP_STM32F372C8 is not set +# CONFIG_ARCH_CHIP_STM32F372R8 is not set +# CONFIG_ARCH_CHIP_STM32F372V8 is not set +# CONFIG_ARCH_CHIP_STM32F372CB is not set +# CONFIG_ARCH_CHIP_STM32F372RB is not set +# CONFIG_ARCH_CHIP_STM32F372VB is not set +# CONFIG_ARCH_CHIP_STM32F372CC is not set +# CONFIG_ARCH_CHIP_STM32F372RC is not set +# CONFIG_ARCH_CHIP_STM32F372VC is not set +# CONFIG_ARCH_CHIP_STM32F373C8 is not set +# CONFIG_ARCH_CHIP_STM32F373R8 is not set +# CONFIG_ARCH_CHIP_STM32F373V8 is not set +# CONFIG_ARCH_CHIP_STM32F373CB is not set +# CONFIG_ARCH_CHIP_STM32F373RB is not set +# CONFIG_ARCH_CHIP_STM32F373VB is not set +# CONFIG_ARCH_CHIP_STM32F373CC is not set +# CONFIG_ARCH_CHIP_STM32F373RC is not set +# CONFIG_ARCH_CHIP_STM32F373VC is not set +# CONFIG_ARCH_CHIP_STM32F401RE is not set +# CONFIG_ARCH_CHIP_STM32F411RE is not set +# CONFIG_ARCH_CHIP_STM32F411VE is not set +# CONFIG_ARCH_CHIP_STM32F405RG is not set +# CONFIG_ARCH_CHIP_STM32F405VG is not set +# CONFIG_ARCH_CHIP_STM32F405ZG is not set +# CONFIG_ARCH_CHIP_STM32F407VE is not set +# CONFIG_ARCH_CHIP_STM32F407VG is not set +# CONFIG_ARCH_CHIP_STM32F407ZE is not set +CONFIG_ARCH_CHIP_STM32F407ZG=y +# CONFIG_ARCH_CHIP_STM32F407IE is not set +# CONFIG_ARCH_CHIP_STM32F407IG is not set +# CONFIG_ARCH_CHIP_STM32F427V is not set +# CONFIG_ARCH_CHIP_STM32F427Z is not set +# CONFIG_ARCH_CHIP_STM32F427I is not set +# CONFIG_ARCH_CHIP_STM32F429V is not set +# CONFIG_ARCH_CHIP_STM32F429Z is not set +# CONFIG_ARCH_CHIP_STM32F429I is not set +# CONFIG_ARCH_CHIP_STM32F429B is not set +# CONFIG_ARCH_CHIP_STM32F429N is not set +# CONFIG_ARCH_CHIP_STM32F446M is not set +# CONFIG_ARCH_CHIP_STM32F446R is not set +# CONFIG_ARCH_CHIP_STM32F446V is not set +# CONFIG_ARCH_CHIP_STM32F446Z is not set +# CONFIG_ARCH_CHIP_STM32F469A is not set +# CONFIG_ARCH_CHIP_STM32F469I is not set +# CONFIG_ARCH_CHIP_STM32F469B is not set +# CONFIG_ARCH_CHIP_STM32F469N is not set +CONFIG_STM32_FLASH_CONFIG_DEFAULT=y +# CONFIG_STM32_FLASH_CONFIG_4 is not set +# CONFIG_STM32_FLASH_CONFIG_6 is not set +# CONFIG_STM32_FLASH_CONFIG_8 is not set +# CONFIG_STM32_FLASH_CONFIG_B is not set +# CONFIG_STM32_FLASH_CONFIG_C is not set +# CONFIG_STM32_FLASH_CONFIG_D is not set +# CONFIG_STM32_FLASH_CONFIG_E is not set +# CONFIG_STM32_FLASH_CONFIG_F is not set +# CONFIG_STM32_FLASH_CONFIG_G is not set +# CONFIG_STM32_FLASH_CONFIG_I is not set +# CONFIG_STM32_STM32L15XX is not set +# CONFIG_STM32_ENERGYLITE is not set +# CONFIG_STM32_STM32F10XX is not set +# CONFIG_STM32_VALUELINE is not set +# CONFIG_STM32_CONNECTIVITYLINE is not set +# CONFIG_STM32_PERFORMANCELINE is not set +# CONFIG_STM32_USBACCESSLINE is not set +# CONFIG_STM32_HIGHDENSITY is not set +# CONFIG_STM32_MEDIUMDENSITY is not set +# CONFIG_STM32_LOWDENSITY is not set +# CONFIG_STM32_STM32F20XX is not set +# CONFIG_STM32_STM32F205 is not set +# CONFIG_STM32_STM32F207 is not set +# CONFIG_STM32_STM32F30XX is not set +# CONFIG_STM32_STM32F302 is not set +# CONFIG_STM32_STM32F303 is not set +# CONFIG_STM32_STM32F37XX is not set +CONFIG_STM32_STM32F40XX=y +# CONFIG_STM32_STM32F401 is not set +# CONFIG_STM32_STM32F411 is not set +# CONFIG_STM32_STM32F405 is not set +CONFIG_STM32_STM32F407=y +# CONFIG_STM32_STM32F427 is not set +# CONFIG_STM32_STM32F429 is not set +# CONFIG_STM32_STM32F446 is not set +# CONFIG_STM32_STM32F469 is not set +# CONFIG_STM32_DFU is not set + +# +# STM32 Peripheral Support +# +CONFIG_STM32_HAVE_CCM=y +# CONFIG_STM32_HAVE_USBDEV is not set +CONFIG_STM32_HAVE_OTGFS=y +CONFIG_STM32_HAVE_FSMC=y +# CONFIG_STM32_HAVE_LTDC is not set +CONFIG_STM32_HAVE_USART3=y +CONFIG_STM32_HAVE_UART4=y +CONFIG_STM32_HAVE_UART5=y +CONFIG_STM32_HAVE_USART6=y +# CONFIG_STM32_HAVE_UART7 is not set +# CONFIG_STM32_HAVE_UART8 is not set +CONFIG_STM32_HAVE_TIM1=y +CONFIG_STM32_HAVE_TIM2=y +CONFIG_STM32_HAVE_TIM3=y +CONFIG_STM32_HAVE_TIM4=y +CONFIG_STM32_HAVE_TIM5=y +CONFIG_STM32_HAVE_TIM6=y +CONFIG_STM32_HAVE_TIM7=y +CONFIG_STM32_HAVE_TIM8=y +CONFIG_STM32_HAVE_TIM9=y +CONFIG_STM32_HAVE_TIM10=y +CONFIG_STM32_HAVE_TIM11=y +CONFIG_STM32_HAVE_TIM12=y +CONFIG_STM32_HAVE_TIM13=y +CONFIG_STM32_HAVE_TIM14=y +# CONFIG_STM32_HAVE_TIM15 is not set +# CONFIG_STM32_HAVE_TIM16 is not set +# CONFIG_STM32_HAVE_TIM17 is not set +CONFIG_STM32_HAVE_ADC2=y +CONFIG_STM32_HAVE_ADC3=y +# CONFIG_STM32_HAVE_ADC4 is not set +# CONFIG_STM32_HAVE_ADC1_DMA is not set +# CONFIG_STM32_HAVE_ADC2_DMA is not set +# CONFIG_STM32_HAVE_ADC3_DMA is not set +# CONFIG_STM32_HAVE_ADC4_DMA is not set +CONFIG_STM32_HAVE_CAN1=y +CONFIG_STM32_HAVE_CAN2=y +CONFIG_STM32_HAVE_DAC1=y +CONFIG_STM32_HAVE_DAC2=y +CONFIG_STM32_HAVE_RNG=y +CONFIG_STM32_HAVE_ETHMAC=y +CONFIG_STM32_HAVE_I2C2=y +CONFIG_STM32_HAVE_I2C3=y +CONFIG_STM32_HAVE_SPI2=y +CONFIG_STM32_HAVE_SPI3=y +# CONFIG_STM32_HAVE_SPI4 is not set +# CONFIG_STM32_HAVE_SPI5 is not set +# CONFIG_STM32_HAVE_SPI6 is not set +# CONFIG_STM32_HAVE_SAIPLL is not set +# CONFIG_STM32_HAVE_I2SPLL is not set +# CONFIG_STM32_ADC1 is not set +# CONFIG_STM32_ADC2 is not set +# CONFIG_STM32_ADC3 is not set +# CONFIG_STM32_BKPSRAM is not set +# CONFIG_STM32_CAN1 is not set +# CONFIG_STM32_CAN2 is not set +# CONFIG_STM32_CCMDATARAM is not set +# CONFIG_STM32_CRC is not set +# CONFIG_STM32_CRYP is not set +# CONFIG_STM32_DMA1 is not set +# CONFIG_STM32_DMA2 is not set +# CONFIG_STM32_DAC1 is not set +# CONFIG_STM32_DAC2 is not set +# CONFIG_STM32_DCMI is not set +CONFIG_STM32_ETHMAC=y +# CONFIG_STM32_FSMC is not set +# CONFIG_STM32_HASH is not set +# CONFIG_STM32_I2C1 is not set +# CONFIG_STM32_I2C2 is not set +# CONFIG_STM32_I2C3 is not set +# CONFIG_STM32_OTGFS is not set +# CONFIG_STM32_OTGHS is not set +CONFIG_STM32_PWR=y +# CONFIG_STM32_RNG is not set +# CONFIG_STM32_SDIO is not set +# CONFIG_STM32_SPI1 is not set +# CONFIG_STM32_SPI2 is not set +# CONFIG_STM32_SPI3 is not set +CONFIG_STM32_SYSCFG=y +# CONFIG_STM32_TIM1 is not set +# CONFIG_STM32_TIM2 is not set +# CONFIG_STM32_TIM3 is not set +# CONFIG_STM32_TIM4 is not set +# CONFIG_STM32_TIM5 is not set +# CONFIG_STM32_TIM6 is not set +# CONFIG_STM32_TIM7 is not set +# CONFIG_STM32_TIM8 is not set +# CONFIG_STM32_TIM9 is not set +# CONFIG_STM32_TIM10 is not set +# CONFIG_STM32_TIM11 is not set +# CONFIG_STM32_TIM12 is not set +# CONFIG_STM32_TIM13 is not set +# CONFIG_STM32_TIM14 is not set +# CONFIG_STM32_USART1 is not set +CONFIG_STM32_USART2=y +# CONFIG_STM32_USART3 is not set +# CONFIG_STM32_UART4 is not set +# CONFIG_STM32_UART5 is not set +# CONFIG_STM32_USART6 is not set +# CONFIG_STM32_IWDG is not set +# CONFIG_STM32_WWDG is not set +# CONFIG_STM32_NOEXT_VECTORS is not set + +# +# Alternate Pin Mapping +# +# CONFIG_STM32_FLASH_PREFETCH is not set +# CONFIG_STM32_JTAG_DISABLE is not set +CONFIG_STM32_JTAG_FULL_ENABLE=y +# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set +# CONFIG_STM32_JTAG_SW_ENABLE is not set +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +# CONFIG_STM32_FORCEPOWER is not set +# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set +# CONFIG_STM32_CCMEXCLUDE is not set + +# +# Timer Configuration +# +# CONFIG_STM32_ONESHOT is not set +# CONFIG_STM32_FREERUN is not set +# CONFIG_STM32_TIM1_CAP is not set +# CONFIG_STM32_TIM2_CAP is not set +# CONFIG_STM32_TIM3_CAP is not set +# CONFIG_STM32_TIM4_CAP is not set +# CONFIG_STM32_TIM5_CAP is not set +# CONFIG_STM32_TIM8_CAP is not set +# CONFIG_STM32_TIM9_CAP is not set +# CONFIG_STM32_TIM10_CAP is not set +# CONFIG_STM32_TIM11_CAP is not set +# CONFIG_STM32_TIM12_CAP is not set +# CONFIG_STM32_TIM13_CAP is not set +# CONFIG_STM32_TIM14_CAP is not set +CONFIG_STM32_USART=y +CONFIG_STM32_SERIALDRIVER=y + +# +# U[S]ART Configuration +# + +# +# U[S]ART Device Configuration +# +CONFIG_STM32_USART2_SERIALDRIVER=y +# CONFIG_STM32_USART2_1WIREDRIVER is not set +# CONFIG_USART2_RS485 is not set + +# +# Serial Driver Configuration +# +# CONFIG_SERIAL_DISABLE_REORDERING is not set +# CONFIG_STM32_FLOWCONTROL_BROKEN is not set +# CONFIG_STM32_USART_BREAKS is not set +# CONFIG_STM32_USART_SINGLEWIRE is not set +# CONFIG_STM32_HAVE_RTC_COUNTER is not set +# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set + +# +# Ethernet MAC configuration +# +CONFIG_STM32_PHYADDR=0 +# CONFIG_STM32_PHYINIT is not set +# CONFIG_STM32_MII is not set +CONFIG_STM32_AUTONEG=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_100FD=0x0018 +# CONFIG_STM32_ETH_PTP is not set +CONFIG_STM32_RMII=y +# CONFIG_STM32_RMII_MCO1 is not set +# CONFIG_STM32_RMII_MCO2 is not set +CONFIG_STM32_RMII_EXTCLK=y + +# +# USB FS Host Configuration +# + +# +# USB HS Host Configuration +# + +# +# USB Host Debug Configuration +# + +# +# USB Device Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=16717 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_SIZE=114688 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +# CONFIG_ARCH_BOARD_OLIMEX_STM32H407 is not set +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="olimex-stm32-e407" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_HAVE_IRQBUTTONS=y +# CONFIG_ARCH_IRQBUTTONS is not set + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +# CONFIG_LIB_BOARDCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Clocks and Timers +# +CONFIG_ARCH_HAVE_TICKLESS=y +# CONFIG_SCHED_TICKLESS is not set +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +CONFIG_ARCH_HAVE_TIMEKEEPING=y +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2011 +CONFIG_START_MONTH=12 +CONFIG_START_DAY=6 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_WDOG_INTRESERVE=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="telnetd_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=31 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_HPWORK is not set +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +# CONFIG_DISABLE_POLL is not set +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +CONFIG_ARCH_HAVE_I2CRESET=y +# CONFIG_I2C is not set +CONFIG_SPI=y +# CONFIG_SPI_SLAVE is not set +CONFIG_SPI_EXCHANGE=y +# CONFIG_SPI_CMDDATA is not set +# CONFIG_SPI_CALLBACK is not set +# CONFIG_SPI_HWFEATURES is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y +# CONFIG_SPI_BITORDER is not set +# CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +CONFIG_NETDEVICES=y + +# +# General Ethernet MAC Driver Options +# +# CONFIG_NETDEV_LOOPBACK is not set +CONFIG_NETDEV_TELNET=y +CONFIG_TELNET_RXBUFFER_SIZE=256 +CONFIG_TELNET_TXBUFFER_SIZE=256 +# CONFIG_NETDEV_MULTINIC is not set +# CONFIG_ARCH_HAVE_NETDEV_STATISTICS is not set +# CONFIG_NETDEV_LATEINIT is not set + +# +# External Ethernet MAC Device Support +# +# CONFIG_NET_DM90x0 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ENCX24J600 is not set +# CONFIG_NET_E1000 is not set +# CONFIG_NET_SLIP is not set +# CONFIG_NET_FTMAC100 is not set +# CONFIG_NET_VNET is not set + +# +# External Ethernet PHY Device Support +# +# CONFIG_ARCH_PHY_INTERRUPT is not set +# CONFIG_ETH0_PHY_NONE is not set +# CONFIG_ETH0_PHY_AM79C874 is not set +# CONFIG_ETH0_PHY_KS8721 is not set +# CONFIG_ETH0_PHY_KSZ8041 is not set +# CONFIG_ETH0_PHY_KSZ8051 is not set +# CONFIG_ETH0_PHY_KSZ8061 is not set +# CONFIG_ETH0_PHY_KSZ8081 is not set +# CONFIG_ETH0_PHY_KSZ90x1 is not set +# CONFIG_ETH0_PHY_DP83848C is not set +CONFIG_ETH0_PHY_LAN8720=y +# CONFIG_ETH0_PHY_LAN8740 is not set +# CONFIG_ETH0_PHY_LAN8740A is not set +# CONFIG_ETH0_PHY_LAN8742A is not set +# CONFIG_ETH0_PHY_DM9161 is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +CONFIG_USART2_SERIALDRIVER=y +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_SERIAL_NPOLLWAITERS=2 +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +CONFIG_USART2_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# USART2 Configuration +# +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_USART2_BAUD=115200 +CONFIG_USART2_BITS=8 +CONFIG_USART2_PARITY=0 +CONFIG_USART2_2STOP=0 +# CONFIG_USART2_IFLOWCONTROL is not set +# CONFIG_USART2_OFLOWCONTROL is not set +# CONFIG_USART2_DMA is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +CONFIG_ARCH_HAVE_NET=y +CONFIG_ARCH_HAVE_PHY=y +CONFIG_NET=y +# CONFIG_NET_NOINTS is not set +# CONFIG_NET_PROMISCUOUS is not set + +# +# Driver buffer configuration +# +CONFIG_NET_MULTIBUFFER=y +CONFIG_NET_ETH_MTU=590 +CONFIG_NET_ETH_TCP_RECVWNDO=536 +CONFIG_NET_GUARDSIZE=2 + +# +# Data link support +# +# CONFIG_NET_MULTILINK is not set +CONFIG_NET_ETHERNET=y +# CONFIG_NET_LOOPBACK is not set +# CONFIG_NET_TUN is not set + +# +# Network Device Operations +# +# CONFIG_NETDEV_PHY_IOCTL is not set + +# +# Internet Protocol Selection +# +CONFIG_NET_IPv4=y +# CONFIG_NET_IPv6 is not set + +# +# Socket Support +# +CONFIG_NSOCKET_DESCRIPTORS=10 +CONFIG_NET_NACTIVESOCKETS=16 +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_SOLINGER=y + +# +# Raw Socket Support +# +# CONFIG_NET_PKT is not set + +# +# Unix Domain Socket Support +# +# CONFIG_NET_LOCAL is not set + +# +# TCP/IP Networking +# +CONFIG_NET_TCP=y +# CONFIG_NET_TCPURGDATA is not set +CONFIG_NET_TCP_CONNS=40 +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_TCP_READAHEAD=y +# CONFIG_NET_TCP_WRITE_BUFFERS is not set +CONFIG_NET_TCP_RECVDELAY=0 +CONFIG_NET_TCPBACKLOG=y +# CONFIG_NET_TCP_SPLIT is not set +# CONFIG_NET_SENDFILE is not set + +# +# UDP Networking +# +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NET_UDP_CONNS=8 +CONFIG_NET_BROADCAST=y +# CONFIG_NET_RXAVAIL is not set +CONFIG_NET_UDP_READAHEAD=y + +# +# ICMP Networking Support +# +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_PING=y + +# +# IGMPv2 Client Support +# +# CONFIG_NET_IGMP is not set + +# +# ARP Configuration +# +CONFIG_NET_ARP=y +CONFIG_NET_ARPTAB_SIZE=16 +CONFIG_NET_ARP_MAXAGE=120 +CONFIG_NET_ARP_IPIN=y +# CONFIG_NET_ARP_SEND is not set + +# +# Network I/O Buffer Support +# +CONFIG_NET_IOB=y +CONFIG_IOB_NBUFFERS=24 +CONFIG_IOB_BUFSIZE=196 +CONFIG_IOB_NCHAINS=8 +# CONFIG_NET_ARCH_INCR32 is not set +# CONFIG_NET_ARCH_CHKSUM is not set +CONFIG_NET_STATISTICS=y + +# +# Routing Table Configuration +# +# CONFIG_NET_ROUTE is not set +CONFIG_NET_HOSTNAME="" + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_FS_READABLE is not set +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_NFS is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=2 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set +CONFIG_LIBC_NETDB=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSCLIENT_ENTRIES=8 +CONFIG_NETDB_DNSCLIENT_NAMESIZE=32 +CONFIG_NETDB_DNSCLIENT_LIFESEC=3600 +CONFIG_NETDB_DNSCLIENT_MAXRESPONSE=96 +# CONFIG_NETDB_DNSSERVER_NOADDR is not set +CONFIG_NETDB_DNSSERVER_IPv4=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0a000001 + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +# CONFIG_CXX_NEWLONG is not set + +# +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set + +# +# Application Configuration +# + +# +# NxWidgets/NxWM +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_CXXTEST is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_DISCOVER is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NETTEST is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +# CONFIG_EXAMPLES_NSH is not set +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +CONFIG_EXAMPLES_TELNETD=y +CONFIG_EXAMPLES_TELNETD_NOMAC=y +CONFIG_EXAMPLES_TELNETD_IPADDR=0xc0a80185 +CONFIG_EXAMPLES_TELNETD_DRIPADDR=0xc0a80101 +CONFIG_EXAMPLES_TELNETD_NETMASK=0xffffff00 +CONFIG_EXAMPLES_TELNETD_DAEMONPRIO=128 +CONFIG_EXAMPLES_TELNETD_DAEMONSTACKSIZE=2048 +CONFIG_EXAMPLES_TELNETD_CLIENTPRIO=128 +CONFIG_EXAMPLES_TELNETD_CLIENTSTACKSIZE=2048 +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UDPBLASTER is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set +# CONFIG_EXAMPLES_WGET is not set +# CONFIG_EXAMPLES_XMLRPC is not set + +# +# External +# + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CHAT is not set +# CONFIG_NETUTILS_CODECS is not set +CONFIG_NETUTILS_DHCPC=y +# CONFIG_NETUTILS_DHCPD is not set +CONFIG_NETUTILS_DISCOVER=y +CONFIG_DISCOVER_STACK_SIZE=1024 +CONFIG_DISCOVER_PRIORITY=50 +CONFIG_DISCOVER_PORT=96 +CONFIG_DISCOVER_INTERFACE="eth0" +CONFIG_DISCOVER_DEVICE_CLASS=0xff +CONFIG_DISCOVER_DESCR="NuttX" +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +CONFIG_NETUTILS_NETLIB=y +# CONFIG_NETUTILS_NTPCLIENT is not set +# CONFIG_NETUTILS_PPPD is not set +# CONFIG_NETUTILS_SMTP is not set +CONFIG_NETUTILS_TELNETD=y +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_WEBCLIENT is not set +# CONFIG_NETUTILS_WEBSERVER is not set +# CONFIG_NETUTILS_XMLRPC is not set + +# +# NSH Library +# +# CONFIG_NSH_LIBRARY is not set + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_NETDB is not set +# CONFIG_SYSTEM_RAMTEST is not set +# CONFIG_READLINE_HAVE_EXTMATCH is not set +# CONFIG_SYSTEM_READLINE is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set \ No newline at end of file diff --git a/configs/olimex-stm32-e407/telnetd/setenv.sh b/configs/olimex-stm32-e407/telnetd/setenv.sh new file mode 100755 index 0000000000..62aa001c6e --- /dev/null +++ b/configs/olimex-stm32-e407/telnetd/setenv.sh @@ -0,0 +1,80 @@ +#!/bin/bash +# configs/olimex-stm32-e407/telnetd/setenv.sh +# +# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the RIDE +# toolchain under windows. You will also have to edit this if you install +# the RIDE toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Raisonance/Ride/arm-gcc/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +#export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" +# You can this free toolchain here https://launchpad.net/gcc-arm-embedded +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" + +# These are the Cygwin paths to the locations where I installed the Atollic +# toolchain under windows. You will also have to edit this if you install +# the Atollic toolchain in any other location. /usr/bin is added before +# the Atollic bin path because there is are binaries named gcc.exe and g++.exe +# at those locations as well. +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +#export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH variable +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/configs/olimex-stm32-e407/webserver/Make.defs b/configs/olimex-stm32-e407/webserver/Make.defs new file mode 100644 index 0000000000..621d215e24 --- /dev/null +++ b/configs/olimex-stm32-e407/webserver/Make.defs @@ -0,0 +1,112 @@ +############################################################################ +# configs/olimex-stm32-e407/webserver/Make.defs +# +# Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = diff --git a/configs/olimex-stm32-e407/webserver/defconfig b/configs/olimex-stm32-e407/webserver/defconfig new file mode 100644 index 0000000000..9ba20f2d5c --- /dev/null +++ b/configs/olimex-stm32-e407/webserver/defconfig @@ -0,0 +1,1309 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +CONFIG_ARCH_HAVE_HEAPCHECK=y +# CONFIG_HEAP_COLORATION is not set +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +CONFIG_ARCH_CHIP_STM32=y +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM3 is not set +CONFIG_ARCH_CORTEXM4=y +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="stm32" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARMV7M_LAZYFPU is not set +CONFIG_ARCH_HAVE_FPU=y +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set +# CONFIG_ARMV7M_OABI_TOOLCHAIN is not set +CONFIG_ARMV7M_HAVE_STACKCHECK=y +# CONFIG_ARMV7M_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set +# CONFIG_SERIAL_TERMIOS is not set + +# +# STM32 Configuration Options +# +# CONFIG_ARCH_CHIP_STM32L151C6 is not set +# CONFIG_ARCH_CHIP_STM32L151C8 is not set +# CONFIG_ARCH_CHIP_STM32L151CB is not set +# CONFIG_ARCH_CHIP_STM32L151R6 is not set +# CONFIG_ARCH_CHIP_STM32L151R8 is not set +# CONFIG_ARCH_CHIP_STM32L151RB is not set +# CONFIG_ARCH_CHIP_STM32L151V6 is not set +# CONFIG_ARCH_CHIP_STM32L151V8 is not set +# CONFIG_ARCH_CHIP_STM32L151VB is not set +# CONFIG_ARCH_CHIP_STM32L152C6 is not set +# CONFIG_ARCH_CHIP_STM32L152C8 is not set +# CONFIG_ARCH_CHIP_STM32L152CB is not set +# CONFIG_ARCH_CHIP_STM32L152R6 is not set +# CONFIG_ARCH_CHIP_STM32L152R8 is not set +# CONFIG_ARCH_CHIP_STM32L152RB is not set +# CONFIG_ARCH_CHIP_STM32L152V6 is not set +# CONFIG_ARCH_CHIP_STM32L152V8 is not set +# CONFIG_ARCH_CHIP_STM32L152VB is not set +# CONFIG_ARCH_CHIP_STM32L162ZD is not set +# CONFIG_ARCH_CHIP_STM32L162VE is not set +# CONFIG_ARCH_CHIP_STM32F100C8 is not set +# CONFIG_ARCH_CHIP_STM32F100CB is not set +# CONFIG_ARCH_CHIP_STM32F100R8 is not set +# CONFIG_ARCH_CHIP_STM32F100RB is not set +# CONFIG_ARCH_CHIP_STM32F100RC is not set +# CONFIG_ARCH_CHIP_STM32F100RD is not set +# CONFIG_ARCH_CHIP_STM32F100RE is not set +# CONFIG_ARCH_CHIP_STM32F100V8 is not set +# CONFIG_ARCH_CHIP_STM32F100VB is not set +# CONFIG_ARCH_CHIP_STM32F100VC is not set +# CONFIG_ARCH_CHIP_STM32F100VD is not set +# CONFIG_ARCH_CHIP_STM32F100VE is not set +# CONFIG_ARCH_CHIP_STM32F102CB is not set +# CONFIG_ARCH_CHIP_STM32F103T8 is not set +# CONFIG_ARCH_CHIP_STM32F103TB is not set +# CONFIG_ARCH_CHIP_STM32F103C4 is not set +# CONFIG_ARCH_CHIP_STM32F103C8 is not set +# CONFIG_ARCH_CHIP_STM32F103CB is not set +# CONFIG_ARCH_CHIP_STM32F103R8 is not set +# CONFIG_ARCH_CHIP_STM32F103RB is not set +# CONFIG_ARCH_CHIP_STM32F103RC is not set +# CONFIG_ARCH_CHIP_STM32F103RD is not set +# CONFIG_ARCH_CHIP_STM32F103RE is not set +# CONFIG_ARCH_CHIP_STM32F103RG is not set +# CONFIG_ARCH_CHIP_STM32F103V8 is not set +# CONFIG_ARCH_CHIP_STM32F103VB is not set +# CONFIG_ARCH_CHIP_STM32F103VC is not set +# CONFIG_ARCH_CHIP_STM32F103VE is not set +# CONFIG_ARCH_CHIP_STM32F103ZE is not set +# CONFIG_ARCH_CHIP_STM32F105VB is not set +# CONFIG_ARCH_CHIP_STM32F105RB is not set +# CONFIG_ARCH_CHIP_STM32F107VC is not set +# CONFIG_ARCH_CHIP_STM32F205RG is not set +# CONFIG_ARCH_CHIP_STM32F207IG is not set +# CONFIG_ARCH_CHIP_STM32F207ZE is not set +# CONFIG_ARCH_CHIP_STM32F302K6 is not set +# CONFIG_ARCH_CHIP_STM32F302K8 is not set +# CONFIG_ARCH_CHIP_STM32F302CB is not set +# CONFIG_ARCH_CHIP_STM32F302CC is not set +# CONFIG_ARCH_CHIP_STM32F302RB is not set +# CONFIG_ARCH_CHIP_STM32F302RC is not set +# CONFIG_ARCH_CHIP_STM32F302VB is not set +# CONFIG_ARCH_CHIP_STM32F302VC is not set +# CONFIG_ARCH_CHIP_STM32F303K6 is not set +# CONFIG_ARCH_CHIP_STM32F303K8 is not set +# CONFIG_ARCH_CHIP_STM32F303C6 is not set +# CONFIG_ARCH_CHIP_STM32F303C8 is not set +# CONFIG_ARCH_CHIP_STM32F303CB is not set +# CONFIG_ARCH_CHIP_STM32F303CC is not set +# CONFIG_ARCH_CHIP_STM32F303RB is not set +# CONFIG_ARCH_CHIP_STM32F303RC is not set +# CONFIG_ARCH_CHIP_STM32F303RD is not set +# CONFIG_ARCH_CHIP_STM32F303RE is not set +# CONFIG_ARCH_CHIP_STM32F303VB is not set +# CONFIG_ARCH_CHIP_STM32F303VC is not set +# CONFIG_ARCH_CHIP_STM32F372C8 is not set +# CONFIG_ARCH_CHIP_STM32F372R8 is not set +# CONFIG_ARCH_CHIP_STM32F372V8 is not set +# CONFIG_ARCH_CHIP_STM32F372CB is not set +# CONFIG_ARCH_CHIP_STM32F372RB is not set +# CONFIG_ARCH_CHIP_STM32F372VB is not set +# CONFIG_ARCH_CHIP_STM32F372CC is not set +# CONFIG_ARCH_CHIP_STM32F372RC is not set +# CONFIG_ARCH_CHIP_STM32F372VC is not set +# CONFIG_ARCH_CHIP_STM32F373C8 is not set +# CONFIG_ARCH_CHIP_STM32F373R8 is not set +# CONFIG_ARCH_CHIP_STM32F373V8 is not set +# CONFIG_ARCH_CHIP_STM32F373CB is not set +# CONFIG_ARCH_CHIP_STM32F373RB is not set +# CONFIG_ARCH_CHIP_STM32F373VB is not set +# CONFIG_ARCH_CHIP_STM32F373CC is not set +# CONFIG_ARCH_CHIP_STM32F373RC is not set +# CONFIG_ARCH_CHIP_STM32F373VC is not set +# CONFIG_ARCH_CHIP_STM32F401RE is not set +# CONFIG_ARCH_CHIP_STM32F411RE is not set +# CONFIG_ARCH_CHIP_STM32F411VE is not set +# CONFIG_ARCH_CHIP_STM32F405RG is not set +# CONFIG_ARCH_CHIP_STM32F405VG is not set +# CONFIG_ARCH_CHIP_STM32F405ZG is not set +# CONFIG_ARCH_CHIP_STM32F407VE is not set +# CONFIG_ARCH_CHIP_STM32F407VG is not set +# CONFIG_ARCH_CHIP_STM32F407ZE is not set +CONFIG_ARCH_CHIP_STM32F407ZG=y +# CONFIG_ARCH_CHIP_STM32F407IE is not set +# CONFIG_ARCH_CHIP_STM32F407IG is not set +# CONFIG_ARCH_CHIP_STM32F427V is not set +# CONFIG_ARCH_CHIP_STM32F427Z is not set +# CONFIG_ARCH_CHIP_STM32F427I is not set +# CONFIG_ARCH_CHIP_STM32F429V is not set +# CONFIG_ARCH_CHIP_STM32F429Z is not set +# CONFIG_ARCH_CHIP_STM32F429I is not set +# CONFIG_ARCH_CHIP_STM32F429B is not set +# CONFIG_ARCH_CHIP_STM32F429N is not set +# CONFIG_ARCH_CHIP_STM32F446M is not set +# CONFIG_ARCH_CHIP_STM32F446R is not set +# CONFIG_ARCH_CHIP_STM32F446V is not set +# CONFIG_ARCH_CHIP_STM32F446Z is not set +# CONFIG_ARCH_CHIP_STM32F469A is not set +# CONFIG_ARCH_CHIP_STM32F469I is not set +# CONFIG_ARCH_CHIP_STM32F469B is not set +# CONFIG_ARCH_CHIP_STM32F469N is not set +CONFIG_STM32_FLASH_CONFIG_DEFAULT=y +# CONFIG_STM32_FLASH_CONFIG_4 is not set +# CONFIG_STM32_FLASH_CONFIG_6 is not set +# CONFIG_STM32_FLASH_CONFIG_8 is not set +# CONFIG_STM32_FLASH_CONFIG_B is not set +# CONFIG_STM32_FLASH_CONFIG_C is not set +# CONFIG_STM32_FLASH_CONFIG_D is not set +# CONFIG_STM32_FLASH_CONFIG_E is not set +# CONFIG_STM32_FLASH_CONFIG_F is not set +# CONFIG_STM32_FLASH_CONFIG_G is not set +# CONFIG_STM32_FLASH_CONFIG_I is not set +# CONFIG_STM32_STM32L15XX is not set +# CONFIG_STM32_ENERGYLITE is not set +# CONFIG_STM32_STM32F10XX is not set +# CONFIG_STM32_VALUELINE is not set +# CONFIG_STM32_CONNECTIVITYLINE is not set +# CONFIG_STM32_PERFORMANCELINE is not set +# CONFIG_STM32_USBACCESSLINE is not set +# CONFIG_STM32_HIGHDENSITY is not set +# CONFIG_STM32_MEDIUMDENSITY is not set +# CONFIG_STM32_LOWDENSITY is not set +# CONFIG_STM32_STM32F20XX is not set +# CONFIG_STM32_STM32F205 is not set +# CONFIG_STM32_STM32F207 is not set +# CONFIG_STM32_STM32F30XX is not set +# CONFIG_STM32_STM32F302 is not set +# CONFIG_STM32_STM32F303 is not set +# CONFIG_STM32_STM32F37XX is not set +CONFIG_STM32_STM32F40XX=y +# CONFIG_STM32_STM32F401 is not set +# CONFIG_STM32_STM32F411 is not set +# CONFIG_STM32_STM32F405 is not set +CONFIG_STM32_STM32F407=y +# CONFIG_STM32_STM32F427 is not set +# CONFIG_STM32_STM32F429 is not set +# CONFIG_STM32_STM32F446 is not set +# CONFIG_STM32_STM32F469 is not set +# CONFIG_STM32_DFU is not set + +# +# STM32 Peripheral Support +# +CONFIG_STM32_HAVE_CCM=y +# CONFIG_STM32_HAVE_USBDEV is not set +CONFIG_STM32_HAVE_OTGFS=y +CONFIG_STM32_HAVE_FSMC=y +# CONFIG_STM32_HAVE_LTDC is not set +CONFIG_STM32_HAVE_USART3=y +CONFIG_STM32_HAVE_UART4=y +CONFIG_STM32_HAVE_UART5=y +CONFIG_STM32_HAVE_USART6=y +# CONFIG_STM32_HAVE_UART7 is not set +# CONFIG_STM32_HAVE_UART8 is not set +CONFIG_STM32_HAVE_TIM1=y +CONFIG_STM32_HAVE_TIM2=y +CONFIG_STM32_HAVE_TIM3=y +CONFIG_STM32_HAVE_TIM4=y +CONFIG_STM32_HAVE_TIM5=y +CONFIG_STM32_HAVE_TIM6=y +CONFIG_STM32_HAVE_TIM7=y +CONFIG_STM32_HAVE_TIM8=y +CONFIG_STM32_HAVE_TIM9=y +CONFIG_STM32_HAVE_TIM10=y +CONFIG_STM32_HAVE_TIM11=y +CONFIG_STM32_HAVE_TIM12=y +CONFIG_STM32_HAVE_TIM13=y +CONFIG_STM32_HAVE_TIM14=y +# CONFIG_STM32_HAVE_TIM15 is not set +# CONFIG_STM32_HAVE_TIM16 is not set +# CONFIG_STM32_HAVE_TIM17 is not set +CONFIG_STM32_HAVE_ADC2=y +CONFIG_STM32_HAVE_ADC3=y +# CONFIG_STM32_HAVE_ADC4 is not set +# CONFIG_STM32_HAVE_ADC1_DMA is not set +# CONFIG_STM32_HAVE_ADC2_DMA is not set +# CONFIG_STM32_HAVE_ADC3_DMA is not set +# CONFIG_STM32_HAVE_ADC4_DMA is not set +CONFIG_STM32_HAVE_CAN1=y +CONFIG_STM32_HAVE_CAN2=y +CONFIG_STM32_HAVE_DAC1=y +CONFIG_STM32_HAVE_DAC2=y +CONFIG_STM32_HAVE_RNG=y +CONFIG_STM32_HAVE_ETHMAC=y +CONFIG_STM32_HAVE_I2C2=y +CONFIG_STM32_HAVE_I2C3=y +CONFIG_STM32_HAVE_SPI2=y +CONFIG_STM32_HAVE_SPI3=y +# CONFIG_STM32_HAVE_SPI4 is not set +# CONFIG_STM32_HAVE_SPI5 is not set +# CONFIG_STM32_HAVE_SPI6 is not set +# CONFIG_STM32_HAVE_SAIPLL is not set +# CONFIG_STM32_HAVE_I2SPLL is not set +# CONFIG_STM32_ADC1 is not set +# CONFIG_STM32_ADC2 is not set +# CONFIG_STM32_ADC3 is not set +# CONFIG_STM32_BKPSRAM is not set +# CONFIG_STM32_CAN1 is not set +# CONFIG_STM32_CAN2 is not set +# CONFIG_STM32_CCMDATARAM is not set +# CONFIG_STM32_CRC is not set +# CONFIG_STM32_CRYP is not set +# CONFIG_STM32_DMA1 is not set +# CONFIG_STM32_DMA2 is not set +# CONFIG_STM32_DAC1 is not set +# CONFIG_STM32_DAC2 is not set +# CONFIG_STM32_DCMI is not set +CONFIG_STM32_ETHMAC=y +# CONFIG_STM32_FSMC is not set +# CONFIG_STM32_HASH is not set +# CONFIG_STM32_I2C1 is not set +# CONFIG_STM32_I2C2 is not set +# CONFIG_STM32_I2C3 is not set +# CONFIG_STM32_OTGFS is not set +# CONFIG_STM32_OTGHS is not set +CONFIG_STM32_PWR=y +# CONFIG_STM32_RNG is not set +# CONFIG_STM32_SDIO is not set +# CONFIG_STM32_SPI1 is not set +# CONFIG_STM32_SPI2 is not set +# CONFIG_STM32_SPI3 is not set +CONFIG_STM32_SYSCFG=y +# CONFIG_STM32_TIM1 is not set +# CONFIG_STM32_TIM2 is not set +# CONFIG_STM32_TIM3 is not set +# CONFIG_STM32_TIM4 is not set +# CONFIG_STM32_TIM5 is not set +# CONFIG_STM32_TIM6 is not set +# CONFIG_STM32_TIM7 is not set +# CONFIG_STM32_TIM8 is not set +# CONFIG_STM32_TIM9 is not set +# CONFIG_STM32_TIM10 is not set +# CONFIG_STM32_TIM11 is not set +# CONFIG_STM32_TIM12 is not set +# CONFIG_STM32_TIM13 is not set +# CONFIG_STM32_TIM14 is not set +# CONFIG_STM32_USART1 is not set +CONFIG_STM32_USART2=y +# CONFIG_STM32_USART3 is not set +# CONFIG_STM32_UART4 is not set +# CONFIG_STM32_UART5 is not set +# CONFIG_STM32_USART6 is not set +# CONFIG_STM32_IWDG is not set +# CONFIG_STM32_WWDG is not set +# CONFIG_STM32_NOEXT_VECTORS is not set + +# +# Alternate Pin Mapping +# +# CONFIG_STM32_FLASH_PREFETCH is not set +# CONFIG_STM32_JTAG_DISABLE is not set +CONFIG_STM32_JTAG_FULL_ENABLE=y +# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set +# CONFIG_STM32_JTAG_SW_ENABLE is not set +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +# CONFIG_STM32_FORCEPOWER is not set +# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set +# CONFIG_STM32_CCMEXCLUDE is not set + +# +# Timer Configuration +# +# CONFIG_STM32_ONESHOT is not set +# CONFIG_STM32_FREERUN is not set +# CONFIG_STM32_TIM1_CAP is not set +# CONFIG_STM32_TIM2_CAP is not set +# CONFIG_STM32_TIM3_CAP is not set +# CONFIG_STM32_TIM4_CAP is not set +# CONFIG_STM32_TIM5_CAP is not set +# CONFIG_STM32_TIM8_CAP is not set +# CONFIG_STM32_TIM9_CAP is not set +# CONFIG_STM32_TIM10_CAP is not set +# CONFIG_STM32_TIM11_CAP is not set +# CONFIG_STM32_TIM12_CAP is not set +# CONFIG_STM32_TIM13_CAP is not set +# CONFIG_STM32_TIM14_CAP is not set +CONFIG_STM32_USART=y +CONFIG_STM32_SERIALDRIVER=y + +# +# U[S]ART Configuration +# + +# +# U[S]ART Device Configuration +# +CONFIG_STM32_USART2_SERIALDRIVER=y +# CONFIG_STM32_USART2_1WIREDRIVER is not set +# CONFIG_USART2_RS485 is not set + +# +# Serial Driver Configuration +# +# CONFIG_SERIAL_DISABLE_REORDERING is not set +# CONFIG_STM32_FLOWCONTROL_BROKEN is not set +# CONFIG_STM32_USART_BREAKS is not set +# CONFIG_STM32_USART_SINGLEWIRE is not set +# CONFIG_STM32_HAVE_RTC_COUNTER is not set +# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set + +# +# Ethernet MAC configuration +# +CONFIG_STM32_PHYADDR=0 +# CONFIG_STM32_PHYINIT is not set +# CONFIG_STM32_MII is not set +CONFIG_STM32_AUTONEG=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_100FD=0x0018 +# CONFIG_STM32_ETH_PTP is not set +CONFIG_STM32_RMII=y +# CONFIG_STM32_RMII_MCO1 is not set +# CONFIG_STM32_RMII_MCO2 is not set +CONFIG_STM32_RMII_EXTCLK=y + +# +# USB FS Host Configuration +# + +# +# USB HS Host Configuration +# + +# +# USB Host Debug Configuration +# + +# +# USB Device Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=16717 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_SIZE=114688 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +# CONFIG_ARCH_BOARD_OLIMEX_STM32H407 is not set +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="olimex-stm32-e407" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_HAVE_IRQBUTTONS=y +# CONFIG_ARCH_IRQBUTTONS is not set + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +# CONFIG_LIB_BOARDCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Clocks and Timers +# +CONFIG_ARCH_HAVE_TICKLESS=y +# CONFIG_SCHED_TICKLESS is not set +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +CONFIG_ARCH_HAVE_TIMEKEEPING=y +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2011 +CONFIG_START_MONTH=12 +CONFIG_START_DAY=6 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_WDOG_INTRESERVE=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="webserver_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=31 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_HPWORK is not set +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +# CONFIG_DISABLE_POLL is not set +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +CONFIG_ARCH_HAVE_I2CRESET=y +# CONFIG_I2C is not set +CONFIG_SPI=y +# CONFIG_SPI_SLAVE is not set +CONFIG_SPI_EXCHANGE=y +# CONFIG_SPI_CMDDATA is not set +# CONFIG_SPI_CALLBACK is not set +# CONFIG_SPI_HWFEATURES is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y +# CONFIG_SPI_BITORDER is not set +# CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +CONFIG_NETDEVICES=y + +# +# General Ethernet MAC Driver Options +# +# CONFIG_NETDEV_LOOPBACK is not set +# CONFIG_NETDEV_TELNET is not set +# CONFIG_NETDEV_MULTINIC is not set +# CONFIG_ARCH_HAVE_NETDEV_STATISTICS is not set +# CONFIG_NETDEV_LATEINIT is not set + +# +# External Ethernet MAC Device Support +# +# CONFIG_NET_DM90x0 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ENCX24J600 is not set +# CONFIG_NET_E1000 is not set +# CONFIG_NET_SLIP is not set +# CONFIG_NET_FTMAC100 is not set +# CONFIG_NET_VNET is not set + +# +# External Ethernet PHY Device Support +# +# CONFIG_ARCH_PHY_INTERRUPT is not set +# CONFIG_ETH0_PHY_NONE is not set +# CONFIG_ETH0_PHY_AM79C874 is not set +# CONFIG_ETH0_PHY_KS8721 is not set +# CONFIG_ETH0_PHY_KSZ8041 is not set +# CONFIG_ETH0_PHY_KSZ8051 is not set +# CONFIG_ETH0_PHY_KSZ8061 is not set +# CONFIG_ETH0_PHY_KSZ8081 is not set +# CONFIG_ETH0_PHY_KSZ90x1 is not set +# CONFIG_ETH0_PHY_DP83848C is not set +CONFIG_ETH0_PHY_LAN8720=y +# CONFIG_ETH0_PHY_LAN8740 is not set +# CONFIG_ETH0_PHY_LAN8740A is not set +# CONFIG_ETH0_PHY_LAN8742A is not set +# CONFIG_ETH0_PHY_DM9161 is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +CONFIG_USART2_SERIALDRIVER=y +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_SERIAL_NPOLLWAITERS=2 +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +CONFIG_USART2_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# USART2 Configuration +# +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_USART2_BAUD=115200 +CONFIG_USART2_BITS=8 +CONFIG_USART2_PARITY=0 +CONFIG_USART2_2STOP=0 +# CONFIG_USART2_IFLOWCONTROL is not set +# CONFIG_USART2_OFLOWCONTROL is not set +# CONFIG_USART2_DMA is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +CONFIG_ARCH_HAVE_NET=y +CONFIG_ARCH_HAVE_PHY=y +CONFIG_NET=y +# CONFIG_NET_NOINTS is not set +# CONFIG_NET_PROMISCUOUS is not set + +# +# Driver buffer configuration +# +CONFIG_NET_MULTIBUFFER=y +CONFIG_NET_ETH_MTU=590 +CONFIG_NET_ETH_TCP_RECVWNDO=536 +CONFIG_NET_GUARDSIZE=2 + +# +# Data link support +# +# CONFIG_NET_MULTILINK is not set +CONFIG_NET_ETHERNET=y +# CONFIG_NET_LOOPBACK is not set +# CONFIG_NET_TUN is not set + +# +# Network Device Operations +# +# CONFIG_NETDEV_PHY_IOCTL is not set + +# +# Internet Protocol Selection +# +CONFIG_NET_IPv4=y +# CONFIG_NET_IPv6 is not set + +# +# Socket Support +# +CONFIG_NSOCKET_DESCRIPTORS=10 +CONFIG_NET_NACTIVESOCKETS=16 +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_SOLINGER=y + +# +# Raw Socket Support +# +# CONFIG_NET_PKT is not set + +# +# Unix Domain Socket Support +# +# CONFIG_NET_LOCAL is not set + +# +# TCP/IP Networking +# +CONFIG_NET_TCP=y +# CONFIG_NET_TCPURGDATA is not set +CONFIG_NET_TCP_CONNS=40 +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_TCP_READAHEAD=y +# CONFIG_NET_TCP_WRITE_BUFFERS is not set +CONFIG_NET_TCP_RECVDELAY=0 +CONFIG_NET_TCPBACKLOG=y +# CONFIG_NET_TCP_SPLIT is not set +# CONFIG_NET_SENDFILE is not set + +# +# UDP Networking +# +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NET_UDP_CONNS=8 +CONFIG_NET_BROADCAST=y +# CONFIG_NET_RXAVAIL is not set +CONFIG_NET_UDP_READAHEAD=y + +# +# ICMP Networking Support +# +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_PING=y + +# +# IGMPv2 Client Support +# +# CONFIG_NET_IGMP is not set + +# +# ARP Configuration +# +CONFIG_NET_ARP=y +CONFIG_NET_ARPTAB_SIZE=16 +CONFIG_NET_ARP_MAXAGE=120 +CONFIG_NET_ARP_IPIN=y +# CONFIG_NET_ARP_SEND is not set + +# +# Network I/O Buffer Support +# +CONFIG_NET_IOB=y +CONFIG_IOB_NBUFFERS=24 +CONFIG_IOB_BUFSIZE=196 +CONFIG_IOB_NCHAINS=8 +# CONFIG_NET_ARCH_INCR32 is not set +# CONFIG_NET_ARCH_CHKSUM is not set +CONFIG_NET_STATISTICS=y + +# +# Routing Table Configuration +# +# CONFIG_NET_ROUTE is not set +CONFIG_NET_HOSTNAME="" + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_FS_READABLE is not set +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_NFS is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=2 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set +CONFIG_LIBC_NETDB=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSCLIENT_ENTRIES=8 +CONFIG_NETDB_DNSCLIENT_NAMESIZE=32 +CONFIG_NETDB_DNSCLIENT_LIFESEC=3600 +CONFIG_NETDB_DNSCLIENT_MAXRESPONSE=96 +# CONFIG_NETDB_DNSSERVER_NOADDR is not set +CONFIG_NETDB_DNSSERVER_IPv4=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0a000001 + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +# CONFIG_CXX_NEWLONG is not set + +# +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set + +# +# Application Configuration +# + +# +# NxWidgets/NxWM +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_CXXTEST is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_DISCOVER is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NETTEST is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +# CONFIG_EXAMPLES_NSH is not set +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UDPBLASTER is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +CONFIG_EXAMPLES_WEBSERVER=y +CONFIG_EXAMPLES_WEBSERVER_DHCPC=y +CONFIG_EXAMPLES_WEBSERVER_DRIPADDR=0xc0a80101 +CONFIG_EXAMPLES_WEBSERVER_NETMASK=0xffffff00 +CONFIG_EXAMPLES_WEBSERVER_NOMAC=y +# CONFIG_EXAMPLES_WGET is not set +# CONFIG_EXAMPLES_XMLRPC is not set + +# +# External +# + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CHAT is not set +# CONFIG_NETUTILS_CODECS is not set +CONFIG_NETUTILS_DHCPC=y +# CONFIG_NETUTILS_DHCPD is not set +CONFIG_NETUTILS_DISCOVER=y +CONFIG_DISCOVER_STACK_SIZE=1024 +CONFIG_DISCOVER_PRIORITY=50 +CONFIG_DISCOVER_PORT=96 +CONFIG_DISCOVER_INTERFACE="eth0" +CONFIG_DISCOVER_DEVICE_CLASS=0xff +CONFIG_DISCOVER_DESCR="NuttX" +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set +# CONFIG_NETUTILS_JSON is not set +CONFIG_NETUTILS_NETLIB=y +# CONFIG_NETUTILS_NTPCLIENT is not set +# CONFIG_NETUTILS_PPPD is not set +# CONFIG_NETUTILS_SMTP is not set +# CONFIG_NETUTILS_TELNETD is not set +# CONFIG_NETUTILS_TFTPC is not set +# CONFIG_NETUTILS_WEBCLIENT is not set +CONFIG_NETUTILS_WEBSERVER=y +# CONFIG_NETUTILS_HTTPD_SINGLECONNECT is not set +# CONFIG_NETUTILS_HTTPD_SCRIPT_DISABLE is not set +CONFIG_NETUTILS_HTTPD_MAXPATH=64 +# CONFIG_NETUTILS_HTTPD_CGIPATH is not set +CONFIG_NETUTILS_HTTPD_ERRPATH="" +# CONFIG_NETUTILS_HTTPD_SERVERHEADER_DISABLE is not set +CONFIG_NETUTILS_HTTPD_TIMEOUT=0 +CONFIG_NETUTILS_HTTPD_CLASSIC=y +# CONFIG_NETUTILS_HTTPD_MMAP is not set +# CONFIG_NETUTILS_HTTPD_SENDFILE is not set +CONFIG_NETUTILS_HTTPD_KEEPALIVE_DISABLE=y +# CONFIG_NETUTILS_XMLRPC is not set + +# +# NSH Library +# +# CONFIG_NSH_LIBRARY is not set + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_NETDB is not set +# CONFIG_SYSTEM_RAMTEST is not set +# CONFIG_READLINE_HAVE_EXTMATCH is not set +# CONFIG_SYSTEM_READLINE is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/olimex-stm32-e407/webserver/setenv.sh b/configs/olimex-stm32-e407/webserver/setenv.sh new file mode 100755 index 0000000000..3cffa68d40 --- /dev/null +++ b/configs/olimex-stm32-e407/webserver/setenv.sh @@ -0,0 +1,80 @@ +#!/bin/bash +# configs/olimex-stm32-e407/webserver/setenv.sh +# +# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the RIDE +# toolchain under windows. You will also have to edit this if you install +# the RIDE toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Raisonance/Ride/arm-gcc/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +#export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" +# You can this free toolchain here https://launchpad.net/gcc-arm-embedded +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" + +# These are the Cygwin paths to the locations where I installed the Atollic +# toolchain under windows. You will also have to edit this if you install +# the Atollic toolchain in any other location. /usr/bin is added before +# the Atollic bin path because there is are binaries named gcc.exe and g++.exe +# at those locations as well. +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +#export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH variable +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" -- GitLab From 4f4b709ef5a095fb9ba62cbeaba6a0b06d3b0ab1 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 6 Oct 2016 07:08:50 -0600 Subject: [PATCH 029/734] configs/stm32l476-mdk/nsh: Remove CONFIG_CXX_INITIALIZE. up_cxxinitialize is not provided in apps/platfor for this board. --- configs/stm32l476-mdk/nsh/defconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/configs/stm32l476-mdk/nsh/defconfig b/configs/stm32l476-mdk/nsh/defconfig index e1d92b95af..188e704f0b 100644 --- a/configs/stm32l476-mdk/nsh/defconfig +++ b/configs/stm32l476-mdk/nsh/defconfig @@ -770,7 +770,7 @@ CONFIG_ARCH_HAVE_TLS=y # # CONFIG_C99_BOOL8 is not set CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y +# CONFIG_HAVE_CXXINITIALIZE is not set # CONFIG_CXX_NEWLONG is not set # @@ -817,7 +817,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_MOUNT is not set # CONFIG_EXAMPLES_NRF24L01TERM is not set CONFIG_EXAMPLES_NSH=y -CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_NULL is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set @@ -948,6 +947,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1017,6 +1017,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set # CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set -- GitLab From 6a0917ae7f6b301354030e8eb783351ca7eff274 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 6 Oct 2016 07:27:19 -0600 Subject: [PATCH 030/734] Eliminate warnings --- drivers/sensors/xen1210.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/sensors/xen1210.c b/drivers/sensors/xen1210.c index ea4de97fff..0f7bfd2b1e 100644 --- a/drivers/sensors/xen1210.c +++ b/drivers/sensors/xen1210.c @@ -147,8 +147,6 @@ static ssize_t xen1210_read(FAR struct file *filep, FAR char *buffer, { FAR struct inode *inode; FAR struct xen1210_dev_s *priv; - struct xen1210_sample_s sample; - uint32_t regval; int ret; sninfo("len=%d\n", len); @@ -290,7 +288,6 @@ XEN1210_HANDLE xen1210_instantiate(FAR struct spi_dev_s *dev, { FAR struct xen1210_dev_s *priv; uint32_t regval; - int ret; /* Allocate the XEN1210 driver instance */ @@ -445,7 +442,6 @@ void xen1210_getdata(FAR struct xen1210_dev_s *priv) #ifdef CONFIG_XEN1210_REGDEBUG _err("%02x->%02x\n", regaddr, regval); #endif - return regval; } /**************************************************************************** -- GitLab From f55bee5325ee769f1a51ff35d78958d152787c5b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 6 Oct 2016 07:42:13 -0600 Subject: [PATCH 031/734] Update defconfig files --- configs/spark/composite/defconfig | 2 +- configs/spark/nsh/defconfig | 2 +- configs/spark/usbmsc/defconfig | 2 +- configs/spark/usbserial/defconfig | 2 +- configs/stm32_tiny/nsh/defconfig | 2 +- configs/stm32f103-minimum/rfid-rc522/defconfig | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/configs/spark/composite/defconfig b/configs/spark/composite/defconfig index 96c044fab9..490744f429 100644 --- a/configs/spark/composite/defconfig +++ b/configs/spark/composite/defconfig @@ -917,7 +917,7 @@ CONFIG_CC3000_SELECT_STACKSIZE=390 CONFIG_CC3000_UNSOLICED_STACKSIZE=264 # CONFIG_CC3000_PROBES is not set # CONFIG_WL_NRF24L01 is not set -# CONFIG_WL_MFRC522 is not set +# CONFIG_CL_MFRC522 is not set # CONFIG_WL_PN532 is not set # diff --git a/configs/spark/nsh/defconfig b/configs/spark/nsh/defconfig index 93ace169f0..a32b364ed2 100644 --- a/configs/spark/nsh/defconfig +++ b/configs/spark/nsh/defconfig @@ -917,7 +917,7 @@ CONFIG_CC3000_SELECT_STACKSIZE=368 CONFIG_CC3000_UNSOLICED_STACKSIZE=264 # CONFIG_CC3000_PROBES is not set # CONFIG_WL_NRF24L01 is not set -# CONFIG_WL_MFRC522 is not set +# CONFIG_CL_MFRC522 is not set # CONFIG_WL_PN532 is not set # diff --git a/configs/spark/usbmsc/defconfig b/configs/spark/usbmsc/defconfig index 0ab4fcd241..9ac901f2a1 100644 --- a/configs/spark/usbmsc/defconfig +++ b/configs/spark/usbmsc/defconfig @@ -882,7 +882,7 @@ CONFIG_CC3000_SELECT_STACKSIZE=390 CONFIG_CC3000_UNSOLICED_STACKSIZE=264 # CONFIG_CC3000_PROBES is not set # CONFIG_WL_NRF24L01 is not set -# CONFIG_WL_MFRC522 is not set +# CONFIG_CL_MFRC522 is not set # CONFIG_WL_PN532 is not set # diff --git a/configs/spark/usbserial/defconfig b/configs/spark/usbserial/defconfig index a2bee31d24..da3d0c5e5d 100644 --- a/configs/spark/usbserial/defconfig +++ b/configs/spark/usbserial/defconfig @@ -892,7 +892,7 @@ CONFIG_CC3000_SELECT_STACKSIZE=390 CONFIG_CC3000_UNSOLICED_STACKSIZE=264 CONFIG_CC3000_PROBES=y # CONFIG_WL_NRF24L01 is not set -# CONFIG_WL_MFRC522 is not set +# CONFIG_CL_MFRC522 is not set # CONFIG_WL_PN532 is not set # diff --git a/configs/stm32_tiny/nsh/defconfig b/configs/stm32_tiny/nsh/defconfig index c796e5e93d..8b9c4c1d86 100644 --- a/configs/stm32_tiny/nsh/defconfig +++ b/configs/stm32_tiny/nsh/defconfig @@ -795,7 +795,7 @@ CONFIG_WL_NRF24L01_DFLT_ADDR_WIDTH=5 CONFIG_WL_NRF24L01_CHECK_PARAMS=y CONFIG_WL_NRF24L01_RXSUPPORT=y CONFIG_WL_NRF24L01_RXFIFO_LEN=128 -# CONFIG_WL_MFRC522 is not set +# CONFIG_CL_MFRC522 is not set # CONFIG_WL_PN532 is not set # diff --git a/configs/stm32f103-minimum/rfid-rc522/defconfig b/configs/stm32f103-minimum/rfid-rc522/defconfig index 140ef6a66f..6a74dc01de 100644 --- a/configs/stm32f103-minimum/rfid-rc522/defconfig +++ b/configs/stm32f103-minimum/rfid-rc522/defconfig @@ -791,7 +791,7 @@ CONFIG_DRIVERS_WIRELESS=y # CONFIG_WL_CC1101 is not set # CONFIG_WL_CC3000 is not set # CONFIG_WL_NRF24L01 is not set -CONFIG_WL_MFRC522=y +CONFIG_CL_MFRC522=y CONFIG_MFRC522_SPI_FREQ=1000000 CONFIG_MFRC522_DEBUG=y # CONFIG_MFRC522_DEBUG_TX is not set -- GitLab From 1fda0523da7c5728d2afdb099ed99079015d4da9 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 6 Oct 2016 07:44:00 -0600 Subject: [PATCH 032/734] CONFIG_CL_MFR522, not CONFIG_WL_MFR522 --- configs/stm32f103-minimum/src/Makefile | 2 +- configs/stm32f103-minimum/src/stm32_bringup.c | 2 +- configs/stm32f103-minimum/src/stm32_spi.c | 4 ++-- configs/stm32f103-minimum/src/stm32f103_minimum.h | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/configs/stm32f103-minimum/src/Makefile b/configs/stm32f103-minimum/src/Makefile index 5876a6df68..c502b43a47 100644 --- a/configs/stm32f103-minimum/src/Makefile +++ b/configs/stm32f103-minimum/src/Makefile @@ -53,7 +53,7 @@ ifeq ($(CONFIG_AUDIO_TONE),y) CSRCS += stm32_tone.c endif -ifeq ($(CONFIG_WL_MFRC522),y) +ifeq ($(CONFIG_CL_MRFC522),y) CSRCS += stm32_mfrc522.c endif diff --git a/configs/stm32f103-minimum/src/stm32_bringup.c b/configs/stm32f103-minimum/src/stm32_bringup.c index ec7d33db3f..016e7149bd 100644 --- a/configs/stm32f103-minimum/src/stm32_bringup.c +++ b/configs/stm32f103-minimum/src/stm32_bringup.c @@ -112,7 +112,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_WL_MFRC522 +#ifdef CONFIG_CL_MRFC522 ret = stm32_mfrc522initialize("/dev/rfid0"); if (ret < 0) { diff --git a/configs/stm32f103-minimum/src/stm32_spi.c b/configs/stm32f103-minimum/src/stm32_spi.c index 2095e3e2af..10aabe207c 100644 --- a/configs/stm32f103-minimum/src/stm32_spi.c +++ b/configs/stm32f103-minimum/src/stm32_spi.c @@ -74,7 +74,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_WL_MFRC522 +#ifdef CONFIG_CL_MRFC522 (void)stm32_configgpio(GPIO_CS_MFRC522); /* MFRC522 chip select */ #endif @@ -112,7 +112,7 @@ void stm32_spidev_initialize(void) void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { -#if defined(CONFIG_WL_MFRC522) +#if defined(CONFIG_CL_MRFC522) if (devid == SPIDEV_WIRELESS) { stm32_gpiowrite(GPIO_CS_MFRC522, !selected); diff --git a/configs/stm32f103-minimum/src/stm32f103_minimum.h b/configs/stm32f103-minimum/src/stm32f103_minimum.h index f3c083ac6b..68c57ba3a1 100644 --- a/configs/stm32f103-minimum/src/stm32f103_minimum.h +++ b/configs/stm32f103-minimum/src/stm32f103_minimum.h @@ -139,7 +139,7 @@ void stm32_usbinitialize(void); * ************************************************************************************/ -#ifdef CONFIG_WL_MFRC522 +#ifdef CONFIG_CL_MRFC522 int stm32_mfrc522initialize(FAR const char *devpath); #endif -- GitLab From f34d5db09448cf142b9e3f61063c12b2625d5551 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 6 Oct 2016 07:58:14 -0600 Subject: [PATCH 033/734] More fixed related to name changes from CONFIG_WL_MFRC522 to CONFIG_CL_MFRC522. Also depends on CONFIG_CONTACTLESS. not CONFIG_WIRELESS. --- .../stm32f103-minimum/rfid-rc522/defconfig | 19 ++++++++++--------- configs/stm32f103-minimum/src/Makefile | 2 +- configs/stm32f103-minimum/src/stm32_bringup.c | 2 +- configs/stm32f103-minimum/src/stm32_spi.c | 4 ++-- .../stm32f103-minimum/src/stm32f103_minimum.h | 2 +- 5 files changed, 15 insertions(+), 14 deletions(-) diff --git a/configs/stm32f103-minimum/rfid-rc522/defconfig b/configs/stm32f103-minimum/rfid-rc522/defconfig index 6a74dc01de..0f41c12085 100644 --- a/configs/stm32f103-minimum/rfid-rc522/defconfig +++ b/configs/stm32f103-minimum/rfid-rc522/defconfig @@ -697,6 +697,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -787,16 +788,12 @@ CONFIG_USART1_2STOP=0 # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set -CONFIG_DRIVERS_WIRELESS=y -# CONFIG_WL_CC1101 is not set -# CONFIG_WL_CC3000 is not set -# CONFIG_WL_NRF24L01 is not set +# CONFIG_DRIVERS_WIRELESS is not set +CONFIG_DRIVERS_CONTACTLESS=y CONFIG_CL_MFRC522=y CONFIG_MFRC522_SPI_FREQ=1000000 -CONFIG_MFRC522_DEBUG=y -# CONFIG_MFRC522_DEBUG_TX is not set -# CONFIG_MFRC522_DEBUG_RX is not set -# CONFIG_WL_PN532 is not set +# CONFIG_CL_MFRC522_DEBUG is not set +# CONFIG_CL_PN532 is not set # # System Logging @@ -965,10 +962,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_NRF24L01TERM is not set CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set @@ -1019,6 +1016,7 @@ CONFIG_EXAMPLES_RFID_READUID_STACKSIZE=2048 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1090,6 +1088,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1156,6 +1155,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm32f103-minimum/src/Makefile b/configs/stm32f103-minimum/src/Makefile index c502b43a47..746f20edbc 100644 --- a/configs/stm32f103-minimum/src/Makefile +++ b/configs/stm32f103-minimum/src/Makefile @@ -53,7 +53,7 @@ ifeq ($(CONFIG_AUDIO_TONE),y) CSRCS += stm32_tone.c endif -ifeq ($(CONFIG_CL_MRFC522),y) +ifeq ($(CONFIG_CL_MFRC522),y) CSRCS += stm32_mfrc522.c endif diff --git a/configs/stm32f103-minimum/src/stm32_bringup.c b/configs/stm32f103-minimum/src/stm32_bringup.c index 016e7149bd..2843f67e5b 100644 --- a/configs/stm32f103-minimum/src/stm32_bringup.c +++ b/configs/stm32f103-minimum/src/stm32_bringup.c @@ -112,7 +112,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_CL_MRFC522 +#ifdef CONFIG_CL_MFRC522 ret = stm32_mfrc522initialize("/dev/rfid0"); if (ret < 0) { diff --git a/configs/stm32f103-minimum/src/stm32_spi.c b/configs/stm32f103-minimum/src/stm32_spi.c index 10aabe207c..98593be3ca 100644 --- a/configs/stm32f103-minimum/src/stm32_spi.c +++ b/configs/stm32f103-minimum/src/stm32_spi.c @@ -74,7 +74,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_CL_MRFC522 +#ifdef CONFIG_CL_MFRC522 (void)stm32_configgpio(GPIO_CS_MFRC522); /* MFRC522 chip select */ #endif @@ -112,7 +112,7 @@ void stm32_spidev_initialize(void) void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { -#if defined(CONFIG_CL_MRFC522) +#if defined(CONFIG_CL_MFRC522) if (devid == SPIDEV_WIRELESS) { stm32_gpiowrite(GPIO_CS_MFRC522, !selected); diff --git a/configs/stm32f103-minimum/src/stm32f103_minimum.h b/configs/stm32f103-minimum/src/stm32f103_minimum.h index 68c57ba3a1..a52b49b3a0 100644 --- a/configs/stm32f103-minimum/src/stm32f103_minimum.h +++ b/configs/stm32f103-minimum/src/stm32f103_minimum.h @@ -139,7 +139,7 @@ void stm32_usbinitialize(void); * ************************************************************************************/ -#ifdef CONFIG_CL_MRFC522 +#ifdef CONFIG_CL_MFRC522 int stm32_mfrc522initialize(FAR const char *devpath); #endif -- GitLab From d61239e38ff7329d651469df4b24ee876fe86709 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 6 Oct 2016 08:50:52 -0600 Subject: [PATCH 034/734] stm32_modifycr2 should be available on all platforms is DMA is enabled. --- arch/arm/src/stm32/stm32_spi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/stm32/stm32_spi.c b/arch/arm/src/stm32/stm32_spi.c index d82b6eb3cb..c70bf8f6f1 100644 --- a/arch/arm/src/stm32/stm32_spi.c +++ b/arch/arm/src/stm32/stm32_spi.c @@ -1022,7 +1022,8 @@ static void spi_modifycr1(FAR struct stm32_spidev_s *priv, uint16_t setbits, * ************************************************************************************/ -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_SPI_DMA) static void spi_modifycr2(FAR struct stm32_spidev_s *priv, uint16_t setbits, uint16_t clrbits) { -- GitLab From 49ee2631f73891192d6b76ca0ca02f9d5ce91b2b Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Thu, 6 Oct 2016 13:33:31 -0600 Subject: [PATCH 035/734] Enable JTAG in stm32f103-minimum/userled configuration --- configs/stm32f103-minimum/userled/defconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/stm32f103-minimum/userled/defconfig b/configs/stm32f103-minimum/userled/defconfig index 39ef59233b..9cdfdc6380 100644 --- a/configs/stm32f103-minimum/userled/defconfig +++ b/configs/stm32f103-minimum/userled/defconfig @@ -402,9 +402,9 @@ CONFIG_STM32_USART1=y # # CONFIG_STM32_USART1_REMAP is not set # CONFIG_STM32_JTAG_DISABLE is not set -CONFIG_STM32_JTAG_FULL_ENABLE=y +# CONFIG_STM32_JTAG_FULL_ENABLE is not set # CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set -# CONFIG_STM32_JTAG_SW_ENABLE is not set +CONFIG_STM32_JTAG_SW_ENABLE=y CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y # CONFIG_STM32_FORCEPOWER is not set # CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set -- GitLab From 1d3abd17cc011857e542d42185de49b455afc2d8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jens=20Gr=C3=A4f?= Date: Fri, 7 Oct 2016 13:42:24 +0200 Subject: [PATCH 036/734] dma2d: fix an error in up_dma2dcreatelayer where an invalid pointer was returned when a certain underlying function failed. --- arch/arm/src/stm32/stm32_dma2d.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/src/stm32/stm32_dma2d.c b/arch/arm/src/stm32/stm32_dma2d.c index 5e5740e27b..db76245708 100644 --- a/arch/arm/src/stm32/stm32_dma2d.c +++ b/arch/arm/src/stm32/stm32_dma2d.c @@ -2069,6 +2069,7 @@ FAR struct dma2d_layer_s *up_dma2dcreatelayer(fb_coord_t width, /* free the layer struture */ kmm_free(layer); + layer = NULL; lcderr("ERROR: ENOMEM, Unable to allocate layer buffer\n"); errno = ENOMEM; } -- GitLab From a2e4c0e898734ea78a9f22975aeea7eee0e38362 Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Fri, 7 Oct 2016 15:12:34 +0200 Subject: [PATCH 037/734] i2s rcc typo fix --- arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c index aac857b9c3..10e4fe2bb5 100644 --- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c @@ -882,10 +882,10 @@ static void stm32_stdclockconfig(void) | RCC_PLLI2SCFGR_PLLI2SP_MASK | RCC_PLLI2SCFGR_PLLI2SQ_MASK | RCC_PLLI2SCFGR_PLLI2SR_MASK); - regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN - | STM32_RCC_PLLSAICFGR_PLLSAIP - | STM32_RCC_PLLSAICFGR_PLLSAIQ - | STM32_RCC_PLLSAICFGR_PLLSAIR); + regval |= (STM32_RCC_PLLI2SCFGR_PLLI2SN + | STM32_RCC_PLLI2SCFGR_PLLI2SP + | STM32_RCC_PLLI2SCFGR_PLLI2SQ + | STM32_RCC_PLLI2SCFGR_PLLI2SR); putreg32(regval, STM32_RCC_PLLI2SCFGR); regval = getreg32(STM32_RCC_DCKCFGR2); -- GitLab From fd92f01f556fbe5cf24365aa153af104469441e1 Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Fri, 7 Oct 2016 15:12:46 +0200 Subject: [PATCH 038/734] exact values for i2c clock --- arch/arm/src/stm32f7/stm32_i2c.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c index 3786e7d52c..8d5e4db7c0 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.c +++ b/arch/arm/src/stm32f7/stm32_i2c.c @@ -1306,17 +1306,17 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ if (frequency == 100000) { presc = 0; - scl_delay = 3; + scl_delay = 5; sda_delay = 0; - scl_h_period = 30; - scl_l_period = 120; + scl_h_period = 61; + scl_l_period = 89; } else if (frequency == 400000) { presc = 0; scl_delay = 3; - sda_delay = 9; + sda_delay = 0; scl_h_period = 6; scl_l_period = 24; } -- GitLab From 74284aec14ab5824f2a76497fe72aae40cac9b81 Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Fri, 7 Oct 2016 15:13:07 +0200 Subject: [PATCH 039/734] enable i2c clock config --- configs/stm32f746-ws/include/board.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/stm32f746-ws/include/board.h b/configs/stm32f746-ws/include/board.h index 17ca38417e..8cbd85bc92 100644 --- a/configs/stm32f746-ws/include/board.h +++ b/configs/stm32f746-ws/include/board.h @@ -144,7 +144,7 @@ /* Configure factors for PLLI2S clock */ - +#define CONFIG_STM32F7_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) #define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) -- GitLab From bd08646768ab324fd220cdcf59ea7e385089c824 Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Fri, 7 Oct 2016 15:18:20 +0200 Subject: [PATCH 040/734] enable PLLSAI --- configs/stm32f746-ws/include/board.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/stm32f746-ws/include/board.h b/configs/stm32f746-ws/include/board.h index 8cbd85bc92..65a27fc6b7 100644 --- a/configs/stm32f746-ws/include/board.h +++ b/configs/stm32f746-ws/include/board.h @@ -124,7 +124,7 @@ /* Configure factors for PLLSAI clock */ - +#define CONFIG_STM32F7_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2) -- GitLab From 9e3479555db056bb8c2c2f6868d9a6b4e5ae4b5b Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Fri, 7 Oct 2016 15:47:30 +0200 Subject: [PATCH 041/734] usb set value typo --- arch/arm/src/stm32f7/stm32_otgdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/stm32f7/stm32_otgdev.c b/arch/arm/src/stm32f7/stm32_otgdev.c index 54a0232cdf..694cf713a8 100644 --- a/arch/arm/src/stm32f7/stm32_otgdev.c +++ b/arch/arm/src/stm32f7/stm32_otgdev.c @@ -4232,7 +4232,7 @@ static void stm32_epin_disable(FAR struct stm32_ep_s *privep) regval = stm32_getreg(regaddr); regval |= OTG_DIEPINT_EPDISD; - stm32_putreg(OTG_DIEPINT_EPDISD, regaddr); + stm32_putreg(regval, regaddr); /* Flush any data remaining in the TxFIFO */ -- GitLab From 741e100dcfd0b0b99518e99bd182e045837b1a68 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 7 Oct 2016 13:47:02 -0600 Subject: [PATCH 042/734] Eliminate some warnings --- configs/tm4c1294-launchpad/src/tm4c_bringup.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/configs/tm4c1294-launchpad/src/tm4c_bringup.c b/configs/tm4c1294-launchpad/src/tm4c_bringup.c index 1ac0b95e58..35e1f76027 100644 --- a/configs/tm4c1294-launchpad/src/tm4c_bringup.c +++ b/configs/tm4c1294-launchpad/src/tm4c_bringup.c @@ -44,6 +44,7 @@ #include #include +#include #include #include @@ -65,7 +66,7 @@ # define HAVE_PWM #endif -#ifdef CONFIG_TM4C1294_LAUNCHPAD_QEI +#if defined(CONFIG_TIVA_QEI0) || defined(CONFIG_TIVA_QEI1) # define HAVE_QEI #endif @@ -247,6 +248,7 @@ static void tm4c_pwm(void) * ****************************************************************************/ +#ifdef HAVE_QEI static void tm4c_qei_register(int id) { FAR struct qe_lowerhalf_s *dev; @@ -268,6 +270,7 @@ static void tm4c_qei_register(int id) } } } +#endif /**************************************************************************** * Name: tm4c_qei -- GitLab From 6ac51cb70857ff34542085ca3b1a38348ea08256 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 8 Oct 2016 07:38:56 -0600 Subject: [PATCH 043/734] Update ChangeLog --- ChangeLog | 104 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 103 insertions(+), 1 deletion(-) diff --git a/ChangeLog b/ChangeLog index a8f56d1e8e..53e86da467 100755 --- a/ChangeLog +++ b/ChangeLog @@ -12393,7 +12393,7 @@ (2016-07-23). * Freedom-K64F: Add PWM support. From Jordan MacIntyre (2016-07-25). -7.18 2016-xx-xx Gregory Nutt +7.18 2016-10-09 Gregory Nutt * drivers/serial/pty.c, serial.c, usbdev/cdcacm.c, include/nuttx/fs/ioctl.h: Fix FIONWRITE and add FIONSPACE. All implementations of FIONWRITE @@ -12672,3 +12672,105 @@ Vyhovanec (2016-09-02). * MTD: SPI-based driver for Macronix MX25L3233F or MX25L6433F. From Aleksandr Vyhovanec (2016-09-02). + * sched/: The TCB nchildren field should not be incremented when + pthreads are created (2016-09-06). + * sched/: Move fields related to parent/child task relationship out of + TCB into group structure (2016-09-06). + * STM32L4: Add support for USART3-USART5. For STM32L4 parts, the higher + number USART ports supported varies. Add the HAVE_USARTx definitions + to the configuration to allow enabling the higher numbered USART ports. + From Jim Wylder (2016-09-15). + * configs/stm32l476-mdk: Support basic booting and nsh on Motorola MDK. + The Motorola MDK is based off of an earlier version of NuttX. This + only provides a basic NSH shell. From Jim Wylder (2016-09-15). + * STM32 USB: Set USB address to avoid a failed assertion. From Pierre-noel + Bouteville (2016-09-15). + * STM32 L4 and L7 USB: Pierre's assertion-avoidance change should also be + applied to STM32 F7 and L4 (2016-09-15). + * sched/: mq_send() was not setting the errno value on certain failures + to allocate a message (2016-09-15). + * include/nuttx/modem: Move all modem-related IOCTL commands to a common + file to assure that they will be unique (2016-09-16). + * STM32 F4 Discovery: Add support for XEN1210 3D-board. From Alan + Carvalho de Assis (2016-09-17). + * drivers/sensors: Adds support for the Sensixs XEN1210 3D-board. This + sensor is used on NANOSATC-BR2 a Brazillian CUBESAT project. From + Alan Carvalho de Assis (2016-09-16). + * include/analog/dac.h: Make DAC structure packed. From Marc Rechté + (2016-09-20). + * All SAM Ethernet Drivers: Add support so that the drivers can be built + with CONFIG_NET_MULTIBUFFER=y (2016-09-20). + * Tiva Ethernet: Needs support for CONFIG_NET_MULTIBUFFER=y (2016-09-20). + * drivers/net: NET_TUN=y => NET_MULTIBUFFER=y. From Vladimir + Komendantskiy (2016-09-20). + * SAM3/4: Fix GPIO pull-up/down code. Enabling the pull-down resistor + while the pull-up resistor is still enabled is not possible. In this + case, the write of PIO_PPDER for the relevant I/O line is discarded. + Likewise, enabling the pull-up resistor while the pull-down resistor + is still enabled is not possible. In this case, the write of PIO_PUER + for the relevant I/O line is discarded. From Wolfgang Reißnegger + (2016-09-20). + * SAM GPIO: Apply Wolfgang's change for SAM3/4 to SAMA5 and SAMV7 + (2016-09-20). + * Tiva QEI: Add QEI lower-half driver impl. for Tiva series chip. From + Young (2016-09-21). + * STM32, L4, and F7: Remove GPIO_ETH_RMII_TX_CLK. TX_CLK is not present + in RMII. Mateusz Szafoni (2016-09-22). + * sched/: Define 'group' even if HAVE_GROUPID is not set. From Mateusz + Szafoni (2016-09-22). + * sched/: vector table should have dimension NR_IRQS, not NR_IRQS+1. + From Sagitta Li (2016-09-22). + * fs/mount: Corrects a bad assertion noted by Pierre-noel Bouteville. + Also fixes a reference counting problem in an error condition: When + the mountpoint inode is found but is not an appropriate mountpoint, + the reference count on the inode was not being decremented (2016-09-22). + * libnx/nxglib: Fix handling of near-horizontal lines of width 1 in + nxgl_splitline(). Missing handling for degenerate condition caused + width 1 lines such as (0, 0) - (100, 10) to have gaps in the drawing. + From Petteri Aimonen (2016-09-22). + * drivers/net/slip.c: Fix calculations using MSEC_PER_TICK. If + USEC_PER_TICK is less than 1000, then MSEC_PER_TICK will be zero. It + will be inaccurate in any case (2016-09-25). + * Tiva QEI: Add a new ioctl command (set MAXPOS) for tiva QEI. From + Young (2016-09-26). + * LPC43xx Serial: There are some small problems in LPC43xx RS485 mode + configuration. In particular: (1) UART0,2,3 do not have DTR pins + (different from UART1), so, Kconfig needs to be adjusted. (2) + lpc43_uart.c in RS485 mode only configures DIR pin, but doesn't enable + pin output for UART0,2,3. (3) should be option to reverse DIR control + pin output polarity. (4) lpc43xx/chip/lpc43_uart.h doesn't have USART3 + definitions. NOTE: I didn't modified and didn't tested USART1, as it + has different hardware. From Vytautas Lukenskas. From Vytautas + Lukenskas (2016-09-30). + * STM32 Ethernet: Correct typo in conditional logic. From Neil Hancock + (2016-10-01). + * sched/pthread and task: When a pthread is started, there is a small + bit of logic that will run on the thread of execution of the new + pthread. In the case where the new pthread has a lower priority than + the parent thread, then this could cause both the parent thread and + the new pthread to be blocked at the priority of the lower priority + pthread (assuming that CONFIG_PRIORITY_INHERITANCE is not selected). + This change temporarily boosts the priority of the new pthread to at + least the priority of the new pthread to at least the priority of the + parent thread. When that bit of logic has executed on the thread of + execution of the new pthread, it will then drop to the correct + priority (if necessary) before calling into the new pthread's entry + point (2016-10-01). + * configs/stm32f103-minimum: Add stm32_bringup support and userled + example to STM32F103 Minimum board. From Alan Carvalho de Assis + (2016-10-02). + * STM32 L4: Add support for quadrature encoders on STM32L4. Sebastien + Lorquet (2016-10-02). + * configs: Add support for qencoders on various nucleo boards. From + Sebastien Lorquet (2016-10-03). + * STM32 L4 USB Device: Fixed L4 USB Driver by avoiding SETUPDONE and + EPOUT_SETUP. From David Sidrane (2016-10-04). + * configs/olimex-stm32-e407: Add some networking configurations. From + Mateusz Szafoni (2016-10-06). + * STM32 SPI: stm32_modifycr2 should be available on all platforms if DMA + is enabled. (2016-10-06). + * STM32 DMA2D: fix an error in up_dma2dcreatelayer where an invalid + pointer was returned when a certain underlying function failed. From + Jens Gräf (2016-10-07). + +7.19 2016-xx-xx Gregory Nutt -- GitLab From 693f5138697113ff698902ca34f05b23d61672e6 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 8 Oct 2016 10:53:54 -0600 Subject: [PATCH 044/734] Update ReleaseNotes --- ChangeLog | 2 +- ReleaseNotes | 519 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 520 insertions(+), 1 deletion(-) diff --git a/ChangeLog b/ChangeLog index 53e86da467..2ff44a1710 100755 --- a/ChangeLog +++ b/ChangeLog @@ -12393,7 +12393,7 @@ (2016-07-23). * Freedom-K64F: Add PWM support. From Jordan MacIntyre (2016-07-25). -7.18 2016-10-09 Gregory Nutt +7.18 2016-10-08 Gregory Nutt * drivers/serial/pty.c, serial.c, usbdev/cdcacm.c, include/nuttx/fs/ioctl.h: Fix FIONWRITE and add FIONSPACE. All implementations of FIONWRITE diff --git a/ReleaseNotes b/ReleaseNotes index 66e1c712c1..18b20f8b14 100644 --- a/ReleaseNotes +++ b/ReleaseNotes @@ -11775,3 +11775,522 @@ detailed bugfix information): command line argument, or a compiled-in default value from config. However, the default was ignored, leading to confusing error messages. From ziggurat29. + +NuttX-7.18 Release Notes +------------------------ + +The 118th release of NuttX, Version 7.18, was made on October 8, 2016, +and is available for download from the Bitbucket.org website. Note +that release consists of two tarballs: nuttx-7.18.tar.gz and +apps-7.18.tar.gz. These are available from: + + https://bitbucket.org/nuttx/nuttx/downloads + https://bitbucket.org/nuttx/apps/downloads + +Both may be needed (see the top-level nuttx/README.txt file for build +information). + +Additional new features and extended functionality: + + * Core OS: + + - Add standard adjtime() interface and basic timekeeping support. + Normally used with an NTP client to keep system time in + synchronization. From Max Neklyudov. + - Use the oneshot timer with optional entropy to measure CPU load if + so configured. + + * File System and Block and MTD Drivers: + + - Add Fujistu MB85RS256B ramtron support. From Beat Küng. + - SPI-based MTD driver for Macronix MX25L3233F or MX25L6433F. From + Aleksandr Vyhovanec. + + * Graphics/Display Drivers: + + - SH1106 0.96 OLED module support (SSD1306 compatible) + I2C fixes. + From v01d (phreakuencies). + + * Sensor Drivers: + + - Add KXJT9 Accelerometer driver from the Motorola Moto Z MDK. + - Add MFRC522 RFID ISO14443 and Mifare transceiver driver. From Alan + Carvalho de Assis. + - Add driver for the LIS3MDL 3 axis magnetometer. From Alexander + Entinger. + - Add driver for the MLX90393 3 axis magnetometer. From Alexander + Entinger. + - Add driver for the LIS3DSH 3 axis accelerometer. From Alexander + Entinger. + - Add driver for the Bosch BMG160 3 axis gyroscope. From Alexander + Entinger. + - Add support for the Sensixs XEN1210 3D-board. This sensor is used + on NANOSATC-BR2 a Brazillian CUBESAT project. From Alan Carvalho + de Assis. + - Add a new ioctl command (set MAXPOS) for Tiva QEI. From Young. + + * Other Common Device Drivers: + + - I/O Expander: Remove hard-coded PCA9555 fields from ioexpander.h + definitons. Add support for an attach() method that may be used + when any subset of pin interrupts occur. + - I/O Expander Interface: Encode and extend I/O expander options to + include interrupt configuration. + - PCA9555 Driver: Replace the signalling logic with a simple callback + using the new definitons of ioexpander.h. This repartitioning of + functionality is necessary because (1) the I/O expander driver is + the lower-lower part of any driver that uses GPIOs (include the GPIO + driver itself) and should not be interacting directly with the much + higher level application layer. And (2) in order to be compatible + with the GPIO driver (and any arbitrary upper half driver), the + PCA9555 should not directly signal, but should call back into the + upper half. The upper half driver that interacts directly with the + application is the appropriate place to be generating signal. + - Add a skeleton I/O Expander driver (based on the PCA9555 driver). + - Add PCF8574 I/O Expander driver. + - GPIO driver: Add IOCTLs to get the pin type and to unregister a + signal handler. + - Add a GPIO lower-half driver that can be used to register a GPIO + character driver for accessing pins on an I/O expander. + - Add an SPI helper function that encapsulates and manages a sequence + of SPI transfers. + - Add an SPI character driver that will permit access to the SPI bus + for testing purposes. + - Add oneshot timer lower half interface definition. + - Add an upper-half, oneshot timer character driver. + - Add Audio Tone Generator for NuttX. From Alan Carvalho de Assis. + - Add USB host support for composite devices. This feature is not + well tested. + - drivers/ioexpander: Add an (untested) TCA64XX I/O Expander driver + leveraged from Project Ara. + + * Simulation Platform: + + - Add a simulated I/O Expander driver. + - Add simulator-based test support for apps/examples/gpio. + - Add a configuration useful for testing Mini Basic. + - Add a simulated oneshot lowerhalf driver. + + * Atmel SAM3/4 Drivers: + + - SAM4CM: Add option to support oneshot timer without free-running + timer. Add oneshot lower half driver. + + * Atmel SAMA5 Drivers: + + - SAMA5D: Add option to support oneshot timer without free-running + timer. Add oneshot lower half driver. + + * Atmel SAMV7 Drivers: + + - SAMV71/SAME70: Add option to support oneshot timer without + free-running timer. Add oneshot lower half driver. + - Add support for SAMV7 DACC module. From Piotr Mienkowski. + + * NXP Freescale Kinetis Drivers: + + - Add support for I2C and RTC. From v01d (phreakuencies). + + * NXP Freescale Kinetis Boards: + + - Add teensy 3.x I2C support. From v01d (phreakuencies). + + * STMicro STM32: + + - Add IAR-style STM32F1xx vectors. Tested on STM32F103RB and + STM32F107RC. From Aleksandr Vyhovanec. + + * STMicro STM32 Drivers: + + - Add timekeeping support for the STM32 tickless mode. From Max + Neklyudov. + - Add a oneshot, lower-half driver for STM32. + - STM32 L4: Add oneshot lower half driver for STM32 L4. + - STM32 L4: Add support for quadrature encoders on STM32L4. Sebastien + Lorquet. + + * STMicro STM32 Boards: + + - stm32f103-minimum: Add board support to MFRC522 driver. From Alan + Carvalho de Assis. + - Add oneshot board initialization to stm32f103-minimum. From Alan + Carvalho de Assis. + - stm32f103-minimum: Add board configuration to initialize Audio Tone + Generator. From Alan Carvalho de Assis. + - stm32bufferfly2: Add support for the Kamami stm32butterfly2 + development board with optional ETH phy. From Michal Lyszczek. + - stm32f103-minimum: Add board config support to SPI LCD module + JLX12864G-086. From Alan Carvalho de Assis. + - stm32l476-mdk: Support basic booting and nsh on Motorola MDK. The + Motorola MDK is based off of an earlier version of NuttX. + This only provides a basic NSH shell. From Jim Wylder. + - STM32 F4 Discovery: Add support for XEN1210 3D-board. From Alan + Carvalho de Assis. + - stm32f103-minimum: Add stm32_bringup support and userled example to + STM32F103 Minimum board. From Alan Carvalho de Assis. + - Add support for qencoders on various nucleo boards. From Sebastien + Lorquet. + - olimex-stm32-e407: Add some networking configurations. From Mateusz + Szafoni. + + * TI Tiva Drivers: + + - Add tiva PWM lower-half driver implementation. From Young. + - Tiva QEI: Add QEI lower-half driver for Tiva series chip. From + Young. + + * C Library/Header Files: + + - Separate XorShift128 PRNG from /dev/urandom and make it generally + available. + - Add POSIX type sig_atomic_t. From Sebastien Lorquet. + - Add the difftime() function. The function depends on the toolchain- + dependent CONFIG_HAVE_DOUBLE so is not available on tiny platforms. + From Sebastien Lorquet. + - Add support for remove(). From Sebastien Lorquet. + - Add system() to stdlib.h. Actual implementation is in + apps/system/system. + + * Build/Configuration System: + + - Rename arch/sh to arch/renesas. + - Remove contactless drivers from drivers/wireless to drivers + contactless. From Sebastien Lorquet. + - Move all modem-related IOCTL commands to a common file to assure + that they will be unique. + + * Tools: + + - Add sethost.sh. This is a script that you can use to quickly + change the host platform from Linux to Windows/Cygwin. Might save + you a lot of headaches. + + * Applications: apps/nshlib: + + - Add logic to support an NSH-specific system command. + - Add printf command to NSH, e.g., controlling /dev/userleds from + command line: nsh> printf \x01 > /dev/userleds. From Alan Carvalho + de Assis. + + * Platforms: apps/system: + + - Port tee command from NetBSD. + - Add a generic system command. Current implentation cannot use + /bin/sh and spawns the custom NSH system command directly. + + * Platforms: apps/platform: + + - Add C++ support for STM32L476-MDK. + + * Platforms: apps/interpreters: + + - Add a port of Mini Basic, version 1.0, written by Malcom McLean and + released under the Creative Commons Attribution license. + + * Applications: apps/examples: + + - Add a simple test of the GPIO driver. + - Add RFID_READUID sample application. From Alan Carvalho de Assis. + - Add Oneshot timer example. + - Add a simple test of the system command. + +Works-In-Progress: + + * IEEE802.14.5/6LowPAN. Hooks and framework for this effort were + introduced in NuttX-7.15. Work has continued on this effort on + forks from the main repositories, albeit with many interruptions. + The completion of this wireless feature will postponed until at + least NuttX-7.19. + +Bugfixes. Only the most critical bugfixes are listed here (see the +ChangeLog for the complete list of bugfixes and for additional, more +detailed bugfix information): + + * Core OS: + + - Explicitly initialize the group tg_exitsem with sem_init(). The + existing logic worked because the correct initialization value is + all zero, but it is better to initialize the semaphore explicitly. + - The TCB nchildren field should not be incremented when pthreads are + created. + - Move fields related to parent/child task relationship out of TCB + into group structure where they belong. Child is a group, not a + thread. + - mq_send() was not setting the errno value on certain failures to + allocate a message. + - Define 'group' even if HAVE_GROUPID is not set. From Mateusz + Szafoni. + - Vector table should have dimension NR_IRQS, not NR_IRQS+1. From + Sagitta Li. + - pthreads: When a pthread is started, there is a small bit + of logic that will run on the thread of execution of the new + pthread. In the case where the new pthread has a lower + priority than the parent thread, then this could cause both the + parent thread and the new pthread to be blocked at the priority of + the lower priority pthread (assuming that CONFIG_PRIORITY_INHERITANCE + is not selected). This change temporarily boosts the priority of the + new pthread to at least the priority of the new pthread to at least + the priority of the parent thread. When that bit of logic has + executed on the thread of execution of the new pthread, it will then + drop to the correct priority (if necessary) before calling into the + new pthread's entry point. + + * File System/Block Drivers/MTD Drivers: + + - FAT performance improvement. In large files, seeking to a + position from the beginning of the file can be very time consuming. + ftell does lssek(fd, 0, SET_CURR). In that case, that is wasted + time since we are going to seek to the same position. This fix + short-circuits fat_seek() in all cases where we attempt to seek to + current position. Suggested by Nate Weibley. + - MTD: Fixed cloned typos in several FLASH drivers. From Aleksandr + Vyhovanec. + - mount: Corrects a bad assertion noted by Pierre-noel Bouteville. + Also fixes a reference counting problem in an error condition: + When the mountpoint inode is found but is not an appropriate + mountpoint, the reference count on the inode was not being + decremented. + + * Common Drivers: + + - Various serial drivers: Fix FIONWRITE and add FIONSPACE. All + implementations of FIONWRITE were wrong. FIONWRITE should return + the number of bytes waiting in the outgoing send queue, not the free + space. Rather, FIONSPACE should return the free space in the send + queue. + - Add missing prototype for btn_lower_initialize(). + - Make DAC sample structure packed. From Marc Rechté. + + * Networking: + + - TCP: tcp_ipvX_bind() not actually using the port selected with + port==0. Also removes duplicate call to pkt_input(). Issues noted + by Pascal Speck. + - drivers/net: NET_TUN=y => NET_MULTIBUFFER=y. From Vladimir + Komendantskiy. + - slip driver: Fix calculations using MSEC_PER_TICK. If + USEC_PER_TICK is less than 1000, then MSEC_PER_TICK will be + zero. It will be inaccurate in any case. + + * Atmel SAM3/4 Drivers: + + - SAM3/4 GPIO: Enable peripheral clock for GPIO port when GPIO is + configured as input. The value of a GPIO input is only sampled when + the peripheral clock for the port controller the GPIO resides in is + enabled. Therefore we need to enable the clock even when polling a + GPIO. From Wolfgang Reissnegger. + - All SAM Ethernet Drivers: Add support so that the drivers can be + built with CONFIG_NET_MULTIBUFFER=y. + - SAM3/4: Fix GPIO pull-up/down code. Enabling the pull-down resistor + while the pull-up resistor is still enabled is not possible. In this + case, the write of PIO_PPDER for the relevant I/O line is discarded. + Likewise, enabling the pull-up resistor while the pull-down resistor + is still enabled is not possible. In this case, the write of + PIO_PUER for the relevant I/O line is discarded. From Wolfgang + Reißnegger. + + * Atmel SAMV7 Drivers: + + - All SAM Ethernet Drivers: Add support so that the drivers can be + built with CONFIG_NET_MULTIBUFFER=y. + - SAM GPIO: Apply Wolfgang's change for SAM3/4 to SAMA5 and SAMV7. + + * Atmel SAMA5: + + - Add missing oneshot max_delay method. + - All SAM Ethernet Drivers: Add support so that the drivers can be + built with CONFIG_NET_MULTIBUFFER=y. + - SAM GPIO: Apply Wolfgang's change for SAM3/4 to SAMA5 and SAMV7. + + * NXP Freescale LPC43xx Drivers: + + - LPC43xx serial: Fix typos in LPC43 serial driver. Found by Vytautas + Lukenskas. + - LPC43xx Serial: There are some small problems in LPC43xx RS485 mode + configuration. In particular: (1) UART0,2,3 do not have DTR pins + (different from UART1), so, Kconfig needs to be adjusted. (2) + lpc43_uart.c in RS485 mode only configures DIR pin, but doesn't + enable pin output for UART0,2,3. (3) should be option to reverse DIR + control pin output polarity. (4) lpc43xx/chip/lpc43_uart.h doesn't + have USART3 definitions. NOTE: I didn't modified and didn't tested + USART1, as it has different hardware. From Vytautas Lukenskas. + From Vytautas Lukenskas. + + * SiLabs EFM32 Drivers: + + - EFM32 SPI drivers adopted incompatible conventions (See STM32 for + details of the issue). + + * STMicro STM32 Drivers: + + - STM32, STM32 L4, and EFM32 SPI drivers adopted incompatible + conventions somewhere along the line. They set the number of bits + to negative when calling SPI_SETBITS which had the magical side- + effect of setting LSB first order of bit transmission. This is not + only a hokey way to pass control information but is supported by no + other SPI drivers. This change three things: (1) It adds + HWFEAT_LSBFIRST as a new H/W feature. (2) It changes the + implementations of SPI_SETBITS in the STM32 and EFM32 drivers so + that negated bit numbers are simply errors and it adds the + SPI_HWFEATURES method that can set the LSB bit order, and + (3) It changes all calls with negative number of bits from all + drivers: The number of bits is now always positive and + SPI_HWFEATURES is called with HWFEAT_LSBFIRST to set the bit order. + - Add missing SPI2 and SPI3 support for STM32F3F3. Add STM32F37XX DMA + channel configuration. For STM32F37XX, SYSCFG_EXTICR_PORTE defined + twice. From Alan Carvalho de Assis. + - STM32: Make stm32_pwr_enablebkp thread safe. From Max Neklyudov. + - Fix bad pllmul values for STM32F1XX connectivity line. STM32F1XX + connectivity line supports only x4, x5, x6, x7, x8, x9 and x6.5 + values. From Michal Lyszczek. + - STM32F3 SPI: Fix the number of bit setting for the F3. That and + data packing work differently on the STM32F3 than for other STM32 + parts. + - STM32 and STM32 L4: Enabling SPI DMA loses other bits in CR2. + - STM32F3 SPI: Cannot write always 16-bit value to DR register + because of how the F3 implements data packing. + - STM32F411 and STM32F446 map i2c2_sda_4 to different alternate + function numbers. From Konstantin Berezenko. + - STM32 DMA Fix: Change stm32 adc dma callback to send channel + number instead of index. From Konstantin Berezenko. + - STM32 OTGFS device: Fix for lost first word from FIFO + + 1) Do not overwrite Reserved Bits in GINTSTS (per ref manual)* + 2) Acknowledge all pending int on entry to ISR that are Only rc_w1* + 3) Do not disable RXFVL* + 4) Loop until RXFVL is cleared* + 5) Only clear the NAK on the endpoint on the OTGFS_GRXSTSD_PKTSTS_SETUPDONE to not loose the first WORD of FIFO all the data (Bug Fix) + + Changed marked *are just driver clean up and ensure ints are not lost. The bug fix is #5 + + Test case open putty and observer the Set/Get LineCoding. Without this fix #5 the Get will not match the Set, and in fact the data might be skewed by 4 bytes, that are lost from the FIFO if the OTGFS_DOEPCTL0_CNAK bit is set in the OTGFS_GRXSTSD_PKTSTS_SETUPRECVD as opposed to the OTGFS_GRXSTSD_PKTSTS_SETUPDONE + + Set Line Coding DATA1: 4B | 00 c2 01 00 00 00 08 | c8 1B + Get Line Coding DATA1: 4B | .. .. .. .. 00 00 08 c8 .. 00 00 07 | 7a 72 + + From David Sidrane. + - STM32 L4 OTGFS device: Apply stm32 fix to stm32l4. From Sebastien + Lorquet. + - STM32 F7: Remove duplicate call to pkt_input from Ethernet driver. + Issues noted by Pascal Speck. + - STM32 L4: Add support for USART3-USART5. For STM32L4 parts, the + higher number USART ports supported varies. Add the HAVE_USARTx + definitions to the configuration to allow enabling the higher + numbered USART ports. From Jim Wylder. + - STM32 USB: Set USB address to avoid a failed assertion. From + Pierre-noel Bouteville. + - STM32 L4 and L7 USB: Pierre's assertion-avoidance change should + also be applied to STM32 F7 and L4. + - STM32, L4, and F7: Remove GPIO_ETH_RMII_TX_CLK. TX_CLK is not + present in RMII. Mateusz Szafoni. + - STM32 Ethernet: Correct typo in conditional logic. From Neil + Hancock. + - STM32 L4 USB Device: Fixed L4 USB Driver by avoiding SETUPDONE and + EPOUT_SETUP. From David Sidrane. + - STM32 SPI: stm32_modifycr2 should be available on all platforms if + DMA is enabled. + - STM32 DMA2D: fix an error in up_dma2dcreatelayer where an invalid + pointer was returned when a certain underlying function failed. + From Jens Gräf. + + * TI Tiva Drivers: + + - Fix two bugs of tiva pwm lower-half driver implementation. From + Young. + - Tiva Ethernet: Needs support for CONFIG_NET_MULTIBUFFER=y. + + * C Library/Header Files: + + - lib_dumpbuffer() now prints a large on-stack buffer first to avoid + problems when the syslog output is prefixed with time. From + Pierre-noel Bouteville. + - libc/math: This fixes the following libc/math issues: (1) asin[f l]() + use Newton’s method to converge on a solution. But Newton’s method + converges very slowly (> 500,000 iterations) for values of x close to + 1.0; and, in the case of asinl(), sometimes fails to converge (loops + forever). The attached patch uses an trig identity for values of + x > sqrt(2). The resultant functions converge in no more than 5 + iterations, 6 for asinl(). (2) The NuttX erf[f l]() functions are + based on Chebyshev fitting to a good guess. The problem there’s a + bug in the implementation that causes the functions to blow up with + x near -3.0. This patch fixes that problem. It should be noted that + this method returns the error function erf(x) with fractional error + less than 1.2E-07 and that’s fine for the float version erff(), but + the same method is used for double and long double version which + will yield only slightly better precision. This patch doesn't + address the issue of lower precision for erf() and erfl(). (3) a + faster version of copysignf() for floats is included. From David S. + Alessio. + - strtod() was not returning endptr on error conditions. + - libc/math: floor(), floorf(), and floorl(): Fix logic error. Was + not correctly handling negative integral value. + - isatty() should be prototyped in unstid.h, not termios.h. From + Sebastien Lorquet. + - nxglib: Fix handling of near-horizontal lines of width 1 in + nxgl_splitline(). Missing handling for degenerate condition caused + width 1 lines such as (0, 0) - (100, 10) to have gaps in the + drawing. From Petteri Aimonen. + + * Build/Configuration System: + + - Top-Level Makefiles: Fix a chicken-and-egg problem. In the menuconfig + target, the context dependency was executed before kconfig-mconf. That + was necessary because the link at apps/platform/board needed to be set + up before creating the apps/Kconfig file. Otherwise, the platform + Kconfig files would not be included. But this introduces the chicken- + and-egg problem in some configurations. In particular: (1) An NX + graphics configuration is used that requires auto-generation of + source files using cpp, (2) the configuration is set for Linux, but + (3) we are running under Cygwin with (4) a Windows native toolchain. + In this case, POSIX-style symbolic links are set up but the Windows + native toolchain cannot follow them. The reason we are running + 'make menuconfig' is to change from Linux to Cygwin, but the target + fails. During the context phase, NX runs CPP to generate source files + but that fails because the Windows native toolchain cannot follow + the links. Checkmate. This was fixed by changing all of the make + menuconfig (and related) targets. They no longer depend on context + being run. Instead, they depend only on the dirlinks target. The + dirlinks target only sets up the directory links but does not try + to run all of the context setup; the compiler is never invoked; no + code is autogenerated and things work. + - CXXFLAGS: add -fcheck-new whenever -fno-exceptions is used. From + Beat Küng. + + * Tools + + - tools/refresh.sh: Recent complexities added to apps/ means that + configuration needs the correct Make.defs file in place in order to + configure properly. + - tools/kconfig2html.c: Update to handle absolute paths when sourcing + Kconfig files. + - tools/mkfsdata.pl was still generating the old-style apps/include + inclusion paths. + + * Application Build/Configuration System: + + - Add DIRLINK and DIRUNLINK tool definitions to apps/Make.defs. + + * apps/nshlib: + + - Fix FIFO_SIZE vs PIPE_SIZE. + - Fix hex representation of IP address in Kconfig. Noted by Michal + Lyszczek. + - nsh_syscmds.c: missing semicolon. From Mateusz Szafoni. + - In system command, don't try to flush output streams if stdio + buffered I/O is not supported. + + * apps/canutils: + + - libuavcan: Under certain circumstances, DELIM is not be defined in + Makefile. + - Add definition for APPNAME in apps/canutils/canlib. From Sebastien + Lorquet. + + * apps/gpsutils: + + - Fix an error minmea. From Aleksandr Vyhovanec. + + * apps/examples: + + - apps/examples/oneshot: If the requested delay is > max_delay, then + break the delay up into several pieces. -- GitLab From 0fa7c62bf4a5e168513ba04434cc4d075b71f45e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 8 Oct 2016 11:47:19 -0600 Subject: [PATCH 045/734] Update NuttX.html for 7.18 release --- Documentation/NuttX.html | 60 +++++++++++++++++++++++++++++++++------- 1 file changed, 50 insertions(+), 10 deletions(-) diff --git a/Documentation/NuttX.html b/Documentation/NuttX.html index 4d6823305e..c77315e797 100644 --- a/Documentation/NuttX.html +++ b/Documentation/NuttX.html @@ -8,7 +8,7 @@

NuttX RTOS

-

Last Updated: September 30, 2016

+

Last Updated: October 8, 2016

@@ -1339,11 +1339,11 @@

Released Versions

In addition to the ever-changing GIT repository, there are frozen released versions of NuttX available. - The current release is NuttX 7.17. - NuttX 7.17 is the 117th release of NuttX. - It was released on June 1, 2016, and is available for download from the + The current release is NuttX 7.18. + NuttX 7.18 is the 118th release of NuttX. + It was released on October 8, 2016, and is available for download from the Bitbucket.org website. - Note that the release consists of two tarballs: nuttx-7.17.tar.gz and apps-7.17.tar.gz. + Note that the release consists of two tarballs: nuttx-7.18.tar.gz and apps-7.18.tar.gz. Both may be needed (see the top-level nuttx/README.txt file for build information).

@@ -1352,7 +1352,7 @@
  • nuttx.

      - Release notes for NuttX 7.17 are available here. + Release notes for NuttX 7.18 are available here. Release notes for all released versions on NuttX are available in the Bitbucket GIT. The ChangeLog for all releases of NuttX is available in the ChangeLog file that can viewed in the Bitbucket GIT. The ChangeLog for the current release is at the bottom of that file. @@ -1360,7 +1360,7 @@

  • apps.

      - Release notes for NuttX 7.17 are available here. + Release notes for NuttX 7.18 are available here. Release notes for all released versions on NuttX are available in the Bitbucket GIT The ChangeLog for the all releases of apps/ is available in the ChangeLog file that can viewed in the Bitbucket GIT. The ChangeLog for the current release is at the bottom of that file. @@ -2926,6 +2926,7 @@ nsh>

    • The other port is for a generic minimual STM32F103CBT6 "blue" board contributed by Alan Carvalho de Assis. + Alan added support for numerous sensors, tone generators, user LEDs, and LCD support in NuttX 7.18.

    @@ -3099,7 +3100,7 @@ nsh>

    STMicro STM32F107x (STM32 F1 "Connectivity Line" family). - Chip support for the STM32 F1 "Connectivity Line" family has been present in NuttX for some time and users have reported that they have successful brought up NuttX on there proprietary boards using this logic. + Chip support for the STM32 F1 "Connectivity Line" family has been present in NuttX for some time and users have reported that they have successful brought up NuttX on theor proprietary boards using this logic.

    • @@ -3153,7 +3154,17 @@ nsh> STATUS: Networking and touchscreen support are well test. But, at present, neither USB nor LCD functionality have been verified. - Refer to the SViewtool STM32F103/F107 README file for further information. + Refer to the Viewtool STM32F103/F107 README file for further information. +

      +
      • +
    • +

      + Kamami STM32 Butterfly 2 + Support for the Kamami STM32 Butterfly 2 was contributed by MichaÅ‚ Åyszczek in NuttX-7/18. That port features the STMicro STM32F107VC MCU. +

      +

      + STATUS: + A configuration for the NuttShell (NSH), NSH with networking, and NSH with USB host are available and verified.

      • @@ -3803,6 +3814,7 @@ nsh>

      Olimex STM32 E407. Support for the Olimex STM32 E407 development board was contributed by Mateusz Szafoni and appeared in NuttX-7.17. + Networking configurations were added in NuttX-7.18. See the NuttX board README file for further information about the NuttX port.

      @@ -3904,7 +3916,7 @@ nsh>

      STMicro STM32 L476. - Two boards are supported in this family: + Three boards are supported in this family:

      • @@ -3919,6 +3931,14 @@ nsh> Board support for the STMicro STM32L476VG Discovery board from ST Micro was contributed by Dave in NuttX-7.15. See the STMicro website and the board README file for further information.

        • +
      • +

        + STM32L476 MDK. + Very basic support for NuttX on the Motorola Moto Z MDK was contributed by Jim Wylder in NuttX 7.18. + A simple NSH configuration is available for the STM32L476 chip. + See the Moto Mods Development Kit and the board README file for further information. +

        +

      Status:

        @@ -3942,6 +3962,22 @@ nsh>
      • CAN contributed by Sebastien Lorquet.
      • I2C made functional by Dave (ziggurat29).
      +

      + NuttX-7.17. + Additional drivers/features were contributed: +

      +
        +
      • Support for tickless mode.
        • +
      • CAN driver enhancements.
        • +
      +

      + NuttX-7.18. + Additional drivers were contributed: +

      +
        +
      • Oneshot timer driver.
        • +
      • Quadrature encode contributed by Sebastien Lorquet.
        • +
      @@ -4154,6 +4190,7 @@ nsh>
    • Support for the EK-TM4C1294XL was contributed by Frank Sautter and was released in NuttX 7.9. This basic board support included a configuration for the NuttShell NSH) and a configuration for testing IPv6. + See drivers for the TI Tiva TM4C129X.

    @@ -4189,6 +4226,9 @@ nsh> Both are networked enabled: One configured to support IPv4 and one configured to supported IPv6. Instructions are included in the board README file for configuring both IPv4 and IPv6 simultaneously..
    • +
  • + Tiva PWM and Quadrature Encoder drivers were contributed to NuttX in 7.18 by Young. +

Refer to the DK-TM4C129X board README file for more detailed information about this port. -- GitLab From e568b08b047652aac71e03e83769c4898d6a8f2d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 9 Oct 2016 09:36:03 -0600 Subject: [PATCH 046/734] Update TODO list --- TODO | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 57 insertions(+), 4 deletions(-) diff --git a/TODO b/TODO index 5372b0aec5..3c187e017e 100644 --- a/TODO +++ b/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated July 20, 2016) +NuttX TODO List (Last updated October 9, 2016) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with @@ -11,18 +11,19 @@ nuttx/: (13) Task/Scheduler (sched/) (1) Memory Management (mm/) + (1) Power Management (drivers/pm) (3) Signals (sched/signal, arch/) (2) pthreads (sched/pthread) (0) Message Queues (sched/mqueue) (9) Kernel/Protected Build (3) C++ Support (6) Binary loaders (binfmt/) - (11) Network (net/, drivers/net) + (12) Network (net/, drivers/net) (4) USB (drivers/usbdev, drivers/usbhost) (0) Other drivers (drivers/) (11) Libraries (libc/, libm/) (11) File system/Generic drivers (fs/, drivers/) - (8) Graphics subsystem (graphics/) + (9) Graphics Subsystem (graphics/) (2) Build system / Toolchains (3) Linux/Cywgin simulation (arch/sim) (4) ARM (arch/arm/) @@ -323,6 +324,34 @@ o Memory Management (mm/) Priority: Medium/Low, a good feature to prevent memory leaks but would have negative impact on memory usage and code size. +o Power Management (drivers/pm) + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + Title: PM CALLBACKS AREN'T BASED ON DOMAIN + Description: Recently support for different power domains was added. Prior + to this, only a single domain (the "IDLE" domain was supported). + Having multiple power domains extends the basic concept to + support power management for different functionality. For + example, a UI may be managed separately from, say, some network + functionality. + + One thing that was missed when the PM domains was added was + support for domain-specific driver callbacks: Currently, all + callbacks will be invoked for all PM domain events making it + impossible to distinguish the domain in the driver. + + Possibilities: + - Add a domain value to the PM registration function. In this + case, callbacks would be retained separately for each domain + and those callbacks would be invoked only for domain-specific + events. + - Add a domain value to the PM callback functions. In this case, + each driver would receive events from all domains and could + respond different (or ignore) events from other domains. + Status: Open + Priority: Currently low because I know of no use of the multiple PM + domains. But, obviously, this would become important if the + features were used. o Signals (sched/signal, arch/) ^^^^^^^^^^^^^^^^^^^^^^^ @@ -1032,6 +1061,15 @@ o Network (net/, drivers/net) Status: Open Priority: Low + Title: REMOVE CONFIG_NET_MULTIBUFFER + Description: The CONFIG_NET_MULTIBUFFER controls some details in the layout + of the network device structure. This is really a unnecessary + complexity and should be removed. The cost for those network + drivers that currently do not support CONFIG_NET_MULTIBUFFER + is the size of one pointer. + Status: Open + Priority: Low + o USB (drivers/usbdev, drivers/usbhost) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1501,7 +1539,7 @@ o File system / Generic drivers (fs/, drivers/) ignored by readder() logic. This the file does not appear in the 'ls'. -o Graphics subsystem (graphics/) +o Graphics Subsystem (graphics/) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ See also the NxWidgets TODO list file for related issues. @@ -1621,6 +1659,21 @@ o Build system Priority: Low, since I am not aware of anyone using the Windows Native build. But, of course, very high if you want to use it. + Title: REMOVE SINGLE USER MODE + Description: The graphics sub-system can operate in either a single-user mode or + in a multi-user mode. In the multiple-user mode, a kernel thread + is used to support a graphics server. Multiple applications may then + communicate with the server using a message queue. This users only + standard POSIX interfaces and works in all build modes (FLAT, + PROTECTED, and KERNEL builds). + + The single-user mode, on the hand, uses inappropriate calls directly + into the OS. This violates the POSIX interface and must, eventually, + be eliminated. These inappropriate calls can only be supported in + the FLAT build mode. + Status: Open + Priority: Medium-High + o Other drivers (drivers/) ^^^^^^^^^^^^^^^^^^^^^^^^ -- GitLab From 79c9e25a123d33b211c01b43ea64895426ebd200 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 9 Oct 2016 14:07:19 -0600 Subject: [PATCH 047/734] include/nuttx/fs/nxffs.h: Needs forward reference to struct mtd_dev_s and needs to include stdbool.h --- include/nuttx/fs/nxffs.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/nuttx/fs/nxffs.h b/include/nuttx/fs/nxffs.h index edbaf190aa..53bec45cf5 100644 --- a/include/nuttx/fs/nxffs.h +++ b/include/nuttx/fs/nxffs.h @@ -41,6 +41,9 @@ ****************************************************************************/ #include + +#include + #include /**************************************************************************** @@ -134,6 +137,7 @@ extern "C" * ****************************************************************************/ +struct mtd_dev_s; int nxffs_initialize(FAR struct mtd_dev_s *mtd); /**************************************************************************** @@ -154,6 +158,7 @@ int nxffs_initialize(FAR struct mtd_dev_s *mtd); * ****************************************************************************/ +struct mtd_dev_s; int nxffs_dump(FAR struct mtd_dev_s *mtd, bool verbose); #undef EXTERN -- GitLab From 4703a231716be13eb4ab103040a26ce0d25442c1 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Mon, 10 Oct 2016 15:56:02 +0000 Subject: [PATCH 048/734] kinetis.h edited online with Bitbucket --- arch/arm/src/kinetis/kinetis.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/kinetis/kinetis.h b/arch/arm/src/kinetis/kinetis.h index bb02f01e92..621b21a75c 100644 --- a/arch/arm/src/kinetis/kinetis.h +++ b/arch/arm/src/kinetis/kinetis.h @@ -143,8 +143,8 @@ #define PIN_ALT2_OUTPUT (_PIN_MODE_ALT2 | _PIN_OUTPUT) #define PIN_ALT2_FAST (_PIN_MODE_ALT2 | _PIN_OUTPUT_FAST) #define PIN_ALT2_SLOW (_PIN_MODE_ALT2 | _PIN_OUTPUT_SLOW) -#define PIN_ALT2_OPENDRAIN (_PIN_MODE_ALT2 | _PIN_OUTPUT_LOWDRIVE) -#define PIN_ALT2_LOWDRIVE (_PIN_MODE_ALT2 | _PIN_OUTPUT_OPENDRAIN) +#define PIN_ALT2_OPENDRAIN (_PIN_MODE_ALT2 | _PIN_OUTPUT_OPENDRAIN) +#define PIN_ALT2_LOWDRIVE (_PIN_MODE_ALT2 | _PIN_OUTPUT_LOWDRIVE) #define PIN_ALT2_HIGHDRIVE (_PIN_MODE_ALT2 | _PIN_OUTPUT_HIGHDRIVE) #define PIN_ALT3 _PIN_MODE_ALT3 -- GitLab From 0476c4374806c68c3f876acc15f335697ee62bc4 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Mon, 10 Oct 2016 15:58:21 +0000 Subject: [PATCH 049/734] kinetis.h edited online with Bitbucket --- arch/arm/src/kinetis/kinetis.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/kinetis/kinetis.h b/arch/arm/src/kinetis/kinetis.h index bb02f01e92..c10abd9976 100644 --- a/arch/arm/src/kinetis/kinetis.h +++ b/arch/arm/src/kinetis/kinetis.h @@ -652,7 +652,7 @@ int kinetis_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cm * ****************************************************************************/ -#if defined(CONFIG_KINETIS_SPI0) || defined(CONFIG_KINETIS_SPI0) || defined(CONFIG_KINETIS_SPI2) +#if defined(CONFIG_KINETIS_SPI0) || defined(CONFIG_KINETIS_SPI1) || defined(CONFIG_KINETIS_SPI2) struct spi_dev_s; void spi_flush(FAR struct spi_dev_s *dev); #endif -- GitLab From df313581dbef0a22ba04ade1cde4298599ecde62 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Tue, 11 Oct 2016 13:00:43 -0600 Subject: [PATCH 050/734] Correct typo in comments --- include/nuttx/input/buttons.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/nuttx/input/buttons.h b/include/nuttx/input/buttons.h index 901480bc8e..3012ba9857 100644 --- a/include/nuttx/input/buttons.h +++ b/include/nuttx/input/buttons.h @@ -69,7 +69,7 @@ * Description: Specify the set of button events that can cause a poll() * to awaken. The default is all button depressions and all * button releases (all supported buttons); - * Argument: A read-only pointer to an instance of struct ajoy_pollevents_s + * Argument: A read-only pointer to an instance of struct btn_pollevents_s * Return: Zero (OK) on success. Minus one will be returned on failure * with the errno value set appropriately. */ -- GitLab From 4825a8fc3fd8cb957c8735009a1daa902ef01a0d Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Tue, 11 Oct 2016 14:03:10 -0600 Subject: [PATCH 051/734] STM32 Minimum: Note in Kconfig that the board supports buttons --- configs/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/Kconfig b/configs/Kconfig index b4552dd05b..ca3b408285 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -959,6 +959,8 @@ config ARCH_BOARD_STM32F103_MINIMUM bool "STM32F103C8T6 Minimum ARM Development Board" depends on ARCH_CHIP_STM32F103C8 select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS ---help--- A configuration for the STM32F103 Minimum board. -- GitLab From 91fa8ffaea7e2ae176d6a96031c1c912867da500 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Tue, 11 Oct 2016 14:14:06 -0600 Subject: [PATCH 052/734] STM32F103 Minimum: Add button supprt --- configs/stm32f103-minimum/buttons/Make.defs | 113 ++ configs/stm32f103-minimum/buttons/defconfig | 1160 +++++++++++++++++ configs/stm32f103-minimum/buttons/setenv.sh | 100 ++ configs/stm32f103-minimum/include/board.h | 9 + configs/stm32f103-minimum/src/Makefile | 4 + configs/stm32f103-minimum/src/stm32_bringup.c | 14 + configs/stm32f103-minimum/src/stm32_buttons.c | 171 +++ .../stm32f103-minimum/src/stm32f103_minimum.h | 12 + 8 files changed, 1583 insertions(+) create mode 100644 configs/stm32f103-minimum/buttons/Make.defs create mode 100644 configs/stm32f103-minimum/buttons/defconfig create mode 100644 configs/stm32f103-minimum/buttons/setenv.sh create mode 100644 configs/stm32f103-minimum/src/stm32_buttons.c diff --git a/configs/stm32f103-minimum/buttons/Make.defs b/configs/stm32f103-minimum/buttons/Make.defs new file mode 100644 index 0000000000..d7974b005f --- /dev/null +++ b/configs/stm32f103-minimum/buttons/Make.defs @@ -0,0 +1,113 @@ +############################################################################ +# configs/stm32f103-minimum/userled/Make.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/stm32f103-minimum/buttons/defconfig b/configs/stm32f103-minimum/buttons/defconfig new file mode 100644 index 0000000000..b9acf84dce --- /dev/null +++ b/configs/stm32f103-minimum/buttons/defconfig @@ -0,0 +1,1160 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_DEFAULT_SMALL=y +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +CONFIG_ARCH_HAVE_HEAPCHECK=y +# CONFIG_HEAP_COLORATION is not set +# CONFIG_DEBUG_SYMBOLS is not set +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +CONFIG_ARCH_CHIP_STM32=y +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +CONFIG_ARCH_CORTEXM3=y +# CONFIG_ARCH_CORTEXM4 is not set +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="stm32" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARMV7M_LAZYFPU is not set +# CONFIG_ARCH_HAVE_FPU is not set +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y +CONFIG_ARMV7M_HAVE_STACKCHECK=y +# CONFIG_ARMV7M_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set +CONFIG_SERIAL_TERMIOS=y + +# +# STM32 Configuration Options +# +# CONFIG_ARCH_CHIP_STM32L151C6 is not set +# CONFIG_ARCH_CHIP_STM32L151C8 is not set +# CONFIG_ARCH_CHIP_STM32L151CB is not set +# CONFIG_ARCH_CHIP_STM32L151R6 is not set +# CONFIG_ARCH_CHIP_STM32L151R8 is not set +# CONFIG_ARCH_CHIP_STM32L151RB is not set +# CONFIG_ARCH_CHIP_STM32L151V6 is not set +# CONFIG_ARCH_CHIP_STM32L151V8 is not set +# CONFIG_ARCH_CHIP_STM32L151VB is not set +# CONFIG_ARCH_CHIP_STM32L152C6 is not set +# CONFIG_ARCH_CHIP_STM32L152C8 is not set +# CONFIG_ARCH_CHIP_STM32L152CB is not set +# CONFIG_ARCH_CHIP_STM32L152R6 is not set +# CONFIG_ARCH_CHIP_STM32L152R8 is not set +# CONFIG_ARCH_CHIP_STM32L152RB is not set +# CONFIG_ARCH_CHIP_STM32L152V6 is not set +# CONFIG_ARCH_CHIP_STM32L152V8 is not set +# CONFIG_ARCH_CHIP_STM32L152VB is not set +# CONFIG_ARCH_CHIP_STM32L162ZD is not set +# CONFIG_ARCH_CHIP_STM32L162VE is not set +# CONFIG_ARCH_CHIP_STM32F100C8 is not set +# CONFIG_ARCH_CHIP_STM32F100CB is not set +# CONFIG_ARCH_CHIP_STM32F100R8 is not set +# CONFIG_ARCH_CHIP_STM32F100RB is not set +# CONFIG_ARCH_CHIP_STM32F100RC is not set +# CONFIG_ARCH_CHIP_STM32F100RD is not set +# CONFIG_ARCH_CHIP_STM32F100RE is not set +# CONFIG_ARCH_CHIP_STM32F100V8 is not set +# CONFIG_ARCH_CHIP_STM32F100VB is not set +# CONFIG_ARCH_CHIP_STM32F100VC is not set +# CONFIG_ARCH_CHIP_STM32F100VD is not set +# CONFIG_ARCH_CHIP_STM32F100VE is not set +# CONFIG_ARCH_CHIP_STM32F102CB is not set +# CONFIG_ARCH_CHIP_STM32F103T8 is not set +# CONFIG_ARCH_CHIP_STM32F103TB is not set +# CONFIG_ARCH_CHIP_STM32F103C4 is not set +CONFIG_ARCH_CHIP_STM32F103C8=y +# CONFIG_ARCH_CHIP_STM32F103CB is not set +# CONFIG_ARCH_CHIP_STM32F103R8 is not set +# CONFIG_ARCH_CHIP_STM32F103RB is not set +# CONFIG_ARCH_CHIP_STM32F103RC is not set +# CONFIG_ARCH_CHIP_STM32F103RD is not set +# CONFIG_ARCH_CHIP_STM32F103RE is not set +# CONFIG_ARCH_CHIP_STM32F103RG is not set +# CONFIG_ARCH_CHIP_STM32F103V8 is not set +# CONFIG_ARCH_CHIP_STM32F103VB is not set +# CONFIG_ARCH_CHIP_STM32F103VC is not set +# CONFIG_ARCH_CHIP_STM32F103VE is not set +# CONFIG_ARCH_CHIP_STM32F103ZE is not set +# CONFIG_ARCH_CHIP_STM32F105VB is not set +# CONFIG_ARCH_CHIP_STM32F105RB is not set +# CONFIG_ARCH_CHIP_STM32F107VC is not set +# CONFIG_ARCH_CHIP_STM32F205RG is not set +# CONFIG_ARCH_CHIP_STM32F207IG is not set +# CONFIG_ARCH_CHIP_STM32F207ZE is not set +# CONFIG_ARCH_CHIP_STM32F302K6 is not set +# CONFIG_ARCH_CHIP_STM32F302K8 is not set +# CONFIG_ARCH_CHIP_STM32F302CB is not set +# CONFIG_ARCH_CHIP_STM32F302CC is not set +# CONFIG_ARCH_CHIP_STM32F302RB is not set +# CONFIG_ARCH_CHIP_STM32F302RC is not set +# CONFIG_ARCH_CHIP_STM32F302VB is not set +# CONFIG_ARCH_CHIP_STM32F302VC is not set +# CONFIG_ARCH_CHIP_STM32F303K6 is not set +# CONFIG_ARCH_CHIP_STM32F303K8 is not set +# CONFIG_ARCH_CHIP_STM32F303C6 is not set +# CONFIG_ARCH_CHIP_STM32F303C8 is not set +# CONFIG_ARCH_CHIP_STM32F303CB is not set +# CONFIG_ARCH_CHIP_STM32F303CC is not set +# CONFIG_ARCH_CHIP_STM32F303RB is not set +# CONFIG_ARCH_CHIP_STM32F303RC is not set +# CONFIG_ARCH_CHIP_STM32F303RD is not set +# CONFIG_ARCH_CHIP_STM32F303RE is not set +# CONFIG_ARCH_CHIP_STM32F303VB is not set +# CONFIG_ARCH_CHIP_STM32F303VC is not set +# CONFIG_ARCH_CHIP_STM32F372C8 is not set +# CONFIG_ARCH_CHIP_STM32F372R8 is not set +# CONFIG_ARCH_CHIP_STM32F372V8 is not set +# CONFIG_ARCH_CHIP_STM32F372CB is not set +# CONFIG_ARCH_CHIP_STM32F372RB is not set +# CONFIG_ARCH_CHIP_STM32F372VB is not set +# CONFIG_ARCH_CHIP_STM32F372CC is not set +# CONFIG_ARCH_CHIP_STM32F372RC is not set +# CONFIG_ARCH_CHIP_STM32F372VC is not set +# CONFIG_ARCH_CHIP_STM32F373C8 is not set +# CONFIG_ARCH_CHIP_STM32F373R8 is not set +# CONFIG_ARCH_CHIP_STM32F373V8 is not set +# CONFIG_ARCH_CHIP_STM32F373CB is not set +# CONFIG_ARCH_CHIP_STM32F373RB is not set +# CONFIG_ARCH_CHIP_STM32F373VB is not set +# CONFIG_ARCH_CHIP_STM32F373CC is not set +# CONFIG_ARCH_CHIP_STM32F373RC is not set +# CONFIG_ARCH_CHIP_STM32F373VC is not set +# CONFIG_ARCH_CHIP_STM32F401RE is not set +# CONFIG_ARCH_CHIP_STM32F411RE is not set +# CONFIG_ARCH_CHIP_STM32F411VE is not set +# CONFIG_ARCH_CHIP_STM32F405RG is not set +# CONFIG_ARCH_CHIP_STM32F405VG is not set +# CONFIG_ARCH_CHIP_STM32F405ZG is not set +# CONFIG_ARCH_CHIP_STM32F407VE is not set +# CONFIG_ARCH_CHIP_STM32F407VG is not set +# CONFIG_ARCH_CHIP_STM32F407ZE is not set +# CONFIG_ARCH_CHIP_STM32F407ZG is not set +# CONFIG_ARCH_CHIP_STM32F407IE is not set +# CONFIG_ARCH_CHIP_STM32F407IG is not set +# CONFIG_ARCH_CHIP_STM32F427V is not set +# CONFIG_ARCH_CHIP_STM32F427Z is not set +# CONFIG_ARCH_CHIP_STM32F427I is not set +# CONFIG_ARCH_CHIP_STM32F429V is not set +# CONFIG_ARCH_CHIP_STM32F429Z is not set +# CONFIG_ARCH_CHIP_STM32F429I is not set +# CONFIG_ARCH_CHIP_STM32F429B is not set +# CONFIG_ARCH_CHIP_STM32F429N is not set +# CONFIG_ARCH_CHIP_STM32F446M is not set +# CONFIG_ARCH_CHIP_STM32F446R is not set +# CONFIG_ARCH_CHIP_STM32F446V is not set +# CONFIG_ARCH_CHIP_STM32F446Z is not set +# CONFIG_ARCH_CHIP_STM32F469A is not set +# CONFIG_ARCH_CHIP_STM32F469I is not set +# CONFIG_ARCH_CHIP_STM32F469B is not set +# CONFIG_ARCH_CHIP_STM32F469N is not set +CONFIG_STM32_FLASH_CONFIG_DEFAULT=y +# CONFIG_STM32_FLASH_CONFIG_4 is not set +# CONFIG_STM32_FLASH_CONFIG_6 is not set +# CONFIG_STM32_FLASH_CONFIG_8 is not set +# CONFIG_STM32_FLASH_CONFIG_B is not set +# CONFIG_STM32_FLASH_CONFIG_C is not set +# CONFIG_STM32_FLASH_CONFIG_D is not set +# CONFIG_STM32_FLASH_CONFIG_E is not set +# CONFIG_STM32_FLASH_CONFIG_F is not set +# CONFIG_STM32_FLASH_CONFIG_G is not set +# CONFIG_STM32_FLASH_CONFIG_I is not set +# CONFIG_STM32_STM32L15XX is not set +# CONFIG_STM32_ENERGYLITE is not set +CONFIG_STM32_STM32F10XX=y +# CONFIG_STM32_VALUELINE is not set +# CONFIG_STM32_CONNECTIVITYLINE is not set +CONFIG_STM32_PERFORMANCELINE=y +# CONFIG_STM32_USBACCESSLINE is not set +# CONFIG_STM32_HIGHDENSITY is not set +CONFIG_STM32_MEDIUMDENSITY=y +# CONFIG_STM32_LOWDENSITY is not set +# CONFIG_STM32_STM32F20XX is not set +# CONFIG_STM32_STM32F205 is not set +# CONFIG_STM32_STM32F207 is not set +# CONFIG_STM32_STM32F30XX is not set +# CONFIG_STM32_STM32F302 is not set +# CONFIG_STM32_STM32F303 is not set +# CONFIG_STM32_STM32F37XX is not set +# CONFIG_STM32_STM32F40XX is not set +# CONFIG_STM32_STM32F401 is not set +# CONFIG_STM32_STM32F411 is not set +# CONFIG_STM32_STM32F405 is not set +# CONFIG_STM32_STM32F407 is not set +# CONFIG_STM32_STM32F427 is not set +# CONFIG_STM32_STM32F429 is not set +# CONFIG_STM32_STM32F446 is not set +# CONFIG_STM32_STM32F469 is not set +# CONFIG_STM32_DFU is not set + +# +# STM32 Peripheral Support +# +# CONFIG_STM32_HAVE_CCM is not set +CONFIG_STM32_HAVE_USBDEV=y +# CONFIG_STM32_HAVE_OTGFS is not set +# CONFIG_STM32_HAVE_FSMC is not set +# CONFIG_STM32_HAVE_LTDC is not set +CONFIG_STM32_HAVE_USART3=y +CONFIG_STM32_HAVE_UART4=y +CONFIG_STM32_HAVE_UART5=y +# CONFIG_STM32_HAVE_USART6 is not set +# CONFIG_STM32_HAVE_UART7 is not set +# CONFIG_STM32_HAVE_UART8 is not set +CONFIG_STM32_HAVE_TIM1=y +# CONFIG_STM32_HAVE_TIM2 is not set +CONFIG_STM32_HAVE_TIM3=y +CONFIG_STM32_HAVE_TIM4=y +CONFIG_STM32_HAVE_TIM5=y +CONFIG_STM32_HAVE_TIM6=y +CONFIG_STM32_HAVE_TIM7=y +CONFIG_STM32_HAVE_TIM8=y +# CONFIG_STM32_HAVE_TIM9 is not set +# CONFIG_STM32_HAVE_TIM10 is not set +# CONFIG_STM32_HAVE_TIM11 is not set +# CONFIG_STM32_HAVE_TIM12 is not set +# CONFIG_STM32_HAVE_TIM13 is not set +# CONFIG_STM32_HAVE_TIM14 is not set +# CONFIG_STM32_HAVE_TIM15 is not set +# CONFIG_STM32_HAVE_TIM16 is not set +# CONFIG_STM32_HAVE_TIM17 is not set +CONFIG_STM32_HAVE_ADC2=y +CONFIG_STM32_HAVE_ADC3=y +# CONFIG_STM32_HAVE_ADC4 is not set +# CONFIG_STM32_HAVE_ADC1_DMA is not set +# CONFIG_STM32_HAVE_ADC2_DMA is not set +# CONFIG_STM32_HAVE_ADC3_DMA is not set +# CONFIG_STM32_HAVE_ADC4_DMA is not set +CONFIG_STM32_HAVE_CAN1=y +# CONFIG_STM32_HAVE_CAN2 is not set +# CONFIG_STM32_HAVE_DAC1 is not set +# CONFIG_STM32_HAVE_DAC2 is not set +# CONFIG_STM32_HAVE_RNG is not set +# CONFIG_STM32_HAVE_ETHMAC is not set +CONFIG_STM32_HAVE_I2C2=y +# CONFIG_STM32_HAVE_I2C3 is not set +CONFIG_STM32_HAVE_SPI2=y +CONFIG_STM32_HAVE_SPI3=y +# CONFIG_STM32_HAVE_SPI4 is not set +# CONFIG_STM32_HAVE_SPI5 is not set +# CONFIG_STM32_HAVE_SPI6 is not set +# CONFIG_STM32_HAVE_SAIPLL is not set +# CONFIG_STM32_HAVE_I2SPLL is not set +# CONFIG_STM32_ADC1 is not set +# CONFIG_STM32_ADC2 is not set +# CONFIG_STM32_ADC3 is not set +# CONFIG_STM32_BKP is not set +# CONFIG_STM32_CAN1 is not set +# CONFIG_STM32_CRC is not set +# CONFIG_STM32_DMA1 is not set +# CONFIG_STM32_DMA2 is not set +# CONFIG_STM32_I2C1 is not set +# CONFIG_STM32_I2C2 is not set +# CONFIG_STM32_PWR is not set +# CONFIG_STM32_SDIO is not set +# CONFIG_STM32_SPI1 is not set +# CONFIG_STM32_SPI2 is not set +# CONFIG_STM32_SPI3 is not set +# CONFIG_STM32_TIM1 is not set +# CONFIG_STM32_TIM2 is not set +# CONFIG_STM32_TIM3 is not set +# CONFIG_STM32_TIM4 is not set +# CONFIG_STM32_TIM5 is not set +# CONFIG_STM32_TIM6 is not set +# CONFIG_STM32_TIM7 is not set +# CONFIG_STM32_TIM8 is not set +CONFIG_STM32_USART1=y +# CONFIG_STM32_USART2 is not set +# CONFIG_STM32_USART3 is not set +# CONFIG_STM32_UART4 is not set +# CONFIG_STM32_UART5 is not set +# CONFIG_STM32_USB is not set +# CONFIG_STM32_IWDG is not set +# CONFIG_STM32_WWDG is not set +# CONFIG_STM32_NOEXT_VECTORS is not set + +# +# Alternate Pin Mapping +# +# CONFIG_STM32_USART1_REMAP is not set +# CONFIG_STM32_JTAG_DISABLE is not set +# CONFIG_STM32_JTAG_FULL_ENABLE is not set +# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +# CONFIG_STM32_FORCEPOWER is not set +# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set + +# +# Timer Configuration +# +# CONFIG_STM32_ONESHOT is not set +# CONFIG_STM32_FREERUN is not set +# CONFIG_STM32_TIM1_CAP is not set +# CONFIG_STM32_TIM3_CAP is not set +# CONFIG_STM32_TIM4_CAP is not set +# CONFIG_STM32_TIM5_CAP is not set +# CONFIG_STM32_TIM8_CAP is not set +CONFIG_STM32_USART=y +CONFIG_STM32_SERIALDRIVER=y + +# +# U[S]ART Configuration +# + +# +# U[S]ART Device Configuration +# +CONFIG_STM32_USART1_SERIALDRIVER=y +# CONFIG_STM32_USART1_1WIREDRIVER is not set +# CONFIG_USART1_RS485 is not set + +# +# Serial Driver Configuration +# +# CONFIG_SERIAL_DISABLE_REORDERING is not set +# CONFIG_STM32_FLOWCONTROL_BROKEN is not set +# CONFIG_STM32_USART_BREAKS is not set +# CONFIG_STM32_USART_SINGLEWIRE is not set +CONFIG_STM32_HAVE_RTC_COUNTER=y +# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set + +# +# USB FS Host Configuration +# + +# +# USB HS Host Configuration +# + +# +# USB Host Debug Configuration +# + +# +# USB Device Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=5483 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_SIZE=20480 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +# CONFIG_ARCH_BOARD_STM32_TINY is not set +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="stm32f103-minimum" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +# CONFIG_ARCH_LEDS is not set +CONFIG_ARCH_HAVE_BUTTONS=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_HAVE_IRQBUTTONS=y +CONFIG_ARCH_IRQBUTTONS=y + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_RESET is not set +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_ADCTEST is not set +# CONFIG_BOARDCTL_PWMTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set + +# +# RTOS Features +# +# CONFIG_DISABLE_OS_API is not set + +# +# Clocks and Timers +# +CONFIG_ARCH_HAVE_TICKLESS=y +# CONFIG_SCHED_TICKLESS is not set +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +CONFIG_ARCH_HAVE_TIMEKEEPING=y +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2011 +CONFIG_START_MONTH=7 +CONFIG_START_DAY=5 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=0 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +CONFIG_BOARD_INITIALIZE=y +# CONFIG_BOARD_INITTHREAD is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +# CONFIG_DISABLE_POLL is not set +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +CONFIG_ARCH_HAVE_I2CRESET=y +# CONFIG_I2C is not set +# CONFIG_SPI is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +CONFIG_INPUT=y +# CONFIG_MOUSE is not set +# CONFIG_INPUT_MAX11802 is not set +# CONFIG_INPUT_TSC2007 is not set +# CONFIG_INPUT_ADS7843E is not set +# CONFIG_INPUT_MXT is not set +# CONFIG_INPUT_STMPE811 is not set +CONFIG_BUTTONS=y +CONFIG_BUTTONS_LOWER=y +CONFIG_BUTTONS_NPOLLWAITERS=2 +# CONFIG_DJOYSTICK is not set +# CONFIG_AJOYSTICK is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +CONFIG_USART1_SERIALDRIVER=y +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_SERIAL_NPOLLWAITERS=2 +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +CONFIG_USART1_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# USART1 Configuration +# +CONFIG_USART1_RXBUFSIZE=256 +CONFIG_USART1_TXBUFSIZE=256 +CONFIG_USART1_BAUD=115200 +CONFIG_USART1_BITS=8 +CONFIG_USART1_PARITY=0 +CONFIG_USART1_2STOP=0 +# CONFIG_USART1_IFLOWCONTROL is not set +# CONFIG_USART1_OFLOWCONTROL is not set +# CONFIG_USART1_DMA is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +# CONFIG_FS_READABLE is not set +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +CONFIG_SYMTAB_ORDEREDBYNAME=y + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_LIBC_LONG_LONG is not set +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set +# CONFIG_LIBC_NETDB is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_ARCHBUTTONS is not set +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_PRIORITY=100 +CONFIG_EXAMPLES_BUTTONS_STACKSIZE=2048 +CONFIG_EXAMPLES_BUTTONS_DEVPATH="/dev/buttons" +# CONFIG_EXAMPLES_BUTTONS_NAMES is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_LEDS is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CHAT is not set +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=80 +CONFIG_NSH_DISABLE_SEMICOLON=y +# CONFIG_NSH_CMDPARMS is not set +CONFIG_NSH_MAXARGUMENTS=6 +# CONFIG_NSH_ARGCAT is not set +CONFIG_NSH_NESTDEPTH=3 +CONFIG_NSH_DISABLEBG=y +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +CONFIG_NSH_DISABLE_ADDROUTE=y +CONFIG_NSH_DISABLE_BASENAME=y +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +CONFIG_NSH_DISABLE_DF=y +CONFIG_NSH_DISABLE_DELROUTE=y +CONFIG_NSH_DISABLE_DIRNAME=y +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +CONFIG_NSH_DISABLE_IFCONFIG=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_KILL is not set +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +CONFIG_NSH_DISABLE_TIME=y +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +CONFIG_NSH_DISABLE_UNAME=y +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Configure Command Options +# +CONFIG_NSH_CODECS_BUFSIZE=128 +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_NSH_FILEIOSIZE=1024 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +CONFIG_NSH_DISABLE_ITEF=y +CONFIG_NSH_DISABLE_LOOPS=y + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm32f103-minimum/buttons/setenv.sh b/configs/stm32f103-minimum/buttons/setenv.sh new file mode 100644 index 0000000000..73dfab5a4d --- /dev/null +++ b/configs/stm32f103-minimum/buttons/setenv.sh @@ -0,0 +1,100 @@ +#!/bin/bash +# configs//stm32f103-minimum/nsh/setenv.sh +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" +# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" +# You can this free toolchain here https://launchpad.net/gcc-arm-embedded +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" + +# This is the path to the location where I installed the devkitARM toolchain +# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/ +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/configs/stm32f103-minimum/include/board.h b/configs/stm32f103-minimum/include/board.h index 85bdf23464..c2a17aff37 100644 --- a/configs/stm32f103-minimum/include/board.h +++ b/configs/stm32f103-minimum/include/board.h @@ -152,6 +152,15 @@ # define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) #endif +/* BUTTON definitions ***************************************************************/ + +#define NUM_BUTTONS 2 + +#define BUTTON_USER1 0 +#define BUTTON_USER2 1 +#define BUTTON_USER1_BIT (1 << BUTTON_USER1) +#define BUTTON_USER2_BIT (1 << BUTTON_USER2) + /* LED definitions ******************************************************************/ /* Define how many LEDs this board has (needed by userleds) */ diff --git a/configs/stm32f103-minimum/src/Makefile b/configs/stm32f103-minimum/src/Makefile index 746f20edbc..5596fb6e43 100644 --- a/configs/stm32f103-minimum/src/Makefile +++ b/configs/stm32f103-minimum/src/Makefile @@ -43,6 +43,10 @@ ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += stm32_appinit.c endif +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + ifeq ($(CONFIG_ARCH_LEDS),y) CSRCS += stm32_autoleds.c else diff --git a/configs/stm32f103-minimum/src/stm32_bringup.c b/configs/stm32f103-minimum/src/stm32_bringup.c index 2843f67e5b..fac7292c58 100644 --- a/configs/stm32f103-minimum/src/stm32_bringup.c +++ b/configs/stm32f103-minimum/src/stm32_bringup.c @@ -61,6 +61,10 @@ # include "stm32_usbhost.h" #endif +#ifdef CONFIG_BUTTONS +# include +#endif + #ifdef CONFIG_USERLED # include #endif @@ -128,6 +132,16 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + #ifdef CONFIG_USERLED /* Register the LED driver */ diff --git a/configs/stm32f103-minimum/src/stm32_buttons.c b/configs/stm32f103-minimum/src/stm32_buttons.c new file mode 100644 index 0000000000..d611bf44fb --- /dev/null +++ b/configs/stm32f103-minimum/src/stm32_buttons.c @@ -0,0 +1,171 @@ +/**************************************************************************** + * configs/stm32f103-minimum/src/stm32_buttons.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "stm32f103_minimum.h" + +#if defined(CONFIG_ARCH_BUTTONS) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_BUTTONS) && !defined(CONFIG_ARCH_IRQBUTTONS) +# error "The NuttX Buttons Driver depends on IRQ support to work!\n" +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Pin configuration for each STM32F3Discovery button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER1, GPIO_BTN_USER2 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. After + * that, board_buttons() may be called to collect the current state of all + * buttons or board_button_irq() may be called to register button interrupt + * handlers. + * + ****************************************************************************/ + +void board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint8_t board_buttons(void) +{ + uint8_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. + */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns + * an 8-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. The previous interrupt handler address is returned (so that it + * may be restored, if so desired). + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +xcpt_t board_button_irq(int id, xcpt_t irqhandler) +{ + xcpt_t oldhandler = NULL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler); + } + + return oldhandler; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/configs/stm32f103-minimum/src/stm32f103_minimum.h b/configs/stm32f103-minimum/src/stm32f103_minimum.h index a52b49b3a0..ec66bb5898 100644 --- a/configs/stm32f103-minimum/src/stm32f103_minimum.h +++ b/configs/stm32f103-minimum/src/stm32f103_minimum.h @@ -65,6 +65,18 @@ #define GPIO_LED1 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN13) +/* BUTTONs */ + +#define GPIO_BTN_USER1 (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|\ + GPIO_EXTI|GPIO_PORTA|GPIO_PIN0) + +#define GPIO_BTN_USER2 (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|\ + GPIO_EXTI|GPIO_PORTA|GPIO_PIN1) + +#define MIN_IRQBUTTON BUTTON_USER1 +#define MAX_IRQBUTTON BUTTON_USER2 +#define NUM_IRQBUTTONS (BUTTON_USER1 - BUTTON_USER2 + 1) + /* SPI chip selects */ -- GitLab From 4195692bb4f22622bb9781958d2341b4f6fb716c Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Tue, 11 Oct 2016 14:29:27 -0600 Subject: [PATCH 053/734] Change "Board LED support" to "Board LED Status support" --- configs/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/Kconfig b/configs/Kconfig index ca3b408285..2b629c1a4f 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -1501,7 +1501,7 @@ config ARCH_HAVE_LEDS bool config ARCH_LEDS - bool "Board LED support" + bool "Board LED Status support" default y depends on ARCH_HAVE_LEDS ---help--- -- GitLab From 55523f5771f329d911e4f44a870d7f8d31c24fa8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 12 Oct 2016 13:11:05 -0600 Subject: [PATCH 054/734] arch/xtensa: Add a few basic XTENSA/LX6 files. Not yet enough to do anything with --- arch/xtensa/Kconfig | 31 ++ arch/xtensa/include/arch.h | 82 +++++ arch/xtensa/include/irq.h | 91 ++++++ arch/xtensa/include/limits.h | 87 ++++++ arch/xtensa/include/lx6/chip.h | 84 ++++++ arch/xtensa/include/lx6/irq.h | 85 ++++++ arch/xtensa/include/syscall.h | 82 +++++ arch/xtensa/include/types.h | 94 ++++++ arch/xtensa/src/common/up_arch.h | 90 ++++++ arch/xtensa/src/common/xtensa.h | 285 ++++++++++++++++++ arch/xtensa/src/common/xtensa_allocateheap.c | 88 ++++++ arch/xtensa/src/common/xtensa_createstack.c | 214 +++++++++++++ arch/xtensa/src/common/xtensa_etherstub.c | 86 ++++++ arch/xtensa/src/common/xtensa_exit.c | 188 ++++++++++++ arch/xtensa/src/common/xtensa_idle.c | 95 ++++++ arch/xtensa/src/common/xtensa_initialize.c | 261 ++++++++++++++++ .../src/common/xtensa_interruptcontext.c | 70 +++++ arch/xtensa/src/common/xtensa_lowputs.c | 74 +++++ arch/xtensa/src/common/xtensa_mdelay.c | 90 ++++++ arch/xtensa/src/common/xtensa_modifyreg16.c | 85 ++++++ arch/xtensa/src/common/xtensa_modifyreg32.c | 85 ++++++ arch/xtensa/src/common/xtensa_modifyreg8.c | 85 ++++++ arch/xtensa/src/common/xtensa_puts.c | 75 +++++ arch/xtensa/src/common/xtensa_releasestack.c | 122 ++++++++ arch/xtensa/src/common/xtensa_stackframe.c | 143 +++++++++ arch/xtensa/src/common/xtensa_udelay.c | 129 ++++++++ arch/xtensa/src/common/xtensa_usestack.c | 152 ++++++++++ arch/xtensa/src/lx6/Kconfig | 9 + arch/xtensa/src/lx6/Make.defs | 67 ++++ 29 files changed, 3129 insertions(+) create mode 100644 arch/xtensa/Kconfig create mode 100644 arch/xtensa/include/arch.h create mode 100644 arch/xtensa/include/irq.h create mode 100644 arch/xtensa/include/limits.h create mode 100644 arch/xtensa/include/lx6/chip.h create mode 100644 arch/xtensa/include/lx6/irq.h create mode 100644 arch/xtensa/include/syscall.h create mode 100644 arch/xtensa/include/types.h create mode 100644 arch/xtensa/src/common/up_arch.h create mode 100644 arch/xtensa/src/common/xtensa.h create mode 100644 arch/xtensa/src/common/xtensa_allocateheap.c create mode 100644 arch/xtensa/src/common/xtensa_createstack.c create mode 100644 arch/xtensa/src/common/xtensa_etherstub.c create mode 100644 arch/xtensa/src/common/xtensa_exit.c create mode 100644 arch/xtensa/src/common/xtensa_idle.c create mode 100644 arch/xtensa/src/common/xtensa_initialize.c create mode 100644 arch/xtensa/src/common/xtensa_interruptcontext.c create mode 100644 arch/xtensa/src/common/xtensa_lowputs.c create mode 100644 arch/xtensa/src/common/xtensa_mdelay.c create mode 100644 arch/xtensa/src/common/xtensa_modifyreg16.c create mode 100644 arch/xtensa/src/common/xtensa_modifyreg32.c create mode 100644 arch/xtensa/src/common/xtensa_modifyreg8.c create mode 100644 arch/xtensa/src/common/xtensa_puts.c create mode 100644 arch/xtensa/src/common/xtensa_releasestack.c create mode 100644 arch/xtensa/src/common/xtensa_stackframe.c create mode 100644 arch/xtensa/src/common/xtensa_udelay.c create mode 100644 arch/xtensa/src/common/xtensa_usestack.c create mode 100644 arch/xtensa/src/lx6/Kconfig create mode 100644 arch/xtensa/src/lx6/Make.defs diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig new file mode 100644 index 0000000000..d740939c1e --- /dev/null +++ b/arch/xtensa/Kconfig @@ -0,0 +1,31 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_XTENSA + +choice + prompt "XTENSA architecture selection" + default ARCH_CHIP_LX6 + +config ARCH_CHIP_LX6 + bool "LX6 DPU" + select ARCH_LX6 + ---help--- + Cadence® Tensilica® Xtensa® LX6 data plane processing unit (DPU). + The LX6 is a configurable and extensible processor core. + +endchoice # XTENSA chip selection + +config ARCH_LX6 + bool + default n + +config ARCH_CHIP + string + default "lx6" if ARCH_LX6 + +source arch/xtensa/src/lx6/Kconfig + +endif # ARCH_XTENSA diff --git a/arch/xtensa/include/arch.h b/arch/xtensa/include/arch.h new file mode 100644 index 0000000000..760e52ff70 --- /dev/null +++ b/arch/xtensa/include/arch.h @@ -0,0 +1,82 @@ +/**************************************************************************** + * arch/xtensa/include/arch.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/arch.h + */ + +#ifndef __ARCH_XTENSA_INCLUDE_ARCH_H +#define __ARCH_XTENSA_INCLUDE_ARCH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ARCH_XTENSA_INCLUDE_ARCH_H */ diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h new file mode 100644 index 0000000000..d2af5ba4e4 --- /dev/null +++ b/arch/xtensa/include/irq.h @@ -0,0 +1,91 @@ +/**************************************************************************** + * arch/xtensa/include/irq.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_XTENSA_INCLUDE_IRQ_H +#define __ARCH_XTENSA_INCLUDE_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include NuttX-specific IRQ definitions */ + +#include + +/* Include chip-specific IRQ definitions (including IRQ numbers) */ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_INCLUDE_IRQ_H */ diff --git a/arch/xtensa/include/limits.h b/arch/xtensa/include/limits.h new file mode 100644 index 0000000000..f3eb3b4795 --- /dev/null +++ b/arch/xtensa/include/limits.h @@ -0,0 +1,87 @@ +/**************************************************************************** + * arch/xtensa/include/limits.h + * + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_INCLUDE_LIMITS_H +#define __ARCH_XTENSA_INCLUDE_LIMITS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CHAR_BIT 8 +#define SCHAR_MIN (-SCHAR_MAX - 1) +#define SCHAR_MAX 127 +#define UCHAR_MAX 255 + +/* These could be different on machines where char is unsigned */ + +#ifdef __CHAR_UNSIGNED__ +#define CHAR_MIN 0 +#define CHAR_MAX UCHAR_MAX +#else +#define CHAR_MIN SCHAR_MIN +#define CHAR_MAX SCHAR_MAX +#endif + +#define SHRT_MIN (-SHRT_MAX - 1) +#define SHRT_MAX 32767 +#define USHRT_MAX 65535U + +#define INT_MIN (-INT_MAX - 1) +#define INT_MAX 2147483647 +#define UINT_MAX 4294967295U + +/* These change on 32-bit and 64-bit platforms */ + +#define LONG_MIN (-LONG_MAX - 1) +#define LONG_MAX 2147483647L +#define ULONG_MAX 4294967295UL + +#define LLONG_MIN (-LLONG_MAX - 1) +#define LLONG_MAX 9223372036854775807LL +#define ULLONG_MAX 18446744073709551615ULL + +/* A pointer is 4 bytes */ + +#define PTR_MIN (-PTR_MAX - 1) +#define PTR_MAX 2147483647 +#define UPTR_MAX 4294967295U + +#endif /* __ARCH_XTENSA_INCLUDE_LIMITS_H */ + diff --git a/arch/xtensa/include/lx6/chip.h b/arch/xtensa/include/lx6/chip.h new file mode 100644 index 0000000000..060d99e945 --- /dev/null +++ b/arch/xtensa/include/lx6/chip.h @@ -0,0 +1,84 @@ +/**************************************************************************** + * arch/xtensa/include/lx6/chip.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_INCLUDE_LX6_CHIP_H +#define __ARCH_XTENSA_INCLUDE_LX6_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +#if defined(CONFIG_ARCH_CHIP_LX6) +/* To be provided */ +#else +# error "Unrecognized LX6 device +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_INCLUDE_LX6_CHIP_H */ diff --git a/arch/xtensa/include/lx6/irq.h b/arch/xtensa/include/lx6/irq.h new file mode 100644 index 0000000000..ec2b218f58 --- /dev/null +++ b/arch/xtensa/include/lx6/irq.h @@ -0,0 +1,85 @@ +/**************************************************************************** + * arch/xtensa/include/lx6/irq.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_XTENSA_INCLUDE_LX6_IRQ_H +#define __ARCH_XTENSA_INCLUDE_LX6_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_INCLUDE_LX6_IRQ_H */ diff --git a/arch/xtensa/include/syscall.h b/arch/xtensa/include/syscall.h new file mode 100644 index 0000000000..fe2d71e6de --- /dev/null +++ b/arch/xtensa/include/syscall.h @@ -0,0 +1,82 @@ +/**************************************************************************** + * arch/xtensa/include/syscall.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through include/syscall.h or include/sys/sycall.h + */ + +#ifndef __ARCH_XTENSA_INCLUDE_SYSCALL_H +#define __ARCH_XTENSA_INCLUDE_SYSCALL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_XTENSA_INCLUDE_SYSCALL_H */ diff --git a/arch/xtensa/include/types.h b/arch/xtensa/include/types.h new file mode 100644 index 0000000000..aa987ff8bb --- /dev/null +++ b/arch/xtensa/include/types.h @@ -0,0 +1,94 @@ +/**************************************************************************** + * arch/xtensa/include/types.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through stdint.h + */ + +#ifndef __ARCH_XTENSA_INCLUDE_TYPES_H +#define __ARCH_XTENSA_INCLUDE_TYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Type Declarations + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* These are the sizes of the standard integer types. NOTE that these type + * names have a leading underscore character. This file will be included + * (indirectly) by include/stdint.h and typedef'ed to the final name without + * the underscore character. This roundabout way of doings things allows + * the stdint.h to be removed from the include/ directory in the event that + * the user prefers to use the definitions provided by their toolchain header + * files + */ + +typedef signed char _int8_t; +typedef unsigned char _uint8_t; + +typedef signed short _int16_t; +typedef unsigned short _uint16_t; + +typedef signed int _int32_t; +typedef unsigned int _uint32_t; + +typedef signed long long _int64_t; +typedef unsigned long long _uint64_t; +#define __INT64_DEFINED + +/* A pointer is 4 bytes */ + +typedef signed int _intptr_t; +typedef unsigned int _uintptr_t; + +/* This is the size of the interrupt state save returned by up_irq_save(). */ + +typedef unsigned int irqstate_t; + +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_XTENSA_INCLUDE_TYPES_H */ diff --git a/arch/xtensa/src/common/up_arch.h b/arch/xtensa/src/common/up_arch.h new file mode 100644 index 0000000000..4fd625bf7a --- /dev/null +++ b/arch/xtensa/src/common/up_arch.h @@ -0,0 +1,90 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_arch.h + * + * Copyright (C) 2010, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef ___ARCH_XTENSA_SRC_COMMON_XTENSA_ARCH_H +#define ___ARCH_XTENSA_SRC_COMMON_XTENSA_ARCH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +# define getreg8(a) (*(volatile uint8_t *)(a)) +# define putreg8(v,a) (*(volatile uint8_t *)(a) = (v)) +# define getreg16(a) (*(volatile uint16_t *)(a)) +# define putreg16(v,a) (*(volatile uint16_t *)(a) = (v)) +# define getreg32(a) (*(volatile uint32_t *)(a)) +# define putreg32(v,a) (*(volatile uint32_t *)(a) = (v)) + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* Atomic modification of registers */ + +void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits); +void modifyreg16(unsigned int addr, uint16_t clearbits, uint16_t setbits); +void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* ___ARCH_XTENSA_SRC_COMMON_XTENSA_ARCH_H */ diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h new file mode 100644 index 0000000000..cef80d3ae9 --- /dev/null +++ b/arch/xtensa/src/common/xtensa.h @@ -0,0 +1,285 @@ +/**************************************************************************** + * arch/xtensa/common/xtensa_internal.h + * + * Copyright (C) 2011, 2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_INTERNAL_H +#define __ARCH_XTENSA_SRC_COMMON_XTENSA_INTERNAL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Bring-up debug configurations. These are here (vs defconfig) + * because these should only be controlled during low level + * board bring-up and not part of normal platform configuration. + */ + +#undef CONFIG_SUPPRESS_INTERRUPTS /* DEFINED: Do not enable interrupts */ +#undef CONFIG_SUPPRESS_TIMER_INTS /* DEFINED: No timer */ +#undef CONFIG_SUPPRESS_SERIAL_INTS /* DEFINED: Console will poll */ +#undef CONFIG_SUPPRESS_UART_CONFIG /* DEFINED: Do not reconfig UART */ +#undef CONFIG_DUMP_ON_EXIT /* DEFINED: Dump task state on exit */ + +#ifndef CONFIG_DEBUG_SCHED_INFO +# undef CONFIG_DUMP_ON_EXIT /* Needs CONFIG_DEBUG_SCHED_INFO */ +#endif + +/* Determine which (if any) console driver to use. If a console is enabled + * and no other console device is specified, then a serial console is + * assumed. + */ + +#if !defined(CONFIG_DEV_CONSOLE) || CONFIG_NFILE_DESCRIPTORS <= 0 +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +# undef CONFIG_DEV_LOWCONSOLE +# undef CONFIG_RAMLOG_CONSOLE +#else +# if defined(CONFIG_RAMLOG_CONSOLE) +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +# undef CONFIG_DEV_LOWCONSOLE +# elif defined(CONFIG_DEV_LOWCONSOLE) +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +# else +# define USE_SERIALDRIVER 1 +# define USE_EARLYSERIALINIT 1 +# endif +#endif + +/* If some other device is used as the console, then the serial driver may + * still be needed. Let's assume that if the upper half serial driver is + * built, then the lower half will also be needed. There is no need for + * the early serial initialization in this case. + */ + +#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL) +# define USE_SERIALDRIVER 1 +#endif + +/* Check if an interrupt stack size is configured */ + +#ifndef CONFIG_ARCH_INTERRUPTSTACK +# define CONFIG_ARCH_INTERRUPTSTACK 0 +#endif + +/* In the XTENSA model, the state is copied from the stack to the TCB, but + * only a referenced is passed to get the state from the TCB. + */ + +#define up_savestate(regs) up_copystate(regs, (uint32_t*)g_current_regs) +#define up_restorestate(regs) (g_current_regs = regs) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +typedef void (*up_vector_t)(void); +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +/* This holds a references to the current interrupt level register storage + * structure. If is non-NULL only during interrupt processing. + */ + +extern volatile uint32_t *g_current_regs; + +/* This is the beginning of heap as provided from up_head.S. This is the + * first address in DRAM after the loaded program+bss+idle stack. The end + * of the heap is CONFIG_RAM_END + */ + +extern uint32_t g_idle_topstack; + +/* Address of the saved user stack pointer */ + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 +extern void g_intstackbase; +#endif + +/* These 'addresses' of these values are setup by the linker script. They are + * not actual uint32_t storage locations! They are only used meaningfully in the + * following way: + * + * - The linker script defines, for example, the symbol_sdata. + * - The declaration extern uint32_t _sdata; makes C happy. C will believe + * that the value _sdata is the address of a uint32_t variable _data (it is + * not!). + * - We can recoved the linker value then by simply taking the address of + * of _data. like: uint32_t *pdata = &_sdata; + */ + +extern uint32_t _stext; /* Start of .text */ +extern uint32_t _etext; /* End+1 of .text + .rodata */ +extern const uint32_t _data_loaddr; /* Start of .data in FLASH */ +extern uint32_t _sdata; /* Start of .data */ +extern uint32_t _edata; /* End+1 of .data */ +extern uint32_t _sbss; /* Start of .bss */ +extern uint32_t _ebss; /* End+1 of .bss */ +#ifdef CONFIG_ARCH_RAMFUNCS +extern uint32_t _sramfunc; /* Start of ramfuncs */ +extern uint32_t _eramfunc; /* End+1 of ramfuncs */ +extern uint32_t _ramfunc_loadaddr; /* Start of ramfuncs in FLASH */ +extern uint32_t _ramfunc_sizeof; /* Size of ramfuncs */ +extern uint32_t _bmxdkpba_address; /* BMX register setting */ +extern uint32_t _bmxdudba_address; /* BMX register setting */ +extern uint32_t _bmxdupba_address; /* BMX register setting */ +#endif /* CONFIG_ARCH_RAMFUNCS */ +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +/* Common Functions *********************************************************/ +/* Common functions define in arch/xtensa/src/common. These may be replaced + * with chip-specific functions of the same name if needed. See also + * functions prototyped in include/nuttx/arch.h. + */ + +/* Context switching */ + +void up_copystate(uint32_t *dest, uint32_t *src); + +/* Serial output */ + +void up_puts(const char *str); +void up_lowputs(const char *str); + +/* Defined in drivers/lowconsole.c */ + +#ifdef CONFIG_DEV_LOWCONSOLE +void lowconsole_init(void); +#else +# define lowconsole_init() +#endif + +/* Debug */ + +#ifdef CONFIG_ARCH_STACKDUMP +void up_dumpstate(void); +#else +# define up_dumpstate() +#endif + +/* Common XTENSA32 functions defined in arch/xtensa/src/XTENSA32 */ +/* IRQs */ + +uint32_t *up_doirq(int irq, uint32_t *regs); + +/* Software interrupt 0 handler */ + +int up_swint0(int irq, FAR void *context); + +/* Signals */ + +void up_sigdeliver(void); + +/* Chip-specific functions **************************************************/ +/* Chip specific functions defined in arch/xtensa/src/ */ +/* IRQs */ + +void up_irqinitialize(void); +bool up_pending_irq(int irq); +void up_clrpend_irq(int irq); + +/* DMA */ + +#ifdef CONFIG_ARCH_DMA +void weak_function up_dmainitialize(void); +#endif + +/* Memory management */ + +#if CONFIG_MM_REGIONS > 1 +void up_addregion(void); +#else +# define up_addregion() +#endif + +/* Serial output */ + +void up_lowputc(char ch); +#if CONFIG_NFILE_DESCRIPTORS > 0 +void up_earlyserialinit(void); +void up_serialinit(void); +#else +# define up_earlyserialinit() +# define up_serialinit() +#endif + +/* System timer */ + +void up_timer_initialize(void); + +/* Network */ + +#ifdef CONFIG_NET +void up_netinitialize(void); +#else +# define up_netinitialize() +#endif + +/* USB */ + +#ifdef CONFIG_USBDEV +void up_usbinitialize(void); +void up_usbuninitialize(void); +#else +# define up_usbinitialize() +# define up_usbuninitialize() +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_INTERNAL_H */ diff --git a/arch/xtensa/src/common/xtensa_allocateheap.c b/arch/xtensa/src/common/xtensa_allocateheap.c new file mode 100644 index 0000000000..fc2178b5d1 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_allocateheap.c @@ -0,0 +1,88 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_allocateheap.c + * + * Copyright (C) 2010, 2013, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * For the kernel build (CONFIG_BUILD_KERNEL=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the + * size of the unprotected, user-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated (and protected) by an analogous up_allocate_kheap(). + * + ****************************************************************************/ + +void up_allocate_heap(FAR void **heap_start, size_t *heap_size) +{ + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (FAR void *)g_idle_topstack; + *heap_size = CONFIG_RAM_END - g_idle_topstack; +} diff --git a/arch/xtensa/src/common/xtensa_createstack.c b/arch/xtensa/src/common/xtensa_createstack.c new file mode 100644 index 0000000000..08d310e497 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_createstack.c @@ -0,0 +1,214 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_createstack.c + * + * Copyright (C) 2011, 2013, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Macros + ****************************************************************************/ + +/* XTENSA requires at least a 4-byte stack alignment. For floating point use, + * however, the stack must be aligned to 8-byte addresses. + */ + +#ifdef CONFIG_LIBC_FLOATINGPOINT +# define STACK_ALIGNMENT 8 +#else +# define STACK_ALIGNMENT 4 +#endif + +/* Stack alignment macros */ + +#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1) +#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK) +#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_create_stack + * + * Description: + * Allocate a stack for a new thread and setup up stack-related information + * in the TCB. + * + * The following TCB fields must be initialized by this function: + * + * - adj_stack_size: Stack size after adjustment for hardware, processor, + * etc. This value is retained only for debug purposes. + * - stack_alloc_ptr: Pointer to allocated stack + * - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of + * the stack pointer. + * + * Inputs: + * - tcb: The TCB of new task + * - stack_size: The requested stack size. At least this much + * must be allocated. + * - ttype: The thread type. This may be one of following (defined in + * include/nuttx/sched.h): + * + * TCB_FLAG_TTYPE_TASK Normal user task + * TCB_FLAG_TTYPE_PTHREAD User pthread + * TCB_FLAG_TTYPE_KERNEL Kernel thread + * + * This thread type is normally available in the flags field of the TCB, + * however, there are certain contexts where the TCB may not be fully + * initialized when up_create_stack is called. + * + * If CONFIG_BUILD_KERNEL is defined, then this thread type may affect + * how the stack is allocated. For example, kernel thread stacks should + * be allocated from protected kernel memory. Stacks for user tasks and + * threads must come from memory that is accessible to user code. + * + ****************************************************************************/ + +int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) +{ + /* Is there already a stack allocated of a different size? Because of + * alignment issues, stack_size might erroneously appear to be of a + * different size. Fortunately, this is not a critical operation. + */ + + if (tcb->stack_alloc_ptr && tcb->adj_stack_size != stack_size) + { + /* Yes.. Release the old stack */ + + up_release_stack(tcb, ttype); + } + + /* Do we need to allocate a new stack? */ + + if (!tcb->stack_alloc_ptr) + { + /* Allocate the stack. If DEBUG is enabled (but not stack debug), + * then create a zeroed stack to make stack dumps easier to trace. + */ + +#if defined(CONFIG_BUILD_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP) + /* Use the kernel allocator if this is a kernel thread */ + + if (ttype == TCB_FLAG_TTYPE_KERNEL) + { + tcb->stack_alloc_ptr = (uint32_t *)kmm_malloc(stack_size); + } + else +#endif + { + /* Use the user-space allocator if this is a task or pthread */ + + tcb->stack_alloc_ptr = (uint32_t *)kumm_malloc(stack_size); + } + +#ifdef CONFIG_DEBUG_FEATURES + /* Was the allocation successful? */ + + if (!tcb->stack_alloc_ptr) + { + serr("ERROR: Failed to allocate stack, size %d\n", stack_size); + } +#endif + } + + /* Did we successfully allocate a stack? */ + + if (tcb->stack_alloc_ptr) + { + size_t top_of_stack; + size_t size_of_stack; + + /* Yes.. If stack debug is enabled, then fill the stack with a + * recognizable value that we can use later to test for high + * water marks. + */ + +#ifdef CONFIG_STACK_COLORATION + memset(tcb->stack_alloc_ptr, 0xaa, stack_size); +#endif + + /* XTENSA uses a push-down stack: the stack grows toward lower + * addresses in memory. The stack pointer register points to the + * lowest, valid working address (the "top" of the stack). Items on + * the stack are referenced as positive word offsets from sp. + */ + + top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4; + + /* The XTENSA stack must be aligned at word (4 byte) boundaries; for + * floating point use, the stack must be aligned to 8-byte addresses. + * If necessary top_of_stack must be rounded down to the next + * boundary to meet these alignment requirements. + */ + + top_of_stack = STACK_ALIGN_DOWN(top_of_stack); + size_of_stack = top_of_stack - (uint32_t)tcb->stack_alloc_ptr + 4; + + /* Save the adjusted stack values in the struct tcb_s */ + + tcb->adj_stack_ptr = (FAR uint32_t *)top_of_stack; + tcb->adj_stack_size = size_of_stack; + + board_autoled_on(LED_STACKCREATED); + return OK; + } + + return ERROR; +} diff --git a/arch/xtensa/src/common/xtensa_etherstub.c b/arch/xtensa/src/common/xtensa_etherstub.c new file mode 100644 index 0000000000..e19b26a208 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_etherstub.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_etherstub.c + * + * Copyright (C) 2011-2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_netinitialize (stub) + * + * Description: + * This is a stub version os up_netinitialize. Normally, up_netinitialize + * is defined in board/xyz_network.c for board-specific Ethernet + * implementations, or chip/xyx_ethernet.c for chip-specific Ethernet + * implementations. The stub version here is used in the corner case where + * the network is enable yet there is no Ethernet driver to be initialized. + * In this case, up_initialize will still try to call up_netinitialize() + * when one does not exist. This corner case would occur if, for example, + * only a USB network interface is being used or perhaps if a SLIP is + * being used). + * + * Use of this stub is deprecated. The preferred mechanism is to use + * CONFIG_NETDEV_LATEINIT=y to suppress the call to up_netinitialize() in + * up_initialize(). Then this stub would not be needed. + * + ****************************************************************************/ + +void up_netinitialize(void) +{ +} diff --git a/arch/xtensa/src/common/xtensa_exit.c b/arch/xtensa/src/common/xtensa_exit.c new file mode 100644 index 0000000000..f300c9b89a --- /dev/null +++ b/arch/xtensa/src/common/xtensa_exit.c @@ -0,0 +1,188 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_exit.c + * + * Copyright (C) 2011, 2013-2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#ifdef CONFIG_DUMP_ON_EXIT +#include +#endif + +#include "task/task.h" +#include "sched/sched.h" +#include "group/group.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_DEBUG_SCHED_INFO +# undef CONFIG_DUMP_ON_EXIT +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _up_dumponexit + * + * Description: + * Dump the state of all tasks whenever on task exits. This is debug + * instrumentation that was added to check file-related reference counting + * but could be useful again sometime in the future. + * + ****************************************************************************/ + +#ifdef CONFIG_DUMP_ON_EXIT +static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) +{ +#if CONFIG_NFILE_DESCRIPTORS > 0 + FAR struct filelist *filelist; +#if CONFIG_NFILE_STREAMS > 0 + FAR struct streamlist *streamlist; +#endif + int i; +#endif + + sinfo(" TCB=%p name=%s pid=%d\n", tcb, tcb->argv[0], tcb->pid); + sinfo(" priority=%d state=%d\n", tcb->sched_priority, tcb->task_state); + +#if CONFIG_NFILE_DESCRIPTORS > 0 + filelist = tcb->group->tg_filelist; + for (i = 0; i < CONFIG_NFILE_DESCRIPTORS; i++) + { + struct inode *inode = filelist->fl_files[i].f_inode; + if (inode) + { + sinfo(" fd=%d refcount=%d\n", + i, inode->i_crefs); + } + } +#endif + +#if CONFIG_NFILE_STREAMS > 0 + streamlist = tcb->group->tg_streamlist; + for (i = 0; i < CONFIG_NFILE_STREAMS; i++) + { + struct file_struct *filep = &streamlist->sl_streams[i]; + if (filep->fs_fd >= 0) + { +#if CONFIG_STDIO_BUFFER_SIZE > 0 + sinfo(" fd=%d nbytes=%d\n", + filep->fs_fd, + filep->fs_bufpos - filep->fs_bufstart); +#else + sinfo(" fd=%d\n", filep->fs_fd); +#endif + } + } +#endif +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _exit + * + * Description: + * This function causes the currently executing task to cease + * to exist. This is a special case of task_delete() where the task to + * be deleted is the currently executing task. It is more complex because + * a context switch must be perform to the next ready to run task. + * + ****************************************************************************/ + +void _exit(int status) +{ + struct tcb_s *tcb; + + /* Disable interrupts. They will be restored when the next + * task is started. + */ + + (void)up_irq_save(); + + sinfo("TCB=%p exiting\n", this_task()); + +#ifdef CONFIG_DUMP_ON_EXIT + sinfo("Other tasks:\n"); + sched_foreach(_up_dumponexit, NULL); +#endif + + /* Destroy the task at the head of the ready to run list. */ + + (void)task_exit(); + + /* Now, perform the context switch to the new ready-to-run task at the + * head of the list. + */ + + tcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously running + * task is closed down gracefully (data caches dump, MMU flushed) and + * set up the address environment for the new thread at the head of + * the ready-to-run list. + */ + + (void)group_addrenv(tcb); +#endif + + /* Then switch contexts */ + + up_fullcontextrestore(tcb->xcp.regs); + + /* up_fullcontextrestore() should not return but could if the software + * interrupts are disabled. + */ + + PANIC(); +} + diff --git a/arch/xtensa/src/common/xtensa_idle.c b/arch/xtensa/src/common/xtensa_idle.c new file mode 100644 index 0000000000..e48441d5b4 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_idle.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_idle.c + * + * Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "up_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + sched_process_timer(); +#else + + /* This would be an appropriate place to put some MCU-specific logic to + * sleep in a reduced power mode until an interrupt occurs to save power + */ + + /* This is a kludge that I still don't understand. The call to kmm_trysemaphore() + * in the os_start.c IDLE loop seems necessary for the good health of the IDLE + * loop. When the work queue is enabled, this logic is removed from the IDLE + * loop and it appears that we are somehow left idling with interrupts non- + * functional. The following should be no-op, it just disables then re-enables + * interrupts. But it fixes the problem and will stay here until I understand + * the problem/fix better. + * + * And no, the contents of the CP0 status register are not incorrect. But for + * some reason the status register needs to be re-written again on this thread + * for it to take effect. This might be a PIC32-only issue? + */ + +#ifdef CONFIG_SCHED_WORKQUEUE + irqstate_t flags = enter_critical_section(); + leave_critical_section(flags); +#endif +#endif +} diff --git a/arch/xtensa/src/common/xtensa_initialize.c b/arch/xtensa/src/common/xtensa_initialize.c new file mode 100644 index 0000000000..1fedf99149 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_initialize.c @@ -0,0 +1,261 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_initialize.c + * + * Copyright (C) 2011-2013, 2015-2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_calibratedelay + * + * Description: + * Delay loops are provided for short timing loops. This function, if + * enabled, will just wait for 100 seconds. Using a stopwatch, you can + * can then determine if the timing loops are properly calibrated. + * + ****************************************************************************/ + +#if defined(CONFIG_ARCH_CALIBRATION) && defined(CONFIG_DEBUG_FEATURES) +static void up_calibratedelay(void) +{ + int i; + + _warn("Beginning 100s delay\n"); + for (i = 0; i < 100; i++) + { + up_mdelay(1000); + } + + _warn("End 100s delay\n"); +} +#else +# define up_calibratedelay() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_initialize + * + * Description: + * up_initialize will be called once during OS initialization after the + * basic OS services have been initialized. The architecture specific + * details of initializing the OS will be handled here. Such things as + * setting up interrupt service routines, starting the clock, and + * registering device drivers are some of the things that are different + * for each processor and hardware platform. + * + * up_initialize is called after the OS initialized but before the user + * initialization logic has been started and before the libraries have + * been initialized. OS services and driver services are available. + * + ****************************************************************************/ + +void up_initialize(void) +{ + /* Initialize global variables */ + + g_current_regs = NULL; + + /* Calibrate the timing loop */ + + up_calibratedelay(); + + /* Add any extra memory fragments to the memory manager */ + + up_addregion(); + + /* Initialize the interrupt subsystem */ + + up_irqinitialize(); + +#ifdef CONFIG_PM + /* Initialize the power management subsystem. This MCU-specific function + * must be called *very* early in the initialization sequence *before* any + * other device drivers are initialized (since they may attempt to register + * with the power management subsystem). + */ + + up_pminitialize(); +#endif + +#ifdef CONFIG_ARCH_DMA + /* Initialize the DMA subsystem if the weak function up_dmainitialize has been + * brought into the build + */ + +#ifdef CONFIG_HAVE_WEAKFUNCTIONS + if (up_dmainitialize) +#endif + { + up_dmainitialize(); + } +#endif + + /* Initialize the system timer interrupt */ + +#if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS) + up_timer_initialize(); +#endif + + /* Register devices */ + +#if CONFIG_NFILE_DESCRIPTORS > 0 + +#if defined(CONFIG_DEV_NULL) + devnull_register(); /* Standard /dev/null */ +#endif + +#if defined(CONFIG_DEV_RANDOM) + devrandom_register(); /* Standard /dev/random */ +#endif + +#if defined(CONFIG_DEV_URANDOM) + devurandom_register(); /* Standard /dev/urandom */ +#endif + +#if defined(CONFIG_DEV_ZERO) + devzero_register(); /* Standard /dev/zero */ +#endif + +#if defined(CONFIG_DEV_LOOP) + loop_register(); /* Standard /dev/loop */ +#endif +#endif /* CONFIG_NFILE_DESCRIPTORS */ + +#if defined(CONFIG_SCHED_INSTRUMENTATION_BUFFER) && \ + defined(CONFIG_DRIVER_NOTE) + note_register(); /* Non-standard /dev/note */ +#endif + + /* Initialize the serial device driver */ + +#ifdef USE_SERIALDRIVER + up_serialinit(); +#endif + + /* Initialize the console device driver (if it is other than the standard + * serial driver). + */ + +#if defined(CONFIG_DEV_LOWCONSOLE) + lowconsole_init(); +#elif defined(CONFIG_CONSOLE_SYSLOG) + syslog_console_init(); +#elif defined(CONFIG_RAMLOG_CONSOLE) + ramlog_consoleinit(); +#endif + +#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_PSEUDOTERM_SUSV1) + /* Register the master pseudo-terminal multiplexor device */ + + (void)ptmx_register(); +#endif + + /* Early initialization of the system logging device. Some SYSLOG channel + * can be initialized early in the initialization sequence because they + * depend on only minimal OS initialization. + */ + + syslog_initialize(SYSLOG_INIT_EARLY); + +#if defined(CONFIG_CRYPTO) + /* Initialize the HW crypto and /dev/crypto */ + + up_cryptoinitialize(); +#endif + +#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_CRYPTO_CRYPTODEV) + devcrypto_register(); +#endif + +#ifndef CONFIG_NETDEV_LATEINIT + /* Initialize the network */ + + up_netinitialize(); +#endif + +#ifdef CONFIG_NETDEV_LOOPBACK + /* Initialize the local loopback device */ + + (void)localhost_initialize(); +#endif + +#ifdef CONFIG_NET_TUN + /* Initialize the TUN device */ + + (void)tun_initialize(); +#endif + +#ifdef CONFIG_NETDEV_TELNET + /* Initialize the Telnet session factory */ + + (void)telnet_initialize(); +#endif + + /* Initialize USB -- device and/or host */ + + up_usbinitialize(); + board_autoled_on(LED_IRQSENABLED); +} diff --git a/arch/xtensa/src/common/xtensa_interruptcontext.c b/arch/xtensa/src/common/xtensa_interruptcontext.c new file mode 100644 index 0000000000..c6d83d05e0 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_interruptcontext.c @@ -0,0 +1,70 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_interruptcontext.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "up_internal.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_interrupt_context + * + * Description: Return true is we are currently executing in + * the interrupt handler context. + ****************************************************************************/ + +bool up_interrupt_context(void) +{ + return g_current_regs != NULL; +} diff --git a/arch/xtensa/src/common/xtensa_lowputs.c b/arch/xtensa/src/common/xtensa_lowputs.c new file mode 100644 index 0000000000..764f8393a6 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_lowputs.c @@ -0,0 +1,74 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_lowputs.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_lowputs + * + * Description: + * This is a low-level helper function used to support debug. + * + ****************************************************************************/ + +void up_lowputs(const char *str) +{ + while (*str) + { + up_lowputc(*str++); + } +} diff --git a/arch/xtensa/src/common/xtensa_mdelay.c b/arch/xtensa/src/common/xtensa_mdelay.c new file mode 100644 index 0000000000..f6b728bcc6 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_mdelay.c @@ -0,0 +1,90 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_mdelay.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_mdelay + * + * Description: + * Delay inline for the requested number of milliseconds. + * *** NOT multi-tasking friendly *** + * + * ASSUMPTIONS: + * The setting CONFIG_BOARD_LOOPSPERMSEC has been calibrated + * + ****************************************************************************/ + +void up_mdelay(unsigned int milliseconds) +{ + volatile int i; + volatile int j; + + for (i = 0; i < milliseconds; i++) + { + for (j = 0; j < CONFIG_BOARD_LOOPSPERMSEC; j++) + { + } + } +} diff --git a/arch/xtensa/src/common/xtensa_modifyreg16.c b/arch/xtensa/src/common/xtensa_modifyreg16.c new file mode 100644 index 0000000000..98a51c86ba --- /dev/null +++ b/arch/xtensa/src/common/xtensa_modifyreg16.c @@ -0,0 +1,85 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_modifyreg16.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "up_arch.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: modifyreg16 + * + * Description: + * Atomically modify the specified bits in a memory mapped register + * + ****************************************************************************/ + +void modifyreg16(unsigned int addr, uint16_t clearbits, uint16_t setbits) +{ + irqstate_t flags; + uint16_t regval; + + flags = enter_critical_section(); + regval = getreg16(addr); + regval &= ~clearbits; + regval |= setbits; + putreg16(regval, addr); + leave_critical_section(flags); +} diff --git a/arch/xtensa/src/common/xtensa_modifyreg32.c b/arch/xtensa/src/common/xtensa_modifyreg32.c new file mode 100644 index 0000000000..5619e6f272 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_modifyreg32.c @@ -0,0 +1,85 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_modifyreg32.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "up_arch.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: modifyreg32 + * + * Description: + * Atomically modify the specified bits in a memory mapped register + * + ****************************************************************************/ + +void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits) +{ + irqstate_t flags; + uint32_t regval; + + flags = enter_critical_section(); + regval = getreg32(addr); + regval &= ~clearbits; + regval |= setbits; + putreg32(regval, addr); + leave_critical_section(flags); +} diff --git a/arch/xtensa/src/common/xtensa_modifyreg8.c b/arch/xtensa/src/common/xtensa_modifyreg8.c new file mode 100644 index 0000000000..e3bc73843e --- /dev/null +++ b/arch/xtensa/src/common/xtensa_modifyreg8.c @@ -0,0 +1,85 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_modifyreg8.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "up_arch.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: modifyreg8 + * + * Description: + * Atomically modify the specified bits in a memory mapped register + * + ****************************************************************************/ + +void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits) +{ + irqstate_t flags; + uint8_t regval; + + flags = enter_critical_section(); + regval = getreg8(addr); + regval &= ~clearbits; + regval |= setbits; + putreg8(regval, addr); + leave_critical_section(flags); +} diff --git a/arch/xtensa/src/common/xtensa_puts.c b/arch/xtensa/src/common/xtensa_puts.c new file mode 100644 index 0000000000..47675baa8d --- /dev/null +++ b/arch/xtensa/src/common/xtensa_puts.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_puts.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_puts + * + * Description: + * This is a low-level helper function used to support debug. + * + ****************************************************************************/ + +void up_puts(const char *str) +{ + while (*str) + { + up_putc(*str++); + } +} diff --git a/arch/xtensa/src/common/xtensa_releasestack.c b/arch/xtensa/src/common/xtensa_releasestack.c new file mode 100644 index 0000000000..76b3164bce --- /dev/null +++ b/arch/xtensa/src/common/xtensa_releasestack.c @@ -0,0 +1,122 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_releasestack.c + * + * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "up_internal.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_release_stack + * + * Description: + * A task has been stopped. Free all stack related resources retained in + * the defunct TCB. + * + * Input Parmeters + * - dtcb: The TCB containing information about the stack to be released + * - ttype: The thread type. This may be one of following (defined in + * include/nuttx/sched.h): + * + * TCB_FLAG_TTYPE_TASK Normal user task + * TCB_FLAG_TTYPE_PTHREAD User pthread + * TCB_FLAG_TTYPE_KERNEL Kernel thread + * + * This thread type is normally available in the flags field of the TCB, + * however, there are certain error recovery contexts where the TCB may + * not be fully initialized when up_release_stack is called. + * + * If CONFIG_BUILD_KERNEL is defined, then this thread type may affect + * how the stack is freed. For example, kernel thread stacks may have + * been allocated from protected kernel memory. Stacks for user tasks + * and threads must have come from memory that is accessible to user + * code. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_release_stack(FAR struct tcb_s *dtcb, uint8_t ttype) +{ + /* Is there a stack allocated? */ + + if (dtcb->stack_alloc_ptr) + { +#if defined(CONFIG_BUILD_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP) + /* Use the kernel allocator if this is a kernel thread */ + + if (ttype == TCB_FLAG_TTYPE_KERNEL) + { + sched_kfree(dtcb->stack_alloc_ptr); + } + else +#endif + { + /* Use the user-space allocator if this is a task or pthread */ + + sched_ufree(dtcb->stack_alloc_ptr); + } + + /* Mark the stack freed */ + + dtcb->stack_alloc_ptr = NULL; + } + + /* The size of the allocated stack is now zero */ + + dtcb->adj_stack_size = 0; +} diff --git a/arch/xtensa/src/common/xtensa_stackframe.c b/arch/xtensa/src/common/xtensa_stackframe.c new file mode 100644 index 0000000000..f0a1da976d --- /dev/null +++ b/arch/xtensa/src/common/xtensa_stackframe.c @@ -0,0 +1,143 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_stackframe.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Macros + ****************************************************************************/ +/* XTENSA requires at least a 4-byte stack alignment. For floating point use, + * however, the stack must be aligned to 8-byte addresses. + */ + +#ifdef CONFIG_LIBC_FLOATINGPOINT +# define STACK_ALIGNMENT 8 +#else +# define STACK_ALIGNMENT 4 +#endif + +/* Stack alignment macros */ + +#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1) +#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK) +#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_stack_frame + * + * Description: + * Allocate a stack frame in the TCB's stack to hold thread-specific data. + * This function may be called anytime after up_create_stack() or + * up_use_stack() have been called but before the task has been started. + * + * Thread data may be kept in the stack (instead of in the TCB) if it is + * accessed by the user code directly. This includes such things as + * argv[]. The stack memory is guaranteed to be in the same protection + * domain as the thread. + * + * The following TCB fields will be re-initialized: + * + * - adj_stack_size: Stack size after removal of the stack frame from + * the stack + * - adj_stack_ptr: Adjusted initial stack pointer after the frame has + * been removed from the stack. This will still be the initial value + * of the stack pointer when the task is started. + * + * Inputs: + * - tcb: The TCB of new task + * - frame_size: The size of the stack frame to allocate. + * + * Returned Value: + * - A pointer to bottom of the allocated stack frame. NULL will be + * returned on any failures. The alignment of the returned value is + * the same as the alignment of the stack itself. + * + ****************************************************************************/ + +FAR void *up_stack_frame(FAR struct tcb_s *tcb, size_t frame_size) +{ + uintptr_t topaddr; + + /* Align the frame_size */ + + frame_size = STACK_ALIGN_UP(frame_size); + + /* Is there already a stack allocated? Is it big enough? */ + + if (!tcb->stack_alloc_ptr || tcb->adj_stack_size <= frame_size) + { + return NULL; + } + + /* Save the adjusted stack values in the struct tcb_s */ + + topaddr = (uintptr_t)tcb->adj_stack_ptr - frame_size; + tcb->adj_stack_ptr = (FAR void *)topaddr; + tcb->adj_stack_size -= frame_size; + + /* Reset the initial stack pointer */ + + tcb->xcp.regs[REG_SP] = (uint32_t)tcb->adj_stack_ptr; + + /* And return the pointer to the allocated region */ + + return (FAR void *)(topaddr + sizeof(uint32_t)); +} + diff --git a/arch/xtensa/src/common/xtensa_udelay.c b/arch/xtensa/src/common/xtensa_udelay.c new file mode 100644 index 0000000000..f18be5b891 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_udelay.c @@ -0,0 +1,129 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_udelay.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CONFIG_BOARD_LOOPSPER100USEC ((CONFIG_BOARD_LOOPSPERMSEC+5)/10) +#define CONFIG_BOARD_LOOPSPER10USEC ((CONFIG_BOARD_LOOPSPERMSEC+50)/100) +#define CONFIG_BOARD_LOOPSPERUSEC ((CONFIG_BOARD_LOOPSPERMSEC+500)/1000) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_udelay + * + * Description: + * Delay inline for the requested number of microseconds. NOTE: Because + * of all of the setup, several microseconds will be lost before the actual + * timing looop begins. Thus, the delay will always be a few microseconds + * longer than requested. + * + * *** NOT multi-tasking friendly *** + * + * ASSUMPTIONS: + * The setting CONFIG_BOARD_LOOPSPERMSEC has been calibrated + * + ****************************************************************************/ + +void up_udelay(useconds_t microseconds) +{ + volatile int i; + + /* We'll do this a little at a time because we expect that the + * CONFIG_BOARD_LOOPSPERUSEC is very inaccurate during to truncation in + * the divisions of its calculation. We'll use the largest values that + * we can in order to prevent significant error buildup in the loops. + */ + + while (microseconds > 1000) + { + for (i = 0; i < CONFIG_BOARD_LOOPSPERMSEC; i++) + { + } + microseconds -= 1000; + } + + while (microseconds > 100) + { + for (i = 0; i < CONFIG_BOARD_LOOPSPER100USEC; i++) + { + } + microseconds -= 100; + } + + while (microseconds > 10) + { + for (i = 0; i < CONFIG_BOARD_LOOPSPER10USEC; i++) + { + } + microseconds -= 10; + } + + while (microseconds > 0) + { + for (i = 0; i < CONFIG_BOARD_LOOPSPERUSEC; i++) + { + } + microseconds--; + } +} diff --git a/arch/xtensa/src/common/xtensa_usestack.c b/arch/xtensa/src/common/xtensa_usestack.c new file mode 100644 index 0000000000..9b35e2d0a9 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_usestack.c @@ -0,0 +1,152 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_usestack.c + * + * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* XTENSA requires at least a 4-byte stack alignment. For floating point use, + * however, the stack must be aligned to 8-byte addresses. + */ + +#ifdef CONFIG_LIBC_FLOATINGPOINT +# define STACK_ALIGNMENT 8 +#else +# define STACK_ALIGNMENT 4 +#endif + +/* Stack alignment macros */ + +#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1) +#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK) +#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_use_stack + * + * Description: + * Setup up stack-related information in the TCB using pre-allocated stack + * memory. This function is called only from task_init() when a task or + * kernel thread is started (never for pthreads). + * + * The following TCB fields must be initialized: + * + * - adj_stack_size: Stack size after adjustment for hardware, + * processor, etc. This value is retained only for debug + * purposes. + * - stack_alloc_ptr: Pointer to allocated stack + * - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The + * initial value of the stack pointer. + * + * Inputs: + * - tcb: The TCB of new task + * - stack_size: The allocated stack size. + * + * NOTE: Unlike up_stack_create() and up_stack_release, this function + * does not require the task type (ttype) parameter. The TCB flags will + * always be set to provide the task type to up_use_stack() if it needs + * that information. + * + ****************************************************************************/ + +int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size) +{ + size_t top_of_stack; + size_t size_of_stack; + + /* Is there already a stack allocated? */ + + if (tcb->stack_alloc_ptr) + { + /* Yes.. Release the old stack allocation */ + + up_release_stack(tcb, tcb->flags & TCB_FLAG_TTYPE_MASK); + } + + /* Save the new stack allocation */ + + tcb->stack_alloc_ptr = stack; + + /* XTENSA uses a push-down stack: the stack grows toward loweraddresses in + * memory. The stack pointer register, points to the lowest, valid work + * address (the "top" of the stack). Items on the stack are referenced + * as positive word offsets from sp. + */ + + top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4; + + /* The XTENSA stack must be aligned at word (4 byte) or double word (8 byte) + * boundaries. If necessary top_of_stack must be rounded down to the + * next boundary + */ + + top_of_stack = STACK_ALIGN_DOWN(top_of_stack); + size_of_stack = top_of_stack - (uint32_t)tcb->stack_alloc_ptr + 4; + + /* Save the adjusted stack values in the struct tcb_s */ + + tcb->adj_stack_ptr = (uint32_t *)top_of_stack; + tcb->adj_stack_size = size_of_stack; + + return OK; +} diff --git a/arch/xtensa/src/lx6/Kconfig b/arch/xtensa/src/lx6/Kconfig new file mode 100644 index 0000000000..8ccb4fe392 --- /dev/null +++ b/arch/xtensa/src/lx6/Kconfig @@ -0,0 +1,9 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_LX6 + +endif # ARCH_LX6 + diff --git a/arch/xtensa/src/lx6/Make.defs b/arch/xtensa/src/lx6/Make.defs new file mode 100644 index 0000000000..06ba9cad86 --- /dev/null +++ b/arch/xtensa/src/lx6/Make.defs @@ -0,0 +1,67 @@ +############################################################################ +# arch/xtensa/src/lx6/Make.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# The start-up, "head", file + +HEAD_ASRC = + +# Common XTENSA files (arch/xtensa/src/common) + +CMN_ASRCS = +CMN_CSRCS = xtensa_allocateheap.c xtensa_createstack.c xtensa_exit.c +CMN_CSRCS += xtensa_idle.c xtensa_initialize.c xtensa_interruptcontext.c +CMN_CSRCS += xtensa_lowputs.c xtensa_mdelay.c xtensa_modifyreg8.c +CMN_CSRCS += xtensa_modifyreg16.c xtensa_modifyreg32.c xtensa_puts.c +CMN_CSRCS += xtensa_releasestack.c xtensa_stackframe.c xtensa_udelay.c +CMN_CSRCS += xtensa_usestack.c + +# Configuration-dependent common XTENSA files + +# Use of common/xtensa_etherstub.c is deprecated. The preferred mechanism +# is to use CONFIG_NETDEV_LATEINIT=y to suppress the call to up_netinitialize() +# in xtensa_initialize.c. Then this stub would not be needed. + +ifneq ($(CONFIG_LX6_ETHERNET),y) +ifeq ($(CONFIG_NET),y) + CMN_CSRCS += xtensa_etherstub.c +endif +endif + +# Required LX6 files (arch/xtensa/src/lx6) + +CHIP_ASRCS = +CHIP_CSRCS = + +# Configuration-dependent LX6 files -- GitLab From 852330876b5aeff8ea777597eb5185ffe4e03eab Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 12 Oct 2016 14:50:28 -0600 Subject: [PATCH 055/734] arch/xtensa: A little more ESP32 configuration logic --- arch/Kconfig | 7 ++ arch/xtensa/include/esp32/chip.h | 77 +++++++++++++++++++++ arch/xtensa/include/esp32/irq.h | 85 ++++++++++++++++++++++++ arch/xtensa/include/irq.h | 17 ++++- arch/xtensa/include/lx6/chip.h | 7 -- arch/xtensa/include/lx6/irq.h | 2 - arch/xtensa/src/esp32/Kconfig | 9 +++ arch/xtensa/src/{lx6 => esp32}/Make.defs | 0 arch/xtensa/src/lx6/Kconfig | 26 +++++++- 9 files changed, 217 insertions(+), 13 deletions(-) create mode 100644 arch/xtensa/include/esp32/chip.h create mode 100644 arch/xtensa/include/esp32/irq.h create mode 100644 arch/xtensa/src/esp32/Kconfig rename arch/xtensa/src/{lx6 => esp32}/Make.defs (100%) diff --git a/arch/Kconfig b/arch/Kconfig index 319419bb2d..ee252d2cbd 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -67,6 +67,11 @@ config ARCH_X86 ---help--- Intel x86 architectures. +config ARCH_XTENSA + bool "Xtensa" + ---help--- + Cadence Cadence® Tensilica® Xtensa® actictures. + config ARCH_Z16 bool "ZNEO" select ARCH_HAVE_HEAP2 @@ -91,6 +96,7 @@ config ARCH default "renesas" if ARCH_RENESAS default "sim" if ARCH_SIM default "x86" if ARCH_X86 + default "xtensa" if ARCH_XTENSA default "z16" if ARCH_Z16 default "z80" if ARCH_Z80 @@ -102,6 +108,7 @@ source arch/rgmp/Kconfig source arch/renesas/Kconfig source arch/sim/Kconfig source arch/x86/Kconfig +source arch/xtensa/Kconfig source arch/z16/Kconfig source arch/z80/Kconfig diff --git a/arch/xtensa/include/esp32/chip.h b/arch/xtensa/include/esp32/chip.h new file mode 100644 index 0000000000..95e9e2cac3 --- /dev/null +++ b/arch/xtensa/include/esp32/chip.h @@ -0,0 +1,77 @@ +/**************************************************************************** + * arch/xtensa/include/esp32/chip.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_INCLUDE_ESP32_CHIP_H +#define __ARCH_XTENSA_INCLUDE_ESP32_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_INCLUDE_ESP32_CHIP_H */ diff --git a/arch/xtensa/include/esp32/irq.h b/arch/xtensa/include/esp32/irq.h new file mode 100644 index 0000000000..d67ea04794 --- /dev/null +++ b/arch/xtensa/include/esp32/irq.h @@ -0,0 +1,85 @@ +/**************************************************************************** + * arch/xtensa/include/esp32/irq.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_XTENSA_INCLUDE_ESP32_IRQ_H +#define __ARCH_XTENSA_INCLUDE_ESP32_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_INCLUDE_ESP32_IRQ_H */ diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index d2af5ba4e4..19739e7944 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -48,9 +48,22 @@ #include -/* Include chip-specific IRQ definitions (including IRQ numbers) */ +/* Include architecture-specific IRQ definitions */ -#include +#ifdef CONFIG_ARCH_CHIP_LX6 +# include + +/* Include implementation-specific IRQ definitions (including IRQ numbers) */ + +# ifdef CONFIG_ARCH_CHIP_ESP32 +# include +# else +# error Unknown LX6 implementation +# endif + +#else +# error Unknown XTENSA architecture +#endif /**************************************************************************** * Pre-processor Definitions diff --git a/arch/xtensa/include/lx6/chip.h b/arch/xtensa/include/lx6/chip.h index 060d99e945..a3cb0e3e84 100644 --- a/arch/xtensa/include/lx6/chip.h +++ b/arch/xtensa/include/lx6/chip.h @@ -45,13 +45,6 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Configuration ************************************************************/ - -#if defined(CONFIG_ARCH_CHIP_LX6) -/* To be provided */ -#else -# error "Unrecognized LX6 device -#endif /**************************************************************************** * Public Types diff --git a/arch/xtensa/include/lx6/irq.h b/arch/xtensa/include/lx6/irq.h index ec2b218f58..ddc87e0c2b 100644 --- a/arch/xtensa/include/lx6/irq.h +++ b/arch/xtensa/include/lx6/irq.h @@ -44,8 +44,6 @@ * Included Files ****************************************************************************/ -#include - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/arch/xtensa/src/esp32/Kconfig b/arch/xtensa/src/esp32/Kconfig new file mode 100644 index 0000000000..8ccb4fe392 --- /dev/null +++ b/arch/xtensa/src/esp32/Kconfig @@ -0,0 +1,9 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_LX6 + +endif # ARCH_LX6 + diff --git a/arch/xtensa/src/lx6/Make.defs b/arch/xtensa/src/esp32/Make.defs similarity index 100% rename from arch/xtensa/src/lx6/Make.defs rename to arch/xtensa/src/esp32/Make.defs diff --git a/arch/xtensa/src/lx6/Kconfig b/arch/xtensa/src/lx6/Kconfig index 8ccb4fe392..073954b7d6 100644 --- a/arch/xtensa/src/lx6/Kconfig +++ b/arch/xtensa/src/lx6/Kconfig @@ -3,7 +3,29 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -if ARCH_LX6 +if ARCH_CHIP_LX6 -endif # ARCH_LX6 +choice + prompt "LX6 implementation" + default ARCH_CHIP_ESP32 +config ARCH_CHIP_ESP32 + bool "Expressif ESP32" + ---help--- + The ESP32 is a dual-core system with two Harvard Architecture Xtensa + LX6 CPUs. All embedded memory, external memory and peripherals are + located on the data bus and/or the instruction bus of these CPUs. + With some minor exceptions the address mapping of two CPUs is + symmetric, meaning they use the same addresses to access the same + memory. Multiple peripherals in the system can access embedded + memory via DMA. + + The two CPUs are named "PRO_CPU" and "APP_CPU" (for "protocol" and + "application"), however for most purposes the two CPUs are + interchangeable. + +endchoice # LX6 implementation + +source arch/xtensa/src/esp32/Kconfig + +endif # ARCH_CHIP_LX6 -- GitLab From 52b1ca87477a593b125d75e236bcecc9a83e61c2 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 12 Oct 2016 15:27:34 -0600 Subject: [PATCH 056/734] configs/esp32-core: Add basic directory to support the ESP32 Core board V2 --- arch/README.txt | 15 +++++++++++++ configs/Kconfig | 19 +++++++++++----- configs/README.txt | 8 +++++++ configs/esp32-core/Kconfig | 8 +++++++ configs/esp32-core/README.txt | 41 +++++++++++++++++++++++++++++++++++ 5 files changed, 85 insertions(+), 6 deletions(-) create mode 100644 configs/esp32-core/Kconfig create mode 100644 configs/esp32-core/README.txt diff --git a/arch/README.txt b/arch/README.txt index bd49fb31a7..ffdb4ba317 100644 --- a/arch/README.txt +++ b/arch/README.txt @@ -244,6 +244,21 @@ arch/x86 - Intel x86 architectures arch/x86/include/i486 and arch/x86/src/i486 arch/x86/include/qemu and arch/x86/src/qemu +arch/xtensa + + Implementations based on the Cadence® Tensilica® Xtensa® processors, + such as the Xtensa LX6 dataplane processing units (DPUs). At + present, this includes the following subdirectories: + + Common XTENSA support: + arch/xtensa/include and arch/xtensa/src/common + + LX6 DPU support: + arch/xtensa/include/lx6 and arch/xtensa/xtensa/lx6 + + Expressif ESP32 implemenation of the LX6 DPU: + arch/xtensa/include/esp32 and arch/xtensa/xtensa/esp32 + arch/z16 - ZiLOG 16-bit processors This directory holds related, 16-bit architectures from ZiLOG. At present, this includes the following subdirectories: diff --git a/configs/Kconfig b/configs/Kconfig index 2b629c1a4f..2506d8c081 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -170,14 +170,17 @@ config ARCH_BOARD_EKKLM3S9B96 TI/Stellaris EKK-LM3S9B96 board. This board is based on the an EKK-LM3S9B96 which is a Cortex-M3. -config ARCH_BOARD_EZ80F910200KITG - bool "ZiLOG ez80f910200kitg development kit" - depends on ARCH_CHIP_EZ80F91 +config ARCH_BOARD_ESP32CORE + bool "Expressif ESP32 Core board V2" + depends on ARCH_CHIP_ESP32 select ARCH_HAVE_LEDS ---help--- - ez80Acclaim! Microcontroller. This port use the ZiLOG ez80f910200kitg - development kit, eZ80F091 part, and the Zilog ZDS-II Windows command line - tools. The development environment is Cygwin under WinXP. + The ESP32 is a dual-core system from Expressif with two Harvard + architecture Xtensa LX6 CPUs. All embedded memory, external memory + and peripherals are located on the data bus and/or the instruction + bus of these CPUs. With some minor exceptions, the address mapping + of two CPUs is symmetric, meaning they use the same addresses to + access the same memory. config ARCH_BOARD_EZ80F910200ZCO bool "ZiLOG ez80f910200zco development kit" @@ -1383,6 +1386,7 @@ config ARCH_BOARD default "efm32-g8xx-stk" if ARCH_BOARD_EFM32G8XXSTK default "efm32gg-stk3700" if ARCH_BOARD_EFM32GG_STK3700 default "ekk-lm3s9b96" if ARCH_BOARD_EKKLM3S9B96 + default "esp32-core" if ARCH_BOARD_ESP32CORE default "ez80f910200kitg" if ARCH_BOARD_EZ80F910200KITG default "ez80f910200zco" if ARCH_BOARD_EZ80F910200ZCO default "fire-stm32v2" if ARCH_BOARD_FIRE_STM32 @@ -1581,6 +1585,9 @@ endif if ARCH_BOARD_EKKLM3S9B96 source "configs/ekk-lm3s9b96/Kconfig" endif +if ARCH_BOARD_ESP32CORE +source "configs/esp32-core/Kconfig" +endif if ARCH_BOARD_EZ80F910200KITG source "configs/ez80f910200kitg/Kconfig" endif diff --git a/configs/README.txt b/configs/README.txt index 8bf546a298..fa34391328 100644 --- a/configs/README.txt +++ b/configs/README.txt @@ -246,6 +246,14 @@ configs/ekk-lm3s9b96 TI/Stellaris EKK-LM3S9B96 board. This board is based on the an EKK-LM3S9B96 which is a Cortex-M3. +configs/esp-core + The ESP32 is a dual-core system from Expressif with two Harvard + architecture Xtensa LX6 CPUs. All embedded memory, external memory and + nd peripherals are located on the data bus and/or the instruction bus of + bus of these CPUs. With some minor exceptions, the address mapping of two + CPUs is symmetric, meaning they use the same addresses to access the same + memory. + configs/ez80f0910200kitg ez80Acclaim! Microcontroller. This port use the Zilog ez80f0910200kitg development kit, eZ80F091 part, and the Zilog ZDS-II Windows command line diff --git a/configs/esp32-core/Kconfig b/configs/esp32-core/Kconfig new file mode 100644 index 0000000000..719b83d1a5 --- /dev/null +++ b/configs/esp32-core/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_ESP32CORE + +endif # ARCH_BOARD_ESP32CORE diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt new file mode 100644 index 0000000000..84fd259b58 --- /dev/null +++ b/configs/esp32-core/README.txt @@ -0,0 +1,41 @@ +README for the Expressif ESP32 Core board (V2) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + The ESP32 is a dual-core system from Expressif with two Harvard + architecture Xtensa LX6 CPUs. All embedded memory, external memory and + peripherals are located on the data bus and/or the instruction bus of + these CPUs. With some minor exceptions, the address mapping of two CPUs + is symmetric, meaning they use the same addresses to access the same + memory. Multiple peripherals in the system can access embedded memory via + DMA. + + The two CPUs are named "PRO_CPU" and "APP_CPU" (for "protocol" and + "application"), however for most purposes the two CPUs are + interchangeable. + + Features: + + * Address Space + - Symmetric address mapping + - 4 GB (32-bit) address space for both data bus and instruction bus + - 1296 KB embedded memory address space + - 19704 KB external memory address space + - 512 KB peripheral address space + - Some embedded and external memory regions can be accessed by either + data bus or instruction bus + - 328 KB DMA address space + * Embedded Memory + - 448 KB Internal ROM + - 520 KB Internal SRAM + - 8 KB RTC FAST Memory + - 8 KB RTC SLOW Memory + * External Memory + Off-chip SPI memory can be mapped into the available address space as + external memory. Parts of the embedded memory can be used as transparent + cache for this external memory. + - Supports up to 16 MB off-Chip SPI Flash. + - Supports up to 8 MB off-Chip SPI SRAM. + * Peripherals + - 41 peripherals + * DMA + - 13 modules are capable of DMA operation \ No newline at end of file -- GitLab From 38d9436e42ca01e79651d09708faa7e6d68942d2 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 13 Oct 2016 11:34:29 -0600 Subject: [PATCH 057/734] ESP32 Core board: Add a dummy board Makefile --- configs/esp32-core/src/.gitignore | 2 ++ configs/esp32-core/src/Makefile | 41 +++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) create mode 100644 configs/esp32-core/src/.gitignore create mode 100644 configs/esp32-core/src/Makefile diff --git a/configs/esp32-core/src/.gitignore b/configs/esp32-core/src/.gitignore new file mode 100644 index 0000000000..726d936e1e --- /dev/null +++ b/configs/esp32-core/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/configs/esp32-core/src/Makefile b/configs/esp32-core/src/Makefile new file mode 100644 index 0000000000..017d00f499 --- /dev/null +++ b/configs/esp32-core/src/Makefile @@ -0,0 +1,41 @@ +############################################################################ +# configs//srp32-core/Makefile +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = + +include $(TOPDIR)/configs/Board.mk -- GitLab From ae5ada0ec5284cff5f0bb80184d7211369d8d284 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 13 Oct 2016 14:22:27 -0600 Subject: [PATCH 058/734] ESP32 Core: Add a dummy board.h header file --- configs/esp32-core/include/board.h | 39 ++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 configs/esp32-core/include/board.h diff --git a/configs/esp32-core/include/board.h b/configs/esp32-core/include/board.h new file mode 100644 index 0000000000..d07ba907cf --- /dev/null +++ b/configs/esp32-core/include/board.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * configs/esp32-core/include/board.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIGS_ESP32_CORE_INCLUDE_BOARD_H +#define __CONFIGS_ESP32_CORE_INCLUDE_BOARD_H + +#endif /* __CONFIGS_ESP32_CORE_INCLUDE_BOARD_H */ -- GitLab From 25331aeb631b1a72c0d60e6acd3b7137ebb82dd8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 13 Oct 2016 14:37:28 -0600 Subject: [PATCH 059/734] ESP32 Core: Add an NSH configuration for build testing --- arch/Kconfig | 2 +- arch/xtensa/Kconfig | 23 +- configs/esp32-core/nsh/Make.defs | 113 +++++ configs/esp32-core/nsh/defconfig | 750 +++++++++++++++++++++++++++++++ configs/esp32-core/nsh/setenv.sh | 80 ++++ 5 files changed, 959 insertions(+), 9 deletions(-) create mode 100644 configs/esp32-core/nsh/Make.defs create mode 100644 configs/esp32-core/nsh/defconfig create mode 100644 configs/esp32-core/nsh/setenv.sh diff --git a/arch/Kconfig b/arch/Kconfig index ee252d2cbd..dd873f9723 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -70,7 +70,7 @@ config ARCH_X86 config ARCH_XTENSA bool "Xtensa" ---help--- - Cadence Cadence® Tensilica® Xtensa® actictures. + Cadence® Tensilica® Xtensa® actictures. config ARCH_Z16 bool "ZNEO" diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index d740939c1e..3ba3a48ec3 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -7,24 +7,31 @@ if ARCH_XTENSA choice prompt "XTENSA architecture selection" - default ARCH_CHIP_LX6 + default ARCH_CHIP_ESP32 -config ARCH_CHIP_LX6 - bool "LX6 DPU" - select ARCH_LX6 +config ARCH_CHIP_ESP32 + bool "Expressif ESP32" + select ARCH_FAMILY_LX6 ---help--- - Cadence® Tensilica® Xtensa® LX6 data plane processing unit (DPU). - The LX6 is a configurable and extensible processor core. + The ESP32 is a dual-core system from Expressif with two Harvard + architecture Xtensa LX6 CPUs. All embedded memory, external memory + and peripherals are located on the data bus and/or the instruction + bus of these CPUs. With some minor exceptions, the address mapping + of two CPUs is symmetric, meaning they use the same addresses to + access the same memory. endchoice # XTENSA chip selection -config ARCH_LX6 +config ARCH_FAMILY_LX6 bool default n + ---help--- + Cadence® Tensilica® Xtensa® LX6 data plane processing unit (DPU). + The LX6 is a configurable and extensible processor core. config ARCH_CHIP string - default "lx6" if ARCH_LX6 + default "esp32" if ARCH_CHIP_ESP32 source arch/xtensa/src/lx6/Kconfig diff --git a/configs/esp32-core/nsh/Make.defs b/configs/esp32-core/nsh/Make.defs new file mode 100644 index 0000000000..02251501c8 --- /dev/null +++ b/configs/esp32-core/nsh/Make.defs @@ -0,0 +1,113 @@ +############################################################################ +# configs/stm32f4discovery/nsh/Make.defs +# +# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/esp32-core/nsh/defconfig b/configs/esp32-core/nsh/defconfig new file mode 100644 index 0000000000..cee088cc3e --- /dev/null +++ b/configs/esp32-core/nsh/defconfig @@ -0,0 +1,750 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +# CONFIG_HOST_LINUX is not set +# CONFIG_HOST_OSX is not set +CONFIG_HOST_WINDOWS=y +# CONFIG_HOST_OTHER is not set +# CONFIG_WINDOWS_NATIVE is not set +CONFIG_WINDOWS_CYGWIN=y +# CONFIG_WINDOWS_MSYS is not set +# CONFIG_WINDOWS_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +# CONFIG_ARCH_HAVE_STACKCHECK is not set +# CONFIG_ARCH_HAVE_HEAPCHECK is not set +# CONFIG_DEBUG_SYMBOLS is not set +# CONFIG_ARCH_HAVE_CUSTOMOPT is not set +# CONFIG_DEBUG_NOOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +CONFIG_ARCH_XTENSA=y +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_CHIP="esp32" +CONFIG_ARCH_CHIP_ESP32=y +CONFIG_ARCH_FAMILY_LX6=y + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +# CONFIG_ARCH_HAVE_IRQPRIO is not set +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +# CONFIG_ARCH_HAVE_VFORK is not set +# CONFIG_ARCH_HAVE_MMU is not set +# CONFIG_ARCH_HAVE_MPU is not set +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +# CONFIG_ARCH_HAVE_RESET is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +# CONFIG_ARCH_HAVE_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=16717 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +# CONFIG_ARCH_HAVE_INTERRUPTSTACK is not set +# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_SIZE=114688 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_ESP32CORE=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="esp32-core" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +# CONFIG_LIB_BOARDCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Clocks and Timers +# +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2011 +CONFIG_START_MONTH=12 +CONFIG_START_DAY=6 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_WDOG_INTRESERVE=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=31 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_HPWORK is not set +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +# CONFIG_ARCH_HAVE_I2CRESET is not set +# CONFIG_I2C is not set +CONFIG_SPI=y +# CONFIG_SPI_SLAVE is not set +CONFIG_SPI_EXCHANGE=y +# CONFIG_SPI_CMDDATA is not set +# CONFIG_SPI_CALLBACK is not set +# CONFIG_SPI_HWFEATURES is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set +# CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +# CONFIG_SERIAL_CONSOLE is not set +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +# CONFIG_MCU_SERIAL is not set +CONFIG_STANDARD_SERIAL=y +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +# CONFIG_SYSLOG_SERIAL_CONSOLE is not set +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +CONFIG_FS_READABLE=y +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +CONFIG_FS_PROCFS=y +# CONFIG_FS_PROCFS_REGISTER is not set + +# +# Exclude individual procfs entries +# +# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set +# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=2 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +# CONFIG_ARCH_HAVE_TLS is not set +# CONFIG_LIBC_NETDB is not set +# CONFIG_NETDB_HOSTFILE is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +# CONFIG_CXX_NEWLONG is not set + +# +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_CXXTEST is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set +# CONFIG_FSUTILS_PASSWD is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_BAS is not set +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=64 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_NSH_MAXARGUMENTS=6 +# CONFIG_NSH_ARGCAT is not set +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_IFUPDOWN is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Configure Command Options +# +# CONFIG_NSH_CMDOPT_DF_H is not set +CONFIG_NSH_CODECS_BUFSIZE=128 +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_NSH_PROC_MOUNTPOINT="/proc" +CONFIG_NSH_FILEIOSIZE=512 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +# CONFIG_NSH_ARCHINIT is not set +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/esp32-core/nsh/setenv.sh b/configs/esp32-core/nsh/setenv.sh new file mode 100644 index 0000000000..d67e6fdc7d --- /dev/null +++ b/configs/esp32-core/nsh/setenv.sh @@ -0,0 +1,80 @@ +#!/bin/bash +# configs/stm32f4discovery/nsh/setenv.sh +# +# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the RIDE +# toolchain under windows. You will also have to edit this if you install +# the RIDE toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Raisonance/Ride/arm-gcc/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +#export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" +# You can this free toolchain here https://launchpad.net/gcc-arm-embedded +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" + +# These are the Cygwin paths to the locations where I installed the Atollic +# toolchain under windows. You will also have to edit this if you install +# the Atollic toolchain in any other location. /usr/bin is added before +# the Atollic bin path because there is are binaries named gcc.exe and g++.exe +# at those locations as well. +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +#export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH variable +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" -- GitLab From 43c46fd34c12615221bbca1cb615d1c976a3d1b6 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 13 Oct 2016 14:40:43 -0600 Subject: [PATCH 060/734] ESP32 Core: Add a dummy Toolchain.defs. Fix some cloning errors left in the NSH configuration. --- arch/xtensa/src/lx6/Toolchain.defs | 36 ++++++++++++++++++++++++++++++ configs/esp32-core/nsh/Make.defs | 15 +++++-------- configs/esp32-core/nsh/setenv.sh | 31 ++++--------------------- tools/sethost.sh | 0 4 files changed, 45 insertions(+), 37 deletions(-) create mode 100644 arch/xtensa/src/lx6/Toolchain.defs mode change 100644 => 100755 tools/sethost.sh diff --git a/arch/xtensa/src/lx6/Toolchain.defs b/arch/xtensa/src/lx6/Toolchain.defs new file mode 100644 index 0000000000..e58071c20d --- /dev/null +++ b/arch/xtensa/src/lx6/Toolchain.defs @@ -0,0 +1,36 @@ +############################################################################ +# arch/xtensa/src/lx6/Toolchain.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +CROSSDEV = xtensa-esp32- diff --git a/configs/esp32-core/nsh/Make.defs b/configs/esp32-core/nsh/Make.defs index 02251501c8..75a3287f6e 100644 --- a/configs/esp32-core/nsh/Make.defs +++ b/configs/esp32-core/nsh/Make.defs @@ -1,7 +1,7 @@ ############################################################################ -# configs/stm32f4discovery/nsh/Make.defs +# configs/esp32-core/nsh/Make.defs # -# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Copyright (C) 2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -35,7 +35,7 @@ include ${TOPDIR}/.config include ${TOPDIR}/tools/Config.mk -include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs +include ${TOPDIR}/arch/xtensa/src/lx6/Toolchain.defs LDSCRIPT = ld.script @@ -64,9 +64,6 @@ NM = $(ARCROSSDEV)nm OBJCOPY = $(CROSSDEV)objcopy OBJDUMP = $(CROSSDEV)objdump -ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} -ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} - ifeq ($(CONFIG_DEBUG_SYMBOLS),y) ARCHOPTIMIZATION = -g endif @@ -80,7 +77,7 @@ ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef ARCHWARNINGSXX = -Wall -Wshadow -Wundef ARCHDEFINES = -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 +ARCHPICFLAGS = -fpic CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) @@ -98,9 +95,7 @@ OBJEXT = .o LIBEXT = .a EXEEXT = -ifneq ($(CROSSDEV),arm-nuttx-elf-) - LDFLAGS += -nostartfiles -nodefaultlibs -endif +LDFLAGS += -nostartfiles -nodefaultlibs ifeq ($(CONFIG_DEBUG_SYMBOLS),y) LDFLAGS += -g endif diff --git a/configs/esp32-core/nsh/setenv.sh b/configs/esp32-core/nsh/setenv.sh index d67e6fdc7d..dedaec8923 100644 --- a/configs/esp32-core/nsh/setenv.sh +++ b/configs/esp32-core/nsh/setenv.sh @@ -1,5 +1,5 @@ #!/bin/bash -# configs/stm32f4discovery/nsh/setenv.sh +# configs/esp32-core/nsh/setenv.sh # # Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. # Author: Gregory Nutt @@ -47,32 +47,9 @@ if [ -z "${PATH_ORIG}" ]; then export PATH_ORIG="${PATH}" fi -# This is the Cygwin path to the location where I installed the RIDE -# toolchain under windows. You will also have to edit this if you install -# the RIDE toolchain in any other location -#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Raisonance/Ride/arm-gcc/bin" - -# This is the Cygwin path to the location where I installed the CodeSourcery -# toolchain under windows. You will also have to edit this if you install -# the CodeSourcery toolchain in any other location -export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" -#export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" - -# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" -# You can this free toolchain here https://launchpad.net/gcc-arm-embedded -#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" - -# These are the Cygwin paths to the locations where I installed the Atollic -# toolchain under windows. You will also have to edit this if you install -# the Atollic toolchain in any other location. /usr/bin is added before -# the Atollic bin path because there is are binaries named gcc.exe and g++.exe -# at those locations as well. -#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" -#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" - -# This is the Cygwin path to the location where I build the buildroot -# toolchain. -#export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" +# This is the path to the location where I installed the Expressif crosstools-NG +# toolchaing +export TOOLCHAIN_BIN="home/patacongo/projects/nuttx/crosstool-NG/builds/xtensa-esp32-elf/bin" # Add the path to the toolchain to the PATH variable export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" diff --git a/tools/sethost.sh b/tools/sethost.sh old mode 100644 new mode 100755 -- GitLab From 04940840b6a8417d90b5c3c970b31e0f7c7888a0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 13 Oct 2016 14:48:29 -0600 Subject: [PATCH 061/734] ESP32 Core: Correct tool-related prefix and path --- arch/xtensa/include/irq.h | 2 +- arch/xtensa/include/types.h | 10 +++++----- arch/xtensa/src/lx6/Toolchain.defs | 2 +- configs/esp32-core/nsh/setenv.sh | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index 19739e7944..ed10e3bbb1 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -50,7 +50,7 @@ /* Include architecture-specific IRQ definitions */ -#ifdef CONFIG_ARCH_CHIP_LX6 +#ifdef CONFIG_ARCH_FAMILY_LX6 # include /* Include implementation-specific IRQ definitions (including IRQ numbers) */ diff --git a/arch/xtensa/include/types.h b/arch/xtensa/include/types.h index aa987ff8bb..ea8e19ff36 100644 --- a/arch/xtensa/include/types.h +++ b/arch/xtensa/include/types.h @@ -69,8 +69,8 @@ typedef unsigned char _uint8_t; typedef signed short _int16_t; typedef unsigned short _uint16_t; -typedef signed int _int32_t; -typedef unsigned int _uint32_t; +typedef signed long _int32_t; +typedef unsigned long _uint32_t; typedef signed long long _int64_t; typedef unsigned long long _uint64_t; @@ -78,12 +78,12 @@ typedef unsigned long long _uint64_t; /* A pointer is 4 bytes */ -typedef signed int _intptr_t; -typedef unsigned int _uintptr_t; +typedef signed long _intptr_t; +typedef unsigned long _uintptr_t; /* This is the size of the interrupt state save returned by up_irq_save(). */ -typedef unsigned int irqstate_t; +typedef unsigned long irqstate_t; #endif /* __ASSEMBLY__ */ diff --git a/arch/xtensa/src/lx6/Toolchain.defs b/arch/xtensa/src/lx6/Toolchain.defs index e58071c20d..b18659fe55 100644 --- a/arch/xtensa/src/lx6/Toolchain.defs +++ b/arch/xtensa/src/lx6/Toolchain.defs @@ -33,4 +33,4 @@ # ############################################################################ -CROSSDEV = xtensa-esp32- +CROSSDEV = xtensa-esp32-elf- diff --git a/configs/esp32-core/nsh/setenv.sh b/configs/esp32-core/nsh/setenv.sh index dedaec8923..3c57c18b55 100644 --- a/configs/esp32-core/nsh/setenv.sh +++ b/configs/esp32-core/nsh/setenv.sh @@ -49,7 +49,7 @@ fi # This is the path to the location where I installed the Expressif crosstools-NG # toolchaing -export TOOLCHAIN_BIN="home/patacongo/projects/nuttx/crosstool-NG/builds/xtensa-esp32-elf/bin" +export TOOLCHAIN_BIN="/home/patacongo/projects/nuttx/crosstool-NG/builds/xtensa-esp32-elf/bin" # Add the path to the toolchain to the PATH variable export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" -- GitLab From 1c383b665177814d49459f76092c728d6cb58295 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 13 Oct 2016 16:29:54 -0600 Subject: [PATCH 062/734] Update README --- configs/esp32-core/README.txt | 100 ++++++++++++++++++++-------------- 1 file changed, 59 insertions(+), 41 deletions(-) diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index 84fd259b58..984d16f16a 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -1,41 +1,59 @@ -README for the Expressif ESP32 Core board (V2) -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - - The ESP32 is a dual-core system from Expressif with two Harvard - architecture Xtensa LX6 CPUs. All embedded memory, external memory and - peripherals are located on the data bus and/or the instruction bus of - these CPUs. With some minor exceptions, the address mapping of two CPUs - is symmetric, meaning they use the same addresses to access the same - memory. Multiple peripherals in the system can access embedded memory via - DMA. - - The two CPUs are named "PRO_CPU" and "APP_CPU" (for "protocol" and - "application"), however for most purposes the two CPUs are - interchangeable. - - Features: - - * Address Space - - Symmetric address mapping - - 4 GB (32-bit) address space for both data bus and instruction bus - - 1296 KB embedded memory address space - - 19704 KB external memory address space - - 512 KB peripheral address space - - Some embedded and external memory regions can be accessed by either - data bus or instruction bus - - 328 KB DMA address space - * Embedded Memory - - 448 KB Internal ROM - - 520 KB Internal SRAM - - 8 KB RTC FAST Memory - - 8 KB RTC SLOW Memory - * External Memory - Off-chip SPI memory can be mapped into the available address space as - external memory. Parts of the embedded memory can be used as transparent - cache for this external memory. - - Supports up to 16 MB off-Chip SPI Flash. - - Supports up to 8 MB off-Chip SPI SRAM. - * Peripherals - - 41 peripherals - * DMA - - 13 modules are capable of DMA operation \ No newline at end of file +README for the Expressif ESP32 Core board (V2) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + The ESP32 is a dual-core system from Expressif with two Harvard + architecture Xtensa LX6 CPUs. All embedded memory, external memory and + peripherals are located on the data bus and/or the instruction bus of + these CPUs. With some minor exceptions, the address mapping of two CPUs + is symmetric, meaning they use the same addresses to access the same + memory. Multiple peripherals in the system can access embedded memory via + DMA. + + The two CPUs are named "PRO_CPU" and "APP_CPU" (for "protocol" and + "application"), however for most purposes the two CPUs are + interchangeable. + + Features: + + * Address Space + - Symmetric address mapping + - 4 GB (32-bit) address space for both data bus and instruction bus + - 1296 KB embedded memory address space + - 19704 KB external memory address space + - 512 KB peripheral address space + - Some embedded and external memory regions can be accessed by either + data bus or instruction bus + - 328 KB DMA address space + * Embedded Memory + - 448 KB Internal ROM + - 520 KB Internal SRAM + - 8 KB RTC FAST Memory + - 8 KB RTC SLOW Memory + * External Memory + Off-chip SPI memory can be mapped into the available address space as + external memory. Parts of the embedded memory can be used as transparent + cache for this external memory. + - Supports up to 16 MB off-Chip SPI Flash. + - Supports up to 8 MB off-Chip SPI SRAM. + * Peripherals + - 41 peripherals + * DMA + - 13 modules are capable of DMA operation + +ESP32 Toolchain +=============== + + The steps to build toolchain with crosstool-NG on Linux are as follows: + + git clone -b xtensa-1.22.x https://github.com/espressif/crosstool-NG.git + cd crosstool-NG + ./bootstrap && ./configure --prefix=$PWD && make install + ./ct-ng xtensa-esp32-elf + ./ct-ng build + chmod -R u+w builds/xtensa-esp32-elf + + These steps are given in setup guide in ESP-IDF repository: + https://github.com/espressif/esp-idf/blob/master/docs/linux-setup.rst#alternative-step-1-compile-the-toolchain-from-source-using-crosstool-ng + + NOTE: the xtensa-esp32-elf configuration is only available in the + xtensa-1.22.x branch. -- GitLab From c078573677de9af2889277ad5b6ba4465e442689 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 13 Oct 2016 16:29:50 -0600 Subject: [PATCH 063/734] Add some .gitignore files --- arch/xtensa/include/.gitignore | 3 +++ arch/xtensa/src/.gitignore | 4 ++++ 2 files changed, 7 insertions(+) create mode 100644 arch/xtensa/include/.gitignore create mode 100644 arch/xtensa/src/.gitignore diff --git a/arch/xtensa/include/.gitignore b/arch/xtensa/include/.gitignore new file mode 100644 index 0000000000..e6460c4a67 --- /dev/null +++ b/arch/xtensa/include/.gitignore @@ -0,0 +1,3 @@ +/board +/chip + diff --git a/arch/xtensa/src/.gitignore b/arch/xtensa/src/.gitignore new file mode 100644 index 0000000000..8d209f76a4 --- /dev/null +++ b/arch/xtensa/src/.gitignore @@ -0,0 +1,4 @@ +/.depend +/Make.dep +/board +/chip -- GitLab From 64b020f1a8fa3fbd1490fad45a3b370b2ad8f727 Mon Sep 17 00:00:00 2001 From: neilh10 Date: Thu, 13 Oct 2016 19:42:39 -0700 Subject: [PATCH 064/734] Add UID Unique ID --- arch/arm/src/kinetis/Make.defs | 2 +- arch/arm/src/kinetis/kinetis_uid.c | 68 +++++++++++++++++++++++ arch/arm/src/kinetis/kinetis_uid.h | 49 +++++++++++++++++ configs/freedom-k64f/README.txt | 2 + configs/freedom-k64f/src/Makefile | 3 + configs/freedom-k64f/src/k64_uid.c | 73 +++++++++++++++++++++++++ configs/freedom-k64f/src/k64_userleds.c | 1 + 7 files changed, 197 insertions(+), 1 deletion(-) create mode 100644 arch/arm/src/kinetis/kinetis_uid.c create mode 100644 arch/arm/src/kinetis/kinetis_uid.h create mode 100644 configs/freedom-k64f/src/k64_uid.c diff --git a/arch/arm/src/kinetis/Make.defs b/arch/arm/src/kinetis/Make.defs index bb7f54d87b..b2f1046caa 100644 --- a/arch/arm/src/kinetis/Make.defs +++ b/arch/arm/src/kinetis/Make.defs @@ -90,7 +90,7 @@ CHIP_ASRCS = CHIP_CSRCS = kinetis_allocateheap.c kinetis_clockconfig.c CHIP_CSRCS += kinetis_clrpend.c kinetis_idle.c kinetis_irq.c CHIP_CSRCS += kinetis_lowputc.c kinetis_pin.c kinetis_pingpio.c -CHIP_CSRCS += kinetis_serial.c kinetis_start.c kinetis_wdog.c +CHIP_CSRCS += kinetis_serial.c kinetis_start.c kinetis_uid.c kinetis_wdog.c CHIP_CSRCS += kinetis_cfmconfig.c # Configuration-dependent Kinetis files diff --git a/arch/arm/src/kinetis/kinetis_uid.c b/arch/arm/src/kinetis/kinetis_uid.c new file mode 100644 index 0000000000..3693b3507b --- /dev/null +++ b/arch/arm/src/kinetis/kinetis_uid.c @@ -0,0 +1,68 @@ +/************************************************************************************ + * arch/arm/src/kinetis/kinetis_uid.c + * + * Copyright (C) 2016 Neil Hancock. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +//#include + +#include +#include +#include "kinetis_uid.h" + +#ifdef CONFIG_BOARDCTL_UNIQUEID + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +void kinetis_get_uniqueid(uint8_t *uniqueid) +{ + int i; + uint32_t *unique_u32; + unique_u32 = (uint32_t *)uniqueid; + + /* + * Copy into buffer LS first, which in the Kinetis is the highest memory + */ + + for (i = 0; i < (KINETIS_UID_SIZE/sizeof(uint32_t)); i++) + { + unique_u32[i] = *((uint32_t*)(KINETIS_SIM_UIDL)-i); + } +} + +#endif /* CONFIG_BOARDCTL_UNIQUEID */ + diff --git a/arch/arm/src/kinetis/kinetis_uid.h b/arch/arm/src/kinetis/kinetis_uid.h new file mode 100644 index 0000000000..84620f53e5 --- /dev/null +++ b/arch/arm/src/kinetis/kinetis_uid.h @@ -0,0 +1,49 @@ +/************************************************************************************ + * arch/arm/src/kinetis/kinetis_uid.h + * + * Copyright (C) 2016 Neil Hancock. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_UID_H +#define __ARCH_ARM_SRC_KINETIS_UID_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ +#define KINETIS_UID_SIZE 16 +void kinetis_get_uniqueid(uint8_t *uniqueid); +#endif /* __ARCH_ARM_SRC_KINETIS_UID_H */ diff --git a/configs/freedom-k64f/README.txt b/configs/freedom-k64f/README.txt index 0b80b603d1..2c6666a7e6 100644 --- a/configs/freedom-k64f/README.txt +++ b/configs/freedom-k64f/README.txt @@ -56,6 +56,8 @@ OpenSDAv2 HDK-compatible debug interface preloaded with the open-source CMSIS-DAP Interface firmware (mbed interface) for rapid prototyping and product development. + + To use set raw binary output for nuttx.bin Serial Console ============== diff --git a/configs/freedom-k64f/src/Makefile b/configs/freedom-k64f/src/Makefile index 8c533ec849..7da96029aa 100644 --- a/configs/freedom-k64f/src/Makefile +++ b/configs/freedom-k64f/src/Makefile @@ -73,4 +73,7 @@ ifeq ($(CONFIG_PWM),y) CSRCS += k64_pwm.c endif +ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) +CSRCS += k64_uid.c +endif include $(TOPDIR)/configs/Board.mk diff --git a/configs/freedom-k64f/src/k64_uid.c b/configs/freedom-k64f/src/k64_uid.c new file mode 100644 index 0000000000..545de899c0 --- /dev/null +++ b/configs/freedom-k64f/src/k64_uid.c @@ -0,0 +1,73 @@ +/************************************************************************************ + * configs/freedom-k64/src/kinetis_uid.c + * + * Copyright (C) 2016 Neil Hancock. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include +#include "kinetis_uid.h" + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#ifndef OK +# define OK 0 +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#if defined(CONFIG_BOARDCTL_UNIQUEID) + +int board_uniqueid(FAR uint8_t *uniqueid) +{ + if (uniqueid == 0) + { + return -EINVAL; + } + + kinetis_get_uniqueid(uniqueid); + return OK; +} + +#endif diff --git a/configs/freedom-k64f/src/k64_userleds.c b/configs/freedom-k64f/src/k64_userleds.c index 48a396a3ce..e75a2abb8e 100644 --- a/configs/freedom-k64f/src/k64_userleds.c +++ b/configs/freedom-k64f/src/k64_userleds.c @@ -107,3 +107,4 @@ void board_userled_all(uint8_t ledset) kinetis_gpiowrite(GPIO_LED_G, (ledset & BOARD_LED_G_BIT) == 0); kinetis_gpiowrite(GPIO_LED_B, (ledset & BOARD_LED_B_BIT) == 0); } +#endif -- GitLab From 6dca9a439033a311685260e008176cce8730f72b Mon Sep 17 00:00:00 2001 From: neilh10 Date: Thu, 13 Oct 2016 19:50:35 -0700 Subject: [PATCH 065/734] Add UID Unique ID --- arch/arm/src/kinetis/kinetis_uid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/kinetis/kinetis_uid.c b/arch/arm/src/kinetis/kinetis_uid.c index 3693b3507b..54a98d08ce 100644 --- a/arch/arm/src/kinetis/kinetis_uid.c +++ b/arch/arm/src/kinetis/kinetis_uid.c @@ -36,7 +36,7 @@ * Included Files ************************************************************************************/ -//#include +#include #include #include -- GitLab From f7e0a36f55e5a3887cca2ac6bec82e7dba0fdd67 Mon Sep 17 00:00:00 2001 From: Sebastien Lorquet Date: Fri, 14 Oct 2016 12:50:45 +0200 Subject: [PATCH 066/734] Multiple stm32l4 timer fixes: - too many parentheses when calculating max chan count (???) - channel 4 does not have a complementary output --- arch/arm/src/stm32l4/stm32l4_pwm.c | 4 ++-- arch/arm/src/stm32l4/stm32l4_pwm.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.c b/arch/arm/src/stm32l4/stm32l4_pwm.c index d3478ea0df..7d23582b17 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.c +++ b/arch/arm/src/stm32l4/stm32l4_pwm.c @@ -1206,7 +1206,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv, */ ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | - ATIM_CCER_CC3NE | ATIM_CCER_CC3NP | ATIM_CCER_CC4NP); + ATIM_CCER_CC3NE | ATIM_CCER_CC3NP); /* Reset the output compare and output compare N IDLE State */ @@ -1225,7 +1225,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv, else #endif { - ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP | ATIM_CCER_CC4NP); + ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP); } /* Save the modified register values */ diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.h b/arch/arm/src/stm32l4/stm32l4_pwm.h index 942aef0cfa..f2b17198c0 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.h +++ b/arch/arm/src/stm32l4/stm32l4_pwm.h @@ -422,7 +422,7 @@ PWM_MAX(PWM_TIM8_NCHANNELS, \ PWM_MAX(PWM_TIM15_NCHANNELS, \ PWM_MAX(PWM_TIM16_NCHANNELS, \ - PWM_TIM17_NCHANNELS)))))))))))))) + PWM_TIM17_NCHANNELS)))))))) #else -- GitLab From fb1f424e129010097f54f5635b1f1b74b1e06e59 Mon Sep 17 00:00:00 2001 From: Sebastien Lorquet Date: Fri, 14 Oct 2016 18:06:11 +0200 Subject: [PATCH 067/734] Support Complementary PWM outputs on STM32L4 --- arch/arm/src/stm32l4/Kconfig | 63 ++++++++++++++++ arch/arm/src/stm32l4/stm32l4_pwm.c | 114 ++++++++++++++++++++++++++--- arch/arm/src/stm32l4/stm32l4_pwm.h | 45 ++++++++++++ 3 files changed, 211 insertions(+), 11 deletions(-) diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index 3ccbfff8af..b6eba519cd 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -731,6 +731,13 @@ config STM32L4_TIM1_CH1OUT ---help--- Enables channel 1 output. +config STM32L4_TIM1_CH1NOUT + bool "TIM1 Channel 1 Complementary Output" + default n + depends on STM32L4_TIM1_CH1OUT + ---help--- + Enables channel 1 complementary output. + endif # STM32L4_TIM1_CHANNEL1 config STM32L4_TIM1_CHANNEL2 @@ -754,6 +761,13 @@ config STM32L4_TIM1_CH2OUT ---help--- Enables channel 2 output. +config STM32L4_TIM1_CH2NOUT + bool "TIM1 Channel 2 Complemenrary Output" + default n + depends on STM32L4_TIM1_CH2OUT + ---help--- + Enables channel 2 complementary output. + endif # STM32L4_TIM1_CHANNEL2 config STM32L4_TIM1_CHANNEL3 @@ -777,6 +791,13 @@ config STM32L4_TIM1_CH3OUT ---help--- Enables channel 3 output. +config STM32L4_TIM1_CH3NOUT + bool "TIM1 Channel 3 Complementary Output" + default n + depends on STM32L4_TIM1_CH3OUT + ---help--- + Enables channel 3 complementary output. + endif # STM32L4_TIM1_CHANNEL3 config STM32L4_TIM1_CHANNEL4 @@ -1426,6 +1447,13 @@ config STM32L4_TIM8_CH1OUT ---help--- Enables channel 1 output. +config STM32L4_TIM8_CH1NOUT + bool "TIM8 Channel 1 Complementary Output" + default n + depends on STM32L4_TIM8_CH1OUT + ---help--- + Enables channel 1 complementary output. + endif # STM32L4_TIM8_CHANNEL1 config STM32L4_TIM8_CHANNEL2 @@ -1449,6 +1477,13 @@ config STM32L4_TIM8_CH2OUT ---help--- Enables channel 2 output. +config STM32L4_TIM8_CH2NOUT + bool "TIM8 Channel 2 Complementary Output" + default n + depends on STM32L4_TIM8_CH2OUT + ---help--- + Enables channel 2 complementary output. + endif # STM32L4_TIM8_CHANNEL2 config STM32L4_TIM8_CHANNEL3 @@ -1472,6 +1507,13 @@ config STM32L4_TIM8_CH3OUT ---help--- Enables channel 3 output. +config STM32L4_TIM8_CH3NOUT + bool "TIM8 Channel 3 Complementary Output" + default n + depends on STM32L4_TIM8_CH3OUT + ---help--- + Enables channel 3 complementary output. + endif # STM32L4_TIM8_CHANNEL3 config STM32L4_TIM8_CHANNEL4 @@ -1557,6 +1599,13 @@ config STM32L4_TIM15_CH1OUT ---help--- Enables channel 1 output. +config STM32L4_TIM15_CH1NOUT + bool "TIM15 Channel 1 Complementary Output" + default n + depends on STM32L4_TIM15_CH1OUT + ---help--- + Enables channel 1 complementary output. + endif # STM32L4_TIM15_CHANNEL1 config STM32L4_TIM15_CHANNEL2 @@ -1642,6 +1691,13 @@ config STM32L4_TIM16_CH1OUT ---help--- Enables channel 1 output. +config STM32L4_TIM16_CH1NOUT + bool "TIM16 Channel 1 Complementary Output" + default n + depends on STM32L4_TIM16_CH1OUT + ---help--- + Enables channel 1 complementary output. + endif # STM32L4_TIM16_CHANNEL1 endif # STM32L4_PWM_MULTICHAN @@ -1704,6 +1760,13 @@ config STM32L4_TIM17_CH1OUT ---help--- Enables channel 1 output. +config STM32L4_TIM17_CH1NOUT + bool "TIM17 Channel 1 Complementary Output" + default n + depends on STM32L4_TIM17_CH1OUT + ---help--- + Enables channel 1 complementary output. + endif # STM32L4_TIM17_CHANNEL1 endif # STM32L4_PWM_MULTICHAN diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.c b/arch/arm/src/stm32l4/stm32l4_pwm.c index 7d23582b17..f45e4c1384 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.c +++ b/arch/arm/src/stm32l4/stm32l4_pwm.c @@ -128,6 +128,7 @@ struct stm32l4_pwmchan_s uint8_t channel; /* Timer output channel: {1,..4} */ uint32_t pincfg; /* Output pin configuration */ enum stm32l4_chanmode_e mode; + uint32_t npincfg; /* Complementary output pin configuration (only TIM1/8 CH1-3)*/ }; /* This structure represents the state of one PWM timer */ @@ -229,6 +230,7 @@ static struct stm32l4_pwmtimer_s g_pwm1dev = .channel = 1, .pincfg = PWM_TIM1_CH1CFG, .mode = CONFIG_STM32L4_TIM1_CH1MODE, + .npincfg = PWM_TIM1_CH1NCFG, }, #endif #ifdef CONFIG_STM32L4_TIM1_CHANNEL2 @@ -236,6 +238,7 @@ static struct stm32l4_pwmtimer_s g_pwm1dev = .channel = 2, .pincfg = PWM_TIM1_CH2CFG, .mode = CONFIG_STM32L4_TIM1_CH2MODE, + .npincfg = PWM_TIM1_CH2NCFG, }, #endif #ifdef CONFIG_STM32L4_TIM1_CHANNEL3 @@ -243,6 +246,7 @@ static struct stm32l4_pwmtimer_s g_pwm1dev = .channel = 3, .pincfg = PWM_TIM1_CH3CFG, .mode = CONFIG_STM32L4_TIM1_CH3MODE, + .npincfg = PWM_TIM1_CH3NCFG, }, #endif #ifdef CONFIG_STM32L4_TIM1_CHANNEL4 @@ -250,6 +254,7 @@ static struct stm32l4_pwmtimer_s g_pwm1dev = .channel = 4, .pincfg = PWM_TIM1_CH4CFG, .mode = CONFIG_STM32L4_TIM1_CH4MODE, + .npincfg = 0, }, #endif }, @@ -275,6 +280,7 @@ static struct stm32l4_pwmtimer_s g_pwm2dev = .channel = 1, .pincfg = PWM_TIM2_CH1CFG, .mode = CONFIG_STM32L4_TIM2_CH1MODE, + .npincfg = 0, }, #endif #ifdef CONFIG_STM32L4_TIM2_CHANNEL2 @@ -282,6 +288,7 @@ static struct stm32l4_pwmtimer_s g_pwm2dev = .channel = 2, .pincfg = PWM_TIM2_CH2CFG, .mode = CONFIG_STM32L4_TIM2_CH2MODE, + .npincfg = 0, }, #endif #ifdef CONFIG_STM32L4_TIM2_CHANNEL3 @@ -289,6 +296,7 @@ static struct stm32l4_pwmtimer_s g_pwm2dev = .channel = 3, .pincfg = PWM_TIM2_CH3CFG, .mode = CONFIG_STM32L4_TIM2_CH3MODE, + .npincfg = 0, }, #endif #ifdef CONFIG_STM32L4_TIM2_CHANNEL4 @@ -296,6 +304,7 @@ static struct stm32l4_pwmtimer_s g_pwm2dev = .channel = 4, .pincfg = PWM_TIM2_CH4CFG, .mode = CONFIG_STM32L4_TIM2_CH4MODE, + .npincfg = 0, }, #endif }, @@ -321,6 +330,7 @@ static struct stm32l4_pwmtimer_s g_pwm3dev = .channel = 1, .pincfg = PWM_TIM3_CH1CFG, .mode = CONFIG_STM32L4_TIM3_CH1MODE, + .npincfg = 0, }, #endif #ifdef CONFIG_STM32L4_TIM3_CHANNEL2 @@ -328,6 +338,7 @@ static struct stm32l4_pwmtimer_s g_pwm3dev = .channel = 2, .pincfg = PWM_TIM3_CH2CFG, .mode = CONFIG_STM32L4_TIM3_CH2MODE, + .npincfg = 0, }, #endif #ifdef CONFIG_STM32L4_TIM3_CHANNEL3 @@ -335,6 +346,7 @@ static struct stm32l4_pwmtimer_s g_pwm3dev = .channel = 3, .pincfg = PWM_TIM3_CH3CFG, .mode = CONFIG_STM32L4_TIM3_CH3MODE, + .npincfg = 0, }, #endif #ifdef CONFIG_STM32L4_TIM3_CHANNEL4 @@ -342,6 +354,7 @@ static struct stm32l4_pwmtimer_s g_pwm3dev = .channel = 4, .pincfg = PWM_TIM3_CH4CFG, .mode = CONFIG_STM32L4_TIM3_CH4MODE, + .npincfg = 0, }, #endif }, @@ -367,6 +380,7 @@ static struct stm32l4_pwmtimer_s g_pwm4dev = .channel = 1, .pincfg = PWM_TIM4_CH1CFG, .mode = CONFIG_STM32L4_TIM4_CH1MODE, + .npincfg = 0, }, #endif #ifdef CONFIG_STM32L4_TIM4_CHANNEL2 @@ -374,6 +388,7 @@ static struct stm32l4_pwmtimer_s g_pwm4dev = .channel = 2, .pincfg = PWM_TIM4_CH2CFG, .mode = CONFIG_STM32L4_TIM4_CH2MODE, + .npincfg = 0, }, #endif #ifdef CONFIG_STM32L4_TIM4_CHANNEL3 @@ -381,6 +396,7 @@ static struct stm32l4_pwmtimer_s g_pwm4dev = .channel = 3, .pincfg = PWM_TIM4_CH3CFG, .mode = CONFIG_STM32L4_TIM4_CH3MODE, + .npincfg = 0, }, #endif #ifdef CONFIG_STM32L4_TIM4_CHANNEL4 @@ -388,6 +404,7 @@ static struct stm32l4_pwmtimer_s g_pwm4dev = .channel = 4, .pincfg = PWM_TIM4_CH4CFG, .mode = CONFIG_STM32L4_TIM4_CH4MODE, + .npincfg = 0, }, #endif }, @@ -413,6 +430,7 @@ static struct stm32l4_pwmtimer_s g_pwm5dev = .channel = 1, .pincfg = PWM_TIM5_CH1CFG, .mode = CONFIG_STM32L4_TIM5_CH1MODE, + .npincfg = 0, }, #endif #ifdef CONFIG_STM32L4_TIM5_CHANNEL2 @@ -420,6 +438,7 @@ static struct stm32l4_pwmtimer_s g_pwm5dev = .channel = 2, .pincfg = PWM_TIM5_CH2CFG, .mode = CONFIG_STM32L4_TIM5_CH2MODE, + .npincfg = 0, }, #endif #ifdef CONFIG_STM32L4_TIM5_CHANNEL3 @@ -427,6 +446,7 @@ static struct stm32l4_pwmtimer_s g_pwm5dev = .channel = 3, .pincfg = PWM_TIM5_CH3CFG, .mode = CONFIG_STM32L4_TIM5_CH3MODE, + .npincfg = 0, }, #endif #ifdef CONFIG_STM32L4_TIM5_CHANNEL4 @@ -434,6 +454,7 @@ static struct stm32l4_pwmtimer_s g_pwm5dev = .channel = 4, .pincfg = PWM_TIM5_CH4CFG, .mode = CONFIG_STM32L4_TIM5_CH4MODE, + .npincfg = 0, }, #endif }, @@ -459,6 +480,7 @@ static struct stm32l4_pwmtimer_s g_pwm8dev = .channel = 1, .pincfg = PWM_TIM8_CH1CFG, .mode = CONFIG_STM32L4_TIM8_CH1MODE, + .npincfg = PWM_TIM8_CH1NCFG, }, #endif #ifdef CONFIG_STM32L4_TIM8_CHANNEL2 @@ -466,6 +488,7 @@ static struct stm32l4_pwmtimer_s g_pwm8dev = .channel = 2, .pincfg = PWM_TIM8_CH2CFG, .mode = CONFIG_STM32L4_TIM8_CH2MODE, + .npincfg = PWM_TIM8_CH2NCFG, }, #endif #ifdef CONFIG_STM32L4_TIM8_CHANNEL3 @@ -473,6 +496,7 @@ static struct stm32l4_pwmtimer_s g_pwm8dev = .channel = 3, .pincfg = PWM_TIM8_CH3CFG, .mode = CONFIG_STM32L4_TIM8_CH3MODE, + .npincfg = PWM_TIM8_CH3NCFG, }, #endif #ifdef CONFIG_STM32L4_TIM8_CHANNEL4 @@ -480,6 +504,7 @@ static struct stm32l4_pwmtimer_s g_pwm8dev = .channel = 4, .pincfg = PWM_TIM8_CH4CFG, .mode = CONFIG_STM32L4_TIM8_CH4MODE, + .npincfg = 0, }, #endif }, @@ -505,6 +530,7 @@ static struct stm32l4_pwmtimer_s g_pwm15dev = .channel = 1, .pincfg = PWM_TIM15_CH1CFG, .mode = CONFIG_STM32L4_TIM15_CH1MODE, + .npincfg = PWM_TIM15_CH1NCFG, }, #endif #ifdef CONFIG_STM32L4_TIM15_CHANNEL2 @@ -512,6 +538,7 @@ static struct stm32l4_pwmtimer_s g_pwm15dev = .channel = 2, .pincfg = PWM_TIM15_CH2CFG, .mode = CONFIG_STM32L4_TIM15_CH2MODE, + .npincfg = 0, }, #endif }, @@ -537,6 +564,7 @@ static struct stm32l4_pwmtimer_s g_pwm16dev = .channel = 1, .pincfg = PWM_TIM16_CH1CFG, .mode = CONFIG_STM32L4_TIM16_CH1MODE, + .npincfg = PWM_TIM16_CH1NCFG, }, #endif }, @@ -562,6 +590,7 @@ static struct stm32l4_pwmtimer_s g_pwm17dev = .channel = 1, .pincfg = PWM_TIM17_CH1CFG, .mode = CONFIG_STM32L4_TIM17_CH1MODE, + .npincfg = PWM_TIM17_CH1NCFG, }, #endif }, @@ -737,6 +766,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv, /* New timer register bit settings */ uint16_t ccenable; + uint16_t ccnenable; uint32_t ocmode1; uint32_t ocmode2; @@ -967,6 +997,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv, /* Handle channel specific setup */ ccenable = 0; + ccnenable = 0; ocmode1 = 0; ocmode2 = 0; @@ -976,6 +1007,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv, { ub16_t duty; uint32_t chanmode; + uint32_t compout; /* Complementary output config */ bool ocmbit = false; uint8_t channel; #ifdef CONFIG_PWM_MULTICHAN @@ -1001,6 +1033,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv, if (priv->channels[j].channel == channel) { mode = priv->channels[j].mode; + compout = priv->channels[j].npincfg; break; } } @@ -1014,6 +1047,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv, duty = info->duty; channel = priv->channels[0].channel; mode = priv->channels[0].mode; + compout = priv->channels[0].npincfg; #endif /* Duty cycle: @@ -1068,6 +1102,13 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv, ccenable |= ATIM_CCER_CC1E; + /* Conditionnaly enable the complementary output */ + + if(compout) + { + ccnenable |= ATIM_CCER_CC1NE; + } + /* Set the CCMR1 mode values (leave CCMR2 zero) */ ocmode1 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT) | @@ -1091,6 +1132,13 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv, ccenable |= ATIM_CCER_CC2E; + /* Conditionnaly enable the complementary output */ + + if(compout) + { + ccnenable |= ATIM_CCER_CC2NE; + } + /* Set the CCMR1 mode values (leave CCMR2 zero) */ ocmode1 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT) | @@ -1114,6 +1162,13 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv, ccenable |= ATIM_CCER_CC3E; + /* Conditionnaly enable the complementary output */ + + if(compout) + { + ccnenable |= ATIM_CCER_CC3NE; + } + /* Set the CCMR2 mode values (leave CCMR1 zero) */ ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT) | @@ -1208,6 +1263,8 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv, ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | ATIM_CCER_CC3NE | ATIM_CCER_CC3NP); + ccer |= ccnenable; + /* Reset the output compare and output compare N IDLE State */ cr2 &= ~(ATIM_CR2_OIS1 | ATIM_CR2_OIS1N | ATIM_CR2_OIS2 | ATIM_CR2_OIS2N | @@ -1223,9 +1280,23 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv, stm32l4pwm_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, bdtr); } else +#if defined(CONFIG_STM32L4_TIM15_PWM) || defined(CONFIG_STM32L4_TIM15_PWM) || defined(CONFIG_STM32L4_TIM15_PWM) + if (priv->timtype == TIMTYPE_COUNTUP16) + { + + /* Reset output N polarity level, output N state, output compare state, + * output compare N idle state. + */ + + ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP); + + ccer |= ccnenable; + } + else +#endif #endif { - ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP); + ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP); //Not sure why ?? } /* Save the modified register values */ @@ -1646,14 +1717,24 @@ static int stm32l4pwm_setup(FAR struct pwm_lowerhalf_s *dev) for (i = 0; i < PWM_NCHANNELS; i++) { pincfg = priv->channels[i].pincfg; - if (pincfg == 0) + if (pincfg != 0) { - continue; + pwminfo("pincfg: %08x\n", pincfg); + + stm32l4_configgpio(pincfg); } - pwminfo("pincfg: %08x\n", pincfg); - stm32l4_configgpio(pincfg); + /* Enable complementary channel if available */ + + pincfg = priv->channels[i].npincfg; + if (pincfg != 0) + { + pwminfo("npincfg: %08x\n", pincfg); + + stm32l4_configgpio(pincfg); + } + pwm_dumpgpio(pincfg, "PWM setup"); } @@ -1697,18 +1778,29 @@ static int stm32l4pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) for (i = 0; i < PWM_NCHANNELS; i++) { pincfg = priv->channels[i].pincfg; - if (pincfg == 0) + if (pincfg != 0) { - continue; + pwminfo("pincfg: %08x\n", pincfg); + + pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); + + pincfg |= GPIO_INPUT | GPIO_FLOAT; + + stm32l4_configgpio(pincfg); } - pwminfo("pincfg: %08x\n", pincfg); + pincfg = priv->channels[i].npincfg; + if (pincfg != 0) + { + pwminfo("npincfg: %08x\n", pincfg); + + pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); + pincfg |= GPIO_INPUT | GPIO_FLOAT; - pincfg |= GPIO_INPUT | GPIO_FLOAT; + stm32l4_configgpio(pincfg); + } - stm32l4_configgpio(pincfg); } return OK; diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.h b/arch/arm/src/stm32l4/stm32l4_pwm.h index f2b17198c0..b314834520 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.h +++ b/arch/arm/src/stm32l4/stm32l4_pwm.h @@ -114,6 +114,11 @@ # else # define PWM_TIM1_CH1CFG 0 # endif +# ifdef CONFIG_STM32L4_TIM1_CH1NOUT +# define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT +# else +# define PWM_TIM1_CH1NCFG 0 +# endif # define PWM_TIM1_CHANNEL1 1 #else # define PWM_TIM1_CHANNEL1 0 @@ -124,6 +129,11 @@ # else # define PWM_TIM1_CH2CFG 0 # endif +# ifdef CONFIG_STM32L4_TIM1_CH2NOUT +# define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT +# else +# define PWM_TIM1_CH2NCFG 0 +# endif # define PWM_TIM1_CHANNEL2 1 #else # define PWM_TIM1_CHANNEL2 0 @@ -134,6 +144,11 @@ # else # define PWM_TIM1_CH3CFG 0 # endif +# ifdef CONFIG_STM32L4_TIM1_CH3NOUT +# define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT +# else +# define PWM_TIM1_CH3NCFG 0 +# endif # define PWM_TIM1_CHANNEL3 1 #else # define PWM_TIM1_CHANNEL3 0 @@ -329,6 +344,11 @@ # else # define PWM_TIM8_CH1CFG 0 # endif +# ifdef CONFIG_STM32L4_TIM8_CH1OUT +# define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT +# else +# define PWM_TIM8_CH1NCFG 0 +# endif # define PWM_TIM8_CHANNEL1 1 #else # define PWM_TIM8_CHANNEL1 0 @@ -339,6 +359,11 @@ # else # define PWM_TIM8_CH2CFG 0 # endif +# ifdef CONFIG_STM32L4_TIM8_CH2NOUT +# define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT +# else +# define PWM_TIM8_CH2NCFG 0 +# endif # define PWM_TIM8_CHANNEL2 1 #else # define PWM_TIM8_CHANNEL2 0 @@ -349,6 +374,11 @@ # else # define PWM_TIM8_CH3CFG 0 # endif +# ifdef CONFIG_STM32L4_TIM8_CH3NOUT +# define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT +# else +# define PWM_TIM8_CH3NCFG 0 +# endif # define PWM_TIM8_CHANNEL3 1 #else # define PWM_TIM8_CHANNEL3 0 @@ -372,6 +402,11 @@ # else # define PWM_TIM15_CH1CFG 0 # endif +# ifdef CONFIG_STM32L4_TIM15_CH1NOUT +# define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT +# else +# define PWM_TIM15_CH1NCFG 0 +# endif # define PWM_TIM15_CHANNEL1 1 #else # define PWM_TIM15_CHANNEL1 0 @@ -394,6 +429,11 @@ # else # define PWM_TIM16_CH1CFG 0 # endif +# ifdef CONFIG_STM32L4_TIM16_CH1NOUT +# define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT +# else +# define PWM_TIM16_CH1NCFG 0 +# endif # define PWM_TIM16_CHANNEL1 1 #else # define PWM_TIM16_CHANNEL1 0 @@ -406,6 +446,11 @@ # else # define PWM_TIM17_CH1CFG 0 # endif +# ifdef CONFIG_STM32L4_TIM17_CH1NOUT +# define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT +# else +# define PWM_TIM17_CH1NCFG 0 +# endif # define PWM_TIM17_CHANNEL1 1 #else # define PWM_TIM17_CHANNEL1 0 -- GitLab From 49238489fdf6040ff41661c89b6e5e3aee2d318b Mon Sep 17 00:00:00 2001 From: Sebastien Lorquet Date: Fri, 14 Oct 2016 18:06:42 +0200 Subject: [PATCH 068/734] Support PWM testing on board nucleo-l476. --- configs/nucleo-l476rg/include/board.h | 12 + configs/nucleo-l476rg/src/Makefile | 4 + configs/nucleo-l476rg/src/stm32_appinit.c | 21 ++ configs/nucleo-l476rg/src/stm32_pwm.c | 275 ++++++++++++++++++++++ 4 files changed, 312 insertions(+) create mode 100644 configs/nucleo-l476rg/src/stm32_pwm.c diff --git a/configs/nucleo-l476rg/include/board.h b/configs/nucleo-l476rg/include/board.h index a7a983221d..986844bf33 100644 --- a/configs/nucleo-l476rg/include/board.h +++ b/configs/nucleo-l476rg/include/board.h @@ -212,6 +212,18 @@ #define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_1 #define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_1 +/* PWM output for full bridge, uses config 1, because port E is N/A on QFP64 + * CH1 | 1(A8) 2(E9) + * CH2 | 1(A9) 2(E11) + * CHN1 | 1(A7) 2(B13) 3(E8) + * CHN2 | 1(B0) 2(B14) 3(E10) + */ + +#define GPIO_TIM1_CH1OUT GPIO_TIM1_CH1OUT_1 +#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1N_1 +#define GPIO_TIM1_CH2OUT GPIO_TIM1_CH2OUT_1 +#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2N_1 + /************************************************************************************ * Public Data ************************************************************************************/ diff --git a/configs/nucleo-l476rg/src/Makefile b/configs/nucleo-l476rg/src/Makefile index 771a34ffd6..c47701ba2c 100644 --- a/configs/nucleo-l476rg/src/Makefile +++ b/configs/nucleo-l476rg/src/Makefile @@ -66,6 +66,10 @@ ifeq ($(CONFIG_QENCODER),y) CSRCS += stm32_qencoder.c endif +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += stm32_appinit.c endif diff --git a/configs/nucleo-l476rg/src/stm32_appinit.c b/configs/nucleo-l476rg/src/stm32_appinit.c index 9910184bf8..4f805ff147 100644 --- a/configs/nucleo-l476rg/src/stm32_appinit.c +++ b/configs/nucleo-l476rg/src/stm32_appinit.c @@ -207,3 +207,24 @@ int board_app_initialize(uintptr_t arg) return OK; } + +#ifdef CONFIG_BOARDCTL_IOCTL +int board_ioctl(unsigned int cmd, uintptr_t arg) +{ + return -ENOTTY; +} +#endif + +#if defined(CONFIG_BOARDCTL_UNIQUEID) +int board_uniqueid(uint8_t *uniqueid) +{ + if (uniqueid == 0) + { + return -EINVAL; + } + + stm32l4_get_uniqueid(uniqueid); + return OK; +} +#endif + diff --git a/configs/nucleo-l476rg/src/stm32_pwm.c b/configs/nucleo-l476rg/src/stm32_pwm.c new file mode 100644 index 0000000000..0f753844bb --- /dev/null +++ b/configs/nucleo-l476rg/src/stm32_pwm.c @@ -0,0 +1,275 @@ +/************************************************************************************ + * configs/nucleo-l476rg/src/stm32_pwm.c + * + * Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Copyright (C) 2016 Sebastien Lorquet. All rights reserved. + * Author: Sebastien Lorquet + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "up_arch.h" +#include "stm32l4_pwm.h" +#include "nucleo-l476rg.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Configuration *******************************************************************/ +/* PWM + * + * The STM3240G-Eval has no real on-board PWM devices, but the board can be + * configured to output a pulse train using variously unused pins on the board for + * PWM output (see board.h for details of pins). + */ + +#ifdef CONFIG_PWM + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: board_pwm_setup + * + * Description: + * All STM32L4 architectures must provide the following interface to work with + * examples/pwm. + * + ************************************************************************************/ + +int board_pwm_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32l4_pwminitialize() to get an instance of the PWM interface */ +/* PWM + * + * The Nucleo-l476rg has no real on-board PWM devices, but the board can be + * configured to output a pulse train using TIM1 or 8, or others (see board.h). + * Let's figure out which the user has configured. + */ + +# if defined(CONFIG_STM32L4_TIM1_PWM) + pwm = stm32l4_pwminitialize(1); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +# if defined(CONFIG_STM32L4_TIM2_PWM) + pwm = stm32l4_pwminitialize(2); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm1" */ + + ret = pwm_register("/dev/pwm1", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +# if defined(CONFIG_STM32L4_TIM3_PWM) + pwm = stm32l4_pwminitialize(3); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm2" */ + + ret = pwm_register("/dev/pwm2", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +# if defined(CONFIG_STM32L4_TIM4_PWM) + pwm = stm32l4_pwminitialize(4); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm3" */ + + ret = pwm_register("/dev/pwm3", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +# if defined(CONFIG_STM32L4_TIM5_PWM) + pwm = stm32l4_pwminitialize(5); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm4" */ + + ret = pwm_register("/dev/pwm4", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +# if defined(CONFIG_STM32L4_TIM8_PWM) + pwm = stm32l4_pwminitialize(8); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm5" */ + + ret = pwm_register("/dev/pwm5", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +# if defined(CONFIG_STM32L4_TIM15_PWM) + pwm = stm32l4_pwminitialize(15); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm6" */ + + ret = pwm_register("/dev/pwm6", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +# if defined(CONFIG_STM32L4_TIM16_PWM) + pwm = stm32l4_pwminitialize(16); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm7" */ + + ret = pwm_register("/dev/pwm7", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +# if defined(CONFIG_STM32L4_TIM17_PWM) + pwm = stm32l4_pwminitialize(17); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm8" */ + + ret = pwm_register("/dev/pwm8", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_PWM */ -- GitLab From b669d78f8c7124083e167773afc5869bbe93d7c9 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 14 Oct 2016 11:01:28 -0600 Subject: [PATCH 069/734] Trivial changes to README.txt --- configs/esp32-core/README.txt | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index 984d16f16a..514c84cef9 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -1,5 +1,5 @@ README for the Expressif ESP32 Core board (V2) -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +============================================== The ESP32 is a dual-core system from Expressif with two Harvard architecture Xtensa LX6 CPUs. All embedded memory, external memory and @@ -13,7 +13,8 @@ README for the Expressif ESP32 Core board (V2) "application"), however for most purposes the two CPUs are interchangeable. - Features: +ESP32 Features +============== * Address Space - Symmetric address mapping @@ -43,7 +44,9 @@ README for the Expressif ESP32 Core board (V2) ESP32 Toolchain =============== - The steps to build toolchain with crosstool-NG on Linux are as follows: + You must use the custom Xtensa toolchain in order to build the ESP32 Core + BSP. The steps to build toolchain with crosstool-NG on Linux are as + follows: git clone -b xtensa-1.22.x https://github.com/espressif/crosstool-NG.git cd crosstool-NG @@ -55,5 +58,5 @@ ESP32 Toolchain These steps are given in setup guide in ESP-IDF repository: https://github.com/espressif/esp-idf/blob/master/docs/linux-setup.rst#alternative-step-1-compile-the-toolchain-from-source-using-crosstool-ng - NOTE: the xtensa-esp32-elf configuration is only available in the + NOTE: The xtensa-esp32-elf configuration is only available in the xtensa-1.22.x branch. -- GitLab From ad6856c931ed92929b607e5d22fec3d3c24e35b1 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 14 Oct 2016 11:12:49 -0600 Subject: [PATCH 070/734] Trivial stylistic changes from review of last PR --- arch/arm/src/stm32l4/stm32l4_pwm.c | 19 +++++++--------- configs/nucleo-l476rg/src/stm32_pwm.c | 32 ++++++++++++++------------- 2 files changed, 25 insertions(+), 26 deletions(-) diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.c b/arch/arm/src/stm32l4/stm32l4_pwm.c index f45e4c1384..80214fb9e5 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.c +++ b/arch/arm/src/stm32l4/stm32l4_pwm.c @@ -128,7 +128,7 @@ struct stm32l4_pwmchan_s uint8_t channel; /* Timer output channel: {1,..4} */ uint32_t pincfg; /* Output pin configuration */ enum stm32l4_chanmode_e mode; - uint32_t npincfg; /* Complementary output pin configuration (only TIM1/8 CH1-3)*/ + uint32_t npincfg; /* Complementary output pin configuration (only TIM1/8 CH1-3)*/ }; /* This structure represents the state of one PWM timer */ @@ -996,10 +996,10 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv, /* Handle channel specific setup */ - ccenable = 0; + ccenable = 0; ccnenable = 0; - ocmode1 = 0; - ocmode2 = 0; + ocmode1 = 0; + ocmode2 = 0; #ifdef CONFIG_PWM_MULTICHAN for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) @@ -1104,7 +1104,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv, /* Conditionnaly enable the complementary output */ - if(compout) + if (compout) { ccnenable |= ATIM_CCER_CC1NE; } @@ -1134,7 +1134,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv, /* Conditionnaly enable the complementary output */ - if(compout) + if (compout) { ccnenable |= ATIM_CCER_CC2NE; } @@ -1164,7 +1164,7 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv, /* Conditionnaly enable the complementary output */ - if(compout) + if (compout) { ccnenable |= ATIM_CCER_CC3NE; } @@ -1289,14 +1289,13 @@ static int stm32l4pwm_timer(FAR struct stm32l4_pwmtimer_s *priv, */ ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP); - ccer |= ccnenable; } else #endif #endif { - ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP); //Not sure why ?? + ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP); /* Not sure why? */ } /* Save the modified register values */ @@ -1783,7 +1782,6 @@ static int stm32l4pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) pwminfo("pincfg: %08x\n", pincfg); pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= GPIO_INPUT | GPIO_FLOAT; stm32l4_configgpio(pincfg); @@ -1795,7 +1793,6 @@ static int stm32l4pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) pwminfo("npincfg: %08x\n", pincfg); pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= GPIO_INPUT | GPIO_FLOAT; stm32l4_configgpio(pincfg); diff --git a/configs/nucleo-l476rg/src/stm32_pwm.c b/configs/nucleo-l476rg/src/stm32_pwm.c index 0f753844bb..f5c00a1a64 100644 --- a/configs/nucleo-l476rg/src/stm32_pwm.c +++ b/configs/nucleo-l476rg/src/stm32_pwm.c @@ -96,14 +96,15 @@ int board_pwm_setup(void) if (!initialized) { /* Call stm32l4_pwminitialize() to get an instance of the PWM interface */ -/* PWM - * - * The Nucleo-l476rg has no real on-board PWM devices, but the board can be - * configured to output a pulse train using TIM1 or 8, or others (see board.h). - * Let's figure out which the user has configured. - */ -# if defined(CONFIG_STM32L4_TIM1_PWM) + /* PWM + * + * The Nucleo-l476rg has no real on-board PWM devices, but the board can be + * configured to output a pulse train using TIM1 or 8, or others (see board.h). + * Let's figure out which the user has configured. + */ + +#if defined(CONFIG_STM32L4_TIM1_PWM) pwm = stm32l4_pwminitialize(1); if (!pwm) { @@ -121,7 +122,7 @@ int board_pwm_setup(void) } #endif -# if defined(CONFIG_STM32L4_TIM2_PWM) +#if defined(CONFIG_STM32L4_TIM2_PWM) pwm = stm32l4_pwminitialize(2); if (!pwm) { @@ -139,7 +140,7 @@ int board_pwm_setup(void) } #endif -# if defined(CONFIG_STM32L4_TIM3_PWM) +#if defined(CONFIG_STM32L4_TIM3_PWM) pwm = stm32l4_pwminitialize(3); if (!pwm) { @@ -157,7 +158,7 @@ int board_pwm_setup(void) } #endif -# if defined(CONFIG_STM32L4_TIM4_PWM) +#if defined(CONFIG_STM32L4_TIM4_PWM) pwm = stm32l4_pwminitialize(4); if (!pwm) { @@ -175,7 +176,7 @@ int board_pwm_setup(void) } #endif -# if defined(CONFIG_STM32L4_TIM5_PWM) +#if defined(CONFIG_STM32L4_TIM5_PWM) pwm = stm32l4_pwminitialize(5); if (!pwm) { @@ -193,7 +194,7 @@ int board_pwm_setup(void) } #endif -# if defined(CONFIG_STM32L4_TIM8_PWM) +#if defined(CONFIG_STM32L4_TIM8_PWM) pwm = stm32l4_pwminitialize(8); if (!pwm) { @@ -211,7 +212,7 @@ int board_pwm_setup(void) } #endif -# if defined(CONFIG_STM32L4_TIM15_PWM) +#if defined(CONFIG_STM32L4_TIM15_PWM) pwm = stm32l4_pwminitialize(15); if (!pwm) { @@ -229,7 +230,7 @@ int board_pwm_setup(void) } #endif -# if defined(CONFIG_STM32L4_TIM16_PWM) +#if defined(CONFIG_STM32L4_TIM16_PWM) pwm = stm32l4_pwminitialize(16); if (!pwm) { @@ -247,7 +248,7 @@ int board_pwm_setup(void) } #endif -# if defined(CONFIG_STM32L4_TIM17_PWM) +#if defined(CONFIG_STM32L4_TIM17_PWM) pwm = stm32l4_pwminitialize(17); if (!pwm) { @@ -273,3 +274,4 @@ int board_pwm_setup(void) } #endif /* CONFIG_PWM */ + -- GitLab From e3ead1db697c3397a46cb08a52e12374caf37c0a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 14 Oct 2016 13:17:48 -0600 Subject: [PATCH 071/734] Xtensa: Add an initial guess at the form of struct xcpcontext --- arch/xtensa/Kconfig | 16 +++++++ arch/xtensa/include/irq.h | 97 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 113 insertions(+) diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 3ba3a48ec3..1bd5c0f54d 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -29,6 +29,22 @@ config ARCH_FAMILY_LX6 Cadence® Tensilica® Xtensa® LX6 data plane processing unit (DPU). The LX6 is a configurable and extensible processor core. +config XTENSA_HAVE_LOOPS + bool "Zero overhead loops" + default n + +config XTENSA_USE_SWPRI + bool "Use SWPRI" + default n + +config XTENSA_CALL0_ABI + bool "CALL0 ABI" + default y + +config XTENSA_USE_OVLY + bool "Use overlay" + default n + config ARCH_CHIP string default "esp32" if ARCH_CHIP_ESP32 diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index ed10e3bbb1..3e8dfd4666 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -69,12 +69,109 @@ * Pre-processor Definitions ****************************************************************************/ +/* IRQ Stack Frame Format. Each value is a uint32_t register index */ + +#define REG_EXIT (0) /* Exit point for dispatch */ +#define REG_PC (1) /* Return PC */ +#define REG_PS (2) /* Return PS */ +#define REG_A0 (3) +#define REG_A1 (4) /* Stack pointer before interrupt */ +#define REG_A2 (5) +#define REG_A3 (6) +#define REG_A4 (7) +#define REG_A5 (8) +#define REG_A6 (9) +#define REG_A7 (10) +#define REG_A8 (11) +#define REG_A9 (12) +#define REG_A10 (13) +#define REG_A11 (14) +#define REG_A12 (15) +#define REG_A13 (16) +#define REG_A14 (17) +#define REG_A15 (18) +#define REG_SAR (19) +#define REG_EXCCAUSE (20) +#define REG_EXCVADDR (21) +#define _REG_LOOPS_START (22) + +#if CONFIG_XTENSA_HAVE_LOOPS +# define REG_LBEG (_REG_LOOPS_START + 0) +# define REG_LEND (_REG_LOOPS_START + 1) +# define REG_LCOUNT (_REG_LOOPS_START + 2) +# define _REG_CALL0_START (_REG_LOOPS_START + 3) +#else +# define _REG_CALL0_START _REG_LOOPS_START +#endif + +#ifndef CONFIG_XTENSA_CALL0_ABI + /* Temporary space for saving stuff during window spill */ + +# define REG_TMP0 (_REG_CALL0_START + 0) +# define REG_TMP1 (_REG_CALL0_START + 1) +# define REG_TMP2 (_REG_CALL0_START + 2) +# define _REG_SWPRI_START (_REG_CALL0_START + 3) +#else +# define _REG_SWPRI_START _REG_CALL0_START +#endif + +#ifdef CONFIG_XTENSA_USE_SWPRI + /* Storage for virtual priority mask */ + +# define REG_VPRI (_REG_SWPRI_START + 0) +# define _REG_OVLY_START (_REG_SWPRI_START + 1) +#else +# define _REG_OVLY_START _REG_SWPRI_START +#endif + +#ifdef CONFIG_XTENSA_USE_OVLY +/* Storage for overlay state */ + +# define REG_OVLY (_REG_OVLY_START + 0) +# define XCPTCONTEXT_REGS (_REG_OVLY_START + 1) +#else +# define XCPTCONTEXT_REGS _REG_OVLY_START +#endif + +#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS) + /**************************************************************************** * Public Types ****************************************************************************/ #ifndef __ASSEMBLY__ +/* This struct defines the way the registers are stored. */ + +struct xcptcontext +{ + /* The following function pointer is non-zero if there are pending signals + * to be processed. + */ + +#ifndef CONFIG_DISABLE_SIGNALS + void *sigdeliver; /* Actual type is sig_deliver_t */ + + /* These are saved copies of registers used during signal processing. */ + + uint32_t saved_pc; + uint32_t saved_cpsr; +#endif + + /* Register save area */ + + uint32_t regs[XCPTCONTEXT_REGS]; + +#ifdef CONFIG_LIB_SYSCALL + /* The following array holds the return address and the exc_return value + * needed to return from each nested system call. + */ + + uint8_t nsyscalls; + struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST]; +#endif +}; + /**************************************************************************** * Inline functions ****************************************************************************/ -- GitLab From 5b46ce4889e034bd2def7367563b62b4122dcb61 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 14 Oct 2016 17:39:21 -0600 Subject: [PATCH 072/734] Cosmetic changes from review of last PR --- arch/arm/src/kinetis/kinetis_uid.c | 28 +++++++++++++------------ arch/arm/src/kinetis/kinetis_uid.h | 21 ++++++++++++------- configs/freedom-k64f/src/Makefile | 1 + configs/freedom-k64f/src/k64_uid.c | 24 ++++++++++++--------- configs/freedom-k64f/src/k64_userleds.c | 3 ++- 5 files changed, 46 insertions(+), 31 deletions(-) diff --git a/arch/arm/src/kinetis/kinetis_uid.c b/arch/arm/src/kinetis/kinetis_uid.c index 54a98d08ce..954c667f41 100644 --- a/arch/arm/src/kinetis/kinetis_uid.c +++ b/arch/arm/src/kinetis/kinetis_uid.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/kinetis_uid.c * * Copyright (C) 2016 Neil Hancock. All rights reserved. @@ -30,11 +30,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -44,25 +44,27 @@ #ifdef CONFIG_BOARDCTL_UNIQUEID -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ + +/**************************************************************************** + * Name: kinetis_get_uniqueid + ****************************************************************************/ void kinetis_get_uniqueid(uint8_t *uniqueid) { - int i; uint32_t *unique_u32; + int i; + unique_u32 = (uint32_t *)uniqueid; - /* - * Copy into buffer LS first, which in the Kinetis is the highest memory - */ + /* Copy into buffer LS first, which in the Kinetis is the highest memory */ - for (i = 0; i < (KINETIS_UID_SIZE/sizeof(uint32_t)); i++) + for (i = 0; i < (KINETIS_UID_SIZE / sizeof(uint32_t)); i++) { - unique_u32[i] = *((uint32_t*)(KINETIS_SIM_UIDL)-i); + unique_u32[i] = *((uint32_t*)(KINETIS_SIM_UIDL) - i); } } #endif /* CONFIG_BOARDCTL_UNIQUEID */ - diff --git a/arch/arm/src/kinetis/kinetis_uid.h b/arch/arm/src/kinetis/kinetis_uid.h index 84620f53e5..29299da582 100644 --- a/arch/arm/src/kinetis/kinetis_uid.h +++ b/arch/arm/src/kinetis/kinetis_uid.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/kinetis/kinetis_uid.h * * Copyright (C) 2016 Neil Hancock. All rights reserved. @@ -30,20 +30,27 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_UID_H #define __ARCH_ARM_SRC_KINETIS_UID_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + #define KINETIS_UID_SIZE 16 + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + void kinetis_get_uniqueid(uint8_t *uniqueid); + #endif /* __ARCH_ARM_SRC_KINETIS_UID_H */ diff --git a/configs/freedom-k64f/src/Makefile b/configs/freedom-k64f/src/Makefile index 7da96029aa..e11590bbc1 100644 --- a/configs/freedom-k64f/src/Makefile +++ b/configs/freedom-k64f/src/Makefile @@ -76,4 +76,5 @@ endif ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) CSRCS += k64_uid.c endif + include $(TOPDIR)/configs/Board.mk diff --git a/configs/freedom-k64f/src/k64_uid.c b/configs/freedom-k64f/src/k64_uid.c index 545de899c0..0fc1527637 100644 --- a/configs/freedom-k64f/src/k64_uid.c +++ b/configs/freedom-k64f/src/k64_uid.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * configs/freedom-k64/src/kinetis_uid.c * * Copyright (C) 2016 Neil Hancock. All rights reserved. @@ -30,11 +30,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -45,19 +45,23 @@ #include -/************************************************************************************ +#if defined(CONFIG_BOARDCTL_UNIQUEID) + +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #ifndef OK # define OK 0 #endif -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -#if defined(CONFIG_BOARDCTL_UNIQUEID) +/**************************************************************************** + * Name: board_uniqueid + ****************************************************************************/ int board_uniqueid(FAR uint8_t *uniqueid) { @@ -70,4 +74,4 @@ int board_uniqueid(FAR uint8_t *uniqueid) return OK; } -#endif +#endif /* CONFIG_BOARDCTL_UNIQUEID */ diff --git a/configs/freedom-k64f/src/k64_userleds.c b/configs/freedom-k64f/src/k64_userleds.c index e75a2abb8e..8b334823a5 100644 --- a/configs/freedom-k64f/src/k64_userleds.c +++ b/configs/freedom-k64f/src/k64_userleds.c @@ -107,4 +107,5 @@ void board_userled_all(uint8_t ledset) kinetis_gpiowrite(GPIO_LED_G, (ledset & BOARD_LED_G_BIT) == 0); kinetis_gpiowrite(GPIO_LED_B, (ledset & BOARD_LED_B_BIT) == 0); } -#endif + +#endif /* CONFIG_ARCH_LEDS */ -- GitLab From 909ea5e8efbb57a9a37752dd1cae894fd051f1e8 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Sat, 15 Oct 2016 03:55:48 -1000 Subject: [PATCH 073/734] F4 Support versampling by 8 --- arch/arm/src/stm32/stm32_serial.c | 56 ++++++++++++++++++++++++------- 1 file changed, 43 insertions(+), 13 deletions(-) diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c index eeb5a846a7..381df6c016 100644 --- a/arch/arm/src/stm32/stm32_serial.c +++ b/arch/arm/src/stm32/stm32_serial.c @@ -1190,15 +1190,20 @@ static void up_set_format(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; uint32_t regval; + uint32_t brr; + + /* Load CR1 */ + + regval = up_serialin(priv, STM32_USART_CR1_OFFSET); #if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) /* This first implementation is for U[S]ARTs that support oversampling * by 8 in additional to the standard oversampling by 16. + * With baud rate of fCK / Divider for oversampling by 16. + * and baud rate of 2 * fCK / Divider for oversampling by 8 */ uint32_t usartdiv8; - uint32_t cr1; - uint32_t brr; /* In case of oversampling by 8, the equation is: * @@ -1218,7 +1223,6 @@ static void up_set_format(struct uart_dev_s *dev) /* Use oversamply by 8 only if the divisor is small. But what is small? */ - cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET); if (usartdiv8 > 100) { /* Use usartdiv16 */ @@ -1227,7 +1231,7 @@ static void up_set_format(struct uart_dev_s *dev) /* Clear oversampling by 8 to enable oversampling by 16 */ - cr1 &= ~USART_CR1_OVER8; + regval &= ~USART_CR1_OVER8; } else { @@ -1239,12 +1243,9 @@ static void up_set_format(struct uart_dev_s *dev) /* Set oversampling by 8 */ - cr1 |= USART_CR1_OVER8; + regval |= USART_CR1_OVER8; } - up_serialout(priv, STM32_USART_CR1_OFFSET, cr1); - up_serialout(priv, STM32_USART_BRR_OFFSET, brr); - #else /* This second implementation is for U[S]ARTs that support fractional @@ -1254,7 +1255,6 @@ static void up_set_format(struct uart_dev_s *dev) uint32_t usartdiv32; uint32_t mantissa; uint32_t fraction; - uint32_t brr; /* Configure the USART Baud Rate. The baud rate for the receiver and * transmitter (Rx and Tx) are both set to the same value as programmed @@ -1272,23 +1272,53 @@ static void up_set_format(struct uart_dev_s *dev) * usartdiv32 = 32 * usartdiv = fCK / (baud/2) */ - usartdiv32 = priv->apbclock / (priv->baud >> 1); + usartdiv32 = priv->apbclock / (priv->baud >> 1); /* The mantissa part is then */ mantissa = usartdiv32 >> 5; - brr = mantissa << USART_BRR_MANT_SHIFT; /* The fractional remainder (with rounding) */ fraction = (usartdiv32 - (mantissa << 5) + 1) >> 1; + +#if defined(CONFIG_STM32_STM32F40XX) + + /* The F4 supports 8 X in oversampling additional to the + * standard oversampling by 16. + * With baud rate of fCK / (16 * Divider) for oversampling by 16. + * and baud rate of fCK / (8 * Divider) for oversampling by 8 + */ + + /* Check if 8x oversampling is necessary */ + + if (mantissa == 0) + { + regval |= USART_CR1_OVER8; + + /* Rescale the mantissa */ + + mantissa = usartdiv32 >> 4; + + /* The fractional remainder (with rounding) */ + + fraction = (usartdiv32 - (mantissa << 4) + 1) >> 1; + } + else + {/* Use 16x Oversampling */ + regval &= ~USART_CR1_OVER8; + } +#endif + + brr = mantissa << USART_BRR_MANT_SHIFT; brr |= fraction << USART_BRR_FRAC_SHIFT; - up_serialout(priv, STM32_USART_BRR_OFFSET, brr); #endif + up_serialout(priv, STM32_USART_CR1_OFFSET, regval); + up_serialout(priv, STM32_USART_BRR_OFFSET, brr); + /* Configure parity mode */ - regval = up_serialin(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M); if (priv->parity == 1) /* Odd parity */ -- GitLab From 6f35ced002226385c294c2410db00df607cd47c7 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 15 Oct 2016 08:39:15 -0600 Subject: [PATCH 074/734] ESP32: Add peripheral interrupt IRQ numbers --- arch/xtensa/include/esp32/irq.h | 133 ++++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) diff --git a/arch/xtensa/include/esp32/irq.h b/arch/xtensa/include/esp32/irq.h index d67ea04794..058833dc9b 100644 --- a/arch/xtensa/include/esp32/irq.h +++ b/arch/xtensa/include/esp32/irq.h @@ -49,6 +49,139 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +/* Exceptions + * + * IRAM Offset Description + * 0x0000 Windows + * 0x0180 Level 2 interrupt + * 0x01c0 Level 3 interrupt + * 0x0200 Level 4 interrupt + * 0x0240 Level 5 interrupt + * 0x0280 Debug exception + * 0x02c0 NMI exception + * 0x0300 Kernel exception + * 0x0340 User exception + * 0x03c0 Double exception + * + * REVISIT: In more architectures supported by NuttX, exception errors + * tie into the normal interrupt handling via special IRQ numbers. I + * is still to be determined what will be done for the the ESP32. + */ + +/* Interrupt Matrix + * + * The Interrupt Matrix embedded in the ESP32 independently allocates + * peripheral interrupt sources to the two CPUs’ peripheral interrupts. This + * configuration is highly flexible in order to meet many different needs. + * + * Features + * - Accepts 71 peripheral interrupt sources as input. + * - Generates 26 peripheral interrupt sources per CPU as output (52 total). + * - CPU NMI Interrupt Mask. + * - Queries current interrupt status of peripheral interrupt sources. + * + * Peripheral Interrupt Source + * + * ESP32 has 71 peripheral interrupt sources in total. 67 of 71 ESP32 + * peripheral interrupt sources can be allocated to either CPU. The four + * remaining peripheral interrupt sources are CPU-specific, two per CPU. + * + * - GPIO_INTERRUPT_PRO and GPIO_INTERRUPT_PRO_NMI can only be allocated to + * PRO_CPU. + * - GPIO_INTERRUPT_APP and GPIO_INTERRUPT_APP_NMI can only be allocated to + * APP_CPU. + * + * As a result, PRO_CPU and APP_CPU each have 69 peripheral interrupt + * sources. + */ + +/* PRO_INTR_STATUS_REG_0 / APP_INTR_STATUS_REG_0 */ + +#define XTENSA_IRQ_MAC 0 /* 1. *_INTR_STATUS_REG_0, bit 0 */ +#define XTENSA_IRQ_MAC_NMI 1 /* 2. *_INTR_STATUS_REG_0, bit 1 */ +#define XTENSA_IRQ_BB 2 /* 3. *_INTR_STATUS_REG_0, bit 2 */ +#define XTENSA_IRQ_BB_MAC 3 /* 4. *_INTR_STATUS_REG_0, bit 3 */ +#define XTENSA_IRQ_BT_BB 4 /* 5. *_INTR_STATUS_REG_0, bit 4 */ +#define XTENSA_IRQ_BT_BB_NMI 5 /* 6. *_INTR_STATUS_REG_0, bit 5 */ +#define XTENSA_IRQ_RWBT_IRQ 6 /* 7. *_INTR_STATUS_REG_0, bit 6 */ +#define XTENSA_IRQ_RWBLE_IRQ 7 /* 8. *_INTR_STATUS_REG_0, bit 7 */ +#define XTENSA_IRQ_RWBT_NMI 8 /* 9. *_INTR_STATUS_REG_0, bit 8 */ +#define XTENSA_IRQ_RWBLE_NMI 9 /* 10. *_INTR_STATUS_REG_0, bit 9 */ + +#define XTENSA_IRQ_SLC0 10 /* 11. *_INTR_STATUS_REG_0, bit 10 */ +#define XTENSA_IRQ_SLC1 11 /* 12. *_INTR_STATUS_REG_0, bit 11 */ +#define XTENSA_IRQ_UHCI0 12 /* 13. *_INTR_STATUS_REG_0, bit 12 */ +#define XTENSA_IRQ_UHCI1 13 /* 14. *_INTR_STATUS_REG_0, bit 13 */ +#define XTENSA_IRQ_TG_T0_LEVEL 14 /* 15. *_INTR_STATUS_REG_0, bit 14 */ +#define XTENSA_IRQ_TG_T1_LEVEL 15 /* 16. *_INTR_STATUS_REG_0, bit 15 */ +#define XTENSA_IRQ_TG_WDT_LEVEL 16 /* 17. *_INTR_STATUS_REG_0, bit 16 */ +#define XTENSA_IRQ_TG_LACT_LEVEL 17 /* 18. *_INTR_STATUS_REG_0, bit 17 */ +#define XTENSA_IRQ_TG1_T0_LEVEL 18 /* 19. *_INTR_STATUS_REG_0, bit 18 */ +#define XTENSA_IRQ_TG1_T1_LEVEL 19 /* 20. *_INTR_STATUS_REG_0, bit 19 */ + +#define XTENSA_IRQ_TG1_WDT_LEVEL 20 /* 21. *_INTR_STATUS_REG_0, bit 20 */ +#define XTENSA_IRQ_G1_LACT_LEVEL 21 /* 22. *_INTR_STATUS_REG_0, bit 21 */ +#define XTENSA_IRQ_CPU_GPIO 22 /* 23. *_INTR_STATUS_REG_0, bit 22 */ +#define XTENSA_IRQ_CPU_NMI 23 /* 24. *_INTR_STATUS_REG_0, bit 23 */ +#define XTENSA_IRQ_CPU_CPU0 24 /* 25. *_INTR_STATUS_REG_0, bit 24 */ +#define XTENSA_IRQ_CPU_CPU1 25 /* 26. *_INTR_STATUS_REG_0, bit 25 */ +#define XTENSA_IRQ_CPU_CPU2 26 /* 27. *_INTR_STATUS_REG_0, bit 26 */ +#define XTENSA_IRQ_CPU_CPU3 27 /* 28. *_INTR_STATUS_REG_0, bit 27 */ +#define XTENSA_IRQ_SPI0 28 /* 29. *_INTR_STATUS_REG_0, bit 28 */ +#define XTENSA_IRQ_SPI1 29 /* 30. *_INTR_STATUS_REG_0, bit 29 */ + +#define XTENSA_IRQ_SPI2 30 /* 31. *_INTR_STATUS_REG_0, bit 30 */ +#define XTENSA_IRQ_SPI3 31 /* 32. *_INTR_STATUS_REG_0, bit 31 */ + +/* PRO_INTR_STATUS_REG_1 / APP_INTR_STATUS_REG_1 */ + +#define XTENSA_IRQ_I2S0 32 /* 33. *_INTR_STATUS_REG_1, bit 0 */ +#define XTENSA_IRQ_I2S1 33 /* 34. *_INTR_STATUS_REG_1, bit 1 */ +#define XTENSA_IRQ_UART 34 /* 35. *_INTR_STATUS_REG_1, bit 2 */ +#define XTENSA_IRQ_UART1 35 /* 36. *_INTR_STATUS_REG_1, bit 3 */ +#define XTENSA_IRQ_UART2 36 /* 37. *_INTR_STATUS_REG_1, bit 4 */ +#define XTENSA_IRQ_SDIO_HOST 37 /* 38. *_INTR_STATUS_REG_1, bit 5 */ +#define XTENSA_IRQ_EMAC 38 /* 39. *_INTR_STATUS_REG_1, bit 6 */ +#define XTENSA_IRQ_PWM0 39 /* 40. *_INTR_STATUS_REG_1, bit 7 */ +#define XTENSA_IRQ_PWM1 40 /* 41. *_INTR_STATUS_REG_1, bit 8 */ +#define XTENSA_IRQ_PWM2 41 /* 42. *_INTR_STATUS_REG_1, bit 9 */ + +#define XTENSA_IRQ_PWM3 42 /* 43. *_INTR_STATUS_REG_1, bit 10 */ +#define XTENSA_IRQ_LEDC 43 /* 44. *_INTR_STATUS_REG_1, bit 11 */ +#define XTENSA_IRQ_EFUSE 44 /* 45. *_INTR_STATUS_REG_1, bit 12 */ +#define XTENSA_IRQ_CAN 45 /* 46. *_INTR_STATUS_REG_1, bit 13 */ +#define XTENSA_IRQ_RTC_CORE 46 /* 47. *_INTR_STATUS_REG_1, bit 14 */ +#define XTENSA_IRQ_RMT 47 /* 48. *_INTR_STATUS_REG_1, bit 15 */ +#define XTENSA_IRQ_PCNT 48 /* 49. *_INTR_STATUS_REG_1, bit 16 */ +#define XTENSA_IRQ_I2C_EXT0 49 /* 50. *_INTR_STATUS_REG_1, bit 17 */ +#define XTENSA_IRQ_I2C_EXT1 50 /* 51. *_INTR_STATUS_REG_1, bit 18 */ +#define XTENSA_IRQ_RSA 51 /* 52. *_INTR_STATUS_REG_1, bit 19 */ + +#define XTENSA_IRQ_SPI1_DMA 52 /* 53. *_INTR_STATUS_REG_1, bit 20 */ +#define XTENSA_IRQ_SPI2_DMA 53 /* 54. *_INTR_STATUS_REG_1, bit 21 */ +#define XTENSA_IRQ_SPI3_DMA 54 /* 55. *_INTR_STATUS_REG_1, bit 22 */ +#define XTENSA_IRQ_WDG 55 /* 56. *_INTR_STATUS_REG_1, bit 23 */ +#define XTENSA_IRQ_TIMER1 56 /* 57. *_INTR_STATUS_REG_1, bit 24 */ +#define XTENSA_IRQ_TIMER2 57 /* 58. *_INTR_STATUS_REG_1, bit 25 */ +#define XTENSA_IRQ_TG_T0_EDGE 58 /* 59. *_INTR_STATUS_REG_1, bit 26 */ +#define XTENSA_IRQ_TG_T1_EDGE 59 /* 60. *_INTR_STATUS_REG_1, bit 27 */ +#define XTENSA_IRQ_TG_WDT_EDGE 60 /* 61. *_INTR_STATUS_REG_1, bit 28 */ +#define XTENSA_IRQ_TG_LACT_EDGE 61 /* 62. *_INTR_STATUS_REG_1, bit 29 */ + +#define XTENSA_IRQ_TG1_T0_EDGE 62 /* 63. *_INTR_STATUS_REG_1, bit 30 */ +#define XTENSA_IRQ_TG1_T1_EDGE 63 /* 64. *_INTR_STATUS_REG_1, bit 31 */ + +/* PRO_INTR_STATUS_REG_2 / APP_INTR_STATUS_REG_2 */ + +#define XTENSA_IRQ_TG1_WDT_EDGE 64 /* 65. *_INTR_STATUS_REG_2, bit 0 */ +#define XTENSA_IRQ_TG1_LACT_EDGE 65 /* 66. *_INTR_STATUS_REG_2, bit 1 */ +#define XTENSA_IRQ_MMU_IA 66 /* 67. *_INTR_STATUS_REG_2, bit 2 */ +#define XTENSA_IRQ_MPU_IA 67 /* 68. *_INTR_STATUS_REG_2, bit 3 */ +#define XTENSA_IRQ_CACHE_IA 68 /* 69. *_INTR_STATUS_REG_2, bit 4 */ + +/* Total number of interrupts */ + +#define NR_IRQS 69 /**************************************************************************** * Public Types -- GitLab From 30598c005f59d40d56cb6eb5551b0fc0a2c2bbf7 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 15 Oct 2016 08:56:11 -0600 Subject: [PATCH 075/734] Cosmetic changes from review of last PR --- arch/arm/src/stm32/stm32_serial.c | 45 ++++++++++++++++--------------- 1 file changed, 23 insertions(+), 22 deletions(-) diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c index 381df6c016..6152d5795d 100644 --- a/arch/arm/src/stm32/stm32_serial.c +++ b/arch/arm/src/stm32/stm32_serial.c @@ -1189,6 +1189,13 @@ static int up_dma_nextrx(struct up_dev_s *priv) static void up_set_format(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) + uint32_t usartdiv8; +#else + uint32_t usartdiv32; + uint32_t mantissa; + uint32_t fraction; +#endif uint32_t regval; uint32_t brr; @@ -1201,11 +1208,8 @@ static void up_set_format(struct uart_dev_s *dev) * by 8 in additional to the standard oversampling by 16. * With baud rate of fCK / Divider for oversampling by 16. * and baud rate of 2 * fCK / Divider for oversampling by 8 - */ - - uint32_t usartdiv8; - - /* In case of oversampling by 8, the equation is: + * + * In case of oversampling by 8, the equation is: * * baud = 2 * fCK / usartdiv8 * usartdiv8 = 2 * fCK / baud @@ -1219,10 +1223,10 @@ static void up_set_format(struct uart_dev_s *dev) * baud = fCK / usartdiv16 * usartdiv16 = fCK / baud * = 2 * usartdiv8 + * + * Use oversamply by 8 only if the divisor is small. But what is small? */ - /* Use oversamply by 8 only if the divisor is small. But what is small? */ - if (usartdiv8 > 100) { /* Use usartdiv16 */ @@ -1247,16 +1251,10 @@ static void up_set_format(struct uart_dev_s *dev) } #else - /* This second implementation is for U[S]ARTs that support fractional * dividers. - */ - - uint32_t usartdiv32; - uint32_t mantissa; - uint32_t fraction; - - /* Configure the USART Baud Rate. The baud rate for the receiver and + * + * Configure the USART Baud Rate. The baud rate for the receiver and * transmitter (Rx and Tx) are both set to the same value as programmed * in the Mantissa and Fraction values of USARTDIV. * @@ -1283,9 +1281,9 @@ static void up_set_format(struct uart_dev_s *dev) fraction = (usartdiv32 - (mantissa << 5) + 1) >> 1; #if defined(CONFIG_STM32_STM32F40XX) - /* The F4 supports 8 X in oversampling additional to the * standard oversampling by 16. + * * With baud rate of fCK / (16 * Divider) for oversampling by 16. * and baud rate of fCK / (8 * Divider) for oversampling by 8 */ @@ -1300,18 +1298,20 @@ static void up_set_format(struct uart_dev_s *dev) mantissa = usartdiv32 >> 4; - /* The fractional remainder (with rounding) */ + /* The fractional remainder (with rounding) */ - fraction = (usartdiv32 - (mantissa << 4) + 1) >> 1; + fraction = (usartdiv32 - (mantissa << 4) + 1) >> 1; } else - {/* Use 16x Oversampling */ + { + /* Use 16x Oversampling */ + regval &= ~USART_CR1_OVER8; } #endif - brr = mantissa << USART_BRR_MANT_SHIFT; - brr |= fraction << USART_BRR_FRAC_SHIFT; + brr = mantissa << USART_BRR_MANT_SHIFT; + brr |= fraction << USART_BRR_FRAC_SHIFT; #endif up_serialout(priv, STM32_USART_CR1_OFFSET, regval); @@ -1364,7 +1364,8 @@ static void up_set_format(struct uart_dev_s *dev) regval = up_serialin(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && \ + !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; -- GitLab From 0b3c75f6bd50908adb19ea37d5355fd18a60334e Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Sat, 15 Oct 2016 05:15:40 -1000 Subject: [PATCH 076/734] Fixes sscan %sn where strlen(data) < n --- libc/stdio/lib_sscanf.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/libc/stdio/lib_sscanf.c b/libc/stdio/lib_sscanf.c index ae8774cc57..50125e9bff 100644 --- a/libc/stdio/lib_sscanf.c +++ b/libc/stdio/lib_sscanf.c @@ -164,7 +164,7 @@ int sscanf(FAR const char *buf, FAR const char *fmt, ...) * ANSI standard vsscanf implementation. * ****************************************************************************/ - +#pragma GCC optimize ("O0") int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) { FAR const char *bufstart; @@ -174,6 +174,7 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) bool noassign; int count; int width; + int fwidth; int base = 10; char tmp[MAXLN]; @@ -275,16 +276,22 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) buf++; } - /* Was a fieldwidth specified? */ + /* Guess a field width using some heuristics */ - if (!width) - { - /* No... Guess a field width using some heuristics */ + fwidth = findwidth(buf, fmt); - int tmpwidth = findwidth(buf, fmt); - width = MIN(sizeof(tmp) - 1, tmpwidth); + /* Use the actual field's width if 1) no fieldwidth + * specified or 2) the actual field's width is smaller + * than fieldwidth specified + */ + + if (!width || fwidth < width) + { + width = fwidth; } + width = MIN(sizeof(tmp) - 1, width); + /* Copy the string (if we are making an assignment) */ if (!noassign) -- GitLab From 55b798c35758bd53f0ae8b499dca5869cdc6e75c Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Sat, 15 Oct 2016 05:23:18 -1000 Subject: [PATCH 077/734] Indented --- libc/stdio/lib_sscanf.c | 201 +++++++++++++++++----------------------- 1 file changed, 87 insertions(+), 114 deletions(-) diff --git a/libc/stdio/lib_sscanf.c b/libc/stdio/lib_sscanf.c index 50125e9bff..3e8cd6c9ec 100644 --- a/libc/stdio/lib_sscanf.c +++ b/libc/stdio/lib_sscanf.c @@ -93,8 +93,7 @@ static int findwidth(FAR const char *buf, FAR const char *fmt) FAR const char *next = fmt + 1; /* No... is there a space after the format? Or does the format string end - * here? - */ + * here? */ if (isspace(*next) || *next == 0) { @@ -103,15 +102,13 @@ static int findwidth(FAR const char *buf, FAR const char *fmt) return strcspn(buf, spaces); } - /* No.. Another possibility is the format character is followed by - * some recognizable delimiting value. - */ + /* No.. Another possibility is the format character is followed by some + * recognizable delimiting value. */ if (*next != '%') { /* If so we will say that the string ends there if we can find that - * delimiter in the input string. - */ + * delimiter in the input string. */ FAR const char *ptr = strchr(buf, *next); if (ptr) @@ -120,16 +117,14 @@ static int findwidth(FAR const char *buf, FAR const char *fmt) } } - /* No... the format has no delimiter and is back-to-back with the next - * format (or is followed by a delimiter that does not exist in the - * input string). At this point we just bail and Use the input up until - * the first white space is encountered. - * - * NOTE: This means that values from the following format may be - * concatenated with the first. This is a bug. We have no generic way of - * determining the width of the data if there is no fieldwidth, no space - * separating the input, and no usable delimiter character. - */ + /* No... the format has no delimiter and is back-to-back with the next format + * (or is followed by a delimiter that does not exist in the input string). + * At this point we just bail and Use the input up until the first white + * space is encountered. NOTE: This means that values from the following + * format may be concatenated with the first. This is a bug. We have no + * generic way of determining the width of the data if there is no + * fieldwidth, no space separating the input, and no usable delimiter + * character. */ return strcspn(buf, spaces); } @@ -149,7 +144,7 @@ static int findwidth(FAR const char *buf, FAR const char *fmt) int sscanf(FAR const char *buf, FAR const char *fmt, ...) { va_list ap; - int count; + int count; va_start(ap, fmt); count = vsscanf((FAR const char *)buf, fmt, ap); @@ -168,35 +163,33 @@ int sscanf(FAR const char *buf, FAR const char *fmt, ...) int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) { FAR const char *bufstart; - FAR char *tv; + FAR char *tv; FAR const char *tc; - bool lflag; - bool noassign; - int count; - int width; - int fwidth; - int base = 10; - char tmp[MAXLN]; + bool lflag; + bool noassign; + int count; + int width; + int fwidth; + int base = 10; + char tmp[MAXLN]; linfo("vsscanf: buf=\"%s\" fmt=\"%s\"\n", buf, fmt); /* Remember the start of the input buffer. We will need this for %n - * calculations. - */ + * calculations. */ bufstart = buf; /* Parse the format, extracting values from the input buffer as needed */ - count = 0; - width = 0; + count = 0; + width = 0; noassign = false; - lflag = false; + lflag = false; - /* Loop until all characters in the fmt string have been processed. We - * may have to continue loop after reaching the end the input data in - * order to handle trailing %n format specifiers. - */ + /* Loop until all characters in the fmt string have been processed. We may + * have to continue loop after reaching the end the input data in order to + * handle trailing %n format specifiers. */ while (*fmt) { @@ -245,27 +238,25 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } } - /* Process %s: String conversion */ + /* Process %s: String conversion */ if (*fmt == 's') { linfo("vsscanf: Performing string conversion\n"); - /* Get a pointer to the char * value. We need to do this even - * if we have reached the end of the input data in order to - * update the 'ap' variable. - */ + /* Get a pointer to the char * value. We need to do this even if + * we have reached the end of the input data in order to update + * the 'ap' variable. */ - tv = NULL; /* To avoid warnings about begin uninitialized */ + tv = NULL; /* To avoid warnings about begin uninitialized */ if (!noassign) { - tv = va_arg(ap, FAR char *); + tv = va_arg(ap, FAR char *); tv[0] = '\0'; } - /* But we only perform the data conversion is we still have - * bytes remaining in the input data stream. - */ + /* But we only perform the data conversion is we still have bytes + * remaining in the input data stream. */ if (*buf) { @@ -280,14 +271,13 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) fwidth = findwidth(buf, fmt); - /* Use the actual field's width if 1) no fieldwidth - * specified or 2) the actual field's width is smaller - * than fieldwidth specified - */ + /* Use the actual field's width if 1) no fieldwidth specified + * or 2) the actual field's width is smaller than fieldwidth + * specified */ if (!width || fwidth < width) { - width = fwidth; + width = fwidth; } width = MIN(sizeof(tmp) - 1, width); @@ -307,27 +297,25 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } } - /* Process %c: Character conversion */ + /* Process %c: Character conversion */ else if (*fmt == 'c') { linfo("vsscanf: Performing character conversion\n"); - /* Get a pointer to the char * value. We need to do this even - * if we have reached the end of the input data in order to - * update the 'ap' variable. - */ + /* Get a pointer to the char * value. We need to do this even if + * we have reached the end of the input data in order to update + * the 'ap' variable. */ - tv = NULL; /* To avoid warnings about beign uninitialized */ + tv = NULL; /* To avoid warnings about beign uninitialized */ if (!noassign) { - tv = va_arg(ap, FAR char *); + tv = va_arg(ap, FAR char *); tv[0] = '\0'; } - /* But we only perform the data conversion is we still have - * bytes remaining in the input data stream. - */ + /* But we only perform the data conversion is we still have bytes + * remaining in the input data stream. */ if (*buf) { @@ -350,33 +338,30 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } /* Update the buffer pointer past the character(s) in the - * input - */ + * input */ buf += width; } } - /* Process %d, %o, %b, %x, %u: Various integer conversions */ + /* Process %d, %o, %b, %x, %u: Various integer conversions */ else if (strchr("dobxu", *fmt)) { FAR long *plong = NULL; - FAR int *pint = NULL; + FAR int *pint = NULL; bool sign; linfo("vsscanf: Performing integer conversion\n"); /* Get a pointer to the integer value. We need to do this even * if we have reached the end of the input data in order to - * update the 'ap' variable. - */ + * update the 'ap' variable. */ if (!noassign) { /* We have to check whether we need to return a long or an - * int. - */ + * int. */ if (lflag) { @@ -390,15 +375,14 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } } - /* But we only perform the data conversion if we still have - * bytes remaining in the input data stream. - */ + /* But we only perform the data conversion if we still have bytes + * remaining in the input data stream. */ if (*buf) { FAR char *endptr; - int errsave; - long tmplong; + int errsave; + long tmplong; /* Skip over any white space before the integer string */ @@ -407,9 +391,8 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) buf++; } - /* The base of the integer conversion depends on the - * specific conversion specification. - */ + /* The base of the integer conversion depends on the specific + * conversion specification. */ sign = false; switch (*fmt) @@ -445,9 +428,7 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) width = MIN(sizeof(tmp) - 1, tmpwidth); } - /* Copy the numeric string into a temporary working - * buffer. - */ + /* Copy the numeric string into a temporary working buffer. */ strncpy(tmp, buf, width); tmp[width] = '\0'; @@ -482,9 +463,8 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) if (!noassign) { - /* We have to check whether we need to return a long - * or an int. - */ + /* We have to check whether we need to return a long or + * an int. */ if (lflag) { @@ -494,8 +474,7 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } else { - linfo("vsscanf: Return %ld to 0x%p\n", - tmplong, pint); + linfo("vsscanf: Return %ld to 0x%p\n", tmplong, pint); *pint = (int)tmplong; } @@ -504,48 +483,44 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } } - /* Process %a, %A, %f, %F, %e, %E, %g, and %G: Floating point - * conversions - */ + /* Process %a, %A, %f, %F, %e, %E, %g, and %G: Floating point + * conversions */ else if (strchr("aAfFeEgG", *fmt) != NULL) { #ifdef CONFIG_HAVE_DOUBLE FAR double_t *pd = NULL; #endif - FAR float *pf = NULL; + FAR float *pf = NULL; linfo("vsscanf: Performing floating point conversion\n"); - /* Get a pointer to the double value. We need to do this even - * if we have reached the end of the input data in order to - * update the 'ap' variable. - */ + /* Get a pointer to the double value. We need to do this even if + * we have reached the end of the input data in order to update + * the 'ap' variable. */ if (!noassign) { /* We have to check whether we need to return a float or a - * double. - */ + * double. */ #ifdef CONFIG_HAVE_DOUBLE if (lflag) { - pd = va_arg(ap, FAR double_t *); + pd = va_arg(ap, FAR double_t *); *pd = 0.0; } else #endif { - pf = va_arg(ap, FAR float *); + pf = va_arg(ap, FAR float *); *pf = 0.0; } } #ifdef CONFIG_LIBC_FLOATINGPOINT - /* But we only perform the data conversion is we still have - * bytes remaining in the input data stream. - */ + /* But we only perform the data conversion is we still have bytes + * remaining in the input data stream. */ if (*buf) { @@ -580,14 +555,14 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) /* strtod always returns a double */ FAR char *endptr; - int errsave; - double_t dvalue; + int errsave; + double_t dvalue; /* Preserve the errno value */ errsave = get_errno(); set_errno(0); - dvalue = strtod(tmp, &endptr); + dvalue = strtod(tmp, &endptr); /* Check if the number was successfully converted */ @@ -598,18 +573,17 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) set_errno(errsave); - /* We have to check whether we need to return a float - * or a double. - */ + /* We have to check whether we need to return a float or + * a double. */ -#ifdef CONFIG_HAVE_DOUBLE +# ifdef CONFIG_HAVE_DOUBLE if (lflag) { linfo("vsscanf: Return %f to %p\n", dvalue, pd); *pd = dvalue; } else -#endif +# endif { linfo("vsscanf: Return %f to %p\n", dvalue, pf); *pf = (float)dvalue; @@ -621,7 +595,7 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) #endif } - /* Process %n: Character count */ + /* Process %n: Character count */ else if (*fmt == 'n') { @@ -629,7 +603,7 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) if (!noassign) { - size_t nchars = (size_t)(buf - bufstart); + size_t nchars = (size_t) (buf - bufstart); /* Note %n does not count as a conversion */ @@ -646,14 +620,14 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } } - width = 0; + width = 0; noassign = false; - lflag = false; + lflag = false; fmt++; } - /* It is not a conversion specifier */ + /* It is not a conversion specifier */ else if (*buf) { @@ -685,8 +659,7 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } /* sscanf is required to return EOF if the input ends before the first - * matching failure or conversion. - */ + * matching failure or conversion. */ return count ? count : EOF; } -- GitLab From d538b6b3183d135f2d9d88dcfd77f71ba804c20a Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Sat, 15 Oct 2016 06:00:00 -1000 Subject: [PATCH 078/734] Removed debug pragma --- libc/stdio/lib_sscanf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libc/stdio/lib_sscanf.c b/libc/stdio/lib_sscanf.c index 3e8cd6c9ec..7c73e476ea 100644 --- a/libc/stdio/lib_sscanf.c +++ b/libc/stdio/lib_sscanf.c @@ -159,7 +159,7 @@ int sscanf(FAR const char *buf, FAR const char *fmt, ...) * ANSI standard vsscanf implementation. * ****************************************************************************/ -#pragma GCC optimize ("O0") + int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) { FAR const char *bufstart; -- GitLab From 0be3d12ba007fdcf6d5c330801ff83bb83824f8c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 15 Oct 2016 10:11:35 -0600 Subject: [PATCH 079/734] ESP32: Add option for interrupt support --- arch/xtensa/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 1bd5c0f54d..6befe7eff2 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -12,6 +12,7 @@ choice config ARCH_CHIP_ESP32 bool "Expressif ESP32" select ARCH_FAMILY_LX6 + select XTENSA_HAVE_INTERRUPTS ---help--- The ESP32 is a dual-core system from Expressif with two Harvard architecture Xtensa LX6 CPUs. All embedded memory, external memory @@ -33,6 +34,10 @@ config XTENSA_HAVE_LOOPS bool "Zero overhead loops" default n +config XTENSA_HAVE_INTERRUPTS + bool + default n + config XTENSA_USE_SWPRI bool "Use SWPRI" default n -- GitLab From 887895bf165ec8d3199426eebb0ddf1d05cdc1cd Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 15 Oct 2016 10:23:42 -0600 Subject: [PATCH 080/734] Revert last merge. That merge addes too many coding style violations. --- libc/stdio/lib_sscanf.c | 73 +++++++++++++++++++++++++++-------------- 1 file changed, 48 insertions(+), 25 deletions(-) diff --git a/libc/stdio/lib_sscanf.c b/libc/stdio/lib_sscanf.c index 7c73e476ea..8ba7f9bfe4 100644 --- a/libc/stdio/lib_sscanf.c +++ b/libc/stdio/lib_sscanf.c @@ -93,7 +93,8 @@ static int findwidth(FAR const char *buf, FAR const char *fmt) FAR const char *next = fmt + 1; /* No... is there a space after the format? Or does the format string end - * here? */ + * here? + */ if (isspace(*next) || *next == 0) { @@ -103,12 +104,14 @@ static int findwidth(FAR const char *buf, FAR const char *fmt) } /* No.. Another possibility is the format character is followed by some - * recognizable delimiting value. */ + * recognizable delimiting value. + */ if (*next != '%') { /* If so we will say that the string ends there if we can find that - * delimiter in the input string. */ + * delimiter in the input string. + */ FAR const char *ptr = strchr(buf, *next); if (ptr) @@ -124,7 +127,8 @@ static int findwidth(FAR const char *buf, FAR const char *fmt) * format may be concatenated with the first. This is a bug. We have no * generic way of determining the width of the data if there is no * fieldwidth, no space separating the input, and no usable delimiter - * character. */ + * character. + */ return strcspn(buf, spaces); } @@ -176,7 +180,8 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) linfo("vsscanf: buf=\"%s\" fmt=\"%s\"\n", buf, fmt); /* Remember the start of the input buffer. We will need this for %n - * calculations. */ + * calculations. + */ bufstart = buf; @@ -189,7 +194,8 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) /* Loop until all characters in the fmt string have been processed. We may * have to continue loop after reaching the end the input data in order to - * handle trailing %n format specifiers. */ + * handle trailing %n format specifiers. + */ while (*fmt) { @@ -246,7 +252,8 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) /* Get a pointer to the char * value. We need to do this even if * we have reached the end of the input data in order to update - * the 'ap' variable. */ + * the 'ap' variable. + */ tv = NULL; /* To avoid warnings about begin uninitialized */ if (!noassign) @@ -256,7 +263,8 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } /* But we only perform the data conversion is we still have bytes - * remaining in the input data stream. */ + * remaining in the input data stream. + */ if (*buf) { @@ -273,7 +281,8 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) /* Use the actual field's width if 1) no fieldwidth specified * or 2) the actual field's width is smaller than fieldwidth - * specified */ + * specified + */ if (!width || fwidth < width) { @@ -305,7 +314,8 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) /* Get a pointer to the char * value. We need to do this even if * we have reached the end of the input data in order to update - * the 'ap' variable. */ + * the 'ap' variable. + */ tv = NULL; /* To avoid warnings about beign uninitialized */ if (!noassign) @@ -315,7 +325,8 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } /* But we only perform the data conversion is we still have bytes - * remaining in the input data stream. */ + * remaining in the input data stream. + */ if (*buf) { @@ -338,7 +349,8 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } /* Update the buffer pointer past the character(s) in the - * input */ + * input. + */ buf += width; } @@ -356,12 +368,14 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) /* Get a pointer to the integer value. We need to do this even * if we have reached the end of the input data in order to - * update the 'ap' variable. */ + * update the 'ap' variable. + */ if (!noassign) { /* We have to check whether we need to return a long or an - * int. */ + * int. + */ if (lflag) { @@ -376,7 +390,8 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } /* But we only perform the data conversion if we still have bytes - * remaining in the input data stream. */ + * remaining in the input data stream. + */ if (*buf) { @@ -392,7 +407,8 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } /* The base of the integer conversion depends on the specific - * conversion specification. */ + * conversion specification. + */ sign = false; switch (*fmt) @@ -464,7 +480,8 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) { /* We have to check whether we need to return a long or - * an int. */ + * an int. + */ if (lflag) { @@ -484,7 +501,8 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } /* Process %a, %A, %f, %F, %e, %E, %g, and %G: Floating point - * conversions */ + * conversions. + */ else if (strchr("aAfFeEgG", *fmt) != NULL) { @@ -497,12 +515,14 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) /* Get a pointer to the double value. We need to do this even if * we have reached the end of the input data in order to update - * the 'ap' variable. */ + * the 'ap' variable. + */ if (!noassign) { /* We have to check whether we need to return a float or a - * double. */ + * double. + */ #ifdef CONFIG_HAVE_DOUBLE if (lflag) @@ -520,7 +540,8 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) #ifdef CONFIG_LIBC_FLOATINGPOINT /* But we only perform the data conversion is we still have bytes - * remaining in the input data stream. */ + * remaining in the input data stream. + */ if (*buf) { @@ -574,16 +595,17 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) set_errno(errsave); /* We have to check whether we need to return a float or - * a double. */ + * a double. + */ -# ifdef CONFIG_HAVE_DOUBLE +#ifdef CONFIG_HAVE_DOUBLE if (lflag) { linfo("vsscanf: Return %f to %p\n", dvalue, pd); *pd = dvalue; } else -# endif +#endif { linfo("vsscanf: Return %f to %p\n", dvalue, pf); *pf = (float)dvalue; @@ -659,7 +681,8 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } /* sscanf is required to return EOF if the input ends before the first - * matching failure or conversion. */ + * matching failure or conversion. + */ return count ? count : EOF; } -- GitLab From 7ee82c0168c0b8464aa6e36781d06f48a3eccee2 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Sat, 15 Oct 2016 05:15:40 -1000 Subject: [PATCH 081/734] Fixes sscan %sn where strlen(data) < n --- libc/stdio/lib_sscanf.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/libc/stdio/lib_sscanf.c b/libc/stdio/lib_sscanf.c index ae8774cc57..50bcd8956e 100644 --- a/libc/stdio/lib_sscanf.c +++ b/libc/stdio/lib_sscanf.c @@ -174,6 +174,7 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) bool noassign; int count; int width; + int fwidth; int base = 10; char tmp[MAXLN]; @@ -275,16 +276,22 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) buf++; } - /* Was a fieldwidth specified? */ + /* Guess a field width using some heuristics */ - if (!width) - { - /* No... Guess a field width using some heuristics */ + fwidth = findwidth(buf, fmt); - int tmpwidth = findwidth(buf, fmt); - width = MIN(sizeof(tmp) - 1, tmpwidth); + /* Use the actual field's width if 1) no fieldwidth + * specified or 2) the actual field's width is smaller + * than fieldwidth specified + */ + + if (!width || fwidth < width) + { + width = fwidth; } + width = MIN(sizeof(tmp) - 1, width); + /* Copy the string (if we are making an assignment) */ if (!noassign) -- GitLab From 4034a23704cd204f6e6854317de447000beae75f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 15 Oct 2016 10:42:15 -0600 Subject: [PATCH 082/734] Finish backing out the last PR that corrupted the file coding standard --- libc/stdio/lib_sscanf.c | 169 ++++++++++++++++++++-------------------- 1 file changed, 83 insertions(+), 86 deletions(-) diff --git a/libc/stdio/lib_sscanf.c b/libc/stdio/lib_sscanf.c index 8ba7f9bfe4..ae8774cc57 100644 --- a/libc/stdio/lib_sscanf.c +++ b/libc/stdio/lib_sscanf.c @@ -103,8 +103,8 @@ static int findwidth(FAR const char *buf, FAR const char *fmt) return strcspn(buf, spaces); } - /* No.. Another possibility is the format character is followed by some - * recognizable delimiting value. + /* No.. Another possibility is the format character is followed by + * some recognizable delimiting value. */ if (*next != '%') @@ -120,14 +120,15 @@ static int findwidth(FAR const char *buf, FAR const char *fmt) } } - /* No... the format has no delimiter and is back-to-back with the next format - * (or is followed by a delimiter that does not exist in the input string). - * At this point we just bail and Use the input up until the first white - * space is encountered. NOTE: This means that values from the following - * format may be concatenated with the first. This is a bug. We have no - * generic way of determining the width of the data if there is no - * fieldwidth, no space separating the input, and no usable delimiter - * character. + /* No... the format has no delimiter and is back-to-back with the next + * format (or is followed by a delimiter that does not exist in the + * input string). At this point we just bail and Use the input up until + * the first white space is encountered. + * + * NOTE: This means that values from the following format may be + * concatenated with the first. This is a bug. We have no generic way of + * determining the width of the data if there is no fieldwidth, no space + * separating the input, and no usable delimiter character. */ return strcspn(buf, spaces); @@ -148,7 +149,7 @@ static int findwidth(FAR const char *buf, FAR const char *fmt) int sscanf(FAR const char *buf, FAR const char *fmt, ...) { va_list ap; - int count; + int count; va_start(ap, fmt); count = vsscanf((FAR const char *)buf, fmt, ap); @@ -167,15 +168,14 @@ int sscanf(FAR const char *buf, FAR const char *fmt, ...) int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) { FAR const char *bufstart; - FAR char *tv; + FAR char *tv; FAR const char *tc; - bool lflag; - bool noassign; - int count; - int width; - int fwidth; - int base = 10; - char tmp[MAXLN]; + bool lflag; + bool noassign; + int count; + int width; + int base = 10; + char tmp[MAXLN]; linfo("vsscanf: buf=\"%s\" fmt=\"%s\"\n", buf, fmt); @@ -187,14 +187,14 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) /* Parse the format, extracting values from the input buffer as needed */ - count = 0; - width = 0; + count = 0; + width = 0; noassign = false; - lflag = false; + lflag = false; - /* Loop until all characters in the fmt string have been processed. We may - * have to continue loop after reaching the end the input data in order to - * handle trailing %n format specifiers. + /* Loop until all characters in the fmt string have been processed. We + * may have to continue loop after reaching the end the input data in + * order to handle trailing %n format specifiers. */ while (*fmt) @@ -244,26 +244,26 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } } - /* Process %s: String conversion */ + /* Process %s: String conversion */ if (*fmt == 's') { linfo("vsscanf: Performing string conversion\n"); - /* Get a pointer to the char * value. We need to do this even if - * we have reached the end of the input data in order to update - * the 'ap' variable. + /* Get a pointer to the char * value. We need to do this even + * if we have reached the end of the input data in order to + * update the 'ap' variable. */ - tv = NULL; /* To avoid warnings about begin uninitialized */ + tv = NULL; /* To avoid warnings about begin uninitialized */ if (!noassign) { - tv = va_arg(ap, FAR char *); + tv = va_arg(ap, FAR char *); tv[0] = '\0'; } - /* But we only perform the data conversion is we still have bytes - * remaining in the input data stream. + /* But we only perform the data conversion is we still have + * bytes remaining in the input data stream. */ if (*buf) @@ -275,21 +275,15 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) buf++; } - /* Guess a field width using some heuristics */ - - fwidth = findwidth(buf, fmt); - - /* Use the actual field's width if 1) no fieldwidth specified - * or 2) the actual field's width is smaller than fieldwidth - * specified - */ + /* Was a fieldwidth specified? */ - if (!width || fwidth < width) + if (!width) { - width = fwidth; - } + /* No... Guess a field width using some heuristics */ - width = MIN(sizeof(tmp) - 1, width); + int tmpwidth = findwidth(buf, fmt); + width = MIN(sizeof(tmp) - 1, tmpwidth); + } /* Copy the string (if we are making an assignment) */ @@ -306,26 +300,26 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } } - /* Process %c: Character conversion */ + /* Process %c: Character conversion */ else if (*fmt == 'c') { linfo("vsscanf: Performing character conversion\n"); - /* Get a pointer to the char * value. We need to do this even if - * we have reached the end of the input data in order to update - * the 'ap' variable. + /* Get a pointer to the char * value. We need to do this even + * if we have reached the end of the input data in order to + * update the 'ap' variable. */ - tv = NULL; /* To avoid warnings about beign uninitialized */ + tv = NULL; /* To avoid warnings about beign uninitialized */ if (!noassign) { - tv = va_arg(ap, FAR char *); + tv = va_arg(ap, FAR char *); tv[0] = '\0'; } - /* But we only perform the data conversion is we still have bytes - * remaining in the input data stream. + /* But we only perform the data conversion is we still have + * bytes remaining in the input data stream. */ if (*buf) @@ -349,19 +343,19 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } /* Update the buffer pointer past the character(s) in the - * input. + * input */ buf += width; } } - /* Process %d, %o, %b, %x, %u: Various integer conversions */ + /* Process %d, %o, %b, %x, %u: Various integer conversions */ else if (strchr("dobxu", *fmt)) { FAR long *plong = NULL; - FAR int *pint = NULL; + FAR int *pint = NULL; bool sign; linfo("vsscanf: Performing integer conversion\n"); @@ -389,15 +383,15 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } } - /* But we only perform the data conversion if we still have bytes - * remaining in the input data stream. + /* But we only perform the data conversion if we still have + * bytes remaining in the input data stream. */ if (*buf) { FAR char *endptr; - int errsave; - long tmplong; + int errsave; + long tmplong; /* Skip over any white space before the integer string */ @@ -406,8 +400,8 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) buf++; } - /* The base of the integer conversion depends on the specific - * conversion specification. + /* The base of the integer conversion depends on the + * specific conversion specification. */ sign = false; @@ -444,7 +438,9 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) width = MIN(sizeof(tmp) - 1, tmpwidth); } - /* Copy the numeric string into a temporary working buffer. */ + /* Copy the numeric string into a temporary working + * buffer. + */ strncpy(tmp, buf, width); tmp[width] = '\0'; @@ -479,8 +475,8 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) if (!noassign) { - /* We have to check whether we need to return a long or - * an int. + /* We have to check whether we need to return a long + * or an int. */ if (lflag) @@ -491,7 +487,8 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } else { - linfo("vsscanf: Return %ld to 0x%p\n", tmplong, pint); + linfo("vsscanf: Return %ld to 0x%p\n", + tmplong, pint); *pint = (int)tmplong; } @@ -500,8 +497,8 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } } - /* Process %a, %A, %f, %F, %e, %E, %g, and %G: Floating point - * conversions. + /* Process %a, %A, %f, %F, %e, %E, %g, and %G: Floating point + * conversions */ else if (strchr("aAfFeEgG", *fmt) != NULL) @@ -509,13 +506,13 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) #ifdef CONFIG_HAVE_DOUBLE FAR double_t *pd = NULL; #endif - FAR float *pf = NULL; + FAR float *pf = NULL; linfo("vsscanf: Performing floating point conversion\n"); - /* Get a pointer to the double value. We need to do this even if - * we have reached the end of the input data in order to update - * the 'ap' variable. + /* Get a pointer to the double value. We need to do this even + * if we have reached the end of the input data in order to + * update the 'ap' variable. */ if (!noassign) @@ -527,20 +524,20 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) #ifdef CONFIG_HAVE_DOUBLE if (lflag) { - pd = va_arg(ap, FAR double_t *); + pd = va_arg(ap, FAR double_t *); *pd = 0.0; } else #endif { - pf = va_arg(ap, FAR float *); + pf = va_arg(ap, FAR float *); *pf = 0.0; } } #ifdef CONFIG_LIBC_FLOATINGPOINT - /* But we only perform the data conversion is we still have bytes - * remaining in the input data stream. + /* But we only perform the data conversion is we still have + * bytes remaining in the input data stream. */ if (*buf) @@ -576,14 +573,14 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) /* strtod always returns a double */ FAR char *endptr; - int errsave; - double_t dvalue; + int errsave; + double_t dvalue; /* Preserve the errno value */ errsave = get_errno(); set_errno(0); - dvalue = strtod(tmp, &endptr); + dvalue = strtod(tmp, &endptr); /* Check if the number was successfully converted */ @@ -594,8 +591,8 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) set_errno(errsave); - /* We have to check whether we need to return a float or - * a double. + /* We have to check whether we need to return a float + * or a double. */ #ifdef CONFIG_HAVE_DOUBLE @@ -617,7 +614,7 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) #endif } - /* Process %n: Character count */ + /* Process %n: Character count */ else if (*fmt == 'n') { @@ -625,7 +622,7 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) if (!noassign) { - size_t nchars = (size_t) (buf - bufstart); + size_t nchars = (size_t)(buf - bufstart); /* Note %n does not count as a conversion */ @@ -642,14 +639,14 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } } - width = 0; + width = 0; noassign = false; - lflag = false; + lflag = false; fmt++; } - /* It is not a conversion specifier */ + /* It is not a conversion specifier */ else if (*buf) { -- GitLab From 43d08db1a0849a3e946d7b24b07a5d9963db08ed Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 15 Oct 2016 11:29:50 -0600 Subject: [PATCH 083/734] XTENSA: Add some interrupt controls --- arch/xtensa/src/common/xtensa_irq.S | 148 ++++++++++++++++++++++ arch/xtensa/src/common/xtensa_macros.h | 108 ++++++++++++++++ arch/xtensa/src/common/xtensa_specregs.h | 154 +++++++++++++++++++++++ 3 files changed, 410 insertions(+) create mode 100644 arch/xtensa/src/common/xtensa_irq.S create mode 100644 arch/xtensa/src/common/xtensa_macros.h create mode 100644 arch/xtensa/src/common/xtensa_specregs.h diff --git a/arch/xtensa/src/common/xtensa_irq.S b/arch/xtensa/src/common/xtensa_irq.S new file mode 100644 index 0000000000..c2963b9aa5 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_irq.S @@ -0,0 +1,148 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_irq.S + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * + * Copyright (c) 2006-2015 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "xtensa_specregs.h" +#include "xtensa_macros.h" + +#ifdef CONFIG_XTENSA_HAVE_INTERRUPTS + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* INTENABLE virtualization information. */ + + .data + .global _xtensa_intdata + .align 8 +_xtensa_intdata: + + .global _xtensa_intenable + .type _xtensa_intenable, @object +_xtensa_intenable: + .word 0 /* Virtual INTENABLE */ + .size _xtensa_intenable,4 + + .global _xtensa_vprimask + .type _xtensa_vprimask, @object +_xtensa_vprimask: + .word 0xffffffff /* Virtual priority mask */ + .size _xtensa_vprimask, 4 + +#endif /* XCHAL_HAVE_INTERRUPTS */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * C Prototype: + * irqstate_t xtensa_enable_interrupts(irqstate_t mask) + * + * Description: + * Enables a set of interrupts. Does not simply set INTENABLE directly, + * but computes it as a function of the current virtual priority. + * Can be called from interrupt handlers. + * + ****************************************************************************/ + + .text + .align 4 + .global xtensa_enable_interrupts + .type xtensa_enable_interrupts, @function + +xtensa_enable_interrupts: + + ENTRY0 +#if XCHAL_HAVE_INTERRUPTS + movi a3, 0 + movi a4, _xtensa_intdata + xsr a3, INTENABLE /* Disables all interrupts */ + rsync + l32i a3, a4, 0 /* a3 = _xtensa_intenable */ + l32i a6, a4, 4 /* a6 = _xtensa_vprimask */ + or a5, a3, a2 /* a5 = _xtensa_intenable | mask */ + s32i a5, a4, 0 /* _xtensa_intenable |= mask */ + and a5, a5, a6 /* a5 = _xtensa_intenable & _xtensa_vprimask */ + wsr a5, INTENABLE /* Reenable interrupts */ + mov a2, a3 /* Previous mask */ +#else + movi a2, 0 /* Return zero */ +#endif + RET0 + + .size xtensa_enable_interrupts, . - xtensa_enable_interrupts + +/**************************************************************************** + * C Prototype: + * irqstate_t xtensa_disable_interrupts(irqstate_t mask) + * + * Description: + * Disables a set of interrupts. Does not simply set INTENABLE directly, + * but computes it as a function of the current virtual priority. + * Can be called from interrupt handlers. + * + ****************************************************************************/ + + .text + .align 4 + .global xtensa_disable_interrupts + .type xtensa_disable_interrupts,@function + +xtensa_disable_interrupts: + + ENTRY0 +#if XCHAL_HAVE_INTERRUPTS + movi a3, 0 + movi a4, _xtensa_intdata + xsr a3, INTENABLE /* Disables all interrupts */ + rsync + l32i a3, a4, 0 /* a3 = _xtensa_intenable */ + l32i a6, a4, 4 /* a6 = _xtensa_vprimask */ + or a5, a3, a2 /* a5 = _xtensa_intenable | mask */ + xor a5, a5, a2 /* a5 = _xtensa_intenable & ~mask */ + s32i a5, a4, 0 /* _xtensa_intenable &= ~mask */ + and a5, a5, a6 /* a5 = _xtensa_intenable & _xtensa_vprimask */ + wsr a5, INTENABLE /* Reenable interrupts */ + mov a2, a3 /* Previous mask */ +#else + movi a2, 0 /* return zero */ +#endif + RET0 + + .size xtensa_disable_interrupts, . - xtensa_disable_interrupts diff --git a/arch/xtensa/src/common/xtensa_macros.h b/arch/xtensa/src/common/xtensa_macros.h new file mode 100644 index 0000000000..cf83048109 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_macros.h @@ -0,0 +1,108 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_macros.h + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * + * Copyright (c) 2006-2015 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + ****************************************************************************/ + +#ifdef __ARCH_XTENSA_SRC_COMMON_XTENSA_MACROS_H +#define __ARCH_XTENSA_SRC_COMMON_XTENSA_MACROS_H 1 + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Assembly Language Macros + ****************************************************************************/ + +#ifdef __ASSEMBLY__ + +/* Macro to get the current core ID. Only uses the reg given as an argument. + * Reading PRID on the ESP108 architecture gives us 0xcdcd on the PRO + * processor and 0xabab on the APP CPU. We distinguish between the two by + * simply checking bit 1: it's 1 on the APP and 0 on the PRO processor. + */ + + .macro getcoreid reg + rsr.prid \reg + bbci \reg,1,1f + movi \reg,1 + j 2f +1: + movi \reg,0 +2: + .endm + +/* Macros to handle ABI specifics of function entry and return. + * + * Convenient where the frame size requirements are the same for both ABIs. + * ENTRY(sz), RET(sz) are for framed functions (have locals or make calls). + * ENTRY0, RET0 are for frameless functions (no locals, no calls). + * + * where size = size of stack frame in bytes (must be >0 and aligned to 16). + * For framed functions the frame is created and the return address saved at + * base of frame (Call0 ABI) or as determined by hardware (Windowed ABI). + * For frameless functions, there is no frame and return address remains in a0. + * Note: Because CPP macros expand to a single line, macros requiring multi-line + * expansions are implemented as assembler macros. + */ + +#ifdef CONFIG_XTENSA_CALL0_ABI + /* Call0 */ + + .macro entry1 size=0x10 + addi sp, sp, -\size + s32i a0, sp, 0 + .endm + + .macro ret1 size=0x10 + l32i a0, sp, 0 + addi sp, sp, \size + ret + .endm + +# define ENTRY(sz) entry1 sz +# define ENTRY0 +# define RET(sz) ret1 sz +# define RET0 ret + +#else + /* Windowed */ + +# define ENTRY(sz) entry sp, sz +# define ENTRY0 entry sp, 0x10 +# define RET(sz) retw +# define RET0 retw + +#endif /* CONFIG_XTENSA_CALL0_ABI */ + +#endif /* __ASSEMBLY */ +#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_MACROS_H */ diff --git a/arch/xtensa/src/common/xtensa_specregs.h b/arch/xtensa/src/common/xtensa_specregs.h new file mode 100644 index 0000000000..0b8b880d80 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_specregs.h @@ -0,0 +1,154 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_macros.h + * Xtensa Special Register symbolic names + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Tensilica Inc. + * + * Copyright (c) 2005-2011 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_SPECREGS_H +#define __ARCH_XTENSA_SRC_COMMON_XTENSA_SPECREGS_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Special registers: */ + +#define LBEG 0 +#define LEND 1 +#define LCOUNT 2 +#define SAR 3 +#define BR 4 +#define LITBASE 5 +#define SCOMPARE1 12 +#define ACCLO 16 +#define ACCHI 17 +#define MR_0 32 +#define MR_1 33 +#define MR_2 34 +#define MR_3 35 +#define PREFCTL 40 +#define WINDOWBASE 72 +#define WINDOWSTART 73 +#define PTEVADDR 83 +#define RASID 90 +#define ITLBCFG 91 +#define DTLBCFG 92 +#define IBREAKENABLE 96 +#define MEMCTL 97 +#define CACHEATTR 98 +#define ATOMCTL 99 +#define DDR 104 +#define MECR 110 +#define IBREAKA_0 128 +#define IBREAKA_1 129 +#define DBREAKA_0 144 +#define DBREAKA_1 145 +#define DBREAKC_0 160 +#define DBREAKC_1 161 +#define CONFIGID0 176 +#define EPC_1 177 +#define EPC_2 178 +#define EPC_3 179 +#define EPC_4 180 +#define EPC_5 181 +#define EPC_6 182 +#define EPC_7 183 +#define DEPC 192 +#define EPS_2 194 +#define EPS_3 195 +#define EPS_4 196 +#define EPS_5 197 +#define EPS_6 198 +#define EPS_7 199 +#define CONFIGID1 208 +#define EXCSAVE_1 209 +#define EXCSAVE_2 210 +#define EXCSAVE_3 211 +#define EXCSAVE_4 212 +#define EXCSAVE_5 213 +#define EXCSAVE_6 214 +#define EXCSAVE_7 215 +#define CPENABLE 224 +#define INTERRUPT 226 +#define INTREAD INTERRUPT /* Alternate name for backward compatibility */ +#define INTSET INTERRUPT /* Alternate name for backward compatibility */ +#define INTCLEAR 227 +#define INTENABLE 228 +#define PS 230 +#define VECBASE 231 +#define EXCCAUSE 232 +#define DEBUGCAUSE 233 +#define CCOUNT 234 +#define PRID 235 +#define ICOUNT 236 +#define ICOUNTLEVEL 237 +#define EXCVADDR 238 +#define CCOMPARE_0 240 +#define CCOMPARE_1 241 +#define CCOMPARE_2 242 +#define MISC_REG_0 244 +#define MISC_REG_1 245 +#define MISC_REG_2 246 +#define MISC_REG_3 247 + +/* Special cases (bases of special register series): */ + +#define MR 32 +#define IBREAKA 128 +#define DBREAKA 144 +#define DBREAKC 160 +#define EPC 176 +#define EPS 192 +#define EXCSAVE 208 +#define CCOMPARE 240 +#define MISC_REG 244 + +/* Tensilica-defined user registers: */ + +#if 0 +/*#define ... 21..24 */ /* (545CK) */ +/*#define ... 140..143 */ /* (545CK) */ +#define EXPSTATE 230 /* Diamond */ +#define THREADPTR 231 /* threadptr option */ +#define FCR 232 /* FPU */ +#define FSR 233 /* FPU */ +#define AE_OVF_SAR 240 /* HiFi2 */ +#define AE_BITHEAD 241 /* HiFi2 */ +#define AE_TS_FTS_BU_BP 242 /* HiFi2 */ +#define AE_SD_NO 243 /* HiFi2 */ +#define VSAR 240 /* VectraLX */ +#define ROUND_LO 242 /* VectraLX */ +#define ROUND_HI 243 /* VectraLX */ +#define CBEGIN 246 /* VectraLX */ +#define CEND 247 /* VectraLX */ +#endif + +#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_SPECREGS_H */ -- GitLab From 0a0278a3ca92ba9730409317b24a75b38a2195d9 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 15 Oct 2016 11:36:48 -0600 Subject: [PATCH 084/734] XTENSA: Add and architecture Makefile. Initial verion is just the MIPS Makefile. --- arch/xtensa/src/Makefile | 187 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 187 insertions(+) create mode 100644 arch/xtensa/src/Makefile diff --git a/arch/xtensa/src/Makefile b/arch/xtensa/src/Makefile new file mode 100644 index 0000000000..0e22a4e010 --- /dev/null +++ b/arch/xtensa/src/Makefile @@ -0,0 +1,187 @@ +############################################################################ +# arch/xtensa/src/Makefile +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs +-include chip/Make.defs + +ifeq ($(CONFIG_ARCH_FAMILY_LX6),y) +ARCH_SUBDIR = lx6 +endif + +CPPFLAGS += $(EXTRADEFINES) +CFLAGS += $(EXTRADEFINES) +CXXFLAGS += $(EXTRADEFINES) + +ifeq ($(CONFIG_WINDOWS_NATIVE),y) + ARCH_SRCDIR = $(TOPDIR)\arch\$(CONFIG_ARCH)\src + NUTTX = $(TOPDIR)\nuttx$(EXEEXT) + CFLAGS += -I$(ARCH_SRCDIR)\chip + CFLAGS += -I$(ARCH_SRCDIR)\common + CFLAGS += -I$(ARCH_SRCDIR)\$(ARCH_SUBDIR) + CFLAGS += -I$(TOPDIR)\sched +else + ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src +ifeq ($(WINTOOL),y) + NUTTX = "${shell cygpath -w $(TOPDIR)/nuttx$(EXEEXT)}" + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/$(ARCH_SUBDIR)}" + CFLAGS += -I "${shell cygpath -w $(TOPDIR)/sched}" +else + NUTTX = $(TOPDIR)/nuttx$(EXEEXT) + CFLAGS += -I$(ARCH_SRCDIR)/chip + CFLAGS += -I$(ARCH_SRCDIR)/common + CFLAGS += -I$(ARCH_SRCDIR)/$(ARCH_SUBDIR) + CFLAGS += -I$(TOPDIR)/sched +endif +endif + +HEAD_OBJ = $(HEAD_ASRC:.S=$(OBJEXT)) +STARTUP_OBJS ?= $(HEAD_OBJ) + +ASRCS = $(CHIP_ASRCS) $(CMN_ASRCS) +AOBJS = $(ASRCS:.S=$(OBJEXT)) + +CSRCS = $(CHIP_CSRCS) $(CMN_CSRCS) +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +# Override in Make.defs if linker is not 'ld' + +LDSTARTGROUP ?= --start-group +LDENDGROUP ?= --end-group + +LDFLAGS += $(ARCHSCRIPT) +EXTRA_LIBS ?= +LINKLIBS ?= + +ifeq ($(CONFIG_WINDOWS_NATIVE),y) + BOARDMAKE = $(if $(wildcard .\board\Makefile),y,) + LIBPATHS += -L"$(TOPDIR)\lib" +ifeq ($(BOARDMAKE),y) + LIBPATHS += -L"$(TOPDIR)\arch\$(CONFIG_ARCH)\src\board" +endif + +else + BOARDMAKE = $(if $(wildcard ./board/Makefile),y,) + +ifeq ($(WINTOOL),y) + LIBPATHS += -L"${shell cygpath -w "$(TOPDIR)/lib"}" +ifeq ($(BOARDMAKE),y) + LIBPATHS += -L"${shell cygpath -w "$(TOPDIR)/arch/$(CONFIG_ARCH)/src/board"}" +endif + +else + LIBPATHS += -L"$(TOPDIR)/lib" +ifeq ($(BOARDMAKE),y) + LIBPATHS += -L"$(TOPDIR)/arch/$(CONFIG_ARCH)/src/board" +endif +endif +endif + +LDLIBS = $(patsubst %.a,%,$(patsubst lib%,-l%,$(LINKLIBS))) +ifeq ($(BOARDMAKE),y) + LDLIBS += -lboard +endif + +LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" + +VPATH = chip:common:$(ARCH_SUBDIR) + +all: $(HEAD_OBJ) libarch$(LIBEXT) + +.PHONY: board/libboard$(LIBEXT) + +$(AOBJS) $(HEAD_OBJ): %$(OBJEXT): %.S + $(call ASSEMBLE, $<, $@) + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +libarch$(LIBEXT): $(OBJS) + $(call ARCHIVE, $@, $(OBJS)) + +board/libboard$(LIBEXT): + $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" libboard$(LIBEXT) EXTRADEFINES=$(EXTRADEFINES) + +nuttx$(EXEEXT): $(HEAD_OBJ) board/libboard$(LIBEXT) + @echo "LD: nuttx" + $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) -o $(NUTTX)$(EXEEXT) $(HEAD_OBJ) $(EXTRA_OBJS) \ + $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) $(LDENDGROUP) +ifneq ($(CONFIG_WINDOWS_NATIVE),y) + $(Q) $(NM) $(NUTTX)$(EXEEXT) | \ + grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ + sort > $(TOPDIR)/System.map +endif + +# This is part of the top-level export target + +export_startup: board/libboard$(LIBEXT) $(STARTUP_OBJS) + $(Q) if [ -d "$(EXPORT_DIR)/startup" ]; then \ + cp -f $(STARTUP_OBJS) "$(EXPORT_DIR)/startup"; \ + else \ + echo "$(EXPORT_DIR)/startup does not exist"; \ + exit 1; \ + fi + +# Dependencies + +.depend: Makefile chip/Make.defs $(SRCS) +ifeq ($(BOARDMAKE),y) + $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" depend +endif + $(Q) $(MKDEP) --dep-path chip --dep-path common --dep-path $(ARCH_SUBDIR) \ + "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) touch $@ + +depend: .depend + +clean: +ifeq ($(BOARDMAKE),y) + $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" clean +endif + $(call DELFILE, libarch$(LIBEXT)) + $(call CLEAN) + +distclean: clean +ifeq ($(BOARDMAKE),y) + $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" distclean +endif + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + +-include Make.dep -- GitLab From 4621784617e8dcc41f76f6b47d6937a2f05de9b4 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 15 Oct 2016 11:45:15 -0600 Subject: [PATCH 085/734] Add xtensa.h (which is call up_internal.h in other architectures. --- arch/xtensa/include/irq.h | 4 +-- arch/xtensa/src/common/xtensa.h | 28 +++++++++---------- arch/xtensa/src/common/xtensa_allocateheap.c | 2 +- arch/xtensa/src/common/xtensa_createstack.c | 2 +- arch/xtensa/src/common/xtensa_etherstub.c | 2 +- arch/xtensa/src/common/xtensa_exit.c | 2 +- arch/xtensa/src/common/xtensa_idle.c | 2 +- arch/xtensa/src/common/xtensa_initialize.c | 2 +- .../src/common/xtensa_interruptcontext.c | 2 +- arch/xtensa/src/common/xtensa_lowputs.c | 2 +- arch/xtensa/src/common/xtensa_puts.c | 2 +- arch/xtensa/src/common/xtensa_releasestack.c | 2 +- arch/xtensa/src/common/xtensa_stackframe.c | 2 +- arch/xtensa/src/common/xtensa_usestack.c | 2 +- 14 files changed, 28 insertions(+), 28 deletions(-) diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index 3e8dfd4666..49bfc5b138 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -158,9 +158,9 @@ struct xcptcontext uint32_t saved_cpsr; #endif - /* Register save area */ + /* Pointer to the register save area on the stack*/ - uint32_t regs[XCPTCONTEXT_REGS]; + uint32_t *regs; #ifdef CONFIG_LIB_SYSCALL /* The following array holds the return address and the exc_return value diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index cef80d3ae9..01a3ed9e06 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -1,7 +1,7 @@ /**************************************************************************** - * arch/xtensa/common/xtensa_internal.h + * arch/xtensa/common/xtensa.h * - * Copyright (C) 2011, 2012, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ****************************************************************************/ -#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_INTERNAL_H -#define __ARCH_XTENSA_SRC_COMMON_XTENSA_INTERNAL_H +#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_H +#define __ARCH_XTENSA_SRC_COMMON_XTENSA_H /**************************************************************************** * Included Files @@ -104,12 +104,12 @@ # define CONFIG_ARCH_INTERRUPTSTACK 0 #endif -/* In the XTENSA model, the state is copied from the stack to the TCB, but - * only a referenced is passed to get the state from the TCB. +/* In the XTENSA model, only a pointer to register state on the stack is + * saved in the TCB. */ -#define up_savestate(regs) up_copystate(regs, (uint32_t*)g_current_regs) -#define up_restorestate(regs) (g_current_regs = regs) +#define up_savestate(regs) do { reg = g_current_regs; } while (0) +#define up_restorestate(regs) do { g_current_regs = regs; } while (0) /**************************************************************************** * Public Types @@ -183,7 +183,7 @@ extern uint32_t _bmxdupba_address; /* BMX register setting */ #ifndef __ASSEMBLY__ /* Common Functions *********************************************************/ -/* Common functions define in arch/xtensa/src/common. These may be replaced +/* Common functions define in arch/mips/src/common. These may be replaced * with chip-specific functions of the same name if needed. See also * functions prototyped in include/nuttx/arch.h. */ @@ -213,21 +213,21 @@ void up_dumpstate(void); # define up_dumpstate() #endif -/* Common XTENSA32 functions defined in arch/xtensa/src/XTENSA32 */ +/* Common XTENSA functions */ /* IRQs */ uint32_t *up_doirq(int irq, uint32_t *regs); -/* Software interrupt 0 handler */ +/* Software interrupt handler */ -int up_swint0(int irq, FAR void *context); +int up_swint(int irq, FAR void *context); /* Signals */ void up_sigdeliver(void); /* Chip-specific functions **************************************************/ -/* Chip specific functions defined in arch/xtensa/src/ */ +/* Chip specific functions defined in arch/mips/src/ */ /* IRQs */ void up_irqinitialize(void); @@ -282,4 +282,4 @@ void up_usbuninitialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_INTERNAL_H */ +#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_H */ diff --git a/arch/xtensa/src/common/xtensa_allocateheap.c b/arch/xtensa/src/common/xtensa_allocateheap.c index fc2178b5d1..b821eb4e34 100644 --- a/arch/xtensa/src/common/xtensa_allocateheap.c +++ b/arch/xtensa/src/common/xtensa_allocateheap.c @@ -47,7 +47,7 @@ #include #include "up_arch.h" -#include "up_internal.h" +#include "xtensa.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/xtensa/src/common/xtensa_createstack.c b/arch/xtensa/src/common/xtensa_createstack.c index 08d310e497..f895f47a50 100644 --- a/arch/xtensa/src/common/xtensa_createstack.c +++ b/arch/xtensa/src/common/xtensa_createstack.c @@ -50,7 +50,7 @@ #include #include "up_arch.h" -#include "up_internal.h" +#include "xtensa.h" /**************************************************************************** * Pre-processor Macros diff --git a/arch/xtensa/src/common/xtensa_etherstub.c b/arch/xtensa/src/common/xtensa_etherstub.c index e19b26a208..b41b7bf6d4 100644 --- a/arch/xtensa/src/common/xtensa_etherstub.c +++ b/arch/xtensa/src/common/xtensa_etherstub.c @@ -39,7 +39,7 @@ #include -#include "up_internal.h" +#include "xtensa.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/xtensa/src/common/xtensa_exit.c b/arch/xtensa/src/common/xtensa_exit.c index f300c9b89a..4f451539d2 100644 --- a/arch/xtensa/src/common/xtensa_exit.c +++ b/arch/xtensa/src/common/xtensa_exit.c @@ -52,7 +52,7 @@ #include "task/task.h" #include "sched/sched.h" #include "group/group.h" -#include "up_internal.h" +#include "xtensa.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/xtensa/src/common/xtensa_idle.c b/arch/xtensa/src/common/xtensa_idle.c index e48441d5b4..672a0fae1c 100644 --- a/arch/xtensa/src/common/xtensa_idle.c +++ b/arch/xtensa/src/common/xtensa_idle.c @@ -41,7 +41,7 @@ #include #include -#include "up_internal.h" +#include "xtensa.h" /**************************************************************************** * Public Functions diff --git a/arch/xtensa/src/common/xtensa_initialize.c b/arch/xtensa/src/common/xtensa_initialize.c index 1fedf99149..46de907db4 100644 --- a/arch/xtensa/src/common/xtensa_initialize.c +++ b/arch/xtensa/src/common/xtensa_initialize.c @@ -58,7 +58,7 @@ #include #include "up_arch.h" -#include "up_internal.h" +#include "xtensa.h" /**************************************************************************** * Private Functions diff --git a/arch/xtensa/src/common/xtensa_interruptcontext.c b/arch/xtensa/src/common/xtensa_interruptcontext.c index c6d83d05e0..8b6bf802ec 100644 --- a/arch/xtensa/src/common/xtensa_interruptcontext.c +++ b/arch/xtensa/src/common/xtensa_interruptcontext.c @@ -43,7 +43,7 @@ #include #include -#include "up_internal.h" +#include "xtensa.h" /**************************************************************************** * Private Types diff --git a/arch/xtensa/src/common/xtensa_lowputs.c b/arch/xtensa/src/common/xtensa_lowputs.c index 764f8393a6..f1acb1059d 100644 --- a/arch/xtensa/src/common/xtensa_lowputs.c +++ b/arch/xtensa/src/common/xtensa_lowputs.c @@ -39,7 +39,7 @@ #include -#include "up_internal.h" +#include "xtensa.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/xtensa/src/common/xtensa_puts.c b/arch/xtensa/src/common/xtensa_puts.c index 47675baa8d..3eaa3078a4 100644 --- a/arch/xtensa/src/common/xtensa_puts.c +++ b/arch/xtensa/src/common/xtensa_puts.c @@ -40,7 +40,7 @@ #include #include -#include "up_internal.h" +#include "xtensa.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/xtensa/src/common/xtensa_releasestack.c b/arch/xtensa/src/common/xtensa_releasestack.c index 76b3164bce..40b5bd7571 100644 --- a/arch/xtensa/src/common/xtensa_releasestack.c +++ b/arch/xtensa/src/common/xtensa_releasestack.c @@ -45,7 +45,7 @@ #include #include -#include "up_internal.h" +#include "xtensa.h" /**************************************************************************** * Private Types diff --git a/arch/xtensa/src/common/xtensa_stackframe.c b/arch/xtensa/src/common/xtensa_stackframe.c index f0a1da976d..6c1adc992b 100644 --- a/arch/xtensa/src/common/xtensa_stackframe.c +++ b/arch/xtensa/src/common/xtensa_stackframe.c @@ -46,7 +46,7 @@ #include -#include "up_internal.h" +#include "xtensa.h" /**************************************************************************** * Pre-processor Macros diff --git a/arch/xtensa/src/common/xtensa_usestack.c b/arch/xtensa/src/common/xtensa_usestack.c index 9b35e2d0a9..83daf2729c 100644 --- a/arch/xtensa/src/common/xtensa_usestack.c +++ b/arch/xtensa/src/common/xtensa_usestack.c @@ -47,7 +47,7 @@ #include #include -#include "up_internal.h" +#include "xtensa.h" /**************************************************************************** * Pre-processor Definitions -- GitLab From 8ffbf6d95efdf21fd70faa1cbac825b4ef442e59 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 15 Oct 2016 11:46:21 -0600 Subject: [PATCH 086/734] XTENSA: Hook xtensa_irq.S into build --- arch/xtensa/src/common/xtensa_irq.S | 10 +++++----- arch/xtensa/src/common/xtensa_macros.h | 2 +- arch/xtensa/src/esp32/Make.defs | 2 +- configs/esp32-core/nsh/defconfig | 7 ++++++- 4 files changed, 13 insertions(+), 8 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_irq.S b/arch/xtensa/src/common/xtensa_irq.S index c2963b9aa5..4ecd099d10 100644 --- a/arch/xtensa/src/common/xtensa_irq.S +++ b/arch/xtensa/src/common/xtensa_irq.S @@ -39,12 +39,12 @@ #include "xtensa_specregs.h" #include "xtensa_macros.h" -#ifdef CONFIG_XTENSA_HAVE_INTERRUPTS - /**************************************************************************** * Public Data ****************************************************************************/ +#ifdef CONFIG_XTENSA_HAVE_INTERRUPTS + /* INTENABLE virtualization information. */ .data @@ -64,7 +64,7 @@ _xtensa_vprimask: .word 0xffffffff /* Virtual priority mask */ .size _xtensa_vprimask, 4 -#endif /* XCHAL_HAVE_INTERRUPTS */ +#endif /* CONFIG_XTENSA_HAVE_INTERRUPTS */ /**************************************************************************** * Public Functions @@ -89,7 +89,7 @@ _xtensa_vprimask: xtensa_enable_interrupts: ENTRY0 -#if XCHAL_HAVE_INTERRUPTS +#ifdef CONFIG_XTENSA_HAVE_INTERRUPTS movi a3, 0 movi a4, _xtensa_intdata xsr a3, INTENABLE /* Disables all interrupts */ @@ -127,7 +127,7 @@ xtensa_enable_interrupts: xtensa_disable_interrupts: ENTRY0 -#if XCHAL_HAVE_INTERRUPTS +#ifdef CONFIG_XTENSA_HAVE_INTERRUPTS movi a3, 0 movi a4, _xtensa_intdata xsr a3, INTENABLE /* Disables all interrupts */ diff --git a/arch/xtensa/src/common/xtensa_macros.h b/arch/xtensa/src/common/xtensa_macros.h index cf83048109..d988386059 100644 --- a/arch/xtensa/src/common/xtensa_macros.h +++ b/arch/xtensa/src/common/xtensa_macros.h @@ -30,7 +30,7 @@ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ****************************************************************************/ -#ifdef __ARCH_XTENSA_SRC_COMMON_XTENSA_MACROS_H +#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_MACROS_H #define __ARCH_XTENSA_SRC_COMMON_XTENSA_MACROS_H 1 /**************************************************************************** diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 06ba9cad86..1312fd1cf6 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -39,7 +39,7 @@ HEAD_ASRC = # Common XTENSA files (arch/xtensa/src/common) -CMN_ASRCS = +CMN_ASRCS = xtensa_irq.S CMN_CSRCS = xtensa_allocateheap.c xtensa_createstack.c xtensa_exit.c CMN_CSRCS += xtensa_idle.c xtensa_initialize.c xtensa_interruptcontext.c CMN_CSRCS += xtensa_lowputs.c xtensa_mdelay.c xtensa_modifyreg8.c diff --git a/configs/esp32-core/nsh/defconfig b/configs/esp32-core/nsh/defconfig index cee088cc3e..082df28cc6 100644 --- a/configs/esp32-core/nsh/defconfig +++ b/configs/esp32-core/nsh/defconfig @@ -73,6 +73,11 @@ CONFIG_ARCH="xtensa" CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_FAMILY_LX6=y +# CONFIG_XTENSA_HAVE_LOOPS is not set +CONFIG_XTENSA_HAVE_INTERRUPTS=y +# CONFIG_XTENSA_USE_SWPRI is not set +CONFIG_XTENSA_CALL0_ABI=y +# CONFIG_XTENSA_USE_OVLY is not set # # Architecture Options @@ -550,10 +555,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set -- GitLab From eada2bf8d8c7acdef8c020018522df2ebdb00c2e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 15 Oct 2016 12:23:36 -0600 Subject: [PATCH 087/734] XTENSA: Add function prototypes --- arch/xtensa/include/irq.h | 33 +++++++++++++++++++++++++++++---- arch/xtensa/include/types.h | 2 +- 2 files changed, 30 insertions(+), 5 deletions(-) diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index 49bfc5b138..7e47291618 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -47,6 +47,7 @@ /* Include NuttX-specific IRQ definitions */ #include +#include /* Include architecture-specific IRQ definitions */ @@ -180,10 +181,6 @@ struct xcptcontext * Public Data ****************************************************************************/ -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - #ifdef __cplusplus #define EXTERN extern "C" extern "C" @@ -192,6 +189,34 @@ extern "C" #define EXTERN extern #endif +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_enable_interrupts + * + * Description: + * Enables a set of interrupts. Does not simply set INTENABLE directly, + * but computes it as a function of the current virtual priority. + * Can be called from interrupt handlers. + * + ****************************************************************************/ + +irqstate_t xtensa_enable_interrupts(irqstate_t mask); + +/**************************************************************************** + * Name: xtensa_disable_interrupts + * + * Description: + * Disables a set of interrupts. Does not simply set INTENABLE directly, + * but computes it as a function of the current virtual priority. + * Can be called from interrupt handlers. + * + ****************************************************************************/ + +irqstate_t xtensa_disable_interrupts(irqstate_t mask); + #undef EXTERN #ifdef __cplusplus } diff --git a/arch/xtensa/include/types.h b/arch/xtensa/include/types.h index ea8e19ff36..55d2fee188 100644 --- a/arch/xtensa/include/types.h +++ b/arch/xtensa/include/types.h @@ -83,7 +83,7 @@ typedef unsigned long _uintptr_t; /* This is the size of the interrupt state save returned by up_irq_save(). */ -typedef unsigned long irqstate_t; +typedef unsigned int irqstate_t; #endif /* __ASSEMBLY__ */ -- GitLab From 275120a6d1c880c8e1331939950005a558d6ee0c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 15 Oct 2016 14:57:06 -0600 Subject: [PATCH 088/734] XTENSA: Add some context switching definitions (incomplete); ESP32: Add some dummy LED definitions --- arch/xtensa/src/common/xtensa_context.S | 666 ++++++++++++++++++++++++ configs/esp32-core/README.txt | 109 ++++ configs/esp32-core/include/board.h | 25 + 3 files changed, 800 insertions(+) create mode 100644 arch/xtensa/src/common/xtensa_context.S diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S new file mode 100644 index 0000000000..60a4d6edb3 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_context.S @@ -0,0 +1,666 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_context.S + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * + * Copyright (c) 2006-2015 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + +/* XTENSA CONTEXT SAVE AND RESTORE ROUTINES + * + * Low-level Call0 functions for handling generic context save and restore of + * registers not specifically addressed by the interrupt vectors and handlers. + * Those registers (not handled by these functions) are PC, PS, A0, A1 (SP). + * Except for the calls to RTOS functions, this code is generic to Xtensa. + * + * Note that in Call0 ABI, interrupt handlers are expected to preserve the callee- + * save regs (A12-A15), which is always the case if the handlers are coded in C. + * However A12, A13 are made available as scratch registers for interrupt dispatch + * code, so are presumed saved anyway, and are always restored even in Call0 ABI. + * Only A14, A15 are truly handled as callee-save regs. + * + * Because Xtensa is a configurable architecture, this port supports all user + * generated configurations (except restrictions stated in the release notes). + * This is accomplished by conditional compilation using macros and functions + * defined in the Xtensa HAL (hardware adaptation layer) for your configuration. + * Only the processor state included in your configuration is saved and restored, + * including any processor state added by user configuration options or TIE. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "xtensa_rtos.h" +#include "xtensa_context.h" + +#ifdef CONFIG_XTENSA_USE_OVLY +# include +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + + .text + +/**************************************************************************** + * Name: _xtensa_context_save + * + * Description: + * + * NOTE: MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION! + * + * Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13, + * in the interrupt stack frame defined in xtensa_rtos.h. Its counterpart + * is _xtensa_context_restore (which also restores A12, A13). + * + * Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the + * frame. This function preserves A12 & A13 in order to provide the caller + * with 2 scratch regs that need not be saved over the call to this + * function. The choice of which 2 regs to provide is governed by + * xthal_window_spill_nw and xthal_save_extra_nw, to avoid moving data + * more than necessary. Caller can assign regs accordingly. + * + * Entry Conditions: + * - A0 = Return address in caller. + * - A1 = Stack pointer of interrupted thread or handler ("interruptee"). + * - Original A12, A13 have already been saved in the interrupt stack + * frame. + * - Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as a + * the point of interruption. + * - If windowed ABI, PS.EXCM = 1 (exceptions disabled). + * + * Exit conditions: + * - A0 = Return address in caller. + * - A1 = Stack pointer of interrupted thread or handler ("interruptee"). + * - A12, A13 as at entry (preserved). + * - If windowed ABI, PS.EXCM = 1 (exceptions disabled). + * + ****************************************************************************/ + + .global _xtensa_context_save + .type _xtensa_context_save, @function + .align 4 + .literal_position + .align 4 +_xtensa_context_save: + + s32i a2, sp, (4 * REG_A2) + s32i a3, sp, (4 * REG_A3) + s32i a4, sp, (4 * REG_A4) + s32i a5, sp, (4 * REG_A5) + s32i a6, sp, (4 * REG_A6) + s32i a7, sp, (4 * REG_A7) + s32i a8, sp, (4 * REG_A8) + s32i a9, sp, (4 * REG_A9) + s32i a10, sp, (4 * REG_A10) + s32i a11, sp, (4 * REG_A11) + + /* Call0 ABI callee-saved regs a12-15 do not need to be saved here. + * a12-13 are the caller's responsibility so it can use them as scratch. + * So only need to save a14-a15 here for Windowed ABI (not Call0). + */ + +#ifndef CONFIG_XTENSA_CALL0_ABI + s32i a14, sp, (4 * REG_A14) + s32i a15, sp, (4 * REG_A15) +#endif + + rsr a3, SAR + s32i a3, sp, (4 * REG_SAR) + +#ifdef CONFIG_XTENSA_HAVE_LOOPS + rsr a3, LBEG + s32i a3, sp, (4 * REG_LBEG) + rsr a3, LEND + s32i a3, sp, (4 * REG_LEND) + rsr a3, LCOUNT + s32i a3, sp, (4 * REG_LCOUNT) +#endif + +#ifdef CONFIG_XTENSA_USE_SWPRI + /* Save virtual priority mask */ + + movi a3, _xtensa_vprimask + l32i a3, a3, 0 + s32i a3, sp, (4 * REG_VPRI) +#endif + +#if XCHAL_EXTRA_SA_SIZE > 0 || !defined(CONFIG_XTENSA_CALL0_ABI) + mov a9, a0 /* Preserve ret addr */ + #endif + +#ifndef CONFIG_XTENSA_CALL0_ABI + /* To spill the reg windows, temp. need pre-interrupt stack ptr and + * a4-15. Need to save a9,12,13 temporarily (in frame temps) and + * recover originals. Interrupts need to be disabled below + * XCHAL_EXCM_LEVEL and window overflow and underflow exceptions + * disabled (assured by PS.EXCM == 1). + */ + + s32i a12, sp, (4 * REG_TMP0) /* Temp. save stuff in stack frame */ + s32i a13, sp, (4 * REG_TMP1) + s32i a9, sp, (4 * REG_TMP2) + + /* Save the overlay state if we are supporting overlays. Since we just + * saved three registers, we can conveniently use them here. Note that + * as of now, overlays only work for windowed calling ABI. + */ + +#ifdef CONFIG_XTENSA_USE_OVLY + l32i a9, sp, (4 * REG_PC) /* Recover saved PC */ + _xt_overlay_get_state a9, a12, a13 + s32i a9, sp, (4 * REG_OVLY) /* Save overlay state */ +#endif + + l32i a12, sp, (4 * REG_A12) /* Recover original a9,12,13 */ + l32i a13, sp, (4 * REG_A13) + l32i a9, sp, (4 * REG_A9) + addi sp, sp, (4 * REG_FRMSZ) /* Restore the interruptee's SP */ + call0 xthal_window_spill_nw /* Preserves only a4,5,8,9,12,13 */ + addi sp, sp, -(4 * REG_FRMSZ) + l32i a12, sp, (4 * REG_TMP0) /* Recover stuff from stack frame */ + l32i a13, sp, (4 * REG_TMP1) + l32i a9, sp, (4 * REG_TMP2) +#endif + +#if XCHAL_EXTRA_SA_SIZE > 0 + /* NOTE: Normally the xthal_save_extra_nw macro only affects address + * registers a2-a5. It is theoretically possible for Xtensa processor + * designers to write TIE that causes more address registers to be + * affected, but it is generally unlikely. If that ever happens, + * more registers need to be saved/restored around this macro invocation. + * Here we assume a9,12,13 are preserved. + * Future Xtensa tools releases might limit the regs that can be affected. + */ + + addi a2, sp, (4 * REG_EXTRA) /* Where to save it */ +#if XCHAL_EXTRA_SA_ALIGN > 16 + movi a3, -XCHAL_EXTRA_SA_ALIGN + and a2, a2, a3 /* Align dynamically >16 bytes */ +#endif + call0 xthal_save_extra_nw /* Destroys a0,2,3,4,5 */ +#endif + +#if XCHAL_EXTRA_SA_SIZE > 0 || !defined(CONFIG_XTENSA_CALL0_ABI) + mov a0, a9 /* Retrieve ret addr */ +#endif + + ret + +/**************************************************************************** + * Name: _xtensa_context_restore + * + * Description: + * + * NOTE: MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION! + * + * Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in + * Call0 ABI, A14, A15 which are preserved by all interrupt handlers) from + * an interrupt stack frame defined in xtensa_rtos.h. + * Its counterpart is _xtensa_context_save (whose caller saved A12, A13). + * + * Caller is responsible to restore PC, PS, A0, A1 (SP). + * + * Entry Conditions: + * - A0 = Return address in caller. + * - A1 = Stack pointer of interrupted thread or handler ("interruptee"). + * + * Exit conditions: + * - A0 = Return address in caller. + * - A1 = Stack pointer of interrupted thread or handler ("interruptee"). + * - Other processor state except PC, PS, A0, A1 (SP), is as at the point + * of interruption. + * + ****************************************************************************/ + + .global _xtensa_context_restore + .type _xtensa_context_restore,@function + .align 4 + .literal_position + .align 4 +_xtensa_context_restore: + +#if XCHAL_EXTRA_SA_SIZE > 0 + /* NOTE: Normally the xthal_restore_extra_nw macro only affects address + * registers a2-a5. It is theoretically possible for Xtensa processor + * designers to write TIE that causes more address registers to be + * affected, but it is generally unlikely. If that ever happens, + * more registers need to be saved/restored around this macro invocation. + * Here we only assume a13 is preserved. + * Future Xtensa tools releases might limit the regs that can be affected. + */ + + mov a13, a0 /* Preserve ret addr */ + addi a2, sp, (4 * REG_EXTRA) /* Where to find it */ +#if XCHAL_EXTRA_SA_ALIGN > 16 + movi a3, -XCHAL_EXTRA_SA_ALIGN + and a2, a2, a3 /* Align dynamically >16 bytes */ +#endif + call0 xthal_restore_extra_nw /* Destroys a0,2,3,4,5 */ + mov a0, a13 /* Retrieve ret addr */ +#endif + +#ifdef CONFIG_XTENSA_HAVE_LOOPS + l32i a2, sp, (4 * REG_LBEG) + l32i a3, sp, (4 * REG_LEND) + wsr a2, LBEG + l32i a2, sp, (4 * REG_LCOUNT) + wsr a3, LEND + wsr a2, LCOUNT +#endif + +#ifdef CONFIG_XTENSA_USE_OVLY + /* If we are using overlays, this is a good spot to check if we need + * to restore an overlay for the incoming task. Here we have a bunch + * of registers to spare. Note that this step is going to use a few + * bytes of storage below SP (SP-20 to SP-32) if an overlay is going + * to be restored. + */ + + l32i a2, sp, (4 * REG_PC) /* Retrieve PC */ + l32i a3, sp, (4 * REG_PS) /* Retrieve PS */ + l32i a4, sp, (4 * REG_OVLY) /* Retrieve overlay state */ + l32i a5, sp, (4 * REG_A1) /* Retrieve stack ptr */ + _xt_overlay_check_map a2, a3, a4, a5, a6 + s32i a2, sp, (4 * REG_PC) /* Save updated PC */ + s32i a3, sp, (4 * REG_PS) /* Save updated PS */ +#endif + +#ifdef CONFIG_XTENSA_USE_SWPRI + /* Restore virtual interrupt priority and interrupt enable */ + + movi a3, _xtensa_intdata + l32i a4, a3, 0 /* a4 = _xtensa_intenable */ + l32i a5, sp, (4 * REG_VPRI) /* a5 = saved _xtensa_vprimask */ + and a4, a4, a5 + wsr a4, INTENABLE /* Update INTENABLE */ + s32i a5, a3, 4 /* Restore _xtensa_vprimask */ + #endif + + l32i a3, sp, (4 * REG_SAR) + l32i a2, sp, (4 * REG_A2) + wsr a3, SAR + l32i a3, sp, (4 * REG_A3) + l32i a4, sp, (4 * REG_A4) + l32i a5, sp, (4 * REG_A5) + l32i a6, sp, (4 * REG_A6) + l32i a7, sp, (4 * REG_A7) + l32i a8, sp, (4 * REG_A8) + l32i a9, sp, (4 * REG_A9) + l32i a10, sp, (4 * REG_A10) + l32i a11, sp, (4 * REG_A11) + + /* Call0 ABI callee-saved regs a12-15 do not need to be restored here. + * However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(), + * so need to be restored anyway, despite being callee-saved in Call0. + */ + + l32i a12, sp, (4 * REG_A12) + l32i a13, sp, (4 * REG_A13) +#ifndef CONFIG_XTENSA_CALL0_ABI + l32i a14, sp, (4 * REG_A14) + l32i a15, sp, (4 * REG_A15) +#endif + + ret + +/**************************************************************************** + * Name: _xt_coproc_init + * + * Description: + * + * + ****************************************************************************/ + + + + * Initializes global co-processor management data, setting all co- + * processors to "unowned". Leaves CPENABLE as it found it (does NOT clear + * it). + * + * Called during initialization of the RTOS, before any threads run. + * + * This may be called from normal Xtensa single-threaded application code + * which might use co-processors. The Xtensa run-time initialization enables + * all co-processors. They must remain enabled here, else a co-processor + * exception might occur outside of a thread, which the exception handler + * doesn't expect. + * + * Entry Conditions: + * - Xtensa single-threaded run-time environment is in effect. + * No thread is yet running. + * + * Exit conditions: + * - None. + * + * Obeys ABI conventions per prototype: + * void _xt_coproc_init(void) + * + ****************************************************************************/ + +#if XCHAL_CP_NUM > 0 + .global _xt_coproc_init + .type _xt_coproc_init,@function + .align 4 + .literal_position + .align 4 +_xt_coproc_init: + ENTRY0 + + /* Initialize thread co-processor ownerships to 0 (unowned). */ + + movi a2, _xt_coproc_owner_sa /* a2 = base of owner array */ + addi a3, a2, (XCHAL_CP_MAX*portNUM_PROCESSORS) << 2 /* a3 = top+1 of owner array */ + movi a4, 0 /* a4 = 0 (unowned) */ +1: s32i a4, a2, 0 + addi a2, a2, 4 + bltu a2, a3, 1b + + RET0 +#endif + +/**************************************************************************** + * Name: _xt_coproc_release + * + * Description: + * Releases any and all co-processors owned by a given thread. The thread + * is identified by it's co-processor state save area defined in + * xtensa_context.h. + * + * Must be called before a thread's co-proc save area is deleted to avoid + * memory corruption when the exception handler tries to save the state. + * May be called when a thread terminates or completes but does not delete + * the co-proc save area, to avoid the exception handler having to save + * the thread's co-proc state before another thread can use it + * (optimization). + * + * Entry Conditions: + * - A2 = Pointer to base of co-processor state save area. + * + * Exit conditions: + * - None. + * + * Obeys ABI conventions per prototype: + * void _xt_coproc_release(void * coproc_sa_base) + * + ****************************************************************************/ + +#if XCHAL_CP_NUM > 0 + .global _xt_coproc_release + .type _xt_coproc_release,@function + .align 4 + .literal_position + .align 4 +_xt_coproc_release: + ENTRY0 /* a2 = base of save area */ + + getcoreid a5 + movi a3, XCHAL_CP_MAX << 2 + mull a5, a5, a3 + movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */ + add a3, a3, a5 + + addi a4, a3, XCHAL_CP_MAX << 2 /* a4 = top+1 of owner array */ + movi a5, 0 /* a5 = 0 (unowned) */ + + rsil a6, XCHAL_EXCM_LEVEL /* lock interrupts */ + +1: l32i a7, a3, 0 /* a7 = owner at a3 */ + bne a2, a7, 2f /* if (coproc_sa_base == owner) */ + s32i a5, a3, 0 /* owner = unowned */ +2: addi a3, a3, 1<<2 /* a3 = next entry in owner array */ + bltu a3, a4, 1b /* repeat until end of array */ + +3: wsr a6, PS /* restore interrupts */ + + RET0 +#endif + +/**************************************************************************** + * Name: _xt_coproc_savecs + * + * Description: + * If there is a current thread and it has a coprocessor state save area, + * then save all callee-saved state into this area. This function is called + * from the solicited context switch handler. It calls a system-specific + * function to get the coprocessor save area base address. + * + * Entry conditions: + * - The thread being switched out is still the current thread. + * - CPENABLE state reflects which coprocessors are active. + * - Registers have been saved/spilled already. + * + * Exit conditions: + * - All necessary CP callee-saved state has been saved. + * - Registers a2-a7, a13-a15 have been trashed. + * + * Must be called from assembly code only, using CALL0. + * + ****************************************************************************/ + +#if XCHAL_CP_NUM > 0 + .extern _xt_coproc_sa_offset /* external reference */ + .global _xt_coproc_savecs + .type _xt_coproc_savecs,@function + .align 4 + .literal_position + .align 4 +_xt_coproc_savecs: + + /* At entry, CPENABLE should be showing which CPs are enabled. */ + + rsr a2, CPENABLE /* a2 = which CPs are enabled */ + beqz a2, .Ldone /* quick exit if none */ + mov a14, a0 /* save return address */ + call0 XT_RTOS_CP_STATE /* get address of CP save area */ + mov a0, a14 /* restore return address */ + beqz a15, .Ldone /* if none then nothing to do */ + s16i a2, a15, XT_CP_CS_ST /* save mask of CPs being stored */ + movi a13, _xt_coproc_sa_offset /* array of CP save offsets */ + l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ + +#if XCHAL_CP0_SA_SIZE + bbci.l a2, 0, 2f /* CP 0 not enabled */ + l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ + add a3, a14, a15 /* a3 = save area for CP 0 */ + xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP1_SA_SIZE + bbci.l a2, 1, 2f /* CP 1 not enabled */ + l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ + add a3, a14, a15 /* a3 = save area for CP 1 */ + xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP2_SA_SIZE + bbci.l a2, 2, 2f + l32i a14, a13, 8 + add a3, a14, a15 + xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP3_SA_SIZE + bbci.l a2, 3, 2f + l32i a14, a13, 12 + add a3, a14, a15 + xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP4_SA_SIZE + bbci.l a2, 4, 2f + l32i a14, a13, 16 + add a3, a14, a15 + xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP5_SA_SIZE + bbci.l a2, 5, 2f + l32i a14, a13, 20 + add a3, a14, a15 + xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP6_SA_SIZE + bbci.l a2, 6, 2f + l32i a14, a13, 24 + add a3, a14, a15 + xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP7_SA_SIZE + bbci.l a2, 7, 2f + l32i a14, a13, 28 + add a3, a14, a15 + xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +.Ldone: + ret +#endif + +/**************************************************************************** + * Name: _xt_coproc_restorecs + * + * Description: + * Restore any callee-saved coprocessor state for the incoming thread. + * This function is called from coprocessor exception handling, when + * giving ownership to a thread that solicited a context switch earlier. + * It calls a system-specific function to get the coprocessor save area + * base address. + * + * Entry conditions: + * - The incoming thread is set as the current thread. + * - CPENABLE is set up correctly for all required coprocessors. + * - a2 = mask of coprocessors to be restored. + * + * Exit conditions: + * - All necessary CP callee-saved state has been restored. + * - CPENABLE - unchanged. + * - Registers a2-a7, a13-a15 have been trashed. + * + * Must be called from assembly code only, using CALL0. + * + ****************************************************************************/ + +#if XCHAL_CP_NUM > 0 + .global _xt_coproc_restorecs + .type _xt_coproc_restorecs,@function + .align 4 + .literal_position + .align 4 +_xt_coproc_restorecs: + + mov a14, a0 /* Save return address */ + call0 XT_RTOS_CP_STATE /* Get address of CP save area */ + mov a0, a14 /* Restore return address */ + beqz a15, .Ldone2 /* If none then nothing to do */ + l16ui a3, a15, XT_CP_CS_ST /* a3 = which CPs have been saved */ + xor a3, a3, a2 /* Clear the ones being restored */ + s32i a3, a15, XT_CP_CS_ST /* Update saved CP mask */ + movi a13, _xt_coproc_sa_offset /* Array of CP save offsets */ + l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ + +#if XCHAL_CP0_SA_SIZE + bbci.l a2, 0, 2f /* CP 0 not enabled */ + l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ + add a3, a14, a15 /* a3 = save area for CP 0 */ + xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP1_SA_SIZE + bbci.l a2, 1, 2f /* CP 1 not enabled */ + l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ + add a3, a14, a15 /* a3 = save area for CP 1 */ + xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP2_SA_SIZE + bbci.l a2, 2, 2f + l32i a14, a13, 8 + add a3, a14, a15 + xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP3_SA_SIZE + bbci.l a2, 3, 2f + l32i a14, a13, 12 + add a3, a14, a15 + xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP4_SA_SIZE + bbci.l a2, 4, 2f + l32i a14, a13, 16 + add a3, a14, a15 + xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP5_SA_SIZE + bbci.l a2, 5, 2f + l32i a14, a13, 20 + add a3, a14, a15 + xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP6_SA_SIZE + bbci.l a2, 6, 2f + l32i a14, a13, 24 + add a3, a14, a15 + xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP7_SA_SIZE + bbci.l a2, 7, 2f + l32i a14, a13, 28 + add a3, a14, a15 + xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +.Ldone2: + ret + +#endif diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index 514c84cef9..2b8278dab3 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -13,6 +13,21 @@ README for the Expressif ESP32 Core board (V2) "application"), however for most purposes the two CPUs are interchangeable. +Contents +======== + + o STATUS + o ESP32 Features + o ESP32 Toolchain + o Serial Console + o Buttons and LEDs + o Configurations + +STATUS +====== + + The basic port is underway. No testing has yet been performed. + ESP32 Features ============== @@ -60,3 +75,97 @@ ESP32 Toolchain NOTE: The xtensa-esp32-elf configuration is only available in the xtensa-1.22.x branch. + +Serial Console +============== + + To be provided + +Buttons and LEDs +================ + + NOTE: As of this writing, I have no schematic for the ESP32 Core board. + The following information derives only from examining the parts visible + on the board. + + Buttons + ------- + I see two buttons labelled Boot and EN. I suspect that neither is + available to software. + + LEDs + A single LED labelled D1 is available. + + When CONFIG_ARCH_LEDS is defined in the NuttX configuration, NuttX will + control the LED as follows: + + SYMBOL Meaning LED + ------------------- ----------------------- ------ + LED_STARTED NuttX has been started OFF + LED_HEAPALLOCATE Heap has been allocated OFF + LED_IRQSENABLED Interrupts enabled OFF + LED_STACKCREATED Idle stack created ON + LED_INIRQ In an interrupt N/C + LED_SIGNAL In a signal handler N/C + LED_ASSERTION An assertion failed N/C + LED_PANIC The system has crashed FLASH + + Thus is LED is statically on, NuttX has successfully booted and is, + apparently, running normally. If LED is flashing at approximately + 2Hz, then a fatal error has been detected and the system has halted. + +Configurations +============== + + Common Configuration Information + -------------------------------- + Each ESP32 core configuration is maintained in sub-directories and + can be selected as follow: + + cd tools + ./configure.sh esp32-core/ + cd - + make oldconfig + . ./setenv.sh + + Before sourcing the setenv.sh file above, you should examine it and + perform edits as necessary so that TOOLCHAIN_BIN is the correct path to + the directory than holds your toolchain binaries. + + If this is a Windows native build, then configure.bat should be used + instead of configure.sh: + + configure.bat esp32-core\ + + And then build NuttX by simply typing the following. At the conclusion of + the make, the nuttx binary will reside in an ELF file called, simply, + nuttx. + + make oldconfig + make + + The that is provided above as an argument to the + tools/configure.sh must be is one of the directories listed below. + +NOTES: + + 1. These configurations use the mconf-based configuration tool. To + change any of these configurations using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository. + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Unless stated otherwise, all configurations generate console + output on [To be provided]. + + Configuration sub-directories + ----------------------------- + + nsh: + + Configures the NuttShell (nsh) located at apps/examples/nsh. + + NOTES: diff --git a/configs/esp32-core/include/board.h b/configs/esp32-core/include/board.h index d07ba907cf..2a82eb16e8 100644 --- a/configs/esp32-core/include/board.h +++ b/configs/esp32-core/include/board.h @@ -36,4 +36,29 @@ #ifndef __CONFIGS_ESP32_CORE_INCLUDE_BOARD_H #define __CONFIGS_ESP32_CORE_INCLUDE_BOARD_H +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* A single LED labelled D1 is available. + * + * When CONFIG_ARCH_LEDS is defined in the NuttX configuration, NuttX will + * control the LED as follows: + * + * SYMBOL Value Meaning LED + * ------------------- ----- ----------------------- ------ */ +#define LED_STARTED 0 /* NuttX has been started OFF */ +#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */ +#define LED_STACKCREATED 1 /* Idle stack created ON */ +#define LED_INIRQ 2 /* In an interrupt N/C */ +#define LED_SIGNAL 2 /* In a signal handler N/C */ +#define LED_ASSERTION 2 /* An assertion failed N/C */ +#define LED_PANIC 3 /* The system has crashed FLASH */ + +/* Thus if the LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If LED is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + #endif /* __CONFIGS_ESP32_CORE_INCLUDE_BOARD_H */ -- GitLab From a8662c70db7b0e42836b29ab96f5ddfb205145d7 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 16 Oct 2016 07:57:16 -0600 Subject: [PATCH 089/734] Xtensa: Keep task state in TCB (unless you want to redesign signal handling). Lots of cosmetic clean-up. --- arch/xtensa/include/irq.h | 4 +- arch/xtensa/src/common/xtensa.h | 51 +++++++++------ arch/xtensa/src/common/xtensa_allocateheap.c | 15 +---- .../common/{up_arch.h => xtensa_copystate.c} | 62 +++++++------------ arch/xtensa/src/common/xtensa_createstack.c | 3 +- arch/xtensa/src/common/xtensa_etherstub.c | 18 +----- arch/xtensa/src/common/xtensa_exit.c | 9 ++- arch/xtensa/src/common/xtensa_idle.c | 2 +- arch/xtensa/src/common/xtensa_initialize.c | 15 +++-- .../src/common/xtensa_interruptcontext.c | 10 +-- arch/xtensa/src/common/xtensa_lowputs.c | 14 +---- arch/xtensa/src/common/xtensa_mdelay.c | 22 +------ arch/xtensa/src/common/xtensa_modifyreg16.c | 16 +---- arch/xtensa/src/common/xtensa_modifyreg32.c | 16 +---- arch/xtensa/src/common/xtensa_modifyreg8.c | 16 +---- arch/xtensa/src/common/xtensa_puts.c | 14 +---- arch/xtensa/src/common/xtensa_releasestack.c | 10 +-- arch/xtensa/src/common/xtensa_stackframe.c | 2 +- arch/xtensa/src/common/xtensa_udelay.c | 18 +----- arch/xtensa/src/common/xtensa_usestack.c | 2 +- 20 files changed, 87 insertions(+), 232 deletions(-) rename arch/xtensa/src/common/{up_arch.h => xtensa_copystate.c} (62%) diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index 7e47291618..101cda03fb 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -159,9 +159,9 @@ struct xcptcontext uint32_t saved_cpsr; #endif - /* Pointer to the register save area on the stack*/ + /* Register save area */ - uint32_t *regs; + uint32_t regs[XCPTCONTEXT_REGS]; #ifdef CONFIG_LIB_SYSCALL /* The following array holds the return address and the exc_return value diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index 01a3ed9e06..849500863c 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -104,19 +104,28 @@ # define CONFIG_ARCH_INTERRUPTSTACK 0 #endif -/* In the XTENSA model, only a pointer to register state on the stack is - * saved in the TCB. +/* In the XTENSA model, the state is copied from the stack to the TCB, but + * only a referenced is passed to get the state from the TCB. */ -#define up_savestate(regs) do { reg = g_current_regs; } while (0) -#define up_restorestate(regs) do { g_current_regs = regs; } while (0) +#define xtensa_savestate(regs) xtensa_copystate(regs, (uint32_t*)g_current_regs) +#define xtensa_restorestate(regs) do { g_current_regs = regs; } while (0) + +/* Register access macros */ + +# define getreg8(a) (*(volatile uint8_t *)(a)) +# define putreg8(v,a) (*(volatile uint8_t *)(a) = (v)) +# define getreg16(a) (*(volatile uint16_t *)(a)) +# define putreg16(v,a) (*(volatile uint16_t *)(a) = (v)) +# define getreg32(a) (*(volatile uint32_t *)(a)) +# define putreg32(v,a) (*(volatile uint32_t *)(a) = (v)) /**************************************************************************** * Public Types ****************************************************************************/ #ifndef __ASSEMBLY__ -typedef void (*up_vector_t)(void); +typedef void (*xtensa_vector_t)(void); #endif /**************************************************************************** @@ -130,7 +139,7 @@ typedef void (*up_vector_t)(void); extern volatile uint32_t *g_current_regs; -/* This is the beginning of heap as provided from up_head.S. This is the +/* This is the beginning of heap as provided from *_head.S. This is the * first address in DRAM after the loaded program+bss+idle stack. The end * of the heap is CONFIG_RAM_END */ @@ -183,14 +192,20 @@ extern uint32_t _bmxdupba_address; /* BMX register setting */ #ifndef __ASSEMBLY__ /* Common Functions *********************************************************/ -/* Common functions define in arch/mips/src/common. These may be replaced +/* Common functions defined in arch/mips/src/common. These may be replaced * with chip-specific functions of the same name if needed. See also * functions prototyped in include/nuttx/arch.h. */ +/* Atomic modification of registers */ + +void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits); +void modifyreg16(unsigned int addr, uint16_t clearbits, uint16_t setbits); +void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits); + /* Context switching */ -void up_copystate(uint32_t *dest, uint32_t *src); +void xtensa_copystate(uint32_t *dest, uint32_t *src); /* Serial output */ @@ -208,36 +223,36 @@ void lowconsole_init(void); /* Debug */ #ifdef CONFIG_ARCH_STACKDUMP -void up_dumpstate(void); +void xtensa_dumpstate(void); #else -# define up_dumpstate() +# define xtensa_dumpstate() #endif /* Common XTENSA functions */ /* IRQs */ -uint32_t *up_doirq(int irq, uint32_t *regs); +uint32_t *xtensa_doirq(int irq, uint32_t *regs); /* Software interrupt handler */ -int up_swint(int irq, FAR void *context); +int xtensa_swint(int irq, FAR void *context); /* Signals */ -void up_sigdeliver(void); +void xtensa_sigdeliver(void); /* Chip-specific functions **************************************************/ /* Chip specific functions defined in arch/mips/src/ */ /* IRQs */ -void up_irqinitialize(void); -bool up_pending_irq(int irq); -void up_clrpend_irq(int irq); +void xtensa_irq_initialize(void); +bool xtensa_pending_irq(int irq); +void xtensa_clrpend_irq(int irq); /* DMA */ #ifdef CONFIG_ARCH_DMA -void weak_function up_dmainitialize(void); +void weak_function xtensa_dma_initialize(void); #endif /* Memory management */ @@ -261,7 +276,7 @@ void up_serialinit(void); /* System timer */ -void up_timer_initialize(void); +void xtensa_timer_initialize(void); /* Network */ diff --git a/arch/xtensa/src/common/xtensa_allocateheap.c b/arch/xtensa/src/common/xtensa_allocateheap.c index b821eb4e34..692624bece 100644 --- a/arch/xtensa/src/common/xtensa_allocateheap.c +++ b/arch/xtensa/src/common/xtensa_allocateheap.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/xtensa/src/common/xtensa_allocateheap.c * - * Copyright (C) 2010, 2013, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -46,21 +46,8 @@ #include #include -#include "up_arch.h" #include "xtensa.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/xtensa/src/common/up_arch.h b/arch/xtensa/src/common/xtensa_copystate.c similarity index 62% rename from arch/xtensa/src/common/up_arch.h rename to arch/xtensa/src/common/xtensa_copystate.c index 4fd625bf7a..ade771715d 100644 --- a/arch/xtensa/src/common/up_arch.h +++ b/arch/xtensa/src/common/xtensa_copystate.c @@ -1,7 +1,7 @@ /**************************************************************************** - * arch/xtensa/src/common/xtensa_arch.h + * arch/xtensa/src/common/xtensa_copystate.c * - * Copyright (C) 2010, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,58 +33,42 @@ * ****************************************************************************/ -#ifndef ___ARCH_XTENSA_SRC_COMMON_XTENSA_ARCH_H -#define ___ARCH_XTENSA_SRC_COMMON_XTENSA_ARCH_H - /**************************************************************************** * Included Files ****************************************************************************/ #include -#ifndef __ASSEMBLY__ -# include -#endif -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ +#include +#include + +#include "xtensa.h" /**************************************************************************** - * Inline Functions + * Public Functions ****************************************************************************/ -#ifndef __ASSEMBLY__ - -# define getreg8(a) (*(volatile uint8_t *)(a)) -# define putreg8(v,a) (*(volatile uint8_t *)(a) = (v)) -# define getreg16(a) (*(volatile uint16_t *)(a)) -# define putreg16(v,a) (*(volatile uint16_t *)(a) = (v)) -# define getreg32(a) (*(volatile uint32_t *)(a)) -# define putreg32(v,a) (*(volatile uint32_t *)(a) = (v)) - /**************************************************************************** - * Public Function Prototypes + * Name: up_copystate ****************************************************************************/ -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif +/* A little faster than most memcpy's */ -/* Atomic modification of registers */ +void xtensa_copystate(uint32_t *dest, uint32_t *src) +{ + int i; -void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits); -void modifyreg16(unsigned int addr, uint16_t clearbits, uint16_t setbits); -void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits); + /* In the XTENSA model, the state is copied from the stack to the TCB, + * but only a reference is passed to get the state from the TCB. So the + * following check avoids copying the TCB save area onto itself: + */ -#undef EXTERN -#if defined(__cplusplus) + if (src != dest) + { + for (i = 0; i < XCPTCONTEXT_REGS; i++) + { + *dest++ = *src++; + } + } } -#endif -#endif /* __ASSEMBLY__ */ -#endif /* ___ARCH_XTENSA_SRC_COMMON_XTENSA_ARCH_H */ diff --git a/arch/xtensa/src/common/xtensa_createstack.c b/arch/xtensa/src/common/xtensa_createstack.c index f895f47a50..d4769f33d0 100644 --- a/arch/xtensa/src/common/xtensa_createstack.c +++ b/arch/xtensa/src/common/xtensa_createstack.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/xtensa/src/common/xtensa_createstack.c * - * Copyright (C) 2011, 2013, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -49,7 +49,6 @@ #include #include -#include "up_arch.h" #include "xtensa.h" /**************************************************************************** diff --git a/arch/xtensa/src/common/xtensa_etherstub.c b/arch/xtensa/src/common/xtensa_etherstub.c index b41b7bf6d4..9174a0e6d6 100644 --- a/arch/xtensa/src/common/xtensa_etherstub.c +++ b/arch/xtensa/src/common/xtensa_etherstub.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/xtensa/src/common/xtensa_etherstub.c * - * Copyright (C) 2011-2012, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -41,22 +41,6 @@ #include "xtensa.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/xtensa/src/common/xtensa_exit.c b/arch/xtensa/src/common/xtensa_exit.c index 4f451539d2..0bc6da54d8 100644 --- a/arch/xtensa/src/common/xtensa_exit.c +++ b/arch/xtensa/src/common/xtensa_exit.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/xtensa/src/common/xtensa_exit.c * - * Copyright (C) 2011, 2013-2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -67,7 +67,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: _up_dumponexit + * Name: _xtensa_dumponexit * * Description: * Dump the state of all tasks whenever on task exits. This is debug @@ -77,7 +77,7 @@ ****************************************************************************/ #ifdef CONFIG_DUMP_ON_EXIT -static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) +static void _xtensa_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) { #if CONFIG_NFILE_DESCRIPTORS > 0 FAR struct filelist *filelist; @@ -152,7 +152,7 @@ void _exit(int status) #ifdef CONFIG_DUMP_ON_EXIT sinfo("Other tasks:\n"); - sched_foreach(_up_dumponexit, NULL); + sched_foreach(_xtensa_dumponexit, NULL); #endif /* Destroy the task at the head of the ready to run list. */ @@ -185,4 +185,3 @@ void _exit(int status) PANIC(); } - diff --git a/arch/xtensa/src/common/xtensa_idle.c b/arch/xtensa/src/common/xtensa_idle.c index 672a0fae1c..894cdb606b 100644 --- a/arch/xtensa/src/common/xtensa_idle.c +++ b/arch/xtensa/src/common/xtensa_idle.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/xtensa/src/common/xtensa_idle.c * - * Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without diff --git a/arch/xtensa/src/common/xtensa_initialize.c b/arch/xtensa/src/common/xtensa_initialize.c index 46de907db4..a66c3b8ecd 100644 --- a/arch/xtensa/src/common/xtensa_initialize.c +++ b/arch/xtensa/src/common/xtensa_initialize.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/xtensa/src/common/xtensa_initialize.c * - * Copyright (C) 2011-2013, 2015-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -57,7 +57,6 @@ #include -#include "up_arch.h" #include "xtensa.h" /**************************************************************************** @@ -128,7 +127,7 @@ void up_initialize(void) /* Initialize the interrupt subsystem */ - up_irqinitialize(); + xtensa_irq_initialize(); #ifdef CONFIG_PM /* Initialize the power management subsystem. This MCU-specific function @@ -141,22 +140,22 @@ void up_initialize(void) #endif #ifdef CONFIG_ARCH_DMA - /* Initialize the DMA subsystem if the weak function up_dmainitialize has been - * brought into the build + /* Initialize the DMA subsystem if the weak function xtensa_dma_initialize + * has been brought into the build */ #ifdef CONFIG_HAVE_WEAKFUNCTIONS - if (up_dmainitialize) + if (xtensa_dma_initialize) #endif { - up_dmainitialize(); + xtensa_dma_initialize(); } #endif /* Initialize the system timer interrupt */ #if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS) - up_timer_initialize(); + xtensa_timer_initialize(); #endif /* Register devices */ diff --git a/arch/xtensa/src/common/xtensa_interruptcontext.c b/arch/xtensa/src/common/xtensa_interruptcontext.c index 8b6bf802ec..db03c5c19d 100644 --- a/arch/xtensa/src/common/xtensa_interruptcontext.c +++ b/arch/xtensa/src/common/xtensa_interruptcontext.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/xtensa/src/common/xtensa_interruptcontext.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -45,14 +45,6 @@ #include "xtensa.h" -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/xtensa/src/common/xtensa_lowputs.c b/arch/xtensa/src/common/xtensa_lowputs.c index f1acb1059d..3daeadc3ef 100644 --- a/arch/xtensa/src/common/xtensa_lowputs.c +++ b/arch/xtensa/src/common/xtensa_lowputs.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/xtensa/src/common/xtensa_lowputs.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -41,18 +41,6 @@ #include "xtensa.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/xtensa/src/common/xtensa_mdelay.c b/arch/xtensa/src/common/xtensa_mdelay.c index f6b728bcc6..094ba97a79 100644 --- a/arch/xtensa/src/common/xtensa_mdelay.c +++ b/arch/xtensa/src/common/xtensa_mdelay.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/xtensa/src/common/xtensa_mdelay.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -40,26 +40,6 @@ #include #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/xtensa/src/common/xtensa_modifyreg16.c b/arch/xtensa/src/common/xtensa_modifyreg16.c index 98a51c86ba..8554fda46f 100644 --- a/arch/xtensa/src/common/xtensa_modifyreg16.c +++ b/arch/xtensa/src/common/xtensa_modifyreg16.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/xtensa/src/common/xtensa_modifyreg16.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -45,19 +45,7 @@ #include #include -#include "up_arch.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ +#include "xtensa.h" /**************************************************************************** * Public Functions diff --git a/arch/xtensa/src/common/xtensa_modifyreg32.c b/arch/xtensa/src/common/xtensa_modifyreg32.c index 5619e6f272..599e39db4b 100644 --- a/arch/xtensa/src/common/xtensa_modifyreg32.c +++ b/arch/xtensa/src/common/xtensa_modifyreg32.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/xtensa/src/common/xtensa_modifyreg32.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -45,19 +45,7 @@ #include #include -#include "up_arch.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ +#include "xtensa.h" /**************************************************************************** * Public Functions diff --git a/arch/xtensa/src/common/xtensa_modifyreg8.c b/arch/xtensa/src/common/xtensa_modifyreg8.c index e3bc73843e..24201b5e97 100644 --- a/arch/xtensa/src/common/xtensa_modifyreg8.c +++ b/arch/xtensa/src/common/xtensa_modifyreg8.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/xtensa/src/common/xtensa_modifyreg8.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -45,19 +45,7 @@ #include #include -#include "up_arch.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ +#include "xtensa.h" /**************************************************************************** * Public Functions diff --git a/arch/xtensa/src/common/xtensa_puts.c b/arch/xtensa/src/common/xtensa_puts.c index 3eaa3078a4..d9449f7ffd 100644 --- a/arch/xtensa/src/common/xtensa_puts.c +++ b/arch/xtensa/src/common/xtensa_puts.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/xtensa/src/common/xtensa_puts.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -42,18 +42,6 @@ #include "xtensa.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/xtensa/src/common/xtensa_releasestack.c b/arch/xtensa/src/common/xtensa_releasestack.c index 40b5bd7571..94bb2d8cd8 100644 --- a/arch/xtensa/src/common/xtensa_releasestack.c +++ b/arch/xtensa/src/common/xtensa_releasestack.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/xtensa/src/common/xtensa_releasestack.c * - * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -47,14 +47,6 @@ #include "xtensa.h" -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/xtensa/src/common/xtensa_stackframe.c b/arch/xtensa/src/common/xtensa_stackframe.c index 6c1adc992b..19f61a1508 100644 --- a/arch/xtensa/src/common/xtensa_stackframe.c +++ b/arch/xtensa/src/common/xtensa_stackframe.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/xtensa/src/common/xtensa_stackframe.c * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without diff --git a/arch/xtensa/src/common/xtensa_udelay.c b/arch/xtensa/src/common/xtensa_udelay.c index f18be5b891..09d16d5d4d 100644 --- a/arch/xtensa/src/common/xtensa_udelay.c +++ b/arch/xtensa/src/common/xtensa_udelay.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/xtensa/src/common/xtensa_udelay.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -49,22 +49,6 @@ #define CONFIG_BOARD_LOOPSPER10USEC ((CONFIG_BOARD_LOOPSPERMSEC+50)/100) #define CONFIG_BOARD_LOOPSPERUSEC ((CONFIG_BOARD_LOOPSPERMSEC+500)/1000) -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/xtensa/src/common/xtensa_usestack.c b/arch/xtensa/src/common/xtensa_usestack.c index 83daf2729c..679deffb1f 100644 --- a/arch/xtensa/src/common/xtensa_usestack.c +++ b/arch/xtensa/src/common/xtensa_usestack.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/xtensa/src/common/xtensa_usestack.c * - * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without -- GitLab From 8c3c78f24a7c2fd0a66680bed282bc81af742aa9 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 16 Oct 2016 09:26:33 -0600 Subject: [PATCH 090/734] Xtensa: Fix register usage in up_strackframe --- arch/xtensa/Kconfig | 4 + arch/xtensa/include/irq.h | 1 + arch/xtensa/src/common/xtensa_context.S | 8 +- arch/xtensa/src/common/xtensa_corebits.h | 206 +++++++++++++++++++++ arch/xtensa/src/common/xtensa_stackframe.c | 13 +- arch/xtensa/src/esp32/Make.defs | 12 +- configs/esp32-core/nsh/defconfig | 3 +- 7 files changed, 225 insertions(+), 22 deletions(-) create mode 100644 arch/xtensa/src/common/xtensa_corebits.h diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 6befe7eff2..940235cbf2 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -30,6 +30,10 @@ config ARCH_FAMILY_LX6 Cadence® Tensilica® Xtensa® LX6 data plane processing unit (DPU). The LX6 is a configurable and extensible processor core. +config XTENSA_NCOPROCESSORS + int "Number of co-processors" + default 1 + config XTENSA_HAVE_LOOPS bool "Zero overhead loops" default n diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index 101cda03fb..0d7ef43807 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -94,6 +94,7 @@ #define REG_SAR (19) #define REG_EXCCAUSE (20) #define REG_EXCVADDR (21) + #define _REG_LOOPS_START (22) #if CONFIG_XTENSA_HAVE_LOOPS diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index 60a4d6edb3..fb156fbfb2 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -365,7 +365,7 @@ _xtensa_context_restore: * ****************************************************************************/ -#if XCHAL_CP_NUM > 0 +#if CONFIG_XTENSA_NCOPROCESSORS > 0 .global _xt_coproc_init .type _xt_coproc_init,@function .align 4 @@ -412,7 +412,7 @@ _xt_coproc_init: * ****************************************************************************/ -#if XCHAL_CP_NUM > 0 +#if CONFIG_XTENSA_NCOPROCESSORS > 0 .global _xt_coproc_release .type _xt_coproc_release,@function .align 4 @@ -465,7 +465,7 @@ _xt_coproc_release: * ****************************************************************************/ -#if XCHAL_CP_NUM > 0 +#if CONFIG_XTENSA_NCOPROCESSORS > 0 .extern _xt_coproc_sa_offset /* external reference */ .global _xt_coproc_savecs .type _xt_coproc_savecs,@function @@ -578,7 +578,7 @@ _xt_coproc_savecs: * ****************************************************************************/ -#if XCHAL_CP_NUM > 0 +#if CONFIG_XTENSA_NCOPROCESSORS > 0 .global _xt_coproc_restorecs .type _xt_coproc_restorecs,@function .align 4 diff --git a/arch/xtensa/src/common/xtensa_corebits.h b/arch/xtensa/src/common/xtensa_corebits.h new file mode 100644 index 0000000000..13da9dbca4 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_corebits.h @@ -0,0 +1,206 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_corebits.h + * Xtensa Special Register field positions, masks, values. + * NOTE: This file may be processor configuration dependent. + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Tensilica Inc. + * + * Copyright (c) 2005-2011 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + +#ifndef __ARCH_EXTENSA_SRC_COMMON_XTENSA_COREBITS_H +#define __ARCH_EXTENSA_SRC_COMMON_XTENSA_COREBITS_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* EXCCAUSE register fields: */ + +#define EXCCAUSE_EXCCAUSE_SHIFT 0 +#define EXCCAUSE_EXCCAUSE_MASK 0x3f + +/* EXCCAUSE register values: + * + * General Exception Causes + * (values of EXCCAUSE special register set by general exceptions, + * which vector to the user, kernel, or double-exception vectors). + */ + +#define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */ +#define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */ +#define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */ +# define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, deprecated, avoid) */ +#define EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */ +# define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, deprecated, avoid) */ +#define EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */ +# define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */ +#define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */ +#define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */ +#define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (not implemented) */ +#define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */ +#define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */ +/* Reserved 10-11 */ +#define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */ +#define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Store (RB-200x and later) */ +#define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */ +#define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 /* PIF Address Error on Load or Store (RB-200x and later) */ +#define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw refill also missed) */ +#define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries match) */ +#define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction Fetch */ +/* Reserved 19 *//* Size Restriction on IFetch (not implemented) */ +#define EXCCAUSE_INSTR_PROHIBITED 20 /* Cache Attribute does not allow Instruction Fetch */ +/* Reserved 21..23 */ +#define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw refill also missed) */ +#define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries match) */ +#define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or Store */ +/* Reserved 27 *//* Size Restriction on Load/Store (not implemented) */ +#define EXCCAUSE_LOAD_PROHIBITED 28 /* Cache Attribute does not allow Load */ +#define EXCCAUSE_STORE_PROHIBITED 29 /* Cache Attribute does not allow Store */ +/* Reserved 30-31 */ +#define EXCCAUSE_CP_DISABLED(n) (32+(n)) /* Access to Coprocessor 'n' when disabled */ +# define EXCCAUSE_CP0_DISABLED 32 /* Access to Coprocessor 0 when disabled */ +# define EXCCAUSE_CP1_DISABLED 33 /* Access to Coprocessor 1 when disabled */ +# define EXCCAUSE_CP2_DISABLED 34 /* Access to Coprocessor 2 when disabled */ +# define EXCCAUSE_CP3_DISABLED 35 /* Access to Coprocessor 3 when disabled */ +# define EXCCAUSE_CP4_DISABLED 36 /* Access to Coprocessor 4 when disabled */ +# define EXCCAUSE_CP5_DISABLED 37 /* Access to Coprocessor 5 when disabled */ +# define EXCCAUSE_CP6_DISABLED 38 /* Access to Coprocessor 6 when disabled */ +# define EXCCAUSE_CP7_DISABLED 39 /* Access to Coprocessor 7 when disabled */ +/* Reserved 40..63 */ + +/* PS register fields: */ + +#define PS_WOE_SHIFT 18 +#define PS_WOE_MASK 0x00040000 +#define PS_WOE PS_WOE_MASK + +#define PS_CALLINC_SHIFT 16 +#define PS_CALLINC_MASK 0x00030000 +#define PS_CALLINC(n) (((n)&3)<adj_stack_ptr = (FAR void *)topaddr; tcb->adj_stack_size -= frame_size; - /* Reset the initial stack pointer */ + /* Reset the initial stack pointer (A1) */ - tcb->xcp.regs[REG_SP] = (uint32_t)tcb->adj_stack_ptr; + tcb->xcp.regs[REG_A1] = (uint32_t)tcb->adj_stack_ptr; /* And return the pointer to the allocated region */ return (FAR void *)(topaddr + sizeof(uint32_t)); } - diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 1312fd1cf6..d6cd7667f9 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -40,12 +40,12 @@ HEAD_ASRC = # Common XTENSA files (arch/xtensa/src/common) CMN_ASRCS = xtensa_irq.S -CMN_CSRCS = xtensa_allocateheap.c xtensa_createstack.c xtensa_exit.c -CMN_CSRCS += xtensa_idle.c xtensa_initialize.c xtensa_interruptcontext.c -CMN_CSRCS += xtensa_lowputs.c xtensa_mdelay.c xtensa_modifyreg8.c -CMN_CSRCS += xtensa_modifyreg16.c xtensa_modifyreg32.c xtensa_puts.c -CMN_CSRCS += xtensa_releasestack.c xtensa_stackframe.c xtensa_udelay.c -CMN_CSRCS += xtensa_usestack.c +CMN_CSRCS = xtensa_allocateheap.c xtensa_copystate.c xtensa_createstack.c +CMN_CSRCS += xtensa_exit.c xtensa_idle.c xtensa_initialize.c +CMN_CSRCS += xtensa_interruptcontext.c xtensa_lowputs.c xtensa_mdelay.c +CMN_CSRCS += xtensa_modifyreg8.c xtensa_modifyreg16.c xtensa_modifyreg32.c +CMN_CSRCS += xtensa_puts.c xtensa_releasestack.c xtensa_stackframe.c +CMN_CSRCS += xtensa_udelay.c xtensa_usestack.c # Configuration-dependent common XTENSA files diff --git a/configs/esp32-core/nsh/defconfig b/configs/esp32-core/nsh/defconfig index 082df28cc6..14d63fcdc9 100644 --- a/configs/esp32-core/nsh/defconfig +++ b/configs/esp32-core/nsh/defconfig @@ -73,6 +73,7 @@ CONFIG_ARCH="xtensa" CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_FAMILY_LX6=y +CONFIG_XTENSA_NCOPROCESSORS=1 # CONFIG_XTENSA_HAVE_LOOPS is not set CONFIG_XTENSA_HAVE_INTERRUPTS=y # CONFIG_XTENSA_USE_SWPRI is not set @@ -555,10 +556,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set -- GitLab From 201a32cf8cfa0302a2843f36111f6a90d0faad19 Mon Sep 17 00:00:00 2001 From: Ken Pettit Date: Sun, 16 Oct 2016 09:47:07 -0600 Subject: [PATCH 091/734] Add support for the RISC-V architecture and configs/nr5m100-nexys4 board. I will be making the FPGA code for this available soon (within a week I would say). The board support on this is pretty thin, but it seems like maybe a good idea to get the base RISC-V stuff in since there are people interested in it. --- arch/Kconfig | 10 + arch/README.txt | 9 + arch/risc-v/Kconfig | 55 ++ arch/risc-v/include/arch.h | 119 +++ arch/risc-v/include/irq.h | 79 ++ arch/risc-v/include/limits.h | 90 ++ arch/risc-v/include/nr5m100/chip.h | 61 ++ arch/risc-v/include/nr5m100/irq.h | 73 ++ arch/risc-v/include/nr5m100/nr5m1xx_irq.h | 71 ++ arch/risc-v/include/rv32im/csr.h | 100 ++ arch/risc-v/include/rv32im/irq.h | 347 +++++++ arch/risc-v/include/rv32im/syscall.h | 208 ++++ arch/risc-v/include/stdarg.h | 59 ++ arch/risc-v/include/syscall.h | 91 ++ arch/risc-v/include/types.h | 96 ++ arch/risc-v/src/Makefile | 232 +++++ arch/risc-v/src/common/up_allocateheap.c | 88 ++ arch/risc-v/src/common/up_arch.h | 70 ++ arch/risc-v/src/common/up_createstack.c | 214 +++++ arch/risc-v/src/common/up_exit.c | 188 ++++ arch/risc-v/src/common/up_idle.c | 95 ++ arch/risc-v/src/common/up_initialize.c | 203 ++++ arch/risc-v/src/common/up_internal.h | 160 ++++ arch/risc-v/src/common/up_interruptcontext.c | 70 ++ arch/risc-v/src/common/up_releasestack.c | 122 +++ arch/risc-v/src/common/up_stackframe.c | 143 +++ arch/risc-v/src/common/up_usestack.c | 152 +++ arch/risc-v/src/nr5m100/Kconfig | 121 +++ arch/risc-v/src/nr5m100/Make.defs | 74 ++ arch/risc-v/src/nr5m100/chip.h | 67 ++ arch/risc-v/src/nr5m100/chip/nr5m1xx_epic.h | 41 + .../src/nr5m100/chip/nr5m1xx_memorymap.h | 57 ++ arch/risc-v/src/nr5m100/chip/nr5m1xx_timer.h | 190 ++++ arch/risc-v/src/nr5m100/chip/nr5m1xx_uart.h | 75 ++ arch/risc-v/src/nr5m100/nr5.h | 68 ++ arch/risc-v/src/nr5m100/nr5_allocateheap.c | 63 ++ arch/risc-v/src/nr5m100/nr5_arch.c | 43 + arch/risc-v/src/nr5m100/nr5_config.h | 97 ++ arch/risc-v/src/nr5m100/nr5_csr.S | 289 ++++++ arch/risc-v/src/nr5m100/nr5_csr.h | 94 ++ arch/risc-v/src/nr5m100/nr5_custom_ops.h | 61 ++ arch/risc-v/src/nr5m100/nr5_head.S | 611 ++++++++++++ arch/risc-v/src/nr5m100/nr5_init.c | 76 ++ arch/risc-v/src/nr5m100/nr5_irq.c | 320 +++++++ arch/risc-v/src/nr5m100/nr5_irq_dispatch.c | 155 +++ arch/risc-v/src/nr5m100/nr5_lowputc.c | 181 ++++ arch/risc-v/src/nr5m100/nr5_lowputc.h | 79 ++ arch/risc-v/src/nr5m100/nr5_memorymap.h | 43 + arch/risc-v/src/nr5m100/nr5_serial.c | 888 ++++++++++++++++++ arch/risc-v/src/nr5m100/nr5_timer.c | 512 ++++++++++ arch/risc-v/src/nr5m100/nr5_timer.h | 168 ++++ arch/risc-v/src/nr5m100/nr5_timerisr.c | 159 ++++ arch/risc-v/src/nr5m100/nr5_uart.c | 254 +++++ arch/risc-v/src/nr5m100/nr5_uart.h | 49 + arch/risc-v/src/nr5m100/nr5_vectors.S | 101 ++ .../risc-v/src/nr5m100/up_schedulesigaction.c | 213 +++++ arch/risc-v/src/rv32im/Kconfig | 51 + arch/risc-v/src/rv32im/Toolchain.defs | 104 ++ arch/risc-v/src/rv32im/up_assert.c | 161 ++++ arch/risc-v/src/rv32im/up_blocktask.c | 179 ++++ arch/risc-v/src/rv32im/up_copystate.c | 86 ++ arch/risc-v/src/rv32im/up_doirq.c | 148 +++ arch/risc-v/src/rv32im/up_dumpstate.c | 231 +++++ arch/risc-v/src/rv32im/up_initialstate.c | 133 +++ arch/risc-v/src/rv32im/up_releasepending.c | 148 +++ arch/risc-v/src/rv32im/up_reprioritizertr.c | 203 ++++ arch/risc-v/src/rv32im/up_sigdeliver.c | 155 +++ arch/risc-v/src/rv32im/up_swint.c | 285 ++++++ arch/risc-v/src/rv32im/up_syscall.S | 112 +++ arch/risc-v/src/rv32im/up_unblocktask.c | 163 ++++ arch/risc-v/src/rv32im/up_vfork.c | 262 ++++++ arch/risc-v/src/rv32im/up_vfork.h | 132 +++ configs/Kconfig | 9 + configs/README.txt | 3 + configs/nr5m100-nexys4/Kconfig | 9 + configs/nr5m100-nexys4/README.txt | 251 +++++ configs/nr5m100-nexys4/include/board.h | 178 ++++ configs/nr5m100-nexys4/nsh/Make.defs | 114 +++ configs/nr5m100-nexys4/nsh/defconfig | 800 ++++++++++++++++ configs/nr5m100-nexys4/nsh/setenv.sh | 45 + configs/nr5m100-nexys4/scripts/ld.script | 305 ++++++ configs/nr5m100-nexys4/scripts/nr5m1xx.cfg | 64 ++ configs/nr5m100-nexys4/scripts/openocd.cfg | 61 ++ configs/nr5m100-nexys4/src/Makefile | 90 ++ configs/nr5m100-nexys4/src/nr5_appinit.c | 86 ++ configs/nr5m100-nexys4/src/nr5_autoleds.c | 71 ++ configs/nr5m100-nexys4/src/nr5_boot.c | 70 ++ 87 files changed, 13063 insertions(+) create mode 100644 arch/risc-v/Kconfig create mode 100644 arch/risc-v/include/arch.h create mode 100644 arch/risc-v/include/irq.h create mode 100644 arch/risc-v/include/limits.h create mode 100644 arch/risc-v/include/nr5m100/chip.h create mode 100644 arch/risc-v/include/nr5m100/irq.h create mode 100644 arch/risc-v/include/nr5m100/nr5m1xx_irq.h create mode 100644 arch/risc-v/include/rv32im/csr.h create mode 100644 arch/risc-v/include/rv32im/irq.h create mode 100644 arch/risc-v/include/rv32im/syscall.h create mode 100644 arch/risc-v/include/stdarg.h create mode 100644 arch/risc-v/include/syscall.h create mode 100644 arch/risc-v/include/types.h create mode 100644 arch/risc-v/src/Makefile create mode 100644 arch/risc-v/src/common/up_allocateheap.c create mode 100644 arch/risc-v/src/common/up_arch.h create mode 100644 arch/risc-v/src/common/up_createstack.c create mode 100644 arch/risc-v/src/common/up_exit.c create mode 100644 arch/risc-v/src/common/up_idle.c create mode 100644 arch/risc-v/src/common/up_initialize.c create mode 100644 arch/risc-v/src/common/up_internal.h create mode 100644 arch/risc-v/src/common/up_interruptcontext.c create mode 100644 arch/risc-v/src/common/up_releasestack.c create mode 100644 arch/risc-v/src/common/up_stackframe.c create mode 100644 arch/risc-v/src/common/up_usestack.c create mode 100644 arch/risc-v/src/nr5m100/Kconfig create mode 100644 arch/risc-v/src/nr5m100/Make.defs create mode 100644 arch/risc-v/src/nr5m100/chip.h create mode 100644 arch/risc-v/src/nr5m100/chip/nr5m1xx_epic.h create mode 100644 arch/risc-v/src/nr5m100/chip/nr5m1xx_memorymap.h create mode 100644 arch/risc-v/src/nr5m100/chip/nr5m1xx_timer.h create mode 100644 arch/risc-v/src/nr5m100/chip/nr5m1xx_uart.h create mode 100644 arch/risc-v/src/nr5m100/nr5.h create mode 100644 arch/risc-v/src/nr5m100/nr5_allocateheap.c create mode 100644 arch/risc-v/src/nr5m100/nr5_arch.c create mode 100644 arch/risc-v/src/nr5m100/nr5_config.h create mode 100644 arch/risc-v/src/nr5m100/nr5_csr.S create mode 100644 arch/risc-v/src/nr5m100/nr5_csr.h create mode 100644 arch/risc-v/src/nr5m100/nr5_custom_ops.h create mode 100644 arch/risc-v/src/nr5m100/nr5_head.S create mode 100644 arch/risc-v/src/nr5m100/nr5_init.c create mode 100644 arch/risc-v/src/nr5m100/nr5_irq.c create mode 100644 arch/risc-v/src/nr5m100/nr5_irq_dispatch.c create mode 100644 arch/risc-v/src/nr5m100/nr5_lowputc.c create mode 100644 arch/risc-v/src/nr5m100/nr5_lowputc.h create mode 100644 arch/risc-v/src/nr5m100/nr5_memorymap.h create mode 100644 arch/risc-v/src/nr5m100/nr5_serial.c create mode 100644 arch/risc-v/src/nr5m100/nr5_timer.c create mode 100644 arch/risc-v/src/nr5m100/nr5_timer.h create mode 100644 arch/risc-v/src/nr5m100/nr5_timerisr.c create mode 100644 arch/risc-v/src/nr5m100/nr5_uart.c create mode 100644 arch/risc-v/src/nr5m100/nr5_uart.h create mode 100644 arch/risc-v/src/nr5m100/nr5_vectors.S create mode 100644 arch/risc-v/src/nr5m100/up_schedulesigaction.c create mode 100644 arch/risc-v/src/rv32im/Kconfig create mode 100644 arch/risc-v/src/rv32im/Toolchain.defs create mode 100644 arch/risc-v/src/rv32im/up_assert.c create mode 100644 arch/risc-v/src/rv32im/up_blocktask.c create mode 100644 arch/risc-v/src/rv32im/up_copystate.c create mode 100644 arch/risc-v/src/rv32im/up_doirq.c create mode 100644 arch/risc-v/src/rv32im/up_dumpstate.c create mode 100644 arch/risc-v/src/rv32im/up_initialstate.c create mode 100644 arch/risc-v/src/rv32im/up_releasepending.c create mode 100644 arch/risc-v/src/rv32im/up_reprioritizertr.c create mode 100644 arch/risc-v/src/rv32im/up_sigdeliver.c create mode 100644 arch/risc-v/src/rv32im/up_swint.c create mode 100644 arch/risc-v/src/rv32im/up_syscall.S create mode 100644 arch/risc-v/src/rv32im/up_unblocktask.c create mode 100644 arch/risc-v/src/rv32im/up_vfork.c create mode 100644 arch/risc-v/src/rv32im/up_vfork.h create mode 100644 configs/nr5m100-nexys4/Kconfig create mode 100644 configs/nr5m100-nexys4/README.txt create mode 100644 configs/nr5m100-nexys4/include/board.h create mode 100644 configs/nr5m100-nexys4/nsh/Make.defs create mode 100644 configs/nr5m100-nexys4/nsh/defconfig create mode 100644 configs/nr5m100-nexys4/nsh/setenv.sh create mode 100644 configs/nr5m100-nexys4/scripts/ld.script create mode 100644 configs/nr5m100-nexys4/scripts/nr5m1xx.cfg create mode 100644 configs/nr5m100-nexys4/scripts/openocd.cfg create mode 100644 configs/nr5m100-nexys4/src/Makefile create mode 100644 configs/nr5m100-nexys4/src/nr5_appinit.c create mode 100644 configs/nr5m100-nexys4/src/nr5_autoleds.c create mode 100644 configs/nr5m100-nexys4/src/nr5_boot.c diff --git a/arch/Kconfig b/arch/Kconfig index 319419bb2d..a3c43d12d8 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -52,6 +52,13 @@ config ARCH_RENESAS ---help--- Renesas architectures (SH and M16C). +config ARCH_RISCV + bool "RISC-V" + select ARCH_HAVE_INTERRUPTSTACK + select ARCH_HAVE_CUSTOMOPT + ---help--- + RISC-V 32 and 64-bit RV32 / RV64 architectures. + config ARCH_SIM bool "Simulation" select ARCH_HAVE_MULTICPU @@ -89,6 +96,7 @@ config ARCH default "mips" if ARCH_MIPS default "rgmp" if ARCH_RGMP default "renesas" if ARCH_RENESAS + default "risc-v" if ARCH_RISCV default "sim" if ARCH_SIM default "x86" if ARCH_X86 default "z16" if ARCH_Z16 @@ -100,6 +108,7 @@ source arch/hc/Kconfig source arch/mips/Kconfig source arch/rgmp/Kconfig source arch/renesas/Kconfig +source arch/risc-v/Kconfig source arch/sim/Kconfig source arch/x86/Kconfig source arch/z16/Kconfig @@ -540,6 +549,7 @@ config ARCH_USBDUMP config ENDIAN_BIG bool "Big Endian Architecture" default n + depends on !ARCH_RISCV ---help--- Select if architecture operates using big-endian byte ordering. diff --git a/arch/README.txt b/arch/README.txt index bd49fb31a7..6067669976 100644 --- a/arch/README.txt +++ b/arch/README.txt @@ -233,6 +233,15 @@ arch/rgmp See http://rgmp.sourceforge.net/wiki/index.php/Main_Page for further information about RGMP. +arch/risc-v + This directory is dedicated to ports to the RISC-V family. + + Architecture Support + arch/risc-v/include/rv32im + + MCU support + arch/risc-v/include/nr5m100 + arch/x86 - Intel x86 architectures This directory holds related, 32- and 64-bit architectures from Intel. At present, this includes the following subdirectories: diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig new file mode 100644 index 0000000000..65ed34459f --- /dev/null +++ b/arch/risc-v/Kconfig @@ -0,0 +1,55 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_RISCV +comment "RISC-V Options" + +choice + prompt "RISC-V chip selection" + default ARCH_CHIP_NR5M100 + +config ARCH_CHIP_NR5M100 + bool "NEXT NanoRisc5 M100" + select ARCH_RV32IM + default ARCH_CHIP_NR5 + ---help--- + NEXT RISC-V NR5Mxx architectures (RISC-V RV32IM cores). + +endchoice + +config ARCH_RV32I + bool + default n + +config ARCH_RV32IM + bool + default n + +config ARCH_FAMILY + string + default "rv32im" if ARCH_RM32IM + +config ARCH_CHIP + string + default "nr5m100" if ARCH_CHIP_NR5M100 + +config NR5_MPU + bool "MPU support" + default n + depends on ARCH_HAVE_MPU + select ARCH_USE_MPU + ---help--- + Build in support for the RISC-V Memory Protection Unit (MPU). + Check your chip specifications first; not all RISC-V architectures + support the MPU. + +if ARCH_RV32IM +source arch/risc-v/src/rv32im/Kconfig +endif +if ARCH_CHIP_NR5M100 +source arch/risc-v/src/nr5m100/Kconfig +endif + +endif diff --git a/arch/risc-v/include/arch.h b/arch/risc-v/include/arch.h new file mode 100644 index 0000000000..e0e60b4e1b --- /dev/null +++ b/arch/risc-v/include/arch.h @@ -0,0 +1,119 @@ +/**************************************************************************** + * arch/risc-v/include/arch.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, + * only indirectly through nuttx/arch.h + */ + +#ifndef __ARCH_RISCV_INCLUDE_ARCH_H +#define __ARCH_RISCV_INCLUDE_ARCH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +#ifdef CONFIG_ARCH_RV32IM +# include "rv32im/csr.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Macros to get the core and vendor ID, HART, arch and ISA codes, etc. + */ +#ifdef CONFIG_RV32IM_SYSTEM_CSRRS_SUPPORT + +uint32_t up_getmisa(void); +uint32_t up_getarchid(void); +uint32_t up_getimpid(void); +uint32_t up_getvendorid(void); +uint32_t up_gethartid(void); + +#else + +#define up_getmisa() 0 +#define up_getarchid() 0 +#define up_getimpid() 0 +#define up_getvendorid() 0 +#define up_gethartid() 0 + +#endif + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef CONFIG_RV32IM_HW_MULDIV +uint32_t up_hard_mul(uint32_t a, uint32_t b); +uint32_t up_hard_mulh(uint32_t a, uint32_t b); +uint32_t up_hard_mulhsu(uint32_t a, uint32_t b); +uint32_t up_hard_mulhu(uint32_t a, uint32_t b); +uint32_t up_hard_div(uint32_t a, uint32_t b); +uint32_t up_hard_rem(uint32_t a, uint32_t b); +uint32_t up_hard_divu(uint32_t a, uint32_t b); +uint32_t up_hard_remu(uint32_t a, uint32_t b); +uint32_t time_hard_mul(uint32_t a, uint32_t b, uint32_t *t); +#endif + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ARCH_RISCV_INCLUDE_ARCH_H */ + diff --git a/arch/risc-v/include/irq.h b/arch/risc-v/include/irq.h new file mode 100644 index 0000000000..7de60dc316 --- /dev/null +++ b/arch/risc-v/include/irq.h @@ -0,0 +1,79 @@ +/**************************************************************************** + * arch/risc-v/include/irq.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_RISCV_INCLUDE_IRQ_H +#define __ARCH_RISCV_INCLUDE_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific IRQ definitions (including IRQ numbers) */ + +#include +#include +#include + +/* Include RISC-V architecture-specific IRQ definitions */ + +#if defined(CONFIG_ARCH_RV32IM) || defined(CONFIG_ARCH_RV32I) +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +typedef uint32_t irqstate_t; + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +irqstate_t irqsave(void); + +void irqrestore(irqstate_t); + +#endif /* __ARCH_RISCV_INCLUDE_IRQ_H */ + diff --git a/arch/risc-v/include/limits.h b/arch/risc-v/include/limits.h new file mode 100644 index 0000000000..6be24b9b41 --- /dev/null +++ b/arch/risc-v/include/limits.h @@ -0,0 +1,90 @@ +/**************************************************************************** + * arch/risc-v/include/limits.h + * + * Copyright (C) 2007-2009, 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_LIMITS_H +#define __ARCH_RISCV_INCLUDE_LIMITS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CHAR_BIT 8 +#define SCHAR_MIN (-SCHAR_MAX - 1) +#define SCHAR_MAX 127 +#define UCHAR_MAX 255 + +/* These could be different on machines where char is unsigned */ + +#ifdef __CHAR_UNSIGNED__ +#define CHAR_MIN 0 +#define CHAR_MAX UCHAR_MAX +#else +#define CHAR_MIN SCHAR_MIN +#define CHAR_MAX SCHAR_MAX +#endif + +#define SHRT_MIN (-SHRT_MAX - 1) +#define SHRT_MAX 32767 +#define USHRT_MAX 65535U + +#define INT_MIN (-INT_MAX - 1) +#define INT_MAX 2147483647 +#define UINT_MAX 4294967295U + +/* These change on 32-bit and 64-bit platforms */ + +#if defined(CONFIG_ARCH_32IM) || defined(CONFIG_ARCH_32I) + +#define LONG_MIN (-LONG_MAX - 1) +#define LONG_MAX 2147483647L +#define ULONG_MAX 4294967295UL + +#define LLONG_MIN (-LLONG_MAX - 1) +#define LLONG_MAX 9223372036854775807LL +#define ULLONG_MAX 18446744073709551615ULL + +/* A pointer is 4 bytes */ + +#define PTR_MIN (-PTR_MAX - 1) +#define PTR_MAX 2147483647 +#define UPTR_MAX 4294967295U + +#endif /* defined(CONFIG_ARCH_32IM) || defined(CONFIG_ARCH_32I) */ + +#endif /* __ARCH_RISCV_INCLUDE_LIMITS_H */ diff --git a/arch/risc-v/include/nr5m100/chip.h b/arch/risc-v/include/nr5m100/chip.h new file mode 100644 index 0000000000..79d681f6e2 --- /dev/null +++ b/arch/risc-v/include/nr5m100/chip.h @@ -0,0 +1,61 @@ +/**************************************************************************** + * arch/risc-v/include/nr5m100/chip.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_RISCV_INCLUDE_NR5M100_CHIP_H +#define __ARCH_RISCV_INCLUDE_NR5M100_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_RISCV_INCLUDE_NR5M100_CHIP_H */ + diff --git a/arch/risc-v/include/nr5m100/irq.h b/arch/risc-v/include/nr5m100/irq.h new file mode 100644 index 0000000000..d8d1806d1e --- /dev/null +++ b/arch/risc-v/include/nr5m100/irq.h @@ -0,0 +1,73 @@ +/**************************************************************************** + * arch/risc-v/include/nr5m100/irq.h + * include/arch/nr5m100/irq.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_NR5M100_IRQ_H +#define __ARCH_RISCV_INCLUDE_NR5M100_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if defined(CONFIG_NR5_NR5M1XX) +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NR5_IRQ_TRAP 0 + +#define EPIC_STATUS_PRI_MASK 0x001C +#define EPIC_STATUS_INT_PRI_MASK 0x01C0 +#define EPIC_STATUS_INT_PRI1 0x0040 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +void up_enable_irq(int irq); + +irqstate_t up_irq_save(void); +void up_irq_restore(irqstate_t irqstate); + +#endif /* __ARCH_RISCV_INCLUDE_NR5M100_IRQ_H */ + diff --git a/arch/risc-v/include/nr5m100/nr5m1xx_irq.h b/arch/risc-v/include/nr5m100/nr5m1xx_irq.h new file mode 100644 index 0000000000..ceffbb2985 --- /dev/null +++ b/arch/risc-v/include/nr5m100/nr5m1xx_irq.h @@ -0,0 +1,71 @@ +/**************************************************************************** + * arch/risc-v/include/nr5m100/nr5m1xx_irq.h + * include/arch/nr5m100/nr5m1xx_irq.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_NR5M100_NR5M1XX_IRQ_H +#define __ARCH_RISCV_INCLUDE_NR5M100_NR5M1XX_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NR5_IRQ_SYSTICK 1 +#define NR5_IRQ_TIMER 2 +#define NR5_IRQ_SOFTWARE 3 +#define NR5_IRQ_DEBUG 4 +#define NR5_IRQ_UART1_RX 5 +#define NR5_IRQ_UART1_TX 6 +#define NR5_IRQ_TIMER1_A 7 +#define NR5_IRQ_TIMER1_B 8 +#define NR5_IRQ_TIMER2_A 9 +#define NR5_IRQ_TIMER2_B 10 + +#define NR_IRQS 11 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_RISCV_INCLUDE_NR5M100_NR5M1XX_IRQ_H */ + diff --git a/arch/risc-v/include/rv32im/csr.h b/arch/risc-v/include/rv32im/csr.h new file mode 100644 index 0000000000..3aac4173e6 --- /dev/null +++ b/arch/risc-v/include/rv32im/csr.h @@ -0,0 +1,100 @@ +/**************************************************************************** + * arch/risc-v/include/rv32im/csr.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_RISCV_INCLUDE_RV32IM_CSR_H +#define __ARCH_RISCV_INCLUDE_RV32IM_CSR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Machine Information Registers */ + +#define CSR_MISA 0xF10 +#define CSR_MVENDORID 0xF11 +#define CSR_MARCHID 0xF12 +#define CSR_MIMPID 0xF13 +#define CSR_MHARTID 0xF14 + +/* Machine Trap Registers */ + +#define CSR_MSTATUS 0x300 +#define CSR_MTDELEG 0x302 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MIVEC 0x30f + +/* Machine Trap Handling */ + +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MBADADDR 0x343 +#define CSR_MIP 0x344 + +/* Machine Timers and Counters */ + +#define CSR_CYCLE 0xF00 +#define CSR_TIME 0xF01 +#define CSR_INSTRET 0xF02 +#define CSR_CYCLEH 0xF80 +#define CSR_TIMEH 0xF81 +#define CSR_INSTRETH 0xF82 + +/* Debug interface CSRs */ + +#define CSR_DCSR 0x7B0 +#define CSR_DPC 0x7B1 +#define CSR_DSCRATCH 0x7B2 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_RISCV_INCLUDE_RV32IM_CSR_H */ + diff --git a/arch/risc-v/include/rv32im/irq.h b/arch/risc-v/include/rv32im/irq.h new file mode 100644 index 0000000000..0a9010703f --- /dev/null +++ b/arch/risc-v/include/rv32im/irq.h @@ -0,0 +1,347 @@ +/**************************************************************************** + * arch/risc-v/include/rv32im/irq.h + * + * Copyright (C) 2011, 2013, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_RISCV_INCLUDE_RV32IM_IRQ_H +#define __ARCH_RISCV_INCLUDE_RV32IM_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +/* If this is a kernel build, how many nested system calls should we support? */ + +#ifndef CONFIG_SYS_NNEST +# define CONFIG_SYS_NNEST 2 +#endif + +/* Processor PC */ +#define REG_EPC_NDX 0 + +/* General pupose registers */ +/* $0: Zero register does not need to be saved */ +/* $1: ra (return address) */ + +#define REG_X1_NDX 1 + +/* $2: Stack POinter + * $3: Global Pointer + * $4: Thread Pointer + */ + +#define REG_X2_NDX 2 +#define REG_X3_NDX 3 +#define REG_X4_NDX 4 + +/* $5-$7 = t0-t3: Temporary registers */ + +#define REG_X5_NDX 5 +#define REG_X6_NDX 6 +#define REG_X7_NDX 7 + +/* $8: s0 / fp Frame pointer */ + +#define REG_X8_NDX 8 + +/* $89 s1 Saved register */ + +#define REG_X9_NDX 9 + +/* $10-$17 = a0-a7: Argument registers */ + +#define REG_X10_NDX 10 +#define REG_X11_NDX 11 +#define REG_X12_NDX 12 +#define REG_X13_NDX 13 +#define REG_X14_NDX 14 +#define REG_X15_NDX 15 +#define REG_X16_NDX 16 +#define REG_X17_NDX 17 + +/* $18-$27 = s2-s11: Saved registers */ + +#define REG_X18_NDX 18 +#define REG_X19_NDX 19 +#define REG_X20_NDX 20 +#define REG_X21_NDX 21 +#define REG_X22_NDX 22 +#define REG_X23_NDX 23 +#define REG_X24_NDX 24 +#define REG_X25_NDX 25 +#define REG_X26_NDX 26 +#define REG_X27_NDX 27 + +/* $28-31 = t3-t6: Temporary (Volatile) registers */ + +#define REG_X28_NDX 28 +#define REG_X29_NDX 29 +#define REG_X30_NDX 30 +#define REG_X31_NDX 31 + +/* Interrupt Context register */ + +#define REG_INT_CTX_NDX 32 + +#define XCPTCONTEXT_REGS 33 +#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS) + +/* In assembly language, values have to be referenced as byte address + * offsets. But in C, it is more convenient to reference registers as + * register save table offsets. + */ + +#ifdef __ASSEMBLY__ +# define REG_EPC (4*REG_EPC_NDX) +# define REG_X1 (4*REG_X1_NDX) +# define REG_X2 (4*REG_X2_NDX) +# define REG_X3 (4*REG_X3_NDX) +# define REG_X4 (4*REG_X4_NDX) +# define REG_X5 (4*REG_X5_NDX) +# define REG_X6 (4*REG_X6_NDX) +# define REG_X7 (4*REG_X7_NDX) +# define REG_X8 (4*REG_X8_NDX) +# define REG_X9 (4*REG_X9_NDX) +# define REG_X10 (4*REG_X10_NDX) +# define REG_X11 (4*REG_X11_NDX) +# define REG_X12 (4*REG_X12_NDX) +# define REG_X13 (4*REG_X13_NDX) +# define REG_X14 (4*REG_X14_NDX) +# define REG_X15 (4*REG_X15_NDX) +# define REG_X16 (4*REG_X16_NDX) +# define REG_X17 (4*REG_X17_NDX) +# define REG_X18 (4*REG_X18_NDX) +# define REG_X19 (4*REG_X19_NDX) +# define REG_X20 (4*REG_X20_NDX) +# define REG_X21 (4*REG_X21_NDX) +# define REG_X22 (4*REG_X22_NDX) +# define REG_X23 (4*REG_X23_NDX) +# define REG_X24 (4*REG_X24_NDX) +# define REG_X25 (4*REG_X25_NDX) +# define REG_X26 (4*REG_X26_NDX) +# define REG_X27 (4*REG_X27_NDX) +# define REG_X28 (4*REG_X28_NDX) +# define REG_X29 (4*REG_X29_NDX) +# define REG_X30 (4*REG_X30_NDX) +# define REG_X31 (4*REG_X31_NDX) +# define REG_INT_CTX (4*REG_INT_CTX_NDX) +#else +# define REG_EPC REG_EPC_NDX +# define REG_X1 REG_X1_NDX +# define REG_X2 REG_X2_NDX +# define REG_X3 REG_X3_NDX +# define REG_X4 REG_X4_NDX +# define REG_X5 REG_X5_NDX +# define REG_X6 REG_X6_NDX +# define REG_X7 REG_X7_NDX +# define REG_X8 REG_X8_NDX +# define REG_X9 REG_X9_NDX +# define REG_X10 REG_X10_NDX +# define REG_X11 REG_X11_NDX +# define REG_X12 REG_X12_NDX +# define REG_X13 REG_X13_NDX +# define REG_X14 REG_X14_NDX +# define REG_X15 REG_X15_NDX +# define REG_X16 REG_X16_NDX +# define REG_X17 REG_X17_NDX +# define REG_X18 REG_X18_NDX +# define REG_X19 REG_X19_NDX +# define REG_X20 REG_X20_NDX +# define REG_X21 REG_X21_NDX +# define REG_X22 REG_X22_NDX +# define REG_X23 REG_X23_NDX +# define REG_X24 REG_X24_NDX +# define REG_X25 REG_X25_NDX +# define REG_X26 REG_X26_NDX +# define REG_X27 REG_X27_NDX +# define REG_X28 REG_X28_NDX +# define REG_X29 REG_X29_NDX +# define REG_X30 REG_X30_NDX +# define REG_X31 REG_X31_NDX +# define REG_INT_CTX REG_INT_CTX_NDX +#endif + +/* Now define more user friendly alternative name that can be used either + * in assembly or C contexts. + */ + +/* $1 = ra: Return address */ + +#define REG_RA REG_X1 + +/* $2 = sp: The value of the stack pointer on return from the exception */ + +#define REG_SP REG_X2 + +/* $3 = gp: Only needs to be saved under conditions where there are + * multiple, per-thread values for the GP. + */ + +#define REG_GP REG_X3 + +/* $4 = tp: Thread Pointer */ + +#define REG_TP REG_X4 + +/* $5-$7 = t0-t2: Caller saved temporary registers */ + +#define REG_T0 REG_X5 +#define REG_T1 REG_X6 +#define REG_T2 REG_X7 + +/* $8 = either s0 or fp: Depends if a frame pointer is used or not */ + +#define REG_S0 REG_X8 +#define REG_FP REG_X8 + +/* $9 = s1: Caller saved register */ + +#define REG_S1 REG_X9 + +/* $10-$17 = a0-a7: Argument registers */ + +#define REG_A0 REG_X10 +#define REG_A1 REG_X11 +#define REG_A2 REG_X12 +#define REG_A3 REG_X13 +#define REG_A4 REG_X14 +#define REG_A5 REG_X15 +#define REG_A6 REG_X16 +#define REG_A7 REG_X17 + +/* $18-$27 = s2-s11: Callee saved registers */ + +#define REG_S2 REG_X18 +#define REG_S3 REG_X19 +#define REG_S4 REG_X20 +#define REG_S5 REG_X21 +#define REG_S6 REG_X22 +#define REG_S7 REG_X23 +#define REG_S8 REG_X24 +#define REG_S9 REG_X25 +#define REG_S10 REG_X26 +#define REG_S11 REG_X27 + +/* $28-$31 = t3-t6: Caller saved temporary registers */ + +#define REG_T3 REG_X28 +#define REG_T4 REG_X29 +#define REG_T5 REG_X30 +#define REG_T6 REG_X31 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* This structure represents the return state from a system call */ + +#ifdef CONFIG_BUILD_KERNEL +struct xcpt_syscall_s +{ + uint32_t sysreturn; /* The return PC */ +}; +#endif + +/* The following structure is included in the TCB and defines the complete + * state of the thread. + */ + +struct xcptcontext +{ +#ifndef CONFIG_DISABLE_SIGNALS + /* The following function pointer is non-NULL if there are pending signals + * to be processed. + */ + + void *sigdeliver; /* Actual type is sig_deliver_t */ + + /* These additional register save locations are used to implement the + * signal delivery trampoline. + */ + + uint32_t saved_epc; /* Trampoline PC */ + uint32_t saved_int_ctx; /* Interrupt context with interrupts disabled. */ + +# ifdef CONFIG_BUILD_KERNEL + /* This is the saved address to use when returning from a user-space + * signal handler. + */ + + uint32_t sigreturn; + +# endif +#endif + +#ifdef CONFIG_BUILD_KERNEL + /* The following array holds information needed to return from each nested + * system call. + */ + + uint8_t nsyscalls; + struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST]; + +#endif + + /* Register save area */ + + uint32_t regs[XCPTCONTEXT_REGS]; +}; + +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_RISCV_INCLUDE_RV32IM_IRQ_H */ + diff --git a/arch/risc-v/include/rv32im/syscall.h b/arch/risc-v/include/rv32im/syscall.h new file mode 100644 index 0000000000..5269b21e87 --- /dev/null +++ b/arch/risc-v/include/rv32im/syscall.h @@ -0,0 +1,208 @@ +/**************************************************************************** + * arch/risc-v/include/rv32im/syscall.h + * + * Copyright (C) 2011-2013, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through include/syscall.h or include/sys/sycall.h + */ + +#ifndef __ARCH_RISCV_INCLUDE_RV32IM_SYSCALL_H +#define __ARCH_RISCV_INCLUDE_RV32IM_SYSCALL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SYS_syscall 0x00 + +/* Configuration ********************************************************************/ +/* SYS call 1 and 2 are defined for internal use by the RISC-V port (see + * arch/riscv/include/mips32/syscall.h). In addition, SYS call 3 is the return from + * a SYS call in kernel mode. The first four syscall values must, therefore, be + * reserved (0 is not used). + */ + +#ifdef CONFIG_BUILD_KERNEL +# ifndef CONFIG_SYS_RESERVED +# error "CONFIG_SYS_RESERVED must be defined to the value 4" +# elif CONFIG_SYS_RESERVED != 4 +# error "CONFIG_SYS_RESERVED must have the value 4" +# endif +#endif + +/* sys_call macros ******************************************************************/ + +#ifndef __ASSEMBLY__ + +/* Context switching system calls ***************************************************/ + +/* SYS call 0: (not used) */ + +/* SYS call 1: + * + * void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function; + */ + +#define SYS_restore_context (1) +#define up_fullcontextrestore(restoreregs) \ + (void)sys_call1(SYS_restore_context, (uintptr_t)restoreregs) + +/* SYS call 2: + * + * void up_switchcontext(uint32_t *saveregs, uint32_t *restoreregs); + */ + +#define SYS_switch_context (2) +#define up_switchcontext(saveregs, restoreregs) \ + (void)sys_call2(SYS_switch_context, (uintptr_t)saveregs, (uintptr_t)restoreregs) + +#ifdef CONFIG_BUILD_KERNEL +/* SYS call 3: + * + * void up_syscall_return(void); + */ + +#define SYS_syscall_return (3) +#define up_syscall_return() (void)sys_call0(SYS_syscall_return) + +#endif +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: up_syscall0 + * + * Description: + * System call SYS_ argument and no additional parameters. + * + ****************************************************************************/ + +uintptr_t sys_call0(unsigned int nbr); + +/**************************************************************************** + * Name: up_syscall1 + * + * Description: + * System call SYS_ argument and one additional parameter. + * + ****************************************************************************/ + +uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1); + +/**************************************************************************** + * Name: up_syscall2 + * + * Description: + * System call SYS_ argument and two additional parameters. + * + ****************************************************************************/ + +uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1, uintptr_t parm2); + +/**************************************************************************** + * Name: up_syscall3 + * + * Description: + * System call SYS_ argument and three additional parameters. + * + ****************************************************************************/ + +uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1, uintptr_t parm2, + uintptr_t parm3); + +/**************************************************************************** + * Name: up_syscall4 + * + * Description: + * System call SYS_ argument and four additional parameters. + * + ****************************************************************************/ + +uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1, uintptr_t parm2, + uintptr_t parm3, uintptr_t parm4); + +/**************************************************************************** + * Name: up_syscall5 + * + * Description: + * System call SYS_ argument and five additional parameters. + * + ****************************************************************************/ + +uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1, uintptr_t parm2, + uintptr_t parm3, uintptr_t parm4, uintptr_t parm5); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_INCLUDE_RV32IM_SYSCALL_H */ + diff --git a/arch/risc-v/include/stdarg.h b/arch/risc-v/include/stdarg.h new file mode 100644 index 0000000000..143009f2c2 --- /dev/null +++ b/arch/risc-v/include/stdarg.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/risc-v/include/stdarg.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_STDARG_H +#define __ARCH_RISCV_INCLUDE_STDARG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* This should work with any modern gcc (newer than 3.4 or so) */ + +#define va_start(v,l) __builtin_va_start(v,l) +#define va_end(v) __builtin_va_end(v) +#define va_arg(v,l) __builtin_va_arg(v,l) +#define va_copy(d,s) __builtin_va_copy(d,s) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +typedef __builtin_va_list va_list; + +#endif /* __ARCH_RISCV_INCLUDE_STDARG_H */ diff --git a/arch/risc-v/include/syscall.h b/arch/risc-v/include/syscall.h new file mode 100644 index 0000000000..1616cb4685 --- /dev/null +++ b/arch/risc-v/include/syscall.h @@ -0,0 +1,91 @@ +/**************************************************************************** + * arch/risc-v/include/syscall.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified 2016 by Ken Pettit for RISC-V architecture. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through include/syscall.h or include/sys/sycall.h + */ + +#ifndef __ARCH_RISCV_INCLUDE_SYSCALL_H +#define __ARCH_RISCV_INCLUDE_SYSCALL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include RISC-V architecture-specific syscall macros */ + +#ifdef CONFIG_ARCH_RV32IM +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_RISCV_INCLUDE_SYSCALL_H */ + diff --git a/arch/risc-v/include/types.h b/arch/risc-v/include/types.h new file mode 100644 index 0000000000..8b7b09457c --- /dev/null +++ b/arch/risc-v/include/types.h @@ -0,0 +1,96 @@ +/**************************************************************************** + * arch/risc-v/include/types.h + * + * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through sys/types.h + */ + +#ifndef __ARCH_RISCV_INCLUDE_TYPES_H +#define __ARCH_RISCV_INCLUDE_TYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +//#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Type Declarations + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* These are the sizes of the standard integer types. NOTE that these type + * names have a leading underscore character. This file will be included + * (indirectly) by include/stdint.h and typedef'ed to the final name without + * the underscore character. This roundabout way of doings things allows + * the stdint.h to be removed from the include/ directory in the event that + * the user prefers to use the definitions provided by their toolchain header + * files + */ + +typedef signed char _int8_t; +typedef unsigned char _uint8_t; + +typedef signed short _int16_t; +typedef unsigned short _uint16_t; + +typedef signed int _int32_t; +typedef unsigned int _uint32_t; + +typedef signed long long _int64_t; +typedef unsigned long long _uint64_t; +#define __INT64_DEFINED + +/* A pointer is 4 bytes */ + +typedef signed int _intptr_t; +typedef unsigned int _uintptr_t; + +/* This is the size of the interrupt state save returned by irqsave(). */ + +typedef unsigned int irqstate_t; + +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Global Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_RISCV_INCLUDE_TYPES_H */ diff --git a/arch/risc-v/src/Makefile b/arch/risc-v/src/Makefile new file mode 100644 index 0000000000..e5916c3534 --- /dev/null +++ b/arch/risc-v/src/Makefile @@ -0,0 +1,232 @@ +############################################################################ +# arch/risc-v/src/Makefile +# +# Copyright (C) 2011-2012, 2014, 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Modified for RISC-V: +# +# Copyright (C) 2016 Ken Pettit. All rights reserved. +# Author: Ken Pettit +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include $(TOPDIR)/Make.defs +include chip/Make.defs + +ifeq ($(CONFIG_ARCH_RV32I),y) # Base Integer support +ARCH_SUBDIR = rv32i +else ifeq ($(CONFIG_ARCH_RV32IM),y) # Integer + math support +ARCH_SUBDIR = rv32im +else +ARCH_SUBDIR = rv32i # Default to base RV32I core +endif + +CPPFLAGS += $(EXTRADEFINES) +CFLAGS += $(EXTRADEFINES) +CXXFLAGS += $(EXTRADEFINES) + +ifeq ($(CONFIG_WINDOWS_NATIVE),y) + ARCH_SRCDIR = $(TOPDIR)\arch\$(CONFIG_ARCH)\src + NUTTX = "$(TOPDIR)\nuttx$(EXEEXT)" + CFLAGS += -I$(ARCH_SRCDIR)\chip + CFLAGS += -I$(ARCH_SRCDIR)\common + CFLAGS += -I$(ARCH_SRCDIR)\$(ARCH_SUBDIR) + CFLAGS += -I$(TOPDIR)\sched +else + ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src +ifeq ($(WINTOOL),y) + NUTTX = "${shell cygpath -w $(TOPDIR)/nuttx$(EXEEXT)}" + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/$(ARCH_SUBDIR)}" + CFLAGS += -I "${shell cygpath -w $(TOPDIR)/sched}" +else + NUTTX = "$(TOPDIR)/nuttx$(EXEEXT)" + CFLAGS += -I$(ARCH_SRCDIR)/chip + CFLAGS += -I$(ARCH_SRCDIR)/common + CFLAGS += -I$(ARCH_SRCDIR)/$(ARCH_SUBDIR) + CFLAGS += -I$(TOPDIR)/sched +endif +endif + +# The "head" object + +HEAD_OBJ = $(HEAD_ASRC:.S=$(OBJEXT)) +STARTUP_OBJS ?= $(HEAD_OBJ) + +# Flat build or kernel-mode objects + +ASRCS = $(CHIP_ASRCS) $(CMN_ASRCS) +AOBJS = $(ASRCS:.S=$(OBJEXT)) + +CSRCS = $(CHIP_CSRCS) $(CMN_CSRCS) +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +# User-mode objects + +UASRCS = $(CHIP_UASRCS) $(CMN_UASRCS) +UAOBJS = $(UASRCS:.S=$(OBJEXT)) + +UCSRCS = $(CHIP_UCSRCS) $(CMN_UCSRCS) +UCOBJS = $(UCSRCS:.c=$(OBJEXT)) + +USRCS = $(UASRCS) $(UCSRCS) +UOBJS = $(UAOBJS) $(UCOBJS) + +KBIN = libkarch$(LIBEXT) +UBIN = libuarch$(LIBEXT) +BIN = libarch$(LIBEXT) + +LDFLAGS += $(ARCHSCRIPT) + +EXTRA_LIBS ?= +EXTRA_LIBPATHS ?= +LINKLIBS ?= + +AFLAGS += -I$(TOPDIR)/include + +ifeq ($(CONFIG_WINDOWS_NATIVE),y) + BOARDMAKE = $(if $(wildcard .\board\Makefile),y,) + LIBPATHS += -L"$(TOPDIR)\lib" +ifeq ($(BOARDMAKE),y) + LIBPATHS += -L"$(TOPDIR)\arch\$(CONFIG_ARCH)\src\board" +endif + +else + BOARDMAKE = $(if $(wildcard ./board/Makefile),y,) + +ifeq ($(WINTOOL),y) + LIBPATHS += -L"${shell cygpath -w "$(TOPDIR)/lib"}" +ifeq ($(BOARDMAKE),y) + LIBPATHS += -L"${shell cygpath -w "$(TOPDIR)/arch/$(CONFIG_ARCH)/src/board"}" +endif + +else + LIBPATHS += -L"$(TOPDIR)/lib" +ifeq ($(BOARDMAKE),y) + LIBPATHS += -L"$(TOPDIR)/arch/$(CONFIG_ARCH)/src/board" +endif +endif +endif + +LDLIBS = $(patsubst %.a,%,$(patsubst lib%,-l%,$(LINKLIBS))) +ifeq ($(BOARDMAKE),y) + LDLIBS += -lboard +endif + +LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" +GCC_LIBDIR := ${shell dirname $(LIBGCC)} + +VPATH += chip +VPATH += common +VPATH += $(ARCH_SUBDIR) +VPATH += $(CHIP_DIR) + +all: $(HEAD_OBJ) $(BIN) + +.PHONY: board/libboard$(LIBEXT) + +$(AOBJS) $(UAOBJS) $(HEAD_OBJ): %$(OBJEXT): %.S + $(call ASSEMBLE, $<, $@) + +$(COBJS) $(UCOBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +$(BIN) $(KBIN): $(OBJS) + $(call ARCHIVE, $@, $(OBJS)) + @$(MAKE) depend + +$(UBIN): $(UOBJS) + $(call ARCHIVE, $@, $(UOBJS)) + +board/libboard$(LIBEXT): + $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" libboard$(LIBEXT) EXTRADEFINES=$(EXTRADEFINES) + +nuttx$(EXEEXT): $(HEAD_OBJ) board/libboard$(LIBEXT) + $(Q) echo "LD: nuttx" + $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ + -o $(NUTTX) $(HEAD_OBJ) $(EXTRA_OBJS) \ + --start-group $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) --end-group +ifneq ($(CONFIG_WINDOWS_NATIVE),y) + $(Q) $(NM) $(NUTTX) | \ + grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ + sort > $(TOPDIR)/System.map +endif + +# This is part of the top-level export target +# Note that there may not be a head object if layout is handled +# by the linker configuration. + +export_startup: board/libboard$(LIBEXT) $(STARTUP_OBJS) +ifneq ($(STARTUP_OBJS),) + $(Q) if [ -d "$(EXPORT_DIR)/startup" ]; then \ + cp -f $(STARTUP_OBJS) "$(EXPORT_DIR)/startup/."; \ + else \ + echo "$(EXPORT_DIR)/startup does not exist"; \ + exit 1; \ + fi +endif + +# Dependencies + +.depend: Makefile $(SRCS) +ifeq ($(BOARDMAKE),y) + $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" depend +endif + $(Q) $(MKDEP) $(patsubst %,--dep-path %,$(subst :, ,$(VPATH))) \ + "$(CC)" -- $(CFLAGS) -- $(SRCS) > Make.dep + $(Q) touch $@ + +depend: .depend + +clean: +ifeq ($(BOARDMAKE),y) + $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" clean +endif + $(call DELFILE, $(KBIN)) + $(call DELFILE, $(UBIN)) + $(call DELFILE, $(BIN)) + $(call DELFILE, $(HEAD_OBJ)) + $(call CLEAN) + +distclean: clean +ifeq ($(BOARDMAKE),y) + $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" distclean +endif + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + +info: + @echo $(HEAD_OBJ) + @echo $(ASRCS) + @echo $(CONFIG_ARCH_CHIP) + +#-include Make.dep diff --git a/arch/risc-v/src/common/up_allocateheap.c b/arch/risc-v/src/common/up_allocateheap.c new file mode 100644 index 0000000000..002c853cd0 --- /dev/null +++ b/arch/risc-v/src/common/up_allocateheap.c @@ -0,0 +1,88 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_allocateheap.c + * + * Copyright (C) 2010, 2013, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * For the kernel build (CONFIG_BUILD_KERNEL=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the + * size of the unprotected, user-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated (and protected) by an analogous up_allocate_kheap(). + * + ****************************************************************************/ + +void up_allocate_heap(FAR void **heap_start, size_t *heap_size) +{ + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (FAR void *)g_idle_topstack; + *heap_size = CONFIG_RAM_END - g_idle_topstack; +} diff --git a/arch/risc-v/src/common/up_arch.h b/arch/risc-v/src/common/up_arch.h new file mode 100644 index 0000000000..fc60219345 --- /dev/null +++ b/arch/risc-v/src/common/up_arch.h @@ -0,0 +1,70 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_arch.h + * + * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef ___ARCH_RISCV_SRC_COMMON_UP_ARCH_H +#define ___ARCH_RISCV_SRC_COMMON_UP_ARCH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +# define getreg8(a) (*(volatile uint8_t *)(a)) +# define putreg8(v,a) (*(volatile uint8_t *)(a) = (v)) +# define getreg16(a) (*(volatile uint16_t *)(a)) +# define putreg16(v,a) (*(volatile uint16_t *)(a) = (v)) +# define getreg32(a) (*(volatile uint32_t *)(a)) +# define putreg32(v,a) (*(volatile uint32_t *)(a) = (v)) + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ASSEMBLY__ */ +#endif /* ___ARCH_ARM_SRC_COMMON_UP_ARCH_H */ diff --git a/arch/risc-v/src/common/up_createstack.c b/arch/risc-v/src/common/up_createstack.c new file mode 100644 index 0000000000..494d54e4ab --- /dev/null +++ b/arch/risc-v/src/common/up_createstack.c @@ -0,0 +1,214 @@ +/**************************************************************************** + * arch/riscv/src/common/up_createstack.c + * + * Copyright (C) 2011, 2013, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Macros + ****************************************************************************/ + +/* MIPS requires at least a 4-byte stack alignment. For floating point use, + * however, the stack must be aligned to 8-byte addresses. + */ + +#ifdef CONFIG_LIBC_FLOATINGPOINT +# define STACK_ALIGNMENT 8 +#else +# define STACK_ALIGNMENT 4 +#endif + +/* Stack alignment macros */ + +#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1) +#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK) +#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_create_stack + * + * Description: + * Allocate a stack for a new thread and setup up stack-related information + * in the TCB. + * + * The following TCB fields must be initialized by this function: + * + * - adj_stack_size: Stack size after adjustment for hardware, processor, + * etc. This value is retained only for debug purposes. + * - stack_alloc_ptr: Pointer to allocated stack + * - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of + * the stack pointer. + * + * Inputs: + * - tcb: The TCB of new task + * - stack_size: The requested stack size. At least this much + * must be allocated. + * - ttype: The thread type. This may be one of following (defined in + * include/nuttx/sched.h): + * + * TCB_FLAG_TTYPE_TASK Normal user task + * TCB_FLAG_TTYPE_PTHREAD User pthread + * TCB_FLAG_TTYPE_KERNEL Kernel thread + * + * This thread type is normally available in the flags field of the TCB, + * however, there are certain contexts where the TCB may not be fully + * initialized when up_create_stack is called. + * + * If CONFIG_BUILD_KERNEL is defined, then this thread type may affect + * how the stack is allocated. For example, kernel thread stacks should + * be allocated from protected kernel memory. Stacks for user tasks and + * threads must come from memory that is accessible to user code. + * + ****************************************************************************/ + +int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) +{ + /* Is there already a stack allocated of a different size? Because of + * alignment issues, stack_size might erroneously appear to be of a + * different size. Fortunately, this is not a critical operation. + */ + + if (tcb->stack_alloc_ptr && tcb->adj_stack_size != stack_size) + { + /* Yes.. Release the old stack */ + + up_release_stack(tcb, ttype); + } + + /* Do we need to allocate a new stack? */ + + if (!tcb->stack_alloc_ptr) + { + /* Allocate the stack. If DEBUG is enabled (but not stack debug), + * then create a zeroed stack to make stack dumps easier to trace. + */ + +#if defined(CONFIG_BUILD_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP) + /* Use the kernel allocator if this is a kernel thread */ + + if (ttype == TCB_FLAG_TTYPE_KERNEL) + { + tcb->stack_alloc_ptr = (uint32_t *)kmm_malloc(stack_size); + } + else +#endif + { + /* Use the user-space allocator if this is a task or pthread */ + + tcb->stack_alloc_ptr = (uint32_t *)kumm_malloc(stack_size); + } + +#ifdef CONFIG_DEBUG_FEATURES + /* Was the allocation successful? */ + + if (!tcb->stack_alloc_ptr) + { + serr("ERROR: Failed to allocate stack, size %d\n", stack_size); + } +#endif + } + + /* Did we successfully allocate a stack? */ + + if (tcb->stack_alloc_ptr) + { + size_t top_of_stack; + size_t size_of_stack; + + /* Yes.. If stack debug is enabled, then fill the stack with a + * recognizable value that we can use later to test for high + * water marks. + */ + +#ifdef CONFIG_STACK_COLORATION + memset(tcb->stack_alloc_ptr, 0xaa, stack_size); +#endif + + /* MIPS uses a push-down stack: the stack grows toward lower + * addresses in memory. The stack pointer register points to the + * lowest, valid working address (the "top" of the stack). Items on + * the stack are referenced as positive word offsets from sp. + */ + + top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4; + + /* The MIPS stack must be aligned at word (4 byte) boundaries; for + * floating point use, the stack must be aligned to 8-byte addresses. + * If necessary top_of_stack must be rounded down to the next + * boundary to meet these alignment requirements. + */ + + top_of_stack = STACK_ALIGN_DOWN(top_of_stack); + size_of_stack = top_of_stack - (uint32_t)tcb->stack_alloc_ptr + 4; + + /* Save the adjusted stack values in the struct tcb_s */ + + tcb->adj_stack_ptr = (FAR uint32_t *)top_of_stack; + tcb->adj_stack_size = size_of_stack; + + board_autoled_on(LED_STACKCREATED); + return OK; + } + + return ERROR; +} diff --git a/arch/risc-v/src/common/up_exit.c b/arch/risc-v/src/common/up_exit.c new file mode 100644 index 0000000000..4345f03f22 --- /dev/null +++ b/arch/risc-v/src/common/up_exit.c @@ -0,0 +1,188 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_exit.c + * + * Copyright (C) 2011, 2013-2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#ifdef CONFIG_DUMP_ON_EXIT +#include +#endif + +#include "task/task.h" +#include "sched/sched.h" +#include "group/group.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_DEBUG_SCHED_INFO +# undef CONFIG_DUMP_ON_EXIT +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _up_dumponexit + * + * Description: + * Dump the state of all tasks whenever on task exits. This is debug + * instrumentation that was added to check file-related reference counting + * but could be useful again sometime in the future. + * + ****************************************************************************/ + +#ifdef CONFIG_DUMP_ON_EXIT +static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) +{ +#if CONFIG_NFILE_DESCRIPTORS > 0 + FAR struct filelist *filelist; +#if CONFIG_NFILE_STREAMS > 0 + FAR struct streamlist *streamlist; +#endif + int i; +#endif + + sinfo(" TCB=%p name=%s pid=%d\n", tcb, tcb->argv[0], tcb->pid); + sinfo(" priority=%d state=%d\n", tcb->sched_priority, tcb->task_state); + +#if CONFIG_NFILE_DESCRIPTORS > 0 + filelist = tcb->group->tg_filelist; + for (i = 0; i < CONFIG_NFILE_DESCRIPTORS; i++) + { + struct inode *inode = filelist->fl_files[i].f_inode; + if (inode) + { + sinfo(" fd=%d refcount=%d\n", + i, inode->i_crefs); + } + } +#endif + +#if CONFIG_NFILE_STREAMS > 0 + streamlist = tcb->group->tg_streamlist; + for (i = 0; i < CONFIG_NFILE_STREAMS; i++) + { + struct file_struct *filep = &streamlist->sl_streams[i]; + if (filep->fs_fd >= 0) + { +#if CONFIG_STDIO_BUFFER_SIZE > 0 + sinfo(" fd=%d nbytes=%d\n", + filep->fs_fd, + filep->fs_bufpos - filep->fs_bufstart); +#else + sinfo(" fd=%d\n", filep->fs_fd); +#endif + } + } +#endif +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _exit + * + * Description: + * This function causes the currently executing task to cease + * to exist. This is a special case of task_delete() where the task to + * be deleted is the currently executing task. It is more complex because + * a context switch must be perform to the next ready to run task. + * + ****************************************************************************/ + +void _exit(int status) +{ + struct tcb_s *tcb; + + /* Disable interrupts. They will be restored when the next + * task is started. + */ + + (void)up_irq_save(); + + sinfo("TCB=%p exiting\n", this_task()); + +#ifdef CONFIG_DUMP_ON_EXIT + sinfo("Other tasks:\n"); + sched_foreach(_up_dumponexit, NULL); +#endif + + /* Destroy the task at the head of the ready to run list. */ + + (void)task_exit(); + + /* Now, perform the context switch to the new ready-to-run task at the + * head of the list. + */ + + tcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously running + * task is closed down gracefully (data caches dump, MMU flushed) and + * set up the address environment for the new thread at the head of + * the ready-to-run list. + */ + + (void)group_addrenv(tcb); +#endif + + /* Then switch contexts */ + + up_fullcontextrestore(tcb->xcp.regs); + + /* up_fullcontextrestore() should not return but could if the software + * interrupts are disabled. + */ + + PANIC(); +} + diff --git a/arch/risc-v/src/common/up_idle.c b/arch/risc-v/src/common/up_idle.c new file mode 100644 index 0000000000..0c8a867d79 --- /dev/null +++ b/arch/risc-v/src/common/up_idle.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_idle.c + * + * Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "up_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + sched_process_timer(); +#else + + /* This would be an appropriate place to put some MCU-specific logic to + * sleep in a reduced power mode until an interrupt occurs to save power + */ + + /* This is a kludge that I still don't understand. The call to kmm_trysemaphore() + * in the os_start.c IDLE loop seems necessary for the good health of the IDLE + * loop. When the work queue is enabled, this logic is removed from the IDLE + * loop and it appears that we are somehow left idling with interrupts non- + * functional. The following should be no-op, it just disables then re-enables + * interrupts. But it fixes the problem and will stay here until I understand + * the problem/fix better. + * + * And no, the contents of the CP0 status register are not incorrect. But for + * some reason the status register needs to be re-written again on this thread + * for it to take effect. This might be a PIC32-only issue? + */ + +#ifdef CONFIG_SCHED_WORKQUEUE + irqstate_t flags = enter_critical_section(); + leave_critical_section(flags); +#endif +#endif +} diff --git a/arch/risc-v/src/common/up_initialize.c b/arch/risc-v/src/common/up_initialize.c new file mode 100644 index 0000000000..a31051f3e3 --- /dev/null +++ b/arch/risc-v/src/common/up_initialize.c @@ -0,0 +1,203 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_initialize.c + * + * Copyright (C) 2007-2010, 2012-2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_calibratedelay + * + * Description: + * Delay loops are provided for short timing loops. This function, if + * enabled, will just wait for 100 seconds. Using a stopwatch, you can + * can then determine if the timing loops are properly calibrated. + * + ****************************************************************************/ + +#if defined(CONFIG_ARCH_CALIBRATION) && defined(CONFIG_DEBUG) +static void up_calibratedelay(void) +{ + int i; + lldbg("Beginning 100s delay\n"); + for (i = 0; i < 100; i++) + { + up_mdelay(1000); + } + lldbg("End 100s delay\n"); +} +#else +# define up_calibratedelay() +#endif + +/**************************************************************************** + * Name: up_color_intstack + * + * Description: + * Set the interrupt stack to a value so that later we can determine how + * much stack space was used by interrupt handling logic + * + ****************************************************************************/ + +#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 +static inline void up_color_intstack(void) +{ + uint32_t *ptr = (uint32_t *)&g_intstackalloc; + ssize_t size; + + for (size = (CONFIG_ARCH_INTERRUPTSTACK & ~3); + size > 0; + size -= sizeof(uint32_t)) + { + *ptr++ = INTSTACK_COLOR; + } +} +#else +# define up_color_intstack() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_initialize + * + * Description: + * up_initialize will be called once during OS initialization after the + * basic OS services have been initialized. The architecture specific + * details of initializing the OS will be handled here. Such things as + * setting up interrupt service routines, starting the clock, and + * registering device drivers are some of the things that are different + * for each processor and hardware platform. + * + * up_initialize is called after the OS initialized but before the user + * initialization logic has been started and before the libraries have + * been initialized. OS services and driver services are available. + * + ****************************************************************************/ + +void up_initialize(void) +{ + /* Calibrate the timing loop */ + + up_calibratedelay(); + + /* Colorize the interrupt stack */ + + up_color_intstack(); + + /* Add any extra memory fragments to the memory manager */ + + up_addregion(); + + /* Initialize the interrupt subsystem */ + + up_irqinitialize(); + + /* Initialize the system timer interrupt */ + +#if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS) && \ + !defined(CONFIG_SYSTEMTICK_EXTCLK) + up_timer_initialize(); +#endif + + /* Register devices */ + +#if CONFIG_NFILE_DESCRIPTORS > 0 + +#if defined(CONFIG_DEV_NULL) + devnull_register(); /* Standard /dev/null */ +#endif + +#if defined(CONFIG_DEV_ZERO) + devzero_register(); /* Standard /dev/zero */ +#endif + +#endif /* CONFIG_NFILE_DESCRIPTORS */ + + /* Initialize the serial device driver */ + +#ifdef USE_SERIALDRIVER + up_serialinit(); +#endif + + /* Initialize the console device driver (if it is other than the standard + * serial driver). + */ + +#if defined(CONFIG_DEV_LOWCONSOLE) + lowconsole_init(); +#elif defined(CONFIG_SYSLOG_CONSOLE) + syslog_console_init(); +#elif defined(CONFIG_RAMLOG_CONSOLE) + ramlog_consoleinit(); +#endif + + /* Initialize the system logging device */ + +#ifdef CONFIG_SYSLOG_CHAR + syslog_initialize(); +#endif +#ifdef CONFIG_RAMLOG_SYSLOG + ramlog_sysloginit(); +#endif + + board_autoled_on(LED_IRQSENABLED); +} diff --git a/arch/risc-v/src/common/up_internal.h b/arch/risc-v/src/common/up_internal.h new file mode 100644 index 0000000000..f4481a2269 --- /dev/null +++ b/arch/risc-v/src/common/up_internal.h @@ -0,0 +1,160 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_internal.h + * + * Copyright (C) 2007-2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_COMMON_UP_INTERNAL_H +#define __ARCH_RISCV_SRC_COMMON_UP_INTERNAL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* This is the value used to mark the stack for subsequent stack monitoring + * logic. + */ + +#define STACK_COLOR 0xdeadbeef +#define INTSTACK_COLOR 0xdeadbeef +#define HEAP_COLOR 'h' + +/* In the RISC_V model, the state is copied from the stack to the TCB, but + * only a referenced is passed to get the state from the TCB. + */ + +#define up_savestate(regs) up_copystate(regs, (uint32_t*)g_current_regs) +#define up_restorestate(regs) (g_current_regs = regs) + +/* Determine which (if any) console driver to use. If a console is enabled + * and no other console device is specified, then a serial console is + * assumed. + */ + +#if !defined(CONFIG_DEV_CONSOLE) || CONFIG_NFILE_DESCRIPTORS <= 0 +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +# undef CONFIG_DEV_LOWCONSOLE +# undef CONFIG_RAMLOG_CONSOLE +#else +# if defined(CONFIG_RAMLOG_CONSOLE) +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +# undef CONFIG_DEV_LOWCONSOLE +# elif defined(CONFIG_DEV_LOWCONSOLE) +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +# else +# define USE_SERIALDRIVER 1 +# define USE_EARLYSERIALINIT 1 +# endif +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Variables + ****************************************************************************/ + +extern volatile uint32_t *g_current_regs; + +extern uint32_t g_idle_topstack; + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* Low level initialization provided by board-level logic ******************/ + +void up_boot(void); + +/* Memory allocation ********************************************************/ + +void up_addregion(void); +void up_allocat_eheap(FAR void **heap_start, size_t *heap_size); + +/* IRQ initialization *******************************************************/ + +void up_irqinitialize(void); +void up_copystate(uint32_t *dest, uint32_t *src); +void up_dumpstate(void); +void up_sigdeliver(void); +int up_swint(int irq, FAR void *context); +uint32_t up_get_newintctx(void); + +/* System timer *************************************************************/ + +void up_timer_initialize(void); +int up_timerisr(int irq, void *context); + +/* Low level serial output **************************************************/ + +void up_lowputc(char ch); +void up_puts(const char *str); +void up_lowputs(const char *str); + +/* The OS start routine **************************************************/ + +void os_start(void); + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_RISCV_SRC_COMMON_UP_INTERNAL_H */ diff --git a/arch/risc-v/src/common/up_interruptcontext.c b/arch/risc-v/src/common/up_interruptcontext.c new file mode 100644 index 0000000000..8bdc595529 --- /dev/null +++ b/arch/risc-v/src/common/up_interruptcontext.c @@ -0,0 +1,70 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_interruptcontext.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "up_internal.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_interrupt_context + * + * Description: Return true is we are currently executing in + * the interrupt handler context. + ****************************************************************************/ + +bool up_interrupt_context(void) +{ + return g_current_regs != NULL; +} diff --git a/arch/risc-v/src/common/up_releasestack.c b/arch/risc-v/src/common/up_releasestack.c new file mode 100644 index 0000000000..15301c49d2 --- /dev/null +++ b/arch/risc-v/src/common/up_releasestack.c @@ -0,0 +1,122 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_releasestack.c + * + * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "up_internal.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_release_stack + * + * Description: + * A task has been stopped. Free all stack related resources retained in + * the defunct TCB. + * + * Input Parmeters + * - dtcb: The TCB containing information about the stack to be released + * - ttype: The thread type. This may be one of following (defined in + * include/nuttx/sched.h): + * + * TCB_FLAG_TTYPE_TASK Normal user task + * TCB_FLAG_TTYPE_PTHREAD User pthread + * TCB_FLAG_TTYPE_KERNEL Kernel thread + * + * This thread type is normally available in the flags field of the TCB, + * however, there are certain error recovery contexts where the TCB may + * not be fully initialized when up_release_stack is called. + * + * If CONFIG_BUILD_KERNEL is defined, then this thread type may affect + * how the stack is freed. For example, kernel thread stacks may have + * been allocated from protected kernel memory. Stacks for user tasks + * and threads must have come from memory that is accessible to user + * code. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_release_stack(FAR struct tcb_s *dtcb, uint8_t ttype) +{ + /* Is there a stack allocated? */ + + if (dtcb->stack_alloc_ptr) + { +#if defined(CONFIG_BUILD_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP) + /* Use the kernel allocator if this is a kernel thread */ + + if (ttype == TCB_FLAG_TTYPE_KERNEL) + { + sched_kfree(dtcb->stack_alloc_ptr); + } + else +#endif + { + /* Use the user-space allocator if this is a task or pthread */ + + sched_ufree(dtcb->stack_alloc_ptr); + } + + /* Mark the stack freed */ + + dtcb->stack_alloc_ptr = NULL; + } + + /* The size of the allocated stack is now zero */ + + dtcb->adj_stack_size = 0; +} diff --git a/arch/risc-v/src/common/up_stackframe.c b/arch/risc-v/src/common/up_stackframe.c new file mode 100644 index 0000000000..b3cb9801d4 --- /dev/null +++ b/arch/risc-v/src/common/up_stackframe.c @@ -0,0 +1,143 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_stackframe.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Macros + ****************************************************************************/ +/* MIPS requires at least a 4-byte stack alignment. For floating point use, + * however, the stack must be aligned to 8-byte addresses. + */ + +#ifdef CONFIG_LIBC_FLOATINGPOINT +# define STACK_ALIGNMENT 8 +#else +# define STACK_ALIGNMENT 4 +#endif + +/* Stack alignment macros */ + +#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1) +#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK) +#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_stack_frame + * + * Description: + * Allocate a stack frame in the TCB's stack to hold thread-specific data. + * This function may be called anytime after up_create_stack() or + * up_use_stack() have been called but before the task has been started. + * + * Thread data may be kept in the stack (instead of in the TCB) if it is + * accessed by the user code directly. This includes such things as + * argv[]. The stack memory is guaranteed to be in the same protection + * domain as the thread. + * + * The following TCB fields will be re-initialized: + * + * - adj_stack_size: Stack size after removal of the stack frame from + * the stack + * - adj_stack_ptr: Adjusted initial stack pointer after the frame has + * been removed from the stack. This will still be the initial value + * of the stack pointer when the task is started. + * + * Inputs: + * - tcb: The TCB of new task + * - frame_size: The size of the stack frame to allocate. + * + * Returned Value: + * - A pointer to bottom of the allocated stack frame. NULL will be + * returned on any failures. The alignment of the returned value is + * the same as the alignment of the stack itself. + * + ****************************************************************************/ + +FAR void *up_stack_frame(FAR struct tcb_s *tcb, size_t frame_size) +{ + uintptr_t topaddr; + + /* Align the frame_size */ + + frame_size = STACK_ALIGN_UP(frame_size); + + /* Is there already a stack allocated? Is it big enough? */ + + if (!tcb->stack_alloc_ptr || tcb->adj_stack_size <= frame_size) + { + return NULL; + } + + /* Save the adjusted stack values in the struct tcb_s */ + + topaddr = (uintptr_t)tcb->adj_stack_ptr - frame_size; + tcb->adj_stack_ptr = (FAR void *)topaddr; + tcb->adj_stack_size -= frame_size; + + /* Reset the initial stack pointer */ + + tcb->xcp.regs[REG_SP] = (uint32_t)tcb->adj_stack_ptr; + + /* And return the pointer to the allocated region */ + + return (FAR void *)(topaddr + sizeof(uint32_t)); +} + diff --git a/arch/risc-v/src/common/up_usestack.c b/arch/risc-v/src/common/up_usestack.c new file mode 100644 index 0000000000..605bb79b04 --- /dev/null +++ b/arch/risc-v/src/common/up_usestack.c @@ -0,0 +1,152 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_usestack.c + * + * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* MIPS requires at least a 4-byte stack alignment. For floating point use, + * however, the stack must be aligned to 8-byte addresses. + */ + +#ifdef CONFIG_LIBC_FLOATINGPOINT +# define STACK_ALIGNMENT 8 +#else +# define STACK_ALIGNMENT 4 +#endif + +/* Stack alignment macros */ + +#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1) +#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK) +#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_use_stack + * + * Description: + * Setup up stack-related information in the TCB using pre-allocated stack + * memory. This function is called only from task_init() when a task or + * kernel thread is started (never for pthreads). + * + * The following TCB fields must be initialized: + * + * - adj_stack_size: Stack size after adjustment for hardware, + * processor, etc. This value is retained only for debug + * purposes. + * - stack_alloc_ptr: Pointer to allocated stack + * - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The + * initial value of the stack pointer. + * + * Inputs: + * - tcb: The TCB of new task + * - stack_size: The allocated stack size. + * + * NOTE: Unlike up_stack_create() and up_stack_release, this function + * does not require the task type (ttype) parameter. The TCB flags will + * always be set to provide the task type to up_use_stack() if it needs + * that information. + * + ****************************************************************************/ + +int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size) +{ + size_t top_of_stack; + size_t size_of_stack; + + /* Is there already a stack allocated? */ + + if (tcb->stack_alloc_ptr) + { + /* Yes.. Release the old stack allocation */ + + up_release_stack(tcb, tcb->flags & TCB_FLAG_TTYPE_MASK); + } + + /* Save the new stack allocation */ + + tcb->stack_alloc_ptr = stack; + + /* MIPS uses a push-down stack: the stack grows toward loweraddresses in + * memory. The stack pointer register, points to the lowest, valid work + * address (the "top" of the stack). Items on the stack are referenced + * as positive word offsets from sp. + */ + + top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4; + + /* The MIPS stack must be aligned at word (4 byte) or double word (8 byte) + * boundaries. If necessary top_of_stack must be rounded down to the + * next boundary + */ + + top_of_stack = STACK_ALIGN_DOWN(top_of_stack); + size_of_stack = top_of_stack - (uint32_t)tcb->stack_alloc_ptr + 4; + + /* Save the adjusted stack values in the struct tcb_s */ + + tcb->adj_stack_ptr = (uint32_t *)top_of_stack; + tcb->adj_stack_size = size_of_stack; + + return OK; +} diff --git a/arch/risc-v/src/nr5m100/Kconfig b/arch/risc-v/src/nr5m100/Kconfig new file mode 100644 index 0000000000..c54f950c62 --- /dev/null +++ b/arch/risc-v/src/nr5m100/Kconfig @@ -0,0 +1,121 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "NanoRisc5 Configuration Options" + +choice + prompt "NR5 Chip Selection" + default ARCH_CHIP_NR5M100 + depends on ARCH_CHIP_NR5 + +config ARCH_CHIP_NR5M100 + bool "NR5M100" + select NR5_HAVE_UART1 + select NR5_HAVE_GPIOA + select NR5_HAVE_GPIOB + select NR5_HAVE_GPIOC + ---help--- + NanoRisc5, RV32IM 128K PROGRAM SRAM, 128K DATA SRAM + +endchoice + +config NR5_NR5M100 + bool + default y + select NR5_NR5M1XX + select NR5_HAVE_UART1 + select NR5_HAVE_TIMER1 + +config NR5_NR5M1XX + bool + default n + +config NR5_EPIC + bool "Has Embedded Priority Interrupt Controller (EPIC)" + ---help--- + NanoRisc5 core can have either single vector interrupts or priority + encoded interrupts. Selects if the core was compiled with EPIC. + +menu "NR5 Peripheral Support" + +# These "hidden" settings determine is a peripheral option is available for the +# selection MCU + +config NR5_HAVE_UART1 + bool + default n + select UART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +config NR5_HAVE_TIMER1 + bool + default n + +config NR5_HAVE_TIM2 + bool + default n + +config NR5_HAVE_I2C1 + bool + default n + +config NR5_HAVE_SPI1 + bool + default n + +# These are the peripheral selections proper + +config NR5_I2C1 + bool "I2C1" + default n + select NR5_I2C + +config NR5_SPI1 + bool "SPI1" + default n + select SPI + select NR5_SPI + +config NR5_TIMER1 + bool "TIMER1" + default n + depends on NR5_HAVE_TIMER1 + +config NR5_TIMER2 + bool "TIMER2" + default n + +config NR5_UART1 + bool "UART1" + default n + select ARCH_HAVE_UART1 + select ARCH_HAVE_SERIAL_TERMIOS + select NR5_UART + +endmenu + +config NR5_SPI + bool + +config NR5_I2C + bool + +config NR5_UART + bool + +config NR5_UART_RX_BUF_SIZE + int "UART RX Bufer size" + default 64 + depends on NR5_UART + ---help--- + Size of RX buffers for NR5 UARTs + +config NR5_UART_TX_BUF_SIZE + int "UART TX Bufer size" + default 64 + depends on NR5_UART + ---help--- + Size of TX buffers for NR5 UARTs + diff --git a/arch/risc-v/src/nr5m100/Make.defs b/arch/risc-v/src/nr5m100/Make.defs new file mode 100644 index 0000000000..8d7b9ee85b --- /dev/null +++ b/arch/risc-v/src/nr5m100/Make.defs @@ -0,0 +1,74 @@ +############################################################################ +# arch/risc-v/src/nr5m100/Make.defs +# +# Copyright (C) 2016 Ken Pettit. All rights reserved. +# Author: Ken Pettit +# +# # Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# Specify our HEAD assembly file. This will be linked as +# the first object file, so it will appear at address 0 +HEAD_ASRC = nr5_vectors.S + +# Specify our general Assembly files +CHIP_ASRCS = nr5_head.S nr5_csr.S up_syscall.S + +# If we are compiling the NELIB library, then specify it +# in AFLAGS so we can change up our startup behavior +ifeq ($(CONFIG_LIB_NEWLIB),y) +AFLAGS += -DCONFIG_LIB_NEWLIB +endif + +# Override the arch to enable hardware MUL during assembly. +# This is to support our hardware mul test. For that test, +# we have to disable hardware mul for C code so the soft +# math libs will be used to compare software mul vs hw mul. +# But hw mul must be enabled to compile the .S file, or we +# will get an illegal instruction error. +ASARCHCPUFLAGS += -march=RV32IMXcustom + +# Specify C code within the common directory to be included +CMN_CSRCS += up_initialize.c up_swint.c +CMN_CSRCS += up_allocateheap.c up_createstack.c up_dumpstate.c up_exit.c up_idle.c +CMN_CSRCS += up_assert.c up_blocktask.c up_copystate.c up_initialstate.c +CMN_CSRCS += up_interruptcontext.c up_releasepending.c up_reprioritizertr.c +CMN_CSRCS += up_releasestack.c up_stackframe.c up_schedulesigaction.c up_sigdeliver.c +CMN_CSRCS += up_unblocktask.c up_usestack.c + +ifeq ($(CONFIG_ARCH_HAVE_VFORK),y) +CMN_CSRCS += up_vfork.c +endif + +# Specify our C code within this directory to be included +CHIP_CSRCS = nr5_init.c nr5_arch.c +CHIP_CSRCS += nr5_lowputc.c nr5_allocateheap.c nr5_serial.c +CHIP_CSRCS += nr5_timerisr.c nr5_irq.c nr5_irq_dispatch.c + +ifeq ($(CONFIG_TIMER),y) +CHIP_CSRCS += nr5_tim_lowerhalf.c +endif + diff --git a/arch/risc-v/src/nr5m100/chip.h b/arch/risc-v/src/nr5m100/chip.h new file mode 100644 index 0000000000..dbe9928c6f --- /dev/null +++ b/arch/risc-v/src/nr5m100/chip.h @@ -0,0 +1,67 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/chip.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_NR5M100_CHIP_H +#define __ARCH_RISCV_SRC_NR5M100_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/* If the common RV32IM vector handling logic is used, then include the + * required vector definitions as well. + */ + +#ifdef CONFIG_RV32IM_CMNVECTOR +# if defined(CONFIG_NR5_NR5M1XX) +# include "chip/nr5m1xx_vectors.h" +# else +# error "No vector file for this NanoRisc5 family" +# endif +#endif + +/* Include the chip memory map. */ + +#include "nr5_memorymap.h" + +/* Include our custom access routines for ISR masking, priority */ + +#include "nr5_csr.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#endif /* __ARCH_RISCV_SRC_NR5M100_CHIP_H */ + diff --git a/arch/risc-v/src/nr5m100/chip/nr5m1xx_epic.h b/arch/risc-v/src/nr5m100/chip/nr5m1xx_epic.h new file mode 100644 index 0000000000..3fa13aed10 --- /dev/null +++ b/arch/risc-v/src/nr5m100/chip/nr5m1xx_epic.h @@ -0,0 +1,41 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/chip/nr5_epic.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_EPIC_H +#define ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_EPIC_H + +#define NR5_EPIC_PRI1_REG 0x7E1 +#define NR5_EPIC_PRI2_REG 0x7E2 +#define NR5_EPIC_PRI3_REG 0x7E3 +#define NR5_EPIC_STAT_REG 0x7E4 + +#endif /* _ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_EPIC_H */ diff --git a/arch/risc-v/src/nr5m100/chip/nr5m1xx_memorymap.h b/arch/risc-v/src/nr5m100/chip/nr5m1xx_memorymap.h new file mode 100644 index 0000000000..4ebc6879d1 --- /dev/null +++ b/arch/risc-v/src/nr5m100/chip/nr5m1xx_memorymap.h @@ -0,0 +1,57 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/chip/nr5m1xx_memorymap.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_MEMORYMAP_H +#define __ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_MEMORYMAP_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* BOOT ROM, SRAM, PERIPHERALS ******************************************************/ + +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000 - 384Kb SRAM */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x4fffffff: Peripheral block */ + +/* Register Base Address ************************************************************/ + +#define NR5_UART1_BASE 0x40000000 /* 0x40000000 - 0x40000fff: UART0 */ +#define NR5_GPIO1_BASE 0x40001000 /* 0x40001000 - 0x40001fff: GPIO1 */ +#define NR5_GPIO2_BASE 0x40002000 /* 0x40002000 - 0x40002fff: GPIO2 */ +#define NR5_GPIO3_BASE 0x40003000 /* 0x40003000 - 0x40003fff: GPIO3 */ +#define NR5_TIMER1_BASE 0x40004000 /* 0x40004000 - 0x40004fff: TIMER0 timer */ +#define NR5_TIMER2_BASE 0x40005000 /* 0x40005000 - 0x40005fff: TIMER1 timer */ +#define NR5_EXTMEM_BASE 0x40006000 /* 0x40006000 - 0x40006fff: EXTMEM Controller*/ + +#endif /* __ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_MEMORYMAP_H */ + diff --git a/arch/risc-v/src/nr5m100/chip/nr5m1xx_timer.h b/arch/risc-v/src/nr5m100/chip/nr5m1xx_timer.h new file mode 100644 index 0000000000..4739965cf4 --- /dev/null +++ b/arch/risc-v/src/nr5m100/chip/nr5m1xx_timer.h @@ -0,0 +1,190 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/chip/nr5_timer.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_TIMERA_H +#define ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_TIMERA_H + +#include "nr5m1xx_memorymap.h" + +/* The timers used in the NR5M100 are functionally equivalent to + * Timer A in the MSP430. The hardware peripheral in the FPGA uses the BSD + * licensed RTL code from the OpenMSP430 project on opencores.org. + */ + +/* TimerA offet definitions */ + +#define NR5_TIMERA_TACTL_OFFSET 0x00 +#define NR5_TIMERA_TAR_OFFSET 0x04 +#define NR5_TIMERA_TACCTL0_OFFSET 0x08 +#define NR5_TIMERA_TACCR0_OFFSET 0x0C +#define NR5_TIMERA_TACCTL1_OFFSET 0x10 +#define NR5_TIMERA_TACCR1_OFFSET 0x14 +#define NR5_TIMERA_TACCTL2_OFFSET 0x18 +#define NR5_TIMERA_TACCR2_OFFSET 0x1C +#define NR5_TIMERA_TAIV_OFFSET 0x20 + +/* Timer 1 address definitions */ + +#ifdef CONFIG_NR5_TIMER1 +#define NR5_TIMER1_TACTL_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACTL_OFFSET) +#define NR5_TIMER1_TAR_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TAR_OFFSET) +#define NR5_TIMER1_TACCTL0_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACCTL0_OFFSET) +#define NR5_TIMER1_TACCR0_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACCR0_OFFSET) +#define NR5_TIMER1_TACCTL1_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACCTL1_OFFSET) +#define NR5_TIMER1_TACCR1_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACCR1_OFFSET) +#define NR5_TIMER1_TACCTL2_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACCTL2_OFFSET) +#define NR5_TIMER1_TACCR2_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TACCR2_OFFSET) +#define NR5_TIMER1_TAIV_OFFSET (NR5_TIMER1_BASE+NR5_TIMERA_TAIV_OFFSET) +#endif + +/* Timer 2 address definitions */ + +#ifdef CONFIG_NR5_TIMER2 +#define NR5_TIMER2_TACTL_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACTL_OFFSET) +#define NR5_TIMER2_TAR_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TAR_OFFSET) +#define NR5_TIMER2_TACCTL0_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACCTL0_OFFSET) +#define NR5_TIMER2_TACCR0_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACCR0_OFFSET) +#define NR5_TIMER2_TACCTL1_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACCTL1_OFFSET) +#define NR5_TIMER2_TACCR1_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACCR1_OFFSET) +#define NR5_TIMER2_TACCTL2_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACCTL2_OFFSET) +#define NR5_TIMER2_TACCR2_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TACCR2_OFFSET) +#define NR5_TIMER2_TAIV_OFFSET (NR5_TIMER2_BASE+NR5_TIMERA_TAIV_OFFSET) +#endif + +/* Timer 3 address definitions */ + +#ifdef CONFIG_NR5_TIMER3 +#define NR5_TIMER3_TACTL_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACTL_OFFSET) +#define NR5_TIMER3_TAR_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TAR_OFFSET) +#define NR5_TIMER3_TACCTL0_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACCTL0_OFFSET) +#define NR5_TIMER3_TACCR0_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACCR0_OFFSET) +#define NR5_TIMER3_TACCTL1_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACCTL1_OFFSET) +#define NR5_TIMER3_TACCR1_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACCR1_OFFSET) +#define NR5_TIMER3_TACCTL2_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACCTL2_OFFSET) +#define NR5_TIMER3_TACCR2_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TACCR2_OFFSET) +#define NR5_TIMER3_TAIV_OFFSET (NR5_TIMER3_BASE+NR5_TIMERA_TAIV_OFFSET) +#endif + +/* Timer 4 address definitions */ + +#ifdef CONFIG_NR5_TIMER4 +#define NR5_TIMER4_TACTL_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACTL_OFFSET) +#define NR5_TIMER4_TAR_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TAR_OFFSET) +#define NR5_TIMER4_TACCTL0_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACCTL0_OFFSET) +#define NR5_TIMER4_TACCR0_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACCR0_OFFSET) +#define NR5_TIMER4_TACCTL1_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACCTL1_OFFSET) +#define NR5_TIMER4_TACCR1_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACCR1_OFFSET) +#define NR5_TIMER4_TACCTL2_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACCTL2_OFFSET) +#define NR5_TIMER4_TACCR2_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TACCR2_OFFSET) +#define NR5_TIMER4_TAIV_OFFSET (NR5_TIMER4_BASE+NR5_TIMERA_TAIV_OFFSET) +#endif + +/* Timer 5 address definitions */ + +#ifdef CONFIG_NR5_TIMER5 +#define NR5_TIMER5_TACTL_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACTL_OFFSET) +#define NR5_TIMER5_TAR_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TAR_OFFSET) +#define NR5_TIMER5_TACCTL0_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACCTL0_OFFSET) +#define NR5_TIMER5_TACCR0_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACCR0_OFFSET) +#define NR5_TIMER5_TACCTL1_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACCTL1_OFFSET) +#define NR5_TIMER5_TACCR1_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACCR1_OFFSET) +#define NR5_TIMER5_TACCTL2_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACCTL2_OFFSET) +#define NR5_TIMER5_TACCR2_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TACCR2_OFFSET) +#define NR5_TIMER5_TAIV_OFFSET (NR5_TIMER5_BASE+NR5_TIMERA_TAIV_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************************/ + +/* Control register TACTL Bit definitions */ + +#define TIMERA_TACTL_TAIFG (1 << 0) /* Bit 0: Interrupt Pending Flag */ +#define TIMERA_TACTL_TAIE (1 << 1) /* Bit 1: Interrupt Enable */ +#define TIMERA_TACTL_TACLR (1 << 2) /* Bit 2: TAR counter clear */ +#define TIMERA_TACTL_MC_SHIFT 4 /* Bits 4-5: Mode Control */ +# define TIMERA_TACTL_MC_MASK (3 << TIMERA_TACTL_MC_SHIFT) +# define TIMERA_TACTL_STOP (0 << TIMERA_TACTL_MC_SHIFT) +# define TIMERA_TACTL_UP (1 << TIMERA_TACTL_MC_SHIFT) +# define TIMERA_TACTL_CONTINUOUS (2 << TIMERA_TACTL_MC_SHIFT) +# define TIMERA_TACTL_UPDOWN (3 << TIMERA_TACTL_MC_SHIFT) +#define TIMERA_TACTL_ID_SHIFT 6 /* Bits 6-7: Input Divider */ +# define TIMERA_TACTL_DIV_1 (0 << TIMERA_TACTL_ID_SHIFT) +# define TIMERA_TACTL_DIV_2 (1 << TIMERA_TACTL_ID_SHIFT) +# define TIMERA_TACTL_DIV_4 (2 << TIMERA_TACTL_ID_SHIFT) +# define TIMERA_TACTL_DIV_8 (3 << TIMERA_TACTL_ID_SHIFT) +#define TIMERA_TACTL_TASSEL_SHIFT 8 /* Bits 8-9: Clock Source Select */ +# define TIMERA_TACTL_MED_CLOCK (0 << TIMERA_TACTL_TASSEL_SHIFT) +# define TIMERA_TACTL_SLOW_CLOCK (1 << TIMERA_TACTL_TASSEL_SHIFT) +# define TIMERA_TACTL_SYS_CLOCK (2 << TIMERA_TACTL_TASSEL_SHIFT) +# define TIMERA_TACTL_EXT_CLOCK (3 << TIMERA_TACTL_TASSEL_SHIFT) +#define TIMERA_TACTL_TAPRE_SHIFT 10 /* Bits 10-15: Clock Prescaler */ +#define TIMERA_TACTL_TAPRE_MASK 0x3F +# define TIMERA_TACTL_TAPRE(x) (((x) & TIMERA_TACTL_TAPRE_MASK) << TIMERA_TACTL_TAPRE_SHIFT) + +/* Capture / Compare register bit definitions */ + +#define TIMERA_TACCTL_CCIFG (1 << 0) /* Bit 0: Capture/compare interrupt Flag */ +#define TIMERA_TACCTL_COV (1 << 1) /* Bit 1: Capture overflow */ +#define TIMERA_TACCTL_OUTVAL (1 << 2) /* Bit 2: Output value */ +#define TIMERA_TACCTL_CCI (1 << 3) /* Bit 3: Capture/compare input value */ +#define TIMERA_TACCTL_CCIE (1 << 4) /* Bit 4: Capture/Compare interrupt Enable */ +#define TIMERA_TACCTL_OUTMOD_SHIFT 5 /* Bits 5-7: Output Mode */ +# define TIMERA_TACCTL_OUT (0 << TIMERA_TACCTL_OUTMOD_SHIFT) +# define TIMERA_TACCTL_SET (1 << TIMERA_TACCTL_OUTMOD_SHIFT) +# define TIMERA_TACCTL_TOGGLE_RESET (2 << TIMERA_TACCTL_OUTMOD_SHIFT) +# define TIMERA_TACCTL_SET_RESET (3 << TIMERA_TACCTL_OUTMOD_SHIFT) +# define TIMERA_TACCTL_TOGGLE (4 << TIMERA_TACCTL_OUTMOD_SHIFT) +# define TIMERA_TACCTL_RESET (5 << TIMERA_TACCTL_OUTMOD_SHIFT) +# define TIMERA_TACCTL_TOGGLE_SET (6 << TIMERA_TACCTL_OUTMOD_SHIFT) +# define TIMERA_TACCTL_RESET_SET (7 << TIMERA_TACCTL_OUTMOD_SHIFT) +#define TIMERA_TACCTL_CAP (1 << 8) /* Bit 8: Capture mode select */ +#define TIMERA_TACCTL_SCCI (1 << 10) /* Bit 10: Synchronized capture input */ +#define TIMERA_TACCTL_SCS (1 << 11) /* Bit 11: Syncronize capture source */ +#define TIMERA_TACCTL_CCIS_SHIFT 12 /* Bits 12-13: Capture Input Select */ +# define TIMERA_TACCTL_CCIS_CCIA (0 << TIMERA_TACCTL_CCIS_SHIFT) +# define TIMERA_TACCTL_CCIS_CCIB (1 << TIMERA_TACCTL_CCIS_SHIFT) +# define TIMERA_TACCTL_CCIS_GND (2 << TIMERA_TACCTL_CCIS_SHIFT) +# define TIMERA_TACCTL_CCIS_VCC (3 << TIMERA_TACCTL_CCIS_SHIFT) +#define TIMERA_TACCTL_CM_SHIFT 14 /* Bits 14-15: Capture Mode */ +# define TIMERA_TACCTL_CM_NO_CAPTURE (0 << TIMERA_TACCTL_SM_SHIFT) +# define TIMERA_TACCTL_CM_RISING (1 << TIMERA_TACCTL_SM_SHIFT) +# define TIMERA_TACCTL_CM_FALLING (2 << TIMERA_TACCTL_SM_SHIFT) +# define TIMERA_TACCTL_CM_BOTH (3 << TIMERA_TACCTL_SM_SHIFT) + +/* Interrupt Vector Register */ + +#define TIMERA_TAIV_TAIV_SHIFT 1 /* Bits 1-3: Interrupt Source */ +# define TIMERA_TAIV_TACCR1 (1 << TIMERA_TAIV_TAIV_SHIFT) +# define TIMERA_TAIV_TACCR2 (2 << TIMERA_TAIV_TAIV_SHIFT) +# define TIMERA_TAIV_TAIFG (5 << TIMERA_TAIV_TAIV_SHIFT) + +#endif /* _ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_TIMERA_H */ + diff --git a/arch/risc-v/src/nr5m100/chip/nr5m1xx_uart.h b/arch/risc-v/src/nr5m100/chip/nr5m1xx_uart.h new file mode 100644 index 0000000000..5a790782e9 --- /dev/null +++ b/arch/risc-v/src/nr5m100/chip/nr5m1xx_uart.h @@ -0,0 +1,75 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/chip/nr5_uart.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_UART_H +#define ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_UART_H + +/* The UART in NR5M100 is a very small (i.e. dumb) peripheral. It + * only supports the most common mode ever used: + * + * 8 Data bits + * 1 Stop bit + * No parity. + * + * It has a programmable baud rate and RX / TX interrupt capability + * and that's about it. The primary goal for the UART is to provide a + * debug console to the part. + */ + +#define NR5_UART_BAUD_RATE_OFFSET 0x000 +#define NR5_UART_TX_REG_OFFSET 0x004 +#define NR5_UART_RX_REG_OFFSET 0x008 +#define NR5_UART_STATUS_REG_OFFSET 0x00C +#define NR5_UART_CTRL_REG_OFFSET 0x010 + +#ifdef CONFIG_NR5_UART1 +# define NR5_UART1_BAUD_RATE_REG (NR5_UART1_BASE+NR5_UART_BAUD_RATE_OFFSET) +# define NR5_UART1_TX_REG (NR5_UART1_BASE+NR5_UART_TX_REG_OFFSET) +# define NR5_UART1_RX_REG (NR5_UART1_BASE+NR5_UART_RX_REG_OFFSET) +# define NR5_UART1_STATUS_REG (NR5_UART1_BASE+NR5_UART_STATUS_REG_OFFSET) +# define NR5_UART1_CTRL_REG (NR5_UART1_BASE+NR5_UART_CTRL_REG_OFFSET) +#endif + +/* Status Register Bit definitions */ + +#define NR5_UART_STATUS_TX_EMPTY 0x01 +#define NR5_UART_STATUS_RX_AVAIL 0x02 +#define NR5_UART_STATUS_RX_OVERRUN 0x04 +#define NR5_UART_RX_IRQ_PENDING 0x08 +#define NR5_UART_TX_IRQ_PENDING 0x10 + +/* Control Register Bit definitions */ + +#define NR5_UART_CTRL_ENABLE_RX_IRQ 0x01 +#define NR5_UART_CTRL_ENABLE_TX_IRQ 0x02 + +#endif /* _ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_UART_H */ diff --git a/arch/risc-v/src/nr5m100/nr5.h b/arch/risc-v/src/nr5m100/nr5.h new file mode 100644 index 0000000000..f6038a7620 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5.h @@ -0,0 +1,68 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5.h + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Authors: Uros Platise + * Gregory Nutt + * Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_NR5M100_NR5_H +#define __ARCH_RISCV_SRC_NR5M100_NR5_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include +#include +#include + +#include +#include "up_internal.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Peripherals **********************************************************************/ + +#include "chip.h" +#include "nr5_csr.h" +#include "nr5_lowputc.h" +#include "nr5_timer.h" +#include "nr5_uart.h" + +#endif /* __ARCH_RISCV_SRC_NR5_NR5_H */ + diff --git a/arch/risc-v/src/nr5m100/nr5_allocateheap.c b/arch/risc-v/src/nr5m100/nr5_allocateheap.c new file mode 100644 index 0000000000..3467cee05c --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_allocateheap.c @@ -0,0 +1,63 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_allocateheap.c + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include "nr5.h" + +/************************************************************************************ + * Private Types + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: up_addregion + * + * Descripton: + * RAM may be added in non-contiguous chunks. This routine adds all chunks + * that may be used for heap. + * + ************************************************************************************/ + +void up_addregion(void) +{ +} + diff --git a/arch/risc-v/src/nr5m100/nr5_arch.c b/arch/risc-v/src/nr5m100/nr5_arch.c new file mode 100644 index 0000000000..0bc09cacb5 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_arch.c @@ -0,0 +1,43 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_arch.c + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#include +#include +#include "nr5.h" + +void up_puts(const char *p) +{ + while (*p != 0) + up_lowputc(*(p++)); + up_lowputc('\n'); +} + diff --git a/arch/risc-v/src/nr5m100/nr5_config.h b/arch/risc-v/src/nr5m100/nr5_config.h new file mode 100644 index 0000000000..36b20d5914 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_config.h @@ -0,0 +1,97 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_config.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_NR5M100_NR5_CONFIG_H +#define __ARCH_RISCV_SRC_NR5M100_NR5_CONFIG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* UARTs ****************************************************************************/ + +/* Are any UARTs enabled? */ + +#undef HAVE_UART_DEVICE +#if defined(CONFIG_NR5_UART1) || defined(CONFIG_NR5_UART2) +# define HAVE_UART_DEVICE 1 +#endif + +/* Is there a serial console? There should be no more than one defined. It + * could be on any UARTn, n=1,.. CHIP_NUARTS + */ + +#if defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_NR5_UART1) +# undef CONFIG_UART2_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_NR5_UART2) +# undef CONFIG_UART1_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#else +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef HAVE_SERIAL_CONSOLE +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_RISCV_SRC_NR5M100_NR5_CONFIG_H */ diff --git a/arch/risc-v/src/nr5m100/nr5_csr.S b/arch/risc-v/src/nr5m100/nr5_csr.S new file mode 100644 index 0000000000..d586270e09 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_csr.S @@ -0,0 +1,289 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_csr.c + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/* + * Provide C level access function to asm only CSR registers + */ + +#define ENABLE_QREGS +#include "nr5_custom_ops.h" +#include "nr5_csr.h" + + .global up_getmisa + .global up_getarchid + .global up_getimpid + .global up_getvendorid + .global up_gethartid + .global up_getepicprimask + .global up_setepicprimask + .global up_setepicstat + .global up_setsystick + .global up_setpri1bit + .global up_clearpri1bit + .global up_setpri2bit + .global up_clearpri2bit + .global up_setpri3bit + .global up_clearpri3bit + .global up_setirqmaskbit + .global up_clearirqmaskbit + .global up_disableints + .global up_enableints + .global up_getq0 + .global up_getq1 + .global up_getq2 + .global up_setq0 + .global up_setq1 + .global up_setq2 + .global up_lsbenc + + .section .text + +/**************************************************************************** + * Returns the Read Only RV32IM Machine ISA (capabilities) + ****************************************************************************/ + +up_getmisa: + csrr a0, CSR_MISA + ret + +/**************************************************************************** + * Returns the Read Only RV32IM Vendor ID + ****************************************************************************/ + +up_getvendorid: + csrr a0, CSR_MVENDORID + ret + +/**************************************************************************** + * Returns the Read Only RV32IM ARCH ID + ****************************************************************************/ + +up_getarchid: + csrr a0, CSR_MARCHID + ret + +/**************************************************************************** + * Returns the Read Only RV32IM IMP ID + ****************************************************************************/ + +up_getimpid: + csrr a0, CSR_MIMPID + ret + +/**************************************************************************** + * Returns the Read Only RV32IM HART ID + ****************************************************************************/ + +up_gethartid: + csrr a0, CSR_MHARTID + ret + +/**************************************************************************** + * Returns the NR5M100 specific Embedded Priority Interrupt Controller (EPIC) + * IRQ MASK register + ****************************************************************************/ + +up_getepicmask: + csrr a0, NR5_EPIC_IRQ_MASK + ret + +/**************************************************************************** + * Returns the NR5M100 specific EPIC IRQ Priority register + ****************************************************************************/ + +up_getepicpri: + csrr a0, NR5_EPIC_PRIMASK + ret + +/**************************************************************************** + * Sets the NR5M100 specific EPIC IRQ Priority register + ****************************************************************************/ + +up_setepicpri: + csrrw a0, NR5_EPIC_PRIMASK, a0 + ret + +/**************************************************************************** + * Sets the NR5M100 specific SYSTICK control register + ****************************************************************************/ + +up_setsystick: + csrw NR5_MSYSTICK_REG, a0 + ret + +/**************************************************************************** + * Sets bits in the NR5M100 specific PRI1 mask control register + ****************************************************************************/ + +up_setpri1bit: + csrrs a0, NR5_EPIC_PRI1, a0 + ret + +/**************************************************************************** + * Clears bits in the NR5M100 specific PRI1 mask control register + ****************************************************************************/ + +up_clearpri1bit: + csrrc a0, NR5_EPIC_PRI1, a0 + ret + +/**************************************************************************** + * Sets bits in the NR5M100 specific PRI2 mask control register + ****************************************************************************/ + +up_setpri2bit: + csrrs a0, NR5_EPIC_PRI2, a0 + ret + +/**************************************************************************** + * Clears bits in the NR5M100 specific PRI2 mask control register + ****************************************************************************/ + +up_clearpri2bit: + csrrc a0, NR5_EPIC_PRI2, a0 + ret + +/**************************************************************************** + * Sets bits in the NR5M100 specific PRI3 mask control register + ****************************************************************************/ + +up_setpri3bit: + csrrs a0, NR5_EPIC_PRI3, a0 + ret + +/**************************************************************************** + * Clears bits in the NR5M100 specific PRI3 mask control register + ****************************************************************************/ + +up_clearpri3bit: + csrrc a0, NR5_EPIC_PRI3, a0 + ret + +/**************************************************************************** + * Sets bits in the NR5M100 specific IRQ mask control register + ****************************************************************************/ + +up_setirqmaskbit: + csrrs a0, NR5_EPIC_IRQ_MASK, a0 + ret + +/**************************************************************************** + * Clears bits in the NR5M100 specific IRQ mask control register + ****************************************************************************/ + +up_clearirqmaskbit: + csrrc a0, NR5_EPIC_IRQ_MASK, a0 + ret + +/**************************************************************************** + * Disables global interrupts in NR5M100 specific IRQ PRI control register + ****************************************************************************/ + +up_disableints: + csrrc a0, NR5_EPIC_PRIMASK, 1 + ret + +/**************************************************************************** + * Enables global interrupts in NR5M100 specific IRQ PRI control register + ****************************************************************************/ + +up_enableints: + csrrs a0, NR5_EPIC_PRIMASK, 1 + ret + +/**************************************************************************** + * Reads NR5M100 specific Q0 register (used for interrupt processing) + ****************************************************************************/ + +up_getq0: + getq a0, q0 + ret + +/**************************************************************************** + * Reads NR5M100 specific Q1 register (used for interrupt processing) + ****************************************************************************/ + +up_getq1: + getq a0, q1 + ret + +/**************************************************************************** + * Reads NR5M100 specific Q2 register (used for interrupt processing) + ****************************************************************************/ + +up_getq2: + getq a0, q2 + ret + +/**************************************************************************** + * Sets NR5M100 specific Q0 register (used for interrupt processing) + ****************************************************************************/ + +up_setq0: + setq q0, a0 + ret + +/**************************************************************************** + * Sets NR5M100 specific Q1 register (used for interrupt processing) + ****************************************************************************/ + +up_setq1: + setq q1, a0 + ret + +/**************************************************************************** + * Sets NR5M100 specific Q2 register (used for interrupt processing) + ****************************************************************************/ + +up_setq2: + setq q2, a0 + ret + +/**************************************************************************** + * Calls the NR5M100 specific LSBENC opcode. This opcode will find the + * first least significant non-zero bit in a0 and return it's ordinal value. + ****************************************************************************/ + +up_lsbenc: + lsbenc a0, a0 + ret + +/**************************************************************************** + * Modeline to set vim formatting options for ASM file. For this to work, + * you must enable moeline processing in your ~/.vimrc file with: + * + * ~/.vimrc: + * set modeline + * + * vim: noet:ts=4:sw=4 + ****************************************************************************/ + diff --git a/arch/risc-v/src/nr5m100/nr5_csr.h b/arch/risc-v/src/nr5m100/nr5_csr.h new file mode 100644 index 0000000000..025a509886 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_csr.h @@ -0,0 +1,94 @@ +/************************************************************************************ + * arch/riscv/src/nr5/nr5_csr.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/* CSR Definitions */ + +#ifndef __ARCH_RISCV_SRC_NR5_NR5_CSR_H +#define __ARCH_RISCV_SRC_NR5_NR5_CSR_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#include +#endif + +#if defined(CONFIG_NR5_NR5M1XX) +# include "chip/nr5m1xx_epic.h" +#endif + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#define NR5_EPIC_IRQ_MASK 0x7E0 +#define NR5_EPIC_PRI1 0x7E1 +#define NR5_EPIC_PRI2 0x7E2 +#define NR5_EPIC_PRI3 0x7E3 +#define NR5_EPIC_PRIMASK 0x7E4 +#define NR5_MSYSTICK_REG 0x7E5 + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +void up_setsystick(uint32_t); + +void up_setpri1bit(uint32_t); +void up_setpri2bit(uint32_t); +void up_setpri3bit(uint32_t); + +void up_clearpri1bit(uint32_t); +void up_clearpri2bit(uint32_t); +void up_clearpri3bit(uint32_t); + +void up_setirqmaskbit(uint32_t); +void up_clearirqmaskbit(uint32_t); + +void up_disableints(void); +void up_enableints(void); + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_RISCV_SRC_NR5_NR5_CSR_H */ + diff --git a/arch/risc-v/src/nr5m100/nr5_custom_ops.h b/arch/risc-v/src/nr5m100/nr5_custom_ops.h new file mode 100644 index 0000000000..0c600eccf5 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_custom_ops.h @@ -0,0 +1,61 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_custom_ops.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define q0 0 +#define q1 1 +#define q2 2 +#define q3 3 + +/**************************************************************************** + * Assmebler Macros + ****************************************************************************/ + +.macro getq rd qs +custom0 \rd,\qs,0,0 +.endm + +.macro setq qd rs +custom0 \qd,\rs,0,1 +.endm + +.macro lsbenc rd rs +custom0 \rd,\rs,0,2 +.endm + +.macro timer rd rs +custom0 \rd,\rs,0,5 +.endm + diff --git a/arch/risc-v/src/nr5m100/nr5_head.S b/arch/risc-v/src/nr5m100/nr5_head.S new file mode 100644 index 0000000000..aa6eb23264 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_head.S @@ -0,0 +1,611 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_head.S + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#define ENABLE_QREGS + +#include "nr5_custom_ops.h" +#include "nr5_csr.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +#define NR5M100_STACK_BASE _ebss +#define NR5M100_STACK_TOP _ebss+CONFIG_IDLETHREAD_STACKSIZE-4 + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 +# define NR5M100_INTSTACK_BASE NR5M100_STACK_TOP +# define NR5M100_INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~3) +# define NR5M100_INTSTACK_TOP NR5M100_STACK_TOP+NR5M100_INTSTACK_SIZE +# define NR5M100_HEAP_BASE NR5M100_INTSTACK_TOP +#else +# define NR5M100_HEAP_BASE NR5M100_STACK_TOP +#endif + +/**************************************************************************** + * Public Symbols + ****************************************************************************/ + + .global irq_handler + +#ifdef CONFIG_RV32IM_HW_MULDIV + .global time_hard_mul + .global hard_mul + .global hard_mulh + .global hard_mulhsu + .global hard_div + .global hard_divu + .global hard_rem + .global hard_remu + .global hard_mulhu +#endif + + .global g_idle_topstack + + /* Imported symbols */ + + .extern __reset_vec + .extern __trap_vec + .extern __stack_start + .global os_start + +#ifndef CONFIG_LIB_NEWLIB + + .section .text + .global __start + +__start: + + /* Set IRQ regs address */ + + lui x1, %hi(irq_regs) + addi x1, x1, %lo(irq_regs) + lui x2, %hi(irq_regs_addr) + addi x2, x2, %lo(irq_regs_addr) + sw x1, 0(x2) + + /* Set IRQ stack address */ + + lui x1, %hi(irq_stack) + addi x1, x1, %lo(irq_stack) + lui x2, %hi(irq_stack_addr) + addi x2, x2, %lo(irq_stack_addr) + sw x1, 0(x2) + + /* Zero out the registers */ + + addi x1, zero, 0 + addi x2, zero, 0 + addi x3, zero, 0 + addi x4, zero, 0 + addi x5, zero, 0 + addi x6, zero, 0 + addi x7, zero, 0 + addi x8, zero, 0 + addi x9, zero, 0 + addi x10, zero, 0 + addi x11, zero, 0 + addi x12, zero, 0 + addi x13, zero, 0 + addi x14, zero, 0 + addi x15, zero, 0 + addi x16, zero, 0 + addi x17, zero, 0 + addi x18, zero, 0 + addi x19, zero, 0 + addi x20, zero, 0 + addi x21, zero, 0 + addi x22, zero, 0 + addi x23, zero, 0 + addi x24, zero, 0 + addi x25, zero, 0 + addi x26, zero, 0 + addi x27, zero, 0 + addi x28, zero, 0 + addi x29, zero, 0 + addi x30, zero, 0 + addi x31, zero, 0 + + /* Set stack pointer */ + + lui sp,%hi(__stack_start) + + /* Initialize global pointer */ + +1: auipc gp, %pcrel_hi(_gp) + addi gp, gp, %pcrel_lo(1b) + + /* Initialize the Machine Trap Vector */ + + lui t0, %hi(__trap_vec) + addi t0, t0, %lo(__trap_vec) + csrw CSR_MTVEC, t0 + + /* Initialize the Machine Interrupt Table Vector */ + lui t0, %hi(__reset_vec) + csrw CSR_MIVEC, t0 + + /* clear the bss segment */ + + la t0, _fbss + la t1, _end +1: +#ifdef __riscv64 + sd zero,0(t0) + addi t0, t0, 8 +#else + sw zero,0(t0) + addi t0, t0, 4 +#endif + bltu t0, t1, 1b + + /* Call the nr5_init_array routine to initialize C variables */ + + //call __nr5_init_array + + lw a0, 0(sp) # a0 = argc + addi a1, sp, _RISCV_SZPTR/8 # a1 = argv + li a2, 0 # a2 = envp = NULL + + /* Now jump to the main nr5_init routine to setup interrupts, etc. */ + + la t0, __nr5_init + jr t0 + + /* We shouldn't return from __nr5_init */ + + .global _init + .global _fini +_init: +_fini: + # These don't have to do anything since we use init_array/fini_array. + ret + +#endif + +/* +============================================================== +IRQ Handler routine .. save all regs and call the C handler. +============================================================== +*/ + +irq_handler: + + /* save All registers */ + +#ifdef ENABLE_QREGS + + /* Save x1,x2 in the spare q2,q3 registers */ + + setq q2, x1 + setq q3, x2 + + /* Get pointer to our IRQ REGS save region in RAM */ + + lui x2, %hi(irq_regs_addr) + addi x2, x2, %lo(irq_regs_addr) + lw x1, 0(x2) + addi x1, x1, 32*4 + sw x1, 0(x2) + addi x1, x1, -32*4 + + /* Save x3 and x4 to hold regs / stack pointer */ + + sw x3, 3*4(x1) + sw x4, 4*4(x1) + addi x4, x1, 0 + + /* Save the IRQ pending mask to the irq_regs area */ + + getq x2, q1 + sw x2, 33*4(x1) + + /* Save the x1 register (which is in q2) */ + + getq x2, q2 + sw x2, 1*4(x1) + + /* Save the x2 register (which is in q3) */ + + getq x2, q3 + sw x2, 2*4(x1) + + /* Get a stack region in irq stack space */ + + lui x3, %hi(irq_stack_addr) + addi x3, x3, %lo(irq_stack_addr) + lw x2, 0(x3) + addi x2, x2, -128*4 + sw x2, 0(x3) + addi x3, x2, 128*4 + + /* Save the return PC. After the getq of q0, + * the higher priority interrupts will be enabled + * as we are done using the shared resources (Qregs). + */ + + getq x2, q0 + sw x2, 0*4(x1) + + sw x5, 5*4(x1) + sw x6, 6*4(x1) + sw x7, 7*4(x1) + sw x8, 8*4(x1) + sw x9, 9*4(x1) + sw x10, 10*4(x1) + sw x11, 11*4(x1) + sw x12, 12*4(x1) + sw x13, 13*4(x1) + sw x14, 14*4(x1) + sw x15, 15*4(x1) + sw x16, 16*4(x1) + sw x17, 17*4(x1) + sw x18, 18*4(x1) + sw x19, 19*4(x1) + sw x20, 20*4(x1) + sw x21, 21*4(x1) + sw x22, 22*4(x1) + sw x23, 23*4(x1) + sw x24, 24*4(x1) + sw x25, 25*4(x1) + sw x26, 26*4(x1) + sw x27, 27*4(x1) + sw x28, 28*4(x1) + sw x29, 29*4(x1) + sw x30, 30*4(x1) + sw x31, 31*4(x1) + + /* Get the EPIC STATUS */ + + csrr t6, NR5_EPIC_PRIMASK + sw t6, 32*4(x1) + + /* Set ISR Stack pointer */ + + addi sp, x3, 0 # IRQ SP is in x3 from above + +#else // ENABLE_QREGS + + sw gp, 0*4+0x200(zero) + sw x1, 1*4+0x200(zero) + sw x2, 2*4+0x200(zero) + sw x3, 3*4+0x200(zero) + sw x4, 4*4+0x200(zero) + sw x5, 5*4+0x200(zero) + sw x6, 6*4+0x200(zero) + sw x7, 7*4+0x200(zero) + sw x8, 8*4+0x200(zero) + sw x9, 9*4+0x200(zero) + sw x10, 10*4+0x200(zero) + sw x11, 11*4+0x200(zero) + sw x12, 12*4+0x200(zero) + sw x13, 13*4+0x200(zero) + sw x14, 14*4+0x200(zero) + sw x15, 15*4+0x200(zero) + sw x16, 16*4+0x200(zero) + sw x17, 17*4+0x200(zero) + sw x18, 18*4+0x200(zero) + sw x19, 19*4+0x200(zero) + sw x20, 20*4+0x200(zero) + sw x21, 21*4+0x200(zero) + sw x22, 22*4+0x200(zero) + sw x23, 23*4+0x200(zero) + sw x24, 24*4+0x200(zero) + sw x25, 25*4+0x200(zero) + sw x26, 26*4+0x200(zero) + sw x27, 27*4+0x200(zero) + sw x28, 28*4+0x200(zero) + sw x29, 29*4+0x200(zero) + sw x30, 30*4+0x200(zero) + sw x31, 31*4+0x200(zero) + + /* Get the EPIC STATUS */ + + csrr t6, NR5_EPIC_PRIMASK + sw t6, 32*4+0x200(zero) + + /* Set ISR Stack pointer */ + + lui sp, %hi(irq_stack) + addi sp, sp, %lo(irq_stack) + +#endif // ENABLE_QREGS + + /* Set arg0 = address of regs */ + +#ifdef ENABLE_QREGS + addi a0, x4, 0 # REG addr in x4 from above +#else + lui a0, %hi(irq_regs) + addi a0, a0, %lo(irq_regs) +#endif + + /* Set arg1 = interrupt type */ + +#ifdef ENABLE_QREGS + lw a1, 33*4(x1) +#else + addi a1, tp, 0 +#endif + + /* call interrupt handler C function */ + + jal ra, irq_dispatch_all + + /* restore registers */ + +#ifdef ENABLE_QREGS + + /* new irq_regs address returned from C code in a0 */ + + addi x1, a0, 0 + + lw x3, 3*4(x1) + lw x4, 4*4(x1) + lw x5, 5*4(x1) + lw x6, 6*4(x1) + lw x7, 7*4(x1) + lw x8, 8*4(x1) + lw x9, 9*4(x1) + lw x10, 10*4(x1) + lw x11, 11*4(x1) + lw x12, 12*4(x1) + lw x13, 13*4(x1) + lw x14, 14*4(x1) + lw x15, 15*4(x1) + lw x16, 16*4(x1) + lw x17, 17*4(x1) + lw x18, 18*4(x1) + lw x19, 19*4(x1) + lw x20, 20*4(x1) + lw x21, 21*4(x1) + lw x22, 22*4(x1) + lw x23, 23*4(x1) + lw x24, 24*4(x1) + lw x25, 25*4(x1) + lw x26, 26*4(x1) + lw x27, 27*4(x1) + lw x28, 28*4(x1) + lw x29, 29*4(x1) + lw x30, 30*4(x1) + lw x31, 31*4(x1) + + /* Restore return PC to q0. This will cause the + * processor to enter a critical state where + * higher priority IRQs won't happen until after + * the mret, thus protecting our shared QREGS. + */ + + lw x2, 0*4(x1) + setq q0, x2 + + /* Restore EPIC STATUS (it may have changed) */ + + lw x2, 32*4(x1) + csrw NR5_EPIC_PRIMASK, x2 + + /* Restore the IRQ mask so the processor knows + * which interrupts to signal as handled + */ + + lw x2, 33*4(x1) + setq q1, x2 + + /* Put original x1 into q2 */ + + lw x2, 1*4(x1) + setq q2, x2 + + /* Put original x2 into q3 */ + + lw x2, 2*4(x1) + setq q3, x2 + + /* Deallocate the irq_stack space */ + + lui x2, %hi(irq_stack_addr) + addi x2, x2, %lo(irq_stack_addr) + lw x1, 0(x2) + addi x1, x1, 128*4 + sw x1, 0(x2) + + /* Deallocate the irq_regs space */ + + lui x2, %hi(irq_regs_addr) + addi x2, x2, %lo(irq_regs_addr) + lw x1, 0(x2) + addi x1, x1, -32*4 + sw x1, 0(x2) + + /* Now restore original x1,x2 from q2,q3 */ + + getq x1, q2 + getq x2, q3 + +#else // ENABLE_QREGS + + /* new irq_regs address returned from C code in a0 */ + + addi a1, zero, 0x200 + beq a0, a1, 1f + sbreak +1: + + lw gp, 0*4+0x200(zero) + lw x1, 1*4+0x200(zero) + lw x2, 2*4+0x200(zero) + // do not restore x3 (gp) + lw x4, 4*4+0x200(zero) + lw x5, 5*4+0x200(zero) + lw x6, 6*4+0x200(zero) + lw x7, 7*4+0x200(zero) + lw x8, 8*4+0x200(zero) + lw x9, 9*4+0x200(zero) + lw x10, 10*4+0x200(zero) + lw x11, 11*4+0x200(zero) + lw x12, 12*4+0x200(zero) + lw x13, 13*4+0x200(zero) + lw x14, 14*4+0x200(zero) + lw x15, 15*4+0x200(zero) + lw x16, 16*4+0x200(zero) + lw x17, 17*4+0x200(zero) + lw x18, 18*4+0x200(zero) + lw x19, 19*4+0x200(zero) + lw x20, 20*4+0x200(zero) + lw x21, 21*4+0x200(zero) + lw x22, 22*4+0x200(zero) + lw x23, 23*4+0x200(zero) + lw x24, 24*4+0x200(zero) + lw x25, 25*4+0x200(zero) + lw x26, 26*4+0x200(zero) + lw x27, 27*4+0x200(zero) + lw x28, 28*4+0x200(zero) + lw x29, 29*4+0x200(zero) + lw x30, 30*4+0x200(zero) + lw x31, 31*4+0x200(zero) + +#endif // ENABLE_QREGS + + /* Return from Machine Interrupt */ + + mret + +irq_regs: + /* registers are saved to this memory region during interrupt handling + * the program counter is saved as register 0 + */ + + .fill 34*5,4 + + /* stack for the interrupt handler */ + + .fill 128*5,4 +irq_stack: + +irq_regs_addr: + .fill 4,4 +irq_stack_addr: + .fill 4,4 + + +/**************************************************************************** + * Hard mul and div functions for multest. These are C interfaces to + * the MUL / DIV opcodes for performing HARD vs SOFT testing. + ****************************************************************************/ + +#ifdef CONFIG_RV32IM_HW_MULDIV + +/* Multiply, return lower 32 bits */ + +up_hard_mul: + mul a0, a0, a1 + ret + +/* Multiply, return upper 32 bits */ + +up_hard_mulh: + mulh a0, a0, a1 + ret + +/* Multiply unsigned */ + +up_hard_mulhsu: + mulhsu a0, a0, a1 + ret + +up_hard_mulhu: + mulhu a0, a0, a1 + ret + +/* Divide */ + +up_hard_div: + div a0, a0, a1 + ret + +/* Divide, return remainder */ + +up_hard_rem: + rem a0, a0, a1 + ret + +/* Divide, unsigned */ + +up_hard_divu: + divu a0, a0, a1 + ret + +/* Remainder, unsigned */ + +up_hard_remu: + remu a0, a0, a1 + ret + +/* Calculate number of clock cycles requried for MUL */ + +up_time_hard_mul: + rdcycle a3 + mul a0, a0, a1 + rdcycle a4 + sub a1, a4, a3 + sw a1,0(a2) + ret + +#endif + +/**************************************************************************** + * This global variable is unsigned int g_idle_topstack and is exported here only + * because of its coupling to idle thread stack. + ****************************************************************************/ + + .section .data + .type g_idle_topstack, object +g_idle_topstack: + .long NR5M100_HEAP_BASE + .size g_idle_topstack, .-g_idle_topstack + +/**************************************************************************** + * Modeline to set vim formatting options for ASM file. For this to work, + * you must enable moeline processing in your ~/.vimrc file with: + * + * ~/.vimrc: + * set modeline + * + * vim: noet:ts=4:sw=4 + ****************************************************************************/ diff --git a/arch/risc-v/src/nr5m100/nr5_init.c b/arch/risc-v/src/nr5m100/nr5_init.c new file mode 100644 index 0000000000..a296ad5a13 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_init.c @@ -0,0 +1,76 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_init.c + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include "nr5.h" + +/************************************************************************************ + * Private Types + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Function - Initialization + * + * Performs low level board initializaiton tasks. + ************************************************************************************/ + +void __nr5_init(void) +{ + /* Configure the UART so we can get debug output */ + + nr5_lowsetup(); + + /* Do board initialization */ + + nr5_boardinitialize(); + + /* Call os_start() */ + + os_start(); + + /* Shouldn't get here */ + + for (;;); +} + + diff --git a/arch/risc-v/src/nr5m100/nr5_irq.c b/arch/risc-v/src/nr5m100/nr5_irq.c new file mode 100644 index 0000000000..b0d1bfa756 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_irq.c @@ -0,0 +1,320 @@ +/**************************************************************************** + * arch/risc-v/src/nr5m100/nr5_irq.c + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "nr5.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uint32_t *g_current_regs; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: epic_dump + * + * Description: + * Dump the EPIC priority register settings + * + ****************************************************************************/ + +void epic_dump(void) +{ + uint32_t reg; + char str[40]; + + __asm__ volatile("csrr %0, 0x7e0" : "=r"(reg)); + sprintf(str, "IRQMASK = 0x%08X\r", (int) reg); + up_puts(str); + __asm__ volatile("csrr %0, 0x7e4" : "=r"(reg)); + sprintf(str, "IRQSTACK = 0x%08X\r", (int) reg); + up_puts(str); + __asm__ volatile("csrr %0, 0x7e1" : "=r"(reg)); + sprintf(str, "PRI1 = 0x%08X\r", (int) reg); + up_puts(str); + __asm__ volatile("csrr %0, 0x7e2" : "=r"(reg)); + sprintf(str, "PRI2 = 0x%08X\r", (int) reg); + up_puts(str); + __asm__ volatile("csrr %0, 0x7e3" : "=r"(reg)); + sprintf(str, "PRI3 = 0x%08X\r", (int) reg); + up_puts(str); + __asm__ volatile("csrr %0, 0x7e5" : "=r"(reg)); + sprintf(str, "SYSTICK = 0x%08X\r", (int) reg); + up_puts(str); +} + +/**************************************************************************** + * Name: nr5_trap + * + * Description: + * Handler for execptions. None are handled and all are fatal + * error conditions. The only advantage these provided over the default + * unexpected interrupt handler is that they provide a diagnostic output. + * + ****************************************************************************/ + +#define CONFIG_DEBUG + +int nr5_trap_handler(int irq, void *context) +{ + uint32_t sp; + + /* Print a PANIC message */ + + up_puts("PANIC!!! TRAP received\r\n"); + +#ifdef CONFIG_DEBUG + + /* restore the SP to that of the bad code */ + + sp = g_current_regs[2]; + __asm__ volatile ("addi x2, %0, 0" ::"r"(sp)); + + __asm__ volatile ("ebreak"); +#endif + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + uint32_t mask; + + /* Disable all interrupts */ + + mask = ~0; + __asm__ volatile("csrw %0, %1" :: "i"(NR5_EPIC_IRQ_MASK), "r"(mask)); + + /* Colorize the interrupt stack for debug purposes */ + +#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 + { + size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3); + up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size), + intstack_size); + } +#endif + + /* Set the location of the vector table */ + + /* Set all interrupts (and exceptions) to the default priority */ + +#ifdef NR5_EPIC_PRI_REG + __asm__ volatile (" \ + csrw %0, 0(zero) \ + csrw %1, 0(zero) \ + csrw %2, 0(zero) " :: + "i"(NR5_EPIC_PRI1_REG), "i"(NR5_EPIC_PRI2_REG), + "i"(NR5_EPIC_PRI3_REG) ); +#endif + + /* Initialize the IRQ stack to Pri level 5 with interrupts disabled */ + + mask = 0x05 << 2; + __asm__ volatile("csrw %0, %1" :: "i"(NR5_EPIC_PRIMASK), "r"(mask)); + + /* currents_regs is non-NULL only while processing an interrupt */ + + g_current_regs = NULL; + + /* Attach the Trap exception handler. */ + + irq_attach(NR5_IRQ_TRAP, nr5_trap_handler); + + /* Attach software interrupt handler */ + + irq_attach(NR5_IRQ_SOFTWARE, up_swint); + up_enable_irq(NR5_IRQ_SOFTWARE); + + /* Set the software interrupt priority higher */ + + up_setpri2bit(1 << NR5_IRQ_SOFTWARE); + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + + /* And finally, enable interrupts */ + + up_enable_irq(NR5_IRQ_TRAP); + +#endif + + /* Now enable Global Interrupts */ + + __asm__ volatile("csrrs a0, %0, 3" :: "i"(NR5_EPIC_PRIMASK)); + +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + up_setirqmaskbit(1 << irq); +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + up_clearirqmaskbit(1 << irq); +} + +/**************************************************************************** + * Name: up_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void up_ack_irq(int irq) +{ +} + +/**************************************************************************** + * Name: up_get_newintctx + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +uint32_t up_get_newintctx(void) +{ + int32_t regval; + + /* Set priority level 5, enabled upon return from interrupt */ + + regval = ((5 << 2) | 2) << 4; + + return regval; +} + +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int irq, int priority) +{ + return OK; +} +#endif + +/**************************************************************************** + * Name: irqsave + * + * Description: + * Disable IRQs while returning the previous IRQ state + * + ****************************************************************************/ + +irqstate_t up_irq_save(void) +{ + irqstate_t newIrqPri = (2 << 2) | 3; + irqstate_t oldIrqPri; + + /* Set the new IRQ Priority level to level 2, enabled. + * This will allow SW and DEBUG / TRAP interrupts to + * continue to fire, but no general purpose ints. + */ + + __asm__ volatile("csrrw %0, %1, %2" : "=r"(oldIrqPri) : + "i"(NR5_EPIC_PRIMASK), "r"(newIrqPri)); + + return oldIrqPri; +} + +/**************************************************************************** + * Name: irqrestore + * + * Description: + * Restore previous IRQ mask state + * + ****************************************************************************/ + +void up_irq_restore(irqstate_t pri) +{ + __asm__ volatile("csrw %0, %1" :: "i"(NR5_EPIC_PRIMASK), "r"(pri)); +} diff --git a/arch/risc-v/src/nr5m100/nr5_irq_dispatch.c b/arch/risc-v/src/nr5m100/nr5_irq_dispatch.c new file mode 100644 index 0000000000..5271d51abf --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_irq_dispatch.c @@ -0,0 +1,155 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_irq_dispatch.c + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "group/group.h" + +/**************************************************************************** + * Extern Functions + ****************************************************************************/ + +int up_lsbenc(int); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uint32_t * g_current_regs; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * irq_dispatch_all + ****************************************************************************/ + +uint32_t * irq_dispatch_all(uint32_t *regs, uint32_t irqmask) +{ + int next, mask; + mask = irqmask & 0xFFFF; + + board_autoled_on(LED_INIRQ); + +#ifdef CONFIG_SUPPRESS_INTERRUPTS + PANIC(); +#else + /* Current regs non-zero indicates that we are processing an interrupt; + * g_current_regs is also used to manage interrupt level context switches. + * + * Nested interrupts are not supported + */ + + DEBUGASSERT(g_current_regs == NULL); + g_current_regs = regs; + + /* Get ordinal index of interrupt number from mask */ + + next = up_lsbenc(mask); + while (next != -1) + { + /* Deliver the IRQ */ + + irq_dispatch(next, regs); + + /* Clear the IRQ from the mask */ + + mask &= !(1 << next); + next = up_lsbenc(mask); + +#if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV) + /* Check for a context switch. If a context switch occurred, then + * g_current_regs will have a different value than it did on entry. If an + * interrupt level context switch has occurred, then restore the floating + * point state and the establish the correct address environment before + * returning from the interrupt. + */ + if (regs != g_current_regs) + { +#ifdef CONFIG_ARCH_FPU + /* Restore floating point registers */ + + up_restorefpu((uint32_t *)g_current_regs); +#endif + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(NULL); +#endif + } +#endif + } + +#endif + + /* If a context switch occurred while processing the interrupt then + * g_current_regs may have change value. If we return any value different + * from the input regs, then the lower level will know that a context + * switch occurred during interrupt processing. + */ + + regs = (uint32_t *) g_current_regs; + g_current_regs = NULL; + + board_autoled_off(LED_INIRQ); + + /* Return the stack pointer */ + + return regs; +} + diff --git a/arch/risc-v/src/nr5m100/nr5_lowputc.c b/arch/risc-v/src/nr5m100/nr5_lowputc.c new file mode 100644 index 0000000000..87a665be51 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_lowputc.c @@ -0,0 +1,181 @@ +/************************************************************************** + * arch/risc-v/src/nr5m100/nr5_lowputc.c + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************/ + +/************************************************************************** + * Included Files + **************************************************************************/ + +#include + +#include + +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "nr5_config.h" +#include "nr5.h" + +/************************************************************************** + * Pre-processor Definitions + **************************************************************************/ + +/* Select UART parameters for the selected console */ + +#ifdef HAVE_SERIAL_CONSOLE +# if defined(CONFIG_UART1_SERIAL_CONSOLE) +# define NR5_CONSOLE_BASE NR5_UART1_BASE +# define NR5_CONSOLE_BAUD CONFIG_UART1_BAUD +# define NR5_CONSOLE_BITS CONFIG_UART1_BITS +# define NR5_CONSOLE_PARITY CONFIG_UART1_PARITY +# define NR5_CONSOLE_2STOP CONFIG_UART1_2STOP +# define NR5_CONSOLE_TX GPIO_UART1_TX +# define NR5_CONSOLE_RX GPIO_UART1_RX +# define HAVE_UART +# elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define NR5_CONSOLE_BASE NR5_UART1_BASE +# define NR5_CONSOLE_BAUD CONFIG_UART1_BAUD +# define NR5_CONSOLE_BITS CONFIG_UART1_BITS +# define NR5_CONSOLE_PARITY CONFIG_UART1_PARITY +# define NR5_CONSOLE_2STOP CONFIG_UART1_2STOP +# define NR5_CONSOLE_TX GPIO_UART1_TX +# define NR5_CONSOLE_RX GPIO_UART1_RX +# define HAVE_UART +# endif + + /* Calculate UART BAUD rate divider */ + +# if defined(CONFIG_NR5_NR5M1XX) + + /* Baud rate for standard UART: + * + * In case of oversampling by 16, the equation is: + * UARTDIV = fCK / 32 / baud + */ + +# define NR5_UARTDIV \ + ((NR5_HCLK_FREQUENCY >> 5) / NR5_CONSOLE_BAUD) + +# endif /* CONFIG_NR5_NR5M1XX */ +#endif /* HAVE_CONSOLE */ + +/************************************************************************** + * Private Types + **************************************************************************/ + +/************************************************************************** + * Private Function Prototypes + **************************************************************************/ + +/************************************************************************** + * Global Variables + **************************************************************************/ + +/************************************************************************** + * Private Variables + **************************************************************************/ + +/************************************************************************** + * Private Functions + **************************************************************************/ + +/************************************************************************** + * Public Functions + **************************************************************************/ + +/************************************************************************** + * Name: up_lowputc + * + * Description: + * Output one byte on the serial console + * + **************************************************************************/ + +void up_lowputc(char ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + /* Wait until the TX data register is empty */ + + while ((getreg32(NR5_CONSOLE_BASE + NR5_UART_STATUS_REG_OFFSET) & NR5_UART_STATUS_TX_EMPTY) == 0) + ; + + /* Then send the character */ + + putreg32((uint32_t)ch, NR5_CONSOLE_BASE + NR5_UART_TX_REG_OFFSET); + +#endif /* HAVE_CONSOLE */ +} + +/************************************************************************** + * Name: nr5_lowsetup + * + * Description: + * This performs basic initialization of the UART used for the serial + * console. Its purpose is to get the console output availabe as soon + * as possible. + * + **************************************************************************/ + +#if defined(CONFIG_NR5_NR5M1XX) + +void nr5_lowsetup(void) +{ +#if defined(HAVE_UART) + + /* Enable and configure the selected console device */ + +#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + + /* Configure the UART Baud Rate */ + + putreg32(NR5_UARTDIV, NR5_CONSOLE_BASE + NR5_UART_BAUD_RATE_OFFSET); + + /* Configure the RX interrupt */ + + putreg32(NR5_UART_CTRL_ENABLE_RX_IRQ, NR5_CONSOLE_BASE + NR5_UART_CTRL_REG_OFFSET); + +#endif /* HAVE_SERIAL_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ +#endif /* HAVE_UART */ +} + +#else +# error "Unsupported NR5 chip" +#endif diff --git a/arch/risc-v/src/nr5m100/nr5_lowputc.h b/arch/risc-v/src/nr5m100/nr5_lowputc.h new file mode 100644 index 0000000000..4ab7ce0837 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_lowputc.h @@ -0,0 +1,79 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_lowputc.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_NR5M100_NR5_LOWPUTC_H +#define __ARCH_RISCV_SRC_NR5M100_NR5_LOWPUTC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Name: nr5_lowsetup + * + * Description: + * Called at the very beginning of __nr5_init. Performs low level initialization + * of serial console. + * + ************************************************************************************/ + +EXTERN void nr5_lowsetup(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_NR5M100_NR5_LOWPUTC_H */ + diff --git a/arch/risc-v/src/nr5m100/nr5_memorymap.h b/arch/risc-v/src/nr5m100/nr5_memorymap.h new file mode 100644 index 0000000000..8ebcfedd68 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_memorymap.h @@ -0,0 +1,43 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_memorymap.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef _ARCH_RISCV_SRC_NR5M100_NR5_MEMORYMAP_H +#define _ARCH_RISCV_SRC_NR5M100_NR5_MEMORYMAP_H + +//#include + +#ifdef CONFIG_NR5_NR5MXXX +#include "chip/nr5m1xx_memorymap.h" +#endif + +#endif /* _ARCH_RISCV_SRC_NR5M100_NR5_MEMORYMAP_H */ + diff --git a/arch/risc-v/src/nr5m100/nr5_serial.c b/arch/risc-v/src/nr5m100/nr5_serial.c new file mode 100644 index 0000000000..44a4cd5d9f --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_serial.c @@ -0,0 +1,888 @@ +/**************************************************************************** + * arch/risc-v/src/nr5m100/nr5_serial.c + * + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "nr5_config.h" +#include "chip.h" +#include "nr5.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* If we are not using the serial driver for the console, then we still must + * provide some minimal implementation of up_putc. + */ + +#ifdef USE_SERIALDRIVER + +/* Which UART with be tty0/console and which tty1? The console will always + * be ttyS0. If there is no console then will use the lowest numbered UART. + */ + +#ifdef HAVE_SERIAL_CONSOLE +# if defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1 is console */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# undef TTYS1_DEV /* No ttyS1 */ +# define SERIAL_CONSOLE 1 +# else +# error "I'm confused... Do we have a serial console or not?" +# endif +#else +# undef CONSOLE_DEV /* No console */ +# undef CONFIG_UART1_SERIAL_CONSOLE +# if defined(CONFIG_NR5_UART1) +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# undef TTYS1_DEV /* No ttyS1 */ +# define SERIAL_CONSOLE 1 +# else +# undef TTYS0_DEV +# undef TTYS1_DEV +# endif +#endif + +/* Common initialization logic will not not know that the all of the UARTs + * have been disabled. So, as a result, we may still have to provide + * stub implementations of up_earlyserialinit(), up_serialinit(), and + * up_putc(). + */ + +#ifdef HAVE_UART_DEVICE + +/* These values describe the set of enabled interrupts */ + +#define IE_RX (1 << 0) +#define IE_TX (1 << 1) + +#define RX_ENABLED(im) (((im) & IE_RX) != 0) +#define TX_ENABLED(im) (((im) & IE_TX) != 0) + +#define ENABLE_RX(im) do { (im) |= IE_RX; } while (0) +#define ENABLE_TX(im) do { (im) |= IE_TX; } while (0) + +#define DISABLE_RX(im) do { (im) &= ~IE_RX; } while (0) +#define DISABLE_TX(im) do { (im) &= ~IE_TX; } while (0) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct up_dev_s +{ + uintptr_t uartbase; /* Base address of UART registers */ + uint32_t baud; /* Configured baud */ + uint8_t irqrx; /* RX IRQ associated with this UART (for enable) */ + uint8_t irqtx; /* TX IRQ associated with this UART (for enable) */ + uint8_t irqprio; /* Interrupt priority */ + uint8_t im; /* Interrupt mask state */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Low-level helpers */ + +static inline uint32_t up_serialin(struct up_dev_s *priv, int offset); +static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value); +static void up_restoreuartint(struct uart_dev_s *dev, uint8_t im); +static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im); + +/* Serial driver methods */ + +static int up_setup(struct uart_dev_s *dev); +static void up_shutdown(struct uart_dev_s *dev); +static int up_attach(struct uart_dev_s *dev); +static void up_detach(struct uart_dev_s *dev); +static int up_interrupt(int irq, void *context); +static int up_ioctl(struct file *filep, int cmd, unsigned long arg); +static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static void up_rxint(struct uart_dev_s *dev, bool enable); +static bool up_rxavailable(struct uart_dev_s *dev); +static void up_send(struct uart_dev_s *dev, int ch); +static void up_txint(struct uart_dev_s *dev, bool enable); +static bool up_txready(struct uart_dev_s *dev); +static bool up_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = up_setup, + .shutdown = up_shutdown, + .attach = up_attach, + .detach = up_detach, + .ioctl = up_ioctl, + .receive = up_receive, + .rxint = up_rxint, + .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = up_send, + .txint = up_txint, + .txready = up_txready, + .txempty = up_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_NR5_UART1 +static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; +#endif + +/* This describes the state of the NR5 UART1 port. */ + +#ifdef CONFIG_NR5_UART1 +#ifndef CONFIG_NR5_UART1PRIO +# define CONFIG_NR5_UART1PRIO 4 +#endif + +static struct up_dev_s g_uart1priv = +{ + .uartbase = NR5_UART1_BASE, + .baud = CONFIG_UART1_BAUD, + .irqrx = NR5_IRQ_UART1_RX, + .irqtx = NR5_IRQ_UART1_TX, + .irqprio = CONFIG_NR5_UART1PRIO, +}; + +static uart_dev_t g_uart1port = +{ +#if SERIAL_CONSOLE == 1 + .isconsole = 1, +#endif + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_serialin + ****************************************************************************/ + +static inline uint32_t up_serialin(struct up_dev_s *priv, int offset) +{ + return getreg32(priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_serialout + ****************************************************************************/ + +static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value) +{ + putreg32(value, priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_restoreuartint + ****************************************************************************/ + +static void up_restoreuartint(struct uart_dev_s *dev, uint8_t im) +{ + irqstate_t flags; + + /* Re-enable/re-disable interrupts corresponding to the state of bits in im */ + + flags = enter_critical_section(); + up_rxint(dev, RX_ENABLED(im)); + up_txint(dev, TX_ENABLED(im)); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_disableuartint + ****************************************************************************/ + +static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + irqstate_t flags; + + flags = enter_critical_section(); + if (im) + { + *im = priv->im; + } + up_restoreuartint(dev, 0); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_setup + * + * Description: + * Configure the UART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev) +{ +#ifndef CONFIG_SUPPRESS_UART_CONFIG +// struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Configure the UART as an RS-232 UART */ + + //pic32mx_uartconfigure(priv->uartbase, priv->baud, priv->parity, + // priv->bits, priv->stopbits2); +#endif + +#ifdef CONFIG_ARCH_IRQPRIO + /* Set up the interrupt priority */ + + up_prioritize_irq(priv->irq, priv->irqprio); +#endif + + return OK; +} + +/**************************************************************************** + * Name: up_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void up_shutdown(struct uart_dev_s *dev) +{ + //struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Disable interrupts */ + + up_disableuartint(dev, NULL); + + /* Reset hardware and disable Rx and Tx */ + + //nr5_uartreset(priv->uartbase); +} + +/**************************************************************************** + * Name: up_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled by the attach method (unless the + * hardware supports multiple levels of interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() methods are called. + * + ****************************************************************************/ + +static int up_attach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Initialize interrupt generation on the peripheral */ + + up_serialout(priv, NR5_UART_CTRL_REG_OFFSET, IE_RX | IE_TX); + irq_attach(priv->irqrx, up_interrupt); + irq_attach(priv->irqtx, up_interrupt); + + /* Indicate no interrupts active in EPIC */ + + priv->im = 0; + + return OK; +} + +/**************************************************************************** + * Name: up_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception + * is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void up_detach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Disable interrupts */ + + up_disableuartint(dev, NULL); + + /* Disable interrupt generation on the peripheral */ + + up_serialout(priv, NR5_UART_CTRL_REG_OFFSET, 0); + + /* Detach from the interrupt */ + + irq_detach(priv->irqrx); + irq_detach(priv->irqtx); +} + +/**************************************************************************** + * Name: up_interrupt + * + * Description: + * This is the UART interrupt handler. It will be invoked when an + * interrupt received on the 'irq' It should call uart_transmitchars or + * uart_receivechar to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'irq' number into the + * approprite uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int up_interrupt(int irq, void *context) +{ + struct uart_dev_s *dev = NULL; + struct up_dev_s *priv; + int passes; + uint32_t status; + bool handled; + +#ifdef CONFIG_NR5_UART1 + if (g_uart1priv.irqrx == irq || g_uart1priv.irqtx == irq) + { + dev = &g_uart1port; + } + else +#endif +#ifdef CONFIG_NR5_UART2 + if (g_uart2priv.irqrx == irq || g_uart2priv.irqtx == irq) + { + dev = &g_uart2port; + } + else +#endif + { + PANIC(); + } + priv = (struct up_dev_s *)dev->priv; + DEBUGASSERT(priv); + + /* Loop until there are no characters to be transferred or, + * until we have been looping for a long time. + */ + + handled = true; + for (passes = 0; passes < 256 && handled; passes++) + { + handled = false; + + status = up_serialin(priv, NR5_UART_STATUS_REG_OFFSET); + + /* Handle incoming, received bytes. The RX FIFO is configured to + * interrupt when the RX FIFO is 75% full (that is 6 of 8 for 8-deep + * FIFOs or 3 of 4 for 4-deep FIFOS. + */ + + if (status & NR5_UART_RX_IRQ_PENDING) + { + /* Process incoming bytes */ + + uart_recvchars(dev); + handled = true; + } + + /* Handle outgoing, transmit bytes The RT FIFO is configured to + * interrupt only when the TX FIFO is empty. There are not many + * options on trigger TX interrupts. The FIFO-not-full might generate + * better through-put but with a higher interrupt rate. FIFO-empty should + * lower the interrupt rate but result in a burstier output. If + * you change this, You will probably need to change the conditions for + * clearing the pending TX interrupt below. + * + * NOTE: When I tried using the FIFO-not-full interrupt trigger, I + * had either lost interrupts, or else a window where I might get + * infinite interrupts. The problem is that there is a race condition + * with trying to clearing the pending interrupt based on the FIFO + * full condition. + */ + + if (status & NR5_UART_TX_IRQ_PENDING) + { + /* Process outgoing bytes */ + + uart_xmitchars(dev); + handled = true; + } + } + + return OK; +} + +/**************************************************************************** + * Name: up_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int up_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#ifdef CONFIG_SERIAL_TERMIOS + struct inode *inode; + struct uart_dev_s *dev; + struct up_dev_s *priv; + int ret = OK; + + DEBUGASSERT(filep, filep->f_inode); + inode = filep->f_inode; + dev = inode->i_private; + + DEBUGASSERT(dev, dev->priv); + priv = (struct up_dev_s *)dev->priv; + + switch (cmd) + { + case xxx: /* Add commands here */ + break; + + case TCGETS: + { + struct termios *termiosp = (struct termios *)arg; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* TODO: Other termios fields are not yet returned. + * Note that only cfsetospeed is not necessary because we have + * knowledge that only one speed is supported. + */ + + cfsetispeed(termiosp, priv->baud); + } + break; + + case TCSETS: + { + struct termios *termiosp = (struct termios *)arg; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* TODO: Handle other termios settings. + * Note that only cfgetispeed is used besued we have knowledge + * that only one speed is supported. + */ + + priv->baud = cfgetispeed(termiosp); + //pic32mx_uartconfigure(priv->uartbase, priv->baud, priv->parity, + // priv->bits, priv->stopbits2); + } + break; + + default: + ret = -ENOTTY; + break; + } + + return ret; +#else + return -ENOTTY; +#endif +} + +/**************************************************************************** + * Name: up_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int up_receive(struct uart_dev_s *dev, uint32_t *status) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Return status information */ + + if (status) + { + *status = 0; /* We are not yet tracking serial errors */ + } + + /* Then return the actual received byte */ + + return (int)(up_serialin(priv, NR5_UART_RX_REG_OFFSET)); +} + +/**************************************************************************** + * Name: up_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void up_rxint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + irqstate_t flags; + uint8_t im; + + flags = enter_critical_section(); + im = priv->im; + if (enable) + { + /* Receive an interrupt when their is anything in the Rx data register (or an Rx + * timeout occurs). + */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + up_enable_irq(priv->irqrx); + ENABLE_RX(im); +#endif + } + else + { + up_disable_irq(priv->irqrx); + DISABLE_RX(im); + } + priv->im = im; + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +static bool up_rxavailable(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Return true is data is available in the receive data buffer */ + + return (up_serialin(priv, NR5_UART_STATUS_REG_OFFSET) & NR5_UART_STATUS_RX_AVAIL) != 0; +} + +/**************************************************************************** + * Name: up_send + * + * Description: + * This method will send one byte on the UART. + * + ****************************************************************************/ + +static void up_send(struct uart_dev_s *dev, int ch) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + up_serialout(priv, NR5_UART_TX_REG_OFFSET, (uint32_t)ch); +} + +/**************************************************************************** + * Name: up_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void up_txint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + irqstate_t flags; + uint8_t im; + + flags = enter_critical_section(); + im = priv->im; + if (enable) + { + /* Enable the TX interrupt */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + up_enable_irq(priv->irqtx); + ENABLE_TX(im); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); +#endif + } + else + { + /* Disable the TX interrupt */ + + up_disable_irq(priv->irqtx); + DISABLE_TX(im); + } + + priv->im = im; + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_txready + * + * Description: + * Return true if the tranmsit data register is empty + * + ****************************************************************************/ + +static bool up_txready(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Return TRUE if the Transmit buffer register is not full */ + + return (up_serialin(priv, NR5_UART_STATUS_REG_OFFSET) & NR5_UART_STATUS_TX_EMPTY) != 0; +} + +/**************************************************************************** + * Name: up_txempty + * + * Description: + * Return true if the tranmsit data register is empty + * + ****************************************************************************/ + +static bool up_txempty(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Return TRUE if the Transmit shift register is empty */ + + return (up_serialin(priv, NR5_UART_STATUS_REG_OFFSET) & NR5_UART_STATUS_TX_EMPTY) != 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before up_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in up_consoleinit() and main clock iniialization + * performed in up_clkinitialize(). + * + ****************************************************************************/ + +void up_earlyserialinit(void) +{ + /* Disable interrupts from all UARTS. The console is enabled in + * nr5_consoleinit(). + */ + + up_disableuartint(&TTYS0_DEV, NULL); +#ifdef TTYS1_DEV + up_disableuartint(&TTYS1_DEV, NULL); +#endif + + /* Configuration whichever one is the console */ + +#ifdef HAVE_SERIAL_CONSOLE + CONSOLE_DEV.isconsole = true; + up_setup(&CONSOLE_DEV); +#endif +} + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that up_earlyserialinit was called previously. + * + ****************************************************************************/ + +void up_serialinit(void) +{ + /* Register the console */ + +#ifdef HAVE_SERIAL_CONSOLE + (void)uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* Register all UARTs */ + + (void)uart_register("/dev/ttyS0", &TTYS0_DEV); +#ifdef TTYS1_DEV + (void)uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + struct uart_dev_s *dev = (struct uart_dev_s *)&CONSOLE_DEV; + uint8_t imr; + + up_disableuartint(dev, &imr); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); + up_restoreuartint(dev, imr); +#endif + return ch; +} + +/**************************************************************************** + * Name: up_earlyserialinit, up_serialinit, and up_putc + * + * Description: + * stubs that may be needed. These stubs would be used if all UARTs are + * disabled. In that case, the logic in common/up_initialize() is not + * smart enough to know that there are not UARTs and will still expect + * these interfaces to be provided. + * + ****************************************************************************/ +#else /* HAVE_UART_DEVICE */ +void up_earlyserialinit(void) +{ +} + +void up_serialinit(void) +{ +} + +int up_putc(int ch) +{ + return ch; +} + +#endif /* HAVE_UART_DEVICE */ +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); +#endif + return ch; +} + +#endif /* USE_SERIALDRIVER */ + diff --git a/arch/risc-v/src/nr5m100/nr5_timer.c b/arch/risc-v/src/nr5m100/nr5_timer.c new file mode 100644 index 0000000000..132cb9e984 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_timer.c @@ -0,0 +1,512 @@ +/************************************************************************************ + * arm/risc-v/src/nr5m100/nr5_timer.c + * + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include +#include +#include +#include +#include + +#include "chip.h" +#include "up_internal.h" +#include "up_arch.h" + +#include "nr5.h" + +/************************************************************************************ + * Private Types + ************************************************************************************/ +/* Configuration ********************************************************************/ + +/* This module then only compiles if there are enabled timers that are not intended for + * some other purpose. + */ + +#if defined(CONFIG_NR5_TIMER0) || defined(CONFIG_NR5_TIMER1) || defined(CONFIG_NR5_TIMER2) || \ + defined(CONFIG_NR5_TIMER3) || defined(CONFIG_NR5_TIMER4) || defined(CONFIG_NR5_TIMER5) + +/************************************************************************************ + * Private Types + ************************************************************************************/ + +/* Timer Device Structure */ + +struct nr5_timer_priv_s +{ + struct nr5_timer_ops_s *ops; + nr5_timer_mode_t mode; + uint32_t base; /* TIMERn base address */ +}; + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/* Get a 16-bit register value by offset */ + +static inline uint16_t nr5_getreg16(FAR struct nr5_timer_dev_s *dev, + uint8_t offset) +{ + uint16_t *p16 = (uint16_t *) (((struct nr5_timer_priv_s *)dev)->base + offset); + return *p16; +} + +/* Put a 16-bit register value by offset */ + +static inline void nr5_putreg16(FAR struct nr5_timer_dev_s *dev, uint8_t offset, + uint16_t value) +{ + uint16_t *p16 = (uint16_t *) (((struct nr5_timer_priv_s *)dev)->base + offset); + *p16 = value; +} + +/* Modify a 16-bit register value by offset */ + +static inline void nr5_modifyreg16(FAR struct nr5_timer_dev_s *dev, + uint8_t offset, uint16_t clearbits, + uint16_t setbits) +{ + modifyreg16(((struct nr5_timer_priv_s *)dev)->base + offset, clearbits, setbits); +} + +/* Clear the TAR counter */ + +static void nr5_timer_clear_counter(FAR struct nr5_timer_dev_s *dev) +{ + uint16_t val = nr5_getreg16(dev, NR5_TIMERA_TACTL_OFFSET); + val |= TIMERA_TACTL_TACLR; + nr5_putreg16(dev, NR5_TIMERA_TACTL_OFFSET, val); +} + +static void nr5_timer_enable(FAR struct nr5_timer_dev_s *dev) +{ + uint16_t val = nr5_getreg16(dev, NR5_BTIM_CR1_OFFSET); + nr5_timer_clear_counter(dev); + val |= ATIM_CR1_CEN; + nr5_putreg16(dev, NR5_BTIM_CR1_OFFSET, val); +} + +/* Disable the timer by setting the mode to STOP */ + +static void nr5_timer_disable(FAR struct nr5_timer_dev_s *dev) +{ + uint16_t val = nr5_getreg16(dev, NR5_TIMERA_TACTL_OFFSET); + val &= ~TIMERA_TACTL_MC_MASK; + nr5_putreg16(dev, NR5_TIMERA_TACTL_OFFSET, val); +} + +/* Reset timer into system default state, but do not affect output/input pins */ + +static void nr5_timer_reset(FAR struct nr5_timer_dev_s *dev) +{ + ((struct nr5_timer_priv_s *)dev)->mode = NR5_TIMER_MODE_DISABLED; + nr5_timer_disable(dev); +} + +/************************************************************************************ + * Basic Functions + ************************************************************************************/ + +static int nr5_timer_setclock(FAR struct nr5_timer_dev_s *dev, uint32_t freq) +{ + int prescaler; + + ASSERT(dev); + + /* Disable Timer? */ + + if (freq == 0) + { + nr5_timer_disable(dev); + return 0; + } + +#if NR5_NATIM > 0 + if (((struct nr5_timer_priv_s *)dev)->base == NR5_TIM1_BASE || + ((struct nr5_timer_priv_s *)dev)->base == NR5_TIM8_BASE) + { + prescaler = NR5_TIM18_FREQUENCY / freq; + } + else +#endif + { + prescaler = NR5_TIM27_FREQUENCY / freq; + } + + /* We need to decrement value for '1', but only, if we are allowed to + * not to cause underflow. Check for overflow. + */ + + if (prescaler > 0) + { + prescaler--; + } + + if (prescaler > 0xffff) + { + prescaler = 0xffff; + } + + nr5_putreg16(dev, NR5_BTIM_PSC_OFFSET, prescaler); + nr5_timer_enable(dev); + + return prescaler; +} + +static void nr5_timer_setperiod(FAR struct nr5_timer_dev_s *dev, + uint32_t period) +{ + ASSERT(dev); + nr5_putreg32(dev, NR5_BTIM_ARR_OFFSET, period); +} + +static int nr5_timer_setisr(FAR struct nr5_timer_dev_s *dev, + int (*handler)(int irq, void *context), + int source) +{ + int vectorno; + + ASSERT(dev); + ASSERT(source == 0); + + switch (((struct nr5_timer_priv_s *)dev)->base) + { +#ifdef CONFIG_NR5_TIM2 + case NR5_TIM2_BASE: + vectorno = NR5_IRQ_TIM2; + break; +#endif +#ifdef CONFIG_NR5_TIM3 + case NR5_TIM3_BASE: + vectorno = NR5_IRQ_TIM3; + break; +#endif +#ifdef CONFIG_NR5_TIM4 + case NR5_TIM4_BASE: + vectorno = NR5_IRQ_TIM4; + break; +#endif +#ifdef CONFIG_NR5_TIM5 + case NR5_TIM5_BASE: + vectorno = NR5_IRQ_TIM5; + break; +#endif +#if NR5_NBTIM > 0 +#ifdef CONFIG_NR5_TIM6 + case NR5_TIM6_BASE: + vectorno = NR5_IRQ_TIM6; + break; +#endif +#endif +#if NR5_NBTIM > 1 +#ifdef CONFIG_NR5_TIM7 + case NR5_TIM7_BASE: + vectorno = NR5_IRQ_TIM7; + break; +#endif +#endif +#if NR5_NATIM > 0 + /* TODO: add support for multiple sources and callbacks */ + +#ifdef CONFIG_NR5_TIM1 + case NR5_TIM1_BASE: + vectorno = NR5_IRQ_TIM1UP; + break; +#endif +#ifdef CONFIG_NR5_TIM8 + case NR5_TIM8_BASE: + vectorno = NR5_IRQ_TIM8UP; + break; +#endif +#endif + default: + return ERROR; + } + + /* Disable interrupt when callback is removed */ + + if (!handler) + { + up_disable_irq(vectorno); + irq_detach(vectorno); + return OK; + } + + /* Otherwise set callback and enable interrupt */ + + irq_attach(vectorno, handler); + up_enable_irq(vectorno); + +#ifdef CONFIG_ARCH_IRQPRIO + /* Set the interrupt priority */ + + up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT); +#endif + + return OK; +} + +static void nr5_timer_enableint(FAR struct nr5_timer_dev_s *dev, int source) +{ + ASSERT(dev); + nr5_modifyreg16(dev, NR5_BTIM_DIER_OFFSET, 0, ATIM_DIER_UIE); +} + +static void nr5_timer_disableint(FAR struct nr5_timer_dev_s *dev, int source) +{ + ASSERT(dev); + nr5_modifyreg16(dev, NR5_BTIM_DIER_OFFSET, ATIM_DIER_UIE, 0); +} + +static void nr5_timer_ackint(FAR struct nr5_timer_dev_s *dev, int source) +{ + nr5_putreg16(dev, NR5_BTIM_SR_OFFSET, ~ATIM_SR_UIF); +} + +/************************************************************************************ + * General Functions + ************************************************************************************/ + +static int nr5_timer_setmode(FAR struct nr5_timer_dev_s *dev, nr5_timer_mode_t mode) +{ + uint16_t val = ATIM_CR1_CEN | ATIM_CR1_ARPE; + + ASSERT(dev); + + /* Decode operational modes */ + + switch (mode & NR5_TIMER_MODE_MASK) + { + case NR5_TIMER_MODE_DISABLED: + val = 0; + break; + + case NR5_TIMER_MODE_DOWN: + val |= ATIM_CR1_DIR; + + case NR5_TIMER_MODE_UP: + break; + + case NR5_TIMER_MODE_UPDOWN: + val |= ATIM_CR1_CENTER1; + // Our default: Interrupts are generated on compare, when counting down + break; + + case NR5_TIMER_MODE_PULSE: + val |= ATIM_CR1_OPM; + break; + + default: return ERROR; + } + + nr5_timer_clear_counter(dev); + nr5_putreg16(dev, NR5_BTIM_CR1_OFFSET, val); + + return OK; +} + +/************************************************************************************ + * Device Structures, Instantiation + ************************************************************************************/ + +struct nr5_timer_ops_s nr5_timer_ops = +{ + .setmode = &nr5_timer_setmode, + .setclock = &nr5_timer_setclock, + .setperiod = &nr5_timer_setperiod, + .setisr = &nr5_timer_setisr, + .enableint = &nr5_timer_enableint, + .disableint = &nr5_timer_disableint, + .ackint = &nr5_timer_ackint +}; + +#ifdef CONFIG_NR5_TIMER1 +struct nr5_timer_priv_s nr5_timer1_priv = +{ + .ops = &nr5_timer_ops, + .mode = NR5_TIMER_MODE_UNUSED, + .base = NR5_TIMER1_BASE, +}; +#endif + +#ifdef CONFIG_NR5_TIMER2 +struct nr5_timer_priv_s nr5_timer2_priv = +{ + .ops = &nr5_timer_ops, + .mode = NR5_TIMER_MODE_UNUSED, + .base = NR5_TIMER2_BASE, +}; +#endif + +#ifdef CONFIG_NR5_TIMER3 +struct nr5_timer_priv_s nr5_timer3_priv = +{ + .ops = &nr5_timer_ops, + .mode = NR5_TIMER_MODE_UNUSED, + .base = NR5_TIMER3_BASE, +}; +#endif + +#ifdef CONFIG_NR5_TIMER4 +struct nr5_timer_priv_s nr5_timer4_priv = +{ + .ops = &nr5_timer_ops, + .mode = NR5_TIMER_MODE_UNUSED, + .base = NR5_TIMER4_BASE, +}; +#endif + +#ifdef CONFIG_NR5_TIMER5 +struct nr5_timer_priv_s nr5_timer5_priv = +{ + .ops = &nr5_timer_ops, + .mode = NR5_TIMER_MODE_UNUSED, + .base = NR5_TIMER5_BASE, +}; +#endif + +/************************************************************************************ + * Public Function - Initialization + ************************************************************************************/ + +FAR struct nr5_timer_dev_s *nr5_timer_init(int timer) +{ + struct nr5_timer_dev_s *dev = NULL; + + /* Get structure pointer */ + + switch (timer) + { +#ifdef CONFIG_NR5_TIMER1 + case 1: + dev = (struct nr5_timer_dev_s *)&nr5_timer1_priv; + break; +#endif +#ifdef CONFIG_NR5_TIMER2 + case 2: + dev = (struct nr5_timer_dev_s *)&nr5_timer2_priv; + break; +#endif +#ifdef CONFIG_NR5_TIMER3 + case 3: + dev = (struct nr5_timer_dev_s *)&nr5_timer3_priv; + break; +#endif +#ifdef CONFIG_NR5_TIMER4 + case 4: + dev = (struct nr5_timer_dev_s *)&nr5_timer4_priv; + break; +#endif +#ifdef CONFIG_NR5_TIMER5 + case 5: + dev = (struct nr5_timer_dev_s *)&nr5_timer5_priv; + break; +#endif + + default: + return NULL; + } + + /* Is device already allocated */ + + if (((struct nr5_timer_priv_s *)dev)->mode != NR5_TIMER_MODE_UNUSED) + { + return NULL; + } + + nr5_timer_reset(dev); + + return dev; +} + +/* TODO: Detach interrupts, and close down all TIM Channels */ + +int nr5_timer_deinit(FAR struct nr5_timer_dev_s * dev) +{ + ASSERT(dev); + + /* Set timer mode to STOP */ + + switch (((struct nr5_timer_priv_s *)dev)->base) + { +#if NR5_NATIM > 0 +#ifdef CONFIG_NR5_TIM1 + case NR5_TIMER1_BASE: + modifyreg32(NR5_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); + break; +#endif +#ifdef CONFIG_NR5_TIM2 + case NR5_TIMER2_BASE: + modifyreg32(NR5_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); + break; +#endif +#ifdef CONFIG_NR5_TIM3 + case NR5_TIMER3_BASE: + modifyreg32(NR5_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); + break; +#endif +#ifdef CONFIG_NR5_TIM4 + case NR5_TIMER4_BASE: + modifyreg32(NR5_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); + break; +#endif +#ifdef CONFIG_NR5_TIM5 + case NR5_TIMER5_BASE: + modifyreg32(NR5_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); + break; +#endif +#endif + + default: + return ERROR; + } + + /* Mark it as free */ + + ((struct nr5_timer_priv_s *)dev)->mode = NR5_TIMER_MODE_UNUSED; + + return OK; +} + +#endif /* defined(CONFIG_NR5_TIM1 || ... || TIM8) */ diff --git a/arch/risc-v/src/nr5m100/nr5_timer.h b/arch/risc-v/src/nr5m100/nr5_timer.h new file mode 100644 index 0000000000..b1c76cc911 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_timer.h @@ -0,0 +1,168 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_timer.h + * + * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_NR5M100_NR5_TIMER_H +#define __ARCH_RISCV_SRC_NR5M100_NR5_TIMER_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "chip/nr5m1xx_timer.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Helpers **************************************************************************/ + +#define NR5_TIMER_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define NR5_TIMER_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define NR5_TIMER_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define NR5_TIMER_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define NR5_TIMER_SETISR(d,hnd,s) ((d)->ops->setisr(d,hnd,s)) +#define NR5_TIMER_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define NR5_TIMER_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define NR5_TIMER_ACKINT(d,s) ((d)->ops->ackint(d,s)) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* Timer Modes of Operation */ + +typedef enum +{ + NR5_TIMER_MODE_UNUSED = -1, + + /* One of the following */ + + NR5_TIMER_MODE_DISABLED = 0x0000, + NR5_TIMER_MODE_UP = 0x0001, + NR5_TIMER_MODE_CONTINUOUS = 0x0002, + NR5_TIMER_MODE_UPDOWN = 0x0003, + + /* One of the following */ + + NR5_TIM_MODE_CK_SLOW = 0x0000, + NR5_TIM_MODE_CK_MED = 0x0010, + NR5_TIM_MODE_CK_SYS = 0x0020, + NR5_TIM_MODE_CK_EXT = 0x0030, + +} nr5_timer_mode_t; + +/* Timer Operations */ + +struct nr5_timer_dev_s; + +struct nr5_timer_ops_s +{ + /* Basic Timer Operations */ + + int (*setmode)(FAR struct nr5_timer_dev_s *dev, nr5_timer_mode_t mode); + int (*setclock)(FAR struct nr5_timer_dev_s *dev, uint32_t freq); + void (*setperiod)(FAR struct nr5_timer_dev_s *dev, uint32_t period); + + /* Timer Interrupt Operations */ + + int (*setisr)(FAR struct nr5_timer_dev_s *dev, int (*handler)(int irq, void *context), int source); + void (*enableint)(FAR struct nr5_timer_dev_s *dev, int source); + void (*disableint)(FAR struct nr5_timer_dev_s *dev, int source); + void (*ackint)(FAR struct nr5_timer_dev_s *dev, int source); +}; + +/* Timer Device Structure */ + +struct nr5_timer_dev_s +{ + struct nr5_timer_ops_s *ops; +}; + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/* Power-up timer and get its structure */ + +FAR struct nr5_timer_dev_s *nr5_timer_init(int timer); + +/* Power-down timer, mark it as unused */ + +int nr5_timer_deinit(FAR struct nr5_timer_dev_s * dev); + +/**************************************************************************** + * Name: nr5_timer_initialize + * + * Description: + * Bind the configuration timer to a timer lower half instance and + * register the timer drivers at 'devpath' + * + * Input Parameters: + * devpath - The full path to the timer device. This should be of the form /dev/timer0 + * timer - the timer number. + * + * Returned Values: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_TIMER +int nr5_timer_initialize(FAR const char *devpath, int timer); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_NR5M100_NR5_TIMER_H */ + diff --git a/arch/risc-v/src/nr5m100/nr5_timerisr.c b/arch/risc-v/src/nr5m100/nr5_timerisr.c new file mode 100644 index 0000000000..5406b0f851 --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_timerisr.c @@ -0,0 +1,159 @@ +/**************************************************************************** + * arch/risc-v/src/nr5m100/nr5_timerisr.c + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include "up_arch.h" + +#include "nr5.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The desired timer interrupt frequency is provided by the definition + * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of + * system clock ticks per second. That value is a user configurable setting + * that defaults to 100 (100 ticks per second = 10 MS interval). + * + * The RCC feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK) + * divided by 8. The SysTick can work either with this clock or with the + * Cortex clock (HCLK), configurable in the SysTick Control and Status + * register. + */ + +#ifdef CONFIG_NR5_SYSTICK_SCLK +# define SYSTICK_RELOAD ((NR5_SCLK_FREQUENCY / CLOCKS_PER_SEC) - 1) +#else +# define SYSTICK_RELOAD ((NR5_HCLK_FREQUENCY / CLOCKS_PER_SEC) - 1) +#endif + +/* The size of the reload field is 30 bits. Verify that the reload value + * will fit in the reload register. + */ + +#if SYSTICK_RELOAD > 0x3fffffff +# error SYSTICK_RELOAD exceeds the range of the RELOAD register +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +static uint64_t g_systick = 0; + +int up_timerisr(int irq, void *context) +{ + /* Process timer interrupt */ + + sched_process_timer(); + return 0; +} + +/**************************************************************************** + * Function: up_get_systick + * + * Description: + * Returns the current value of systick. + * + ****************************************************************************/ + +uint64_t up_get_systick(void) +{ + return g_systick; +} + +/**************************************************************************** + * Function: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + /* Set the SysTick interrupt to the default priority */ + + up_clearpri1bit(NR5_IRQ_SYSTICK); + up_clearpri2bit(NR5_IRQ_SYSTICK); + up_clearpri3bit(NR5_IRQ_SYSTICK); + + /* Attach the timer interrupt vector */ + + (void)irq_attach(NR5_IRQ_SYSTICK, up_timerisr); + + /* Configure and enable SysTick to interrupt at the requested rate */ + + up_setsystick(0x80000000 | SYSTICK_RELOAD); + + /* And enable the timer interrupt */ + + up_enable_irq(NR5_IRQ_SYSTICK); +} + diff --git a/arch/risc-v/src/nr5m100/nr5_uart.c b/arch/risc-v/src/nr5m100/nr5_uart.c new file mode 100644 index 0000000000..4497e70d3e --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_uart.c @@ -0,0 +1,254 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_uart.c + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#include +#include +#include + +#include "nr5.h" + +#define MAKE_UINT32(a,b,c,d) (((a) << 24) | ((b) << 16) | ((c) << 8) | d) + +struct nr5_uart_buffer_s +{ + uint16_t head; + uint16_t tail; + uint16_t size; + char * buffer; +}; + +struct nr5_uart_regs_s +{ + uint32_t* pBaud; // Data status port + uint32_t* pStat; // Data status port + uint8_t* pTx; // Data TX port + uint8_t* pRx; // Data RX port + uint32_t* pIntCtrl; // Interrupt enable control + int rx_irq; // IRQ number + int tx_irq; // IRQ number +}; + +struct nr5_uart_s +{ + volatile struct nr5_uart_regs_s * regs; + struct nr5_uart_buffer_s * tx_buf; + struct nr5_uart_buffer_s * rx_buf; +}; + +/* +============================================================================== +Static global pointers to access the hardware +============================================================================== +*/ + +#ifdef CONFIG_NR5_HAVE_UART1 +static char g_uart1_rx_buf[CONFIG_NR5_UART_RX_BUF_SIZE]; +static char g_uart1_tx_buf[CONFIG_NR5_UART_TX_BUF_SIZE]; + +static struct nr5_uart_buffer_s g_nr5_uart1_rx_buf = +{ + .head = 0, + .tail = 0, + .size = CONFIG_NR5_UART_RX_BUF_SIZE, + .buffer = g_uart1_rx_buf, +}; + +static struct nr5_uart_buffer_s g_nr5_uart1_tx_buf = +{ + .head = 0, + .tail = 0, + .size = CONFIG_NR5_UART_TX_BUF_SIZE, + .buffer = g_uart1_tx_buf, +}; + +static volatile struct nr5_uart_regs_s g_nr5_uart1_regs = +{ + .pBaud = (uint32_t *) NR5_UART1_BAUD_RATE_REG, + .pStat = (uint32_t *) NR5_UART1_STATUS_REG, + .pRx = (uint8_t *) NR5_UART1_RX_REG, + .pTx = (uint8_t *) NR5_UART1_TX_REG, + .pIntCtrl = (uint32_t *) NR5_UART1_CTRL_REG, + .rx_irq = NR5_IRQ_UART1_RX, + .tx_irq = NR5_IRQ_UART1_TX, +}; + +static struct nr5_uart_s g_nr5_uart1 = +{ + .regs = &g_nr5_uart1_regs, + .rx_buf = &g_nr5_uart1_rx_buf, + .tx_buf = &g_nr5_uart1_tx_buf, +}; +#endif + +/* +============================================================================== +ISR for NanoRisc5 UART RX availalbe. +============================================================================== +*/ +int nr5_uart_rx_isr(int irq_num, void *context) +{ + struct nr5_uart_s *dev = NULL; + char rxdata; + +#ifdef CONFIG_NR5_HAVE_UART1 + if (irq_num == g_nr5_uart1_regs.rx_irq) + { + dev = &g_nr5_uart1; + } +#endif + + /* Process the data */ + + if (dev != NULL) + { + /* Read the RX byte */ + + rxdata = *dev->regs->pRx; + *dev->regs->pTx = rxdata; + + dev->rx_buf->buffer[dev->rx_buf->head++] = rxdata; + if (dev->rx_buf->head == dev->rx_buf->size) + dev->rx_buf->head = 0; + } + + return 0; +} + +/* +============================================================================== +Routine to initialize the HAL layer. Must be called prior to any other +HAL function. +============================================================================== +*/ +void nr5_uart_init(int uart) +{ + volatile struct nr5_uart_s *dev = NULL; + uint32_t cmpval = MAKE_UINT32('F', 'P', 'G', 'A'); + + switch (uart) + { +#ifdef CONFIG_NR5_HAVE_UART1 + case 1: + dev = &g_nr5_uart1; +#endif + } + + // If a device was selected above, then initilize it + // + if (dev != NULL) + { + /* Attache the ISR and enable the IRQ with the EPIC */ + + //irq_attach(dev->regs->rx_irq, &nr5_uart_rx_isr); + //up_enable_irq(dev->regs->rx_irq); + + // Set the baud rate + + if (up_getimpid() == cmpval) + { + *dev->regs->pBaud = 0x0d; + } + + /* Now enable the RX IRQ in the UART peripheral */ + + //*dev->regs->pIntCtrl = NR5_UART_CTRL_ENABLE_RX_IRQ; + } +} + +/* +============================================================================== +Routine to get RX byte from console UART +============================================================================== +*/ +uint8_t nr5_uart_get_rx() +{ + uint8_t rxdata = 0; + + up_disableints(); + if (g_nr5_uart1.rx_buf->head != g_nr5_uart1.rx_buf->tail) + { + struct nr5_uart_buffer_s *pBuf = g_nr5_uart1.rx_buf; + + rxdata = pBuf->buffer[pBuf->tail++]; + if (pBuf->tail == pBuf->size) + pBuf->tail = 0; + } + up_enableints(); + return rxdata; +} + +/* +============================================================================== +Routine to test if RX byte available at console UART +============================================================================== +*/ +int nr5_uart_test_rx_avail() +{ + struct nr5_uart_buffer_s *pBuf = g_nr5_uart1.rx_buf; + int avail; + + up_disableints(); + avail= !(pBuf->head == pBuf->tail); + up_enableints(); + + /* If no RX data available then halt the processor until an interrupt */ + if (!avail) + __asm__ volatile ("wfi"); + + return avail; +} + +/* +============================================================================== +Routine to test if RX byte available at console UART +============================================================================== +*/ +int nr5_uart_test_tx_empty() +{ + return *g_nr5_uart1.regs->pStat & NR5_UART_STATUS_TX_EMPTY; +} + +/* +============================================================================== +Routine to send TX byte to console UART +============================================================================== +*/ +void nr5_uart_put_tx(uint8_t ch) +{ + // Wait for TX to be empty + while (!(*g_nr5_uart1.regs->pStat & NR5_UART_STATUS_TX_EMPTY)) + ; + + // Write to TX + *g_nr5_uart1.regs->pTx = ch; +} + diff --git a/arch/risc-v/src/nr5m100/nr5_uart.h b/arch/risc-v/src/nr5m100/nr5_uart.h new file mode 100644 index 0000000000..7f40dfc0ab --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_uart.h @@ -0,0 +1,49 @@ +/************************************************************************************ + * arch/riscv/src/nr5/nr5_uart.h + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef _ARCH_RISCV_SRC_NR5_NR5_UART_H +#define _ARCH_RISCV_SRC_NR5_NR5_UART_H + +#include + +#ifdef CONFIG_NR5_NR5M1XX +#include "chip/nr5m1xx_uart.h" +#endif + +void nr5_uart_init(int uart_num); +uint8_t nr5_uart_get_rx(void); +int nr5_uart_test_rx_avail(void); +int nr5_uart_test_tx_empty(void); +void nr5_uart_put_tx(uint8_t ch); + +#endif /* _ARCH_RISCV_SRC_NR5_NR5_UART_H */ + diff --git a/arch/risc-v/src/nr5m100/nr5_vectors.S b/arch/risc-v/src/nr5m100/nr5_vectors.S new file mode 100644 index 0000000000..ea239d91ce --- /dev/null +++ b/arch/risc-v/src/nr5m100/nr5_vectors.S @@ -0,0 +1,101 @@ +/************************************************************************************ + * arch/risc-v/src/nr5m100/nr5_vectors.S + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include "nr5_csr.h" + + .section .text.vec + .global __reset_vec + .global __trap_vec + + +/************************************************************************************ + * ADDR: 00h - RESET + ************************************************************************************/ + +__reset_vec: + csrw NR5_EPIC_PRIMASK, 7 + j __start + +/************************************************************************************ + * ADDR: 08h - PRI0 (Illegal Instruction, Bus Error) + ************************************************************************************/ + +__trap_vec: +__pri0_vec: + j irq_handler + nop + +/************************************************************************************ + * ADDR: 10h - PRI1 Interrupt Handler + ************************************************************************************/ + +__pri1_vec: + j irq_handler + nop + +/************************************************************************************ + * ADDR: 18h - PRI2 Interrupt Handler + ************************************************************************************/ + +__pri2_vec: + j irq_handler + nop + +/************************************************************************************ + * ADDR: 20h - PRI3 Interrupt Handler + ************************************************************************************/ + +__pri3_vec: + j irq_handler + nop + +/************************************************************************************ + * ADDR: 28h - PRI4 Interrupt Handler + ************************************************************************************/ + +__pri4_vec: + j irq_handler + nop + +/**************************************************************************** + * Modeline to set vim formatting options for ASM file. For this to work, + * you must enable moeline processing in your ~/.vimrc file with: + * + * ~/.vimrc: + * set modeline + * + * vim: noet:ts=4:sw=4 + ****************************************************************************/ diff --git a/arch/risc-v/src/nr5m100/up_schedulesigaction.c b/arch/risc-v/src/nr5m100/up_schedulesigaction.c new file mode 100644 index 0000000000..d7b8698a56 --- /dev/null +++ b/arch/risc-v/src/nr5m100/up_schedulesigaction.c @@ -0,0 +1,213 @@ +/**************************************************************************** + * arch/risc-v/src/nr5m100/up_schedulesigaction.c + * + * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "sched/sched.h" +#include "up_internal.h" +#include "up_arch.h" + +#ifndef CONFIG_DISABLE_SIGNALS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_schedule_sigaction + * + * Description: + * This function is called by the OS when one or more + * signal handling actions have been queued for execution. + * The architecture specific code must configure things so + * that the 'igdeliver' callback is executed on the thread + * specified by 'tcb' as soon as possible. + * + * This function may be called from interrupt handling logic. + * + * This operation should not cause the task to be unblocked + * nor should it cause any immediate execution of sigdeliver. + * Typically, a few cases need to be considered: + * + * (1) This function may be called from an interrupt handler + * During interrupt processing, all xcptcontext structures + * should be valid for all tasks. That structure should + * be modified to invoke sigdeliver() either on return + * from (this) interrupt or on some subsequent context + * switch to the recipient task. + * (2) If not in an interrupt handler and the tcb is NOT + * the currently executing task, then again just modify + * the saved xcptcontext structure for the recipient + * task so it will invoke sigdeliver when that task is + * later resumed. + * (3) If not in an interrupt handler and the tcb IS the + * currently executing task -- just call the signal + * handler now. + * + ****************************************************************************/ + +void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) +{ + irqstate_t flags; + uint32_t int_ctx; + + sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver); + + /* Make sure that interrupts are disabled */ + + flags = enter_critical_section(); + + /* Refuse to handle nested signal actions */ + + if (!tcb->xcp.sigdeliver) + { + /* First, handle some special cases when the signal is + * being delivered to the currently executing task. + */ + + sinfo("rtcb=0x%p g_current_regs=0x%p\n", + this_task(), g_current_regs); + + if (tcb == this_task()) + { + /* CASE 1: We are not in an interrupt handler and + * a task is signalling itself for some reason. + */ + + if (!g_current_regs) + { + /* In this case just deliver the signal now. */ + + sigdeliver(tcb); + } + + /* CASE 2: We are in an interrupt handler AND the + * interrupted task is the same as the one that + * must receive the signal, then we will have to modify + * the return state as well as the state in the TCB. + * + * Hmmm... there looks like a latent bug here: The following + * logic would fail in the strange case where we are in an + * interrupt handler, the thread is signalling itself, but + * a context switch to another task has occurred so that + * g_current_regs does not refer to the thread of this_task()! + */ + + else + { + /* Save the return EPC and STATUS registers. These will be + * restored by the signal trampoline after the signals have + * been delivered. + */ + + tcb->xcp.sigdeliver = sigdeliver; + tcb->xcp.saved_epc = g_current_regs[REG_EPC]; + + /* Then set up to vector to the trampoline with interrupts + * disabled + */ + + g_current_regs[REG_EPC] = (uint32_t)up_sigdeliver; + int_ctx = g_current_regs[REG_INT_CTX]; + int_ctx &= ~EPIC_STATUS_INT_PRI_MASK; + int_ctx |= EPIC_STATUS_INT_PRI1; + g_current_regs[REG_INT_CTX] = int_ctx; + + /* And make sure that the saved context in the TCB + * is the same as the interrupt return context. + */ + + up_savestate(tcb->xcp.regs); + + sinfo("PC/STATUS Saved: %08x/%08x New: %08x/%08x\n", + tcb->xcp.saved_epc, tcb->xcp.saved_status, + g_current_regs[REG_EPC], g_current_regs[REG_STATUS]); + } + } + + /* Otherwise, we are (1) signaling a task is not running + * from an interrupt handler or (2) we are not in an + * interrupt handler and the running task is signalling + * some non-running task. + */ + + else + { + /* Save the return EPC and STATUS registers. These will be + * restored by the signal trampoline after the signals have + * been delivered. + */ + + tcb->xcp.sigdeliver = sigdeliver; + tcb->xcp.saved_epc = tcb->xcp.regs[REG_EPC]; + tcb->xcp.saved_int_ctx = tcb->xcp.regs[REG_INT_CTX]; + + /* Then set up to vector to the trampoline with interrupts + * disabled + */ + + tcb->xcp.regs[REG_EPC] = (uint32_t)up_sigdeliver; + int_ctx = tcb->xcp.regs[REG_INT_CTX]; + int_ctx &= ~EPIC_STATUS_INT_PRI_MASK; + int_ctx |= EPIC_STATUS_INT_PRI1; + tcb->xcp.regs[REG_INT_CTX] = int_ctx; + + sinfo("PC/STATUS Saved: %08x/%08x New: %08x/%08x\n", + tcb->xcp.saved_epc, tcb->xcp.saved_status, + tcb->xcp.regs[REG_EPC], tcb->xcp.regs[REG_STATUS]); + } + } + + leave_critical_section(flags); +} + +#endif /* !CONFIG_DISABLE_SIGNALS */ diff --git a/arch/risc-v/src/rv32im/Kconfig b/arch/risc-v/src/rv32im/Kconfig new file mode 100644 index 0000000000..9bc4b560f5 --- /dev/null +++ b/arch/risc-v/src/rv32im/Kconfig @@ -0,0 +1,51 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "RV32IM Configuration Options" + +choice + prompt "Toolchain Selection" + default RV32IM_TOOLCHAIN_GNU_RVGW if HOST_WINDOWS + default RV32IM_TOOLCHAIN_GNU_RVGL if !HOST_WINDOWS + +config RV32IM_TOOLCHAIN_GNU_RVGL + bool "Generic GNU RVG toolchain under Linux (or other POSIX environment)" + ---help--- + This option should work for any modern GNU toolchain (GCC 5.2 or newer) + configured for riscv32-unknown-elf. + +config RV32IM_TOOLCHAIN_GNU_RVGW + bool "Generic GNU RVG toolchain under Windows" + depends on HOST_WINDOWS + ---help--- + This option should work for any modern GNU toolchain (GCC 5.2 or newer) + configured for riscv32-unknown-elf. + +endchoice + +config RV32IM_HW_MULDIV + bool "Supports Hardware MUL and DIV" + default n + ---help--- + Specifies if the architecture supports hardware multiply and + hardware division instructions. Selecting this will cause the + generated code to natively use mul / div instructions for any + math operations. + +config RV32IM_SYSTEM_CSRRS_SUPPORT + bool "Supports RV core feature identification via CSRRS opcode" + default n + ---help--- + Specifies if the architecture supports the SYSTEM opcode for reading + Control Status Registers to obtain the RV core option flags. + +config RV32IM_CUSTOM_IRQ_SUPPORT + bool "Has custom implementation for IRQ handling" + default n + ---help--- + Allows overriding the standard IRQ processing as described + in the RISC-V architecture documents. This allows architecture + specific code to support non-standard IRQ processing in the core. + diff --git a/arch/risc-v/src/rv32im/Toolchain.defs b/arch/risc-v/src/rv32im/Toolchain.defs new file mode 100644 index 0000000000..a89cf6cb26 --- /dev/null +++ b/arch/risc-v/src/rv32im/Toolchain.defs @@ -0,0 +1,104 @@ +############################################################################ +# arch/risc-v/src/rv32im/Toolchain.defs +# +# Copyright (C) 2012-2013, 2015 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# modified for RISC-V: +# +# Copyright (C) 2016 Ken Pettit. All rights reserved. +# Author: Ken Pettit +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# Setup for the selected toolchain + +# +# Handle old-style chip-specific toolchain names in the absence of +# a new-style toolchain specification, force the selection of a single +# toolchain and allow the selected toolchain to be overridden by a +# command-line selection. +# + +ifeq ($(filter y, $(CONFIG_RV32IM_TOOLCHAIN_GNU_RVGL)),y) + CONFIG_RISCV_TOOLCHAIN ?= GNU_RVGL +endif + +ifeq ($(filter y, $(CONFIG_RV32IM_TOOLCHAIN_GNU_RVGW)),y) + CONFIG_RISCV_TOOLCHAIN ?= GNU_RVGW +endif + +# +# Supported toolchains +# +# Each toolchain definition should set: +# +# CROSSDEV The GNU toolchain triple (command prefix) +# ARCROSSDEV If required, an alternative prefix used when +# invoking ar and nm. +# ARCHCPUFLAGS CPU-specific flags selecting the instruction set +# options, etc. +# MAXOPTIMIZATION The maximum optimization level that results in +# reliable code generation. +# + +ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) + MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL) +endif + +# Generic GNU RVG toolchain on OS X, Linux or any typical Posix system + +ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVGL) + CROSSDEV ?= riscv64-unknown-elf- + ARCROSSDEV ?= riscv64-unknown-elf- +ifeq ($(CONFIG_RV32IM_HW_MULDIV),y) + ARCHCPUFLAGS = -march=RV32IMXcustom -m32 +else + ARCHCPUFLAGS = -march=RV32IXcustom -m32 +endif +endif + +ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVGW) + CROSSDEV ?= riscv32-unknown-elf- + ARCROSSDEV ?= riscv32-unknown-elf- + ifneq ($(CONFIG_WINDOWS_NATIVE),y) + WINTOOL = y + endif +ifeq ($(CONFIG_RV32IM_HW_MULDIV),y) + ARCHCPUFLAGS = -march=RV32IMXcustom -m32 +else + ARCHCPUFLAGS = -march=RV32IXcustom -m32 +endif +endif + +# Individual tools may limit the optimizatin level but, by default, the +# optimization level will be set to to -Os + +ifeq ($(CONFIG_DEBUG_SYMBOLS),) +MAXOPTIMIZATION ?= -Os +endif + diff --git a/arch/risc-v/src/rv32im/up_assert.c b/arch/risc-v/src/rv32im/up_assert.c new file mode 100644 index 0000000000..a5edaa54d1 --- /dev/null +++ b/arch/risc-v/src/rv32im/up_assert.c @@ -0,0 +1,161 @@ +/**************************************************************************** + * arch/risc-v/src/rv32im/up_assert.c + * + * Copyright (C) 2011-2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "up_arch.h" +#include "sched/sched.h" +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* USB trace dumping */ + +#ifndef CONFIG_USBDEV_TRACE +# undef CONFIG_ARCH_USBDUMP +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _up_assert + ****************************************************************************/ + +static void _up_assert(int errorcode) noreturn_function; +static void _up_assert(int errorcode) +{ + /* Are we in an interrupt handler or the idle task? */ + + if (g_current_regs || this_task()->pid == 0) + { + (void)up_irq_save(); + for (; ; ) + { +#ifdef CONFIG_ARCH_LEDS + board_autoled_on(LED_PANIC); + up_mdelay(250); + board_autoled_off(LED_PANIC); + up_mdelay(250); +#endif + } + } + else + { + exit(errorcode); + } +} + +/**************************************************************************** + * Name: assert_tracecallback + ****************************************************************************/ + +#ifdef CONFIG_ARCH_USBDUMP +static int usbtrace_syslog(FAR const char *fmt, ...) +{ + va_list ap; + int ret; + + /* Let vsyslog do the real work */ + + va_start(ap, fmt); + ret = vsyslog(LOG_EMERG, fmt, ap); + va_end(ap); + return ret; +} + +static int assert_tracecallback(FAR struct usbtrace_s *trace, FAR void *arg) +{ + usbtrace_trprintf(usbtrace_syslog, trace->event, trace->value); + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_assert + ****************************************************************************/ + +void up_assert(const uint8_t *filename, int lineno) +{ +#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT) + struct tcb_s *rtcb = this_task(); +#endif + + board_autoled_on(LED_ASSERTION); + +#if CONFIG_TASK_NAME_SIZE > 0 + _alert("Assertion failed at file:%s line: %d task: %s\n", + filename, lineno, rtcb->name); +#else + _alert("Assertion failed at file:%s line: %d\n", + filename, lineno); +#endif + + up_dumpstate(); + +#ifdef CONFIG_ARCH_USBDUMP + /* Dump USB trace data */ + + (void)usbtrace_enumerate(assert_tracecallback, NULL); +#endif + +#ifdef CONFIG_BOARD_CRASHDUMP + board_crashdump(up_getsp(), this_task(), filename, lineno); +#endif + + _up_assert(EXIT_FAILURE); +} diff --git a/arch/risc-v/src/rv32im/up_blocktask.c b/arch/risc-v/src/rv32im/up_blocktask.c new file mode 100644 index 0000000000..530797da2b --- /dev/null +++ b/arch/risc-v/src/rv32im/up_blocktask.c @@ -0,0 +1,179 @@ +/**************************************************************************** + * arch/risc-v/src/rv32im/up_blocktask.c + * + * Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "group/group.h" +#include "up_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_block_task + * + * Description: + * The currently executing task at the head of + * the ready to run list must be stopped. Save its context + * and move it to the inactive list specified by task_state. + * + * Inputs: + * tcb: Refers to a task in the ready-to-run list (normally + * the task at the head of the list). It most be + * stopped, its context saved and moved into one of the + * waiting task lists. It it was the task at the head + * of the ready-to-run list, then a context to the new + * ready to run task must be performed. + * task_state: Specifies which waiting task list should be + * hold the blocked task TCB. + * + ****************************************************************************/ + +void up_block_task(struct tcb_s *tcb, tstate_t task_state) +{ + struct tcb_s *rtcb = this_task(); + bool switch_needed; + + /* Verify that the context switch can be performed */ + + ASSERT((tcb->task_state >= FIRST_READY_TO_RUN_STATE) && + (tcb->task_state <= LAST_READY_TO_RUN_STATE)); + + /* Remove the tcb task from the ready-to-run list. If we + * are blocking the task at the head of the task list (the + * most likely case), then a context switch to the next + * ready-to-run task is needed. In this case, it should + * also be true that rtcb == tcb. + */ + + switch_needed = sched_removereadytorun(tcb); + + /* Add the task to the specified blocked task list */ + + sched_addblocked(tcb, (tstate_t)task_state); + + /* If there are any pending tasks, then add them to the ready-to-run + * task list now + */ + + if (g_pendingtasks.head) + { + switch_needed |= sched_mergepending(); + } + + /* Now, perform the context switch if one is needed */ + + if (switch_needed) + { + /* Update scheduler parameters */ + + sched_suspend_scheduler(rtcb); + + /* Are we in an interrupt handler? */ + + if (g_current_regs) + { + /* Yes, then we have to do things differently. + * Just copy the g_current_regs into the OLD rtcb. + */ + + up_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + + /* Reset scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + up_restorestate(rtcb->xcp.regs); + } + + /* No, then we will need to perform the user context switch */ + + else + { + /* Get the context of the task at the head of the ready to + * run list. + */ + + struct tcb_s *nexttcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(nexttcb); +#endif + /* Reset scheduler parameters */ + + sched_resume_scheduler(nexttcb); + + /* Then switch contexts */ + + up_switchcontext(rtcb->xcp.regs, nexttcb->xcp.regs); + + /* up_switchcontext forces a context switch to the task at the + * head of the ready-to-run list. It does not 'return' in the + * normal sense. When it does return, it is because the blocked + * task is again ready to run and has execution priority. + */ + } + } +} diff --git a/arch/risc-v/src/rv32im/up_copystate.c b/arch/risc-v/src/rv32im/up_copystate.c new file mode 100644 index 0000000000..ca0fa98019 --- /dev/null +++ b/arch/risc-v/src/rv32im/up_copystate.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * arch/risc-v/src/rv32im/up_copystate.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_copystate + ****************************************************************************/ + +/* A little faster than most memcpy's */ + +void up_copystate(uint32_t *dest, uint32_t *src) +{ + int i; + + /* In the MIPS model, the state is copied from the stack to the TCB, + * but only a reference is passed to get the state from the TCB. So the + * following check avoids copying the TCB save area onto itself: + */ + + if (src != dest) + { + for (i = 0; i < XCPTCONTEXT_REGS; i++) + { + *dest++ = *src++; + } + } +} + diff --git a/arch/risc-v/src/rv32im/up_doirq.c b/arch/risc-v/src/rv32im/up_doirq.c new file mode 100644 index 0000000000..70966d12f9 --- /dev/null +++ b/arch/risc-v/src/rv32im/up_doirq.c @@ -0,0 +1,148 @@ +/**************************************************************************** + * arch/risc-v/src/rv32im/up_doirq.c + * + * Copyright (C) 2011, 2014-2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "group/group.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +uint32_t *up_doirq(int irq, uint32_t *regs) +{ + board_autoled_on(LED_INIRQ); +#ifdef CONFIG_SUPPRESS_INTERRUPTS + PANIC(); +#else + /* Current regs non-zero indicates that we are processing an interrupt; + * g_current_regs is also used to manage interrupt level context switches. + * + * Nested interrupts are not supported + */ + + DEBUGASSERT(g_current_regs == NULL); + g_current_regs = regs; + + /* Disable further occurrences of this interrupt (until the interrupt sources + * have been clear by the driver). + */ + + up_disable_irq(irq); + + /* Deliver the IRQ */ + + irq_dispatch(irq, regs); + +#if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV) + /* Check for a context switch. If a context switch occurred, then + * g_current_regs will have a different value than it did on entry. If an + * interrupt level context switch has occurred, then restore the floating + * point state and the establish the correct address environment before + * returning from the interrupt. + */ + + if (regs != g_current_regs) + { +#ifdef CONFIG_ARCH_FPU + /* Restore floating point registers */ + + up_restorefpu((uint32_t *)g_current_regs); +#endif + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(NULL); +#endif + } +#endif + + /* If a context switch occurred while processing the interrupt then + * g_current_regs may have change value. If we return any value different + * from the input regs, then the lower level will know that a context + * switch occurred during interrupt processing. + */ + + regs = (uint32_t *)g_current_regs; + + /* Set g_current_regs to NULL to indicate that we are no longer in an + * interrupt handler. + */ + + g_current_regs = NULL; + + /* Unmask the last interrupt (global interrupts are still disabled) */ + + up_enable_irq(irq); +#endif + board_autoled_off(LED_INIRQ); + return regs; +} diff --git a/arch/risc-v/src/rv32im/up_dumpstate.c b/arch/risc-v/src/rv32im/up_dumpstate.c new file mode 100644 index 0000000000..97f74c6411 --- /dev/null +++ b/arch/risc-v/src/rv32im/up_dumpstate.c @@ -0,0 +1,231 @@ +/**************************************************************************** + * arch/risc-v/src/rv32im/up_dumpstate.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Updated for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "up_arch.h" +#include "sched/sched.h" +#include "up_internal.h" + +#ifdef CONFIG_ARCH_STACKDUMP + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_getsp + ****************************************************************************/ + +static inline uint32_t up_getsp(void) +{ + register uint32_t sp; + __asm__ + ( + "\tadd %0, x0, x2\n" + : "=r"(sp) + ); + return sp; +} + +/**************************************************************************** + * Name: up_stackdump + ****************************************************************************/ + +static void up_stackdump(uint32_t sp, uint32_t stack_base) +{ + uint32_t stack ; + + for (stack = sp & ~0x1f; stack < stack_base; stack += 32) + { + uint32_t *ptr = (uint32_t *)stack; + _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", + stack, ptr[0], ptr[1], ptr[2], ptr[3], + ptr[4], ptr[5], ptr[6], ptr[7]); + } +} + +/**************************************************************************** + * Name: up_registerdump + ****************************************************************************/ + +static inline void up_registerdump(void) +{ + /* Are user registers available from interrupt processing? */ + + if (g_current_regs) + { + _alert("EPC:%08x \n", + g_current_regs[REG_EPC]); + _alert("A0:%08x A1:%08x A2:%08x A3:%08x A4:%08x A5:%08x A6:%08x A7:%08x\n", + g_current_regs[REG_A0], g_current_regs[REG_A1], g_current_regs[REG_A2], + g_current_regs[REG_A3], g_current_regs[REG_A4], g_current_regs[REG_A5], + g_current_regs[REG_A6], g_current_regs[REG_A7]); + _alert("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x\n", + g_current_regs[REG_T0], g_current_regs[REG_T1], g_current_regs[REG_T2], + g_current_regs[REG_T3], g_current_regs[REG_T4], g_current_regs[REG_T5], + g_current_regs[REG_T6]); + _alert("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n", + g_current_regs[REG_S0], g_current_regs[REG_S1], g_current_regs[REG_S2], + g_current_regs[REG_S3], g_current_regs[REG_S4], g_current_regs[REG_S5], + g_current_regs[REG_S6], g_current_regs[REG_S7]); + _alert("S8:%08x S9:%08x S10:%08x S11:%08x\n", + g_current_regs[REG_S8], g_current_regs[REG_S9], g_current_regs[REG_S10], + g_current_regs[REG_S11]); +#ifdef RISCV_SAVE_GP + _alert("GP:%08x SP:%08x FP:%08x TP:%08x RA:%08x\n", + g_current_regs[REG_GP], g_current_regs[REG_SP], g_current_regs[REG_FP], + g_current_regs[REG_TP], g_current_regs[REG_RA]); +#else + _alert("SP:%08x FP:%08x TP:%08x RA:%08x\n", + g_current_regs[REG_SP], g_current_regs[REG_FP], g_current_regs[REG_TP], + g_current_regs[REG_RA]); +#endif + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_dumpstate + ****************************************************************************/ + +void up_dumpstate(void) +{ + struct tcb_s *rtcb = this_task(); + uint32_t sp = up_getsp(); + uint32_t ustackbase; + uint32_t ustacksize; +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + uint32_t istackbase; + uint32_t istacksize; +#endif + + /* Get the limits on the user stack memory */ + + if (rtcb->pid == 0) + { + ustackbase = g_idle_topstack - 4; + ustacksize = CONFIG_IDLETHREAD_STACKSIZE; + } + else + { + ustackbase = (uint32_t)rtcb->adj_stack_ptr; + ustacksize = (uint32_t)rtcb->adj_stack_size; + } + + /* Get the limits on the interrupt stack memory */ + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + istackbase = (uint32_t)&g_intstackbase; + istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4; + + /* Show interrupt stack info */ + + _alert("sp: %08x\n", sp); + _alert("IRQ stack:\n"); + _alert(" base: %08x\n", istackbase); + _alert(" size: %08x\n", istacksize); + + /* Does the current stack pointer lie within the interrupt + * stack? + */ + + if (sp <= istackbase && sp > istackbase - istacksize) + { + /* Yes.. dump the interrupt stack */ + + up_stackdump(sp, istackbase); + + /* Extract the user stack pointer which should lie + * at the base of the interrupt stack. + */ + + sp = g_intstackbase; + _alert("sp: %08x\n", sp); + } + + /* Show user stack info */ + + _alert("User stack:\n"); + _alert(" base: %08x\n", ustackbase); + _alert(" size: %08x\n", ustacksize); +#else + _alert("sp: %08x\n", sp); + _alert("stack base: %08x\n", ustackbase); + _alert("stack size: %08x\n", ustacksize); +#endif + + /* Dump the user stack if the stack pointer lies within the allocated user + * stack memory. + */ + + if (sp > ustackbase || sp <= ustackbase - ustacksize) + { +#if !defined(CONFIG_ARCH_INTERRUPTSTACK) || CONFIG_ARCH_INTERRUPTSTACK < 4 + _alert("ERROR: Stack pointer is not within allocated stack\n"); +#endif + } + else + { + up_stackdump(sp, ustackbase); + } + + /* Then dump the registers (if available) */ + + up_registerdump(); +} + +#endif /* CONFIG_ARCH_STACKDUMP */ diff --git a/arch/risc-v/src/rv32im/up_initialstate.c b/arch/risc-v/src/rv32im/up_initialstate.c new file mode 100644 index 0000000000..492f9f1086 --- /dev/null +++ b/arch/risc-v/src/rv32im/up_initialstate.c @@ -0,0 +1,133 @@ +/**************************************************************************** + * arch/risc-v/src/rv32im/up_initialstate.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_initial_state + * + * Description: + * A new thread is being started and a new TCB + * has been created. This function is called to initialize + * the processor specific portions of the new TCB. + * + * This function must setup the intial architecture registers + * and/or stack so that execution will begin at tcb->start + * on the next context switch. + * + ****************************************************************************/ + +void up_initial_state(struct tcb_s *tcb) +{ + struct xcptcontext *xcp = &tcb->xcp; + uint32_t regval; + + /* Initialize the initial exception register context structure */ + + memset(xcp, 0, sizeof(struct xcptcontext)); + + /* Save the initial stack pointer. Hmmm.. the stack is set to the very + * beginning of the stack region. Some functions may want to store data on + * the caller's stack and it might be good to reserve some space. However, + * only the start function would do that and we have control over that one + */ + + xcp->regs[REG_SP] = (uint32_t)tcb->adj_stack_ptr; + + /* Save the task entry point */ + + xcp->regs[REG_EPC] = (uint32_t)tcb->start; + + /* If this task is running PIC, then set the PIC base register to the + * address of the allocated D-Space region. + */ + +#ifdef CONFIG_PIC +# warning "Missing logic" +#endif + + /* Set privileged- or unprivileged-mode, depending on how NuttX is + * configured and what kind of thread is being started. + * + * If the kernel build is not selected, then all threads run in + * privileged thread mode. + */ + +#ifdef CONFIG_BUILD_KERNEL +# warning "Missing logic" +#endif + + /* Set the initial value of the interrupt context register. + * + * Since various RISC-V platforms use different interrupt + * methodologies, the value of the interrupt context is + * part specific. + * + */ + + regval = up_get_newintctx(); + xcp->regs[REG_INT_CTX] = regval; +} + diff --git a/arch/risc-v/src/rv32im/up_releasepending.c b/arch/risc-v/src/rv32im/up_releasepending.c new file mode 100644 index 0000000000..e3fa22d47e --- /dev/null +++ b/arch/risc-v/src/rv32im/up_releasepending.c @@ -0,0 +1,148 @@ +/**************************************************************************** + * arch/risc-v/src/rv32im/up_releasepending.c + * + * Copyright (C) 2011, 2014-2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "group/group.h" +#include "up_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_release_pending + * + * Description: + * Release and ready-to-run tasks that have + * collected in the pending task list. This can call a + * context switch if a new task is placed at the head of + * the ready to run list. + * + ****************************************************************************/ + +void up_release_pending(void) +{ + struct tcb_s *rtcb = this_task(); + + sinfo("From TCB=%p\n", rtcb); + + /* Merge the g_pendingtasks list into the ready-to-run task list */ + + /* sched_lock(); */ + if (sched_mergepending()) + { + /* The currently active task has changed! We will need to switch + * contexts. + * + * Update scheduler parameters. + */ + + sched_suspend_scheduler(rtcb); + + /* Are we operating in interrupt context? */ + + if (g_current_regs) + { + /* Yes, then we have to do things differently. + * Just copy the g_current_regs into the OLD rtcb. + */ + + up_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + + /* Update scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + up_restorestate(rtcb->xcp.regs); + } + + /* No, then we will need to perform the user context switch */ + + else + { + /* Switch context to the context of the task at the head of the + * ready to run list. + */ + + struct tcb_s *nexttcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(nexttcb); +#endif + /* Update scheduler parameters */ + + sched_resume_scheduler(nexttcb); + + /* Then switch contexts */ + + up_switchcontext(rtcb->xcp.regs, nexttcb->xcp.regs); + + /* up_switchcontext forces a context switch to the task at the + * head of the ready-to-run list. It does not 'return' in the + * normal sense. When it does return, it is because the blocked + * task is again ready to run and has execution priority. + */ + } + } +} diff --git a/arch/risc-v/src/rv32im/up_reprioritizertr.c b/arch/risc-v/src/rv32im/up_reprioritizertr.c new file mode 100644 index 0000000000..26ed4ab2d1 --- /dev/null +++ b/arch/risc-v/src/rv32im/up_reprioritizertr.c @@ -0,0 +1,203 @@ +/**************************************************************************** + * arch/risc-v/src/rv32im/up_reprioritizertr.c + * + * Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "group/group.h" +#include "up_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_reprioritize_rtr + * + * Description: + * Called when the priority of a running or + * ready-to-run task changes and the reprioritization will + * cause a context switch. Two cases: + * + * 1) The priority of the currently running task drops and the next + * task in the ready to run list has priority. + * 2) An idle, ready to run task's priority has been raised above the + * the priority of the current, running task and it now has the + * priority. + * + * Inputs: + * tcb: The TCB of the task that has been reprioritized + * priority: The new task priority + * + ****************************************************************************/ + +void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) +{ + /* Verify that the caller is sane */ + + if (tcb->task_state < FIRST_READY_TO_RUN_STATE || + tcb->task_state > LAST_READY_TO_RUN_STATE +#if SCHED_PRIORITY_MIN > 0 + || priority < SCHED_PRIORITY_MIN +#endif +#if SCHED_PRIORITY_MAX < UINT8_MAX + || priority > SCHED_PRIORITY_MAX +#endif + ) + { + PANIC(); + } + else + { + struct tcb_s *rtcb = this_task(); + bool switch_needed; + + sinfo("TCB=%p PRI=%d\n", tcb, priority); + + /* Remove the tcb task from the ready-to-run list. + * sched_removereadytorun will return true if we just + * remove the head of the ready to run list. + */ + + switch_needed = sched_removereadytorun(tcb); + + /* Setup up the new task priority */ + + tcb->sched_priority = (uint8_t)priority; + + /* Return the task to the specified blocked task list. + * sched_addreadytorun will return true if the task was + * added to the new list. We will need to perform a context + * switch only if the EXCLUSIVE or of the two calls is non-zero + * (i.e., one and only one the calls changes the head of the + * ready-to-run list). + */ + + switch_needed ^= sched_addreadytorun(tcb); + + /* Now, perform the context switch if one is needed */ + + if (switch_needed) + { + /* If we are going to do a context switch, then now is the right + * time to add any pending tasks back into the ready-to-run list. + * task list now + */ + + if (g_pendingtasks.head) + { + sched_mergepending(); + } + + /* Update scheduler parameters */ + + sched_suspend_scheduler(rtcb); + + /* Are we in an interrupt handler? */ + + if (g_current_regs) + { + /* Yes, then we have to do things differently. + * Just copy the g_current_regs into the OLD rtcb. + */ + + up_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + + /* Update scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + up_restorestate(rtcb->xcp.regs); + } + + /* No, then we will need to perform the user context switch */ + + else + { + /* Switch context to the context of the task at the head of the + * ready to run list. + */ + + struct tcb_s *nexttcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(nexttcb); +#endif + /* Update scheduler parameters */ + + sched_resume_scheduler(nexttcb); + + /* Then switch contexts */ + + up_switchcontext(rtcb->xcp.regs, nexttcb->xcp.regs); + + /* up_switchcontext forces a context switch to the task at the + * head of the ready-to-run list. It does not 'return' in the + * normal sense. When it does return, it is because the blocked + * task is again ready to run and has execution priority. + */ + } + } + } +} diff --git a/arch/risc-v/src/rv32im/up_sigdeliver.c b/arch/risc-v/src/rv32im/up_sigdeliver.c new file mode 100644 index 0000000000..6d57a2b4a3 --- /dev/null +++ b/arch/risc-v/src/rv32im/up_sigdeliver.c @@ -0,0 +1,155 @@ +/**************************************************************************** + * arch/risc-v/src/rv32im/up_sigdeliver.c + * + * Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "sched/sched.h" +#include "up_internal.h" +#include "up_arch.h" + +#ifndef CONFIG_DISABLE_SIGNALS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_sigdeliver + * + * Description: + * This is the a signal handling trampoline. When a signal action was + * posted. The task context was mucked with and forced to branch to this + * location with interrupts disabled. + * + ****************************************************************************/ + +void up_sigdeliver(void) +{ + struct tcb_s *rtcb = this_task(); + uint32_t regs[XCPTCONTEXT_REGS]; + sig_deliver_t sigdeliver; + + /* Save the errno. This must be preserved throughout the signal handling + * so that the user code final gets the correct errno value (probably + * EINTR). + */ + + int saved_errno = rtcb->pterrno; + + board_autoled_on(LED_SIGNAL); + + sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", + rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); + ASSERT(rtcb->xcp.sigdeliver != NULL); + + /* Save the real return state on the stack. */ + + up_copystate(regs, rtcb->xcp.regs); + regs[REG_EPC] = rtcb->xcp.saved_epc; + regs[REG_INT_CTX] = rtcb->xcp.saved_int_ctx; + + /* Get a local copy of the sigdeliver function pointer. We do this so that + * we can nullify the sigdeliver function pointer in the TCB and accept + * more signal deliveries while processing the current pending signals. + */ + + sigdeliver = rtcb->xcp.sigdeliver; + rtcb->xcp.sigdeliver = NULL; + + /* Then restore the task interrupt state */ + + up_irq_restore((irqstate_t)regs[REG_INT_CTX]); + + /* Deliver the signals */ + + sigdeliver(rtcb); + + /* Output any debug messages BEFORE restoring errno (because they may + * alter errno), then disable interrupts again and restore the original + * errno that is needed by the user logic (it is probably EINTR). + */ + + sinfo("Resuming EPC: %08x INT_CTX: %08x\n", regs[REG_EPC], regs[REG_INT_CTX]); + + (void)up_irq_save(); + rtcb->pterrno = saved_errno; + + /* Then restore the correct state for this thread of + * execution. + */ + + board_autoled_off(LED_SIGNAL); + up_fullcontextrestore(regs); + + /* up_fullcontextrestore() should not return but could if the software + * interrupts are disabled. + */ + + PANIC(); +} + +#endif /* !CONFIG_DISABLE_SIGNALS */ + diff --git a/arch/risc-v/src/rv32im/up_swint.c b/arch/risc-v/src/rv32im/up_swint.c new file mode 100644 index 0000000000..61f3afefac --- /dev/null +++ b/arch/risc-v/src/rv32im/up_swint.c @@ -0,0 +1,285 @@ +/**************************************************************************** + * arch/riscv/src/rv32im/up_swint.c + * + * Copyright (C) 2011-2012, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include + +#include "up_internal.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_registerdump + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_SYSCALL_INFO +static void up_registerdump(const uint32_t *regs) +{ + svcinfo("EPC:%08x\n", + regs[REG_EPC]); + svcinfo("A0:%08x A1:%08x A2:%08x A3:%08x A4:%08x A5:%08x A6:%08x A7:%08x\n", + regs[REG_A0], regs[REG_A1], regs[REG_A2], regs[REG_A3], + regs[REG_A4], regs[REG_A5], regs[REG_A6], regs[REG_A7]); + svcinfo("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x\n", + regs[REG_T0], regs[REG_T1], regs[REG_T2], regs[REG_T3], + regs[REG_T4], regs[REG_T5], regs[REG_T6]); + svcinfo("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n", + regs[REG_S0], regs[REG_S1], regs[REG_S2], regs[REG_S3], + regs[REG_S4], regs[REG_S5], regs[REG_S6], regs[REG_S7]); + svcinfo("S8:%08x S9:%08x S10:%08x S11:%08x\n", + regs[REG_S8], regs[REG_S9], regs[REG_S10], regs[REG_S11]); +#ifdef MIPS32_SAVE_GP + svcinfo("GP:%08x SP:%08x FP:%08x TP:%08x RA:%08x\n", + regs[REG_GP], regs[REG_SP], regs[REG_FP], regs[REG_TP], regs[REG_RA]); +#else + svcinfo("SP:%08x FP:%08x TP:%08x RA:%08x\n", + regs[REG_SP], regs[REG_FP], regs[REG_TP], regs[REG_RA]); +#endif +} +#else +# define up_registerdump(regs) +#endif + +/**************************************************************************** + * Name: dispatch_syscall + * + * Description: + * Call the stub function corresponding to the system call. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_KERNEL +static void dispatch_syscall(void) naked_function; +static void dispatch_syscall(void) +{ +# error "Missing logic" + +/* Refer to arch/arm/src/armv7-m/up_svcall.h for how this is done for ARM */ +/* __asm__ __volatile__ */ +/* ( */ +/* Save registers */ +/* Get the base of the stub lookup table */ +/* Get the offset of the stub for this syscall */ +/* Load the entry of the stub for this syscall */ +/* Call the stub */ +/* Restore regsisters */ +/* Return from the syscall */ +/* ); */ +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_swint + * + * Description: + * This is software interrupt exception handler that performs context + * switching and manages system calls + * + ****************************************************************************/ + +int up_swint(int irq, FAR void *context) +{ + uint32_t *regs = (uint32_t *)context; + + DEBUGASSERT(regs && regs == g_current_regs); + + /* Software interrupt 0 is invoked with REG_A0 (REG_X10) = system call + * command and REG_A1-6 = variable number of + * arguments depending on the system call. + */ + +#ifdef CONFIG_DEBUG_SYSCALL_INFO + svcinfo("Entry: regs: %p cmd: %d\n", regs, regs[REG_A0]); + up_registerdump(regs); +#endif + + /* Handle the SWInt according to the command in $a0 */ + + switch (regs[REG_A0]) + { + /* A0=SYS_restore_context: This a restore context command: + * + * void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function; + * + * At this point, the following values are saved in context: + * + * A0 = SYS_restore_context + * A1 = restoreregs + * + * In this case, we simply need to set g_current_regs to restore register + * area referenced in the saved R1. context == g_current_regs is the normal + * exception return. By setting g_current_regs = context[R1], we force + * the return to the saved context referenced in $a1. + */ + + case SYS_restore_context: + { + DEBUGASSERT(regs[REG_A1] != 0); + g_current_regs = (uint32_t *)regs[REG_A1]; + } + break; + + /* A0=SYS_switch_context: This a switch context command: + * + * void up_switchcontext(uint32_t *saveregs, uint32_t *restoreregs); + * + * At this point, the following values are saved in context: + * + * A0 = SYS_switch_context + * A1 = saveregs + * A2 = restoreregs + * + * In this case, we save the context registers to the save register + * area reference by the saved contents of R5 and then set + * g_current_regs to to the save register area referenced by the saved + * contents of R6. + */ + + case SYS_switch_context: + { + DEBUGASSERT(regs[REG_A1] != 0 && regs[REG_A2] != 0); + up_copystate((uint32_t *)regs[REG_A1], regs); + g_current_regs = (uint32_t *)regs[REG_A2]; + } + break; + + /* A0=SYS_syscall_return: This a switch context command: + * + * void up_sycall_return(void); + * + * At this point, the following values are saved in context: + * + * A0 = SYS_syscall_return + * + * We need to restore the saved return address and return in + * unprivileged thread mode. + */ + +#ifdef CONFIG_BUILD_KERNEL + case SYS_syscall_return: + { + struct tcb_s *rtcb = sched_self(); + int index = (int)rtcb->xcp.nsyscalls - 1; + + /* Make sure that there is a saved syscall return address. */ + + DEBUGASSERT(index >= 0); + + /* Setup to return to the saved syscall return address in + * the original mode. + */ + + g_current_regs[REG_EPC] = rtcb->xcp.syscall[index].sysreturn; +#error "Missing logic -- need to restore the original mode" + rtcb->xcp.nsyscalls = index; + } + break; +#endif + + /* This is not an architecture-specify system call. If NuttX is built + * as a standalone kernel with a system call interface, then all of the + * additional system calls must be handled as in the default case. + */ + + default: + { +#ifdef CONFIG_BUILD_KERNEL + FAR struct tcb_s *rtcb = sched_self(); + int index = rtcb->xcp.nsyscalls; + + /* Verify that the SYS call number is within range */ + + DEBUGASSERT(g_current_regs[REG_A0] < SYS_maxsyscall); + + /* Make sure that we got here that there is a no saved syscall + * return address. We cannot yet handle nested system calls. + */ + + DEBUGASSERT(index < CONFIG_SYS_NNEST); + + /* Setup to return to dispatch_syscall in privileged mode. */ + + rtcb->xcpsyscall[index].sysreturn = regs[REG_EPC]; +#error "Missing logic -- Need to save mode" + rtcb->xcp.nsyscalls = index + 1; + + regs[REG_EPC] = (uint32_t)dispatch_syscall; +#error "Missing logic -- Need to set privileged mode" + + /* Offset R0 to account for the reserved values */ + + g_current_regs[REG_A0] -= CONFIG_SYS_RESERVED; +#else + svcerr("ERROR: Bad SYS call: %d\n", regs[REG_A0]); +#endif + } + break; + } + + /* Report what happened. That might difficult in the case of a context switch */ + +#ifdef CONFIG_DEBUG_SYSCALL_INFO + if (regs != g_current_regs) + { + svcinfo("SWInt Return: Context switch!\n"); + up_registerdump((const uint32_t *)g_current_regs); + } + else + { + svcinfo("SWInt Return: %d\n", regs[REG_A0]); + } +#endif + + return OK; +} diff --git a/arch/risc-v/src/rv32im/up_syscall.S b/arch/risc-v/src/rv32im/up_syscall.S new file mode 100644 index 0000000000..1c110db629 --- /dev/null +++ b/arch/risc-v/src/rv32im/up_syscall.S @@ -0,0 +1,112 @@ +/**************************************************************************** + * arch/riscv/src/rv32im/up_syscall.S + * + * Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for RISC-V: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Symbols + ****************************************************************************/ + + .file "up_syscall0.S" + .global sys_call0 + .global sys_call1 + .global sys_call2 + .global sys_call3 + .global sys_call4 + .global sys_call5 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_syscall0, up_syscall1, up_syscall2, up_syscall3 + * + * Description: + * up_syscall0 - System call SYS_ argument and no additional parameters. + * up_syscall1 - System call SYS_ argument and one additional parameter. + * up_syscall2 - System call SYS_ argument and two additional parameters. + * up_syscall3 - System call SYS_ argument and three additional parameters. + * up_syscall4 - System call SYS_ argument and four additional parameters. + * up_syscall5 - System call SYS_ argument and five additional parameters. + * + * Assumption: + * All interrupts are disabled except for the software interrupts. + * + ****************************************************************************/ + + .text + +sys_call0: /* a0 holds the syscall number */ +sys_call1: /* a0 holds the syscall number, argument in a1 */ +sys_call2: /* a0 holds the syscall number, arguments in a1 and a2 */ +sys_call3: /* a0 holds the syscall number, arguments in a1, a2, and a3 */ +sys_call4: /* a0 holds the syscall number, arguments in a1, a2, a3 and a4 */ +sys_call5: /* a0 holds the syscall number, arguments in a1, a2, a3, a4 and a5 */ + + /* Issue the ECALL opcode to perform a SW interrupt to the OS */ + + ecall + + /* The actual interrupt may not a occur for a few more cycles. Let's + * put a few nop's here in hope that the SW interrupt occurs during + * the sequence of nops. + */ + + nop + nop + + /* Then return with the result of the software interrupt in v0 */ + + ret + nop + diff --git a/arch/risc-v/src/rv32im/up_unblocktask.c b/arch/risc-v/src/rv32im/up_unblocktask.c new file mode 100644 index 0000000000..1b7350e05b --- /dev/null +++ b/arch/risc-v/src/rv32im/up_unblocktask.c @@ -0,0 +1,163 @@ +/**************************************************************************** + * arch/risc-v/src/rv32im/up_unblocktask.c + * + * Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "group/group.h" +#include "clock/clock.h" +#include "up_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_unblock_task + * + * Description: + * A task is currently in an inactive task list + * but has been prepped to execute. Move the TCB to the + * ready-to-run list, restore its context, and start execution. + * + * Inputs: + * tcb: Refers to the tcb to be unblocked. This tcb is + * in one of the waiting tasks lists. It must be moved to + * the ready-to-run list and, if it is the highest priority + * ready to run task, executed. + * + ****************************************************************************/ + +void up_unblock_task(struct tcb_s *tcb) +{ + struct tcb_s *rtcb = this_task(); + + /* Verify that the context switch can be performed */ + + ASSERT((tcb->task_state >= FIRST_BLOCKED_STATE) && + (tcb->task_state <= LAST_BLOCKED_STATE)); + + /* Remove the task from the blocked task list */ + + sched_removeblocked(tcb); + + /* Add the task in the correct location in the prioritized + * ready-to-run task list + */ + + if (sched_addreadytorun(tcb)) + { + /* The currently active task has changed! We need to do + * a context switch to the new task. + */ + + /* Update scheduler parameters */ + + sched_suspend_scheduler(rtcb); + + /* Are we in an interrupt handler? */ + + if (g_current_regs) + { + /* Yes, then we have to do things differently. + * Just copy the g_current_regs into the OLD rtcb. + */ + + up_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + + /* Update scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + up_restorestate(rtcb->xcp.regs); + } + + /* No, then we will need to perform the user context switch */ + + else + { + /* Restore the exception context of the new task that is ready to + * run (probably tcb). This is the new rtcb at the head of the + * ready-to-run task list. + */ + + struct tcb_s *nexttcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(nexttcb); +#endif + /* Update scheduler parameters */ + + sched_resume_scheduler(nexttcb); + + /* Then switch contexts */ + + up_switchcontext(rtcb->xcp.regs, nexttcb->xcp.regs); + + /* up_switchcontext forces a context switch to the task at the + * head of the ready-to-run list. It does not 'return' in the + * normal sense. When it does return, it is because the blocked + * task is again ready to run and has execution priority. + */ + } + } +} diff --git a/arch/risc-v/src/rv32im/up_vfork.c b/arch/risc-v/src/rv32im/up_vfork.c new file mode 100644 index 0000000000..f2f5332bec --- /dev/null +++ b/arch/risc-v/src/rv32im/up_vfork.c @@ -0,0 +1,262 @@ +/**************************************************************************** + * arch/mips/src/mips32/up_vfork.c + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "up_vfork.h" +#include "sched/sched.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STACK_ALIGNMENT +# define CONFIG_STACK_ALIGNMENT 4 +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_vfork + * + * Description: + * The vfork() function has the same effect as fork(), except that the + * behavior is undefined if the process created by vfork() either modifies + * any data other than a variable of type pid_t used to store the return + * value from vfork(), or returns from the function in which vfork() was + * called, or calls any other function before successfully calling _exit() + * or one of the exec family of functions. + * + * The overall sequence is: + * + * 1) User code calls vfork(). vfork() collects context information and + * transfers control up up_vfork(). + * 2) up_vfork()and calls task_vforksetup(). + * 3) task_vforksetup() allocates and configures the child task's TCB. This + * consists of: + * - Allocation of the child task's TCB. + * - Initialization of file descriptors and streams + * - Configuration of environment variables + * - Setup the intput parameters for the task. + * - Initialization of the TCB (including call to up_initial_state() + * 4) up_vfork() provides any additional operating context. up_vfork must: + * - Allocate and initialize the stack + * - Initialize special values in any CPU registers that were not + * already configured by up_initial_state() + * 5) up_vfork() then calls task_vforkstart() + * 6) task_vforkstart() then executes the child thread. + * + * task_vforkabort() may be called if an error occurs between steps 3 and 6. + * + * Input Paremeters: + * context - Caller context information saved by vfork() + * + * Return: + * Upon successful completion, vfork() returns 0 to the child process and + * returns the process ID of the child process to the parent process. + * Otherwise, -1 is returned to the parent, no child process is created, + * and errno is set to indicate the error. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_HAVE_VFORK + +#error This part of the port is not done yet!! + +pid_t up_vfork(const struct vfork_s *context) +{ + struct tcb_s *parent = this_task(); + struct task_tcb_s *child; + size_t stacksize; + uint32_t newsp; +#ifdef CONFIG_MIPS32_FRAMEPOINTER + uint32_t newfp; +#endif + uint32_t stackutil; + int ret; + + sinfo("s0:%08x s1:%08x s2:%08x s3:%08x s4:%08x\n", + context->s0, context->s1, context->s2, context->s3, context->s4); +#ifdef CONFIG_MIPS32_FRAMEPOINTER + sinfo("s5:%08x s6:%08x s7:%08x\n", + context->s5, context->s6, context->s7); +#ifdef MIPS32_SAVE_GP + sinfo("fp:%08x sp:%08x ra:%08x gp:%08x\n", + context->fp, context->sp, context->ra, context->gp); +#else + sinfo("fp:%08x sp:%08x ra:%08x\n", + context->fp context->sp, context->ra); +#endif +#else + sinfo("s5:%08x s6:%08x s7:%08x s8:%08x\n", + context->s5, context->s6, context->s7, context->s8); +#ifdef MIPS32_SAVE_GP + sinfo("sp:%08x ra:%08x gp:%08x\n", + context->sp, context->ra, context->gp); +#else + sinfo("sp:%08x ra:%08x\n", + context->sp, context->ra); +#endif +#endif + + /* Allocate and initialize a TCB for the child task. */ + + child = task_vforksetup((start_t)context->ra); + if (!child) + { + sinfo("task_vforksetup failed\n"); + return (pid_t)ERROR; + } + + sinfo("Parent=%p Child=%p\n", parent, child); + + /* Get the size of the parent task's stack. Due to alignment operations, + * the adjusted stack size may be smaller than the stack size originally + * requrested. + */ + + stacksize = parent->adj_stack_size + CONFIG_STACK_ALIGNMENT - 1; + + /* Allocate the stack for the TCB */ + + ret = up_create_stack((FAR struct tcb_s *)child, stacksize, + parent->flags & TCB_FLAG_TTYPE_MASK); + if (ret != OK) + { + serr("ERROR: up_create_stack failed: %d\n", ret); + task_vforkabort(child, -ret); + return (pid_t)ERROR; + } + + /* How much of the parent's stack was utilized? The MIPS uses + * a push-down stack so that the current stack pointer should + * be lower than the initial, adjusted stack pointer. The + * stack usage should be the difference between those two. + */ + + DEBUGASSERT((uint32_t)parent->adj_stack_ptr > context->sp); + stackutil = (uint32_t)parent->adj_stack_ptr - context->sp; + + sinfo("stacksize:%d stackutil:%d\n", stacksize, stackutil); + + /* Make some feeble effort to perserve the stack contents. This is + * feeble because the stack surely contains invalid pointers and other + * content that will not work in the child context. However, if the + * user follows all of the caveats of vfork() usage, even this feeble + * effort is overkill. + */ + + newsp = (uint32_t)child->cmn.adj_stack_ptr - stackutil; + memcpy((void *)newsp, (const void *)context->sp, stackutil); + + /* Was there a frame pointer in place before? */ + +#ifdef CONFIG_MIPS32_FRAMEPOINTER + if (context->fp <= (uint32_t)parent->adj_stack_ptr && + context->fp >= (uint32_t)parent->adj_stack_ptr - stacksize) + { + uint32_t frameutil = (uint32_t)parent->adj_stack_ptr - context->fp; + newfp = (uint32_t)child->cmn.adj_stack_ptr - frameutil; + } + else + { + newfp = context->fp; + } + + sinfo("Old stack base:%08x SP:%08x FP:%08x\n", + parent->adj_stack_ptr, context->sp, context->fp); + sinfo("New stack base:%08x SP:%08x FP:%08x\n", + child->cmn.adj_stack_ptr, newsp, newfp); +#else + sinfo("Old stack base:%08x SP:%08x\n", + parent->adj_stack_ptr, context->sp); + sinfo("New stack base:%08x SP:%08x\n", + child->cmn.adj_stack_ptr, newsp); +#endif + + /* Update the stack pointer, frame pointer, global pointer and saved + * registers. When the child TCB was initialized, all of the values + * were set to zero. up_initial_state() altered a few values, but the + * return value in v0 should be cleared to zero, providing the + * indication to the newly started child thread. + */ + + child->cmn.xcp.regs[REG_S0] = context->s0; /* Saved register s0 */ + child->cmn.xcp.regs[REG_S1] = context->s1; /* Saved register s1 */ + child->cmn.xcp.regs[REG_S2] = context->s2; /* Saved register s2 */ + child->cmn.xcp.regs[REG_S3] = context->s3; /* Volatile register s3 */ + child->cmn.xcp.regs[REG_S4] = context->s4; /* Volatile register s4 */ + child->cmn.xcp.regs[REG_S5] = context->s5; /* Volatile register s5 */ + child->cmn.xcp.regs[REG_S6] = context->s6; /* Volatile register s6 */ + child->cmn.xcp.regs[REG_S7] = context->s7; /* Volatile register s7 */ +#ifdef CONFIG_MIPS32_FRAMEPOINTER + child->cmn.xcp.regs[REG_FP] = newfp; /* Frame pointer */ +#else + child->cmn.xcp.regs[REG_S8] = context->s8; /* Volatile register s8 */ +#endif + child->cmn.xcp.regs[REG_SP] = newsp; /* Stack pointer */ +#ifdef MIPS32_SAVE_GP + child->cmn.xcp.regs[REG_GP] = newsp; /* Global pointer */ +#endif + + /* And, finally, start the child task. On a failure, task_vforkstart() + * will discard the TCB by calling task_vforkabort(). + */ + + return task_vforkstart(child); +} + +#endif /* CONFIG_ARCH_HAVE_VFORK */ + diff --git a/arch/risc-v/src/rv32im/up_vfork.h b/arch/risc-v/src/rv32im/up_vfork.h new file mode 100644 index 0000000000..079a744c83 --- /dev/null +++ b/arch/risc-v/src/rv32im/up_vfork.h @@ -0,0 +1,132 @@ +/**************************************************************************** + * arch/mips/src/mips/up_vfork.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_MIPS32_VFORK_H +#define __ARCH_MIPS_SRC_MIPS32_VFORK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Register r30 may be a frame pointer in some ABIs. Or may just be saved + * register s8. It makes a difference for vfork handling. + */ + +#undef VFORK_HAVE_FP + +/* r0 zero Always has the value 0. + * r1 at Temporary generally used by assembler. + * r2-r3 v0-v1 Used for expression evaluations and to hold the integer and + * pointer type function return values. + * r4-r7 a0-a3 Used for passing arguments to functions; values are not + * preserved across function calls. + * r8-r15 t0-t7 Temporary registers used for expression evaluation; values + * are not preserved across function calls. + * r16-r23 s0-s7 Saved registers; values are preserved across function calls. + * r24-r25 t8-t9 Temporary registers used for expression evaluations; values + * are not preserved across function calls. When calling + * position independent functions r25 must contain the address + * of the called function. + * r26-r27 k0-k1 Used only by the operating system. + * r28 gp Global pointer and context pointer. + * r29 sp Stack pointer. + * r30 s8 Saved register (like s0-s7). If a frame pointer is used, + * then this is the frame pointer. + * r31 ra Return address. + */ + +#define VFORK_S0_OFFSET (0*4) /* Saved register s0 */ +#define VFORK_S1_OFFSET (1*4) /* Saved register s1 */ +#define VFORK_S2_OFFSET (2*4) /* Saved register s2 */ +#define VFORK_S3_OFFSET (3*4) /* Saved register s3 */ +#define VFORK_S4_OFFSET (4*4) /* Saved register s4 */ +#define VFORK_S5_OFFSET (5*4) /* Saved register s5 */ +#define VFORK_S6_OFFSET (6*4) /* Saved register s6 */ +#define VFORK_S7_OFFSET (7*4) /* Saved register s7 */ + +#ifdef CONFIG_MIPS32_FRAMEPOINTER +# define VFORK_FP_OFFSET (8*4) /* Frame pointer */ +#else +# define VFORK_S8_OFFSET (8*4) /* Saved register s8 */ +#endif + +#define VFORK_SP_OFFSET (9*4) /* Stack pointer*/ +#define VFORK_RA_OFFSET (10*4) /* Return address*/ +#ifdef MIPS32_SAVE_GP +# define VFORK_GP_OFFSET (11*4) /* Global pointer */ +# define VFORK_SIZEOF (12*4) +#else +# define VFORK_SIZEOF (11*4) +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +struct vfork_s +{ + /* CPU registers */ + + uint32_t s0; /* Saved register s0 */ + uint32_t s1; /* Saved register s1 */ + uint32_t s2; /* Saved register s2 */ + uint32_t s3; /* Saved register s3 */ + uint32_t s4; /* Saved register s4 */ + uint32_t s5; /* Saved register s5 */ + uint32_t s6; /* Saved register s6 */ + uint32_t s7; /* Saved register s7 */ +#ifdef CONFIG_MIPS32_FRAMEPOINTER + uint32_t fp; /* Frame pointer */ +#else + uint32_t s8; /* Saved register s8 */ +#endif + uint32_t sp; /* Stack pointer*/ + uint32_t ra; /* Return address*/ +#ifdef MIPS32_SAVE_GP + uint32_t gp; /* Global pointer */ +#endif + + /* Floating point registers (not yet) */ +}; +#endif + +#endif /* __ARCH_MIPS_SRC_MIPS32_VFORK_H */ diff --git a/configs/Kconfig b/configs/Kconfig index 2b629c1a4f..3e08a0dba4 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -673,6 +673,14 @@ config ARCH_BOARD_PIRELLI_DPL10 This directory contains the board support for Pirelli dpl10 phones. The additions were made by Craig Comstock (with help form Alan Carvalho de Assis). +config ARCH_BOARD_NR5M100_NEXYS4 + bool "NEXT RISC-V NR5M100 on Nexys-4 board" + depends on ARCH_CHIP_NR5M100 + select UART_SERIALDRIVER + ---help--- + This is the port NuttX to the NEXT RISC-V processor runnining on a Digilent + Nexys-4 (non DDR version) FPGA board. + config ARCH_BOARD_NUCLEO_144 bool "STMicro NUCLEO-144" depends on ARCH_CHIP_STM32F746ZG || ARCH_CHIP_STM32F767ZI @@ -1413,6 +1421,7 @@ config ARCH_BOARD default "ne64badge" if ARCH_BOARD_NE64BADGE default "ntosd-dm320" if ARCH_BOARD_NTOSD_DM320 default "nutiny-nuc120" if ARCH_BOARD_NUTINY_NUC120 + default "nr5m100-nexys4" if ARCH_BOARD_NR5M100_NEXYS4 default "olimex-efm32g880f128-stk" if ARCH_BOARD_OLIMEX_EFM32G880F128_STK default "olimex-lpc1766stk" if ARCH_BOARD_LPC1766STK default "olimex-lpc2378" if ARCH_BOARD_OLIMEXLPC2378 diff --git a/configs/README.txt b/configs/README.txt index 8bf546a298..9bd796ffa7 100644 --- a/configs/README.txt +++ b/configs/README.txt @@ -551,6 +551,9 @@ configs/rgmp See http://rgmp.sourceforge.net/wiki/index.php/Main_Page for further information about RGMP. +configs/nr5m100-nexys4 + Port of NuttX to RISC-V platform on IQ-Analog NR5M100 RISC-V FPGA platform. + configs/sabre-6quad This directory holds a port of NuttX to the NXP/Freescale Sabre board featuring the iMX 6Quad CPU. diff --git a/configs/nr5m100-nexys4/Kconfig b/configs/nr5m100-nexys4/Kconfig new file mode 100644 index 0000000000..8824428a4d --- /dev/null +++ b/configs/nr5m100-nexys4/Kconfig @@ -0,0 +1,9 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +if ARCH_BOARD_NR5M100_NEXYS4 + + +endif diff --git a/configs/nr5m100-nexys4/README.txt b/configs/nr5m100-nexys4/README.txt new file mode 100644 index 0000000000..fc939aa4c6 --- /dev/null +++ b/configs/nr5m100-nexys4/README.txt @@ -0,0 +1,251 @@ +README +====== + +This README discusses issues unique to NuttX configurations for the +IQ-Analog NR5M100 FPGA implementation of a RISC-V core on the Digilent +Nexys4 FPGA board. + +The port is currently very minimal, though additional support may be +added in the future to address more of the board peripherals supplied +on the FPGA board. Those peripherals include: + + Supported: + - USB UART (console port) + - 16 single color LEDs + - 16 slide switch inputs + - Two tri-color LEDs + - 5 Joystick style pushbuttons + - 16 GPIO pins on 2 of the PMOD expansion connectors + + Not supported: + - VGA display port + - 8 digit 7-segement display + - SD card slot + - SPI FLASH memory (shared with FPGA configuration data). + - USB HID (single device) connector serviced by external PIC uC + - Non-DDR (older version): 16 MB Cellular SRAM + - DDR (newer version): 128 MB DDR2 SDRAM + - Microphone + - 10/100 Ethernet PHY + - 3-Axis accelerometer + - Temperature sensor + +See http://store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-board-recommended-for-ece-curriculum/ +or http://store.digilentinc.com/nexys-4-artix-7-fpga-trainer-board-limited-time-see-nexys4-ddr/ +for more information about these boards. + +Contents +======== + + - NR5M100 Overview + - Development Environment + - GNU Toolchain Options + - Debugger + - IDEs + - LEDs + - PWM + - UARTs + - Timer Inputs/Outputs + - FSMC SRAM + - SSD1289 + - Mikroe-STM32F4-specific Configuration Options + - Configurations + +Development Environment +======================= + The NR5M100 RISC-V core was designed as a low gate count / low performance micro controller + for inclusion in an ASIC. It is based on a Verilog RISC-V called picorv32, but has many + additions beyond that baseline. The design running on the Digilent Nexys4 FPGA is a + validation platform for the core and is presented as an open source project. + + The reason NR5M100 is "low performance" is that it is a state machine based core (like the + picorv32) and not a multi-stage pipeline core. This means that it requires an average of + 4.5 clock cycles to execute each instruction. On a multi-stage pipeline architecure, this + average would be closer to 1 clock cycle per instruction (though a bit higher due to + pipeline branch misses). The tradeoff for lower performance is a simpler design. There + is a single memory bus interface for both instructions and data. Multi-stage pipeline + cores require a separate I and D bus with cache SRAM and an external memory cache controller, + etc. This in addition to the pipeline registers adds additional gate count. + + The nr5m100-nexys4 core runs at 83.333 Mhz which provides about 18 Mhz effective operating + speed with the multi-clock per instruction architecture. If you are looking for a higher + performance platform, you should check out the PULP Platform ( http://www.pulp-platform.org ). + That is an FPGA design with a 4-stage pipeline RISC-V core, though not currently supported + by NuttX. The NR5M100 project will likely pull in the RISC-V core from that design next, + though this will probably not be available soon. With a bit of work, it is possible to + run the nr5m100-nexys4 core at 170 Mhz with a 6.5 clocks-per-instruction state machine. + This would give an effective performance of about 26Mhz. + +Development Environment +======================= + + Linux is the best choice for development, though Cygwin on Windows may work. + The source has been built only using the GNU toolchain (see below) under a Linux + environment. Other toolchains will likely cause problems or not be available yet. + +RISC-V GNU Toolchain +==================== + + To compile the code, you must first build a RISC-V GNU Toolchain from the sources at + https://github.com/riscv/riscv-gnu-toolchain. I don't know of any sources for pre-compiled + toolchains (though there may be some out there). + + To build this toolchain, follow these instructions (tested on Ubuntu 12.04): + + 1. Create a working directory in your home folder: + + mkdir ~/riscv + cd ~/riscv + + 2. Clone the GNU source tree: + + git clone --recursive https://github.com/riscv/riscv-gnu-toolchain + + 3. Ensure the following packages are installed: + + sudo apt-get install texinfo bison flex autoconf automake libgmp-dev libmpfr-dev libmpc-dev + + 4. Configure and build the toolchain: + + cd riscv-gnu-toolchain + ./configure --with-xlen=64 --with-arch=I --disable-float --disable-atomic --enable-multilib --prefix=~/riscv + make -j4 (or -j8 based on how many cores you have) + + 5. Setup your PATH environment variable to include the toolchain (you may want to add this to + your shell login script, such as .bash_profile, etc.): + + export PATH=~/riscv/bin:$PATH + + Windows based toolchain + ----------------------- + May be possible to compile the GNU toolchain described above using Cygwin, but havne't tried it. + +Debugger +======== + The Debug Module within the NR5M100 RISC-V has been designed to work with the RISC-V gdb + debugger interfaced with the SiFive implementation of OpenOCD. The interface has been tested + with a J-LINK JTAG probe connected to PMOD header B on the FPGA using an adapter board + that I designed and fabbed at OSHPark. I will update this README.txt file soon with a link + to the shared project for anyone who wishes to build one. + + To build OpenOCD, perform the following: + + 1. Ensure the proper packages are installed: + + sudo apt-get install autoconf automake libtool libusb-1.0-0-dev + + 2. Download the latest OpenOCD sources from the SiFive github repo: + + cd ~/riscv + git clone --recursive https://github.com/sifive/openocd.git + + 3. Configure and build OpenOCD. The x86_64 GCC compilers will give errors because of + shadowed variable warnings, so diable the -Werror flag also: + + cd openocd + sed -i 's/ -Werror//g' configure.ac + ./bootstrap + ./configure --enable-jlink --enable-maintainer-mode --enable-ftdi --prefix=~/riscv CFLAGS=-g + + The configuration scripts for openocd and nr5m100-nexys4 have been provided in the + nuttx/configs/nr5m100-nexys4/scripts directory. They are configured to use a J-LINK JTAG + probe and to search for the IQ-Analog (the company I work for) IDCODE and part number for + the FPGA board (7a10 for Artix xc7a100 part on the Digilent Nexys4 board). With FPGA + source directly from the nr5m100 github site (to be provided), this ID will match the + hardware. If changes are made to the JEDEC ID and/or part number, then the nr5m100.cfg + file will need to be modified with the proper CPUID value. + +IDEs +==== + + NuttX is built using command-line make. It can be used with an IDE, but some + effort will be required to create the project. While I haven't tried it as + I am not an IDE guy, the team at SiFive have reported that they now have + Eclipse working with the RISC-V gdb debugger. + + NOTE: The notes below are taken from an ARM build of NuttX, not RISC-V, so + they may or may not work. Try it and see I suppose. + + Makefile Build + -------------- + Under Eclipse, it is pretty easy to set up an "empty makefile project" and + simply use the NuttX makefile to build the system. That is almost for free + under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty + makefile project in order to work with Windows (Google for "Eclipse Cygwin" - + there is a lot of help on the internet). + + Native Build + ------------ + Here are a few tips before you start that effort: + + 1) Select the toolchain that you will be using in your .config file + 2) Start the NuttX build at least one time from the Cygwin command line + before trying to create your project. This is necessary to create + certain auto-generated files and directories that will be needed. + 3) Set up include pathes: You will need include/, arch/risc-v/src/rv32im, + arch/risc-v/src/common, arch/risc-v/src/nr5m100, and sched/. + 4) All assembly files need to have the definition option -D __ASSEMBLY__ + on the command line. + + Startup files will probably cause you some headaches. The NuttX startup file + is arch/risc-v/src/nr5m100/nr5_vectors.S. With RIDE, I build NuttX + one time from the Cygwin command line in order to obtain the pre-built + startup object needed by RIDE. + +LEDs +==== + +The Nexys4 board has 16 single-color LEDs onboard, as well as 2 tri-color LEDs. +These are supported using GPIO Ports A (16-single color) and B (tri-color). +Additionally the tri-color LEDs can be driven from the Timer 1 or 2 PWM output +signals. + +PWM +=== + +The nr5m100-nexys4 design has PWM capabilities within the Timer 1 and Timer 2 +modules. These PWM signals can be muxed to the tri-color LEDs or to I/O +pins on one of the PMOD expansion headers. + +UARTs +===== + +The nr5m100-nexys4 design has an onboard USB-UART providing an RS-232 interface +via the same USB cable that is used to program the FPGA. The core proivdes a +fixed 8-Data bit, 1 stop bit, no parity UART connected to this intrface. + +UART PINS +--------- + +UART1 + RX FPGA C4 (USB UART device) + TX FPGA D4 (USB UART device) + +Default USART/UART Configuration +-------------------------------- + +UART1 is enabled in all configurations (see */defconfig). + +Configurations +============== + +Each nr5m100-nexys4 configuration is maintained in a sub-directory and +can be selected as follow: + + cd tools + ./configure.sh nr5m100-nexys4/ + cd - + . ./setenv.sh + +If this is a Windows native build, then configure.bat should be used +instead of configure.sh: + + configure.bat nr5m100-nexys4\ + +Where is one of the following: + + nsh + --- + This is an NSH example that uses UART1 as the console. UART1 is connected + to the USB UART bridge on the FPGA board. + diff --git a/configs/nr5m100-nexys4/include/board.h b/configs/nr5m100-nexys4/include/board.h new file mode 100644 index 0000000000..366c3007d1 --- /dev/null +++ b/configs/nr5m100-nexys4/include/board.h @@ -0,0 +1,178 @@ +/************************************************************************************ + * configs/nr5m100-nexys4/include/board.h + * include/arch/board/board.h + * + * Copyright (C) 2012-2013, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for NR5M100: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIG_NR5M100_NEXYS4_INCLUDE_BOARD_H +#define __CONFIG_NR5M100_NEXYS4_INCLUDE_BOARD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +#include "nr5.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ +/* The NR5M100_Nexys4 system uses a 100 MHz main oscillator */ + +#define NR5_HCLK_FREQUENCY 100000000ul +#define NR5_SCLK_FREQUENCY 100000000ul + +//#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* Timer Frequencies are the same as the HCLK frequency + */ + +#define NR5_TIMER_FREQUENCY NR5_HCLK_FREQUENCY + +/* LED definitions ******************************************************************/ +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any + * way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with stm32_setled() */ + +#if 0 +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#endif +#define BOARD_NLEDS 0 + +#if 1 +#define BOARD_LED_GREEN BOARD_LED1 +#define BOARD_LED_ORANGE BOARD_LED2 +#define BOARD_LED_RED BOARD_LED3 +#define BOARD_LED_BLUE BOARD_LED4 + +/* LED bits for use with nr5_setleds() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on board the + * stm32f4discovery. The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions ***************************************************************/ +/* The STM32F4 Discovery supports one button: */ + +#define BUTTON_USER 0 + +#define NUM_BUTTONS 5 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +#endif /* 0 */ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ +/************************************************************************************ + * Name: nr5_boardinitialize + * + * Description: + * All NR5 architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void nr5_boardinitialize(void); + +/************************************************************************************ + * Name: nr5_ledinit, nr5_setled, and nr5_setleds + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board LEDs. If + * CONFIG_ARCH_LEDS is not defined, then the following interfacesare available to + * control the LEDs from user applications. + * + ************************************************************************************/ + +#ifndef CONFIG_ARCH_LEDS +void nr5_ledinit(void); +void nr5_setled(int led, bool ledon); +void nr5_setleds(uint8_t ledset); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIG_NR5M100_NEXYS4_INCLUDE_BOARD_H */ + diff --git a/configs/nr5m100-nexys4/nsh/Make.defs b/configs/nr5m100-nexys4/nsh/Make.defs new file mode 100644 index 0000000000..190f6def74 --- /dev/null +++ b/configs/nr5m100-nexys4/nsh/Make.defs @@ -0,0 +1,114 @@ +############################################################################ +# configs/stm32f4discovery/nsh/Make.defs +# +# Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/risc-v/src/rv32im/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g + ASARCHCPUFLAGS += -Wa,-g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS += $(CFLAGS) -D__ASSEMBLY__ $(ASARCHCPUFLAGS) + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs -melf32lriscv +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g -melf32lriscv +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/nr5m100-nexys4/nsh/defconfig b/configs/nr5m100-nexys4/nsh/defconfig new file mode 100644 index 0000000000..bfd3fc4fc2 --- /dev/null +++ b/configs/nr5m100-nexys4/nsh/defconfig @@ -0,0 +1,800 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +# CONFIG_ARCH_HAVE_STACKCHECK is not set +# CONFIG_ARCH_HAVE_HEAPCHECK is not set +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_RENESAS is not set +CONFIG_ARCH_RISCV=y +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_CHIP="nr5m100" +# CONFIG_SERIAL_TERMIOS is not set + +# +# RISC-V Options +# +CONFIG_ARCH_CHIP_NR5M100=y +# CONFIG_ARCH_RV32I is not set +CONFIG_ARCH_RV32IM=y + +# +# RV32IM Configuration Options +# +CONFIG_RV32IM_TOOLCHAIN_GNU_RVGL=y +CONFIG_RV32IM_HW_MULDIV=y +CONFIG_RV32IM_SYSTEM_CSRRS_SUPPORT=y +# CONFIG_RV32IM_CUSTOM_IRQ_SUPPORT is not set + +# +# NanoRisc5 Configuration Options +# +CONFIG_NR5_NR5M100=y +CONFIG_NR5_NR5M1XX=y +# CONFIG_NR5_EPIC is not set + +# +# NR5 Peripheral Support +# +CONFIG_NR5_HAVE_UART1=y +CONFIG_NR5_HAVE_TIMER1=y +# CONFIG_NR5_HAVE_TIM2 is not set +# CONFIG_NR5_HAVE_I2C1 is not set +# CONFIG_NR5_HAVE_SPI1 is not set +# CONFIG_NR5_I2C1 is not set +# CONFIG_NR5_SPI1 is not set +CONFIG_NR5_TIMER1=y +CONFIG_NR5_TIMER2=y +CONFIG_NR5_UART1=y +CONFIG_NR5_UART=y +CONFIG_NR5_UART_RX_BUF_SIZE=64 +CONFIG_NR5_UART_TX_BUF_SIZE=64 + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +# CONFIG_ARCH_HAVE_IRQPRIO is not set +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +# CONFIG_ARCH_HAVE_VFORK is not set +# CONFIG_ARCH_HAVE_MMU is not set +# CONFIG_ARCH_HAVE_MPU is not set +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +# CONFIG_ARCH_HAVE_RESET is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +# CONFIG_ARCH_HAVE_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_ARCH_CALIBRATION=y + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_SIZE=114688 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_NR5M100_NEXYS4=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="nr5m100-nexys4" + +# +# Common Board Options +# + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_ADCTEST is not set +# CONFIG_BOARDCTL_PWMTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Clocks and Timers +# +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2013 +CONFIG_START_MONTH=1 +CONFIG_START_DAY=27 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=0 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +# CONFIG_SCHED_WAITPID is not set + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +# CONFIG_SDCLONE_DISABLE is not set +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=32 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_HPWORK is not set +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +CONFIG_DEV_ZERO=y +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +# CONFIG_ARCH_HAVE_I2CRESET is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +CONFIG_UART_SERIALDRIVER=y +# CONFIG_UART0_SERIALDRIVER is not set +CONFIG_UART1_SERIALDRIVER=y +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +# CONFIG_UART_SERIAL_CONSOLE is not set +CONFIG_UART1_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART Configuration +# +CONFIG_UART_RXBUFSIZE=256 +CONFIG_UART_TXBUFSIZE=256 +CONFIG_UART_BAUD=115200 +CONFIG_UART_BITS=8 +CONFIG_UART_PARITY=0 +CONFIG_UART_2STOP=0 +# CONFIG_UART_IFLOWCONTROL is not set +# CONFIG_UART_OFLOWCONTROL is not set +# CONFIG_UART_DMA is not set + +# +# UART1 Configuration +# +CONFIG_UART1_RXBUFSIZE=256 +CONFIG_UART1_TXBUFSIZE=256 +CONFIG_UART1_BAUD=115200 +CONFIG_UART1_BITS=8 +CONFIG_UART1_PARITY=0 +CONFIG_UART1_2STOP=0 +# CONFIG_UART1_IFLOWCONTROL is not set +# CONFIG_UART1_OFLOWCONTROL is not set +# CONFIG_UART1_DMA is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +# CONFIG_SYSLOG_SERIAL_CONSOLE is not set +# CONFIG_SYSLOG_CHAR is not set +# CONFIG_SYSLOG_CONSOLE is not set +CONFIG_SYSLOG_NONE=y +# CONFIG_SYSLOG_FILE is not set +# CONFIG_CONSOLE_SYSLOG is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_FS_READABLE is not set +CONFIG_FS_WRITABLE=y +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +CONFIG_LIBC_STRERROR=y +# CONFIG_LIBC_STRERROR_SHORT is not set +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_TMPDIR="/tmp" +CONFIG_LIBC_MAX_TMPFILE=32 +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +# CONFIG_ARCH_HAVE_TLS is not set +# CONFIG_LIBC_NETDB is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +# CONFIG_CXX_NEWLONG is not set + +# +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_CXXTEST is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=64 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +CONFIG_NSH_CMDPARMS=y +CONFIG_NSH_MAXARGUMENTS=6 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +CONFIG_NSH_DISABLE_MKRD=y +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Configure Command Options +# +CONFIG_NSH_CMDOPT_DF_H=y +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_CMDOPT_HEXDUMP=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_STRERROR=y + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/nr5m100-nexys4/nsh/setenv.sh b/configs/nr5m100-nexys4/nsh/setenv.sh new file mode 100644 index 0000000000..8322085596 --- /dev/null +++ b/configs/nr5m100-nexys4/nsh/setenv.sh @@ -0,0 +1,45 @@ +#!/bin/bash +# configs/nr5m100-nexys4/nsh/setenv.sh +# +# Copyright (C) 2008 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$(basename $0)" = "setenv.sh" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi + +#export NUTTX_BIN= +#export PATH=${NUTTX_BIN}:/sbin:/usr/sbin:${PATH_ORIG} + +echo "PATH : ${PATH}" diff --git a/configs/nr5m100-nexys4/scripts/ld.script b/configs/nr5m100-nexys4/scripts/ld.script new file mode 100644 index 0000000000..df856beb23 --- /dev/null +++ b/configs/nr5m100-nexys4/scripts/ld.script @@ -0,0 +1,305 @@ +/**************************************************************************** + * configs/nr5m100-nexys4/scripts/ld.script + * + * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Ken Pettit. + * Author: Gregory Nutt + * Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/*======================================================================*/ +/* Linker script for nr5m100_nexys board */ +/*======================================================================*/ + +/*----------------------------------------------------------------------*/ +/* Setup */ +/*----------------------------------------------------------------------*/ + +/* The OUTPUT_ARCH command specifies the machine architecture where the + argument is one of the names used in the BFD library. More + specifically one of the entires in bfd/cpu-mips.c */ + +OUTPUT_ARCH( "riscv" ) + +/* Define the memory regions were we put stuff */ +MEMORY +{ + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 384K +} + +stack_size = 4096; + +/* Define the beginning and ending stack */ +__stack_start = ORIGIN(sram) + LENGTH(sram); +__stack_end = __stack_start - stack_size; + + +/* The ENTRY command specifies the entry point (ie. first instruction to + execute). The symbol _start is defined in crt0.S */ + +ENTRY( __reset ) + +/* The GROUP command is special since the listed archives will be + searched repeatedly until there are no new undefined references. We + need this since -lc depends on -lgloss and -lgloss depends on -lc. I + thought gcc would automatically include -lgcc when needed, but + idt32.ld includes it explicitly here and I was seeing link errors + without it. */ + +/*GROUP( -lc -lgloss -lgcc ) */ +GROUP( -lc ) + +/*----------------------------------------------------------------------*/ +/* Sections */ +/*----------------------------------------------------------------------*/ +/* This is where we specify how the input sections map to output + sections. The .= commands set the location counter, and the + sections are inserted in increasing address order according to the + location counter. The following statement will take all of the .bar + input sections and reloate them into the .foo output section which + starts at address 0x1000. + + . = 0.x1000; + .foo : { *(.bar) } + + If we wrap an input specification with a KEEP command then it + prevents it from being eliminted during "link-time garbage + collection". I'm not sure what this is, so I just followed what was + done in idt32.ld. + + We can also set a global external symbol to a specific address in the + output binary with this syntax: + + _etext = .; + PROVIDE( etext = . ); + + This will set the global symbol _ftext to the current location. If we + wrap this in a PROVIDE commad, the symbol will only be set if it is + not defined. We do this with symbols which don't begin with an + underscore since technically in ansi C someone might have a function + with the same name (eg. etext). + + If we need to label the beginning of a section we need to make sure + that the linker doesn't insert an orphan section inbetween where we + set the symbol and the actual begining of the section. We can do that + by assigning the location dot to itself. + + . = . + _ftext = .; + .text : + { } + + */ + +SECTIONS +{ + + /*--------------------------------------------------------------------*/ + /* Startup vectors + /*--------------------------------------------------------------------*/ + . = 0x20000000; + _vectors = .; + + /* vectors: Program code section */ + .vectors : + { + *(.text.vec) + *(.text.vec.*) + *(.gnu.linkonce.t.*) + } + _evectors = .; + + /*--------------------------------------------------------------------*/ + /* Code and read-only segment */ + /*--------------------------------------------------------------------*/ + + /* Begining of code and text segment */ + . = 0x20000030; + _ftext = .; + PROVIDE( eprol = . ); + + /* text: Program code section */ + .text : + { + _stext = ABSOLUTE(.); + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + } + + /* init: Code to execute before main (called by crt0.S) */ + .init : + { + KEEP( *(.init) ) + } + + /* fini: Code to execute after main (called by crt0.S) */ + .fini : + { + KEEP( *(.fini) ) + } + + /* rodata: Read-only data */ + _rodata = .; + .rodata : + { + *(.rdata) + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + } + + /* End of code and read-only segment */ + PROVIDE( etext = . ); + _etext = .; + + /*--------------------------------------------------------------------*/ + /* Global constructor/destructor segement */ + /*--------------------------------------------------------------------*/ + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array )) + PROVIDE_HIDDEN (__init_array_end = .); + } + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array )) + PROVIDE_HIDDEN (__fini_array_end = .); + } + + /*--------------------------------------------------------------------*/ + /* Other misc gcc segments (this was in idt32.ld) */ + /*--------------------------------------------------------------------*/ + /* I am not quite sure about these sections but it seems they are for + C++ exception handling. I think .jcr is for "Java Class + Registration" but it seems to end up in C++ binaries as well. */ + + .eh_frame_hdr : { *(.eh_frame_hdr) } + .eh_frame : { KEEP( *(.eh_frame) ) } + .gcc_except_table : { *(.gcc_except_table) } + .jcr : { KEEP (*(.jcr)) } + + /*--------------------------------------------------------------------*/ + /* Initialized data segment */ + /*--------------------------------------------------------------------*/ + + /* Start of initialized data segment */ + . = ALIGN(16); + _fdata = .; + + /* data: Writable data */ + _sdata = .; + .data : + { + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + } + + /* End of initialized data segment */ + PROVIDE( edata = . ); + _edata = .; + + /* Have _gp point to middle of sdata/sbss to maximize displacement range */ + . = ALIGN(16); + _gp = . + 0x7FF0; + + /* Writable small data segment */ + .sdata : + { + *(.sdata) + *(.sdata.*) + *(.srodata.*) + . = ALIGN(16); + *(.gnu.linkonce.s.*) + } + + /*--------------------------------------------------------------------*/ + /* Uninitialized data segment */ + /*--------------------------------------------------------------------*/ + + /* Start of uninitialized data segment */ + . = ALIGN(8); + _fbss = .; + + /* Writable uninitialized small data segment */ + .sbss : + { + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + } + + /* bss: Uninitialized writeable data section */ + . = .; + _bss_start = .; + .bss : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + } + _bss_end = .; + _ebss = .; + + /* End of uninitialized data segment (used by syscalls.c for heap) */ + . = ALIGN(16); + PROVIDE( end = . ); + _end = ALIGN(16); + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/nr5m100-nexys4/scripts/nr5m1xx.cfg b/configs/nr5m100-nexys4/scripts/nr5m1xx.cfg new file mode 100644 index 0000000000..9218333b82 --- /dev/null +++ b/configs/nr5m100-nexys4/scripts/nr5m1xx.cfg @@ -0,0 +1,64 @@ +############################################################################ +# configs/nr5m100-nexys4/scripts/nr5m1xx.cfg +# +# Copyright (C) 2016 Ken Pettit. All rights reserved. +# Author: Ken Pettit +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +proc init_board {} { + reset_config srst_only +} + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME nr5m1xx +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x1f40092d +} + +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x5 -irmask 0x1f -expected-id $_CPUTAPID +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME riscv -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x20018000 -work-area-size 0x2000 -work-area-backup 0 + diff --git a/configs/nr5m100-nexys4/scripts/openocd.cfg b/configs/nr5m100-nexys4/scripts/openocd.cfg new file mode 100644 index 0000000000..ea4564d84e --- /dev/null +++ b/configs/nr5m100-nexys4/scripts/openocd.cfg @@ -0,0 +1,61 @@ +############################################################################ +# configs/nr5m100-nexys4/scripts/openocd.cfg +# +# Copyright (C) 2016 Ken Pettit. All rights reserved. +# Author: Ken Pettit +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +#====================================== +# +# Define the interface +# +#===================================== + +interface jlink +adapter_khz 2000 + +#====================================== +# +# Define the target +# +#===================================== + +source [find nr5m1xx.cfg] + +#====================================== +# +# Init and halt the processor +# +#===================================== + +init +reset halt + diff --git a/configs/nr5m100-nexys4/src/Makefile b/configs/nr5m100-nexys4/src/Makefile new file mode 100644 index 0000000000..66a28f1b00 --- /dev/null +++ b/configs/nr5m100-nexys4/src/Makefile @@ -0,0 +1,90 @@ +############################################################################ +# configs/nr5m100-nexys4/src/Makefile +# +# Copyright (C) 2016 Ken Pettit. All rights reserved. +# Author: Ken Pettit +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +AOBJS = $(ASRCS:.S=$(OBJEXT)) + +CSRCS = nr5_appinit.c nr5_boot.c nr5_autoleds.c + +ifeq ($(CONFIG_ARCH_BOARD_NR5_CUSTOM_CLOCKCONFIG),y) +CSRCS += nr5_clockconfig.c +endif + +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src +ifeq ($(CONFIG_WINDOWS_NATIVE),y) + CFLAGS += -I$(ARCH_SRCDIR) -I$(ARCH_SRCDIR)\common -I$(ARCH_SRCDIR)\rv32im +else +ifeq ($(WINTOOL),y) + CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \ + -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \ + -I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}" +else + CFLAGS += -I$(ARCH_SRCDIR)/$(CONFIG_ARCH_CHIP) -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/rv32im +endif +endif + +all: libboard$(LIBEXT) + +$(AOBJS): %$(OBJEXT): %.S + $(call ASSEMBLE, $<, $@) + +$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +libboard$(LIBEXT): $(OBJS) + $(call ARCHIVE, $@, $(OBJS)) + +.depend: Makefile $(SRCS) + $(Q) $(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) touch $@ + +depend: .depend + +clean: + $(call DELFILE, libboard$(LIBEXT)) + $(call CLEAN) + +distclean: clean + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + +-include Make.dep diff --git a/configs/nr5m100-nexys4/src/nr5_appinit.c b/configs/nr5m100-nexys4/src/nr5_appinit.c new file mode 100644 index 0000000000..861f1d44a8 --- /dev/null +++ b/configs/nr5m100-nexys4/src/nr5_appinit.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * config/nr5m100-nexys4/src/nr5_appinit.c + * + * Copyright (C) 2012-2013, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "nr5.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform architecture specific initialization + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ + + return OK; +} diff --git a/configs/nr5m100-nexys4/src/nr5_autoleds.c b/configs/nr5m100-nexys4/src/nr5_autoleds.c new file mode 100644 index 0000000000..a35a6331cc --- /dev/null +++ b/configs/nr5m100-nexys4/src/nr5_autoleds.c @@ -0,0 +1,71 @@ +/************************************************************************************ + * configs/nr5m100_nexys4/src/nr5_autoleds.c + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: board_autoled_on + * + * Description: + * All NR5 architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void board_autoled_on(int led) +{ + +} diff --git a/configs/nr5m100-nexys4/src/nr5_boot.c b/configs/nr5m100-nexys4/src/nr5_boot.c new file mode 100644 index 0000000000..a98722566c --- /dev/null +++ b/configs/nr5m100-nexys4/src/nr5_boot.c @@ -0,0 +1,70 @@ +/************************************************************************************ + * configs/nr5m100_nexys4/src/nr5_boot.c + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: nr5_boardinitialize + * + * Description: + * All NR5 architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void nr5_boardinitialize(void) +{ +} -- GitLab From e7d791dd957a79bef641201e53bb3c37c0bb0957 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 16 Oct 2016 10:36:03 -0600 Subject: [PATCH 092/734] XTensa: Add an initial implementation of up_initialstate. Need to think through co-processor support. --- arch/xtensa/src/common/xtensa_context.S | 6 - arch/xtensa/src/common/xtensa_initialstate.c | 124 +++++++++++++++++++ arch/xtensa/src/esp32/Make.defs | 8 +- 3 files changed, 128 insertions(+), 10 deletions(-) create mode 100644 arch/xtensa/src/common/xtensa_initialstate.c diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index fb156fbfb2..407b78690c 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -335,12 +335,6 @@ _xtensa_context_restore: * Name: _xt_coproc_init * * Description: - * - * - ****************************************************************************/ - - - * Initializes global co-processor management data, setting all co- * processors to "unowned". Leaves CPENABLE as it found it (does NOT clear * it). diff --git a/arch/xtensa/src/common/xtensa_initialstate.c b/arch/xtensa/src/common/xtensa_initialstate.c new file mode 100644 index 0000000000..fe00a95e92 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_initialstate.c @@ -0,0 +1,124 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_initialstate.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "xtensa.h" +#include "xtensa_corebits.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_initial_state + * + * Description: + * A new thread is being started and a new TCB has been created. This + * function is called to initialize the processor specific portions of the + * new TCB. + * + * This function must setup the intial architecture registers and/or stack + * so that execution will begin at tcb->start on the next context switch. + * + ****************************************************************************/ + +void up_initial_state(struct tcb_s *tcb) +{ + struct xcptcontext *xcp = &tcb->xcp; +#if 0 /* REVISIT */ +#if CONFIG_XTENSA_NCOPROCESSORS > 0 + uint32_t *ptr; +#endif +#endif /* REVISIT */ + uint32_t regval; + + /* Initialize the initial exception register context structure */ + + memset(xcp, 0, sizeof(struct xcptcontext)); + + /* Set initial values of registers */ + + xcp->regs[REG_PC] = (uint32_t)tcb->start; /* Task entrypoint */ + xcp->regs[REG_A0] = 0; /* To terminate GDB backtrace */ + xcp->regs[REG_A1] = (uint32_t)tcb->adj_stack_ptr; /* Physical top of stack frame */ + xcp->regs[REG_EXIT] = (uint32_t)_xt_user_exit; /* User exception exit dispatcher */ + + /* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user + * mode. + */ + +#ifdef CONFIG_XTENSA_CALL0_ABI + xcp->regs[REG_PS] = PS_UM | PS_EXCM; + +#else + /* For windowed ABI set WOE and CALLINC (pretend task was 'call4'd). */ + + xcp->regs[REG_PS] = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1); +#endif + +#ifdef CONFIG_XTENSA_USE_SWPRI + /* Set the initial virtual priority mask value to all 1's. */ + + xcp->regs[REG_VPRI] = 0xffffffff; +#endif + +# warning Revisit co-processor support +#if 0 /* REVISIT */ +#if CONFIG_XTENSA_NCOPROCESSORS > 0 + /* Init the coprocessor save area (see xtensa_context.h) + * + * No access to TCB here, so derive indirectly. Stack growth is top to bottom. + * //ptr = (uint32_t *) xMPUSettings->coproc_area; + */ + + ptr = (uint32_t *)(((uint32_t)tcb->adj_stack_ptr - XT_CP_SIZE) & ~0xf); + ptr[0] = 0; + ptr[1] = 0; + ptr[2] = (((uint32_t)ptr) + 12 + XCHAL_TOTAL_SA_ALIGN - 1) & -XCHAL_TOTAL_SA_ALIGN; +#endif +#endif /* REVISIT */ +} diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index d6cd7667f9..06aeded18c 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -42,10 +42,10 @@ HEAD_ASRC = CMN_ASRCS = xtensa_irq.S CMN_CSRCS = xtensa_allocateheap.c xtensa_copystate.c xtensa_createstack.c CMN_CSRCS += xtensa_exit.c xtensa_idle.c xtensa_initialize.c -CMN_CSRCS += xtensa_interruptcontext.c xtensa_lowputs.c xtensa_mdelay.c -CMN_CSRCS += xtensa_modifyreg8.c xtensa_modifyreg16.c xtensa_modifyreg32.c -CMN_CSRCS += xtensa_puts.c xtensa_releasestack.c xtensa_stackframe.c -CMN_CSRCS += xtensa_udelay.c xtensa_usestack.c +CMN_CSRCS += xtensa_initialstate.c xtensa_interruptcontext.c xtensa_lowputs.c +CMN_CSRCS += xtensa_mdelay.c xtensa_modifyreg8.c xtensa_modifyreg16.c +CMN_CSRCS += xtensa_modifyreg32.c xtensa_puts.c xtensa_releasestack.c +CMN_CSRCS += xtensa_stackframe.c xtensa_udelay.c xtensa_usestack.c # Configuration-dependent common XTENSA files -- GitLab From 0591b67c15335f73f7acaf4db3b3be618a6c79d4 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 16 Oct 2016 10:27:52 -0600 Subject: [PATCH 093/734] Xtensa: A few fixes for clean compile --- arch/xtensa/src/common/xtensa_initialstate.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_initialstate.c b/arch/xtensa/src/common/xtensa_initialstate.c index fe00a95e92..0072118bbe 100644 --- a/arch/xtensa/src/common/xtensa_initialstate.c +++ b/arch/xtensa/src/common/xtensa_initialstate.c @@ -49,6 +49,11 @@ #include "xtensa.h" #include "xtensa_corebits.h" +/* Temporary for clean compile */ + +#warning REVISIT _xt_user_exit +void _xt_user_exit(void); + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -74,7 +79,6 @@ void up_initial_state(struct tcb_s *tcb) uint32_t *ptr; #endif #endif /* REVISIT */ - uint32_t regval; /* Initialize the initial exception register context structure */ @@ -106,7 +110,7 @@ void up_initial_state(struct tcb_s *tcb) xcp->regs[REG_VPRI] = 0xffffffff; #endif -# warning Revisit co-processor support +# warning REVISIT co-processor support #if 0 /* REVISIT */ #if CONFIG_XTENSA_NCOPROCESSORS > 0 /* Init the coprocessor save area (see xtensa_context.h) -- GitLab From c1334048c55e7be260ec671751ab61565374c091 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 17 Oct 2016 08:15:36 -0600 Subject: [PATCH 094/734] Xtensa: Add initial CPU0 start-up logic --- arch/xtensa/Kconfig | 1 + arch/xtensa/src/common/xtensa_attr.h | 65 + arch/xtensa/src/common/xtensa_initialstate.c | 2 +- arch/xtensa/src/esp32/chip/xtensa_dport.h | 3854 ++++++++++++++++++ arch/xtensa/src/esp32/chip/xtensa_rtccntl.h | 2009 +++++++++ arch/xtensa/src/esp32/chip/xtensa_soc.h | 356 ++ arch/xtensa/src/esp32/esp32_start.c | 128 + 7 files changed, 6414 insertions(+), 1 deletion(-) create mode 100644 arch/xtensa/src/common/xtensa_attr.h create mode 100644 arch/xtensa/src/esp32/chip/xtensa_dport.h create mode 100644 arch/xtensa/src/esp32/chip/xtensa_rtccntl.h create mode 100644 arch/xtensa/src/esp32/chip/xtensa_soc.h create mode 100644 arch/xtensa/src/esp32/esp32_start.c diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 940235cbf2..889b8d798c 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -13,6 +13,7 @@ config ARCH_CHIP_ESP32 bool "Expressif ESP32" select ARCH_FAMILY_LX6 select XTENSA_HAVE_INTERRUPTS + select ARCH_HAVE_MULTICPU ---help--- The ESP32 is a dual-core system from Expressif with two Harvard architecture Xtensa LX6 CPUs. All embedded memory, external memory diff --git a/arch/xtensa/src/common/xtensa_attr.h b/arch/xtensa/src/common/xtensa_attr.h new file mode 100644 index 0000000000..72cce41da9 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_attr.h @@ -0,0 +1,65 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_irq.S + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Espressif Systems: + * + * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_ATTR_H +#define __ARCH_XTENSA_SRC_COMMON_XTENSA_ATTR_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ROMFN_ATTR + +/* Normally, the linker script will put all code and rodata in flash, + * and all variables in shared RAM. These macros can be used to redirect + * particular functions/variables to other memory regions. + */ + +/* Forces code into IRAM instead of flash */ + +#define IRAM_ATTR __attribute__((section(".iram1"))) + +/* Forces data into DRAM instead of flash */ + +#define DRAM_ATTR __attribute__((section(".dram1"))) + +/* Forces code into RTC fast memory */ + +#define RTC_IRAM_ATTR __attribute__((section(".rtc.text"))) + +/* Forces data into RTC slow memory + * Any variable marked with this attribute will keep its value + * during a deep sleep / wake cycle. */ + +#define RTC_DATA_ATTR __attribute__((section(".rtc.data"))) + +/* Forces read-only data into RTC slow memory + * Makes constant data available to RTC wake stubs. + */ + +#define RTC_RODATA_ATTR __attribute__((section(".rtc.rodata"))) + +#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_ATTR_H */ diff --git a/arch/xtensa/src/common/xtensa_initialstate.c b/arch/xtensa/src/common/xtensa_initialstate.c index 0072118bbe..d447f49ad2 100644 --- a/arch/xtensa/src/common/xtensa_initialstate.c +++ b/arch/xtensa/src/common/xtensa_initialstate.c @@ -110,7 +110,7 @@ void up_initial_state(struct tcb_s *tcb) xcp->regs[REG_VPRI] = 0xffffffff; #endif -# warning REVISIT co-processor support +#warning REVISIT co-processor support #if 0 /* REVISIT */ #if CONFIG_XTENSA_NCOPROCESSORS > 0 /* Init the coprocessor save area (see xtensa_context.h) diff --git a/arch/xtensa/src/esp32/chip/xtensa_dport.h b/arch/xtensa/src/esp32/chip/xtensa_dport.h new file mode 100644 index 0000000000..85a145fe92 --- /dev/null +++ b/arch/xtensa/src/esp32/chip/xtensa_dport.h @@ -0,0 +1,3854 @@ +/**************************************************************************** + * arch/xtensa/src/common/exp32_dport.h + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Espressif Systems: + * + * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_XTENSA_DPORT_H +#define __ARCH_XTENSA_SRC_ESP32_CHIP_XTENSA_DPORT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "chip/esp32_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define DPORT_PRO_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x000) +/* DPORT_PRO_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_BOOT_REMAP (BIT(0)) +#define DPORT_PRO_BOOT_REMAP_M (BIT(0)) +#define DPORT_PRO_BOOT_REMAP_V 0x1 +#define DPORT_PRO_BOOT_REMAP_S 0 + +#define DPORT_APP_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x004) +/* DPORT_APP_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_BOOT_REMAP (BIT(0)) +#define DPORT_APP_BOOT_REMAP_M (BIT(0)) +#define DPORT_APP_BOOT_REMAP_V 0x1 +#define DPORT_APP_BOOT_REMAP_S 0 + +#define DPORT_ACCESS_CHECK_REG (DR_REG_DPORT_BASE + 0x008) +/* DPORT_ACCESS_CHECK_APP : RO ;bitpos:[8] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_ACCESS_CHECK_APP (BIT(8)) +#define DPORT_ACCESS_CHECK_APP_M (BIT(8)) +#define DPORT_ACCESS_CHECK_APP_V 0x1 +#define DPORT_ACCESS_CHECK_APP_S 8 +/* DPORT_ACCESS_CHECK_PRO : RO ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_ACCESS_CHECK_PRO (BIT(0)) +#define DPORT_ACCESS_CHECK_PRO_M (BIT(0)) +#define DPORT_ACCESS_CHECK_PRO_V 0x1 +#define DPORT_ACCESS_CHECK_PRO_S 0 + +#define DPORT_PRO_DPORT_APB_MASK0_REG (DR_REG_DPORT_BASE + 0x00C) +/* DPORT_PRODPORT_APB_MASK0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_PRODPORT_APB_MASK0 0xFFFFFFFF +#define DPORT_PRODPORT_APB_MASK0_M ((DPORT_PRODPORT_APB_MASK0_V)<<(DPORT_PRODPORT_APB_MASK0_S)) +#define DPORT_PRODPORT_APB_MASK0_V 0xFFFFFFFF +#define DPORT_PRODPORT_APB_MASK0_S 0 + +#define DPORT_PRO_DPORT_APB_MASK1_REG (DR_REG_DPORT_BASE + 0x010) +/* DPORT_PRODPORT_APB_MASK1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_PRODPORT_APB_MASK1 0xFFFFFFFF +#define DPORT_PRODPORT_APB_MASK1_M ((DPORT_PRODPORT_APB_MASK1_V)<<(DPORT_PRODPORT_APB_MASK1_S)) +#define DPORT_PRODPORT_APB_MASK1_V 0xFFFFFFFF +#define DPORT_PRODPORT_APB_MASK1_S 0 + +#define DPORT_APP_DPORT_APB_MASK0_REG (DR_REG_DPORT_BASE + 0x014) +/* DPORT_APPDPORT_APB_MASK0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_APPDPORT_APB_MASK0 0xFFFFFFFF +#define DPORT_APPDPORT_APB_MASK0_M ((DPORT_APPDPORT_APB_MASK0_V)<<(DPORT_APPDPORT_APB_MASK0_S)) +#define DPORT_APPDPORT_APB_MASK0_V 0xFFFFFFFF +#define DPORT_APPDPORT_APB_MASK0_S 0 + +#define DPORT_APP_DPORT_APB_MASK1_REG (DR_REG_DPORT_BASE + 0x018) +/* DPORT_APPDPORT_APB_MASK1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_APPDPORT_APB_MASK1 0xFFFFFFFF +#define DPORT_APPDPORT_APB_MASK1_M ((DPORT_APPDPORT_APB_MASK1_V)<<(DPORT_APPDPORT_APB_MASK1_S)) +#define DPORT_APPDPORT_APB_MASK1_V 0xFFFFFFFF +#define DPORT_APPDPORT_APB_MASK1_S 0 + +#define DPORT_PERI_CLK_EN_REG (DR_REG_DPORT_BASE + 0x01C) +/* DPORT_PERI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_PERI_CLK_EN 0xFFFFFFFF +#define DPORT_PERI_CLK_EN_M ((DPORT_PERI_CLK_EN_V)<<(DPORT_PERI_CLK_EN_S)) +#define DPORT_PERI_CLK_EN_V 0xFFFFFFFF +#define DPORT_PERI_CLK_EN_S 0 + +#define DPORT_PERI_RST_EN_REG (DR_REG_DPORT_BASE + 0x020) +/* DPORT_PERI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_PERI_RST_EN 0xFFFFFFFF +#define DPORT_PERI_RST_EN_M ((DPORT_PERI_RST_EN_V)<<(DPORT_PERI_RST_EN_S)) +#define DPORT_PERI_RST_EN_V 0xFFFFFFFF +#define DPORT_PERI_RST_EN_S 0 + +#define DPORT_WIFI_BB_CFG_REG (DR_REG_DPORT_BASE + 0x024) +/* DPORT_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_WIFI_BB_CFG 0xFFFFFFFF +#define DPORT_WIFI_BB_CFG_M ((DPORT_WIFI_BB_CFG_V)<<(DPORT_WIFI_BB_CFG_S)) +#define DPORT_WIFI_BB_CFG_V 0xFFFFFFFF +#define DPORT_WIFI_BB_CFG_S 0 + +#define DPORT_WIFI_BB_CFG_2_REG (DR_REG_DPORT_BASE + 0x028) +/* DPORT_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_WIFI_BB_CFG_2 0xFFFFFFFF +#define DPORT_WIFI_BB_CFG_2_M ((DPORT_WIFI_BB_CFG_2_V)<<(DPORT_WIFI_BB_CFG_2_S)) +#define DPORT_WIFI_BB_CFG_2_V 0xFFFFFFFF +#define DPORT_WIFI_BB_CFG_2_S 0 + +#define DPORT_APPCPU_CTRL_A_REG (DR_REG_DPORT_BASE + 0x02C) +/* DPORT_APPCPU_RESETTING : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APPCPU_RESETTING (BIT(0)) +#define DPORT_APPCPU_RESETTING_M (BIT(0)) +#define DPORT_APPCPU_RESETTING_V 0x1 +#define DPORT_APPCPU_RESETTING_S 0 + +#define DPORT_APPCPU_CTRL_B_REG (DR_REG_DPORT_BASE + 0x030) +/* DPORT_APPCPU_CLKGATE_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APPCPU_CLKGATE_EN (BIT(0)) +#define DPORT_APPCPU_CLKGATE_EN_M (BIT(0)) +#define DPORT_APPCPU_CLKGATE_EN_V 0x1 +#define DPORT_APPCPU_CLKGATE_EN_S 0 + +#define DPORT_APPCPU_CTRL_C_REG (DR_REG_DPORT_BASE + 0x034) +/* DPORT_APPCPU_RUNSTALL : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APPCPU_RUNSTALL (BIT(0)) +#define DPORT_APPCPU_RUNSTALL_M (BIT(0)) +#define DPORT_APPCPU_RUNSTALL_V 0x1 +#define DPORT_APPCPU_RUNSTALL_S 0 + +#define DPORT_APPCPU_CTRL_D_REG (DR_REG_DPORT_BASE + 0x038) +/* DPORT_APPCPU_BOOT_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_APPCPU_BOOT_ADDR 0xFFFFFFFF +#define DPORT_APPCPU_BOOT_ADDR_M ((DPORT_APPCPU_BOOT_ADDR_V)<<(DPORT_APPCPU_BOOT_ADDR_S)) +#define DPORT_APPCPU_BOOT_ADDR_V 0xFFFFFFFF +#define DPORT_APPCPU_BOOT_ADDR_S 0 + +#define DPORT_CPU_PER_CONF_REG (DR_REG_DPORT_BASE + 0x03C) +/* DPORT_FAST_CLK_RTC_SEL : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_FAST_CLK_RTC_SEL (BIT(3)) +#define DPORT_FAST_CLK_RTC_SEL_M (BIT(3)) +#define DPORT_FAST_CLK_RTC_SEL_V 0x1 +#define DPORT_FAST_CLK_RTC_SEL_S 3 +/* DPORT_LOWSPEED_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_LOWSPEED_CLK_SEL (BIT(2)) +#define DPORT_LOWSPEED_CLK_SEL_M (BIT(2)) +#define DPORT_LOWSPEED_CLK_SEL_V 0x1 +#define DPORT_LOWSPEED_CLK_SEL_S 2 +/* DPORT_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_CPUPERIOD_SEL 0x00000003 +#define DPORT_CPUPERIOD_SEL_M ((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S)) +#define DPORT_CPUPERIOD_SEL_V 0x3 +#define DPORT_CPUPERIOD_SEL_S 0 + +#define DPORT_PRO_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x040) +/* DPORT_PRO_DRAM_HL : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_DRAM_HL (BIT(16)) +#define DPORT_PRO_DRAM_HL_M (BIT(16)) +#define DPORT_PRO_DRAM_HL_V 0x1 +#define DPORT_PRO_DRAM_HL_S 16 +/* DPORT_SLAVE_REQ : RO ;bitpos:[15] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_SLAVE_REQ (BIT(15)) +#define DPORT_SLAVE_REQ_M (BIT(15)) +#define DPORT_SLAVE_REQ_V 0x1 +#define DPORT_SLAVE_REQ_S 15 +/* DPORT_AHB_SPI_REQ : RO ;bitpos:[14] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_AHB_SPI_REQ (BIT(14)) +#define DPORT_AHB_SPI_REQ_M (BIT(14)) +#define DPORT_AHB_SPI_REQ_V 0x1 +#define DPORT_AHB_SPI_REQ_S 14 +/* DPORT_PRO_SLAVE_REQ : RO ;bitpos:[13] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_SLAVE_REQ (BIT(13)) +#define DPORT_PRO_SLAVE_REQ_M (BIT(13)) +#define DPORT_PRO_SLAVE_REQ_V 0x1 +#define DPORT_PRO_SLAVE_REQ_S 13 +/* DPORT_PRO_AHB_SPI_REQ : RO ;bitpos:[12] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_AHB_SPI_REQ (BIT(12)) +#define DPORT_PRO_AHB_SPI_REQ_M (BIT(12)) +#define DPORT_PRO_AHB_SPI_REQ_V 0x1 +#define DPORT_PRO_AHB_SPI_REQ_S 12 +/* DPORT_PRO_DRAM_SPLIT : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_DRAM_SPLIT (BIT(11)) +#define DPORT_PRO_DRAM_SPLIT_M (BIT(11)) +#define DPORT_PRO_DRAM_SPLIT_V 0x1 +#define DPORT_PRO_DRAM_SPLIT_S 11 +/* DPORT_PRO_SINGLE_IRAM_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_SINGLE_IRAM_ENA (BIT(10)) +#define DPORT_PRO_SINGLE_IRAM_ENA_M (BIT(10)) +#define DPORT_PRO_SINGLE_IRAM_ENA_V 0x1 +#define DPORT_PRO_SINGLE_IRAM_ENA_S 10 +/* DPORT_PRO_CACHE_LOCK_3_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_3_EN (BIT(9)) +#define DPORT_PRO_CACHE_LOCK_3_EN_M (BIT(9)) +#define DPORT_PRO_CACHE_LOCK_3_EN_V 0x1 +#define DPORT_PRO_CACHE_LOCK_3_EN_S 9 +/* DPORT_PRO_CACHE_LOCK_2_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_2_EN (BIT(8)) +#define DPORT_PRO_CACHE_LOCK_2_EN_M (BIT(8)) +#define DPORT_PRO_CACHE_LOCK_2_EN_V 0x1 +#define DPORT_PRO_CACHE_LOCK_2_EN_S 8 +/* DPORT_PRO_CACHE_LOCK_1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_1_EN (BIT(7)) +#define DPORT_PRO_CACHE_LOCK_1_EN_M (BIT(7)) +#define DPORT_PRO_CACHE_LOCK_1_EN_V 0x1 +#define DPORT_PRO_CACHE_LOCK_1_EN_S 7 +/* DPORT_PRO_CACHE_LOCK_0_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_0_EN (BIT(6)) +#define DPORT_PRO_CACHE_LOCK_0_EN_M (BIT(6)) +#define DPORT_PRO_CACHE_LOCK_0_EN_V 0x1 +#define DPORT_PRO_CACHE_LOCK_0_EN_S 6 +/* DPORT_PRO_CACHE_FLUSH_DONE : RO ;bitpos:[5] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_FLUSH_DONE (BIT(5)) +#define DPORT_PRO_CACHE_FLUSH_DONE_M (BIT(5)) +#define DPORT_PRO_CACHE_FLUSH_DONE_V 0x1 +#define DPORT_PRO_CACHE_FLUSH_DONE_S 5 +/* DPORT_PRO_CACHE_FLUSH_ENA : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_FLUSH_ENA (BIT(4)) +#define DPORT_PRO_CACHE_FLUSH_ENA_M (BIT(4)) +#define DPORT_PRO_CACHE_FLUSH_ENA_V 0x1 +#define DPORT_PRO_CACHE_FLUSH_ENA_S 4 +/* DPORT_PRO_CACHE_ENABLE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_ENABLE (BIT(3)) +#define DPORT_PRO_CACHE_ENABLE_M (BIT(3)) +#define DPORT_PRO_CACHE_ENABLE_V 0x1 +#define DPORT_PRO_CACHE_ENABLE_S 3 +/* DPORT_PRO_CACHE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_MODE (BIT(2)) +#define DPORT_PRO_CACHE_MODE_M (BIT(2)) +#define DPORT_PRO_CACHE_MODE_V 0x1 +#define DPORT_PRO_CACHE_MODE_S 2 + +#define DPORT_PRO_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x044) +/* DPORT_PRO_CACHE_MMU_IA_CLR : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_MMU_IA_CLR (BIT(13)) +#define DPORT_PRO_CACHE_MMU_IA_CLR_M (BIT(13)) +#define DPORT_PRO_CACHE_MMU_IA_CLR_V 0x1 +#define DPORT_PRO_CACHE_MMU_IA_CLR_S 13 +/* DPORT_PRO_CMMU_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CMMU_PD (BIT(12)) +#define DPORT_PRO_CMMU_PD_M (BIT(12)) +#define DPORT_PRO_CMMU_PD_V 0x1 +#define DPORT_PRO_CMMU_PD_S 12 +/* DPORT_PRO_CMMU_FORCE_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PRO_CMMU_FORCE_ON (BIT(11)) +#define DPORT_PRO_CMMU_FORCE_ON_M (BIT(11)) +#define DPORT_PRO_CMMU_FORCE_ON_V 0x1 +#define DPORT_PRO_CMMU_FORCE_ON_S 11 +/* DPORT_PRO_CMMU_FLASH_PAGE_MODE : R/W ;bitpos:[10:9] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_PRO_CMMU_FLASH_PAGE_MODE 0x00000003 +#define DPORT_PRO_CMMU_FLASH_PAGE_MODE_M ((DPORT_PRO_CMMU_FLASH_PAGE_MODE_V)<<(DPORT_PRO_CMMU_FLASH_PAGE_MODE_S)) +#define DPORT_PRO_CMMU_FLASH_PAGE_MODE_V 0x3 +#define DPORT_PRO_CMMU_FLASH_PAGE_MODE_S 9 +/* DPORT_PRO_CMMU_SRAM_PAGE_MODE : R/W ;bitpos:[8:6] ;default: 3'd3 ; */ +/* Description: */ +#define DPORT_PRO_CMMU_SRAM_PAGE_MODE 0x00000007 +#define DPORT_PRO_CMMU_SRAM_PAGE_MODE_M ((DPORT_PRO_CMMU_SRAM_PAGE_MODE_V)<<(DPORT_PRO_CMMU_SRAM_PAGE_MODE_S)) +#define DPORT_PRO_CMMU_SRAM_PAGE_MODE_V 0x7 +#define DPORT_PRO_CMMU_SRAM_PAGE_MODE_S 6 +/* DPORT_PRO_CACHE_MASK_OPSDRAM : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_MASK_OPSDRAM (BIT(5)) +#define DPORT_PRO_CACHE_MASK_OPSDRAM_M (BIT(5)) +#define DPORT_PRO_CACHE_MASK_OPSDRAM_V 0x1 +#define DPORT_PRO_CACHE_MASK_OPSDRAM_S 5 +/* DPORT_PRO_CACHE_MASK_DROM0 : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_MASK_DROM0 (BIT(4)) +#define DPORT_PRO_CACHE_MASK_DROM0_M (BIT(4)) +#define DPORT_PRO_CACHE_MASK_DROM0_V 0x1 +#define DPORT_PRO_CACHE_MASK_DROM0_S 4 +/* DPORT_PRO_CACHE_MASK_DRAM1 : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_MASK_DRAM1 (BIT(3)) +#define DPORT_PRO_CACHE_MASK_DRAM1_M (BIT(3)) +#define DPORT_PRO_CACHE_MASK_DRAM1_V 0x1 +#define DPORT_PRO_CACHE_MASK_DRAM1_S 3 +/* DPORT_PRO_CACHE_MASK_IROM0 : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_MASK_IROM0 (BIT(2)) +#define DPORT_PRO_CACHE_MASK_IROM0_M (BIT(2)) +#define DPORT_PRO_CACHE_MASK_IROM0_V 0x1 +#define DPORT_PRO_CACHE_MASK_IROM0_S 2 +/* DPORT_PRO_CACHE_MASK_IRAM1 : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_MASK_IRAM1 (BIT(1)) +#define DPORT_PRO_CACHE_MASK_IRAM1_M (BIT(1)) +#define DPORT_PRO_CACHE_MASK_IRAM1_V 0x1 +#define DPORT_PRO_CACHE_MASK_IRAM1_S 1 +/* DPORT_PRO_CACHE_MASK_IRAM0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_MASK_IRAM0 (BIT(0)) +#define DPORT_PRO_CACHE_MASK_IRAM0_M (BIT(0)) +#define DPORT_PRO_CACHE_MASK_IRAM0_V 0x1 +#define DPORT_PRO_CACHE_MASK_IRAM0_S 0 + +#define DPORT_PRO_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x048) +/* DPORT_PRO_CACHE_LOCK_0_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX 0x0000000F +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S)) +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V 0xF +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S 18 +/* DPORT_PRO_CACHE_LOCK_0_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN 0x0000000F +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S)) +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V 0xF +#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S 14 +/* DPORT_PRO_CACHE_LOCK_0_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE 0x00003FFF +#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S)) +#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V 0x3FFF +#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S 0 + +#define DPORT_PRO_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x04C) +/* DPORT_PRO_CACHE_LOCK_1_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX 0x0000000F +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S)) +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V 0xF +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S 18 +/* DPORT_PRO_CACHE_LOCK_1_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN 0x0000000F +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S)) +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V 0xF +#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S 14 +/* DPORT_PRO_CACHE_LOCK_1_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE 0x00003FFF +#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S)) +#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V 0x3FFF +#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S 0 + +#define DPORT_PRO_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x050) +/* DPORT_PRO_CACHE_LOCK_2_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX 0x0000000F +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S)) +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V 0xF +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S 18 +/* DPORT_PRO_CACHE_LOCK_2_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN 0x0000000F +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S)) +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V 0xF +#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S 14 +/* DPORT_PRO_CACHE_LOCK_2_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE 0x00003FFF +#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S)) +#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V 0x3FFF +#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S 0 + +#define DPORT_PRO_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x054) +/* DPORT_PRO_CACHE_LOCK_3_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX 0x0000000F +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S)) +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V 0xF +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S 18 +/* DPORT_PRO_CACHE_LOCK_3_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN 0x0000000F +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S)) +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V 0xF +#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S 14 +/* DPORT_PRO_CACHE_LOCK_3_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE 0x00003FFF +#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S)) +#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V 0x3FFF +#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S 0 + +#define DPORT_APP_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x058) +/* DPORT_APP_DRAM_HL : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_DRAM_HL (BIT(14)) +#define DPORT_APP_DRAM_HL_M (BIT(14)) +#define DPORT_APP_DRAM_HL_V 0x1 +#define DPORT_APP_DRAM_HL_S 14 +/* DPORT_APP_SLAVE_REQ : RO ;bitpos:[13] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_SLAVE_REQ (BIT(13)) +#define DPORT_APP_SLAVE_REQ_M (BIT(13)) +#define DPORT_APP_SLAVE_REQ_V 0x1 +#define DPORT_APP_SLAVE_REQ_S 13 +/* DPORT_APP_AHB_SPI_REQ : RO ;bitpos:[12] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_AHB_SPI_REQ (BIT(12)) +#define DPORT_APP_AHB_SPI_REQ_M (BIT(12)) +#define DPORT_APP_AHB_SPI_REQ_V 0x1 +#define DPORT_APP_AHB_SPI_REQ_S 12 +/* DPORT_APP_DRAM_SPLIT : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_DRAM_SPLIT (BIT(11)) +#define DPORT_APP_DRAM_SPLIT_M (BIT(11)) +#define DPORT_APP_DRAM_SPLIT_V 0x1 +#define DPORT_APP_DRAM_SPLIT_S 11 +/* DPORT_APP_SINGLE_IRAM_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_SINGLE_IRAM_ENA (BIT(10)) +#define DPORT_APP_SINGLE_IRAM_ENA_M (BIT(10)) +#define DPORT_APP_SINGLE_IRAM_ENA_V 0x1 +#define DPORT_APP_SINGLE_IRAM_ENA_S 10 +/* DPORT_APP_CACHE_LOCK_3_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_3_EN (BIT(9)) +#define DPORT_APP_CACHE_LOCK_3_EN_M (BIT(9)) +#define DPORT_APP_CACHE_LOCK_3_EN_V 0x1 +#define DPORT_APP_CACHE_LOCK_3_EN_S 9 +/* DPORT_APP_CACHE_LOCK_2_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_2_EN (BIT(8)) +#define DPORT_APP_CACHE_LOCK_2_EN_M (BIT(8)) +#define DPORT_APP_CACHE_LOCK_2_EN_V 0x1 +#define DPORT_APP_CACHE_LOCK_2_EN_S 8 +/* DPORT_APP_CACHE_LOCK_1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_1_EN (BIT(7)) +#define DPORT_APP_CACHE_LOCK_1_EN_M (BIT(7)) +#define DPORT_APP_CACHE_LOCK_1_EN_V 0x1 +#define DPORT_APP_CACHE_LOCK_1_EN_S 7 +/* DPORT_APP_CACHE_LOCK_0_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_0_EN (BIT(6)) +#define DPORT_APP_CACHE_LOCK_0_EN_M (BIT(6)) +#define DPORT_APP_CACHE_LOCK_0_EN_V 0x1 +#define DPORT_APP_CACHE_LOCK_0_EN_S 6 +/* DPORT_APP_CACHE_FLUSH_DONE : RO ;bitpos:[5] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_FLUSH_DONE (BIT(5)) +#define DPORT_APP_CACHE_FLUSH_DONE_M (BIT(5)) +#define DPORT_APP_CACHE_FLUSH_DONE_V 0x1 +#define DPORT_APP_CACHE_FLUSH_DONE_S 5 +/* DPORT_APP_CACHE_FLUSH_ENA : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APP_CACHE_FLUSH_ENA (BIT(4)) +#define DPORT_APP_CACHE_FLUSH_ENA_M (BIT(4)) +#define DPORT_APP_CACHE_FLUSH_ENA_V 0x1 +#define DPORT_APP_CACHE_FLUSH_ENA_S 4 +/* DPORT_APP_CACHE_ENABLE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_ENABLE (BIT(3)) +#define DPORT_APP_CACHE_ENABLE_M (BIT(3)) +#define DPORT_APP_CACHE_ENABLE_V 0x1 +#define DPORT_APP_CACHE_ENABLE_S 3 +/* DPORT_APP_CACHE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_MODE (BIT(2)) +#define DPORT_APP_CACHE_MODE_M (BIT(2)) +#define DPORT_APP_CACHE_MODE_V 0x1 +#define DPORT_APP_CACHE_MODE_S 2 + +#define DPORT_APP_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x05C) +/* DPORT_APP_CACHE_MMU_IA_CLR : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_MMU_IA_CLR (BIT(13)) +#define DPORT_APP_CACHE_MMU_IA_CLR_M (BIT(13)) +#define DPORT_APP_CACHE_MMU_IA_CLR_V 0x1 +#define DPORT_APP_CACHE_MMU_IA_CLR_S 13 +/* DPORT_APP_CMMU_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CMMU_PD (BIT(12)) +#define DPORT_APP_CMMU_PD_M (BIT(12)) +#define DPORT_APP_CMMU_PD_V 0x1 +#define DPORT_APP_CMMU_PD_S 12 +/* DPORT_APP_CMMU_FORCE_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APP_CMMU_FORCE_ON (BIT(11)) +#define DPORT_APP_CMMU_FORCE_ON_M (BIT(11)) +#define DPORT_APP_CMMU_FORCE_ON_V 0x1 +#define DPORT_APP_CMMU_FORCE_ON_S 11 +/* DPORT_APP_CMMU_FLASH_PAGE_MODE : R/W ;bitpos:[10:9] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_APP_CMMU_FLASH_PAGE_MODE 0x00000003 +#define DPORT_APP_CMMU_FLASH_PAGE_MODE_M ((DPORT_APP_CMMU_FLASH_PAGE_MODE_V)<<(DPORT_APP_CMMU_FLASH_PAGE_MODE_S)) +#define DPORT_APP_CMMU_FLASH_PAGE_MODE_V 0x3 +#define DPORT_APP_CMMU_FLASH_PAGE_MODE_S 9 +/* DPORT_APP_CMMU_SRAM_PAGE_MODE : R/W ;bitpos:[8:6] ;default: 3'd3 ; */ +/* Description: */ +#define DPORT_APP_CMMU_SRAM_PAGE_MODE 0x00000007 +#define DPORT_APP_CMMU_SRAM_PAGE_MODE_M ((DPORT_APP_CMMU_SRAM_PAGE_MODE_V)<<(DPORT_APP_CMMU_SRAM_PAGE_MODE_S)) +#define DPORT_APP_CMMU_SRAM_PAGE_MODE_V 0x7 +#define DPORT_APP_CMMU_SRAM_PAGE_MODE_S 6 +/* DPORT_APP_CACHE_MASK_OPSDRAM : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APP_CACHE_MASK_OPSDRAM (BIT(5)) +#define DPORT_APP_CACHE_MASK_OPSDRAM_M (BIT(5)) +#define DPORT_APP_CACHE_MASK_OPSDRAM_V 0x1 +#define DPORT_APP_CACHE_MASK_OPSDRAM_S 5 +/* DPORT_APP_CACHE_MASK_DROM0 : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APP_CACHE_MASK_DROM0 (BIT(4)) +#define DPORT_APP_CACHE_MASK_DROM0_M (BIT(4)) +#define DPORT_APP_CACHE_MASK_DROM0_V 0x1 +#define DPORT_APP_CACHE_MASK_DROM0_S 4 +/* DPORT_APP_CACHE_MASK_DRAM1 : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APP_CACHE_MASK_DRAM1 (BIT(3)) +#define DPORT_APP_CACHE_MASK_DRAM1_M (BIT(3)) +#define DPORT_APP_CACHE_MASK_DRAM1_V 0x1 +#define DPORT_APP_CACHE_MASK_DRAM1_S 3 +/* DPORT_APP_CACHE_MASK_IROM0 : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APP_CACHE_MASK_IROM0 (BIT(2)) +#define DPORT_APP_CACHE_MASK_IROM0_M (BIT(2)) +#define DPORT_APP_CACHE_MASK_IROM0_V 0x1 +#define DPORT_APP_CACHE_MASK_IROM0_S 2 +/* DPORT_APP_CACHE_MASK_IRAM1 : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APP_CACHE_MASK_IRAM1 (BIT(1)) +#define DPORT_APP_CACHE_MASK_IRAM1_M (BIT(1)) +#define DPORT_APP_CACHE_MASK_IRAM1_V 0x1 +#define DPORT_APP_CACHE_MASK_IRAM1_S 1 +/* DPORT_APP_CACHE_MASK_IRAM0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APP_CACHE_MASK_IRAM0 (BIT(0)) +#define DPORT_APP_CACHE_MASK_IRAM0_M (BIT(0)) +#define DPORT_APP_CACHE_MASK_IRAM0_V 0x1 +#define DPORT_APP_CACHE_MASK_IRAM0_S 0 + +#define DPORT_APP_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x060) +/* DPORT_APP_CACHE_LOCK_0_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX 0x0000000F +#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S)) +#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V 0xF +#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S 18 +/* DPORT_APP_CACHE_LOCK_0_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN 0x0000000F +#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S)) +#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V 0xF +#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S 14 +/* DPORT_APP_CACHE_LOCK_0_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE 0x00003FFF +#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S)) +#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V 0x3FFF +#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S 0 + +#define DPORT_APP_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x064) +/* DPORT_APP_CACHE_LOCK_1_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX 0x0000000F +#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S)) +#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V 0xF +#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S 18 +/* DPORT_APP_CACHE_LOCK_1_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN 0x0000000F +#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S)) +#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V 0xF +#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S 14 +/* DPORT_APP_CACHE_LOCK_1_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE 0x00003FFF +#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S)) +#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V 0x3FFF +#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S 0 + +#define DPORT_APP_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x068) +/* DPORT_APP_CACHE_LOCK_2_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX 0x0000000F +#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S)) +#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V 0xF +#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S 18 +/* DPORT_APP_CACHE_LOCK_2_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN 0x0000000F +#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S)) +#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V 0xF +#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S 14 +/* DPORT_APP_CACHE_LOCK_2_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE 0x00003FFF +#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S)) +#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V 0x3FFF +#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S 0 + +#define DPORT_APP_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x06C) +/* DPORT_APP_CACHE_LOCK_3_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX 0x0000000F +#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S)) +#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V 0xF +#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S 18 +/* DPORT_APP_CACHE_LOCK_3_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN 0x0000000F +#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S)) +#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V 0xF +#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S 14 +/* DPORT_APP_CACHE_LOCK_3_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE 0x00003FFF +#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S)) +#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V 0x3FFF +#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S 0 + +#define DPORT_TRACEMEM_MUX_MODE_REG (DR_REG_DPORT_BASE + 0x070) +/* DPORT_TRACEMEM_MUX_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_TRACEMEM_MUX_MODE 0x00000003 +#define DPORT_TRACEMEM_MUX_MODE_M ((DPORT_TRACEMEM_MUX_MODE_V)<<(DPORT_TRACEMEM_MUX_MODE_S)) +#define DPORT_TRACEMEM_MUX_MODE_V 0x3 +#define DPORT_TRACEMEM_MUX_MODE_S 0 + +#define DPORT_PRO_TRACEMEM_ENA_REG (DR_REG_DPORT_BASE + 0x074) +/* DPORT_PRO_TRACEMEM_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_TRACEMEM_ENA (BIT(0)) +#define DPORT_PRO_TRACEMEM_ENA_M (BIT(0)) +#define DPORT_PRO_TRACEMEM_ENA_V 0x1 +#define DPORT_PRO_TRACEMEM_ENA_S 0 + +#define DPORT_APP_TRACEMEM_ENA_REG (DR_REG_DPORT_BASE + 0x078) +/* DPORT_APP_TRACEMEM_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_TRACEMEM_ENA (BIT(0)) +#define DPORT_APP_TRACEMEM_ENA_M (BIT(0)) +#define DPORT_APP_TRACEMEM_ENA_V 0x1 +#define DPORT_APP_TRACEMEM_ENA_S 0 + +#define DPORT_CACHE_MUX_MODE_REG (DR_REG_DPORT_BASE + 0x07C) +/* DPORT_CACHE_MUX_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_CACHE_MUX_MODE 0x00000003 +#define DPORT_CACHE_MUX_MODE_M ((DPORT_CACHE_MUX_MODE_V)<<(DPORT_CACHE_MUX_MODE_S)) +#define DPORT_CACHE_MUX_MODE_V 0x3 +#define DPORT_CACHE_MUX_MODE_S 0 + +#define DPORT_IMMU_PAGE_MODE_REG (DR_REG_DPORT_BASE + 0x080) +/* DPORT_IMMU_PAGE_MODE : R/W ;bitpos:[2:1] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_IMMU_PAGE_MODE 0x00000003 +#define DPORT_IMMU_PAGE_MODE_M ((DPORT_IMMU_PAGE_MODE_V)<<(DPORT_IMMU_PAGE_MODE_S)) +#define DPORT_IMMU_PAGE_MODE_V 0x3 +#define DPORT_IMMU_PAGE_MODE_S 1 +/* DPORT_INTERNAL_SRAM_IMMU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_INTERNAL_SRAM_IMMU_ENA (BIT(0)) +#define DPORT_INTERNAL_SRAM_IMMU_ENA_M (BIT(0)) +#define DPORT_INTERNAL_SRAM_IMMU_ENA_V 0x1 +#define DPORT_INTERNAL_SRAM_IMMU_ENA_S 0 + +#define DPORT_DMMU_PAGE_MODE_REG (DR_REG_DPORT_BASE + 0x084) +/* DPORT_DMMU_PAGE_MODE : R/W ;bitpos:[2:1] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_DMMU_PAGE_MODE 0x00000003 +#define DPORT_DMMU_PAGE_MODE_M ((DPORT_DMMU_PAGE_MODE_V)<<(DPORT_DMMU_PAGE_MODE_S)) +#define DPORT_DMMU_PAGE_MODE_V 0x3 +#define DPORT_DMMU_PAGE_MODE_S 1 +/* DPORT_INTERNAL_SRAM_DMMU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_INTERNAL_SRAM_DMMU_ENA (BIT(0)) +#define DPORT_INTERNAL_SRAM_DMMU_ENA_M (BIT(0)) +#define DPORT_INTERNAL_SRAM_DMMU_ENA_V 0x1 +#define DPORT_INTERNAL_SRAM_DMMU_ENA_S 0 + +#define DPORT_ROM_MPU_ENA_REG (DR_REG_DPORT_BASE + 0x088) +/* DPORT_APP_ROM_MPU_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_ROM_MPU_ENA (BIT(2)) +#define DPORT_APP_ROM_MPU_ENA_M (BIT(2)) +#define DPORT_APP_ROM_MPU_ENA_V 0x1 +#define DPORT_APP_ROM_MPU_ENA_S 2 +/* DPORT_PRO_ROM_MPU_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_ROM_MPU_ENA (BIT(1)) +#define DPORT_PRO_ROM_MPU_ENA_M (BIT(1)) +#define DPORT_PRO_ROM_MPU_ENA_V 0x1 +#define DPORT_PRO_ROM_MPU_ENA_S 1 +/* DPORT_SHARE_ROM_MPU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_SHARE_ROM_MPU_ENA (BIT(0)) +#define DPORT_SHARE_ROM_MPU_ENA_M (BIT(0)) +#define DPORT_SHARE_ROM_MPU_ENA_V 0x1 +#define DPORT_SHARE_ROM_MPU_ENA_S 0 + +#define DPORT_MEM_PD_MASK_REG (DR_REG_DPORT_BASE + 0x08C) +/* DPORT_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_LSLP_MEM_PD_MASK (BIT(0)) +#define DPORT_LSLP_MEM_PD_MASK_M (BIT(0)) +#define DPORT_LSLP_MEM_PD_MASK_V 0x1 +#define DPORT_LSLP_MEM_PD_MASK_S 0 + +#define DPORT_ROM_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x090) +/* DPORT_SHARE_ROM_PD : R/W ;bitpos:[7:2] ;default: 6'h0 ; */ +/* Description: */ +#define DPORT_SHARE_ROM_PD 0x0000003F +#define DPORT_SHARE_ROM_PD_M ((DPORT_SHARE_ROM_PD_V)<<(DPORT_SHARE_ROM_PD_S)) +#define DPORT_SHARE_ROM_PD_V 0x3F +#define DPORT_SHARE_ROM_PD_S 2 +/* DPORT_APP_ROM_PD : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/* Description: */ +#define DPORT_APP_ROM_PD (BIT(1)) +#define DPORT_APP_ROM_PD_M (BIT(1)) +#define DPORT_APP_ROM_PD_V 0x1 +#define DPORT_APP_ROM_PD_S 1 +/* DPORT_PRO_ROM_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/* Description: */ +#define DPORT_PRO_ROM_PD (BIT(0)) +#define DPORT_PRO_ROM_PD_M (BIT(0)) +#define DPORT_PRO_ROM_PD_V 0x1 +#define DPORT_PRO_ROM_PD_S 0 + +#define DPORT_ROM_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x094) +/* DPORT_SHARE_ROM_FO : R/W ;bitpos:[7:2] ;default: 6'h0 ; */ +/* Description: */ +#define DPORT_SHARE_ROM_FO 0x0000003F +#define DPORT_SHARE_ROM_FO_M ((DPORT_SHARE_ROM_FO_V)<<(DPORT_SHARE_ROM_FO_S)) +#define DPORT_SHARE_ROM_FO_V 0x3F +#define DPORT_SHARE_ROM_FO_S 2 +/* DPORT_APP_ROM_FO : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/* Description: */ +#define DPORT_APP_ROM_FO (BIT(1)) +#define DPORT_APP_ROM_FO_M (BIT(1)) +#define DPORT_APP_ROM_FO_V 0x1 +#define DPORT_APP_ROM_FO_S 1 +/* DPORT_PRO_ROM_FO : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/* Description: */ +#define DPORT_PRO_ROM_FO (BIT(0)) +#define DPORT_PRO_ROM_FO_M (BIT(0)) +#define DPORT_PRO_ROM_FO_V 0x1 +#define DPORT_PRO_ROM_FO_S 0 + +#define DPORT_SRAM_PD_CTRL_0_REG (DR_REG_DPORT_BASE + 0x098) +/* DPORT_SRAM_PD_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_SRAM_PD_0 0xFFFFFFFF +#define DPORT_SRAM_PD_0_M ((DPORT_SRAM_PD_0_V)<<(DPORT_SRAM_PD_0_S)) +#define DPORT_SRAM_PD_0_V 0xFFFFFFFF +#define DPORT_SRAM_PD_0_S 0 + +#define DPORT_SRAM_PD_CTRL_1_REG (DR_REG_DPORT_BASE + 0x09C) +/* DPORT_SRAM_PD_1 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/* Description: */ +#define DPORT_SRAM_PD_1 (BIT(0)) +#define DPORT_SRAM_PD_1_M (BIT(0)) +#define DPORT_SRAM_PD_1_V 0x1 +#define DPORT_SRAM_PD_1_S 0 + +#define DPORT_SRAM_FO_CTRL_0_REG (DR_REG_DPORT_BASE + 0x0A0) +/* DPORT_SRAM_FO_0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/* Description: */ +#define DPORT_SRAM_FO_0 0xFFFFFFFF +#define DPORT_SRAM_FO_0_M ((DPORT_SRAM_FO_0_V)<<(DPORT_SRAM_FO_0_S)) +#define DPORT_SRAM_FO_0_V 0xFFFFFFFF +#define DPORT_SRAM_FO_0_S 0 + +#define DPORT_SRAM_FO_CTRL_1_REG (DR_REG_DPORT_BASE + 0x0A4) +/* DPORT_SRAM_FO_1 : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/* Description: */ +#define DPORT_SRAM_FO_1 (BIT(0)) +#define DPORT_SRAM_FO_1_M (BIT(0)) +#define DPORT_SRAM_FO_1_V 0x1 +#define DPORT_SRAM_FO_1_S 0 + +#define DPORT_IRAM_DRAM_AHB_SEL_REG (DR_REG_DPORT_BASE + 0x0A8) +/* DPORT_MAC_DUMP_MODE : R/W ;bitpos:[6:5] ;default: 2'h0 ; */ +/* Description: */ +#define DPORT_MAC_DUMP_MODE 0x00000003 +#define DPORT_MAC_DUMP_MODE_M ((DPORT_MAC_DUMP_MODE_V)<<(DPORT_MAC_DUMP_MODE_S)) +#define DPORT_MAC_DUMP_MODE_V 0x3 +#define DPORT_MAC_DUMP_MODE_S 5 +/* DPORT_MASK_AHB : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_MASK_AHB (BIT(4)) +#define DPORT_MASK_AHB_M (BIT(4)) +#define DPORT_MASK_AHB_V 0x1 +#define DPORT_MASK_AHB_S 4 +/* DPORT_MASK_APP_DRAM : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_MASK_APP_DRAM (BIT(3)) +#define DPORT_MASK_APP_DRAM_M (BIT(3)) +#define DPORT_MASK_APP_DRAM_V 0x1 +#define DPORT_MASK_APP_DRAM_S 3 +/* DPORT_MASK_PRO_DRAM : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_MASK_PRO_DRAM (BIT(2)) +#define DPORT_MASK_PRO_DRAM_M (BIT(2)) +#define DPORT_MASK_PRO_DRAM_V 0x1 +#define DPORT_MASK_PRO_DRAM_S 2 +/* DPORT_MASK_APP_IRAM : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_MASK_APP_IRAM (BIT(1)) +#define DPORT_MASK_APP_IRAM_M (BIT(1)) +#define DPORT_MASK_APP_IRAM_V 0x1 +#define DPORT_MASK_APP_IRAM_S 1 +/* DPORT_MASK_PRO_IRAM : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_MASK_PRO_IRAM (BIT(0)) +#define DPORT_MASK_PRO_IRAM_M (BIT(0)) +#define DPORT_MASK_PRO_IRAM_V 0x1 +#define DPORT_MASK_PRO_IRAM_S 0 + +#define DPORT_TAG_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x0AC) +/* DPORT_APP_CACHE_TAG_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_TAG_PD (BIT(9)) +#define DPORT_APP_CACHE_TAG_PD_M (BIT(9)) +#define DPORT_APP_CACHE_TAG_PD_V 0x1 +#define DPORT_APP_CACHE_TAG_PD_S 9 +/* DPORT_APP_CACHE_TAG_FORCE_ON : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APP_CACHE_TAG_FORCE_ON (BIT(8)) +#define DPORT_APP_CACHE_TAG_FORCE_ON_M (BIT(8)) +#define DPORT_APP_CACHE_TAG_FORCE_ON_V 0x1 +#define DPORT_APP_CACHE_TAG_FORCE_ON_S 8 +/* DPORT_PRO_CACHE_TAG_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_TAG_PD (BIT(1)) +#define DPORT_PRO_CACHE_TAG_PD_M (BIT(1)) +#define DPORT_PRO_CACHE_TAG_PD_V 0x1 +#define DPORT_PRO_CACHE_TAG_PD_S 1 +/* DPORT_PRO_CACHE_TAG_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_TAG_FORCE_ON (BIT(0)) +#define DPORT_PRO_CACHE_TAG_FORCE_ON_M (BIT(0)) +#define DPORT_PRO_CACHE_TAG_FORCE_ON_V 0x1 +#define DPORT_PRO_CACHE_TAG_FORCE_ON_S 0 + +#define DPORT_AHB_LITE_MASK_REG (DR_REG_DPORT_BASE + 0x0B0) +/* DPORT_AHB_LITE_SDHOST_PID_REG : R/W ;bitpos:[13:11] ;default: 3'b0 ; */ +/* Description: */ +#define DPORT_AHB_LITE_SDHOST_PID_REG 0x00000007 +#define DPORT_AHB_LITE_SDHOST_PID_REG_M ((DPORT_AHB_LITE_SDHOST_PID_REG_V)<<(DPORT_AHB_LITE_SDHOST_PID_REG_S)) +#define DPORT_AHB_LITE_SDHOST_PID_REG_V 0x7 +#define DPORT_AHB_LITE_SDHOST_PID_REG_S 11 +/* DPORT_AHB_LITE_MASK_APPDPORT : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_AHB_LITE_MASK_APPDPORT (BIT(10)) +#define DPORT_AHB_LITE_MASK_APPDPORT_M (BIT(10)) +#define DPORT_AHB_LITE_MASK_APPDPORT_V 0x1 +#define DPORT_AHB_LITE_MASK_APPDPORT_S 10 +/* DPORT_AHB_LITE_MASK_PRODPORT : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_AHB_LITE_MASK_PRODPORT (BIT(9)) +#define DPORT_AHB_LITE_MASK_PRODPORT_M (BIT(9)) +#define DPORT_AHB_LITE_MASK_PRODPORT_V 0x1 +#define DPORT_AHB_LITE_MASK_PRODPORT_S 9 +/* DPORT_AHB_LITE_MASK_SDIO : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_AHB_LITE_MASK_SDIO (BIT(8)) +#define DPORT_AHB_LITE_MASK_SDIO_M (BIT(8)) +#define DPORT_AHB_LITE_MASK_SDIO_V 0x1 +#define DPORT_AHB_LITE_MASK_SDIO_S 8 +/* DPORT_AHB_LITE_MASK_APP : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_AHB_LITE_MASK_APP (BIT(4)) +#define DPORT_AHB_LITE_MASK_APP_M (BIT(4)) +#define DPORT_AHB_LITE_MASK_APP_V 0x1 +#define DPORT_AHB_LITE_MASK_APP_S 4 +/* DPORT_AHB_LITE_MASK_PRO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_AHB_LITE_MASK_PRO (BIT(0)) +#define DPORT_AHB_LITE_MASK_PRO_M (BIT(0)) +#define DPORT_AHB_LITE_MASK_PRO_V 0x1 +#define DPORT_AHB_LITE_MASK_PRO_S 0 + +#define DPORT_AHB_MPU_TABLE_0_REG (DR_REG_DPORT_BASE + 0x0B4) +/* DPORT_AHB_ACCESS_GRANT_0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/* Description: */ +#define DPORT_AHB_ACCESS_GRANT_0 0xFFFFFFFF +#define DPORT_AHB_ACCESS_GRANT_0_M ((DPORT_AHB_ACCESS_GRANT_0_V)<<(DPORT_AHB_ACCESS_GRANT_0_S)) +#define DPORT_AHB_ACCESS_GRANT_0_V 0xFFFFFFFF +#define DPORT_AHB_ACCESS_GRANT_0_S 0 + +#define DPORT_AHB_MPU_TABLE_1_REG (DR_REG_DPORT_BASE + 0x0B8) +/* DPORT_AHB_ACCESS_GRANT_1 : R/W ;bitpos:[8:0] ;default: 9'h1ff ; */ +/* Description: */ +#define DPORT_AHB_ACCESS_GRANT_1 0x000001FF +#define DPORT_AHB_ACCESS_GRANT_1_M ((DPORT_AHB_ACCESS_GRANT_1_V)<<(DPORT_AHB_ACCESS_GRANT_1_S)) +#define DPORT_AHB_ACCESS_GRANT_1_V 0x1FF +#define DPORT_AHB_ACCESS_GRANT_1_S 0 + +#define DPORT_HOST_INF_SEL_REG (DR_REG_DPORT_BASE + 0x0BC) +/* DPORT_LINK_DEVICE_SEL : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/* Description: */ +#define DPORT_LINK_DEVICE_SEL 0x000000FF +#define DPORT_LINK_DEVICE_SEL_M ((DPORT_LINK_DEVICE_SEL_V)<<(DPORT_LINK_DEVICE_SEL_S)) +#define DPORT_LINK_DEVICE_SEL_V 0xFF +#define DPORT_LINK_DEVICE_SEL_S 8 +/* DPORT_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/* Description: */ +#define DPORT_PERI_IO_SWAP 0x000000FF +#define DPORT_PERI_IO_SWAP_M ((DPORT_PERI_IO_SWAP_V)<<(DPORT_PERI_IO_SWAP_S)) +#define DPORT_PERI_IO_SWAP_V 0xFF +#define DPORT_PERI_IO_SWAP_S 0 + +#define DPORT_PERIP_CLK_EN_REG (DR_REG_DPORT_BASE + 0x0C0) +/* DPORT_PERIP_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hf9c1e06f ; */ +/* Description: */ +#define DPORT_PERIP_CLK_EN 0xFFFFFFFF +#define DPORT_PERIP_CLK_EN_M ((DPORT_PERIP_CLK_EN_V)<<(DPORT_PERIP_CLK_EN_S)) +#define DPORT_PERIP_CLK_EN_V 0xFFFFFFFF +#define DPORT_PERIP_CLK_EN_S 0 + +#define DPORT_PWM3_CLK_EN (BIT(26)) +#define DPORT_PWM2_CLK_EN (BIT(25)) +#define DPORT_UART_MEM_CLK_EN (BIT(24)) +#define DPORT_UART2_CLK_EN (BIT(23)) +#define DPORT_SPI_DMA_CLK_EN (BIT(22)) +#define DPORT_I2S1_CLK_EN (BIT(21)) +#define DPORT_PWM1_CLK_EN (BIT(20)) +#define DPORT_CAN_CLK_EN (BIT(19)) +#define DPORT_I2C_EXT1_CLK_EN (BIT(18)) +#define DPORT_PWM0_CLK_EN (BIT(17)) +#define DPORT_SPI_CLK_EN (BIT(16)) +#define DPORT_TIMERGROUP1_CLK_EN (BIT(15)) +#define DPORT_EFUSE_CLK_EN (BIT(14)) +#define DPORT_TIMERGROUP_CLK_EN (BIT(13)) +#define DPORT_UHCI1_CLK_EN (BIT(12)) +#define DPORT_LEDC_CLK_EN (BIT(11)) +#define DPORT_PCNT_CLK_EN (BIT(10)) +#define DPORT_RMT_CLK_EN (BIT(9)) +#define DPORT_UHCI0_CLK_EN (BIT(8)) +#define DPORT_I2C_EXT0_CLK_EN (BIT(7)) +#define DPORT_SPI_CLK_EN_2 (BIT(6)) +#define DPORT_UART1_CLK_EN (BIT(5)) +#define DPORT_I2S0_CLK_EN (BIT(4)) +#define DPORT_WDG_CLK_EN (BIT(3)) +#define DPORT_UART_CLK_EN (BIT(2)) +#define DPORT_SPI_CLK_EN_1 (BIT(1)) +#define DPORT_TIMERS_CLK_EN (BIT(0)) +#define DPORT_PERIP_RST_EN_REG (DR_REG_DPORT_BASE + 0x0C4) +/* DPORT_PERIP_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_PERIP_RST 0xFFFFFFFF +#define DPORT_PERIP_RST_M ((DPORT_PERIP_RST_V)<<(DPORT_PERIP_RST_S)) +#define DPORT_PERIP_RST_V 0xFFFFFFFF +#define DPORT_PERIP_RST_S 0 +#define DPORT_PWM3_RST (BIT(26)) +#define DPORT_PWM2_RST (BIT(25)) +#define DPORT_UART_MEM_RST (BIT(24)) +#define DPORT_UART2_RST (BIT(23)) +#define DPORT_SPI_DMA_RST (BIT(22)) +#define DPORT_I2S1_RST (BIT(21)) +#define DPORT_PWM1_RST (BIT(20)) +#define DPORT_CAN_RST (BIT(19)) +#define DPORT_I2C_EXT1_RST (BIT(18)) +#define DPORT_PWM0_RST (BIT(17)) +#define DPORT_SPI_RST (BIT(16)) +#define DPORT_TIMERGROUP1_RST (BIT(15)) +#define DPORT_EFUSE_RST (BIT(14)) +#define DPORT_TIMERGROUP_RST (BIT(13)) +#define DPORT_UHCI1_RST (BIT(12)) +#define DPORT_LEDC_RST (BIT(11)) +#define DPORT_PCNT_RST (BIT(10)) +#define DPORT_RMT_RST (BIT(9)) +#define DPORT_UHCI0_RST (BIT(8)) +#define DPORT_I2C_EXT0_RST (BIT(7)) +#define DPORT_SPI_RST_2 (BIT(6)) +#define DPORT_UART1_RST (BIT(5)) +#define DPORT_I2S0_RST (BIT(4)) +#define DPORT_WDG_RST (BIT(3)) +#define DPORT_UART_RST (BIT(2)) +#define DPORT_SPI_RST_1 (BIT(1)) +#define DPORT_TIMERS_RST (BIT(0)) +#define DPORT_SLAVE_SPI_CONFIG_REG (DR_REG_DPORT_BASE + 0x0C8) +/* DPORT_SPI_DECRYPT_ENABLE : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_SPI_DECRYPT_ENABLE (BIT(12)) +#define DPORT_SPI_DECRYPT_ENABLE_M (BIT(12)) +#define DPORT_SPI_DECRYPT_ENABLE_V 0x1 +#define DPORT_SPI_DECRYPT_ENABLE_S 12 +/* DPORT_SPI_ENCRYPT_ENABLE : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_SPI_ENCRYPT_ENABLE (BIT(8)) +#define DPORT_SPI_ENCRYPT_ENABLE_M (BIT(8)) +#define DPORT_SPI_ENCRYPT_ENABLE_V 0x1 +#define DPORT_SPI_ENCRYPT_ENABLE_S 8 +/* DPORT_SLAVE_SPI_MASK_APP : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_SLAVE_SPI_MASK_APP (BIT(4)) +#define DPORT_SLAVE_SPI_MASK_APP_M (BIT(4)) +#define DPORT_SLAVE_SPI_MASK_APP_V 0x1 +#define DPORT_SLAVE_SPI_MASK_APP_S 4 +/* DPORT_SLAVE_SPI_MASK_PRO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_SLAVE_SPI_MASK_PRO (BIT(0)) +#define DPORT_SLAVE_SPI_MASK_PRO_M (BIT(0)) +#define DPORT_SLAVE_SPI_MASK_PRO_V 0x1 +#define DPORT_SLAVE_SPI_MASK_PRO_S 0 + +#define DPORT_WIFI_CLK_EN_REG (DR_REG_DPORT_BASE + 0x0CC) +/* DPORT_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ +/* Description: */ +#define DPORT_WIFI_CLK_EN 0xFFFFFFFF +#define DPORT_WIFI_CLK_EN_M ((DPORT_WIFI_CLK_EN_V)<<(DPORT_WIFI_CLK_EN_S)) +#define DPORT_WIFI_CLK_EN_V 0xFFFFFFFF +#define DPORT_WIFI_CLK_EN_S 0 + +#define DPORT_WIFI_RST_EN_REG (DR_REG_DPORT_BASE + 0x0D0) +/* DPORT_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_WIFI_RST 0xFFFFFFFF +#define DPORT_WIFI_RST_M ((DPORT_WIFI_RST_V)<<(DPORT_WIFI_RST_S)) +#define DPORT_WIFI_RST_V 0xFFFFFFFF +#define DPORT_WIFI_RST_S 0 + +#define DPORT_BT_LPCK_DIV_INT_REG (DR_REG_DPORT_BASE + 0x0D4) +/* DPORT_BTEXTWAKEUP_REQ : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_BTEXTWAKEUP_REQ (BIT(12)) +#define DPORT_BTEXTWAKEUP_REQ_M (BIT(12)) +#define DPORT_BTEXTWAKEUP_REQ_V 0x1 +#define DPORT_BTEXTWAKEUP_REQ_S 12 +/* DPORT_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */ +/* Description: */ +#define DPORT_BT_LPCK_DIV_NUM 0x00000FFF +#define DPORT_BT_LPCK_DIV_NUM_M ((DPORT_BT_LPCK_DIV_NUM_V)<<(DPORT_BT_LPCK_DIV_NUM_S)) +#define DPORT_BT_LPCK_DIV_NUM_V 0xFFF +#define DPORT_BT_LPCK_DIV_NUM_S 0 + +#define DPORT_BT_LPCK_DIV_FRAC_REG (DR_REG_DPORT_BASE + 0x0D8) +/* DPORT_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_LPCLK_SEL_XTAL32K (BIT(27)) +#define DPORT_LPCLK_SEL_XTAL32K_M (BIT(27)) +#define DPORT_LPCLK_SEL_XTAL32K_V 0x1 +#define DPORT_LPCLK_SEL_XTAL32K_S 27 +/* DPORT_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_LPCLK_SEL_XTAL (BIT(26)) +#define DPORT_LPCLK_SEL_XTAL_M (BIT(26)) +#define DPORT_LPCLK_SEL_XTAL_V 0x1 +#define DPORT_LPCLK_SEL_XTAL_S 26 +/* DPORT_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_LPCLK_SEL_8M (BIT(25)) +#define DPORT_LPCLK_SEL_8M_M (BIT(25)) +#define DPORT_LPCLK_SEL_8M_V 0x1 +#define DPORT_LPCLK_SEL_8M_S 25 +/* DPORT_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_LPCLK_SEL_RTC_SLOW (BIT(24)) +#define DPORT_LPCLK_SEL_RTC_SLOW_M (BIT(24)) +#define DPORT_LPCLK_SEL_RTC_SLOW_V 0x1 +#define DPORT_LPCLK_SEL_RTC_SLOW_S 24 +/* DPORT_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */ +/* Description: */ +#define DPORT_BT_LPCK_DIV_A 0x00000FFF +#define DPORT_BT_LPCK_DIV_A_M ((DPORT_BT_LPCK_DIV_A_V)<<(DPORT_BT_LPCK_DIV_A_S)) +#define DPORT_BT_LPCK_DIV_A_V 0xFFF +#define DPORT_BT_LPCK_DIV_A_S 12 +/* DPORT_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */ +/* Description: */ +#define DPORT_BT_LPCK_DIV_B 0x00000FFF +#define DPORT_BT_LPCK_DIV_B_M ((DPORT_BT_LPCK_DIV_B_V)<<(DPORT_BT_LPCK_DIV_B_S)) +#define DPORT_BT_LPCK_DIV_B_V 0xFFF +#define DPORT_BT_LPCK_DIV_B_S 0 + +#define DPORT_CPU_INTR_FROM_CPU_0_REG (DR_REG_DPORT_BASE + 0x0DC) +/* DPORT_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_CPU_INTR_FROM_CPU_0 (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_0_M (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_0_V 0x1 +#define DPORT_CPU_INTR_FROM_CPU_0_S 0 + +#define DPORT_CPU_INTR_FROM_CPU_1_REG (DR_REG_DPORT_BASE + 0x0E0) +/* DPORT_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_CPU_INTR_FROM_CPU_1 (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_1_M (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_1_V 0x1 +#define DPORT_CPU_INTR_FROM_CPU_1_S 0 + +#define DPORT_CPU_INTR_FROM_CPU_2_REG (DR_REG_DPORT_BASE + 0x0E4) +/* DPORT_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_CPU_INTR_FROM_CPU_2 (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_2_M (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_2_V 0x1 +#define DPORT_CPU_INTR_FROM_CPU_2_S 0 + +#define DPORT_CPU_INTR_FROM_CPU_3_REG (DR_REG_DPORT_BASE + 0x0E8) +/* DPORT_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_CPU_INTR_FROM_CPU_3 (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_3_M (BIT(0)) +#define DPORT_CPU_INTR_FROM_CPU_3_V 0x1 +#define DPORT_CPU_INTR_FROM_CPU_3_S 0 + +#define DPORT_PRO_INTR_STATUS_0_REG (DR_REG_DPORT_BASE + 0x0EC) +/* DPORT_PRO_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_PRO_INTR_STATUS_0 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_0_M ((DPORT_PRO_INTR_STATUS_0_V)<<(DPORT_PRO_INTR_STATUS_0_S)) +#define DPORT_PRO_INTR_STATUS_0_V 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_0_S 0 + +#define DPORT_PRO_INTR_STATUS_1_REG (DR_REG_DPORT_BASE + 0x0F0) +/* DPORT_PRO_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_PRO_INTR_STATUS_1 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_1_M ((DPORT_PRO_INTR_STATUS_1_V)<<(DPORT_PRO_INTR_STATUS_1_S)) +#define DPORT_PRO_INTR_STATUS_1_V 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_1_S 0 + +#define DPORT_PRO_INTR_STATUS_2_REG (DR_REG_DPORT_BASE + 0x0F4) +/* DPORT_PRO_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_PRO_INTR_STATUS_2 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_2_M ((DPORT_PRO_INTR_STATUS_2_V)<<(DPORT_PRO_INTR_STATUS_2_S)) +#define DPORT_PRO_INTR_STATUS_2_V 0xFFFFFFFF +#define DPORT_PRO_INTR_STATUS_2_S 0 + +#define DPORT_APP_INTR_STATUS_0_REG (DR_REG_DPORT_BASE + 0x0F8) +/* DPORT_APP_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_APP_INTR_STATUS_0 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_0_M ((DPORT_APP_INTR_STATUS_0_V)<<(DPORT_APP_INTR_STATUS_0_S)) +#define DPORT_APP_INTR_STATUS_0_V 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_0_S 0 + +#define DPORT_APP_INTR_STATUS_1_REG (DR_REG_DPORT_BASE + 0x0FC) +/* DPORT_APP_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_APP_INTR_STATUS_1 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_1_M ((DPORT_APP_INTR_STATUS_1_V)<<(DPORT_APP_INTR_STATUS_1_S)) +#define DPORT_APP_INTR_STATUS_1_V 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_1_S 0 + +#define DPORT_APP_INTR_STATUS_2_REG (DR_REG_DPORT_BASE + 0x100) +/* DPORT_APP_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/* Description: */ +#define DPORT_APP_INTR_STATUS_2 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_2_M ((DPORT_APP_INTR_STATUS_2_V)<<(DPORT_APP_INTR_STATUS_2_S)) +#define DPORT_APP_INTR_STATUS_2_V 0xFFFFFFFF +#define DPORT_APP_INTR_STATUS_2_S 0 + +#define DPORT_PRO_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x104) +/* DPORT_PRO_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_MAC_INTR_MAP 0x0000001F +#define DPORT_PRO_MAC_INTR_MAP_M ((DPORT_PRO_MAC_INTR_MAP_V)<<(DPORT_PRO_MAC_INTR_MAP_S)) +#define DPORT_PRO_MAC_INTR_MAP_V 0x1F +#define DPORT_PRO_MAC_INTR_MAP_S 0 + +#define DPORT_PRO_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x108) +/* DPORT_PRO_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_MAC_NMI_MAP 0x0000001F +#define DPORT_PRO_MAC_NMI_MAP_M ((DPORT_PRO_MAC_NMI_MAP_V)<<(DPORT_PRO_MAC_NMI_MAP_S)) +#define DPORT_PRO_MAC_NMI_MAP_V 0x1F +#define DPORT_PRO_MAC_NMI_MAP_S 0 + +#define DPORT_PRO_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x10C) +/* DPORT_PRO_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_BB_INT_MAP 0x0000001F +#define DPORT_PRO_BB_INT_MAP_M ((DPORT_PRO_BB_INT_MAP_V)<<(DPORT_PRO_BB_INT_MAP_S)) +#define DPORT_PRO_BB_INT_MAP_V 0x1F +#define DPORT_PRO_BB_INT_MAP_S 0 + +#define DPORT_PRO_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x110) +/* DPORT_PRO_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_BT_MAC_INT_MAP 0x0000001F +#define DPORT_PRO_BT_MAC_INT_MAP_M ((DPORT_PRO_BT_MAC_INT_MAP_V)<<(DPORT_PRO_BT_MAC_INT_MAP_S)) +#define DPORT_PRO_BT_MAC_INT_MAP_V 0x1F +#define DPORT_PRO_BT_MAC_INT_MAP_S 0 + +#define DPORT_PRO_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x114) +/* DPORT_PRO_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_BT_BB_INT_MAP 0x0000001F +#define DPORT_PRO_BT_BB_INT_MAP_M ((DPORT_PRO_BT_BB_INT_MAP_V)<<(DPORT_PRO_BT_BB_INT_MAP_S)) +#define DPORT_PRO_BT_BB_INT_MAP_V 0x1F +#define DPORT_PRO_BT_BB_INT_MAP_S 0 + +#define DPORT_PRO_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x118) +/* DPORT_PRO_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_BT_BB_NMI_MAP 0x0000001F +#define DPORT_PRO_BT_BB_NMI_MAP_M ((DPORT_PRO_BT_BB_NMI_MAP_V)<<(DPORT_PRO_BT_BB_NMI_MAP_S)) +#define DPORT_PRO_BT_BB_NMI_MAP_V 0x1F +#define DPORT_PRO_BT_BB_NMI_MAP_S 0 + +#define DPORT_PRO_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x11C) +/* DPORT_PRO_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_RWBT_IRQ_MAP 0x0000001F +#define DPORT_PRO_RWBT_IRQ_MAP_M ((DPORT_PRO_RWBT_IRQ_MAP_V)<<(DPORT_PRO_RWBT_IRQ_MAP_S)) +#define DPORT_PRO_RWBT_IRQ_MAP_V 0x1F +#define DPORT_PRO_RWBT_IRQ_MAP_S 0 + +#define DPORT_PRO_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x120) +/* DPORT_PRO_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_RWBLE_IRQ_MAP 0x0000001F +#define DPORT_PRO_RWBLE_IRQ_MAP_M ((DPORT_PRO_RWBLE_IRQ_MAP_V)<<(DPORT_PRO_RWBLE_IRQ_MAP_S)) +#define DPORT_PRO_RWBLE_IRQ_MAP_V 0x1F +#define DPORT_PRO_RWBLE_IRQ_MAP_S 0 + +#define DPORT_PRO_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x124) +/* DPORT_PRO_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_RWBT_NMI_MAP 0x0000001F +#define DPORT_PRO_RWBT_NMI_MAP_M ((DPORT_PRO_RWBT_NMI_MAP_V)<<(DPORT_PRO_RWBT_NMI_MAP_S)) +#define DPORT_PRO_RWBT_NMI_MAP_V 0x1F +#define DPORT_PRO_RWBT_NMI_MAP_S 0 + +#define DPORT_PRO_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x128) +/* DPORT_PRO_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_RWBLE_NMI_MAP 0x0000001F +#define DPORT_PRO_RWBLE_NMI_MAP_M ((DPORT_PRO_RWBLE_NMI_MAP_V)<<(DPORT_PRO_RWBLE_NMI_MAP_S)) +#define DPORT_PRO_RWBLE_NMI_MAP_V 0x1F +#define DPORT_PRO_RWBLE_NMI_MAP_S 0 + +#define DPORT_PRO_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x12C) +/* DPORT_PRO_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_SLC0_INTR_MAP 0x0000001F +#define DPORT_PRO_SLC0_INTR_MAP_M ((DPORT_PRO_SLC0_INTR_MAP_V)<<(DPORT_PRO_SLC0_INTR_MAP_S)) +#define DPORT_PRO_SLC0_INTR_MAP_V 0x1F +#define DPORT_PRO_SLC0_INTR_MAP_S 0 + +#define DPORT_PRO_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x130) +/* DPORT_PRO_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_SLC1_INTR_MAP 0x0000001F +#define DPORT_PRO_SLC1_INTR_MAP_M ((DPORT_PRO_SLC1_INTR_MAP_V)<<(DPORT_PRO_SLC1_INTR_MAP_S)) +#define DPORT_PRO_SLC1_INTR_MAP_V 0x1F +#define DPORT_PRO_SLC1_INTR_MAP_S 0 + +#define DPORT_PRO_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x134) +/* DPORT_PRO_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_UHCI0_INTR_MAP 0x0000001F +#define DPORT_PRO_UHCI0_INTR_MAP_M ((DPORT_PRO_UHCI0_INTR_MAP_V)<<(DPORT_PRO_UHCI0_INTR_MAP_S)) +#define DPORT_PRO_UHCI0_INTR_MAP_V 0x1F +#define DPORT_PRO_UHCI0_INTR_MAP_S 0 + +#define DPORT_PRO_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x138) +/* DPORT_PRO_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_UHCI1_INTR_MAP 0x0000001F +#define DPORT_PRO_UHCI1_INTR_MAP_M ((DPORT_PRO_UHCI1_INTR_MAP_V)<<(DPORT_PRO_UHCI1_INTR_MAP_S)) +#define DPORT_PRO_UHCI1_INTR_MAP_V 0x1F +#define DPORT_PRO_UHCI1_INTR_MAP_S 0 + +#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x13C) +/* DPORT_PRO_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG_T0_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_M ((DPORT_PRO_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T0_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x140) +/* DPORT_PRO_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG_T1_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_M ((DPORT_PRO_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T1_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x144) +/* DPORT_PRO_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_M ((DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x148) +/* DPORT_PRO_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_M ((DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x14C) +/* DPORT_PRO_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x150) +/* DPORT_PRO_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x154) +/* DPORT_PRO_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x158) +/* DPORT_PRO_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S)) +#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S 0 + +#define DPORT_PRO_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x15C) +/* DPORT_PRO_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP 0x0000001F +#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_M ((DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V)<<(DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S)) +#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V 0x1F +#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S 0 + +#define DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x160) +/* DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F +#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_M ((DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S)) +#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F +#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 + +#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x164) +/* DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP 0x0000001F +#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S)) +#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V 0x1F +#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S 0 + +#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x168) +/* DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP 0x0000001F +#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S)) +#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V 0x1F +#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S 0 + +#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x16C) +/* DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP 0x0000001F +#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S)) +#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V 0x1F +#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S 0 + +#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x170) +/* DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP 0x0000001F +#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S)) +#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V 0x1F +#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S 0 + +#define DPORT_PRO_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x174) +/* DPORT_PRO_SPI_INTR_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_SPI_INTR_0_MAP 0x0000001F +#define DPORT_PRO_SPI_INTR_0_MAP_M ((DPORT_PRO_SPI_INTR_0_MAP_V)<<(DPORT_PRO_SPI_INTR_0_MAP_S)) +#define DPORT_PRO_SPI_INTR_0_MAP_V 0x1F +#define DPORT_PRO_SPI_INTR_0_MAP_S 0 + +#define DPORT_PRO_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x178) +/* DPORT_PRO_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_SPI_INTR_1_MAP 0x0000001F +#define DPORT_PRO_SPI_INTR_1_MAP_M ((DPORT_PRO_SPI_INTR_1_MAP_V)<<(DPORT_PRO_SPI_INTR_1_MAP_S)) +#define DPORT_PRO_SPI_INTR_1_MAP_V 0x1F +#define DPORT_PRO_SPI_INTR_1_MAP_S 0 + +#define DPORT_PRO_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x17C) +/* DPORT_PRO_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_SPI_INTR_2_MAP 0x0000001F +#define DPORT_PRO_SPI_INTR_2_MAP_M ((DPORT_PRO_SPI_INTR_2_MAP_V)<<(DPORT_PRO_SPI_INTR_2_MAP_S)) +#define DPORT_PRO_SPI_INTR_2_MAP_V 0x1F +#define DPORT_PRO_SPI_INTR_2_MAP_S 0 + +#define DPORT_PRO_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x180) +/* DPORT_PRO_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_SPI_INTR_3_MAP 0x0000001F +#define DPORT_PRO_SPI_INTR_3_MAP_M ((DPORT_PRO_SPI_INTR_3_MAP_V)<<(DPORT_PRO_SPI_INTR_3_MAP_S)) +#define DPORT_PRO_SPI_INTR_3_MAP_V 0x1F +#define DPORT_PRO_SPI_INTR_3_MAP_S 0 + +#define DPORT_PRO_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x184) +/* DPORT_PRO_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_I2S0_INT_MAP 0x0000001F +#define DPORT_PRO_I2S0_INT_MAP_M ((DPORT_PRO_I2S0_INT_MAP_V)<<(DPORT_PRO_I2S0_INT_MAP_S)) +#define DPORT_PRO_I2S0_INT_MAP_V 0x1F +#define DPORT_PRO_I2S0_INT_MAP_S 0 + +#define DPORT_PRO_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x188) +/* DPORT_PRO_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_I2S1_INT_MAP 0x0000001F +#define DPORT_PRO_I2S1_INT_MAP_M ((DPORT_PRO_I2S1_INT_MAP_V)<<(DPORT_PRO_I2S1_INT_MAP_S)) +#define DPORT_PRO_I2S1_INT_MAP_V 0x1F +#define DPORT_PRO_I2S1_INT_MAP_S 0 + +#define DPORT_PRO_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x18C) +/* DPORT_PRO_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_UART_INTR_MAP 0x0000001F +#define DPORT_PRO_UART_INTR_MAP_M ((DPORT_PRO_UART_INTR_MAP_V)<<(DPORT_PRO_UART_INTR_MAP_S)) +#define DPORT_PRO_UART_INTR_MAP_V 0x1F +#define DPORT_PRO_UART_INTR_MAP_S 0 + +#define DPORT_PRO_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x190) +/* DPORT_PRO_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_UART1_INTR_MAP 0x0000001F +#define DPORT_PRO_UART1_INTR_MAP_M ((DPORT_PRO_UART1_INTR_MAP_V)<<(DPORT_PRO_UART1_INTR_MAP_S)) +#define DPORT_PRO_UART1_INTR_MAP_V 0x1F +#define DPORT_PRO_UART1_INTR_MAP_S 0 + +#define DPORT_PRO_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x194) +/* DPORT_PRO_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_UART2_INTR_MAP 0x0000001F +#define DPORT_PRO_UART2_INTR_MAP_M ((DPORT_PRO_UART2_INTR_MAP_V)<<(DPORT_PRO_UART2_INTR_MAP_S)) +#define DPORT_PRO_UART2_INTR_MAP_V 0x1F +#define DPORT_PRO_UART2_INTR_MAP_S 0 + +#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x198) +/* DPORT_PRO_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP 0x0000001F +#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_M ((DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V)<<(DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S)) +#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V 0x1F +#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S 0 + +#define DPORT_PRO_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x19C) +/* DPORT_PRO_EMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_EMAC_INT_MAP 0x0000001F +#define DPORT_PRO_EMAC_INT_MAP_M ((DPORT_PRO_EMAC_INT_MAP_V)<<(DPORT_PRO_EMAC_INT_MAP_S)) +#define DPORT_PRO_EMAC_INT_MAP_V 0x1F +#define DPORT_PRO_EMAC_INT_MAP_S 0 + +#define DPORT_PRO_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A0) +/* DPORT_PRO_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_PWM0_INTR_MAP 0x0000001F +#define DPORT_PRO_PWM0_INTR_MAP_M ((DPORT_PRO_PWM0_INTR_MAP_V)<<(DPORT_PRO_PWM0_INTR_MAP_S)) +#define DPORT_PRO_PWM0_INTR_MAP_V 0x1F +#define DPORT_PRO_PWM0_INTR_MAP_S 0 + +#define DPORT_PRO_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A4) +/* DPORT_PRO_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_PWM1_INTR_MAP 0x0000001F +#define DPORT_PRO_PWM1_INTR_MAP_M ((DPORT_PRO_PWM1_INTR_MAP_V)<<(DPORT_PRO_PWM1_INTR_MAP_S)) +#define DPORT_PRO_PWM1_INTR_MAP_V 0x1F +#define DPORT_PRO_PWM1_INTR_MAP_S 0 + +#define DPORT_PRO_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A8) +/* DPORT_PRO_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_PWM2_INTR_MAP 0x0000001F +#define DPORT_PRO_PWM2_INTR_MAP_M ((DPORT_PRO_PWM2_INTR_MAP_V)<<(DPORT_PRO_PWM2_INTR_MAP_S)) +#define DPORT_PRO_PWM2_INTR_MAP_V 0x1F +#define DPORT_PRO_PWM2_INTR_MAP_S 0 + +#define DPORT_PRO_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1AC) +/* DPORT_PRO_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_PWM3_INTR_MAP 0x0000001F +#define DPORT_PRO_PWM3_INTR_MAP_M ((DPORT_PRO_PWM3_INTR_MAP_V)<<(DPORT_PRO_PWM3_INTR_MAP_S)) +#define DPORT_PRO_PWM3_INTR_MAP_V 0x1F +#define DPORT_PRO_PWM3_INTR_MAP_S 0 + +#define DPORT_PRO_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B0) +/* DPORT_PRO_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_LEDC_INT_MAP 0x0000001F +#define DPORT_PRO_LEDC_INT_MAP_M ((DPORT_PRO_LEDC_INT_MAP_V)<<(DPORT_PRO_LEDC_INT_MAP_S)) +#define DPORT_PRO_LEDC_INT_MAP_V 0x1F +#define DPORT_PRO_LEDC_INT_MAP_S 0 + +#define DPORT_PRO_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B4) +/* DPORT_PRO_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_EFUSE_INT_MAP 0x0000001F +#define DPORT_PRO_EFUSE_INT_MAP_M ((DPORT_PRO_EFUSE_INT_MAP_V)<<(DPORT_PRO_EFUSE_INT_MAP_S)) +#define DPORT_PRO_EFUSE_INT_MAP_V 0x1F +#define DPORT_PRO_EFUSE_INT_MAP_S 0 + +#define DPORT_PRO_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B8) +/* DPORT_PRO_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_CAN_INT_MAP 0x0000001F +#define DPORT_PRO_CAN_INT_MAP_M ((DPORT_PRO_CAN_INT_MAP_V)<<(DPORT_PRO_CAN_INT_MAP_S)) +#define DPORT_PRO_CAN_INT_MAP_V 0x1F +#define DPORT_PRO_CAN_INT_MAP_S 0 + +#define DPORT_PRO_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1BC) +/* DPORT_PRO_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_RTC_CORE_INTR_MAP 0x0000001F +#define DPORT_PRO_RTC_CORE_INTR_MAP_M ((DPORT_PRO_RTC_CORE_INTR_MAP_V)<<(DPORT_PRO_RTC_CORE_INTR_MAP_S)) +#define DPORT_PRO_RTC_CORE_INTR_MAP_V 0x1F +#define DPORT_PRO_RTC_CORE_INTR_MAP_S 0 + +#define DPORT_PRO_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C0) +/* DPORT_PRO_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_RMT_INTR_MAP 0x0000001F +#define DPORT_PRO_RMT_INTR_MAP_M ((DPORT_PRO_RMT_INTR_MAP_V)<<(DPORT_PRO_RMT_INTR_MAP_S)) +#define DPORT_PRO_RMT_INTR_MAP_V 0x1F +#define DPORT_PRO_RMT_INTR_MAP_S 0 + +#define DPORT_PRO_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C4) +/* DPORT_PRO_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_PCNT_INTR_MAP 0x0000001F +#define DPORT_PRO_PCNT_INTR_MAP_M ((DPORT_PRO_PCNT_INTR_MAP_V)<<(DPORT_PRO_PCNT_INTR_MAP_S)) +#define DPORT_PRO_PCNT_INTR_MAP_V 0x1F +#define DPORT_PRO_PCNT_INTR_MAP_S 0 + +#define DPORT_PRO_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C8) +/* DPORT_PRO_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_I2C_EXT0_INTR_MAP 0x0000001F +#define DPORT_PRO_I2C_EXT0_INTR_MAP_M ((DPORT_PRO_I2C_EXT0_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT0_INTR_MAP_S)) +#define DPORT_PRO_I2C_EXT0_INTR_MAP_V 0x1F +#define DPORT_PRO_I2C_EXT0_INTR_MAP_S 0 + +#define DPORT_PRO_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1CC) +/* DPORT_PRO_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_I2C_EXT1_INTR_MAP 0x0000001F +#define DPORT_PRO_I2C_EXT1_INTR_MAP_M ((DPORT_PRO_I2C_EXT1_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT1_INTR_MAP_S)) +#define DPORT_PRO_I2C_EXT1_INTR_MAP_V 0x1F +#define DPORT_PRO_I2C_EXT1_INTR_MAP_S 0 + +#define DPORT_PRO_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1D0) +/* DPORT_PRO_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_RSA_INTR_MAP 0x0000001F +#define DPORT_PRO_RSA_INTR_MAP_M ((DPORT_PRO_RSA_INTR_MAP_V)<<(DPORT_PRO_RSA_INTR_MAP_S)) +#define DPORT_PRO_RSA_INTR_MAP_V 0x1F +#define DPORT_PRO_RSA_INTR_MAP_S 0 + +#define DPORT_PRO_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D4) +/* DPORT_PRO_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_SPI1_DMA_INT_MAP 0x0000001F +#define DPORT_PRO_SPI1_DMA_INT_MAP_M ((DPORT_PRO_SPI1_DMA_INT_MAP_V)<<(DPORT_PRO_SPI1_DMA_INT_MAP_S)) +#define DPORT_PRO_SPI1_DMA_INT_MAP_V 0x1F +#define DPORT_PRO_SPI1_DMA_INT_MAP_S 0 + +#define DPORT_PRO_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D8) +/* DPORT_PRO_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_SPI2_DMA_INT_MAP 0x0000001F +#define DPORT_PRO_SPI2_DMA_INT_MAP_M ((DPORT_PRO_SPI2_DMA_INT_MAP_V)<<(DPORT_PRO_SPI2_DMA_INT_MAP_S)) +#define DPORT_PRO_SPI2_DMA_INT_MAP_V 0x1F +#define DPORT_PRO_SPI2_DMA_INT_MAP_S 0 + +#define DPORT_PRO_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1DC) +/* DPORT_PRO_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_SPI3_DMA_INT_MAP 0x0000001F +#define DPORT_PRO_SPI3_DMA_INT_MAP_M ((DPORT_PRO_SPI3_DMA_INT_MAP_V)<<(DPORT_PRO_SPI3_DMA_INT_MAP_S)) +#define DPORT_PRO_SPI3_DMA_INT_MAP_V 0x1F +#define DPORT_PRO_SPI3_DMA_INT_MAP_S 0 + +#define DPORT_PRO_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1E0) +/* DPORT_PRO_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_WDG_INT_MAP 0x0000001F +#define DPORT_PRO_WDG_INT_MAP_M ((DPORT_PRO_WDG_INT_MAP_V)<<(DPORT_PRO_WDG_INT_MAP_S)) +#define DPORT_PRO_WDG_INT_MAP_V 0x1F +#define DPORT_PRO_WDG_INT_MAP_S 0 + +#define DPORT_PRO_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x1E4) +/* DPORT_PRO_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TIMER_INT1_MAP 0x0000001F +#define DPORT_PRO_TIMER_INT1_MAP_M ((DPORT_PRO_TIMER_INT1_MAP_V)<<(DPORT_PRO_TIMER_INT1_MAP_S)) +#define DPORT_PRO_TIMER_INT1_MAP_V 0x1F +#define DPORT_PRO_TIMER_INT1_MAP_S 0 + +#define DPORT_PRO_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x1E8) +/* DPORT_PRO_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TIMER_INT2_MAP 0x0000001F +#define DPORT_PRO_TIMER_INT2_MAP_M ((DPORT_PRO_TIMER_INT2_MAP_V)<<(DPORT_PRO_TIMER_INT2_MAP_S)) +#define DPORT_PRO_TIMER_INT2_MAP_V 0x1F +#define DPORT_PRO_TIMER_INT2_MAP_S 0 + +#define DPORT_PRO_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1EC) +/* DPORT_PRO_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG_T0_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG_T0_EDGE_INT_MAP_M ((DPORT_PRO_TG_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T0_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG_T0_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG_T0_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F0) +/* DPORT_PRO_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG_T1_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG_T1_EDGE_INT_MAP_M ((DPORT_PRO_TG_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T1_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG_T1_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG_T1_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F4) +/* DPORT_PRO_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG_WDT_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_M ((DPORT_PRO_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_WDT_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F8) +/* DPORT_PRO_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG_LACT_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_M ((DPORT_PRO_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_LACT_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1FC) +/* DPORT_PRO_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG1_T0_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_M ((DPORT_PRO_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T0_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x200) +/* DPORT_PRO_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG1_T1_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_M ((DPORT_PRO_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T1_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x204) +/* DPORT_PRO_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_M ((DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x208) +/* DPORT_PRO_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP 0x0000001F +#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_M ((DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S)) +#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V 0x1F +#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S 0 + +#define DPORT_PRO_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x20C) +/* DPORT_PRO_MMU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_MMU_IA_INT_MAP 0x0000001F +#define DPORT_PRO_MMU_IA_INT_MAP_M ((DPORT_PRO_MMU_IA_INT_MAP_V)<<(DPORT_PRO_MMU_IA_INT_MAP_S)) +#define DPORT_PRO_MMU_IA_INT_MAP_V 0x1F +#define DPORT_PRO_MMU_IA_INT_MAP_S 0 + +#define DPORT_PRO_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x210) +/* DPORT_PRO_MPU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_MPU_IA_INT_MAP 0x0000001F +#define DPORT_PRO_MPU_IA_INT_MAP_M ((DPORT_PRO_MPU_IA_INT_MAP_V)<<(DPORT_PRO_MPU_IA_INT_MAP_S)) +#define DPORT_PRO_MPU_IA_INT_MAP_V 0x1F +#define DPORT_PRO_MPU_IA_INT_MAP_S 0 + +#define DPORT_PRO_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x214) +/* DPORT_PRO_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_IA_INT_MAP 0x0000001F +#define DPORT_PRO_CACHE_IA_INT_MAP_M ((DPORT_PRO_CACHE_IA_INT_MAP_V)<<(DPORT_PRO_CACHE_IA_INT_MAP_S)) +#define DPORT_PRO_CACHE_IA_INT_MAP_V 0x1F +#define DPORT_PRO_CACHE_IA_INT_MAP_S 0 + +#define DPORT_APP_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x218) +/* DPORT_APP_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_MAC_INTR_MAP 0x0000001F +#define DPORT_APP_MAC_INTR_MAP_M ((DPORT_APP_MAC_INTR_MAP_V)<<(DPORT_APP_MAC_INTR_MAP_S)) +#define DPORT_APP_MAC_INTR_MAP_V 0x1F +#define DPORT_APP_MAC_INTR_MAP_S 0 + +#define DPORT_APP_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x21C) +/* DPORT_APP_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_MAC_NMI_MAP 0x0000001F +#define DPORT_APP_MAC_NMI_MAP_M ((DPORT_APP_MAC_NMI_MAP_V)<<(DPORT_APP_MAC_NMI_MAP_S)) +#define DPORT_APP_MAC_NMI_MAP_V 0x1F +#define DPORT_APP_MAC_NMI_MAP_S 0 + +#define DPORT_APP_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x220) +/* DPORT_APP_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_BB_INT_MAP 0x0000001F +#define DPORT_APP_BB_INT_MAP_M ((DPORT_APP_BB_INT_MAP_V)<<(DPORT_APP_BB_INT_MAP_S)) +#define DPORT_APP_BB_INT_MAP_V 0x1F +#define DPORT_APP_BB_INT_MAP_S 0 + +#define DPORT_APP_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x224) +/* DPORT_APP_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_BT_MAC_INT_MAP 0x0000001F +#define DPORT_APP_BT_MAC_INT_MAP_M ((DPORT_APP_BT_MAC_INT_MAP_V)<<(DPORT_APP_BT_MAC_INT_MAP_S)) +#define DPORT_APP_BT_MAC_INT_MAP_V 0x1F +#define DPORT_APP_BT_MAC_INT_MAP_S 0 + +#define DPORT_APP_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x228) +/* DPORT_APP_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_BT_BB_INT_MAP 0x0000001F +#define DPORT_APP_BT_BB_INT_MAP_M ((DPORT_APP_BT_BB_INT_MAP_V)<<(DPORT_APP_BT_BB_INT_MAP_S)) +#define DPORT_APP_BT_BB_INT_MAP_V 0x1F +#define DPORT_APP_BT_BB_INT_MAP_S 0 + +#define DPORT_APP_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x22C) +/* DPORT_APP_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_BT_BB_NMI_MAP 0x0000001F +#define DPORT_APP_BT_BB_NMI_MAP_M ((DPORT_APP_BT_BB_NMI_MAP_V)<<(DPORT_APP_BT_BB_NMI_MAP_S)) +#define DPORT_APP_BT_BB_NMI_MAP_V 0x1F +#define DPORT_APP_BT_BB_NMI_MAP_S 0 + +#define DPORT_APP_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x230) +/* DPORT_APP_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_RWBT_IRQ_MAP 0x0000001F +#define DPORT_APP_RWBT_IRQ_MAP_M ((DPORT_APP_RWBT_IRQ_MAP_V)<<(DPORT_APP_RWBT_IRQ_MAP_S)) +#define DPORT_APP_RWBT_IRQ_MAP_V 0x1F +#define DPORT_APP_RWBT_IRQ_MAP_S 0 + +#define DPORT_APP_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x234) +/* DPORT_APP_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_RWBLE_IRQ_MAP 0x0000001F +#define DPORT_APP_RWBLE_IRQ_MAP_M ((DPORT_APP_RWBLE_IRQ_MAP_V)<<(DPORT_APP_RWBLE_IRQ_MAP_S)) +#define DPORT_APP_RWBLE_IRQ_MAP_V 0x1F +#define DPORT_APP_RWBLE_IRQ_MAP_S 0 + +#define DPORT_APP_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x238) +/* DPORT_APP_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_RWBT_NMI_MAP 0x0000001F +#define DPORT_APP_RWBT_NMI_MAP_M ((DPORT_APP_RWBT_NMI_MAP_V)<<(DPORT_APP_RWBT_NMI_MAP_S)) +#define DPORT_APP_RWBT_NMI_MAP_V 0x1F +#define DPORT_APP_RWBT_NMI_MAP_S 0 + +#define DPORT_APP_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x23C) +/* DPORT_APP_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_RWBLE_NMI_MAP 0x0000001F +#define DPORT_APP_RWBLE_NMI_MAP_M ((DPORT_APP_RWBLE_NMI_MAP_V)<<(DPORT_APP_RWBLE_NMI_MAP_S)) +#define DPORT_APP_RWBLE_NMI_MAP_V 0x1F +#define DPORT_APP_RWBLE_NMI_MAP_S 0 + +#define DPORT_APP_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x240) +/* DPORT_APP_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_SLC0_INTR_MAP 0x0000001F +#define DPORT_APP_SLC0_INTR_MAP_M ((DPORT_APP_SLC0_INTR_MAP_V)<<(DPORT_APP_SLC0_INTR_MAP_S)) +#define DPORT_APP_SLC0_INTR_MAP_V 0x1F +#define DPORT_APP_SLC0_INTR_MAP_S 0 + +#define DPORT_APP_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x244) +/* DPORT_APP_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_SLC1_INTR_MAP 0x0000001F +#define DPORT_APP_SLC1_INTR_MAP_M ((DPORT_APP_SLC1_INTR_MAP_V)<<(DPORT_APP_SLC1_INTR_MAP_S)) +#define DPORT_APP_SLC1_INTR_MAP_V 0x1F +#define DPORT_APP_SLC1_INTR_MAP_S 0 + +#define DPORT_APP_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x248) +/* DPORT_APP_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_UHCI0_INTR_MAP 0x0000001F +#define DPORT_APP_UHCI0_INTR_MAP_M ((DPORT_APP_UHCI0_INTR_MAP_V)<<(DPORT_APP_UHCI0_INTR_MAP_S)) +#define DPORT_APP_UHCI0_INTR_MAP_V 0x1F +#define DPORT_APP_UHCI0_INTR_MAP_S 0 + +#define DPORT_APP_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x24C) +/* DPORT_APP_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_UHCI1_INTR_MAP 0x0000001F +#define DPORT_APP_UHCI1_INTR_MAP_M ((DPORT_APP_UHCI1_INTR_MAP_V)<<(DPORT_APP_UHCI1_INTR_MAP_S)) +#define DPORT_APP_UHCI1_INTR_MAP_V 0x1F +#define DPORT_APP_UHCI1_INTR_MAP_S 0 + +#define DPORT_APP_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x250) +/* DPORT_APP_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG_T0_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG_T0_LEVEL_INT_MAP_M ((DPORT_APP_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_T0_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG_T0_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG_T0_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x254) +/* DPORT_APP_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG_T1_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG_T1_LEVEL_INT_MAP_M ((DPORT_APP_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_T1_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG_T1_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG_T1_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x258) +/* DPORT_APP_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG_WDT_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_M ((DPORT_APP_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_WDT_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x25C) +/* DPORT_APP_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG_LACT_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_M ((DPORT_APP_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_LACT_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x260) +/* DPORT_APP_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG1_T0_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_M ((DPORT_APP_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_T0_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x264) +/* DPORT_APP_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG1_T1_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_M ((DPORT_APP_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_T1_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x268) +/* DPORT_APP_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_M ((DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x26C) +/* DPORT_APP_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP 0x0000001F +#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_M ((DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S)) +#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V 0x1F +#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S 0 + +#define DPORT_APP_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x270) +/* DPORT_APP_GPIO_INTERRUPT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_GPIO_INTERRUPT_APP_MAP 0x0000001F +#define DPORT_APP_GPIO_INTERRUPT_APP_MAP_M ((DPORT_APP_GPIO_INTERRUPT_APP_MAP_V)<<(DPORT_APP_GPIO_INTERRUPT_APP_MAP_S)) +#define DPORT_APP_GPIO_INTERRUPT_APP_MAP_V 0x1F +#define DPORT_APP_GPIO_INTERRUPT_APP_MAP_S 0 + +#define DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x274) +/* DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F +#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_M ((DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V)<<(DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S)) +#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V 0x1F +#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S 0 + +#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x278) +/* DPORT_APP_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP 0x0000001F +#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S)) +#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V 0x1F +#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S 0 + +#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x27C) +/* DPORT_APP_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP 0x0000001F +#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S)) +#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V 0x1F +#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S 0 + +#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x280) +/* DPORT_APP_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP 0x0000001F +#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S)) +#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V 0x1F +#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S 0 + +#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x284) +/* DPORT_APP_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP 0x0000001F +#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S)) +#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V 0x1F +#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S 0 + +#define DPORT_APP_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x288) +/* DPORT_APP_SPI_INTR_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_SPI_INTR_0_MAP 0x0000001F +#define DPORT_APP_SPI_INTR_0_MAP_M ((DPORT_APP_SPI_INTR_0_MAP_V)<<(DPORT_APP_SPI_INTR_0_MAP_S)) +#define DPORT_APP_SPI_INTR_0_MAP_V 0x1F +#define DPORT_APP_SPI_INTR_0_MAP_S 0 + +#define DPORT_APP_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x28C) +/* DPORT_APP_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_SPI_INTR_1_MAP 0x0000001F +#define DPORT_APP_SPI_INTR_1_MAP_M ((DPORT_APP_SPI_INTR_1_MAP_V)<<(DPORT_APP_SPI_INTR_1_MAP_S)) +#define DPORT_APP_SPI_INTR_1_MAP_V 0x1F +#define DPORT_APP_SPI_INTR_1_MAP_S 0 + +#define DPORT_APP_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x290) +/* DPORT_APP_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_SPI_INTR_2_MAP 0x0000001F +#define DPORT_APP_SPI_INTR_2_MAP_M ((DPORT_APP_SPI_INTR_2_MAP_V)<<(DPORT_APP_SPI_INTR_2_MAP_S)) +#define DPORT_APP_SPI_INTR_2_MAP_V 0x1F +#define DPORT_APP_SPI_INTR_2_MAP_S 0 + +#define DPORT_APP_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x294) +/* DPORT_APP_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_SPI_INTR_3_MAP 0x0000001F +#define DPORT_APP_SPI_INTR_3_MAP_M ((DPORT_APP_SPI_INTR_3_MAP_V)<<(DPORT_APP_SPI_INTR_3_MAP_S)) +#define DPORT_APP_SPI_INTR_3_MAP_V 0x1F +#define DPORT_APP_SPI_INTR_3_MAP_S 0 + +#define DPORT_APP_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x298) +/* DPORT_APP_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_I2S0_INT_MAP 0x0000001F +#define DPORT_APP_I2S0_INT_MAP_M ((DPORT_APP_I2S0_INT_MAP_V)<<(DPORT_APP_I2S0_INT_MAP_S)) +#define DPORT_APP_I2S0_INT_MAP_V 0x1F +#define DPORT_APP_I2S0_INT_MAP_S 0 + +#define DPORT_APP_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x29C) +/* DPORT_APP_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_I2S1_INT_MAP 0x0000001F +#define DPORT_APP_I2S1_INT_MAP_M ((DPORT_APP_I2S1_INT_MAP_V)<<(DPORT_APP_I2S1_INT_MAP_S)) +#define DPORT_APP_I2S1_INT_MAP_V 0x1F +#define DPORT_APP_I2S1_INT_MAP_S 0 + +#define DPORT_APP_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A0) +/* DPORT_APP_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_UART_INTR_MAP 0x0000001F +#define DPORT_APP_UART_INTR_MAP_M ((DPORT_APP_UART_INTR_MAP_V)<<(DPORT_APP_UART_INTR_MAP_S)) +#define DPORT_APP_UART_INTR_MAP_V 0x1F +#define DPORT_APP_UART_INTR_MAP_S 0 + +#define DPORT_APP_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A4) +/* DPORT_APP_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_UART1_INTR_MAP 0x0000001F +#define DPORT_APP_UART1_INTR_MAP_M ((DPORT_APP_UART1_INTR_MAP_V)<<(DPORT_APP_UART1_INTR_MAP_S)) +#define DPORT_APP_UART1_INTR_MAP_V 0x1F +#define DPORT_APP_UART1_INTR_MAP_S 0 + +#define DPORT_APP_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A8) +/* DPORT_APP_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_UART2_INTR_MAP 0x0000001F +#define DPORT_APP_UART2_INTR_MAP_M ((DPORT_APP_UART2_INTR_MAP_V)<<(DPORT_APP_UART2_INTR_MAP_S)) +#define DPORT_APP_UART2_INTR_MAP_V 0x1F +#define DPORT_APP_UART2_INTR_MAP_S 0 + +#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x2AC) +/* DPORT_APP_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP 0x0000001F +#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_M ((DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V)<<(DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S)) +#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V 0x1F +#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S 0 + +#define DPORT_APP_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2B0) +/* DPORT_APP_EMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_EMAC_INT_MAP 0x0000001F +#define DPORT_APP_EMAC_INT_MAP_M ((DPORT_APP_EMAC_INT_MAP_V)<<(DPORT_APP_EMAC_INT_MAP_S)) +#define DPORT_APP_EMAC_INT_MAP_V 0x1F +#define DPORT_APP_EMAC_INT_MAP_S 0 + +#define DPORT_APP_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B4) +/* DPORT_APP_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_PWM0_INTR_MAP 0x0000001F +#define DPORT_APP_PWM0_INTR_MAP_M ((DPORT_APP_PWM0_INTR_MAP_V)<<(DPORT_APP_PWM0_INTR_MAP_S)) +#define DPORT_APP_PWM0_INTR_MAP_V 0x1F +#define DPORT_APP_PWM0_INTR_MAP_S 0 + +#define DPORT_APP_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B8) +/* DPORT_APP_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_PWM1_INTR_MAP 0x0000001F +#define DPORT_APP_PWM1_INTR_MAP_M ((DPORT_APP_PWM1_INTR_MAP_V)<<(DPORT_APP_PWM1_INTR_MAP_S)) +#define DPORT_APP_PWM1_INTR_MAP_V 0x1F +#define DPORT_APP_PWM1_INTR_MAP_S 0 + +#define DPORT_APP_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2BC) +/* DPORT_APP_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_PWM2_INTR_MAP 0x0000001F +#define DPORT_APP_PWM2_INTR_MAP_M ((DPORT_APP_PWM2_INTR_MAP_V)<<(DPORT_APP_PWM2_INTR_MAP_S)) +#define DPORT_APP_PWM2_INTR_MAP_V 0x1F +#define DPORT_APP_PWM2_INTR_MAP_S 0 + +#define DPORT_APP_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2C0) +/* DPORT_APP_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_PWM3_INTR_MAP 0x0000001F +#define DPORT_APP_PWM3_INTR_MAP_M ((DPORT_APP_PWM3_INTR_MAP_V)<<(DPORT_APP_PWM3_INTR_MAP_S)) +#define DPORT_APP_PWM3_INTR_MAP_V 0x1F +#define DPORT_APP_PWM3_INTR_MAP_S 0 + +#define DPORT_APP_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C4) +/* DPORT_APP_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_LEDC_INT_MAP 0x0000001F +#define DPORT_APP_LEDC_INT_MAP_M ((DPORT_APP_LEDC_INT_MAP_V)<<(DPORT_APP_LEDC_INT_MAP_S)) +#define DPORT_APP_LEDC_INT_MAP_V 0x1F +#define DPORT_APP_LEDC_INT_MAP_S 0 + +#define DPORT_APP_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C8) +/* DPORT_APP_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_EFUSE_INT_MAP 0x0000001F +#define DPORT_APP_EFUSE_INT_MAP_M ((DPORT_APP_EFUSE_INT_MAP_V)<<(DPORT_APP_EFUSE_INT_MAP_S)) +#define DPORT_APP_EFUSE_INT_MAP_V 0x1F +#define DPORT_APP_EFUSE_INT_MAP_S 0 + +#define DPORT_APP_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2CC) +/* DPORT_APP_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_CAN_INT_MAP 0x0000001F +#define DPORT_APP_CAN_INT_MAP_M ((DPORT_APP_CAN_INT_MAP_V)<<(DPORT_APP_CAN_INT_MAP_S)) +#define DPORT_APP_CAN_INT_MAP_V 0x1F +#define DPORT_APP_CAN_INT_MAP_S 0 + +#define DPORT_APP_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D0) +/* DPORT_APP_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_RTC_CORE_INTR_MAP 0x0000001F +#define DPORT_APP_RTC_CORE_INTR_MAP_M ((DPORT_APP_RTC_CORE_INTR_MAP_V)<<(DPORT_APP_RTC_CORE_INTR_MAP_S)) +#define DPORT_APP_RTC_CORE_INTR_MAP_V 0x1F +#define DPORT_APP_RTC_CORE_INTR_MAP_S 0 + +#define DPORT_APP_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D4) +/* DPORT_APP_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_RMT_INTR_MAP 0x0000001F +#define DPORT_APP_RMT_INTR_MAP_M ((DPORT_APP_RMT_INTR_MAP_V)<<(DPORT_APP_RMT_INTR_MAP_S)) +#define DPORT_APP_RMT_INTR_MAP_V 0x1F +#define DPORT_APP_RMT_INTR_MAP_S 0 + +#define DPORT_APP_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D8) +/* DPORT_APP_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_PCNT_INTR_MAP 0x0000001F +#define DPORT_APP_PCNT_INTR_MAP_M ((DPORT_APP_PCNT_INTR_MAP_V)<<(DPORT_APP_PCNT_INTR_MAP_S)) +#define DPORT_APP_PCNT_INTR_MAP_V 0x1F +#define DPORT_APP_PCNT_INTR_MAP_S 0 + +#define DPORT_APP_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2DC) +/* DPORT_APP_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_I2C_EXT0_INTR_MAP 0x0000001F +#define DPORT_APP_I2C_EXT0_INTR_MAP_M ((DPORT_APP_I2C_EXT0_INTR_MAP_V)<<(DPORT_APP_I2C_EXT0_INTR_MAP_S)) +#define DPORT_APP_I2C_EXT0_INTR_MAP_V 0x1F +#define DPORT_APP_I2C_EXT0_INTR_MAP_S 0 + +#define DPORT_APP_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E0) +/* DPORT_APP_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_I2C_EXT1_INTR_MAP 0x0000001F +#define DPORT_APP_I2C_EXT1_INTR_MAP_M ((DPORT_APP_I2C_EXT1_INTR_MAP_V)<<(DPORT_APP_I2C_EXT1_INTR_MAP_S)) +#define DPORT_APP_I2C_EXT1_INTR_MAP_V 0x1F +#define DPORT_APP_I2C_EXT1_INTR_MAP_S 0 + +#define DPORT_APP_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E4) +/* DPORT_APP_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_RSA_INTR_MAP 0x0000001F +#define DPORT_APP_RSA_INTR_MAP_M ((DPORT_APP_RSA_INTR_MAP_V)<<(DPORT_APP_RSA_INTR_MAP_S)) +#define DPORT_APP_RSA_INTR_MAP_V 0x1F +#define DPORT_APP_RSA_INTR_MAP_S 0 + +#define DPORT_APP_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2E8) +/* DPORT_APP_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_SPI1_DMA_INT_MAP 0x0000001F +#define DPORT_APP_SPI1_DMA_INT_MAP_M ((DPORT_APP_SPI1_DMA_INT_MAP_V)<<(DPORT_APP_SPI1_DMA_INT_MAP_S)) +#define DPORT_APP_SPI1_DMA_INT_MAP_V 0x1F +#define DPORT_APP_SPI1_DMA_INT_MAP_S 0 + +#define DPORT_APP_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2EC) +/* DPORT_APP_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_SPI2_DMA_INT_MAP 0x0000001F +#define DPORT_APP_SPI2_DMA_INT_MAP_M ((DPORT_APP_SPI2_DMA_INT_MAP_V)<<(DPORT_APP_SPI2_DMA_INT_MAP_S)) +#define DPORT_APP_SPI2_DMA_INT_MAP_V 0x1F +#define DPORT_APP_SPI2_DMA_INT_MAP_S 0 + +#define DPORT_APP_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F0) +/* DPORT_APP_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_SPI3_DMA_INT_MAP 0x0000001F +#define DPORT_APP_SPI3_DMA_INT_MAP_M ((DPORT_APP_SPI3_DMA_INT_MAP_V)<<(DPORT_APP_SPI3_DMA_INT_MAP_S)) +#define DPORT_APP_SPI3_DMA_INT_MAP_V 0x1F +#define DPORT_APP_SPI3_DMA_INT_MAP_S 0 + +#define DPORT_APP_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F4) +/* DPORT_APP_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_WDG_INT_MAP 0x0000001F +#define DPORT_APP_WDG_INT_MAP_M ((DPORT_APP_WDG_INT_MAP_V)<<(DPORT_APP_WDG_INT_MAP_S)) +#define DPORT_APP_WDG_INT_MAP_V 0x1F +#define DPORT_APP_WDG_INT_MAP_S 0 + +#define DPORT_APP_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x2F8) +/* DPORT_APP_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TIMER_INT1_MAP 0x0000001F +#define DPORT_APP_TIMER_INT1_MAP_M ((DPORT_APP_TIMER_INT1_MAP_V)<<(DPORT_APP_TIMER_INT1_MAP_S)) +#define DPORT_APP_TIMER_INT1_MAP_V 0x1F +#define DPORT_APP_TIMER_INT1_MAP_S 0 + +#define DPORT_APP_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x2FC) +/* DPORT_APP_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TIMER_INT2_MAP 0x0000001F +#define DPORT_APP_TIMER_INT2_MAP_M ((DPORT_APP_TIMER_INT2_MAP_V)<<(DPORT_APP_TIMER_INT2_MAP_S)) +#define DPORT_APP_TIMER_INT2_MAP_V 0x1F +#define DPORT_APP_TIMER_INT2_MAP_S 0 + +#define DPORT_APP_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x300) +/* DPORT_APP_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG_T0_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG_T0_EDGE_INT_MAP_M ((DPORT_APP_TG_T0_EDGE_INT_MAP_V)<<(DPORT_APP_TG_T0_EDGE_INT_MAP_S)) +#define DPORT_APP_TG_T0_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG_T0_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x304) +/* DPORT_APP_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG_T1_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG_T1_EDGE_INT_MAP_M ((DPORT_APP_TG_T1_EDGE_INT_MAP_V)<<(DPORT_APP_TG_T1_EDGE_INT_MAP_S)) +#define DPORT_APP_TG_T1_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG_T1_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x308) +/* DPORT_APP_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG_WDT_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG_WDT_EDGE_INT_MAP_M ((DPORT_APP_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_APP_TG_WDT_EDGE_INT_MAP_S)) +#define DPORT_APP_TG_WDT_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG_WDT_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x30C) +/* DPORT_APP_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG_LACT_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG_LACT_EDGE_INT_MAP_M ((DPORT_APP_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_APP_TG_LACT_EDGE_INT_MAP_S)) +#define DPORT_APP_TG_LACT_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG_LACT_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x310) +/* DPORT_APP_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG1_T0_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG1_T0_EDGE_INT_MAP_M ((DPORT_APP_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_T0_EDGE_INT_MAP_S)) +#define DPORT_APP_TG1_T0_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG1_T0_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x314) +/* DPORT_APP_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG1_T1_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG1_T1_EDGE_INT_MAP_M ((DPORT_APP_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_T1_EDGE_INT_MAP_S)) +#define DPORT_APP_TG1_T1_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG1_T1_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x318) +/* DPORT_APP_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG1_WDT_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_M ((DPORT_APP_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_WDT_EDGE_INT_MAP_S)) +#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_S 0 + +#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x31C) +/* DPORT_APP_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_TG1_LACT_EDGE_INT_MAP 0x0000001F +#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_M ((DPORT_APP_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_LACT_EDGE_INT_MAP_S)) +#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_V 0x1F +#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_S 0 + +#define DPORT_APP_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x320) +/* DPORT_APP_MMU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_MMU_IA_INT_MAP 0x0000001F +#define DPORT_APP_MMU_IA_INT_MAP_M ((DPORT_APP_MMU_IA_INT_MAP_V)<<(DPORT_APP_MMU_IA_INT_MAP_S)) +#define DPORT_APP_MMU_IA_INT_MAP_V 0x1F +#define DPORT_APP_MMU_IA_INT_MAP_S 0 + +#define DPORT_APP_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x324) +/* DPORT_APP_MPU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_MPU_IA_INT_MAP 0x0000001F +#define DPORT_APP_MPU_IA_INT_MAP_M ((DPORT_APP_MPU_IA_INT_MAP_V)<<(DPORT_APP_MPU_IA_INT_MAP_S)) +#define DPORT_APP_MPU_IA_INT_MAP_V 0x1F +#define DPORT_APP_MPU_IA_INT_MAP_S 0 + +#define DPORT_APP_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x328) +/* DPORT_APP_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/* Description: */ +#define DPORT_APP_CACHE_IA_INT_MAP 0x0000001F +#define DPORT_APP_CACHE_IA_INT_MAP_M ((DPORT_APP_CACHE_IA_INT_MAP_V)<<(DPORT_APP_CACHE_IA_INT_MAP_S)) +#define DPORT_APP_CACHE_IA_INT_MAP_V 0x1F +#define DPORT_APP_CACHE_IA_INT_MAP_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_UART_REG (DR_REG_DPORT_BASE + 0x32C) +/* DPORT_UART_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_UART_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_UART_ACCESS_GRANT_CONFIG_M ((DPORT_UART_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART_ACCESS_GRANT_CONFIG_S)) +#define DPORT_UART_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_UART_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SPI1_REG (DR_REG_DPORT_BASE + 0x330) +/* DPORT_SPI1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_SPI1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SPI1_ACCESS_GRANT_CONFIG_M ((DPORT_SPI1_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SPI1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SPI1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SPI0_REG (DR_REG_DPORT_BASE + 0x334) +/* DPORT_SPI0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_SPI0_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SPI0_ACCESS_GRANT_CONFIG_M ((DPORT_SPI0_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI0_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SPI0_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SPI0_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_GPIO_REG (DR_REG_DPORT_BASE + 0x338) +/* DPORT_GPIO_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_GPIO_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_GPIO_ACCESS_GRANT_CONFIG_M ((DPORT_GPIO_ACCESS_GRANT_CONFIG_V)<<(DPORT_GPIO_ACCESS_GRANT_CONFIG_S)) +#define DPORT_GPIO_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_GPIO_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_FE2_REG (DR_REG_DPORT_BASE + 0x33C) +/* DPORT_FE2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_FE2_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_FE2_ACCESS_GRANT_CONFIG_M ((DPORT_FE2_ACCESS_GRANT_CONFIG_V)<<(DPORT_FE2_ACCESS_GRANT_CONFIG_S)) +#define DPORT_FE2_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_FE2_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_FE_REG (DR_REG_DPORT_BASE + 0x340) +/* DPORT_FE_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_FE_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_FE_ACCESS_GRANT_CONFIG_M ((DPORT_FE_ACCESS_GRANT_CONFIG_V)<<(DPORT_FE_ACCESS_GRANT_CONFIG_S)) +#define DPORT_FE_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_FE_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_TIMER_REG (DR_REG_DPORT_BASE + 0x344) +/* DPORT_TIMER_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_TIMER_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_TIMER_ACCESS_GRANT_CONFIG_M ((DPORT_TIMER_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMER_ACCESS_GRANT_CONFIG_S)) +#define DPORT_TIMER_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_TIMER_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_RTC_REG (DR_REG_DPORT_BASE + 0x348) +/* DPORT_RTC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_RTC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_RTC_ACCESS_GRANT_CONFIG_M ((DPORT_RTC_ACCESS_GRANT_CONFIG_V)<<(DPORT_RTC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_RTC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_RTC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG (DR_REG_DPORT_BASE + 0x34C) +/* DPORT_IOMUX_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_IOMUX_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_IOMUX_ACCESS_GRANT_CONFIG_M ((DPORT_IOMUX_ACCESS_GRANT_CONFIG_V)<<(DPORT_IOMUX_ACCESS_GRANT_CONFIG_S)) +#define DPORT_IOMUX_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_IOMUX_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_WDG_REG (DR_REG_DPORT_BASE + 0x350) +/* DPORT_WDG_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_WDG_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_WDG_ACCESS_GRANT_CONFIG_M ((DPORT_WDG_ACCESS_GRANT_CONFIG_V)<<(DPORT_WDG_ACCESS_GRANT_CONFIG_S)) +#define DPORT_WDG_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_WDG_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_HINF_REG (DR_REG_DPORT_BASE + 0x354) +/* DPORT_HINF_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_HINF_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_HINF_ACCESS_GRANT_CONFIG_M ((DPORT_HINF_ACCESS_GRANT_CONFIG_V)<<(DPORT_HINF_ACCESS_GRANT_CONFIG_S)) +#define DPORT_HINF_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_HINF_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_UHCI1_REG (DR_REG_DPORT_BASE + 0x358) +/* DPORT_UHCI1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_UHCI1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_UHCI1_ACCESS_GRANT_CONFIG_M ((DPORT_UHCI1_ACCESS_GRANT_CONFIG_V)<<(DPORT_UHCI1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_UHCI1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_UHCI1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_MISC_REG (DR_REG_DPORT_BASE + 0x35C) +/* DPORT_MISC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_MISC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_MISC_ACCESS_GRANT_CONFIG_M ((DPORT_MISC_ACCESS_GRANT_CONFIG_V)<<(DPORT_MISC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_MISC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_MISC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_I2C_REG (DR_REG_DPORT_BASE + 0x360) +/* DPORT_I2C_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_I2C_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_I2C_ACCESS_GRANT_CONFIG_M ((DPORT_I2C_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2C_ACCESS_GRANT_CONFIG_S)) +#define DPORT_I2C_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_I2C_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_I2S0_REG (DR_REG_DPORT_BASE + 0x364) +/* DPORT_I2S0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_I2S0_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_I2S0_ACCESS_GRANT_CONFIG_M ((DPORT_I2S0_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2S0_ACCESS_GRANT_CONFIG_S)) +#define DPORT_I2S0_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_I2S0_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_UART1_REG (DR_REG_DPORT_BASE + 0x368) +/* DPORT_UART1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_UART1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_UART1_ACCESS_GRANT_CONFIG_M ((DPORT_UART1_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_UART1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_UART1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_BT_REG (DR_REG_DPORT_BASE + 0x36C) +/* DPORT_BT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_BT_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_BT_ACCESS_GRANT_CONFIG_M ((DPORT_BT_ACCESS_GRANT_CONFIG_V)<<(DPORT_BT_ACCESS_GRANT_CONFIG_S)) +#define DPORT_BT_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_BT_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_BT_BUFFER_REG (DR_REG_DPORT_BASE + 0x370) +/* DPORT_BTBUFFER_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_M ((DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V)<<(DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S)) +#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG (DR_REG_DPORT_BASE + 0x374) +/* DPORT_I2CEXT0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_M ((DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S)) +#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_UHCI0_REG (DR_REG_DPORT_BASE + 0x378) +/* DPORT_UHCI0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_UHCI0_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_UHCI0_ACCESS_GRANT_CONFIG_M ((DPORT_UHCI0_ACCESS_GRANT_CONFIG_V)<<(DPORT_UHCI0_ACCESS_GRANT_CONFIG_S)) +#define DPORT_UHCI0_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_UHCI0_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG (DR_REG_DPORT_BASE + 0x37C) +/* DPORT_SLCHOST_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_M ((DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V)<<(DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_RMT_REG (DR_REG_DPORT_BASE + 0x380) +/* DPORT_RMT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_RMT_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_RMT_ACCESS_GRANT_CONFIG_M ((DPORT_RMT_ACCESS_GRANT_CONFIG_V)<<(DPORT_RMT_ACCESS_GRANT_CONFIG_S)) +#define DPORT_RMT_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_RMT_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PCNT_REG (DR_REG_DPORT_BASE + 0x384) +/* DPORT_PCNT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_PCNT_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PCNT_ACCESS_GRANT_CONFIG_M ((DPORT_PCNT_ACCESS_GRANT_CONFIG_V)<<(DPORT_PCNT_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PCNT_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PCNT_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SLC_REG (DR_REG_DPORT_BASE + 0x388) +/* DPORT_SLC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_SLC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SLC_ACCESS_GRANT_CONFIG_M ((DPORT_SLC_ACCESS_GRANT_CONFIG_V)<<(DPORT_SLC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SLC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SLC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_LEDC_REG (DR_REG_DPORT_BASE + 0x38C) +/* DPORT_LEDC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_LEDC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_LEDC_ACCESS_GRANT_CONFIG_M ((DPORT_LEDC_ACCESS_GRANT_CONFIG_V)<<(DPORT_LEDC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_LEDC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_LEDC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_EFUSE_REG (DR_REG_DPORT_BASE + 0x390) +/* DPORT_EFUSE_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_EFUSE_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_EFUSE_ACCESS_GRANT_CONFIG_M ((DPORT_EFUSE_ACCESS_GRANT_CONFIG_V)<<(DPORT_EFUSE_ACCESS_GRANT_CONFIG_S)) +#define DPORT_EFUSE_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_EFUSE_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG (DR_REG_DPORT_BASE + 0x394) +/* DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_M ((DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_BB_REG (DR_REG_DPORT_BASE + 0x398) +/* DPORT_BB_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_BB_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_BB_ACCESS_GRANT_CONFIG_M ((DPORT_BB_ACCESS_GRANT_CONFIG_V)<<(DPORT_BB_ACCESS_GRANT_CONFIG_S)) +#define DPORT_BB_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_BB_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PWM0_REG (DR_REG_DPORT_BASE + 0x39C) +/* DPORT_PWM0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_PWM0_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PWM0_ACCESS_GRANT_CONFIG_M ((DPORT_PWM0_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM0_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PWM0_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PWM0_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG (DR_REG_DPORT_BASE + 0x3A0) +/* DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_M ((DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S)) +#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG (DR_REG_DPORT_BASE + 0x3A4) +/* DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_M ((DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SPI2_REG (DR_REG_DPORT_BASE + 0x3A8) +/* DPORT_SPI2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_SPI2_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SPI2_ACCESS_GRANT_CONFIG_M ((DPORT_SPI2_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI2_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SPI2_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SPI2_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SPI3_REG (DR_REG_DPORT_BASE + 0x3AC) +/* DPORT_SPI3_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_SPI3_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SPI3_ACCESS_GRANT_CONFIG_M ((DPORT_SPI3_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI3_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SPI3_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SPI3_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG (DR_REG_DPORT_BASE + 0x3B0) +/* DPORT_APBCTRL_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_M ((DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V)<<(DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S)) +#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG (DR_REG_DPORT_BASE + 0x3B4) +/* DPORT_I2CEXT1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_M ((DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG (DR_REG_DPORT_BASE + 0x3B8) +/* DPORT_SDIOHOST_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_M ((DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V)<<(DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S)) +#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_EMAC_REG (DR_REG_DPORT_BASE + 0x3BC) +/* DPORT_EMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_EMAC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_EMAC_ACCESS_GRANT_CONFIG_M ((DPORT_EMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_EMAC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_EMAC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_EMAC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_CAN_REG (DR_REG_DPORT_BASE + 0x3C0) +/* DPORT_CAN_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_CAN_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_CAN_ACCESS_GRANT_CONFIG_M ((DPORT_CAN_ACCESS_GRANT_CONFIG_V)<<(DPORT_CAN_ACCESS_GRANT_CONFIG_S)) +#define DPORT_CAN_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_CAN_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PWM1_REG (DR_REG_DPORT_BASE + 0x3C4) +/* DPORT_PWM1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_PWM1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PWM1_ACCESS_GRANT_CONFIG_M ((DPORT_PWM1_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PWM1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PWM1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_I2S1_REG (DR_REG_DPORT_BASE + 0x3C8) +/* DPORT_I2S1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_I2S1_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_I2S1_ACCESS_GRANT_CONFIG_M ((DPORT_I2S1_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2S1_ACCESS_GRANT_CONFIG_S)) +#define DPORT_I2S1_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_I2S1_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_UART2_REG (DR_REG_DPORT_BASE + 0x3CC) +/* DPORT_UART2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_UART2_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_UART2_ACCESS_GRANT_CONFIG_M ((DPORT_UART2_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART2_ACCESS_GRANT_CONFIG_S)) +#define DPORT_UART2_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_UART2_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PWM2_REG (DR_REG_DPORT_BASE + 0x3D0) +/* DPORT_PWM2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_PWM2_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PWM2_ACCESS_GRANT_CONFIG_M ((DPORT_PWM2_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM2_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PWM2_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PWM2_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PWM3_REG (DR_REG_DPORT_BASE + 0x3D4) +/* DPORT_PWM3_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_PWM3_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PWM3_ACCESS_GRANT_CONFIG_M ((DPORT_PWM3_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM3_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PWM3_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PWM3_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_RWBT_REG (DR_REG_DPORT_BASE + 0x3D8) +/* DPORT_RWBT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_RWBT_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_RWBT_ACCESS_GRANT_CONFIG_M ((DPORT_RWBT_ACCESS_GRANT_CONFIG_V)<<(DPORT_RWBT_ACCESS_GRANT_CONFIG_S)) +#define DPORT_RWBT_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_RWBT_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_BTMAC_REG (DR_REG_DPORT_BASE + 0x3DC) +/* DPORT_BTMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_BTMAC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_BTMAC_ACCESS_GRANT_CONFIG_M ((DPORT_BTMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_BTMAC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_BTMAC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_BTMAC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_WIFIMAC_REG (DR_REG_DPORT_BASE + 0x3E0) +/* DPORT_WIFIMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_M ((DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S)) +#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_AHBLITE_MPU_TABLE_PWR_REG (DR_REG_DPORT_BASE + 0x3E4) +/* DPORT_PWR_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_PWR_ACCESS_GRANT_CONFIG 0x0000003F +#define DPORT_PWR_ACCESS_GRANT_CONFIG_M ((DPORT_PWR_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWR_ACCESS_GRANT_CONFIG_S)) +#define DPORT_PWR_ACCESS_GRANT_CONFIG_V 0x3F +#define DPORT_PWR_ACCESS_GRANT_CONFIG_S 0 + +#define DPORT_MEM_ACCESS_DBUG0_REG (DR_REG_DPORT_BASE + 0x3E8) +/* DPORT_INTERNAL_SRAM_MMU_MULTI_HIT : RO ;bitpos:[29:26] ;default: 4'b0 ; */ +/* Description: */ +#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT 0x0000000F +#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_M ((DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V)<<(DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S)) +#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V 0xF +#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S 26 +/* DPORT_INTERNAL_SRAM_IA : RO ;bitpos:[25:14] ;default: 12'b0 ; */ +/* Description: */ +#define DPORT_INTERNAL_SRAM_IA 0x00000FFF +#define DPORT_INTERNAL_SRAM_IA_M ((DPORT_INTERNAL_SRAM_IA_V)<<(DPORT_INTERNAL_SRAM_IA_S)) +#define DPORT_INTERNAL_SRAM_IA_V 0xFFF +#define DPORT_INTERNAL_SRAM_IA_S 14 +/* DPORT_INTERNAL_SRAM_MMU_AD : RO ;bitpos:[13:10] ;default: 4'b0 ; */ +/* Description: */ +#define DPORT_INTERNAL_SRAM_MMU_AD 0x0000000F +#define DPORT_INTERNAL_SRAM_MMU_AD_M ((DPORT_INTERNAL_SRAM_MMU_AD_V)<<(DPORT_INTERNAL_SRAM_MMU_AD_S)) +#define DPORT_INTERNAL_SRAM_MMU_AD_V 0xF +#define DPORT_INTERNAL_SRAM_MMU_AD_S 10 +/* DPORT_SHARE_ROM_IA : RO ;bitpos:[9:6] ;default: 4'b0 ; */ +/* Description: */ +#define DPORT_SHARE_ROM_IA 0x0000000F +#define DPORT_SHARE_ROM_IA_M ((DPORT_SHARE_ROM_IA_V)<<(DPORT_SHARE_ROM_IA_S)) +#define DPORT_SHARE_ROM_IA_V 0xF +#define DPORT_SHARE_ROM_IA_S 6 +/* DPORT_SHARE_ROM_MPU_AD : RO ;bitpos:[5:4] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_SHARE_ROM_MPU_AD 0x00000003 +#define DPORT_SHARE_ROM_MPU_AD_M ((DPORT_SHARE_ROM_MPU_AD_V)<<(DPORT_SHARE_ROM_MPU_AD_S)) +#define DPORT_SHARE_ROM_MPU_AD_V 0x3 +#define DPORT_SHARE_ROM_MPU_AD_S 4 +/* DPORT_APP_ROM_IA : RO ;bitpos:[3] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_ROM_IA (BIT(3)) +#define DPORT_APP_ROM_IA_M (BIT(3)) +#define DPORT_APP_ROM_IA_V 0x1 +#define DPORT_APP_ROM_IA_S 3 +/* DPORT_APP_ROM_MPU_AD : RO ;bitpos:[2] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_ROM_MPU_AD (BIT(2)) +#define DPORT_APP_ROM_MPU_AD_M (BIT(2)) +#define DPORT_APP_ROM_MPU_AD_V 0x1 +#define DPORT_APP_ROM_MPU_AD_S 2 +/* DPORT_PRO_ROM_IA : RO ;bitpos:[1] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_ROM_IA (BIT(1)) +#define DPORT_PRO_ROM_IA_M (BIT(1)) +#define DPORT_PRO_ROM_IA_V 0x1 +#define DPORT_PRO_ROM_IA_S 1 +/* DPORT_PRO_ROM_MPU_AD : RO ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_ROM_MPU_AD (BIT(0)) +#define DPORT_PRO_ROM_MPU_AD_M (BIT(0)) +#define DPORT_PRO_ROM_MPU_AD_V 0x1 +#define DPORT_PRO_ROM_MPU_AD_S 0 + +#define DPORT_MEM_ACCESS_DBUG1_REG (DR_REG_DPORT_BASE + 0x3EC) +/* DPORT_AHBLITE_IA : RO ;bitpos:[10] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_AHBLITE_IA (BIT(10)) +#define DPORT_AHBLITE_IA_M (BIT(10)) +#define DPORT_AHBLITE_IA_V 0x1 +#define DPORT_AHBLITE_IA_S 10 +/* DPORT_AHBLITE_ACCESS_DENY : RO ;bitpos:[9] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_AHBLITE_ACCESS_DENY (BIT(9)) +#define DPORT_AHBLITE_ACCESS_DENY_M (BIT(9)) +#define DPORT_AHBLITE_ACCESS_DENY_V 0x1 +#define DPORT_AHBLITE_ACCESS_DENY_S 9 +/* DPORT_AHB_ACCESS_DENY : RO ;bitpos:[8] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_AHB_ACCESS_DENY (BIT(8)) +#define DPORT_AHB_ACCESS_DENY_M (BIT(8)) +#define DPORT_AHB_ACCESS_DENY_V 0x1 +#define DPORT_AHB_ACCESS_DENY_S 8 +/* DPORT_PIDGEN_IA : RO ;bitpos:[7:6] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_PIDGEN_IA 0x00000003 +#define DPORT_PIDGEN_IA_M ((DPORT_PIDGEN_IA_V)<<(DPORT_PIDGEN_IA_S)) +#define DPORT_PIDGEN_IA_V 0x3 +#define DPORT_PIDGEN_IA_S 6 +/* DPORT_ARB_IA : RO ;bitpos:[5:4] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_ARB_IA 0x00000003 +#define DPORT_ARB_IA_M ((DPORT_ARB_IA_V)<<(DPORT_ARB_IA_S)) +#define DPORT_ARB_IA_V 0x3 +#define DPORT_ARB_IA_S 4 +/* DPORT_INTERNAL_SRAM_MMU_MISS : RO ;bitpos:[3:0] ;default: 4'b0 ; */ +/* Description: */ +#define DPORT_INTERNAL_SRAM_MMU_MISS 0x0000000F +#define DPORT_INTERNAL_SRAM_MMU_MISS_M ((DPORT_INTERNAL_SRAM_MMU_MISS_V)<<(DPORT_INTERNAL_SRAM_MMU_MISS_S)) +#define DPORT_INTERNAL_SRAM_MMU_MISS_V 0xF +#define DPORT_INTERNAL_SRAM_MMU_MISS_S 0 + +#define DPORT_PRO_DCACHE_DBUG0_REG (DR_REG_DPORT_BASE + 0x3F0) +/* DPORT_PRO_RX_END : RO ;bitpos:[23] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_RX_END (BIT(23)) +#define DPORT_PRO_RX_END_M (BIT(23)) +#define DPORT_PRO_RX_END_V 0x1 +#define DPORT_PRO_RX_END_S 23 +/* DPORT_PRO_SLAVE_WDATA_V : RO ;bitpos:[22] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_SLAVE_WDATA_V (BIT(22)) +#define DPORT_PRO_SLAVE_WDATA_V_M (BIT(22)) +#define DPORT_PRO_SLAVE_WDATA_V_V 0x1 +#define DPORT_PRO_SLAVE_WDATA_V_S 22 +/* DPORT_PRO_SLAVE_WR : RO ;bitpos:[21] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_SLAVE_WR (BIT(21)) +#define DPORT_PRO_SLAVE_WR_M (BIT(21)) +#define DPORT_PRO_SLAVE_WR_V 0x1 +#define DPORT_PRO_SLAVE_WR_S 21 +/* DPORT_PRO_TX_END : RO ;bitpos:[20] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_TX_END (BIT(20)) +#define DPORT_PRO_TX_END_M (BIT(20)) +#define DPORT_PRO_TX_END_V 0x1 +#define DPORT_PRO_TX_END_S 20 +/* DPORT_PRO_WR_BAK_TO_READ : RO ;bitpos:[19] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_WR_BAK_TO_READ (BIT(19)) +#define DPORT_PRO_WR_BAK_TO_READ_M (BIT(19)) +#define DPORT_PRO_WR_BAK_TO_READ_V 0x1 +#define DPORT_PRO_WR_BAK_TO_READ_S 19 +/* DPORT_PRO_CACHE_STATE : RO ;bitpos:[18:7] ;default: 12'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_STATE 0x00000FFF +#define DPORT_PRO_CACHE_STATE_M ((DPORT_PRO_CACHE_STATE_V)<<(DPORT_PRO_CACHE_STATE_S)) +#define DPORT_PRO_CACHE_STATE_V 0xFFF +#define DPORT_PRO_CACHE_STATE_S 7 +/* DPORT_PRO_CACHE_IA : RO ;bitpos:[6:1] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_IA 0x0000003F +#define DPORT_PRO_CACHE_IA_M ((DPORT_PRO_CACHE_IA_V)<<(DPORT_PRO_CACHE_IA_S)) +#define DPORT_PRO_CACHE_IA_V 0x3F +#define DPORT_PRO_CACHE_IA_S 1 +/* DPORT_PRO_CACHE_MMU_IA : RO ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_MMU_IA (BIT(0)) +#define DPORT_PRO_CACHE_MMU_IA_M (BIT(0)) +#define DPORT_PRO_CACHE_MMU_IA_V 0x1 +#define DPORT_PRO_CACHE_MMU_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG1_REG (DR_REG_DPORT_BASE + 0x3F4) +/* DPORT_PRO_CTAG_RAM_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_PRO_CTAG_RAM_RDATA 0xFFFFFFFF +#define DPORT_PRO_CTAG_RAM_RDATA_M ((DPORT_PRO_CTAG_RAM_RDATA_V)<<(DPORT_PRO_CTAG_RAM_RDATA_S)) +#define DPORT_PRO_CTAG_RAM_RDATA_V 0xFFFFFFFF +#define DPORT_PRO_CTAG_RAM_RDATA_S 0 + +#define DPORT_PRO_DCACHE_DBUG2_REG (DR_REG_DPORT_BASE + 0x3F8) +/* DPORT_PRO_CACHE_VADDR : RO ;bitpos:[26:0] ;default: 27'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_VADDR 0x07FFFFFF +#define DPORT_PRO_CACHE_VADDR_M ((DPORT_PRO_CACHE_VADDR_V)<<(DPORT_PRO_CACHE_VADDR_S)) +#define DPORT_PRO_CACHE_VADDR_V 0x7FFFFFF +#define DPORT_PRO_CACHE_VADDR_S 0 + +#define DPORT_PRO_DCACHE_DBUG3_REG (DR_REG_DPORT_BASE + 0x3FC) +/* DPORT_PRO_CACHE_IRAM0_PID_ERROR : RO ;bitpos:[15] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CACHE_IRAM0_PID_ERROR (BIT(15)) +#define DPORT_PRO_CACHE_IRAM0_PID_ERROR_M (BIT(15)) +#define DPORT_PRO_CACHE_IRAM0_PID_ERROR_V 0x1 +#define DPORT_PRO_CACHE_IRAM0_PID_ERROR_S 15 +/* DPORT_PRO_CPU_DISABLED_CACHE_IA : RO ;bitpos:[14:9] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_PRO_CPU_DISABLED_CACHE_IA 0x0000003F +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_M ((DPORT_PRO_CPU_DISABLED_CACHE_IA_V)<<(DPORT_PRO_CPU_DISABLED_CACHE_IA_S)) +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_V 0x3F +#define DPORT_PRO_CPU_DISABLED_CACHE_IA_S 9 +/* DPORT_PRO_MMU_RDATA : RO ;bitpos:[8:0] ;default: 9'h0 ; */ +/* Description: */ +#define DPORT_PRO_MMU_RDATA 0x000001FF +#define DPORT_PRO_MMU_RDATA_M ((DPORT_PRO_MMU_RDATA_V)<<(DPORT_PRO_MMU_RDATA_S)) +#define DPORT_PRO_MMU_RDATA_V 0x1FF +#define DPORT_PRO_MMU_RDATA_S 0 + +#define DPORT_PRO_DCACHE_DBUG4_REG (DR_REG_DPORT_BASE + 0x400) +/* DPORT_PRO_DRAM1ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_PRO_DRAM1ADDR0_IA 0x000FFFFF +#define DPORT_PRO_DRAM1ADDR0_IA_M ((DPORT_PRO_DRAM1ADDR0_IA_V)<<(DPORT_PRO_DRAM1ADDR0_IA_S)) +#define DPORT_PRO_DRAM1ADDR0_IA_V 0xFFFFF +#define DPORT_PRO_DRAM1ADDR0_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG5_REG (DR_REG_DPORT_BASE + 0x404) +/* DPORT_PRO_DROM0ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_PRO_DROM0ADDR0_IA 0x000FFFFF +#define DPORT_PRO_DROM0ADDR0_IA_M ((DPORT_PRO_DROM0ADDR0_IA_V)<<(DPORT_PRO_DROM0ADDR0_IA_S)) +#define DPORT_PRO_DROM0ADDR0_IA_V 0xFFFFF +#define DPORT_PRO_DROM0ADDR0_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG6_REG (DR_REG_DPORT_BASE + 0x408) +/* DPORT_PRO_IRAM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_PRO_IRAM0ADDR_IA 0x000FFFFF +#define DPORT_PRO_IRAM0ADDR_IA_M ((DPORT_PRO_IRAM0ADDR_IA_V)<<(DPORT_PRO_IRAM0ADDR_IA_S)) +#define DPORT_PRO_IRAM0ADDR_IA_V 0xFFFFF +#define DPORT_PRO_IRAM0ADDR_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG7_REG (DR_REG_DPORT_BASE + 0x40C) +/* DPORT_PRO_IRAM1ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_PRO_IRAM1ADDR_IA 0x000FFFFF +#define DPORT_PRO_IRAM1ADDR_IA_M ((DPORT_PRO_IRAM1ADDR_IA_V)<<(DPORT_PRO_IRAM1ADDR_IA_S)) +#define DPORT_PRO_IRAM1ADDR_IA_V 0xFFFFF +#define DPORT_PRO_IRAM1ADDR_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG8_REG (DR_REG_DPORT_BASE + 0x410) +/* DPORT_PRO_IROM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_PRO_IROM0ADDR_IA 0x000FFFFF +#define DPORT_PRO_IROM0ADDR_IA_M ((DPORT_PRO_IROM0ADDR_IA_V)<<(DPORT_PRO_IROM0ADDR_IA_S)) +#define DPORT_PRO_IROM0ADDR_IA_V 0xFFFFF +#define DPORT_PRO_IROM0ADDR_IA_S 0 + +#define DPORT_PRO_DCACHE_DBUG9_REG (DR_REG_DPORT_BASE + 0x414) +/* DPORT_PRO_OPSDRAMADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_PRO_OPSDRAMADDR_IA 0x000FFFFF +#define DPORT_PRO_OPSDRAMADDR_IA_M ((DPORT_PRO_OPSDRAMADDR_IA_V)<<(DPORT_PRO_OPSDRAMADDR_IA_S)) +#define DPORT_PRO_OPSDRAMADDR_IA_V 0xFFFFF +#define DPORT_PRO_OPSDRAMADDR_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG0_REG (DR_REG_DPORT_BASE + 0x418) +/* DPORT_APP_RX_END : RO ;bitpos:[23] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_RX_END (BIT(23)) +#define DPORT_APP_RX_END_M (BIT(23)) +#define DPORT_APP_RX_END_V 0x1 +#define DPORT_APP_RX_END_S 23 +/* DPORT_APP_SLAVE_WDATA_V : RO ;bitpos:[22] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_SLAVE_WDATA_V (BIT(22)) +#define DPORT_APP_SLAVE_WDATA_V_M (BIT(22)) +#define DPORT_APP_SLAVE_WDATA_V_V 0x1 +#define DPORT_APP_SLAVE_WDATA_V_S 22 +/* DPORT_APP_SLAVE_WR : RO ;bitpos:[21] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_SLAVE_WR (BIT(21)) +#define DPORT_APP_SLAVE_WR_M (BIT(21)) +#define DPORT_APP_SLAVE_WR_V 0x1 +#define DPORT_APP_SLAVE_WR_S 21 +/* DPORT_APP_TX_END : RO ;bitpos:[20] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_TX_END (BIT(20)) +#define DPORT_APP_TX_END_M (BIT(20)) +#define DPORT_APP_TX_END_V 0x1 +#define DPORT_APP_TX_END_S 20 +/* DPORT_APP_WR_BAK_TO_READ : RO ;bitpos:[19] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_WR_BAK_TO_READ (BIT(19)) +#define DPORT_APP_WR_BAK_TO_READ_M (BIT(19)) +#define DPORT_APP_WR_BAK_TO_READ_V 0x1 +#define DPORT_APP_WR_BAK_TO_READ_S 19 +/* DPORT_APP_CACHE_STATE : RO ;bitpos:[18:7] ;default: 12'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_STATE 0x00000FFF +#define DPORT_APP_CACHE_STATE_M ((DPORT_APP_CACHE_STATE_V)<<(DPORT_APP_CACHE_STATE_S)) +#define DPORT_APP_CACHE_STATE_V 0xFFF +#define DPORT_APP_CACHE_STATE_S 7 +/* DPORT_APP_CACHE_IA : RO ;bitpos:[6:1] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_IA 0x0000003F +#define DPORT_APP_CACHE_IA_M ((DPORT_APP_CACHE_IA_V)<<(DPORT_APP_CACHE_IA_S)) +#define DPORT_APP_CACHE_IA_V 0x3F +#define DPORT_APP_CACHE_IA_S 1 +/* DPORT_APP_CACHE_MMU_IA : RO ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_MMU_IA (BIT(0)) +#define DPORT_APP_CACHE_MMU_IA_M (BIT(0)) +#define DPORT_APP_CACHE_MMU_IA_V 0x1 +#define DPORT_APP_CACHE_MMU_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG1_REG (DR_REG_DPORT_BASE + 0x41C) +/* DPORT_APP_CTAG_RAM_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_APP_CTAG_RAM_RDATA 0xFFFFFFFF +#define DPORT_APP_CTAG_RAM_RDATA_M ((DPORT_APP_CTAG_RAM_RDATA_V)<<(DPORT_APP_CTAG_RAM_RDATA_S)) +#define DPORT_APP_CTAG_RAM_RDATA_V 0xFFFFFFFF +#define DPORT_APP_CTAG_RAM_RDATA_S 0 + +#define DPORT_APP_DCACHE_DBUG2_REG (DR_REG_DPORT_BASE + 0x420) +/* DPORT_APP_CACHE_VADDR : RO ;bitpos:[26:0] ;default: 27'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_VADDR 0x07FFFFFF +#define DPORT_APP_CACHE_VADDR_M ((DPORT_APP_CACHE_VADDR_V)<<(DPORT_APP_CACHE_VADDR_S)) +#define DPORT_APP_CACHE_VADDR_V 0x7FFFFFF +#define DPORT_APP_CACHE_VADDR_S 0 + +#define DPORT_APP_DCACHE_DBUG3_REG (DR_REG_DPORT_BASE + 0x424) +/* DPORT_APP_CACHE_IRAM0_PID_ERROR : RO ;bitpos:[15] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CACHE_IRAM0_PID_ERROR (BIT(15)) +#define DPORT_APP_CACHE_IRAM0_PID_ERROR_M (BIT(15)) +#define DPORT_APP_CACHE_IRAM0_PID_ERROR_V 0x1 +#define DPORT_APP_CACHE_IRAM0_PID_ERROR_S 15 +/* DPORT_APP_CPU_DISABLED_CACHE_IA : RO ;bitpos:[14:9] ;default: 6'b0 ; */ +/* Description: */ +#define DPORT_APP_CPU_DISABLED_CACHE_IA 0x0000003F +#define DPORT_APP_CPU_DISABLED_CACHE_IA_M ((DPORT_APP_CPU_DISABLED_CACHE_IA_V)<<(DPORT_APP_CPU_DISABLED_CACHE_IA_S)) +#define DPORT_APP_CPU_DISABLED_CACHE_IA_V 0x3F +#define DPORT_APP_CPU_DISABLED_CACHE_IA_S 9 +/* DPORT_APP_MMU_RDATA : RO ;bitpos:[8:0] ;default: 9'h0 ; */ +/* Description: */ +#define DPORT_APP_MMU_RDATA 0x000001FF +#define DPORT_APP_MMU_RDATA_M ((DPORT_APP_MMU_RDATA_V)<<(DPORT_APP_MMU_RDATA_S)) +#define DPORT_APP_MMU_RDATA_V 0x1FF +#define DPORT_APP_MMU_RDATA_S 0 + +#define DPORT_APP_DCACHE_DBUG4_REG (DR_REG_DPORT_BASE + 0x428) +/* DPORT_APP_DRAM1ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_APP_DRAM1ADDR0_IA 0x000FFFFF +#define DPORT_APP_DRAM1ADDR0_IA_M ((DPORT_APP_DRAM1ADDR0_IA_V)<<(DPORT_APP_DRAM1ADDR0_IA_S)) +#define DPORT_APP_DRAM1ADDR0_IA_V 0xFFFFF +#define DPORT_APP_DRAM1ADDR0_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG5_REG (DR_REG_DPORT_BASE + 0x42C) +/* DPORT_APP_DROM0ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_APP_DROM0ADDR0_IA 0x000FFFFF +#define DPORT_APP_DROM0ADDR0_IA_M ((DPORT_APP_DROM0ADDR0_IA_V)<<(DPORT_APP_DROM0ADDR0_IA_S)) +#define DPORT_APP_DROM0ADDR0_IA_V 0xFFFFF +#define DPORT_APP_DROM0ADDR0_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG6_REG (DR_REG_DPORT_BASE + 0x430) +/* DPORT_APP_IRAM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_APP_IRAM0ADDR_IA 0x000FFFFF +#define DPORT_APP_IRAM0ADDR_IA_M ((DPORT_APP_IRAM0ADDR_IA_V)<<(DPORT_APP_IRAM0ADDR_IA_S)) +#define DPORT_APP_IRAM0ADDR_IA_V 0xFFFFF +#define DPORT_APP_IRAM0ADDR_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG7_REG (DR_REG_DPORT_BASE + 0x434) +/* DPORT_APP_IRAM1ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_APP_IRAM1ADDR_IA 0x000FFFFF +#define DPORT_APP_IRAM1ADDR_IA_M ((DPORT_APP_IRAM1ADDR_IA_V)<<(DPORT_APP_IRAM1ADDR_IA_S)) +#define DPORT_APP_IRAM1ADDR_IA_V 0xFFFFF +#define DPORT_APP_IRAM1ADDR_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG8_REG (DR_REG_DPORT_BASE + 0x438) +/* DPORT_APP_IROM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_APP_IROM0ADDR_IA 0x000FFFFF +#define DPORT_APP_IROM0ADDR_IA_M ((DPORT_APP_IROM0ADDR_IA_V)<<(DPORT_APP_IROM0ADDR_IA_S)) +#define DPORT_APP_IROM0ADDR_IA_V 0xFFFFF +#define DPORT_APP_IROM0ADDR_IA_S 0 + +#define DPORT_APP_DCACHE_DBUG9_REG (DR_REG_DPORT_BASE + 0x43C) +/* DPORT_APP_OPSDRAMADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ +/* Description: */ +#define DPORT_APP_OPSDRAMADDR_IA 0x000FFFFF +#define DPORT_APP_OPSDRAMADDR_IA_M ((DPORT_APP_OPSDRAMADDR_IA_V)<<(DPORT_APP_OPSDRAMADDR_IA_S)) +#define DPORT_APP_OPSDRAMADDR_IA_V 0xFFFFF +#define DPORT_APP_OPSDRAMADDR_IA_S 0 + +#define DPORT_PRO_CPU_RECORD_CTRL_REG (DR_REG_DPORT_BASE + 0x440) +/* DPORT_PRO_CPU_PDEBUG_ENABLE : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PRO_CPU_PDEBUG_ENABLE (BIT(8)) +#define DPORT_PRO_CPU_PDEBUG_ENABLE_M (BIT(8)) +#define DPORT_PRO_CPU_PDEBUG_ENABLE_V 0x1 +#define DPORT_PRO_CPU_PDEBUG_ENABLE_S 8 +/* DPORT_PRO_CPU_RECORD_DISABLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CPU_RECORD_DISABLE (BIT(4)) +#define DPORT_PRO_CPU_RECORD_DISABLE_M (BIT(4)) +#define DPORT_PRO_CPU_RECORD_DISABLE_V 0x1 +#define DPORT_PRO_CPU_RECORD_DISABLE_S 4 +/* DPORT_PRO_CPU_RECORD_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CPU_RECORD_ENABLE (BIT(0)) +#define DPORT_PRO_CPU_RECORD_ENABLE_M (BIT(0)) +#define DPORT_PRO_CPU_RECORD_ENABLE_V 0x1 +#define DPORT_PRO_CPU_RECORD_ENABLE_S 0 + +#define DPORT_PRO_CPU_RECORD_STATUS_REG (DR_REG_DPORT_BASE + 0x444) +/* DPORT_PRO_CPU_RECORDING : RO ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PRO_CPU_RECORDING (BIT(0)) +#define DPORT_PRO_CPU_RECORDING_M (BIT(0)) +#define DPORT_PRO_CPU_RECORDING_V 0x1 +#define DPORT_PRO_CPU_RECORDING_S 0 + +#define DPORT_PRO_CPU_RECORD_PID_REG (DR_REG_DPORT_BASE + 0x448) +/* DPORT_RECORD_PRO_PID : RO ;bitpos:[2:0] ;default: 3'd0 ; */ +/* Description: */ +#define DPORT_RECORD_PRO_PID 0x00000007 +#define DPORT_RECORD_PRO_PID_M ((DPORT_RECORD_PRO_PID_V)<<(DPORT_RECORD_PRO_PID_S)) +#define DPORT_RECORD_PRO_PID_V 0x7 +#define DPORT_RECORD_PRO_PID_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGINST_REG (DR_REG_DPORT_BASE + 0x44C) +/* DPORT_RECORD_PRO_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_PRO_PDEBUGINST 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGINST_M ((DPORT_RECORD_PRO_PDEBUGINST_V)<<(DPORT_RECORD_PRO_PDEBUGINST_S)) +#define DPORT_RECORD_PRO_PDEBUGINST_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGINST_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG (DR_REG_DPORT_BASE + 0x450) +/* DPORT_RECORD_PRO_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/* Description: */ +#define DPORT_RECORD_PRO_PDEBUGSTATUS 0x000000FF +#define DPORT_RECORD_PRO_PDEBUGSTATUS_M ((DPORT_RECORD_PRO_PDEBUGSTATUS_V)<<(DPORT_RECORD_PRO_PDEBUGSTATUS_S)) +#define DPORT_RECORD_PRO_PDEBUGSTATUS_V 0xFF +#define DPORT_RECORD_PRO_PDEBUGSTATUS_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG (DR_REG_DPORT_BASE + 0x454) +/* DPORT_RECORD_PRO_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_PRO_PDEBUGDATA 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGDATA_M ((DPORT_RECORD_PRO_PDEBUGDATA_V)<<(DPORT_RECORD_PRO_PDEBUGDATA_S)) +#define DPORT_RECORD_PRO_PDEBUGDATA_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGDATA_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGPC_REG (DR_REG_DPORT_BASE + 0x458) +/* DPORT_RECORD_PRO_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_PRO_PDEBUGPC 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGPC_M ((DPORT_RECORD_PRO_PDEBUGPC_V)<<(DPORT_RECORD_PRO_PDEBUGPC_S)) +#define DPORT_RECORD_PRO_PDEBUGPC_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGPC_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG (DR_REG_DPORT_BASE + 0x45C) +/* DPORT_RECORD_PRO_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_PRO_PDEBUGLS0STAT 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0STAT_M ((DPORT_RECORD_PRO_PDEBUGLS0STAT_V)<<(DPORT_RECORD_PRO_PDEBUGLS0STAT_S)) +#define DPORT_RECORD_PRO_PDEBUGLS0STAT_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0STAT_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG (DR_REG_DPORT_BASE + 0x460) +/* DPORT_RECORD_PRO_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_PRO_PDEBUGLS0ADDR 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0ADDR_M ((DPORT_RECORD_PRO_PDEBUGLS0ADDR_V)<<(DPORT_RECORD_PRO_PDEBUGLS0ADDR_S)) +#define DPORT_RECORD_PRO_PDEBUGLS0ADDR_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0ADDR_S 0 + +#define DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG (DR_REG_DPORT_BASE + 0x464) +/* DPORT_RECORD_PRO_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_PRO_PDEBUGLS0DATA 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0DATA_M ((DPORT_RECORD_PRO_PDEBUGLS0DATA_V)<<(DPORT_RECORD_PRO_PDEBUGLS0DATA_S)) +#define DPORT_RECORD_PRO_PDEBUGLS0DATA_V 0xFFFFFFFF +#define DPORT_RECORD_PRO_PDEBUGLS0DATA_S 0 + +#define DPORT_APP_CPU_RECORD_CTRL_REG (DR_REG_DPORT_BASE + 0x468) +/* DPORT_APP_CPU_PDEBUG_ENABLE : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APP_CPU_PDEBUG_ENABLE (BIT(8)) +#define DPORT_APP_CPU_PDEBUG_ENABLE_M (BIT(8)) +#define DPORT_APP_CPU_PDEBUG_ENABLE_V 0x1 +#define DPORT_APP_CPU_PDEBUG_ENABLE_S 8 +/* DPORT_APP_CPU_RECORD_DISABLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CPU_RECORD_DISABLE (BIT(4)) +#define DPORT_APP_CPU_RECORD_DISABLE_M (BIT(4)) +#define DPORT_APP_CPU_RECORD_DISABLE_V 0x1 +#define DPORT_APP_CPU_RECORD_DISABLE_S 4 +/* DPORT_APP_CPU_RECORD_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CPU_RECORD_ENABLE (BIT(0)) +#define DPORT_APP_CPU_RECORD_ENABLE_M (BIT(0)) +#define DPORT_APP_CPU_RECORD_ENABLE_V 0x1 +#define DPORT_APP_CPU_RECORD_ENABLE_S 0 + +#define DPORT_APP_CPU_RECORD_STATUS_REG (DR_REG_DPORT_BASE + 0x46C) +/* DPORT_APP_CPU_RECORDING : RO ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_APP_CPU_RECORDING (BIT(0)) +#define DPORT_APP_CPU_RECORDING_M (BIT(0)) +#define DPORT_APP_CPU_RECORDING_V 0x1 +#define DPORT_APP_CPU_RECORDING_S 0 + +#define DPORT_APP_CPU_RECORD_PID_REG (DR_REG_DPORT_BASE + 0x470) +/* DPORT_RECORD_APP_PID : RO ;bitpos:[2:0] ;default: 3'd0 ; */ +/* Description: */ +#define DPORT_RECORD_APP_PID 0x00000007 +#define DPORT_RECORD_APP_PID_M ((DPORT_RECORD_APP_PID_V)<<(DPORT_RECORD_APP_PID_S)) +#define DPORT_RECORD_APP_PID_V 0x7 +#define DPORT_RECORD_APP_PID_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGINST_REG (DR_REG_DPORT_BASE + 0x474) +/* DPORT_RECORD_APP_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_APP_PDEBUGINST 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGINST_M ((DPORT_RECORD_APP_PDEBUGINST_V)<<(DPORT_RECORD_APP_PDEBUGINST_S)) +#define DPORT_RECORD_APP_PDEBUGINST_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGINST_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG (DR_REG_DPORT_BASE + 0x478) +/* DPORT_RECORD_APP_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/* Description: */ +#define DPORT_RECORD_APP_PDEBUGSTATUS 0x000000FF +#define DPORT_RECORD_APP_PDEBUGSTATUS_M ((DPORT_RECORD_APP_PDEBUGSTATUS_V)<<(DPORT_RECORD_APP_PDEBUGSTATUS_S)) +#define DPORT_RECORD_APP_PDEBUGSTATUS_V 0xFF +#define DPORT_RECORD_APP_PDEBUGSTATUS_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGDATA_REG (DR_REG_DPORT_BASE + 0x47C) +/* DPORT_RECORD_APP_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_APP_PDEBUGDATA 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGDATA_M ((DPORT_RECORD_APP_PDEBUGDATA_V)<<(DPORT_RECORD_APP_PDEBUGDATA_S)) +#define DPORT_RECORD_APP_PDEBUGDATA_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGDATA_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGPC_REG (DR_REG_DPORT_BASE + 0x480) +/* DPORT_RECORD_APP_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_APP_PDEBUGPC 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGPC_M ((DPORT_RECORD_APP_PDEBUGPC_V)<<(DPORT_RECORD_APP_PDEBUGPC_S)) +#define DPORT_RECORD_APP_PDEBUGPC_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGPC_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG (DR_REG_DPORT_BASE + 0x484) +/* DPORT_RECORD_APP_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_APP_PDEBUGLS0STAT 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0STAT_M ((DPORT_RECORD_APP_PDEBUGLS0STAT_V)<<(DPORT_RECORD_APP_PDEBUGLS0STAT_S)) +#define DPORT_RECORD_APP_PDEBUGLS0STAT_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0STAT_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG (DR_REG_DPORT_BASE + 0x488) +/* DPORT_RECORD_APP_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_APP_PDEBUGLS0ADDR 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0ADDR_M ((DPORT_RECORD_APP_PDEBUGLS0ADDR_V)<<(DPORT_RECORD_APP_PDEBUGLS0ADDR_S)) +#define DPORT_RECORD_APP_PDEBUGLS0ADDR_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0ADDR_S 0 + +#define DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG (DR_REG_DPORT_BASE + 0x48C) +/* DPORT_RECORD_APP_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/* Description: */ +#define DPORT_RECORD_APP_PDEBUGLS0DATA 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0DATA_M ((DPORT_RECORD_APP_PDEBUGLS0DATA_V)<<(DPORT_RECORD_APP_PDEBUGLS0DATA_S)) +#define DPORT_RECORD_APP_PDEBUGLS0DATA_V 0xFFFFFFFF +#define DPORT_RECORD_APP_PDEBUGLS0DATA_S 0 + +#define DPORT_RSA_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x490) +/* DPORT_RSA_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_RSA_PD (BIT(0)) +#define DPORT_RSA_PD_M (BIT(0)) +#define DPORT_RSA_PD_V 0x1 +#define DPORT_RSA_PD_S 0 + +#define DPORT_ROM_MPU_TABLE0_REG (DR_REG_DPORT_BASE + 0x494) +/* DPORT_ROM_MPU_TABLE0 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_ROM_MPU_TABLE0 0x00000003 +#define DPORT_ROM_MPU_TABLE0_M ((DPORT_ROM_MPU_TABLE0_V)<<(DPORT_ROM_MPU_TABLE0_S)) +#define DPORT_ROM_MPU_TABLE0_V 0x3 +#define DPORT_ROM_MPU_TABLE0_S 0 + +#define DPORT_ROM_MPU_TABLE1_REG (DR_REG_DPORT_BASE + 0x498) +/* DPORT_ROM_MPU_TABLE1 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_ROM_MPU_TABLE1 0x00000003 +#define DPORT_ROM_MPU_TABLE1_M ((DPORT_ROM_MPU_TABLE1_V)<<(DPORT_ROM_MPU_TABLE1_S)) +#define DPORT_ROM_MPU_TABLE1_V 0x3 +#define DPORT_ROM_MPU_TABLE1_S 0 + +#define DPORT_ROM_MPU_TABLE2_REG (DR_REG_DPORT_BASE + 0x49C) +/* DPORT_ROM_MPU_TABLE2 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_ROM_MPU_TABLE2 0x00000003 +#define DPORT_ROM_MPU_TABLE2_M ((DPORT_ROM_MPU_TABLE2_V)<<(DPORT_ROM_MPU_TABLE2_S)) +#define DPORT_ROM_MPU_TABLE2_V 0x3 +#define DPORT_ROM_MPU_TABLE2_S 0 + +#define DPORT_ROM_MPU_TABLE3_REG (DR_REG_DPORT_BASE + 0x4A0) +/* DPORT_ROM_MPU_TABLE3 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_ROM_MPU_TABLE3 0x00000003 +#define DPORT_ROM_MPU_TABLE3_M ((DPORT_ROM_MPU_TABLE3_V)<<(DPORT_ROM_MPU_TABLE3_S)) +#define DPORT_ROM_MPU_TABLE3_V 0x3 +#define DPORT_ROM_MPU_TABLE3_S 0 + +#define DPORT_SHROM_MPU_TABLE0_REG (DR_REG_DPORT_BASE + 0x4A4) +/* DPORT_SHROM_MPU_TABLE0 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE0 0x00000003 +#define DPORT_SHROM_MPU_TABLE0_M ((DPORT_SHROM_MPU_TABLE0_V)<<(DPORT_SHROM_MPU_TABLE0_S)) +#define DPORT_SHROM_MPU_TABLE0_V 0x3 +#define DPORT_SHROM_MPU_TABLE0_S 0 + +#define DPORT_SHROM_MPU_TABLE1_REG (DR_REG_DPORT_BASE + 0x4A8) +/* DPORT_SHROM_MPU_TABLE1 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE1 0x00000003 +#define DPORT_SHROM_MPU_TABLE1_M ((DPORT_SHROM_MPU_TABLE1_V)<<(DPORT_SHROM_MPU_TABLE1_S)) +#define DPORT_SHROM_MPU_TABLE1_V 0x3 +#define DPORT_SHROM_MPU_TABLE1_S 0 + +#define DPORT_SHROM_MPU_TABLE2_REG (DR_REG_DPORT_BASE + 0x4AC) +/* DPORT_SHROM_MPU_TABLE2 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE2 0x00000003 +#define DPORT_SHROM_MPU_TABLE2_M ((DPORT_SHROM_MPU_TABLE2_V)<<(DPORT_SHROM_MPU_TABLE2_S)) +#define DPORT_SHROM_MPU_TABLE2_V 0x3 +#define DPORT_SHROM_MPU_TABLE2_S 0 + +#define DPORT_SHROM_MPU_TABLE3_REG (DR_REG_DPORT_BASE + 0x4B0) +/* DPORT_SHROM_MPU_TABLE3 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE3 0x00000003 +#define DPORT_SHROM_MPU_TABLE3_M ((DPORT_SHROM_MPU_TABLE3_V)<<(DPORT_SHROM_MPU_TABLE3_S)) +#define DPORT_SHROM_MPU_TABLE3_V 0x3 +#define DPORT_SHROM_MPU_TABLE3_S 0 + +#define DPORT_SHROM_MPU_TABLE4_REG (DR_REG_DPORT_BASE + 0x4B4) +/* DPORT_SHROM_MPU_TABLE4 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE4 0x00000003 +#define DPORT_SHROM_MPU_TABLE4_M ((DPORT_SHROM_MPU_TABLE4_V)<<(DPORT_SHROM_MPU_TABLE4_S)) +#define DPORT_SHROM_MPU_TABLE4_V 0x3 +#define DPORT_SHROM_MPU_TABLE4_S 0 + +#define DPORT_SHROM_MPU_TABLE5_REG (DR_REG_DPORT_BASE + 0x4B8) +/* DPORT_SHROM_MPU_TABLE5 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE5 0x00000003 +#define DPORT_SHROM_MPU_TABLE5_M ((DPORT_SHROM_MPU_TABLE5_V)<<(DPORT_SHROM_MPU_TABLE5_S)) +#define DPORT_SHROM_MPU_TABLE5_V 0x3 +#define DPORT_SHROM_MPU_TABLE5_S 0 + +#define DPORT_SHROM_MPU_TABLE6_REG (DR_REG_DPORT_BASE + 0x4BC) +/* DPORT_SHROM_MPU_TABLE6 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE6 0x00000003 +#define DPORT_SHROM_MPU_TABLE6_M ((DPORT_SHROM_MPU_TABLE6_V)<<(DPORT_SHROM_MPU_TABLE6_S)) +#define DPORT_SHROM_MPU_TABLE6_V 0x3 +#define DPORT_SHROM_MPU_TABLE6_S 0 + +#define DPORT_SHROM_MPU_TABLE7_REG (DR_REG_DPORT_BASE + 0x4C0) +/* DPORT_SHROM_MPU_TABLE7 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE7 0x00000003 +#define DPORT_SHROM_MPU_TABLE7_M ((DPORT_SHROM_MPU_TABLE7_V)<<(DPORT_SHROM_MPU_TABLE7_S)) +#define DPORT_SHROM_MPU_TABLE7_V 0x3 +#define DPORT_SHROM_MPU_TABLE7_S 0 + +#define DPORT_SHROM_MPU_TABLE8_REG (DR_REG_DPORT_BASE + 0x4C4) +/* DPORT_SHROM_MPU_TABLE8 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE8 0x00000003 +#define DPORT_SHROM_MPU_TABLE8_M ((DPORT_SHROM_MPU_TABLE8_V)<<(DPORT_SHROM_MPU_TABLE8_S)) +#define DPORT_SHROM_MPU_TABLE8_V 0x3 +#define DPORT_SHROM_MPU_TABLE8_S 0 + +#define DPORT_SHROM_MPU_TABLE9_REG (DR_REG_DPORT_BASE + 0x4C8) +/* DPORT_SHROM_MPU_TABLE9 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE9 0x00000003 +#define DPORT_SHROM_MPU_TABLE9_M ((DPORT_SHROM_MPU_TABLE9_V)<<(DPORT_SHROM_MPU_TABLE9_S)) +#define DPORT_SHROM_MPU_TABLE9_V 0x3 +#define DPORT_SHROM_MPU_TABLE9_S 0 + +#define DPORT_SHROM_MPU_TABLE10_REG (DR_REG_DPORT_BASE + 0x4CC) +/* DPORT_SHROM_MPU_TABLE10 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE10 0x00000003 +#define DPORT_SHROM_MPU_TABLE10_M ((DPORT_SHROM_MPU_TABLE10_V)<<(DPORT_SHROM_MPU_TABLE10_S)) +#define DPORT_SHROM_MPU_TABLE10_V 0x3 +#define DPORT_SHROM_MPU_TABLE10_S 0 + +#define DPORT_SHROM_MPU_TABLE11_REG (DR_REG_DPORT_BASE + 0x4D0) +/* DPORT_SHROM_MPU_TABLE11 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE11 0x00000003 +#define DPORT_SHROM_MPU_TABLE11_M ((DPORT_SHROM_MPU_TABLE11_V)<<(DPORT_SHROM_MPU_TABLE11_S)) +#define DPORT_SHROM_MPU_TABLE11_V 0x3 +#define DPORT_SHROM_MPU_TABLE11_S 0 + +#define DPORT_SHROM_MPU_TABLE12_REG (DR_REG_DPORT_BASE + 0x4D4) +/* DPORT_SHROM_MPU_TABLE12 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE12 0x00000003 +#define DPORT_SHROM_MPU_TABLE12_M ((DPORT_SHROM_MPU_TABLE12_V)<<(DPORT_SHROM_MPU_TABLE12_S)) +#define DPORT_SHROM_MPU_TABLE12_V 0x3 +#define DPORT_SHROM_MPU_TABLE12_S 0 + +#define DPORT_SHROM_MPU_TABLE13_REG (DR_REG_DPORT_BASE + 0x4D8) +/* DPORT_SHROM_MPU_TABLE13 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE13 0x00000003 +#define DPORT_SHROM_MPU_TABLE13_M ((DPORT_SHROM_MPU_TABLE13_V)<<(DPORT_SHROM_MPU_TABLE13_S)) +#define DPORT_SHROM_MPU_TABLE13_V 0x3 +#define DPORT_SHROM_MPU_TABLE13_S 0 + +#define DPORT_SHROM_MPU_TABLE14_REG (DR_REG_DPORT_BASE + 0x4DC) +/* DPORT_SHROM_MPU_TABLE14 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE14 0x00000003 +#define DPORT_SHROM_MPU_TABLE14_M ((DPORT_SHROM_MPU_TABLE14_V)<<(DPORT_SHROM_MPU_TABLE14_S)) +#define DPORT_SHROM_MPU_TABLE14_V 0x3 +#define DPORT_SHROM_MPU_TABLE14_S 0 + +#define DPORT_SHROM_MPU_TABLE15_REG (DR_REG_DPORT_BASE + 0x4E0) +/* DPORT_SHROM_MPU_TABLE15 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE15 0x00000003 +#define DPORT_SHROM_MPU_TABLE15_M ((DPORT_SHROM_MPU_TABLE15_V)<<(DPORT_SHROM_MPU_TABLE15_S)) +#define DPORT_SHROM_MPU_TABLE15_V 0x3 +#define DPORT_SHROM_MPU_TABLE15_S 0 + +#define DPORT_SHROM_MPU_TABLE16_REG (DR_REG_DPORT_BASE + 0x4E4) +/* DPORT_SHROM_MPU_TABLE16 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE16 0x00000003 +#define DPORT_SHROM_MPU_TABLE16_M ((DPORT_SHROM_MPU_TABLE16_V)<<(DPORT_SHROM_MPU_TABLE16_S)) +#define DPORT_SHROM_MPU_TABLE16_V 0x3 +#define DPORT_SHROM_MPU_TABLE16_S 0 + +#define DPORT_SHROM_MPU_TABLE17_REG (DR_REG_DPORT_BASE + 0x4E8) +/* DPORT_SHROM_MPU_TABLE17 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE17 0x00000003 +#define DPORT_SHROM_MPU_TABLE17_M ((DPORT_SHROM_MPU_TABLE17_V)<<(DPORT_SHROM_MPU_TABLE17_S)) +#define DPORT_SHROM_MPU_TABLE17_V 0x3 +#define DPORT_SHROM_MPU_TABLE17_S 0 + +#define DPORT_SHROM_MPU_TABLE18_REG (DR_REG_DPORT_BASE + 0x4EC) +/* DPORT_SHROM_MPU_TABLE18 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE18 0x00000003 +#define DPORT_SHROM_MPU_TABLE18_M ((DPORT_SHROM_MPU_TABLE18_V)<<(DPORT_SHROM_MPU_TABLE18_S)) +#define DPORT_SHROM_MPU_TABLE18_V 0x3 +#define DPORT_SHROM_MPU_TABLE18_S 0 + +#define DPORT_SHROM_MPU_TABLE19_REG (DR_REG_DPORT_BASE + 0x4F0) +/* DPORT_SHROM_MPU_TABLE19 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE19 0x00000003 +#define DPORT_SHROM_MPU_TABLE19_M ((DPORT_SHROM_MPU_TABLE19_V)<<(DPORT_SHROM_MPU_TABLE19_S)) +#define DPORT_SHROM_MPU_TABLE19_V 0x3 +#define DPORT_SHROM_MPU_TABLE19_S 0 + +#define DPORT_SHROM_MPU_TABLE20_REG (DR_REG_DPORT_BASE + 0x4F4) +/* DPORT_SHROM_MPU_TABLE20 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE20 0x00000003 +#define DPORT_SHROM_MPU_TABLE20_M ((DPORT_SHROM_MPU_TABLE20_V)<<(DPORT_SHROM_MPU_TABLE20_S)) +#define DPORT_SHROM_MPU_TABLE20_V 0x3 +#define DPORT_SHROM_MPU_TABLE20_S 0 + +#define DPORT_SHROM_MPU_TABLE21_REG (DR_REG_DPORT_BASE + 0x4F8) +/* DPORT_SHROM_MPU_TABLE21 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE21 0x00000003 +#define DPORT_SHROM_MPU_TABLE21_M ((DPORT_SHROM_MPU_TABLE21_V)<<(DPORT_SHROM_MPU_TABLE21_S)) +#define DPORT_SHROM_MPU_TABLE21_V 0x3 +#define DPORT_SHROM_MPU_TABLE21_S 0 + +#define DPORT_SHROM_MPU_TABLE22_REG (DR_REG_DPORT_BASE + 0x4FC) +/* DPORT_SHROM_MPU_TABLE22 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE22 0x00000003 +#define DPORT_SHROM_MPU_TABLE22_M ((DPORT_SHROM_MPU_TABLE22_V)<<(DPORT_SHROM_MPU_TABLE22_S)) +#define DPORT_SHROM_MPU_TABLE22_V 0x3 +#define DPORT_SHROM_MPU_TABLE22_S 0 + +#define DPORT_SHROM_MPU_TABLE23_REG (DR_REG_DPORT_BASE + 0x500) +/* DPORT_SHROM_MPU_TABLE23 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ +/* Description: */ +#define DPORT_SHROM_MPU_TABLE23 0x00000003 +#define DPORT_SHROM_MPU_TABLE23_M ((DPORT_SHROM_MPU_TABLE23_V)<<(DPORT_SHROM_MPU_TABLE23_S)) +#define DPORT_SHROM_MPU_TABLE23_V 0x3 +#define DPORT_SHROM_MPU_TABLE23_S 0 + +#define DPORT_IMMU_TABLE0_REG (DR_REG_DPORT_BASE + 0x504) +/* DPORT_IMMU_TABLE0 : R/W ;bitpos:[6:0] ;default: 7'd0 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE0 0x0000007F +#define DPORT_IMMU_TABLE0_M ((DPORT_IMMU_TABLE0_V)<<(DPORT_IMMU_TABLE0_S)) +#define DPORT_IMMU_TABLE0_V 0x7F +#define DPORT_IMMU_TABLE0_S 0 + +#define DPORT_IMMU_TABLE1_REG (DR_REG_DPORT_BASE + 0x508) +/* DPORT_IMMU_TABLE1 : R/W ;bitpos:[6:0] ;default: 7'd1 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE1 0x0000007F +#define DPORT_IMMU_TABLE1_M ((DPORT_IMMU_TABLE1_V)<<(DPORT_IMMU_TABLE1_S)) +#define DPORT_IMMU_TABLE1_V 0x7F +#define DPORT_IMMU_TABLE1_S 0 + +#define DPORT_IMMU_TABLE2_REG (DR_REG_DPORT_BASE + 0x50C) +/* DPORT_IMMU_TABLE2 : R/W ;bitpos:[6:0] ;default: 7'd2 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE2 0x0000007F +#define DPORT_IMMU_TABLE2_M ((DPORT_IMMU_TABLE2_V)<<(DPORT_IMMU_TABLE2_S)) +#define DPORT_IMMU_TABLE2_V 0x7F +#define DPORT_IMMU_TABLE2_S 0 + +#define DPORT_IMMU_TABLE3_REG (DR_REG_DPORT_BASE + 0x510) +/* DPORT_IMMU_TABLE3 : R/W ;bitpos:[6:0] ;default: 7'd3 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE3 0x0000007F +#define DPORT_IMMU_TABLE3_M ((DPORT_IMMU_TABLE3_V)<<(DPORT_IMMU_TABLE3_S)) +#define DPORT_IMMU_TABLE3_V 0x7F +#define DPORT_IMMU_TABLE3_S 0 + +#define DPORT_IMMU_TABLE4_REG (DR_REG_DPORT_BASE + 0x514) +/* DPORT_IMMU_TABLE4 : R/W ;bitpos:[6:0] ;default: 7'd4 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE4 0x0000007F +#define DPORT_IMMU_TABLE4_M ((DPORT_IMMU_TABLE4_V)<<(DPORT_IMMU_TABLE4_S)) +#define DPORT_IMMU_TABLE4_V 0x7F +#define DPORT_IMMU_TABLE4_S 0 + +#define DPORT_IMMU_TABLE5_REG (DR_REG_DPORT_BASE + 0x518) +/* DPORT_IMMU_TABLE5 : R/W ;bitpos:[6:0] ;default: 7'd5 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE5 0x0000007F +#define DPORT_IMMU_TABLE5_M ((DPORT_IMMU_TABLE5_V)<<(DPORT_IMMU_TABLE5_S)) +#define DPORT_IMMU_TABLE5_V 0x7F +#define DPORT_IMMU_TABLE5_S 0 + +#define DPORT_IMMU_TABLE6_REG (DR_REG_DPORT_BASE + 0x51C) +/* DPORT_IMMU_TABLE6 : R/W ;bitpos:[6:0] ;default: 7'd6 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE6 0x0000007F +#define DPORT_IMMU_TABLE6_M ((DPORT_IMMU_TABLE6_V)<<(DPORT_IMMU_TABLE6_S)) +#define DPORT_IMMU_TABLE6_V 0x7F +#define DPORT_IMMU_TABLE6_S 0 + +#define DPORT_IMMU_TABLE7_REG (DR_REG_DPORT_BASE + 0x520) +/* DPORT_IMMU_TABLE7 : R/W ;bitpos:[6:0] ;default: 7'd7 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE7 0x0000007F +#define DPORT_IMMU_TABLE7_M ((DPORT_IMMU_TABLE7_V)<<(DPORT_IMMU_TABLE7_S)) +#define DPORT_IMMU_TABLE7_V 0x7F +#define DPORT_IMMU_TABLE7_S 0 + +#define DPORT_IMMU_TABLE8_REG (DR_REG_DPORT_BASE + 0x524) +/* DPORT_IMMU_TABLE8 : R/W ;bitpos:[6:0] ;default: 7'd8 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE8 0x0000007F +#define DPORT_IMMU_TABLE8_M ((DPORT_IMMU_TABLE8_V)<<(DPORT_IMMU_TABLE8_S)) +#define DPORT_IMMU_TABLE8_V 0x7F +#define DPORT_IMMU_TABLE8_S 0 + +#define DPORT_IMMU_TABLE9_REG (DR_REG_DPORT_BASE + 0x528) +/* DPORT_IMMU_TABLE9 : R/W ;bitpos:[6:0] ;default: 7'd9 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE9 0x0000007F +#define DPORT_IMMU_TABLE9_M ((DPORT_IMMU_TABLE9_V)<<(DPORT_IMMU_TABLE9_S)) +#define DPORT_IMMU_TABLE9_V 0x7F +#define DPORT_IMMU_TABLE9_S 0 + +#define DPORT_IMMU_TABLE10_REG (DR_REG_DPORT_BASE + 0x52C) +/* DPORT_IMMU_TABLE10 : R/W ;bitpos:[6:0] ;default: 7'd10 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE10 0x0000007F +#define DPORT_IMMU_TABLE10_M ((DPORT_IMMU_TABLE10_V)<<(DPORT_IMMU_TABLE10_S)) +#define DPORT_IMMU_TABLE10_V 0x7F +#define DPORT_IMMU_TABLE10_S 0 + +#define DPORT_IMMU_TABLE11_REG (DR_REG_DPORT_BASE + 0x530) +/* DPORT_IMMU_TABLE11 : R/W ;bitpos:[6:0] ;default: 7'd11 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE11 0x0000007F +#define DPORT_IMMU_TABLE11_M ((DPORT_IMMU_TABLE11_V)<<(DPORT_IMMU_TABLE11_S)) +#define DPORT_IMMU_TABLE11_V 0x7F +#define DPORT_IMMU_TABLE11_S 0 + +#define DPORT_IMMU_TABLE12_REG (DR_REG_DPORT_BASE + 0x534) +/* DPORT_IMMU_TABLE12 : R/W ;bitpos:[6:0] ;default: 7'd12 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE12 0x0000007F +#define DPORT_IMMU_TABLE12_M ((DPORT_IMMU_TABLE12_V)<<(DPORT_IMMU_TABLE12_S)) +#define DPORT_IMMU_TABLE12_V 0x7F +#define DPORT_IMMU_TABLE12_S 0 + +#define DPORT_IMMU_TABLE13_REG (DR_REG_DPORT_BASE + 0x538) +/* DPORT_IMMU_TABLE13 : R/W ;bitpos:[6:0] ;default: 7'd13 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE13 0x0000007F +#define DPORT_IMMU_TABLE13_M ((DPORT_IMMU_TABLE13_V)<<(DPORT_IMMU_TABLE13_S)) +#define DPORT_IMMU_TABLE13_V 0x7F +#define DPORT_IMMU_TABLE13_S 0 + +#define DPORT_IMMU_TABLE14_REG (DR_REG_DPORT_BASE + 0x53C) +/* DPORT_IMMU_TABLE14 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE14 0x0000007F +#define DPORT_IMMU_TABLE14_M ((DPORT_IMMU_TABLE14_V)<<(DPORT_IMMU_TABLE14_S)) +#define DPORT_IMMU_TABLE14_V 0x7F +#define DPORT_IMMU_TABLE14_S 0 + +#define DPORT_IMMU_TABLE15_REG (DR_REG_DPORT_BASE + 0x540) +/* DPORT_IMMU_TABLE15 : R/W ;bitpos:[6:0] ;default: 7'd15 ; */ +/* Description: */ +#define DPORT_IMMU_TABLE15 0x0000007F +#define DPORT_IMMU_TABLE15_M ((DPORT_IMMU_TABLE15_V)<<(DPORT_IMMU_TABLE15_S)) +#define DPORT_IMMU_TABLE15_V 0x7F +#define DPORT_IMMU_TABLE15_S 0 + +#define DPORT_DMMU_TABLE0_REG (DR_REG_DPORT_BASE + 0x544) +/* DPORT_DMMU_TABLE0 : R/W ;bitpos:[6:0] ;default: 7'd0 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE0 0x0000007F +#define DPORT_DMMU_TABLE0_M ((DPORT_DMMU_TABLE0_V)<<(DPORT_DMMU_TABLE0_S)) +#define DPORT_DMMU_TABLE0_V 0x7F +#define DPORT_DMMU_TABLE0_S 0 + +#define DPORT_DMMU_TABLE1_REG (DR_REG_DPORT_BASE + 0x548) +/* DPORT_DMMU_TABLE1 : R/W ;bitpos:[6:0] ;default: 7'd1 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE1 0x0000007F +#define DPORT_DMMU_TABLE1_M ((DPORT_DMMU_TABLE1_V)<<(DPORT_DMMU_TABLE1_S)) +#define DPORT_DMMU_TABLE1_V 0x7F +#define DPORT_DMMU_TABLE1_S 0 + +#define DPORT_DMMU_TABLE2_REG (DR_REG_DPORT_BASE + 0x54C) +/* DPORT_DMMU_TABLE2 : R/W ;bitpos:[6:0] ;default: 7'd2 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE2 0x0000007F +#define DPORT_DMMU_TABLE2_M ((DPORT_DMMU_TABLE2_V)<<(DPORT_DMMU_TABLE2_S)) +#define DPORT_DMMU_TABLE2_V 0x7F +#define DPORT_DMMU_TABLE2_S 0 + +#define DPORT_DMMU_TABLE3_REG (DR_REG_DPORT_BASE + 0x550) +/* DPORT_DMMU_TABLE3 : R/W ;bitpos:[6:0] ;default: 7'd3 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE3 0x0000007F +#define DPORT_DMMU_TABLE3_M ((DPORT_DMMU_TABLE3_V)<<(DPORT_DMMU_TABLE3_S)) +#define DPORT_DMMU_TABLE3_V 0x7F +#define DPORT_DMMU_TABLE3_S 0 + +#define DPORT_DMMU_TABLE4_REG (DR_REG_DPORT_BASE + 0x554) +/* DPORT_DMMU_TABLE4 : R/W ;bitpos:[6:0] ;default: 7'd4 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE4 0x0000007F +#define DPORT_DMMU_TABLE4_M ((DPORT_DMMU_TABLE4_V)<<(DPORT_DMMU_TABLE4_S)) +#define DPORT_DMMU_TABLE4_V 0x7F +#define DPORT_DMMU_TABLE4_S 0 + +#define DPORT_DMMU_TABLE5_REG (DR_REG_DPORT_BASE + 0x558) +/* DPORT_DMMU_TABLE5 : R/W ;bitpos:[6:0] ;default: 7'd5 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE5 0x0000007F +#define DPORT_DMMU_TABLE5_M ((DPORT_DMMU_TABLE5_V)<<(DPORT_DMMU_TABLE5_S)) +#define DPORT_DMMU_TABLE5_V 0x7F +#define DPORT_DMMU_TABLE5_S 0 + +#define DPORT_DMMU_TABLE6_REG (DR_REG_DPORT_BASE + 0x55C) +/* DPORT_DMMU_TABLE6 : R/W ;bitpos:[6:0] ;default: 7'd6 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE6 0x0000007F +#define DPORT_DMMU_TABLE6_M ((DPORT_DMMU_TABLE6_V)<<(DPORT_DMMU_TABLE6_S)) +#define DPORT_DMMU_TABLE6_V 0x7F +#define DPORT_DMMU_TABLE6_S 0 + +#define DPORT_DMMU_TABLE7_REG (DR_REG_DPORT_BASE + 0x560) +/* DPORT_DMMU_TABLE7 : R/W ;bitpos:[6:0] ;default: 7'd7 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE7 0x0000007F +#define DPORT_DMMU_TABLE7_M ((DPORT_DMMU_TABLE7_V)<<(DPORT_DMMU_TABLE7_S)) +#define DPORT_DMMU_TABLE7_V 0x7F +#define DPORT_DMMU_TABLE7_S 0 + +#define DPORT_DMMU_TABLE8_REG (DR_REG_DPORT_BASE + 0x564) +/* DPORT_DMMU_TABLE8 : R/W ;bitpos:[6:0] ;default: 7'd8 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE8 0x0000007F +#define DPORT_DMMU_TABLE8_M ((DPORT_DMMU_TABLE8_V)<<(DPORT_DMMU_TABLE8_S)) +#define DPORT_DMMU_TABLE8_V 0x7F +#define DPORT_DMMU_TABLE8_S 0 + +#define DPORT_DMMU_TABLE9_REG (DR_REG_DPORT_BASE + 0x568) +/* DPORT_DMMU_TABLE9 : R/W ;bitpos:[6:0] ;default: 7'd9 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE9 0x0000007F +#define DPORT_DMMU_TABLE9_M ((DPORT_DMMU_TABLE9_V)<<(DPORT_DMMU_TABLE9_S)) +#define DPORT_DMMU_TABLE9_V 0x7F +#define DPORT_DMMU_TABLE9_S 0 + +#define DPORT_DMMU_TABLE10_REG (DR_REG_DPORT_BASE + 0x56C) +/* DPORT_DMMU_TABLE10 : R/W ;bitpos:[6:0] ;default: 7'd10 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE10 0x0000007F +#define DPORT_DMMU_TABLE10_M ((DPORT_DMMU_TABLE10_V)<<(DPORT_DMMU_TABLE10_S)) +#define DPORT_DMMU_TABLE10_V 0x7F +#define DPORT_DMMU_TABLE10_S 0 + +#define DPORT_DMMU_TABLE11_REG (DR_REG_DPORT_BASE + 0x570) +/* DPORT_DMMU_TABLE11 : R/W ;bitpos:[6:0] ;default: 7'd11 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE11 0x0000007F +#define DPORT_DMMU_TABLE11_M ((DPORT_DMMU_TABLE11_V)<<(DPORT_DMMU_TABLE11_S)) +#define DPORT_DMMU_TABLE11_V 0x7F +#define DPORT_DMMU_TABLE11_S 0 + +#define DPORT_DMMU_TABLE12_REG (DR_REG_DPORT_BASE + 0x574) +/* DPORT_DMMU_TABLE12 : R/W ;bitpos:[6:0] ;default: 7'd12 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE12 0x0000007F +#define DPORT_DMMU_TABLE12_M ((DPORT_DMMU_TABLE12_V)<<(DPORT_DMMU_TABLE12_S)) +#define DPORT_DMMU_TABLE12_V 0x7F +#define DPORT_DMMU_TABLE12_S 0 + +#define DPORT_DMMU_TABLE13_REG (DR_REG_DPORT_BASE + 0x578) +/* DPORT_DMMU_TABLE13 : R/W ;bitpos:[6:0] ;default: 7'd13 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE13 0x0000007F +#define DPORT_DMMU_TABLE13_M ((DPORT_DMMU_TABLE13_V)<<(DPORT_DMMU_TABLE13_S)) +#define DPORT_DMMU_TABLE13_V 0x7F +#define DPORT_DMMU_TABLE13_S 0 + +#define DPORT_DMMU_TABLE14_REG (DR_REG_DPORT_BASE + 0x57C) +/* DPORT_DMMU_TABLE14 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE14 0x0000007F +#define DPORT_DMMU_TABLE14_M ((DPORT_DMMU_TABLE14_V)<<(DPORT_DMMU_TABLE14_S)) +#define DPORT_DMMU_TABLE14_V 0x7F +#define DPORT_DMMU_TABLE14_S 0 + +#define DPORT_DMMU_TABLE15_REG (DR_REG_DPORT_BASE + 0x580) +/* DPORT_DMMU_TABLE15 : R/W ;bitpos:[6:0] ;default: 7'd15 ; */ +/* Description: */ +#define DPORT_DMMU_TABLE15 0x0000007F +#define DPORT_DMMU_TABLE15_M ((DPORT_DMMU_TABLE15_V)<<(DPORT_DMMU_TABLE15_S)) +#define DPORT_DMMU_TABLE15_V 0x7F +#define DPORT_DMMU_TABLE15_S 0 + +#define DPORT_PRO_INTRUSION_CTRL_REG (DR_REG_DPORT_BASE + 0x584) +/* DPORT_PRO_INTRUSION_RECORD_RESET_N : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PRO_INTRUSION_RECORD_RESET_N (BIT(0)) +#define DPORT_PRO_INTRUSION_RECORD_RESET_N_M (BIT(0)) +#define DPORT_PRO_INTRUSION_RECORD_RESET_N_V 0x1 +#define DPORT_PRO_INTRUSION_RECORD_RESET_N_S 0 + +#define DPORT_PRO_INTRUSION_STATUS_REG (DR_REG_DPORT_BASE + 0x588) +/* DPORT_PRO_INTRUSION_RECORD : RO ;bitpos:[3:0] ;default: 4'b0 ; */ +/* Description: */ +#define DPORT_PRO_INTRUSION_RECORD 0x0000000F +#define DPORT_PRO_INTRUSION_RECORD_M ((DPORT_PRO_INTRUSION_RECORD_V)<<(DPORT_PRO_INTRUSION_RECORD_S)) +#define DPORT_PRO_INTRUSION_RECORD_V 0xF +#define DPORT_PRO_INTRUSION_RECORD_S 0 + +#define DPORT_APP_INTRUSION_CTRL_REG (DR_REG_DPORT_BASE + 0x58C) +/* DPORT_APP_INTRUSION_RECORD_RESET_N : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_APP_INTRUSION_RECORD_RESET_N (BIT(0)) +#define DPORT_APP_INTRUSION_RECORD_RESET_N_M (BIT(0)) +#define DPORT_APP_INTRUSION_RECORD_RESET_N_V 0x1 +#define DPORT_APP_INTRUSION_RECORD_RESET_N_S 0 + +#define DPORT_APP_INTRUSION_STATUS_REG (DR_REG_DPORT_BASE + 0x590) +/* DPORT_APP_INTRUSION_RECORD : RO ;bitpos:[3:0] ;default: 4'b0 ; */ +/* Description: */ +#define DPORT_APP_INTRUSION_RECORD 0x0000000F +#define DPORT_APP_INTRUSION_RECORD_M ((DPORT_APP_INTRUSION_RECORD_V)<<(DPORT_APP_INTRUSION_RECORD_S)) +#define DPORT_APP_INTRUSION_RECORD_V 0xF +#define DPORT_APP_INTRUSION_RECORD_S 0 + +#define DPORT_FRONT_END_MEM_PD_REG (DR_REG_DPORT_BASE + 0x594) +/* DPORT_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_PBUS_MEM_FORCE_PD (BIT(3)) +#define DPORT_PBUS_MEM_FORCE_PD_M (BIT(3)) +#define DPORT_PBUS_MEM_FORCE_PD_V 0x1 +#define DPORT_PBUS_MEM_FORCE_PD_S 3 +/* DPORT_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_PBUS_MEM_FORCE_PU (BIT(2)) +#define DPORT_PBUS_MEM_FORCE_PU_M (BIT(2)) +#define DPORT_PBUS_MEM_FORCE_PU_V 0x1 +#define DPORT_PBUS_MEM_FORCE_PU_S 2 +/* DPORT_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_AGC_MEM_FORCE_PD (BIT(1)) +#define DPORT_AGC_MEM_FORCE_PD_M (BIT(1)) +#define DPORT_AGC_MEM_FORCE_PD_V 0x1 +#define DPORT_AGC_MEM_FORCE_PD_S 1 +/* DPORT_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/* Description: */ +#define DPORT_AGC_MEM_FORCE_PU (BIT(0)) +#define DPORT_AGC_MEM_FORCE_PU_M (BIT(0)) +#define DPORT_AGC_MEM_FORCE_PU_V 0x1 +#define DPORT_AGC_MEM_FORCE_PU_S 0 + +#define DPORT_MMU_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x598) +/* DPORT_MMU_IA_INT_EN : R/W ;bitpos:[23:0] ;default: 24'b0 ; */ +/* Description: */ +#define DPORT_MMU_IA_INT_EN 0x00FFFFFF +#define DPORT_MMU_IA_INT_EN_M ((DPORT_MMU_IA_INT_EN_V)<<(DPORT_MMU_IA_INT_EN_S)) +#define DPORT_MMU_IA_INT_EN_V 0xFFFFFF +#define DPORT_MMU_IA_INT_EN_S 0 + +#define DPORT_MPU_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x59C) +/* DPORT_MPU_IA_INT_EN : R/W ;bitpos:[16:0] ;default: 17'b0 ; */ +/* Description: */ +#define DPORT_MPU_IA_INT_EN 0x0001FFFF +#define DPORT_MPU_IA_INT_EN_M ((DPORT_MPU_IA_INT_EN_V)<<(DPORT_MPU_IA_INT_EN_S)) +#define DPORT_MPU_IA_INT_EN_V 0x1FFFF +#define DPORT_MPU_IA_INT_EN_S 0 + +#define DPORT_CACHE_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x5A0) +/* DPORT_CACHE_IA_INT_EN : R/W ;bitpos:[27:0] ;default: 28'b0 ; */ +/* Description: */ +#define DPORT_CACHE_IA_INT_EN 0x0FFFFFFF +#define DPORT_CACHE_IA_INT_EN_M ((DPORT_CACHE_IA_INT_EN_V)<<(DPORT_CACHE_IA_INT_EN_S)) +#define DPORT_CACHE_IA_INT_EN_V 0xFFFFFFF +#define DPORT_CACHE_IA_INT_EN_S 0 + +#define DPORT_SECURE_BOOT_CTRL_REG (DR_REG_DPORT_BASE + 0x5A4) +/* DPORT_SW_BOOTLOADER_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: */ +#define DPORT_SW_BOOTLOADER_SEL (BIT(0)) +#define DPORT_SW_BOOTLOADER_SEL_M (BIT(0)) +#define DPORT_SW_BOOTLOADER_SEL_V 0x1 +#define DPORT_SW_BOOTLOADER_SEL_S 0 + +#define DPORT_SPI_DMA_CHAN_SEL_REG (DR_REG_DPORT_BASE + 0x5A8) +/* DPORT_SPI3_DMA_CHAN_SEL : R/W ;bitpos:[5:4] ;default: 2'b00 ; */ +/* Description: */ +#define DPORT_SPI3_DMA_CHAN_SEL 0x00000003 +#define DPORT_SPI3_DMA_CHAN_SEL_M ((DPORT_SPI3_DMA_CHAN_SEL_V)<<(DPORT_SPI3_DMA_CHAN_SEL_S)) +#define DPORT_SPI3_DMA_CHAN_SEL_V 0x3 +#define DPORT_SPI3_DMA_CHAN_SEL_S 4 +/* DPORT_SPI2_DMA_CHAN_SEL : R/W ;bitpos:[3:2] ;default: 2'b00 ; */ +/* Description: */ +#define DPORT_SPI2_DMA_CHAN_SEL 0x00000003 +#define DPORT_SPI2_DMA_CHAN_SEL_M ((DPORT_SPI2_DMA_CHAN_SEL_V)<<(DPORT_SPI2_DMA_CHAN_SEL_S)) +#define DPORT_SPI2_DMA_CHAN_SEL_V 0x3 +#define DPORT_SPI2_DMA_CHAN_SEL_S 2 +/* DPORT_SPI1_DMA_CHAN_SEL : R/W ;bitpos:[1:0] ;default: 2'b00 ; */ +/* Description: */ +#define DPORT_SPI1_DMA_CHAN_SEL 0x00000003 +#define DPORT_SPI1_DMA_CHAN_SEL_M ((DPORT_SPI1_DMA_CHAN_SEL_V)<<(DPORT_SPI1_DMA_CHAN_SEL_S)) +#define DPORT_SPI1_DMA_CHAN_SEL_V 0x3 +#define DPORT_SPI1_DMA_CHAN_SEL_S 0 + +#define DPORT_PRO_VECBASE_CTRL_REG (DR_REG_DPORT_BASE + 0x5AC) +/* DPORT_PRO_OUT_VECBASE_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_PRO_OUT_VECBASE_SEL 0x00000003 +#define DPORT_PRO_OUT_VECBASE_SEL_M ((DPORT_PRO_OUT_VECBASE_SEL_V)<<(DPORT_PRO_OUT_VECBASE_SEL_S)) +#define DPORT_PRO_OUT_VECBASE_SEL_V 0x3 +#define DPORT_PRO_OUT_VECBASE_SEL_S 0 + +#define DPORT_PRO_VECBASE_SET_REG (DR_REG_DPORT_BASE + 0x5B0) +/* DPORT_PRO_OUT_VECBASE_REG : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ +/* Description: */ +#define DPORT_PRO_OUT_VECBASE_REG 0x003FFFFF +#define DPORT_PRO_OUT_VECBASE_REG_M ((DPORT_PRO_OUT_VECBASE_REG_V)<<(DPORT_PRO_OUT_VECBASE_REG_S)) +#define DPORT_PRO_OUT_VECBASE_REG_V 0x3FFFFF +#define DPORT_PRO_OUT_VECBASE_REG_S 0 + +#define DPORT_APP_VECBASE_CTRL_REG (DR_REG_DPORT_BASE + 0x5B4) +/* DPORT_APP_OUT_VECBASE_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/* Description: */ +#define DPORT_APP_OUT_VECBASE_SEL 0x00000003 +#define DPORT_APP_OUT_VECBASE_SEL_M ((DPORT_APP_OUT_VECBASE_SEL_V)<<(DPORT_APP_OUT_VECBASE_SEL_S)) +#define DPORT_APP_OUT_VECBASE_SEL_V 0x3 +#define DPORT_APP_OUT_VECBASE_SEL_S 0 + +#define DPORT_APP_VECBASE_SET_REG (DR_REG_DPORT_BASE + 0x5B8) +/* DPORT_APP_OUT_VECBASE_REG : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ +/* Description: */ +#define DPORT_APP_OUT_VECBASE_REG 0x003FFFFF +#define DPORT_APP_OUT_VECBASE_REG_M ((DPORT_APP_OUT_VECBASE_REG_V)<<(DPORT_APP_OUT_VECBASE_REG_S)) +#define DPORT_APP_OUT_VECBASE_REG_V 0x3FFFFF +#define DPORT_APP_OUT_VECBASE_REG_S 0 + +#define DPORT_DATE_REG (DR_REG_DPORT_BASE + 0xFFC) +/* DPORT_DATE : R/W ;bitpos:[27:0] ;default: 28'h1605190 ; */ +/* Description: */ +#define DPORT_DATE 0x0FFFFFFF +#define DPORT_DATE_M ((DPORT_DATE_V)<<(DPORT_DATE_S)) +#define DPORT_DATE_V 0xFFFFFFF +#define DPORT_DATE_S 0 +#define DPORT_DPORT_DATE_VERSION 0x1605190 + +#endif /*__ARCH_XTENSA_SRC_ESP32_CHIP_XTENSA_DPORT_H */ diff --git a/arch/xtensa/src/esp32/chip/xtensa_rtccntl.h b/arch/xtensa/src/esp32/chip/xtensa_rtccntl.h new file mode 100644 index 0000000000..f79fa9aa88 --- /dev/null +++ b/arch/xtensa/src/esp32/chip/xtensa_rtccntl.h @@ -0,0 +1,2009 @@ +/**************************************************************************** + * arch/xtensa/src/common/esp32_rtccnt.h + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Espressif Systems: + * + * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_XTENSA_RTCCNTL_H +#define __ARCH_XTENSA_SRC_ESP32_CHIP_XTENSA_RTCCNTL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "chip/esp32_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) +/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */ +/*description: SW system reset*/ +#define RTC_CNTL_SW_SYS_RST (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_M (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_V 0x1 +#define RTC_CNTL_SW_SYS_RST_S 31 +/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: digital core force no reset in deep sleep*/ +#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 +/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: digital wrap force reset in deep sleep*/ +#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 +/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 +/* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_NOISO_S 27 +/* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_NOISO_S 26 +/* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_ISO_S 25 +/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_ISO_S 24 +/* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_ISO_S 23 +/* RTC_CNTL_BIAS_CORE_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */ +/*description: BIAS_CORE force power up*/ +#define RTC_CNTL_BIAS_CORE_FORCE_PU (BIT(22)) +#define RTC_CNTL_BIAS_CORE_FORCE_PU_M (BIT(22)) +#define RTC_CNTL_BIAS_CORE_FORCE_PU_V 0x1 +#define RTC_CNTL_BIAS_CORE_FORCE_PU_S 22 +/* RTC_CNTL_BIAS_CORE_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: BIAS_CORE force power down*/ +#define RTC_CNTL_BIAS_CORE_FORCE_PD (BIT(21)) +#define RTC_CNTL_BIAS_CORE_FORCE_PD_M (BIT(21)) +#define RTC_CNTL_BIAS_CORE_FORCE_PD_V 0x1 +#define RTC_CNTL_BIAS_CORE_FORCE_PD_S 21 +/* RTC_CNTL_BIAS_CORE_FOLW_8M : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: BIAS_CORE follow CK8M*/ +#define RTC_CNTL_BIAS_CORE_FOLW_8M (BIT(20)) +#define RTC_CNTL_BIAS_CORE_FOLW_8M_M (BIT(20)) +#define RTC_CNTL_BIAS_CORE_FOLW_8M_V 0x1 +#define RTC_CNTL_BIAS_CORE_FOLW_8M_S 20 +/* RTC_CNTL_BIAS_I2C_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd1 ; */ +/*description: BIAS_I2C force power up*/ +#define RTC_CNTL_BIAS_I2C_FORCE_PU (BIT(19)) +#define RTC_CNTL_BIAS_I2C_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_BIAS_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BIAS_I2C_FORCE_PU_S 19 +/* RTC_CNTL_BIAS_I2C_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: BIAS_I2C force power down*/ +#define RTC_CNTL_BIAS_I2C_FORCE_PD (BIT(18)) +#define RTC_CNTL_BIAS_I2C_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_BIAS_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BIAS_I2C_FORCE_PD_S 18 +/* RTC_CNTL_BIAS_I2C_FOLW_8M : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: BIAS_I2C follow CK8M*/ +#define RTC_CNTL_BIAS_I2C_FOLW_8M (BIT(17)) +#define RTC_CNTL_BIAS_I2C_FOLW_8M_M (BIT(17)) +#define RTC_CNTL_BIAS_I2C_FOLW_8M_V 0x1 +#define RTC_CNTL_BIAS_I2C_FOLW_8M_S 17 +/* RTC_CNTL_BIAS_FORCE_NOSLEEP : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: BIAS_SLEEP force no sleep*/ +#define RTC_CNTL_BIAS_FORCE_NOSLEEP (BIT(16)) +#define RTC_CNTL_BIAS_FORCE_NOSLEEP_M (BIT(16)) +#define RTC_CNTL_BIAS_FORCE_NOSLEEP_V 0x1 +#define RTC_CNTL_BIAS_FORCE_NOSLEEP_S 16 +/* RTC_CNTL_BIAS_FORCE_SLEEP : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: BIAS_SLEEP force sleep*/ +#define RTC_CNTL_BIAS_FORCE_SLEEP (BIT(15)) +#define RTC_CNTL_BIAS_FORCE_SLEEP_M (BIT(15)) +#define RTC_CNTL_BIAS_FORCE_SLEEP_V 0x1 +#define RTC_CNTL_BIAS_FORCE_SLEEP_S 15 +/* RTC_CNTL_BIAS_SLEEP_FOLW_8M : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: BIAS_SLEEP follow CK8M*/ +#define RTC_CNTL_BIAS_SLEEP_FOLW_8M (BIT(14)) +#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_M (BIT(14)) +#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_S 14 +/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ +/*description: crystall force power up*/ +#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_V 0x1 +#define RTC_CNTL_XTL_FORCE_PU_S 13 +/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: crystall force power down*/ +#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_V 0x1 +#define RTC_CNTL_XTL_FORCE_PD_S 12 +/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: BB_PLL force power up*/ +#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PU_S 11 +/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: BB_PLL force power down*/ +#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PD_S 10 +/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: BB_PLL_I2C force power up*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 +/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: BB_PLL _I2C force power down*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 +/* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: BB_I2C force power up*/ +#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PU_S 7 +/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: BB_I2C force power down*/ +#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PD_S 6 +/* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: PRO CPU SW reset*/ +#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_V 0x1 +#define RTC_CNTL_SW_PROCPU_RST_S 5 +/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: APP CPU SW reset*/ +#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_V 0x1 +#define RTC_CNTL_SW_APPCPU_RST_S 4 +/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == + 0x86 will stall PRO CPU*/ +#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 +/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == + 0x86 will stall APP CPU*/ +#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 + +#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) +/* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC sleep timer low 32 bits*/ +#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S)) +#define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_S 0 + +#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) +/* RTC_CNTL_MAIN_TIMER_ALARM_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: timer alarm enable bit*/ +#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 +/* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC sleep timer high 16 bits*/ +#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF +#define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S)) +#define RTC_CNTL_SLP_VAL_HI_V 0xFFFF +#define RTC_CNTL_SLP_VAL_HI_S 0 + +#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xc) +/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: Set 1: to update register with RTC timer*/ +#define RTC_CNTL_TIME_UPDATE (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_M (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_V 0x1 +#define RTC_CNTL_TIME_UPDATE_S 31 +/* RTC_CNTL_TIME_VALID : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: To indicate the register is updated*/ +#define RTC_CNTL_TIME_VALID (BIT(30)) +#define RTC_CNTL_TIME_VALID_M (BIT(30)) +#define RTC_CNTL_TIME_VALID_V 0x1 +#define RTC_CNTL_TIME_VALID_S 30 + +#define RTC_CNTL_TIME0_REG (DR_REG_RTCCNTL_BASE + 0x10) +/* RTC_CNTL_TIME_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC timer low 32 bits*/ +#define RTC_CNTL_TIME_LO 0xFFFFFFFF +#define RTC_CNTL_TIME_LO_M ((RTC_CNTL_TIME_LO_V)<<(RTC_CNTL_TIME_LO_S)) +#define RTC_CNTL_TIME_LO_V 0xFFFFFFFF +#define RTC_CNTL_TIME_LO_S 0 + +#define RTC_CNTL_TIME1_REG (DR_REG_RTCCNTL_BASE + 0x14) +/* RTC_CNTL_TIME_HI : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC timer high 16 bits*/ +#define RTC_CNTL_TIME_HI 0x0000FFFF +#define RTC_CNTL_TIME_HI_M ((RTC_CNTL_TIME_HI_V)<<(RTC_CNTL_TIME_HI_S)) +#define RTC_CNTL_TIME_HI_V 0xFFFF +#define RTC_CNTL_TIME_HI_S 0 + +#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) +/* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: sleep enable bit*/ +#define RTC_CNTL_SLEEP_EN (BIT(31)) +#define RTC_CNTL_SLEEP_EN_M (BIT(31)) +#define RTC_CNTL_SLEEP_EN_V 0x1 +#define RTC_CNTL_SLEEP_EN_S 31 +/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: sleep reject bit*/ +#define RTC_CNTL_SLP_REJECT (BIT(30)) +#define RTC_CNTL_SLP_REJECT_M (BIT(30)) +#define RTC_CNTL_SLP_REJECT_V 0x1 +#define RTC_CNTL_SLP_REJECT_S 30 +/* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: sleep wakeup bit*/ +#define RTC_CNTL_SLP_WAKEUP (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_S 29 +/* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */ +/*description: SDIO active indication*/ +#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 +#define RTC_CNTL_SDIO_ACTIVE_IND_S 28 +/* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: ULP-coprocessor timer enable bit*/ +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(24)) +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M (BIT(24)) +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V 0x1 +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S 24 +/* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: touch timer enable bit*/ +#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(23)) +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_M (BIT(23)) +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x1 +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 23 +/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: 1: APB to RTC using bridge 0: APB to RTC using sync*/ +#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 +/* RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: ULP-coprocessor force wake up*/ +#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN (BIT(21)) +#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_M (BIT(21)) +#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_V 0x1 +#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_S 21 +/* RTC_CNTL_TOUCH_WAKEUP_FORCE_EN : R/W ;bitpos:[20] ;default: 1'd1 ; */ +/*description: touch controller force wake up*/ +#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN (BIT(20)) +#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_M (BIT(20)) +#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_V 0x1 +#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_S 20 + +#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1c) +/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ +/*description: PLL wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF +#define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) +#define RTC_CNTL_PLL_BUF_WAIT_V 0xFF +#define RTC_CNTL_PLL_BUF_WAIT_S 24 +/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ +/*description: XTAL wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF +#define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) +#define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF +#define RTC_CNTL_XTL_BUF_WAIT_S 14 +/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ +/*description: CK8M wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_CK8M_WAIT 0x000000FF +#define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) +#define RTC_CNTL_CK8M_WAIT_V 0xFF +#define RTC_CNTL_CK8M_WAIT_S 6 +/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ +/*description: CPU stall wait cycles in fast_clk_rtc*/ +#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F +#define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S)) +#define RTC_CNTL_CPU_STALL_WAIT_V 0x1F +#define RTC_CNTL_CPU_STALL_WAIT_S 1 +/* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ +/*description: CPU stall enable bit*/ +#define RTC_CNTL_CPU_STALL_EN (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_V 0x1 +#define RTC_CNTL_CPU_STALL_EN_S 0 + +#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) +/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ +/*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/ +#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S)) +#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 +/* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W ;bitpos:[23:15] ;default: 9'h10 ; */ +/*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller + start to work*/ +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V)<<(RTC_CNTL_ULPCP_TOUCH_START_WAIT_S)) +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x1FF +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15 + +#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) +/* RTC_CNTL_ROM_RAM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */ +/*description: */ +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_M ((RTC_CNTL_ROM_RAM_POWERUP_TIMER_V)<<(RTC_CNTL_ROM_RAM_POWERUP_TIMER_S)) +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S 25 +/* RTC_CNTL_ROM_RAM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */ +/*description: */ +#define RTC_CNTL_ROM_RAM_WAIT_TIMER 0x000001FF +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_M ((RTC_CNTL_ROM_RAM_WAIT_TIMER_V)<<(RTC_CNTL_ROM_RAM_WAIT_TIMER_S)) +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_S 16 +/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S)) +#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 +/* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S)) +#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_WIFI_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28) +/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 +/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 +/* RTC_CNTL_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_POWERUP_TIMER_M ((RTC_CNTL_POWERUP_TIMER_V)<<(RTC_CNTL_POWERUP_TIMER_S)) +#define RTC_CNTL_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_POWERUP_TIMER_S 9 +/* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WAIT_TIMER_M ((RTC_CNTL_WAIT_TIMER_V)<<(RTC_CNTL_WAIT_TIMER_S)) +#define RTC_CNTL_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2c) +/* RTC_CNTL_RTCMEM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h9 ; */ +/*description: */ +#define RTC_CNTL_RTCMEM_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_M ((RTC_CNTL_RTCMEM_POWERUP_TIMER_V)<<(RTC_CNTL_RTCMEM_POWERUP_TIMER_S)) +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_S 25 +/* RTC_CNTL_RTCMEM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h14 ; */ +/*description: */ +#define RTC_CNTL_RTCMEM_WAIT_TIMER 0x000001FF +#define RTC_CNTL_RTCMEM_WAIT_TIMER_M ((RTC_CNTL_RTCMEM_WAIT_TIMER_V)<<(RTC_CNTL_RTCMEM_WAIT_TIMER_S)) +#define RTC_CNTL_RTCMEM_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_RTCMEM_WAIT_TIMER_S 16 +/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */ +/*description: minimal sleep cycles in slow_clk_rtc*/ +#define RTC_CNTL_MIN_SLP_VAL 0x000000FF +#define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) +#define RTC_CNTL_MIN_SLP_VAL_V 0xFF +#define RTC_CNTL_MIN_SLP_VAL_S 8 +/* RTC_CNTL_ULP_CP_SUBTIMER_PREDIV : R/W ;bitpos:[7:0] ;default: 8'd1 ; */ +/*description: */ +#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV 0x000000FF +#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_M ((RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_V)<<(RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_S)) +#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_V 0xFF +#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_S 0 + +#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x30) +/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: 1: PLL_I2C power up otherwise power down*/ +#define RTC_CNTL_PLL_I2C_PU (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_V 0x1 +#define RTC_CNTL_PLL_I2C_PU_S 31 +/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: 1: CKGEN_I2C power up otherwise power down*/ +#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_V 0x1 +#define RTC_CNTL_CKGEN_I2C_PU_S 30 +/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: 1: RFRX_PBUS power up otherwise power down*/ +#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_V 0x1 +#define RTC_CNTL_RFRX_PBUS_PU_S 28 +/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: 1: TXRF_I2C power up otherwise power down*/ +#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_V 0x1 +#define RTC_CNTL_TXRF_I2C_PU_S 27 +/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1: PVTMON power up otherwise power down*/ +#define RTC_CNTL_PVTMON_PU (BIT(26)) +#define RTC_CNTL_PVTMON_PU_M (BIT(26)) +#define RTC_CNTL_PVTMON_PU_V 0x1 +#define RTC_CNTL_PVTMON_PU_S 26 +/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: start BBPLL calibration during sleep*/ +#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 +#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 +/* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: PLLA force power up*/ +#define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_M (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PU_S 24 +/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: PLLA force power down*/ +#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PD_S 23 + +#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x34) +/* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: PRO CPU state vector sel*/ +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (BIT(13)) +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x1 +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13 +/* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: APP CPU state vector sel*/ +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (BIT(12)) +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x1 +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12 +/* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */ +/*description: reset cause of APP CPU*/ +#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S)) +#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 +/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */ +/*description: reset cause of PRO CPU*/ +#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S)) +#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 + +#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) +/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: enable filter for gpio wakeup event*/ +#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(22)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(22)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 +#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 22 +/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[21:11] ;default: 11'b1100 ; */ +/*description: wakeup enable bitmap*/ +#define RTC_CNTL_WAKEUP_ENA 0x000007FF +#define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) +#define RTC_CNTL_WAKEUP_ENA_V 0x7FF +#define RTC_CNTL_WAKEUP_ENA_S 11 +/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: wakeup cause*/ +#define RTC_CNTL_WAKEUP_CAUSE 0x000007FF +#define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) +#define RTC_CNTL_WAKEUP_CAUSE_V 0x7FF +#define RTC_CNTL_WAKEUP_CAUSE_S 0 + +#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x3c) +/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: enable RTC main timer interrupt*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_S 8 +/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: enable brown out interrupt*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_S 7 +/* RTC_CNTL_TOUCH_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: enable touch interrupt*/ +#define RTC_CNTL_TOUCH_INT_ENA (BIT(6)) +#define RTC_CNTL_TOUCH_INT_ENA_M (BIT(6)) +#define RTC_CNTL_TOUCH_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_INT_ENA_S 6 +/* RTC_CNTL_ULP_CP_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: enable ULP-coprocessor interrupt*/ +#define RTC_CNTL_ULP_CP_INT_ENA (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_V 0x1 +#define RTC_CNTL_ULP_CP_INT_ENA_S 5 +/* RTC_CNTL_TIME_VALID_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: enable RTC time valid interrupt*/ +#define RTC_CNTL_TIME_VALID_INT_ENA (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_ENA_M (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_ENA_V 0x1 +#define RTC_CNTL_TIME_VALID_INT_ENA_S 4 +/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable RTC WDT interrupt*/ +#define RTC_CNTL_WDT_INT_ENA (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: enable SDIO idle interrupt*/ +#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2 +/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable sleep reject interrupt*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable sleep wakeup interrupt*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 + +#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x40) +/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: RTC main timer interrupt raw*/ +#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_RAW_S 8 +/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: brown out interrupt raw*/ +#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_RAW_S 7 +/* RTC_CNTL_TOUCH_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: touch interrupt raw*/ +#define RTC_CNTL_TOUCH_INT_RAW (BIT(6)) +#define RTC_CNTL_TOUCH_INT_RAW_M (BIT(6)) +#define RTC_CNTL_TOUCH_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_INT_RAW_S 6 +/* RTC_CNTL_ULP_CP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ULP-coprocessor interrupt raw*/ +#define RTC_CNTL_ULP_CP_INT_RAW (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_RAW_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_RAW_V 0x1 +#define RTC_CNTL_ULP_CP_INT_RAW_S 5 +/* RTC_CNTL_TIME_VALID_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: RTC time valid interrupt raw*/ +#define RTC_CNTL_TIME_VALID_INT_RAW (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_RAW_M (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_RAW_V 0x1 +#define RTC_CNTL_TIME_VALID_INT_RAW_S 4 +/* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC WDT interrupt raw*/ +#define RTC_CNTL_WDT_INT_RAW (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_V 0x1 +#define RTC_CNTL_WDT_INT_RAW_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SDIO idle interrupt raw*/ +#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_RAW_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2 +/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: sleep reject interrupt raw*/ +#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: sleep wakeup interrupt raw*/ +#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 + +#define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x44) +/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: RTC main timer interrupt state*/ +#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ST_S 8 +/* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: brown out interrupt state*/ +#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ST_S 7 +/* RTC_CNTL_TOUCH_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: touch interrupt state*/ +#define RTC_CNTL_TOUCH_INT_ST (BIT(6)) +#define RTC_CNTL_TOUCH_INT_ST_M (BIT(6)) +#define RTC_CNTL_TOUCH_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_INT_ST_S 6 +/* RTC_CNTL_SAR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ULP-coprocessor interrupt state*/ +#define RTC_CNTL_SAR_INT_ST (BIT(5)) +#define RTC_CNTL_SAR_INT_ST_M (BIT(5)) +#define RTC_CNTL_SAR_INT_ST_V 0x1 +#define RTC_CNTL_SAR_INT_ST_S 5 +/* RTC_CNTL_TIME_VALID_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: RTC time valid interrupt state*/ +#define RTC_CNTL_TIME_VALID_INT_ST (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_ST_M (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_ST_V 0x1 +#define RTC_CNTL_TIME_VALID_INT_ST_S 4 +/* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC WDT interrupt state*/ +#define RTC_CNTL_WDT_INT_ST (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_V 0x1 +#define RTC_CNTL_WDT_INT_ST_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SDIO idle interrupt state*/ +#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ST_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ST_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ST_S 2 +/* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: sleep reject interrupt state*/ +#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ST_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: sleep wakeup interrupt state*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 + +#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x48) +/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Clear RTC main timer interrupt state*/ +#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(8)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_CLR_S 8 +/* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Clear brown out interrupt state*/ +#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(7)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_CLR_S 7 +/* RTC_CNTL_TOUCH_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Clear touch interrupt state*/ +#define RTC_CNTL_TOUCH_INT_CLR (BIT(6)) +#define RTC_CNTL_TOUCH_INT_CLR_M (BIT(6)) +#define RTC_CNTL_TOUCH_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_INT_CLR_S 6 +/* RTC_CNTL_SAR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Clear ULP-coprocessor interrupt state*/ +#define RTC_CNTL_SAR_INT_CLR (BIT(5)) +#define RTC_CNTL_SAR_INT_CLR_M (BIT(5)) +#define RTC_CNTL_SAR_INT_CLR_V 0x1 +#define RTC_CNTL_SAR_INT_CLR_S 5 +/* RTC_CNTL_TIME_VALID_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Clear RTC time valid interrupt state*/ +#define RTC_CNTL_TIME_VALID_INT_CLR (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_CLR_M (BIT(4)) +#define RTC_CNTL_TIME_VALID_INT_CLR_V 0x1 +#define RTC_CNTL_TIME_VALID_INT_CLR_S 4 +/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Clear RTC WDT interrupt state*/ +#define RTC_CNTL_WDT_INT_CLR (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_V 0x1 +#define RTC_CNTL_WDT_INT_CLR_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Clear SDIO idle interrupt state*/ +#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_CLR_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2 +/* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Clear sleep reject interrupt state*/ +#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Clear sleep wakeup interrupt state*/ +#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 + +#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x4c) +/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH0 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S)) +#define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_S 0 + +#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x50) +/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH1 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S)) +#define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_S 0 + +#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x54) +/* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH2 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S)) +#define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_S 0 + +#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x58) +/* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH3 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S)) +#define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_S 0 + +#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x5c) +/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: enable control XTAL by external pads*/ +#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_EN_S 31 +/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 0: power down XTAL at high level 1: power down XTAL at low level*/ +#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_LV_S 30 + +#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) +/* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 0: external wakeup at low level 1: external wakeup at high level*/ +#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) +#define RTC_CNTL_EXT_WAKEUP1_LV_M (BIT(31)) +#define RTC_CNTL_EXT_WAKEUP1_LV_V 0x1 +#define RTC_CNTL_EXT_WAKEUP1_LV_S 31 +/* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 0: external wakeup at low level 1: external wakeup at high level*/ +#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) +#define RTC_CNTL_EXT_WAKEUP0_LV_M (BIT(30)) +#define RTC_CNTL_EXT_WAKEUP0_LV_V 0x1 +#define RTC_CNTL_EXT_WAKEUP0_LV_S 30 + +#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) +/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[31:28] ;default: 4'b0 ; */ +/*description: sleep reject cause*/ +#define RTC_CNTL_REJECT_CAUSE 0x0000000F +#define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) +#define RTC_CNTL_REJECT_CAUSE_V 0xF +#define RTC_CNTL_REJECT_CAUSE_S 28 +/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: enable reject for deep sleep*/ +#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(27)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(27)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 27 +/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: enable reject for light sleep*/ +#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(26)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(26)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 26 +/* RTC_CNTL_SDIO_REJECT_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: enable SDIO reject*/ +#define RTC_CNTL_SDIO_REJECT_EN (BIT(25)) +#define RTC_CNTL_SDIO_REJECT_EN_M (BIT(25)) +#define RTC_CNTL_SDIO_REJECT_EN_V 0x1 +#define RTC_CNTL_SDIO_REJECT_EN_S 25 +/* RTC_CNTL_GPIO_REJECT_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: enable GPIO reject*/ +#define RTC_CNTL_GPIO_REJECT_EN (BIT(24)) +#define RTC_CNTL_GPIO_REJECT_EN_M (BIT(24)) +#define RTC_CNTL_GPIO_REJECT_EN_V 0x1 +#define RTC_CNTL_GPIO_REJECT_EN_S 24 + +#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68) +/* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ +/*description: CPU period sel*/ +#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 +#define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S)) +#define RTC_CNTL_CPUPERIOD_SEL_V 0x3 +#define RTC_CNTL_CPUPERIOD_SEL_S 30 +/* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: CPU sel option*/ +#define RTC_CNTL_CPUSEL_CONF (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_V 0x1 +#define RTC_CNTL_CPUSEL_CONF_S 29 + +#define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6c) +/* RTC_CNTL_SDIO_ACT_DNUM : R/W ;bitpos:[31:22] ;default: 10'b0 ; */ +/*description: */ +#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF +#define RTC_CNTL_SDIO_ACT_DNUM_M ((RTC_CNTL_SDIO_ACT_DNUM_V)<<(RTC_CNTL_SDIO_ACT_DNUM_S)) +#define RTC_CNTL_SDIO_ACT_DNUM_V 0x3FF +#define RTC_CNTL_SDIO_ACT_DNUM_S 22 + +#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) +/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT*/ +#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 +#define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) +#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 +#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 +/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: fast_clk_rtc sel. 0: XTAL div 4 1: CK8M*/ +#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 +#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 +/* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ +/*description: SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL*/ +#define RTC_CNTL_SOC_CLK_SEL 0x00000003 +#define RTC_CNTL_SOC_CLK_SEL_M ((RTC_CNTL_SOC_CLK_SEL_V)<<(RTC_CNTL_SOC_CLK_SEL_S)) +#define RTC_CNTL_SOC_CLK_SEL_V 0x3 +#define RTC_CNTL_SOC_CLK_SEL_S 27 +/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: CK8M force power up*/ +#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PU_S 26 +/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: CK8M force power down*/ +#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PD_S 25 +/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd0 ; */ +/*description: CK8M_DFREQ*/ +#define RTC_CNTL_CK8M_DFREQ 0x000000FF +#define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) +#define RTC_CNTL_CK8M_DFREQ_V 0xFF +#define RTC_CNTL_CK8M_DFREQ_S 17 +/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: CK8M force no gating during sleep*/ +#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 +/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: XTAL force no gating during sleep*/ +#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 +/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd2 ; */ +/*description: divider = reg_ck8m_div_sel + 1*/ +#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 +#define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) +#define RTC_CNTL_CK8M_DIV_SEL_V 0x7 +#define RTC_CNTL_CK8M_DIV_SEL_S 12 +/* RTC_CNTL_CK8M_DFREQ_FORCE : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_CK8M_DFREQ_FORCE (BIT(11)) +#define RTC_CNTL_CK8M_DFREQ_FORCE_M (BIT(11)) +#define RTC_CNTL_CK8M_DFREQ_FORCE_V 0x1 +#define RTC_CNTL_CK8M_DFREQ_FORCE_S 11 +/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: enable CK8M for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_EN_S 10 +/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ +/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 +/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 +#define RTC_CNTL_DIG_XTAL32K_EN_S 8 +/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256*/ +#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_V 0x1 +#define RTC_CNTL_ENB_CK8M_DIV_S 7 +/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: disable CK8M and CK8M_D256_OUT*/ +#define RTC_CNTL_ENB_CK8M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_V 0x1 +#define RTC_CNTL_ENB_CK8M_S 6 +/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ +/*description: CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.*/ +#define RTC_CNTL_CK8M_DIV 0x00000003 +#define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S)) +#define RTC_CNTL_CK8M_DIV_V 0x3 +#define RTC_CNTL_CK8M_DIV_S 4 + +#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) +/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_V 0x1 +#define RTC_CNTL_XPD_SDIO_REG_S 31 +/* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */ +/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFH_SDIO 0x00000003 +#define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S)) +#define RTC_CNTL_DREFH_SDIO_V 0x3 +#define RTC_CNTL_DREFH_SDIO_S 29 +/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b00 ; */ +/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFM_SDIO 0x00000003 +#define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S)) +#define RTC_CNTL_DREFM_SDIO_V 0x3 +#define RTC_CNTL_DREFM_SDIO_S 27 +/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */ +/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFL_SDIO 0x00000003 +#define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S)) +#define RTC_CNTL_DREFL_SDIO_V 0x3 +#define RTC_CNTL_DREFL_SDIO_S 25 +/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */ +/*description: read only register for REG1P8_READY*/ +#define RTC_CNTL_REG1P8_READY (BIT(24)) +#define RTC_CNTL_REG1P8_READY_M (BIT(24)) +#define RTC_CNTL_REG1P8_READY_V 0x1 +#define RTC_CNTL_REG1P8_READY_S 24 +/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_SDIO_TIEH (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_M (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_V 0x1 +#define RTC_CNTL_SDIO_TIEH_S 23 +/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: 1: use SW option to control SDIO_REG 0: use state machine*/ +#define RTC_CNTL_SDIO_FORCE (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_M (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_V 0x1 +#define RTC_CNTL_SDIO_FORCE_S 22 +/* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ +#define RTC_CNTL_SDIO_PD_EN (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_V 0x1 +#define RTC_CNTL_SDIO_PD_EN_S 21 + +#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) +/* RTC_CNTL_RST_BIAS_I2C : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: RST_BIAS_I2C*/ +#define RTC_CNTL_RST_BIAS_I2C (BIT(31)) +#define RTC_CNTL_RST_BIAS_I2C_M (BIT(31)) +#define RTC_CNTL_RST_BIAS_I2C_V 0x1 +#define RTC_CNTL_RST_BIAS_I2C_S 31 +/* RTC_CNTL_DEC_HEARTBEAT_WIDTH : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: DEC_HEARTBEAT_WIDTH*/ +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH (BIT(30)) +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_M (BIT(30)) +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_V 0x1 +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_S 30 +/* RTC_CNTL_INC_HEARTBEAT_PERIOD : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: INC_HEARTBEAT_PERIOD*/ +#define RTC_CNTL_INC_HEARTBEAT_PERIOD (BIT(29)) +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_M (BIT(29)) +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_V 0x1 +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_S 29 +/* RTC_CNTL_DEC_HEARTBEAT_PERIOD : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: DEC_HEARTBEAT_PERIOD*/ +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD (BIT(28)) +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_M (BIT(28)) +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_V 0x1 +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_S 28 +/* RTC_CNTL_INC_HEARTBEAT_REFRESH : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: INC_HEARTBEAT_REFRESH*/ +#define RTC_CNTL_INC_HEARTBEAT_REFRESH (BIT(27)) +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_M (BIT(27)) +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_V 0x1 +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_S 27 +/* RTC_CNTL_ENB_SCK_XTAL : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: ENB_SCK_XTAL*/ +#define RTC_CNTL_ENB_SCK_XTAL (BIT(26)) +#define RTC_CNTL_ENB_SCK_XTAL_M (BIT(26)) +#define RTC_CNTL_ENB_SCK_XTAL_V 0x1 +#define RTC_CNTL_ENB_SCK_XTAL_S 26 +/* RTC_CNTL_DBG_ATTEN : R/W ;bitpos:[25:24] ;default: 2'b00 ; */ +/*description: DBG_ATTEN*/ +#define RTC_CNTL_DBG_ATTEN 0x00000003 +#define RTC_CNTL_DBG_ATTEN_M ((RTC_CNTL_DBG_ATTEN_V)<<(RTC_CNTL_DBG_ATTEN_S)) +#define RTC_CNTL_DBG_ATTEN_V 0x3 +#define RTC_CNTL_DBG_ATTEN_S 24 + +#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c) +/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ +/*description: RTC_REG force power up*/ +#define RTC_CNTL_FORCE_PU (BIT(31)) +#define RTC_CNTL_FORCE_PU_M (BIT(31)) +#define RTC_CNTL_FORCE_PU_V 0x1 +#define RTC_CNTL_FORCE_PU_S 31 +/* RTC_CNTL_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: RTC_REG force power down (for RTC_REG power down means decrease + the voltage to 0.8v or lower )*/ +#define RTC_CNTL_FORCE_PD (BIT(30)) +#define RTC_CNTL_FORCE_PD_M (BIT(30)) +#define RTC_CNTL_FORCE_PD_V 0x1 +#define RTC_CNTL_FORCE_PD_S 30 +/* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ +/*description: RTC_DBOOST force power up*/ +#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PU_S 29 +/* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RTC_DBOOST force power down*/ +#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PD_S 28 +/* RTC_CNTL_DBIAS_WAK : R/W ;bitpos:[27:25] ;default: 3'd4 ; */ +/*description: RTC_DBIAS during wakeup*/ +#define RTC_CNTL_DBIAS_WAK 0x00000007 +#define RTC_CNTL_DBIAS_WAK_M ((RTC_CNTL_DBIAS_WAK_V)<<(RTC_CNTL_DBIAS_WAK_S)) +#define RTC_CNTL_DBIAS_WAK_V 0x7 +#define RTC_CNTL_DBIAS_WAK_S 25 +/* RTC_CNTL_DBIAS_SLP : R/W ;bitpos:[24:22] ;default: 3'd4 ; */ +/*description: RTC_DBIAS during sleep*/ +#define RTC_CNTL_DBIAS_SLP 0x00000007 +#define RTC_CNTL_DBIAS_SLP_M ((RTC_CNTL_DBIAS_SLP_V)<<(RTC_CNTL_DBIAS_SLP_S)) +#define RTC_CNTL_DBIAS_SLP_V 0x7 +#define RTC_CNTL_DBIAS_SLP_S 22 +/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ +/*description: SCK_DCAP*/ +#define RTC_CNTL_SCK_DCAP 0x000000FF +#define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) +#define RTC_CNTL_SCK_DCAP_V 0xFF +#define RTC_CNTL_SCK_DCAP_S 14 +/* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */ +/*description: DIG_REG_DBIAS during wakeup*/ +#define RTC_CNTL_DIG_DBIAS_WAK 0x00000007 +#define RTC_CNTL_DIG_DBIAS_WAK_M ((RTC_CNTL_DIG_DBIAS_WAK_V)<<(RTC_CNTL_DIG_DBIAS_WAK_S)) +#define RTC_CNTL_DIG_DBIAS_WAK_V 0x7 +#define RTC_CNTL_DIG_DBIAS_WAK_S 11 +/* RTC_CNTL_DIG_DBIAS_SLP : R/W ;bitpos:[10:8] ;default: 3'd4 ; */ +/*description: DIG_REG_DBIAS during sleep*/ +#define RTC_CNTL_DIG_DBIAS_SLP 0x00000007 +#define RTC_CNTL_DIG_DBIAS_SLP_M ((RTC_CNTL_DIG_DBIAS_SLP_V)<<(RTC_CNTL_DIG_DBIAS_SLP_S)) +#define RTC_CNTL_DIG_DBIAS_SLP_V 0x7 +#define RTC_CNTL_DIG_DBIAS_SLP_S 8 +/* RTC_CNTL_SCK_DCAP_FORCE : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: N/A*/ +#define RTC_CNTL_SCK_DCAP_FORCE (BIT(7)) +#define RTC_CNTL_SCK_DCAP_FORCE_M (BIT(7)) +#define RTC_CNTL_SCK_DCAP_FORCE_V 0x1 +#define RTC_CNTL_SCK_DCAP_FORCE_S 7 + +#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x80) +/* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: enable power down rtc_peri in sleep*/ +#define RTC_CNTL_PD_EN (BIT(20)) +#define RTC_CNTL_PD_EN_M (BIT(20)) +#define RTC_CNTL_PD_EN_V 0x1 +#define RTC_CNTL_PD_EN_S 20 +/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: rtc_peri force power up*/ +#define RTC_CNTL_PWC_FORCE_PU (BIT(19)) +#define RTC_CNTL_PWC_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_PWC_FORCE_PU_V 0x1 +#define RTC_CNTL_PWC_FORCE_PU_S 19 +/* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: rtc_peri force power down*/ +#define RTC_CNTL_PWC_FORCE_PD (BIT(18)) +#define RTC_CNTL_PWC_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_PWC_FORCE_PD_V 0x1 +#define RTC_CNTL_PWC_FORCE_PD_S 18 +/* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: enable power down RTC memory in sleep*/ +#define RTC_CNTL_SLOWMEM_PD_EN (BIT(17)) +#define RTC_CNTL_SLOWMEM_PD_EN_M (BIT(17)) +#define RTC_CNTL_SLOWMEM_PD_EN_V 0x1 +#define RTC_CNTL_SLOWMEM_PD_EN_S 17 +/* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: RTC memory force power up*/ +#define RTC_CNTL_SLOWMEM_FORCE_PU (BIT(16)) +#define RTC_CNTL_SLOWMEM_FORCE_PU_M (BIT(16)) +#define RTC_CNTL_SLOWMEM_FORCE_PU_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_PU_S 16 +/* RTC_CNTL_SLOWMEM_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: RTC memory force power down*/ +#define RTC_CNTL_SLOWMEM_FORCE_PD (BIT(15)) +#define RTC_CNTL_SLOWMEM_FORCE_PD_M (BIT(15)) +#define RTC_CNTL_SLOWMEM_FORCE_PD_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_PD_S 15 +/* RTC_CNTL_FASTMEM_PD_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable power down fast RTC memory in sleep*/ +#define RTC_CNTL_FASTMEM_PD_EN (BIT(14)) +#define RTC_CNTL_FASTMEM_PD_EN_M (BIT(14)) +#define RTC_CNTL_FASTMEM_PD_EN_V 0x1 +#define RTC_CNTL_FASTMEM_PD_EN_S 14 +/* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: Fast RTC memory force power up*/ +#define RTC_CNTL_FASTMEM_FORCE_PU (BIT(13)) +#define RTC_CNTL_FASTMEM_FORCE_PU_M (BIT(13)) +#define RTC_CNTL_FASTMEM_FORCE_PU_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_PU_S 13 +/* RTC_CNTL_FASTMEM_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Fast RTC memory force power down*/ +#define RTC_CNTL_FASTMEM_FORCE_PD (BIT(12)) +#define RTC_CNTL_FASTMEM_FORCE_PD_M (BIT(12)) +#define RTC_CNTL_FASTMEM_FORCE_PD_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_PD_S 12 +/* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: RTC memory force no PD*/ +#define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11)) +#define RTC_CNTL_SLOWMEM_FORCE_LPU_M (BIT(11)) +#define RTC_CNTL_SLOWMEM_FORCE_LPU_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 +/* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: RTC memory force PD*/ +#define RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10)) +#define RTC_CNTL_SLOWMEM_FORCE_LPD_M (BIT(10)) +#define RTC_CNTL_SLOWMEM_FORCE_LPD_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 +/* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 1: RTC memory PD following CPU 0: RTC memory PD following RTC state machine*/ +#define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9)) +#define RTC_CNTL_SLOWMEM_FOLW_CPU_M (BIT(9)) +#define RTC_CNTL_SLOWMEM_FOLW_CPU_V 0x1 +#define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 +/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: Fast RTC memory force no PD*/ +#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(8)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPU_S 8 +/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Fast RTC memory force PD*/ +#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(7)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPD_S 7 +/* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: 1: Fast RTC memory PD following CPU 0: fast RTC memory PD following + RTC state machine*/ +#define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6)) +#define RTC_CNTL_FASTMEM_FOLW_CPU_M (BIT(6)) +#define RTC_CNTL_FASTMEM_FOLW_CPU_V 0x1 +#define RTC_CNTL_FASTMEM_FOLW_CPU_S 6 +/* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */ +/*description: rtc_peri force no ISO*/ +#define RTC_CNTL_FORCE_NOISO (BIT(5)) +#define RTC_CNTL_FORCE_NOISO_M (BIT(5)) +#define RTC_CNTL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_FORCE_NOISO_S 5 +/* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: rtc_peri force ISO*/ +#define RTC_CNTL_FORCE_ISO (BIT(4)) +#define RTC_CNTL_FORCE_ISO_M (BIT(4)) +#define RTC_CNTL_FORCE_ISO_V 0x1 +#define RTC_CNTL_FORCE_ISO_S 4 +/* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC memory force ISO*/ +#define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3)) +#define RTC_CNTL_SLOWMEM_FORCE_ISO_M (BIT(3)) +#define RTC_CNTL_SLOWMEM_FORCE_ISO_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 +/* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: RTC memory force no ISO*/ +#define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2)) +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_M (BIT(2)) +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 +/* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Fast RTC memory force ISO*/ +#define RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1)) +#define RTC_CNTL_FASTMEM_FORCE_ISO_M (BIT(1)) +#define RTC_CNTL_FASTMEM_FORCE_ISO_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_ISO_S 1 +/* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Fast RTC memory force no ISO*/ +#define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0)) +#define RTC_CNTL_FASTMEM_FORCE_NOISO_M (BIT(0)) +#define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 + +#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x84) +/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */ +/*description: enable power down digital core in sleep*/ +#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 +#define RTC_CNTL_DG_WRAP_PD_EN_S 31 +/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0 ; */ +/*description: enable power down wifi in sleep*/ +#define RTC_CNTL_WIFI_PD_EN (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_V 0x1 +#define RTC_CNTL_WIFI_PD_EN_S 30 +/* RTC_CNTL_INTER_RAM4_PD_EN : R/W ;bitpos:[29] ;default: 0 ; */ +/*description: enable power down internal SRAM 4 in sleep*/ +#define RTC_CNTL_INTER_RAM4_PD_EN (BIT(29)) +#define RTC_CNTL_INTER_RAM4_PD_EN_M (BIT(29)) +#define RTC_CNTL_INTER_RAM4_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM4_PD_EN_S 29 +/* RTC_CNTL_INTER_RAM3_PD_EN : R/W ;bitpos:[28] ;default: 0 ; */ +/*description: enable power down internal SRAM 3 in sleep*/ +#define RTC_CNTL_INTER_RAM3_PD_EN (BIT(28)) +#define RTC_CNTL_INTER_RAM3_PD_EN_M (BIT(28)) +#define RTC_CNTL_INTER_RAM3_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM3_PD_EN_S 28 +/* RTC_CNTL_INTER_RAM2_PD_EN : R/W ;bitpos:[27] ;default: 0 ; */ +/*description: enable power down internal SRAM 2 in sleep*/ +#define RTC_CNTL_INTER_RAM2_PD_EN (BIT(27)) +#define RTC_CNTL_INTER_RAM2_PD_EN_M (BIT(27)) +#define RTC_CNTL_INTER_RAM2_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM2_PD_EN_S 27 +/* RTC_CNTL_INTER_RAM1_PD_EN : R/W ;bitpos:[26] ;default: 0 ; */ +/*description: enable power down internal SRAM 1 in sleep*/ +#define RTC_CNTL_INTER_RAM1_PD_EN (BIT(26)) +#define RTC_CNTL_INTER_RAM1_PD_EN_M (BIT(26)) +#define RTC_CNTL_INTER_RAM1_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM1_PD_EN_S 26 +/* RTC_CNTL_INTER_RAM0_PD_EN : R/W ;bitpos:[25] ;default: 0 ; */ +/*description: enable power down internal SRAM 0 in sleep*/ +#define RTC_CNTL_INTER_RAM0_PD_EN (BIT(25)) +#define RTC_CNTL_INTER_RAM0_PD_EN_M (BIT(25)) +#define RTC_CNTL_INTER_RAM0_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM0_PD_EN_S 25 +/* RTC_CNTL_ROM0_PD_EN : R/W ;bitpos:[24] ;default: 0 ; */ +/*description: enable power down ROM in sleep*/ +#define RTC_CNTL_ROM0_PD_EN (BIT(24)) +#define RTC_CNTL_ROM0_PD_EN_M (BIT(24)) +#define RTC_CNTL_ROM0_PD_EN_V 0x1 +#define RTC_CNTL_ROM0_PD_EN_S 24 +/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */ +/*description: digital core force power up*/ +#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 +/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: digital core force power down*/ +#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 +/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ +/*description: wifi force power up*/ +#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PU_S 18 +/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: wifi force power down*/ +#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PD_S 17 +/* RTC_CNTL_INTER_RAM4_FORCE_PU : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: internal SRAM 4 force power up*/ +#define RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16)) +#define RTC_CNTL_INTER_RAM4_FORCE_PU_M (BIT(16)) +#define RTC_CNTL_INTER_RAM4_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_PU_S 16 +/* RTC_CNTL_INTER_RAM4_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: internal SRAM 4 force power down*/ +#define RTC_CNTL_INTER_RAM4_FORCE_PD (BIT(15)) +#define RTC_CNTL_INTER_RAM4_FORCE_PD_M (BIT(15)) +#define RTC_CNTL_INTER_RAM4_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_PD_S 15 +/* RTC_CNTL_INTER_RAM3_FORCE_PU : R/W ;bitpos:[14] ;default: 1'd1 ; */ +/*description: internal SRAM 3 force power up*/ +#define RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14)) +#define RTC_CNTL_INTER_RAM3_FORCE_PU_M (BIT(14)) +#define RTC_CNTL_INTER_RAM3_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_PU_S 14 +/* RTC_CNTL_INTER_RAM3_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: internal SRAM 3 force power down*/ +#define RTC_CNTL_INTER_RAM3_FORCE_PD (BIT(13)) +#define RTC_CNTL_INTER_RAM3_FORCE_PD_M (BIT(13)) +#define RTC_CNTL_INTER_RAM3_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_PD_S 13 +/* RTC_CNTL_INTER_RAM2_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: internal SRAM 2 force power up*/ +#define RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12)) +#define RTC_CNTL_INTER_RAM2_FORCE_PU_M (BIT(12)) +#define RTC_CNTL_INTER_RAM2_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_PU_S 12 +/* RTC_CNTL_INTER_RAM2_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: internal SRAM 2 force power down*/ +#define RTC_CNTL_INTER_RAM2_FORCE_PD (BIT(11)) +#define RTC_CNTL_INTER_RAM2_FORCE_PD_M (BIT(11)) +#define RTC_CNTL_INTER_RAM2_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_PD_S 11 +/* RTC_CNTL_INTER_RAM1_FORCE_PU : R/W ;bitpos:[10] ;default: 1'd1 ; */ +/*description: internal SRAM 1 force power up*/ +#define RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10)) +#define RTC_CNTL_INTER_RAM1_FORCE_PU_M (BIT(10)) +#define RTC_CNTL_INTER_RAM1_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_PU_S 10 +/* RTC_CNTL_INTER_RAM1_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: internal SRAM 1 force power down*/ +#define RTC_CNTL_INTER_RAM1_FORCE_PD (BIT(9)) +#define RTC_CNTL_INTER_RAM1_FORCE_PD_M (BIT(9)) +#define RTC_CNTL_INTER_RAM1_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_PD_S 9 +/* RTC_CNTL_INTER_RAM0_FORCE_PU : R/W ;bitpos:[8] ;default: 1'd1 ; */ +/*description: internal SRAM 0 force power up*/ +#define RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8)) +#define RTC_CNTL_INTER_RAM0_FORCE_PU_M (BIT(8)) +#define RTC_CNTL_INTER_RAM0_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_PU_S 8 +/* RTC_CNTL_INTER_RAM0_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: internal SRAM 0 force power down*/ +#define RTC_CNTL_INTER_RAM0_FORCE_PD (BIT(7)) +#define RTC_CNTL_INTER_RAM0_FORCE_PD_M (BIT(7)) +#define RTC_CNTL_INTER_RAM0_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_PD_S 7 +/* RTC_CNTL_ROM0_FORCE_PU : R/W ;bitpos:[6] ;default: 1'd1 ; */ +/*description: ROM force power up*/ +#define RTC_CNTL_ROM0_FORCE_PU (BIT(6)) +#define RTC_CNTL_ROM0_FORCE_PU_M (BIT(6)) +#define RTC_CNTL_ROM0_FORCE_PU_V 0x1 +#define RTC_CNTL_ROM0_FORCE_PU_S 6 +/* RTC_CNTL_ROM0_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ROM force power down*/ +#define RTC_CNTL_ROM0_FORCE_PD (BIT(5)) +#define RTC_CNTL_ROM0_FORCE_PD_M (BIT(5)) +#define RTC_CNTL_ROM0_FORCE_PD_V 0x1 +#define RTC_CNTL_ROM0_FORCE_PD_S 5 +/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: memories in digital core force no PD in sleep*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 +/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: memories in digital core force PD in sleep*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 + +#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x88) +/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ +/*description: digital core force no ISO*/ +#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 +/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: digital core force ISO*/ +#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 +/* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */ +/*description: wifi force no ISO*/ +#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_NOISO_S 29 +/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: wifi force ISO*/ +#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_ISO_S 28 +/* RTC_CNTL_INTER_RAM4_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: internal SRAM 4 force no ISO*/ +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S 27 +/* RTC_CNTL_INTER_RAM4_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: internal SRAM 4 force ISO*/ +#define RTC_CNTL_INTER_RAM4_FORCE_ISO (BIT(26)) +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_M (BIT(26)) +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_S 26 +/* RTC_CNTL_INTER_RAM3_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ +/*description: internal SRAM 3 force no ISO*/ +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25)) +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_M (BIT(25)) +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S 25 +/* RTC_CNTL_INTER_RAM3_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: internal SRAM 3 force ISO*/ +#define RTC_CNTL_INTER_RAM3_FORCE_ISO (BIT(24)) +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_S 24 +/* RTC_CNTL_INTER_RAM2_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: internal SRAM 2 force no ISO*/ +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23)) +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_M (BIT(23)) +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S 23 +/* RTC_CNTL_INTER_RAM2_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: internal SRAM 2 force ISO*/ +#define RTC_CNTL_INTER_RAM2_FORCE_ISO (BIT(22)) +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_M (BIT(22)) +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_S 22 +/* RTC_CNTL_INTER_RAM1_FORCE_NOISO : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: internal SRAM 1 force no ISO*/ +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21)) +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_M (BIT(21)) +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S 21 +/* RTC_CNTL_INTER_RAM1_FORCE_ISO : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: internal SRAM 1 force ISO*/ +#define RTC_CNTL_INTER_RAM1_FORCE_ISO (BIT(20)) +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_M (BIT(20)) +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_S 20 +/* RTC_CNTL_INTER_RAM0_FORCE_NOISO : R/W ;bitpos:[19] ;default: 1'd1 ; */ +/*description: internal SRAM 0 force no ISO*/ +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19)) +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_M (BIT(19)) +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S 19 +/* RTC_CNTL_INTER_RAM0_FORCE_ISO : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: internal SRAM 0 force ISO*/ +#define RTC_CNTL_INTER_RAM0_FORCE_ISO (BIT(18)) +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_M (BIT(18)) +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_S 18 +/* RTC_CNTL_ROM0_FORCE_NOISO : R/W ;bitpos:[17] ;default: 1'd1 ; */ +/*description: ROM force no ISO*/ +#define RTC_CNTL_ROM0_FORCE_NOISO (BIT(17)) +#define RTC_CNTL_ROM0_FORCE_NOISO_M (BIT(17)) +#define RTC_CNTL_ROM0_FORCE_NOISO_V 0x1 +#define RTC_CNTL_ROM0_FORCE_NOISO_S 17 +/* RTC_CNTL_ROM0_FORCE_ISO : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: ROM force ISO*/ +#define RTC_CNTL_ROM0_FORCE_ISO (BIT(16)) +#define RTC_CNTL_ROM0_FORCE_ISO_M (BIT(16)) +#define RTC_CNTL_ROM0_FORCE_ISO_V 0x1 +#define RTC_CNTL_ROM0_FORCE_ISO_S 16 +/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: digital pad force hold*/ +#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 +/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */ +/*description: digital pad force un-hold*/ +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 +/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: digital pad force ISO*/ +#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 +/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: digital pad force no ISO*/ +#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 +/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: digital pad enable auto-hold*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 +/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */ +/*description: wtite only register to clear digital pad auto-hold*/ +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 +/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: read only register to indicate digital pad auto-hold status*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 +/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 +/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 + +#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x8c) +/* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: enable RTC WDT*/ +#define RTC_CNTL_WDT_EN (BIT(31)) +#define RTC_CNTL_WDT_EN_M (BIT(31)) +#define RTC_CNTL_WDT_EN_V 0x1 +#define RTC_CNTL_WDT_EN_S 31 +/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG0 0x00000007 +#define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S)) +#define RTC_CNTL_WDT_STG0_V 0x7 +#define RTC_CNTL_WDT_STG0_S 28 +/* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG1 0x00000007 +#define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S)) +#define RTC_CNTL_WDT_STG1_V 0x7 +#define RTC_CNTL_WDT_STG1_S 25 +/* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG2 0x00000007 +#define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S)) +#define RTC_CNTL_WDT_STG2_V 0x7 +#define RTC_CNTL_WDT_STG2_S 22 +/* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en 2: CPU reset stage en 3: system reset + stage en 4: RTC reset stage en*/ +#define RTC_CNTL_WDT_STG3 0x00000007 +#define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S)) +#define RTC_CNTL_WDT_STG3_V 0x7 +#define RTC_CNTL_WDT_STG3_S 19 +/* RTC_CNTL_WDT_EDGE_INT_EN : R/W ;bitpos:[18] ;default: 1'h0 ; */ +/*description: N/A*/ +#define RTC_CNTL_WDT_EDGE_INT_EN (BIT(18)) +#define RTC_CNTL_WDT_EDGE_INT_EN_M (BIT(18)) +#define RTC_CNTL_WDT_EDGE_INT_EN_V 0x1 +#define RTC_CNTL_WDT_EDGE_INT_EN_S 18 +/* RTC_CNTL_WDT_LEVEL_INT_EN : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: N/A*/ +#define RTC_CNTL_WDT_LEVEL_INT_EN (BIT(17)) +#define RTC_CNTL_WDT_LEVEL_INT_EN_M (BIT(17)) +#define RTC_CNTL_WDT_LEVEL_INT_EN_V 0x1 +#define RTC_CNTL_WDT_LEVEL_INT_EN_S 17 +/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[16:14] ;default: 3'h1 ; */ +/*description: CPU reset counter length*/ +#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 14 +/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[13:11] ;default: 3'h1 ; */ +/*description: system reset counter length*/ +#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 11 +/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */ +/*description: enable WDT in flash boot*/ +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(10)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(10)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 10 +/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: enable WDT reset PRO CPU*/ +#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(9)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(9)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 9 +/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: enable WDT reset APP CPU*/ +#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(8)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(8)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 8 +/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[7] ;default: 1'd1 ; */ +/*description: pause WDT in sleep*/ +#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(7)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(7)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 +#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 7 + +#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x90) +/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd128000 ; */ +/*description: */ +#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S)) +#define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x94) +/* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ +/*description: */ +#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S)) +#define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x98) +/* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ +/*description: */ +#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S)) +#define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x9c) +/* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ +/*description: */ +#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S)) +#define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_S 0 + +#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xa0) +/* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_WDT_FEED (BIT(31)) +#define RTC_CNTL_WDT_FEED_M (BIT(31)) +#define RTC_CNTL_WDT_FEED_V 0x1 +#define RTC_CNTL_WDT_FEED_S 31 + +#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xa4) +/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ +/*description: */ +#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) +#define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_S 0 + +#define RTC_CNTL_TEST_MUX_REG (DR_REG_RTCCNTL_BASE + 0xa8) +/* RTC_CNTL_DTEST_RTC : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: DTEST_RTC*/ +#define RTC_CNTL_DTEST_RTC 0x00000003 +#define RTC_CNTL_DTEST_RTC_M ((RTC_CNTL_DTEST_RTC_V)<<(RTC_CNTL_DTEST_RTC_S)) +#define RTC_CNTL_DTEST_RTC_V 0x3 +#define RTC_CNTL_DTEST_RTC_S 30 +/* RTC_CNTL_ENT_RTC : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: ENT_RTC*/ +#define RTC_CNTL_ENT_RTC (BIT(29)) +#define RTC_CNTL_ENT_RTC_M (BIT(29)) +#define RTC_CNTL_ENT_RTC_V 0x1 +#define RTC_CNTL_ENT_RTC_S 29 + +#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xac) +/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ +/*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == + 0x86 will stall PRO CPU*/ +#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 +/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */ +/*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == + 0x86 will stall APP CPU*/ +#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 + +#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xb0) +/* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH4 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S)) +#define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_S 0 + +#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xb4) +/* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH5 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S)) +#define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_S 0 + +#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xb8) +/* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH6 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S)) +#define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_S 0 + +#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xbc) +/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: 32-bit general purpose retention register*/ +#define RTC_CNTL_SCRATCH7 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S)) +#define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_S 0 + +#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xc0) +/* RTC_CNTL_LOW_POWER_DIAG0 : RO ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_LOW_POWER_DIAG0 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG0_M ((RTC_CNTL_LOW_POWER_DIAG0_V)<<(RTC_CNTL_LOW_POWER_DIAG0_S)) +#define RTC_CNTL_LOW_POWER_DIAG0_V 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG0_S 0 + +#define RTC_CNTL_DIAG1_REG (DR_REG_RTCCNTL_BASE + 0xc4) +/* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S)) +#define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_S 0 + +#define RTC_CNTL_HOLD_FORCE_REG (DR_REG_RTCCNTL_BASE + 0xc8) +/* RTC_CNTL_X32N_HOLD_FORCE : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_X32N_HOLD_FORCE (BIT(17)) +#define RTC_CNTL_X32N_HOLD_FORCE_M (BIT(17)) +#define RTC_CNTL_X32N_HOLD_FORCE_V 0x1 +#define RTC_CNTL_X32N_HOLD_FORCE_S 17 +/* RTC_CNTL_X32P_HOLD_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_X32P_HOLD_FORCE (BIT(16)) +#define RTC_CNTL_X32P_HOLD_FORCE_M (BIT(16)) +#define RTC_CNTL_X32P_HOLD_FORCE_V 0x1 +#define RTC_CNTL_X32P_HOLD_FORCE_S 16 +/* RTC_CNTL_TOUCH_PAD7_HOLD_FORCE : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE (BIT(15)) +#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_M (BIT(15)) +#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_S 15 +/* RTC_CNTL_TOUCH_PAD6_HOLD_FORCE : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE (BIT(14)) +#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_M (BIT(14)) +#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_S 14 +/* RTC_CNTL_TOUCH_PAD5_HOLD_FORCE : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE (BIT(13)) +#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_M (BIT(13)) +#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_S 13 +/* RTC_CNTL_TOUCH_PAD4_HOLD_FORCE : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE (BIT(12)) +#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_M (BIT(12)) +#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_S 12 +/* RTC_CNTL_TOUCH_PAD3_HOLD_FORCE : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE (BIT(11)) +#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_M (BIT(11)) +#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_S 11 +/* RTC_CNTL_TOUCH_PAD2_HOLD_FORCE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE (BIT(10)) +#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_M (BIT(10)) +#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_S 10 +/* RTC_CNTL_TOUCH_PAD1_HOLD_FORCE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE (BIT(9)) +#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_M (BIT(9)) +#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_S 9 +/* RTC_CNTL_TOUCH_PAD0_HOLD_FORCE : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE (BIT(8)) +#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_M (BIT(8)) +#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_S 8 +/* RTC_CNTL_SENSE4_HOLD_FORCE : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SENSE4_HOLD_FORCE (BIT(7)) +#define RTC_CNTL_SENSE4_HOLD_FORCE_M (BIT(7)) +#define RTC_CNTL_SENSE4_HOLD_FORCE_V 0x1 +#define RTC_CNTL_SENSE4_HOLD_FORCE_S 7 +/* RTC_CNTL_SENSE3_HOLD_FORCE : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SENSE3_HOLD_FORCE (BIT(6)) +#define RTC_CNTL_SENSE3_HOLD_FORCE_M (BIT(6)) +#define RTC_CNTL_SENSE3_HOLD_FORCE_V 0x1 +#define RTC_CNTL_SENSE3_HOLD_FORCE_S 6 +/* RTC_CNTL_SENSE2_HOLD_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SENSE2_HOLD_FORCE (BIT(5)) +#define RTC_CNTL_SENSE2_HOLD_FORCE_M (BIT(5)) +#define RTC_CNTL_SENSE2_HOLD_FORCE_V 0x1 +#define RTC_CNTL_SENSE2_HOLD_FORCE_S 5 +/* RTC_CNTL_SENSE1_HOLD_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SENSE1_HOLD_FORCE (BIT(4)) +#define RTC_CNTL_SENSE1_HOLD_FORCE_M (BIT(4)) +#define RTC_CNTL_SENSE1_HOLD_FORCE_V 0x1 +#define RTC_CNTL_SENSE1_HOLD_FORCE_S 4 +/* RTC_CNTL_PDAC2_HOLD_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_PDAC2_HOLD_FORCE (BIT(3)) +#define RTC_CNTL_PDAC2_HOLD_FORCE_M (BIT(3)) +#define RTC_CNTL_PDAC2_HOLD_FORCE_V 0x1 +#define RTC_CNTL_PDAC2_HOLD_FORCE_S 3 +/* RTC_CNTL_PDAC1_HOLD_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_PDAC1_HOLD_FORCE (BIT(2)) +#define RTC_CNTL_PDAC1_HOLD_FORCE_M (BIT(2)) +#define RTC_CNTL_PDAC1_HOLD_FORCE_V 0x1 +#define RTC_CNTL_PDAC1_HOLD_FORCE_S 2 +/* RTC_CNTL_ADC2_HOLD_FORCE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_ADC2_HOLD_FORCE (BIT(1)) +#define RTC_CNTL_ADC2_HOLD_FORCE_M (BIT(1)) +#define RTC_CNTL_ADC2_HOLD_FORCE_V 0x1 +#define RTC_CNTL_ADC2_HOLD_FORCE_S 1 +/* RTC_CNTL_ADC1_HOLD_FORCE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_ADC1_HOLD_FORCE (BIT(0)) +#define RTC_CNTL_ADC1_HOLD_FORCE_M (BIT(0)) +#define RTC_CNTL_ADC1_HOLD_FORCE_V 0x1 +#define RTC_CNTL_ADC1_HOLD_FORCE_S 0 + +#define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xcc) +/* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */ +/*description: clear ext wakeup1 status*/ +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(18)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (BIT(18)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x1 +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 18 +/* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[17:0] ;default: 18'd0 ; */ +/*description: Bitmap to select RTC pads for ext wakeup1*/ +#define RTC_CNTL_EXT_WAKEUP1_SEL 0x0003FFFF +#define RTC_CNTL_EXT_WAKEUP1_SEL_M ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S)) +#define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x3FFFF +#define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 + +#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xd0) +/* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[17:0] ;default: 18'd0 ; */ +/*description: ext wakeup1 status*/ +#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x0003FFFF +#define RTC_CNTL_EXT_WAKEUP1_STATUS_M ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x3FFFF +#define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 + +#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xd4) +/* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: brown out detect*/ +#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_V 0x1 +#define RTC_CNTL_BROWN_OUT_DET_S 31 +/* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: enable brown out*/ +#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_ENA_S 30 +/* RTC_CNTL_DBROWN_OUT_THRES : R/W ;bitpos:[29:27] ;default: 3'b010 ; */ +/*description: brown out threshold*/ +#define RTC_CNTL_DBROWN_OUT_THRES 0x00000007 +#define RTC_CNTL_DBROWN_OUT_THRES_M ((RTC_CNTL_DBROWN_OUT_THRES_V)<<(RTC_CNTL_DBROWN_OUT_THRES_S)) +#define RTC_CNTL_DBROWN_OUT_THRES_V 0x7 +#define RTC_CNTL_DBROWN_OUT_THRES_S 27 +/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: enable brown out reset*/ +#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 +/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */ +/*description: brown out reset wait cycles*/ +#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S)) +#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 +/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable power down RF when brown out happens*/ +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 +/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable close flash when brown out happens*/ +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 + +#define RTC_MEM_CONF (DR_REG_RTCCNTL_BASE + 0x40 * 4) +#define RTC_MEM_CRC_FINISH (BIT(31)) +#define RTC_MEM_CRC_FINISH_M (BIT(31)) +#define RTC_MEM_CRC_FINISH_V 0x1 +#define RTC_MEM_CRC_FINISH_S (31) +#define RTC_MEM_CRC_LEN (0x7ff) +#define RTC_MEM_CRC_LEN_M ((RTC_MEM_CRC_LEN_V)<<(RTC_MEM_CRC_LEN_S)) +#define RTC_MEM_CRC_LEN_V (0x7ff) +#define RTC_MEM_CRC_LEN_S (20) +#define RTC_MEM_CRC_ADDR (0x7ff) +#define RTC_MEM_CRC_ADDR_M ((RTC_MEM_CRC_ADDR_V)<<(RTC_MEM_CRC_ADDR_S)) +#define RTC_MEM_CRC_ADDR_V (0x7ff) +#define RTC_MEM_CRC_ADDR_S (9) +#define RTC_MEM_CRC_START (BIT(8)) +#define RTC_MEM_CRC_START_M (BIT(8)) +#define RTC_MEM_CRC_START_V 0x1 +#define RTC_MEM_CRC_START_S (8) +#define RTC_MEM_PID_CONF (0xff) +#define RTC_MEM_PID_CONF_M (0xff) +#define RTC_MEM_PID_CONF_V (0xff) +#define RTC_MEM_PID_CONF_S (0) + +#define RTC_MEM_CRC_RES (DR_REG_RTCCNTL_BASE + 0x41 * 4) + +#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x13c) +/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h1604280 ; */ +/*description: */ +#define RTC_CNTL_CNTL_DATE 0x0FFFFFFF +#define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S)) +#define RTC_CNTL_CNTL_DATE_V 0xFFFFFFF +#define RTC_CNTL_CNTL_DATE_S 0 +#define RTC_CNTL_RTC_CNTL_DATE_VERSION 0x1604280 + + + + +#endif /*__ARCH_XTENSA_SRC_ESP32_CHIP_XTENSA_RTCCNTL_H */ + + diff --git a/arch/xtensa/src/esp32/chip/xtensa_soc.h b/arch/xtensa/src/esp32/chip/xtensa_soc.h new file mode 100644 index 0000000000..99e3600284 --- /dev/null +++ b/arch/xtensa/src/esp32/chip/xtensa_soc.h @@ -0,0 +1,356 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_att.h + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Espressif Systems: + * Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License./* + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_ATTR_H +#define __ARCH_XTENSA_SRC_COMMON_XTENSA_ATTR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Bits */ + +#define BIT31 0x80000000 +#define BIT30 0x40000000 +#define BIT29 0x20000000 +#define BIT28 0x10000000 +#define BIT27 0x08000000 +#define BIT26 0x04000000 +#define BIT25 0x02000000 +#define BIT24 0x01000000 +#define BIT23 0x00800000 +#define BIT22 0x00400000 +#define BIT21 0x00200000 +#define BIT20 0x00100000 +#define BIT19 0x00080000 +#define BIT18 0x00040000 +#define BIT17 0x00020000 +#define BIT16 0x00010000 +#define BIT15 0x00008000 +#define BIT14 0x00004000 +#define BIT13 0x00002000 +#define BIT12 0x00001000 +#define BIT11 0x00000800 +#define BIT10 0x00000400 +#define BIT9 0x00000200 +#define BIT8 0x00000100 +#define BIT7 0x00000080 +#define BIT6 0x00000040 +#define BIT5 0x00000020 +#define BIT4 0x00000010 +#define BIT3 0x00000008 +#define BIT2 0x00000004 +#define BIT1 0x00000002 +#define BIT0 0x00000001 + +#define PRO_CPU_NUM (0) +#define APP_CPU_NUM (1) + +/* Registers Operation */ + +#define ETS_UNCACHED_ADDR(addr) (addr) +#define ETS_CACHED_ADDR(addr) (addr) + +#define BIT(nr) (1UL << (nr)) + +/* Write value to register */ + +#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) + +/* Read value from register */ + +#define REG_READ(_r) (*(volatile uint32_t *)(_r)) + +/* Get bit or get bits from register */ + +#define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b)) + +/* Set bit or set bits to register */ + +#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b)) + +/* Clear bit or clear bits of register */ + +#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b)) + +/* Set bits of register controlled by mask */ + +#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))) + +/* Get field from register, used when _f is not left shifted by _f##_S */ + +#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f)) + +/* Set field to register, used when _f is not left shifted by _f##_S */ + +#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f) << (_f##_S)))|(((_v) & (_f))<<(_f##_S))))) + +/* Set field value from a variable, used when _f is not left shifted by _f##_S */ + +#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +/* Get field value from a variable, used when _f is left shifted by _f##_S */ + +#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +/* Set field value to a variable, used when _f is not left shifted by _f##_S */ + +#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +/* Set field value to a variable, used when _f is left shifted by _f##_S + +#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +/* Generate a value from a field value, used when _f is not left shifted by _f##_S */ + +#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +/* Generate a value from a field value, used when _f is left shifted by _f##_S */ + +#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +/* Read value from register */ + +#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) + +/* Write value to register */ + +#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val) + +/* Clear bits of register controlled by mask */ + +#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))) + +/* Set bits of register controlled by mask + +#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))) + +/* Get bits of register controlled by mask + +#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask)) + +/* Get bits of register controlled by highest bit and lowest bit */ + +#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) + +/* Set bits of register controlled by mask and shift */ + +#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )) + +/* Get field of register */ + +#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask)) + +/* Periheral Clock */ + +#define APB_CLK_FREQ_ROM 26*1000000 +#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM +#define CPU_CLK_FREQ APB_CLK_FREQ +#define APB_CLK_FREQ 80*1000000 /* Unit: Hz */ +#define UART_CLK_FREQ APB_CLK_FREQ +#define WDT_CLK_FREQ APB_CLK_FREQ +#define TIMER_CLK_FREQ (80000000>>4) /* 80MHz divided by 16 */ +#define SPI_CLK_DIV 4 +#define TICKS_PER_US_ROM 26 /* CPU is 80MHz */ + +#define DR_REG_DPORT_BASE 0x3ff00000 +#define DR_REG_UART_BASE 0x3ff40000 +#define DR_REG_SPI1_BASE 0x3ff42000 +#define DR_REG_SPI0_BASE 0x3ff43000 +#define DR_REG_GPIO_BASE 0x3ff44000 +#define DR_REG_GPIO_SD_BASE 0x3ff44f00 +#define DR_REG_FE2_BASE 0x3ff45000 +#define DR_REG_FE_BASE 0x3ff46000 +#define DR_REG_RTCCNTL_BASE 0x3ff48000 +#define DR_REG_RTCIO_BASE 0x3ff48400 +#define DR_REG_SARADC_BASE 0x3ff48800 +#define DR_REG_IO_MUX_BASE 0x3ff49000 +#define DR_REG_RTCMEM0_BASE 0x3ff61000 +#define DR_REG_RTCMEM1_BASE 0x3ff62000 +#define DR_REG_RTCMEM2_BASE 0x3ff63000 +#define DR_REG_HINF_BASE 0x3ff4B000 +#define DR_REG_UHCI1_BASE 0x3ff4C000 +#define DR_REG_I2S_BASE 0x3ff4F000 +#define DR_REG_UART1_BASE 0x3ff50000 +#define DR_REG_BT_BASE 0x3ff51000 +#define DR_REG_I2C_EXT_BASE 0x3ff53000 +#define DR_REG_UHCI0_BASE 0x3ff54000 +#define DR_REG_SLCHOST_BASE 0x3ff55000 +#define DR_REG_RMT_BASE 0x3ff56000 +#define DR_REG_PCNT_BASE 0x3ff57000 +#define DR_REG_SLC_BASE 0x3ff58000 +#define DR_REG_LEDC_BASE 0x3ff59000 +#define DR_REG_EFUSE_BASE 0x3ff5A000 +#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000 +#define DR_REG_PWM_BASE 0x3ff5E000 +#define DR_REG_TIMERGROUP0_BASE 0x3ff5F000 +#define DR_REG_TIMERGROUP1_BASE 0x3ff60000 +#define DR_REG_SPI2_BASE 0x3ff64000 +#define DR_REG_SPI3_BASE 0x3ff65000 +#define DR_REG_I2C1_EXT_BASE 0x3ff67000 +#define DR_REG_SDMMC_BASE 0x3ff68000 +#define DR_REG_EMAC_BASE 0x3ff69000 +#define DR_REG_PWM1_BASE 0x3ff6C000 +#define DR_REG_I2S1_BASE 0x3ff6D000 +#define DR_REG_UART2_BASE 0x3ff6E000 +#define DR_REG_PWM2_BASE 0x3ff6F000 +#define DR_REG_PWM3_BASE 0x3ff70000 +#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE + +/* Interrupt hardware source table + * This table is decided by hardware, don't touch this. + */ + +#define ETS_WIFI_MAC_INTR_SOURCE 0 /* Interrupt of WiFi MAC, level */ +#define ETS_WIFI_MAC_NMI_SOURCE 1 /* Interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI */ +#define ETS_WIFI_BB_INTR_SOURCE 2 /* Interrupt of WiFi BB, level, we can do some calibartion */ +#define ETS_BT_MAC_INTR_SOURCE 3 /* will be cancelled */ +#define ETS_BT_BB_INTR_SOURCE 4 /* Interrupt of BT BB, level */ +#define ETS_BT_BB_NMI_SOURCE 5 /* Interrupt of BT BB, NMI, use if BB have bug to fix in NMI */ +#define ETS_RWBT_INTR_SOURCE 6 /* Interrupt of RWBT, level */ +#define ETS_RWBLE_INTR_SOURCE 7 /* Interrupt of RWBLE, level */ +#define ETS_RWBT_NMI_SOURCE 8 /* Interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI */ +#define ETS_RWBLE_NMI_SOURCE 9 /* Interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI */ +#define ETS_SLC0_INTR_SOURCE 10 /* Interrupt of SLC0, level */ +#define ETS_SLC1_INTR_SOURCE 11 /* Interrupt of SLC1, level */ +#define ETS_UHCI0_INTR_SOURCE 12 /* Interrupt of UHCI0, level */ +#define ETS_UHCI1_INTR_SOURCE 13 /* Interrupt of UHCI1, level */ +#define ETS_TG0_T0_LEVEL_INTR_SOURCE 14 /* Interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission */ +#define ETS_TG0_T1_LEVEL_INTR_SOURCE 15 /* Interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission */ +#define ETS_TG0_WDT_LEVEL_INTR_SOURCE 16 /* Interrupt of TIMER_GROUP0, WATCHDOG, level */ +#define ETS_TG0_LACT_LEVEL_INTR_SOURCE 17 /* Interrupt of TIMER_GROUP0, LACT, level */ +#define ETS_TG1_T0_LEVEL_INTR_SOURCE 18 /* Interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission */ +#define ETS_TG1_T1_LEVEL_INTR_SOURCE 19 /* Interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission */ +#define ETS_TG1_WDT_LEVEL_INTR_SOURCE 20 /* Interrupt of TIMER_GROUP1, WATCHDOG, level */ +#define ETS_TG1_LACT_LEVEL_INTR_SOURCE 21 /* Interrupt of TIMER_GROUP1, LACT, level */ +#define ETS_GPIO_INTR_SOURCE 22 /* Interrupt of GPIO, level */ +#define ETS_GPIO_NMI_SOURCE 23 /* Interrupt of GPIO, NMI */ +#define ETS_FROM_CPU_INTR0_SOURCE 24 /* Interrupt0 generated from a CPU, level */ +#define ETS_FROM_CPU_INTR1_SOURCE 25 /* Interrupt1 generated from a CPU, level */ +#define ETS_FROM_CPU_INTR2_SOURCE 26 /* Interrupt2 generated from a CPU, level */ +#define ETS_FROM_CPU_INTR3_SOURCE 27 /* Interrupt3 generated from a CPU, level */ +#define ETS_SPI0_INTR_SOURCE 28 /* Interrupt of SPI0, level, SPI0 is for Cache Access, do not use this */ +#define ETS_SPI1_INTR_SOURCE 29 /* Interrupt of SPI1, level, SPI1 is for flash read/write, do not use this */ +#define ETS_SPI2_INTR_SOURCE 30 /* Interrupt of SPI2, level */ +#define ETS_SPI3_INTR_SOURCE 31 /* Interrupt of SPI3, level */ +#define ETS_I2S0_INTR_SOURCE 32 /* Interrupt of I2S0, level */ +#define ETS_I2S1_INTR_SOURCE 33 /* Interrupt of I2S1, level */ +#define ETS_UART0_INTR_SOURCE 34 /* Interrupt of UART0, level */ +#define ETS_UART1_INTR_SOURCE 35 /* Interrupt of UART1, level */ +#define ETS_UART2_INTR_SOURCE 36 /* Interrupt of UART2, level */ +#define ETS_SDIO_HOST_INTR_SOURCE 37 /* Interrupt of SD/SDIO/MMC HOST, level */ +#define ETS_ETH_MAC_INTR_SOURCE 38 /* Interrupt of ethernet mac, level */ +#define ETS_PWM0_INTR_SOURCE 39 /* Interrupt of PWM0, level, Reserved */ +#define ETS_PWM1_INTR_SOURCE 40 /* Interrupt of PWM1, level, Reserved */ +#define ETS_PWM2_INTR_SOURCE 41 /* Interrupt of PWM2, level */ +#define ETS_PWM3_INTR_SOURCE 42 /* Interruot of PWM3, level */ +#define ETS_LEDC_INTR_SOURCE 43 /* Interrupt of LED PWM, level */ +#define ETS_EFUSE_INTR_SOURCE 44 /* Interrupt of efuse, level, not likely to use */ +#define ETS_CAN_INTR_SOURCE 45 /* Interrupt of can, level */ +#define ETS_RTC_CORE_INTR_SOURCE 46 /* Interrupt of rtc core, level, include rtc watchdog */ +#define ETS_RMT_INTR_SOURCE 47 /* Interrupt of remote controller, level */ +#define ETS_PCNT_INTR_SOURCE 48 /* Interrupt of pluse count, level */ +#define ETS_I2C_EXT0_INTR_SOURCE 49 /* Interrupt of I2C controller1, level */ +#define ETS_I2C_EXT1_INTR_SOURCE 50 /* Interrupt of I2C controller0, level */ +#define ETS_RSA_INTR_SOURCE 51 /* Interrupt of RSA accelerator, level */ +#define ETS_SPI1_DMA_INTR_SOURCE 52 /* Interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this */ +#define ETS_SPI2_DMA_INTR_SOURCE 53 /* Interrupt of SPI2 DMA, level */ +#define ETS_SPI3_DMA_INTR_SOURCE 54 /* Interrupt of SPI3 DMA, level */ +#define ETS_WDT_INTR_SOURCE 55 /* will be cancelled */ +#define ETS_TIMER1_INTR_SOURCE 56 /* will be cancelled */ +#define ETS_TIMER2_INTR_SOURCE 57 /* will be cancelled */ +#define ETS_TG0_T0_EDGE_INTR_SOURCE 58 /* Interrupt of TIMER_GROUP0, TIMER0, EDGE */ +#define ETS_TG0_T1_EDGE_INTR_SOURCE 59 /* Interrupt of TIMER_GROUP0, TIMER1, EDGE */ +#define ETS_TG0_WDT_EDGE_INTR_SOURCE 60 /* Interrupt of TIMER_GROUP0, WATCH DOG, EDGE */ +#define ETS_TG0_LACT_EDGE_INTR_SOURCE 61 /* Interrupt of TIMER_GROUP0, LACT, EDGE */ +#define ETS_TG1_T0_EDGE_INTR_SOURCE 62 /* Interrupt of TIMER_GROUP1, TIMER0, EDGE */ +#define ETS_TG1_T1_EDGE_INTR_SOURCE 63 /* Interrupt of TIMER_GROUP1, TIMER1, EDGE */ +#define ETS_TG1_WDT_EDGE_INTR_SOURCE 64 /* Interrupt of TIMER_GROUP1, WATCHDOG, EDGE */ +#define ETS_TG1_LACT_EDGE_INTR_SOURCE 65 /* Interrupt of TIMER_GROUP0, LACT, EDGE */ +#define ETS_MMU_IA_INTR_SOURCE 66 /* Interrupt of MMU Invalid Access, LEVEL */ +#define ETS_MPU_IA_INTR_SOURCE 67 /* Interrupt of MPU Invalid Access, LEVEL */ +#define ETS_CACHE_IA_INTR_SOURCE 68 /* Interrupt of Cache Invalied Access, LEVEL */ + +/* Interrupt cpu using table */ +/************************************************************************************************************* + * Intr num Level Type PRO CPU usage APP CPU uasge + * 0 1 extern level WMAC Reserved + * 1 1 extern level BT/BLE Host VHCI Reserved + * 2 1 extern level FROM_CPU FROM_CPU + * 3 1 extern level TG0_WDT Reserved + * 4 1 extern level WBB + * 5 1 extern level BT Controller + * 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1) + * 7 1 software Reserved Reserved + * 8 1 extern level BLE Controller + * 9 1 extern level + * 10 1 extern edge Internal Timer + * 11 3 profiling + * 12 1 extern level + * 13 1 extern level + * 14 7 nmi Reserved Reserved + * 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3) + * 16 5 timer + * 17 1 extern level + * 18 1 extern level + * 19 2 extern level + * 20 2 extern level + * 21 2 extern level + * 22 3 extern edge + * 23 3 extern level + * 24 4 extern level + * 25 4 extern level Reserved Reserved + * 26 5 extern level Reserved Reserved + * 27 3 extern level Reserved Reserved + * 28 4 extern edge + * 29 3 software Reserved Reserved + * 30 4 extern edge Reserved Reserved + * 31 5 extern level Reserved Reserved + *************************************************************************************************************/ + +/* CPU0 Interrupt number reserved, not touch this. */ + +#define ETS_WMAC_INUM 0 +#define ETS_BT_HOST_INUM 1 +#define ETS_FROM_CPU_INUM 2 +#define ETS_T0_WDT_INUM 3 +#define ETS_WBB_INUM 4 +#define ETS_TG0_T1_INUM 10 /* Use edge interrupt */ + +/* CPU0 Intrrupt number used in ROM, should be cancelled in SDK */ + +#define ETS_SLC_INUM 1 +#define ETS_UART0_INUM 5 +#define ETS_UART1_INUM 5 + +/* Other interrupt numbers should be managed by the user */ + +#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_ATTR_H */ diff --git a/arch/xtensa/src/esp32/esp32_start.c b/arch/xtensa/src/esp32/esp32_start.c new file mode 100644 index 0000000000..7e73b4a04e --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_start.c @@ -0,0 +1,128 @@ +/**************************************************************************** + * arch/xtensa/src/common/esp32_start.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Basic initialize sequence derives from logic originally provided by + * Espressif Systems: + * + * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "xtensa_attr.h" +#include "chip/esp32_dport.h" +#include "chip/esp32_rtccntl.h" +#include "xtensa.h" + +#warning REVISIT Need cpu_configure_region_protection() prototype +void cpu_configure_region_protection(void); + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: __start + * + * Description: + * We arrive here after the bootloader finished loading the program from + * flash. The hardware is mostly uninitialized, and the app CPU is in + * reset. We do have a stack, so we can do the initialization in C. + * + * The app CPU will remain in reset unless CONFIG_SMP is selected and + * up_cpu_start() is called later in the bring-up sequeuence. + * + ****************************************************************************/ + +void IRAM_ATTR __start() +{ + uint32_t regval; + + /* Kill the watchdog timer */ + + regval = getreg32(RTC_CNTL_WDTCONFIG0_REG); + regval ~= RTC_CNTL_WDT_FLASHBOOT_MOD_EN; + putreg32(regval, RTC_CNTL_WDTCONFIG0_REG); + + regval = getreg32(0x6001f048); /* DR_REG_BB_BASE+48 */ + regval ~= (1 << 14); + putreg32(regval, 0x6001f048); + + /* Make page 0 access raise an exception */ + + cpu_configure_region_protection(); + + /* Move exception vectors to IRAM */ + + asm volatile ("wsr %0, vecbase\n"::"r" (&_init_start)); + + /* Set .bss to zero */ + + memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start)); + +#warning Missing logic: Initialize .data + +#warning REVISIT heap. Do what with non-heterogeneous memory? +#warning REVISIT belongs in up_allocateheap() +#if 0 + /* Initialize heap allocator */ + + heap_alloc_caps_init(); +#endif + + /* Make sure that the APP_CPU is disabled for now */ + + regval = getreg32(DPORT_APPCPU_CTRL_B_REG); + regval &= ~DPORT_APPCPU_CLKGATE_EN + putreg32(regval, DPORT_APPCPU_CTRL_B_REG); + + /* Set CPU frequency configured in board.h */ + + esp_set_cpu_freq(); + +#ifdef USE_EARLYSERIALINIT + /* Perform early serial initialization */ + + up_earlyserialinit(); +#endif + + /* Initialize onboard resources */ + + esp32_board_initialize(); + +#warning These belong elsewhere +#if 0 + ets_setup_syscalls(); + esp_ipc_init(); + spi_flash_init(); +#endif + + /* Bring up NuttX */ + + os_start(); +} -- GitLab From 51fc3de40b5d4fd077610dd713b11203e9068347 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 17 Oct 2016 09:13:12 -0600 Subject: [PATCH 095/734] Xtensa: Add CPU1 start logic --- arch/xtensa/src/esp32/Make.defs | 17 +- arch/xtensa/src/esp32/esp32_cpustart.c | 220 +++++++++++++++++++++++++ arch/xtensa/src/esp32/esp32_start.c | 8 +- 3 files changed, 236 insertions(+), 9 deletions(-) create mode 100644 arch/xtensa/src/esp32/esp32_cpustart.c diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 06aeded18c..71f583227c 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -35,7 +35,7 @@ # The start-up, "head", file -HEAD_ASRC = +HEAD_ASRC = esp32_start.c # Common XTENSA files (arch/xtensa/src/common) @@ -50,8 +50,9 @@ CMN_CSRCS += xtensa_stackframe.c xtensa_udelay.c xtensa_usestack.c # Configuration-dependent common XTENSA files # Use of common/xtensa_etherstub.c is deprecated. The preferred mechanism -# is to use CONFIG_NETDEV_LATEINIT=y to suppress the call to up_netinitialize() -# in xtensa_initialize.c. Then this stub would not be needed. +# is to use CONFIG_NETDEV_LATEINIT=y to suppress the call to +# up_netinitialize() in xtensa_initialize.c. Then this stub would not be +# needed. ifneq ($(CONFIG_LX6_ETHERNET),y) ifeq ($(CONFIG_NET),y) @@ -59,9 +60,15 @@ ifeq ($(CONFIG_NET),y) endif endif -# Required LX6 files (arch/xtensa/src/lx6) +# Required ESP32 files (arch/xtensa/src/lx6) CHIP_ASRCS = CHIP_CSRCS = -# Configuration-dependent LX6 files +# Configuration-dependent ESP32 files + +ifeq ($(CONFIG_SMP),y) +#CMN_CSRCS += esp32_cpuindex.c esp32_cpustart.c esp32_cpupause.c +#CMN_CSRCS += esp32_cpuidlestack.c +CMN_CSRCS += esp32_cpustart.c +endif diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c new file mode 100644 index 0000000000..c8e7cc66bb --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -0,0 +1,220 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_cpustart.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "xtensa.h" + +#ifdef CONFIG_SMP + +#warning REVISIT Need cpu_configure_region_protection() prototype +void cpu_configure_region_protection(void); +#warning REVISIT Need ets_set_appcpu_boot_addr() prototype +void ets_set_appcpu_boot_addr(uint32_t); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static bool g_appcpu_started; +static sem_t g_appcpu_interlock; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_registerdump + ****************************************************************************/ + +#if 0 /* Was useful in solving some startup problems */ +static inline void xtensa_registerdump(FAR struct tcb_s *tcb) +{ + _info("CPU%d:\n", up_cpu_index()); + + /* Dump the startup registers */ + /* To be provided */ +} +#else +# define xtensa_registerdump(tcb) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_start_handler + * + * Description: + * This is the handler for SGI1. This handler simply returns from the + * interrupt, restoring the state of the new task at the head of the ready + * to run list. + * + * Input Parameters: + * Standard interrupt handling + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +int xtensa_start_handler(int irq, FAR void *context) +{ + FAR struct tcb_s *tcb; + + sinfo("CPU%d Started\n", up_cpu_index()); + + /* Handle interlock*/ + + g_appcpu_started = true; + sem_post(&g_appcpu_interlock); + + /* Reset scheduler parameters */ + + tcb = this_task(); + sched_resume_scheduler(tcb); + + /* Move CPU0 exception vectors to IRAM */ + + asm volatile ("wsr %0, vecbase\n"::"r" (&_init_start)); + + /* Make page 0 access raise an exception */ + + cpu_configure_region_protection(); + + /* Dump registers so that we can see what is going to happen on return */ + + xtensa_registerdump(tcb); + + /* Then switch contexts. This instantiates the exception context of the + * tcb at the head of the assigned task list. In this case, this should + * be the CPUs NULL task. + */ + + up_restorestate(tcb->xcp.regs); + return OK; +} + +/**************************************************************************** + * Name: up_cpu_start + * + * Description: + * In an SMP configution, only one CPU is initially active (CPU 0). System + * initialization occurs on that single thread. At the completion of the + * initialization of the OS, just before beginning normal multitasking, + * the additional CPUs would be started by calling this function. + * + * Each CPU is provided the entry point to is IDLE task when started. A + * TCB for each CPU's IDLE task has been initialized and placed in the + * CPU's g_assignedtasks[cpu] list. Not stack has been alloced or + * initialized. + * + * The OS initialization logic calls this function repeatedly until each + * CPU has been started, 1 through (CONFIG_SMP_NCPUS-1). + * + * Input Parameters: + * cpu - The index of the CPU being started. This will be a numeric + * value in the range of from one to (CONFIG_SMP_NCPUS-1). (CPU + * 0 is already active) + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +int up_cpu_start(int cpu) +{ + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu()); + + if (!g_appcpu_started) + { + uint32_t regval; + int ret; + + /* Start CPU1 */ + + sinfo("Starting CPU%d\n", cpu); + sem_init(&g_appcpu_interlock, 0, 0) + + regval = getreg32(DPORT_APPCPU_CTRL_B_REG); + regval |= DPORT_APPCPU_CLKGATE_EN; + putreg32(regval, DPORT_APPCPU_CTRL_B_REG); + + regval = getreg32(DPORT_APPCPU_CTRL_C_REG); + regval ~= DPORT_APPCPU_RUNSTALL; + putreg32(regval, DPORT_APPCPU_CTRL_C_REG); + + regval = getreg32(DPORT_APPCPU_CTRL_A_REG); + regval |= DPORT_APPCPU_RESETTING; + putreg32(regval, DPORT_APPCPU_CTRL_A_REG); + + regval = getreg32(DPORT_APPCPU_CTRL_A_REG); + regval &= ~DPORT_APPCPU_RESETTING; + putreg32(regval, DPORT_APPCPU_CTRL_A_REG); + + /* Set the CPU1 start address */ + + ets_set_appcpu_boot_addr((uint32_t)xtensa_start_handler); + + /* And way for the initial task to run on CPU1 */ + + while (!app_cpu_started) + { + ret = sem_wait(&g_appcpu_interlock); + if (ret < 0) + { + DEBUGASSERT(errno == EINTR); + } + } + + sem_destroy(&g_appcpu_interlock); + } +} + +#endif /* CONFIG_SMP */ diff --git a/arch/xtensa/src/esp32/esp32_start.c b/arch/xtensa/src/esp32/esp32_start.c index 7e73b4a04e..e78c0cff17 100644 --- a/arch/xtensa/src/esp32/esp32_start.c +++ b/arch/xtensa/src/esp32/esp32_start.c @@ -66,20 +66,20 @@ void IRAM_ATTR __start() /* Kill the watchdog timer */ regval = getreg32(RTC_CNTL_WDTCONFIG0_REG); - regval ~= RTC_CNTL_WDT_FLASHBOOT_MOD_EN; + regval &= ~RTC_CNTL_WDT_FLASHBOOT_MOD_EN; putreg32(regval, RTC_CNTL_WDTCONFIG0_REG); regval = getreg32(0x6001f048); /* DR_REG_BB_BASE+48 */ - regval ~= (1 << 14); + regval &= ~(1 << 14); putreg32(regval, 0x6001f048); /* Make page 0 access raise an exception */ cpu_configure_region_protection(); - /* Move exception vectors to IRAM */ + /* Move CPU0 exception vectors to IRAM */ - asm volatile ("wsr %0, vecbase\n"::"r" (&_init_start)); + asm volatile ("wsr %0, vecbase\n"::"r" (&_init_start)); /* Set .bss to zero */ -- GitLab From 84049a19baf049abafcbd4124febafb585a65677 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 17 Oct 2016 09:45:12 -0600 Subject: [PATCH 096/734] C library: Add a dummy setlocale() function to avoid drawing the function from newlib --- include/locale.h | 68 +++++++++++++++++++++++++++++++++++++ libc/Makefile | 1 + libc/README.txt | 1 + libc/locale/Make.defs | 43 +++++++++++++++++++++++ libc/locale/lib_setlocale.c | 66 +++++++++++++++++++++++++++++++++++ libc/misc/lib_uadd32x64.c | 2 +- libc/misc/lib_uadd64.c | 2 +- libc/misc/lib_umul32.c | 2 +- libc/misc/lib_umul32x64.c | 2 +- libc/misc/lib_umul64.c | 2 +- libc/misc/lib_usub64.c | 2 +- libc/misc/lib_usub64x32.c | 2 +- 12 files changed, 186 insertions(+), 7 deletions(-) create mode 100644 include/locale.h create mode 100644 libc/locale/Make.defs create mode 100644 libc/locale/lib_setlocale.c diff --git a/include/locale.h b/include/locale.h new file mode 100644 index 0000000000..2d61f8d753 --- /dev/null +++ b/include/locale.h @@ -0,0 +1,68 @@ +/**************************************************************************** + * include/locale.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __INCLUDE_LOCALE_H +#define __INCLUDE_LOCALE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Type Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +FAR char *setlocale(int category, FAR const char *locale); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __INCLUDE_LOCALE_H */ diff --git a/libc/Makefile b/libc/Makefile index 1399de558a..b903fe4737 100644 --- a/libc/Makefile +++ b/libc/Makefile @@ -67,6 +67,7 @@ include dirent/Make.defs include fixedmath/Make.defs include hex2bin/Make.defs include libgen/Make.defs +include locale/Make.defs include math/Make.defs include misc/Make.defs include net/Make.defs diff --git a/libc/README.txt b/libc/README.txt index 4b329205eb..c964749e28 100644 --- a/libc/README.txt +++ b/libc/README.txt @@ -31,6 +31,7 @@ we have: audio - This part of he audio system: nuttx/audio/audio.h hex2bin - hex2bin.h libgen - libgen.h + locale - locale.h fixedmath - fixedmath.h math - math.h net - Various network-related header files: netinet/ether.h, arpa/inet.h diff --git a/libc/locale/Make.defs b/libc/locale/Make.defs new file mode 100644 index 0000000000..a7a40e190b --- /dev/null +++ b/libc/locale/Make.defs @@ -0,0 +1,43 @@ +############################################################################ +# libc/locale/Make.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# Add the locale files to the build + +CSRCS += lib_setlocale.c + +# Add the locale directory to the build + +DEPPATH += --dep-path locale +VPATH += :locale diff --git a/libc/locale/lib_setlocale.c b/libc/locale/lib_setlocale.c new file mode 100644 index 0000000000..8f5fffd62e --- /dev/null +++ b/libc/locale/lib_setlocale.c @@ -0,0 +1,66 @@ +/**************************************************************************** + * libc/locale/lib_setlocale.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: setlocale + * + * Description: + * locales are not supported by NuttX + * + * Input Parameters: + * category and locale - Select the appropriate piece of the program's + * locale. + * + ****************************************************************************/ + +FAR char *setlocale(int category, FAR const char *locale) +{ + /* NULL indicates the the locale was not changed */ + + return NULL; +} diff --git a/libc/misc/lib_uadd32x64.c b/libc/misc/lib_uadd32x64.c index 291a282d7c..ea9b851da6 100644 --- a/libc/misc/lib_uadd32x64.c +++ b/libc/misc/lib_uadd32x64.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/fixedmath/lib_uadd32x64.c + * libc/misc/lib_uadd32x64.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/misc/lib_uadd64.c b/libc/misc/lib_uadd64.c index 8d07168791..60baf6867c 100644 --- a/libc/misc/lib_uadd64.c +++ b/libc/misc/lib_uadd64.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/fixedmath/lib_uadd64.c + * libc/misc/lib_uadd64.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/misc/lib_umul32.c b/libc/misc/lib_umul32.c index 27540c08ef..f390673734 100644 --- a/libc/misc/lib_umul32.c +++ b/libc/misc/lib_umul32.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/fixedmath/lib_umul32.c + * libc/misc/lib_umul32.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/misc/lib_umul32x64.c b/libc/misc/lib_umul32x64.c index b7c4510f01..326b3d4d7d 100644 --- a/libc/misc/lib_umul32x64.c +++ b/libc/misc/lib_umul32x64.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/fixedmath/lib_umul32x64.c + * libc/misc/lib_umul32x64.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/misc/lib_umul64.c b/libc/misc/lib_umul64.c index 29cbd37a9e..4a5b3f4151 100644 --- a/libc/misc/lib_umul64.c +++ b/libc/misc/lib_umul64.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/fixedmath/lib_umul64.c + * libc/misc/lib_umul64.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/misc/lib_usub64.c b/libc/misc/lib_usub64.c index 49742ac27d..5b1deaa77b 100644 --- a/libc/misc/lib_usub64.c +++ b/libc/misc/lib_usub64.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/fixedmath/lib_usub64.c + * libc/misc/lib_usub64.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/misc/lib_usub64x32.c b/libc/misc/lib_usub64x32.c index 7bda326e2a..5996c35b30 100644 --- a/libc/misc/lib_usub64x32.c +++ b/libc/misc/lib_usub64x32.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/fixedmath/lib_usub64x32.c + * libc/misc/lib_usub64x32.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt -- GitLab From c5d14f949664a687d7f10e42e5ea67c1836075be Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 17 Oct 2016 10:45:21 -0600 Subject: [PATCH 097/734] Xtensa: A few changes to get esp32_start.c to compile --- arch/xtensa/src/Makefile | 15 ++-- arch/xtensa/src/common/xtensa.h | 4 +- arch/xtensa/src/esp32/Kconfig | 4 +- arch/xtensa/src/esp32/Make.defs | 5 +- .../chip/{xtensa_dport.h => esp32_dport.h} | 8 +-- .../{xtensa_rtccntl.h => esp32_rtccntl.h} | 11 +-- .../esp32/chip/{xtensa_soc.h => esp32_soc.h} | 18 ++--- arch/xtensa/src/esp32/esp32_clockconfig.h | 63 +++++++++++++++++ arch/xtensa/src/esp32/esp32_start.c | 10 +-- arch/xtensa/src/esp32/esp32_start.h | 69 +++++++++++++++++++ 10 files changed, 168 insertions(+), 39 deletions(-) rename arch/xtensa/src/esp32/chip/{xtensa_dport.h => esp32_dport.h} (99%) rename arch/xtensa/src/esp32/chip/{xtensa_rtccntl.h => esp32_rtccntl.h} (99%) rename arch/xtensa/src/esp32/chip/{xtensa_soc.h => esp32_soc.h} (98%) create mode 100644 arch/xtensa/src/esp32/esp32_clockconfig.h create mode 100644 arch/xtensa/src/esp32/esp32_start.h diff --git a/arch/xtensa/src/Makefile b/arch/xtensa/src/Makefile index 0e22a4e010..e6f288ebc5 100644 --- a/arch/xtensa/src/Makefile +++ b/arch/xtensa/src/Makefile @@ -68,8 +68,9 @@ else endif endif -HEAD_OBJ = $(HEAD_ASRC:.S=$(OBJEXT)) -STARTUP_OBJS ?= $(HEAD_OBJ) +HEAD_AOBJ = $(HEAD_ASRC:.S=$(OBJEXT)) +HEAD_COBJ = $(HEAD_CSRC:.c=$(OBJEXT)) +STARTUP_OBJS ?= $(HEAD_AOBJ) $(HEAD_COBJ) ASRCS = $(CHIP_ASRCS) $(CMN_ASRCS) AOBJS = $(ASRCS:.S=$(OBJEXT)) @@ -122,14 +123,14 @@ LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" VPATH = chip:common:$(ARCH_SUBDIR) -all: $(HEAD_OBJ) libarch$(LIBEXT) +all: $(STARTUP_OBJS) libarch$(LIBEXT) .PHONY: board/libboard$(LIBEXT) -$(AOBJS) $(HEAD_OBJ): %$(OBJEXT): %.S +$(AOBJS) $(HEAD_AOBJ): %$(OBJEXT): %.S $(call ASSEMBLE, $<, $@) -$(COBJS): %$(OBJEXT): %.c +$(COBJS) $(HEAD_COBJ): %$(OBJEXT): %.c $(call COMPILE, $<, $@) libarch$(LIBEXT): $(OBJS) @@ -138,9 +139,9 @@ libarch$(LIBEXT): $(OBJS) board/libboard$(LIBEXT): $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" libboard$(LIBEXT) EXTRADEFINES=$(EXTRADEFINES) -nuttx$(EXEEXT): $(HEAD_OBJ) board/libboard$(LIBEXT) +nuttx$(EXEEXT): $(STARTUP_OBJS) board/libboard$(LIBEXT) @echo "LD: nuttx" - $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) -o $(NUTTX)$(EXEEXT) $(HEAD_OBJ) $(EXTRA_OBJS) \ + $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) -o $(NUTTX)$(EXEEXT) $(STARTUP_OBJS) $(EXTRA_OBJS) \ $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) $(LDENDGROUP) ifneq ($(CONFIG_WINDOWS_NATIVE),y) $(Q) $(NM) $(NUTTX)$(EXEEXT) | \ diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index 849500863c..5d4a65f788 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -164,6 +164,7 @@ extern void g_intstackbase; * of _data. like: uint32_t *pdata = &_sdata; */ +extern uint32_t _init_start; /* Start of initialization logic */ extern uint32_t _stext; /* Start of .text */ extern uint32_t _etext; /* End+1 of .text + .rodata */ extern const uint32_t _data_loaddr; /* Start of .data in FLASH */ @@ -176,9 +177,6 @@ extern uint32_t _sramfunc; /* Start of ramfuncs */ extern uint32_t _eramfunc; /* End+1 of ramfuncs */ extern uint32_t _ramfunc_loadaddr; /* Start of ramfuncs in FLASH */ extern uint32_t _ramfunc_sizeof; /* Size of ramfuncs */ -extern uint32_t _bmxdkpba_address; /* BMX register setting */ -extern uint32_t _bmxdudba_address; /* BMX register setting */ -extern uint32_t _bmxdupba_address; /* BMX register setting */ #endif /* CONFIG_ARCH_RAMFUNCS */ #endif /* __ASSEMBLY__ */ diff --git a/arch/xtensa/src/esp32/Kconfig b/arch/xtensa/src/esp32/Kconfig index 8ccb4fe392..956d57c47b 100644 --- a/arch/xtensa/src/esp32/Kconfig +++ b/arch/xtensa/src/esp32/Kconfig @@ -3,7 +3,7 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -if ARCH_LX6 +if ARCH_CHIP_ESP32 -endif # ARCH_LX6 +endif # ARCH_CHIP_ESP32 diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 71f583227c..4bda2cd0ab 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -33,9 +33,10 @@ # ############################################################################ -# The start-up, "head", file +# The start-up, "head", file. May be either a .S or a .c file. -HEAD_ASRC = esp32_start.c +HEAD_ASRC = +HEAD_CSRC = esp32_start.c # Common XTENSA files (arch/xtensa/src/common) diff --git a/arch/xtensa/src/esp32/chip/xtensa_dport.h b/arch/xtensa/src/esp32/chip/esp32_dport.h similarity index 99% rename from arch/xtensa/src/esp32/chip/xtensa_dport.h rename to arch/xtensa/src/esp32/chip/esp32_dport.h index 85a145fe92..0dcf98b626 100644 --- a/arch/xtensa/src/esp32/chip/xtensa_dport.h +++ b/arch/xtensa/src/esp32/chip/esp32_dport.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/common/exp32_dport.h + * arch/xtensa/src/common/esp32_dport.h * * Adapted from use in NuttX by: * @@ -24,8 +24,8 @@ * ****************************************************************************/ -#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_XTENSA_DPORT_H -#define __ARCH_XTENSA_SRC_ESP32_CHIP_XTENSA_DPORT_H +#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_DPORT_H +#define __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_DPORT_H /**************************************************************************** * Included Files @@ -3851,4 +3851,4 @@ #define DPORT_DATE_S 0 #define DPORT_DPORT_DATE_VERSION 0x1605190 -#endif /*__ARCH_XTENSA_SRC_ESP32_CHIP_XTENSA_DPORT_H */ +#endif /*__ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_DPORT_H */ diff --git a/arch/xtensa/src/esp32/chip/xtensa_rtccntl.h b/arch/xtensa/src/esp32/chip/esp32_rtccntl.h similarity index 99% rename from arch/xtensa/src/esp32/chip/xtensa_rtccntl.h rename to arch/xtensa/src/esp32/chip/esp32_rtccntl.h index f79fa9aa88..12f5ba07a9 100644 --- a/arch/xtensa/src/esp32/chip/xtensa_rtccntl.h +++ b/arch/xtensa/src/esp32/chip/esp32_rtccntl.h @@ -24,8 +24,8 @@ * ****************************************************************************/ -#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_XTENSA_RTCCNTL_H -#define __ARCH_XTENSA_SRC_ESP32_CHIP_XTENSA_RTCCNTL_H +#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_XTENSA_ESP32_H +#define __ARCH_XTENSA_SRC_ESP32_CHIP_XTENSA_ESP32_H /**************************************************************************** * Included Files @@ -2001,9 +2001,4 @@ #define RTC_CNTL_CNTL_DATE_S 0 #define RTC_CNTL_RTC_CNTL_DATE_VERSION 0x1604280 - - - -#endif /*__ARCH_XTENSA_SRC_ESP32_CHIP_XTENSA_RTCCNTL_H */ - - +#endif /*__ARCH_XTENSA_SRC_ESP32_CHIP_XTENSA_ESP32_H */ diff --git a/arch/xtensa/src/esp32/chip/xtensa_soc.h b/arch/xtensa/src/esp32/chip/esp32_soc.h similarity index 98% rename from arch/xtensa/src/esp32/chip/xtensa_soc.h rename to arch/xtensa/src/esp32/chip/esp32_soc.h index 99e3600284..6760b1509e 100644 --- a/arch/xtensa/src/esp32/chip/xtensa_soc.h +++ b/arch/xtensa/src/esp32/chip/esp32_soc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/common/xtensa_att.h + * arch/xtensa/src/esp32/chip/esp32_soc.h * * Adapted from use in NuttX by: * @@ -19,12 +19,12 @@ * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and - * limitations under the License./* + * limitations under the License. * ****************************************************************************/ -#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_ATTR_H -#define __ARCH_XTENSA_SRC_COMMON_XTENSA_ATTR_H +#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_SOC_H +#define __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_SOC_H /**************************************************************************** * Included Files @@ -125,7 +125,7 @@ #define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) -/* Set field value to a variable, used when _f is left shifted by _f##_S +/* Set field value to a variable, used when _f is left shifted by _f##_S */ #define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) @@ -149,11 +149,11 @@ #define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))) -/* Set bits of register controlled by mask +/* Set bits of register controlled by mask */ -#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))) +#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))) */ -/* Get bits of register controlled by mask +/* Get bits of register controlled by mask */ #define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask)) @@ -353,4 +353,4 @@ /* Other interrupt numbers should be managed by the user */ -#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_ATTR_H */ +#endif /* __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_SOC_H */ diff --git a/arch/xtensa/src/esp32/esp32_clockconfig.h b/arch/xtensa/src/esp32/esp32_clockconfig.h new file mode 100644 index 0000000000..a552f9b33d --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_clockconfig.h @@ -0,0 +1,63 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_clockconfig.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt > + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_CLOCKCONFIG_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_CLOCKCONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_clockconfig + * + * Description: + * Called to initialize the ESP32. This does whatever setup is needed to + * put the SoC in a usable state. This includes the initialization of + * clocking using the settings in board.h. + * + ****************************************************************************/ + +void esp32_clockconfig(void); + +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_CLOCKCONFIG_H */ diff --git a/arch/xtensa/src/esp32/esp32_start.c b/arch/xtensa/src/esp32/esp32_start.c index e78c0cff17..b7c37b87ad 100644 --- a/arch/xtensa/src/esp32/esp32_start.c +++ b/arch/xtensa/src/esp32/esp32_start.c @@ -37,6 +37,8 @@ #include "xtensa_attr.h" #include "chip/esp32_dport.h" #include "chip/esp32_rtccntl.h" +#include "esp32_clockconfig.h" +#include "esp32_start.h" #include "xtensa.h" #warning REVISIT Need cpu_configure_region_protection() prototype @@ -59,7 +61,7 @@ void cpu_configure_region_protection(void); * ****************************************************************************/ -void IRAM_ATTR __start() +void IRAM_ATTR __start(void) { uint32_t regval; @@ -83,7 +85,7 @@ void IRAM_ATTR __start() /* Set .bss to zero */ - memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start)); + memset(&_sbss, 0, (&_ebss - &_sbss) * sizeof(_sbss)); #warning Missing logic: Initialize .data @@ -98,12 +100,12 @@ void IRAM_ATTR __start() /* Make sure that the APP_CPU is disabled for now */ regval = getreg32(DPORT_APPCPU_CTRL_B_REG); - regval &= ~DPORT_APPCPU_CLKGATE_EN + regval &= ~DPORT_APPCPU_CLKGATE_EN; putreg32(regval, DPORT_APPCPU_CTRL_B_REG); /* Set CPU frequency configured in board.h */ - esp_set_cpu_freq(); + esp32_clockconfig(); #ifdef USE_EARLYSERIALINIT /* Perform early serial initialization */ diff --git a/arch/xtensa/src/esp32/esp32_start.h b/arch/xtensa/src/esp32/esp32_start.h new file mode 100644 index 0000000000..d836f40147 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_start.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_start.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt > + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_START_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_START_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_board_initialize + * + * Description: + * All ESP32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured but before any devices have been initialized. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32_board_initialize(void); + +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_START_H */ -- GitLab From 5354bc1dc753715bd88bef6fce04ae8d01b3fcbe Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Mon, 17 Oct 2016 16:02:08 -0600 Subject: [PATCH 098/734] Add wcslen, wmemchr, wmemcmp, wmemcpy and wmemset to NuttX --- libc/Kconfig | 6 +++ libc/Makefile | 1 + libc/README.txt | 1 + libc/wchar/Make.defs | 43 ++++++++++++++++++++ libc/wchar/lib_wcslen.c | 80 +++++++++++++++++++++++++++++++++++++ libc/wchar/lib_wmemchr.c | 84 +++++++++++++++++++++++++++++++++++++++ libc/wchar/lib_wmemcmp.c | 85 ++++++++++++++++++++++++++++++++++++++++ libc/wchar/lib_wmemcpy.c | 72 ++++++++++++++++++++++++++++++++++ libc/wchar/lib_wmemset.c | 81 ++++++++++++++++++++++++++++++++++++++ 9 files changed, 453 insertions(+) create mode 100644 libc/wchar/Make.defs create mode 100644 libc/wchar/lib_wcslen.c create mode 100644 libc/wchar/lib_wmemchr.c create mode 100644 libc/wchar/lib_wmemcmp.c create mode 100644 libc/wchar/lib_wmemcpy.c create mode 100644 libc/wchar/lib_wmemset.c diff --git a/libc/Kconfig b/libc/Kconfig index 4a2fa5ed49..6df979b0ce 100644 --- a/libc/Kconfig +++ b/libc/Kconfig @@ -104,6 +104,12 @@ config LIBC_IOCTL_VARIADIC this should just result in a garbage value for arg. But you may discover cases where something worse happens! +config LIBC_WCHAR + bool "Enable wide-characters (Unicode) support" + default n + ---help--- + By default, wide-characters support is disabled. + config LIB_RAND_ORDER int "Order of the random number generate" default 1 diff --git a/libc/Makefile b/libc/Makefile index b903fe4737..4df221514c 100644 --- a/libc/Makefile +++ b/libc/Makefile @@ -87,6 +87,7 @@ include termios/Make.defs include time/Make.defs include tls/Make.defs include unistd/Make.defs +include wchar/Make.defs include wqueue/Make.defs # REVISIT: Backslash causes problems in $(COBJS) target diff --git a/libc/README.txt b/libc/README.txt index c964749e28..2e4f902212 100644 --- a/libc/README.txt +++ b/libc/README.txt @@ -44,6 +44,7 @@ we have: string - string.h time - time.h unistd - unistd.h + wchar - wchar.h Most of these are "standard" header files; some are not: hex2bin.h and fixemath.h are non-standard. diff --git a/libc/wchar/Make.defs b/libc/wchar/Make.defs new file mode 100644 index 0000000000..5cf6997007 --- /dev/null +++ b/libc/wchar/Make.defs @@ -0,0 +1,43 @@ +############################################################################ +# libc/wchar/Make.defs +# +# Copyright (C) 2011-2012, 2014, 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# Add the internal C files to the build + +CSRCS += lib_wcslen.c lib_wmemchr.c lib_wmemcmp.c lib_wmemcpy.c lib_wmemset.c + +# Add the wchar directory to the build + +DEPPATH += --dep-path wchar +VPATH += :wchar diff --git a/libc/wchar/lib_wcslen.c b/libc/wchar/lib_wcslen.c new file mode 100644 index 0000000000..be99ccded6 --- /dev/null +++ b/libc/wchar/lib_wcslen.c @@ -0,0 +1,80 @@ + +/**************************************************************************** + * libc/wchar/lib_wcslen.c + * + * Copyright (c)1999 Citrus Project, + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * citrus Id: wcslen.c,v 1.1 1999/12/29 21:47:45 tshiozak Exp + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: wcslen + * + * Description: + * The wcslen() function is the wide-character equivalent of the strlen() + * function. It determines the length of the wide-character string pointed + * to by s, excluding the terminating null wide character (L'\0'). + * + ****************************************************************************/ + +#ifdef CONFIG_LIBC_WCHAR +size_t wcslen(FAR const wchar_t * s) +{ + const wchar_t *p; + + p = s; + while (*p) + { + p++; + } + + return p - s; +} +#endif diff --git a/libc/wchar/lib_wmemchr.c b/libc/wchar/lib_wmemchr.c new file mode 100644 index 0000000000..696de1abf9 --- /dev/null +++ b/libc/wchar/lib_wmemchr.c @@ -0,0 +1,84 @@ + +/**************************************************************************** + * libc/wchar/lib_wmemchr.c + * + * Copyright (c)1999 Citrus Project, + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * citrus Id: wmemchr.c,v 1.2 2000/12/20 14:08:31 itojun Exp + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: wmemchr + * + * Description: + * The wmemchr() function is the wide-character equivalent of the memchr() + * function. It searches the n wide characters starting at s for the first + * occurrence of the wide character c. + * + ****************************************************************************/ + +#ifdef CONFIG_LIBC_WCHAR +FAR wchar_t *wmemchr(FAR wchar_t * s, wchar_t c, size_t n) +{ + size_t i; + + for (i = 0; i < n; i++) + { + if (*s == c) + { + /* LINTED const castaway */ + return (wchar_t *) s; + } + s++; + } + + return NULL; +} +#endif diff --git a/libc/wchar/lib_wmemcmp.c b/libc/wchar/lib_wmemcmp.c new file mode 100644 index 0000000000..223c3eefc8 --- /dev/null +++ b/libc/wchar/lib_wmemcmp.c @@ -0,0 +1,85 @@ + +/**************************************************************************** + * libc/wchar/lib_wmemcmp.c + * + * Copyright (c)1999 Citrus Project, + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * citrus Id: wmemcmp.c,v 1.2 2000/12/20 14:08:31 itojun Exp + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: wmemcmp + * + * Description: + * The wmemcmp() function is the wide-character equivalent of the memcmp() + * function. It compares the n wide-characters starting at s1 and the n + * wide-characters starting at s2. + * + ****************************************************************************/ + +#ifdef CONFIG_LIBC_WCHAR +int wmemcmp(FAR const wchar_t * s1, FAR const wchar_t * s2, size_t n) +{ + size_t i; + + for (i = 0; i < n; i++) + { + if (*s1 != *s2) + { + /* wchar might be unsigned */ + return *s1 > *s2 ? 1 : -1; + } + s1++; + s2++; + } + + return 0; +} +#endif diff --git a/libc/wchar/lib_wmemcpy.c b/libc/wchar/lib_wmemcpy.c new file mode 100644 index 0000000000..e5e6b926e7 --- /dev/null +++ b/libc/wchar/lib_wmemcpy.c @@ -0,0 +1,72 @@ + +/**************************************************************************** + * libc/wchar/lib_wmemcpy.c + * + * Copyright (c)1999 Citrus Project, + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * citrus Id: wmemcpy.c,v 1.2 2000/12/20 14:08:31 itojun Exp + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: wmemcpy + * + * Description: + * This function is the wide-character equivalent of the memcpy function. + * It copies n wide characters from the array starting at src to the array + * starting at dest. The arrays may not overlap. + * + ****************************************************************************/ + +#ifdef CONFIG_LIBC_WCHAR +wchar_t *wmemcpy(FAR wchar_t * d, FAR wchar_t * s, size_t n) +{ + return (wchar_t *) memcpy(d, s, n * sizeof(wchar_t)); +} +#endif diff --git a/libc/wchar/lib_wmemset.c b/libc/wchar/lib_wmemset.c new file mode 100644 index 0000000000..0deba00f4c --- /dev/null +++ b/libc/wchar/lib_wmemset.c @@ -0,0 +1,81 @@ + +/**************************************************************************** + * libc/wchar/lib_wmemset.c + * + * Copyright (c)1999 Citrus Project, + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * citrus Id: wmemset.c,v 1.2 2000/12/20 14:08:31 itojun Exp + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: wmemset + * + * Description: + * The wmemset() function is the wide-character equivalent of the memset() + * function. It fills the array of n wide-characters starting at s with n + * copies of the wide character c. + * + ****************************************************************************/ + +#ifdef CONFIG_LIBC_WCHAR +FAR wchar_t *wmemset(FAR wchar_t * s, wchar_t c, size_t n) +{ + size_t i; + wchar_t *p; + + p = (wchar_t *) s; + for (i = 0; i < n; i++) + { + *p = c; + p++; + } + + return s; +} +#endif -- GitLab From 0249f3271e382e64aa311c2cddbe6cbb043c90bb Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 17 Oct 2016 17:15:19 -0600 Subject: [PATCH 099/734] C library: Add setlocale to libc.csv --- libc/libc.csv | 1 + 1 file changed, 1 insertion(+) diff --git a/libc/libc.csv b/libc/libc.csv index 7fbbf47e0e..3cdfa73c9e 100644 --- a/libc/libc.csv +++ b/libc/libc.csv @@ -109,6 +109,7 @@ "sem_getvalue","semaphore.h","","int","FAR sem_t *","FAR int *" "sem_init","semaphore.h","","int","FAR sem_t *","int","unsigned int" "sendfile","sys/sendfile.h","CONFIG_NSOCKET_DESCRIPTORS > 0 || CONFIG_NFILE_DESCRIPTORS > 0","ssize_t","int","int","off_t","size_t" +"setlocale","local.h","","FAR char *s","int","FAR const char *s" "setlogmask","syslog.h","","int","int" "sigaddset","signal.h","!defined(CONFIG_DISABLE_SIGNALS)","int","FAR sigset_t *","int" "sigdelset","signal.h","!defined(CONFIG_DISABLE_SIGNALS)","int","FAR sigset_t *","int" -- GitLab From 626408bc29c9e380230769c6ce9838686a5f84d7 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 18 Oct 2016 07:52:22 -0600 Subject: [PATCH 100/734] C Library: Add clocale header file --- include/cxx/clocale | 54 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 include/cxx/clocale diff --git a/include/cxx/clocale b/include/cxx/clocale new file mode 100644 index 0000000000..c99e456567 --- /dev/null +++ b/include/cxx/clocale @@ -0,0 +1,54 @@ +//*************************************************************************** +// include/cxx/clocale +// +// Copyright (C) 2016 Gregory Nutt. All rights reserved. +// Author: Gregory Nutt +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// 3. Neither the name NuttX nor the names of its contributors may be +// used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +// AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +// LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +// ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +//*************************************************************************** + +#ifndef __INCLUDE_CXX_CLOCALE +#define __INCLUDE_CXX_CLOCALE + +//*************************************************************************** +// Included Files +//*************************************************************************** + +#include + +//*************************************************************************** +// Namespace +//*************************************************************************** + +namespace std +{ + using ::setlocale; +} + +#endif // __INCLUDE_CXX_CLOCALE -- GitLab From f01c5b79fc8c27fac9be9ec3606661bb9bdf4591 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Tue, 18 Oct 2016 08:05:28 -0600 Subject: [PATCH 101/734] C library: Add functions btowc, mbrtowc, mbtowc, wcscmp, wcscoll, wmemmove --- libc/libc.csv | 10 +++++ libc/wchar/Make.defs | 4 +- libc/wchar/lib_btowc.c | 76 ++++++++++++++++++++++++++++++++++++++ libc/wchar/lib_mbrtowc.c | 77 +++++++++++++++++++++++++++++++++++++++ libc/wchar/lib_mbtowc.c | 71 ++++++++++++++++++++++++++++++++++++ libc/wchar/lib_wcscmp.c | 70 +++++++++++++++++++++++++++++++++++ libc/wchar/lib_wcscoll.c | 63 ++++++++++++++++++++++++++++++++ libc/wchar/lib_wcslen.c | 22 +++-------- libc/wchar/lib_wmemchr.c | 25 +++---------- libc/wchar/lib_wmemcmp.c | 24 +++--------- libc/wchar/lib_wmemcpy.c | 24 +++--------- libc/wchar/lib_wmemmove.c | 58 +++++++++++++++++++++++++++++ libc/wchar/lib_wmemset.c | 27 ++++---------- 13 files changed, 457 insertions(+), 94 deletions(-) create mode 100644 libc/wchar/lib_btowc.c create mode 100644 libc/wchar/lib_mbrtowc.c create mode 100644 libc/wchar/lib_mbtowc.c create mode 100644 libc/wchar/lib_wcscmp.c create mode 100644 libc/wchar/lib_wcscoll.c create mode 100644 libc/wchar/lib_wmemmove.c diff --git a/libc/libc.csv b/libc/libc.csv index 3cdfa73c9e..327b796d32 100644 --- a/libc/libc.csv +++ b/libc/libc.csv @@ -65,6 +65,8 @@ "lio_listio","aio.h","defined(CONFIG_FS_AIO)","int","int","FAR struct aiocb *const []|FAR struct aiocb *const *","int","FAR struct sigevent *" "llabs","stdlib.h","defined(CONFIG_HAVE_LONG_LONG)","long long int","long long int" "match","nuttx/lib/regex.h","","int","const char *","const char *" +"mbrtowc","wchar.h",""defined(CONFIG_LIBC_WCHAR)","size_t","wchar_t *","const char *", "size_t", "mbstate_t *" +"mbtowc","wchar.h",""defined(CONFIG_LIBC_WCHAR)","int","wchar_t *","const wchar_t *", "size_t" "memccpy","string.h","","FAR void","FAR void *","FAR const void *","int c","size_t" "memchr","string.h","","FAR void","FAR const void *","int c","size_t" "memcmp","string.h","","int","FAR const void *","FAR const void *","size_t" @@ -174,4 +176,12 @@ "vsprintf","stdio.h","","int","FAR char *","const char *","va_list" "vsscanf","stdio.h","","int","char *","const char *","va_list" "vsyslog","syslog.h","","int","int","FAR const char *","va_list" +"wcscmp","wchar.h","defined(CONFIG_LIBC_WCHAR)","int", "const wchar_t *", "const wchar_t *" +"wcscoll","wchar.h","defined(CONFIG_LIBC_WCHAR)","int", "const wchar_t *", "const wchar_t *" +"wcslen","wchar.h","defined(CONFIG_LIBC_WCHAR)","size_t", "const wchar_t *" +"wmemchr","wchar.h","defined(CONFIG_LIBC_WCHAR)","wchar_t *", "wchar_t *", "wchar_t", "size_t" +"wmemcmp","wchar.h","defined(CONFIG_LIBC_WCHAR)","int", "wchar_t *", "wchar_t *", "size_t" +"wmemcpy","wchar.h","defined(CONFIG_LIBC_WCHAR)","wchat_t *", "wchar_t *", "wchar_t *", "size_t" +"wmemmove","wchar.h","defined(CONFIG_LIBC_WCHAR)","wchat_t *", "wchar_t *", "wchar_t *", "size_t" +"wmemset","wchar.h","defined(CONFIG_LIBC_WCHAR)","wchat_t *", "wchar_t *", "wchar_t", "size_t" "_warn","debug.h","!defined(CONFIG_CPP_HAVE_VARARGS) && defined(CONFIG_DEBUG_WARN)","int","const char *","..." diff --git a/libc/wchar/Make.defs b/libc/wchar/Make.defs index 5cf6997007..45936e895b 100644 --- a/libc/wchar/Make.defs +++ b/libc/wchar/Make.defs @@ -35,9 +35,11 @@ # Add the internal C files to the build -CSRCS += lib_wcslen.c lib_wmemchr.c lib_wmemcmp.c lib_wmemcpy.c lib_wmemset.c +CSRCS += lib_wcscmp.c lib_wcslen.c lib_wmemchr.c lib_wmemcmp.c lib_wmemcpy.c +CSRCS += lib_wmemmove.c lib_wmemset.c lib_mbtowc.c lib_btowc.c lib_mbrtowc.c # Add the wchar directory to the build DEPPATH += --dep-path wchar VPATH += :wchar + diff --git a/libc/wchar/lib_btowc.c b/libc/wchar/lib_btowc.c new file mode 100644 index 0000000000..7314294699 --- /dev/null +++ b/libc/wchar/lib_btowc.c @@ -0,0 +1,76 @@ +/**************************************************************************** + * libc/wchar/lib_btowc.c + * + * Copyright (c)1999 Citrus Project, + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: btowc + * + * Description: + * Minimal byte to wide char converter + * + ****************************************************************************/ + +#ifdef CONFIG_LIBC_WCHAR +wint_t btowc(int c) +{ + int retval = 0; + wchar_t pwc; + unsigned char b; + + if (c == EOF) + { + return WEOF; + } + + b = (unsigned char)c; + + retval = mbtowc(&pwc, &b, 1); + + if (retval != 0 && retval != 1) + { + return WEOF; + } + + return (wint_t)pwc; +} +#endif diff --git a/libc/wchar/lib_mbrtowc.c b/libc/wchar/lib_mbrtowc.c new file mode 100644 index 0000000000..09887b77e0 --- /dev/null +++ b/libc/wchar/lib_mbrtowc.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * libc/wchar/lib_mbrtowc.c + * + * Copyright (c)1999 Citrus Project, + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mbrtowc + * + * Description: + * Convert a multibyte sequence to a wide character + * + ****************************************************************************/ + +#ifdef CONFIG_LIBC_WCHAR +size_t mbrtowc(FAR wchar_t *pwc, FAR const char *s, size_t n, mbstate_t *ps) +{ + int retval = 0; + + if (s == NULL) + { + retval = mbtowc(NULL, "", 1); + } + else + { + retval = mbtowc(pwc, s, n); + } + + if (retval == -1) + { + return (size_t) (-1); + } + else + { + return (size_t) retval; + } +} +#endif diff --git a/libc/wchar/lib_mbtowc.c b/libc/wchar/lib_mbtowc.c new file mode 100644 index 0000000000..5e50d86b28 --- /dev/null +++ b/libc/wchar/lib_mbtowc.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * libc/wchar/lib_mbtowc.c + * + * Copyright (c)1999 Citrus Project, + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mbtowc.c + * + * Description: + * Minimal multibyte to wide char converter + * + ****************************************************************************/ + +#ifdef CONFIG_LIBC_WCHAR +int mbtowc(FAR wchar_t * pwc, FAR const char *s, size_t n) +{ + if (s == NULL) + { + return 0; + } + + if (n == 0) + { + return -1; + } + + if (pwc) + { + *pwc = (wchar_t) * s; + } + + return (*s != '\0'); +} +#endif diff --git a/libc/wchar/lib_wcscmp.c b/libc/wchar/lib_wcscmp.c new file mode 100644 index 0000000000..72e6bb3565 --- /dev/null +++ b/libc/wchar/lib_wcscmp.c @@ -0,0 +1,70 @@ +/**************************************************************************** + * libc/wchar/lib_wcscmp.c + * + * This code is derived from software contributed to Berkeley by + * Chris Torek. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: wcscmp + * + * Description: + * The wcscmp() function returns zero if the wide-character strings at s1 + * and s2 are equal. It returns an integer greater than zero if at the first + * differing position i, the corresponding wide-character s1[i] is greater + * than s2[i]. It returns an integer less than zero if at the first differ- + * ing position i, the corresponding wide-character s1[i] is less than s2[i] + * + ****************************************************************************/ + +#ifdef CONFIG_LIBC_WCHAR +int wcscmp(FAR const wchar_t *s1, FAR const wchar_t *s2) +{ + while (*s1 == *s2++) + { + if (*s1++ == 0) + { + return (0); + } + } + + return (*s1 - *--s2); +} +#endif diff --git a/libc/wchar/lib_wcscoll.c b/libc/wchar/lib_wcscoll.c new file mode 100644 index 0000000000..9bdc727d21 --- /dev/null +++ b/libc/wchar/lib_wcscoll.c @@ -0,0 +1,63 @@ +/**************************************************************************** + * libc/wchar/lib_wcscoll.c + * + * This code is derived from software contributed to Berkeley by + * Chris Torek. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: wcscoll + * + * Description: + * The wcscoll() compares the wide-character string pointed to by a to the + * wide-character string pointed to by b using an interpretation appropriate + * to the current LC_COLLATE state. + * + * The current implementation of wcscoll() simply uses wcscmp() and does + * not support any language-specific sorting. + * + ****************************************************************************/ + +#ifdef CONFIG_LIBC_WCHAR +int wcscoll(FAR const wchar_t *a, FAR const wchar_t *b) +{ + return wcscmp(a, b); +} +#endif diff --git a/libc/wchar/lib_wcslen.c b/libc/wchar/lib_wcslen.c index be99ccded6..f5a4d18afc 100644 --- a/libc/wchar/lib_wcslen.c +++ b/libc/wchar/lib_wcslen.c @@ -1,13 +1,13 @@ - /**************************************************************************** * libc/wchar/lib_wcslen.c * - * Copyright (c)1999 Citrus Project, - * All rights reserved. + * Copyright (c)1999 Citrus Project, + * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: + * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright @@ -38,18 +38,6 @@ #include #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -65,9 +53,9 @@ ****************************************************************************/ #ifdef CONFIG_LIBC_WCHAR -size_t wcslen(FAR const wchar_t * s) +size_t wcslen(FAR const wchar_t *s) { - const wchar_t *p; + FAR const wchar_t *p; p = s; while (*p) diff --git a/libc/wchar/lib_wmemchr.c b/libc/wchar/lib_wmemchr.c index 696de1abf9..732c4ca019 100644 --- a/libc/wchar/lib_wmemchr.c +++ b/libc/wchar/lib_wmemchr.c @@ -1,13 +1,13 @@ - /**************************************************************************** * libc/wchar/lib_wmemchr.c * - * Copyright (c)1999 Citrus Project, - * All rights reserved. + * Copyright (c)1999 Citrus Project, + * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: + * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright @@ -26,8 +26,6 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * citrus Id: wmemchr.c,v 1.2 2000/12/20 14:08:31 itojun Exp - * ****************************************************************************/ /**************************************************************************** @@ -38,18 +36,6 @@ #include #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -65,7 +51,7 @@ ****************************************************************************/ #ifdef CONFIG_LIBC_WCHAR -FAR wchar_t *wmemchr(FAR wchar_t * s, wchar_t c, size_t n) +FAR wchar_t *wmemchr(FAR wchar_t *s, wchar_t c, size_t n) { size_t i; @@ -74,7 +60,8 @@ FAR wchar_t *wmemchr(FAR wchar_t * s, wchar_t c, size_t n) if (*s == c) { /* LINTED const castaway */ - return (wchar_t *) s; + + return (FAR wchar_t *) s; } s++; } diff --git a/libc/wchar/lib_wmemcmp.c b/libc/wchar/lib_wmemcmp.c index 223c3eefc8..134f69e0d1 100644 --- a/libc/wchar/lib_wmemcmp.c +++ b/libc/wchar/lib_wmemcmp.c @@ -1,13 +1,13 @@ - /**************************************************************************** * libc/wchar/lib_wmemcmp.c * - * Copyright (c)1999 Citrus Project, - * All rights reserved. + * Copyright (c)1999 Citrus Project, + * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: + * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright @@ -26,8 +26,6 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * citrus Id: wmemcmp.c,v 1.2 2000/12/20 14:08:31 itojun Exp - * ****************************************************************************/ /**************************************************************************** @@ -38,18 +36,6 @@ #include #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -65,7 +51,7 @@ ****************************************************************************/ #ifdef CONFIG_LIBC_WCHAR -int wmemcmp(FAR const wchar_t * s1, FAR const wchar_t * s2, size_t n) +int wmemcmp(FAR const wchar_t *s1, FAR const wchar_t *s2, size_t n) { size_t i; @@ -74,8 +60,10 @@ int wmemcmp(FAR const wchar_t * s1, FAR const wchar_t * s2, size_t n) if (*s1 != *s2) { /* wchar might be unsigned */ + return *s1 > *s2 ? 1 : -1; } + s1++; s2++; } diff --git a/libc/wchar/lib_wmemcpy.c b/libc/wchar/lib_wmemcpy.c index e5e6b926e7..8a28173c7f 100644 --- a/libc/wchar/lib_wmemcpy.c +++ b/libc/wchar/lib_wmemcpy.c @@ -1,13 +1,13 @@ - /**************************************************************************** * libc/wchar/lib_wmemcpy.c * - * Copyright (c)1999 Citrus Project, - * All rights reserved. + * Copyright (c)1999 Citrus Project, + * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: + * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright @@ -26,8 +26,6 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * citrus Id: wmemcpy.c,v 1.2 2000/12/20 14:08:31 itojun Exp - * ****************************************************************************/ /**************************************************************************** @@ -38,18 +36,6 @@ #include #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -65,8 +51,8 @@ ****************************************************************************/ #ifdef CONFIG_LIBC_WCHAR -wchar_t *wmemcpy(FAR wchar_t * d, FAR wchar_t * s, size_t n) +FAR wchar_t *wmemcpy(FAR wchar_t *d, FAR wchar_t *s, size_t n) { - return (wchar_t *) memcpy(d, s, n * sizeof(wchar_t)); + return (FAR wchar_t *) memcpy(d, s, n * sizeof(wchar_t)); } #endif diff --git a/libc/wchar/lib_wmemmove.c b/libc/wchar/lib_wmemmove.c new file mode 100644 index 0000000000..3ce34272f3 --- /dev/null +++ b/libc/wchar/lib_wmemmove.c @@ -0,0 +1,58 @@ +/**************************************************************************** + * libc/wchar/lib_wmemmove.c + * + * Copyright (c)1999 Citrus Project, + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: wmemmove + * + * Description: + * The wmemmove() function is the wide-character equivalent of the memmove() + * function. It copies n wide characters from the array starting at src to + * the array starting at dest. The arrays may overlap. + * + ****************************************************************************/ + +#ifdef CONFIG_LIBC_WCHAR +FAR wchar_t *wmemmove(FAR wchar_t *d, FAR const wchar_t *s, size_t n) +{ + return (FAR wchar_t *) memmove(d, s, n * sizeof(wchar_t)); +} +#endif diff --git a/libc/wchar/lib_wmemset.c b/libc/wchar/lib_wmemset.c index 0deba00f4c..8eea8a23ed 100644 --- a/libc/wchar/lib_wmemset.c +++ b/libc/wchar/lib_wmemset.c @@ -1,13 +1,13 @@ - /**************************************************************************** * libc/wchar/lib_wmemset.c * - * Copyright (c)1999 Citrus Project, - * All rights reserved. + * Copyright (c)1999 Citrus Project, + * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: + * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright @@ -26,8 +26,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * citrus Id: wmemset.c,v 1.2 2000/12/20 14:08:31 itojun Exp - */ + ****************************************************************************/ /**************************************************************************** * Included Files @@ -37,18 +36,6 @@ #include #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -64,12 +51,12 @@ ****************************************************************************/ #ifdef CONFIG_LIBC_WCHAR -FAR wchar_t *wmemset(FAR wchar_t * s, wchar_t c, size_t n) +FAR wchar_t *wmemset(FAR wchar_t *s, wchar_t c, size_t n) { + FAR wchar_t *p; size_t i; - wchar_t *p; - p = (wchar_t *) s; + p = (FAR wchar_t *) s; for (i = 0; i < n; i++) { *p = c; -- GitLab From 72f13db4bf7be0792b83bdbd44557ed0d5aeff20 Mon Sep 17 00:00:00 2001 From: Janne Rosberg Date: Tue, 18 Oct 2016 08:15:19 -0600 Subject: [PATCH 102/734] usbhost/enumerate: fix possible buffer overwrite --- drivers/usbhost/usbhost_enumerate.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/usbhost/usbhost_enumerate.c b/drivers/usbhost/usbhost_enumerate.c index 80b6d48ff3..01062d077b 100644 --- a/drivers/usbhost/usbhost_enumerate.c +++ b/drivers/usbhost/usbhost_enumerate.c @@ -469,6 +469,14 @@ int usbhost_enumerate(FAR struct usbhost_hubport_s *hport, cfglen = (unsigned int)usbhost_getle16(((struct usb_cfgdesc_s *)buffer)->totallen); uinfo("sizeof config data: %d\n", cfglen); + if (cfglen > maxlen) + { + uerr("ERROR: Configuration doesn't fit in buffer, length=%d, maxlen=%d\n", + cfglen, maxlen); + ret = -E2BIG; + goto errout; + } + /* Get all of the configuration descriptor data, index == 0 (Should not be * hard-coded!) */ -- GitLab From ac97a81fb053ae894b0638145f1dc9acc27d1f7e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 18 Oct 2016 09:43:56 -0600 Subject: [PATCH 103/734] ESP32 core: Add linker script --- arch/xtensa/src/esp32/Kconfig | 13 +- configs/esp32-core/nsh/Make.defs | 2 +- configs/esp32-core/scripts/esp32.ld | 62 + configs/esp32-core/scripts/esp32_common.ld | 179 ++ .../esp32-core/scripts/esp32_peripherals.ld | 24 + configs/esp32-core/scripts/esp32_rom.ld | 1846 +++++++++++++++++ configs/esp32-core/src/Makefile | 8 + 7 files changed, 2132 insertions(+), 2 deletions(-) create mode 100644 configs/esp32-core/scripts/esp32.ld create mode 100644 configs/esp32-core/scripts/esp32_common.ld create mode 100644 configs/esp32-core/scripts/esp32_peripherals.ld create mode 100644 configs/esp32-core/scripts/esp32_rom.ld diff --git a/arch/xtensa/src/esp32/Kconfig b/arch/xtensa/src/esp32/Kconfig index 956d57c47b..5263d6c5b7 100644 --- a/arch/xtensa/src/esp32/Kconfig +++ b/arch/xtensa/src/esp32/Kconfig @@ -5,5 +5,16 @@ if ARCH_CHIP_ESP32 -endif # ARCH_CHIP_ESP32 +config ESP32_BT_RESERVE_DRAM + int "Reserved BT DRAM" + default 0 + +config ESP32_TRACEMEM_RESERVE_DRAM + int "Reserved trace memory DRAM" + default 0 +config ESP32_ULP_COPROC_RESERVE_MEM + int "Reserved ULP co-processor DRAM" + default 0 + +endif # ARCH_CHIP_ESP32 diff --git a/configs/esp32-core/nsh/Make.defs b/configs/esp32-core/nsh/Make.defs index 75a3287f6e..3789e51c7c 100644 --- a/configs/esp32-core/nsh/Make.defs +++ b/configs/esp32-core/nsh/Make.defs @@ -37,7 +37,7 @@ include ${TOPDIR}/.config include ${TOPDIR}/tools/Config.mk include ${TOPDIR}/arch/xtensa/src/lx6/Toolchain.defs -LDSCRIPT = ld.script +LDSCRIPT += -T esp32_out.ld -T esp32_common.ld -T esp32_rom.ld -T esp32_peripherals.ld ifeq ($(WINTOOL),y) # Windows-native toolchains diff --git a/configs/esp32-core/scripts/esp32.ld b/configs/esp32-core/scripts/esp32.ld new file mode 100644 index 0000000000..68c0c73cf8 --- /dev/null +++ b/configs/esp32-core/scripts/esp32.ld @@ -0,0 +1,62 @@ +/**************************************************************************** + * configs/elf32-core/scripts/esp32.ld + * ESP32 Linker Script Memory Layout + * + * This file describes the memory layout (memory blocks) as virtual + * memory addresses. + * + * esp32.common.ld contains output sections to link compiler output + * into these memory blocks. + * + * NOTE: That this is not the actual linker script but rather a "template" + * for the elf32_out.ld script. This template script is passed through + * the C preprocessor to include selected configuration options. + * + ****************************************************************************/ + +#include + +MEMORY +{ + /* All these values assume the flash cache is on, and have the blocks this + * uses subtracted from the length of the various regions. The 'data access + * port' dram/drom regions map to the same iram/irom regions but are + * connected to the data port of the CPU and eg allow bytewise access. + */ + + /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */ + + iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 + + /* Even though the segment name is iram, it is actually mapped to flash */ + + iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 + + /* Shared data RAM, excluding memory reserved for ROM bss/data/stack. + * Enabling Bluetooth & Trace Memory features in menuconfig will decrease + * the amount of RAM available. + */ + + dram0_0_seg (RW) : org = 0x3ffb0000 + CONFIG_ESP32_BT_RESERVE_DRAM, + len = 0x50000 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM - CONFIG_ESP32_BT_RESERVE_DRAM + + /* Flash mapped constant data */ + + drom0_0_seg (R) : org = 0x3f400010, len = 0x800000 + + /* RTC fast memory (executable). Persists over deep sleep. */ + + rtc_iram_seg(RWX) : org = 0x400c0000, len = 0x2000 + + /* RTC slow memory (data accessible). Persists over deep sleep. + * Start of RTC slow memory is reserved for ULP co-processor code + data, + * if enabled. + */ + + rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ESP32_ULP_COPROC_RESERVE_MEM, + len = 0x1000 - CONFIG_ESP32_ULP_COPROC_RESERVE_MEM +} + +/* Heap ends at top of dram0_0_seg */ + +_heap_end = 0x40000000 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM; diff --git a/configs/esp32-core/scripts/esp32_common.ld b/configs/esp32-core/scripts/esp32_common.ld new file mode 100644 index 0000000000..8d7f49a48a --- /dev/null +++ b/configs/esp32-core/scripts/esp32_common.ld @@ -0,0 +1,179 @@ +/**************************************************************************** + * configs/elf32-core/scripts/esp32_common.ld + ****************************************************************************/ + +/* Default entry point: */ + +ENTRY(__start); + +SECTIONS +{ + /* Send .iram0 code to iram */ + + .iram0.vectors : + { + /* Vectors go to IRAM */ + + _init_start = ABSOLUTE(.); + + /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ + + . = 0x0; + KEEP(*(.WindowVectors.text)); + . = 0x180; + KEEP(*(.Level2InterruptVector.text)); + . = 0x1c0; + KEEP(*(.Level3InterruptVector.text)); + . = 0x200; + KEEP(*(.Level4InterruptVector.text)); + . = 0x240; + KEEP(*(.Level5InterruptVector.text)); + . = 0x280; + KEEP(*(.DebugExceptionVector.text)); + . = 0x2c0; + KEEP(*(.NMIExceptionVector.text)); + . = 0x300; + KEEP(*(.KernelExceptionVector.text)); + . = 0x340; + KEEP(*(.UserExceptionVector.text)); + . = 0x3C0; + KEEP(*(.DoubleExceptionVector.text)); + . = 0x400; + *(.*Vector.literal) + + *(.UserEnter.literal); + *(.UserEnter.text); + . = ALIGN (16); + *(.entry.text) + *(.init.literal) + *(.init) + _init_end = ABSOLUTE(.); + } > iram0_0_seg + + .iram0.text : + { + /* Code marked as runnning out of IRAM */ + + _iram_text_start = ABSOLUTE(.); + *(.iram1 .iram1.*) + *libfreertos.a:(.literal .text .literal.* .text.*) + *libphy.a:(.literal .text .literal.* .text.*) + *librtc.a:(.literal .text .literal.* .text.*) + *libpp.a:(.literal .text .literal.* .text.*) + *libhal.a:(.literal .text .literal.* .text.*) + _iram_text_end = ABSOLUTE(.); + } > iram0_0_seg + + /* Shared RAM */ + + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + KEEP(*(.bss)) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + _ebss = ABSOLUTE(.); + } >dram0_0_seg + + .dram0.data : + { + _data_start = ABSOLUTE(.); + KEEP(*(.data)) + KEEP(*(.data.*)) + KEEP(*(.gnu.linkonce.d.*)) + KEEP(*(.data1)) + KEEP(*(.sdata)) + KEEP(*(.sdata.*)) + KEEP(*(.gnu.linkonce.s.*)) + KEEP(*(.sdata2)) + KEEP(*(.sdata2.*)) + KEEP(*(.gnu.linkonce.s2.*)) + KEEP(*(.jcr)) + *(.dram1 .dram1.*) + _data_end = ABSOLUTE(.); + . = ALIGN(4); + _heap_start = ABSOLUTE(.); + } >dram0_0_seg + + .flash.rodata : + { + _rodata_start = ABSOLUTE(.); + *(.rodata) + *(.rodata.*) + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + *(.eh_frame) + . = (. + 3) & ~ 3; + /* C++ constructor and destructor tables, properly ordered: */ + __init_array_start = ABSOLUTE(.); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __init_array_end = ABSOLUTE(.); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _rodata_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + } >drom0_0_seg + + .flash.text : + { + _stext = .; + _text_start = ABSOLUTE(.); + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + _text_end = ABSOLUTE(.); + _etext = .; + } >iram0_2_seg + + .rtc.text : + { + . = ALIGN(4); + *(.rtc.literal .rtc.text) + } >rtc_iram_seg + + .rtc.data : + { + *(.rtc.data) + *(.rtc.rodata) + } > rtc_slow_seg +} diff --git a/configs/esp32-core/scripts/esp32_peripherals.ld b/configs/esp32-core/scripts/esp32_peripherals.ld new file mode 100644 index 0000000000..cabfe4aaa4 --- /dev/null +++ b/configs/esp32-core/scripts/esp32_peripherals.ld @@ -0,0 +1,24 @@ +/**************************************************************************** + * configs/elf32-core/scripts/esp32_peripherals.ld + ****************************************************************************/ + +PROVIDE ( UART0 = 0x3ff40000 ); +PROVIDE ( SPI1 = 0x3ff42000 ); +PROVIDE ( SPI0 = 0x3ff43000 ); +PROVIDE ( GPIO = 0x3ff44000 ); +PROVIDE ( SIGMADELTA = 0x3ff44f00 ); +PROVIDE ( UHCI1 = 0x3ff4C000 ); +PROVIDE ( I2S0 = 0x3ff4F000 ); +PROVIDE ( UART1 = 0x3ff50000 ); +PROVIDE ( I2C0 = 0x3ff53000 ); +PROVIDE ( UHCI0 = 0x3ff54000 ); +PROVIDE ( RMT = 0x3ff56000 ); +PROVIDE ( PCNT = 0x3ff57000 ); +PROVIDE ( LEDC = 0x3ff59000 ); +PROVIDE ( TIMERG0 = 0x3ff5F000 ); +PROVIDE ( TIMERG1 = 0x3ff60000 ); +PROVIDE ( SPI2 = 0x3ff64000 ); +PROVIDE ( SPI3 = 0x3ff65000 ); +PROVIDE ( I2C1 = 0x3ff67000 ); +PROVIDE ( I2S1 = 0x3ff6D000 ); +PROVIDE ( UART2 = 0x3ff6E000 ); diff --git a/configs/esp32-core/scripts/esp32_rom.ld b/configs/esp32-core/scripts/esp32_rom.ld new file mode 100644 index 0000000000..5276fa76c2 --- /dev/null +++ b/configs/esp32-core/scripts/esp32_rom.ld @@ -0,0 +1,1846 @@ +/* +ESP32 ROM address table +Generated for ROM with MD5sum: +ab8282ae908fe9e7a63fb2a4ac2df013 ../../rom_image/prorom.elf +*/ + +PROVIDE ( abort = 0x4000bba4 ); +PROVIDE ( abs = 0x40056340 ); +PROVIDE ( __absvdi2 = 0x4006387c ); +PROVIDE ( __absvsi2 = 0x40063868 ); +PROVIDE ( Add2SelfBigHex256 = 0x40015b7c ); +PROVIDE ( AddBigHex256 = 0x40015b28 ); +PROVIDE ( AddBigHexModP256 = 0x40015c98 ); +PROVIDE ( __adddf3 = 0x40002590 ); +PROVIDE ( AddP256 = 0x40015c74 ); +PROVIDE ( AddPdiv2_256 = 0x40015ce0 ); +PROVIDE ( __addsf3 = 0x400020e8 ); +PROVIDE ( __addvdi3 = 0x40002cbc ); +PROVIDE ( __addvsi3 = 0x40002c98 ); +PROVIDE ( aes_128_cbc_decrypt = 0x4005cc7c ); +PROVIDE ( aes_128_cbc_encrypt = 0x4005cc18 ); +PROVIDE ( aes_unwrap = 0x4005ccf0 ); +PROVIDE ( app_gpio_arg = 0x3ffe003c ); +PROVIDE ( app_gpio_handler = 0x3ffe0040 ); +PROVIDE ( __ascii_wctomb = 0x40058ef0 ); +PROVIDE ( asctime = 0x40059588 ); +PROVIDE ( asctime_r = 0x40000ec8 ); +PROVIDE ( __ashldi3 = 0x4000c818 ); +PROVIDE ( __ashrdi3 = 0x4000c830 ); +PROVIDE ( asiprintf = 0x40056d9c ); +PROVIDE ( _asiprintf_r = 0x40056d4c ); +PROVIDE ( asniprintf = 0x40056cd8 ); +PROVIDE ( _asniprintf_r = 0x40056c64 ); +PROVIDE ( asnprintf = 0x40056cd8 ); +PROVIDE ( _asnprintf_r = 0x40056c64 ); +PROVIDE ( asprintf = 0x40056d9c ); +PROVIDE ( _asprintf_r = 0x40056d4c ); +PROVIDE ( atoi = 0x400566c4 ); +PROVIDE ( _atoi_r = 0x400566d4 ); +PROVIDE ( atol = 0x400566ec ); +PROVIDE ( _atol_r = 0x400566fc ); +PROVIDE ( base64_decode = 0x4005ced8 ); +PROVIDE ( base64_encode = 0x4005cdbc ); +PROVIDE ( BasePoint_x_256 = 0x3ff97488 ); +PROVIDE ( BasePoint_y_256 = 0x3ff97468 ); +PROVIDE ( bigHexInversion256 = 0x400168f0 ); +PROVIDE ( bigHexP256 = 0x3ff973bc ); +PROVIDE ( __bswapdi2 = 0x400649c4 ); +PROVIDE ( __bswapsi2 = 0x4006499c ); +PROVIDE ( btdm_r_ble_bt_handler_tab_p_get = 0x40019b0c ); +PROVIDE ( btdm_r_btdm_option_data_p_get = 0x40010004 ); +PROVIDE ( btdm_r_btdm_rom_version_get = 0x40010078 ); +PROVIDE ( btdm_r_data_init = 0x4001002c ); +PROVIDE ( btdm_r_import_rf_phy_func_p_get = 0x40054298 ); +PROVIDE ( btdm_r_ip_func_p_get = 0x40019af0 ); +PROVIDE ( btdm_r_ip_func_p_set = 0x40019afc ); +PROVIDE ( btdm_r_modules_func_p_get = 0x4005427c ); +PROVIDE ( btdm_r_modules_func_p_set = 0x40054270 ); +PROVIDE ( btdm_r_plf_func_p_set = 0x40054288 ); +PROVIDE ( bt_util_buf_env = 0x3ffb8bd4 ); +PROVIDE ( bzero = 0x4000c1f4 ); +PROVIDE ( cache_flash_mmu_set = 0x400095e0 ); +PROVIDE ( Cache_Flush = 0x40009a14 ); +PROVIDE ( Cache_Read_Disable = 0x40009ab8 ); +PROVIDE ( Cache_Read_Enable = 0x40009a84 ); +PROVIDE ( Cache_Read_Init = 0x40009950 ); +PROVIDE ( cache_sram_mmu_set = 0x400097f4 ); +/* This is static function, but can be used, not generated by script*/ +PROVIDE ( calc_rtc_memory_crc = 0x40008170 ); +PROVIDE ( calloc = 0x4000bee4 ); +PROVIDE ( _calloc_r = 0x4000bbf8 ); +PROVIDE ( check_pos = 0x400068b8 ); +PROVIDE ( _cleanup = 0x40001df8 ); +PROVIDE ( _cleanup_r = 0x40001d48 ); +PROVIDE ( __clear_cache = 0x40063860 ); +PROVIDE ( close = 0x40001778 ); +PROVIDE ( _close_r = 0x4000bd3c ); +PROVIDE ( __clrsbdi2 = 0x40064a38 ); +PROVIDE ( __clrsbsi2 = 0x40064a20 ); +PROVIDE ( __clzdi2 = 0x4000ca50 ); +PROVIDE ( __clzsi2 = 0x4000c7e8 ); +PROVIDE ( __cmpdi2 = 0x40063820 ); +PROVIDE ( co_default_bdaddr = 0x3ffae704 ); +PROVIDE ( co_null_bdaddr = 0x3ffb80e0 ); +PROVIDE ( co_sca2ppm = 0x3ff971e8 ); +PROVIDE ( crc16_be = 0x4005d09c ); +PROVIDE ( crc16_le = 0x4005d05c ); +PROVIDE ( crc32_be = 0x4005d024 ); +PROVIDE ( crc32_le = 0x4005cfec ); +PROVIDE ( crc8_be = 0x4005d114 ); +PROVIDE ( crc8_le = 0x4005d0e0 ); +PROVIDE ( creat = 0x40000e8c ); +PROVIDE ( ctime = 0x400595b0 ); +PROVIDE ( ctime_r = 0x400595c4 ); +PROVIDE ( _ctype_ = 0x3ff96354 ); +PROVIDE ( __ctype_ptr__ = 0x3ff96350 ); +PROVIDE ( __ctzdi2 = 0x4000ca64 ); +PROVIDE ( __ctzsi2 = 0x4000c7f0 ); +PROVIDE ( _data_end = 0x4000d5c8 ); +PROVIDE ( _data_end_btdm_rom = 0x4000d4f8 ); +PROVIDE ( _data_start = 0x4000d4f8 ); +PROVIDE ( _data_start_btdm_rom = 0x4000d4f4 ); +PROVIDE ( _data_start_btdm = 0x3ffae6e0); +PROVIDE ( _data_end_btdm = 0x3ffaff10); +PROVIDE ( _sbss_btdm = 0x3ffb8000); +PROVIDE ( _ebss_btdm = 0x3ffbff70); +PROVIDE ( _daylight = 0x3ffae0a4 ); +PROVIDE ( dbg_default_handler = 0x3ff97218 ); +PROVIDE ( dbg_state = 0x3ffb8d5d ); +PROVIDE ( DebugE256PublicKey_x = 0x3ff97428 ); +PROVIDE ( DebugE256PublicKey_y = 0x3ff97408 ); +PROVIDE ( DebugE256SecretKey = 0x3ff973e8 ); +PROVIDE ( _DebugExceptionVector = 0x40000280 ); +PROVIDE ( debug_timer = 0x3ffe042c ); +PROVIDE ( debug_timerfn = 0x3ffe0430 ); +PROVIDE ( dh_group14_generator = 0x3ff9ac60 ); +PROVIDE ( dh_group14_prime = 0x3ff9ab60 ); +PROVIDE ( dh_group15_generator = 0x3ff9ab5f ); +PROVIDE ( dh_group15_prime = 0x3ff9a9df ); +PROVIDE ( dh_group16_generator = 0x3ff9a9de ); +PROVIDE ( dh_group16_prime = 0x3ff9a7de ); +PROVIDE ( dh_group17_generator = 0x3ff9a7dd ); +PROVIDE ( dh_group17_prime = 0x3ff9a4dd ); +PROVIDE ( dh_group18_generator = 0x3ff9a4dc ); +PROVIDE ( dh_group18_prime = 0x3ff9a0dc ); +PROVIDE ( dh_group1_generator = 0x3ff9ae03 ); +PROVIDE ( dh_group1_prime = 0x3ff9ada3 ); +PROVIDE ( dh_group2_generator = 0x3ff9ada2 ); +PROVIDE ( dh_group2_prime = 0x3ff9ad22 ); +PROVIDE ( dh_group5_generator = 0x3ff9ad21 ); +PROVIDE ( dh_group5_prime = 0x3ff9ac61 ); +PROVIDE ( div = 0x40056348 ); +PROVIDE ( __divdc3 = 0x40064460 ); +PROVIDE ( __divdf3 = 0x40002954 ); +PROVIDE ( __divdi3 = 0x4000ca84 ); +PROVIDE ( __divsc3 = 0x40064200 ); +PROVIDE ( __divsf3 = 0x4000234c ); +PROVIDE ( __divsi3 = 0x4000c7b8 ); +PROVIDE ( _DoubleExceptionVector = 0x400003c0 ); +PROVIDE ( dummy_len_plus = 0x3ffae290 ); +PROVIDE ( __dummy_lock = 0x4000c728 ); +PROVIDE ( __dummy_lock_try = 0x4000c730 ); +PROVIDE ( ecc_env = 0x3ffb8d60 ); +PROVIDE ( ecc_Jacobian_InfinityPoint256 = 0x3ff972e8 ); +PROVIDE ( em_buf_env = 0x3ffb8d74 ); +PROVIDE ( environ = 0x3ffae0b4 ); +PROVIDE ( __env_lock = 0x40001fd4 ); +PROVIDE ( __env_unlock = 0x40001fe0 ); +PROVIDE ( __eqdf2 = 0x400636a8 ); +PROVIDE ( __eqsf2 = 0x40063374 ); +PROVIDE ( esp_crc8 = 0x4005d144 ); +PROVIDE ( _etext = 0x4000d66c ); +PROVIDE ( ets_aes_crypt = 0x4005c9b8 ); +PROVIDE ( ets_aes_disable = 0x4005c8f8 ); +PROVIDE ( ets_aes_enable = 0x4005c8cc ); +PROVIDE ( ets_aes_set_endian = 0x4005c928 ); +PROVIDE ( ets_aes_setkey_dec = 0x4005c994 ); +PROVIDE ( ets_aes_setkey_enc = 0x4005c97c ); +PROVIDE ( ets_bigint_disable = 0x4005c4e0 ); +PROVIDE ( ets_bigint_enable = 0x4005c498 ); +PROVIDE ( ets_bigint_mod_mult_getz = 0x4005c818 ); +PROVIDE ( ets_bigint_mod_mult_prepare = 0x4005c7b4 ); +PROVIDE ( ets_bigint_mod_power_getz = 0x4005c614 ); +PROVIDE ( ets_bigint_mod_power_prepare = 0x4005c54c ); +PROVIDE ( ets_bigint_montgomery_mult_getz = 0x4005c7a4 ); +PROVIDE ( ets_bigint_montgomery_mult_prepare = 0x4005c6fc ); +PROVIDE ( ets_bigint_mult_getz = 0x4005c6e8 ); +PROVIDE ( ets_bigint_mult_prepare = 0x4005c630 ); +PROVIDE ( ets_bigint_wait_finish = 0x4005c520 ); +PROVIDE ( ets_delay_us = 0x40008534 ); +PROVIDE ( ets_efuse_get_8M_clock = 0x40008710 ); +PROVIDE ( ets_efuse_get_spiconfig = 0x40008658 ); +PROVIDE ( ets_efuse_program_op = 0x40008628 ); +PROVIDE ( ets_efuse_read_op = 0x40008600 ); +PROVIDE ( ets_get_cpu_frequency = 0x4000855c ); +PROVIDE ( ets_get_detected_xtal_freq = 0x40008588 ); +PROVIDE ( ets_get_xtal_scale = 0x4000856c ); +PROVIDE ( ets_install_putc1 = 0x40007d18 ); +PROVIDE ( ets_install_putc2 = 0x40007d38 ); +PROVIDE ( ets_install_uart_printf = 0x40007d28 ); +PROVIDE ( ets_intr_count = 0x3ffe03fc ); +PROVIDE ( ets_intr_lock = 0x400067b0 ); +PROVIDE ( ets_intr_unlock = 0x400067c4 ); +PROVIDE ( ets_isr_attach = 0x400067ec ); +PROVIDE ( ets_isr_mask = 0x400067fc ); +PROVIDE ( ets_isr_unmask = 0x40006808 ); +PROVIDE ( ets_post = 0x4000673c ); +PROVIDE ( ets_printf = 0x40007d54 ); +PROVIDE ( ets_readySet_ = 0x3ffe01f0 ); +PROVIDE ( ets_run = 0x400066bc ); +PROVIDE ( ets_secure_boot_check = 0x4005cb40 ); +PROVIDE ( ets_secure_boot_check_finish = 0x4005cc04 ); +PROVIDE ( ets_secure_boot_check_start = 0x4005cbcc ); +PROVIDE ( ets_secure_boot_finish = 0x4005ca84 ); +PROVIDE ( ets_secure_boot_hash = 0x4005cad4 ); +PROVIDE ( ets_secure_boot_obtain = 0x4005cb14 ); +PROVIDE ( ets_secure_boot_rd_abstract = 0x4005cba8 ); +PROVIDE ( ets_secure_boot_rd_iv = 0x4005cb84 ); +PROVIDE ( ets_secure_boot_start = 0x4005ca34 ); +PROVIDE ( ets_set_appcpu_boot_addr = 0x4000689c ); +PROVIDE ( ets_set_idle_cb = 0x40006674 ); +PROVIDE ( ets_set_startup_callback = 0x4000688c ); +PROVIDE ( ets_set_user_start = 0x4000687c ); +PROVIDE ( ets_sha_disable = 0x4005c0a8 ); +PROVIDE ( ets_sha_enable = 0x4005c07c ); +PROVIDE ( ets_sha_finish = 0x4005c104 ); +PROVIDE ( ets_sha_init = 0x4005c0d4 ); +PROVIDE ( ets_sha_update = 0x4005c2a0 ); +PROVIDE ( ets_startup_callback = 0x3ffe0404 ); +PROVIDE ( ets_task = 0x40006688 ); +PROVIDE ( ets_timer_arm = 0x40008368 ); +PROVIDE ( ets_timer_arm_us = 0x400083ac ); +PROVIDE ( ets_timer_disarm = 0x400083ec ); +PROVIDE ( ets_timer_done = 0x40008428 ); +PROVIDE ( ets_timer_handler_isr = 0x40008454 ); +PROVIDE ( ets_timer_init = 0x400084e8 ); +PROVIDE ( ets_timer_setfn = 0x40008350 ); +PROVIDE ( ets_unpack_flash_code = 0x40007018 ); +PROVIDE ( ets_unpack_flash_code_legacy = 0x4000694c ); +PROVIDE ( ets_update_cpu_frequency = 0x40008550 ); +PROVIDE ( ets_waiti0 = 0x400067d8 ); +PROVIDE ( exc_cause_table = 0x3ff991d0 ); +PROVIDE ( _exit_r = 0x4000bd28 ); +PROVIDE ( __extendsfdf2 = 0x40002c34 ); +PROVIDE ( fclose = 0x400020ac ); +PROVIDE ( _fclose_r = 0x40001fec ); +PROVIDE ( fflush = 0x40059394 ); +PROVIDE ( _fflush_r = 0x40059320 ); +PROVIDE ( __ffsdi2 = 0x4000ca2c ); +PROVIDE ( __ffssi2 = 0x4000c804 ); +PROVIDE ( FilePacketSendDeflatedReqMsgProc = 0x40008b24 ); +PROVIDE ( FilePacketSendReqMsgProc = 0x40008860 ); +PROVIDE ( _findenv_r = 0x40001f44 ); +PROVIDE ( fiprintf = 0x40056efc ); +PROVIDE ( _fiprintf_r = 0x40056ed8 ); +PROVIDE ( fiscanf = 0x40058884 ); +PROVIDE ( _fiscanf_r = 0x400588b4 ); +PROVIDE ( __fixdfdi = 0x40002ac4 ); +PROVIDE ( __fixdfsi = 0x40002a78 ); +PROVIDE ( __fixsfdi = 0x4000244c ); +PROVIDE ( __fixsfsi = 0x4000240c ); +PROVIDE ( __fixunsdfsi = 0x40002b30 ); +PROVIDE ( __fixunssfdi = 0x40002504 ); +PROVIDE ( __fixunssfsi = 0x400024ac ); +PROVIDE ( FlashDwnLdDeflatedStartMsgProc = 0x40008ad8 ); +PROVIDE ( FlashDwnLdParamCfgMsgProc = 0x4000891c ); +PROVIDE ( FlashDwnLdStartMsgProc = 0x40008820 ); +PROVIDE ( FlashDwnLdStopDeflatedReqMsgProc = 0x40008c18 ); +PROVIDE ( FlashDwnLdStopReqMsgProc = 0x400088ec ); +PROVIDE ( __floatdidf = 0x4000c988 ); +PROVIDE ( __floatdisf = 0x4000c8c0 ); +PROVIDE ( __floatsidf = 0x4000c944 ); +PROVIDE ( __floatsisf = 0x4000c870 ); +PROVIDE ( __floatundidf = 0x4000c978 ); +PROVIDE ( __floatundisf = 0x4000c8b0 ); +PROVIDE ( __floatunsidf = 0x4000c938 ); +PROVIDE ( __floatunsisf = 0x4000c864 ); +PROVIDE ( __fp_lock_all = 0x40001f1c ); +PROVIDE ( fprintf = 0x40056efc ); +PROVIDE ( _fprintf_r = 0x40056ed8 ); +PROVIDE ( __fp_unlock_all = 0x40001f30 ); +PROVIDE ( fputwc = 0x40058ea8 ); +PROVIDE ( __fputwc = 0x40058da0 ); +PROVIDE ( _fputwc_r = 0x40058e4c ); +PROVIDE ( free = 0x4000beb8 ); +PROVIDE ( _free_r = 0x4000bbcc ); +PROVIDE ( fscanf = 0x40058884 ); +PROVIDE ( _fscanf_r = 0x400588b4 ); +PROVIDE ( _fstat_r = 0x4000bccc ); +PROVIDE ( _fwalk = 0x4000c738 ); +PROVIDE ( _fwalk_reent = 0x4000c770 ); +PROVIDE ( __gcc_bcmp = 0x40064a70 ); +PROVIDE ( __gedf2 = 0x40063768 ); +PROVIDE ( _GeneralException = 0x40000e14 ); +PROVIDE ( __gesf2 = 0x4006340c ); +PROVIDE ( __get_current_time_locale = 0x40001834 ); +PROVIDE ( _getenv_r = 0x40001fbc ); +PROVIDE ( _getpid_r = 0x4000bcfc ); +PROVIDE ( __getreent = 0x4000be8c ); +PROVIDE ( _gettimeofday_r = 0x4000bc58 ); +PROVIDE ( __gettzinfo = 0x40001fcc ); +PROVIDE ( GetUartDevice = 0x40009598 ); +PROVIDE ( GF_Jacobian_Point_Addition256 = 0x400163a4 ); +PROVIDE ( GF_Jacobian_Point_Double256 = 0x40016260 ); +PROVIDE ( GF_Point_Jacobian_To_Affine256 = 0x40016b0c ); +PROVIDE ( _global_impure_ptr = 0x3ffae0b0 ); +PROVIDE ( gmtime = 0x40059848 ); +PROVIDE ( gmtime_r = 0x40059868 ); +PROVIDE ( g_phyFuns_instance = 0x3ffae0c4 ); +PROVIDE ( gpio_init = 0x40009c20 ); +PROVIDE ( gpio_input_get = 0x40009b88 ); +PROVIDE ( gpio_input_get_high = 0x40009b9c ); +PROVIDE ( gpio_intr_ack = 0x40009dd4 ); +PROVIDE ( gpio_intr_ack_high = 0x40009e1c ); +PROVIDE ( gpio_intr_handler_register = 0x40009e6c ); +PROVIDE ( gpio_intr_pending = 0x40009cec ); +PROVIDE ( gpio_intr_pending_high = 0x40009cf8 ); +PROVIDE ( gpio_matrix_in = 0x40009edc ); +PROVIDE ( gpio_matrix_out = 0x40009f0c ); +PROVIDE ( gpio_output_set = 0x40009b24 ); +PROVIDE ( gpio_output_set_high = 0x40009b5c ); +PROVIDE ( gpio_pad_hold = 0x4000a734 ); +PROVIDE ( gpio_pad_pulldown = 0x4000a348 ); +PROVIDE ( gpio_pad_pullup = 0x4000a22c ); +PROVIDE ( gpio_pad_select_gpio = 0x40009fdc ); +PROVIDE ( gpio_pad_set_drv = 0x4000a11c ); +PROVIDE ( gpio_pad_unhold = 0x4000a484 ); +PROVIDE ( gpio_pending_mask = 0x3ffe0038 ); +PROVIDE ( gpio_pending_mask_high = 0x3ffe0044 ); +PROVIDE ( gpio_pin_intr_state_set = 0x40009d04 ); +PROVIDE ( gpio_pin_wakeup_disable = 0x40009eb0 ); +PROVIDE ( gpio_pin_wakeup_enable = 0x40009e7c ); +PROVIDE ( gpio_register_get = 0x40009cbc ); +PROVIDE ( gpio_register_set = 0x40009bbc ); +PROVIDE ( __gtdf2 = 0x400636dc ); +PROVIDE ( __gtsf2 = 0x400633a0 ); +PROVIDE ( gTxMsg = 0x3ffe0050 ); +PROVIDE ( hci_cmd_desc_root_tab = 0x3ff976d4 ); +PROVIDE ( hci_cmd_desc_tab_ctrl_bb = 0x3ff97b70 ); +PROVIDE ( hci_cmd_desc_tab_info_par = 0x3ff97b1c ); +PROVIDE ( hci_cmd_desc_tab_le = 0x3ff97870 ); +PROVIDE ( hci_cmd_desc_tab_lk_ctrl = 0x3ff97fc0 ); +PROVIDE ( hci_cmd_desc_tab_lk_pol = 0x3ff97f3c ); +PROVIDE ( hci_cmd_desc_tab_stat_par = 0x3ff97ac8 ); +PROVIDE ( hci_cmd_desc_tab_testing = 0x3ff97a98 ); +PROVIDE ( hci_cmd_desc_tab_vs = 0x3ff97714 ); +PROVIDE ( hci_command_handler = 0x4004c928 ); +PROVIDE ( hci_env = 0x3ffb9350 ); +PROVIDE ( hci_evt_dbg_desc_tab = 0x3ff9750c ); +PROVIDE ( hci_evt_desc_tab = 0x3ff9751c ); +PROVIDE ( hci_evt_le_desc_tab = 0x3ff974b4 ); +PROVIDE ( hci_fc_env = 0x3ffb9340 ); +PROVIDE ( hmac_md5 = 0x4005d264 ); +PROVIDE ( hmac_md5_vector = 0x4005d17c ); +PROVIDE ( hmac_sha1 = 0x40060acc ); +PROVIDE ( hmac_sha1_vector = 0x400609e4 ); +PROVIDE ( hmac_sha256 = 0x40060d58 ); +PROVIDE ( hmac_sha256_vector = 0x40060c84 ); +PROVIDE ( intr_matrix_set = 0x4000681c ); +PROVIDE ( iprintf = 0x40056978 ); +PROVIDE ( _iprintf_r = 0x40056944 ); +PROVIDE ( isalnum = 0x40000f04 ); +PROVIDE ( isalpha = 0x40000f18 ); +PROVIDE ( isascii = 0x4000c20c ); +PROVIDE ( _isatty_r = 0x40000ea0 ); +PROVIDE ( isblank = 0x40000f2c ); +PROVIDE ( iscanf = 0x40058760 ); +PROVIDE ( _iscanf_r = 0x4005879c ); +PROVIDE ( iscntrl = 0x40000f50 ); +PROVIDE ( isdigit = 0x40000f64 ); +PROVIDE ( isgraph = 0x40000f94 ); +PROVIDE ( islower = 0x40000f78 ); +PROVIDE ( isprint = 0x40000fa8 ); +PROVIDE ( ispunct = 0x40000fc0 ); +PROVIDE ( isspace = 0x40000fd4 ); +PROVIDE ( isupper = 0x40000fe8 ); +PROVIDE ( itoa = 0x400566b4 ); +PROVIDE ( __itoa = 0x40056678 ); +PROVIDE ( jd_decomp = 0x400613e8 ); +PROVIDE ( jd_prepare = 0x40060fa8 ); +PROVIDE ( ke_env = 0x3ffb93cc ); +PROVIDE ( _KernelExceptionVector = 0x40000300 ); +PROVIDE ( _kill_r = 0x4000bd10 ); +PROVIDE ( labs = 0x40056370 ); +PROVIDE ( lb_default_handler = 0x3ff982b8 ); +PROVIDE ( lb_default_state_tab_p_get = 0x4001c198 ); +PROVIDE ( lb_env = 0x3ffb9424 ); +PROVIDE ( lb_hci_cmd_handler_tab_p_get = 0x4001c18c ); +PROVIDE ( lb_state = 0x3ffb94e8 ); +PROVIDE ( lc_default_handler = 0x3ff98648 ); +PROVIDE ( lc_default_state_tab_p_get = 0x4002f494 ); +PROVIDE ( lc_env = 0x3ffb94ec ); +PROVIDE ( lc_hci_cmd_handler_tab_p_get = 0x4002f488 ); +PROVIDE ( lc_state = 0x3ffb9508 ); +PROVIDE ( ld_acl_br_sizes = 0x3ff98a2a ); +PROVIDE ( ld_acl_br_types = 0x3ff98a36 ); +PROVIDE ( ld_acl_edr_sizes = 0x3ff98a14 ); +PROVIDE ( ld_acl_edr_types = 0x3ff98a22 ); +PROVIDE ( ld_env = 0x3ffb9510 ); +PROVIDE ( ldiv = 0x40056378 ); +PROVIDE ( ld_pcm_settings_dft = 0x3ff98a0c ); +PROVIDE ( ld_sched_params = 0x3ffb96c0 ); +PROVIDE ( ld_sync_train_channels = 0x3ff98a3c ); +PROVIDE ( __ledf2 = 0x40063704 ); +PROVIDE ( __lesf2 = 0x400633c0 ); +PROVIDE ( _Level2FromVector = 0x40000954 ); +PROVIDE ( _Level2Vector = 0x40000180 ); +PROVIDE ( _Level3FromVector = 0x40000a28 ); +PROVIDE ( _Level3Vector = 0x400001c0 ); +PROVIDE ( _Level4FromVector = 0x40000af8 ); +PROVIDE ( _Level4Vector = 0x40000200 ); +PROVIDE ( _Level5FromVector = 0x40000c68 ); +PROVIDE ( _Level5Vector = 0x40000240 ); +PROVIDE ( _LevelOneInterrupt = 0x40000835 ); +PROVIDE ( _link_r = 0x4000bc9c ); +PROVIDE ( llc_default_handler = 0x3ff98b3c ); +PROVIDE ( llc_default_state_tab_p_get = 0x40046058 ); +PROVIDE ( llc_env = 0x3ffb96d0 ); +PROVIDE ( llc_hci_acl_data_tx_handler = 0x40042398 ); +PROVIDE ( llc_hci_cmd_handler_tab_p_get = 0x40042358 ); +PROVIDE ( llc_hci_command_handler = 0x40042360 ); +PROVIDE ( llcp_pdu_handler_tab_p_get = 0x40043f64 ); +PROVIDE ( llc_state = 0x3ffb96f8 ); +PROVIDE ( lldesc_build_chain = 0x4000a850 ); +PROVIDE ( lldesc_num2link = 0x4000a948 ); +PROVIDE ( lldesc_set_owner = 0x4000a974 ); +PROVIDE ( lld_evt_env = 0x3ffb9704 ); +PROVIDE ( lld_pdu_adv_pk_desc_tab = 0x3ff98c70 ); +PROVIDE ( lld_pdu_llcp_pk_desc_tab = 0x3ff98b68 ); +PROVIDE ( LLM_AA_CT1 = 0x3ff98d8a ); +PROVIDE ( LLM_AA_CT2 = 0x3ff98d88 ); +PROVIDE ( llm_default_handler = 0x3ff98d80 ); +PROVIDE ( llm_default_state_tab_p_get = 0x4004e718 ); +PROVIDE ( llm_hci_cmd_handler_tab_p_get = 0x4004c920 ); +PROVIDE ( llm_le_env = 0x3ffb976c ); +PROVIDE ( llm_local_cmds = 0x3ff98d38 ); +PROVIDE ( llm_local_data_len_values = 0x3ff98d1c ); +PROVIDE ( llm_local_le_feats = 0x3ff98d30 ); +PROVIDE ( llm_local_le_states = 0x3ff98d28 ); +PROVIDE ( llm_state = 0x3ffb985c ); +PROVIDE ( lm_default_handler = 0x3ff990e0 ); +PROVIDE ( lm_default_state_tab_p_get = 0x40054268 ); +PROVIDE ( lm_env = 0x3ffb9860 ); +PROVIDE ( lm_hci_cmd_handler_tab_p_get = 0x4005425c ); +PROVIDE ( lm_local_supp_feats = 0x3ff990ee ); +PROVIDE ( lm_n_page_tab = 0x3ff990e8 ); +PROVIDE ( lmp_desc_tab = 0x3ff96e6c ); +PROVIDE ( lmp_ext_desc_tab = 0x3ff96d9c ); +PROVIDE ( lm_state = 0x3ffb9a1c ); +PROVIDE ( __locale_charset = 0x40059540 ); +PROVIDE ( __locale_cjk_lang = 0x40059558 ); +PROVIDE ( localeconv = 0x4005957c ); +PROVIDE ( _localeconv_r = 0x40059560 ); +PROVIDE ( __locale_mb_cur_max = 0x40059548 ); +PROVIDE ( __locale_msgcharset = 0x40059550 ); +PROVIDE ( localtime = 0x400595dc ); +PROVIDE ( localtime_r = 0x400595fc ); +PROVIDE ( _lock_acquire = 0x4000be14 ); +PROVIDE ( _lock_acquire_recursive = 0x4000be28 ); +PROVIDE ( _lock_close = 0x4000bdec ); +PROVIDE ( _lock_close_recursive = 0x4000be00 ); +PROVIDE ( _lock_init = 0x4000bdc4 ); +PROVIDE ( _lock_init_recursive = 0x4000bdd8 ); +PROVIDE ( _lock_release = 0x4000be64 ); +PROVIDE ( _lock_release_recursive = 0x4000be78 ); +PROVIDE ( _lock_try_acquire = 0x4000be3c ); +PROVIDE ( _lock_try_acquire_recursive = 0x4000be50 ); +PROVIDE ( longjmp = 0x400562cc ); +PROVIDE ( _lseek_r = 0x4000bd8c ); +PROVIDE ( __lshrdi3 = 0x4000c84c ); +PROVIDE ( __ltdf2 = 0x40063790 ); +PROVIDE ( __ltsf2 = 0x4006342c ); +PROVIDE ( malloc = 0x4000bea0 ); +PROVIDE ( _malloc_r = 0x4000bbb4 ); +PROVIDE ( maxSecretKey_256 = 0x3ff97448 ); +PROVIDE ( __mb_cur_max = 0x3ff96530 ); +PROVIDE ( MD5Final = 0x4005db1c ); +PROVIDE ( MD5Init = 0x4005da7c ); +PROVIDE ( MD5Update = 0x4005da9c ); +PROVIDE ( md5_vector = 0x4005db80 ); +PROVIDE ( memccpy = 0x4000c220 ); +PROVIDE ( memchr = 0x4000c244 ); +PROVIDE ( memcmp = 0x4000c260 ); +PROVIDE ( memcpy = 0x4000c2c8 ); +PROVIDE ( MemDwnLdStartMsgProc = 0x40008948 ); +PROVIDE ( MemDwnLdStopReqMsgProc = 0x400089dc ); +PROVIDE ( memmove = 0x4000c3c0 ); +PROVIDE ( MemPacketSendReqMsgProc = 0x40008978 ); +PROVIDE ( memrchr = 0x4000c400 ); +PROVIDE ( memset = 0x4000c44c ); +PROVIDE ( mktime = 0x4005a5e8 ); +PROVIDE ( mmu_init = 0x400095a4 ); +PROVIDE ( __moddi3 = 0x4000cd4c ); +PROVIDE ( __modsi3 = 0x4000c7c0 ); +PROVIDE ( __month_lengths = 0x3ff9609c ); +PROVIDE ( __muldc3 = 0x40063bf4 ); +PROVIDE ( __muldf3 = 0x4006358c ); +PROVIDE ( __muldi3 = 0x4000c9fc ); +PROVIDE ( __mulsc3 = 0x40063934 ); +PROVIDE ( __mulsf3 = 0x400632c8 ); +PROVIDE ( __mulsi3 = 0x4000c7b0 ); +PROVIDE ( MultiplyBigHexByUint32_256 = 0x40016214 ); +PROVIDE ( MultiplyBigHexModP256 = 0x400160b8 ); +PROVIDE ( MultiplyByU32ModP256 = 0x40015fdc ); +PROVIDE ( multofup = 0x4000ab8c ); +PROVIDE ( __mulvdi3 = 0x40002d78 ); +PROVIDE ( __mulvsi3 = 0x40002d60 ); +PROVIDE ( mz_adler32 = 0x4005edbc ); +PROVIDE ( mz_crc32 = 0x4005ee88 ); +PROVIDE ( mz_free = 0x4005eed4 ); +PROVIDE ( __nedf2 = 0x400636a8 ); +PROVIDE ( __negdf2 = 0x400634a0 ); +PROVIDE ( __negdi2 = 0x4000ca14 ); +PROVIDE ( __negsf2 = 0x400020c0 ); +PROVIDE ( __negvdi2 = 0x40002e98 ); +PROVIDE ( __negvsi2 = 0x40002e78 ); +PROVIDE ( __nesf2 = 0x40063374 ); +PROVIDE ( _NMIExceptionVector = 0x400002c0 ); +PROVIDE ( notEqual256 = 0x40015b04 ); +PROVIDE ( __nsau_data = 0x3ff96544 ); +PROVIDE ( one_bits = 0x3ff971f8 ); +PROVIDE ( open = 0x4000178c ); +PROVIDE ( _open_r = 0x4000bd54 ); +PROVIDE ( __paritysi2 = 0x40002f3c ); +PROVIDE ( pbkdf2_sha1 = 0x40060ba4 ); +PROVIDE ( phy_get_romfuncs = 0x40004100 ); +PROVIDE ( __popcountdi2 = 0x40002ef8 ); +PROVIDE ( __popcountsi2 = 0x40002ed0 ); +PROVIDE ( __popcount_tab = 0x3ff96544 ); +PROVIDE ( __powidf2 = 0x400638d4 ); +PROVIDE ( __powisf2 = 0x4006389c ); +PROVIDE ( _Pri_4_HandlerAddress = 0x3ffe0648 ); +PROVIDE ( _Pri_5_HandlerAddress = 0x3ffe064c ); +PROVIDE ( printf = 0x40056978 ); +PROVIDE ( _printf_common = 0x40057338 ); +PROVIDE ( _printf_float = 0x4000befc ); +PROVIDE ( _printf_i = 0x40057404 ); +PROVIDE ( _printf_r = 0x40056944 ); +PROVIDE ( qsort = 0x40056424 ); +PROVIDE ( _raise_r = 0x4000bc70 ); +PROVIDE ( rand = 0x40001058 ); +PROVIDE ( rand_r = 0x400010d4 ); +PROVIDE ( r_btdm_option_data = 0x3ffae6e0 ); +PROVIDE ( r_bt_util_buf_acl_rx_alloc = 0x40010218 ); +PROVIDE ( r_bt_util_buf_acl_rx_free = 0x40010234 ); +PROVIDE ( r_bt_util_buf_acl_tx_alloc = 0x40010268 ); +PROVIDE ( r_bt_util_buf_acl_tx_free = 0x40010280 ); +PROVIDE ( r_bt_util_buf_init = 0x400100e4 ); +PROVIDE ( r_bt_util_buf_lmp_tx_alloc = 0x400101d0 ); +PROVIDE ( r_bt_util_buf_lmp_tx_free = 0x400101ec ); +PROVIDE ( r_bt_util_buf_sync_clear = 0x400103c8 ); +PROVIDE ( r_bt_util_buf_sync_init = 0x400102c4 ); +PROVIDE ( r_bt_util_buf_sync_rx_alloc = 0x40010468 ); +PROVIDE ( r_bt_util_buf_sync_rx_free = 0x4001049c ); +PROVIDE ( r_bt_util_buf_sync_tx_alloc = 0x400103ec ); +PROVIDE ( r_bt_util_buf_sync_tx_free = 0x40010428 ); +PROVIDE ( rc4_skip = 0x40060928 ); +PROVIDE ( r_co_bdaddr_compare = 0x40014324 ); +PROVIDE ( r_co_bytes_to_string = 0x400142e4 ); +PROVIDE ( r_co_list_check_size_available = 0x400142c4 ); +PROVIDE ( r_co_list_extract = 0x4001404c ); +PROVIDE ( r_co_list_extract_after = 0x40014118 ); +PROVIDE ( r_co_list_find = 0x4001419c ); +PROVIDE ( r_co_list_init = 0x40013f14 ); +PROVIDE ( r_co_list_insert_after = 0x40014254 ); +PROVIDE ( r_co_list_insert_before = 0x40014200 ); +PROVIDE ( r_co_list_merge = 0x400141bc ); +PROVIDE ( r_co_list_pool_init = 0x40013f30 ); +PROVIDE ( r_co_list_pop_front = 0x40014028 ); +PROVIDE ( r_co_list_push_back = 0x40013fb8 ); +PROVIDE ( r_co_list_push_front = 0x40013ff4 ); +PROVIDE ( r_co_list_size = 0x400142ac ); +PROVIDE ( r_co_nb_good_channels = 0x40014360 ); +PROVIDE ( r_co_slot_to_duration = 0x40014348 ); +PROVIDE ( RcvMsg = 0x4000954c ); +PROVIDE ( r_dbg_init = 0x40014394 ); +PROVIDE ( r_dbg_platform_reset_complete = 0x400143d0 ); +PROVIDE ( r_dbg_swdiag_init = 0x40014470 ); +PROVIDE ( r_dbg_swdiag_read = 0x400144a4 ); +PROVIDE ( r_dbg_swdiag_write = 0x400144d0 ); +PROVIDE ( r_E1 = 0x400108e8 ); +PROVIDE ( r_E21 = 0x40010968 ); +PROVIDE ( r_E22 = 0x400109b4 ); +PROVIDE ( r_E3 = 0x40010a58 ); +PROVIDE ( r_ea_alarm_clear = 0x40015ab4 ); +PROVIDE ( r_ea_alarm_set = 0x40015a10 ); +PROVIDE ( read = 0x400017dc ); +PROVIDE ( _read_r = 0x4000bda8 ); +PROVIDE ( r_ea_elt_cancel = 0x400150d0 ); +PROVIDE ( r_ea_elt_create = 0x40015264 ); +PROVIDE ( r_ea_elt_insert = 0x400152a8 ); +PROVIDE ( r_ea_elt_remove = 0x400154f0 ); +PROVIDE ( r_ea_finetimer_isr = 0x400155d4 ); +PROVIDE ( r_ea_init = 0x40015228 ); +PROVIDE ( r_ea_interval_create = 0x4001555c ); +PROVIDE ( r_ea_interval_delete = 0x400155a8 ); +PROVIDE ( r_ea_interval_duration_req = 0x4001597c ); +PROVIDE ( r_ea_interval_insert = 0x4001557c ); +PROVIDE ( r_ea_interval_remove = 0x40015590 ); +PROVIDE ( realloc = 0x4000becc ); +PROVIDE ( _realloc_r = 0x4000bbe0 ); +PROVIDE ( r_ea_offset_req = 0x40015748 ); +PROVIDE ( r_ea_sleep_check = 0x40015928 ); +PROVIDE ( r_ea_sw_isr = 0x40015724 ); +PROVIDE ( r_ea_time_get_halfslot_rounded = 0x40015894 ); +PROVIDE ( r_ea_time_get_slot_rounded = 0x400158d4 ); +PROVIDE ( r_ecc_abort_key256_generation = 0x40017070 ); +PROVIDE ( r_ecc_generate_key256 = 0x40016e00 ); +PROVIDE ( r_ecc_gen_new_public_key = 0x400170c0 ); +PROVIDE ( r_ecc_gen_new_secret_key = 0x400170e4 ); +PROVIDE ( r_ecc_get_debug_Keys = 0x40017224 ); +PROVIDE ( r_ecc_init = 0x40016dbc ); +PROVIDE ( RecvBuff = 0x3ffe009c ); +PROVIDE ( recv_packet = 0x40009424 ); +PROVIDE ( r_em_buf_init = 0x4001729c ); +PROVIDE ( r_em_buf_rx_buff_addr_get = 0x400173e8 ); +PROVIDE ( r_em_buf_rx_free = 0x400173c4 ); +PROVIDE ( r_em_buf_tx_buff_addr_get = 0x40017404 ); +PROVIDE ( r_em_buf_tx_free = 0x4001741c ); +PROVIDE ( _rename_r = 0x4000bc28 ); +PROVIDE ( _ResetHandler = 0x40000450 ); +PROVIDE ( _ResetVector = 0x40000400 ); +PROVIDE ( r_F1_256 = 0x400133e4 ); +PROVIDE ( r_F2_256 = 0x40013568 ); +PROVIDE ( r_F3_256 = 0x40013664 ); +PROVIDE ( RFPLL_ICP_TABLE = 0x3ffb8b7c ); +PROVIDE ( r_G_256 = 0x40013470 ); +PROVIDE ( r_H3 = 0x40013760 ); +PROVIDE ( r_H4 = 0x40013830 ); +PROVIDE ( r_h4tl_init = 0x40017878 ); +PROVIDE ( r_h4tl_start = 0x40017924 ); +PROVIDE ( r_h4tl_stop = 0x40017934 ); +PROVIDE ( r_h4tl_write = 0x400178d0 ); +PROVIDE ( r_H5 = 0x400138dc ); +PROVIDE ( r_hashConcat = 0x40013a38 ); +PROVIDE ( r_hci_acl_tx_data_alloc = 0x4001951c ); +PROVIDE ( r_hci_acl_tx_data_received = 0x40019654 ); +PROVIDE ( r_hci_bt_acl_bdaddr_register = 0x40018900 ); +PROVIDE ( r_hci_bt_acl_bdaddr_unregister = 0x400189ac ); +PROVIDE ( r_hci_bt_acl_conhdl_register = 0x4001895c ); +PROVIDE ( r_hci_cmd_get_max_param_size = 0x400192d0 ); +PROVIDE ( r_hci_cmd_received = 0x400192f8 ); +PROVIDE ( r_hci_evt_filter_add = 0x40018a64 ); +PROVIDE ( r_hci_evt_mask_set = 0x400189e4 ); +PROVIDE ( r_hci_fc_acl_buf_size_set = 0x40017988 ); +PROVIDE ( r_hci_fc_acl_en = 0x400179d8 ); +PROVIDE ( r_hci_fc_acl_packet_sent = 0x40017a3c ); +PROVIDE ( r_hci_fc_check_host_available_nb_acl_packets = 0x40017aa4 ); +PROVIDE ( r_hci_fc_check_host_available_nb_sync_packets = 0x40017ac8 ); +PROVIDE ( r_hci_fc_host_nb_acl_pkts_complete = 0x40017a6c ); +PROVIDE ( r_hci_fc_host_nb_sync_pkts_complete = 0x40017a88 ); +PROVIDE ( r_hci_fc_init = 0x40017974 ); +PROVIDE ( r_hci_fc_sync_buf_size_set = 0x400179b0 ); +PROVIDE ( r_hci_fc_sync_en = 0x40017a30 ); +PROVIDE ( r_hci_fc_sync_packet_sent = 0x40017a54 ); +PROVIDE ( r_hci_init = 0x40018538 ); +PROVIDE ( r_hci_look_for_cmd_desc = 0x40018454 ); +PROVIDE ( r_hci_look_for_dbg_evt_desc = 0x400184c4 ); +PROVIDE ( r_hci_look_for_evt_desc = 0x400184a0 ); +PROVIDE ( r_hci_look_for_le_evt_desc = 0x400184e0 ); +PROVIDE ( r_hci_reset = 0x4001856c ); +PROVIDE ( r_hci_send_2_host = 0x400185bc ); +PROVIDE ( r_hci_sync_tx_data_alloc = 0x40019754 ); +PROVIDE ( r_hci_sync_tx_data_received = 0x400197c0 ); +PROVIDE ( r_hci_tl_init = 0x40019290 ); +PROVIDE ( r_hci_tl_send = 0x40019228 ); +PROVIDE ( r_hci_util_pack = 0x40019874 ); +PROVIDE ( r_hci_util_unpack = 0x40019998 ); +PROVIDE ( r_hci_voice_settings_get = 0x40018bdc ); +PROVIDE ( r_hci_voice_settings_set = 0x40018be8 ); +PROVIDE ( r_HMAC = 0x40013968 ); +PROVIDE ( r_import_rf_phy_func = 0x3ffb8354 ); +PROVIDE ( r_import_rf_phy_func_p = 0x3ffafd64 ); +PROVIDE ( r_ip_funcs = 0x3ffae710 ); +PROVIDE ( r_ip_funcs_p = 0x3ffae70c ); +PROVIDE ( r_ke_check_malloc = 0x40019de0 ); +PROVIDE ( r_ke_event_callback_set = 0x40019ba8 ); +PROVIDE ( r_ke_event_clear = 0x40019c2c ); +PROVIDE ( r_ke_event_flush = 0x40019ccc ); +PROVIDE ( r_ke_event_get = 0x40019c78 ); +PROVIDE ( r_ke_event_get_all = 0x40019cc0 ); +PROVIDE ( r_ke_event_init = 0x40019b90 ); +PROVIDE ( r_ke_event_schedule = 0x40019cdc ); +PROVIDE ( r_ke_event_set = 0x40019be0 ); +PROVIDE ( r_ke_flush = 0x4001a374 ); +PROVIDE ( r_ke_free = 0x4001a014 ); +PROVIDE ( r_ke_get_max_mem_usage = 0x4001a1c8 ); +PROVIDE ( r_ke_get_mem_usage = 0x4001a1a0 ); +PROVIDE ( r_ke_init = 0x4001a318 ); +PROVIDE ( r_ke_is_free = 0x4001a184 ); +PROVIDE ( r_ke_malloc = 0x40019eb4 ); +PROVIDE ( r_ke_mem_init = 0x40019d3c ); +PROVIDE ( r_ke_mem_is_empty = 0x40019d8c ); +PROVIDE ( r_ke_msg_alloc = 0x4001a1e0 ); +PROVIDE ( r_ke_msg_dest_id_get = 0x4001a2e0 ); +PROVIDE ( r_ke_msg_discard = 0x4001a850 ); +PROVIDE ( r_ke_msg_forward = 0x4001a290 ); +PROVIDE ( r_ke_msg_forward_new_id = 0x4001a2ac ); +PROVIDE ( r_ke_msg_free = 0x4001a2cc ); +PROVIDE ( r_ke_msg_in_queue = 0x4001a2f8 ); +PROVIDE ( r_ke_msg_save = 0x4001a858 ); +PROVIDE ( r_ke_msg_send = 0x4001a234 ); +PROVIDE ( r_ke_msg_send_basic = 0x4001a26c ); +PROVIDE ( r_ke_msg_src_id_get = 0x4001a2ec ); +PROVIDE ( r_ke_queue_extract = 0x40055fd0 ); +PROVIDE ( r_ke_queue_insert = 0x40056020 ); +PROVIDE ( r_ke_sleep_check = 0x4001a3d8 ); +PROVIDE ( r_ke_state_get = 0x4001a7d8 ); +PROVIDE ( r_ke_state_set = 0x4001a6fc ); +PROVIDE ( r_ke_stats_get = 0x4001a3f0 ); +PROVIDE ( r_ke_task_check = 0x4001a8a4 ); +PROVIDE ( r_ke_task_create = 0x4001a674 ); +PROVIDE ( r_ke_task_delete = 0x4001a6c0 ); +PROVIDE ( r_ke_task_init = 0x4001a650 ); +PROVIDE ( r_ke_task_msg_flush = 0x4001a860 ); +PROVIDE ( r_ke_timer_active = 0x4001ac08 ); +PROVIDE ( r_ke_timer_adjust_all = 0x4001ac30 ); +PROVIDE ( r_ke_timer_clear = 0x4001ab90 ); +PROVIDE ( r_ke_timer_init = 0x4001aa9c ); +PROVIDE ( r_ke_timer_set = 0x4001aac0 ); +PROVIDE ( r_ke_timer_sleep_check = 0x4001ac50 ); +PROVIDE ( r_KPrimC = 0x40010ad4 ); +PROVIDE ( r_lb_clk_adj_activate = 0x4001ae70 ); +PROVIDE ( r_lb_clk_adj_id_get = 0x4001af14 ); +PROVIDE ( r_lb_clk_adj_period_update = 0x4001af20 ); +PROVIDE ( r_lb_init = 0x4001acd4 ); +PROVIDE ( r_lb_mst_key = 0x4001afc0 ); +PROVIDE ( r_lb_mst_key_cmp = 0x4001af74 ); +PROVIDE ( r_lb_mst_key_restart_enc = 0x4001b0d4 ); +PROVIDE ( r_lb_mst_start_act_bcst_enc = 0x4001b198 ); +PROVIDE ( r_lb_mst_stop_act_bcst_enc = 0x4001b24c ); +PROVIDE ( r_lb_reset = 0x4001ad38 ); +PROVIDE ( r_lb_send_lmp = 0x4001adbc ); +PROVIDE ( r_lb_send_pdu_clk_adj = 0x4001af3c ); +PROVIDE ( r_lb_util_get_csb_mode = 0x4001ada4 ); +PROVIDE ( r_lb_util_get_nb_broadcast = 0x4001ad80 ); +PROVIDE ( r_lb_util_get_res_lt_addr = 0x4001ad98 ); +PROVIDE ( r_lb_util_set_nb_broadcast = 0x4001ad8c ); +PROVIDE ( r_lc_afh_set = 0x4001cc74 ); +PROVIDE ( r_lc_afh_start = 0x4001d240 ); +PROVIDE ( r_lc_auth_cmp = 0x4001cd54 ); +PROVIDE ( r_lc_calc_link_key = 0x4001ce7c ); +PROVIDE ( r_lc_chg_pkt_type_cmp = 0x4001d038 ); +PROVIDE ( r_lc_chg_pkt_type_cont = 0x4001cfbc ); +PROVIDE ( r_lc_chg_pkt_type_retry = 0x4001d0ac ); +PROVIDE ( r_lc_chk_to = 0x4001d2a8 ); +PROVIDE ( r_lc_cmd_stat_send = 0x4001c914 ); +PROVIDE ( r_lc_comb_key_svr = 0x4001d30c ); +PROVIDE ( r_lc_con_cmp = 0x4001d44c ); +PROVIDE ( r_lc_con_cmp_evt_send = 0x4001d4fc ); +PROVIDE ( r_lc_conn_seq_done = 0x40021334 ); +PROVIDE ( r_lc_detach = 0x4002037c ); +PROVIDE ( r_lc_dhkey = 0x4001d564 ); +PROVIDE ( r_lc_enc_cmp = 0x4001d8bc ); +PROVIDE ( r_lc_enc_key_refresh = 0x4001d720 ); +PROVIDE ( r_lc_end_chk_colli = 0x4001d858 ); +PROVIDE ( r_lc_end_of_sniff_nego = 0x4001d9a4 ); +PROVIDE ( r_lc_enter_sniff_mode = 0x4001ddb8 ); +PROVIDE ( r_lc_epr_change_lk = 0x4001db38 ); +PROVIDE ( r_lc_epr_cmp = 0x4001da88 ); +PROVIDE ( r_lc_epr_resp = 0x4001e0b4 ); +PROVIDE ( r_lc_epr_rsw_cmp = 0x4001dd40 ); +PROVIDE ( r_lc_ext_feat = 0x40020d6c ); +PROVIDE ( r_lc_feat = 0x40020984 ); +PROVIDE ( r_lc_hl_connect = 0x400209e8 ); +PROVIDE ( r_lc_init = 0x4001c948 ); +PROVIDE ( r_lc_init_calc_f3 = 0x4001deb0 ); +PROVIDE ( r_lc_initiator_epr = 0x4001e064 ); +PROVIDE ( r_lc_init_passkey_loop = 0x4001dfc0 ); +PROVIDE ( r_lc_init_start_mutual_auth = 0x4001df60 ); +PROVIDE ( r_lc_key_exch_end = 0x4001e140 ); +PROVIDE ( r_lc_legacy_pair = 0x4001e1c0 ); +PROVIDE ( r_lc_local_switch = 0x4001e22c ); +PROVIDE ( r_lc_local_trans_mode = 0x4001e2e4 ); +PROVIDE ( r_lc_local_untrans_mode = 0x4001e3a0 ); +PROVIDE ( r_lc_loc_auth = 0x40020ecc ); +PROVIDE ( r_lc_locepr_lkref = 0x4001d648 ); +PROVIDE ( r_lc_locepr_rsw = 0x4001d5d0 ); +PROVIDE ( r_lc_loc_sniff = 0x40020a6c ); +PROVIDE ( r_lc_max_slot_mgt = 0x4001e410 ); +PROVIDE ( r_lc_mst_key = 0x4001e7c0 ); +PROVIDE ( r_lc_mst_qos_done = 0x4001ea80 ); +PROVIDE ( r_lc_mst_send_mst_key = 0x4001e8f4 ); +PROVIDE ( r_lc_mutual_auth_end = 0x4001e670 ); +PROVIDE ( r_lc_mutual_auth_end2 = 0x4001e4f4 ); +PROVIDE ( r_lc_packet_type = 0x40021038 ); +PROVIDE ( r_lc_pair = 0x40020ddc ); +PROVIDE ( r_lc_pairing_cont = 0x4001eafc ); +PROVIDE ( r_lc_passkey_comm = 0x4001ed20 ); +PROVIDE ( r_lc_prepare_all_links_for_clk_adj = 0x40021430 ); +PROVIDE ( r_lc_proc_rcv_dhkey = 0x4001edec ); +PROVIDE ( r_lc_ptt = 0x4001ee2c ); +PROVIDE ( r_lc_ptt_cmp = 0x4001eeec ); +PROVIDE ( r_lc_qos_setup = 0x4001ef50 ); +PROVIDE ( r_lc_rd_rem_name = 0x4001efd0 ); +PROVIDE ( r_lc_release = 0x4001f8a8 ); +PROVIDE ( r_lc_rem_enc = 0x4001f124 ); +PROVIDE ( r_lc_rem_name_cont = 0x4001f290 ); +PROVIDE ( r_lc_rem_nego_trans_mode = 0x4001f1b4 ); +PROVIDE ( r_lc_rem_sniff = 0x40020ca4 ); +PROVIDE ( r_lc_rem_sniff_sub_rate = 0x40020b10 ); +PROVIDE ( r_lc_rem_switch = 0x4001f070 ); +PROVIDE ( r_lc_rem_trans_mode = 0x4001f314 ); +PROVIDE ( r_lc_rem_unsniff = 0x400207a0 ); +PROVIDE ( r_lc_rem_untrans_mode = 0x4001f36c ); +PROVIDE ( r_lc_reset = 0x4001c99c ); +PROVIDE ( r_lc_resp_auth = 0x4001f518 ); +PROVIDE ( r_lc_resp_calc_f3 = 0x4001f710 ); +PROVIDE ( r_lc_resp_num_comp = 0x40020074 ); +PROVIDE ( r_lc_resp_oob_nonce = 0x4001f694 ); +PROVIDE ( r_lc_resp_oob_wait_nonce = 0x4001f66c ); +PROVIDE ( r_lc_resp_pair = 0x400208a4 ); +PROVIDE ( r_lc_resp_sec_auth = 0x4001f4a0 ); +PROVIDE ( r_lc_resp_wait_dhkey_cont = 0x4001f86c ); +PROVIDE ( r_lc_restart_enc = 0x4001f8ec ); +PROVIDE ( r_lc_restart_enc_cont = 0x4001f940 ); +PROVIDE ( r_lc_restore_afh_reporting = 0x4001f028 ); +PROVIDE ( r_lc_restore_to = 0x4001f9e0 ); +PROVIDE ( r_lc_ret_sniff_max_slot_chg = 0x4001fa30 ); +PROVIDE ( r_lc_rsw_clean_up = 0x4001dc70 ); +PROVIDE ( r_lc_rsw_done = 0x4001db94 ); +PROVIDE ( r_lc_sco_baseband_ack = 0x40022b00 ); +PROVIDE ( r_lc_sco_detach = 0x40021e40 ); +PROVIDE ( r_lc_sco_host_accept = 0x40022118 ); +PROVIDE ( r_lc_sco_host_reject = 0x400222b8 ); +PROVIDE ( r_lc_sco_host_request = 0x40021f4c ); +PROVIDE ( r_lc_sco_host_request_disc = 0x4002235c ); +PROVIDE ( r_lc_sco_init = 0x40021dc8 ); +PROVIDE ( r_lc_sco_peer_accept = 0x40022780 ); +PROVIDE ( r_lc_sco_peer_accept_disc = 0x40022a08 ); +PROVIDE ( r_lc_sco_peer_reject = 0x40022824 ); +PROVIDE ( r_lc_sco_peer_reject_disc = 0x40022a8c ); +PROVIDE ( r_lc_sco_peer_request = 0x4002240c ); +PROVIDE ( r_lc_sco_peer_request_disc = 0x400228ec ); +PROVIDE ( r_lc_sco_release = 0x40021eec ); +PROVIDE ( r_lc_sco_reset = 0x40021dfc ); +PROVIDE ( r_lc_sco_timeout = 0x40022bd4 ); +PROVIDE ( r_lc_sec_auth_compute_sres = 0x4001f3ec ); +PROVIDE ( r_lc_semi_key_cmp = 0x40020294 ); +PROVIDE ( r_lc_send_enc_chg_evt = 0x4002134c ); +PROVIDE ( r_lc_send_enc_mode = 0x40020220 ); +PROVIDE ( r_lc_send_lmp = 0x4001c1a8 ); +PROVIDE ( r_lc_send_pdu_acc = 0x4001c21c ); +PROVIDE ( r_lc_send_pdu_acc_ext4 = 0x4001c240 ); +PROVIDE ( r_lc_send_pdu_au_rand = 0x4001c308 ); +PROVIDE ( r_lc_send_pdu_auto_rate = 0x4001c5d0 ); +PROVIDE ( r_lc_send_pdu_clk_adj_ack = 0x4001c46c ); +PROVIDE ( r_lc_send_pdu_clk_adj_req = 0x4001c494 ); +PROVIDE ( r_lc_send_pdu_comb_key = 0x4001c368 ); +PROVIDE ( r_lc_send_pdu_dhkey_chk = 0x4001c8e8 ); +PROVIDE ( r_lc_send_pdu_encaps_head = 0x4001c440 ); +PROVIDE ( r_lc_send_pdu_encaps_payl = 0x4001c410 ); +PROVIDE ( r_lc_send_pdu_enc_key_sz_req = 0x4001c670 ); +PROVIDE ( r_lc_send_pdu_esco_lk_rem_req = 0x4001c5a8 ); +PROVIDE ( r_lc_send_pdu_feats_ext_req = 0x4001c6ec ); +PROVIDE ( r_lc_send_pdu_feats_res = 0x4001c694 ); +PROVIDE ( r_lc_send_pdu_in_rand = 0x4001c338 ); +PROVIDE ( r_lc_send_pdu_io_cap_res = 0x4001c72c ); +PROVIDE ( r_lc_send_pdu_lsto = 0x4001c64c ); +PROVIDE ( r_lc_send_pdu_max_slot = 0x4001c3c8 ); +PROVIDE ( r_lc_send_pdu_max_slot_req = 0x4001c3ec ); +PROVIDE ( r_lc_send_pdu_not_acc = 0x4001c26c ); +PROVIDE ( r_lc_send_pdu_not_acc_ext4 = 0x4001c294 ); +PROVIDE ( r_lc_send_pdu_num_comp_fail = 0x4001c770 ); +PROVIDE ( r_lc_send_pdu_pause_enc_aes_req = 0x4001c794 ); +PROVIDE ( r_lc_send_pdu_paus_enc_req = 0x4001c7c0 ); +PROVIDE ( r_lc_send_pdu_ptt_req = 0x4001c4c0 ); +PROVIDE ( r_lc_send_pdu_qos_req = 0x4001c82c ); +PROVIDE ( r_lc_send_pdu_resu_enc_req = 0x4001c7e4 ); +PROVIDE ( r_lc_send_pdu_sco_lk_rem_req = 0x4001c580 ); +PROVIDE ( r_lc_send_pdu_set_afh = 0x4001c2c8 ); +PROVIDE ( r_lc_send_pdu_setup_cmp = 0x4001c808 ); +PROVIDE ( r_lc_send_pdu_slot_off = 0x4001c854 ); +PROVIDE ( r_lc_send_pdu_sniff_req = 0x4001c5f0 ); +PROVIDE ( r_lc_send_pdu_sp_cfm = 0x4001c518 ); +PROVIDE ( r_lc_send_pdu_sp_nb = 0x4001c4e8 ); +PROVIDE ( r_lc_send_pdu_sres = 0x4001c548 ); +PROVIDE ( r_lc_send_pdu_tim_acc = 0x4001c6cc ); +PROVIDE ( r_lc_send_pdu_unit_key = 0x4001c398 ); +PROVIDE ( r_lc_send_pdu_unsniff_req = 0x4001c894 ); +PROVIDE ( r_lc_send_pdu_vers_req = 0x4001c8b4 ); +PROVIDE ( r_lc_skip_hl_oob_req = 0x400201bc ); +PROVIDE ( r_lc_sniff_init = 0x40022cac ); +PROVIDE ( r_lc_sniff_max_slot_chg = 0x40020590 ); +PROVIDE ( r_lc_sniff_reset = 0x40022cc8 ); +PROVIDE ( r_lc_sniff_slot_unchange = 0x40021100 ); +PROVIDE ( r_lc_sniff_sub_mode = 0x400204fc ); +PROVIDE ( r_lc_sp_end = 0x400213a8 ); +PROVIDE ( r_lc_sp_fail = 0x40020470 ); +PROVIDE ( r_lc_sp_oob_tid_fail = 0x400204cc ); +PROVIDE ( r_lc_ssr_nego = 0x4002125c ); +PROVIDE ( r_lc_start = 0x4001ca28 ); +PROVIDE ( r_lc_start_enc = 0x4001fb28 ); +PROVIDE ( r_lc_start_enc_key_size = 0x4001fd9c ); +PROVIDE ( r_lc_start_key_exch = 0x4001fe10 ); +PROVIDE ( r_lc_start_lmp_to = 0x4001fae8 ); +PROVIDE ( r_lc_start_oob = 0x4001fffc ); +PROVIDE ( r_lc_start_passkey = 0x4001feac ); +PROVIDE ( r_lc_start_passkey_loop = 0x4001ff88 ); +PROVIDE ( r_lc_stop_afh_report = 0x40020184 ); +PROVIDE ( r_lc_stop_enc = 0x40020110 ); +PROVIDE ( r_lc_switch_cmp = 0x40020448 ); +PROVIDE ( r_lc_unit_key_svr = 0x400206d8 ); +PROVIDE ( r_lc_unsniff = 0x40020c50 ); +PROVIDE ( r_lc_unsniff_cmp = 0x40020810 ); +PROVIDE ( r_lc_unsniff_cont = 0x40020750 ); +PROVIDE ( r_lc_upd_to = 0x4002065c ); +PROVIDE ( r_lc_util_convert_pref_rate_to_packet_type = 0x4002f9b0 ); +PROVIDE ( r_lc_util_get_max_packet_size = 0x4002f4ac ); +PROVIDE ( r_lc_util_get_offset_clke = 0x4002f538 ); +PROVIDE ( r_lc_util_get_offset_clkn = 0x4002f51c ); +PROVIDE ( r_lc_util_set_loc_trans_coll = 0x4002f500 ); +PROVIDE ( r_lc_version = 0x40020a30 ); +PROVIDE ( r_ld_acl_active_hop_types_get = 0x40036e10 ); +PROVIDE ( r_ld_acl_afh_confirm = 0x40036d40 ); +PROVIDE ( r_ld_acl_afh_prepare = 0x40036c84 ); +PROVIDE ( r_ld_acl_afh_set = 0x40036b60 ); +PROVIDE ( r_ld_acl_allowed_tx_packet_types_set = 0x40036810 ); +PROVIDE ( r_ld_acl_bcst_rx_dec = 0x40036394 ); +PROVIDE ( r_ld_acl_bit_off_get = 0x40036b18 ); +PROVIDE ( r_ld_acl_clk_adj_set = 0x40036a00 ); +PROVIDE ( r_ld_acl_clk_off_get = 0x40036b00 ); +PROVIDE ( r_ld_acl_clk_set = 0x40036950 ); +PROVIDE ( r_ld_acl_clock_offset_get = 0x400364c0 ); +PROVIDE ( r_ld_acl_current_tx_power_get = 0x400368f0 ); +PROVIDE ( r_ld_acl_data_flush = 0x400357bc ); +PROVIDE ( r_ld_acl_data_tx = 0x4003544c ); +PROVIDE ( r_ld_acl_edr_set = 0x4003678c ); +PROVIDE ( r_ld_acl_enc_key_load = 0x40036404 ); +PROVIDE ( r_ld_acl_flow_off = 0x40035400 ); +PROVIDE ( r_ld_acl_flow_on = 0x4003541c ); +PROVIDE ( r_ld_acl_flush_timeout_get = 0x40035f9c ); +PROVIDE ( r_ld_acl_flush_timeout_set = 0x40035fe0 ); +PROVIDE ( r_ld_acl_init = 0x40034d08 ); +PROVIDE ( r_ld_acl_lmp_flush = 0x40035d80 ); +PROVIDE ( r_ld_acl_lmp_tx = 0x40035b34 ); +PROVIDE ( r_ld_acl_lsto_get = 0x400366b4 ); +PROVIDE ( r_ld_acl_lsto_set = 0x400366f8 ); +PROVIDE ( r_ld_acl_reset = 0x40034d24 ); +PROVIDE ( r_ld_acl_role_get = 0x40036b30 ); +PROVIDE ( r_ld_acl_rssi_delta_get = 0x40037028 ); +PROVIDE ( r_ld_acl_rsw_req = 0x40035e74 ); +PROVIDE ( r_ld_acl_rx_enc = 0x40036344 ); +PROVIDE ( r_ld_acl_rx_max_slot_get = 0x40036e58 ); +PROVIDE ( r_ld_acl_rx_max_slot_set = 0x40036ea0 ); +PROVIDE ( r_ld_acl_slot_offset_get = 0x4003653c ); +PROVIDE ( r_ld_acl_slot_offset_set = 0x40036658 ); +PROVIDE ( r_ld_acl_sniff = 0x4003617c ); +PROVIDE ( r_ld_acl_sniff_trans = 0x400360a8 ); +PROVIDE ( r_ld_acl_ssr_set = 0x40036274 ); +PROVIDE ( r_ld_acl_start = 0x40034ddc ); +PROVIDE ( r_ld_acl_stop = 0x4003532c ); +PROVIDE ( r_ld_acl_test_mode_set = 0x40036f24 ); +PROVIDE ( r_ld_acl_timing_accuracy_set = 0x4003673c ); +PROVIDE ( r_ld_acl_t_poll_get = 0x40036024 ); +PROVIDE ( r_ld_acl_t_poll_set = 0x40036068 ); +PROVIDE ( r_ld_acl_tx_enc = 0x400362f8 ); +PROVIDE ( r_ld_acl_unsniff = 0x400361e0 ); +PROVIDE ( r_ld_active_check = 0x4003cac4 ); +PROVIDE ( r_ld_afh_ch_assess_data_get = 0x4003caec ); +PROVIDE ( r_ld_bcst_acl_data_tx = 0x40038d3c ); +PROVIDE ( r_ld_bcst_acl_init = 0x40038bd0 ); +PROVIDE ( r_ld_bcst_acl_reset = 0x40038bdc ); +PROVIDE ( r_ld_bcst_acl_start = 0x4003882c ); +PROVIDE ( r_ld_bcst_afh_update = 0x40038f3c ); +PROVIDE ( r_ld_bcst_enc_key_load = 0x4003906c ); +PROVIDE ( r_ld_bcst_lmp_tx = 0x40038bf8 ); +PROVIDE ( r_ld_bcst_tx_enc = 0x40038ff8 ); +PROVIDE ( r_ld_bd_addr_get = 0x4003ca20 ); +PROVIDE ( r_ld_channel_assess = 0x4003c184 ); +PROVIDE ( r_ld_class_of_dev_get = 0x4003ca34 ); +PROVIDE ( r_ld_class_of_dev_set = 0x4003ca50 ); +PROVIDE ( r_ld_csb_rx_afh_update = 0x40039af4 ); +PROVIDE ( r_ld_csb_rx_init = 0x40039690 ); +PROVIDE ( r_ld_csb_rx_reset = 0x4003969c ); +PROVIDE ( r_ld_csb_rx_start = 0x4003972c ); +PROVIDE ( r_ld_csb_rx_stop = 0x40039bb8 ); +PROVIDE ( r_ld_csb_tx_afh_update = 0x4003a5fc ); +PROVIDE ( r_ld_csb_tx_clr_data = 0x4003a71c ); +PROVIDE ( r_ld_csb_tx_dis = 0x4003a5e8 ); +PROVIDE ( r_ld_csb_tx_en = 0x4003a1c0 ); +PROVIDE ( r_ld_csb_tx_init = 0x4003a0e8 ); +PROVIDE ( r_ld_csb_tx_reset = 0x4003a0f8 ); +PROVIDE ( r_ld_csb_tx_set_data = 0x4003a6c0 ); +PROVIDE ( r_ld_fm_clk_isr = 0x4003a7a8 ); +PROVIDE ( r_ld_fm_frame_isr = 0x4003a82c ); +PROVIDE ( r_ld_fm_init = 0x4003a760 ); +PROVIDE ( r_ld_fm_prog_check = 0x4003ab28 ); +PROVIDE ( r_ld_fm_prog_disable = 0x4003a984 ); +PROVIDE ( r_ld_fm_prog_enable = 0x4003a944 ); +PROVIDE ( r_ld_fm_prog_push = 0x4003a9d4 ); +PROVIDE ( r_ld_fm_reset = 0x4003a794 ); +PROVIDE ( r_ld_fm_rx_isr = 0x4003a7f4 ); +PROVIDE ( r_ld_fm_sket_isr = 0x4003a8a4 ); +PROVIDE ( r_ld_init = 0x4003c294 ); +PROVIDE ( r_ld_inq_init = 0x4003b15c ); +PROVIDE ( r_ld_inq_reset = 0x4003b168 ); +PROVIDE ( r_ld_inq_start = 0x4003b1f0 ); +PROVIDE ( r_ld_inq_stop = 0x4003b4f0 ); +PROVIDE ( r_ld_iscan_eir_get = 0x4003c118 ); +PROVIDE ( r_ld_iscan_eir_set = 0x4003bfa0 ); +PROVIDE ( r_ld_iscan_init = 0x4003b9f0 ); +PROVIDE ( r_ld_iscan_reset = 0x4003ba14 ); +PROVIDE ( r_ld_iscan_restart = 0x4003ba44 ); +PROVIDE ( r_ld_iscan_start = 0x4003bb28 ); +PROVIDE ( r_ld_iscan_stop = 0x4003bf1c ); +PROVIDE ( r_ld_iscan_tx_pwr_get = 0x4003c138 ); +PROVIDE ( r_ld_page_init = 0x4003d808 ); +PROVIDE ( r_ld_page_reset = 0x4003d814 ); +PROVIDE ( r_ld_page_start = 0x4003d848 ); +PROVIDE ( r_ld_page_stop = 0x4003da54 ); +PROVIDE ( r_ld_pca_coarse_clock_adjust = 0x4003e324 ); +PROVIDE ( r_ld_pca_init = 0x4003deb4 ); +PROVIDE ( r_ld_pca_initiate_clock_dragging = 0x4003e4ac ); +PROVIDE ( r_ld_pca_local_config = 0x4003df6c ); +PROVIDE ( r_ld_pca_mws_frame_sync = 0x4003e104 ); +PROVIDE ( r_ld_pca_mws_moment_offset_gt = 0x4003e278 ); +PROVIDE ( r_ld_pca_mws_moment_offset_lt = 0x4003e280 ); +PROVIDE ( r_ld_pca_reporting_enable = 0x4003e018 ); +PROVIDE ( r_ld_pca_reset = 0x4003df0c ); +PROVIDE ( r_ld_pca_update_target_offset = 0x4003e050 ); +PROVIDE ( r_ld_pscan_evt_handler = 0x4003f238 ); +PROVIDE ( r_ld_pscan_init = 0x4003f474 ); +PROVIDE ( r_ld_pscan_reset = 0x4003f498 ); +PROVIDE ( r_ld_pscan_restart = 0x4003f4b8 ); +PROVIDE ( r_ld_pscan_start = 0x4003f514 ); +PROVIDE ( r_ld_pscan_stop = 0x4003f618 ); +PROVIDE ( r_ld_read_clock = 0x4003c9e4 ); +PROVIDE ( r_ld_reset = 0x4003c714 ); +PROVIDE ( r_ld_sched_acl_add = 0x4003f978 ); +PROVIDE ( r_ld_sched_acl_remove = 0x4003f99c ); +PROVIDE ( r_ld_sched_compute = 0x4003f6f8 ); +PROVIDE ( r_ld_sched_init = 0x4003f7ac ); +PROVIDE ( r_ld_sched_inq_add = 0x4003f8a8 ); +PROVIDE ( r_ld_sched_inq_remove = 0x4003f8d0 ); +PROVIDE ( r_ld_sched_iscan_add = 0x4003f7e8 ); +PROVIDE ( r_ld_sched_iscan_remove = 0x4003f808 ); +PROVIDE ( r_ld_sched_page_add = 0x4003f910 ); +PROVIDE ( r_ld_sched_page_remove = 0x4003f938 ); +PROVIDE ( r_ld_sched_pscan_add = 0x4003f828 ); +PROVIDE ( r_ld_sched_pscan_remove = 0x4003f848 ); +PROVIDE ( r_ld_sched_reset = 0x4003f7d4 ); +PROVIDE ( r_ld_sched_sco_add = 0x4003fa4c ); +PROVIDE ( r_ld_sched_sco_remove = 0x4003fa9c ); +PROVIDE ( r_ld_sched_sniff_add = 0x4003f9c4 ); +PROVIDE ( r_ld_sched_sniff_remove = 0x4003fa0c ); +PROVIDE ( r_ld_sched_sscan_add = 0x4003f868 ); +PROVIDE ( r_ld_sched_sscan_remove = 0x4003f888 ); +PROVIDE ( r_ld_sco_audio_isr = 0x40037cc8 ); +PROVIDE ( r_ld_sco_data_tx = 0x40037ee8 ); +PROVIDE ( r_ld_sco_start = 0x40037110 ); +PROVIDE ( r_ld_sco_stop = 0x40037c40 ); +PROVIDE ( r_ld_sco_update = 0x40037a74 ); +PROVIDE ( r_ld_sscan_activated = 0x4004031c ); +PROVIDE ( r_ld_sscan_init = 0x400402f0 ); +PROVIDE ( r_ld_sscan_reset = 0x400402fc ); +PROVIDE ( r_ld_sscan_start = 0x40040384 ); +PROVIDE ( r_ld_strain_init = 0x400409f4 ); +PROVIDE ( r_ld_strain_reset = 0x40040a00 ); +PROVIDE ( r_ld_strain_start = 0x40040a8c ); +PROVIDE ( r_ld_strain_stop = 0x40040df0 ); +PROVIDE ( r_ld_timing_accuracy_get = 0x4003caac ); +PROVIDE ( r_ld_util_active_master_afh_map_get = 0x4004131c ); +PROVIDE ( r_ld_util_active_master_afh_map_set = 0x40041308 ); +PROVIDE ( r_ld_util_bch_create = 0x40040fcc ); +PROVIDE ( r_ld_util_fhs_pk = 0x400411c8 ); +PROVIDE ( r_ld_util_fhs_unpk = 0x40040e54 ); +PROVIDE ( r_ld_util_stp_pk = 0x400413f4 ); +PROVIDE ( r_ld_util_stp_unpk = 0x40041324 ); +PROVIDE ( r_ld_version_get = 0x4003ca6c ); +PROVIDE ( r_ld_wlcoex_set = 0x4003caf8 ); +PROVIDE ( r_llc_ch_assess_get_current_ch_map = 0x40041574 ); +PROVIDE ( r_llc_ch_assess_get_local_ch_map = 0x4004150c ); +PROVIDE ( r_llc_ch_assess_local = 0x40041494 ); +PROVIDE ( r_llc_ch_assess_merge_ch = 0x40041588 ); +PROVIDE ( r_llc_ch_assess_reass_ch = 0x400415c0 ); +PROVIDE ( r_llc_common_cmd_complete_send = 0x40044eac ); +PROVIDE ( r_llc_common_cmd_status_send = 0x40044ee0 ); +PROVIDE ( r_llc_common_enc_change_evt_send = 0x40044f6c ); +PROVIDE ( r_llc_common_enc_key_ref_comp_evt_send = 0x40044f38 ); +PROVIDE ( r_llc_common_flush_occurred_send = 0x40044f0c ); +PROVIDE ( r_llc_common_nb_of_pkt_comp_evt_send = 0x40045000 ); +PROVIDE ( r_llc_con_update_complete_send = 0x40044d68 ); +PROVIDE ( r_llc_con_update_finished = 0x4004518c ); +PROVIDE ( r_llc_con_update_ind = 0x40045038 ); +PROVIDE ( r_llc_discon_event_complete_send = 0x40044a30 ); +PROVIDE ( r_llc_end_evt_defer = 0x40046330 ); +PROVIDE ( r_llc_feats_rd_event_send = 0x40044e0c ); +PROVIDE ( r_llc_init = 0x40044778 ); +PROVIDE ( r_llc_le_con_cmp_evt_send = 0x40044a78 ); +PROVIDE ( r_llc_llcp_ch_map_update_pdu_send = 0x40043f94 ); +PROVIDE ( r_llc_llcp_con_param_req_pdu_send = 0x400442fc ); +PROVIDE ( r_llc_llcp_con_param_rsp_pdu_send = 0x40044358 ); +PROVIDE ( r_llc_llcp_con_update_pdu_send = 0x400442c4 ); +PROVIDE ( r_llc_llcp_enc_req_pdu_send = 0x40044064 ); +PROVIDE ( r_llc_llcp_enc_rsp_pdu_send = 0x40044160 ); +PROVIDE ( r_llc_llcp_feats_req_pdu_send = 0x400443b4 ); +PROVIDE ( r_llc_llcp_feats_rsp_pdu_send = 0x400443f0 ); +PROVIDE ( r_llc_llcp_get_autorize = 0x4004475c ); +PROVIDE ( r_llc_llcp_length_req_pdu_send = 0x40044574 ); +PROVIDE ( r_llc_llcp_length_rsp_pdu_send = 0x400445ac ); +PROVIDE ( r_llc_llcp_pause_enc_req_pdu_send = 0x40043fd8 ); +PROVIDE ( r_llc_llcp_pause_enc_rsp_pdu_send = 0x40044010 ); +PROVIDE ( r_llc_llcp_ping_req_pdu_send = 0x4004454c ); +PROVIDE ( r_llc_llcp_ping_rsp_pdu_send = 0x40044560 ); +PROVIDE ( r_llc_llcp_recv_handler = 0x40044678 ); +PROVIDE ( r_llc_llcp_reject_ind_pdu_send = 0x4004425c ); +PROVIDE ( r_llc_llcp_start_enc_req_pdu_send = 0x4004441c ); +PROVIDE ( r_llc_llcp_start_enc_rsp_pdu_send = 0x400441f8 ); +PROVIDE ( r_llc_llcp_terminate_ind_pdu_send = 0x400444b0 ); +PROVIDE ( r_llc_llcp_tester_send = 0x400445e4 ); +PROVIDE ( r_llc_llcp_unknown_rsp_send_pdu = 0x40044534 ); +PROVIDE ( r_llc_llcp_version_ind_pdu_send = 0x40043f6c ); +PROVIDE ( r_llc_lsto_con_update = 0x40045098 ); +PROVIDE ( r_llc_ltk_req_send = 0x40044dc0 ); +PROVIDE ( r_llc_map_update_finished = 0x40045260 ); +PROVIDE ( r_llc_map_update_ind = 0x400450f0 ); +PROVIDE ( r_llc_pdu_acl_tx_ack_defer = 0x400464dc ); +PROVIDE ( r_llc_pdu_defer = 0x40046528 ); +PROVIDE ( r_llc_pdu_llcp_tx_ack_defer = 0x400463ac ); +PROVIDE ( r_llc_reset = 0x400447b8 ); +PROVIDE ( r_llc_start = 0x400447f4 ); +PROVIDE ( r_llc_stop = 0x400449ac ); +PROVIDE ( r_llc_util_bw_mgt = 0x4004629c ); +PROVIDE ( r_llc_util_clear_operation_ptr = 0x40046234 ); +PROVIDE ( r_llc_util_dicon_procedure = 0x40046130 ); +PROVIDE ( r_llc_util_get_free_conhdl = 0x400460c8 ); +PROVIDE ( r_llc_util_get_nb_active_link = 0x40046100 ); +PROVIDE ( r_llc_util_set_auth_payl_to_margin = 0x400461f4 ); +PROVIDE ( r_llc_util_set_llcp_discard_enable = 0x400461c8 ); +PROVIDE ( r_llc_util_update_channel_map = 0x400461ac ); +PROVIDE ( r_llc_version_rd_event_send = 0x40044e60 ); +PROVIDE ( r_lld_adv_start = 0x40048b38 ); +PROVIDE ( r_lld_adv_stop = 0x40048ea0 ); +PROVIDE ( r_lld_ch_map_ind = 0x4004a2f4 ); +PROVIDE ( r_lld_con_param_req = 0x40049f0c ); +PROVIDE ( r_lld_con_param_rsp = 0x40049e00 ); +PROVIDE ( r_lld_con_start = 0x400491f8 ); +PROVIDE ( r_lld_con_stop = 0x40049fdc ); +PROVIDE ( r_lld_con_update_after_param_req = 0x40049bcc ); +PROVIDE ( r_lld_con_update_ind = 0x4004a30c ); +PROVIDE ( r_lld_con_update_req = 0x40049b60 ); +PROVIDE ( r_lld_core_reset = 0x40048a9c ); +PROVIDE ( r_lld_crypt_isr = 0x4004a324 ); +PROVIDE ( r_lld_evt_adv_create = 0x400481f4 ); +PROVIDE ( r_lld_evt_canceled = 0x400485c8 ); +PROVIDE ( r_lld_evt_channel_next = 0x40046aac ); +PROVIDE ( r_lld_evt_deffered_elt_handler = 0x400482bc ); +PROVIDE ( r_lld_evt_delete_elt_handler = 0x40046974 ); +PROVIDE ( r_lld_evt_delete_elt_push = 0x40046a3c ); +PROVIDE ( r_lld_evt_drift_compute = 0x40047670 ); +PROVIDE ( r_lld_evt_elt_delete = 0x40047538 ); +PROVIDE ( r_lld_evt_elt_insert = 0x400474c8 ); +PROVIDE ( r_lld_evt_end = 0x400483e8 ); +PROVIDE ( r_lld_evt_end_isr = 0x4004862c ); +PROVIDE ( r_lld_evt_init = 0x40046b3c ); +PROVIDE ( r_lld_evt_init_evt = 0x40046cd0 ); +PROVIDE ( r_lld_evt_move_to_master = 0x40047ba0 ); +PROVIDE ( r_lld_evt_move_to_slave = 0x40047e18 ); +PROVIDE ( r_lld_evt_prevent_stop = 0x40047adc ); +PROVIDE ( r_lld_evt_restart = 0x40046d50 ); +PROVIDE ( r_lld_evt_rx = 0x40048578 ); +PROVIDE ( r_lld_evt_rx_isr = 0x40048678 ); +PROVIDE ( r_lld_evt_scan_create = 0x40047ae8 ); +PROVIDE ( r_lld_evt_schedule = 0x40047908 ); +PROVIDE ( r_lld_evt_schedule_next = 0x400477dc ); +PROVIDE ( r_lld_evt_schedule_next_instant = 0x400476a8 ); +PROVIDE ( r_lld_evt_slave_update = 0x40048138 ); +PROVIDE ( r_lld_evt_update_create = 0x40047cd8 ); +PROVIDE ( r_lld_get_mode = 0x40049ff8 ); +PROVIDE ( r_lld_init = 0x4004873c ); +PROVIDE ( r_lld_move_to_master = 0x400499e0 ); +PROVIDE ( r_lld_move_to_slave = 0x4004a024 ); +PROVIDE ( r_lld_pdu_adv_pack = 0x4004b488 ); +PROVIDE ( r_lld_pdu_check = 0x4004ac34 ); +PROVIDE ( r_lld_pdu_data_send = 0x4004b018 ); +PROVIDE ( r_lld_pdu_data_tx_push = 0x4004aecc ); +PROVIDE ( r_lld_pdu_rx_handler = 0x4004b4d4 ); +PROVIDE ( r_lld_pdu_send_packet = 0x4004b774 ); +PROVIDE ( r_lld_pdu_tx_flush = 0x4004b414 ); +PROVIDE ( r_lld_pdu_tx_loop = 0x4004ae40 ); +PROVIDE ( r_lld_pdu_tx_prog = 0x4004b120 ); +PROVIDE ( r_lld_pdu_tx_push = 0x4004b080 ); +PROVIDE ( r_lld_ral_renew_req = 0x4004a73c ); +/**************************************************************************** + * configs/elf32-core/scripts/esp32_rom.ld + ****************************************************************************/ + +PROVIDE ( r_lld_scan_start = 0x40048ee0 ); +PROVIDE ( r_lld_scan_stop = 0x40049190 ); +PROVIDE ( r_lld_test_mode_rx = 0x4004a540 ); +PROVIDE ( r_lld_test_mode_tx = 0x4004a350 ); +PROVIDE ( r_lld_test_stop = 0x4004a710 ); +PROVIDE ( r_lld_util_anchor_point_move = 0x4004bacc ); +PROVIDE ( r_lld_util_compute_ce_max = 0x4004bc0c ); +PROVIDE ( r_lld_util_connection_param_set = 0x4004ba40 ); +PROVIDE ( r_lld_util_dle_set_cs_fields = 0x4004ba90 ); +PROVIDE ( r_lld_util_eff_tx_time_set = 0x4004bd88 ); +PROVIDE ( r_lld_util_elt_programmed = 0x4004bce0 ); +PROVIDE ( r_lld_util_flush_list = 0x4004bbd8 ); +PROVIDE ( r_lld_util_freq2chnl = 0x4004b9e4 ); +PROVIDE ( r_lld_util_get_bd_address = 0x4004b8ac ); +PROVIDE ( r_lld_util_get_local_offset = 0x4004ba10 ); +PROVIDE ( r_lld_util_get_peer_offset = 0x4004ba24 ); +PROVIDE ( r_lld_util_get_tx_pkt_cnt = 0x4004bd80 ); +PROVIDE ( r_lld_util_instant_get = 0x4004b890 ); +PROVIDE ( r_lld_util_instant_ongoing = 0x4004bbfc ); +PROVIDE ( r_lld_util_priority_set = 0x4004bd10 ); +PROVIDE ( r_lld_util_priority_update = 0x4004bd78 ); +PROVIDE ( r_lld_util_ral_force_rpa_renew = 0x4004b980 ); +PROVIDE ( r_lld_util_set_bd_address = 0x4004b8f8 ); +PROVIDE ( r_lld_wlcoex_set = 0x4004bd98 ); +PROVIDE ( r_llm_ble_ready = 0x4004cc34 ); +PROVIDE ( r_llm_common_cmd_complete_send = 0x4004d288 ); +PROVIDE ( r_llm_common_cmd_status_send = 0x4004d2b4 ); +PROVIDE ( r_llm_con_req_ind = 0x4004cc54 ); +PROVIDE ( r_llm_con_req_tx_cfm = 0x4004d158 ); +PROVIDE ( r_llm_create_con = 0x4004de78 ); +PROVIDE ( r_llm_encryption_done = 0x4004dff8 ); +PROVIDE ( r_llm_encryption_start = 0x4004e128 ); +PROVIDE ( r_llm_end_evt_defer = 0x4004eb6c ); +PROVIDE ( r_llm_init = 0x4004c9f8 ); +PROVIDE ( r_llm_le_adv_report_ind = 0x4004cdf4 ); +PROVIDE ( r_llm_pdu_defer = 0x4004ec48 ); +PROVIDE ( r_llm_ral_clear = 0x4004e1fc ); +PROVIDE ( r_llm_ral_dev_add = 0x4004e23c ); +PROVIDE ( r_llm_ral_dev_rm = 0x4004e3bc ); +PROVIDE ( r_llm_ral_get_rpa = 0x4004e400 ); +PROVIDE ( r_llm_ral_set_timeout = 0x4004e4a0 ); +PROVIDE ( r_llm_ral_update = 0x4004e4f8 ); +PROVIDE ( r_llm_set_adv_data = 0x4004d960 ); +PROVIDE ( r_llm_set_adv_en = 0x4004d7ec ); +PROVIDE ( r_llm_set_adv_param = 0x4004d5f4 ); +PROVIDE ( r_llm_set_scan_en = 0x4004db64 ); +PROVIDE ( r_llm_set_scan_param = 0x4004dac8 ); +PROVIDE ( r_llm_set_scan_rsp_data = 0x4004da14 ); +PROVIDE ( r_llm_test_mode_start_rx = 0x4004d534 ); +PROVIDE ( r_llm_test_mode_start_tx = 0x4004d2fc ); +PROVIDE ( r_llm_util_adv_data_update = 0x4004e8fc ); +PROVIDE ( r_llm_util_apply_bd_addr = 0x4004e868 ); +PROVIDE ( r_llm_util_bd_addr_in_ral = 0x4004eb08 ); +PROVIDE ( r_llm_util_bd_addr_in_wl = 0x4004e788 ); +PROVIDE ( r_llm_util_bd_addr_wl_position = 0x4004e720 ); +PROVIDE ( r_llm_util_bl_add = 0x4004e9ac ); +PROVIDE ( r_llm_util_bl_check = 0x4004e930 ); +PROVIDE ( r_llm_util_bl_rem = 0x4004ea70 ); +PROVIDE ( r_llm_util_check_address_validity = 0x4004e7e4 ); +PROVIDE ( r_llm_util_check_evt_mask = 0x4004e8b0 ); +PROVIDE ( r_llm_util_check_map_validity = 0x4004e800 ); +PROVIDE ( r_llm_util_get_channel_map = 0x4004e8d4 ); +PROVIDE ( r_llm_util_get_supp_features = 0x4004e8e8 ); +PROVIDE ( r_llm_util_set_public_addr = 0x4004e89c ); +PROVIDE ( r_llm_wl_clr = 0x4004dc54 ); +PROVIDE ( r_llm_wl_dev_add = 0x4004dcc0 ); +PROVIDE ( r_llm_wl_dev_add_hdl = 0x4004dd38 ); +PROVIDE ( r_llm_wl_dev_rem = 0x4004dcfc ); +PROVIDE ( r_llm_wl_dev_rem_hdl = 0x4004dde0 ); +PROVIDE ( r_lm_acl_disc = 0x4004f148 ); +PROVIDE ( r_LM_AddSniff = 0x40022d20 ); +PROVIDE ( r_lm_add_sync = 0x40051358 ); +PROVIDE ( r_lm_afh_activate_timer = 0x4004f444 ); +PROVIDE ( r_lm_afh_ch_ass_en_get = 0x4004f3f8 ); +PROVIDE ( r_lm_afh_host_ch_class_get = 0x4004f410 ); +PROVIDE ( r_lm_afh_master_ch_map_get = 0x4004f43c ); +PROVIDE ( r_lm_afh_peer_ch_class_set = 0x4004f418 ); +PROVIDE ( r_lm_check_active_sync = 0x40051334 ); +PROVIDE ( r_LM_CheckEdrFeatureRequest = 0x4002f90c ); +PROVIDE ( r_LM_CheckSwitchInstant = 0x4002f8c0 ); +PROVIDE ( r_lm_check_sync_hl_rsp = 0x4005169c ); +PROVIDE ( r_lm_clk_adj_ack_pending_clear = 0x4004f514 ); +PROVIDE ( r_lm_clk_adj_instant_pending_set = 0x4004f4d8 ); +PROVIDE ( r_LM_ComputePacketType = 0x4002f554 ); +PROVIDE ( r_LM_ComputeSniffSubRate = 0x400233ac ); +PROVIDE ( r_lm_debug_key_compare_192 = 0x4004f3a8 ); +PROVIDE ( r_lm_debug_key_compare_256 = 0x4004f3d0 ); +PROVIDE ( r_lm_dhkey_calc_init = 0x40013234 ); +PROVIDE ( r_lm_dhkey_compare = 0x400132d8 ); +PROVIDE ( r_lm_dut_mode_en_get = 0x4004f3ec ); +PROVIDE ( r_LM_ExtractMaxEncKeySize = 0x4001aca4 ); +PROVIDE ( r_lm_f1 = 0x40012bb8 ); +PROVIDE ( r_lm_f2 = 0x40012cfc ); +PROVIDE ( r_lm_f3 = 0x40013050 ); +PROVIDE ( r_lm_g = 0x40012f90 ); +PROVIDE ( r_LM_GetAFHSwitchInstant = 0x4002f86c ); +PROVIDE ( r_lm_get_auth_en = 0x4004f1ac ); +PROVIDE ( r_lm_get_common_pkt_types = 0x4002fa1c ); +PROVIDE ( r_LM_GetConnectionAcceptTimeout = 0x4004f1f4 ); +PROVIDE ( r_LM_GetFeature = 0x4002f924 ); +PROVIDE ( r_LM_GetLinkTimeout = 0x400233ec ); +PROVIDE ( r_LM_GetLocalNameSeg = 0x4004f200 ); +PROVIDE ( r_lm_get_loopback_mode = 0x4004f248 ); +PROVIDE ( r_LM_GetMasterEncKeySize = 0x4001b29c ); +PROVIDE ( r_LM_GetMasterEncRand = 0x4001b288 ); +PROVIDE ( r_LM_GetMasterKey = 0x4001b260 ); +PROVIDE ( r_LM_GetMasterKeyRand = 0x4001b274 ); +PROVIDE ( r_lm_get_min_sync_intv = 0x400517a8 ); +PROVIDE ( r_lm_get_nb_acl = 0x4004ef9c ); +PROVIDE ( r_lm_get_nb_sync_link = 0x4005179c ); +PROVIDE ( r_lm_get_nonce = 0x400131c4 ); +PROVIDE ( r_lm_get_oob_local_commit = 0x4004f374 ); +PROVIDE ( r_lm_get_oob_local_data_192 = 0x4004f2d4 ); +PROVIDE ( r_lm_get_oob_local_data_256 = 0x4004f318 ); +PROVIDE ( r_LM_GetPINType = 0x4004f1e8 ); +PROVIDE ( r_lm_get_priv_key_192 = 0x4004f278 ); +PROVIDE ( r_lm_get_priv_key_256 = 0x4004f2b8 ); +PROVIDE ( r_lm_get_pub_key_192 = 0x4004f258 ); +PROVIDE ( r_lm_get_pub_key_256 = 0x4004f298 ); +PROVIDE ( r_LM_GetQoSParam = 0x4002f6e0 ); +PROVIDE ( r_lm_get_sec_con_host_supp = 0x4004f1d4 ); +PROVIDE ( r_LM_GetSniffSubratingParam = 0x4002325c ); +PROVIDE ( r_lm_get_sp_en = 0x4004f1c0 ); +PROVIDE ( r_LM_GetSwitchInstant = 0x4002f7f8 ); +PROVIDE ( r_lm_get_synchdl = 0x4005175c ); +PROVIDE ( r_lm_get_sync_param = 0x400503b4 ); +PROVIDE ( r_lm_init = 0x4004ed34 ); +PROVIDE ( r_lm_init_sync = 0x400512d8 ); +PROVIDE ( r_lm_is_acl_con = 0x4004f47c ); +PROVIDE ( r_lm_is_acl_con_role = 0x4004f49c ); +PROVIDE ( r_lm_is_clk_adj_ack_pending = 0x4004f4e8 ); +PROVIDE ( r_lm_is_clk_adj_instant_pending = 0x4004f4c8 ); +PROVIDE ( r_lm_local_ext_fr_configured = 0x4004f540 ); +PROVIDE ( r_lm_look_for_stored_link_key = 0x4002f948 ); +PROVIDE ( r_lm_look_for_sync = 0x40051774 ); +PROVIDE ( r_lm_lt_addr_alloc = 0x4004ef1c ); +PROVIDE ( r_lm_lt_addr_free = 0x4004ef74 ); +PROVIDE ( r_lm_lt_addr_reserve = 0x4004ef48 ); +PROVIDE ( r_LM_MakeCof = 0x4002f84c ); +PROVIDE ( r_LM_MakeRandVec = 0x400112d8 ); +PROVIDE ( r_lm_master_clk_adj_req_handler = 0x40054180 ); +PROVIDE ( r_LM_MaxSlot = 0x4002f694 ); +PROVIDE ( r_lm_modif_sync = 0x40051578 ); +PROVIDE ( r_lm_n_is_zero = 0x40012170 ); +PROVIDE ( r_lm_num_clk_adj_ack_pending_set = 0x4004f500 ); +PROVIDE ( r_lm_oob_f1 = 0x40012e54 ); +PROVIDE ( r_lm_pca_sscan_link_get = 0x4004f560 ); +PROVIDE ( r_lm_pca_sscan_link_set = 0x4004f550 ); +PROVIDE ( r_lmp_pack = 0x4001135c ); +PROVIDE ( r_lmp_unpack = 0x4001149c ); +PROVIDE ( r_lm_read_features = 0x4004f0d8 ); +PROVIDE ( r_LM_RemoveSniff = 0x40023124 ); +PROVIDE ( r_LM_RemoveSniffSubrating = 0x400233c4 ); +PROVIDE ( r_lm_remove_sync = 0x400517c8 ); +PROVIDE ( r_lm_reset_sync = 0x40051304 ); +PROVIDE ( r_lm_role_switch_finished = 0x4004f028 ); +PROVIDE ( r_lm_role_switch_start = 0x4004efe0 ); +PROVIDE ( r_lm_sco_nego_end = 0x40051828 ); +PROVIDE ( r_LM_SniffSubrateNegoRequired = 0x40023334 ); +PROVIDE ( r_LM_SniffSubratingHlReq = 0x40023154 ); +PROVIDE ( r_LM_SniffSubratingPeerReq = 0x400231dc ); +PROVIDE ( r_lm_sp_debug_mode_get = 0x4004f398 ); +PROVIDE ( r_lm_sp_n192_convert_wnaf = 0x400123c0 ); +PROVIDE ( r_lm_sp_n_one = 0x400123a4 ); +PROVIDE ( r_lm_sp_p192_add = 0x40012828 ); +PROVIDE ( r_lm_sp_p192_dbl = 0x4001268c ); +PROVIDE ( r_lm_sp_p192_invert = 0x40012b6c ); +PROVIDE ( r_lm_sp_p192_point_jacobian_to_affine = 0x40012468 ); +PROVIDE ( r_lm_sp_p192_points_jacobian_to_affine = 0x400124e4 ); +PROVIDE ( r_lm_sp_p192_point_to_inf = 0x40012458 ); +PROVIDE ( r_lm_sp_pre_compute_points = 0x40012640 ); +PROVIDE ( r_lm_sp_sha256_calculate = 0x400121a0 ); +PROVIDE ( r_LM_SuppressAclPacket = 0x4002f658 ); +PROVIDE ( r_lm_sync_flow_ctrl_en_get = 0x4004f404 ); +PROVIDE ( r_LM_UpdateAclEdrPacketType = 0x4002f5d8 ); +PROVIDE ( r_LM_UpdateAclPacketType = 0x4002f584 ); +PROVIDE ( r_modules_funcs = 0x3ffafd6c ); +PROVIDE ( r_modules_funcs_p = 0x3ffafd68 ); +PROVIDE ( r_nvds_del = 0x400544c4 ); +PROVIDE ( r_nvds_get = 0x40054488 ); +PROVIDE ( r_nvds_init = 0x40054410 ); +PROVIDE ( r_nvds_lock = 0x400544fc ); +PROVIDE ( r_nvds_put = 0x40054534 ); +PROVIDE ( rom_abs_temp = 0x400054f0 ); +PROVIDE ( rom_bb_bss_bw_40_en = 0x4000401c ); +PROVIDE ( rom_bb_bss_cbw40_dig = 0x40003bac ); +PROVIDE ( rom_bb_rx_ht20_cen_bcov_en = 0x40003734 ); +PROVIDE ( rom_bb_tx_ht20_cen = 0x40003760 ); +PROVIDE ( rom_bb_wdg_test_en = 0x40003b70 ); +PROVIDE ( rom_cbw2040_cfg = 0x400040b0 ); +PROVIDE ( rom_check_noise_floor = 0x40003c78 ); +PROVIDE ( rom_chip_i2c_readReg = 0x40004110 ); +PROVIDE ( rom_chip_i2c_writeReg = 0x40004168 ); +PROVIDE ( rom_chip_v7_bt_init = 0x40004d8c ); +PROVIDE ( rom_chip_v7_rx_init = 0x40004cec ); +PROVIDE ( rom_chip_v7_rx_rifs_en = 0x40003d90 ); +PROVIDE ( rom_chip_v7_tx_init = 0x40004d18 ); +PROVIDE ( rom_clk_force_on_vit = 0x40003710 ); +PROVIDE ( rom_correct_rf_ana_gain = 0x400062a8 ); +PROVIDE ( rom_dc_iq_est = 0x400055c8 ); +PROVIDE ( rom_disable_agc = 0x40002fa4 ); +PROVIDE ( rom_enable_agc = 0x40002fcc ); +PROVIDE ( rom_en_pwdet = 0x4000506c ); +PROVIDE ( rom_gen_rx_gain_table = 0x40003e3c ); +PROVIDE ( rom_get_data_sat = 0x4000312c ); +PROVIDE ( rom_get_fm_sar_dout = 0x40005204 ); +PROVIDE ( rom_get_power_db = 0x40005fc8 ); +PROVIDE ( rom_get_pwctrl_correct = 0x400065d4 ); +PROVIDE ( rom_get_rfcal_rxiq_data = 0x40005bbc ); +PROVIDE ( rom_get_rf_gain_qdb = 0x40006290 ); +PROVIDE ( rom_get_sar_dout = 0x40006564 ); +PROVIDE ( rom_i2c_readReg = 0x40004148 ); +PROVIDE ( rom_i2c_readReg_Mask = 0x400041c0 ); +PROVIDE ( rom_i2c_writeReg = 0x400041a4 ); +PROVIDE ( rom_i2c_writeReg_Mask = 0x400041fc ); +PROVIDE ( rom_index_to_txbbgain = 0x40004df8 ); +PROVIDE ( rom_iq_est_disable = 0x40005590 ); +PROVIDE ( rom_iq_est_enable = 0x40005514 ); +PROVIDE ( rom_linear_to_db = 0x40005f64 ); +PROVIDE ( rom_loopback_mode_en = 0x400030f8 ); +PROVIDE ( rom_main = 0x400076c4 ); +PROVIDE ( rom_meas_tone_pwr_db = 0x40006004 ); +PROVIDE ( rom_mhz2ieee = 0x4000404c ); +PROVIDE ( rom_noise_floor_auto_set = 0x40003bdc ); +PROVIDE ( rom_pbus_debugmode = 0x40004458 ); +PROVIDE ( rom_pbus_force_mode = 0x40004270 ); +PROVIDE ( rom_pbus_force_test = 0x400043c0 ); +PROVIDE ( rom_pbus_rd = 0x40004414 ); +PROVIDE ( rom_pbus_rd_addr = 0x40004334 ); +PROVIDE ( rom_pbus_rd_shift = 0x40004374 ); +PROVIDE ( rom_pbus_rx_dco_cal = 0x40005620 ); +PROVIDE ( rom_pbus_set_dco = 0x40004638 ); +PROVIDE ( rom_pbus_set_rxgain = 0x40004480 ); +PROVIDE ( rom_pbus_workmode = 0x4000446c ); +PROVIDE ( rom_pbus_xpd_rx_off = 0x40004508 ); +PROVIDE ( rom_pbus_xpd_rx_on = 0x4000453c ); +PROVIDE ( rom_pbus_xpd_tx_off = 0x40004590 ); +PROVIDE ( rom_pbus_xpd_tx_on = 0x400045e0 ); +PROVIDE ( rom_phy_disable_agc = 0x40002f6c ); +PROVIDE ( rom_phy_disable_cca = 0x40003000 ); +PROVIDE ( rom_phy_enable_agc = 0x40002f88 ); +PROVIDE ( rom_phy_enable_cca = 0x4000302c ); +PROVIDE ( rom_phy_freq_correct = 0x40004b44 ); +PROVIDE ( rom_phyFuns = 0x3ffae0c0 ); +PROVIDE ( rom_phy_get_noisefloor = 0x40003c2c ); +PROVIDE ( rom_phy_get_vdd33 = 0x4000642c ); +PROVIDE ( rom_pow_usr = 0x40003044 ); +PROVIDE ( rom_read_sar_dout = 0x400051c0 ); +PROVIDE ( rom_restart_cal = 0x400046e0 ); +PROVIDE ( rom_rfcal_pwrctrl = 0x40006058 ); +PROVIDE ( rom_rfcal_rxiq = 0x40005b4c ); +PROVIDE ( rom_rfcal_txcap = 0x40005dec ); +PROVIDE ( rom_rfpll_reset = 0x40004680 ); +PROVIDE ( rom_rfpll_set_freq = 0x400047f8 ); +PROVIDE ( rom_rtc_mem_backup = 0x40003db4 ); +PROVIDE ( rom_rtc_mem_recovery = 0x40003df4 ); +PROVIDE ( rom_rx_gain_force = 0x4000351c ); +PROVIDE ( rom_rxiq_cover_mg_mp = 0x40005a68 ); +PROVIDE ( rom_rxiq_get_mis = 0x400058e4 ); +PROVIDE ( rom_rxiq_set_reg = 0x40005a00 ); +PROVIDE ( rom_set_cal_rxdc = 0x400030b8 ); +PROVIDE ( rom_set_chan_cal_interp = 0x40005ce0 ); +PROVIDE ( rom_set_channel_freq = 0x40004880 ); +PROVIDE ( rom_set_loopback_gain = 0x40003060 ); +PROVIDE ( rom_set_noise_floor = 0x40003d48 ); +PROVIDE ( rom_set_pbus_mem = 0x400031a4 ); +PROVIDE ( rom_set_rf_freq_offset = 0x40004ca8 ); +PROVIDE ( rom_set_rxclk_en = 0x40003594 ); +PROVIDE ( rom_set_txcap_reg = 0x40005d50 ); +PROVIDE ( rom_set_txclk_en = 0x40003564 ); +PROVIDE ( rom_spur_coef_cfg = 0x40003ac8 ); +PROVIDE ( rom_spur_reg_write_one_tone = 0x400037f0 ); +PROVIDE ( rom_start_tx_tone = 0x400036b4 ); +PROVIDE ( rom_start_tx_tone_step = 0x400035d0 ); +PROVIDE ( rom_stop_tx_tone = 0x40003f98 ); +PROVIDE ( _rom_store = 0x4000d66c ); +PROVIDE ( _rom_store_table = 0x4000d4f8 ); +PROVIDE ( rom_target_power_add_backoff = 0x40006268 ); +PROVIDE ( rom_tx_atten_set_interp = 0x400061cc ); +PROVIDE ( rom_txbbgain_to_index = 0x40004dc0 ); +PROVIDE ( rom_txcal_work_mode = 0x4000510c ); +PROVIDE ( rom_txdc_cal_init = 0x40004e10 ); +PROVIDE ( rom_txdc_cal_v70 = 0x40004ea4 ); +PROVIDE ( rom_txiq_cover = 0x4000538c ); +PROVIDE ( rom_txiq_get_mis_pwr = 0x400052dc ); +PROVIDE ( rom_txiq_set_reg = 0x40005154 ); +PROVIDE ( rom_tx_pwctrl_bg_init = 0x4000662c ); +PROVIDE ( rom_txtone_linear_pwr = 0x40005290 ); +PROVIDE ( rom_wait_rfpll_cal_end = 0x400047a8 ); +PROVIDE ( rom_write_gain_mem = 0x4000348c ); +PROVIDE ( rom_write_rfpll_sdm = 0x40004740 ); +PROVIDE ( roundup2 = 0x4000ab7c ); +PROVIDE ( r_plf_funcs_p = 0x3ffb8360 ); +PROVIDE ( r_rf_rw_bt_init = 0x40054868 ); +PROVIDE ( r_rf_rw_init = 0x40054b0c ); +PROVIDE ( r_rf_rw_le_init = 0x400549d0 ); +PROVIDE ( r_rwble_activity_ongoing_check = 0x40054d8c ); +PROVIDE ( r_rwble_init = 0x40054bf4 ); +PROVIDE ( r_rwble_isr = 0x40054e08 ); +PROVIDE ( r_rwble_reset = 0x40054ce8 ); +PROVIDE ( r_rwble_sleep_check = 0x40054d78 ); +PROVIDE ( r_rwble_version = 0x40054dac ); +PROVIDE ( r_rwbt_init = 0x40055160 ); +PROVIDE ( r_rwbt_isr = 0x40055248 ); +PROVIDE ( r_rwbt_reset = 0x400551bc ); +PROVIDE ( r_rwbt_sleep_check = 0x4005577c ); +PROVIDE ( r_rwbt_sleep_enter = 0x400557a4 ); +PROVIDE ( r_rwbt_sleep_wakeup = 0x400557fc ); +PROVIDE ( r_rwbt_sleep_wakeup_end = 0x400558cc ); +PROVIDE ( r_rwbt_version = 0x4005520c ); +PROVIDE ( r_rwip_assert_err = 0x40055f88 ); +PROVIDE ( r_rwip_check_wakeup_boundary = 0x400558fc ); +PROVIDE ( r_rwip_ext_wakeup_enable = 0x40055f3c ); +PROVIDE ( r_rwip_init = 0x4005595c ); +PROVIDE ( r_rwip_pca_clock_dragging_only = 0x40055f48 ); +PROVIDE ( r_rwip_prevent_sleep_clear = 0x40055ec8 ); +PROVIDE ( r_rwip_prevent_sleep_set = 0x40055e64 ); +PROVIDE ( r_rwip_reset = 0x40055ab8 ); +PROVIDE ( r_rwip_schedule = 0x40055b38 ); +PROVIDE ( r_rwip_sleep = 0x40055b5c ); +PROVIDE ( r_rwip_sleep_enable = 0x40055f30 ); +PROVIDE ( r_rwip_version = 0x40055b20 ); +PROVIDE ( r_rwip_wakeup = 0x40055dc4 ); +PROVIDE ( r_rwip_wakeup_delay_set = 0x40055e4c ); +PROVIDE ( r_rwip_wakeup_end = 0x40055e18 ); +PROVIDE ( r_rwip_wlcoex_set = 0x40055f60 ); +PROVIDE ( r_SHA_256 = 0x40013a90 ); +PROVIDE ( rtc_boot_control = 0x4000821c ); +PROVIDE ( rtc_get_reset_reason = 0x400081d4 ); +PROVIDE ( rtc_get_wakeup_cause = 0x400081f4 ); +PROVIDE ( rtc_select_apb_bridge = 0x40008288 ); +PROVIDE ( rwip_coex_cfg = 0x3ff9914c ); +PROVIDE ( rwip_priority = 0x3ff99159 ); +PROVIDE ( rwip_rf = 0x3ffbdb28 ); +PROVIDE ( rwip_rf_p_get = 0x400558f4 ); +PROVIDE ( r_XorKey = 0x400112c0 ); +PROVIDE ( sbrk = 0x400017f4 ); +PROVIDE ( _sbrk_r = 0x4000bce4 ); +PROVIDE ( scanf = 0x40058760 ); +PROVIDE ( _scanf_chars = 0x40058384 ); +PROVIDE ( _scanf_float = 0x4000bf18 ); +PROVIDE ( _scanf_i = 0x4005845c ); +PROVIDE ( _scanf_r = 0x4005879c ); +PROVIDE ( __sccl = 0x4000c498 ); +PROVIDE ( __sclose = 0x400011b8 ); +PROVIDE ( SelectSpiFunction = 0x40061f84 ); +PROVIDE ( SelectSpiQIO = 0x40061ddc ); +PROVIDE ( SendMsg = 0x40009384 ); +PROVIDE ( send_packet = 0x40009340 ); +PROVIDE ( __seofread = 0x40001148 ); +PROVIDE ( setjmp = 0x40056268 ); +PROVIDE ( setlocale = 0x40059568 ); +PROVIDE ( _setlocale_r = 0x4005950c ); +PROVIDE ( set_rtc_memory_crc = 0x40008208 ); +PROVIDE ( SetSpiDrvs = 0x40061e78 ); +PROVIDE ( __sf_fake_stderr = 0x3ff96458 ); +PROVIDE ( __sf_fake_stdin = 0x3ff96498 ); +PROVIDE ( __sf_fake_stdout = 0x3ff96478 ); +PROVIDE ( __sflush_r = 0x400591e0 ); +PROVIDE ( __sfmoreglue = 0x40001dc8 ); +PROVIDE ( __sfp = 0x40001e90 ); +PROVIDE ( __sfp_lock_acquire = 0x40001e08 ); +PROVIDE ( __sfp_lock_release = 0x40001e14 ); +PROVIDE ( __sfputs_r = 0x40057790 ); +PROVIDE ( __sfvwrite_r = 0x4005893c ); +PROVIDE ( sha1_prf = 0x40060ae8 ); +PROVIDE ( sha1_vector = 0x40060b64 ); +PROVIDE ( sha256_prf = 0x40060d70 ); +PROVIDE ( sha256_vector = 0x40060e08 ); +PROVIDE ( sha_blk_bits = 0x3ff99290 ); +PROVIDE ( sha_blk_bits_bytes = 0x3ff99288 ); +PROVIDE ( sha_blk_hash_bytes = 0x3ff9928c ); +PROVIDE ( sig_matrix = 0x3ffae293 ); +PROVIDE ( __sinit = 0x40001e38 ); +PROVIDE ( __sinit_lock_acquire = 0x40001e20 ); +PROVIDE ( __sinit_lock_release = 0x40001e2c ); +PROVIDE ( sip_after_tx_complete = 0x4000b358 ); +PROVIDE ( sip_alloc_to_host_evt = 0x4000ab9c ); +PROVIDE ( sip_get_ptr = 0x4000b34c ); +PROVIDE ( sip_get_state = 0x4000ae2c ); +PROVIDE ( sip_init_attach = 0x4000ae58 ); +PROVIDE ( sip_install_rx_ctrl_cb = 0x4000ae10 ); +PROVIDE ( sip_install_rx_data_cb = 0x4000ae20 ); +PROVIDE ( sip_is_active = 0x4000b3c0 ); +PROVIDE ( sip_post_init = 0x4000aed8 ); +PROVIDE ( sip_reclaim_from_host_cmd = 0x4000adbc ); +PROVIDE ( sip_reclaim_tx_data_pkt = 0x4000ad5c ); +PROVIDE ( siprintf = 0x40056c08 ); +PROVIDE ( _siprintf_r = 0x40056bbc ); +PROVIDE ( sip_send = 0x4000af54 ); +PROVIDE ( sip_to_host_chain_append = 0x4000aef8 ); +PROVIDE ( sip_to_host_evt_send_done = 0x4000ac04 ); +PROVIDE ( siscanf = 0x400587d0 ); +PROVIDE ( _siscanf_r = 0x40058830 ); +PROVIDE ( slc_add_credits = 0x4000baf4 ); +PROVIDE ( slc_enable = 0x4000b64c ); +PROVIDE ( slc_from_host_chain_fetch = 0x4000b7e8 ); +PROVIDE ( slc_from_host_chain_recycle = 0x4000bb10 ); +PROVIDE ( slc_has_pkt_to_host = 0x4000b5fc ); +PROVIDE ( slc_init_attach = 0x4000b918 ); +PROVIDE ( slc_init_credit = 0x4000badc ); +PROVIDE ( slc_reattach = 0x4000b62c ); +PROVIDE ( slc_send_to_host_chain = 0x4000b6a0 ); +PROVIDE ( slc_set_host_io_max_window = 0x4000b89c ); +PROVIDE ( slc_to_host_chain_recycle = 0x4000b758 ); +PROVIDE ( __smakebuf_r = 0x40059108 ); +PROVIDE ( sniprintf = 0x40056b4c ); +PROVIDE ( _sniprintf_r = 0x40056ae4 ); +PROVIDE ( snprintf = 0x40056b4c ); +PROVIDE ( _snprintf_r = 0x40056ae4 ); +PROVIDE ( software_reset = 0x4000824c ); +PROVIDE ( software_reset_cpu = 0x40008264 ); +PROVIDE ( specialModP256 = 0x4001600c ); +PROVIDE ( spi_cache_sram_init = 0x400626e4 ); +PROVIDE ( SPIClkConfig = 0x40062bc8 ); +PROVIDE ( SPI_Common_Command = 0x4006246c ); +PROVIDE ( spi_dummy_len_fix = 0x40061d90 ); +PROVIDE ( SPI_Encrypt_Write = 0x40062e78 ); +PROVIDE ( SPIEraseArea = 0x400631ac ); +PROVIDE ( SPIEraseBlock = 0x40062c4c ); +PROVIDE ( SPIEraseChip = 0x40062c14 ); +PROVIDE ( SPIEraseSector = 0x40062ccc ); +PROVIDE ( spi_flash_attach = 0x40062a6c ); +PROVIDE ( SPILock = 0x400628f0 ); +PROVIDE ( SPIMasterReadModeCnfig = 0x40062b64 ); +PROVIDE ( spi_modes = 0x3ff99270 ); +PROVIDE ( SPIParamCfg = 0x40063238 ); +PROVIDE ( SPI_Prepare_Encrypt_Data = 0x40062e1c ); +PROVIDE ( SPIRead = 0x40062ed8 ); +PROVIDE ( SPIReadModeCnfig = 0x40062944 ); +/* This is static function, but can be used, not generated by script*/ +PROVIDE ( SPI_read_status = 0x4006226c ); +/* This is static function, but can be used, not generated by script*/ +PROVIDE ( SPI_read_status_high = 0x40062448 ); +PROVIDE ( SPIUnlock = 0x400628b0 ); +PROVIDE ( SPI_user_command_read = 0x400621b0 ); +PROVIDE ( spi_w25q16 = 0x3ffae270 ); +PROVIDE ( SPIWrite = 0x40062d50 ); +/* This is static function, but can be used, not generated by script*/ +PROVIDE ( SPI_write_enable = 0x40062320 ); +PROVIDE ( SPI_Write_Encrypt_Disable = 0x40062e60 ); +PROVIDE ( SPI_Write_Encrypt_Enable = 0x40062df4 ); +/* This is static function, but can be used, not generated by script*/ +PROVIDE ( SPI_write_status = 0x400622f0 ); +PROVIDE ( sprintf = 0x40056c08 ); +PROVIDE ( _sprintf_r = 0x40056bbc ); +PROVIDE ( __sprint_r = 0x400577e4 ); +PROVIDE ( srand = 0x40001004 ); +PROVIDE ( __sread = 0x40001118 ); +PROVIDE ( __srefill_r = 0x400593d4 ); +PROVIDE ( sscanf = 0x400587d0 ); +PROVIDE ( _sscanf_r = 0x40058830 ); +PROVIDE ( __sseek = 0x40001184 ); +PROVIDE ( __ssprint_r = 0x40056ff8 ); +PROVIDE ( __ssputs_r = 0x40056f2c ); +PROVIDE ( __ssrefill_r = 0x40057fec ); +PROVIDE ( __ssvfiscanf_r = 0x4005802c ); +PROVIDE ( __ssvfscanf_r = 0x4005802c ); +PROVIDE ( __stack = 0x3ffe3f20 ); +PROVIDE ( __stack_app = 0x3ffe7e30 ); +PROVIDE ( _stack_sentry = 0x3ffe1320 ); +PROVIDE ( _stack_sentry_app = 0x3ffe5230 ); +PROVIDE ( _start = 0x40000704 ); +PROVIDE ( start_tb_console = 0x4005a980 ); +PROVIDE ( _stat_r = 0x4000bcb4 ); +PROVIDE ( _stext = 0x40000560 ); +PROVIDE ( strcasecmp = 0x400011cc ); +PROVIDE ( strcasestr = 0x40001210 ); +PROVIDE ( strcat = 0x4000c518 ); +PROVIDE ( strchr = 0x4000c53c ); +PROVIDE ( strcmp = 0x40001274 ); +PROVIDE ( strcoll = 0x40001398 ); +PROVIDE ( strcpy = 0x400013ac ); +PROVIDE ( strcspn = 0x4000c558 ); +PROVIDE ( strdup = 0x4000143c ); +PROVIDE ( _strdup_r = 0x40001450 ); +PROVIDE ( strftime = 0x40059ab4 ); +PROVIDE ( strlcat = 0x40001470 ); +PROVIDE ( strlcpy = 0x4000c584 ); +PROVIDE ( strlen = 0x400014c0 ); +PROVIDE ( strlwr = 0x40001524 ); +PROVIDE ( strncasecmp = 0x40001550 ); +PROVIDE ( strncat = 0x4000c5c4 ); +PROVIDE ( strncmp = 0x4000c5f4 ); +PROVIDE ( strncpy = 0x400015d4 ); +PROVIDE ( strndup = 0x400016b0 ); +PROVIDE ( _strndup_r = 0x400016c4 ); +PROVIDE ( strnlen = 0x4000c628 ); +PROVIDE ( strrchr = 0x40001708 ); +PROVIDE ( strsep = 0x40001734 ); +PROVIDE ( strspn = 0x4000c648 ); +PROVIDE ( strstr = 0x4000c674 ); +PROVIDE ( __strtok_r = 0x4000c6a8 ); +PROVIDE ( strtok_r = 0x4000c70c ); +PROVIDE ( strtol = 0x4005681c ); +PROVIDE ( _strtol_r = 0x40056714 ); +PROVIDE ( strtoul = 0x4005692c ); +PROVIDE ( _strtoul_r = 0x40056834 ); +PROVIDE ( strupr = 0x4000174c ); +PROVIDE ( __subdf3 = 0x400026e4 ); +PROVIDE ( __submore = 0x40058f3c ); +PROVIDE ( __subsf3 = 0x400021d0 ); +PROVIDE ( SubtractBigHex256 = 0x40015bcc ); +PROVIDE ( SubtractBigHexMod256 = 0x40015e8c ); +PROVIDE ( SubtractBigHexUint32_256 = 0x40015f8c ); +PROVIDE ( SubtractFromSelfBigHex256 = 0x40015c20 ); +PROVIDE ( SubtractFromSelfBigHexSign256 = 0x40015dc8 ); +PROVIDE ( __subvdi3 = 0x40002d20 ); +PROVIDE ( __subvsi3 = 0x40002cf8 ); +PROVIDE ( _sungetc_r = 0x40057f6c ); +PROVIDE ( _svfiprintf_r = 0x40057100 ); +PROVIDE ( __svfiscanf_r = 0x40057b08 ); +PROVIDE ( _svfprintf_r = 0x40057100 ); +PROVIDE ( __svfscanf = 0x40057f04 ); +PROVIDE ( __svfscanf_r = 0x40057b08 ); +PROVIDE ( __swbuf = 0x40058cb4 ); +PROVIDE ( __swbuf_r = 0x40058bec ); +PROVIDE ( __swrite = 0x40001150 ); +PROVIDE ( __swsetup_r = 0x40058cc8 ); +PROVIDE ( sw_to_hw = 0x3ffb8d40 ); +PROVIDE ( _SyscallException = 0x400007cf ); +PROVIDE ( syscall_table_ptr_app = 0x3ffae020 ); +PROVIDE ( syscall_table_ptr_pro = 0x3ffae024 ); +PROVIDE ( _system_r = 0x4000bc10 ); +PROVIDE ( tdefl_compress = 0x400600bc ); +PROVIDE ( tdefl_compress_buffer = 0x400607f4 ); +PROVIDE ( tdefl_compress_mem_to_mem = 0x40060900 ); +PROVIDE ( tdefl_compress_mem_to_output = 0x400608e0 ); +PROVIDE ( tdefl_get_adler32 = 0x400608d8 ); +PROVIDE ( tdefl_get_prev_return_status = 0x400608d0 ); +PROVIDE ( tdefl_init = 0x40060810 ); +PROVIDE ( tdefl_write_image_to_png_file_in_memory = 0x4006091c ); +PROVIDE ( tdefl_write_image_to_png_file_in_memory_ex = 0x40060910 ); +PROVIDE ( time = 0x40001844 ); +PROVIDE ( __time_load_locale = 0x4000183c ); +PROVIDE ( times = 0x40001808 ); +PROVIDE ( _times_r = 0x4000bc40 ); +PROVIDE ( _timezone = 0x3ffae0a0 ); +PROVIDE ( tinfl_decompress = 0x4005ef30 ); +PROVIDE ( tinfl_decompress_mem_to_callback = 0x40060090 ); +PROVIDE ( tinfl_decompress_mem_to_mem = 0x40060050 ); +PROVIDE ( toascii = 0x4000c720 ); +PROVIDE ( tolower = 0x40001868 ); +PROVIDE ( toupper = 0x40001884 ); +PROVIDE ( __truncdfsf2 = 0x40002b90 ); +PROVIDE ( __tzcalc_limits = 0x400018a0 ); +PROVIDE ( __tz_lock = 0x40001a04 ); +PROVIDE ( _tzname = 0x3ffae030 ); +PROVIDE ( tzset = 0x40001a1c ); +PROVIDE ( _tzset_r = 0x40001a28 ); +PROVIDE ( __tz_unlock = 0x40001a10 ); +PROVIDE ( uartAttach = 0x40008fd0 ); +PROVIDE ( uart_baudrate_detect = 0x40009034 ); +PROVIDE ( uart_buff_switch = 0x400093c0 ); +PROVIDE ( UartConnCheck = 0x40008738 ); +PROVIDE ( UartConnectProc = 0x40008a04 ); +PROVIDE ( UartDev = 0x3ffe019c ); +PROVIDE ( uart_div_modify = 0x400090cc ); +PROVIDE ( UartDwnLdProc = 0x40008ce8 ); +PROVIDE ( UartGetCmdLn = 0x40009564 ); +PROVIDE ( Uart_Init = 0x40009120 ); +PROVIDE ( UartRegReadProc = 0x40008a58 ); +PROVIDE ( UartRegWriteProc = 0x40008a14 ); +PROVIDE ( uart_rx_intr_handler = 0x40008f4c ); +PROVIDE ( uart_rx_one_char = 0x400092d0 ); +PROVIDE ( uart_rx_one_char_block = 0x400092a4 ); +PROVIDE ( uart_rx_readbuff = 0x40009394 ); +PROVIDE ( UartRxString = 0x400092fc ); +PROVIDE ( UartSetBaudProc = 0x40008aac ); +PROVIDE ( UartSpiAttachProc = 0x40008a6c ); +PROVIDE ( UartSpiReadProc = 0x40008a80 ); +PROVIDE ( uart_tx_flush = 0x40009258 ); +PROVIDE ( uart_tx_one_char = 0x40009200 ); +PROVIDE ( uart_tx_one_char2 = 0x4000922c ); +PROVIDE ( uart_tx_switch = 0x40009028 ); +PROVIDE ( uart_tx_wait_idle = 0x40009278 ); +PROVIDE ( __ucmpdi2 = 0x40063840 ); +PROVIDE ( __udivdi3 = 0x4000cff8 ); +PROVIDE ( __udivmoddi4 = 0x40064ab0 ); +PROVIDE ( __udivsi3 = 0x4000c7c8 ); +PROVIDE ( __udiv_w_sdiv = 0x40064aa8 ); +PROVIDE ( __umoddi3 = 0x4000d280 ); +PROVIDE ( __umodsi3 = 0x4000c7d0 ); +PROVIDE ( __umulsidi3 = 0x4000c7d8 ); +PROVIDE ( ungetc = 0x400590f4 ); +PROVIDE ( _ungetc_r = 0x40058fa0 ); +PROVIDE ( _unlink_r = 0x4000bc84 ); +PROVIDE ( __unorddf2 = 0x400637f4 ); +PROVIDE ( __unordsf2 = 0x40063478 ); +PROVIDE ( user_code_start = 0x3ffe0400 ); +PROVIDE ( _UserExceptionVector = 0x40000340 ); +PROVIDE ( utoa = 0x40056258 ); +PROVIDE ( __utoa = 0x400561f0 ); +PROVIDE ( vasiprintf = 0x40056eb8 ); +PROVIDE ( _vasiprintf_r = 0x40056e80 ); +PROVIDE ( vasniprintf = 0x40056e58 ); +PROVIDE ( _vasniprintf_r = 0x40056df8 ); +PROVIDE ( vasnprintf = 0x40056e58 ); +PROVIDE ( _vasnprintf_r = 0x40056df8 ); +PROVIDE ( vasprintf = 0x40056eb8 ); +PROVIDE ( _vasprintf_r = 0x40056e80 ); +PROVIDE ( VerifyFlashMd5Proc = 0x40008c44 ); +PROVIDE ( veryBigHexP256 = 0x3ff9736c ); +PROVIDE ( vfiprintf = 0x40057ae8 ); +PROVIDE ( _vfiprintf_r = 0x40057850 ); +PROVIDE ( vfiscanf = 0x40057eb8 ); +PROVIDE ( _vfiscanf_r = 0x40057f24 ); +PROVIDE ( vfprintf = 0x40057ae8 ); +PROVIDE ( _vfprintf_r = 0x40057850 ); +PROVIDE ( vfscanf = 0x40057eb8 ); +PROVIDE ( _vfscanf_r = 0x40057f24 ); +PROVIDE ( viprintf = 0x400569b4 ); +PROVIDE ( _viprintf_r = 0x400569e4 ); +PROVIDE ( viscanf = 0x40058698 ); +PROVIDE ( _viscanf_r = 0x400586c8 ); +PROVIDE ( vprintf = 0x400569b4 ); +PROVIDE ( _vprintf_r = 0x400569e4 ); +PROVIDE ( vscanf = 0x40058698 ); +PROVIDE ( _vscanf_r = 0x400586c8 ); +PROVIDE ( vsiprintf = 0x40056ac4 ); +PROVIDE ( _vsiprintf_r = 0x40056a90 ); +PROVIDE ( vsiscanf = 0x40058740 ); +PROVIDE ( _vsiscanf_r = 0x400586f8 ); +PROVIDE ( vsniprintf = 0x40056a68 ); +PROVIDE ( _vsniprintf_r = 0x40056a14 ); +PROVIDE ( vsnprintf = 0x40056a68 ); +PROVIDE ( _vsnprintf_r = 0x40056a14 ); +PROVIDE ( vsprintf = 0x40056ac4 ); +PROVIDE ( _vsprintf_r = 0x40056a90 ); +PROVIDE ( vsscanf = 0x40058740 ); +PROVIDE ( _vsscanf_r = 0x400586f8 ); +PROVIDE ( wcrtomb = 0x40058920 ); +PROVIDE ( _wcrtomb_r = 0x400588d8 ); +PROVIDE ( __wctomb = 0x3ff96540 ); +PROVIDE ( _wctomb_r = 0x40058f14 ); +PROVIDE ( _WindowOverflow12 = 0x40000100 ); +PROVIDE ( _WindowOverflow4 = 0x40000000 ); +PROVIDE ( _WindowOverflow8 = 0x40000080 ); +PROVIDE ( _WindowUnderflow12 = 0x40000140 ); +PROVIDE ( _WindowUnderflow4 = 0x40000040 ); +PROVIDE ( _WindowUnderflow8 = 0x400000c0 ); +PROVIDE ( write = 0x4000181c ); +PROVIDE ( _write_r = 0x4000bd70 ); +PROVIDE ( xthal_bcopy = 0x4000c098 ); +PROVIDE ( xthal_copy123 = 0x4000c124 ); +PROVIDE ( xthal_get_ccompare = 0x4000c078 ); +PROVIDE ( xthal_get_ccount = 0x4000c050 ); +PROVIDE ( xthal_get_interrupt = 0x4000c1e4 ); +PROVIDE ( xthal_get_intread = 0x4000c1e4 ); +PROVIDE ( Xthal_intlevel = 0x3ff9c2b4 ); +PROVIDE ( xthal_memcpy = 0x4000c0bc ); +PROVIDE ( xthal_set_ccompare = 0x4000c058 ); +PROVIDE ( xthal_set_intclear = 0x4000c1ec ); +PROVIDE ( _xtos_alloca_handler = 0x40000010 ); +PROVIDE ( _xtos_cause3_handler = 0x40000dd8 ); +PROVIDE ( _xtos_c_handler_table = 0x3ffe0548 ); +PROVIDE ( _xtos_c_wrapper_handler = 0x40000de8 ); +PROVIDE ( _xtos_enabled = 0x3ffe0650 ); +PROVIDE ( _xtos_exc_handler_table = 0x3ffe0448 ); +PROVIDE ( _xtos_interrupt_mask_table = 0x3ffe0758 ); +PROVIDE ( _xtos_interrupt_table = 0x3ffe0658 ); +PROVIDE ( _xtos_ints_off = 0x4000bfac ); +PROVIDE ( _xtos_ints_on = 0x4000bf88 ); +PROVIDE ( _xtos_intstruct = 0x3ffe0650 ); +PROVIDE ( _xtos_l1int_handler = 0x40000814 ); +PROVIDE ( _xtos_p_none = 0x4000bfd4 ); +PROVIDE ( _xtos_restore_intlevel = 0x40000928 ); +PROVIDE ( _xtos_return_from_exc = 0x4000c034 ); +PROVIDE ( _xtos_set_exception_handler = 0x4000074c ); +PROVIDE ( _xtos_set_interrupt_handler = 0x4000bf78 ); +PROVIDE ( _xtos_set_interrupt_handler_arg = 0x4000bf34 ); +PROVIDE ( _xtos_set_intlevel = 0x4000bfdc ); +PROVIDE ( _xtos_set_min_intlevel = 0x4000bff8 ); +PROVIDE ( _xtos_set_vpri = 0x40000934 ); +PROVIDE ( _xtos_syscall_handler = 0x40000790 ); +PROVIDE ( _xtos_unhandled_exception = 0x4000c024 ); +PROVIDE ( _xtos_unhandled_interrupt = 0x4000c01c ); +PROVIDE ( _xtos_vpri_enabled = 0x3ffe0654 ); diff --git a/configs/esp32-core/src/Makefile b/configs/esp32-core/src/Makefile index 017d00f499..a2f4f134f4 100644 --- a/configs/esp32-core/src/Makefile +++ b/configs/esp32-core/src/Makefile @@ -35,7 +35,15 @@ -include $(TOPDIR)/Make.defs +SCRIPTDIR = $(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts +CONFIGFILE = $(TOPDIR)$(DELIM)include$(DELIM)nuttx$(DELIM)config.h +SCRIPTIN = esp32.ld +SCRIPTOUT = esp32_out.ld + ASRCS = CSRCS = include $(TOPDIR)/configs/Board.mk + +$(SCRIPTOUT): $(SCRIPTIN) $(CONFIGFILE) + $(call PREPROCESS, $<, $(SCRIPTIN)) -- GitLab From 6745690a6f094b034cb2a803689e6efbc176ea25 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 18 Oct 2016 09:46:48 -0600 Subject: [PATCH 104/734] configs/Board.mk: Add extra clean operations --- configs/Board.mk | 2 ++ configs/esp32-core/src/Makefile | 8 ++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/configs/Board.mk b/configs/Board.mk index a04da66427..13226676b6 100644 --- a/configs/Board.mk +++ b/configs/Board.mk @@ -127,9 +127,11 @@ depend: .depend clean: $(call DELFILE, libboard$(LIBEXT)) $(call CLEAN) + $(EXTRA_CLEAN) distclean: clean $(call DELFILE, Make.dep) $(call DELFILE, .depend) + $(EXTRA_DISTCLEAN) -include Make.dep diff --git a/configs/esp32-core/src/Makefile b/configs/esp32-core/src/Makefile index a2f4f134f4..48b013f367 100644 --- a/configs/esp32-core/src/Makefile +++ b/configs/esp32-core/src/Makefile @@ -37,12 +37,16 @@ SCRIPTDIR = $(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts CONFIGFILE = $(TOPDIR)$(DELIM)include$(DELIM)nuttx$(DELIM)config.h -SCRIPTIN = esp32.ld -SCRIPTOUT = esp32_out.ld ASRCS = CSRCS = +SCRIPTIN = esp32.ld +SCRIPTOUT = esp32_out.ld + +EXTRA_CLEAN = +EXTRA_DISTCLEAN = $(call DELFILE, $(SCRIPTOUT)) + include $(TOPDIR)/configs/Board.mk $(SCRIPTOUT): $(SCRIPTIN) $(CONFIGFILE) -- GitLab From 054a1a8231163e5c8c786677b49ed59f7841caab Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 18 Oct 2016 09:41:16 -0600 Subject: [PATCH 105/734] ESP32 Core: Refresh configuration --- arch/xtensa/Kconfig | 3 +++ configs/esp32-core/nsh/defconfig | 8 ++++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 889b8d798c..2ff92ee1bc 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -60,5 +60,8 @@ config ARCH_CHIP default "esp32" if ARCH_CHIP_ESP32 source arch/xtensa/src/lx6/Kconfig +if ARCH_CHIP_ESP32 +source arch/xtensa/src/esp32/Kconfig +endif endif # ARCH_XTENSA diff --git a/configs/esp32-core/nsh/defconfig b/configs/esp32-core/nsh/defconfig index 14d63fcdc9..895a2d6bac 100644 --- a/configs/esp32-core/nsh/defconfig +++ b/configs/esp32-core/nsh/defconfig @@ -64,6 +64,7 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set CONFIG_ARCH_XTENSA=y @@ -79,6 +80,9 @@ CONFIG_XTENSA_HAVE_INTERRUPTS=y # CONFIG_XTENSA_USE_SWPRI is not set CONFIG_XTENSA_CALL0_ABI=y # CONFIG_XTENSA_USE_OVLY is not set +CONFIG_ESP32_BT_RESERVE_DRAM=0 +CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0 +CONFIG_ESP32_ULP_COPROC_RESERVE_MEM=0 # # Architecture Options @@ -91,7 +95,7 @@ CONFIG_XTENSA_CALL0_ABI=y # CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set # CONFIG_ARCH_HAVE_ADDRENV is not set # CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set -# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_MULTICPU=y # CONFIG_ARCH_HAVE_VFORK is not set # CONFIG_ARCH_HAVE_MMU is not set # CONFIG_ARCH_HAVE_MPU is not set @@ -556,10 +560,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set -- GitLab From 8b25782d0112f152f8eccc3fecc8eb216113a038 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 18 Oct 2016 09:56:00 -0600 Subject: [PATCH 106/734] ESP32 Core: Correct linker script CFLAGS selection --- configs/esp32-core/nsh/Make.defs | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/configs/esp32-core/nsh/Make.defs b/configs/esp32-core/nsh/Make.defs index 3789e51c7c..eaf619d7c0 100644 --- a/configs/esp32-core/nsh/Make.defs +++ b/configs/esp32-core/nsh/Make.defs @@ -37,7 +37,10 @@ include ${TOPDIR}/.config include ${TOPDIR}/tools/Config.mk include ${TOPDIR}/arch/xtensa/src/lx6/Toolchain.defs -LDSCRIPT += -T esp32_out.ld -T esp32_common.ld -T esp32_rom.ld -T esp32_peripherals.ld +LDSCRIPT1 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_out.ld +LDSCRIPT2 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_common.ld +LDSCRIPT3 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_rom.ld +LDSCRIPT4 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_peripherals.ld ifeq ($(WINTOOL),y) # Windows-native toolchains @@ -46,13 +49,16 @@ ifeq ($(WINTOOL),y) MKDEP = $(TOPDIR)/tools/mkwindeps.sh ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" - ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" + ARCHSCRIPT = -T "${shell cygpath -w $(LDSCRIPT1)}" + ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT2)}" + ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT3)}" + ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT4)}" else # Linux/Cygwin-native toolchain MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) ARCHINCLUDES = -I. -isystem $(TOPDIR)/include ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx - ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) + ARCHSCRIPT = -T$(LDSCRIPT1) -T$(LDSCRIPT2) -T$(LDSCRIPT3) -T$(LDSCRIPT4) endif CC = $(CROSSDEV)gcc -- GitLab From e72fab6f265a9a253926c473446106a93604168f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 18 Oct 2016 10:54:26 -0600 Subject: [PATCH 107/734] Add a board context target --- configs/Board.mk | 3 +++ configs/Makefile | 8 ++++++++ configs/arduino-mega2560/src/Makefile | 2 ++ configs/skp16c26/src/Makefile | 2 ++ 4 files changed, 15 insertions(+) diff --git a/configs/Board.mk b/configs/Board.mk index 13226676b6..af932faa47 100644 --- a/configs/Board.mk +++ b/configs/Board.mk @@ -124,6 +124,9 @@ endif depend: .depend +context: $(EXTRA_CONTEXT_DEPENDENCY) + $(EXTRA_CONTEXT) + clean: $(call DELFILE, libboard$(LIBEXT)) $(call CLEAN) diff --git a/configs/Makefile b/configs/Makefile index 9a04b131bb..68a5fad87f 100644 --- a/configs/Makefile +++ b/configs/Makefile @@ -57,6 +57,11 @@ endif DUMMY_KCONFIG = $(TOPDIR)$(DELIM)configs$(DELIM)dummy$(DELIM)Kconfig +# The board configuration should be installed in the arch/ directory + +BOARD_DIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board +BOARD_INSTALLED = $(if $(wildcard $(BOARD_DIR)$(DELIM)Makefile),y,) + # Basic CONFIG_ASRCS = @@ -106,6 +111,9 @@ $(DUMMY_KCONFIG): $(BOARD_KCONFIG) dirlinks: $(DUMMY_KCONFIG) context: $(DUMMY_KCONFIG) +ifeq ($(BOARD_INSTALLED),y) + $(Q) $(MAKE) -C $(BOARD_DIR) TOPDIR="$(TOPDIR)" context +endif clean_context: $(call DELFILE, $(DUMMY_KCONFIG)) diff --git a/configs/arduino-mega2560/src/Makefile b/configs/arduino-mega2560/src/Makefile index 1f7743da6f..7e5911999e 100644 --- a/configs/arduino-mega2560/src/Makefile +++ b/configs/arduino-mega2560/src/Makefile @@ -87,6 +87,8 @@ libboard$(LIBEXT): $(OBJS) depend: .depend +context: + clean: $(call DELFILE, libboard$(LIBEXT)) $(call CLEAN) diff --git a/configs/skp16c26/src/Makefile b/configs/skp16c26/src/Makefile index 8b4f1312c6..a17f913472 100644 --- a/configs/skp16c26/src/Makefile +++ b/configs/skp16c26/src/Makefile @@ -65,6 +65,8 @@ libboard$(LIBEXT): $(OBJS) depend: .depend +context: + clean: $(call DELFILE, libboard$(LIBEXT)) $(call CLEAN) -- GitLab From 6d974a8c69da8ca83c239245f953c42a0fa30778 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 18 Oct 2016 11:30:30 -0600 Subject: [PATCH 108/734] ESP32: Correct logic to auto-generate esp_out.ld linker script --- configs/Board.mk | 5 +++-- .../esp32-core/scripts/{esp32.ld => esp32.template} | 2 +- configs/esp32-core/src/Makefile | 12 +++++++++--- 3 files changed, 13 insertions(+), 6 deletions(-) rename configs/esp32-core/scripts/{esp32.ld => esp32.template} (98%) diff --git a/configs/Board.mk b/configs/Board.mk index af932faa47..11f0ed4dc2 100644 --- a/configs/Board.mk +++ b/configs/Board.mk @@ -124,8 +124,9 @@ endif depend: .depend -context: $(EXTRA_CONTEXT_DEPENDENCY) - $(EXTRA_CONTEXT) +ifneq ($(BOARD_CONTEXT),y) +context: +endif clean: $(call DELFILE, libboard$(LIBEXT)) diff --git a/configs/esp32-core/scripts/esp32.ld b/configs/esp32-core/scripts/esp32.template similarity index 98% rename from configs/esp32-core/scripts/esp32.ld rename to configs/esp32-core/scripts/esp32.template index 68c0c73cf8..9fbe0f1ccc 100644 --- a/configs/esp32-core/scripts/esp32.ld +++ b/configs/esp32-core/scripts/esp32.template @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/elf32-core/scripts/esp32.ld + * configs/elf32-core/scripts/esp32.template * ESP32 Linker Script Memory Layout * * This file describes the memory layout (memory blocks) as virtual diff --git a/configs/esp32-core/src/Makefile b/configs/esp32-core/src/Makefile index 48b013f367..8abf354d6f 100644 --- a/configs/esp32-core/src/Makefile +++ b/configs/esp32-core/src/Makefile @@ -41,13 +41,19 @@ CONFIGFILE = $(TOPDIR)$(DELIM)include$(DELIM)nuttx$(DELIM)config.h ASRCS = CSRCS = -SCRIPTIN = esp32.ld -SCRIPTOUT = esp32_out.ld +SCRIPTIN = $(SCRIPTDIR)$(DELIM)esp32.template +SCRIPTOUT = $(SCRIPTDIR)$(DELIM)esp32_out.ld +BOARD_CONTEXT = y EXTRA_CLEAN = EXTRA_DISTCLEAN = $(call DELFILE, $(SCRIPTOUT)) +.PHONY = context + include $(TOPDIR)/configs/Board.mk $(SCRIPTOUT): $(SCRIPTIN) $(CONFIGFILE) - $(call PREPROCESS, $<, $(SCRIPTIN)) + # $(call PREPROCESS, $(SCRIPTIN), $@) + $(Q) $(CC) -isystem $(TOPDIR)/include -C -P -x c -E $(SCRIPTIN) -o $@ + +context: $(SCRIPTOUT) -- GitLab From 847d2b4218146a2e6566a47636b1b3a9b86c59ba Mon Sep 17 00:00:00 2001 From: Janne Rosberg Date: Tue, 18 Oct 2016 11:52:23 -0600 Subject: [PATCH 109/734] usbhost/composite: fix compile; missing semicolons --- drivers/usbhost/usbhost_composite.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usbhost/usbhost_composite.c b/drivers/usbhost/usbhost_composite.c index 42ad0bf030..64ce014250 100644 --- a/drivers/usbhost/usbhost_composite.c +++ b/drivers/usbhost/usbhost_composite.c @@ -641,7 +641,7 @@ int usbhost_composite(FAR struct usbhost_hubport_s *hport, if (priv == NULL) { - uerr("ERROR: Failed to allocate class container\n") + uerr("ERROR: Failed to allocate class container\n"); return -ENOMEM; } @@ -650,7 +650,7 @@ int usbhost_composite(FAR struct usbhost_hubport_s *hport, if (priv->members == NULL) { - uerr("ERROR: Failed to allocate class members\n") + uerr("ERROR: Failed to allocate class members\n"); ret = -ENOMEM; goto errout_with_container; } -- GitLab From 503a2472e71af6b20faa210b8e0164db14cd3c6f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 18 Oct 2016 12:42:57 -0600 Subject: [PATCH 110/734] Xtensa: Add assertion logic --- arch/xtensa/src/common/xtensa.h | 12 +- arch/xtensa/src/common/xtensa_assert.c | 160 ++++++++++++++ arch/xtensa/src/common/xtensa_dumpstate.c | 243 +++++++++++++++++++++ arch/xtensa/src/common/xtensa_initialize.c | 2 +- arch/xtensa/src/esp32/Make.defs | 18 +- arch/xtensa/src/esp32/esp32_start.c | 2 +- 6 files changed, 423 insertions(+), 14 deletions(-) create mode 100644 arch/xtensa/src/common/xtensa_assert.c create mode 100644 arch/xtensa/src/common/xtensa_dumpstate.c diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index 5d4a65f788..533713be23 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -190,7 +190,7 @@ extern uint32_t _ramfunc_sizeof; /* Size of ramfuncs */ #ifndef __ASSEMBLY__ /* Common Functions *********************************************************/ -/* Common functions defined in arch/mips/src/common. These may be replaced +/* Common functions defined in arch/xtensa/src/common. These may be replaced * with chip-specific functions of the same name if needed. See also * functions prototyped in include/nuttx/arch.h. */ @@ -240,7 +240,7 @@ int xtensa_swint(int irq, FAR void *context); void xtensa_sigdeliver(void); /* Chip-specific functions **************************************************/ -/* Chip specific functions defined in arch/mips/src/ */ +/* Chip specific functions defined in arch/xtensa/src/ */ /* IRQs */ void xtensa_irq_initialize(void); @@ -265,11 +265,11 @@ void up_addregion(void); void up_lowputc(char ch); #if CONFIG_NFILE_DESCRIPTORS > 0 -void up_earlyserialinit(void); -void up_serialinit(void); +void xtensa_earlyserialinit(void); +void xtensa_serial_initialize(void); #else -# define up_earlyserialinit() -# define up_serialinit() +# define xtensa_earlyserialinit() +# define xtensa_serial_initialize() #endif /* System timer */ diff --git a/arch/xtensa/src/common/xtensa_assert.c b/arch/xtensa/src/common/xtensa_assert.c new file mode 100644 index 0000000000..4e7577fb76 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_assert.c @@ -0,0 +1,160 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_assert.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "sched/sched.h" +#include "xtensa.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* USB trace dumping */ + +#ifndef CONFIG_USBDEV_TRACE +# undef CONFIG_ARCH_USBDUMP +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_assert + ****************************************************************************/ + +static void xtensa_assert(int errorcode) noreturn_function; +static void xtensa_assert(int errorcode) +{ + /* Are we in an interrupt handler or the idle task? */ + + if (g_current_regs || this_task()->pid == 0) + { + (void)up_irq_save(); + for (; ; ) + { +#ifdef CONFIG_ARCH_LEDS + board_autoled_on(LED_PANIC); + up_mdelay(250); + board_autoled_off(LED_PANIC); + up_mdelay(250); +#endif + } + } + else + { + exit(errorcode); + } +} + +/**************************************************************************** + * Name: assert_tracecallback + ****************************************************************************/ + +#ifdef CONFIG_ARCH_USBDUMP +static int usbtrace_syslog(FAR const char *fmt, ...) +{ + va_list ap; + int ret; + + /* Let vsyslog do the real work */ + + va_start(ap, fmt); + ret = vsyslog(LOG_EMERG, fmt, ap); + va_end(ap); + return ret; +} + +static int assert_tracecallback(FAR struct usbtrace_s *trace, FAR void *arg) +{ + usbtrace_trprintf(usbtrace_syslog, trace->event, trace->value); + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_assert + ****************************************************************************/ + +void up_assert(const uint8_t *filename, int lineno) +{ +#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT) + struct tcb_s *rtcb = this_task(); +#endif + + board_autoled_on(LED_ASSERTION); + +#if CONFIG_TASK_NAME_SIZE > 0 + _alert("Assertion failed at file:%s line: %d task: %s\n", + filename, lineno, rtcb->name); +#else + _alert("Assertion failed at file:%s line: %d\n", + filename, lineno); +#endif + + xtensa_dumpstate(); + +#ifdef CONFIG_ARCH_USBDUMP + /* Dump USB trace data */ + + (void)usbtrace_enumerate(assert_tracecallback, NULL); +#endif + +#ifdef CONFIG_BOARD_CRASHDUMP + board_crashdump(up_getsp(), this_task(), filename, lineno); +#endif + + xtensa_assert(EXIT_FAILURE); +} diff --git a/arch/xtensa/src/common/xtensa_dumpstate.c b/arch/xtensa/src/common/xtensa_dumpstate.c new file mode 100644 index 0000000000..0c28a63a7b --- /dev/null +++ b/arch/xtensa/src/common/xtensa_dumpstate.c @@ -0,0 +1,243 @@ +/**************************************************************************** + * arch/xtensa/src/mips32/xtensa_dumpstate.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "sched/sched.h" +#include "xtensa.h" + +#ifdef CONFIG_DEBUG_ALERT + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_getsp + ****************************************************************************/ + +/* I don't know if the builtin to get SP is enabled */ + +static inline uint32_t xtensa_getsp(void) +{ + register uint32_t sp; +#waning Missing logic + return sp; +} + +/**************************************************************************** + * Name: xtensa_stackdump + ****************************************************************************/ + +static void xtensa_stackdump(uint32_t sp, uint32_t stack_base) +{ + uint32_t stack ; + + for (stack = sp & ~0x1f; stack < stack_base; stack += 32) + { + uint32_t *ptr = (uint32_t *)stack; + _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", + stack, ptr[0], ptr[1], ptr[2], ptr[3], + ptr[4], ptr[5], ptr[6], ptr[7]); + } +} + +/**************************************************************************** + * Name: xtensa_registerdump + ****************************************************************************/ + +static inline void xtensa_registerdump(void) +{ + /* Are user registers available from interrupt processing? */ + + if (g_current_regs != NULL) + { + _alert(" EXIT: %08lx PC: %08lx PS: %08lx\n", + (unsigned long)g_current_regs[REG_EXIT], + (unsigned long)g_current_regs[REG_PC], + (unsigned long)g_current_regs[REG_PS]); + _alert(" A0: %08lx A1: %08lx A2: %08lx A3: %08lx\n", + (unsigned long)g_current_regs[REG_A0], + (unsigned long)g_current_regs[REG_A1], + (unsigned long)g_current_regs[REG_A2], + (unsigned long)g_current_regs[REG_A3]); + _alert(" A4: %08lx A5: %08lx A6: %08lx A7: %08lx\n", + (unsigned long)g_current_regs[REG_A4], + (unsigned long)g_current_regs[REG_A5], + (unsigned long)g_current_regs[REG_A6], + (unsigned long)g_current_regs[REG_A7]); + _alert(" A8: %08lx A9: %08lx A10: %08lx A11: %08lx\n", + (unsigned long)g_current_regs[REG_A8], + (unsigned long)g_current_regs[REG_A9], + (unsigned long)g_current_regs[REG_A10], + (unsigned long)g_current_regs[REG_A11]); + _alert(" A12: %08lx A13: %08lx A14: %08lx A15: %08lx\n", + (unsigned long)g_current_regs[REG_A12], + (unsigned long)g_current_regs[REG_A13], + (unsigned long)g_current_regs[REG_A14], + (unsigned long)g_current_regs[REG_A15]); + _alert(" SAR: %08lx CAUSE: %08lx VADDR: %08lx\n", + (unsigned long)g_current_regs[REG_EXIT], + (unsigned long)g_current_regs[REG_EXCCAUSE], + (unsigned long)g_current_regs[REG_EXCVADDR]); +#if CONFIG_XTENSA_HAVE_LOOPS + _alert(" LBEG: %08lx LEND: %08lx LCNT: %08lx\n", + (unsigned long)g_current_regs[REG_LBEG], + (unsigned long)g_current_regs[REG_LEND], + (unsigned long)g_current_regs[REG_LCOUNT]); +#endif +#ifndef CONFIG_XTENSA_CALL0_ABI + _alert(" TMP0: %08lx TMP1: %08lx TMP2: %08lx\n", + (unsigned long)g_current_regs[REG_TMP0], + (unsigned long)g_current_regs[REG_TMP1], + (unsigned long)g_current_regs[REG_TMP2]); +#endif + +#ifdef CONFIG_XTENSA_USE_SWPRI + _alert(" VPRI: %08lx\n", + (unsigned long)g_current_regs[REG_VPRI]); +#endif + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_dumpstate + ****************************************************************************/ + +void xtensa_dumpstate(void) +{ + struct tcb_s *rtcb = this_task(); + uint32_t sp = xtensa_getsp(); + uint32_t ustackbase; + uint32_t ustacksize; +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + uint32_t istackbase; + uint32_t istacksize; +#endif + + /* Get the limits on the user stack memory */ + + if (rtcb->pid == 0) + { + ustackbase = g_idle_topstack - 4; + ustacksize = CONFIG_IDLETHREAD_STACKSIZE; + } + else + { + ustackbase = (uint32_t)rtcb->adj_stack_ptr; + ustacksize = (uint32_t)rtcb->adj_stack_size; + } + + /* Get the limits on the interrupt stack memory */ + +#warning REVISIT interrupt stack +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + istackbase = (uint32_t)&g_intstackbase; + istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4; + + /* Show interrupt stack info */ + + _alert("sp: %08x\n", sp); + _alert("IRQ stack:\n"); + _alert(" base: %08x\n", istackbase); + _alert(" size: %08x\n", istacksize); + + /* Does the current stack pointer lie within the interrupt + * stack? + */ + + if (sp <= istackbase && sp > istackbase - istacksize) + { + /* Yes.. dump the interrupt stack */ + + xtensa_stackdump(sp, istackbase); + + /* Extract the user stack pointer which should lie + * at the base of the interrupt stack. + */ + + sp = g_intstackbase; + _alert("sp: %08x\n", sp); + } + + /* Show user stack info */ + + _alert("User stack:\n"); + _alert(" base: %08x\n", ustackbase); + _alert(" size: %08x\n", ustacksize); +#else + _alert("sp: %08x\n", sp); + _alert("stack base: %08x\n", ustackbase); + _alert("stack size: %08x\n", ustacksize); +#endif + + /* Dump the user stack if the stack pointer lies within the allocated user + * stack memory. + */ + + if (sp > ustackbase || sp <= ustackbase - ustacksize) + { +#if !defined(CONFIG_ARCH_INTERRUPTSTACK) || CONFIG_ARCH_INTERRUPTSTACK < 4 + _alert("ERROR: Stack pointer is not within allocated stack\n"); +#endif + } + else + { + xtensa_stackdump(sp, ustackbase); + } + + /* Then dump the registers (if available) */ + + xtensa_registerdump(); +} + +#endif /* CONFIG_ARCH_STACKDUMP */ diff --git a/arch/xtensa/src/common/xtensa_initialize.c b/arch/xtensa/src/common/xtensa_initialize.c index a66c3b8ecd..6b807d7abd 100644 --- a/arch/xtensa/src/common/xtensa_initialize.c +++ b/arch/xtensa/src/common/xtensa_initialize.c @@ -191,7 +191,7 @@ void up_initialize(void) /* Initialize the serial device driver */ #ifdef USE_SERIALDRIVER - up_serialinit(); + xtensa_serial_initialize(); #endif /* Initialize the console device driver (if it is other than the standard diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 4bda2cd0ab..3556729be7 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -41,15 +41,21 @@ HEAD_CSRC = esp32_start.c # Common XTENSA files (arch/xtensa/src/common) CMN_ASRCS = xtensa_irq.S -CMN_CSRCS = xtensa_allocateheap.c xtensa_copystate.c xtensa_createstack.c -CMN_CSRCS += xtensa_exit.c xtensa_idle.c xtensa_initialize.c -CMN_CSRCS += xtensa_initialstate.c xtensa_interruptcontext.c xtensa_lowputs.c -CMN_CSRCS += xtensa_mdelay.c xtensa_modifyreg8.c xtensa_modifyreg16.c -CMN_CSRCS += xtensa_modifyreg32.c xtensa_puts.c xtensa_releasestack.c -CMN_CSRCS += xtensa_stackframe.c xtensa_udelay.c xtensa_usestack.c +CMN_CSRCS = xtensa_allocateheap.c xtensa_assert.c xtensa_copystate.c +CMN_CSRCS += xtensa_createstack.c xtensa_exit.c xtensa_idle.c +CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c +CMN_CSRCS += xtensa_interruptcontext.c xtensa_lowputs.c xtensa_mdelay.c +CMN_CSRCS += xtensa_modifyreg8.c xtensa_modifyreg16.c xtensa_modifyreg32.c +CMN_CSRCS += xtensa_puts.c xtensa_releasestack.c xtensa_stackframe.c +CMN_CSRCS += xtensa_udelay.c xtensa_usestack.c # Configuration-dependent common XTENSA files +ifeq ($(CONFIG_DEBUG_ALERT),y) + CMN_CSRCS += xtensa_dumpstate.c +endif + + # Use of common/xtensa_etherstub.c is deprecated. The preferred mechanism # is to use CONFIG_NETDEV_LATEINIT=y to suppress the call to # up_netinitialize() in xtensa_initialize.c. Then this stub would not be diff --git a/arch/xtensa/src/esp32/esp32_start.c b/arch/xtensa/src/esp32/esp32_start.c index b7c37b87ad..8926f0e79c 100644 --- a/arch/xtensa/src/esp32/esp32_start.c +++ b/arch/xtensa/src/esp32/esp32_start.c @@ -110,7 +110,7 @@ void IRAM_ATTR __start(void) #ifdef USE_EARLYSERIALINIT /* Perform early serial initialization */ - up_earlyserialinit(); + xtensa_earlyserialinit(); #endif /* Initialize onboard resources */ -- GitLab From 6357970c5f02d1427f8664360269bccb5c5da161 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 18 Oct 2016 12:38:57 -0600 Subject: [PATCH 111/734] Xtensa: Fix some compilation issues --- arch/xtensa/include/irq.h | 2 +- arch/xtensa/src/common/xtensa_dumpstate.c | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index 0d7ef43807..a218a1f167 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -97,7 +97,7 @@ #define _REG_LOOPS_START (22) -#if CONFIG_XTENSA_HAVE_LOOPS +#ifdef CONFIG_XTENSA_HAVE_LOOPS # define REG_LBEG (_REG_LOOPS_START + 0) # define REG_LEND (_REG_LOOPS_START + 1) # define REG_LCOUNT (_REG_LOOPS_START + 2) diff --git a/arch/xtensa/src/common/xtensa_dumpstate.c b/arch/xtensa/src/common/xtensa_dumpstate.c index 0c28a63a7b..97128013cf 100644 --- a/arch/xtensa/src/common/xtensa_dumpstate.c +++ b/arch/xtensa/src/common/xtensa_dumpstate.c @@ -66,7 +66,7 @@ static inline uint32_t xtensa_getsp(void) { register uint32_t sp; -#waning Missing logic +#warning Missing logic return sp; } @@ -125,7 +125,7 @@ static inline void xtensa_registerdump(void) (unsigned long)g_current_regs[REG_EXIT], (unsigned long)g_current_regs[REG_EXCCAUSE], (unsigned long)g_current_regs[REG_EXCVADDR]); -#if CONFIG_XTENSA_HAVE_LOOPS +#ifdef CONFIG_XTENSA_HAVE_LOOPS _alert(" LBEG: %08lx LEND: %08lx LCNT: %08lx\n", (unsigned long)g_current_regs[REG_LBEG], (unsigned long)g_current_regs[REG_LEND], @@ -137,7 +137,6 @@ static inline void xtensa_registerdump(void) (unsigned long)g_current_regs[REG_TMP1], (unsigned long)g_current_regs[REG_TMP2]); #endif - #ifdef CONFIG_XTENSA_USE_SWPRI _alert(" VPRI: %08lx\n", (unsigned long)g_current_regs[REG_VPRI]); -- GitLab From 8c606c487808ee969c55c054dfa5628589cfbedf Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 18 Oct 2016 13:18:59 -0600 Subject: [PATCH 112/734] ESP32: Add more missing infrastructure --- arch/xtensa/src/common/xtensa.h | 4 +- arch/xtensa/src/common/xtensa_initialize.c | 2 +- arch/xtensa/src/esp32/Make.defs | 4 +- .../esp32_allocateheap.c} | 17 +++- configs/esp32-core/src/Makefile | 6 +- configs/esp32-core/src/esp32_appinit.c | 98 +++++++++++++++++++ configs/esp32-core/src/esp32_boot.c | 95 ++++++++++++++++++ configs/esp32-core/src/esp32_bringup.c | 69 +++++++++++++ 8 files changed, 288 insertions(+), 7 deletions(-) rename arch/xtensa/src/{common/xtensa_allocateheap.c => esp32/esp32_allocateheap.c} (87%) create mode 100644 configs/esp32-core/src/esp32_appinit.c create mode 100644 configs/esp32-core/src/esp32_boot.c create mode 100644 configs/esp32-core/src/esp32_bringup.c diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index 533713be23..aa49e00159 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -256,9 +256,9 @@ void weak_function xtensa_dma_initialize(void); /* Memory management */ #if CONFIG_MM_REGIONS > 1 -void up_addregion(void); +void xtensa_add_region(void); #else -# define up_addregion() +# define xtensa_add_region() #endif /* Serial output */ diff --git a/arch/xtensa/src/common/xtensa_initialize.c b/arch/xtensa/src/common/xtensa_initialize.c index 6b807d7abd..45ee3b4233 100644 --- a/arch/xtensa/src/common/xtensa_initialize.c +++ b/arch/xtensa/src/common/xtensa_initialize.c @@ -123,7 +123,7 @@ void up_initialize(void) /* Add any extra memory fragments to the memory manager */ - up_addregion(); + xtensa_add_region(); /* Initialize the interrupt subsystem */ diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 3556729be7..804a539c6a 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -41,7 +41,7 @@ HEAD_CSRC = esp32_start.c # Common XTENSA files (arch/xtensa/src/common) CMN_ASRCS = xtensa_irq.S -CMN_CSRCS = xtensa_allocateheap.c xtensa_assert.c xtensa_copystate.c +CMN_CSRCS = xtensa_assert.c xtensa_copystate.c CMN_CSRCS += xtensa_createstack.c xtensa_exit.c xtensa_idle.c CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c CMN_CSRCS += xtensa_interruptcontext.c xtensa_lowputs.c xtensa_mdelay.c @@ -70,7 +70,7 @@ endif # Required ESP32 files (arch/xtensa/src/lx6) CHIP_ASRCS = -CHIP_CSRCS = +CHIP_CSRCS = esp32_allocateheap.c esp32_start.c # Configuration-dependent ESP32 files diff --git a/arch/xtensa/src/common/xtensa_allocateheap.c b/arch/xtensa/src/esp32/esp32_allocateheap.c similarity index 87% rename from arch/xtensa/src/common/xtensa_allocateheap.c rename to arch/xtensa/src/esp32/esp32_allocateheap.c index 692624bece..4e613adc6d 100644 --- a/arch/xtensa/src/common/xtensa_allocateheap.c +++ b/arch/xtensa/src/esp32/esp32_allocateheap.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/common/xtensa_allocateheap.c + * arch/xtensa/src/esp32/esp32_allocateheap.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -73,3 +73,18 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) *heap_start = (FAR void *)g_idle_topstack; *heap_size = CONFIG_RAM_END - g_idle_topstack; } + +/**************************************************************************** + * Name: xtensa_add_region + * + * Description: + * Memory may be added in non-contiguous chunks. Additional chunks are + * added by calling this function. + * + ****************************************************************************/ + +#if CONFIG_MM_REGIONS > 1 +void xtensa_add_region(void) +{ +} +#endif diff --git a/configs/esp32-core/src/Makefile b/configs/esp32-core/src/Makefile index 8abf354d6f..2e23d2db4b 100644 --- a/configs/esp32-core/src/Makefile +++ b/configs/esp32-core/src/Makefile @@ -39,7 +39,11 @@ SCRIPTDIR = $(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts CONFIGFILE = $(TOPDIR)$(DELIM)include$(DELIM)nuttx$(DELIM)config.h ASRCS = -CSRCS = +CSRCS = esp32_boot.c esp32_bringup.c + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CONFIG_CSRCS += esp32_appinit.c +endif SCRIPTIN = $(SCRIPTDIR)$(DELIM)esp32.template SCRIPTOUT = $(SCRIPTDIR)$(DELIM)esp32_out.ld diff --git a/configs/esp32-core/src/esp32_appinit.c b/configs/esp32-core/src/esp32_appinit.c new file mode 100644 index 0000000000..2b94c9d9f6 --- /dev/null +++ b/configs/esp32-core/src/esp32_appinit.c @@ -0,0 +1,98 @@ +/**************************************************************************** + * config/esp32-core/src/esp32_appinit.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "esp32_core.h" + +#ifdef CONFIG_LIB_BOARDCTL + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef OK +# define OK 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_INITIALIZE + /* Board initialization already performed by board_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return esp32_bringup(); +#endif +} + +#endif /* CONFIG_LIB_BOARDCTL */ diff --git a/configs/esp32-core/src/esp32_boot.c b/configs/esp32-core/src/esp32_boot.c new file mode 100644 index 0000000000..6dfe57a5ed --- /dev/null +++ b/configs/esp32-core/src/esp32_boot.c @@ -0,0 +1,95 @@ +/************************************************************************************ + * configs/esp32-core/src/esp32_boot.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include +#include + +#include "esp32-core.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: esp32_board_initialize + * + * Description: + * All STM32 architectures must provide the following entry point. This entry point + * is called early in the initialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void esp32_board_initialize(void) +{ +} + +/**************************************************************************** + * Name: board_initialize + * + * Description: + * If CONFIG_BOARD_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_initialize(). board_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_INITIALIZE +void board_initialize(void) +{ + /* Perform board-specific initialization */ + + (void)esp32_bringup(); +} +#endif diff --git a/configs/esp32-core/src/esp32_bringup.c b/configs/esp32-core/src/esp32_bringup.c new file mode 100644 index 0000000000..13688c7fd1 --- /dev/null +++ b/configs/esp32-core/src/esp32_bringup.c @@ -0,0 +1,69 @@ +/**************************************************************************** + * config/esp32-core/src/esp32_bringup.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "esp32-core.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int esp32_bringup(void) +{ + return OK; +} -- GitLab From 4a7d7e9a5aa46d133eacb77eda3f0da02b31b0a0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 18 Oct 2016 13:21:56 -0600 Subject: [PATCH 113/734] ESP32: Forgot to add file in last commit --- configs/esp32-core/src/esp32-core.h | 82 +++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 configs/esp32-core/src/esp32-core.h diff --git a/configs/esp32-core/src/esp32-core.h b/configs/esp32-core/src/esp32-core.h new file mode 100644 index 0000000000..88e6f9fe79 --- /dev/null +++ b/configs/esp32-core/src/esp32-core.h @@ -0,0 +1,82 @@ +/**************************************************************************** + * configs/esp32-core/src/esp32-core.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIGS_ESP32_CORE_SRC_ESP32_CORE_H +#define __CONFIGS_ESP32_CORE_SRC_ESP32_CORE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library via board_app_initialize() + * + ****************************************************************************/ + +int esp32_bringup(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_ESP32_CORE_SRC_ESP32_CORE_H */ -- GitLab From 89851b744614ada77fa2caa976db682428b7ff6d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 18 Oct 2016 13:13:11 -0600 Subject: [PATCH 114/734] ESP32: Add .gitignore; minor compile fixes --- configs/esp32-core/scripts/.gitignore | 2 ++ configs/esp32-core/src/esp32_appinit.c | 5 +---- configs/esp32-core/src/esp32_bringup.c | 2 +- 3 files changed, 4 insertions(+), 5 deletions(-) create mode 100644 configs/esp32-core/scripts/.gitignore diff --git a/configs/esp32-core/scripts/.gitignore b/configs/esp32-core/scripts/.gitignore new file mode 100644 index 0000000000..1d86910067 --- /dev/null +++ b/configs/esp32-core/scripts/.gitignore @@ -0,0 +1,2 @@ +esp32_out.ld + diff --git a/configs/esp32-core/src/esp32_appinit.c b/configs/esp32-core/src/esp32_appinit.c index 2b94c9d9f6..b352aa2fd2 100644 --- a/configs/esp32-core/src/esp32_appinit.c +++ b/configs/esp32-core/src/esp32_appinit.c @@ -39,6 +39,7 @@ #include +#include #include #include "esp32_core.h" @@ -49,10 +50,6 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef OK -# define OK 0 -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/configs/esp32-core/src/esp32_bringup.c b/configs/esp32-core/src/esp32_bringup.c index 13688c7fd1..0267217785 100644 --- a/configs/esp32-core/src/esp32_bringup.c +++ b/configs/esp32-core/src/esp32_bringup.c @@ -38,7 +38,7 @@ ****************************************************************************/ #include - +#include #include "esp32-core.h" /**************************************************************************** -- GitLab From 847af7c3c1ef085bd820fd92e90405fb79797740 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 18 Oct 2016 13:30:07 -0600 Subject: [PATCH 115/734] Trivial change to .gitignore --- configs/esp32-core/scripts/.gitignore | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/esp32-core/scripts/.gitignore b/configs/esp32-core/scripts/.gitignore index 1d86910067..155d3f5034 100644 --- a/configs/esp32-core/scripts/.gitignore +++ b/configs/esp32-core/scripts/.gitignore @@ -1,2 +1,2 @@ -esp32_out.ld +/esp32_out.ld -- GitLab From 402b876869e8a3ae68b982830427a14450dcb76b Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Tue, 18 Oct 2016 13:32:03 -0600 Subject: [PATCH 116/734] Include wchar.h to lib_libvsprintf.c to fix compilation error --- libc/stdio/lib_libvsprintf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/libc/stdio/lib_libvsprintf.c b/libc/stdio/lib_libvsprintf.c index a103b0c4ee..21219849e6 100644 --- a/libc/stdio/lib_libvsprintf.c +++ b/libc/stdio/lib_libvsprintf.c @@ -39,6 +39,7 @@ #include +#include #include #include #include -- GitLab From 70d5c7753e43e452372490eaff06abd05a963a02 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Wed, 12 Oct 2016 15:43:35 -1000 Subject: [PATCH 117/734] Kinetis - Added missing headers --- arch/arm/src/kinetis/kinetis_pindma.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/kinetis/kinetis_pindma.c b/arch/arm/src/kinetis/kinetis_pindma.c index 40acdc036b..411f371bbb 100644 --- a/arch/arm/src/kinetis/kinetis_pindma.c +++ b/arch/arm/src/kinetis/kinetis_pindma.c @@ -37,12 +37,24 @@ * Included Files ****************************************************************************/ -#include #include +#include +#include +#include +#include + +#include + #include #include "up_internal.h" +#include "kinetis_config.h" +#include "chip.h" +#include "kinetis.h" + + + #ifdef CONFIG_KINETIS_DMA /**************************************************************************** -- GitLab From 42ac6ecebd289db6aaa964f6097968b66a49d457 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Wed, 12 Oct 2016 15:43:06 -1000 Subject: [PATCH 118/734] Kinetis broke out SPI to kinetis/kinetis_spi.h --- arch/arm/src/kinetis/kinetis.h | 73 ------------- arch/arm/src/kinetis/kinetis_spi.h | 166 +++++++++++++++++++++++++++++ 2 files changed, 166 insertions(+), 73 deletions(-) create mode 100644 arch/arm/src/kinetis/kinetis_spi.h diff --git a/arch/arm/src/kinetis/kinetis.h b/arch/arm/src/kinetis/kinetis.h index 76d0c4e595..74d7ca81b6 100644 --- a/arch/arm/src/kinetis/kinetis.h +++ b/arch/arm/src/kinetis/kinetis.h @@ -583,79 +583,6 @@ void kinetis_pindump(uint32_t pinset, const char *msg); void kinetis_clrpend(int irq); -/************************************************************************************ - * Name: kinetis_spi[n]select, kinetis_spi[n]status, and kinetis_spi[n]cmddata - * - * Description: - * These external functions must be provided by board-specific logic. They are - * implementations of the select, status, and cmddata methods of the SPI interface - * defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * including kinetis_spibus_initialize()) are provided by common Kinetis logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in kinetis_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide kinetis_spi[n]select() and kinetis_spi[n]status() functions - * in your board-specific logic. These functions will perform chip selection - * and status operations using GPIOs in the way your board is configured. - * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide - * kinetis_spi[n]cmddata() functions in your board-specific logic. These - * functions will perform cmd/data selection operations using GPIOs in the way - * your board is configured. - * 3. Add a call to kinetis_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by kinetis_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ************************************************************************************/ - -struct spi_dev_s; -enum spi_dev_e; - -#ifdef CONFIG_KINETIS_SPI0 -void kinetis_spi0select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); -uint8_t kinetis_spi0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); -#ifdef CONFIG_SPI_CMDDATA -int kinetis_spi0cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); -#endif -#endif -#ifdef CONFIG_KINETIS_SPI1 -void kinetis_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); -uint8_t kinetis_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); -#ifdef CONFIG_SPI_CMDDATA -int kinetis_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); -#endif -#endif -#ifdef CONFIG_KINETIS_SPI2 -void kinetis_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); -uint8_t kinetis_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); -#ifdef CONFIG_SPI_CMDDATA -int kinetis_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); -#endif -#endif - -/**************************************************************************** - * Name: ssp_flush - * - * Description: - * Flush and discard any words left in the RX fifo. This can be called - * from spi[n]select after a device is deselected (if you worry about such - * things). - * - * Input Parameters: - * dev - Device-specific state data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_KINETIS_SPI0) || defined(CONFIG_KINETIS_SPI1) || defined(CONFIG_KINETIS_SPI2) -struct spi_dev_s; -void spi_flush(FAR struct spi_dev_s *dev); -#endif /**************************************************************************** * Name: kinetis_dmainitialize diff --git a/arch/arm/src/kinetis/kinetis_spi.h b/arch/arm/src/kinetis/kinetis_spi.h new file mode 100644 index 0000000000..19ce126d10 --- /dev/null +++ b/arch/arm/src/kinetis/kinetis_spi.h @@ -0,0 +1,166 @@ +/**************************************************************************** + * arch/arm/src/kinetis/kinetis_spi.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_SPI_H +#define __ARCH_ARM_SRC_KINETIS_KINETIS_SPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip/kinetis_dspi.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +struct spi_dev_s; +enum spi_dev_e; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/************************************************************************************ + * Name: kinetis_spibus_initialize + * + * Description: + * Initialize the selected SPI bus + * + * Input Parameter: + * bus number (for hardware that has mutiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on succcess; a NULL on failure + * + ************************************************************************************/ + +FAR struct spi_dev_s *kinetis_spibus_initialize(int bus); + +/************************************************************************************ + * Name: kinetis_spi[n]select, kinetis_spi[n]status, and kinetis_spi[n]cmddata + * + * Description: + * These external functions must be provided by board-specific logic. They are + * implementations of the select, status, and cmddata methods of the SPI interface + * defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * including kinetis_spibus_initialize()) are provided by common Kinetis logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in kinetis_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide kinetis_spi[n]select() and kinetis_spi[n]status() functions + * in your board-specific logic. These functions will perform chip selection + * and status operations using GPIOs in the way your board is configured. + * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide + * kinetis_spi[n]cmddata() functions in your board-specific logic. These + * functions will perform cmd/data selection operations using GPIOs in the way + * your board is configured. + * 3. Add a call to kinetis_spibus_initialize() in your low level application + * initialization logic + * 4. The handle returned by kinetis_spibus_initialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ************************************************************************************/ + +#ifdef CONFIG_KINETIS_SPI0 +void kinetis_spi0select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t kinetis_spi0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int kinetis_spi0cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +#endif +#ifdef CONFIG_KINETIS_SPI1 +void kinetis_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t kinetis_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int kinetis_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +#endif +#ifdef CONFIG_KINETIS_SPI2 +void kinetis_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +uint8_t kinetis_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +int kinetis_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +#endif + +/**************************************************************************** + * Name: ssp_flush + * + * Description: + * Flush and discard any words left in the RX fifo. This can be called + * from spi[n]select after a device is deselected (if you worry about such + * things). + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#if defined(CONFIG_KINETIS_SPI0) || defined(CONFIG_KINETIS_SPI1) || defined(CONFIG_KINETIS_SPI2) +struct spi_dev_s; +void spi_flush(FAR struct spi_dev_s *dev); +#endif + + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_SPI_H */ -- GitLab From 4de46c848d389b19dcde12a97fb20c1085841329 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Wed, 12 Oct 2016 15:41:47 -1000 Subject: [PATCH 119/734] Broke out DMA to use the modern Nuttx chip inclusion - still STUBS --- arch/arm/src/kinetis/Make.defs | 4 + arch/arm/src/kinetis/kinetis.h | 157 --------------------- arch/arm/src/kinetis/kinetis_dma.c | 199 ++++++++++++++++++++++++++ arch/arm/src/kinetis/kinetis_dma.h | 219 +++++++++++++++++++++++++++++ 4 files changed, 422 insertions(+), 157 deletions(-) create mode 100644 arch/arm/src/kinetis/kinetis_dma.c create mode 100644 arch/arm/src/kinetis/kinetis_dma.h diff --git a/arch/arm/src/kinetis/Make.defs b/arch/arm/src/kinetis/Make.defs index b2f1046caa..f27bf25fae 100644 --- a/arch/arm/src/kinetis/Make.defs +++ b/arch/arm/src/kinetis/Make.defs @@ -131,6 +131,10 @@ ifeq ($(CONFIG_PWM),y) CHIP_CSRCS += kinetis_pwm.c endif +ifeq ($(CONFIG_PWM),y) +CHIP_CSRCS += kinetis_dma.c +endif + ifeq ($(CONFIG_I2C),y) CHIP_CSRCS += kinetis_i2c.c endif diff --git a/arch/arm/src/kinetis/kinetis.h b/arch/arm/src/kinetis/kinetis.h index 74d7ca81b6..b4832274c3 100644 --- a/arch/arm/src/kinetis/kinetis.h +++ b/arch/arm/src/kinetis/kinetis.h @@ -305,40 +305,6 @@ #define PIN30 (30 << _PIN_SHIFT) #define PIN31 (31 << _PIN_SHIFT) -/************************************************************************************ - * Public Types - ************************************************************************************/ - -typedef FAR void *DMA_HANDLE; -typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); - -/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ - -#ifdef CONFIG_DEBUG_DMA -struct kinetis_dmaglobalregs_s -{ -#warning "Missing logic" - /* Global Registers */ -}; - -struct kinetis_dmachanregs_s -{ -#warning "Missing logic" - /* Channel Registers */ -}; - -struct kinetis_dmaregs_s -{ - /* Global Registers */ - - struct kinetis_dmaglobalregs_s gbl; - - /* Channel Registers */ - - struct kinetis_dmachanregs_s ch; -}; -#endif - /************************************************************************************ * Inline Functions ************************************************************************************/ @@ -583,129 +549,6 @@ void kinetis_pindump(uint32_t pinset, const char *msg); void kinetis_clrpend(int irq); - -/**************************************************************************** - * Name: kinetis_dmainitialize - * - * Description: - * Initialize the GPDMA subsystem. - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_KINETIS_DMA -void kinetis_dmainitilaize(void); -#endif - -/**************************************************************************** - * Name: kinetis_dmachannel - * - * Description: - * Allocate a DMA channel. This function sets aside a DMA channel and - * gives the caller exclusive access to the DMA channel. - * - * Returned Value: - * One success, this function returns a non-NULL, void* DMA channel - * handle. NULL is returned on any failure. This function can fail only - * if no DMA channel is available. - * - ****************************************************************************/ - -#ifdef CONFIG_KINETIS_DMA -DMA_HANDLE kinetis_dmachannel(void); -#endif - -/**************************************************************************** - * Name: kinetis_dmafree - * - * Description: - * Release a DMA channel. NOTE: The 'handle' used in this argument must - * NEVER be used again until kinetis_dmachannel() is called again to re-gain - * a valid handle. - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_KINETIS_DMA -void kinetis_dmafree(DMA_HANDLE handle); -#endif - -/**************************************************************************** - * Name: kinetis_dmasetup - * - * Description: - * Configure DMA for one transfer. - * - ****************************************************************************/ - -#ifdef CONFIG_KINETIS_DMA -int kinetis_dmarxsetup(DMA_HANDLE handle, uint32_t control, uint32_t config, - uint32_t srcaddr, uint32_t destaddr, size_t nbytes); -#endif - -/**************************************************************************** - * Name: kinetis_dmastart - * - * Description: - * Start the DMA transfer - * - ****************************************************************************/ - -#ifdef CONFIG_KINETIS_DMA -int kinetis_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg); -#endif - -/**************************************************************************** - * Name: kinetis_dmastop - * - * Description: - * Cancel the DMA. After kinetis_dmastop() is called, the DMA channel is - * reset and kinetis_dmasetup() must be called before kinetis_dmastart() can be - * called again - * - ****************************************************************************/ - -#ifdef CONFIG_KINETIS_DMA -void kinetis_dmastop(DMA_HANDLE handle); -#endif - -/**************************************************************************** - * Name: kinetis_dmasample - * - * Description: - * Sample DMA register contents - * - ****************************************************************************/ - -#ifdef CONFIG_KINETIS_DMA -#ifdef CONFIG_DEBUG_DMA -void kinetis_dmasample(DMA_HANDLE handle, struct kinetis_dmaregs_s *regs); -#else -# define kinetis_dmasample(handle,regs) -#endif -#endif - -/**************************************************************************** - * Name: kinetis_dmadump - * - * Description: - * Dump previously sampled DMA register contents - * - ****************************************************************************/ - -#ifdef CONFIG_KINETIS_DMA -#ifdef CONFIG_DEBUG_DMA -void kinetis_dmadump(DMA_HANDLE handle, const struct kinetis_dmaregs_s *regs, - const char *msg); -#else -# define kinetis_dmadump(handle,regs,msg) -#endif -#endif - /**************************************************************************** * Name: sdhc_initialize * diff --git a/arch/arm/src/kinetis/kinetis_dma.c b/arch/arm/src/kinetis/kinetis_dma.c new file mode 100644 index 0000000000..fda8c5fb4f --- /dev/null +++ b/arch/arm/src/kinetis/kinetis_dma.c @@ -0,0 +1,199 @@ +/**************************************************************************** + * arch/arm/src/kinetis/kinetis_dma.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "kinetis_config.h" +#include "chip.h" +#include "kinetis_dma.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + + +/**************************************************************************** + * Name: kinetis_dmainitialize + * + * Description: + * Initialize the DMA subsystem. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void kinetis_dmainitilaize(void) +{ + +} + +/**************************************************************************** + * Name: kinetis_dmachannel + * + * Description: + * Allocate a DMA channel. This function sets aside a DMA channel and + * gives the caller exclusive access to the DMA channel. + * + * Returned Value: + * One success, this function returns a non-NULL, void* DMA channel + * handle. NULL is returned on any failure. This function can fail only + * if no DMA channel is available. + * + ****************************************************************************/ + +DMA_HANDLE kinetis_dmachannel(void) +{ + return NULL; +} + +/**************************************************************************** + * Name: kinetis_dmafree + * + * Description: + * Release a DMA channel. NOTE: The 'handle' used in this argument must + * NEVER be used again until kinetis_dmachannel() is called again to re-gain + * a valid handle. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void kinetis_dmafree(DMA_HANDLE handle) +{ + +} + +/**************************************************************************** + * Name: kinetis_dmasetup + * + * Description: + * Configure DMA for one transfer. + * + ****************************************************************************/ + +int kinetis_dmarxsetup(DMA_HANDLE handle, uint32_t control, uint32_t config, + uint32_t srcaddr, uint32_t destaddr, size_t nbytes) +{ + return -1; +} + +/**************************************************************************** + * Name: kinetis_dmastart + * + * Description: + * Start the DMA transfer + * + ****************************************************************************/ + +int kinetis_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg) +{ + return -1; +} + + +/**************************************************************************** + * Name: kinetis_dmastop + * + * Description: + * Cancel the DMA. After kinetis_dmastop() is called, the DMA channel is + * reset and kinetis_dmasetup() must be called before kinetis_dmastart() can be + * called again + * + ****************************************************************************/ + +void kinetis_dmastop(DMA_HANDLE handle) +{ +} + +/**************************************************************************** + * Name: kinetis_dmasample + * + * Description: + * Sample DMA register contents + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void kinetis_dmasample(DMA_HANDLE handle, struct kinetis_dmaregs_s *regs) +{ + +} +#endif + +/**************************************************************************** + * Name: kinetis_dmadump + * + * Description: + * Dump previously sampled DMA register contents + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void kinetis_dmadump(DMA_HANDLE handle, const struct kinetis_dmaregs_s *regs, + const char *msg) +{ + +} +#endif + diff --git a/arch/arm/src/kinetis/kinetis_dma.h b/arch/arm/src/kinetis/kinetis_dma.h new file mode 100644 index 0000000000..bea2649833 --- /dev/null +++ b/arch/arm/src/kinetis/kinetis_dma.h @@ -0,0 +1,219 @@ +/**************************************************************************** + * arch/arm/src/kenetis/kinetis_dma.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETEIS_KINETEIS_DMA_H +#define __ARCH_ARM_SRC_KINETEIS_KINETEIS_DMA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "chip/kinetis_dma.h" + +/**************************************************************************** + * Pre-processor Declarations + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +typedef FAR void *DMA_HANDLE; +typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); + +/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ + +#ifdef CONFIG_DEBUG_DMA +struct kinetis_dmaglobalregs_s +{ +#warning "Missing logic" + /* Global Registers */ +}; + +struct kinetis_dmachanregs_s +{ +#warning "Missing logic" + /* Channel Registers */ +}; + +struct kinetis_dmaregs_s +{ + /* Global Registers */ + + struct kinetis_dmaglobalregs_s gbl; + + /* Channel Registers */ + + struct kinetis_dmachanregs_s ch; +}; +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/**************************************************************************** + * Name: kinetis_dmainitialize + * + * Description: + * Initialize the GPDMA subsystem. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void kinetis_dmainitilaize(void); + +/**************************************************************************** + * Name: kinetis_dmachannel + * + * Description: + * Allocate a DMA channel. This function sets aside a DMA channel and + * gives the caller exclusive access to the DMA channel. + * + * Returned Value: + * One success, this function returns a non-NULL, void* DMA channel + * handle. NULL is returned on any failure. This function can fail only + * if no DMA channel is available. + * + ****************************************************************************/ + +DMA_HANDLE kinetis_dmachannel(void); + +/**************************************************************************** + * Name: kinetis_dmafree + * + * Description: + * Release a DMA channel. NOTE: The 'handle' used in this argument must + * NEVER be used again until kinetis_dmachannel() is called again to re-gain + * a valid handle. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void kinetis_dmafree(DMA_HANDLE handle); + +/**************************************************************************** + * Name: kinetis_dmasetup + * + * Description: + * Configure DMA for one transfer. + * + ****************************************************************************/ + +int kinetis_dmarxsetup(DMA_HANDLE handle, uint32_t control, uint32_t config, + uint32_t srcaddr, uint32_t destaddr, size_t nbytes); + +/**************************************************************************** + * Name: kinetis_dmastart + * + * Description: + * Start the DMA transfer + * + ****************************************************************************/ + +int kinetis_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg); + +/**************************************************************************** + * Name: kinetis_dmastop + * + * Description: + * Cancel the DMA. After kinetis_dmastop() is called, the DMA channel is + * reset and kinetis_dmasetup() must be called before kinetis_dmastart() can be + * called again + * + ****************************************************************************/ + +void kinetis_dmastop(DMA_HANDLE handle); + +/**************************************************************************** + * Name: kinetis_dmasample + * + * Description: + * Sample DMA register contents + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void kinetis_dmasample(DMA_HANDLE handle, struct kinetis_dmaregs_s *regs); +#else +# define kinetis_dmasample(handle,regs) +#endif + +/**************************************************************************** + * Name: kinetis_dmadump + * + * Description: + * Dump previously sampled DMA register contents + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void kinetis_dmadump(DMA_HANDLE handle, const struct kinetis_dmaregs_s *regs, + const char *msg); +#else +# define kinetis_dmadump(handle,regs,msg) +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_KINETEIS_KINETEIS_DMA_H */ -- GitLab From bce382da5277b3e2567c05864b54b50dec1ec177 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Sat, 15 Oct 2016 01:41:22 -1000 Subject: [PATCH 120/734] Kinetis Support ARMV7 Common Vector and FPU --- arch/arm/Kconfig | 1 + arch/arm/include/kinetis/irq.h | 425 +-------- arch/arm/include/kinetis/kinetis_k20irq.h | 200 ++++ arch/arm/include/kinetis/kinetis_k40irq.h | 200 ++++ arch/arm/include/kinetis/kinetis_k60irq.h | 200 ++++ arch/arm/include/kinetis/kinetis_k64irq.h | 190 ++++ arch/arm/include/kinetis/kinetis_k66irq.h | 206 ++++ arch/arm/src/kinetis/Make.defs | 41 +- arch/arm/src/kinetis/chip.h | 9 + .../arm/src/kinetis/chip/kinetis_k20vectors.h | 156 +++ .../arm/src/kinetis/chip/kinetis_k40vectors.h | 156 +++ .../arm/src/kinetis/chip/kinetis_k60vectors.h | 156 +++ .../arm/src/kinetis/chip/kinetis_k64vectors.h | 147 +++ .../arm/src/kinetis/chip/kinetis_k66vectors.h | 162 ++++ arch/arm/src/kinetis/kinetis_clrpend.c | 16 +- arch/arm/src/kinetis/kinetis_irq.c | 24 +- arch/arm/src/kinetis/kinetis_vectors.S | 889 ++---------------- 17 files changed, 1937 insertions(+), 1241 deletions(-) create mode 100644 arch/arm/include/kinetis/kinetis_k20irq.h create mode 100644 arch/arm/include/kinetis/kinetis_k40irq.h create mode 100644 arch/arm/include/kinetis/kinetis_k60irq.h create mode 100644 arch/arm/include/kinetis/kinetis_k64irq.h create mode 100644 arch/arm/include/kinetis/kinetis_k66irq.h create mode 100644 arch/arm/src/kinetis/chip/kinetis_k20vectors.h create mode 100644 arch/arm/src/kinetis/chip/kinetis_k40vectors.h create mode 100644 arch/arm/src/kinetis/chip/kinetis_k60vectors.h create mode 100644 arch/arm/src/kinetis/chip/kinetis_k64vectors.h create mode 100644 arch/arm/src/kinetis/chip/kinetis_k66vectors.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 63af8acafc..9b721e2a3e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -85,6 +85,7 @@ config ARCH_CHIP_KINETIS select ARM_HAVE_MPU_UNIFIED select ARCH_HAVE_FPU select ARCH_HAVE_RAMFUNCS + select ARCH_HAVE_CMNVECTOR ---help--- Freescale Kinetis Architectures (ARM Cortex-M4) diff --git a/arch/arm/include/kinetis/irq.h b/arch/arm/include/kinetis/irq.h index 1e45a5b4c6..6eb5f00a7c 100644 --- a/arch/arm/include/kinetis/irq.h +++ b/arch/arm/include/kinetis/irq.h @@ -1,8 +1,9 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/include/kinetis/irq.h * - * Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -31,10 +32,10 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/* This file should never be included directed but, rather, only indirectly through - * nuttx/irq.h +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h */ #ifndef __ARCH_ARM_INCLUDE_KINETIS_IRQ_H @@ -50,8 +51,8 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* IRQ numbers **********************************************************************/ -/* The IRQ numbers corresponds directly to vector numbers and hence map directly to + +/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to * bits in the NVIC. This does, however, waste several words of memory in the IRQ * to handle mapping tables. */ @@ -73,410 +74,20 @@ #define KINETIS_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ #define KINETIS_IRQ_SYSTICK (15) /* Vector 15: System tick */ -/* External interrupts (vectors >= 16) */ - -#define KINETIS_IRQ_EXTINT (16) +/* External interrupts (vectors >= 16). These definitions are chip-specific */ -/* K20 Family *********************************************************************** - * - * The interrupt vectors for the following parts is defined in Freescale document - * K20P64M72SF1RM - */ +#define KINETIS_IRQ_FIRST (16) /* Vector number of the first external interrupt */ #if defined(CONFIG_ARCH_FAMILY_K20) -# define KINETIS_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */ -# define KINETIS_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */ -# define KINETIS_IRQ_DMACH2 (18) /* Vector 18: DMA channel 2 transfer complete */ -# define KINETIS_IRQ_DMACH3 (19) /* Vector 19: DMA channel 3 transfer complete */ -# define KINETIS_IRQ_DMACH4 (20) /* Vector 20: DMA channel 4 transfer complete */ -# define KINETIS_IRQ_DMACH5 (21) /* Vector 21: DMA channel 5 transfer complete */ -# define KINETIS_IRQ_DMACH6 (22) /* Vector 22: DMA channel 6 transfer complete */ -# define KINETIS_IRQ_DMACH7 (23) /* Vector 23: DMA channel 7 transfer complete */ -# define KINETIS_IRQ_DMACH8 (24) /* Vector 24: DMA channel 8 transfer complete */ -# define KINETIS_IRQ_DMACH9 (25) /* Vector 25: DMA channel 9 transfer complete */ -# define KINETIS_IRQ_DMACH10 (26) /* Vector 26: DMA channel 10 transfer complete */ -# define KINETIS_IRQ_DMACH11 (27) /* Vector 27: DMA channel 11 transfer complete */ -# define KINETIS_IRQ_DMACH12 (28) /* Vector 28: DMA channel 12 transfer complete */ -# define KINETIS_IRQ_DMACH13 (29) /* Vector 29: DMA channel 13 transfer complete */ -# define KINETIS_IRQ_DMACH14 (30) /* Vector 30: DMA channel 14 transfer complete */ -# define KINETIS_IRQ_DMACH15 (31) /* Vector 31: DMA channel 15 transfer complete */ -# define KINETIS_IRQ_DMAERR (32) /* Vector 32: DMA error interrupt channels 0-15 */ -# define KINETIS_IRQ_FLASHCC (34) /* Vector 34: Flash memory command complete */ -# define KINETIS_IRQ_FLASHRC (35) /* Vector 35: Flash memory read collision */ -# define KINETIS_IRQ_SMCLVD (36) /* Vector 36: Mode Controller low-voltage - * detect, low-voltage warning */ -# define KINETIS_IRQ_LLWU (37) /* Vector 37: LLWU Normal Low Leakage Wakeup */ -# define KINETIS_IRQ_WDOG (38) /* Vector 38: Watchdog */ -# define KINETIS_IRQ_I2C0 (40) /* Vector 40: I2C0 */ -# define KINETIS_IRQ_I2C1 (41) /* Vector 41: I2C1 */ -# define KINETIS_IRQ_SPI0 (42) /* Vector 42: SPI0 all sources */ -# define KINETIS_IRQ_SPI1 (43) /* Vector 43: SPI1 all sources */ -# define KINETIS_IRQ_CAN0MB (45) /* Vector 45: CAN0 OR'ed Message buffer (0-15) */ -# define KINETIS_IRQ_CAN0BO (46) /* Vector 46: CAN0 Bus Off */ -# define KINETIS_IRQ_CAN0ERR (47) /* Vector 47: CAN0 Error */ -# define KINETIS_IRQ_CAN0TW (48) /* Vector 48: CAN0 Transmit Warning */ -# define KINETIS_IRQ_CAN0RW (49) /* Vector 49: CAN0 Receive Warning */ -# define KINETIS_IRQ_CAN0WU (50) /* Vector 50: CAN0 Wake UP */ -//TODO UART0_LON -# define KINETIS_IRQ_UART0S (61) /* Vector 61: UART0 status */ -# define KINETIS_IRQ_UART0E (62) /* Vector 62: UART0 error */ -# define KINETIS_IRQ_UART1S (63) /* Vector 63: UART1 status */ -# define KINETIS_IRQ_UART1E (64) /* Vector 64: UART1 error */ -# define KINETIS_IRQ_UART2S (65) /* Vector 65: UART2 status */ -# define KINETIS_IRQ_UART2E (66) /* Vector 66: UART2 error */ -# define KINETIS_IRQ_ADC0 (73) /* Vector 73: ADC0 */ -# define KINETIS_IRQ_ADC1 (74) /* Vector 74: ADC1 */ -# define KINETIS_IRQ_CMP0 (75) /* Vector 75: CMP0 */ -# define KINETIS_IRQ_CMP1 (76) /* Vector 76: CMP1 */ -# define KINETIS_IRQ_CMP2 (77) /* Vector 77: CMP2 */ -# define KINETIS_IRQ_FTM0 (78) /* Vector 78: FTM0 all sources */ -# define KINETIS_IRQ_FTM1 (79) /* Vector 79: FTM1 all sources */ -# define KINETIS_IRQ_FTM2 (80) /* Vector 80: FTM2 all sources */ -# define KINETIS_IRQ_CMT (81) /* Vector 81: CMT */ -# define KINETIS_IRQ_RTC (82) /* Vector 82: RTC alarm interrupt */ -//TODO RTC_SECOND -# define KINETIS_IRQ_PITCH0 (84) /* Vector 84: PIT channel 0 */ -# define KINETIS_IRQ_PITCH1 (85) /* Vector 85: PIT channel 1 */ -# define KINETIS_IRQ_PITCH2 (86) /* Vector 86: PIT channel 2 */ -# define KINETIS_IRQ_PITCH3 (87) /* Vector 87: PIT channel 3 */ -# define KINETIS_IRQ_PDB (88) /* Vector 88: PDB */ -# define KINETIS_IRQ_USBOTG (89) /* Vector 88: USB OTG */ -# define KINETIS_IRQ_USBCD (90) /* Vector 90: USB charger detect */ -# define KINETIS_IRQ_DAC0 (97) /* Vector 97: DAC0 */ -# define KINETIS_IRQ_TSI (99) /* Vector 97: TSI all sources */ -# define KINETIS_IRQ_MCG (100) /* Vector 100: MCG */ -# define KINETIS_IRQ_LPT (101) /* Vector 101: Low power timer */ -# define KINETIS_IRQ_PORTA (103) /* Vector 103: Pin detect port A */ -# define KINETIS_IRQ_PORTB (104) /* Vector 104: Pin detect port B */ -# define KINETIS_IRQ_PORTC (105) /* Vector 105: Pin detect port C */ -# define KINETIS_IRQ_PORTD (106) /* Vector 106: Pin detect port D */ -# define KINETIS_IRQ_PORTE (107) /* Vector 107: Pin detect port E */ -# define KINETIS_IRQ_SWI (110) /* Vector 110: Software interrupt */ - -# define NR_VECTORS (111) /* 111 vectors */ -# define NR_IRQS (111) /* 94 interrupts but 111 IRQ numbers */ - -/* K40 Family *********************************************************************** - * - * The interrupt vectors for the following parts is defined in Freescale document - * K40P144M100SF2RM - */ - +# include #elif defined(CONFIG_ARCH_FAMILY_K40) - -# define KINETIS_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */ -# define KINETIS_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */ -# define KINETIS_IRQ_DMACH2 (18) /* Vector 18: DMA channel 2 transfer complete */ -# define KINETIS_IRQ_DMACH3 (19) /* Vector 19: DMA channel 3 transfer complete */ -# define KINETIS_IRQ_DMACH4 (20) /* Vector 20: DMA channel 4 transfer complete */ -# define KINETIS_IRQ_DMACH5 (21) /* Vector 21: DMA channel 5 transfer complete */ -# define KINETIS_IRQ_DMACH6 (22) /* Vector 22: DMA channel 6 transfer complete */ -# define KINETIS_IRQ_DMACH7 (23) /* Vector 23: DMA channel 7 transfer complete */ -# define KINETIS_IRQ_DMACH8 (24) /* Vector 24: DMA channel 8 transfer complete */ -# define KINETIS_IRQ_DMACH9 (25) /* Vector 25: DMA channel 9 transfer complete */ -# define KINETIS_IRQ_DMACH10 (26) /* Vector 26: DMA channel 10 transfer complete */ -# define KINETIS_IRQ_DMACH11 (27) /* Vector 27: DMA channel 11 transfer complete */ -# define KINETIS_IRQ_DMACH12 (28) /* Vector 28: DMA channel 12 transfer complete */ -# define KINETIS_IRQ_DMACH13 (29) /* Vector 29: DMA channel 13 transfer complete */ -# define KINETIS_IRQ_DMACH14 (30) /* Vector 30: DMA channel 14 transfer complete */ -# define KINETIS_IRQ_DMACH15 (31) /* Vector 31: DMA channel 15 transfer complete */ -# define KINETIS_IRQ_DMAERR (32) /* Vector 32: DMA error interrupt channels 0-15 */ -# define KINETIS_IRQ_MCM (33) /* Vector 33: MCM Normal interrupt */ -# define KINETIS_IRQ_FLASHCC (34) /* Vector 34: Flash memory command complete */ -# define KINETIS_IRQ_FLASHRC (35) /* Vector 35: Flash memory read collision */ -# define KINETIS_IRQ_SMCLVD (36) /* Vector 36: Mode Controller low-voltage - * detect, low-voltage warning */ -# define KINETIS_IRQ_LLWU (37) /* Vector 37: LLWU Normal Low Leakage Wakeup */ -# define KINETIS_IRQ_WDOG (38) /* Vector 38: Watchdog */ - /* Vector 39: Reserved */ -# define KINETIS_IRQ_I2C0 (40) /* Vector 40: I2C0 */ -# define KINETIS_IRQ_I2C1 (41) /* Vector 41: I2C1 */ -# define KINETIS_IRQ_SPI0 (42) /* Vector 42: SPI0 all sources */ -# define KINETIS_IRQ_SPI1 (43) /* Vector 43: SPI1 all sources */ -# define KINETIS_IRQ_SPI2 (44) /* Vector 44: SPI2 all sources */ -# define KINETIS_IRQ_CAN0MB (45) /* Vector 45: CAN0 OR'ed Message buffer (0-15) */ -# define KINETIS_IRQ_CAN0BO (46) /* Vector 46: CAN0 Bus Off */ -# define KINETIS_IRQ_CAN0ERR (47) /* Vector 47: CAN0 Error */ -# define KINETIS_IRQ_CAN0TW (48) /* Vector 48: CAN0 Transmit Warning */ -# define KINETIS_IRQ_CAN0RW (49) /* Vector 49: CAN0 Receive Warning */ -# define KINETIS_IRQ_CAN0WU (50) /* Vector 50: CAN0 Wake UP */ - /* Vectors 51-52: Reserved */ -# define KINETIS_IRQ_CAN1MB (53) /* Vector 53: CAN1 OR'ed Message buffer (0-15) */ -# define KINETIS_IRQ_CAN1BO (54) /* Vector 54: CAN1 Bus Off */ -# define KINETIS_IRQ_CAN1ERR (55) /* Vector 55: CAN1 Error */ -# define KINETIS_IRQ_CAN1TW (56) /* Vector 56: CAN1 Transmit Warning */ -# define KINETIS_IRQ_CAN1RW (57) /* Vector 57: CAN1 Receive Warning */ -# define KINETIS_IRQ_CAN1WU (58) /* Vector 58: CAN1 Wake UP */ - /* Vectors 59-60: Reserved */ -# define KINETIS_IRQ_UART0S (61) /* Vector 61: UART0 status */ -# define KINETIS_IRQ_UART0E (62) /* Vector 62: UART0 error */ -# define KINETIS_IRQ_UART1S (63) /* Vector 63: UART1 status */ -# define KINETIS_IRQ_UART1E (64) /* Vector 64: UART1 error */ -# define KINETIS_IRQ_UART2S (65) /* Vector 65: UART2 status */ -# define KINETIS_IRQ_UART2E (66) /* Vector 66: UART2 error */ -# define KINETIS_IRQ_UART3S (67) /* Vector 67: UART3 status */ -# define KINETIS_IRQ_UART3E (68) /* Vector 68: UART3 error */ -# define KINETIS_IRQ_UART4S (69) /* Vector 69: UART4 status */ -# define KINETIS_IRQ_UART4E (70) /* Vector 70: UART4 error */ -# define KINETIS_IRQ_UART5S (71) /* Vector 71: UART5 status */ -# define KINETIS_IRQ_UART5E (72) /* Vector 72: UART5 error */ -# define KINETIS_IRQ_ADC0 (73) /* Vector 73: ADC0 */ -# define KINETIS_IRQ_ADC1 (74) /* Vector 74: ADC1 */ -# define KINETIS_IRQ_CMP0 (75) /* Vector 75: CMP0 */ -# define KINETIS_IRQ_CMP1 (76) /* Vector 76: CMP1 */ -# define KINETIS_IRQ_CMP2 (77) /* Vector 77: CMP2 */ -# define KINETIS_IRQ_FTM0 (78) /* Vector 78: FTM0 all sources */ -# define KINETIS_IRQ_FTM1 (79) /* Vector 79: FTM1 all sources */ -# define KINETIS_IRQ_FTM2 (80) /* Vector 80: FTM2 all sources */ -# define KINETIS_IRQ_CMT (81) /* Vector 81: CMT */ -# define KINETIS_IRQ_RTC (82) /* Vector 82: RTC alarm interrupt */ - /* Vector 83: Reserved */ -# define KINETIS_IRQ_PITCH0 (84) /* Vector 84: PIT channel 0 */ -# define KINETIS_IRQ_PITCH1 (85) /* Vector 85: PIT channel 1 */ -# define KINETIS_IRQ_PITCH2 (86) /* Vector 86: PIT channel 2 */ -# define KINETIS_IRQ_PITCH3 (87) /* Vector 87: PIT channel 3 */ -# define KINETIS_IRQ_PDB (88) /* Vector 88: PDB */ -# define KINETIS_IRQ_USBOTG (89) /* Vector 88: USB OTG */ -# define KINETIS_IRQ_USBCD (90) /* Vector 90: USB charger detect */ - /* Vectors 91-94: Reserved */ -# define KINETIS_IRQ_I2S0 (95) /* Vector 95: I2S0 */ -# define KINETIS_IRQ_SDHC (96) /* Vector 96: SDHC */ -# define KINETIS_IRQ_DAC0 (97) /* Vector 97: DAC0 */ -# define KINETIS_IRQ_DAC1 (98) /* Vector 98: DAC1 */ -# define KINETIS_IRQ_TSI (99) /* Vector 97: TSI all sources */ -# define KINETIS_IRQ_MCG (100) /* Vector 100: MCG */ -# define KINETIS_IRQ_LPT (101) /* Vector 101: Low power timer */ -# define KINETIS_IRQ_SLCD (102) /* Vector 102: Segment LCD all sources */ -# define KINETIS_IRQ_PORTA (103) /* Vector 103: Pin detect port A */ -# define KINETIS_IRQ_PORTB (104) /* Vector 104: Pin detect port B */ -# define KINETIS_IRQ_PORTC (105) /* Vector 105: Pin detect port C */ -# define KINETIS_IRQ_PORTD (106) /* Vector 106: Pin detect port D */ -# define KINETIS_IRQ_PORTE (107) /* Vector 107: Pin detect port E */ - /* Vectors 108-109: Reserved */ -# define KINETIS_IRQ_SWI (110) /* Vector 110: Software interrupt */ - -/* Note that the total number of IRQ numbers supported is equal to the number of - * valid interrupt vectors. This is wasteful in that certain tables are sized by - * this value. There are only 94 valid interrupts so, potentially the numver of - * IRQs to could be reduced to 94. However, equating IRQ numbers with vector numbers - * also simplifies operations on NVIC registers and (at least in my state of mind - * now) seems to justify the waste. - */ - -# define NR_VECTORS (111) /* 111 vectors */ -# define NR_IRQS (111) /* 94 interrupts but 111 IRQ numbers */ - -/* K60 Family *********************************************************************** - * - * The memory map for the following parts is defined in Freescale document - * K60P144M100SF2RM - */ - +# include #elif defined(CONFIG_ARCH_FAMILY_K60) - -# define KINETIS_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */ -# define KINETIS_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */ -# define KINETIS_IRQ_DMACH2 (18) /* Vector 18: DMA channel 2 transfer complete */ -# define KINETIS_IRQ_DMACH3 (19) /* Vector 19: DMA channel 3 transfer complete */ -# define KINETIS_IRQ_DMACH4 (20) /* Vector 20: DMA channel 4 transfer complete */ -# define KINETIS_IRQ_DMACH5 (21) /* Vector 21: DMA channel 5 transfer complete */ -# define KINETIS_IRQ_DMACH6 (22) /* Vector 22: DMA channel 6 transfer complete */ -# define KINETIS_IRQ_DMACH7 (23) /* Vector 23: DMA channel 7 transfer complete */ -# define KINETIS_IRQ_DMACH8 (24) /* Vector 24: DMA channel 8 transfer complete */ -# define KINETIS_IRQ_DMACH9 (25) /* Vector 25: DMA channel 9 transfer complete */ -# define KINETIS_IRQ_DMACH10 (26) /* Vector 26: DMA channel 10 transfer complete */ -# define KINETIS_IRQ_DMACH11 (27) /* Vector 27: DMA channel 11 transfer complete */ -# define KINETIS_IRQ_DMACH12 (28) /* Vector 28: DMA channel 12 transfer complete */ -# define KINETIS_IRQ_DMACH13 (29) /* Vector 29: DMA channel 13 transfer complete */ -# define KINETIS_IRQ_DMACH14 (30) /* Vector 30: DMA channel 14 transfer complete */ -# define KINETIS_IRQ_DMACH15 (31) /* Vector 31: DMA channel 15 transfer complete */ -# define KINETIS_IRQ_DMAERR (32) /* Vector 32: DMA error interrupt channels 0-15 */ -# define KINETIS_IRQ_MCM (33) /* Vector 33: MCM Normal interrupt */ -# define KINETIS_IRQ_FLASHCC (34) /* Vector 34: Flash memory command complete */ -# define KINETIS_IRQ_FLASHRC (35) /* Vector 35: Flash memory read collision */ -# define KINETIS_IRQ_SMCLVD (36) /* Vector 36: Mode Controller low-voltage - * detect, low-voltage warning */ -# define KINETIS_IRQ_LLWU (37) /* Vector 37: LLWU Normal Low Leakage Wakeup */ -# define KINETIS_IRQ_WDOG (38) /* Vector 38: Watchdog */ -# define KINETIS_IRQ_RNGB (39) /* Vector 39: Random number generator */ -# define KINETIS_IRQ_I2C0 (40) /* Vector 40: I2C0 */ -# define KINETIS_IRQ_I2C1 (41) /* Vector 41: I2C1 */ -# define KINETIS_IRQ_SPI0 (42) /* Vector 42: SPI0 all sources */ -# define KINETIS_IRQ_SPI1 (43) /* Vector 43: SPI1 all sources */ -# define KINETIS_IRQ_SPI2 (44) /* Vector 44: SPI2 all sources */ -# define KINETIS_IRQ_CAN0MB (45) /* Vector 45: CAN0 OR'ed Message buffer (0-15) */ -# define KINETIS_IRQ_CAN0BO (46) /* Vector 46: CAN0 Bus Off */ -# define KINETIS_IRQ_CAN0ERR (47) /* Vector 47: CAN0 Error */ -# define KINETIS_IRQ_CAN0TW (48) /* Vector 48: CAN0 Transmit Warning */ -# define KINETIS_IRQ_CAN0RW (49) /* Vector 49: CAN0 Receive Warning */ -# define KINETIS_IRQ_CAN0WU (50) /* Vector 50: CAN0 Wake UP */ - /* Vectors 51-52: Reserved */ -# define KINETIS_IRQ_CAN1MB (53) /* Vector 53: CAN1 OR'ed Message buffer (0-15) */ -# define KINETIS_IRQ_CAN1BO (54) /* Vector 54: CAN1 Bus Off */ -# define KINETIS_IRQ_CAN1ERR (55) /* Vector 55: CAN1 Error */ -# define KINETIS_IRQ_CAN1TW (56) /* Vector 56: CAN1 Transmit Warning */ -# define KINETIS_IRQ_CAN1RW (57) /* Vector 57: CAN1 Receive Warning */ -# define KINETIS_IRQ_CAN1WU (58) /* Vector 58: CAN1 Wake UP */ - /* Vectors 59-60: Reserved */ -# define KINETIS_IRQ_UART0S (61) /* Vector 61: UART0 status */ -# define KINETIS_IRQ_UART0E (62) /* Vector 62: UART0 error */ -# define KINETIS_IRQ_UART1S (63) /* Vector 63: UART1 status */ -# define KINETIS_IRQ_UART1E (64) /* Vector 64: UART1 error */ -# define KINETIS_IRQ_UART2S (65) /* Vector 65: UART2 status */ -# define KINETIS_IRQ_UART2E (66) /* Vector 66: UART2 error */ -# define KINETIS_IRQ_UART3S (67) /* Vector 67: UART3 status */ -# define KINETIS_IRQ_UART3E (68) /* Vector 68: UART3 error */ -# define KINETIS_IRQ_UART4S (69) /* Vector 69: UART4 status */ -# define KINETIS_IRQ_UART4E (70) /* Vector 70: UART4 error */ -# define KINETIS_IRQ_UART5S (71) /* Vector 71: UART5 status */ -# define KINETIS_IRQ_UART5E (72) /* Vector 72: UART5 error */ -# define KINETIS_IRQ_ADC0 (73) /* Vector 73: ADC0 */ -# define KINETIS_IRQ_ADC1 (74) /* Vector 74: ADC1 */ -# define KINETIS_IRQ_CMP0 (75) /* Vector 75: CMP0 */ -# define KINETIS_IRQ_CMP1 (76) /* Vector 76: CMP1 */ -# define KINETIS_IRQ_CMP2 (77) /* Vector 77: CMP2 */ -# define KINETIS_IRQ_FTM0 (78) /* Vector 78: FTM0 all sources */ -# define KINETIS_IRQ_FTM1 (79) /* Vector 79: FTM1 all sources */ -# define KINETIS_IRQ_FTM2 (80) /* Vector 80: FTM2 all sources */ -# define KINETIS_IRQ_CMT (81) /* Vector 81: CMT */ -# define KINETIS_IRQ_RTC (82) /* Vector 82: RTC alarm interrupt */ - /* Vector 83: Reserved */ -# define KINETIS_IRQ_PITCH0 (84) /* Vector 84: PIT channel 0 */ -# define KINETIS_IRQ_PITCH1 (85) /* Vector 85: PIT channel 1 */ -# define KINETIS_IRQ_PITCH2 (86) /* Vector 86: PIT channel 2 */ -# define KINETIS_IRQ_PITCH3 (87) /* Vector 87: PIT channel 3 */ -# define KINETIS_IRQ_PDB (88) /* Vector 88: PDB */ -# define KINETIS_IRQ_USBOTG (89) /* Vector 88: USB OTG */ -# define KINETIS_IRQ_USBCD (90) /* Vector 90: USB charger detect */ -# define KINETIS_IRQ_EMACTMR (91) /* Vector 91: Ethernet MAC IEEE 1588 timer interrupt */ -# define KINETIS_IRQ_EMACTX (92) /* Vector 92: Ethernet MAC transmit interrupt */ -# define KINETIS_IRQ_EMACRX (93) /* Vector 93: Ethernet MAC receive interrupt */ -# define KINETIS_IRQ_EMACMISC (94) /* Vector 94: Ethernet MAC error and misc interrupt */ -# define KINETIS_IRQ_I2S0 (95) /* Vector 95: I2S0 */ -# define KINETIS_IRQ_SDHC (96) /* Vector 96: SDHC */ -# define KINETIS_IRQ_DAC0 (97) /* Vector 97: DAC0 */ -# define KINETIS_IRQ_DAC1 (98) /* Vector 98: DAC1 */ -# define KINETIS_IRQ_TSI (99) /* Vector 97: TSI all sources */ -# define KINETIS_IRQ_MCG (100) /* Vector 100: MCG */ -# define KINETIS_IRQ_LPT (101) /* Vector 101: Low power timer */ - /* Vector 102: Reserved */ -# define KINETIS_IRQ_PORTA (103) /* Vector 103: Pin detect port A */ -# define KINETIS_IRQ_PORTB (104) /* Vector 104: Pin detect port B */ -# define KINETIS_IRQ_PORTC (105) /* Vector 105: Pin detect port C */ -# define KINETIS_IRQ_PORTD (106) /* Vector 106: Pin detect port D */ -# define KINETIS_IRQ_PORTE (107) /* Vector 107: Pin detect port E */ - /* Vectors 108-119: Reserved */ - -/* Note that the total number of IRQ numbers supported is equal to the number of - * valid interrupt vectors. This is wasteful in that certain tables are sized by - * this value. There are only 97 valid interrupts so, potentially the number of - * IRQs to could be reduced to 97. However, equating IRQ numbers with vector numbers - * also simplifies operations on NVIC registers and (at least in my state of mind - * now) seems to justify the waste. - */ - -# define NR_VECTORS (120) /* 120 vectors */ -# define NR_IRQS (108) /* 120 interrupts but 108 IRQ numbers */ - -/* K64 Family *********************************************************************** - * - * The memory map for the following parts is defined in NXP document - * K64P144M120SF5RM.pdf - */ - +# include #elif defined(CONFIG_ARCH_FAMILY_K64) - -# define KINETIS_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */ -# define KINETIS_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */ -# define KINETIS_IRQ_DMACH2 (18) /* Vector 18: DMA channel 2 transfer complete */ -# define KINETIS_IRQ_DMACH3 (19) /* Vector 19: DMA channel 3 transfer complete */ -# define KINETIS_IRQ_DMACH4 (20) /* Vector 20: DMA channel 4 transfer complete */ -# define KINETIS_IRQ_DMACH5 (21) /* Vector 21: DMA channel 5 transfer complete */ -# define KINETIS_IRQ_DMACH6 (22) /* Vector 22: DMA channel 6 transfer complete */ -# define KINETIS_IRQ_DMACH7 (23) /* Vector 23: DMA channel 7 transfer complete */ -# define KINETIS_IRQ_DMACH8 (24) /* Vector 24: DMA channel 8 transfer complete */ -# define KINETIS_IRQ_DMACH9 (25) /* Vector 25: DMA channel 9 transfer complete */ -# define KINETIS_IRQ_DMACH10 (26) /* Vector 26: DMA channel 10 transfer complete */ -# define KINETIS_IRQ_DMACH11 (27) /* Vector 27: DMA channel 11 transfer complete */ -# define KINETIS_IRQ_DMACH12 (28) /* Vector 28: DMA channel 12 transfer complete */ -# define KINETIS_IRQ_DMACH13 (29) /* Vector 29: DMA channel 13 transfer complete */ -# define KINETIS_IRQ_DMACH14 (30) /* Vector 30: DMA channel 14 transfer complete */ -# define KINETIS_IRQ_DMACH15 (31) /* Vector 31: DMA channel 15 transfer complete */ -# define KINETIS_IRQ_DMAERR (32) /* Vector 32: DMA error interrupt channels 0-15 */ -# define KINETIS_IRQ_MCM (33) /* Vector 33: MCM Normal interrupt */ -# define KINETIS_IRQ_FLASHCC (34) /* Vector 34: Flash memory command complete */ -# define KINETIS_IRQ_FLASHRC (35) /* Vector 35: Flash memory read collision */ -# define KINETIS_IRQ_SMCLVD (36) /* Vector 36: Mode Controller low-voltage - * detect, low-voltage warning */ -# define KINETIS_IRQ_LLWU (37) /* Vector 37: LLWU Normal Low Leakage Wakeup */ -# define KINETIS_IRQ_WDOG (38) /* Vector 38: Watchdog */ -# define KINETIS_IRQ_RNGB (39) /* Vector 39: Random number generator */ -# define KINETIS_IRQ_I2C0 (40) /* Vector 40: I2C0 */ -# define KINETIS_IRQ_I2C1 (41) /* Vector 41: I2C1 */ -# define KINETIS_IRQ_SPI0 (42) /* Vector 42: SPI0 all sources */ -# define KINETIS_IRQ_SPI1 (43) /* Vector 43: SPI1 all sources */ -# define KINETIS_IRQ_I2S0 (44) /* Vector 44: Transmit */ -# define KINETIS_IRQ_I2S1 (45) /* Vector 45: Transmit */ - /* Vector 46: Reserved */ -# define KINETIS_IRQ_UART0S (47) /* Vector 47: UART0 status */ -# define KINETIS_IRQ_UART0E (48) /* Vector 48: UART0 error */ -# define KINETIS_IRQ_UART1S (49) /* Vector 49: UART1 status */ -# define KINETIS_IRQ_UART1E (50) /* Vector 50: UART1 error */ -# define KINETIS_IRQ_UART2S (51) /* Vector 51: UART2 status */ -# define KINETIS_IRQ_UART2E (52) /* Vector 52: UART2 error */ -# define KINETIS_IRQ_UART3S (53) /* Vector 53: UART3 status */ -# define KINETIS_IRQ_UART3E (54) /* Vector 54: UART3 error */ -# define KINETIS_IRQ_ADC0 (55) /* Vector 55: ADC0 */ -# define KINETIS_IRQ_CMP0 (56) /* Vector 56: CMP0 */ -# define KINETIS_IRQ_CMP1 (57) /* Vector 57: CMP1 */ -# define KINETIS_IRQ_FTM0 (58) /* Vector 58: FTM0 all sources */ -# define KINETIS_IRQ_FTM1 (59) /* Vector 59: FTM1 all sources */ -# define KINETIS_IRQ_FTM2 (60) /* Vector 60: FTM2 all sources */ -# define KINETIS_IRQ_CMT (61) /* Vector 61: CMT */ -# define KINETIS_IRQ_RTC0 (62) /* Vector 62: RTC alarm interrupt */ -# define KINETIS_IRQ_RTC1 (63) /* Vector 63: RTC seconds interrupt */ -# define KINETIS_IRQ_PITCH0 (64) /* Vector 64: PIT channel 0 */ -# define KINETIS_IRQ_PITCH1 (65) /* Vector 65: PIT channel 1 */ -# define KINETIS_IRQ_PITCH2 (66) /* Vector 66: PIT channel 2 */ -# define KINETIS_IRQ_PITCH3 (67) /* Vector 67: PIT channel 3 */ -# define KINETIS_IRQ_PDB (68) /* Vector 68: PDB */ -# define KINETIS_IRQ_USBOTG (69) /* Vector 68: USB OTG */ -# define KINETIS_IRQ_USBCD (70) /* Vector 70: USB charger detect */ - /* Vector 71: Reserved */ -# define KINETIS_IRQ_DAC0 (72) /* Vector 72: DAC0 */ -# define KINETIS_IRQ_MCG (73) /* Vector 73: MCG */ -# define KINETIS_IRQ_LPT (74) /* Vector 74: Low power timer */ -# define KINETIS_IRQ_PORTA (75) /* Vector 75: Pin detect port A */ -# define KINETIS_IRQ_PORTB (76) /* Vector 76: Pin detect port B */ -# define KINETIS_IRQ_PORTC (77) /* Vector 77: Pin detect port C */ -# define KINETIS_IRQ_PORTD (78) /* Vector 78: Pin detect port D */ -# define KINETIS_IRQ_PORTE (79) /* Vector 79: Pin detect port E */ -# define KINETIS_IRQ_SOFTWARE (80) /* Vector 80: Software interrupt */ -# define KINETIS_IRQ_SPI2 (81) /* Vector 81: SPI2 all sources */ -# define KINETIS_IRQ_UART4S (82) /* Vector 82: UART4 status */ -# define KINETIS_IRQ_UART4E (83) /* Vector 83: UART4 error */ -# define KINETIS_IRQ_UART5S (84) /* Vector 84: UART5 status */ -# define KINETIS_IRQ_UART5E (85) /* Vector 85: UART5 error */ -# define KINETIS_IRQ_CMP2 (86) /* Vector 86: CMP2 */ -# define KINETIS_IRQ_FTM3 (87) /* Vector 87: FTM3 all sources */ -# define KINETIS_IRQ_DAC1 (88) /* Vector 88: DAC1 */ -# define KINETIS_IRQ_ADC1 (89) /* Vector 89: ADC1 */ -# define KINETIS_IRQ_I2C2 (90) /* Vector 90: I2C2 */ -# define KINETIS_IRQ_CAN0MB (91) /* Vector 91: CAN0 OR'ed Message buffer (0-15) */ -# define KINETIS_IRQ_CAN0BO (92) /* Vector 92: CAN0 Bus Off */ -# define KINETIS_IRQ_CAN0ERR (93) /* Vector 93: CAN0 Error */ -# define KINETIS_IRQ_CAN0TW (94) /* Vector 94: CAN0 Transmit Warning */ -# define KINETIS_IRQ_CAN0RW (95) /* Vector 95: CAN0 Receive Warning */ -# define KINETIS_IRQ_CAN0WU (96) /* Vector 96: CAN0 Wake UP */ -# define KINETIS_IRQ_SDHC (97) /* Vector 97: SDHC */ -# define KINETIS_IRQ_EMACTMR (98) /* Vector 91: Ethernet MAC IEEE 1588 timer interrupt */ -# define KINETIS_IRQ_EMACTX (99) /* Vector 92: Ethernet MAC transmit interrupt */ -# define KINETIS_IRQ_EMACRX (100) /* Vector 93: Ethernet MAC receive interrupt */ -# define KINETIS_IRQ_EMACMISC (101) /* Vector 94: Ethernet MAC error and misc interrupt */ - -# define NR_VECTORS (102) /* 102 vectors */ -# define NR_IRQS (102) /* 85 interrupts but 102 IRQ numbers */ - +# include +#elif defined(CONFIG_ARCH_FAMILY_K66) +# include #else /* The interrupt vectors for other parts are defined in other documents and may or * may not be the same as above (the family members are all very similar) This @@ -484,7 +95,7 @@ * if the vectors are the same. */ -# error "No IRQ numbers for this Kinetis part" +# error "No IRQ numbers for this Kinetis K part" #endif /************************************************************************************ diff --git a/arch/arm/include/kinetis/kinetis_k20irq.h b/arch/arm/include/kinetis/kinetis_k20irq.h new file mode 100644 index 0000000000..a5bb3068a6 --- /dev/null +++ b/arch/arm/include/kinetis/kinetis_k20irq.h @@ -0,0 +1,200 @@ +/***************************************************************************** + * arch/arm/include/kinetis/kinetis_k20irq.h + * + * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_K20IRQ_H +#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_K20IRQ_H + +/***************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/***************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. + * + * Processor Exceptions (vectors 0-15). These common definitions can be found + * in the file nuttx/arch/arm/include/kinets/irq.h which includes this file + * + * External interrupts (vectors >= 16) + * + * K20 Family **************************************************************** + * + * The interrupt vectors for the following parts is defined in Freescale + * document K20P64M72SF1RM + */ + +#define KINETIS_IRQ_DMACH0 (KINETIS_IRQ_FIRST+0) /* 0: DMA channel 0 transfer complete */ +#define KINETIS_IRQ_DMACH1 (KINETIS_IRQ_FIRST+1) /* 1: DMA channel 1 transfer complete */ +#define KINETIS_IRQ_DMACH2 (KINETIS_IRQ_FIRST+2) /* 2: DMA channel 2 transfer complete */ +#define KINETIS_IRQ_DMACH3 (KINETIS_IRQ_FIRST+3) /* 3: DMA channel 3 transfer complete */ +#define KINETIS_IRQ_DMACH4 (KINETIS_IRQ_FIRST+4) /* 4: DMA channel 4 transfer complete */ +#define KINETIS_IRQ_DMACH5 (KINETIS_IRQ_FIRST+5) /* 5: DMA channel 5 transfer complete */ +#define KINETIS_IRQ_DMACH6 (KINETIS_IRQ_FIRST+6) /* 6: DMA channel 6 transfer complete */ +#define KINETIS_IRQ_DMACH7 (KINETIS_IRQ_FIRST+7) /* 7: DMA channel 7 transfer complete */ +#define KINETIS_IRQ_DMACH8 (KINETIS_IRQ_FIRST+8) /* 8: DMA channel 8 transfer complete */ +#define KINETIS_IRQ_DMACH9 (KINETIS_IRQ_FIRST+9) /* 9: DMA channel 9 transfer complete */ +#define KINETIS_IRQ_DMACH10 (KINETIS_IRQ_FIRST+10) /* 10: DMA channel 10 transfer complete */ +#define KINETIS_IRQ_DMACH11 (KINETIS_IRQ_FIRST+11) /* 11: DMA channel 11 transfer complete */ +#define KINETIS_IRQ_DMACH12 (KINETIS_IRQ_FIRST+12) /* 12: DMA channel 12 transfer complete */ +#define KINETIS_IRQ_DMACH13 (KINETIS_IRQ_FIRST+13) /* 13: DMA channel 13 transfer complete */ +#define KINETIS_IRQ_DMACH14 (KINETIS_IRQ_FIRST+14) /* 14: DMA channel 14 transfer complete */ +#define KINETIS_IRQ_DMACH15 (KINETIS_IRQ_FIRST+15) /* 15: DMA channel 15 transfer complete */ +#define KINETIS_IRQ_DMAERR (KINETIS_IRQ_FIRST+16) /* 16: DMA error interrupt channels 0-15 */ +#define KINETIS_IRQ_RESVD17 (KINETIS_IRQ_FIRST+17) /* 17: Reserved */ +#define KINETIS_IRQ_FLASHCC (KINETIS_IRQ_FIRST+18) /* 18: Flash memory command complete */ +#define KINETIS_IRQ_FLASHRC (KINETIS_IRQ_FIRST+19) /* 19: Flash memory read collision */ +#define KINETIS_IRQ_SMCLVD (KINETIS_IRQ_FIRST+20) /* 20: Mode Controller low-voltage + * detect, low-voltage warning */ +#define KINETIS_IRQ_LLWU (KINETIS_IRQ_FIRST+21) /* 21: LLWU Normal Low Leakage Wakeup */ +#define KINETIS_IRQ_WDOG (KINETIS_IRQ_FIRST+22) /* 22: Watchdog */ +#define KINETIS_IRQ_RESVD23 (KINETIS_IRQ_FIRST+23) /* 23: Reserved */ +#define KINETIS_IRQ_I2C0 (KINETIS_IRQ_FIRST+24) /* 24: I2C0 */ +#define KINETIS_IRQ_I2C1 (KINETIS_IRQ_FIRST+25) /* 25: I2C1 */ +#define KINETIS_IRQ_SPI0 (KINETIS_IRQ_FIRST+26) /* 26: SPI0 all sources */ +#define KINETIS_IRQ_SPI1 (KINETIS_IRQ_FIRST+27) /* 27: SPI1 all sources */ +#define KINETIS_IRQ_RESVD28 (KINETIS_IRQ_FIRST+28) /* 28: Reserved */ +#define KINETIS_IRQ_CAN0MB (KINETIS_IRQ_FIRST+29) /* 29: CAN0 OR'ed Message buffer (0-15) */ +#define KINETIS_IRQ_CAN0BO (KINETIS_IRQ_FIRST+30) /* 30: CAN0 Bus Off */ +#define KINETIS_IRQ_CAN0ERR (KINETIS_IRQ_FIRST+31) /* 31: CAN0 Error */ +#define KINETIS_IRQ_CAN0TW (KINETIS_IRQ_FIRST+32) /* 32: CAN0 Transmit Warning */ +#define KINETIS_IRQ_CAN0RW (KINETIS_IRQ_FIRST+33) /* 33: CAN0 Receive Warning */ +#define KINETIS_IRQ_CAN0WU (KINETIS_IRQ_FIRST+34) /* 34: CAN0 Wake UP */ +#define KINETIS_IRQ_I2S0TX (KINETIS_IRQ_FIRST+35) /* 35: I2S0 Transmit */ +#define KINETIS_IRQ_I2S0TX (KINETIS_IRQ_FIRST+36) /* 36: I2S0 Receive */ +#define KINETIS_IRQ_RESVD37 (KINETIS_IRQ_FIRST+37) /* 37: Reserved */ +#define KINETIS_IRQ_RESVD38 (KINETIS_IRQ_FIRST+38) /* 38: Reserved */ +#define KINETIS_IRQ_RESVD39 (KINETIS_IRQ_FIRST+39) /* 39: Reserved */ +#define KINETIS_IRQ_RESVD40 (KINETIS_IRQ_FIRST+40) /* 40: Reserved */ +#define KINETIS_IRQ_RESVD41 (KINETIS_IRQ_FIRST+41) /* 41: Reserved */ +#define KINETIS_IRQ_RESVD42 (KINETIS_IRQ_FIRST+42) /* 42: Reserved */ +#define KINETIS_IRQ_RESVD43 (KINETIS_IRQ_FIRST+43) /* 43: Reserved */ +#define KINETIS_IRQ_UART0L (KINETIS_IRQ_FIRST+44) /* 44: UART0 LON */ +#define KINETIS_IRQ_UART0S (KINETIS_IRQ_FIRST+45) /* 45: UART0 status */ +#define KINETIS_IRQ_UART0E (KINETIS_IRQ_FIRST+46) /* 46: UART0 error */ +#define KINETIS_IRQ_UART1S (KINETIS_IRQ_FIRST+47) /* 47: UART1 status */ +#define KINETIS_IRQ_UART1E (KINETIS_IRQ_FIRST+48) /* 48: UART1 error */ +#define KINETIS_IRQ_UART2S (KINETIS_IRQ_FIRST+49) /* 49: UART2 status */ +#define KINETIS_IRQ_UART2E (KINETIS_IRQ_FIRST+50) /* 50: UART2 error */ +#define KINETIS_IRQ_RESVD51 (KINETIS_IRQ_FIRST+51) /* 51: Reserved */ +#define KINETIS_IRQ_RESVD52 (KINETIS_IRQ_FIRST+52) /* 52: Reserved */ +#define KINETIS_IRQ_RESVD53 (KINETIS_IRQ_FIRST+53) /* 53: Reserved */ +#define KINETIS_IRQ_RESVD54 (KINETIS_IRQ_FIRST+54) /* 54: Reserved */ +#define KINETIS_IRQ_RESVD55 (KINETIS_IRQ_FIRST+55) /* 55: Reserved */ +#define KINETIS_IRQ_RESVD56 (KINETIS_IRQ_FIRST+56) /* 56: Reserved */ +#define KINETIS_IRQ_ADC0 (KINETIS_IRQ_FIRST+57) /* 57: ADC0 */ +#define KINETIS_IRQ_ADC1 (KINETIS_IRQ_FIRST+58) /* 58: ADC1 */ +#define KINETIS_IRQ_CMP0 (KINETIS_IRQ_FIRST+59) /* 59: CMP0 */ +#define KINETIS_IRQ_CMP1 (KINETIS_IRQ_FIRST+60) /* 60: CMP1 */ +#define KINETIS_IRQ_CMP2 (KINETIS_IRQ_FIRST+61) /* 61: CMP2 */ +#define KINETIS_IRQ_FTM0 (KINETIS_IRQ_FIRST+62) /* 62: FTM0 all sources */ +#define KINETIS_IRQ_FTM1 (KINETIS_IRQ_FIRST+63) /* 63: FTM1 all sources */ +#define KINETIS_IRQ_FTM2 (KINETIS_IRQ_FIRST+64) /* 64: FTM2 all sources */ +#define KINETIS_IRQ_CMT (KINETIS_IRQ_FIRST+65) /* 65: CMT */ +#define KINETIS_IRQ_RTC (KINETIS_IRQ_FIRST+66) /* 66: RTC alarm interrupt */ +#define KINETIS_IRQ_RTCS (KINETIS_IRQ_FIRST+67) /* 67: RTC Seconds interrupt */ +#define KINETIS_IRQ_PITCH0 (KINETIS_IRQ_FIRST+68) /* 68: PIT channel 0 */ +#define KINETIS_IRQ_PITCH1 (KINETIS_IRQ_FIRST+69) /* 69: PIT channel 1 */ +#define KINETIS_IRQ_PITCH2 (KINETIS_IRQ_FIRST+70) /* 70: PIT channel 2 */ +#define KINETIS_IRQ_PITCH3 (KINETIS_IRQ_FIRST+71) /* 71: PIT channel 3 */ +#define KINETIS_IRQ_PDB (KINETIS_IRQ_FIRST+72) /* 72: PDB */ +#define KINETIS_IRQ_USBOTG (KINETIS_IRQ_FIRST+73) /* 73: USB OTG */ +#define KINETIS_IRQ_USBCD (KINETIS_IRQ_FIRST+74) /* 74: USB charger detect */ +#define KINETIS_IRQ_RESVD75 (KINETIS_IRQ_FIRST+75) /* 75: Reserved */ +#define KINETIS_IRQ_RESVD76 (KINETIS_IRQ_FIRST+76) /* 76: Reserved */ +#define KINETIS_IRQ_RESVD77 (KINETIS_IRQ_FIRST+77) /* 77: Reserved */ +#define KINETIS_IRQ_RESVD78 (KINETIS_IRQ_FIRST+78) /* 78: Reserved */ +#define KINETIS_IRQ_RESVD79 (KINETIS_IRQ_FIRST+79) /* 79: Reserved */ +#define KINETIS_IRQ_RESVD80 (KINETIS_IRQ_FIRST+80) /* 80: Reserved */ +#define KINETIS_IRQ_DAC0 (KINETIS_IRQ_FIRST+81) /* 81: DAC0 */ +#define KINETIS_IRQ_RESVD82 (KINETIS_IRQ_FIRST+82) /* 82: Reserved */ +#define KINETIS_IRQ_TSI (KINETIS_IRQ_FIRST+83) /* 83: TSI all sources */ +#define KINETIS_IRQ_MCG (KINETIS_IRQ_FIRST+84) /* 84: MCG */ +#define KINETIS_IRQ_LPT (KINETIS_IRQ_FIRST+85) /* 85: Low power timer */ +#define KINETIS_IRQ_RESVD86 (KINETIS_IRQ_FIRST+86) /* 86: Reserved */ +#define KINETIS_IRQ_PORTA (KINETIS_IRQ_FIRST+87) /* 87: Pin detect port A */ +#define KINETIS_IRQ_PORTB (KINETIS_IRQ_FIRST+88) /* 88: Pin detect port B */ +#define KINETIS_IRQ_PORTC (KINETIS_IRQ_FIRST+89) /* 89: Pin detect port C */ +#define KINETIS_IRQ_PORTD (KINETIS_IRQ_FIRST+90) /* 90: Pin detect port D */ +#define KINETIS_IRQ_PORTE (KINETIS_IRQ_FIRST+91) /* 91: Pin detect port E */ +#define KINETIS_IRQ_RESVD92 (KINETIS_IRQ_FIRST+92) /* 92: Reserved */ +#define KINETIS_IRQ_RESVD93 (KINETIS_IRQ_FIRST+93) /* 93: Reserved */ +#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST+94) /* 94: Software interrupt */ + +#define NR_INTERRUPTS 95 /* 95 Non core IRQs*/ +#define NR_VECTORS (KINETIS_IRQ_FIRST+NR_INTERRUPTS) /* 111 vectors */ + +/* EXTI interrupts (Do not use IRQ numbers) */ + +#define NR_IRQS NR_VECTORS + +/***************************************************************************** + * Public Types + ****************************************************************************/ + +/***************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/***************************************************************************** + * Public Functions + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_K20IRQ_H */ diff --git a/arch/arm/include/kinetis/kinetis_k40irq.h b/arch/arm/include/kinetis/kinetis_k40irq.h new file mode 100644 index 0000000000..4156b321f9 --- /dev/null +++ b/arch/arm/include/kinetis/kinetis_k40irq.h @@ -0,0 +1,200 @@ +/***************************************************************************** + * arch/arm/include/kinetis/kinetis_k40irq.h + * + * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_40KIRQ_H +#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_40KIRQ_H + +/***************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/***************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. + * + * Processor Exceptions (vectors 0-15). These common definitions can be found + * in the file nuttx/arch/arm/include/kinets/irq.h which includes this file + * + * External interrupts (vectors >= 16) + * + * K40 Family **************************************************************** + * + * The interrupt vectors for the following parts is defined in Freescale + * document K40P144M100SF2RM + */ + +#define KINETIS_IRQ_DMACH0 (KINETIS_IRQ_FIRST+0) /* 0: DMA channel 0 transfer complete */ +#define KINETIS_IRQ_DMACH1 (KINETIS_IRQ_FIRST+1) /* 1: DMA channel 1 transfer complete */ +#define KINETIS_IRQ_DMACH2 (KINETIS_IRQ_FIRST+2) /* 2: DMA channel 2 transfer complete */ +#define KINETIS_IRQ_DMACH3 (KINETIS_IRQ_FIRST+3) /* 3: DMA channel 3 transfer complete */ +#define KINETIS_IRQ_DMACH4 (KINETIS_IRQ_FIRST+4) /* 4: DMA channel 4 transfer complete */ +#define KINETIS_IRQ_DMACH5 (KINETIS_IRQ_FIRST+5) /* 5: DMA channel 5 transfer complete */ +#define KINETIS_IRQ_DMACH6 (KINETIS_IRQ_FIRST+6) /* 6: DMA channel 6 transfer complete */ +#define KINETIS_IRQ_DMACH7 (KINETIS_IRQ_FIRST+7) /* 7: DMA channel 7 transfer complete */ +#define KINETIS_IRQ_DMACH8 (KINETIS_IRQ_FIRST+8) /* 8: DMA channel 8 transfer complete */ +#define KINETIS_IRQ_DMACH9 (KINETIS_IRQ_FIRST+9) /* 9: DMA channel 9 transfer complete */ +#define KINETIS_IRQ_DMACH10 (KINETIS_IRQ_FIRST+10) /* 10: DMA channel 10 transfer complete */ +#define KINETIS_IRQ_DMACH11 (KINETIS_IRQ_FIRST+11) /* 11: DMA channel 11 transfer complete */ +#define KINETIS_IRQ_DMACH12 (KINETIS_IRQ_FIRST+12) /* 12: DMA channel 12 transfer complete */ +#define KINETIS_IRQ_DMACH13 (KINETIS_IRQ_FIRST+13) /* 13: DMA channel 13 transfer complete */ +#define KINETIS_IRQ_DMACH14 (KINETIS_IRQ_FIRST+14) /* 14: DMA channel 14 transfer complete */ +#define KINETIS_IRQ_DMACH15 (KINETIS_IRQ_FIRST+15) /* 15: DMA channel 15 transfer complete */ +#define KINETIS_IRQ_DMAERR (KINETIS_IRQ_FIRST+16) /* 16: DMA error interrupt channels 0-15 */ +#define KINETIS_IRQ_MCM (KINETIS_IRQ_FIRST+17) /* 17: MCM Normal interrupt */ +#define KINETIS_IRQ_FLASHCC (KINETIS_IRQ_FIRST+18) /* 18: Flash memory command complete */ +#define KINETIS_IRQ_FLASHRC (KINETIS_IRQ_FIRST+19) /* 19: Flash memory read collision */ +#define KINETIS_IRQ_SMCLVD (KINETIS_IRQ_FIRST+20) /* 20: Mode Controller low-voltage + * detect, low-voltage warning */ +#define KINETIS_IRQ_LLWU (KINETIS_IRQ_FIRST+21) /* 21: LLWU Normal Low Leakage Wakeup */ +#define KINETIS_IRQ_WDOG (KINETIS_IRQ_FIRST+22) /* 22: Watchdog */ +#define KINETIS_IRQ_RESVD23 (KINETIS_IRQ_FIRST+23) /* 23: Reserved */ +#define KINETIS_IRQ_I2C0 (KINETIS_IRQ_FIRST+24) /* 24: I2C0 */ +#define KINETIS_IRQ_I2C1 (KINETIS_IRQ_FIRST+25) /* 25: I2C1 */ +#define KINETIS_IRQ_SPI0 (KINETIS_IRQ_FIRST+26) /* 26: SPI0 all sources */ +#define KINETIS_IRQ_SPI1 (KINETIS_IRQ_FIRST+27) /* 27: SPI1 all sources */ +#define KINETIS_IRQ_SPI2 (KINETIS_IRQ_FIRST+28) /* 28: SPI2 all sources */ +#define KINETIS_IRQ_CAN0MB (KINETIS_IRQ_FIRST+29) /* 29: CAN0 OR'ed Message buffer (0-15) */ +#define KINETIS_IRQ_CAN0BO (KINETIS_IRQ_FIRST+30) /* 30: CAN0 Bus Off */ +#define KINETIS_IRQ_CAN0ERR (KINETIS_IRQ_FIRST+31) /* 31: CAN0 Error */ +#define KINETIS_IRQ_CAN0TW (KINETIS_IRQ_FIRST+32) /* 32: CAN0 Transmit Warning */ +#define KINETIS_IRQ_CAN0RW (KINETIS_IRQ_FIRST+33) /* 33: CAN0 Receive Warning */ +#define KINETIS_IRQ_CAN0WU (KINETIS_IRQ_FIRST+34) /* 34: CAN0 Wake UP */ +#define KINETIS_IRQ_RESVD35 (KINETIS_IRQ_FIRST+35) /* 35: Reserved */ +#define KINETIS_IRQ_RESVD36 (KINETIS_IRQ_FIRST+36) /* 36: Reserved */ +#define KINETIS_IRQ_CAN1MB (KINETIS_IRQ_FIRST+37) /* 37: CAN1 OR'ed Message buffer (0-15) */ +#define KINETIS_IRQ_CAN1BO (KINETIS_IRQ_FIRST+38) /* 38: CAN1 Bus Off */ +#define KINETIS_IRQ_CAN1ERR (KINETIS_IRQ_FIRST+39) /* 39: CAN1 Error */ +#define KINETIS_IRQ_CAN1TW (KINETIS_IRQ_FIRST+40) /* 40: CAN1 Transmit Warning */ +#define KINETIS_IRQ_CAN1RW (KINETIS_IRQ_FIRST+41) /* 41: CAN1 Receive Warning */ +#define KINETIS_IRQ_CAN1WU (KINETIS_IRQ_FIRST+42) /* 42: CAN1 Wake UP */ +#define KINETIS_IRQ_RESVD43 (KINETIS_IRQ_FIRST+43) /* 43: Reserved */ +#define KINETIS_IRQ_RESVD44 (KINETIS_IRQ_FIRST+44) /* 44: Reserved */ +#define KINETIS_IRQ_UART0S (KINETIS_IRQ_FIRST+45) /* 45: UART0 status */ +#define KINETIS_IRQ_UART0E (KINETIS_IRQ_FIRST+46) /* 46: UART0 error */ +#define KINETIS_IRQ_UART1S (KINETIS_IRQ_FIRST+47) /* 47: UART1 status */ +#define KINETIS_IRQ_UART1E (KINETIS_IRQ_FIRST+48) /* 48: UART1 error */ +#define KINETIS_IRQ_UART2S (KINETIS_IRQ_FIRST+49) /* 49: UART2 status */ +#define KINETIS_IRQ_UART2E (KINETIS_IRQ_FIRST+50) /* 50: UART2 error */ +#define KINETIS_IRQ_UART3S (KINETIS_IRQ_FIRST+51) /* 51: UART3 status */ +#define KINETIS_IRQ_UART3E (KINETIS_IRQ_FIRST+52) /* 52: UART3 error */ +#define KINETIS_IRQ_UART4S (KINETIS_IRQ_FIRST+53) /* 53: UART4 status */ +#define KINETIS_IRQ_UART4E (KINETIS_IRQ_FIRST+54) /* 54: UART4 error */ +#define KINETIS_IRQ_UART5S (KINETIS_IRQ_FIRST+55) /* 55: UART5 status */ +#define KINETIS_IRQ_UART5E (KINETIS_IRQ_FIRST+56) /* 56: UART5 error */ +#define KINETIS_IRQ_ADC0 (KINETIS_IRQ_FIRST+57) /* 57: ADC0 */ +#define KINETIS_IRQ_ADC1 (KINETIS_IRQ_FIRST+58) /* 58: ADC1 */ +#define KINETIS_IRQ_CMP0 (KINETIS_IRQ_FIRST+59) /* 59: CMP0 */ +#define KINETIS_IRQ_CMP1 (KINETIS_IRQ_FIRST+60) /* 60: CMP1 */ +#define KINETIS_IRQ_CMP2 (KINETIS_IRQ_FIRST+61) /* 61: CMP2 */ +#define KINETIS_IRQ_FTM0 (KINETIS_IRQ_FIRST+62) /* 62: FTM0 all sources */ +#define KINETIS_IRQ_FTM1 (KINETIS_IRQ_FIRST+63) /* 63: FTM1 all sources */ +#define KINETIS_IRQ_FTM2 (KINETIS_IRQ_FIRST+64) /* 64: FTM2 all sources */ +#define KINETIS_IRQ_CMT (KINETIS_IRQ_FIRST+65) /* 65: CMT */ +#define KINETIS_IRQ_RTC (KINETIS_IRQ_FIRST+66) /* 66: RTC alarm interrupt */ +#define KINETIS_IRQ_RESVD67 (KINETIS_IRQ_FIRST+67) /* 67: Reserved */ +#define KINETIS_IRQ_PITCH0 (KINETIS_IRQ_FIRST+68) /* 68: PIT channel 0 */ +#define KINETIS_IRQ_PITCH1 (KINETIS_IRQ_FIRST+69) /* 69: PIT channel 1 */ +#define KINETIS_IRQ_PITCH2 (KINETIS_IRQ_FIRST+70) /* 70: PIT channel 2 */ +#define KINETIS_IRQ_PITCH3 (KINETIS_IRQ_FIRST+71) /* 71: PIT channel 3 */ +#define KINETIS_IRQ_PDB (KINETIS_IRQ_FIRST+72) /* 72: PDB */ +#define KINETIS_IRQ_USBOTG (KINETIS_IRQ_FIRST+73) /* 73: USB OTG */ +#define KINETIS_IRQ_USBCD (KINETIS_IRQ_FIRST+74) /* 74: USB charger detect */ +#define KINETIS_IRQ_RESVD75 (KINETIS_IRQ_FIRST+75) /* 75: Reserved */ +#define KINETIS_IRQ_RESVD76 (KINETIS_IRQ_FIRST+76) /* 76: Reserved */ +#define KINETIS_IRQ_RESVD77 (KINETIS_IRQ_FIRST+77) /* 77: Reserved */ +#define KINETIS_IRQ_RESVD78 (KINETIS_IRQ_FIRST+78) /* 78: Reserved */ +#define KINETIS_IRQ_I2S0 (KINETIS_IRQ_FIRST+79) /* 79: I2S0 */ +#define KINETIS_IRQ_SDHC (KINETIS_IRQ_FIRST+80) /* 80: SDHC */ +#define KINETIS_IRQ_DAC0 (KINETIS_IRQ_FIRST+81) /* 81: DAC0 */ +#define KINETIS_IRQ_DAC1 (KINETIS_IRQ_FIRST+82) /* 82: DAC1 */ +#define KINETIS_IRQ_TSI (KINETIS_IRQ_FIRST+83) /* 83: TSI all sources */ +#define KINETIS_IRQ_MCG (KINETIS_IRQ_FIRST+84) /* 84: MCG */ +#define KINETIS_IRQ_LPT (KINETIS_IRQ_FIRST+85) /* 85: Low power timer */ +#define KINETIS_IRQ_SLCD (KINETIS_IRQ_FIRST+86) /* 86: Segment LCD all sources */ +#define KINETIS_IRQ_PORTA (KINETIS_IRQ_FIRST+87) /* 87: Pin detect port A */ +#define KINETIS_IRQ_PORTB (KINETIS_IRQ_FIRST+88) /* 88: Pin detect port B */ +#define KINETIS_IRQ_PORTC (KINETIS_IRQ_FIRST+89) /* 89: Pin detect port C */ +#define KINETIS_IRQ_PORTD (KINETIS_IRQ_FIRST+90) /* 90: Pin detect port D */ +#define KINETIS_IRQ_PORTE (KINETIS_IRQ_FIRST+91) /* 91: Pin detect port E */ +#define KINETIS_IRQ_RESVD92 (KINETIS_IRQ_FIRST+92) /* 92: Reserved */ +#define KINETIS_IRQ_RESVD93 (KINETIS_IRQ_FIRST+93) /* 93: Reserved */ +#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST+94) /* 94: Software interrupt */ + +#define NR_INTERRUPTS 95 /* 95 Non core IRQs*/ +#define NR_VECTORS (KINETIS_IRQ_FIRST+NR_INTERRUPTS) /* 111 vectors */ + +/* EXTI interrupts (Do not use IRQ numbers) */ + +#define NR_IRQS NR_VECTORS + +/***************************************************************************** + * Public Types + ****************************************************************************/ + +/***************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/***************************************************************************** + * Public Functions + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_40KIRQ_H */ diff --git a/arch/arm/include/kinetis/kinetis_k60irq.h b/arch/arm/include/kinetis/kinetis_k60irq.h new file mode 100644 index 0000000000..b2e3a79b83 --- /dev/null +++ b/arch/arm/include/kinetis/kinetis_k60irq.h @@ -0,0 +1,200 @@ +/***************************************************************************** + * arch/arm/include/kinetis/kinetis_k60irq.h + * + * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_60KIRQ_H +#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_60KIRQ_H + +/***************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/***************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. + * + * Processor Exceptions (vectors 0-15). These common definitions can be found + * in the file nuttx/arch/arm/include/kinets/irq.h which includes this file + * + * External interrupts (vectors >= 16) + * + * K60 Family **************************************************************** + * + * The interrupt vectors for the following parts is defined in Freescale + * document K60P144M100SF2RM + */ + +#define KINETIS_IRQ_DMACH0 (KINETIS_IRQ_FIRST+0) /* 0: DMA channel 0 transfer complete */ +#define KINETIS_IRQ_DMACH1 (KINETIS_IRQ_FIRST+1) /* 1: DMA channel 1 transfer complete */ +#define KINETIS_IRQ_DMACH2 (KINETIS_IRQ_FIRST+2) /* 2: DMA channel 2 transfer complete */ +#define KINETIS_IRQ_DMACH3 (KINETIS_IRQ_FIRST+3) /* 3: DMA channel 3 transfer complete */ +#define KINETIS_IRQ_DMACH4 (KINETIS_IRQ_FIRST+4) /* 4: DMA channel 4 transfer complete */ +#define KINETIS_IRQ_DMACH5 (KINETIS_IRQ_FIRST+5) /* 5: DMA channel 5 transfer complete */ +#define KINETIS_IRQ_DMACH6 (KINETIS_IRQ_FIRST+6) /* 6: DMA channel 6 transfer complete */ +#define KINETIS_IRQ_DMACH7 (KINETIS_IRQ_FIRST+7) /* 7: DMA channel 7 transfer complete */ +#define KINETIS_IRQ_DMACH8 (KINETIS_IRQ_FIRST+8) /* 8: DMA channel 8 transfer complete */ +#define KINETIS_IRQ_DMACH9 (KINETIS_IRQ_FIRST+9) /* 9: DMA channel 9 transfer complete */ +#define KINETIS_IRQ_DMACH10 (KINETIS_IRQ_FIRST+10) /* 10: DMA channel 10 transfer complete */ +#define KINETIS_IRQ_DMACH11 (KINETIS_IRQ_FIRST+11) /* 11: DMA channel 11 transfer complete */ +#define KINETIS_IRQ_DMACH12 (KINETIS_IRQ_FIRST+12) /* 12: DMA channel 12 transfer complete */ +#define KINETIS_IRQ_DMACH13 (KINETIS_IRQ_FIRST+13) /* 13: DMA channel 13 transfer complete */ +#define KINETIS_IRQ_DMACH14 (KINETIS_IRQ_FIRST+14) /* 14: DMA channel 14 transfer complete */ +#define KINETIS_IRQ_DMACH15 (KINETIS_IRQ_FIRST+15) /* 15: DMA channel 15 transfer complete */ +#define KINETIS_IRQ_DMAERR (KINETIS_IRQ_FIRST+16) /* 16: DMA error interrupt channels 0-15 */ +#define KINETIS_IRQ_MCM (KINETIS_IRQ_FIRST+17) /* 17: MCM Normal interrupt */ +#define KINETIS_IRQ_FLASHCC (KINETIS_IRQ_FIRST+18) /* 18: Flash memory command complete */ +#define KINETIS_IRQ_FLASHRC (KINETIS_IRQ_FIRST+19) /* 19: Flash memory read collision */ +#define KINETIS_IRQ_SMCLVD (KINETIS_IRQ_FIRST+20) /* 20: Mode Controller low-voltage + * detect, low-voltage warning */ +#define KINETIS_IRQ_LLWU (KINETIS_IRQ_FIRST+21) /* 21: LLWU Normal Low Leakage Wakeup */ +#define KINETIS_IRQ_WDOG (KINETIS_IRQ_FIRST+22) /* 22: Watchdog */ +#define KINETIS_IRQ_RNGB (KINETIS_IRQ_FIRST+23) /* 23: Random number generator */ +#define KINETIS_IRQ_I2C0 (KINETIS_IRQ_FIRST+24) /* 24: I2C0 */ +#define KINETIS_IRQ_I2C1 (KINETIS_IRQ_FIRST+25) /* 25: I2C1 */ +#define KINETIS_IRQ_SPI0 (KINETIS_IRQ_FIRST+26) /* 26: SPI0 all sources */ +#define KINETIS_IRQ_SPI1 (KINETIS_IRQ_FIRST+27) /* 27: SPI1 all sources */ +#define KINETIS_IRQ_SPI2 (KINETIS_IRQ_FIRST+28) /* 28: SPI2 all sources */ +#define KINETIS_IRQ_CAN0MB (KINETIS_IRQ_FIRST+29) /* 29: CAN0 OR'ed Message buffer (0-15) */ +#define KINETIS_IRQ_CAN0BO (KINETIS_IRQ_FIRST+30) /* 30: CAN0 Bus Off */ +#define KINETIS_IRQ_CAN0ERR (KINETIS_IRQ_FIRST+31) /* 31: CAN0 Error */ +#define KINETIS_IRQ_CAN0TW (KINETIS_IRQ_FIRST+32) /* 32: CAN0 Transmit Warning */ +#define KINETIS_IRQ_CAN0RW (KINETIS_IRQ_FIRST+33) /* 33: CAN0 Receive Warning */ +#define KINETIS_IRQ_CAN0WU (KINETIS_IRQ_FIRST+34) /* 34: CAN0 Wake UP */ +#define KINETIS_IRQ_RESVD35 (KINETIS_IRQ_FIRST+35) /* 35: Reserved */ +#define KINETIS_IRQ_RESVD36 (KINETIS_IRQ_FIRST+36) /* 36: Reserved */ +#define KINETIS_IRQ_CAN1MB (KINETIS_IRQ_FIRST+37) /* 37: CAN1 OR'ed Message buffer (0-15) */ +#define KINETIS_IRQ_CAN1BO (KINETIS_IRQ_FIRST+38) /* 38: CAN1 Bus Off */ +#define KINETIS_IRQ_CAN1ERR (KINETIS_IRQ_FIRST+39) /* 39: CAN1 Error */ +#define KINETIS_IRQ_CAN1TW (KINETIS_IRQ_FIRST+40) /* 40: CAN1 Transmit Warning */ +#define KINETIS_IRQ_CAN1RW (KINETIS_IRQ_FIRST+41) /* 41: CAN1 Receive Warning */ +#define KINETIS_IRQ_CAN1WU (KINETIS_IRQ_FIRST+42) /* 42: CAN1 Wake UP */ +#define KINETIS_IRQ_RESVD43 (KINETIS_IRQ_FIRST+43) /* 43: Reserved */ +#define KINETIS_IRQ_RESVD44 (KINETIS_IRQ_FIRST+44) /* 44: Reserved */ +#define KINETIS_IRQ_UART0S (KINETIS_IRQ_FIRST+45) /* 45: UART0 status */ +#define KINETIS_IRQ_UART0E (KINETIS_IRQ_FIRST+46) /* 46: UART0 error */ +#define KINETIS_IRQ_UART1S (KINETIS_IRQ_FIRST+47) /* 47: UART1 status */ +#define KINETIS_IRQ_UART1E (KINETIS_IRQ_FIRST+48) /* 48: UART1 error */ +#define KINETIS_IRQ_UART2S (KINETIS_IRQ_FIRST+49) /* 49: UART2 status */ +#define KINETIS_IRQ_UART2E (KINETIS_IRQ_FIRST+50) /* 50: UART2 error */ +#define KINETIS_IRQ_UART3S (KINETIS_IRQ_FIRST+51) /* 51: UART3 status */ +#define KINETIS_IRQ_UART3E (KINETIS_IRQ_FIRST+52) /* 52: UART3 error */ +#define KINETIS_IRQ_UART4S (KINETIS_IRQ_FIRST+53) /* 53: UART4 status */ +#define KINETIS_IRQ_UART4E (KINETIS_IRQ_FIRST+54) /* 54: UART4 error */ +#define KINETIS_IRQ_UART5S (KINETIS_IRQ_FIRST+55) /* 55: UART5 status */ +#define KINETIS_IRQ_UART5E (KINETIS_IRQ_FIRST+56) /* 56: UART5 error */ +#define KINETIS_IRQ_ADC0 (KINETIS_IRQ_FIRST+57) /* 57: ADC0 */ +#define KINETIS_IRQ_ADC1 (KINETIS_IRQ_FIRST+58) /* 58: ADC1 */ +#define KINETIS_IRQ_CMP0 (KINETIS_IRQ_FIRST+59) /* 59: CMP0 */ +#define KINETIS_IRQ_CMP1 (KINETIS_IRQ_FIRST+60) /* 60: CMP1 */ +#define KINETIS_IRQ_CMP2 (KINETIS_IRQ_FIRST+61) /* 61: CMP2 */ +#define KINETIS_IRQ_FTM0 (KINETIS_IRQ_FIRST+62) /* 62: FTM0 all sources */ +#define KINETIS_IRQ_FTM1 (KINETIS_IRQ_FIRST+63) /* 63: FTM1 all sources */ +#define KINETIS_IRQ_FTM2 (KINETIS_IRQ_FIRST+64) /* 64: FTM2 all sources */ +#define KINETIS_IRQ_CMT (KINETIS_IRQ_FIRST+65) /* 65: CMT */ +#define KINETIS_IRQ_RTC (KINETIS_IRQ_FIRST+66) /* 66: RTC alarm interrupt */ +#define KINETIS_IRQ_RESVD67 (KINETIS_IRQ_FIRST+67) /* 67: Reserved */ +#define KINETIS_IRQ_PITCH0 (KINETIS_IRQ_FIRST+68) /* 68: PIT channel 0 */ +#define KINETIS_IRQ_PITCH1 (KINETIS_IRQ_FIRST+69) /* 69: PIT channel 1 */ +#define KINETIS_IRQ_PITCH2 (KINETIS_IRQ_FIRST+70) /* 70: PIT channel 2 */ +#define KINETIS_IRQ_PITCH3 (KINETIS_IRQ_FIRST+71) /* 71: PIT channel 3 */ +#define KINETIS_IRQ_PDB (KINETIS_IRQ_FIRST+72) /* 72: PDB */ +#define KINETIS_IRQ_USBOTG (KINETIS_IRQ_FIRST+73) /* 73: USB OTG */ +#define KINETIS_IRQ_USBCD (KINETIS_IRQ_FIRST+74) /* 74: USB charger detect */ +#define KINETIS_IRQ_EMACTMR (KINETIS_IRQ_FIRST+75) /* 75: Ethernet MAC IEEE 1588 timer interrupt */ +#define KINETIS_IRQ_EMACTX (KINETIS_IRQ_FIRST+76) /* 76: Ethernet MAC transmit interrupt */ +#define KINETIS_IRQ_EMACRX (KINETIS_IRQ_FIRST+77) /* 77: Ethernet MAC receive interrupt */ +#define KINETIS_IRQ_EMACMISC (KINETIS_IRQ_FIRST+78) /* 78: Ethernet MAC error and misc interrupt */ +#define KINETIS_IRQ_I2S0 (KINETIS_IRQ_FIRST+79) /* 79: I2S0 */ +#define KINETIS_IRQ_SDHC (KINETIS_IRQ_FIRST+80) /* 80: SDHC */ +#define KINETIS_IRQ_DAC0 (KINETIS_IRQ_FIRST+81) /* 81: DAC0 */ +#define KINETIS_IRQ_DAC1 (KINETIS_IRQ_FIRST+82) /* 82: DAC1 */ +#define KINETIS_IRQ_TSI (KINETIS_IRQ_FIRST+83) /* 83: TSI all sources */ +#define KINETIS_IRQ_MCG (KINETIS_IRQ_FIRST+84) /* 84: MCG */ +#define KINETIS_IRQ_LPT (KINETIS_IRQ_FIRST+85) /* 85: Low power timer */ +#define KINETIS_IRQ_RESVD86 (KINETIS_IRQ_FIRST+86) /* 86: Reserved */ +#define KINETIS_IRQ_PORTA (KINETIS_IRQ_FIRST+87) /* 87: Pin detect port A */ +#define KINETIS_IRQ_PORTB (KINETIS_IRQ_FIRST+88) /* 88: Pin detect port B */ +#define KINETIS_IRQ_PORTC (KINETIS_IRQ_FIRST+89) /* 89: Pin detect port C */ +#define KINETIS_IRQ_PORTD (KINETIS_IRQ_FIRST+90) /* 90: Pin detect port D */ +#define KINETIS_IRQ_PORTE (KINETIS_IRQ_FIRST+91) /* 91: Pin detect port E */ +#define KINETIS_IRQ_RESVD92 (KINETIS_IRQ_FIRST+92) /* 92: Reserved */ +#define KINETIS_IRQ_RESVD93 (KINETIS_IRQ_FIRST+93) /* 93: Reserved */ +#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST+94) /* 94: Software interrupt */ + +#define NR_INTERRUPTS 95 /* 95 Non core IRQs*/ +#define NR_VECTORS (KINETIS_IRQ_FIRST+NR_INTERRUPTS) /* 111 vectors */ + +/* EXTI interrupts (Do not use IRQ numbers) */ + +#define NR_IRQS NR_VECTORS + +/***************************************************************************** + * Public Types + ****************************************************************************/ + +/***************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/***************************************************************************** + * Public Functions + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_60KIRQ_H */ diff --git a/arch/arm/include/kinetis/kinetis_k64irq.h b/arch/arm/include/kinetis/kinetis_k64irq.h new file mode 100644 index 0000000000..c97c4b2512 --- /dev/null +++ b/arch/arm/include/kinetis/kinetis_k64irq.h @@ -0,0 +1,190 @@ +/***************************************************************************** + * arch/arm/include/kinetis/kinetis_k64irq.h + * + * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_64KIRQ_H +#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_64KIRQ_H + +/***************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/***************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. + * + * Processor Exceptions (vectors 0-15). These common definitions can be found + * in the file nuttx/arch/arm/include/kinets/irq.h which includes this file + * + * External interrupts (vectors >= 16) + * + * K60 Family **************************************************************** + * + * The interrupt vectors for the following parts is defined in Freescale + * document K64P144M120SF5RM.pdf + */ +#define KINETIS_IRQ_DMACH0 (KINETIS_IRQ_FIRST+0) /* 0: DMA channel 0 transfer complete */ +#define KINETIS_IRQ_DMACH1 (KINETIS_IRQ_FIRST+1) /* 1: DMA channel 1 transfer complete */ +#define KINETIS_IRQ_DMACH2 (KINETIS_IRQ_FIRST+2) /* 2: DMA channel 2 transfer complete */ +#define KINETIS_IRQ_DMACH3 (KINETIS_IRQ_FIRST+3) /* 3: DMA channel 3 transfer complete */ +#define KINETIS_IRQ_DMACH4 (KINETIS_IRQ_FIRST+4) /* 4: DMA channel 4 transfer complete */ +#define KINETIS_IRQ_DMACH5 (KINETIS_IRQ_FIRST+5) /* 5: DMA channel 5 transfer complete */ +#define KINETIS_IRQ_DMACH6 (KINETIS_IRQ_FIRST+6) /* 6: DMA channel 6 transfer complete */ +#define KINETIS_IRQ_DMACH7 (KINETIS_IRQ_FIRST+7) /* 7: DMA channel 7 transfer complete */ +#define KINETIS_IRQ_DMACH8 (KINETIS_IRQ_FIRST+8) /* 8: DMA channel 8 transfer complete */ +#define KINETIS_IRQ_DMACH9 (KINETIS_IRQ_FIRST+9) /* 9: DMA channel 9 transfer complete */ +#define KINETIS_IRQ_DMACH10 (KINETIS_IRQ_FIRST+10) /* 10: DMA channel 10 transfer complete */ +#define KINETIS_IRQ_DMACH11 (KINETIS_IRQ_FIRST+11) /* 11: DMA channel 11 transfer complete */ +#define KINETIS_IRQ_DMACH12 (KINETIS_IRQ_FIRST+12) /* 12: DMA channel 12 transfer complete */ +#define KINETIS_IRQ_DMACH13 (KINETIS_IRQ_FIRST+13) /* 13: DMA channel 13 transfer complete */ +#define KINETIS_IRQ_DMACH14 (KINETIS_IRQ_FIRST+14) /* 14: DMA channel 14 transfer complete */ +#define KINETIS_IRQ_DMACH15 (KINETIS_IRQ_FIRST+15) /* 15: DMA channel 15 transfer complete */ +#define KINETIS_IRQ_DMAERR (KINETIS_IRQ_FIRST+16) /* 16: DMA error interrupt channels 0-15 */ +#define KINETIS_IRQ_MCM (KINETIS_IRQ_FIRST+17) /* 17: MCM Normal interrupt */ +#define KINETIS_IRQ_FLASHCC (KINETIS_IRQ_FIRST+18) /* 18: Flash memory command complete */ +#define KINETIS_IRQ_FLASHRC (KINETIS_IRQ_FIRST+19) /* 19: Flash memory read collision */ +#define KINETIS_IRQ_SMCLVD (KINETIS_IRQ_FIRST+20) /* 20: Mode Controller low-voltage + * detect, low-voltage warning */ +#define KINETIS_IRQ_LLWU (KINETIS_IRQ_FIRST+21) /* 21: LLWU Normal Low Leakage Wakeup */ +#define KINETIS_IRQ_WDOG (KINETIS_IRQ_FIRST+22) /* 22: Watchdog or EWM */ +#define KINETIS_IRQ_RNGB (KINETIS_IRQ_FIRST+23) /* 23: Random number generator */ +#define KINETIS_IRQ_I2C0 (KINETIS_IRQ_FIRST+24) /* 24: I2C0 */ +#define KINETIS_IRQ_I2C1 (KINETIS_IRQ_FIRST+25) /* 25: I2C1 */ +#define KINETIS_IRQ_SPI0 (KINETIS_IRQ_FIRST+26) /* 26: SPI0 all sources */ +#define KINETIS_IRQ_SPI1 (KINETIS_IRQ_FIRST+27) /* 27: SPI1 all sources */ +#define KINETIS_IRQ_I2S0 (KINETIS_IRQ_FIRST+28) /* 28: 12S0 Transmit */ +#define KINETIS_IRQ_I2S1 (KINETIS_IRQ_FIRST+29) /* 29: 12S0 Receive */ +#define KINETIS_IRQ_RESVD30 (KINETIS_IRQ_FIRST+30) /* 30: Reserved */ +#define KINETIS_IRQ_UART0S (KINETIS_IRQ_FIRST+31) /* 31: UART0 status */ +#define KINETIS_IRQ_UART0E (KINETIS_IRQ_FIRST+32) /* 32: UART0 error */ +#define KINETIS_IRQ_UART1S (KINETIS_IRQ_FIRST+33) /* 33: UART1 status */ +#define KINETIS_IRQ_UART1E (KINETIS_IRQ_FIRST+34) /* 34: UART1 error */ +#define KINETIS_IRQ_UART2S (KINETIS_IRQ_FIRST+35) /* 35: UART2 status */ +#define KINETIS_IRQ_UART2E (KINETIS_IRQ_FIRST+36) /* 36: UART2 error */ +#define KINETIS_IRQ_UART3S (KINETIS_IRQ_FIRST+37) /* 37: UART3 status */ +#define KINETIS_IRQ_UART3E (KINETIS_IRQ_FIRST+38) /* 38: UART3 error */ +#define KINETIS_IRQ_ADC0 (KINETIS_IRQ_FIRST+39) /* 39: ADC0 */ +#define KINETIS_IRQ_CMP0 (KINETIS_IRQ_FIRST+40) /* 40: CMP0 */ +#define KINETIS_IRQ_CMP1 (KINETIS_IRQ_FIRST+41) /* 41: CMP1 */ +#define KINETIS_IRQ_FTM0 (KINETIS_IRQ_FIRST+42) /* 42: FTM0 all sources */ +#define KINETIS_IRQ_FTM1 (KINETIS_IRQ_FIRST+43) /* 43: FTM1 all sources */ +#define KINETIS_IRQ_FTM2 (KINETIS_IRQ_FIRST+44) /* 44: FTM2 all sources */ +#define KINETIS_IRQ_CMT (KINETIS_IRQ_FIRST+45) /* 45: CMT */ +#define KINETIS_IRQ_RTC (KINETIS_IRQ_FIRST+46) /* 46: RTC alarm interrupt */ +#define KINETIS_IRQ_RTCS (KINETIS_IRQ_FIRST+47) /* 47: RTC seconds interrupt */ +#define KINETIS_IRQ_PITCH0 (KINETIS_IRQ_FIRST+48) /* 48: PIT channel 0 */ +#define KINETIS_IRQ_PITCH1 (KINETIS_IRQ_FIRST+49) /* 49: PIT channel 1 */ +#define KINETIS_IRQ_PITCH2 (KINETIS_IRQ_FIRST+50) /* 50: PIT channel 2 */ +#define KINETIS_IRQ_PITCH3 (KINETIS_IRQ_FIRST+51) /* 51: PIT channel 3 */ +#define KINETIS_IRQ_PDB (KINETIS_IRQ_FIRST+52) /* 52: PDB */ +#define KINETIS_IRQ_USBOTG (KINETIS_IRQ_FIRST+53) /* 53: USB OTG */ +#define KINETIS_IRQ_USBCD (KINETIS_IRQ_FIRST+54) /* 54: USB charger detect */ +#define KINETIS_IRQ_RESVD55 (KINETIS_IRQ_FIRST+55) /* 55: Reserved */ +#define KINETIS_IRQ_DAC0 (KINETIS_IRQ_FIRST+56) /* 56: DAC0 */ +#define KINETIS_IRQ_MCG (KINETIS_IRQ_FIRST+57) /* 57: MCG */ +#define KINETIS_IRQ_LPT (KINETIS_IRQ_FIRST+58) /* 58: Low power timer */ +#define KINETIS_IRQ_PORTA (KINETIS_IRQ_FIRST+59) /* 59: Pin detect port A */ +#define KINETIS_IRQ_PORTB (KINETIS_IRQ_FIRST+60) /* 60: Pin detect port B */ +#define KINETIS_IRQ_PORTC (KINETIS_IRQ_FIRST+61) /* 61: Pin detect port C */ +#define KINETIS_IRQ_PORTD (KINETIS_IRQ_FIRST+62) /* 62: Pin detect port D */ +#define KINETIS_IRQ_PORTE (KINETIS_IRQ_FIRST+63) /* 63: Pin detect port E */ +#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST+64) /* 64: Software interrupt */ +#define KINETIS_IRQ_SPI2 (KINETIS_IRQ_FIRST+65) /* 65: SPI2 all sources */ +#define KINETIS_IRQ_UART4S (KINETIS_IRQ_FIRST+66) /* 66: UART4 status */ +#define KINETIS_IRQ_UART4E (KINETIS_IRQ_FIRST+67) /* 67: UART4 error */ +#define KINETIS_IRQ_UART5S (KINETIS_IRQ_FIRST+68) /* 68: UART5 status */ +#define KINETIS_IRQ_UART5E (KINETIS_IRQ_FIRST+69) /* 69: UART5 error */ +#define KINETIS_IRQ_CMP2 (KINETIS_IRQ_FIRST+70) /* 70: CMP2 */ +#define KINETIS_IRQ_FTM3 (KINETIS_IRQ_FIRST+71) /* 71: FTM3 all sources */ +#define KINETIS_IRQ_DAC1 (KINETIS_IRQ_FIRST+72) /* 72: DAC1 */ +#define KINETIS_IRQ_ADC1 (KINETIS_IRQ_FIRST+73) /* 73: ADC1 */ +#define KINETIS_IRQ_I2C2 (KINETIS_IRQ_FIRST+74) /* 74: I2C2 */ +#define KINETIS_IRQ_CAN0MB (KINETIS_IRQ_FIRST+75) /* 75: CAN0 OR'ed Message buffer (0-15) */ +#define KINETIS_IRQ_CAN0BO (KINETIS_IRQ_FIRST+76) /* 76: CAN0 Bus Off */ +#define KINETIS_IRQ_CAN0ERR (KINETIS_IRQ_FIRST+77) /* 77: CAN0 Error */ +#define KINETIS_IRQ_CAN0TW (KINETIS_IRQ_FIRST+78) /* 78: CAN0 Transmit Warning */ +#define KINETIS_IRQ_CAN0RW (KINETIS_IRQ_FIRST+79) /* 79: CAN0 Receive Warning */ +#define KINETIS_IRQ_CAN0WU (KINETIS_IRQ_FIRST+80) /* 80: CAN0 Wake UP */ +#define KINETIS_IRQ_SDHC (KINETIS_IRQ_FIRST+81) /* 81: SDHC */ +#define KINETIS_IRQ_EMACTMR (KINETIS_IRQ_FIRST+82) /* 82: Ethernet MAC IEEE 1588 timer interrupt */ +#define KINETIS_IRQ_EMACTX (KINETIS_IRQ_FIRST+83) /* 83: Ethernet MAC transmit interrupt */ +#define KINETIS_IRQ_EMACRX (KINETIS_IRQ_FIRST+84) /* 84: Ethernet MAC receive interrupt */ +#define KINETIS_IRQ_EMACMISC (KINETIS_IRQ_FIRST+85) /* 85: Ethernet MAC error and misc interrupt */ + +#define NR_INTERRUPTS 86 /* 86 Non core IRQs*/ +#define NR_VECTORS (KINETIS_IRQ_FIRST+NR_INTERRUPTS) /* 102 vectors */ + +/* EXTI interrupts (Do not use IRQ numbers) */ + +#define NR_IRQS NR_VECTORS + +/***************************************************************************** + * Public Types + ****************************************************************************/ + +/***************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/***************************************************************************** + * Public Functions + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_64KIRQ_H */ diff --git a/arch/arm/include/kinetis/kinetis_k66irq.h b/arch/arm/include/kinetis/kinetis_k66irq.h new file mode 100644 index 0000000000..bbf0903f5a --- /dev/null +++ b/arch/arm/include/kinetis/kinetis_k66irq.h @@ -0,0 +1,206 @@ +/***************************************************************************** + * arch/arm/include/kinetis/kinetis_k66irq.h + * + * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_66KIRQ_H +#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_66KIRQ_H + +/***************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/***************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. + * + * Processor Exceptions (vectors 0-15). These common definitions can be found + * in the file nuttx/arch/arm/include/kinets/irq.h which includes this file + * + * External interrupts (vectors >= 16) + * + * K66 Family **************************************************************** + * + * The interrupt vectors for the following parts is defined in Freescale + * document K66P144M180SF5RMV2 + */ + +#define KINETIS_IRQ_DMACH0 (KINETIS_IRQ_FIRST+0) /* 0: DMA channel 0, 16 transfer complete */ +#define KINETIS_IRQ_DMACH1 (KINETIS_IRQ_FIRST+1) /* 1: DMA channel 1, 17 transfer complete */ +#define KINETIS_IRQ_DMACH2 (KINETIS_IRQ_FIRST+2) /* 2: DMA channel 2, 18 transfer complete */ +#define KINETIS_IRQ_DMACH3 (KINETIS_IRQ_FIRST+3) /* 3: DMA channel 3, 19 transfer complete */ +#define KINETIS_IRQ_DMACH4 (KINETIS_IRQ_FIRST+4) /* 4: DMA channel 4, 20 transfer complete */ +#define KINETIS_IRQ_DMACH5 (KINETIS_IRQ_FIRST+5) /* 5: DMA channel 5, 21 transfer complete */ +#define KINETIS_IRQ_DMACH6 (KINETIS_IRQ_FIRST+6) /* 6: DMA channel 6, 11 transfer complete */ +#define KINETIS_IRQ_DMACH7 (KINETIS_IRQ_FIRST+7) /* 7: DMA channel 7, 23 transfer complete */ +#define KINETIS_IRQ_DMACH8 (KINETIS_IRQ_FIRST+8) /* 8: DMA channel 8, 24 transfer complete */ +#define KINETIS_IRQ_DMACH9 (KINETIS_IRQ_FIRST+9) /* 9: DMA channel 9, 25 transfer complete */ +#define KINETIS_IRQ_DMACH10 (KINETIS_IRQ_FIRST+10) /* 10: DMA channel 10, 26 transfer complete */ +#define KINETIS_IRQ_DMACH11 (KINETIS_IRQ_FIRST+11) /* 11: DMA channel 11, 27 transfer complete */ +#define KINETIS_IRQ_DMACH12 (KINETIS_IRQ_FIRST+12) /* 12: DMA channel 12, 28 transfer complete */ +#define KINETIS_IRQ_DMACH13 (KINETIS_IRQ_FIRST+13) /* 13: DMA channel 13, 29 transfer complete */ +#define KINETIS_IRQ_DMACH14 (KINETIS_IRQ_FIRST+14) /* 14: DMA channel 14, 30 transfer complete */ +#define KINETIS_IRQ_DMACH15 (KINETIS_IRQ_FIRST+15) /* 15: DMA channel 15, 31 transfer complete */ +#define KINETIS_IRQ_DMAERR (KINETIS_IRQ_FIRST+16) /* 16: DMA error interrupt channels 0-31 */ +#define KINETIS_IRQ_MCM (KINETIS_IRQ_FIRST+17) /* 17: MCM Normal interrupt */ +#define KINETIS_IRQ_FLASHCC (KINETIS_IRQ_FIRST+18) /* 18: Flash memory command complete */ +#define KINETIS_IRQ_FLASHRC (KINETIS_IRQ_FIRST+19) /* 19: Flash memory read collision */ +#define KINETIS_IRQ_SMCLVD (KINETIS_IRQ_FIRST+20) /* 20: Mode Controller low-voltage + * detect, low-voltage warning */ +#define KINETIS_IRQ_LLWU (KINETIS_IRQ_FIRST+21) /* 21: LLWU Normal Low Leakage Wakeup */ +#define KINETIS_IRQ_WDOG (KINETIS_IRQ_FIRST+22) /* 22: Watchdog or EWM */ +#define KINETIS_IRQ_RNGB (KINETIS_IRQ_FIRST+23) /* 23: Random number generator */ +#define KINETIS_IRQ_I2C0 (KINETIS_IRQ_FIRST+24) /* 24: I2C0 */ +#define KINETIS_IRQ_I2C1 (KINETIS_IRQ_FIRST+25) /* 25: I2C1 */ +#define KINETIS_IRQ_SPI0 (KINETIS_IRQ_FIRST+26) /* 26: SPI0 all sources */ +#define KINETIS_IRQ_SPI1 (KINETIS_IRQ_FIRST+27) /* 27: SPI1 all sources */ +#define KINETIS_IRQ_I2S0 (KINETIS_IRQ_FIRST+28) /* 28: 12S0 Transmit */ +#define KINETIS_IRQ_I2S1 (KINETIS_IRQ_FIRST+29) /* 29: 12S0 Receive */ +#define KINETIS_IRQ_RESVD30 (KINETIS_IRQ_FIRST+30) /* 30: Reserved */ +#define KINETIS_IRQ_UART0S (KINETIS_IRQ_FIRST+31) /* 31: UART0 status */ +#define KINETIS_IRQ_UART0E (KINETIS_IRQ_FIRST+32) /* 32: UART0 error */ +#define KINETIS_IRQ_UART1S (KINETIS_IRQ_FIRST+33) /* 33: UART1 status */ +#define KINETIS_IRQ_UART1E (KINETIS_IRQ_FIRST+34) /* 34: UART1 error */ +#define KINETIS_IRQ_UART2S (KINETIS_IRQ_FIRST+35) /* 35: UART2 status */ +#define KINETIS_IRQ_UART2E (KINETIS_IRQ_FIRST+36) /* 36: UART2 error */ +#define KINETIS_IRQ_UART3S (KINETIS_IRQ_FIRST+37) /* 37: UART3 status */ +#define KINETIS_IRQ_UART3E (KINETIS_IRQ_FIRST+38) /* 38: UART3 error */ +#define KINETIS_IRQ_ADC0 (KINETIS_IRQ_FIRST+39) /* 39: ADC0 */ +#define KINETIS_IRQ_CMP0 (KINETIS_IRQ_FIRST+40) /* 40: CMP0 */ +#define KINETIS_IRQ_CMP1 (KINETIS_IRQ_FIRST+41) /* 41: CMP1 */ +#define KINETIS_IRQ_FTM0 (KINETIS_IRQ_FIRST+42) /* 42: FTM0 all sources */ +#define KINETIS_IRQ_FTM1 (KINETIS_IRQ_FIRST+43) /* 43: FTM1 all sources */ +#define KINETIS_IRQ_FTM2 (KINETIS_IRQ_FIRST+44) /* 44: FTM2 all sources */ +#define KINETIS_IRQ_CMT (KINETIS_IRQ_FIRST+45) /* 45: CMT */ +#define KINETIS_IRQ_RTC (KINETIS_IRQ_FIRST+46) /* 46: RTC alarm interrupt */ +#define KINETIS_IRQ_RTCS (KINETIS_IRQ_FIRST+47) /* 47: RTC seconds interrupt */ +#define KINETIS_IRQ_PITCH0 (KINETIS_IRQ_FIRST+48) /* 48: PIT channel 0 */ +#define KINETIS_IRQ_PITCH1 (KINETIS_IRQ_FIRST+49) /* 49: PIT channel 1 */ +#define KINETIS_IRQ_PITCH2 (KINETIS_IRQ_FIRST+50) /* 50: PIT channel 2 */ +#define KINETIS_IRQ_PITCH3 (KINETIS_IRQ_FIRST+51) /* 51: PIT channel 3 */ +#define KINETIS_IRQ_PDB (KINETIS_IRQ_FIRST+52) /* 52: PDB */ +#define KINETIS_IRQ_USBOTG (KINETIS_IRQ_FIRST+53) /* 53: USB OTG */ +#define KINETIS_IRQ_USBCD (KINETIS_IRQ_FIRST+54) /* 54: USB charger detect */ +#define KINETIS_IRQ_RESVD55 (KINETIS_IRQ_FIRST+55) /* 55: Reserved */ +#define KINETIS_IRQ_DAC0 (KINETIS_IRQ_FIRST+56) /* 56: DAC0 */ +#define KINETIS_IRQ_MCG (KINETIS_IRQ_FIRST+57) /* 57: MCG */ +#define KINETIS_IRQ_LPT (KINETIS_IRQ_FIRST+58) /* 58: Low power timer */ +#define KINETIS_IRQ_PORTA (KINETIS_IRQ_FIRST+59) /* 59: Pin detect port A */ +#define KINETIS_IRQ_PORTB (KINETIS_IRQ_FIRST+60) /* 60: Pin detect port B */ +#define KINETIS_IRQ_PORTC (KINETIS_IRQ_FIRST+61) /* 61: Pin detect port C */ +#define KINETIS_IRQ_PORTD (KINETIS_IRQ_FIRST+62) /* 62: Pin detect port D */ +#define KINETIS_IRQ_PORTE (KINETIS_IRQ_FIRST+63) /* 63: Pin detect port E */ +#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST+64) /* 64: Software interrupt */ +#define KINETIS_IRQ_SPI2 (KINETIS_IRQ_FIRST+65) /* 65: SPI2 all sources */ +#define KINETIS_IRQ_UART4S (KINETIS_IRQ_FIRST+66) /* 66: UART4 status */ +#define KINETIS_IRQ_UART4E (KINETIS_IRQ_FIRST+67) /* 67: UART4 error */ +#define KINETIS_IRQ_RESVD68 (KINETIS_IRQ_FIRST+68) /* 68: Reserved */ +#define KINETIS_IRQ_RESVD69 (KINETIS_IRQ_FIRST+69) /* 69: Reserved */ +#define KINETIS_IRQ_CMP2 (KINETIS_IRQ_FIRST+70) /* 70: CMP2 */ +#define KINETIS_IRQ_FTM3 (KINETIS_IRQ_FIRST+71) /* 71: FTM3 all sources */ +#define KINETIS_IRQ_DAC1 (KINETIS_IRQ_FIRST+72) /* 72: DAC1 */ +#define KINETIS_IRQ_ADC1 (KINETIS_IRQ_FIRST+73) /* 73: ADC1 */ +#define KINETIS_IRQ_I2C2 (KINETIS_IRQ_FIRST+74) /* 74: I2C2 */ +#define KINETIS_IRQ_CAN0MB (KINETIS_IRQ_FIRST+75) /* 75: CAN0 OR'ed Message buffer (0-15) */ +#define KINETIS_IRQ_CAN0BO (KINETIS_IRQ_FIRST+76) /* 76: CAN0 Bus Off */ +#define KINETIS_IRQ_CAN0ERR (KINETIS_IRQ_FIRST+77) /* 77: CAN0 Error */ +#define KINETIS_IRQ_CAN0TW (KINETIS_IRQ_FIRST+78) /* 78: CAN0 Transmit Warning */ +#define KINETIS_IRQ_CAN0RW (KINETIS_IRQ_FIRST+79) /* 79: CAN0 Receive Warning */ +#define KINETIS_IRQ_CAN0WU (KINETIS_IRQ_FIRST+80) /* 80: CAN0 Wake UP */ +#define KINETIS_IRQ_SDHC (KINETIS_IRQ_FIRST+81) /* 81: SDHC */ +#define KINETIS_IRQ_EMACTMR (KINETIS_IRQ_FIRST+82) /* 82: Ethernet MAC IEEE 1588 timer interrupt */ +#define KINETIS_IRQ_EMACTX (KINETIS_IRQ_FIRST+83) /* 83: Ethernet MAC transmit interrupt */ +#define KINETIS_IRQ_EMACRX (KINETIS_IRQ_FIRST+84) /* 84: Ethernet MAC receive interrupt */ +#define KINETIS_IRQ_EMACMISC (KINETIS_IRQ_FIRST+85) /* 85: Ethernet MAC error and misc interrupt */ +#define KINETIS_IRQ_LPUART0 (KINETIS_IRQ_FIRST+86) /* 86: LPUART0 Status and error */ +#define KINETIS_IRQ_TSI0 (KINETIS_IRQ_FIRST+87) /* 87: TSI0 */ +#define KINETIS_IRQ_TPM1 (KINETIS_IRQ_FIRST+88) /* 88: TPM1 */ +#define KINETIS_IRQ_TPM2 (KINETIS_IRQ_FIRST+89) /* 89: TPM2 */ +#define KINETIS_IRQ_USBHSDCD (KINETIS_IRQ_FIRST+90) /* 90: shared by USBHS DCD & USBHS Phy modules */ +#define KINETIS_IRQ_I2C3 (KINETIS_IRQ_FIRST+91) /* 91: I2C3 */ +#define KINETIS_IRQ_CMP3 (KINETIS_IRQ_FIRST+92) /* 92: CMP3 */ +#define KINETIS_IRQ_USBHSOTG (KINETIS_IRQ_FIRST+93) /* 93: USBHS OTG*/ +#define KINETIS_IRQ_CAN1MB (KINETIS_IRQ_FIRST+94) /* 94: CAN1 OR'ed Message buffer (0-15) */ +#define KINETIS_IRQ_CAN1BO (KINETIS_IRQ_FIRST+95) /* 95: CAN1 Bus Off */ +#define KINETIS_IRQ_CAN1ERR (KINETIS_IRQ_FIRST+96) /* 96: CAN1 Error */ +#define KINETIS_IRQ_CAN1TW (KINETIS_IRQ_FIRST+97) /* 97: CAN1 Transmit Warning */ +#define KINETIS_IRQ_CAN1RW (KINETIS_IRQ_FIRST+98) /* 98: CAN1 Receive Warning */ +#define KINETIS_IRQ_CAN1WU (KINETIS_IRQ_FIRST+99) /* 99: CAN1 Wake UP */ + + +#define NR_INTERRUPTS 100 /* 100 Non core IRQs*/ +#define NR_VECTORS (KINETIS_IRQ_FIRST+NR_INTERRUPTS) /* 116 vectors */ + +/* EXTI interrupts (Do not use IRQ numbers) */ + +#define NR_IRQS NR_VECTORS + +/***************************************************************************** + * Public Types + ****************************************************************************/ + +/***************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/***************************************************************************** + * Public Functions + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_66KIRQ_H */ diff --git a/arch/arm/src/kinetis/Make.defs b/arch/arm/src/kinetis/Make.defs index f27bf25fae..e4dd09df79 100644 --- a/arch/arm/src/kinetis/Make.defs +++ b/arch/arm/src/kinetis/Make.defs @@ -33,11 +33,14 @@ # ############################################################################ -# The start-up, "head", file - +ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y) +HEAD_ASRC = +else HEAD_ASRC = kinetis_vectors.S +endif -# Common ARM and Cortex-M3 files +CMN_UASRCS = +CMN_UCSRCS = CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S CMN_ASRCS += up_testset.S vfork.S @@ -48,9 +51,22 @@ CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_modifyreg8.c CMN_CSRCS += up_modifyreg16.c up_modifyreg32.c up_releasestack.c CMN_CSRCS += up_reprioritizertr.c up_schedulesigaction.c up_releasepending.c CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_unblocktask.c up_usestack.c -CMN_CSRCS += up_doirq.c up_hardfault.c up_svcall.c up_checkstack.c up_vfork.c +CMN_CSRCS += up_doirq.c up_hardfault.c up_svcall.c up_vfork.c CMN_CSRCS += up_systemreset.c +ifeq ($(CONFIG_ARMV7M_STACKCHECK),y) +CMN_CSRCS += up_stackcheck.c +endif + +ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y) +ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) +CMN_ASRCS += up_lazyexception.S +else +CMN_ASRCS += up_exception.S +endif +CMN_CSRCS += up_vectors.c +endif + ifeq ($(CONFIG_ARCH_RAMVECTORS),y) CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c endif @@ -67,6 +83,10 @@ CMN_UASRCS += up_signal_handler.S endif endif +ifeq ($(CONFIG_STACK_COLORATION),y) +CMN_CSRCS += up_checkstack.c +endif + # Use of common/up_etherstub.c is deprecated. The preferred mechanism is to # use CONFIG_NETDEV_LATEINIT=y to suppress the call to up_netinitialize() in # up_initialize(). Then this stub would not be needed. @@ -83,6 +103,19 @@ else ifeq ($(CONFIG_MODULE),y) CMN_CSRCS += up_elf.c endif +ifeq ($(CONFIG_ARCH_FPU),y) +CMN_ASRCS += up_fpu.S +ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y) +CMN_CSRCS += up_copyarmstate.c +else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) +CMN_CSRCS += up_copyarmstate.c +endif +endif + +ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y) +CMN_CSRCS += up_itm_syslog.c +endif + # Required Kinetis files CHIP_ASRCS = diff --git a/arch/arm/src/kinetis/chip.h b/arch/arm/src/kinetis/chip.h index 26fa7e38a0..c16f31b14d 100644 --- a/arch/arm/src/kinetis/chip.h +++ b/arch/arm/src/kinetis/chip.h @@ -46,9 +46,18 @@ * should then include this file for the proper setup. */ +#include #include #include "chip/kinetis_memorymap.h" +/* If the common ARMv7-M vector handling logic is used, then it expects the + * following definition in this file that provides the number of supported external + * interrupts which, for this architecture, is provided in the arch/stm32f7/chip.h + * header file. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS NR_INTERRUPTS + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ diff --git a/arch/arm/src/kinetis/chip/kinetis_k20vectors.h b/arch/arm/src/kinetis/chip/kinetis_k20vectors.h new file mode 100644 index 0000000000..ef0730d4ae --- /dev/null +++ b/arch/arm/src/kinetis/chip/kinetis_k20vectors.h @@ -0,0 +1,156 @@ +/************************************************************************************ + * arch/arm/src/kinetis/chip/kinetis_k20vectors.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor definitions + ************************************************************************************/ +/* This file is included by kinetis_vectors.S. It provides the macro VECTOR that + * supplies ach K20 vector in terms of a (lower-case) ISR label and an + * (upper-case) IRQ number as defined in arch/arm/include/kinetis/kinetis_k20irq.h. + * kinetis_vectors.S will defined the VECTOR in different ways in order to generate + * the interrupt vectors and handlers in their final form. + */ + +#if defined(CONFIG_ARCH_FAMILY_K20) + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +# ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS NR_INTERRUPTS + +# else +VECTOR(kinetis_dmach0, KINETIS_IRQ_DMACH0) /* Vector 16: DMA channel 0 transfer complete */ +VECTOR(kinetis_dmach1, KINETIS_IRQ_DMACH1) /* Vector 17: DMA channel 1 transfer complete */ +VECTOR(kinetis_dmach2, KINETIS_IRQ_DMACH2) /* Vector 18: DMA channel 2 transfer complete */ +VECTOR(kinetis_dmach3, KINETIS_IRQ_DMACH3) /* Vector 19: DMA channel 3 transfer complete */ +VECTOR(kinetis_dmach4, KINETIS_IRQ_DMACH4) /* Vector 20: DMA channel 4 transfer complete */ +VECTOR(kinetis_dmach5, KINETIS_IRQ_DMACH5) /* Vector 21: DMA channel 5 transfer complete */ +VECTOR(kinetis_dmach6, KINETIS_IRQ_DMACH6) /* Vector 22: DMA channel 6 transfer complete */ +VECTOR(kinetis_dmach7, KINETIS_IRQ_DMACH7) /* Vector 23: DMA channel 7 transfer complete */ +VECTOR(kinetis_dmach8, KINETIS_IRQ_DMACH8) /* Vector 24: DMA channel 8 transfer complete */ +VECTOR(kinetis_dmach9, KINETIS_IRQ_DMACH9) /* Vector 25: DMA channel 9 transfer complete */ +VECTOR(kinetis_dmach10, KINETIS_IRQ_DMACH10) /* Vector 26: DMA channel 10 transfer complete */ +VECTOR(kinetis_dmach11, KINETIS_IRQ_DMACH11) /* Vector 27: DMA channel 11 transfer complete */ +VECTOR(kinetis_dmach12, KINETIS_IRQ_DMACH12) /* Vector 28: DMA channel 12 transfer complete */ +VECTOR(kinetis_dmach13, KINETIS_IRQ_DMACH13) /* Vector 29: DMA channel 13 transfer complete */ +VECTOR(kinetis_dmach14, KINETIS_IRQ_DMACH14) /* Vector 30: DMA channel 14 transfer complete */ +VECTOR(kinetis_dmach15, KINETIS_IRQ_DMACH15) /* Vector 31: DMA channel 15 transfer complete */ +VECTOR(kinetis_dmaerr, KINETIS_IRQ_DMAERR) /* Vector 32: DMA error interrupt channels 0-15 */ +UNUSED(KINETIS_IRQ_RESVD17) /* Vector 33: Reserved */ +VECTOR(kinetis_flashcc, KINETIS_IRQ_FLASHCC) /* Vector 34: Flash memory command complete */ +VECTOR(kinetis_flashrc, KINETIS_IRQ_FLASHRC) /* Vector 35: Flash memory read collision */ +VECTOR(kinetis_smclvd, KINETIS_IRQ_SMCLVD) /* Vector 36: Mode Controller low-voltage detect, low-voltage warning */ +VECTOR(kinetis_llwu, KINETIS_IRQ_LLWU) /* Vector 37: LLWU Normal Low Leakage Wakeup */ +VECTOR(kinetis_wdog, KINETIS_IRQ_WDOG) /* Vector 38: Watchdog */ +UNUSED(KINETIS_IRQ_RESVD23) /* Vector 39: Reserved */ +VECTOR(kinetis_i2c0, KINETIS_IRQ_I2C0) /* Vector 40: I2C0 */ +VECTOR(kinetis_i2c1, KINETIS_IRQ_I2C1) /* Vector 41: I2C1 */ +VECTOR(kinetis_spi0, KINETIS_IRQ_SPI0) /* Vector 42: SPI0 all sources */ +VECTOR(kinetis_spi1, KINETIS_IRQ_SPI1) /* Vector 43: SPI1 all sources */ +UNUSED(KINETIS_IRQ_RESVD28) /* Vector 44: Reserved */ +VECTOR(kinetis_can0mb, KINETIS_IRQ_CAN0MB) /* Vector 45: CAN0 OR'ed Message buffer (0-15) */ +VECTOR(kinetis_can0bo, KINETIS_IRQ_CAN0BO) /* Vector 46: CAN0 Bus Off */ +VECTOR(kinetis_can0err, KINETIS_IRQ_CAN0ERR) /* Vector 47: CAN0 Error */ +VECTOR(kinetis_can0tw, KINETIS_IRQ_CAN0TW) /* Vector 48: CAN0 Transmit Warning */ +VECTOR(kinetis_can0rw, KINETIS_IRQ_CAN0RW) /* Vector 49: CAN0 Receive Warning */ +VECTOR(kinetis_can0wu, KINETIS_IRQ_CAN0WU) /* Vector 50: CAN0 Wake UP */ +UNUSED(KINETIS_IRQ_RESVD35) /* Vector 51: Reserved */ +UNUSED(KINETIS_IRQ_RESVD36) /* Vector 52: Reserved */ +UNUSED(KINETIS_IRQ_RESVD37) /* Vector 53: Reserved */ +UNUSED(KINETIS_IRQ_RESVD38) /* Vector 54: Reserved */ +UNUSED(KINETIS_IRQ_RESVD39) /* Vector 55: Reserved */ +UNUSED(KINETIS_IRQ_RESVD40) /* Vector 56: Reserved */ +UNUSED(KINETIS_IRQ_RESVD41) /* Vector 57: Reserved */ +UNUSED(KINETIS_IRQ_RESVD42) /* Vector 58: Reserved */ +UNUSED(KINETIS_IRQ_RESVD43) /* Vector 59: Reserved */ +VECTOR(kinetis_uart0l, KINETIS_IRQ_UART0L) /* Vector 60: UART0 LON */ +VECTOR(kinetis_uart0s, KINETIS_IRQ_UART0S) /* Vector 61: UART0 status */ +VECTOR(kinetis_uart0e, KINETIS_IRQ_UART0E) /* Vector 62: UART0 error */ +VECTOR(kinetis_uart1s, KINETIS_IRQ_UART1S) /* Vector 63: UART1 status */ +VECTOR(kinetis_uart1e, KINETIS_IRQ_UART1E) /* Vector 64: UART1 error */ +VECTOR(kinetis_uart2s, KINETIS_IRQ_UART2S) /* Vector 65: UART2 status */ +VECTOR(kinetis_uart2e, KINETIS_IRQ_UART2E) /* Vector 66: UART2 error */ +UNUSED(KINETIS_IRQ_RESVD51) /* Vector 67: Reserved */ +UNUSED(KINETIS_IRQ_RESVD52) /* Vector 68: Reserved */ +UNUSED(KINETIS_IRQ_RESVD53) /* Vector 69: Reserved */ +UNUSED(KINETIS_IRQ_RESVD54) /* Vector 70: Reserved */ +UNUSED(KINETIS_IRQ_RESVD55) /* Vector 71: Reserved */ +UNUSED(KINETIS_IRQ_RESVD56) /* Vector 72: Reserved */ +VECTOR(kinetis_adc0, KINETIS_IRQ_ADC0) /* Vector 73: ADC0 */ +VECTOR(kinetis_adc1, KINETIS_IRQ_ADC1) /* Vector 74: ADC1 */ +VECTOR(kinetis_cmp0, KINETIS_IRQ_CMP0) /* Vector 75: CMP0 */ +VECTOR(kinetis_cmp1, KINETIS_IRQ_CMP1) /* Vector 76: CMP1 */ +VECTOR(kinetis_cmp2, KINETIS_IRQ_CMP2) /* Vector 77: CMP2 */ +VECTOR(kinetis_ftm0, KINETIS_IRQ_FTM0) /* Vector 78: FTM0 all sources */ +VECTOR(kinetis_ftm1, KINETIS_IRQ_FTM1) /* Vector 79: FTM1 all sources */ +VECTOR(kinetis_ftm2, KINETIS_IRQ_FTM2) /* Vector 80: FTM2 all sources */ +VECTOR(kinetis_cmt, KINETIS_IRQ_CMT) /* Vector 81: CMT */ +VECTOR(kinetis_rtc, KINETIS_IRQ_RTC) /* Vector 82: RTC alarm interrupt */ +VECTOR(kinetis_rtcs, KINETIS_IRQ_RTCS) /* Vector 83: RTC seconds interrupt */ +VECTOR(kinetis_pitch0, KINETIS_IRQ_PITCH0) /* Vector 84: PIT channel 0 */ +VECTOR(kinetis_pitch1, KINETIS_IRQ_PITCH1) /* Vector 85: PIT channel 1 */ +VECTOR(kinetis_pitch2, KINETIS_IRQ_PITCH2) /* Vector 86: PIT channel 2 */ +VECTOR(kinetis_pitch3, KINETIS_IRQ_PITCH3) /* Vector 87: PIT channel 3 */ +VECTOR(kinetis_pdb, KINETIS_IRQ_PDB) /* Vector 88: PDB */ +VECTOR(kinetis_usbotg, KINETIS_IRQ_USBOTG) /* Vector 89: USB OTG */ +VECTOR(kinetis_usbcd, KINETIS_IRQ_USBCD) /* Vector 90: USB charger detect */ +UNUSED(KINETIS_IRQ_RESVD75) /* Vector 91: Reserved */ +UNUSED(KINETIS_IRQ_RESVD76) /* Vector 92: Reserved */ +UNUSED(KINETIS_IRQ_RESVD77) /* Vector 93: Reserved */ +UNUSED(KINETIS_IRQ_RESVD78) /* Vector 94: Reserved */ +UNUSED(KINETIS_IRQ_RESVD79) /* Vector 95: Reserved */ +UNUSED(KINETIS_IRQ_RESVD80) /* Vector 96: Reserved */ +VECTOR(kinetis_dac0, KINETIS_IRQ_DAC0) /* Vector 97: DAC0 */ +UNUSED(KINETIS_IRQ_RESVD82) /* Vector 98: Reserved */ +VECTOR(kinetis_tsi, KINETIS_IRQ_TSI) /* Vector 99: TSI all sources */ +VECTOR(kinetis_mcg, KINETIS_IRQ_MCG) /* Vector 100: MCG */ +VECTOR(kinetis_lpt, KINETIS_IRQ_LPT) /* Vector 101: Low power timer */ +UNUSED(KINETIS_IRQ_RESVD86) /* Vector 102: Reserved */ +VECTOR(kinetis_porta, KINETIS_IRQ_PORTA) /* Vector 103: Pin detect port A */ +VECTOR(kinetis_portb, KINETIS_IRQ_PORTB) /* Vector 104: Pin detect port B */ +VECTOR(kinetis_portc, KINETIS_IRQ_PORTC) /* Vector 105: Pin detect port C */ +VECTOR(kinetis_portd, KINETIS_IRQ_PORTD) /* Vector 106: Pin detect port D */ +VECTOR(kinetis_porte, KINETIS_IRQ_PORTE) /* Vector 107: Pin detect port E */ +UNUSED(KINETIS_IRQ_RESVD92) /* Vector 108: Reserved */ +UNUSED(KINETIS_IRQ_RESVD93) /* Vector 109: Reserved */ +VECTOR(kinetis_swi, KINETIS_IRQ_SWI) /* Vector 110: Software interrupt */ +# endif /* CONFIG_ARMV7M_CMNVECTOR */ +#endif /* CONFIG_STM32_CONNECTIVITYLINE */ diff --git a/arch/arm/src/kinetis/chip/kinetis_k40vectors.h b/arch/arm/src/kinetis/chip/kinetis_k40vectors.h new file mode 100644 index 0000000000..08aeb61e20 --- /dev/null +++ b/arch/arm/src/kinetis/chip/kinetis_k40vectors.h @@ -0,0 +1,156 @@ +/************************************************************************************ + * arch/arm/src/kinetis/chip/kinetis_k40vectors.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor definitions + ************************************************************************************/ +/* This file is included by kinetis_vectors.S. It provides the macro VECTOR that + * supplies ach K40 vector in terms of a (lower-case) ISR label and an + * (upper-case) IRQ number as defined in arch/arm/include/kinetis/kinetis_k40irq.h. + * kinetis_vectors.S will defined the VECTOR in different ways in order to generate + * the interrupt vectors and handlers in their final form. + */ + +#if defined(CONFIG_ARCH_FAMILY_K40) + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +# ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS NR_INTERRUPTS + +# else +VECTOR(kinetis_dmach0, KINETIS_IRQ_DMACH0) /* Vector 16: DMA channel 0 transfer complete */ +VECTOR(kinetis_dmach1, KINETIS_IRQ_DMACH1) /* Vector 17: DMA channel 1 transfer complete */ +VECTOR(kinetis_dmach2, KINETIS_IRQ_DMACH2) /* Vector 18: DMA channel 2 transfer complete */ +VECTOR(kinetis_dmach3, KINETIS_IRQ_DMACH3) /* Vector 19: DMA channel 3 transfer complete */ +VECTOR(kinetis_dmach4, KINETIS_IRQ_DMACH4) /* Vector 20: DMA channel 4 transfer complete */ +VECTOR(kinetis_dmach5, KINETIS_IRQ_DMACH5) /* Vector 21: DMA channel 5 transfer complete */ +VECTOR(kinetis_dmach6, KINETIS_IRQ_DMACH6) /* Vector 22: DMA channel 6 transfer complete */ +VECTOR(kinetis_dmach7, KINETIS_IRQ_DMACH7) /* Vector 23: DMA channel 7 transfer complete */ +VECTOR(kinetis_dmach8, KINETIS_IRQ_DMACH8) /* Vector 24: DMA channel 8 transfer complete */ +VECTOR(kinetis_dmach9, KINETIS_IRQ_DMACH9) /* Vector 25: DMA channel 9 transfer complete */ +VECTOR(kinetis_dmach10, KINETIS_IRQ_DMACH10) /* Vector 26: DMA channel 10 transfer complete */ +VECTOR(kinetis_dmach11, KINETIS_IRQ_DMACH11) /* Vector 27: DMA channel 11 transfer complete */ +VECTOR(kinetis_dmach12, KINETIS_IRQ_DMACH12) /* Vector 28: DMA channel 12 transfer complete */ +VECTOR(kinetis_dmach13, KINETIS_IRQ_DMACH13) /* Vector 29: DMA channel 13 transfer complete */ +VECTOR(kinetis_dmach14, KINETIS_IRQ_DMACH14) /* Vector 30: DMA channel 14 transfer complete */ +VECTOR(kinetis_dmach15, KINETIS_IRQ_DMACH15) /* Vector 31: DMA channel 15 transfer complete */ +VECTOR(kinetis_dmaerr, KINETIS_IRQ_DMAERR) /* Vector 32: DMA error interrupt channels 0-15 */ +VECTOR(kinetis_mcm, KINETIS_IRQ_MCM) /* Vector 33: MCM Normal interrupt */ +VECTOR(kinetis_flashcc, KINETIS_IRQ_FLASHCC) /* Vector 34: Flash memory command complete */ +VECTOR(kinetis_flashrc, KINETIS_IRQ_FLASHRC) /* Vector 35: Flash memory read collision */ +VECTOR(kinetis_smclvd, KINETIS_IRQ_SMCLVD) /* Vector 36: Mode Controller low-voltage detect, low-voltage warning */ +VECTOR(kinetis_llwu, KINETIS_IRQ_LLWU) /* Vector 37: LLWU Normal Low Leakage Wakeup */ +VECTOR(kinetis_wdog, KINETIS_IRQ_WDOG) /* Vector 38: Watchdog */ +UNUSED(KINETIS_IRQ_RESVD23) /* Vector 39: Reserved */ +VECTOR(kinetis_i2c0, KINETIS_IRQ_I2C0) /* Vector 40: I2C0 */ +VECTOR(kinetis_i2c1, KINETIS_IRQ_I2C1) /* Vector 41: I2C1 */ +VECTOR(kinetis_spi0, KINETIS_IRQ_SPI0) /* Vector 42: SPI0 all sources */ +VECTOR(kinetis_spi1, KINETIS_IRQ_SPI1) /* Vector 43: SPI1 all sources */ +VECTOR(kinetis_spi2, KINETIS_IRQ_SPI2) /* Vector 44: SPI2 all sources */ +VECTOR(kinetis_can0mb, KINETIS_IRQ_CAN0MB) /* Vector 45: CAN0 OR'ed Message buffer (0-15) */ +VECTOR(kinetis_can0bo, KINETIS_IRQ_CAN0BO) /* Vector 46: CAN0 Bus Off */ +VECTOR(kinetis_can0err, KINETIS_IRQ_CAN0ERR) /* Vector 47: CAN0 Error */ +VECTOR(kinetis_can0tw, KINETIS_IRQ_CAN0TW) /* Vector 48: CAN0 Transmit Warning */ +VECTOR(kinetis_can0rw, KINETIS_IRQ_CAN0RW) /* Vector 49: CAN0 Receive Warning */ +VECTOR(kinetis_can0wu, KINETIS_IRQ_CAN0WU) /* Vector 50: CAN0 Wake UP */ +UNUSED(KINETIS_IRQ_RESVD35) /* Vector 51: Reserved */ +UNUSED(KINETIS_IRQ_RESVD36) /* Vector 52: Reserved */ +VECTOR(kinetis_can1mb, KINETIS_IRQ_CAN1MB) /* Vector 53: CAN1 OR'ed Message buffer (0-15) */ +VECTOR(kinetis_can1bo, KINETIS_IRQ_CAN1BO) /* Vector 54: CAN1 Bus Off */ +VECTOR(kinetis_can1err, KINETIS_IRQ_CAN1ERR) /* Vector 55: CAN1 Error */ +VECTOR(kinetis_can1tw, KINETIS_IRQ_CAN1TW) /* Vector 56: CAN1 Transmit Warning */ +VECTOR(kinetis_can1rw, KINETIS_IRQ_CAN1RW) /* Vector 57: CAN1 Receive Warning */ +VECTOR(kinetis_can1wu, KINETIS_IRQ_CAN1WU) /* Vector 58: CAN1 Wake UP */ +UNUSED(KINETIS_IRQ_RESVD43) /* Vector 59: Reserved */ +UNUSED(KINETIS_IRQ_RESVD44) /* Vector 60: Reserved */ +VECTOR(kinetis_uart0s, KINETIS_IRQ_UART0S) /* Vector 61: UART0 status */ +VECTOR(kinetis_uart0e, KINETIS_IRQ_UART0E) /* Vector 62: UART0 error */ +VECTOR(kinetis_uart1s, KINETIS_IRQ_UART1S) /* Vector 63: UART1 status */ +VECTOR(kinetis_uart1e, KINETIS_IRQ_UART1E) /* Vector 64: UART1 error */ +VECTOR(kinetis_uart2s, KINETIS_IRQ_UART2S) /* Vector 65: UART2 status */ +VECTOR(kinetis_uart2e, KINETIS_IRQ_UART2E) /* Vector 66: UART2 error */ +VECTOR(kinetis_uart3s, KINETIS_IRQ_UART3S) /* Vector 67: UART3 status */ +VECTOR(kinetis_uart3e, KINETIS_IRQ_UART3E) /* Vector 68: UART3 error */ +VECTOR(kinetis_uart4s, KINETIS_IRQ_UART4S) /* Vector 69: UART4 status */ +VECTOR(kinetis_uart4e, KINETIS_IRQ_UART4E) /* Vector 70: UART4 error */ +VECTOR(kinetis_uart5s, KINETIS_IRQ_UART5S) /* Vector 71: UART5 status */ +VECTOR(kinetis_uart5e, KINETIS_IRQ_UART5E) /* Vector 72: UART5 error */ +VECTOR(kinetis_adc0, KINETIS_IRQ_ADC0) /* Vector 73: ADC0 */ +VECTOR(kinetis_adc1, KINETIS_IRQ_ADC1) /* Vector 74: ADC1 */ +VECTOR(kinetis_cmp0, KINETIS_IRQ_CMP0) /* Vector 75: CMP0 */ +VECTOR(kinetis_cmp1, KINETIS_IRQ_CMP1) /* Vector 76: CMP1 */ +VECTOR(kinetis_cmp2, KINETIS_IRQ_CMP2) /* Vector 77: CMP2 */ +VECTOR(kinetis_ftm0, KINETIS_IRQ_FTM0) /* Vector 78: FTM0 all sources */ +VECTOR(kinetis_ftm1, KINETIS_IRQ_FTM1) /* Vector 79: FTM1 all sources */ +VECTOR(kinetis_ftm2, KINETIS_IRQ_FTM2) /* Vector 80: FTM2 all sources */ +VECTOR(kinetis_cmt, KINETIS_IRQ_CMT) /* Vector 81: CMT */ +VECTOR(kinetis_rtc, KINETIS_IRQ_RTC) /* Vector 82: RTC alarm interrupt */ +UNUSED(KINETIS_IRQ_RESVD67) /* Vector 83: Reserved */ +VECTOR(kinetis_pitch0, KINETIS_IRQ_PITCH0) /* Vector 84: PIT channel 0 */ +VECTOR(kinetis_pitch1, KINETIS_IRQ_PITCH1) /* Vector 85: PIT channel 1 */ +VECTOR(kinetis_pitch2, KINETIS_IRQ_PITCH2) /* Vector 86: PIT channel 2 */ +VECTOR(kinetis_pitch3, KINETIS_IRQ_PITCH3) /* Vector 87: PIT channel 3 */ +VECTOR(kinetis_pdb, KINETIS_IRQ_PDB) /* Vector 88: PDB */ +VECTOR(kinetis_usbotg, KINETIS_IRQ_USBOTG) /* Vector 89: USB OTG */ +VECTOR(kinetis_usbcd, KINETIS_IRQ_USBCD) /* Vector 90: USB charger detect */ +UNUSED(KINETIS_IRQ_RESVD75) /* Vector 91: Reserved */ +UNUSED(KINETIS_IRQ_RESVD76) /* Vector 92: Reserved */ +UNUSED(KINETIS_IRQ_RESVD77) /* Vector 93: Reserved */ +UNUSED(KINETIS_IRQ_RESVD78) /* Vector 94: Reserved */ +VECTOR(kinetis_i2s0, KINETIS_IRQ_I2S0) /* Vector 95: I2S0 */ +VECTOR(kinetis_sdhc, KINETIS_IRQ_SDHC) /* Vector 96: SDHC */ +VECTOR(kinetis_dac0, KINETIS_IRQ_DAC0) /* Vector 97: DAC0 */ +VECTOR(kinetis_dac1, KINETIS_IRQ_DAC1) /* Vector 98: DAC1 */ +VECTOR(kinetis_tsi, KINETIS_IRQ_TSI) /* Vector 99: TSI all sources */ +VECTOR(kinetis_mcg, KINETIS_IRQ_MCG) /* Vector 100: MCG */ +VECTOR(kinetis_lpt, KINETIS_IRQ_LPT) /* Vector 101: Low power timer */ +VECTOR(kinetis_slcd, KINETIS_IRQ_SLCD) /* Vector 102: Segment LCD all sources */ +VECTOR(kinetis_porta, KINETIS_IRQ_PORTA) /* Vector 103: Pin detect port A */ +VECTOR(kinetis_portb, KINETIS_IRQ_PORTB) /* Vector 104: Pin detect port B */ +VECTOR(kinetis_portc, KINETIS_IRQ_PORTC) /* Vector 105: Pin detect port C */ +VECTOR(kinetis_portd, KINETIS_IRQ_PORTD) /* Vector 106: Pin detect port D */ +VECTOR(kinetis_porte, KINETIS_IRQ_PORTE) /* Vector 107: Pin detect port E */ +UNUSED(KINETIS_IRQ_RESVD92) /* Vector 108: Reserved */ +UNUSED(KINETIS_IRQ_RESVD93) /* Vector 109: Reserved */ +VECTOR(kinetis_swi, KINETIS_IRQ_SWI) /* Vector 110: Software interrupt */ +# endif /* CONFIG_ARMV7M_CMNVECTOR */ +#endif /* CONFIG_ARCH_FAMILY_K40 */ diff --git a/arch/arm/src/kinetis/chip/kinetis_k60vectors.h b/arch/arm/src/kinetis/chip/kinetis_k60vectors.h new file mode 100644 index 0000000000..e7b2cf7887 --- /dev/null +++ b/arch/arm/src/kinetis/chip/kinetis_k60vectors.h @@ -0,0 +1,156 @@ +/************************************************************************************ + * arch/arm/src/kinetis/chip/kinetis_k60vectors.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor definitions + ************************************************************************************/ +/* This file is included by kinetis_vectors.S. It provides the macro VECTOR that + * supplies ach K60 vector in terms of a (lower-case) ISR label and an + * (upper-case) IRQ number as defined in arch/arm/include/kinetis/kinetis_k60irq.h. + * kinetis_vectors.S will defined the VECTOR in different ways in order to generate + * the interrupt vectors and handlers in their final form. + */ + +#if defined(CONFIG_ARCH_FAMILY_K60) + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +# ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS NR_INTERRUPTS + +# else +VECTOR(kinetis_dmach0, KINETIS_IRQ_DMACH0) /* Vector 16: DMA channel 0 transfer complete */ +VECTOR(kinetis_dmach1, KINETIS_IRQ_DMACH1) /* Vector 17: DMA channel 1 transfer complete */ +VECTOR(kinetis_dmach2, KINETIS_IRQ_DMACH2) /* Vector 18: DMA channel 2 transfer complete */ +VECTOR(kinetis_dmach3, KINETIS_IRQ_DMACH3) /* Vector 19: DMA channel 3 transfer complete */ +VECTOR(kinetis_dmach4, KINETIS_IRQ_DMACH4) /* Vector 20: DMA channel 4 transfer complete */ +VECTOR(kinetis_dmach5, KINETIS_IRQ_DMACH5) /* Vector 21: DMA channel 5 transfer complete */ +VECTOR(kinetis_dmach6, KINETIS_IRQ_DMACH6) /* Vector 22: DMA channel 6 transfer complete */ +VECTOR(kinetis_dmach7, KINETIS_IRQ_DMACH7) /* Vector 23: DMA channel 7 transfer complete */ +VECTOR(kinetis_dmach8, KINETIS_IRQ_DMACH8) /* Vector 24: DMA channel 8 transfer complete */ +VECTOR(kinetis_dmach9, KINETIS_IRQ_DMACH9) /* Vector 25: DMA channel 9 transfer complete */ +VECTOR(kinetis_dmach10, KINETIS_IRQ_DMACH10) /* Vector 26: DMA channel 10 transfer complete */ +VECTOR(kinetis_dmach11, KINETIS_IRQ_DMACH11) /* Vector 27: DMA channel 11 transfer complete */ +VECTOR(kinetis_dmach12, KINETIS_IRQ_DMACH12) /* Vector 28: DMA channel 12 transfer complete */ +VECTOR(kinetis_dmach13, KINETIS_IRQ_DMACH13) /* Vector 29: DMA channel 13 transfer complete */ +VECTOR(kinetis_dmach14, KINETIS_IRQ_DMACH14) /* Vector 30: DMA channel 14 transfer complete */ +VECTOR(kinetis_dmach15, KINETIS_IRQ_DMACH15) /* Vector 31: DMA channel 15 transfer complete */ +VECTOR(kinetis_dmaerr, KINETIS_IRQ_DMAERR) /* Vector 32: DMA error interrupt channels 0-15 */ +VECTOR(kinetis_mcm, KINETIS_IRQ_MCM) /* Vector 33: MCM Normal interrupt */ +VECTOR(kinetis_flashcc, KINETIS_IRQ_FLASHCC) /* Vector 34: Flash memory command complete */ +VECTOR(kinetis_flashrc, KINETIS_IRQ_FLASHRC) /* Vector 35: Flash memory read collision */ +VECTOR(kinetis_smclvd, KINETIS_IRQ_SMCLVD) /* Vector 36: Mode Controller low-voltage detect, low-voltage warning */ +VECTOR(kinetis_llwu, KINETIS_IRQ_LLWU) /* Vector 37: LLWU Normal Low Leakage Wakeup */ +VECTOR(kinetis_wdog, KINETIS_IRQ_WDOG) /* Vector 38: Watchdog */ +VECTOR(kinetis_rngb, KINETIS_IRQ_RNGB) /* Vector 39: Random number generator */ +VECTOR(kinetis_i2c0, KINETIS_IRQ_I2C0) /* Vector 40: I2C0 */ +VECTOR(kinetis_i2c1, KINETIS_IRQ_I2C1) /* Vector 41: I2C1 */ +VECTOR(kinetis_spi0, KINETIS_IRQ_SPI0) /* Vector 42: SPI0 all sources */ +VECTOR(kinetis_spi1, KINETIS_IRQ_SPI1) /* Vector 43: SPI1 all sources */ +VECTOR(kinetis_spi2, KINETIS_IRQ_SPI2) /* Vector 44: SPI2 all sources */ +VECTOR(kinetis_can0mb, KINETIS_IRQ_CAN0MB) /* Vector 45: CAN0 OR'ed Message buffer (0-15) */ +VECTOR(kinetis_can0bo, KINETIS_IRQ_CAN0BO) /* Vector 46: CAN0 Bus Off */ +VECTOR(kinetis_can0err, KINETIS_IRQ_CAN0ERR) /* Vector 47: CAN0 Error */ +VECTOR(kinetis_can0tw, KINETIS_IRQ_CAN0TW) /* Vector 48: CAN0 Transmit Warning */ +VECTOR(kinetis_can0rw, KINETIS_IRQ_CAN0RW) /* Vector 49: CAN0 Receive Warning */ +VECTOR(kinetis_can0wu, KINETIS_IRQ_CAN0WU) /* Vector 50: CAN0 Wake UP */ +UNUSED(KINETIS_IRQ_RESVD35) /* Vector 51: Reserved */ +UNUSED(KINETIS_IRQ_RESVD36) /* Vector 52: Reserved */ +VECTOR(kinetis_can1mb, KINETIS_IRQ_CAN1MB) /* Vector 53: CAN1 OR'ed Message buffer (0-15) */ +VECTOR(kinetis_can1bo, KINETIS_IRQ_CAN1BO) /* Vector 54: CAN1 Bus Off */ +VECTOR(kinetis_can1err, KINETIS_IRQ_CAN1ERR) /* Vector 55: CAN1 Error */ +VECTOR(kinetis_can1tw, KINETIS_IRQ_CAN1TW) /* Vector 56: CAN1 Transmit Warning */ +VECTOR(kinetis_can1rw, KINETIS_IRQ_CAN1RW) /* Vector 57: CAN1 Receive Warning */ +VECTOR(kinetis_can1wu, KINETIS_IRQ_CAN1WU) /* Vector 58: CAN1 Wake UP */ +UNUSED(KINETIS_IRQ_RESVD43) /* Vector 59: Reserved */ +UNUSED(KINETIS_IRQ_RESVD44) /* Vector 60: Reserved */ +VECTOR(kinetis_uart0s, KINETIS_IRQ_UART0S) /* Vector 61: UART0 status */ +VECTOR(kinetis_uart0e, KINETIS_IRQ_UART0E) /* Vector 62: UART0 error */ +VECTOR(kinetis_uart1s, KINETIS_IRQ_UART1S) /* Vector 63: UART1 status */ +VECTOR(kinetis_uart1e, KINETIS_IRQ_UART1E) /* Vector 64: UART1 error */ +VECTOR(kinetis_uart2s, KINETIS_IRQ_UART2S) /* Vector 65: UART2 status */ +VECTOR(kinetis_uart2e, KINETIS_IRQ_UART2E) /* Vector 66: UART2 error */ +VECTOR(kinetis_uart3s, KINETIS_IRQ_UART3S) /* Vector 67: UART3 status */ +VECTOR(kinetis_uart3e, KINETIS_IRQ_UART3E) /* Vector 68: UART3 error */ +VECTOR(kinetis_uart4s, KINETIS_IRQ_UART4S) /* Vector 69: UART4 status */ +VECTOR(kinetis_uart4e, KINETIS_IRQ_UART4E) /* Vector 70: UART4 error */ +VECTOR(kinetis_uart5s, KINETIS_IRQ_UART5S) /* Vector 71: UART5 status */ +VECTOR(kinetis_uart5e, KINETIS_IRQ_UART5E) /* Vector 72: UART5 error */ +VECTOR(kinetis_adc0, KINETIS_IRQ_ADC0) /* Vector 73: ADC0 */ +VECTOR(kinetis_adc1, KINETIS_IRQ_ADC1) /* Vector 74: ADC1 */ +VECTOR(kinetis_cmp0, KINETIS_IRQ_CMP0) /* Vector 75: CMP0 */ +VECTOR(kinetis_cmp1, KINETIS_IRQ_CMP1) /* Vector 76: CMP1 */ +VECTOR(kinetis_cmp2, KINETIS_IRQ_CMP2) /* Vector 77: CMP2 */ +VECTOR(kinetis_ftm0, KINETIS_IRQ_FTM0) /* Vector 78: FTM0 all sources */ +VECTOR(kinetis_ftm1, KINETIS_IRQ_FTM1) /* Vector 79: FTM1 all sources */ +VECTOR(kinetis_ftm2, KINETIS_IRQ_FTM2) /* Vector 80: FTM2 all sources */ +VECTOR(kinetis_cmt, KINETIS_IRQ_CMT) /* Vector 81: CMT */ +VECTOR(kinetis_rtc, KINETIS_IRQ_RTC) /* Vector 82: RTC alarm interrupt */ +UNUSED(KINETIS_IRQ_RESVD67) /* Vector 83: Reserved */ +VECTOR(kinetis_pitch0, KINETIS_IRQ_PITCH0) /* Vector 84: PIT channel 0 */ +VECTOR(kinetis_pitch1, KINETIS_IRQ_PITCH1) /* Vector 85: PIT channel 1 */ +VECTOR(kinetis_pitch2, KINETIS_IRQ_PITCH2) /* Vector 86: PIT channel 2 */ +VECTOR(kinetis_pitch3, KINETIS_IRQ_PITCH3) /* Vector 87: PIT channel 3 */ +VECTOR(kinetis_pdb, KINETIS_IRQ_PDB) /* Vector 88: PDB */ +VECTOR(kinetis_usbotg, KINETIS_IRQ_USBOTG) /* Vector 89: USB OTG */ +VECTOR(kinetis_usbcd, KINETIS_IRQ_USBCD) /* Vector 90: USB charger detect */ +VECTOR(kinetis_emactmr, KINETIS_IRQ_EMACTMR) /* Vector 91: Ethernet MAC IEEE 1588 timer interrupt */ +VECTOR(kinetis_emactx, KINETIS_IRQ_EMACTX) /* Vector 92: Ethernet MAC transmit interrupt */ +VECTOR(kinetis_emacrx, KINETIS_IRQ_EMACRX) /* Vector 93: Ethernet MAC receive interrupt */ +VECTOR(kinetis_emacmisc, KINETIS_IRQ_EMACMISC) /* Vector 94: Ethernet MAC error and misc interrupt */ +VECTOR(kinetis_i2s0, KINETIS_IRQ_I2S0) /* Vector 95: I2S0 */ +VECTOR(kinetis_sdhc, KINETIS_IRQ_SDHC) /* Vector 96: SDHC */ +VECTOR(kinetis_dac0, KINETIS_IRQ_DAC0) /* Vector 97: DAC0 */ +VECTOR(kinetis_dac1, KINETIS_IRQ_DAC1) /* Vector 98: DAC1 */ +VECTOR(kinetis_tsi, KINETIS_IRQ_TSI) /* Vector 99: TSI all sources */ +VECTOR(kinetis_mcg, KINETIS_IRQ_MCG) /* Vector 100: MCG */ +VECTOR(kinetis_lpt, KINETIS_IRQ_LPT) /* Vector 101: Low power timer */ +UNUSED(KINETIS_IRQ_RESVD86) /* Vector 102: Reserved */ +VECTOR(kinetis_porta, KINETIS_IRQ_PORTA) /* Vector 103: Pin detect port A */ +VECTOR(kinetis_portb, KINETIS_IRQ_PORTB) /* Vector 104: Pin detect port B */ +VECTOR(kinetis_portc, KINETIS_IRQ_PORTC) /* Vector 105: Pin detect port C */ +VECTOR(kinetis_portd, KINETIS_IRQ_PORTD) /* Vector 106: Pin detect port D */ +VECTOR(kinetis_porte, KINETIS_IRQ_PORTE) /* Vector 107: Pin detect port E */ +UNUSED(KINETIS_IRQ_RESVD92) /* Vector 108: Reserved */ +UNUSED(KINETIS_IRQ_RESVD93) /* Vector 109: Reserved */ +VECTOR(kinetis_swi, KINETIS_IRQ_SWI) /* Vector 110: Software interrupt */ +# endif /* CONFIG_ARMV7M_CMNVECTOR */ +#endif /* CONFIG_ARCH_FAMILY_K60 */ diff --git a/arch/arm/src/kinetis/chip/kinetis_k64vectors.h b/arch/arm/src/kinetis/chip/kinetis_k64vectors.h new file mode 100644 index 0000000000..e010253a7f --- /dev/null +++ b/arch/arm/src/kinetis/chip/kinetis_k64vectors.h @@ -0,0 +1,147 @@ +/************************************************************************************ + * arch/arm/src/kinetis/chip/kinetis_k64vectors.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor definitions + ************************************************************************************/ +/* This file is included by kinetis_vectors.S. It provides the macro VECTOR that + * supplies ach K64 vector in terms of a (lower-case) ISR label and an + * (upper-case) IRQ number as defined in arch/arm/include/kinetis/kinetis_k64irq.h. + * kinetis_vectors.S will defined the VECTOR in different ways in order to generate + * the interrupt vectors and handlers in their final form. + */ + +#if defined(CONFIG_ARCH_FAMILY_K64) + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +# ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS NR_INTERRUPTS + +# else +VECTOR(kinetis_dmach0, KINETIS_IRQ_DMACH0) /* Vector 16: DMA channel 0 transfer complete */ +VECTOR(kinetis_dmach1, KINETIS_IRQ_DMACH1) /* Vector 17: DMA channel 1 transfer complete */ +VECTOR(kinetis_dmach2, KINETIS_IRQ_DMACH2) /* Vector 18: DMA channel 2 transfer complete */ +VECTOR(kinetis_dmach3, KINETIS_IRQ_DMACH3) /* Vector 19: DMA channel 3 transfer complete */ +VECTOR(kinetis_dmach4, KINETIS_IRQ_DMACH4) /* Vector 20: DMA channel 4 transfer complete */ +VECTOR(kinetis_dmach5, KINETIS_IRQ_DMACH5) /* Vector 21: DMA channel 5 transfer complete */ +VECTOR(kinetis_dmach6, KINETIS_IRQ_DMACH6) /* Vector 22: DMA channel 6 transfer complete */ +VECTOR(kinetis_dmach7, KINETIS_IRQ_DMACH7) /* Vector 23: DMA channel 7 transfer complete */ +VECTOR(kinetis_dmach8, KINETIS_IRQ_DMACH8) /* Vector 24: DMA channel 8 transfer complete */ +VECTOR(kinetis_dmach9, KINETIS_IRQ_DMACH9) /* Vector 25: DMA channel 9 transfer complete */ +VECTOR(kinetis_dmach10, KINETIS_IRQ_DMACH10) /* Vector 26: DMA channel 10 transfer complete */ +VECTOR(kinetis_dmach11, KINETIS_IRQ_DMACH11) /* Vector 27: DMA channel 11 transfer complete */ +VECTOR(kinetis_dmach12, KINETIS_IRQ_DMACH12) /* Vector 28: DMA channel 12 transfer complete */ +VECTOR(kinetis_dmach13, KINETIS_IRQ_DMACH13) /* Vector 29: DMA channel 13 transfer complete */ +VECTOR(kinetis_dmach14, KINETIS_IRQ_DMACH14) /* Vector 30: DMA channel 14 transfer complete */ +VECTOR(kinetis_dmach15, KINETIS_IRQ_DMACH15) /* Vector 31: DMA channel 15 transfer complete */ +VECTOR(kinetis_dmaerr, KINETIS_IRQ_DMAERR) /* Vector 32: DMA error interrupt channels 0-15 */ +VECTOR(kinetis_mcm, KINETIS_IRQ_MCM) /* Vector 33: MCM Normal interrupt */ +VECTOR(kinetis_flashcc, KINETIS_IRQ_FLASHCC) /* Vector 34: Flash memory command complete */ +VECTOR(kinetis_flashrc, KINETIS_IRQ_FLASHRC) /* Vector 35: Flash memory read collision */ +VECTOR(kinetis_smclvd, KINETIS_IRQ_SMCLVD) /* Vector 36: Mode Controller low-voltage detect, low-voltage warning */ +VECTOR(kinetis_llwu, KINETIS_IRQ_LLWU) /* Vector 37: LLWU Normal Low Leakage Wakeup */ +VECTOR(kinetis_wdog, KINETIS_IRQ_WDOG) /* Vector 38: Watchdog */ +VECTOR(kinetis_rngb, KINETIS_IRQ_RNGB) /* Vector 39: Random number generator */ +VECTOR(kinetis_i2c0, KINETIS_IRQ_I2C0) /* Vector 40: I2C0 */ +VECTOR(kinetis_i2c1, KINETIS_IRQ_I2C1) /* Vector 41: I2C1 */ +VECTOR(kinetis_spi0, KINETIS_IRQ_SPI0) /* Vector 42: SPI0 all sources */ +VECTOR(kinetis_spi1, KINETIS_IRQ_SPI1) /* Vector 43: SPI1 all sources */ +VECTOR(kinetis_i2s0, KINETIS_IRQ_I2S0) /* Vector 44: Transmit */ +VECTOR(kinetis_i2s1, KINETIS_IRQ_I2S1) /* Vector 45: Transmit */ +UNUSED(KINETIS_IRQ_RESVD30) /* Vector 46: Reserved */ +VECTOR(kinetis_uart0s, KINETIS_IRQ_UART0S) /* Vector 47: UART0 status */ +VECTOR(kinetis_uart0e, KINETIS_IRQ_UART0E) /* Vector 48: UART0 error */ +VECTOR(kinetis_uart1s, KINETIS_IRQ_UART1S) /* Vector 49: UART1 status */ +VECTOR(kinetis_uart1e, KINETIS_IRQ_UART1E) /* Vector 50: UART1 error */ +VECTOR(kinetis_uart2s, KINETIS_IRQ_UART2S) /* Vector 51: UART2 status */ +VECTOR(kinetis_uart2e, KINETIS_IRQ_UART2E) /* Vector 52: UART2 error */ +VECTOR(kinetis_uart3s, KINETIS_IRQ_UART3S) /* Vector 53: UART3 status */ +VECTOR(kinetis_uart3e, KINETIS_IRQ_UART3E) /* Vector 54: UART3 error */ +VECTOR(kinetis_adc0, KINETIS_IRQ_ADC0) /* Vector 55: ADC0 */ +VECTOR(kinetis_cmp0, KINETIS_IRQ_CMP0) /* Vector 56: CMP0 */ +VECTOR(kinetis_cmp1, KINETIS_IRQ_CMP1) /* Vector 57: CMP1 */ +VECTOR(kinetis_ftm0, KINETIS_IRQ_FTM0) /* Vector 58: FTM0 all sources */ +VECTOR(kinetis_ftm1, KINETIS_IRQ_FTM1) /* Vector 59: FTM1 all sources */ +VECTOR(kinetis_ftm2, KINETIS_IRQ_FTM2) /* Vector 60: FTM2 all sources */ +VECTOR(kinetis_cmt, KINETIS_IRQ_CMT) /* Vector 61: CMT */ +VECTOR(kinetis_rtc0, KINETIS_IRQ_RTC) /* Vector 62: RTC alarm interrupt */ +VECTOR(kinetis_rtc1, KINETIS_IRQ_RTCS) /* Vector 63: RTC seconds interrupt */ +VECTOR(kinetis_pitch0, KINETIS_IRQ_PITCH0) /* Vector 64: PIT channel 0 */ +VECTOR(kinetis_pitch1, KINETIS_IRQ_PITCH1) /* Vector 65: PIT channel 1 */ +VECTOR(kinetis_pitch2, KINETIS_IRQ_PITCH2) /* Vector 66: PIT channel 2 */ +VECTOR(kinetis_pitch3, KINETIS_IRQ_PITCH3) /* Vector 67: PIT channel 3 */ +VECTOR(kinetis_pdb, KINETIS_IRQ_PDB) /* Vector 68: PDB */ +VECTOR(kinetis_usbotg, KINETIS_IRQ_USBOTG) /* Vector 69: USB OTG */ +VECTOR(kinetis_usbcd, KINETIS_IRQ_USBCD) /* Vector 70: USB charger detect */ +UNUSED(KINETIS_IRQ_RESVD55) /* Vector 71: Reserved */ +VECTOR(kinetis_dac0, KINETIS_IRQ_DAC0) /* Vector 72: DAC0 */ +VECTOR(kinetis_mcg, KINETIS_IRQ_MCG) /* Vector 73: MCG */ +VECTOR(kinetis_lpt, KINETIS_IRQ_LPT) /* Vector 74: Low power timer */ +VECTOR(kinetis_porta, KINETIS_IRQ_PORTA) /* Vector 75: Pin detect port A */ +VECTOR(kinetis_portb, KINETIS_IRQ_PORTB) /* Vector 76: Pin detect port B */ +VECTOR(kinetis_portc, KINETIS_IRQ_PORTC) /* Vector 77: Pin detect port C */ +VECTOR(kinetis_portd, KINETIS_IRQ_PORTD) /* Vector 78: Pin detect port D */ +VECTOR(kinetis_porte, KINETIS_IRQ_PORTE) /* Vector 79: Pin detect port E */ +VECTOR(kinetis_software, KINETIS_IRQ_SWI) /* Vector 80: Software interrupt */ +VECTOR(kinetis_spi2, KINETIS_IRQ_SPI2) /* Vector 81: SPI2 all sources */ +VECTOR(kinetis_uart4s, KINETIS_IRQ_UART4S) /* Vector 82: UART4 status */ +VECTOR(kinetis_uart4e, KINETIS_IRQ_UART4E) /* Vector 83: UART4 error */ +VECTOR(kinetis_uart5s, KINETIS_IRQ_UART5S) /* Vector 84: UART5 status */ +VECTOR(kinetis_uart5e, KINETIS_IRQ_UART5E) /* Vector 85: UART5 error */ +VECTOR(kinetis_cmp2, KINETIS_IRQ_CMP2) /* Vector 86: CMP2 */ +VECTOR(kinetis_ftm3, KINETIS_IRQ_FTM3) /* Vector 87: FTM3 all sources */ +VECTOR(kinetis_dac1, KINETIS_IRQ_DAC1) /* Vector 88: DAC1 */ +VECTOR(kinetis_adc1, KINETIS_IRQ_ADC1) /* Vector 89: ADC1 */ +VECTOR(kinetis_i2c2, KINETIS_IRQ_I2C2) /* Vector 90: I2C2 */ +VECTOR(kinetis_can0mb, KINETIS_IRQ_CAN0MB) /* Vector 91: CAN0 ORed Message buffer (0-15) */ +VECTOR(kinetis_can0bo, KINETIS_IRQ_CAN0BO) /* Vector 92: CAN0 Bus Off */ +VECTOR(kinetis_can0err, KINETIS_IRQ_CAN0ERR) /* Vector 93: CAN0 Error */ +VECTOR(kinetis_can0tw, KINETIS_IRQ_CAN0TW) /* Vector 94: CAN0 Transmit Warning */ +VECTOR(kinetis_can0rw, KINETIS_IRQ_CAN0RW) /* Vector 95: CAN0 Receive Warning */ +VECTOR(kinetis_can0wu, KINETIS_IRQ_CAN0WU) /* Vector 96: CAN0 Wake UP */ +VECTOR(kinetis_sdhc, KINETIS_IRQ_SDHC) /* Vector 97: SDHC */ +VECTOR(kinetis_emactmr, KINETIS_IRQ_EMACTMR) /* Vector 91: Ethernet MAC IEEE 1588 timer interrupt */ +VECTOR(kinetis_emactx, KINETIS_IRQ_EMACTX) /* Vector 92: Ethernet MAC transmit interrupt */ +VECTOR(kinetis_emacrx, KINETIS_IRQ_EMACRX) /* Vector 93: Ethernet MAC receive interrupt */ +VECTOR(kinetis_emacmisc, KINETIS_IRQ_EMACMISC) /* Vector 94: Ethernet MAC error and misc interrupt */ +# endif /* CONFIG_ARMV7M_CMNVECTOR */ +#endif /* CONFIG_ARCH_FAMILY_K64 */ diff --git a/arch/arm/src/kinetis/chip/kinetis_k66vectors.h b/arch/arm/src/kinetis/chip/kinetis_k66vectors.h new file mode 100644 index 0000000000..982320e07e --- /dev/null +++ b/arch/arm/src/kinetis/chip/kinetis_k66vectors.h @@ -0,0 +1,162 @@ +/************************************************************************************ + * arch/arm/src/kinetis/chip/kinetis_k64vectors.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Pre-processor definitions + ************************************************************************************/ +/* This file is included by kinetis_vectors.S. It provides the macro VECTOR that + * supplies ach K64 vector in terms of a (lower-case) ISR label and an + * (upper-case) IRQ number as defined in arch/arm/include/kinetis/kinetis_k64irq.h. + * kinetis_vectors.S will defined the VECTOR in different ways in order to generate + * the interrupt vectors and handlers in their final form. + */ + +#if defined(CONFIG_ARCH_FAMILY_K64) + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +# ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS NR_INTERRUPTS + +# else +VECTOR(kinetis_dmach0, KINETIS_IRQ_DMACH0) /* Vector 16: DMA channel 0 transfer complete */ +VECTOR(kinetis_dmach1, KINETIS_IRQ_DMACH1) /* Vector 17: DMA channel 1 transfer complete */ +VECTOR(kinetis_dmach2, KINETIS_IRQ_DMACH2) /* Vector 18: DMA channel 2 transfer complete */ +VECTOR(kinetis_dmach3, KINETIS_IRQ_DMACH3) /* Vector 19: DMA channel 3 transfer complete */ +VECTOR(kinetis_dmach4, KINETIS_IRQ_DMACH4) /* Vector 20: DMA channel 4 transfer complete */ +VECTOR(kinetis_dmach5, KINETIS_IRQ_DMACH5) /* Vector 21: DMA channel 5 transfer complete */ +VECTOR(kinetis_dmach6, KINETIS_IRQ_DMACH6) /* Vector 22: DMA channel 6 transfer complete */ +VECTOR(kinetis_dmach7, KINETIS_IRQ_DMACH7) /* Vector 23: DMA channel 7 transfer complete */ +VECTOR(kinetis_dmach8, KINETIS_IRQ_DMACH8) /* Vector 24: DMA channel 8 transfer complete */ +VECTOR(kinetis_dmach9, KINETIS_IRQ_DMACH9) /* Vector 25: DMA channel 9 transfer complete */ +VECTOR(kinetis_dmach10, KINETIS_IRQ_DMACH10) /* Vector 26: DMA channel 10 transfer complete */ +VECTOR(kinetis_dmach11, KINETIS_IRQ_DMACH11) /* Vector 27: DMA channel 11 transfer complete */ +VECTOR(kinetis_dmach12, KINETIS_IRQ_DMACH12) /* Vector 28: DMA channel 12 transfer complete */ +VECTOR(kinetis_dmach13, KINETIS_IRQ_DMACH13) /* Vector 29: DMA channel 13 transfer complete */ +VECTOR(kinetis_dmach14, KINETIS_IRQ_DMACH14) /* Vector 30: DMA channel 14 transfer complete */ +VECTOR(kinetis_dmach15, KINETIS_IRQ_DMACH15) /* Vector 31: DMA channel 15 transfer complete */ +VECTOR(kinetis_dmaerr, KINETIS_IRQ_DMAERR) /* Vector 32: DMA error interrupt channels 0-15 */ +VECTOR(kinetis_mcm, KINETIS_IRQ_MCM) /* Vector 33: MCM Normal interrupt */ +VECTOR(kinetis_flashcc, KINETIS_IRQ_FLASHCC) /* Vector 34: Flash memory command complete */ +VECTOR(kinetis_flashrc, KINETIS_IRQ_FLASHRC) /* Vector 35: Flash memory read collision */ +VECTOR(kinetis_smclvd, KINETIS_IRQ_SMCLVD) /* Vector 36: Mode Controller low-voltage detect, low-voltage warning */ +VECTOR(kinetis_llwu, KINETIS_IRQ_LLWU) /* Vector 37: LLWU Normal Low Leakage Wakeup */ +VECTOR(kinetis_wdog, KINETIS_IRQ_WDOG) /* Vector 38: Watchdog */ +VECTOR(kinetis_rngb, KINETIS_IRQ_RNGB) /* Vector 39: Random number generator */ +VECTOR(kinetis_i2c0, KINETIS_IRQ_I2C0) /* Vector 40: I2C0 */ +VECTOR(kinetis_i2c1, KINETIS_IRQ_I2C1) /* Vector 41: I2C1 */ +VECTOR(kinetis_spi0, KINETIS_IRQ_SPI0) /* Vector 42: SPI0 all sources */ +VECTOR(kinetis_spi1, KINETIS_IRQ_SPI1) /* Vector 43: SPI1 all sources */ +VECTOR(kinetis_i2s0, KINETIS_IRQ_I2S0) /* Vector 44: Transmit */ +VECTOR(kinetis_i2s1, KINETIS_IRQ_I2S1) /* Vector 45: Transmit */ +UNUSED(KINETIS_IRQ_RESVD30) /* Vector 46: Reserved */ +VECTOR(kinetis_uart0s, KINETIS_IRQ_UART0S) /* Vector 47: UART0 status */ +VECTOR(kinetis_uart0e, KINETIS_IRQ_UART0E) /* Vector 48: UART0 error */ +VECTOR(kinetis_uart1s, KINETIS_IRQ_UART1S) /* Vector 49: UART1 status */ +VECTOR(kinetis_uart1e, KINETIS_IRQ_UART1E) /* Vector 50: UART1 error */ +VECTOR(kinetis_uart2s, KINETIS_IRQ_UART2S) /* Vector 51: UART2 status */ +VECTOR(kinetis_uart2e, KINETIS_IRQ_UART2E) /* Vector 52: UART2 error */ +VECTOR(kinetis_uart3s, KINETIS_IRQ_UART3S) /* Vector 53: UART3 status */ +VECTOR(kinetis_uart3e, KINETIS_IRQ_UART3E) /* Vector 54: UART3 error */ +VECTOR(kinetis_adc0, KINETIS_IRQ_ADC0) /* Vector 55: ADC0 */ +VECTOR(kinetis_cmp0, KINETIS_IRQ_CMP0) /* Vector 56: CMP0 */ +VECTOR(kinetis_cmp1, KINETIS_IRQ_CMP1) /* Vector 57: CMP1 */ +VECTOR(kinetis_ftm0, KINETIS_IRQ_FTM0) /* Vector 58: FTM0 all sources */ +VECTOR(kinetis_ftm1, KINETIS_IRQ_FTM1) /* Vector 59: FTM1 all sources */ +VECTOR(kinetis_ftm2, KINETIS_IRQ_FTM2) /* Vector 60: FTM2 all sources */ +VECTOR(kinetis_cmt, KINETIS_IRQ_CMT) /* Vector 61: CMT */ +VECTOR(kinetis_rtc0, KINETIS_IRQ_RTC) /* Vector 62: RTC alarm interrupt */ +VECTOR(kinetis_rtc1, KINETIS_IRQ_RTCS) /* Vector 63: RTC seconds interrupt */ +VECTOR(kinetis_pitch0, KINETIS_IRQ_PITCH0) /* Vector 64: PIT channel 0 */ +VECTOR(kinetis_pitch1, KINETIS_IRQ_PITCH1) /* Vector 65: PIT channel 1 */ +VECTOR(kinetis_pitch2, KINETIS_IRQ_PITCH2) /* Vector 66: PIT channel 2 */ +VECTOR(kinetis_pitch3, KINETIS_IRQ_PITCH3) /* Vector 67: PIT channel 3 */ +VECTOR(kinetis_pdb, KINETIS_IRQ_PDB) /* Vector 68: PDB */ +VECTOR(kinetis_usbotg, KINETIS_IRQ_USBOTG) /* Vector 69: USB OTG */ +VECTOR(kinetis_usbcd, KINETIS_IRQ_USBCD) /* Vector 70: USB charger detect */ +UNUSED(KINETIS_IRQ_RESVD55) /* Vector 71: Reserved */ +VECTOR(kinetis_dac0, KINETIS_IRQ_DAC0) /* Vector 72: DAC0 */ +VECTOR(kinetis_mcg, KINETIS_IRQ_MCG) /* Vector 73: MCG */ +VECTOR(kinetis_lpt, KINETIS_IRQ_LPT) /* Vector 74: Low power timer */ +VECTOR(kinetis_porta, KINETIS_IRQ_PORTA) /* Vector 75: Pin detect port A */ +VECTOR(kinetis_portb, KINETIS_IRQ_PORTB) /* Vector 76: Pin detect port B */ +VECTOR(kinetis_portc, KINETIS_IRQ_PORTC) /* Vector 77: Pin detect port C */ +VECTOR(kinetis_portd, KINETIS_IRQ_PORTD) /* Vector 78: Pin detect port D */ +VECTOR(kinetis_porte, KINETIS_IRQ_PORTE) /* Vector 79: Pin detect port E */ +VECTOR(kinetis_software, KINETIS_IRQ_SWI) /* Vector 80: Software interrupt */ +VECTOR(kinetis_spi2, KINETIS_IRQ_SPI2) /* Vector 81: SPI2 all sources */ +VECTOR(kinetis_uart4s, KINETIS_IRQ_UART4S) /* Vector 82: UART4 status */ +VECTOR(kinetis_uart4e, KINETIS_IRQ_UART4E) /* Vector 83: UART4 error */ +UNUSED(KINETIS_IRQ_RESVD68) /* Vector 84: Reserved */ +UNUSED(KINETIS_IRQ_RESVD69) /* Vector 85: Reserved */ +VECTOR(kinetis_cmp2, KINETIS_IRQ_CMP2) /* Vector 86: CMP2 */ +VECTOR(kinetis_ftm3, KINETIS_IRQ_FTM3) /* Vector 87: FTM3 all sources */ +VECTOR(kinetis_dac1, KINETIS_IRQ_DAC1) /* Vector 88: DAC1 */ +VECTOR(kinetis_adc1, KINETIS_IRQ_ADC1) /* Vector 89: ADC1 */ +VECTOR(kinetis_i2c2, KINETIS_IRQ_I2C2) /* Vector 90: I2C2 */ +VECTOR(kinetis_can0mb, KINETIS_IRQ_CAN0MB) /* Vector 91: CAN0 ORed Message buffer (0-15) */ +VECTOR(kinetis_can0bo, KINETIS_IRQ_CAN0BO) /* Vector 92: CAN0 Bus Off */ +VECTOR(kinetis_can0err, KINETIS_IRQ_CAN0ERR) /* Vector 93: CAN0 Error */ +VECTOR(kinetis_can0tw, KINETIS_IRQ_CAN0TW) /* Vector 94: CAN0 Transmit Warning */ +VECTOR(kinetis_can0rw, KINETIS_IRQ_CAN0RW) /* Vector 95: CAN0 Receive Warning */ +VECTOR(kinetis_can0wu, KINETIS_IRQ_CAN0WU) /* Vector 96: CAN0 Wake UP */ +VECTOR(kinetis_sdhc, KINETIS_IRQ_SDHC) /* Vector 97: SDHC */ +VECTOR(kinetis_emactmr, KINETIS_IRQ_EMACTMR) /* Vector 98: Ethernet MAC IEEE 1588 timer interrupt */ +VECTOR(kinetis_emactx, KINETIS_IRQ_EMACTX) /* Vector 99: Ethernet MAC transmit interrupt */ +VECTOR(kinetis_emacrx, KINETIS_IRQ_EMACRX) /* Vector 100: Ethernet MAC receive interrupt */ +VECTOR(kinetis_emacmisc, KINETIS_IRQ_EMACMISC) /* Vector 101: Ethernet MAC error and misc interrupt */ +VECTOR(kinetis_lpuart0, KINETIS_IRQ_LPUART0) /* Vector 102: LPUART0 Status and error */ +VECTOR(kinetis_tsi0, KINETIS_IRQ_TSI0) /* Vector 103: TSI0 */ +VECTOR(kinetis_tpm1, KINETIS_IRQ_TPM1) /* Vector 104: TPM1 */ +VECTOR(kinetis_tpm2, KINETIS_IRQ_TPM2) /* Vector 105: TPM2 */ +VECTOR(kinetis_usbhsdcd,KINETIS_IRQ_USBHSDCD) /* Vector 106: shared by USBHS DCD & USBHS Phy modules */ +VECTOR(kinetis_i2c3, KINETIS_IRQ_I2C3) /* Vector 107: I2C3 */ +VECTOR(kinetis_cmp3, KINETIS_IRQ_CMP3) /* Vector 108: CMP3 */ +VECTOR(kinetis_usbhsotg,KINETIS_IRQ_USBHSOTG) /* Vector 109: USBHS OTG*/ +VECTOR(kinetis_can1mb, KINETIS_IRQ_CAN1MB) /* Vector 110: CAN1 OR'ed Message buffer (0-15) */ +VECTOR(kinetis_can1bo, KINETIS_IRQ_CAN1BO) /* Vector 111: CAN1 Bus Off */ +VECTOR(kinetis_can1err, KINETIS_IRQ_CAN1ERR ) /* Vector 112: CAN1 Error */ +VECTOR(kinetis_can1tw, KINETIS_IRQ_CAN1TW) /* Vector 113: CAN1 Transmit Warning */ +VECTOR(kinetis_can1rw, KINETIS_IRQ_CAN1RW) /* Vector 114: CAN1 Receive Warning */ +VECTOR(kinetis_can1wu, KINETIS_IRQ_CAN1WU) /* Vector 115: CAN1 Wake UP */ + +# endif /* CONFIG_ARMV7M_CMNVECTOR */ +#endif /* CONFIG_ARCH_FAMILY_K64 */ diff --git a/arch/arm/src/kinetis/kinetis_clrpend.c b/arch/arm/src/kinetis/kinetis_clrpend.c index 7f0395c4ae..faf35271d8 100644 --- a/arch/arm/src/kinetis/kinetis_clrpend.c +++ b/arch/arm/src/kinetis/kinetis_clrpend.c @@ -82,23 +82,23 @@ void kinetis_clrpend(int irq) { /* Check for external interrupt */ - if (irq >= KINETIS_IRQ_EXTINT) + if (irq >= KINETIS_IRQ_FIRST) { - if (irq < (KINETIS_IRQ_EXTINT+32)) + if (irq < (KINETIS_IRQ_FIRST+32)) { - putreg32(1 << (irq - KINETIS_IRQ_EXTINT), NVIC_IRQ0_31_CLRPEND); + putreg32(1 << (irq - KINETIS_IRQ_FIRST), NVIC_IRQ0_31_CLRPEND); } - else if (irq < (KINETIS_IRQ_EXTINT+64)) + else if (irq < (KINETIS_IRQ_FIRST+64)) { - putreg32(1 << (irq - KINETIS_IRQ_EXTINT - 32), NVIC_IRQ32_63_CLRPEND); + putreg32(1 << (irq - KINETIS_IRQ_FIRST - 32), NVIC_IRQ32_63_CLRPEND); } - else if (irq < (KINETIS_IRQ_EXTINT+96)) + else if (irq < (KINETIS_IRQ_FIRST+96)) { - putreg32(1 << (irq - KINETIS_IRQ_EXTINT - 64), NVIC_IRQ64_95_CLRPEND); + putreg32(1 << (irq - KINETIS_IRQ_FIRST - 64), NVIC_IRQ64_95_CLRPEND); } else if (irq < NR_IRQS) { - putreg32(1 << (irq - KINETIS_IRQ_EXTINT - 96), NVIC_IRQ96_127_CLRPEND); + putreg32(1 << (irq - KINETIS_IRQ_FIRST - 96), NVIC_IRQ96_127_CLRPEND); } } } diff --git a/arch/arm/src/kinetis/kinetis_irq.c b/arch/arm/src/kinetis/kinetis_irq.c index a969bbacd7..7830d8756e 100644 --- a/arch/arm/src/kinetis/kinetis_irq.c +++ b/arch/arm/src/kinetis/kinetis_irq.c @@ -258,27 +258,27 @@ static int kinetis_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, /* Check for external interrupt */ - if (irq >= KINETIS_IRQ_EXTINT) + if (irq >= KINETIS_IRQ_FIRST) { - if (irq < (KINETIS_IRQ_EXTINT+32)) + if (irq < (KINETIS_IRQ_FIRST+32)) { *regaddr = (NVIC_IRQ0_31_ENABLE + offset); - *bit = 1 << (irq - KINETIS_IRQ_EXTINT); + *bit = 1 << (irq - KINETIS_IRQ_FIRST); } - else if (irq < (KINETIS_IRQ_EXTINT+64)) + else if (irq < (KINETIS_IRQ_FIRST+64)) { *regaddr = (NVIC_IRQ32_63_ENABLE + offset); - *bit = 1 << (irq - KINETIS_IRQ_EXTINT - 32); + *bit = 1 << (irq - KINETIS_IRQ_FIRST - 32); } - else if (irq < (KINETIS_IRQ_EXTINT+96)) + else if (irq < (KINETIS_IRQ_FIRST+96)) { *regaddr = (NVIC_IRQ64_95_ENABLE + offset); - *bit = 1 << (irq - KINETIS_IRQ_EXTINT - 64); + *bit = 1 << (irq - KINETIS_IRQ_FIRST - 64); } else if (irq < NR_IRQS) { *regaddr = (NVIC_IRQ96_127_ENABLE + offset); - *bit = 1 << (irq - KINETIS_IRQ_EXTINT - 96); + *bit = 1 << (irq - KINETIS_IRQ_FIRST - 96); } else { @@ -472,7 +472,7 @@ void up_disable_irq(int irq) * clear the bit in the System Handler Control and State Register. */ - if (irq >= KINETIS_IRQ_EXTINT) + if (irq >= KINETIS_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -509,7 +509,7 @@ void up_enable_irq(int irq) * set the bit in the System Handler Control and State Register. */ - if (irq >= KINETIS_IRQ_EXTINT) + if (irq >= KINETIS_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -560,7 +560,7 @@ int up_prioritize_irq(int irq, int priority) DEBUGASSERT(irq >= KINETIS_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - if (irq < KINETIS_IRQ_EXTINT) + if (irq < KINETIS_IRQ_FIRST) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) @@ -573,7 +573,7 @@ int up_prioritize_irq(int irq, int priority) { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ - irq -= KINETIS_IRQ_EXTINT; + irq -= KINETIS_IRQ_FIRST; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/arch/arm/src/kinetis/kinetis_vectors.S b/arch/arm/src/kinetis/kinetis_vectors.S index 39f07fc000..48c74c7059 100644 --- a/arch/arm/src/kinetis/kinetis_vectors.S +++ b/arch/arm/src/kinetis/kinetis_vectors.S @@ -1,9 +1,9 @@ -/************************************************************************************************ +/***************************************************************************** * arch/arm/src/kinetis/kinetis_vectors.S - * arch/arm/src/chip/kinetis_vectors.S * - * Copyright (C) 2011, 2013-2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2011, 2013-2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -32,11 +32,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************************/ + ****************************************************************************/ -/************************************************************************************************ +/***************************************************************************** * Included Files - ************************************************************************************************/ + ****************************************************************************/ #include @@ -45,23 +45,25 @@ #include "chip.h" #include "exc_return.h" -/************************************************************************************************ +/***************************************************************************** * Pre-processor Definitions - ************************************************************************************************/ -/* Configuration ********************************************************************************/ + ****************************************************************************/ +/* Configuration ************************************************************/ #ifdef CONFIG_ARCH_HIPRI_INTERRUPT - /* In kernel mode without an interrupt stack, this interrupt handler will set the MSP to the - * stack pointer of the interrupted thread. If the interrupted thread was a privileged - * thread, that will be the MSP otherwise it will be the PSP. If the PSP is used, then the - * value of the MSP will be invalid when the interrupt handler returns because it will be a - * pointer to an old position in the unprivileged stack. Then when the high priority - * interrupt occurs and uses this stale MSP, there will most likely be a system failure. + /* In kernel mode without an interrupt stack, this interrupt handler will set the + * MSP to the stack pointer of the interrupted thread. If the interrupted thread + * was a privileged thread, that will be the MSP otherwise it will be the PSP. If + * the PSP is used, then the value of the MSP will be invalid when the interrupt + * handler returns because it will be a pointer to an old position in the + * unprivileged stack. Then when the high priority interrupt occurs and uses this + * stale MSP, there will most likely be a system failure. * - * If the interrupt stack is selected, on the other hand, then the interrupt handler will - * always set the the MSP to the interrupt stack. So when the high priority interrupt occurs, - * it will either use the MSP of the last privileged thread to run or, in the case of the - * nested interrupt, the interrupt stack if no privileged task has run. + * If the interrupt stack is selected, on the other hand, then the interrupt + * handler will always set the the MSP to the interrupt stack. So when the high + * priority interrupt occurs, it will either use the MSP of the last privileged + * thread to run or, in the case of the nested interrupt, the interrupt stack if + * no privileged task has run. */ # if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 4 @@ -77,7 +79,7 @@ # endif #endif -/* Memory Map ***********************************************************************************/ +/* Memory Map ***********************************************************************/ /* * 0x0000:0000 - Beginning of FLASH. Address of vectors * 0x1800:0000 - Start of CPU SRAM and start of .data (_sdata) @@ -92,9 +94,9 @@ #define IDLE_STACK (_ebss+CONFIG_IDLETHREAD_STACKSIZE-4) #define HEAP_BASE (_ebss+CONFIG_IDLETHREAD_STACKSIZE) -/************************************************************************************************ +/************************************************************************************ * Public Symbols - ************************************************************************************************/ + ************************************************************************************/ .syntax unified .thumb @@ -106,9 +108,9 @@ .globl __start -/************************************************************************************************ +/************************************************************************************ * Macros - ************************************************************************************************/ + ************************************************************************************/ /* On entry into an IRQ, the hardware automatically saves the xPSR, PC, LR, R12, R0-R3 * registers on the stack, then branches to an instantantiation of the following @@ -123,9 +125,9 @@ b exception_common .endm -/************************************************************************************************ +/************************************************************************************ * Vectors - ************************************************************************************************/ + ************************************************************************************/ .section .vectors, "ax" .code 16 @@ -135,7 +137,7 @@ _vectors: -/* Processor Exceptions *************************************************************************/ +/* Processor Exceptions */ .word IDLE_STACK /* Vector 0: Reset stack pointer */ .word __start /* Vector 1: Reset vector */ @@ -154,437 +156,38 @@ _vectors: .word kinetis_pendsv /* Vector 14: Pendable system service request */ .word kinetis_systick /* Vector 15: System tick */ -/* External Interrupts **************************************************************************/ -/* K20 Family *********************************************************************************** - * - * The interrupt vectors for the following parts is defined in Freescale document - * K20P64M72SF1RM - */ - -#if defined(KINETIS_K20) - .word kinetis_dmach0 /* Vector 16: DMA channel 0 transfer complete */ - .word kinetis_dmach1 /* Vector 17: DMA channel 1 transfer complete */ - .word kinetis_dmach2 /* Vector 18: DMA channel 2 transfer complete */ - .word kinetis_dmach3 /* Vector 19: DMA channel 3 transfer complete */ - .word kinetis_dmach4 /* Vector 20: DMA channel 4 transfer complete */ - .word kinetis_dmach5 /* Vector 21: DMA channel 5 transfer complete */ - .word kinetis_dmach6 /* Vector 22: DMA channel 6 transfer complete */ - .word kinetis_dmach7 /* Vector 23: DMA channel 7 transfer complete */ - .word kinetis_dmach8 /* Vector 24: DMA channel 8 transfer complete */ - .word kinetis_dmach9 /* Vector 25: DMA channel 9 transfer complete */ - .word kinetis_dmach10 /* Vector 26: DMA channel 10 transfer complete */ - .word kinetis_dmach11 /* Vector 27: DMA channel 11 transfer complete */ - .word kinetis_dmach12 /* Vector 28: DMA channel 12 transfer complete */ - .word kinetis_dmach13 /* Vector 29: DMA channel 13 transfer complete */ - .word kinetis_dmach14 /* Vector 30: DMA channel 14 transfer complete */ - .word kinetis_dmach15 /* Vector 31: DMA channel 15 transfer complete */ - .word kinetis_dmaerr /* Vector 32: DMA error interrupt channels 0-15 */ - .word kinetis_reserved /* Vector 33: Reserved */ - .word kinetis_flashcc /* Vector 34: Flash memory command complete */ - .word kinetis_flashrc /* Vector 35: Flash memory read collision */ - .word kinetis_smclvd /* Vector 36: Mode Controller low-voltage detect, low-voltage warning */ - .word kinetis_llwu /* Vector 37: LLWU Normal Low Leakage Wakeup */ - .word kinetis_wdog /* Vector 38: Watchdog */ - .word kinetis_reserved /* Vector 39: Reserved */ - .word kinetis_i2c0 /* Vector 40: I2C0 */ - .word kinetis_i2c1 /* Vector 41: I2C1 */ - .word kinetis_spi0 /* Vector 42: SPI0 all sources */ - .word kinetis_spi1 /* Vector 43: SPI1 all sources */ - .word kinetis_reserved /* Vector 44: Reserved */ - .word kinetis_can0mb /* Vector 45: CAN0 OR'ed Message buffer (0-15) */ - .word kinetis_can0bo /* Vector 46: CAN0 Bus Off */ - .word kinetis_can0err /* Vector 47: CAN0 Error */ - .word kinetis_can0tw /* Vector 48: CAN0 Transmit Warning */ - .word kinetis_can0rw /* Vector 49: CAN0 Receive Warning */ - .word kinetis_can0wu /* Vector 50: CAN0 Wake UP */ - .word kinetis_reserved /* Vector 51: Reserved */ - .word kinetis_reserved /* Vector 52: Reserved */ - .word kinetis_reserved /* Vector 53: Reserved */ - .word kinetis_reserved /* Vector 54: Reserved */ - .word kinetis_reserved /* Vector 55: Reserved */ - .word kinetis_reserved /* Vector 56: Reserved */ - .word kinetis_reserved /* Vector 57: Reserved */ - .word kinetis_reserved /* Vector 58: Reserved */ - .word kinetis_reserved /* Vector 59: Reserved */ - .word kinetis_reserved /* Vector 60: Reserved */ - .word kinetis_uart0s /* Vector 61: UART0 status */ - .word kinetis_uart0e /* Vector 62: UART0 error */ - .word kinetis_uart1s /* Vector 63: UART1 status */ - .word kinetis_uart1e /* Vector 64: UART1 error */ - .word kinetis_uart2s /* Vector 65: UART2 status */ - .word kinetis_uart2e /* Vector 66: UART2 error */ - .word kinetis_reserved /* Vector 67: Reserved */ - .word kinetis_reserved /* Vector 68: Reserved */ - .word kinetis_reserved /* Vector 69: Reserved */ - .word kinetis_reserved /* Vector 70: Reserved */ - .word kinetis_reserved /* Vector 71: Reserved */ - .word kinetis_reserved /* Vector 72: Reserved */ - .word kinetis_adc0 /* Vector 73: ADC0 */ - .word kinetis_adc1 /* Vector 74: ADC1 */ - .word kinetis_cmp0 /* Vector 75: CMP0 */ - .word kinetis_cmp1 /* Vector 76: CMP1 */ - .word kinetis_cmp2 /* Vector 77: CMP2 */ - .word kinetis_ftm0 /* Vector 78: FTM0 all sources */ - .word kinetis_ftm1 /* Vector 79: FTM1 all sources */ - .word kinetis_ftm2 /* Vector 80: FTM2 all sources */ - .word kinetis_cmt /* Vector 81: CMT */ - .word kinetis_rtc /* Vector 82: RTC alarm interrupt */ - .word kinetis_reserved /* Vector 83: Reserved */ - .word kinetis_pitch0 /* Vector 84: PIT channel 0 */ - .word kinetis_pitch1 /* Vector 85: PIT channel 1 */ - .word kinetis_pitch2 /* Vector 86: PIT channel 2 */ - .word kinetis_pitch3 /* Vector 87: PIT channel 3 */ - .word kinetis_pdb /* Vector 88: PDB */ - .word kinetis_usbotg /* Vector 88: USB OTG */ - .word kinetis_usbcd /* Vector 90: USB charger detect */ - .word kinetis_reserved /* Vector 91: Reserved */ - .word kinetis_reserved /* Vector 92: Reserved */ - .word kinetis_reserved /* Vector 93: Reserved */ - .word kinetis_reserved /* Vector 94: Reserved */ - .word kinetis_reserved /* Vector 95: Reserved */ - .word kinetis_reserved /* Vector 96: Reserved */ - .word kinetis_dac0 /* Vector 97: DAC0 */ - .word kinetis_reserved /* Vector 98: Reserved */ - .word kinetis_tsi /* Vector 99: TSI all sources */ - .word kinetis_mcg /* Vector 100: MCG */ - .word kinetis_lpt /* Vector 101: Low power timer */ - .word kinetis_reserved /* Vector 102: Reserved */ - .word kinetis_porta /* Vector 103: Pin detect port A */ - .word kinetis_portb /* Vector 104: Pin detect port B */ - .word kinetis_portc /* Vector 105: Pin detect port C */ - .word kinetis_portd /* Vector 106: Pin detect port D */ - .word kinetis_porte /* Vector 107: Pin detect port E */ - .word kinetis_reserved /* Vector 108: Reserved */ - .word kinetis_reserved /* Vector 109: Reserved */ - .word kinetis_swi /* Vector 110: Software interrupt */ - -/* K40 Family *********************************************************************************** - * - * The interrupt vectors for the following parts is defined in Freescale document - * K40P144M100SF2RM - */ - -#elif defined(KINETIS_K40) - - .word kinetis_dmach0 /* Vector 16: DMA channel 0 transfer complete */ - .word kinetis_dmach1 /* Vector 17: DMA channel 1 transfer complete */ - .word kinetis_dmach2 /* Vector 18: DMA channel 2 transfer complete */ - .word kinetis_dmach3 /* Vector 19: DMA channel 3 transfer complete */ - .word kinetis_dmach4 /* Vector 20: DMA channel 4 transfer complete */ - .word kinetis_dmach5 /* Vector 21: DMA channel 5 transfer complete */ - .word kinetis_dmach6 /* Vector 22: DMA channel 6 transfer complete */ - .word kinetis_dmach7 /* Vector 23: DMA channel 7 transfer complete */ - .word kinetis_dmach8 /* Vector 24: DMA channel 8 transfer complete */ - .word kinetis_dmach9 /* Vector 25: DMA channel 9 transfer complete */ - .word kinetis_dmach10 /* Vector 26: DMA channel 10 transfer complete */ - .word kinetis_dmach11 /* Vector 27: DMA channel 11 transfer complete */ - .word kinetis_dmach12 /* Vector 28: DMA channel 12 transfer complete */ - .word kinetis_dmach13 /* Vector 29: DMA channel 13 transfer complete */ - .word kinetis_dmach14 /* Vector 30: DMA channel 14 transfer complete */ - .word kinetis_dmach15 /* Vector 31: DMA channel 15 transfer complete */ - .word kinetis_dmaerr /* Vector 32: DMA error interrupt channels 0-15 */ - .word kinetis_mcm /* Vector 33: MCM Normal interrupt */ - .word kinetis_flashcc /* Vector 34: Flash memory command complete */ - .word kinetis_flashrc /* Vector 35: Flash memory read collision */ - .word kinetis_smclvd /* Vector 36: Mode Controller low-voltage detect, low-voltage warning */ - .word kinetis_llwu /* Vector 37: LLWU Normal Low Leakage Wakeup */ - .word kinetis_wdog /* Vector 38: Watchdog */ - .word kinetis_reserved /* Vector 39: Reserved */ - .word kinetis_i2c0 /* Vector 40: I2C0 */ - .word kinetis_i2c1 /* Vector 41: I2C1 */ - .word kinetis_spi0 /* Vector 42: SPI0 all sources */ - .word kinetis_spi1 /* Vector 43: SPI1 all sources */ - .word kinetis_spi2 /* Vector 44: SPI2 all sources */ - .word kinetis_can0mb /* Vector 45: CAN0 OR'ed Message buffer (0-15) */ - .word kinetis_can0bo /* Vector 46: CAN0 Bus Off */ - .word kinetis_can0err /* Vector 47: CAN0 Error */ - .word kinetis_can0tw /* Vector 48: CAN0 Transmit Warning */ - .word kinetis_can0rw /* Vector 49: CAN0 Receive Warning */ - .word kinetis_can0wu /* Vector 50: CAN0 Wake UP */ - .word kinetis_reserved /* Vector 51: Reserved */ - .word kinetis_reserved /* Vector 52: Reserved */ - .word kinetis_can1mb /* Vector 53: CAN1 OR'ed Message buffer (0-15) */ - .word kinetis_can1bo /* Vector 54: CAN1 Bus Off */ - .word kinetis_can1err /* Vector 55: CAN1 Error */ - .word kinetis_can1tw /* Vector 56: CAN1 Transmit Warning */ - .word kinetis_can1rw /* Vector 57: CAN1 Receive Warning */ - .word kinetis_can1wu /* Vector 58: CAN1 Wake UP */ - .word kinetis_reserved /* Vector 59: Reserved */ - .word kinetis_reserved /* Vector 60: Reserved */ - .word kinetis_uart0s /* Vector 61: UART0 status */ - .word kinetis_uart0e /* Vector 62: UART0 error */ - .word kinetis_uart1s /* Vector 63: UART1 status */ - .word kinetis_uart1e /* Vector 64: UART1 error */ - .word kinetis_uart2s /* Vector 65: UART2 status */ - .word kinetis_uart2e /* Vector 66: UART2 error */ - .word kinetis_uart3s /* Vector 67: UART3 status */ - .word kinetis_uart3e /* Vector 68: UART3 error */ - .word kinetis_uart4s /* Vector 69: UART4 status */ - .word kinetis_uart4e /* Vector 70: UART4 error */ - .word kinetis_uart5s /* Vector 71: UART5 status */ - .word kinetis_uart5e /* Vector 72: UART5 error */ - .word kinetis_adc0 /* Vector 73: ADC0 */ - .word kinetis_adc1 /* Vector 74: ADC1 */ - .word kinetis_cmp0 /* Vector 75: CMP0 */ - .word kinetis_cmp1 /* Vector 76: CMP1 */ - .word kinetis_cmp2 /* Vector 77: CMP2 */ - .word kinetis_ftm0 /* Vector 78: FTM0 all sources */ - .word kinetis_ftm1 /* Vector 79: FTM1 all sources */ - .word kinetis_ftm2 /* Vector 80: FTM2 all sources */ - .word kinetis_cmt /* Vector 81: CMT */ - .word kinetis_rtc /* Vector 82: RTC alarm interrupt */ - .word kinetis_reserved /* Vector 83: Reserved */ - .word kinetis_pitch0 /* Vector 84: PIT channel 0 */ - .word kinetis_pitch1 /* Vector 85: PIT channel 1 */ - .word kinetis_pitch2 /* Vector 86: PIT channel 2 */ - .word kinetis_pitch3 /* Vector 87: PIT channel 3 */ - .word kinetis_pdb /* Vector 88: PDB */ - .word kinetis_usbotg /* Vector 88: USB OTG */ - .word kinetis_usbcd /* Vector 90: USB charger detect */ - .word kinetis_reserved /* Vector 91: Reserved */ - .word kinetis_reserved /* Vector 92: Reserved */ - .word kinetis_reserved /* Vector 93: Reserved */ - .word kinetis_reserved /* Vector 94: Reserved */ - .word kinetis_i2s0 /* Vector 95: I2S0 */ - .word kinetis_sdhc /* Vector 96: SDHC */ - .word kinetis_dac0 /* Vector 97: DAC0 */ - .word kinetis_dac1 /* Vector 98: DAC1 */ - .word kinetis_tsi /* Vector 97: TSI all sources */ - .word kinetis_mcg /* Vector 100: MCG */ - .word kinetis_lpt /* Vector 101: Low power timer */ - .word kinetis_slcd /* Vector 102: Segment LCD all sources */ - .word kinetis_porta /* Vector 103: Pin detect port A */ - .word kinetis_portb /* Vector 104: Pin detect port B */ - .word kinetis_portc /* Vector 105: Pin detect port C */ - .word kinetis_portd /* Vector 106: Pin detect port D */ - .word kinetis_porte /* Vector 107: Pin detect port E */ - .word kinetis_reserved /* Vector 108: Reserved */ - .word kinetis_reserved /* Vector 109: Reserved */ - .word kinetis_swi /* Vector 110: Software interrupt */ - -/* K60 Family *********************************************************************************** - * - * The memory map for the following parts is defined in Freescale document - * K60P144M100SF2RM - */ - -#elif defined(KINETIS_K60) - - .word kinetis_dmach0 /* Vector 16: DMA channel 0 transfer complete */ - .word kinetis_dmach1 /* Vector 17: DMA channel 1 transfer complete */ - .word kinetis_dmach2 /* Vector 18: DMA channel 2 transfer complete */ - .word kinetis_dmach3 /* Vector 19: DMA channel 3 transfer complete */ - .word kinetis_dmach4 /* Vector 20: DMA channel 4 transfer complete */ - .word kinetis_dmach5 /* Vector 21: DMA channel 5 transfer complete */ - .word kinetis_dmach6 /* Vector 22: DMA channel 6 transfer complete */ - .word kinetis_dmach7 /* Vector 23: DMA channel 7 transfer complete */ - .word kinetis_dmach8 /* Vector 24: DMA channel 8 transfer complete */ - .word kinetis_dmach9 /* Vector 25: DMA channel 9 transfer complete */ - .word kinetis_dmach10 /* Vector 26: DMA channel 10 transfer complete */ - .word kinetis_dmach11 /* Vector 27: DMA channel 11 transfer complete */ - .word kinetis_dmach12 /* Vector 28: DMA channel 12 transfer complete */ - .word kinetis_dmach13 /* Vector 29: DMA channel 13 transfer complete */ - .word kinetis_dmach14 /* Vector 30: DMA channel 14 transfer complete */ - .word kinetis_dmach15 /* Vector 31: DMA channel 15 transfer complete */ - .word kinetis_dmaerr /* Vector 32: DMA error interrupt channels 0-15 */ - .word kinetis_mcm /* Vector 33: MCM Normal interrupt */ - .word kinetis_flashcc /* Vector 34: Flash memory command complete */ - .word kinetis_flashrc /* Vector 35: Flash memory read collision */ - .word kinetis_smclvd /* Vector 36: Mode Controller low-voltage detect, low-voltage warning */ - .word kinetis_llwu /* Vector 37: LLWU Normal Low Leakage Wakeup */ - .word kinetis_wdog /* Vector 38: Watchdog */ - .word kinetis_rngb /* Vector 39: Random number generator */ - .word kinetis_i2c0 /* Vector 40: I2C0 */ - .word kinetis_i2c1 /* Vector 41: I2C1 */ - .word kinetis_spi0 /* Vector 42: SPI0 all sources */ - .word kinetis_spi1 /* Vector 43: SPI1 all sources */ - .word kinetis_spi2 /* Vector 44: SPI2 all sources */ - .word kinetis_can0mb /* Vector 45: CAN0 OR'ed Message buffer (0-15) */ - .word kinetis_can0bo /* Vector 46: CAN0 Bus Off */ - .word kinetis_can0err /* Vector 47: CAN0 Error */ - .word kinetis_can0tw /* Vector 48: CAN0 Transmit Warning */ - .word kinetis_can0rw /* Vector 49: CAN0 Receive Warning */ - .word kinetis_can0wu /* Vector 50: CAN0 Wake UP */ - .word kinetis_reserved /* Vector 51: Reserved */ - .word kinetis_reserved /* Vector 52: Reserved */ - .word kinetis_can1mb /* Vector 53: CAN1 OR'ed Message buffer (0-15) */ - .word kinetis_can1bo /* Vector 54: CAN1 Bus Off */ - .word kinetis_can1err /* Vector 55: CAN1 Error */ - .word kinetis_can1tw /* Vector 56: CAN1 Transmit Warning */ - .word kinetis_can1rw /* Vector 57: CAN1 Receive Warning */ - .word kinetis_can1wu /* Vector 58: CAN1 Wake UP */ - .word kinetis_reserved /* Vector 59: Reserved */ - .word kinetis_reserved /* Vector 60: Reserved */ - .word kinetis_uart0s /* Vector 61: UART0 status */ - .word kinetis_uart0e /* Vector 62: UART0 error */ - .word kinetis_uart1s /* Vector 63: UART1 status */ - .word kinetis_uart1e /* Vector 64: UART1 error */ - .word kinetis_uart2s /* Vector 65: UART2 status */ - .word kinetis_uart2e /* Vector 66: UART2 error */ - .word kinetis_uart3s /* Vector 67: UART3 status */ - .word kinetis_uart3e /* Vector 68: UART3 error */ - .word kinetis_uart4s /* Vector 69: UART4 status */ - .word kinetis_uart4e /* Vector 70: UART4 error */ - .word kinetis_uart5s /* Vector 71: UART5 status */ - .word kinetis_uart5e /* Vector 72: UART5 error */ - .word kinetis_adc0 /* Vector 73: ADC0 */ - .word kinetis_adc1 /* Vector 74: ADC1 */ - .word kinetis_cmp0 /* Vector 75: CMP0 */ - .word kinetis_cmp1 /* Vector 76: CMP1 */ - .word kinetis_cmp2 /* Vector 77: CMP2 */ - .word kinetis_ftm0 /* Vector 78: FTM0 all sources */ - .word kinetis_ftm1 /* Vector 79: FTM1 all sources */ - .word kinetis_ftm2 /* Vector 80: FTM2 all sources */ - .word kinetis_cmt /* Vector 81: CMT */ - .word kinetis_rtc /* Vector 82: RTC alarm interrupt */ - .word kinetis_reserved /* Vector 83: Reserved */ - .word kinetis_pitch0 /* Vector 84: PIT channel 0 */ - .word kinetis_pitch1 /* Vector 85: PIT channel 1 */ - .word kinetis_pitch2 /* Vector 86: PIT channel 2 */ - .word kinetis_pitch3 /* Vector 87: PIT channel 3 */ - .word kinetis_pdb /* Vector 88: PDB */ - .word kinetis_usbotg /* Vector 88: USB OTG */ - .word kinetis_usbcd /* Vector 90: USB charger detect */ - .word kinetis_emactmr /* Vector 91: Ethernet MAC IEEE 1588 timer interrupt */ - .word kinetis_emactx /* Vector 92: Ethernet MAC transmit interrupt */ - .word kinetis_emacrx /* Vector 93: Ethernet MAC receive interrupt */ - .word kinetis_emacmisc /* Vector 94: Ethernet MAC error and misc interrupt */ - .word kinetis_i2s0 /* Vector 95: I2S0 */ - .word kinetis_sdhc /* Vector 96: SDHC */ - .word kinetis_dac0 /* Vector 97: DAC0 */ - .word kinetis_dac1 /* Vector 98: DAC1 */ - .word kinetis_tsi /* Vector 97: TSI all sources */ - .word kinetis_mcg /* Vector 100: MCG */ - .word kinetis_lpt /* Vector 101: Low power timer */ - .word kinetis_reserved /* Vector 102: Reserved */ - .word kinetis_porta /* Vector 103: Pin detect port A */ - .word kinetis_portb /* Vector 104: Pin detect port B */ - .word kinetis_portc /* Vector 105: Pin detect port C */ - .word kinetis_portd /* Vector 106: Pin detect port D */ - .word kinetis_porte /* Vector 107: Pin detect port E */ - .word kinetis_reserved /* Vector 108: Reserved */ - .word kinetis_reserved /* Vector 109: Reserved */ - .word kinetis_reserved /* Vector 110: Reserved */ - .word kinetis_reserved /* Vector 111: Reserved */ - .word kinetis_reserved /* Vector 112: Reserved */ - .word kinetis_reserved /* Vector 113: Reserved */ - .word kinetis_reserved /* Vector 114: Reserved */ - .word kinetis_reserved /* Vector 115: Reserved */ - .word kinetis_reserved /* Vector 116: Reserved */ - .word kinetis_reserved /* Vector 117: Reserved */ - .word kinetis_reserved /* Vector 118: Reserved */ - .word kinetis_reserved /* Vector 119: Reserved */ - -/* K64 Family *********************************************************************************** - * - * The memory map for the following parts is defined in Freescale document - * MK64FX512VLL12 - */ - -#elif defined(KINETIS_K64) - - .word kinetis_dmach0 /* Vector 16: DMA channel 0 transfer complete */ - .word kinetis_dmach1 /* Vector 17: DMA channel 1 transfer complete */ - .word kinetis_dmach2 /* Vector 18: DMA channel 2 transfer complete */ - .word kinetis_dmach3 /* Vector 19: DMA channel 3 transfer complete */ - .word kinetis_dmach4 /* Vector 20: DMA channel 4 transfer complete */ - .word kinetis_dmach5 /* Vector 21: DMA channel 5 transfer complete */ - .word kinetis_dmach6 /* Vector 22: DMA channel 6 transfer complete */ - .word kinetis_dmach7 /* Vector 23: DMA channel 7 transfer complete */ - .word kinetis_dmach8 /* Vector 24: DMA channel 8 transfer complete */ - .word kinetis_dmach9 /* Vector 25: DMA channel 9 transfer complete */ - .word kinetis_dmach10 /* Vector 26: DMA channel 10 transfer complete */ - .word kinetis_dmach11 /* Vector 27: DMA channel 11 transfer complete */ - .word kinetis_dmach12 /* Vector 28: DMA channel 12 transfer complete */ - .word kinetis_dmach13 /* Vector 29: DMA channel 13 transfer complete */ - .word kinetis_dmach14 /* Vector 30: DMA channel 14 transfer complete */ - .word kinetis_dmach15 /* Vector 31: DMA channel 15 transfer complete */ - .word kinetis_dmaerr /* Vector 32: DMA error interrupt channels 0-15 */ - .word kinetis_mcm /* Vector 33: MCM Normal interrupt */ - .word kinetis_flashcc /* Vector 34: Flash memory command complete */ - .word kinetis_flashrc /* Vector 35: Flash memory read collision */ - .word kinetis_smclvd /* Vector 36: Mode Controller low-voltage detect, low-voltage warning */ - .word kinetis_llwu /* Vector 37: LLWU Normal Low Leakage Wakeup */ - .word kinetis_wdog /* Vector 38: Watchdog */ - .word kinetis_rngb /* Vector 39: Random number generator */ - .word kinetis_i2c0 /* Vector 40: I2C0 */ - .word kinetis_i2c1 /* Vector 41: I2C1 */ - .word kinetis_spi0 /* Vector 42: SPI0 all sources */ - .word kinetis_spi1 /* Vector 43: SPI1 all sources */ - .word kinetis_i2s0 /* Vector 44: Transmit */ - .word kinetis_i2s1 /* Vector 45: Transmit */ - .word kinetis_reserved /* Vector 46: Reserved */ - .word kinetis_uart0s /* Vector 47: UART0 status */ - .word kinetis_uart0e /* Vector 48: UART0 error */ - .word kinetis_uart1s /* Vector 49: UART1 status */ - .word kinetis_uart1e /* Vector 50: UART1 error */ - .word kinetis_uart2s /* Vector 51: UART2 status */ - .word kinetis_uart2e /* Vector 52: UART2 error */ - .word kinetis_uart3s /* Vector 53: UART3 status */ - .word kinetis_uart3e /* Vector 54: UART3 error */ - .word kinetis_adc0 /* Vector 55: ADC0 */ - .word kinetis_cmp0 /* Vector 56: CMP0 */ - .word kinetis_cmp1 /* Vector 57: CMP1 */ - .word kinetis_ftm0 /* Vector 58: FTM0 all sources */ - .word kinetis_ftm1 /* Vector 59: FTM1 all sources */ - .word kinetis_ftm2 /* Vector 60: FTM2 all sources */ - .word kinetis_cmt /* Vector 61: CMT */ - .word kinetis_rtc0 /* Vector 62: RTC alarm interrupt */ - .word kinetis_rtc1 /* Vector 63: RTC seconds interrupt */ - .word kinetis_pitch0 /* Vector 64: PIT channel 0 */ - .word kinetis_pitch1 /* Vector 65: PIT channel 1 */ - .word kinetis_pitch2 /* Vector 66: PIT channel 2 */ - .word kinetis_pitch3 /* Vector 67: PIT channel 3 */ - .word kinetis_pdb /* Vector 68: PDB */ - .word kinetis_usbotg /* Vector 68: USB OTG */ - .word kinetis_usbcd /* Vector 70: USB charger detect */ - .word kinetis_reserved /* Vector 71: Reserved */ - .word kinetis_dac0 /* Vector 72: DAC0 */ - .word kinetis_mcg /* Vector 73: MCG */ - .word kinetis_lpt /* Vector 74: Low power timer */ - .word kinetis_porta /* Vector 75: Pin detect port A */ - .word kinetis_portb /* Vector 76: Pin detect port B */ - .word kinetis_portc /* Vector 77: Pin detect port C */ - .word kinetis_portd /* Vector 78: Pin detect port D */ - .word kinetis_porte /* Vector 79: Pin detect port E */ - .word kinetis_software /* Vector 80: Software interrupt */ - .word kinetis_spi2 /* Vector 81: SPI2 all sources */ - .word kinetis_uart4s /* Vector 82: UART4 status */ - .word kinetis_uart4e /* Vector 83: UART4 error */ - .word kinetis_uart5s /* Vector 84: UART5 status */ - .word kinetis_uart5e /* Vector 85: UART5 error */ - .word kinetis_cmp2 /* Vector 86: CMP2 */ - .word kinetis_ftm3 /* Vector 87: FTM3 all sources */ - .word kinetis_dac1 /* Vector 88: DAC1 */ - .word kinetis_adc1 /* Vector 89: ADC1 */ - .word kinetis_i2c2 /* Vector 90: I2C2 */ - .word kinetis_can0mb /* Vector 91: CAN0 ORed Message buffer (0-15) */ - .word kinetis_can0bo /* Vector 92: CAN0 Bus Off */ - .word kinetis_can0err /* Vector 93: CAN0 Error */ - .word kinetis_can0tw /* Vector 94: CAN0 Transmit Warning */ - .word kinetis_can0rw /* Vector 95: CAN0 Receive Warning */ - .word kinetis_can0wu /* Vector 96: CAN0 Wake UP */ - .word kinetis_sdhc /* Vector 97: SDHC */ - .word kinetis_emactmr /* Vector 91: Ethernet MAC IEEE 1588 timer interrupt */ - .word kinetis_emactx /* Vector 92: Ethernet MAC transmit interrupt */ - .word kinetis_emacrx /* Vector 93: Ethernet MAC receive interrupt */ - .word kinetis_emacmisc /* Vector 94: Ethernet MAC error and misc interrupt */ - +/* External Interrupts */ + +#if !defined(CONFIG_KINETIS_NOEXT_VECTORS) +#undef VECTOR +#define VECTOR(l,i) .word l + +#undef UNUSED +#define UNUSED(i) .word kinetis_reserved + +#if defined(CONFIG_ARCH_FAMILY_K20) +# include "chip/kinetis_k20vectors.h" +#elif defined(CONFIG_ARCH_FAMILY_K40) +# include "chip/kinetis_k40vectors.h" +#elif defined(CONFIG_ARCH_FAMILY_K60) +# include "chip/kinetis_k60vectors.h" +#elif defined(CONFIG_ARCH_FAMILY_K64) +# include "chip/kinetis_k64vectors.h" +#elif defined(CONFIG_ARCH_FAMILY_K66) +# include "chip/kinetis_k66vectors.h" #else -# error "No vectors for this Kinetis part" +# error "No vectors for Kinetis K chip" #endif +#endif /* CONFIG_KINETIS_NOEXT_VECTORS */ + .size _vectors, .-_vectors -/************************************************************************************************ +/************************************************************************************ * .text - ************************************************************************************************/ - + ************************************************************************************/ .text .type handlers, function .thumb_func handlers: - -/* Processor Exceptions *************************************************************************/ - HANDLER kinetis_reserved, KINETIS_IRQ_RESERVED /* Unexpected/reserved vector */ HANDLER kinetis_nmi, KINETIS_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */ HANDLER kinetis_hardfault, KINETIS_IRQ_HARDFAULT /* Vector 3: Hard fault */ @@ -596,365 +199,30 @@ handlers: HANDLER kinetis_pendsv, KINETIS_IRQ_PENDSV /* Vector 14: Penable system service request */ HANDLER kinetis_systick, KINETIS_IRQ_SYSTICK /* Vector 15: System tick */ -/* External Interrupts **************************************************************************/ -/* K20 Family *********************************************************************************** - * - * The interrupt vectors for the following parts is defined in Freescale document - * K20P64M72SF1RM - */ - -#if defined(KINETIS_K20) - - HANDLER kinetis_dmach0, KINETIS_IRQ_DMACH0 /* Vector 16: DMA channel 0 transfer complete */ - HANDLER kinetis_dmach1, KINETIS_IRQ_DMACH1 /* Vector 17: DMA channel 1 transfer complete */ - HANDLER kinetis_dmach2, KINETIS_IRQ_DMACH2 /* Vector 18: DMA channel 2 transfer complete */ - HANDLER kinetis_dmach3, KINETIS_IRQ_DMACH3 /* Vector 19: DMA channel 3 transfer complete */ - HANDLER kinetis_dmach4, KINETIS_IRQ_DMACH4 /* Vector 20: DMA channel 4 transfer complete */ - HANDLER kinetis_dmach5, KINETIS_IRQ_DMACH5 /* Vector 21: DMA channel 5 transfer complete */ - HANDLER kinetis_dmach6, KINETIS_IRQ_DMACH6 /* Vector 22: DMA channel 6 transfer complete */ - HANDLER kinetis_dmach7, KINETIS_IRQ_DMACH7 /* Vector 23: DMA channel 7 transfer complete */ - HANDLER kinetis_dmach8, KINETIS_IRQ_DMACH8 /* Vector 24: DMA channel 8 transfer complete */ - HANDLER kinetis_dmach9, KINETIS_IRQ_DMACH9 /* Vector 25: DMA channel 9 transfer complete */ - HANDLER kinetis_dmach10, KINETIS_IRQ_DMACH10 /* Vector 26: DMA channel 10 transfer complete */ - HANDLER kinetis_dmach11, KINETIS_IRQ_DMACH11 /* Vector 27: DMA channel 11 transfer complete */ - HANDLER kinetis_dmach12, KINETIS_IRQ_DMACH12 /* Vector 28: DMA channel 12 transfer complete */ - HANDLER kinetis_dmach13, KINETIS_IRQ_DMACH13 /* Vector 29: DMA channel 13 transfer complete */ - HANDLER kinetis_dmach14, KINETIS_IRQ_DMACH14 /* Vector 30: DMA channel 14 transfer complete */ - HANDLER kinetis_dmach15, KINETIS_IRQ_DMACH15 /* Vector 31: DMA channel 15 transfer complete */ - HANDLER kinetis_dmaerr, KINETIS_IRQ_DMAERR /* Vector 32: DMA error interrupt channels 0-15 */ - HANDLER kinetis_flashcc, KINETIS_IRQ_FLASHCC /* Vector 34: Flash memory command complete */ - HANDLER kinetis_flashrc, KINETIS_IRQ_FLASHRC /* Vector 35: Flash memory read collision */ - HANDLER kinetis_smclvd, KINETIS_IRQ_SMCLVD /* Vector 36: Mode Controller low-voltage detect, low-voltage warning */ - HANDLER kinetis_llwu, KINETIS_IRQ_LLWU /* Vector 37: LLWU Normal Low Leakage Wakeup */ - HANDLER kinetis_wdog, KINETIS_IRQ_WDOG /* Vector 38: Watchdog */ - HANDLER kinetis_i2c0, KINETIS_IRQ_I2C0 /* Vector 40: I2C0 */ - HANDLER kinetis_i2c1, KINETIS_IRQ_I2C1 /* Vector 41: I2C1 */ - HANDLER kinetis_spi0, KINETIS_IRQ_SPI0 /* Vector 42: SPI0 all sources */ - HANDLER kinetis_spi1, KINETIS_IRQ_SPI1 /* Vector 43: SPI1 all sources */ - HANDLER kinetis_can0mb, KINETIS_IRQ_CAN0MB /* Vector 45: CAN0 OR'ed Message buffer (0-15) */ - HANDLER kinetis_can0bo, KINETIS_IRQ_CAN0BO /* Vector 46: CAN0 Bus Off */ - HANDLER kinetis_can0err, KINETIS_IRQ_CAN0ERR /* Vector 47: CAN0 Error */ - HANDLER kinetis_can0tw, KINETIS_IRQ_CAN0TW /* Vector 48: CAN0 Transmit Warning */ - HANDLER kinetis_can0rw, KINETIS_IRQ_CAN0RW /* Vector 49: CAN0 Receive Warning */ - HANDLER kinetis_can0wu, KINETIS_IRQ_CAN0WU /* Vector 50: CAN0 Wake UP */ - HANDLER kinetis_uart0s, KINETIS_IRQ_UART0S /* Vector 61: UART0 status */ - HANDLER kinetis_uart0e, KINETIS_IRQ_UART0E /* Vector 62: UART0 error */ - HANDLER kinetis_uart1s, KINETIS_IRQ_UART1S /* Vector 63: UART1 status */ - HANDLER kinetis_uart1e, KINETIS_IRQ_UART1E /* Vector 64: UART1 error */ - HANDLER kinetis_uart2s, KINETIS_IRQ_UART2S /* Vector 65: UART2 status */ - HANDLER kinetis_uart2e, KINETIS_IRQ_UART2E /* Vector 66: UART2 error */ - HANDLER kinetis_adc0, KINETIS_IRQ_ADC0 /* Vector 73: ADC0 */ - HANDLER kinetis_adc1, KINETIS_IRQ_ADC1 /* Vector 74: ADC1 */ - HANDLER kinetis_cmp0, KINETIS_IRQ_CMP0 /* Vector 75: CMP0 */ - HANDLER kinetis_cmp1, KINETIS_IRQ_CMP1 /* Vector 76: CMP1 */ - HANDLER kinetis_cmp2, KINETIS_IRQ_CMP2 /* Vector 77: CMP2 */ - HANDLER kinetis_ftm0, KINETIS_IRQ_FTM0 /* Vector 78: FTM0 all sources */ - HANDLER kinetis_ftm1, KINETIS_IRQ_FTM1 /* Vector 79: FTM1 all sources */ - HANDLER kinetis_ftm2, KINETIS_IRQ_FTM2 /* Vector 80: FTM2 all sources */ - HANDLER kinetis_cmt, KINETIS_IRQ_CMT /* Vector 81: CMT */ - HANDLER kinetis_rtc, KINETIS_IRQ_RTC /* Vector 82: RTC alarm interrupt */ - HANDLER kinetis_pitch0, KINETIS_IRQ_PITCH0 /* Vector 84: PIT channel 0 */ - HANDLER kinetis_pitch1, KINETIS_IRQ_PITCH1 /* Vector 85: PIT channel 1 */ - HANDLER kinetis_pitch2, KINETIS_IRQ_PITCH2 /* Vector 86: PIT channel 2 */ - HANDLER kinetis_pitch3, KINETIS_IRQ_PITCH3 /* Vector 87: PIT channel 3 */ - HANDLER kinetis_pdb, KINETIS_IRQ_PDB /* Vector 88: PDB */ - HANDLER kinetis_usbotg, KINETIS_IRQ_USBOTG /* Vector 88: USB OTG */ - HANDLER kinetis_usbcd, KINETIS_IRQ_USBCD /* Vector 90: USB charger detect */ - HANDLER kinetis_dac0, KINETIS_IRQ_DAC0 /* Vector 97: DAC0 */ - HANDLER kinetis_tsi, KINETIS_IRQ_TSI /* Vector 97: TSI all sources */ - HANDLER kinetis_mcg, KINETIS_IRQ_MCG /* Vector 100: MCG */ - HANDLER kinetis_lpt, KINETIS_IRQ_LPT /* Vector 101: Low power timer */ - HANDLER kinetis_porta, KINETIS_IRQ_PORTA /* Vector 103: Pin detect port A */ - HANDLER kinetis_portb, KINETIS_IRQ_PORTB /* Vector 104: Pin detect port B */ - HANDLER kinetis_portc, KINETIS_IRQ_PORTC /* Vector 105: Pin detect port C */ - HANDLER kinetis_portd, KINETIS_IRQ_PORTD /* Vector 106: Pin detect port D */ - HANDLER kinetis_porte, KINETIS_IRQ_PORTE /* Vector 107: Pin detect port E */ - HANDLER kinetis_swi, KINETIS_IRQ_SWI /* Vector 110: Software interrupt */ - -/* K40 Family *********************************************************************************** - * - * The interrupt vectors for the following parts is defined in Freescale document - * K40P144M100SF2RM - */ - -#elif defined(KINETIS_K40) - - HANDLER kinetis_dmach0, KINETIS_IRQ_DMACH0 /* Vector 16: DMA channel 0 transfer complete */ - HANDLER kinetis_dmach1, KINETIS_IRQ_DMACH1 /* Vector 17: DMA channel 1 transfer complete */ - HANDLER kinetis_dmach2, KINETIS_IRQ_DMACH2 /* Vector 18: DMA channel 2 transfer complete */ - HANDLER kinetis_dmach3, KINETIS_IRQ_DMACH3 /* Vector 19: DMA channel 3 transfer complete */ - HANDLER kinetis_dmach4, KINETIS_IRQ_DMACH4 /* Vector 20: DMA channel 4 transfer complete */ - HANDLER kinetis_dmach5, KINETIS_IRQ_DMACH5 /* Vector 21: DMA channel 5 transfer complete */ - HANDLER kinetis_dmach6, KINETIS_IRQ_DMACH6 /* Vector 22: DMA channel 6 transfer complete */ - HANDLER kinetis_dmach7, KINETIS_IRQ_DMACH7 /* Vector 23: DMA channel 7 transfer complete */ - HANDLER kinetis_dmach8, KINETIS_IRQ_DMACH8 /* Vector 24: DMA channel 8 transfer complete */ - HANDLER kinetis_dmach9, KINETIS_IRQ_DMACH9 /* Vector 25: DMA channel 9 transfer complete */ - HANDLER kinetis_dmach10, KINETIS_IRQ_DMACH10 /* Vector 26: DMA channel 10 transfer complete */ - HANDLER kinetis_dmach11, KINETIS_IRQ_DMACH11 /* Vector 27: DMA channel 11 transfer complete */ - HANDLER kinetis_dmach12, KINETIS_IRQ_DMACH12 /* Vector 28: DMA channel 12 transfer complete */ - HANDLER kinetis_dmach13, KINETIS_IRQ_DMACH13 /* Vector 29: DMA channel 13 transfer complete */ - HANDLER kinetis_dmach14, KINETIS_IRQ_DMACH14 /* Vector 30: DMA channel 14 transfer complete */ - HANDLER kinetis_dmach15, KINETIS_IRQ_DMACH15 /* Vector 31: DMA channel 15 transfer complete */ - HANDLER kinetis_dmaerr, KINETIS_IRQ_DMAERR /* Vector 32: DMA error interrupt channels 0-15 */ - HANDLER kinetis_mcm, KINETIS_IRQ_MCM /* Vector 33: MCM Normal interrupt */ - HANDLER kinetis_flashcc, KINETIS_IRQ_FLASHCC /* Vector 34: Flash memory command complete */ - HANDLER kinetis_flashrc, KINETIS_IRQ_FLASHRC /* Vector 35: Flash memory read collision */ - HANDLER kinetis_smclvd, KINETIS_IRQ_SMCLVD /* Vector 36: Mode Controller low-voltage detect, low-voltage warning */ - HANDLER kinetis_llwu, KINETIS_IRQ_LLWU /* Vector 37: LLWU Normal Low Leakage Wakeup */ - HANDLER kinetis_wdog, KINETIS_IRQ_WDOG /* Vector 38: Watchdog */ - HANDLER kinetis_i2c0, KINETIS_IRQ_I2C0 /* Vector 40: I2C0 */ - HANDLER kinetis_i2c1, KINETIS_IRQ_I2C1 /* Vector 41: I2C1 */ - HANDLER kinetis_spi0, KINETIS_IRQ_SPI0 /* Vector 42: SPI0 all sources */ - HANDLER kinetis_spi1, KINETIS_IRQ_SPI1 /* Vector 43: SPI1 all sources */ - HANDLER kinetis_spi2, KINETIS_IRQ_SPI2 /* Vector 44: SPI2 all sources */ - HANDLER kinetis_can0mb, KINETIS_IRQ_CAN0MB /* Vector 45: CAN0 OR'ed Message buffer (0-15) */ - HANDLER kinetis_can0bo, KINETIS_IRQ_CAN0BO /* Vector 46: CAN0 Bus Off */ - HANDLER kinetis_can0err, KINETIS_IRQ_CAN0ERR /* Vector 47: CAN0 Error */ - HANDLER kinetis_can0tw, KINETIS_IRQ_CAN0TW /* Vector 48: CAN0 Transmit Warning */ - HANDLER kinetis_can0rw, KINETIS_IRQ_CAN0RW /* Vector 49: CAN0 Receive Warning */ - HANDLER kinetis_can0wu, KINETIS_IRQ_CAN0WU /* Vector 50: CAN0 Wake UP */ - HANDLER kinetis_can1mb, KINETIS_IRQ_CAN1MB /* Vector 53: CAN1 OR'ed Message buffer (0-15) */ - HANDLER kinetis_can1bo, KINETIS_IRQ_CAN1BO /* Vector 54: CAN1 Bus Off */ - HANDLER kinetis_can1err, KINETIS_IRQ_CAN1ERR /* Vector 55: CAN1 Error */ - HANDLER kinetis_can1tw, KINETIS_IRQ_CAN1TW /* Vector 56: CAN1 Transmit Warning */ - HANDLER kinetis_can1rw, KINETIS_IRQ_CAN1RW /* Vector 57: CAN1 Receive Warning */ - HANDLER kinetis_can1wu, KINETIS_IRQ_CAN1WU /* Vector 58: CAN1 Wake UP */ - HANDLER kinetis_uart0s, KINETIS_IRQ_UART0S /* Vector 61: UART0 status */ - HANDLER kinetis_uart0e, KINETIS_IRQ_UART0E /* Vector 62: UART0 error */ - HANDLER kinetis_uart1s, KINETIS_IRQ_UART1S /* Vector 63: UART1 status */ - HANDLER kinetis_uart1e, KINETIS_IRQ_UART1E /* Vector 64: UART1 error */ - HANDLER kinetis_uart2s, KINETIS_IRQ_UART2S /* Vector 65: UART2 status */ - HANDLER kinetis_uart2e, KINETIS_IRQ_UART2E /* Vector 66: UART2 error */ - HANDLER kinetis_uart3s, KINETIS_IRQ_UART3S /* Vector 67: UART3 status */ - HANDLER kinetis_uart3e, KINETIS_IRQ_UART3E /* Vector 68: UART3 error */ - HANDLER kinetis_uart4s, KINETIS_IRQ_UART4S /* Vector 69: UART4 status */ - HANDLER kinetis_uart4e, KINETIS_IRQ_UART4E /* Vector 70: UART4 error */ - HANDLER kinetis_uart5s, KINETIS_IRQ_UART5S /* Vector 71: UART5 status */ - HANDLER kinetis_uart5e, KINETIS_IRQ_UART5E /* Vector 72: UART5 error */ - HANDLER kinetis_adc0, KINETIS_IRQ_ADC0 /* Vector 73: ADC0 */ - HANDLER kinetis_adc1, KINETIS_IRQ_ADC1 /* Vector 74: ADC1 */ - HANDLER kinetis_cmp0, KINETIS_IRQ_CMP0 /* Vector 75: CMP0 */ - HANDLER kinetis_cmp1, KINETIS_IRQ_CMP1 /* Vector 76: CMP1 */ - HANDLER kinetis_cmp2, KINETIS_IRQ_CMP2 /* Vector 77: CMP2 */ - HANDLER kinetis_ftm0, KINETIS_IRQ_FTM0 /* Vector 78: FTM0 all sources */ - HANDLER kinetis_ftm1, KINETIS_IRQ_FTM1 /* Vector 79: FTM1 all sources */ - HANDLER kinetis_ftm2, KINETIS_IRQ_FTM2 /* Vector 80: FTM2 all sources */ - HANDLER kinetis_cmt, KINETIS_IRQ_CMT /* Vector 81: CMT */ - HANDLER kinetis_rtc, KINETIS_IRQ_RTC /* Vector 82: RTC alarm interrupt */ - HANDLER kinetis_pitch0, KINETIS_IRQ_PITCH0 /* Vector 84: PIT channel 0 */ - HANDLER kinetis_pitch1, KINETIS_IRQ_PITCH1 /* Vector 85: PIT channel 1 */ - HANDLER kinetis_pitch2, KINETIS_IRQ_PITCH2 /* Vector 86: PIT channel 2 */ - HANDLER kinetis_pitch3, KINETIS_IRQ_PITCH3 /* Vector 87: PIT channel 3 */ - HANDLER kinetis_pdb, KINETIS_IRQ_PDB /* Vector 88: PDB */ - HANDLER kinetis_usbotg, KINETIS_IRQ_USBOTG /* Vector 88: USB OTG */ - HANDLER kinetis_usbcd, KINETIS_IRQ_USBCD /* Vector 90: USB charger detect */ - HANDLER kinetis_i2s0, KINETIS_IRQ_I2S0 /* Vector 95: I2S0 */ - HANDLER kinetis_sdhc, KINETIS_IRQ_SDHC /* Vector 96: SDHC */ - HANDLER kinetis_dac0, KINETIS_IRQ_DAC0 /* Vector 97: DAC0 */ - HANDLER kinetis_dac1, KINETIS_IRQ_DAC1 /* Vector 98: DAC1 */ - HANDLER kinetis_tsi, KINETIS_IRQ_TSI /* Vector 97: TSI all sources */ - HANDLER kinetis_mcg, KINETIS_IRQ_MCG /* Vector 100: MCG */ - HANDLER kinetis_lpt, KINETIS_IRQ_LPT /* Vector 101: Low power timer */ - HANDLER kinetis_slcd, KINETIS_IRQ_SLCD /* Vector 102: Segment LCD all sources */ - HANDLER kinetis_porta, KINETIS_IRQ_PORTA /* Vector 103: Pin detect port A */ - HANDLER kinetis_portb, KINETIS_IRQ_PORTB /* Vector 104: Pin detect port B */ - HANDLER kinetis_portc, KINETIS_IRQ_PORTC /* Vector 105: Pin detect port C */ - HANDLER kinetis_portd, KINETIS_IRQ_PORTD /* Vector 106: Pin detect port D */ - HANDLER kinetis_porte, KINETIS_IRQ_PORTE /* Vector 107: Pin detect port E */ - HANDLER kinetis_swi, KINETIS_IRQ_SWI /* Vector 110: Software interrupt */ - -/* K60 Family *********************************************************************************** - * - * The memory map for the following parts is defined in Freescale document - * K60P144M100SF2RM - */ +#if !defined(CONFIG_KINETIS_NOEXT_VECTORS) -#elif defined(KINETIS_K60) - - HANDLER kinetis_dmach0, KINETIS_IRQ_DMACH0 /* Vector 16: DMA channel 0 transfer complete */ - HANDLER kinetis_dmach1, KINETIS_IRQ_DMACH1 /* Vector 17: DMA channel 1 transfer complete */ - HANDLER kinetis_dmach2, KINETIS_IRQ_DMACH2 /* Vector 18: DMA channel 2 transfer complete */ - HANDLER kinetis_dmach3, KINETIS_IRQ_DMACH3 /* Vector 19: DMA channel 3 transfer complete */ - HANDLER kinetis_dmach4, KINETIS_IRQ_DMACH4 /* Vector 20: DMA channel 4 transfer complete */ - HANDLER kinetis_dmach5, KINETIS_IRQ_DMACH5 /* Vector 21: DMA channel 5 transfer complete */ - HANDLER kinetis_dmach6, KINETIS_IRQ_DMACH6 /* Vector 22: DMA channel 6 transfer complete */ - HANDLER kinetis_dmach7, KINETIS_IRQ_DMACH7 /* Vector 23: DMA channel 7 transfer complete */ - HANDLER kinetis_dmach8, KINETIS_IRQ_DMACH8 /* Vector 24: DMA channel 8 transfer complete */ - HANDLER kinetis_dmach9, KINETIS_IRQ_DMACH9 /* Vector 25: DMA channel 9 transfer complete */ - HANDLER kinetis_dmach10, KINETIS_IRQ_DMACH10 /* Vector 26: DMA channel 10 transfer complete */ - HANDLER kinetis_dmach11, KINETIS_IRQ_DMACH11 /* Vector 27: DMA channel 11 transfer complete */ - HANDLER kinetis_dmach12, KINETIS_IRQ_DMACH12 /* Vector 28: DMA channel 12 transfer complete */ - HANDLER kinetis_dmach13, KINETIS_IRQ_DMACH13 /* Vector 29: DMA channel 13 transfer complete */ - HANDLER kinetis_dmach14, KINETIS_IRQ_DMACH14 /* Vector 30: DMA channel 14 transfer complete */ - HANDLER kinetis_dmach15, KINETIS_IRQ_DMACH15 /* Vector 31: DMA channel 15 transfer complete */ - HANDLER kinetis_dmaerr, KINETIS_IRQ_DMAERR /* Vector 32: DMA error interrupt channels 0-15 */ - HANDLER kinetis_mcm, KINETIS_IRQ_MCM /* Vector 33: MCM Normal interrupt */ - HANDLER kinetis_flashcc, KINETIS_IRQ_FLASHCC /* Vector 34: Flash memory command complete */ - HANDLER kinetis_flashrc, KINETIS_IRQ_FLASHRC /* Vector 35: Flash memory read collision */ - HANDLER kinetis_smclvd, KINETIS_IRQ_SMCLVD /* Vector 36: Mode Controller low-voltage detect, low-voltage warning */ - HANDLER kinetis_llwu, KINETIS_IRQ_LLWU /* Vector 37: LLWU Normal Low Leakage Wakeup */ - HANDLER kinetis_wdog, KINETIS_IRQ_WDOG /* Vector 38: Watchdog */ - HANDLER kinetis_rngb, KINETIS_IRQ_RNGB /* Vector 39: Random number generator */ - HANDLER kinetis_i2c0, KINETIS_IRQ_I2C0 /* Vector 40: I2C0 */ - HANDLER kinetis_i2c1, KINETIS_IRQ_I2C1 /* Vector 41: I2C1 */ - HANDLER kinetis_spi0, KINETIS_IRQ_SPI0 /* Vector 42: SPI0 all sources */ - HANDLER kinetis_spi1, KINETIS_IRQ_SPI1 /* Vector 43: SPI1 all sources */ - HANDLER kinetis_spi2, KINETIS_IRQ_SPI2 /* Vector 44: SPI2 all sources */ - HANDLER kinetis_can0mb, KINETIS_IRQ_CAN0MB /* Vector 45: CAN0 OR'ed Message buffer (0-15) */ - HANDLER kinetis_can0bo, KINETIS_IRQ_CAN0BO /* Vector 46: CAN0 Bus Off */ - HANDLER kinetis_can0err, KINETIS_IRQ_CAN0ERR /* Vector 47: CAN0 Error */ - HANDLER kinetis_can0tw, KINETIS_IRQ_CAN0TW /* Vector 48: CAN0 Transmit Warning */ - HANDLER kinetis_can0rw, KINETIS_IRQ_CAN0RW /* Vector 49: CAN0 Receive Warning */ - HANDLER kinetis_can0wu, KINETIS_IRQ_CAN0WU /* Vector 50: CAN0 Wake UP */ - HANDLER kinetis_can1mb, KINETIS_IRQ_CAN1MB /* Vector 53: CAN1 OR'ed Message buffer (0-15) */ - HANDLER kinetis_can1bo, KINETIS_IRQ_CAN1BO /* Vector 54: CAN1 Bus Off */ - HANDLER kinetis_can1err, KINETIS_IRQ_CAN1ERR /* Vector 55: CAN1 Error */ - HANDLER kinetis_can1tw, KINETIS_IRQ_CAN1TW /* Vector 56: CAN1 Transmit Warning */ - HANDLER kinetis_can1rw, KINETIS_IRQ_CAN1RW /* Vector 57: CAN1 Receive Warning */ - HANDLER kinetis_can1wu, KINETIS_IRQ_CAN1WU /* Vector 58: CAN1 Wake UP */ - HANDLER kinetis_uart0s, KINETIS_IRQ_UART0S /* Vector 61: UART0 status */ - HANDLER kinetis_uart0e, KINETIS_IRQ_UART0E /* Vector 62: UART0 error */ - HANDLER kinetis_uart1s, KINETIS_IRQ_UART1S /* Vector 63: UART1 status */ - HANDLER kinetis_uart1e, KINETIS_IRQ_UART1E /* Vector 64: UART1 error */ - HANDLER kinetis_uart2s, KINETIS_IRQ_UART2S /* Vector 65: UART2 status */ - HANDLER kinetis_uart2e, KINETIS_IRQ_UART2E /* Vector 66: UART2 error */ - HANDLER kinetis_uart3s, KINETIS_IRQ_UART3S /* Vector 67: UART3 status */ - HANDLER kinetis_uart3e, KINETIS_IRQ_UART3E /* Vector 68: UART3 error */ - HANDLER kinetis_uart4s, KINETIS_IRQ_UART4S /* Vector 69: UART4 status */ - HANDLER kinetis_uart4e, KINETIS_IRQ_UART4E /* Vector 70: UART4 error */ - HANDLER kinetis_uart5s, KINETIS_IRQ_UART5S /* Vector 71: UART5 status */ - HANDLER kinetis_uart5e, KINETIS_IRQ_UART5E /* Vector 72: UART5 error */ - HANDLER kinetis_adc0, KINETIS_IRQ_ADC0 /* Vector 73: ADC0 */ - HANDLER kinetis_adc1, KINETIS_IRQ_ADC1 /* Vector 74: ADC1 */ - HANDLER kinetis_cmp0, KINETIS_IRQ_CMP0 /* Vector 75: CMP0 */ - HANDLER kinetis_cmp1, KINETIS_IRQ_CMP1 /* Vector 76: CMP1 */ - HANDLER kinetis_cmp2, KINETIS_IRQ_CMP2 /* Vector 77: CMP2 */ - HANDLER kinetis_ftm0, KINETIS_IRQ_FTM0 /* Vector 78: FTM0 all sources */ - HANDLER kinetis_ftm1, KINETIS_IRQ_FTM1 /* Vector 79: FTM1 all sources */ - HANDLER kinetis_ftm2, KINETIS_IRQ_FTM2 /* Vector 80: FTM2 all sources */ - HANDLER kinetis_cmt, KINETIS_IRQ_CMT /* Vector 81: CMT */ - HANDLER kinetis_rtc, KINETIS_IRQ_RTC /* Vector 82: RTC alarm interrupt */ - HANDLER kinetis_pitch0, KINETIS_IRQ_PITCH0 /* Vector 84: PIT channel 0 */ - HANDLER kinetis_pitch1, KINETIS_IRQ_PITCH1 /* Vector 85: PIT channel 1 */ - HANDLER kinetis_pitch2, KINETIS_IRQ_PITCH2 /* Vector 86: PIT channel 2 */ - HANDLER kinetis_pitch3, KINETIS_IRQ_PITCH3 /* Vector 87: PIT channel 3 */ - HANDLER kinetis_pdb, KINETIS_IRQ_PDB /* Vector 88: PDB */ - HANDLER kinetis_usbotg, KINETIS_IRQ_USBOTG /* Vector 88: USB OTG */ - HANDLER kinetis_usbcd, KINETIS_IRQ_USBCD /* Vector 90: USB charger detect */ - HANDLER kinetis_emactmr, KINETIS_IRQ_EMACTMR /* Vector 91: Ethernet MAC IEEE 1588 timer interrupt */ - HANDLER kinetis_emactx, KINETIS_IRQ_EMACTX /* Vector 92: Ethernet MAC transmit interrupt */ - HANDLER kinetis_emacrx, KINETIS_IRQ_EMACRX /* Vector 93: Ethernet MAC receive interrupt */ - HANDLER kinetis_emacmisc, KINETIS_IRQ_EMACMISC /* Vector 94: Ethernet MAC error and misc interrupt */ - HANDLER kinetis_i2s0, KINETIS_IRQ_I2S0 /* Vector 95: I2S0 */ - HANDLER kinetis_sdhc, KINETIS_IRQ_SDHC /* Vector 96: SDHC */ - HANDLER kinetis_dac0, KINETIS_IRQ_DAC0 /* Vector 97: DAC0 */ - HANDLER kinetis_dac1, KINETIS_IRQ_DAC1 /* Vector 98: DAC1 */ - HANDLER kinetis_tsi, KINETIS_IRQ_TSI /* Vector 97: TSI all sources */ - HANDLER kinetis_mcg, KINETIS_IRQ_MCG /* Vector 100: MCG */ - HANDLER kinetis_lpt, KINETIS_IRQ_LPT /* Vector 101: Low power timer */ - HANDLER kinetis_porta, KINETIS_IRQ_PORTA /* Vector 103: Pin detect port A */ - HANDLER kinetis_portb, KINETIS_IRQ_PORTB /* Vector 104: Pin detect port B */ - HANDLER kinetis_portc, KINETIS_IRQ_PORTC /* Vector 105: Pin detect port C */ - HANDLER kinetis_portd, KINETIS_IRQ_PORTD /* Vector 106: Pin detect port D */ - HANDLER kinetis_porte, KINETIS_IRQ_PORTE /* Vector 107: Pin detect port E */ - -/* K64 Family *********************************************************************************** - * - * The memory map for the following parts is defined in Freescale document - * MK64FX512VLL12 - */ +#undef VECTOR +#define VECTOR(l,i) HANDLER l, i -#elif defined(KINETIS_K64) - - HANDLER kinetis_dmach0, KINETIS_IRQ_DMACH0 /* Vector 16: DMA channel 0 transfer complete */ - HANDLER kinetis_dmach1, KINETIS_IRQ_DMACH1 /* Vector 17: DMA channel 1 transfer complete */ - HANDLER kinetis_dmach2, KINETIS_IRQ_DMACH2 /* Vector 18: DMA channel 2 transfer complete */ - HANDLER kinetis_dmach3, KINETIS_IRQ_DMACH3 /* Vector 19: DMA channel 3 transfer complete */ - HANDLER kinetis_dmach4, KINETIS_IRQ_DMACH4 /* Vector 20: DMA channel 4 transfer complete */ - HANDLER kinetis_dmach5, KINETIS_IRQ_DMACH5 /* Vector 21: DMA channel 5 transfer complete */ - HANDLER kinetis_dmach6, KINETIS_IRQ_DMACH6 /* Vector 22: DMA channel 6 transfer complete */ - HANDLER kinetis_dmach7, KINETIS_IRQ_DMACH7 /* Vector 23: DMA channel 7 transfer complete */ - HANDLER kinetis_dmach8, KINETIS_IRQ_DMACH8 /* Vector 24: DMA channel 8 transfer complete */ - HANDLER kinetis_dmach9, KINETIS_IRQ_DMACH9 /* Vector 25: DMA channel 9 transfer complete */ - HANDLER kinetis_dmach10, KINETIS_IRQ_DMACH10 /* Vector 26: DMA channel 10 transfer complete */ - HANDLER kinetis_dmach11, KINETIS_IRQ_DMACH11 /* Vector 27: DMA channel 11 transfer complete */ - HANDLER kinetis_dmach12, KINETIS_IRQ_DMACH12 /* Vector 28: DMA channel 12 transfer complete */ - HANDLER kinetis_dmach13, KINETIS_IRQ_DMACH13 /* Vector 29: DMA channel 13 transfer complete */ - HANDLER kinetis_dmach14, KINETIS_IRQ_DMACH14 /* Vector 30: DMA channel 14 transfer complete */ - HANDLER kinetis_dmach15, KINETIS_IRQ_DMACH15 /* Vector 31: DMA channel 15 transfer complete */ - HANDLER kinetis_dmaerr, KINETIS_IRQ_DMAERR /* Vector 32: DMA error interrupt channels 0-15 */ - HANDLER kinetis_mcm, KINETIS_IRQ_MCM /* Vector 33: MCM Normal interrupt */ - HANDLER kinetis_flashcc, KINETIS_IRQ_FLASHCC /* Vector 34: Flash memory command complete */ - HANDLER kinetis_flashrc, KINETIS_IRQ_FLASHRC /* Vector 35: Flash memory read collision */ - HANDLER kinetis_smclvd, KINETIS_IRQ_SMCLVD /* Vector 36: Mode Controller low-voltage detect, low-voltage warning */ - HANDLER kinetis_llwu, KINETIS_IRQ_LLWU /* Vector 37: LLWU Normal Low Leakage Wakeup */ - HANDLER kinetis_wdog, KINETIS_IRQ_WDOG /* Vector 38: Watchdog */ - HANDLER kinetis_rngb, KINETIS_IRQ_RNGB /* Vector 39: Random number generator */ - HANDLER kinetis_i2c0, KINETIS_IRQ_I2C0 /* Vector 40: I2C0 */ - HANDLER kinetis_i2c1, KINETIS_IRQ_I2C1 /* Vector 41: I2C1 */ - HANDLER kinetis_spi0, KINETIS_IRQ_SPI0 /* Vector 42: SPI0 all sources */ - HANDLER kinetis_spi1, KINETIS_IRQ_SPI1 /* Vector 43: SPI1 all sources */ - HANDLER kinetis_i2s0, KINETIS_IRQ_I2S0 /* Vector 44: Transmit */ - HANDLER kinetis_i2s1, KINETIS_IRQ_I2S1 /* Vector 45: Transmit */ - HANDLER kinetis_uart0s, KINETIS_IRQ_UART0S /* Vector 47: UART0 status */ - HANDLER kinetis_uart0e, KINETIS_IRQ_UART0E /* Vector 48: UART0 error */ - HANDLER kinetis_uart1s, KINETIS_IRQ_UART1S /* Vector 49: UART1 status */ - HANDLER kinetis_uart1e, KINETIS_IRQ_UART1E /* Vector 50: UART1 error */ - HANDLER kinetis_uart2s, KINETIS_IRQ_UART2S /* Vector 51: UART2 status */ - HANDLER kinetis_uart2e, KINETIS_IRQ_UART2E /* Vector 52: UART2 error */ - HANDLER kinetis_uart3s, KINETIS_IRQ_UART3S /* Vector 53: UART3 status */ - HANDLER kinetis_uart3e, KINETIS_IRQ_UART3E /* Vector 54: UART3 error */ - HANDLER kinetis_adc0, KINETIS_IRQ_ADC0 /* Vector 55: ADC0 */ - HANDLER kinetis_cmp0, KINETIS_IRQ_CMP0 /* Vector 56: CMP0 */ - HANDLER kinetis_cmp1, KINETIS_IRQ_CMP1 /* Vector 57: CMP1 */ - HANDLER kinetis_ftm0, KINETIS_IRQ_FTM0 /* Vector 58: FTM0 all sources */ - HANDLER kinetis_ftm1, KINETIS_IRQ_FTM1 /* Vector 59: FTM1 all sources */ - HANDLER kinetis_ftm2, KINETIS_IRQ_FTM2 /* Vector 60: FTM2 all sources */ - HANDLER kinetis_cmt, KINETIS_IRQ_CMT /* Vector 61: CMT */ - HANDLER kinetis_rtc0, KINETIS_IRQ_RTC0 /* Vector 62: RTC alarm interrupt */ - HANDLER kinetis_rtc1, KINETIS_IRQ_RTC1 /* Vector 63: RTC seconds interrupt */ - HANDLER kinetis_pitch0, KINETIS_IRQ_PITCH0 /* Vector 64: PIT channel 0 */ - HANDLER kinetis_pitch1, KINETIS_IRQ_PITCH1 /* Vector 65: PIT channel 1 */ - HANDLER kinetis_pitch2, KINETIS_IRQ_PITCH2 /* Vector 66: PIT channel 2 */ - HANDLER kinetis_pitch3, KINETIS_IRQ_PITCH3 /* Vector 67: PIT channel 3 */ - HANDLER kinetis_pdb, KINETIS_IRQ_PDB /* Vector 68: PDB */ - HANDLER kinetis_usbotg, KINETIS_IRQ_USBOTG /* Vector 68: USB OTG */ - HANDLER kinetis_usbcd, KINETIS_IRQ_USBCD /* Vector 70: USB charger detect */ - HANDLER kinetis_dac0, KINETIS_IRQ_DAC0 /* Vector 72: DAC0 */ - HANDLER kinetis_mcg, KINETIS_IRQ_MCG /* Vector 73: MCG */ - HANDLER kinetis_lpt, KINETIS_IRQ_LPT /* Vector 74: Low power timer */ - HANDLER kinetis_porta, KINETIS_IRQ_PORTA /* Vector 75: Pin detect port A */ - HANDLER kinetis_portb, KINETIS_IRQ_PORTB /* Vector 76: Pin detect port B */ - HANDLER kinetis_portc, KINETIS_IRQ_PORTC /* Vector 77: Pin detect port C */ - HANDLER kinetis_portd, KINETIS_IRQ_PORTD /* Vector 78: Pin detect port D */ - HANDLER kinetis_porte, KINETIS_IRQ_PORTE /* Vector 79: Pin detect port E */ - HANDLER kinetis_software, KINETIS_IRQ_SOFTWARE /* Vector 80: Software interrupt */ - HANDLER kinetis_spi2, KINETIS_IRQ_SPI2 /* Vector 81: SPI2 all sources */ - HANDLER kinetis_uart4s, KINETIS_IRQ_UART4S /* Vector 82: UART4 status */ - HANDLER kinetis_uart4e, KINETIS_IRQ_UART4E /* Vector 83: UART4 error */ - HANDLER kinetis_uart5s, KINETIS_IRQ_UART5S /* Vector 84: UART5 status */ - HANDLER kinetis_uart5e, KINETIS_IRQ_UART5E /* Vector 85: UART5 error */ - HANDLER kinetis_cmp2, KINETIS_IRQ_CMP2 /* Vector 86: CMP2 */ - HANDLER kinetis_ftm3, KINETIS_IRQ_FTM3 /* Vector 87: FTM3 all sources */ - HANDLER kinetis_dac1, KINETIS_IRQ_DAC1 /* Vector 88: DAC1 */ - HANDLER kinetis_adc1, KINETIS_IRQ_ADC1 /* Vector 89: ADC1 */ - HANDLER kinetis_i2c2, KINETIS_IRQ_I2C2 /* Vector 90: I2C2 */ - HANDLER kinetis_can0mb, KINETIS_IRQ_CAN0MB /* Vector 91: CAN0 ORed Message buffer (0-15) */ - HANDLER kinetis_can0bo, KINETIS_IRQ_CAN0BO /* Vector 92: CAN0 Bus Off */ - HANDLER kinetis_can0err, KINETIS_IRQ_CAN0ERR /* Vector 93: CAN0 Error */ - HANDLER kinetis_can0tw, KINETIS_IRQ_CAN0TW /* Vector 94: CAN0 Transmit Warning */ - HANDLER kinetis_can0rw, KINETIS_IRQ_CAN0RW /* Vector 95: CAN0 Receive Warning */ - HANDLER kinetis_can0wu, KINETIS_IRQ_CAN0WU /* Vector 96: CAN0 Wake UP */ - HANDLER kinetis_sdhc, KINETIS_IRQ_SDHC /* Vector 97: SDHC */ - HANDLER kinetis_emactmr, KINETIS_IRQ_EMACTMR /* Vector 91: Ethernet MAC IEEE 1588 timer interrupt */ - HANDLER kinetis_emactx, KINETIS_IRQ_EMACTX /* Vector 92: Ethernet MAC transmit interrupt */ - HANDLER kinetis_emacrx, KINETIS_IRQ_EMACRX /* Vector 93: Ethernet MAC receive interrupt */ - HANDLER kinetis_emacmisc, KINETIS_IRQ_EMACMISC /* Vector 94: Ethernet MAC error and misc interrupt */ +#undef UNUSED +#define UNUSED(i) +#if defined(CONFIG_ARCH_FAMILY_K20) +# include "chip/kinetis_k20vectors.h" +#elif defined(CONFIG_ARCH_FAMILY_K40) +# include "chip/kinetis_k40vectors.h" +#elif defined(CONFIG_ARCH_FAMILY_K60) +# include "chip/kinetis_k60vectors.h" +#elif defined(CONFIG_ARCH_FAMILY_K64) +# include "chip/kinetis_k64vectors.h" +#elif defined(CONFIG_ARCH_FAMILY_K66) +# include "chip/kinetis_k66vectors.h" #else -# error "No handlers for this Kinetis part" +# error "No vectors for Kinetis K chip" #endif +#endif /* CONFIG_KINETIS_NOEXT_VECTORS */ + /* Common IRQ handling logic. On entry here, the return stack is on either * the PSP or the MSP and looks like the following: * @@ -1096,7 +364,7 @@ exception_common: * * Here: * r0 = Address of the register save area - + * * NOTE: It is a requirement that up_restorefpu() preserve the value of * r0! */ @@ -1183,7 +451,7 @@ exception_common: ldr r14, =EXC_RETURN_PRIVTHR /* Load the special value */ #endif - /* Restore the interrupt state */ + /* Restore the interrupt state */ #ifdef CONFIG_ARMV7M_USEBASEPRI msr basepri, r3 /* Restore interrupts priority masking */ @@ -1202,13 +470,13 @@ exception_common: bx r14 /* And return */ .size handlers, .-handlers -/************************************************************************************************ +/************************************************************************************ * Name: g_intstackalloc/g_intstackbase * * Description: * Shouldn't happen * - ************************************************************************************************/ + ************************************************************************************/ #if CONFIG_ARCH_INTERRUPTSTACK > 7 .bss @@ -1220,11 +488,12 @@ g_intstackalloc: g_intstackbase: .size g_intstackalloc, .-g_intstackalloc #endif + #endif /* CONFIG_ARMV7M_CMNVECTOR */ -/************************************************************************************************ +/************************************************************************************ * .rodata - ************************************************************************************************/ + ************************************************************************************/ .section .rodata, "a" -- GitLab From b29b2874fe52aa820c4346c691723de67a77301a Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Tue, 18 Oct 2016 09:31:42 -1000 Subject: [PATCH 121/734] Kinetis Allow CONFIG_ARMV7M_CMNVECTOR, CONFIG_STACK_COLORATION, CONFIG_ARCH_FPU --- arch/arm/src/kinetis/kinetis_start.c | 195 ++++++++++++++++++++++++++- 1 file changed, 194 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/kinetis/kinetis_start.c b/arch/arm/src/kinetis/kinetis_start.c index 21885d9268..7f209b1351 100644 --- a/arch/arm/src/kinetis/kinetis_start.c +++ b/arch/arm/src/kinetis/kinetis_start.c @@ -54,9 +54,59 @@ #include "chip/kinetis_smc.h" #include "kinetis_userspace.h" +#ifdef CONFIG_ARCH_FPU +# include "nvic.h" +#endif + +/**************************************************************************** + * Private Function prototypes + ****************************************************************************/ + +#ifdef CONFIG_ARCH_FPU +static inline void stm32_fpuconfig(void); +#endif +#ifdef CONFIG_STACK_COLORATION +static void go_os_start(void *pv, unsigned int nbytes) + __attribute__ ((naked, no_instrument_function, noreturn)); +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +/* Memory Map ***************************************************************/ +/* + * 0x0000:0000 - Beginning of the internal FLASH. Address of vectors. + * Mapped as boot memory address 0x0000:0000 at reset. + * 0x07ff:ffff - End of flash region (assuming the max of 2MiB of FLASH). + * 0x1fff:0000 - Start of internal SRAM and start of .data (_sdata) + * - End of .data (_edata) and start of .bss (_sbss) + * - End of .bss (_ebss) and bottom of idle stack + * - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, + * start of heap. NOTE that the ARM uses a decrement before + * store stack so that the correct initial value is the end of + * the stack + 4; + * 0x2002:ffff - End of internal SRAM and end of heap (a + */ + +#define IDLE_STACK ((uintptr_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE-4) +#define HEAP_BASE ((uintptr_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_idle_topstack: _sbss is the start of the BSS region as defined by the + * linker script. _ebss lies at the end of the BSS region. The idle task + * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. + * The IDLE thread is the thread that the system boots on and, eventually, + * becomes the IDLE, do nothing task that runs only when there is nothing + * else to run. The heap continues from there until the end of memory. + * g_idle_topstack is a read-only variable the provides this computed + * address. + */ +#if defined(CONFIG_ARMV7M_CMNVECTOR) +const uintptr_t g_idle_topstack = HEAP_BASE; +#endif /**************************************************************************** * Private Data @@ -70,6 +120,143 @@ * Private Functions ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_STACKCHECK +/* we need to get r10 set before we can allow instrumentation calls */ + +void __start(void) __attribute__ ((no_instrument_function)); +#endif + +/**************************************************************************** + * Name: stm32_fpuconfig + * + * Description: + * Configure the FPU. Relative bit settings: + * + * CPACR: Enables access to CP10 and CP11 + * CONTROL.FPCA: Determines whether the FP extension is active in the + * current context: + * FPCCR.ASPEN: Enables automatic FP state preservation, then the + * processor sets this bit to 1 on successful completion of any FP + * instruction. + * FPCCR.LSPEN: Enables lazy context save of FP state. When this is + * done, the processor reserves space on the stack for the FP state, + * but does not save that state information to the stack. + * + * Software must not change the value of the ASPEN bit or LSPEN bit while either: + * - the CPACR permits access to CP10 and CP11, that give access to the FP + * extension, or + * - the CONTROL.FPCA bit is set to 1 + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_FPU +#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU) + +static inline void stm32_fpuconfig(void) +{ + uint32_t regval; + + /* Set CONTROL.FPCA so that we always get the extended context frame + * with the volatile FP registers stacked above the basic context. + */ + + regval = getcontrol(); + regval |= (1 << 2); + setcontrol(regval); + + /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend + * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we + * are going to turn on CONTROL.FPCA for all contexts. + */ + + regval = getreg32(NVIC_FPCCR); + regval &= ~((1 << 31) | (1 << 30)); + putreg32(regval, NVIC_FPCCR); + + /* Enable full access to CP10 and CP11 */ + + regval = getreg32(NVIC_CPACR); + regval |= ((3 << (2*10)) | (3 << (2*11))); + putreg32(regval, NVIC_CPACR); +} + +#else + +static inline void stm32_fpuconfig(void) +{ + uint32_t regval; + + /* Clear CONTROL.FPCA so that we do not get the extended context frame + * with the volatile FP registers stacked in the saved context. + */ + + regval = getcontrol(); + regval &= ~(1 << 2); + setcontrol(regval); + + /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend + * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we + * are going to keep CONTROL.FPCA off for all contexts. + */ + + regval = getreg32(NVIC_FPCCR); + regval &= ~((1 << 31) | (1 << 30)); + putreg32(regval, NVIC_FPCCR); + + /* Enable full access to CP10 and CP11 */ + + regval = getreg32(NVIC_CPACR); + regval |= ((3 << (2*10)) | (3 << (2*11))); + putreg32(regval, NVIC_CPACR); +} + +#endif + +#else +# define stm32_fpuconfig() +#endif + +/**************************************************************************** + * Name: go_os_start + * + * Description: + * Set the IDLE stack to the + * + ****************************************************************************/ + +#ifdef CONFIG_STACK_COLORATION +static void go_os_start(void *pv, unsigned int nbytes) +{ + /* Set the IDLE stack to the stack coloration value then jump to + * os_start(). We take extreme care here because were currently + * executing on this stack. + * + * We want to avoid sneak stack access generated by the compiler. + */ + + __asm__ __volatile__ + ( + "\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */ + "\tbeq 2f\n" /* (should not happen) */ + + "\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */ + "\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */ + "\tmovt r2, #0xdead\n" + + "1:\n" /* Top of the loop */ + "\tsub r1, r1, #1\n" /* R1 nwords-- */ + "\tcmp r1, #0\n" /* Check (nwords == 0) */ + "\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */ + "\tbne 1b\n" /* Bottom of the loop */ + + "2:\n" + "\tmov r14, #0\n" /* LR = return address (none) */ + "\tb os_start\n" /* Branch to os_start */ + ); +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -87,6 +274,12 @@ void __start(void) const uint32_t *src; uint32_t *dest; +#ifdef CONFIG_ARMV7M_STACKCHECK + /* Set the stack limit before we attempt to call any functions */ + + __asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : ); +#endif + /* Disable the watchdog timer */ kinetis_wddisable(); @@ -134,7 +327,7 @@ void __start(void) * can get debug output as soon as possible (This depends on clock * configuration). */ - + stm32_fpuconfig(); kinetis_lowsetup(); #ifdef USE_EARLYSERIALINIT up_earlyserialinit(); -- GitLab From c3543cf402d0fc0a0abfbd9ab76facfe1866e6b8 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Tue, 18 Oct 2016 10:49:06 -1000 Subject: [PATCH 122/734] Kinetis:BugFix:i2c driver offset swapped for value in kinetis_i2c_putreg --- arch/arm/src/kinetis/kinetis_i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/kinetis/kinetis_i2c.c b/arch/arm/src/kinetis/kinetis_i2c.c index 1713bdbbb1..520534b3a5 100644 --- a/arch/arm/src/kinetis/kinetis_i2c.c +++ b/arch/arm/src/kinetis/kinetis_i2c.c @@ -202,8 +202,8 @@ static uint8_t kinetis_i2c_getreg(struct kinetis_i2cdev_s *priv, * ****************************************************************************/ -static void kinetis_i2c_putreg(struct kinetis_i2cdev_s *priv, uint8_t offset, - uint8_t value) +static void kinetis_i2c_putreg(struct kinetis_i2cdev_s *priv, uint8_t value, + uint8_t offset) { putreg8(value, priv->base + offset); } -- GitLab From 4d39b513b585be5d148c4fd4b8c361de136abd3e Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Tue, 18 Oct 2016 18:15:54 -0600 Subject: [PATCH 123/734] Add functions wcrtomb, wcslcpy, wcsxfrm, wctob, wctomb, wctype, localeconv, strcoll, strxfrm --- include/locale.h | 6 ++ include/string.h | 4 +- libc/Kconfig | 6 ++ libc/libc.csv | 80 +++++++++++--------- libc/locale/Make.defs | 4 + libc/locale/lib_localeconv.c | 69 +++++++++++++++++ libc/locale/lib_setlocale.c | 3 + libc/string/Make.defs | 6 +- libc/string/lib_strcoll.c | 59 +++++++++++++++ libc/string/lib_strxfrm.c | 80 ++++++++++++++++++++ libc/wchar/Make.defs | 8 +- libc/wchar/lib_btowc.c | 3 +- libc/wchar/lib_mbrtowc.c | 3 +- libc/wchar/lib_mbtowc.c | 3 +- libc/wchar/lib_wcrtomb.c | 81 ++++++++++++++++++++ libc/wchar/lib_wcscmp.c | 3 +- libc/wchar/lib_wcscoll.c | 3 +- libc/wchar/lib_wcslcpy.c | 93 +++++++++++++++++++++++ libc/wchar/lib_wcslen.c | 3 +- libc/wchar/lib_wcsxfrm.c | 62 +++++++++++++++ libc/wchar/lib_wctob.c | 68 +++++++++++++++++ libc/wchar/lib_wctomb.c | 75 ++++++++++++++++++ libc/wchar/lib_wctype.c | 143 +++++++++++++++++++++++++++++++++++ libc/wchar/lib_wmemchr.c | 3 +- libc/wchar/lib_wmemcmp.c | 3 +- libc/wchar/lib_wmemcpy.c | 3 +- libc/wchar/lib_wmemmove.c | 3 +- libc/wchar/lib_wmemset.c | 3 +- 28 files changed, 830 insertions(+), 50 deletions(-) create mode 100644 libc/locale/lib_localeconv.c create mode 100644 libc/string/lib_strcoll.c create mode 100644 libc/string/lib_strxfrm.c create mode 100644 libc/wchar/lib_wcrtomb.c create mode 100644 libc/wchar/lib_wcslcpy.c create mode 100644 libc/wchar/lib_wcsxfrm.c create mode 100644 libc/wchar/lib_wctob.c create mode 100644 libc/wchar/lib_wctomb.c create mode 100644 libc/wchar/lib_wctype.c diff --git a/include/locale.h b/include/locale.h index 2d61f8d753..32f97b2dc1 100644 --- a/include/locale.h +++ b/include/locale.h @@ -42,10 +42,14 @@ #include +#ifdef CONFIG_LIBC_LOCALE + /**************************************************************************** * Type Definitions ****************************************************************************/ +struct lconv; + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ @@ -59,10 +63,12 @@ extern "C" #endif FAR char *setlocale(int category, FAR const char *locale); +FAR struct lconv *localeconv(void); #undef EXTERN #ifdef __cplusplus } #endif +#endif /* CONFIG_LIBC_LOCALE */ #endif /* __INCLUDE_LOCALE_H */ diff --git a/include/string.h b/include/string.h index 396f440872..351a9da0e7 100644 --- a/include/string.h +++ b/include/string.h @@ -1,7 +1,7 @@ /**************************************************************************** * include/string.h * - * Copyright (C) 2007-2012, 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2012, 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -79,6 +79,7 @@ int strcmp(FAR const char *, FAR const char *); int strncmp(FAR const char *, FAR const char *, size_t); int strcasecmp(FAR const char *, FAR const char *); int strncasecmp(FAR const char *, FAR const char *, size_t); +int strcoll(FAR const char *, FAR const char *s2); FAR char *strcpy(char *dest, FAR const char *src); FAR char *stpcpy(char *dest, FAR const char *src); FAR char *strncpy(char *, FAR const char *, size_t); @@ -91,6 +92,7 @@ FAR char *strstr(FAR const char *, FAR const char *); FAR char *strcasestr(FAR const char *, FAR const char *); FAR char *strtok(FAR char *, FAR const char *); FAR char *strtok_r(FAR char *, FAR const char *, FAR char **); +size_t strxfrm(FAR char *, FAR const char *, size_t n); FAR void *memchr(FAR const void *s, int c, size_t n); FAR void *memccpy(FAR void *s1, FAR const void *s2, int c, size_t n); diff --git a/libc/Kconfig b/libc/Kconfig index 6df979b0ce..dead1df0b3 100644 --- a/libc/Kconfig +++ b/libc/Kconfig @@ -110,6 +110,12 @@ config LIBC_WCHAR ---help--- By default, wide-characters support is disabled. +config LIBC_LOCALE + bool "Enable I18N (LOCALE) support" + default n + ---help--- + By default, i18n (locale) support is disabled. + config LIB_RAND_ORDER int "Order of the random number generate" default 1 diff --git a/libc/libc.csv b/libc/libc.csv index 327b796d32..c150080de9 100644 --- a/libc/libc.csv +++ b/libc/libc.csv @@ -4,8 +4,8 @@ "aio_error","aio.h","defined(CONFIG_FS_AIO)","int","FAR struct aiocb *" "aio_return","aio.h","defined(CONFIG_FS_AIO)","ssize_t","FAR struct aiocb *" "aio_suspend","aio.h","defined(CONFIG_FS_AIO)","int","FAR struct aiocb *const []|FAR struct aiocb *const *","int","FAR const struct timespec *" -"asprintf","stdio.h","","int","FAR char **","const char *","..." -"vasprintf","stdio.h","","int","FAR char **","const char *","va_list" +"asprintf","stdio.h","","int","FAR char **","FAR const char *","..." +"vasprintf","stdio.h","","int","FAR char **","FAR const char *","va_list" "b16atan2","fixedmath.h","!defined(CONFIG_HAVE_LONG_LONG)","b16_t","b16_t","b16_t" "b16cos","fixedmath.h","","b16_t","b16_t" "b16divb16","fixedmath.h","!defined(CONFIG_HAVE_LONG_LONG)","b16_t","b16_t","b16_t" @@ -26,7 +26,7 @@ "dq_rem","queue.h","","void","FAR dq_entry_t *","dq_queue_t *" "dq_remfirst","queue.h","","FAR dq_entry_t","dq_queue_t *" "dq_remlast","queue.h","","FAR dq_entry_t","dq_queue_t *" -"_err","debug.h","!defined(CONFIG_CPP_HAVE_VARARGS) && defined(CONFIG_DEBUG_ERROR)","int","const char *","..." +"_err","debug.h","!defined(CONFIG_CPP_HAVE_VARARGS) && defined(CONFIG_DEBUG_ERROR)","int","FAR const char *","..." "ether_ntoa","netinet/ether.h","","FAR char","FAR const struct ether_addr *" "fclose","stdio.h","CONFIG_NFILE_DESCRIPTORS > 0 && CONFIG_NFILE_STREAMS > 0","int","FAR FILE *" "fdopen","stdio.h","CONFIG_NFILE_DESCRIPTORS > 0 && CONFIG_NFILE_STREAMS > 0","FAR FILE","int","FAR const char *" @@ -51,7 +51,7 @@ "getoptindp","unistd.h","","int" "getoptoptp","unistd.h","","int" "gets","stdio.h","CONFIG_NFILE_DESCRIPTORS > 0 && CONFIG_NFILE_STREAMS > 0","FAR char","FAR char *" -"gmtime","time.h","","struct tm","const time_t *" +"gmtime","time.h","","struct tm","FAR const time_t *" "gmtime_r","time.h","","FAR struct tm","FAR const time_t *","FAR struct tm *" "htonl","arpa/inet.h","","uint32_t","uint32_t" "htons","arpa/inet.h","","uint16_t","uint16_t" @@ -64,9 +64,9 @@ "lib_dumpbuffer","debug.h","","void","FAR const char *","FAR const uint8_t *","unsigned int" "lio_listio","aio.h","defined(CONFIG_FS_AIO)","int","int","FAR struct aiocb *const []|FAR struct aiocb *const *","int","FAR struct sigevent *" "llabs","stdlib.h","defined(CONFIG_HAVE_LONG_LONG)","long long int","long long int" -"match","nuttx/lib/regex.h","","int","const char *","const char *" -"mbrtowc","wchar.h",""defined(CONFIG_LIBC_WCHAR)","size_t","wchar_t *","const char *", "size_t", "mbstate_t *" -"mbtowc","wchar.h",""defined(CONFIG_LIBC_WCHAR)","int","wchar_t *","const wchar_t *", "size_t" +"match","nuttx/lib/regex.h","","int","FAR const char *","FAR const char *" +"mbrtowc","wchar.h",""defined(CONFIG_LIBC_WCHAR)","size_t","wchar_t *","FAR const char *","size_t","mbstate_t *" +"mbtowc","wchar.h",""defined(CONFIG_LIBC_WCHAR)","int","wchar_t *","FAR const wchar_t *","size_t" "memccpy","string.h","","FAR void","FAR void *","FAR const void *","int c","size_t" "memchr","string.h","","FAR void","FAR const void *","int c","size_t" "memcmp","string.h","","int","FAR const void *","FAR const void *","size_t" @@ -74,12 +74,12 @@ "memmove","string.h","","FAR void","FAR void *","FAR const void *","size_t" "memset","string.h","","FAR void","FAR void *","int c","size_t" "mkfifo","sys/stat.h","CONFIG_NFILE_DESCRIPTORS > 0","int","FAR const char*","mode_t" -"mktime","time.h","","time_t","const struct tm *" +"mktime","time.h","","time_t","FAR const struct tm *" "ntohl","arpa/inet.h","","uint32_t","uint32_t" "ntohs","arpa/inet.h","","uint16_t","uint16_t" "perror","stdio.h","CONFIG_NFILE_DESCRIPTORS > 0 && CONFIG_NFILE_STREAMS > 0","void","FAR const char *" "pipe","unistd.h","CONFIG_NFILE_DESCRIPTORS > 0","int","int [2]|int*" -"printf","stdio.h","","int","const char *","..." +"printf","stdio.h","","int","FAR const char *","..." "pthread_attr_destroy","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_attr_t *" "pthread_attr_getinheritsched","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR const pthread_attr_t *","FAR int *" "pthread_attr_getschedparam","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_attr_t *","FAR struct sched_param *" @@ -98,12 +98,12 @@ "pthread_condattr_init","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_condattr_t *" "pthread_mutexattr_destroy","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_mutexattr_t *" "pthread_mutexattr_getpshared","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_mutexattr_t *","FAR int *" -"pthread_mutexattr_gettype","pthread.h","!defined(CONFIG_DISABLE_PTHREAD) && defined(CONFIG_MUTEX_TYPES)","int","const pthread_mutexattr_t *","int *" +"pthread_mutexattr_gettype","pthread.h","!defined(CONFIG_DISABLE_PTHREAD) && defined(CONFIG_MUTEX_TYPES)","int","FAR const pthread_mutexattr_t *","int *" "pthread_mutexattr_init","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_mutexattr_t *" "pthread_mutexattr_setpshared","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_mutexattr_t *","int " "pthread_mutexattr_settype","pthread.h","!defined(CONFIG_DISABLE_PTHREAD) && defined(CONFIG_MUTEX_TYPES)","int","pthread_mutexattr_t *","int" "puts","stdio.h","CONFIG_NFILE_DESCRIPTORS > 0 && CONFIG_NFILE_STREAMS > 0","int","FAR const char *" -"qsort","stdlib.h","","void","void *","size_t","size_t","int(*)(const void *","const void *)" +"qsort","stdlib.h","","void","void *","size_t","size_t","int(*)(const void *","FAR const void *)" "rand","stdlib.h","","int" "readdir_r","dirent.h","CONFIG_NFILE_DESCRIPTORS > 0","int","FAR DIR *","FAR struct dirent *","FAR struct dirent **" "sched_get_priority_max","sched.h","","int","int" @@ -119,8 +119,8 @@ "sigfillset","signal.h","!defined(CONFIG_DISABLE_SIGNALS)","int","FAR sigset_t *" "sigismember","signal.h","!defined(CONFIG_DISABLE_SIGNALS)","int","FAR const sigset_t *","int" "sleep","unistd.h","!defined(CONFIG_DISABLE_SIGNALS)","unsigned int","unsigned int" -"snprintf","stdio.h","","int","FAR char *","size_t","const char *","..." -"sprintf","stdio.h","","int","FAR char *","const char *","..." +"snprintf","stdio.h","","int","FAR char *","size_t","FAR const char *","..." +"sprintf","stdio.h","","int","FAR char *","FAR const char *","..." "sq_addafter","queue.h","","void","FAR sq_entry_t *","FAR sq_entry_t *","FAR sq_queue_t *" "sq_addfirst","queue.h","","void","FAR sq_entry_t *","sq_queue_t *" "sq_addlast","queue.h","","void","FAR sq_entry_t *","sq_queue_t *" @@ -129,35 +129,37 @@ "sq_remfirst","queue.h","","FAR sq_entry_t","sq_queue_t *" "sq_remlast","queue.h","","FAR sq_entry_t","sq_queue_t *" "srand","stdlib.h","","void","unsigned int" -"sscanf","stdio.h","","int","const char *","const char *","..." +"sscanf","stdio.h","","int","FAR const char *","FAR const char *","..." "strcasecmp","string.h","","int","FAR const char *","FAR const char *" "strcasestr","string.h","","FAR char","FAR const char *","FAR const char *" "strcat","string.h","","FAR char","FAR char *","FAR const char *" "strchr","string.h","","FAR char","FAR const char *","int" "strcmp","string.h","","int","FAR const char *","FAR const char *" -"strcpy","string.h","","FAR char","char *","FAR const char *" +"strcoll","string.h","CONFIG_LIBC_LOCALE","int","FAR const char *","FAR const char *" +"strcpy","string.h","","FAR char *","FAR char *","FAR const char *" "strcspn","string.h","","size_t","FAR const char *","FAR const char *" "strdup","string.h","","FAR char","FAR const char *" "strerror","string.h","","FAR const char","int" -"strftime","time.h","","size_t","char *","size_t","const char *","const struct tm *" +"strftime","time.h","","size_t","FAR char *","size_t","FAR const char *","FAR const struct tm *" "strlen","string.h","","size_t","FAR const char *" "strncasecmp","string.h","","int","FAR const char *","FAR const char *","size_t" "strncat","string.h","","FAR char","FAR char *","FAR const char *","size_t" "strncmp","string.h","","int","FAR const char *","FAR const char *","size_t" -"strncpy","string.h","","FAR char","char *","FAR const char *","size_t" +"strncpy","string.h","","FAR char","FAR char *","FAR const char *","size_t" "strndup","string.h","","FAR char","FAR const char *","size_t" "strnlen","string.h","","size_t","FAR const char *","size_t" "strpbrk","string.h","","FAR char","FAR const char *","FAR const char *" "strrchr","string.h","","FAR char","FAR const char *","int" "strspn","string.h","","size_t","FAR const char *","FAR const char *" "strstr","string.h","","FAR char","FAR const char *","FAR const char *" -"strtod","stdlib.h","","double_t","const char *str","char **endptr" +"strtod","stdlib.h","","double_t","FAR const char *str","FAR char **endptr" "strtok","string.h","","FAR char","FAR char *","FAR const char *" "strtok_r","string.h","","FAR char","FAR char *","FAR const char *","FAR char **" -"strtol","string.h","","long","const char *","char **","int" -"strtoll","stdlib.h","defined(CONFIG_HAVE_LONG_LONG)","long long","const char *nptr","char **endptr","int base" -"strtoul","stdlib.h","","unsigned long","const char *","char **","int" -"strtoull","stdlib.h","defined(CONFIG_HAVE_LONG_LONG)","unsigned long long","const char *","char **","int" +"strtol","string.h","","long","FAR const char *","FAR char **","int" +"strtoll","stdlib.h","defined(CONFIG_HAVE_LONG_LONG)","long long","FAR const char *nptr","FAR char **endptr","int base" +"strtoul","stdlib.h","","unsigned long","FAR const char *","FAR char **","int" +"strtoull","stdlib.h","defined(CONFIG_HAVE_LONG_LONG)","unsigned long long","FAR const char *","FAR char **","int" +"strxfrm","string.h","defined(CONFIG_LIBC_LOCALE)","size_t","FAR char *","FAR const char *","size_t" "syslog","syslog.h","","int","int","FAR const char *","..." "tcflush","termios.h","CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_SERIAL_TERMIOS)","int","int","int" "tcgetattr","termios.h","CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_SERIAL_TERMIOS)","int","int","FAR struct termios *" @@ -169,19 +171,25 @@ "ub16sqr","fixedmath.h","!defined(CONFIG_HAVE_LONG_LONG)","ub16_t","ub16_t" "ungetc","stdio.h","CONFIG_NFILE_DESCRIPTORS > 0 && CONFIG_NFILE_STREAMS > 0","int","int","FAR FILE *" "usleep","unistd.h","!defined(CONFIG_DISABLE_SIGNALS)","int","int","FAR FILE *" -"_info","debug.h","!defined(CONFIG_CPP_HAVE_VARARGS) && defined(CONFIG_DEBUG_INFO)","int","const char *","..." -"vfprintf","stdio.h","CONFIG_NFILE_DESCRIPTORS > 0 && CONFIG_NFILE_STREAMS > 0","int","FAR FILE *","const char *","va_list" +"_info","debug.h","!defined(CONFIG_CPP_HAVE_VARARGS) && defined(CONFIG_DEBUG_INFO)","int","FAR const char *","..." +"vfprintf","stdio.h","CONFIG_NFILE_DESCRIPTORS > 0 && CONFIG_NFILE_STREAMS > 0","int","FAR FILE *","FAR const char *","va_list" "vprintf","stdio.h","CONFIG_NFILE_DESCRIPTORS > 0 && CONFIG_NFILE_STREAMS > 0","int","FAR const char *","va_list" -"vsnprintf","stdio.h","","int","FAR char *","size_t","const char *","va_list" -"vsprintf","stdio.h","","int","FAR char *","const char *","va_list" -"vsscanf","stdio.h","","int","char *","const char *","va_list" +"vsnprintf","stdio.h","","int","FAR char *","size_t","FAR const char *","va_list" +"vsprintf","stdio.h","","int","FAR char *","FAR const char *","va_list" +"vsscanf","stdio.h","","int","FAR char *","FAR const char *","va_list" "vsyslog","syslog.h","","int","int","FAR const char *","va_list" -"wcscmp","wchar.h","defined(CONFIG_LIBC_WCHAR)","int", "const wchar_t *", "const wchar_t *" -"wcscoll","wchar.h","defined(CONFIG_LIBC_WCHAR)","int", "const wchar_t *", "const wchar_t *" -"wcslen","wchar.h","defined(CONFIG_LIBC_WCHAR)","size_t", "const wchar_t *" -"wmemchr","wchar.h","defined(CONFIG_LIBC_WCHAR)","wchar_t *", "wchar_t *", "wchar_t", "size_t" -"wmemcmp","wchar.h","defined(CONFIG_LIBC_WCHAR)","int", "wchar_t *", "wchar_t *", "size_t" -"wmemcpy","wchar.h","defined(CONFIG_LIBC_WCHAR)","wchat_t *", "wchar_t *", "wchar_t *", "size_t" -"wmemmove","wchar.h","defined(CONFIG_LIBC_WCHAR)","wchat_t *", "wchar_t *", "wchar_t *", "size_t" -"wmemset","wchar.h","defined(CONFIG_LIBC_WCHAR)","wchat_t *", "wchar_t *", "wchar_t", "size_t" -"_warn","debug.h","!defined(CONFIG_CPP_HAVE_VARARGS) && defined(CONFIG_DEBUG_WARN)","int","const char *","..." +"wcrtomb","wchar.h","defined(CONFIG_LIBC_WCHAR)","size_t","FAR char *","wchar_t","mbstate_t *" +"wcscmp","wchar.h","defined(CONFIG_LIBC_WCHAR)","int","FAR const wchar_t *","FAR const wchar_t *" +"wcscoll","wchar.h","defined(CONFIG_LIBC_WCHAR)","int","FAR const wchar_t *","FAR const wchar_t *" +"wcslcpy","wchar.h","defined(CONFIG_LIBC_WCHAR)","size_t","FAR const wchar_t *","FAR const wchar_t *","size_t" +"wcslen","wchar.h","defined(CONFIG_LIBC_WCHAR)","size_t","FAR const wchar_t *" +"wcsxfrm","wchar.h","defined(CONFIG_LIBC_WCHAR)","size_t","wchar_t *","FAR const wchar_t *","size_t" +"wctob","wchar.h","defined(CONFIG_LIBC_WCHAR)","int","wchar_t" +"wctomb","wchar.h","defined(CONFIG_LIBC_WCHAR)","int","FAR char *","wchar_t" +"wctype","wctype.h","defined(CONFIG_LIBC_WCHAR)","wctype_t","FAR const char *" +"wmemchr","wchar.h","defined(CONFIG_LIBC_WCHAR)","wchar_t *","wchar_t *","wchar_t","size_t" +"wmemcmp","wchar.h","defined(CONFIG_LIBC_WCHAR)","int","wchar_t *","wchar_t *","size_t" +"wmemcpy","wchar.h","defined(CONFIG_LIBC_WCHAR)","wchat_t *","wchar_t *","wchar_t *","size_t" +"wmemmove","wchar.h","defined(CONFIG_LIBC_WCHAR)","wchat_t *","wchar_t *","wchar_t *","size_t" +"wmemset","wchar.h","defined(CONFIG_LIBC_WCHAR)","wchat_t *","wchar_t *","wchar_t","size_t" +"_warn","debug.h","!defined(CONFIG_CPP_HAVE_VARARGS) && defined(CONFIG_DEBUG_WARN)","int","FAR const char *","..." diff --git a/libc/locale/Make.defs b/libc/locale/Make.defs index a7a40e190b..bbf9c6a33d 100644 --- a/libc/locale/Make.defs +++ b/libc/locale/Make.defs @@ -33,6 +33,8 @@ # ############################################################################ +ifeq ($(CONFIG_LIBC_LOCALE),y) + # Add the locale files to the build CSRCS += lib_setlocale.c @@ -41,3 +43,5 @@ CSRCS += lib_setlocale.c DEPPATH += --dep-path locale VPATH += :locale + +endif diff --git a/libc/locale/lib_localeconv.c b/libc/locale/lib_localeconv.c new file mode 100644 index 0000000000..3238dfa10a --- /dev/null +++ b/libc/locale/lib_localeconv.c @@ -0,0 +1,69 @@ +/**************************************************************************** + * libc/locale/lib_localeconv.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#ifdef CONFIG_LIBC_LOCALE + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: localeconv + * + * Description: + * locales are not supported by NuttX + * + * Input Parameters: + * category and locale - Select the appropriate piece of the program's + * locale. + * + ****************************************************************************/ + +FAR struct lconv *localeconv(void); +{ + /* NULL indicates the the locale was not changed */ + + return NULL; +} +#endif diff --git a/libc/locale/lib_setlocale.c b/libc/locale/lib_setlocale.c index 8f5fffd62e..335eda84e4 100644 --- a/libc/locale/lib_setlocale.c +++ b/libc/locale/lib_setlocale.c @@ -42,6 +42,8 @@ #include #include +#ifdef CONFIG_LIBC_LOCALE + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -64,3 +66,4 @@ FAR char *setlocale(int category, FAR const char *locale) return NULL; } +#endif diff --git a/libc/string/Make.defs b/libc/string/Make.defs index ff0ca1f6bf..beac5ac4de 100644 --- a/libc/string/Make.defs +++ b/libc/string/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # libc/string/Make.defs # -# Copyright (C) 2011-2012, 2014 Gregory Nutt. All rights reserved. +# Copyright (C) 2011-2012, 2014, 2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -51,6 +51,10 @@ CSRCS += lib_memcpy.c endif endif +ifeq ($(CONFIG_LIBC_LOCALE),y) +CSRCS += lib_strcoll.c lib_strxfrm.c +endif + # Add the string directory to the build DEPPATH += --dep-path string diff --git a/libc/string/lib_strcoll.c b/libc/string/lib_strcoll.c new file mode 100644 index 0000000000..25d274dc8e --- /dev/null +++ b/libc/string/lib_strcoll.c @@ -0,0 +1,59 @@ +/**************************************************************************** + * libc/string/lib_strcoll.c + * + * Copyright (c)1999 Citrus Project, + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#ifdef CONFIG_LIBC_LOCALE + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: strcoll + * + * Description: + * The strcoll() compares the string pointed to by a to the string pointed + * to by b, using an interpretation appropriate to the current + * LC_COLLATE state. Current implementation doesn't care about locale. + * + ****************************************************************************/ + +int strcoll(const char *a, const char *b) +{ + return strcmp(a, b); +} +#endif diff --git a/libc/string/lib_strxfrm.c b/libc/string/lib_strxfrm.c new file mode 100644 index 0000000000..61b6bba7e7 --- /dev/null +++ b/libc/string/lib_strxfrm.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * libc/string/lib_strxfrm.c + * + * Copyright (c)1999 Citrus Project, + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#ifdef CONFIG_LIBC_LOCALE + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: strxfrm + * + * Description: + * This function transforms the string pointed to by s2 and places the + * resulting string into the array pointed to by s1. The transformation is + * such that if the strcmp() function is applied to the two transformed + * strings, it returns a value greater than, equal to, or less than zero, + * correspoinding to the result of a <> function applied to the + * same two original strings. + * With a C locale, this function just copies. + * + ****************************************************************************/ + +size_t strxfrm(FAR char *s1, FAR const char *s2, size_t n) +{ + size_t res; + res = 0; + while (n-- > 0) + { + if ((*s1++ = *s2++) != '\0') + { + ++res; + } + else + { + return res; + } + } + while (*s2) + { + ++s2; + ++res; + } + + return res; +} +#endif diff --git a/libc/wchar/Make.defs b/libc/wchar/Make.defs index 45936e895b..4ec911e7b9 100644 --- a/libc/wchar/Make.defs +++ b/libc/wchar/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # libc/wchar/Make.defs # -# Copyright (C) 2011-2012, 2014, 2016 Gregory Nutt. All rights reserved. +# Copyright (C) 2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -33,13 +33,19 @@ # ############################################################################ +ifeq ($(CONFIG_LIBC_WCHAR),y) + # Add the internal C files to the build CSRCS += lib_wcscmp.c lib_wcslen.c lib_wmemchr.c lib_wmemcmp.c lib_wmemcpy.c CSRCS += lib_wmemmove.c lib_wmemset.c lib_mbtowc.c lib_btowc.c lib_mbrtowc.c +CSRCS += lib_wctomb.c lib_wctob.c lib_wcslcpy.c lib_wcsxfrm.c lib_wctype.c +CSRCS += lib_wcrtomb.c # Add the wchar directory to the build DEPPATH += --dep-path wchar VPATH += :wchar +endif + diff --git a/libc/wchar/lib_btowc.c b/libc/wchar/lib_btowc.c index 7314294699..066ed654cc 100644 --- a/libc/wchar/lib_btowc.c +++ b/libc/wchar/lib_btowc.c @@ -38,6 +38,8 @@ #include #include +#ifdef CONFIG_LIBC_WCHAR + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -50,7 +52,6 @@ * ****************************************************************************/ -#ifdef CONFIG_LIBC_WCHAR wint_t btowc(int c) { int retval = 0; diff --git a/libc/wchar/lib_mbrtowc.c b/libc/wchar/lib_mbrtowc.c index 09887b77e0..a1f3ee765c 100644 --- a/libc/wchar/lib_mbrtowc.c +++ b/libc/wchar/lib_mbrtowc.c @@ -39,6 +39,8 @@ #include #include +#ifdef CONFIG_LIBC_WCHAR + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -51,7 +53,6 @@ * ****************************************************************************/ -#ifdef CONFIG_LIBC_WCHAR size_t mbrtowc(FAR wchar_t *pwc, FAR const char *s, size_t n, mbstate_t *ps) { int retval = 0; diff --git a/libc/wchar/lib_mbtowc.c b/libc/wchar/lib_mbtowc.c index 5e50d86b28..aba6d55b56 100644 --- a/libc/wchar/lib_mbtowc.c +++ b/libc/wchar/lib_mbtowc.c @@ -36,6 +36,8 @@ #include #include +#ifdef CONFIG_LIBC_WCHAR + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -48,7 +50,6 @@ * ****************************************************************************/ -#ifdef CONFIG_LIBC_WCHAR int mbtowc(FAR wchar_t * pwc, FAR const char *s, size_t n) { if (s == NULL) diff --git a/libc/wchar/lib_wcrtomb.c b/libc/wchar/lib_wcrtomb.c new file mode 100644 index 0000000000..3e130da6fe --- /dev/null +++ b/libc/wchar/lib_wcrtomb.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * libc/wchar/lib_wcrtomb.c + * + * This code is derived from software contributed to Berkeley by + * Chris Torek. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_LIBC_WCHAR + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: wcrtomb + * + * Description: + * Convert a wide character to a multibyte sequence + * + ****************************************************************************/ + +size_t wcrtomb(FAR char *s, wchar_t wc, FAR mbstate_t * ps) +{ + int retval = 0; + char buf[10]; + + if (s == NULL) + { + retval = wctomb((char *)buf, L'\0'); + } + else + { + retval = wctomb(s, wc); + } + + if (retval == -1) + { + return (size_t) (-1); + } + else + { + return (size_t) retval; + } +} +#endif diff --git a/libc/wchar/lib_wcscmp.c b/libc/wchar/lib_wcscmp.c index 72e6bb3565..c16aa4362c 100644 --- a/libc/wchar/lib_wcscmp.c +++ b/libc/wchar/lib_wcscmp.c @@ -38,6 +38,8 @@ #include #include +#ifdef CONFIG_LIBC_WCHAR + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -54,7 +56,6 @@ * ****************************************************************************/ -#ifdef CONFIG_LIBC_WCHAR int wcscmp(FAR const wchar_t *s1, FAR const wchar_t *s2) { while (*s1 == *s2++) diff --git a/libc/wchar/lib_wcscoll.c b/libc/wchar/lib_wcscoll.c index 9bdc727d21..54308a7117 100644 --- a/libc/wchar/lib_wcscoll.c +++ b/libc/wchar/lib_wcscoll.c @@ -38,6 +38,8 @@ #include #include +#ifdef CONFIG_LIBC_WCHAR + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -55,7 +57,6 @@ * ****************************************************************************/ -#ifdef CONFIG_LIBC_WCHAR int wcscoll(FAR const wchar_t *a, FAR const wchar_t *b) { return wcscmp(a, b); diff --git a/libc/wchar/lib_wcslcpy.c b/libc/wchar/lib_wcslcpy.c new file mode 100644 index 0000000000..3f0522f504 --- /dev/null +++ b/libc/wchar/lib_wcslcpy.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * libc/wchar/lib_wcslcpy.c + * + * Copyright (c) 1998 Todd C. Miller + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#ifdef CONFIG_LIBC_WCHAR + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: wcslen + * + * Description: + * Copy src to string dst of size siz. At most siz-1 characters + * will be copied. Always NUL terminates (unless siz == 0). + * Returns wcslen(src); if retval >= siz, truncation occurred. + * + ****************************************************************************/ + +size_t wcslcpy(FAR wchar_t *dst, FAR const wchar_t *src, size_t siz) +{ + FAR wchar_t *d = dst; + FAR const wchar_t *s = src; + size_t n = siz; + + /* Copy as many bytes as will fit */ + + if (n != 0 && --n != 0) + { + do + { + if ((*d++ = *s++) == 0) + { + break; + } + } + while (--n != 0); + } + + /* Not enough room in dst, add NUL and traverse rest of src */ + + if (n == 0) + { + if (siz != 0) + { + *d = '\0'; /* NUL-terminate dst */ + } + while (*s++); + } + + return (s - src - 1); /* count does not include NUL */ +} +#endif diff --git a/libc/wchar/lib_wcslen.c b/libc/wchar/lib_wcslen.c index f5a4d18afc..2a9a8adca7 100644 --- a/libc/wchar/lib_wcslen.c +++ b/libc/wchar/lib_wcslen.c @@ -38,6 +38,8 @@ #include #include +#ifdef CONFIG_LIBC_WCHAR + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -52,7 +54,6 @@ * ****************************************************************************/ -#ifdef CONFIG_LIBC_WCHAR size_t wcslen(FAR const wchar_t *s) { FAR const wchar_t *p; diff --git a/libc/wchar/lib_wcsxfrm.c b/libc/wchar/lib_wcsxfrm.c new file mode 100644 index 0000000000..2ecad45139 --- /dev/null +++ b/libc/wchar/lib_wcsxfrm.c @@ -0,0 +1,62 @@ +/**************************************************************************** + * libc/wchar/lib_wcsxfrm.c + * + * Copyright (c)1999 Citrus Project, + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#ifdef CONFIG_LIBC_WCHAR + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: wcsxfrm + * + * Description: + * The wcsxfrm() transforms the wide-character string pointed to by b to the + * wide-character string pointed to by a, comparing two transformed wide + * strings with wcscmp() should return the same result as comparing the + * original strings with wcscoll(). + * No more than n wide characters are transformed, including the trailing + * null character. The current implementation of wcsxfrm() simply uses + * wcslcpy() and does not support any language-specific transformations. + * + ****************************************************************************/ + +size_t wcsxfrm(FAR wchar_t *a, FAR const wchar_t *b, size_t n) +{ + return wcslcpy(a, b, n); +} +#endif diff --git a/libc/wchar/lib_wctob.c b/libc/wchar/lib_wctob.c new file mode 100644 index 0000000000..75290974e0 --- /dev/null +++ b/libc/wchar/lib_wctob.c @@ -0,0 +1,68 @@ +/**************************************************************************** + * libc/wchar/lib_wctob.c + * + * This code is derived from software contributed to Berkeley by + * Chris Torek. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_LIBC_WCHAR + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef MB_LEN_MAX +# define MB_LEN_MAX 8 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int wctob(wint_t wc) +{ + unsigned char pmb[MB_LEN_MAX]; + + if (wc == WEOF) + { + return EOF; + } + + return wctomb((char *)pmb, wc) == 1 ? (int)pmb[0] : EOF; +} +#endif diff --git a/libc/wchar/lib_wctomb.c b/libc/wchar/lib_wctomb.c new file mode 100644 index 0000000000..0e86576063 --- /dev/null +++ b/libc/wchar/lib_wctomb.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * libc/wchar/lib_wctomb.c + * + * This code is derived from software contributed to Berkeley by + * Chris Torek. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_LIBC_WCHAR + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: wctomb + * + * Description: + * Try to represent a wide character as a multi byte + * + ****************************************************************************/ + +int wctomb(FAR char *s, wchar_t wc) +{ + if (s == NULL) + { + return 0; + } + + /* Verify that wchar is a valid single-byte character. */ + + if ((size_t) wc >= 0x100) + { + errno = EILSEQ; + return -1; + } + + *s = (char)wc; + return 1; +} +#endif diff --git a/libc/wchar/lib_wctype.c b/libc/wchar/lib_wctype.c new file mode 100644 index 0000000000..5b701c7cf6 --- /dev/null +++ b/libc/wchar/lib_wctype.c @@ -0,0 +1,143 @@ +/**************************************************************************** + * libc/wchar/wctype.c + * + * Copyright (c) 2002 Red Hat Incorporated. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * The name of Red Hat Incorporated may not be used to endorse + * or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#ifdef CONFIG_LIBC_WCHAR + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +wctype_t wctype(FAR const char *c) +{ + switch (*c) + { + case 'a': + if (!strcmp(c, "alnum")) + { + return WC_ALNUM; + } + else if (!strcmp(c, "alpha")) + { + return WC_ALPHA; + } + + break; + + case 'b': + if (!strcmp(c, "blank")) + { + return WC_BLANK; + } + + break; + + case 'c': + if (!strcmp(c, "cntrl")) + { + return WC_CNTRL; + } + + break; + + case 'd': + if (!strcmp(c, "digit")) + { + return WC_DIGIT; + } + + break; + + case 'g': + if (!strcmp(c, "graph")) + { + return WC_GRAPH; + } + + break; + + case 'l': + if (!strcmp(c, "lower")) + { + return WC_LOWER; + } + + break; + + case 'p': + if (!strcmp(c, "print")) + { + return WC_PRINT; + } + else if (!strcmp(c, "punct")) + { + return WC_PUNCT; + } + + break; + + case 's': + if (!strcmp(c, "space")) + { + return WC_SPACE; + } + + break; + + case 'u': + if (!strcmp(c, "upper")) + { + return WC_UPPER; + } + + break; + + case 'x': + if (!strcmp(c, "xdigit")) + { + return WC_XDIGIT; + } + + break; + } + + return 0; +} +#endif diff --git a/libc/wchar/lib_wmemchr.c b/libc/wchar/lib_wmemchr.c index 732c4ca019..4f3e6073cb 100644 --- a/libc/wchar/lib_wmemchr.c +++ b/libc/wchar/lib_wmemchr.c @@ -36,6 +36,8 @@ #include #include +#ifdef CONFIG_LIBC_WCHAR + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -50,7 +52,6 @@ * ****************************************************************************/ -#ifdef CONFIG_LIBC_WCHAR FAR wchar_t *wmemchr(FAR wchar_t *s, wchar_t c, size_t n) { size_t i; diff --git a/libc/wchar/lib_wmemcmp.c b/libc/wchar/lib_wmemcmp.c index 134f69e0d1..05b473a09c 100644 --- a/libc/wchar/lib_wmemcmp.c +++ b/libc/wchar/lib_wmemcmp.c @@ -36,6 +36,8 @@ #include #include +#ifdef CONFIG_LIBC_WCHAR + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -50,7 +52,6 @@ * ****************************************************************************/ -#ifdef CONFIG_LIBC_WCHAR int wmemcmp(FAR const wchar_t *s1, FAR const wchar_t *s2, size_t n) { size_t i; diff --git a/libc/wchar/lib_wmemcpy.c b/libc/wchar/lib_wmemcpy.c index 8a28173c7f..8441ae70b2 100644 --- a/libc/wchar/lib_wmemcpy.c +++ b/libc/wchar/lib_wmemcpy.c @@ -36,6 +36,8 @@ #include #include +#ifdef CONFIG_LIBC_WCHAR + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -50,7 +52,6 @@ * ****************************************************************************/ -#ifdef CONFIG_LIBC_WCHAR FAR wchar_t *wmemcpy(FAR wchar_t *d, FAR wchar_t *s, size_t n) { return (FAR wchar_t *) memcpy(d, s, n * sizeof(wchar_t)); diff --git a/libc/wchar/lib_wmemmove.c b/libc/wchar/lib_wmemmove.c index 3ce34272f3..cbe986ab07 100644 --- a/libc/wchar/lib_wmemmove.c +++ b/libc/wchar/lib_wmemmove.c @@ -36,6 +36,8 @@ #include #include +#ifdef CONFIG_LIBC_WCHAR + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -50,7 +52,6 @@ * ****************************************************************************/ -#ifdef CONFIG_LIBC_WCHAR FAR wchar_t *wmemmove(FAR wchar_t *d, FAR const wchar_t *s, size_t n) { return (FAR wchar_t *) memmove(d, s, n * sizeof(wchar_t)); diff --git a/libc/wchar/lib_wmemset.c b/libc/wchar/lib_wmemset.c index 8eea8a23ed..55da089501 100644 --- a/libc/wchar/lib_wmemset.c +++ b/libc/wchar/lib_wmemset.c @@ -36,6 +36,8 @@ #include #include +#ifdef CONFIG_LIBC_WCHAR + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -50,7 +52,6 @@ * ****************************************************************************/ -#ifdef CONFIG_LIBC_WCHAR FAR wchar_t *wmemset(FAR wchar_t *s, wchar_t c, size_t n) { FAR wchar_t *p; -- GitLab From dfdde741e3587a7cb41ddef2006079cdf49c7563 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Tue, 18 Oct 2016 18:24:58 -0600 Subject: [PATCH 124/734] C library: Add wctype.h; Move lib_wctype.c to libc/wctype --- include/wctype.h | 115 ++++++++++++++++++++++++++++ libc/Makefile | 1 + libc/README.txt | 1 + libc/wctype/Make.defs | 48 ++++++++++++ libc/{wchar => wctype}/lib_wctype.c | 2 +- 5 files changed, 166 insertions(+), 1 deletion(-) create mode 100644 include/wctype.h create mode 100644 libc/wctype/Make.defs rename libc/{wchar => wctype}/lib_wctype.c (99%) diff --git a/include/wctype.h b/include/wctype.h new file mode 100644 index 0000000000..780fb67c7c --- /dev/null +++ b/include/wctype.h @@ -0,0 +1,115 @@ +/**************************************************************************** + * include/wctype.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __INCLUDE_WTYPE_H +#define __INCLUDE_WTYPE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef WEOF +# define WEOF ((wint_t)-1) +#endif + +/* valid values for wctype_t */ + +#define WC_ALNUM 1 +#define WC_ALPHA 2 +#define WC_BLANK 3 +#define WC_CNTRL 4 +#define WC_DIGIT 5 +#define WC_GRAPH 6 +#define WC_LOWER 7 +#define WC_PRINT 8 +#define WC_PUNCT 9 +#define WC_SPACE 10 +#define WC_UPPER 11 +#define WC_XDIGIT 12 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef _WCTYPE_T +# define _WCTYPE_T +typedef int wctype_t; +#endif + +#ifndef _WCTRANS_T +# define _WCTRANS_T +typedef int wctrans_t; +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/* "The header declares the following as functions and may also + * define them as macros. Function prototypes must be provided for use with + * an ISO C compiler." + * + * Reference: Opengroup.org + */ + +int iswalnum(wint_t); +int iswalpha(wint_t); +int iswblank(wint_t); +int iswcntrl(wint_t); +int iswctype(wint_t, wctype_t); +int iswdigit(wint_t); +int iswgraph(wint_t); +int iswlower(wint_t); +int iswprint(wint_t); +int iswpunct(wint_t); +int iswspace(wint_t); +int iswupper(wint_t); +int iswxdigit(wint_t); +int towctrans(wint_t, wctrans_t); +wint_t towlower(wint_t); +wint_t towupper(wint_t); +wctrans_t wctrans(FAR const char *); +int iswctype(wint_t, wctype_t); +wctype_t wctype(FAR const char *); + +#endif /* INCLUDE_WTYPE_H */ diff --git a/libc/Makefile b/libc/Makefile index 4df221514c..81a1994007 100644 --- a/libc/Makefile +++ b/libc/Makefile @@ -88,6 +88,7 @@ include time/Make.defs include tls/Make.defs include unistd/Make.defs include wchar/Make.defs +include wctype/Make.defs include wqueue/Make.defs # REVISIT: Backslash causes problems in $(COBJS) target diff --git a/libc/README.txt b/libc/README.txt index 2e4f902212..dd8a94020d 100644 --- a/libc/README.txt +++ b/libc/README.txt @@ -45,6 +45,7 @@ we have: time - time.h unistd - unistd.h wchar - wchar.h + wctype - wctype.h Most of these are "standard" header files; some are not: hex2bin.h and fixemath.h are non-standard. diff --git a/libc/wctype/Make.defs b/libc/wctype/Make.defs new file mode 100644 index 0000000000..c48e619b64 --- /dev/null +++ b/libc/wctype/Make.defs @@ -0,0 +1,48 @@ +############################################################################ +# libc/wctype/Make.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +ifeq ($(CONFIG_LIBC_WCHAR),y) + +# Add the internal C files to the build + +CSRCS += lib_wctype.c + +# Add the wctype directory to the build + +DEPPATH += --dep-path wctype +VPATH += :wctype + +endif + diff --git a/libc/wchar/lib_wctype.c b/libc/wctype/lib_wctype.c similarity index 99% rename from libc/wchar/lib_wctype.c rename to libc/wctype/lib_wctype.c index 5b701c7cf6..8ba10f06f7 100644 --- a/libc/wchar/lib_wctype.c +++ b/libc/wctype/lib_wctype.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/wchar/wctype.c + * libc/wctype/wctype.c * * Copyright (c) 2002 Red Hat Incorporated. * All rights reserved. -- GitLab From b37c94bc68ffee71ccd9eae7ea20eb456b526cc3 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Tue, 18 Oct 2016 18:28:17 -0600 Subject: [PATCH 125/734] Modify locale.h to add localeconv() and lconv structure --- include/locale.h | 42 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/include/locale.h b/include/locale.h index 32f97b2dc1..17501ec700 100644 --- a/include/locale.h +++ b/include/locale.h @@ -45,10 +45,48 @@ #ifdef CONFIG_LIBC_LOCALE /**************************************************************************** - * Type Definitions + * Pre-processor Definitions ****************************************************************************/ -struct lconv; +#define LC_ALL 0 +#define LC_COLLATE 1 +#define LC_CTYPE 2 +#define LC_MONETARY 3 +#define LC_NUMERIC 4 +#define LC_TIME 5 +#define LC_MESSAGES 6 + +/**************************************************************************** + * Public Type Definitions + ****************************************************************************/ + +struct lconv +{ + FAR char *decimal_point; + FAR char *thousands_sep; + FAR char *grouping; + FAR char *int_curr_symbol; + FAR char *currency_symbol; + FAR char *mon_decimal_point; + FAR char *mon_thousands_sep; + FAR char *mon_grouping; + FAR char *positive_sign; + FAR char *negative_sign; + FAR char int_frac_digits; + FAR char frac_digits; + FAR char p_cs_precedes; + FAR char p_sep_by_space; + FAR char n_cs_precedes; + FAR char n_sep_by_space; + FAR char p_sign_posn; + FAR char n_sign_posn; + FAR char int_n_cs_precedes; + FAR char int_n_sep_by_space; + FAR char int_n_sign_posn; + FAR char int_p_cs_precedes; + FAR char int_p_sep_by_space; + FAR char int_p_sign_posn; +}; /**************************************************************************** * Public Function Prototypes -- GitLab From 890a9eb45d4660314e19eae0270b349529fecb24 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 18 Oct 2016 19:11:09 -0600 Subject: [PATCH 126/734] Fix a few wide character build issues --- include/stdlib.h | 9 +++++++++ include/wchar.h | 15 ++++++++++----- libc/locale/Make.defs | 2 +- libc/locale/lib_localeconv.c | 2 +- libc/stdlib/Make.defs | 4 ++++ libc/{wchar => stdlib}/lib_mbtowc.c | 2 +- libc/{wchar => stdlib}/lib_wctomb.c | 5 +++-- libc/wchar/Make.defs | 5 ++--- libc/wchar/lib_btowc.c | 11 ++++++----- libc/wchar/lib_mbrtowc.c | 7 ++++--- libc/wchar/lib_wcsxfrm.c | 1 + libc/wchar/lib_wctob.c | 4 +++- 12 files changed, 45 insertions(+), 22 deletions(-) rename libc/{wchar => stdlib}/lib_mbtowc.c (98%) rename libc/{wchar => stdlib}/lib_wctomb.c (98%) diff --git a/include/stdlib.h b/include/stdlib.h index 6b4498ebea..ddfcea74a8 100644 --- a/include/stdlib.h +++ b/include/stdlib.h @@ -42,8 +42,10 @@ #include #include + #include #include +#include /**************************************************************************** * Pre-processor Definitions @@ -202,6 +204,13 @@ double_t strtod(FAR const char *str, FAR char **endptr); FAR char *itoa(int val, FAR char *str, int base); +/* Wide character operations */ + +#ifdef CONFIG_LIBC_WCHAR +int mbtowc(FAR wchar_t *pwc, FAR const char *s, size_t n); +int wctomb(FAR char *s, wchar_t wchar); +#endif + /* Memory Management */ FAR void *malloc(size_t); diff --git a/include/wchar.h b/include/wchar.h index 90e3d4f12c..582cec4683 100644 --- a/include/wchar.h +++ b/include/wchar.h @@ -33,9 +33,6 @@ * ****************************************************************************/ -#ifndef __INCLUDE_WCHAR_H -#define __INCLUDE_WCHAR_H - /**************************************************************************** * Included Files ****************************************************************************/ @@ -50,6 +47,14 @@ #include #include +/* REVISIT: Moving the idempotence to this location resolves a circular + * dependency problem with stdlib.h which gets included indirectory and + * needs wchar_t. + */ + +#ifndef __INCLUDE_WCHAR_H +#define __INCLUDE_WCHAR_H + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -105,7 +110,6 @@ typedef int wint_t; * state, the results are unspecified. */ -#if 0 /* Not used */ /* Commented out because this is dangerous. This defines a type that would * be internal to some wchar implementation. NuttX does not implement the * wchar functions. Having this definition is a time bomb: If this header @@ -127,7 +131,6 @@ struct mbstate_s }; typedef struct mbstate_s mbstate_t; -#endif /* FILE * As described in . @@ -218,6 +221,8 @@ size_t wcscspn(const wchar_t *, const wchar_t *); size_t wcsftime(wchar_t *, size_t, const wchar_t *, const struct tm *); size_t wcslen(const wchar_t *); +size_t wcslcpy(FAR wchar_t *, FAR const wchar_t *, size_t); +size_t wcslcat(FAR wchar_t *, FAR const wchar_t *, size_t); wchar_t *wcsncat(wchar_t *, const wchar_t *, size_t); int wcsncmp(const wchar_t *, const wchar_t *, size_t); wchar_t *wcsncpy(wchar_t *, const wchar_t *, size_t); diff --git a/libc/locale/Make.defs b/libc/locale/Make.defs index bbf9c6a33d..b59b798145 100644 --- a/libc/locale/Make.defs +++ b/libc/locale/Make.defs @@ -37,7 +37,7 @@ ifeq ($(CONFIG_LIBC_LOCALE),y) # Add the locale files to the build -CSRCS += lib_setlocale.c +CSRCS += lib_setlocale.c lib_localeconv.c # Add the locale directory to the build diff --git a/libc/locale/lib_localeconv.c b/libc/locale/lib_localeconv.c index 3238dfa10a..697f369cf4 100644 --- a/libc/locale/lib_localeconv.c +++ b/libc/locale/lib_localeconv.c @@ -60,7 +60,7 @@ * ****************************************************************************/ -FAR struct lconv *localeconv(void); +FAR struct lconv *localeconv(void) { /* NULL indicates the the locale was not changed */ diff --git a/libc/stdlib/Make.defs b/libc/stdlib/Make.defs index 618b16a545..22509d22dd 100644 --- a/libc/stdlib/Make.defs +++ b/libc/stdlib/Make.defs @@ -45,6 +45,10 @@ ifeq ($(CONFIG_FS_WRITABLE),y) CSRCS += lib_mktemp.c lib_mkstemp.c endif +ifeq ($(CONFIG_LIBC_WCHAR),y) +CSRCS += lib_mbtowc.c lib_wctomb.c +endif + ifeq ($(CONFIG_PSEUDOTERM_SUSV1),y) CSRCS += lib_ptsname.c lib_ptsnamer.c endif diff --git a/libc/wchar/lib_mbtowc.c b/libc/stdlib/lib_mbtowc.c similarity index 98% rename from libc/wchar/lib_mbtowc.c rename to libc/stdlib/lib_mbtowc.c index aba6d55b56..03b2b93d4e 100644 --- a/libc/wchar/lib_mbtowc.c +++ b/libc/stdlib/lib_mbtowc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/wchar/lib_mbtowc.c + * libc/stdlib/lib_mbtowc.c * * Copyright (c)1999 Citrus Project, * All rights reserved. diff --git a/libc/wchar/lib_wctomb.c b/libc/stdlib/lib_wctomb.c similarity index 98% rename from libc/wchar/lib_wctomb.c rename to libc/stdlib/lib_wctomb.c index 0e86576063..cef60ad149 100644 --- a/libc/wchar/lib_wctomb.c +++ b/libc/stdlib/lib_wctomb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/wchar/lib_wctomb.c + * libc/stdlib/lib_wctomb.c * * This code is derived from software contributed to Berkeley by * Chris Torek. @@ -35,9 +35,10 @@ ****************************************************************************/ #include -#include + #include #include +#include #include #ifdef CONFIG_LIBC_WCHAR diff --git a/libc/wchar/Make.defs b/libc/wchar/Make.defs index 4ec911e7b9..f6788f592d 100644 --- a/libc/wchar/Make.defs +++ b/libc/wchar/Make.defs @@ -38,9 +38,8 @@ ifeq ($(CONFIG_LIBC_WCHAR),y) # Add the internal C files to the build CSRCS += lib_wcscmp.c lib_wcslen.c lib_wmemchr.c lib_wmemcmp.c lib_wmemcpy.c -CSRCS += lib_wmemmove.c lib_wmemset.c lib_mbtowc.c lib_btowc.c lib_mbrtowc.c -CSRCS += lib_wctomb.c lib_wctob.c lib_wcslcpy.c lib_wcsxfrm.c lib_wctype.c -CSRCS += lib_wcrtomb.c +CSRCS += lib_wmemmove.c lib_wmemset.c lib_btowc.c lib_mbrtowc.c lib_wctob.c +CSRCS +=lib_wcslcpy.c lib_wcsxfrm.c lib_wcrtomb.c # Add the wchar directory to the build diff --git a/libc/wchar/lib_btowc.c b/libc/wchar/lib_btowc.c index 066ed654cc..069a4dc9c4 100644 --- a/libc/wchar/lib_btowc.c +++ b/libc/wchar/lib_btowc.c @@ -33,10 +33,11 @@ ****************************************************************************/ #include -#include + #include #include #include +#include #ifdef CONFIG_LIBC_WCHAR @@ -54,18 +55,18 @@ wint_t btowc(int c) { - int retval = 0; wchar_t pwc; - unsigned char b; + char b; + int retval = 0; if (c == EOF) { return WEOF; } - b = (unsigned char)c; + b = (char)c; - retval = mbtowc(&pwc, &b, 1); + retval = mbtowc(&pwc, (FAR const char *)&b, 1); if (retval != 0 && retval != 1) { diff --git a/libc/wchar/lib_mbrtowc.c b/libc/wchar/lib_mbrtowc.c index a1f3ee765c..f82ff1808a 100644 --- a/libc/wchar/lib_mbrtowc.c +++ b/libc/wchar/lib_mbrtowc.c @@ -33,11 +33,12 @@ ****************************************************************************/ #include -#include + #include #include #include #include +#include #ifdef CONFIG_LIBC_WCHAR @@ -68,11 +69,11 @@ size_t mbrtowc(FAR wchar_t *pwc, FAR const char *s, size_t n, mbstate_t *ps) if (retval == -1) { - return (size_t) (-1); + return (size_t)(-1); } else { - return (size_t) retval; + return (size_t)retval; } } #endif diff --git a/libc/wchar/lib_wcsxfrm.c b/libc/wchar/lib_wcsxfrm.c index 2ecad45139..303a540b32 100644 --- a/libc/wchar/lib_wcsxfrm.c +++ b/libc/wchar/lib_wcsxfrm.c @@ -32,6 +32,7 @@ ****************************************************************************/ #include + #include #include diff --git a/libc/wchar/lib_wctob.c b/libc/wchar/lib_wctob.c index 75290974e0..1808bf9e0d 100644 --- a/libc/wchar/lib_wctob.c +++ b/libc/wchar/lib_wctob.c @@ -35,9 +35,11 @@ ****************************************************************************/ #include -#include + #include +#include #include +#include #include #ifdef CONFIG_LIBC_WCHAR -- GitLab From bbf16270247e78d06ca5f555d8241ff0743eca23 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 18 Oct 2016 19:47:42 -0600 Subject: [PATCH 127/734] sys/time.h: timersub macro modified per recommendations of phreakuencies --- include/sys/time.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/include/sys/time.h b/include/sys/time.h index 7b1e15e9b5..3d7139e754 100644 --- a/include/sys/time.h +++ b/include/sys/time.h @@ -77,13 +77,13 @@ #define timersub(tvp, uvp, vvp) \ do \ { \ - (vvp)->tv_sec = (tvp)->tv_sec - (uvp)->tv_sec; \ - if ((uvp)->tv_usec > (tvp)->tv_usec) \ +    (vvp)->tv_sec = (tvp)->tv_sec - (uvp)->tv_sec; \ +    (vvp)->tv_usec = (tvp)->tv_usec - (uvp)->tv_usec; \ +    if ((vvp)->tv_usec < 0) \ { \ - (vvp)->tv_sec--; \ - (tvp)->tv_usec += 1000000; \ - } \ - (vvp)->tv_usec = (tvp)->tv_usec - (uvp)->tv_usec; \ +      (vvp)->tv_sec--; \ +      (vvp)->tv_usec += 1000000; \ +    } \ } \ while (0) @@ -92,8 +92,8 @@ #define timerclear(tvp) \ do \ { \ - tvp)->tv_sec = 0; \ - tvp)->tv_usec = 0; \ + (tvp)->tv_sec = 0; \ + (tvp)->tv_usec = 0; \ } \ while (0) -- GitLab From c73d3e9c5f2a8c0a6a45e33c81b21c98f5dbec39 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 19 Oct 2016 07:06:43 -0600 Subject: [PATCH 128/734] Remove comments that no longer apply. clocale should not do anyting if CONFIG_LIBC_LOCALE is not defined. --- include/cxx/clocale | 2 ++ include/locale.h | 1 + include/stddef.h | 2 +- include/wchar.h | 17 ++--------------- 4 files changed, 6 insertions(+), 16 deletions(-) diff --git a/include/cxx/clocale b/include/cxx/clocale index c99e456567..39d691e484 100644 --- a/include/cxx/clocale +++ b/include/cxx/clocale @@ -46,9 +46,11 @@ // Namespace //*************************************************************************** +#ifdef CONFIG_LIBC_LOCALE namespace std { using ::setlocale; } +#endif #endif // __INCLUDE_CXX_CLOCALE diff --git a/include/locale.h b/include/locale.h index 17501ec700..501990dbaa 100644 --- a/include/locale.h +++ b/include/locale.h @@ -40,6 +40,7 @@ * Included Files ****************************************************************************/ +#include #include #ifdef CONFIG_LIBC_LOCALE diff --git a/include/stddef.h b/include/stddef.h index 2b59c58a3d..63e815daf8 100644 --- a/include/stddef.h +++ b/include/stddef.h @@ -80,7 +80,7 @@ * codes for all members of the largest character set specified among the * locales supported by the compilation environment: the null character has * the code value 0 and each member of the portable character set has a - * code value equal to its value when used as the lone character in an\ + * code value equal to its value when used as the lone character in an * integer character constant. * * size_t diff --git a/include/wchar.h b/include/wchar.h index 582cec4683..805521fa2c 100644 --- a/include/wchar.h +++ b/include/wchar.h @@ -102,6 +102,8 @@ typedef int wint_t; * A scalar type of a data object that can hold values which represent * locale-specific character classification. * + * Ddefined in wctype.h. Should be defined here. + * * mbstate_t * An object type other than an array type that can hold the conversion * state information necessary to convert between sequences of (possibly @@ -110,21 +112,6 @@ typedef int wint_t; * state, the results are unspecified. */ -/* Commented out because this is dangerous. This defines a type that would - * be internal to some wchar implementation. NuttX does not implement the - * wchar functions. Having this definition is a time bomb: If this header - * file is inadvertently included in code that interacts with an external - * library and if the definition of mbstate_t does not EXACTLY match the - * usage in that external library, then a potentially fatal error could - * occur. - * - * It is better to let the build error out due to the lack of the mbstate_t - * definition. At least that way, the problem can be avoided and the user - * can come up with some alternative way of dealing with the interfacing - * issue that does not require NuttX to be in lock-step with some external - * implementation. - */ - struct mbstate_s { int __fill[6]; -- GitLab From 53700fc71f42f9c5831fbccae6aff5fb049c7bc0 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Wed, 19 Oct 2016 07:22:13 -0600 Subject: [PATCH 129/734] Add isblank() macro to ctype.h --- include/ctype.h | 10 ++++++++++ include/cxx/cctype | 1 + 2 files changed, 11 insertions(+) diff --git a/include/ctype.h b/include/ctype.h index 67dc99e6e1..d3d62b53fd 100644 --- a/include/ctype.h +++ b/include/ctype.h @@ -134,6 +134,16 @@ #define isalpha(c) (islower(c) || isupper(c)) +/**************************************************************************** + * Name: isblank + * + * Description: + * Checks for blank characters (space or tab) + * + ****************************************************************************/ + +#define isblank(c) (isspace(c) || (c) == '\t') + /**************************************************************************** * Name: isdigit * diff --git a/include/cxx/cctype b/include/cxx/cctype index 604bc2c23d..36b62ca8c5 100644 --- a/include/cxx/cctype +++ b/include/cxx/cctype @@ -55,6 +55,7 @@ #undef isprint #undef ispunct #undef isspace +#undef isblank #undef isupper #undef isxdigit #undef tolower -- GitLab From b852bb3403b2f2e319a481c9b014124e11cc22eb Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Wed, 19 Oct 2016 07:49:33 -0600 Subject: [PATCH 130/734] Add iswctype, towlower, towupper and wcsftime functions --- include/wchar.h | 2 +- libc/libc.csv | 16 ++++ libc/wchar/Make.defs | 7 +- libc/wchar/lib_wcsftime.c | 57 +++++++++++++ libc/wchar/lib_wcsxfrm.c | 1 + libc/wctype/Make.defs | 3 +- libc/wctype/lib_iswctype.c | 161 +++++++++++++++++++++++++++++++++++++ libc/wctype/lib_towlower.c | 66 +++++++++++++++ libc/wctype/lib_towupper.c | 66 +++++++++++++++ libc/wctype/lib_wctype.c | 2 + 10 files changed, 375 insertions(+), 6 deletions(-) create mode 100644 libc/wchar/lib_wcsftime.c create mode 100644 libc/wctype/lib_iswctype.c create mode 100644 libc/wctype/lib_towlower.c create mode 100644 libc/wctype/lib_towupper.c diff --git a/include/wchar.h b/include/wchar.h index 805521fa2c..7fd721d7ef 100644 --- a/include/wchar.h +++ b/include/wchar.h @@ -48,7 +48,7 @@ #include /* REVISIT: Moving the idempotence to this location resolves a circular - * dependency problem with stdlib.h which gets included indirectory and + * dependency problem with stdlib.h which gets included indirectly and * needs wchar_t. */ diff --git a/libc/libc.csv b/libc/libc.csv index c150080de9..e54fa5a7df 100644 --- a/libc/libc.csv +++ b/libc/libc.csv @@ -60,6 +60,19 @@ "inet_ntoa","arpa/inet.h","defined(CONFIG_NET_IPv4) && defined(CONFIG_CAN_PASS_STRUCTS)","FAR char","struct in_addr" "inet_ntop","arpa/inet.h","","FAR const char","int","FAR const void *","FAR char *","socklen_t" "inet_pton","arpa/inet.h","","int","int","FAR const char *","FAR void *" +"iswalnum","wctype.h","defined(CONFIG_LIBC_WCHAR)","int","wint_t" +"iswalpha","wctype.h","defined(CONFIG_LIBC_WCHAR)","int","wint_t" +"iswblank","wctype.h","defined(CONFIG_LIBC_WCHAR)","int","wint_t" +"iswcntrl","wctype.h","defined(CONFIG_LIBC_WCHAR)","int","wint_t" +"iswctype","wctype.h","defined(CONFIG_LIBC_WCHAR)","int","wint_t", "wctype_t" +"iswdigit","wctype.h","defined(CONFIG_LIBC_WCHAR)","int","wint_t" +"iswgraph","wctype.h","defined(CONFIG_LIBC_WCHAR)","int","wint_t" +"iswlower","wctype.h","defined(CONFIG_LIBC_WCHAR)","int","wint_t" +"iswprint","wctype.h","defined(CONFIG_LIBC_WCHAR)","int","wint_t" +"iswpunct","wctype.h","defined(CONFIG_LIBC_WCHAR)","int","wint_t" +"iswspace","wctype.h","defined(CONFIG_LIBC_WCHAR)","int","wint_t" +"iswupper","wctype.h","defined(CONFIG_LIBC_WCHAR)","int","wint_t" +"iswxdigit","wctype.h","defined(CONFIG_LIBC_WCHAR)","int","wint_t" "labs","stdlib.h","","long int","long int" "lib_dumpbuffer","debug.h","","void","FAR const char *","FAR const uint8_t *","unsigned int" "lio_listio","aio.h","defined(CONFIG_FS_AIO)","int","int","FAR struct aiocb *const []|FAR struct aiocb *const *","int","FAR struct sigevent *" @@ -166,6 +179,8 @@ "tcsetattr","termios.h","CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_SERIAL_TERMIOS)","int","int","int","FAR const struct termios *" "telldir","dirent.h","CONFIG_NFILE_DESCRIPTORS > 0","off_t","FAR DIR *" "time","time.h","","time_t","time_t *" +"towlower","wchar.h","defined(CONFIG_LIBC_WCHAR)","wint_t","wint_t" +"towupper","wchar.h","defined(CONFIG_LIBC_WCHAR)","wint_t","wint_t" "ub16divub16","fixedmath.h","!defined(CONFIG_HAVE_LONG_LONG)","ub16_t","ub16_t","ub16_t" "ub16mulub16","fixedmath.h","!defined(CONFIG_HAVE_LONG_LONG)","ub16_t","ub16_t","ub16_t" "ub16sqr","fixedmath.h","!defined(CONFIG_HAVE_LONG_LONG)","ub16_t","ub16_t" @@ -181,6 +196,7 @@ "wcrtomb","wchar.h","defined(CONFIG_LIBC_WCHAR)","size_t","FAR char *","wchar_t","mbstate_t *" "wcscmp","wchar.h","defined(CONFIG_LIBC_WCHAR)","int","FAR const wchar_t *","FAR const wchar_t *" "wcscoll","wchar.h","defined(CONFIG_LIBC_WCHAR)","int","FAR const wchar_t *","FAR const wchar_t *" +"wcsftime","wchar.h","defined(CONFIG_LIBC_WCHAR)","size_t", "FAR wchar_t *", "size_t", "FAR const wchar_t *", "FAR const struct tm *" "wcslcpy","wchar.h","defined(CONFIG_LIBC_WCHAR)","size_t","FAR const wchar_t *","FAR const wchar_t *","size_t" "wcslen","wchar.h","defined(CONFIG_LIBC_WCHAR)","size_t","FAR const wchar_t *" "wcsxfrm","wchar.h","defined(CONFIG_LIBC_WCHAR)","size_t","wchar_t *","FAR const wchar_t *","size_t" diff --git a/libc/wchar/Make.defs b/libc/wchar/Make.defs index f6788f592d..dbede3342a 100644 --- a/libc/wchar/Make.defs +++ b/libc/wchar/Make.defs @@ -37,9 +37,10 @@ ifeq ($(CONFIG_LIBC_WCHAR),y) # Add the internal C files to the build -CSRCS += lib_wcscmp.c lib_wcslen.c lib_wmemchr.c lib_wmemcmp.c lib_wmemcpy.c -CSRCS += lib_wmemmove.c lib_wmemset.c lib_btowc.c lib_mbrtowc.c lib_wctob.c -CSRCS +=lib_wcslcpy.c lib_wcsxfrm.c lib_wcrtomb.c +CSRCS += lib_wcscmp.c lib_wcslen.c lib_wmemchr.c lib_wmemcmp.c +CSRCS += lib_wmemcpy.c lib_wmemmove.c lib_wmemset.c lib_btowc.c +CSRCS += lib_mbrtowc.c lib_wctob.c lib_wcslcpy.c lib_wcsxfrm.c +CSRCS += lib_wcrtomb.c lib_wcsftime.c lib_wcscoll.c # Add the wchar directory to the build diff --git a/libc/wchar/lib_wcsftime.c b/libc/wchar/lib_wcsftime.c new file mode 100644 index 0000000000..70d3b55237 --- /dev/null +++ b/libc/wchar/lib_wcsftime.c @@ -0,0 +1,57 @@ +/**************************************************************************** + * libc/wchar/lib_wcsftime.c + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef CONFIG_LIBC_WCHAR +size_t wcsftime(FAR wchar_t *s, size_t maxsize, FAR const wchar_t *format, + FAR const struct tm *tim_p) +{ + /* REVISIT: We can't just use the wide character string... We need to + * convert it to a normal C string first. + */ + + return strftime((FAR char *)s, maxsize, (FAR char *)format, tim_p); +} +#endif diff --git a/libc/wchar/lib_wcsxfrm.c b/libc/wchar/lib_wcsxfrm.c index 303a540b32..b083eaf013 100644 --- a/libc/wchar/lib_wcsxfrm.c +++ b/libc/wchar/lib_wcsxfrm.c @@ -7,6 +7,7 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: + * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright diff --git a/libc/wctype/Make.defs b/libc/wctype/Make.defs index c48e619b64..aa94e9716b 100644 --- a/libc/wctype/Make.defs +++ b/libc/wctype/Make.defs @@ -37,7 +37,7 @@ ifeq ($(CONFIG_LIBC_WCHAR),y) # Add the internal C files to the build -CSRCS += lib_wctype.c +CSRCS += lib_wctype.c lib_iswctype.c lib_towlower.c lib_towupper.c # Add the wctype directory to the build @@ -45,4 +45,3 @@ DEPPATH += --dep-path wctype VPATH += :wctype endif - diff --git a/libc/wctype/lib_iswctype.c b/libc/wctype/lib_iswctype.c new file mode 100644 index 0000000000..8c3185250d --- /dev/null +++ b/libc/wctype/lib_iswctype.c @@ -0,0 +1,161 @@ +/**************************************************************************** + * libc/wctype/lib_iswctype.c + * + * Copyright (c) 2002 Red Hat Incorporated. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * The name of Red Hat Incorporated may not be used to endorse + * or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#ifdef CONFIG_LIBC_WCHAR + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int iswalnum(wint_t c) +{ + return (iswalpha(c) || iswdigit(c)); +} + +int iswalpha(wint_t c) +{ + return (c < (wint_t)0x100 ? isalpha(c) : 0); +} + +int iswblank(wint_t c) +{ + return (c < (wint_t)0x100 ? isblank(c) : 0); +} + +int iswcntrl(wint_t c) +{ + return (c < (wint_t)0x100 ? iscntrl(c) : 0); +} + +int iswdigit(wint_t c) +{ + return (c >= (wint_t)'0' && c <= (wint_t)'9'); +} + +int iswgraph(wint_t c) +{ + return (iswprint(c) && !iswspace(c)); +} + +int iswlower(wint_t c) +{ + return (towupper(c) != c); +} + +int iswprint(wint_t c) +{ + return (c < (wint_t) 0x100 ? isprint(c) : 0); +} + +int iswpunct(wint_t c) +{ + return (!iswalnum(c) && iswgraph(c)); +} + +int iswspace(wint_t c) +{ + return (c < 0x100 ? isspace(c) : 0); +} + +int iswupper(wint_t c) +{ + return (towlower(c) != c); +} + +int iswxdigit(wint_t c) +{ + return ((c >= (wint_t)'0' && c <= (wint_t)'9') || + (c >= (wint_t)'a' && c <= (wint_t)'f') || + (c >= (wint_t)'A' && c <= (wint_t)'F')); +} + +int iswctype(wint_t c, wctype_t desc) +{ + switch (desc) + { + case WC_ALNUM: + return iswalnum(c); + + case WC_ALPHA: + return iswalpha(c); + + case WC_BLANK: + return iswblank(c); + + case WC_CNTRL: + return iswcntrl(c); + + case WC_DIGIT: + return iswdigit(c); + + case WC_GRAPH: + return iswgraph(c); + + case WC_LOWER: + return iswlower(c); + + case WC_PRINT: + return iswprint(c); + + case WC_PUNCT: + return iswpunct(c); + + case WC_SPACE: + return iswspace(c); + + case WC_UPPER: + return iswupper(c); + + case WC_XDIGIT: + return iswxdigit(c); + + default: + return 0; /* eliminate warning */ + } + + /* Otherwise unknown */ + + return 0; +} +#endif diff --git a/libc/wctype/lib_towlower.c b/libc/wctype/lib_towlower.c new file mode 100644 index 0000000000..0da9c37748 --- /dev/null +++ b/libc/wctype/lib_towlower.c @@ -0,0 +1,66 @@ +/**************************************************************************** + * libc/wchar/lib_towlower.c + * + * Copyright (c) 2002 Red Hat Incorporated. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * The name of Red Hat Incorporated may not be used to endorse + * or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#ifdef CONFIG_LIBC_WCHAR + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: towlower + * + * Description: + * The towlower() function is the wide-character equivalent of the + * tolower() function. If c is an uppercase wide character, and there + * exists a lowercase equivalent in the current locale, it returns the + * lowercase equivalent of c. This current code don't use locale. + * + ****************************************************************************/ + +wint_t towlower(wint_t c) +{ + return (c < (wint_t)0x00ff ? (wint_t)tolower((int)c) : c); +} +#endif diff --git a/libc/wctype/lib_towupper.c b/libc/wctype/lib_towupper.c new file mode 100644 index 0000000000..ee86a56dad --- /dev/null +++ b/libc/wctype/lib_towupper.c @@ -0,0 +1,66 @@ +/**************************************************************************** + * libc/wchar/lib_towupper.c + * + * Copyright (c) 2002 Red Hat Incorporated. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * The name of Red Hat Incorporated may not be used to endorse + * or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#ifdef CONFIG_LIBC_WCHAR + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: towupper + * + * Description: + * The towupper() function is the wide-character equivalent of the + * toupper() function. If c is an lowercase wide character, and there + * exists a uppercase equivalent in the current locale, it returns the + * uppercase equivalent of c. This current code don't use locale. + * + ****************************************************************************/ + +wint_t towupper(wint_t c) +{ + return (c < (wint_t)0x00ff ? (wint_t)toupper((int)c) : c); +} +#endif diff --git a/libc/wctype/lib_wctype.c b/libc/wctype/lib_wctype.c index 8ba10f06f7..99df9453ad 100644 --- a/libc/wctype/lib_wctype.c +++ b/libc/wctype/lib_wctype.c @@ -35,6 +35,8 @@ * Included Files ****************************************************************************/ +#include + #include #include #include -- GitLab From 54fd0f0a041ecaf569e65a0638ddf6cd9ba003d4 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 19 Oct 2016 08:18:46 -0600 Subject: [PATCH 131/734] Fix a few more compile issues with the new wide character support --- include/stdlib.h | 1 - include/sys/types.h | 4 +- include/wchar.h | 116 +++++++++++++++++++-------------------- include/wctype.h | 10 +--- libc/wchar/lib_wcsxfrm.c | 1 + libc/wchar/lib_wmemchr.c | 3 +- libc/wchar/lib_wmemcpy.c | 3 +- 7 files changed, 65 insertions(+), 73 deletions(-) diff --git a/include/stdlib.h b/include/stdlib.h index ddfcea74a8..83eb7dd886 100644 --- a/include/stdlib.h +++ b/include/stdlib.h @@ -45,7 +45,6 @@ #include #include -#include /**************************************************************************** * Pre-processor Definitions diff --git a/include/sys/types.h b/include/sys/types.h index a818cc2a80..ed82645e7d 100644 --- a/include/sys/types.h +++ b/include/sys/types.h @@ -191,6 +191,7 @@ typedef int16_t key_t; typedef intptr_t ptrdiff_t; +#ifndef CONFIG_WCHAR_BUILTIN /* Wide, 16-bit character types. wchar_t is a built-in type in C++ and * its declaration here may cause compilation errors on some compilers * if -DCONFIG_WCHAR_BUILTIN is not included in the CXXFLAGS. @@ -198,7 +199,6 @@ typedef intptr_t ptrdiff_t; * REVISIT: wchar_t belongs in stddef.h */ -#ifndef CONFIG_WCHAR_BUILTIN typedef uint16_t wchar_t; #endif @@ -215,9 +215,9 @@ typedef uint32_t blkcnt_t; typedef int32_t off_t; typedef off_t fpos_t; +#ifdef CONFIG_HAVE_LONG_LONG /* Large file versions */ -#ifdef CONFIG_HAVE_LONG_LONG typedef int64_t off64_t; typedef int64_t fpos64_t; #endif diff --git a/include/wchar.h b/include/wchar.h index 7fd721d7ef..11cad2415b 100644 --- a/include/wchar.h +++ b/include/wchar.h @@ -33,6 +33,9 @@ * ****************************************************************************/ +#ifndef __INCLUDE_WCHAR_H +#define __INCLUDE_WCHAR_H + /**************************************************************************** * Included Files ****************************************************************************/ @@ -47,14 +50,6 @@ #include #include -/* REVISIT: Moving the idempotence to this location resolves a circular - * dependency problem with stdlib.h which gets included indirectly and - * needs wchar_t. - */ - -#ifndef __INCLUDE_WCHAR_H -#define __INCLUDE_WCHAR_H - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -101,10 +96,11 @@ typedef int wint_t; /* wctype_t * A scalar type of a data object that can hold values which represent * locale-specific character classification. - * - * Ddefined in wctype.h. Should be defined here. - * - * mbstate_t + */ + +typedef int wctype_t; + +/* mbstate_t * An object type other than an array type that can hold the conversion * state information necessary to convert between sequences of (possibly * multibyte) characters and wide-characters. If a codeset is being used @@ -158,10 +154,9 @@ extern "C" * Reference: Opengroup.org */ -#if 0 /* Not yet implemented */ wint_t btowc(int); -int fwprintf(FILE *, const wchar_t *, ...); -int fwscanf(FILE *, const wchar_t *, ...); +int fwprintf(FILE *, FAR const wchar_t *, ...); +int fwscanf(FILE *, FAR const wchar_t *, ...); int iswalnum(wint_t); int iswalpha(wint_t); int iswcntrl(wint_t); @@ -175,68 +170,67 @@ int iswupper(wint_t); int iswxdigit(wint_t); int iswctype(wint_t, wctype_t); wint_t fgetwc(FILE *); -wchar_t *fgetws(wchar_t *, int, FILE *); +FAR wchar_t *fgetws(wchar_t *, int, FILE *); wint_t fputwc(wchar_t, FILE *); -int fputws(const wchar_t *, FILE *); +int fputws(FAR const wchar_t *, FILE *); int fwide(FILE *, int); wint_t getwc(FILE *); wint_t getwchar(void); -int mbsinit(const mbstate_t *); -size_t mbrlen(const char *, size_t, mbstate_t *); -size_t mbrtowc(wchar_t *, const char *, size_t, +int mbsinit(FAR const mbstate_t *); +size_t mbrlen(FAR const char *, size_t, FAR mbstate_t *); +size_t mbrtowc(wchar_t *, FAR const char *, size_t, mbstate_t *); -size_t mbsrtowcs(wchar_t *, const char **, size_t, +size_t mbsrtowcs(wchar_t *, FAR const char **, size_t, mbstate_t *); wint_t putwc(wchar_t, FILE *); wint_t putwchar(wchar_t); -int swprintf(wchar_t *, size_t, const wchar_t *, ...); -int swscanf(const wchar_t *, const wchar_t *, ...); +int swprintf(FAR wchar_t *, size_t, FAR const wchar_t *, ...); +int swscanf(FAR const wchar_t *, FAR const wchar_t *, ...); wint_t towlower(wint_t); wint_t towupper(wint_t); wint_t ungetwc(wint_t, FILE *); -int vfwprintf(FILE *, const wchar_t *, va_list); -int vwprintf(const wchar_t *, va_list); -int vswprintf(wchar_t *, size_t, const wchar_t *, +int vfwprintf(FILE *, FAR const wchar_t *, va_list); +int vwprintf(FAR const wchar_t *, va_list); +int vswprintf(wchar_t *, size_t, FAR const wchar_t *, va_list); -size_t wcrtomb(char *, wchar_t, mbstate_t *); -wchar_t *wcscat(wchar_t *, const wchar_t *); -wchar_t *wcschr(const wchar_t *, wchar_t); -int wcscmp(const wchar_t *, const wchar_t *); -int wcscoll(const wchar_t *, const wchar_t *); -wchar_t *wcscpy(wchar_t *, const wchar_t *); -size_t wcscspn(const wchar_t *, const wchar_t *); -size_t wcsftime(wchar_t *, size_t, const wchar_t *, - const struct tm *); -size_t wcslen(const wchar_t *); +size_t wcrtomb(FAR char *, wchar_t, FAR mbstate_t *); +FAR wchar_t *wcscat(FAR wchar_t *, FAR const wchar_t *); +FAR wchar_t *wcschr(FAR const wchar_t *, wchar_t); +int wcscmp(FAR const wchar_t *, FAR const wchar_t *); +int wcscoll(FAR const wchar_t *, FAR const wchar_t *); +FAR wchar_t *wcscpy(FAR wchar_t *, FAR const wchar_t *); +size_t wcscspn(FAR const wchar_t *, FAR const wchar_t *); +size_t wcsftime(FAR wchar_t *, size_t, FAR const wchar_t *, + FAR const struct tm *); +size_t wcslen(FAR const wchar_t *); size_t wcslcpy(FAR wchar_t *, FAR const wchar_t *, size_t); size_t wcslcat(FAR wchar_t *, FAR const wchar_t *, size_t); -wchar_t *wcsncat(wchar_t *, const wchar_t *, size_t); -int wcsncmp(const wchar_t *, const wchar_t *, size_t); -wchar_t *wcsncpy(wchar_t *, const wchar_t *, size_t); -wchar_t *wcspbrk(const wchar_t *, const wchar_t *); -wchar_t *wcsrchr(const wchar_t *, wchar_t); -size_t wcsrtombs(char *, const wchar_t **, size_t, - mbstate_t *); -size_t wcsspn(const wchar_t *, const wchar_t *); -wchar_t *wcsstr(const wchar_t *, const wchar_t *); -double wcstod(const wchar_t *, wchar_t **); -wchar_t *wcstok(wchar_t *, const wchar_t *, wchar_t **); -long int wcstol(const wchar_t *, wchar_t **, int); -unsigned long int wcstoul(const wchar_t *, wchar_t **, int); -wchar_t *wcswcs(const wchar_t *, const wchar_t *); -int wcswidth(const wchar_t *, size_t); -size_t wcsxfrm(wchar_t *, const wchar_t *, size_t); +FAR wchar_t *wcsncat(FAR wchar_t *, FAR const wchar_t *, size_t); +int wcsncmp(FAR const wchar_t *, FAR const wchar_t *, size_t); +FAR wchar_t *wcsncpy(FAR wchar_t *, FAR const wchar_t *, size_t); +FAR wchar_t *wcspbrk(FAR const wchar_t *, FAR const wchar_t *); +FAR wchar_t *wcsrchr(FAR const wchar_t *, wchar_t); +size_t wcsrtombs(FAR char *, FAR const wchar_t **, size_t, + FAR mbstate_t *); +size_t wcsspn(FAR const wchar_t *, FAR const wchar_t *); +FAR wchar_t *wcsstr(FAR const wchar_t *, FAR const wchar_t *); +double wcstod(FAR const wchar_t *, FAR wchar_t **); +FAR wchar_t *wcstok(FAR wchar_t *, FAR const wchar_t *, FAR wchar_t **); +long int wcstol(FAR const wchar_t *, FAR wchar_t **, int); +unsigned long int wcstoul(FAR const wchar_t *, FAR wchar_t **, int); +FAR wchar_t *wcswcs(FAR const wchar_t *, FAR const wchar_t *); +int wcswidth(FAR const wchar_t *, size_t); +size_t wcsxfrm(wchar_t *, FAR const wchar_t *, size_t); int wctob(wint_t); -wctype_t wctype(const char *); +wctype_t wctype(FAR const char *); int wcwidth(wchar_t); -wchar_t *wmemchr(const wchar_t *, wchar_t, size_t); -int wmemcmp(const wchar_t *, const wchar_t *, size_t); -wchar_t *wmemcpy(wchar_t *, const wchar_t *, size_t); -wchar_t *wmemmove(wchar_t *, const wchar_t *, size_t); -wchar_t *wmemset(wchar_t *, wchar_t, size_t); -int wprintf(const wchar_t *, ...); -int wscanf(const wchar_t *, ...); -#endif +FAR wchar_t *wmemchr(FAR const wchar_t *, wchar_t, size_t); +int wmemcmp(FAR const wchar_t *, FAR const wchar_t *, size_t); +FAR wchar_t *wmemcpy(FAR wchar_t *, FAR const wchar_t *, size_t); +FAR wchar_t *wmemmove(FAR wchar_t *, FAR const wchar_t *, size_t); +FAR wchar_t *wmemset(FAR wchar_t *, wchar_t, size_t); +int wprintf(FAR const wchar_t *, ...); +int wscanf(FAR const wchar_t *, ...); #undef EXTERN #ifdef __cplusplus diff --git a/include/wctype.h b/include/wctype.h index 780fb67c7c..fac596eae1 100644 --- a/include/wctype.h +++ b/include/wctype.h @@ -71,15 +71,11 @@ * Public Types ****************************************************************************/ -#ifndef _WCTYPE_T -# define _WCTYPE_T -typedef int wctype_t; -#endif +/* A scalar type that can hold values which represent locale-specific + * character mappings. + */ -#ifndef _WCTRANS_T -# define _WCTRANS_T typedef int wctrans_t; -#endif /**************************************************************************** * Public Function Prototypes diff --git a/libc/wchar/lib_wcsxfrm.c b/libc/wchar/lib_wcsxfrm.c index b083eaf013..e35ea8ff60 100644 --- a/libc/wchar/lib_wcsxfrm.c +++ b/libc/wchar/lib_wcsxfrm.c @@ -34,6 +34,7 @@ #include +#include #include #include diff --git a/libc/wchar/lib_wmemchr.c b/libc/wchar/lib_wmemchr.c index 4f3e6073cb..d648146a6a 100644 --- a/libc/wchar/lib_wmemchr.c +++ b/libc/wchar/lib_wmemchr.c @@ -33,6 +33,7 @@ ****************************************************************************/ #include + #include #include @@ -52,7 +53,7 @@ * ****************************************************************************/ -FAR wchar_t *wmemchr(FAR wchar_t *s, wchar_t c, size_t n) +FAR wchar_t *wmemchr(FAR const wchar_t *s, wchar_t c, size_t n) { size_t i; diff --git a/libc/wchar/lib_wmemcpy.c b/libc/wchar/lib_wmemcpy.c index 8441ae70b2..96f12c62c0 100644 --- a/libc/wchar/lib_wmemcpy.c +++ b/libc/wchar/lib_wmemcpy.c @@ -33,6 +33,7 @@ ****************************************************************************/ #include + #include #include @@ -52,7 +53,7 @@ * ****************************************************************************/ -FAR wchar_t *wmemcpy(FAR wchar_t *d, FAR wchar_t *s, size_t n) +FAR wchar_t *wmemcpy(FAR wchar_t *d, FAR const wchar_t *s, size_t n) { return (FAR wchar_t *) memcpy(d, s, n * sizeof(wchar_t)); } -- GitLab From 77e5115e233b10bfbd7e04a19850e505251fd662 Mon Sep 17 00:00:00 2001 From: Max Kriegleder Date: Wed, 19 Oct 2016 08:27:20 -0600 Subject: [PATCH 132/734] syslog: Fixes required for file syslog output --- drivers/syslog/syslog.h | 4 ++-- drivers/syslog/syslog_filechannel.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/syslog/syslog.h b/drivers/syslog/syslog.h index 3ebb480f00..67aedbb9f1 100644 --- a/drivers/syslog/syslog.h +++ b/drivers/syslog/syslog.h @@ -61,10 +61,10 @@ extern "C" /* The default SYSLOG channel */ struct syslog_channel_s; /* Forward reference */ -EXTERN const struct syslog_channel_s g_default_syslog_channel; +EXTERN const struct syslog_channel_s g_default_channel; /* This is the current syslog channel in use. It initially points to - * g_default_syslog_channel. + * g_default_channel. */ EXTERN FAR const struct syslog_channel_s *g_syslog_channel; diff --git a/drivers/syslog/syslog_filechannel.c b/drivers/syslog/syslog_filechannel.c index 3f2f7d7df1..efd5e541b3 100644 --- a/drivers/syslog/syslog_filechannel.c +++ b/drivers/syslog/syslog_filechannel.c @@ -149,7 +149,7 @@ int syslog_file_channel(FAR const char *devpath) sched_lock(); saved_channel = g_syslog_channel; - ret = syslog_channel(&g_default_syslog_channel); + ret = syslog_channel(&g_default_channel); if (ret < 0) { goto errout_with_lock; -- GitLab From c719a32a40973eb4651d8001c6e0d479c1cc12a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Maciej=20W=C3=B3jcik?= Date: Wed, 19 Oct 2016 16:34:07 +0200 Subject: [PATCH 133/734] add tim8 to stm32f103v pinmap --- arch/arm/src/stm32/chip/stm32f103v_pinmap.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/src/stm32/chip/stm32f103v_pinmap.h b/arch/arm/src/stm32/chip/stm32f103v_pinmap.h index 61895a74e9..17492579f7 100644 --- a/arch/arm/src/stm32/chip/stm32f103v_pinmap.h +++ b/arch/arm/src/stm32/chip/stm32f103v_pinmap.h @@ -341,6 +341,20 @@ #define GPIO_TIM5_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3) #define GPIO_TIM5_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3) +#define GPIO_TIM8_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0) +#define GPIO_TIM8_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM8_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6) +#define GPIO_TIM8_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM8_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7) +#define GPIO_TIM8_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM8_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8) +#define GPIO_TIM8_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM8_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9) +#define GPIO_TIM8_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6) +#define GPIO_TIM8_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM8_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM8_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1) + #if 0 /* Needs further investigation */ #define GPIO_TRACECK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN2) #define GPIO_TRACED0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN3) -- GitLab From 841e1aa77f45ec49251c146047fd8898822f82ff Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 19 Oct 2016 09:14:21 -0600 Subject: [PATCH 134/734] Fix a cloned typo --- arch/arm/src/armv7-a/arm_testset.S | 2 +- arch/arm/src/armv7-m/gnu/up_testset.S | 2 +- arch/arm/src/armv7-m/iar/up_testset.S | 2 +- arch/arm/src/armv7-r/arm_testset.S | 2 +- arch/sim/src/up_testset.c | 2 +- include/nuttx/arch.h | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_testset.S b/arch/arm/src/armv7-a/arm_testset.S index 6d6cdcd4ac..e89cbb3adc 100644 --- a/arch/arm/src/armv7-a/arm_testset.S +++ b/arch/arm/src/armv7-a/arm_testset.S @@ -70,7 +70,7 @@ * Name: up_testset * * Description: - * Perform and atomic test and set operation on the provided spinlock. + * Perform an atomic test and set operation on the provided spinlock. * * This function must be provided via the architecture-specific logoic. * diff --git a/arch/arm/src/armv7-m/gnu/up_testset.S b/arch/arm/src/armv7-m/gnu/up_testset.S index 7dd45eee4d..c1888c56a9 100644 --- a/arch/arm/src/armv7-m/gnu/up_testset.S +++ b/arch/arm/src/armv7-m/gnu/up_testset.S @@ -72,7 +72,7 @@ * Name: up_testset * * Description: - * Perform and atomic test and set operation on the provided spinlock. + * Perform an atomic test and set operation on the provided spinlock. * * This function must be provided via the architecture-specific logoic. * diff --git a/arch/arm/src/armv7-m/iar/up_testset.S b/arch/arm/src/armv7-m/iar/up_testset.S index 9590e576e7..e690aed3de 100644 --- a/arch/arm/src/armv7-m/iar/up_testset.S +++ b/arch/arm/src/armv7-m/iar/up_testset.S @@ -57,7 +57,7 @@ * Name: up_testset * * Description: - * Perform and atomic test and set operation on the provided spinlock. + * Perform an atomic test and set operation on the provided spinlock. * * This function must be provided via the architecture-specific logoic. * diff --git a/arch/arm/src/armv7-r/arm_testset.S b/arch/arm/src/armv7-r/arm_testset.S index 7cd741fed7..f82837d5fe 100644 --- a/arch/arm/src/armv7-r/arm_testset.S +++ b/arch/arm/src/armv7-r/arm_testset.S @@ -70,7 +70,7 @@ * Name: up_testset * * Description: - * Perform and atomic test and set operation on the provided spinlock. + * Perform an atomic test and set operation on the provided spinlock. * * This function must be provided via the architecture-specific logoic. * diff --git a/arch/sim/src/up_testset.c b/arch/sim/src/up_testset.c index 30cb64c0ef..d1b754bca0 100644 --- a/arch/sim/src/up_testset.c +++ b/arch/sim/src/up_testset.c @@ -71,7 +71,7 @@ static pthread_mutex_t g_tsmutex = PTHREAD_MUTEX_INITIALIZER; * Name: up_testset * * Description: - * Perform and atomic test and set operation on the provided spinlock. + * Perform an atomic test and set operation on the provided spinlock. * * This function must be provided via the architecture-specific logoic. * diff --git a/include/nuttx/arch.h b/include/nuttx/arch.h index c1eacf0bd9..1ef8efe4b1 100644 --- a/include/nuttx/arch.h +++ b/include/nuttx/arch.h @@ -1689,7 +1689,7 @@ int up_timer_start(FAR const struct timespec *ts); * Name: up_testset * * Description: - * Perform and atomic test and set operation on the provided spinlock. + * Perform an atomic test and set operation on the provided spinlock. * * Input Parameters: * lock - The address of spinlock object. -- GitLab From 29c3acdc4ead66216d27c74f6bddd119f807ecda Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 19 Oct 2016 09:58:12 -0600 Subject: [PATCH 135/734] Add xtensa_testset.c --- arch/arm/include/spinlock.h | 2 +- arch/xtensa/src/common/xtensa_createstack.c | 8 -- arch/xtensa/src/common/xtensa_testset.c | 141 ++++++++++++++++++++ arch/xtensa/src/common/xtensa_usestack.c | 8 -- arch/xtensa/src/esp32/Make.defs | 3 + include/nuttx/spinlock.h | 2 +- 6 files changed, 146 insertions(+), 18 deletions(-) create mode 100644 arch/xtensa/src/common/xtensa_testset.c diff --git a/arch/arm/include/spinlock.h b/arch/arm/include/spinlock.h index fbd0e42438..44e405e630 100644 --- a/arch/arm/include/spinlock.h +++ b/arch/arm/include/spinlock.h @@ -82,7 +82,7 @@ typedef uint8_t spinlock_t; * Name: up_testset * * Description: - * Perform and atomic test and set operation on the provided spinlock. + * Perform an atomic test and set operation on the provided spinlock. * * This function must be provided via the architecture-specific logoic. * diff --git a/arch/xtensa/src/common/xtensa_createstack.c b/arch/xtensa/src/common/xtensa_createstack.c index d4769f33d0..5e1ca5a447 100644 --- a/arch/xtensa/src/common/xtensa_createstack.c +++ b/arch/xtensa/src/common/xtensa_createstack.c @@ -71,14 +71,6 @@ #define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK) #define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK) -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/xtensa/src/common/xtensa_testset.c b/arch/xtensa/src/common/xtensa_testset.c new file mode 100644 index 0000000000..b4b3baa0fb --- /dev/null +++ b/arch/xtensa/src/common/xtensa_testset.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_testset.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "xtensa.h" + +#ifdef CONFIG_SPINLOCK + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_compareset + * + * Description: + * Wrapper for the Xtensa compare-and-set instruction. This function will + * atomically compare *addr to compare, and if it's the same, will set + * *addr to set. It will return the old value of *addr. + * + * Warning: From the ISA docs: in some (unspecified) cases, the s32c1i + * instruction may return the *bitwise inverse* of the old mem if the + * mem wasn't written. This doesn't seem to happen on the ESP32, though. + * (Would show up directly if it did because the magic wouldn't match.) + * + ****************************************************************************/ + +static inline uint32_t xtensa_compareset(FAR volatile uint32_t *addr, + uint32_t compare, + uint32_t set) +{ + __asm__ __volatile__ + ( + "WSR %2, SCOMPARE1\n" /* Initialize SCOMPARE1 */ + "ISYNC\n" /* Wait sync */ + "S32C1I %0, %1, 0\n" /* Store id into the lock, if the lock is the + * same as comparel. Otherwise, no write-access */ + : "=r"(set) : "r"(addr), "r"(compare), "0"(set) + ); + + return set; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_testset + * + * Description: + * Perform an atomic test and set operation on the provided spinlock. + * + * This function must be provided via the architecture-specific logoic. + * + * Input Parameters: + * lock - The address of spinlock object. + * + * Returned Value: + * The spinlock is always locked upon return. The value of previous value + * of the spinlock variable is returned, either SP_LOCKED if the spinlock + * was previously locked (meaning that the test-and-set operation failed to + * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked + * (meaning that we successfully obtained the lock) + * + ****************************************************************************/ + +spinlock_t up_testset(volatile FAR spinlock_t *lock) +{ + spinlock_t prev; + + /* Perform the 32-bit compare and set operation */ + + prev = xtensa_compareset((FAR volatile uint32_t *)lock, + SP_UNLOCKED, SP_LOCKED); + + /* xtensa_compareset() should return either SP_UNLOCKED if the spinlock + * was locked or SP_LOCKED or possibly ~SP_UNLOCKED if the spinlock was + * not locked: + * + * "In the RE-2013.0 release and after, there is a slight change in the + * semantics of the S32C1I instruction. Nothing is changed about the + * operation on memory. In rare cases the resulting value in register + * at can be different in this and later releases. The rule still holds + * that memory has been written if and only if the register result + * equals SCOMPARE1. + * + * "The difference is that in some cases where memory has not been + * written, the instruction returns ~SCOMPARE1 instead of the current + * value of memory. Although this change can, in principle, affect + * the operation of code, scanning all internal Cadence code produced + * no examples where this change would change the operation of the + * code." + * + * In any case, the return value of SP_UNLOCKED can be trusted and will + * always mean that the the spinlock was set. + */ + + return (prev == SP_UNLOCKED) ? SP_UNLOCKED : SP_LOCKED; +} diff --git a/arch/xtensa/src/common/xtensa_usestack.c b/arch/xtensa/src/common/xtensa_usestack.c index 679deffb1f..0b5db031e9 100644 --- a/arch/xtensa/src/common/xtensa_usestack.c +++ b/arch/xtensa/src/common/xtensa_usestack.c @@ -69,14 +69,6 @@ #define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK) #define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK) -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 804a539c6a..c7114c4adf 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -55,6 +55,9 @@ ifeq ($(CONFIG_DEBUG_ALERT),y) CMN_CSRCS += xtensa_dumpstate.c endif +ifeq ($(CONFIG_SPINLOCK),y) + CMN_CSRCS += xtensa_testset.c +endif # Use of common/xtensa_etherstub.c is deprecated. The preferred mechanism # is to use CONFIG_NETDEV_LATEINIT=y to suppress the call to diff --git a/include/nuttx/spinlock.h b/include/nuttx/spinlock.h index 544facfef9..c749d9e329 100644 --- a/include/nuttx/spinlock.h +++ b/include/nuttx/spinlock.h @@ -83,7 +83,7 @@ struct spinlock_s * Name: up_testset * * Description: - * Perform and atomic test and set operation on the provided spinlock. + * Perform an atomic test and set operation on the provided spinlock. * * This function must be provided via the architecture-specific logoic. * -- GitLab From 31d5acc8a777152dd89813ebff4b93676503a90e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 19 Oct 2016 10:06:07 -0600 Subject: [PATCH 136/734] Forgot to add a file before the last commit --- arch/xtensa/include/spinlock.h | 99 ++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 arch/xtensa/include/spinlock.h diff --git a/arch/xtensa/include/spinlock.h b/arch/xtensa/include/spinlock.h new file mode 100644 index 0000000000..9d0ef213d0 --- /dev/null +++ b/arch/xtensa/include/spinlock.h @@ -0,0 +1,99 @@ +/**************************************************************************** + * arch/xtensa/include/spinlock.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_SPINLOCK_H +#define __ARCH_ARM_INCLUDE_SPINLOCK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SP_UNLOCKED 0 /* The Un-locked state */ +#define SP_LOCKED 1 /* The Locked state */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* The Type of a spinlock. + * + * This must be a uint32_ becaue it will be set using S32C1I instruction. + * That instruction atomically stores to a memory location only if its + * current value is the expected one. The state register (SCOMPARE1) is + * used to provide the additional comparison operand. Some implementations + * also have a state register (ATOMCTL) for further control of the atomic + * operation in cache and on the PIF bus. + */ + +typedef uint32_t spinlock_t; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_testset + * + * Description: + * Perform an atomic test and set operation on the provided spinlock. + * + * This function must be provided via the architecture-specific logoic. + * + * Input Parameters: + * lock - The address of spinlock object. + * + * Returned Value: + * The spinlock is always locked upon return. The value of previous value + * of the spinlock variable is returned, either SP_LOCKED if the spinlock + * as previously locked (meaning that the test-and-set operation failed to + * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked + * (meaning that we successfully obtained the lock) + * + ****************************************************************************/ + +/* See prototype in nuttx/include/nuttx/spinlock.h */ + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_INCLUDE_SPINLOCK_H */ -- GitLab From 48fb97e7b542931a398f41ac1132e68a6767117a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 19 Oct 2016 10:07:44 -0600 Subject: [PATCH 137/734] More of the same cloned typo --- arch/arm/include/spinlock.h | 2 +- arch/sim/include/spinlock.h | 2 +- include/nuttx/spinlock.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/spinlock.h b/arch/arm/include/spinlock.h index fbd0e42438..44e405e630 100644 --- a/arch/arm/include/spinlock.h +++ b/arch/arm/include/spinlock.h @@ -82,7 +82,7 @@ typedef uint8_t spinlock_t; * Name: up_testset * * Description: - * Perform and atomic test and set operation on the provided spinlock. + * Perform an atomic test and set operation on the provided spinlock. * * This function must be provided via the architecture-specific logoic. * diff --git a/arch/sim/include/spinlock.h b/arch/sim/include/spinlock.h index 3c20ffe22a..350bf24b33 100644 --- a/arch/sim/include/spinlock.h +++ b/arch/sim/include/spinlock.h @@ -66,7 +66,7 @@ typedef bool spinlock_t; * Name: up_testset * * Description: - * Perform and atomic test and set operation on the provided spinlock. + * Perform an atomic test and set operation on the provided spinlock. * * This function must be provided via the architecture-specific logoic. * diff --git a/include/nuttx/spinlock.h b/include/nuttx/spinlock.h index 544facfef9..c749d9e329 100644 --- a/include/nuttx/spinlock.h +++ b/include/nuttx/spinlock.h @@ -83,7 +83,7 @@ struct spinlock_s * Name: up_testset * * Description: - * Perform and atomic test and set operation on the provided spinlock. + * Perform an atomic test and set operation on the provided spinlock. * * This function must be provided via the architecture-specific logoic. * -- GitLab From b1ed7910f008b82c202e31a24c3ef4e5bf41d5f6 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Wed, 19 Oct 2016 05:54:20 -1000 Subject: [PATCH 138/734] Allows c++ code to compile with or without CONFIG_LIBC_LOCALE and will generate a link error if CONFIG_LIBC_LOCALE is not defined and setlocale is referneced. With CONFIG_LIBC_LOCALE defined setlocale will act as if MB string is not supported and return "C" for POSIX. C and "" --- include/cxx/clocale | 3 +-- include/locale.h | 3 --- libc/locale/lib_setlocale.c | 5 +++-- 3 files changed, 4 insertions(+), 7 deletions(-) diff --git a/include/cxx/clocale b/include/cxx/clocale index 39d691e484..154bf8040a 100644 --- a/include/cxx/clocale +++ b/include/cxx/clocale @@ -46,11 +46,10 @@ // Namespace //*************************************************************************** -#ifdef CONFIG_LIBC_LOCALE namespace std { using ::setlocale; + using ::localeconv; } -#endif #endif // __INCLUDE_CXX_CLOCALE diff --git a/include/locale.h b/include/locale.h index 501990dbaa..16923e4a3d 100644 --- a/include/locale.h +++ b/include/locale.h @@ -43,8 +43,6 @@ #include #include -#ifdef CONFIG_LIBC_LOCALE - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -109,5 +107,4 @@ FAR struct lconv *localeconv(void); } #endif -#endif /* CONFIG_LIBC_LOCALE */ #endif /* __INCLUDE_LOCALE_H */ diff --git a/libc/locale/lib_setlocale.c b/libc/locale/lib_setlocale.c index 335eda84e4..fbd621a110 100644 --- a/libc/locale/lib_setlocale.c +++ b/libc/locale/lib_setlocale.c @@ -43,6 +43,7 @@ #include #ifdef CONFIG_LIBC_LOCALE +#include /**************************************************************************** * Public Functions @@ -62,8 +63,8 @@ FAR char *setlocale(int category, FAR const char *locale) { - /* NULL indicates the the locale was not changed */ - return NULL; + return ((strcmp (locale, "POSIX") == 0 || strcmp (locale, "C") == 0 || + strcmp (locale, "") == 0) ? "C" : NULL); } #endif -- GitLab From 291c49afc32fe64c61fc4e475e6cc67e9f396267 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 19 Oct 2016 11:28:42 -0600 Subject: [PATCH 139/734] Xtensa/ESP32: Move some ESP32-specific macros from xtensa_macros.h to chip_macros.h --- arch/xtensa/src/common/xtensa_macros.h | 18 +------ arch/xtensa/src/esp32/chip_macros.h | 65 ++++++++++++++++++++++++++ 2 files changed, 66 insertions(+), 17 deletions(-) create mode 100644 arch/xtensa/src/esp32/chip_macros.h diff --git a/arch/xtensa/src/common/xtensa_macros.h b/arch/xtensa/src/common/xtensa_macros.h index d988386059..3e8952be88 100644 --- a/arch/xtensa/src/common/xtensa_macros.h +++ b/arch/xtensa/src/common/xtensa_macros.h @@ -38,29 +38,13 @@ ****************************************************************************/ #include +#include chip_macros.h" /**************************************************************************** * Assembly Language Macros ****************************************************************************/ #ifdef __ASSEMBLY__ - -/* Macro to get the current core ID. Only uses the reg given as an argument. - * Reading PRID on the ESP108 architecture gives us 0xcdcd on the PRO - * processor and 0xabab on the APP CPU. We distinguish between the two by - * simply checking bit 1: it's 1 on the APP and 0 on the PRO processor. - */ - - .macro getcoreid reg - rsr.prid \reg - bbci \reg,1,1f - movi \reg,1 - j 2f -1: - movi \reg,0 -2: - .endm - /* Macros to handle ABI specifics of function entry and return. * * Convenient where the frame size requirements are the same for both ABIs. diff --git a/arch/xtensa/src/esp32/chip_macros.h b/arch/xtensa/src/esp32/chip_macros.h new file mode 100644 index 0000000000..8b3530cc26 --- /dev/null +++ b/arch/xtensa/src/esp32/chip_macros.h @@ -0,0 +1,65 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/chip_macros.h + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * + * Copyright (c) 2006-2015 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_MACROS_H +#define __ARCH_XTENSA_SRC_ESP32_CHIP_MACROS_H 1 + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Assembly Language Macros + ****************************************************************************/ + +#ifdef __ASSEMBLY__ + +/* Macro to get the current core ID. Only uses the reg given as an argument. + * Reading PRID on the ESP108 architecture gives us 0xcdcd on the PRO + * processor and 0xabab on the APP CPU. We distinguish between the two by + * simply checking bit 1: it's 1 on the APP and 0 on the PRO processor. + */ + + .macro getcoreid reg + rsr.prid \reg + bbci \reg, 1, 1f + movi \reg, 1 + j 2f +1: + movi \reg, 0 +2: + .endm + +#endif /* __ASSEMBLY */ +#endif /* __ARCH_XTENSA_SRC_ESP32_CHIP_MACROS_H */ -- GitLab From 97b324073754acf1763d7a79c746a6b3a587ad9c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 19 Oct 2016 11:50:19 -0600 Subject: [PATCH 140/734] Minor changes from review of last PR --- libc/locale/lib_setlocale.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/libc/locale/lib_setlocale.c b/libc/locale/lib_setlocale.c index fbd621a110..e5b576508d 100644 --- a/libc/locale/lib_setlocale.c +++ b/libc/locale/lib_setlocale.c @@ -40,10 +40,10 @@ #include #include +#include #include #ifdef CONFIG_LIBC_LOCALE -#include /**************************************************************************** * Public Functions @@ -63,8 +63,7 @@ FAR char *setlocale(int category, FAR const char *locale) { - - return ((strcmp (locale, "POSIX") == 0 || strcmp (locale, "C") == 0 || - strcmp (locale, "") == 0) ? "C" : NULL); + return ((strcmp(locale, "POSIX") == 0 || strcmp(locale, "C") == 0 || + strcmp(locale, "") == 0) ? "C" : NULL); } #endif -- GitLab From d1562a18e6de6ca3d65af07e3496b4b059f658fa Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 19 Oct 2016 13:58:51 -0600 Subject: [PATCH 141/734] Add vectors for interrupt levels 2-6 --- arch/xtensa/Kconfig | 8 ++ arch/xtensa/src/common/xtensa_context.S | 16 +-- arch/xtensa/src/common/xtensa_vectors.S | 156 +++++++++++++++++++++ arch/xtensa/src/esp32/Make.defs | 2 +- configs/esp32-core/scripts/esp32_common.ld | 8 +- configs/esp32-core/scripts/esp32_rom.ld | 16 +-- 6 files changed, 185 insertions(+), 21 deletions(-) create mode 100644 arch/xtensa/src/common/xtensa_vectors.S diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 2ff92ee1bc..a028ee2ec1 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -35,6 +35,14 @@ config XTENSA_NCOPROCESSORS int "Number of co-processors" default 1 +config XTENSA_INT_NLEVELS + int "Number of interrupt levels" + default 5 + +config XTENSA_EXCM_LEVEL + int "Level masked by PS.EXCM" + default 3 + config XTENSA_HAVE_LOOPS bool "Zero overhead loops" default n diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index 407b78690c..96dd333848 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -31,7 +31,7 @@ * ****************************************************************************/ -/* XTENSA CONTEXT SAVE AND RESTORE ROUTINES +/* XTENSA CONTEXT SAVE AND RESTORE ROUTINES * * Low-level Call0 functions for handling generic context save and restore of * registers not specifically addressed by the interrupt vectors and handlers. @@ -160,7 +160,7 @@ _xtensa_context_save: /* To spill the reg windows, temp. need pre-interrupt stack ptr and * a4-15. Need to save a9,12,13 temporarily (in frame temps) and * recover originals. Interrupts need to be disabled below - * XCHAL_EXCM_LEVEL and window overflow and underflow exceptions + * CONFIG_XTENSA_EXCM_LEVEL and window overflow and underflow exceptions * disabled (assured by PS.EXCM == 1). */ @@ -373,7 +373,7 @@ _xt_coproc_init: movi a2, _xt_coproc_owner_sa /* a2 = base of owner array */ addi a3, a2, (XCHAL_CP_MAX*portNUM_PROCESSORS) << 2 /* a3 = top+1 of owner array */ movi a4, 0 /* a4 = 0 (unowned) */ -1: s32i a4, a2, 0 +1: s32i a4, a2, 0 addi a2, a2, 4 bltu a2, a3, 1b @@ -424,15 +424,15 @@ _xt_coproc_release: addi a4, a3, XCHAL_CP_MAX << 2 /* a4 = top+1 of owner array */ movi a5, 0 /* a5 = 0 (unowned) */ - rsil a6, XCHAL_EXCM_LEVEL /* lock interrupts */ + rsil a6, CONFIG_XTENSA_EXCM_LEVEL /* Lock interrupts */ -1: l32i a7, a3, 0 /* a7 = owner at a3 */ +1: l32i a7, a3, 0 /* a7 = owner at a3 */ bne a2, a7, 2f /* if (coproc_sa_base == owner) */ s32i a5, a3, 0 /* owner = unowned */ -2: addi a3, a3, 1<<2 /* a3 = next entry in owner array */ - bltu a3, a4, 1b /* repeat until end of array */ +2: addi a3, a3, 1 << 2 /* a3 = next entry in owner array */ + bltu a3, a4, 1b /* Repeat until end of array */ -3: wsr a6, PS /* restore interrupts */ +3: wsr a6, PS /* Restore interrupts */ RET0 #endif diff --git a/arch/xtensa/src/common/xtensa_vectors.S b/arch/xtensa/src/common/xtensa_vectors.S new file mode 100644 index 0000000000..6af479677c --- /dev/null +++ b/arch/xtensa/src/common/xtensa_vectors.S @@ -0,0 +1,156 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_vectors.S + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * + * Copyright (c) 2006-2015 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + ****************************************************************************/ + + .file "xtensa_vectors.S" + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "xtensa_specregs.h" +#include "xtensa_macros.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * C Prototype: + * void _xtensa_levelN_vector(void) + * + * Description: + * Xtensa interrupt vectors. Each vector goes at a predetermined location + * according to the Xtensa hardware configuration, which is ensured by its + * placement in a special section known to the NuttX linker script. The + * vector logic performs the minimum necessary operations before jumping + * to the handler. + * + ****************************************************************************/ + +#if CONFIG_XTENSA_EXCM_LEVEL >= 2 + .begin literal_prefix .xtensa_level2_vector + .section .xtensa_level2_vector.text, "ax" + .global _xtensa_level2_vector + .global _xtensa_level2_handler + .type _xtensa_level2_vector, @function + .align 4 + +_xtensa_level2_vector: + wsr a0, EXCSAVE_2 /* Preserve a0 */ + call0 _xtensa_level2_handler /* Call level 2 interrupt handling */ + + /* Never returns here - call0 is used as a jump */ + + .end literal_prefix + + .size _xtensa_level2_vector, . - _xtensa_level2_vector +#endif + +#if CONFIG_XTENSA_EXCM_LEVEL >= 3 + .begin literal_prefix .xtensa_level3_vector + .section .xtensa_level3_vector.text, "ax" + .global _xtensa_level3_vector + .global _xtensa_level3_handler + .type _xtensa_level3_vector, @function + .align 4 + +_xtensa_level3_vector: + wsr a0, EXCSAVE_3 /* Preserve a0 */ + call0 _xtensa_level3_handler /* Call level 3 interrupt handling */ + + /* Never returns here - call0 is used as a jump */ + + .end literal_prefix + + .size _xtensa_level3_vector, . - _xtensa_level3_vector +#endif + +#if CONFIG_XTENSA_EXCM_LEVEL >= 4 + .begin literal_prefix .xtensa_level4_vector + .section .xtensa_level4_vector.text, "ax" + .global _xtensa_level4_vector + .global _xtensa_level4_handler + .type _xtensa_level4_vector, @function + .align 4 + +_xtensa_level4_vector: + wsr a0, EXCSAVE_4 /* Preserve a0 */ + call0 _xtensa_level4_handler /* Call level 5 interrupt handling */ + + /* Never returns here - call0 is used as a jump */ + + .end literal_prefix + + .size _xtensa_level5_vector, . - _xtensa_level5_vector +#endif + +#if CONFIG_XTENSA_EXCM_LEVEL >= 5 + .begin literal_prefix .xtensa_level5_vector + .section .xtensa_level5_vector.text, "ax" + .global _xtensa_level5_vector + .global _xtensa_level5_handler + .type _xtensa_level5_vector, @function + .align 4 + +_xtensa_level5_vector: + wsr a0, EXCSAVE_5 /* Preserve a0 */ + call0 _xtensa_level5_handler /* Call level 5 interrupt handling */ + + /* Never returns here - call0 is used as a jump */ + + .end literal_prefix + + .size _xtensa_level5_vector, . - _xtensa_level5_vector +#endif + +#if CONFIG_XTENSA_EXCM_LEVEL >= 6 + .begin literal_prefix .xtensa_level6_vector + .section .xtensa_level6_vector.text, "ax" + .global _xtensa_level6_vector + .global _xtensa_level6_handler + .type _xtensa_level6_vector, @function + .align 4 + +_xtensa_level6_vector: + wsr a0, EXCSAVE_6 /* Preserve a0 */ + call0 _xtensa_level6_handler /* Call level 6 interrupt handling */ + + /* Never returns here - call0 is used as a jump */ + + .end literal_prefix + + .size _xtensa_level6_vector, . - _xtensa_level6_vector +#endif + + .end diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index c7114c4adf..b66af09c90 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -40,7 +40,7 @@ HEAD_CSRC = esp32_start.c # Common XTENSA files (arch/xtensa/src/common) -CMN_ASRCS = xtensa_irq.S +CMN_ASRCS = xtensa_irq.S xtensa_vectors.S CMN_CSRCS = xtensa_assert.c xtensa_copystate.c CMN_CSRCS += xtensa_createstack.c xtensa_exit.c xtensa_idle.c CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c diff --git a/configs/esp32-core/scripts/esp32_common.ld b/configs/esp32-core/scripts/esp32_common.ld index 8d7f49a48a..da7b74d510 100644 --- a/configs/esp32-core/scripts/esp32_common.ld +++ b/configs/esp32-core/scripts/esp32_common.ld @@ -21,13 +21,13 @@ SECTIONS . = 0x0; KEEP(*(.WindowVectors.text)); . = 0x180; - KEEP(*(.Level2InterruptVector.text)); + KEEP(*(.xtensa_level2_vector.text)); . = 0x1c0; - KEEP(*(.Level3InterruptVector.text)); + KEEP(*(.xtensa_level3_vector.text)); . = 0x200; - KEEP(*(.Level4InterruptVector.text)); + KEEP(*(.xtensa_level4_vector.text)); . = 0x240; - KEEP(*(.Level5InterruptVector.text)); + KEEP(*(.xtensa_level5_vector.text)); . = 0x280; KEEP(*(.DebugExceptionVector.text)); . = 0x2c0; diff --git a/configs/esp32-core/scripts/esp32_rom.ld b/configs/esp32-core/scripts/esp32_rom.ld index 5276fa76c2..b7181d8896 100644 --- a/configs/esp32-core/scripts/esp32_rom.ld +++ b/configs/esp32-core/scripts/esp32_rom.ld @@ -383,14 +383,14 @@ PROVIDE ( ld_sched_params = 0x3ffb96c0 ); PROVIDE ( ld_sync_train_channels = 0x3ff98a3c ); PROVIDE ( __ledf2 = 0x40063704 ); PROVIDE ( __lesf2 = 0x400633c0 ); -PROVIDE ( _Level2FromVector = 0x40000954 ); -PROVIDE ( _Level2Vector = 0x40000180 ); -PROVIDE ( _Level3FromVector = 0x40000a28 ); -PROVIDE ( _Level3Vector = 0x400001c0 ); -PROVIDE ( _Level4FromVector = 0x40000af8 ); -PROVIDE ( _Level4Vector = 0x40000200 ); -PROVIDE ( _Level5FromVector = 0x40000c68 ); -PROVIDE ( _Level5Vector = 0x40000240 ); +PROVIDE ( _xtensa_level2_from = 0x40000954 ); +PROVIDE ( _xtensa_level2_vector = 0x40000180 ); +PROVIDE ( _xtensa_level3_from = 0x40000a28 ); +PROVIDE ( _xtensa_level3_vector = 0x400001c0 ); +PROVIDE ( _xtensa_level4_from = 0x40000af8 ); +PROVIDE ( _xtensa_level4_vector = 0x40000200 ); +PROVIDE ( _xtensa_level5_from = 0x40000c68 ); +PROVIDE ( _xtensa_level5_vector = 0x40000240 ); PROVIDE ( _LevelOneInterrupt = 0x40000835 ); PROVIDE ( _link_r = 0x4000bc9c ); PROVIDE ( llc_default_handler = 0x3ff98b3c ); -- GitLab From dda7f4cd750d352e3487032d692f74740dfcbdf1 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 19 Oct 2016 14:01:51 -0600 Subject: [PATCH 142/734] Trivial corrections to spacing --- arch/xtensa/src/common/xtensa_context.S | 32 ++++++++++++------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index 96dd333848..665fd03c9d 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -476,21 +476,21 @@ _xt_coproc_savecs: call0 XT_RTOS_CP_STATE /* get address of CP save area */ mov a0, a14 /* restore return address */ beqz a15, .Ldone /* if none then nothing to do */ - s16i a2, a15, XT_CP_CS_ST /* save mask of CPs being stored */ - movi a13, _xt_coproc_sa_offset /* array of CP save offsets */ - l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ + s16i a2, a15, XT_CP_CS_ST /* save mask of CPs being stored */ + movi a13, _xt_coproc_sa_offset /* array of CP save offsets */ + l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ #if XCHAL_CP0_SA_SIZE - bbci.l a2, 0, 2f /* CP 0 not enabled */ - l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ + bbci.l a2, 0, 2f /* CP 0 not enabled */ + l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ add a3, a14, a15 /* a3 = save area for CP 0 */ xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL 2: #endif #if XCHAL_CP1_SA_SIZE - bbci.l a2, 1, 2f /* CP 1 not enabled */ - l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ + bbci.l a2, 1, 2f /* CP 1 not enabled */ + l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ add a3, a14, a15 /* a3 = save area for CP 1 */ xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL 2: @@ -584,23 +584,23 @@ _xt_coproc_restorecs: call0 XT_RTOS_CP_STATE /* Get address of CP save area */ mov a0, a14 /* Restore return address */ beqz a15, .Ldone2 /* If none then nothing to do */ - l16ui a3, a15, XT_CP_CS_ST /* a3 = which CPs have been saved */ - xor a3, a3, a2 /* Clear the ones being restored */ - s32i a3, a15, XT_CP_CS_ST /* Update saved CP mask */ - movi a13, _xt_coproc_sa_offset /* Array of CP save offsets */ - l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ + l16ui a3, a15, XT_CP_CS_ST /* a3 = which CPs have been saved */ + xor a3, a3, a2 /* Clear the ones being restored */ + s32i a3, a15, XT_CP_CS_ST /* Update saved CP mask */ + movi a13, _xt_coproc_sa_offset /* Array of CP save offsets */ + l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ #if XCHAL_CP0_SA_SIZE - bbci.l a2, 0, 2f /* CP 0 not enabled */ - l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ + bbci.l a2, 0, 2f /* CP 0 not enabled */ + l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ add a3, a14, a15 /* a3 = save area for CP 0 */ xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL 2: #endif #if XCHAL_CP1_SA_SIZE - bbci.l a2, 1, 2f /* CP 1 not enabled */ - l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ + bbci.l a2, 1, 2f /* CP 1 not enabled */ + l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ add a3, a14, a15 /* a3 = save area for CP 1 */ xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL 2: -- GitLab From d2d60a59bf841fa44bca1ef0650b39af008a3d7e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 19 Oct 2016 13:58:50 -0600 Subject: [PATCH 143/734] ESP32: Refresh configuration; fix some compile issues --- arch/xtensa/src/common/xtensa_macros.h | 2 +- arch/xtensa/src/common/xtensa_vectors.S | 2 -- configs/esp32-core/nsh/defconfig | 4 ++++ 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_macros.h b/arch/xtensa/src/common/xtensa_macros.h index 3e8952be88..aabe43b848 100644 --- a/arch/xtensa/src/common/xtensa_macros.h +++ b/arch/xtensa/src/common/xtensa_macros.h @@ -38,7 +38,7 @@ ****************************************************************************/ #include -#include chip_macros.h" +#include "chip_macros.h" /**************************************************************************** * Assembly Language Macros diff --git a/arch/xtensa/src/common/xtensa_vectors.S b/arch/xtensa/src/common/xtensa_vectors.S index 6af479677c..35de6b3239 100644 --- a/arch/xtensa/src/common/xtensa_vectors.S +++ b/arch/xtensa/src/common/xtensa_vectors.S @@ -152,5 +152,3 @@ _xtensa_level6_vector: .size _xtensa_level6_vector, . - _xtensa_level6_vector #endif - - .end diff --git a/configs/esp32-core/nsh/defconfig b/configs/esp32-core/nsh/defconfig index 895a2d6bac..6e1935c244 100644 --- a/configs/esp32-core/nsh/defconfig +++ b/configs/esp32-core/nsh/defconfig @@ -75,6 +75,8 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_FAMILY_LX6=y CONFIG_XTENSA_NCOPROCESSORS=1 +CONFIG_XTENSA_INT_NLEVELS=5 +CONFIG_XTENSA_EXCM_LEVEL=3 # CONFIG_XTENSA_HAVE_LOOPS is not set CONFIG_XTENSA_HAVE_INTERRUPTS=y # CONFIG_XTENSA_USE_SWPRI is not set @@ -482,6 +484,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set -- GitLab From 1cb05d007d8bdbb70b9c46fbc184deb871ab5d94 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Wed, 19 Oct 2016 14:26:48 -0600 Subject: [PATCH 144/734] Add some less-than-perfect macros to provide some implementation of strtof() and strtold() --- include/stdlib.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/stdlib.h b/include/stdlib.h index 83eb7dd886..1d45291f1a 100644 --- a/include/stdlib.h +++ b/include/stdlib.h @@ -80,6 +80,19 @@ # define environ get_environ_ptr() #endif +/* The functions strtof() and strtold() are not currently implemented in + * NuttX. Ideally, custom implementations of these functions to be provided: + * + * strtof() - Some MCUs, such as the Cortex-M4F, have built in 32-bit FPU. + * A true implementation could exploit the improved performance by the + * the FPU. + * strtold() - Of course, there is a lost of 32-bits of accuracy in this + * conversion. + */ + +#define strtof(a,b) (float)strtod(a,b) +#define strtold(a,b) (long double)strtod(a,b) + /**************************************************************************** * Public Type Definitions ****************************************************************************/ -- GitLab From 2dbcdd781c0f493e62663e244f6c7da136360695 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 20 Oct 2016 07:18:23 -0600 Subject: [PATCH 145/734] Correct STM32 Butterfly2 URL. Correct some comments. --- Documentation/NuttX.html | 2 +- configs/Kconfig | 3 ++- configs/README.txt | 3 ++- include/stdlib.h | 5 +++-- 4 files changed, 8 insertions(+), 5 deletions(-) diff --git a/Documentation/NuttX.html b/Documentation/NuttX.html index c77315e797..18963bc574 100644 --- a/Documentation/NuttX.html +++ b/Documentation/NuttX.html @@ -3160,7 +3160,7 @@ nsh>

  • Kamami STM32 Butterfly 2 - Support for the Kamami STM32 Butterfly 2 was contributed by MichaÅ‚ Åyszczek in NuttX-7/18. That port features the STMicro STM32F107VC MCU. + Support for the Kamami STM32 Butterfly 2 was contributed by MichaÅ‚ Åyszczek in NuttX-7/18. That port features the STMicro STM32F107VC MCU.

    STATUS: diff --git a/configs/Kconfig b/configs/Kconfig index 3e08a0dba4..65f6a690d9 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -952,7 +952,8 @@ config ARCH_BOARD_STM32_BUTTERFLY2 ---help--- A configuration for the Kamami STM32Butterfly2 development board based on STM32F107VC micro-controler chip with optional ETH - board. + board. See + https://kamami.pl/zestawy-uruchomieniowe-stm32/178507-stm32butterfly2.html config ARCH_BOARD_STM32_TINY bool "STM32-Tiny board" diff --git a/configs/README.txt b/configs/README.txt index 9bd796ffa7..c9b84676b2 100644 --- a/configs/README.txt +++ b/configs/README.txt @@ -652,7 +652,8 @@ configs/stm3240g-eval toolchain (such as CodeSourcery). configs/stm32butterfly2 - Kamami stm32butterfly2 development board with optional ETH phy. + Kamami stm32butterfly2 development board with optional ETH phy. See + https://kamami.pl/zestawy-uruchomieniowe-stm32/178507-stm32butterfly2.html configs/stm32f103-minimum Generic STM32F103C8T6 Minimum ARM Development Board. diff --git a/include/stdlib.h b/include/stdlib.h index 1d45291f1a..10ec6c2629 100644 --- a/include/stdlib.h +++ b/include/stdlib.h @@ -81,12 +81,13 @@ #endif /* The functions strtof() and strtold() are not currently implemented in - * NuttX. Ideally, custom implementations of these functions to be provided: + * NuttX. Ideally, custom implementations of these functions would be + * provided because: * * strtof() - Some MCUs, such as the Cortex-M4F, have built in 32-bit FPU. * A true implementation could exploit the improved performance by the * the FPU. - * strtold() - Of course, there is a lost of 32-bits of accuracy in this + * strtold() - Of course, there is a loss of 32-bits of accuracy in this * conversion. */ -- GitLab From 11af1fc24cf3e036859e927fd43908276a439935 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 20 Oct 2016 08:51:15 -0600 Subject: [PATCH 146/734] Xtensa: Separate context save/restore from coprocessor functions. Making to changes to interrupt handling to support NuttX. --- arch/xtensa/src/common/xtensa_context.S | 431 +++--------------- arch/xtensa/src/common/xtensa_coproc.S | 397 ++++++++++++++++ .../{xtensa_vectors.S => xtensa_intvectors.S} | 2 +- arch/xtensa/src/esp32/Make.defs | 2 +- 4 files changed, 470 insertions(+), 362 deletions(-) create mode 100644 arch/xtensa/src/common/xtensa_coproc.S rename arch/xtensa/src/common/{xtensa_vectors.S => xtensa_intvectors.S} (99%) diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index 665fd03c9d..43d43ba060 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -33,10 +33,10 @@ /* XTENSA CONTEXT SAVE AND RESTORE ROUTINES * - * Low-level Call0 functions for handling generic context save and restore of - * registers not specifically addressed by the interrupt vectors and handlers. - * Those registers (not handled by these functions) are PC, PS, A0, A1 (SP). - * Except for the calls to RTOS functions, this code is generic to Xtensa. + * Low-level Call0 functions for handling generic context save and restore + * of registers not specifically addressed by the interrupt vectors and + * handlers. Those registers (not handled by these functions) are PC, PS, + * A0, A1 (SP). * * Note that in Call0 ABI, interrupt handlers are expected to preserve the callee- * save regs (A12-A15), which is always the case if the handlers are coded in C. @@ -71,44 +71,59 @@ /**************************************************************************** * Name: _xtensa_context_save + * _xtensa_full_context_save * * Description: * * NOTE: MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION! * - * Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13, - * in the interrupt stack frame defined in xtensa_rtos.h. Its counterpart - * is _xtensa_context_restore (which also restores A12, A13). + * These functions save Xtensa processor state: * - * Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the - * frame. This function preserves A12 & A13 in order to provide the caller - * with 2 scratch regs that need not be saved over the call to this - * function. The choice of which 2 regs to provide is governed by - * xthal_window_spill_nw and xthal_save_extra_nw, to avoid moving data - * more than necessary. Caller can assign regs accordingly. + * - _xtensa_full_context_save saves all registers except PC, PS, A0, and + * A1 (SP) + * - _xtensa_context_save, in addition, does not save A12-A15 which + * are preserved by the callee). * - * Entry Conditions: + * Caller is expected to have saved PC, PS, A0, and A1 (SP). + * + * The counterparts to these functions are _xtensa_context_restore() and + * xtensa_full_context_restore(). + * + * Entry Conditions: * - A0 = Return address in caller. - * - A1 = Stack pointer of interrupted thread or handler ("interruptee"). - * - Original A12, A13 have already been saved in the interrupt stack - * frame. - * - Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as a + * - A1 = Stack pointer of calling thread or interrupt handler. + * - Other processor state except PC, PS, A0, and A1 (SP) are as at * the point of interruption. * - If windowed ABI, PS.EXCM = 1 (exceptions disabled). * * Exit conditions: * - A0 = Return address in caller. * - A1 = Stack pointer of interrupted thread or handler ("interruptee"). - * - A12, A13 as at entry (preserved). + * - A12-A15 as at entry (preserved). * - If windowed ABI, PS.EXCM = 1 (exceptions disabled). * ****************************************************************************/ + .global _xtensa_full_context_save .global _xtensa_context_save + .type _xtensa_full_context_save, @function .type _xtensa_context_save, @function + .align 4 .literal_position .align 4 + +_xtensa_full_context_save: + +#ifndef CONFIG_XTENSA_CALL0_ABI + /* Save Call0 ABI callee-saved regs a12-15. */ + + s32i a12, sp, (4 * REG_A12) + s32i a13, sp, (4 * REG_A13) + s32i a14, sp, (4 * REG_A14) + s32i a15, sp, (4 * REG_A15) +#endif + _xtensa_context_save: s32i a2, sp, (4 * REG_A2) @@ -128,6 +143,8 @@ _xtensa_context_save: */ #ifndef CONFIG_XTENSA_CALL0_ABI + s32i a12, sp, (4 * REG_A12) + s32i a13, sp, (4 * REG_A13) s32i a14, sp, (4 * REG_A14) s32i a15, sp, (4 * REG_A15) #endif @@ -216,35 +233,56 @@ _xtensa_context_save: /**************************************************************************** * Name: _xtensa_context_restore + * _xtensa_full_context_restore * * Description: * - * NOTE: MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION! + * NOTE: MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION! * - * Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in - * Call0 ABI, A14, A15 which are preserved by all interrupt handlers) from - * an interrupt stack frame defined in xtensa_rtos.h. - * Its counterpart is _xtensa_context_save (whose caller saved A12, A13). + * These functions restores Xtensa processor state and differ in which + * registers are saved: * - * Caller is responsible to restore PC, PS, A0, A1 (SP). + * - _xtensa_full_context_restore restores all registers except PC, PS, + * A0, and A1 (SP) + * - _xtensa_context_restore, in addition, does not restore A12-A15 which + * are preserved by the callee). + * + * The caller is responsible for restoring PC, PS, A0, A1 (SP) in both cases. + * + * _xtensa_context_save and _xtensa_full_context_save are the counterparts + * to these functions. * * Entry Conditions: - * - A0 = Return address in caller. - * - A1 = Stack pointer of interrupted thread or handler ("interruptee"). + * - A0 = Return address in caller. + * - A1 = Stack pointer of calling thread or interrupt handler. * * Exit conditions: - * - A0 = Return address in caller. - * - A1 = Stack pointer of interrupted thread or handler ("interruptee"). - * - Other processor state except PC, PS, A0, A1 (SP), is as at the point - * of interruption. + * - A0 = Return address in caller. + * - A1 = Stack pointer of calling thread or interrupt handler. + * - Other registers are restored as detailed above. * ****************************************************************************/ + .global _xtensa_full_context_restore .global _xtensa_context_restore + .type _xtensa_full_context_restore,@function .type _xtensa_context_restore,@function + .align 4 .literal_position .align 4 + +_xtensa_full_context_restore: + +#ifndef CONFIG_XTENSA_CALL0_ABI + /* Restore Call0 ABI callee-saved regs a12-15. */ + + l32i a12, sp, (4 * REG_A12) + l32i a13, sp, (4 * REG_A13) + l32i a14, sp, (4 * REG_A14) + l32i a15, sp, (4 * REG_A15) +#endif + _xtensa_context_restore: #if XCHAL_EXTRA_SA_SIZE > 0 @@ -259,6 +297,7 @@ _xtensa_context_restore: mov a13, a0 /* Preserve ret addr */ addi a2, sp, (4 * REG_EXTRA) /* Where to find it */ + #if XCHAL_EXTRA_SA_ALIGN > 16 movi a3, -XCHAL_EXTRA_SA_ALIGN and a2, a2, a3 /* Align dynamically >16 bytes */ @@ -322,339 +361,11 @@ _xtensa_context_restore: * so need to be restored anyway, despite being callee-saved in Call0. */ +#ifndef CONFIG_XTENSA_CALL0_ABI l32i a12, sp, (4 * REG_A12) l32i a13, sp, (4 * REG_A13) -#ifndef CONFIG_XTENSA_CALL0_ABI l32i a14, sp, (4 * REG_A14) l32i a15, sp, (4 * REG_A15) #endif ret - -/**************************************************************************** - * Name: _xt_coproc_init - * - * Description: - * Initializes global co-processor management data, setting all co- - * processors to "unowned". Leaves CPENABLE as it found it (does NOT clear - * it). - * - * Called during initialization of the RTOS, before any threads run. - * - * This may be called from normal Xtensa single-threaded application code - * which might use co-processors. The Xtensa run-time initialization enables - * all co-processors. They must remain enabled here, else a co-processor - * exception might occur outside of a thread, which the exception handler - * doesn't expect. - * - * Entry Conditions: - * - Xtensa single-threaded run-time environment is in effect. - * No thread is yet running. - * - * Exit conditions: - * - None. - * - * Obeys ABI conventions per prototype: - * void _xt_coproc_init(void) - * - ****************************************************************************/ - -#if CONFIG_XTENSA_NCOPROCESSORS > 0 - .global _xt_coproc_init - .type _xt_coproc_init,@function - .align 4 - .literal_position - .align 4 -_xt_coproc_init: - ENTRY0 - - /* Initialize thread co-processor ownerships to 0 (unowned). */ - - movi a2, _xt_coproc_owner_sa /* a2 = base of owner array */ - addi a3, a2, (XCHAL_CP_MAX*portNUM_PROCESSORS) << 2 /* a3 = top+1 of owner array */ - movi a4, 0 /* a4 = 0 (unowned) */ -1: s32i a4, a2, 0 - addi a2, a2, 4 - bltu a2, a3, 1b - - RET0 -#endif - -/**************************************************************************** - * Name: _xt_coproc_release - * - * Description: - * Releases any and all co-processors owned by a given thread. The thread - * is identified by it's co-processor state save area defined in - * xtensa_context.h. - * - * Must be called before a thread's co-proc save area is deleted to avoid - * memory corruption when the exception handler tries to save the state. - * May be called when a thread terminates or completes but does not delete - * the co-proc save area, to avoid the exception handler having to save - * the thread's co-proc state before another thread can use it - * (optimization). - * - * Entry Conditions: - * - A2 = Pointer to base of co-processor state save area. - * - * Exit conditions: - * - None. - * - * Obeys ABI conventions per prototype: - * void _xt_coproc_release(void * coproc_sa_base) - * - ****************************************************************************/ - -#if CONFIG_XTENSA_NCOPROCESSORS > 0 - .global _xt_coproc_release - .type _xt_coproc_release,@function - .align 4 - .literal_position - .align 4 -_xt_coproc_release: - ENTRY0 /* a2 = base of save area */ - - getcoreid a5 - movi a3, XCHAL_CP_MAX << 2 - mull a5, a5, a3 - movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */ - add a3, a3, a5 - - addi a4, a3, XCHAL_CP_MAX << 2 /* a4 = top+1 of owner array */ - movi a5, 0 /* a5 = 0 (unowned) */ - - rsil a6, CONFIG_XTENSA_EXCM_LEVEL /* Lock interrupts */ - -1: l32i a7, a3, 0 /* a7 = owner at a3 */ - bne a2, a7, 2f /* if (coproc_sa_base == owner) */ - s32i a5, a3, 0 /* owner = unowned */ -2: addi a3, a3, 1 << 2 /* a3 = next entry in owner array */ - bltu a3, a4, 1b /* Repeat until end of array */ - -3: wsr a6, PS /* Restore interrupts */ - - RET0 -#endif - -/**************************************************************************** - * Name: _xt_coproc_savecs - * - * Description: - * If there is a current thread and it has a coprocessor state save area, - * then save all callee-saved state into this area. This function is called - * from the solicited context switch handler. It calls a system-specific - * function to get the coprocessor save area base address. - * - * Entry conditions: - * - The thread being switched out is still the current thread. - * - CPENABLE state reflects which coprocessors are active. - * - Registers have been saved/spilled already. - * - * Exit conditions: - * - All necessary CP callee-saved state has been saved. - * - Registers a2-a7, a13-a15 have been trashed. - * - * Must be called from assembly code only, using CALL0. - * - ****************************************************************************/ - -#if CONFIG_XTENSA_NCOPROCESSORS > 0 - .extern _xt_coproc_sa_offset /* external reference */ - .global _xt_coproc_savecs - .type _xt_coproc_savecs,@function - .align 4 - .literal_position - .align 4 -_xt_coproc_savecs: - - /* At entry, CPENABLE should be showing which CPs are enabled. */ - - rsr a2, CPENABLE /* a2 = which CPs are enabled */ - beqz a2, .Ldone /* quick exit if none */ - mov a14, a0 /* save return address */ - call0 XT_RTOS_CP_STATE /* get address of CP save area */ - mov a0, a14 /* restore return address */ - beqz a15, .Ldone /* if none then nothing to do */ - s16i a2, a15, XT_CP_CS_ST /* save mask of CPs being stored */ - movi a13, _xt_coproc_sa_offset /* array of CP save offsets */ - l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ - -#if XCHAL_CP0_SA_SIZE - bbci.l a2, 0, 2f /* CP 0 not enabled */ - l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ - add a3, a14, a15 /* a3 = save area for CP 0 */ - xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP1_SA_SIZE - bbci.l a2, 1, 2f /* CP 1 not enabled */ - l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ - add a3, a14, a15 /* a3 = save area for CP 1 */ - xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP2_SA_SIZE - bbci.l a2, 2, 2f - l32i a14, a13, 8 - add a3, a14, a15 - xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP3_SA_SIZE - bbci.l a2, 3, 2f - l32i a14, a13, 12 - add a3, a14, a15 - xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP4_SA_SIZE - bbci.l a2, 4, 2f - l32i a14, a13, 16 - add a3, a14, a15 - xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP5_SA_SIZE - bbci.l a2, 5, 2f - l32i a14, a13, 20 - add a3, a14, a15 - xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP6_SA_SIZE - bbci.l a2, 6, 2f - l32i a14, a13, 24 - add a3, a14, a15 - xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP7_SA_SIZE - bbci.l a2, 7, 2f - l32i a14, a13, 28 - add a3, a14, a15 - xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -.Ldone: - ret -#endif - -/**************************************************************************** - * Name: _xt_coproc_restorecs - * - * Description: - * Restore any callee-saved coprocessor state for the incoming thread. - * This function is called from coprocessor exception handling, when - * giving ownership to a thread that solicited a context switch earlier. - * It calls a system-specific function to get the coprocessor save area - * base address. - * - * Entry conditions: - * - The incoming thread is set as the current thread. - * - CPENABLE is set up correctly for all required coprocessors. - * - a2 = mask of coprocessors to be restored. - * - * Exit conditions: - * - All necessary CP callee-saved state has been restored. - * - CPENABLE - unchanged. - * - Registers a2-a7, a13-a15 have been trashed. - * - * Must be called from assembly code only, using CALL0. - * - ****************************************************************************/ - -#if CONFIG_XTENSA_NCOPROCESSORS > 0 - .global _xt_coproc_restorecs - .type _xt_coproc_restorecs,@function - .align 4 - .literal_position - .align 4 -_xt_coproc_restorecs: - - mov a14, a0 /* Save return address */ - call0 XT_RTOS_CP_STATE /* Get address of CP save area */ - mov a0, a14 /* Restore return address */ - beqz a15, .Ldone2 /* If none then nothing to do */ - l16ui a3, a15, XT_CP_CS_ST /* a3 = which CPs have been saved */ - xor a3, a3, a2 /* Clear the ones being restored */ - s32i a3, a15, XT_CP_CS_ST /* Update saved CP mask */ - movi a13, _xt_coproc_sa_offset /* Array of CP save offsets */ - l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ - -#if XCHAL_CP0_SA_SIZE - bbci.l a2, 0, 2f /* CP 0 not enabled */ - l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ - add a3, a14, a15 /* a3 = save area for CP 0 */ - xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP1_SA_SIZE - bbci.l a2, 1, 2f /* CP 1 not enabled */ - l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ - add a3, a14, a15 /* a3 = save area for CP 1 */ - xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP2_SA_SIZE - bbci.l a2, 2, 2f - l32i a14, a13, 8 - add a3, a14, a15 - xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP3_SA_SIZE - bbci.l a2, 3, 2f - l32i a14, a13, 12 - add a3, a14, a15 - xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP4_SA_SIZE - bbci.l a2, 4, 2f - l32i a14, a13, 16 - add a3, a14, a15 - xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP5_SA_SIZE - bbci.l a2, 5, 2f - l32i a14, a13, 20 - add a3, a14, a15 - xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP6_SA_SIZE - bbci.l a2, 6, 2f - l32i a14, a13, 24 - add a3, a14, a15 - xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP7_SA_SIZE - bbci.l a2, 7, 2f - l32i a14, a13, 28 - add a3, a14, a15 - xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -.Ldone2: - ret - -#endif diff --git a/arch/xtensa/src/common/xtensa_coproc.S b/arch/xtensa/src/common/xtensa_coproc.S new file mode 100644 index 0000000000..92ce8fbaf0 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_coproc.S @@ -0,0 +1,397 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_coproc.S + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * + * Copyright (c) 2006-2015 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + +/* XTENSA CONTEXT SAVE AND RESTORE ROUTINES + * + * Low-level Call0 functions for handling generic context save and restore of + * registers not specifically addressed by the interrupt vectors and handlers. + * Those registers (not handled by these functions) are PC, PS, A0, A1 (SP). + * Except for the calls to RTOS functions, this code is generic to Xtensa. + * + * Note that in Call0 ABI, interrupt handlers are expected to preserve the callee- + * save regs (A12-A15), which is always the case if the handlers are coded in C. + * However A12, A13 are made available as scratch registers for interrupt dispatch + * code, so are presumed saved anyway, and are always restored even in Call0 ABI. + * Only A14, A15 are truly handled as callee-save regs. + * + * Because Xtensa is a configurable architecture, this port supports all user + * generated configurations (except restrictions stated in the release notes). + * This is accomplished by conditional compilation using macros and functions + * defined in the Xtensa HAL (hardware adaptation layer) for your configuration. + * Only the processor state included in your configuration is saved and restored, + * including any processor state added by user configuration options or TIE. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "xtensa_context.h" + +#ifdef CONFIG_XTENSA_USE_OVLY +# include +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + + .text + +/**************************************************************************** + * Name: _xt_coproc_init + * + * Description: + * Initializes global co-processor management data, setting all co- + * processors to "unowned". Leaves CPENABLE as it found it (does NOT clear + * it). + * + * Called during initialization of the RTOS, before any threads run. + * + * This may be called from normal Xtensa single-threaded application code + * which might use co-processors. The Xtensa run-time initialization enables + * all co-processors. They must remain enabled here, else a co-processor + * exception might occur outside of a thread, which the exception handler + * doesn't expect. + * + * Entry Conditions: + * - Xtensa single-threaded run-time environment is in effect. + * No thread is yet running. + * + * Exit conditions: + * - None. + * + * Obeys ABI conventions per prototype: + * void _xt_coproc_init(void) + * + ****************************************************************************/ + +#if CONFIG_XTENSA_NCOPROCESSORS > 0 + .global _xt_coproc_init + .type _xt_coproc_init,@function + .align 4 + .literal_position + .align 4 +_xt_coproc_init: + ENTRY0 + + /* Initialize thread co-processor ownerships to 0 (unowned). */ + + movi a2, _xt_coproc_owner_sa /* a2 = base of owner array */ + addi a3, a2, (XCHAL_CP_MAX*portNUM_PROCESSORS) << 2 /* a3 = top+1 of owner array */ + movi a4, 0 /* a4 = 0 (unowned) */ +1: s32i a4, a2, 0 + addi a2, a2, 4 + bltu a2, a3, 1b + + RET0 +#endif + +/**************************************************************************** + * Name: _xt_coproc_release + * + * Description: + * Releases any and all co-processors owned by a given thread. The thread + * is identified by it's co-processor state save area defined in + * xtensa_context.h. + * + * Must be called before a thread's co-proc save area is deleted to avoid + * memory corruption when the exception handler tries to save the state. + * May be called when a thread terminates or completes but does not delete + * the co-proc save area, to avoid the exception handler having to save + * the thread's co-proc state before another thread can use it + * (optimization). + * + * Entry Conditions: + * - A2 = Pointer to base of co-processor state save area. + * + * Exit conditions: + * - None. + * + * Obeys ABI conventions per prototype: + * void _xt_coproc_release(void * coproc_sa_base) + * + ****************************************************************************/ + +#if CONFIG_XTENSA_NCOPROCESSORS > 0 + .global _xt_coproc_release + .type _xt_coproc_release,@function + .align 4 + .literal_position + .align 4 +_xt_coproc_release: + ENTRY0 /* a2 = base of save area */ + + getcoreid a5 + movi a3, XCHAL_CP_MAX << 2 + mull a5, a5, a3 + movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */ + add a3, a3, a5 + + addi a4, a3, XCHAL_CP_MAX << 2 /* a4 = top+1 of owner array */ + movi a5, 0 /* a5 = 0 (unowned) */ + + rsil a6, CONFIG_XTENSA_EXCM_LEVEL /* Lock interrupts */ + +1: l32i a7, a3, 0 /* a7 = owner at a3 */ + bne a2, a7, 2f /* if (coproc_sa_base == owner) */ + s32i a5, a3, 0 /* owner = unowned */ +2: addi a3, a3, 1 << 2 /* a3 = next entry in owner array */ + bltu a3, a4, 1b /* Repeat until end of array */ + +3: wsr a6, PS /* Restore interrupts */ + + RET0 +#endif + +/**************************************************************************** + * Name: _xt_coproc_savecs + * + * Description: + * If there is a current thread and it has a coprocessor state save area, + * then save all callee-saved state into this area. This function is called + * from the solicited context switch handler. It calls a system-specific + * function to get the coprocessor save area base address. + * + * Entry conditions: + * - The thread being switched out is still the current thread. + * - CPENABLE state reflects which coprocessors are active. + * - Registers have been saved/spilled already. + * + * Exit conditions: + * - All necessary CP callee-saved state has been saved. + * - Registers a2-a7, a13-a15 have been trashed. + * + * Must be called from assembly code only, using CALL0. + * + ****************************************************************************/ + +#if CONFIG_XTENSA_NCOPROCESSORS > 0 + .extern _xt_coproc_sa_offset /* external reference */ + .global _xt_coproc_savecs + .type _xt_coproc_savecs,@function + .align 4 + .literal_position + .align 4 +_xt_coproc_savecs: + + /* At entry, CPENABLE should be showing which CPs are enabled. */ + + rsr a2, CPENABLE /* a2 = which CPs are enabled */ + beqz a2, .Ldone /* quick exit if none */ + mov a14, a0 /* save return address */ + call0 XT_RTOS_CP_STATE /* get address of CP save area */ + mov a0, a14 /* restore return address */ + beqz a15, .Ldone /* if none then nothing to do */ + s16i a2, a15, XT_CP_CS_ST /* save mask of CPs being stored */ + movi a13, _xt_coproc_sa_offset /* array of CP save offsets */ + l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ + +#if XCHAL_CP0_SA_SIZE + bbci.l a2, 0, 2f /* CP 0 not enabled */ + l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ + add a3, a14, a15 /* a3 = save area for CP 0 */ + xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP1_SA_SIZE + bbci.l a2, 1, 2f /* CP 1 not enabled */ + l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ + add a3, a14, a15 /* a3 = save area for CP 1 */ + xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP2_SA_SIZE + bbci.l a2, 2, 2f + l32i a14, a13, 8 + add a3, a14, a15 + xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP3_SA_SIZE + bbci.l a2, 3, 2f + l32i a14, a13, 12 + add a3, a14, a15 + xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP4_SA_SIZE + bbci.l a2, 4, 2f + l32i a14, a13, 16 + add a3, a14, a15 + xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP5_SA_SIZE + bbci.l a2, 5, 2f + l32i a14, a13, 20 + add a3, a14, a15 + xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP6_SA_SIZE + bbci.l a2, 6, 2f + l32i a14, a13, 24 + add a3, a14, a15 + xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP7_SA_SIZE + bbci.l a2, 7, 2f + l32i a14, a13, 28 + add a3, a14, a15 + xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +.Ldone: + ret +#endif + +/**************************************************************************** + * Name: _xt_coproc_restorecs + * + * Description: + * Restore any callee-saved coprocessor state for the incoming thread. + * This function is called from coprocessor exception handling, when + * giving ownership to a thread that solicited a context switch earlier. + * It calls a system-specific function to get the coprocessor save area + * base address. + * + * Entry conditions: + * - The incoming thread is set as the current thread. + * - CPENABLE is set up correctly for all required coprocessors. + * - a2 = mask of coprocessors to be restored. + * + * Exit conditions: + * - All necessary CP callee-saved state has been restored. + * - CPENABLE - unchanged. + * - Registers a2-a7, a13-a15 have been trashed. + * + * Must be called from assembly code only, using CALL0. + * + ****************************************************************************/ + +#if CONFIG_XTENSA_NCOPROCESSORS > 0 + .global _xt_coproc_restorecs + .type _xt_coproc_restorecs,@function + .align 4 + .literal_position + .align 4 +_xt_coproc_restorecs: + + mov a14, a0 /* Save return address */ + call0 XT_RTOS_CP_STATE /* Get address of CP save area */ + mov a0, a14 /* Restore return address */ + beqz a15, .Ldone2 /* If none then nothing to do */ + l16ui a3, a15, XT_CP_CS_ST /* a3 = which CPs have been saved */ + xor a3, a3, a2 /* Clear the ones being restored */ + s32i a3, a15, XT_CP_CS_ST /* Update saved CP mask */ + movi a13, _xt_coproc_sa_offset /* Array of CP save offsets */ + l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ + +#if XCHAL_CP0_SA_SIZE + bbci.l a2, 0, 2f /* CP 0 not enabled */ + l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ + add a3, a14, a15 /* a3 = save area for CP 0 */ + xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP1_SA_SIZE + bbci.l a2, 1, 2f /* CP 1 not enabled */ + l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ + add a3, a14, a15 /* a3 = save area for CP 1 */ + xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP2_SA_SIZE + bbci.l a2, 2, 2f + l32i a14, a13, 8 + add a3, a14, a15 + xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP3_SA_SIZE + bbci.l a2, 3, 2f + l32i a14, a13, 12 + add a3, a14, a15 + xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP4_SA_SIZE + bbci.l a2, 4, 2f + l32i a14, a13, 16 + add a3, a14, a15 + xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP5_SA_SIZE + bbci.l a2, 5, 2f + l32i a14, a13, 20 + add a3, a14, a15 + xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP6_SA_SIZE + bbci.l a2, 6, 2f + l32i a14, a13, 24 + add a3, a14, a15 + xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XCHAL_CP7_SA_SIZE + bbci.l a2, 7, 2f + l32i a14, a13, 28 + add a3, a14, a15 + xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +.Ldone2: + ret + +#endif diff --git a/arch/xtensa/src/common/xtensa_vectors.S b/arch/xtensa/src/common/xtensa_intvectors.S similarity index 99% rename from arch/xtensa/src/common/xtensa_vectors.S rename to arch/xtensa/src/common/xtensa_intvectors.S index 35de6b3239..cf84869b3c 100644 --- a/arch/xtensa/src/common/xtensa_vectors.S +++ b/arch/xtensa/src/common/xtensa_intvectors.S @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/common/xtensa_vectors.S + * arch/xtensa/src/common/xtensa_intvectors.S * * Adapted from use in NuttX by: * diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index b66af09c90..1954962fdc 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -40,7 +40,7 @@ HEAD_CSRC = esp32_start.c # Common XTENSA files (arch/xtensa/src/common) -CMN_ASRCS = xtensa_irq.S xtensa_vectors.S +CMN_ASRCS = xtensa_context.S xtensa_irq.S xtensa_intvectors.S CMN_CSRCS = xtensa_assert.c xtensa_copystate.c CMN_CSRCS += xtensa_createstack.c xtensa_exit.c xtensa_idle.c CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c -- GitLab From d75fb34b6200de4f227aa5511756b580cc5904a3 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 20 Oct 2016 08:58:33 -0600 Subject: [PATCH 147/734] Xtensa: Fix some xtensa_context.S assemble issues --- arch/xtensa/src/common/xtensa_context.S | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index 43d43ba060..deeca55735 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -56,13 +56,16 @@ * Included Files ****************************************************************************/ -#include "xtensa_rtos.h" -#include "xtensa_context.h" +#include +#include #ifdef CONFIG_XTENSA_USE_OVLY # include #endif +#warning REVIST XCHAL_EXTRA_SA_SIZE is not yet provided +#define XCHAL_EXTRA_SA_SIZE 0 /* REMOVE ME */ + /**************************************************************************** * Public Functions ****************************************************************************/ -- GitLab From 5c3afd088ea979e7b75cbb542589914b62cd9e02 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 20 Oct 2016 11:44:14 -0600 Subject: [PATCH 148/734] Xtensa: A little more interrupt handling logic --- arch/xtensa/Kconfig | 12 - arch/xtensa/include/esp32/core-isa.h | 638 +++++++++++++++++++ arch/xtensa/include/irq.h | 52 +- arch/xtensa/src/common/xtensa_context.S | 29 +- arch/xtensa/src/common/xtensa_coproc.S | 354 +--------- arch/xtensa/src/common/xtensa_dumpstate.c | 4 +- arch/xtensa/src/common/xtensa_initialstate.c | 9 +- arch/xtensa/src/common/xtensa_inthandlers.S | 512 +++++++++++++++ arch/xtensa/src/common/xtensa_intvectors.S | 10 +- arch/xtensa/src/common/xtensa_timer.h | 147 +++++ 10 files changed, 1350 insertions(+), 417 deletions(-) create mode 100644 arch/xtensa/include/esp32/core-isa.h create mode 100644 arch/xtensa/src/common/xtensa_inthandlers.S create mode 100644 arch/xtensa/src/common/xtensa_timer.h diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index a028ee2ec1..9b08f38d12 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -35,18 +35,6 @@ config XTENSA_NCOPROCESSORS int "Number of co-processors" default 1 -config XTENSA_INT_NLEVELS - int "Number of interrupt levels" - default 5 - -config XTENSA_EXCM_LEVEL - int "Level masked by PS.EXCM" - default 3 - -config XTENSA_HAVE_LOOPS - bool "Zero overhead loops" - default n - config XTENSA_HAVE_INTERRUPTS bool default n diff --git a/arch/xtensa/include/esp32/core-isa.h b/arch/xtensa/include/esp32/core-isa.h new file mode 100644 index 0000000000..6027ec6479 --- /dev/null +++ b/arch/xtensa/include/esp32/core-isa.h @@ -0,0 +1,638 @@ +/**************************************************************************** + * arch/xtensa/include/esp32/core-isa.h + * Xtensa processor CORE configuration + * + * Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_INCLUDE_ESP32_CORE_ISA_H +#define __ARCH_XTENSA_INCLUDE_ESP32_CORE_ISA_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Note: Macros of the form XTENSA_HAVE_*** have a value of 1 if the option + * is configured, and a value of 0 otherwise (or undefined if 0 is a valid + * numeric option. These macros are always defined. + */ + +/* ISA **********************************************************************/ + +#define XTENSA_HAVE_BE 0 /* big-endian byte ordering */ +#define XTENSA_HAVE_WINDOWED 1 /* windowed registers option */ +#define XTENSA_NUM_AREGS 64 /* num of physical addr regs */ +#define XTENSA_NUM_AREGS_LOG2 6 /* log2(XTENSA_NUM_AREGS) */ +#define XTENSA_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ +#define XTENSA_HAVE_DEBUG 1 /* debug option */ +#define XTENSA_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XTENSA_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XTENSA_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */ +#define XTENSA_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XTENSA_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XTENSA_HAVE_SEXT 1 /* SEXT instruction */ +#define XTENSA_HAVE_DEPBITS 0 /* DEPBITS instruction */ +#define XTENSA_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XTENSA_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XTENSA_HAVE_MUL32 1 /* MULL instruction */ +#define XTENSA_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ +#define XTENSA_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ +#define XTENSA_HAVE_L32R 1 /* L32R instruction */ +#define XTENSA_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ +#define XTENSA_HAVE_CONST16 0 /* CONST16 instruction */ +#define XTENSA_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XTENSA_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XTENSA_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XTENSA_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XTENSA_HAVE_ABS 1 /* ABS instruction */ +/*#define XTENSA_HAVE_POPC 0*/ /* POPC instruction */ +/*#define XTENSA_HAVE_CRC 0*/ /* CRC instruction */ +#define XTENSA_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XTENSA_HAVE_S32C1I 1 /* S32C1I instruction */ +#define XTENSA_HAVE_SPECULATION 0 /* speculation */ +#define XTENSA_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XTENSA_NUM_CONTEXTS 1 /* */ +#define XTENSA_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */ +#define XTENSA_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XTENSA_HAVE_PRID 1 /* processor ID register */ +#define XTENSA_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XTENSA_HAVE_MX 0 /* MX core (Tensilica internal) */ +#define XTENSA_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XTENSA_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XTENSA_HAVE_PSO 0 /* Power Shut-Off */ +#define XTENSA_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ +#define XTENSA_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ +#define XTENSA_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XTENSA_HAVE_BOOLEANS 1 /* boolean registers */ +#define XTENSA_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XTENSA_CP_MAXCFG 8 /* max allowed cp id plus one */ +#define XTENSA_HAVE_MAC16 1 /* MAC16 package */ + +#define XTENSA_HAVE_FUSION 0 /* Fusion*/ +#define XTENSA_HAVE_FUSION_FP 0 /* Fusion FP option */ +#define XTENSA_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ +#define XTENSA_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ +#define XTENSA_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ +#define XTENSA_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ +#define XTENSA_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ +#define XTENSA_HAVE_FUSION_AVS 0 /* Fusion AVS option */ +#define XTENSA_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ +#define XTENSA_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ +#define XTENSA_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ +#define XTENSA_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XTENSA_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ +#define XTENSA_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ +#define XTENSA_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ +#define XTENSA_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ +#define XTENSA_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ +#define XTENSA_HAVE_HIFI2EP 0 /* HiFi2EP */ +#define XTENSA_HAVE_HIFI_MINI 0 + +#define XTENSA_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */ +#define XTENSA_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ +#define XTENSA_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */ +#define XTENSA_HAVE_FP 1 /* single prec floating point */ +#define XTENSA_HAVE_FP_DIV 1 /* FP with DIV instructions */ +#define XTENSA_HAVE_FP_RECIP 1 /* FP with RECIP instructions */ +#define XTENSA_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ +#define XTENSA_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */ +#define XTENSA_HAVE_DFP 0 /* double precision FP pkg */ +#define XTENSA_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ +#define XTENSA_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ +#define XTENSA_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ +#define XTENSA_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ +#define XTENSA_HAVE_DFP_ACCEL 1 /* double precision FP acceleration pkg */ +#define XTENSA_HAVE_DFP_accel XTENSA_HAVE_DFP_ACCEL /* for backward compatibility */ + +#define XTENSA_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */ +#define XTENSA_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ +#define XTENSA_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XTENSA_HAVE_VECTRALX 0 /* Vectra LX pkg */ +#define XTENSA_HAVE_PDX4 0 /* PDX4 */ +#define XTENSA_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XTENSA_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ +#define XTENSA_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XTENSA_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XTENSA_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XTENSA_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XTENSA_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ +#define XTENSA_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XTENSA_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ +#define XTENSA_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XTENSA_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XTENSA_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XTENSA_HAVE_BBP16 0 /* ConnX BBP16 pkg */ +#define XTENSA_HAVE_FLIX3 0 /* basic 3-way FLIX option */ +#define XTENSA_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */ +#define XTENSA_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ + +/* Misc. ********************************************************************/ + +#define XTENSA_NUM_LOADSTORE_UNITS 1 /* load/store units */ +#define XTENSA_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */ +#define XTENSA_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ +#define XTENSA_DATA_WIDTH 4 /* data width in bytes */ +#define XTENSA_DATA_PIPE_DELAY 2 /* d-side pipeline delay + * (1 = 5-stage, 2 = 7-stage) */ +#define XTENSA_CLOCK_GATING_GLOBAL 1 /* global clock gating */ +#define XTENSA_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XTENSA_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */ +#define XTENSA_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/ +#define XTENSA_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */ +#define XTENSA_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/ + +#define XTENSA_SW_VERSION 1100003 /* sw version of this header */ + +#define XTENSA_CORE_ID "esp32_v3_49_prod" /* alphanum core name + * (CoreID) set in the Xtensa + * Processor Generator */ + +#define XTENSA_BUILD_UNIQUE_ID 0x0005fe96 /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XTENSA_HW_CONFIGID0 0xc2bcfffe /* ConfigID hi 32 bits*/ +#define XTENSA_HW_CONFIGID1 0x1cc5fe96 /* ConfigID lo 32 bits*/ +#define XTENSA_HW_VERSION_NAME "LX6.0.3" /* full version name */ +#define XTENSA_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */ +#define XTENSA_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */ +#define XTENSA_HW_VERSION 260003 /* major*100+minor */ +#define XTENSA_HW_REL_LX6 1 +#define XTENSA_HW_REL_LX6_0 1 +#define XTENSA_HW_REL_LX6_0_3 1 +#define XTENSA_HW_CONFIGID_RELIABLE 1 + +/* If software targets a *range* of hardware versions, these are the bounds: */ + +#define XTENSA_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */ +#define XTENSA_HW_MIN_VERSION_MINOR 3 /* minor v of earliest tgt hw */ +#define XTENSA_HW_MIN_VERSION 260003 /* earliest targeted hw */ +#define XTENSA_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */ +#define XTENSA_HW_MAX_VERSION_MINOR 3 /* minor v of latest tgt hw */ +#define XTENSA_HW_MAX_VERSION 260003 /* latest targeted hw */ + +/* Cache ********************************************************************/ + +#define XTENSA_ICACHE_LINESIZE 4 /* I-cache line size in bytes */ +#define XTENSA_DCACHE_LINESIZE 4 /* D-cache line size in bytes */ +#define XTENSA_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */ +#define XTENSA_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */ + +#define XTENSA_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ +#define XTENSA_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ + +#define XTENSA_DCACHE_IS_WRITEBACK 0 /* writeback feature */ +#define XTENSA_DCACHE_IS_COHERENT 0 /* MP coherence feature */ + +#define XTENSA_HAVE_PREFETCH 0 /* PREFCTL register */ +#define XTENSA_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ +#define XTENSA_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ +#define XTENSA_PREFETCH_ENTRIES 0 /* cache prefetch entries */ +#define XTENSA_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ +#define XTENSA_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ +#define XTENSA_HAVE_ICACHE_TEST 0 /* Icache test instructions */ +#define XTENSA_HAVE_DCACHE_TEST 0 /* Dcache test instructions */ +#define XTENSA_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ +#define XTENSA_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ + +/* Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code */ + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/* Cache ********************************************************************/ + +#define XTENSA_HAVE_PIF 1 /* any outbound PIF present */ +#define XTENSA_HAVE_AXI 0 /* AXI bus */ + +#define XTENSA_HAVE_PIF_WR_RESP 0 /* pif write response */ +#define XTENSA_HAVE_PIF_REQ_ATTR 0 /* pif attribute */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ + +#define XTENSA_ICACHE_SETWIDTH 0 +#define XTENSA_DCACHE_SETWIDTH 0 + +/* Cache set associativity (number of ways): */ + +#define XTENSA_ICACHE_WAYS 1 +#define XTENSA_DCACHE_WAYS 1 + +/* Cache features: */ + +#define XTENSA_ICACHE_LINE_LOCKABLE 0 +#define XTENSA_DCACHE_LINE_LOCKABLE 0 +#define XTENSA_ICACHE_ECC_PARITY 0 +#define XTENSA_DCACHE_ECC_PARITY 0 + +/* Cache access size in bytes (affects operation of SICW instruction): */ + +#define XTENSA_ICACHE_ACCESS_SIZE 1 +#define XTENSA_DCACHE_ACCESS_SIZE 1 + +#define XTENSA_DCACHE_BANKS 0 /* number of banks */ + +/* Number of encoded cache attr bits for decoded bits): */ + +#define XTENSA_CA_BITS 4 + +/* Internal I/D RAM/ROMs and XLMI *******************************************/ + +#define XTENSA_NUM_INSTROM 1 /* number of core instr. ROMs */ +#define XTENSA_NUM_INSTRAM 2 /* number of core instr. RAMs */ +#define XTENSA_NUM_DATAROM 1 /* number of core data ROMs */ +#define XTENSA_NUM_DATARAM 2 /* number of core data RAMs */ +#define XTENSA_NUM_URAM 0 /* number of core unified RAMs*/ +#define XTENSA_NUM_XLMI 1 /* number of core XLMI ports */ + +/* Instruction ROM 0: */ + +#define XTENSA_INSTROM0_VADDR 0x40800000 /* virtual address */ +#define XTENSA_INSTROM0_PADDR 0x40800000 /* physical address */ +#define XTENSA_INSTROM0_SIZE 4194304 /* size in bytes */ +#define XTENSA_INSTROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +/* Instruction RAM 0: */ + +#define XTENSA_INSTRAM0_VADDR 0x40000000 /* virtual address */ +#define XTENSA_INSTRAM0_PADDR 0x40000000 /* physical address */ +#define XTENSA_INSTRAM0_SIZE 4194304 /* size in bytes */ +#define XTENSA_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +/* Instruction RAM 1: */ + +#define XTENSA_INSTRAM1_VADDR 0x40400000 /* virtual address */ +#define XTENSA_INSTRAM1_PADDR 0x40400000 /* physical address */ +#define XTENSA_INSTRAM1_SIZE 4194304 /* size in bytes */ +#define XTENSA_INSTRAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +/* Data ROM 0: */ + +#define XTENSA_DATAROM0_VADDR 0x3F400000 /* virtual address */ +#define XTENSA_DATAROM0_PADDR 0x3F400000 /* physical address */ +#define XTENSA_DATAROM0_SIZE 4194304 /* size in bytes */ +#define XTENSA_DATAROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XTENSA_DATAROM0_BANKS 1 /* number of banks */ + +/* Data RAM 0: */ +#define XTENSA_DATARAM0_VADDR 0x3FF80000 /* virtual address */ +#define XTENSA_DATARAM0_PADDR 0x3FF80000 /* physical address */ +#define XTENSA_DATARAM0_SIZE 524288 /* size in bytes */ +#define XTENSA_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XTENSA_DATARAM0_BANKS 1 /* number of banks */ + +/* Data RAM 1: */ + +#define XTENSA_DATARAM1_VADDR 0x3F800000 /* virtual address */ +#define XTENSA_DATARAM1_PADDR 0x3F800000 /* physical address */ +#define XTENSA_DATARAM1_SIZE 4194304 /* size in bytes */ +#define XTENSA_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XTENSA_DATARAM1_BANKS 1 /* number of banks */ + +/* XLMI Port 0: */ + +#define XTENSA_XLMI0_VADDR 0x3FF00000 /* virtual address */ +#define XTENSA_XLMI0_PADDR 0x3FF00000 /* physical address */ +#define XTENSA_XLMI0_SIZE 524288 /* size in bytes */ +#define XTENSA_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +#define XTENSA_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ + +/* Interrupts and Timers ****************************************************/ + +#define XTENSA_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XTENSA_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XTENSA_HAVE_NMI 1 /* non-maskable interrupt */ +#define XTENSA_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XTENSA_NUM_TIMERS 3 /* number of CCOMPAREn regs */ +#define XTENSA_NUM_INTERRUPTS 32 /* number of interrupts */ +#define XTENSA_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XTENSA_NUM_EXTINTERRUPTS 26 /* num of external interrupts */ +#define XTENSA_INT_NLEVELS 6 /* number of interrupt levels + (not including level zero) */ +#define XTENSA_EXCM_LEVEL 3 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ + +#define XTENSA_INTLEVEL1_MASK 0x000637FF +#define XTENSA_INTLEVEL2_MASK 0x00380000 +#define XTENSA_INTLEVEL3_MASK 0x28C08800 +#define XTENSA_INTLEVEL4_MASK 0x53000000 +#define XTENSA_INTLEVEL5_MASK 0x84010000 +#define XTENSA_INTLEVEL6_MASK 0x00000000 +#define XTENSA_INTLEVEL7_MASK 0x00004000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ + +#define XTENSA_INTLEVEL1_ANDBELOW_MASK 0x000637FF +#define XTENSA_INTLEVEL2_ANDBELOW_MASK 0x003E37FF +#define XTENSA_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF +#define XTENSA_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF +#define XTENSA_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF +#define XTENSA_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFFF +#define XTENSA_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF + +/* Level of each interrupt: */ + +#define XTENSA_INT0_LEVEL 1 +#define XTENSA_INT1_LEVEL 1 +#define XTENSA_INT2_LEVEL 1 +#define XTENSA_INT3_LEVEL 1 +#define XTENSA_INT4_LEVEL 1 +#define XTENSA_INT5_LEVEL 1 +#define XTENSA_INT6_LEVEL 1 +#define XTENSA_INT7_LEVEL 1 +#define XTENSA_INT8_LEVEL 1 +#define XTENSA_INT9_LEVEL 1 +#define XTENSA_INT10_LEVEL 1 +#define XTENSA_INT11_LEVEL 3 +#define XTENSA_INT12_LEVEL 1 +#define XTENSA_INT13_LEVEL 1 +#define XTENSA_INT14_LEVEL 7 +#define XTENSA_INT15_LEVEL 3 +#define XTENSA_INT16_LEVEL 5 +#define XTENSA_INT17_LEVEL 1 +#define XTENSA_INT18_LEVEL 1 +#define XTENSA_INT19_LEVEL 2 +#define XTENSA_INT20_LEVEL 2 +#define XTENSA_INT21_LEVEL 2 +#define XTENSA_INT22_LEVEL 3 +#define XTENSA_INT23_LEVEL 3 +#define XTENSA_INT24_LEVEL 4 +#define XTENSA_INT25_LEVEL 4 +#define XTENSA_INT26_LEVEL 5 +#define XTENSA_INT27_LEVEL 3 +#define XTENSA_INT28_LEVEL 4 +#define XTENSA_INT29_LEVEL 3 +#define XTENSA_INT30_LEVEL 4 +#define XTENSA_INT31_LEVEL 5 +#define XTENSA_DEBUGLEVEL 6 /* debug interrupt level */ +#define XTENSA_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XTENSA_NMILEVEL 7 /* NMI "level" (for use with + * EXCSAVE/EPS/EPC_n, RFI n) */ + +/* Type of each interrupt: */ + +#define XTENSA_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XTENSA_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XTENSA_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XTENSA_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XTENSA_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XTENSA_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XTENSA_INT6_TYPE XTHAL_INTTYPE_TIMER +#define XTENSA_INT7_TYPE XTHAL_INTTYPE_SOFTWARE +#define XTENSA_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XTENSA_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XTENSA_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XTENSA_INT11_TYPE XTHAL_INTTYPE_PROFILING +#define XTENSA_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XTENSA_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XTENSA_INT14_TYPE XTHAL_INTTYPE_NMI +#define XTENSA_INT15_TYPE XTHAL_INTTYPE_TIMER +#define XTENSA_INT16_TYPE XTHAL_INTTYPE_TIMER +#define XTENSA_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XTENSA_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XTENSA_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XTENSA_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XTENSA_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XTENSA_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XTENSA_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XTENSA_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XTENSA_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XTENSA_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XTENSA_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XTENSA_INT28_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XTENSA_INT29_TYPE XTHAL_INTTYPE_SOFTWARE +#define XTENSA_INT30_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XTENSA_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL + +/* Masks of interrupts for each type of interrupt: */ + +#define XTENSA_INTTYPE_MASK_UNCONFIGURED 0x00000000 +#define XTENSA_INTTYPE_MASK_SOFTWARE 0x20000080 +#define XTENSA_INTTYPE_MASK_EXTERN_EDGE 0x50400400 +#define XTENSA_INTTYPE_MASK_EXTERN_LEVEL 0x8FBE333F +#define XTENSA_INTTYPE_MASK_TIMER 0x00018040 +#define XTENSA_INTTYPE_MASK_NMI 0x00004000 +#define XTENSA_INTTYPE_MASK_WRITE_ERROR 0x00000000 +#define XTENSA_INTTYPE_MASK_PROFILING 0x00000800 + +/* Interrupt numbers assigned to specific interrupt sources: */ + +#define XTENSA_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ +#define XTENSA_TIMER1_INTERRUPT 15 /* CCOMPARE1 */ +#define XTENSA_TIMER2_INTERRUPT 16 /* CCOMPARE2 */ +#undef XTENSA_TIMER3_INTERRUPT +#define XTENSA_NMI_INTERRUPT 14 /* non-maskable interrupt */ +#define XTENSA_PROFILING_INTERRUPT 11 /* profiling interrupt */ + +/* Interrupt numbers for levels at which only one interrupt is configured: */ + +#define XTENSA_INTLEVEL7_NUM 14 + +/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */ + +/* External interrupt mapping. + * + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ + +#define XTENSA_EXTINT0_NUM 0 /* (intlevel 1) */ +#define XTENSA_EXTINT1_NUM 1 /* (intlevel 1) */ +#define XTENSA_EXTINT2_NUM 2 /* (intlevel 1) */ +#define XTENSA_EXTINT3_NUM 3 /* (intlevel 1) */ +#define XTENSA_EXTINT4_NUM 4 /* (intlevel 1) */ +#define XTENSA_EXTINT5_NUM 5 /* (intlevel 1) */ +#define XTENSA_EXTINT6_NUM 8 /* (intlevel 1) */ +#define XTENSA_EXTINT7_NUM 9 /* (intlevel 1) */ +#define XTENSA_EXTINT8_NUM 10 /* (intlevel 1) */ +#define XTENSA_EXTINT9_NUM 12 /* (intlevel 1) */ +#define XTENSA_EXTINT10_NUM 13 /* (intlevel 1) */ +#define XTENSA_EXTINT11_NUM 14 /* (intlevel 7) */ +#define XTENSA_EXTINT12_NUM 17 /* (intlevel 1) */ +#define XTENSA_EXTINT13_NUM 18 /* (intlevel 1) */ +#define XTENSA_EXTINT14_NUM 19 /* (intlevel 2) */ +#define XTENSA_EXTINT15_NUM 20 /* (intlevel 2) */ +#define XTENSA_EXTINT16_NUM 21 /* (intlevel 2) */ +#define XTENSA_EXTINT17_NUM 22 /* (intlevel 3) */ +#define XTENSA_EXTINT18_NUM 23 /* (intlevel 3) */ +#define XTENSA_EXTINT19_NUM 24 /* (intlevel 4) */ +#define XTENSA_EXTINT20_NUM 25 /* (intlevel 4) */ +#define XTENSA_EXTINT21_NUM 26 /* (intlevel 5) */ +#define XTENSA_EXTINT22_NUM 27 /* (intlevel 3) */ +#define XTENSA_EXTINT23_NUM 28 /* (intlevel 4) */ +#define XTENSA_EXTINT24_NUM 30 /* (intlevel 4) */ +#define XTENSA_EXTINT25_NUM 31 /* (intlevel 5) */ +/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ +#define XTENSA_INT0_EXTNUM 0 /* (intlevel 1) */ +#define XTENSA_INT1_EXTNUM 1 /* (intlevel 1) */ +#define XTENSA_INT2_EXTNUM 2 /* (intlevel 1) */ +#define XTENSA_INT3_EXTNUM 3 /* (intlevel 1) */ +#define XTENSA_INT4_EXTNUM 4 /* (intlevel 1) */ +#define XTENSA_INT5_EXTNUM 5 /* (intlevel 1) */ +#define XTENSA_INT8_EXTNUM 6 /* (intlevel 1) */ +#define XTENSA_INT9_EXTNUM 7 /* (intlevel 1) */ +#define XTENSA_INT10_EXTNUM 8 /* (intlevel 1) */ +#define XTENSA_INT12_EXTNUM 9 /* (intlevel 1) */ +#define XTENSA_INT13_EXTNUM 10 /* (intlevel 1) */ +#define XTENSA_INT14_EXTNUM 11 /* (intlevel 7) */ +#define XTENSA_INT17_EXTNUM 12 /* (intlevel 1) */ +#define XTENSA_INT18_EXTNUM 13 /* (intlevel 1) */ +#define XTENSA_INT19_EXTNUM 14 /* (intlevel 2) */ +#define XTENSA_INT20_EXTNUM 15 /* (intlevel 2) */ +#define XTENSA_INT21_EXTNUM 16 /* (intlevel 2) */ +#define XTENSA_INT22_EXTNUM 17 /* (intlevel 3) */ +#define XTENSA_INT23_EXTNUM 18 /* (intlevel 3) */ +#define XTENSA_INT24_EXTNUM 19 /* (intlevel 4) */ +#define XTENSA_INT25_EXTNUM 20 /* (intlevel 4) */ +#define XTENSA_INT26_EXTNUM 21 /* (intlevel 5) */ +#define XTENSA_INT27_EXTNUM 22 /* (intlevel 3) */ +#define XTENSA_INT28_EXTNUM 23 /* (intlevel 4) */ +#define XTENSA_INT30_EXTNUM 24 /* (intlevel 4) */ +#define XTENSA_INT31_EXTNUM 25 /* (intlevel 5) */ + +/* Exceptions and Vectors ***************************************************/ + +#define XTENSA_XEA_VERSION 2 /* Xtensa Exception Architecture + * number: 1 == XEA1 (old) + * 2 == XEA2 (new) + * 0 == XEAX (extern) or TX */ +#define XTENSA_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XTENSA_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XTENSA_HAVE_XEAX 0 /* External Exception Arch. */ +#define XTENSA_HAVE_EXCEPTIONS 1 /* exception option */ +#define XTENSA_HAVE_HALT 0 /* halt architecture option */ +#define XTENSA_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ +#define XTENSA_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XTENSA_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XTENSA_HAVE_VECBASE 1 /* relocatable vectors */ +#define XTENSA_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */ +#define XTENSA_VECBASE_RESET_PADDR 0x40000000 +#define XTENSA_RESET_VECBASE_OVERLAP 0 + +#define XTENSA_RESET_VECTOR0_VADDR 0x50000000 +#define XTENSA_RESET_VECTOR0_PADDR 0x50000000 +#define XTENSA_RESET_VECTOR1_VADDR 0x40000400 +#define XTENSA_RESET_VECTOR1_PADDR 0x40000400 +#define XTENSA_RESET_VECTOR_VADDR 0x40000400 +#define XTENSA_RESET_VECTOR_PADDR 0x40000400 +#define XTENSA_USER_VECOFS 0x00000340 +#define XTENSA_USER_VECTOR_VADDR 0x40000340 +#define XTENSA_USER_VECTOR_PADDR 0x40000340 +#define XTENSA_KERNEL_VECOFS 0x00000300 +#define XTENSA_KERNEL_VECTOR_VADDR 0x40000300 +#define XTENSA_KERNEL_VECTOR_PADDR 0x40000300 +#define XTENSA_DOUBLEEXC_VECOFS 0x000003C0 +#define XTENSA_DOUBLEEXC_VECTOR_VADDR 0x400003C0 +#define XTENSA_DOUBLEEXC_VECTOR_PADDR 0x400003C0 +#define XTENSA_WINDOW_OF4_VECOFS 0x00000000 +#define XTENSA_WINDOW_UF4_VECOFS 0x00000040 +#define XTENSA_WINDOW_OF8_VECOFS 0x00000080 +#define XTENSA_WINDOW_UF8_VECOFS 0x000000C0 +#define XTENSA_WINDOW_OF12_VECOFS 0x00000100 +#define XTENSA_WINDOW_UF12_VECOFS 0x00000140 +#define XTENSA_WINDOW_VECTORS_VADDR 0x40000000 +#define XTENSA_WINDOW_VECTORS_PADDR 0x40000000 +#define XTENSA_INTLEVEL2_VECOFS 0x00000180 +#define XTENSA_INTLEVEL2_VECTOR_VADDR 0x40000180 +#define XTENSA_INTLEVEL2_VECTOR_PADDR 0x40000180 +#define XTENSA_INTLEVEL3_VECOFS 0x000001C0 +#define XTENSA_INTLEVEL3_VECTOR_VADDR 0x400001C0 +#define XTENSA_INTLEVEL3_VECTOR_PADDR 0x400001C0 +#define XTENSA_INTLEVEL4_VECOFS 0x00000200 +#define XTENSA_INTLEVEL4_VECTOR_VADDR 0x40000200 +#define XTENSA_INTLEVEL4_VECTOR_PADDR 0x40000200 +#define XTENSA_INTLEVEL5_VECOFS 0x00000240 +#define XTENSA_INTLEVEL5_VECTOR_VADDR 0x40000240 +#define XTENSA_INTLEVEL5_VECTOR_PADDR 0x40000240 +#define XTENSA_INTLEVEL6_VECOFS 0x00000280 +#define XTENSA_INTLEVEL6_VECTOR_VADDR 0x40000280 +#define XTENSA_INTLEVEL6_VECTOR_PADDR 0x40000280 +#define XTENSA_DEBUG_VECOFS XTENSA_INTLEVEL6_VECOFS +#define XTENSA_DEBUG_VECTOR_VADDR XTENSA_INTLEVEL6_VECTOR_VADDR +#define XTENSA_DEBUG_VECTOR_PADDR XTENSA_INTLEVEL6_VECTOR_PADDR +#define XTENSA_NMI_VECOFS 0x000002C0 +#define XTENSA_NMI_VECTOR_VADDR 0x400002C0 +#define XTENSA_NMI_VECTOR_PADDR 0x400002C0 +#define XTENSA_INTLEVEL7_VECOFS XTENSA_NMI_VECOFS +#define XTENSA_INTLEVEL7_VECTOR_VADDR XTENSA_NMI_VECTOR_VADDR +#define XTENSA_INTLEVEL7_VECTOR_PADDR XTENSA_NMI_VECTOR_PADDR + +/* Debug Module *************************************************************/ + +/* Misc */ + +#define XTENSA_HAVE_DEBUG_ERI 1 /* ERI to debug module */ +#define XTENSA_HAVE_DEBUG_APB 1 /* APB to debug module */ +#define XTENSA_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ + +/* On-Chip Debug (OCD) */ + +#define XTENSA_HAVE_OCD 1 /* OnChipDebug option */ +#define XTENSA_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XTENSA_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XTENSA_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ +#define XTENSA_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ + +/* TRAX (in core) */ + +#define XTENSA_HAVE_TRAX 1 /* TRAX in debug module */ +#define XTENSA_TRAX_MEM_SIZE 16384 /* TRAX memory size in bytes */ +#define XTENSA_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ +#define XTENSA_TRAX_ATB_WIDTH 32 /* ATB width (bits), 0=no ATB */ +#define XTENSA_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ + +/* Perf counters */ + +#define XTENSA_NUM_PERF_COUNTERS 2 /* performance counters */ + +/* MMU **********************************************************************/ + +#define XTENSA_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ +#define XTENSA_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ +#define XTENSA_SPANNING_WAY 0 /* TLB spanning way number */ +#define XTENSA_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ +#define XTENSA_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XTENSA_HAVE_MIMIC_CACHEATTR 1 /* region protection */ +#define XTENSA_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XTENSA_HAVE_PTP_MMU 0 /* full MMU (with page table + * [autorefill] and protection) + * usable for an MMU-based OS */ +/* If none of the above last 4 are set, it's a custom TLB configuration. */ + +#define XTENSA_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XTENSA_MMU_RINGS 1 /* number of rings (1..4) */ +#define XTENSA_MMU_RING_BITS 0 /* num of bits in RING field */ + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + +#endif /* __ARCH_XTENSA_INCLUDE_ESP32_CORE_ISA_H */ diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index a218a1f167..8960754da2 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -48,6 +48,7 @@ #include #include +#include /* Include architecture-specific IRQ definitions */ @@ -72,32 +73,31 @@ /* IRQ Stack Frame Format. Each value is a uint32_t register index */ -#define REG_EXIT (0) /* Exit point for dispatch */ -#define REG_PC (1) /* Return PC */ -#define REG_PS (2) /* Return PS */ -#define REG_A0 (3) -#define REG_A1 (4) /* Stack pointer before interrupt */ -#define REG_A2 (5) -#define REG_A3 (6) -#define REG_A4 (7) -#define REG_A5 (8) -#define REG_A6 (9) -#define REG_A7 (10) -#define REG_A8 (11) -#define REG_A9 (12) -#define REG_A10 (13) -#define REG_A11 (14) -#define REG_A12 (15) -#define REG_A13 (16) -#define REG_A14 (17) -#define REG_A15 (18) -#define REG_SAR (19) -#define REG_EXCCAUSE (20) -#define REG_EXCVADDR (21) - -#define _REG_LOOPS_START (22) - -#ifdef CONFIG_XTENSA_HAVE_LOOPS +#define REG_PC (0) /* Return PC */ +#define REG_PS (1) /* Return PS */ +#define REG_A0 (2) +#define REG_A1 (3) /* Stack pointer before interrupt */ +#define REG_A2 (4) +#define REG_A3 (5) +#define REG_A4 (6) +#define REG_A5 (7) +#define REG_A6 (8) +#define REG_A7 (9) +#define REG_A8 (10) +#define REG_A9 (11) +#define REG_A10 (12) +#define REG_A11 (13) +#define REG_A12 (14) +#define REG_A13 (15) +#define REG_A14 (16) +#define REG_A15 (17) +#define REG_SAR (18) +#define REG_EXCCAUSE (19) +#define REG_EXCVADDR (20) + +#define _REG_LOOPS_START (21) + +#ifdef XTENSA_HAVE_LOOPS # define REG_LBEG (_REG_LOOPS_START + 0) # define REG_LEND (_REG_LOOPS_START + 1) # define REG_LCOUNT (_REG_LOOPS_START + 2) diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index deeca55735..e1a21412e8 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -31,6 +31,8 @@ * ****************************************************************************/ + .file "xtensa_context.S" + /* XTENSA CONTEXT SAVE AND RESTORE ROUTINES * * Low-level Call0 functions for handling generic context save and restore @@ -57,14 +59,15 @@ ****************************************************************************/ #include +#include #include #ifdef CONFIG_XTENSA_USE_OVLY # include #endif -#warning REVIST XCHAL_EXTRA_SA_SIZE is not yet provided -#define XCHAL_EXTRA_SA_SIZE 0 /* REMOVE ME */ +#warning REVIST XTENSA_EXTRA_SA_SIZE is not yet provided +#define XTENSA_EXTRA_SA_SIZE 0 /* REMOVE ME */ /**************************************************************************** * Public Functions @@ -155,7 +158,7 @@ _xtensa_context_save: rsr a3, SAR s32i a3, sp, (4 * REG_SAR) -#ifdef CONFIG_XTENSA_HAVE_LOOPS +#ifdef XTENSA_HAVE_LOOPS rsr a3, LBEG s32i a3, sp, (4 * REG_LBEG) rsr a3, LEND @@ -172,7 +175,7 @@ _xtensa_context_save: s32i a3, sp, (4 * REG_VPRI) #endif -#if XCHAL_EXTRA_SA_SIZE > 0 || !defined(CONFIG_XTENSA_CALL0_ABI) +#if XTENSA_EXTRA_SA_SIZE > 0 || !defined(CONFIG_XTENSA_CALL0_ABI) mov a9, a0 /* Preserve ret addr */ #endif @@ -180,7 +183,7 @@ _xtensa_context_save: /* To spill the reg windows, temp. need pre-interrupt stack ptr and * a4-15. Need to save a9,12,13 temporarily (in frame temps) and * recover originals. Interrupts need to be disabled below - * CONFIG_XTENSA_EXCM_LEVEL and window overflow and underflow exceptions + * XTENSA_EXCM_LEVEL and window overflow and underflow exceptions * disabled (assured by PS.EXCM == 1). */ @@ -210,7 +213,7 @@ _xtensa_context_save: l32i a9, sp, (4 * REG_TMP2) #endif -#if XCHAL_EXTRA_SA_SIZE > 0 +#if XTENSA_EXTRA_SA_SIZE > 0 /* NOTE: Normally the xthal_save_extra_nw macro only affects address * registers a2-a5. It is theoretically possible for Xtensa processor * designers to write TIE that causes more address registers to be @@ -221,14 +224,14 @@ _xtensa_context_save: */ addi a2, sp, (4 * REG_EXTRA) /* Where to save it */ -#if XCHAL_EXTRA_SA_ALIGN > 16 - movi a3, -XCHAL_EXTRA_SA_ALIGN +#if XTENSA_EXTRA_SA_ALIGN > 16 + movi a3, -XTENSA_EXTRA_SA_ALIGN and a2, a2, a3 /* Align dynamically >16 bytes */ #endif call0 xthal_save_extra_nw /* Destroys a0,2,3,4,5 */ #endif -#if XCHAL_EXTRA_SA_SIZE > 0 || !defined(CONFIG_XTENSA_CALL0_ABI) +#if XTENSA_EXTRA_SA_SIZE > 0 || !defined(CONFIG_XTENSA_CALL0_ABI) mov a0, a9 /* Retrieve ret addr */ #endif @@ -288,7 +291,7 @@ _xtensa_full_context_restore: _xtensa_context_restore: -#if XCHAL_EXTRA_SA_SIZE > 0 +#if XTENSA_EXTRA_SA_SIZE > 0 /* NOTE: Normally the xthal_restore_extra_nw macro only affects address * registers a2-a5. It is theoretically possible for Xtensa processor * designers to write TIE that causes more address registers to be @@ -301,15 +304,15 @@ _xtensa_context_restore: mov a13, a0 /* Preserve ret addr */ addi a2, sp, (4 * REG_EXTRA) /* Where to find it */ -#if XCHAL_EXTRA_SA_ALIGN > 16 - movi a3, -XCHAL_EXTRA_SA_ALIGN +#if XTENSA_EXTRA_SA_ALIGN > 16 + movi a3, -XTENSA_EXTRA_SA_ALIGN and a2, a2, a3 /* Align dynamically >16 bytes */ #endif call0 xthal_restore_extra_nw /* Destroys a0,2,3,4,5 */ mov a0, a13 /* Retrieve ret addr */ #endif -#ifdef CONFIG_XTENSA_HAVE_LOOPS +#ifdef XTENSA_HAVE_LOOPS l32i a2, sp, (4 * REG_LBEG) l32i a3, sp, (4 * REG_LEND) wsr a2, LBEG diff --git a/arch/xtensa/src/common/xtensa_coproc.S b/arch/xtensa/src/common/xtensa_coproc.S index 92ce8fbaf0..7e9843c796 100644 --- a/arch/xtensa/src/common/xtensa_coproc.S +++ b/arch/xtensa/src/common/xtensa_coproc.S @@ -31,367 +31,15 @@ * ****************************************************************************/ -/* XTENSA CONTEXT SAVE AND RESTORE ROUTINES - * - * Low-level Call0 functions for handling generic context save and restore of - * registers not specifically addressed by the interrupt vectors and handlers. - * Those registers (not handled by these functions) are PC, PS, A0, A1 (SP). - * Except for the calls to RTOS functions, this code is generic to Xtensa. - * - * Note that in Call0 ABI, interrupt handlers are expected to preserve the callee- - * save regs (A12-A15), which is always the case if the handlers are coded in C. - * However A12, A13 are made available as scratch registers for interrupt dispatch - * code, so are presumed saved anyway, and are always restored even in Call0 ABI. - * Only A14, A15 are truly handled as callee-save regs. - * - * Because Xtensa is a configurable architecture, this port supports all user - * generated configurations (except restrictions stated in the release notes). - * This is accomplished by conditional compilation using macros and functions - * defined in the Xtensa HAL (hardware adaptation layer) for your configuration. - * Only the processor state included in your configuration is saved and restored, - * including any processor state added by user configuration options or TIE. - */ + .file "xtensa_coproc.S" /**************************************************************************** * Included Files ****************************************************************************/ -#include "xtensa_context.h" - -#ifdef CONFIG_XTENSA_USE_OVLY -# include -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ .text -/**************************************************************************** - * Name: _xt_coproc_init - * - * Description: - * Initializes global co-processor management data, setting all co- - * processors to "unowned". Leaves CPENABLE as it found it (does NOT clear - * it). - * - * Called during initialization of the RTOS, before any threads run. - * - * This may be called from normal Xtensa single-threaded application code - * which might use co-processors. The Xtensa run-time initialization enables - * all co-processors. They must remain enabled here, else a co-processor - * exception might occur outside of a thread, which the exception handler - * doesn't expect. - * - * Entry Conditions: - * - Xtensa single-threaded run-time environment is in effect. - * No thread is yet running. - * - * Exit conditions: - * - None. - * - * Obeys ABI conventions per prototype: - * void _xt_coproc_init(void) - * - ****************************************************************************/ - -#if CONFIG_XTENSA_NCOPROCESSORS > 0 - .global _xt_coproc_init - .type _xt_coproc_init,@function - .align 4 - .literal_position - .align 4 -_xt_coproc_init: - ENTRY0 - - /* Initialize thread co-processor ownerships to 0 (unowned). */ - - movi a2, _xt_coproc_owner_sa /* a2 = base of owner array */ - addi a3, a2, (XCHAL_CP_MAX*portNUM_PROCESSORS) << 2 /* a3 = top+1 of owner array */ - movi a4, 0 /* a4 = 0 (unowned) */ -1: s32i a4, a2, 0 - addi a2, a2, 4 - bltu a2, a3, 1b - - RET0 -#endif - -/**************************************************************************** - * Name: _xt_coproc_release - * - * Description: - * Releases any and all co-processors owned by a given thread. The thread - * is identified by it's co-processor state save area defined in - * xtensa_context.h. - * - * Must be called before a thread's co-proc save area is deleted to avoid - * memory corruption when the exception handler tries to save the state. - * May be called when a thread terminates or completes but does not delete - * the co-proc save area, to avoid the exception handler having to save - * the thread's co-proc state before another thread can use it - * (optimization). - * - * Entry Conditions: - * - A2 = Pointer to base of co-processor state save area. - * - * Exit conditions: - * - None. - * - * Obeys ABI conventions per prototype: - * void _xt_coproc_release(void * coproc_sa_base) - * - ****************************************************************************/ - -#if CONFIG_XTENSA_NCOPROCESSORS > 0 - .global _xt_coproc_release - .type _xt_coproc_release,@function - .align 4 - .literal_position - .align 4 -_xt_coproc_release: - ENTRY0 /* a2 = base of save area */ - - getcoreid a5 - movi a3, XCHAL_CP_MAX << 2 - mull a5, a5, a3 - movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */ - add a3, a3, a5 - - addi a4, a3, XCHAL_CP_MAX << 2 /* a4 = top+1 of owner array */ - movi a5, 0 /* a5 = 0 (unowned) */ - - rsil a6, CONFIG_XTENSA_EXCM_LEVEL /* Lock interrupts */ - -1: l32i a7, a3, 0 /* a7 = owner at a3 */ - bne a2, a7, 2f /* if (coproc_sa_base == owner) */ - s32i a5, a3, 0 /* owner = unowned */ -2: addi a3, a3, 1 << 2 /* a3 = next entry in owner array */ - bltu a3, a4, 1b /* Repeat until end of array */ - -3: wsr a6, PS /* Restore interrupts */ - - RET0 -#endif - -/**************************************************************************** - * Name: _xt_coproc_savecs - * - * Description: - * If there is a current thread and it has a coprocessor state save area, - * then save all callee-saved state into this area. This function is called - * from the solicited context switch handler. It calls a system-specific - * function to get the coprocessor save area base address. - * - * Entry conditions: - * - The thread being switched out is still the current thread. - * - CPENABLE state reflects which coprocessors are active. - * - Registers have been saved/spilled already. - * - * Exit conditions: - * - All necessary CP callee-saved state has been saved. - * - Registers a2-a7, a13-a15 have been trashed. - * - * Must be called from assembly code only, using CALL0. - * - ****************************************************************************/ - -#if CONFIG_XTENSA_NCOPROCESSORS > 0 - .extern _xt_coproc_sa_offset /* external reference */ - .global _xt_coproc_savecs - .type _xt_coproc_savecs,@function - .align 4 - .literal_position - .align 4 -_xt_coproc_savecs: - - /* At entry, CPENABLE should be showing which CPs are enabled. */ - - rsr a2, CPENABLE /* a2 = which CPs are enabled */ - beqz a2, .Ldone /* quick exit if none */ - mov a14, a0 /* save return address */ - call0 XT_RTOS_CP_STATE /* get address of CP save area */ - mov a0, a14 /* restore return address */ - beqz a15, .Ldone /* if none then nothing to do */ - s16i a2, a15, XT_CP_CS_ST /* save mask of CPs being stored */ - movi a13, _xt_coproc_sa_offset /* array of CP save offsets */ - l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ - -#if XCHAL_CP0_SA_SIZE - bbci.l a2, 0, 2f /* CP 0 not enabled */ - l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ - add a3, a14, a15 /* a3 = save area for CP 0 */ - xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP1_SA_SIZE - bbci.l a2, 1, 2f /* CP 1 not enabled */ - l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ - add a3, a14, a15 /* a3 = save area for CP 1 */ - xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP2_SA_SIZE - bbci.l a2, 2, 2f - l32i a14, a13, 8 - add a3, a14, a15 - xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP3_SA_SIZE - bbci.l a2, 3, 2f - l32i a14, a13, 12 - add a3, a14, a15 - xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP4_SA_SIZE - bbci.l a2, 4, 2f - l32i a14, a13, 16 - add a3, a14, a15 - xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP5_SA_SIZE - bbci.l a2, 5, 2f - l32i a14, a13, 20 - add a3, a14, a15 - xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP6_SA_SIZE - bbci.l a2, 6, 2f - l32i a14, a13, 24 - add a3, a14, a15 - xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP7_SA_SIZE - bbci.l a2, 7, 2f - l32i a14, a13, 28 - add a3, a14, a15 - xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -.Ldone: - ret -#endif - -/**************************************************************************** - * Name: _xt_coproc_restorecs - * - * Description: - * Restore any callee-saved coprocessor state for the incoming thread. - * This function is called from coprocessor exception handling, when - * giving ownership to a thread that solicited a context switch earlier. - * It calls a system-specific function to get the coprocessor save area - * base address. - * - * Entry conditions: - * - The incoming thread is set as the current thread. - * - CPENABLE is set up correctly for all required coprocessors. - * - a2 = mask of coprocessors to be restored. - * - * Exit conditions: - * - All necessary CP callee-saved state has been restored. - * - CPENABLE - unchanged. - * - Registers a2-a7, a13-a15 have been trashed. - * - * Must be called from assembly code only, using CALL0. - * - ****************************************************************************/ - -#if CONFIG_XTENSA_NCOPROCESSORS > 0 - .global _xt_coproc_restorecs - .type _xt_coproc_restorecs,@function - .align 4 - .literal_position - .align 4 -_xt_coproc_restorecs: - - mov a14, a0 /* Save return address */ - call0 XT_RTOS_CP_STATE /* Get address of CP save area */ - mov a0, a14 /* Restore return address */ - beqz a15, .Ldone2 /* If none then nothing to do */ - l16ui a3, a15, XT_CP_CS_ST /* a3 = which CPs have been saved */ - xor a3, a3, a2 /* Clear the ones being restored */ - s32i a3, a15, XT_CP_CS_ST /* Update saved CP mask */ - movi a13, _xt_coproc_sa_offset /* Array of CP save offsets */ - l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ - -#if XCHAL_CP0_SA_SIZE - bbci.l a2, 0, 2f /* CP 0 not enabled */ - l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ - add a3, a14, a15 /* a3 = save area for CP 0 */ - xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP1_SA_SIZE - bbci.l a2, 1, 2f /* CP 1 not enabled */ - l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ - add a3, a14, a15 /* a3 = save area for CP 1 */ - xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP2_SA_SIZE - bbci.l a2, 2, 2f - l32i a14, a13, 8 - add a3, a14, a15 - xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP3_SA_SIZE - bbci.l a2, 3, 2f - l32i a14, a13, 12 - add a3, a14, a15 - xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP4_SA_SIZE - bbci.l a2, 4, 2f - l32i a14, a13, 16 - add a3, a14, a15 - xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP5_SA_SIZE - bbci.l a2, 5, 2f - l32i a14, a13, 20 - add a3, a14, a15 - xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP6_SA_SIZE - bbci.l a2, 6, 2f - l32i a14, a13, 24 - add a3, a14, a15 - xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -#if XCHAL_CP7_SA_SIZE - bbci.l a2, 7, 2f - l32i a14, a13, 28 - add a3, a14, a15 - xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL -2: -#endif - -.Ldone2: - ret - -#endif diff --git a/arch/xtensa/src/common/xtensa_dumpstate.c b/arch/xtensa/src/common/xtensa_dumpstate.c index 97128013cf..8096e887f1 100644 --- a/arch/xtensa/src/common/xtensa_dumpstate.c +++ b/arch/xtensa/src/common/xtensa_dumpstate.c @@ -46,7 +46,9 @@ #include #include + #include +#include #include "sched/sched.h" #include "xtensa.h" @@ -125,7 +127,7 @@ static inline void xtensa_registerdump(void) (unsigned long)g_current_regs[REG_EXIT], (unsigned long)g_current_regs[REG_EXCCAUSE], (unsigned long)g_current_regs[REG_EXCVADDR]); -#ifdef CONFIG_XTENSA_HAVE_LOOPS +#ifdef XTENSA_HAVE_LOOPS _alert(" LBEG: %08lx LEND: %08lx LCNT: %08lx\n", (unsigned long)g_current_regs[REG_LBEG], (unsigned long)g_current_regs[REG_LEND], diff --git a/arch/xtensa/src/common/xtensa_initialstate.c b/arch/xtensa/src/common/xtensa_initialstate.c index d447f49ad2..dab7af55cd 100644 --- a/arch/xtensa/src/common/xtensa_initialstate.c +++ b/arch/xtensa/src/common/xtensa_initialstate.c @@ -45,15 +45,11 @@ #include #include +#include #include "xtensa.h" #include "xtensa_corebits.h" -/* Temporary for clean compile */ - -#warning REVISIT _xt_user_exit -void _xt_user_exit(void); - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -89,7 +85,6 @@ void up_initial_state(struct tcb_s *tcb) xcp->regs[REG_PC] = (uint32_t)tcb->start; /* Task entrypoint */ xcp->regs[REG_A0] = 0; /* To terminate GDB backtrace */ xcp->regs[REG_A1] = (uint32_t)tcb->adj_stack_ptr; /* Physical top of stack frame */ - xcp->regs[REG_EXIT] = (uint32_t)_xt_user_exit; /* User exception exit dispatcher */ /* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user * mode. @@ -122,7 +117,7 @@ void up_initial_state(struct tcb_s *tcb) ptr = (uint32_t *)(((uint32_t)tcb->adj_stack_ptr - XT_CP_SIZE) & ~0xf); ptr[0] = 0; ptr[1] = 0; - ptr[2] = (((uint32_t)ptr) + 12 + XCHAL_TOTAL_SA_ALIGN - 1) & -XCHAL_TOTAL_SA_ALIGN; + ptr[2] = (((uint32_t)ptr) + 12 + XTENSA_TOTAL_SA_ALIGN - 1) & -XTENSA_TOTAL_SA_ALIGN; #endif #endif /* REVISIT */ } diff --git a/arch/xtensa/src/common/xtensa_inthandlers.S b/arch/xtensa/src/common/xtensa_inthandlers.S new file mode 100644 index 0000000000..0eee1a2e74 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_inthandlers.S @@ -0,0 +1,512 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_inthandlers.S + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * + * Copyright (c) 2006-2015 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + ****************************************************************************/ + + .file "xtensa_inthandlers.S" + +/* NOTES on the use of 'call0' for long jumps instead of 'j': + * + * 1. This file should be assembled with the -mlongcalls option to xt-xcc. + * + * 2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to + * a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the + * distance from the call to the destination. The linker then relaxes + * it back to 'call0 dest' if it determines that dest is within range. + * This allows more flexibility in locating code without the performance + * overhead of the 'l32r' literal data load in cases where the destination + * is in range of 'call0'. There is an additional benefit in that 'call0' + * has a longer range than 'j' due to the target being word-aligned, so + * the 'l32r' sequence is less likely needed. + * + * 3. The use of 'call0' with -mlongcalls requires that register a0 not be + * live at the time of the call, which is always the case for a function + * call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'. + * + * 4. This use of 'call0' is independent of the C function call ABI. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "xtensa_specregs.h" +#include "xtensa_macros.h" +#include "xtensa_timer.h" + +/**************************************************************************** + * Assembly Language Macros + ****************************************************************************/ + +/* Macro extract_msb - return the input with only the highest bit set. + * + * Input : "ain" - Input value, clobbered. + * Output : "aout" - Output value, has only one bit set, MSB of "ain". + * The two arguments must be different AR registers. + */ + + .macro extract_msb aout ain +1: + addi \aout, \ain, -1 /* aout = ain - 1 */ + and \ain, \ain, \aout /* ain = ain & aout */ + bnez \ain, 1b /* repeat until ain == 0 */ + addi \aout, \aout, 1 /* return aout + 1 */ + .endm + +/* Macro dispatch_c_isr - dispatch interrupts to user ISRs. + * This will dispatch to user handlers (if any) that are registered in the + * XTOS dispatch table (_xtos_interrupt_table). These handlers would have + * been registered by calling _xtos_set_interrupt_handler(). There is one + * exception - the timer interrupt used by the OS will not be dispatched + * to a user handler - this must be handled by the caller of this macro. + * + * Level triggered and software interrupts are automatically deasserted by + * this code. + * + * ASSUMPTIONS: + * - PS.INTLEVEL is set to "level" at entry + * - PS.EXCM = 0, C calling enabled + * + * NOTE: This macro will use registers a0 and a2-a6. The arguments are: + * level -- interrupt level + * mask -- interrupt bitmask for this level + */ + + .macro dispatch_c_isr level mask + + /* Get mask of pending, enabled interrupts at this level into a2. */ + +.L_xt_user_int_&level&: + rsr a2, INTENABLE + rsr a3, INTERRUPT + movi a4, \mask + and a2, a2, a3 + and a2, a2, a4 + beqz a2, 9f /* Nothing to do */ + + /* This bit of code provides a nice debug backtrace in the debugger. + * It does take a few more instructions, so undef XT_DEBUG_BACKTRACE + * if you want to save the cycles. + * / + +#if XT_DEBUG_BACKTRACE +#ifndef CONFIG_XTENSA_CALL0_ABI + rsr a0, EPC_1 + \level - 1 /* Return address */ + movi a4, 0xC0000000 /* Constant with top 2 bits set (call size) */ + or a0, a0, a4 /* Set top 2 bits */ + addx2 a0, a4, a0 /* Clear top bit -- simulating call4 size */ +#endif +#endif + +#ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + + movi a4, _xt_intexc_hooks + l32i a4, a4, \level << 2 + beqz a4, 2f + +#ifdef CONFIG_XTENSA_CALL0_ABI + callx0 a4 + beqz a2, 9f +#else + mov a6, a2 + callx4 a4 + beqz a6, 9f + mov a2, a6 +#endif +2: +#endif + + /* Now look up in the dispatch table and call user ISR if any. */ + /* If multiple bits are set then MSB has highest priority. */ + + extract_msb a4, a2 /* a4 = MSB of a2, a2 trashed */ + +#ifdef CONFIG_XTENSA_USE_SWPRI + /* Enable all interrupts at this level that are numerically higher + * than the one we just selected, since they are treated as higher + * priority. + */ + + movi a3, \mask /* a3 = all interrupts at this level */ + add a2, a4, a4 /* a2 = a4 << 1 */ + addi a2, a2, -1 /* a2 = mask of 1's <= a4 bit */ + and a2, a2, a3 /* a2 = mask of all bits <= a4 at this level */ + movi a3, _xt_intdata + l32i a6, a3, 4 /* a6 = _xt_vpri_mask */ + neg a2, a2 + addi a2, a2, -1 /* a2 = mask to apply */ + and a5, a6, a2 /* mask off all bits <= a4 bit */ + s32i a5, a3, 4 /* update _xt_vpri_mask */ + rsr a3, INTENABLE + and a3, a3, a2 /* mask off all bits <= a4 bit */ + wsr a3, INTENABLE + rsil a3, \level - 1 /* lower interrupt level by 1 */ +#endif + + movi a3, XT_TIMER_INTEN /* a3 = timer interrupt bit */ + wsr a4, INTCLEAR /* Clear sw or edge-triggered interrupt */ + beq a3, a4, 7f /* If timer interrupt then skip table */ + + find_ms_setbit a3, a4, a3, 0 /* a3 = interrupt number */ + + movi a4, _xt_interrupt_table + addx8 a3, a3, a4 /* a3 = address of interrupt table entry */ + l32i a4, a3, XIE_HANDLER /* a4 = handler address */ + +#ifdef CONFIG_XTENSA_CALL0_ABI + mov a12, a6 /* Save in callee-saved reg */ + l32i a2, a3, XIE_ARG /* a2 = handler arg */ + callx0 a4 /* call handler */ + mov a2, a12 +#else + mov a2, a6 /* Save in windowed reg */ + l32i a6, a3, XIE_ARG /* a6 = handler arg */ + callx4 a4 /* Call handler */ +#endif + +#ifdef CONFIG_XTENSA_USE_SWPRI + j 8f +#else + j .L_xt_user_int_&level& /* Check for more interrupts */ +#endif + +7: + + .ifeq XT_TIMER_INTPRI - \level +.L_xt_user_int_timer_&level&: + /* Interrupt handler for the RTOS tick timer if at this level. + We'll be reading the interrupt state again after this call + so no need to preserve any registers except a6 (vpri_mask). + */ + +#ifdef CONFIG_XTENSA_CALL0_ABI + mov a12, a6 + call0 XT_RTOS_TIMER_INT + mov a2, a12 +#else + mov a2, a6 + call4 XT_RTOS_TIMER_INT +#endif + .endif + +#ifdef CONFIG_XTENSA_USE_SWPRI + j 8f +#else + j .L_xt_user_int_&level& /* check for more interrupts */ +#endif + +#ifdef CONFIG_XTENSA_USE_SWPRI +8: + /* Restore old value of _xt_vpri_mask from a2. Also update INTENABLE from + virtual _xt_intenable which _could_ have changed during interrupt + processing. */ + + movi a3, _xt_intdata + l32i a4, a3, 0 /* a4 = _xt_intenable */ + s32i a2, a3, 4 /* update _xt_vpri_mask */ + and a4, a4, a2 /* a4 = masked intenable */ + wsr a4, INTENABLE /* update INTENABLE */ +#endif + +9: + /* done */ + + .endm + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * MEDIUM PRIORITY (LEVEL 2+) INTERRUPT VECTORS AND LOW LEVEL HANDLERS. + * + * C Prototype: + * void _xtensa_levelN_handler(void) + * + * Description: + * Medium priority interrupts are by definition those with priority greater + * than 1 and not greater than XTENSA_EXCM_LEVEL. These are disabled + * by setting PS.EXCM and therefore can easily support a C environment for + * handlers in C, and interact safely with NuttX. + * + * Each vector goes at a predetermined location according to the Xtensa + * hardware configuration, which is ensured by its placement in a special + * section known to the NuttX linker script. The vector logic performs + * the minimum necessary operations before jumping to the handler via + * a CALL0 instruction. See "NOTES on the use of call0 ..." above. + * + * The corresponding handler sets up the appropriate stack frame, saves + * a few vector-specific registers and calls _xtensa_full_context_save() + * to save the rest of the interrupted context. It then calls the C + * logic to decode the specific interrupt source and dispatch to the + * appropriate C interrupt handler. + * + ****************************************************************************/ + +#if XTENSA_EXCM_LEVEL >= 2 + .section .iram1,"ax" + .type _xtensa_level2_handler,@function + .align 4 +_xtensa_level2_handler: + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * REG_FRMSZ) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS_2 /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EPC_2 /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE_2 /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) + + /* Save rest of interrupt context and enter RTOS. */ + + call0 _xtensa_full_context_save /* Save full register state */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + +#ifdef CONFIG_XTENSA_CALL0_ABI + movi a0, PS_INTLEVEL(2) | PS_UM + #else + movi a0, PS_INTLEVEL(2) | PS_UM | PS_WOE +#endif + wsr a0, PS + rsync + + /* Decode and dispatch the interrupt. In the event of an interrupt + * level context xtensa_int_decode() will return a pointer to the new + * register state in A2. + */ + + dispatch_c_isr 2 XTENSA_INTLEVEL2_MASK + + /* Restore registers in preparation to return from interrupt */ + + call0 _xtensa_int_exit /* does not return directly here */ + + /* Restore only level-specific regs (the rest were already restored) */ + + l32i a0, sp, (4 * REG_PS) /* retrieve interruptee's PS */ + wsr a0, EPS_2 + l32i a0, sp, (4 * REG_PC) /* retrieve interruptee's PC */ + wsr a0, EPC_2 + l32i a0, sp, (4 * REG_A0) /* retrieve interruptee's A0 */ + l32i sp, sp, (4 * REG_A1) /* remove interrupt stack frame */ + rsync /* Ensure EPS and EPC written */ + + /* Return from interrupt. RFI restores the PS from EPS_2 and jumps to + * the address in EPC_2. + */ + + rfi 2 + +#endif /* XTENSA_EXCM_LEVEL >= 2 */ + +/******************************************************************************* + +HIGH PRIORITY (LEVEL > XTENSA_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS + +High priority interrupts are by definition those with priorities greater +than XTENSA_EXCM_LEVEL. This includes non-maskable (NMI). High priority +interrupts cannot interact with the RTOS, that is they must save all regs +they use and not call any RTOS function. + +A further restriction imposed by the Xtensa windowed architecture is that +high priority interrupts must not modify the stack area even logically +"above" the top of the interrupted stack (they need to provide their +own stack or static save area). + +Cadence Design Systems recommends high priority interrupt handlers be coded in assembly +and used for purposes requiring very short service times. + +Here are templates for high priority (level 2+) interrupt vectors. +They assume only one interrupt per level to avoid the burden of identifying +which interrupts at this level are pending and enabled. This allows for +minimum latency and avoids having to save/restore a2 in addition to a0. +If more than one interrupt per high priority level is configured, this burden +is on the handler which in any case must provide a way to save and restore +registers it uses without touching the interrupted stack. + +Each vector goes at a predetermined location according to the Xtensa +hardware configuration, which is ensured by its placement in a special +section known to the Xtensa linker support package (LSP). It performs +the minimum necessary before jumping to the handler in the .text section. + +*******************************************************************************/ + +/* +Currently only shells for high priority interrupt handlers are provided +here. However a template and example can be found in the Cadence Design Systems tools +documentation: "Microprocessor Programmer's Guide". +*/ + +#if XTENSA_INT_NLEVELS >=2 && XTENSA_EXCM_LEVEL < 2 && XTENSA_DEBUGLEVEL !=2 + .section .iram1,"ax" + .type _xtensa_level2_handler, @function + .align 4 +_xtensa_level2_handler: + +#ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + + movi a0, _xt_intexc_hooks + l32i a0, a0, 2<<2 + beqz a0, 1f +.Ln_xtensa_level2_handler_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: +#endif + + /* USER_EDIT: + ADD HIGH PRIORITY LEVEL 2 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 +.L_xtensa_level2_handler_exit: + rsr a0, EXCSAVE_2 /* restore a0 */ + rfi 2 + +#endif /* XTENSA_INT_NLEVELS >=2 && XTENSA_EXCM_LEVEL < 2 && XTENSA_DEBUGLEVEL !=2 */ + +#if XTENSA_INT_NLEVELS >=3 && XTENSA_EXCM_LEVEL < 3 && XTENSA_DEBUGLEVEL !=3 + .section .iram1,"ax" + .type _xtensa_level3_handler,@function + .align 4 +_xtensa_level3_handler: + +#ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + + movi a0, _xt_intexc_hooks + l32i a0, a0, 3<<2 + beqz a0, 1f +.Ln_xtensa_level3_handler_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: +#endif + + /* USER_EDIT: + ADD HIGH PRIORITY LEVEL 3 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 +.L_xtensa_level3_handler_exit: + rsr a0, EXCSAVE_3 /* restore a0 */ + rfi 3 + +#endif /* XTENSA_INT_NLEVELS >=3 && XTENSA_EXCM_LEVEL < 3 && XTENSA_DEBUGLEVEL !=3 */ + +#if XTENSA_INT_NLEVELS >=4 && XTENSA_EXCM_LEVEL < 4 && XTENSA_DEBUGLEVEL !=4 + .section .iram1,"ax" + .type _xtensa_level4_handler,@function + .align 4 +_xtensa_level4_handler: + +#ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + + movi a0, _xt_intexc_hooks + l32i a0, a0, 4<<2 + beqz a0, 1f +.Ln_xtensa_level4_handler_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: +#endif + + /* USER_EDIT: + ADD HIGH PRIORITY LEVEL 4 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 +.L_xtensa_level4_handler_exit: + rsr a0, EXCSAVE_4 /* restore a0 */ + rfi 4 + +#endif /* XTENSA_INT_NLEVELS >=4 && XTENSA_EXCM_LEVEL < 4 && XTENSA_DEBUGLEVEL !=4 */ + +#if XTENSA_INT_NLEVELS >=5 && XTENSA_EXCM_LEVEL < 5 && XTENSA_DEBUGLEVEL !=5 + .section .iram1,"ax" + .type _xtensa_level5_handler,@function + .align 4 +_xtensa_level5_handler: + +#ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + + movi a0, _xt_intexc_hooks + l32i a0, a0, 5<<2 + beqz a0, 1f +.Ln_xtensa_level5_handler_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: +#endif + + /* USER_EDIT: + ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 +.L_xtensa_level5_handler_exit: + rsr a0, EXCSAVE_5 /* restore a0 */ + rfi 5 + +#endif /* XTENSA_INT_NLEVELS >=5 && XTENSA_EXCM_LEVEL < 5 && XTENSA_DEBUGLEVEL !=5 */ + +#if XTENSA_INT_NLEVELS >=6 && XTENSA_EXCM_LEVEL < 6 && XTENSA_DEBUGLEVEL !=6 + .section .iram1,"ax" + .type _xtensa_level6_handler, @function + .align 4 +_xtensa_level6_handler: + +#ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + + movi a0, _xt_intexc_hooks + l32i a0, a0, 6<<2 + beqz a0, 1f +.Ln_xtensa_level6_handler_call_hook: + callx0 a0 /* must NOT disturb stack! */ +1: +#endif + + /* USER_EDIT: + ADD HIGH PRIORITY LEVEL 6 INTERRUPT HANDLER CODE HERE. + */ + + .align 4 +.L_xtensa_level6_handler_exit: + rsr a0, EXCSAVE_6 /* restore a0 */ + rfi 6 + +#endif /* XTENSA_INT_NLEVELS >=6 && XTENSA_EXCM_LEVEL < 6 && XTENSA_DEBUGLEVEL !=6 */ diff --git a/arch/xtensa/src/common/xtensa_intvectors.S b/arch/xtensa/src/common/xtensa_intvectors.S index cf84869b3c..c7da5a7478 100644 --- a/arch/xtensa/src/common/xtensa_intvectors.S +++ b/arch/xtensa/src/common/xtensa_intvectors.S @@ -58,7 +58,7 @@ * ****************************************************************************/ -#if CONFIG_XTENSA_EXCM_LEVEL >= 2 +#if XTENSA_EXCM_LEVEL >= 2 .begin literal_prefix .xtensa_level2_vector .section .xtensa_level2_vector.text, "ax" .global _xtensa_level2_vector @@ -77,7 +77,7 @@ _xtensa_level2_vector: .size _xtensa_level2_vector, . - _xtensa_level2_vector #endif -#if CONFIG_XTENSA_EXCM_LEVEL >= 3 +#if XTENSA_EXCM_LEVEL >= 3 .begin literal_prefix .xtensa_level3_vector .section .xtensa_level3_vector.text, "ax" .global _xtensa_level3_vector @@ -96,7 +96,7 @@ _xtensa_level3_vector: .size _xtensa_level3_vector, . - _xtensa_level3_vector #endif -#if CONFIG_XTENSA_EXCM_LEVEL >= 4 +#if XTENSA_EXCM_LEVEL >= 4 .begin literal_prefix .xtensa_level4_vector .section .xtensa_level4_vector.text, "ax" .global _xtensa_level4_vector @@ -115,7 +115,7 @@ _xtensa_level4_vector: .size _xtensa_level5_vector, . - _xtensa_level5_vector #endif -#if CONFIG_XTENSA_EXCM_LEVEL >= 5 +#if XTENSA_EXCM_LEVEL >= 5 .begin literal_prefix .xtensa_level5_vector .section .xtensa_level5_vector.text, "ax" .global _xtensa_level5_vector @@ -134,7 +134,7 @@ _xtensa_level5_vector: .size _xtensa_level5_vector, . - _xtensa_level5_vector #endif -#if CONFIG_XTENSA_EXCM_LEVEL >= 6 +#if XTENSA_EXCM_LEVEL >= 6 .begin literal_prefix .xtensa_level6_vector .section .xtensa_level6_vector.text, "ax" .global _xtensa_level6_vector diff --git a/arch/xtensa/src/common/xtensa_timer.h b/arch/xtensa/src/common/xtensa_timer.h new file mode 100644 index 0000000000..6adf77fea3 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_timer.h @@ -0,0 +1,147 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_irq.S + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * Copyright (c) 2003-2015 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + *******************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_TIMER_H +#define __ARCH_XTENSA_SRC_COMMON_XTENSA_TIMER_H + +#ifdef __ASSEMBLER__ +#include +#endif + +#include +#include + +/* Select timer to use for periodic tick, and determine its interrupt number + * and priority. User may specify a timer by defining XT_TIMER_INDEX with -D, + * in which case its validity is checked (it must exist in this core and must + * not be on a high priority interrupt - an error will be reported in invalid). + * Otherwise select the first low or medium priority interrupt timer available. + */ + +#if XTENSA_NUM_TIMERS == 0 + +# error "This Xtensa configuration is unsupported, it has no timers." + +#else + +#ifndef XT_TIMER_INDEX +# if XTENSA_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED +# if XTENSA_INT_LEVEL(XTENSA_TIMER3_INTERRUPT) <= XTENSA_EXCM_LEVEL +# undef XT_TIMER_INDEX +# define XT_TIMER_INDEX 3 +# endif +# endif +# if XTENSA_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED +# if XTENSA_INT_LEVEL(XTENSA_TIMER2_INTERRUPT) <= XTENSA_EXCM_LEVEL +# undef XT_TIMER_INDEX +# define XT_TIMER_INDEX 2 +# endif +# endif +# if XTENSA_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED +# if XTENSA_INT_LEVEL(XTENSA_TIMER1_INTERRUPT) <= XTENSA_EXCM_LEVEL +# undef XT_TIMER_INDEX +# define XT_TIMER_INDEX 1 +# endif +# endif +# if XTENSA_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED +# if XTENSA_INT_LEVEL(XTENSA_TIMER0_INTERRUPT) <= XTENSA_EXCM_LEVEL +# undef XT_TIMER_INDEX +# define XT_TIMER_INDEX 0 +# endif +# endif +#endif +#ifndef XT_TIMER_INDEX +# error "There is no suitable timer in this Xtensa configuration." +#endif + +#define XT_CCOMPARE (CCOMPARE + XT_TIMER_INDEX) +#define XT_TIMER_INTNUM XTENSA_TIMER_INTERRUPT(XT_TIMER_INDEX) +#define XT_TIMER_INTPRI XTENSA_INT_LEVEL(XT_TIMER_INTNUM) +#define XT_TIMER_INTEN (1 << XT_TIMER_INTNUM) + +#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED +# error "The timer selected by XT_TIMER_INDEX does not exist in this core." +#elif XT_TIMER_INTPRI > XTENSA_EXCM_LEVEL +# error "The timer interrupt cannot be high priority (use medium or low)." +#endif + +#endif /* XTENSA_NUM_TIMERS */ + +/* Set processor clock frequency, used to determine clock divisor for timer + * tick. User should BE SURE TO ADJUST THIS for the Xtensa platform being + * used. If using a supported board via the board-independent API defined in + * xtbsp.h, this may be left undefined and frequency and tick divisor will + * be computed and cached during run-time initialization. + * + * NOTE ON SIMULATOR: + * Under the Xtensa instruction set simulator, the frequency can only be + * estimated because it depends on the speed of the host and the version of + * the simulator. Also because it runs much slower than hardware, it is not + * possible to achieve real-time performance for most applications under the + * simulator. A frequency too low does not allow enough time between timer + * interrupts, starving threads. To obtain a more convenient but non-real- + * time tick duration on the simulator, compile with xt-xcc option + * "-DXT_SIMULATOR". Adjust this frequency to taste (it's not real-time + * anyway!). + */ + +#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ) +# define XT_CLOCK_FREQ +#endif + +#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD) +# error "XT_CLOCK_FREQ must be defined for the target platform." +#endif + +/* Default number of timer "ticks" per second (default 100 for 10ms tick). + * RTOS may define this in its own way (if applicable) in xtensa_rtos.h. + * User may redefine this to an optimal value for the application, either by + * editing this here or in xtensa_rtos.h, or compiling with xt-xcc option + * "-DXT_TICK_PER_SEC=" where is a suitable number. + */ + +#ifndef XT_TICK_PER_SEC +# define XT_TICK_PER_SEC (1000000 / CONFIG_USEC_PER_TICK) +#endif + +/* Derivation of clock divisor for timer tick and interrupt (one per tick). */ + +#ifdef XT_CLOCK_FREQ +# define XT_TICK_DIVISOR (XT_CLOCK_FREQ / XT_TICK_PER_SEC) +#endif + +#ifndef __ASSEMBLER__ +extern unsigned _xt_tick_divisor; +void _xt_tick_divisor_init(void); +#endif + +#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_TIMER_H */ -- GitLab From 30c4a41332394dd0f34ea8c1c5ffea0c79918d7e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 20 Oct 2016 11:33:53 -0600 Subject: [PATCH 149/734] Fix a few compile-related issues --- arch/xtensa/src/common/xtensa_dumpstate.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_dumpstate.c b/arch/xtensa/src/common/xtensa_dumpstate.c index 8096e887f1..ae260f0e6d 100644 --- a/arch/xtensa/src/common/xtensa_dumpstate.c +++ b/arch/xtensa/src/common/xtensa_dumpstate.c @@ -99,8 +99,7 @@ static inline void xtensa_registerdump(void) if (g_current_regs != NULL) { - _alert(" EXIT: %08lx PC: %08lx PS: %08lx\n", - (unsigned long)g_current_regs[REG_EXIT], + _alert(" PC: %08lx PS: %08lx\n", (unsigned long)g_current_regs[REG_PC], (unsigned long)g_current_regs[REG_PS]); _alert(" A0: %08lx A1: %08lx A2: %08lx A3: %08lx\n", @@ -124,7 +123,7 @@ static inline void xtensa_registerdump(void) (unsigned long)g_current_regs[REG_A14], (unsigned long)g_current_regs[REG_A15]); _alert(" SAR: %08lx CAUSE: %08lx VADDR: %08lx\n", - (unsigned long)g_current_regs[REG_EXIT], + (unsigned long)g_current_regs[REG_SAR], (unsigned long)g_current_regs[REG_EXCCAUSE], (unsigned long)g_current_regs[REG_EXCVADDR]); #ifdef XTENSA_HAVE_LOOPS -- GitLab From 30ab01b1d8f02dc8212e1524900143206c3a4a7f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 20 Oct 2016 12:07:12 -0600 Subject: [PATCH 150/734] strtof: Add strtof() as simply a compy of strtod with types and limits changed --- include/stdlib.h | 14 ++++---------- libc/stdlib/Make.defs | 2 +- libc/stdlib/lib_strtod.c | 2 +- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/include/stdlib.h b/include/stdlib.h index 10ec6c2629..09eb2cf6c0 100644 --- a/include/stdlib.h +++ b/include/stdlib.h @@ -80,18 +80,11 @@ # define environ get_environ_ptr() #endif -/* The functions strtof() and strtold() are not currently implemented in - * NuttX. Ideally, custom implementations of these functions would be - * provided because: - * - * strtof() - Some MCUs, such as the Cortex-M4F, have built in 32-bit FPU. - * A true implementation could exploit the improved performance by the - * the FPU. - * strtold() - Of course, there is a loss of 32-bits of accuracy in this - * conversion. +/* The function strtold() is not currently implemented in NuttX. Ideally, a + * custom implementation should be provided because, of course, there is a + * loss of 32-bits of accuracy in this conversion. */ -#define strtof(a,b) (float)strtod(a,b) #define strtold(a,b) (long double)strtod(a,b) /**************************************************************************** @@ -205,6 +198,7 @@ unsigned long long strtoull(FAR const char *nptr, FAR char **endptr, int base); #endif double_t strtod(FAR const char *str, FAR char **endptr); +float strtof(FAR const char *str, FAR char **endptr); #define atoi(nptr) ((int)strtol((nptr), NULL, 10)) #define atol(nptr) strtol((nptr), NULL, 10) diff --git a/libc/stdlib/Make.defs b/libc/stdlib/Make.defs index 22509d22dd..d08a0bb434 100644 --- a/libc/stdlib/Make.defs +++ b/libc/stdlib/Make.defs @@ -39,7 +39,7 @@ CSRCS += lib_abs.c lib_abort.c lib_div.c lib_ldiv.c lib_lldiv.c CSRCS += lib_imaxabs.c lib_itoa.c lib_labs.c lib_llabs.c CSRCS += lib_bsearch.c lib_rand.c lib_qsort.c lib_srand.c CSRCS += lib_strtol.c lib_strtoll.c lib_strtoul.c lib_strtoull.c -CSRCS += lib_strtod.c lib_checkbase.c +CSRCS += lib_strtod.c lib_strtof.c lib_checkbase.c ifeq ($(CONFIG_FS_WRITABLE),y) CSRCS += lib_mktemp.c lib_mkstemp.c diff --git a/libc/stdlib/lib_strtod.c b/libc/stdlib/lib_strtod.c index bd2a55e996..7d8d08b532 100644 --- a/libc/stdlib/lib_strtod.c +++ b/libc/stdlib/lib_strtod.c @@ -92,7 +92,7 @@ double_t strtod(FAR const char *str, FAR char **endptr) double_t number; int exponent; int negative; - char *p = (char *) str; + FAR char *p = (FAR char *) str; double p10; int n; int num_digits; -- GitLab From 9e1600b7d314fb3b75c1e721bfb887a7179f1a1a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 20 Oct 2016 12:56:35 -0600 Subject: [PATCH 151/734] Xtensa: Trivial interrupt-related changes --- arch/xtensa/include/esp32/core-isa.h | 6 +- arch/xtensa/include/esp32/irq.h | 154 ++++++++++++++------------- 2 files changed, 82 insertions(+), 78 deletions(-) diff --git a/arch/xtensa/include/esp32/core-isa.h b/arch/xtensa/include/esp32/core-isa.h index 6027ec6479..76a5b4ba46 100644 --- a/arch/xtensa/include/esp32/core-isa.h +++ b/arch/xtensa/include/esp32/core-isa.h @@ -32,8 +32,8 @@ * Pre-processor Definitions ****************************************************************************/ /* Note: Macros of the form XTENSA_HAVE_*** have a value of 1 if the option - * is configured, and a value of 0 otherwise (or undefined if 0 is a valid - * numeric option. These macros are always defined. + * is configured, and a value of 0 otherwise. These macros are always + * defined. */ /* ISA **********************************************************************/ @@ -445,7 +445,7 @@ #define XTENSA_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ #define XTENSA_TIMER1_INTERRUPT 15 /* CCOMPARE1 */ #define XTENSA_TIMER2_INTERRUPT 16 /* CCOMPARE2 */ -#undef XTENSA_TIMER3_INTERRUPT +#define XTENSA_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED #define XTENSA_NMI_INTERRUPT 14 /* non-maskable interrupt */ #define XTENSA_PROFILING_INTERRUPT 11 /* profiling interrupt */ diff --git a/arch/xtensa/include/esp32/irq.h b/arch/xtensa/include/esp32/irq.h index 058833dc9b..1dadb66b89 100644 --- a/arch/xtensa/include/esp32/irq.h +++ b/arch/xtensa/include/esp32/irq.h @@ -49,6 +49,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Exceptions * * IRAM Offset Description @@ -97,87 +98,90 @@ /* PRO_INTR_STATUS_REG_0 / APP_INTR_STATUS_REG_0 */ -#define XTENSA_IRQ_MAC 0 /* 1. *_INTR_STATUS_REG_0, bit 0 */ -#define XTENSA_IRQ_MAC_NMI 1 /* 2. *_INTR_STATUS_REG_0, bit 1 */ -#define XTENSA_IRQ_BB 2 /* 3. *_INTR_STATUS_REG_0, bit 2 */ -#define XTENSA_IRQ_BB_MAC 3 /* 4. *_INTR_STATUS_REG_0, bit 3 */ -#define XTENSA_IRQ_BT_BB 4 /* 5. *_INTR_STATUS_REG_0, bit 4 */ -#define XTENSA_IRQ_BT_BB_NMI 5 /* 6. *_INTR_STATUS_REG_0, bit 5 */ -#define XTENSA_IRQ_RWBT_IRQ 6 /* 7. *_INTR_STATUS_REG_0, bit 6 */ -#define XTENSA_IRQ_RWBLE_IRQ 7 /* 8. *_INTR_STATUS_REG_0, bit 7 */ -#define XTENSA_IRQ_RWBT_NMI 8 /* 9. *_INTR_STATUS_REG_0, bit 8 */ -#define XTENSA_IRQ_RWBLE_NMI 9 /* 10. *_INTR_STATUS_REG_0, bit 9 */ - -#define XTENSA_IRQ_SLC0 10 /* 11. *_INTR_STATUS_REG_0, bit 10 */ -#define XTENSA_IRQ_SLC1 11 /* 12. *_INTR_STATUS_REG_0, bit 11 */ -#define XTENSA_IRQ_UHCI0 12 /* 13. *_INTR_STATUS_REG_0, bit 12 */ -#define XTENSA_IRQ_UHCI1 13 /* 14. *_INTR_STATUS_REG_0, bit 13 */ -#define XTENSA_IRQ_TG_T0_LEVEL 14 /* 15. *_INTR_STATUS_REG_0, bit 14 */ -#define XTENSA_IRQ_TG_T1_LEVEL 15 /* 16. *_INTR_STATUS_REG_0, bit 15 */ -#define XTENSA_IRQ_TG_WDT_LEVEL 16 /* 17. *_INTR_STATUS_REG_0, bit 16 */ -#define XTENSA_IRQ_TG_LACT_LEVEL 17 /* 18. *_INTR_STATUS_REG_0, bit 17 */ -#define XTENSA_IRQ_TG1_T0_LEVEL 18 /* 19. *_INTR_STATUS_REG_0, bit 18 */ -#define XTENSA_IRQ_TG1_T1_LEVEL 19 /* 20. *_INTR_STATUS_REG_0, bit 19 */ - -#define XTENSA_IRQ_TG1_WDT_LEVEL 20 /* 21. *_INTR_STATUS_REG_0, bit 20 */ -#define XTENSA_IRQ_G1_LACT_LEVEL 21 /* 22. *_INTR_STATUS_REG_0, bit 21 */ -#define XTENSA_IRQ_CPU_GPIO 22 /* 23. *_INTR_STATUS_REG_0, bit 22 */ -#define XTENSA_IRQ_CPU_NMI 23 /* 24. *_INTR_STATUS_REG_0, bit 23 */ -#define XTENSA_IRQ_CPU_CPU0 24 /* 25. *_INTR_STATUS_REG_0, bit 24 */ -#define XTENSA_IRQ_CPU_CPU1 25 /* 26. *_INTR_STATUS_REG_0, bit 25 */ -#define XTENSA_IRQ_CPU_CPU2 26 /* 27. *_INTR_STATUS_REG_0, bit 26 */ -#define XTENSA_IRQ_CPU_CPU3 27 /* 28. *_INTR_STATUS_REG_0, bit 27 */ -#define XTENSA_IRQ_SPI0 28 /* 29. *_INTR_STATUS_REG_0, bit 28 */ -#define XTENSA_IRQ_SPI1 29 /* 30. *_INTR_STATUS_REG_0, bit 29 */ - -#define XTENSA_IRQ_SPI2 30 /* 31. *_INTR_STATUS_REG_0, bit 30 */ -#define XTENSA_IRQ_SPI3 31 /* 32. *_INTR_STATUS_REG_0, bit 31 */ +#define XTENSA_IRQ_SREG0 0 +#define XTENSA_IRQ_MAC 0 /* INTR_STATUS_REG_0, bit 0 */ +#define XTENSA_IRQ_MAC_NMI 1 /* INTR_STATUS_REG_0, bit 1 */ +#define XTENSA_IRQ_BB 2 /* INTR_STATUS_REG_0, bit 2 */ +#define XTENSA_IRQ_BB_MAC 3 /* INTR_STATUS_REG_0, bit 3 */ +#define XTENSA_IRQ_BT_BB 4 /* INTR_STATUS_REG_0, bit 4 */ +#define XTENSA_IRQ_BT_BB_NMI 5 /* INTR_STATUS_REG_0, bit 5 */ +#define XTENSA_IRQ_RWBT_IRQ 6 /* INTR_STATUS_REG_0, bit 6 */ +#define XTENSA_IRQ_RWBLE_IRQ 7 /* INTR_STATUS_REG_0, bit 7 */ +#define XTENSA_IRQ_RWBT_NMI 8 /* INTR_STATUS_REG_0, bit 8 */ +#define XTENSA_IRQ_RWBLE_NMI 9 /* INTR_STATUS_REG_0, bit 9 */ + +#define XTENSA_IRQ_SLC0 10 /* INTR_STATUS_REG_0, bit 10 */ +#define XTENSA_IRQ_SLC1 11 /* INTR_STATUS_REG_0, bit 11 */ +#define XTENSA_IRQ_UHCI0 12 /* INTR_STATUS_REG_0, bit 12 */ +#define XTENSA_IRQ_UHCI1 13 /* INTR_STATUS_REG_0, bit 13 */ +#define XTENSA_IRQ_TG_T0_LEVEL 14 /* INTR_STATUS_REG_0, bit 14 */ +#define XTENSA_IRQ_TG_T1_LEVEL 15 /* INTR_STATUS_REG_0, bit 15 */ +#define XTENSA_IRQ_TG_WDT_LEVEL 16 /* INTR_STATUS_REG_0, bit 16 */ +#define XTENSA_IRQ_TG_LACT_LEVEL 17 /* INTR_STATUS_REG_0, bit 17 */ +#define XTENSA_IRQ_TG1_T0_LEVEL 18 /* INTR_STATUS_REG_0, bit 18 */ +#define XTENSA_IRQ_TG1_T1_LEVEL 19 /* INTR_STATUS_REG_0, bit 19 */ + +#define XTENSA_IRQ_TG1_WDT_LEVEL 20 /* INTR_STATUS_REG_0, bit 20 */ +#define XTENSA_IRQ_G1_LACT_LEVEL 21 /* INTR_STATUS_REG_0, bit 21 */ +#define XTENSA_IRQ_CPU_GPIO 22 /* INTR_STATUS_REG_0, bit 22 */ +#define XTENSA_IRQ_CPU_NMI 23 /* INTR_STATUS_REG_0, bit 23 */ +#define XTENSA_IRQ_CPU_CPU0 24 /* INTR_STATUS_REG_0, bit 24 */ +#define XTENSA_IRQ_CPU_CPU1 25 /* INTR_STATUS_REG_0, bit 25 */ +#define XTENSA_IRQ_CPU_CPU2 26 /* INTR_STATUS_REG_0, bit 26 */ +#define XTENSA_IRQ_CPU_CPU3 27 /* INTR_STATUS_REG_0, bit 27 */ +#define XTENSA_IRQ_SPI0 28 /* INTR_STATUS_REG_0, bit 28 */ +#define XTENSA_IRQ_SPI1 29 /* INTR_STATUS_REG_0, bit 29 */ + +#define XTENSA_IRQ_SPI2 30 /* INTR_STATUS_REG_0, bit 30 */ +#define XTENSA_IRQ_SPI3 31 /* INTR_STATUS_REG_0, bit 31 */ /* PRO_INTR_STATUS_REG_1 / APP_INTR_STATUS_REG_1 */ -#define XTENSA_IRQ_I2S0 32 /* 33. *_INTR_STATUS_REG_1, bit 0 */ -#define XTENSA_IRQ_I2S1 33 /* 34. *_INTR_STATUS_REG_1, bit 1 */ -#define XTENSA_IRQ_UART 34 /* 35. *_INTR_STATUS_REG_1, bit 2 */ -#define XTENSA_IRQ_UART1 35 /* 36. *_INTR_STATUS_REG_1, bit 3 */ -#define XTENSA_IRQ_UART2 36 /* 37. *_INTR_STATUS_REG_1, bit 4 */ -#define XTENSA_IRQ_SDIO_HOST 37 /* 38. *_INTR_STATUS_REG_1, bit 5 */ -#define XTENSA_IRQ_EMAC 38 /* 39. *_INTR_STATUS_REG_1, bit 6 */ -#define XTENSA_IRQ_PWM0 39 /* 40. *_INTR_STATUS_REG_1, bit 7 */ -#define XTENSA_IRQ_PWM1 40 /* 41. *_INTR_STATUS_REG_1, bit 8 */ -#define XTENSA_IRQ_PWM2 41 /* 42. *_INTR_STATUS_REG_1, bit 9 */ - -#define XTENSA_IRQ_PWM3 42 /* 43. *_INTR_STATUS_REG_1, bit 10 */ -#define XTENSA_IRQ_LEDC 43 /* 44. *_INTR_STATUS_REG_1, bit 11 */ -#define XTENSA_IRQ_EFUSE 44 /* 45. *_INTR_STATUS_REG_1, bit 12 */ -#define XTENSA_IRQ_CAN 45 /* 46. *_INTR_STATUS_REG_1, bit 13 */ -#define XTENSA_IRQ_RTC_CORE 46 /* 47. *_INTR_STATUS_REG_1, bit 14 */ -#define XTENSA_IRQ_RMT 47 /* 48. *_INTR_STATUS_REG_1, bit 15 */ -#define XTENSA_IRQ_PCNT 48 /* 49. *_INTR_STATUS_REG_1, bit 16 */ -#define XTENSA_IRQ_I2C_EXT0 49 /* 50. *_INTR_STATUS_REG_1, bit 17 */ -#define XTENSA_IRQ_I2C_EXT1 50 /* 51. *_INTR_STATUS_REG_1, bit 18 */ -#define XTENSA_IRQ_RSA 51 /* 52. *_INTR_STATUS_REG_1, bit 19 */ - -#define XTENSA_IRQ_SPI1_DMA 52 /* 53. *_INTR_STATUS_REG_1, bit 20 */ -#define XTENSA_IRQ_SPI2_DMA 53 /* 54. *_INTR_STATUS_REG_1, bit 21 */ -#define XTENSA_IRQ_SPI3_DMA 54 /* 55. *_INTR_STATUS_REG_1, bit 22 */ -#define XTENSA_IRQ_WDG 55 /* 56. *_INTR_STATUS_REG_1, bit 23 */ -#define XTENSA_IRQ_TIMER1 56 /* 57. *_INTR_STATUS_REG_1, bit 24 */ -#define XTENSA_IRQ_TIMER2 57 /* 58. *_INTR_STATUS_REG_1, bit 25 */ -#define XTENSA_IRQ_TG_T0_EDGE 58 /* 59. *_INTR_STATUS_REG_1, bit 26 */ -#define XTENSA_IRQ_TG_T1_EDGE 59 /* 60. *_INTR_STATUS_REG_1, bit 27 */ -#define XTENSA_IRQ_TG_WDT_EDGE 60 /* 61. *_INTR_STATUS_REG_1, bit 28 */ -#define XTENSA_IRQ_TG_LACT_EDGE 61 /* 62. *_INTR_STATUS_REG_1, bit 29 */ - -#define XTENSA_IRQ_TG1_T0_EDGE 62 /* 63. *_INTR_STATUS_REG_1, bit 30 */ -#define XTENSA_IRQ_TG1_T1_EDGE 63 /* 64. *_INTR_STATUS_REG_1, bit 31 */ +#define XTENSA_IRQ_SREG1 32 +#define XTENSA_IRQ_I2S0 32 /* INTR_STATUS_REG_1, bit 0 */ +#define XTENSA_IRQ_I2S1 33 /* INTR_STATUS_REG_1, bit 1 */ +#define XTENSA_IRQ_UART 34 /* INTR_STATUS_REG_1, bit 2 */ +#define XTENSA_IRQ_UART1 35 /* INTR_STATUS_REG_1, bit 3 */ +#define XTENSA_IRQ_UART2 36 /* INTR_STATUS_REG_1, bit 4 */ +#define XTENSA_IRQ_SDIO_HOST 37 /* INTR_STATUS_REG_1, bit 5 */ +#define XTENSA_IRQ_EMAC 38 /* INTR_STATUS_REG_1, bit 6 */ +#define XTENSA_IRQ_PWM0 39 /* INTR_STATUS_REG_1, bit 7 */ +#define XTENSA_IRQ_PWM1 40 /* INTR_STATUS_REG_1, bit 8 */ +#define XTENSA_IRQ_PWM2 41 /* INTR_STATUS_REG_1, bit 9 */ + +#define XTENSA_IRQ_PWM3 42 /* INTR_STATUS_REG_1, bit 10 */ +#define XTENSA_IRQ_LEDC 43 /* INTR_STATUS_REG_1, bit 11 */ +#define XTENSA_IRQ_EFUSE 44 /* INTR_STATUS_REG_1, bit 12 */ +#define XTENSA_IRQ_CAN 45 /* INTR_STATUS_REG_1, bit 13 */ +#define XTENSA_IRQ_RTC_CORE 46 /* INTR_STATUS_REG_1, bit 14 */ +#define XTENSA_IRQ_RMT 47 /* INTR_STATUS_REG_1, bit 15 */ +#define XTENSA_IRQ_PCNT 48 /* INTR_STATUS_REG_1, bit 16 */ +#define XTENSA_IRQ_I2C_EXT0 49 /* INTR_STATUS_REG_1, bit 17 */ +#define XTENSA_IRQ_I2C_EXT1 50 /* INTR_STATUS_REG_1, bit 18 */ +#define XTENSA_IRQ_RSA 51 /* INTR_STATUS_REG_1, bit 19 */ + +#define XTENSA_IRQ_SPI1_DMA 52 /* INTR_STATUS_REG_1, bit 20 */ +#define XTENSA_IRQ_SPI2_DMA 53 /* INTR_STATUS_REG_1, bit 21 */ +#define XTENSA_IRQ_SPI3_DMA 54 /* INTR_STATUS_REG_1, bit 22 */ +#define XTENSA_IRQ_WDG 55 /* INTR_STATUS_REG_1, bit 23 */ +#define XTENSA_IRQ_TIMER1 56 /* INTR_STATUS_REG_1, bit 24 */ +#define XTENSA_IRQ_TIMER2 57 /* INTR_STATUS_REG_1, bit 25 */ +#define XTENSA_IRQ_TG_T0_EDGE 58 /* INTR_STATUS_REG_1, bit 26 */ +#define XTENSA_IRQ_TG_T1_EDGE 59 /* INTR_STATUS_REG_1, bit 27 */ +#define XTENSA_IRQ_TG_WDT_EDGE 60 /* INTR_STATUS_REG_1, bit 28 */ +#define XTENSA_IRQ_TG_LACT_EDGE 61 /* INTR_STATUS_REG_1, bit 29 */ + +#define XTENSA_IRQ_TG1_T0_EDGE 62 /* INTR_STATUS_REG_1, bit 30 */ +#define XTENSA_IRQ_TG1_T1_EDGE 63 /* INTR_STATUS_REG_1, bit 31 */ /* PRO_INTR_STATUS_REG_2 / APP_INTR_STATUS_REG_2 */ -#define XTENSA_IRQ_TG1_WDT_EDGE 64 /* 65. *_INTR_STATUS_REG_2, bit 0 */ -#define XTENSA_IRQ_TG1_LACT_EDGE 65 /* 66. *_INTR_STATUS_REG_2, bit 1 */ -#define XTENSA_IRQ_MMU_IA 66 /* 67. *_INTR_STATUS_REG_2, bit 2 */ -#define XTENSA_IRQ_MPU_IA 67 /* 68. *_INTR_STATUS_REG_2, bit 3 */ -#define XTENSA_IRQ_CACHE_IA 68 /* 69. *_INTR_STATUS_REG_2, bit 4 */ +#define XTENSA_IRQ_SREG0 64 +#define XTENSA_IRQ_TG1_WDT_EDGE 64 /* INTR_STATUS_REG_2, bit 0 */ +#define XTENSA_IRQ_TG1_LACT_EDGE 65 /* INTR_STATUS_REG_2, bit 1 */ +#define XTENSA_IRQ_MMU_IA 66 /* INTR_STATUS_REG_2, bit 2 */ +#define XTENSA_IRQ_MPU_IA 67 /* INTR_STATUS_REG_2, bit 3 */ +#define XTENSA_IRQ_CACHE_IA 68 /* INTR_STATUS_REG_2, bit 4 */ /* Total number of interrupts */ -- GitLab From 2b22666554611acd117d309e75095641eaa90edd Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 20 Oct 2016 12:57:27 -0600 Subject: [PATCH 152/734] Forgot to add a file before the last commit --- libc/stdlib/lib_strtof.c | 252 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 252 insertions(+) create mode 100644 libc/stdlib/lib_strtof.c diff --git a/libc/stdlib/lib_strtof.c b/libc/stdlib/lib_strtof.c new file mode 100644 index 0000000000..82f77a78c5 --- /dev/null +++ b/libc/stdlib/lib_strtof.c @@ -0,0 +1,252 @@ +/**************************************************************************** + * libc/stdlib/lib_strtof.c + * Convert string to float + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * + * A pretty straight forward conversion fo strtod(): + * + * Copyright (C) 2002 Michael Ringgaard. All rights reserved. + * Copyright (C) 2006-2007 H. Peter Anvin. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the project nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#ifdef CONFIG_HAVE_DOUBLE + +/**************************************************************************** + * Pre-processor definitions + ****************************************************************************/ + +/* These are predefined with GCC, but could be issues for other compilers. If + * not defined, an arbitrary big number is put in for now. These should be + * added to nuttx/compiler for your compiler. + */ + +#if !defined(__FLT_MIN_EXP__) || !defined(__FLT_MAX_EXP__) +# ifdef CONFIG_CPP_HAVE_WARNING +# warning "Size of exponent is unknown" +# endif +# undef __FLT_MIN_EXP__ +# define __FLT_MIN_EXP__ (-125) +# undef __FLT_MAX_EXP__ +# define __FLT_MAX_EXP__ (128) +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline int is_real(float x) +{ + const float infinite = 1.0/0.0; + return (x < infinite) && (x >= -infinite); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/***************************************************(************************ + * Name: strtof + * + * Description: + * Convert a string to a float value + * + ****************************************************************************/ + +float strtof(FAR const char *str, FAR char **endptr) +{ + float number; + int exponent; + int negative; + FAR char *p = (FAR char *) str; + float p10; + int n; + int num_digits; + int num_decimals; + const float infinite = 1.0/0.0; + + /* Skip leading whitespace */ + + while (isspace(*p)) + { + p++; + } + + /* Handle optional sign */ + + negative = 0; + switch (*p) + { + case '-': + negative = 1; /* Fall through to increment position */ + case '+': + p++; + default: + break; + } + + number = 0.; + exponent = 0; + num_digits = 0; + num_decimals = 0; + + /* Process string of digits */ + + while (isdigit(*p)) + { + number = number * 10. + (*p - '0'); + p++; + num_digits++; + } + + /* Process decimal part */ + + if (*p == '.') + { + p++; + + while (isdigit(*p)) + { + number = number * 10. + (*p - '0'); + p++; + num_digits++; + num_decimals++; + } + + exponent -= num_decimals; + } + + if (num_digits == 0) + { + set_errno(ERANGE); + number = 0.0; + goto errout; + } + + /* Correct for sign */ + + if (negative) + { + number = -number; + } + + /* Process an exponent string */ + + if (*p == 'e' || *p == 'E') + { + /* Handle optional sign */ + + negative = 0; + switch (*++p) + { + case '-': + negative = 1; /* Fall through to increment pos */ + case '+': + p++; + default: + break; + } + + /* Process string of digits */ + + n = 0; + while (isdigit(*p)) + { + n = n * 10 + (*p - '0'); + p++; + } + + if (negative) + { + exponent -= n; + } + else + { + exponent += n; + } + } + + if (exponent < __FLT_MIN_EXP__ || + exponent > __FLT_MAX_EXP__) + { + set_errno(ERANGE); + number = infinite; + goto errout; + } + + /* Scale the result */ + + p10 = 10.; + n = exponent; + if (n < 0) n = -n; + while (n) + { + if (n & 1) + { + if (exponent < 0) + { + number /= p10; + } + else + { + number *= p10; + } + } + + n >>= 1; + p10 *= p10; + } + + if (!is_real(number)) + { + set_errno(ERANGE); + } + +errout: + if (endptr) + { + *endptr = p; + } + + return number; +} + +#endif /* CONFIG_HAVE_DOUBLE */ -- GitLab From e30a47ba46b97d310f0e9cb9a1142744aeb5b36f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 20 Oct 2016 13:03:15 -0600 Subject: [PATCH 153/734] libc: Make sure that all constant floating point values have F suffix in strtof() --- libc/stdlib/lib_strtof.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/libc/stdlib/lib_strtof.c b/libc/stdlib/lib_strtof.c index 82f77a78c5..b1f479a31f 100644 --- a/libc/stdlib/lib_strtof.c +++ b/libc/stdlib/lib_strtof.c @@ -75,7 +75,7 @@ static inline int is_real(float x) { - const float infinite = 1.0/0.0; + const float infinite = 1.0F/0.0F; return (x < infinite) && (x >= -infinite); } @@ -101,7 +101,7 @@ float strtof(FAR const char *str, FAR char **endptr) int n; int num_digits; int num_decimals; - const float infinite = 1.0/0.0; + const float infinite = 1.0F/0.0F; /* Skip leading whitespace */ @@ -123,7 +123,7 @@ float strtof(FAR const char *str, FAR char **endptr) break; } - number = 0.; + number = 0.0F; exponent = 0; num_digits = 0; num_decimals = 0; @@ -132,7 +132,7 @@ float strtof(FAR const char *str, FAR char **endptr) while (isdigit(*p)) { - number = number * 10. + (*p - '0'); + number = number * 10.0F + (*p - '0'); p++; num_digits++; } @@ -145,7 +145,7 @@ float strtof(FAR const char *str, FAR char **endptr) while (isdigit(*p)) { - number = number * 10. + (*p - '0'); + number = number * 10.0F + (*p - '0'); p++; num_digits++; num_decimals++; @@ -157,7 +157,7 @@ float strtof(FAR const char *str, FAR char **endptr) if (num_digits == 0) { set_errno(ERANGE); - number = 0.0; + number = 0.0F; goto errout; } @@ -214,7 +214,7 @@ float strtof(FAR const char *str, FAR char **endptr) /* Scale the result */ - p10 = 10.; + p10 = 10.0F; n = exponent; if (n < 0) n = -n; while (n) -- GitLab From 9438c42fff4582263eccbc0f93a23346f5db52e4 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 20 Oct 2016 13:06:55 -0600 Subject: [PATCH 154/734] strtof: Also make sure that all integer values use in expressions are cast to float --- libc/stdlib/lib_strtof.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libc/stdlib/lib_strtof.c b/libc/stdlib/lib_strtof.c index b1f479a31f..f081db0ad4 100644 --- a/libc/stdlib/lib_strtof.c +++ b/libc/stdlib/lib_strtof.c @@ -132,7 +132,7 @@ float strtof(FAR const char *str, FAR char **endptr) while (isdigit(*p)) { - number = number * 10.0F + (*p - '0'); + number = number * 10.0F + (float)(*p - '0'); p++; num_digits++; } @@ -145,7 +145,7 @@ float strtof(FAR const char *str, FAR char **endptr) while (isdigit(*p)) { - number = number * 10.0F + (*p - '0'); + number = number * 10.0F + (float)(*p - '0'); p++; num_digits++; num_decimals++; -- GitLab From ed8377af72b65867ad48de995260b9eabb8b35f9 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 20 Oct 2016 14:28:14 -0600 Subject: [PATCH 155/734] Xtensa: More interrupt-related logic --- arch/xtensa/src/common/xtensa_context.S | 4 +- arch/xtensa/src/common/xtensa_inthandlers.S | 212 ++++++++++---------- 2 files changed, 111 insertions(+), 105 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index e1a21412e8..b0ab5a6ce7 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -205,9 +205,9 @@ _xtensa_context_save: l32i a12, sp, (4 * REG_A12) /* Recover original a9,12,13 */ l32i a13, sp, (4 * REG_A13) l32i a9, sp, (4 * REG_A9) - addi sp, sp, (4 * REG_FRMSZ) /* Restore the interruptee's SP */ + addi sp, sp, (4 * XCPTCONTEXT_SIZE) /* Restore the interruptee's SP */ call0 xthal_window_spill_nw /* Preserves only a4,5,8,9,12,13 */ - addi sp, sp, -(4 * REG_FRMSZ) + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) l32i a12, sp, (4 * REG_TMP0) /* Recover stuff from stack frame */ l32i a13, sp, (4 * REG_TMP1) l32i a9, sp, (4 * REG_TMP2) diff --git a/arch/xtensa/src/common/xtensa_inthandlers.S b/arch/xtensa/src/common/xtensa_inthandlers.S index 0eee1a2e74..cac66b0892 100644 --- a/arch/xtensa/src/common/xtensa_inthandlers.S +++ b/arch/xtensa/src/common/xtensa_inthandlers.S @@ -78,10 +78,10 @@ .macro extract_msb aout ain 1: - addi \aout, \ain, -1 /* aout = ain - 1 */ - and \ain, \ain, \aout /* ain = ain & aout */ - bnez \ain, 1b /* repeat until ain == 0 */ - addi \aout, \aout, 1 /* return aout + 1 */ + addi \aout, \ain, -1 /* aout = ain - 1 */ + and \ain, \ain, \aout /* ain = ain & aout */ + bnez \ain, 1b /* Repeat until ain == 0 */ + addi \aout, \aout, 1 /* Return aout + 1 */ .endm /* Macro dispatch_c_isr - dispatch interrupts to user ISRs. @@ -148,7 +148,6 @@ 2: #endif - /* Now look up in the dispatch table and call user ISR if any. */ /* If multiple bits are set then MSB has highest priority. */ extract_msb a4, a2 /* a4 = MSB of a2, a2 trashed */ @@ -179,23 +178,28 @@ wsr a4, INTCLEAR /* Clear sw or edge-triggered interrupt */ beq a3, a4, 7f /* If timer interrupt then skip table */ - find_ms_setbit a3, a4, a3, 0 /* a3 = interrupt number */ + /* Call xtensa_int_decode with, passing that address of the register save + * area as a parameter (A2). + */ - movi a4, _xt_interrupt_table - addx8 a3, a3, a4 /* a3 = address of interrupt table entry */ - l32i a4, a3, XIE_HANDLER /* a4 = handler address */ + mov a2, sp /* Argument: Top of stack = register save area */ + call0 xtensa_int_decode /* Call xtensa_int_decode */ -#ifdef CONFIG_XTENSA_CALL0_ABI - mov a12, a6 /* Save in callee-saved reg */ - l32i a2, a3, XIE_ARG /* a2 = handler arg */ - callx0 a4 /* call handler */ - mov a2, a12 -#else - mov a2, a6 /* Save in windowed reg */ - l32i a6, a3, XIE_ARG /* a6 = handler arg */ - callx4 a4 /* Call handler */ -#endif + /* On return from xtensa_int_decode, A2 will contain the address of the new + * register save area. Usually this would be the same as the current SP. + * But in the event of a context switch, A2 will instead refer to the TCB + * register save area. + */ + + beq a2, sp, 3f /* If timer interrupt then skip table */ + /* Switch stacks */ +#warning REVIST: Should use register save are on stack. + + l32i a4, sp, (4 * REG_A1) /* Retrieve stack ptr and replace */ + addi sp, a4, -(4 * XCPTCONTEXT_SIZE) + +3: #ifdef CONFIG_XTENSA_USE_SWPRI j 8f #else @@ -212,7 +216,7 @@ */ #ifdef CONFIG_XTENSA_CALL0_ABI - mov a12, a6 + mov a12, a6 call0 XT_RTOS_TIMER_INT mov a2, a12 #else @@ -236,8 +240,8 @@ movi a3, _xt_intdata l32i a4, a3, 0 /* a4 = _xt_intenable */ s32i a2, a3, 4 /* update _xt_vpri_mask */ - and a4, a4, a2 /* a4 = masked intenable */ - wsr a4, INTENABLE /* update INTENABLE */ + and a4, a4, a2 /* a4 = masked intenable */ + wsr a4, INTENABLE /* update INTENABLE */ #endif 9: @@ -277,17 +281,17 @@ #if XTENSA_EXCM_LEVEL >= 2 .section .iram1,"ax" - .type _xtensa_level2_handler,@function - .align 4 + .type _xtensa_level2_handler,@function + .align 4 _xtensa_level2_handler: - mov a0, sp /* sp == a1 */ - addi sp, sp, -(4 * REG_FRMSZ) /* Allocate interrupt stack frame */ + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ - rsr a0, EPS_2 /* Save interruptee's PS */ + rsr a0, EPS_2 /* Save interruptee's PS */ s32i a0, sp, (4 * REG_PS) - rsr a0, EPC_2 /* Save interruptee's PC */ + rsr a0, EPC_2 /* Save interruptee's PC */ s32i a0, sp, (4 * REG_PC) - rsr a0, EXCSAVE_2 /* Save interruptee's a0 */ + rsr a0, EXCSAVE_2 /* Save interruptee's a0 */ s32i a0, sp, (4 * REG_A0) /* Save rest of interrupt context and enter RTOS. */ @@ -301,69 +305,71 @@ _xtensa_level2_handler: #else movi a0, PS_INTLEVEL(2) | PS_UM | PS_WOE #endif - wsr a0, PS + wsr a0, PS rsync /* Decode and dispatch the interrupt. In the event of an interrupt - * level context xtensa_int_decode() will return a pointer to the new - * register state in A2. + * level context dispatch_c_isr() will switch stacks to the new task's + * context save area. */ - dispatch_c_isr 2 XTENSA_INTLEVEL2_MASK + dispatch_c_isr 2 XTENSA_INTLEVEL2_MASK /* Restore registers in preparation to return from interrupt */ - call0 _xtensa_int_exit /* does not return directly here */ + call0 _xtensa_int_exit /* Restore only level-specific regs (the rest were already restored) */ l32i a0, sp, (4 * REG_PS) /* retrieve interruptee's PS */ - wsr a0, EPS_2 + wsr a0, EPS_2 l32i a0, sp, (4 * REG_PC) /* retrieve interruptee's PC */ - wsr a0, EPC_2 + wsr a0, EPC_2 l32i a0, sp, (4 * REG_A0) /* retrieve interruptee's A0 */ l32i sp, sp, (4 * REG_A1) /* remove interrupt stack frame */ - rsync /* Ensure EPS and EPC written */ + rsync /* Ensure EPS and EPC written */ /* Return from interrupt. RFI restores the PS from EPS_2 and jumps to * the address in EPC_2. */ - rfi 2 + rfi 2 #endif /* XTENSA_EXCM_LEVEL >= 2 */ -/******************************************************************************* - -HIGH PRIORITY (LEVEL > XTENSA_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS - -High priority interrupts are by definition those with priorities greater -than XTENSA_EXCM_LEVEL. This includes non-maskable (NMI). High priority -interrupts cannot interact with the RTOS, that is they must save all regs -they use and not call any RTOS function. - -A further restriction imposed by the Xtensa windowed architecture is that -high priority interrupts must not modify the stack area even logically -"above" the top of the interrupted stack (they need to provide their -own stack or static save area). - -Cadence Design Systems recommends high priority interrupt handlers be coded in assembly -and used for purposes requiring very short service times. - -Here are templates for high priority (level 2+) interrupt vectors. -They assume only one interrupt per level to avoid the burden of identifying -which interrupts at this level are pending and enabled. This allows for -minimum latency and avoids having to save/restore a2 in addition to a0. -If more than one interrupt per high priority level is configured, this burden -is on the handler which in any case must provide a way to save and restore -registers it uses without touching the interrupted stack. - -Each vector goes at a predetermined location according to the Xtensa -hardware configuration, which is ensured by its placement in a special -section known to the Xtensa linker support package (LSP). It performs -the minimum necessary before jumping to the handler in the .text section. - -*******************************************************************************/ +/**************************************************************************** + * + * HIGH PRIORITY (LEVEL > XTENSA_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS + * + * High priority interrupts are by definition those with priorities greater + * than XTENSA_EXCM_LEVEL. This includes non-maskable (NMI). High priority + * interrupts cannot interact with the RTOS, that is they must save all regs + * they use and not call any RTOS function. + * + * A further restriction imposed by the Xtensa windowed architecture is that + * high priority interrupts must not modify the stack area even logically + * "above" the top of the interrupted stack (they need to provide their + * own stack or static save area). + * + * Cadence Design Systems recommends high priority interrupt handlers be + * coded in assembly and used for purposes requiring very short service + * times. + * + * Here are templates for high priority (level 2+) interrupt vectors. + * They assume only one interrupt per level to avoid the burden of + * identifying which interrupts at this level are pending and enabled. This + * allows for minimum latency and avoids having to save/restore a2 in + * addition to a0. If more than one interrupt per high priority level is + * configured, this burden is on the handler which in any case must provide + * a way to save and restore registers it uses without touching the + * interrupted stack. + * + * Each vector goes at a predetermined location according to the Xtensa + * hardware configuration, which is ensured by its placement in a special + * section known to the Xtensa linker support package (LSP). It performs + * the minimum necessary before jumping to the handler in the .text section. + * + ****************************************************************************/ /* Currently only shells for high priority interrupt handlers are provided @@ -372,7 +378,7 @@ documentation: "Microprocessor Programmer's Guide". */ #if XTENSA_INT_NLEVELS >=2 && XTENSA_EXCM_LEVEL < 2 && XTENSA_DEBUGLEVEL !=2 - .section .iram1,"ax" + .section .iram1,"ax" .type _xtensa_level2_handler, @function .align 4 _xtensa_level2_handler: @@ -384,24 +390,24 @@ _xtensa_level2_handler: l32i a0, a0, 2<<2 beqz a0, 1f .Ln_xtensa_level2_handler_call_hook: - callx0 a0 /* must NOT disturb stack! */ + callx0 a0 /* Must NOT disturb stack! */ 1: #endif /* USER_EDIT: - ADD HIGH PRIORITY LEVEL 2 INTERRUPT HANDLER CODE HERE. - */ + * ADD HIGH PRIORITY LEVEL 2 INTERRUPT HANDLER CODE HERE. + */ .align 4 .L_xtensa_level2_handler_exit: - rsr a0, EXCSAVE_2 /* restore a0 */ - rfi 2 + rsr a0, EXCSAVE_2 /* Restore a0 */ + rfi 2 #endif /* XTENSA_INT_NLEVELS >=2 && XTENSA_EXCM_LEVEL < 2 && XTENSA_DEBUGLEVEL !=2 */ #if XTENSA_INT_NLEVELS >=3 && XTENSA_EXCM_LEVEL < 3 && XTENSA_DEBUGLEVEL !=3 - .section .iram1,"ax" - .type _xtensa_level3_handler,@function + .section .iram1,"ax" + .type _xtensa_level3_handler, @function .align 4 _xtensa_level3_handler: @@ -412,23 +418,23 @@ _xtensa_level3_handler: l32i a0, a0, 3<<2 beqz a0, 1f .Ln_xtensa_level3_handler_call_hook: - callx0 a0 /* must NOT disturb stack! */ + callx0 a0 /* Must NOT disturb stack! */ 1: #endif /* USER_EDIT: - ADD HIGH PRIORITY LEVEL 3 INTERRUPT HANDLER CODE HERE. - */ + * ADD HIGH PRIORITY LEVEL 3 INTERRUPT HANDLER CODE HERE. + */ .align 4 .L_xtensa_level3_handler_exit: - rsr a0, EXCSAVE_3 /* restore a0 */ - rfi 3 + rsr a0, EXCSAVE_3 /* Restore a0 */ + rfi 3 #endif /* XTENSA_INT_NLEVELS >=3 && XTENSA_EXCM_LEVEL < 3 && XTENSA_DEBUGLEVEL !=3 */ #if XTENSA_INT_NLEVELS >=4 && XTENSA_EXCM_LEVEL < 4 && XTENSA_DEBUGLEVEL !=4 - .section .iram1,"ax" + .section .iram1,"ax" .type _xtensa_level4_handler,@function .align 4 _xtensa_level4_handler: @@ -437,26 +443,26 @@ _xtensa_level4_handler: /* Call interrupt hook if present to (pre)handle interrupts. */ movi a0, _xt_intexc_hooks - l32i a0, a0, 4<<2 + l32i a0, a0, 4 << 2 beqz a0, 1f .Ln_xtensa_level4_handler_call_hook: - callx0 a0 /* must NOT disturb stack! */ + callx0 a0 /* Must NOT disturb stack! */ 1: #endif /* USER_EDIT: - ADD HIGH PRIORITY LEVEL 4 INTERRUPT HANDLER CODE HERE. - */ + * ADD HIGH PRIORITY LEVEL 4 INTERRUPT HANDLER CODE HERE. + */ .align 4 .L_xtensa_level4_handler_exit: - rsr a0, EXCSAVE_4 /* restore a0 */ - rfi 4 + rsr a0, EXCSAVE_4 /* Restore a0 */ + rfi 4 #endif /* XTENSA_INT_NLEVELS >=4 && XTENSA_EXCM_LEVEL < 4 && XTENSA_DEBUGLEVEL !=4 */ #if XTENSA_INT_NLEVELS >=5 && XTENSA_EXCM_LEVEL < 5 && XTENSA_DEBUGLEVEL !=5 - .section .iram1,"ax" + .section .iram1,"ax" .type _xtensa_level5_handler,@function .align 4 _xtensa_level5_handler: @@ -465,26 +471,26 @@ _xtensa_level5_handler: /* Call interrupt hook if present to (pre)handle interrupts. */ movi a0, _xt_intexc_hooks - l32i a0, a0, 5<<2 + l32i a0, a0, 5 << 2 beqz a0, 1f .Ln_xtensa_level5_handler_call_hook: - callx0 a0 /* must NOT disturb stack! */ + callx0 a0 /* Must NOT disturb stack! */ 1: #endif /* USER_EDIT: - ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE. - */ + * ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE. + */ .align 4 .L_xtensa_level5_handler_exit: - rsr a0, EXCSAVE_5 /* restore a0 */ - rfi 5 + rsr a0, EXCSAVE_5 /* restore a0 */ + rfi 5 #endif /* XTENSA_INT_NLEVELS >=5 && XTENSA_EXCM_LEVEL < 5 && XTENSA_DEBUGLEVEL !=5 */ #if XTENSA_INT_NLEVELS >=6 && XTENSA_EXCM_LEVEL < 6 && XTENSA_DEBUGLEVEL !=6 - .section .iram1,"ax" + .section .iram1,"ax" .type _xtensa_level6_handler, @function .align 4 _xtensa_level6_handler: @@ -493,20 +499,20 @@ _xtensa_level6_handler: /* Call interrupt hook if present to (pre)handle interrupts. */ movi a0, _xt_intexc_hooks - l32i a0, a0, 6<<2 + l32i a0, a0, 6 << 2 beqz a0, 1f .Ln_xtensa_level6_handler_call_hook: - callx0 a0 /* must NOT disturb stack! */ + callx0 a0 /* Must NOT disturb stack! */ 1: #endif /* USER_EDIT: - ADD HIGH PRIORITY LEVEL 6 INTERRUPT HANDLER CODE HERE. - */ + * ADD HIGH PRIORITY LEVEL 6 INTERRUPT HANDLER CODE HERE. + */ .align 4 .L_xtensa_level6_handler_exit: - rsr a0, EXCSAVE_6 /* restore a0 */ - rfi 6 + rsr a0, EXCSAVE_6 /* Restore a0 */ + rfi 6 #endif /* XTENSA_INT_NLEVELS >=6 && XTENSA_EXCM_LEVEL < 6 && XTENSA_DEBUGLEVEL !=6 */ -- GitLab From 520513f456dcb9b5e0918d02f678f0d95c6176ff Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 20 Oct 2016 14:34:51 -0600 Subject: [PATCH 156/734] Xtensa: Add interrupt decode framework --- arch/xtensa/src/common/xtensa_intdecode.c | 69 +++++++++++++++++++++++ arch/xtensa/src/esp32/Make.defs | 8 +-- 2 files changed, 73 insertions(+), 4 deletions(-) create mode 100644 arch/xtensa/src/common/xtensa_intdecode.c diff --git a/arch/xtensa/src/common/xtensa_intdecode.c b/arch/xtensa/src/common/xtensa_intdecode.c new file mode 100644 index 0000000000..c170732f6b --- /dev/null +++ b/arch/xtensa/src/common/xtensa_intdecode.c @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_intdecode.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_intdecode + * + * Description: + * Determine the peripheral that geneated the interrupt and dispatch + * handling to the registered interrupt handler via irq_dispatch(). + * + * Input Parameters: + * regs - Saves processor state on the stack + * + * Returned Value: + * Normally the same vale as regs is returned. But, in the event of an + * interrupt level context switch, the returned value will, instead point + * to the saved processor state in the TCB of the newly started task. + * + ****************************************************************************/ + +uint32_t xtensa_intdecode(uint32_t *regs) +{ +#warning Missing implementation + return regs; +} diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 1954962fdc..c957048920 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -44,10 +44,10 @@ CMN_ASRCS = xtensa_context.S xtensa_irq.S xtensa_intvectors.S CMN_CSRCS = xtensa_assert.c xtensa_copystate.c CMN_CSRCS += xtensa_createstack.c xtensa_exit.c xtensa_idle.c CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c -CMN_CSRCS += xtensa_interruptcontext.c xtensa_lowputs.c xtensa_mdelay.c -CMN_CSRCS += xtensa_modifyreg8.c xtensa_modifyreg16.c xtensa_modifyreg32.c -CMN_CSRCS += xtensa_puts.c xtensa_releasestack.c xtensa_stackframe.c -CMN_CSRCS += xtensa_udelay.c xtensa_usestack.c +CMN_CSRCS += xtensa_interruptcontext.c xtensa_intdecode.c xtensa_lowputs.c +CMN_CSRCS += xtensa_mdelay.c xtensa_modifyreg8.c xtensa_modifyreg16.c +CMN_CSRCS += xtensa_modifyreg32.c xtensa_puts.c xtensa_releasestack.c +CMN_CSRCS += xtensa_stackframe.c xtensa_udelay.c xtensa_usestack.c # Configuration-dependent common XTENSA files -- GitLab From 67c98baaea851213db8ebf34345458faca4f475a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 20 Oct 2016 14:28:13 -0600 Subject: [PATCH 157/734] Xtensa: Add a missing include file --- arch/xtensa/src/common/xtensa_intvectors.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/xtensa/src/common/xtensa_intvectors.S b/arch/xtensa/src/common/xtensa_intvectors.S index c7da5a7478..3d27de4767 100644 --- a/arch/xtensa/src/common/xtensa_intvectors.S +++ b/arch/xtensa/src/common/xtensa_intvectors.S @@ -38,6 +38,8 @@ #include +#include + #include "xtensa_specregs.h" #include "xtensa_macros.h" -- GitLab From bd6633dd84b2b6715c1a5c0118182c9daf8e7066 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 20 Oct 2016 15:21:29 -0600 Subject: [PATCH 158/734] Xtensa: Add some data structures needed for SMP support. --- arch/xtensa/src/common/xtensa.h | 29 ++++- arch/xtensa/src/common/xtensa_assert.c | 2 +- arch/xtensa/src/common/xtensa_dumpstate.c | 47 +++---- arch/xtensa/src/common/xtensa_initialize.c | 11 +- arch/xtensa/src/common/xtensa_intdecode.c | 6 +- .../src/common/xtensa_interruptcontext.c | 7 +- arch/xtensa/src/common/xtensa_irqdispatch.c | 116 ++++++++++++++++++ 7 files changed, 175 insertions(+), 43 deletions(-) create mode 100644 arch/xtensa/src/common/xtensa_irqdispatch.c diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index aa49e00159..ba7da8055a 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -108,8 +108,8 @@ * only a referenced is passed to get the state from the TCB. */ -#define xtensa_savestate(regs) xtensa_copystate(regs, (uint32_t*)g_current_regs) -#define xtensa_restorestate(regs) do { g_current_regs = regs; } while (0) +#define xtensa_savestate(regs) xtensa_copystate(regs, (uint32_t*)CURRENT_REGS) +#define xtensa_restorestate(regs) do { CURRENT_REGS = regs; } while (0) /* Register access macros */ @@ -133,11 +133,27 @@ typedef void (*xtensa_vector_t)(void); ****************************************************************************/ #ifndef __ASSEMBLY__ -/* This holds a references to the current interrupt level register storage - * structure. If is non-NULL only during interrupt processing. +/* g_current_regs[] holds a references to the current interrupt level + * register storage structure. If is non-NULL only during interrupt + * processing. Access to g_current_regs[] must be through the macro + * CURRENT_REGS for portability. */ -extern volatile uint32_t *g_current_regs; +#ifdef CONFIG_SMP +/* For the case of architectures with multiple CPUs, then there must be one + * such value for each processor that can receive an interrupt. + */ + +int up_cpu_index(void); /* See include/nuttx/arch.h */ +extern volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; +# define CURRENT_REGS (g_current_regs[up_cpu_index()]) + +#else + +extern volatile uint32_t *g_current_regs[1]; +# define CURRENT_REGS (g_current_regs[0]) + +#endif /* This is the beginning of heap as provided from *_head.S. This is the * first address in DRAM after the loaded program+bss+idle stack. The end @@ -229,7 +245,8 @@ void xtensa_dumpstate(void); /* Common XTENSA functions */ /* IRQs */ -uint32_t *xtensa_doirq(int irq, uint32_t *regs); +uint32_t *xtensa_int_decode(uint32_t *regs); +uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs); /* Software interrupt handler */ diff --git a/arch/xtensa/src/common/xtensa_assert.c b/arch/xtensa/src/common/xtensa_assert.c index 4e7577fb76..98c5562d92 100644 --- a/arch/xtensa/src/common/xtensa_assert.c +++ b/arch/xtensa/src/common/xtensa_assert.c @@ -76,7 +76,7 @@ static void xtensa_assert(int errorcode) { /* Are we in an interrupt handler or the idle task? */ - if (g_current_regs || this_task()->pid == 0) + if (CURRENT_REGS || this_task()->pid == 0) { (void)up_irq_save(); for (; ; ) diff --git a/arch/xtensa/src/common/xtensa_dumpstate.c b/arch/xtensa/src/common/xtensa_dumpstate.c index ae260f0e6d..14217d0117 100644 --- a/arch/xtensa/src/common/xtensa_dumpstate.c +++ b/arch/xtensa/src/common/xtensa_dumpstate.c @@ -95,52 +95,41 @@ static void xtensa_stackdump(uint32_t sp, uint32_t stack_base) static inline void xtensa_registerdump(void) { + uint32_ *regs = CURRENT_REGS; /* Are user registers available from interrupt processing? */ - if (g_current_regs != NULL) + if (regs != NULL) { _alert(" PC: %08lx PS: %08lx\n", - (unsigned long)g_current_regs[REG_PC], - (unsigned long)g_current_regs[REG_PS]); + (unsigned long)regs[REG_PC], (unsigned long)regs[REG_PS]); _alert(" A0: %08lx A1: %08lx A2: %08lx A3: %08lx\n", - (unsigned long)g_current_regs[REG_A0], - (unsigned long)g_current_regs[REG_A1], - (unsigned long)g_current_regs[REG_A2], - (unsigned long)g_current_regs[REG_A3]); + (unsigned long)regs[REG_A0], (unsigned long)regs[REG_A1], + (unsigned long)regs[REG_A2], (unsigned long)regs[REG_A3]); _alert(" A4: %08lx A5: %08lx A6: %08lx A7: %08lx\n", - (unsigned long)g_current_regs[REG_A4], - (unsigned long)g_current_regs[REG_A5], - (unsigned long)g_current_regs[REG_A6], - (unsigned long)g_current_regs[REG_A7]); + (unsigned long)regs[REG_A4], (unsigned long)regs[REG_A5], + (unsigned long)regs[REG_A6], (unsigned long)regs[REG_A7]); _alert(" A8: %08lx A9: %08lx A10: %08lx A11: %08lx\n", - (unsigned long)g_current_regs[REG_A8], - (unsigned long)g_current_regs[REG_A9], - (unsigned long)g_current_regs[REG_A10], - (unsigned long)g_current_regs[REG_A11]); + (unsigned long)regs[REG_A8], (unsigned long)regs[REG_A9], + (unsigned long)regs[REG_A10], (unsigned long)regs[REG_A11]); _alert(" A12: %08lx A13: %08lx A14: %08lx A15: %08lx\n", - (unsigned long)g_current_regs[REG_A12], - (unsigned long)g_current_regs[REG_A13], - (unsigned long)g_current_regs[REG_A14], - (unsigned long)g_current_regs[REG_A15]); + (unsigned long)regs[REG_A12], (unsigned long)regs[REG_A13], + (unsigned long)regs[REG_A14], (unsigned long)regs[REG_A15]); _alert(" SAR: %08lx CAUSE: %08lx VADDR: %08lx\n", - (unsigned long)g_current_regs[REG_SAR], - (unsigned long)g_current_regs[REG_EXCCAUSE], - (unsigned long)g_current_regs[REG_EXCVADDR]); + (unsigned long)regs[REG_SAR], (unsigned long)regs[REG_EXCCAUSE], + (unsigned long)regs[REG_EXCVADDR]); #ifdef XTENSA_HAVE_LOOPS _alert(" LBEG: %08lx LEND: %08lx LCNT: %08lx\n", - (unsigned long)g_current_regs[REG_LBEG], - (unsigned long)g_current_regs[REG_LEND], - (unsigned long)g_current_regs[REG_LCOUNT]); + (unsigned long)regs[REG_LBEG], (unsigned long)regs[REG_LEND], + (unsigned long)regs[REG_LCOUNT]); #endif #ifndef CONFIG_XTENSA_CALL0_ABI _alert(" TMP0: %08lx TMP1: %08lx TMP2: %08lx\n", - (unsigned long)g_current_regs[REG_TMP0], - (unsigned long)g_current_regs[REG_TMP1], - (unsigned long)g_current_regs[REG_TMP2]); + (unsigned long)regs[REG_TMP0], (unsigned long)regs[REG_TMP1], + (unsigned long)regs[REG_TMP2]); #endif #ifdef CONFIG_XTENSA_USE_SWPRI _alert(" VPRI: %08lx\n", - (unsigned long)g_current_regs[REG_VPRI]); + (unsigned long)regs[REG_VPRI]); #endif } } diff --git a/arch/xtensa/src/common/xtensa_initialize.c b/arch/xtensa/src/common/xtensa_initialize.c index 45ee3b4233..2041548b17 100644 --- a/arch/xtensa/src/common/xtensa_initialize.c +++ b/arch/xtensa/src/common/xtensa_initialize.c @@ -113,9 +113,18 @@ static void up_calibratedelay(void) void up_initialize(void) { +#ifdef CONFIG_SMP + int i; + /* Initialize global variables */ - g_current_regs = NULL; + for (i = 0; i < CONFIG_SMP_NCPUS; i++) + { + g_current_regs[i] = NULL; + } +#else + CURRENT_REGS = NULL; +#endif /* Calibrate the timing loop */ diff --git a/arch/xtensa/src/common/xtensa_intdecode.c b/arch/xtensa/src/common/xtensa_intdecode.c index c170732f6b..484d30f849 100644 --- a/arch/xtensa/src/common/xtensa_intdecode.c +++ b/arch/xtensa/src/common/xtensa_intdecode.c @@ -46,11 +46,11 @@ ****************************************************************************/ /**************************************************************************** - * Name: xtensa_intdecode + * Name: xtensa_int_decode * * Description: * Determine the peripheral that geneated the interrupt and dispatch - * handling to the registered interrupt handler via irq_dispatch(). + * handling to the registered interrupt handler via xtensa_irq_dispatch(). * * Input Parameters: * regs - Saves processor state on the stack @@ -62,7 +62,7 @@ * ****************************************************************************/ -uint32_t xtensa_intdecode(uint32_t *regs) +uint32_t *xtensa_int_decode(uint32_t *regs) { #warning Missing implementation return regs; diff --git a/arch/xtensa/src/common/xtensa_interruptcontext.c b/arch/xtensa/src/common/xtensa_interruptcontext.c index db03c5c19d..8cf096f725 100644 --- a/arch/xtensa/src/common/xtensa_interruptcontext.c +++ b/arch/xtensa/src/common/xtensa_interruptcontext.c @@ -52,11 +52,12 @@ /**************************************************************************** * Name: up_interrupt_context * - * Description: Return true is we are currently executing in - * the interrupt handler context. + * Description: Return true is we are currently executing in + * the interrupt handler context on this CPU. + * ****************************************************************************/ bool up_interrupt_context(void) { - return g_current_regs != NULL; + return CURRENT_REGS != NULL; } diff --git a/arch/xtensa/src/common/xtensa_irqdispatch.c b/arch/xtensa/src/common/xtensa_irqdispatch.c new file mode 100644 index 0000000000..2a3e9920e0 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_irqdispatch.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtena_irqdispatch.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "xtensa.h" + +#include "group/group.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs) +{ + board_autoled_on(LED_INIRQ); +#ifdef CONFIG_SUPPRESS_INTERRUPTS + PANIC(); +#else + /* Nested interrupts are not supported */ + + DEBUGASSERT(CURRENT_REGS == NULL); + + /* Current regs non-zero indicates that we are processing an interrupt; + * CURRENT_REGS is also used to manage interrupt level context switches. + */ + + CURRENT_REGS = regs; + + /* Deliver the IRQ */ + + irq_dispatch(irq, regs); + +#if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV) + /* Check for a context switch. If a context switch occurred, then + * CURRENT_REGS will have a different value than it did on entry. If an + * interrupt level context switch has occurred, then restore the floating + * point state and the establish the correct address environment before + * returning from the interrupt. + */ + + if (regs != CURRENT_REGS) + { +#ifdef CONFIG_ARCH_FPU + /* Restore floating point registers */ + + up_restorefpu((uint32_t *)CURRENT_REGS); +#endif + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(NULL); +#endif + } +#endif + + /* Set CURRENT_REGS to NULL to indicate that we are no longer in an + * interrupt handler. + */ + + regs = (uint32_t *)CURRENT_REGS; + CURRENT_REGS = NULL; +#endif + + board_autoled_off(LED_INIRQ); + return regs; +} -- GitLab From 7a89808debe9854599f7f6613fa750625127da08 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 20 Oct 2016 16:22:37 -0600 Subject: [PATCH 159/734] ESP32: Add interrupt decode logic --- arch/xtensa/src/esp32/Make.defs | 4 +- .../esp32_intdecode.c} | 65 ++++++++++++++++++- 2 files changed, 65 insertions(+), 4 deletions(-) rename arch/xtensa/src/{common/xtensa_intdecode.c => esp32/esp32_intdecode.c} (66%) diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index c957048920..8aef01a506 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -44,7 +44,7 @@ CMN_ASRCS = xtensa_context.S xtensa_irq.S xtensa_intvectors.S CMN_CSRCS = xtensa_assert.c xtensa_copystate.c CMN_CSRCS += xtensa_createstack.c xtensa_exit.c xtensa_idle.c CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c -CMN_CSRCS += xtensa_interruptcontext.c xtensa_intdecode.c xtensa_lowputs.c +CMN_CSRCS += xtensa_interruptcontext.c xtensa_irqdispatch.c xtensa_lowputs.c CMN_CSRCS += xtensa_mdelay.c xtensa_modifyreg8.c xtensa_modifyreg16.c CMN_CSRCS += xtensa_modifyreg32.c xtensa_puts.c xtensa_releasestack.c CMN_CSRCS += xtensa_stackframe.c xtensa_udelay.c xtensa_usestack.c @@ -73,7 +73,7 @@ endif # Required ESP32 files (arch/xtensa/src/lx6) CHIP_ASRCS = -CHIP_CSRCS = esp32_allocateheap.c esp32_start.c +CHIP_CSRCS = esp32_allocateheap.c esp32_intdecode.c esp32_start.c # Configuration-dependent ESP32 files diff --git a/arch/xtensa/src/common/xtensa_intdecode.c b/arch/xtensa/src/esp32/esp32_intdecode.c similarity index 66% rename from arch/xtensa/src/common/xtensa_intdecode.c rename to arch/xtensa/src/esp32/esp32_intdecode.c index 484d30f849..96bc4c8092 100644 --- a/arch/xtensa/src/common/xtensa_intdecode.c +++ b/arch/xtensa/src/esp32/esp32_intdecode.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/common/xtensa_intdecode.c + * arch/xtensa/src/esp32/esp32_intdecode.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -64,6 +64,67 @@ uint32_t *xtensa_int_decode(uint32_t *regs) { -#warning Missing implementation + uintptr_t regaddr; + uint32_t regval; + uint32_t mask; + int regndx; + int bit; + int baseirq; + int irq; + +#ifdef CONFIG_SMP + int cpu; + + /* Select PRO or APP interrupt status registers */ + + cpu = up_cpu_index(); + if (cpu == 0) + { + regaddr = DPORT_PRO_INTR_STATUS_0_REG; + } + else +#endif + { + regaddr = DPORT_APP_INTR_STATUS_0_REG; + } + + /* Process each pending interrupt in each of the three interrupt status + * registers. + */ + + for (regndx = 0, baseirq = XTENSA_IRQ_SREG0; + regndx < 3; + regndx++, baseirq += 32, regaddr += sizeof(uint32_t)) + { + /* Fetch the next register status register */ + + regval = getreg32(regaddr); + + /* Decode and dispatch each pending bit in the interrupt status + * register. + */ + + for (bit = 0; regval != 0 && bit < 32; bit++) + { + /* Check if this interrupt is pending */ + + mask = (1 << bit); + if ((regval & mask) != 0) + { + /* Yes.. Dispatch the interrupt. Note that regs may be + * altered in the case of an interrupt level context switch. + */ + + regs = xtensa_irq_dispatch(baseirq + bit, regs); + + /* Clear this bit in the sampled status register so that + * perhaps we can exit this loop sooner. + */ + + regval &= ~mask; + } + } + } + return regs; } -- GitLab From 363fe19ff69401aab7c131519d3d9cd570ae9c0e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 20 Oct 2016 16:42:37 -0600 Subject: [PATCH 160/734] Xtensa: Fix some compile issues --- arch/xtensa/src/common/xtensa.h | 5 +++ arch/xtensa/src/common/xtensa_context.S | 44 ++++++++++----------- arch/xtensa/src/common/xtensa_dumpstate.c | 3 +- arch/xtensa/src/common/xtensa_exit.c | 6 +-- arch/xtensa/src/common/xtensa_inthandlers.S | 4 +- arch/xtensa/src/esp32/esp32_intdecode.c | 4 +- 6 files changed, 37 insertions(+), 29 deletions(-) diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index ba7da8055a..7f193ab97c 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -248,6 +248,11 @@ void xtensa_dumpstate(void); uint32_t *xtensa_int_decode(uint32_t *regs); uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs); +void xtensa_context_save(uint32_t *regs); +void xtensa_full_context_save(uint32_t *regs); +void xtensa_context_restore(uint32_t *regs); +void xtensa_full_context_restore(uint32_t *regs); + /* Software interrupt handler */ int xtensa_swint(int irq, FAR void *context); diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index b0ab5a6ce7..b1e7714d47 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -76,8 +76,8 @@ .text /**************************************************************************** - * Name: _xtensa_context_save - * _xtensa_full_context_save + * Name: xtensa_context_save + * xtensa_full_context_save * * Description: * @@ -85,14 +85,14 @@ * * These functions save Xtensa processor state: * - * - _xtensa_full_context_save saves all registers except PC, PS, A0, and + * - xtensa_full_context_save saves all registers except PC, PS, A0, and * A1 (SP) - * - _xtensa_context_save, in addition, does not save A12-A15 which + * - xtensa_context_save, in addition, does not save A12-A15 which * are preserved by the callee). * * Caller is expected to have saved PC, PS, A0, and A1 (SP). * - * The counterparts to these functions are _xtensa_context_restore() and + * The counterparts to these functions are xtensa_context_restore() and * xtensa_full_context_restore(). * * Entry Conditions: @@ -110,16 +110,16 @@ * ****************************************************************************/ - .global _xtensa_full_context_save - .global _xtensa_context_save - .type _xtensa_full_context_save, @function - .type _xtensa_context_save, @function + .global xtensa_full_context_save + .global xtensa_context_save + .type xtensa_full_context_save, @function + .type xtensa_context_save, @function .align 4 .literal_position .align 4 -_xtensa_full_context_save: +xtensa_full_context_save: #ifndef CONFIG_XTENSA_CALL0_ABI /* Save Call0 ABI callee-saved regs a12-15. */ @@ -130,7 +130,7 @@ _xtensa_full_context_save: s32i a15, sp, (4 * REG_A15) #endif -_xtensa_context_save: +xtensa_context_save: s32i a2, sp, (4 * REG_A2) s32i a3, sp, (4 * REG_A3) @@ -238,8 +238,8 @@ _xtensa_context_save: ret /**************************************************************************** - * Name: _xtensa_context_restore - * _xtensa_full_context_restore + * Name: xtensa_context_restore + * xtensa_full_context_restore * * Description: * @@ -248,14 +248,14 @@ _xtensa_context_save: * These functions restores Xtensa processor state and differ in which * registers are saved: * - * - _xtensa_full_context_restore restores all registers except PC, PS, + * - xtensa_full_context_restore restores all registers except PC, PS, * A0, and A1 (SP) - * - _xtensa_context_restore, in addition, does not restore A12-A15 which + * - xtensa_context_restore, in addition, does not restore A12-A15 which * are preserved by the callee). * * The caller is responsible for restoring PC, PS, A0, A1 (SP) in both cases. * - * _xtensa_context_save and _xtensa_full_context_save are the counterparts + * xtensa_context_save and xtensa_full_context_save are the counterparts * to these functions. * * Entry Conditions: @@ -269,16 +269,16 @@ _xtensa_context_save: * ****************************************************************************/ - .global _xtensa_full_context_restore - .global _xtensa_context_restore - .type _xtensa_full_context_restore,@function - .type _xtensa_context_restore,@function + .global xtensa_full_context_restore + .global xtensa_context_restore + .type xtensa_full_context_restore,@function + .type xtensa_context_restore,@function .align 4 .literal_position .align 4 -_xtensa_full_context_restore: +xtensa_full_context_restore: #ifndef CONFIG_XTENSA_CALL0_ABI /* Restore Call0 ABI callee-saved regs a12-15. */ @@ -289,7 +289,7 @@ _xtensa_full_context_restore: l32i a15, sp, (4 * REG_A15) #endif -_xtensa_context_restore: +xtensa_context_restore: #if XTENSA_EXTRA_SA_SIZE > 0 /* NOTE: Normally the xthal_restore_extra_nw macro only affects address diff --git a/arch/xtensa/src/common/xtensa_dumpstate.c b/arch/xtensa/src/common/xtensa_dumpstate.c index 14217d0117..0fd5538f30 100644 --- a/arch/xtensa/src/common/xtensa_dumpstate.c +++ b/arch/xtensa/src/common/xtensa_dumpstate.c @@ -95,7 +95,8 @@ static void xtensa_stackdump(uint32_t sp, uint32_t stack_base) static inline void xtensa_registerdump(void) { - uint32_ *regs = CURRENT_REGS; + uint32_t *regs = (uint32_t *)CURRENT_REGS; /* Don't need volatile here */ + /* Are user registers available from interrupt processing? */ if (regs != NULL) diff --git a/arch/xtensa/src/common/xtensa_exit.c b/arch/xtensa/src/common/xtensa_exit.c index 0bc6da54d8..0352a4d8f5 100644 --- a/arch/xtensa/src/common/xtensa_exit.c +++ b/arch/xtensa/src/common/xtensa_exit.c @@ -142,8 +142,8 @@ void _exit(int status) { struct tcb_s *tcb; - /* Disable interrupts. They will be restored when the next - * task is started. + /* Disable interrupts. They will be restored when the next task is + * started. */ (void)up_irq_save(); @@ -177,7 +177,7 @@ void _exit(int status) /* Then switch contexts */ - up_fullcontextrestore(tcb->xcp.regs); + xtensa_full_context_restore(tcb->xcp.regs); /* up_fullcontextrestore() should not return but could if the software * interrupts are disabled. diff --git a/arch/xtensa/src/common/xtensa_inthandlers.S b/arch/xtensa/src/common/xtensa_inthandlers.S index cac66b0892..cc48797c80 100644 --- a/arch/xtensa/src/common/xtensa_inthandlers.S +++ b/arch/xtensa/src/common/xtensa_inthandlers.S @@ -272,7 +272,7 @@ * a CALL0 instruction. See "NOTES on the use of call0 ..." above. * * The corresponding handler sets up the appropriate stack frame, saves - * a few vector-specific registers and calls _xtensa_full_context_save() + * a few vector-specific registers and calls xtensa_full_context_save() * to save the rest of the interrupted context. It then calls the C * logic to decode the specific interrupt source and dispatch to the * appropriate C interrupt handler. @@ -296,7 +296,7 @@ _xtensa_level2_handler: /* Save rest of interrupt context and enter RTOS. */ - call0 _xtensa_full_context_save /* Save full register state */ + call0 xtensa_full_context_save /* Save full register state */ /* Set up PS for C, enable interrupts above this level and clear EXCM. */ diff --git a/arch/xtensa/src/esp32/esp32_intdecode.c b/arch/xtensa/src/esp32/esp32_intdecode.c index 96bc4c8092..5490e614e3 100644 --- a/arch/xtensa/src/esp32/esp32_intdecode.c +++ b/arch/xtensa/src/esp32/esp32_intdecode.c @@ -39,6 +39,9 @@ #include +#include + +#include "chip/esp32_dport.h" #include "xtensa.h" /**************************************************************************** @@ -70,7 +73,6 @@ uint32_t *xtensa_int_decode(uint32_t *regs) int regndx; int bit; int baseirq; - int irq; #ifdef CONFIG_SMP int cpu; -- GitLab From cf5fdf1f8fc0413c9dc1ff361df470ee3349ac9f Mon Sep 17 00:00:00 2001 From: Frank Benkert Date: Fri, 21 Oct 2016 07:09:20 -0600 Subject: [PATCH 161/734] SAM Watchdog: Register the watchdog device at the configured device path CONFIG_WATCHDOG_DEVPATH vs. hard-coded /dev/wdt --- arch/arm/src/sam34/sam_wdt.c | 4 +++- arch/arm/src/sama5/sam_wdt.c | 6 ++++-- arch/arm/src/samv7/sam_wdt.c | 6 ++++-- 3 files changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/arm/src/sam34/sam_wdt.c b/arch/arm/src/sam34/sam_wdt.c index 62075d9a76..a75f63097b 100644 --- a/arch/arm/src/sam34/sam_wdt.c +++ b/arch/arm/src/sam34/sam_wdt.c @@ -695,7 +695,9 @@ void sam_wdtinitialize(FAR const char *devpath) priv->window = priv->reload; - /* Register the watchdog driver as /dev/watchdog0 */ + /* Register the watchdog driver, usually at CONFIG_WATCHDOG_DEVPATH + * (default /dev/watchdog0). + */ (void)watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv); diff --git a/arch/arm/src/sama5/sam_wdt.c b/arch/arm/src/sama5/sam_wdt.c index 26f40860b7..342aa5c8f3 100644 --- a/arch/arm/src/sama5/sam_wdt.c +++ b/arch/arm/src/sama5/sam_wdt.c @@ -687,9 +687,11 @@ int sam_wdt_initialize(void) (void)irq_attach(SAM_IRQ_WDT, sam_interrupt); #endif - /* Register the watchdog driver as /dev/watchdog0 */ + /* Register the watchdog driver at the configured location (default + * /dev/watchdog0). + */ - (void)watchdog_register("/dev/watchdog0", + (void)watchdog_register(CONFIG_WATCHDOG_DEVPATH, (FAR struct watchdog_lowerhalf_s *)priv); return OK; } diff --git a/arch/arm/src/samv7/sam_wdt.c b/arch/arm/src/samv7/sam_wdt.c index d317bbd74d..850fd2288c 100644 --- a/arch/arm/src/samv7/sam_wdt.c +++ b/arch/arm/src/samv7/sam_wdt.c @@ -687,9 +687,11 @@ int sam_wdt_initialize(void) (void)irq_attach(SAM_IRQ_WDT, sam_interrupt); #endif - /* Register the watchdog driver as /dev/wdt */ + /* Register the watchdog driver as device-node configured via .config. + * Normally /dev/watchdog0 + */ - (void)watchdog_register("/dev/wdt", + (void)watchdog_register(CONFIG_WATCHDOG_DEVPATH, (FAR struct watchdog_lowerhalf_s *)priv); return OK; } -- GitLab From 7a007a1e8e537353d63830183092d5b63db812e2 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 21 Oct 2016 07:35:56 -0600 Subject: [PATCH 162/734] ESP32: The ESP32 Core V2 board does not have any user controllable LEDs. --- arch/xtensa/src/common/xtensa_exit.c | 2 +- configs/Kconfig | 1 - configs/esp32-core/README.txt | 35 ++++++++-------------------- configs/esp32-core/include/board.h | 21 ----------------- configs/esp32-core/nsh/defconfig | 6 ----- 5 files changed, 11 insertions(+), 54 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_exit.c b/arch/xtensa/src/common/xtensa_exit.c index 0352a4d8f5..9d54bf9ede 100644 --- a/arch/xtensa/src/common/xtensa_exit.c +++ b/arch/xtensa/src/common/xtensa_exit.c @@ -179,7 +179,7 @@ void _exit(int status) xtensa_full_context_restore(tcb->xcp.regs); - /* up_fullcontextrestore() should not return but could if the software + /* xtensa_full_context_restore() should not return but could if the software * interrupts are disabled. */ diff --git a/configs/Kconfig b/configs/Kconfig index e61761409f..9385de296b 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -173,7 +173,6 @@ config ARCH_BOARD_EKKLM3S9B96 config ARCH_BOARD_ESP32CORE bool "Expressif ESP32 Core board V2" depends on ARCH_CHIP_ESP32 - select ARCH_HAVE_LEDS ---help--- The ESP32 is a dual-core system from Expressif with two Harvard architecture Xtensa LX6 CPUs. All embedded memory, external memory diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index 2b8278dab3..50fd2d273d 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -84,35 +84,20 @@ Serial Console Buttons and LEDs ================ - NOTE: As of this writing, I have no schematic for the ESP32 Core board. - The following information derives only from examining the parts visible - on the board. - Buttons ------- - I see two buttons labelled Boot and EN. I suspect that neither is - available to software. + There are two buttons labeled Boot and EN. The EN button is not available + to software. It pulls the chip enable line that doubles as a reset line. + + The BOOT button is connected to IO0. On reset it is used as a strapping + pin to determine whether the chip boots normally or into the serial + bootloader. After reset, however, the BOOT button can be used for software + input. LEDs - A single LED labelled D1 is available. - - When CONFIG_ARCH_LEDS is defined in the NuttX configuration, NuttX will - control the LED as follows: - - SYMBOL Meaning LED - ------------------- ----------------------- ------ - LED_STARTED NuttX has been started OFF - LED_HEAPALLOCATE Heap has been allocated OFF - LED_IRQSENABLED Interrupts enabled OFF - LED_STACKCREATED Idle stack created ON - LED_INIRQ In an interrupt N/C - LED_SIGNAL In a signal handler N/C - LED_ASSERTION An assertion failed N/C - LED_PANIC The system has crashed FLASH - - Thus is LED is statically on, NuttX has successfully booted and is, - apparently, running normally. If LED is flashing at approximately - 2Hz, then a fatal error has been detected and the system has halted. + ---- + There are several on-board LEDs for that indicate the presence of power + and USB activity. None of these are available for use by sofware. Configurations ============== diff --git a/configs/esp32-core/include/board.h b/configs/esp32-core/include/board.h index 2a82eb16e8..678a3c1e5e 100644 --- a/configs/esp32-core/include/board.h +++ b/configs/esp32-core/include/board.h @@ -40,25 +40,4 @@ * Pre-processor Definitions ****************************************************************************/ -/* A single LED labelled D1 is available. - * - * When CONFIG_ARCH_LEDS is defined in the NuttX configuration, NuttX will - * control the LED as follows: - * - * SYMBOL Value Meaning LED - * ------------------- ----- ----------------------- ------ */ -#define LED_STARTED 0 /* NuttX has been started OFF */ -#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */ -#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */ -#define LED_STACKCREATED 1 /* Idle stack created ON */ -#define LED_INIRQ 2 /* In an interrupt N/C */ -#define LED_SIGNAL 2 /* In a signal handler N/C */ -#define LED_ASSERTION 2 /* An assertion failed N/C */ -#define LED_PANIC 3 /* The system has crashed FLASH */ - -/* Thus if the LED is statically on, NuttX has successfully booted and is, - * apparently, running normally. If LED is flashing at approximately - * 2Hz, then a fatal error has been detected and the system has halted. - */ - #endif /* __CONFIGS_ESP32_CORE_INCLUDE_BOARD_H */ diff --git a/configs/esp32-core/nsh/defconfig b/configs/esp32-core/nsh/defconfig index 6e1935c244..67a5268ab1 100644 --- a/configs/esp32-core/nsh/defconfig +++ b/configs/esp32-core/nsh/defconfig @@ -75,9 +75,6 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_FAMILY_LX6=y CONFIG_XTENSA_NCOPROCESSORS=1 -CONFIG_XTENSA_INT_NLEVELS=5 -CONFIG_XTENSA_EXCM_LEVEL=3 -# CONFIG_XTENSA_HAVE_LOOPS is not set CONFIG_XTENSA_HAVE_INTERRUPTS=y # CONFIG_XTENSA_USE_SWPRI is not set CONFIG_XTENSA_CALL0_ABI=y @@ -149,8 +146,6 @@ CONFIG_ARCH_BOARD="esp32-core" # # Common Board Options # -CONFIG_ARCH_HAVE_LEDS=y -CONFIG_ARCH_LEDS=y # # Board-Specific Options @@ -324,7 +319,6 @@ CONFIG_SPI_EXCHANGE=y # # LED Support # -# CONFIG_USERLED is not set # CONFIG_RGBLED is not set # CONFIG_PCA9635PW is not set # CONFIG_NCP5623C is not set -- GitLab From f07601a0675a8ed632c5755c653a5e09ce4ccd67 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 21 Oct 2016 10:43:59 -0600 Subject: [PATCH 163/734] Xtensa: First cat at context switching functions --- arch/xtensa/include/irq.h | 1 - arch/xtensa/src/common/xtensa.h | 10 +- arch/xtensa/src/common/xtensa_blocktask.c | 175 +++++++++ arch/xtensa/src/common/xtensa_context.S | 347 +++++++++++------- arch/xtensa/src/common/xtensa_copystate.c | 2 +- arch/xtensa/src/common/xtensa_inthandlers.S | 45 ++- .../xtensa/src/common/xtensa_releasepending.c | 144 ++++++++ .../src/common/xtensa_reprioritizertr.c | 198 ++++++++++ .../xtensa/src/common/xtensa_schedsigaction.c | 190 ++++++++++ arch/xtensa/src/common/xtensa_sigdeliver.c | 126 +++++++ arch/xtensa/src/common/xtensa_unblocktask.c | 159 ++++++++ arch/xtensa/src/esp32/Make.defs | 8 +- arch/xtensa/src/esp32/esp32_cpustart.c | 2 +- 13 files changed, 1251 insertions(+), 156 deletions(-) create mode 100644 arch/xtensa/src/common/xtensa_blocktask.c create mode 100644 arch/xtensa/src/common/xtensa_releasepending.c create mode 100644 arch/xtensa/src/common/xtensa_reprioritizertr.c create mode 100644 arch/xtensa/src/common/xtensa_schedsigaction.c create mode 100644 arch/xtensa/src/common/xtensa_sigdeliver.c create mode 100644 arch/xtensa/src/common/xtensa_unblocktask.c diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index 8960754da2..4eece4c34b 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -157,7 +157,6 @@ struct xcptcontext /* These are saved copies of registers used during signal processing. */ uint32_t saved_pc; - uint32_t saved_cpsr; #endif /* Register save area */ diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index 7f193ab97c..063edbe473 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -248,15 +248,15 @@ void xtensa_dumpstate(void); uint32_t *xtensa_int_decode(uint32_t *regs); uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs); -void xtensa_context_save(uint32_t *regs); -void xtensa_full_context_save(uint32_t *regs); -void xtensa_context_restore(uint32_t *regs); -void xtensa_full_context_restore(uint32_t *regs); - /* Software interrupt handler */ int xtensa_swint(int irq, FAR void *context); +/* Synchronous context switching */ + +int xtensa_context_save(uint32_t *regs); +int xtensa_context_restore(uint32_t *regs); + /* Signals */ void xtensa_sigdeliver(void); diff --git a/arch/xtensa/src/common/xtensa_blocktask.c b/arch/xtensa/src/common/xtensa_blocktask.c new file mode 100644 index 0000000000..82eb5e30c9 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_blocktask.c @@ -0,0 +1,175 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_blocktask.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "group/group.h" +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_block_task + * + * Description: + * The currently executing task at the head of + * the ready to run list must be stopped. Save its context + * and move it to the inactive list specified by task_state. + * + * Inputs: + * tcb: Refers to a task in the ready-to-run list (normally + * the task at the head of the list). It most be + * stopped, its context saved and moved into one of the + * waiting task lists. It it was the task at the head + * of the ready-to-run list, then a context to the new + * ready to run task must be performed. + * task_state: Specifies which waiting task list should be + * hold the blocked task TCB. + * + ****************************************************************************/ + +void up_block_task(struct tcb_s *tcb, tstate_t task_state) +{ + struct tcb_s *rtcb = this_task(); + bool switch_needed; + + /* Verify that the context switch can be performed */ + + ASSERT((tcb->task_state >= FIRST_READY_TO_RUN_STATE) && + (tcb->task_state <= LAST_READY_TO_RUN_STATE)); + + /* Remove the tcb task from the ready-to-run list. If we + * are blocking the task at the head of the task list (the + * most likely case), then a context switch to the next + * ready-to-run task is needed. In this case, it should + * also be true that rtcb == tcb. + */ + + switch_needed = sched_removereadytorun(tcb); + + /* Add the task to the specified blocked task list */ + + sched_addblocked(tcb, (tstate_t)task_state); + + /* If there are any pending tasks, then add them to the ready-to-run + * task list now + */ + + if (g_pendingtasks.head) + { + switch_needed |= sched_mergepending(); + } + + /* Now, perform the context switch if one is needed */ + + if (switch_needed) + { + /* Update scheduler parameters */ + + sched_suspend_scheduler(rtcb); + + /* Are we in an interrupt handler? */ + + if (CURRENT_REGS) + { + /* Yes, then we have to do things differently. + * Just copy the CURRENT_REGS into the OLD rtcb. + */ + + xtensa_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + + /* Reset scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + xtensa_restorestate(rtcb->xcp.regs); + } + + /* Copy the user C context into the TCB at the (old) head of the + * ready-to-run Task list. if up_saveusercontext returns a non-zero + * value, then this is really the previously running task restarting! + */ + + else if (!xtensa_context_save(rtcb->xcp.regs)) + { + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(rtcb); +#endif + /* Reset scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts */ + + xtensa_context_restore(rtcb->xcp.regs); + } + } +} diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index b1e7714d47..840620b4e5 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -76,95 +76,76 @@ .text /**************************************************************************** - * Name: xtensa_context_save - * xtensa_full_context_save + * Name: _xtensa_context_save * * Description: * * NOTE: MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION! * - * These functions save Xtensa processor state: - * - * - xtensa_full_context_save saves all registers except PC, PS, A0, and - * A1 (SP) - * - xtensa_context_save, in addition, does not save A12-A15 which - * are preserved by the callee). + * This function saves Xtensa processor state: xtensa_context_save + * saves all registers except PC, PS, A0, A1 (SP), and A2 * - * Caller is expected to have saved PC, PS, A0, and A1 (SP). + * This function is called directly by interrupt handling logic and from + * xtensa_context_save() below with interrupts disabled. In either calling + * context, caller saves saves PC, PS, A0, A1 (SP), and A2. This + * logic also executes indirectly from xtena_context_save() by falling + * through from above. * - * The counterparts to these functions are xtensa_context_restore() and - * xtensa_full_context_restore(). + * The counterpart to this function is _xtensa_context_restore(). * * Entry Conditions: - * - A0 = Return address in caller. - * - A1 = Stack pointer of calling thread or interrupt handler. - * - Other processor state except PC, PS, A0, and A1 (SP) are as at + * - A0 = Return address to caller. + * - A2 = Pointer to the processor state save area + * - Other processor state except PC, PS, A0, A1 (SP), and A2 are as at * the point of interruption. - * - If windowed ABI, PS.EXCM = 1 (exceptions disabled). * - * Exit conditions: + * Exit conditions: * - A0 = Return address in caller. - * - A1 = Stack pointer of interrupted thread or handler ("interruptee"). - * - A12-A15 as at entry (preserved). + * - A2, A12-A15 as at entry (preserved). + * + * Assumptions: + * - Caller is expected to have saved PC, PS, A0, A1 (SP), and A2. * - If windowed ABI, PS.EXCM = 1 (exceptions disabled). * ****************************************************************************/ - .global xtensa_full_context_save - .global xtensa_context_save - .type xtensa_full_context_save, @function - .type xtensa_context_save, @function + .global _xtensa_context_save + .type _xtensa_context_save, @function .align 4 .literal_position .align 4 -xtensa_full_context_save: - -#ifndef CONFIG_XTENSA_CALL0_ABI - /* Save Call0 ABI callee-saved regs a12-15. */ +_xtensa_context_save: - s32i a12, sp, (4 * REG_A12) - s32i a13, sp, (4 * REG_A13) - s32i a14, sp, (4 * REG_A14) - s32i a15, sp, (4 * REG_A15) -#endif + s32i a2, a2, (4 * REG_A2) + s32i a3, a2, (4 * REG_A3) + s32i a4, a2, (4 * REG_A4) + s32i a5, a2, (4 * REG_A5) + s32i a6, a2, (4 * REG_A6) + s32i a7, a2, (4 * REG_A7) + s32i a8, a2, (4 * REG_A8) + s32i a9, a2, (4 * REG_A9) + s32i a10, a2, (4 * REG_A10) + s32i a11, a2, (4 * REG_A11) -xtensa_context_save: + /* Call0 ABI callee-saved regs a12-15 */ - s32i a2, sp, (4 * REG_A2) - s32i a3, sp, (4 * REG_A3) - s32i a4, sp, (4 * REG_A4) - s32i a5, sp, (4 * REG_A5) - s32i a6, sp, (4 * REG_A6) - s32i a7, sp, (4 * REG_A7) - s32i a8, sp, (4 * REG_A8) - s32i a9, sp, (4 * REG_A9) - s32i a10, sp, (4 * REG_A10) - s32i a11, sp, (4 * REG_A11) - - /* Call0 ABI callee-saved regs a12-15 do not need to be saved here. - * a12-13 are the caller's responsibility so it can use them as scratch. - * So only need to save a14-a15 here for Windowed ABI (not Call0). - */ - -#ifndef CONFIG_XTENSA_CALL0_ABI - s32i a12, sp, (4 * REG_A12) - s32i a13, sp, (4 * REG_A13) - s32i a14, sp, (4 * REG_A14) - s32i a15, sp, (4 * REG_A15) -#endif + s32i a12, a2, (4 * REG_A12) + s32i a13, a2, (4 * REG_A13) + s32i a14, a2, (4 * REG_A14) + s32i a15, a2, (4 * REG_A15) rsr a3, SAR - s32i a3, sp, (4 * REG_SAR) + s32i a3, a2, (4 * REG_SAR) #ifdef XTENSA_HAVE_LOOPS rsr a3, LBEG - s32i a3, sp, (4 * REG_LBEG) + s32i a3, a2, (4 * REG_LBEG) rsr a3, LEND - s32i a3, sp, (4 * REG_LEND) + s32i a3, a2, (4 * REG_LEND) rsr a3, LCOUNT - s32i a3, sp, (4 * REG_LCOUNT) + s32i a3, a2, (4 * REG_LCOUNT) #endif #ifdef CONFIG_XTENSA_USE_SWPRI @@ -172,7 +153,7 @@ xtensa_context_save: movi a3, _xtensa_vprimask l32i a3, a3, 0 - s32i a3, sp, (4 * REG_VPRI) + s32i a3, a2, (4 * REG_VPRI) #endif #if XTENSA_EXTRA_SA_SIZE > 0 || !defined(CONFIG_XTENSA_CALL0_ABI) @@ -187,9 +168,9 @@ xtensa_context_save: * disabled (assured by PS.EXCM == 1). */ - s32i a12, sp, (4 * REG_TMP0) /* Temp. save stuff in stack frame */ - s32i a13, sp, (4 * REG_TMP1) - s32i a9, sp, (4 * REG_TMP2) + s32i a12, a2, (4 * REG_TMP0) /* Temp. save stuff in stack frame */ + s32i a13, a2, (4 * REG_TMP1) + s32i a9, a2, (4 * REG_TMP2) /* Save the overlay state if we are supporting overlays. Since we just * saved three registers, we can conveniently use them here. Note that @@ -197,14 +178,16 @@ xtensa_context_save: */ #ifdef CONFIG_XTENSA_USE_OVLY - l32i a9, sp, (4 * REG_PC) /* Recover saved PC */ + l32i a9, a2, (4 * REG_PC) /* Recover saved PC */ _xt_overlay_get_state a9, a12, a13 - s32i a9, sp, (4 * REG_OVLY) /* Save overlay state */ + s32i a9, a2, (4 * REG_OVLY) /* Save overlay state */ #endif - l32i a12, sp, (4 * REG_A12) /* Recover original a9,12,13 */ - l32i a13, sp, (4 * REG_A13) - l32i a9, sp, (4 * REG_A9) + l32i a12, a2, (4 * REG_A12) /* Recover original a9,12,13 */ + l32i a13, a2, (4 * REG_A13) + l32i a9, a2, (4 * REG_A9) + +#warning REVISIT: The following is probably not correct due to changes in registers addi sp, sp, (4 * XCPTCONTEXT_SIZE) /* Restore the interruptee's SP */ call0 xthal_window_spill_nw /* Preserves only a4,5,8,9,12,13 */ addi sp, sp, -(4 * XCPTCONTEXT_SIZE) @@ -223,7 +206,7 @@ xtensa_context_save: * Future Xtensa tools releases might limit the regs that can be affected. */ - addi a2, sp, (4 * REG_EXTRA) /* Where to save it */ + addi a2, a2, (4 * REG_EXTRA) /* Where to save it */ #if XTENSA_EXTRA_SA_ALIGN > 16 movi a3, -XTENSA_EXTRA_SA_ALIGN and a2, a2, a3 /* Align dynamically >16 bytes */ @@ -238,58 +221,99 @@ xtensa_context_save: ret /**************************************************************************** - * Name: xtensa_context_restore - * xtensa_full_context_restore + * Name: xtensa_context_save * * Description: * * NOTE: MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION! * - * These functions restores Xtensa processor state and differ in which - * registers are saved: + * This functions implements the moral equivalent of setjmp(). It is + * called from user code (with interrupts disabled) to save the current + * state of the running thread. This function always returns zero. + * However, it sets the saved value of the return address (A2) to 1. + * If the thread is restarted via _xtensa_contest_restore or + * xtensa_context_restore, it will appear as a second return from + * xtensa_context_save but with the returned value of 1 to distinguish + * the two cases. + * + * The counterpart to this function is xtensa_context_restore(). + * + * Entry Conditions: + * - A0 = Return address to caller. + * - A2 = Pointer to the processor state save area + * + * Exit conditions: + * - A0 = Return address in caller. + * - A2 = 0 + * + * Assumptions: + * - Interrupts are disabled. + * + ****************************************************************************/ + + .global xtensa_context_save + .type xtensa_context_save, @function + + .align 4 + .literal_position + .align 4 + +xtensa_context_save: + + /* Set up for call to _xtensa_context_save() */ + + rsr a12, EPS_2 /* Save callee's PS */ + s32i a12, a2, (4 * REG_PS) + s32i a0, a2, (4 * REG_PC) /* Save Return address as PC */ + + s32i a0, a2, (4 * REG_A0) /* Save callee's a0 */ + s32i sp, a2, (4 * REG_A1) /* Save callee's SP */ + movi a12, 1 /* Set saved A2 to 1 */ + s32i a12, a2, (4 * REG_A2) + + /* Save the rest of the processor state */ + + call0 _xtensa_context_save /* Save full register state */ + + /* Recover the return address and return zero */ + + l32i a0, a2, (4 * REG_A0) /* Recover return addess */ + movi a2, 0 /* Return zero */ + ret + +/**************************************************************************** + * Name: _xtensa_context_restore + * + * Description: * - * - xtensa_full_context_restore restores all registers except PC, PS, - * A0, and A1 (SP) - * - xtensa_context_restore, in addition, does not restore A12-A15 which - * are preserved by the callee). + * NOTE: MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION! + * + * These functions restores Xtensa processor state and differ in which + * registers are saved: _xtensa_context_restore() restores all registers + * except PC, PS, and A0 * - * The caller is responsible for restoring PC, PS, A0, A1 (SP) in both cases. + * The caller is responsible for restoring PC, PS, and A0 in both cases. * - * xtensa_context_save and xtensa_full_context_save are the counterparts - * to these functions. + * _xtensa_context_save is the counterpart to this function. * * Entry Conditions: * - A0 = Return address in caller. - * - A1 = Stack pointer of calling thread or interrupt handler. + * - A2 = Pointer to the processor state save area * * Exit conditions: * - A0 = Return address in caller. - * - A1 = Stack pointer of calling thread or interrupt handler. - * - Other registers are restored as detailed above. + * - Other registers are restored as detailed above (including A1 and A2). * ****************************************************************************/ - .global xtensa_full_context_restore - .global xtensa_context_restore - .type xtensa_full_context_restore,@function - .type xtensa_context_restore,@function + .global _xtensa_context_restore + .type _xtensa_context_restore,@function .align 4 .literal_position .align 4 -xtensa_full_context_restore: - -#ifndef CONFIG_XTENSA_CALL0_ABI - /* Restore Call0 ABI callee-saved regs a12-15. */ - - l32i a12, sp, (4 * REG_A12) - l32i a13, sp, (4 * REG_A13) - l32i a14, sp, (4 * REG_A14) - l32i a15, sp, (4 * REG_A15) -#endif - -xtensa_context_restore: +_xtensa_context_restore: #if XTENSA_EXTRA_SA_SIZE > 0 /* NOTE: Normally the xthal_restore_extra_nw macro only affects address @@ -302,7 +326,7 @@ xtensa_context_restore: */ mov a13, a0 /* Preserve ret addr */ - addi a2, sp, (4 * REG_EXTRA) /* Where to find it */ + addi a2, a2, (4 * REG_EXTRA) /* Where to find it */ #if XTENSA_EXTRA_SA_ALIGN > 16 movi a3, -XTENSA_EXTRA_SA_ALIGN @@ -313,10 +337,10 @@ xtensa_context_restore: #endif #ifdef XTENSA_HAVE_LOOPS - l32i a2, sp, (4 * REG_LBEG) - l32i a3, sp, (4 * REG_LEND) + l32i a2, a2, (4 * REG_LBEG) + l32i a3, a2, (4 * REG_LEND) wsr a2, LBEG - l32i a2, sp, (4 * REG_LCOUNT) + l32i a2, a2, (4 * REG_LCOUNT) wsr a3, LEND wsr a2, LCOUNT #endif @@ -329,13 +353,13 @@ xtensa_context_restore: * to be restored. */ - l32i a2, sp, (4 * REG_PC) /* Retrieve PC */ - l32i a3, sp, (4 * REG_PS) /* Retrieve PS */ - l32i a4, sp, (4 * REG_OVLY) /* Retrieve overlay state */ - l32i a5, sp, (4 * REG_A1) /* Retrieve stack ptr */ + l32i a2, a2, (4 * REG_PC) /* Retrieve PC */ + l32i a3, a2, (4 * REG_PS) /* Retrieve PS */ + l32i a4, a2, (4 * REG_OVLY) /* Retrieve overlay state */ + l32i a5, a2, (4 * REG_A1) /* Retrieve stack ptr */ _xt_overlay_check_map a2, a3, a4, a5, a6 - s32i a2, sp, (4 * REG_PC) /* Save updated PC */ - s32i a3, sp, (4 * REG_PS) /* Save updated PS */ + s32i a2, a2, (4 * REG_PC) /* Save updated PC */ + s32i a3, a2, (4 * REG_PS) /* Save updated PS */ #endif #ifdef CONFIG_XTENSA_USE_SWPRI @@ -343,35 +367,96 @@ xtensa_context_restore: movi a3, _xtensa_intdata l32i a4, a3, 0 /* a4 = _xtensa_intenable */ - l32i a5, sp, (4 * REG_VPRI) /* a5 = saved _xtensa_vprimask */ + l32i a5, a2, (4 * REG_VPRI) /* a5 = saved _xtensa_vprimask */ and a4, a4, a5 wsr a4, INTENABLE /* Update INTENABLE */ s32i a5, a3, 4 /* Restore _xtensa_vprimask */ #endif - l32i a3, sp, (4 * REG_SAR) - l32i a2, sp, (4 * REG_A2) + l32i a3, a2, (4 * REG_SAR) + l32i sp, a2, (4 * REG_A1) wsr a3, SAR - l32i a3, sp, (4 * REG_A3) - l32i a4, sp, (4 * REG_A4) - l32i a5, sp, (4 * REG_A5) - l32i a6, sp, (4 * REG_A6) - l32i a7, sp, (4 * REG_A7) - l32i a8, sp, (4 * REG_A8) - l32i a9, sp, (4 * REG_A9) - l32i a10, sp, (4 * REG_A10) - l32i a11, sp, (4 * REG_A11) - - /* Call0 ABI callee-saved regs a12-15 do not need to be restored here. - * However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(), - * so need to be restored anyway, despite being callee-saved in Call0. - */ + l32i a3, a2, (4 * REG_A3) + l32i a4, a2, (4 * REG_A4) + l32i a5, a2, (4 * REG_A5) + l32i a6, a2, (4 * REG_A6) + l32i a7, a2, (4 * REG_A7) + l32i a8, a2, (4 * REG_A8) + l32i a9, a2, (4 * REG_A9) + l32i a10, a2, (4 * REG_A10) + l32i a11, a2, (4 * REG_A11) -#ifndef CONFIG_XTENSA_CALL0_ABI - l32i a12, sp, (4 * REG_A12) - l32i a13, sp, (4 * REG_A13) - l32i a14, sp, (4 * REG_A14) - l32i a15, sp, (4 * REG_A15) -#endif + /* Call0 ABI callee-saved regs a12-15 */ + + l32i a12, a2, (4 * REG_A12) + l32i a13, a2, (4 * REG_A13) + l32i a14, a2, (4 * REG_A14) + l32i a15, a2, (4 * REG_A15) + + /* Finally, restore A2 with the correct value */ + + l32i a2, a2, (4 * REG_A2) + + ret + +/**************************************************************************** + * Name: xtensa_context_restore + * + * Description: + * + * NOTE: MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION! + * + * This functions implements the moral equivalent of longjmp(). It is + * called from user code (with interrupts disabled) to restor the current + * state of the running thread. This function always returns 1 because + * the saved value of A2 was set to 1 in xtensa_context_save(). + * + * The counterpart to this function is xtensa_context_save(). + * + * Entry Conditions: + * - A0 = Return address to caller. + * - A2 = Pointer to the processor state save area + * + * Exit conditions: + * - A0 = Return address in caller. + * - A2 = 1 + * + * NOTE: That this function does NOT return to the caller but rather + * to a new threading context. + * + * Assumptions: + * - Interrupts are disabled. + * + ****************************************************************************/ + .global xtensa_context_restore + .type xtensa_context_restore, @function + + .align 4 + .literal_position + .align 4 + +xtensa_context_restore: + + /* Restore the processor state */ + + call0 _xtensa_context_restore /* Restore full register state */ + + /* Restore PC, PS, and A0. */ + + s32i a0, sp, (4 * REG_PS) + + rsr a12, EPS_2 /* Save callee's PS */ + s32i a12, sp, (4 * REG_PS) + s32i a0, a2, (4 * REG_PC) /* Save Return address as PC */ + + s32i a0, a2, (4 * REG_A0) /* Save callee's a0 */ + s32i sp, a2, (4 * REG_A1) /* Save callee's SP */ + movi a12, 1 /* Set saved A2 to 1 */ + s32i a12, a2, (4 * REG_A2) + + + l32i a0, a2, (4 * REG_A0) /* Recover return addess */ + movi a2, 0 /* Return zero */ ret + diff --git a/arch/xtensa/src/common/xtensa_copystate.c b/arch/xtensa/src/common/xtensa_copystate.c index ade771715d..1e8cfa8c14 100644 --- a/arch/xtensa/src/common/xtensa_copystate.c +++ b/arch/xtensa/src/common/xtensa_copystate.c @@ -49,7 +49,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: up_copystate + * Name: xtensa_copystate ****************************************************************************/ /* A little faster than most memcpy's */ diff --git a/arch/xtensa/src/common/xtensa_inthandlers.S b/arch/xtensa/src/common/xtensa_inthandlers.S index cc48797c80..fbd3e6b08c 100644 --- a/arch/xtensa/src/common/xtensa_inthandlers.S +++ b/arch/xtensa/src/common/xtensa_inthandlers.S @@ -272,7 +272,7 @@ * a CALL0 instruction. See "NOTES on the use of call0 ..." above. * * The corresponding handler sets up the appropriate stack frame, saves - * a few vector-specific registers and calls xtensa_full_context_save() + * a few vector-specific registers and calls _xtensa_context_save() * to save the rest of the interrupted context. It then calls the C * logic to decode the specific interrupt source and dispatch to the * appropriate C interrupt handler. @@ -283,7 +283,9 @@ .section .iram1,"ax" .type _xtensa_level2_handler,@function .align 4 + _xtensa_level2_handler: + mov a0, sp /* sp == a1 */ addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ @@ -296,7 +298,9 @@ _xtensa_level2_handler: /* Save rest of interrupt context and enter RTOS. */ - call0 xtensa_full_context_save /* Save full register state */ + s32i a2, sp, (4 * REG_A2) + movi a2, sp /* Address of state save on stack */ + call0 _xtensa_context_save /* Save full register state */ /* Set up PS for C, enable interrupts above this level and clear EXCM. */ @@ -317,16 +321,17 @@ _xtensa_level2_handler: /* Restore registers in preparation to return from interrupt */ - call0 _xtensa_int_exit + call0 _xtensa_context_restore /* Restore only level-specific regs (the rest were already restored) */ - l32i a0, sp, (4 * REG_PS) /* retrieve interruptee's PS */ + l32i a0, sp, (4 * REG_PS) /* Retrieve interruptee's PS */ wsr a0, EPS_2 - l32i a0, sp, (4 * REG_PC) /* retrieve interruptee's PC */ + l32i a0, sp, (4 * REG_PC) /* Retrieve interruptee's PC */ wsr a0, EPC_2 - l32i a0, sp, (4 * REG_A0) /* retrieve interruptee's A0 */ - l32i sp, sp, (4 * REG_A1) /* remove interrupt stack frame */ + l32i a0, sp, (4 * REG_A0) /* Retrieve interruptee's A0 */ + l32i a2, sp, (4 * REG_A2) /* Retrieve interruptee's A2 */ + l32i sp, sp, (4 * REG_A1) /* Remove interrupt stack frame */ rsync /* Ensure EPS and EPC written */ /* Return from interrupt. RFI restores the PS from EPS_2 and jumps to @@ -381,6 +386,7 @@ documentation: "Microprocessor Programmer's Guide". .section .iram1,"ax" .type _xtensa_level2_handler, @function .align 4 + _xtensa_level2_handler: #ifdef XT_INTEXC_HOOKS @@ -389,8 +395,11 @@ _xtensa_level2_handler: movi a0, _xt_intexc_hooks l32i a0, a0, 2<<2 beqz a0, 1f + .Ln_xtensa_level2_handler_call_hook: + callx0 a0 /* Must NOT disturb stack! */ + 1: #endif @@ -399,7 +408,7 @@ _xtensa_level2_handler: */ .align 4 -.L_xtensa_level2_handler_exit: + rsr a0, EXCSAVE_2 /* Restore a0 */ rfi 2 @@ -409,6 +418,7 @@ _xtensa_level2_handler: .section .iram1,"ax" .type _xtensa_level3_handler, @function .align 4 + _xtensa_level3_handler: #ifdef XT_INTEXC_HOOKS @@ -417,7 +427,9 @@ _xtensa_level3_handler: movi a0, _xt_intexc_hooks l32i a0, a0, 3<<2 beqz a0, 1f + .Ln_xtensa_level3_handler_call_hook: + callx0 a0 /* Must NOT disturb stack! */ 1: #endif @@ -427,7 +439,7 @@ _xtensa_level3_handler: */ .align 4 -.L_xtensa_level3_handler_exit: + rsr a0, EXCSAVE_3 /* Restore a0 */ rfi 3 @@ -437,6 +449,7 @@ _xtensa_level3_handler: .section .iram1,"ax" .type _xtensa_level4_handler,@function .align 4 + _xtensa_level4_handler: #ifdef XT_INTEXC_HOOKS @@ -445,7 +458,9 @@ _xtensa_level4_handler: movi a0, _xt_intexc_hooks l32i a0, a0, 4 << 2 beqz a0, 1f + .Ln_xtensa_level4_handler_call_hook: + callx0 a0 /* Must NOT disturb stack! */ 1: #endif @@ -455,7 +470,7 @@ _xtensa_level4_handler: */ .align 4 -.L_xtensa_level4_handler_exit: + rsr a0, EXCSAVE_4 /* Restore a0 */ rfi 4 @@ -465,6 +480,7 @@ _xtensa_level4_handler: .section .iram1,"ax" .type _xtensa_level5_handler,@function .align 4 + _xtensa_level5_handler: #ifdef XT_INTEXC_HOOKS @@ -473,7 +489,9 @@ _xtensa_level5_handler: movi a0, _xt_intexc_hooks l32i a0, a0, 5 << 2 beqz a0, 1f + .Ln_xtensa_level5_handler_call_hook: + callx0 a0 /* Must NOT disturb stack! */ 1: #endif @@ -482,8 +500,6 @@ _xtensa_level5_handler: * ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE. */ - .align 4 -.L_xtensa_level5_handler_exit: rsr a0, EXCSAVE_5 /* restore a0 */ rfi 5 @@ -493,6 +509,7 @@ _xtensa_level5_handler: .section .iram1,"ax" .type _xtensa_level6_handler, @function .align 4 + _xtensa_level6_handler: #ifdef XT_INTEXC_HOOKS @@ -501,7 +518,9 @@ _xtensa_level6_handler: movi a0, _xt_intexc_hooks l32i a0, a0, 6 << 2 beqz a0, 1f + .Ln_xtensa_level6_handler_call_hook: + callx0 a0 /* Must NOT disturb stack! */ 1: #endif @@ -510,8 +529,6 @@ _xtensa_level6_handler: * ADD HIGH PRIORITY LEVEL 6 INTERRUPT HANDLER CODE HERE. */ - .align 4 -.L_xtensa_level6_handler_exit: rsr a0, EXCSAVE_6 /* Restore a0 */ rfi 6 diff --git a/arch/xtensa/src/common/xtensa_releasepending.c b/arch/xtensa/src/common/xtensa_releasepending.c new file mode 100644 index 0000000000..99dc0c39b8 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_releasepending.c @@ -0,0 +1,144 @@ +/**************************************************************************** + * arch/xtensa/src/common/arm_releasepending.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include "sched/sched.h" +#include "group/group.h" +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_release_pending + * + * Description: + * Release and ready-to-run tasks that have + * collected in the pending task list. This can call a + * context switch if a new task is placed at the head of + * the ready to run list. + * + ****************************************************************************/ + +void up_release_pending(void) +{ + struct tcb_s *rtcb = this_task(); + + sinfo("From TCB=%p\n", rtcb); + + /* Merge the g_pendingtasks list into the ready-to-run task list */ + + /* sched_lock(); */ + if (sched_mergepending()) + { + /* The currently active task has changed! We will need to + * switch contexts. + */ + + /* Update scheduler parameters */ + + sched_suspend_scheduler(rtcb); + + /* Are we operating in interrupt context? */ + + if (CURRENT_REGS) + { + /* Yes, then we have to do things differently. + * Just copy the CURRENT_REGS into the OLD rtcb. + */ + + xtensa_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + + /* Update scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + xtensa_restorestate(rtcb->xcp.regs); + } + + /* Copy the exception context into the TCB of the task that + * was currently active. if up_saveusercontext returns a non-zero + * value, then this is really the previously running task + * restarting! + */ + + else if (!xtensa_context_save(rtcb->xcp.regs)) + { + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(rtcb); +#endif + /* Update scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts */ + + xtensa_context_restore(rtcb->xcp.regs); + } + } +} diff --git a/arch/xtensa/src/common/xtensa_reprioritizertr.c b/arch/xtensa/src/common/xtensa_reprioritizertr.c new file mode 100644 index 0000000000..3cc2978f47 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_reprioritizertr.c @@ -0,0 +1,198 @@ +/**************************************************************************** + * arch/xtensa/src/common/arm_reprioritizertr.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include "sched/sched.h" +#include "group/group.h" +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_reprioritize_rtr + * + * Description: + * Called when the priority of a running or + * ready-to-run task changes and the reprioritization will + * cause a context switch. Two cases: + * + * 1) The priority of the currently running task drops and the next + * task in the ready to run list has priority. + * 2) An idle, ready to run task's priority has been raised above the + * the priority of the current, running task and it now has the + * priority. + * + * Inputs: + * tcb: The TCB of the task that has been reprioritized + * priority: The new task priority + * + ****************************************************************************/ + +void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) +{ + /* Verify that the caller is sane */ + + if (tcb->task_state < FIRST_READY_TO_RUN_STATE || + tcb->task_state > LAST_READY_TO_RUN_STATE +#if SCHED_PRIORITY_MIN > 0 + || priority < SCHED_PRIORITY_MIN +#endif +#if SCHED_PRIORITY_MAX < UINT8_MAX + || priority > SCHED_PRIORITY_MAX +#endif + ) + { + PANIC(); + } + else + { + struct tcb_s *rtcb = this_task(); + bool switch_needed; + + sinfo("TCB=%p PRI=%d\n", tcb, priority); + + /* Remove the tcb task from the ready-to-run list. + * sched_removereadytorun will return true if we just + * remove the head of the ready to run list. + */ + + switch_needed = sched_removereadytorun(tcb); + + /* Setup up the new task priority */ + + tcb->sched_priority = (uint8_t)priority; + + /* Return the task to the specified blocked task list. + * sched_addreadytorun will return true if the task was + * added to the new list. We will need to perform a context + * switch only if the EXCLUSIVE or of the two calls is non-zero + * (i.e., one and only one the calls changes the head of the + * ready-to-run list). + */ + + switch_needed ^= sched_addreadytorun(tcb); + + /* Now, perform the context switch if one is needed */ + + if (switch_needed) + { + /* If we are going to do a context switch, then now is the right + * time to add any pending tasks back into the ready-to-run list. + * task list now + */ + + if (g_pendingtasks.head) + { + sched_mergepending(); + } + + /* Update scheduler parameters */ + + sched_suspend_scheduler(rtcb); + + /* Are we in an interrupt handler? */ + + if (CURRENT_REGS) + { + /* Yes, then we have to do things differently. + * Just copy the CURRENT_REGS into the OLD rtcb. + */ + + xtensa_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + + /* Update scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + xtensa_restorestate(rtcb->xcp.regs); + } + + /* Copy the exception context into the TCB at the (old) head of the + * ready-to-run Task list. if up_saveusercontext returns a non-zero + * value, then this is really the previously running task restarting! + */ + + else if (!xtensa_context_save(rtcb->xcp.regs)) + { + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(rtcb); +#endif + /* Update scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts */ + + xtensa_context_restore(rtcb->xcp.regs); + } + } + } +} diff --git a/arch/xtensa/src/common/xtensa_schedsigaction.c b/arch/xtensa/src/common/xtensa_schedsigaction.c new file mode 100644 index 0000000000..5f6b1cc536 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_schedsigaction.c @@ -0,0 +1,190 @@ +/**************************************************************************** + * arch/xtensa/src/common/arm_schedulesigaction.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "xtensa.h" + +#ifndef CONFIG_DISABLE_SIGNALS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_schedule_sigaction + * + * Description: + * This function is called by the OS when one or more + * signal handling actions have been queued for execution. + * The architecture specific code must configure things so + * that the 'sigdeliver' callback is executed on the thread + * specified by 'tcb' as soon as possible. + * + * This function may be called from interrupt handling logic. + * + * This operation should not cause the task to be unblocked + * nor should it cause any immediate execution of sigdeliver. + * Typically, a few cases need to be considered: + * + * (1) This function may be called from an interrupt handler + * During interrupt processing, all xcptcontext structures + * should be valid for all tasks. That structure should + * be modified to invoke sigdeliver() either on return + * from (this) interrupt or on some subsequent context + * switch to the recipient task. + * (2) If not in an interrupt handler and the tcb is NOT + * the currently executing task, then again just modify + * the saved xcptcontext structure for the recipient + * task so it will invoke sigdeliver when that task is + * later resumed. + * (3) If not in an interrupt handler and the tcb IS the + * currently executing task -- just call the signal + * handler now. + * + ****************************************************************************/ + +void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) +{ + irqstate_t flags; + + sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver); + + /* Make sure that interrupts are disabled */ + + flags = enter_critical_section(); + + /* Refuse to handle nested signal actions */ + + if (!tcb->xcp.sigdeliver) + { + /* First, handle some special cases when the signal is being delivered + * to the currently executing task. + */ + + sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS); + + if (tcb == this_task()) + { + /* CASE 1: We are not in an interrupt handler and a task is + * signalling itself for some reason. + */ + + if (!CURRENT_REGS) + { + /* In this case just deliver the signal now. */ + + sigdeliver(tcb); + } + + /* CASE 2: We are in an interrupt handler AND the interrupted + * task is the same as the one that must receive the signal, then + * we will have to modify the return state as well as the state + * in the TCB. + * + * Hmmm... there looks like a latent bug here: The following logic + * would fail in the strange case where we are in an interrupt + * handler, the thread is signalling itself, but a context switch + * to another task has occurred so that CURRENT_REGS does not + * refer to the thread of this_task()! + */ + + else + { + /* Save the return lr and cpsr and one scratch register + * These will be restored by the signal trampoline after + * the signals have been delivered. + */ + + tcb->xcp.sigdeliver = sigdeliver; + tcb->xcp.saved_pc = CURRENT_REGS[REG_PC]; +#warning REVISIT: Missing logic... need to save interrupt state + + /* Then set up to vector to the trampoline with interrupts + * disabled + */ + + CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver; +#warning REVISIT: Missing logic... need to set interrupt state with interrupts disabled + + /* And make sure that the saved context in the TCB is the same + * as the interrupt return context. + */ + + xtensa_savestate(tcb->xcp.regs); + } + } + + /* Otherwise, we are (1) signaling a task is not running from an + * interrupt handler or (2) we are not in an interrupt handler and the + * running task is signalling some non-running task. + */ + + else + { + /* Save the return lr and cpsr and one scratch register. These + * will be restored by the signal trampoline after the signals + * have been delivered. + */ + + tcb->xcp.sigdeliver = sigdeliver; + tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC]; +#warning REVISIT: Missing logic... need to save interrupt state + + /* Then set up to vector to the trampoline with interrupts + * disabled + */ + + tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver; +#warning REVISIT: Missing logic... need to set interrupt state with interrupts disabled + } + } + + leave_critical_section(flags); +} + +#endif /* !CONFIG_DISABLE_SIGNALS */ diff --git a/arch/xtensa/src/common/xtensa_sigdeliver.c b/arch/xtensa/src/common/xtensa_sigdeliver.c new file mode 100644 index 0000000000..b28ed30d71 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_sigdeliver.c @@ -0,0 +1,126 @@ +/**************************************************************************** + * arch/xtensa/src/common/arm_sigdeliver.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "sched/sched.h" +#include "xtensa.h" + +#ifndef CONFIG_DISABLE_SIGNALS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_sigdeliver + * + * Description: + * This is the a signal handling trampoline. When a signal action was + * posted. The task context was mucked with and forced to branch to this + * location with interrupts disabled. + * + ****************************************************************************/ + +void up_sigdeliver(void) +{ + struct tcb_s *rtcb = this_task(); + uint32_t regs[XCPTCONTEXT_REGS]; + sig_deliver_t sigdeliver; + + /* Save the errno. This must be preserved throughout the signal handling + * so that the user code final gets the correct errno value (probably + * EINTR). + */ + + int saved_errno = rtcb->pterrno; + + board_autoled_on(LED_SIGNAL); + + sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", + rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); + ASSERT(rtcb->xcp.sigdeliver != NULL); + + /* Save the real return state on the stack. */ + + xtensa_copystate(regs, rtcb->xcp.regs); + regs[REG_PC] = rtcb->xcp.saved_pc; +#warbing Missing Logic... Need to restore the correct interrupt here + + /* Get a local copy of the sigdeliver function pointer. we do this so that + * we can nullify the sigdeliver function pointer in the TCB and accept + * more signal deliveries while processing the current pending signals. + */ + + sigdeliver = rtcb->xcp.sigdeliver; + rtcb->xcp.sigdeliver = NULL; + + /* Then restore the task interrupt state */ + + up_irq_restore(regs[REG_CPSR]); + + /* Deliver the signals */ + + sigdeliver(rtcb); + + /* Output any debug messages BEFORE restoring errno (because they may + * alter errno), then disable interrupts again and restore the original + * errno that is needed by the user logic (it is probably EINTR). + */ + + sinfo("Resuming\n"); + (void)up_irq_save(); + rtcb->pterrno = saved_errno; + + /* Then restore the correct state for this thread of execution. */ + + board_autoled_off(LED_SIGNAL); + xtensa_context_restore(regs); +} + +#endif /* !CONFIG_DISABLE_SIGNALS */ diff --git a/arch/xtensa/src/common/xtensa_unblocktask.c b/arch/xtensa/src/common/xtensa_unblocktask.c new file mode 100644 index 0000000000..e7a37ba410 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_unblocktask.c @@ -0,0 +1,159 @@ +/**************************************************************************** + * arch/xtensa/src/common/arm_unblocktask.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include "sched/sched.h" +#include "group/group.h" +#include "clock/clock.h" +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_unblock_task + * + * Description: + * A task is currently in an inactive task list + * but has been prepped to execute. Move the TCB to the + * ready-to-run list, restore its context, and start execution. + * + * Inputs: + * tcb: Refers to the tcb to be unblocked. This tcb is + * in one of the waiting tasks lists. It must be moved to + * the ready-to-run list and, if it is the highest priority + * ready to run task, executed. + * + ****************************************************************************/ + +void up_unblock_task(struct tcb_s *tcb) +{ + struct tcb_s *rtcb = this_task(); + + /* Verify that the context switch can be performed */ + + ASSERT((tcb->task_state >= FIRST_BLOCKED_STATE) && + (tcb->task_state <= LAST_BLOCKED_STATE)); + + /* Remove the task from the blocked task list */ + + sched_removeblocked(tcb); + + /* Add the task in the correct location in the prioritized + * ready-to-run task list + */ + + if (sched_addreadytorun(tcb)) + { + /* The currently active task has changed! We need to do + * a context switch to the new task. + */ + + /* Update scheduler parameters */ + + sched_suspend_scheduler(rtcb); + + /* Are we in an interrupt handler? */ + + if (CURRENT_REGS) + { + /* Yes, then we have to do things differently. + * Just copy the CURRENT_REGS into the OLD rtcb. + */ + + xtensa_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + + /* Update scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + xtensa_restorestate(rtcb->xcp.regs); + } + + /* We are not in an interrupt handler. Copy the user C context + * into the TCB of the task that was previously active. if + * up_saveusercontext returns a non-zero value, then this is really the + * previously running task restarting! + */ + + else if (!xtensa_context_save(rtcb->xcp.regs)) + { + /* Restore the exception context of the new task that is ready to + * run (probably tcb). This is the new rtcb at the head of the + * ready-to-run task list. + */ + + rtcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(rtcb); +#endif + /* Update scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts */ + + xtensa_context_restore(rtcb->xcp.regs); + } + } +} diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 8aef01a506..c9f4ea0ae3 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -41,13 +41,15 @@ HEAD_CSRC = esp32_start.c # Common XTENSA files (arch/xtensa/src/common) CMN_ASRCS = xtensa_context.S xtensa_irq.S xtensa_intvectors.S -CMN_CSRCS = xtensa_assert.c xtensa_copystate.c +CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c CMN_CSRCS += xtensa_createstack.c xtensa_exit.c xtensa_idle.c CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c CMN_CSRCS += xtensa_interruptcontext.c xtensa_irqdispatch.c xtensa_lowputs.c CMN_CSRCS += xtensa_mdelay.c xtensa_modifyreg8.c xtensa_modifyreg16.c -CMN_CSRCS += xtensa_modifyreg32.c xtensa_puts.c xtensa_releasestack.c -CMN_CSRCS += xtensa_stackframe.c xtensa_udelay.c xtensa_usestack.c +CMN_CSRCS += xtensa_modifyreg32.c xtensa_puts.c xtensa_releasepending.c +CMN_CSRCS += xtensa_releasestack.c xtensa_reprioritizertr.c +CMN_CSRCS += xtensa_schedsigaction.c xtensa_sigdeliver.c xtensa_stackframe.c +CMN_CSRCS += xtensa_udelay.c xtensa_unblocktask.c xtensa_usestack.c # Configuration-dependent common XTENSA files diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c index c8e7cc66bb..01e0412c75 100644 --- a/arch/xtensa/src/esp32/esp32_cpustart.c +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -137,7 +137,7 @@ int xtensa_start_handler(int irq, FAR void *context) * be the CPUs NULL task. */ - up_restorestate(tcb->xcp.regs); + xtensa_context_restore(tcb->xcp.regs); return OK; } -- GitLab From cf217c6e87cbde9b617e759c2461d20acba51acc Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 21 Oct 2016 11:24:23 -0600 Subject: [PATCH 164/734] Xtensa: Fix a few more compilation issues --- arch/xtensa/src/common/xtensa.h | 2 +- arch/xtensa/src/common/xtensa_context.S | 37 +++++++------------ arch/xtensa/src/common/xtensa_exit.c | 2 +- .../xtensa/src/common/xtensa_schedsigaction.c | 4 +- arch/xtensa/src/common/xtensa_sigdeliver.c | 10 ++--- 5 files changed, 23 insertions(+), 32 deletions(-) diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index 063edbe473..3065911cf0 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -255,7 +255,7 @@ int xtensa_swint(int irq, FAR void *context); /* Synchronous context switching */ int xtensa_context_save(uint32_t *regs); -int xtensa_context_restore(uint32_t *regs); +void xtensa_context_restore(uint32_t *regs) noreturn_function; /* Signals */ diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index 840620b4e5..01d9e97748 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -59,9 +59,12 @@ ****************************************************************************/ #include + #include #include +#include "xtensa_specregs.h" + #ifdef CONFIG_XTENSA_USE_OVLY # include #endif @@ -262,7 +265,7 @@ xtensa_context_save: /* Set up for call to _xtensa_context_save() */ - rsr a12, EPS_2 /* Save callee's PS */ + rsr a12, PS /* Save callee's PS */ s32i a12, a2, (4 * REG_PS) s32i a0, a2, (4 * REG_PC) /* Save Return address as PC */ @@ -290,9 +293,9 @@ xtensa_context_save: * * These functions restores Xtensa processor state and differ in which * registers are saved: _xtensa_context_restore() restores all registers - * except PC, PS, and A0 + * except PC, PS, A0, and A2 * - * The caller is responsible for restoring PC, PS, and A0 in both cases. + * The caller is responsible for restoring PC, PS, A0, and A2. * * _xtensa_context_save is the counterpart to this function. * @@ -418,9 +421,6 @@ _xtensa_context_restore: * - A2 = Pointer to the processor state save area * * Exit conditions: - * - A0 = Return address in caller. - * - A2 = 1 - * * NOTE: That this function does NOT return to the caller but rather * to a new threading context. * @@ -442,21 +442,12 @@ xtensa_context_restore: call0 _xtensa_context_restore /* Restore full register state */ - /* Restore PC, PS, and A0. */ - - s32i a0, sp, (4 * REG_PS) - - rsr a12, EPS_2 /* Save callee's PS */ - s32i a12, sp, (4 * REG_PS) - s32i a0, a2, (4 * REG_PC) /* Save Return address as PC */ - - s32i a0, a2, (4 * REG_A0) /* Save callee's a0 */ - s32i sp, a2, (4 * REG_A1) /* Save callee's SP */ - movi a12, 1 /* Set saved A2 to 1 */ - s32i a12, a2, (4 * REG_A2) - - - l32i a0, a2, (4 * REG_A0) /* Recover return addess */ - movi a2, 0 /* Return zero */ - ret + /* Restore PC, PS, A0, and A2. */ + l32i a0, a2, (4 * REG_PS) /* Restore PS */ + wsr a0, PS + l32i a0, a2, (4 * REG_PC) /* Set up for RFE */ + rsr a0, EPC + l32i a0, a2, (4 * REG_A0) /* Restore a0 */ + l32i a2, a2, (4 * REG_A2) /* Restore A2 */ + rfe /* And return from "exception" */ diff --git a/arch/xtensa/src/common/xtensa_exit.c b/arch/xtensa/src/common/xtensa_exit.c index 9d54bf9ede..e6c64aaecd 100644 --- a/arch/xtensa/src/common/xtensa_exit.c +++ b/arch/xtensa/src/common/xtensa_exit.c @@ -177,7 +177,7 @@ void _exit(int status) /* Then switch contexts */ - xtensa_full_context_restore(tcb->xcp.regs); + xtensa_context_restore(tcb->xcp.regs); /* xtensa_full_context_restore() should not return but could if the software * interrupts are disabled. diff --git a/arch/xtensa/src/common/xtensa_schedsigaction.c b/arch/xtensa/src/common/xtensa_schedsigaction.c index 5f6b1cc536..76c8669a39 100644 --- a/arch/xtensa/src/common/xtensa_schedsigaction.c +++ b/arch/xtensa/src/common/xtensa_schedsigaction.c @@ -148,7 +148,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) * disabled */ - CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver; + CURRENT_REGS[REG_PC] = (uint32_t)xtensa_sigdeliver; #warning REVISIT: Missing logic... need to set interrupt state with interrupts disabled /* And make sure that the saved context in the TCB is the same @@ -179,7 +179,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) * disabled */ - tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver; + tcb->xcp.regs[REG_PC] = (uint32_t)xtensa_sigdeliver; #warning REVISIT: Missing logic... need to set interrupt state with interrupts disabled } } diff --git a/arch/xtensa/src/common/xtensa_sigdeliver.c b/arch/xtensa/src/common/xtensa_sigdeliver.c index b28ed30d71..381b08f9a7 100644 --- a/arch/xtensa/src/common/xtensa_sigdeliver.c +++ b/arch/xtensa/src/common/xtensa_sigdeliver.c @@ -58,7 +58,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: up_sigdeliver + * Name: xtensa_sigdeliver * * Description: * This is the a signal handling trampoline. When a signal action was @@ -67,7 +67,7 @@ * ****************************************************************************/ -void up_sigdeliver(void) +void xtensa_sigdeliver(void) { struct tcb_s *rtcb = this_task(); uint32_t regs[XCPTCONTEXT_REGS]; @@ -90,7 +90,7 @@ void up_sigdeliver(void) xtensa_copystate(regs, rtcb->xcp.regs); regs[REG_PC] = rtcb->xcp.saved_pc; -#warbing Missing Logic... Need to restore the correct interrupt here +#warning Missing Logic... Need to save the correct interrupt state /* Get a local copy of the sigdeliver function pointer. we do this so that * we can nullify the sigdeliver function pointer in the TCB and accept @@ -101,8 +101,8 @@ void up_sigdeliver(void) rtcb->xcp.sigdeliver = NULL; /* Then restore the task interrupt state */ - - up_irq_restore(regs[REG_CPSR]); +#warning Missing Logic... Need to restore the correct interrupt state + //up_irq_restore(regs[REG_CPSR]); /* Deliver the signals */ -- GitLab From 19a221297178f3f773279cf6b829bbcf606ecbed Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 21 Oct 2016 12:12:04 -0600 Subject: [PATCH 165/734] The buttons example was changed to archbuttons. As a result all of the button configurations are broken and need some renaming in the defconfig files. Noted by Frank Berkert --- configs/hymini-stm32v/buttons/defconfig | 30 +++++++---- configs/hymini-stm32v/nsh2/defconfig | 33 ++++++++---- configs/hymini-stm32v/usbnsh/defconfig | 32 +++++++---- configs/olimex-stm32-h405/usbnsh/defconfig | 32 +++++++---- configs/olimex-stm32-p207/nsh/defconfig | 33 ++++++++---- configs/olimexino-stm32/composite/defconfig | 31 +++++++---- configs/olimexino-stm32/nsh/defconfig | 31 +++++++---- configs/sama5d4-ek/ipv6/defconfig | 55 +++++++++++++------ configs/sama5d4-ek/nsh/defconfig | 55 +++++++++++++------ configs/sama5d4-ek/nxwm/defconfig | 55 +++++++++++++------ configs/same70-xplained/netnsh/defconfig | 37 ++++++++----- configs/same70-xplained/nsh/defconfig | 34 ++++++++---- configs/samv71-xult/mxtxplnd/defconfig | 35 ++++++++---- configs/samv71-xult/netnsh/defconfig | 37 ++++++++----- configs/samv71-xult/nsh/defconfig | 34 ++++++++---- configs/stm3210e-eval/buttons/defconfig | 30 +++++++---- configs/stm3210e-eval/pm/defconfig | 11 ++++ configs/stm32butterfly2/nsh/defconfig | 56 ++++++++++---------- configs/stm32butterfly2/nshnet/defconfig | 20 ++++--- configs/stm32butterfly2/nshusbdev/defconfig | 38 ++++++++----- configs/stm32butterfly2/nshusbhost/defconfig | 39 +++++++++----- configs/stm32l476vg-disco/nsh/defconfig | 39 +++++++++----- 22 files changed, 526 insertions(+), 271 deletions(-) diff --git a/configs/hymini-stm32v/buttons/defconfig b/configs/hymini-stm32v/buttons/defconfig index 159cb319de..39464dac3d 100644 --- a/configs/hymini-stm32v/buttons/defconfig +++ b/configs/hymini-stm32v/buttons/defconfig @@ -63,6 +63,7 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set # CONFIG_ARCH_Z16 is not set @@ -682,6 +683,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -772,6 +774,7 @@ CONFIG_USART1_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -867,6 +870,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -911,19 +916,20 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=1 +CONFIG_EXAMPLES_ARCHBUTTONS=y +CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 +CONFIG_EXAMPLES_ARCHBUTTONS_MAX=1 CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 CONFIG_EXAMPLES_IRQBUTTONS_MAX=1 -CONFIG_EXAMPLES_BUTTONS_NAME0="Key A" -CONFIG_EXAMPLES_BUTTONS_NAME1="Key B" -CONFIG_EXAMPLES_BUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_BUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_BUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_BUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_BUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="Key A" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Key B" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" +# CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -992,6 +998,7 @@ CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7" # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1037,6 +1044,7 @@ CONFIG_SYSTEM_READLINE=y CONFIG_READLINE_ECHO=y # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/hymini-stm32v/nsh2/defconfig b/configs/hymini-stm32v/nsh2/defconfig index 45c640cacf..79ee362dc1 100644 --- a/configs/hymini-stm32v/nsh2/defconfig +++ b/configs/hymini-stm32v/nsh2/defconfig @@ -63,6 +63,7 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set # CONFIG_ARCH_Z16 is not set @@ -724,6 +725,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -776,6 +778,7 @@ CONFIG_LCD_MAXPOWER=100 # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set # CONFIG_LCD_UG9664HSWAG01 is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -918,6 +921,7 @@ CONFIG_USBMSC_SCSI_STACKSIZE=2048 CONFIG_HAVE_USBTRACE=y # CONFIG_USBMONITOR is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1111,6 +1115,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1164,19 +1170,20 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=1 +CONFIG_EXAMPLES_ARCHBUTTONS=y +CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 +CONFIG_EXAMPLES_ARCHBUTTONS_MAX=1 CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 CONFIG_EXAMPLES_IRQBUTTONS_MAX=1 -CONFIG_EXAMPLES_BUTTONS_NAME0="Key A" -CONFIG_EXAMPLES_BUTTONS_NAME1="Key B" -CONFIG_EXAMPLES_BUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_BUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_BUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_BUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_BUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="Key A" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Key B" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" +# CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1292,6 +1299,7 @@ CONFIG_EXAMPLES_TOUCHSCREEN_ARCHINIT=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1363,6 +1371,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1438,6 +1447,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set CONFIG_SYSTEM_USBMSC=y CONFIG_SYSTEM_USBMSC_NLUNS=1 diff --git a/configs/hymini-stm32v/usbnsh/defconfig b/configs/hymini-stm32v/usbnsh/defconfig index f482b3328d..1c7d14202f 100644 --- a/configs/hymini-stm32v/usbnsh/defconfig +++ b/configs/hymini-stm32v/usbnsh/defconfig @@ -63,6 +63,7 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set # CONFIG_ARCH_Z16 is not set @@ -690,6 +691,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -820,6 +822,7 @@ CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial" # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -918,6 +921,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -962,19 +967,20 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=1 +CONFIG_EXAMPLES_ARCHBUTTONS=y +CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 +CONFIG_EXAMPLES_ARCHBUTTONS_MAX=1 CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 CONFIG_EXAMPLES_IRQBUTTONS_MAX=1 -CONFIG_EXAMPLES_BUTTONS_NAME0="Key A" -CONFIG_EXAMPLES_BUTTONS_NAME1="Key B" -CONFIG_EXAMPLES_BUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_BUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_BUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_BUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_BUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="Key A" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Key B" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" +# CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1044,6 +1050,7 @@ CONFIG_EXAMPLES_NSH=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1113,6 +1120,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1182,6 +1190,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/olimex-stm32-h405/usbnsh/defconfig b/configs/olimex-stm32-h405/usbnsh/defconfig index c9828f8f3e..a0deb7cb54 100644 --- a/configs/olimex-stm32-h405/usbnsh/defconfig +++ b/configs/olimex-stm32-h405/usbnsh/defconfig @@ -63,6 +63,7 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set # CONFIG_ARCH_Z16 is not set @@ -743,6 +744,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set CONFIG_ANALOG=y @@ -879,6 +881,7 @@ CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial" # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -978,6 +981,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1040,19 +1045,20 @@ CONFIG_EXAMPLES_ADC=y CONFIG_EXAMPLES_ADC_DEVPATH="/dev/adc0" CONFIG_EXAMPLES_ADC_GROUPSIZE=4 # CONFIG_EXAMPLES_ADC_SWTRIG is not set -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=0 +CONFIG_EXAMPLES_ARCHBUTTONS=y +CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 +CONFIG_EXAMPLES_ARCHBUTTONS_MAX=0 CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 CONFIG_EXAMPLES_IRQBUTTONS_MAX=0 -CONFIG_EXAMPLES_BUTTONS_NAME0="BUT" -CONFIG_EXAMPLES_BUTTONS_NAME1="Button 1" -CONFIG_EXAMPLES_BUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_BUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_BUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_BUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_BUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="BUT" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Button 1" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" +# CONFIG_EXAMPLES_BUTTONS is not set CONFIG_EXAMPLES_CAN=y CONFIG_EXAMPLES_CAN_DEVPATH="/dev/can0" CONFIG_EXAMPLES_CAN_NMSGS=32 @@ -1132,6 +1138,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1202,6 +1209,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set CONFIG_NSH_DISABLE_PUT=y # CONFIG_NSH_DISABLE_PWD is not set @@ -1271,6 +1279,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/olimex-stm32-p207/nsh/defconfig b/configs/olimex-stm32-p207/nsh/defconfig index e1d2bf47a2..3337b0d0b4 100644 --- a/configs/olimex-stm32-p207/nsh/defconfig +++ b/configs/olimex-stm32-p207/nsh/defconfig @@ -63,6 +63,7 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set # CONFIG_ARCH_Z16 is not set @@ -768,6 +769,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set CONFIG_ANALOG=y @@ -907,6 +909,7 @@ CONFIG_USBHOST_NPREALLOC=4 CONFIG_USBHOST_HAVE_ASYNCH=y # CONFIG_USBHOST_ASYNCH is not set # CONFIG_USBHOST_HUB is not set +# CONFIG_USBHOST_COMPOSITE is not set # CONFIG_USBHOST_MSC is not set # CONFIG_USBHOST_CDCACM is not set # CONFIG_USBHOST_HIDKBD is not set @@ -915,6 +918,7 @@ CONFIG_USBHOST_HAVE_ASYNCH=y # CONFIG_USBHOST_TRACE is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1124,6 +1128,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1194,19 +1200,20 @@ CONFIG_EXAMPLES_ADC=y CONFIG_EXAMPLES_ADC_DEVPATH="/dev/adc0" CONFIG_EXAMPLES_ADC_GROUPSIZE=1 # CONFIG_EXAMPLES_ADC_SWTRIG is not set -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=6 +CONFIG_EXAMPLES_ARCHBUTTONS=y +CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 +CONFIG_EXAMPLES_ARCHBUTTONS_MAX=6 CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 CONFIG_EXAMPLES_IRQBUTTONS_MAX=7 -CONFIG_EXAMPLES_BUTTONS_NAME0="Button 0" -CONFIG_EXAMPLES_BUTTONS_NAME1="Button 1" -CONFIG_EXAMPLES_BUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_BUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_BUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_BUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_BUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="Button 0" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Button 1" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" +# CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CAN is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set @@ -1285,6 +1292,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1367,6 +1375,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set CONFIG_NSH_DISABLE_PUT=y @@ -1458,6 +1467,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/olimexino-stm32/composite/defconfig b/configs/olimexino-stm32/composite/defconfig index 13806d1ab8..fcb7a0c8d7 100644 --- a/configs/olimexino-stm32/composite/defconfig +++ b/configs/olimexino-stm32/composite/defconfig @@ -63,6 +63,7 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set # CONFIG_ARCH_Z16 is not set @@ -734,6 +735,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y # CONFIG_RTC_DATETIME is not set # CONFIG_RTC_HIRES is not set @@ -927,6 +929,7 @@ CONFIG_USBMSC_SCSI_STACKSIZE=340 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1035,6 +1038,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set # CONFIG_LIBC_LONG_LONG is not set # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1096,19 +1101,20 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=768 # # Examples # -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=0 +CONFIG_EXAMPLES_ARCHBUTTONS=y +CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 +CONFIG_EXAMPLES_ARCHBUTTONS_MAX=0 CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 CONFIG_EXAMPLES_IRQBUTTONS_MAX=0 -CONFIG_EXAMPLES_BUTTONS_NAME0="BOOT 0" -CONFIG_EXAMPLES_BUTTONS_NAME1="Button 1" -CONFIG_EXAMPLES_BUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_BUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_BUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_BUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_BUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="BOOT 0" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Button 1" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" +# CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1186,6 +1192,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1258,6 +1265,7 @@ CONFIG_NSH_DISABLE_MKFATFS=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PSSTACKUSAGE is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1343,6 +1351,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_STACKMONITOR is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_USBMSC is not set # CONFIG_SYSTEM_VI is not set diff --git a/configs/olimexino-stm32/nsh/defconfig b/configs/olimexino-stm32/nsh/defconfig index 12a981172d..8b9fd359f9 100644 --- a/configs/olimexino-stm32/nsh/defconfig +++ b/configs/olimexino-stm32/nsh/defconfig @@ -63,6 +63,7 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set # CONFIG_ARCH_Z16 is not set @@ -733,6 +734,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y # CONFIG_RTC_DATETIME is not set # CONFIG_RTC_HIRES is not set @@ -856,6 +858,7 @@ CONFIG_USART2_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -964,6 +967,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set # CONFIG_LIBC_LONG_LONG is not set # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1025,19 +1030,20 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=768 # # Examples # -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=0 +CONFIG_EXAMPLES_ARCHBUTTONS=y +CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 +CONFIG_EXAMPLES_ARCHBUTTONS_MAX=0 CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 CONFIG_EXAMPLES_IRQBUTTONS_MAX=0 -CONFIG_EXAMPLES_BUTTONS_NAME0="BOOT 0" -CONFIG_EXAMPLES_BUTTONS_NAME1="Button 1" -CONFIG_EXAMPLES_BUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_BUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_BUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_BUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_BUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="BOOT 0" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Button 1" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" +# CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1115,6 +1121,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1187,6 +1194,7 @@ CONFIG_NSH_DISABLE_MKFATFS=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PSSTACKUSAGE is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1258,6 +1266,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_STACKMONITOR is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sama5d4-ek/ipv6/defconfig b/configs/sama5d4-ek/ipv6/defconfig index a6af39fe39..1e0f9b6ba6 100644 --- a/configs/sama5d4-ek/ipv6/defconfig +++ b/configs/sama5d4-ek/ipv6/defconfig @@ -66,6 +66,7 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set # CONFIG_ARCH_Z16 is not set @@ -493,8 +494,6 @@ CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_HAVE_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 # # Board-Specific Options @@ -520,6 +519,7 @@ CONFIG_SAMA5D4EK_MXT_DEVMINOR=0 CONFIG_SAMA5D4EK_WM8904_I2CFREQUENCY=400000 CONFIG_SAMA5D4EK_WM8904_SRCMAIN=y # CONFIG_SAMA5D4EK_WM8904_SRCSCK is not set +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y @@ -546,6 +546,7 @@ CONFIG_ARCH_HAVE_TICKLESS=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_MAX_WDOGPARMS=2 CONFIG_PREALLOC_WDOGS=32 @@ -642,6 +643,7 @@ CONFIG_DEV_NULL=y CONFIG_DEV_ZERO=y CONFIG_ARCH_HAVE_RNG=y CONFIG_DEV_RANDOM=y +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -668,6 +670,7 @@ CONFIG_I2S=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y CONFIG_RTC_DATETIME=y # CONFIG_RTC_ALARM is not set @@ -704,7 +707,12 @@ CONFIG_MXT_NPOLLWAITERS=4 # CONFIG_BUTTONS is not set # CONFIG_DJOYSTICK is not set # CONFIG_AJOYSTICK is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -843,12 +851,14 @@ CONFIG_USART4_2STOP=0 # CONFIG_USART4_IFLOWCONTROL is not set # CONFIG_USART4_OFLOWCONTROL is not set # CONFIG_USART4_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set CONFIG_USBHOST=y CONFIG_USBHOST_NPREALLOC=4 CONFIG_USBHOST_HAVE_ASYNCH=y # CONFIG_USBHOST_ASYNCH is not set # CONFIG_USBHOST_HUB is not set +# CONFIG_USBHOST_COMPOSITE is not set CONFIG_USBHOST_MSC=y # CONFIG_USBHOST_CDCACM is not set CONFIG_USBHOST_HIDKBD=y @@ -863,7 +873,9 @@ CONFIG_HIDKBD_NPOLLWAITERS=2 # CONFIG_USBHOST_HIDMOUSE is not set # CONFIG_USBHOST_RTL8187 is not set # CONFIG_USBHOST_TRACE is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -884,6 +896,7 @@ CONFIG_RAMLOG_SYSLOG=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set # CONFIG_CONSOLE_SYSLOG is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -1216,6 +1229,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1246,6 +1261,7 @@ CONFIG_LIBC_NETDB=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -1276,22 +1292,22 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=0 +CONFIG_EXAMPLES_ARCHBUTTONS=y +CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 +CONFIG_EXAMPLES_ARCHBUTTONS_MAX=0 CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 CONFIG_EXAMPLES_IRQBUTTONS_MAX=0 -CONFIG_EXAMPLES_BUTTONS_NAME0="PB_USER" -CONFIG_EXAMPLES_BUTTONS_NAME1="Button 1" -CONFIG_EXAMPLES_BUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_BUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_BUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_BUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_BUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="PB_USER" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Button 1" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" +# CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set @@ -1331,10 +1347,10 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RANDOM is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set @@ -1387,6 +1403,7 @@ CONFIG_EXAMPLES_TOUCHSCREEN_ARCHINIT=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1464,12 +1481,12 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1486,6 +1503,8 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 # # Configure Command Options @@ -1594,7 +1613,7 @@ CONFIG_NSH_MAX_ROUNDTRIP=20 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=0 @@ -1624,6 +1643,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sama5d4-ek/nsh/defconfig b/configs/sama5d4-ek/nsh/defconfig index 8313741426..32fefdc17d 100644 --- a/configs/sama5d4-ek/nsh/defconfig +++ b/configs/sama5d4-ek/nsh/defconfig @@ -66,6 +66,7 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set # CONFIG_ARCH_Z16 is not set @@ -493,8 +494,6 @@ CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_HAVE_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 # # Board-Specific Options @@ -520,6 +519,7 @@ CONFIG_SAMA5D4EK_MXT_DEVMINOR=0 CONFIG_SAMA5D4EK_WM8904_I2CFREQUENCY=400000 CONFIG_SAMA5D4EK_WM8904_SRCMAIN=y # CONFIG_SAMA5D4EK_WM8904_SRCSCK is not set +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y @@ -546,6 +546,7 @@ CONFIG_ARCH_HAVE_TICKLESS=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_MAX_WDOGPARMS=2 CONFIG_PREALLOC_WDOGS=32 @@ -642,6 +643,7 @@ CONFIG_DEV_NULL=y CONFIG_DEV_ZERO=y CONFIG_ARCH_HAVE_RNG=y CONFIG_DEV_RANDOM=y +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -668,6 +670,7 @@ CONFIG_I2S=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y CONFIG_RTC_DATETIME=y # CONFIG_RTC_ALARM is not set @@ -704,7 +707,12 @@ CONFIG_MXT_NPOLLWAITERS=4 # CONFIG_BUTTONS is not set # CONFIG_DJOYSTICK is not set # CONFIG_AJOYSTICK is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -845,12 +853,14 @@ CONFIG_USART4_2STOP=0 # CONFIG_USART4_IFLOWCONTROL is not set # CONFIG_USART4_OFLOWCONTROL is not set # CONFIG_USART4_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set CONFIG_USBHOST=y CONFIG_USBHOST_NPREALLOC=4 CONFIG_USBHOST_HAVE_ASYNCH=y # CONFIG_USBHOST_ASYNCH is not set # CONFIG_USBHOST_HUB is not set +# CONFIG_USBHOST_COMPOSITE is not set CONFIG_USBHOST_MSC=y # CONFIG_USBHOST_CDCACM is not set CONFIG_USBHOST_HIDKBD=y @@ -865,7 +875,9 @@ CONFIG_HIDKBD_NPOLLWAITERS=2 # CONFIG_USBHOST_HIDMOUSE is not set # CONFIG_USBHOST_RTL8187 is not set # CONFIG_USBHOST_TRACE is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -886,6 +898,7 @@ CONFIG_RAMLOG_SYSLOG=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set # CONFIG_CONSOLE_SYSLOG is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -1220,6 +1233,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1257,6 +1272,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -1287,22 +1303,22 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=0 +CONFIG_EXAMPLES_ARCHBUTTONS=y +CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 +CONFIG_EXAMPLES_ARCHBUTTONS_MAX=0 CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 CONFIG_EXAMPLES_IRQBUTTONS_MAX=0 -CONFIG_EXAMPLES_BUTTONS_NAME0="PB_USER" -CONFIG_EXAMPLES_BUTTONS_NAME1="Button 1" -CONFIG_EXAMPLES_BUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_BUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_BUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_BUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_BUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="PB_USER" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Button 1" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" +# CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set @@ -1342,10 +1358,10 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RANDOM is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set @@ -1398,6 +1414,7 @@ CONFIG_EXAMPLES_TOUCHSCREEN_ARCHINIT=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1480,13 +1497,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1504,6 +1521,8 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 # # Configure Command Options @@ -1595,7 +1614,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=0 @@ -1625,6 +1644,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sama5d4-ek/nxwm/defconfig b/configs/sama5d4-ek/nxwm/defconfig index 2693a12fb3..d8ca33141b 100644 --- a/configs/sama5d4-ek/nxwm/defconfig +++ b/configs/sama5d4-ek/nxwm/defconfig @@ -66,6 +66,7 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set # CONFIG_ARCH_Z16 is not set @@ -467,8 +468,6 @@ CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_HAVE_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 # # Board-Specific Options @@ -491,6 +490,7 @@ CONFIG_SAMA5D4EK_USBHOST_PRIO=100 CONFIG_SAMA5D4EK_MXT_I2CFREQUENCY=400000 CONFIG_SAMA5D4EK_MXT_DEVMINOR=0 # CONFIG_SAMA5D4EK_SLOWCLOCK is not set +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set @@ -517,6 +517,7 @@ CONFIG_ARCH_HAVE_TICKLESS=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_MAX_WDOGPARMS=2 CONFIG_PREALLOC_WDOGS=32 @@ -616,6 +617,7 @@ CONFIG_DEV_NULL=y CONFIG_DEV_ZERO=y CONFIG_ARCH_HAVE_RNG=y CONFIG_DEV_RANDOM=y +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -642,6 +644,7 @@ CONFIG_I2C_DRIVER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y CONFIG_RTC_DATETIME=y # CONFIG_RTC_ALARM is not set @@ -673,7 +676,12 @@ CONFIG_MXT_NPOLLWAITERS=4 # CONFIG_BUTTONS is not set # CONFIG_DJOYSTICK is not set # CONFIG_AJOYSTICK is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -814,12 +822,14 @@ CONFIG_USART4_2STOP=0 # CONFIG_USART4_IFLOWCONTROL is not set # CONFIG_USART4_OFLOWCONTROL is not set # CONFIG_USART4_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set CONFIG_USBHOST=y CONFIG_USBHOST_NPREALLOC=4 CONFIG_USBHOST_HAVE_ASYNCH=y # CONFIG_USBHOST_ASYNCH is not set # CONFIG_USBHOST_HUB is not set +# CONFIG_USBHOST_COMPOSITE is not set CONFIG_USBHOST_MSC=y # CONFIG_USBHOST_CDCACM is not set CONFIG_USBHOST_HIDKBD=y @@ -834,7 +844,9 @@ CONFIG_HIDKBD_NPOLLWAITERS=2 # CONFIG_USBHOST_HIDMOUSE is not set # CONFIG_USBHOST_RTL8187 is not set # CONFIG_USBHOST_TRACE is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -855,6 +867,7 @@ CONFIG_RAMLOG_SYSLOG=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set # CONFIG_CONSOLE_SYSLOG is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -1208,6 +1221,8 @@ CONFIG_LIBM=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1245,6 +1260,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -1275,22 +1291,22 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=0 +CONFIG_EXAMPLES_ARCHBUTTONS=y +CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 +CONFIG_EXAMPLES_ARCHBUTTONS_MAX=0 CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 CONFIG_EXAMPLES_IRQBUTTONS_MAX=0 -CONFIG_EXAMPLES_BUTTONS_NAME0="PB_USER" -CONFIG_EXAMPLES_BUTTONS_NAME1="Button 1" -CONFIG_EXAMPLES_BUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_BUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_BUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_BUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_BUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="PB_USER" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Button 1" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" +# CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set @@ -1321,10 +1337,10 @@ CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RANDOM is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set @@ -1373,6 +1389,7 @@ CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7" # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1455,13 +1472,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1479,6 +1496,8 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 # # Configure Command Options @@ -1784,7 +1803,7 @@ CONFIG_NXWM_MEDIAPLAYER_MINVOLUMEHEIGHT=6 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=0 @@ -1813,6 +1832,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/same70-xplained/netnsh/defconfig b/configs/same70-xplained/netnsh/defconfig index 1eaf1f773d..c173e39bfe 100644 --- a/configs/same70-xplained/netnsh/defconfig +++ b/configs/same70-xplained/netnsh/defconfig @@ -66,6 +66,7 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set # CONFIG_ARCH_Z16 is not set @@ -195,7 +196,8 @@ CONFIG_ARCH_CHIP_SAME70Q=y # CONFIG_ARCH_CHIP_SAMV71J is not set # CONFIG_SAMV7_MCAN is not set CONFIG_SAMV7_HAVE_MCAN1=y -CONFIG_SAMV7_HAVE_DAC1=y +# CONFIG_SAMV7_DAC is not set +# CONFIG_SAMV7_HAVE_DAC1 is not set CONFIG_SAMV7_HAVE_EBI=y CONFIG_SAMV7_EMAC=y CONFIG_SAMV7_HSMCI=y @@ -228,7 +230,6 @@ CONFIG_SAMV7_HAVE_USART2=y # CONFIG_SAMV7_MCAN0 is not set # CONFIG_SAMV7_MCAN1 is not set # CONFIG_SAMV7_DAC0 is not set -# CONFIG_SAMV7_DAC1 is not set # CONFIG_SAMV7_EBI is not set CONFIG_SAMV7_EMAC0=y CONFIG_SAMV7_XDMAC=y @@ -556,6 +557,7 @@ CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_TIMERS_CS2100CP is not set @@ -630,6 +632,7 @@ CONFIG_AT25_SPIFREQUENCY=20000000 # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -742,6 +745,7 @@ CONFIG_USART1_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -971,6 +975,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1032,19 +1038,20 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=0 +CONFIG_EXAMPLES_ARCHBUTTONS=y +CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 +CONFIG_EXAMPLES_ARCHBUTTONS_MAX=0 CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 CONFIG_EXAMPLES_IRQBUTTONS_MAX=0 -CONFIG_EXAMPLES_BUTTONS_NAME0="SW0" -CONFIG_EXAMPLES_BUTTONS_NAME1="Button 1" -CONFIG_EXAMPLES_BUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_BUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_BUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_BUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_BUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="SW0" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Button 1" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" +# CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1123,6 +1130,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1209,6 +1217,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1325,6 +1334,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/same70-xplained/nsh/defconfig b/configs/same70-xplained/nsh/defconfig index 65be44eafb..183961eacf 100644 --- a/configs/same70-xplained/nsh/defconfig +++ b/configs/same70-xplained/nsh/defconfig @@ -66,6 +66,7 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set # CONFIG_ARCH_Z16 is not set @@ -195,6 +196,7 @@ CONFIG_ARCH_CHIP_SAME70Q=y # CONFIG_ARCH_CHIP_SAMV71J is not set # CONFIG_SAMV7_MCAN is not set CONFIG_SAMV7_HAVE_MCAN1=y +# CONFIG_SAMV7_DAC is not set CONFIG_SAMV7_HAVE_DAC1=y CONFIG_SAMV7_HAVE_EBI=y # CONFIG_SAMV7_EMAC is not set @@ -541,6 +543,7 @@ CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_TIMERS_CS2100CP is not set @@ -615,6 +618,7 @@ CONFIG_AT25_SPIFREQUENCY=20000000 # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -684,6 +688,7 @@ CONFIG_USART1_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -800,6 +805,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -853,19 +860,20 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=0 +CONFIG_EXAMPLES_ARCHBUTTONS=y +CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 +CONFIG_EXAMPLES_ARCHBUTTONS_MAX=0 CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 CONFIG_EXAMPLES_IRQBUTTONS_MAX=0 -CONFIG_EXAMPLES_BUTTONS_NAME0="SW0" -CONFIG_EXAMPLES_BUTTONS_NAME1="Button 1" -CONFIG_EXAMPLES_BUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_BUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_BUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_BUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_BUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="SW0" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Button 1" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" +# CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -940,6 +948,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1011,6 +1020,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1088,6 +1098,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/samv71-xult/mxtxplnd/defconfig b/configs/samv71-xult/mxtxplnd/defconfig index 4dc8dac69d..3ce521bbfb 100644 --- a/configs/samv71-xult/mxtxplnd/defconfig +++ b/configs/samv71-xult/mxtxplnd/defconfig @@ -66,6 +66,7 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set # CONFIG_ARCH_Z16 is not set @@ -195,6 +196,7 @@ CONFIG_ARCH_CHIP_SAMV71Q=y # CONFIG_ARCH_CHIP_SAMV71J is not set # CONFIG_SAMV7_MCAN is not set CONFIG_SAMV7_HAVE_MCAN1=y +# CONFIG_SAMV7_DAC is not set CONFIG_SAMV7_HAVE_DAC1=y CONFIG_SAMV7_HAVE_EBI=y # CONFIG_SAMV7_EMAC is not set @@ -542,6 +544,7 @@ CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_TIMERS_CS2100CP is not set @@ -589,6 +592,7 @@ CONFIG_LCD_MAXPOWER=1 # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set # CONFIG_LCD_UG9664HSWAG01 is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -658,6 +662,7 @@ CONFIG_AT25_SPIFREQUENCY=20000000 # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -727,6 +732,7 @@ CONFIG_USART0_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -929,6 +935,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -982,19 +990,20 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=1 +CONFIG_EXAMPLES_ARCHBUTTONS=y +CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 +CONFIG_EXAMPLES_ARCHBUTTONS_MAX=1 CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 CONFIG_EXAMPLES_IRQBUTTONS_MAX=1 -CONFIG_EXAMPLES_BUTTONS_NAME0="SW0" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW1" -CONFIG_EXAMPLES_BUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_BUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_BUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_BUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_BUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="SW0" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="SW1" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" +# CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1081,6 +1090,7 @@ CONFIG_EXAMPLES_TOUCHSCREEN_ARCHINIT=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1152,6 +1162,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1229,6 +1240,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/samv71-xult/netnsh/defconfig b/configs/samv71-xult/netnsh/defconfig index d557fa1098..a348cbc087 100644 --- a/configs/samv71-xult/netnsh/defconfig +++ b/configs/samv71-xult/netnsh/defconfig @@ -67,6 +67,7 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set # CONFIG_ARCH_Z16 is not set @@ -196,7 +197,8 @@ CONFIG_ARCH_CHIP_SAMV71Q=y # CONFIG_ARCH_CHIP_SAMV71J is not set # CONFIG_SAMV7_MCAN is not set CONFIG_SAMV7_HAVE_MCAN1=y -CONFIG_SAMV7_HAVE_DAC1=y +# CONFIG_SAMV7_DAC is not set +# CONFIG_SAMV7_HAVE_DAC1 is not set CONFIG_SAMV7_HAVE_EBI=y CONFIG_SAMV7_EMAC=y CONFIG_SAMV7_HSMCI=y @@ -229,7 +231,6 @@ CONFIG_SAMV7_HAVE_USART2=y # CONFIG_SAMV7_MCAN0 is not set # CONFIG_SAMV7_MCAN1 is not set # CONFIG_SAMV7_DAC0 is not set -# CONFIG_SAMV7_DAC1 is not set # CONFIG_SAMV7_EBI is not set CONFIG_SAMV7_EMAC0=y CONFIG_SAMV7_XDMAC=y @@ -559,6 +560,7 @@ CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_TIMERS_CS2100CP is not set @@ -633,6 +635,7 @@ CONFIG_AT25_SPIFREQUENCY=20000000 # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -745,6 +748,7 @@ CONFIG_UART3_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -974,6 +978,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1036,19 +1042,20 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=1 +CONFIG_EXAMPLES_ARCHBUTTONS=y +CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 +CONFIG_EXAMPLES_ARCHBUTTONS_MAX=1 CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 CONFIG_EXAMPLES_IRQBUTTONS_MAX=1 -CONFIG_EXAMPLES_BUTTONS_NAME0="SW0" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW1" -CONFIG_EXAMPLES_BUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_BUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_BUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_BUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_BUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="SW0" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="SW1" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" +# CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1127,6 +1134,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1213,6 +1221,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1329,6 +1338,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/samv71-xult/nsh/defconfig b/configs/samv71-xult/nsh/defconfig index d7d04be39c..b135609f71 100644 --- a/configs/samv71-xult/nsh/defconfig +++ b/configs/samv71-xult/nsh/defconfig @@ -66,6 +66,7 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set # CONFIG_ARCH_Z16 is not set @@ -195,6 +196,7 @@ CONFIG_ARCH_CHIP_SAMV71Q=y # CONFIG_ARCH_CHIP_SAMV71J is not set # CONFIG_SAMV7_MCAN is not set CONFIG_SAMV7_HAVE_MCAN1=y +# CONFIG_SAMV7_DAC is not set CONFIG_SAMV7_HAVE_DAC1=y CONFIG_SAMV7_HAVE_EBI=y # CONFIG_SAMV7_EMAC is not set @@ -544,6 +546,7 @@ CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_TIMERS_CS2100CP is not set @@ -618,6 +621,7 @@ CONFIG_AT25_SPIFREQUENCY=20000000 # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -687,6 +691,7 @@ CONFIG_UART3_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -803,6 +808,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -856,19 +863,20 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=1 +CONFIG_EXAMPLES_ARCHBUTTONS=y +CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 +CONFIG_EXAMPLES_ARCHBUTTONS_MAX=1 CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 CONFIG_EXAMPLES_IRQBUTTONS_MAX=1 -CONFIG_EXAMPLES_BUTTONS_NAME0="SW0" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW1" -CONFIG_EXAMPLES_BUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_BUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_BUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_BUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_BUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="SW0" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="SW1" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" +# CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -943,6 +951,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1014,6 +1023,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1091,6 +1101,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3210e-eval/buttons/defconfig b/configs/stm3210e-eval/buttons/defconfig index 7fd348de1a..5cbbaebc25 100644 --- a/configs/stm3210e-eval/buttons/defconfig +++ b/configs/stm3210e-eval/buttons/defconfig @@ -67,6 +67,7 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set # CONFIG_ARCH_Z16 is not set @@ -682,6 +683,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -785,6 +787,7 @@ CONFIG_USART2_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -875,6 +878,8 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -919,19 +924,20 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=7 +CONFIG_EXAMPLES_ARCHBUTTONS=y +CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 +CONFIG_EXAMPLES_ARCHBUTTONS_MAX=7 CONFIG_EXAMPLES_IRQBUTTONS_MIN=2 CONFIG_EXAMPLES_IRQBUTTONS_MAX=7 -CONFIG_EXAMPLES_BUTTONS_NAME0="WAKEUP" -CONFIG_EXAMPLES_BUTTONS_NAME1="TAMPER" -CONFIG_EXAMPLES_BUTTONS_NAME2="KEY" -CONFIG_EXAMPLES_BUTTONS_NAME3="SELECT" -CONFIG_EXAMPLES_BUTTONS_NAME4="DOWN" -CONFIG_EXAMPLES_BUTTONS_NAME5="LEFT" -CONFIG_EXAMPLES_BUTTONS_NAME6="RIGHT" -CONFIG_EXAMPLES_BUTTONS_NAME7="UP" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="WAKEUP" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="TAMPER" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="KEY" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="SELECT" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="DOWN" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="LEFT" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="RIGHT" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="UP" +# CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1000,6 +1006,7 @@ CONFIG_EXAMPLES_BUTTONS_NAME7="UP" # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1043,6 +1050,7 @@ CONFIG_EXAMPLES_BUTTONS_NAME7="UP" # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3210e-eval/pm/defconfig b/configs/stm3210e-eval/pm/defconfig index 2ebcc7d696..957c9a57a1 100644 --- a/configs/stm3210e-eval/pm/defconfig +++ b/configs/stm3210e-eval/pm/defconfig @@ -67,6 +67,7 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set # CONFIG_ARCH_Z16 is not set @@ -729,6 +730,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y # CONFIG_RTC_DATETIME is not set CONFIG_RTC_HIRES=y @@ -770,6 +772,7 @@ CONFIG_LCD_MAXPOWER=100 # CONFIG_LCD_NOKIA6100 is not set # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -888,6 +891,7 @@ CONFIG_USART2_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1077,6 +1081,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1127,6 +1133,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set @@ -1230,6 +1237,7 @@ CONFIG_EXAMPLES_NXHELLO_FONTID=6 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1300,6 +1308,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1367,6 +1376,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm32butterfly2/nsh/defconfig b/configs/stm32butterfly2/nsh/defconfig index c45cf46a3c..76318ef95c 100644 --- a/configs/stm32butterfly2/nsh/defconfig +++ b/configs/stm32butterfly2/nsh/defconfig @@ -62,7 +62,8 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set -# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set # CONFIG_ARCH_Z16 is not set @@ -460,8 +461,6 @@ CONFIG_STM32_USART2_SERIALDRIVER=y # CONFIG_STM32_SPI_DMA is not set CONFIG_STM32_HAVE_RTC_COUNTER=y # CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set -# CONFIG_STM32_MII_MCO is not set -# CONFIG_STM32_MII_EXTCLK is not set # # USB FS Host Configuration @@ -587,6 +586,7 @@ CONFIG_ARCH_HAVE_TICKLESS=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set CONFIG_CLOCK_MONOTONIC=y +CONFIG_ARCH_HAVE_TIMEKEEPING=y # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=1970 CONFIG_START_MONTH=0 @@ -706,17 +706,21 @@ CONFIG_SPI=y CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set CONFIG_SPI_CALLBACK=y -# CONFIG_SPI_BITBANG is not set -CONFIG_SPI_HWFEATURES=y -# CONFIG_SPI_CRCGENERATION is not set -CONFIG_SPI_CS_CONTROL=y +# CONFIG_SPI_HWFEATURES is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y +# CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set CONFIG_ANALOG=y @@ -765,20 +769,6 @@ CONFIG_MMCSD_SPIMODE=0 # CONFIG_MODEM is not set # CONFIG_MTD is not set # CONFIG_EEPROM is not set -# CONFIG_ETH0_PHY_NONE is not set -# CONFIG_ETH0_PHY_AM79C874 is not set -# CONFIG_ETH0_PHY_KS8721 is not set -# CONFIG_ETH0_PHY_KSZ8041 is not set -# CONFIG_ETH0_PHY_KSZ8051 is not set -# CONFIG_ETH0_PHY_KSZ8061 is not set -# CONFIG_ETH0_PHY_KSZ8081 is not set -# CONFIG_ETH0_PHY_KSZ90x1 is not set -# CONFIG_ETH0_PHY_DP83848C is not set -# CONFIG_ETH0_PHY_LAN8720 is not set -# CONFIG_ETH0_PHY_LAN8740 is not set -# CONFIG_ETH0_PHY_LAN8740A is not set -# CONFIG_ETH0_PHY_LAN8742A is not set -# CONFIG_ETH0_PHY_DM9161 is not set # CONFIG_PIPES is not set # CONFIG_PM is not set # CONFIG_POWER is not set @@ -841,6 +831,7 @@ CONFIG_USBHOST_NPREALLOC=4 CONFIG_USBHOST_HAVE_ASYNCH=y # CONFIG_USBHOST_ASYNCH is not set # CONFIG_USBHOST_HUB is not set +# CONFIG_USBHOST_COMPOSITE is not set CONFIG_USBHOST_MSC=y # CONFIG_USBHOST_CDCACM is not set CONFIG_USBHOST_HIDKBD=y @@ -856,6 +847,7 @@ CONFIG_HIDKBD_NPOLLWAITERS=2 # CONFIG_USBHOST_TRACE is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -972,6 +964,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1014,10 +1008,6 @@ CONFIG_ARCH_HAVE_TLS=y # Application Configuration # -# -# NxWidgets/NxWM -# - # # Built-In Applications # @@ -1034,9 +1024,10 @@ CONFIG_EXAMPLES_ADC=y CONFIG_EXAMPLES_ADC_DEVPATH="/dev/adc0" CONFIG_EXAMPLES_ADC_GROUPSIZE=4 CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=4 +CONFIG_EXAMPLES_ARCHBUTTONS=y +CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 +CONFIG_EXAMPLES_ARCHBUTTONS_MAX=4 +# CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1074,6 +1065,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PCA9635 is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -1116,6 +1108,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1190,6 +1183,7 @@ CONFIG_NSH_BUILTIN_APPS=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1234,10 +1228,13 @@ CONFIG_NSH_CONSOLE=y # CONFIG_NSH_ALTCONDEV is not set # CONFIG_NSH_USBKBD is not set CONFIG_NSH_ARCHINIT=y -# CONFIG_NSH_SWMAC is not set # CONFIG_NSH_LOGIN is not set # CONFIG_NSH_CONSOLE_LOGIN is not set +# +# NxWidgets/NxWM +# + # # Platform-specific Support # @@ -1261,6 +1258,7 @@ CONFIG_READLINE_MAX_BUILTINS=64 CONFIG_READLINE_MAX_EXTCMDS=64 # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set CONFIG_SYSTEM_VI=y CONFIG_SYSTEM_VI_COLS=64 diff --git a/configs/stm32butterfly2/nshnet/defconfig b/configs/stm32butterfly2/nshnet/defconfig index 9bd2ad699a..4cc7757737 100644 --- a/configs/stm32butterfly2/nshnet/defconfig +++ b/configs/stm32butterfly2/nshnet/defconfig @@ -63,6 +63,7 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set # CONFIG_ARCH_Z16 is not set @@ -912,6 +913,7 @@ CONFIG_PL2303_PRODUCTSTR="PL2303 Emulation" # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1140,6 +1142,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1183,10 +1187,6 @@ CONFIG_LIBC_NETDB=y # Application Configuration # -# -# NxWidgets/NxWM -# - # # Built-In Applications # @@ -1203,9 +1203,10 @@ CONFIG_EXAMPLES_ADC=y CONFIG_EXAMPLES_ADC_DEVPATH="/dev/adc0" CONFIG_EXAMPLES_ADC_GROUPSIZE=4 CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=4 +CONFIG_EXAMPLES_ARCHBUTTONS=y +CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 +CONFIG_EXAMPLES_ARCHBUTTONS_MAX=4 +# CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CPUHOG is not set @@ -1381,6 +1382,7 @@ CONFIG_NSH_BUILTIN_APPS=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1450,6 +1452,10 @@ CONFIG_NSH_MAX_ROUNDTRIP=20 # CONFIG_NSH_LOGIN is not set # CONFIG_NSH_CONSOLE_LOGIN is not set +# +# NxWidgets/NxWM +# + # # Platform-specific Support # diff --git a/configs/stm32butterfly2/nshusbdev/defconfig b/configs/stm32butterfly2/nshusbdev/defconfig index c9353da661..e9ca79f09d 100644 --- a/configs/stm32butterfly2/nshusbdev/defconfig +++ b/configs/stm32butterfly2/nshusbdev/defconfig @@ -62,7 +62,8 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set -# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set # CONFIG_ARCH_Z16 is not set @@ -578,6 +579,7 @@ CONFIG_ARCH_HAVE_TICKLESS=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set CONFIG_CLOCK_MONOTONIC=y +CONFIG_ARCH_HAVE_TIMEKEEPING=y # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=1970 CONFIG_START_MONTH=0 @@ -697,17 +699,21 @@ CONFIG_SPI=y CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set CONFIG_SPI_CALLBACK=y -# CONFIG_SPI_BITBANG is not set -CONFIG_SPI_HWFEATURES=y -# CONFIG_SPI_CRCGENERATION is not set -CONFIG_SPI_CS_CONTROL=y +# CONFIG_SPI_HWFEATURES is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y +# CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set CONFIG_ANALOG=y @@ -850,6 +856,7 @@ CONFIG_PL2303_PRODUCTSTR="PL2303 Emulation" # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -966,6 +973,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1008,10 +1017,6 @@ CONFIG_ARCH_HAVE_TLS=y # Application Configuration # -# -# NxWidgets/NxWM -# - # # Built-In Applications # @@ -1028,9 +1033,10 @@ CONFIG_EXAMPLES_ADC=y CONFIG_EXAMPLES_ADC_DEVPATH="/dev/adc0" CONFIG_EXAMPLES_ADC_GROUPSIZE=4 CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=4 +CONFIG_EXAMPLES_ARCHBUTTONS=y +CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 +CONFIG_EXAMPLES_ARCHBUTTONS_MAX=4 +# CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1065,6 +1071,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PCA9635 is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -1108,6 +1115,7 @@ CONFIG_EXAMPLES_USBTERM=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1182,6 +1190,7 @@ CONFIG_NSH_BUILTIN_APPS=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1229,6 +1238,10 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_NSH_LOGIN is not set # CONFIG_NSH_CONSOLE_LOGIN is not set +# +# NxWidgets/NxWM +# + # # Platform-specific Support # @@ -1252,6 +1265,7 @@ CONFIG_READLINE_MAX_BUILTINS=64 CONFIG_READLINE_MAX_EXTCMDS=64 # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set CONFIG_SYSTEM_VI=y CONFIG_SYSTEM_VI_COLS=64 diff --git a/configs/stm32butterfly2/nshusbhost/defconfig b/configs/stm32butterfly2/nshusbhost/defconfig index bbaf4d92bd..76318ef95c 100644 --- a/configs/stm32butterfly2/nshusbhost/defconfig +++ b/configs/stm32butterfly2/nshusbhost/defconfig @@ -62,7 +62,8 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set -# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set # CONFIG_ARCH_Z16 is not set @@ -585,6 +586,7 @@ CONFIG_ARCH_HAVE_TICKLESS=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set CONFIG_CLOCK_MONOTONIC=y +CONFIG_ARCH_HAVE_TIMEKEEPING=y # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=1970 CONFIG_START_MONTH=0 @@ -704,17 +706,21 @@ CONFIG_SPI=y CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set CONFIG_SPI_CALLBACK=y -# CONFIG_SPI_BITBANG is not set -CONFIG_SPI_HWFEATURES=y -# CONFIG_SPI_CRCGENERATION is not set -CONFIG_SPI_CS_CONTROL=y +# CONFIG_SPI_HWFEATURES is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y +# CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set CONFIG_ANALOG=y @@ -825,6 +831,7 @@ CONFIG_USBHOST_NPREALLOC=4 CONFIG_USBHOST_HAVE_ASYNCH=y # CONFIG_USBHOST_ASYNCH is not set # CONFIG_USBHOST_HUB is not set +# CONFIG_USBHOST_COMPOSITE is not set CONFIG_USBHOST_MSC=y # CONFIG_USBHOST_CDCACM is not set CONFIG_USBHOST_HIDKBD=y @@ -840,6 +847,7 @@ CONFIG_HIDKBD_NPOLLWAITERS=2 # CONFIG_USBHOST_TRACE is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -956,6 +964,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -998,10 +1008,6 @@ CONFIG_ARCH_HAVE_TLS=y # Application Configuration # -# -# NxWidgets/NxWM -# - # # Built-In Applications # @@ -1018,9 +1024,10 @@ CONFIG_EXAMPLES_ADC=y CONFIG_EXAMPLES_ADC_DEVPATH="/dev/adc0" CONFIG_EXAMPLES_ADC_GROUPSIZE=4 CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=4 +CONFIG_EXAMPLES_ARCHBUTTONS=y +CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 +CONFIG_EXAMPLES_ARCHBUTTONS_MAX=4 +# CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1058,6 +1065,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PCA9635 is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -1100,6 +1108,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1174,6 +1183,7 @@ CONFIG_NSH_BUILTIN_APPS=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1221,6 +1231,10 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_NSH_LOGIN is not set # CONFIG_NSH_CONSOLE_LOGIN is not set +# +# NxWidgets/NxWM +# + # # Platform-specific Support # @@ -1244,6 +1258,7 @@ CONFIG_READLINE_MAX_BUILTINS=64 CONFIG_READLINE_MAX_EXTCMDS=64 # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set CONFIG_SYSTEM_VI=y CONFIG_SYSTEM_VI_COLS=64 diff --git a/configs/stm32l476vg-disco/nsh/defconfig b/configs/stm32l476vg-disco/nsh/defconfig index 0e77bb76a6..25cfb5102c 100644 --- a/configs/stm32l476vg-disco/nsh/defconfig +++ b/configs/stm32l476vg-disco/nsh/defconfig @@ -63,6 +63,7 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set # CONFIG_ARCH_Z16 is not set @@ -243,8 +244,6 @@ CONFIG_STM32L4_PWR=y # CONFIG_STM32L4_USART1 is not set CONFIG_STM32L4_USART2=y # CONFIG_STM32L4_USART3 is not set -# CONFIG_STM32L4_UART4 is not set -# CONFIG_STM32L4_UART5 is not set # CONFIG_STM32L4_I2C1 is not set # CONFIG_STM32L4_I2C2 is not set # CONFIG_STM32L4_I2C3 is not set @@ -293,6 +292,9 @@ CONFIG_STM32L4_SAI1PLL=y # # CONFIG_STM32L4_ONESHOT is not set # CONFIG_STM32L4_FREERUN is not set +CONFIG_STM32L4_HAVE_USART3=y +# CONFIG_STM32L4_HAVE_USART4 is not set +# CONFIG_STM32L4_HAVE_USART5 is not set # # U[S]ART Configuration @@ -363,6 +365,7 @@ CONFIG_RAM_SIZE=98304 # # CONFIG_ARCH_BOARD_NUCLEO_L476RG is not set CONFIG_ARCH_BOARD_STM32L476VG_DISCO=y +# CONFIG_ARCH_BOARD_STM32L476_MDK is not set # CONFIG_ARCH_BOARD_CUSTOM is not set CONFIG_ARCH_BOARD="stm32l476vg-disco" @@ -534,6 +537,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y CONFIG_RTC_DATETIME=y CONFIG_RTC_ALARM=y @@ -592,6 +596,7 @@ CONFIG_MTD_PARTITION=y # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set CONFIG_MTD_N25QXXX=y CONFIG_N25QXXX_QSPIMODE=0 @@ -664,6 +669,7 @@ CONFIG_USART2_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -779,6 +785,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -844,19 +852,20 @@ CONFIG_EXAMPLES_ALARM_PRIORITY=100 CONFIG_EXAMPLES_ALARM_STACKSIZE=2048 CONFIG_EXAMPLES_ALARM_DEVPATH="/dev/rtc0" CONFIG_EXAMPLES_ALARM_SIGNO=1 -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_MIN=0 -CONFIG_EXAMPLES_BUTTONS_MAX=4 +CONFIG_EXAMPLES_ARCHBUTTONS=y +CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 +CONFIG_EXAMPLES_ARCHBUTTONS_MAX=4 CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 CONFIG_EXAMPLES_IRQBUTTONS_MAX=4 -CONFIG_EXAMPLES_BUTTONS_NAME0="Center" -CONFIG_EXAMPLES_BUTTONS_NAME1="Left" -CONFIG_EXAMPLES_BUTTONS_NAME2="Down" -CONFIG_EXAMPLES_BUTTONS_NAME3="Right" -CONFIG_EXAMPLES_BUTTONS_NAME4="Up" -CONFIG_EXAMPLES_BUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_BUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="Center" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Left" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Down" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Right" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Up" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" +CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" +# CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -941,6 +950,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1011,6 +1021,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1089,6 +1100,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set -- GitLab From 1ea22b680d7ed5a87412128103e9ec88c74e7d23 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 21 Oct 2016 13:23:28 -0600 Subject: [PATCH 166/734] Xtensa: Add timer dispatch logic --- arch/xtensa/include/esp32/irq.h | 162 ++++++++++---------- arch/xtensa/src/common/xtensa_inthandlers.S | 22 ++- 2 files changed, 93 insertions(+), 91 deletions(-) diff --git a/arch/xtensa/include/esp32/irq.h b/arch/xtensa/include/esp32/irq.h index 1dadb66b89..b394e8d6ba 100644 --- a/arch/xtensa/include/esp32/irq.h +++ b/arch/xtensa/include/esp32/irq.h @@ -69,6 +69,10 @@ * is still to be determined what will be done for the the ESP32. */ +#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */ +#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */ +#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */ + /* Interrupt Matrix * * The Interrupt Matrix embedded in the ESP32 independently allocates @@ -98,94 +102,94 @@ /* PRO_INTR_STATUS_REG_0 / APP_INTR_STATUS_REG_0 */ -#define XTENSA_IRQ_SREG0 0 -#define XTENSA_IRQ_MAC 0 /* INTR_STATUS_REG_0, bit 0 */ -#define XTENSA_IRQ_MAC_NMI 1 /* INTR_STATUS_REG_0, bit 1 */ -#define XTENSA_IRQ_BB 2 /* INTR_STATUS_REG_0, bit 2 */ -#define XTENSA_IRQ_BB_MAC 3 /* INTR_STATUS_REG_0, bit 3 */ -#define XTENSA_IRQ_BT_BB 4 /* INTR_STATUS_REG_0, bit 4 */ -#define XTENSA_IRQ_BT_BB_NMI 5 /* INTR_STATUS_REG_0, bit 5 */ -#define XTENSA_IRQ_RWBT_IRQ 6 /* INTR_STATUS_REG_0, bit 6 */ -#define XTENSA_IRQ_RWBLE_IRQ 7 /* INTR_STATUS_REG_0, bit 7 */ -#define XTENSA_IRQ_RWBT_NMI 8 /* INTR_STATUS_REG_0, bit 8 */ -#define XTENSA_IRQ_RWBLE_NMI 9 /* INTR_STATUS_REG_0, bit 9 */ - -#define XTENSA_IRQ_SLC0 10 /* INTR_STATUS_REG_0, bit 10 */ -#define XTENSA_IRQ_SLC1 11 /* INTR_STATUS_REG_0, bit 11 */ -#define XTENSA_IRQ_UHCI0 12 /* INTR_STATUS_REG_0, bit 12 */ -#define XTENSA_IRQ_UHCI1 13 /* INTR_STATUS_REG_0, bit 13 */ -#define XTENSA_IRQ_TG_T0_LEVEL 14 /* INTR_STATUS_REG_0, bit 14 */ -#define XTENSA_IRQ_TG_T1_LEVEL 15 /* INTR_STATUS_REG_0, bit 15 */ -#define XTENSA_IRQ_TG_WDT_LEVEL 16 /* INTR_STATUS_REG_0, bit 16 */ -#define XTENSA_IRQ_TG_LACT_LEVEL 17 /* INTR_STATUS_REG_0, bit 17 */ -#define XTENSA_IRQ_TG1_T0_LEVEL 18 /* INTR_STATUS_REG_0, bit 18 */ -#define XTENSA_IRQ_TG1_T1_LEVEL 19 /* INTR_STATUS_REG_0, bit 19 */ - -#define XTENSA_IRQ_TG1_WDT_LEVEL 20 /* INTR_STATUS_REG_0, bit 20 */ -#define XTENSA_IRQ_G1_LACT_LEVEL 21 /* INTR_STATUS_REG_0, bit 21 */ -#define XTENSA_IRQ_CPU_GPIO 22 /* INTR_STATUS_REG_0, bit 22 */ -#define XTENSA_IRQ_CPU_NMI 23 /* INTR_STATUS_REG_0, bit 23 */ -#define XTENSA_IRQ_CPU_CPU0 24 /* INTR_STATUS_REG_0, bit 24 */ -#define XTENSA_IRQ_CPU_CPU1 25 /* INTR_STATUS_REG_0, bit 25 */ -#define XTENSA_IRQ_CPU_CPU2 26 /* INTR_STATUS_REG_0, bit 26 */ -#define XTENSA_IRQ_CPU_CPU3 27 /* INTR_STATUS_REG_0, bit 27 */ -#define XTENSA_IRQ_SPI0 28 /* INTR_STATUS_REG_0, bit 28 */ -#define XTENSA_IRQ_SPI1 29 /* INTR_STATUS_REG_0, bit 29 */ - -#define XTENSA_IRQ_SPI2 30 /* INTR_STATUS_REG_0, bit 30 */ -#define XTENSA_IRQ_SPI3 31 /* INTR_STATUS_REG_0, bit 31 */ +#define XTENSA_IRQ_SREG0 3 +#define XTENSA_IRQ_MAC 3 /* INTR_STATUS_REG_0, bit 0 */ +#define XTENSA_IRQ_MAC_NMI 4 /* INTR_STATUS_REG_0, bit 1 */ +#define XTENSA_IRQ_BB 5 /* INTR_STATUS_REG_0, bit 2 */ +#define XTENSA_IRQ_BB_MAC 6 /* INTR_STATUS_REG_0, bit 3 */ +#define XTENSA_IRQ_BT_BB 7 /* INTR_STATUS_REG_0, bit 4 */ +#define XTENSA_IRQ_BT_BB_NMI 8 /* INTR_STATUS_REG_0, bit 5 */ +#define XTENSA_IRQ_RWBT_IRQ 9 /* INTR_STATUS_REG_0, bit 6 */ +#define XTENSA_IRQ_RWBLE_IRQ 10 /* INTR_STATUS_REG_0, bit 7 */ +#define XTENSA_IRQ_RWBT_NMI 11 /* INTR_STATUS_REG_0, bit 8 */ +#define XTENSA_IRQ_RWBLE_NMI 12 /* INTR_STATUS_REG_0, bit 9 */ + +#define XTENSA_IRQ_SLC0 13 /* INTR_STATUS_REG_0, bit 10 */ +#define XTENSA_IRQ_SLC1 14 /* INTR_STATUS_REG_0, bit 11 */ +#define XTENSA_IRQ_UHCI0 15 /* INTR_STATUS_REG_0, bit 12 */ +#define XTENSA_IRQ_UHCI1 16 /* INTR_STATUS_REG_0, bit 13 */ +#define XTENSA_IRQ_TG_T0_LEVEL 17 /* INTR_STATUS_REG_0, bit 14 */ +#define XTENSA_IRQ_TG_T1_LEVEL 18 /* INTR_STATUS_REG_0, bit 15 */ +#define XTENSA_IRQ_TG_WDT_LEVEL 19 /* INTR_STATUS_REG_0, bit 16 */ +#define XTENSA_IRQ_TG_LACT_LEVEL 20 /* INTR_STATUS_REG_0, bit 17 */ +#define XTENSA_IRQ_TG1_T0_LEVEL 21 /* INTR_STATUS_REG_0, bit 18 */ +#define XTENSA_IRQ_TG1_T1_LEVEL 22 /* INTR_STATUS_REG_0, bit 19 */ + +#define XTENSA_IRQ_TG1_WDT_LEVEL 23 /* INTR_STATUS_REG_0, bit 20 */ +#define XTENSA_IRQ_G1_LACT_LEVEL 24 /* INTR_STATUS_REG_0, bit 21 */ +#define XTENSA_IRQ_CPU_GPIO 25 /* INTR_STATUS_REG_0, bit 22 */ +#define XTENSA_IRQ_CPU_NMI 26 /* INTR_STATUS_REG_0, bit 23 */ +#define XTENSA_IRQ_CPU_CPU0 27 /* INTR_STATUS_REG_0, bit 24 */ +#define XTENSA_IRQ_CPU_CPU1 28 /* INTR_STATUS_REG_0, bit 25 */ +#define XTENSA_IRQ_CPU_CPU2 29 /* INTR_STATUS_REG_0, bit 26 */ +#define XTENSA_IRQ_CPU_CPU3 30 /* INTR_STATUS_REG_0, bit 27 */ +#define XTENSA_IRQ_SPI0 31 /* INTR_STATUS_REG_0, bit 28 */ +#define XTENSA_IRQ_SPI1 32 /* INTR_STATUS_REG_0, bit 29 */ + +#define XTENSA_IRQ_SPI2 33 /* INTR_STATUS_REG_0, bit 30 */ +#define XTENSA_IRQ_SPI3 34 /* INTR_STATUS_REG_0, bit 31 */ /* PRO_INTR_STATUS_REG_1 / APP_INTR_STATUS_REG_1 */ -#define XTENSA_IRQ_SREG1 32 -#define XTENSA_IRQ_I2S0 32 /* INTR_STATUS_REG_1, bit 0 */ -#define XTENSA_IRQ_I2S1 33 /* INTR_STATUS_REG_1, bit 1 */ -#define XTENSA_IRQ_UART 34 /* INTR_STATUS_REG_1, bit 2 */ -#define XTENSA_IRQ_UART1 35 /* INTR_STATUS_REG_1, bit 3 */ -#define XTENSA_IRQ_UART2 36 /* INTR_STATUS_REG_1, bit 4 */ -#define XTENSA_IRQ_SDIO_HOST 37 /* INTR_STATUS_REG_1, bit 5 */ -#define XTENSA_IRQ_EMAC 38 /* INTR_STATUS_REG_1, bit 6 */ -#define XTENSA_IRQ_PWM0 39 /* INTR_STATUS_REG_1, bit 7 */ -#define XTENSA_IRQ_PWM1 40 /* INTR_STATUS_REG_1, bit 8 */ -#define XTENSA_IRQ_PWM2 41 /* INTR_STATUS_REG_1, bit 9 */ - -#define XTENSA_IRQ_PWM3 42 /* INTR_STATUS_REG_1, bit 10 */ -#define XTENSA_IRQ_LEDC 43 /* INTR_STATUS_REG_1, bit 11 */ -#define XTENSA_IRQ_EFUSE 44 /* INTR_STATUS_REG_1, bit 12 */ -#define XTENSA_IRQ_CAN 45 /* INTR_STATUS_REG_1, bit 13 */ -#define XTENSA_IRQ_RTC_CORE 46 /* INTR_STATUS_REG_1, bit 14 */ -#define XTENSA_IRQ_RMT 47 /* INTR_STATUS_REG_1, bit 15 */ -#define XTENSA_IRQ_PCNT 48 /* INTR_STATUS_REG_1, bit 16 */ -#define XTENSA_IRQ_I2C_EXT0 49 /* INTR_STATUS_REG_1, bit 17 */ -#define XTENSA_IRQ_I2C_EXT1 50 /* INTR_STATUS_REG_1, bit 18 */ -#define XTENSA_IRQ_RSA 51 /* INTR_STATUS_REG_1, bit 19 */ - -#define XTENSA_IRQ_SPI1_DMA 52 /* INTR_STATUS_REG_1, bit 20 */ -#define XTENSA_IRQ_SPI2_DMA 53 /* INTR_STATUS_REG_1, bit 21 */ -#define XTENSA_IRQ_SPI3_DMA 54 /* INTR_STATUS_REG_1, bit 22 */ -#define XTENSA_IRQ_WDG 55 /* INTR_STATUS_REG_1, bit 23 */ -#define XTENSA_IRQ_TIMER1 56 /* INTR_STATUS_REG_1, bit 24 */ -#define XTENSA_IRQ_TIMER2 57 /* INTR_STATUS_REG_1, bit 25 */ -#define XTENSA_IRQ_TG_T0_EDGE 58 /* INTR_STATUS_REG_1, bit 26 */ -#define XTENSA_IRQ_TG_T1_EDGE 59 /* INTR_STATUS_REG_1, bit 27 */ -#define XTENSA_IRQ_TG_WDT_EDGE 60 /* INTR_STATUS_REG_1, bit 28 */ -#define XTENSA_IRQ_TG_LACT_EDGE 61 /* INTR_STATUS_REG_1, bit 29 */ - -#define XTENSA_IRQ_TG1_T0_EDGE 62 /* INTR_STATUS_REG_1, bit 30 */ -#define XTENSA_IRQ_TG1_T1_EDGE 63 /* INTR_STATUS_REG_1, bit 31 */ +#define XTENSA_IRQ_SREG1 35 +#define XTENSA_IRQ_I2S0 35 /* INTR_STATUS_REG_1, bit 0 */ +#define XTENSA_IRQ_I2S1 36 /* INTR_STATUS_REG_1, bit 1 */ +#define XTENSA_IRQ_UART 37 /* INTR_STATUS_REG_1, bit 2 */ +#define XTENSA_IRQ_UART1 38 /* INTR_STATUS_REG_1, bit 3 */ +#define XTENSA_IRQ_UART2 39 /* INTR_STATUS_REG_1, bit 4 */ +#define XTENSA_IRQ_SDIO_HOST 40 /* INTR_STATUS_REG_1, bit 5 */ +#define XTENSA_IRQ_EMAC 41 /* INTR_STATUS_REG_1, bit 6 */ +#define XTENSA_IRQ_PWM0 42 /* INTR_STATUS_REG_1, bit 7 */ +#define XTENSA_IRQ_PWM1 43 /* INTR_STATUS_REG_1, bit 8 */ +#define XTENSA_IRQ_PWM2 44 /* INTR_STATUS_REG_1, bit 9 */ + +#define XTENSA_IRQ_PWM3 45 /* INTR_STATUS_REG_1, bit 10 */ +#define XTENSA_IRQ_LEDC 46 /* INTR_STATUS_REG_1, bit 11 */ +#define XTENSA_IRQ_EFUSE 47 /* INTR_STATUS_REG_1, bit 12 */ +#define XTENSA_IRQ_CAN 48 /* INTR_STATUS_REG_1, bit 13 */ +#define XTENSA_IRQ_RTC_CORE 49 /* INTR_STATUS_REG_1, bit 14 */ +#define XTENSA_IRQ_RMT 50 /* INTR_STATUS_REG_1, bit 15 */ +#define XTENSA_IRQ_PCNT 51 /* INTR_STATUS_REG_1, bit 16 */ +#define XTENSA_IRQ_I2C_EXT0 52 /* INTR_STATUS_REG_1, bit 17 */ +#define XTENSA_IRQ_I2C_EXT1 53 /* INTR_STATUS_REG_1, bit 18 */ +#define XTENSA_IRQ_RSA 54 /* INTR_STATUS_REG_1, bit 19 */ + +#define XTENSA_IRQ_SPI1_DMA 55 /* INTR_STATUS_REG_1, bit 20 */ +#define XTENSA_IRQ_SPI2_DMA 56 /* INTR_STATUS_REG_1, bit 21 */ +#define XTENSA_IRQ_SPI3_DMA 57 /* INTR_STATUS_REG_1, bit 22 */ +#define XTENSA_IRQ_WDG 58 /* INTR_STATUS_REG_1, bit 23 */ +#define XTENSA_IRQ_TIMER1 59 /* INTR_STATUS_REG_1, bit 24 */ +#define XTENSA_IRQ_TIMER2 60 /* INTR_STATUS_REG_1, bit 25 */ +#define XTENSA_IRQ_TG_T0_EDGE 61 /* INTR_STATUS_REG_1, bit 26 */ +#define XTENSA_IRQ_TG_T1_EDGE 62 /* INTR_STATUS_REG_1, bit 27 */ +#define XTENSA_IRQ_TG_WDT_EDGE 63 /* INTR_STATUS_REG_1, bit 28 */ +#define XTENSA_IRQ_TG_LACT_EDGE 64 /* INTR_STATUS_REG_1, bit 29 */ + +#define XTENSA_IRQ_TG1_T0_EDGE 65 /* INTR_STATUS_REG_1, bit 30 */ +#define XTENSA_IRQ_TG1_T1_EDGE 66 /* INTR_STATUS_REG_1, bit 31 */ /* PRO_INTR_STATUS_REG_2 / APP_INTR_STATUS_REG_2 */ -#define XTENSA_IRQ_SREG0 64 -#define XTENSA_IRQ_TG1_WDT_EDGE 64 /* INTR_STATUS_REG_2, bit 0 */ -#define XTENSA_IRQ_TG1_LACT_EDGE 65 /* INTR_STATUS_REG_2, bit 1 */ -#define XTENSA_IRQ_MMU_IA 66 /* INTR_STATUS_REG_2, bit 2 */ -#define XTENSA_IRQ_MPU_IA 67 /* INTR_STATUS_REG_2, bit 3 */ -#define XTENSA_IRQ_CACHE_IA 68 /* INTR_STATUS_REG_2, bit 4 */ +#define XTENSA_IRQ_SREG2 67 +#define XTENSA_IRQ_TG1_WDT_EDGE 67 /* INTR_STATUS_REG_2, bit 0 */ +#define XTENSA_IRQ_TG1_LACT_EDGE 68 /* INTR_STATUS_REG_2, bit 1 */ +#define XTENSA_IRQ_MMU_IA 69 /* INTR_STATUS_REG_2, bit 2 */ +#define XTENSA_IRQ_MPU_IA 70 /* INTR_STATUS_REG_2, bit 3 */ +#define XTENSA_IRQ_CACHE_IA 71 /* INTR_STATUS_REG_2, bit 4 */ /* Total number of interrupts */ -#define NR_IRQS 69 +#define NR_IRQS 72 /**************************************************************************** * Public Types diff --git a/arch/xtensa/src/common/xtensa_inthandlers.S b/arch/xtensa/src/common/xtensa_inthandlers.S index fbd3e6b08c..cb18aec95b 100644 --- a/arch/xtensa/src/common/xtensa_inthandlers.S +++ b/arch/xtensa/src/common/xtensa_inthandlers.S @@ -60,6 +60,7 @@ #include #include +#include #include "xtensa_specregs.h" #include "xtensa_macros.h" @@ -209,20 +210,17 @@ 7: .ifeq XT_TIMER_INTPRI - \level -.L_xt_user_int_timer_&level&: + /* Interrupt handler for the RTOS tick timer if at this level. - We'll be reading the interrupt state again after this call - so no need to preserve any registers except a6 (vpri_mask). - */ + * We'll be reading the interrupt state again after this call + * so no need to preserve any registers except a6 (vpri_mask). + */ -#ifdef CONFIG_XTENSA_CALL0_ABI - mov a12, a6 - call0 XT_RTOS_TIMER_INT - mov a2, a12 -#else - mov a2, a6 - call4 XT_RTOS_TIMER_INT -#endif + mov a12, a6 /* Preserve a6 */ + movi a2, XTENSA_IRQ_TIMER&level& /* Arg 1: IRQ number */ + mov a3, sp /* Arg 2: Top of stack = register save area */ + call0 xtensa_irq_dispatch /* Call xtensa_int_decode */ + mov a6, a12 /* Preserve a6 */ .endif #ifdef CONFIG_XTENSA_USE_SWPRI -- GitLab From 31da3e30a98ecdfe1ba4c11336bb0f788bbabbfd Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Fri, 21 Oct 2016 13:27:04 -0600 Subject: [PATCH 167/734] Add support to PWM on STM32F103-Minimum board --- configs/stm32f103-minimum/include/board.h | 8 + configs/stm32f103-minimum/pwm/Make.defs | 113 ++ configs/stm32f103-minimum/pwm/defconfig | 1158 +++++++++++++++++ configs/stm32f103-minimum/pwm/setenv.sh | 100 ++ configs/stm32f103-minimum/src/Makefile | 4 + configs/stm32f103-minimum/src/stm32_pwm.c | 143 ++ .../stm32f103-minimum/src/stm32f103_minimum.h | 5 + 7 files changed, 1531 insertions(+) create mode 100644 configs/stm32f103-minimum/pwm/Make.defs create mode 100644 configs/stm32f103-minimum/pwm/defconfig create mode 100644 configs/stm32f103-minimum/pwm/setenv.sh create mode 100644 configs/stm32f103-minimum/src/stm32_pwm.c diff --git a/configs/stm32f103-minimum/include/board.h b/configs/stm32f103-minimum/include/board.h index c2a17aff37..8e983ae351 100644 --- a/configs/stm32f103-minimum/include/board.h +++ b/configs/stm32f103-minimum/include/board.h @@ -178,6 +178,14 @@ #define LED_ASSERTION 6 /* LED1 + LED2 */ #define LED_PANIC 7 /* LED1 / LED2 blinking */ +/* PWM + * + * The STM32F103-Minimum has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM3 CH3 on PB0. + * + * Note: we don't need redefine GPIO_TIM3_CH3OUT because PB0 is not remap pin. + */ + /************************************************************************************ * Public Data ************************************************************************************/ diff --git a/configs/stm32f103-minimum/pwm/Make.defs b/configs/stm32f103-minimum/pwm/Make.defs new file mode 100644 index 0000000000..8d3d478305 --- /dev/null +++ b/configs/stm32f103-minimum/pwm/Make.defs @@ -0,0 +1,113 @@ +############################################################################ +# configs/stm32f103-minimum/nsh/Make.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/stm32f103-minimum/pwm/defconfig b/configs/stm32f103-minimum/pwm/defconfig new file mode 100644 index 0000000000..27fa9d85b2 --- /dev/null +++ b/configs/stm32f103-minimum/pwm/defconfig @@ -0,0 +1,1158 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_DEFAULT_SMALL=y +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +CONFIG_ARCH_HAVE_HEAPCHECK=y +# CONFIG_HEAP_COLORATION is not set +# CONFIG_DEBUG_SYMBOLS is not set +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +CONFIG_ARCH_CHIP_STM32=y +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +CONFIG_ARCH_CORTEXM3=y +# CONFIG_ARCH_CORTEXM4 is not set +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="stm32" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARMV7M_LAZYFPU is not set +# CONFIG_ARCH_HAVE_FPU is not set +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y +CONFIG_ARMV7M_HAVE_STACKCHECK=y +# CONFIG_ARMV7M_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set +CONFIG_SERIAL_TERMIOS=y + +# +# STM32 Configuration Options +# +# CONFIG_ARCH_CHIP_STM32L151C6 is not set +# CONFIG_ARCH_CHIP_STM32L151C8 is not set +# CONFIG_ARCH_CHIP_STM32L151CB is not set +# CONFIG_ARCH_CHIP_STM32L151R6 is not set +# CONFIG_ARCH_CHIP_STM32L151R8 is not set +# CONFIG_ARCH_CHIP_STM32L151RB is not set +# CONFIG_ARCH_CHIP_STM32L151V6 is not set +# CONFIG_ARCH_CHIP_STM32L151V8 is not set +# CONFIG_ARCH_CHIP_STM32L151VB is not set +# CONFIG_ARCH_CHIP_STM32L152C6 is not set +# CONFIG_ARCH_CHIP_STM32L152C8 is not set +# CONFIG_ARCH_CHIP_STM32L152CB is not set +# CONFIG_ARCH_CHIP_STM32L152R6 is not set +# CONFIG_ARCH_CHIP_STM32L152R8 is not set +# CONFIG_ARCH_CHIP_STM32L152RB is not set +# CONFIG_ARCH_CHIP_STM32L152V6 is not set +# CONFIG_ARCH_CHIP_STM32L152V8 is not set +# CONFIG_ARCH_CHIP_STM32L152VB is not set +# CONFIG_ARCH_CHIP_STM32L162ZD is not set +# CONFIG_ARCH_CHIP_STM32L162VE is not set +# CONFIG_ARCH_CHIP_STM32F100C8 is not set +# CONFIG_ARCH_CHIP_STM32F100CB is not set +# CONFIG_ARCH_CHIP_STM32F100R8 is not set +# CONFIG_ARCH_CHIP_STM32F100RB is not set +# CONFIG_ARCH_CHIP_STM32F100RC is not set +# CONFIG_ARCH_CHIP_STM32F100RD is not set +# CONFIG_ARCH_CHIP_STM32F100RE is not set +# CONFIG_ARCH_CHIP_STM32F100V8 is not set +# CONFIG_ARCH_CHIP_STM32F100VB is not set +# CONFIG_ARCH_CHIP_STM32F100VC is not set +# CONFIG_ARCH_CHIP_STM32F100VD is not set +# CONFIG_ARCH_CHIP_STM32F100VE is not set +# CONFIG_ARCH_CHIP_STM32F102CB is not set +# CONFIG_ARCH_CHIP_STM32F103T8 is not set +# CONFIG_ARCH_CHIP_STM32F103TB is not set +# CONFIG_ARCH_CHIP_STM32F103C4 is not set +CONFIG_ARCH_CHIP_STM32F103C8=y +# CONFIG_ARCH_CHIP_STM32F103CB is not set +# CONFIG_ARCH_CHIP_STM32F103R8 is not set +# CONFIG_ARCH_CHIP_STM32F103RB is not set +# CONFIG_ARCH_CHIP_STM32F103RC is not set +# CONFIG_ARCH_CHIP_STM32F103RD is not set +# CONFIG_ARCH_CHIP_STM32F103RE is not set +# CONFIG_ARCH_CHIP_STM32F103RG is not set +# CONFIG_ARCH_CHIP_STM32F103V8 is not set +# CONFIG_ARCH_CHIP_STM32F103VB is not set +# CONFIG_ARCH_CHIP_STM32F103VC is not set +# CONFIG_ARCH_CHIP_STM32F103VE is not set +# CONFIG_ARCH_CHIP_STM32F103ZE is not set +# CONFIG_ARCH_CHIP_STM32F105VB is not set +# CONFIG_ARCH_CHIP_STM32F105RB is not set +# CONFIG_ARCH_CHIP_STM32F107VC is not set +# CONFIG_ARCH_CHIP_STM32F205RG is not set +# CONFIG_ARCH_CHIP_STM32F207IG is not set +# CONFIG_ARCH_CHIP_STM32F207ZE is not set +# CONFIG_ARCH_CHIP_STM32F302K6 is not set +# CONFIG_ARCH_CHIP_STM32F302K8 is not set +# CONFIG_ARCH_CHIP_STM32F302CB is not set +# CONFIG_ARCH_CHIP_STM32F302CC is not set +# CONFIG_ARCH_CHIP_STM32F302RB is not set +# CONFIG_ARCH_CHIP_STM32F302RC is not set +# CONFIG_ARCH_CHIP_STM32F302VB is not set +# CONFIG_ARCH_CHIP_STM32F302VC is not set +# CONFIG_ARCH_CHIP_STM32F303K6 is not set +# CONFIG_ARCH_CHIP_STM32F303K8 is not set +# CONFIG_ARCH_CHIP_STM32F303C6 is not set +# CONFIG_ARCH_CHIP_STM32F303C8 is not set +# CONFIG_ARCH_CHIP_STM32F303CB is not set +# CONFIG_ARCH_CHIP_STM32F303CC is not set +# CONFIG_ARCH_CHIP_STM32F303RB is not set +# CONFIG_ARCH_CHIP_STM32F303RC is not set +# CONFIG_ARCH_CHIP_STM32F303RD is not set +# CONFIG_ARCH_CHIP_STM32F303RE is not set +# CONFIG_ARCH_CHIP_STM32F303VB is not set +# CONFIG_ARCH_CHIP_STM32F303VC is not set +# CONFIG_ARCH_CHIP_STM32F372C8 is not set +# CONFIG_ARCH_CHIP_STM32F372R8 is not set +# CONFIG_ARCH_CHIP_STM32F372V8 is not set +# CONFIG_ARCH_CHIP_STM32F372CB is not set +# CONFIG_ARCH_CHIP_STM32F372RB is not set +# CONFIG_ARCH_CHIP_STM32F372VB is not set +# CONFIG_ARCH_CHIP_STM32F372CC is not set +# CONFIG_ARCH_CHIP_STM32F372RC is not set +# CONFIG_ARCH_CHIP_STM32F372VC is not set +# CONFIG_ARCH_CHIP_STM32F373C8 is not set +# CONFIG_ARCH_CHIP_STM32F373R8 is not set +# CONFIG_ARCH_CHIP_STM32F373V8 is not set +# CONFIG_ARCH_CHIP_STM32F373CB is not set +# CONFIG_ARCH_CHIP_STM32F373RB is not set +# CONFIG_ARCH_CHIP_STM32F373VB is not set +# CONFIG_ARCH_CHIP_STM32F373CC is not set +# CONFIG_ARCH_CHIP_STM32F373RC is not set +# CONFIG_ARCH_CHIP_STM32F373VC is not set +# CONFIG_ARCH_CHIP_STM32F401RE is not set +# CONFIG_ARCH_CHIP_STM32F411RE is not set +# CONFIG_ARCH_CHIP_STM32F411VE is not set +# CONFIG_ARCH_CHIP_STM32F405RG is not set +# CONFIG_ARCH_CHIP_STM32F405VG is not set +# CONFIG_ARCH_CHIP_STM32F405ZG is not set +# CONFIG_ARCH_CHIP_STM32F407VE is not set +# CONFIG_ARCH_CHIP_STM32F407VG is not set +# CONFIG_ARCH_CHIP_STM32F407ZE is not set +# CONFIG_ARCH_CHIP_STM32F407ZG is not set +# CONFIG_ARCH_CHIP_STM32F407IE is not set +# CONFIG_ARCH_CHIP_STM32F407IG is not set +# CONFIG_ARCH_CHIP_STM32F427V is not set +# CONFIG_ARCH_CHIP_STM32F427Z is not set +# CONFIG_ARCH_CHIP_STM32F427I is not set +# CONFIG_ARCH_CHIP_STM32F429V is not set +# CONFIG_ARCH_CHIP_STM32F429Z is not set +# CONFIG_ARCH_CHIP_STM32F429I is not set +# CONFIG_ARCH_CHIP_STM32F429B is not set +# CONFIG_ARCH_CHIP_STM32F429N is not set +# CONFIG_ARCH_CHIP_STM32F446M is not set +# CONFIG_ARCH_CHIP_STM32F446R is not set +# CONFIG_ARCH_CHIP_STM32F446V is not set +# CONFIG_ARCH_CHIP_STM32F446Z is not set +# CONFIG_ARCH_CHIP_STM32F469A is not set +# CONFIG_ARCH_CHIP_STM32F469I is not set +# CONFIG_ARCH_CHIP_STM32F469B is not set +# CONFIG_ARCH_CHIP_STM32F469N is not set +CONFIG_STM32_FLASH_CONFIG_DEFAULT=y +# CONFIG_STM32_FLASH_CONFIG_4 is not set +# CONFIG_STM32_FLASH_CONFIG_6 is not set +# CONFIG_STM32_FLASH_CONFIG_8 is not set +# CONFIG_STM32_FLASH_CONFIG_B is not set +# CONFIG_STM32_FLASH_CONFIG_C is not set +# CONFIG_STM32_FLASH_CONFIG_D is not set +# CONFIG_STM32_FLASH_CONFIG_E is not set +# CONFIG_STM32_FLASH_CONFIG_F is not set +# CONFIG_STM32_FLASH_CONFIG_G is not set +# CONFIG_STM32_FLASH_CONFIG_I is not set +# CONFIG_STM32_STM32L15XX is not set +# CONFIG_STM32_ENERGYLITE is not set +CONFIG_STM32_STM32F10XX=y +# CONFIG_STM32_VALUELINE is not set +# CONFIG_STM32_CONNECTIVITYLINE is not set +CONFIG_STM32_PERFORMANCELINE=y +# CONFIG_STM32_USBACCESSLINE is not set +# CONFIG_STM32_HIGHDENSITY is not set +CONFIG_STM32_MEDIUMDENSITY=y +# CONFIG_STM32_LOWDENSITY is not set +# CONFIG_STM32_STM32F20XX is not set +# CONFIG_STM32_STM32F205 is not set +# CONFIG_STM32_STM32F207 is not set +# CONFIG_STM32_STM32F30XX is not set +# CONFIG_STM32_STM32F302 is not set +# CONFIG_STM32_STM32F303 is not set +# CONFIG_STM32_STM32F37XX is not set +# CONFIG_STM32_STM32F40XX is not set +# CONFIG_STM32_STM32F401 is not set +# CONFIG_STM32_STM32F411 is not set +# CONFIG_STM32_STM32F405 is not set +# CONFIG_STM32_STM32F407 is not set +# CONFIG_STM32_STM32F427 is not set +# CONFIG_STM32_STM32F429 is not set +# CONFIG_STM32_STM32F446 is not set +# CONFIG_STM32_STM32F469 is not set +# CONFIG_STM32_DFU is not set + +# +# STM32 Peripheral Support +# +# CONFIG_STM32_HAVE_CCM is not set +CONFIG_STM32_HAVE_USBDEV=y +# CONFIG_STM32_HAVE_OTGFS is not set +# CONFIG_STM32_HAVE_FSMC is not set +# CONFIG_STM32_HAVE_LTDC is not set +CONFIG_STM32_HAVE_USART3=y +CONFIG_STM32_HAVE_UART4=y +CONFIG_STM32_HAVE_UART5=y +# CONFIG_STM32_HAVE_USART6 is not set +# CONFIG_STM32_HAVE_UART7 is not set +# CONFIG_STM32_HAVE_UART8 is not set +CONFIG_STM32_HAVE_TIM1=y +# CONFIG_STM32_HAVE_TIM2 is not set +CONFIG_STM32_HAVE_TIM3=y +CONFIG_STM32_HAVE_TIM4=y +CONFIG_STM32_HAVE_TIM5=y +CONFIG_STM32_HAVE_TIM6=y +CONFIG_STM32_HAVE_TIM7=y +CONFIG_STM32_HAVE_TIM8=y +# CONFIG_STM32_HAVE_TIM9 is not set +# CONFIG_STM32_HAVE_TIM10 is not set +# CONFIG_STM32_HAVE_TIM11 is not set +# CONFIG_STM32_HAVE_TIM12 is not set +# CONFIG_STM32_HAVE_TIM13 is not set +# CONFIG_STM32_HAVE_TIM14 is not set +# CONFIG_STM32_HAVE_TIM15 is not set +# CONFIG_STM32_HAVE_TIM16 is not set +# CONFIG_STM32_HAVE_TIM17 is not set +CONFIG_STM32_HAVE_ADC2=y +CONFIG_STM32_HAVE_ADC3=y +# CONFIG_STM32_HAVE_ADC4 is not set +# CONFIG_STM32_HAVE_ADC1_DMA is not set +# CONFIG_STM32_HAVE_ADC2_DMA is not set +# CONFIG_STM32_HAVE_ADC3_DMA is not set +# CONFIG_STM32_HAVE_ADC4_DMA is not set +CONFIG_STM32_HAVE_CAN1=y +# CONFIG_STM32_HAVE_CAN2 is not set +# CONFIG_STM32_HAVE_DAC1 is not set +# CONFIG_STM32_HAVE_DAC2 is not set +# CONFIG_STM32_HAVE_RNG is not set +# CONFIG_STM32_HAVE_ETHMAC is not set +CONFIG_STM32_HAVE_I2C2=y +# CONFIG_STM32_HAVE_I2C3 is not set +CONFIG_STM32_HAVE_SPI2=y +CONFIG_STM32_HAVE_SPI3=y +# CONFIG_STM32_HAVE_SPI4 is not set +# CONFIG_STM32_HAVE_SPI5 is not set +# CONFIG_STM32_HAVE_SPI6 is not set +# CONFIG_STM32_HAVE_SAIPLL is not set +# CONFIG_STM32_HAVE_I2SPLL is not set +# CONFIG_STM32_ADC1 is not set +# CONFIG_STM32_ADC2 is not set +# CONFIG_STM32_ADC3 is not set +# CONFIG_STM32_BKP is not set +# CONFIG_STM32_CAN1 is not set +# CONFIG_STM32_CRC is not set +# CONFIG_STM32_DMA1 is not set +# CONFIG_STM32_DMA2 is not set +# CONFIG_STM32_I2C1 is not set +# CONFIG_STM32_I2C2 is not set +# CONFIG_STM32_PWR is not set +# CONFIG_STM32_SDIO is not set +# CONFIG_STM32_SPI1 is not set +# CONFIG_STM32_SPI2 is not set +# CONFIG_STM32_SPI3 is not set +# CONFIG_STM32_TIM1 is not set +# CONFIG_STM32_TIM2 is not set +CONFIG_STM32_TIM3=y +# CONFIG_STM32_TIM4 is not set +# CONFIG_STM32_TIM5 is not set +# CONFIG_STM32_TIM6 is not set +# CONFIG_STM32_TIM7 is not set +# CONFIG_STM32_TIM8 is not set +CONFIG_STM32_USART1=y +# CONFIG_STM32_USART2 is not set +# CONFIG_STM32_USART3 is not set +# CONFIG_STM32_UART4 is not set +# CONFIG_STM32_UART5 is not set +# CONFIG_STM32_USB is not set +# CONFIG_STM32_IWDG is not set +# CONFIG_STM32_WWDG is not set +# CONFIG_STM32_NOEXT_VECTORS is not set + +# +# Alternate Pin Mapping +# +CONFIG_STM32_TIM3_NO_REMAP=y +# CONFIG_STM32_TIM3_FULL_REMAP is not set +# CONFIG_STM32_TIM3_PARTIAL_REMAP is not set +# CONFIG_STM32_USART1_REMAP is not set +# CONFIG_STM32_JTAG_DISABLE is not set +CONFIG_STM32_JTAG_FULL_ENABLE=y +# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set +# CONFIG_STM32_JTAG_SW_ENABLE is not set +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +# CONFIG_STM32_FORCEPOWER is not set +# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set + +# +# Timer Configuration +# +# CONFIG_STM32_ONESHOT is not set +# CONFIG_STM32_FREERUN is not set +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_TIM3_MODE=0 +CONFIG_STM32_TIM3_CHANNEL=3 +CONFIG_STM32_TIM3_CHMODE=0 +# CONFIG_STM32_PWM_MULTICHAN is not set +# CONFIG_STM32_TIM1_CAP is not set +# CONFIG_STM32_TIM3_CAP is not set +# CONFIG_STM32_TIM4_CAP is not set +# CONFIG_STM32_TIM5_CAP is not set +# CONFIG_STM32_TIM8_CAP is not set +CONFIG_STM32_USART=y +CONFIG_STM32_SERIALDRIVER=y + +# +# U[S]ART Configuration +# + +# +# U[S]ART Device Configuration +# +CONFIG_STM32_USART1_SERIALDRIVER=y +# CONFIG_STM32_USART1_1WIREDRIVER is not set +# CONFIG_USART1_RS485 is not set + +# +# Serial Driver Configuration +# +# CONFIG_SERIAL_DISABLE_REORDERING is not set +# CONFIG_STM32_FLOWCONTROL_BROKEN is not set +# CONFIG_STM32_USART_BREAKS is not set +# CONFIG_STM32_USART_SINGLEWIRE is not set +CONFIG_STM32_HAVE_RTC_COUNTER=y +# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set + +# +# USB FS Host Configuration +# + +# +# USB HS Host Configuration +# + +# +# USB Host Debug Configuration +# + +# +# USB Device Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=5483 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_SIZE=20480 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +# CONFIG_ARCH_BOARD_STM32_TINY is not set +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="stm32f103-minimum" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +# CONFIG_ARCH_BUTTONS is not set +CONFIG_ARCH_HAVE_IRQBUTTONS=y + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_RESET is not set +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_ADCTEST is not set +CONFIG_BOARDCTL_PWMTEST=y +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set + +# +# RTOS Features +# +# CONFIG_DISABLE_OS_API is not set + +# +# Clocks and Timers +# +CONFIG_ARCH_HAVE_TICKLESS=y +# CONFIG_SCHED_TICKLESS is not set +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +CONFIG_ARCH_HAVE_TIMEKEEPING=y +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2011 +CONFIG_START_MONTH=7 +CONFIG_START_DAY=5 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=0 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +# CONFIG_DISABLE_POLL is not set +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +CONFIG_ARCH_HAVE_PWM_PULSECOUNT=y +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +CONFIG_PWM=y +# CONFIG_PWM_PULSECOUNT is not set +CONFIG_ARCH_HAVE_I2CRESET=y +# CONFIG_I2C is not set +# CONFIG_SPI is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +CONFIG_USART1_SERIALDRIVER=y +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_SERIAL_NPOLLWAITERS=2 +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +CONFIG_USART1_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# USART1 Configuration +# +CONFIG_USART1_RXBUFSIZE=256 +CONFIG_USART1_TXBUFSIZE=256 +CONFIG_USART1_BAUD=115200 +CONFIG_USART1_BITS=8 +CONFIG_USART1_PARITY=0 +CONFIG_USART1_2STOP=0 +# CONFIG_USART1_IFLOWCONTROL is not set +# CONFIG_USART1_OFLOWCONTROL is not set +# CONFIG_USART1_DMA is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +# CONFIG_FS_READABLE is not set +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +CONFIG_SYMTAB_ORDEREDBYNAME=y + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_LIBC_LONG_LONG is not set +# CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set +# CONFIG_LIBC_NETDB is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +CONFIG_EXAMPLES_PWM=y +CONFIG_EXAMPLES_PWM_DEVPATH="/dev/pwm0" +CONFIG_EXAMPLES_PWM_FREQUENCY=100 +CONFIG_EXAMPLES_PWM_DURATION=5 +CONFIG_EXAMPLES_PWM_DUTYPCT=50 +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CHAT is not set +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=80 +CONFIG_NSH_DISABLE_SEMICOLON=y +# CONFIG_NSH_CMDPARMS is not set +CONFIG_NSH_MAXARGUMENTS=6 +# CONFIG_NSH_ARGCAT is not set +CONFIG_NSH_NESTDEPTH=3 +CONFIG_NSH_DISABLEBG=y +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +CONFIG_NSH_DISABLE_ADDROUTE=y +CONFIG_NSH_DISABLE_BASENAME=y +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +CONFIG_NSH_DISABLE_DF=y +CONFIG_NSH_DISABLE_DELROUTE=y +CONFIG_NSH_DISABLE_DIRNAME=y +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +CONFIG_NSH_DISABLE_IFCONFIG=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_KILL is not set +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +CONFIG_NSH_DISABLE_TIME=y +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +CONFIG_NSH_DISABLE_UNAME=y +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Configure Command Options +# +CONFIG_NSH_CODECS_BUFSIZE=128 +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_NSH_FILEIOSIZE=1024 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +CONFIG_NSH_DISABLE_ITEF=y +CONFIG_NSH_DISABLE_LOOPS=y + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm32f103-minimum/pwm/setenv.sh b/configs/stm32f103-minimum/pwm/setenv.sh new file mode 100644 index 0000000000..73dfab5a4d --- /dev/null +++ b/configs/stm32f103-minimum/pwm/setenv.sh @@ -0,0 +1,100 @@ +#!/bin/bash +# configs//stm32f103-minimum/nsh/setenv.sh +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" +# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" +# You can this free toolchain here https://launchpad.net/gcc-arm-embedded +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" + +# This is the path to the location where I installed the devkitARM toolchain +# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/ +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/configs/stm32f103-minimum/src/Makefile b/configs/stm32f103-minimum/src/Makefile index 5596fb6e43..3259d5ab12 100644 --- a/configs/stm32f103-minimum/src/Makefile +++ b/configs/stm32f103-minimum/src/Makefile @@ -53,6 +53,10 @@ else CSRCS += stm32_userleds.c endif +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + ifeq ($(CONFIG_AUDIO_TONE),y) CSRCS += stm32_tone.c endif diff --git a/configs/stm32f103-minimum/src/stm32_pwm.c b/configs/stm32f103-minimum/src/stm32_pwm.c new file mode 100644 index 0000000000..3238a9077b --- /dev/null +++ b/configs/stm32f103-minimum/src/stm32_pwm.c @@ -0,0 +1,143 @@ +/************************************************************************************ + * configs/stm32f103-minimum/src/stm32_pwm.c + * + * Copyright (C) 2013, 2015, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "up_arch.h" +#include "stm32_pwm.h" +#include "stm32f103_minimum.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Configuration *******************************************************************/ +/* PWM + * + * The stm32f103-minimum has no real on-board PWM devices, but the board can be + * configured to output a pulse train using TIM4 CH2. This pin is used by FSMC + * is connect to CN5 just for this purpose: + * + * PB0 ADC12_IN8/TIM3_CH3 + * + */ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM3 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM3_PWM +# undef HAVE_PWM +#endif + +#if CONFIG_STM32_TIM3_CHANNEL != STM32F103MINIMUM_PWMCHANNEL +# undef HAVE_PWM +#endif + +#ifdef HAVE_PWM + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: board_pwm_setup + * + * Description: + * All STM32 architectures must provide the following interface to work with + * examples/pwm. + * + ************************************************************************************/ + +int board_pwm_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM32F103MINIMUM_PWMTIMER); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#endif /* HAVE_PWM */ diff --git a/configs/stm32f103-minimum/src/stm32f103_minimum.h b/configs/stm32f103-minimum/src/stm32f103_minimum.h index ec66bb5898..7b0ae80221 100644 --- a/configs/stm32f103-minimum/src/stm32f103_minimum.h +++ b/configs/stm32f103-minimum/src/stm32f103_minimum.h @@ -92,6 +92,11 @@ #define STM32_LCD_RS (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN2) +/* PWN Configuration */ + +#define STM32F103MINIMUM_PWMTIMER 3 +#define STM32F103MINIMUM_PWMCHANNEL 3 + /* USB Soft Connect Pullup: PC.13 */ #define GPIO_USB_PULLUP (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ -- GitLab From 1e40e03c7f73fbac93663099d436fe65fec25338 Mon Sep 17 00:00:00 2001 From: Ken Pettit Date: Fri, 21 Oct 2016 17:01:40 -0600 Subject: [PATCH 168/734] Minor RISC-V update --- arch/risc-v/Kconfig | 7 +++---- arch/risc-v/src/nr5m100/nr5_csr.S | 2 +- arch/risc-v/src/nr5m100/nr5_head.S | 4 ---- configs/nr5m100-nexys4/include/board.h | 2 -- configs/nr5m100-nexys4/scripts/nr5m1xx.cfg | 2 +- 5 files changed, 5 insertions(+), 12 deletions(-) diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig index 65ed34459f..645ad2c88e 100644 --- a/arch/risc-v/Kconfig +++ b/arch/risc-v/Kconfig @@ -10,10 +10,9 @@ choice prompt "RISC-V chip selection" default ARCH_CHIP_NR5M100 -config ARCH_CHIP_NR5M100 - bool "NEXT NanoRisc5 M100" +config ARCH_CHIP_NR5 + bool "NEXT NanoRisc5" select ARCH_RV32IM - default ARCH_CHIP_NR5 ---help--- NEXT RISC-V NR5Mxx architectures (RISC-V RV32IM cores). @@ -48,7 +47,7 @@ config NR5_MPU if ARCH_RV32IM source arch/risc-v/src/rv32im/Kconfig endif -if ARCH_CHIP_NR5M100 +if ARCH_CHIP_NR5 source arch/risc-v/src/nr5m100/Kconfig endif diff --git a/arch/risc-v/src/nr5m100/nr5_csr.S b/arch/risc-v/src/nr5m100/nr5_csr.S index d586270e09..13133005a0 100644 --- a/arch/risc-v/src/nr5m100/nr5_csr.S +++ b/arch/risc-v/src/nr5m100/nr5_csr.S @@ -1,5 +1,5 @@ /************************************************************************************ - * arch/risc-v/src/nr5m100/nr5_csr.c + * arch/risc-v/src/nr5m100/nr5_csr.S * * Copyright (C) 2016 Ken Pettit. All rights reserved. * Author: Ken Pettit diff --git a/arch/risc-v/src/nr5m100/nr5_head.S b/arch/risc-v/src/nr5m100/nr5_head.S index aa6eb23264..cc0d215632 100644 --- a/arch/risc-v/src/nr5m100/nr5_head.S +++ b/arch/risc-v/src/nr5m100/nr5_head.S @@ -175,10 +175,6 @@ __start: #endif bltu t0, t1, 1b - /* Call the nr5_init_array routine to initialize C variables */ - - //call __nr5_init_array - lw a0, 0(sp) # a0 = argc addi a1, sp, _RISCV_SZPTR/8 # a1 = argv li a2, 0 # a2 = envp = NULL diff --git a/configs/nr5m100-nexys4/include/board.h b/configs/nr5m100-nexys4/include/board.h index 366c3007d1..0d2dd772f3 100644 --- a/configs/nr5m100-nexys4/include/board.h +++ b/configs/nr5m100-nexys4/include/board.h @@ -64,8 +64,6 @@ #define NR5_HCLK_FREQUENCY 100000000ul #define NR5_SCLK_FREQUENCY 100000000ul -//#define STM32_SYSCLK_FREQUENCY 168000000ul - /* Timer Frequencies are the same as the HCLK frequency */ diff --git a/configs/nr5m100-nexys4/scripts/nr5m1xx.cfg b/configs/nr5m100-nexys4/scripts/nr5m1xx.cfg index 9218333b82..9cff1d5aa8 100644 --- a/configs/nr5m100-nexys4/scripts/nr5m1xx.cfg +++ b/configs/nr5m100-nexys4/scripts/nr5m1xx.cfg @@ -52,7 +52,7 @@ if { [info exists ENDIAN] } { if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { - set _CPUTAPID 0x1f40092d + set _CPUTAPID 0x17a1092d } jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x5 -irmask 0x1f -expected-id $_CPUTAPID -- GitLab From c08cb7ddea84164dd4a22536be05f1e4f7049130 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 22 Oct 2016 08:18:00 -0600 Subject: [PATCH 169/734] Implement ctype.h functions as inline if possible. cctype can then properly select namespace. --- include/ctype.h | 159 ++++++++++++++++++++++++++++++++++++++------- include/cxx/cctype | 42 ++++++------ 2 files changed, 155 insertions(+), 46 deletions(-) diff --git a/include/ctype.h b/include/ctype.h index d3d62b53fd..49cc47f030 100644 --- a/include/ctype.h +++ b/include/ctype.h @@ -1,7 +1,7 @@ /**************************************************************************** * include/ctype.h * - * Copyright (C) 2007-2009, 2011, 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2011, 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -45,6 +45,8 @@ * Included Files ****************************************************************************/ +#include + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -59,9 +61,17 @@ * ****************************************************************************/ -#define isspace(c) \ - ((c) == ' ' || (c) == '\t' || (c) == '\n' || \ - (c) == '\r' || (c) == '\f' || c== '\v') +#if defined(CONFIG_HAVE_INLINE) || defined(__cplusplus) +static inline int isspace(int c) +{ + return c == ' ' || c == '\t' || c == '\n' || c == '\r' || + c == '\f' || c == '\v'; +} +#else +# define isspace(c) \ + ((c) == ' ' || (c) == '\t' || (c) == '\n' || (c) == '\r' || \ + (c) == '\f' || c== '\v') +#endif /**************************************************************************** * Name: isascii @@ -72,7 +82,14 @@ * ****************************************************************************/ -#define isascii(c) ((c) >= 0 && (c) <= 0x7f) +#if defined(CONFIG_HAVE_INLINE) || defined(__cplusplus) +static inline int isascii(int c) +{ + return c >= 0 && c <= 0x7f; +} +#else +# define isascii(c) ((c) >= 0 && (c) <= 0x7f) +#endif /**************************************************************************** * Name: isprint @@ -82,7 +99,14 @@ * ****************************************************************************/ -#define isprint(c) ((c) >= 0x20 && (c) < 0x7f) +#if defined(CONFIG_HAVE_INLINE) || defined(__cplusplus) +static inline int isprint(int c) +{ + return c >= 0x20 && c < 0x7f; +} +#else +# define isprint(c) ((c) >= 0x20 && (c) < 0x7f) +#endif /**************************************************************************** * Name: isgraph @@ -92,7 +116,14 @@ * ****************************************************************************/ -#define isgraph(c) ((c) > 0x20 && (c) < 0x7f) +#if defined(CONFIG_HAVE_INLINE) || defined(__cplusplus) +static inline int isgraph(int c) +{ + return c > 0x20 && c < 0x7f; +} +#else +# define isgraph(c) ((c) > 0x20 && (c) < 0x7f) +#endif /**************************************************************************** * Name: iscntrl @@ -102,7 +133,14 @@ * ****************************************************************************/ -#define iscntrl(c) (!isprint(c)) +#if defined(CONFIG_HAVE_INLINE) || defined(__cplusplus) +static inline int iscntrl(int c) +{ + return !isprint(c); +} +#else +# define iscntrl(c) (!isprint(c)) +#endif /**************************************************************************** * Name: islower @@ -112,7 +150,14 @@ * ****************************************************************************/ -#define islower(c) ((c) >= 'a' && (c) <= 'z') +#if defined(CONFIG_HAVE_INLINE) || defined(__cplusplus) +static inline int islower(int c) +{ + return c >= 'a' && c <= 'z'; +} +#else +# define islower(c) ((c) >= 'a' && (c) <= 'z') +#endif /**************************************************************************** * Name: isupper @@ -122,7 +167,14 @@ * ****************************************************************************/ -#define isupper(c) ((c) >= 'A' && (c) <= 'Z') +#if defined(CONFIG_HAVE_INLINE) || defined(__cplusplus) +static inline int isupper(int c) +{ + return c >= 'A' && c <= 'Z'; +} +#else +# define isupper(c) ((c) >= 'A' && (c) <= 'Z') +#endif /**************************************************************************** * Name: isalpha @@ -132,17 +184,31 @@ * ****************************************************************************/ -#define isalpha(c) (islower(c) || isupper(c)) +#if defined(CONFIG_HAVE_INLINE) || defined(__cplusplus) +static inline int isalpha(int c) +{ + return islower(c) || isupper(c); +} +#else +# define isalpha(c) (islower(c) || isupper(c)) +#endif /**************************************************************************** * Name: isblank * * Description: - * Checks for blank characters (space or tab) + * Checks for blank characters (space or tab). C++11 * ****************************************************************************/ -#define isblank(c) (isspace(c) || (c) == '\t') +#if defined(CONFIG_HAVE_INLINE) || defined(__cplusplus) +static inline int isblank(int c) +{ + return c == ' ' || c == '\t'; +} +#else +# define isblank(c) ((c) == ' ' || (c) == '\t') +#endif /**************************************************************************** * Name: isdigit @@ -152,7 +218,14 @@ * ****************************************************************************/ -#define isdigit(c) ((c) >= '0' && (c) <= '9') +#if defined(CONFIG_HAVE_INLINE) || defined(__cplusplus) +static inline int isdigit(int c) +{ + return c >= '0' && c <= '9'; +} +#else +# define isdigit(c) ((c) >= '0' && (c) <= '9') +#endif /**************************************************************************** * Name: isalnum @@ -162,7 +235,14 @@ * ****************************************************************************/ -#define isalnum(c) (isalpha(c) || isdigit(c)) +#if defined(CONFIG_HAVE_INLINE) || defined(__cplusplus) +static inline int isalnum(int c) +{ + return isalpha(c) || isdigit(c); +} +#else +# define isalnum(c) (isalpha(c) || isdigit(c)) +#endif /**************************************************************************** * Name: ispunct @@ -173,7 +253,14 @@ * ****************************************************************************/ -#define ispunct(c) (isgraph(c) && !isalnum(c)) +#if defined(CONFIG_HAVE_INLINE) || defined(__cplusplus) +static inline int ispunct(int c) +{ + return isgraph(c) && !isalnum(c); +} +#else +# define ispunct(c) (isgraph(c) && !isalnum(c)) +#endif /**************************************************************************** * Name: isxdigit @@ -183,10 +270,19 @@ * ****************************************************************************/ -#define isxdigit(c) \ - (((c) >= '0' && (c) <= '9') || \ - ((c) >= 'a' && (c) <= 'f') || \ - ((c) >= 'A' && (c) <= 'F')) +#if defined(CONFIG_HAVE_INLINE) || defined(__cplusplus) +static inline int isxdigit(int c) +{ + return (c >= '0' && c <= '9') || + (c >= 'a' && c <= 'f') || + (c >= 'A' && c <= 'F'); +} +#else +# define isxdigit(c) \ + (((c) >= '0' && (c) <= '9') || \ + ((c) >= 'a' && (c) <= 'f') || \ + ((c) >= 'A' && (c) <= 'F')) +#endif /**************************************************************************** * Name: toupper @@ -196,8 +292,15 @@ * ****************************************************************************/ -#define toupper(c) \ - (((c) >= 'a' && (c) <= 'z') ? ((c) - 'a' + 'A') : (c)) +#if defined(CONFIG_HAVE_INLINE) || defined(__cplusplus) +static inline int toupper(int c) +{ + return (c >= 'a' && c <= 'z') ? c - 'a' + 'A' : c; +} +#else +# define toupper(c) \ + (((c) >= 'a' && (c) <= 'z') ? ((c) - 'a' + 'A') : (c)) +#endif /**************************************************************************** * Name: tolower @@ -207,8 +310,16 @@ * ****************************************************************************/ -#define tolower(c) \ - (((c) >= 'A' && (c) <= 'Z') ? ((c) - 'A' + 'a') : (c)) +#if defined(CONFIG_HAVE_INLINE) || defined(__cplusplus) +static inline int tolower(int c) +{ + return (c >= 'A' && c <= 'Z') ? (c - 'A' + 'a') : c; +} +#else +# define tolower(c) \ + (((c) >= 'A' && (c) <= 'Z') ? ((c) - 'A' + 'a') : (c)) +# define +#endif /**************************************************************************** * Public Type Definitions diff --git a/include/cxx/cctype b/include/cxx/cctype index 36b62ca8c5..52c4c86ba7 100644 --- a/include/cxx/cctype +++ b/include/cxx/cctype @@ -1,7 +1,7 @@ //*************************************************************************** // include/cxx/cctype // -// Copyright (C) 2009 Gregory Nutt. All rights reserved. +// Copyright (C) 2009, 2016 Gregory Nutt. All rights reserved. // Author: Gregory Nutt // // Redistribution and use in source and binary forms, with or without @@ -42,29 +42,27 @@ #include -// Remove macros in favor of builtin implementations - -#if !defined(CONFIG_UCLIBCXX) - -#undef isalnum -#undef isalpha -#undef iscntrl -#undef isdigit -#undef isgraph -#undef islower -#undef isprint -#undef ispunct -#undef isspace -#undef isblank -#undef isupper -#undef isxdigit -#undef tolower -#undef toupper - -#endif - //*************************************************************************** // Namespace //*************************************************************************** +namespace std +{ + using ::isspace; + using ::isascii; + using ::isprint; + using ::isgraph; + using ::iscntrl; + using ::islower; + using ::isupper; + using ::isalpha; + using ::isblank; + using ::isdigit; + using ::isalnum; + using ::ispunct; + using ::isxdigit; + using ::toupper; + using ::tolower; +} + #endif // __INCLUDE_CXX_CCTYPE -- GitLab From 764ef72641a9872d313d04660fb0b296ccba6af8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 22 Oct 2016 09:03:43 -0600 Subject: [PATCH 170/734] Xtensa: Restore XCHAL_ naming convenction --- arch/xtensa/include/esp32/core-isa.h | 923 ++++++++++---------- arch/xtensa/include/irq.h | 2 +- arch/xtensa/src/common/xtensa_context.S | 6 +- arch/xtensa/src/common/xtensa_dumpstate.c | 2 +- arch/xtensa/src/common/xtensa_inthandlers.S | 32 +- arch/xtensa/src/common/xtensa_intvectors.S | 10 +- arch/xtensa/src/common/xtensa_irq.S | 8 +- arch/xtensa/src/common/xtensa_timer.h | 22 +- 8 files changed, 503 insertions(+), 502 deletions(-) diff --git a/arch/xtensa/include/esp32/core-isa.h b/arch/xtensa/include/esp32/core-isa.h index 76a5b4ba46..1465a3a459 100644 --- a/arch/xtensa/include/esp32/core-isa.h +++ b/arch/xtensa/include/esp32/core-isa.h @@ -31,427 +31,428 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Note: Macros of the form XTENSA_HAVE_*** have a value of 1 if the option +/* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option * is configured, and a value of 0 otherwise. These macros are always * defined. */ /* ISA **********************************************************************/ -#define XTENSA_HAVE_BE 0 /* big-endian byte ordering */ -#define XTENSA_HAVE_WINDOWED 1 /* windowed registers option */ -#define XTENSA_NUM_AREGS 64 /* num of physical addr regs */ -#define XTENSA_NUM_AREGS_LOG2 6 /* log2(XTENSA_NUM_AREGS) */ -#define XTENSA_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ -#define XTENSA_HAVE_DEBUG 1 /* debug option */ -#define XTENSA_HAVE_DENSITY 1 /* 16-bit instructions */ -#define XTENSA_HAVE_LOOPS 1 /* zero-overhead loops */ -#define XTENSA_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */ -#define XTENSA_HAVE_NSA 1 /* NSA/NSAU instructions */ -#define XTENSA_HAVE_MINMAX 1 /* MIN/MAX instructions */ -#define XTENSA_HAVE_SEXT 1 /* SEXT instruction */ -#define XTENSA_HAVE_DEPBITS 0 /* DEPBITS instruction */ -#define XTENSA_HAVE_CLAMPS 1 /* CLAMPS instruction */ -#define XTENSA_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ -#define XTENSA_HAVE_MUL32 1 /* MULL instruction */ -#define XTENSA_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ -#define XTENSA_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ -#define XTENSA_HAVE_L32R 1 /* L32R instruction */ -#define XTENSA_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ -#define XTENSA_HAVE_CONST16 0 /* CONST16 instruction */ -#define XTENSA_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ -#define XTENSA_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ -#define XTENSA_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ -#define XTENSA_HAVE_CALL4AND12 1 /* (obsolete option) */ -#define XTENSA_HAVE_ABS 1 /* ABS instruction */ -/*#define XTENSA_HAVE_POPC 0*/ /* POPC instruction */ -/*#define XTENSA_HAVE_CRC 0*/ /* CRC instruction */ -#define XTENSA_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ -#define XTENSA_HAVE_S32C1I 1 /* S32C1I instruction */ -#define XTENSA_HAVE_SPECULATION 0 /* speculation */ -#define XTENSA_HAVE_FULL_RESET 1 /* all regs/state reset */ -#define XTENSA_NUM_CONTEXTS 1 /* */ -#define XTENSA_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */ -#define XTENSA_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ -#define XTENSA_HAVE_PRID 1 /* processor ID register */ -#define XTENSA_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ -#define XTENSA_HAVE_MX 0 /* MX core (Tensilica internal) */ -#define XTENSA_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ -#define XTENSA_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ -#define XTENSA_HAVE_PSO 0 /* Power Shut-Off */ -#define XTENSA_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ -#define XTENSA_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ -#define XTENSA_HAVE_THREADPTR 1 /* THREADPTR register */ -#define XTENSA_HAVE_BOOLEANS 1 /* boolean registers */ -#define XTENSA_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ -#define XTENSA_CP_MAXCFG 8 /* max allowed cp id plus one */ -#define XTENSA_HAVE_MAC16 1 /* MAC16 package */ - -#define XTENSA_HAVE_FUSION 0 /* Fusion*/ -#define XTENSA_HAVE_FUSION_FP 0 /* Fusion FP option */ -#define XTENSA_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ -#define XTENSA_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ -#define XTENSA_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ -#define XTENSA_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ -#define XTENSA_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ -#define XTENSA_HAVE_FUSION_AVS 0 /* Fusion AVS option */ -#define XTENSA_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ -#define XTENSA_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ -#define XTENSA_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ -#define XTENSA_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ -#define XTENSA_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ -#define XTENSA_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ -#define XTENSA_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ -#define XTENSA_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ -#define XTENSA_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ -#define XTENSA_HAVE_HIFI2EP 0 /* HiFi2EP */ -#define XTENSA_HAVE_HIFI_MINI 0 - -#define XTENSA_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */ -#define XTENSA_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ -#define XTENSA_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */ -#define XTENSA_HAVE_FP 1 /* single prec floating point */ -#define XTENSA_HAVE_FP_DIV 1 /* FP with DIV instructions */ -#define XTENSA_HAVE_FP_RECIP 1 /* FP with RECIP instructions */ -#define XTENSA_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ -#define XTENSA_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */ -#define XTENSA_HAVE_DFP 0 /* double precision FP pkg */ -#define XTENSA_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ -#define XTENSA_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ -#define XTENSA_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ -#define XTENSA_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ -#define XTENSA_HAVE_DFP_ACCEL 1 /* double precision FP acceleration pkg */ -#define XTENSA_HAVE_DFP_accel XTENSA_HAVE_DFP_ACCEL /* for backward compatibility */ - -#define XTENSA_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */ -#define XTENSA_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ -#define XTENSA_HAVE_VECTRA1 0 /* Vectra I pkg */ -#define XTENSA_HAVE_VECTRALX 0 /* Vectra LX pkg */ -#define XTENSA_HAVE_PDX4 0 /* PDX4 */ -#define XTENSA_HAVE_CONNXD2 0 /* ConnX D2 pkg */ -#define XTENSA_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ -#define XTENSA_HAVE_BBE16 0 /* ConnX BBE16 pkg */ -#define XTENSA_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ -#define XTENSA_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ -#define XTENSA_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ -#define XTENSA_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ -#define XTENSA_HAVE_BSP3 0 /* ConnX BSP3 pkg */ -#define XTENSA_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ -#define XTENSA_HAVE_SSP16 0 /* ConnX SSP16 pkg */ -#define XTENSA_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ -#define XTENSA_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ -#define XTENSA_HAVE_BBP16 0 /* ConnX BBP16 pkg */ -#define XTENSA_HAVE_FLIX3 0 /* basic 3-way FLIX option */ -#define XTENSA_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */ -#define XTENSA_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ +/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ +#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ +#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ +#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 1 /* MAC16 package */ + +#define XCHAL_HAVE_FUSION 0 /* Fusion*/ +#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ +#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ +#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ +#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ +#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ +#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ +#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ +#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ +#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ +#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ +#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ +#define XCHAL_HAVE_HIFI_MINI 0 + +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */ +#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_FP 1 /* single prec floating point */ +#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */ +#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */ +#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ +#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */ +#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ +#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ +#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ +#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ +#define XCHAL_HAVE_DFP_ACCEL 1 /* double precision FP acceleration pkg */ +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ + +#define XCHAL_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */ +#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ +#define XCHAL_HAVE_PDX4 0 /* PDX4 */ +#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ +#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ +#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */ +#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ /* Misc. ********************************************************************/ -#define XTENSA_NUM_LOADSTORE_UNITS 1 /* load/store units */ -#define XTENSA_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */ -#define XTENSA_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ -#define XTENSA_DATA_WIDTH 4 /* data width in bytes */ -#define XTENSA_DATA_PIPE_DELAY 2 /* d-side pipeline delay - * (1 = 5-stage, 2 = 7-stage) */ -#define XTENSA_CLOCK_GATING_GLOBAL 1 /* global clock gating */ -#define XTENSA_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ +#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 4 /* data width in bytes */ +#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay + * (1 = 5-stage, 2 = 7-stage) */ +#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ +#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ /* In T1050, applies to selected core load and store instructions (see ISA): */ -#define XTENSA_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */ -#define XTENSA_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/ -#define XTENSA_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */ -#define XTENSA_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/ +#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */ +#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/ -#define XTENSA_SW_VERSION 1100003 /* sw version of this header */ +#define XCHAL_SW_VERSION 1100003 /* sw version of this header */ -#define XTENSA_CORE_ID "esp32_v3_49_prod" /* alphanum core name - * (CoreID) set in the Xtensa - * Processor Generator */ +#define XCHAL_CORE_ID "esp32_v3_49_prod" + /* alphanum core name + * (CoreID) set in the Xtensa + * Processor Generator */ -#define XTENSA_BUILD_UNIQUE_ID 0x0005fe96 /* 22-bit sw build ID */ +#define XCHAL_BUILD_UNIQUE_ID 0x0005fe96 /* 22-bit sw build ID */ /* * These definitions describe the hardware targeted by this software. */ -#define XTENSA_HW_CONFIGID0 0xc2bcfffe /* ConfigID hi 32 bits*/ -#define XTENSA_HW_CONFIGID1 0x1cc5fe96 /* ConfigID lo 32 bits*/ -#define XTENSA_HW_VERSION_NAME "LX6.0.3" /* full version name */ -#define XTENSA_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */ -#define XTENSA_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */ -#define XTENSA_HW_VERSION 260003 /* major*100+minor */ -#define XTENSA_HW_REL_LX6 1 -#define XTENSA_HW_REL_LX6_0 1 -#define XTENSA_HW_REL_LX6_0_3 1 -#define XTENSA_HW_CONFIGID_RELIABLE 1 +#define XCHAL_HW_CONFIGID0 0xc2bcfffe /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x1cc5fe96 /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX6.0.3" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION 260003 /* major*100+minor */ +#define XCHAL_HW_REL_LX6 1 +#define XCHAL_HW_REL_LX6_0 1 +#define XCHAL_HW_REL_LX6_0_3 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 /* If software targets a *range* of hardware versions, these are the bounds: */ -#define XTENSA_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */ -#define XTENSA_HW_MIN_VERSION_MINOR 3 /* minor v of earliest tgt hw */ -#define XTENSA_HW_MIN_VERSION 260003 /* earliest targeted hw */ -#define XTENSA_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */ -#define XTENSA_HW_MAX_VERSION_MINOR 3 /* minor v of latest tgt hw */ -#define XTENSA_HW_MAX_VERSION 260003 /* latest targeted hw */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 3 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 260003 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 3 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 260003 /* latest targeted hw */ /* Cache ********************************************************************/ -#define XTENSA_ICACHE_LINESIZE 4 /* I-cache line size in bytes */ -#define XTENSA_DCACHE_LINESIZE 4 /* D-cache line size in bytes */ -#define XTENSA_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */ -#define XTENSA_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */ +#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */ -#define XTENSA_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ -#define XTENSA_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ +#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ -#define XTENSA_DCACHE_IS_WRITEBACK 0 /* writeback feature */ -#define XTENSA_DCACHE_IS_COHERENT 0 /* MP coherence feature */ +#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */ +#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ -#define XTENSA_HAVE_PREFETCH 0 /* PREFCTL register */ -#define XTENSA_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ -#define XTENSA_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ -#define XTENSA_PREFETCH_ENTRIES 0 /* cache prefetch entries */ -#define XTENSA_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ -#define XTENSA_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ -#define XTENSA_HAVE_ICACHE_TEST 0 /* Icache test instructions */ -#define XTENSA_HAVE_DCACHE_TEST 0 /* Dcache test instructions */ -#define XTENSA_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ -#define XTENSA_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ +#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ +#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ +#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ +#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ +#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ +#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ +#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */ +#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */ +#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ +#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ /* Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code */ -#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY +#ifndef XCHAL_HAL_NON_PRIVILEGED_ONLY /* Cache ********************************************************************/ -#define XTENSA_HAVE_PIF 1 /* any outbound PIF present */ -#define XTENSA_HAVE_AXI 0 /* AXI bus */ +#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ +#define XCHAL_HAVE_AXI 0 /* AXI bus */ -#define XTENSA_HAVE_PIF_WR_RESP 0 /* pif write response */ -#define XTENSA_HAVE_PIF_REQ_ATTR 0 /* pif attribute */ +#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ +#define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */ /* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ /* Number of cache sets in log2(lines per way): */ -#define XTENSA_ICACHE_SETWIDTH 0 -#define XTENSA_DCACHE_SETWIDTH 0 +#define XCHAL_ICACHE_SETWIDTH 0 +#define XCHAL_DCACHE_SETWIDTH 0 /* Cache set associativity (number of ways): */ -#define XTENSA_ICACHE_WAYS 1 -#define XTENSA_DCACHE_WAYS 1 +#define XCHAL_ICACHE_WAYS 1 +#define XCHAL_DCACHE_WAYS 1 /* Cache features: */ -#define XTENSA_ICACHE_LINE_LOCKABLE 0 -#define XTENSA_DCACHE_LINE_LOCKABLE 0 -#define XTENSA_ICACHE_ECC_PARITY 0 -#define XTENSA_DCACHE_ECC_PARITY 0 +#define XCHAL_ICACHE_LINE_LOCKABLE 0 +#define XCHAL_DCACHE_LINE_LOCKABLE 0 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 /* Cache access size in bytes (affects operation of SICW instruction): */ -#define XTENSA_ICACHE_ACCESS_SIZE 1 -#define XTENSA_DCACHE_ACCESS_SIZE 1 +#define XCHAL_ICACHE_ACCESS_SIZE 1 +#define XCHAL_DCACHE_ACCESS_SIZE 1 -#define XTENSA_DCACHE_BANKS 0 /* number of banks */ +#define XCHAL_DCACHE_BANKS 0 /* number of banks */ /* Number of encoded cache attr bits for decoded bits): */ -#define XTENSA_CA_BITS 4 +#define XCHAL_CA_BITS 4 /* Internal I/D RAM/ROMs and XLMI *******************************************/ -#define XTENSA_NUM_INSTROM 1 /* number of core instr. ROMs */ -#define XTENSA_NUM_INSTRAM 2 /* number of core instr. RAMs */ -#define XTENSA_NUM_DATAROM 1 /* number of core data ROMs */ -#define XTENSA_NUM_DATARAM 2 /* number of core data RAMs */ -#define XTENSA_NUM_URAM 0 /* number of core unified RAMs*/ -#define XTENSA_NUM_XLMI 1 /* number of core XLMI ports */ +#define XCHAL_NUM_INSTROM 1 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 1 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */ /* Instruction ROM 0: */ -#define XTENSA_INSTROM0_VADDR 0x40800000 /* virtual address */ -#define XTENSA_INSTROM0_PADDR 0x40800000 /* physical address */ -#define XTENSA_INSTROM0_SIZE 4194304 /* size in bytes */ -#define XTENSA_INSTROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_INSTROM0_VADDR 0x40800000 /* virtual address */ +#define XCHAL_INSTROM0_PADDR 0x40800000 /* physical address */ +#define XCHAL_INSTROM0_SIZE 4194304 /* size in bytes */ +#define XCHAL_INSTROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ /* Instruction RAM 0: */ -#define XTENSA_INSTRAM0_VADDR 0x40000000 /* virtual address */ -#define XTENSA_INSTRAM0_PADDR 0x40000000 /* physical address */ -#define XTENSA_INSTRAM0_SIZE 4194304 /* size in bytes */ -#define XTENSA_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */ +#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */ +#define XCHAL_INSTRAM0_SIZE 4194304 /* size in bytes */ +#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ /* Instruction RAM 1: */ -#define XTENSA_INSTRAM1_VADDR 0x40400000 /* virtual address */ -#define XTENSA_INSTRAM1_PADDR 0x40400000 /* physical address */ -#define XTENSA_INSTRAM1_SIZE 4194304 /* size in bytes */ -#define XTENSA_INSTRAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_INSTRAM1_VADDR 0x40400000 /* virtual address */ +#define XCHAL_INSTRAM1_PADDR 0x40400000 /* physical address */ +#define XCHAL_INSTRAM1_SIZE 4194304 /* size in bytes */ +#define XCHAL_INSTRAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ /* Data ROM 0: */ -#define XTENSA_DATAROM0_VADDR 0x3F400000 /* virtual address */ -#define XTENSA_DATAROM0_PADDR 0x3F400000 /* physical address */ -#define XTENSA_DATAROM0_SIZE 4194304 /* size in bytes */ -#define XTENSA_DATAROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ -#define XTENSA_DATAROM0_BANKS 1 /* number of banks */ +#define XCHAL_DATAROM0_VADDR 0x3F400000 /* virtual address */ +#define XCHAL_DATAROM0_PADDR 0x3F400000 /* physical address */ +#define XCHAL_DATAROM0_SIZE 4194304 /* size in bytes */ +#define XCHAL_DATAROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATAROM0_BANKS 1 /* number of banks */ /* Data RAM 0: */ -#define XTENSA_DATARAM0_VADDR 0x3FF80000 /* virtual address */ -#define XTENSA_DATARAM0_PADDR 0x3FF80000 /* physical address */ -#define XTENSA_DATARAM0_SIZE 524288 /* size in bytes */ -#define XTENSA_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ -#define XTENSA_DATARAM0_BANKS 1 /* number of banks */ +#define XCHAL_DATARAM0_VADDR 0x3FF80000 /* virtual address */ +#define XCHAL_DATARAM0_PADDR 0x3FF80000 /* physical address */ +#define XCHAL_DATARAM0_SIZE 524288 /* size in bytes */ +#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM0_BANKS 1 /* number of banks */ /* Data RAM 1: */ -#define XTENSA_DATARAM1_VADDR 0x3F800000 /* virtual address */ -#define XTENSA_DATARAM1_PADDR 0x3F800000 /* physical address */ -#define XTENSA_DATARAM1_SIZE 4194304 /* size in bytes */ -#define XTENSA_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ -#define XTENSA_DATARAM1_BANKS 1 /* number of banks */ +#define XCHAL_DATARAM1_VADDR 0x3F800000 /* virtual address */ +#define XCHAL_DATARAM1_PADDR 0x3F800000 /* physical address */ +#define XCHAL_DATARAM1_SIZE 4194304 /* size in bytes */ +#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM1_BANKS 1 /* number of banks */ /* XLMI Port 0: */ -#define XTENSA_XLMI0_VADDR 0x3FF00000 /* virtual address */ -#define XTENSA_XLMI0_PADDR 0x3FF00000 /* physical address */ -#define XTENSA_XLMI0_SIZE 524288 /* size in bytes */ -#define XTENSA_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_XLMI0_VADDR 0x3FF00000 /* virtual address */ +#define XCHAL_XLMI0_PADDR 0x3FF00000 /* physical address */ +#define XCHAL_XLMI0_SIZE 524288 /* size in bytes */ +#define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */ -#define XTENSA_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ +#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ /* Interrupts and Timers ****************************************************/ -#define XTENSA_HAVE_INTERRUPTS 1 /* interrupt option */ -#define XTENSA_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ -#define XTENSA_HAVE_NMI 1 /* non-maskable interrupt */ -#define XTENSA_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ -#define XTENSA_NUM_TIMERS 3 /* number of CCOMPAREn regs */ -#define XTENSA_NUM_INTERRUPTS 32 /* number of interrupts */ -#define XTENSA_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ -#define XTENSA_NUM_EXTINTERRUPTS 26 /* num of external interrupts */ -#define XTENSA_INT_NLEVELS 6 /* number of interrupt levels +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */ +#define XCHAL_INT_NLEVELS 6 /* number of interrupt levels (not including level zero) */ -#define XTENSA_EXCM_LEVEL 3 /* level masked by PS.EXCM */ +#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ /* Masks of interrupts at each interrupt level: */ -#define XTENSA_INTLEVEL1_MASK 0x000637FF -#define XTENSA_INTLEVEL2_MASK 0x00380000 -#define XTENSA_INTLEVEL3_MASK 0x28C08800 -#define XTENSA_INTLEVEL4_MASK 0x53000000 -#define XTENSA_INTLEVEL5_MASK 0x84010000 -#define XTENSA_INTLEVEL6_MASK 0x00000000 -#define XTENSA_INTLEVEL7_MASK 0x00004000 +#define XCHAL_INTLEVEL1_MASK 0x000637FF +#define XCHAL_INTLEVEL2_MASK 0x00380000 +#define XCHAL_INTLEVEL3_MASK 0x28C08800 +#define XCHAL_INTLEVEL4_MASK 0x53000000 +#define XCHAL_INTLEVEL5_MASK 0x84010000 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00004000 /* Masks of interrupts at each range 1..n of interrupt levels: */ -#define XTENSA_INTLEVEL1_ANDBELOW_MASK 0x000637FF -#define XTENSA_INTLEVEL2_ANDBELOW_MASK 0x003E37FF -#define XTENSA_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF -#define XTENSA_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF -#define XTENSA_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF -#define XTENSA_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFFF -#define XTENSA_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000637FF +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x003E37FF +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF /* Level of each interrupt: */ -#define XTENSA_INT0_LEVEL 1 -#define XTENSA_INT1_LEVEL 1 -#define XTENSA_INT2_LEVEL 1 -#define XTENSA_INT3_LEVEL 1 -#define XTENSA_INT4_LEVEL 1 -#define XTENSA_INT5_LEVEL 1 -#define XTENSA_INT6_LEVEL 1 -#define XTENSA_INT7_LEVEL 1 -#define XTENSA_INT8_LEVEL 1 -#define XTENSA_INT9_LEVEL 1 -#define XTENSA_INT10_LEVEL 1 -#define XTENSA_INT11_LEVEL 3 -#define XTENSA_INT12_LEVEL 1 -#define XTENSA_INT13_LEVEL 1 -#define XTENSA_INT14_LEVEL 7 -#define XTENSA_INT15_LEVEL 3 -#define XTENSA_INT16_LEVEL 5 -#define XTENSA_INT17_LEVEL 1 -#define XTENSA_INT18_LEVEL 1 -#define XTENSA_INT19_LEVEL 2 -#define XTENSA_INT20_LEVEL 2 -#define XTENSA_INT21_LEVEL 2 -#define XTENSA_INT22_LEVEL 3 -#define XTENSA_INT23_LEVEL 3 -#define XTENSA_INT24_LEVEL 4 -#define XTENSA_INT25_LEVEL 4 -#define XTENSA_INT26_LEVEL 5 -#define XTENSA_INT27_LEVEL 3 -#define XTENSA_INT28_LEVEL 4 -#define XTENSA_INT29_LEVEL 3 -#define XTENSA_INT30_LEVEL 4 -#define XTENSA_INT31_LEVEL 5 -#define XTENSA_DEBUGLEVEL 6 /* debug interrupt level */ -#define XTENSA_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ -#define XTENSA_NMILEVEL 7 /* NMI "level" (for use with - * EXCSAVE/EPS/EPC_n, RFI n) */ +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 1 +#define XCHAL_INT2_LEVEL 1 +#define XCHAL_INT3_LEVEL 1 +#define XCHAL_INT4_LEVEL 1 +#define XCHAL_INT5_LEVEL 1 +#define XCHAL_INT6_LEVEL 1 +#define XCHAL_INT7_LEVEL 1 +#define XCHAL_INT8_LEVEL 1 +#define XCHAL_INT9_LEVEL 1 +#define XCHAL_INT10_LEVEL 1 +#define XCHAL_INT11_LEVEL 3 +#define XCHAL_INT12_LEVEL 1 +#define XCHAL_INT13_LEVEL 1 +#define XCHAL_INT14_LEVEL 7 +#define XCHAL_INT15_LEVEL 3 +#define XCHAL_INT16_LEVEL 5 +#define XCHAL_INT17_LEVEL 1 +#define XCHAL_INT18_LEVEL 1 +#define XCHAL_INT19_LEVEL 2 +#define XCHAL_INT20_LEVEL 2 +#define XCHAL_INT21_LEVEL 2 +#define XCHAL_INT22_LEVEL 3 +#define XCHAL_INT23_LEVEL 3 +#define XCHAL_INT24_LEVEL 4 +#define XCHAL_INT25_LEVEL 4 +#define XCHAL_INT26_LEVEL 5 +#define XCHAL_INT27_LEVEL 3 +#define XCHAL_INT28_LEVEL 4 +#define XCHAL_INT29_LEVEL 3 +#define XCHAL_INT30_LEVEL 4 +#define XCHAL_INT31_LEVEL 5 +#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with + * EXCSAVE/EPS/EPC_n, RFI n) */ /* Type of each interrupt: */ -#define XTENSA_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XTENSA_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XTENSA_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XTENSA_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XTENSA_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XTENSA_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XTENSA_INT6_TYPE XTHAL_INTTYPE_TIMER -#define XTENSA_INT7_TYPE XTHAL_INTTYPE_SOFTWARE -#define XTENSA_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XTENSA_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XTENSA_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE -#define XTENSA_INT11_TYPE XTHAL_INTTYPE_PROFILING -#define XTENSA_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XTENSA_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XTENSA_INT14_TYPE XTHAL_INTTYPE_NMI -#define XTENSA_INT15_TYPE XTHAL_INTTYPE_TIMER -#define XTENSA_INT16_TYPE XTHAL_INTTYPE_TIMER -#define XTENSA_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XTENSA_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XTENSA_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XTENSA_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XTENSA_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XTENSA_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE -#define XTENSA_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XTENSA_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XTENSA_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XTENSA_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XTENSA_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL -#define XTENSA_INT28_TYPE XTHAL_INTTYPE_EXTERN_EDGE -#define XTENSA_INT29_TYPE XTHAL_INTTYPE_SOFTWARE -#define XTENSA_INT30_TYPE XTHAL_INTTYPE_EXTERN_EDGE -#define XTENSA_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_PROFILING +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT29_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL /* Masks of interrupts for each type of interrupt: */ -#define XTENSA_INTTYPE_MASK_UNCONFIGURED 0x00000000 -#define XTENSA_INTTYPE_MASK_SOFTWARE 0x20000080 -#define XTENSA_INTTYPE_MASK_EXTERN_EDGE 0x50400400 -#define XTENSA_INTTYPE_MASK_EXTERN_LEVEL 0x8FBE333F -#define XTENSA_INTTYPE_MASK_TIMER 0x00018040 -#define XTENSA_INTTYPE_MASK_NMI 0x00004000 -#define XTENSA_INTTYPE_MASK_WRITE_ERROR 0x00000000 -#define XTENSA_INTTYPE_MASK_PROFILING 0x00000800 +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x20000080 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x50400400 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x8FBE333F +#define XCHAL_INTTYPE_MASK_TIMER 0x00018040 +#define XCHAL_INTTYPE_MASK_NMI 0x00004000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 +#define XCHAL_INTTYPE_MASK_PROFILING 0x00000800 /* Interrupt numbers assigned to specific interrupt sources: */ -#define XTENSA_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ -#define XTENSA_TIMER1_INTERRUPT 15 /* CCOMPARE1 */ -#define XTENSA_TIMER2_INTERRUPT 16 /* CCOMPARE2 */ -#define XTENSA_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED -#define XTENSA_NMI_INTERRUPT 14 /* non-maskable interrupt */ -#define XTENSA_PROFILING_INTERRUPT 11 /* profiling interrupt */ +#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 15 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT 16 /* CCOMPARE2 */ +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ +#define XCHAL_PROFILING_INTERRUPT 11 /* profiling interrupt */ /* Interrupt numbers for levels at which only one interrupt is configured: */ -#define XTENSA_INTLEVEL7_NUM 14 +#define XCHAL_INTLEVEL7_NUM 14 /* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */ @@ -466,173 +467,173 @@ /* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ -#define XTENSA_EXTINT0_NUM 0 /* (intlevel 1) */ -#define XTENSA_EXTINT1_NUM 1 /* (intlevel 1) */ -#define XTENSA_EXTINT2_NUM 2 /* (intlevel 1) */ -#define XTENSA_EXTINT3_NUM 3 /* (intlevel 1) */ -#define XTENSA_EXTINT4_NUM 4 /* (intlevel 1) */ -#define XTENSA_EXTINT5_NUM 5 /* (intlevel 1) */ -#define XTENSA_EXTINT6_NUM 8 /* (intlevel 1) */ -#define XTENSA_EXTINT7_NUM 9 /* (intlevel 1) */ -#define XTENSA_EXTINT8_NUM 10 /* (intlevel 1) */ -#define XTENSA_EXTINT9_NUM 12 /* (intlevel 1) */ -#define XTENSA_EXTINT10_NUM 13 /* (intlevel 1) */ -#define XTENSA_EXTINT11_NUM 14 /* (intlevel 7) */ -#define XTENSA_EXTINT12_NUM 17 /* (intlevel 1) */ -#define XTENSA_EXTINT13_NUM 18 /* (intlevel 1) */ -#define XTENSA_EXTINT14_NUM 19 /* (intlevel 2) */ -#define XTENSA_EXTINT15_NUM 20 /* (intlevel 2) */ -#define XTENSA_EXTINT16_NUM 21 /* (intlevel 2) */ -#define XTENSA_EXTINT17_NUM 22 /* (intlevel 3) */ -#define XTENSA_EXTINT18_NUM 23 /* (intlevel 3) */ -#define XTENSA_EXTINT19_NUM 24 /* (intlevel 4) */ -#define XTENSA_EXTINT20_NUM 25 /* (intlevel 4) */ -#define XTENSA_EXTINT21_NUM 26 /* (intlevel 5) */ -#define XTENSA_EXTINT22_NUM 27 /* (intlevel 3) */ -#define XTENSA_EXTINT23_NUM 28 /* (intlevel 4) */ -#define XTENSA_EXTINT24_NUM 30 /* (intlevel 4) */ -#define XTENSA_EXTINT25_NUM 31 /* (intlevel 5) */ +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ +#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ +#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ +#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ +#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ +#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ +#define XCHAL_EXTINT6_NUM 8 /* (intlevel 1) */ +#define XCHAL_EXTINT7_NUM 9 /* (intlevel 1) */ +#define XCHAL_EXTINT8_NUM 10 /* (intlevel 1) */ +#define XCHAL_EXTINT9_NUM 12 /* (intlevel 1) */ +#define XCHAL_EXTINT10_NUM 13 /* (intlevel 1) */ +#define XCHAL_EXTINT11_NUM 14 /* (intlevel 7) */ +#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ +#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ +#define XCHAL_EXTINT14_NUM 19 /* (intlevel 2) */ +#define XCHAL_EXTINT15_NUM 20 /* (intlevel 2) */ +#define XCHAL_EXTINT16_NUM 21 /* (intlevel 2) */ +#define XCHAL_EXTINT17_NUM 22 /* (intlevel 3) */ +#define XCHAL_EXTINT18_NUM 23 /* (intlevel 3) */ +#define XCHAL_EXTINT19_NUM 24 /* (intlevel 4) */ +#define XCHAL_EXTINT20_NUM 25 /* (intlevel 4) */ +#define XCHAL_EXTINT21_NUM 26 /* (intlevel 5) */ +#define XCHAL_EXTINT22_NUM 27 /* (intlevel 3) */ +#define XCHAL_EXTINT23_NUM 28 /* (intlevel 4) */ +#define XCHAL_EXTINT24_NUM 30 /* (intlevel 4) */ +#define XCHAL_EXTINT25_NUM 31 /* (intlevel 5) */ /* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ -#define XTENSA_INT0_EXTNUM 0 /* (intlevel 1) */ -#define XTENSA_INT1_EXTNUM 1 /* (intlevel 1) */ -#define XTENSA_INT2_EXTNUM 2 /* (intlevel 1) */ -#define XTENSA_INT3_EXTNUM 3 /* (intlevel 1) */ -#define XTENSA_INT4_EXTNUM 4 /* (intlevel 1) */ -#define XTENSA_INT5_EXTNUM 5 /* (intlevel 1) */ -#define XTENSA_INT8_EXTNUM 6 /* (intlevel 1) */ -#define XTENSA_INT9_EXTNUM 7 /* (intlevel 1) */ -#define XTENSA_INT10_EXTNUM 8 /* (intlevel 1) */ -#define XTENSA_INT12_EXTNUM 9 /* (intlevel 1) */ -#define XTENSA_INT13_EXTNUM 10 /* (intlevel 1) */ -#define XTENSA_INT14_EXTNUM 11 /* (intlevel 7) */ -#define XTENSA_INT17_EXTNUM 12 /* (intlevel 1) */ -#define XTENSA_INT18_EXTNUM 13 /* (intlevel 1) */ -#define XTENSA_INT19_EXTNUM 14 /* (intlevel 2) */ -#define XTENSA_INT20_EXTNUM 15 /* (intlevel 2) */ -#define XTENSA_INT21_EXTNUM 16 /* (intlevel 2) */ -#define XTENSA_INT22_EXTNUM 17 /* (intlevel 3) */ -#define XTENSA_INT23_EXTNUM 18 /* (intlevel 3) */ -#define XTENSA_INT24_EXTNUM 19 /* (intlevel 4) */ -#define XTENSA_INT25_EXTNUM 20 /* (intlevel 4) */ -#define XTENSA_INT26_EXTNUM 21 /* (intlevel 5) */ -#define XTENSA_INT27_EXTNUM 22 /* (intlevel 3) */ -#define XTENSA_INT28_EXTNUM 23 /* (intlevel 4) */ -#define XTENSA_INT30_EXTNUM 24 /* (intlevel 4) */ -#define XTENSA_INT31_EXTNUM 25 /* (intlevel 5) */ +#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ +#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ +#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ +#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ +#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ +#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ +#define XCHAL_INT8_EXTNUM 6 /* (intlevel 1) */ +#define XCHAL_INT9_EXTNUM 7 /* (intlevel 1) */ +#define XCHAL_INT10_EXTNUM 8 /* (intlevel 1) */ +#define XCHAL_INT12_EXTNUM 9 /* (intlevel 1) */ +#define XCHAL_INT13_EXTNUM 10 /* (intlevel 1) */ +#define XCHAL_INT14_EXTNUM 11 /* (intlevel 7) */ +#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */ +#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */ +#define XCHAL_INT19_EXTNUM 14 /* (intlevel 2) */ +#define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */ +#define XCHAL_INT21_EXTNUM 16 /* (intlevel 2) */ +#define XCHAL_INT22_EXTNUM 17 /* (intlevel 3) */ +#define XCHAL_INT23_EXTNUM 18 /* (intlevel 3) */ +#define XCHAL_INT24_EXTNUM 19 /* (intlevel 4) */ +#define XCHAL_INT25_EXTNUM 20 /* (intlevel 4) */ +#define XCHAL_INT26_EXTNUM 21 /* (intlevel 5) */ +#define XCHAL_INT27_EXTNUM 22 /* (intlevel 3) */ +#define XCHAL_INT28_EXTNUM 23 /* (intlevel 4) */ +#define XCHAL_INT30_EXTNUM 24 /* (intlevel 4) */ +#define XCHAL_INT31_EXTNUM 25 /* (intlevel 5) */ /* Exceptions and Vectors ***************************************************/ -#define XTENSA_XEA_VERSION 2 /* Xtensa Exception Architecture +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture * number: 1 == XEA1 (old) * 2 == XEA2 (new) * 0 == XEAX (extern) or TX */ -#define XTENSA_HAVE_XEA1 0 /* Exception Architecture 1 */ -#define XTENSA_HAVE_XEA2 1 /* Exception Architecture 2 */ -#define XTENSA_HAVE_XEAX 0 /* External Exception Arch. */ -#define XTENSA_HAVE_EXCEPTIONS 1 /* exception option */ -#define XTENSA_HAVE_HALT 0 /* halt architecture option */ -#define XTENSA_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ -#define XTENSA_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ -#define XTENSA_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ -#define XTENSA_HAVE_VECBASE 1 /* relocatable vectors */ -#define XTENSA_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */ -#define XTENSA_VECBASE_RESET_PADDR 0x40000000 -#define XTENSA_RESET_VECBASE_OVERLAP 0 - -#define XTENSA_RESET_VECTOR0_VADDR 0x50000000 -#define XTENSA_RESET_VECTOR0_PADDR 0x50000000 -#define XTENSA_RESET_VECTOR1_VADDR 0x40000400 -#define XTENSA_RESET_VECTOR1_PADDR 0x40000400 -#define XTENSA_RESET_VECTOR_VADDR 0x40000400 -#define XTENSA_RESET_VECTOR_PADDR 0x40000400 -#define XTENSA_USER_VECOFS 0x00000340 -#define XTENSA_USER_VECTOR_VADDR 0x40000340 -#define XTENSA_USER_VECTOR_PADDR 0x40000340 -#define XTENSA_KERNEL_VECOFS 0x00000300 -#define XTENSA_KERNEL_VECTOR_VADDR 0x40000300 -#define XTENSA_KERNEL_VECTOR_PADDR 0x40000300 -#define XTENSA_DOUBLEEXC_VECOFS 0x000003C0 -#define XTENSA_DOUBLEEXC_VECTOR_VADDR 0x400003C0 -#define XTENSA_DOUBLEEXC_VECTOR_PADDR 0x400003C0 -#define XTENSA_WINDOW_OF4_VECOFS 0x00000000 -#define XTENSA_WINDOW_UF4_VECOFS 0x00000040 -#define XTENSA_WINDOW_OF8_VECOFS 0x00000080 -#define XTENSA_WINDOW_UF8_VECOFS 0x000000C0 -#define XTENSA_WINDOW_OF12_VECOFS 0x00000100 -#define XTENSA_WINDOW_UF12_VECOFS 0x00000140 -#define XTENSA_WINDOW_VECTORS_VADDR 0x40000000 -#define XTENSA_WINDOW_VECTORS_PADDR 0x40000000 -#define XTENSA_INTLEVEL2_VECOFS 0x00000180 -#define XTENSA_INTLEVEL2_VECTOR_VADDR 0x40000180 -#define XTENSA_INTLEVEL2_VECTOR_PADDR 0x40000180 -#define XTENSA_INTLEVEL3_VECOFS 0x000001C0 -#define XTENSA_INTLEVEL3_VECTOR_VADDR 0x400001C0 -#define XTENSA_INTLEVEL3_VECTOR_PADDR 0x400001C0 -#define XTENSA_INTLEVEL4_VECOFS 0x00000200 -#define XTENSA_INTLEVEL4_VECTOR_VADDR 0x40000200 -#define XTENSA_INTLEVEL4_VECTOR_PADDR 0x40000200 -#define XTENSA_INTLEVEL5_VECOFS 0x00000240 -#define XTENSA_INTLEVEL5_VECTOR_VADDR 0x40000240 -#define XTENSA_INTLEVEL5_VECTOR_PADDR 0x40000240 -#define XTENSA_INTLEVEL6_VECOFS 0x00000280 -#define XTENSA_INTLEVEL6_VECTOR_VADDR 0x40000280 -#define XTENSA_INTLEVEL6_VECTOR_PADDR 0x40000280 -#define XTENSA_DEBUG_VECOFS XTENSA_INTLEVEL6_VECOFS -#define XTENSA_DEBUG_VECTOR_VADDR XTENSA_INTLEVEL6_VECTOR_VADDR -#define XTENSA_DEBUG_VECTOR_PADDR XTENSA_INTLEVEL6_VECTOR_PADDR -#define XTENSA_NMI_VECOFS 0x000002C0 -#define XTENSA_NMI_VECTOR_VADDR 0x400002C0 -#define XTENSA_NMI_VECTOR_PADDR 0x400002C0 -#define XTENSA_INTLEVEL7_VECOFS XTENSA_NMI_VECOFS -#define XTENSA_INTLEVEL7_VECTOR_VADDR XTENSA_NMI_VECTOR_VADDR -#define XTENSA_INTLEVEL7_VECTOR_PADDR XTENSA_NMI_VECTOR_PADDR +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_HALT 0 /* halt architecture option */ +#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x40000000 +#define XCHAL_RESET_VECBASE_OVERLAP 0 + +#define XCHAL_RESET_VECTOR0_VADDR 0x50000000 +#define XCHAL_RESET_VECTOR0_PADDR 0x50000000 +#define XCHAL_RESET_VECTOR1_VADDR 0x40000400 +#define XCHAL_RESET_VECTOR1_PADDR 0x40000400 +#define XCHAL_RESET_VECTOR_VADDR 0x40000400 +#define XCHAL_RESET_VECTOR_PADDR 0x40000400 +#define XCHAL_USER_VECOFS 0x00000340 +#define XCHAL_USER_VECTOR_VADDR 0x40000340 +#define XCHAL_USER_VECTOR_PADDR 0x40000340 +#define XCHAL_KERNEL_VECOFS 0x00000300 +#define XCHAL_KERNEL_VECTOR_VADDR 0x40000300 +#define XCHAL_KERNEL_VECTOR_PADDR 0x40000300 +#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0 +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0 +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000 +#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000 +#define XCHAL_INTLEVEL2_VECOFS 0x00000180 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180 +#define XCHAL_INTLEVEL3_VECOFS 0x000001C0 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0 +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0 +#define XCHAL_INTLEVEL4_VECOFS 0x00000200 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200 +#define XCHAL_INTLEVEL5_VECOFS 0x00000240 +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240 +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240 +#define XCHAL_INTLEVEL6_VECOFS 0x00000280 +#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280 +#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280 +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x000002C0 +#define XCHAL_NMI_VECTOR_VADDR 0x400002C0 +#define XCHAL_NMI_VECTOR_PADDR 0x400002C0 +#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR /* Debug Module *************************************************************/ /* Misc */ -#define XTENSA_HAVE_DEBUG_ERI 1 /* ERI to debug module */ -#define XTENSA_HAVE_DEBUG_APB 1 /* APB to debug module */ -#define XTENSA_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ +#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ +#define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */ +#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ /* On-Chip Debug (OCD) */ -#define XTENSA_HAVE_OCD 1 /* OnChipDebug option */ -#define XTENSA_NUM_IBREAK 2 /* number of IBREAKn regs */ -#define XTENSA_NUM_DBREAK 2 /* number of DBREAKn regs */ -#define XTENSA_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ -#define XTENSA_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ +#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ /* TRAX (in core) */ -#define XTENSA_HAVE_TRAX 1 /* TRAX in debug module */ -#define XTENSA_TRAX_MEM_SIZE 16384 /* TRAX memory size in bytes */ -#define XTENSA_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ -#define XTENSA_TRAX_ATB_WIDTH 32 /* ATB width (bits), 0=no ATB */ -#define XTENSA_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ +#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ +#define XCHAL_TRAX_MEM_SIZE 16384 /* TRAX memory size in bytes */ +#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ +#define XCHAL_TRAX_ATB_WIDTH 32 /* ATB width (bits), 0=no ATB */ +#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ /* Perf counters */ -#define XTENSA_NUM_PERF_COUNTERS 2 /* performance counters */ +#define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */ /* MMU **********************************************************************/ -#define XTENSA_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ -#define XTENSA_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ -#define XTENSA_SPANNING_WAY 0 /* TLB spanning way number */ -#define XTENSA_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ -#define XTENSA_HAVE_CACHEATTR 0 /* CACHEATTR register present */ -#define XTENSA_HAVE_MIMIC_CACHEATTR 1 /* region protection */ -#define XTENSA_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ -#define XTENSA_HAVE_PTP_MMU 0 /* full MMU (with page table - * [autorefill] and protection) - * usable for an MMU-based OS */ +#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ +#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ +#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table + * [autorefill] and protection) + * usable for an MMU-based OS */ /* If none of the above last 4 are set, it's a custom TLB configuration. */ -#define XTENSA_MMU_ASID_BITS 0 /* number of bits in ASIDs */ -#define XTENSA_MMU_RINGS 1 /* number of rings (1..4) */ -#define XTENSA_MMU_RING_BITS 0 /* num of bits in RING field */ +#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ -#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ +#endif /* !XCHAL_HAL_NON_PRIVILEGED_ONLY */ #endif /* __ARCH_XTENSA_INCLUDE_ESP32_CORE_ISA_H */ diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index 4eece4c34b..ae7e71ec37 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -97,7 +97,7 @@ #define _REG_LOOPS_START (21) -#ifdef XTENSA_HAVE_LOOPS +#ifdef XCHAL_HAVE_LOOPS # define REG_LBEG (_REG_LOOPS_START + 0) # define REG_LEND (_REG_LOOPS_START + 1) # define REG_LCOUNT (_REG_LOOPS_START + 2) diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index 01d9e97748..6bcab6a501 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -142,7 +142,7 @@ _xtensa_context_save: rsr a3, SAR s32i a3, a2, (4 * REG_SAR) -#ifdef XTENSA_HAVE_LOOPS +#ifdef XCHAL_HAVE_LOOPS rsr a3, LBEG s32i a3, a2, (4 * REG_LBEG) rsr a3, LEND @@ -167,7 +167,7 @@ _xtensa_context_save: /* To spill the reg windows, temp. need pre-interrupt stack ptr and * a4-15. Need to save a9,12,13 temporarily (in frame temps) and * recover originals. Interrupts need to be disabled below - * XTENSA_EXCM_LEVEL and window overflow and underflow exceptions + * XCHAL_EXCM_LEVEL and window overflow and underflow exceptions * disabled (assured by PS.EXCM == 1). */ @@ -339,7 +339,7 @@ _xtensa_context_restore: mov a0, a13 /* Retrieve ret addr */ #endif -#ifdef XTENSA_HAVE_LOOPS +#ifdef XCHAL_HAVE_LOOPS l32i a2, a2, (4 * REG_LBEG) l32i a3, a2, (4 * REG_LEND) wsr a2, LBEG diff --git a/arch/xtensa/src/common/xtensa_dumpstate.c b/arch/xtensa/src/common/xtensa_dumpstate.c index 0fd5538f30..8c8cea3bf9 100644 --- a/arch/xtensa/src/common/xtensa_dumpstate.c +++ b/arch/xtensa/src/common/xtensa_dumpstate.c @@ -118,7 +118,7 @@ static inline void xtensa_registerdump(void) _alert(" SAR: %08lx CAUSE: %08lx VADDR: %08lx\n", (unsigned long)regs[REG_SAR], (unsigned long)regs[REG_EXCCAUSE], (unsigned long)regs[REG_EXCVADDR]); -#ifdef XTENSA_HAVE_LOOPS +#ifdef XCHAL_HAVE_LOOPS _alert(" LBEG: %08lx LEND: %08lx LCNT: %08lx\n", (unsigned long)regs[REG_LBEG], (unsigned long)regs[REG_LEND], (unsigned long)regs[REG_LCOUNT]); diff --git a/arch/xtensa/src/common/xtensa_inthandlers.S b/arch/xtensa/src/common/xtensa_inthandlers.S index cb18aec95b..817e458d50 100644 --- a/arch/xtensa/src/common/xtensa_inthandlers.S +++ b/arch/xtensa/src/common/xtensa_inthandlers.S @@ -259,7 +259,7 @@ * * Description: * Medium priority interrupts are by definition those with priority greater - * than 1 and not greater than XTENSA_EXCM_LEVEL. These are disabled + * than 1 and not greater than XCHAL_EXCM_LEVEL. These are disabled * by setting PS.EXCM and therefore can easily support a C environment for * handlers in C, and interact safely with NuttX. * @@ -277,7 +277,7 @@ * ****************************************************************************/ -#if XTENSA_EXCM_LEVEL >= 2 +#if XCHAL_EXCM_LEVEL >= 2 .section .iram1,"ax" .type _xtensa_level2_handler,@function .align 4 @@ -315,7 +315,7 @@ _xtensa_level2_handler: * context save area. */ - dispatch_c_isr 2 XTENSA_INTLEVEL2_MASK + dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK /* Restore registers in preparation to return from interrupt */ @@ -338,14 +338,14 @@ _xtensa_level2_handler: rfi 2 -#endif /* XTENSA_EXCM_LEVEL >= 2 */ +#endif /* XCHAL_EXCM_LEVEL >= 2 */ /**************************************************************************** * - * HIGH PRIORITY (LEVEL > XTENSA_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS + * HIGH PRIORITY (LEVEL > XCHAL_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS * * High priority interrupts are by definition those with priorities greater - * than XTENSA_EXCM_LEVEL. This includes non-maskable (NMI). High priority + * than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority * interrupts cannot interact with the RTOS, that is they must save all regs * they use and not call any RTOS function. * @@ -380,7 +380,7 @@ here. However a template and example can be found in the Cadence Design Systems documentation: "Microprocessor Programmer's Guide". */ -#if XTENSA_INT_NLEVELS >=2 && XTENSA_EXCM_LEVEL < 2 && XTENSA_DEBUGLEVEL !=2 +#if XCHAL_INT_NLEVELS >=2 && XCHAL_EXCM_LEVEL < 2 && XCHAL_DEBUGLEVEL !=2 .section .iram1,"ax" .type _xtensa_level2_handler, @function .align 4 @@ -410,9 +410,9 @@ _xtensa_level2_handler: rsr a0, EXCSAVE_2 /* Restore a0 */ rfi 2 -#endif /* XTENSA_INT_NLEVELS >=2 && XTENSA_EXCM_LEVEL < 2 && XTENSA_DEBUGLEVEL !=2 */ +#endif /* XCHAL_INT_NLEVELS >=2 && XCHAL_EXCM_LEVEL < 2 && XCHAL_DEBUGLEVEL !=2 */ -#if XTENSA_INT_NLEVELS >=3 && XTENSA_EXCM_LEVEL < 3 && XTENSA_DEBUGLEVEL !=3 +#if XCHAL_INT_NLEVELS >=3 && XCHAL_EXCM_LEVEL < 3 && XCHAL_DEBUGLEVEL !=3 .section .iram1,"ax" .type _xtensa_level3_handler, @function .align 4 @@ -441,9 +441,9 @@ _xtensa_level3_handler: rsr a0, EXCSAVE_3 /* Restore a0 */ rfi 3 -#endif /* XTENSA_INT_NLEVELS >=3 && XTENSA_EXCM_LEVEL < 3 && XTENSA_DEBUGLEVEL !=3 */ +#endif /* XCHAL_INT_NLEVELS >=3 && XCHAL_EXCM_LEVEL < 3 && XCHAL_DEBUGLEVEL !=3 */ -#if XTENSA_INT_NLEVELS >=4 && XTENSA_EXCM_LEVEL < 4 && XTENSA_DEBUGLEVEL !=4 +#if XCHAL_INT_NLEVELS >=4 && XCHAL_EXCM_LEVEL < 4 && XCHAL_DEBUGLEVEL !=4 .section .iram1,"ax" .type _xtensa_level4_handler,@function .align 4 @@ -472,9 +472,9 @@ _xtensa_level4_handler: rsr a0, EXCSAVE_4 /* Restore a0 */ rfi 4 -#endif /* XTENSA_INT_NLEVELS >=4 && XTENSA_EXCM_LEVEL < 4 && XTENSA_DEBUGLEVEL !=4 */ +#endif /* XCHAL_INT_NLEVELS >=4 && XCHAL_EXCM_LEVEL < 4 && XCHAL_DEBUGLEVEL !=4 */ -#if XTENSA_INT_NLEVELS >=5 && XTENSA_EXCM_LEVEL < 5 && XTENSA_DEBUGLEVEL !=5 +#if XCHAL_INT_NLEVELS >=5 && XCHAL_EXCM_LEVEL < 5 && XCHAL_DEBUGLEVEL !=5 .section .iram1,"ax" .type _xtensa_level5_handler,@function .align 4 @@ -501,9 +501,9 @@ _xtensa_level5_handler: rsr a0, EXCSAVE_5 /* restore a0 */ rfi 5 -#endif /* XTENSA_INT_NLEVELS >=5 && XTENSA_EXCM_LEVEL < 5 && XTENSA_DEBUGLEVEL !=5 */ +#endif /* XCHAL_INT_NLEVELS >=5 && XCHAL_EXCM_LEVEL < 5 && XCHAL_DEBUGLEVEL !=5 */ -#if XTENSA_INT_NLEVELS >=6 && XTENSA_EXCM_LEVEL < 6 && XTENSA_DEBUGLEVEL !=6 +#if XCHAL_INT_NLEVELS >=6 && XCHAL_EXCM_LEVEL < 6 && XCHAL_DEBUGLEVEL !=6 .section .iram1,"ax" .type _xtensa_level6_handler, @function .align 4 @@ -530,4 +530,4 @@ _xtensa_level6_handler: rsr a0, EXCSAVE_6 /* Restore a0 */ rfi 6 -#endif /* XTENSA_INT_NLEVELS >=6 && XTENSA_EXCM_LEVEL < 6 && XTENSA_DEBUGLEVEL !=6 */ +#endif /* XCHAL_INT_NLEVELS >=6 && XCHAL_EXCM_LEVEL < 6 && XCHAL_DEBUGLEVEL !=6 */ diff --git a/arch/xtensa/src/common/xtensa_intvectors.S b/arch/xtensa/src/common/xtensa_intvectors.S index 3d27de4767..d570057086 100644 --- a/arch/xtensa/src/common/xtensa_intvectors.S +++ b/arch/xtensa/src/common/xtensa_intvectors.S @@ -60,7 +60,7 @@ * ****************************************************************************/ -#if XTENSA_EXCM_LEVEL >= 2 +#if XCHAL_EXCM_LEVEL >= 2 .begin literal_prefix .xtensa_level2_vector .section .xtensa_level2_vector.text, "ax" .global _xtensa_level2_vector @@ -79,7 +79,7 @@ _xtensa_level2_vector: .size _xtensa_level2_vector, . - _xtensa_level2_vector #endif -#if XTENSA_EXCM_LEVEL >= 3 +#if XCHAL_EXCM_LEVEL >= 3 .begin literal_prefix .xtensa_level3_vector .section .xtensa_level3_vector.text, "ax" .global _xtensa_level3_vector @@ -98,7 +98,7 @@ _xtensa_level3_vector: .size _xtensa_level3_vector, . - _xtensa_level3_vector #endif -#if XTENSA_EXCM_LEVEL >= 4 +#if XCHAL_EXCM_LEVEL >= 4 .begin literal_prefix .xtensa_level4_vector .section .xtensa_level4_vector.text, "ax" .global _xtensa_level4_vector @@ -117,7 +117,7 @@ _xtensa_level4_vector: .size _xtensa_level5_vector, . - _xtensa_level5_vector #endif -#if XTENSA_EXCM_LEVEL >= 5 +#if XCHAL_EXCM_LEVEL >= 5 .begin literal_prefix .xtensa_level5_vector .section .xtensa_level5_vector.text, "ax" .global _xtensa_level5_vector @@ -136,7 +136,7 @@ _xtensa_level5_vector: .size _xtensa_level5_vector, . - _xtensa_level5_vector #endif -#if XTENSA_EXCM_LEVEL >= 6 +#if XCHAL_EXCM_LEVEL >= 6 .begin literal_prefix .xtensa_level6_vector .section .xtensa_level6_vector.text, "ax" .global _xtensa_level6_vector diff --git a/arch/xtensa/src/common/xtensa_irq.S b/arch/xtensa/src/common/xtensa_irq.S index 4ecd099d10..d601d6d9ce 100644 --- a/arch/xtensa/src/common/xtensa_irq.S +++ b/arch/xtensa/src/common/xtensa_irq.S @@ -43,7 +43,7 @@ * Public Data ****************************************************************************/ -#ifdef CONFIG_XTENSA_HAVE_INTERRUPTS +#ifdef CONFIG_XCHAL_HAVE_INTERRUPTS /* INTENABLE virtualization information. */ @@ -64,7 +64,7 @@ _xtensa_vprimask: .word 0xffffffff /* Virtual priority mask */ .size _xtensa_vprimask, 4 -#endif /* CONFIG_XTENSA_HAVE_INTERRUPTS */ +#endif /* CONFIG_XCHAL_HAVE_INTERRUPTS */ /**************************************************************************** * Public Functions @@ -89,7 +89,7 @@ _xtensa_vprimask: xtensa_enable_interrupts: ENTRY0 -#ifdef CONFIG_XTENSA_HAVE_INTERRUPTS +#ifdef CONFIG_XCHAL_HAVE_INTERRUPTS movi a3, 0 movi a4, _xtensa_intdata xsr a3, INTENABLE /* Disables all interrupts */ @@ -127,7 +127,7 @@ xtensa_enable_interrupts: xtensa_disable_interrupts: ENTRY0 -#ifdef CONFIG_XTENSA_HAVE_INTERRUPTS +#ifdef CONFIG_XCHAL_HAVE_INTERRUPTS movi a3, 0 movi a4, _xtensa_intdata xsr a3, INTENABLE /* Disables all interrupts */ diff --git a/arch/xtensa/src/common/xtensa_timer.h b/arch/xtensa/src/common/xtensa_timer.h index 6adf77fea3..27203b3725 100644 --- a/arch/xtensa/src/common/xtensa_timer.h +++ b/arch/xtensa/src/common/xtensa_timer.h @@ -47,33 +47,33 @@ * Otherwise select the first low or medium priority interrupt timer available. */ -#if XTENSA_NUM_TIMERS == 0 +#if XCHAL_NUM_TIMERS == 0 # error "This Xtensa configuration is unsupported, it has no timers." #else #ifndef XT_TIMER_INDEX -# if XTENSA_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED -# if XTENSA_INT_LEVEL(XTENSA_TIMER3_INTERRUPT) <= XTENSA_EXCM_LEVEL +# if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED +# if XTENSA_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL # undef XT_TIMER_INDEX # define XT_TIMER_INDEX 3 # endif # endif -# if XTENSA_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED -# if XTENSA_INT_LEVEL(XTENSA_TIMER2_INTERRUPT) <= XTENSA_EXCM_LEVEL +# if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED +# if XTENSA_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL # undef XT_TIMER_INDEX # define XT_TIMER_INDEX 2 # endif # endif -# if XTENSA_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED -# if XTENSA_INT_LEVEL(XTENSA_TIMER1_INTERRUPT) <= XTENSA_EXCM_LEVEL +# if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED +# if XTENSA_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL # undef XT_TIMER_INDEX # define XT_TIMER_INDEX 1 # endif # endif -# if XTENSA_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED -# if XTENSA_INT_LEVEL(XTENSA_TIMER0_INTERRUPT) <= XTENSA_EXCM_LEVEL +# if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED +# if XTENSA_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL # undef XT_TIMER_INDEX # define XT_TIMER_INDEX 0 # endif @@ -90,11 +90,11 @@ #if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED # error "The timer selected by XT_TIMER_INDEX does not exist in this core." -#elif XT_TIMER_INTPRI > XTENSA_EXCM_LEVEL +#elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL # error "The timer interrupt cannot be high priority (use medium or low)." #endif -#endif /* XTENSA_NUM_TIMERS */ +#endif /* XCHAL_NUM_TIMERS */ /* Set processor clock frequency, used to determine clock divisor for timer * tick. User should BE SURE TO ADJUST THIS for the Xtensa platform being -- GitLab From 53de345f054cf760b720853217103ee1bd2add39 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 22 Oct 2016 09:29:15 -0600 Subject: [PATCH 171/734] Xtensa: Add up_cpu_index() --- arch/xtensa/src/common/xtensa_context.S | 8 +-- arch/xtensa/src/common/xtensa_inthandlers.S | 16 ++--- arch/xtensa/src/common/xtensa_irq.S | 2 + arch/xtensa/src/esp32/Make.defs | 4 +- arch/xtensa/src/esp32/esp32_cpuindex.S | 76 +++++++++++++++++++++ 5 files changed, 92 insertions(+), 14 deletions(-) create mode 100644 arch/xtensa/src/esp32/esp32_cpuindex.S diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index 6bcab6a501..37cdb796fd 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -160,7 +160,7 @@ _xtensa_context_save: #endif #if XTENSA_EXTRA_SA_SIZE > 0 || !defined(CONFIG_XTENSA_CALL0_ABI) - mov a9, a0 /* Preserve ret addr */ + mov a9, a0 /* Preserve ret addr */ #endif #ifndef CONFIG_XTENSA_CALL0_ABI @@ -171,7 +171,7 @@ _xtensa_context_save: * disabled (assured by PS.EXCM == 1). */ - s32i a12, a2, (4 * REG_TMP0) /* Temp. save stuff in stack frame */ + s32i a12, a2, (4 * REG_TMP0) /* Temp. save stuff in stack frame */ s32i a13, a2, (4 * REG_TMP1) s32i a9, a2, (4 * REG_TMP2) @@ -181,9 +181,9 @@ _xtensa_context_save: */ #ifdef CONFIG_XTENSA_USE_OVLY - l32i a9, a2, (4 * REG_PC) /* Recover saved PC */ + l32i a9, a2, (4 * REG_PC) /* Recover saved PC */ _xt_overlay_get_state a9, a12, a13 - s32i a9, a2, (4 * REG_OVLY) /* Save overlay state */ + s32i a9, a2, (4 * REG_OVLY) /* Save overlay state */ #endif l32i a12, a2, (4 * REG_A12) /* Recover original a9,12,13 */ diff --git a/arch/xtensa/src/common/xtensa_inthandlers.S b/arch/xtensa/src/common/xtensa_inthandlers.S index 817e458d50..32562b5834 100644 --- a/arch/xtensa/src/common/xtensa_inthandlers.S +++ b/arch/xtensa/src/common/xtensa_inthandlers.S @@ -167,12 +167,12 @@ l32i a6, a3, 4 /* a6 = _xt_vpri_mask */ neg a2, a2 addi a2, a2, -1 /* a2 = mask to apply */ - and a5, a6, a2 /* mask off all bits <= a4 bit */ - s32i a5, a3, 4 /* update _xt_vpri_mask */ + and a5, a6, a2 /* Mask off all bits <= a4 bit */ + s32i a5, a3, 4 /* Update _xt_vpri_mask */ rsr a3, INTENABLE - and a3, a3, a2 /* mask off all bits <= a4 bit */ + and a3, a3, a2 /* Mask off all bits <= a4 bit */ wsr a3, INTENABLE - rsil a3, \level - 1 /* lower interrupt level by 1 */ + rsil a3, \level - 1 /* Lower interrupt level by 1 */ #endif movi a3, XT_TIMER_INTEN /* a3 = timer interrupt bit */ @@ -226,7 +226,7 @@ #ifdef CONFIG_XTENSA_USE_SWPRI j 8f #else - j .L_xt_user_int_&level& /* check for more interrupts */ + j .L_xt_user_int_&level& /* Check for more interrupts */ #endif #ifdef CONFIG_XTENSA_USE_SWPRI @@ -237,9 +237,9 @@ movi a3, _xt_intdata l32i a4, a3, 0 /* a4 = _xt_intenable */ - s32i a2, a3, 4 /* update _xt_vpri_mask */ + s32i a2, a3, 4 /* Update _xt_vpri_mask */ and a4, a4, a2 /* a4 = masked intenable */ - wsr a4, INTENABLE /* update INTENABLE */ + wsr a4, INTENABLE /* Update INTENABLE */ #endif 9: @@ -498,7 +498,7 @@ _xtensa_level5_handler: * ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE. */ - rsr a0, EXCSAVE_5 /* restore a0 */ + rsr a0, EXCSAVE_5 /* Restore a0 */ rfi 5 #endif /* XCHAL_INT_NLEVELS >=5 && XCHAL_EXCM_LEVEL < 5 && XCHAL_DEBUGLEVEL !=5 */ diff --git a/arch/xtensa/src/common/xtensa_irq.S b/arch/xtensa/src/common/xtensa_irq.S index d601d6d9ce..9244a42052 100644 --- a/arch/xtensa/src/common/xtensa_irq.S +++ b/arch/xtensa/src/common/xtensa_irq.S @@ -30,6 +30,8 @@ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ****************************************************************************/ + .file "xtensa_irq.S" + /**************************************************************************** * Included Files ****************************************************************************/ diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index c9f4ea0ae3..5ec3886f99 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -80,7 +80,7 @@ CHIP_CSRCS = esp32_allocateheap.c esp32_intdecode.c esp32_start.c # Configuration-dependent ESP32 files ifeq ($(CONFIG_SMP),y) -#CMN_CSRCS += esp32_cpuindex.c esp32_cpustart.c esp32_cpupause.c -#CMN_CSRCS += esp32_cpuidlestack.c +CHIP_ASRCS = esp32_cpuindex.S +#CMN_CSRCS += esp32_cpustart.c esp32_cpupause.c esp32_cpuidlestack.c CMN_CSRCS += esp32_cpustart.c endif diff --git a/arch/xtensa/src/esp32/esp32_cpuindex.S b/arch/xtensa/src/esp32/esp32_cpuindex.S new file mode 100644 index 0000000000..0059f256e2 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_cpuindex.S @@ -0,0 +1,76 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/exp32_cpuindex.S + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + + .file "xtensa_cpumacros.S" + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "chip_macros.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_cpu_index + * + * Description: + * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + * If TLS is enabled, then the RTOS can get this information from the TLS + * info structure. Otherwise, the MCU-specific logic must provide some + * mechanism to provide the CPU index. + * + * Input Parameters: + * None + * + * Returned Value: + * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + ****************************************************************************/ + + .text + .align 4 + .global up_cpu_index + .type up_cpu_index, @function + +up_cpu_index: + getcoreid a2 + ret + .size up_cpu_index, . - up_cpu_index -- GitLab From aac8634de2ee4f6f8d82172c97ec651e51097662 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 22 Oct 2016 10:12:10 -0600 Subject: [PATCH 172/734] ctype.h: Correct some dangling garbage from the last change --- include/ctype.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/ctype.h b/include/ctype.h index 49cc47f030..9138a97f4c 100644 --- a/include/ctype.h +++ b/include/ctype.h @@ -318,7 +318,6 @@ static inline int tolower(int c) #else # define tolower(c) \ (((c) >= 'A' && (c) <= 'Z') ? ((c) - 'A' + 'a') : (c)) -# define #endif /**************************************************************************** -- GitLab From 23b003c6496ebb17c8baae55939cea155fcbed4e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 22 Oct 2016 12:25:56 -0600 Subject: [PATCH 173/734] Xtensa: Some things in Kconfig are really core options, not user configurations. --- arch/xtensa/Kconfig | 11 ++++++----- arch/xtensa/src/common/xtensa_context.S | 18 +++--------------- configs/esp32-core/nsh/defconfig | 4 ++-- 3 files changed, 11 insertions(+), 22 deletions(-) diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 9b08f38d12..c211140c9c 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -35,10 +35,6 @@ config XTENSA_NCOPROCESSORS int "Number of co-processors" default 1 -config XTENSA_HAVE_INTERRUPTS - bool - default n - config XTENSA_USE_SWPRI bool "Use SWPRI" default n @@ -46,10 +42,15 @@ config XTENSA_USE_SWPRI config XTENSA_CALL0_ABI bool "CALL0 ABI" default y + ---help--- + The Window ABI is not supported. Only the CALL0 ABI is supported in the + current implementation. config XTENSA_USE_OVLY - bool "Use overlay" + bool default n + ---help--- + Enable code overlay support. This option is currently unsupported. config ARCH_CHIP string diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index 37cdb796fd..db9ce31b71 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -65,10 +65,6 @@ #include "xtensa_specregs.h" -#ifdef CONFIG_XTENSA_USE_OVLY -# include -#endif - #warning REVIST XTENSA_EXTRA_SA_SIZE is not yet provided #define XTENSA_EXTRA_SA_SIZE 0 /* REMOVE ME */ @@ -175,15 +171,13 @@ _xtensa_context_save: s32i a13, a2, (4 * REG_TMP1) s32i a9, a2, (4 * REG_TMP2) +#ifdef CONFIG_XTENSA_USE_OVLY /* Save the overlay state if we are supporting overlays. Since we just * saved three registers, we can conveniently use them here. Note that * as of now, overlays only work for windowed calling ABI. */ -#ifdef CONFIG_XTENSA_USE_OVLY - l32i a9, a2, (4 * REG_PC) /* Recover saved PC */ - _xt_overlay_get_state a9, a12, a13 - s32i a9, a2, (4 * REG_OVLY) /* Save overlay state */ +#error Overly support is not implemented #endif l32i a12, a2, (4 * REG_A12) /* Recover original a9,12,13 */ @@ -356,13 +350,7 @@ _xtensa_context_restore: * to be restored. */ - l32i a2, a2, (4 * REG_PC) /* Retrieve PC */ - l32i a3, a2, (4 * REG_PS) /* Retrieve PS */ - l32i a4, a2, (4 * REG_OVLY) /* Retrieve overlay state */ - l32i a5, a2, (4 * REG_A1) /* Retrieve stack ptr */ - _xt_overlay_check_map a2, a3, a4, a5, a6 - s32i a2, a2, (4 * REG_PC) /* Save updated PC */ - s32i a3, a2, (4 * REG_PS) /* Save updated PS */ +#error Overly support is not implemented #endif #ifdef CONFIG_XTENSA_USE_SWPRI diff --git a/configs/esp32-core/nsh/defconfig b/configs/esp32-core/nsh/defconfig index 67a5268ab1..f78400225a 100644 --- a/configs/esp32-core/nsh/defconfig +++ b/configs/esp32-core/nsh/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_FAMILY_LX6=y CONFIG_XTENSA_NCOPROCESSORS=1 -CONFIG_XTENSA_HAVE_INTERRUPTS=y # CONFIG_XTENSA_USE_SWPRI is not set CONFIG_XTENSA_CALL0_ABI=y # CONFIG_XTENSA_USE_OVLY is not set @@ -537,6 +536,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -558,10 +558,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set -- GitLab From 41137b82fa1d3f6987d042d505202906bfd2c846 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 22 Oct 2016 13:02:55 -0600 Subject: [PATCH 174/734] Add strtold() --- include/stdlib.h | 14 +-- libc/stdlib/Make.defs | 2 +- libc/stdlib/lib_strtod.c | 8 +- libc/stdlib/lib_strtof.c | 4 - libc/stdlib/lib_strtold.c | 248 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 259 insertions(+), 17 deletions(-) create mode 100644 libc/stdlib/lib_strtold.c diff --git a/include/stdlib.h b/include/stdlib.h index 09eb2cf6c0..d10628ac41 100644 --- a/include/stdlib.h +++ b/include/stdlib.h @@ -80,13 +80,6 @@ # define environ get_environ_ptr() #endif -/* The function strtold() is not currently implemented in NuttX. Ideally, a - * custom implementation should be provided because, of course, there is a - * loss of 32-bits of accuracy in this conversion. - */ - -#define strtold(a,b) (long double)strtod(a,b) - /**************************************************************************** * Public Type Definitions ****************************************************************************/ @@ -197,8 +190,13 @@ long long strtoll(FAR const char *nptr, FAR char **endptr, int base); unsigned long long strtoull(FAR const char *nptr, FAR char **endptr, int base); #endif -double_t strtod(FAR const char *str, FAR char **endptr); float strtof(FAR const char *str, FAR char **endptr); +#ifdef CONFIG_HAVE_DOUBLE +double strtod(FAR const char *str, FAR char **endptr); +#endif +#ifdef CONFIG_HAVE_LONG_DOUBLE +long double strtold(FAR const char *str, FAR char **endptr); +#endif #define atoi(nptr) ((int)strtol((nptr), NULL, 10)) #define atol(nptr) strtol((nptr), NULL, 10) diff --git a/libc/stdlib/Make.defs b/libc/stdlib/Make.defs index d08a0bb434..ec3977575d 100644 --- a/libc/stdlib/Make.defs +++ b/libc/stdlib/Make.defs @@ -39,7 +39,7 @@ CSRCS += lib_abs.c lib_abort.c lib_div.c lib_ldiv.c lib_lldiv.c CSRCS += lib_imaxabs.c lib_itoa.c lib_labs.c lib_llabs.c CSRCS += lib_bsearch.c lib_rand.c lib_qsort.c lib_srand.c CSRCS += lib_strtol.c lib_strtoll.c lib_strtoul.c lib_strtoull.c -CSRCS += lib_strtod.c lib_strtof.c lib_checkbase.c +CSRCS += lib_strtod.c lib_strtof.c lib_strtold.c lib_checkbase.c ifeq ($(CONFIG_FS_WRITABLE),y) CSRCS += lib_mktemp.c lib_mkstemp.c diff --git a/libc/stdlib/lib_strtod.c b/libc/stdlib/lib_strtod.c index 7d8d08b532..16d0dd331a 100644 --- a/libc/stdlib/lib_strtod.c +++ b/libc/stdlib/lib_strtod.c @@ -71,7 +71,7 @@ static inline int is_real(double x) { - const double_t infinite = 1.0/0.0; + const double infinite = 1.0/0.0; return (x < infinite) && (x >= -infinite); } @@ -87,9 +87,9 @@ static inline int is_real(double x) * ****************************************************************************/ -double_t strtod(FAR const char *str, FAR char **endptr) +double strtod(FAR const char *str, FAR char **endptr) { - double_t number; + double number; int exponent; int negative; FAR char *p = (FAR char *) str; @@ -97,7 +97,7 @@ double_t strtod(FAR const char *str, FAR char **endptr) int n; int num_digits; int num_decimals; - const double_t infinite = 1.0/0.0; + const double infinite = 1.0/0.0; /* Skip leading whitespace */ diff --git a/libc/stdlib/lib_strtof.c b/libc/stdlib/lib_strtof.c index f081db0ad4..6c19d6d285 100644 --- a/libc/stdlib/lib_strtof.c +++ b/libc/stdlib/lib_strtof.c @@ -48,8 +48,6 @@ #include #include -#ifdef CONFIG_HAVE_DOUBLE - /**************************************************************************** * Pre-processor definitions ****************************************************************************/ @@ -248,5 +246,3 @@ errout: return number; } - -#endif /* CONFIG_HAVE_DOUBLE */ diff --git a/libc/stdlib/lib_strtold.c b/libc/stdlib/lib_strtold.c new file mode 100644 index 0000000000..b0d10399f9 --- /dev/null +++ b/libc/stdlib/lib_strtold.c @@ -0,0 +1,248 @@ +/**************************************************************************** + * libc/stdlib/lib_strtod.c + * Convert string to long double + * + * Copyright (C) 2002 Michael Ringgaard. All rights reserved. + * Copyright (C) 2006-2007 H. Peter Anvin. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the project nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#ifdef CONFIG_HAVE_LONG_DOUBLE + +/**************************************************************************** + * Pre-processor definitions + ****************************************************************************/ + +/* These are predefined with GCC, but could be issues for other compilers. If + * not defined, an arbitrary big number is put in for now. These should be + * added to nuttx/compiler for your compiler. + */ + +#if !defined(__LDBL_MIN_EXP__) || !defined(__LDBL_MAX_EXP__) +# ifdef CONFIG_CPP_HAVE_WARNING +# warning "Size of exponent is unknown" +# endif +# undef __LDBL_MIN_EXP__ +# define __LDBL_MIN_EXP__ (-1021) +# undef __LDBL_MAX_EXP__ +# define __LDBL_MAX_EXP__ (1024) +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline int is_real(long double x) +{ + const long double infinite = 1.0L/0.0L; + return (x < infinite) && (x >= -infinite); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/***************************************************(************************ + * Name: strtold + * + * Description: + * Convert a string to a long double value + * + ****************************************************************************/ + +long double strtold(FAR const char *str, FAR char **endptr) +{ + long double number; + int exponent; + int negative; + FAR char *p = (FAR char *) str; + long double p10; + int n; + int num_digits; + int num_decimals; + const long double infinite = 1.0L/0.0L; + + /* Skip leading whitespace */ + + while (isspace(*p)) + { + p++; + } + + /* Handle optional sign */ + + negative = 0; + switch (*p) + { + case '-': + negative = 1; /* Fall through to increment position */ + case '+': + p++; + default: + break; + } + + number = 0.0L; + exponent = 0; + num_digits = 0; + num_decimals = 0; + + /* Process string of digits */ + + while (isdigit(*p)) + { + number = number * 10.0L + (long double)(*p - '0'); + p++; + num_digits++; + } + + /* Process decimal part */ + + if (*p == '.') + { + p++; + + while (isdigit(*p)) + { + number = number * 10.0L + (long double)(*p - '0'); + p++; + num_digits++; + num_decimals++; + } + + exponent -= num_decimals; + } + + if (num_digits == 0) + { + set_errno(ERANGE); + number = 0.0L; + goto errout; + } + + /* Correct for sign */ + + if (negative) + { + number = -number; + } + + /* Process an exponent string */ + + if (*p == 'e' || *p == 'E') + { + /* Handle optional sign */ + + negative = 0; + switch (*++p) + { + case '-': + negative = 1; /* Fall through to increment pos */ + case '+': + p++; + default: + break; + } + + /* Process string of digits */ + + n = 0; + while (isdigit(*p)) + { + n = n * 10 + (*p - '0'); + p++; + } + + if (negative) + { + exponent -= n; + } + else + { + exponent += n; + } + } + + if (exponent < __LDBL_MIN_EXP__ || + exponent > __LDBL_MAX_EXP__) + { + set_errno(ERANGE); + number = infinite; + goto errout; + } + + /* Scale the result */ + + p10 = 10.; + n = exponent; + if (n < 0) n = -n; + while (n) + { + if (n & 1) + { + if (exponent < 0) + { + number /= p10; + } + else + { + number *= p10; + } + } + + n >>= 1; + p10 *= p10; + } + + if (!is_real(number)) + { + set_errno(ERANGE); + } + +errout: + if (endptr) + { + *endptr = p; + } + + return number; +} + +#endif /* CONFIG_HAVE_LONG_DOUBLE */ -- GitLab From d08596a653f1bec8badd630a186f43d9af8a6715 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 22 Oct 2016 13:27:56 -0600 Subject: [PATCH 175/734] libc/stdlib: Fix a few minor coding style issues --- libc/stdlib/lib_strtod.c | 18 +++++++++++------- libc/stdlib/lib_strtof.c | 18 +++++++++++------- libc/stdlib/lib_strtold.c | 20 ++++++++++++-------- 3 files changed, 34 insertions(+), 22 deletions(-) diff --git a/libc/stdlib/lib_strtod.c b/libc/stdlib/lib_strtod.c index 16d0dd331a..62da9e0f6e 100644 --- a/libc/stdlib/lib_strtod.c +++ b/libc/stdlib/lib_strtod.c @@ -140,12 +140,12 @@ double strtod(FAR const char *str, FAR char **endptr) p++; while (isdigit(*p)) - { - number = number * 10. + (*p - '0'); - p++; - num_digits++; - num_decimals++; - } + { + number = number * 10. + (*p - '0'); + p++; + num_digits++; + num_decimals++; + } exponent -= num_decimals; } @@ -212,7 +212,11 @@ double strtod(FAR const char *str, FAR char **endptr) p10 = 10.; n = exponent; - if (n < 0) n = -n; + if (n < 0) + { + n = -n; + } + while (n) { if (n & 1) diff --git a/libc/stdlib/lib_strtof.c b/libc/stdlib/lib_strtof.c index 6c19d6d285..467842f4e6 100644 --- a/libc/stdlib/lib_strtof.c +++ b/libc/stdlib/lib_strtof.c @@ -142,12 +142,12 @@ float strtof(FAR const char *str, FAR char **endptr) p++; while (isdigit(*p)) - { - number = number * 10.0F + (float)(*p - '0'); - p++; - num_digits++; - num_decimals++; - } + { + number = number * 10.0F + (float)(*p - '0'); + p++; + num_digits++; + num_decimals++; + } exponent -= num_decimals; } @@ -214,7 +214,11 @@ float strtof(FAR const char *str, FAR char **endptr) p10 = 10.0F; n = exponent; - if (n < 0) n = -n; + if (n < 0) + { + n = -n; + } + while (n) { if (n & 1) diff --git a/libc/stdlib/lib_strtold.c b/libc/stdlib/lib_strtold.c index b0d10399f9..c306392cec 100644 --- a/libc/stdlib/lib_strtold.c +++ b/libc/stdlib/lib_strtold.c @@ -140,12 +140,12 @@ long double strtold(FAR const char *str, FAR char **endptr) p++; while (isdigit(*p)) - { - number = number * 10.0L + (long double)(*p - '0'); - p++; - num_digits++; - num_decimals++; - } + { + number = number * 10.0L + (long double)(*p - '0'); + p++; + num_digits++; + num_decimals++; + } exponent -= num_decimals; } @@ -210,9 +210,13 @@ long double strtold(FAR const char *str, FAR char **endptr) /* Scale the result */ - p10 = 10.; + p10 = 10.0L; n = exponent; - if (n < 0) n = -n; + if (n < 0) + { + n = -n; + } + while (n) { if (n & 1) -- GitLab From 177239feae1d313c10719684eb3f0ace15e0d29a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 22 Oct 2016 13:42:43 -0600 Subject: [PATCH 176/734] sscanf: Use strtof() instead of strtod() if a short floating point value was requested. The should help performance with MCUs with 32-bit FPU support --- libc/stdio/lib_sscanf.c | 51 ++++++++++++++++++++++++++++------------- 1 file changed, 35 insertions(+), 16 deletions(-) diff --git a/libc/stdio/lib_sscanf.c b/libc/stdio/lib_sscanf.c index 50bcd8956e..0bc413295b 100644 --- a/libc/stdio/lib_sscanf.c +++ b/libc/stdio/lib_sscanf.c @@ -511,9 +511,9 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) else if (strchr("aAfFeEgG", *fmt) != NULL) { #ifdef CONFIG_HAVE_DOUBLE - FAR double_t *pd = NULL; + FAR double *pd = NULL; #endif - FAR float *pf = NULL; + FAR float *pf = NULL; linfo("vsscanf: Performing floating point conversion\n"); @@ -531,7 +531,7 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) #ifdef CONFIG_HAVE_DOUBLE if (lflag) { - pd = va_arg(ap, FAR double_t *); + pd = va_arg(ap, FAR double *); *pd = 0.0; } else @@ -581,22 +581,11 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) FAR char *endptr; int errsave; - double_t dvalue; /* Preserve the errno value */ errsave = get_errno(); set_errno(0); - dvalue = strtod(tmp, &endptr); - - /* Check if the number was successfully converted */ - - if (tmp == endptr || get_errno() == ERANGE) - { - return count; - } - - set_errno(errsave); /* We have to check whether we need to return a float * or a double. @@ -605,14 +594,44 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) #ifdef CONFIG_HAVE_DOUBLE if (lflag) { + /* Get the converted double value */ + + double dvalue = strtod(tmp, &endptr); + + /* Check if the number was successfully converted */ + + if (tmp == endptr || get_errno() == ERANGE) + { + return count; + } + + set_errno(errsave); + + /* Return the double value */ + linfo("vsscanf: Return %f to %p\n", dvalue, pd); *pd = dvalue; } else #endif { - linfo("vsscanf: Return %f to %p\n", dvalue, pf); - *pf = (float)dvalue; + /* Get the converted float value */ + + float fvalue = strtof(tmp, &endptr); + + /* Check if the number was successfully converted */ + + if (tmp == endptr || get_errno() == ERANGE) + { + return count; + } + + set_errno(errsave); + + /* Return the float value */ + + linfo("vsscanf: Return %f to %p\n", (double)fvalue, pf); + *pf = fvalue; } count++; -- GitLab From 2c83d79465f50127e531543b714d4e58eeee94b8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 23 Oct 2016 06:24:35 -0600 Subject: [PATCH 177/734] Xtensa: Remove 'virtual' interrupt support --- arch/xtensa/include/irq.h | 4 +- arch/xtensa/src/common/xtensa_inthandlers.S | 2 +- arch/xtensa/src/common/xtensa_irq.S | 150 -------------------- arch/xtensa/src/esp32/Make.defs | 2 +- arch/xtensa/src/esp32/chip/esp32_soc.h | 4 +- 5 files changed, 6 insertions(+), 156 deletions(-) delete mode 100644 arch/xtensa/src/common/xtensa_irq.S diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index ae7e71ec37..7bfd3ebdcb 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -129,8 +129,8 @@ #ifdef CONFIG_XTENSA_USE_OVLY /* Storage for overlay state */ -# define REG_OVLY (_REG_OVLY_START + 0) -# define XCPTCONTEXT_REGS (_REG_OVLY_START + 1) +# error Overlays not supported +# define XCPTCONTEXT_REGS _REG_OVLY_START #else # define XCPTCONTEXT_REGS _REG_OVLY_START #endif diff --git a/arch/xtensa/src/common/xtensa_inthandlers.S b/arch/xtensa/src/common/xtensa_inthandlers.S index 32562b5834..1b16559d30 100644 --- a/arch/xtensa/src/common/xtensa_inthandlers.S +++ b/arch/xtensa/src/common/xtensa_inthandlers.S @@ -294,7 +294,7 @@ _xtensa_level2_handler: rsr a0, EXCSAVE_2 /* Save interruptee's a0 */ s32i a0, sp, (4 * REG_A0) - /* Save rest of interrupt context and enter RTOS. */ + /* Save rest of interrupt context. */ s32i a2, sp, (4 * REG_A2) movi a2, sp /* Address of state save on stack */ diff --git a/arch/xtensa/src/common/xtensa_irq.S b/arch/xtensa/src/common/xtensa_irq.S deleted file mode 100644 index 9244a42052..0000000000 --- a/arch/xtensa/src/common/xtensa_irq.S +++ /dev/null @@ -1,150 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/common/xtensa_irq.S - * - * Adapted from use in NuttX by: - * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Derives from logic originally provided by Cadence Design Systems Inc. - * - * Copyright (c) 2006-2015 Cadence Design Systems Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - ****************************************************************************/ - - .file "xtensa_irq.S" - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "xtensa_specregs.h" -#include "xtensa_macros.h" - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef CONFIG_XCHAL_HAVE_INTERRUPTS - -/* INTENABLE virtualization information. */ - - .data - .global _xtensa_intdata - .align 8 -_xtensa_intdata: - - .global _xtensa_intenable - .type _xtensa_intenable, @object -_xtensa_intenable: - .word 0 /* Virtual INTENABLE */ - .size _xtensa_intenable,4 - - .global _xtensa_vprimask - .type _xtensa_vprimask, @object -_xtensa_vprimask: - .word 0xffffffff /* Virtual priority mask */ - .size _xtensa_vprimask, 4 - -#endif /* CONFIG_XCHAL_HAVE_INTERRUPTS */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * C Prototype: - * irqstate_t xtensa_enable_interrupts(irqstate_t mask) - * - * Description: - * Enables a set of interrupts. Does not simply set INTENABLE directly, - * but computes it as a function of the current virtual priority. - * Can be called from interrupt handlers. - * - ****************************************************************************/ - - .text - .align 4 - .global xtensa_enable_interrupts - .type xtensa_enable_interrupts, @function - -xtensa_enable_interrupts: - - ENTRY0 -#ifdef CONFIG_XCHAL_HAVE_INTERRUPTS - movi a3, 0 - movi a4, _xtensa_intdata - xsr a3, INTENABLE /* Disables all interrupts */ - rsync - l32i a3, a4, 0 /* a3 = _xtensa_intenable */ - l32i a6, a4, 4 /* a6 = _xtensa_vprimask */ - or a5, a3, a2 /* a5 = _xtensa_intenable | mask */ - s32i a5, a4, 0 /* _xtensa_intenable |= mask */ - and a5, a5, a6 /* a5 = _xtensa_intenable & _xtensa_vprimask */ - wsr a5, INTENABLE /* Reenable interrupts */ - mov a2, a3 /* Previous mask */ -#else - movi a2, 0 /* Return zero */ -#endif - RET0 - - .size xtensa_enable_interrupts, . - xtensa_enable_interrupts - -/**************************************************************************** - * C Prototype: - * irqstate_t xtensa_disable_interrupts(irqstate_t mask) - * - * Description: - * Disables a set of interrupts. Does not simply set INTENABLE directly, - * but computes it as a function of the current virtual priority. - * Can be called from interrupt handlers. - * - ****************************************************************************/ - - .text - .align 4 - .global xtensa_disable_interrupts - .type xtensa_disable_interrupts,@function - -xtensa_disable_interrupts: - - ENTRY0 -#ifdef CONFIG_XCHAL_HAVE_INTERRUPTS - movi a3, 0 - movi a4, _xtensa_intdata - xsr a3, INTENABLE /* Disables all interrupts */ - rsync - l32i a3, a4, 0 /* a3 = _xtensa_intenable */ - l32i a6, a4, 4 /* a6 = _xtensa_vprimask */ - or a5, a3, a2 /* a5 = _xtensa_intenable | mask */ - xor a5, a5, a2 /* a5 = _xtensa_intenable & ~mask */ - s32i a5, a4, 0 /* _xtensa_intenable &= ~mask */ - and a5, a5, a6 /* a5 = _xtensa_intenable & _xtensa_vprimask */ - wsr a5, INTENABLE /* Reenable interrupts */ - mov a2, a3 /* Previous mask */ -#else - movi a2, 0 /* return zero */ -#endif - RET0 - - .size xtensa_disable_interrupts, . - xtensa_disable_interrupts diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 5ec3886f99..fea64934e1 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -40,7 +40,7 @@ HEAD_CSRC = esp32_start.c # Common XTENSA files (arch/xtensa/src/common) -CMN_ASRCS = xtensa_context.S xtensa_irq.S xtensa_intvectors.S +CMN_ASRCS = xtensa_context.S xtensa_intvectors.S CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c CMN_CSRCS += xtensa_createstack.c xtensa_exit.c xtensa_idle.c CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c diff --git a/arch/xtensa/src/esp32/chip/esp32_soc.h b/arch/xtensa/src/esp32/chip/esp32_soc.h index 6760b1509e..20405c067d 100644 --- a/arch/xtensa/src/esp32/chip/esp32_soc.h +++ b/arch/xtensa/src/esp32/chip/esp32_soc.h @@ -308,7 +308,7 @@ * 3 1 extern level TG0_WDT Reserved * 4 1 extern level WBB * 5 1 extern level BT Controller - * 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1) + * 6 1 timer RTOS Tick RTOS Tick * 7 1 software Reserved Reserved * 8 1 extern level BLE Controller * 9 1 extern level @@ -317,7 +317,7 @@ * 12 1 extern level * 13 1 extern level * 14 7 nmi Reserved Reserved - * 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3) + * 15 3 timer Internal Timer * 16 5 timer * 17 1 extern level * 18 1 extern level -- GitLab From 75df09fd408df41927c702893e98b07335273406 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 23 Oct 2016 06:37:28 -0600 Subject: [PATCH 178/734] Remove support for software prioritization of interrupts --- arch/xtensa/Kconfig | 4 -- arch/xtensa/include/irq.h | 13 +---- arch/xtensa/src/common/xtensa_context.S | 19 ------- arch/xtensa/src/common/xtensa_dumpstate.c | 4 -- arch/xtensa/src/common/xtensa_initialstate.c | 6 --- arch/xtensa/src/common/xtensa_inthandlers.S | 55 +++----------------- 6 files changed, 8 insertions(+), 93 deletions(-) diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index c211140c9c..7d6ab3d343 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -35,10 +35,6 @@ config XTENSA_NCOPROCESSORS int "Number of co-processors" default 1 -config XTENSA_USE_SWPRI - bool "Use SWPRI" - default n - config XTENSA_CALL0_ABI bool "CALL0 ABI" default y diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index 7bfd3ebdcb..60d6af4758 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -112,18 +112,9 @@ # define REG_TMP0 (_REG_CALL0_START + 0) # define REG_TMP1 (_REG_CALL0_START + 1) # define REG_TMP2 (_REG_CALL0_START + 2) -# define _REG_SWPRI_START (_REG_CALL0_START + 3) +# define _REG_OVLY_START (_REG_CALL0_START + 3) #else -# define _REG_SWPRI_START _REG_CALL0_START -#endif - -#ifdef CONFIG_XTENSA_USE_SWPRI - /* Storage for virtual priority mask */ - -# define REG_VPRI (_REG_SWPRI_START + 0) -# define _REG_OVLY_START (_REG_SWPRI_START + 1) -#else -# define _REG_OVLY_START _REG_SWPRI_START +# define _REG_OVLY_START _REG_CALL0_START #endif #ifdef CONFIG_XTENSA_USE_OVLY diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index db9ce31b71..70dcf673be 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -147,14 +147,6 @@ _xtensa_context_save: s32i a3, a2, (4 * REG_LCOUNT) #endif -#ifdef CONFIG_XTENSA_USE_SWPRI - /* Save virtual priority mask */ - - movi a3, _xtensa_vprimask - l32i a3, a3, 0 - s32i a3, a2, (4 * REG_VPRI) -#endif - #if XTENSA_EXTRA_SA_SIZE > 0 || !defined(CONFIG_XTENSA_CALL0_ABI) mov a9, a0 /* Preserve ret addr */ #endif @@ -353,17 +345,6 @@ _xtensa_context_restore: #error Overly support is not implemented #endif -#ifdef CONFIG_XTENSA_USE_SWPRI - /* Restore virtual interrupt priority and interrupt enable */ - - movi a3, _xtensa_intdata - l32i a4, a3, 0 /* a4 = _xtensa_intenable */ - l32i a5, a2, (4 * REG_VPRI) /* a5 = saved _xtensa_vprimask */ - and a4, a4, a5 - wsr a4, INTENABLE /* Update INTENABLE */ - s32i a5, a3, 4 /* Restore _xtensa_vprimask */ - #endif - l32i a3, a2, (4 * REG_SAR) l32i sp, a2, (4 * REG_A1) wsr a3, SAR diff --git a/arch/xtensa/src/common/xtensa_dumpstate.c b/arch/xtensa/src/common/xtensa_dumpstate.c index 8c8cea3bf9..74de6d74a5 100644 --- a/arch/xtensa/src/common/xtensa_dumpstate.c +++ b/arch/xtensa/src/common/xtensa_dumpstate.c @@ -127,10 +127,6 @@ static inline void xtensa_registerdump(void) _alert(" TMP0: %08lx TMP1: %08lx TMP2: %08lx\n", (unsigned long)regs[REG_TMP0], (unsigned long)regs[REG_TMP1], (unsigned long)regs[REG_TMP2]); -#endif -#ifdef CONFIG_XTENSA_USE_SWPRI - _alert(" VPRI: %08lx\n", - (unsigned long)regs[REG_VPRI]); #endif } } diff --git a/arch/xtensa/src/common/xtensa_initialstate.c b/arch/xtensa/src/common/xtensa_initialstate.c index dab7af55cd..9bea96d7da 100644 --- a/arch/xtensa/src/common/xtensa_initialstate.c +++ b/arch/xtensa/src/common/xtensa_initialstate.c @@ -99,12 +99,6 @@ void up_initial_state(struct tcb_s *tcb) xcp->regs[REG_PS] = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1); #endif -#ifdef CONFIG_XTENSA_USE_SWPRI - /* Set the initial virtual priority mask value to all 1's. */ - - xcp->regs[REG_VPRI] = 0xffffffff; -#endif - #warning REVISIT co-processor support #if 0 /* REVISIT */ #if CONFIG_XTENSA_NCOPROCESSORS > 0 diff --git a/arch/xtensa/src/common/xtensa_inthandlers.S b/arch/xtensa/src/common/xtensa_inthandlers.S index 1b16559d30..4547ccbaee 100644 --- a/arch/xtensa/src/common/xtensa_inthandlers.S +++ b/arch/xtensa/src/common/xtensa_inthandlers.S @@ -114,7 +114,7 @@ movi a4, \mask and a2, a2, a3 and a2, a2, a4 - beqz a2, 9f /* Nothing to do */ + beqz a2, 5f /* Nothing to do */ /* This bit of code provides a nice debug backtrace in the debugger. * It does take a few more instructions, so undef XT_DEBUG_BACKTRACE @@ -139,11 +139,11 @@ #ifdef CONFIG_XTENSA_CALL0_ABI callx0 a4 - beqz a2, 9f + beqz a2, 5f #else mov a6, a2 callx4 a4 - beqz a6, 9f + beqz a6, 5f mov a2, a6 #endif 2: @@ -153,31 +153,9 @@ extract_msb a4, a2 /* a4 = MSB of a2, a2 trashed */ -#ifdef CONFIG_XTENSA_USE_SWPRI - /* Enable all interrupts at this level that are numerically higher - * than the one we just selected, since they are treated as higher - * priority. - */ - - movi a3, \mask /* a3 = all interrupts at this level */ - add a2, a4, a4 /* a2 = a4 << 1 */ - addi a2, a2, -1 /* a2 = mask of 1's <= a4 bit */ - and a2, a2, a3 /* a2 = mask of all bits <= a4 at this level */ - movi a3, _xt_intdata - l32i a6, a3, 4 /* a6 = _xt_vpri_mask */ - neg a2, a2 - addi a2, a2, -1 /* a2 = mask to apply */ - and a5, a6, a2 /* Mask off all bits <= a4 bit */ - s32i a5, a3, 4 /* Update _xt_vpri_mask */ - rsr a3, INTENABLE - and a3, a3, a2 /* Mask off all bits <= a4 bit */ - wsr a3, INTENABLE - rsil a3, \level - 1 /* Lower interrupt level by 1 */ -#endif - movi a3, XT_TIMER_INTEN /* a3 = timer interrupt bit */ wsr a4, INTCLEAR /* Clear sw or edge-triggered interrupt */ - beq a3, a4, 7f /* If timer interrupt then skip table */ + beq a3, a4, 4f /* If timer interrupt then skip table */ /* Call xtensa_int_decode with, passing that address of the register save * area as a parameter (A2). @@ -201,13 +179,9 @@ addi sp, a4, -(4 * XCPTCONTEXT_SIZE) 3: -#ifdef CONFIG_XTENSA_USE_SWPRI - j 8f -#else j .L_xt_user_int_&level& /* Check for more interrupts */ -#endif -7: +4: .ifeq XT_TIMER_INTPRI - \level @@ -223,26 +197,9 @@ mov a6, a12 /* Preserve a6 */ .endif -#ifdef CONFIG_XTENSA_USE_SWPRI - j 8f -#else j .L_xt_user_int_&level& /* Check for more interrupts */ -#endif - -#ifdef CONFIG_XTENSA_USE_SWPRI -8: - /* Restore old value of _xt_vpri_mask from a2. Also update INTENABLE from - virtual _xt_intenable which _could_ have changed during interrupt - processing. */ - - movi a3, _xt_intdata - l32i a4, a3, 0 /* a4 = _xt_intenable */ - s32i a2, a3, 4 /* Update _xt_vpri_mask */ - and a4, a4, a2 /* a4 = masked intenable */ - wsr a4, INTENABLE /* Update INTENABLE */ -#endif -9: +5: /* done */ .endm -- GitLab From ea175cd98babb88687a97228c1faa62237c3ac53 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 23 Oct 2016 07:08:19 -0600 Subject: [PATCH 179/734] Xtensa: Flesh out other interrupt handlers. Suppress nested interrupts, at least for now. --- arch/xtensa/src/common/xtensa_inthandlers.S | 328 ++++++++++++++++++-- 1 file changed, 305 insertions(+), 23 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_inthandlers.S b/arch/xtensa/src/common/xtensa_inthandlers.S index 4547ccbaee..de9d1d2a98 100644 --- a/arch/xtensa/src/common/xtensa_inthandlers.S +++ b/arch/xtensa/src/common/xtensa_inthandlers.S @@ -43,11 +43,11 @@ * This allows more flexibility in locating code without the performance * overhead of the 'l32r' literal data load in cases where the destination * is in range of 'call0'. There is an additional benefit in that 'call0' - * has a longer range than 'j' due to the target being word-aligned, so + * has a longer range than 'j' due to the target being word-aligned, so * the 'l32r' sequence is less likely needed. * - * 3. The use of 'call0' with -mlongcalls requires that register a0 not be - * live at the time of the call, which is always the case for a function + * 3. The use of 'call0' with -mlongcalls requires that register a0 not be + * live at the time of the call, which is always the case for a function * call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'. * * 4. This use of 'call0' is independent of the C function call ABI. @@ -70,12 +70,16 @@ * Assembly Language Macros ****************************************************************************/ -/* Macro extract_msb - return the input with only the highest bit set. +/**************************************************************************** + * Macro extract_msb - return the input with only the highest bit set. + * + * Entry Conditions/Side Effects: + * Input : "ain" - Input value, clobbered. + * Output : "aout" - Output value, has only one bit set, MSB of "ain". * - * Input : "ain" - Input value, clobbered. - * Output : "aout" - Output value, has only one bit set, MSB of "ain". * The two arguments must be different AR registers. - */ + * + ****************************************************************************/ .macro extract_msb aout ain 1: @@ -85,7 +89,11 @@ addi \aout, \aout, 1 /* Return aout + 1 */ .endm -/* Macro dispatch_c_isr - dispatch interrupts to user ISRs. +/**************************************************************************** + * Macro dispatch_c_isr level mask + * + * Description: + * * This will dispatch to user handlers (if any) that are registered in the * XTOS dispatch table (_xtos_interrupt_table). These handlers would have * been registered by calling _xtos_set_interrupt_handler(). There is one @@ -95,14 +103,16 @@ * Level triggered and software interrupts are automatically deasserted by * this code. * - * ASSUMPTIONS: + * Assumptions: * - PS.INTLEVEL is set to "level" at entry * - PS.EXCM = 0, C calling enabled * - * NOTE: This macro will use registers a0 and a2-a6. The arguments are: - * level -- interrupt level - * mask -- interrupt bitmask for this level - */ + * Entry Conditions/Side Effects: + * This macro will use registers a0 and a2-a6. The arguments are: + * level - interrupt level + * mask - interrupt bitmask for this level + * + ****************************************************************************/ .macro dispatch_c_isr level mask @@ -204,12 +214,63 @@ .endm +/**************************************************************************** + * Macro: ps_setup + * + * Description: + * Set up PS for C, enable interrupts above this level and clear EXCM. + * + * Entry Conditions: + * level - interrupt level + * tmp - scratch register + * + * Side Effects: + * PS and scratch register modified + * + * Assumptions: + * - PS.EXCM = 1, C calling disabled + * + ****************************************************************************/ + + .macro ps_setup level tmp + +#if 0 /* Nested interrupts no yet supported */ +# ifdef CONFIG_XTENSA_CALL0_ABI + /* Disable interrupts at level and below */ + + movi \tmp, PS_INTLEVEL(\level) | PS_UM +# else + movi \tmp, PS_INTLEVEL(\level) | PS_UM | PS_WOE +# endif +#else +# ifdef CONFIG_XTENSA_CALL0_ABI + /* Disable all low- and medium-priority interrupts. Nested are not yet + * supported. + */ + + movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM +# else + movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE +# endif +#endif + + wsr \tmp, PS + rsync + + .endm + /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * MEDIUM PRIORITY (LEVEL 2+) INTERRUPT VECTORS AND LOW LEVEL HANDLERS. + * LOW PRIORITY (LEVEL 1) LOW LEVEL HANDLER. + ****************************************************************************/ + +#warning REVISIT level 1 interrupt handlers + +/**************************************************************************** + * MEDIUM PRIORITY (LEVEL 2+) INTERRUPT LOW LEVEL HANDLERS. * * C Prototype: * void _xtensa_levelN_handler(void) @@ -259,13 +320,7 @@ _xtensa_level2_handler: /* Set up PS for C, enable interrupts above this level and clear EXCM. */ -#ifdef CONFIG_XTENSA_CALL0_ABI - movi a0, PS_INTLEVEL(2) | PS_UM - #else - movi a0, PS_INTLEVEL(2) | PS_UM | PS_WOE -#endif - wsr a0, PS - rsync + ps_setup 2 a0 /* Decode and dispatch the interrupt. In the event of an interrupt * level context dispatch_c_isr() will switch stacks to the new task's @@ -297,9 +352,236 @@ _xtensa_level2_handler: #endif /* XCHAL_EXCM_LEVEL >= 2 */ +#if XCHAL_EXCM_LEVEL >= 3 + .section .iram1,"ax" + .type _xtensa_level3_handler,@function + .align 4 + +_xtensa_level3_handler: + + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS_3 /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EPC_3 /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE_3 /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) + + /* Save rest of interrupt context. */ + + s32i a2, sp, (4 * REG_A2) + movi a2, sp /* Address of state save on stack */ + call0 _xtensa_context_save /* Save full register state */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + + ps_setup 3 a0 + + /* Decode and dispatch the interrupt. In the event of an interrupt + * level context dispatch_c_isr() will switch stacks to the new task's + * context save area. + */ + + dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK + + /* Restore registers in preparation to return from interrupt */ + + call0 _xtensa_context_restore + + /* Restore only level-specific regs (the rest were already restored) */ + + l32i a0, sp, (4 * REG_PS) /* Retrieve interruptee's PS */ + wsr a0, EPS_3 + l32i a0, sp, (4 * REG_PC) /* Retrieve interruptee's PC */ + wsr a0, EPC_3 + l32i a0, sp, (4 * REG_A0) /* Retrieve interruptee's A0 */ + l32i a2, sp, (4 * REG_A2) /* Retrieve interruptee's A2 */ + l32i sp, sp, (4 * REG_A1) /* Remove interrupt stack frame */ + rsync /* Ensure EPS and EPC written */ + + /* Return from interrupt. RFI restores the PS from EPS_3 and jumps to + * the address in EPC_3. + */ + + rfi 3 + +#endif /* XCHAL_EXCM_LEVEL >= 3 */ + +#if XCHAL_EXCM_LEVEL >= 4 + .section .iram1,"ax" + .type _xtensa_level4_handler,@function + .align 4 + +_xtensa_level4_handler: + + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS_4 /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EPC_4 /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE_4 /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) + + /* Save rest of interrupt context. */ + + s32i a2, sp, (4 * REG_A2) + movi a2, sp /* Address of state save on stack */ + call0 _xtensa_context_save /* Save full register state */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + + ps_setup 4 a0 + + /* Decode and dispatch the interrupt. In the event of an interrupt + * level context dispatch_c_isr() will switch stacks to the new task's + * context save area. + */ + + dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK + + /* Restore registers in preparation to return from interrupt */ + + call0 _xtensa_context_restore + + /* Restore only level-specific regs (the rest were already restored) */ + + l32i a0, sp, (4 * REG_PS) /* Retrieve interruptee's PS */ + wsr a0, EPS_4 + l32i a0, sp, (4 * REG_PC) /* Retrieve interruptee's PC */ + wsr a0, EPC_4 + l32i a0, sp, (4 * REG_A0) /* Retrieve interruptee's A0 */ + l32i a2, sp, (4 * REG_A2) /* Retrieve interruptee's A2 */ + l32i sp, sp, (4 * REG_A1) /* Remove interrupt stack frame */ + rsync /* Ensure EPS and EPC written */ + + /* Return from interrupt. RFI restores the PS from EPS_4 and jumps to + * the address in EPC_4. + */ + + rfi 4 + +#endif /* XCHAL_EXCM_LEVEL >= 4 */ + +#if XCHAL_EXCM_LEVEL >= 5 + .section .iram1,"ax" + .type _xtensa_level5_handler,@function + .align 4 + +_xtensa_level5_handler: + + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS_5 /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EPC_5 /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE_5 /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) + + /* Save rest of interrupt context. */ + + s32i a2, sp, (4 * REG_A2) + movi a2, sp /* Address of state save on stack */ + call0 _xtensa_context_save /* Save full register state */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + + ps_setup 5 a0 + + /* Decode and dispatch the interrupt. In the event of an interrupt + * level context dispatch_c_isr() will switch stacks to the new task's + * context save area. + */ + + dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK + + /* Restore registers in preparation to return from interrupt */ + + call0 _xtensa_context_restore + + /* Restore only level-specific regs (the rest were already restored) */ + + l32i a0, sp, (4 * REG_PS) /* Retrieve interruptee's PS */ + wsr a0, EPS_5 + l32i a0, sp, (4 * REG_PC) /* Retrieve interruptee's PC */ + wsr a0, EPC_5 + l32i a0, sp, (4 * REG_A0) /* Retrieve interruptee's A0 */ + l32i a2, sp, (4 * REG_A2) /* Retrieve interruptee's A2 */ + l32i sp, sp, (4 * REG_A1) /* Remove interrupt stack frame */ + rsync /* Ensure EPS and EPC written */ + + /* Return from interrupt. RFI restores the PS from EPS_5 and jumps to + * the address in EPC_5. + */ + + rfi 5 + +#endif /* XCHAL_EXCM_LEVEL >= 2 */ + +#if XCHAL_EXCM_LEVEL >= 6 + .section .iram1,"ax" + .type _xtensa_level6_handler,@function + .align 4 + +_xtensa_level6_handler: + + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS_6 /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EPC_6 /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE_6 /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) + + /* Save rest of interrupt context. */ + + s32i a2, sp, (4 * REG_A2) + movi a2, sp /* Address of state save on stack */ + call0 _xtensa_context_save /* Save full register state */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + + ps_setup 6 a0 + + /* Decode and dispatch the interrupt. In the event of an interrupt + * level context dispatch_c_isr() will switch stacks to the new task's + * context save area. + */ + + dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK + + /* Restore registers in preparation to return from interrupt */ + + call0 _xtensa_context_restore + + /* Restore only level-specific regs (the rest were already restored) */ + + l32i a0, sp, (4 * REG_PS) /* Retrieve interruptee's PS */ + wsr a0, EPS_6 + l32i a0, sp, (4 * REG_PC) /* Retrieve interruptee's PC */ + wsr a0, EPC_6 + l32i a0, sp, (4 * REG_A0) /* Retrieve interruptee's A0 */ + l32i a2, sp, (4 * REG_A2) /* Retrieve interruptee's A2 */ + l32i sp, sp, (4 * REG_A1) /* Remove interrupt stack frame */ + rsync /* Ensure EPS and EPC written */ + + /* Return from interrupt. RFI restores the PS from EPS_6 and jumps to + * the address in EPC_6. + */ + + rfi 6 + +#endif /* XCHAL_EXCM_LEVEL >= 6 */ + /**************************************************************************** - * - * HIGH PRIORITY (LEVEL > XCHAL_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS + * HIGH PRIORITY (LEVEL > XCHAL_EXCM_LEVEL) LOW-LEVEL HANDLERS * * High priority interrupts are by definition those with priorities greater * than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority -- GitLab From a9a4f6384d6ca4a7057bd430656b175bd8673ab6 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 23 Oct 2016 08:00:17 -0600 Subject: [PATCH 180/734] Xtensa: Add interrupt enable/disable controls. Add dummy timer and IRQ initialization. --- arch/xtensa/include/irq.h | 66 ++++++ .../xtensa}/xtensa_corebits.h | 8 +- .../xtensa}/xtensa_specregs.h | 8 +- arch/xtensa/src/common/xtensa_context.S | 5 +- arch/xtensa/src/common/xtensa_initialstate.c | 2 +- arch/xtensa/src/common/xtensa_inthandlers.S | 4 +- arch/xtensa/src/common/xtensa_intvectors.S | 2 +- arch/xtensa/src/common/xtensa_timer.h | 2 +- arch/xtensa/src/esp32/Make.defs | 3 +- arch/xtensa/src/esp32/esp32_irq.c | 202 ++++++++++++++++++ arch/xtensa/src/esp32/esp32_timerisr.c | 107 ++++++++++ 11 files changed, 392 insertions(+), 17 deletions(-) rename arch/xtensa/{src/common => include/xtensa}/xtensa_corebits.h (97%) rename arch/xtensa/{src/common => include/xtensa}/xtensa_specregs.h (95%) create mode 100644 arch/xtensa/src/esp32/esp32_irq.c create mode 100644 arch/xtensa/src/esp32/esp32_timerisr.c diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index 60d6af4758..692086c47b 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -46,9 +46,12 @@ /* Include NuttX-specific IRQ definitions */ +#include #include #include #include +#include +#include /* Include architecture-specific IRQ definitions */ @@ -168,6 +171,69 @@ struct xcptcontext * Inline functions ****************************************************************************/ +/* Return the current value of the PS register */ + +static inline uint32_t xtensa_getps(void) +{ + uint32_t ps; + + __asm__ __volatile__ + ( + "rsr %0, PS" : "=r"(ps) + ); + + return ps; +} + +/* Set the value of the PS register */ + +static inline void xtensa_setps(uint32_t ps) +{ + __asm__ __volatile__ + ( + "wsr %0, PS" : : "=r"(ps) + ); +} + +/* Restore the value of the PS register */ + +static inline void up_irq_restore(uint32_t ps) +{ + __asm__ __volatile__ + ( + "wsr %0, PS" : : "=r"(ps) + ); +} + +/* Disable interrupts and return the previous value of the PS register */ + +static inline uint32_t up_irq_save(void) +{ + /* Get the current value of the PS for return */ + + uint32_t ps = xtensa_getps(); + + /* Disable all low- and medium-priority interrupts. High priority + * interrupts should not interfere with ongoing RTOS operations and + * are not disabled. + * + * NOTE: We also assume that since we were called from C logic, the + * EXCM must already be cleared. + */ + +#ifdef CONFIG_XTENSA_CALL0_ABI + xtensa_setps(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM); +#else + xtensa_setps(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE); +#endif + + /* Return the previous PS value so that it can be restored with + * up_irq_restore(). + */ + + return ps; +} + /**************************************************************************** * Public Data ****************************************************************************/ diff --git a/arch/xtensa/src/common/xtensa_corebits.h b/arch/xtensa/include/xtensa/xtensa_corebits.h similarity index 97% rename from arch/xtensa/src/common/xtensa_corebits.h rename to arch/xtensa/include/xtensa/xtensa_corebits.h index 13da9dbca4..24f92d9a58 100644 --- a/arch/xtensa/src/common/xtensa_corebits.h +++ b/arch/xtensa/include/xtensa/xtensa_corebits.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/common/xtensa_corebits.h + * arch/xtensa/include/xtensa/xtensa_corebits.h * Xtensa Special Register field positions, masks, values. * NOTE: This file may be processor configuration dependent. * @@ -33,8 +33,8 @@ * ****************************************************************************/ -#ifndef __ARCH_EXTENSA_SRC_COMMON_XTENSA_COREBITS_H -#define __ARCH_EXTENSA_SRC_COMMON_XTENSA_COREBITS_H +#ifndef __ARCH_EXTENSA_INCLUDE_XTENSA_XTENSA_COREBITS_H +#define __ARCH_EXTENSA_INCLUDE_XTENSA_XTENSA_COREBITS_H /**************************************************************************** * Pre-processor Definitions @@ -203,4 +203,4 @@ #define MEMCTL_DCW_CLR_MASK (MEMCTL_DCWU_CLR_MASK | MEMCTL_DCWA_CLR_MASK) #define MEMCTL_IDCW_CLR_MASK (MEMCTL_DCW_CLR_MASK | MEMCTL_ICWU_CLR_MASK) -#endif /*__ARCH_EXTENSA_SRC_COMMON_XTENSA_COREBITS_H*/ +#endif /*__ARCH_EXTENSA_INCLUDE_XTENSA_XTENSA_COREBITS_H*/ diff --git a/arch/xtensa/src/common/xtensa_specregs.h b/arch/xtensa/include/xtensa/xtensa_specregs.h similarity index 95% rename from arch/xtensa/src/common/xtensa_specregs.h rename to arch/xtensa/include/xtensa/xtensa_specregs.h index 0b8b880d80..7d2843b39b 100644 --- a/arch/xtensa/src/common/xtensa_specregs.h +++ b/arch/xtensa/include/xtensa/xtensa_specregs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/common/xtensa_macros.h + * arch/xtensa/include/xtensa/xtensa_specregs.h * Xtensa Special Register symbolic names * * Adapted from use in NuttX by: @@ -32,8 +32,8 @@ * ****************************************************************************/ -#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_SPECREGS_H -#define __ARCH_XTENSA_SRC_COMMON_XTENSA_SPECREGS_H +#ifndef __ARCH_XTENSA_INCLUDE_XTENSA_XTENSA_SPECREGS_H +#define __ARCH_XTENSA_INCLUDE_XTENSA_XTENSA_SPECREGS_H /**************************************************************************** * Pre-processor Definitions @@ -151,4 +151,4 @@ #define CEND 247 /* VectraLX */ #endif -#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_SPECREGS_H */ +#endif /* __ARCH_XTENSA_INCLUDE_XTENSA_XTENSA_SPECREGS_H */ diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index 70dcf673be..c3c0835232 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -60,10 +60,9 @@ #include -#include #include - -#include "xtensa_specregs.h" +#include +#include #warning REVIST XTENSA_EXTRA_SA_SIZE is not yet provided #define XTENSA_EXTRA_SA_SIZE 0 /* REMOVE ME */ diff --git a/arch/xtensa/src/common/xtensa_initialstate.c b/arch/xtensa/src/common/xtensa_initialstate.c index 9bea96d7da..cce4e0c467 100644 --- a/arch/xtensa/src/common/xtensa_initialstate.c +++ b/arch/xtensa/src/common/xtensa_initialstate.c @@ -46,9 +46,9 @@ #include #include #include +#include #include "xtensa.h" -#include "xtensa_corebits.h" /**************************************************************************** * Public Functions diff --git a/arch/xtensa/src/common/xtensa_inthandlers.S b/arch/xtensa/src/common/xtensa_inthandlers.S index de9d1d2a98..456f574e17 100644 --- a/arch/xtensa/src/common/xtensa_inthandlers.S +++ b/arch/xtensa/src/common/xtensa_inthandlers.S @@ -59,10 +59,10 @@ #include -#include #include +#include +#include -#include "xtensa_specregs.h" #include "xtensa_macros.h" #include "xtensa_timer.h" diff --git a/arch/xtensa/src/common/xtensa_intvectors.S b/arch/xtensa/src/common/xtensa_intvectors.S index d570057086..13d7955f0b 100644 --- a/arch/xtensa/src/common/xtensa_intvectors.S +++ b/arch/xtensa/src/common/xtensa_intvectors.S @@ -39,8 +39,8 @@ #include #include +#include -#include "xtensa_specregs.h" #include "xtensa_macros.h" /**************************************************************************** diff --git a/arch/xtensa/src/common/xtensa_timer.h b/arch/xtensa/src/common/xtensa_timer.h index 27203b3725..b4fdf357ef 100644 --- a/arch/xtensa/src/common/xtensa_timer.h +++ b/arch/xtensa/src/common/xtensa_timer.h @@ -37,7 +37,7 @@ #include #endif -#include +#include #include /* Select timer to use for periodic tick, and determine its interrupt number diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index fea64934e1..3eea150d14 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -75,7 +75,8 @@ endif # Required ESP32 files (arch/xtensa/src/lx6) CHIP_ASRCS = -CHIP_CSRCS = esp32_allocateheap.c esp32_intdecode.c esp32_start.c +CHIP_CSRCS = esp32_allocateheap.c esp32_intdecode.c esp32_irq.c +CHIP_CSRCS += esp32_start.c esp32_timerisr.c # Configuration-dependent ESP32 files diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c new file mode 100644 index 0000000000..e0db64a92d --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -0,0 +1,202 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_irq.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "xtensa.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_current_regs[] holds a references to the current interrupt level + * register storage structure. If is non-NULL only during interrupt + * processing. Access to g_current_regs[] must be through the macro + * CURRENT_REGS for portability. + */ + +volatile uint32_t *g_current_regs[1]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_irq_dump + * + * Description: + * Dump some interesting NVIC registers + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_IRQ_INFO) +static void esp32_irq_dump(const char *msg, int irq) +{ + irqstate_t flags; + + flags = enter_critical_section(); +#warning Missing logic + leave_critical_section(flags); +} +#else +# define esp32_irq_dump(msg, irq) +#endif + +/**************************************************************************** + * Name: esp32_nmi + * + * Description: + * Handlers for various execptions. None are handled and all are fatal + * error conditions. The only advantage these provided over the default + * unexpected interrupt handler is that they provide a diagnostic output. + * + ****************************************************************************/ + +static int esp32_nmi(int irq, FAR void *context) +{ + (void)up_irq_save(); + _err("PANIC!!! NMI received\n"); + PANIC(); + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + int i; + + /* Disable all interrupts */ +#warning Missing logic + +#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 + /* Colorize the interrupt stack for debug purposes */ + +#warning Missing logic +#endif + + /* Set all interrupts (and exceptions) to the default priority */ +#warning Missing logic + + /* Attach all other processor exceptions (except reset and sys tick) */ +#warning Missing logic + + esp32_irq_dump("initial", NR_IRQS); + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + + /* And finally, enable interrupts */ + + up_irq_enable(); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: up_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void up_ack_irq(int irq) +{ +} + +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int irq, int priority) +{ +#warning Missing logic + return OK; +} +#endif diff --git a/arch/xtensa/src/esp32/esp32_timerisr.c b/arch/xtensa/src/esp32/esp32_timerisr.c new file mode 100644 index 0000000000..0d8b4d7612 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_timerisr.c @@ -0,0 +1,107 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_timerisr.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "clock/clock.h" +#include "xtensa.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: esp32_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +static int esp32_timerisr(int irq, uint32_t *regs) +{ + /* Process timer interrupt */ + + sched_process_timer(); + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + uint32_t regval; + + /* Configured the timer0 as the system timer */ +#warning Missing logic + + /* Attach the timer interrupt vector */ + + (void)irq_attach(XTENSA_IRQ_TIMER0, (xcpt_t)esp32_timerisr); + + /* Enable SysTick interrupts */ +#warning Missing logic + + /* And enable the timer interrupt */ + + up_enable_irq(XTENSA_IRQ_TIMER0); +} -- GitLab From 112b62a14e05b8e9a65e98bf905343e9bb8844fc Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 23 Oct 2016 08:04:57 -0600 Subject: [PATCH 181/734] Xtensa: Correct variou compilation issues --- arch/xtensa/include/irq.h | 30 ++++++++++++++++++--- arch/xtensa/src/common/xtensa_inthandlers.S | 2 +- arch/xtensa/src/common/xtensa_intvectors.S | 2 +- arch/xtensa/src/esp32/esp32_irq.c | 4 +-- arch/xtensa/src/esp32/esp32_timerisr.c | 4 +-- 5 files changed, 32 insertions(+), 10 deletions(-) diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index 692086c47b..26b6a0e3db 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -50,8 +50,8 @@ #include #include #include -#include -#include +#include +#include /* Include architecture-specific IRQ definitions */ @@ -191,7 +191,7 @@ static inline void xtensa_setps(uint32_t ps) { __asm__ __volatile__ ( - "wsr %0, PS" : : "=r"(ps) + "wsr %0, PS" : : "r"(ps) ); } @@ -201,7 +201,7 @@ static inline void up_irq_restore(uint32_t ps) { __asm__ __volatile__ ( - "wsr %0, PS" : : "=r"(ps) + "wsr %0, PS" : : "r"(ps) ); } @@ -234,6 +234,28 @@ static inline uint32_t up_irq_save(void) return ps; } +/* Enable interrupts at all levels */ + +static inline void up_irq_enable(void) +{ +#ifdef CONFIG_XTENSA_CALL0_ABI + xtensa_setps(PS_INTLEVEL(0) | PS_UM); +#else + xtensa_setps(PS_INTLEVEL(0) | PS_UM | PS_WOE); +#endif +} + +/* Disable low- and medium- priority interrupts */ + +static inline void up_irq_disable(void) +{ +#ifdef CONFIG_XTENSA_CALL0_ABI + xtensa_setps(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM); +#else + xtensa_setps(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE); +#endif +} + /**************************************************************************** * Public Data ****************************************************************************/ diff --git a/arch/xtensa/src/common/xtensa_inthandlers.S b/arch/xtensa/src/common/xtensa_inthandlers.S index 456f574e17..3193018819 100644 --- a/arch/xtensa/src/common/xtensa_inthandlers.S +++ b/arch/xtensa/src/common/xtensa_inthandlers.S @@ -61,7 +61,7 @@ #include #include -#include +#include #include "xtensa_macros.h" #include "xtensa_timer.h" diff --git a/arch/xtensa/src/common/xtensa_intvectors.S b/arch/xtensa/src/common/xtensa_intvectors.S index 13d7955f0b..103a35d886 100644 --- a/arch/xtensa/src/common/xtensa_intvectors.S +++ b/arch/xtensa/src/common/xtensa_intvectors.S @@ -39,7 +39,7 @@ #include #include -#include +#include #include "xtensa_macros.h" diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c index e0db64a92d..2620210f4b 100644 --- a/arch/xtensa/src/esp32/esp32_irq.c +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -112,10 +112,10 @@ static int esp32_nmi(int irq, FAR void *context) ****************************************************************************/ /**************************************************************************** - * Name: up_irqinitialize + * Name: xtensa_irq_initialize ****************************************************************************/ -void up_irqinitialize(void) +void xtensa_irq_initialize(void) { int i; diff --git a/arch/xtensa/src/esp32/esp32_timerisr.c b/arch/xtensa/src/esp32/esp32_timerisr.c index 0d8b4d7612..04fd396645 100644 --- a/arch/xtensa/src/esp32/esp32_timerisr.c +++ b/arch/xtensa/src/esp32/esp32_timerisr.c @@ -79,7 +79,7 @@ static int esp32_timerisr(int irq, uint32_t *regs) ****************************************************************************/ /**************************************************************************** - * Function: up_timer_initialize + * Function: xtensa_timer_initialize * * Description: * This function is called during start-up to initialize @@ -87,7 +87,7 @@ static int esp32_timerisr(int irq, uint32_t *regs) * ****************************************************************************/ -void up_timer_initialize(void) +void xtensa_timer_initialize(void) { uint32_t regval; -- GitLab From 09b462e41903c8bd65bf3717f303eadf929e45f0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 23 Oct 2016 09:02:50 -0600 Subject: [PATCH 182/734] Xtensa: Add region protected; Implement some missing signal handling logic. --- arch/xtensa/include/irq.h | 1 + .../xtensa/src/common/xtensa_schedsigaction.c | 18 ++- arch/xtensa/src/common/xtensa_sigdeliver.c | 6 +- arch/xtensa/src/esp32/Make.defs | 2 +- arch/xtensa/src/esp32/esp32_cpustart.c | 5 +- arch/xtensa/src/esp32/esp32_region.c | 106 ++++++++++++++++++ arch/xtensa/src/esp32/esp32_region.h | 67 +++++++++++ arch/xtensa/src/esp32/esp32_start.c | 6 +- 8 files changed, 196 insertions(+), 15 deletions(-) create mode 100644 arch/xtensa/src/esp32/esp32_region.c create mode 100644 arch/xtensa/src/esp32/esp32_region.h diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index 26b6a0e3db..1c11515dee 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -151,6 +151,7 @@ struct xcptcontext /* These are saved copies of registers used during signal processing. */ uint32_t saved_pc; + uint32_t saved_ps; #endif /* Register save area */ diff --git a/arch/xtensa/src/common/xtensa_schedsigaction.c b/arch/xtensa/src/common/xtensa_schedsigaction.c index 76c8669a39..8090bb262d 100644 --- a/arch/xtensa/src/common/xtensa_schedsigaction.c +++ b/arch/xtensa/src/common/xtensa_schedsigaction.c @@ -138,18 +138,24 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) /* Save the return lr and cpsr and one scratch register * These will be restored by the signal trampoline after * the signals have been delivered. + * + * NOTE: that hi-priority interrupts are not disabled. */ tcb->xcp.sigdeliver = sigdeliver; tcb->xcp.saved_pc = CURRENT_REGS[REG_PC]; -#warning REVISIT: Missing logic... need to save interrupt state + tcb->xcp.saved_ps = CURRENT_REGS[REG_PS]; /* Then set up to vector to the trampoline with interrupts * disabled */ CURRENT_REGS[REG_PC] = (uint32_t)xtensa_sigdeliver; -#warning REVISIT: Missing logic... need to set interrupt state with interrupts disabled +#ifdef CONFIG_XTENSA_CALL0_ABI + CURRENT_REGS[REG_PS] = (uint32_t)(PS_INTLEVEL(0) | PS_UM); +#else + CURRENT_REGS[REG_PS] = (uint32_t)(PS_INTLEVEL(0) | PS_UM | PS_WOE); +#endif /* And make sure that the saved context in the TCB is the same * as the interrupt return context. @@ -173,14 +179,18 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) tcb->xcp.sigdeliver = sigdeliver; tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC]; -#warning REVISIT: Missing logic... need to save interrupt state + tcb->xcp.saved_ps = tcb->xcp.regs[REG_PS]; /* Then set up to vector to the trampoline with interrupts * disabled */ tcb->xcp.regs[REG_PC] = (uint32_t)xtensa_sigdeliver; -#warning REVISIT: Missing logic... need to set interrupt state with interrupts disabled +#ifdef CONFIG_XTENSA_CALL0_ABI + tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(0) | PS_UM); +#else + tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(0) | PS_UM | PS_WOE); +#endif } } diff --git a/arch/xtensa/src/common/xtensa_sigdeliver.c b/arch/xtensa/src/common/xtensa_sigdeliver.c index 381b08f9a7..5f54c4035c 100644 --- a/arch/xtensa/src/common/xtensa_sigdeliver.c +++ b/arch/xtensa/src/common/xtensa_sigdeliver.c @@ -90,7 +90,7 @@ void xtensa_sigdeliver(void) xtensa_copystate(regs, rtcb->xcp.regs); regs[REG_PC] = rtcb->xcp.saved_pc; -#warning Missing Logic... Need to save the correct interrupt state + regs[REG_PS] = rtcb->xcp.saved_ps; /* Get a local copy of the sigdeliver function pointer. we do this so that * we can nullify the sigdeliver function pointer in the TCB and accept @@ -101,8 +101,8 @@ void xtensa_sigdeliver(void) rtcb->xcp.sigdeliver = NULL; /* Then restore the task interrupt state */ -#warning Missing Logic... Need to restore the correct interrupt state - //up_irq_restore(regs[REG_CPSR]); + + up_irq_restore(regs[REG_PS]); /* Deliver the signals */ diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 3eea150d14..1270f0c0cc 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -76,7 +76,7 @@ endif CHIP_ASRCS = CHIP_CSRCS = esp32_allocateheap.c esp32_intdecode.c esp32_irq.c -CHIP_CSRCS += esp32_start.c esp32_timerisr.c +CHIP_CSRCS += esp32_region.c esp32_start.c esp32_timerisr.c # Configuration-dependent ESP32 files diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c index 01e0412c75..038a2851c2 100644 --- a/arch/xtensa/src/esp32/esp32_cpustart.c +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -49,11 +49,10 @@ #include "sched/sched.h" #include "xtensa.h" +#include "esp32_region.h" #ifdef CONFIG_SMP -#warning REVISIT Need cpu_configure_region_protection() prototype -void cpu_configure_region_protection(void); #warning REVISIT Need ets_set_appcpu_boot_addr() prototype void ets_set_appcpu_boot_addr(uint32_t); @@ -126,7 +125,7 @@ int xtensa_start_handler(int irq, FAR void *context) /* Make page 0 access raise an exception */ - cpu_configure_region_protection(); + esp32_region_protection(); /* Dump registers so that we can see what is going to happen on return */ diff --git a/arch/xtensa/src/esp32/esp32_region.c b/arch/xtensa/src/esp32/esp32_region.c new file mode 100644 index 0000000000..bd3758342d --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_region.c @@ -0,0 +1,106 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_region.c + * + * Developed for NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from code originally provided Espressif Systems: + * + * C opyright 2010-2016 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint32_t g_protected_pages[] = +{ + 0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000 +}; + +#define NPROTECTED_PAGES (sizeof(g_protected_pages)/sizeof(uint32_t)) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_write_dtlb and xtensa_write_itlb + * + * Description: + * Functions to set page attributes for Region Protection option in the + * CPU. See Xtensa ISA Reference manual for explanation of arguments + * (section 4.6.3.2). + * + ****************************************************************************/ + +static inline void xtensa_write_dtlb(uint32_t vpn, unsigned int attr) +{ + __asm__ __volatile__ + ( + "wdtlb %1, %0\n" + "dsync\n" + : : "r" (vpn), "r" (attr)); + ); +} + +static inline void xtensa_write_itlb(unsigned vpn, unsigned int attr) +{ + __asm__ __volatile__ + ( + "witlb %1, %0\n" + "isync\n" + : : "r" (vpn), "r" (attr)); + ); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_region_protection + * + * Description: + * Make page 0 access raise an exception. Also protect some other unused + * pages so we can catch weirdness. + * + * Useful attribute values: + * 0 — cached, RW + * 2 — bypass cache, RWX (default value after CPU reset) + * 15 — no access, raise exception + * + ****************************************************************************/ + +void esp32_region_protection(void) +{ + for (int i = 0; i < NPROTECTED_PAGES; ++i) + { + xtensa_write_dtlb(g_protected_pages[i], 0xf); + xtensa_write_itlb(g_protected_pages[i], 0xf); + } + + xtensa_write_dtlb(0x20000000, 0); + xtensa_write_itlb(0x20000000, 0); +} diff --git a/arch/xtensa/src/esp32/esp32_region.h b/arch/xtensa/src/esp32/esp32_region.h new file mode 100644 index 0000000000..6a39afad09 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_region.h @@ -0,0 +1,67 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_region.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt > + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_REGION_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_REGION_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_region_protection + * + * Description: + * Make page 0 access raise an exception. Also protect some other unused + * pages so we can catch weirdness. + * + * Useful attribute values: + * 0 — cached, RW + * 2 — bypass cache, RWX (default value after CPU reset) + * 15 — no access, raise exception + * + ****************************************************************************/ + +void esp32_region_protection(void); + +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_REGION_H */ diff --git a/arch/xtensa/src/esp32/esp32_start.c b/arch/xtensa/src/esp32/esp32_start.c index 8926f0e79c..3d1ca5c9b9 100644 --- a/arch/xtensa/src/esp32/esp32_start.c +++ b/arch/xtensa/src/esp32/esp32_start.c @@ -38,12 +38,10 @@ #include "chip/esp32_dport.h" #include "chip/esp32_rtccntl.h" #include "esp32_clockconfig.h" +#include "esp32_region.h" #include "esp32_start.h" #include "xtensa.h" -#warning REVISIT Need cpu_configure_region_protection() prototype -void cpu_configure_region_protection(void); - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -77,7 +75,7 @@ void IRAM_ATTR __start(void) /* Make page 0 access raise an exception */ - cpu_configure_region_protection(); + esp32_region_protection(); /* Move CPU0 exception vectors to IRAM */ -- GitLab From c3d76d56bc0e4a61806a144d0e4c9de5951d3398 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 23 Oct 2016 10:06:30 -0600 Subject: [PATCH 183/734] Xtensa: Fix some compilation issues --- arch/xtensa/include/irq.h | 8 ++++---- arch/xtensa/src/common/xtensa_timer.h | 2 +- arch/xtensa/src/esp32/esp32_irq.c | 2 -- arch/xtensa/src/esp32/esp32_region.c | 8 +++++--- arch/xtensa/src/esp32/esp32_timerisr.c | 17 ++++++++++------- 5 files changed, 20 insertions(+), 17 deletions(-) diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index 1c11515dee..7432441f94 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -115,18 +115,18 @@ # define REG_TMP0 (_REG_CALL0_START + 0) # define REG_TMP1 (_REG_CALL0_START + 1) # define REG_TMP2 (_REG_CALL0_START + 2) -# define _REG_OVLY_START (_REG_CALL0_START + 3) +# define _REG_OVLY_START (_REG_CALL0_START + 3) #else -# define _REG_OVLY_START _REG_CALL0_START +# define _REG_OVLY_START _REG_CALL0_START #endif #ifdef CONFIG_XTENSA_USE_OVLY /* Storage for overlay state */ # error Overlays not supported -# define XCPTCONTEXT_REGS _REG_OVLY_START +# define XCPTCONTEXT_REGS _REG_OVLY_START #else -# define XCPTCONTEXT_REGS _REG_OVLY_START +# define XCPTCONTEXT_REGS _REG_OVLY_START #endif #define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS) diff --git a/arch/xtensa/src/common/xtensa_timer.h b/arch/xtensa/src/common/xtensa_timer.h index b4fdf357ef..f6cf6bab7b 100644 --- a/arch/xtensa/src/common/xtensa_timer.h +++ b/arch/xtensa/src/common/xtensa_timer.h @@ -38,7 +38,7 @@ #endif #include -#include +//#include /* Select timer to use for periodic tick, and determine its interrupt number * and priority. User may specify a timer by defining XT_TIMER_INDEX with -D, diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c index 2620210f4b..2fa02c8e93 100644 --- a/arch/xtensa/src/esp32/esp32_irq.c +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -117,8 +117,6 @@ static int esp32_nmi(int irq, FAR void *context) void xtensa_irq_initialize(void) { - int i; - /* Disable all interrupts */ #warning Missing logic diff --git a/arch/xtensa/src/esp32/esp32_region.c b/arch/xtensa/src/esp32/esp32_region.c index bd3758342d..1e64aa7e32 100644 --- a/arch/xtensa/src/esp32/esp32_region.c +++ b/arch/xtensa/src/esp32/esp32_region.c @@ -61,7 +61,7 @@ static inline void xtensa_write_dtlb(uint32_t vpn, unsigned int attr) ( "wdtlb %1, %0\n" "dsync\n" - : : "r" (vpn), "r" (attr)); + : : "r" (vpn), "r" (attr) ); } @@ -71,7 +71,7 @@ static inline void xtensa_write_itlb(unsigned vpn, unsigned int attr) ( "witlb %1, %0\n" "isync\n" - : : "r" (vpn), "r" (attr)); + : : "r" (vpn), "r" (attr) ); } @@ -95,7 +95,9 @@ static inline void xtensa_write_itlb(unsigned vpn, unsigned int attr) void esp32_region_protection(void) { - for (int i = 0; i < NPROTECTED_PAGES; ++i) + int i; + + for (i = 0; i < NPROTECTED_PAGES; ++i) { xtensa_write_dtlb(g_protected_pages[i], 0xf); xtensa_write_itlb(g_protected_pages[i], 0xf); diff --git a/arch/xtensa/src/esp32/esp32_timerisr.c b/arch/xtensa/src/esp32/esp32_timerisr.c index acf3862a97..6ff272d0f4 100644 --- a/arch/xtensa/src/esp32/esp32_timerisr.c +++ b/arch/xtensa/src/esp32/esp32_timerisr.c @@ -48,6 +48,7 @@ #include #include "clock/clock.h" +#include "xtensa_timer.h" #include "xtensa.h" /**************************************************************************** @@ -106,7 +107,7 @@ static inline uint32_t xtensa_getcompare(void) /* Set the value of the compare register */ -static inline void xtensa_setps(uint32_t compare) +static inline void xtensa_setcompare(uint32_t compare) { __asm__ __volatile__ ( @@ -122,10 +123,10 @@ static inline void xtensa_enable_timer(void) { __asm__ __volatile__ ( - "rsr a2, INTENABLE" - "ori a2, XT_TIMER_INTEN" - "wsr a2, INTENABLE" - : : "a2" + "rsr a2, INTENABLE\n" + "ori a2, XT_TIMER_INTEN\n" + "wsr a2, INTENABLE\n" + : : : "a2" ); } @@ -150,15 +151,17 @@ static inline void xtensa_enable_timer(void) static int esp32_timerisr(int irq, uint32_t *regs) { + uint32_t divisor; uint32_t compare; uint32_t diff; + divisor = g_tick_divisor; do { /* Increment the compare register for the next tick */ compare = xtensa_getcompare(); - xtensa_setcompare(count + g_tick_divisor); + xtensa_setcompare(compare + divisor); /* Process one timer tick */ @@ -168,7 +171,7 @@ static int esp32_timerisr(int irq, uint32_t *regs) * interrupts. */ - diff = xtensa_readcount() - compare; + diff = xtensa_getcount() - compare; } while (diff < divisor); -- GitLab From 9b5fedc81e4f663f5385696da1799cd6db45265f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 23 Oct 2016 10:08:38 -0600 Subject: [PATCH 184/734] Xtensa: Add implementation of system timer; Correct CFLAGS --- arch/xtensa/src/esp32/esp32_timerisr.c | 134 +++++++++++++++++++++++-- configs/esp32-core/nsh/Make.defs | 4 +- 2 files changed, 128 insertions(+), 10 deletions(-) diff --git a/arch/xtensa/src/esp32/esp32_timerisr.c b/arch/xtensa/src/esp32/esp32_timerisr.c index 04fd396645..acf3862a97 100644 --- a/arch/xtensa/src/esp32/esp32_timerisr.c +++ b/arch/xtensa/src/esp32/esp32_timerisr.c @@ -45,6 +45,7 @@ #include #include +#include #include "clock/clock.h" #include "xtensa.h" @@ -53,10 +54,81 @@ * Pre-processor Definitions ****************************************************************************/ +#warning REVISIT .. Need XT_CLOCK_FREQ +#define XT_CLOCK_FREQ 80000000 + +/**************************************************************************** + * Private data + ****************************************************************************/ + +static uint32_t g_tick_divisor; + /**************************************************************************** * Private Functions ****************************************************************************/ +/**************************************************************************** + * Function: xtensa_getcount, xtensa_getcompare, xtensa_setcompare, and + * xtensa_enable_timer + * + * Description: + * Lower level operations on Xtensa special registers. + * + ****************************************************************************/ + +/* Return the current value of the cyle count register */ + +static inline uint32_t xtensa_getcount(void) +{ + uint32_t count; + + __asm__ __volatile__ + ( + "rsr %0, CCOUNT" : "=r"(count) + ); + + return count; +} + +/* Return the old value of the compare register */ + +static inline uint32_t xtensa_getcompare(void) +{ + uint32_t compare; + + __asm__ __volatile__ + ( + "rsr %0, XT_CCOMPARE" : "=r"(compare) + ); + + return compare; +} + +/* Set the value of the compare register */ + +static inline void xtensa_setps(uint32_t compare) +{ + __asm__ __volatile__ + ( + "wsr %0, XT_CCOMPARE" : : "r"(compare) + ); +} + +/* Enable the timer interrupt. NOTE: This is non-atomic but safe in this + * context because this occurs early in the initialization sequence. + */ + +static inline void xtensa_enable_timer(void) +{ + __asm__ __volatile__ + ( + "rsr a2, INTENABLE" + "ori a2, XT_TIMER_INTEN" + "wsr a2, INTENABLE" + : : "a2" + ); +} + /**************************************************************************** * Function: esp32_timerisr * @@ -64,14 +136,43 @@ * The timer ISR will perform a variety of services for various portions * of the systems. * + * Xtensa timers work by comparing a cycle counter with a preset value. + * Once the match occurs an interrupt is generated, and the handler has to + * set a new cycle count into the comparator. To avoid clock drift due to + * interrupt latency, the new cycle count is computed from the old, not the + * time the interrupt was serviced. However if a timer interrupt is ever + * serviced more than one tick late, it is necessary to process multiple + * ticks until the new cycle count is in the future, otherwise the next + * timer interrupt would not occur until after the cycle counter had + * wrapped (2^32 cycles later). + * ****************************************************************************/ static int esp32_timerisr(int irq, uint32_t *regs) { - /* Process timer interrupt */ + uint32_t compare; + uint32_t diff; - sched_process_timer(); - return 0; + do + { + /* Increment the compare register for the next tick */ + + compare = xtensa_getcompare(); + xtensa_setcompare(count + g_tick_divisor); + + /* Process one timer tick */ + + sched_process_timer(); + + /* Check if we are falling behind and need to process multiple timer + * interrupts. + */ + + diff = xtensa_readcount() - compare; + } + while (diff < divisor); + + return OK; } /**************************************************************************** @@ -89,17 +190,34 @@ static int esp32_timerisr(int irq, uint32_t *regs) void xtensa_timer_initialize(void) { - uint32_t regval; + uint64_t divisor; + uint32_t count; + + /* Configured the timer0 as the system timer. + * + * divisor = XT_CLOCK_FREQ / ticks_per_sec + * = XT_CLOCK_FREQ / (ticks_per_usec * 1000000) + * = (1000000 * XT_CLOCK_FREQ) / ticks_per_usec + * + * A long long calculation is used to preserve accuracy in all cases. + */ + + divisor = (1000000ull * (uint64_t)XT_CLOCK_FREQ) / CONFIG_USEC_PER_TICK; + DEBUGASSERT(divisor <= UINT32_MAX) + g_tick_divisor = divisor; - /* Configured the timer0 as the system timer */ -#warning Missing logic + /* Set up periodic timer */ + + count = xtensa_getcount(); + xtensa_setcompare(count + divisor); /* Attach the timer interrupt vector */ (void)irq_attach(XTENSA_IRQ_TIMER0, (xcpt_t)esp32_timerisr); - /* Enable SysTick interrupts */ -#warning Missing logic + /* Enable the timer interrupt at the device level */ + + xtensa_enable_timer(); /* And enable the timer interrupt */ diff --git a/configs/esp32-core/nsh/Make.defs b/configs/esp32-core/nsh/Make.defs index eaf619d7c0..f8901d0f8b 100644 --- a/configs/esp32-core/nsh/Make.defs +++ b/configs/esp32-core/nsh/Make.defs @@ -78,8 +78,8 @@ ifneq ($(CONFIG_DEBUG_NOOPT),y) ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer endif -ARCHCFLAGS = -fno-builtin -ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHCFLAGS = -fno-builtin -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -mlongcalls -MMD -MP +ARCHCXXFLAGS = $(ARCHCFLAGS) -fno-exceptions -fcheck-new -fno-rtti ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef ARCHWARNINGSXX = -Wall -Wshadow -Wundef ARCHDEFINES = -- GitLab From 9f06b13ffbb05919db2f3e1fc45c196ce80006a6 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 23 Oct 2016 10:43:16 -0600 Subject: [PATCH 185/734] Xtensa: Add core.h header file --- arch/xtensa/include/xtensa/core.h | 1455 +++++++++++++++++++++++++ arch/xtensa/src/common/xtensa_timer.h | 7 +- 2 files changed, 1459 insertions(+), 3 deletions(-) create mode 100644 arch/xtensa/include/xtensa/core.h diff --git a/arch/xtensa/include/xtensa/core.h b/arch/xtensa/include/xtensa/core.h new file mode 100644 index 0000000000..8a17c7a2ff --- /dev/null +++ b/arch/xtensa/include/xtensa/core.h @@ -0,0 +1,1455 @@ +/**************************************************************************** + * arch/xtensa/include/core.h + * + * Leveraged to NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * + * This file derives from code provided Cadence Design Systems, Inc.: + * + * Copyright (c) 2005-2014 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + +/* This header file is sometimes referred to as the "compile-time HAL" or CHAL. + * It pulls definitions tailored for a specific Xtensa processor configuration. + * + * Sources for binaries meant to be configuration-independent generally avoid + * including this file (they may use the configuration-specific HAL library). + * It is normal for the HAL library source itself to include this file. + */ + +#ifndef __ARCH_XTENSA_INCUDE_XTENSA_CORE_H +#define __ARCH_XTENSA_INCUDE_XTENSA_CORE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Configuration independent definitions: */ + +#warning REVISIT: Missing header files: +//#include +//#include + +/* Configuration specific definitions: */ + +#include +//#include +//#include + +#ifdef __ASSEMBLY__ +//# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* General ******************************************************************/ + +/* Separators for macros that expand into arrays. + * These can be predefined by files that #include this one, + * when different separators are required. + */ + +/* Element separator for macros that expand into 1-dimensional arrays: */ +#ifndef XCHAL_SEP +# define XCHAL_SEP , +#endif + +/* Array separator for macros that expand into 2-dimensional arrays: */ +#ifndef XCHAL_SEP2 +# define XCHAL_SEP2 },{ +#endif + +/* ISA **********************************************************************/ + +#if XCHAL_HAVE_BE +# define XCHAL_HAVE_LE 0 +# define XCHAL_MEMORY_ORDER XTHAL_BIGENDIAN +#else +# define XCHAL_HAVE_LE 1 +# define XCHAL_MEMORY_ORDER XTHAL_LITTLEENDIAN +#endif + +/* Interrupts ***************************************************************/ + +/* Indexing macros: */ + +#define _XCHAL_INTLEVEL_MASK(n) XCHAL_INTLEVEL ## n ## _MASK +#define XCHAL_INTLEVEL_MASK(n) _XCHAL_INTLEVEL_MASK(n) /* n = 0 .. 15 */ +#define _XCHAL_INTLEVEL_ANDBELOWMASK(n) XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK +#define XCHAL_INTLEVEL_ANDBELOW_MASK(n) _XCHAL_INTLEVEL_ANDBELOWMASK(n) /* n = 0 .. 15 */ +#define _XCHAL_INTLEVEL_NUM(n) XCHAL_INTLEVEL ## n ## _NUM +#define XCHAL_INTLEVEL_NUM(n) _XCHAL_INTLEVEL_NUM(n) /* n = 0 .. 15 */ +#define _XCHAL_INT_LEVEL(n) XCHAL_INT ## n ## _LEVEL +#define XCHAL_INT_LEVEL(n) _XCHAL_INT_LEVEL(n) /* n = 0 .. 31 */ +#define _XCHAL_INT_TYPE(n) XCHAL_INT ## n ## _TYPE +#define XCHAL_INT_TYPE(n) _XCHAL_INT_TYPE(n) /* n = 0 .. 31 */ +#define _XCHAL_TIMER_INTERRUPT(n) XCHAL_TIMER ## n ## _INTERRUPT +#define XCHAL_TIMER_INTERRUPT(n) _XCHAL_TIMER_INTERRUPT(n) /* n = 0 .. 3 */ + +#define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS XCHAL_HAVE_HIGHPRI_INTERRUPTS +#define XCHAL_NUM_LOWPRI_LEVELS 1 /* Number of low-priority + * interrupt levels (always 1) */ +#define XCHAL_FIRST_HIGHPRI_LEVEL (XCHAL_NUM_LOWPRI_LEVELS+1) + /* Level of first high-priority + * interrupt (always 2) */ + +/* Note: 1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15 */ + +/* These values are constant for existing Xtensa processor implementations: */ + +#define XCHAL_INTLEVEL0_MASK 0x00000000 +#define XCHAL_INTLEVEL8_MASK 0x00000000 +#define XCHAL_INTLEVEL9_MASK 0x00000000 +#define XCHAL_INTLEVEL10_MASK 0x00000000 +#define XCHAL_INTLEVEL11_MASK 0x00000000 +#define XCHAL_INTLEVEL12_MASK 0x00000000 +#define XCHAL_INTLEVEL13_MASK 0x00000000 +#define XCHAL_INTLEVEL14_MASK 0x00000000 +#define XCHAL_INTLEVEL15_MASK 0x00000000 + +/* Array of masks of interrupts at each interrupt level: */ + +#define XCHAL_INTLEVEL_MASKS XCHAL_INTLEVEL0_MASK \ + XCHAL_SEP XCHAL_INTLEVEL1_MASK \ + XCHAL_SEP XCHAL_INTLEVEL2_MASK \ + XCHAL_SEP XCHAL_INTLEVEL3_MASK \ + XCHAL_SEP XCHAL_INTLEVEL4_MASK \ + XCHAL_SEP XCHAL_INTLEVEL5_MASK \ + XCHAL_SEP XCHAL_INTLEVEL6_MASK \ + XCHAL_SEP XCHAL_INTLEVEL7_MASK \ + XCHAL_SEP XCHAL_INTLEVEL8_MASK \ + XCHAL_SEP XCHAL_INTLEVEL9_MASK \ + XCHAL_SEP XCHAL_INTLEVEL10_MASK \ + XCHAL_SEP XCHAL_INTLEVEL11_MASK \ + XCHAL_SEP XCHAL_INTLEVEL12_MASK \ + XCHAL_SEP XCHAL_INTLEVEL13_MASK \ + XCHAL_SEP XCHAL_INTLEVEL14_MASK \ + XCHAL_SEP XCHAL_INTLEVEL15_MASK + +/* These values are constant for existing Xtensa processor implementations: */ + +#define XCHAL_INTLEVEL0_ANDBELOW_MASK 0x00000000 +#define XCHAL_INTLEVEL8_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL9_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL10_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL11_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL12_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL13_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL14_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL15_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK + +/* Mask of all low-priority interrupts: */ + +#define XCHAL_LOWPRI_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK + +/* Mask of all interrupts masked by PS.EXCM (or CEXCM): */ + +#define XCHAL_EXCM_MASK XCHAL_INTLEVEL_ANDBELOW_MASK(XCHAL_EXCM_LEVEL) + +/* Array of masks of interrupts at each range 1..n of interrupt levels: */ + +#define XCHAL_INTLEVEL_ANDBELOW_MASKS XCHAL_INTLEVEL0_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL1_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL2_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL3_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL4_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL5_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL6_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL7_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL8_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL9_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL10_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL11_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL12_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL13_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL14_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL15_ANDBELOW_MASK + +#if 0 /* XCHAL_HAVE_NMI */ + +/* NMI "interrupt level" (for use with EXCSAVE_n, EPS_n, EPC_n, RFI n): */ + +# define XCHAL_NMILEVEL (XCHAL_NUM_INTLEVELS+1) +#endif + +/* Array of levels of each possible interrupt: */ + +#define XCHAL_INT_LEVELS XCHAL_INT0_LEVEL \ + XCHAL_SEP XCHAL_INT1_LEVEL \ + XCHAL_SEP XCHAL_INT2_LEVEL \ + XCHAL_SEP XCHAL_INT3_LEVEL \ + XCHAL_SEP XCHAL_INT4_LEVEL \ + XCHAL_SEP XCHAL_INT5_LEVEL \ + XCHAL_SEP XCHAL_INT6_LEVEL \ + XCHAL_SEP XCHAL_INT7_LEVEL \ + XCHAL_SEP XCHAL_INT8_LEVEL \ + XCHAL_SEP XCHAL_INT9_LEVEL \ + XCHAL_SEP XCHAL_INT10_LEVEL \ + XCHAL_SEP XCHAL_INT11_LEVEL \ + XCHAL_SEP XCHAL_INT12_LEVEL \ + XCHAL_SEP XCHAL_INT13_LEVEL \ + XCHAL_SEP XCHAL_INT14_LEVEL \ + XCHAL_SEP XCHAL_INT15_LEVEL \ + XCHAL_SEP XCHAL_INT16_LEVEL \ + XCHAL_SEP XCHAL_INT17_LEVEL \ + XCHAL_SEP XCHAL_INT18_LEVEL \ + XCHAL_SEP XCHAL_INT19_LEVEL \ + XCHAL_SEP XCHAL_INT20_LEVEL \ + XCHAL_SEP XCHAL_INT21_LEVEL \ + XCHAL_SEP XCHAL_INT22_LEVEL \ + XCHAL_SEP XCHAL_INT23_LEVEL \ + XCHAL_SEP XCHAL_INT24_LEVEL \ + XCHAL_SEP XCHAL_INT25_LEVEL \ + XCHAL_SEP XCHAL_INT26_LEVEL \ + XCHAL_SEP XCHAL_INT27_LEVEL \ + XCHAL_SEP XCHAL_INT28_LEVEL \ + XCHAL_SEP XCHAL_INT29_LEVEL \ + XCHAL_SEP XCHAL_INT30_LEVEL \ + XCHAL_SEP XCHAL_INT31_LEVEL + +/* Array of types of each possible interrupt: */ + +#define XCHAL_INT_TYPES XCHAL_INT0_TYPE \ + XCHAL_SEP XCHAL_INT1_TYPE \ + XCHAL_SEP XCHAL_INT2_TYPE \ + XCHAL_SEP XCHAL_INT3_TYPE \ + XCHAL_SEP XCHAL_INT4_TYPE \ + XCHAL_SEP XCHAL_INT5_TYPE \ + XCHAL_SEP XCHAL_INT6_TYPE \ + XCHAL_SEP XCHAL_INT7_TYPE \ + XCHAL_SEP XCHAL_INT8_TYPE \ + XCHAL_SEP XCHAL_INT9_TYPE \ + XCHAL_SEP XCHAL_INT10_TYPE \ + XCHAL_SEP XCHAL_INT11_TYPE \ + XCHAL_SEP XCHAL_INT12_TYPE \ + XCHAL_SEP XCHAL_INT13_TYPE \ + XCHAL_SEP XCHAL_INT14_TYPE \ + XCHAL_SEP XCHAL_INT15_TYPE \ + XCHAL_SEP XCHAL_INT16_TYPE \ + XCHAL_SEP XCHAL_INT17_TYPE \ + XCHAL_SEP XCHAL_INT18_TYPE \ + XCHAL_SEP XCHAL_INT19_TYPE \ + XCHAL_SEP XCHAL_INT20_TYPE \ + XCHAL_SEP XCHAL_INT21_TYPE \ + XCHAL_SEP XCHAL_INT22_TYPE \ + XCHAL_SEP XCHAL_INT23_TYPE \ + XCHAL_SEP XCHAL_INT24_TYPE \ + XCHAL_SEP XCHAL_INT25_TYPE \ + XCHAL_SEP XCHAL_INT26_TYPE \ + XCHAL_SEP XCHAL_INT27_TYPE \ + XCHAL_SEP XCHAL_INT28_TYPE \ + XCHAL_SEP XCHAL_INT29_TYPE \ + XCHAL_SEP XCHAL_INT30_TYPE \ + XCHAL_SEP XCHAL_INT31_TYPE + +/* Array of masks of interrupts for each type of interrupt: */ + +#define XCHAL_INTTYPE_MASKS XCHAL_INTTYPE_MASK_UNCONFIGURED \ + XCHAL_SEP XCHAL_INTTYPE_MASK_SOFTWARE \ + XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_EDGE \ + XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_LEVEL \ + XCHAL_SEP XCHAL_INTTYPE_MASK_TIMER \ + XCHAL_SEP XCHAL_INTTYPE_MASK_NMI \ + XCHAL_SEP XCHAL_INTTYPE_MASK_WRITE_ERROR + +/* Interrupts that can be cleared using the INTCLEAR special register: */ + +#define XCHAL_INTCLEARABLE_MASK \ + (XCHAL_INTTYPE_MASK_SOFTWARE+XCHAL_INTTYPE_MASK_EXTERN_EDGE+XCHAL_INTTYPE_MASK_WRITE_ERROR) + +/* Interrupts that can be triggered using the INTSET special register: */ + +#define XCHAL_INTSETTABLE_MASK XCHAL_INTTYPE_MASK_SOFTWARE + +/* Array of interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3): */ + +#define XCHAL_TIMER_INTERRUPTS XCHAL_TIMER0_INTERRUPT \ + XCHAL_SEP XCHAL_TIMER1_INTERRUPT \ + XCHAL_SEP XCHAL_TIMER2_INTERRUPT \ + XCHAL_SEP XCHAL_TIMER3_INTERRUPT + +/* For backward compatibility and for the array macros, define macros for + * each unconfigured interrupt number (unfortunately, the value of + * XTHAL_INTTYPE_UNCONFIGURED is not zero): + */ + +#if XCHAL_NUM_INTERRUPTS == 0 +# define XCHAL_INT0_LEVEL 0 +# define XCHAL_INT0_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 1 +# define XCHAL_INT1_LEVEL 0 +# define XCHAL_INT1_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 2 +# define XCHAL_INT2_LEVEL 0 +# define XCHAL_INT2_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 3 +# define XCHAL_INT3_LEVEL 0 +# define XCHAL_INT3_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 4 +# define XCHAL_INT4_LEVEL 0 +# define XCHAL_INT4_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 5 +# define XCHAL_INT5_LEVEL 0 +# define XCHAL_INT5_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 6 +# define XCHAL_INT6_LEVEL 0 +# define XCHAL_INT6_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 7 +# define XCHAL_INT7_LEVEL 0 +# define XCHAL_INT7_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 8 +# define XCHAL_INT8_LEVEL 0 +# define XCHAL_INT8_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 9 +# define XCHAL_INT9_LEVEL 0 +# define XCHAL_INT9_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 10 +# define XCHAL_INT10_LEVEL 0 +# define XCHAL_INT10_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 11 +# define XCHAL_INT11_LEVEL 0 +# define XCHAL_INT11_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 12 +# define XCHAL_INT12_LEVEL 0 +# define XCHAL_INT12_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 13 +# define XCHAL_INT13_LEVEL 0 +# define XCHAL_INT13_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 14 +# define XCHAL_INT14_LEVEL 0 +# define XCHAL_INT14_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 15 +# define XCHAL_INT15_LEVEL 0 +# define XCHAL_INT15_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 16 +# define XCHAL_INT16_LEVEL 0 +# define XCHAL_INT16_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 17 +# define XCHAL_INT17_LEVEL 0 +# define XCHAL_INT17_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 18 +# define XCHAL_INT18_LEVEL 0 +# define XCHAL_INT18_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 19 +# define XCHAL_INT19_LEVEL 0 +# define XCHAL_INT19_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 20 +# define XCHAL_INT20_LEVEL 0 +# define XCHAL_INT20_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 21 +# define XCHAL_INT21_LEVEL 0 +# define XCHAL_INT21_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 22 +# define XCHAL_INT22_LEVEL 0 +# define XCHAL_INT22_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 23 +# define XCHAL_INT23_LEVEL 0 +# define XCHAL_INT23_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 24 +# define XCHAL_INT24_LEVEL 0 +# define XCHAL_INT24_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 25 +# define XCHAL_INT25_LEVEL 0 +# define XCHAL_INT25_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 26 +# define XCHAL_INT26_LEVEL 0 +# define XCHAL_INT26_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 27 +# define XCHAL_INT27_LEVEL 0 +# define XCHAL_INT27_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 28 +# define XCHAL_INT28_LEVEL 0 +# define XCHAL_INT28_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 29 +# define XCHAL_INT29_LEVEL 0 +# define XCHAL_INT29_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 30 +# define XCHAL_INT30_LEVEL 0 +# define XCHAL_INT30_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 31 +# define XCHAL_INT31_LEVEL 0 +# define XCHAL_INT31_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif + +/* Masks and levels corresponding to each *external* interrupt. */ + +#define XCHAL_EXTINT0_MASK (1 << XCHAL_EXTINT0_NUM) +#define XCHAL_EXTINT0_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT0_NUM) +#define XCHAL_EXTINT1_MASK (1 << XCHAL_EXTINT1_NUM) +#define XCHAL_EXTINT1_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT1_NUM) +#define XCHAL_EXTINT2_MASK (1 << XCHAL_EXTINT2_NUM) +#define XCHAL_EXTINT2_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT2_NUM) +#define XCHAL_EXTINT3_MASK (1 << XCHAL_EXTINT3_NUM) +#define XCHAL_EXTINT3_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT3_NUM) +#define XCHAL_EXTINT4_MASK (1 << XCHAL_EXTINT4_NUM) +#define XCHAL_EXTINT4_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT4_NUM) +#define XCHAL_EXTINT5_MASK (1 << XCHAL_EXTINT5_NUM) +#define XCHAL_EXTINT5_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT5_NUM) +#define XCHAL_EXTINT6_MASK (1 << XCHAL_EXTINT6_NUM) +#define XCHAL_EXTINT6_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT6_NUM) +#define XCHAL_EXTINT7_MASK (1 << XCHAL_EXTINT7_NUM) +#define XCHAL_EXTINT7_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT7_NUM) +#define XCHAL_EXTINT8_MASK (1 << XCHAL_EXTINT8_NUM) +#define XCHAL_EXTINT8_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT8_NUM) +#define XCHAL_EXTINT9_MASK (1 << XCHAL_EXTINT9_NUM) +#define XCHAL_EXTINT9_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT9_NUM) +#define XCHAL_EXTINT10_MASK (1 << XCHAL_EXTINT10_NUM) +#define XCHAL_EXTINT10_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT10_NUM) +#define XCHAL_EXTINT11_MASK (1 << XCHAL_EXTINT11_NUM) +#define XCHAL_EXTINT11_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT11_NUM) +#define XCHAL_EXTINT12_MASK (1 << XCHAL_EXTINT12_NUM) +#define XCHAL_EXTINT12_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT12_NUM) +#define XCHAL_EXTINT13_MASK (1 << XCHAL_EXTINT13_NUM) +#define XCHAL_EXTINT13_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT13_NUM) +#define XCHAL_EXTINT14_MASK (1 << XCHAL_EXTINT14_NUM) +#define XCHAL_EXTINT14_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT14_NUM) +#define XCHAL_EXTINT15_MASK (1 << XCHAL_EXTINT15_NUM) +#define XCHAL_EXTINT15_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT15_NUM) +#define XCHAL_EXTINT16_MASK (1 << XCHAL_EXTINT16_NUM) +#define XCHAL_EXTINT16_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT16_NUM) +#define XCHAL_EXTINT17_MASK (1 << XCHAL_EXTINT17_NUM) +#define XCHAL_EXTINT17_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT17_NUM) +#define XCHAL_EXTINT18_MASK (1 << XCHAL_EXTINT18_NUM) +#define XCHAL_EXTINT18_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT18_NUM) +#define XCHAL_EXTINT19_MASK (1 << XCHAL_EXTINT19_NUM) +#define XCHAL_EXTINT19_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT19_NUM) +#define XCHAL_EXTINT20_MASK (1 << XCHAL_EXTINT20_NUM) +#define XCHAL_EXTINT20_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT20_NUM) +#define XCHAL_EXTINT21_MASK (1 << XCHAL_EXTINT21_NUM) +#define XCHAL_EXTINT21_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT21_NUM) +#define XCHAL_EXTINT22_MASK (1 << XCHAL_EXTINT22_NUM) +#define XCHAL_EXTINT22_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT22_NUM) +#define XCHAL_EXTINT23_MASK (1 << XCHAL_EXTINT23_NUM) +#define XCHAL_EXTINT23_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT23_NUM) +#define XCHAL_EXTINT24_MASK (1 << XCHAL_EXTINT24_NUM) +#define XCHAL_EXTINT24_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT24_NUM) +#define XCHAL_EXTINT25_MASK (1 << XCHAL_EXTINT25_NUM) +#define XCHAL_EXTINT25_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT25_NUM) +#define XCHAL_EXTINT26_MASK (1 << XCHAL_EXTINT26_NUM) +#define XCHAL_EXTINT26_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT26_NUM) +#define XCHAL_EXTINT27_MASK (1 << XCHAL_EXTINT27_NUM) +#define XCHAL_EXTINT27_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT27_NUM) +#define XCHAL_EXTINT28_MASK (1 << XCHAL_EXTINT28_NUM) +#define XCHAL_EXTINT28_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT28_NUM) +#define XCHAL_EXTINT29_MASK (1 << XCHAL_EXTINT29_NUM) +#define XCHAL_EXTINT29_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT29_NUM) +#define XCHAL_EXTINT30_MASK (1 << XCHAL_EXTINT30_NUM) +#define XCHAL_EXTINT30_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT30_NUM) +#define XCHAL_EXTINT31_MASK (1 << XCHAL_EXTINT31_NUM) +#define XCHAL_EXTINT31_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT31_NUM) + +/* Exceptions and Vectors ***************************************************/ + +/* For backward compatibility ONLY -- DO NOT USE (will be removed in future release): */ + +#define XCHAL_HAVE_OLD_EXC_ARCH XCHAL_HAVE_XEA1 /* (DEPRECATED) 1 if + * old exception + * architecture (XEA1), + * 0 otherwise (eg. + * XEA2) */ +#define XCHAL_HAVE_EXCM XCHAL_HAVE_XEA2 /* (DEPRECATED) 1 if + * PS.EXCM bit exists + * (currently equals + * XCHAL_HAVE_TLBS) */ +#ifdef XCHAL_USER_VECTOR_VADDR +# define XCHAL_PROGRAMEXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR +# define XCHAL_USEREXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR +#endif +#ifdef XCHAL_USER_VECTOR_PADDR +# define XCHAL_PROGRAMEXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR +# define XCHAL_USEREXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR +#endif +#ifdef XCHAL_KERNEL_VECTOR_VADDR +# define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR +# define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR +#endif +#ifdef XCHAL_KERNEL_VECTOR_PADDR +# define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR +# define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR +#endif + +#if 0 +# if XCHAL_HAVE_DEBUG +# define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL) + +/* This one should only get defined if the corresponding intlevel paddr macro exists: */ + +# define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL_VECTOR_PADDR(XCHAL_DEBUGLEVEL) +# endif +#endif + +/* Indexing macros: */ + +#define _XCHAL_INTLEVEL_VECTOR_VADDR(n) XCHAL_INTLEVEL ## n ## _VECTOR_VADDR +#define XCHAL_INTLEVEL_VECTOR_VADDR(n) _XCHAL_INTLEVEL_VECTOR_VADDR(n) /* n = 0 .. 15 */ + +/* General Exception Causes: + * + * Values of EXCCAUSE special register set by general exceptions, + * which vector to the user, kernel, or double-exception vectors. + * + * DEPRECATED. Please use the equivalent EXCCAUSE_xxx macros + * defined in . (Note that these have slightly + * different names, they don't just have the XCHAL_ prefix removed.) + */ + +#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction */ +#define XCHAL_EXCCAUSE_SYSTEM_CALL 1 /* System Call */ +#define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 /* Instruction Fetch Error */ +#define XCHAL_EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */ +#define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */ +#define XCHAL_EXCCAUSE_ALLOCA 5 /* Stack Extension Assist */ +#define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */ +#define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation */ +#define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */ +#define XCHAL_EXCCAUSE_UNALIGNED 9 /* Unaligned Load Store */ + /* 10..15 reserved */ +#define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception */ +#define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception */ +#define XCHAL_EXCCAUSE_ITLB_PRIVILEGE 18 /* ITlb Privilege Exception */ +#define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION 19 /* ITlb Size Restriction Exception */ +#define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 /* Fetch Cache Attribute Exception */ + /* 21..23 reserved */ +#define XCHAL_EXCCAUSE_DTLB_MISS 24 /* DTlb Miss Exception */ +#define XCHAL_EXCCAUSE_DTLB_MULTIHIT 25 /* DTlb Multihit Exception */ +#define XCHAL_EXCCAUSE_DTLB_PRIVILEGE 26 /* DTlb Privilege Exception */ +#define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION 27 /* DTlb Size Restriction Exception */ +#define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 /* Load Cache Attribute Exception */ +#define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 /* Store Cache Attribute Exception */ + /* 30..31 reserved */ +#define XCHAL_EXCCAUSE_COPROCESSOR0_DISABLED 32 /* Coprocessor 0 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR1_DISABLED 33 /* Coprocessor 1 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR2_DISABLED 34 /* Coprocessor 2 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR3_DISABLED 35 /* Coprocessor 3 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR4_DISABLED 36 /* Coprocessor 4 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR5_DISABLED 37 /* Coprocessor 5 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR6_DISABLED 38 /* Coprocessor 6 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR7_DISABLED 39 /* Coprocessor 7 disabled */ + /* 40..63 reserved */ + +/* Miscellaneous special register fields. + * + * For each special register, and each field within each register: + * XCHAL__VALIDMASK is the set of bits defined in the register. + * XCHAL___BITS is the number of bits in the field. + * XCHAL___NUM is 2^bits, the number of possible values + * of the field. + * XCHAL___SHIFT is the position of the field within + * the register, starting from the least significant bit. + * + * DEPRECATED. Please use the equivalent macros defined in + * . (Note that these have different names.) + */ + +/* DBREAKC (special register number 160): */ + +#define XCHAL_DBREAKC_VALIDMASK 0xC000003F +#define XCHAL_DBREAKC_MASK_BITS 6 +#define XCHAL_DBREAKC_MASK_NUM 64 +#define XCHAL_DBREAKC_MASK_SHIFT 0 +#define XCHAL_DBREAKC_MASK_MASK 0x0000003F +#define XCHAL_DBREAKC_LOADBREAK_BITS 1 +#define XCHAL_DBREAKC_LOADBREAK_NUM 2 +#define XCHAL_DBREAKC_LOADBREAK_SHIFT 30 +#define XCHAL_DBREAKC_LOADBREAK_MASK 0x40000000 +#define XCHAL_DBREAKC_STOREBREAK_BITS 1 +#define XCHAL_DBREAKC_STOREBREAK_NUM 2 +#define XCHAL_DBREAKC_STOREBREAK_SHIFT 31 +#define XCHAL_DBREAKC_STOREBREAK_MASK 0x80000000 + +/* PS (special register number 230): */ + +#define XCHAL_PS_VALIDMASK 0x00070F3F +#define XCHAL_PS_INTLEVEL_BITS 4 +#define XCHAL_PS_INTLEVEL_NUM 16 +#define XCHAL_PS_INTLEVEL_SHIFT 0 +#define XCHAL_PS_INTLEVEL_MASK 0x0000000F +#define XCHAL_PS_EXCM_BITS 1 +#define XCHAL_PS_EXCM_NUM 2 +#define XCHAL_PS_EXCM_SHIFT 4 +#define XCHAL_PS_EXCM_MASK 0x00000010 +#define XCHAL_PS_UM_BITS 1 +#define XCHAL_PS_UM_NUM 2 +#define XCHAL_PS_UM_SHIFT 5 +#define XCHAL_PS_UM_MASK 0x00000020 +#define XCHAL_PS_RING_BITS 2 +#define XCHAL_PS_RING_NUM 4 +#define XCHAL_PS_RING_SHIFT 6 +#define XCHAL_PS_RING_MASK 0x000000C0 +#define XCHAL_PS_OWB_BITS 4 +#define XCHAL_PS_OWB_NUM 16 +#define XCHAL_PS_OWB_SHIFT 8 +#define XCHAL_PS_OWB_MASK 0x00000F00 +#define XCHAL_PS_CALLINC_BITS 2 +#define XCHAL_PS_CALLINC_NUM 4 +#define XCHAL_PS_CALLINC_SHIFT 16 +#define XCHAL_PS_CALLINC_MASK 0x00030000 +#define XCHAL_PS_WOE_BITS 1 +#define XCHAL_PS_WOE_NUM 2 +#define XCHAL_PS_WOE_SHIFT 18 +#define XCHAL_PS_WOE_MASK 0x00040000 + +/* EXCCAUSE (special register number 232): */ + +#define XCHAL_EXCCAUSE_VALIDMASK 0x0000003F +#define XCHAL_EXCCAUSE_BITS 6 +#define XCHAL_EXCCAUSE_NUM 64 +#define XCHAL_EXCCAUSE_SHIFT 0 +#define XCHAL_EXCCAUSE_MASK 0x0000003F + +/* DEBUGCAUSE (special register number 233): */ + +#define XCHAL_DEBUGCAUSE_VALIDMASK 0x0000003F +#define XCHAL_DEBUGCAUSE_ICOUNT_BITS 1 +#define XCHAL_DEBUGCAUSE_ICOUNT_NUM 2 +#define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT 0 +#define XCHAL_DEBUGCAUSE_ICOUNT_MASK 0x00000001 +#define XCHAL_DEBUGCAUSE_IBREAK_BITS 1 +#define XCHAL_DEBUGCAUSE_IBREAK_NUM 2 +#define XCHAL_DEBUGCAUSE_IBREAK_SHIFT 1 +#define XCHAL_DEBUGCAUSE_IBREAK_MASK 0x00000002 +#define XCHAL_DEBUGCAUSE_DBREAK_BITS 1 +#define XCHAL_DEBUGCAUSE_DBREAK_NUM 2 +#define XCHAL_DEBUGCAUSE_DBREAK_SHIFT 2 +#define XCHAL_DEBUGCAUSE_DBREAK_MASK 0x00000004 +#define XCHAL_DEBUGCAUSE_BREAK_BITS 1 +#define XCHAL_DEBUGCAUSE_BREAK_NUM 2 +#define XCHAL_DEBUGCAUSE_BREAK_SHIFT 3 +#define XCHAL_DEBUGCAUSE_BREAK_MASK 0x00000008 +#define XCHAL_DEBUGCAUSE_BREAKN_BITS 1 +#define XCHAL_DEBUGCAUSE_BREAKN_NUM 2 +#define XCHAL_DEBUGCAUSE_BREAKN_SHIFT 4 +#define XCHAL_DEBUGCAUSE_BREAKN_MASK 0x00000010 +#define XCHAL_DEBUGCAUSE_DEBUGINT_BITS 1 +#define XCHAL_DEBUGCAUSE_DEBUGINT_NUM 2 +#define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT 5 +#define XCHAL_DEBUGCAUSE_DEBUGINT_MASK 0x00000020 + +/* Timers *******************************************************************/ + +/* #define XCHAL_HAVE_TIMERS XCHAL_HAVE_CCOUNT */ + +/* Internal I/D RAMS/ROMS and XLMI ******************************************/ + +#define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */ +#define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */ +#define XCHAL_NUM_DROM XCHAL_NUM_DATAROM /* (DEPRECATED) */ +#define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */ + +#define XCHAL_IROM0_VADDR XCHAL_INSTROM0_VADDR /* (DEPRECATED) */ +#define XCHAL_IROM0_PADDR XCHAL_INSTROM0_PADDR /* (DEPRECATED) */ +#define XCHAL_IROM0_SIZE XCHAL_INSTROM0_SIZE /* (DEPRECATED) */ +#define XCHAL_IROM1_VADDR XCHAL_INSTROM1_VADDR /* (DEPRECATED) */ +#define XCHAL_IROM1_PADDR XCHAL_INSTROM1_PADDR /* (DEPRECATED) */ +#define XCHAL_IROM1_SIZE XCHAL_INSTROM1_SIZE /* (DEPRECATED) */ +#define XCHAL_IRAM0_VADDR XCHAL_INSTRAM0_VADDR /* (DEPRECATED) */ +#define XCHAL_IRAM0_PADDR XCHAL_INSTRAM0_PADDR /* (DEPRECATED) */ +#define XCHAL_IRAM0_SIZE XCHAL_INSTRAM0_SIZE /* (DEPRECATED) */ +#define XCHAL_IRAM1_VADDR XCHAL_INSTRAM1_VADDR /* (DEPRECATED) */ +#define XCHAL_IRAM1_PADDR XCHAL_INSTRAM1_PADDR /* (DEPRECATED) */ +#define XCHAL_IRAM1_SIZE XCHAL_INSTRAM1_SIZE /* (DEPRECATED) */ +#define XCHAL_DROM0_VADDR XCHAL_DATAROM0_VADDR /* (DEPRECATED) */ +#define XCHAL_DROM0_PADDR XCHAL_DATAROM0_PADDR /* (DEPRECATED) */ +#define XCHAL_DROM0_SIZE XCHAL_DATAROM0_SIZE /* (DEPRECATED) */ +#define XCHAL_DROM1_VADDR XCHAL_DATAROM1_VADDR /* (DEPRECATED) */ +#define XCHAL_DROM1_PADDR XCHAL_DATAROM1_PADDR /* (DEPRECATED) */ +#define XCHAL_DROM1_SIZE XCHAL_DATAROM1_SIZE /* (DEPRECATED) */ +#define XCHAL_DRAM0_VADDR XCHAL_DATARAM0_VADDR /* (DEPRECATED) */ +#define XCHAL_DRAM0_PADDR XCHAL_DATARAM0_PADDR /* (DEPRECATED) */ +#define XCHAL_DRAM0_SIZE XCHAL_DATARAM0_SIZE /* (DEPRECATED) */ +#define XCHAL_DRAM1_VADDR XCHAL_DATARAM1_VADDR /* (DEPRECATED) */ +#define XCHAL_DRAM1_PADDR XCHAL_DATARAM1_PADDR /* (DEPRECATED) */ +#define XCHAL_DRAM1_SIZE XCHAL_DATARAM1_SIZE /* (DEPRECATED) */ + +/* Cache ********************************************************************/ + +/* Default PREFCTL value to enable prefetch. */ + +#if XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RE_2012_0 +# define XCHAL_CACHE_PREFCTL_DEFAULT 0x00044 /* Enabled, not aggressive */ +#elif XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RF_2014_0 +# define XCHAL_CACHE_PREFCTL_DEFAULT 0x01044 /* + enable prefetch to L1 */ +#elif XCHAL_PREFETCH_ENTRIES >= 16 +# define XCHAL_CACHE_PREFCTL_DEFAULT 0x81044 /* 12 entries for block ops */ +#elif XCHAL_PREFETCH_ENTRIES >= 8 +# define XCHAL_CACHE_PREFCTL_DEFAULT 0x51044 /* 5 entries for block ops */ +#else +# define XCHAL_CACHE_PREFCTL_DEFAULT 0x01044 /* 0 entries for block ops */ +#endif + +/* Max for both I-cache and D-cache (used for general alignment): */ + +#if XCHAL_ICACHE_LINESIZE > XCHAL_DCACHE_LINESIZE +# define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_ICACHE_LINEWIDTH +# define XCHAL_CACHE_LINESIZE_MAX XCHAL_ICACHE_LINESIZE +#else +# define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_DCACHE_LINEWIDTH +# define XCHAL_CACHE_LINESIZE_MAX XCHAL_DCACHE_LINESIZE +#endif + +#define XCHAL_ICACHE_SETSIZE (1 << XCHAL_ICACHE_SETWIDTH) +#define XCHAL_DCACHE_SETSIZE (1 << XCHAL_DCACHE_SETWIDTH) + +/* Max for both I and D caches (used for cache-coherency page alignment): */ + +#if XCHAL_ICACHE_SETWIDTH > XCHAL_DCACHE_SETWIDTH +# define XCHAL_CACHE_SETWIDTH_MAX XCHAL_ICACHE_SETWIDTH +# define XCHAL_CACHE_SETSIZE_MAX XCHAL_ICACHE_SETSIZE +#else +# define XCHAL_CACHE_SETWIDTH_MAX XCHAL_DCACHE_SETWIDTH +# define XCHAL_CACHE_SETSIZE_MAX XCHAL_DCACHE_SETSIZE +#endif + +/* Instruction cache tag bits: */ + +#define XCHAL_ICACHE_TAG_V_SHIFT 0 +#define XCHAL_ICACHE_TAG_V 0x1 /* Valid bit */ +#if XCHAL_ICACHE_WAYS > 1 +# define XCHAL_ICACHE_TAG_F_SHIFT 1 +# define XCHAL_ICACHE_TAG_F 0x2 /* Fill (LRU) bit */ +#else +# define XCHAL_ICACHE_TAG_F_SHIFT 0 +# define XCHAL_ICACHE_TAG_F 0 /* No fill (LRU) bit */ +#endif +#if XCHAL_ICACHE_LINE_LOCKABLE +# define XCHAL_ICACHE_TAG_L_SHIFT (XCHAL_ICACHE_TAG_F_SHIFT+1) +# define XCHAL_ICACHE_TAG_L (1 << XCHAL_ICACHE_TAG_L_SHIFT) /* Lock bit */ +#else +# define XCHAL_ICACHE_TAG_L_SHIFT XCHAL_ICACHE_TAG_F_SHIFT +# define XCHAL_ICACHE_TAG_L 0 /* No lock bit */ +#endif + +/* Data cache tag bits: */ + +#define XCHAL_DCACHE_TAG_V_SHIFT 0 +#define XCHAL_DCACHE_TAG_V 0x1 /* Valid bit */ +#if XCHAL_DCACHE_WAYS > 1 +# define XCHAL_DCACHE_TAG_F_SHIFT 1 +# define XCHAL_DCACHE_TAG_F 0x2 /* Fill (LRU) bit */ +#else +# define XCHAL_DCACHE_TAG_F_SHIFT 0 +# define XCHAL_DCACHE_TAG_F 0 /* No fill (LRU) bit */ +#endif +#if XCHAL_DCACHE_IS_WRITEBACK +# define XCHAL_DCACHE_TAG_D_SHIFT (XCHAL_DCACHE_TAG_F_SHIFT+1) +# define XCHAL_DCACHE_TAG_D (1 << XCHAL_DCACHE_TAG_D_SHIFT) /* Dirty bit */ +#else +# define XCHAL_DCACHE_TAG_D_SHIFT XCHAL_DCACHE_TAG_F_SHIFT +# define XCHAL_DCACHE_TAG_D 0 /* No dirty bit */ +#endif +#if XCHAL_DCACHE_LINE_LOCKABLE +# define XCHAL_DCACHE_TAG_L_SHIFT (XCHAL_DCACHE_TAG_D_SHIFT+1) +# define XCHAL_DCACHE_TAG_L (1 << XCHAL_DCACHE_TAG_L_SHIFT) /* Lock bit */ +#else +# define XCHAL_DCACHE_TAG_L_SHIFT XCHAL_DCACHE_TAG_D_SHIFT +# define XCHAL_DCACHE_TAG_L 0 /* No lock bit */ +#endif + +/* Whether MEMCTL register has anything useful */ + +#define XCHAL_USE_MEMCTL \ + (((XCHAL_LOOP_BUFFER_SIZE > 0) || \ + XCHAL_DCACHE_IS_COHERENT || \ + XCHAL_HAVE_ICACHE_DYN_WAYS || \ + XCHAL_HAVE_DCACHE_DYN_WAYS) && \ + (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0)) + +/* Default MEMCTL values: */ + +#if XCHAL_HAVE_ICACHE_DYN_WAYS || XCHAL_HAVE_DCACHE_DYN_WAYS + +/* NOTE: constant defined this way to allow movi instead of l32r in reset code. */ + +# define XCHAL_CACHE_MEMCTL_DEFAULT 0xFFFFFF00 /* Init all possible ways */ +#else +# define XCHAL_CACHE_MEMCTL_DEFAULT 0x00000000 /* Nothing to do */ +#endif + +#if XCHAL_DCACHE_IS_COHERENT +# define _MEMCTL_SNOOP_EN 0x02 /* Enable snoop */ +#else +# define _MEMCTL_SNOOP_EN 0x00 /* Don't enable snoop */ +#endif + +#if (XCHAL_LOOP_BUFFER_SIZE == 0) || XCHAL_ERRATUM_453 +# define _MEMCTL_L0IBUF_EN 0x00 /* No loop buffer or don't enable */ +#else +# define _MEMCTL_L0IBUF_EN 0x01 /* Enable loop buffer */ +#endif + +#define XCHAL_SNOOP_LB_MEMCTL_DEFAULT (_MEMCTL_SNOOP_EN | _MEMCTL_L0IBUF_EN) + +/* MMU **********************************************************************/ + +/* See for more details. */ + +/* Has different semantic in open source headers (where it means HAVE_PTP_MMU), + * so comment out starting with RB-2008.3 release; later, might get + * get reintroduced as a synonym for XCHAL_HAVE_PTP_MMU instead: + */ + +/* #define XCHAL_HAVE_MMU XCHAL_HAVE_TLBS*//* (DEPRECATED; use XCHAL_HAVE_TLBS instead) */ + +/* Indexing macros: */ + +#define _XCHAL_ITLB_SET(n,_what) XCHAL_ITLB_SET ## n ## _what +#define XCHAL_ITLB_SET(n,what) _XCHAL_ITLB_SET(n, _ ## what ) +#define _XCHAL_ITLB_SET_E(n,i,_what) XCHAL_ITLB_SET ## n ## _E ## i ## _what +#define XCHAL_ITLB_SET_E(n,i,what) _XCHAL_ITLB_SET_E(n,i, _ ## what ) +#define _XCHAL_DTLB_SET(n,_what) XCHAL_DTLB_SET ## n ## _what +#define XCHAL_DTLB_SET(n,what) _XCHAL_DTLB_SET(n, _ ## what ) +#define _XCHAL_DTLB_SET_E(n,i,_what) XCHAL_DTLB_SET ## n ## _E ## i ## _what +#define XCHAL_DTLB_SET_E(n,i,what) _XCHAL_DTLB_SET_E(n,i, _ ## what ) + +/* Example use: XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES) + * to get the value of XCHAL_ITLB_SET_ENTRIES where is the first auto-refill set. + */ + +/* Number of entries per autorefill way: */ + +#define XCHAL_ITLB_ARF_ENTRIES (1 << XCHAL_ITLB_ARF_ENTRIES_LOG2) +#define XCHAL_DTLB_ARF_ENTRIES (1 << XCHAL_DTLB_ARF_ENTRIES_LOG2) + +/* Determine whether we have a full MMU (with Page Table and Protection) + * usable for an MMU-based OS: + */ + +#if 0 +# if XCHAL_HAVE_TLBS && !XCHAL_HAVE_SPANNING_WAY && XCHAL_ITLB_ARF_WAYS > 0 && \ + XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2 +# define XCHAL_HAVE_PTP_MMU 1 /* Have full MMU (with page table + * [autorefill] and protection) */ +# else +# define XCHAL_HAVE_PTP_MMU 0 /* Don't have full MMU */ +# endif +#endif + +/* For full MMUs, report kernel RAM segment and kernel I/O segment static + * page mappings: + */ + +#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY +# define XCHAL_KSEG_CACHED_VADDR 0xD0000000 /* virt.addr of kernel + * RAM cached static + * map */ +# define XCHAL_KSEG_CACHED_PADDR 0x00000000 /* phys.addr of + * kseg_cached */ +# define XCHAL_KSEG_CACHED_SIZE 0x08000000 /* size in bytes of + * kseg_cached (assumed + * power of 2!!!) */ +# define XCHAL_KSEG_BYPASS_VADDR 0xD8000000 /* virt.addr of kernel + * RAM bypass + * (uncached) static + * map */ +# define XCHAL_KSEG_BYPASS_PADDR 0x00000000 /* phys.addr of + * kseg_bypass */ +# define XCHAL_KSEG_BYPASS_SIZE 0x08000000 /* size in bytes of + * kseg_bypass (assumed + * power of 2!!!) */ +# define XCHAL_KIO_CACHED_VADDR 0xE0000000 /* virt.addr of kernel + * I/O cached static + * map */ +# define XCHAL_KIO_CACHED_PADDR 0xF0000000 /* phys.addr of + * kio_cached */ +# define XCHAL_KIO_CACHED_SIZE 0x10000000 /* size in bytes of kio_cached + * (assumed power of 2!!!) */ +# define XCHAL_KIO_BYPASS_VADDR 0xF0000000 /* virt.addr of kernel + * I/O bypass + * (uncached) static + * map */ +# define XCHAL_KIO_BYPASS_PADDR 0xF0000000 /* phys.addr of + * kio_bypass */ +# define XCHAL_KIO_BYPASS_SIZE 0x10000000 /* size in bytes of kio_bypass + * (assumed power of 2!!!) */ +# define XCHAL_SEG_MAPPABLE_VADDR 0x00000000 /* start of largest + * non-static-mapped virtual + * addr area */ +# define XCHAL_SEG_MAPPABLE_SIZE 0xD0000000 /* size in bytes of " */ + +/* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of + * descending size. + */ +#endif + +/* Misc. **************************************************** + +/* Data alignment required if used for instructions: */ + +#if XCHAL_INST_FETCH_WIDTH > XCHAL_DATA_WIDTH +# define XCHAL_ALIGN_MAX XCHAL_INST_FETCH_WIDTH +#else +# define XCHAL_ALIGN_MAX XCHAL_DATA_WIDTH +#endif + +/* Names kept for backward compatibility. + * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases + * under which they are released. In the T10##.# era there was no distinction.) + */ + +#define XCHAL_HW_RELEASE_MAJOR XCHAL_HW_VERSION_MAJOR +#define XCHAL_HW_RELEASE_MINOR XCHAL_HW_VERSION_MINOR +#define XCHAL_HW_RELEASE_NAME XCHAL_HW_VERSION_NAME + +/* Co-processors and extra state ********************************************/ + +#define XCHAL_EXTRA_SA_SIZE XCHAL_NCP_SA_SIZE +#define XCHAL_EXTRA_SA_ALIGN XCHAL_NCP_SA_ALIGN +#define XCHAL_CPEXTRA_SA_SIZE XCHAL_TOTAL_SA_SIZE +#define XCHAL_CPEXTRA_SA_ALIGN XCHAL_TOTAL_SA_ALIGN + +#ifdef __ASSEMBLY__ + +/* Invoked at start of save area load/store sequence macro to setup macro + * internal offsets. Not usually invoked directly. continue 0 for 1st + * sequence, 1 for subsequent consecutive ones. totofs offset from + * original ptr to next load/store location. + */ + + .macro xchal_sa_start continue totofs + .ifeq \continue + .set .Lxchal_pofs_, 0 /* offset from original ptr to current \ptr */ + .set .Lxchal_ofs_, 0 /* offset from current \ptr to next load/store location */ + .endif + .if \totofs + 1 /* if totofs specified (not -1) */ + .set .Lxchal_ofs_, \totofs - .Lxchal_pofs_ /* specific offset from original ptr */ + .endif + .endm + +/* Align portion of save area and bring ptr in range if necessary. Used by + * save area load/store sequences. Not usually invoked directly. Allows + * combining multiple (sub-)sequences arbitrarily. ptr pointer to save + * area (may be off, see .Lxchal_pofs_) minofs,maxofs range of offset from + * cur ptr to next load/store loc; minofs <= 0 <= maxofs (0 must always be + * valid offset) range must be within +/- 30kB or so. ofsalign alignment + * granularity of minofs .. maxofs (pow of 2) (restriction on offset from + * ptr to next load/store loc) totalign align from orig ptr to next + * load/store loc (pow of 2) + */ + + .macro xchal_sa_align ptr minofs maxofs ofsalign totalign + + /* First align where we start accessing the next register + * per \totalign relative to original ptr (i.e. start of the save area): + */ + + .set .Lxchal_ofs_, ((.Lxchal_pofs_ + .Lxchal_ofs_ + \totalign - 1) & -\totalign) - .Lxchal_pofs_ + + /* If necessary, adjust \ptr to bring .Lxchal_ofs_ in acceptable range: */ + + .if (((\maxofs) - .Lxchal_ofs_) & 0xC0000000) | ((.Lxchal_ofs_ - (\minofs)) & 0xC0000000) | (.Lxchal_ofs_ & (\ofsalign-1)) + .set .Ligmask, 0xFFFFFFFF /* TODO: optimize to addmi, per aligns and .Lxchal_ofs_ */ + addi \ptr, \ptr, (.Lxchal_ofs_ & .Ligmask) + .set .Lxchal_pofs_, .Lxchal_pofs_ + (.Lxchal_ofs_ & .Ligmask) + .set .Lxchal_ofs_, (.Lxchal_ofs_ & ~.Ligmask) + .endif + .endm + +/* We could optimize for addi to expand to only addmi instead of + * "addmi;addi", where possible. Here's a partial example how: + * + * .set .Lmaxmask, -(\ofsalign) & -(\totalign) + * .if (((\maxofs) + ~.Lmaxmask + 1) & 0xFFFFFF00) && ((.Lxchal_ofs_ & ~.Lmaxmask) == 0) + * .set .Ligmask, 0xFFFFFF00 + * .elif ... ditto for negative ofs range ... + * .set .Ligmask, 0xFFFFFF00 + * .set ... adjust per offset ... + * .else + * .set .Ligmask, 0xFFFFFFFF + * .endif + * + +/* Invoke this after xchal_XXX_{load,store} macros to restore \ptr. */ + + .macro xchal_sa_ptr_restore ptr + .if .Lxchal_pofs_ + addi \ptr, \ptr, - .Lxchal_pofs_ + .set .Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_ + .set .Lxchal_pofs_, 0 + .endif + .endm + +/* Use as eg: + * xchal_atmps_store a1, SOMEOFS, XCHAL_SA_NUM_ATMPS, a4, a5 + * xchal_ncp_load a2, a0,a3,a4,a5 + * xchal_atmps_load a1, SOMEOFS, XCHAL_SA_NUM_ATMPS, a4, a5 + * + * Specify only the ARs you *haven't* saved/restored already, up to 4. + * They *must* be the *last* ARs (in same order) specified to save area + * load/store sequences. In the example above, a0 and a3 were already + * saved/restored and unused (thus available) but a4 and a5 were not. + */ + +#define xchal_atmps_store xchal_atmps_loadstore s32i, +#define xchal_atmps_load xchal_atmps_loadstore l32i, + + .macro xchal_atmps_loadstore inst ptr offset nreq aa=0 ab=0 ac=0 ad=0 + .set .Lnsaved_, 0 + .irp reg,\aa,\ab,\ac,\ad + .ifeq 0x\reg ; .set .Lnsaved_,.Lnsaved_+1 ; .endif + .endr + .set .Laofs_, 0 + .irp reg,\aa,\ab,\ac,\ad + .ifgt (\nreq)-.Lnsaved_ + \inst \reg, \ptr, .Laofs_+\offset + .set .Laofs_,.Laofs_+4 + .set .Lnsaved_,.Lnsaved_+1 + .endif + .endr + .endm + + +/* #define xchal_ncp_load_a2 xchal_ncp_load a2,a3,a4,a5,a6 */ +/* #define xchal_ncp_store_a2 xchal_ncp_store a2,a3,a4,a5,a6 */ +# define xchal_extratie_load xchal_ncptie_load +# define xchal_extratie_store xchal_ncptie_store +# define xchal_extratie_load_a2 xchal_ncptie_load a2,a3,a4,a5,a6 +# define xchal_extratie_store_a2 xchal_ncptie_store a2,a3,a4,a5,a6 +# define xchal_extra_load xchal_ncp_load +# define xchal_extra_store xchal_ncp_store +# define xchal_extra_load_a2 xchal_ncp_load a2,a3,a4,a5,a6 +# define xchal_extra_store_a2 xchal_ncp_store a2,a3,a4,a5,a6 +# define xchal_extra_load_funcbody xchal_ncp_load a2,a3,a4,a5,a6 +# define xchal_extra_store_funcbody xchal_ncp_store a2,a3,a4,a5,a6 +# define xchal_cp0_store_a2 xchal_cp0_store a2,a3,a4,a5,a6 +# define xchal_cp0_load_a2 xchal_cp0_load a2,a3,a4,a5,a6 +# define xchal_cp1_store_a2 xchal_cp1_store a2,a3,a4,a5,a6 +# define xchal_cp1_load_a2 xchal_cp1_load a2,a3,a4,a5,a6 +# define xchal_cp2_store_a2 xchal_cp2_store a2,a3,a4,a5,a6 +# define xchal_cp2_load_a2 xchal_cp2_load a2,a3,a4,a5,a6 +# define xchal_cp3_store_a2 xchal_cp3_store a2,a3,a4,a5,a6 +# define xchal_cp3_load_a2 xchal_cp3_load a2,a3,a4,a5,a6 +# define xchal_cp4_store_a2 xchal_cp4_store a2,a3,a4,a5,a6 +# define xchal_cp4_load_a2 xchal_cp4_load a2,a3,a4,a5,a6 +# define xchal_cp5_store_a2 xchal_cp5_store a2,a3,a4,a5,a6 +# define xchal_cp5_load_a2 xchal_cp5_load a2,a3,a4,a5,a6 +# define xchal_cp6_store_a2 xchal_cp6_store a2,a3,a4,a5,a6 +# define xchal_cp6_load_a2 xchal_cp6_load a2,a3,a4,a5,a6 +# define xchal_cp7_store_a2 xchal_cp7_store a2,a3,a4,a5,a6 +# define xchal_cp7_load_a2 xchal_cp7_load a2,a3,a4,a5,a6 + +/* Empty placeholder macros for undefined coprocessors: */ + +#if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) == 0 +# if XCHAL_CP0_SA_SIZE == 0 + .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +# if XCHAL_CP1_SA_SIZE == 0 + .macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +# if XCHAL_CP2_SA_SIZE == 0 + .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +# if XCHAL_CP3_SA_SIZE == 0 + .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +# if XCHAL_CP4_SA_SIZE == 0 + .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +# if XCHAL_CP5_SA_SIZE == 0 + .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +# if XCHAL_CP6_SA_SIZE == 0 + .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +# if XCHAL_CP7_SA_SIZE == 0 + .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm +# endif +#endif + +/* Macros to create functions that save and restore the state of *any* TIE + * coprocessor (by dynamic index). + */ + +/* Macro that expands to the body of a function that stores the selected + * coprocessor's state (registers etc). + * + * Entry: a2 = ptr to save area in which to save cp state + * a3 = coprocessor number + * Exit: any register a2-a15 (?) may have been clobbered. + */ + + .macro xchal_cpi_store_funcbody +#if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) +# if XCHAL_CP0_SA_SIZE + bnez a3, 99f + xchal_cp0_store_a2 + j 90f +99: +# endif +# if XCHAL_CP1_SA_SIZE + bnei a3, 1, 99f + xchal_cp1_store_a2 + j 90f +99: +# endif +# if XCHAL_CP2_SA_SIZE + bnei a3, 2, 99f + xchal_cp2_store_a2 + j 90f +99: +# endif +# if XCHAL_CP3_SA_SIZE + bnei a3, 3, 99f + xchal_cp3_store_a2 + j 90f +99: +# endif +# if XCHAL_CP4_SA_SIZE + bnei a3, 4, 99f + xchal_cp4_store_a2 + j 90f +99: +# endif +# if XCHAL_CP5_SA_SIZE + bnei a3, 5, 99f + xchal_cp5_store_a2 + j 90f +99: +# endif +# if XCHAL_CP6_SA_SIZE + bnei a3, 6, 99f + xchal_cp6_store_a2 + j 90f +99: +# endif +# if XCHAL_CP7_SA_SIZE + bnei a3, 7, 99f + xchal_cp7_store_a2 + j 90f +99: +# endif +90: +#endif + +/* Macro that expands to the body of a function that loads the selected coprocessor's state + * (registers etc). + * + * Entry: a2 = ptr to save area from which to restore cp state + * a3 = coprocessor number + * Exit: any register a2-a15 (?) may have been clobbered. + */ + + .macro xchal_cpi_load_funcbody +#if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) +# if XCHAL_CP0_SA_SIZE + bnez a3, 99f + xchal_cp0_load_a2 + j 90f +99: +# endif +# if XCHAL_CP1_SA_SIZE + bnei a3, 1, 99f + xchal_cp1_load_a2 + j 90f +99: +# endif +# if XCHAL_CP2_SA_SIZE + bnei a3, 2, 99f + xchal_cp2_load_a2 + j 90f +99: +# endif +# if XCHAL_CP3_SA_SIZE + bnei a3, 3, 99f + xchal_cp3_load_a2 + j 90f +99: +# endif +# if XCHAL_CP4_SA_SIZE + bnei a3, 4, 99f + xchal_cp4_load_a2 + j 90f +99: +# endif +# if XCHAL_CP5_SA_SIZE + bnei a3, 5, 99f + xchal_cp5_load_a2 + j 90f +99: +# endif +# if XCHAL_CP6_SA_SIZE + bnei a3, 6, 99f + xchal_cp6_load_a2 + j 90f +99: +# endif +# if XCHAL_CP7_SA_SIZE + bnei a3, 7, 99f + xchal_cp7_load_a2 + j 90f +99: +# endif +90: +#endif + .endm + +#endif /* __ASSEMBLY__ */ + +/* Other default macros for undefined coprocessors: */ + +#ifndef XCHAL_CP0_NAME +# define XCHAL_CP0_NAME 0 +# define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP1_NAME +# define XCHAL_CP1_NAME 0 +# define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP2_NAME +# define XCHAL_CP2_NAME 0 +# define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP3_NAME +# define XCHAL_CP3_NAME 0 +# define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP4_NAME +# define XCHAL_CP4_NAME 0 +# define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP5_NAME +# define XCHAL_CP5_NAME 0 +# define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP6_NAME +# define XCHAL_CP6_NAME 0 +# define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP7_NAME +# define XCHAL_CP7_NAME 0 +# define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */ +#endif + +#if XCHAL_CP_MASK == 0 +/* Filler info for unassigned coprocessors, to simplify arrays etc: */ + +# define XCHAL_CP0_SA_SIZE 0 +# define XCHAL_CP0_SA_ALIGN 1 +# define XCHAL_CP1_SA_SIZE 0 +# define XCHAL_CP1_SA_ALIGN 1 +# define XCHAL_CP2_SA_SIZE 0 +# define XCHAL_CP2_SA_ALIGN 1 +# define XCHAL_CP3_SA_SIZE 0 +# define XCHAL_CP3_SA_ALIGN 1 +# define XCHAL_CP4_SA_SIZE 0 +# define XCHAL_CP4_SA_ALIGN 1 +# define XCHAL_CP5_SA_SIZE 0 +# define XCHAL_CP5_SA_ALIGN 1 +# define XCHAL_CP6_SA_SIZE 0 +# define XCHAL_CP6_SA_ALIGN 1 +# define XCHAL_CP7_SA_SIZE 0 +# define XCHAL_CP7_SA_ALIGN 1 +#endif + +/* Indexing macros: */ + +#define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE +#define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */ +#define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN +#define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */ +#define XCHAL_CPEXTRA_SA_SIZE_TOR2 XCHAL_CPEXTRA_SA_SIZE /* Tor2Beta only - do not use */ + +/* Link-time HAL global variables that report coprocessor numbers by name + * (names are case-preserved from the original TIE): + */ + + #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) +# define _XCJOIN(a,b) a ## b +# define XCJOIN(a,b) _XCJOIN(a,b) +# ifdef XCHAL_CP0_NAME + extern const unsigned char XCJOIN(Xthal_cp_id_, XCHAL_CP0_IDENT); + extern const unsigned int XCJOIN(Xthal_cp_mask_, XCHAL_CP0_IDENT); +# endif +# ifdef XCHAL_CP1_NAME + extern const unsigned char XCJOIN(Xthal_cp_id_, XCHAL_CP1_IDENT); + extern const unsigned int XCJOIN(Xthal_cp_mask_, XCHAL_CP1_IDENT); +# endif +# ifdef XCHAL_CP2_NAME + extern const unsigned char XCJOIN(Xthal_cp_id_, XCHAL_CP2_IDENT); + extern const unsigned int XCJOIN(Xthal_cp_mask_, XCHAL_CP2_IDENT); +# endif +# ifdef XCHAL_CP3_NAME + extern const unsigned char XCJOIN(Xthal_cp_id_, XCHAL_CP3_IDENT); + extern const unsigned int XCJOIN(Xthal_cp_mask_, XCHAL_CP3_IDENT); +# endif +# ifdef XCHAL_CP4_NAME + extern const unsigned char XCJOIN(Xthal_cp_id_, XCHAL_CP4_IDENT); + extern const unsigned int XCJOIN(Xthal_cp_mask_, XCHAL_CP4_IDENT); +# endif +# ifdef XCHAL_CP5_NAME + extern const unsigned char XCJOIN(Xthal_cp_id_, XCHAL_CP5_IDENT); + extern const unsigned int XCJOIN(Xthal_cp_mask_, XCHAL_CP5_IDENT); +# endif +# ifdef XCHAL_CP6_NAME + extern const unsigned char XCJOIN(Xthal_cp_id_, XCHAL_CP6_IDENT); + extern const unsigned int XCJOIN(Xthal_cp_mask_, XCHAL_CP6_IDENT); +# endif +# ifdef XCHAL_CP7_NAME + extern const unsigned char XCJOIN(Xthal_cp_id_, XCHAL_CP7_IDENT); + extern const unsigned int XCJOIN(Xthal_cp_mask_, XCHAL_CP7_IDENT); +# endif +#endif + +/* Derived ******************************************************************/ + +#if XCHAL_HAVE_BE +# define XCHAL_INST_ILLN 0xD60F /* 2-byte illegal instruction, + * msb-first */ +# define XCHAL_INST_ILLN_BYTE0 0xD6 /* 2-byte illegal instruction, + * 1st byte */ +# define XCHAL_INST_ILLN_BYTE1 0x0F /* 2-byte illegal instruction, + * 2nd byte */ +#else +# define XCHAL_INST_ILLN 0xF06D /* 2-byte illegal instruction, + * lsb-first */ +# define XCHAL_INST_ILLN_BYTE0 0x6D /* 2-byte illegal instruction, + * 1st byte */ +# define XCHAL_INST_ILLN_BYTE1 0xF0 /* 2-byte illegal instruction, + * 2nd byte */ +#endif + +/* Belongs in xtensa/hal.h: */ + +#define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */ + +/* Because information as to exactly which hardware version is targeted + * by a given software build is not always available, compile-time HAL + * Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE): + * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases + * under which they are released. In the T10##.# era there was no distinction.) + */ + +#if XCHAL_HW_CONFIGID_RELIABLE +# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) (XTHAL_REL_LE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) +# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) (XTHAL_REL_GE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) +# define XCHAL_HW_RELEASE_AT(major,minor) (XTHAL_REL_EQ( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) +# define XCHAL_HW_RELEASE_MAJOR_AT(major) ((XCHAL_HW_VERSION_MAJOR == (major)) ? 1 : 0) +#else +# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \ + : ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \ + : XTHAL_MAYBE ) +# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \ + : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \ + : XTHAL_MAYBE ) +# define XCHAL_HW_RELEASE_AT(major,minor) ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \ + ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE) +# define XCHAL_HW_RELEASE_MAJOR_AT(major) XCHAL_HW_RELEASE_AT(major,0) +#endif + +/* Specific errata: */ + +/* Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1; + * relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled): + */ + +#define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN \ + (XCHAL_HAVE_XEA1 && \ + (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 || \ + XCHAL_HW_RELEASE_AT(1050,0))) + +/* Erratum 453 present in RE-2013.2 up to RF-2014.0, fixed in RF-2014.1. + * Applies to specific set of configuration options. + * Part of the workaround is to add ISYNC at certain points in the code. + * The workaround gated by this macro can be disabled if not needed, e.g. if + * zero-overhead loop buffer will be disabled, by defining _NO_ERRATUM_453. + */ + +#if (XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RE_2013_2 && \ + XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2014_0 && \ + XCHAL_ICACHE_SIZE != 0 && XCHAL_HAVE_PIF /*covers also AXI/AHB*/ && \ + XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE != 0 && \ + XCHAL_CLOCK_GATING_GLOBAL && !defined(_NO_ERRATUM_453)) +# define XCHAL_ERRATUM_453 1 +#else +# define XCHAL_ERRATUM_453 0 +#endif + +/* Erratum 497 present in RE-2012.2 up to RG/RF-2015.2 + * Applies to specific set of configuration options. + * Workaround is to add MEMWs after at most 8 cache WB instructions + */ + +#if (((XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RE_2012_0 && \ + XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2015_2) || \ + (XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RG_2015_0 && \ + XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RG_2015_2)) && \ + XCHAL_DCACHE_IS_WRITEBACK && \ + XCHAL_HAVE_AXI && \ + XCHAL_HAVE_PIF_WR_RESP && \ + XCHAL_HAVE_PIF_REQ_ATTR && !defined(_NO_ERRATUM_497)) +# define XCHAL_ERRATUM_497 1 +#else +# define XCHAL_ERRATUM_497 0 +#endif + +#endif /*__ARCH_XTENSA_INCUDE_XTENSA_CORE_H*/ diff --git a/arch/xtensa/src/common/xtensa_timer.h b/arch/xtensa/src/common/xtensa_timer.h index b4fdf357ef..f9eadbe983 100644 --- a/arch/xtensa/src/common/xtensa_timer.h +++ b/arch/xtensa/src/common/xtensa_timer.h @@ -34,11 +34,12 @@ #define __ARCH_XTENSA_SRC_COMMON_XTENSA_TIMER_H #ifdef __ASSEMBLER__ -#include +#include #endif -#include -#include +#include +#include +#include /* Select timer to use for periodic tick, and determine its interrupt number * and priority. User may specify a timer by defining XT_TIMER_INDEX with -D, -- GitLab From 2b33768d090ed67a193c27d40c11a0058214925a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 23 Oct 2016 10:39:51 -0600 Subject: [PATCH 186/734] Xtensa: Revert back to some XCHAL naming --- arch/xtensa/src/common/xtensa_timer.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_timer.h b/arch/xtensa/src/common/xtensa_timer.h index db8c527b94..ccdfaad3bf 100644 --- a/arch/xtensa/src/common/xtensa_timer.h +++ b/arch/xtensa/src/common/xtensa_timer.h @@ -56,25 +56,25 @@ #ifndef XT_TIMER_INDEX # if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED -# if XTENSA_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL +# if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL # undef XT_TIMER_INDEX # define XT_TIMER_INDEX 3 # endif # endif # if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED -# if XTENSA_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL +# if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL # undef XT_TIMER_INDEX # define XT_TIMER_INDEX 2 # endif # endif # if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED -# if XTENSA_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL +# if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL # undef XT_TIMER_INDEX # define XT_TIMER_INDEX 1 # endif # endif # if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED -# if XTENSA_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL +# if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL # undef XT_TIMER_INDEX # define XT_TIMER_INDEX 0 # endif @@ -86,7 +86,7 @@ #define XT_CCOMPARE (CCOMPARE + XT_TIMER_INDEX) #define XT_TIMER_INTNUM XTENSA_TIMER_INTERRUPT(XT_TIMER_INDEX) -#define XT_TIMER_INTPRI XTENSA_INT_LEVEL(XT_TIMER_INTNUM) +#define XT_TIMER_INTPRI XCHAL_INT_LEVEL(XT_TIMER_INTNUM) #define XT_TIMER_INTEN (1 << XT_TIMER_INTNUM) #if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED -- GitLab From 1fcced12ebd524264d2d7c436042f057c23591b7 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 23 Oct 2016 11:31:48 -0600 Subject: [PATCH 187/734] Xtensa: Timer code now compiles okay --- arch/xtensa/include/esp32/core-isa.h | 1 + arch/xtensa/include/xtensa/core.h | 8 +++---- arch/xtensa/src/common/xtensa_timer.h | 20 ++++++++--------- arch/xtensa/src/esp32/esp32_timerisr.c | 30 +++++++++++--------------- configs/esp32-core/include/board.h | 4 ++++ 5 files changed, 31 insertions(+), 32 deletions(-) diff --git a/arch/xtensa/include/esp32/core-isa.h b/arch/xtensa/include/esp32/core-isa.h index 1465a3a459..1204a26b8d 100644 --- a/arch/xtensa/include/esp32/core-isa.h +++ b/arch/xtensa/include/esp32/core-isa.h @@ -443,6 +443,7 @@ /* Interrupt numbers assigned to specific interrupt sources: */ +#define XTHAL_TIMER_UNCONFIGURED -1 /* REVISIT: should be in hal.h */ #define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ #define XCHAL_TIMER1_INTERRUPT 15 /* CCOMPARE1 */ #define XCHAL_TIMER2_INTERRUPT 16 /* CCOMPARE2 */ diff --git a/arch/xtensa/include/xtensa/core.h b/arch/xtensa/include/xtensa/core.h index 8a17c7a2ff..ae9f01ab30 100644 --- a/arch/xtensa/include/xtensa/core.h +++ b/arch/xtensa/include/xtensa/core.h @@ -685,10 +685,10 @@ /* Internal I/D RAMS/ROMS and XLMI ******************************************/ -#define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */ -#define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */ -#define XCHAL_NUM_DROM XCHAL_NUM_DATAROM /* (DEPRECATED) */ -#define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */ +#define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */ +#define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */ +#define XCHAL_NUM_DROM XCHAL_NUM_DATAROM /* (DEPRECATED) */ +#define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */ #define XCHAL_IROM0_VADDR XCHAL_INSTROM0_VADDR /* (DEPRECATED) */ #define XCHAL_IROM0_PADDR XCHAL_INSTROM0_PADDR /* (DEPRECATED) */ diff --git a/arch/xtensa/src/common/xtensa_timer.h b/arch/xtensa/src/common/xtensa_timer.h index ccdfaad3bf..0a4429633b 100644 --- a/arch/xtensa/src/common/xtensa_timer.h +++ b/arch/xtensa/src/common/xtensa_timer.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/common/xtensa_irq.S + * arch/xtensa/src/common/xtensa_timer.h * * Adapted from use in NuttX by: * @@ -34,12 +34,12 @@ #define __ARCH_XTENSA_SRC_COMMON_XTENSA_TIMER_H #ifdef __ASSEMBLER__ -#include +# include #endif #include #include -//#include +#include /* Select timer to use for periodic tick, and determine its interrupt number * and priority. User may specify a timer by defining XT_TIMER_INDEX with -D, @@ -85,7 +85,7 @@ #endif #define XT_CCOMPARE (CCOMPARE + XT_TIMER_INDEX) -#define XT_TIMER_INTNUM XTENSA_TIMER_INTERRUPT(XT_TIMER_INDEX) +#define XT_TIMER_INTNUM XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX) #define XT_TIMER_INTPRI XCHAL_INT_LEVEL(XT_TIMER_INTNUM) #define XT_TIMER_INTEN (1 << XT_TIMER_INTNUM) @@ -115,12 +115,12 @@ * anyway!). */ -#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ) -# define XT_CLOCK_FREQ +#if defined(XT_SIMULATOR) && !defined(BOARD_CLOCK_FREQUENCY) +# define BOARD_CLOCK_FREQUENCY #endif -#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD) -# error "XT_CLOCK_FREQ must be defined for the target platform." +#if !defined(BOARD_CLOCK_FREQUENCY) && !defined(XT_BOARD) +# warning "BOARD_CLOCK_FREQUENCY must be defined for the target platform." #endif /* Default number of timer "ticks" per second (default 100 for 10ms tick). @@ -136,8 +136,8 @@ /* Derivation of clock divisor for timer tick and interrupt (one per tick). */ -#ifdef XT_CLOCK_FREQ -# define XT_TICK_DIVISOR (XT_CLOCK_FREQ / XT_TICK_PER_SEC) +#ifdef BOARD_CLOCK_FREQUENCY +# define XT_TICK_DIVISOR (BOARD_CLOCK_FREQUENCY / XT_TICK_PER_SEC) #endif #ifndef __ASSEMBLER__ diff --git a/arch/xtensa/src/esp32/esp32_timerisr.c b/arch/xtensa/src/esp32/esp32_timerisr.c index 6ff272d0f4..982b3bfa3c 100644 --- a/arch/xtensa/src/esp32/esp32_timerisr.c +++ b/arch/xtensa/src/esp32/esp32_timerisr.c @@ -44,20 +44,13 @@ #include #include -#include #include +#include #include "clock/clock.h" #include "xtensa_timer.h" #include "xtensa.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#warning REVISIT .. Need XT_CLOCK_FREQ -#define XT_CLOCK_FREQ 80000000 - /**************************************************************************** * Private data ****************************************************************************/ @@ -99,7 +92,7 @@ static inline uint32_t xtensa_getcompare(void) __asm__ __volatile__ ( - "rsr %0, XT_CCOMPARE" : "=r"(compare) + "rsr %0, %1" : "=r"(compare) : "I"(XT_CCOMPARE) ); return compare; @@ -111,7 +104,7 @@ static inline void xtensa_setcompare(uint32_t compare) { __asm__ __volatile__ ( - "wsr %0, XT_CCOMPARE" : : "r"(compare) + "wsr %0, %1" : : "r"(compare), "I"(XT_CCOMPARE) ); } @@ -123,10 +116,11 @@ static inline void xtensa_enable_timer(void) { __asm__ __volatile__ ( - "rsr a2, INTENABLE\n" - "ori a2, XT_TIMER_INTEN\n" - "wsr a2, INTENABLE\n" - : : : "a2" + "movi a3, %0\n" + "rsr a2, INTENABLE\n" + "or a2, a2, a3\n" + "wsr a2, INTENABLE\n" + : : "I"(XT_TIMER_INTEN) : "a2", "a3" ); } @@ -198,14 +192,14 @@ void xtensa_timer_initialize(void) /* Configured the timer0 as the system timer. * - * divisor = XT_CLOCK_FREQ / ticks_per_sec - * = XT_CLOCK_FREQ / (ticks_per_usec * 1000000) - * = (1000000 * XT_CLOCK_FREQ) / ticks_per_usec + * divisor = BOARD_CLOCK_FREQUENCY / ticks_per_sec + * = BOARD_CLOCK_FREQUENCY / (ticks_per_usec * 1000000) + * = (1000000 * BOARD_CLOCK_FREQUENCY) / ticks_per_usec * * A long long calculation is used to preserve accuracy in all cases. */ - divisor = (1000000ull * (uint64_t)XT_CLOCK_FREQ) / CONFIG_USEC_PER_TICK; + divisor = (1000000ull * (uint64_t)BOARD_CLOCK_FREQUENCY) / CONFIG_USEC_PER_TICK; DEBUGASSERT(divisor <= UINT32_MAX) g_tick_divisor = divisor; diff --git a/configs/esp32-core/include/board.h b/configs/esp32-core/include/board.h index 678a3c1e5e..94dcebef32 100644 --- a/configs/esp32-core/include/board.h +++ b/configs/esp32-core/include/board.h @@ -40,4 +40,8 @@ * Pre-processor Definitions ****************************************************************************/ +/* Clocking ****************************************************************/ + +#define BOARD_CLOCK_FREQUENCY 80000000 + #endif /* __CONFIGS_ESP32_CORE_INCLUDE_BOARD_H */ -- GitLab From 6bbe55602cd5816f5aeeeb2bdfead2de6fe2dbc5 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 23 Oct 2016 13:25:41 -0600 Subject: [PATCH 188/734] Xtensa: Add tie.h --- arch/xtensa/Kconfig | 6 +- arch/xtensa/include/esp32/tie.h | 193 +++++++++++++++++++ arch/xtensa/include/xtensa/core.h | 2 +- arch/xtensa/src/common/xtensa_initialstate.c | 5 +- 4 files changed, 198 insertions(+), 8 deletions(-) create mode 100644 arch/xtensa/include/esp32/tie.h diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 7d6ab3d343..a163955de3 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -31,12 +31,8 @@ config ARCH_FAMILY_LX6 Cadence® Tensilica® Xtensa® LX6 data plane processing unit (DPU). The LX6 is a configurable and extensible processor core. -config XTENSA_NCOPROCESSORS - int "Number of co-processors" - default 1 - config XTENSA_CALL0_ABI - bool "CALL0 ABI" + bool default y ---help--- The Window ABI is not supported. Only the CALL0 ABI is supported in the diff --git a/arch/xtensa/include/esp32/tie.h b/arch/xtensa/include/esp32/tie.h new file mode 100644 index 0000000000..8bc24b342d --- /dev/null +++ b/arch/xtensa/include/esp32/tie.h @@ -0,0 +1,193 @@ +/**************************************************************************** + * arch/xtensa/include/esp32/tie.h + * Compile-time HAL definitions dependent on CORE & TIE configuration + * + * NOTE: This header file is not meant to be included directly. + * + * This header file describes this specific Xtensa processor's TIE extensions + * that extend basic Xtensa core functionality. It is customized to this + * Xtensa processor configuration. + * + * Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + +#ifndef _ARCH_XTENSA_INCLUDE_ESP32_TIE_H +#define _ARCH_XTENSA_INCLUDE_ESP32_TIE_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define XCHAL_CP_NUM 1 /* number of coprocessors */ +#define XCHAL_CP_MAX 1 /* max CP ID + 1 (0 if none) */ +#define XCHAL_CP_MASK 0x01 /* bitmask of all CPs by ID */ +#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ + +/* Basic parameters of each coprocessor: */ + +#define XCHAL_CP0_NAME "FPU" +#define XCHAL_CP0_IDENT FPU +#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */ +#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */ +#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */ + +/* Filler info for unassigned coprocessors, to simplify arrays etc: */ + +#define XCHAL_CP1_SA_SIZE 0 +#define XCHAL_CP1_SA_ALIGN 1 +#define XCHAL_CP2_SA_SIZE 0 +#define XCHAL_CP2_SA_ALIGN 1 +#define XCHAL_CP3_SA_SIZE 0 +#define XCHAL_CP3_SA_ALIGN 1 +#define XCHAL_CP4_SA_SIZE 0 +#define XCHAL_CP4_SA_ALIGN 1 +#define XCHAL_CP5_SA_SIZE 0 +#define XCHAL_CP5_SA_ALIGN 1 +#define XCHAL_CP6_SA_SIZE 0 +#define XCHAL_CP6_SA_ALIGN 1 +#define XCHAL_CP7_SA_SIZE 0 +#define XCHAL_CP7_SA_ALIGN 1 + +/* Save area for non-coprocessor optional and custom (TIE) state: */ + +#define XCHAL_NCP_SA_SIZE 48 +#define XCHAL_NCP_SA_ALIGN 4 + +/* Total save area for optional and custom state (NCP + CPn): */ + +#define XCHAL_TOTAL_SA_SIZE 128 /* with 16-byte align padding */ +#define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */ + +/* Detailed contents of save areas. + * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) + * before expanding the XCHAL_xxx_SA_LIST() macros. + * + * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, + * dbnum,base,regnum,bitsz,gapsz,reset,x...) + * + * s = passed from XCHAL_*_LIST(s), eg. to select how to expand + * ccused = set if used by compiler without special options or code + * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) + * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) + * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) + * name = lowercase reg name (no quotes) + * galign = group byte alignment (power of 2) (galign >= align) + * align = register byte alignment (power of 2) + * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) + * (not including any pad bytes required to galign this or next reg) + * dbnum = unique target number f/debug (see ) + * base = reg shortname w/o index (or sr=special, ur=TIE user reg) + * regnum = reg index in regfile, or special/TIE-user reg number + * bitsz = number of significant bits (regfile width, or ur/sr mask bits) + * gapsz = intervening bits, if bitsz bits not stored contiguously + * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) + * reset = register reset value (or 0 if undefined at reset) + * x = reserved for future use (0 until then) + * + * To filter out certain registers, e.g. to expand only the non-global + * registers used by the compiler, you can do something like this: + * + * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) + * #define SELCC0(p...) + * #define SELCC1(abikind,p...) SELAK##abikind(p) + * #define SELAK0(p...) REG(p) + * #define SELAK1(p...) REG(p) + * #define SELAK2(p...) + * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ + * ...what you want to expand... + */ + +#define XCHAL_NCP_SA_NUM 12 +#define XCHAL_NCP_SA_LIST(s) \ + XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \ + XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ + XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, f64r_lo, 4, 4, 4,0x03EA, ur,234, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, f64r_hi, 4, 4, 4,0x03EB, ur,235, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, f64s, 4, 4, 4,0x03EC, ur,236, 32,0,0,0) + +#define XCHAL_CP0_SA_NUM 18 +#define XCHAL_CP0_SA_LIST(s) \ + XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, fsr, 4, 4, 4,0x03E9, ur,233, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f0, 4, 4, 4,0x0030, f,0 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f1, 4, 4, 4,0x0031, f,1 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f2, 4, 4, 4,0x0032, f,2 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f3, 4, 4, 4,0x0033, f,3 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f4, 4, 4, 4,0x0034, f,4 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f5, 4, 4, 4,0x0035, f,5 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f6, 4, 4, 4,0x0036, f,6 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f7, 4, 4, 4,0x0037, f,7 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f8, 4, 4, 4,0x0038, f,8 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f9, 4, 4, 4,0x0039, f,9 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f10, 4, 4, 4,0x003A, f,10 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f11, 4, 4, 4,0x003B, f,11 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f12, 4, 4, 4,0x003C, f,12 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f13, 4, 4, 4,0x003D, f,13 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f14, 4, 4, 4,0x003E, f,14 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f15, 4, 4, 4,0x003F, f,15 , 32,0,0,0) + +#define XCHAL_CP1_SA_NUM 0 +#define XCHAL_CP1_SA_LIST(s) /* empty */ + +#define XCHAL_CP2_SA_NUM 0 +#define XCHAL_CP2_SA_LIST(s) /* empty */ + +#define XCHAL_CP3_SA_NUM 0 +#define XCHAL_CP3_SA_LIST(s) /* empty */ + +#define XCHAL_CP4_SA_NUM 0 +#define XCHAL_CP4_SA_LIST(s) /* empty */ + +#define XCHAL_CP5_SA_NUM 0 +#define XCHAL_CP5_SA_LIST(s) /* empty */ + +#define XCHAL_CP6_SA_NUM 0 +#define XCHAL_CP6_SA_LIST(s) /* empty */ + +#define XCHAL_CP7_SA_NUM 0 +#define XCHAL_CP7_SA_LIST(s) /* empty */ + +/* Byte length of instruction from its first nibble (op0 field), per FLIX. */ + +#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 + +/* Byte length of instruction from its first byte, per FLIX. */ + +#define XCHAL_BYTE0_FORMAT_LENGTHS \ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 + +#endif /*_ARCH_XTENSA_INCLUDE_ESP32_TIE_H*/ diff --git a/arch/xtensa/include/xtensa/core.h b/arch/xtensa/include/xtensa/core.h index ae9f01ab30..b8aac7dbed 100644 --- a/arch/xtensa/include/xtensa/core.h +++ b/arch/xtensa/include/xtensa/core.h @@ -55,7 +55,7 @@ #include //#include -//#include +#include #ifdef __ASSEMBLY__ //# include diff --git a/arch/xtensa/src/common/xtensa_initialstate.c b/arch/xtensa/src/common/xtensa_initialstate.c index cce4e0c467..a5e76565f1 100644 --- a/arch/xtensa/src/common/xtensa_initialstate.c +++ b/arch/xtensa/src/common/xtensa_initialstate.c @@ -45,6 +45,7 @@ #include #include +#include #include #include @@ -71,7 +72,7 @@ void up_initial_state(struct tcb_s *tcb) { struct xcptcontext *xcp = &tcb->xcp; #if 0 /* REVISIT */ -#if CONFIG_XTENSA_NCOPROCESSORS > 0 +#if XCHAL_CP_NUM > 0 uint32_t *ptr; #endif #endif /* REVISIT */ @@ -101,7 +102,7 @@ void up_initial_state(struct tcb_s *tcb) #warning REVISIT co-processor support #if 0 /* REVISIT */ -#if CONFIG_XTENSA_NCOPROCESSORS > 0 +#if XCHAL_CP_NUM > 0 /* Init the coprocessor save area (see xtensa_context.h) * * No access to TCB here, so derive indirectly. Stack growth is top to bottom. -- GitLab From 1166d444415036c49af96f8344f1633e12cc131f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 23 Oct 2016 13:37:40 -0600 Subject: [PATCH 189/734] Minor improvement to the up_irq_save() implementation --- arch/xtensa/include/irq.h | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index 7432441f94..4082567501 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -210,23 +210,17 @@ static inline void up_irq_restore(uint32_t ps) static inline uint32_t up_irq_save(void) { - /* Get the current value of the PS for return */ - - uint32_t ps = xtensa_getps(); + uint32_t ps; /* Disable all low- and medium-priority interrupts. High priority * interrupts should not interfere with ongoing RTOS operations and * are not disabled. - * - * NOTE: We also assume that since we were called from C logic, the - * EXCM must already be cleared. */ -#ifdef CONFIG_XTENSA_CALL0_ABI - xtensa_setps(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM); -#else - xtensa_setps(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE); -#endif + __asm__ __volatile__ + ( + "psil %0, %1" : "=r"(ps) : "I"(XCHAL_EXCM_LEVEL) + ); /* Return the previous PS value so that it can be restored with * up_irq_restore(). -- GitLab From a41c98952cc7c13233afa01d9c8b168923739261 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 23 Oct 2016 13:33:48 -0600 Subject: [PATCH 190/734] Xtensa: Fix some compilation issues --- arch/xtensa/include/irq.h | 2 +- arch/xtensa/src/lx6/Toolchain.defs | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index 4082567501..c973d0fe45 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -219,7 +219,7 @@ static inline uint32_t up_irq_save(void) __asm__ __volatile__ ( - "psil %0, %1" : "=r"(ps) : "I"(XCHAL_EXCM_LEVEL) + "rsil %0, %1" : "=r"(ps) : "I"(XCHAL_EXCM_LEVEL) ); /* Return the previous PS value so that it can be restored with diff --git a/arch/xtensa/src/lx6/Toolchain.defs b/arch/xtensa/src/lx6/Toolchain.defs index b18659fe55..7e810c5498 100644 --- a/arch/xtensa/src/lx6/Toolchain.defs +++ b/arch/xtensa/src/lx6/Toolchain.defs @@ -33,4 +33,26 @@ # ############################################################################ + +# Supported toolchains +# +# Each toolchain definition should set: +# +# CROSSDEV The GNU toolchain triple (command prefix) +# ARCROSSDEV If required, an alternative prefix used when +# invoking ar and nm. +# ARCHCPUFLAGS CPU-specific flags selecting the instruction set +# FPU options, etc. +# MAXOPTIMIZATION The maximum optimization level that results in +# reliable code generation. +# + CROSSDEV = xtensa-esp32-elf- + +ARCHCPUFLAGS = + +ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) + MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL) +else + MAXOPTIMIZATION := -Os +endif -- GitLab From 9a9488ae92bcfa5883b90b0ff6ae03058aff33ab Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 23 Oct 2016 14:20:03 -0600 Subject: [PATCH 191/734] ESP32: Fix heap initialization --- arch/xtensa/src/common/xtensa.h | 12 ++++-------- arch/xtensa/src/esp32/esp32_allocateheap.c | 6 ++++-- arch/xtensa/src/esp32/esp32_start.c | 10 ---------- configs/esp32-core/scripts/esp32.template | 2 +- configs/esp32-core/scripts/esp32_common.ld | 15 +++++++++------ 5 files changed, 18 insertions(+), 27 deletions(-) diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index 3065911cf0..31a49e16e2 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -183,18 +183,14 @@ extern void g_intstackbase; extern uint32_t _init_start; /* Start of initialization logic */ extern uint32_t _stext; /* Start of .text */ extern uint32_t _etext; /* End+1 of .text + .rodata */ -extern const uint32_t _data_loaddr; /* Start of .data in FLASH */ extern uint32_t _sdata; /* Start of .data */ extern uint32_t _edata; /* End+1 of .data */ +extern uint32_t _srodata; /* Start of .rodata */ +extern uint32_t _erodata; /* End+1 of .rodata */ extern uint32_t _sbss; /* Start of .bss */ extern uint32_t _ebss; /* End+1 of .bss */ -#ifdef CONFIG_ARCH_RAMFUNCS -extern uint32_t _sramfunc; /* Start of ramfuncs */ -extern uint32_t _eramfunc; /* End+1 of ramfuncs */ -extern uint32_t _ramfunc_loadaddr; /* Start of ramfuncs in FLASH */ -extern uint32_t _ramfunc_sizeof; /* Size of ramfuncs */ -#endif /* CONFIG_ARCH_RAMFUNCS */ -#endif /* __ASSEMBLY__ */ +extern uint32_t _sheap; /* Start of heap */ +extern uint32_t _eheap; /* End+1 of heap */ /**************************************************************************** * Inline Functions diff --git a/arch/xtensa/src/esp32/esp32_allocateheap.c b/arch/xtensa/src/esp32/esp32_allocateheap.c index 4e613adc6d..c0b3b82218 100644 --- a/arch/xtensa/src/esp32/esp32_allocateheap.c +++ b/arch/xtensa/src/esp32/esp32_allocateheap.c @@ -67,11 +67,13 @@ * ****************************************************************************/ +#warning REVISIT heap. Do what with non-heterogeneous memory? + void up_allocate_heap(FAR void **heap_start, size_t *heap_size) { board_autoled_on(LED_HEAPALLOCATE); - *heap_start = (FAR void *)g_idle_topstack; - *heap_size = CONFIG_RAM_END - g_idle_topstack; + *heap_start = (FAR void *)&_sheap; + *heap_size = (size_t)((uintptr_t)&_eheap - (uintptr_t)&_sheap); } /**************************************************************************** diff --git a/arch/xtensa/src/esp32/esp32_start.c b/arch/xtensa/src/esp32/esp32_start.c index 3d1ca5c9b9..c52924a94e 100644 --- a/arch/xtensa/src/esp32/esp32_start.c +++ b/arch/xtensa/src/esp32/esp32_start.c @@ -85,16 +85,6 @@ void IRAM_ATTR __start(void) memset(&_sbss, 0, (&_ebss - &_sbss) * sizeof(_sbss)); -#warning Missing logic: Initialize .data - -#warning REVISIT heap. Do what with non-heterogeneous memory? -#warning REVISIT belongs in up_allocateheap() -#if 0 - /* Initialize heap allocator */ - - heap_alloc_caps_init(); -#endif - /* Make sure that the APP_CPU is disabled for now */ regval = getreg32(DPORT_APPCPU_CTRL_B_REG); diff --git a/configs/esp32-core/scripts/esp32.template b/configs/esp32-core/scripts/esp32.template index 9fbe0f1ccc..871171ddde 100644 --- a/configs/esp32-core/scripts/esp32.template +++ b/configs/esp32-core/scripts/esp32.template @@ -59,4 +59,4 @@ MEMORY /* Heap ends at top of dram0_0_seg */ -_heap_end = 0x40000000 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM; +_eheap = 0x40000000 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM; diff --git a/configs/esp32-core/scripts/esp32_common.ld b/configs/esp32-core/scripts/esp32_common.ld index da7b74d510..213f53f499 100644 --- a/configs/esp32-core/scripts/esp32_common.ld +++ b/configs/esp32-core/scripts/esp32_common.ld @@ -56,7 +56,6 @@ SECTIONS _iram_text_start = ABSOLUTE(.); *(.iram1 .iram1.*) - *libfreertos.a:(.literal .text .literal.* .text.*) *libphy.a:(.literal .text .literal.* .text.*) *librtc.a:(.literal .text .literal.* .text.*) *libpp.a:(.literal .text .literal.* .text.*) @@ -90,7 +89,7 @@ SECTIONS .dram0.data : { - _data_start = ABSOLUTE(.); + _sdata = ABSOLUTE(.); KEEP(*(.data)) KEEP(*(.data.*)) KEEP(*(.gnu.linkonce.d.*)) @@ -103,14 +102,14 @@ SECTIONS KEEP(*(.gnu.linkonce.s2.*)) KEEP(*(.jcr)) *(.dram1 .dram1.*) - _data_end = ABSOLUTE(.); + _edata = ABSOLUTE(.); . = ALIGN(4); - _heap_start = ABSOLUTE(.); + _sheap = ABSOLUTE(.); } >dram0_0_seg .flash.rodata : { - _rodata_start = ABSOLUTE(.); + _srodata = ABSOLUTE(.); *(.rodata) *(.rodata.*) *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ @@ -122,7 +121,9 @@ SECTIONS *(.gnu.linkonce.e.*) *(.gnu.version_r) *(.eh_frame) + . = (. + 3) & ~ 3; + /* C++ constructor and destructor tables, properly ordered: */ __init_array_start = ABSOLUTE(.); KEEP (*crtbegin.o(.ctors)) @@ -134,7 +135,9 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); *(.xt_except_desc) *(.gnu.linkonce.h.*) @@ -142,7 +145,7 @@ SECTIONS *(.xt_except_desc_end) *(.dynamic) *(.gnu.version_d) - _rodata_end = ABSOLUTE(.); + _erodata = ABSOLUTE(.); /* Literals are also RO data. */ _lit4_start = ABSOLUTE(.); *(*.lit4) -- GitLab From 261eec110b6fe11d0bf7d4342a95688587b63a86 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 23 Oct 2016 14:19:08 -0600 Subject: [PATCH 192/734] Xtensa: Mismatched #endif --- arch/xtensa/src/common/xtensa.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index 31a49e16e2..df93eb1d36 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -200,7 +200,6 @@ extern uint32_t _eheap; /* End+1 of heap */ * Public Functions ****************************************************************************/ -#ifndef __ASSEMBLY__ /* Common Functions *********************************************************/ /* Common functions defined in arch/xtensa/src/common. These may be replaced * with chip-specific functions of the same name if needed. See also -- GitLab From 2514ddec8b3a77dbf24d1571993d18823c1d2047 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 23 Oct 2016 16:24:09 -0600 Subject: [PATCH 193/734] Xtensa: Add NMI handler --- arch/xtensa/src/common/xtensa_inthandlers.S | 13 +- arch/xtensa/src/common/xtensa_nmihandler.S | 126 ++++++++++++++++++ .../{xtensa_intvectors.S => xtensa_vectors.S} | 38 +++++- arch/xtensa/src/esp32/Make.defs | 4 +- configs/esp32-core/scripts/esp32_common.ld | 2 +- 5 files changed, 168 insertions(+), 15 deletions(-) create mode 100644 arch/xtensa/src/common/xtensa_nmihandler.S rename arch/xtensa/src/common/{xtensa_intvectors.S => xtensa_vectors.S} (81%) diff --git a/arch/xtensa/src/common/xtensa_inthandlers.S b/arch/xtensa/src/common/xtensa_inthandlers.S index 3193018819..6f824d9b0c 100644 --- a/arch/xtensa/src/common/xtensa_inthandlers.S +++ b/arch/xtensa/src/common/xtensa_inthandlers.S @@ -606,6 +606,9 @@ _xtensa_level6_handler: * a way to save and restore registers it uses without touching the * interrupted stack. * + * A template and example can be found in the Cadence Design Systems tools + * documentation: "Microprocessor Programmer's Guide". + * * Each vector goes at a predetermined location according to the Xtensa * hardware configuration, which is ensured by its placement in a special * section known to the Xtensa linker support package (LSP). It performs @@ -613,12 +616,6 @@ _xtensa_level6_handler: * ****************************************************************************/ -/* -Currently only shells for high priority interrupt handlers are provided -here. However a template and example can be found in the Cadence Design Systems tools -documentation: "Microprocessor Programmer's Guide". -*/ - #if XCHAL_INT_NLEVELS >=2 && XCHAL_EXCM_LEVEL < 2 && XCHAL_DEBUGLEVEL !=2 .section .iram1,"ax" .type _xtensa_level2_handler, @function @@ -630,7 +627,7 @@ _xtensa_level2_handler: /* Call interrupt hook if present to (pre)handle interrupts. */ movi a0, _xt_intexc_hooks - l32i a0, a0, 2<<2 + l32i a0, a0, 2 << 2 beqz a0, 1f .Ln_xtensa_level2_handler_call_hook: @@ -662,7 +659,7 @@ _xtensa_level3_handler: /* Call interrupt hook if present to (pre)handle interrupts. */ movi a0, _xt_intexc_hooks - l32i a0, a0, 3<<2 + l32i a0, a0, 3 << 2 beqz a0, 1f .Ln_xtensa_level3_handler_call_hook: diff --git a/arch/xtensa/src/common/xtensa_nmihandler.S b/arch/xtensa/src/common/xtensa_nmihandler.S new file mode 100644 index 0000000000..85f18c5a7f --- /dev/null +++ b/arch/xtensa/src/common/xtensa_nmihandler.S @@ -0,0 +1,126 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_nmihandler.S + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * + * Copyright (c) 2006-2015 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + ****************************************************************************/ + + .file "xtensa_nmihandler.S" + +/* NOTES on the use of 'call0' for long jumps instead of 'j': + * + * 1. This file should be assembled with the -mlongcalls option to xt-xcc. + * + * 2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to + * a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the + * distance from the call to the destination. The linker then relaxes + * it back to 'call0 dest' if it determines that dest is within range. + * This allows more flexibility in locating code without the performance + * overhead of the 'l32r' literal data load in cases where the destination + * is in range of 'call0'. There is an additional benefit in that 'call0' + * has a longer range than 'j' due to the target being word-aligned, so + * the 'l32r' sequence is less likely needed. + * + * 3. The use of 'call0' with -mlongcalls requires that register a0 not be + * live at the time of the call, which is always the case for a function + * call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'. + * + * 4. This use of 'call0' is independent of the C function call ABI. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "xtensa_macros.h" +#include "xtensa_timer.h" + +/**************************************************************************** + * Assembly Language Macros + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * HIGH PRIORITY NMI LOW-LEVEL HANDLER + * + * High priority interrupts are by definition those with priorities greater + * than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority + * interrupts cannot interact with the RTOS, that is they must save all regs + * they use and not call any RTOS function. + * + * A further restriction imposed by the Xtensa windowed architecture is that + * high priority interrupts must not modify the stack area even logically + * "above" the top of the interrupted stack (they need to provide their + * own stack or static save area). + * + * Cadence Design Systems recommends high priority interrupt handlers be + * coded in assembly and used for purposes requiring very short service + * times. + * + * The NMI vector goes at a predetermined location according to the Xtensa + * hardware configuration, which is ensured by its placement in a special + * section known to the Xtensa linker support package (LSP). It performs + * the minimum necessary before jumping to the NMI andler. + * + * Below is a template for the high priority NMI interrupt handler. + * A template and example can be found in the Cadence Design Systems tools + * documentation: "Microprocessor Programmer's Guide". + * + ****************************************************************************/ + +#if XCHAL_HAVE_NMI + .section .iram1,"ax" + .type _xt_nmi,@function + .align 4 +_xt_nmi: + +#ifdef XT_INTEXC_HOOKS + /* Call interrupt hook if present to (pre)handle interrupts. */ + + movi a0, _xt_intexc_hooks + l32i a0, a0, XCHAL_NMILEVEL << 2 + beqz a0, 1f + callx0 a0 /* Must NOT disturb stack! */ +1: +#endif + + /* Add high priority non-maskable interrupt (NMI) handler code here. */ + + rsr a0, EXCSAVE + XCHAL_NMILEVEL /* Restore a0 */ + rfi XCHAL_NMILEVEL + +#endif /* XCHAL_HAVE_NMI */ diff --git a/arch/xtensa/src/common/xtensa_intvectors.S b/arch/xtensa/src/common/xtensa_vectors.S similarity index 81% rename from arch/xtensa/src/common/xtensa_intvectors.S rename to arch/xtensa/src/common/xtensa_vectors.S index 103a35d886..19773e7e8a 100644 --- a/arch/xtensa/src/common/xtensa_intvectors.S +++ b/arch/xtensa/src/common/xtensa_vectors.S @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/common/xtensa_intvectors.S + * arch/xtensa/src/common/xtensa_vectors.S * * Adapted from use in NuttX by: * @@ -131,9 +131,8 @@ _xtensa_level5_vector: /* Never returns here - call0 is used as a jump */ - .end literal_prefix - .size _xtensa_level5_vector, . - _xtensa_level5_vector + .end literal_prefix #endif #if XCHAL_EXCM_LEVEL >= 6 @@ -150,7 +149,36 @@ _xtensa_level6_vector: /* Never returns here - call0 is used as a jump */ - .end literal_prefix + .size _xtensa_level6_vector, . - _xtensa_level6_vector + .end literal_prefix +#endif + +/**************************************************************************** + * C Prototype: + * void _xtensa_nmi_vector(void) + * + * Description: + * Xtensa NMI vectors. This vector goes at a predetermined location + * according to the Xtensa hardware configuration, which is ensured by its + * placement in a special section known to the NuttX linker script. The + * vector logic performs the minimum necessary operations before jumping + * to the handler. + * + ****************************************************************************/ + +#if XCHAL_HAVE_NMI + .begin literal_prefix .nmi_vector + .section .nmi_vector.text, "ax" + .global _xtensa_nmi_vector + .type _xtensa_nmi_vector, @function + .align 4 + +_xtensa_nmi_vector: + wsr a0, EXCSAVE + XCHAL_NMILEVEL _ /* preserve a0 */ + call0 _xt_nmi /* load interrupt handler */ + + /* Never returns here - call0 is used as a jump */ - .size _xtensa_level6_vector, . - _xtensa_level6_vector + .size _xtensa_nmi_vector, . - _xtensa_nmi_vector + .end literal_prefix #endif diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 1270f0c0cc..993965dac8 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -40,7 +40,9 @@ HEAD_CSRC = esp32_start.c # Common XTENSA files (arch/xtensa/src/common) -CMN_ASRCS = xtensa_context.S xtensa_intvectors.S +CMN_ASRCS = xtensa_context.S xtensa_vectors.S xtensa_inthandlers.S +CMN_ASRCS += xtensa_nmihandler.S + CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c CMN_CSRCS += xtensa_createstack.c xtensa_exit.c xtensa_idle.c CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c diff --git a/configs/esp32-core/scripts/esp32_common.ld b/configs/esp32-core/scripts/esp32_common.ld index 213f53f499..540a4f4ad6 100644 --- a/configs/esp32-core/scripts/esp32_common.ld +++ b/configs/esp32-core/scripts/esp32_common.ld @@ -31,7 +31,7 @@ SECTIONS . = 0x280; KEEP(*(.DebugExceptionVector.text)); . = 0x2c0; - KEEP(*(.NMIExceptionVector.text)); + KEEP(*(.nmi_vector.text)); . = 0x300; KEEP(*(.KernelExceptionVector.text)); . = 0x340; -- GitLab From 4cf60022cabe14c31136b6f90825b63ad50ff1f8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 23 Oct 2016 16:25:55 -0600 Subject: [PATCH 194/734] Xtensa: Correct some compile issues --- arch/xtensa/include/xtensa/core.h | 3 ++- arch/xtensa/src/common/xtensa_inthandlers.S | 14 -------------- arch/xtensa/src/common/xtensa_nmihandler.S | 2 -- arch/xtensa/src/common/xtensa_timer.h | 2 +- arch/xtensa/src/esp32/esp32_irq.c | 18 ------------------ 5 files changed, 3 insertions(+), 36 deletions(-) diff --git a/arch/xtensa/include/xtensa/core.h b/arch/xtensa/include/xtensa/core.h index b8aac7dbed..77ecb5aa76 100644 --- a/arch/xtensa/include/xtensa/core.h +++ b/arch/xtensa/include/xtensa/core.h @@ -1130,7 +1130,7 @@ * Exit: any register a2-a15 (?) may have been clobbered. */ - .macro xchal_cpi_store_funcbody + .macro xchal_cpi_store_funcbody #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) # if XCHAL_CP0_SA_SIZE bnez a3, 99f @@ -1182,6 +1182,7 @@ # endif 90: #endif + .endm /* Macro that expands to the body of a function that loads the selected coprocessor's state * (registers etc). diff --git a/arch/xtensa/src/common/xtensa_inthandlers.S b/arch/xtensa/src/common/xtensa_inthandlers.S index 6f824d9b0c..483916ae2b 100644 --- a/arch/xtensa/src/common/xtensa_inthandlers.S +++ b/arch/xtensa/src/common/xtensa_inthandlers.S @@ -126,20 +126,6 @@ and a2, a2, a4 beqz a2, 5f /* Nothing to do */ - /* This bit of code provides a nice debug backtrace in the debugger. - * It does take a few more instructions, so undef XT_DEBUG_BACKTRACE - * if you want to save the cycles. - * / - -#if XT_DEBUG_BACKTRACE -#ifndef CONFIG_XTENSA_CALL0_ABI - rsr a0, EPC_1 + \level - 1 /* Return address */ - movi a4, 0xC0000000 /* Constant with top 2 bits set (call size) */ - or a0, a0, a4 /* Set top 2 bits */ - addx2 a0, a4, a0 /* Clear top bit -- simulating call4 size */ -#endif -#endif - #ifdef XT_INTEXC_HOOKS /* Call interrupt hook if present to (pre)handle interrupts. */ diff --git a/arch/xtensa/src/common/xtensa_nmihandler.S b/arch/xtensa/src/common/xtensa_nmihandler.S index 85f18c5a7f..47d8bba2dc 100644 --- a/arch/xtensa/src/common/xtensa_nmihandler.S +++ b/arch/xtensa/src/common/xtensa_nmihandler.S @@ -59,12 +59,10 @@ #include -#include #include #include #include "xtensa_macros.h" -#include "xtensa_timer.h" /**************************************************************************** * Assembly Language Macros diff --git a/arch/xtensa/src/common/xtensa_timer.h b/arch/xtensa/src/common/xtensa_timer.h index 0a4429633b..f44c1738ad 100644 --- a/arch/xtensa/src/common/xtensa_timer.h +++ b/arch/xtensa/src/common/xtensa_timer.h @@ -34,7 +34,7 @@ #define __ARCH_XTENSA_SRC_COMMON_XTENSA_TIMER_H #ifdef __ASSEMBLER__ -# include +//# include #endif #include diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c index 2fa02c8e93..d5cf4b552a 100644 --- a/arch/xtensa/src/esp32/esp32_irq.c +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -89,24 +89,6 @@ static void esp32_irq_dump(const char *msg, int irq) # define esp32_irq_dump(msg, irq) #endif -/**************************************************************************** - * Name: esp32_nmi - * - * Description: - * Handlers for various execptions. None are handled and all are fatal - * error conditions. The only advantage these provided over the default - * unexpected interrupt handler is that they provide a diagnostic output. - * - ****************************************************************************/ - -static int esp32_nmi(int irq, FAR void *context) -{ - (void)up_irq_save(); - _err("PANIC!!! NMI received\n"); - PANIC(); - return 0; -} - /**************************************************************************** * Public Functions ****************************************************************************/ -- GitLab From 818b0171d79c032c8fa6dbe25ef85471d55e3134 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 24 Oct 2016 07:30:11 -0600 Subject: [PATCH 195/734] ESP32: Clock configuration is not yet implemented. ESP32 will be running a XTAL frequency. --- arch/xtensa/src/common/xtensa.h | 13 +-- arch/xtensa/src/common/xtensa_inthandlers.S | 35 +++---- arch/xtensa/src/common/xtensa_nmihandler.S | 5 +- arch/xtensa/src/esp32/chip_macros.h | 10 ++ arch/xtensa/src/esp32/esp32_clockconfig.c | 107 ++++++++++++++++++++ configs/esp32-core/include/board.h | 13 ++- 6 files changed, 157 insertions(+), 26 deletions(-) create mode 100644 arch/xtensa/src/esp32/esp32_clockconfig.c diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index df93eb1d36..fb13a8150a 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -49,16 +49,17 @@ * Pre-processor Definitions ****************************************************************************/ -/* Bring-up debug configurations. These are here (vs defconfig) +/* Bring-up debug configurations. These are here (vs Kconfig) * because these should only be controlled during low level * board bring-up and not part of normal platform configuration. */ -#undef CONFIG_SUPPRESS_INTERRUPTS /* DEFINED: Do not enable interrupts */ -#undef CONFIG_SUPPRESS_TIMER_INTS /* DEFINED: No timer */ -#undef CONFIG_SUPPRESS_SERIAL_INTS /* DEFINED: Console will poll */ -#undef CONFIG_SUPPRESS_UART_CONFIG /* DEFINED: Do not reconfig UART */ -#undef CONFIG_DUMP_ON_EXIT /* DEFINED: Dump task state on exit */ +#undef CONFIG_SUPPRESS_INTERRUPTS /* DEFINED: Do not enable interrupts */ +#undef CONFIG_SUPPRESS_TIMER_INTS /* DEFINED: No timer */ +#undef CONFIG_SUPPRESS_SERIAL_INTS /* DEFINED: Console will poll */ +#undef CONFIG_SUPPRESS_UART_CONFIG /* DEFINED: Do not reconfigure UART */ +#define CONFIG_SUPPRESS_CLOCK_CONFIG 1 /* DEFINED: Do not reconfigure clocking */ +#undef CONFIG_DUMP_ON_EXIT /* DEFINED: Dump task state on exit */ #ifndef CONFIG_DEBUG_SCHED_INFO # undef CONFIG_DUMP_ON_EXIT /* Needs CONFIG_DEBUG_SCHED_INFO */ diff --git a/arch/xtensa/src/common/xtensa_inthandlers.S b/arch/xtensa/src/common/xtensa_inthandlers.S index 483916ae2b..af4e068728 100644 --- a/arch/xtensa/src/common/xtensa_inthandlers.S +++ b/arch/xtensa/src/common/xtensa_inthandlers.S @@ -62,6 +62,7 @@ #include #include #include +#include #include "xtensa_macros.h" #include "xtensa_timer.h" @@ -282,8 +283,8 @@ ****************************************************************************/ #if XCHAL_EXCM_LEVEL >= 2 - .section .iram1,"ax" - .type _xtensa_level2_handler,@function + .section HANDLER_SECTION, "ax" + .type _xtensa_level2_handler, @function .align 4 _xtensa_level2_handler: @@ -339,8 +340,8 @@ _xtensa_level2_handler: #endif /* XCHAL_EXCM_LEVEL >= 2 */ #if XCHAL_EXCM_LEVEL >= 3 - .section .iram1,"ax" - .type _xtensa_level3_handler,@function + .section HANDLER_SECTION, "ax" + .type _xtensa_level3_handler, @function .align 4 _xtensa_level3_handler: @@ -396,8 +397,8 @@ _xtensa_level3_handler: #endif /* XCHAL_EXCM_LEVEL >= 3 */ #if XCHAL_EXCM_LEVEL >= 4 - .section .iram1,"ax" - .type _xtensa_level4_handler,@function + .section HANDLER_SECTION, "ax" + .type _xtensa_level4_handler, @function .align 4 _xtensa_level4_handler: @@ -453,8 +454,8 @@ _xtensa_level4_handler: #endif /* XCHAL_EXCM_LEVEL >= 4 */ #if XCHAL_EXCM_LEVEL >= 5 - .section .iram1,"ax" - .type _xtensa_level5_handler,@function + .section HANDLER_SECTION, "ax" + .type _xtensa_level5_handler, @function .align 4 _xtensa_level5_handler: @@ -510,8 +511,8 @@ _xtensa_level5_handler: #endif /* XCHAL_EXCM_LEVEL >= 2 */ #if XCHAL_EXCM_LEVEL >= 6 - .section .iram1,"ax" - .type _xtensa_level6_handler,@function + .section HANDLER_SECTION, "ax" + .type _xtensa_level6_handler, @function .align 4 _xtensa_level6_handler: @@ -603,7 +604,7 @@ _xtensa_level6_handler: ****************************************************************************/ #if XCHAL_INT_NLEVELS >=2 && XCHAL_EXCM_LEVEL < 2 && XCHAL_DEBUGLEVEL !=2 - .section .iram1,"ax" + .section HANDLER_SECTION, "ax" .type _xtensa_level2_handler, @function .align 4 @@ -635,7 +636,7 @@ _xtensa_level2_handler: #endif /* XCHAL_INT_NLEVELS >=2 && XCHAL_EXCM_LEVEL < 2 && XCHAL_DEBUGLEVEL !=2 */ #if XCHAL_INT_NLEVELS >=3 && XCHAL_EXCM_LEVEL < 3 && XCHAL_DEBUGLEVEL !=3 - .section .iram1,"ax" + .section HANDLER_SECTION, "ax" .type _xtensa_level3_handler, @function .align 4 @@ -666,8 +667,8 @@ _xtensa_level3_handler: #endif /* XCHAL_INT_NLEVELS >=3 && XCHAL_EXCM_LEVEL < 3 && XCHAL_DEBUGLEVEL !=3 */ #if XCHAL_INT_NLEVELS >=4 && XCHAL_EXCM_LEVEL < 4 && XCHAL_DEBUGLEVEL !=4 - .section .iram1,"ax" - .type _xtensa_level4_handler,@function + .section HANDLER_SECTION, "ax" + .type _xtensa_level4_handler, @function .align 4 _xtensa_level4_handler: @@ -697,8 +698,8 @@ _xtensa_level4_handler: #endif /* XCHAL_INT_NLEVELS >=4 && XCHAL_EXCM_LEVEL < 4 && XCHAL_DEBUGLEVEL !=4 */ #if XCHAL_INT_NLEVELS >=5 && XCHAL_EXCM_LEVEL < 5 && XCHAL_DEBUGLEVEL !=5 - .section .iram1,"ax" - .type _xtensa_level5_handler,@function + .section HANDLER_SECTION, "ax" + .type _xtensa_level5_handler, @function .align 4 _xtensa_level5_handler: @@ -726,7 +727,7 @@ _xtensa_level5_handler: #endif /* XCHAL_INT_NLEVELS >=5 && XCHAL_EXCM_LEVEL < 5 && XCHAL_DEBUGLEVEL !=5 */ #if XCHAL_INT_NLEVELS >=6 && XCHAL_EXCM_LEVEL < 6 && XCHAL_DEBUGLEVEL !=6 - .section .iram1,"ax" + .section HANDLER_SECTION, "ax" .type _xtensa_level6_handler, @function .align 4 diff --git a/arch/xtensa/src/common/xtensa_nmihandler.S b/arch/xtensa/src/common/xtensa_nmihandler.S index 47d8bba2dc..0720b1fe71 100644 --- a/arch/xtensa/src/common/xtensa_nmihandler.S +++ b/arch/xtensa/src/common/xtensa_nmihandler.S @@ -61,6 +61,7 @@ #include #include +#include #include "xtensa_macros.h" @@ -101,8 +102,8 @@ ****************************************************************************/ #if XCHAL_HAVE_NMI - .section .iram1,"ax" - .type _xt_nmi,@function + .section HANDLER_SECTION, "ax" + .type _xt_nmi, @function .align 4 _xt_nmi: diff --git a/arch/xtensa/src/esp32/chip_macros.h b/arch/xtensa/src/esp32/chip_macros.h index 8b3530cc26..62add87fa2 100644 --- a/arch/xtensa/src/esp32/chip_macros.h +++ b/arch/xtensa/src/esp32/chip_macros.h @@ -39,6 +39,16 @@ #include +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* This is the name of the section containing the Xtensa low level handlers + * that is used by the board linker scripts. + */ + +#define HANDLER_SECTION .iram1 + /**************************************************************************** * Assembly Language Macros ****************************************************************************/ diff --git a/arch/xtensa/src/esp32/esp32_clockconfig.c b/arch/xtensa/src/esp32/esp32_clockconfig.c new file mode 100644 index 0000000000..73abcac8e2 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_clockconfig.c @@ -0,0 +1,107 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/exp32_cpuindex.S + * + * Mofidifed by use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from software originally provided by Expressif Systems: + * + * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + **************************************************************************** + +/**************************************************************************** + * Included Files + **************************************************************************** + +#include +#include "xtensa.h" + +#warning REVISIT ... function prototypes + +void phy_get_romfunc_addr(void); +void rtc_init_lite(void); +void rtc_set_cpu_freq(xtal_freq_t xtal_freq, enum xtal_freq_e cpu_freq); + +/**************************************************************************** + * Private Types + **************************************************************************** + +enum xtal_freq_e +{ + XTAL_40M = 40, + XTAL_26M = 26, + XTAL_24M = 24, + XTAL_AUTO = 0 +}; + +enum xtal_freq_e +{ + CPU_80M = 1, + CPU_160M = 2, + CPU_240M = 3, +}; + +/**************************************************************************** + * Public Functions + **************************************************************************** + +/**************************************************************************** + * Name: esp32_clockconfig + * + * Description: + * Called to initialize the ESP32. This does whatever setup is needed to + * put the SoC in a usable state. This includes the initialization of + * clocking using the settings in board.h. + * + ****************************************************************************/ + +void esp32_clockconfig(void) +{ +#ifndef CONFIG_SUPPRESS_CLOCK_CONFIG + uint32_t freq_mhz = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ; + enum xtal_freq_e freq; + + phy_get_romfunc_addr(); + + // freq will be changed to 40MHz in rtc_init_lite + + rtc_init_lite(); + + freq = CPU_80M; + switch (freq_mhz) + { + case 240: + freq = CPU_240M; + break; + case 160: + freq = CPU_160M; + break; + default: + freq_mhz = 80; + /* no break */ + case 80: + freq = CPU_80M; + break; + } + + // freq will be changed to freq in rtc_set_cpu_freq, + + rtc_set_cpu_freq(XTAL_AUTO, freq); + ets_update_cpu_frequency(freq_mhz); +#endif +} diff --git a/configs/esp32-core/include/board.h b/configs/esp32-core/include/board.h index 94dcebef32..6e24654f39 100644 --- a/configs/esp32-core/include/board.h +++ b/configs/esp32-core/include/board.h @@ -41,7 +41,18 @@ ****************************************************************************/ /* Clocking ****************************************************************/ +/* The ESP32 Core board V2 is fitted with a 40MHz crystal */ -#define BOARD_CLOCK_FREQUENCY 80000000 +#define BOARD_XTAL_FREQUENCY 40000000 + +/* Clock reconfiguration is currently disabled, so the CPU will be running + * at the XTAL frequency. + *. + +#if 0 +# define BOARD_CLOCK_FREQUENCY 80000000 +#else +# define BOARD_CLOCK_FREQUENCY BOARD_XTAL_FREQUENCY +#endif #endif /* __CONFIGS_ESP32_CORE_INCLUDE_BOARD_H */ -- GitLab From 802cd127968d3c290208354c3a98107d65c5650e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 24 Oct 2016 07:31:18 -0600 Subject: [PATCH 196/734] Fix typo in last commit --- configs/esp32-core/include/board.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/esp32-core/include/board.h b/configs/esp32-core/include/board.h index 6e24654f39..a08840fbe0 100644 --- a/configs/esp32-core/include/board.h +++ b/configs/esp32-core/include/board.h @@ -47,7 +47,7 @@ /* Clock reconfiguration is currently disabled, so the CPU will be running * at the XTAL frequency. - *. + */ #if 0 # define BOARD_CLOCK_FREQUENCY 80000000 -- GitLab From 7b7e352d6e365295d2b4bc14b4be26cc28cf369a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 24 Oct 2016 14:09:47 -0600 Subject: [PATCH 197/734] ESP32: Add some peripheral configuration --- arch/xtensa/src/esp32/Kconfig | 188 +++++++++++++++++++++++++ arch/xtensa/src/esp32/chip/esp32_soc.h | 3 +- configs/esp32-core/README.txt | 3 +- 3 files changed, 192 insertions(+), 2 deletions(-) diff --git a/arch/xtensa/src/esp32/Kconfig b/arch/xtensa/src/esp32/Kconfig index 5263d6c5b7..3d7592362c 100644 --- a/arch/xtensa/src/esp32/Kconfig +++ b/arch/xtensa/src/esp32/Kconfig @@ -5,6 +5,194 @@ if ARCH_CHIP_ESP32 +menu "ESP32 Peripheral Selection" + +config ESP32_BT + bool "Bluetooth" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32_EMAC + bool "Ethernet MAC" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32_I2C + bool "I2C" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32_I2S0 + bool "I2S 0" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32_I2S1 + bool "I2S 2" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32_LEDC + bool "LED PWM (LEDC)" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32_PCNT + bool "Pulse Count Module (PCNT)" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32_RMT + bool "Remote Control Module (RMT)" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32_SDIO_SAVE + bool "SDIO Slave" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32_SDMMC + bool "SD/MMC card support" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32_SPI0 + bool "SPI 0" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32_SPI1 + bool "SPI 1" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32_SPI2 + bool "SPI 2" + default n + ---help--- + No yet implemented + +config XTENSA_TIMER1 + bool "Xtensa Timer 1" + default n + +config XTENSA_TIMER2 + bool "Xtensa Timer 2" + default n + +config ESP32_TIMER0 + bool "64-bit Timer 0" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32_TIMER1 + bool "64-bit Timer 1" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32_TIMER2 + bool "64-bit Timer 2" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32_TIMER3 + bool "64-bit Timer 3" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32_MWDT0 + bool "Timer 0 Watchdog" + default n + depends on EXPERIMENTAL + select ESP32_TIMER0 + ---help--- + No yet implemented + +config ESP32_MWDT1 + bool "Timer 1 Watchdog" + default n + depends on EXPERIMENTAL + select ESP32_TIMER1 + ---help--- + No yet implemented + +config ESP32_MWDT2 + bool "Timer 2 Watchdog" + default n + depends on EXPERIMENTAL + select ESP32_TIMER2 + ---help--- + No yet implemented + +config ESP32_MWDT3 + bool "Timer 3 Watchdog" + default n + depends on EXPERIMENTAL + select ESP32_TIMER3 + ---help--- + No yet implemented + +config ESP32_RWDT + bool "RTC Watchdog" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32_UART0 + bool "UART 0" + default n + +config ESP32_UART1 + bool "UART 1" + default n + +config ESP32_UART2 + bool "UART 2" + default n + +config ESP32_WIRELESS + bool "Wireless" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +endmenu # ESP32 Peripheral Selection + config ESP32_BT_RESERVE_DRAM int "Reserved BT DRAM" default 0 diff --git a/arch/xtensa/src/esp32/chip/esp32_soc.h b/arch/xtensa/src/esp32/chip/esp32_soc.h index 20405c067d..0073508ab6 100644 --- a/arch/xtensa/src/esp32/chip/esp32_soc.h +++ b/arch/xtensa/src/esp32/chip/esp32_soc.h @@ -7,7 +7,8 @@ * Author: Gregory Nutt * * Derives from logic originally provided by Espressif Systems: - * Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD + * + * Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index 50fd2d273d..1f0ff0d717 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -79,7 +79,8 @@ ESP32 Toolchain Serial Console ============== - To be provided + USART0 is, by default, the serial console. It connects to the on-board + CP2102 converter and is available on the USB connector USB CON8 (J1). Buttons and LEDs ================ -- GitLab From 146d7e79212878c289c3f1eaea454bf5d72d1b3b Mon Sep 17 00:00:00 2001 From: Max Nekludov Date: Mon, 24 Oct 2016 15:17:01 -0600 Subject: [PATCH 198/734] drivers/net/tun.c: Fix bug in TUN interface driver --- drivers/net/tun.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/net/tun.c b/drivers/net/tun.c index 37c199d167..fc1425a768 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -1,7 +1,7 @@ /**************************************************************************** * drivers/net/tun.c * - * Copyright (C) 2015 Max Nekludov. All rights reserved. + * Copyright (C) 2015-2016 Max Nekludov. All rights reserved. * Author: Max Nekludov * * Redistribution and use in source and binary forms, with or without @@ -149,12 +149,12 @@ static void tun_unlock(FAR struct tun_device_s *priv); /* Common TX logic */ -static int tun_transmit(FAR struct tun_device_s *priv); +static int tun_fd_transmit(FAR struct tun_device_s *priv); static int tun_txpoll(struct net_driver_s *dev); /* Interrupt handling */ -static void tun_receive(FAR struct tun_device_s *priv); +static void tun_net_receive(FAR struct tun_device_s *priv); static void tun_txdone(FAR struct tun_device_s *priv); /* Watchdog timer expirations */ @@ -211,7 +211,7 @@ static const struct file_operations g_tun_file_ops = tun_close, /* close */ tun_read, /* read */ tun_write, /* write */ - 0, /* seek */ + 0, /* seek */ tun_ioctl, /* ioctl */ #ifndef CONFIG_DISABLE_POLL tun_poll, /* poll */ @@ -322,7 +322,7 @@ static void tun_pollnotify(FAR struct tun_device_s *priv, pollevent_t eventset) * ****************************************************************************/ -static int tun_transmit(FAR struct tun_device_s *priv) +static int tun_fd_transmit(FAR struct tun_device_s *priv) { NETDEV_TXPACKETS(&priv->dev); @@ -379,7 +379,7 @@ static int tun_txpoll(struct net_driver_s *dev) /* Send the packet */ priv->read_d_len = priv->dev.d_len; - tun_transmit(priv); + tun_fd_transmit(priv); return 1; } @@ -408,8 +408,10 @@ static int tun_txpoll(struct net_driver_s *dev) * ****************************************************************************/ -static void tun_receive(FAR struct tun_device_s *priv) +static void tun_net_receive(FAR struct tun_device_s *priv) { + int ret; + /* Copy the data data from the hardware to priv->dev.d_buf. Set amount of * data in priv->dev.d_len */ @@ -736,7 +738,7 @@ static int tun_txavail(struct net_driver_s *dev) /* Check if there is room to hold another network packet. */ - if (priv->read_d_len) + if (priv->read_d_len != 0 || priv->write_d_len != 0) { tun_unlock(priv); return OK; @@ -1000,7 +1002,7 @@ static ssize_t tun_write(FAR struct file *filep, FAR const char *buffer, priv->dev.d_buf = priv->write_buf; priv->dev.d_len = buflen; - tun_receive(priv); + tun_net_receive(priv); ret = (ssize_t)buflen; } @@ -1047,6 +1049,14 @@ static ssize_t tun_read(FAR struct file *filep, FAR char *buffer, priv->write_d_len = 0; tun_pollnotify(priv, POLLOUT); + + if (priv->read_d_len == 0) + { + state = net_lock(); + tun_txdone(priv); + net_unlock(state); + } + goto out; } -- GitLab From 3d4ce55ebd4eec29ac53fc68873318581f87b05a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 24 Oct 2016 15:25:40 -0600 Subject: [PATCH 199/734] Oops.. a couple of hunks failed in the last patch. Hope I got them fixed correctly. --- arch/xtensa/src/esp32/esp32_clockconfig.c | 4 ++- drivers/net/tun.c | 42 ++++++++++++++--------- 2 files changed, 29 insertions(+), 17 deletions(-) diff --git a/arch/xtensa/src/esp32/esp32_clockconfig.c b/arch/xtensa/src/esp32/esp32_clockconfig.c index 73abcac8e2..2da4e0b4de 100644 --- a/arch/xtensa/src/esp32/esp32_clockconfig.c +++ b/arch/xtensa/src/esp32/esp32_clockconfig.c @@ -72,7 +72,9 @@ enum xtal_freq_e void esp32_clockconfig(void) { -#ifndef CONFIG_SUPPRESS_CLOCK_CONFIG +#ifdef CONFIG_SUPPRESS_CLOCK_CONFIG +# warning WARNING: Clock coniguration disabled +#else uint32_t freq_mhz = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ; enum xtal_freq_e freq; diff --git a/drivers/net/tun.c b/drivers/net/tun.c index fc1425a768..a8b76290c4 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -429,24 +429,34 @@ static void tun_net_receive(FAR struct tun_device_s *priv) #if defined(CONFIG_NET_IPv4) ninfo("IPv4 frame\n"); NETDEV_RXIPV4(&priv->dev); +################################################################################# +@@ -429,20 +431,27 @@ static void tun_receive(FAR struct tun_device_s *priv) - /* Give the IPv4 packet to the network layer */ + /* Give the IPv4 packet to the network layer */ - ipv4_input(&priv->dev); + ret = ipv4_input(&priv->dev); - /* If the above function invocation resulted in data that should be - * sent out on the network, the field d_len will set to a value > 0. - */ - - if (priv->dev.d_len > 0) - { - priv->write_d_len = priv->dev.d_len; - tun_transmit(priv); - } - else - { - priv->write_d_len = 0; - tun_pollnotify(priv, POLLOUT); + if (ret == OK) + { + /* If the above function invocation resulted in data that should be + * sent out on the network, the field d_len will set to a value > 0. + */ + + if (priv->dev.d_len > 0) + { + priv->write_d_len = priv->dev.d_len; + tun_fd_transmit(priv); + } + else + { + tun_pollnotify(priv, POLLOUT); + } + } + else + { + priv->dev.d_len = 0; + tun_pollnotify(priv, POLLOUT); + } } #elif defined(CONFIG_NET_IPv6) @@ -464,7 +474,7 @@ static void tun_net_receive(FAR struct tun_device_s *priv) if (priv->dev.d_len > 0) { priv->write_d_len = priv->dev.d_len; - tun_transmit(priv); + tun_fd_transmit(priv); } else { -- GitLab From de6db52b52efa13b496d072b0fde0c786bc246a0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 24 Oct 2016 15:36:11 -0600 Subject: [PATCH 200/734] Oops... Last commit had some garbage in the file --- drivers/net/tun.c | 62 ++++++++++++++++++++++++++--------------------- 1 file changed, 34 insertions(+), 28 deletions(-) diff --git a/drivers/net/tun.c b/drivers/net/tun.c index a8b76290c4..d14fb7ed28 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -429,52 +429,58 @@ static void tun_net_receive(FAR struct tun_device_s *priv) #if defined(CONFIG_NET_IPv4) ninfo("IPv4 frame\n"); NETDEV_RXIPV4(&priv->dev); -################################################################################# -@@ -429,20 +431,27 @@ static void tun_receive(FAR struct tun_device_s *priv) - /* Give the IPv4 packet to the network layer */ + /* Give the IPv4 packet to the network layer. ipv4_input will return + * an error if it is unable to dispatch the packet at this time. + */ - ret = ipv4_input(&priv->dev); + ret = ipv4_input(&priv->dev); + if (ret == OK) + { + /* If the above function invocation resulted in data that should be + * sent out on the network, the field d_len will set to a value > 0. + */ - if (ret == OK) + if (priv->dev.d_len > 0) { - /* If the above function invocation resulted in data that should be - * sent out on the network, the field d_len will set to a value > 0. - */ - - if (priv->dev.d_len > 0) - { - priv->write_d_len = priv->dev.d_len; - tun_fd_transmit(priv); - } - else - { - tun_pollnotify(priv, POLLOUT); - } + priv->write_d_len = priv->dev.d_len; + tun_fd_transmit(priv); } else { - priv->dev.d_len = 0; tun_pollnotify(priv, POLLOUT); } } + else + { + priv->dev.d_len = 0; + tun_pollnotify(priv, POLLOUT); + } #elif defined(CONFIG_NET_IPv6) ninfo("Iv6 frame\n"); NETDEV_RXIPV6(&priv->dev); - /* Give the IPv6 packet to the network layer */ - - ipv6_input(&priv->dev); - - /* If the above function invocation resulted in data that should be - * sent out on the network, the field d_len will set to a value > 0. + /* Give the IPv6 packet to the network layer. ipv6_input will return + * an error if it is unable to dispatch the packet at this time. */ - if (priv->dev.d_len > 0) + ret = ipv6_input(&priv->dev); + if (ret == OK) { - priv->write_d_len = priv->dev.d_len; - tun_fd_transmit(priv); + /* If the above function invocation resulted in data that should be + * sent out on the network, the field d_len will set to a value > 0. + */ + + if (priv->dev.d_len > 0) + { + priv->write_d_len = priv->dev.d_len; + tun_fd_transmit(priv); + } + else + { + tun_pollnotify(priv, POLLOUT); + } } else { -- GitLab From 1dabbd848928a3d8aa2c7d91c1a65228d89c389a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 24 Oct 2016 16:18:30 -0600 Subject: [PATCH 201/734] Costmetic changes --- arch/xtensa/include/esp32/irq.h | 2 +- arch/xtensa/src/esp32/chip/esp32_dport.h | 1008 ++++++++++++++++++++++ arch/xtensa/src/esp32/esp32_timerisr.c | 8 +- include/ctype.h | 2 +- net/devif/ipv4_input.c | 2 - 5 files changed, 1013 insertions(+), 9 deletions(-) diff --git a/arch/xtensa/include/esp32/irq.h b/arch/xtensa/include/esp32/irq.h index b394e8d6ba..36fce7d4e5 100644 --- a/arch/xtensa/include/esp32/irq.h +++ b/arch/xtensa/include/esp32/irq.h @@ -66,7 +66,7 @@ * * REVISIT: In more architectures supported by NuttX, exception errors * tie into the normal interrupt handling via special IRQ numbers. I - * is still to be determined what will be done for the the ESP32. + * is still to be determined what will be done for the ESP32. */ #define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */ diff --git a/arch/xtensa/src/esp32/chip/esp32_dport.h b/arch/xtensa/src/esp32/chip/esp32_dport.h index 0dcf98b626..202e4824c3 100644 --- a/arch/xtensa/src/esp32/chip/esp32_dport.h +++ b/arch/xtensa/src/esp32/chip/esp32_dport.h @@ -38,914 +38,1186 @@ ****************************************************************************/ #define DPORT_PRO_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x000) + /* DPORT_PRO_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_BOOT_REMAP (BIT(0)) #define DPORT_PRO_BOOT_REMAP_M (BIT(0)) #define DPORT_PRO_BOOT_REMAP_V 0x1 #define DPORT_PRO_BOOT_REMAP_S 0 #define DPORT_APP_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x004) + /* DPORT_APP_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_BOOT_REMAP (BIT(0)) #define DPORT_APP_BOOT_REMAP_M (BIT(0)) #define DPORT_APP_BOOT_REMAP_V 0x1 #define DPORT_APP_BOOT_REMAP_S 0 #define DPORT_ACCESS_CHECK_REG (DR_REG_DPORT_BASE + 0x008) + /* DPORT_ACCESS_CHECK_APP : RO ;bitpos:[8] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_ACCESS_CHECK_APP (BIT(8)) #define DPORT_ACCESS_CHECK_APP_M (BIT(8)) #define DPORT_ACCESS_CHECK_APP_V 0x1 #define DPORT_ACCESS_CHECK_APP_S 8 + /* DPORT_ACCESS_CHECK_PRO : RO ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_ACCESS_CHECK_PRO (BIT(0)) #define DPORT_ACCESS_CHECK_PRO_M (BIT(0)) #define DPORT_ACCESS_CHECK_PRO_V 0x1 #define DPORT_ACCESS_CHECK_PRO_S 0 #define DPORT_PRO_DPORT_APB_MASK0_REG (DR_REG_DPORT_BASE + 0x00C) + /* DPORT_PRODPORT_APB_MASK0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /* Description: */ + #define DPORT_PRODPORT_APB_MASK0 0xFFFFFFFF #define DPORT_PRODPORT_APB_MASK0_M ((DPORT_PRODPORT_APB_MASK0_V)<<(DPORT_PRODPORT_APB_MASK0_S)) #define DPORT_PRODPORT_APB_MASK0_V 0xFFFFFFFF #define DPORT_PRODPORT_APB_MASK0_S 0 #define DPORT_PRO_DPORT_APB_MASK1_REG (DR_REG_DPORT_BASE + 0x010) + /* DPORT_PRODPORT_APB_MASK1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /* Description: */ + #define DPORT_PRODPORT_APB_MASK1 0xFFFFFFFF #define DPORT_PRODPORT_APB_MASK1_M ((DPORT_PRODPORT_APB_MASK1_V)<<(DPORT_PRODPORT_APB_MASK1_S)) #define DPORT_PRODPORT_APB_MASK1_V 0xFFFFFFFF #define DPORT_PRODPORT_APB_MASK1_S 0 #define DPORT_APP_DPORT_APB_MASK0_REG (DR_REG_DPORT_BASE + 0x014) + /* DPORT_APPDPORT_APB_MASK0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /* Description: */ + #define DPORT_APPDPORT_APB_MASK0 0xFFFFFFFF #define DPORT_APPDPORT_APB_MASK0_M ((DPORT_APPDPORT_APB_MASK0_V)<<(DPORT_APPDPORT_APB_MASK0_S)) #define DPORT_APPDPORT_APB_MASK0_V 0xFFFFFFFF #define DPORT_APPDPORT_APB_MASK0_S 0 #define DPORT_APP_DPORT_APB_MASK1_REG (DR_REG_DPORT_BASE + 0x018) + /* DPORT_APPDPORT_APB_MASK1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /* Description: */ + #define DPORT_APPDPORT_APB_MASK1 0xFFFFFFFF #define DPORT_APPDPORT_APB_MASK1_M ((DPORT_APPDPORT_APB_MASK1_V)<<(DPORT_APPDPORT_APB_MASK1_S)) #define DPORT_APPDPORT_APB_MASK1_V 0xFFFFFFFF #define DPORT_APPDPORT_APB_MASK1_S 0 #define DPORT_PERI_CLK_EN_REG (DR_REG_DPORT_BASE + 0x01C) + /* DPORT_PERI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /* Description: */ + #define DPORT_PERI_CLK_EN 0xFFFFFFFF #define DPORT_PERI_CLK_EN_M ((DPORT_PERI_CLK_EN_V)<<(DPORT_PERI_CLK_EN_S)) #define DPORT_PERI_CLK_EN_V 0xFFFFFFFF #define DPORT_PERI_CLK_EN_S 0 #define DPORT_PERI_RST_EN_REG (DR_REG_DPORT_BASE + 0x020) + /* DPORT_PERI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /* Description: */ + #define DPORT_PERI_RST_EN 0xFFFFFFFF #define DPORT_PERI_RST_EN_M ((DPORT_PERI_RST_EN_V)<<(DPORT_PERI_RST_EN_S)) #define DPORT_PERI_RST_EN_V 0xFFFFFFFF #define DPORT_PERI_RST_EN_S 0 #define DPORT_WIFI_BB_CFG_REG (DR_REG_DPORT_BASE + 0x024) + /* DPORT_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /* Description: */ + #define DPORT_WIFI_BB_CFG 0xFFFFFFFF #define DPORT_WIFI_BB_CFG_M ((DPORT_WIFI_BB_CFG_V)<<(DPORT_WIFI_BB_CFG_S)) #define DPORT_WIFI_BB_CFG_V 0xFFFFFFFF #define DPORT_WIFI_BB_CFG_S 0 #define DPORT_WIFI_BB_CFG_2_REG (DR_REG_DPORT_BASE + 0x028) + /* DPORT_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /* Description: */ + #define DPORT_WIFI_BB_CFG_2 0xFFFFFFFF #define DPORT_WIFI_BB_CFG_2_M ((DPORT_WIFI_BB_CFG_2_V)<<(DPORT_WIFI_BB_CFG_2_S)) #define DPORT_WIFI_BB_CFG_2_V 0xFFFFFFFF #define DPORT_WIFI_BB_CFG_2_S 0 #define DPORT_APPCPU_CTRL_A_REG (DR_REG_DPORT_BASE + 0x02C) + /* DPORT_APPCPU_RESETTING : R/W ;bitpos:[0] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_APPCPU_RESETTING (BIT(0)) #define DPORT_APPCPU_RESETTING_M (BIT(0)) #define DPORT_APPCPU_RESETTING_V 0x1 #define DPORT_APPCPU_RESETTING_S 0 #define DPORT_APPCPU_CTRL_B_REG (DR_REG_DPORT_BASE + 0x030) + /* DPORT_APPCPU_CLKGATE_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APPCPU_CLKGATE_EN (BIT(0)) #define DPORT_APPCPU_CLKGATE_EN_M (BIT(0)) #define DPORT_APPCPU_CLKGATE_EN_V 0x1 #define DPORT_APPCPU_CLKGATE_EN_S 0 #define DPORT_APPCPU_CTRL_C_REG (DR_REG_DPORT_BASE + 0x034) + /* DPORT_APPCPU_RUNSTALL : R/W ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APPCPU_RUNSTALL (BIT(0)) #define DPORT_APPCPU_RUNSTALL_M (BIT(0)) #define DPORT_APPCPU_RUNSTALL_V 0x1 #define DPORT_APPCPU_RUNSTALL_S 0 #define DPORT_APPCPU_CTRL_D_REG (DR_REG_DPORT_BASE + 0x038) + /* DPORT_APPCPU_BOOT_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /* Description: */ + #define DPORT_APPCPU_BOOT_ADDR 0xFFFFFFFF #define DPORT_APPCPU_BOOT_ADDR_M ((DPORT_APPCPU_BOOT_ADDR_V)<<(DPORT_APPCPU_BOOT_ADDR_S)) #define DPORT_APPCPU_BOOT_ADDR_V 0xFFFFFFFF #define DPORT_APPCPU_BOOT_ADDR_S 0 #define DPORT_CPU_PER_CONF_REG (DR_REG_DPORT_BASE + 0x03C) + /* DPORT_FAST_CLK_RTC_SEL : R/W ;bitpos:[3] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_FAST_CLK_RTC_SEL (BIT(3)) #define DPORT_FAST_CLK_RTC_SEL_M (BIT(3)) #define DPORT_FAST_CLK_RTC_SEL_V 0x1 #define DPORT_FAST_CLK_RTC_SEL_S 3 + /* DPORT_LOWSPEED_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_LOWSPEED_CLK_SEL (BIT(2)) #define DPORT_LOWSPEED_CLK_SEL_M (BIT(2)) #define DPORT_LOWSPEED_CLK_SEL_V 0x1 #define DPORT_LOWSPEED_CLK_SEL_S 2 + /* DPORT_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ /* Description: */ + #define DPORT_CPUPERIOD_SEL 0x00000003 #define DPORT_CPUPERIOD_SEL_M ((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S)) #define DPORT_CPUPERIOD_SEL_V 0x3 #define DPORT_CPUPERIOD_SEL_S 0 #define DPORT_PRO_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x040) + /* DPORT_PRO_DRAM_HL : R/W ;bitpos:[16] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_DRAM_HL (BIT(16)) #define DPORT_PRO_DRAM_HL_M (BIT(16)) #define DPORT_PRO_DRAM_HL_V 0x1 #define DPORT_PRO_DRAM_HL_S 16 + /* DPORT_SLAVE_REQ : RO ;bitpos:[15] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_SLAVE_REQ (BIT(15)) #define DPORT_SLAVE_REQ_M (BIT(15)) #define DPORT_SLAVE_REQ_V 0x1 #define DPORT_SLAVE_REQ_S 15 + /* DPORT_AHB_SPI_REQ : RO ;bitpos:[14] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_AHB_SPI_REQ (BIT(14)) #define DPORT_AHB_SPI_REQ_M (BIT(14)) #define DPORT_AHB_SPI_REQ_V 0x1 #define DPORT_AHB_SPI_REQ_S 14 + /* DPORT_PRO_SLAVE_REQ : RO ;bitpos:[13] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_SLAVE_REQ (BIT(13)) #define DPORT_PRO_SLAVE_REQ_M (BIT(13)) #define DPORT_PRO_SLAVE_REQ_V 0x1 #define DPORT_PRO_SLAVE_REQ_S 13 + /* DPORT_PRO_AHB_SPI_REQ : RO ;bitpos:[12] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_AHB_SPI_REQ (BIT(12)) #define DPORT_PRO_AHB_SPI_REQ_M (BIT(12)) #define DPORT_PRO_AHB_SPI_REQ_V 0x1 #define DPORT_PRO_AHB_SPI_REQ_S 12 + /* DPORT_PRO_DRAM_SPLIT : R/W ;bitpos:[11] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_DRAM_SPLIT (BIT(11)) #define DPORT_PRO_DRAM_SPLIT_M (BIT(11)) #define DPORT_PRO_DRAM_SPLIT_V 0x1 #define DPORT_PRO_DRAM_SPLIT_S 11 + /* DPORT_PRO_SINGLE_IRAM_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_SINGLE_IRAM_ENA (BIT(10)) #define DPORT_PRO_SINGLE_IRAM_ENA_M (BIT(10)) #define DPORT_PRO_SINGLE_IRAM_ENA_V 0x1 #define DPORT_PRO_SINGLE_IRAM_ENA_S 10 + /* DPORT_PRO_CACHE_LOCK_3_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_LOCK_3_EN (BIT(9)) #define DPORT_PRO_CACHE_LOCK_3_EN_M (BIT(9)) #define DPORT_PRO_CACHE_LOCK_3_EN_V 0x1 #define DPORT_PRO_CACHE_LOCK_3_EN_S 9 + /* DPORT_PRO_CACHE_LOCK_2_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_LOCK_2_EN (BIT(8)) #define DPORT_PRO_CACHE_LOCK_2_EN_M (BIT(8)) #define DPORT_PRO_CACHE_LOCK_2_EN_V 0x1 #define DPORT_PRO_CACHE_LOCK_2_EN_S 8 + /* DPORT_PRO_CACHE_LOCK_1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_LOCK_1_EN (BIT(7)) #define DPORT_PRO_CACHE_LOCK_1_EN_M (BIT(7)) #define DPORT_PRO_CACHE_LOCK_1_EN_V 0x1 #define DPORT_PRO_CACHE_LOCK_1_EN_S 7 + /* DPORT_PRO_CACHE_LOCK_0_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_LOCK_0_EN (BIT(6)) #define DPORT_PRO_CACHE_LOCK_0_EN_M (BIT(6)) #define DPORT_PRO_CACHE_LOCK_0_EN_V 0x1 #define DPORT_PRO_CACHE_LOCK_0_EN_S 6 + /* DPORT_PRO_CACHE_FLUSH_DONE : RO ;bitpos:[5] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_FLUSH_DONE (BIT(5)) #define DPORT_PRO_CACHE_FLUSH_DONE_M (BIT(5)) #define DPORT_PRO_CACHE_FLUSH_DONE_V 0x1 #define DPORT_PRO_CACHE_FLUSH_DONE_S 5 + /* DPORT_PRO_CACHE_FLUSH_ENA : R/W ;bitpos:[4] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_PRO_CACHE_FLUSH_ENA (BIT(4)) #define DPORT_PRO_CACHE_FLUSH_ENA_M (BIT(4)) #define DPORT_PRO_CACHE_FLUSH_ENA_V 0x1 #define DPORT_PRO_CACHE_FLUSH_ENA_S 4 + /* DPORT_PRO_CACHE_ENABLE : R/W ;bitpos:[3] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_ENABLE (BIT(3)) #define DPORT_PRO_CACHE_ENABLE_M (BIT(3)) #define DPORT_PRO_CACHE_ENABLE_V 0x1 #define DPORT_PRO_CACHE_ENABLE_S 3 + /* DPORT_PRO_CACHE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_MODE (BIT(2)) #define DPORT_PRO_CACHE_MODE_M (BIT(2)) #define DPORT_PRO_CACHE_MODE_V 0x1 #define DPORT_PRO_CACHE_MODE_S 2 #define DPORT_PRO_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x044) + /* DPORT_PRO_CACHE_MMU_IA_CLR : R/W ;bitpos:[13] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_MMU_IA_CLR (BIT(13)) #define DPORT_PRO_CACHE_MMU_IA_CLR_M (BIT(13)) #define DPORT_PRO_CACHE_MMU_IA_CLR_V 0x1 #define DPORT_PRO_CACHE_MMU_IA_CLR_S 13 + /* DPORT_PRO_CMMU_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_CMMU_PD (BIT(12)) #define DPORT_PRO_CMMU_PD_M (BIT(12)) #define DPORT_PRO_CMMU_PD_V 0x1 #define DPORT_PRO_CMMU_PD_S 12 + /* DPORT_PRO_CMMU_FORCE_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_PRO_CMMU_FORCE_ON (BIT(11)) #define DPORT_PRO_CMMU_FORCE_ON_M (BIT(11)) #define DPORT_PRO_CMMU_FORCE_ON_V 0x1 #define DPORT_PRO_CMMU_FORCE_ON_S 11 + /* DPORT_PRO_CMMU_FLASH_PAGE_MODE : R/W ;bitpos:[10:9] ;default: 2'b0 ; */ /* Description: */ + #define DPORT_PRO_CMMU_FLASH_PAGE_MODE 0x00000003 #define DPORT_PRO_CMMU_FLASH_PAGE_MODE_M ((DPORT_PRO_CMMU_FLASH_PAGE_MODE_V)<<(DPORT_PRO_CMMU_FLASH_PAGE_MODE_S)) #define DPORT_PRO_CMMU_FLASH_PAGE_MODE_V 0x3 #define DPORT_PRO_CMMU_FLASH_PAGE_MODE_S 9 + /* DPORT_PRO_CMMU_SRAM_PAGE_MODE : R/W ;bitpos:[8:6] ;default: 3'd3 ; */ /* Description: */ + #define DPORT_PRO_CMMU_SRAM_PAGE_MODE 0x00000007 #define DPORT_PRO_CMMU_SRAM_PAGE_MODE_M ((DPORT_PRO_CMMU_SRAM_PAGE_MODE_V)<<(DPORT_PRO_CMMU_SRAM_PAGE_MODE_S)) #define DPORT_PRO_CMMU_SRAM_PAGE_MODE_V 0x7 #define DPORT_PRO_CMMU_SRAM_PAGE_MODE_S 6 + /* DPORT_PRO_CACHE_MASK_OPSDRAM : R/W ;bitpos:[5] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_PRO_CACHE_MASK_OPSDRAM (BIT(5)) #define DPORT_PRO_CACHE_MASK_OPSDRAM_M (BIT(5)) #define DPORT_PRO_CACHE_MASK_OPSDRAM_V 0x1 #define DPORT_PRO_CACHE_MASK_OPSDRAM_S 5 + /* DPORT_PRO_CACHE_MASK_DROM0 : R/W ;bitpos:[4] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_PRO_CACHE_MASK_DROM0 (BIT(4)) #define DPORT_PRO_CACHE_MASK_DROM0_M (BIT(4)) #define DPORT_PRO_CACHE_MASK_DROM0_V 0x1 #define DPORT_PRO_CACHE_MASK_DROM0_S 4 + /* DPORT_PRO_CACHE_MASK_DRAM1 : R/W ;bitpos:[3] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_PRO_CACHE_MASK_DRAM1 (BIT(3)) #define DPORT_PRO_CACHE_MASK_DRAM1_M (BIT(3)) #define DPORT_PRO_CACHE_MASK_DRAM1_V 0x1 #define DPORT_PRO_CACHE_MASK_DRAM1_S 3 + /* DPORT_PRO_CACHE_MASK_IROM0 : R/W ;bitpos:[2] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_PRO_CACHE_MASK_IROM0 (BIT(2)) #define DPORT_PRO_CACHE_MASK_IROM0_M (BIT(2)) #define DPORT_PRO_CACHE_MASK_IROM0_V 0x1 #define DPORT_PRO_CACHE_MASK_IROM0_S 2 + /* DPORT_PRO_CACHE_MASK_IRAM1 : R/W ;bitpos:[1] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_PRO_CACHE_MASK_IRAM1 (BIT(1)) #define DPORT_PRO_CACHE_MASK_IRAM1_M (BIT(1)) #define DPORT_PRO_CACHE_MASK_IRAM1_V 0x1 #define DPORT_PRO_CACHE_MASK_IRAM1_S 1 + /* DPORT_PRO_CACHE_MASK_IRAM0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_PRO_CACHE_MASK_IRAM0 (BIT(0)) #define DPORT_PRO_CACHE_MASK_IRAM0_M (BIT(0)) #define DPORT_PRO_CACHE_MASK_IRAM0_V 0x1 #define DPORT_PRO_CACHE_MASK_IRAM0_S 0 #define DPORT_PRO_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x048) + /* DPORT_PRO_CACHE_LOCK_0_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX 0x0000000F #define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S)) #define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_V 0xF #define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S 18 + /* DPORT_PRO_CACHE_LOCK_0_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN 0x0000000F #define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S)) #define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_V 0xF #define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S 14 + /* DPORT_PRO_CACHE_LOCK_0_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE 0x00003FFF #define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S)) #define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_V 0x3FFF #define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S 0 #define DPORT_PRO_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x04C) + /* DPORT_PRO_CACHE_LOCK_1_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX 0x0000000F #define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S)) #define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_V 0xF #define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S 18 + /* DPORT_PRO_CACHE_LOCK_1_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN 0x0000000F #define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S)) #define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_V 0xF #define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S 14 + /* DPORT_PRO_CACHE_LOCK_1_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE 0x00003FFF #define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S)) #define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_V 0x3FFF #define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S 0 #define DPORT_PRO_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x050) + /* DPORT_PRO_CACHE_LOCK_2_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX 0x0000000F #define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S)) #define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_V 0xF #define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S 18 + /* DPORT_PRO_CACHE_LOCK_2_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN 0x0000000F #define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S)) #define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_V 0xF #define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S 14 + /* DPORT_PRO_CACHE_LOCK_2_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE 0x00003FFF #define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S)) #define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_V 0x3FFF #define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S 0 #define DPORT_PRO_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x054) + /* DPORT_PRO_CACHE_LOCK_3_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX 0x0000000F #define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S)) #define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_V 0xF #define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S 18 + /* DPORT_PRO_CACHE_LOCK_3_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN 0x0000000F #define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S)) #define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_V 0xF #define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S 14 + /* DPORT_PRO_CACHE_LOCK_3_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE 0x00003FFF #define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_M ((DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V)<<(DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S)) #define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_V 0x3FFF #define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S 0 #define DPORT_APP_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x058) + /* DPORT_APP_DRAM_HL : R/W ;bitpos:[14] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_DRAM_HL (BIT(14)) #define DPORT_APP_DRAM_HL_M (BIT(14)) #define DPORT_APP_DRAM_HL_V 0x1 #define DPORT_APP_DRAM_HL_S 14 + /* DPORT_APP_SLAVE_REQ : RO ;bitpos:[13] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_SLAVE_REQ (BIT(13)) #define DPORT_APP_SLAVE_REQ_M (BIT(13)) #define DPORT_APP_SLAVE_REQ_V 0x1 #define DPORT_APP_SLAVE_REQ_S 13 + /* DPORT_APP_AHB_SPI_REQ : RO ;bitpos:[12] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_AHB_SPI_REQ (BIT(12)) #define DPORT_APP_AHB_SPI_REQ_M (BIT(12)) #define DPORT_APP_AHB_SPI_REQ_V 0x1 #define DPORT_APP_AHB_SPI_REQ_S 12 + /* DPORT_APP_DRAM_SPLIT : R/W ;bitpos:[11] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_DRAM_SPLIT (BIT(11)) #define DPORT_APP_DRAM_SPLIT_M (BIT(11)) #define DPORT_APP_DRAM_SPLIT_V 0x1 #define DPORT_APP_DRAM_SPLIT_S 11 + /* DPORT_APP_SINGLE_IRAM_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_SINGLE_IRAM_ENA (BIT(10)) #define DPORT_APP_SINGLE_IRAM_ENA_M (BIT(10)) #define DPORT_APP_SINGLE_IRAM_ENA_V 0x1 #define DPORT_APP_SINGLE_IRAM_ENA_S 10 + /* DPORT_APP_CACHE_LOCK_3_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_CACHE_LOCK_3_EN (BIT(9)) #define DPORT_APP_CACHE_LOCK_3_EN_M (BIT(9)) #define DPORT_APP_CACHE_LOCK_3_EN_V 0x1 #define DPORT_APP_CACHE_LOCK_3_EN_S 9 + /* DPORT_APP_CACHE_LOCK_2_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_CACHE_LOCK_2_EN (BIT(8)) #define DPORT_APP_CACHE_LOCK_2_EN_M (BIT(8)) #define DPORT_APP_CACHE_LOCK_2_EN_V 0x1 #define DPORT_APP_CACHE_LOCK_2_EN_S 8 + /* DPORT_APP_CACHE_LOCK_1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_CACHE_LOCK_1_EN (BIT(7)) #define DPORT_APP_CACHE_LOCK_1_EN_M (BIT(7)) #define DPORT_APP_CACHE_LOCK_1_EN_V 0x1 #define DPORT_APP_CACHE_LOCK_1_EN_S 7 + /* DPORT_APP_CACHE_LOCK_0_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_CACHE_LOCK_0_EN (BIT(6)) #define DPORT_APP_CACHE_LOCK_0_EN_M (BIT(6)) #define DPORT_APP_CACHE_LOCK_0_EN_V 0x1 #define DPORT_APP_CACHE_LOCK_0_EN_S 6 + /* DPORT_APP_CACHE_FLUSH_DONE : RO ;bitpos:[5] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_CACHE_FLUSH_DONE (BIT(5)) #define DPORT_APP_CACHE_FLUSH_DONE_M (BIT(5)) #define DPORT_APP_CACHE_FLUSH_DONE_V 0x1 #define DPORT_APP_CACHE_FLUSH_DONE_S 5 + /* DPORT_APP_CACHE_FLUSH_ENA : R/W ;bitpos:[4] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_APP_CACHE_FLUSH_ENA (BIT(4)) #define DPORT_APP_CACHE_FLUSH_ENA_M (BIT(4)) #define DPORT_APP_CACHE_FLUSH_ENA_V 0x1 #define DPORT_APP_CACHE_FLUSH_ENA_S 4 + /* DPORT_APP_CACHE_ENABLE : R/W ;bitpos:[3] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_CACHE_ENABLE (BIT(3)) #define DPORT_APP_CACHE_ENABLE_M (BIT(3)) #define DPORT_APP_CACHE_ENABLE_V 0x1 #define DPORT_APP_CACHE_ENABLE_S 3 + /* DPORT_APP_CACHE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_CACHE_MODE (BIT(2)) #define DPORT_APP_CACHE_MODE_M (BIT(2)) #define DPORT_APP_CACHE_MODE_V 0x1 #define DPORT_APP_CACHE_MODE_S 2 #define DPORT_APP_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x05C) + /* DPORT_APP_CACHE_MMU_IA_CLR : R/W ;bitpos:[13] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_CACHE_MMU_IA_CLR (BIT(13)) #define DPORT_APP_CACHE_MMU_IA_CLR_M (BIT(13)) #define DPORT_APP_CACHE_MMU_IA_CLR_V 0x1 #define DPORT_APP_CACHE_MMU_IA_CLR_S 13 + /* DPORT_APP_CMMU_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_CMMU_PD (BIT(12)) #define DPORT_APP_CMMU_PD_M (BIT(12)) #define DPORT_APP_CMMU_PD_V 0x1 #define DPORT_APP_CMMU_PD_S 12 + /* DPORT_APP_CMMU_FORCE_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_APP_CMMU_FORCE_ON (BIT(11)) #define DPORT_APP_CMMU_FORCE_ON_M (BIT(11)) #define DPORT_APP_CMMU_FORCE_ON_V 0x1 #define DPORT_APP_CMMU_FORCE_ON_S 11 + /* DPORT_APP_CMMU_FLASH_PAGE_MODE : R/W ;bitpos:[10:9] ;default: 2'b0 ; */ /* Description: */ + #define DPORT_APP_CMMU_FLASH_PAGE_MODE 0x00000003 #define DPORT_APP_CMMU_FLASH_PAGE_MODE_M ((DPORT_APP_CMMU_FLASH_PAGE_MODE_V)<<(DPORT_APP_CMMU_FLASH_PAGE_MODE_S)) #define DPORT_APP_CMMU_FLASH_PAGE_MODE_V 0x3 #define DPORT_APP_CMMU_FLASH_PAGE_MODE_S 9 + /* DPORT_APP_CMMU_SRAM_PAGE_MODE : R/W ;bitpos:[8:6] ;default: 3'd3 ; */ /* Description: */ + #define DPORT_APP_CMMU_SRAM_PAGE_MODE 0x00000007 #define DPORT_APP_CMMU_SRAM_PAGE_MODE_M ((DPORT_APP_CMMU_SRAM_PAGE_MODE_V)<<(DPORT_APP_CMMU_SRAM_PAGE_MODE_S)) #define DPORT_APP_CMMU_SRAM_PAGE_MODE_V 0x7 #define DPORT_APP_CMMU_SRAM_PAGE_MODE_S 6 + /* DPORT_APP_CACHE_MASK_OPSDRAM : R/W ;bitpos:[5] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_APP_CACHE_MASK_OPSDRAM (BIT(5)) #define DPORT_APP_CACHE_MASK_OPSDRAM_M (BIT(5)) #define DPORT_APP_CACHE_MASK_OPSDRAM_V 0x1 #define DPORT_APP_CACHE_MASK_OPSDRAM_S 5 + /* DPORT_APP_CACHE_MASK_DROM0 : R/W ;bitpos:[4] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_APP_CACHE_MASK_DROM0 (BIT(4)) #define DPORT_APP_CACHE_MASK_DROM0_M (BIT(4)) #define DPORT_APP_CACHE_MASK_DROM0_V 0x1 #define DPORT_APP_CACHE_MASK_DROM0_S 4 + /* DPORT_APP_CACHE_MASK_DRAM1 : R/W ;bitpos:[3] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_APP_CACHE_MASK_DRAM1 (BIT(3)) #define DPORT_APP_CACHE_MASK_DRAM1_M (BIT(3)) #define DPORT_APP_CACHE_MASK_DRAM1_V 0x1 #define DPORT_APP_CACHE_MASK_DRAM1_S 3 + /* DPORT_APP_CACHE_MASK_IROM0 : R/W ;bitpos:[2] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_APP_CACHE_MASK_IROM0 (BIT(2)) #define DPORT_APP_CACHE_MASK_IROM0_M (BIT(2)) #define DPORT_APP_CACHE_MASK_IROM0_V 0x1 #define DPORT_APP_CACHE_MASK_IROM0_S 2 + /* DPORT_APP_CACHE_MASK_IRAM1 : R/W ;bitpos:[1] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_APP_CACHE_MASK_IRAM1 (BIT(1)) #define DPORT_APP_CACHE_MASK_IRAM1_M (BIT(1)) #define DPORT_APP_CACHE_MASK_IRAM1_V 0x1 #define DPORT_APP_CACHE_MASK_IRAM1_S 1 + /* DPORT_APP_CACHE_MASK_IRAM0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_APP_CACHE_MASK_IRAM0 (BIT(0)) #define DPORT_APP_CACHE_MASK_IRAM0_M (BIT(0)) #define DPORT_APP_CACHE_MASK_IRAM0_V 0x1 #define DPORT_APP_CACHE_MASK_IRAM0_S 0 #define DPORT_APP_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x060) + /* DPORT_APP_CACHE_LOCK_0_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ /* Description: */ + #define DPORT_APP_CACHE_LOCK_0_ADDR_MAX 0x0000000F #define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S)) #define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_V 0xF #define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S 18 + /* DPORT_APP_CACHE_LOCK_0_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ /* Description: */ + #define DPORT_APP_CACHE_LOCK_0_ADDR_MIN 0x0000000F #define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S)) #define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_V 0xF #define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S 14 + /* DPORT_APP_CACHE_LOCK_0_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ /* Description: */ + #define DPORT_APP_CACHE_LOCK_0_ADDR_PRE 0x00003FFF #define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S)) #define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_V 0x3FFF #define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S 0 #define DPORT_APP_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x064) + /* DPORT_APP_CACHE_LOCK_1_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ /* Description: */ + #define DPORT_APP_CACHE_LOCK_1_ADDR_MAX 0x0000000F #define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S)) #define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_V 0xF #define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S 18 + /* DPORT_APP_CACHE_LOCK_1_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ /* Description: */ + #define DPORT_APP_CACHE_LOCK_1_ADDR_MIN 0x0000000F #define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S)) #define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_V 0xF #define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S 14 + /* DPORT_APP_CACHE_LOCK_1_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ /* Description: */ + #define DPORT_APP_CACHE_LOCK_1_ADDR_PRE 0x00003FFF #define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S)) #define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_V 0x3FFF #define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S 0 #define DPORT_APP_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x068) + /* DPORT_APP_CACHE_LOCK_2_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ /* Description: */ + #define DPORT_APP_CACHE_LOCK_2_ADDR_MAX 0x0000000F #define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S)) #define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_V 0xF #define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S 18 + /* DPORT_APP_CACHE_LOCK_2_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ /* Description: */ + #define DPORT_APP_CACHE_LOCK_2_ADDR_MIN 0x0000000F #define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S)) #define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_V 0xF #define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S 14 + /* DPORT_APP_CACHE_LOCK_2_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ /* Description: */ + #define DPORT_APP_CACHE_LOCK_2_ADDR_PRE 0x00003FFF #define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S)) #define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_V 0x3FFF #define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S 0 #define DPORT_APP_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x06C) + /* DPORT_APP_CACHE_LOCK_3_ADDR_MAX : R/W ;bitpos:[21:18] ;default: 4'h0 ; */ /* Description: */ + #define DPORT_APP_CACHE_LOCK_3_ADDR_MAX 0x0000000F #define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_M ((DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S)) #define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_V 0xF #define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S 18 + /* DPORT_APP_CACHE_LOCK_3_ADDR_MIN : R/W ;bitpos:[17:14] ;default: 4'h0 ; */ /* Description: */ + #define DPORT_APP_CACHE_LOCK_3_ADDR_MIN 0x0000000F #define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_M ((DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S)) #define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_V 0xF #define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S 14 + /* DPORT_APP_CACHE_LOCK_3_ADDR_PRE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ /* Description: */ + #define DPORT_APP_CACHE_LOCK_3_ADDR_PRE 0x00003FFF #define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_M ((DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V)<<(DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S)) #define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_V 0x3FFF #define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S 0 #define DPORT_TRACEMEM_MUX_MODE_REG (DR_REG_DPORT_BASE + 0x070) + /* DPORT_TRACEMEM_MUX_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ /* Description: */ + #define DPORT_TRACEMEM_MUX_MODE 0x00000003 #define DPORT_TRACEMEM_MUX_MODE_M ((DPORT_TRACEMEM_MUX_MODE_V)<<(DPORT_TRACEMEM_MUX_MODE_S)) #define DPORT_TRACEMEM_MUX_MODE_V 0x3 #define DPORT_TRACEMEM_MUX_MODE_S 0 #define DPORT_PRO_TRACEMEM_ENA_REG (DR_REG_DPORT_BASE + 0x074) + /* DPORT_PRO_TRACEMEM_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_TRACEMEM_ENA (BIT(0)) #define DPORT_PRO_TRACEMEM_ENA_M (BIT(0)) #define DPORT_PRO_TRACEMEM_ENA_V 0x1 #define DPORT_PRO_TRACEMEM_ENA_S 0 #define DPORT_APP_TRACEMEM_ENA_REG (DR_REG_DPORT_BASE + 0x078) + /* DPORT_APP_TRACEMEM_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_TRACEMEM_ENA (BIT(0)) #define DPORT_APP_TRACEMEM_ENA_M (BIT(0)) #define DPORT_APP_TRACEMEM_ENA_V 0x1 #define DPORT_APP_TRACEMEM_ENA_S 0 #define DPORT_CACHE_MUX_MODE_REG (DR_REG_DPORT_BASE + 0x07C) + /* DPORT_CACHE_MUX_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ /* Description: */ + #define DPORT_CACHE_MUX_MODE 0x00000003 #define DPORT_CACHE_MUX_MODE_M ((DPORT_CACHE_MUX_MODE_V)<<(DPORT_CACHE_MUX_MODE_S)) #define DPORT_CACHE_MUX_MODE_V 0x3 #define DPORT_CACHE_MUX_MODE_S 0 #define DPORT_IMMU_PAGE_MODE_REG (DR_REG_DPORT_BASE + 0x080) + /* DPORT_IMMU_PAGE_MODE : R/W ;bitpos:[2:1] ;default: 2'b0 ; */ /* Description: */ + #define DPORT_IMMU_PAGE_MODE 0x00000003 #define DPORT_IMMU_PAGE_MODE_M ((DPORT_IMMU_PAGE_MODE_V)<<(DPORT_IMMU_PAGE_MODE_S)) #define DPORT_IMMU_PAGE_MODE_V 0x3 #define DPORT_IMMU_PAGE_MODE_S 1 + /* DPORT_INTERNAL_SRAM_IMMU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_INTERNAL_SRAM_IMMU_ENA (BIT(0)) #define DPORT_INTERNAL_SRAM_IMMU_ENA_M (BIT(0)) #define DPORT_INTERNAL_SRAM_IMMU_ENA_V 0x1 #define DPORT_INTERNAL_SRAM_IMMU_ENA_S 0 #define DPORT_DMMU_PAGE_MODE_REG (DR_REG_DPORT_BASE + 0x084) + /* DPORT_DMMU_PAGE_MODE : R/W ;bitpos:[2:1] ;default: 2'b0 ; */ /* Description: */ + #define DPORT_DMMU_PAGE_MODE 0x00000003 #define DPORT_DMMU_PAGE_MODE_M ((DPORT_DMMU_PAGE_MODE_V)<<(DPORT_DMMU_PAGE_MODE_S)) #define DPORT_DMMU_PAGE_MODE_V 0x3 #define DPORT_DMMU_PAGE_MODE_S 1 + /* DPORT_INTERNAL_SRAM_DMMU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_INTERNAL_SRAM_DMMU_ENA (BIT(0)) #define DPORT_INTERNAL_SRAM_DMMU_ENA_M (BIT(0)) #define DPORT_INTERNAL_SRAM_DMMU_ENA_V 0x1 #define DPORT_INTERNAL_SRAM_DMMU_ENA_S 0 #define DPORT_ROM_MPU_ENA_REG (DR_REG_DPORT_BASE + 0x088) + /* DPORT_APP_ROM_MPU_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_ROM_MPU_ENA (BIT(2)) #define DPORT_APP_ROM_MPU_ENA_M (BIT(2)) #define DPORT_APP_ROM_MPU_ENA_V 0x1 #define DPORT_APP_ROM_MPU_ENA_S 2 + /* DPORT_PRO_ROM_MPU_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_ROM_MPU_ENA (BIT(1)) #define DPORT_PRO_ROM_MPU_ENA_M (BIT(1)) #define DPORT_PRO_ROM_MPU_ENA_V 0x1 #define DPORT_PRO_ROM_MPU_ENA_S 1 + /* DPORT_SHARE_ROM_MPU_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_SHARE_ROM_MPU_ENA (BIT(0)) #define DPORT_SHARE_ROM_MPU_ENA_M (BIT(0)) #define DPORT_SHARE_ROM_MPU_ENA_V 0x1 #define DPORT_SHARE_ROM_MPU_ENA_S 0 #define DPORT_MEM_PD_MASK_REG (DR_REG_DPORT_BASE + 0x08C) + /* DPORT_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_LSLP_MEM_PD_MASK (BIT(0)) #define DPORT_LSLP_MEM_PD_MASK_M (BIT(0)) #define DPORT_LSLP_MEM_PD_MASK_V 0x1 #define DPORT_LSLP_MEM_PD_MASK_S 0 #define DPORT_ROM_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x090) + /* DPORT_SHARE_ROM_PD : R/W ;bitpos:[7:2] ;default: 6'h0 ; */ /* Description: */ + #define DPORT_SHARE_ROM_PD 0x0000003F #define DPORT_SHARE_ROM_PD_M ((DPORT_SHARE_ROM_PD_V)<<(DPORT_SHARE_ROM_PD_S)) #define DPORT_SHARE_ROM_PD_V 0x3F #define DPORT_SHARE_ROM_PD_S 2 + /* DPORT_APP_ROM_PD : R/W ;bitpos:[1] ;default: 1'h0 ; */ /* Description: */ + #define DPORT_APP_ROM_PD (BIT(1)) #define DPORT_APP_ROM_PD_M (BIT(1)) #define DPORT_APP_ROM_PD_V 0x1 #define DPORT_APP_ROM_PD_S 1 + /* DPORT_PRO_ROM_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */ /* Description: */ + #define DPORT_PRO_ROM_PD (BIT(0)) #define DPORT_PRO_ROM_PD_M (BIT(0)) #define DPORT_PRO_ROM_PD_V 0x1 #define DPORT_PRO_ROM_PD_S 0 #define DPORT_ROM_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x094) + /* DPORT_SHARE_ROM_FO : R/W ;bitpos:[7:2] ;default: 6'h0 ; */ /* Description: */ + #define DPORT_SHARE_ROM_FO 0x0000003F #define DPORT_SHARE_ROM_FO_M ((DPORT_SHARE_ROM_FO_V)<<(DPORT_SHARE_ROM_FO_S)) #define DPORT_SHARE_ROM_FO_V 0x3F #define DPORT_SHARE_ROM_FO_S 2 + /* DPORT_APP_ROM_FO : R/W ;bitpos:[1] ;default: 1'h1 ; */ /* Description: */ + #define DPORT_APP_ROM_FO (BIT(1)) #define DPORT_APP_ROM_FO_M (BIT(1)) #define DPORT_APP_ROM_FO_V 0x1 #define DPORT_APP_ROM_FO_S 1 + /* DPORT_PRO_ROM_FO : R/W ;bitpos:[0] ;default: 1'h1 ; */ /* Description: */ + #define DPORT_PRO_ROM_FO (BIT(0)) #define DPORT_PRO_ROM_FO_M (BIT(0)) #define DPORT_PRO_ROM_FO_V 0x1 #define DPORT_PRO_ROM_FO_S 0 #define DPORT_SRAM_PD_CTRL_0_REG (DR_REG_DPORT_BASE + 0x098) + /* DPORT_SRAM_PD_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /* Description: */ + #define DPORT_SRAM_PD_0 0xFFFFFFFF #define DPORT_SRAM_PD_0_M ((DPORT_SRAM_PD_0_V)<<(DPORT_SRAM_PD_0_S)) #define DPORT_SRAM_PD_0_V 0xFFFFFFFF #define DPORT_SRAM_PD_0_S 0 #define DPORT_SRAM_PD_CTRL_1_REG (DR_REG_DPORT_BASE + 0x09C) + /* DPORT_SRAM_PD_1 : R/W ;bitpos:[0] ;default: 1'h0 ; */ /* Description: */ + #define DPORT_SRAM_PD_1 (BIT(0)) #define DPORT_SRAM_PD_1_M (BIT(0)) #define DPORT_SRAM_PD_1_V 0x1 #define DPORT_SRAM_PD_1_S 0 #define DPORT_SRAM_FO_CTRL_0_REG (DR_REG_DPORT_BASE + 0x0A0) + /* DPORT_SRAM_FO_0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ /* Description: */ + #define DPORT_SRAM_FO_0 0xFFFFFFFF #define DPORT_SRAM_FO_0_M ((DPORT_SRAM_FO_0_V)<<(DPORT_SRAM_FO_0_S)) #define DPORT_SRAM_FO_0_V 0xFFFFFFFF #define DPORT_SRAM_FO_0_S 0 #define DPORT_SRAM_FO_CTRL_1_REG (DR_REG_DPORT_BASE + 0x0A4) + /* DPORT_SRAM_FO_1 : R/W ;bitpos:[0] ;default: 1'h1 ; */ /* Description: */ + #define DPORT_SRAM_FO_1 (BIT(0)) #define DPORT_SRAM_FO_1_M (BIT(0)) #define DPORT_SRAM_FO_1_V 0x1 #define DPORT_SRAM_FO_1_S 0 #define DPORT_IRAM_DRAM_AHB_SEL_REG (DR_REG_DPORT_BASE + 0x0A8) + /* DPORT_MAC_DUMP_MODE : R/W ;bitpos:[6:5] ;default: 2'h0 ; */ /* Description: */ + #define DPORT_MAC_DUMP_MODE 0x00000003 #define DPORT_MAC_DUMP_MODE_M ((DPORT_MAC_DUMP_MODE_V)<<(DPORT_MAC_DUMP_MODE_S)) #define DPORT_MAC_DUMP_MODE_V 0x3 #define DPORT_MAC_DUMP_MODE_S 5 + /* DPORT_MASK_AHB : R/W ;bitpos:[4] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_MASK_AHB (BIT(4)) #define DPORT_MASK_AHB_M (BIT(4)) #define DPORT_MASK_AHB_V 0x1 #define DPORT_MASK_AHB_S 4 + /* DPORT_MASK_APP_DRAM : R/W ;bitpos:[3] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_MASK_APP_DRAM (BIT(3)) #define DPORT_MASK_APP_DRAM_M (BIT(3)) #define DPORT_MASK_APP_DRAM_V 0x1 #define DPORT_MASK_APP_DRAM_S 3 + /* DPORT_MASK_PRO_DRAM : R/W ;bitpos:[2] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_MASK_PRO_DRAM (BIT(2)) #define DPORT_MASK_PRO_DRAM_M (BIT(2)) #define DPORT_MASK_PRO_DRAM_V 0x1 #define DPORT_MASK_PRO_DRAM_S 2 + /* DPORT_MASK_APP_IRAM : R/W ;bitpos:[1] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_MASK_APP_IRAM (BIT(1)) #define DPORT_MASK_APP_IRAM_M (BIT(1)) #define DPORT_MASK_APP_IRAM_V 0x1 #define DPORT_MASK_APP_IRAM_S 1 + /* DPORT_MASK_PRO_IRAM : R/W ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_MASK_PRO_IRAM (BIT(0)) #define DPORT_MASK_PRO_IRAM_M (BIT(0)) #define DPORT_MASK_PRO_IRAM_V 0x1 #define DPORT_MASK_PRO_IRAM_S 0 #define DPORT_TAG_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x0AC) + /* DPORT_APP_CACHE_TAG_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_CACHE_TAG_PD (BIT(9)) #define DPORT_APP_CACHE_TAG_PD_M (BIT(9)) #define DPORT_APP_CACHE_TAG_PD_V 0x1 #define DPORT_APP_CACHE_TAG_PD_S 9 + /* DPORT_APP_CACHE_TAG_FORCE_ON : R/W ;bitpos:[8] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_APP_CACHE_TAG_FORCE_ON (BIT(8)) #define DPORT_APP_CACHE_TAG_FORCE_ON_M (BIT(8)) #define DPORT_APP_CACHE_TAG_FORCE_ON_V 0x1 #define DPORT_APP_CACHE_TAG_FORCE_ON_S 8 + /* DPORT_PRO_CACHE_TAG_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_TAG_PD (BIT(1)) #define DPORT_PRO_CACHE_TAG_PD_M (BIT(1)) #define DPORT_PRO_CACHE_TAG_PD_V 0x1 #define DPORT_PRO_CACHE_TAG_PD_S 1 + /* DPORT_PRO_CACHE_TAG_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_PRO_CACHE_TAG_FORCE_ON (BIT(0)) #define DPORT_PRO_CACHE_TAG_FORCE_ON_M (BIT(0)) #define DPORT_PRO_CACHE_TAG_FORCE_ON_V 0x1 #define DPORT_PRO_CACHE_TAG_FORCE_ON_S 0 #define DPORT_AHB_LITE_MASK_REG (DR_REG_DPORT_BASE + 0x0B0) + /* DPORT_AHB_LITE_SDHOST_PID_REG : R/W ;bitpos:[13:11] ;default: 3'b0 ; */ /* Description: */ + #define DPORT_AHB_LITE_SDHOST_PID_REG 0x00000007 #define DPORT_AHB_LITE_SDHOST_PID_REG_M ((DPORT_AHB_LITE_SDHOST_PID_REG_V)<<(DPORT_AHB_LITE_SDHOST_PID_REG_S)) #define DPORT_AHB_LITE_SDHOST_PID_REG_V 0x7 #define DPORT_AHB_LITE_SDHOST_PID_REG_S 11 + /* DPORT_AHB_LITE_MASK_APPDPORT : R/W ;bitpos:[10] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_AHB_LITE_MASK_APPDPORT (BIT(10)) #define DPORT_AHB_LITE_MASK_APPDPORT_M (BIT(10)) #define DPORT_AHB_LITE_MASK_APPDPORT_V 0x1 #define DPORT_AHB_LITE_MASK_APPDPORT_S 10 + /* DPORT_AHB_LITE_MASK_PRODPORT : R/W ;bitpos:[9] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_AHB_LITE_MASK_PRODPORT (BIT(9)) #define DPORT_AHB_LITE_MASK_PRODPORT_M (BIT(9)) #define DPORT_AHB_LITE_MASK_PRODPORT_V 0x1 #define DPORT_AHB_LITE_MASK_PRODPORT_S 9 + /* DPORT_AHB_LITE_MASK_SDIO : R/W ;bitpos:[8] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_AHB_LITE_MASK_SDIO (BIT(8)) #define DPORT_AHB_LITE_MASK_SDIO_M (BIT(8)) #define DPORT_AHB_LITE_MASK_SDIO_V 0x1 #define DPORT_AHB_LITE_MASK_SDIO_S 8 + /* DPORT_AHB_LITE_MASK_APP : R/W ;bitpos:[4] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_AHB_LITE_MASK_APP (BIT(4)) #define DPORT_AHB_LITE_MASK_APP_M (BIT(4)) #define DPORT_AHB_LITE_MASK_APP_V 0x1 #define DPORT_AHB_LITE_MASK_APP_S 4 + /* DPORT_AHB_LITE_MASK_PRO : R/W ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_AHB_LITE_MASK_PRO (BIT(0)) #define DPORT_AHB_LITE_MASK_PRO_M (BIT(0)) #define DPORT_AHB_LITE_MASK_PRO_V 0x1 #define DPORT_AHB_LITE_MASK_PRO_S 0 #define DPORT_AHB_MPU_TABLE_0_REG (DR_REG_DPORT_BASE + 0x0B4) + /* DPORT_AHB_ACCESS_GRANT_0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ /* Description: */ + #define DPORT_AHB_ACCESS_GRANT_0 0xFFFFFFFF #define DPORT_AHB_ACCESS_GRANT_0_M ((DPORT_AHB_ACCESS_GRANT_0_V)<<(DPORT_AHB_ACCESS_GRANT_0_S)) #define DPORT_AHB_ACCESS_GRANT_0_V 0xFFFFFFFF #define DPORT_AHB_ACCESS_GRANT_0_S 0 #define DPORT_AHB_MPU_TABLE_1_REG (DR_REG_DPORT_BASE + 0x0B8) + /* DPORT_AHB_ACCESS_GRANT_1 : R/W ;bitpos:[8:0] ;default: 9'h1ff ; */ /* Description: */ + #define DPORT_AHB_ACCESS_GRANT_1 0x000001FF #define DPORT_AHB_ACCESS_GRANT_1_M ((DPORT_AHB_ACCESS_GRANT_1_V)<<(DPORT_AHB_ACCESS_GRANT_1_S)) #define DPORT_AHB_ACCESS_GRANT_1_V 0x1FF #define DPORT_AHB_ACCESS_GRANT_1_S 0 #define DPORT_HOST_INF_SEL_REG (DR_REG_DPORT_BASE + 0x0BC) + /* DPORT_LINK_DEVICE_SEL : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ /* Description: */ + #define DPORT_LINK_DEVICE_SEL 0x000000FF #define DPORT_LINK_DEVICE_SEL_M ((DPORT_LINK_DEVICE_SEL_V)<<(DPORT_LINK_DEVICE_SEL_S)) #define DPORT_LINK_DEVICE_SEL_V 0xFF #define DPORT_LINK_DEVICE_SEL_S 8 + /* DPORT_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ /* Description: */ + #define DPORT_PERI_IO_SWAP 0x000000FF #define DPORT_PERI_IO_SWAP_M ((DPORT_PERI_IO_SWAP_V)<<(DPORT_PERI_IO_SWAP_S)) #define DPORT_PERI_IO_SWAP_V 0xFF #define DPORT_PERI_IO_SWAP_S 0 #define DPORT_PERIP_CLK_EN_REG (DR_REG_DPORT_BASE + 0x0C0) + /* DPORT_PERIP_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hf9c1e06f ; */ /* Description: */ + #define DPORT_PERIP_CLK_EN 0xFFFFFFFF #define DPORT_PERIP_CLK_EN_M ((DPORT_PERIP_CLK_EN_V)<<(DPORT_PERIP_CLK_EN_S)) #define DPORT_PERIP_CLK_EN_V 0xFFFFFFFF @@ -979,8 +1251,10 @@ #define DPORT_SPI_CLK_EN_1 (BIT(1)) #define DPORT_TIMERS_CLK_EN (BIT(0)) #define DPORT_PERIP_RST_EN_REG (DR_REG_DPORT_BASE + 0x0C4) + /* DPORT_PERIP_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /* Description: */ + #define DPORT_PERIP_RST 0xFFFFFFFF #define DPORT_PERIP_RST_M ((DPORT_PERIP_RST_V)<<(DPORT_PERIP_RST_S)) #define DPORT_PERIP_RST_V 0xFFFFFFFF @@ -1013,2838 +1287,3572 @@ #define DPORT_SPI_RST_1 (BIT(1)) #define DPORT_TIMERS_RST (BIT(0)) #define DPORT_SLAVE_SPI_CONFIG_REG (DR_REG_DPORT_BASE + 0x0C8) + /* DPORT_SPI_DECRYPT_ENABLE : R/W ;bitpos:[12] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_SPI_DECRYPT_ENABLE (BIT(12)) #define DPORT_SPI_DECRYPT_ENABLE_M (BIT(12)) #define DPORT_SPI_DECRYPT_ENABLE_V 0x1 #define DPORT_SPI_DECRYPT_ENABLE_S 12 + /* DPORT_SPI_ENCRYPT_ENABLE : R/W ;bitpos:[8] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_SPI_ENCRYPT_ENABLE (BIT(8)) #define DPORT_SPI_ENCRYPT_ENABLE_M (BIT(8)) #define DPORT_SPI_ENCRYPT_ENABLE_V 0x1 #define DPORT_SPI_ENCRYPT_ENABLE_S 8 + /* DPORT_SLAVE_SPI_MASK_APP : R/W ;bitpos:[4] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_SLAVE_SPI_MASK_APP (BIT(4)) #define DPORT_SLAVE_SPI_MASK_APP_M (BIT(4)) #define DPORT_SLAVE_SPI_MASK_APP_V 0x1 #define DPORT_SLAVE_SPI_MASK_APP_S 4 + /* DPORT_SLAVE_SPI_MASK_PRO : R/W ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_SLAVE_SPI_MASK_PRO (BIT(0)) #define DPORT_SLAVE_SPI_MASK_PRO_M (BIT(0)) #define DPORT_SLAVE_SPI_MASK_PRO_V 0x1 #define DPORT_SLAVE_SPI_MASK_PRO_S 0 #define DPORT_WIFI_CLK_EN_REG (DR_REG_DPORT_BASE + 0x0CC) + /* DPORT_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ /* Description: */ + #define DPORT_WIFI_CLK_EN 0xFFFFFFFF #define DPORT_WIFI_CLK_EN_M ((DPORT_WIFI_CLK_EN_V)<<(DPORT_WIFI_CLK_EN_S)) #define DPORT_WIFI_CLK_EN_V 0xFFFFFFFF #define DPORT_WIFI_CLK_EN_S 0 #define DPORT_WIFI_RST_EN_REG (DR_REG_DPORT_BASE + 0x0D0) + /* DPORT_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ /* Description: */ + #define DPORT_WIFI_RST 0xFFFFFFFF #define DPORT_WIFI_RST_M ((DPORT_WIFI_RST_V)<<(DPORT_WIFI_RST_S)) #define DPORT_WIFI_RST_V 0xFFFFFFFF #define DPORT_WIFI_RST_S 0 #define DPORT_BT_LPCK_DIV_INT_REG (DR_REG_DPORT_BASE + 0x0D4) + /* DPORT_BTEXTWAKEUP_REQ : R/W ;bitpos:[12] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_BTEXTWAKEUP_REQ (BIT(12)) #define DPORT_BTEXTWAKEUP_REQ_M (BIT(12)) #define DPORT_BTEXTWAKEUP_REQ_V 0x1 #define DPORT_BTEXTWAKEUP_REQ_S 12 + /* DPORT_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */ /* Description: */ + #define DPORT_BT_LPCK_DIV_NUM 0x00000FFF #define DPORT_BT_LPCK_DIV_NUM_M ((DPORT_BT_LPCK_DIV_NUM_V)<<(DPORT_BT_LPCK_DIV_NUM_S)) #define DPORT_BT_LPCK_DIV_NUM_V 0xFFF #define DPORT_BT_LPCK_DIV_NUM_S 0 #define DPORT_BT_LPCK_DIV_FRAC_REG (DR_REG_DPORT_BASE + 0x0D8) + /* DPORT_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_LPCLK_SEL_XTAL32K (BIT(27)) #define DPORT_LPCLK_SEL_XTAL32K_M (BIT(27)) #define DPORT_LPCLK_SEL_XTAL32K_V 0x1 #define DPORT_LPCLK_SEL_XTAL32K_S 27 + /* DPORT_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_LPCLK_SEL_XTAL (BIT(26)) #define DPORT_LPCLK_SEL_XTAL_M (BIT(26)) #define DPORT_LPCLK_SEL_XTAL_V 0x1 #define DPORT_LPCLK_SEL_XTAL_S 26 + /* DPORT_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_LPCLK_SEL_8M (BIT(25)) #define DPORT_LPCLK_SEL_8M_M (BIT(25)) #define DPORT_LPCLK_SEL_8M_V 0x1 #define DPORT_LPCLK_SEL_8M_S 25 + /* DPORT_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_LPCLK_SEL_RTC_SLOW (BIT(24)) #define DPORT_LPCLK_SEL_RTC_SLOW_M (BIT(24)) #define DPORT_LPCLK_SEL_RTC_SLOW_V 0x1 #define DPORT_LPCLK_SEL_RTC_SLOW_S 24 + /* DPORT_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */ /* Description: */ + #define DPORT_BT_LPCK_DIV_A 0x00000FFF #define DPORT_BT_LPCK_DIV_A_M ((DPORT_BT_LPCK_DIV_A_V)<<(DPORT_BT_LPCK_DIV_A_S)) #define DPORT_BT_LPCK_DIV_A_V 0xFFF #define DPORT_BT_LPCK_DIV_A_S 12 + /* DPORT_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */ /* Description: */ + #define DPORT_BT_LPCK_DIV_B 0x00000FFF #define DPORT_BT_LPCK_DIV_B_M ((DPORT_BT_LPCK_DIV_B_V)<<(DPORT_BT_LPCK_DIV_B_S)) #define DPORT_BT_LPCK_DIV_B_V 0xFFF #define DPORT_BT_LPCK_DIV_B_S 0 #define DPORT_CPU_INTR_FROM_CPU_0_REG (DR_REG_DPORT_BASE + 0x0DC) + /* DPORT_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_CPU_INTR_FROM_CPU_0 (BIT(0)) #define DPORT_CPU_INTR_FROM_CPU_0_M (BIT(0)) #define DPORT_CPU_INTR_FROM_CPU_0_V 0x1 #define DPORT_CPU_INTR_FROM_CPU_0_S 0 #define DPORT_CPU_INTR_FROM_CPU_1_REG (DR_REG_DPORT_BASE + 0x0E0) + /* DPORT_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_CPU_INTR_FROM_CPU_1 (BIT(0)) #define DPORT_CPU_INTR_FROM_CPU_1_M (BIT(0)) #define DPORT_CPU_INTR_FROM_CPU_1_V 0x1 #define DPORT_CPU_INTR_FROM_CPU_1_S 0 #define DPORT_CPU_INTR_FROM_CPU_2_REG (DR_REG_DPORT_BASE + 0x0E4) + /* DPORT_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_CPU_INTR_FROM_CPU_2 (BIT(0)) #define DPORT_CPU_INTR_FROM_CPU_2_M (BIT(0)) #define DPORT_CPU_INTR_FROM_CPU_2_V 0x1 #define DPORT_CPU_INTR_FROM_CPU_2_S 0 #define DPORT_CPU_INTR_FROM_CPU_3_REG (DR_REG_DPORT_BASE + 0x0E8) + /* DPORT_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_CPU_INTR_FROM_CPU_3 (BIT(0)) #define DPORT_CPU_INTR_FROM_CPU_3_M (BIT(0)) #define DPORT_CPU_INTR_FROM_CPU_3_V 0x1 #define DPORT_CPU_INTR_FROM_CPU_3_S 0 #define DPORT_PRO_INTR_STATUS_0_REG (DR_REG_DPORT_BASE + 0x0EC) + /* DPORT_PRO_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /* Description: */ + #define DPORT_PRO_INTR_STATUS_0 0xFFFFFFFF #define DPORT_PRO_INTR_STATUS_0_M ((DPORT_PRO_INTR_STATUS_0_V)<<(DPORT_PRO_INTR_STATUS_0_S)) #define DPORT_PRO_INTR_STATUS_0_V 0xFFFFFFFF #define DPORT_PRO_INTR_STATUS_0_S 0 #define DPORT_PRO_INTR_STATUS_1_REG (DR_REG_DPORT_BASE + 0x0F0) + /* DPORT_PRO_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /* Description: */ + #define DPORT_PRO_INTR_STATUS_1 0xFFFFFFFF #define DPORT_PRO_INTR_STATUS_1_M ((DPORT_PRO_INTR_STATUS_1_V)<<(DPORT_PRO_INTR_STATUS_1_S)) #define DPORT_PRO_INTR_STATUS_1_V 0xFFFFFFFF #define DPORT_PRO_INTR_STATUS_1_S 0 #define DPORT_PRO_INTR_STATUS_2_REG (DR_REG_DPORT_BASE + 0x0F4) + /* DPORT_PRO_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /* Description: */ + #define DPORT_PRO_INTR_STATUS_2 0xFFFFFFFF #define DPORT_PRO_INTR_STATUS_2_M ((DPORT_PRO_INTR_STATUS_2_V)<<(DPORT_PRO_INTR_STATUS_2_S)) #define DPORT_PRO_INTR_STATUS_2_V 0xFFFFFFFF #define DPORT_PRO_INTR_STATUS_2_S 0 #define DPORT_APP_INTR_STATUS_0_REG (DR_REG_DPORT_BASE + 0x0F8) + /* DPORT_APP_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /* Description: */ + #define DPORT_APP_INTR_STATUS_0 0xFFFFFFFF #define DPORT_APP_INTR_STATUS_0_M ((DPORT_APP_INTR_STATUS_0_V)<<(DPORT_APP_INTR_STATUS_0_S)) #define DPORT_APP_INTR_STATUS_0_V 0xFFFFFFFF #define DPORT_APP_INTR_STATUS_0_S 0 #define DPORT_APP_INTR_STATUS_1_REG (DR_REG_DPORT_BASE + 0x0FC) + /* DPORT_APP_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /* Description: */ + #define DPORT_APP_INTR_STATUS_1 0xFFFFFFFF #define DPORT_APP_INTR_STATUS_1_M ((DPORT_APP_INTR_STATUS_1_V)<<(DPORT_APP_INTR_STATUS_1_S)) #define DPORT_APP_INTR_STATUS_1_V 0xFFFFFFFF #define DPORT_APP_INTR_STATUS_1_S 0 #define DPORT_APP_INTR_STATUS_2_REG (DR_REG_DPORT_BASE + 0x100) + /* DPORT_APP_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ /* Description: */ + #define DPORT_APP_INTR_STATUS_2 0xFFFFFFFF #define DPORT_APP_INTR_STATUS_2_M ((DPORT_APP_INTR_STATUS_2_V)<<(DPORT_APP_INTR_STATUS_2_S)) #define DPORT_APP_INTR_STATUS_2_V 0xFFFFFFFF #define DPORT_APP_INTR_STATUS_2_S 0 #define DPORT_PRO_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x104) + /* DPORT_PRO_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_MAC_INTR_MAP 0x0000001F #define DPORT_PRO_MAC_INTR_MAP_M ((DPORT_PRO_MAC_INTR_MAP_V)<<(DPORT_PRO_MAC_INTR_MAP_S)) #define DPORT_PRO_MAC_INTR_MAP_V 0x1F #define DPORT_PRO_MAC_INTR_MAP_S 0 #define DPORT_PRO_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x108) + /* DPORT_PRO_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_MAC_NMI_MAP 0x0000001F #define DPORT_PRO_MAC_NMI_MAP_M ((DPORT_PRO_MAC_NMI_MAP_V)<<(DPORT_PRO_MAC_NMI_MAP_S)) #define DPORT_PRO_MAC_NMI_MAP_V 0x1F #define DPORT_PRO_MAC_NMI_MAP_S 0 #define DPORT_PRO_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x10C) + /* DPORT_PRO_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_BB_INT_MAP 0x0000001F #define DPORT_PRO_BB_INT_MAP_M ((DPORT_PRO_BB_INT_MAP_V)<<(DPORT_PRO_BB_INT_MAP_S)) #define DPORT_PRO_BB_INT_MAP_V 0x1F #define DPORT_PRO_BB_INT_MAP_S 0 #define DPORT_PRO_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x110) + /* DPORT_PRO_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_BT_MAC_INT_MAP 0x0000001F #define DPORT_PRO_BT_MAC_INT_MAP_M ((DPORT_PRO_BT_MAC_INT_MAP_V)<<(DPORT_PRO_BT_MAC_INT_MAP_S)) #define DPORT_PRO_BT_MAC_INT_MAP_V 0x1F #define DPORT_PRO_BT_MAC_INT_MAP_S 0 #define DPORT_PRO_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x114) + /* DPORT_PRO_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_BT_BB_INT_MAP 0x0000001F #define DPORT_PRO_BT_BB_INT_MAP_M ((DPORT_PRO_BT_BB_INT_MAP_V)<<(DPORT_PRO_BT_BB_INT_MAP_S)) #define DPORT_PRO_BT_BB_INT_MAP_V 0x1F #define DPORT_PRO_BT_BB_INT_MAP_S 0 #define DPORT_PRO_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x118) + /* DPORT_PRO_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_BT_BB_NMI_MAP 0x0000001F #define DPORT_PRO_BT_BB_NMI_MAP_M ((DPORT_PRO_BT_BB_NMI_MAP_V)<<(DPORT_PRO_BT_BB_NMI_MAP_S)) #define DPORT_PRO_BT_BB_NMI_MAP_V 0x1F #define DPORT_PRO_BT_BB_NMI_MAP_S 0 #define DPORT_PRO_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x11C) + /* DPORT_PRO_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_RWBT_IRQ_MAP 0x0000001F #define DPORT_PRO_RWBT_IRQ_MAP_M ((DPORT_PRO_RWBT_IRQ_MAP_V)<<(DPORT_PRO_RWBT_IRQ_MAP_S)) #define DPORT_PRO_RWBT_IRQ_MAP_V 0x1F #define DPORT_PRO_RWBT_IRQ_MAP_S 0 #define DPORT_PRO_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x120) + /* DPORT_PRO_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_RWBLE_IRQ_MAP 0x0000001F #define DPORT_PRO_RWBLE_IRQ_MAP_M ((DPORT_PRO_RWBLE_IRQ_MAP_V)<<(DPORT_PRO_RWBLE_IRQ_MAP_S)) #define DPORT_PRO_RWBLE_IRQ_MAP_V 0x1F #define DPORT_PRO_RWBLE_IRQ_MAP_S 0 #define DPORT_PRO_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x124) + /* DPORT_PRO_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_RWBT_NMI_MAP 0x0000001F #define DPORT_PRO_RWBT_NMI_MAP_M ((DPORT_PRO_RWBT_NMI_MAP_V)<<(DPORT_PRO_RWBT_NMI_MAP_S)) #define DPORT_PRO_RWBT_NMI_MAP_V 0x1F #define DPORT_PRO_RWBT_NMI_MAP_S 0 #define DPORT_PRO_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x128) + /* DPORT_PRO_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_RWBLE_NMI_MAP 0x0000001F #define DPORT_PRO_RWBLE_NMI_MAP_M ((DPORT_PRO_RWBLE_NMI_MAP_V)<<(DPORT_PRO_RWBLE_NMI_MAP_S)) #define DPORT_PRO_RWBLE_NMI_MAP_V 0x1F #define DPORT_PRO_RWBLE_NMI_MAP_S 0 #define DPORT_PRO_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x12C) + /* DPORT_PRO_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_SLC0_INTR_MAP 0x0000001F #define DPORT_PRO_SLC0_INTR_MAP_M ((DPORT_PRO_SLC0_INTR_MAP_V)<<(DPORT_PRO_SLC0_INTR_MAP_S)) #define DPORT_PRO_SLC0_INTR_MAP_V 0x1F #define DPORT_PRO_SLC0_INTR_MAP_S 0 #define DPORT_PRO_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x130) + /* DPORT_PRO_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_SLC1_INTR_MAP 0x0000001F #define DPORT_PRO_SLC1_INTR_MAP_M ((DPORT_PRO_SLC1_INTR_MAP_V)<<(DPORT_PRO_SLC1_INTR_MAP_S)) #define DPORT_PRO_SLC1_INTR_MAP_V 0x1F #define DPORT_PRO_SLC1_INTR_MAP_S 0 #define DPORT_PRO_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x134) + /* DPORT_PRO_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_UHCI0_INTR_MAP 0x0000001F #define DPORT_PRO_UHCI0_INTR_MAP_M ((DPORT_PRO_UHCI0_INTR_MAP_V)<<(DPORT_PRO_UHCI0_INTR_MAP_S)) #define DPORT_PRO_UHCI0_INTR_MAP_V 0x1F #define DPORT_PRO_UHCI0_INTR_MAP_S 0 #define DPORT_PRO_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x138) + /* DPORT_PRO_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_UHCI1_INTR_MAP 0x0000001F #define DPORT_PRO_UHCI1_INTR_MAP_M ((DPORT_PRO_UHCI1_INTR_MAP_V)<<(DPORT_PRO_UHCI1_INTR_MAP_S)) #define DPORT_PRO_UHCI1_INTR_MAP_V 0x1F #define DPORT_PRO_UHCI1_INTR_MAP_S 0 #define DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x13C) + /* DPORT_PRO_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_TG_T0_LEVEL_INT_MAP 0x0000001F #define DPORT_PRO_TG_T0_LEVEL_INT_MAP_M ((DPORT_PRO_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T0_LEVEL_INT_MAP_S)) #define DPORT_PRO_TG_T0_LEVEL_INT_MAP_V 0x1F #define DPORT_PRO_TG_T0_LEVEL_INT_MAP_S 0 #define DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x140) + /* DPORT_PRO_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_TG_T1_LEVEL_INT_MAP 0x0000001F #define DPORT_PRO_TG_T1_LEVEL_INT_MAP_M ((DPORT_PRO_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T1_LEVEL_INT_MAP_S)) #define DPORT_PRO_TG_T1_LEVEL_INT_MAP_V 0x1F #define DPORT_PRO_TG_T1_LEVEL_INT_MAP_S 0 #define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x144) + /* DPORT_PRO_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_TG_WDT_LEVEL_INT_MAP 0x0000001F #define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_M ((DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S)) #define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V 0x1F #define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S 0 #define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x148) + /* DPORT_PRO_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_TG_LACT_LEVEL_INT_MAP 0x0000001F #define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_M ((DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S)) #define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V 0x1F #define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S 0 #define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x14C) + /* DPORT_PRO_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_TG1_T0_LEVEL_INT_MAP 0x0000001F #define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S)) #define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V 0x1F #define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S 0 #define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x150) + /* DPORT_PRO_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_TG1_T1_LEVEL_INT_MAP 0x0000001F #define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S)) #define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V 0x1F #define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S 0 #define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x154) + /* DPORT_PRO_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP 0x0000001F #define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S)) #define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V 0x1F #define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S 0 #define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x158) + /* DPORT_PRO_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP 0x0000001F #define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_M ((DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S)) #define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V 0x1F #define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S 0 #define DPORT_PRO_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x15C) + /* DPORT_PRO_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP 0x0000001F #define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_M ((DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V)<<(DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S)) #define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_V 0x1F #define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S 0 #define DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x160) + /* DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F #define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_M ((DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S)) #define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F #define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 #define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x164) + /* DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP 0x0000001F #define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S)) #define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V 0x1F #define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S 0 #define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x168) + /* DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP 0x0000001F #define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S)) #define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V 0x1F #define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S 0 #define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x16C) + /* DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP 0x0000001F #define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S)) #define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V 0x1F #define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S 0 #define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x170) + /* DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP 0x0000001F #define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_M ((DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S)) #define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V 0x1F #define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S 0 #define DPORT_PRO_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x174) + /* DPORT_PRO_SPI_INTR_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_SPI_INTR_0_MAP 0x0000001F #define DPORT_PRO_SPI_INTR_0_MAP_M ((DPORT_PRO_SPI_INTR_0_MAP_V)<<(DPORT_PRO_SPI_INTR_0_MAP_S)) #define DPORT_PRO_SPI_INTR_0_MAP_V 0x1F #define DPORT_PRO_SPI_INTR_0_MAP_S 0 #define DPORT_PRO_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x178) + /* DPORT_PRO_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_SPI_INTR_1_MAP 0x0000001F #define DPORT_PRO_SPI_INTR_1_MAP_M ((DPORT_PRO_SPI_INTR_1_MAP_V)<<(DPORT_PRO_SPI_INTR_1_MAP_S)) #define DPORT_PRO_SPI_INTR_1_MAP_V 0x1F #define DPORT_PRO_SPI_INTR_1_MAP_S 0 #define DPORT_PRO_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x17C) + /* DPORT_PRO_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_SPI_INTR_2_MAP 0x0000001F #define DPORT_PRO_SPI_INTR_2_MAP_M ((DPORT_PRO_SPI_INTR_2_MAP_V)<<(DPORT_PRO_SPI_INTR_2_MAP_S)) #define DPORT_PRO_SPI_INTR_2_MAP_V 0x1F #define DPORT_PRO_SPI_INTR_2_MAP_S 0 #define DPORT_PRO_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x180) + /* DPORT_PRO_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_SPI_INTR_3_MAP 0x0000001F #define DPORT_PRO_SPI_INTR_3_MAP_M ((DPORT_PRO_SPI_INTR_3_MAP_V)<<(DPORT_PRO_SPI_INTR_3_MAP_S)) #define DPORT_PRO_SPI_INTR_3_MAP_V 0x1F #define DPORT_PRO_SPI_INTR_3_MAP_S 0 #define DPORT_PRO_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x184) + /* DPORT_PRO_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_I2S0_INT_MAP 0x0000001F #define DPORT_PRO_I2S0_INT_MAP_M ((DPORT_PRO_I2S0_INT_MAP_V)<<(DPORT_PRO_I2S0_INT_MAP_S)) #define DPORT_PRO_I2S0_INT_MAP_V 0x1F #define DPORT_PRO_I2S0_INT_MAP_S 0 #define DPORT_PRO_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x188) + /* DPORT_PRO_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_I2S1_INT_MAP 0x0000001F #define DPORT_PRO_I2S1_INT_MAP_M ((DPORT_PRO_I2S1_INT_MAP_V)<<(DPORT_PRO_I2S1_INT_MAP_S)) #define DPORT_PRO_I2S1_INT_MAP_V 0x1F #define DPORT_PRO_I2S1_INT_MAP_S 0 #define DPORT_PRO_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x18C) + /* DPORT_PRO_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_UART_INTR_MAP 0x0000001F #define DPORT_PRO_UART_INTR_MAP_M ((DPORT_PRO_UART_INTR_MAP_V)<<(DPORT_PRO_UART_INTR_MAP_S)) #define DPORT_PRO_UART_INTR_MAP_V 0x1F #define DPORT_PRO_UART_INTR_MAP_S 0 #define DPORT_PRO_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x190) + /* DPORT_PRO_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_UART1_INTR_MAP 0x0000001F #define DPORT_PRO_UART1_INTR_MAP_M ((DPORT_PRO_UART1_INTR_MAP_V)<<(DPORT_PRO_UART1_INTR_MAP_S)) #define DPORT_PRO_UART1_INTR_MAP_V 0x1F #define DPORT_PRO_UART1_INTR_MAP_S 0 #define DPORT_PRO_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x194) + /* DPORT_PRO_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_UART2_INTR_MAP 0x0000001F #define DPORT_PRO_UART2_INTR_MAP_M ((DPORT_PRO_UART2_INTR_MAP_V)<<(DPORT_PRO_UART2_INTR_MAP_S)) #define DPORT_PRO_UART2_INTR_MAP_V 0x1F #define DPORT_PRO_UART2_INTR_MAP_S 0 #define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x198) + /* DPORT_PRO_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP 0x0000001F #define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_M ((DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V)<<(DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S)) #define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_V 0x1F #define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S 0 #define DPORT_PRO_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x19C) + /* DPORT_PRO_EMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_EMAC_INT_MAP 0x0000001F #define DPORT_PRO_EMAC_INT_MAP_M ((DPORT_PRO_EMAC_INT_MAP_V)<<(DPORT_PRO_EMAC_INT_MAP_S)) #define DPORT_PRO_EMAC_INT_MAP_V 0x1F #define DPORT_PRO_EMAC_INT_MAP_S 0 #define DPORT_PRO_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A0) + /* DPORT_PRO_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_PWM0_INTR_MAP 0x0000001F #define DPORT_PRO_PWM0_INTR_MAP_M ((DPORT_PRO_PWM0_INTR_MAP_V)<<(DPORT_PRO_PWM0_INTR_MAP_S)) #define DPORT_PRO_PWM0_INTR_MAP_V 0x1F #define DPORT_PRO_PWM0_INTR_MAP_S 0 #define DPORT_PRO_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A4) + /* DPORT_PRO_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_PWM1_INTR_MAP 0x0000001F #define DPORT_PRO_PWM1_INTR_MAP_M ((DPORT_PRO_PWM1_INTR_MAP_V)<<(DPORT_PRO_PWM1_INTR_MAP_S)) #define DPORT_PRO_PWM1_INTR_MAP_V 0x1F #define DPORT_PRO_PWM1_INTR_MAP_S 0 #define DPORT_PRO_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A8) + /* DPORT_PRO_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_PWM2_INTR_MAP 0x0000001F #define DPORT_PRO_PWM2_INTR_MAP_M ((DPORT_PRO_PWM2_INTR_MAP_V)<<(DPORT_PRO_PWM2_INTR_MAP_S)) #define DPORT_PRO_PWM2_INTR_MAP_V 0x1F #define DPORT_PRO_PWM2_INTR_MAP_S 0 #define DPORT_PRO_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1AC) + /* DPORT_PRO_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_PWM3_INTR_MAP 0x0000001F #define DPORT_PRO_PWM3_INTR_MAP_M ((DPORT_PRO_PWM3_INTR_MAP_V)<<(DPORT_PRO_PWM3_INTR_MAP_S)) #define DPORT_PRO_PWM3_INTR_MAP_V 0x1F #define DPORT_PRO_PWM3_INTR_MAP_S 0 #define DPORT_PRO_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B0) + /* DPORT_PRO_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_LEDC_INT_MAP 0x0000001F #define DPORT_PRO_LEDC_INT_MAP_M ((DPORT_PRO_LEDC_INT_MAP_V)<<(DPORT_PRO_LEDC_INT_MAP_S)) #define DPORT_PRO_LEDC_INT_MAP_V 0x1F #define DPORT_PRO_LEDC_INT_MAP_S 0 #define DPORT_PRO_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B4) + /* DPORT_PRO_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_EFUSE_INT_MAP 0x0000001F #define DPORT_PRO_EFUSE_INT_MAP_M ((DPORT_PRO_EFUSE_INT_MAP_V)<<(DPORT_PRO_EFUSE_INT_MAP_S)) #define DPORT_PRO_EFUSE_INT_MAP_V 0x1F #define DPORT_PRO_EFUSE_INT_MAP_S 0 #define DPORT_PRO_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B8) + /* DPORT_PRO_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_CAN_INT_MAP 0x0000001F #define DPORT_PRO_CAN_INT_MAP_M ((DPORT_PRO_CAN_INT_MAP_V)<<(DPORT_PRO_CAN_INT_MAP_S)) #define DPORT_PRO_CAN_INT_MAP_V 0x1F #define DPORT_PRO_CAN_INT_MAP_S 0 #define DPORT_PRO_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1BC) + /* DPORT_PRO_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_RTC_CORE_INTR_MAP 0x0000001F #define DPORT_PRO_RTC_CORE_INTR_MAP_M ((DPORT_PRO_RTC_CORE_INTR_MAP_V)<<(DPORT_PRO_RTC_CORE_INTR_MAP_S)) #define DPORT_PRO_RTC_CORE_INTR_MAP_V 0x1F #define DPORT_PRO_RTC_CORE_INTR_MAP_S 0 #define DPORT_PRO_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C0) + /* DPORT_PRO_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_RMT_INTR_MAP 0x0000001F #define DPORT_PRO_RMT_INTR_MAP_M ((DPORT_PRO_RMT_INTR_MAP_V)<<(DPORT_PRO_RMT_INTR_MAP_S)) #define DPORT_PRO_RMT_INTR_MAP_V 0x1F #define DPORT_PRO_RMT_INTR_MAP_S 0 #define DPORT_PRO_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C4) + /* DPORT_PRO_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_PCNT_INTR_MAP 0x0000001F #define DPORT_PRO_PCNT_INTR_MAP_M ((DPORT_PRO_PCNT_INTR_MAP_V)<<(DPORT_PRO_PCNT_INTR_MAP_S)) #define DPORT_PRO_PCNT_INTR_MAP_V 0x1F #define DPORT_PRO_PCNT_INTR_MAP_S 0 #define DPORT_PRO_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C8) + /* DPORT_PRO_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_I2C_EXT0_INTR_MAP 0x0000001F #define DPORT_PRO_I2C_EXT0_INTR_MAP_M ((DPORT_PRO_I2C_EXT0_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT0_INTR_MAP_S)) #define DPORT_PRO_I2C_EXT0_INTR_MAP_V 0x1F #define DPORT_PRO_I2C_EXT0_INTR_MAP_S 0 #define DPORT_PRO_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1CC) + /* DPORT_PRO_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_I2C_EXT1_INTR_MAP 0x0000001F #define DPORT_PRO_I2C_EXT1_INTR_MAP_M ((DPORT_PRO_I2C_EXT1_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT1_INTR_MAP_S)) #define DPORT_PRO_I2C_EXT1_INTR_MAP_V 0x1F #define DPORT_PRO_I2C_EXT1_INTR_MAP_S 0 #define DPORT_PRO_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1D0) + /* DPORT_PRO_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_RSA_INTR_MAP 0x0000001F #define DPORT_PRO_RSA_INTR_MAP_M ((DPORT_PRO_RSA_INTR_MAP_V)<<(DPORT_PRO_RSA_INTR_MAP_S)) #define DPORT_PRO_RSA_INTR_MAP_V 0x1F #define DPORT_PRO_RSA_INTR_MAP_S 0 #define DPORT_PRO_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D4) + /* DPORT_PRO_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_SPI1_DMA_INT_MAP 0x0000001F #define DPORT_PRO_SPI1_DMA_INT_MAP_M ((DPORT_PRO_SPI1_DMA_INT_MAP_V)<<(DPORT_PRO_SPI1_DMA_INT_MAP_S)) #define DPORT_PRO_SPI1_DMA_INT_MAP_V 0x1F #define DPORT_PRO_SPI1_DMA_INT_MAP_S 0 #define DPORT_PRO_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D8) + /* DPORT_PRO_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_SPI2_DMA_INT_MAP 0x0000001F #define DPORT_PRO_SPI2_DMA_INT_MAP_M ((DPORT_PRO_SPI2_DMA_INT_MAP_V)<<(DPORT_PRO_SPI2_DMA_INT_MAP_S)) #define DPORT_PRO_SPI2_DMA_INT_MAP_V 0x1F #define DPORT_PRO_SPI2_DMA_INT_MAP_S 0 #define DPORT_PRO_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1DC) + /* DPORT_PRO_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_SPI3_DMA_INT_MAP 0x0000001F #define DPORT_PRO_SPI3_DMA_INT_MAP_M ((DPORT_PRO_SPI3_DMA_INT_MAP_V)<<(DPORT_PRO_SPI3_DMA_INT_MAP_S)) #define DPORT_PRO_SPI3_DMA_INT_MAP_V 0x1F #define DPORT_PRO_SPI3_DMA_INT_MAP_S 0 #define DPORT_PRO_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1E0) + /* DPORT_PRO_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_WDG_INT_MAP 0x0000001F #define DPORT_PRO_WDG_INT_MAP_M ((DPORT_PRO_WDG_INT_MAP_V)<<(DPORT_PRO_WDG_INT_MAP_S)) #define DPORT_PRO_WDG_INT_MAP_V 0x1F #define DPORT_PRO_WDG_INT_MAP_S 0 #define DPORT_PRO_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x1E4) + /* DPORT_PRO_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_TIMER_INT1_MAP 0x0000001F #define DPORT_PRO_TIMER_INT1_MAP_M ((DPORT_PRO_TIMER_INT1_MAP_V)<<(DPORT_PRO_TIMER_INT1_MAP_S)) #define DPORT_PRO_TIMER_INT1_MAP_V 0x1F #define DPORT_PRO_TIMER_INT1_MAP_S 0 #define DPORT_PRO_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x1E8) + /* DPORT_PRO_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_TIMER_INT2_MAP 0x0000001F #define DPORT_PRO_TIMER_INT2_MAP_M ((DPORT_PRO_TIMER_INT2_MAP_V)<<(DPORT_PRO_TIMER_INT2_MAP_S)) #define DPORT_PRO_TIMER_INT2_MAP_V 0x1F #define DPORT_PRO_TIMER_INT2_MAP_S 0 #define DPORT_PRO_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1EC) + /* DPORT_PRO_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_TG_T0_EDGE_INT_MAP 0x0000001F #define DPORT_PRO_TG_T0_EDGE_INT_MAP_M ((DPORT_PRO_TG_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T0_EDGE_INT_MAP_S)) #define DPORT_PRO_TG_T0_EDGE_INT_MAP_V 0x1F #define DPORT_PRO_TG_T0_EDGE_INT_MAP_S 0 #define DPORT_PRO_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F0) + /* DPORT_PRO_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_TG_T1_EDGE_INT_MAP 0x0000001F #define DPORT_PRO_TG_T1_EDGE_INT_MAP_M ((DPORT_PRO_TG_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T1_EDGE_INT_MAP_S)) #define DPORT_PRO_TG_T1_EDGE_INT_MAP_V 0x1F #define DPORT_PRO_TG_T1_EDGE_INT_MAP_S 0 #define DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F4) + /* DPORT_PRO_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_TG_WDT_EDGE_INT_MAP 0x0000001F #define DPORT_PRO_TG_WDT_EDGE_INT_MAP_M ((DPORT_PRO_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_WDT_EDGE_INT_MAP_S)) #define DPORT_PRO_TG_WDT_EDGE_INT_MAP_V 0x1F #define DPORT_PRO_TG_WDT_EDGE_INT_MAP_S 0 #define DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F8) + /* DPORT_PRO_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_TG_LACT_EDGE_INT_MAP 0x0000001F #define DPORT_PRO_TG_LACT_EDGE_INT_MAP_M ((DPORT_PRO_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_LACT_EDGE_INT_MAP_S)) #define DPORT_PRO_TG_LACT_EDGE_INT_MAP_V 0x1F #define DPORT_PRO_TG_LACT_EDGE_INT_MAP_S 0 #define DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1FC) + /* DPORT_PRO_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_TG1_T0_EDGE_INT_MAP 0x0000001F #define DPORT_PRO_TG1_T0_EDGE_INT_MAP_M ((DPORT_PRO_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T0_EDGE_INT_MAP_S)) #define DPORT_PRO_TG1_T0_EDGE_INT_MAP_V 0x1F #define DPORT_PRO_TG1_T0_EDGE_INT_MAP_S 0 #define DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x200) + /* DPORT_PRO_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_TG1_T1_EDGE_INT_MAP 0x0000001F #define DPORT_PRO_TG1_T1_EDGE_INT_MAP_M ((DPORT_PRO_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T1_EDGE_INT_MAP_S)) #define DPORT_PRO_TG1_T1_EDGE_INT_MAP_V 0x1F #define DPORT_PRO_TG1_T1_EDGE_INT_MAP_S 0 #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x204) + /* DPORT_PRO_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP 0x0000001F #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_M ((DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S)) #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V 0x1F #define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S 0 #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x208) + /* DPORT_PRO_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP 0x0000001F #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_M ((DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S)) #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V 0x1F #define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S 0 #define DPORT_PRO_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x20C) + /* DPORT_PRO_MMU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_MMU_IA_INT_MAP 0x0000001F #define DPORT_PRO_MMU_IA_INT_MAP_M ((DPORT_PRO_MMU_IA_INT_MAP_V)<<(DPORT_PRO_MMU_IA_INT_MAP_S)) #define DPORT_PRO_MMU_IA_INT_MAP_V 0x1F #define DPORT_PRO_MMU_IA_INT_MAP_S 0 #define DPORT_PRO_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x210) + /* DPORT_PRO_MPU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_MPU_IA_INT_MAP 0x0000001F #define DPORT_PRO_MPU_IA_INT_MAP_M ((DPORT_PRO_MPU_IA_INT_MAP_V)<<(DPORT_PRO_MPU_IA_INT_MAP_S)) #define DPORT_PRO_MPU_IA_INT_MAP_V 0x1F #define DPORT_PRO_MPU_IA_INT_MAP_S 0 #define DPORT_PRO_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x214) + /* DPORT_PRO_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_PRO_CACHE_IA_INT_MAP 0x0000001F #define DPORT_PRO_CACHE_IA_INT_MAP_M ((DPORT_PRO_CACHE_IA_INT_MAP_V)<<(DPORT_PRO_CACHE_IA_INT_MAP_S)) #define DPORT_PRO_CACHE_IA_INT_MAP_V 0x1F #define DPORT_PRO_CACHE_IA_INT_MAP_S 0 #define DPORT_APP_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x218) + /* DPORT_APP_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_MAC_INTR_MAP 0x0000001F #define DPORT_APP_MAC_INTR_MAP_M ((DPORT_APP_MAC_INTR_MAP_V)<<(DPORT_APP_MAC_INTR_MAP_S)) #define DPORT_APP_MAC_INTR_MAP_V 0x1F #define DPORT_APP_MAC_INTR_MAP_S 0 #define DPORT_APP_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x21C) + /* DPORT_APP_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_MAC_NMI_MAP 0x0000001F #define DPORT_APP_MAC_NMI_MAP_M ((DPORT_APP_MAC_NMI_MAP_V)<<(DPORT_APP_MAC_NMI_MAP_S)) #define DPORT_APP_MAC_NMI_MAP_V 0x1F #define DPORT_APP_MAC_NMI_MAP_S 0 #define DPORT_APP_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x220) + /* DPORT_APP_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_BB_INT_MAP 0x0000001F #define DPORT_APP_BB_INT_MAP_M ((DPORT_APP_BB_INT_MAP_V)<<(DPORT_APP_BB_INT_MAP_S)) #define DPORT_APP_BB_INT_MAP_V 0x1F #define DPORT_APP_BB_INT_MAP_S 0 #define DPORT_APP_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x224) + /* DPORT_APP_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_BT_MAC_INT_MAP 0x0000001F #define DPORT_APP_BT_MAC_INT_MAP_M ((DPORT_APP_BT_MAC_INT_MAP_V)<<(DPORT_APP_BT_MAC_INT_MAP_S)) #define DPORT_APP_BT_MAC_INT_MAP_V 0x1F #define DPORT_APP_BT_MAC_INT_MAP_S 0 #define DPORT_APP_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x228) + /* DPORT_APP_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_BT_BB_INT_MAP 0x0000001F #define DPORT_APP_BT_BB_INT_MAP_M ((DPORT_APP_BT_BB_INT_MAP_V)<<(DPORT_APP_BT_BB_INT_MAP_S)) #define DPORT_APP_BT_BB_INT_MAP_V 0x1F #define DPORT_APP_BT_BB_INT_MAP_S 0 #define DPORT_APP_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x22C) + /* DPORT_APP_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_BT_BB_NMI_MAP 0x0000001F #define DPORT_APP_BT_BB_NMI_MAP_M ((DPORT_APP_BT_BB_NMI_MAP_V)<<(DPORT_APP_BT_BB_NMI_MAP_S)) #define DPORT_APP_BT_BB_NMI_MAP_V 0x1F #define DPORT_APP_BT_BB_NMI_MAP_S 0 #define DPORT_APP_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x230) + /* DPORT_APP_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_RWBT_IRQ_MAP 0x0000001F #define DPORT_APP_RWBT_IRQ_MAP_M ((DPORT_APP_RWBT_IRQ_MAP_V)<<(DPORT_APP_RWBT_IRQ_MAP_S)) #define DPORT_APP_RWBT_IRQ_MAP_V 0x1F #define DPORT_APP_RWBT_IRQ_MAP_S 0 #define DPORT_APP_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x234) + /* DPORT_APP_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_RWBLE_IRQ_MAP 0x0000001F #define DPORT_APP_RWBLE_IRQ_MAP_M ((DPORT_APP_RWBLE_IRQ_MAP_V)<<(DPORT_APP_RWBLE_IRQ_MAP_S)) #define DPORT_APP_RWBLE_IRQ_MAP_V 0x1F #define DPORT_APP_RWBLE_IRQ_MAP_S 0 #define DPORT_APP_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x238) + /* DPORT_APP_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_RWBT_NMI_MAP 0x0000001F #define DPORT_APP_RWBT_NMI_MAP_M ((DPORT_APP_RWBT_NMI_MAP_V)<<(DPORT_APP_RWBT_NMI_MAP_S)) #define DPORT_APP_RWBT_NMI_MAP_V 0x1F #define DPORT_APP_RWBT_NMI_MAP_S 0 #define DPORT_APP_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x23C) + /* DPORT_APP_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_RWBLE_NMI_MAP 0x0000001F #define DPORT_APP_RWBLE_NMI_MAP_M ((DPORT_APP_RWBLE_NMI_MAP_V)<<(DPORT_APP_RWBLE_NMI_MAP_S)) #define DPORT_APP_RWBLE_NMI_MAP_V 0x1F #define DPORT_APP_RWBLE_NMI_MAP_S 0 #define DPORT_APP_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x240) + /* DPORT_APP_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_SLC0_INTR_MAP 0x0000001F #define DPORT_APP_SLC0_INTR_MAP_M ((DPORT_APP_SLC0_INTR_MAP_V)<<(DPORT_APP_SLC0_INTR_MAP_S)) #define DPORT_APP_SLC0_INTR_MAP_V 0x1F #define DPORT_APP_SLC0_INTR_MAP_S 0 #define DPORT_APP_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x244) + /* DPORT_APP_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_SLC1_INTR_MAP 0x0000001F #define DPORT_APP_SLC1_INTR_MAP_M ((DPORT_APP_SLC1_INTR_MAP_V)<<(DPORT_APP_SLC1_INTR_MAP_S)) #define DPORT_APP_SLC1_INTR_MAP_V 0x1F #define DPORT_APP_SLC1_INTR_MAP_S 0 #define DPORT_APP_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x248) + /* DPORT_APP_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_UHCI0_INTR_MAP 0x0000001F #define DPORT_APP_UHCI0_INTR_MAP_M ((DPORT_APP_UHCI0_INTR_MAP_V)<<(DPORT_APP_UHCI0_INTR_MAP_S)) #define DPORT_APP_UHCI0_INTR_MAP_V 0x1F #define DPORT_APP_UHCI0_INTR_MAP_S 0 #define DPORT_APP_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x24C) + /* DPORT_APP_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_UHCI1_INTR_MAP 0x0000001F #define DPORT_APP_UHCI1_INTR_MAP_M ((DPORT_APP_UHCI1_INTR_MAP_V)<<(DPORT_APP_UHCI1_INTR_MAP_S)) #define DPORT_APP_UHCI1_INTR_MAP_V 0x1F #define DPORT_APP_UHCI1_INTR_MAP_S 0 #define DPORT_APP_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x250) + /* DPORT_APP_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_TG_T0_LEVEL_INT_MAP 0x0000001F #define DPORT_APP_TG_T0_LEVEL_INT_MAP_M ((DPORT_APP_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_T0_LEVEL_INT_MAP_S)) #define DPORT_APP_TG_T0_LEVEL_INT_MAP_V 0x1F #define DPORT_APP_TG_T0_LEVEL_INT_MAP_S 0 #define DPORT_APP_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x254) + /* DPORT_APP_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_TG_T1_LEVEL_INT_MAP 0x0000001F #define DPORT_APP_TG_T1_LEVEL_INT_MAP_M ((DPORT_APP_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_T1_LEVEL_INT_MAP_S)) #define DPORT_APP_TG_T1_LEVEL_INT_MAP_V 0x1F #define DPORT_APP_TG_T1_LEVEL_INT_MAP_S 0 #define DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x258) + /* DPORT_APP_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_TG_WDT_LEVEL_INT_MAP 0x0000001F #define DPORT_APP_TG_WDT_LEVEL_INT_MAP_M ((DPORT_APP_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_WDT_LEVEL_INT_MAP_S)) #define DPORT_APP_TG_WDT_LEVEL_INT_MAP_V 0x1F #define DPORT_APP_TG_WDT_LEVEL_INT_MAP_S 0 #define DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x25C) + /* DPORT_APP_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_TG_LACT_LEVEL_INT_MAP 0x0000001F #define DPORT_APP_TG_LACT_LEVEL_INT_MAP_M ((DPORT_APP_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG_LACT_LEVEL_INT_MAP_S)) #define DPORT_APP_TG_LACT_LEVEL_INT_MAP_V 0x1F #define DPORT_APP_TG_LACT_LEVEL_INT_MAP_S 0 #define DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x260) + /* DPORT_APP_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_TG1_T0_LEVEL_INT_MAP 0x0000001F #define DPORT_APP_TG1_T0_LEVEL_INT_MAP_M ((DPORT_APP_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_T0_LEVEL_INT_MAP_S)) #define DPORT_APP_TG1_T0_LEVEL_INT_MAP_V 0x1F #define DPORT_APP_TG1_T0_LEVEL_INT_MAP_S 0 #define DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x264) + /* DPORT_APP_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_TG1_T1_LEVEL_INT_MAP 0x0000001F #define DPORT_APP_TG1_T1_LEVEL_INT_MAP_M ((DPORT_APP_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_T1_LEVEL_INT_MAP_S)) #define DPORT_APP_TG1_T1_LEVEL_INT_MAP_V 0x1F #define DPORT_APP_TG1_T1_LEVEL_INT_MAP_S 0 #define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x268) + /* DPORT_APP_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_TG1_WDT_LEVEL_INT_MAP 0x0000001F #define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_M ((DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S)) #define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_V 0x1F #define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S 0 #define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x26C) + /* DPORT_APP_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_TG1_LACT_LEVEL_INT_MAP 0x0000001F #define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_M ((DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S)) #define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_V 0x1F #define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S 0 #define DPORT_APP_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x270) + /* DPORT_APP_GPIO_INTERRUPT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_GPIO_INTERRUPT_APP_MAP 0x0000001F #define DPORT_APP_GPIO_INTERRUPT_APP_MAP_M ((DPORT_APP_GPIO_INTERRUPT_APP_MAP_V)<<(DPORT_APP_GPIO_INTERRUPT_APP_MAP_S)) #define DPORT_APP_GPIO_INTERRUPT_APP_MAP_V 0x1F #define DPORT_APP_GPIO_INTERRUPT_APP_MAP_S 0 #define DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x274) + /* DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F #define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_M ((DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V)<<(DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S)) #define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_V 0x1F #define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S 0 #define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x278) + /* DPORT_APP_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP 0x0000001F #define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S)) #define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_V 0x1F #define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S 0 #define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x27C) + /* DPORT_APP_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP 0x0000001F #define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S)) #define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_V 0x1F #define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S 0 #define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x280) + /* DPORT_APP_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP 0x0000001F #define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S)) #define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_V 0x1F #define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S 0 #define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x284) + /* DPORT_APP_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP 0x0000001F #define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_M ((DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S)) #define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_V 0x1F #define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S 0 #define DPORT_APP_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x288) + /* DPORT_APP_SPI_INTR_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_SPI_INTR_0_MAP 0x0000001F #define DPORT_APP_SPI_INTR_0_MAP_M ((DPORT_APP_SPI_INTR_0_MAP_V)<<(DPORT_APP_SPI_INTR_0_MAP_S)) #define DPORT_APP_SPI_INTR_0_MAP_V 0x1F #define DPORT_APP_SPI_INTR_0_MAP_S 0 #define DPORT_APP_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x28C) + /* DPORT_APP_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_SPI_INTR_1_MAP 0x0000001F #define DPORT_APP_SPI_INTR_1_MAP_M ((DPORT_APP_SPI_INTR_1_MAP_V)<<(DPORT_APP_SPI_INTR_1_MAP_S)) #define DPORT_APP_SPI_INTR_1_MAP_V 0x1F #define DPORT_APP_SPI_INTR_1_MAP_S 0 #define DPORT_APP_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x290) + /* DPORT_APP_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_SPI_INTR_2_MAP 0x0000001F #define DPORT_APP_SPI_INTR_2_MAP_M ((DPORT_APP_SPI_INTR_2_MAP_V)<<(DPORT_APP_SPI_INTR_2_MAP_S)) #define DPORT_APP_SPI_INTR_2_MAP_V 0x1F #define DPORT_APP_SPI_INTR_2_MAP_S 0 #define DPORT_APP_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x294) + /* DPORT_APP_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_SPI_INTR_3_MAP 0x0000001F #define DPORT_APP_SPI_INTR_3_MAP_M ((DPORT_APP_SPI_INTR_3_MAP_V)<<(DPORT_APP_SPI_INTR_3_MAP_S)) #define DPORT_APP_SPI_INTR_3_MAP_V 0x1F #define DPORT_APP_SPI_INTR_3_MAP_S 0 #define DPORT_APP_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x298) + /* DPORT_APP_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_I2S0_INT_MAP 0x0000001F #define DPORT_APP_I2S0_INT_MAP_M ((DPORT_APP_I2S0_INT_MAP_V)<<(DPORT_APP_I2S0_INT_MAP_S)) #define DPORT_APP_I2S0_INT_MAP_V 0x1F #define DPORT_APP_I2S0_INT_MAP_S 0 #define DPORT_APP_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x29C) + /* DPORT_APP_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_I2S1_INT_MAP 0x0000001F #define DPORT_APP_I2S1_INT_MAP_M ((DPORT_APP_I2S1_INT_MAP_V)<<(DPORT_APP_I2S1_INT_MAP_S)) #define DPORT_APP_I2S1_INT_MAP_V 0x1F #define DPORT_APP_I2S1_INT_MAP_S 0 #define DPORT_APP_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A0) + /* DPORT_APP_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_UART_INTR_MAP 0x0000001F #define DPORT_APP_UART_INTR_MAP_M ((DPORT_APP_UART_INTR_MAP_V)<<(DPORT_APP_UART_INTR_MAP_S)) #define DPORT_APP_UART_INTR_MAP_V 0x1F #define DPORT_APP_UART_INTR_MAP_S 0 #define DPORT_APP_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A4) + /* DPORT_APP_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_UART1_INTR_MAP 0x0000001F #define DPORT_APP_UART1_INTR_MAP_M ((DPORT_APP_UART1_INTR_MAP_V)<<(DPORT_APP_UART1_INTR_MAP_S)) #define DPORT_APP_UART1_INTR_MAP_V 0x1F #define DPORT_APP_UART1_INTR_MAP_S 0 #define DPORT_APP_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A8) + /* DPORT_APP_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_UART2_INTR_MAP 0x0000001F #define DPORT_APP_UART2_INTR_MAP_M ((DPORT_APP_UART2_INTR_MAP_V)<<(DPORT_APP_UART2_INTR_MAP_S)) #define DPORT_APP_UART2_INTR_MAP_V 0x1F #define DPORT_APP_UART2_INTR_MAP_S 0 #define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x2AC) + /* DPORT_APP_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_SDIO_HOST_INTERRUPT_MAP 0x0000001F #define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_M ((DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V)<<(DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S)) #define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_V 0x1F #define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S 0 #define DPORT_APP_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2B0) + /* DPORT_APP_EMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_EMAC_INT_MAP 0x0000001F #define DPORT_APP_EMAC_INT_MAP_M ((DPORT_APP_EMAC_INT_MAP_V)<<(DPORT_APP_EMAC_INT_MAP_S)) #define DPORT_APP_EMAC_INT_MAP_V 0x1F #define DPORT_APP_EMAC_INT_MAP_S 0 #define DPORT_APP_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B4) + /* DPORT_APP_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_PWM0_INTR_MAP 0x0000001F #define DPORT_APP_PWM0_INTR_MAP_M ((DPORT_APP_PWM0_INTR_MAP_V)<<(DPORT_APP_PWM0_INTR_MAP_S)) #define DPORT_APP_PWM0_INTR_MAP_V 0x1F #define DPORT_APP_PWM0_INTR_MAP_S 0 #define DPORT_APP_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B8) + /* DPORT_APP_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_PWM1_INTR_MAP 0x0000001F #define DPORT_APP_PWM1_INTR_MAP_M ((DPORT_APP_PWM1_INTR_MAP_V)<<(DPORT_APP_PWM1_INTR_MAP_S)) #define DPORT_APP_PWM1_INTR_MAP_V 0x1F #define DPORT_APP_PWM1_INTR_MAP_S 0 #define DPORT_APP_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2BC) + /* DPORT_APP_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_PWM2_INTR_MAP 0x0000001F #define DPORT_APP_PWM2_INTR_MAP_M ((DPORT_APP_PWM2_INTR_MAP_V)<<(DPORT_APP_PWM2_INTR_MAP_S)) #define DPORT_APP_PWM2_INTR_MAP_V 0x1F #define DPORT_APP_PWM2_INTR_MAP_S 0 #define DPORT_APP_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2C0) + /* DPORT_APP_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_PWM3_INTR_MAP 0x0000001F #define DPORT_APP_PWM3_INTR_MAP_M ((DPORT_APP_PWM3_INTR_MAP_V)<<(DPORT_APP_PWM3_INTR_MAP_S)) #define DPORT_APP_PWM3_INTR_MAP_V 0x1F #define DPORT_APP_PWM3_INTR_MAP_S 0 #define DPORT_APP_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C4) + /* DPORT_APP_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_LEDC_INT_MAP 0x0000001F #define DPORT_APP_LEDC_INT_MAP_M ((DPORT_APP_LEDC_INT_MAP_V)<<(DPORT_APP_LEDC_INT_MAP_S)) #define DPORT_APP_LEDC_INT_MAP_V 0x1F #define DPORT_APP_LEDC_INT_MAP_S 0 #define DPORT_APP_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C8) + /* DPORT_APP_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_EFUSE_INT_MAP 0x0000001F #define DPORT_APP_EFUSE_INT_MAP_M ((DPORT_APP_EFUSE_INT_MAP_V)<<(DPORT_APP_EFUSE_INT_MAP_S)) #define DPORT_APP_EFUSE_INT_MAP_V 0x1F #define DPORT_APP_EFUSE_INT_MAP_S 0 #define DPORT_APP_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2CC) + /* DPORT_APP_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_CAN_INT_MAP 0x0000001F #define DPORT_APP_CAN_INT_MAP_M ((DPORT_APP_CAN_INT_MAP_V)<<(DPORT_APP_CAN_INT_MAP_S)) #define DPORT_APP_CAN_INT_MAP_V 0x1F #define DPORT_APP_CAN_INT_MAP_S 0 #define DPORT_APP_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D0) + /* DPORT_APP_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_RTC_CORE_INTR_MAP 0x0000001F #define DPORT_APP_RTC_CORE_INTR_MAP_M ((DPORT_APP_RTC_CORE_INTR_MAP_V)<<(DPORT_APP_RTC_CORE_INTR_MAP_S)) #define DPORT_APP_RTC_CORE_INTR_MAP_V 0x1F #define DPORT_APP_RTC_CORE_INTR_MAP_S 0 #define DPORT_APP_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D4) + /* DPORT_APP_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_RMT_INTR_MAP 0x0000001F #define DPORT_APP_RMT_INTR_MAP_M ((DPORT_APP_RMT_INTR_MAP_V)<<(DPORT_APP_RMT_INTR_MAP_S)) #define DPORT_APP_RMT_INTR_MAP_V 0x1F #define DPORT_APP_RMT_INTR_MAP_S 0 #define DPORT_APP_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D8) + /* DPORT_APP_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_PCNT_INTR_MAP 0x0000001F #define DPORT_APP_PCNT_INTR_MAP_M ((DPORT_APP_PCNT_INTR_MAP_V)<<(DPORT_APP_PCNT_INTR_MAP_S)) #define DPORT_APP_PCNT_INTR_MAP_V 0x1F #define DPORT_APP_PCNT_INTR_MAP_S 0 #define DPORT_APP_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2DC) + /* DPORT_APP_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_I2C_EXT0_INTR_MAP 0x0000001F #define DPORT_APP_I2C_EXT0_INTR_MAP_M ((DPORT_APP_I2C_EXT0_INTR_MAP_V)<<(DPORT_APP_I2C_EXT0_INTR_MAP_S)) #define DPORT_APP_I2C_EXT0_INTR_MAP_V 0x1F #define DPORT_APP_I2C_EXT0_INTR_MAP_S 0 #define DPORT_APP_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E0) + /* DPORT_APP_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_I2C_EXT1_INTR_MAP 0x0000001F #define DPORT_APP_I2C_EXT1_INTR_MAP_M ((DPORT_APP_I2C_EXT1_INTR_MAP_V)<<(DPORT_APP_I2C_EXT1_INTR_MAP_S)) #define DPORT_APP_I2C_EXT1_INTR_MAP_V 0x1F #define DPORT_APP_I2C_EXT1_INTR_MAP_S 0 #define DPORT_APP_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E4) + /* DPORT_APP_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_RSA_INTR_MAP 0x0000001F #define DPORT_APP_RSA_INTR_MAP_M ((DPORT_APP_RSA_INTR_MAP_V)<<(DPORT_APP_RSA_INTR_MAP_S)) #define DPORT_APP_RSA_INTR_MAP_V 0x1F #define DPORT_APP_RSA_INTR_MAP_S 0 #define DPORT_APP_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2E8) + /* DPORT_APP_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_SPI1_DMA_INT_MAP 0x0000001F #define DPORT_APP_SPI1_DMA_INT_MAP_M ((DPORT_APP_SPI1_DMA_INT_MAP_V)<<(DPORT_APP_SPI1_DMA_INT_MAP_S)) #define DPORT_APP_SPI1_DMA_INT_MAP_V 0x1F #define DPORT_APP_SPI1_DMA_INT_MAP_S 0 #define DPORT_APP_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2EC) + /* DPORT_APP_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_SPI2_DMA_INT_MAP 0x0000001F #define DPORT_APP_SPI2_DMA_INT_MAP_M ((DPORT_APP_SPI2_DMA_INT_MAP_V)<<(DPORT_APP_SPI2_DMA_INT_MAP_S)) #define DPORT_APP_SPI2_DMA_INT_MAP_V 0x1F #define DPORT_APP_SPI2_DMA_INT_MAP_S 0 #define DPORT_APP_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F0) + /* DPORT_APP_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_SPI3_DMA_INT_MAP 0x0000001F #define DPORT_APP_SPI3_DMA_INT_MAP_M ((DPORT_APP_SPI3_DMA_INT_MAP_V)<<(DPORT_APP_SPI3_DMA_INT_MAP_S)) #define DPORT_APP_SPI3_DMA_INT_MAP_V 0x1F #define DPORT_APP_SPI3_DMA_INT_MAP_S 0 #define DPORT_APP_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F4) + /* DPORT_APP_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_WDG_INT_MAP 0x0000001F #define DPORT_APP_WDG_INT_MAP_M ((DPORT_APP_WDG_INT_MAP_V)<<(DPORT_APP_WDG_INT_MAP_S)) #define DPORT_APP_WDG_INT_MAP_V 0x1F #define DPORT_APP_WDG_INT_MAP_S 0 #define DPORT_APP_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x2F8) + /* DPORT_APP_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_TIMER_INT1_MAP 0x0000001F #define DPORT_APP_TIMER_INT1_MAP_M ((DPORT_APP_TIMER_INT1_MAP_V)<<(DPORT_APP_TIMER_INT1_MAP_S)) #define DPORT_APP_TIMER_INT1_MAP_V 0x1F #define DPORT_APP_TIMER_INT1_MAP_S 0 #define DPORT_APP_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x2FC) + /* DPORT_APP_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_TIMER_INT2_MAP 0x0000001F #define DPORT_APP_TIMER_INT2_MAP_M ((DPORT_APP_TIMER_INT2_MAP_V)<<(DPORT_APP_TIMER_INT2_MAP_S)) #define DPORT_APP_TIMER_INT2_MAP_V 0x1F #define DPORT_APP_TIMER_INT2_MAP_S 0 #define DPORT_APP_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x300) + /* DPORT_APP_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_TG_T0_EDGE_INT_MAP 0x0000001F #define DPORT_APP_TG_T0_EDGE_INT_MAP_M ((DPORT_APP_TG_T0_EDGE_INT_MAP_V)<<(DPORT_APP_TG_T0_EDGE_INT_MAP_S)) #define DPORT_APP_TG_T0_EDGE_INT_MAP_V 0x1F #define DPORT_APP_TG_T0_EDGE_INT_MAP_S 0 #define DPORT_APP_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x304) + /* DPORT_APP_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_TG_T1_EDGE_INT_MAP 0x0000001F #define DPORT_APP_TG_T1_EDGE_INT_MAP_M ((DPORT_APP_TG_T1_EDGE_INT_MAP_V)<<(DPORT_APP_TG_T1_EDGE_INT_MAP_S)) #define DPORT_APP_TG_T1_EDGE_INT_MAP_V 0x1F #define DPORT_APP_TG_T1_EDGE_INT_MAP_S 0 #define DPORT_APP_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x308) + /* DPORT_APP_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_TG_WDT_EDGE_INT_MAP 0x0000001F #define DPORT_APP_TG_WDT_EDGE_INT_MAP_M ((DPORT_APP_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_APP_TG_WDT_EDGE_INT_MAP_S)) #define DPORT_APP_TG_WDT_EDGE_INT_MAP_V 0x1F #define DPORT_APP_TG_WDT_EDGE_INT_MAP_S 0 #define DPORT_APP_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x30C) + /* DPORT_APP_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_TG_LACT_EDGE_INT_MAP 0x0000001F #define DPORT_APP_TG_LACT_EDGE_INT_MAP_M ((DPORT_APP_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_APP_TG_LACT_EDGE_INT_MAP_S)) #define DPORT_APP_TG_LACT_EDGE_INT_MAP_V 0x1F #define DPORT_APP_TG_LACT_EDGE_INT_MAP_S 0 #define DPORT_APP_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x310) + /* DPORT_APP_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_TG1_T0_EDGE_INT_MAP 0x0000001F #define DPORT_APP_TG1_T0_EDGE_INT_MAP_M ((DPORT_APP_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_T0_EDGE_INT_MAP_S)) #define DPORT_APP_TG1_T0_EDGE_INT_MAP_V 0x1F #define DPORT_APP_TG1_T0_EDGE_INT_MAP_S 0 #define DPORT_APP_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x314) + /* DPORT_APP_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_TG1_T1_EDGE_INT_MAP 0x0000001F #define DPORT_APP_TG1_T1_EDGE_INT_MAP_M ((DPORT_APP_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_T1_EDGE_INT_MAP_S)) #define DPORT_APP_TG1_T1_EDGE_INT_MAP_V 0x1F #define DPORT_APP_TG1_T1_EDGE_INT_MAP_S 0 #define DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x318) + /* DPORT_APP_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_TG1_WDT_EDGE_INT_MAP 0x0000001F #define DPORT_APP_TG1_WDT_EDGE_INT_MAP_M ((DPORT_APP_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_WDT_EDGE_INT_MAP_S)) #define DPORT_APP_TG1_WDT_EDGE_INT_MAP_V 0x1F #define DPORT_APP_TG1_WDT_EDGE_INT_MAP_S 0 #define DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x31C) + /* DPORT_APP_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_TG1_LACT_EDGE_INT_MAP 0x0000001F #define DPORT_APP_TG1_LACT_EDGE_INT_MAP_M ((DPORT_APP_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_APP_TG1_LACT_EDGE_INT_MAP_S)) #define DPORT_APP_TG1_LACT_EDGE_INT_MAP_V 0x1F #define DPORT_APP_TG1_LACT_EDGE_INT_MAP_S 0 #define DPORT_APP_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x320) + /* DPORT_APP_MMU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_MMU_IA_INT_MAP 0x0000001F #define DPORT_APP_MMU_IA_INT_MAP_M ((DPORT_APP_MMU_IA_INT_MAP_V)<<(DPORT_APP_MMU_IA_INT_MAP_S)) #define DPORT_APP_MMU_IA_INT_MAP_V 0x1F #define DPORT_APP_MMU_IA_INT_MAP_S 0 #define DPORT_APP_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x324) + /* DPORT_APP_MPU_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_MPU_IA_INT_MAP 0x0000001F #define DPORT_APP_MPU_IA_INT_MAP_M ((DPORT_APP_MPU_IA_INT_MAP_V)<<(DPORT_APP_MPU_IA_INT_MAP_S)) #define DPORT_APP_MPU_IA_INT_MAP_V 0x1F #define DPORT_APP_MPU_IA_INT_MAP_S 0 #define DPORT_APP_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x328) + /* DPORT_APP_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ /* Description: */ + #define DPORT_APP_CACHE_IA_INT_MAP 0x0000001F #define DPORT_APP_CACHE_IA_INT_MAP_M ((DPORT_APP_CACHE_IA_INT_MAP_V)<<(DPORT_APP_CACHE_IA_INT_MAP_S)) #define DPORT_APP_CACHE_IA_INT_MAP_V 0x1F #define DPORT_APP_CACHE_IA_INT_MAP_S 0 #define DPORT_AHBLITE_MPU_TABLE_UART_REG (DR_REG_DPORT_BASE + 0x32C) + /* DPORT_UART_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_UART_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_UART_ACCESS_GRANT_CONFIG_M ((DPORT_UART_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART_ACCESS_GRANT_CONFIG_S)) #define DPORT_UART_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_UART_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_SPI1_REG (DR_REG_DPORT_BASE + 0x330) + /* DPORT_SPI1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_SPI1_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_SPI1_ACCESS_GRANT_CONFIG_M ((DPORT_SPI1_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI1_ACCESS_GRANT_CONFIG_S)) #define DPORT_SPI1_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_SPI1_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_SPI0_REG (DR_REG_DPORT_BASE + 0x334) + /* DPORT_SPI0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_SPI0_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_SPI0_ACCESS_GRANT_CONFIG_M ((DPORT_SPI0_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI0_ACCESS_GRANT_CONFIG_S)) #define DPORT_SPI0_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_SPI0_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_GPIO_REG (DR_REG_DPORT_BASE + 0x338) + /* DPORT_GPIO_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_GPIO_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_GPIO_ACCESS_GRANT_CONFIG_M ((DPORT_GPIO_ACCESS_GRANT_CONFIG_V)<<(DPORT_GPIO_ACCESS_GRANT_CONFIG_S)) #define DPORT_GPIO_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_GPIO_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_FE2_REG (DR_REG_DPORT_BASE + 0x33C) + /* DPORT_FE2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_FE2_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_FE2_ACCESS_GRANT_CONFIG_M ((DPORT_FE2_ACCESS_GRANT_CONFIG_V)<<(DPORT_FE2_ACCESS_GRANT_CONFIG_S)) #define DPORT_FE2_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_FE2_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_FE_REG (DR_REG_DPORT_BASE + 0x340) + /* DPORT_FE_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_FE_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_FE_ACCESS_GRANT_CONFIG_M ((DPORT_FE_ACCESS_GRANT_CONFIG_V)<<(DPORT_FE_ACCESS_GRANT_CONFIG_S)) #define DPORT_FE_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_FE_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_TIMER_REG (DR_REG_DPORT_BASE + 0x344) + /* DPORT_TIMER_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_TIMER_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_TIMER_ACCESS_GRANT_CONFIG_M ((DPORT_TIMER_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMER_ACCESS_GRANT_CONFIG_S)) #define DPORT_TIMER_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_TIMER_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_RTC_REG (DR_REG_DPORT_BASE + 0x348) + /* DPORT_RTC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_RTC_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_RTC_ACCESS_GRANT_CONFIG_M ((DPORT_RTC_ACCESS_GRANT_CONFIG_V)<<(DPORT_RTC_ACCESS_GRANT_CONFIG_S)) #define DPORT_RTC_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_RTC_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG (DR_REG_DPORT_BASE + 0x34C) + /* DPORT_IOMUX_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_IOMUX_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_IOMUX_ACCESS_GRANT_CONFIG_M ((DPORT_IOMUX_ACCESS_GRANT_CONFIG_V)<<(DPORT_IOMUX_ACCESS_GRANT_CONFIG_S)) #define DPORT_IOMUX_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_IOMUX_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_WDG_REG (DR_REG_DPORT_BASE + 0x350) + /* DPORT_WDG_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_WDG_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_WDG_ACCESS_GRANT_CONFIG_M ((DPORT_WDG_ACCESS_GRANT_CONFIG_V)<<(DPORT_WDG_ACCESS_GRANT_CONFIG_S)) #define DPORT_WDG_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_WDG_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_HINF_REG (DR_REG_DPORT_BASE + 0x354) + /* DPORT_HINF_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_HINF_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_HINF_ACCESS_GRANT_CONFIG_M ((DPORT_HINF_ACCESS_GRANT_CONFIG_V)<<(DPORT_HINF_ACCESS_GRANT_CONFIG_S)) #define DPORT_HINF_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_HINF_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_UHCI1_REG (DR_REG_DPORT_BASE + 0x358) + /* DPORT_UHCI1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_UHCI1_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_UHCI1_ACCESS_GRANT_CONFIG_M ((DPORT_UHCI1_ACCESS_GRANT_CONFIG_V)<<(DPORT_UHCI1_ACCESS_GRANT_CONFIG_S)) #define DPORT_UHCI1_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_UHCI1_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_MISC_REG (DR_REG_DPORT_BASE + 0x35C) + /* DPORT_MISC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_MISC_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_MISC_ACCESS_GRANT_CONFIG_M ((DPORT_MISC_ACCESS_GRANT_CONFIG_V)<<(DPORT_MISC_ACCESS_GRANT_CONFIG_S)) #define DPORT_MISC_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_MISC_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_I2C_REG (DR_REG_DPORT_BASE + 0x360) + /* DPORT_I2C_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_I2C_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_I2C_ACCESS_GRANT_CONFIG_M ((DPORT_I2C_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2C_ACCESS_GRANT_CONFIG_S)) #define DPORT_I2C_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_I2C_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_I2S0_REG (DR_REG_DPORT_BASE + 0x364) + /* DPORT_I2S0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_I2S0_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_I2S0_ACCESS_GRANT_CONFIG_M ((DPORT_I2S0_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2S0_ACCESS_GRANT_CONFIG_S)) #define DPORT_I2S0_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_I2S0_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_UART1_REG (DR_REG_DPORT_BASE + 0x368) + /* DPORT_UART1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_UART1_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_UART1_ACCESS_GRANT_CONFIG_M ((DPORT_UART1_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART1_ACCESS_GRANT_CONFIG_S)) #define DPORT_UART1_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_UART1_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_BT_REG (DR_REG_DPORT_BASE + 0x36C) + /* DPORT_BT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_BT_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_BT_ACCESS_GRANT_CONFIG_M ((DPORT_BT_ACCESS_GRANT_CONFIG_V)<<(DPORT_BT_ACCESS_GRANT_CONFIG_S)) #define DPORT_BT_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_BT_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_BT_BUFFER_REG (DR_REG_DPORT_BASE + 0x370) + /* DPORT_BTBUFFER_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_M ((DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V)<<(DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S)) #define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG (DR_REG_DPORT_BASE + 0x374) + /* DPORT_I2CEXT0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_M ((DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S)) #define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_UHCI0_REG (DR_REG_DPORT_BASE + 0x378) + /* DPORT_UHCI0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_UHCI0_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_UHCI0_ACCESS_GRANT_CONFIG_M ((DPORT_UHCI0_ACCESS_GRANT_CONFIG_V)<<(DPORT_UHCI0_ACCESS_GRANT_CONFIG_S)) #define DPORT_UHCI0_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_UHCI0_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG (DR_REG_DPORT_BASE + 0x37C) + /* DPORT_SLCHOST_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_SLCHOST_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_M ((DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V)<<(DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S)) #define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_RMT_REG (DR_REG_DPORT_BASE + 0x380) + /* DPORT_RMT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_RMT_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_RMT_ACCESS_GRANT_CONFIG_M ((DPORT_RMT_ACCESS_GRANT_CONFIG_V)<<(DPORT_RMT_ACCESS_GRANT_CONFIG_S)) #define DPORT_RMT_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_RMT_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_PCNT_REG (DR_REG_DPORT_BASE + 0x384) + /* DPORT_PCNT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_PCNT_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_PCNT_ACCESS_GRANT_CONFIG_M ((DPORT_PCNT_ACCESS_GRANT_CONFIG_V)<<(DPORT_PCNT_ACCESS_GRANT_CONFIG_S)) #define DPORT_PCNT_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_PCNT_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_SLC_REG (DR_REG_DPORT_BASE + 0x388) + /* DPORT_SLC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_SLC_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_SLC_ACCESS_GRANT_CONFIG_M ((DPORT_SLC_ACCESS_GRANT_CONFIG_V)<<(DPORT_SLC_ACCESS_GRANT_CONFIG_S)) #define DPORT_SLC_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_SLC_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_LEDC_REG (DR_REG_DPORT_BASE + 0x38C) + /* DPORT_LEDC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_LEDC_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_LEDC_ACCESS_GRANT_CONFIG_M ((DPORT_LEDC_ACCESS_GRANT_CONFIG_V)<<(DPORT_LEDC_ACCESS_GRANT_CONFIG_S)) #define DPORT_LEDC_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_LEDC_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_EFUSE_REG (DR_REG_DPORT_BASE + 0x390) + /* DPORT_EFUSE_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_EFUSE_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_EFUSE_ACCESS_GRANT_CONFIG_M ((DPORT_EFUSE_ACCESS_GRANT_CONFIG_V)<<(DPORT_EFUSE_ACCESS_GRANT_CONFIG_S)) #define DPORT_EFUSE_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_EFUSE_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG (DR_REG_DPORT_BASE + 0x394) + /* DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_M ((DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S)) #define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_BB_REG (DR_REG_DPORT_BASE + 0x398) + /* DPORT_BB_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_BB_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_BB_ACCESS_GRANT_CONFIG_M ((DPORT_BB_ACCESS_GRANT_CONFIG_V)<<(DPORT_BB_ACCESS_GRANT_CONFIG_S)) #define DPORT_BB_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_BB_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_PWM0_REG (DR_REG_DPORT_BASE + 0x39C) + /* DPORT_PWM0_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_PWM0_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_PWM0_ACCESS_GRANT_CONFIG_M ((DPORT_PWM0_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM0_ACCESS_GRANT_CONFIG_S)) #define DPORT_PWM0_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_PWM0_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG (DR_REG_DPORT_BASE + 0x3A0) + /* DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_M ((DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S)) #define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG (DR_REG_DPORT_BASE + 0x3A4) + /* DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_M ((DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V)<<(DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S)) #define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_SPI2_REG (DR_REG_DPORT_BASE + 0x3A8) + /* DPORT_SPI2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_SPI2_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_SPI2_ACCESS_GRANT_CONFIG_M ((DPORT_SPI2_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI2_ACCESS_GRANT_CONFIG_S)) #define DPORT_SPI2_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_SPI2_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_SPI3_REG (DR_REG_DPORT_BASE + 0x3AC) + /* DPORT_SPI3_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_SPI3_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_SPI3_ACCESS_GRANT_CONFIG_M ((DPORT_SPI3_ACCESS_GRANT_CONFIG_V)<<(DPORT_SPI3_ACCESS_GRANT_CONFIG_S)) #define DPORT_SPI3_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_SPI3_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG (DR_REG_DPORT_BASE + 0x3B0) + /* DPORT_APBCTRL_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_APBCTRL_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_M ((DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V)<<(DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S)) #define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG (DR_REG_DPORT_BASE + 0x3B4) + /* DPORT_I2CEXT1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_M ((DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S)) #define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG (DR_REG_DPORT_BASE + 0x3B8) + /* DPORT_SDIOHOST_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_M ((DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V)<<(DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S)) #define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_EMAC_REG (DR_REG_DPORT_BASE + 0x3BC) + /* DPORT_EMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_EMAC_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_EMAC_ACCESS_GRANT_CONFIG_M ((DPORT_EMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_EMAC_ACCESS_GRANT_CONFIG_S)) #define DPORT_EMAC_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_EMAC_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_CAN_REG (DR_REG_DPORT_BASE + 0x3C0) + /* DPORT_CAN_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_CAN_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_CAN_ACCESS_GRANT_CONFIG_M ((DPORT_CAN_ACCESS_GRANT_CONFIG_V)<<(DPORT_CAN_ACCESS_GRANT_CONFIG_S)) #define DPORT_CAN_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_CAN_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_PWM1_REG (DR_REG_DPORT_BASE + 0x3C4) + /* DPORT_PWM1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_PWM1_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_PWM1_ACCESS_GRANT_CONFIG_M ((DPORT_PWM1_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM1_ACCESS_GRANT_CONFIG_S)) #define DPORT_PWM1_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_PWM1_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_I2S1_REG (DR_REG_DPORT_BASE + 0x3C8) + /* DPORT_I2S1_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_I2S1_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_I2S1_ACCESS_GRANT_CONFIG_M ((DPORT_I2S1_ACCESS_GRANT_CONFIG_V)<<(DPORT_I2S1_ACCESS_GRANT_CONFIG_S)) #define DPORT_I2S1_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_I2S1_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_UART2_REG (DR_REG_DPORT_BASE + 0x3CC) + /* DPORT_UART2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_UART2_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_UART2_ACCESS_GRANT_CONFIG_M ((DPORT_UART2_ACCESS_GRANT_CONFIG_V)<<(DPORT_UART2_ACCESS_GRANT_CONFIG_S)) #define DPORT_UART2_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_UART2_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_PWM2_REG (DR_REG_DPORT_BASE + 0x3D0) + /* DPORT_PWM2_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_PWM2_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_PWM2_ACCESS_GRANT_CONFIG_M ((DPORT_PWM2_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM2_ACCESS_GRANT_CONFIG_S)) #define DPORT_PWM2_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_PWM2_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_PWM3_REG (DR_REG_DPORT_BASE + 0x3D4) + /* DPORT_PWM3_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_PWM3_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_PWM3_ACCESS_GRANT_CONFIG_M ((DPORT_PWM3_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWM3_ACCESS_GRANT_CONFIG_S)) #define DPORT_PWM3_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_PWM3_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_RWBT_REG (DR_REG_DPORT_BASE + 0x3D8) + /* DPORT_RWBT_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_RWBT_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_RWBT_ACCESS_GRANT_CONFIG_M ((DPORT_RWBT_ACCESS_GRANT_CONFIG_V)<<(DPORT_RWBT_ACCESS_GRANT_CONFIG_S)) #define DPORT_RWBT_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_RWBT_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_BTMAC_REG (DR_REG_DPORT_BASE + 0x3DC) + /* DPORT_BTMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_BTMAC_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_BTMAC_ACCESS_GRANT_CONFIG_M ((DPORT_BTMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_BTMAC_ACCESS_GRANT_CONFIG_S)) #define DPORT_BTMAC_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_BTMAC_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_WIFIMAC_REG (DR_REG_DPORT_BASE + 0x3E0) + /* DPORT_WIFIMAC_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_M ((DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V)<<(DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S)) #define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S 0 #define DPORT_AHBLITE_MPU_TABLE_PWR_REG (DR_REG_DPORT_BASE + 0x3E4) + /* DPORT_PWR_ACCESS_GRANT_CONFIG : R/W ;bitpos:[5:0] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_PWR_ACCESS_GRANT_CONFIG 0x0000003F #define DPORT_PWR_ACCESS_GRANT_CONFIG_M ((DPORT_PWR_ACCESS_GRANT_CONFIG_V)<<(DPORT_PWR_ACCESS_GRANT_CONFIG_S)) #define DPORT_PWR_ACCESS_GRANT_CONFIG_V 0x3F #define DPORT_PWR_ACCESS_GRANT_CONFIG_S 0 #define DPORT_MEM_ACCESS_DBUG0_REG (DR_REG_DPORT_BASE + 0x3E8) + /* DPORT_INTERNAL_SRAM_MMU_MULTI_HIT : RO ;bitpos:[29:26] ;default: 4'b0 ; */ /* Description: */ + #define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT 0x0000000F #define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_M ((DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V)<<(DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S)) #define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_V 0xF #define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S 26 + /* DPORT_INTERNAL_SRAM_IA : RO ;bitpos:[25:14] ;default: 12'b0 ; */ /* Description: */ + #define DPORT_INTERNAL_SRAM_IA 0x00000FFF #define DPORT_INTERNAL_SRAM_IA_M ((DPORT_INTERNAL_SRAM_IA_V)<<(DPORT_INTERNAL_SRAM_IA_S)) #define DPORT_INTERNAL_SRAM_IA_V 0xFFF #define DPORT_INTERNAL_SRAM_IA_S 14 + /* DPORT_INTERNAL_SRAM_MMU_AD : RO ;bitpos:[13:10] ;default: 4'b0 ; */ /* Description: */ + #define DPORT_INTERNAL_SRAM_MMU_AD 0x0000000F #define DPORT_INTERNAL_SRAM_MMU_AD_M ((DPORT_INTERNAL_SRAM_MMU_AD_V)<<(DPORT_INTERNAL_SRAM_MMU_AD_S)) #define DPORT_INTERNAL_SRAM_MMU_AD_V 0xF #define DPORT_INTERNAL_SRAM_MMU_AD_S 10 + /* DPORT_SHARE_ROM_IA : RO ;bitpos:[9:6] ;default: 4'b0 ; */ /* Description: */ + #define DPORT_SHARE_ROM_IA 0x0000000F #define DPORT_SHARE_ROM_IA_M ((DPORT_SHARE_ROM_IA_V)<<(DPORT_SHARE_ROM_IA_S)) #define DPORT_SHARE_ROM_IA_V 0xF #define DPORT_SHARE_ROM_IA_S 6 + /* DPORT_SHARE_ROM_MPU_AD : RO ;bitpos:[5:4] ;default: 2'b0 ; */ /* Description: */ + #define DPORT_SHARE_ROM_MPU_AD 0x00000003 #define DPORT_SHARE_ROM_MPU_AD_M ((DPORT_SHARE_ROM_MPU_AD_V)<<(DPORT_SHARE_ROM_MPU_AD_S)) #define DPORT_SHARE_ROM_MPU_AD_V 0x3 #define DPORT_SHARE_ROM_MPU_AD_S 4 + /* DPORT_APP_ROM_IA : RO ;bitpos:[3] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_ROM_IA (BIT(3)) #define DPORT_APP_ROM_IA_M (BIT(3)) #define DPORT_APP_ROM_IA_V 0x1 #define DPORT_APP_ROM_IA_S 3 + /* DPORT_APP_ROM_MPU_AD : RO ;bitpos:[2] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_ROM_MPU_AD (BIT(2)) #define DPORT_APP_ROM_MPU_AD_M (BIT(2)) #define DPORT_APP_ROM_MPU_AD_V 0x1 #define DPORT_APP_ROM_MPU_AD_S 2 + /* DPORT_PRO_ROM_IA : RO ;bitpos:[1] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_ROM_IA (BIT(1)) #define DPORT_PRO_ROM_IA_M (BIT(1)) #define DPORT_PRO_ROM_IA_V 0x1 #define DPORT_PRO_ROM_IA_S 1 + /* DPORT_PRO_ROM_MPU_AD : RO ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_ROM_MPU_AD (BIT(0)) #define DPORT_PRO_ROM_MPU_AD_M (BIT(0)) #define DPORT_PRO_ROM_MPU_AD_V 0x1 #define DPORT_PRO_ROM_MPU_AD_S 0 #define DPORT_MEM_ACCESS_DBUG1_REG (DR_REG_DPORT_BASE + 0x3EC) + /* DPORT_AHBLITE_IA : RO ;bitpos:[10] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_AHBLITE_IA (BIT(10)) #define DPORT_AHBLITE_IA_M (BIT(10)) #define DPORT_AHBLITE_IA_V 0x1 #define DPORT_AHBLITE_IA_S 10 + /* DPORT_AHBLITE_ACCESS_DENY : RO ;bitpos:[9] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_AHBLITE_ACCESS_DENY (BIT(9)) #define DPORT_AHBLITE_ACCESS_DENY_M (BIT(9)) #define DPORT_AHBLITE_ACCESS_DENY_V 0x1 #define DPORT_AHBLITE_ACCESS_DENY_S 9 + /* DPORT_AHB_ACCESS_DENY : RO ;bitpos:[8] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_AHB_ACCESS_DENY (BIT(8)) #define DPORT_AHB_ACCESS_DENY_M (BIT(8)) #define DPORT_AHB_ACCESS_DENY_V 0x1 #define DPORT_AHB_ACCESS_DENY_S 8 + /* DPORT_PIDGEN_IA : RO ;bitpos:[7:6] ;default: 2'b0 ; */ /* Description: */ + #define DPORT_PIDGEN_IA 0x00000003 #define DPORT_PIDGEN_IA_M ((DPORT_PIDGEN_IA_V)<<(DPORT_PIDGEN_IA_S)) #define DPORT_PIDGEN_IA_V 0x3 #define DPORT_PIDGEN_IA_S 6 + /* DPORT_ARB_IA : RO ;bitpos:[5:4] ;default: 2'b0 ; */ /* Description: */ + #define DPORT_ARB_IA 0x00000003 #define DPORT_ARB_IA_M ((DPORT_ARB_IA_V)<<(DPORT_ARB_IA_S)) #define DPORT_ARB_IA_V 0x3 #define DPORT_ARB_IA_S 4 + /* DPORT_INTERNAL_SRAM_MMU_MISS : RO ;bitpos:[3:0] ;default: 4'b0 ; */ /* Description: */ + #define DPORT_INTERNAL_SRAM_MMU_MISS 0x0000000F #define DPORT_INTERNAL_SRAM_MMU_MISS_M ((DPORT_INTERNAL_SRAM_MMU_MISS_V)<<(DPORT_INTERNAL_SRAM_MMU_MISS_S)) #define DPORT_INTERNAL_SRAM_MMU_MISS_V 0xF #define DPORT_INTERNAL_SRAM_MMU_MISS_S 0 #define DPORT_PRO_DCACHE_DBUG0_REG (DR_REG_DPORT_BASE + 0x3F0) + /* DPORT_PRO_RX_END : RO ;bitpos:[23] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_RX_END (BIT(23)) #define DPORT_PRO_RX_END_M (BIT(23)) #define DPORT_PRO_RX_END_V 0x1 #define DPORT_PRO_RX_END_S 23 + /* DPORT_PRO_SLAVE_WDATA_V : RO ;bitpos:[22] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_SLAVE_WDATA_V (BIT(22)) #define DPORT_PRO_SLAVE_WDATA_V_M (BIT(22)) #define DPORT_PRO_SLAVE_WDATA_V_V 0x1 #define DPORT_PRO_SLAVE_WDATA_V_S 22 + /* DPORT_PRO_SLAVE_WR : RO ;bitpos:[21] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_SLAVE_WR (BIT(21)) #define DPORT_PRO_SLAVE_WR_M (BIT(21)) #define DPORT_PRO_SLAVE_WR_V 0x1 #define DPORT_PRO_SLAVE_WR_S 21 + /* DPORT_PRO_TX_END : RO ;bitpos:[20] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_TX_END (BIT(20)) #define DPORT_PRO_TX_END_M (BIT(20)) #define DPORT_PRO_TX_END_V 0x1 #define DPORT_PRO_TX_END_S 20 + /* DPORT_PRO_WR_BAK_TO_READ : RO ;bitpos:[19] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_WR_BAK_TO_READ (BIT(19)) #define DPORT_PRO_WR_BAK_TO_READ_M (BIT(19)) #define DPORT_PRO_WR_BAK_TO_READ_V 0x1 #define DPORT_PRO_WR_BAK_TO_READ_S 19 + /* DPORT_PRO_CACHE_STATE : RO ;bitpos:[18:7] ;default: 12'b0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_STATE 0x00000FFF #define DPORT_PRO_CACHE_STATE_M ((DPORT_PRO_CACHE_STATE_V)<<(DPORT_PRO_CACHE_STATE_S)) #define DPORT_PRO_CACHE_STATE_V 0xFFF #define DPORT_PRO_CACHE_STATE_S 7 + /* DPORT_PRO_CACHE_IA : RO ;bitpos:[6:1] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_IA 0x0000003F #define DPORT_PRO_CACHE_IA_M ((DPORT_PRO_CACHE_IA_V)<<(DPORT_PRO_CACHE_IA_S)) #define DPORT_PRO_CACHE_IA_V 0x3F #define DPORT_PRO_CACHE_IA_S 1 + /* DPORT_PRO_CACHE_MMU_IA : RO ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_MMU_IA (BIT(0)) #define DPORT_PRO_CACHE_MMU_IA_M (BIT(0)) #define DPORT_PRO_CACHE_MMU_IA_V 0x1 #define DPORT_PRO_CACHE_MMU_IA_S 0 #define DPORT_PRO_DCACHE_DBUG1_REG (DR_REG_DPORT_BASE + 0x3F4) + /* DPORT_PRO_CTAG_RAM_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ /* Description: */ + #define DPORT_PRO_CTAG_RAM_RDATA 0xFFFFFFFF #define DPORT_PRO_CTAG_RAM_RDATA_M ((DPORT_PRO_CTAG_RAM_RDATA_V)<<(DPORT_PRO_CTAG_RAM_RDATA_S)) #define DPORT_PRO_CTAG_RAM_RDATA_V 0xFFFFFFFF #define DPORT_PRO_CTAG_RAM_RDATA_S 0 #define DPORT_PRO_DCACHE_DBUG2_REG (DR_REG_DPORT_BASE + 0x3F8) + /* DPORT_PRO_CACHE_VADDR : RO ;bitpos:[26:0] ;default: 27'b0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_VADDR 0x07FFFFFF #define DPORT_PRO_CACHE_VADDR_M ((DPORT_PRO_CACHE_VADDR_V)<<(DPORT_PRO_CACHE_VADDR_S)) #define DPORT_PRO_CACHE_VADDR_V 0x7FFFFFF #define DPORT_PRO_CACHE_VADDR_S 0 #define DPORT_PRO_DCACHE_DBUG3_REG (DR_REG_DPORT_BASE + 0x3FC) + /* DPORT_PRO_CACHE_IRAM0_PID_ERROR : RO ;bitpos:[15] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_CACHE_IRAM0_PID_ERROR (BIT(15)) #define DPORT_PRO_CACHE_IRAM0_PID_ERROR_M (BIT(15)) #define DPORT_PRO_CACHE_IRAM0_PID_ERROR_V 0x1 #define DPORT_PRO_CACHE_IRAM0_PID_ERROR_S 15 + /* DPORT_PRO_CPU_DISABLED_CACHE_IA : RO ;bitpos:[14:9] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_PRO_CPU_DISABLED_CACHE_IA 0x0000003F #define DPORT_PRO_CPU_DISABLED_CACHE_IA_M ((DPORT_PRO_CPU_DISABLED_CACHE_IA_V)<<(DPORT_PRO_CPU_DISABLED_CACHE_IA_S)) #define DPORT_PRO_CPU_DISABLED_CACHE_IA_V 0x3F #define DPORT_PRO_CPU_DISABLED_CACHE_IA_S 9 + /* DPORT_PRO_MMU_RDATA : RO ;bitpos:[8:0] ;default: 9'h0 ; */ /* Description: */ + #define DPORT_PRO_MMU_RDATA 0x000001FF #define DPORT_PRO_MMU_RDATA_M ((DPORT_PRO_MMU_RDATA_V)<<(DPORT_PRO_MMU_RDATA_S)) #define DPORT_PRO_MMU_RDATA_V 0x1FF #define DPORT_PRO_MMU_RDATA_S 0 #define DPORT_PRO_DCACHE_DBUG4_REG (DR_REG_DPORT_BASE + 0x400) + /* DPORT_PRO_DRAM1ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ /* Description: */ + #define DPORT_PRO_DRAM1ADDR0_IA 0x000FFFFF #define DPORT_PRO_DRAM1ADDR0_IA_M ((DPORT_PRO_DRAM1ADDR0_IA_V)<<(DPORT_PRO_DRAM1ADDR0_IA_S)) #define DPORT_PRO_DRAM1ADDR0_IA_V 0xFFFFF #define DPORT_PRO_DRAM1ADDR0_IA_S 0 #define DPORT_PRO_DCACHE_DBUG5_REG (DR_REG_DPORT_BASE + 0x404) + /* DPORT_PRO_DROM0ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ /* Description: */ + #define DPORT_PRO_DROM0ADDR0_IA 0x000FFFFF #define DPORT_PRO_DROM0ADDR0_IA_M ((DPORT_PRO_DROM0ADDR0_IA_V)<<(DPORT_PRO_DROM0ADDR0_IA_S)) #define DPORT_PRO_DROM0ADDR0_IA_V 0xFFFFF #define DPORT_PRO_DROM0ADDR0_IA_S 0 #define DPORT_PRO_DCACHE_DBUG6_REG (DR_REG_DPORT_BASE + 0x408) + /* DPORT_PRO_IRAM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ /* Description: */ + #define DPORT_PRO_IRAM0ADDR_IA 0x000FFFFF #define DPORT_PRO_IRAM0ADDR_IA_M ((DPORT_PRO_IRAM0ADDR_IA_V)<<(DPORT_PRO_IRAM0ADDR_IA_S)) #define DPORT_PRO_IRAM0ADDR_IA_V 0xFFFFF #define DPORT_PRO_IRAM0ADDR_IA_S 0 #define DPORT_PRO_DCACHE_DBUG7_REG (DR_REG_DPORT_BASE + 0x40C) + /* DPORT_PRO_IRAM1ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ /* Description: */ + #define DPORT_PRO_IRAM1ADDR_IA 0x000FFFFF #define DPORT_PRO_IRAM1ADDR_IA_M ((DPORT_PRO_IRAM1ADDR_IA_V)<<(DPORT_PRO_IRAM1ADDR_IA_S)) #define DPORT_PRO_IRAM1ADDR_IA_V 0xFFFFF #define DPORT_PRO_IRAM1ADDR_IA_S 0 #define DPORT_PRO_DCACHE_DBUG8_REG (DR_REG_DPORT_BASE + 0x410) + /* DPORT_PRO_IROM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ /* Description: */ + #define DPORT_PRO_IROM0ADDR_IA 0x000FFFFF #define DPORT_PRO_IROM0ADDR_IA_M ((DPORT_PRO_IROM0ADDR_IA_V)<<(DPORT_PRO_IROM0ADDR_IA_S)) #define DPORT_PRO_IROM0ADDR_IA_V 0xFFFFF #define DPORT_PRO_IROM0ADDR_IA_S 0 #define DPORT_PRO_DCACHE_DBUG9_REG (DR_REG_DPORT_BASE + 0x414) + /* DPORT_PRO_OPSDRAMADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ /* Description: */ + #define DPORT_PRO_OPSDRAMADDR_IA 0x000FFFFF #define DPORT_PRO_OPSDRAMADDR_IA_M ((DPORT_PRO_OPSDRAMADDR_IA_V)<<(DPORT_PRO_OPSDRAMADDR_IA_S)) #define DPORT_PRO_OPSDRAMADDR_IA_V 0xFFFFF #define DPORT_PRO_OPSDRAMADDR_IA_S 0 #define DPORT_APP_DCACHE_DBUG0_REG (DR_REG_DPORT_BASE + 0x418) + /* DPORT_APP_RX_END : RO ;bitpos:[23] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_RX_END (BIT(23)) #define DPORT_APP_RX_END_M (BIT(23)) #define DPORT_APP_RX_END_V 0x1 #define DPORT_APP_RX_END_S 23 + /* DPORT_APP_SLAVE_WDATA_V : RO ;bitpos:[22] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_SLAVE_WDATA_V (BIT(22)) #define DPORT_APP_SLAVE_WDATA_V_M (BIT(22)) #define DPORT_APP_SLAVE_WDATA_V_V 0x1 #define DPORT_APP_SLAVE_WDATA_V_S 22 + /* DPORT_APP_SLAVE_WR : RO ;bitpos:[21] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_SLAVE_WR (BIT(21)) #define DPORT_APP_SLAVE_WR_M (BIT(21)) #define DPORT_APP_SLAVE_WR_V 0x1 #define DPORT_APP_SLAVE_WR_S 21 + /* DPORT_APP_TX_END : RO ;bitpos:[20] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_TX_END (BIT(20)) #define DPORT_APP_TX_END_M (BIT(20)) #define DPORT_APP_TX_END_V 0x1 #define DPORT_APP_TX_END_S 20 + /* DPORT_APP_WR_BAK_TO_READ : RO ;bitpos:[19] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_WR_BAK_TO_READ (BIT(19)) #define DPORT_APP_WR_BAK_TO_READ_M (BIT(19)) #define DPORT_APP_WR_BAK_TO_READ_V 0x1 #define DPORT_APP_WR_BAK_TO_READ_S 19 + /* DPORT_APP_CACHE_STATE : RO ;bitpos:[18:7] ;default: 12'b0 ; */ /* Description: */ + #define DPORT_APP_CACHE_STATE 0x00000FFF #define DPORT_APP_CACHE_STATE_M ((DPORT_APP_CACHE_STATE_V)<<(DPORT_APP_CACHE_STATE_S)) #define DPORT_APP_CACHE_STATE_V 0xFFF #define DPORT_APP_CACHE_STATE_S 7 + /* DPORT_APP_CACHE_IA : RO ;bitpos:[6:1] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_APP_CACHE_IA 0x0000003F #define DPORT_APP_CACHE_IA_M ((DPORT_APP_CACHE_IA_V)<<(DPORT_APP_CACHE_IA_S)) #define DPORT_APP_CACHE_IA_V 0x3F #define DPORT_APP_CACHE_IA_S 1 + /* DPORT_APP_CACHE_MMU_IA : RO ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_CACHE_MMU_IA (BIT(0)) #define DPORT_APP_CACHE_MMU_IA_M (BIT(0)) #define DPORT_APP_CACHE_MMU_IA_V 0x1 #define DPORT_APP_CACHE_MMU_IA_S 0 #define DPORT_APP_DCACHE_DBUG1_REG (DR_REG_DPORT_BASE + 0x41C) + /* DPORT_APP_CTAG_RAM_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ /* Description: */ + #define DPORT_APP_CTAG_RAM_RDATA 0xFFFFFFFF #define DPORT_APP_CTAG_RAM_RDATA_M ((DPORT_APP_CTAG_RAM_RDATA_V)<<(DPORT_APP_CTAG_RAM_RDATA_S)) #define DPORT_APP_CTAG_RAM_RDATA_V 0xFFFFFFFF #define DPORT_APP_CTAG_RAM_RDATA_S 0 #define DPORT_APP_DCACHE_DBUG2_REG (DR_REG_DPORT_BASE + 0x420) + /* DPORT_APP_CACHE_VADDR : RO ;bitpos:[26:0] ;default: 27'b0 ; */ /* Description: */ + #define DPORT_APP_CACHE_VADDR 0x07FFFFFF #define DPORT_APP_CACHE_VADDR_M ((DPORT_APP_CACHE_VADDR_V)<<(DPORT_APP_CACHE_VADDR_S)) #define DPORT_APP_CACHE_VADDR_V 0x7FFFFFF #define DPORT_APP_CACHE_VADDR_S 0 #define DPORT_APP_DCACHE_DBUG3_REG (DR_REG_DPORT_BASE + 0x424) + /* DPORT_APP_CACHE_IRAM0_PID_ERROR : RO ;bitpos:[15] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_CACHE_IRAM0_PID_ERROR (BIT(15)) #define DPORT_APP_CACHE_IRAM0_PID_ERROR_M (BIT(15)) #define DPORT_APP_CACHE_IRAM0_PID_ERROR_V 0x1 #define DPORT_APP_CACHE_IRAM0_PID_ERROR_S 15 + /* DPORT_APP_CPU_DISABLED_CACHE_IA : RO ;bitpos:[14:9] ;default: 6'b0 ; */ /* Description: */ + #define DPORT_APP_CPU_DISABLED_CACHE_IA 0x0000003F #define DPORT_APP_CPU_DISABLED_CACHE_IA_M ((DPORT_APP_CPU_DISABLED_CACHE_IA_V)<<(DPORT_APP_CPU_DISABLED_CACHE_IA_S)) #define DPORT_APP_CPU_DISABLED_CACHE_IA_V 0x3F #define DPORT_APP_CPU_DISABLED_CACHE_IA_S 9 + /* DPORT_APP_MMU_RDATA : RO ;bitpos:[8:0] ;default: 9'h0 ; */ /* Description: */ + #define DPORT_APP_MMU_RDATA 0x000001FF #define DPORT_APP_MMU_RDATA_M ((DPORT_APP_MMU_RDATA_V)<<(DPORT_APP_MMU_RDATA_S)) #define DPORT_APP_MMU_RDATA_V 0x1FF #define DPORT_APP_MMU_RDATA_S 0 #define DPORT_APP_DCACHE_DBUG4_REG (DR_REG_DPORT_BASE + 0x428) + /* DPORT_APP_DRAM1ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ /* Description: */ + #define DPORT_APP_DRAM1ADDR0_IA 0x000FFFFF #define DPORT_APP_DRAM1ADDR0_IA_M ((DPORT_APP_DRAM1ADDR0_IA_V)<<(DPORT_APP_DRAM1ADDR0_IA_S)) #define DPORT_APP_DRAM1ADDR0_IA_V 0xFFFFF #define DPORT_APP_DRAM1ADDR0_IA_S 0 #define DPORT_APP_DCACHE_DBUG5_REG (DR_REG_DPORT_BASE + 0x42C) + /* DPORT_APP_DROM0ADDR0_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ /* Description: */ + #define DPORT_APP_DROM0ADDR0_IA 0x000FFFFF #define DPORT_APP_DROM0ADDR0_IA_M ((DPORT_APP_DROM0ADDR0_IA_V)<<(DPORT_APP_DROM0ADDR0_IA_S)) #define DPORT_APP_DROM0ADDR0_IA_V 0xFFFFF #define DPORT_APP_DROM0ADDR0_IA_S 0 #define DPORT_APP_DCACHE_DBUG6_REG (DR_REG_DPORT_BASE + 0x430) + /* DPORT_APP_IRAM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ /* Description: */ + #define DPORT_APP_IRAM0ADDR_IA 0x000FFFFF #define DPORT_APP_IRAM0ADDR_IA_M ((DPORT_APP_IRAM0ADDR_IA_V)<<(DPORT_APP_IRAM0ADDR_IA_S)) #define DPORT_APP_IRAM0ADDR_IA_V 0xFFFFF #define DPORT_APP_IRAM0ADDR_IA_S 0 #define DPORT_APP_DCACHE_DBUG7_REG (DR_REG_DPORT_BASE + 0x434) + /* DPORT_APP_IRAM1ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ /* Description: */ + #define DPORT_APP_IRAM1ADDR_IA 0x000FFFFF #define DPORT_APP_IRAM1ADDR_IA_M ((DPORT_APP_IRAM1ADDR_IA_V)<<(DPORT_APP_IRAM1ADDR_IA_S)) #define DPORT_APP_IRAM1ADDR_IA_V 0xFFFFF #define DPORT_APP_IRAM1ADDR_IA_S 0 #define DPORT_APP_DCACHE_DBUG8_REG (DR_REG_DPORT_BASE + 0x438) + /* DPORT_APP_IROM0ADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ /* Description: */ + #define DPORT_APP_IROM0ADDR_IA 0x000FFFFF #define DPORT_APP_IROM0ADDR_IA_M ((DPORT_APP_IROM0ADDR_IA_V)<<(DPORT_APP_IROM0ADDR_IA_S)) #define DPORT_APP_IROM0ADDR_IA_V 0xFFFFF #define DPORT_APP_IROM0ADDR_IA_S 0 #define DPORT_APP_DCACHE_DBUG9_REG (DR_REG_DPORT_BASE + 0x43C) + /* DPORT_APP_OPSDRAMADDR_IA : RO ;bitpos:[19:0] ;default: 20'b0 ; */ /* Description: */ + #define DPORT_APP_OPSDRAMADDR_IA 0x000FFFFF #define DPORT_APP_OPSDRAMADDR_IA_M ((DPORT_APP_OPSDRAMADDR_IA_V)<<(DPORT_APP_OPSDRAMADDR_IA_S)) #define DPORT_APP_OPSDRAMADDR_IA_V 0xFFFFF #define DPORT_APP_OPSDRAMADDR_IA_S 0 #define DPORT_PRO_CPU_RECORD_CTRL_REG (DR_REG_DPORT_BASE + 0x440) + /* DPORT_PRO_CPU_PDEBUG_ENABLE : R/W ;bitpos:[8] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_PRO_CPU_PDEBUG_ENABLE (BIT(8)) #define DPORT_PRO_CPU_PDEBUG_ENABLE_M (BIT(8)) #define DPORT_PRO_CPU_PDEBUG_ENABLE_V 0x1 #define DPORT_PRO_CPU_PDEBUG_ENABLE_S 8 + /* DPORT_PRO_CPU_RECORD_DISABLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_CPU_RECORD_DISABLE (BIT(4)) #define DPORT_PRO_CPU_RECORD_DISABLE_M (BIT(4)) #define DPORT_PRO_CPU_RECORD_DISABLE_V 0x1 #define DPORT_PRO_CPU_RECORD_DISABLE_S 4 + /* DPORT_PRO_CPU_RECORD_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_CPU_RECORD_ENABLE (BIT(0)) #define DPORT_PRO_CPU_RECORD_ENABLE_M (BIT(0)) #define DPORT_PRO_CPU_RECORD_ENABLE_V 0x1 #define DPORT_PRO_CPU_RECORD_ENABLE_S 0 #define DPORT_PRO_CPU_RECORD_STATUS_REG (DR_REG_DPORT_BASE + 0x444) + /* DPORT_PRO_CPU_RECORDING : RO ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PRO_CPU_RECORDING (BIT(0)) #define DPORT_PRO_CPU_RECORDING_M (BIT(0)) #define DPORT_PRO_CPU_RECORDING_V 0x1 #define DPORT_PRO_CPU_RECORDING_S 0 #define DPORT_PRO_CPU_RECORD_PID_REG (DR_REG_DPORT_BASE + 0x448) + /* DPORT_RECORD_PRO_PID : RO ;bitpos:[2:0] ;default: 3'd0 ; */ /* Description: */ + #define DPORT_RECORD_PRO_PID 0x00000007 #define DPORT_RECORD_PRO_PID_M ((DPORT_RECORD_PRO_PID_V)<<(DPORT_RECORD_PRO_PID_S)) #define DPORT_RECORD_PRO_PID_V 0x7 #define DPORT_RECORD_PRO_PID_S 0 #define DPORT_PRO_CPU_RECORD_PDEBUGINST_REG (DR_REG_DPORT_BASE + 0x44C) + /* DPORT_RECORD_PRO_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */ /* Description: */ + #define DPORT_RECORD_PRO_PDEBUGINST 0xFFFFFFFF #define DPORT_RECORD_PRO_PDEBUGINST_M ((DPORT_RECORD_PRO_PDEBUGINST_V)<<(DPORT_RECORD_PRO_PDEBUGINST_S)) #define DPORT_RECORD_PRO_PDEBUGINST_V 0xFFFFFFFF #define DPORT_RECORD_PRO_PDEBUGINST_S 0 #define DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG (DR_REG_DPORT_BASE + 0x450) + /* DPORT_RECORD_PRO_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */ /* Description: */ + #define DPORT_RECORD_PRO_PDEBUGSTATUS 0x000000FF #define DPORT_RECORD_PRO_PDEBUGSTATUS_M ((DPORT_RECORD_PRO_PDEBUGSTATUS_V)<<(DPORT_RECORD_PRO_PDEBUGSTATUS_S)) #define DPORT_RECORD_PRO_PDEBUGSTATUS_V 0xFF #define DPORT_RECORD_PRO_PDEBUGSTATUS_S 0 #define DPORT_PRO_CPU_RECORD_PDEBUGDATA_REG (DR_REG_DPORT_BASE + 0x454) + /* DPORT_RECORD_PRO_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ /* Description: */ + #define DPORT_RECORD_PRO_PDEBUGDATA 0xFFFFFFFF #define DPORT_RECORD_PRO_PDEBUGDATA_M ((DPORT_RECORD_PRO_PDEBUGDATA_V)<<(DPORT_RECORD_PRO_PDEBUGDATA_S)) #define DPORT_RECORD_PRO_PDEBUGDATA_V 0xFFFFFFFF #define DPORT_RECORD_PRO_PDEBUGDATA_S 0 #define DPORT_PRO_CPU_RECORD_PDEBUGPC_REG (DR_REG_DPORT_BASE + 0x458) + /* DPORT_RECORD_PRO_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ /* Description: */ + #define DPORT_RECORD_PRO_PDEBUGPC 0xFFFFFFFF #define DPORT_RECORD_PRO_PDEBUGPC_M ((DPORT_RECORD_PRO_PDEBUGPC_V)<<(DPORT_RECORD_PRO_PDEBUGPC_S)) #define DPORT_RECORD_PRO_PDEBUGPC_V 0xFFFFFFFF #define DPORT_RECORD_PRO_PDEBUGPC_S 0 #define DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT_REG (DR_REG_DPORT_BASE + 0x45C) + /* DPORT_RECORD_PRO_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */ /* Description: */ + #define DPORT_RECORD_PRO_PDEBUGLS0STAT 0xFFFFFFFF #define DPORT_RECORD_PRO_PDEBUGLS0STAT_M ((DPORT_RECORD_PRO_PDEBUGLS0STAT_V)<<(DPORT_RECORD_PRO_PDEBUGLS0STAT_S)) #define DPORT_RECORD_PRO_PDEBUGLS0STAT_V 0xFFFFFFFF #define DPORT_RECORD_PRO_PDEBUGLS0STAT_S 0 #define DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG (DR_REG_DPORT_BASE + 0x460) + /* DPORT_RECORD_PRO_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ /* Description: */ + #define DPORT_RECORD_PRO_PDEBUGLS0ADDR 0xFFFFFFFF #define DPORT_RECORD_PRO_PDEBUGLS0ADDR_M ((DPORT_RECORD_PRO_PDEBUGLS0ADDR_V)<<(DPORT_RECORD_PRO_PDEBUGLS0ADDR_S)) #define DPORT_RECORD_PRO_PDEBUGLS0ADDR_V 0xFFFFFFFF #define DPORT_RECORD_PRO_PDEBUGLS0ADDR_S 0 #define DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG (DR_REG_DPORT_BASE + 0x464) + /* DPORT_RECORD_PRO_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ /* Description: */ + #define DPORT_RECORD_PRO_PDEBUGLS0DATA 0xFFFFFFFF #define DPORT_RECORD_PRO_PDEBUGLS0DATA_M ((DPORT_RECORD_PRO_PDEBUGLS0DATA_V)<<(DPORT_RECORD_PRO_PDEBUGLS0DATA_S)) #define DPORT_RECORD_PRO_PDEBUGLS0DATA_V 0xFFFFFFFF #define DPORT_RECORD_PRO_PDEBUGLS0DATA_S 0 #define DPORT_APP_CPU_RECORD_CTRL_REG (DR_REG_DPORT_BASE + 0x468) + /* DPORT_APP_CPU_PDEBUG_ENABLE : R/W ;bitpos:[8] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_APP_CPU_PDEBUG_ENABLE (BIT(8)) #define DPORT_APP_CPU_PDEBUG_ENABLE_M (BIT(8)) #define DPORT_APP_CPU_PDEBUG_ENABLE_V 0x1 #define DPORT_APP_CPU_PDEBUG_ENABLE_S 8 + /* DPORT_APP_CPU_RECORD_DISABLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_CPU_RECORD_DISABLE (BIT(4)) #define DPORT_APP_CPU_RECORD_DISABLE_M (BIT(4)) #define DPORT_APP_CPU_RECORD_DISABLE_V 0x1 #define DPORT_APP_CPU_RECORD_DISABLE_S 4 + /* DPORT_APP_CPU_RECORD_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_CPU_RECORD_ENABLE (BIT(0)) #define DPORT_APP_CPU_RECORD_ENABLE_M (BIT(0)) #define DPORT_APP_CPU_RECORD_ENABLE_V 0x1 #define DPORT_APP_CPU_RECORD_ENABLE_S 0 #define DPORT_APP_CPU_RECORD_STATUS_REG (DR_REG_DPORT_BASE + 0x46C) + /* DPORT_APP_CPU_RECORDING : RO ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_APP_CPU_RECORDING (BIT(0)) #define DPORT_APP_CPU_RECORDING_M (BIT(0)) #define DPORT_APP_CPU_RECORDING_V 0x1 #define DPORT_APP_CPU_RECORDING_S 0 #define DPORT_APP_CPU_RECORD_PID_REG (DR_REG_DPORT_BASE + 0x470) + /* DPORT_RECORD_APP_PID : RO ;bitpos:[2:0] ;default: 3'd0 ; */ /* Description: */ + #define DPORT_RECORD_APP_PID 0x00000007 #define DPORT_RECORD_APP_PID_M ((DPORT_RECORD_APP_PID_V)<<(DPORT_RECORD_APP_PID_S)) #define DPORT_RECORD_APP_PID_V 0x7 #define DPORT_RECORD_APP_PID_S 0 #define DPORT_APP_CPU_RECORD_PDEBUGINST_REG (DR_REG_DPORT_BASE + 0x474) + /* DPORT_RECORD_APP_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */ /* Description: */ + #define DPORT_RECORD_APP_PDEBUGINST 0xFFFFFFFF #define DPORT_RECORD_APP_PDEBUGINST_M ((DPORT_RECORD_APP_PDEBUGINST_V)<<(DPORT_RECORD_APP_PDEBUGINST_S)) #define DPORT_RECORD_APP_PDEBUGINST_V 0xFFFFFFFF #define DPORT_RECORD_APP_PDEBUGINST_S 0 #define DPORT_APP_CPU_RECORD_PDEBUGSTATUS_REG (DR_REG_DPORT_BASE + 0x478) + /* DPORT_RECORD_APP_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */ /* Description: */ + #define DPORT_RECORD_APP_PDEBUGSTATUS 0x000000FF #define DPORT_RECORD_APP_PDEBUGSTATUS_M ((DPORT_RECORD_APP_PDEBUGSTATUS_V)<<(DPORT_RECORD_APP_PDEBUGSTATUS_S)) #define DPORT_RECORD_APP_PDEBUGSTATUS_V 0xFF #define DPORT_RECORD_APP_PDEBUGSTATUS_S 0 #define DPORT_APP_CPU_RECORD_PDEBUGDATA_REG (DR_REG_DPORT_BASE + 0x47C) + /* DPORT_RECORD_APP_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ /* Description: */ + #define DPORT_RECORD_APP_PDEBUGDATA 0xFFFFFFFF #define DPORT_RECORD_APP_PDEBUGDATA_M ((DPORT_RECORD_APP_PDEBUGDATA_V)<<(DPORT_RECORD_APP_PDEBUGDATA_S)) #define DPORT_RECORD_APP_PDEBUGDATA_V 0xFFFFFFFF #define DPORT_RECORD_APP_PDEBUGDATA_S 0 #define DPORT_APP_CPU_RECORD_PDEBUGPC_REG (DR_REG_DPORT_BASE + 0x480) + /* DPORT_RECORD_APP_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ /* Description: */ + #define DPORT_RECORD_APP_PDEBUGPC 0xFFFFFFFF #define DPORT_RECORD_APP_PDEBUGPC_M ((DPORT_RECORD_APP_PDEBUGPC_V)<<(DPORT_RECORD_APP_PDEBUGPC_S)) #define DPORT_RECORD_APP_PDEBUGPC_V 0xFFFFFFFF #define DPORT_RECORD_APP_PDEBUGPC_S 0 #define DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG (DR_REG_DPORT_BASE + 0x484) + /* DPORT_RECORD_APP_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */ /* Description: */ + #define DPORT_RECORD_APP_PDEBUGLS0STAT 0xFFFFFFFF #define DPORT_RECORD_APP_PDEBUGLS0STAT_M ((DPORT_RECORD_APP_PDEBUGLS0STAT_V)<<(DPORT_RECORD_APP_PDEBUGLS0STAT_S)) #define DPORT_RECORD_APP_PDEBUGLS0STAT_V 0xFFFFFFFF #define DPORT_RECORD_APP_PDEBUGLS0STAT_S 0 #define DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG (DR_REG_DPORT_BASE + 0x488) + /* DPORT_RECORD_APP_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ /* Description: */ + #define DPORT_RECORD_APP_PDEBUGLS0ADDR 0xFFFFFFFF #define DPORT_RECORD_APP_PDEBUGLS0ADDR_M ((DPORT_RECORD_APP_PDEBUGLS0ADDR_V)<<(DPORT_RECORD_APP_PDEBUGLS0ADDR_S)) #define DPORT_RECORD_APP_PDEBUGLS0ADDR_V 0xFFFFFFFF #define DPORT_RECORD_APP_PDEBUGLS0ADDR_S 0 #define DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG (DR_REG_DPORT_BASE + 0x48C) + /* DPORT_RECORD_APP_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ /* Description: */ + #define DPORT_RECORD_APP_PDEBUGLS0DATA 0xFFFFFFFF #define DPORT_RECORD_APP_PDEBUGLS0DATA_M ((DPORT_RECORD_APP_PDEBUGLS0DATA_V)<<(DPORT_RECORD_APP_PDEBUGLS0DATA_S)) #define DPORT_RECORD_APP_PDEBUGLS0DATA_V 0xFFFFFFFF #define DPORT_RECORD_APP_PDEBUGLS0DATA_S 0 #define DPORT_RSA_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x490) + /* DPORT_RSA_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_RSA_PD (BIT(0)) #define DPORT_RSA_PD_M (BIT(0)) #define DPORT_RSA_PD_V 0x1 #define DPORT_RSA_PD_S 0 #define DPORT_ROM_MPU_TABLE0_REG (DR_REG_DPORT_BASE + 0x494) + /* DPORT_ROM_MPU_TABLE0 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_ROM_MPU_TABLE0 0x00000003 #define DPORT_ROM_MPU_TABLE0_M ((DPORT_ROM_MPU_TABLE0_V)<<(DPORT_ROM_MPU_TABLE0_S)) #define DPORT_ROM_MPU_TABLE0_V 0x3 #define DPORT_ROM_MPU_TABLE0_S 0 #define DPORT_ROM_MPU_TABLE1_REG (DR_REG_DPORT_BASE + 0x498) + /* DPORT_ROM_MPU_TABLE1 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_ROM_MPU_TABLE1 0x00000003 #define DPORT_ROM_MPU_TABLE1_M ((DPORT_ROM_MPU_TABLE1_V)<<(DPORT_ROM_MPU_TABLE1_S)) #define DPORT_ROM_MPU_TABLE1_V 0x3 #define DPORT_ROM_MPU_TABLE1_S 0 #define DPORT_ROM_MPU_TABLE2_REG (DR_REG_DPORT_BASE + 0x49C) + /* DPORT_ROM_MPU_TABLE2 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_ROM_MPU_TABLE2 0x00000003 #define DPORT_ROM_MPU_TABLE2_M ((DPORT_ROM_MPU_TABLE2_V)<<(DPORT_ROM_MPU_TABLE2_S)) #define DPORT_ROM_MPU_TABLE2_V 0x3 #define DPORT_ROM_MPU_TABLE2_S 0 #define DPORT_ROM_MPU_TABLE3_REG (DR_REG_DPORT_BASE + 0x4A0) + /* DPORT_ROM_MPU_TABLE3 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_ROM_MPU_TABLE3 0x00000003 #define DPORT_ROM_MPU_TABLE3_M ((DPORT_ROM_MPU_TABLE3_V)<<(DPORT_ROM_MPU_TABLE3_S)) #define DPORT_ROM_MPU_TABLE3_V 0x3 #define DPORT_ROM_MPU_TABLE3_S 0 #define DPORT_SHROM_MPU_TABLE0_REG (DR_REG_DPORT_BASE + 0x4A4) + /* DPORT_SHROM_MPU_TABLE0 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE0 0x00000003 #define DPORT_SHROM_MPU_TABLE0_M ((DPORT_SHROM_MPU_TABLE0_V)<<(DPORT_SHROM_MPU_TABLE0_S)) #define DPORT_SHROM_MPU_TABLE0_V 0x3 #define DPORT_SHROM_MPU_TABLE0_S 0 #define DPORT_SHROM_MPU_TABLE1_REG (DR_REG_DPORT_BASE + 0x4A8) + /* DPORT_SHROM_MPU_TABLE1 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE1 0x00000003 #define DPORT_SHROM_MPU_TABLE1_M ((DPORT_SHROM_MPU_TABLE1_V)<<(DPORT_SHROM_MPU_TABLE1_S)) #define DPORT_SHROM_MPU_TABLE1_V 0x3 #define DPORT_SHROM_MPU_TABLE1_S 0 #define DPORT_SHROM_MPU_TABLE2_REG (DR_REG_DPORT_BASE + 0x4AC) + /* DPORT_SHROM_MPU_TABLE2 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE2 0x00000003 #define DPORT_SHROM_MPU_TABLE2_M ((DPORT_SHROM_MPU_TABLE2_V)<<(DPORT_SHROM_MPU_TABLE2_S)) #define DPORT_SHROM_MPU_TABLE2_V 0x3 #define DPORT_SHROM_MPU_TABLE2_S 0 #define DPORT_SHROM_MPU_TABLE3_REG (DR_REG_DPORT_BASE + 0x4B0) + /* DPORT_SHROM_MPU_TABLE3 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE3 0x00000003 #define DPORT_SHROM_MPU_TABLE3_M ((DPORT_SHROM_MPU_TABLE3_V)<<(DPORT_SHROM_MPU_TABLE3_S)) #define DPORT_SHROM_MPU_TABLE3_V 0x3 #define DPORT_SHROM_MPU_TABLE3_S 0 #define DPORT_SHROM_MPU_TABLE4_REG (DR_REG_DPORT_BASE + 0x4B4) + /* DPORT_SHROM_MPU_TABLE4 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE4 0x00000003 #define DPORT_SHROM_MPU_TABLE4_M ((DPORT_SHROM_MPU_TABLE4_V)<<(DPORT_SHROM_MPU_TABLE4_S)) #define DPORT_SHROM_MPU_TABLE4_V 0x3 #define DPORT_SHROM_MPU_TABLE4_S 0 #define DPORT_SHROM_MPU_TABLE5_REG (DR_REG_DPORT_BASE + 0x4B8) + /* DPORT_SHROM_MPU_TABLE5 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE5 0x00000003 #define DPORT_SHROM_MPU_TABLE5_M ((DPORT_SHROM_MPU_TABLE5_V)<<(DPORT_SHROM_MPU_TABLE5_S)) #define DPORT_SHROM_MPU_TABLE5_V 0x3 #define DPORT_SHROM_MPU_TABLE5_S 0 #define DPORT_SHROM_MPU_TABLE6_REG (DR_REG_DPORT_BASE + 0x4BC) + /* DPORT_SHROM_MPU_TABLE6 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE6 0x00000003 #define DPORT_SHROM_MPU_TABLE6_M ((DPORT_SHROM_MPU_TABLE6_V)<<(DPORT_SHROM_MPU_TABLE6_S)) #define DPORT_SHROM_MPU_TABLE6_V 0x3 #define DPORT_SHROM_MPU_TABLE6_S 0 #define DPORT_SHROM_MPU_TABLE7_REG (DR_REG_DPORT_BASE + 0x4C0) + /* DPORT_SHROM_MPU_TABLE7 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE7 0x00000003 #define DPORT_SHROM_MPU_TABLE7_M ((DPORT_SHROM_MPU_TABLE7_V)<<(DPORT_SHROM_MPU_TABLE7_S)) #define DPORT_SHROM_MPU_TABLE7_V 0x3 #define DPORT_SHROM_MPU_TABLE7_S 0 #define DPORT_SHROM_MPU_TABLE8_REG (DR_REG_DPORT_BASE + 0x4C4) + /* DPORT_SHROM_MPU_TABLE8 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE8 0x00000003 #define DPORT_SHROM_MPU_TABLE8_M ((DPORT_SHROM_MPU_TABLE8_V)<<(DPORT_SHROM_MPU_TABLE8_S)) #define DPORT_SHROM_MPU_TABLE8_V 0x3 #define DPORT_SHROM_MPU_TABLE8_S 0 #define DPORT_SHROM_MPU_TABLE9_REG (DR_REG_DPORT_BASE + 0x4C8) + /* DPORT_SHROM_MPU_TABLE9 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE9 0x00000003 #define DPORT_SHROM_MPU_TABLE9_M ((DPORT_SHROM_MPU_TABLE9_V)<<(DPORT_SHROM_MPU_TABLE9_S)) #define DPORT_SHROM_MPU_TABLE9_V 0x3 #define DPORT_SHROM_MPU_TABLE9_S 0 #define DPORT_SHROM_MPU_TABLE10_REG (DR_REG_DPORT_BASE + 0x4CC) + /* DPORT_SHROM_MPU_TABLE10 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE10 0x00000003 #define DPORT_SHROM_MPU_TABLE10_M ((DPORT_SHROM_MPU_TABLE10_V)<<(DPORT_SHROM_MPU_TABLE10_S)) #define DPORT_SHROM_MPU_TABLE10_V 0x3 #define DPORT_SHROM_MPU_TABLE10_S 0 #define DPORT_SHROM_MPU_TABLE11_REG (DR_REG_DPORT_BASE + 0x4D0) + /* DPORT_SHROM_MPU_TABLE11 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE11 0x00000003 #define DPORT_SHROM_MPU_TABLE11_M ((DPORT_SHROM_MPU_TABLE11_V)<<(DPORT_SHROM_MPU_TABLE11_S)) #define DPORT_SHROM_MPU_TABLE11_V 0x3 #define DPORT_SHROM_MPU_TABLE11_S 0 #define DPORT_SHROM_MPU_TABLE12_REG (DR_REG_DPORT_BASE + 0x4D4) + /* DPORT_SHROM_MPU_TABLE12 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE12 0x00000003 #define DPORT_SHROM_MPU_TABLE12_M ((DPORT_SHROM_MPU_TABLE12_V)<<(DPORT_SHROM_MPU_TABLE12_S)) #define DPORT_SHROM_MPU_TABLE12_V 0x3 #define DPORT_SHROM_MPU_TABLE12_S 0 #define DPORT_SHROM_MPU_TABLE13_REG (DR_REG_DPORT_BASE + 0x4D8) + /* DPORT_SHROM_MPU_TABLE13 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE13 0x00000003 #define DPORT_SHROM_MPU_TABLE13_M ((DPORT_SHROM_MPU_TABLE13_V)<<(DPORT_SHROM_MPU_TABLE13_S)) #define DPORT_SHROM_MPU_TABLE13_V 0x3 #define DPORT_SHROM_MPU_TABLE13_S 0 #define DPORT_SHROM_MPU_TABLE14_REG (DR_REG_DPORT_BASE + 0x4DC) + /* DPORT_SHROM_MPU_TABLE14 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE14 0x00000003 #define DPORT_SHROM_MPU_TABLE14_M ((DPORT_SHROM_MPU_TABLE14_V)<<(DPORT_SHROM_MPU_TABLE14_S)) #define DPORT_SHROM_MPU_TABLE14_V 0x3 #define DPORT_SHROM_MPU_TABLE14_S 0 #define DPORT_SHROM_MPU_TABLE15_REG (DR_REG_DPORT_BASE + 0x4E0) + /* DPORT_SHROM_MPU_TABLE15 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE15 0x00000003 #define DPORT_SHROM_MPU_TABLE15_M ((DPORT_SHROM_MPU_TABLE15_V)<<(DPORT_SHROM_MPU_TABLE15_S)) #define DPORT_SHROM_MPU_TABLE15_V 0x3 #define DPORT_SHROM_MPU_TABLE15_S 0 #define DPORT_SHROM_MPU_TABLE16_REG (DR_REG_DPORT_BASE + 0x4E4) + /* DPORT_SHROM_MPU_TABLE16 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE16 0x00000003 #define DPORT_SHROM_MPU_TABLE16_M ((DPORT_SHROM_MPU_TABLE16_V)<<(DPORT_SHROM_MPU_TABLE16_S)) #define DPORT_SHROM_MPU_TABLE16_V 0x3 #define DPORT_SHROM_MPU_TABLE16_S 0 #define DPORT_SHROM_MPU_TABLE17_REG (DR_REG_DPORT_BASE + 0x4E8) + /* DPORT_SHROM_MPU_TABLE17 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE17 0x00000003 #define DPORT_SHROM_MPU_TABLE17_M ((DPORT_SHROM_MPU_TABLE17_V)<<(DPORT_SHROM_MPU_TABLE17_S)) #define DPORT_SHROM_MPU_TABLE17_V 0x3 #define DPORT_SHROM_MPU_TABLE17_S 0 #define DPORT_SHROM_MPU_TABLE18_REG (DR_REG_DPORT_BASE + 0x4EC) + /* DPORT_SHROM_MPU_TABLE18 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE18 0x00000003 #define DPORT_SHROM_MPU_TABLE18_M ((DPORT_SHROM_MPU_TABLE18_V)<<(DPORT_SHROM_MPU_TABLE18_S)) #define DPORT_SHROM_MPU_TABLE18_V 0x3 #define DPORT_SHROM_MPU_TABLE18_S 0 #define DPORT_SHROM_MPU_TABLE19_REG (DR_REG_DPORT_BASE + 0x4F0) + /* DPORT_SHROM_MPU_TABLE19 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE19 0x00000003 #define DPORT_SHROM_MPU_TABLE19_M ((DPORT_SHROM_MPU_TABLE19_V)<<(DPORT_SHROM_MPU_TABLE19_S)) #define DPORT_SHROM_MPU_TABLE19_V 0x3 #define DPORT_SHROM_MPU_TABLE19_S 0 #define DPORT_SHROM_MPU_TABLE20_REG (DR_REG_DPORT_BASE + 0x4F4) + /* DPORT_SHROM_MPU_TABLE20 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE20 0x00000003 #define DPORT_SHROM_MPU_TABLE20_M ((DPORT_SHROM_MPU_TABLE20_V)<<(DPORT_SHROM_MPU_TABLE20_S)) #define DPORT_SHROM_MPU_TABLE20_V 0x3 #define DPORT_SHROM_MPU_TABLE20_S 0 #define DPORT_SHROM_MPU_TABLE21_REG (DR_REG_DPORT_BASE + 0x4F8) + /* DPORT_SHROM_MPU_TABLE21 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE21 0x00000003 #define DPORT_SHROM_MPU_TABLE21_M ((DPORT_SHROM_MPU_TABLE21_V)<<(DPORT_SHROM_MPU_TABLE21_S)) #define DPORT_SHROM_MPU_TABLE21_V 0x3 #define DPORT_SHROM_MPU_TABLE21_S 0 #define DPORT_SHROM_MPU_TABLE22_REG (DR_REG_DPORT_BASE + 0x4FC) + /* DPORT_SHROM_MPU_TABLE22 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE22 0x00000003 #define DPORT_SHROM_MPU_TABLE22_M ((DPORT_SHROM_MPU_TABLE22_V)<<(DPORT_SHROM_MPU_TABLE22_S)) #define DPORT_SHROM_MPU_TABLE22_V 0x3 #define DPORT_SHROM_MPU_TABLE22_S 0 #define DPORT_SHROM_MPU_TABLE23_REG (DR_REG_DPORT_BASE + 0x500) + /* DPORT_SHROM_MPU_TABLE23 : R/W ;bitpos:[1:0] ;default: 2'b1 ; */ /* Description: */ + #define DPORT_SHROM_MPU_TABLE23 0x00000003 #define DPORT_SHROM_MPU_TABLE23_M ((DPORT_SHROM_MPU_TABLE23_V)<<(DPORT_SHROM_MPU_TABLE23_S)) #define DPORT_SHROM_MPU_TABLE23_V 0x3 #define DPORT_SHROM_MPU_TABLE23_S 0 #define DPORT_IMMU_TABLE0_REG (DR_REG_DPORT_BASE + 0x504) + /* DPORT_IMMU_TABLE0 : R/W ;bitpos:[6:0] ;default: 7'd0 ; */ /* Description: */ + #define DPORT_IMMU_TABLE0 0x0000007F #define DPORT_IMMU_TABLE0_M ((DPORT_IMMU_TABLE0_V)<<(DPORT_IMMU_TABLE0_S)) #define DPORT_IMMU_TABLE0_V 0x7F #define DPORT_IMMU_TABLE0_S 0 #define DPORT_IMMU_TABLE1_REG (DR_REG_DPORT_BASE + 0x508) + /* DPORT_IMMU_TABLE1 : R/W ;bitpos:[6:0] ;default: 7'd1 ; */ /* Description: */ + #define DPORT_IMMU_TABLE1 0x0000007F #define DPORT_IMMU_TABLE1_M ((DPORT_IMMU_TABLE1_V)<<(DPORT_IMMU_TABLE1_S)) #define DPORT_IMMU_TABLE1_V 0x7F #define DPORT_IMMU_TABLE1_S 0 #define DPORT_IMMU_TABLE2_REG (DR_REG_DPORT_BASE + 0x50C) + /* DPORT_IMMU_TABLE2 : R/W ;bitpos:[6:0] ;default: 7'd2 ; */ /* Description: */ + #define DPORT_IMMU_TABLE2 0x0000007F #define DPORT_IMMU_TABLE2_M ((DPORT_IMMU_TABLE2_V)<<(DPORT_IMMU_TABLE2_S)) #define DPORT_IMMU_TABLE2_V 0x7F #define DPORT_IMMU_TABLE2_S 0 #define DPORT_IMMU_TABLE3_REG (DR_REG_DPORT_BASE + 0x510) + /* DPORT_IMMU_TABLE3 : R/W ;bitpos:[6:0] ;default: 7'd3 ; */ /* Description: */ + #define DPORT_IMMU_TABLE3 0x0000007F #define DPORT_IMMU_TABLE3_M ((DPORT_IMMU_TABLE3_V)<<(DPORT_IMMU_TABLE3_S)) #define DPORT_IMMU_TABLE3_V 0x7F #define DPORT_IMMU_TABLE3_S 0 #define DPORT_IMMU_TABLE4_REG (DR_REG_DPORT_BASE + 0x514) + /* DPORT_IMMU_TABLE4 : R/W ;bitpos:[6:0] ;default: 7'd4 ; */ /* Description: */ + #define DPORT_IMMU_TABLE4 0x0000007F #define DPORT_IMMU_TABLE4_M ((DPORT_IMMU_TABLE4_V)<<(DPORT_IMMU_TABLE4_S)) #define DPORT_IMMU_TABLE4_V 0x7F #define DPORT_IMMU_TABLE4_S 0 #define DPORT_IMMU_TABLE5_REG (DR_REG_DPORT_BASE + 0x518) + /* DPORT_IMMU_TABLE5 : R/W ;bitpos:[6:0] ;default: 7'd5 ; */ /* Description: */ + #define DPORT_IMMU_TABLE5 0x0000007F #define DPORT_IMMU_TABLE5_M ((DPORT_IMMU_TABLE5_V)<<(DPORT_IMMU_TABLE5_S)) #define DPORT_IMMU_TABLE5_V 0x7F #define DPORT_IMMU_TABLE5_S 0 #define DPORT_IMMU_TABLE6_REG (DR_REG_DPORT_BASE + 0x51C) + /* DPORT_IMMU_TABLE6 : R/W ;bitpos:[6:0] ;default: 7'd6 ; */ /* Description: */ + #define DPORT_IMMU_TABLE6 0x0000007F #define DPORT_IMMU_TABLE6_M ((DPORT_IMMU_TABLE6_V)<<(DPORT_IMMU_TABLE6_S)) #define DPORT_IMMU_TABLE6_V 0x7F #define DPORT_IMMU_TABLE6_S 0 #define DPORT_IMMU_TABLE7_REG (DR_REG_DPORT_BASE + 0x520) + /* DPORT_IMMU_TABLE7 : R/W ;bitpos:[6:0] ;default: 7'd7 ; */ /* Description: */ + #define DPORT_IMMU_TABLE7 0x0000007F #define DPORT_IMMU_TABLE7_M ((DPORT_IMMU_TABLE7_V)<<(DPORT_IMMU_TABLE7_S)) #define DPORT_IMMU_TABLE7_V 0x7F #define DPORT_IMMU_TABLE7_S 0 #define DPORT_IMMU_TABLE8_REG (DR_REG_DPORT_BASE + 0x524) + /* DPORT_IMMU_TABLE8 : R/W ;bitpos:[6:0] ;default: 7'd8 ; */ /* Description: */ + #define DPORT_IMMU_TABLE8 0x0000007F #define DPORT_IMMU_TABLE8_M ((DPORT_IMMU_TABLE8_V)<<(DPORT_IMMU_TABLE8_S)) #define DPORT_IMMU_TABLE8_V 0x7F #define DPORT_IMMU_TABLE8_S 0 #define DPORT_IMMU_TABLE9_REG (DR_REG_DPORT_BASE + 0x528) + /* DPORT_IMMU_TABLE9 : R/W ;bitpos:[6:0] ;default: 7'd9 ; */ /* Description: */ + #define DPORT_IMMU_TABLE9 0x0000007F #define DPORT_IMMU_TABLE9_M ((DPORT_IMMU_TABLE9_V)<<(DPORT_IMMU_TABLE9_S)) #define DPORT_IMMU_TABLE9_V 0x7F #define DPORT_IMMU_TABLE9_S 0 #define DPORT_IMMU_TABLE10_REG (DR_REG_DPORT_BASE + 0x52C) + /* DPORT_IMMU_TABLE10 : R/W ;bitpos:[6:0] ;default: 7'd10 ; */ /* Description: */ + #define DPORT_IMMU_TABLE10 0x0000007F #define DPORT_IMMU_TABLE10_M ((DPORT_IMMU_TABLE10_V)<<(DPORT_IMMU_TABLE10_S)) #define DPORT_IMMU_TABLE10_V 0x7F #define DPORT_IMMU_TABLE10_S 0 #define DPORT_IMMU_TABLE11_REG (DR_REG_DPORT_BASE + 0x530) + /* DPORT_IMMU_TABLE11 : R/W ;bitpos:[6:0] ;default: 7'd11 ; */ /* Description: */ + #define DPORT_IMMU_TABLE11 0x0000007F #define DPORT_IMMU_TABLE11_M ((DPORT_IMMU_TABLE11_V)<<(DPORT_IMMU_TABLE11_S)) #define DPORT_IMMU_TABLE11_V 0x7F #define DPORT_IMMU_TABLE11_S 0 #define DPORT_IMMU_TABLE12_REG (DR_REG_DPORT_BASE + 0x534) + /* DPORT_IMMU_TABLE12 : R/W ;bitpos:[6:0] ;default: 7'd12 ; */ /* Description: */ + #define DPORT_IMMU_TABLE12 0x0000007F #define DPORT_IMMU_TABLE12_M ((DPORT_IMMU_TABLE12_V)<<(DPORT_IMMU_TABLE12_S)) #define DPORT_IMMU_TABLE12_V 0x7F #define DPORT_IMMU_TABLE12_S 0 #define DPORT_IMMU_TABLE13_REG (DR_REG_DPORT_BASE + 0x538) + /* DPORT_IMMU_TABLE13 : R/W ;bitpos:[6:0] ;default: 7'd13 ; */ /* Description: */ + #define DPORT_IMMU_TABLE13 0x0000007F #define DPORT_IMMU_TABLE13_M ((DPORT_IMMU_TABLE13_V)<<(DPORT_IMMU_TABLE13_S)) #define DPORT_IMMU_TABLE13_V 0x7F #define DPORT_IMMU_TABLE13_S 0 #define DPORT_IMMU_TABLE14_REG (DR_REG_DPORT_BASE + 0x53C) + /* DPORT_IMMU_TABLE14 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ /* Description: */ + #define DPORT_IMMU_TABLE14 0x0000007F #define DPORT_IMMU_TABLE14_M ((DPORT_IMMU_TABLE14_V)<<(DPORT_IMMU_TABLE14_S)) #define DPORT_IMMU_TABLE14_V 0x7F #define DPORT_IMMU_TABLE14_S 0 #define DPORT_IMMU_TABLE15_REG (DR_REG_DPORT_BASE + 0x540) + /* DPORT_IMMU_TABLE15 : R/W ;bitpos:[6:0] ;default: 7'd15 ; */ /* Description: */ + #define DPORT_IMMU_TABLE15 0x0000007F #define DPORT_IMMU_TABLE15_M ((DPORT_IMMU_TABLE15_V)<<(DPORT_IMMU_TABLE15_S)) #define DPORT_IMMU_TABLE15_V 0x7F #define DPORT_IMMU_TABLE15_S 0 #define DPORT_DMMU_TABLE0_REG (DR_REG_DPORT_BASE + 0x544) + /* DPORT_DMMU_TABLE0 : R/W ;bitpos:[6:0] ;default: 7'd0 ; */ /* Description: */ + #define DPORT_DMMU_TABLE0 0x0000007F #define DPORT_DMMU_TABLE0_M ((DPORT_DMMU_TABLE0_V)<<(DPORT_DMMU_TABLE0_S)) #define DPORT_DMMU_TABLE0_V 0x7F #define DPORT_DMMU_TABLE0_S 0 #define DPORT_DMMU_TABLE1_REG (DR_REG_DPORT_BASE + 0x548) + /* DPORT_DMMU_TABLE1 : R/W ;bitpos:[6:0] ;default: 7'd1 ; */ /* Description: */ + #define DPORT_DMMU_TABLE1 0x0000007F #define DPORT_DMMU_TABLE1_M ((DPORT_DMMU_TABLE1_V)<<(DPORT_DMMU_TABLE1_S)) #define DPORT_DMMU_TABLE1_V 0x7F #define DPORT_DMMU_TABLE1_S 0 #define DPORT_DMMU_TABLE2_REG (DR_REG_DPORT_BASE + 0x54C) + /* DPORT_DMMU_TABLE2 : R/W ;bitpos:[6:0] ;default: 7'd2 ; */ /* Description: */ + #define DPORT_DMMU_TABLE2 0x0000007F #define DPORT_DMMU_TABLE2_M ((DPORT_DMMU_TABLE2_V)<<(DPORT_DMMU_TABLE2_S)) #define DPORT_DMMU_TABLE2_V 0x7F #define DPORT_DMMU_TABLE2_S 0 #define DPORT_DMMU_TABLE3_REG (DR_REG_DPORT_BASE + 0x550) + /* DPORT_DMMU_TABLE3 : R/W ;bitpos:[6:0] ;default: 7'd3 ; */ /* Description: */ + #define DPORT_DMMU_TABLE3 0x0000007F #define DPORT_DMMU_TABLE3_M ((DPORT_DMMU_TABLE3_V)<<(DPORT_DMMU_TABLE3_S)) #define DPORT_DMMU_TABLE3_V 0x7F #define DPORT_DMMU_TABLE3_S 0 #define DPORT_DMMU_TABLE4_REG (DR_REG_DPORT_BASE + 0x554) + /* DPORT_DMMU_TABLE4 : R/W ;bitpos:[6:0] ;default: 7'd4 ; */ /* Description: */ + #define DPORT_DMMU_TABLE4 0x0000007F #define DPORT_DMMU_TABLE4_M ((DPORT_DMMU_TABLE4_V)<<(DPORT_DMMU_TABLE4_S)) #define DPORT_DMMU_TABLE4_V 0x7F #define DPORT_DMMU_TABLE4_S 0 #define DPORT_DMMU_TABLE5_REG (DR_REG_DPORT_BASE + 0x558) + /* DPORT_DMMU_TABLE5 : R/W ;bitpos:[6:0] ;default: 7'd5 ; */ /* Description: */ + #define DPORT_DMMU_TABLE5 0x0000007F #define DPORT_DMMU_TABLE5_M ((DPORT_DMMU_TABLE5_V)<<(DPORT_DMMU_TABLE5_S)) #define DPORT_DMMU_TABLE5_V 0x7F #define DPORT_DMMU_TABLE5_S 0 #define DPORT_DMMU_TABLE6_REG (DR_REG_DPORT_BASE + 0x55C) + /* DPORT_DMMU_TABLE6 : R/W ;bitpos:[6:0] ;default: 7'd6 ; */ /* Description: */ + #define DPORT_DMMU_TABLE6 0x0000007F #define DPORT_DMMU_TABLE6_M ((DPORT_DMMU_TABLE6_V)<<(DPORT_DMMU_TABLE6_S)) #define DPORT_DMMU_TABLE6_V 0x7F #define DPORT_DMMU_TABLE6_S 0 #define DPORT_DMMU_TABLE7_REG (DR_REG_DPORT_BASE + 0x560) + /* DPORT_DMMU_TABLE7 : R/W ;bitpos:[6:0] ;default: 7'd7 ; */ /* Description: */ + #define DPORT_DMMU_TABLE7 0x0000007F #define DPORT_DMMU_TABLE7_M ((DPORT_DMMU_TABLE7_V)<<(DPORT_DMMU_TABLE7_S)) #define DPORT_DMMU_TABLE7_V 0x7F #define DPORT_DMMU_TABLE7_S 0 #define DPORT_DMMU_TABLE8_REG (DR_REG_DPORT_BASE + 0x564) + /* DPORT_DMMU_TABLE8 : R/W ;bitpos:[6:0] ;default: 7'd8 ; */ /* Description: */ + #define DPORT_DMMU_TABLE8 0x0000007F #define DPORT_DMMU_TABLE8_M ((DPORT_DMMU_TABLE8_V)<<(DPORT_DMMU_TABLE8_S)) #define DPORT_DMMU_TABLE8_V 0x7F #define DPORT_DMMU_TABLE8_S 0 #define DPORT_DMMU_TABLE9_REG (DR_REG_DPORT_BASE + 0x568) + /* DPORT_DMMU_TABLE9 : R/W ;bitpos:[6:0] ;default: 7'd9 ; */ /* Description: */ + #define DPORT_DMMU_TABLE9 0x0000007F #define DPORT_DMMU_TABLE9_M ((DPORT_DMMU_TABLE9_V)<<(DPORT_DMMU_TABLE9_S)) #define DPORT_DMMU_TABLE9_V 0x7F #define DPORT_DMMU_TABLE9_S 0 #define DPORT_DMMU_TABLE10_REG (DR_REG_DPORT_BASE + 0x56C) + /* DPORT_DMMU_TABLE10 : R/W ;bitpos:[6:0] ;default: 7'd10 ; */ /* Description: */ + #define DPORT_DMMU_TABLE10 0x0000007F #define DPORT_DMMU_TABLE10_M ((DPORT_DMMU_TABLE10_V)<<(DPORT_DMMU_TABLE10_S)) #define DPORT_DMMU_TABLE10_V 0x7F #define DPORT_DMMU_TABLE10_S 0 #define DPORT_DMMU_TABLE11_REG (DR_REG_DPORT_BASE + 0x570) + /* DPORT_DMMU_TABLE11 : R/W ;bitpos:[6:0] ;default: 7'd11 ; */ /* Description: */ + #define DPORT_DMMU_TABLE11 0x0000007F #define DPORT_DMMU_TABLE11_M ((DPORT_DMMU_TABLE11_V)<<(DPORT_DMMU_TABLE11_S)) #define DPORT_DMMU_TABLE11_V 0x7F #define DPORT_DMMU_TABLE11_S 0 #define DPORT_DMMU_TABLE12_REG (DR_REG_DPORT_BASE + 0x574) + /* DPORT_DMMU_TABLE12 : R/W ;bitpos:[6:0] ;default: 7'd12 ; */ /* Description: */ + #define DPORT_DMMU_TABLE12 0x0000007F #define DPORT_DMMU_TABLE12_M ((DPORT_DMMU_TABLE12_V)<<(DPORT_DMMU_TABLE12_S)) #define DPORT_DMMU_TABLE12_V 0x7F #define DPORT_DMMU_TABLE12_S 0 #define DPORT_DMMU_TABLE13_REG (DR_REG_DPORT_BASE + 0x578) + /* DPORT_DMMU_TABLE13 : R/W ;bitpos:[6:0] ;default: 7'd13 ; */ /* Description: */ + #define DPORT_DMMU_TABLE13 0x0000007F #define DPORT_DMMU_TABLE13_M ((DPORT_DMMU_TABLE13_V)<<(DPORT_DMMU_TABLE13_S)) #define DPORT_DMMU_TABLE13_V 0x7F #define DPORT_DMMU_TABLE13_S 0 #define DPORT_DMMU_TABLE14_REG (DR_REG_DPORT_BASE + 0x57C) + /* DPORT_DMMU_TABLE14 : R/W ;bitpos:[6:0] ;default: 7'd14 ; */ /* Description: */ + #define DPORT_DMMU_TABLE14 0x0000007F #define DPORT_DMMU_TABLE14_M ((DPORT_DMMU_TABLE14_V)<<(DPORT_DMMU_TABLE14_S)) #define DPORT_DMMU_TABLE14_V 0x7F #define DPORT_DMMU_TABLE14_S 0 #define DPORT_DMMU_TABLE15_REG (DR_REG_DPORT_BASE + 0x580) + /* DPORT_DMMU_TABLE15 : R/W ;bitpos:[6:0] ;default: 7'd15 ; */ /* Description: */ + #define DPORT_DMMU_TABLE15 0x0000007F #define DPORT_DMMU_TABLE15_M ((DPORT_DMMU_TABLE15_V)<<(DPORT_DMMU_TABLE15_S)) #define DPORT_DMMU_TABLE15_V 0x7F #define DPORT_DMMU_TABLE15_S 0 #define DPORT_PRO_INTRUSION_CTRL_REG (DR_REG_DPORT_BASE + 0x584) + /* DPORT_PRO_INTRUSION_RECORD_RESET_N : R/W ;bitpos:[0] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_PRO_INTRUSION_RECORD_RESET_N (BIT(0)) #define DPORT_PRO_INTRUSION_RECORD_RESET_N_M (BIT(0)) #define DPORT_PRO_INTRUSION_RECORD_RESET_N_V 0x1 #define DPORT_PRO_INTRUSION_RECORD_RESET_N_S 0 #define DPORT_PRO_INTRUSION_STATUS_REG (DR_REG_DPORT_BASE + 0x588) + /* DPORT_PRO_INTRUSION_RECORD : RO ;bitpos:[3:0] ;default: 4'b0 ; */ /* Description: */ + #define DPORT_PRO_INTRUSION_RECORD 0x0000000F #define DPORT_PRO_INTRUSION_RECORD_M ((DPORT_PRO_INTRUSION_RECORD_V)<<(DPORT_PRO_INTRUSION_RECORD_S)) #define DPORT_PRO_INTRUSION_RECORD_V 0xF #define DPORT_PRO_INTRUSION_RECORD_S 0 #define DPORT_APP_INTRUSION_CTRL_REG (DR_REG_DPORT_BASE + 0x58C) + /* DPORT_APP_INTRUSION_RECORD_RESET_N : R/W ;bitpos:[0] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_APP_INTRUSION_RECORD_RESET_N (BIT(0)) #define DPORT_APP_INTRUSION_RECORD_RESET_N_M (BIT(0)) #define DPORT_APP_INTRUSION_RECORD_RESET_N_V 0x1 #define DPORT_APP_INTRUSION_RECORD_RESET_N_S 0 #define DPORT_APP_INTRUSION_STATUS_REG (DR_REG_DPORT_BASE + 0x590) + /* DPORT_APP_INTRUSION_RECORD : RO ;bitpos:[3:0] ;default: 4'b0 ; */ /* Description: */ + #define DPORT_APP_INTRUSION_RECORD 0x0000000F #define DPORT_APP_INTRUSION_RECORD_M ((DPORT_APP_INTRUSION_RECORD_V)<<(DPORT_APP_INTRUSION_RECORD_S)) #define DPORT_APP_INTRUSION_RECORD_V 0xF #define DPORT_APP_INTRUSION_RECORD_S 0 #define DPORT_FRONT_END_MEM_PD_REG (DR_REG_DPORT_BASE + 0x594) + /* DPORT_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_PBUS_MEM_FORCE_PD (BIT(3)) #define DPORT_PBUS_MEM_FORCE_PD_M (BIT(3)) #define DPORT_PBUS_MEM_FORCE_PD_V 0x1 #define DPORT_PBUS_MEM_FORCE_PD_S 3 + /* DPORT_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_PBUS_MEM_FORCE_PU (BIT(2)) #define DPORT_PBUS_MEM_FORCE_PU_M (BIT(2)) #define DPORT_PBUS_MEM_FORCE_PU_V 0x1 #define DPORT_PBUS_MEM_FORCE_PU_S 2 + /* DPORT_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_AGC_MEM_FORCE_PD (BIT(1)) #define DPORT_AGC_MEM_FORCE_PD_M (BIT(1)) #define DPORT_AGC_MEM_FORCE_PD_V 0x1 #define DPORT_AGC_MEM_FORCE_PD_S 1 + /* DPORT_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ /* Description: */ + #define DPORT_AGC_MEM_FORCE_PU (BIT(0)) #define DPORT_AGC_MEM_FORCE_PU_M (BIT(0)) #define DPORT_AGC_MEM_FORCE_PU_V 0x1 #define DPORT_AGC_MEM_FORCE_PU_S 0 #define DPORT_MMU_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x598) + /* DPORT_MMU_IA_INT_EN : R/W ;bitpos:[23:0] ;default: 24'b0 ; */ /* Description: */ + #define DPORT_MMU_IA_INT_EN 0x00FFFFFF #define DPORT_MMU_IA_INT_EN_M ((DPORT_MMU_IA_INT_EN_V)<<(DPORT_MMU_IA_INT_EN_S)) #define DPORT_MMU_IA_INT_EN_V 0xFFFFFF #define DPORT_MMU_IA_INT_EN_S 0 #define DPORT_MPU_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x59C) + /* DPORT_MPU_IA_INT_EN : R/W ;bitpos:[16:0] ;default: 17'b0 ; */ /* Description: */ + #define DPORT_MPU_IA_INT_EN 0x0001FFFF #define DPORT_MPU_IA_INT_EN_M ((DPORT_MPU_IA_INT_EN_V)<<(DPORT_MPU_IA_INT_EN_S)) #define DPORT_MPU_IA_INT_EN_V 0x1FFFF #define DPORT_MPU_IA_INT_EN_S 0 #define DPORT_CACHE_IA_INT_EN_REG (DR_REG_DPORT_BASE + 0x5A0) + /* DPORT_CACHE_IA_INT_EN : R/W ;bitpos:[27:0] ;default: 28'b0 ; */ /* Description: */ + #define DPORT_CACHE_IA_INT_EN 0x0FFFFFFF #define DPORT_CACHE_IA_INT_EN_M ((DPORT_CACHE_IA_INT_EN_V)<<(DPORT_CACHE_IA_INT_EN_S)) #define DPORT_CACHE_IA_INT_EN_V 0xFFFFFFF #define DPORT_CACHE_IA_INT_EN_S 0 #define DPORT_SECURE_BOOT_CTRL_REG (DR_REG_DPORT_BASE + 0x5A4) + /* DPORT_SW_BOOTLOADER_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */ /* Description: */ + #define DPORT_SW_BOOTLOADER_SEL (BIT(0)) #define DPORT_SW_BOOTLOADER_SEL_M (BIT(0)) #define DPORT_SW_BOOTLOADER_SEL_V 0x1 #define DPORT_SW_BOOTLOADER_SEL_S 0 #define DPORT_SPI_DMA_CHAN_SEL_REG (DR_REG_DPORT_BASE + 0x5A8) + /* DPORT_SPI3_DMA_CHAN_SEL : R/W ;bitpos:[5:4] ;default: 2'b00 ; */ /* Description: */ + #define DPORT_SPI3_DMA_CHAN_SEL 0x00000003 #define DPORT_SPI3_DMA_CHAN_SEL_M ((DPORT_SPI3_DMA_CHAN_SEL_V)<<(DPORT_SPI3_DMA_CHAN_SEL_S)) #define DPORT_SPI3_DMA_CHAN_SEL_V 0x3 #define DPORT_SPI3_DMA_CHAN_SEL_S 4 + /* DPORT_SPI2_DMA_CHAN_SEL : R/W ;bitpos:[3:2] ;default: 2'b00 ; */ /* Description: */ + #define DPORT_SPI2_DMA_CHAN_SEL 0x00000003 #define DPORT_SPI2_DMA_CHAN_SEL_M ((DPORT_SPI2_DMA_CHAN_SEL_V)<<(DPORT_SPI2_DMA_CHAN_SEL_S)) #define DPORT_SPI2_DMA_CHAN_SEL_V 0x3 #define DPORT_SPI2_DMA_CHAN_SEL_S 2 + /* DPORT_SPI1_DMA_CHAN_SEL : R/W ;bitpos:[1:0] ;default: 2'b00 ; */ /* Description: */ + #define DPORT_SPI1_DMA_CHAN_SEL 0x00000003 #define DPORT_SPI1_DMA_CHAN_SEL_M ((DPORT_SPI1_DMA_CHAN_SEL_V)<<(DPORT_SPI1_DMA_CHAN_SEL_S)) #define DPORT_SPI1_DMA_CHAN_SEL_V 0x3 #define DPORT_SPI1_DMA_CHAN_SEL_S 0 #define DPORT_PRO_VECBASE_CTRL_REG (DR_REG_DPORT_BASE + 0x5AC) + /* DPORT_PRO_OUT_VECBASE_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ /* Description: */ + #define DPORT_PRO_OUT_VECBASE_SEL 0x00000003 #define DPORT_PRO_OUT_VECBASE_SEL_M ((DPORT_PRO_OUT_VECBASE_SEL_V)<<(DPORT_PRO_OUT_VECBASE_SEL_S)) #define DPORT_PRO_OUT_VECBASE_SEL_V 0x3 #define DPORT_PRO_OUT_VECBASE_SEL_S 0 #define DPORT_PRO_VECBASE_SET_REG (DR_REG_DPORT_BASE + 0x5B0) + /* DPORT_PRO_OUT_VECBASE_REG : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ /* Description: */ + #define DPORT_PRO_OUT_VECBASE_REG 0x003FFFFF #define DPORT_PRO_OUT_VECBASE_REG_M ((DPORT_PRO_OUT_VECBASE_REG_V)<<(DPORT_PRO_OUT_VECBASE_REG_S)) #define DPORT_PRO_OUT_VECBASE_REG_V 0x3FFFFF #define DPORT_PRO_OUT_VECBASE_REG_S 0 #define DPORT_APP_VECBASE_CTRL_REG (DR_REG_DPORT_BASE + 0x5B4) + /* DPORT_APP_OUT_VECBASE_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ /* Description: */ + #define DPORT_APP_OUT_VECBASE_SEL 0x00000003 #define DPORT_APP_OUT_VECBASE_SEL_M ((DPORT_APP_OUT_VECBASE_SEL_V)<<(DPORT_APP_OUT_VECBASE_SEL_S)) #define DPORT_APP_OUT_VECBASE_SEL_V 0x3 #define DPORT_APP_OUT_VECBASE_SEL_S 0 #define DPORT_APP_VECBASE_SET_REG (DR_REG_DPORT_BASE + 0x5B8) + /* DPORT_APP_OUT_VECBASE_REG : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ /* Description: */ + #define DPORT_APP_OUT_VECBASE_REG 0x003FFFFF #define DPORT_APP_OUT_VECBASE_REG_M ((DPORT_APP_OUT_VECBASE_REG_V)<<(DPORT_APP_OUT_VECBASE_REG_S)) #define DPORT_APP_OUT_VECBASE_REG_V 0x3FFFFF #define DPORT_APP_OUT_VECBASE_REG_S 0 #define DPORT_DATE_REG (DR_REG_DPORT_BASE + 0xFFC) + /* DPORT_DATE : R/W ;bitpos:[27:0] ;default: 28'h1605190 ; */ /* Description: */ + #define DPORT_DATE 0x0FFFFFFF #define DPORT_DATE_M ((DPORT_DATE_V)<<(DPORT_DATE_S)) #define DPORT_DATE_V 0xFFFFFFF diff --git a/arch/xtensa/src/esp32/esp32_timerisr.c b/arch/xtensa/src/esp32/esp32_timerisr.c index 982b3bfa3c..b5a7871ae4 100644 --- a/arch/xtensa/src/esp32/esp32_timerisr.c +++ b/arch/xtensa/src/esp32/esp32_timerisr.c @@ -212,11 +212,9 @@ void xtensa_timer_initialize(void) (void)irq_attach(XTENSA_IRQ_TIMER0, (xcpt_t)esp32_timerisr); - /* Enable the timer interrupt at the device level */ + /* Enable the timer interrupt at the device level. NOTE: It is un-necessary + * to call up_enable_irq() for timers. + */ xtensa_enable_timer(); - - /* And enable the timer interrupt */ - - up_enable_irq(XTENSA_IRQ_TIMER0); } diff --git a/include/ctype.h b/include/ctype.h index 9138a97f4c..dcf918b630 100644 --- a/include/ctype.h +++ b/include/ctype.h @@ -70,7 +70,7 @@ static inline int isspace(int c) #else # define isspace(c) \ ((c) == ' ' || (c) == '\t' || (c) == '\n' || (c) == '\r' || \ - (c) == '\f' || c== '\v') + (c) == '\f' || (c) == '\v') #endif /**************************************************************************** diff --git a/net/devif/ipv4_input.c b/net/devif/ipv4_input.c index ee959754e2..5a773b1ef8 100644 --- a/net/devif/ipv4_input.c +++ b/net/devif/ipv4_input.c @@ -312,8 +312,6 @@ nullreturn: * yet. Currently useful for UDP when a packet arrives before a recv * call is in place. * - * Assumptions: - * ****************************************************************************/ int ipv4_input(FAR struct net_driver_s *dev) -- GitLab From 1d502593581a27d96be5c247debf5d03a6fc73c6 Mon Sep 17 00:00:00 2001 From: Max Kriegleder Date: Mon, 24 Oct 2016 16:32:10 -0600 Subject: [PATCH 202/734] STM32 F4 I2c: A new implementation of the STM32 F4 I2C bottom half. The commin I2C as this did not handled correctly in the current implementation (see also https://github.com/PX4/NuttX/issues/54). The changes almost exclusively affect the ISR. --- arch/arm/src/stm32/Make.defs | 6 +- arch/arm/src/stm32/stm32f40xxx_i2c.c | 2456 ++++++++++++++++++++++++++ 2 files changed, 2459 insertions(+), 3 deletions(-) create mode 100644 arch/arm/src/stm32/stm32f40xxx_i2c.c diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs index f08a904d67..31bd92eee4 100644 --- a/arch/arm/src/stm32/Make.defs +++ b/arch/arm/src/stm32/Make.defs @@ -146,13 +146,13 @@ endif ifeq ($(CONFIG_STM32_I2C_ALT),y) CHIP_CSRCS += stm32_i2c_alt.c -else -ifeq ($(CONFIG_STM32_STM32F30XX),y) +else ifeq ($(CONFIG_STM32_STM32F30XX),y) CHIP_CSRCS += stm32f30xxx_i2c.c +else ifeq ($(CONFIG_STM32_STM32F40XX),y) +CHIP_CSRCS += stm32f40xxx_i2c.c else CHIP_CSRCS += stm32_i2c.c endif -endif ifeq ($(CONFIG_USBDEV),y) ifeq ($(CONFIG_STM32_USB),y) diff --git a/arch/arm/src/stm32/stm32f40xxx_i2c.c b/arch/arm/src/stm32/stm32f40xxx_i2c.c new file mode 100644 index 0000000000..155add73ae --- /dev/null +++ b/arch/arm/src/stm32/stm32f40xxx_i2c.c @@ -0,0 +1,2456 @@ +/************************************************************************************ + * arch/arm/src/stm32/stm32f40xx_i2c.c + * STM32 I2C Hardware Layer - Device Driver + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Author: Uros Platise + * + * With extensions, modifications by: + * + * Copyright (C) 2011-2014, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/* Supports: + * - Master operation, 100 kHz (standard) and 400 kHz (full speed) + * - Multiple instances (shared bus) + * - Interrupt based operation + * + * Structure naming: + * - Device: structure as defined by the nuttx/i2c/i2c.h + * - Instance: represents each individual access to the I2C driver, obtained by + * the i2c_init(); it extends the Device structure from the nuttx/i2c/i2c.h; + * Instance points to OPS, to common I2C Hardware private data and contains + * its own private data, as frequency, address, mode of operation (in the + * future) + * - Private: Private data of an I2C Hardware + * + * TODO + * - Check for all possible deadlocks (as BUSY='1' I2C needs to be reset in HW + * using the I2C_CR1_SWRST) + * - SMBus support (hardware layer timings are already supported) and add SMBA + * gpio pin + * - Slave support with multiple addresses (on multiple instances): + * - 2 x 7-bit address or + * - 1 x 10 bit addresses + 1 x 7 bit address (?) + * - plus the broadcast address (general call) + * - Multi-master support + * - DMA (to get rid of too many CPU wake-ups and interventions) + * - Be ready for IPMI + */ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "up_arch.h" + +#include "stm32_rcc.h" +#include "stm32_i2c.h" +#include "stm32_waste.h" + +/* At least one I2C peripheral must be enabled */ + +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) + +/* This implementation is for the STM32 F1, F2, and F4 only */ +/* Experimentally enabled for STM32L15XX */ + +#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ + defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Configuration ********************************************************************/ +/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. Instead, + * CPU-intensive polling will be used. + */ + +/* Interrupt wait timeout in seconds and milliseconds */ + +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ +#endif + +/* Interrupt wait time timeout in system timer ticks */ + +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) +#endif + +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) +#endif + +/* On the STM32F103ZE, there is an internal conflict between I2C1 and FSMC. In that + * case, it is necessary to disable FSMC before each I2C1 access and re-enable FSMC + * when the I2C access completes. + */ + +#undef I2C1_FSMC_CONFLICT +#if defined(CONFIG_STM32_STM32F10XX) && defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_I2C1) +# define I2C1_FSMC_CONFLICT +#endif + +/* Macros to convert a I2C pin to a GPIO output */ + +#if defined(CONFIG_STM32_STM32L15XX) +# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_OPENDRAIN | \ + GPIO_SPEED_40MHz) +#elif defined(CONFIG_STM32_STM32F10XX) +# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \ + GPIO_MODE_50MHz) +#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +# define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\ + GPIO_SPEED_50MHz | GPIO_OUTPUT_SET) +#endif + +#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT) + +/* Debug ****************************************************************************/ + +/* I2C event trace logic. NOTE: trace uses the internal, non-standard, low-level + * debug interface syslog() but does not require that any other debug + * is enabled. + */ + +#ifndef CONFIG_I2C_TRACE +# define stm32_i2c_tracereset(p) +# define stm32_i2c_tracenew(p,s) +# define stm32_i2c_traceevent(p,e,a) +# define stm32_i2c_tracedump(p) +#endif + +#ifndef CONFIG_I2C_NTRACE +# define CONFIG_I2C_NTRACE 32 +#endif + +/************************************************************************************ + * Private Types + ************************************************************************************/ +/* Interrupt state */ + +enum stm32_intstate_e +{ + INTSTATE_IDLE = 0, /* No I2C activity */ + INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ + INTSTATE_DONE, /* Interrupt activity complete */ +}; + +/* Trace events */ + +enum stm32_trace_e +{ + I2CEVENT_NONE = 0, /* No events have occurred with this status */ + I2CEVENT_SENDADDR, /* Start/Master bit set and address sent, param = msgc */ + I2CEVENT_SENDBYTE, /* Send byte, param = dcnt */ + I2CEVENT_ITBUFEN, /* Enable buffer interrupts, param = 0 */ + I2CEVENT_RCVBYTE, /* Read more dta, param = dcnt */ + I2CEVENT_REITBUFEN, /* Re-enable buffer interrupts, param = 0 */ + I2CEVENT_DISITBUFEN, /* Disable buffer interrupts, param = 0 */ + I2CEVENT_BTFNOSTART, /* BTF on last byte with no restart, param = msgc */ + I2CEVENT_BTFRESTART, /* Last byte sent, re-starting, param = msgc */ + I2CEVENT_BTFSTOP, /* Last byte sten, send stop, param = 0 */ + I2CEVENT_ERROR /* Error occurred, param = 0 */ +}; + +/* Trace data */ + +struct stm32_trace_s +{ + uint32_t status; /* I2C 32-bit SR2|SR1 status */ + uint32_t count; /* Interrupt count when status change */ + enum stm32_intstate_e event; /* Last event that occurred with this status */ + uint32_t parm; /* Parameter associated with the event */ + systime_t time; /* First of event or first status */ +}; + +/* I2C Device hardware configuration */ + +struct stm32_i2c_config_s +{ + uint32_t base; /* I2C base address */ + uint32_t clk_bit; /* Clock enable bit */ + uint32_t reset_bit; /* Reset bit */ + uint32_t scl_pin; /* GPIO configuration for SCL as SCL */ + uint32_t sda_pin; /* GPIO configuration for SDA as SDA */ +#ifndef CONFIG_I2C_POLLED + int (*isr)(int, void *); /* Interrupt handler */ + uint32_t ev_irq; /* Event IRQ */ + uint32_t er_irq; /* Error IRQ */ +#endif +}; + +/* I2C Device Private Data */ + +struct stm32_i2c_priv_s +{ + const struct i2c_ops_s *ops; /* Standard I2C operations */ + const struct stm32_i2c_config_s *config; /* Port configuration */ + int refs; /* Referernce count */ + sem_t sem_excl; /* Mutual exclusion semaphore */ +#ifndef CONFIG_I2C_POLLED + sem_t sem_isr; /* Interrupt wait semaphore */ +#endif + volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */ + + uint8_t msgc; /* Message count */ + struct i2c_msg_s *msgv; /* Message list */ + uint8_t *ptr; /* Current message buffer */ + uint32_t frequency; /* Current I2C frequency */ + int dcnt; /* Current message length */ + uint16_t flags; /* Current message flags */ + bool check_addr_ACK; /* Flag to signal if on next interrupt address has ACKed */ + uint8_t total_msg_len; /* Flag to signal a short read sequence */ + + /* I2C trace support */ + +#ifdef CONFIG_I2C_TRACE + int tndx; /* Trace array index */ + systime_t start_time; /* Time when the trace was started */ + + /* The actual trace data */ + + struct stm32_trace_s trace[CONFIG_I2C_NTRACE]; +#endif + + uint32_t status; /* End of transfer SR2|SR1 status */ +}; + +/************************************************************************************ + * Private Function Prototypes + ************************************************************************************/ + +static inline uint16_t stm32_i2c_getreg(FAR struct stm32_i2c_priv_s *priv, + uint8_t offset); +static inline void stm32_i2c_putreg(FAR struct stm32_i2c_priv_s *priv, uint8_t offset, + uint16_t value); +static inline void stm32_i2c_modifyreg(FAR struct stm32_i2c_priv_s *priv, + uint8_t offset, uint16_t clearbits, + uint16_t setbits); +static inline void stm32_i2c_sem_wait(FAR struct stm32_i2c_priv_s *priv); + +#ifdef CONFIG_STM32_I2C_DYNTIMEO +static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs); +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ + +static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sem_post(FAR struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sem_destroy(FAR struct stm32_i2c_priv_s *priv); + +#ifdef CONFIG_I2C_TRACE +static void stm32_i2c_tracereset(FAR struct stm32_i2c_priv_s *priv); +static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint32_t status); +static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm); +static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv); +#endif /* CONFIG_I2C_TRACE */ + +static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, + uint32_t frequency); +static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_clrstart(FAR struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv); +static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv); + +#ifdef I2C1_FSMC_CONFLICT +static inline uint32_t stm32_i2c_disablefsmc(FAR struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_enablefsmc(uint32_t ahbenr); +#endif /* I2C1_FSMC_CONFLICT */ + +static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv); + +#ifndef CONFIG_I2C_POLLED +#ifdef CONFIG_STM32_I2C1 +static int stm32_i2c1_isr(int irq, void *context); +#endif +#ifdef CONFIG_STM32_I2C2 +static int stm32_i2c2_isr(int irq, void *context); +#endif +#ifdef CONFIG_STM32_I2C3 +static int stm32_i2c3_isr(int irq, void *context); +#endif +#endif /* !CONFIG_I2C_POLLED */ + +static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv); +static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv); +static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs, + int count); +#ifdef CONFIG_I2C_RESET +static int stm32_i2c_reset(FAR struct i2c_master_s *dev); +#endif + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +/* Trace events strings */ + +#ifdef CONFIG_I2C_TRACE +static const char *g_trace_names[] = +{ + "NONE ", + "SENDADDR ", + "SENDBYTE ", + "ITBUFEN ", + "RCVBYTE ", + "REITBUFEN ", + "DISITBUFEN", + "BTFNOSTART", + "BTFRESTART", + "BTFSTOP ", + "ERROR " +}; +#endif + +/* I2C interface */ + +static const struct i2c_ops_s stm32_i2c_ops = +{ + .transfer = stm32_i2c_transfer +#ifdef CONFIG_I2C_RESET + , .reset = stm32_i2c_reset +#endif +}; + +/* I2C device structures */ + +#ifdef CONFIG_STM32_I2C1 +static const struct stm32_i2c_config_s stm32_i2c1_config = +{ + .base = STM32_I2C1_BASE, + .clk_bit = RCC_APB1ENR_I2C1EN, + .reset_bit = RCC_APB1RSTR_I2C1RST, + .scl_pin = GPIO_I2C1_SCL, + .sda_pin = GPIO_I2C1_SDA, +#ifndef CONFIG_I2C_POLLED + .isr = stm32_i2c1_isr, + .ev_irq = STM32_IRQ_I2C1EV, + .er_irq = STM32_IRQ_I2C1ER +#endif +}; + +static struct stm32_i2c_priv_s stm32_i2c1_priv = +{ + .ops = &stm32_i2c_ops, + .config = &stm32_i2c1_config, + .refs = 0, + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +#ifdef CONFIG_STM32_I2C2 +static const struct stm32_i2c_config_s stm32_i2c2_config = +{ + .base = STM32_I2C2_BASE, + .clk_bit = RCC_APB1ENR_I2C2EN, + .reset_bit = RCC_APB1RSTR_I2C2RST, + .scl_pin = GPIO_I2C2_SCL, + .sda_pin = GPIO_I2C2_SDA, +#ifndef CONFIG_I2C_POLLED + .isr = stm32_i2c2_isr, + .ev_irq = STM32_IRQ_I2C2EV, + .er_irq = STM32_IRQ_I2C2ER +#endif +}; + +static struct stm32_i2c_priv_s stm32_i2c2_priv = +{ + .ops = &stm32_i2c_ops, + .config = &stm32_i2c2_config, + .refs = 0, + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +#ifdef CONFIG_STM32_I2C3 +static const struct stm32_i2c_config_s stm32_i2c3_config = +{ + .base = STM32_I2C3_BASE, + .clk_bit = RCC_APB1ENR_I2C3EN, + .reset_bit = RCC_APB1RSTR_I2C3RST, + .scl_pin = GPIO_I2C3_SCL, + .sda_pin = GPIO_I2C3_SDA, +#ifndef CONFIG_I2C_POLLED + .isr = stm32_i2c3_isr, + .ev_irq = STM32_IRQ_I2C3EV, + .er_irq = STM32_IRQ_I2C3ER +#endif +}; + +static struct stm32_i2c_priv_s stm32_i2c3_priv = +{ + .ops = &stm32_i2c_ops, + .config = &stm32_i2c3_config, + .refs = 0, + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_i2c_getreg + * + * Description: + * Get a 16-bit register value by offset + * + ************************************************************************************/ + +static inline uint16_t stm32_i2c_getreg(FAR struct stm32_i2c_priv_s *priv, + uint8_t offset) +{ + return getreg16(priv->config->base + offset); +} + +/************************************************************************************ + * Name: stm32_i2c_putreg + * + * Description: + * Put a 16-bit register value by offset + * + ************************************************************************************/ + +static inline void stm32_i2c_putreg(FAR struct stm32_i2c_priv_s *priv, uint8_t offset, + uint16_t value) +{ + putreg16(value, priv->config->base + offset); +} + +/************************************************************************************ + * Name: stm32_i2c_modifyreg + * + * Description: + * Modify a 16-bit register value by offset + * + ************************************************************************************/ + +static inline void stm32_i2c_modifyreg(FAR struct stm32_i2c_priv_s *priv, + uint8_t offset, uint16_t clearbits, + uint16_t setbits) +{ + modifyreg16(priv->config->base + offset, clearbits, setbits); +} + +/************************************************************************************ + * Name: stm32_i2c_sem_wait + * + * Description: + * Take the exclusive access, waiting as necessary + * + ************************************************************************************/ + +static inline void stm32_i2c_sem_wait(FAR struct stm32_i2c_priv_s *priv) +{ + while (sem_wait(&priv->sem_excl) != 0) + { + ASSERT(errno == EINTR); + } +} + +/************************************************************************************ + * Name: stm32_i2c_tousecs + * + * Description: + * Return a micro-second delay based on the number of bytes left to be processed. + * + ************************************************************************************/ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO +static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs) +{ + size_t bytecount = 0; + int i; + + /* Count the number of bytes left to process */ + + for (i = 0; i < msgc; i++) + { + bytecount += msgs[i].length; + } + + /* Then return a number of microseconds based on a user provided scaling + * factor. + */ + + return (useconds_t)(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); +} +#endif + +/************************************************************************************ + * Name: stm32_i2c_sem_waitdone + * + * Description: + * Wait for a transfer to complete + * + ************************************************************************************/ + +#ifndef CONFIG_I2C_POLLED +static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv) +{ + struct timespec abstime; + irqstate_t flags; + uint32_t regval; + int ret; + + flags = enter_critical_section(); + + /* Enable I2C interrupts */ + + regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + regval |= (I2C_CR2_ITERREN | I2C_CR2_ITEVFEN); + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); + + /* Signal the interrupt handler that we are waiting. NOTE: Interrupts + * are currently disabled but will be temporarily re-enabled below when + * sem_timedwait() sleeps. + */ + + priv->intstate = INTSTATE_WAITING; + do + { + /* Get the current time */ + + (void)clock_gettime(CLOCK_REALTIME, &abstime); + + /* Calculate a time in the future */ + +#if CONFIG_STM32_I2CTIMEOSEC > 0 + abstime.tv_sec += CONFIG_STM32_I2CTIMEOSEC; +#endif + + /* Add a value proportional to the number of bytes in the transfer */ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO + abstime.tv_nsec += 1000 * stm32_i2c_tousecs(priv->msgc, priv->msgv); + if (abstime.tv_nsec >= 1000 * 1000 * 1000) + { + abstime.tv_sec++; + abstime.tv_nsec -= 1000 * 1000 * 1000; + } + +#elif CONFIG_STM32_I2CTIMEOMS > 0 + abstime.tv_nsec += CONFIG_STM32_I2CTIMEOMS * 1000 * 1000; + if (abstime.tv_nsec >= 1000 * 1000 * 1000) + { + abstime.tv_sec++; + abstime.tv_nsec -= 1000 * 1000 * 1000; + } +#endif + + /* Wait until either the transfer is complete or the timeout expires */ + + ret = sem_timedwait(&priv->sem_isr, &abstime); + if (ret != OK && errno != EINTR) + { + /* Break out of the loop on irrecoverable errors. This would + * include timeouts and mystery errors reported by sem_timedwait. + * NOTE that we try again if we are awakened by a signal (EINTR). + */ + + break; + } + } + + /* Loop until the interrupt level transfer is complete. */ + + while (priv->intstate != INTSTATE_DONE); + + /* Set the interrupt state back to IDLE */ + + priv->intstate = INTSTATE_IDLE; + + /* Disable I2C interrupts */ + + regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + regval &= ~I2C_CR2_ALLINTS; + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); + + leave_critical_section(flags); + return ret; +} +#else +static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv) +{ + systime_t timeout; + systime_t start; + systime_t elapsed; + int ret; + + /* Get the timeout value */ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(stm32_i2c_tousecs(priv->msgc, priv->msgv)); +#else + timeout = CONFIG_STM32_I2CTIMEOTICKS; +#endif + + /* Signal the interrupt handler that we are waiting. NOTE: Interrupts + * are currently disabled but will be temporarily re-enabled below when + * sem_timedwait() sleeps. + */ + + priv->intstate = INTSTATE_WAITING; + start = clock_systimer(); + + do + { + /* Poll by simply calling the timer interrupt handler until it + * reports that it is done. + */ + + stm32_i2c_isr(priv); + + /* Calculate the elapsed time */ + + elapsed = clock_systimer() - start; + } + + /* Loop until the transfer is complete. */ + + while (priv->intstate != INTSTATE_DONE && elapsed < timeout); + + i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: %08x\n", + priv->intstate, (long)elapsed, (long)timeout, priv->status); + + /* Set the interrupt state back to IDLE */ + + ret = priv->intstate == INTSTATE_DONE ? OK : -ETIMEDOUT; + priv->intstate = INTSTATE_IDLE; + return ret; +} +#endif + +/************************************************************************************ + * Name: stm32_i2c_sem_waitstop + * + * Description: + * Wait for a STOP to complete + * + ************************************************************************************/ + +static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv) +{ + systime_t start; + systime_t elapsed; + systime_t timeout; + uint32_t cr1; + uint32_t sr1; + + /* Select a timeout */ + +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); +#else + timeout = CONFIG_STM32_I2CTIMEOTICKS; +#endif + + /* Wait as stop might still be in progress; but stop might also + * be set because of a timeout error: "The [STOP] bit is set and + * cleared by software, cleared by hardware when a Stop condition is + * detected, set by hardware when a timeout error is detected." + */ + + start = clock_systimer(); + do + { + /* Check for STOP condition */ + + cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET); + if ((cr1 & I2C_CR1_STOP) == 0) + { + return; + } + + /* Check for timeout error */ + + sr1 = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); + if ((sr1 & I2C_SR1_TIMEOUT) != 0) + { + return; + } + + /* Calculate the elapsed time */ + + elapsed = clock_systimer() - start; + } + + /* Loop until the stop is complete or a timeout occurs. */ + + while (elapsed < timeout); + + /* If we get here then a timeout occurred with the STOP condition + * still pending. + */ + + i2cinfo("Timeout with CR1: %04x SR1: %04x\n", cr1, sr1); +} + +/************************************************************************************ + * Name: stm32_i2c_sem_post + * + * Description: + * Release the mutual exclusion semaphore + * + ************************************************************************************/ + +static inline void stm32_i2c_sem_post(struct stm32_i2c_priv_s *priv) +{ + sem_post(&priv->sem_excl); +} + +/************************************************************************************ + * Name: stm32_i2c_sem_init + * + * Description: + * Initialize semaphores + * + ************************************************************************************/ + +static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv) +{ + sem_init(&priv->sem_excl, 0, 1); +#ifndef CONFIG_I2C_POLLED + sem_init(&priv->sem_isr, 0, 0); +#endif +} + +/************************************************************************************ + * Name: stm32_i2c_sem_destroy + * + * Description: + * Destroy semaphores. + * + ************************************************************************************/ + +static inline void stm32_i2c_sem_destroy(FAR struct stm32_i2c_priv_s *priv) +{ + sem_destroy(&priv->sem_excl); +#ifndef CONFIG_I2C_POLLED + sem_destroy(&priv->sem_isr); +#endif +} + +/************************************************************************************ + * Name: stm32_i2c_trace* + * + * Description: + * I2C trace instrumentation + * + ************************************************************************************/ + +#ifdef CONFIG_I2C_TRACE +static void stm32_i2c_traceclear(FAR struct stm32_i2c_priv_s *priv) +{ + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; + + trace->status = 0; /* I2C 32-bit SR2|SR1 status */ + trace->count = 0; /* Interrupt count when status change */ + trace->event = I2CEVENT_NONE; /* Last event that occurred with this status */ + trace->parm = 0; /* Parameter associated with the event */ + trace->time = 0; /* Time of first status or event */ +} + +static void stm32_i2c_tracereset(FAR struct stm32_i2c_priv_s *priv) +{ + /* Reset the trace info for a new data collection */ + + priv->tndx = 0; + priv->start_time = clock_systimer(); + stm32_i2c_traceclear(priv); +} + +static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint32_t status) +{ + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; + + /* Is the current entry uninitialized? Has the status changed? */ + + if (trace->count == 0 || status != trace->status) + { + /* Yes.. Was it the status changed? */ + + if (trace->count != 0) + { + /* Yes.. bump up the trace index (unless we are out of trace entries) */ + + if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) + { + i2cerr("ERROR: Trace table overflow\n"); + return; + } + + priv->tndx++; + trace = &priv->trace[priv->tndx]; + } + + /* Initialize the new trace entry */ + + stm32_i2c_traceclear(priv); + trace->status = status; + trace->count = 1; + trace->time = clock_systimer(); + } + else + { + /* Just increment the count of times that we have seen this status */ + + trace->count++; + } +} + +static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm) +{ + struct stm32_trace_s *trace; + + if (event != I2CEVENT_NONE) + { + trace = &priv->trace[priv->tndx]; + + /* Initialize the new trace entry */ + + trace->event = event; + trace->parm = parm; + + /* Bump up the trace index (unless we are out of trace entries) */ + + if (priv->tndx >= (CONFIG_I2C_NTRACE-1)) + { + i2cerr("ERROR: Trace table overflow\n"); + return; + } + + priv->tndx++; + stm32_i2c_traceclear(priv); + } +} + +static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv) +{ + struct stm32_trace_s *trace; + int i; + + syslog(LOG_DEBUG, "Elapsed time: %ld\n", + (long)(clock_systimer() - priv->start_time)); + + for (i = 0; i <= priv->tndx; i++) + { + trace = &priv->trace[i]; + syslog(LOG_DEBUG, + "%2d. STATUS: %08x COUNT: %3d EVENT: %s(%2d) PARM: %08x TIME: %d\n", + i+1, trace->status, trace->count, g_trace_names[trace->event], + trace->event, trace->parm, trace->time - priv->start_time); + } +} +#endif /* CONFIG_I2C_TRACE */ + +/************************************************************************************ + * Name: stm32_i2c_setclock + * + * Description: + * Set the I2C clock + * + ************************************************************************************/ + +static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequency) +{ + uint16_t cr1; + uint16_t ccr; + uint16_t trise; + uint16_t freqmhz; + uint16_t speed; + + /* Has the I2C bus frequency changed? */ + + if (frequency != priv->frequency) + { + /* Disable the selected I2C peripheral to configure TRISE */ + + cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET); + stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, cr1 & ~I2C_CR1_PE); + + /* Update timing and control registers */ + + freqmhz = (uint16_t)(STM32_PCLK1_FREQUENCY / 1000000); + ccr = 0; + + /* Configure speed in standard mode */ + + if (frequency <= 100000) + { + /* Standard mode speed calculation */ + + speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency << 1)); + + /* The CCR fault must be >= 4 */ + + if (speed < 4) + { + /* Set the minimum allowed value */ + + speed = 4; + } + + ccr |= speed; + + /* Set Maximum Rise Time for standard mode */ + + trise = freqmhz + 1; + } + + /* Configure speed in fast mode */ + + else /* (frequency <= 400000) */ + { + /* Fast mode speed calculation with Tlow/Thigh = 16/9 */ + +#ifdef CONFIG_STM32_I2C_DUTY16_9 + speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 25)); + + /* Set DUTY and fast speed bits */ + + ccr |= (I2C_CCR_DUTY | I2C_CCR_FS); +#else + /* Fast mode speed calculation with Tlow/Thigh = 2 */ + + speed = (uint16_t)(STM32_PCLK1_FREQUENCY / (frequency * 3)); + + /* Set fast speed bit */ + + ccr |= I2C_CCR_FS; +#endif + + /* Verify that the CCR speed value is nonzero */ + + if (speed < 1) + { + /* Set the minimum allowed value */ + + speed = 1; + } + + ccr |= speed; + + /* Set Maximum Rise Time for fast mode */ + + trise = (uint16_t)(((freqmhz * 300) / 1000) + 1); + } + + /* Write the new values of the CCR and TRISE registers */ + + stm32_i2c_putreg(priv, STM32_I2C_CCR_OFFSET, ccr); + stm32_i2c_putreg(priv, STM32_I2C_TRISE_OFFSET, trise); + + /* Bit 14 of OAR1 must be configured and kept at 1 */ + + stm32_i2c_putreg(priv, STM32_I2C_OAR1_OFFSET, I2C_OAR1_ONE); + + /* Re-enable the peripheral (or not) */ + + stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, cr1); + + /* Save the new I2C frequency */ + + priv->frequency = frequency; + } +} + +/************************************************************************************ + * Name: stm32_i2c_sendstart + * + * Description: + * Send the START conditions/force Master mode + * + ************************************************************************************/ + +static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv) +{ + /* Disable ACK on receive by default and generate START */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, I2C_CR1_START); +} + +/************************************************************************************ + * Name: stm32_i2c_clrstart + * + * Description: + * Clear the STOP, START or PEC condition on certain error recovery steps. + * + ************************************************************************************/ + +static inline void stm32_i2c_clrstart(FAR struct stm32_i2c_priv_s *priv) +{ + /* "Note: When the STOP, START or PEC bit is set, the software must + * not perform any write access to I2C_CR1 before this bit is + * cleared by hardware. Otherwise there is a risk of setting a + * second STOP, START or PEC request." + * + * "The [STOP] bit is set and cleared by software, cleared by hardware + * when a Stop condition is detected, set by hardware when a timeout + * error is detected. + * + * "This [START] bit is set and cleared by software and cleared by hardware + * when start is sent or PE=0." The bit must be cleared by software if the + * START is never sent. + * + * "This [PEC] bit is set and cleared by software, and cleared by hardware + * when PEC is transferred or by a START or Stop condition or when PE=0." + */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, + I2C_CR1_START | I2C_CR1_STOP | I2C_CR1_PEC, 0); +} + +/************************************************************************************ + * Name: stm32_i2c_sendstop + * + * Description: + * Send the STOP conditions + * + ************************************************************************************/ + +static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv) +{ + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, I2C_CR1_STOP); +} + +/************************************************************************************ + * Name: stm32_i2c_getstatus + * + * Description: + * Get 32-bit status (SR1 and SR2 combined) + * + ************************************************************************************/ + +static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv) +{ + uint32_t status = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + return status; +} + +/************************************************************************************ + * Name: stm32_i2c_disablefsmc + * + * Description: + * FSMC must be disable while accessing I2C1 because it uses a common resource + * (LBAR) + * + * NOTE: This is an issue with the STM32F103ZE, but may not be an issue with other + * STM32s. You may need to experiment + * + ************************************************************************************/ + +#ifdef I2C1_FSMC_CONFLICT +static inline uint32_t stm32_i2c_disablefsmc(FAR struct stm32_i2c_priv_s *priv) +{ + uint32_t ret = 0; + uint32_t regval; + + /* Is this I2C1 */ + +#if defined(CONFIG_STM32_I2C2) || defined(CONFIG_STM32_I2C3) + if (priv->config->base == STM32_I2C1_BASE) +#endif + { + /* Disable FSMC unconditionally */ + + ret = getreg32(STM32_RCC_AHBENR); + regval = ret & ~RCC_AHBENR_FSMCEN; + putreg32(regval, STM32_RCC_AHBENR); + } + + return ret; +} + +/************************************************************************************ + * Name: stm32_i2c_enablefsmc + * + * Description: + * Re-enable the FSMC + * + ************************************************************************************/ + +static inline void stm32_i2c_enablefsmc(uint32_t ahbenr) +{ + uint32_t regval; + + /* Enable AHB clocking to the FSMC only if it was previously enabled. */ + + if ((ahbenr & RCC_AHBENR_FSMCEN) != 0) + { + regval = getreg32(STM32_RCC_AHBENR); + regval |= RCC_AHBENR_FSMCEN; + putreg32(regval, STM32_RCC_AHBENR); + } +} +#else +# define stm32_i2c_disablefsmc(priv) (0) +# define stm32_i2c_enablefsmc(ahbenr) +#endif /* I2C1_FSMC_CONFLICT */ + +/************************************************************************************ + * Name: stm32_i2c_isr + * + * Description: + * Common Interrupt Service Routine + * + ************************************************************************************/ + +static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv) +{ + uint32_t status; + + i2cinfo("I2C ISR called\n"); + + /* Get state of the I2C controller (register SR1 only) + * + * Get control register SR1 only as reading both SR1 and SR2 clears the ADDR + * flag(possibly others) causing the hardware to advance to the next state + * without the proper action being taken. + */ + + status = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET); + + /* Update private version of the state */ + + priv->status = status; + + /* Check if this is a new transmission so to set up the + * trace table accordingly. + */ + + stm32_i2c_tracenew(priv, status); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); + + /* Messages handling (1/2) + * + * Message handling should only operate when a message has been completely + * sent and after the ISR had the chance to run to set bits after the last + * written/read byte, i.e. priv->dcnt == -1. This is also the case in when + * the ISR is called for the first time. This can seen in stm32_i2c_process() + * before entering the stm32_i2c_sem_waitdone() waiting process. + * + * Message handling should only operate when: + * - A message has been completely sent and there are still messages + * to send(i.e. msgc > 0). + * - After the ISR had the chance to run to set start bit or termination + * flags after the last written/read byte(after last byte dcnt=0, msg + * handling dcnt = -1). + * + * When the ISR is called for the first time the same conditions hold. + * This can seen in stm32_i2c_process() before entering the + * stm32_i2c_sem_waitdone() waiting process. + */ + + if (priv->dcnt == -1 && priv->msgc > 0) + { + i2cinfo("Switch to new message\n"); + + /* Get current message to process data and copy to private structure */ + + priv->ptr = priv->msgv->buffer; /* Copy buffer to private struct */ + priv->dcnt = priv->msgv->length; /* Set counter of current msg length */ + priv->total_msg_len = priv->msgv->length; /* Set total msg length */ + priv->flags = priv->msgv->flags; /* Copy flags to private struct */ + + i2cinfo("Current flags %i\n", priv->flags); + + /* Decrease counter to indicate the number of messages left to process */ + + priv->msgc--; + + /* Decrease message pointer. If last message set next message vector to null */ + + if (priv->msgc == 0) + { + /* No more messages, don't need to increment msgv. This pointer will be set + * to zero when reaching the termination of the ISR calls, i.e. Messages + * handling(2/2). + */ + } + else + { + /* If not last message increment to next message to process */ + + priv->msgv++; + } + + /* Trace event */ + + stm32_i2c_traceevent(priv, I2CEVENT_MSG_HANDLING, priv->msgc); + } + + /* Note the event where we are on the last message and after the last + * byte is handled at the bottom of this function, as it terminates + * the repeated calls to the ISR. + */ + + /* I2C protocol logic + * + * I2C protocol logic follows. It's organized in an if else chain such that + * only one mode of operation is executed every time the ISR is called. + */ + + /* Address Handling + * + * Check if a start bit was set and transmit address with proper format. + * + * Note: + * On first call the start bit has been set by stm32_i2c_waitdone() + * Otherwise it will be set from this ISR. + * + * Remember that after a start bit an address has always to be sent. + */ + + if ((status & I2C_SR1_SB) != 0) + { + /* Start bit is set */ + + i2cinfo("Entering address handling, status = %i\n", status); + + /* Check for empty message (for robustness) */ + + if (priv->dcnt > 0) + { + /* Set POS bit to zero (can be up from a previous 2 byte receive) */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_POS, 0); + + /* ACK is the expected answer for N>=3 reads and writes */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_ACK); + + /* Send address byte with correct 8th bit set(for writing or reading) + * Transmission happens after having written to the data register + * STM32_I2C_DR + */ + + stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, + (priv->flags & I2C_M_TEN) ? + 0 :((priv->msgv->addr << 1) | (priv->flags & I2C_M_READ))); + + i2cinfo("Address sent. Addr=%#02x Write/Read bit=%i\n", + priv->msgv->addr, (priv->flags & I2C_M_READ)); + + /* Flag that address has just been sent */ + + priv->check_addr_ACK = true; + + stm32_i2c_traceevent(priv, I2CEVENT_SENDADDR, priv->msgv->addr); + } + else + { + /* TODO: untested!! */ + + i2cwarn(" An empty message has been detected, ignoring and passing to next message.\n"); + + /* Trace event */ + + stm32_i2c_traceevent(priv, I2CEVENT_EMPTY_MSG, 0); + + /* Set condition to activate msg handling */ + + priv->dcnt = -1; + + /* Restart ISR by setting an interrupt buffer bit */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); + } + } + + /* Address cleared event + * + * Check if the address cleared, i.e. the driver found a valid address. + * If a NACK was received the address is invalid, if an ACK was + * received the address is valid and transmission can continue. + */ + + /* Check for NACK after an address*/ + +#ifndef CONFIG_I2C_POLLED + /* When polling the i2c ISR it's not possible to determine when + * an address has been ACKed(i.e. the address is valid). + * + * The mechanism to deal a NACKed address is to wait for the I2C + * call to timeout (value defined in defconfig by one of the + * following: CONFIG_STM32_I2C_DYNTIMEO, CONFIG_STM32_I2CTIMEOSEC, + * CONFIG_STM32_I2CTIMEOMS, CONFIG_STM32_I2CTIMEOTICKS). + * + * To be safe in the case of a timeout/NACKed address a stop bit + * is set on the bus to clear it. In POLLED operation it's done + * stm32_i2c_process() after the call to stm32_i2c_sem_waitdone(). + * + * In ISR driven operation the stop bit in case of a NACKed address + * is set in the ISR itself. + * + * Note: this commentary is found in both places. + */ + + else if ((status & I2C_SR1_ADDR) == 0 && priv->check_addr_ACK) + { + i2cinfo("Invalid Address. Setting stop bit and clearing message\n"); + i2cinfo("status %i\n", status); + + /* Set condition to terminate msg chain transmission as address is invalid. */ + + priv->dcnt = -1; + priv->msgc = 0; + + i2cinfo("dcnt %i , msgc %i\n", priv->dcnt, priv->msgc); + + /* Reset flag to check for valid address */ + + priv->check_addr_ACK = false; + + /* Send stop bit to clear bus */ + + stm32_i2c_sendstop(priv); + + /* Trace event */ + + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); + } +#endif + + /* ACK in read mode, ACK in write mode is handled separately */ + + else if ((priv->flags & I2C_M_READ) != 0 && (status & I2C_SR1_ADDR) != 0 && + priv->check_addr_ACK) + { + /* Reset check addr flag as we are handling this event */ + + priv->check_addr_ACK = false; + + /* Enable RxNE and TxE buffers in order to receive one or multiple bytes */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN); + + /* Note: + * + * When reading a single byte the stop condition has to be set + * immediately after clearing the state flags, which happens + * when reading SR2(as SR1 has already been read). + * + * Similarly when reading 2 bytes the NACK bit has to be set as just + * after the clearing of the address. + */ + + if (priv->dcnt == 1 && priv->total_msg_len == 1) + { + /* this should only happen when receiving a message of length 1 */ + + i2cinfo("short read N=1: setting NACK\n"); + + /* Set POS bit to zero (can be up from a previous 2 byte receive) */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_POS, 0); + + /* Immediately set NACK */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0); + + /* Clear ADDR flag by reading SR2 and adding it to status */ + + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + + /* Send Stop */ + + stm32_i2c_sendstop(priv); + + i2cinfo("Address ACKed beginning data reception\n"); + i2cinfo("short read N=1: programming stop bit\n"); + + /* Trace */ + + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED_READ_1, 0); + } + else if (priv->dcnt == 2 && priv->total_msg_len == 2) + { + /* This should only happen when receiving a message of length 2 */ + + /* Set POS bit to zero (can be up from a previous 2 byte receive) */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_POS); + + /* Immediately set NACK */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0); + + /* Clear ADDR flag by reading SR2 and adding it to status */ + + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + + i2cinfo("Address ACKed beginning data reception\n"); + i2cinfo("short read N=2: programming NACK\n"); + + /* Trace */ + + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED_READ_2, 0); + } + else + { + i2cinfo("Address ACKed beginning data reception\n"); + + /* Clear ADDR flag by reading SR2 and adding it to status */ + + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + + /* Trace */ + + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, 0); + } + } + + /* Write mode + * + * Handles all write related I2C protocol logic. Also handles the + * ACK event after clearing the ADDR flag as the write has to + * begin immediately after. + */ + + else if ((priv->flags & (I2C_M_READ)) == 0 && + (status & (I2C_SR1_ADDR | I2C_SR1_TXE)) != 0) + { + /* The has cleared(ADDR is set, ACK was received after the address) + * or the transmit buffer is empty flag has been set(TxE) then we can + * transmit the next byte. + */ + + i2cinfo("Entering write mode dcnt = %i msgc = %i\n", + priv->dcnt, priv->msgc); + + /* Clear ADDR flag by reading SR2 and adding it to status */ + + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + + /* Address has cleared so don't check on next call */ + + priv->check_addr_ACK = false; + + /* Check if we have transmitted the whole message or we are after + * the last byte where the stop condition or else(according to the + * msg flags) has to be set. + */ + + if (priv->dcnt >= 1) + { + /* Transmitting message. Send byte == write data into write register */ + + stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, *priv->ptr++); + + /* Decrease current message length */ + + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); + priv->dcnt--; + + } + else if (priv->dcnt == 0) + { + + /* After last byte, check what to do based on next message flags */ + + if (priv->msgc == 0) + { + /* If last message send stop bit */ + + stm32_i2c_sendstop(priv); + i2cinfo("Stop sent dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); + + /* Decrease counter to get to next message */ + + priv->dcnt--; + i2cinfo("dcnt %i\n", priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, priv->dcnt); + } + + /* If there is a next message with no flags or the read flag + * a restart sequence has to be sent. + * Note msgv already points to the next message. + */ + + else if (priv->msgc > 0 && + (priv->msgv->flags == 0 || (priv->msgv[0].flags & I2C_M_READ) != 0)) + { + /* ACK ISR (for some reason this is necessary even though the + * sendstart should clear the BTF). + */ + + stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); + + /* Send start */ + + stm32_i2c_sendstart(priv); + + i2cinfo("Restart detected!\n"); + i2cinfo("Nextflag %i\n", priv->msgv[0].flags); + + /* Decrease counter to get to next message */ + + priv->dcnt--; + i2cinfo("dcnt %i\n", priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_RESTART, priv->dcnt); + } + + /* If there is a next message with the NO_RESTART flag + * do nothing. + */ + + else if (priv->msgc > 0 && ((priv->msgv->flags & I2C_M_NORESTART) != 0)) + { + /* Set condition to get to next message */ + + priv->dcnt =- 1; + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_NO_RESTART, priv->dcnt); + } + else + { + i2cinfo("Write mode: next message has an unrecognized flag.\n"); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_FLAG_ERROR, priv->msgv->flags); + } + } + else + { + i2cerr("Write mode error.\n"); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); + } + } + + /* Read mode + * + * Handles all read related I2C protocol logic. + * + * * * * * * * WARNING STM32F1xx HARDWARE ERRATA * * * * * * * + * source: https://github.com/hikob/openlab/blob/master/drivers/stm32/i2c.c + * + * RXNE-only events should not be handled since it sometimes + * fails. Only BTF & RXNE events should be handled (with the + * consequence of slowing down the transfer). + * + * It seems that when a RXNE interrupt is handled 'around' + * the end of the next byte reception, the DR register read + * is ignored by the i2c controller: it does not flush the + * DR with next byte + * + * Thus we read twice the same byte and we read effectively + * read one byte less than expected from the i2c slave point + * of view. + * + * Example: + * + we want to receive 6 bytes (B1 to B6) + * + the problem appear when reading B3 + * -> we read B1 B2 B3 B3 B4 B5(B3 twice) + * -> the i2c transfer was B1 B2 B3 B4 B5(B6 is not sent) + */ + + else if ((priv->flags & (I2C_M_READ)) != 0 && (status & I2C_SR1_RXNE) != 0) + { + /* When read flag is set and the receive buffer is not empty + *(RXNE is set) then the driver can read from the data register. + */ + + i2cinfo("Entering read mode dcnt = %i msgc = %i, status %i\n", + priv->dcnt, priv->msgc, status); + + /* Implementation of method 2 for receiving data following + * the stm32f1xx reference manual. + */ + + /* Case total message length = 1 */ + + if (priv->dcnt == 1 && priv->total_msg_len == 1) + { + i2cinfo("short read N=1: Read data from data register(DR)\n"); + + *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); + priv->dcnt = -1; + stm32_i2c_traceevent(priv, I2CEVENT_READ, 0); + } + + /* Case total message length = 2 */ + + else if (priv->dcnt == 2 && priv->total_msg_len == 2 && !(status & I2C_SR1_BTF)) + { + i2cinfo("short read N=2: DR full, SR empty. Waiting for more bytes.\n"); + stm32_i2c_traceevent(priv, I2CEVENT_READ_SR_EMPTY, 0); + } + else if (priv->dcnt == 2 && priv->total_msg_len == 2 && (status & I2C_SR1_BTF)) + { + i2cinfo("short read N=2: DR and SR full setting stop bit and reading twice\n"); + + stm32_i2c_sendstop(priv); + *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); + priv->dcnt--; + *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); + priv->dcnt--; + + /* Stop request already programmed so set dcnt for next message */ + + priv->dcnt--; + + /* Set trace */ + + stm32_i2c_traceevent(priv, I2CEVENT_READ_2, 0); + } + + /* Case total message length >= 3 */ + + else if (priv->dcnt >= 4 && priv->total_msg_len >= 3) + { + /* Read data from data register(DR). Note this clears the + * RXNE(receive buffer not empty) flag. + */ + + i2cinfo("Read data from data register(DR)\n"); + *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); + + /* Decrease current message length */ + + priv->dcnt--; + stm32_i2c_traceevent(priv, I2CEVENT_READ, 0); + } + else if (priv->dcnt == 3 && priv->total_msg_len >= 3 && !(status & I2C_SR1_BTF)) + { + i2cinfo("short read N=3: DR full, SR empty. Waiting for more bytes.\n"); + stm32_i2c_traceevent(priv, I2CEVENT_READ_SR_EMPTY, 0); + } + else if (priv->dcnt == 3 && (status & I2C_SR1_BTF) && priv->total_msg_len >= 3) + { + /* This means that we are reading dcnt 3 and there is already dcnt 2 in + * the shift register. + * This coincides with EV7_1 in the reference manual. + */ + + i2cinfo("Program NACK\n"); + i2cinfo("Read data from data register(DR) dcnt=3\n"); + + stm32_i2c_traceevent(priv, I2CEVENT_READ_3, priv->dcnt); + + /* Program NACK */ + + stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ACK, 0); + + /* Read dcnt = 3, to ensure a BTF event after having recieved + * in the shift register. + */ + + *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); + + /* Decrease current message length */ + + priv->dcnt--; + } + else if (priv->dcnt == 2 && priv->total_msg_len >= 3 && !(status & I2C_SR1_BTF)) + { + i2cinfo("short read N=3: DR full, SR empty. Waiting for more bytes.\n"); + stm32_i2c_traceevent(priv, I2CEVENT_READ_SR_EMPTY, 0); + } + else if (priv->dcnt == 2 && (status & I2C_SR1_BTF) && priv->total_msg_len >= 3) + { + i2cinfo("Program stop\n"); + i2cinfo("Read data from data register(DR) dcnt=2\n"); + i2cinfo("Read data from data register(SR) dcnt=1\n"); + i2cinfo("Setting condition to stop ISR dcnt = -1\n"); + + stm32_i2c_traceevent(priv, I2CEVENT_READ_3, priv->dcnt); + + /* Program stop */ + + stm32_i2c_sendstop(priv); + + /* read dcnt = 2 */ + + *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); + + /* read last byte dcnt=1 */ + + *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); + + /* Stop already sent will not get another interrupt set + * condition to stop ISR + */ + + priv->dcnt = -1; + } + + /* Error handling for read mode */ + + else + { + i2cinfo("I2C read mode no correct state detected\n"); + i2cinfo(" state %i, dcnt=%i\n", status, priv->dcnt); + + /* set condition to terminate ISR and wake waiting thread */ + priv->dcnt = -1; + priv->msgc = 0; + stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); + } + + /* Read rest of the state */ + + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + } + + /* Empty call handler + * + * Case to handle an empty call to the ISR where it only has to + * Shutdown + */ + + else if (priv->dcnt == -1 && priv->msgc == 0) + { + /* Read rest of the state */ + + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + i2cinfo("Empty call to ISR: Stopping ISR\n"); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); + } + + /* Error handler + * + * Gets triggered if the driver does not recognize a situation(state) + * it can deal with. + * This should not happen in interrupt based operation(i.e. when + * CONFIG_I2C_POLLED is not set in the defconfig file). + * During polled operation(i.e. CONFIG_I2C_POLLED=y in defconfig) + * this case should do nothing but tracing the event that the + * device wasn't ready yet. + */ + + else + { + #ifdef CONFIG_I2C_POLLED + stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); + #else + /* Read rest of the state */ + + status |= (stm32_i2c_getreg(priv, STM32_I2C_SR2_OFFSET) << 16); + + i2cinfo(" No correct state detected(start bit, read or write) \n"); + i2cinfo(" state %i\n", status); + + /* set condition to terminate ISR and wake waiting thread */ + + priv->dcnt = -1; + priv->msgc = 0; + stm32_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); + #endif + } + + /* Messages handling(2/2) + * + * Transmission of the whole message chain has been completed. We have to + * terminate the ISR and wake up stm32_i2c_process() that is waiting for + * the ISR cycle to handle the sending/receiving of the messages. + */ + + if (priv->dcnt == -1 && priv->msgc == 0) + { + i2cinfo("Shutting down I2C ISR\n"); + + stm32_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); + + /* Clear internal pointer to the message content. + * Good practice + done by last implementation when messages are finished + * (compatibility concerns) + */ + + priv->msgv = NULL; + + #ifdef CONFIG_I2C_POLLED + priv->intstate = INTSTATE_DONE; + #else + /* Clear all interrupts */ + + uint32_t regval; + regval = stm32_i2c_getreg(priv, STM32_I2C_CR2_OFFSET); + regval &= ~I2C_CR2_ALLINTS; + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, regval); + + /* Is there a thread waiting for this event(there should be) */ + + if (priv->intstate == INTSTATE_WAITING) + { + /* Yes.. inform the thread that the transfer is complete + * and wake it up. + */ + + sem_post(&priv->sem_isr); + priv->intstate = INTSTATE_DONE; + } + #endif + } + + return OK; +} + +/************************************************************************************ + * Name: stm32_i2c1_isr + * + * Description: + * I2C1 interrupt service routine + * + ************************************************************************************/ + +#ifndef CONFIG_I2C_POLLED +#ifdef CONFIG_STM32_I2C1 +static int stm32_i2c1_isr(int irq, void *context) +{ + return stm32_i2c_isr(&stm32_i2c1_priv); +} +#endif + +/************************************************************************************ + * Name: stm32_i2c2_isr + * + * Description: + * I2C2 interrupt service routine + * + ************************************************************************************/ + +#ifdef CONFIG_STM32_I2C2 +static int stm32_i2c2_isr(int irq, void *context) +{ + return stm32_i2c_isr(&stm32_i2c2_priv); +} +#endif + +/************************************************************************************ + * Name: stm32_i2c3_isr + * + * Description: + * I2C2 interrupt service routine + * + ************************************************************************************/ + +#ifdef CONFIG_STM32_I2C3 +static int stm32_i2c3_isr(int irq, void *context) +{ + return stm32_i2c_isr(&stm32_i2c3_priv); +} +#endif +#endif + +/************************************************************************************ + * Private Initialization and Deinitialization + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_i2c_init + * + * Description: + * Setup the I2C hardware, ready for operation with defaults + * + ************************************************************************************/ + +static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv) +{ + /* Power-up and configure GPIOs */ + + /* Enable power and reset the peripheral */ + + modifyreg32(STM32_RCC_APB1ENR, 0, priv->config->clk_bit); + modifyreg32(STM32_RCC_APB1RSTR, 0, priv->config->reset_bit); + modifyreg32(STM32_RCC_APB1RSTR, priv->config->reset_bit, 0); + + /* Configure pins */ + + if (stm32_configgpio(priv->config->scl_pin) < 0) + { + return ERROR; + } + + if (stm32_configgpio(priv->config->sda_pin) < 0) + { + stm32_unconfiggpio(priv->config->scl_pin); + return ERROR; + } + + /* Attach ISRs */ + +#ifndef CONFIG_I2C_POLLED + irq_attach(priv->config->ev_irq, priv->config->isr); + irq_attach(priv->config->er_irq, priv->config->isr); + up_enable_irq(priv->config->ev_irq); + up_enable_irq(priv->config->er_irq); +#endif + + /* Set peripheral frequency, where it must be at least 2 MHz for 100 kHz + * or 4 MHz for 400 kHz. This also disables all I2C interrupts. + */ + + stm32_i2c_putreg(priv, STM32_I2C_CR2_OFFSET, (STM32_PCLK1_FREQUENCY / 1000000)); + + /* Force a frequency update */ + + priv->frequency = 0; + + stm32_i2c_setclock(priv, 100000); + + /* Enable I2C */ + + stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE); + return OK; +} + +/************************************************************************************ + * Name: stm32_i2c_deinit + * + * Description: + * Shutdown the I2C hardware + * + ************************************************************************************/ + +static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv) +{ + /* Disable I2C */ + + stm32_i2c_putreg(priv, STM32_I2C_CR1_OFFSET, 0); + + /* Unconfigure GPIO pins */ + + stm32_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->sda_pin); + + /* Disable and detach interrupts */ + +#ifndef CONFIG_I2C_POLLED + up_disable_irq(priv->config->ev_irq); + up_disable_irq(priv->config->er_irq); + irq_detach(priv->config->ev_irq); + irq_detach(priv->config->er_irq); +#endif + + /* Disable clocking */ + + modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0); + return OK; +} + +/************************************************************************************ + * Device Driver Operations + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_i2c_transfer + * + * Description: + * Generic I2C transfer function + * + ************************************************************************************/ + +static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs, + int count) +{ + FAR struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; + stm32_i2c_sem_wait(priv); /* Ensure that address or flags don't change meanwhile */ + uint32_t status = 0; +#ifdef I2C1_FSMC_CONFLICT + uint32_t ahbenr; +#endif + int ret = 0; + + ASSERT(count); + +#ifdef I2C1_FSMC_CONFLICT + /* Disable FSMC that shares a pin with I2C1 (LBAR) */ + + ahbenr = stm32_i2c_disablefsmc(priv); + +#else + /* Wait for any STOP in progress. NOTE: If we have to disable the FSMC + * then we cannot do this at the top of the loop, unfortunately. The STOP + * will not complete normally if the FSMC is enabled. + */ + + stm32_i2c_sem_waitstop(priv); +#endif + + /* Clear any pending error interrupts */ + + stm32_i2c_putreg(priv, STM32_I2C_SR1_OFFSET, 0); + + /* "Note: When the STOP, START or PEC bit is set, the software must + * not perform any write access to I2C_CR1 before this bit is + * cleared by hardware. Otherwise there is a risk of setting a + * second STOP, START or PEC request." However, if the bits are + * not cleared by hardware, then we will have to do that from hardware. + */ + + stm32_i2c_clrstart(priv); + + /* Old transfers are done */ + + /* Reset ptr and dcnt to ensure an unexpected data interrupt doesn't + * overwrite stale data. + */ + + priv->dcnt = 0; + priv->ptr = NULL; + + priv->msgv = msgs; + priv->msgc = count; + + /* Reset I2C trace logic */ + + stm32_i2c_tracereset(priv); + + /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !) + * REVISIT: Note that the frequency is set only on the first message. + * This could be extended to support different transfer frequencies for + * each message segment. + */ + + stm32_i2c_setclock(priv, msgs->frequency); + + /* Trigger start condition, then the process moves into the ISR. I2C + * interrupts will be enabled within stm32_i2c_waitdone(). + */ + + priv->dcnt = -1; + priv->status = 0; + stm32_i2c_sendstart(priv); + + /* Wait for an ISR, if there was a timeout, fetch latest status to get + * the BUSY flag. + */ + + if (stm32_i2c_sem_waitdone(priv) < 0) + { + status = stm32_i2c_getstatus(priv); + ret = -ETIMEDOUT; + + i2cerr("ERROR: Timed out: CR1: 0x%04x status: 0x%08x\n", + stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET), status); + + /* "Note: When the STOP, START or PEC bit is set, the software must + * not perform any write access to I2C_CR1 before this bit is + * cleared by hardware. Otherwise there is a risk of setting a + * second STOP, START or PEC request." + */ + + stm32_i2c_clrstart(priv); + + /* Clear busy flag in case of timeout */ + + status = priv->status & 0xffff; + } + else + { + /* clear SR2 (BUSY flag) as we've done successfully */ + + status = priv->status & 0xffff; + } + + /* Check for error status conditions */ + + if ((status & I2C_SR1_ERRORMASK) != 0) + { + /* I2C_SR1_ERRORMASK is the 'OR' of the following individual bits: */ + + if (status & I2C_SR1_BERR) + { + /* Bus Error */ + + ret = -EIO; + } + else if (status & I2C_SR1_ARLO) + { + /* Arbitration Lost (master mode) */ + + ret = -EAGAIN; + } + else if (status & I2C_SR1_AF) + { + /* Acknowledge Failure */ + + ret = -ENXIO; + } + else if (status & I2C_SR1_OVR) + { + /* Overrun/Underrun */ + + ret = -EIO; + } + else if (status & I2C_SR1_PECERR) + { + /* PEC Error in reception */ + + ret = -EPROTO; + } + else if (status & I2C_SR1_TIMEOUT) + { + /* Timeout or Tlow Error */ + + ret = -ETIME; + } + + /* This is not an error and should never happen since SMBus is not enabled */ + + else /* if (status & I2C_SR1_SMBALERT) */ + { + /* SMBus alert is an optional signal with an interrupt line for devices + * that want to trade their ability to master for a pin. + */ + + ret = -EINTR; + } + } + + /* This is not an error, but should not happen. The BUSY signal can hang, + * however, if there are unhealthy devices on the bus that need to be reset. + * NOTE: We will only see this busy indication if stm32_i2c_sem_waitdone() + * fails above; Otherwise it is cleared. + */ + + else if ((status & (I2C_SR2_BUSY << 16)) != 0) + { + /* I2C Bus is for some reason busy */ + + ret = -EBUSY; + } + + /* Dump the trace result */ + + stm32_i2c_tracedump(priv); + +#ifdef I2C1_FSMC_CONFLICT + /* Wait for any STOP in progress. NOTE: If we have to disable the FSMC + * then we cannot do this at the top of the loop, unfortunately. The STOP + * will not complete normally if the FSMC is enabled. + */ + + stm32_i2c_sem_waitstop(priv); + + /* Re-enable the FSMC */ + + stm32_i2c_enablefsmc(ahbenr); +#endif + + /* Ensure that any ISR happening after we finish can't overwrite any user data */ + + priv->dcnt = 0; + priv->ptr = NULL; + + stm32_i2c_sem_post(priv); + return ret; +} + +/************************************************************************************ + * Name: stm32_i2c_reset + * + * Description: + * Perform an I2C bus reset in an attempt to break loose stuck I2C devices. + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ************************************************************************************/ + +#ifdef CONFIG_I2C_RESET +static int stm32_i2c_reset(FAR struct i2c_master_s *dev) +{ + FAR struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; + unsigned int clock_count; + unsigned int stretch_count; + uint32_t scl_gpio; + uint32_t sda_gpio; + uint32_t frequency; + int ret = ERROR; + + ASSERT(dev); + + /* Our caller must own a ref */ + + ASSERT(priv->refs > 0); + + /* Lock out other clients */ + + stm32_i2c_sem_wait(priv); + + /* Save the current frequency */ + + frequency = priv->frequency; + + /* De-init the port */ + + stm32_i2c_deinit(priv); + + /* Use GPIO configuration to un-wedge the bus */ + + scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin); + sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin); + + stm32_configgpio(scl_gpio); + stm32_configgpio(sda_gpio); + + /* Let SDA go high */ + + stm32_gpiowrite(sda_gpio, 1); + + /* Clock the bus until any slaves currently driving it let it go. */ + + clock_count = 0; + while (!stm32_gpioread(sda_gpio)) + { + /* Give up if we have tried too hard */ + + if (clock_count++ > 10) + { + goto out; + } + + /* Sniff to make sure that clock stretching has finished. + * + * If the bus never relaxes, the reset has failed. + */ + + stretch_count = 0; + while (!stm32_gpioread(scl_gpio)) + { + /* Give up if we have tried too hard */ + + if (stretch_count++ > 10) + { + goto out; + } + + up_udelay(10); + } + + /* Drive SCL low */ + + stm32_gpiowrite(scl_gpio, 0); + up_udelay(10); + + /* Drive SCL high again */ + + stm32_gpiowrite(scl_gpio, 1); + up_udelay(10); + } + + /* Generate a start followed by a stop to reset slave + * state machines. + */ + + stm32_gpiowrite(sda_gpio, 0); + up_udelay(10); + stm32_gpiowrite(scl_gpio, 0); + up_udelay(10); + stm32_gpiowrite(scl_gpio, 1); + up_udelay(10); + stm32_gpiowrite(sda_gpio, 1); + up_udelay(10); + + /* Revert the GPIO configuration. */ + + stm32_unconfiggpio(sda_gpio); + stm32_unconfiggpio(scl_gpio); + + /* Re-init the port */ + + stm32_i2c_init(priv); + + /* Restore the frequency */ + + stm32_i2c_setclock(priv, frequency); + ret = OK; + +out: + + /* Release the port for re-use by other clients */ + + stm32_i2c_sem_post(priv); + return ret; +} +#endif /* CONFIG_I2C_RESET */ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_i2cbus_initialize + * + * Description: + * Initialize one I2C bus + * + ************************************************************************************/ + +FAR struct i2c_master_s *stm32_i2cbus_initialize(int port) +{ + struct stm32_i2c_priv_s * priv = NULL; + irqstate_t flags; + +#if STM32_PCLK1_FREQUENCY < 4000000 +# warning STM32_I2C_INIT: Peripheral clock must be at least 4 MHz to support 400 kHz operation. +#endif + +#if STM32_PCLK1_FREQUENCY < 2000000 +# warning STM32_I2C_INIT: Peripheral clock must be at least 2 MHz to support 100 kHz operation. + return NULL; +#endif + + /* Get I2C private structure */ + + switch (port) + { +#ifdef CONFIG_STM32_I2C1 + case 1: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; + break; +#endif +#ifdef CONFIG_STM32_I2C2 + case 2: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; + break; +#endif +#ifdef CONFIG_STM32_I2C3 + case 3: + priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; + break; +#endif + default: + return NULL; + } + + /* Initialize private data for the first time, increment reference count, + * power-up hardware and configure GPIOs. + */ + + flags = enter_critical_section(); + + if ((volatile int)priv->refs++ == 0) + { + stm32_i2c_sem_init(priv); + stm32_i2c_init(priv); + } + + leave_critical_section(flags); + return (struct i2c_master_s *)priv; +} + +/************************************************************************************ + * Name: stm32_i2cbus_uninitialize + * + * Description: + * Uninitialize an I2C bus + * + ************************************************************************************/ + +int stm32_i2cbus_uninitialize(FAR struct i2c_master_s *dev) +{ + FAR struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev; + irqstate_t flags; + + ASSERT(dev); + + /* Decrement reference count and check for underflow */ + + if (priv->refs == 0) + { + return ERROR; + } + + flags = enter_critical_section(); + + if (--priv->refs) + { + leave_critical_section(flags); + return OK; + } + + leave_critical_section(flags); + + /* Disable power and other HW resource (GPIO's) */ + + stm32_i2c_deinit(priv); + + /* Release unused resources */ + + stm32_i2c_sem_destroy(priv); + return OK; +} + +#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F40XX */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */ -- GitLab From 9be23d0c76a0eec605c4e3ae9d5b94ff02eb0fdf Mon Sep 17 00:00:00 2001 From: Sebastien Lorquet Date: Tue, 25 Oct 2016 10:53:24 +0200 Subject: [PATCH 203/734] Fix i2c devices rcc registers --- arch/arm/src/stm32l4/stm32l4_i2c.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.c b/arch/arm/src/stm32l4/stm32l4_i2c.c index ce6c91b677..278885fc58 100644 --- a/arch/arm/src/stm32l4/stm32l4_i2c.c +++ b/arch/arm/src/stm32l4/stm32l4_i2c.c @@ -356,8 +356,8 @@ struct stm32l4_i2c_priv_s stm32l4_i2c1_priv = static const struct stm32l4_i2c_config_s stm32l4_i2c2_config = { .base = STM32L4_I2C2_BASE, - .clk_bit = RCC_APB1ENR_I2C2EN, - .reset_bit = RCC_APB1RSTR_I2C2RST, + .clk_bit = RCC_APB1ENR1_I2C2EN, + .reset_bit = RCC_APB1RSTR1_I2C2RST, .scl_pin = GPIO_I2C2_SCL, .sda_pin = GPIO_I2C2_SDA, #ifndef CONFIG_I2C_POLLED @@ -386,8 +386,8 @@ struct stm32l4_i2c_priv_s stm32l4_i2c2_priv = static const struct stm32l4_i2c_config_s stm32l4_i2c3_config = { .base = STM32L4_I2C3_BASE, - .clk_bit = RCC_APB1ENR_I2C3EN, - .reset_bit = RCC_APB1RSTR_I2C3RST, + .clk_bit = RCC_APB1ENR1_I2C3EN, + .reset_bit = RCC_APB1RSTR1_I2C3RST, .scl_pin = GPIO_I2C3_SCL, .sda_pin = GPIO_I2C3_SDA, #ifndef CONFIG_I2C_POLLED -- GitLab From 27920eeae9fee8dce335ed83600f23115ef9ce18 Mon Sep 17 00:00:00 2001 From: Sebastien Lorquet Date: Tue, 25 Oct 2016 10:55:25 +0200 Subject: [PATCH 204/734] Enable and renames for 32l4 UARTs 4 and 5 --- arch/arm/src/stm32l4/Kconfig | 13 +++++++++---- arch/arm/src/stm32l4/stm32l4_serial.c | 2 +- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index b6eba519cd..1192f839f8 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -45,6 +45,8 @@ config STM32L4_STM32L476XX select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM select STM32L4_HAVE_USART3 + select STM32L4_HAVE_UART4 + select STM32L4_HAVE_UART5 config STM32L4_STM32L486XX bool @@ -53,6 +55,9 @@ config STM32L4_STM32L486XX select ARCH_HAVE_DPFPU # REVISIT select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM + select STM32L4_HAVE_USART3 + select STM32L4_HAVE_UART4 + select STM32L4_HAVE_UART5 select STM32L4_FLASH_1024KB choice @@ -425,7 +430,7 @@ config STM32L4_USART3 config STM32L4_UART4 bool "UART4" default n - depends on STM32L4_HAVE_USART4 + depends on STM32L4_HAVE_UART4 select ARCH_HAVE_SERIAL_TERMIOS select UART4_SERIALDRIVER select STM32L4_USART @@ -433,7 +438,7 @@ config STM32L4_UART4 config STM32L4_UART5 bool "UART5" default n - depends on STM32L4_HAVE_USART5 + depends on STM32L4_HAVE_UART5 select ARCH_HAVE_SERIAL_TERMIOS select UART5_SERIALDRIVER select STM32L4_USART @@ -2507,11 +2512,11 @@ config STM32L4_HAVE_USART3 bool default n -config STM32L4_HAVE_USART4 +config STM32L4_HAVE_UART4 bool default n -config STM32L4_HAVE_USART5 +config STM32L4_HAVE_UART5 bool default n diff --git a/arch/arm/src/stm32l4/stm32l4_serial.c b/arch/arm/src/stm32l4/stm32l4_serial.c index e85e73a3e3..8e4b8d3bee 100644 --- a/arch/arm/src/stm32l4/stm32l4_serial.c +++ b/arch/arm/src/stm32l4/stm32l4_serial.c @@ -96,7 +96,7 @@ # if defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) # ifndef CONFIG_STM32L4_DMA2 -# error STM32L4 USART4/5 receive DMA requires CONFIG_STM32L4_DMA2 +# error STM32L4 UART4/5 receive DMA requires CONFIG_STM32L4_DMA2 # endif # endif -- GitLab From c457e26f2a3a02f96b2b0b4f342f675612bb0460 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 25 Oct 2016 08:34:25 -0600 Subject: [PATCH 205/734] ESP32: Add UART register definition file --- arch/xtensa/src/esp32/chip/esp32_uart.h | 1668 +++++++++++++++++++++++ 1 file changed, 1668 insertions(+) create mode 100644 arch/xtensa/src/esp32/chip/esp32_uart.h diff --git a/arch/xtensa/src/esp32/chip/esp32_uart.h b/arch/xtensa/src/esp32/chip/esp32_uart.h new file mode 100644 index 0000000000..f13a5c234c --- /dev/null +++ b/arch/xtensa/src/esp32/chip/esp32_uart.h @@ -0,0 +1,1668 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/chip/esp32_uart.h + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Espressif Systems: + * + * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_UART_H +#define __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_UART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "chip/esp32_soc.h" + +/**************************************************************************** + * Pre-processor Macros + ****************************************************************************/ + +#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000 + (i > 1 ? 0xe000 : 0)) + +#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) + +/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/* Description: This register stores one byte data read by rx fifo.*/ + +#define UART_RXFIFO_RD_BYTE 0x000000FF +#define UART_RXFIFO_RD_BYTE_M ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S)) +#define UART_RXFIFO_RD_BYTE_V 0xFF +#define UART_RXFIFO_RD_BYTE_S 0 + +#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) + +/* UART_AT_CMD_CHAR_DET_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/* Description: This interrupt raw bit turns to high level when receiver + * detects the configured at_cmd chars. + */ + +#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 + +/* UART_RS485_CLASH_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/* Description: This interrupt raw bit turns to high level when rs485 detects + * the clash between transmitter and receiver. + */ + +#define UART_RS485_CLASH_INT_RAW (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_M (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_V 0x1 +#define UART_RS485_CLASH_INT_RAW_S 17 + +/* UART_RS485_FRM_ERR_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/* Description: This interrupt raw bit turns to high level when rs485 detects + * the data frame error. + */ + +#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_V 0x1 +#define UART_RS485_FRM_ERR_INT_RAW_S 16 + +/* UART_RS485_PARITY_ERR_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/* Description: This interrupt raw bit turns to high level when rs485 + * detects the parity error. + */ + +#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_V 0x1 +#define UART_RS485_PARITY_ERR_INT_RAW_S 15 + +/* UART_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/* Description: This interrupt raw bit turns to high level when transmitter + * has send all the data in fifo. + */ + +#define UART_TX_DONE_INT_RAW (BIT(14)) +#define UART_TX_DONE_INT_RAW_M (BIT(14)) +#define UART_TX_DONE_INT_RAW_V 0x1 +#define UART_TX_DONE_INT_RAW_S 14 + +/* UART_TX_BRK_IDLE_DONE_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/* Description: This interrupt raw bit turns to high level when transmitter + * has kept the shortest duration after the last data has been send. + */ + +#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 + +/* UART_TX_BRK_DONE_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/* Description: This interrupt raw bit turns to high level when transmitter + * completes sending 0 after all the datas in transmitter's fifo are send. + */ + +#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_V 0x1 +#define UART_TX_BRK_DONE_INT_RAW_S 12 + +/* UART_GLITCH_DET_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/* Description: This interrupt raw bit turns to high level when receiver + * detects the start bit. + */ + +#define UART_GLITCH_DET_INT_RAW (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_M (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_V 0x1 +#define UART_GLITCH_DET_INT_RAW_S 11 + +/* UART_SW_XOFF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/* Description: This interrupt raw bit turns to high level when receiver + * receives xon char with uart_sw_flow_con_en is set to 1. + */ + +#define UART_SW_XOFF_INT_RAW (BIT(10)) +#define UART_SW_XOFF_INT_RAW_M (BIT(10)) +#define UART_SW_XOFF_INT_RAW_V 0x1 +#define UART_SW_XOFF_INT_RAW_S 10 + +/* UART_SW_XON_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/* Description: This interrupt raw bit turns to high level when receiver + * receives xoff char with uart_sw_flow_con_en is set to 1. + */ + +#define UART_SW_XON_INT_RAW (BIT(9)) +#define UART_SW_XON_INT_RAW_M (BIT(9)) +#define UART_SW_XON_INT_RAW_V 0x1 +#define UART_SW_XON_INT_RAW_S 9 + +/* UART_RXFIFO_TOUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/* Description: This interrupt raw bit turns to high level when receiver + * takes more time than rx_tout_thrhd to receive a byte. + */ + +#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_V 0x1 +#define UART_RXFIFO_TOUT_INT_RAW_S 8 + +/* UART_BRK_DET_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/* Description: This interrupt raw bit turns to high level when receiver + * detects the 0 after the stop bit. + */ + +#define UART_BRK_DET_INT_RAW (BIT(7)) +#define UART_BRK_DET_INT_RAW_M (BIT(7)) +#define UART_BRK_DET_INT_RAW_V 0x1 +#define UART_BRK_DET_INT_RAW_S 7 + +/* UART_CTS_CHG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/* Description: This interrupt raw bit turns to high level when receiver + * detects the edge change of ctsn signal. + */ + +#define UART_CTS_CHG_INT_RAW (BIT(6)) +#define UART_CTS_CHG_INT_RAW_M (BIT(6)) +#define UART_CTS_CHG_INT_RAW_V 0x1 +#define UART_CTS_CHG_INT_RAW_S 6 + +/* UART_DSR_CHG_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/* Description: This interrupt raw bit turns to high level when receiver + * detects the edge change of dsrn signal. + */ + +#define UART_DSR_CHG_INT_RAW (BIT(5)) +#define UART_DSR_CHG_INT_RAW_M (BIT(5)) +#define UART_DSR_CHG_INT_RAW_V 0x1 +#define UART_DSR_CHG_INT_RAW_S 5 + +/* UART_RXFIFO_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/* Description: This interrupt raw bit turns to high level when receiver + * receives more data than the fifo can store. + */ + +#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_V 0x1 +#define UART_RXFIFO_OVF_INT_RAW_S 4 + +/* UART_FRM_ERR_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/* Description: This interrupt raw bit turns to high level when receiver + * detects data's frame error. + */ + +#define UART_FRM_ERR_INT_RAW (BIT(3)) +#define UART_FRM_ERR_INT_RAW_M (BIT(3)) +#define UART_FRM_ERR_INT_RAW_V 0x1 +#define UART_FRM_ERR_INT_RAW_S 3 + +/* UART_PARITY_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/* Description: This interrupt raw bit turns to high level when receiver + * detects the parity error of data. + */ + +#define UART_PARITY_ERR_INT_RAW (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_M (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_V 0x1 +#define UART_PARITY_ERR_INT_RAW_S 2 + +/* UART_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/* Description: This interrupt raw bit turns to high level when the amount + * of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt). + */ + +#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_V 0x1 +#define UART_TXFIFO_EMPTY_INT_RAW_S 1 + +/* UART_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: This interrupt raw bit turns to high level when receiver + * receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd). + */ + +#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_V 0x1 +#define UART_RXFIFO_FULL_INT_RAW_S 0 + +#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) + +/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/* Description: This is the status bit for at_cmd_det_int_raw when + * at_cmd_char_det_int_ena is set to 1. + */ + +#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 + +/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/* Description: This is the status bit for rs485_clash_int_raw when + * rs485_clash_int_ena is set to 1. + */ + +#define UART_RS485_CLASH_INT_ST (BIT(17)) +#define UART_RS485_CLASH_INT_ST_M (BIT(17)) +#define UART_RS485_CLASH_INT_ST_V 0x1 +#define UART_RS485_CLASH_INT_ST_S 17 + +/* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/* Description: This is the status bit for rs485_fm_err_int_raw when + * rs485_fm_err_int_ena is set to 1. + */ + +#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_V 0x1 +#define UART_RS485_FRM_ERR_INT_ST_S 16 + +/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/* Description: This is the status bit for rs485_parity_err_int_raw when + * rs485_parity_int_ena is set to 1. + */ + +#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_V 0x1 +#define UART_RS485_PARITY_ERR_INT_ST_S 15 + +/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/* Description: This is the status bit for tx_done_int_raw when + * tx_done_int_ena is set to 1. + */ + +#define UART_TX_DONE_INT_ST (BIT(14)) +#define UART_TX_DONE_INT_ST_M (BIT(14)) +#define UART_TX_DONE_INT_ST_V 0x1 +#define UART_TX_DONE_INT_ST_S 14 + +/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/* Description: This is the stauts bit for tx_brk_idle_done_int_raw when + * tx_brk_idle_done_int_ena is set to 1. + */ + +#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 + +/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/* Description: This is the status bit for tx_brk_done_int_raw when + * tx_brk_done_int_ena is set to 1. + */ + +#define UART_TX_BRK_DONE_INT_ST (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_V 0x1 +#define UART_TX_BRK_DONE_INT_ST_S 12 + +/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/* Description: This is the status bit for glitch_det_int_raw when + * glitch_det_int_ena is set to 1. + */ + +#define UART_GLITCH_DET_INT_ST (BIT(11)) +#define UART_GLITCH_DET_INT_ST_M (BIT(11)) +#define UART_GLITCH_DET_INT_ST_V 0x1 +#define UART_GLITCH_DET_INT_ST_S 11 + +/* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/* Description: This is the status bit for sw_xoff_int_raw when + * sw_xoff_int_ena is set to 1. + */ + +#define UART_SW_XOFF_INT_ST (BIT(10)) +#define UART_SW_XOFF_INT_ST_M (BIT(10)) +#define UART_SW_XOFF_INT_ST_V 0x1 +#define UART_SW_XOFF_INT_ST_S 10 + +/* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/* Description: This is the status bit for sw_xon_int_raw when + * sw_xon_int_ena is set to 1. + */ + +#define UART_SW_XON_INT_ST (BIT(9)) +#define UART_SW_XON_INT_ST_M (BIT(9)) +#define UART_SW_XON_INT_ST_V 0x1 +#define UART_SW_XON_INT_ST_S 9 + +/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/* Description: This is the status bit for rxfifo_tout_int_raw when + * rxfifo_tout_int_ena is set to 1. + */ + +#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_V 0x1 +#define UART_RXFIFO_TOUT_INT_ST_S 8 + +/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/* Description: This is the status bit for brk_det_int_raw when + * brk_det_int_ena is set to 1. + */ + +#define UART_BRK_DET_INT_ST (BIT(7)) +#define UART_BRK_DET_INT_ST_M (BIT(7)) +#define UART_BRK_DET_INT_ST_V 0x1 +#define UART_BRK_DET_INT_ST_S 7 + +/* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/* Description: This is the status bit for cts_chg_int_raw when + * cts_chg_int_ena is set to 1. + */ + +#define UART_CTS_CHG_INT_ST (BIT(6)) +#define UART_CTS_CHG_INT_ST_M (BIT(6)) +#define UART_CTS_CHG_INT_ST_V 0x1 +#define UART_CTS_CHG_INT_ST_S 6 + +/* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/* Description: This is the status bit for dsr_chg_int_raw when + * dsr_chg_int_ena is set to 1. + */ + +#define UART_DSR_CHG_INT_ST (BIT(5)) +#define UART_DSR_CHG_INT_ST_M (BIT(5)) +#define UART_DSR_CHG_INT_ST_V 0x1 +#define UART_DSR_CHG_INT_ST_S 5 + +/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/* Description: This is the status bit for rxfifo_ovf_int_raw when + * rxfifo_ovf_int_ena is set to 1. + */ + +#define UART_RXFIFO_OVF_INT_ST (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_V 0x1 +#define UART_RXFIFO_OVF_INT_ST_S 4 + +/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/* Description: This is the status bit for frm_err_int_raw when + * fm_err_int_ena is set to 1. + */ + +#define UART_FRM_ERR_INT_ST (BIT(3)) +#define UART_FRM_ERR_INT_ST_M (BIT(3)) +#define UART_FRM_ERR_INT_ST_V 0x1 +#define UART_FRM_ERR_INT_ST_S 3 + +/* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/* Description: This is the status bit for parity_err_int_raw when + * parity_err_int_ena is set to 1. + */ + +#define UART_PARITY_ERR_INT_ST (BIT(2)) +#define UART_PARITY_ERR_INT_ST_M (BIT(2)) +#define UART_PARITY_ERR_INT_ST_V 0x1 +#define UART_PARITY_ERR_INT_ST_S 2 + +/* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/* Description: This is the status bit for txfifo_empty_int_raw when + * txfifo_empty_int_ena is set to 1. + */ + +#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_V 0x1 +#define UART_TXFIFO_EMPTY_INT_ST_S 1 + +/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: This is the status bit for rxfifo_full_int_raw when + * rxfifo_full_int_ena is set to 1.*/ + +#define UART_RXFIFO_FULL_INT_ST (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_V 0x1 +#define UART_RXFIFO_FULL_INT_ST_S 0 + +#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xC) + +/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/* Description: This is the enable bit for at_cmd_char_det_int_st register.*/ + +#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 + +/* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/* Description: This is the enable bit for rs485_clash_int_st register.*/ + +#define UART_RS485_CLASH_INT_ENA (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_M (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_V 0x1 +#define UART_RS485_CLASH_INT_ENA_S 17 + +/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/* Description: This is the enable bit for rs485_parity_err_int_st register.*/ + +#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_V 0x1 +#define UART_RS485_FRM_ERR_INT_ENA_S 16 + +/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/* Description: This is the enable bit for rs485_parity_err_int_st register.*/ + +#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_V 0x1 +#define UART_RS485_PARITY_ERR_INT_ENA_S 15 + +/* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/* Description: This is the enable bit for tx_done_int_st register.*/ + +#define UART_TX_DONE_INT_ENA (BIT(14)) +#define UART_TX_DONE_INT_ENA_M (BIT(14)) +#define UART_TX_DONE_INT_ENA_V 0x1 +#define UART_TX_DONE_INT_ENA_S 14 + +/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/* Description: This is the enable bit for tx_brk_idle_done_int_st register.*/ + +#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 + +/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/* Description: This is the enable bit for tx_brk_done_int_st register.*/ + +#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_V 0x1 +#define UART_TX_BRK_DONE_INT_ENA_S 12 + +/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/* Description: This is the enable bit for glitch_det_int_st register.*/ + +#define UART_GLITCH_DET_INT_ENA (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_M (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_V 0x1 +#define UART_GLITCH_DET_INT_ENA_S 11 + +/* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/* Description: This is the enable bit for sw_xoff_int_st register.*/ + +#define UART_SW_XOFF_INT_ENA (BIT(10)) +#define UART_SW_XOFF_INT_ENA_M (BIT(10)) +#define UART_SW_XOFF_INT_ENA_V 0x1 +#define UART_SW_XOFF_INT_ENA_S 10 + +/* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/* Description: This is the enable bit for sw_xon_int_st register.*/ + +#define UART_SW_XON_INT_ENA (BIT(9)) +#define UART_SW_XON_INT_ENA_M (BIT(9)) +#define UART_SW_XON_INT_ENA_V 0x1 +#define UART_SW_XON_INT_ENA_S 9 + +/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/* Description: This is the enable bit for rxfifo_tout_int_st register.*/ + +#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_V 0x1 +#define UART_RXFIFO_TOUT_INT_ENA_S 8 + +/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/* Description: This is the enable bit for brk_det_int_st register.*/ + +#define UART_BRK_DET_INT_ENA (BIT(7)) +#define UART_BRK_DET_INT_ENA_M (BIT(7)) +#define UART_BRK_DET_INT_ENA_V 0x1 +#define UART_BRK_DET_INT_ENA_S 7 + +/* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/* Description: This is the enable bit for cts_chg_int_st register.*/ + +#define UART_CTS_CHG_INT_ENA (BIT(6)) +#define UART_CTS_CHG_INT_ENA_M (BIT(6)) +#define UART_CTS_CHG_INT_ENA_V 0x1 +#define UART_CTS_CHG_INT_ENA_S 6 + +/* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/* Description: This is the enable bit for dsr_chg_int_st register.*/ + +#define UART_DSR_CHG_INT_ENA (BIT(5)) +#define UART_DSR_CHG_INT_ENA_M (BIT(5)) +#define UART_DSR_CHG_INT_ENA_V 0x1 +#define UART_DSR_CHG_INT_ENA_S 5 + +/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/* Description: This is the enable bit for rxfifo_ovf_int_st register.*/ + +#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_V 0x1 +#define UART_RXFIFO_OVF_INT_ENA_S 4 + +/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/* Description: This is the enable bit for frm_err_int_st register.*/ + +#define UART_FRM_ERR_INT_ENA (BIT(3)) +#define UART_FRM_ERR_INT_ENA_M (BIT(3)) +#define UART_FRM_ERR_INT_ENA_V 0x1 +#define UART_FRM_ERR_INT_ENA_S 3 + +/* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/* Description: This is the enable bit for parity_err_int_st register.*/ + +#define UART_PARITY_ERR_INT_ENA (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_M (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_V 0x1 +#define UART_PARITY_ERR_INT_ENA_S 2 + +/* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/* Description: This is the enable bit for rxfifo_full_int_st register.*/ + +#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_V 0x1 +#define UART_TXFIFO_EMPTY_INT_ENA_S 1 + +/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: This is the enable bit for rxfifo_full_int_st register.*/ + +#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_V 0x1 +#define UART_RXFIFO_FULL_INT_ENA_S 0 + +#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) + +/* UART_AT_CMD_CHAR_DET_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/* Description: Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ + +#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 + +/* UART_RS485_CLASH_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/* Description: Set this bit to clear the rs485_clash_int_raw interrupt.*/ + +#define UART_RS485_CLASH_INT_CLR (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_M (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_V 0x1 +#define UART_RS485_CLASH_INT_CLR_S 17 + +/* UART_RS485_FRM_ERR_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/* Description: Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ + +#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_V 0x1 +#define UART_RS485_FRM_ERR_INT_CLR_S 16 + +/* UART_RS485_PARITY_ERR_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/* Description: Set this bit to clear the rs485_parity_err_int_raw + * interrupt. + */ + +#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_V 0x1 +#define UART_RS485_PARITY_ERR_INT_CLR_S 15 + +/* UART_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/* Description: Set this bit to clear the tx_done_int_raw interrupt.*/ + +#define UART_TX_DONE_INT_CLR (BIT(14)) +#define UART_TX_DONE_INT_CLR_M (BIT(14)) +#define UART_TX_DONE_INT_CLR_V 0x1 +#define UART_TX_DONE_INT_CLR_S 14 + +/* UART_TX_BRK_IDLE_DONE_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/* Description: Set this bit to clear the tx_brk_idle_done_int_raw + * interrupt. + */ + +#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 + +/* UART_TX_BRK_DONE_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/* Description: Set this bit to clear the tx_brk_done_int_raw interrupt. */ + +#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_V 0x1 +#define UART_TX_BRK_DONE_INT_CLR_S 12 + +/* UART_GLITCH_DET_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/* Description: Set this bit to clear the glitch_det_int_raw interrupt.*/ + +#define UART_GLITCH_DET_INT_CLR (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_M (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_V 0x1 +#define UART_GLITCH_DET_INT_CLR_S 11 + +/* UART_SW_XOFF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/* Description: Set this bit to clear the sw_xon_int_raw interrupt.*/ + +#define UART_SW_XOFF_INT_CLR (BIT(10)) +#define UART_SW_XOFF_INT_CLR_M (BIT(10)) +#define UART_SW_XOFF_INT_CLR_V 0x1 +#define UART_SW_XOFF_INT_CLR_S 10 + +/* UART_SW_XON_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/* Description: Set this bit to clear the sw_xon_int_raw interrupt.*/ + +#define UART_SW_XON_INT_CLR (BIT(9)) +#define UART_SW_XON_INT_CLR_M (BIT(9)) +#define UART_SW_XON_INT_CLR_V 0x1 +#define UART_SW_XON_INT_CLR_S 9 + +/* UART_RXFIFO_TOUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/* Description: Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ + +#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_V 0x1 +#define UART_RXFIFO_TOUT_INT_CLR_S 8 + +/* UART_BRK_DET_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/* Description: Set this bit to clear the brk_det_int_raw interrupt.*/ + +#define UART_BRK_DET_INT_CLR (BIT(7)) +#define UART_BRK_DET_INT_CLR_M (BIT(7)) +#define UART_BRK_DET_INT_CLR_V 0x1 +#define UART_BRK_DET_INT_CLR_S 7 + +/* UART_CTS_CHG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/* Description: Set this bit to clear the cts_chg_int_raw interrupt.*/ + +#define UART_CTS_CHG_INT_CLR (BIT(6)) +#define UART_CTS_CHG_INT_CLR_M (BIT(6)) +#define UART_CTS_CHG_INT_CLR_V 0x1 +#define UART_CTS_CHG_INT_CLR_S 6 + +/* UART_DSR_CHG_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/* Description: Set this bit to clear the dsr_chg_int_raw interrupt.*/ + +#define UART_DSR_CHG_INT_CLR (BIT(5)) +#define UART_DSR_CHG_INT_CLR_M (BIT(5)) +#define UART_DSR_CHG_INT_CLR_V 0x1 +#define UART_DSR_CHG_INT_CLR_S 5 + +/* UART_RXFIFO_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/* Description: Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ + +#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_V 0x1 +#define UART_RXFIFO_OVF_INT_CLR_S 4 + +/* UART_FRM_ERR_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/* Description: Set this bit to clear frm_err_int_raw interrupt.*/ + +#define UART_FRM_ERR_INT_CLR (BIT(3)) +#define UART_FRM_ERR_INT_CLR_M (BIT(3)) +#define UART_FRM_ERR_INT_CLR_V 0x1 +#define UART_FRM_ERR_INT_CLR_S 3 + +/* UART_PARITY_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/* Description: Set this bit to clear parity_err_int_raw interrupt.*/ + +#define UART_PARITY_ERR_INT_CLR (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_M (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_V 0x1 +#define UART_PARITY_ERR_INT_CLR_S 2 + +/* UART_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/* Description: Set this bit to clear txfifo_empty_int_raw interrupt.*/ + +#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_V 0x1 +#define UART_TXFIFO_EMPTY_INT_CLR_S 1 + +/* UART_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: Set this bit to clear the rxfifo_full_int_raw interrupt.*/ + +#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_V 0x1 +#define UART_RXFIFO_FULL_INT_CLR_S 0 + +#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14) + +/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ +/* Description: The register value is the decimal part of the frequency + * divider's factor. + */ + +#define UART_CLKDIV_FRAG 0x0000000F +#define UART_CLKDIV_FRAG_M ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S)) +#define UART_CLKDIV_FRAG_V 0xF +#define UART_CLKDIV_FRAG_S 20 + +/* UART_CLKDIV : R/W ;bitpos:[19:0] ;default: 20'h2B6 ; */ +/* Description: The register value is the integer part of the frequency + * divider's factor. + */ + +#define UART_CLKDIV 0x000FFFFF +#define UART_CLKDIV_M ((UART_CLKDIV_V)<<(UART_CLKDIV_S)) +#define UART_CLKDIV_V 0xFFFFF +#define UART_CLKDIV_S 0 + +#define UART_AUTOBAUD_REG(i) (REG_UART_BASE(i) + 0x18) + +/* UART_GLITCH_FILT : R/W ;bitpos:[15:8] ;default: 8'h10 ; */ +/* Description: when input pulse width is lower then this value igore this + * pulse. This register is used in autobaud detect process. + */ + +#define UART_GLITCH_FILT 0x000000FF +#define UART_GLITCH_FILT_M ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S)) +#define UART_GLITCH_FILT_V 0xFF +#define UART_GLITCH_FILT_S 8 + +/* UART_AUTOBAUD_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: This is the enable bit for detecting baudrate.*/ + +#define UART_AUTOBAUD_EN (BIT(0)) +#define UART_AUTOBAUD_EN_M (BIT(0)) +#define UART_AUTOBAUD_EN_V 0x1 +#define UART_AUTOBAUD_EN_S 0 + +#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1C) + +/* UART_TXD : RO ;bitpos:[31] ;default: 8'h0 ; */ +/* Description: This register represent the level value of the internal + * uart rxd signal. + */ + +#define UART_TXD (BIT(31)) +#define UART_TXD_M (BIT(31)) +#define UART_TXD_V 0x1 +#define UART_TXD_S 31 + +/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b0 ; */ +/* Description: This register represent the level value of the internal uart + * cts signal. + */ + +#define UART_RTSN (BIT(30)) +#define UART_RTSN_M (BIT(30)) +#define UART_RTSN_V 0x1 +#define UART_RTSN_S 30 + +/* UART_DTRN : RO ;bitpos:[29] ;default: 1'b0 ; */ +/* Description: The register represent the level value of the internal uart + * dsr signal. + */ + +#define UART_DTRN (BIT(29)) +#define UART_DTRN_M (BIT(29)) +#define UART_DTRN_V 0x1 +#define UART_DTRN_S 29 + +/* UART_ST_UTX_OUT : RO ;bitpos:[27:24] ;default: 4'b0 ; */ +/* Description: This register stores the value of transmitter's finite state + * machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 + * 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY + * 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1 + */ + +#define UART_ST_UTX_OUT 0x0000000F +#define UART_ST_UTX_OUT_M ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S)) +#define UART_ST_UTX_OUT_V 0xF +#define UART_ST_UTX_OUT_S 24 + +/* UART_TXFIFO_CNT : RO ;bitpos:[23:16] ;default: 8'b0 ; */ +/* Description: (tx_mem_cnt txfifo_cnt) stores the byte num of valid datas + * in transmitter's fifo. tx_mem_cnt stores the 3 most significant bits + * txfifo_cnt stores the 8 least significant bits. + */ + +#define UART_TXFIFO_CNT 0x000000FF +#define UART_TXFIFO_CNT_M ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S)) +#define UART_TXFIFO_CNT_V 0xFF +#define UART_TXFIFO_CNT_S 16 + +/* UART_RXD : RO ;bitpos:[15] ;default: 1'b0 ; */ +/* Description: This register stores the level value of the internal uart + * rxd signal. + */ + +#define UART_RXD (BIT(15)) +#define UART_RXD_M (BIT(15)) +#define UART_RXD_V 0x1 +#define UART_RXD_S 15 + +/* UART_CTSN : RO ;bitpos:[14] ;default: 1'b0 ; */ +/* Description: This register stores the level value of the internal uart + * cts signal. + */ + +#define UART_CTSN (BIT(14)) +#define UART_CTSN_M (BIT(14)) +#define UART_CTSN_V 0x1 +#define UART_CTSN_S 14 + +/* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */ +/* Description: This register stores the level value of the internal uart + * dsr signal. + */ + +#define UART_DSRN (BIT(13)) +#define UART_DSRN_M (BIT(13)) +#define UART_DSRN_V 0x1 +#define UART_DSRN_S 13 + +/* UART_ST_URX_OUT : RO ;bitpos:[11:8] ;default: 4'b0 ; */ +/* Description: This register stores the value of receiver's finite state + * machine. + * 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 + * 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 + * 12:RX_STP2 13:RX_DL1 + */ + +#define UART_ST_URX_OUT 0x0000000F +#define UART_ST_URX_OUT_M ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S)) +#define UART_ST_URX_OUT_V 0xF +#define UART_ST_URX_OUT_S 8 + +/* UART_RXFIFO_CNT : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/* Description: (rx_mem_cnt rxfifo_cnt) stores the byte num of valid datas + * in receiver's fifo. rx_mem_cnt register stores the 3 most significant + * bits rxfifo_cnt stores the 8 least significant bits. + */ + +#define UART_RXFIFO_CNT 0x000000FF +#define UART_RXFIFO_CNT_M ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S)) +#define UART_RXFIFO_CNT_V 0xFF +#define UART_RXFIFO_CNT_S 0 + +#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20) + +/* UART_TICK_REF_ALWAYS_ON : R/W ;bitpos:[27] ;default: 1'b1 ; */ +/* Description: This register is used to select the clock.1.apb clock + * 0:ref_tick + */ + +#define UART_TICK_REF_ALWAYS_ON (BIT(27)) +#define UART_TICK_REF_ALWAYS_ON_M (BIT(27)) +#define UART_TICK_REF_ALWAYS_ON_V 0x1 +#define UART_TICK_REF_ALWAYS_ON_S 27 + +/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/* Description: 1.receiver stops storing data int fifo when data is wrong. + * 0.receiver stores the data even if the received data is wrong.*/ + +#define UART_ERR_WR_MASK (BIT(26)) +#define UART_ERR_WR_MASK_M (BIT(26)) +#define UART_ERR_WR_MASK_V 0x1 +#define UART_ERR_WR_MASK_S 26 + +/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */ +/* Description: 1.force clock on for registers.support clock only when write + * registers + */ + +#define UART_CLK_EN (BIT(25)) +#define UART_CLK_EN_M (BIT(25)) +#define UART_CLK_EN_V 0x1 +#define UART_CLK_EN_S 25 + +/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */ +/* Description: Set this bit to inverse the level value of uart dtr signal.*/ + +#define UART_DTR_INV (BIT(24)) +#define UART_DTR_INV_M (BIT(24)) +#define UART_DTR_INV_V 0x1 +#define UART_DTR_INV_S 24 + +/* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */ +/* Description: Set this bit to inverse the level value of uart rts signal.*/ + +#define UART_RTS_INV (BIT(23)) +#define UART_RTS_INV_M (BIT(23)) +#define UART_RTS_INV_V 0x1 +#define UART_RTS_INV_S 23 + +/* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */ +/* Description: Set this bit to inverse the level value of uart txd signal.*/ + +#define UART_TXD_INV (BIT(22)) +#define UART_TXD_INV_M (BIT(22)) +#define UART_TXD_INV_V 0x1 +#define UART_TXD_INV_S 22 + +/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */ +/* Description: Set this bit to inverse the level value of uart dsr signal.*/ + +#define UART_DSR_INV (BIT(21)) +#define UART_DSR_INV_M (BIT(21)) +#define UART_DSR_INV_V 0x1 +#define UART_DSR_INV_S 21 + +/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */ +/* Description: Set this bit to inverse the level value of uart cts signal.*/ + +#define UART_CTS_INV (BIT(20)) +#define UART_CTS_INV_M (BIT(20)) +#define UART_CTS_INV_V 0x1 +#define UART_CTS_INV_S 20 + +/* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */ +/* Description: Set this bit to inverse the level value of uart rxd signal.*/ + +#define UART_RXD_INV (BIT(19)) +#define UART_RXD_INV_M (BIT(19)) +#define UART_RXD_INV_V 0x1 +#define UART_RXD_INV_S 19 + +/* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */ +/* Description: Set this bit to reset uart transmitter's fifo.*/ + +#define UART_TXFIFO_RST (BIT(18)) +#define UART_TXFIFO_RST_M (BIT(18)) +#define UART_TXFIFO_RST_V 0x1 +#define UART_TXFIFO_RST_S 18 + +/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/* Description: Set this bit to reset uart receiver's fifo.*/ + +#define UART_RXFIFO_RST (BIT(17)) +#define UART_RXFIFO_RST_M (BIT(17)) +#define UART_RXFIFO_RST_V 0x1 +#define UART_RXFIFO_RST_S 17 + +/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/* Description: Set this bit to enable irda protocol.*/ + +#define UART_IRDA_EN (BIT(16)) +#define UART_IRDA_EN_M (BIT(16)) +#define UART_IRDA_EN_V 0x1 +#define UART_IRDA_EN_S 16 + +/* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/* Description: Set this bit to enable transmitter's flow control function.*/ + +#define UART_TX_FLOW_EN (BIT(15)) +#define UART_TX_FLOW_EN_M (BIT(15)) +#define UART_TX_FLOW_EN_V 0x1 +#define UART_TX_FLOW_EN_S 15 + +/* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/* Description: Set this bit to enable uart loopback test mode.*/ + +#define UART_LOOPBACK (BIT(14)) +#define UART_LOOPBACK_M (BIT(14)) +#define UART_LOOPBACK_V 0x1 +#define UART_LOOPBACK_S 14 + +/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/* Description: Set this bit to inverse the level value of irda receiver's + * level. + */ + +#define UART_IRDA_RX_INV (BIT(13)) +#define UART_IRDA_RX_INV_M (BIT(13)) +#define UART_IRDA_RX_INV_V 0x1 +#define UART_IRDA_RX_INV_S 13 + +/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/* Description: Set this bit to inverse the level value of irda + * transmitter's level. + */ + +#define UART_IRDA_TX_INV (BIT(12)) +#define UART_IRDA_TX_INV_M (BIT(12)) +#define UART_IRDA_TX_INV_V 0x1 +#define UART_IRDA_TX_INV_S 12 + +/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/* Description: 1.the irda transmitter's 11th bit is the same to the 10th + * bit. 0.set irda transmitter's 11th bit to 0.*/ + +#define UART_IRDA_WCTL (BIT(11)) +#define UART_IRDA_WCTL_M (BIT(11)) +#define UART_IRDA_WCTL_V 0x1 +#define UART_IRDA_WCTL_S 11 + +/* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/* Description: This is the start enable bit for irda transmitter.*/ + +#define UART_IRDA_TX_EN (BIT(10)) +#define UART_IRDA_TX_EN_M (BIT(10)) +#define UART_IRDA_TX_EN_V 0x1 +#define UART_IRDA_TX_EN_S 10 + +/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/* Description: Set this bit to enable irda loopback mode.*/ + +#define UART_IRDA_DPLX (BIT(9)) +#define UART_IRDA_DPLX_M (BIT(9)) +#define UART_IRDA_DPLX_V 0x1 +#define UART_IRDA_DPLX_S 9 + +/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/* Description: Set this bit to enbale transmitter to send 0 when the + * process of sending data is done. + */ + +#define UART_TXD_BRK (BIT(8)) +#define UART_TXD_BRK_M (BIT(8)) +#define UART_TXD_BRK_V 0x1 +#define UART_TXD_BRK_S 8 + +/* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/* Description: This register is used to configure the software dtr signal + * which is used in software flow control. + */ + +#define UART_SW_DTR (BIT(7)) +#define UART_SW_DTR_M (BIT(7)) +#define UART_SW_DTR_V 0x1 +#define UART_SW_DTR_S 7 + +/* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/* Description: This register is used to configure the software rts signal + * which is used in software flow control. + */ + +#define UART_SW_RTS (BIT(6)) +#define UART_SW_RTS_M (BIT(6)) +#define UART_SW_RTS_V 0x1 +#define UART_SW_RTS_S 6 + +/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */ +/* Description: This register is used to set the length of stop bit. + * 1:1bit 2:1.5bits 3:2bits + */ + +#define UART_STOP_BIT_NUM 0x00000003 +#define UART_STOP_BIT_NUM_M ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S)) +#define UART_STOP_BIT_NUM_V 0x3 +#define UART_STOP_BIT_NUM_S 4 + +/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */ +/* Description: This registe is used to set the length of data: + * 0:5bits 1:6bits 2:7bits 3:8bits + */ + +#define UART_BIT_NUM 0x00000003 +#define UART_BIT_NUM_M ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S)) +#define UART_BIT_NUM_V 0x3 +#define UART_BIT_NUM_S 2 + +/* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/* Description: Set this bit to enable uart parity check.*/ + +#define UART_PARITY_EN (BIT(1)) +#define UART_PARITY_EN_M (BIT(1)) +#define UART_PARITY_EN_V 0x1 +#define UART_PARITY_EN_S 1 + +/* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: This register is used to configure the parity check mode. + * 0:even 1:odd + */ + +#define UART_PARITY (BIT(0)) +#define UART_PARITY_M (BIT(0)) +#define UART_PARITY_V 0x1 +#define UART_PARITY_S 0 + +#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) + +/* UART_RX_TOUT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/* Description: This is the enble bit for uart receiver's timeout function.*/ + +#define UART_RX_TOUT_EN (BIT(31)) +#define UART_RX_TOUT_EN_M (BIT(31)) +#define UART_RX_TOUT_EN_V 0x1 +#define UART_RX_TOUT_EN_S 31 + +/* UART_RX_TOUT_THRHD : R/W ;bitpos:[30:24] ;default: 7'b0 ; */ +/* Description: This register is used to configure the timeout value for + * uart receiver receiving a byte. + */ + +#define UART_RX_TOUT_THRHD 0x0000007F +#define UART_RX_TOUT_THRHD_M ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S)) +#define UART_RX_TOUT_THRHD_V 0x7F +#define UART_RX_TOUT_THRHD_S 24 + +/* UART_RX_FLOW_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/* Description: This is the flow enable bit for uart receiver. 1:choose + * software flow control with configuring sw_rts signal + */ + +#define UART_RX_FLOW_EN (BIT(23)) +#define UART_RX_FLOW_EN_M (BIT(23)) +#define UART_RX_FLOW_EN_V 0x1 +#define UART_RX_FLOW_EN_S 23 + +/* UART_RX_FLOW_THRHD : R/W ;bitpos:[22:16] ;default: 7'h0 ; */ +/* Description: when receiver receives more data than its threshold value. + * receiver produce signal to tell the transmitter stop transferring data. + * the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd). + */ + +#define UART_RX_FLOW_THRHD 0x0000007F +#define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S)) +#define UART_RX_FLOW_THRHD_V 0x7F +#define UART_RX_FLOW_THRHD_S 16 + +/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[14:8] ;default: 7'h60 ; */ +/* Description: when the data amount in transmitter fifo is less than its + * threshold value. it will produce txfifo_empty_int_raw interrupt. the + * threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd) + */ + +#define UART_TXFIFO_EMPTY_THRHD 0x0000007F +#define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S)) +#define UART_TXFIFO_EMPTY_THRHD_V 0x7F +#define UART_TXFIFO_EMPTY_THRHD_S 8 + +/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[6:0] ;default: 7'h60 ; */ +/* Description: When receiver receives more data than its threshold + * value.receiver will produce rxfifo_full_int_raw interrupt.the threshold + * value is (rx_flow_thrhd_h3 rxfifo_full_thrhd). + */ + +#define UART_RXFIFO_FULL_THRHD 0x0000007F +#define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S)) +#define UART_RXFIFO_FULL_THRHD_V 0x7F +#define UART_RXFIFO_FULL_THRHD_S 0 + +#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28) + +/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ +/* Description: This register stores the value of the minimum duration time + * for the low level pulse. it is used in baudrate-detect process. + */ + +#define UART_LOWPULSE_MIN_CNT 0x000FFFFF +#define UART_LOWPULSE_MIN_CNT_M ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S)) +#define UART_LOWPULSE_MIN_CNT_V 0xFFFFF +#define UART_LOWPULSE_MIN_CNT_S 0 + +#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C) + +/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ +/* Description: This register stores the value of the maxinum duration time + * for the high level pulse. it is used in baudrate-detect process. + */ + +#define UART_HIGHPULSE_MIN_CNT 0x000FFFFF +#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S)) +#define UART_HIGHPULSE_MIN_CNT_V 0xFFFFF +#define UART_HIGHPULSE_MIN_CNT_S 0 + +#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30) + +/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */ +/* Description: This register stores the count of rxd edge change. it is + * used in baudrate-detect process. + */ + +#define UART_RXD_EDGE_CNT 0x000003FF +#define UART_RXD_EDGE_CNT_M ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S)) +#define UART_RXD_EDGE_CNT_V 0x3FF +#define UART_RXD_EDGE_CNT_S 0 + +#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34) + +/* UART_SEND_XOFF : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/* Description: Set this bit to send xoff char. it is cleared by hardware + * automatically. + */ + +#define UART_SEND_XOFF (BIT(5)) +#define UART_SEND_XOFF_M (BIT(5)) +#define UART_SEND_XOFF_V 0x1 +#define UART_SEND_XOFF_S 5 + +/* UART_SEND_XON : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/* Description: Set this bit to send xon char. it is cleared by hardware + * automatically. + */ + +#define UART_SEND_XON (BIT(4)) +#define UART_SEND_XON_M (BIT(4)) +#define UART_SEND_XON_V 0x1 +#define UART_SEND_XON_S 4 + +/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/* Description: Set this bit to set ctsn to enable the transmitter to go on + * sending data. + */ + +#define UART_FORCE_XOFF (BIT(3)) +#define UART_FORCE_XOFF_M (BIT(3)) +#define UART_FORCE_XOFF_V 0x1 +#define UART_FORCE_XOFF_S 3 + +/* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/* Description: Set this bit to clear ctsn to stop the transmitter from + * sending data. + */ + +#define UART_FORCE_XON (BIT(2)) +#define UART_FORCE_XON_M (BIT(2)) +#define UART_FORCE_XON_V 0x1 +#define UART_FORCE_XON_S 2 + +/* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/* Description: Set this bit to remove flow control char from the received + * data. + */ + +#define UART_XONOFF_DEL (BIT(1)) +#define UART_XONOFF_DEL_M (BIT(1)) +#define UART_XONOFF_DEL_V 0x1 +#define UART_XONOFF_DEL_S 1 + +/* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: Set this bit to enable software flow control. it is used + * with register sw_xon or sw_xoff. + */ + +#define UART_SW_FLOW_CON_EN (BIT(0)) +#define UART_SW_FLOW_CON_EN_M (BIT(0)) +#define UART_SW_FLOW_CON_EN_V 0x1 +#define UART_SW_FLOW_CON_EN_S 0 + +#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38) + +/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */ +/* Description: When the input rxd edge changes more than this register + * value. the uart is active from light sleeping mode. + */ + +#define UART_ACTIVE_THRESHOLD 0x000003FF +#define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S)) +#define UART_ACTIVE_THRESHOLD_V 0x3FF +#define UART_ACTIVE_THRESHOLD_S 0 + +#define UART_SWFC_CONF_REG(i) (REG_UART_BASE(i) + 0x3C) + +/* UART_XOFF_CHAR : R/W ;bitpos:[31:24] ;default: 8'h13 ; */ +/* Description: This register stores the xoff flow control char.*/ + +#define UART_XOFF_CHAR 0x000000FF +#define UART_XOFF_CHAR_M ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S)) +#define UART_XOFF_CHAR_V 0xFF +#define UART_XOFF_CHAR_S 24 + +/* UART_XON_CHAR : R/W ;bitpos:[23:16] ;default: 8'h11 ; */ +/* Description: This register stores the xon flow control char.*/ + +#define UART_XON_CHAR 0x000000FF +#define UART_XON_CHAR_M ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S)) +#define UART_XON_CHAR_V 0xFF +#define UART_XON_CHAR_S 16 + +/* UART_XOFF_THRESHOLD : R/W ;bitpos:[15:8] ;default: 8'he0 ; */ +/* Description: When the data amount in receiver's fifo is less than this + * register value. it will send a xon char with uart_sw_flow_con_en set to + * 1. + */ + +#define UART_XOFF_THRESHOLD 0x000000FF +#define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S)) +#define UART_XOFF_THRESHOLD_V 0xFF +#define UART_XOFF_THRESHOLD_S 8 + +/* UART_XON_THRESHOLD : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/* Description: when the data amount in receiver's fifo is more than this + * register value. it will send a xoff char with uart_sw_flow_con_en set to + * 1. + */ + +#define UART_XON_THRESHOLD 0x000000FF +#define UART_XON_THRESHOLD_M ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S)) +#define UART_XON_THRESHOLD_V 0xFF +#define UART_XON_THRESHOLD_S 0 + +#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x40) + +/* UART_TX_BRK_NUM : R/W ;bitpos:[27:20] ;default: 8'ha ; */ +/* Description: This register is used to configure the num of 0 send after + * the process of sending data is done. it is active when txd_brk is set to + * 1. + */ + +#define UART_TX_BRK_NUM 0x000000FF +#define UART_TX_BRK_NUM_M ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S)) +#define UART_TX_BRK_NUM_V 0xFF +#define UART_TX_BRK_NUM_S 20 + +/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */ +/* Description: This register is used to configure the duration time + * between transfers. + */ + +#define UART_TX_IDLE_NUM 0x000003FF +#define UART_TX_IDLE_NUM_M ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S)) +#define UART_TX_IDLE_NUM_V 0x3FF +#define UART_TX_IDLE_NUM_S 10 + +/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */ +/* Description: when receiver takes more time than this register value to + * receive a byte data. it will produce frame end signal for uhci to stop + * receiving data. + */ + +#define UART_RX_IDLE_THRHD 0x000003FF +#define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S)) +#define UART_RX_IDLE_THRHD_V 0x3FF +#define UART_RX_IDLE_THRHD_S 0 + +#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x44) + +/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */ +/* Description: This register is used to delay the transmitter's internal + * data signal. + */ + +#define UART_RS485_TX_DLY_NUM 0x0000000F +#define UART_RS485_TX_DLY_NUM_M ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S)) +#define UART_RS485_TX_DLY_NUM_V 0xF +#define UART_RS485_TX_DLY_NUM_S 6 + +/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/* Description: This register is used to delay the receiver's internal data + * signal. + */ + +#define UART_RS485_RX_DLY_NUM (BIT(5)) +#define UART_RS485_RX_DLY_NUM_M (BIT(5)) +#define UART_RS485_RX_DLY_NUM_V 0x1 +#define UART_RS485_RX_DLY_NUM_S 5 + +/* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/* Description: 1: enable rs485's transmitter to send data when rs485's + * receiver is busy. 0:rs485's transmitter should not send data when its + * receiver is busy. + */ + +#define UART_RS485RXBY_TX_EN (BIT(4)) +#define UART_RS485RXBY_TX_EN_M (BIT(4)) +#define UART_RS485RXBY_TX_EN_V 0x1 +#define UART_RS485RXBY_TX_EN_S 4 + +/* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/* Description: Set this bit to enable loopback transmitter's output data + * signal to receiver's input data signal. + */ + +#define UART_RS485TX_RX_EN (BIT(3)) +#define UART_RS485TX_RX_EN_M (BIT(3)) +#define UART_RS485TX_RX_EN_V 0x1 +#define UART_RS485TX_RX_EN_S 3 + +/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/* Description: Set this bit to delay the stop bit by 1 bit.*/ + +#define UART_DL1_EN (BIT(2)) +#define UART_DL1_EN_M (BIT(2)) +#define UART_DL1_EN_V 0x1 +#define UART_DL1_EN_S 2 + +/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/* Description: Set this bit to delay the stop bit by 1 bit.*/ + +#define UART_DL0_EN (BIT(1)) +#define UART_DL0_EN_M (BIT(1)) +#define UART_DL0_EN_V 0x1 +#define UART_DL0_EN_S 1 + +/* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: Set this bit to choose rs485 mode.*/ + +#define UART_RS485_EN (BIT(0)) +#define UART_RS485_EN_M (BIT(0)) +#define UART_RS485_EN_V 0x1 +#define UART_RS485_EN_S 0 + +#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x48) + +/* UART_PRE_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */ +/* Description: This register is used to configure the idle duration time + * before the first at_cmd is received by receiver. when the the duration + * is less than this register value it will not take the next data received + * as at_cmd char. + */ + +#define UART_PRE_IDLE_NUM 0x00FFFFFF +#define UART_PRE_IDLE_NUM_M ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S)) +#define UART_PRE_IDLE_NUM_V 0xFFFFFF +#define UART_PRE_IDLE_NUM_S 0 + +#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x4c) + +/* UART_POST_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */ +/* Description: This register is used to configure the duration time between + * the last at_cmd and the next data. when the duration is less than this + * register value it will not take the previous data as at_cmd char. + */ + +#define UART_POST_IDLE_NUM 0x00FFFFFF +#define UART_POST_IDLE_NUM_M ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S)) +#define UART_POST_IDLE_NUM_V 0xFFFFFF +#define UART_POST_IDLE_NUM_S 0 + +#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x50) + +/* UART_RX_GAP_TOUT : R/W ;bitpos:[23:0] ;default: 24'h1e00 ; */ +/* Description: This register is used to configure the duration time between + * the at_cmd chars. when the duration time is less than this register + * value it will not take the datas as continous at_cmd chars. + */ + +#define UART_RX_GAP_TOUT 0x00FFFFFF +#define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S)) +#define UART_RX_GAP_TOUT_V 0xFFFFFF +#define UART_RX_GAP_TOUT_S 0 + +#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x54) + +/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */ +/* Description: This register is used to configure the num of continous + * at_cmd chars received by receiver. + */ + +#define UART_CHAR_NUM 0x000000FF +#define UART_CHAR_NUM_M ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S)) +#define UART_CHAR_NUM_V 0xFF +#define UART_CHAR_NUM_S 8 + +/* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */ +/* Description: This register is used to configure the content of at_cmd + * char. + */ + +#define UART_AT_CMD_CHAR 0x000000FF +#define UART_AT_CMD_CHAR_M ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S)) +#define UART_AT_CMD_CHAR_V 0xFF +#define UART_AT_CMD_CHAR_S 0 + +#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x58) + +/* UART_TX_MEM_EMPTY_THRHD : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ +/* Description: refer to txfifo_empty_thrhd 's describtion.*/ + +#define UART_TX_MEM_EMPTY_THRHD 0x00000007 +#define UART_TX_MEM_EMPTY_THRHD_M ((UART_TX_MEM_EMPTY_THRHD_V)<<(UART_TX_MEM_EMPTY_THRHD_S)) +#define UART_TX_MEM_EMPTY_THRHD_V 0x7 +#define UART_TX_MEM_EMPTY_THRHD_S 28 + +/* UART_RX_MEM_FULL_THRHD : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ +/* Description: refer to the rxfifo_full_thrhd's describtion.*/ + +#define UART_RX_MEM_FULL_THRHD 0x00000007 +#define UART_RX_MEM_FULL_THRHD_M ((UART_RX_MEM_FULL_THRHD_V)<<(UART_RX_MEM_FULL_THRHD_S)) +#define UART_RX_MEM_FULL_THRHD_V 0x7 +#define UART_RX_MEM_FULL_THRHD_S 25 + +/* UART_XOFF_THRESHOLD_H2 : R/W ;bitpos:[24:23] ;default: 2'h0 ; */ +/* Description: refer to the uart_xoff_threshold's describtion.*/ + +#define UART_XOFF_THRESHOLD_H2 0x00000003 +#define UART_XOFF_THRESHOLD_H2_M ((UART_XOFF_THRESHOLD_H2_V)<<(UART_XOFF_THRESHOLD_H2_S)) +#define UART_XOFF_THRESHOLD_H2_V 0x3 +#define UART_XOFF_THRESHOLD_H2_S 23 + +/* UART_XON_THRESHOLD_H2 : R/W ;bitpos:[22:21] ;default: 2'h0 ; */ +/* Description: refer to the uart_xon_threshold's describtion.*/ + +#define UART_XON_THRESHOLD_H2 0x00000003 +#define UART_XON_THRESHOLD_H2_M ((UART_XON_THRESHOLD_H2_V)<<(UART_XON_THRESHOLD_H2_S)) +#define UART_XON_THRESHOLD_H2_V 0x3 +#define UART_XON_THRESHOLD_H2_S 21 + +/* UART_RX_TOUT_THRHD_H3 : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ +/* Description: refer to the rx_tout_thrhd's describtion.*/ + +#define UART_RX_TOUT_THRHD_H3 0x00000007 +#define UART_RX_TOUT_THRHD_H3_M ((UART_RX_TOUT_THRHD_H3_V)<<(UART_RX_TOUT_THRHD_H3_S)) +#define UART_RX_TOUT_THRHD_H3_V 0x7 +#define UART_RX_TOUT_THRHD_H3_S 18 + +/* UART_RX_FLOW_THRHD_H3 : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ +/* Description: refer to the rx_flow_thrhd's describtion.*/ + +#define UART_RX_FLOW_THRHD_H3 0x00000007 +#define UART_RX_FLOW_THRHD_H3_M ((UART_RX_FLOW_THRHD_H3_V)<<(UART_RX_FLOW_THRHD_H3_S)) +#define UART_RX_FLOW_THRHD_H3_V 0x7 +#define UART_RX_FLOW_THRHD_H3_S 15 + +/* UART_TX_SIZE : R/W ;bitpos:[10:7] ;default: 4'h1 ; */ +/* Description: This register is used to configure the amount of mem + * allocated to transmitter's fifo.the default byte num is 128. + */ + +#define UART_TX_SIZE 0x0000000F +#define UART_TX_SIZE_M ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S)) +#define UART_TX_SIZE_V 0xF +#define UART_TX_SIZE_S 7 + +/* UART_RX_SIZE : R/W ;bitpos:[6:3] ;default: 4'h1 ; */ +/* Description: This register is used to configure the amount of mem + * allocated to receiver's fifo. the default byte num is 128. + */ + +#define UART_RX_SIZE 0x0000000F +#define UART_RX_SIZE_M ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S)) +#define UART_RX_SIZE_V 0xF +#define UART_RX_SIZE_S 3 + +/* UART_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/* Description: Set this bit to power down mem.when reg_mem_pd registers in + * the 3 uarts are all set to 1 mem will enter low power mode. + */ + +#define UART_MEM_PD (BIT(0)) +#define UART_MEM_PD_M (BIT(0)) +#define UART_MEM_PD_V 0x1 +#define UART_MEM_PD_S 0 + +#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x5c) + +/* UART_MEM_TX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */ +/* Description: */ + +#define UART_MEM_TX_STATUS 0x00FFFFFF +#define UART_MEM_TX_STATUS_M ((UART_MEM_TX_STATUS_V)<<(UART_MEM_TX_STATUS_S)) +#define UART_MEM_TX_STATUS_V 0xFFFFFF +#define UART_MEM_TX_STATUS_S 0 + +#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x60) + +/* UART_MEM_RX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */ +/* Description: */ + +#define UART_MEM_RX_STATUS 0x00FFFFFF +#define UART_MEM_RX_STATUS_M ((UART_MEM_RX_STATUS_V)<<(UART_MEM_RX_STATUS_S)) +#define UART_MEM_RX_STATUS_V 0xFFFFFF +#define UART_MEM_RX_STATUS_S 0 + +#define UART_MEM_CNT_STATUS_REG(i) (REG_UART_BASE(i) + 0x64) + +/* UART_TX_MEM_CNT : RO ;bitpos:[5:3] ;default: 3'b0 ; */ +/* Description: refer to the txfifo_cnt's describtion.*/ + +#define UART_TX_MEM_CNT 0x00000007 +#define UART_TX_MEM_CNT_M ((UART_TX_MEM_CNT_V)<<(UART_TX_MEM_CNT_S)) +#define UART_TX_MEM_CNT_V 0x7 +#define UART_TX_MEM_CNT_S 3 + +/* UART_RX_MEM_CNT : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/* Description: refer to the rxfifo_cnt's describtion.*/ + +#define UART_RX_MEM_CNT 0x00000007 +#define UART_RX_MEM_CNT_M ((UART_RX_MEM_CNT_V)<<(UART_RX_MEM_CNT_S)) +#define UART_RX_MEM_CNT_V 0x7 +#define UART_RX_MEM_CNT_S 0 + +#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x68) + +/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ +/* Description: This register stores the count of rxd posedge edge. it is + * used in boudrate-detect process. + */ + +#define UART_POSEDGE_MIN_CNT 0x000FFFFF +#define UART_POSEDGE_MIN_CNT_M ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S)) +#define UART_POSEDGE_MIN_CNT_V 0xFFFFF +#define UART_POSEDGE_MIN_CNT_S 0 + +#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x6c) + +/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ +/* Description: This register stores the count of rxd negedge edge. it is + * used in boudrate-detect process. + */ + +#define UART_NEGEDGE_MIN_CNT 0x000FFFFF +#define UART_NEGEDGE_MIN_CNT_M ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S)) +#define UART_NEGEDGE_MIN_CNT_V 0xFFFFF +#define UART_NEGEDGE_MIN_CNT_S 0 + +#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x78) + +/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h15122500 ; */ +/* Description: */ + +#define UART_DATE 0xFFFFFFFF +#define UART_DATE_M ((UART_DATE_V)<<(UART_DATE_S)) +#define UART_DATE_V 0xFFFFFFFF +#define UART_DATE_S 0 + +#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x7C) + +/* UART_ID : R/W ;bitpos:[31:0] ;default: 32'h0500 ; */ +/* Description: */ + +#define UART_ID 0xFFFFFFFF +#define UART_ID_M ((UART_ID_V)<<(UART_ID_S)) +#define UART_ID_V 0xFFFFFFFF +#define UART_ID_S 0 + +#endif /*__ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_UART_H */ -- GitLab From 2a59205ffa8599ba7ff25a0bb966e07b172cf5ef Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 25 Oct 2016 12:02:53 -0600 Subject: [PATCH 206/734] ESP32: Add CPU interrupt managmement logic; improve level interrupt decoding. --- arch/xtensa/include/esp32/irq.h | 372 +++++++++++++++++------- arch/xtensa/src/common/xtensa.h | 9 +- arch/xtensa/src/common/xtensa_cpuint.S | 128 ++++++++ arch/xtensa/src/esp32/Make.defs | 21 +- arch/xtensa/src/esp32/esp32_cpuint.c | 303 +++++++++++++++++++ arch/xtensa/src/esp32/esp32_cpuint.h | 119 ++++++++ arch/xtensa/src/esp32/esp32_cpustart.c | 21 ++ arch/xtensa/src/esp32/esp32_intdecode.c | 32 +- arch/xtensa/src/esp32/esp32_irq.c | 95 ++---- arch/xtensa/src/esp32/esp32_timerisr.c | 33 +-- 10 files changed, 923 insertions(+), 210 deletions(-) create mode 100644 arch/xtensa/src/common/xtensa_cpuint.S create mode 100644 arch/xtensa/src/esp32/esp32_cpuint.c create mode 100644 arch/xtensa/src/esp32/esp32_cpuint.h diff --git a/arch/xtensa/include/esp32/irq.h b/arch/xtensa/include/esp32/irq.h index 36fce7d4e5..4221f30b20 100644 --- a/arch/xtensa/include/esp32/irq.h +++ b/arch/xtensa/include/esp32/irq.h @@ -50,29 +50,6 @@ * Pre-processor Definitions ****************************************************************************/ -/* Exceptions - * - * IRAM Offset Description - * 0x0000 Windows - * 0x0180 Level 2 interrupt - * 0x01c0 Level 3 interrupt - * 0x0200 Level 4 interrupt - * 0x0240 Level 5 interrupt - * 0x0280 Debug exception - * 0x02c0 NMI exception - * 0x0300 Kernel exception - * 0x0340 User exception - * 0x03c0 Double exception - * - * REVISIT: In more architectures supported by NuttX, exception errors - * tie into the normal interrupt handling via special IRQ numbers. I - * is still to be determined what will be done for the ESP32. - */ - -#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */ -#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */ -#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */ - /* Interrupt Matrix * * The Interrupt Matrix embedded in the ESP32 independently allocates @@ -102,94 +79,285 @@ /* PRO_INTR_STATUS_REG_0 / APP_INTR_STATUS_REG_0 */ -#define XTENSA_IRQ_SREG0 3 -#define XTENSA_IRQ_MAC 3 /* INTR_STATUS_REG_0, bit 0 */ -#define XTENSA_IRQ_MAC_NMI 4 /* INTR_STATUS_REG_0, bit 1 */ -#define XTENSA_IRQ_BB 5 /* INTR_STATUS_REG_0, bit 2 */ -#define XTENSA_IRQ_BB_MAC 6 /* INTR_STATUS_REG_0, bit 3 */ -#define XTENSA_IRQ_BT_BB 7 /* INTR_STATUS_REG_0, bit 4 */ -#define XTENSA_IRQ_BT_BB_NMI 8 /* INTR_STATUS_REG_0, bit 5 */ -#define XTENSA_IRQ_RWBT_IRQ 9 /* INTR_STATUS_REG_0, bit 6 */ -#define XTENSA_IRQ_RWBLE_IRQ 10 /* INTR_STATUS_REG_0, bit 7 */ -#define XTENSA_IRQ_RWBT_NMI 11 /* INTR_STATUS_REG_0, bit 8 */ -#define XTENSA_IRQ_RWBLE_NMI 12 /* INTR_STATUS_REG_0, bit 9 */ - -#define XTENSA_IRQ_SLC0 13 /* INTR_STATUS_REG_0, bit 10 */ -#define XTENSA_IRQ_SLC1 14 /* INTR_STATUS_REG_0, bit 11 */ -#define XTENSA_IRQ_UHCI0 15 /* INTR_STATUS_REG_0, bit 12 */ -#define XTENSA_IRQ_UHCI1 16 /* INTR_STATUS_REG_0, bit 13 */ -#define XTENSA_IRQ_TG_T0_LEVEL 17 /* INTR_STATUS_REG_0, bit 14 */ -#define XTENSA_IRQ_TG_T1_LEVEL 18 /* INTR_STATUS_REG_0, bit 15 */ -#define XTENSA_IRQ_TG_WDT_LEVEL 19 /* INTR_STATUS_REG_0, bit 16 */ -#define XTENSA_IRQ_TG_LACT_LEVEL 20 /* INTR_STATUS_REG_0, bit 17 */ -#define XTENSA_IRQ_TG1_T0_LEVEL 21 /* INTR_STATUS_REG_0, bit 18 */ -#define XTENSA_IRQ_TG1_T1_LEVEL 22 /* INTR_STATUS_REG_0, bit 19 */ - -#define XTENSA_IRQ_TG1_WDT_LEVEL 23 /* INTR_STATUS_REG_0, bit 20 */ -#define XTENSA_IRQ_G1_LACT_LEVEL 24 /* INTR_STATUS_REG_0, bit 21 */ -#define XTENSA_IRQ_CPU_GPIO 25 /* INTR_STATUS_REG_0, bit 22 */ -#define XTENSA_IRQ_CPU_NMI 26 /* INTR_STATUS_REG_0, bit 23 */ -#define XTENSA_IRQ_CPU_CPU0 27 /* INTR_STATUS_REG_0, bit 24 */ -#define XTENSA_IRQ_CPU_CPU1 28 /* INTR_STATUS_REG_0, bit 25 */ -#define XTENSA_IRQ_CPU_CPU2 29 /* INTR_STATUS_REG_0, bit 26 */ -#define XTENSA_IRQ_CPU_CPU3 30 /* INTR_STATUS_REG_0, bit 27 */ -#define XTENSA_IRQ_SPI0 31 /* INTR_STATUS_REG_0, bit 28 */ -#define XTENSA_IRQ_SPI1 32 /* INTR_STATUS_REG_0, bit 29 */ - -#define XTENSA_IRQ_SPI2 33 /* INTR_STATUS_REG_0, bit 30 */ -#define XTENSA_IRQ_SPI3 34 /* INTR_STATUS_REG_0, bit 31 */ +#define ESP32_PERIPH_MAC 0 /* INTR_STATUS_REG_0, bit 0 */ +#define ESP32_PERIPH_MAC_NMI 1 /* INTR_STATUS_REG_0, bit 1 */ +#define ESP32_PERIPH_BB 2 /* INTR_STATUS_REG_0, bit 2 */ +#define ESP32_PERIPH_BB_MAC 3 /* INTR_STATUS_REG_0, bit 3 */ +#define ESP32_PERIPH_BT_BB 4 /* INTR_STATUS_REG_0, bit 4 */ +#define ESP32_PERIPH_BT_BB_NMI 5 /* INTR_STATUS_REG_0, bit 5 */ +#define ESP32_PERIPH_RWBT_IRQ 6 /* INTR_STATUS_REG_0, bit 6 */ +#define ESP32_PERIPH_RWBLE_IRQ 7 /* INTR_STATUS_REG_0, bit 7 */ +#define ESP32_PERIPH_RWBT_NMI 8 /* INTR_STATUS_REG_0, bit 8 */ +#define ESP32_PERIPH_RWBLE_NMI 9 /* INTR_STATUS_REG_0, bit 9 */ + +#define ESP32_PERIPH_SLC0 10 /* INTR_STATUS_REG_0, bit 10 */ +#define ESP32_PERIPH_SLC1 11 /* INTR_STATUS_REG_0, bit 11 */ +#define ESP32_PERIPH_UHCI0 12 /* INTR_STATUS_REG_0, bit 12 */ +#define ESP32_PERIPH_UHCI1 13 /* INTR_STATUS_REG_0, bit 13 */ +#define ESP32_PERIPH_TG_T0_LEVEL 14 /* INTR_STATUS_REG_0, bit 14 */ +#define ESP32_PERIPH_TG_T1_LEVEL 15 /* INTR_STATUS_REG_0, bit 15 */ +#define ESP32_PERIPH_TG_WDT_LEVEL 16 /* INTR_STATUS_REG_0, bit 16 */ +#define ESP32_PERIPH_TG_LACT_LEVEL 17 /* INTR_STATUS_REG_0, bit 17 */ +#define ESP32_PERIPH_TG1_T0_LEVEL 18 /* INTR_STATUS_REG_0, bit 18 */ +#define ESP32_PERIPH_TG1_T1_LEVEL 19 /* INTR_STATUS_REG_0, bit 19 */ + +#define ESP32_PERIPH_TG1_WDT_LEVEL 20 /* INTR_STATUS_REG_0, bit 20 */ +#define ESP32_PERIPH_G1_LACT_LEVEL 21 /* INTR_STATUS_REG_0, bit 21 */ +#define ESP32_PERIPH_CPU_GPIO 22 /* INTR_STATUS_REG_0, bit 22 */ +#define ESP32_PERIPH_CPU_NMI 23 /* INTR_STATUS_REG_0, bit 23 */ +#define ESP32_PERIPH_CPU_CPU0 24 /* INTR_STATUS_REG_0, bit 24 */ +#define ESP32_PERIPH_CPU_CPU1 25 /* INTR_STATUS_REG_0, bit 25 */ +#define ESP32_PERIPH_CPU_CPU2 26 /* INTR_STATUS_REG_0, bit 26 */ +#define ESP32_PERIPH_CPU_CPU3 27 /* INTR_STATUS_REG_0, bit 27 */ +#define ESP32_PERIPH_SPI0 28 /* INTR_STATUS_REG_0, bit 28 */ +#define ESP32_PERIPH_SPI1 29 /* INTR_STATUS_REG_0, bit 29 */ + +#define ESP32_PERIPH_SPI2 30 /* INTR_STATUS_REG_0, bit 30 */ +#define ESP32_PERIPH_SPI3 31 /* INTR_STATUS_REG_0, bit 31 */ + +/* PRO_INTR_STATUS_REG_1 / APP_INTR_STATUS_REG_1 */ + +#define ESP32_PERIPH_I2S0 32 /* INTR_STATUS_REG_1, bit 0 */ +#define ESP32_PERIPH_I2S1 33 /* INTR_STATUS_REG_1, bit 1 */ +#define ESP32_PERIPH_UART 34 /* INTR_STATUS_REG_1, bit 2 */ +#define ESP32_PERIPH_UART1 35 /* INTR_STATUS_REG_1, bit 3 */ +#define ESP32_PERIPH_UART2 36 /* INTR_STATUS_REG_1, bit 4 */ +#define ESP32_PERIPH_SDIO_HOST 37 /* INTR_STATUS_REG_1, bit 5 */ +#define ESP32_PERIPH_EMAC 38 /* INTR_STATUS_REG_1, bit 6 */ +#define ESP32_PERIPH_PWM0 39 /* INTR_STATUS_REG_1, bit 7 */ +#define ESP32_PERIPH_PWM1 40 /* INTR_STATUS_REG_1, bit 8 */ +#define ESP32_PERIPH_PWM2 41 /* INTR_STATUS_REG_1, bit 9 */ + +#define ESP32_PERIPH_PWM3 42 /* INTR_STATUS_REG_1, bit 10 */ +#define ESP32_PERIPH_LEDC 43 /* INTR_STATUS_REG_1, bit 11 */ +#define ESP32_PERIPH_EFUSE 44 /* INTR_STATUS_REG_1, bit 12 */ +#define ESP32_PERIPH_CAN 45 /* INTR_STATUS_REG_1, bit 13 */ +#define ESP32_PERIPH_RTC_CORE 46 /* INTR_STATUS_REG_1, bit 14 */ +#define ESP32_PERIPH_RMT 47 /* INTR_STATUS_REG_1, bit 15 */ +#define ESP32_PERIPH_PCNT 48 /* INTR_STATUS_REG_1, bit 16 */ +#define ESP32_PERIPH_I2C_EXT0 49 /* INTR_STATUS_REG_1, bit 17 */ +#define ESP32_PERIPH_I2C_EXT1 50 /* INTR_STATUS_REG_1, bit 18 */ +#define ESP32_PERIPH_RSA 51 /* INTR_STATUS_REG_1, bit 19 */ + +#define ESP32_PERIPH_SPI1_DMA 52 /* INTR_STATUS_REG_1, bit 20 */ +#define ESP32_PERIPH_SPI2_DMA 53 /* INTR_STATUS_REG_1, bit 21 */ +#define ESP32_PERIPH_SPI3_DMA 54 /* INTR_STATUS_REG_1, bit 22 */ +#define ESP32_PERIPH_WDG 55 /* INTR_STATUS_REG_1, bit 23 */ +#define ESP32_PERIPH_TIMER1 56 /* INTR_STATUS_REG_1, bit 24 */ +#define ESP32_PERIPH_TIMER2 57 /* INTR_STATUS_REG_1, bit 25 */ +#define ESP32_PERIPH_TG_T0_EDGE 58 /* INTR_STATUS_REG_1, bit 26 */ +#define ESP32_PERIPH_TG_T1_EDGE 59 /* INTR_STATUS_REG_1, bit 27 */ +#define ESP32_PERIPH_TG_WDT_EDGE 60 /* INTR_STATUS_REG_1, bit 28 */ +#define ESP32_PERIPH_TG_LACT_EDGE 61 /* INTR_STATUS_REG_1, bit 29 */ + +#define ESP32_PERIPH_TG1_T0_EDGE 62 /* INTR_STATUS_REG_1, bit 30 */ +#define ESP32_PERIPH_TG1_T1_EDGE 63 /* INTR_STATUS_REG_1, bit 31 */ + +/* PRO_INTR_STATUS_REG_2 / APP_INTR_STATUS_REG_2 */ + +#define ESP32_PERIPH_TG1_WDT_EDGE 64 /* INTR_STATUS_REG_2, bit 0 */ +#define ESP32_PERIPH_TG1_LACT_EDGE 65 /* INTR_STATUS_REG_2, bit 1 */ +#define ESP32_PERIPH_MMU_IA 66 /* INTR_STATUS_REG_2, bit 2 */ +#define ESP32_PERIPH_MPU_IA 67 /* INTR_STATUS_REG_2, bit 3 */ +#define ESP32_PERIPH_CACHE_IA 68 /* INTR_STATUS_REG_2, bit 4 */ + +/* Total number of peripherals */ + +#define NR_PERIPHERALS 69 + +/* Exceptions + * + * IRAM Offset Description + * 0x0000 Windows + * 0x0180 Level 2 interrupt + * 0x01c0 Level 3 interrupt + * 0x0200 Level 4 interrupt + * 0x0240 Level 5 interrupt + * 0x0280 Debug exception + * 0x02c0 NMI exception + * 0x0300 Kernel exception + * 0x0340 User exception + * 0x03c0 Double exception + * + * REVISIT: In more architectures supported by NuttX, exception errors + * tie into the normal interrupt handling via special IRQ numbers. I + * is still to be determined what will be done for the ESP32. + */ + +/* IRQ numbers for internal interrupts that are dispatched like peripheral + * interrupts + */ + +#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */ +#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */ +#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */ + +#define XTENSA_IRQ_FIRSTPERIPH 3 /* First peripheral IRQ number */ + +/* IRQ numbers for peripheral interrupts coming throught the Interrupt + * Matrix. + */ + +#define ESP32_IRQ2PERIPH(irq) ((irq)-XTENSA_IRQ_FIRSTPERIPH) + +/* PRO_INTR_STATUS_REG_0 / APP_INTR_STATUS_REG_0 */ + +#define ESP32_IRQ_MAC (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_MAC) +#define ESP32_IRQ_MAC_NMI (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_MAC_NMI) +#define ESP32_IRQ_BB (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_BB) +#define ESP32_IRQ_BB_MAC (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_BB_MAC) +#define ESP32_IRQ_BT_BB (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_BT_BB) +#define ESP32_IRQ_BT_BB_NMI (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_BT_BB_NMI) +#define ESP32_IRQ_RWBT_IRQ (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_RWBT_IRQ) +#define ESP32_IRQ_RWBLE_IRQ (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_RWBLE_IRQ) +#define ESP32_IRQ_RWBT_NMI (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_RWBT_NMI) +#define ESP32_IRQ_RWBLE_NMI (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_RWBLE_NMI) +#define ESP32_IRQ_SLC0 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SLC0) +#define ESP32_IRQ_SLC1 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SLC1) +#define ESP32_IRQ_UHCI0 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_UHCI0) +#define ESP32_IRQ_UHCI1 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_UHCI1) +#define ESP32_IRQ_TG_T0_LEVEL (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG_T0_LEVEL) +#define ESP32_IRQ_TG_T1_LEVEL (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG_T1_LEVEL) +#define ESP32_IRQ_TG_WDT_LEVEL (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG_WDT_LEVEL) +#define ESP32_IRQ_TG_LACT_LEVEL (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG_LACT_LEVEL) +#define ESP32_IRQ_TG1_T0_LEVEL (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG1_T0_LEVEL) +#define ESP32_IRQ_TG1_T1_LEVEL (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG1_T1_LEVEL) +#define ESP32_IRQ_TG1_WDT_LEVEL (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG1_WDT_LEVEL) +#define ESP32_IRQ_G1_LACT_LEVEL (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_G1_LACT_LEVEL) +#define ESP32_IRQ_CPU_GPIO (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_CPU_GPIO) +#define ESP32_IRQ_CPU_NMI (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_CPU_NMI) +#define ESP32_IRQ_CPU_CPU0 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_CPU_CPU0) +#define ESP32_IRQ_CPU_CPU1 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_CPU_CPU1) +#define ESP32_IRQ_CPU_CPU2 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_CPU_CPU2) +#define ESP32_IRQ_CPU_CPU3 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_CPU_CPU3) +#define ESP32_IRQ_SPI0 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SPI0) +#define ESP32_IRQ_SPI1 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SPI1 +#define ESP32_IRQ_SPI2 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SPI2) +#define ESP32_IRQ_SPI3 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SPI3 + +#define ESP32_IRQ_SREG0 ESP32_IRQ_MAC +#define ESP32_NIRQS_SREG0 32 /* PRO_INTR_STATUS_REG_1 / APP_INTR_STATUS_REG_1 */ -#define XTENSA_IRQ_SREG1 35 -#define XTENSA_IRQ_I2S0 35 /* INTR_STATUS_REG_1, bit 0 */ -#define XTENSA_IRQ_I2S1 36 /* INTR_STATUS_REG_1, bit 1 */ -#define XTENSA_IRQ_UART 37 /* INTR_STATUS_REG_1, bit 2 */ -#define XTENSA_IRQ_UART1 38 /* INTR_STATUS_REG_1, bit 3 */ -#define XTENSA_IRQ_UART2 39 /* INTR_STATUS_REG_1, bit 4 */ -#define XTENSA_IRQ_SDIO_HOST 40 /* INTR_STATUS_REG_1, bit 5 */ -#define XTENSA_IRQ_EMAC 41 /* INTR_STATUS_REG_1, bit 6 */ -#define XTENSA_IRQ_PWM0 42 /* INTR_STATUS_REG_1, bit 7 */ -#define XTENSA_IRQ_PWM1 43 /* INTR_STATUS_REG_1, bit 8 */ -#define XTENSA_IRQ_PWM2 44 /* INTR_STATUS_REG_1, bit 9 */ - -#define XTENSA_IRQ_PWM3 45 /* INTR_STATUS_REG_1, bit 10 */ -#define XTENSA_IRQ_LEDC 46 /* INTR_STATUS_REG_1, bit 11 */ -#define XTENSA_IRQ_EFUSE 47 /* INTR_STATUS_REG_1, bit 12 */ -#define XTENSA_IRQ_CAN 48 /* INTR_STATUS_REG_1, bit 13 */ -#define XTENSA_IRQ_RTC_CORE 49 /* INTR_STATUS_REG_1, bit 14 */ -#define XTENSA_IRQ_RMT 50 /* INTR_STATUS_REG_1, bit 15 */ -#define XTENSA_IRQ_PCNT 51 /* INTR_STATUS_REG_1, bit 16 */ -#define XTENSA_IRQ_I2C_EXT0 52 /* INTR_STATUS_REG_1, bit 17 */ -#define XTENSA_IRQ_I2C_EXT1 53 /* INTR_STATUS_REG_1, bit 18 */ -#define XTENSA_IRQ_RSA 54 /* INTR_STATUS_REG_1, bit 19 */ - -#define XTENSA_IRQ_SPI1_DMA 55 /* INTR_STATUS_REG_1, bit 20 */ -#define XTENSA_IRQ_SPI2_DMA 56 /* INTR_STATUS_REG_1, bit 21 */ -#define XTENSA_IRQ_SPI3_DMA 57 /* INTR_STATUS_REG_1, bit 22 */ -#define XTENSA_IRQ_WDG 58 /* INTR_STATUS_REG_1, bit 23 */ -#define XTENSA_IRQ_TIMER1 59 /* INTR_STATUS_REG_1, bit 24 */ -#define XTENSA_IRQ_TIMER2 60 /* INTR_STATUS_REG_1, bit 25 */ -#define XTENSA_IRQ_TG_T0_EDGE 61 /* INTR_STATUS_REG_1, bit 26 */ -#define XTENSA_IRQ_TG_T1_EDGE 62 /* INTR_STATUS_REG_1, bit 27 */ -#define XTENSA_IRQ_TG_WDT_EDGE 63 /* INTR_STATUS_REG_1, bit 28 */ -#define XTENSA_IRQ_TG_LACT_EDGE 64 /* INTR_STATUS_REG_1, bit 29 */ - -#define XTENSA_IRQ_TG1_T0_EDGE 65 /* INTR_STATUS_REG_1, bit 30 */ -#define XTENSA_IRQ_TG1_T1_EDGE 66 /* INTR_STATUS_REG_1, bit 31 */ +#define ESP32_IRQ_I2S0 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_I2S0) +#define ESP32_IRQ_I2S1 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_I2S1) +#define ESP32_IRQ_UART (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_UART) +#define ESP32_IRQ_UART1 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_UART1) +#define ESP32_IRQ_UART2 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_UART2) +#define ESP32_IRQ_SDIO_HOST (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SDIO_HOST) +#define ESP32_IRQ_EMAC (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_EMAC) +#define ESP32_IRQ_PWM0 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_PWM0) +#define ESP32_IRQ_PWM1 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_PWM1) +#define ESP32_IRQ_PWM2 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_PWM2) +#define ESP32_IRQ_PWM3 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_PWM3) +#define ESP32_IRQ_LEDC (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_LEDC) +#define ESP32_IRQ_EFUSE (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_EFUSE) +#define ESP32_IRQ_CAN (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_CAN) +#define ESP32_IRQ_RTC_CORE (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_RTC_CORE) +#define ESP32_IRQ_RMT (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_RMT) +#define ESP32_IRQ_PCNT (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_PCNT) +#define ESP32_IRQ_I2C_EXT0 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_I2C_EXT0) +#define ESP32_IRQ_I2C_EXT1 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_I2C_EXT1) +#define ESP32_IRQ_RSA (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_RSA) +#define ESP32_IRQ_SPI1_DMA (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SPI1_DMA) +#define ESP32_IRQ_SPI2_DMA (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SPI2_DMA) +#define ESP32_IRQ_SPI3_DMA (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SPI3_DMA) +#define ESP32_IRQ_WDG (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_WDG) +#define ESP32_IRQ_TIMER1 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TIMER1) +#define ESP32_IRQ_TIMER2 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TIMER2) +#define ESP32_IRQ_TG_T0_EDGE (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG_T0_EDGE) +#define ESP32_IRQ_TG_T1_EDGE (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG_T1_EDGE) +#define ESP32_IRQ_TG_WDT_EDGE (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG_WDT_EDGE) +#define ESP32_IRQ_TG_LACT_EDGE (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG_LACT_EDGE) +#define ESP32_IRQ_TG1_T0_EDGE (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG1_T0_EDGE) +#define ESP32_IRQ_TG1_T1_EDGE (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG1_T1_EDGE) + +#define ESP32_IRQ_SREG1 ESP32_IRQ_I2S0 +#define ESP32_NIRQS_SREG1 32 /* PRO_INTR_STATUS_REG_2 / APP_INTR_STATUS_REG_2 */ -#define XTENSA_IRQ_SREG2 67 -#define XTENSA_IRQ_TG1_WDT_EDGE 67 /* INTR_STATUS_REG_2, bit 0 */ -#define XTENSA_IRQ_TG1_LACT_EDGE 68 /* INTR_STATUS_REG_2, bit 1 */ -#define XTENSA_IRQ_MMU_IA 69 /* INTR_STATUS_REG_2, bit 2 */ -#define XTENSA_IRQ_MPU_IA 70 /* INTR_STATUS_REG_2, bit 3 */ -#define XTENSA_IRQ_CACHE_IA 71 /* INTR_STATUS_REG_2, bit 4 */ +#define ESP32_IRQ_TG1_WDT_EDGE (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG1_WDT_EDGE) +#define ESP32_IRQ_TG1_LACT_EDGE (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_TG1_LACT_EDGE) +#define ESP32_IRQ_MMU_IA (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_MMU_IA) +#define ESP32_IRQ_MPU_IA (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_MPU_IA) +#define ESP32_IRQ_CACHE_IA (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_CACHE_IA) + +#define ESP32_IRQ_SREG2 ESP32_IRQ_TG1_WDT_EDGE +#define ESP32_NIRQS_SREG2 5 /* Total number of interrupts */ -#define NR_IRQS 72 +#define NR_IRQS (ESP32_IRQ_CACHE_IA+1) + +/* CPU Interrupts. + * + * Each of the two CPUs (PRO and APP) have 32 interrupts each, of which + * 26 can be mapped to peripheral interrupts: + * + * Level triggered peripherals (21 total): + * 0-5, 8-9, 12-13, 17-21, 23-27, 31 + * Edge triggered peripherals (4 total): + * 10, 22, 28, 30 + * NMI (1 total): + * 14 + * + * CPU peripheral interrupts can be a assigned to a CPU interrupt using the + * PRO_*_MAP_REG or APP_*_MAP_REG. There are a pair of these registers for + * each peripheral source. Multiple peripheral interrupt sources can be + * mapped to the same. + * + * The remaining, five, internal CPU interrupts are: + * + * 6 Timer0 + * 7 Software + * 15 Timer1 + * 16 Timer2 + * 29 Software + * + * A peripheral interrupt can be disabled + */ + +#define ESP32_CPUINT_LEVELPERIPH_0 0 +#define ESP32_CPUINT_LEVELPERIPH_1 1 +#define ESP32_CPUINT_LEVELPERIPH_2 2 +#define ESP32_CPUINT_LEVELPERIPH_3 3 +#define ESP32_CPUINT_LEVELPERIPH_4 4 +#define ESP32_CPUINT_LEVELPERIPH_5 5 +#define ESP32_CPUINT_LEVELPERIPH_6 8 +#define ESP32_CPUINT_LEVELPERIPH_7 9 +#define ESP32_CPUINT_LEVELPERIPH_8 12 +#define ESP32_CPUINT_LEVELPERIPH_9 13 +#define ESP32_CPUINT_LEVELPERIPH_10 17 +#define ESP32_CPUINT_LEVELPERIPH_11 18 +#define ESP32_CPUINT_LEVELPERIPH_12 19 +#define ESP32_CPUINT_LEVELPERIPH_13 20 +#define ESP32_CPUINT_LEVELPERIPH_14 21 +#define ESP32_CPUINT_LEVELPERIPH_15 23 +#define ESP32_CPUINT_LEVELPERIPH_16 24 +#define ESP32_CPUINT_LEVELPERIPH_17 25 +#define ESP32_CPUINT_LEVELPERIPH_18 26 +#define ESP32_CPUINT_LEVELPERIPH_19 27 +#define ESP32_CPUINT_LEVELPERIPH_20 31 +#define ESP32_CPUINT_NLEVELPERIPHS 21 + +#define ESP32_CPUINT_EDGEPERIPH_0 10 +#define ESP32_CPUINT_EDGEPERIPH_1 22 +#define ESP32_CPUINT_EDGEPERIPH_2 28 +#define ESP32_CPUINT_EDGEPERIPH_3 30 +#define ESP32_CPUINT_NEDGEPERIPHS 4 + +#define ESP32_CPUINT_TIMER0 6 +#define ESP32_CPUINT_SOFTWARE0 7 +#define ESP32_CPUINT_TIMER1 15 +#define ESP32_CPUINT_TIMER2 16 +#define ESP32_CPUINT_SOFTWARE1 29 +#define ESP32_CPUINT_NINTERNAL 5 + +#define ESP32_CPUINT_MAX 31 +#define EPS32_CPUINT_PERIPHSET 0xdffe7f3f +#define EPS32_CPUINT_INTERNALSET 0x200180c0 /**************************************************************************** * Public Types diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index fb13a8150a..bde2eaba5f 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -156,13 +156,6 @@ extern volatile uint32_t *g_current_regs[1]; #endif -/* This is the beginning of heap as provided from *_head.S. This is the - * first address in DRAM after the loaded program+bss+idle stack. The end - * of the heap is CONFIG_RAM_END - */ - -extern uint32_t g_idle_topstack; - /* Address of the saved user stack pointer */ #if CONFIG_ARCH_INTERRUPTSTACK > 3 @@ -243,6 +236,8 @@ void xtensa_dumpstate(void); uint32_t *xtensa_int_decode(uint32_t *regs); uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs); +uint32_t xtensa_enable_cpuint(uint32_t *shadow, uint32_t intmask); +uint32_t xtensa_disable_cpuint(uint32_t *shadow, uint32_t intmask); /* Software interrupt handler */ diff --git a/arch/xtensa/src/common/xtensa_cpuint.S b/arch/xtensa/src/common/xtensa_cpuint.S new file mode 100644 index 0000000000..8d5b9dd33f --- /dev/null +++ b/arch/xtensa/src/common/xtensa_cpuint.S @@ -0,0 +1,128 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_cpuint.S + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * + * Copyright (c) 2006-2015 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + + .file "xtensa_cpuint.S" + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "xtensa_context.h" + +#if XCHAL_HAVE_INTERRUPTS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_enable_cpuint + * + * C Prototype: + * uint32_t xtensa_enable_cpuint(uint32_t *shadow, unsigned int intmask) + * + * Description: + * Enables a set of interrupts. Does not simply set INTENABLE directly, + * but operates on a shadow copy of the CPU INTENABLE register then + * writes that value to the hardware INTENABLE register. Can be called + * from interrupt handlers. + * + * NOTE: It is possible only to enable interrupts on the current CPU + * because there is an INTENABLE register implemented in each CPU. + * + ****************************************************************************/ + + .text + .global xtensa_enable_cpuint + .type xtensa_enable_cpuint, @function + .align 4 + +xtensa_enable_cpuint: + + movi a4, 0 + xsr a4, INTENABLE /* Disables all interrupts */ + rsync + + l32i a4, a2, 0 /* a4 = value of INTENABLE shadow */ + or a5, a4, a3 /* a5 = shadow | mask */ + s32i a5, a2, 0 /* shadow |= mask */ + + wsr a5, INTENABLE /* Set CPU INTENABLE to shadow */ + mov a3, a4 /* Return previous shadow content */ + ret + + .size xtensa_enable_cpuint, . - xtensa_enable_cpuint + +/**************************************************************************** + * Name: xtensa_disable_cpuint + * + * C Prototype: + * uint32_t xtensa_disable_cpuint(uint32_t *shadow, unsigned int intmask) + * + * Description: + * Disables a set of interrupts. Does not simply set INTENABLE directly, + * but operates on a shadow copy of the CPU INTENABLE register then + * writes that value to the hardware INTENABLE register. Can be called + * from interrupt handlers. + * + * NOTE: It is possible only to enable interrupts on the current CPU + * because there is an INTENABLE register implemented in each CPU. + * + ****************************************************************************/ + + .text + .globa xtensa_disable_cpuint + .type xtensa_disable_cpuint, @function + .align 4 + +xtensa_disable_cpuint: + + movi a4, 0 + xsr a4, INTENABLE /* Disables all interrupts */ + rsync + + l32i a4, a2, 0 /* a4 = value of INTENABLE shadow */ + or a5, a4, a3 /* a5 = shadow | mask */ + xor a5, a5, a3 /* a5 = shadow & ~mask */ + s32i a5, a2, 0 /* shadow &= ~mask */ + + wsr a5, INTENABLE /* Set CPU INTENABLE to shadow */ + mov a3, a4 /* Return previous shadow content */ + ret + + .size xtensa_disable_cpuint, . - xtensa_disable_cpuint + +#endif /* XCHAL_HAVE_INTERRUPTS */ diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 993965dac8..d904abdc6c 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -44,14 +44,15 @@ CMN_ASRCS = xtensa_context.S xtensa_vectors.S xtensa_inthandlers.S CMN_ASRCS += xtensa_nmihandler.S CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c -CMN_CSRCS += xtensa_createstack.c xtensa_exit.c xtensa_idle.c -CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c -CMN_CSRCS += xtensa_interruptcontext.c xtensa_irqdispatch.c xtensa_lowputs.c -CMN_CSRCS += xtensa_mdelay.c xtensa_modifyreg8.c xtensa_modifyreg16.c -CMN_CSRCS += xtensa_modifyreg32.c xtensa_puts.c xtensa_releasepending.c -CMN_CSRCS += xtensa_releasestack.c xtensa_reprioritizertr.c -CMN_CSRCS += xtensa_schedsigaction.c xtensa_sigdeliver.c xtensa_stackframe.c -CMN_CSRCS += xtensa_udelay.c xtensa_unblocktask.c xtensa_usestack.c +CMN_CSRCS += xtens_cpuint.c xtensa_createstack.c xtensa_exit.c +CMN_CSRCS += xtensa_idle.c xtensa_initialize.c xtensa_initialstate.c +CMN_CSRCS += xtensa_interruptcontext.c xtensa_irqdispatch.c +CMN_CSRCS += xtensa_lowputs.c xtensa_mdelay.c xtensa_modifyreg8.c +CMN_CSRCS += xtensa_modifyreg16.c xtensa_modifyreg32.c xtensa_puts.c +CMN_CSRCS += xtensa_releasepending.c xtensa_releasestack.c +CMN_CSRCS += xtensa_reprioritizertr.c xtensa_schedsigaction.c +CMN_CSRCS += xtensa_sigdeliver.c xtensa_stackframe.c xtensa_udelay.c +CMN_CSRCS += xtensa_unblocktask.c xtensa_usestack.c # Configuration-dependent common XTENSA files @@ -77,8 +78,8 @@ endif # Required ESP32 files (arch/xtensa/src/lx6) CHIP_ASRCS = -CHIP_CSRCS = esp32_allocateheap.c esp32_intdecode.c esp32_irq.c -CHIP_CSRCS += esp32_region.c esp32_start.c esp32_timerisr.c +CHIP_CSRCS = esp32_allocateheap.c esp32_cpuint.c esp32_intdecode.c +CHIP_CSRCS += esp32_irq.c esp32_region.c esp32_start.c esp32_timerisr.c # Configuration-dependent ESP32 files diff --git a/arch/xtensa/src/esp32/esp32_cpuint.c b/arch/xtensa/src/esp32/esp32_cpuint.c new file mode 100644 index 0000000000..119e9917e2 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_cpuint.c @@ -0,0 +1,303 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_irq.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "xtensa.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ESP32_INTSET(n) ((1 << (n)) - 1) +#define ESP32_LEVEL_SET ESP32_INTSET(ESP32_CPUINT_NLEVELPERIPHS) +#define ESP32_EDGE_SET ESP32_INTSET(ESP32_CPUINT_NEDGEPERIPHS) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register + * content. + */ + +#ifdef CONFIG_SMP + +static uint32_t *g_intenable[CONFIG_SMP_NCPUS]; + +#else + +static uint32_t *g_intenable[1]; + +#endif + +/* Bitsets for free, unallocated CPU interrupts */ + +status uint32_t g_level_ints = ESP32_LEVEL_SET; +status uint32_t g_edge_ints = ESP32_EDGE_SET; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the CPU interrupt specified by 'cpuint' + * + ****************************************************************************/ + +void up_disable_irq(int cpuint) +{ +#ifdef CONFIG_SMP + int cpu; +#endif + + DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32_CPUINT_MAX); + +#ifdef CONFIG_SMP + cpu = up_cpu_index(); + (void)xtensa_disable_cpuint(&g_intenable[cpu], (1ul << cpuint)) +#else + (void)xtensa_disable_cpuint(&g_intenable[0], (1ul << cpuint)) +#endif +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Ensable the CPU interrupt specified by 'cpuint' + * + ****************************************************************************/ + +void up_enable_irq(int cpuint) +{ +#ifdef CONFIG_SMP + int cpu; +#endif + + DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32_CPUINT_MAX); + +#ifdef CONFIG_SMP + cpu = up_cpu_index(); + (void)xtensa_enable_cpuint(&g_intenable[cpu], (1ul << cpuint)) +#else + (void)xtensa_enable_cpuint(&g_intenable[0], (1ul << cpuint)) +#endif +} + +/**************************************************************************** + * Name: esp32_alloc_levelint + * + * Description: + * Allocate a level CPU interrupt + * + * Input Parameters: + * None + * + * Returned Value: + * On success, the allocated level-sensitive, CPU interrupt numbr is + * returned. A negated errno is returned on failure. The only possible + * failure is that all level-sensitive CPU interrupts have already been + * allocated. + * + ****************************************************************************/ + +int esp32_alloc_levelint(void) +{ + irqstate_t flags; + uint32_t mask; + int cpuint; + int ret = -ENOMEM; + + /* Check if there are any level CPU interrupts available */ + + flags = enter_critical_section(); + if ((g_level_ints & ESP32_LEVEL_SET) != 0) + { + /* Search for an unallocated CPU interrupt number in g_level_ints. */ + + for (cpuint = 0; cpuint < ESP32_CPUINT_NLEVELPERIPHS; cpuint++) + { + /* If the bit corresponding to the CPU interrupt is '1', then + * that CPU interrupt is available. + */ + + mask = (1ul << cpuint); + if ((g_level_ints & mask) != 0) + { + /* Got it! */ + + g_level_ints &= ~mask; + ret = cpuint; + break; + } + } + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: esp32_free_levelint + * + * Description: + * Free a previoulsy allocated level CPU interrupt + * + * Input Parameters: + * The CPU interrupt number to be freed + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32_free_levelint(int cpuint) +{ + irqstate_t flags; + uint32_t mask; + + DEBUGASSERT(cpuint >= 0 && cpuint < ESP32_CPUINT_NLEVELPERIPHS); + + /* Mark the CPU interrupt as available */ + + mask = (1ul << cpuint); + flags = enter_critical_section(); + DEBUGASSERT((g_level_ints & mask) == 0); + g_level_ints |= mask; + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: esp32_alloc_edgeint + * + * Description: + * Allocate an edge CPU interrupt + * + * Input Parameters: + * None + * + * Returned Value: + * On success, the allocated edge-sensitive, CPU interrupt numbr is + * returned. A negated errno is returned on failure. The only possible + * failure is that all edge-sensitive CPU interrupts have already been + * allocated. + * + ****************************************************************************/ + +int esp32_alloc_edgeint(void) +{ + irqstate_t flags; + uint32_t mask; + int cpuint; + int ret = -ENOMEM; + + /* Check if there are any level CPU interrupts available */ + + flags = enter_critical_section(); + if ((g_edge_ints & ESP32_EDGE_SET) != 0) + { + /* Search for an unallocated CPU interrupt number in g_edge_ints. */ + + for (cpuint = 0; cpuint < ESP32_CPUINT_NEDGEPERIPHS; cpuint++) + { + /* If the bit corresponding to the CPU interrupt is '1', then + * that CPU interrupt is available. + */ + + mask = (1ul << cpuint); + if ((g_edge_ints & mask) != 0) + { + /* Got it! */ + + g_edge_ints &= ~mask; + ret = cpuint; + break; + } + } + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: esp32_free_edgeint + * + * Description: + * Free a previoulsy allocated edge CPU interrupt + * + * Input Parameters: + * The CPU interrupt number to be freed + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32_free_edgeint(int cpuint) +{ + irqstate_t flags; + uint32_t mask; + + DEBUGASSERT(cpuint >= 0 && cpuint < ESP32_CPUINT_NEDGEPERIPHS); + + /* Mark the CPU interrupt as available */ + + mask = (1ul << cpuint); + flags = enter_critical_section(); + DEBUGASSERT((g_edge_ints & mask) == 0); + g_edge_ints |= mask; + leave_critical_section(flags); +} diff --git a/arch/xtensa/src/esp32/esp32_cpuint.h b/arch/xtensa/src/esp32/esp32_cpuint.h new file mode 100644 index 0000000000..79aa852096 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_cpuint.h @@ -0,0 +1,119 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_cpuint.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_CPUINT_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_CPUINT_H 1 + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_alloc_levelint + * + * Description: + * Allocate a level CPU interrupt + * + * Input Parameters: + * None + * + * Returned Value: + * On success, the allocated level-sensitive, CPU interrupt numbr is + * returned. A negated errno is returned on failure. The only possible + * failure is that all level-sensitive CPU interrupts have already been + * allocated. + * + ****************************************************************************/ + +int esp32_alloc_levelint(void); + +/**************************************************************************** + * Name: esp32_free_levelint + * + * Description: + * Free a previoulsy allocated level CPU interrupt + * + * Input Parameters: + * The CPU interrupt number to be freed + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32_free_levelint(int cpuint); + +/**************************************************************************** + * Name: esp32_alloc_edgeint + * + * Description: + * Allocate an edge CPU interrupt + * + * Input Parameters: + * None + * + * Returned Value: + * On success, the allocated edge-sensitive, CPU interrupt numbr is + * returned. A negated errno is returned on failure. The only possible + * failure is that all edge-sensitive CPU interrupts have already been + * allocated. + * + ****************************************************************************/ + +int esp32_alloc_edgeint(void); + +/**************************************************************************** + * Name: esp32_free_edgeint + * + * Description: + * Free a previoulsy allocated edge CPU interrupt + * + * Input Parameters: + * The CPU interrupt number to be freed + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32_free_edgeint(int cpuint); + +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_CPUINT_H */ diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c index 038a2851c2..1f4a6d4c01 100644 --- a/arch/xtensa/src/esp32/esp32_cpustart.c +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -83,6 +83,20 @@ static inline void xtensa_registerdump(FAR struct tcb_s *tcb) # define xtensa_registerdump(tcb) #endif +/**************************************************************************** + * Name: xtensa_disable_all + ****************************************************************************/ + +static inline void xtensa_disable_all(void) +{ + __asm__ __volatile__ + ( + "movi a2, 0\n" + "xsr a2, INTENABLE\n" + : : : "a2" + ); +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -127,6 +141,13 @@ int xtensa_start_handler(int irq, FAR void *context) esp32_region_protection(); + /* Disable all PRO CPU interrupts */ + + xtensa_disable_all(); + + /* Disable peripheral sources from all PRO CPU interrupt */ +#warning Missing logic + /* Dump registers so that we can see what is going to happen on return */ xtensa_registerdump(tcb); diff --git a/arch/xtensa/src/esp32/esp32_intdecode.c b/arch/xtensa/src/esp32/esp32_intdecode.c index 5490e614e3..e316274f4b 100644 --- a/arch/xtensa/src/esp32/esp32_intdecode.c +++ b/arch/xtensa/src/esp32/esp32_intdecode.c @@ -44,6 +44,24 @@ #include "chip/esp32_dport.h" #include "xtensa.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint8_t g_baseirq[3] = +{ + ESP32_IRQ_SREG0, + ESP32_IRQ_SREG1, + ESP32_IRQ_SREG2 +}; + +static const uint8_t g_nirqs[3] = +{ + ESP32_NIRQS_SREG0, + ESP32_NIRQS_SREG1, + ESP32_NIRQS_SREG2 +}; + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -94,19 +112,23 @@ uint32_t *xtensa_int_decode(uint32_t *regs) * registers. */ - for (regndx = 0, baseirq = XTENSA_IRQ_SREG0; - regndx < 3; - regndx++, baseirq += 32, regaddr += sizeof(uint32_t)) + for (regndx = 0; regndx < 3; regndx++) { /* Fetch the next register status register */ - regval = getreg32(regaddr); + regval = getreg32(regaddr); + regaddr += sizeof(uint32_t); + + /* Set up the search */ + + baseirq = g_baseirq[regndx]; + nirqs = g_nirqs[regndx] /* Decode and dispatch each pending bit in the interrupt status * register. */ - for (bit = 0; regval != 0 && bit < 32; bit++) + for (bit = 0; regval != 0 && bit < nirqs; bit++) { /* Check if this interrupt is pending */ diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c index d5cf4b552a..6394beb8e1 100644 --- a/arch/xtensa/src/esp32/esp32_irq.c +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -48,10 +48,6 @@ #include "xtensa.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - /**************************************************************************** * Public Data ****************************************************************************/ @@ -62,8 +58,19 @@ * CURRENT_REGS for portability. */ +#ifdef CONFIG_SMP +/* For the case of architectures with multiple CPUs, then there must be one + * such value for each processor that can receive an interrupt. + */ + +volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; + +#else + volatile uint32_t *g_current_regs[1]; +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -89,6 +96,20 @@ static void esp32_irq_dump(const char *msg, int irq) # define esp32_irq_dump(msg, irq) #endif +/**************************************************************************** + * Name: xtensa_disable_all + ****************************************************************************/ + +static inline void xtensa_disable_all(void) +{ + __asm__ __volatile__ + ( + "movi a2, 0\n" + "xsr a2, INTENABLE\n" + : : : "a2" + ); +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -99,7 +120,11 @@ static void esp32_irq_dump(const char *msg, int irq) void xtensa_irq_initialize(void) { - /* Disable all interrupts */ + /* Disable all PRO CPU interrupts */ + + xtensa_disable_all(); + + /* Disable peripheral sources from all PRO CPU interrupt */ #warning Missing logic #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 @@ -111,72 +136,14 @@ void xtensa_irq_initialize(void) /* Set all interrupts (and exceptions) to the default priority */ #warning Missing logic - /* Attach all other processor exceptions (except reset and sys tick) */ + /* Attach all processor exceptions */ #warning Missing logic esp32_irq_dump("initial", NR_IRQS); #ifndef CONFIG_SUPPRESS_INTERRUPTS - /* And finally, enable interrupts */ up_irq_enable(); #endif } - -/**************************************************************************** - * Name: up_disable_irq - * - * Description: - * Disable the IRQ specified by 'irq' - * - ****************************************************************************/ - -void up_disable_irq(int irq) -{ -#warning Missing logic -} - -/**************************************************************************** - * Name: up_enable_irq - * - * Description: - * Enable the IRQ specified by 'irq' - * - ****************************************************************************/ - -void up_enable_irq(int irq) -{ -#warning Missing logic -} - -/**************************************************************************** - * Name: up_ack_irq - * - * Description: - * Acknowledge the IRQ - * - ****************************************************************************/ - -void up_ack_irq(int irq) -{ -} - -/**************************************************************************** - * Name: up_prioritize_irq - * - * Description: - * Set the priority of an IRQ. - * - * Since this API is not supported on all architectures, it should be - * avoided in common implementations where possible. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQPRIO -int up_prioritize_irq(int irq, int priority) -{ -#warning Missing logic - return OK; -} -#endif diff --git a/arch/xtensa/src/esp32/esp32_timerisr.c b/arch/xtensa/src/esp32/esp32_timerisr.c index b5a7871ae4..f809fb45d9 100644 --- a/arch/xtensa/src/esp32/esp32_timerisr.c +++ b/arch/xtensa/src/esp32/esp32_timerisr.c @@ -51,6 +51,14 @@ #include "xtensa_timer.h" #include "xtensa.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if XT_TIMER_INTEN != ESP32_CPUINT_TIMER0 +# error Mismatch in irq.h and xtensa_timer.h +#endif + /**************************************************************************** * Private data ****************************************************************************/ @@ -62,8 +70,7 @@ static uint32_t g_tick_divisor; ****************************************************************************/ /**************************************************************************** - * Function: xtensa_getcount, xtensa_getcompare, xtensa_setcompare, and - * xtensa_enable_timer + * Function: xtensa_getcount, xtensa_getcompare, and xtensa_setcompare * * Description: * Lower level operations on Xtensa special registers. @@ -108,22 +115,6 @@ static inline void xtensa_setcompare(uint32_t compare) ); } -/* Enable the timer interrupt. NOTE: This is non-atomic but safe in this - * context because this occurs early in the initialization sequence. - */ - -static inline void xtensa_enable_timer(void) -{ - __asm__ __volatile__ - ( - "movi a3, %0\n" - "rsr a2, INTENABLE\n" - "or a2, a2, a3\n" - "wsr a2, INTENABLE\n" - : : "I"(XT_TIMER_INTEN) : "a2", "a3" - ); -} - /**************************************************************************** * Function: esp32_timerisr * @@ -212,9 +203,7 @@ void xtensa_timer_initialize(void) (void)irq_attach(XTENSA_IRQ_TIMER0, (xcpt_t)esp32_timerisr); - /* Enable the timer interrupt at the device level. NOTE: It is un-necessary - * to call up_enable_irq() for timers. - */ + /* Enable the timer 0 CPU interrupt. */ - xtensa_enable_timer(); + up_enable_irq(ESP32_CPUINT_TIMER0); } -- GitLab From d5fceadacd04bf653fff54e5f145c1d62a638410 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 25 Oct 2016 12:34:23 -0600 Subject: [PATCH 207/734] Xtensa: Fix some compilation issues --- arch/xtensa/src/common/xtensa_cpuint.S | 8 +++----- arch/xtensa/src/common/xtensa_dumpstate.c | 12 ++++++++++++ arch/xtensa/src/common/xtensa_inthandlers.S | 2 +- arch/xtensa/src/common/xtensa_nmihandler.S | 2 +- arch/xtensa/src/esp32/Make.defs | 20 ++++++++++---------- arch/xtensa/src/esp32/esp32_clockconfig.c | 12 ++++++++---- arch/xtensa/src/esp32/esp32_cpuint.c | 17 +++++++++-------- arch/xtensa/src/esp32/esp32_intdecode.c | 3 ++- arch/xtensa/src/esp32/esp32_timerisr.c | 8 -------- 9 files changed, 46 insertions(+), 38 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_cpuint.S b/arch/xtensa/src/common/xtensa_cpuint.S index 8d5b9dd33f..6ea46d71d4 100644 --- a/arch/xtensa/src/common/xtensa_cpuint.S +++ b/arch/xtensa/src/common/xtensa_cpuint.S @@ -37,10 +37,8 @@ * Included Files ****************************************************************************/ -#include -#include - -#include "xtensa_context.h" +#include +#include #if XCHAL_HAVE_INTERRUPTS @@ -104,7 +102,7 @@ xtensa_enable_cpuint: ****************************************************************************/ .text - .globa xtensa_disable_cpuint + .global xtensa_disable_cpuint .type xtensa_disable_cpuint, @function .align 4 diff --git a/arch/xtensa/src/common/xtensa_dumpstate.c b/arch/xtensa/src/common/xtensa_dumpstate.c index 74de6d74a5..f99f3d905c 100644 --- a/arch/xtensa/src/common/xtensa_dumpstate.c +++ b/arch/xtensa/src/common/xtensa_dumpstate.c @@ -150,12 +150,24 @@ void xtensa_dumpstate(void) uint32_t istacksize; #endif +#ifdef CONFIG_SMP + /* Show the CPU number */ + + _alert("CPU%d:\n", up_cpu_index()); +#endif + /* Get the limits on the user stack memory */ if (rtcb->pid == 0) { +#warning REVISIT: Need top of IDLE stack +#if 0 ustackbase = g_idle_topstack - 4; ustacksize = CONFIG_IDLETHREAD_STACKSIZE; +#else + ustackbase = sp + 128; + ustacksize = 128; +#endif } else { diff --git a/arch/xtensa/src/common/xtensa_inthandlers.S b/arch/xtensa/src/common/xtensa_inthandlers.S index af4e068728..b716c9f1f2 100644 --- a/arch/xtensa/src/common/xtensa_inthandlers.S +++ b/arch/xtensa/src/common/xtensa_inthandlers.S @@ -62,9 +62,9 @@ #include #include #include -#include #include "xtensa_macros.h" +#include "chip_macros.h" #include "xtensa_timer.h" /**************************************************************************** diff --git a/arch/xtensa/src/common/xtensa_nmihandler.S b/arch/xtensa/src/common/xtensa_nmihandler.S index 0720b1fe71..7f10b2ae6a 100644 --- a/arch/xtensa/src/common/xtensa_nmihandler.S +++ b/arch/xtensa/src/common/xtensa_nmihandler.S @@ -61,8 +61,8 @@ #include #include -#include +#include "chip_macros.h" #include "xtensa_macros.h" /**************************************************************************** diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index d904abdc6c..5952d79377 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -40,16 +40,15 @@ HEAD_CSRC = esp32_start.c # Common XTENSA files (arch/xtensa/src/common) -CMN_ASRCS = xtensa_context.S xtensa_vectors.S xtensa_inthandlers.S -CMN_ASRCS += xtensa_nmihandler.S +CMN_ASRCS = xtensa_context.S xtensa_cpuint.S xtensa_vectors.S +CMN_ASRCS += xtensa_inthandlers.S xtensa_nmihandler.S CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c -CMN_CSRCS += xtens_cpuint.c xtensa_createstack.c xtensa_exit.c -CMN_CSRCS += xtensa_idle.c xtensa_initialize.c xtensa_initialstate.c -CMN_CSRCS += xtensa_interruptcontext.c xtensa_irqdispatch.c -CMN_CSRCS += xtensa_lowputs.c xtensa_mdelay.c xtensa_modifyreg8.c -CMN_CSRCS += xtensa_modifyreg16.c xtensa_modifyreg32.c xtensa_puts.c -CMN_CSRCS += xtensa_releasepending.c xtensa_releasestack.c +CMN_CSRCS += xtensa_createstack.c xtensa_exit.c xtensa_idle.c +CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c xtensa_interruptcontext.c +CMN_CSRCS += xtensa_irqdispatch.c xtensa_lowputs.c xtensa_mdelay.c +CMN_CSRCS += xtensa_modifyreg8.c xtensa_modifyreg16.c xtensa_modifyreg32.c +CMN_CSRCS += xtensa_puts.c xtensa_releasepending.c xtensa_releasestack.c CMN_CSRCS += xtensa_reprioritizertr.c xtensa_schedsigaction.c CMN_CSRCS += xtensa_sigdeliver.c xtensa_stackframe.c xtensa_udelay.c CMN_CSRCS += xtensa_unblocktask.c xtensa_usestack.c @@ -78,8 +77,9 @@ endif # Required ESP32 files (arch/xtensa/src/lx6) CHIP_ASRCS = -CHIP_CSRCS = esp32_allocateheap.c esp32_cpuint.c esp32_intdecode.c -CHIP_CSRCS += esp32_irq.c esp32_region.c esp32_start.c esp32_timerisr.c +CHIP_CSRCS = esp32_allocateheap.c esp32_clockconfig.c esp32_cpuint.c +CHIP_CSRCS += esp32_intdecode.c esp32_irq.c esp32_region.c esp32_start.c +CHIP_CSRCS += esp32_timerisr.c # Configuration-dependent ESP32 files diff --git a/arch/xtensa/src/esp32/esp32_clockconfig.c b/arch/xtensa/src/esp32/esp32_clockconfig.c index 2da4e0b4de..7ccc12090e 100644 --- a/arch/xtensa/src/esp32/esp32_clockconfig.c +++ b/arch/xtensa/src/esp32/esp32_clockconfig.c @@ -13,7 +13,7 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - + * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software @@ -26,21 +26,24 @@ /**************************************************************************** * Included Files - **************************************************************************** + ****************************************************************************/ #include #include "xtensa.h" +#ifndef CONFIG_SUPPRESS_CLOCK_CONFIG #warning REVISIT ... function prototypes void phy_get_romfunc_addr(void); void rtc_init_lite(void); void rtc_set_cpu_freq(xtal_freq_t xtal_freq, enum xtal_freq_e cpu_freq); +#endif /**************************************************************************** * Private Types - **************************************************************************** + ****************************************************************************/ +#ifndef CONFIG_SUPPRESS_CLOCK_CONFIG enum xtal_freq_e { XTAL_40M = 40, @@ -55,10 +58,11 @@ enum xtal_freq_e CPU_160M = 2, CPU_240M = 3, }; +#endif /**************************************************************************** * Public Functions - **************************************************************************** + ****************************************************************************/ /**************************************************************************** * Name: esp32_clockconfig diff --git a/arch/xtensa/src/esp32/esp32_cpuint.c b/arch/xtensa/src/esp32/esp32_cpuint.c index 119e9917e2..42d56e9566 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.c +++ b/arch/xtensa/src/esp32/esp32_cpuint.c @@ -41,6 +41,7 @@ #include #include +#include #include #include @@ -67,18 +68,18 @@ #ifdef CONFIG_SMP -static uint32_t *g_intenable[CONFIG_SMP_NCPUS]; +static uint32_t g_intenable[CONFIG_SMP_NCPUS]; #else -static uint32_t *g_intenable[1]; +static uint32_t g_intenable[1]; #endif /* Bitsets for free, unallocated CPU interrupts */ -status uint32_t g_level_ints = ESP32_LEVEL_SET; -status uint32_t g_edge_ints = ESP32_EDGE_SET; +static uint32_t g_level_ints = ESP32_LEVEL_SET; +static uint32_t g_edge_ints = ESP32_EDGE_SET; /**************************************************************************** * Private Functions @@ -106,9 +107,9 @@ void up_disable_irq(int cpuint) #ifdef CONFIG_SMP cpu = up_cpu_index(); - (void)xtensa_disable_cpuint(&g_intenable[cpu], (1ul << cpuint)) + (void)xtensa_disable_cpuint(&g_intenable[cpu], (1ul << cpuint)); #else - (void)xtensa_disable_cpuint(&g_intenable[0], (1ul << cpuint)) + (void)xtensa_disable_cpuint(&g_intenable[0], (1ul << cpuint)); #endif } @@ -130,9 +131,9 @@ void up_enable_irq(int cpuint) #ifdef CONFIG_SMP cpu = up_cpu_index(); - (void)xtensa_enable_cpuint(&g_intenable[cpu], (1ul << cpuint)) + (void)xtensa_enable_cpuint(&g_intenable[cpu], (1ul << cpuint)); #else - (void)xtensa_enable_cpuint(&g_intenable[0], (1ul << cpuint)) + (void)xtensa_enable_cpuint(&g_intenable[0], (1ul << cpuint)); #endif } diff --git a/arch/xtensa/src/esp32/esp32_intdecode.c b/arch/xtensa/src/esp32/esp32_intdecode.c index e316274f4b..d75cf08914 100644 --- a/arch/xtensa/src/esp32/esp32_intdecode.c +++ b/arch/xtensa/src/esp32/esp32_intdecode.c @@ -91,6 +91,7 @@ uint32_t *xtensa_int_decode(uint32_t *regs) int regndx; int bit; int baseirq; + int nirqs; #ifdef CONFIG_SMP int cpu; @@ -122,7 +123,7 @@ uint32_t *xtensa_int_decode(uint32_t *regs) /* Set up the search */ baseirq = g_baseirq[regndx]; - nirqs = g_nirqs[regndx] + nirqs = g_nirqs[regndx]; /* Decode and dispatch each pending bit in the interrupt status * register. diff --git a/arch/xtensa/src/esp32/esp32_timerisr.c b/arch/xtensa/src/esp32/esp32_timerisr.c index f809fb45d9..639934d535 100644 --- a/arch/xtensa/src/esp32/esp32_timerisr.c +++ b/arch/xtensa/src/esp32/esp32_timerisr.c @@ -51,14 +51,6 @@ #include "xtensa_timer.h" #include "xtensa.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if XT_TIMER_INTEN != ESP32_CPUINT_TIMER0 -# error Mismatch in irq.h and xtensa_timer.h -#endif - /**************************************************************************** * Private data ****************************************************************************/ -- GitLab From 2d7b1ccdda01fc4b3bf00dc59432f1feac8fd998 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Tue, 25 Oct 2016 12:52:56 -0600 Subject: [PATCH 208/734] STM32F1 Mimumum: Fix Timers 2 to 7 clock frequencies --- configs/stm32f103-minimum/include/board.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/configs/stm32f103-minimum/include/board.h b/configs/stm32f103-minimum/include/board.h index 8e983ae351..1dc84378c7 100644 --- a/configs/stm32f103-minimum/include/board.h +++ b/configs/stm32f103-minimum/include/board.h @@ -114,12 +114,12 @@ * Note: TIM1,8 are on APB2, others on APB1 */ #define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_PCLK1_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_PCLK1_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_PCLK1_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_PCLK1_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_PCLK1_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_PCLK1_FREQUENCY #define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY /* SDIO dividers. Note that slower clocking is required when DMA is disabled -- GitLab From 6756b44dc3969f2302ec5d9d7be203de8d24b384 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 25 Oct 2016 13:16:05 -0600 Subject: [PATCH 209/734] ESP32: Add framework to assign a a peripheral to a CPU interrupt --- arch/xtensa/src/esp32/esp32_cpuint.c | 41 ++++++++++++++++++++++++++++ arch/xtensa/src/esp32/esp32_cpuint.h | 35 ++++++++++++++++++++++++ 2 files changed, 76 insertions(+) diff --git a/arch/xtensa/src/esp32/esp32_cpuint.c b/arch/xtensa/src/esp32/esp32_cpuint.c index 42d56e9566..0bdebfa76b 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.c +++ b/arch/xtensa/src/esp32/esp32_cpuint.c @@ -302,3 +302,44 @@ void esp32_free_edgeint(int cpuint) g_edge_ints |= mask; leave_critical_section(flags); } + +/**************************************************************************** + * Name: esp32_attach_peripheral + * + * Description: + * Attach a peripheral interupt to a CPU interrupt. + * + * Input Parameters: + * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU + * periphid - The peripheral number from ira.h to be assigned. + * cpuint - The CPU interrupt to receive the peripheral interrupt + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32_attach_peripheral(int cpu, int periphid, int cpuint) +{ +# warning Missing logic +} + +/**************************************************************************** + * Name: esp32_detach_peripheral + * + * Description: + * Detach a peripheral interupt from a CPU interrupt. + * + * Input Parameters: + * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU + * cpuint - The CPU interrupt to receive the peripheral interrupt + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32_detach_peripheral(int cpu, int cpuint) +{ +# warning Missing logic +} diff --git a/arch/xtensa/src/esp32/esp32_cpuint.h b/arch/xtensa/src/esp32/esp32_cpuint.h index 79aa852096..f3bbbaf4a4 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.h +++ b/arch/xtensa/src/esp32/esp32_cpuint.h @@ -116,4 +116,39 @@ int esp32_alloc_edgeint(void); void esp32_free_edgeint(int cpuint); +/**************************************************************************** + * Name: esp32_attach_peripheral + * + * Description: + * Attach a peripheral interupt to a CPU interrupt. + * + * Input Parameters: + * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU + * periphid - The peripheral number from ira.h to be assigned. + * cpuint - The CPU interrupt to receive the peripheral interrupt + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32_attach_peripheral(int cpu, int periphid, int cpuint); + +/**************************************************************************** + * Name: esp32_detach_peripheral + * + * Description: + * Detach a peripheral interupt from a CPU interrupt. + * + * Input Parameters: + * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU + * cpuint - The CPU interrupt to receive the peripheral interrupt + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32_detach_peripheral(int cpu, int cpuint); + #endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_CPUINT_H */ -- GitLab From 483f01260023e37a611cee5e5bbad52195c1e24f Mon Sep 17 00:00:00 2001 From: Marc Rechte Date: Tue, 25 Oct 2016 14:14:10 -0600 Subject: [PATCH 210/734] Initial implemention of the STM32 F37xx SDADC module. There are also changes to ADC, DAC modules. SDADC has only been tested in DMA mode and does not support external TIMER triggers. This is a work in progress. --- arch/arm/include/stm32/chip.h | 4 +- arch/arm/src/stm32/Kconfig | 84 + arch/arm/src/stm32/Make.defs | 6 + arch/arm/src/stm32/chip/stm32_dac.h | 64 +- arch/arm/src/stm32/chip/stm32_pwr.h | 11 +- arch/arm/src/stm32/chip/stm32f30xxx_adc.h | 4 +- arch/arm/src/stm32/chip/stm32f37xxx_adc.h | 321 ++++ .../src/stm32/chip/stm32f37xxx_memorymap.h | 4 +- arch/arm/src/stm32/chip/stm32f37xxx_pinmap.h | 73 +- arch/arm/src/stm32/chip/stm32f37xxx_rcc.h | 46 +- arch/arm/src/stm32/chip/stm32f37xxx_sdadc.h | 304 ++++ arch/arm/src/stm32/stm32.h | 1 + arch/arm/src/stm32/stm32_adc.c | 75 +- arch/arm/src/stm32/stm32_adc.h | 2 + arch/arm/src/stm32/stm32_dac.c | 93 +- arch/arm/src/stm32/stm32_i2c.h | 2 +- arch/arm/src/stm32/stm32_pwr.c | 40 + arch/arm/src/stm32/stm32_pwr.h | 18 + arch/arm/src/stm32/stm32_sdadc.c | 1456 +++++++++++++++++ arch/arm/src/stm32/stm32_sdadc.h | 426 +++++ arch/arm/src/stm32/stm32f30xxx_i2c.c | 4 +- arch/arm/src/stm32/stm32f37xxx_rcc.c | 57 +- configs/nucleo-f303re/src/Makefile | 4 + configs/nucleo-f303re/src/nucleo-f303re.h | 14 + configs/nucleo-f303re/src/stm32_adc.c | 276 +++- .../nucleo-f303re/src/stm32_appinitialize.c | 30 + 26 files changed, 3267 insertions(+), 152 deletions(-) create mode 100644 arch/arm/src/stm32/chip/stm32f37xxx_adc.h create mode 100644 arch/arm/src/stm32/chip/stm32f37xxx_sdadc.h create mode 100644 arch/arm/src/stm32/stm32_sdadc.c create mode 100644 arch/arm/src/stm32/stm32_sdadc.h diff --git a/arch/arm/include/stm32/chip.h b/arch/arm/include/stm32/chip.h index e476bff892..8f06701b51 100644 --- a/arch/arm/include/stm32/chip.h +++ b/arch/arm/include/stm32/chip.h @@ -1101,7 +1101,6 @@ * c = C (48pins) R (68 pins) V (100 pins) * c = K (32 pins), C (48 pins), R (68 pins), V (100 pins) * f = 6 (32KB FLASH), 8 (64KB FLASH), B (128KB FLASH), C (256KB FLASH) - * f = 8 (64KB FLASH), B (128KB FLASH), C (256KB FLASH) * xxx = Package, temperature range, options (ignored here) */ @@ -1534,7 +1533,8 @@ # define STM32_NLCD 0 /* (0) No LCD */ # define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ # define STM32_NGPIO 87 /* GPIOA-F */ -# define STM32_NADC 1 /* (3) 12-bit ADC1 */ +# define STM32_NADC 1 /* (1) 12-bit ADC1 */ +# define STM32_NSDADC 3 /* (3) 16-bit SDADC1-3 */ # define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */ # define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ # define STM32_NCRC 1 /* (1) CRC calculation unit */ diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index f914f760e1..abfdf71985 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -1394,6 +1394,9 @@ config STM32_STM32F37XX select STM32_HAVE_TIM15 select STM32_HAVE_TIM16 select STM32_HAVE_TIM17 + select STM32_HAVE_SDADC1 + select STM32_HAVE_SDADC2 + select STM32_HAVE_SDADC3 select STM32_HAVE_CAN1 select STM32_HAVE_DAC1 select STM32_HAVE_DAC2 @@ -1777,6 +1780,30 @@ config STM32_HAVE_ADC4_DMA bool default n +config STM32_HAVE_SDADC1 + bool + default n + +config STM32_HAVE_SDADC2 + bool + default n + +config STM32_HAVE_SDADC3 + bool + default n + +config STM32_HAVE_SDADC1_DMA + bool + default n + +config STM32_HAVE_SDADC2_DMA + bool + default n + +config STM32_HAVE_SDADC3_DMA + bool + default n + config STM32_HAVE_CAN1 bool default n @@ -1844,6 +1871,7 @@ config STM32_ADC1 default n select STM32_ADC select STM32_HAVE_ADC1_DMA if STM32_STM32F10XX && STM32_DMA1 + select STM32_HAVE_ADC1_DMA if STM32_STM32F37XX && STM32_DMA1 select STM32_HAVE_ADC1_DMA if !STM32_STM32F10XX && STM32_DMA2 config STM32_ADC2 @@ -1867,6 +1895,27 @@ config STM32_ADC4 depends on STM32_HAVE_ADC4 select STM32_HAVE_ADC4_DMA if STM32_DMA2 +config STM32_SDADC1 + bool "SDADC1" + default n + select STM32_SDADC + depends on STM32_HAVE_SDADC1 + select STM32_HAVE_SDADC1_DMA if STM32_DMA2 + +config STM32_SDADC2 + bool "SDADC2" + default n + select STM32_SDADC + depends on STM32_HAVE_SDADC2 + select STM32_HAVE_SDADC2_DMA if STM32_DMA2 + +config STM32_SDADC3 + bool "SDADC3" + default n + select STM32_SDADC + depends on STM32_HAVE_SDADC3 + select STM32_HAVE_SDADC3_DMA if STM32_DMA2 + config STM32_COMP bool "COMP" default n @@ -2239,6 +2288,9 @@ endmenu config STM32_ADC bool +config STM32_SDADC + bool + config STM32_DAC bool @@ -5403,6 +5455,38 @@ config STM32_ADC4_DMA endmenu +menu "SDADC Configuration" + depends on STM32_SDADC + +config STM32_SDADC1_DMA + bool "SDADC1 DMA" + depends on STM32_SDADC1 && STM32_HAVE_SDADC1_DMA + default n + ---help--- + If DMA is selected, then the SDADC may be configured to support + DMA transfer, which is advisable if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_SDADC2_DMA + bool "SDADC2 DMA" + depends on STM32_SDADC2 && STM32_HAVE_SDADC2_DMA + default n + ---help--- + If DMA is selected, then the SDADC may be configured to support + DMA transfer, which is advisable if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_SDADC3_DMA + bool "SDADC3 DMA" + depends on STM32_SDADC3 && STM32_HAVE_SDADC3_DMA + default n + ---help--- + If DMA is selected, then the SDADC may be configured to support + DMA transfer, which is advisable if multiple channels are read + or if very high trigger frequencies are used. + +endmenu + menu "DAC Configuration" depends on STM32_DAC1 || STM32_DAC2 diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs index 31bd92eee4..5cd3564893 100644 --- a/arch/arm/src/stm32/Make.defs +++ b/arch/arm/src/stm32/Make.defs @@ -148,6 +148,8 @@ ifeq ($(CONFIG_STM32_I2C_ALT),y) CHIP_CSRCS += stm32_i2c_alt.c else ifeq ($(CONFIG_STM32_STM32F30XX),y) CHIP_CSRCS += stm32f30xxx_i2c.c +else ifeq ($(CONFIG_STM32_STM32F37XX),y) +CHIP_CSRCS += stm32f30xxx_i2c.c else ifeq ($(CONFIG_STM32_STM32F40XX),y) CHIP_CSRCS += stm32f40xxx_i2c.c else @@ -217,6 +219,10 @@ ifeq ($(CONFIG_STM32_ADC),y) CHIP_CSRCS += stm32_adc.c endif +ifeq ($(CONFIG_STM32_SDADC),y) +CHIP_CSRCS += stm32_sdadc.c +endif + ifeq ($(CONFIG_DAC),y) CHIP_CSRCS += stm32_dac.c endif diff --git a/arch/arm/src/stm32/chip/stm32_dac.h b/arch/arm/src/stm32/chip/stm32_dac.h index 1eadecb894..81a69b71e6 100644 --- a/arch/arm/src/stm32/chip/stm32_dac.h +++ b/arch/arm/src/stm32/chip/stm32_dac.h @@ -66,20 +66,56 @@ /* Register Addresses ***************************************************************/ -#define STM32_DAC_CR (STM32_DAC_BASE+STM32_DAC_CR_OFFSET) -#define STM32_DAC_SWTRIGR (STM32_DAC_BASE+STM32_DAC_SWTRIGR_OFFSET) -#define STM32_DAC_DHR12R1 (STM32_DAC_BASE+STM32_DAC_DHR12R1_OFFSET) -#define STM32_DAC_DHR12L1 (STM32_DAC_BASE+STM32_DAC_DHR12L1_OFFSET) -#define STM32_DAC_DHR8R1 (STM32_DAC_BASE+STM32_DAC_DHR8R1_OFFSET) -#define STM32_DAC_DHR12R2 (STM32_DAC_BASE+STM32_DAC_DHR12R2_OFFSET) -#define STM32_DAC_DHR12L2 (STM32_DAC_BASE+STM32_DAC_DHR12L2_OFFSET) -#define STM32_DAC_DHR8R2 (STM32_DAC_BASE+STM32_DAC_DHR8R2_OFFSET) -#define STM32_DAC_DHR12RD (STM32_DAC_BASE+STM32_DAC_DHR12RD_OFFSET) -#define STM32_DAC_DHR12LD (STM32_DAC_BASE+STM32_DAC_DHR12LD_OFFSET) -#define STM32_DAC_DHR8RD (STM32_DAC_BASE+STM32_DAC_DHR8RD_OFFSET) -#define STM32_DAC_DOR1 (STM32_DAC_BASE+STM32_DAC_DOR1_OFFSET) -#define STM32_DAC_DOR2 (STM32_DAC_BASE+STM32_DAC_DOR2_OFFSET) -#define STM32_DAC_SR (STM32_DAC_BASE+STM32_DAC_SR_OFFSET) +#if STM32_NDAC < 2 +# define STM32_DAC_CR (STM32_DAC_BASE+STM32_DAC_CR_OFFSET) +# define STM32_DAC_SWTRIGR (STM32_DAC_BASE+STM32_DAC_SWTRIGR_OFFSET) +# define STM32_DAC_DHR12R1 (STM32_DAC_BASE+STM32_DAC_DHR12R1_OFFSET) +# define STM32_DAC_DHR12L1 (STM32_DAC_BASE+STM32_DAC_DHR12L1_OFFSET) +# define STM32_DAC_DHR8R1 (STM32_DAC_BASE+STM32_DAC_DHR8R1_OFFSET) +# define STM32_DAC_DHR12R2 (STM32_DAC_BASE+STM32_DAC_DHR12R2_OFFSET) +# define STM32_DAC_DHR12L2 (STM32_DAC_BASE+STM32_DAC_DHR12L2_OFFSET) +# define STM32_DAC_DHR8R2 (STM32_DAC_BASE+STM32_DAC_DHR8R2_OFFSET) +# define STM32_DAC_DHR12RD (STM32_DAC_BASE+STM32_DAC_DHR12RD_OFFSET) +# define STM32_DAC_DHR12LD (STM32_DAC_BASE+STM32_DAC_DHR12LD_OFFSET) +# define STM32_DAC_DHR8RD (STM32_DAC_BASE+STM32_DAC_DHR8RD_OFFSET) +# define STM32_DAC_DOR1 (STM32_DAC_BASE+STM32_DAC_DOR1_OFFSET) +# define STM32_DAC_DOR2 (STM32_DAC_BASE+STM32_DAC_DOR2_OFFSET) +# define STM32_DAC_SR (STM32_DAC_BASE+STM32_DAC_SR_OFFSET) +#else +/* DAC1 */ + +# define STM32_DAC1_CR (STM32_DAC1_BASE+STM32_DAC_CR_OFFSET) +# define STM32_DAC1_SWTRIGR (STM32_DAC1_BASE+STM32_DAC_SWTRIGR_OFFSET) +# define STM32_DAC1_DHR12R1 (STM32_DAC1_BASE+STM32_DAC_DHR12R1_OFFSET) +# define STM32_DAC1_DHR12L1 (STM32_DAC1_BASE+STM32_DAC_DHR12L1_OFFSET) +# define STM32_DAC1_DHR8R1 (STM32_DAC1_BASE+STM32_DAC_DHR8R1_OFFSET) +# define STM32_DAC1_DHR12R2 (STM32_DAC1_BASE+STM32_DAC_DHR12R2_OFFSET) +# define STM32_DAC1_DHR12L2 (STM32_DAC1_BASE+STM32_DAC_DHR12L2_OFFSET) +# define STM32_DAC1_DHR8R2 (STM32_DAC1_BASE+STM32_DAC_DHR8R2_OFFSET) +# define STM32_DAC1_DHR12RD (STM32_DAC1_BASE+STM32_DAC_DHR12RD_OFFSET) +# define STM32_DAC1_DHR12LD (STM32_DAC1_BASE+STM32_DAC_DHR12LD_OFFSET) +# define STM32_DAC1_DHR8RD (STM32_DAC1_BASE+STM32_DAC_DHR8RD_OFFSET) +# define STM32_DAC1_DOR1 (STM32_DAC1_BASE+STM32_DAC_DOR1_OFFSET) +# define STM32_DAC1_DOR2 (STM32_DAC1_BASE+STM32_DAC_DOR2_OFFSET) +# define STM32_DAC1_SR (STM32_DAC1_BASE+STM32_DAC_SR_OFFSET) + +/* DAC2 */ + +# define STM32_DAC2_CR (STM32_DAC2_BASE+STM32_DAC_CR_OFFSET) +# define STM32_DAC2_SWTRIGR (STM32_DAC2_BASE+STM32_DAC_SWTRIGR_OFFSET) +# define STM32_DAC2_DHR12R1 (STM32_DAC2_BASE+STM32_DAC_DHR12R1_OFFSET) +# define STM32_DAC2_DHR12L1 (STM32_DAC2_BASE+STM32_DAC_DHR12L1_OFFSET) +# define STM32_DAC2_DHR8R1 (STM32_DAC2_BASE+STM32_DAC_DHR8R1_OFFSET) +# define STM32_DAC2_DHR12R2 (STM32_DAC2_BASE+STM32_DAC_DHR12R2_OFFSET) +# define STM32_DAC2_DHR12L2 (STM32_DAC2_BASE+STM32_DAC_DHR12L2_OFFSET) +# define STM32_DAC2_DHR8R2 (STM32_DAC2_BASE+STM32_DAC_DHR8R2_OFFSET) +# define STM32_DAC2_DHR12RD (STM32_DAC2_BASE+STM32_DAC_DHR12RD_OFFSET) +# define STM32_DAC2_DHR12LD (STM32_DAC2_BASE+STM32_DAC_DHR12LD_OFFSET) +# define STM32_DAC2_DHR8RD (STM32_DAC2_BASE+STM32_DAC_DHR8RD_OFFSET) +# define STM32_DAC2_DOR1 (STM32_DAC2_BASE+STM32_DAC_DOR1_OFFSET) +# define STM32_DAC2_DOR2 (STM32_DAC2_BASE+STM32_DAC_DOR2_OFFSET) +# define STM32_DAC2_SR (STM32_DAC2_BASE+STM32_DAC_SR_OFFSET) +#endif /* Register Bitfield Definitions ****************************************************/ diff --git a/arch/arm/src/stm32/chip/stm32_pwr.h b/arch/arm/src/stm32/chip/stm32_pwr.h index 9c1e64e57b..f2c2fdde0b 100644 --- a/arch/arm/src/stm32/chip/stm32_pwr.h +++ b/arch/arm/src/stm32/chip/stm32_pwr.h @@ -105,6 +105,12 @@ # endif #endif +#if defined(CONFIG_STM32_STM32F37XX) +#define PWR_CR_ENSD1 (1 << 9) /* Bit 9: Enable SDADC1 */ +#define PWR_CR_ENSD2 (1 << 10) /* Bit 10: Enable SDADC2 */ +#define PWR_CR_ENSD3 (1 << 11) /* Bit 11: Enable SDADC3 */ +#endif + #if defined(CONFIG_STM32_STM32L15XX) # define PWR_CR_ULP (1 << 9) /* Ultralow power mode */ # define PWR_CR_FWU (1 << 10) /* Fast wake-up */ @@ -132,7 +138,8 @@ #define PWR_CSR_SBF (1 << 1) /* Bit 1: Standby Flag */ #define PWR_CSR_PVDO (1 << 2) /* Bit 2: PVD Output */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32F40XX) # define PWR_CSR_BRR (1 << 3) /* Bit 3: Backup regulator ready */ #elif defined(CONFIG_STM32_STM32L15XX) # define PWR_CSR_VREFINTRDYF (1 << 3) /* Bit 3: Internal voltage reference (VREFINT) ready flag */ @@ -143,7 +150,7 @@ #if defined(CONFIG_STM32_STM32F30XX) # define PWR_CSR_EWUP1 (1 << 8) /* Bit 8: Enable WKUP1 pin */ # define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */ -#elif defined(CONFIG_STM32_STM32L15XX) +#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F37XX) # define PWR_CSR_EWUP1 (1 << 8) /* Bit 8: Enable WKUP1 pin */ # define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */ # define PWR_CSR_EWUP3 (1 << 10) /* Bit 8: Enable WKUP3 pin */ diff --git a/arch/arm/src/stm32/chip/stm32f30xxx_adc.h b/arch/arm/src/stm32/chip/stm32f30xxx_adc.h index 5763260eb9..7c9da24b0c 100644 --- a/arch/arm/src/stm32/chip/stm32f30xxx_adc.h +++ b/arch/arm/src/stm32/chip/stm32f30xxx_adc.h @@ -60,8 +60,8 @@ #define STM32_ADC_SMPR1_OFFSET 0x0014 /* ADC sample time register 1 */ #define STM32_ADC_SMPR2_OFFSET 0x0018 /* ADC sample time register 2 */ #define STM32_ADC_TR1_OFFSET 0x0020 /* ADC watchdog threshold register 1 */ -#define STM32_ADC_TR2_OFFSET 0x0020 /* ADC watchdog threshold register 2 */ -#define STM32_ADC_TR3_OFFSET 0x0020 /* ADC watchdog threshold register 3 */ +#define STM32_ADC_TR2_OFFSET 0x0024 /* ADC watchdog threshold register 2 */ +#define STM32_ADC_TR3_OFFSET 0x0028 /* ADC watchdog threshold register 3 */ #define STM32_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 */ #define STM32_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 */ #define STM32_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 */ diff --git a/arch/arm/src/stm32/chip/stm32f37xxx_adc.h b/arch/arm/src/stm32/chip/stm32f37xxx_adc.h new file mode 100644 index 0000000000..95a40ade44 --- /dev/null +++ b/arch/arm/src/stm32/chip/stm32f37xxx_adc.h @@ -0,0 +1,321 @@ +/**************************************************************************************************** + * arch/arm/src/stm32/chip/stm32f30xxx_adc.h + * + * Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Studelec SA. All rights reserved. + * Authors: Gregory Nutt + * Marc Rechté + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_ADC_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_ADC_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register */ +#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 */ +#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 */ +#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 */ +#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 */ +#define STM32_ADC_JOFR1_OFFSET 0x0014 /* ADC injected channel data offset register 1 */ +#define STM32_ADC_JOFR2_OFFSET 0x0018 /* ADC injected channel data offset register 2 */ +#define STM32_ADC_JOFR3_OFFSET 0x001c /* ADC injected channel data offset register 3 */ +#define STM32_ADC_JOFR4_OFFSET 0x0020 /* ADC injected channel data offset register 4 */ +#define STM32_ADC_HTR_OFFSET 0x0024 /* ADC watchdog high threshold register */ +#define STM32_ADC_LTR_OFFSET 0x0028 /* ADC watchdog low threshold register */ +#define STM32_ADC_SQR1_OFFSET 0x002c /* ADC regular sequence register 1 */ +#define STM32_ADC_SQR2_OFFSET 0x0030 /* ADC regular sequence register 2 */ +#define STM32_ADC_SQR3_OFFSET 0x0034 /* ADC regular sequence register 3 */ +#define STM32_ADC_JSQR_OFFSET 0x0038 /* ADC injected sequence register */ +#define STM32_ADC_JDR1_OFFSET 0x003c /* ADC injected data register 1 */ +#define STM32_ADC_JDR2_OFFSET 0x0040 /* ADC injected data register 2 */ +#define STM32_ADC_JDR3_OFFSET 0x0044 /* ADC injected data register 3 */ +#define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 4 */ +#define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register */ + +/* Register Addresses *******************************************************************************/ + +#define STM32_ADC_SR (STM32_ADC_BASE+STM32_ADC_SR_OFFSET) +#define STM32_ADC_CR1 (STM32_ADC_BASE+STM32_ADC_CR1_OFFSET) +#define STM32_ADC_CR2 (STM32_ADC_BASE+STM32_ADC_CR2_OFFSET) +#define STM32_ADC_SMPR1 (STM32_ADC_BASE+STM32_ADC_SMPR1_OFFSET) +#define STM32_ADC_SMPR2 (STM32_ADC_BASE+STM32_ADC_SMPR2_OFFSET) +#define STM32_ADC_JOFR1 (STM32_ADC_BASE+STM32_ADC_JOFR1_OFFSET) +#define STM32_ADC_JOFR2 (STM32_ADC_BASE+STM32_ADC_JOFR2_OFFSET) +#define STM32_ADC_JOFR3 (STM32_ADC_BASE+STM32_ADC_JOFR3_OFFSET) +#define STM32_ADC_JOFR4 (STM32_ADC_BASE+STM32_ADC_JOFR4_OFFSET) +#define STM32_ADC_HTR (STM32_ADC_BASE+STM32_ADC_HTR_OFFSET) +#define STM32_ADC_LTR (STM32_ADC_BASE+STM32_ADC_LTR_OFFSET) +#define STM32_ADC_SQR1 (STM32_ADC_BASE+STM32_ADC_SQR1_OFFSET) +#define STM32_ADC_SQR2 (STM32_ADC_BASE+STM32_ADC_SQR2_OFFSET) +#define STM32_ADC_SQR3 (STM32_ADC_BASE+STM32_ADC_SQR3_OFFSET) +#define STM32_ADC_JSQR (STM32_ADC_BASE+STM32_ADC_JSQR_OFFSET) +#define STM32_ADC_JDR1 (STM32_ADC_BASE+STM32_ADC_JDR1_OFFSET) +#define STM32_ADC_JDR2 (STM32_ADC_BASE+STM32_ADC_JDR2_OFFSET) +#define STM32_ADC_JDR3 (STM32_ADC_BASE+STM32_ADC_JDR3_OFFSET) +#define STM32_ADC_JDR4 (STM32_ADC_BASE+STM32_ADC_JDR4_OFFSET) +#define STM32_ADC_DR (STM32_ADC_BASE+STM32_ADC_DR_OFFSET) + +/* Register Bitfield Definitions ********************************************************************/ +/* ADC status register (SR) */ + +#define ADC_SR_AWD (1 << 0) /* Bit 0: Analog wtchdog flag */ +#define ADC_SR_EOC (1 << 1) /* Bit 1: End of conversion */ +#define ADC_SR_JEOC (1 << 2) /* Bit 2: Injected channel end of conversion */ +#define ADC_SR_JSTRT (1 << 3) /* Bit 3: Injected channel start flag */ +#define ADC_SR_RSTRT (1 << 4) /* Bit 4: Regular channel start flag */ + +/* ADC control register 1 */ + +#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 0-4: Analog watchdog channel select bits */ +#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT) +#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable EOC */ +#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog watchdog interrupt enable */ +#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */ +#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */ +#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */ +#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */ +#define ADC_CR1_DISNUM_SHIFT (13) /* Bit 13-15: Discontinuous mode channel count */ +#define ADC_CR1_DISNUM_MASK (0x7 << ADC_CR1_DISNUM_SHIFT) +#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */ + +/* ADC control register 2 */ + +#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D converter ON / OFF */ +#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous conversion */ +#define ADC_CR2_CAL (1 << 2) /* Bit 2: A/D Calibration */ +#define ADC_CR2_RSTCAL (1 << 3) /* Bit 3: Reset calibration */ +#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct memory access mode */ +#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data alignment */ +#define ADC_CR2_JEXTSEL_SHIFT (12) /* Bit 12-14: External event select for injected group */ +#define ADC_CR2_JEXTSEL_MASK (0x7 << ADC_CR2_JEXTSEL_SHIFT) +# define ADC_CR2_JEXTSEL_TIM19_CC1 (0 << ADC_CR2_JEXTSEL_SHIFT) +# define ADC_CR2_JEXTSEL_TIM19_CC2 (1 << ADC_CR2_JEXTSEL_SHIFT) +# define ADC_CR2_JEXTSEL_TIM2_TRGO (2 << ADC_CR2_JEXTSEL_SHIFT) +# define ADC_CR2_JEXTSEL_TIM2_CC1 (3 << ADC_CR2_JEXTSEL_SHIFT) +# define ADC_CR2_JEXTSEL_TIM3_CC4 (4 << ADC_CR2_JEXTSEL_SHIFT) +# define ADC_CR2_JEXTSEL_TIM4_TRGO (5 << ADC_CR2_JEXTSEL_SHIFT) +# define ADC_CR2_JEXTSEL_EXTI15 (6 << ADC_CR2_JEXTSEL_SHIFT) +# define ADC_CR2_JEXTSEL_JSWSTART (7 << ADC_CR2_JEXTSEL_SHIFT) +#define ADC_CR2_JEXTTRIG (1 << 15) /* Bit 15: External trigger conversion mode for injected channels */ +#define ADC_CR2_EXTSEL_SHIFT (17) /* Bit 17-19: External event select for regular group */ +#define ADC_CR2_EXTSEL_MASK (0x7 << ADC_CR2_EXTSEL_SHIFT) +# define ADC_CR2_EXTSEL_TIM19_TRGO (0 << ADC_CR2_EXTSEL_SHIFT) +# define ADC_CR2_EXTSEL_TIM19_CC3 (1 << ADC_CR2_EXTSEL_SHIFT) +# define ADC_CR2_EXTSEL_TIM19_CC4 (2 << ADC_CR2_EXTSEL_SHIFT) +# define ADC_CR2_EXTSEL_TIM2_CC2 (3 << ADC_CR2_EXTSEL_SHIFT) +# define ADC_CR2_EXTSEL_TIM3_TRGO (4 << ADC_CR2_EXTSEL_SHIFT) +# define ADC_CR2_EXTSEL_TIM4_CC4 (5 << ADC_CR2_EXTSEL_SHIFT) +# define ADC_CR2_EXTSEL_EXTI11 (6 << ADC_CR2_EXTSEL_SHIFT) +# define ADC_CR2_EXTSEL_SWSTART (7 << ADC_CR2_EXTSEL_SHIFT) +#define ADC_CR2_EXTTRIG (1 << 20) /* Bit 20: External trigger conversion mode for regular channels */ +#define ADC_CR2_JSWSTART (1 << 21) /* Bit 21: Start conversion of injected channels */ +#define ADC_CR2_SWSTART (1 << 22) /* Bit 22: Start conversion of regular channels */ +#define ADC_CR2_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and V REFINT enable */ + +/* ADC sample time register 1 */ + +#define ADC_SMPR_1p5 0 /* 000: 1.5 cycles */ +#define ADC_SMPR_7p5 1 /* 001: 7.5 cycles */ +#define ADC_SMPR_13p5 2 /* 010: 13.5 cycles */ +#define ADC_SMPR_28p5 3 /* 011: 28.5 cycles */ +#define ADC_SMPR_41p5 4 /* 100: 41.5 cycles */ +#define ADC_SMPR_55p5 5 /* 101: 55.5 cycles */ +#define ADC_SMPR_71p5 6 /* 110: 71.5 cycles */ +#define ADC_SMPR_239p5 7 /* 111: 239.5 cycles */ + +#define ADC_SMPR1_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */ +#define ADC_SMPR1_SMP10_MASK (7 << ADC_SMPR1_SMP10_SHIFT) +#define ADC_SMPR1_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */ +#define ADC_SMPR1_SMP11_MASK (7 << ADC_SMPR1_SMP11_SHIFT) +#define ADC_SMPR1_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */ +#define ADC_SMPR1_SMP12_MASK (7 << ADC_SMPR1_SMP12_SHIFT) +#define ADC_SMPR1_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */ +#define ADC_SMPR1_SMP13_MASK (7 << ADC_SMPR1_SMP13_SHIFT) +#define ADC_SMPR1_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */ +#define ADC_SMPR1_SMP14_MASK (7 << ADC_SMPR1_SMP14_SHIFT) +#define ADC_SMPR1_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */ +#define ADC_SMPR1_SMP15_MASK (7 << ADC_SMPR1_SMP15_SHIFT) +#define ADC_SMPR1_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */ +#define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT) +#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */ +#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT) +#define ADC_SMPR1_SMP18_SHIFT (21) /* Bits 24-26: Channel 18 Sample time selection */ +#define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP17_SHIFT) + +/* ADC sample time register 2 */ + +#define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */ +#define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR2_SMP0_SHIFT) +#define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */ +#define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR2_SMP1_SHIFT) +#define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */ +#define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR2_SMP2_SHIFT) +#define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */ +#define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR2_SMP3_SHIFT) +#define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */ +#define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR2_SMP4_SHIFT) +#define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */ +#define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR2_SMP5_SHIFT) +#define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */ +#define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR2_SMP6_SHIFT) +#define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */ +#define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR2_SMP7_SHIFT) +#define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */ +#define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR2_SMP8_SHIFT) +#define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */ +#define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR2_SMP9_SHIFT) + +/* ADC injected channel data offset register 1, 2, 3, and 4 */ + +#define ADC_JOFR_OFFSETX_SHIFT (0) /* Bits 0-11: Data offset for injected channel x */ +#define ADC_JOFR_OFFSETX_MASK (0x0fff << ADC_JOFR_OFFSETX_SHIFT) + +/* ADC watchdog high threshold register */ + +#define ADC_HTR_HT_SHIFT (0) /* Bits 0-11: Analog watchdog high threshold */ +#define ADC_HTR_HT_MASK (0xfff << ADC_HTR_HT_SHIFT) + +/* ADC watchdog low threshold register */ + +#define ADC_LTR_LT_SHIFT (0) /* Bits 0-11: Analog watchdog low threshold */ +#define ADC_LTR_LT_MASK (0xfff << ADC_LTR_LT_SHIFT) + +/* Offset between SQ bits */ + +#define ADC_SQ_OFFSET (5) + +/* ADC regular sequence register 1 */ + +#define ADC_SQR1_SQ13_SHIFT (0) /* Bits 0-4: 13th conversion in regular sequence */ +#define ADC_SQR1_SQ13_MASK (0x1f << ADC_SQR1_SQ13_SHIFT) +#define ADC_SQR1_SQ14_SHIFT (5) /* Bits 5-9: 14th conversion in regular sequence */ +#define ADC_SQR1_SQ14_MASK (0x1f << ADC_SQR1_SQ14_SHIFT) +#define ADC_SQR1_SQ15_SHIFT (10) /* Bits 10-14: 15th conversion in regular sequence */ +#define ADC_SQR1_SQ15_MASK (0x1f << ADC_SQR1_SQ15_SHIFT) +#define ADC_SQR1_SQ16_SHIFT (15) /* Bits 15-19: 16th conversion in regular sequence */ +#define ADC_SQR1_SQ16_MASK (0x1f << ADC_SQR1_SQ16_SHIFT) +#define ADC_SQR1_L_SHIFT (20) /* Bits 20-23: Regular channel sequence length */ +#define ADC_SQR1_L_MASK (0xf << ADC_SQR1_L_SHIFT) +#define ADC_SQR1_RESERVED (0xff000000) +#define ADC_SQR1_FIRST (13) +#define ADC_SQR1_LAST (16) +#define ADC_SQR1_SQ_OFFSET (0) + +/* ADC regular sequence register 2 */ + +#define ADC_SQR2_SQ7_SHIFT (0) /* Bits 0-4: 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT) +#define ADC_SQR2_SQ8_SHIFT (5) /* Bits 5-9: 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT) +#define ADC_SQR2_SQ9_SHIFT (10) /* Bits 10-14: 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT) +#define ADC_SQR2_SQ10_SHIFT (15) /* Bits 15-19: 10th conversion in regular sequence */ +#define ADC_SQR2_SQ10_MASK (0x1f << ADC_SQR2_SQ10_SHIFT) +#define ADC_SQR2_SQ11_SHIFT (15) /* Bits 20-24: 11th conversion in regular sequence */ +#define ADC_SQR2_SQ11_MASK (0x1f << ADC_SQR2_SQ11_SHIFT) +#define ADC_SQR2_SQ12_SHIFT (15) /* Bits 25-29: 12th conversion in regular sequence */ +#define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT) +#define ADC_SQR2_RESERVED (0xc0000000) +#define ADC_SQR2_FIRST (7) +#define ADC_SQR2_LAST (12) +#define ADC_SQR2_SQ_OFFSET (0) + +/* ADC regular sequence register 3 */ + +#define ADC_SQR3_SQ1_SHIFT (0) /* Bits 0-4: 1rst conversion in regular sequence */ +#define ADC_SQR3_SQ1_MASK (0x1f << ADC_SQR3_SQ1_SHIFT) +#define ADC_SQR3_SQ2_SHIFT (5) /* Bits 5-9: 2nd conversion in regular sequence */ +#define ADC_SQR3_SQ2_MASK (0x1f << ADC_SQR3_SQ2_SHIFT) +#define ADC_SQR3_SQ3_SHIFT (10) /* Bits 10-14: 3rd conversion in regular sequence */ +#define ADC_SQR3_SQ3_MASK (0x1f << ADC_SQR3_SQ3_SHIFT) +#define ADC_SQR3_SQ4_SHIFT (15) /* Bits 15-19: 4th conversion in regular sequence */ +#define ADC_SQR3_SQ4_MASK (0x1f << ADC_SQR3_SQ4_SHIFT) +#define ADC_SQR3_SQ5_SHIFT (15) /* Bits 20-24: 5th conversion in regular sequence */ +#define ADC_SQR3_SQ5_MASK (0x1f << ADC_SQR3_SQ5_SHIFT) +#define ADC_SQR3_SQ6_SHIFT (15) /* Bits 25-29: 6th conversion in regular sequence */ +#define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT) +#define ADC_SQR3_RESERVED (0xc0000000) +#define ADC_SQR3_FIRST (1) +#define ADC_SQR3_LAST (6) +#define ADC_SQR3_SQ_OFFSET (0) + +/* ADC injected sequence register */ + +#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 0-4: 1rst conversion in injected sequence */ +#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT) +#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 5-9: 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT) +#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 10-14: 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT) +#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 15-19: 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT) +#define ADC_JSQR_JL_SHIFT (20) /* Bits 20-21: Injected sequence length */ +#define ADC_JSQR_JL_MASK (0x3 << ADC_JSQR_JL_SHIFT) + +/* ADC injected data register 1, 2, 3, and 4 */ + +#define ADC_JDR_JDATA_SHIFT (0) +#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) + +/* ADC regular data register */ + +#define ADC_DR_RDATA_SHIFT (0) +#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) + +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Data + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Function Prototypes + ****************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_ADC_H */ diff --git a/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h b/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h index a9116019bf..4c703be930 100644 --- a/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h +++ b/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h @@ -117,7 +117,7 @@ #define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103FF SYSCFG + COMP + OPAMP */ #define STM32_EXTI_BASE 0x40010400 /* 0x40010400-0x400107FF EXTI */ -#define STM32_ADC1_BASE 0x40012400 /* 0x40012400-0x400127ff ADC1 */ +#define STM32_ADC_BASE 0x40012400 /* 0x40012400-0x400127ff ADC */ #define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */ #define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */ #define STM32_TIM15_BASE 0x40014000 /* 0x40014000-0x400143ff TIM15 */ @@ -128,6 +128,8 @@ #define STM32_SDADC2_BASE 0x40016400 /* 0x40016000-0x400167ff SDADC2 */ #define STM32_SDADC3_BASE 0x40016800 /* 0x40016000-0x40016bff SDADC3 */ +#define STM32_ADC1_BASE STM32_ADC_BASE + /* AHB1 Base Addresses **************************************************************/ #define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */ diff --git a/arch/arm/src/stm32/chip/stm32f37xxx_pinmap.h b/arch/arm/src/stm32/chip/stm32f37xxx_pinmap.h index 6f48b4bf1e..a20ae8577f 100644 --- a/arch/arm/src/stm32/chip/stm32f37xxx_pinmap.h +++ b/arch/arm/src/stm32/chip/stm32f37xxx_pinmap.h @@ -69,6 +69,71 @@ * pins in this file. */ +/* ADC */ + +#define GPIO_ADC_IN1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1) +#define GPIO_ADC_IN2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2) +#define GPIO_ADC_IN3 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3) +#define GPIO_ADC_IN4 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4) +#define GPIO_ADC_IN5 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5) +#define GPIO_ADC_IN6 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6) +#define GPIO_ADC_IN7 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7) +#define GPIO_ADC_IN8 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0) +#define GPIO_ADC_IN9 (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1) +#define GPIO_ADC_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0) +#define GPIO_ADC_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1) +#define GPIO_ADC_IN12 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2) +#define GPIO_ADC_IN13 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3) +#define GPIO_ADC_IN14 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4) +#define GPIO_ADC_IN15 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5) + +/* SDADC */ + +#define GPIO_SDADC1_AIN0P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN12) +#define GPIO_SDADC1_AIN0M (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN13) +#define GPIO_SDADC1_AIN1P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN11) +#define GPIO_SDADC1_AIN2P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN10) +#define GPIO_SDADC1_AIN2M (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN11) +#define GPIO_SDADC1_AIN3P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN7) +#define GPIO_SDADC1_AIN4P (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN2) +#define GPIO_SDADC1_AIN4M (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN7) +#define GPIO_SDADC1_AIN5P (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1) +#define GPIO_SDADC1_AIN6P (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0) +#define GPIO_SDADC1_AIN6M (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1) +#define GPIO_SDADC1_AIN7P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN9) +#define GPIO_SDADC1_AIN8P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN8) +#define GPIO_SDADC1_AIN8M (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN9) + +#define GPIO_SDADC2_AIN0P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN15) +#define GPIO_SDADC2_AIN0M (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN10) +#define GPIO_SDADC2_AIN1P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN14) +#define GPIO_SDADC2_AIN2P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN13) +#define GPIO_SDADC2_AIN2M (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN14) +#define GPIO_SDADC2_AIN3P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN12) +#define GPIO_SDADC2_AIN4P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN11) +#define GPIO_SDADC2_AIN4M (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN12) +#define GPIO_SDADC2_AIN5P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN7) +#define GPIO_SDADC2_AIN6P (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN2) +#define GPIO_SDADC2_AIN6M (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN7) +#define GPIO_SDADC2_AIN7P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN9) +#define GPIO_SDADC2_AIN8P (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN8) +#define GPIO_SDADC2_AIN8M (GPIO_ANALOG|GPIO_PORTE|GPIO_PIN9) + +#define GPIO_SDADC3_AIN0P (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN14) +#define GPIO_SDADC3_AIN0M (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN15) +#define GPIO_SDADC3_AIN1P (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN13) +#define GPIO_SDADC3_AIN2P (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN12) +#define GPIO_SDADC3_AIN2M (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN13) +#define GPIO_SDADC3_AIN3P (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN11) +#define GPIO_SDADC3_AIN4P (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN10) +#define GPIO_SDADC3_AIN4M (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN11) +#define GPIO_SDADC3_AIN5P (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN9) +#define GPIO_SDADC3_AIN6P (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN8) +#define GPIO_SDADC3_AIN6M (GPIO_ANALOG|GPIO_PORTD|GPIO_PIN9) +#define GPIO_SDADC3_AIN7P (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN15) +#define GPIO_SDADC3_AIN8P (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14) +#define GPIO_SDADC3_AIN8M (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN15) + /* CAN */ #define GPIO_CAN_RX_1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) @@ -96,9 +161,9 @@ * should first be configured to analog (AIN)". */ -#define GPIO_DAC1_1_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4) -#define GPIO_DAC1_2_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5) -#define GPIO_DAC2_1_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6) +#define GPIO_DAC1_OUT1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4) +#define GPIO_DAC1_OUT2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5) +#define GPIO_DAC2_OUT1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6) /* I2C */ @@ -233,7 +298,6 @@ #define GPIO_SPI3_SCK_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3) #define GPIO_SPI3_SCK_3 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10) - /* Timers */ #define GPIO_TIM2_CH1_ETR_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN0) @@ -544,6 +608,5 @@ #define GPIO_PF9_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN9) #define GPIO_PF10_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN10) - #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_PINMAP_H */ diff --git a/arch/arm/src/stm32/chip/stm32f37xxx_rcc.h b/arch/arm/src/stm32/chip/stm32f37xxx_rcc.h index 9c48bbd5d5..1e1f6daf6a 100644 --- a/arch/arm/src/stm32/chip/stm32f37xxx_rcc.h +++ b/arch/arm/src/stm32/chip/stm32f37xxx_rcc.h @@ -128,6 +128,12 @@ # define RCC_CFGR_PPRE2_HCLKd4 (5 << RCC_CFGR_PPRE2_SHIFT) /* 101: HCLK divided by 4 */ # define RCC_CFGR_PPRE2_HCLKd8 (6 << RCC_CFGR_PPRE2_SHIFT) /* 110: HCLK divided by 8 */ # define RCC_CFGR_PPRE2_HCLKd16 (7 << RCC_CFGR_PPRE2_SHIFT) /* 111: HCLK divided by 16 */ +#define RCC_CFGR_ADCPRE_SHIFT (13) /* Bits 14-15: ADC prescaler */ +#define RCC_CFGR_ADCPRE_MASK (7 << RCC_CFGR_ADCPRE_SHIFT) +# define RCC_CFGR_ADCPRE_PCLKd2 (0 << RCC_CFGR_ADCPRE_SHIFT) /* 00: PCLK divided by 2 */ +# define RCC_CFGR_ADCPRE_PCLKd4 (1 << RCC_CFGR_ADCPRE_SHIFT) /* 01: PCLK divided by 4 */ +# define RCC_CFGR_ADCPRE_PCLKd6 (2 << RCC_CFGR_ADCPRE_SHIFT) /* 10: PCLK divided by 6 */ +# define RCC_CFGR_ADCPRE_PCLKd8 (3 << RCC_CFGR_ADCPRE_SHIFT) /* 11: PCLK divided by 8 */ #define RCC_CFGR_PLLSRC (1 << 16) /* Bit 16: PLL entry clock source */ #define RCC_CFGR_PLLXTPRE (1 << 17) /* Bit 17: HSE divider for PLL entry */ #define RCC_CFGR_PLLMUL_SHIFT (18) /* Bits 21-18: PLL Multiplication Factor */ @@ -157,24 +163,24 @@ # define RCC_CFGR_MCO_HSICLK (5 << RCC_CFGR_MCO_SHIFT) /* 101: HSI clock selected */ # define RCC_CFGR_MCO_HSECLK (6 << RCC_CFGR_MCO_SHIFT) /* 101: HSE clock selected */ # define RCC_CFGR_PLLCLKd2 (7 << RCC_CFGR_MCO_SHIFT) /* 111: PLL clock divided by 2 selected */ -#define RCC_CFGR_SDADCPRE_SHIFT (24) /* Bits 27-31: SDADC Prescaler */ -#define RCC_CFGR_SDADCPRE_MASK (31 << RCC_CFGR_SDADCPRE_SHIFT) -# define RCC_CFGR_SDADCPRE_DIV2 (0 << RCC_CFGR_SDADCPRE_SHIFT) /* 0xxxx: System clock divided by 2 */ -# define RCC_CFGR_SDADCPRE_DIV4 (17 << RCC_CFGR_SDADCPRE_SHIFT) /* 10001: System clock divided by 4 */ -# define RCC_CFGR_SDADCPRE_DIV6 (18 << RCC_CFGR_SDADCPRE_SHIFT) /* 10010: System clock divided by 6 */ -# define RCC_CFGR_SDADCPRE_DIV8 (19 << RCC_CFGR_SDADCPRE_SHIFT) /* 10011: System clock divided by 8 */ -# define RCC_CFGR_SDADCPRE_DIV10 (20 << RCC_CFGR_SDADCPRE_SHIFT) /* 10100: System clock divided by 10 */ -# define RCC_CFGR_SDADCPRE_DIV12 (21 << RCC_CFGR_SDADCPRE_SHIFT) /* 10101: System clock divided by 12 */ -# define RCC_CFGR_SDADCPRE_DIV14 (22 << RCC_CFGR_SDADCPRE_SHIFT) /* 10110: System clock divided by 14 */ -# define RCC_CFGR_SDADCPRE_DIV16 (23 << RCC_CFGR_SDADCPRE_SHIFT) /* 10111: System clock divided by 16 */ -# define RCC_CFGR_SDADCPRE_DIV20 (24 << RCC_CFGR_SDADCPRE_SHIFT) /* 11000: System clock divided by 20 */ -# define RCC_CFGR_SDADCPRE_DIV24 (25 << RCC_CFGR_SDADCPRE_SHIFT) /* 11001: System clock divided by 24 */ -# define RCC_CFGR_SDADCPRE_DIV28 (26 << RCC_CFGR_SDADCPRE_SHIFT) /* 11010: System clock divided by 28 */ -# define RCC_CFGR_SDADCPRE_DIV32 (27 << RCC_CFGR_SDADCPRE_SHIFT) /* 11011: System clock divided by 32 */ -# define RCC_CFGR_SDADCPRE_DIV36 (28 << RCC_CFGR_SDADCPRE_SHIFT) /* 11100: System clock divided by 36 */ -# define RCC_CFGR_SDADCPRE_DIV40 (29 << RCC_CFGR_SDADCPRE_SHIFT) /* 11101: System clock divided by 40 */ -# define RCC_CFGR_SDADCPRE_DIV44 (30 << RCC_CFGR_SDADCPRE_SHIFT) /* 11110: System clock divided by 44 */ -# define RCC_CFGR_SDADCPRE_DIV48 (31 << RCC_CFGR_SDADCPRE_SHIFT) /* 11111: System clock divided by 48 */ +#define RCC_CFGR_SDPRE_SHIFT (27) /* Bits 27-31: SDADC Prescaler */ +#define RCC_CFGR_SDPRE_MASK (0x1f << RCC_CFGR_SDPRE_SHIFT) +# define RCC_CFGR_SDPRE_DIV2 (0 << RCC_CFGR_SDPRE_SHIFT) /* 0xxxx: System clock divided by 2 */ +# define RCC_CFGR_SDPRE_DIV4 (17 << RCC_CFGR_SDPRE_SHIFT) /* 10001: System clock divided by 4 */ +# define RCC_CFGR_SDPRE_DIV6 (18 << RCC_CFGR_SDPRE_SHIFT) /* 10010: System clock divided by 6 */ +# define RCC_CFGR_SDPRE_DIV8 (19 << RCC_CFGR_SDPRE_SHIFT) /* 10011: System clock divided by 8 */ +# define RCC_CFGR_SDPRE_DIV10 (20 << RCC_CFGR_SDPRE_SHIFT) /* 10100: System clock divided by 10 */ +# define RCC_CFGR_SDPRE_DIV12 (21 << RCC_CFGR_SDPRE_SHIFT) /* 10101: System clock divided by 12 */ +# define RCC_CFGR_SDPRE_DIV14 (22 << RCC_CFGR_SDPRE_SHIFT) /* 10110: System clock divided by 14 */ +# define RCC_CFGR_SDPRE_DIV16 (23 << RCC_CFGR_SDPRE_SHIFT) /* 10111: System clock divided by 16 */ +# define RCC_CFGR_SDPRE_DIV20 (24 << RCC_CFGR_SDPRE_SHIFT) /* 11000: System clock divided by 20 */ +# define RCC_CFGR_SDPRE_DIV24 (25 << RCC_CFGR_SDPRE_SHIFT) /* 11001: System clock divided by 24 */ +# define RCC_CFGR_SDPRE_DIV28 (26 << RCC_CFGR_SDPRE_SHIFT) /* 11010: System clock divided by 28 */ +# define RCC_CFGR_SDPRE_DIV32 (27 << RCC_CFGR_SDPRE_SHIFT) /* 11011: System clock divided by 32 */ +# define RCC_CFGR_SDPRE_DIV36 (28 << RCC_CFGR_SDPRE_SHIFT) /* 11100: System clock divided by 36 */ +# define RCC_CFGR_SDPRE_DIV40 (29 << RCC_CFGR_SDPRE_SHIFT) /* 11101: System clock divided by 40 */ +# define RCC_CFGR_SDPRE_DIV44 (30 << RCC_CFGR_SDPRE_SHIFT) /* 11110: System clock divided by 44 */ +# define RCC_CFGR_SDPRE_DIV48 (31 << RCC_CFGR_SDPRE_SHIFT) /* 11111: System clock divided by 48 */ /* Clock interrupt register */ @@ -199,7 +205,7 @@ /* APB2 Peripheral reset register */ #define RCC_APB2RSTR_SYSCFGRST (1 << 0) /* Bit 0: SYSCFG, Comparators and operational amplifiers reset */ -#define RCC_APB2RSTR_ADC1RST (1 << 9) /* Bit 9: ADC1 reset */ +#define RCC_APB2RSTR_ADCRST (1 << 9) /* Bit 9: ADC reset */ #define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI 1 reset */ #define RCC_APB2RSTR_USART1RST (1 << 14) /* Bit 14: USART1 reset */ #define RCC_APB2RSTR_TIM15RST (1 << 16) /* Bit 16: TIM15 reset */ @@ -232,7 +238,7 @@ #define RCC_APB1RSTR_USBRST (1 << 23) /* Bit 23: USB reset */ #define RCC_APB1RSTR_CANRST (1 << 25) /* Bit 25: CAN reset */ #define RCC_APB1RSTR_CAN1RST (1 << 25) /* Bit 25: CAN reset */ -#define RCC_APB1RSTR_DAC2RST (1 << 26) /* Bit 26: DAC1 interface reset */ +#define RCC_APB1RSTR_DAC2RST (1 << 26) /* Bit 26: DAC2 interface reset */ #define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: Power interface reset */ #define RCC_APB1RSTR_DAC1RST (1 << 29) /* Bit 29: DAC1 interface reset */ #define RCC_APB1RSTR_CECRST (1 << 30) /* Bit 30: CEC reset */ diff --git a/arch/arm/src/stm32/chip/stm32f37xxx_sdadc.h b/arch/arm/src/stm32/chip/stm32f37xxx_sdadc.h new file mode 100644 index 0000000000..011ab4d58f --- /dev/null +++ b/arch/arm/src/stm32/chip/stm32f37xxx_sdadc.h @@ -0,0 +1,304 @@ +/**************************************************************************************************** + * arch/arm/src/stm32/chip/stm32f37xxx_sdadc.h + * + * Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Studelec SA. All rights reserved. + * Authors: Gregory Nutt + * Marc Rechté + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_SDADC_H +#define __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_SDADC_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +#define STM32_SDADC_CR1_OFFSET 0x0000 /* SDADC control register 1 */ +#define STM32_SDADC_CR2_OFFSET 0x0004 /* SDADC control register 2 */ +#define STM32_SDADC_ISR_OFFSET 0x0008 /* SDADC interrupt and status register */ +#define STM32_SDADC_CLRISR_OFFSET 0x000c /* SDADC interrupt and status clear register */ +#define STM32_SDADC_JCHGR_OFFSET 0x0014 /* SDADC injected channel group selection register */ +#define STM32_SDADC_CONF0R_OFFSET 0x0020 /* SDADC configuration 0 register */ +#define STM32_SDADC_CONF1R_OFFSET 0x0024 /* SDADC configuration 1 register */ +#define STM32_SDADC_CONF2R_OFFSET 0x0028 /* SDADC configuration 2 register */ +#define STM32_SDADC_CONFCHR1_OFFSET 0x0040 /* SDADC channel configuration register 1 */ +#define STM32_SDADC_CONFCHR2_OFFSET 0x0044 /* SDADC channel configuration register 2 */ +#define STM32_SDADC_JDATAR_OFFSET 0x0060 /* SDADC data register for injected group */ +#define STM32_SDADC_RDATAR_OFFSET 0x0064 /* SDADC data register for the regular channel */ +#define STM32_SDADC_JDATA12R_OFFSET 0x0070 /* SDADC1 and SDADC2 injected data register */ +#define STM32_SDADC_RDATA12R_OFFSET 0x0074 /* SDADC1 and SDADC2 regular data register */ +#define STM32_SDADC_JDATA13R_OFFSET 0x0078 /* SDADC1 and SDADC3 injected data register */ +#define STM32_SDADC_RDATA13R_OFFSET 0x007c /* SDADC1 and SDADC3 regular data register */ + + +/* Register Addresses *******************************************************************************/ + +#define STM32_SDADC1_CR1 (STM32_SDADC1_BASE+STM32_SDADC_CR1_OFFSET) +#define STM32_SDADC1_CR2 (STM32_SDADC1_BASE+STM32_SDADC_CR2_OFFSET) +#define STM32_SDADC1_ISR (STM32_SDADC1_BASE+STM32_SDADC_ISR_OFFSET) +#define STM32_SDADC1_CLRISR (STM32_SDADC1_BASE+STM32_SDADC_CLRISR_OFFSET) +#define STM32_SDADC1_JCHGR (STM32_SDADC1_BASE+STM32_SDADC_JCHGR_OFFSET) +#define STM32_SDADC1_CONF0R (STM32_SDADC1_BASE+STM32_SDADC_CONF0R_OFFSET) +#define STM32_SDADC1_CONF1R (STM32_SDADC1_BASE+STM32_SDADC_CONF1R_OFFSET) +#define STM32_SDADC1_CONF2R (STM32_SDADC1_BASE+STM32_SDADC_CONF2R_OFFSET) +#define STM32_SDADC1_CONFCHR1 (STM32_SDADC1_BASE+STM32_SDADC_CONFCHR1_OFFSET) +#define STM32_SDADC1_CONFCHR2 (STM32_SDADC1_BASE+STM32_SDADC_CONFCHR2_OFFSET) +#define STM32_SDADC1_JDATAR (STM32_SDADC1_BASE+STM32_SDADC_JDATAR_OFFSET) +#define STM32_SDADC1_RDATAR (STM32_SDADC1_BASE+STM32_SDADC_RDATAR_OFFSET) +#define STM32_SDADC1_JDATA12R (STM32_SDADC1_BASE+STM32_SDADC_JDATA12R_OFFSET) +#define STM32_SDADC1_RDATA12R (STM32_SDADC1_BASE+STM32_SDADC_RDATA12R_OFFSET) +#define STM32_SDADC1_JDATA13R (STM32_SDADC1_BASE+STM32_SDADC_JDATA13R_OFFSET) +#define STM32_SDADC1_RDATA13R (STM32_SDADC1_BASE+STM32_SDADC_RDATA13R_OFFSET) + +#define STM32_SDADC2_CR1 (STM32_SDADC2_BASE+STM32_SDADC_CR1_OFFSET) +#define STM32_SDADC2_CR2 (STM32_SDADC2_BASE+STM32_SDADC_CR2_OFFSET) +#define STM32_SDADC2_ISR (STM32_SDADC2_BASE+STM32_SDADC_ISR_OFFSET) +#define STM32_SDADC2_CLRISR (STM32_SDADC2_BASE+STM32_SDADC_CLRISR_OFFSET) +#define STM32_SDADC2_JCHGR (STM32_SDADC2_BASE+STM32_SDADC_JCHGR_OFFSET) +#define STM32_SDADC2_CONF0R (STM32_SDADC2_BASE+STM32_SDADC_CONF0R_OFFSET) +#define STM32_SDADC2_CONF1R (STM32_SDADC2_BASE+STM32_SDADC_CONF1R_OFFSET) +#define STM32_SDADC2_CONF2R (STM32_SDADC2_BASE+STM32_SDADC_CONF2R_OFFSET) +#define STM32_SDADC2_CONFCHR1 (STM32_SDADC2_BASE+STM32_SDADC_CONFCHR1_OFFSET) +#define STM32_SDADC2_CONFCHR2 (STM32_SDADC2_BASE+STM32_SDADC_CONFCHR2_OFFSET) +#define STM32_SDADC2_JDATAR (STM32_SDADC2_BASE+STM32_SDADC_JDATAR_OFFSET) +#define STM32_SDADC2_RDATAR (STM32_SDADC2_BASE+STM32_SDADC_RDATAR_OFFSET) + +#define STM32_SDADC3_CR1 (STM32_SDADC3_BASE+STM32_SDADC_CR1_OFFSET) +#define STM32_SDADC3_CR2 (STM32_SDADC3_BASE+STM32_SDADC_CR2_OFFSET) +#define STM32_SDADC3_ISR (STM32_SDADC3_BASE+STM32_SDADC_ISR_OFFSET) +#define STM32_SDADC3_CLRISR (STM32_SDADC3_BASE+STM32_SDADC_CLRISR_OFFSET) +#define STM32_SDADC3_JCHGR (STM32_SDADC3_BASE+STM32_SDADC_JCHGR_OFFSET) +#define STM32_SDADC3_CONF0R (STM32_SDADC3_BASE+STM32_SDADC_CONF0R_OFFSET) +#define STM32_SDADC3_CONF1R (STM32_SDADC3_BASE+STM32_SDADC_CONF1R_OFFSET) +#define STM32_SDADC3_CONF2R (STM32_SDADC3_BASE+STM32_SDADC_CONF2R_OFFSET) +#define STM32_SDADC3_CONFCHR1 (STM32_SDADC3_BASE+STM32_SDADC_CONFCHR1_OFFSET) +#define STM32_SDADC3_CONFCHR2 (STM32_SDADC3_BASE+STM32_SDADC_CONFCHR2_OFFSET) +#define STM32_SDADC3_JDATAR (STM32_SDADC3_BASE+STM32_SDADC_JDATAR_OFFSET) +#define STM32_SDADC3_RDATAR (STM32_SDADC3_BASE+STM32_SDADC_RDATAR_OFFSET) + + +/* Register Bitfield Definitions ********************************************************************/ +/* SDADC control register 1 */ + +#define SDADC_CR1_EOCALIE (1 << 0) /* Bit 0: End of calibration interrupt enable */ +#define SDADC_CR1_JEOCIE (1 << 1) /* Bit 1: Injected end of conversion interrupt enable */ +#define SDADC_CR1_JOVRIE (1 << 2) /* Bit 2: Injected data overrun interrupt enable */ +#define SDADC_CR1_REOCIE (1 << 3) /* Bit 3: Regular end of conversion interrupt enable */ +#define SDADC_CR1_ROVRIE (1 << 4) /* Bit 4: Regular data overrun interrupt enable */ +#define SDADC_CR1_REFV_SHIFT (8) /* Bits 8-9: Reference voltage selection */ +#define SDADC_CR1_REFV_MASK (0x3 << SDADC_CR1_REFV_SHIFT) +# define SDADC_CR1_REFV_EXT (0 << SDADC_CR1_REFV_SHIFT) +# define SDADC_CR1_REFV_INT1p2 (1 << SDADC_CR1_REFV_SHIFT) +# define SDADC_CR1_REFV_INT1p8 (2 << SDADC_CR1_REFV_SHIFT) +# define SDADC_CR1_REFV_INT (3 << SDADC_CR1_REFV_SHIFT) +#define SDADC_CR1_SLOWCK (1 << 10) /* Bit 10: Slow clock mode enable */ +#define SDADC_CR1_SBI (1 << 11) /* Bit 11: Enter Standby mode when idle */ +#define SDADC_CR1_PDI (1 << 12) /* Bit 12: Enter power down mode when idle */ +#define SDADC_CR1_JSYNC (1 << 14) /* Bit 14: Launch a injected conversion synchronously with SDADC1 */ +#define SDADC_CR1_RSYNC (1 << 15) /* Bit 15: Launch regular conversion synchronously with SDADC1 */ +#define SDADC_CR1_JDMAEN (1 << 16) /* Bit 16: DMA channel enabled to read data for the injected channel group */ +#define SDADC_CR1_RDMAEN (1 << 17) /* Bit 17: DMA channel enabled to read data for the regular channel */ +#define SDADC_CR1_INIT (1 << 31) /* Bit 31: Initialization mode request */ + +/* SDADC control register 2 */ + +#define SDADC_CR2_ADON (1 << 0) /* Bit 0: SDADC enable */ +#define SDADC_CR2_CALIBCNT_SHIFT (1) /* Bit 1-2: Number of calibration sequences to be performed (number of valid configurations) */ +#define SDADC_CR2_CALIBCNT_MASK (0x3 << SDADC_CR2_CALIBCNT_SHIFT) +#define SDADC_CR2_STARTCALIB (1 << 4) /* Bit 4: Start calibration */ +#define SDADC_CR2_JCONT (1 << 5) /* Bit 5: Continuous mode selection for injected conversions */ +#define SDADC_CR2_JDS (1 << 6) /* Bit 6: Delay start of injected conversions */ +#define SDADC_CR2_JEXTSEL_SHIFT (8) /* Bit 8-10: Trigger signal selection for launching injected conversions */ +#define SDADC_CR2_JEXTSEL_MASK (0x7 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC1_CR2_JEXTSEL_TIM13_CH1 (0 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC1_CR2_JEXTSEL_TIM14_CH1 (1 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC1_CR2_JEXTSEL_TIM15_CH2 (2 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC1_CR2_JEXTSEL_TIM3_CH1 (3 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC1_CR2_JEXTSEL_TIM4_CH1 (4 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC1_CR2_JEXTSEL_TIM19_CH2 (5 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC1_CR2_JEXTSEL_EXTI15 (6 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC1_CR2_JEXTSEL_EXTI11 (7 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC2_CR2_JEXTSEL_TIM17_CH1 (0 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC2_CR2_JEXTSEL_TIM12_CH1 (1 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC2_CR2_JEXTSEL_TIM2_CH3 (2 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC2_CR2_JEXTSEL_TIM3_CH2 (3 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC2_CR2_JEXTSEL_TIM4_CH2 (4 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC2_CR2_JEXTSEL_TIM19_CH3 (5 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC2_CR2_JEXTSEL_EXTI15 (6 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC2_CR2_JEXTSEL_EXTI11 (7 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC3_CR2_JEXTSEL_TIM16_CH1 (0 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC3_CR2_JEXTSEL_TIM12_CH1 (1 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC3_CR2_JEXTSEL_TIM2_CH4 (2 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC3_CR2_JEXTSEL_TIM3_CH3 (3 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC3_CR2_JEXTSEL_TIM4_CH3 (4 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC3_CR2_JEXTSEL_TIM19_CH4 (5 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC3_CR2_JEXTSEL_EXTI15 (6 << SDADC_CR2_JEXTSEL_SHIFT) +# define SDADC3_CR2_JEXTSEL_EXTI11 (7 << SDADC_CR2_JEXTSEL_SHIFT) +#define SDADC_CR2_JEXTEN_SHIFT (13) /* Bit 13-14: Trigger enable and trigger edge selection for injected conversions */ +#define SDADC_CR2_JEXTEN_MASK (0x3 << SDADC_CR2_JEXTEN_SHIFT) +# define SDADC_CR2_JEXTEN_NONE (0 << SDADC_CR2_JEXTEN_SHIFT) +# define SDADC_CR2_JEXTEN_RISING (1 << SDADC_CR2_JEXTEN_SHIFT) +# define SDADC_CR2_JEXTEN_FALLING (2 << SDADC_CR2_JEXTEN_SHIFT) +# define SDADC_CR2_JEXTEN_BOTH (3 << SDADC_CR2_JEXTEN_SHIFT) +#define SDADC_CR2_JSWSTART (1 << 15) /* Bit 15: Start a conversion of the injected group of channels */ +#define SDADC_CR2_RCH_SHIFT (16) /* Bit 16-19: Regular channel selection */ +#define SDADC_CR2_RCH_MASK (0xf << SDADC_CR2_RCH_SHIFT) +#define SDADC_CR2_RCONT (1 << 22) /* Bit 22: Continuous mode selection for regular conversions */ +#define SDADC_CR2_RSWSTART (1 << 23) /* Bit 23: Software start of a conversion on the regular channel */ +#define SDADC_CR2_FAST (1 << 24) /* Bit 24: Fast conversion mode selection */ + +/* SDADC interrupt and status register */ + +#define SDADC_ISR_EOCALF (1 << 0) /* Bit 0: End of calibration flag */ +#define SDADC_ISR_JEOCF (1 << 1) /* Bit 1: End of injected conversion flag */ +#define SDADC_ISR_JOVRF (1 << 2) /* Bit 2: Injected conversion overrun flag */ +#define SDADC_ISR_REOCF (1 << 3) /* Bit 3: End of regular conversion flag */ +#define SDADC_ISR_ROVRF (1 << 4) /* Bit 4: Regular conversion overrun flag */ +#define SDADC_ISR_CALIBIP (1 << 12) /* Bit 12: Calibration in progress status */ +#define SDADC_ISR_JCIP (1 << 13) /* Bit 13: Injected conversion in progress status */ +#define SDADC_ISR_RCIP (1 << 14) /* Bit 14: Regular conversion in progress status */ +#define SDADC_ISR_STABIP (1 << 15) /* Bit 15: Stabilization in progress status */ +#define SDADC_ISR_INITRDY (1 << 31) /* Bit 31: Initialization mode is ready */ + +/* SDADC interrupt and status clear register */ + +#define SDADC_CLRISR_CLREOCALF (1 << 0) /* Bit 0: Clear the end of calibration flag */ +#define SDADC_CLRISR_CLRJOVRF (1 << 2) /* Bit 2: Clear the injected conversion overrun flag */ +#define SDADC_CLRISR_CLRROVRF (1 << 4) /* Bit 4: Clear the regular conversion overrun flag */ + +/* SDADC injected channel group selection register */ + +#define SDADC_JCHGR_JCHG_SHIFT (0) /* Bit 0-8: Injected channel group selection */ +#define SDADC_JCHGR_JCHG_MASK (0x1ff << SDADC_JCHGR_JCHG_SHIFT) +#define SDADC_JCHGR_JCHG_CH(n) (1 << (n + SDADC_JCHGR_JCHG_SHIFT)) + +/* SDADC configuration 0-2 register */ + +#define SDADC_CONF0R 0 +#define SDADC_CONF1R 1 +#define SDADC_CONF2R 2 + +#define SDADC_CONFR_OFFSET_SHIFT (0) /* Bit 0-11: Twelve-bit calibration offset for configuration 0-2 */ +#define SDADC_CONFR_OFFSET_MASK (0xfff << SDADC_CONFR_OFFSET_SHIFT) +#define SDADC_CONFR_GAIN_SHIFT (20) /* Bit 20-22: Gain setting for configuration 0-2 */ +#define SDADC_CONFR_GAIN_MASK (0x7 << SDADC_CONFR_GAIN_SHIFT) +# define SDADC_CONFR_GAIN_1X (0 << SDADC_CONFR_GAIN_SHIFT) +# define SDADC_CONFR_GAIN_2X (1 << SDADC_CONFR_GAIN_SHIFT) +# define SDADC_CONFR_GAIN_4X (2 << SDADC_CONFR_GAIN_SHIFT) +# define SDADC_CONFR_GAIN_8X (3 << SDADC_CONFR_GAIN_SHIFT) +# define SDADC_CONFR_GAIN_16X (4 << SDADC_CONFR_GAIN_SHIFT) +# define SDADC_CONFR_GAIN_32X (5 << SDADC_CONFR_GAIN_SHIFT) +# define SDADC_CONFR_GAIN_0p5X (7 << SDADC_CONFR_GAIN_SHIFT) +#define SDADC_CONFR_SE_SHIFT (26) /* Bit 27-26: Single-ended mode for configuration 0-2 */ +#define SDADC_CONFR_SE_MASK (0x3 << SDADC_CONFR_SE_SHIFT) +# define SDADC_CONFR_SE_DIF (0 << SDADC_CONFR_SE_SHIFT) +# define SDADC_CONFR_SE_SE_OFFSET (1 << SDADC_CONFR_SE_SHIFT) +# define SDADC_CONFR_SE_SE_ZERO (3 << SDADC_CONFR_SE_SHIFT) +#define SDADC_CONFR_COMMON_SHIFT (30) /* Bit 30-31: Common mode for configuration 0-2 */ +#define SDADC_CONFR_COMMON_MASK (0x3 << SDADC_CONFR_COMMON_SHIFT) +# define SDADC_CONFR_COMMON_GND (0 << SDADC_CONFR_COMMON_SHIFT) +# define SDADC_CONFR_COMMON_VCM (1 << SDADC_CONFR_COMMON_SHIFT) +# define SDADC_CONFR_COMMON_VDD (2 << SDADC_CONFR_COMMON_SHIFT) + +/* SDADC channel configuration register 1 */ + +#define SDADC_CONFCHR1_CH_SHIFT(i) (2*i) /* Bit 0-1: Channel i configuration 0-7 */ +#define SDADC_CONFCHR1_CH_MASK(i) (0x3 << SDADC_CONFCHR1_CH_SHIFT(i)) + +/* SDADC channel configuration register 2 */ + +#define SDADC_CONFCHR2_CH8_SHIFT (0) /* Bit 0-1: Channel 8 configuration */ +#define SDADC_CONFCHR2_CH8_MASK (0x3 << SDADC_CONFCHR2_CH8_SHIFT) + +/* SDADC data register for injected group */ + +#define SDADC_JDATAR_JDATA_SHIFT (0) /* Bit 0-15: Injected group conversion data */ +#define SDADC_JDATAR_JDATA_MASK (0xffff << SDADC_JDATAR_JDATA_SHIFT) +#define SDADC_JDATAR_JDATACH_SHIFT (24) /* Bit 24-27: Injected channel most recently converted */ +#define SDADC_JDATAR_JDATACH_MASK (0xf << SDADC_JDATAR_JDATACH_SHIFT) + +/* SDADC data register for the regular channel */ + +#define SDADC_RDATAR_RDATA_SHIFT (0) /* Bit 0-15: Regular channel conversion data */ +#define SDADC_RDATAR_RDATA_MASK (0xffff << SDADC_RDATAR_RDATA_SHIFT) + +/* SDADC1 and SDADC2 injected data register */ + +#define SDADC_JDATA12R_JDATA1_SHIFT (0) /* Bit 0-15: Injected group conversion data for SDADC1 */ +#define SDADC_JDATA12R_JDATA1_MASK (0xffff << SDADC_JDATA12R_JDATA1_SHIFT) +#define SDADC_JDATA12R_JDATA2_SHIFT (16) /* Bit 16-31: Injected group conversion data for SDADC2 */ +#define SDADC_JDATA12R_JDATA2_MASK (0xffff << SDADC_JDATA12R_JDATA2_SHIFT) + +/* SDADC1 and SDADC2 regular data register */ + +#define SDADC_RDATA12R_RDATA1_SHIFT (0) /* Bit 0-15: Regular conversion data for SDADC1 */ +#define SDADC_RDATA12R_RDATA1_MASK (0xffff << SDADC_RDATA12R_RDATA1_SHIFT) +#define SDADC_RDATA12R_RDATA2_SHIFT (16) /* Bit 16-31: Regular conversion data for SDADC2 */ +#define SDADC_RDATA12R_RDATA2_MASK (0xffff << SDADC_RDATA12R_RDATA2_SHIFT) + +/* SDADC1 and SDADC3 injected data register */ + +#define SDADC_JDATA13R_JDATA1_SHIFT (0) /* Bit 0-15: Injected group conversion data for SDADC1 */ +#define SDADC_JDATA13R_JDATA1_MASK (0xffff << SDADC_JDATA13R_JDATA1_SHIFT) +#define SDADC_JDATA13R_JDATA3_SHIFT (16) /* Bit 16-31: Injected group conversion data for SDADC3 */ +#define SDADC_JDATA13R_JDATA3_MASK (0xffff << SDADC_JDATA13R_JDATA3_SHIFT) + +/* SDADC1 and SDADC3 regular data register */ + +#define SDADC_RDATA13R_RDATA1_SHIFT (0) /* Bit 0-15: Regular conversion data for SDADC1 */ +#define SDADC_RDATA13R_RDATA1_MASK (0xffff << SDADC_RDATA13R_RDATA1_SHIFT) +#define SDADC_RDATA13R_RDATA3_SHIFT (16) /* Bit 16-31: Regular conversion data for SDADC3 */ +#define SDADC_RDATA13R_RDATA3_MASK (0xffff << SDADC_RDATA13R_RDATA3_SHIFT) + +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Data + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Function Prototypes + ****************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_SDADC_H */ diff --git a/arch/arm/src/stm32/stm32.h b/arch/arm/src/stm32/stm32.h index af91ea4ea6..f2304e2735 100644 --- a/arch/arm/src/stm32/stm32.h +++ b/arch/arm/src/stm32/stm32.h @@ -61,6 +61,7 @@ #include "stm32_can.h" #include "stm32_dbgmcu.h" #include "stm32_dma.h" +#include "stm32_dac.h" #include "stm32_exti.h" #include "stm32_flash.h" #include "stm32_fsmc.h" diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c index 2972ebaf9a..acbb707d34 100644 --- a/arch/arm/src/stm32/stm32_adc.c +++ b/arch/arm/src/stm32/stm32_adc.c @@ -79,8 +79,8 @@ /* This implementation is for the STM32 F1, F2, F4 and STM32L15XX only */ #if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F40XX) || \ - defined(CONFIG_STM32_STM32L15XX) + defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX) /* At the moment there is no proper implementation for timers external * trigger in STM32L15XX May be added latter @@ -107,6 +107,9 @@ # define RCC_RSTR_ADC2RST RCC_AHBRSTR_ADC12RST # define RCC_RSTR_ADC3RST RCC_AHBRSTR_ADC34RST # define RCC_RSTR_ADC4RST RCC_AHBRSTR_ADC34RST +#elif defined(CONFIG_STM32_STM32F37XX) +# define STM32_RCC_RSTR STM32_RCC_APB2RSTR +# define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADCRST #elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) # define STM32_RCC_RSTR STM32_RCC_APB2RSTR # define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADCRST @@ -148,7 +151,7 @@ # define ADC_IER_AWD ADC_CR1_AWDIE # define ADC_ISR_JEOC ADC_SR_JEOC # define ADC_IER_JEOC ADC_CR1_JEOCIE -# ifdef CONFIG_STM32_STM32F10XX +# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F37XX) # define ADC_EXTREG_EXTEN_MASK ADC_CR2_EXTTRIG # define ADC_EXTREG_EXTEN_NONE 0 # define ADC_EXTREG_EXTEN_DEFAULT ADC_CR2_EXTTRIG @@ -180,7 +183,11 @@ #ifdef ADC_HAVE_DMA # define ADC_MAX_SAMPLES ADC_MAX_CHANNELS_DMA #else -# define ADC_MAX_SAMPLES ADC_MAX_CHANNELS_NODMA +# if defined(CONFIG_STM32_STM32F30XX) +# define ADC_MAX_SAMPLES ADC_MAX_CHANNELS_DMA /* Works without DMA should sampling frequency be reduced */ +# else +# define ADC_MAX_SAMPLES ADC_MAX_CHANNELS_NODMA +# endif #endif #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) @@ -219,7 +226,12 @@ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT)) #elif defined(CONFIG_STM32_STM32F30XX) -# define ADC_SMPR_DEFAULT ADC_SMPR_61p5 +# ifdef ADC_HAVE_DMA || (ADC_MAX_SAMPLES == 1) +# define ADC_SMPR_DEFAULT ADC_SMPR_61p5 +# else /* Slow down sampling frequency */ +# define ADC_SMPR_DEFAULT ADC_SMPR_601p5 +# endif + # define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP1_SHIFT) | \ (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP2_SHIFT) | \ (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP3_SHIFT) | \ @@ -238,8 +250,13 @@ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP16_SHIFT) | \ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP17_SHIFT) | \ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP18_SHIFT)) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) -# define ADC_SMPR_DEFAULT ADC_SMPR_112 +#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32F40XX) +# if defined(CONFIG_STM32_STM32F37XX) +# define ADC_SMPR_DEFAULT ADC_SMPR_239p5 /* TODO choose 1p5? */ +# else +# define ADC_SMPR_DEFAULT ADC_SMPR_112 +# endif # define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP10_SHIFT) | \ (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP11_SHIFT) | \ (ADC_SMPR_DEFAULT << ADC_SMPR1_SMP12_SHIFT) | \ @@ -320,7 +337,8 @@ struct stm32_dev_s /* ADC Register access */ #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX) + defined(CONFIG_STM32_STM32F37XX) ||defined(CONFIG_STM32_STM32F40XX) || \ + defined(CONFIG_STM32_STM32L15XX) static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, uint32_t setbits); #endif @@ -587,7 +605,8 @@ static struct adc_dev_s g_adcdev4 = ****************************************************************************/ #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX) + defined(CONFIG_STM32_STM32F37XX) ||defined(CONFIG_STM32_STM32F40XX) || \ + defined(CONFIG_STM32_STM32L15XX) static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits, uint32_t setbits) { @@ -1626,7 +1645,7 @@ static void adc_write_sample_time_registers(FAR struct adc_dev_s *dev) #endif /**************************************************************************** - * Name: adc_dmacovcallback + * Name: adc_dmaconvcallback * * Description: * Callback for DMA. Called from the DMA transfer complete interrupt after @@ -1850,7 +1869,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) adc_modifyreg(priv, STM32_ADC_IER_OFFSET, clrbits, setbits); -#else +#else /* ifdef CONFIG_STM32_STM32F30XX */ /* Enable the analog watchdog */ @@ -1864,7 +1883,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) clrbits |= ADC_CR1_DUALMOD_MASK; setbits |= ADC_CR1_IND; -#else +#elif (! defined(CONFIG_STM32_STM32F37XX)) /* Set the resolution of the conversion */ @@ -1880,10 +1899,16 @@ static void adc_reset(FAR struct adc_dev_s *dev) } #endif - /* Enable interrupt flags, but disable overrun interrupt */ + /* Enable interrupt flags, but disable overrun interrupt: TODO this is + * done later by upper half when opening device by adc_rxint(). + */ +#ifndef CONFIG_STM32_STM32F37XX clrbits |= ADC_IER_OVR; setbits |= ADC_IER_ALLINTS & ~ADC_IER_OVR; +#else + /* TODO NON DMA mode */ +#endif /* Set CR1 configuration */ @@ -1916,6 +1941,13 @@ static void adc_reset(FAR struct adc_dev_s *dev) clrbits |= ADC_EXTREG_EXTEN_MASK; setbits |= ADC_EXTREG_EXTEN_NONE; + /* Enable software trigger for regular channels */ + +#ifdef CONFIG_STM32_STM32F37XX + clrbits |= ADC_CR2_EXTSEL_MASK; + setbits |= ADC_CR2_EXTSEL_SWSTART | ADC_CR2_EXTTRIG; /* SW is considered as external trigger */ +#endif + #ifdef ADC_HAVE_DMA if (priv->hasdma) { @@ -2176,9 +2208,12 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable) if (enable) { - /* Enable the end-of-conversion ADC and analog watchdog interrupts */ + /* Enable the analog watchdog / overrun interrupts, and if no DMA, + * end-of-conversion ADC. + */ - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_ALLINTS); + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, + priv->hasdma ? ADC_IER_AWD | ADC_ISR_OVR : ADC_IER_ALLINTS); } else { @@ -2766,8 +2801,10 @@ static int adc_interrupt(FAR struct adc_dev_s *dev) } } - regval &= ~pending; - adc_putreg(priv, STM32_ADC_ISR_OFFSET, regval); + /* by MR regval &= ~pending; */ + /* by MR adc_putreg(priv, STM32_ADC_ISR_OFFSET, regval); + + adc_putreg(priv, STM32_ADC_ISR_OFFSET, pending); */ return OK; } @@ -3039,8 +3076,8 @@ struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist, } #endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || - * CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F40XX || - * CONFIG_STM32_STM32L15XX + * CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F47XX || + * CONFIG_STM32_STM32F40XX || CONFIG_STM32_STM32L15XX */ #endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || * CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4 diff --git a/arch/arm/src/stm32/stm32_adc.h b/arch/arm/src/stm32/stm32_adc.h index 25ad161b62..b2f4ee3918 100644 --- a/arch/arm/src/stm32/stm32_adc.h +++ b/arch/arm/src/stm32/stm32_adc.h @@ -48,6 +48,8 @@ #if defined(CONFIG_STM32_STM32F30XX) # include "chip/stm32f30xxx_adc.h" +#elif defined(CONFIG_STM32_STM32F37XX) +# include "chip/stm32f37xxx_adc.h" #else # include "chip/stm32_adc.h" #endif diff --git a/arch/arm/src/stm32/stm32_dac.c b/arch/arm/src/stm32/stm32_dac.c index 528faf1786..fdcbaf050a 100644 --- a/arch/arm/src/stm32/stm32_dac.c +++ b/arch/arm/src/stm32/stm32_dac.c @@ -348,7 +348,9 @@ struct stm32_chan_s uint8_t timer; /* Timer number 2-8 */ #endif uint8_t intf; /* DAC zero-based interface number (0 or 1) */ + uint32_t pin; /* Pin configuration */ uint32_t dro; /* Data output register */ + uint32_t cr; /* Control register */ uint32_t tsel; /* CR trigger select value */ #ifdef HAVE_DMA uint16_t dmachan; /* DMA channel needed by this DAC */ @@ -408,10 +410,20 @@ static const struct dac_ops_s g_dacops = }; #ifdef CONFIG_STM32_DAC1 +/* Channel 1 */ + static struct stm32_chan_s g_dac1priv = { .intf = 0, +#if STM32_NDAC < 2 + .pin = GPIO_DAC1_OUT, .dro = STM32_DAC_DHR12R1, + .cr = STM32_DAC_CR, +#else + .pin = GPIO_DAC1_OUT1, + .dro = STM32_DAC1_DHR12R1, + .cr = STM32_DAC1_CR, +#endif #ifdef CONFIG_STM32_DAC1_DMA .hasdma = 1, .dmachan = DAC1_DMA_CHAN, @@ -427,13 +439,21 @@ static struct dac_dev_s g_dac1dev = .ad_ops = &g_dacops, .ad_priv = &g_dac1priv, }; -#endif -#ifdef CONFIG_STM32_DAC2 +/* Channel 2 */ + static struct stm32_chan_s g_dac2priv = { .intf = 1, +#if STM32_NDAC < 2 + .pin = GPIO_DAC2_OUT, .dro = STM32_DAC_DHR12R2, + .cr = STM32_DAC_CR, +#else + .pin = GPIO_DAC1_OUT2, + .dro = STM32_DAC1_DHR12R2, + .cr = STM32_DAC1_CR, +#endif #ifdef CONFIG_STM32_DAC2_DMA .hasdma = 1, .dmachan = DAC2_DMA_CHAN, @@ -451,6 +471,24 @@ static struct dac_dev_s g_dac2dev = }; #endif +#ifdef CONFIG_STM32_DAC2 +/* Channel 1 */ + +static struct stm32_chan_s g_dac3priv = +{ + .intf = 2, + .pin = GPIO_DAC2_OUT1, + .dro = STM32_DAC2_DHR12R1, + .cr = STM32_DAC2_CR, +}; + +static struct dac_dev_s g_dac3dev = +{ + .ad_ops = &g_dacops, + .ad_priv = &g_dac3priv, +}; +#endif + static struct stm32_dac_s g_dacblock; /**************************************************************************** @@ -479,7 +517,7 @@ static inline void stm32_dac_modify_cr(FAR struct stm32_chan_s *chan, uint32_t shift; shift = chan->intf * 16; - modifyreg32(STM32_DAC_CR, clearbits << shift, setbits << shift); + modifyreg32(chan->cr, clearbits << shift, setbits << shift); } /**************************************************************************** @@ -738,16 +776,7 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg) /* Non-DMA transfer */ putreg16(msg->am_data, chan->dro); -#ifdef CONFIG_STM32_DAC2 - if (chan->intf) - { - dac_txdone(&g_dac2dev); - } - else -#endif - { - dac_txdone(&g_dac1dev); - } + dac_txdone(dev); } /* Reset counters (generate an update) */ @@ -978,7 +1007,7 @@ static int dac_chaninit(FAR struct stm32_chan_s *chan) * should first be configured to analog (AIN)". */ - stm32_configgpio(chan->intf ? GPIO_DAC2_OUT : GPIO_DAC1_OUT); + stm32_configgpio(chan->pin); /* DAC channel configuration: * @@ -1041,7 +1070,7 @@ static int dac_chaninit(FAR struct stm32_chan_s *chan) * Name: dac_blockinit * * Description: - * All ioctl calls will be routed through this method. + * Initialize the DAC block. * * Input Parameters: * @@ -1055,7 +1084,7 @@ static int dac_blockinit(void) irqstate_t flags; uint32_t regval; - /* Has the DMA block already been initialized? */ + /* Has the DAC block already been initialized? */ if (g_dacblock.init) { @@ -1068,12 +1097,30 @@ static int dac_blockinit(void) flags = enter_critical_section(); regval = getreg32(STM32_RCC_APB1RSTR); +#if STM32_NDAC < 2 regval |= RCC_APB1RSTR_DACRST; +#else +#ifdef CONFIG_STM32_DAC1 + regval |= RCC_APB1RSTR_DAC1RST; +#endif +#ifdef CONFIG_STM32_DAC2 + regval |= RCC_APB1RSTR_DAC2RST; +#endif +#endif putreg32(regval, STM32_RCC_APB1RSTR); /* Take the DAC out of reset state */ +#if STM32_NDAC < 2 regval &= ~RCC_APB1RSTR_DACRST; +#else +#ifdef CONFIG_STM32_DAC1 + regval &= ~RCC_APB1RSTR_DAC1RST; +#endif +#ifdef CONFIG_STM32_DAC2 + regval &= ~RCC_APB1RSTR_DAC2RST; +#endif +#endif putreg32(regval, STM32_RCC_APB1RSTR); leave_critical_section(flags); @@ -1114,18 +1161,24 @@ FAR struct dac_dev_s *stm32_dacinitialize(int intf) #ifdef CONFIG_STM32_DAC1 if (intf == 1) { - ainfo("DAC1 Selected\n"); + ainfo("DAC1-1 Selected\n"); dev = &g_dac1dev; } else -#endif -#ifdef CONFIG_STM32_DAC2 if (intf == 2) { - ainfo("DAC2 Selected\n"); + ainfo("DAC1-2 Selected\n"); dev = &g_dac2dev; } else +#endif +#ifdef CONFIG_STM32_DAC2 + if (intf == 3) + { + ainfo("DAC2-1 Selected\n"); + dev = &g_dac3dev; + } + else #endif { aerr("ERROR: No such DAC interface: %d\n", intf); diff --git a/arch/arm/src/stm32/stm32_i2c.h b/arch/arm/src/stm32/stm32_i2c.h index 05f57ee46f..7274325f54 100644 --- a/arch/arm/src/stm32/stm32_i2c.h +++ b/arch/arm/src/stm32/stm32_i2c.h @@ -44,7 +44,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32_STM32F30XX) +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) # include "chip/stm32f30xxx_i2c.h" #else # include "chip/stm32_i2c.h" diff --git a/arch/arm/src/stm32/stm32_pwr.c b/arch/arm/src/stm32/stm32_pwr.c index 5eda6c08cc..13fbdb3470 100644 --- a/arch/arm/src/stm32/stm32_pwr.c +++ b/arch/arm/src/stm32/stm32_pwr.c @@ -76,6 +76,46 @@ static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint1 * Public Functions ************************************************************************************/ +/************************************************************************************ + * Name: stm32_pwr_enablesdadc + * + * Description: + * Enables SDADC power + * + * Input Parameters: + * sdadc - SDADC number 1-3 + * + * Returned Value: + * None + * + ************************************************************************************/ + +#if defined(CONFIG_STM32_STM32F37XX) +void stm32_pwr_enablesdadc(uint8_t sdadc) +{ + uint32_t setbits = 0; + + switch (sdadc) + { + case 1: + setbits = PWR_CR_ENSD1; + break; + + case 2: + setbits = PWR_CR_ENSD2; + break; + + case 3: + setbits = PWR_CR_ENSD3; + break; + } + + stm32_pwr_modifyreg(STM32_PWR_CR_OFFSET, 0, setbits); + +} +#endif + + /************************************************************************************ * Name: stm32_pwr_enablebkp * diff --git a/arch/arm/src/stm32/stm32_pwr.h b/arch/arm/src/stm32/stm32_pwr.h index 344834c067..700dd60294 100644 --- a/arch/arm/src/stm32/stm32_pwr.h +++ b/arch/arm/src/stm32/stm32_pwr.h @@ -66,6 +66,24 @@ extern "C" * Public Functions ************************************************************************************/ +/************************************************************************************ + * Name: stm32_pwr_enablesdadc + * + * Description: + * Enables SDADC power + * + * Input Parameters: + * sdadc - SDADC number 1-3 + * + * Returned Value: + * None + * + ************************************************************************************/ + +#if defined(CONFIG_STM32_STM32F37XX) +void stm32_pwr_enablesdadc(uint8_t sdadc); +#endif + /************************************************************************************ * Name: stm32_pwr_enablebkp * diff --git a/arch/arm/src/stm32/stm32_sdadc.c b/arch/arm/src/stm32/stm32_sdadc.c new file mode 100644 index 0000000000..a16cade9cd --- /dev/null +++ b/arch/arm/src/stm32/stm32_sdadc.c @@ -0,0 +1,1456 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32_sdadc.c + * + * Copyright (C) 2011, 2013, 2015-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Studelec. All rights reserved. + * Authors: Gregory Nutt + * Marc Rechté + * + * derived from arch/arm/src/stm32/stm32_adc.c + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" +#include "stm32.h" +#include "stm32_dma.h" +#include "stm32_pwr.h" +#include "stm32_sdadc.h" + +#ifdef CONFIG_STM32_SDADC + +/* Some SDADC peripheral must be enabled */ + +#if defined(CONFIG_STM32_SDADC1) || defined(CONFIG_STM32_SDADC2) || \ + defined(CONFIG_STM32_SDADC3) + +/* This implementation is for the STM32F37XX only */ + +#ifndef CONFIG_STM32_STM32F37XX +# error "This chip is not yet supported" +#endif + +/* TODO: At the moment there is no implementation + for timer and external triggers */ + +#if defined(SDADC_HAVE_TIMER) +# error "There is no proper implementation for TIMER TRIGGERS at the moment" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* RCC reset ****************************************************************/ + +#define STM32_RCC_RSTR STM32_RCC_APB2RSTR +#define RCC_RSTR_SDADC1RST RCC_APB2RSTR_SDADC1RST +#define RCC_RSTR_SDADC2RST RCC_APB2RSTR_SDADC2RST +#define RCC_RSTR_SDADC3RST RCC_APB2RSTR_SDADC3RST + +/* SDADC interrupts *********************************************************/ + +#define SDADC_ISR_ALLINTS (SDADC_ISR_JEOCF | SDADC_ISR_JOVRF) + +/* SDADC Channels/DMA *******************************************************/ + + +#define SDADC_DMA_CONTROL_WORD (DMA_CCR_MSIZE_16BITS | \ + DMA_CCR_PSIZE_16BITS | \ + DMA_CCR_MINC | \ + DMA_CCR_CIRC) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure describes the state of one SDADC block */ + +struct stm32_dev_s +{ + FAR const struct adc_callback_s *cb; + uint8_t irq; /* Interrupt generated by this SDADC block */ + uint8_t nchannels; /* Number of channels */ + uint8_t cchannels; /* Number of configured channels */ + uint8_t intf; /* SDADC interface number */ + uint8_t current; /* Current SDADC channel being converted */ + uint8_t refv; /* Reference voltage selection */ +#ifdef SDADC_HAVE_DMA + uint8_t dmachan; /* DMA channel needed by this SDADC */ + bool hasdma; /* True: This channel supports DMA */ +#endif +#ifdef SDADC_HAVE_TIMER + uint8_t trigger; /* Timer trigger selection: see SDADCx_JEXTSEL_TIMxx */ +#endif + xcpt_t isr; /* Interrupt handler for this SDADC block */ + uint32_t base; /* Base address of registers unique to this SDADC + * block */ +#ifdef SDADC_HAVE_TIMER + uint32_t tbase; /* Base address of timer used by this SDADC block */ + uint32_t jextsel /* JEXTSEL value used by this SDADC block */ + uint32_t pclck; /* The PCLK frequency that drives this timer */ + uint32_t freq; /* The desired frequency of conversions */ +#endif +#ifdef SDADC_HAVE_DMA + DMA_HANDLE dma; /* Allocated DMA channel */ + + /* DMA transfer buffer */ + + int16_t dmabuffer[SDADC_MAX_SAMPLES]; +#endif + + /* List of selected SDADC injected channels to sample */ + + uint8_t chanlist[SDADC_MAX_SAMPLES]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* ADC Register access */ + +static uint32_t sdadc_getreg(FAR struct stm32_dev_s *priv, int offset); +static void sdadc_putreg(FAR struct stm32_dev_s *priv, int offset, + uint32_t value); +static void sdadc_modifyreg(FAR struct stm32_dev_s *priv, int offset, + uint32_t clrbits, uint32_t setbits); +#ifdef ADC_HAVE_TIMER +static uint16_t tim_getreg(FAR struct stm32_dev_s *priv, int offset); +static void tim_putreg(FAR struct stm32_dev_s *priv, int offset, + uint16_t value); +static void tim_modifyreg(FAR struct stm32_dev_s *priv, int offset, + uint16_t clrbits, uint16_t setbits); +static void tim_dumpregs(FAR struct stm32_dev_s *priv, + FAR const char *msg); +#endif + +static void sdadc_rccreset(FAR struct stm32_dev_s *priv, bool reset); + +/* ADC Interrupt Handler */ + +static int sdadc_interrupt(FAR struct adc_dev_s *dev); +#if defined(CONFIG_STM32_SDADC1) +static int sdadc1_interrupt(int irq, FAR void *context); +#endif +#if defined(CONFIG_STM32_SDADC2) +static int sdadc2_interrupt(int irq, FAR void *context); +#endif +#if defined(CONFIG_STM32_SDADC3) +static int sdadc3_interrupt(int irq, FAR void *context); +#endif + +/* ADC Driver Methods */ + +static int sdadc_bind(FAR struct adc_dev_s *dev, + FAR const struct adc_callback_s *callback); +static void sdadc_reset(FAR struct adc_dev_s *dev); +static int sdadc_setup(FAR struct adc_dev_s *dev); +static void sdadc_shutdown(FAR struct adc_dev_s *dev); +static void sdadc_rxint(FAR struct adc_dev_s *dev, bool enable); +static int sdadc_ioctl(FAR struct adc_dev_s *dev, int cmd, + unsigned long arg); +static void sdadc_enable(FAR struct stm32_dev_s *priv, bool enable); + +static int sdadc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch); + +#ifdef ADC_HAVE_TIMER +static void sdadc_timstart(FAR struct stm32_dev_s *priv, bool enable); +static int sdadc_timinit(FAR struct stm32_dev_s *priv); +#endif + +#ifdef ADC_HAVE_DMA +static void sdadc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, + FAR void *arg); +#endif + +static void sdadc_startconv(FAR struct stm32_dev_s *priv, bool enable); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* SDADC interface operations */ + +static const struct adc_ops_s g_sdadcops = +{ + .ao_bind = sdadc_bind, + .ao_reset = sdadc_reset, + .ao_setup = sdadc_setup, + .ao_shutdown = sdadc_shutdown, + .ao_rxint = sdadc_rxint, + .ao_ioctl = sdadc_ioctl, +}; + +/* SDADC1 state */ + +#ifdef CONFIG_STM32_SDADC1 +static struct stm32_dev_s g_sdadcpriv1 = +{ + .irq = STM32_IRQ_SDADC1, + .isr = sdadc1_interrupt, + .intf = 1, + .base = STM32_SDADC1_BASE, + .refv = SDADC1_REFV, +#ifdef SDADC1_HAVE_TIMER + .trigger = CONFIG_STM32_SDADC1_TIMTRIG, + .tbase = SDADC1_TIMER_BASE, + .extsel = SDADC1_EXTSEL_VALUE, + .pclck = SDADC1_TIMER_PCLK_FREQUENCY, + .freq = CONFIG_STM32_SDADC1_SAMPLE_FREQUENCY, +#endif +#ifdef SDADC1_HAVE_DMA + .dmachan = DMACHAN_SDADC1, + .hasdma = true, +#endif +}; + +static struct adc_dev_s g_sdadcdev1 = +{ + .ad_ops = &g_sdadcops, + .ad_priv = &g_sdadcpriv1, +}; +#endif + +/* SDADC2 state */ + +#ifdef CONFIG_STM32_SDADC2 +static struct stm32_dev_s g_sdadcpriv2 = +{ + .irq = STM32_IRQ_SDADC2, + .isr = sdadc2_interrupt, + .intf = 2, + .base = STM32_SDADC2_BASE, + .refv = SDADC2_REFV, +#ifdef SDADC2_HAVE_TIMER + .trigger = CONFIG_STM32_SDADC2_TIMTRIG, + .tbase = SDADC2_TIMER_BASE, + .extsel = SDADC2_EXTSEL_VALUE, + .pclck = SDADC2_TIMER_PCLK_FREQUENCY, + .freq = CONFIG_STM32_SDADC2_SAMPLE_FREQUENCY, +#endif +#ifdef SDADC2_HAVE_DMA + .dmachan = DMACHAN_SDADC2, + .hasdma = true, +#endif +}; + +static struct adc_dev_s g_sdadcdev2 = +{ + .ad_ops = &g_sdadcops, + .ad_priv = &g_sdadcpriv2, +}; +#endif + +/* SDADC3 state */ + +#ifdef CONFIG_STM32_SDADC3 +static struct stm32_dev_s g_sdadcpriv3 = +{ + .irq = STM32_IRQ_SDADC3, + .isr = sdadc3_interrupt, + .intf = 3, + .base = STM32_SDADC3_BASE, + .refv = SDADC3_REFV, +#ifdef SDADC3_HAVE_TIMER + .trigger = CONFIG_STM32_SDADC3_TIMTRIG, + .tbase = SDADC3_TIMER_BASE, + .extsel = SDADC3_EXTSEL_VALUE, + .pclck = SDADC3_TIMER_PCLK_FREQUENCY, + .freq = CONFIG_STM32_SDADC3_SAMPLE_FREQUENCY, +#endif +#ifdef SDADC3_HAVE_DMA + .dmachan = DMACHAN_SDADC3, + .hasdma = true, +#endif +}; + +static struct adc_dev_s g_sdadcdev3 = +{ + .ad_ops = &g_sdadcops, + .ad_priv = &g_sdadcpriv3, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sdadc_getreg + * + * Description: + * Read the value of an SDADC register. + * + * Input Parameters: + * priv - A reference to the SDADC block state + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static uint32_t sdadc_getreg(FAR struct stm32_dev_s *priv, int offset) +{ + return getreg32(priv->base + offset); +} + +/**************************************************************************** + * Name: sdadc_putreg + * + * Description: + * Write a value to an SDADC register. + * + * Input Parameters: + * priv - A reference to the SDADC block state + * offset - The offset to the register to write to + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void sdadc_putreg(FAR struct stm32_dev_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->base + offset); +} + +/**************************************************************************** + * Name: sdadc_modifyreg + * + * Description: + * Modify the value of an SDADC register (not atomic). + * + * Input Parameters: + * priv - A reference to the SDADC block state + * offset - The offset to the register to modify + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void sdadc_modifyreg(FAR struct stm32_dev_s *priv, int offset, + uint32_t clrbits, uint32_t setbits) +{ + sdadc_putreg(priv, offset, (sdadc_getreg(priv, offset) & ~clrbits) | setbits); +} + +/**************************************************************************** + * Name: tim_getreg + * + * Description: + * Read the value of an SDADC timer register. + * + * Input Parameters: + * priv - A reference to the SDADC block state + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +#ifdef SDADC_HAVE_TIMER +static uint16_t tim_getreg(FAR struct stm32_dev_s *priv, int offset) +{ + return getreg16(priv->tbase + offset); +} +#endif + +/**************************************************************************** + * Name: tim_putreg + * + * Description: + * Write a value to an SDADC timer register. + * + * Input Parameters: + * priv - A reference to the SDADC block state + * offset - The offset to the register to write to + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef SDADC_HAVE_TIMER +static void tim_putreg(FAR struct stm32_dev_s *priv, int offset, + uint16_t value) +{ + putreg16(value, priv->tbase + offset); +} +#endif + +/**************************************************************************** + * Name: tim_modifyreg + * + * Description: + * Modify the value of an SDADC timer register (not atomic). + * + * Input Parameters: + * priv - A reference to the SDADC block state + * offset - The offset to the register to modify + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef SDADC_HAVE_TIMER +static void tim_modifyreg(FAR struct stm32_dev_s *priv, int offset, + uint16_t clrbits, uint16_t setbits) +{ + tim_putreg(priv, offset, (tim_getreg(priv, offset) & ~clrbits) | setbits); +} +#endif + +/**************************************************************************** + * Name: tim_dumpregs + * + * Description: + * Dump all timer registers. + * + * Input parameters: + * priv - A reference to the SDADC block state + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef SDADC_HAVE_TIMER +static void tim_dumpregs(FAR struct stm32_dev_s *priv, FAR const char *msg) +{ + ainfo("%s:\n", msg); + + /* TODO */ +} +#endif + +/**************************************************************************** + * Name: sdadc_timstart + * + * Description: + * Start (or stop) the timer counter + * + * Input Parameters: + * priv - A reference to the SDADC block state + * enable - True: Start conversion + * + * Returned Value: + * + ****************************************************************************/ + +#ifdef SDADC_HAVE_TIMER +static void sdadc_timstart(FAR struct stm32_dev_s *priv, bool enable) +{ + ainfo("enable: %d\n", enable ? 1 : 0); + + if (enable) + { + /* Start the counter */ + + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + } + else + { + /* Disable the counter */ + + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + } +} +#endif + +/**************************************************************************** + * Name: sdadc_timinit + * + * Description: + * Initialize the timer that drivers the SDADC sampling for this channel + * using the pre-calculated timer divider definitions. + * + * Input Parameters: + * priv - A reference to the SDADC block state + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef SDADC_HAVE_TIMER +static int sdadc_timinit(FAR struct stm32_dev_s *priv) +{ + /* TODO */ + + aerr("ERROR: not implemented"); + return ERROR; +} +#endif + +/**************************************************************************** + * Name: sdadc_startconv + * + * Description: + * Start (or stop) the SDADC conversion process + * + * Input Parameters: + * priv - A reference to the SDADC block state + * enable - True: Start conversion + * + * Returned Value: + * + ****************************************************************************/ + +static void sdadc_startconv(FAR struct stm32_dev_s *priv, bool enable) +{ + ainfo("enable: %d\n", enable ? 1 : 0); + + if (enable) + { + /* Start the conversion of injected channels */ + + sdadc_modifyreg(priv, STM32_SDADC_CR2_OFFSET, 0, SDADC_CR2_JSWSTART); + } + else + { + /* Wait for a possible conversion to stop */ + + while ((sdadc_getreg(priv, STM32_SDADC_ISR_OFFSET) & SDADC_ISR_JCIP) != 0); + } +} + +/**************************************************************************** + * Name: sdadc_rccreset + * + * Description: + * (De)Initializes the SDADC block registers to their default + * reset values. + * + * Input Parameters: + * priv - A reference to the SDADC block state + * reset - true: to put in reset state, false: to revert to normal state + * + * Returned Value: + * + ****************************************************************************/ + +static void sdadc_rccreset(FAR struct stm32_dev_s *priv, bool reset) +{ + uint32_t adcbit; + + /* Pick the appropriate bit in the APB2 reset register. + */ + + switch (priv->intf) + { +#ifdef CONFIG_STM32_SDADC1 + case 1: + adcbit = RCC_RSTR_SDADC1RST; + break; +#endif +#ifdef CONFIG_STM32_SDADC2 + case 2: + adcbit = RCC_RSTR_SDADC2RST; + break; +#endif +#ifdef CONFIG_STM32_SDADC3 + case 3: + adcbit = RCC_RSTR_SDADC3RST; + break; +#endif + default: + return; + } + + /* Set or clear the selected bit in the APB2 reset register. + * modifyreg32() disables interrupts. Disabling interrupts is necessary + * because the APB2RSTR register is used by several different drivers. + */ + + if (reset) + { + /* Enable SDADC reset state */ + + modifyreg32(STM32_RCC_RSTR, 0, adcbit); + } + else + { + /* Release SDADC from reset state */ + + modifyreg32(STM32_RCC_RSTR, adcbit, 0); + } +} + +/**************************************************************************** + * Name: sdadc_power_down_idle + * + * Description : Enables or disables power down during the idle phase. + * + * Input Parameters: + * priv - A reference to the SDADC block state + * pdi_high - true: The SDADC is powered down when waiting for a start event + * false: The SDADC is powered up when waiting for a start event + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#if 0 +static void sdadc_power_down_idle(FAR struct stm32_dev_s *priv, bool pdi_high) +{ + uint32_t regval; + + ainfo("PDI: %d\n", pdi_high ? 1 : 0); + + regval = sdadc_getreg(priv, STM32_SDADC_CR2_OFFSET); + + if ((regval & SDADC_CR2_ADON) == 0) + { + regval = sdadc_getreg(priv, STM32_SDADC_CR1_OFFSET); + if (pdi_high) + { + regval |= SDADC_CR1_PDI; + } + else + { + regval &= ~SDADC_CR1_PDI; + } + + sdadc_putreg(priv, STM32_SDADC_CR1_OFFSET, regval); + } +} +#endif + +/**************************************************************************** + * Name: sdadc_enable + * + * Description : Enables or disables the specified SDADC peripheral. + * Does not start conversion unless the SDADC is + * triggered by timer + * + * Input Parameters: + * priv - A reference to the SDADC block state + * enable - true: enable SDADC conversion + * false: disable SDADC conversion + * + * Returned Value: + * + ****************************************************************************/ + +static void sdadc_enable(FAR struct stm32_dev_s *priv, bool enable) +{ + uint32_t regval; + + ainfo("enable: %d\n", enable ? 1 : 0); + + regval = sdadc_getreg(priv, STM32_SDADC_CR2_OFFSET); + + if (enable) + { + /* Enable the SDADC */ + + sdadc_putreg(priv, STM32_SDADC_CR2_OFFSET, regval | SDADC_CR2_ADON); + + /* Wait for the SDADC to be stabilized */ + + while (sdadc_getreg(priv, STM32_SDADC_ISR_OFFSET) & SDADC_ISR_STABIP); + } + else if ((regval & SDADC_CR2_ADON) != 0) + { + /* Ongoing conversions will be stopped implicitly */ + + /* Disable the SDADC */ + + sdadc_putreg(priv, STM32_SDADC_CR2_OFFSET, regval & ~SDADC_CR2_ADON); + + } +} + +/**************************************************************************** + * Name: sdadc_dmaconvcallback + * + * Description: + * Callback for DMA. Called from the DMA transfer complete interrupt after + * all channels have been converted and transferred with DMA. + * + * Input Parameters: + * handle - handle to DMA + * isr - + * arg - SDADC device + * + * Returned Value: + * + ****************************************************************************/ + +#ifdef SDADC_HAVE_DMA +static void sdadc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg) +{ + FAR struct adc_dev_s *dev = (FAR struct adc_dev_s *)arg; + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; + int i; + + /* Verify that the upper-half driver has bound its callback functions */ + + if (priv->cb != NULL) + { + DEBUGASSERT(priv->cb->au_receive != NULL); + + for (i = 0; i < priv->nchannels; i++) + { + priv->cb->au_receive(dev, priv->chanlist[priv->current], + priv->dmabuffer[priv->current]); + priv->current++; + if (priv->current >= priv->nchannels) + { + /* Restart the conversion sequence from the beginning */ + + priv->current = 0; + } + } + } +} +#endif + +/**************************************************************************** + * Name: sdadc_bind + * + * Description: + * Bind the upper-half driver callbacks to the lower-half implementation. + * This must be called early in order to receive SDADC event notifications. + * + ****************************************************************************/ + +static int sdadc_bind(FAR struct adc_dev_s *dev, + FAR const struct adc_callback_s *callback) +{ + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; + + DEBUGASSERT(priv != NULL); + priv->cb = callback; + return OK; +} + +/**************************************************************************** + * Name: sdadc_reset + * + * Description: + * Reset the SDADC device. + * This is firstly called whenever the SDADC device is registered by + * sdadc_register() + * Does mostly the SDAC register setting. + * Leave the device in power down mode. + * Note that SDACx clock is already enable (for all SDADC) by the + * rcc_enableapb2() + * + * Input Parameters: + * dev - pointer to the sdadc device structure + * + * Returned Value: + * + ****************************************************************************/ + +static void sdadc_reset(FAR struct adc_dev_s *dev) +{ + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; + irqstate_t flags; + uint32_t setbits = 0; + + ainfo("intf: %d\n", priv->intf); + + /* TODO: why critical ? */ + + flags = enter_critical_section(); + + /* Enable SDADC reset state */ + + sdadc_rccreset(priv, true); + + /* Enable power */ + + stm32_pwr_enablesdadc(priv->intf); + + /* Release SDADC from reset state */ + + sdadc_rccreset(priv, false); + + /* Enable the SDADC (and wait it stabilizes) */ + + sdadc_enable(priv, true); + + /* Put SDADC in in initialization mode */ + + sdadc_putreg(priv, STM32_SDADC_CR1_OFFSET, SDADC_CR1_INIT); + + /* Wait for the SDADC to be ready */ + + while ((sdadc_getreg(priv, STM32_SDADC_ISR_OFFSET) & SDADC_ISR_INITRDY) == 0); + + /* Load configurations */ + + sdadc_putreg(priv, STM32_SDADC_CONF0R_OFFSET, SDADC_CONF0R_DEFAULT); + sdadc_putreg(priv, STM32_SDADC_CONF1R_OFFSET, SDADC_CONF1R_DEFAULT); + sdadc_putreg(priv, STM32_SDADC_CONF2R_OFFSET, SDADC_CONF2R_DEFAULT); + + sdadc_putreg(priv, STM32_SDADC_CONFCHR1_OFFSET, SDADC_CONFCHR1_DEFAULT); + sdadc_putreg(priv, STM32_SDADC_CONFCHR2_OFFSET, SDADC_CONFCHR2_DEFAULT); + + /* Configuration of the injected channels group */ + + sdadc_set_ch(dev, 0); + + /* CR1 ********************************************************************/ + + /* Enable interrupt / dma flags, is done later by upper half when opening + * device by calling sdadc_rxint() + */ + + setbits = SDADC_CR1_INIT; /* remains in init mode while configuring */ + + /* Reference voltage */ + + setbits |= priv->refv; + + /* Set CR1 configuration */ + + sdadc_putreg(priv, STM32_SDADC_CR1_OFFSET, setbits); + + /* CR2 ********************************************************************/ + + setbits = SDADC_CR2_ADON; // leave it ON ! + + /* TODO: JEXTEN / JEXTSEL */ + + /* Number of calibrations is for 3 configurations */ + + setbits |= (2 << SDADC_CR2_CALIBCNT_SHIFT); + + /* Set CR2 configuration */ + + sdadc_putreg(priv, STM32_SDADC_CR2_OFFSET, setbits); + + /* Release INIT mode ******************************************************/ + + sdadc_modifyreg(priv, STM32_SDADC_CR1_OFFSET, SDADC_CR1_INIT, 0); + + /* Calibrate the SDADC */ + + sdadc_modifyreg(priv, STM32_SDADC_CR2_OFFSET, 0, SDADC_CR2_STARTCALIB); + + /* Wait for the calibration to complete (may take up to 5ms) */ + + while ((sdadc_getreg(priv, STM32_SDADC_ISR_OFFSET) & SDADC_ISR_EOCALF) == 0); + + /* Clear this flag */ + + sdadc_modifyreg(priv, STM32_SDADC_CLRISR_OFFSET, SDADC_CLRISR_CLREOCALF, 0); + +#ifdef SDADC_HAVE_TIMER + if (priv->tbase != 0) + { + ret = sdadc_timinit(priv); + if (ret < 0) + { + aerr("ERROR: sdadc_timinit failed: %d\n", ret); + } + } +#endif + + /* Put the device in low power mode until it is actually used by + * application code. + */ + + sdadc_enable(priv, false); + + leave_critical_section(flags); + + ainfo("CR1: 0x%08x CR2: 0x%08x\n", + sdadc_getreg(priv, STM32_SDADC_CR1_OFFSET), + sdadc_getreg(priv, STM32_SDADC_CR2_OFFSET)); + + ainfo("CONF0R: 0x%08x CONF1R: 0x%08x CONF3R: 0x%08x\n", + sdadc_getreg(priv, STM32_SDADC_CONF0R_OFFSET), + sdadc_getreg(priv, STM32_SDADC_CONF1R_OFFSET), + sdadc_getreg(priv, STM32_SDADC_CONF2R_OFFSET)); + + ainfo("CONFCHR1: 0x%08x CONFCHR2: 0x%08x JCHGR: 0x%08x\n", + sdadc_getreg(priv, STM32_SDADC_CONFCHR1_OFFSET), + sdadc_getreg(priv, STM32_SDADC_CONFCHR2_OFFSET), + sdadc_getreg(priv, STM32_SDADC_JCHGR_OFFSET)); +} + +/**************************************************************************** + * Name: sdadc_setup + * + * Description: + * Configure the ADC. This method is called the first time that the SDADC + * device is opened. + * This is called by the upper half driver sdadc_open(). + * This will occur when the port is first + * opened in the application code (/dev/sdadcN). + * It would be called again after closing all references to this file and + * reopening it. + * This function wakes up the device and setup the DMA / IRQ + * + * Input Parameters: + * dev - pointer to the sdadc device structure + * + * Returned Value: + * + ****************************************************************************/ + +static int sdadc_setup(FAR struct adc_dev_s *dev) +{ + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; + int ret; + + /* Wakes up the device */ + + sdadc_enable(priv, true); + + /* Setup DMA or interrupt control. Note that either DMA or interrupt is + * setup not both. + */ + +#ifdef SDADC_HAVE_DMA + if (priv->hasdma) + { + /* Setup DMA */ + /* Stop and free DMA if it was started before */ + + if (priv->dma != NULL) + { + stm32_dmastop(priv->dma); + stm32_dmafree(priv->dma); + } + + priv->dma = stm32_dmachannel(priv->dmachan); + + stm32_dmasetup(priv->dma, + priv->base + STM32_SDADC_JDATAR_OFFSET, + (uint32_t)priv->dmabuffer, + priv->nchannels, + SDADC_DMA_CONTROL_WORD); + + stm32_dmastart(priv->dma, sdadc_dmaconvcallback, dev, false); + } + else + { + /* Attach the SDADC interrupt */ + + ret = irq_attach(priv->irq, priv->isr); + if (ret < 0) + { + ainfo("irq_attach failed: %d\n", ret); + return ret; + } + } +#else + /* Attach the SDADC interrupt */ + + ret = irq_attach(priv->irq, priv->isr); + if (ret < 0) + { + ainfo("irq_attach failed: %d\n", ret); + return ret; + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: sdadc_shutdown + * + * Description: + * Disable the ADC. This method is called when the last instance + * of the SDADC device is closed by the user application. + * This method reverses the operation the setup method. + * + * Input Parameters: + * dev - pointer to the sdadc device structure + * + * Returned Value: + * + ****************************************************************************/ + +static void sdadc_shutdown(FAR struct adc_dev_s *dev) +{ + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; + + /* Put the device in low power mode */ + + sdadc_enable(priv, false); + + /* Disable intrerrupt / dma */ + + sdadc_rxint(dev, false); + +#ifdef SDADC_HAVE_DMA + if (priv->hasdma) + { + /* Stop and free DMA if it was started before */ + + if (priv->dma != NULL) + { + stm32_dmastop(priv->dma); + stm32_dmafree(priv->dma); + } + } + else + { + /* Disable ADC interrupts and detach the SDADC interrupt handler */ + + up_disable_irq(priv->irq); + irq_detach(priv->irq); + } +#else + /* Disable ADC interrupts and detach the SDADC interrupt handler */ + + up_disable_irq(priv->irq); + irq_detach(priv->irq); +#endif +} + +/**************************************************************************** + * Name: sdadc_rxint + * + * Description: + * Call to enable or disable RX interrupts. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static void sdadc_rxint(FAR struct adc_dev_s *dev, bool enable) +{ + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; + uint32_t setbits; + + ainfo("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0); + + /* DMA mode */ + +#ifdef SDADC_HAVE_DMA + if (priv->hasdma) + { + setbits = SDADC_CR1_JDMAEN; // DMA enabled for injected channels group + } + else + { + /* Interrupt enable for injected channel group overrun + and end of conversion */ + setbits = SDADC_CR1_JOVRIE | SDADC_CR1_JEOCIE; + } +#else + setbits = SDADC_CR1_JOVRIE | SDADC_CR1_JEOCIE; +#endif + + if (enable) + { + /* Enable */ + + sdadc_modifyreg(priv, STM32_SDADC_CR1_OFFSET, 0, setbits); + } + else + { + /* Disable all ADC interrupts and DMA */ + + sdadc_modifyreg(priv, STM32_SDADC_CR1_OFFSET, + SDADC_CR1_JOVRIE | SDADC_CR1_JEOCIE | SDADC_CR1_JDMAEN, + 0); + } +} + +/**************************************************************************** + * Name: sdadc_set_ch + * + * Description: + * Sets the SDADC injected channel group. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * ch - ADC channel number + 1. 0 reserved for all configured channels + * + * Returned Value: + * int - errno + * + ****************************************************************************/ + +static int sdadc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch) +{ + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; + uint32_t bits = 0; + int i; + + if (ch == 0) + { + priv->current = 0; + priv->nchannels = priv->cchannels; + } + else + { + for (i = 0; i < priv->cchannels && priv->chanlist[i] != ch - 1; i++); + + if (i >= priv->cchannels) + { + return -ENODEV; + } + + priv->current = i; + priv->nchannels = 1; + } + + for (i = 0; i < priv->nchannels; i++) + { + bits |= (uint32_t)(1 << priv->chanlist[i]); + } + + sdadc_putreg(priv, STM32_SDADC_JCHGR_OFFSET, bits); + + return OK; +} + +/**************************************************************************** + * Name: sdadc_ioctl + * + * Description: + * All ioctl calls will be routed through this method. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * cmd - command + * arg - arguments passed with command + * + * Returned Value: + * + ****************************************************************************/ + +static int sdadc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) +{ + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; + int ret = OK; + + switch (cmd) + { + case ANIOC_TRIGGER: + sdadc_startconv(priv, true); + break; + + default: + aerr("ERROR: Unknown cmd: %d\n", cmd); + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: sdadc_interrupt + * + * Description: + * Common SDADC interrupt handler. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static int sdadc_interrupt(FAR struct adc_dev_s *dev) +{ + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; + uint32_t regval; + uint32_t pending; + int32_t data; + uint8_t chan; + + regval = sdadc_getreg(priv, STM32_SDADC_ISR_OFFSET); + pending = regval & SDADC_ISR_ALLINTS; + if (pending == 0) + { + return OK; + } + + /* JOVRF: overrun flag */ + + if ((regval & SDADC_ISR_JOVRF) != 0) + { + awarn("WARNING: Overrun has occurred!\n"); + } + + /* JEOCF: End of conversion */ + + if ((regval & SDADC_ISR_JEOCF) != 0) + { + /* Read the converted value and clear JEOCF bit + * (It is cleared by reading the SDADC_JDATAR) */ + + data = sdadc_getreg(priv, STM32_SDADC_JDATAR_OFFSET) & SDADC_JDATAR_JDATA_MASK; + chan = sdadc_getreg(priv, STM32_SDADC_JDATAR_OFFSET) & SDADC_JDATAR_JDATACH_MASK; + + DEBUGASSERT(priv->chanlist[priv->current] == chan); + + /* Verify that the upper-half driver has bound its callback functions */ + + if (priv->cb != NULL) + { + /* Give the SDADC data to the ADC driver. The ADC receive() method + * accepts 3 parameters: + * + * 1) The first is the ADC device instance for this SDADC block. + * 2) The second is the channel number for the data, and + * 3) The third is the converted data for the channel. + */ + + DEBUGASSERT(priv->cb->au_receive != NULL); + priv->cb->au_receive(dev, chan, data); + } + + /* Set the channel number of the next channel that will complete + * conversion. + */ + + priv->current++; + + if (priv->current >= priv->nchannels) + { + /* Restart the conversion sequence from the beginning */ + + priv->current = 0; + } + + /* do no clear this interrupt (cleared by reading data) */ + + pending &= ~SDADC_ISR_JEOCF; + } + + /* Clears interrupt flags, if any */ + + if (pending) + { + sdadc_putreg(priv, STM32_SDADC_CLRISR_OFFSET, pending); + } + + return OK; +} + +/**************************************************************************** + * Name: adc1_interrupt + * + * Description: + * ADC interrupt handler SDADC1 + * + * Input Parameters: + * irq - The IRQ number that generated the interrupt. + * context - Architecture specific register save information. + * + * Returned Value: + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_SDADC1) +static int sdadc1_interrupt(int irq, FAR void *context) +{ + sdadc_interrupt(&g_sdadcdev1); + + return OK; +} +#endif + +/**************************************************************************** + * Name: adc2_interrupt + * + * Description: + * ADC interrupt handler SDADC2 + * + * Input Parameters: + * irq - The IRQ number that generated the interrupt. + * context - Architecture specific register save information. + * + * Returned Value: + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_SDADC2) +static int sdadc2_interrupt(int irq, FAR void *context) +{ + sdadc_interrupt(&g_sdadcdev2); + + return OK; +} +#endif + +/**************************************************************************** + * Name: adc3_interrupt + * + * Description: + * ADC interrupt handler SDADC3 + * + * Input Parameters: + * irq - The IRQ number that generated the interrupt. + * context - Architecture specific register save information. + * + * Returned Value: + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_SDADC3) +static int sdadc3_interrupt(int irq, FAR void *context) +{ + sdadc_interrupt(&g_sdadcdev3); + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdadcinitialize + * + * Description: + * Initialize one SDADC block + * + * The logic is, save and initialize the channel list in the private driver + * structure and return the corresponding adc device structure. + * + * Each SDADC will convert the channels indicated each + * time a conversion is triggered either by sofware, timer or external event. + * Channels are numbered from 0 - 8 and must be given in order (contrarily + * to what says ST RM0313 doc !!!). + * + * Input Parameters: + * intf - Could be {1,2,3} for SDADC1, SDADC2, or SDADC3 + * chanlist - The list of channels eg. { 0, 3, 7, 8 } + * cchannels - Number of channels + * + * Returned Value: + * Valid ADC device structure reference on succcess; a NULL on failure + * + ****************************************************************************/ + +struct adc_dev_s *stm32_sdadcinitialize(int intf, FAR const uint8_t *chanlist, + int cchannels) +{ + FAR struct adc_dev_s *dev; + FAR struct stm32_dev_s *priv; + int i; + + ainfo("intf: %d cchannels: %d\n", intf, cchannels); + + switch (intf) + { +#ifdef CONFIG_STM32_SDADC1 + case 1: + ainfo("SDADC1 selected\n"); + dev = &g_sdadcdev1; + break; +#endif +#ifdef CONFIG_STM32_SDADC2 + case 2: + ainfo("SDADC2 selected\n"); + dev = &g_sdadcdev2; + break; +#endif +#ifdef CONFIG_STM32_SDADC3 + case 3: + ainfo("SDADC3 selected\n"); + dev = &g_sdadcdev3; + break; +#endif + default: + aerr("ERROR: No SDADC interface defined\n"); + return NULL; + } + + /* Check channel list in order */ + + DEBUGASSERT((cchannels <= SDADC_MAX_SAMPLES) && (cchannels > 0)); + for (i = 0; i < cchannels - 1; i ++) + { + if (chanlist[i] >= chanlist[i+1]) + { + aerr("ERROR: SDADC channel list must be given in order\n"); + return NULL; + } + } + + /* Configure the selected SDADC */ + + priv = (FAR struct stm32_dev_s *)dev->ad_priv; + + priv->cb = NULL; + priv->cchannels = cchannels; + + memcpy(priv->chanlist, chanlist, cchannels); + + return dev; +} + +#endif /* CONFIG_STM32_SDADC1 || CONFIG_STM32_SDADC2 || + * CONFIG_STM32_SDADC3 */ +#endif /* CONFIG_STM32_SDADC */ diff --git a/arch/arm/src/stm32/stm32_sdadc.h b/arch/arm/src/stm32/stm32_sdadc.h new file mode 100644 index 0000000000..b2f7ffedd9 --- /dev/null +++ b/arch/arm/src/stm32/stm32_sdadc.h @@ -0,0 +1,426 @@ +/************************************************************************************ + * arch/arm/src/stm32/stm32_sdadc.h + * + * Copyright (C) 2009, 2011, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Studelec. All rights reserved. + * Authors: Gregory Nutt + * Marc Rechté + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_SDADC_H +#define __ARCH_ARM_SRC_STM32_STM32_SDADC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +#if defined(CONFIG_STM32_STM32F37XX) +# include "chip/stm32f37xxx_sdadc.h" +#else +/* No generic chip/stm32_sdadc.h yet */ + +# error "This chip is not yet supported" +#endif + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Configuration ********************************************************************/ +/* Timer devices may be used for different purposes. One special purpose is to + * control periodic SDADC sampling. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_SDADC must also be defined to indicate that timer "n" is intended + * to be used for that purpose. + */ + +/* For the STM32 F37XX line, timers 2-4, 12-17 an 19 may be used. */ + +/* TODO cf. stm32_adc.h */ + +/* Up to 3 SDADC interfaces are supported */ + +#if STM32_NSDADC < 3 +# undef CONFIG_STM32_SDADC3 +#endif + +#if STM32_NSDADC < 2 +# undef CONFIG_STM32_SDADC2 +#endif + +#if STM32_NSDADC < 1 +# undef CONFIG_STM32_SDADC1 +#endif + +#if defined(CONFIG_STM32_SDADC1) || defined(CONFIG_STM32_SDADC2) || \ + defined(CONFIG_STM32_SDADC3) + +/* DMA support */ + +#if defined(CONFIG_STM32_SDADC1_DMA) || defined(CONFIG_STM32_SDADC2_DMA) || \ + defined(CONFIG_STM32_SDADC3_DMA) +# define SDADC_HAVE_DMA 1 +#endif + +#ifdef CONFIG_STM32_SDADC1_DMA +# define SDADC1_HAVE_DMA 1 +#else +# undef SDADC1_HAVE_DMA +#endif + +#ifdef CONFIG_STM32_SDADC2_DMA +# define SDADC2_HAVE_DMA 1 +#else +# undef SDADC2_HAVE_DMA +#endif + +#ifdef CONFIG_STM32_SDADC3_DMA +# define SDADC3_HAVE_DMA 1 +#else +# undef SDADC3_HAVE_DMA +#endif + +/* SDADC Channels/DMA ****************************************************** + * The maximum number of channels that can be sampled at each scan. + * If DMA support is not enabled, then only a single channel + * ought to be sampled. + * Otherwise, unless sampling frequency is reduced, + * data overruns would occur. + */ + +#define SDADC_MAX_CHANNELS_DMA 9 +#define SDADC_MAX_CHANNELS_NODMA 1 + +#ifndef SDADC_MAX_SAMPLES +#ifdef SDADC_HAVE_DMA +# define SDADC_MAX_SAMPLES SDADC_MAX_CHANNELS_DMA +#else +# define SDADC_MAX_SAMPLES SDADC_MAX_CHANNELS_NODMA +#endif +#endif + +/* Timer configuration: If a timer trigger is specified, then get + * information about the timer. + */ + +#if defined(CONFIG_STM32_TIM3_SDADC1) +# define SDADC1_HAVE_TIMER 1 +# define SDADC1_TIMER_BASE STM32_TIM3_BASE +# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +#elif defined(CONFIG_STM32_TIM4_SDADC1) +# define SDADC1_HAVE_TIMER 1 +# define SDADC1_TIMER_BASE STM32_TIM4_BASE +# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +#elif defined(CONFIG_STM32_TIM13_SDADC1) +# define SDADC1_HAVE_TIMER 1 +# define SDADC1_TIMER_BASE STM32_TIM13_BASE +# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM13_CLKIN +#elif defined(CONFIG_STM32_TIM14_SDADC1) +# define SDADC1_HAVE_TIMER 1 +# define SDADC1_TIMER_BASE STM32_TIM14_BASE +# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM14_CLKIN +#elif defined(CONFIG_STM32_TIM15_SDADC1) +# define SDADC1_HAVE_TIMER 1 +# define SDADC1_TIMER_BASE STM32_TIM15_BASE +# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +#elif defined(CONFIG_STM32_TIM19_SDADC1) +# define SDADC1_HAVE_TIMER 1 +# define SDADC1_TIMER_BASE STM32_TIM19_BASE +# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM19_CLKIN +#else +# undef SDADC1_HAVE_TIMER +#endif + +#ifdef SDADC1_HAVE_TIMER +# ifndef CONFIG_STM32_SDADC1_SAMPLE_FREQUENCY +# error "CONFIG_STM32_SDADC1_SAMPLE_FREQUENCY not defined" +# endif +# ifndef CONFIG_STM32_SDADC1_TIMTRIG +# error "CONFIG_STM32_SDADC1_TIMTRIG not defined" +# warning "Values 0:TIM13_CH1 1:TIM14_CH1 2:TIM15_CH2 3:TIM3_CH1 4:TIM4_CH1 5:TIM19_CH2" +# endif +#endif + +#if defined(CONFIG_STM32_TIM2_SDADC2) +# define SDADC2_HAVE_TIMER 1 +# define SDADC2_TIMER_BASE STM32_TIM2_BASE +# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +#elif defined(CONFIG_STM32_TIM3_SDADC2) +# define SDADC2_HAVE_TIMER 1 +# define SDADC2_TIMER_BASE STM32_TIM3_BASE +# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +#elif defined(CONFIG_STM32_TIM4_SDADC2) +# define SDADC2_HAVE_TIMER 1 +# define SDADC2_TIMER_BASE STM32_TIM4_BASE +# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +#elif defined(CONFIG_STM32_TIM12_SDADC2) +# define SDADC2_HAVE_TIMER 1 +# define SDADC2_TIMER_BASE STM32_TIM12_BASE +# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM12_CLKIN +#elif defined(CONFIG_STM32_TIM17_SDADC2) +# define SDADC2_HAVE_TIMER 1 +# define SDADC2_TIMER_BASE STM32_TIM17_BASE +# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM17_CLKIN +#elif defined(CONFIG_STM32_TIM19_SDADC2) +# define SDADC2_HAVE_TIMER 1 +# define SDADC2_TIMER_BASE STM32_TIM19_BASE +# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM19_CLKIN +#else +# undef SDADC2_HAVE_TIMER +#endif + +#ifdef SDADC2_HAVE_TIMER +# ifndef CONFIG_STM32_SDADC2_SAMPLE_FREQUENCY +# error "CONFIG_STM32_SDADC2_SAMPLE_FREQUENCY not defined" +# endif +# ifndef CONFIG_STM32_SDADC2_TIMTRIG +# error "CONFIG_STM32_SDADC2_TIMTRIG not defined" +# warning "Values 0:TIM17_CH1 1:TIM12_CH1 2:TIM2_CH3 3:TIM3_CH2 4:TIM4_CH2 5:TIM19_CH3" +# endif +#endif + +#if defined(CONFIG_STM32_TIM2_SDADC3) +# define SDADC3_HAVE_TIMER 1 +# define SDADC3_TIMER_BASE STM32_TIM2_BASE +# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +#elif defined(CONFIG_STM32_TIM3_SDADC3) +# define SDADC3_HAVE_TIMER 1 +# define SDADC3_TIMER_BASE STM32_TIM3_BASE +# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +#elif defined(CONFIG_STM32_TIM4_SDADC3) +# define SDADC3_HAVE_TIMER 1 +# define SDADC3_TIMER_BASE STM32_TIM4_BASE +# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +#elif defined(CONFIG_STM32_TIM12_SDADC3) +# define SDADC3_HAVE_TIMER 1 +# define SDADC3_TIMER_BASE STM32_TIM12_BASE +# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM12_CLKIN +#elif defined(CONFIG_STM32_TIM16_SDADC3) +# define SDADC3_HAVE_TIMER 1 +# define SDADC3_TIMER_BASE STM32_TIM16_BASE +# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM16_CLKIN +#elif defined(CONFIG_STM32_TIM19_SDADC3) +# define SDADC3_HAVE_TIMER 1 +# define SDADC3_TIMER_BASE STM32_TIM19_BASE +# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM19_CLKIN +#else +# undef SDADC3_HAVE_TIMER +#endif + +#ifdef SDADC3_HAVE_TIMER +# ifndef CONFIG_STM32_SDADC3_SAMPLE_FREQUENCY +# error "CONFIG_STM32_SDADC3_SAMPLE_FREQUENCY not defined" +# endif +# ifndef CONFIG_STM32_SDADC3_TIMTRIG +# error "CONFIG_STM32_SDADC3_TIMTRIG not defined" +# warning "Values 0:TIM16_CH1 1:TIM12_CH2 2:TIM2_CH4 3:TIM3_CH3 4:TIM4_CH3 5:TIM19_CH4" +# endif +#endif + +#if defined(SDADC1_HAVE_TIMER) || defined(SDADC2_HAVE_TIMER) || \ + defined(SDADC3_HAVE_TIMER) +# define SDADC_HAVE_TIMER 1 +# if defined(CONFIG_STM32_STM32F37XX) && !defined(CONFIG_STM32_FORCEPOWER) +# warning "CONFIG_STM32_FORCEPOWER must be defined to enable the timer(s)" +# endif +#else +# undef SDADC_HAVE_TIMER +#endif + +/* NOTE: The following assumes that all possible combinations of timers and + * values are support JEXTSEL. That is not so and it varies from one STM32 + * to another. But this (wrong) assumptions keeps the logic as simple as + * possible. If unsupported combination is used, an error will show up + * later during compilation although it may be difficult to track it back + * to this simplification. + * + * STM32L37XX-family has 3 SDADC onboard + */ + +#ifdef CONFIG_STM32_STM32F37XX +# define SDADC1_JEXTSEL_TIM13_CH1 SDADC1_CR2_JEXTSEL_TIM13_CH1 +# define SDADC1_JEXTSEL_TIM14_CH1 SDADC1_CR2_JEXTSEL_TIM14_CH1 +# define SDADC1_JEXTSEL_TIM15_CH2 SDADC1_CR2_JEXTSEL_TIM15_CH2 +# define SDADC1_JEXTSEL_TIM3_CH1 SDADC1_CR2_JEXTSEL_TIM3_CH1 +# define SDADC1_JEXTSEL_TIM4_CH1 SDADC1_CR2_JEXTSEL_TIM4_CH1 +# define SDADC1_JEXTSEL_TIM19_CH2 SDADC1_CR2_JEXTSEL_TIM19_CH2 +# define SDADC1_JEXTSEL_EXTI15 SDADC1_CR2_JEXTSEL_EXTI15 +# define SDADC1_JEXTSEL_EXTI11 SDADC1_CR2_JEXTSEL_EXTI11 +# define SDADC2_JEXTSEL_TIM17_CH1 SDADC2_CR2_JEXTSEL_TIM17_CH1 +# define SDADC2_JEXTSEL_TIM12_CH1 SDADC2_CR2_JEXTSEL_TIM12_CH1 +# define SDADC2_JEXTSEL_TIM2_CH3 SDADC2_CR2_JEXTSEL_TIM2_CH3 +# define SDADC2_JEXTSEL_TIM3_CH2 SDADC2_CR2_JEXTSEL_TIM3_CH2 +# define SDADC2_JEXTSEL_TIM4_CH2 SDADC2_CR2_JEXTSEL_TIM4_CH2 +# define SDADC2_JEXTSEL_TIM19_CH3 SDADC2_CR2_JEXTSEL_TIM19_CH3 +# define SDADC2_JEXTSEL_EXTI15 SDADC2_CR2_JEXTSEL_EXTI15 +# define SDADC2_JEXTSEL_EXTI11 SDADC2_CR2_JEXTSEL_EXTI11 +# define SDADC3_JEXTSEL_TIM16_CH1 SDADC3_CR2_JEXTSEL_TIM16_CH1 +# define SDADC3_JEXTSEL_TIM12_CH1 SDADC3_CR2_JEXTSEL_TIM12_CH1 +# define SDADC3_JEXTSEL_TIM2_CH4 SDADC3_CR2_JEXTSEL_TIM2_CH4 +# define SDADC3_JEXTSEL_TIM3_CH3 SDADC3_CR2_JEXTSEL_TIM3_CH3 +# define SDADC3_JEXTSEL_TIM4_CH3 SDADC3_CR2_JEXTSEL_TIM4_CH3 +# define SDADC3_JEXTSEL_TIM19_CH4 SDADC3_CR2_JEXTSEL_TIM19_CH4 +# define SDADC3_JEXTSEL_EXTI15 SDADC3_CR2_JEXTSEL_EXTI15 +# define SDADC3_JEXTSEL_EXTI11 SDADC3_CR2_JEXTSEL_EXTI11 +#endif + +#if defined(CONFIG_STM32_TIM3_SDADC1) +# define SDADC1_JEXTSEL_VALUE 3 +#elif defined(CONFIG_STM32_TIM4_SDADC1) +# define SDADC1_JEXTSEL_VALUE 4 +#elif defined(CONFIG_STM32_TIM13_SDADC1) +# define SDADC1_JEXTSEL_VALUE 0 +#elif defined(CONFIG_STM32_TIM14_SDADC1) +# define SDADC1_JEXTSEL_VALUE 1 +#elif defined(CONFIG_STM32_TIM15_SDADC1) +# define SDADC1_JEXTSEL_VALUE 2 +#elif defined(CONFIG_STM32_TIM19_SDADC1) +# define SDADC1_JEXTSEL_VALUE 5 +#else +# undef SDADC1_JEXTSEL_VALUE +#endif + +#if defined(CONFIG_STM32_TIM2_SDADC2) +# define SDADC2_JEXTSEL_VALUE 2 +#elif defined(CONFIG_STM32_TIM3_SDADC2) +# define SDADC2_JEXTSEL_VALUE 3 +#elif defined(CONFIG_STM32_TIM4_SDADC2) +# define SDADC2_JEXTSEL_VALUE 4 +#elif defined(CONFIG_STM32_TIM12_SDADC2) +# define SDADC2_JEXTSEL_VALUE 1 +#elif defined(CONFIG_STM32_TIM17_SDADC2) +# define SDADC2_JEXTSEL_VALUE 0 +#elif defined(CONFIG_STM32_TIM19_SDADC2) +# define SDADC2_JEXTSEL_VALUE 5 +#else +# undef SDADC2_JEXTSEL_VALUE +#endif + +#if defined(CONFIG_STM32_TIM2_SDADC3) +# define SDADC3_JEXTSEL_VALUE 2 +#elif defined(CONFIG_STM32_TIM3_SDADC3) +# define SDADC3_JEXTSEL_VALUE 3 +#elif defined(CONFIG_STM32_TIM4_SDADC3) +# define SDADC3_JEXTSEL_VALUE 4 +#elif defined(CONFIG_STM32_TIM12_SDADC3) +# define SDADC3_JEXTSEL_VALUE 1 +#elif defined(CONFIG_STM32_TIM16_SDADC3) +# define SDADC3_JEXTSEL_VALUE 0 +#elif defined(CONFIG_STM32_TIM19_SDADC3) +# define SDADC3_JEXTSEL_VALUE 5 +#else +# undef SDADC3_JEXTSEL_VALUE +#endif + +/* SDADC Configurations ******************************************************** + * Up to 3 configuration profiles may be defined in order to define: + * - calibration method + * - SE/differential mode + * - input gain + * Each of the 9 SDADC channels is assigned to a configuration profile + */ +#ifndef SDADC_CONF0R_DEFAULT +# define SDADC_CONF0R_DEFAULT (SDADC_CONFR_GAIN_1X | SDADC_CONFR_SE_SE_OFFSET | SDADC_CONFR_COMMON_GND) +#endif +#ifndef SDADC_CONF1R_DEFAULT +# define SDADC_CONF1R_DEFAULT (SDADC_CONFR_GAIN_2X | SDADC_CONFR_SE_SE_OFFSET | SDADC_CONFR_COMMON_GND) +#endif +#ifndef SDADC_CONF2R_DEFAULT +# define SDADC_CONF2R_DEFAULT (SDADC_CONFR_GAIN_4X | SDADC_CONFR_SE_SE_OFFSET | SDADC_CONFR_COMMON_GND) +#endif +#ifndef SDADC_CONFCHR1_DEFAULT +# define SDADC_CONFCHR1_DEFAULT ((SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(0)) | \ + (SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(1)) | \ + (SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(2)) | \ + (SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(3)) | \ + (SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(4)) | \ + (SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(5)) | \ + (SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(6)) | \ + (SDADC_CONF0R << SDADC_CONFCHR1_CH_SHIFT(7))) +#endif +#ifndef SDADC_CONFCHR2_DEFAULT +# define SDADC_CONFCHR2_DEFAULT (SDADC_CONF0R << SDADC_CONFCHR2_CH8_SHIFT) +#endif + +/* SDADC Reference voltage selection ************************************************/ + +#ifndef SDADC_REFV_DEFAULT +# define SDADC_REFV_DEFAULT SDADC_CR1_REFV_EXT +#endif +#ifndef SDADC1_REFV +# define SDADC1_REFV SDADC_REFV_DEFAULT +#endif +#ifndef SDADC2_REFV +# define SDADC2_REFV SDADC_REFV_DEFAULT +#endif +#ifndef SDADC3_REFV +# define SDADC3_REFV SDADC_REFV_DEFAULT +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_sdadcinitialize + * + ****************************************************************************/ + +struct adc_dev_s *stm32_sdadcinitialize(int intf, FAR const uint8_t *chanlist, + int nchannels); + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_STM32_SDADC1 || CONFIG_STM32_SDADC2 || + * CONFIG_STM32_SDADC3 + */ +#endif /* __ARCH_ARM_SRC_STM32_STM32_SDADC_H */ diff --git a/arch/arm/src/stm32/stm32f30xxx_i2c.c b/arch/arm/src/stm32/stm32f30xxx_i2c.c index 141b0deb75..27b1c92488 100644 --- a/arch/arm/src/stm32/stm32f30xxx_i2c.c +++ b/arch/arm/src/stm32/stm32f30xxx_i2c.c @@ -101,7 +101,7 @@ #if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || defined(CONFIG_STM32_I2C3) /* This implementation is for the STM32 F1, F2, and F4 only */ -#if defined(CONFIG_STM32_STM32F30XX) +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) /************************************************************************************ * Pre-processor Definitions @@ -1949,7 +1949,7 @@ out: FAR struct i2c_master_s *stm32_i2cbus_initialize(int port) { struct stm32_i2c_priv_s * priv = NULL; /* private data of device with multiple instances */ - irqtate_t flags; + irqstate_t flags; #if STM32_PCLK1_FREQUENCY < 4000000 # warning STM32_I2C_INIT: Peripheral clock must be at least 4 MHz to support 400 kHz operation. diff --git a/arch/arm/src/stm32/stm32f37xxx_rcc.c b/arch/arm/src/stm32/stm32f37xxx_rcc.c index 02fa9fd930..6b83ee316c 100644 --- a/arch/arm/src/stm32/stm32f37xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f37xxx_rcc.c @@ -80,7 +80,7 @@ static inline void rcc_reset(void) regval |= RCC_CR_HSION; putreg32(regval, STM32_RCC_CR); - regval = getreg32(STM32_RCC_CFGR); /* Reset SW, HPRE, PPRE1, PPRE2, USBPRE, and MCO bits */ + regval = getreg32(STM32_RCC_CFGR); /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE, USBPRE, MCO, SDADC bits */ regval &= ~(RCC_CFGR_SW_MASK | RCC_CFGR_HPRE_MASK | RCC_CFGR_PPRE1_MASK | RCC_CFGR_PPRE2_MASK | RCC_CFGR_USBPRE | RCC_CFGR_MCO_MASK); putreg32(regval, STM32_RCC_CFGR); @@ -107,6 +107,7 @@ static inline void rcc_reset(void) putreg32(0, STM32_RCC_CIR); /* Disable all interrupts */ } + /**************************************************************************** * Name: rcc_enableahb * @@ -169,7 +170,7 @@ static inline void rcc_enableapb1(void) #ifdef CONFIG_STM32_USB /* USB clock divider. This bit must be valid before enabling the USB - * clock in the RCC_APB1ENR register. This bit can’t be reset if the USB + * clock in the RCC_APB1ENR register. This bit can't be reset if the USB * clock is enabled. */ @@ -356,6 +357,28 @@ static inline void rcc_enableapb2(void) { uint32_t regval; +#if defined(CONFIG_STM32_SDADC) || defined(CONFIG_STM32_ADC) + /* Adjust clock of selected peripherals */ + + regval = getreg32(STM32_RCC_CFGR); + +#ifdef CONFIG_STM32_ADC + /* ADC clock divider */ + + regval &= ~RCC_CFGR_ADCPRE_MASK; + regval |= STM32_RCC_ADCPRE; +#endif + +#ifdef CONFIG_STM32_SDADC + /* SDADC clock divider */ + + regval &= ~RCC_CFGR_SDPRE_MASK; + regval |= STM32_RCC_SDPRE; +#endif + + putreg32(regval, STM32_RCC_CFGR); +#endif + /* Set the appropriate bits in the APB2ENR register to enabled the * selected APB2 peripherals. */ @@ -368,6 +391,12 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; #endif +#ifdef CONFIG_STM32_ADC1 + /* ADC clock enable */ + + regval |= RCC_APB2ENR_ADC1EN; +#endif + #ifdef CONFIG_STM32_SPI1 /* SPI 1 clock enable */ @@ -412,6 +441,24 @@ static inline void rcc_enableapb2(void) #endif #endif +#ifdef CONFIG_STM32_SDADC1 + /* SDCADC1 clock enable */ + + regval |= RCC_APB2ENR_SDADC1EN; +#endif + +#ifdef CONFIG_STM32_SDADC2 + /* SDCADC2 clock enable */ + + regval |= RCC_APB2ENR_SDADC2EN; +#endif + +#ifdef CONFIG_STM32_SDADC3 + /* SDCADC3 clock enable */ + + regval |= RCC_APB2ENR_SDADC3EN; +#endif + putreg32(regval, STM32_RCC_APB2ENR); } @@ -469,13 +516,13 @@ static void stm32_stdclockconfig(void) /* If this is a value-line part and we are using the HSE as the PLL */ -# if (STM32_CFGR_PLLXTPRE >> 17) != (STM32_CFGR2_PREDIV1 & 1) -# error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV1 +# if (STM32_CFGR_PLLXTPRE >> 17) != (STM32_CFGR2_PREDIV & 1) +# error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV # endif /* Set the HSE prescaler */ - regval = STM32_CFGR2_PREDIV1; + regval = STM32_CFGR2_PREDIV; putreg32(regval, STM32_RCC_CFGR2); # endif diff --git a/configs/nucleo-f303re/src/Makefile b/configs/nucleo-f303re/src/Makefile index 7d81b2cbe1..a4906030e7 100644 --- a/configs/nucleo-f303re/src/Makefile +++ b/configs/nucleo-f303re/src/Makefile @@ -62,6 +62,10 @@ ifeq ($(CONFIG_CAN),y) CSRCS += stm32_can.c endif +ifeq ($(CONFIG_DAC),y) +CSRCS += stm32_dac.c +endif + ifeq ($(CONFIG_PWM),y) CSRCS += stm32_pwm.c endif diff --git a/configs/nucleo-f303re/src/nucleo-f303re.h b/configs/nucleo-f303re/src/nucleo-f303re.h index 526bc7ee9a..8d9d21d227 100644 --- a/configs/nucleo-f303re/src/nucleo-f303re.h +++ b/configs/nucleo-f303re/src/nucleo-f303re.h @@ -69,6 +69,8 @@ #define GPIO_LED1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN5) +#define LED_DRIVER_PATH "/dev/userleds" + /* Button definitions *******************************************************/ /* The Nucleo F303RE supports two buttons; only one button is controllable * by software: @@ -153,4 +155,16 @@ void weak_function stm32_spidev_initialize(void); int stm32_timer_driver_setup(FAR const char *devpath, int timer); #endif +/**************************************************************************** + * Name: stm32_dac_setup + * + * Description: + * Configure DAC peripheral for the board. + * + ****************************************************************************/ + +#ifdef CONFIG_DAC +int stm32_dac_setup(void); +#endif + #endif /* __CONFIGS_NUCLEO_F303RE_SRC_NUCLEO_F303RE_H */ diff --git a/configs/nucleo-f303re/src/stm32_adc.c b/configs/nucleo-f303re/src/stm32_adc.c index 10871a82da..2c2e0bed28 100644 --- a/configs/nucleo-f303re/src/stm32_adc.c +++ b/configs/nucleo-f303re/src/stm32_adc.c @@ -58,37 +58,66 @@ * Pre-processor Definitions ****************************************************************************/ +#if (defined(CONFIG_STM32_ADC1) && defined(CONFIG_STM32_ADC2)) || \ + (defined(CONFIG_STM32_ADC3) && defined(CONFIG_STM32_ADC4)) +# error "will not work with this combination of ADCs" +#endif + /* Configuration ************************************************************/ -#if defined(CONFIG_STM32_ADC1) && !defined(CONFIG_STM32_ADC2) && \ - !defined(CONFIG_STM32_ADC3) && !defined(CONFIG_STM32_ADC4) -# define ADC_PORT 1 -#elif defined(CONFIG_STM32_ADC2) && !defined(CONFIG_STM32_ADC1) && \ - !defined(CONFIG_STM32_ADC3) && !defined(CONFIG_STM32_ADC4) -# define ADC_PORT 2 -#elif defined(CONFIG_STM32_ADC3) && !defined(CONFIG_STM32_ADC1) && \ - !defined(CONFIG_STM32_ADC2) && !defined(CONFIG_STM32_ADC4) -# define ADC_PORT 3 -#elif defined(CONFIG_STM32_ADC4) && !defined(CONFIG_STM32_ADC1) && \ - !defined(CONFIG_STM32_ADC2) && !defined(CONFIG_STM32_ADC3) -# define ADC_PORT 4 -#else -# error "Choose only one of ADC1, ADC2, ADC3, ADC4" +/* 1 or 2 ADC devices (DEV1, DEV2) */ + +#if defined(CONFIG_STM32_ADC1) +# define DEV1_PORT 1 +#endif + +#if defined(CONFIG_STM32_ADC2) +# if defined(DEV1_PORT) +# define DEV2_PORT 2 +# else +# define DEV1_PORT 2 +# endif +#endif + +#if defined(CONFIG_STM32_ADC3) +# if defined(DEV2_PORT) +# error "Choose maximum two of ADC1, ADC2, ADC3, ADC4" +# else +# if defined(DEV1_PORT) +# define DEV2_PORT 3 +# else +# define DEV1_PORT 3 +# endif +# endif +#endif + +#if defined(CONFIG_STM32_ADC4) +# if defined(DEV2_PORT) +# error "Choose maximum two of ADC1, ADC2, ADC3, ADC4" +# else +# if defined(DEV1_PORT) +# define DEV2_PORT 4 +# else +# define DEV1_PORT 4 +# endif +# endif #endif /* The number of ADC channels in the conversion list */ +/* TODO DMA */ -#if defined(CONFIG_STM32_ADC1) && defined(ADC1_HAVE_DMA) -# define ADC_NCHANNELS 4 -#elif defined(CONFIG_STM32_ADC2) && defined(ADC2_HAVE_DMA) -# define ADC_NCHANNELS 3 -#elif defined(CONFIG_STM32_ADC3) && defined(ADC3_HAVE_DMA) -# define ADC_NCHANNELS 1 -#elif defined(CONFIG_STM32_ADC4) && defined(ADC4_HAVE_DMA) -# define ADC_NCHANNELS 1 +#if defined(ADC1_HAVE_DMA) +# error "ADC1 with DMA support is not fully implemented" #else -# define ADC_NCHANNELS 1 +# define ADC1_NCHANNELS 4 #endif +#if defined(ADC2_HAVE_DMA) +# error "ADC2 with DMA support is not fully implemented" +#else +# define ADC2_NCHANNELS 3 +#endif +#define ADC3_NCHANNELS 3 +#define ADC4_NCHANNELS 1 /**************************************************************************** * Private Function Prototypes @@ -98,88 +127,187 @@ * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32_ADC1) +/* DEV 1 */ -/* Identifying number of each ADC channel */ +#if DEV1_PORT == 1 + +#define DEV1_NCHANNELS ADC1_NCHANNELS -static const uint8_t g_chanlist[ADC_NCHANNELS] = +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[4] = { 1, -#ifdef ADC1_HAVE_DMA 2, 6, 7, -#endif }; /* Configurations of pins used by each ADC channel */ -static const uint32_t g_pinlist[ADC_NCHANNELS] = +static const uint32_t g_pinlist1[4] = { GPIO_ADC1_IN1, -#ifdef ADC1_HAVE_DMA GPIO_ADC1_IN2, GPIO_ADC1_IN6, - GPIO_ADC1_IN7, -#endif + GPIO_ADC1_IN7 }; -#elif defined(CONFIG_STM32_ADC2) +#elif DEV1_PORT == 2 + +#define DEV1_NCHANNELS ADC2_NCHANNELS /* Identifying number of each ADC channel */ -static const uint8_t g_chanlist[ADC_NCHANNELS] = +static const uint8_t g_chanlist1[3] = { 1, -#ifdef ADC2_HAVE_DMA - 6, - 7, -#endif + 3, + 4 }; /* Configurations of pins used by each ADC channel */ -static const uint32_t g_pinlist[ADC_NCHANNELS] = +static const uint32_t g_pinlist1[3] = { GPIO_ADC2_IN1, -#ifdef ADC2_HAVE_DMA - GPIO_ADC2_IN6, - GPIO_ADC2_IN7, -#endif + GPIO_ADC2_IN3, + GPIO_ADC2_IN4 }; -#elif defined(CONFIG_STM32_ADC3) +#elif DEV1_PORT == 3 + +#define DEV1_NCHANNELS ADC3_NCHANNELS /* Identifying number of each ADC channel */ -static const uint8_t g_chanlist[ADC_NCHANNELS] = +static const uint8_t g_chanlist1[3] = { - 12, + 1, + 5, + 12 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC3_IN1, + GPIO_ADC3_IN5, + GPIO_ADC3_IN12 +}; + +#elif DEV1_PORT == 4 + +#define DEV1_NCHANNELS ADC4_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[1] = +{ + 3 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[1] = +{ + GPIO_ADC4_IN3 +}; + +#endif + +#ifdef DEV2_PORT + +/* DEV 2 */ + +#if DEV2_PORT == 1 + +#define DEV2_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist2[4] = +{ + 1, + 2, + 6, + 7 }; /* Configurations of pins used by each ADC channel */ -static const uint32_t g_pinlist[ADC_NCHANNELS] = +static const uint32_t g_pinlist2[4] = { - GPIO_ADC3_IN12, + GPIO_ADC1_IN1, + GPIO_ADC1_IN2, + GPIO_ADC1_IN6, + GPIO_ADC1_IN7 }; -#elif defined(CONFIG_STM32_ADC4) +#elif DEV2_PORT == 2 + +#define DEV2_NCHANNELS ADC2_NCHANNELS /* Identifying number of each ADC channel */ -static const uint8_t g_chanlist[ADC_NCHANNELS] = +static const uint8_t g_chanlist2[3] = { + 1, 3, + 4 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC2_IN1, + GPIO_ADC2_IN3, + GPIO_ADC2_IN4 +}; + +#elif DEV2_PORT == 3 + +#define DEV2_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[3] = +{ + 1, + 5, + 12 }; /* Configurations of pins used by each ADC channel */ -static const uint32_t g_pinlist[ADC_NCHANNELS] = +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC3_IN1, + GPIO_ADC3_IN5, + GPIO_ADC3_IN12 +}; + +#elif DEV2_PORT == 4 + +#define DEV2_NCHANNELS ADC4_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[1] = { - GPIO_ADC4_IN3, + 3 }; +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[1] = +{ + GPIO_ADC4_IN3 +}; + +#endif #endif /**************************************************************************** @@ -208,21 +336,22 @@ int board_adc_setup(void) /* Check if we have already initialized */ - if (!initialized) - { + if (!initialized) { + + /* DEV1 */ /* Configure the pins as analog inputs for the selected channels */ - for (i = 0; i < ADC_NCHANNELS; i++) + for (i = 0; i < DEV1_NCHANNELS; i++) { - stm32_configgpio(g_pinlist[i]); + stm32_configgpio(g_pinlist1[i]); } /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32_adcinitialize(ADC_PORT, g_chanlist, ADC_NCHANNELS); + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); if (adc == NULL) { - aerr("ERROR: Failed to get ADC interface\n"); + aerr("ERROR: Failed to get ADC interface 1\n"); return -ENODEV; } @@ -231,10 +360,39 @@ int board_adc_setup(void) ret = adc_register("/dev/adc0", adc); if (ret < 0) { - aerr("ERROR: adc_register failed: %d\n", ret); + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); return ret; } +#ifdef DEV2_PORT + + /* DEV2 */ + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 2\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); + return ret; + } +#endif + /* Now we are initialized */ initialized = true; diff --git a/configs/nucleo-f303re/src/stm32_appinitialize.c b/configs/nucleo-f303re/src/stm32_appinitialize.c index d79c7d5041..3ce7e293bd 100644 --- a/configs/nucleo-f303re/src/stm32_appinitialize.c +++ b/configs/nucleo-f303re/src/stm32_appinitialize.c @@ -42,8 +42,12 @@ #include #include +#include #include +#include + +#include "nucleo-f303re.h" /**************************************************************************** * Pre-processor Definitions @@ -80,5 +84,31 @@ int board_app_initialize(uintptr_t arg) { + int ret; + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + + /* Contrairement à l'ADC, il n'y a pas de BOARDIOC_DAC_SETUP spécifique. Il + * faut le faire ici + */ + +#if defined(CONFIG_DAC) + ret = board_dac_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_dac_setup() failed: %d\n", ret); + return ret; + } +#endif + return OK; } -- GitLab From fef7b414c58413b5dfc027d4849db3506b359749 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 25 Oct 2016 15:19:29 -0600 Subject: [PATCH 211/734] Add logic to attach peripheral interrupt sources to CPU interrupts --- arch/xtensa/src/esp32/esp32_cpuint.c | 128 ++++++++++++++++++++++++- arch/xtensa/src/esp32/esp32_cpuint.h | 6 +- arch/xtensa/src/esp32/esp32_cpustart.c | 9 +- arch/xtensa/src/esp32/esp32_irq.c | 13 ++- arch/xtensa/src/esp32/esp32_timerisr.c | 4 + 5 files changed, 145 insertions(+), 15 deletions(-) diff --git a/arch/xtensa/src/esp32/esp32_cpuint.c b/arch/xtensa/src/esp32/esp32_cpuint.c index 0bdebfa76b..9f09a3b72c 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.c +++ b/arch/xtensa/src/esp32/esp32_cpuint.c @@ -58,6 +58,91 @@ #define ESP32_LEVEL_SET ESP32_INTSET(ESP32_CPUINT_NLEVELPERIPHS) #define ESP32_EDGE_SET ESP32_INTSET(ESP32_CPUINT_NEDGEPERIPHS) +/* Mapping Peripheral IDs to map register addresses + * + * PERIPHERAL ID DPORT REGISTER OFFSET + * MNEMONIC VAL PRO CPU APP CPU + * -------------------------- --- ------- ------- + * ESP32_PERIPH_MAC 0 0x104 0x218 + * ESP32_PERIPH_MAC_NMI 1 0x108 0x21c + * ESP32_PERIPH_BB 2 0x10c 0x220 + * ESP32_PERIPH_BB_MAC 3 0x110 0x224 + * ESP32_PERIPH_BT_BB 4 0x114 0x228 + * ESP32_PERIPH_BT_BB_NMI 5 0x118 0x22c + * ESP32_PERIPH_RWBT_IRQ 6 0x11c 0x230 + * ESP32_PERIPH_RWBLE_IRQ 7 0x120 0x234 + * ESP32_PERIPH_RWBT_NMI 8 0x124 0x238 + * ESP32_PERIPH_RWBLE_NMI 9 0x128 0x23c + * ESP32_PERIPH_SLC0 10 0x12c 0x240 + * ESP32_PERIPH_SLC1 11 0x130 0x244 + * ESP32_PERIPH_UHCI0 12 0x134 0x248 + * ESP32_PERIPH_UHCI1 13 0x138 0x24c + * ESP32_PERIPH_TG_T0_LEVEL 14 0x13c 0x250 + * ESP32_PERIPH_TG_T1_LEVEL 15 0x140 0x254 + * ESP32_PERIPH_TG_WDT_LEVEL 16 0x144 0x258 + * ESP32_PERIPH_TG_LACT_LEVEL 17 0x148 0x25c + * ESP32_PERIPH_TG1_T0_LEVEL 18 0x14c 0x260 + * ESP32_PERIPH_TG1_T1_LEVEL 19 0x150 0x264 + * ESP32_PERIPH_TG1_WDT_LEVEL 20 0x154 0x268 + * ESP32_PERIPH_G1_LACT_LEVEL 21 0x158 0x26c + * ESP32_PERIPH_CPU_GPIO 22 0x15c 0x270 + * ESP32_PERIPH_CPU_NMI 23 0x160 0x274 + * ESP32_PERIPH_CPU_CPU0 24 0x164 0x278 + * ESP32_PERIPH_CPU_CPU1 25 0x168 0x27c + * ESP32_PERIPH_CPU_CPU2 26 0x16c 0x280 + * ESP32_PERIPH_CPU_CPU3 27 0x170 0x284 + * ESP32_PERIPH_SPI0 28 0x174 0x288 + * ESP32_PERIPH_SPI1 29 0x178 0x28c + * ESP32_PERIPH_SPI2 30 0x17c 0x290 + * ESP32_PERIPH_SPI3 31 0x180 0x294 + * ESP32_PERIPH_I2S0 32 0x184 0x298 + * ESP32_PERIPH_I2S1 33 0x188 0x29c + * ESP32_PERIPH_UART 34 0x18c 0x2a0 + * ESP32_PERIPH_UART1 35 0x190 0x2a4 + * ESP32_PERIPH_UART2 36 0x194 0x2a8 + * ESP32_PERIPH_SDIO_HOST 37 0x198 0x2ac + * ESP32_PERIPH_EMAC 38 0x19c 0x2b0 + * ESP32_PERIPH_PWM0 39 0x1a0 0x2b4 + * ESP32_PERIPH_PWM1 40 0x1a4 0x2b8 + * ESP32_PERIPH_PWM2 41 0x1a8 0x2bc + * ESP32_PERIPH_PWM3 42 0x1ac 0x2c0 + * ESP32_PERIPH_LEDC 43 0x1b0 0x2c4 + * ESP32_PERIPH_EFUSE 44 0x1b4 0x2c8 + * ESP32_PERIPH_CAN 45 0x1b8 0x2cc + * ESP32_PERIPH_RTC_CORE 46 0x1bc 0x2d0 + * ESP32_PERIPH_RMT 47 0x1c0 0x2d4 + * ESP32_PERIPH_PCNT 48 0x1c4 0x2d8 + * ESP32_PERIPH_I2C_EXT0 49 0x1c8 0x2dc + * ESP32_PERIPH_I2C_EXT1 50 0x1cc 0x2e0 + * ESP32_PERIPH_RSA 51 0x1d0 0x2e4 + * ESP32_PERIPH_SPI1_DMA 52 0x1d4 0x2e8 + * ESP32_PERIPH_SPI2_DMA 53 0x1d8 0x2ec + * ESP32_PERIPH_SPI3_DMA 54 0x1dc 0x2f0 + * ESP32_PERIPH_WDG 55 0x1e0 0x2f4 + * ESP32_PERIPH_TIMER1 56 0x1e4 0x2f8 + * ESP32_PERIPH_TIMER2 57 0x1e8 0x2fc + * ESP32_PERIPH_TG_T0_EDGE 58 0x1ec 0x300 + * ESP32_PERIPH_TG_T1_EDGE 59 0x1f0 0x304 + * ESP32_PERIPH_TG_WDT_EDGE 60 0x1F4 0x308 + * ESP32_PERIPH_TG_LACT_EDGE 61 0x1F8 0x30c + * ESP32_PERIPH_TG1_T0_EDGE 62 0x1fc 0x310 + * ESP32_PERIPH_TG1_T1_EDGE 63 0x200 0x314 + * ESP32_PERIPH_TG1_WDT_EDGE 64 0x204 0x318 + * ESP32_PERIPH_TG1_LACT_EDGE 65 0x208 0x31c + * ESP32_PERIPH_MMU_IA 66 0x20c 0x320 + * ESP32_PERIPH_MPU_IA 67 0x210 0x324 + * ESP32_PERIPH_CACHE_IA 68 0x214 0x328 + */ + +#define DPORT_PRO_MAP_REGADDR(n) (DR_REG_DPORT_BASE + 0x104 + ((n) << 2)) +#define DPORT_APP_MAP_REGADDR(n) (DR_REG_DPORT_BASE + 0x218 + ((n) << 2)) + +/* CPU interrupts can be detached from any peripheral source by setting the + * map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29). + */ + +#define NO_CPUINT ESP32_CPUINT_TIMER0 + /**************************************************************************** * Private Data ****************************************************************************/ @@ -270,7 +355,7 @@ int esp32_alloc_edgeint(void) } leave_critical_section(flags); - return ret; + return ret; } /**************************************************************************** @@ -321,7 +406,24 @@ void esp32_free_edgeint(int cpuint) void esp32_attach_peripheral(int cpu, int periphid, int cpuint) { -# warning Missing logic + uintptr_t regaddr; + + DEBUGASSERT(periphid >= 0 && periphid < NR_PERIPHERALS); + DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32_CPUINT_MAX); +#ifdef CONFIG_SMP + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); + + if (cpu != 0) + { + regaddr = DPORT_APP_MAP_REGADDR(periphid); + } + else +#endif + { + regaddr = DPORT_PRO_MAP_REGADDR(periphid); + } + + putreg(cpuint, regaddr); } /**************************************************************************** @@ -332,14 +434,30 @@ void esp32_attach_peripheral(int cpu, int periphid, int cpuint) * * Input Parameters: * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * cpuint - The CPU interrupt to receive the peripheral interrupt + * periphid - The peripheral number from ira.h to be assigned. * * Returned Value: * None * ****************************************************************************/ -void esp32_detach_peripheral(int cpu, int cpuint) +void esp32_detach_peripheral(int cpu, int periphid) { -# warning Missing logic + uintptr_t regaddr; + + DEBUGASSERT(periphid >= 0 && periphid < NR_PERIPHERALS); +#ifdef CONFIG_SMP + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); + + if (cpu != 0) + { + regaddr = DPORT_APP_MAP_REGADDR(periphid); + } + else +#endif + { + regaddr = DPORT_PRO_MAP_REGADDR(periphid); + } + + putreg(NO_CPUINT, regaddr); } diff --git a/arch/xtensa/src/esp32/esp32_cpuint.h b/arch/xtensa/src/esp32/esp32_cpuint.h index f3bbbaf4a4..07af5ea8f3 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.h +++ b/arch/xtensa/src/esp32/esp32_cpuint.h @@ -124,7 +124,7 @@ void esp32_free_edgeint(int cpuint); * * Input Parameters: * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * periphid - The peripheral number from ira.h to be assigned. + * periphid - The peripheral number from ira.h to be attached. * cpuint - The CPU interrupt to receive the peripheral interrupt * * Returned Value: @@ -142,13 +142,13 @@ void esp32_attach_peripheral(int cpu, int periphid, int cpuint); * * Input Parameters: * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * cpuint - The CPU interrupt to receive the peripheral interrupt + * periphid - The peripheral number from ira.h to be detached. * * Returned Value: * None * ****************************************************************************/ -void esp32_detach_peripheral(int cpu, int cpuint); +void esp32_detach_peripheral(int cpu, int periphid); #endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_CPUINT_H */ diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c index 1f4a6d4c01..ec5d0c7d06 100644 --- a/arch/xtensa/src/esp32/esp32_cpustart.c +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -120,6 +120,7 @@ static inline void xtensa_disable_all(void) int xtensa_start_handler(int irq, FAR void *context) { FAR struct tcb_s *tcb; + int i; sinfo("CPU%d Started\n", up_cpu_index()); @@ -145,8 +146,12 @@ int xtensa_start_handler(int irq, FAR void *context) xtensa_disable_all(); - /* Disable peripheral sources from all PRO CPU interrupt */ -#warning Missing logic + /* Detach all peripheral sources APP CPU interrupts */ + + for (i = 0; i < NR_PERIPHERALS) + { + esp32_detach_peripheral(1, i);; + } /* Dump registers so that we can see what is going to happen on return */ diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c index 6394beb8e1..010f05eb99 100644 --- a/arch/xtensa/src/esp32/esp32_irq.c +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -120,12 +120,18 @@ static inline void xtensa_disable_all(void) void xtensa_irq_initialize(void) { + int i; + /* Disable all PRO CPU interrupts */ xtensa_disable_all(); - /* Disable peripheral sources from all PRO CPU interrupt */ -#warning Missing logic + /* Detach all peripheral sources PRO CPU interrupts */ + + for (i = 0; i < NR_PERIPHERALS) + { + esp32_detach_peripheral(0, i);; + } #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 /* Colorize the interrupt stack for debug purposes */ @@ -133,9 +139,6 @@ void xtensa_irq_initialize(void) #warning Missing logic #endif - /* Set all interrupts (and exceptions) to the default priority */ -#warning Missing logic - /* Attach all processor exceptions */ #warning Missing logic diff --git a/arch/xtensa/src/esp32/esp32_timerisr.c b/arch/xtensa/src/esp32/esp32_timerisr.c index 639934d535..3d031dc776 100644 --- a/arch/xtensa/src/esp32/esp32_timerisr.c +++ b/arch/xtensa/src/esp32/esp32_timerisr.c @@ -191,6 +191,10 @@ void xtensa_timer_initialize(void) count = xtensa_getcount(); xtensa_setcompare(count + divisor); + /* NOTE: Timer 0 is an internal interrupt source so we do not need to + * attach any peripheral ID to the dedicated CPU interrupt. + */ + /* Attach the timer interrupt vector */ (void)irq_attach(XTENSA_IRQ_TIMER0, (xcpt_t)esp32_timerisr); -- GitLab From b8462d3e04e376cb2ef96b356ee007144bfd08d1 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 25 Oct 2016 16:27:58 -0600 Subject: [PATCH 212/734] ESP32: Need to take priority into account when allocating CPU interrupts --- arch/xtensa/include/esp32/irq.h | 38 +++++++++++---- arch/xtensa/src/esp32/esp32_cpuint.c | 71 +++++++++++++++++++++++----- arch/xtensa/src/esp32/esp32_cpuint.h | 14 +++--- 3 files changed, 96 insertions(+), 27 deletions(-) diff --git a/arch/xtensa/include/esp32/irq.h b/arch/xtensa/include/esp32/irq.h index 4221f30b20..46b20fb552 100644 --- a/arch/xtensa/include/esp32/irq.h +++ b/arch/xtensa/include/esp32/irq.h @@ -297,11 +297,17 @@ * 26 can be mapped to peripheral interrupts: * * Level triggered peripherals (21 total): - * 0-5, 8-9, 12-13, 17-21, 23-27, 31 + * 0-5, 8-9, 12-13, 17-18 - Priority 1 + * 19-21 - Priority 2 + * 23, 27 - Priority 3 + * 24-25 - Priority 4 + * 26, 31 - Priority 5 * Edge triggered peripherals (4 total): - * 10, 22, 28, 30 + * 10 - Priority 1 + * 22 - Priority 3 + * 28, 30 - Priority 4 * NMI (1 total): - * 14 + * 14 - NMI * * CPU peripheral interrupts can be a assigned to a CPU interrupt using the * PRO_*_MAP_REG or APP_*_MAP_REG. There are a pair of these registers for @@ -310,11 +316,12 @@ * * The remaining, five, internal CPU interrupts are: * - * 6 Timer0 - * 7 Software - * 15 Timer1 - * 16 Timer2 - * 29 Software + * 6 Timer0 - Priority 1 + * 7 Software - Priority 1 + * 11 Profiling - Priority 3 + * 15 Timer1 - Priority 3 + * 16 Timer2 - Priority 5 + * 29 Software - Priority 3 * * A peripheral interrupt can be disabled */ @@ -359,6 +366,21 @@ #define EPS32_CPUINT_PERIPHSET 0xdffe7f3f #define EPS32_CPUINT_INTERNALSET 0x200180c0 +/* Priority 1: 0-10, 12-13, 17-18 (15) + * Priority 2: 19-21 (3) + * Priority 3: 11, 15, 22-23, 27, 29 (6) + * Priority 4: 24-25, 28, 30 (4) + * Priority 5: 16, 26, 31 (3) + * Priority NMI: 14 (1) + */ + +#define ESP32_INTPRI1_MASK 0x000637ff +#define ESP32_INTPRI2_MASK 0x00380000 +#define ESP32_INTPRI3_MASK 0x28c08800 +#define ESP32_INTPRI4_MASK 0x53000000 +#define ESP32_INTPRI5_MASK 0x84010000 +#define ESP32_INTNMI_MASK 0x00004000 + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/arch/xtensa/src/esp32/esp32_cpuint.c b/arch/xtensa/src/esp32/esp32_cpuint.c index 9f09a3b72c..6a6aec7fe5 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.c +++ b/arch/xtensa/src/esp32/esp32_cpuint.c @@ -143,6 +143,12 @@ #define NO_CPUINT ESP32_CPUINT_TIMER0 +/* Priority range is 1-5 */ + +#define ESP32_MIN_PRIORITY 1 +#define ESP32_MAX_PRIORITY 5 +#define ESP32_PRIO_INDEX(p) ((p) - ESP32_MIN_PRIORITY) + /**************************************************************************** * Private Data ****************************************************************************/ @@ -166,6 +172,17 @@ static uint32_t g_intenable[1]; static uint32_t g_level_ints = ESP32_LEVEL_SET; static uint32_t g_edge_ints = ESP32_EDGE_SET; +/* Bitsets for each interrupt priority 1-5 */ + +static uint32_t g_priority[5] = +{ + ESP32_INTPRI1_MASK, + ESP32_INTPRI2_MASK, + ESP32_INTPRI3_MASK, + ESP32_INTPRI4_MASK, + ESP32_INTPRI5_MASK +}; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -229,7 +246,7 @@ void up_enable_irq(int cpuint) * Allocate a level CPU interrupt * * Input Parameters: - * None + * priority - Priority of the CPU interrupt (1-5) * * Returned Value: * On success, the allocated level-sensitive, CPU interrupt numbr is @@ -239,28 +256,39 @@ void up_enable_irq(int cpuint) * ****************************************************************************/ -int esp32_alloc_levelint(void) +int esp32_alloc_levelint(int priority) { irqstate_t flags; uint32_t mask; + uint32_t intset; int cpuint; int ret = -ENOMEM; + DEBUGASSERT(priority >= ESP32_MIN_PRIORITY && priority <= ESP32_MAX_PRIORITY) + /* Check if there are any level CPU interrupts available */ flags = enter_critical_section(); - if ((g_level_ints & ESP32_LEVEL_SET) != 0) + + intset = g_level_ints & g_priority[ESP32_PRIO_INDEX(priority)] & ESP32_LEVEL_SET; + if (intset != 0) { - /* Search for an unallocated CPU interrupt number in g_level_ints. */ + /* Skip over initial zeroes as quickly in groups of 8 bits. */ + + for (cpuint = 0, mask = 0xff; + cpuint <= ESP32_CPUINT_MAX && (intset & mask) == 0; + cpuint += 8, mask <<= 8); + + /* Search for an unallocated CPU interrupt number in the remaining intset. */ - for (cpuint = 0; cpuint < ESP32_CPUINT_NLEVELPERIPHS; cpuint++) + for (; cpuint <= ESP32_CPUINT_MAX && intset != 0; cpuint++) { /* If the bit corresponding to the CPU interrupt is '1', then * that CPU interrupt is available. */ mask = (1ul << cpuint); - if ((g_level_ints & mask) != 0) + if ((intset & mask) != 0) { /* Got it! */ @@ -268,6 +296,10 @@ int esp32_alloc_levelint(void) ret = cpuint; break; } + + /* Clear the bit in intset so that we may exit the loop sooner */ + + intset &= ~mask; } } @@ -312,7 +344,7 @@ void esp32_free_levelint(int cpuint) * Allocate an edge CPU interrupt * * Input Parameters: - * None + * priority - Priority of the CPU interrupt (1-5) * * Returned Value: * On success, the allocated edge-sensitive, CPU interrupt numbr is @@ -322,28 +354,39 @@ void esp32_free_levelint(int cpuint) * ****************************************************************************/ -int esp32_alloc_edgeint(void) +int esp32_alloc_edgeint(int priority) { irqstate_t flags; uint32_t mask; + uint32_t intset; int cpuint; int ret = -ENOMEM; + DEBUGASSERT(priority >= ESP32_MIN_PRIORITY && priority <= ESP32_MAX_PRIORITY) + /* Check if there are any level CPU interrupts available */ flags = enter_critical_section(); - if ((g_edge_ints & ESP32_EDGE_SET) != 0) + + intset = g_edge_ints & g_priority[ESP32_PRIO_INDEX(priority)] & ESP32_EDGE_SET; + if (intset != 0) { - /* Search for an unallocated CPU interrupt number in g_edge_ints. */ + /* Skip over initial zeroes as quickly in groups of 8 bits. */ - for (cpuint = 0; cpuint < ESP32_CPUINT_NEDGEPERIPHS; cpuint++) + for (cpuint = 0, mask = 0xff; + cpuint <= ESP32_CPUINT_MAX && (intset & mask) == 0; + cpuint += 8, mask <<= 8); + + /* Search for an unallocated CPU interrupt number in the remaining intset. */ + + for (; cpuint <= ESP32_CPUINT_MAX && intset != 0; cpuint++) { /* If the bit corresponding to the CPU interrupt is '1', then * that CPU interrupt is available. */ mask = (1ul << cpuint); - if ((g_edge_ints & mask) != 0) + if ((intset & mask) != 0) { /* Got it! */ @@ -351,6 +394,10 @@ int esp32_alloc_edgeint(void) ret = cpuint; break; } + + /* Clear the bit in intset so that we may exit the loop sooner */ + + intset &= ~mask; } } diff --git a/arch/xtensa/src/esp32/esp32_cpuint.h b/arch/xtensa/src/esp32/esp32_cpuint.h index 07af5ea8f3..746248456d 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.h +++ b/arch/xtensa/src/esp32/esp32_cpuint.h @@ -53,7 +53,7 @@ * Allocate a level CPU interrupt * * Input Parameters: - * None + * priority - Priority of the CPU interrupt (1-5) * * Returned Value: * On success, the allocated level-sensitive, CPU interrupt numbr is @@ -63,7 +63,7 @@ * ****************************************************************************/ -int esp32_alloc_levelint(void); +int esp32_alloc_levelint(int priority); /**************************************************************************** * Name: esp32_free_levelint @@ -72,7 +72,7 @@ int esp32_alloc_levelint(void); * Free a previoulsy allocated level CPU interrupt * * Input Parameters: - * The CPU interrupt number to be freed + * cpuint - The CPU interrupt number to be freed * * Returned Value: * None @@ -88,7 +88,7 @@ void esp32_free_levelint(int cpuint); * Allocate an edge CPU interrupt * * Input Parameters: - * None + * priority - Priority of the CPU interrupt (1-5) * * Returned Value: * On success, the allocated edge-sensitive, CPU interrupt numbr is @@ -98,7 +98,7 @@ void esp32_free_levelint(int cpuint); * ****************************************************************************/ -int esp32_alloc_edgeint(void); +int esp32_alloc_edgeint(int priority); /**************************************************************************** * Name: esp32_free_edgeint @@ -107,14 +107,14 @@ int esp32_alloc_edgeint(void); * Free a previoulsy allocated edge CPU interrupt * * Input Parameters: - * The CPU interrupt number to be freed + * cpuint - The CPU interrupt number to be freed * * Returned Value: * None * ****************************************************************************/ -void esp32_free_edgeint(int cpuint); +void esp32_free_edgeint(int cpuint, int priority); /**************************************************************************** * Name: esp32_attach_peripheral -- GitLab From 68dae715b00bf611a158f5e18304011ed2ae6282 Mon Sep 17 00:00:00 2001 From: Sebastien Lorquet Date: Wed, 26 Oct 2016 13:21:57 +0200 Subject: [PATCH 213/734] CHxN channels are always outputs --- arch/arm/src/stm32l4/Kconfig | 10 +++++ .../arm/src/stm32l4/chip/stm32l4x6xx_pinmap.h | 40 +++++++++---------- 2 files changed, 30 insertions(+), 20 deletions(-) diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index 1192f839f8..cec02a9cbb 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -695,6 +695,7 @@ config STM32L4_TIM1_PWM bool "TIM1 PWM" default n depends on STM32L4_TIM1 + select PWM select ARCH_HAVE_PWM_PULSECOUNT ---help--- Reserve timer 1 for use by PWM @@ -855,6 +856,7 @@ config STM32L4_TIM2_PWM bool "TIM2 PWM" default n depends on STM32L4_TIM2 + select PWM select ARCH_HAVE_PWM_PULSECOUNT ---help--- Reserve timer 2 for use by PWM @@ -994,6 +996,7 @@ config STM32L4_TIM3_PWM bool "TIM3 PWM" default n depends on STM32L4_TIM3 + select PWM select ARCH_HAVE_PWM_PULSECOUNT ---help--- Reserve timer 3 for use by PWM @@ -1133,6 +1136,7 @@ config STM32L4_TIM4_PWM bool "TIM4 PWM" default n depends on STM32L4_TIM4 + select PWM select ARCH_HAVE_PWM_PULSECOUNT ---help--- Reserve timer 4 for use by PWM @@ -1272,6 +1276,8 @@ config STM32L4_TIM5_PWM bool "TIM5 PWM" default n depends on STM32L4_TIM5 + select PWM + select PWM select ARCH_HAVE_PWM_PULSECOUNT ---help--- Reserve timer 5 for use by PWM @@ -1411,6 +1417,7 @@ config STM32L4_TIM8_PWM bool "TIM8 PWM" default n depends on STM32L4_TIM8 + select PWM select ARCH_HAVE_PWM_PULSECOUNT ---help--- Reserve timer 8 for use by PWM @@ -1571,6 +1578,7 @@ config STM32L4_TIM15_PWM bool "TIM15 PWM" default n depends on STM32L4_TIM15 + select PWM ---help--- Reserve timer 15 for use by PWM @@ -1663,6 +1671,7 @@ config STM32L4_TIM16_PWM bool "TIM16 PWM" default n depends on STM32L4_TIM16 + select PWM ---help--- Reserve timer 16 for use by PWM @@ -1732,6 +1741,7 @@ config STM32L4_TIM17_PWM bool "TIM17 PWM" default n depends on STM32L4_TIM17 + select PWM ---help--- Reserve timer 17 for use by PWM diff --git a/arch/arm/src/stm32l4/chip/stm32l4x6xx_pinmap.h b/arch/arm/src/stm32l4/chip/stm32l4x6xx_pinmap.h index 00fa2fa37a..2915c0c439 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4x6xx_pinmap.h +++ b/arch/arm/src/stm32l4/chip/stm32l4x6xx_pinmap.h @@ -516,15 +516,15 @@ #define GPIO_TIM1_CH4IN_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN14) #define GPIO_TIM1_CH4OUT_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) #define GPIO_TIM1_CH4OUT_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN14) -#define GPIO_TIM1_CH1N_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN7) -#define GPIO_TIM1_CH1N_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN13) -#define GPIO_TIM1_CH1N_3 (GPIO_ALT|GPIO_AF1 |GPIO_PORTE|GPIO_PIN8) -#define GPIO_TIM1_CH2N_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN0) -#define GPIO_TIM1_CH2N_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN14) -#define GPIO_TIM1_CH2N_3 (GPIO_ALT|GPIO_AF1 |GPIO_PORTE|GPIO_PIN10) -#define GPIO_TIM1_CH3N_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN1) -#define GPIO_TIM1_CH3N_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN15) -#define GPIO_TIM1_CH3N_3 (GPIO_ALT|GPIO_AF1 |GPIO_PORTE|GPIO_PIN12) +#define GPIO_TIM1_CH1N_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM1_CH1N_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13) +#define GPIO_TIM1_CH1N_3 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN8) +#define GPIO_TIM1_CH2N_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM1_CH2N_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM1_CH2N_3 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN10) +#define GPIO_TIM1_CH3N_1 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM1_CH3N_2 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM1_CH3N_3 (GPIO_ALT|GPIO_AF1 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN12) #define GPIO_TIM1_BKIN_1 (GPIO_ALT|GPIO_AF1 |GPIO_PORTA|GPIO_PIN6) #define GPIO_TIM1_BKIN_2 (GPIO_ALT|GPIO_AF1 |GPIO_PORTB|GPIO_PIN12) #define GPIO_TIM1_BKIN_3 (GPIO_ALT|GPIO_AF1 |GPIO_PORTE|GPIO_PIN15) @@ -635,12 +635,12 @@ #define GPIO_TIM8_CH3OUT (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8) #define GPIO_TIM8_CH4IN (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9) #define GPIO_TIM8_CH4OUT (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) -#define GPIO_TIM8_CH1N_1 (GPIO_ALT|GPIO_AF3 |GPIO_PORTA|GPIO_PIN5) -#define GPIO_TIM8_CH1N_2 (GPIO_ALT|GPIO_AF3 |GPIO_PORTA|GPIO_PIN7) -#define GPIO_TIM8_CH2N_1 (GPIO_ALT|GPIO_AF3 |GPIO_PORTB|GPIO_PIN0) -#define GPIO_TIM8_CH2N_2 (GPIO_ALT|GPIO_AF3 |GPIO_PORTB|GPIO_PIN14) -#define GPIO_TIM8_CH3N_1 (GPIO_ALT|GPIO_AF3 |GPIO_PORTB|GPIO_PIN1) -#define GPIO_TIM8_CH3N_2 (GPIO_ALT|GPIO_AF3 |GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM8_CH1N_1 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5) +#define GPIO_TIM8_CH1N_2 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM8_CH2N_1 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM8_CH2N_2 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM8_CH3N_1 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM8_CH3N_2 (GPIO_ALT|GPIO_AF3 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) #define GPIO_TIM8_BKIN_1 (GPIO_ALT|GPIO_AF3 |GPIO_PORTA|GPIO_PIN6) #define GPIO_TIM8_BKIN_2 (GPIO_ALT|GPIO_AF3 |GPIO_PORTB|GPIO_PIN7) #define GPIO_TIM8_BKIN_COMP1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN7) @@ -667,9 +667,9 @@ #define GPIO_TIM15_CH2OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) #define GPIO_TIM15_CH2OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN10) #define GPIO_TIM15_CH2OUT_4 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11) -#define GPIO_TIM15_CH1N_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN1) -#define GPIO_TIM15_CH1N_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN13) -#define GPIO_TIM15_CH1N_3 (GPIO_ALT|GPIO_AF14|GPIO_PORTG|GPIO_PIN9) +#define GPIO_TIM15_CH1N_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM15_CH1N_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13) +#define GPIO_TIM15_CH1N_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN9) #define GPIO_TIM15_BKIN_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN9) #define GPIO_TIM15_BKIN_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN12) @@ -679,7 +679,7 @@ #define GPIO_TIM16_CH1OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6) #define GPIO_TIM16_CH1OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) #define GPIO_TIM16_CH1OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0) -#define GPIO_TIM16_CH1N (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN6) +#define GPIO_TIM16_CH1N (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6) #define GPIO_TIM16_BKIN (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN5) #define GPIO_TIM17_CH1IN_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN7) @@ -688,7 +688,7 @@ #define GPIO_TIM17_CH1OUT_1 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7) #define GPIO_TIM17_CH1OUT_2 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) #define GPIO_TIM17_CH1OUT_3 (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1) -#define GPIO_TIM17_CH1N (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM17_CH1N (GPIO_ALT|GPIO_AF14|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7) #define GPIO_TIM17_BKIN_1 (GPIO_ALT|GPIO_AF14|GPIO_PORTA|GPIO_PIN10) #define GPIO_TIM17_BKIN_2 (GPIO_ALT|GPIO_AF14|GPIO_PORTB|GPIO_PIN4) -- GitLab From 2c09279343ca75492cc34726ab51e3255b695977 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 26 Oct 2016 06:26:30 -0600 Subject: [PATCH 214/734] ESP32: Add beginning of GPIO register definition file --- arch/xtensa/src/esp32/chip/esp32_gpio.h | 10589 ++++++++++++++++++++++ 1 file changed, 10589 insertions(+) create mode 100644 arch/xtensa/src/esp32/chip/esp32_gpio.h diff --git a/arch/xtensa/src/esp32/chip/esp32_gpio.h b/arch/xtensa/src/esp32/chip/esp32_gpio.h new file mode 100644 index 0000000000..454e378c49 --- /dev/null +++ b/arch/xtensa/src/esp32/chip/esp32_gpio.h @@ -0,0 +1,10589 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/chip/esp32_uart.h + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Espressif Systems: + * + * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + *************************************************************************** */ + +#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_GPIO_H +#define __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_GPIO_H + +/**************************************************************************** + * Included Files + *************************************************************************** */ + +#include "chip/esp32_soc.h" + +/**************************************************************************** + * Pre-preprocessor Definitions + *************************************************************************** */ + +#include "soc.h" +#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0000) + +/* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: x ; */ +/* Description: NA */ + +#define GPIO_BT_SEL 0xFFFFFFFF +#define GPIO_BT_SEL_M ((GPIO_BT_SEL_V)<<(GPIO_BT_SEL_S)) +#define GPIO_BT_SEL_V 0xFFFFFFFF +#define GPIO_BT_SEL_S 0 + +#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x0004) + +/* GPIO_OUT_DATA : R/W ;bitpos:[31:0] ;default: x ; */ +/* Description: GPIO0~31 output value */ + +#define GPIO_OUT_DATA 0xFFFFFFFF +#define GPIO_OUT_DATA_M ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S)) +#define GPIO_OUT_DATA_V 0xFFFFFFFF +#define GPIO_OUT_DATA_S 0 + +#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x0008) + +/* GPIO_OUT_DATA_W1TS : R/W ;bitpos:[31:0] ;default: x ; */ +/* Description: GPIO0~31 output value write 1 to set */ + +#define GPIO_OUT_DATA_W1TS 0xFFFFFFFF +#define GPIO_OUT_DATA_W1TS_M ((GPIO_OUT_DATA_W1TS_V)<<(GPIO_OUT_DATA_W1TS_S)) +#define GPIO_OUT_DATA_W1TS_V 0xFFFFFFFF +#define GPIO_OUT_DATA_W1TS_S 0 + +#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0x000c) + +/* GPIO_OUT_DATA_W1TC : R/W ;bitpos:[31:0] ;default: x ; */ +/* Description: GPIO0~31 output value write 1 to clear */ + +#define GPIO_OUT_DATA_W1TC 0xFFFFFFFF +#define GPIO_OUT_DATA_W1TC_M ((GPIO_OUT_DATA_W1TC_V)<<(GPIO_OUT_DATA_W1TC_S)) +#define GPIO_OUT_DATA_W1TC_V 0xFFFFFFFF +#define GPIO_OUT_DATA_W1TC_S 0 + +#define GPIO_OUT1_REG (DR_REG_GPIO_BASE + 0x0010) + +/* GPIO_OUT1_DATA : R/W ;bitpos:[7:0] ;default: x ; */ +/* Description: GPIO32~39 output value */ + +#define GPIO_OUT1_DATA 0x000000FF +#define GPIO_OUT1_DATA_M ((GPIO_OUT1_DATA_V)<<(GPIO_OUT1_DATA_S)) +#define GPIO_OUT1_DATA_V 0xFF +#define GPIO_OUT1_DATA_S 0 + +#define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x0014) + +/* GPIO_OUT1_DATA_W1TS : R/W ;bitpos:[7:0] ;default: x ; */ +/* Description: GPIO32~39 output value write 1 to set */ + +#define GPIO_OUT1_DATA_W1TS 0x000000FF +#define GPIO_OUT1_DATA_W1TS_M ((GPIO_OUT1_DATA_W1TS_V)<<(GPIO_OUT1_DATA_W1TS_S)) +#define GPIO_OUT1_DATA_W1TS_V 0xFF +#define GPIO_OUT1_DATA_W1TS_S 0 + +#define GPIO_OUT1_W1TC_REG (DR_REG_GPIO_BASE + 0x0018) + +/* GPIO_OUT1_DATA_W1TC : R/W ;bitpos:[7:0] ;default: x ; */ +/* Description: GPIO32~39 output value write 1 to clear */ + +#define GPIO_OUT1_DATA_W1TC 0x000000FF +#define GPIO_OUT1_DATA_W1TC_M ((GPIO_OUT1_DATA_W1TC_V)<<(GPIO_OUT1_DATA_W1TC_S)) +#define GPIO_OUT1_DATA_W1TC_V 0xFF +#define GPIO_OUT1_DATA_W1TC_S 0 + +#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x001c) + +/* GPIO_SDIO_SEL : R/W ;bitpos:[7:0] ;default: x ; */ +/* Description: SDIO PADS on/off control from outside */ + +#define GPIO_SDIO_SEL 0x000000FF +#define GPIO_SDIO_SEL_M ((GPIO_SDIO_SEL_V)<<(GPIO_SDIO_SEL_S)) +#define GPIO_SDIO_SEL_V 0xFF +#define GPIO_SDIO_SEL_S 0 + +#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x0020) + +/* GPIO_ENABLE_DATA : R/W ;bitpos:[31:0] ;default: x ; */ +/* Description: GPIO0~31 output enable */ + +#define GPIO_ENABLE_DATA 0xFFFFFFFF +#define GPIO_ENABLE_DATA_M ((GPIO_ENABLE_DATA_V)<<(GPIO_ENABLE_DATA_S)) +#define GPIO_ENABLE_DATA_V 0xFFFFFFFF +#define GPIO_ENABLE_DATA_S 0 + +#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x0024) + +/* GPIO_ENABLE_DATA_W1TS : R/W ;bitpos:[31:0] ;default: x ; */ +/* Description: GPIO0~31 output enable write 1 to set */ + +#define GPIO_ENABLE_DATA_W1TS 0xFFFFFFFF +#define GPIO_ENABLE_DATA_W1TS_M ((GPIO_ENABLE_DATA_W1TS_V)<<(GPIO_ENABLE_DATA_W1TS_S)) +#define GPIO_ENABLE_DATA_W1TS_V 0xFFFFFFFF +#define GPIO_ENABLE_DATA_W1TS_S 0 + +#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x0028) + +/* GPIO_ENABLE_DATA_W1TC : R/W ;bitpos:[31:0] ;default: x ; */ +/* Description: GPIO0~31 output enable write 1 to clear */ + +#define GPIO_ENABLE_DATA_W1TC 0xFFFFFFFF +#define GPIO_ENABLE_DATA_W1TC_M ((GPIO_ENABLE_DATA_W1TC_V)<<(GPIO_ENABLE_DATA_W1TC_S)) +#define GPIO_ENABLE_DATA_W1TC_V 0xFFFFFFFF +#define GPIO_ENABLE_DATA_W1TC_S 0 + +#define GPIO_ENABLE1_REG (DR_REG_GPIO_BASE + 0x002c) + +/* GPIO_ENABLE1_DATA : R/W ;bitpos:[7:0] ;default: x ; */ +/* Description: GPIO32~39 output enable */ + +#define GPIO_ENABLE1_DATA 0x000000FF +#define GPIO_ENABLE1_DATA_M ((GPIO_ENABLE1_DATA_V)<<(GPIO_ENABLE1_DATA_S)) +#define GPIO_ENABLE1_DATA_V 0xFF +#define GPIO_ENABLE1_DATA_S 0 + +#define GPIO_ENABLE1_W1TS_REG (DR_REG_GPIO_BASE + 0x0030) + +/* GPIO_ENABLE1_DATA_W1TS : R/W ;bitpos:[7:0] ;default: x ; */ +/* Description: GPIO32~39 output enable write 1 to set */ + +#define GPIO_ENABLE1_DATA_W1TS 0x000000FF +#define GPIO_ENABLE1_DATA_W1TS_M ((GPIO_ENABLE1_DATA_W1TS_V)<<(GPIO_ENABLE1_DATA_W1TS_S)) +#define GPIO_ENABLE1_DATA_W1TS_V 0xFF +#define GPIO_ENABLE1_DATA_W1TS_S 0 + +#define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x0034) + +/* GPIO_ENABLE1_DATA_W1TC : R/W ;bitpos:[7:0] ;default: x ; */ +/* Description: GPIO32~39 output enable write 1 to clear */ + +#define GPIO_ENABLE1_DATA_W1TC 0x000000FF +#define GPIO_ENABLE1_DATA_W1TC_M ((GPIO_ENABLE1_DATA_W1TC_V)<<(GPIO_ENABLE1_DATA_W1TC_S)) +#define GPIO_ENABLE1_DATA_W1TC_V 0xFF +#define GPIO_ENABLE1_DATA_W1TC_S 0 + +#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0038) + +/* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default: ; */ +/* Description: GPIO strapping results: {2'd0 boot_sel_dig[7:1] vsdio_boot_sel + boot_sel_chip[5:0]}. Boot_sel_dig[7:1]: {U0RXD SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3}. vsdio_boot_sel: MTDI. boot_sel_chip[5:0]: {GPIO0 U0TXD GPIO2 GPIO4 MTDO GPIO5} */ + +#define GPIO_STRAPPING 0x0000FFFF +#define GPIO_STRAPPING_M ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S)) +#define GPIO_STRAPPING_V 0xFFFF +#define GPIO_STRAPPING_S 0 + +#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x003c) + +/* GPIO_IN_DATA : RO ;bitpos:[31:0] ;default: ; */ +/* Description: GPIO0~31 input value */ + +#define GPIO_IN_DATA 0xFFFFFFFF +#define GPIO_IN_DATA_M ((GPIO_IN_DATA_V)<<(GPIO_IN_DATA_S)) +#define GPIO_IN_DATA_V 0xFFFFFFFF +#define GPIO_IN_DATA_S 0 + +#define GPIO_IN1_REG (DR_REG_GPIO_BASE + 0x0040) + +/* GPIO_IN1_DATA : RO ;bitpos:[7:0] ;default: ; */ +/* Description: GPIO32~39 input value */ + +#define GPIO_IN1_DATA 0x000000FF +#define GPIO_IN1_DATA_M ((GPIO_IN1_DATA_V)<<(GPIO_IN1_DATA_S)) +#define GPIO_IN1_DATA_V 0xFF +#define GPIO_IN1_DATA_S 0 + +#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x0044) + +/* GPIO_STATUS_INT : R/W ;bitpos:[31:0] ;default: x ; */ +/* Description: GPIO0~31 interrupt status */ + +#define GPIO_STATUS_INT 0xFFFFFFFF +#define GPIO_STATUS_INT_M ((GPIO_STATUS_INT_V)<<(GPIO_STATUS_INT_S)) +#define GPIO_STATUS_INT_V 0xFFFFFFFF +#define GPIO_STATUS_INT_S 0 + +#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x0048) + +/* GPIO_STATUS_INT_W1TS : R/W ;bitpos:[31:0] ;default: x ; */ +/* Description: GPIO0~31 interrupt status write 1 to set */ + +#define GPIO_STATUS_INT_W1TS 0xFFFFFFFF +#define GPIO_STATUS_INT_W1TS_M ((GPIO_STATUS_INT_W1TS_V)<<(GPIO_STATUS_INT_W1TS_S)) +#define GPIO_STATUS_INT_W1TS_V 0xFFFFFFFF +#define GPIO_STATUS_INT_W1TS_S 0 + +#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x004c) + +/* GPIO_STATUS_INT_W1TC : R/W ;bitpos:[31:0] ;default: x ; */ +/* Description: GPIO0~31 interrupt status write 1 to clear */ + +#define GPIO_STATUS_INT_W1TC 0xFFFFFFFF +#define GPIO_STATUS_INT_W1TC_M ((GPIO_STATUS_INT_W1TC_V)<<(GPIO_STATUS_INT_W1TC_S)) +#define GPIO_STATUS_INT_W1TC_V 0xFFFFFFFF +#define GPIO_STATUS_INT_W1TC_S 0 + +#define GPIO_STATUS1_REG (DR_REG_GPIO_BASE + 0x0050) + +/* GPIO_STATUS1_INT : R/W ;bitpos:[7:0] ;default: x ; */ +/* Description: GPIO32~39 interrupt status */ + +#define GPIO_STATUS1_INT 0x000000FF +#define GPIO_STATUS1_INT_M ((GPIO_STATUS1_INT_V)<<(GPIO_STATUS1_INT_S)) +#define GPIO_STATUS1_INT_V 0xFF +#define GPIO_STATUS1_INT_S 0 + +#define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x0054) + +/* GPIO_STATUS1_INT_W1TS : R/W ;bitpos:[7:0] ;default: x ; */ +/* Description: GPIO32~39 interrupt status write 1 to set */ + +#define GPIO_STATUS1_INT_W1TS 0x000000FF +#define GPIO_STATUS1_INT_W1TS_M ((GPIO_STATUS1_INT_W1TS_V)<<(GPIO_STATUS1_INT_W1TS_S)) +#define GPIO_STATUS1_INT_W1TS_V 0xFF +#define GPIO_STATUS1_INT_W1TS_S 0 + +#define GPIO_STATUS1_W1TC_REG (DR_REG_GPIO_BASE + 0x0058) + +/* GPIO_STATUS1_INT_W1TC : R/W ;bitpos:[7:0] ;default: x ; */ +/* Description: GPIO32~39 interrupt status write 1 to clear */ + +#define GPIO_STATUS1_INT_W1TC 0x000000FF +#define GPIO_STATUS1_INT_W1TC_M ((GPIO_STATUS1_INT_W1TC_V)<<(GPIO_STATUS1_INT_W1TC_S)) +#define GPIO_STATUS1_INT_W1TC_V 0xFF +#define GPIO_STATUS1_INT_W1TC_S 0 + +#define GPIO_ACPU_INT_REG (DR_REG_GPIO_BASE + 0x0060) + +/* GPIO_APPCPU_INT : RO ;bitpos:[31:0] ;default: x ; */ +/* Description: GPIO0~31 APP CPU interrupt status */ + +#define GPIO_APPCPU_INT 0xFFFFFFFF +#define GPIO_APPCPU_INT_M ((GPIO_APPCPU_INT_V)<<(GPIO_APPCPU_INT_S)) +#define GPIO_APPCPU_INT_V 0xFFFFFFFF +#define GPIO_APPCPU_INT_S 0 + +#define GPIO_ACPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x0064) + +/* GPIO_APPCPU_NMI_INT : RO ;bitpos:[31:0] ;default: x ; */ +/* Description: GPIO0~31 APP CPU non-maskable interrupt status */ + +#define GPIO_APPCPU_NMI_INT 0xFFFFFFFF +#define GPIO_APPCPU_NMI_INT_M ((GPIO_APPCPU_NMI_INT_V)<<(GPIO_APPCPU_NMI_INT_S)) +#define GPIO_APPCPU_NMI_INT_V 0xFFFFFFFF +#define GPIO_APPCPU_NMI_INT_S 0 + +#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x0068) + +/* GPIO_PROCPU_INT : RO ;bitpos:[31:0] ;default: x ; */ +/* Description: GPIO0~31 PRO CPU interrupt status */ + +#define GPIO_PROCPU_INT 0xFFFFFFFF +#define GPIO_PROCPU_INT_M ((GPIO_PROCPU_INT_V)<<(GPIO_PROCPU_INT_S)) +#define GPIO_PROCPU_INT_V 0xFFFFFFFF +#define GPIO_PROCPU_INT_S 0 + +#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x006c) + +/* GPIO_PROCPU_NMI_INT : RO ;bitpos:[31:0] ;default: x ; */ +/* Description: GPIO0~31 PRO CPU non-maskable interrupt status */ + +#define GPIO_PROCPU_NMI_INT 0xFFFFFFFF +#define GPIO_PROCPU_NMI_INT_M ((GPIO_PROCPU_NMI_INT_V)<<(GPIO_PROCPU_NMI_INT_S)) +#define GPIO_PROCPU_NMI_INT_V 0xFFFFFFFF +#define GPIO_PROCPU_NMI_INT_S 0 + +#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x0070) + +/* GPIO_SDIO_INT : RO ;bitpos:[31:0] ;default: x ; */ +/* Description: SDIO's extent GPIO0~31 interrupt */ + +#define GPIO_SDIO_INT 0xFFFFFFFF +#define GPIO_SDIO_INT_M ((GPIO_SDIO_INT_V)<<(GPIO_SDIO_INT_S)) +#define GPIO_SDIO_INT_V 0xFFFFFFFF +#define GPIO_SDIO_INT_S 0 + +#define GPIO_ACPU_INT1_REG (DR_REG_GPIO_BASE + 0x0074) + +/* GPIO_APPCPU_INT_H : RO ;bitpos:[7:0] ;default: x ; */ +/* Description: GPIO32~39 APP CPU interrupt status */ + +#define GPIO_APPCPU_INT_H 0x000000FF +#define GPIO_APPCPU_INT_H_M ((GPIO_APPCPU_INT_H_V)<<(GPIO_APPCPU_INT_H_S)) +#define GPIO_APPCPU_INT_H_V 0xFF +#define GPIO_APPCPU_INT_H_S 0 + +#define GPIO_ACPU_NMI_INT1_REG (DR_REG_GPIO_BASE + 0x0078) + +/* GPIO_APPCPU_NMI_INT_H : RO ;bitpos:[7:0] ;default: x ; */ +/* Description: GPIO32~39 APP CPU non-maskable interrupt status */ + +#define GPIO_APPCPU_NMI_INT_H 0x000000FF +#define GPIO_APPCPU_NMI_INT_H_M ((GPIO_APPCPU_NMI_INT_H_V)<<(GPIO_APPCPU_NMI_INT_H_S)) +#define GPIO_APPCPU_NMI_INT_H_V 0xFF +#define GPIO_APPCPU_NMI_INT_H_S 0 + +#define GPIO_PCPU_INT1_REG (DR_REG_GPIO_BASE + 0x007c) + +/* GPIO_PROCPU_INT_H : RO ;bitpos:[7:0] ;default: x ; */ +/* Description: GPIO32~39 PRO CPU interrupt status */ + +#define GPIO_PROCPU_INT_H 0x000000FF +#define GPIO_PROCPU_INT_H_M ((GPIO_PROCPU_INT_H_V)<<(GPIO_PROCPU_INT_H_S)) +#define GPIO_PROCPU_INT_H_V 0xFF +#define GPIO_PROCPU_INT_H_S 0 + +#define GPIO_PCPU_NMI_INT1_REG (DR_REG_GPIO_BASE + 0x0080) + +/* GPIO_PROCPU_NMI_INT_H : RO ;bitpos:[7:0] ;default: x ; */ +/* Description: GPIO32~39 PRO CPU non-maskable interrupt status */ + +#define GPIO_PROCPU_NMI_INT_H 0x000000FF +#define GPIO_PROCPU_NMI_INT_H_M ((GPIO_PROCPU_NMI_INT_H_V)<<(GPIO_PROCPU_NMI_INT_H_S)) +#define GPIO_PROCPU_NMI_INT_H_V 0xFF +#define GPIO_PROCPU_NMI_INT_H_S 0 + +#define GPIO_CPUSDIO_INT1_REG (DR_REG_GPIO_BASE + 0x0084) + +/* GPIO_SDIO_INT_H : RO ;bitpos:[7:0] ;default: x ; */ +/* Description: SDIO's extent GPIO32~39 interrupt */ + +#define GPIO_SDIO_INT_H 0x000000FF +#define GPIO_SDIO_INT_H_M ((GPIO_SDIO_INT_H_V)<<(GPIO_SDIO_INT_H_S)) +#define GPIO_SDIO_INT_H_V 0xFF +#define GPIO_SDIO_INT_H_S 0 + +#define GPIO_REG(io_num) (GPIO_PIN0_REG + (io_num)*0x4) +#define GPIO_PIN_INT_ENA 0x0000001F +#define GPIO_PIN_INT_ENA_M ((GPIO_PIN_INT_ENA_V)<<(GPIO_PIN_INT_ENA_S)) +#define GPIO_PIN_INT_ENA_V 0x0000001F +#define GPIO_PIN_INT_ENA_S 13 +#define GPIO_PIN_CONFIG 0x00000003 +#define GPIO_PIN_CONFIG_M ((GPIO_PIN_CONFIG_V)<<(GPIO_PIN_CONFIG_S)) +#define GPIO_PIN_CONFIG_V 0x00000003 +#define GPIO_PIN_CONFIG_S 11 +#define GPIO_PIN_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN_WAKEUP_ENABLE_S 10 +#define GPIO_PIN_INT_TYPE 0x00000007 +#define GPIO_PIN_INT_TYPE_M ((GPIO_PIN_INT_TYPE_V)<<(GPIO_PIN_INT_TYPE_S)) +#define GPIO_PIN_INT_TYPE_V 0x00000007 +#define GPIO_PIN_INT_TYPE_S 7 +#define GPIO_PIN_PAD_DRIVER (BIT(2)) +#define GPIO_PIN_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN_PAD_DRIVER_V 0x1 +#define GPIO_PIN_PAD_DRIVER_S 2 + +#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x0088) + +/* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN0_INT_ENA 0x0000001F +#define GPIO_PIN0_INT_ENA_M ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S)) +#define GPIO_PIN0_INT_ENA_V 0x1F +#define GPIO_PIN0_INT_ENA_S 13 + +/* GPIO_PIN0_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN0_CONFIG 0x00000003 +#define GPIO_PIN0_CONFIG_M ((GPIO_PIN0_CONFIG_V)<<(GPIO_PIN0_CONFIG_S)) +#define GPIO_PIN0_CONFIG_V 0x3 +#define GPIO_PIN0_CONFIG_S 11 + +/* GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN0_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN0_INT_TYPE 0x00000007 +#define GPIO_PIN0_INT_TYPE_M ((GPIO_PIN0_INT_TYPE_V)<<(GPIO_PIN0_INT_TYPE_S)) +#define GPIO_PIN0_INT_TYPE_V 0x7 +#define GPIO_PIN0_INT_TYPE_S 7 + +/* GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_V 0x1 +#define GPIO_PIN0_PAD_DRIVER_S 2 + +#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x008c) + +/* GPIO_PIN1_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN1_INT_ENA 0x0000001F +#define GPIO_PIN1_INT_ENA_M ((GPIO_PIN1_INT_ENA_V)<<(GPIO_PIN1_INT_ENA_S)) +#define GPIO_PIN1_INT_ENA_V 0x1F +#define GPIO_PIN1_INT_ENA_S 13 + +/* GPIO_PIN1_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN1_CONFIG 0x00000003 +#define GPIO_PIN1_CONFIG_M ((GPIO_PIN1_CONFIG_V)<<(GPIO_PIN1_CONFIG_S)) +#define GPIO_PIN1_CONFIG_V 0x3 +#define GPIO_PIN1_CONFIG_S 11 + +/* GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN1_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN1_INT_TYPE 0x00000007 +#define GPIO_PIN1_INT_TYPE_M ((GPIO_PIN1_INT_TYPE_V)<<(GPIO_PIN1_INT_TYPE_S)) +#define GPIO_PIN1_INT_TYPE_V 0x7 +#define GPIO_PIN1_INT_TYPE_S 7 + +/* GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_V 0x1 +#define GPIO_PIN1_PAD_DRIVER_S 2 + +#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x0090) + +/* GPIO_PIN2_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN2_INT_ENA 0x0000001F +#define GPIO_PIN2_INT_ENA_M ((GPIO_PIN2_INT_ENA_V)<<(GPIO_PIN2_INT_ENA_S)) +#define GPIO_PIN2_INT_ENA_V 0x1F +#define GPIO_PIN2_INT_ENA_S 13 + +/* GPIO_PIN2_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN2_CONFIG 0x00000003 +#define GPIO_PIN2_CONFIG_M ((GPIO_PIN2_CONFIG_V)<<(GPIO_PIN2_CONFIG_S)) +#define GPIO_PIN2_CONFIG_V 0x3 +#define GPIO_PIN2_CONFIG_S 11 + +/* GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN2_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN2_INT_TYPE 0x00000007 +#define GPIO_PIN2_INT_TYPE_M ((GPIO_PIN2_INT_TYPE_V)<<(GPIO_PIN2_INT_TYPE_S)) +#define GPIO_PIN2_INT_TYPE_V 0x7 +#define GPIO_PIN2_INT_TYPE_S 7 + +/* GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_V 0x1 +#define GPIO_PIN2_PAD_DRIVER_S 2 + +#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x0094) + +/* GPIO_PIN3_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN3_INT_ENA 0x0000001F +#define GPIO_PIN3_INT_ENA_M ((GPIO_PIN3_INT_ENA_V)<<(GPIO_PIN3_INT_ENA_S)) +#define GPIO_PIN3_INT_ENA_V 0x1F +#define GPIO_PIN3_INT_ENA_S 13 + +/* GPIO_PIN3_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN3_CONFIG 0x00000003 +#define GPIO_PIN3_CONFIG_M ((GPIO_PIN3_CONFIG_V)<<(GPIO_PIN3_CONFIG_S)) +#define GPIO_PIN3_CONFIG_V 0x3 +#define GPIO_PIN3_CONFIG_S 11 + +/* GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN3_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN3_INT_TYPE 0x00000007 +#define GPIO_PIN3_INT_TYPE_M ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S)) +#define GPIO_PIN3_INT_TYPE_V 0x7 +#define GPIO_PIN3_INT_TYPE_S 7 + +/* GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_V 0x1 +#define GPIO_PIN3_PAD_DRIVER_S 2 + +#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x0098) + +/* GPIO_PIN4_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN4_INT_ENA 0x0000001F +#define GPIO_PIN4_INT_ENA_M ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S)) +#define GPIO_PIN4_INT_ENA_V 0x1F +#define GPIO_PIN4_INT_ENA_S 13 + +/* GPIO_PIN4_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN4_CONFIG 0x00000003 +#define GPIO_PIN4_CONFIG_M ((GPIO_PIN4_CONFIG_V)<<(GPIO_PIN4_CONFIG_S)) +#define GPIO_PIN4_CONFIG_V 0x3 +#define GPIO_PIN4_CONFIG_S 11 + +/* GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN4_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN4_INT_TYPE 0x00000007 +#define GPIO_PIN4_INT_TYPE_M ((GPIO_PIN4_INT_TYPE_V)<<(GPIO_PIN4_INT_TYPE_S)) +#define GPIO_PIN4_INT_TYPE_V 0x7 +#define GPIO_PIN4_INT_TYPE_S 7 + +/* GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_V 0x1 +#define GPIO_PIN4_PAD_DRIVER_S 2 + +#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x009c) + +/* GPIO_PIN5_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN5_INT_ENA 0x0000001F +#define GPIO_PIN5_INT_ENA_M ((GPIO_PIN5_INT_ENA_V)<<(GPIO_PIN5_INT_ENA_S)) +#define GPIO_PIN5_INT_ENA_V 0x1F +#define GPIO_PIN5_INT_ENA_S 13 + +/* GPIO_PIN5_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN5_CONFIG 0x00000003 +#define GPIO_PIN5_CONFIG_M ((GPIO_PIN5_CONFIG_V)<<(GPIO_PIN5_CONFIG_S)) +#define GPIO_PIN5_CONFIG_V 0x3 +#define GPIO_PIN5_CONFIG_S 11 + +/* GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN5_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN5_INT_TYPE 0x00000007 +#define GPIO_PIN5_INT_TYPE_M ((GPIO_PIN5_INT_TYPE_V)<<(GPIO_PIN5_INT_TYPE_S)) +#define GPIO_PIN5_INT_TYPE_V 0x7 +#define GPIO_PIN5_INT_TYPE_S 7 + +/* GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_V 0x1 +#define GPIO_PIN5_PAD_DRIVER_S 2 + +#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x00a0) + +/* GPIO_PIN6_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN6_INT_ENA 0x0000001F +#define GPIO_PIN6_INT_ENA_M ((GPIO_PIN6_INT_ENA_V)<<(GPIO_PIN6_INT_ENA_S)) +#define GPIO_PIN6_INT_ENA_V 0x1F +#define GPIO_PIN6_INT_ENA_S 13 + +/* GPIO_PIN6_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN6_CONFIG 0x00000003 +#define GPIO_PIN6_CONFIG_M ((GPIO_PIN6_CONFIG_V)<<(GPIO_PIN6_CONFIG_S)) +#define GPIO_PIN6_CONFIG_V 0x3 +#define GPIO_PIN6_CONFIG_S 11 + +/* GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN6_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN6_INT_TYPE 0x00000007 +#define GPIO_PIN6_INT_TYPE_M ((GPIO_PIN6_INT_TYPE_V)<<(GPIO_PIN6_INT_TYPE_S)) +#define GPIO_PIN6_INT_TYPE_V 0x7 +#define GPIO_PIN6_INT_TYPE_S 7 + +/* GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_V 0x1 +#define GPIO_PIN6_PAD_DRIVER_S 2 + +#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x00a4) + +/* GPIO_PIN7_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN7_INT_ENA 0x0000001F +#define GPIO_PIN7_INT_ENA_M ((GPIO_PIN7_INT_ENA_V)<<(GPIO_PIN7_INT_ENA_S)) +#define GPIO_PIN7_INT_ENA_V 0x1F +#define GPIO_PIN7_INT_ENA_S 13 + +/* GPIO_PIN7_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN7_CONFIG 0x00000003 +#define GPIO_PIN7_CONFIG_M ((GPIO_PIN7_CONFIG_V)<<(GPIO_PIN7_CONFIG_S)) +#define GPIO_PIN7_CONFIG_V 0x3 +#define GPIO_PIN7_CONFIG_S 11 + +/* GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN7_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN7_INT_TYPE 0x00000007 +#define GPIO_PIN7_INT_TYPE_M ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S)) +#define GPIO_PIN7_INT_TYPE_V 0x7 +#define GPIO_PIN7_INT_TYPE_S 7 + +/* GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_V 0x1 +#define GPIO_PIN7_PAD_DRIVER_S 2 + +#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x00a8) + +/* GPIO_PIN8_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN8_INT_ENA 0x0000001F +#define GPIO_PIN8_INT_ENA_M ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S)) +#define GPIO_PIN8_INT_ENA_V 0x1F +#define GPIO_PIN8_INT_ENA_S 13 + +/* GPIO_PIN8_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN8_CONFIG 0x00000003 +#define GPIO_PIN8_CONFIG_M ((GPIO_PIN8_CONFIG_V)<<(GPIO_PIN8_CONFIG_S)) +#define GPIO_PIN8_CONFIG_V 0x3 +#define GPIO_PIN8_CONFIG_S 11 + +/* GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN8_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN8_INT_TYPE 0x00000007 +#define GPIO_PIN8_INT_TYPE_M ((GPIO_PIN8_INT_TYPE_V)<<(GPIO_PIN8_INT_TYPE_S)) +#define GPIO_PIN8_INT_TYPE_V 0x7 +#define GPIO_PIN8_INT_TYPE_S 7 + +/* GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_V 0x1 +#define GPIO_PIN8_PAD_DRIVER_S 2 + +#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x00ac) + +/* GPIO_PIN9_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN9_INT_ENA 0x0000001F +#define GPIO_PIN9_INT_ENA_M ((GPIO_PIN9_INT_ENA_V)<<(GPIO_PIN9_INT_ENA_S)) +#define GPIO_PIN9_INT_ENA_V 0x1F +#define GPIO_PIN9_INT_ENA_S 13 + +/* GPIO_PIN9_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN9_CONFIG 0x00000003 +#define GPIO_PIN9_CONFIG_M ((GPIO_PIN9_CONFIG_V)<<(GPIO_PIN9_CONFIG_S)) +#define GPIO_PIN9_CONFIG_V 0x3 +#define GPIO_PIN9_CONFIG_S 11 + +/* GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN9_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN9_INT_TYPE 0x00000007 +#define GPIO_PIN9_INT_TYPE_M ((GPIO_PIN9_INT_TYPE_V)<<(GPIO_PIN9_INT_TYPE_S)) +#define GPIO_PIN9_INT_TYPE_V 0x7 +#define GPIO_PIN9_INT_TYPE_S 7 + +/* GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_V 0x1 +#define GPIO_PIN9_PAD_DRIVER_S 2 + +#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x00b0) + +/* GPIO_PIN10_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN10_INT_ENA 0x0000001F +#define GPIO_PIN10_INT_ENA_M ((GPIO_PIN10_INT_ENA_V)<<(GPIO_PIN10_INT_ENA_S)) +#define GPIO_PIN10_INT_ENA_V 0x1F +#define GPIO_PIN10_INT_ENA_S 13 + +/* GPIO_PIN10_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN10_CONFIG 0x00000003 +#define GPIO_PIN10_CONFIG_M ((GPIO_PIN10_CONFIG_V)<<(GPIO_PIN10_CONFIG_S)) +#define GPIO_PIN10_CONFIG_V 0x3 +#define GPIO_PIN10_CONFIG_S 11 + +/* GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN10_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN10_INT_TYPE 0x00000007 +#define GPIO_PIN10_INT_TYPE_M ((GPIO_PIN10_INT_TYPE_V)<<(GPIO_PIN10_INT_TYPE_S)) +#define GPIO_PIN10_INT_TYPE_V 0x7 +#define GPIO_PIN10_INT_TYPE_S 7 + +/* GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_V 0x1 +#define GPIO_PIN10_PAD_DRIVER_S 2 + +#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0x00b4) + +/* GPIO_PIN11_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN11_INT_ENA 0x0000001F +#define GPIO_PIN11_INT_ENA_M ((GPIO_PIN11_INT_ENA_V)<<(GPIO_PIN11_INT_ENA_S)) +#define GPIO_PIN11_INT_ENA_V 0x1F +#define GPIO_PIN11_INT_ENA_S 13 + +/* GPIO_PIN11_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN11_CONFIG 0x00000003 +#define GPIO_PIN11_CONFIG_M ((GPIO_PIN11_CONFIG_V)<<(GPIO_PIN11_CONFIG_S)) +#define GPIO_PIN11_CONFIG_V 0x3 +#define GPIO_PIN11_CONFIG_S 11 + +/* GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN11_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN11_INT_TYPE 0x00000007 +#define GPIO_PIN11_INT_TYPE_M ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S)) +#define GPIO_PIN11_INT_TYPE_V 0x7 +#define GPIO_PIN11_INT_TYPE_S 7 + +/* GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_V 0x1 +#define GPIO_PIN11_PAD_DRIVER_S 2 + +#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0x00b8) + +/* GPIO_PIN12_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN12_INT_ENA 0x0000001F +#define GPIO_PIN12_INT_ENA_M ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S)) +#define GPIO_PIN12_INT_ENA_V 0x1F +#define GPIO_PIN12_INT_ENA_S 13 + +/* GPIO_PIN12_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN12_CONFIG 0x00000003 +#define GPIO_PIN12_CONFIG_M ((GPIO_PIN12_CONFIG_V)<<(GPIO_PIN12_CONFIG_S)) +#define GPIO_PIN12_CONFIG_V 0x3 +#define GPIO_PIN12_CONFIG_S 11 + +/* GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN12_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN12_INT_TYPE 0x00000007 +#define GPIO_PIN12_INT_TYPE_M ((GPIO_PIN12_INT_TYPE_V)<<(GPIO_PIN12_INT_TYPE_S)) +#define GPIO_PIN12_INT_TYPE_V 0x7 +#define GPIO_PIN12_INT_TYPE_S 7 + +/* GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_V 0x1 +#define GPIO_PIN12_PAD_DRIVER_S 2 + +#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0x00bc) + +/* GPIO_PIN13_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN13_INT_ENA 0x0000001F +#define GPIO_PIN13_INT_ENA_M ((GPIO_PIN13_INT_ENA_V)<<(GPIO_PIN13_INT_ENA_S)) +#define GPIO_PIN13_INT_ENA_V 0x1F +#define GPIO_PIN13_INT_ENA_S 13 + +/* GPIO_PIN13_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN13_CONFIG 0x00000003 +#define GPIO_PIN13_CONFIG_M ((GPIO_PIN13_CONFIG_V)<<(GPIO_PIN13_CONFIG_S)) +#define GPIO_PIN13_CONFIG_V 0x3 +#define GPIO_PIN13_CONFIG_S 11 + +/* GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN13_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN13_INT_TYPE 0x00000007 +#define GPIO_PIN13_INT_TYPE_M ((GPIO_PIN13_INT_TYPE_V)<<(GPIO_PIN13_INT_TYPE_S)) +#define GPIO_PIN13_INT_TYPE_V 0x7 +#define GPIO_PIN13_INT_TYPE_S 7 + +/* GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_V 0x1 +#define GPIO_PIN13_PAD_DRIVER_S 2 + +#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0x00c0) + +/* GPIO_PIN14_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN14_INT_ENA 0x0000001F +#define GPIO_PIN14_INT_ENA_M ((GPIO_PIN14_INT_ENA_V)<<(GPIO_PIN14_INT_ENA_S)) +#define GPIO_PIN14_INT_ENA_V 0x1F +#define GPIO_PIN14_INT_ENA_S 13 + +/* GPIO_PIN14_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN14_CONFIG 0x00000003 +#define GPIO_PIN14_CONFIG_M ((GPIO_PIN14_CONFIG_V)<<(GPIO_PIN14_CONFIG_S)) +#define GPIO_PIN14_CONFIG_V 0x3 +#define GPIO_PIN14_CONFIG_S 11 + +/* GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN14_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN14_INT_TYPE 0x00000007 +#define GPIO_PIN14_INT_TYPE_M ((GPIO_PIN14_INT_TYPE_V)<<(GPIO_PIN14_INT_TYPE_S)) +#define GPIO_PIN14_INT_TYPE_V 0x7 +#define GPIO_PIN14_INT_TYPE_S 7 + +/* GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_V 0x1 +#define GPIO_PIN14_PAD_DRIVER_S 2 + +#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0x00c4) + +/* GPIO_PIN15_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN15_INT_ENA 0x0000001F +#define GPIO_PIN15_INT_ENA_M ((GPIO_PIN15_INT_ENA_V)<<(GPIO_PIN15_INT_ENA_S)) +#define GPIO_PIN15_INT_ENA_V 0x1F +#define GPIO_PIN15_INT_ENA_S 13 + +/* GPIO_PIN15_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN15_CONFIG 0x00000003 +#define GPIO_PIN15_CONFIG_M ((GPIO_PIN15_CONFIG_V)<<(GPIO_PIN15_CONFIG_S)) +#define GPIO_PIN15_CONFIG_V 0x3 +#define GPIO_PIN15_CONFIG_S 11 + +/* GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN15_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN15_INT_TYPE 0x00000007 +#define GPIO_PIN15_INT_TYPE_M ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S)) +#define GPIO_PIN15_INT_TYPE_V 0x7 +#define GPIO_PIN15_INT_TYPE_S 7 + +/* GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_V 0x1 +#define GPIO_PIN15_PAD_DRIVER_S 2 + +#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0x00c8) + +/* GPIO_PIN16_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN16_INT_ENA 0x0000001F +#define GPIO_PIN16_INT_ENA_M ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S)) +#define GPIO_PIN16_INT_ENA_V 0x1F +#define GPIO_PIN16_INT_ENA_S 13 + +/* GPIO_PIN16_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN16_CONFIG 0x00000003 +#define GPIO_PIN16_CONFIG_M ((GPIO_PIN16_CONFIG_V)<<(GPIO_PIN16_CONFIG_S)) +#define GPIO_PIN16_CONFIG_V 0x3 +#define GPIO_PIN16_CONFIG_S 11 + +/* GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN16_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN16_INT_TYPE 0x00000007 +#define GPIO_PIN16_INT_TYPE_M ((GPIO_PIN16_INT_TYPE_V)<<(GPIO_PIN16_INT_TYPE_S)) +#define GPIO_PIN16_INT_TYPE_V 0x7 +#define GPIO_PIN16_INT_TYPE_S 7 + +/* GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_V 0x1 +#define GPIO_PIN16_PAD_DRIVER_S 2 + +#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0x00cc) + +/* GPIO_PIN17_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN17_INT_ENA 0x0000001F +#define GPIO_PIN17_INT_ENA_M ((GPIO_PIN17_INT_ENA_V)<<(GPIO_PIN17_INT_ENA_S)) +#define GPIO_PIN17_INT_ENA_V 0x1F +#define GPIO_PIN17_INT_ENA_S 13 + +/* GPIO_PIN17_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN17_CONFIG 0x00000003 +#define GPIO_PIN17_CONFIG_M ((GPIO_PIN17_CONFIG_V)<<(GPIO_PIN17_CONFIG_S)) +#define GPIO_PIN17_CONFIG_V 0x3 +#define GPIO_PIN17_CONFIG_S 11 + +/* GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN17_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN17_INT_TYPE 0x00000007 +#define GPIO_PIN17_INT_TYPE_M ((GPIO_PIN17_INT_TYPE_V)<<(GPIO_PIN17_INT_TYPE_S)) +#define GPIO_PIN17_INT_TYPE_V 0x7 +#define GPIO_PIN17_INT_TYPE_S 7 + +/* GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_V 0x1 +#define GPIO_PIN17_PAD_DRIVER_S 2 + +#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0x00d0) + +/* GPIO_PIN18_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN18_INT_ENA 0x0000001F +#define GPIO_PIN18_INT_ENA_M ((GPIO_PIN18_INT_ENA_V)<<(GPIO_PIN18_INT_ENA_S)) +#define GPIO_PIN18_INT_ENA_V 0x1F +#define GPIO_PIN18_INT_ENA_S 13 + +/* GPIO_PIN18_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN18_CONFIG 0x00000003 +#define GPIO_PIN18_CONFIG_M ((GPIO_PIN18_CONFIG_V)<<(GPIO_PIN18_CONFIG_S)) +#define GPIO_PIN18_CONFIG_V 0x3 +#define GPIO_PIN18_CONFIG_S 11 + +/* GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN18_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN18_INT_TYPE 0x00000007 +#define GPIO_PIN18_INT_TYPE_M ((GPIO_PIN18_INT_TYPE_V)<<(GPIO_PIN18_INT_TYPE_S)) +#define GPIO_PIN18_INT_TYPE_V 0x7 +#define GPIO_PIN18_INT_TYPE_S 7 + +/* GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN18_PAD_DRIVER (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_V 0x1 +#define GPIO_PIN18_PAD_DRIVER_S 2 + +#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0x00d4) + +/* GPIO_PIN19_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN19_INT_ENA 0x0000001F +#define GPIO_PIN19_INT_ENA_M ((GPIO_PIN19_INT_ENA_V)<<(GPIO_PIN19_INT_ENA_S)) +#define GPIO_PIN19_INT_ENA_V 0x1F +#define GPIO_PIN19_INT_ENA_S 13 + +/* GPIO_PIN19_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN19_CONFIG 0x00000003 +#define GPIO_PIN19_CONFIG_M ((GPIO_PIN19_CONFIG_V)<<(GPIO_PIN19_CONFIG_S)) +#define GPIO_PIN19_CONFIG_V 0x3 +#define GPIO_PIN19_CONFIG_S 11 + +/* GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN19_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN19_INT_TYPE 0x00000007 +#define GPIO_PIN19_INT_TYPE_M ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S)) +#define GPIO_PIN19_INT_TYPE_V 0x7 +#define GPIO_PIN19_INT_TYPE_S 7 + +/* GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN19_PAD_DRIVER (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_V 0x1 +#define GPIO_PIN19_PAD_DRIVER_S 2 + +#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0x00d8) + +/* GPIO_PIN20_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-mask interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-mask interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN20_INT_ENA 0x0000001F +#define GPIO_PIN20_INT_ENA_M ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S)) +#define GPIO_PIN20_INT_ENA_V 0x1F +#define GPIO_PIN20_INT_ENA_S 13 + +/* GPIO_PIN20_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN20_CONFIG 0x00000003 +#define GPIO_PIN20_CONFIG_M ((GPIO_PIN20_CONFIG_V)<<(GPIO_PIN20_CONFIG_S)) +#define GPIO_PIN20_CONFIG_V 0x3 +#define GPIO_PIN20_CONFIG_S 11 + +/* GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN20_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN20_INT_TYPE 0x00000007 +#define GPIO_PIN20_INT_TYPE_M ((GPIO_PIN20_INT_TYPE_V)<<(GPIO_PIN20_INT_TYPE_S)) +#define GPIO_PIN20_INT_TYPE_V 0x7 +#define GPIO_PIN20_INT_TYPE_S 7 + +/* GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN20_PAD_DRIVER (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_V 0x1 +#define GPIO_PIN20_PAD_DRIVER_S 2 + +#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0x00dc) + +/* GPIO_PIN21_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN21_INT_ENA 0x0000001F +#define GPIO_PIN21_INT_ENA_M ((GPIO_PIN21_INT_ENA_V)<<(GPIO_PIN21_INT_ENA_S)) +#define GPIO_PIN21_INT_ENA_V 0x1F +#define GPIO_PIN21_INT_ENA_S 13 + +/* GPIO_PIN21_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN21_CONFIG 0x00000003 +#define GPIO_PIN21_CONFIG_M ((GPIO_PIN21_CONFIG_V)<<(GPIO_PIN21_CONFIG_S)) +#define GPIO_PIN21_CONFIG_V 0x3 +#define GPIO_PIN21_CONFIG_S 11 + +/* GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN21_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN21_INT_TYPE 0x00000007 +#define GPIO_PIN21_INT_TYPE_M ((GPIO_PIN21_INT_TYPE_V)<<(GPIO_PIN21_INT_TYPE_S)) +#define GPIO_PIN21_INT_TYPE_V 0x7 +#define GPIO_PIN21_INT_TYPE_S 7 + +/* GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN21_PAD_DRIVER (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_V 0x1 +#define GPIO_PIN21_PAD_DRIVER_S 2 + +#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0x00e0) + +/* GPIO_PIN22_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: */ + +#define GPIO_PIN22_INT_ENA 0x0000001F +#define GPIO_PIN22_INT_ENA_M ((GPIO_PIN22_INT_ENA_V)<<(GPIO_PIN22_INT_ENA_S)) +#define GPIO_PIN22_INT_ENA_V 0x1F +#define GPIO_PIN22_INT_ENA_S 13 + +/* GPIO_PIN22_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN22_CONFIG 0x00000003 +#define GPIO_PIN22_CONFIG_M ((GPIO_PIN22_CONFIG_V)<<(GPIO_PIN22_CONFIG_S)) +#define GPIO_PIN22_CONFIG_V 0x3 +#define GPIO_PIN22_CONFIG_S 11 + +/* GPIO_PIN22_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN22_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN22_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN22_INT_TYPE 0x00000007 +#define GPIO_PIN22_INT_TYPE_M ((GPIO_PIN22_INT_TYPE_V)<<(GPIO_PIN22_INT_TYPE_S)) +#define GPIO_PIN22_INT_TYPE_V 0x7 +#define GPIO_PIN22_INT_TYPE_S 7 + +/* GPIO_PIN22_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: */ + +#define GPIO_PIN22_PAD_DRIVER (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_V 0x1 +#define GPIO_PIN22_PAD_DRIVER_S 2 + +#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0x00e4) + +/* GPIO_PIN23_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN23_INT_ENA 0x0000001F +#define GPIO_PIN23_INT_ENA_M ((GPIO_PIN23_INT_ENA_V)<<(GPIO_PIN23_INT_ENA_S)) +#define GPIO_PIN23_INT_ENA_V 0x1F +#define GPIO_PIN23_INT_ENA_S 13 + +/* GPIO_PIN23_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN23_CONFIG 0x00000003 +#define GPIO_PIN23_CONFIG_M ((GPIO_PIN23_CONFIG_V)<<(GPIO_PIN23_CONFIG_S)) +#define GPIO_PIN23_CONFIG_V 0x3 +#define GPIO_PIN23_CONFIG_S 11 + +/* GPIO_PIN23_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN23_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN23_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN23_INT_TYPE 0x00000007 +#define GPIO_PIN23_INT_TYPE_M ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S)) +#define GPIO_PIN23_INT_TYPE_V 0x7 +#define GPIO_PIN23_INT_TYPE_S 7 + +/* GPIO_PIN23_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN23_PAD_DRIVER (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_V 0x1 +#define GPIO_PIN23_PAD_DRIVER_S 2 + +#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0x00e8) + +/* GPIO_PIN24_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN24_INT_ENA 0x0000001F +#define GPIO_PIN24_INT_ENA_M ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S)) +#define GPIO_PIN24_INT_ENA_V 0x1F +#define GPIO_PIN24_INT_ENA_S 13 + +/* GPIO_PIN24_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN24_CONFIG 0x00000003 +#define GPIO_PIN24_CONFIG_M ((GPIO_PIN24_CONFIG_V)<<(GPIO_PIN24_CONFIG_S)) +#define GPIO_PIN24_CONFIG_V 0x3 +#define GPIO_PIN24_CONFIG_S 11 + +/* GPIO_PIN24_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN24_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN24_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN24_INT_TYPE 0x00000007 +#define GPIO_PIN24_INT_TYPE_M ((GPIO_PIN24_INT_TYPE_V)<<(GPIO_PIN24_INT_TYPE_S)) +#define GPIO_PIN24_INT_TYPE_V 0x7 +#define GPIO_PIN24_INT_TYPE_S 7 + +/* GPIO_PIN24_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN24_PAD_DRIVER (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_V 0x1 +#define GPIO_PIN24_PAD_DRIVER_S 2 + +#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0x00ec) + +/* GPIO_PIN25_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN25_INT_ENA 0x0000001F +#define GPIO_PIN25_INT_ENA_M ((GPIO_PIN25_INT_ENA_V)<<(GPIO_PIN25_INT_ENA_S)) +#define GPIO_PIN25_INT_ENA_V 0x1F +#define GPIO_PIN25_INT_ENA_S 13 + +/* GPIO_PIN25_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN25_CONFIG 0x00000003 +#define GPIO_PIN25_CONFIG_M ((GPIO_PIN25_CONFIG_V)<<(GPIO_PIN25_CONFIG_S)) +#define GPIO_PIN25_CONFIG_V 0x3 +#define GPIO_PIN25_CONFIG_S 11 + +/* GPIO_PIN25_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN25_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN25_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN25_INT_TYPE 0x00000007 +#define GPIO_PIN25_INT_TYPE_M ((GPIO_PIN25_INT_TYPE_V)<<(GPIO_PIN25_INT_TYPE_S)) +#define GPIO_PIN25_INT_TYPE_V 0x7 +#define GPIO_PIN25_INT_TYPE_S 7 + +/* GPIO_PIN25_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN25_PAD_DRIVER (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_V 0x1 +#define GPIO_PIN25_PAD_DRIVER_S 2 + +#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0x00f0) + +/* GPIO_PIN26_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN26_INT_ENA 0x0000001F +#define GPIO_PIN26_INT_ENA_M ((GPIO_PIN26_INT_ENA_V)<<(GPIO_PIN26_INT_ENA_S)) +#define GPIO_PIN26_INT_ENA_V 0x1F +#define GPIO_PIN26_INT_ENA_S 13 + +/* GPIO_PIN26_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN26_CONFIG 0x00000003 +#define GPIO_PIN26_CONFIG_M ((GPIO_PIN26_CONFIG_V)<<(GPIO_PIN26_CONFIG_S)) +#define GPIO_PIN26_CONFIG_V 0x3 +#define GPIO_PIN26_CONFIG_S 11 + +/* GPIO_PIN26_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN26_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN26_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN26_INT_TYPE 0x00000007 +#define GPIO_PIN26_INT_TYPE_M ((GPIO_PIN26_INT_TYPE_V)<<(GPIO_PIN26_INT_TYPE_S)) +#define GPIO_PIN26_INT_TYPE_V 0x7 +#define GPIO_PIN26_INT_TYPE_S 7 + +/* GPIO_PIN26_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN26_PAD_DRIVER (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_V 0x1 +#define GPIO_PIN26_PAD_DRIVER_S 2 + +#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0x00f4) + +/* GPIO_PIN27_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN27_INT_ENA 0x0000001F +#define GPIO_PIN27_INT_ENA_M ((GPIO_PIN27_INT_ENA_V)<<(GPIO_PIN27_INT_ENA_S)) +#define GPIO_PIN27_INT_ENA_V 0x1F +#define GPIO_PIN27_INT_ENA_S 13 + +/* GPIO_PIN27_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN27_CONFIG 0x00000003 +#define GPIO_PIN27_CONFIG_M ((GPIO_PIN27_CONFIG_V)<<(GPIO_PIN27_CONFIG_S)) +#define GPIO_PIN27_CONFIG_V 0x3 +#define GPIO_PIN27_CONFIG_S 11 + +/* GPIO_PIN27_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN27_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN27_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN27_INT_TYPE 0x00000007 +#define GPIO_PIN27_INT_TYPE_M ((GPIO_PIN27_INT_TYPE_V)<<(GPIO_PIN27_INT_TYPE_S)) +#define GPIO_PIN27_INT_TYPE_V 0x7 +#define GPIO_PIN27_INT_TYPE_S 7 + +/* GPIO_PIN27_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN27_PAD_DRIVER (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_V 0x1 +#define GPIO_PIN27_PAD_DRIVER_S 2 + +#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0x00f8) + +/* GPIO_PIN28_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN28_INT_ENA 0x0000001F +#define GPIO_PIN28_INT_ENA_M ((GPIO_PIN28_INT_ENA_V)<<(GPIO_PIN28_INT_ENA_S)) +#define GPIO_PIN28_INT_ENA_V 0x1F +#define GPIO_PIN28_INT_ENA_S 13 + +/* GPIO_PIN28_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN28_CONFIG 0x00000003 +#define GPIO_PIN28_CONFIG_M ((GPIO_PIN28_CONFIG_V)<<(GPIO_PIN28_CONFIG_S)) +#define GPIO_PIN28_CONFIG_V 0x3 +#define GPIO_PIN28_CONFIG_S 11 + +/* GPIO_PIN28_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN28_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN28_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN28_INT_TYPE 0x00000007 +#define GPIO_PIN28_INT_TYPE_M ((GPIO_PIN28_INT_TYPE_V)<<(GPIO_PIN28_INT_TYPE_S)) +#define GPIO_PIN28_INT_TYPE_V 0x7 +#define GPIO_PIN28_INT_TYPE_S 7 + +/* GPIO_PIN28_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN28_PAD_DRIVER (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_V 0x1 +#define GPIO_PIN28_PAD_DRIVER_S 2 + +#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0x00fc) + +/* GPIO_PIN29_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN29_INT_ENA 0x0000001F +#define GPIO_PIN29_INT_ENA_M ((GPIO_PIN29_INT_ENA_V)<<(GPIO_PIN29_INT_ENA_S)) +#define GPIO_PIN29_INT_ENA_V 0x1F +#define GPIO_PIN29_INT_ENA_S 13 + +/* GPIO_PIN29_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN29_CONFIG 0x00000003 +#define GPIO_PIN29_CONFIG_M ((GPIO_PIN29_CONFIG_V)<<(GPIO_PIN29_CONFIG_S)) +#define GPIO_PIN29_CONFIG_V 0x3 +#define GPIO_PIN29_CONFIG_S 11 + +/* GPIO_PIN29_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN29_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN29_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN29_INT_TYPE 0x00000007 +#define GPIO_PIN29_INT_TYPE_M ((GPIO_PIN29_INT_TYPE_V)<<(GPIO_PIN29_INT_TYPE_S)) +#define GPIO_PIN29_INT_TYPE_V 0x7 +#define GPIO_PIN29_INT_TYPE_S 7 + +/* GPIO_PIN29_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN29_PAD_DRIVER (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER_V 0x1 +#define GPIO_PIN29_PAD_DRIVER_S 2 + +#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0x0100) + +/* GPIO_PIN30_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN30_INT_ENA 0x0000001F +#define GPIO_PIN30_INT_ENA_M ((GPIO_PIN30_INT_ENA_V)<<(GPIO_PIN30_INT_ENA_S)) +#define GPIO_PIN30_INT_ENA_V 0x1F +#define GPIO_PIN30_INT_ENA_S 13 + +/* GPIO_PIN30_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN30_CONFIG 0x00000003 +#define GPIO_PIN30_CONFIG_M ((GPIO_PIN30_CONFIG_V)<<(GPIO_PIN30_CONFIG_S)) +#define GPIO_PIN30_CONFIG_V 0x3 +#define GPIO_PIN30_CONFIG_S 11 + +/* GPIO_PIN30_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN30_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN30_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN30_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN30_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN30_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN30_INT_TYPE 0x00000007 +#define GPIO_PIN30_INT_TYPE_M ((GPIO_PIN30_INT_TYPE_V)<<(GPIO_PIN30_INT_TYPE_S)) +#define GPIO_PIN30_INT_TYPE_V 0x7 +#define GPIO_PIN30_INT_TYPE_S 7 + +/* GPIO_PIN30_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN30_PAD_DRIVER (BIT(2)) +#define GPIO_PIN30_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN30_PAD_DRIVER_V 0x1 +#define GPIO_PIN30_PAD_DRIVER_S 2 + +#define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0x0104) + +/* GPIO_PIN31_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN31_INT_ENA 0x0000001F +#define GPIO_PIN31_INT_ENA_M ((GPIO_PIN31_INT_ENA_V)<<(GPIO_PIN31_INT_ENA_S)) +#define GPIO_PIN31_INT_ENA_V 0x1F +#define GPIO_PIN31_INT_ENA_S 13 + +/* GPIO_PIN31_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN31_CONFIG 0x00000003 +#define GPIO_PIN31_CONFIG_M ((GPIO_PIN31_CONFIG_V)<<(GPIO_PIN31_CONFIG_S)) +#define GPIO_PIN31_CONFIG_V 0x3 +#define GPIO_PIN31_CONFIG_S 11 + +/* GPIO_PIN31_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN31_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN31_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN31_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN31_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN31_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN31_INT_TYPE 0x00000007 +#define GPIO_PIN31_INT_TYPE_M ((GPIO_PIN31_INT_TYPE_V)<<(GPIO_PIN31_INT_TYPE_S)) +#define GPIO_PIN31_INT_TYPE_V 0x7 +#define GPIO_PIN31_INT_TYPE_S 7 + +/* GPIO_PIN31_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN31_PAD_DRIVER (BIT(2)) +#define GPIO_PIN31_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN31_PAD_DRIVER_V 0x1 +#define GPIO_PIN31_PAD_DRIVER_S 2 + +#define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0x0108) + +/* GPIO_PIN32_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN32_INT_ENA 0x0000001F +#define GPIO_PIN32_INT_ENA_M ((GPIO_PIN32_INT_ENA_V)<<(GPIO_PIN32_INT_ENA_S)) +#define GPIO_PIN32_INT_ENA_V 0x1F +#define GPIO_PIN32_INT_ENA_S 13 + +/* GPIO_PIN32_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN32_CONFIG 0x00000003 +#define GPIO_PIN32_CONFIG_M ((GPIO_PIN32_CONFIG_V)<<(GPIO_PIN32_CONFIG_S)) +#define GPIO_PIN32_CONFIG_V 0x3 +#define GPIO_PIN32_CONFIG_S 11 + +/* GPIO_PIN32_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN32_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN32_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN32_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN32_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN32_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN32_INT_TYPE 0x00000007 +#define GPIO_PIN32_INT_TYPE_M ((GPIO_PIN32_INT_TYPE_V)<<(GPIO_PIN32_INT_TYPE_S)) +#define GPIO_PIN32_INT_TYPE_V 0x7 +#define GPIO_PIN32_INT_TYPE_S 7 + +/* GPIO_PIN32_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN32_PAD_DRIVER (BIT(2)) +#define GPIO_PIN32_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN32_PAD_DRIVER_V 0x1 +#define GPIO_PIN32_PAD_DRIVER_S 2 + +#define GPIO_PIN33_REG (DR_REG_GPIO_BASE + 0x010c) + +/* GPIO_PIN33_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN33_INT_ENA 0x0000001F +#define GPIO_PIN33_INT_ENA_M ((GPIO_PIN33_INT_ENA_V)<<(GPIO_PIN33_INT_ENA_S)) +#define GPIO_PIN33_INT_ENA_V 0x1F +#define GPIO_PIN33_INT_ENA_S 13 + +/* GPIO_PIN33_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN33_CONFIG 0x00000003 +#define GPIO_PIN33_CONFIG_M ((GPIO_PIN33_CONFIG_V)<<(GPIO_PIN33_CONFIG_S)) +#define GPIO_PIN33_CONFIG_V 0x3 +#define GPIO_PIN33_CONFIG_S 11 + +/* GPIO_PIN33_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN33_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN33_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN33_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN33_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN33_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN33_INT_TYPE 0x00000007 +#define GPIO_PIN33_INT_TYPE_M ((GPIO_PIN33_INT_TYPE_V)<<(GPIO_PIN33_INT_TYPE_S)) +#define GPIO_PIN33_INT_TYPE_V 0x7 +#define GPIO_PIN33_INT_TYPE_S 7 + +/* GPIO_PIN33_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN33_PAD_DRIVER (BIT(2)) +#define GPIO_PIN33_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN33_PAD_DRIVER_V 0x1 +#define GPIO_PIN33_PAD_DRIVER_S 2 + +#define GPIO_PIN34_REG (DR_REG_GPIO_BASE + 0x0110) + +/* GPIO_PIN34_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN34_INT_ENA 0x0000001F +#define GPIO_PIN34_INT_ENA_M ((GPIO_PIN34_INT_ENA_V)<<(GPIO_PIN34_INT_ENA_S)) +#define GPIO_PIN34_INT_ENA_V 0x1F +#define GPIO_PIN34_INT_ENA_S 13 + +/* GPIO_PIN34_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN34_CONFIG 0x00000003 +#define GPIO_PIN34_CONFIG_M ((GPIO_PIN34_CONFIG_V)<<(GPIO_PIN34_CONFIG_S)) +#define GPIO_PIN34_CONFIG_V 0x3 +#define GPIO_PIN34_CONFIG_S 11 + +/* GPIO_PIN34_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN34_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN34_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN34_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN34_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN34_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN34_INT_TYPE 0x00000007 +#define GPIO_PIN34_INT_TYPE_M ((GPIO_PIN34_INT_TYPE_V)<<(GPIO_PIN34_INT_TYPE_S)) +#define GPIO_PIN34_INT_TYPE_V 0x7 +#define GPIO_PIN34_INT_TYPE_S 7 + +/* GPIO_PIN34_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN34_PAD_DRIVER (BIT(2)) +#define GPIO_PIN34_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN34_PAD_DRIVER_V 0x1 +#define GPIO_PIN34_PAD_DRIVER_S 2 + +#define GPIO_PIN35_REG (DR_REG_GPIO_BASE + 0x0114) + +/* GPIO_PIN35_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN35_INT_ENA 0x0000001F +#define GPIO_PIN35_INT_ENA_M ((GPIO_PIN35_INT_ENA_V)<<(GPIO_PIN35_INT_ENA_S)) +#define GPIO_PIN35_INT_ENA_V 0x1F +#define GPIO_PIN35_INT_ENA_S 13 + +/* GPIO_PIN35_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN35_CONFIG 0x00000003 +#define GPIO_PIN35_CONFIG_M ((GPIO_PIN35_CONFIG_V)<<(GPIO_PIN35_CONFIG_S)) +#define GPIO_PIN35_CONFIG_V 0x3 +#define GPIO_PIN35_CONFIG_S 11 + +/* GPIO_PIN35_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN35_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN35_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN35_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN35_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN35_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN35_INT_TYPE 0x00000007 +#define GPIO_PIN35_INT_TYPE_M ((GPIO_PIN35_INT_TYPE_V)<<(GPIO_PIN35_INT_TYPE_S)) +#define GPIO_PIN35_INT_TYPE_V 0x7 +#define GPIO_PIN35_INT_TYPE_S 7 + +/* GPIO_PIN35_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN35_PAD_DRIVER (BIT(2)) +#define GPIO_PIN35_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN35_PAD_DRIVER_V 0x1 +#define GPIO_PIN35_PAD_DRIVER_S 2 + +#define GPIO_PIN36_REG (DR_REG_GPIO_BASE + 0x0118) + +/* GPIO_PIN36_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN36_INT_ENA 0x0000001F +#define GPIO_PIN36_INT_ENA_M ((GPIO_PIN36_INT_ENA_V)<<(GPIO_PIN36_INT_ENA_S)) +#define GPIO_PIN36_INT_ENA_V 0x1F +#define GPIO_PIN36_INT_ENA_S 13 + +/* GPIO_PIN36_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN36_CONFIG 0x00000003 +#define GPIO_PIN36_CONFIG_M ((GPIO_PIN36_CONFIG_V)<<(GPIO_PIN36_CONFIG_S)) +#define GPIO_PIN36_CONFIG_V 0x3 +#define GPIO_PIN36_CONFIG_S 11 + +/* GPIO_PIN36_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN36_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN36_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN36_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN36_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN36_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN36_INT_TYPE 0x00000007 +#define GPIO_PIN36_INT_TYPE_M ((GPIO_PIN36_INT_TYPE_V)<<(GPIO_PIN36_INT_TYPE_S)) +#define GPIO_PIN36_INT_TYPE_V 0x7 +#define GPIO_PIN36_INT_TYPE_S 7 + +/* GPIO_PIN36_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN36_PAD_DRIVER (BIT(2)) +#define GPIO_PIN36_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN36_PAD_DRIVER_V 0x1 +#define GPIO_PIN36_PAD_DRIVER_S 2 + +#define GPIO_PIN37_REG (DR_REG_GPIO_BASE + 0x011c) + +/* GPIO_PIN37_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN37_INT_ENA 0x0000001F +#define GPIO_PIN37_INT_ENA_M ((GPIO_PIN37_INT_ENA_V)<<(GPIO_PIN37_INT_ENA_S)) +#define GPIO_PIN37_INT_ENA_V 0x1F +#define GPIO_PIN37_INT_ENA_S 13 + +/* GPIO_PIN37_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN37_CONFIG 0x00000003 +#define GPIO_PIN37_CONFIG_M ((GPIO_PIN37_CONFIG_V)<<(GPIO_PIN37_CONFIG_S)) +#define GPIO_PIN37_CONFIG_V 0x3 +#define GPIO_PIN37_CONFIG_S 11 + +/* GPIO_PIN37_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN37_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN37_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN37_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN37_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN37_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN37_INT_TYPE 0x00000007 +#define GPIO_PIN37_INT_TYPE_M ((GPIO_PIN37_INT_TYPE_V)<<(GPIO_PIN37_INT_TYPE_S)) +#define GPIO_PIN37_INT_TYPE_V 0x7 +#define GPIO_PIN37_INT_TYPE_S 7 + +/* GPIO_PIN37_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN37_PAD_DRIVER (BIT(2)) +#define GPIO_PIN37_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN37_PAD_DRIVER_V 0x1 +#define GPIO_PIN37_PAD_DRIVER_S 2 + +#define GPIO_PIN38_REG (DR_REG_GPIO_BASE + 0x0120) + +/* GPIO_PIN38_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN38_INT_ENA 0x0000001F +#define GPIO_PIN38_INT_ENA_M ((GPIO_PIN38_INT_ENA_V)<<(GPIO_PIN38_INT_ENA_S)) +#define GPIO_PIN38_INT_ENA_V 0x1F +#define GPIO_PIN38_INT_ENA_S 13 + +/* GPIO_PIN38_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN38_CONFIG 0x00000003 +#define GPIO_PIN38_CONFIG_M ((GPIO_PIN38_CONFIG_V)<<(GPIO_PIN38_CONFIG_S)) +#define GPIO_PIN38_CONFIG_V 0x3 +#define GPIO_PIN38_CONFIG_S 11 + +/* GPIO_PIN38_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN38_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN38_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN38_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN38_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN38_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN38_INT_TYPE 0x00000007 +#define GPIO_PIN38_INT_TYPE_M ((GPIO_PIN38_INT_TYPE_V)<<(GPIO_PIN38_INT_TYPE_S)) +#define GPIO_PIN38_INT_TYPE_V 0x7 +#define GPIO_PIN38_INT_TYPE_S 7 + +/* GPIO_PIN38_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN38_PAD_DRIVER (BIT(2)) +#define GPIO_PIN38_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN38_PAD_DRIVER_V 0x1 +#define GPIO_PIN38_PAD_DRIVER_S 2 + +#define GPIO_PIN39_REG (DR_REG_GPIO_BASE + 0x0124) + +/* GPIO_PIN39_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt + enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ + +#define GPIO_PIN39_INT_ENA 0x0000001F +#define GPIO_PIN39_INT_ENA_M ((GPIO_PIN39_INT_ENA_V)<<(GPIO_PIN39_INT_ENA_S)) +#define GPIO_PIN39_INT_ENA_V 0x1F +#define GPIO_PIN39_INT_ENA_S 13 + +/* GPIO_PIN39_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ +/* Description: NA */ + +#define GPIO_PIN39_CONFIG 0x00000003 +#define GPIO_PIN39_CONFIG_M ((GPIO_PIN39_CONFIG_V)<<(GPIO_PIN39_CONFIG_S)) +#define GPIO_PIN39_CONFIG_V 0x3 +#define GPIO_PIN39_CONFIG_S 11 + +/* GPIO_PIN39_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ +/* Description: GPIO wake up enable only available in light sleep */ + +#define GPIO_PIN39_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN39_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN39_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN39_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN39_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ +/* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + +#define GPIO_PIN39_INT_TYPE 0x00000007 +#define GPIO_PIN39_INT_TYPE_M ((GPIO_PIN39_INT_TYPE_V)<<(GPIO_PIN39_INT_TYPE_S)) +#define GPIO_PIN39_INT_TYPE_V 0x7 +#define GPIO_PIN39_INT_TYPE_S 7 + +/* GPIO_PIN39_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ +/* Description: if set to 0: normal output if set to 1: open drain */ + +#define GPIO_PIN39_PAD_DRIVER (BIT(2)) +#define GPIO_PIN39_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN39_PAD_DRIVER_V 0x1 +#define GPIO_PIN39_PAD_DRIVER_S 2 + +#define GPIO_cali_conf_REG (DR_REG_GPIO_BASE + 0x0128) + +/* GPIO_CALI_START : R/W ;bitpos:[31] ;default: x ; */ +/* Description: */ + +#define GPIO_CALI_START (BIT(31)) +#define GPIO_CALI_START_M (BIT(31)) +#define GPIO_CALI_START_V 0x1 +#define GPIO_CALI_START_S 31 + +/* GPIO_CALI_RTC_MAX : R/W ;bitpos:[9:0] ;default: x ; */ +/* Description: */ + +#define GPIO_CALI_RTC_MAX 0x000003FF +#define GPIO_CALI_RTC_MAX_M ((GPIO_CALI_RTC_MAX_V)<<(GPIO_CALI_RTC_MAX_S)) +#define GPIO_CALI_RTC_MAX_V 0x3FF +#define GPIO_CALI_RTC_MAX_S 0 + +#define GPIO_cali_data_REG (DR_REG_GPIO_BASE + 0x012c) + +/* GPIO_CALI_RDY_SYNC2 : RO ;bitpos:[31] ;default: ; */ +/* Description: */ + +#define GPIO_CALI_RDY_SYNC2 (BIT(31)) +#define GPIO_CALI_RDY_SYNC2_M (BIT(31)) +#define GPIO_CALI_RDY_SYNC2_V 0x1 +#define GPIO_CALI_RDY_SYNC2_S 31 + +/* GPIO_CALI_RDY_REAL : RO ;bitpos:[30] ;default: ; */ +/* Description: */ + +#define GPIO_CALI_RDY_REAL (BIT(30)) +#define GPIO_CALI_RDY_REAL_M (BIT(30)) +#define GPIO_CALI_RDY_REAL_V 0x1 +#define GPIO_CALI_RDY_REAL_S 30 + +/* GPIO_CALI_VALUE_SYNC2 : RO ;bitpos:[19:0] ;default: ; */ +/* Description: */ + +#define GPIO_CALI_VALUE_SYNC2 0x000FFFFF +#define GPIO_CALI_VALUE_SYNC2_M ((GPIO_CALI_VALUE_SYNC2_V)<<(GPIO_CALI_VALUE_SYNC2_S)) +#define GPIO_CALI_VALUE_SYNC2_V 0xFFFFF +#define GPIO_CALI_VALUE_SYNC2_S 0 + +#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0130) + +/* GPIO_SIG0_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG0_IN_SEL (BIT(7)) +#define GPIO_SIG0_IN_SEL_M (BIT(7)) +#define GPIO_SIG0_IN_SEL_V 0x1 +#define GPIO_SIG0_IN_SEL_S 7 + +/* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC0_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC0_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC0_IN_INV_SEL_V 0x1 +#define GPIO_FUNC0_IN_INV_SEL_S 6 + +/* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC0_IN_SEL 0x0000003F +#define GPIO_FUNC0_IN_SEL_M ((GPIO_FUNC0_IN_SEL_V)<<(GPIO_FUNC0_IN_SEL_S)) +#define GPIO_FUNC0_IN_SEL_V 0x3F +#define GPIO_FUNC0_IN_SEL_S 0 + +#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0134) + +/* GPIO_SIG1_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG1_IN_SEL (BIT(7)) +#define GPIO_SIG1_IN_SEL_M (BIT(7)) +#define GPIO_SIG1_IN_SEL_V 0x1 +#define GPIO_SIG1_IN_SEL_S 7 + +/* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC1_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC1_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC1_IN_INV_SEL_V 0x1 +#define GPIO_FUNC1_IN_INV_SEL_S 6 + +/* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC1_IN_SEL 0x0000003F +#define GPIO_FUNC1_IN_SEL_M ((GPIO_FUNC1_IN_SEL_V)<<(GPIO_FUNC1_IN_SEL_S)) +#define GPIO_FUNC1_IN_SEL_V 0x3F +#define GPIO_FUNC1_IN_SEL_S 0 + +#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0138) + +/* GPIO_SIG2_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG2_IN_SEL (BIT(7)) +#define GPIO_SIG2_IN_SEL_M (BIT(7)) +#define GPIO_SIG2_IN_SEL_V 0x1 +#define GPIO_SIG2_IN_SEL_S 7 + +/* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC2_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC2_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC2_IN_INV_SEL_V 0x1 +#define GPIO_FUNC2_IN_INV_SEL_S 6 + +/* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC2_IN_SEL 0x0000003F +#define GPIO_FUNC2_IN_SEL_M ((GPIO_FUNC2_IN_SEL_V)<<(GPIO_FUNC2_IN_SEL_S)) +#define GPIO_FUNC2_IN_SEL_V 0x3F +#define GPIO_FUNC2_IN_SEL_S 0 + +#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x013c) + +/* GPIO_SIG3_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG3_IN_SEL (BIT(7)) +#define GPIO_SIG3_IN_SEL_M (BIT(7)) +#define GPIO_SIG3_IN_SEL_V 0x1 +#define GPIO_SIG3_IN_SEL_S 7 + +/* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC3_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC3_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC3_IN_INV_SEL_V 0x1 +#define GPIO_FUNC3_IN_INV_SEL_S 6 + +/* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC3_IN_SEL 0x0000003F +#define GPIO_FUNC3_IN_SEL_M ((GPIO_FUNC3_IN_SEL_V)<<(GPIO_FUNC3_IN_SEL_S)) +#define GPIO_FUNC3_IN_SEL_V 0x3F +#define GPIO_FUNC3_IN_SEL_S 0 + +#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0140) + +/* GPIO_SIG4_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG4_IN_SEL (BIT(7)) +#define GPIO_SIG4_IN_SEL_M (BIT(7)) +#define GPIO_SIG4_IN_SEL_V 0x1 +#define GPIO_SIG4_IN_SEL_S 7 + +/* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC4_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC4_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC4_IN_INV_SEL_V 0x1 +#define GPIO_FUNC4_IN_INV_SEL_S 6 + +/* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC4_IN_SEL 0x0000003F +#define GPIO_FUNC4_IN_SEL_M ((GPIO_FUNC4_IN_SEL_V)<<(GPIO_FUNC4_IN_SEL_S)) +#define GPIO_FUNC4_IN_SEL_V 0x3F +#define GPIO_FUNC4_IN_SEL_S 0 + +#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0144) + +/* GPIO_SIG5_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG5_IN_SEL (BIT(7)) +#define GPIO_SIG5_IN_SEL_M (BIT(7)) +#define GPIO_SIG5_IN_SEL_V 0x1 +#define GPIO_SIG5_IN_SEL_S 7 + +/* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC5_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC5_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC5_IN_INV_SEL_V 0x1 +#define GPIO_FUNC5_IN_INV_SEL_S 6 + +/* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC5_IN_SEL 0x0000003F +#define GPIO_FUNC5_IN_SEL_M ((GPIO_FUNC5_IN_SEL_V)<<(GPIO_FUNC5_IN_SEL_S)) +#define GPIO_FUNC5_IN_SEL_V 0x3F +#define GPIO_FUNC5_IN_SEL_S 0 + +#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0148) + +/* GPIO_SIG6_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG6_IN_SEL (BIT(7)) +#define GPIO_SIG6_IN_SEL_M (BIT(7)) +#define GPIO_SIG6_IN_SEL_V 0x1 +#define GPIO_SIG6_IN_SEL_S 7 + +/* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC6_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC6_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC6_IN_INV_SEL_V 0x1 +#define GPIO_FUNC6_IN_INV_SEL_S 6 + +/* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC6_IN_SEL 0x0000003F +#define GPIO_FUNC6_IN_SEL_M ((GPIO_FUNC6_IN_SEL_V)<<(GPIO_FUNC6_IN_SEL_S)) +#define GPIO_FUNC6_IN_SEL_V 0x3F +#define GPIO_FUNC6_IN_SEL_S 0 + +#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x014c) + +/* GPIO_SIG7_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG7_IN_SEL (BIT(7)) +#define GPIO_SIG7_IN_SEL_M (BIT(7)) +#define GPIO_SIG7_IN_SEL_V 0x1 +#define GPIO_SIG7_IN_SEL_S 7 + +/* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC7_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC7_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC7_IN_INV_SEL_V 0x1 +#define GPIO_FUNC7_IN_INV_SEL_S 6 + +/* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC7_IN_SEL 0x0000003F +#define GPIO_FUNC7_IN_SEL_M ((GPIO_FUNC7_IN_SEL_V)<<(GPIO_FUNC7_IN_SEL_S)) +#define GPIO_FUNC7_IN_SEL_V 0x3F +#define GPIO_FUNC7_IN_SEL_S 0 + +#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0150) + +/* GPIO_SIG8_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG8_IN_SEL (BIT(7)) +#define GPIO_SIG8_IN_SEL_M (BIT(7)) +#define GPIO_SIG8_IN_SEL_V 0x1 +#define GPIO_SIG8_IN_SEL_S 7 + +/* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC8_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC8_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC8_IN_INV_SEL_V 0x1 +#define GPIO_FUNC8_IN_INV_SEL_S 6 + +/* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC8_IN_SEL 0x0000003F +#define GPIO_FUNC8_IN_SEL_M ((GPIO_FUNC8_IN_SEL_V)<<(GPIO_FUNC8_IN_SEL_S)) +#define GPIO_FUNC8_IN_SEL_V 0x3F +#define GPIO_FUNC8_IN_SEL_S 0 + +#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0154) + +/* GPIO_SIG9_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG9_IN_SEL (BIT(7)) +#define GPIO_SIG9_IN_SEL_M (BIT(7)) +#define GPIO_SIG9_IN_SEL_V 0x1 +#define GPIO_SIG9_IN_SEL_S 7 + +/* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC9_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC9_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC9_IN_INV_SEL_V 0x1 +#define GPIO_FUNC9_IN_INV_SEL_S 6 + +/* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC9_IN_SEL 0x0000003F +#define GPIO_FUNC9_IN_SEL_M ((GPIO_FUNC9_IN_SEL_V)<<(GPIO_FUNC9_IN_SEL_S)) +#define GPIO_FUNC9_IN_SEL_V 0x3F +#define GPIO_FUNC9_IN_SEL_S 0 + +#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0158) + +/* GPIO_SIG10_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG10_IN_SEL (BIT(7)) +#define GPIO_SIG10_IN_SEL_M (BIT(7)) +#define GPIO_SIG10_IN_SEL_V 0x1 +#define GPIO_SIG10_IN_SEL_S 7 + +/* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC10_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC10_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC10_IN_INV_SEL_V 0x1 +#define GPIO_FUNC10_IN_INV_SEL_S 6 + +/* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC10_IN_SEL 0x0000003F +#define GPIO_FUNC10_IN_SEL_M ((GPIO_FUNC10_IN_SEL_V)<<(GPIO_FUNC10_IN_SEL_S)) +#define GPIO_FUNC10_IN_SEL_V 0x3F +#define GPIO_FUNC10_IN_SEL_S 0 + +#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x015c) + +/* GPIO_SIG11_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG11_IN_SEL (BIT(7)) +#define GPIO_SIG11_IN_SEL_M (BIT(7)) +#define GPIO_SIG11_IN_SEL_V 0x1 +#define GPIO_SIG11_IN_SEL_S 7 + +/* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC11_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC11_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC11_IN_INV_SEL_V 0x1 +#define GPIO_FUNC11_IN_INV_SEL_S 6 + +/* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC11_IN_SEL 0x0000003F +#define GPIO_FUNC11_IN_SEL_M ((GPIO_FUNC11_IN_SEL_V)<<(GPIO_FUNC11_IN_SEL_S)) +#define GPIO_FUNC11_IN_SEL_V 0x3F +#define GPIO_FUNC11_IN_SEL_S 0 + +#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0160) + +/* GPIO_SIG12_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG12_IN_SEL (BIT(7)) +#define GPIO_SIG12_IN_SEL_M (BIT(7)) +#define GPIO_SIG12_IN_SEL_V 0x1 +#define GPIO_SIG12_IN_SEL_S 7 + +/* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC12_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC12_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC12_IN_INV_SEL_V 0x1 +#define GPIO_FUNC12_IN_INV_SEL_S 6 + +/* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC12_IN_SEL 0x0000003F +#define GPIO_FUNC12_IN_SEL_M ((GPIO_FUNC12_IN_SEL_V)<<(GPIO_FUNC12_IN_SEL_S)) +#define GPIO_FUNC12_IN_SEL_V 0x3F +#define GPIO_FUNC12_IN_SEL_S 0 + +#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0164) + +/* GPIO_SIG13_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG13_IN_SEL (BIT(7)) +#define GPIO_SIG13_IN_SEL_M (BIT(7)) +#define GPIO_SIG13_IN_SEL_V 0x1 +#define GPIO_SIG13_IN_SEL_S 7 + +/* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC13_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC13_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC13_IN_INV_SEL_V 0x1 +#define GPIO_FUNC13_IN_INV_SEL_S 6 + +/* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC13_IN_SEL 0x0000003F +#define GPIO_FUNC13_IN_SEL_M ((GPIO_FUNC13_IN_SEL_V)<<(GPIO_FUNC13_IN_SEL_S)) +#define GPIO_FUNC13_IN_SEL_V 0x3F +#define GPIO_FUNC13_IN_SEL_S 0 + +#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0168) + +/* GPIO_SIG14_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG14_IN_SEL (BIT(7)) +#define GPIO_SIG14_IN_SEL_M (BIT(7)) +#define GPIO_SIG14_IN_SEL_V 0x1 +#define GPIO_SIG14_IN_SEL_S 7 + +/* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC14_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC14_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC14_IN_INV_SEL_V 0x1 +#define GPIO_FUNC14_IN_INV_SEL_S 6 + +/* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC14_IN_SEL 0x0000003F +#define GPIO_FUNC14_IN_SEL_M ((GPIO_FUNC14_IN_SEL_V)<<(GPIO_FUNC14_IN_SEL_S)) +#define GPIO_FUNC14_IN_SEL_V 0x3F +#define GPIO_FUNC14_IN_SEL_S 0 + +#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x016c) + +/* GPIO_SIG15_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG15_IN_SEL (BIT(7)) +#define GPIO_SIG15_IN_SEL_M (BIT(7)) +#define GPIO_SIG15_IN_SEL_V 0x1 +#define GPIO_SIG15_IN_SEL_S 7 + +/* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC15_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC15_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC15_IN_INV_SEL_V 0x1 +#define GPIO_FUNC15_IN_INV_SEL_S 6 + +/* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC15_IN_SEL 0x0000003F +#define GPIO_FUNC15_IN_SEL_M ((GPIO_FUNC15_IN_SEL_V)<<(GPIO_FUNC15_IN_SEL_S)) +#define GPIO_FUNC15_IN_SEL_V 0x3F +#define GPIO_FUNC15_IN_SEL_S 0 + +#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0170) + +/* GPIO_SIG16_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG16_IN_SEL (BIT(7)) +#define GPIO_SIG16_IN_SEL_M (BIT(7)) +#define GPIO_SIG16_IN_SEL_V 0x1 +#define GPIO_SIG16_IN_SEL_S 7 + +/* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC16_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC16_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC16_IN_INV_SEL_V 0x1 +#define GPIO_FUNC16_IN_INV_SEL_S 6 + +/* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC16_IN_SEL 0x0000003F +#define GPIO_FUNC16_IN_SEL_M ((GPIO_FUNC16_IN_SEL_V)<<(GPIO_FUNC16_IN_SEL_S)) +#define GPIO_FUNC16_IN_SEL_V 0x3F +#define GPIO_FUNC16_IN_SEL_S 0 + +#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0174) + +/* GPIO_SIG17_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG17_IN_SEL (BIT(7)) +#define GPIO_SIG17_IN_SEL_M (BIT(7)) +#define GPIO_SIG17_IN_SEL_V 0x1 +#define GPIO_SIG17_IN_SEL_S 7 + +/* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC17_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC17_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC17_IN_INV_SEL_V 0x1 +#define GPIO_FUNC17_IN_INV_SEL_S 6 + +/* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC17_IN_SEL 0x0000003F +#define GPIO_FUNC17_IN_SEL_M ((GPIO_FUNC17_IN_SEL_V)<<(GPIO_FUNC17_IN_SEL_S)) +#define GPIO_FUNC17_IN_SEL_V 0x3F +#define GPIO_FUNC17_IN_SEL_S 0 + +#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0178) + +/* GPIO_SIG18_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG18_IN_SEL (BIT(7)) +#define GPIO_SIG18_IN_SEL_M (BIT(7)) +#define GPIO_SIG18_IN_SEL_V 0x1 +#define GPIO_SIG18_IN_SEL_S 7 + +/* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC18_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC18_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC18_IN_INV_SEL_V 0x1 +#define GPIO_FUNC18_IN_INV_SEL_S 6 + +/* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC18_IN_SEL 0x0000003F +#define GPIO_FUNC18_IN_SEL_M ((GPIO_FUNC18_IN_SEL_V)<<(GPIO_FUNC18_IN_SEL_S)) +#define GPIO_FUNC18_IN_SEL_V 0x3F +#define GPIO_FUNC18_IN_SEL_S 0 + +#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x017c) + +/* GPIO_SIG19_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG19_IN_SEL (BIT(7)) +#define GPIO_SIG19_IN_SEL_M (BIT(7)) +#define GPIO_SIG19_IN_SEL_V 0x1 +#define GPIO_SIG19_IN_SEL_S 7 + +/* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC19_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC19_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC19_IN_INV_SEL_V 0x1 +#define GPIO_FUNC19_IN_INV_SEL_S 6 + +/* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC19_IN_SEL 0x0000003F +#define GPIO_FUNC19_IN_SEL_M ((GPIO_FUNC19_IN_SEL_V)<<(GPIO_FUNC19_IN_SEL_S)) +#define GPIO_FUNC19_IN_SEL_V 0x3F +#define GPIO_FUNC19_IN_SEL_S 0 + +#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0180) + +/* GPIO_SIG20_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG20_IN_SEL (BIT(7)) +#define GPIO_SIG20_IN_SEL_M (BIT(7)) +#define GPIO_SIG20_IN_SEL_V 0x1 +#define GPIO_SIG20_IN_SEL_S 7 + +/* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC20_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC20_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC20_IN_INV_SEL_V 0x1 +#define GPIO_FUNC20_IN_INV_SEL_S 6 + +/* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC20_IN_SEL 0x0000003F +#define GPIO_FUNC20_IN_SEL_M ((GPIO_FUNC20_IN_SEL_V)<<(GPIO_FUNC20_IN_SEL_S)) +#define GPIO_FUNC20_IN_SEL_V 0x3F +#define GPIO_FUNC20_IN_SEL_S 0 + +#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0184) + +/* GPIO_SIG21_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG21_IN_SEL (BIT(7)) +#define GPIO_SIG21_IN_SEL_M (BIT(7)) +#define GPIO_SIG21_IN_SEL_V 0x1 +#define GPIO_SIG21_IN_SEL_S 7 + +/* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC21_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC21_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC21_IN_INV_SEL_V 0x1 +#define GPIO_FUNC21_IN_INV_SEL_S 6 + +/* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC21_IN_SEL 0x0000003F +#define GPIO_FUNC21_IN_SEL_M ((GPIO_FUNC21_IN_SEL_V)<<(GPIO_FUNC21_IN_SEL_S)) +#define GPIO_FUNC21_IN_SEL_V 0x3F +#define GPIO_FUNC21_IN_SEL_S 0 + +#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0188) + +/* GPIO_SIG22_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG22_IN_SEL (BIT(7)) +#define GPIO_SIG22_IN_SEL_M (BIT(7)) +#define GPIO_SIG22_IN_SEL_V 0x1 +#define GPIO_SIG22_IN_SEL_S 7 + +/* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC22_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC22_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC22_IN_INV_SEL_V 0x1 +#define GPIO_FUNC22_IN_INV_SEL_S 6 + +/* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC22_IN_SEL 0x0000003F +#define GPIO_FUNC22_IN_SEL_M ((GPIO_FUNC22_IN_SEL_V)<<(GPIO_FUNC22_IN_SEL_S)) +#define GPIO_FUNC22_IN_SEL_V 0x3F +#define GPIO_FUNC22_IN_SEL_S 0 + +#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x018c) + +/* GPIO_SIG23_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG23_IN_SEL (BIT(7)) +#define GPIO_SIG23_IN_SEL_M (BIT(7)) +#define GPIO_SIG23_IN_SEL_V 0x1 +#define GPIO_SIG23_IN_SEL_S 7 + +/* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC23_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC23_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC23_IN_INV_SEL_V 0x1 +#define GPIO_FUNC23_IN_INV_SEL_S 6 + +/* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC23_IN_SEL 0x0000003F +#define GPIO_FUNC23_IN_SEL_M ((GPIO_FUNC23_IN_SEL_V)<<(GPIO_FUNC23_IN_SEL_S)) +#define GPIO_FUNC23_IN_SEL_V 0x3F +#define GPIO_FUNC23_IN_SEL_S 0 + +#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0190) + +/* GPIO_SIG24_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG24_IN_SEL (BIT(7)) +#define GPIO_SIG24_IN_SEL_M (BIT(7)) +#define GPIO_SIG24_IN_SEL_V 0x1 +#define GPIO_SIG24_IN_SEL_S 7 + +/* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC24_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC24_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC24_IN_INV_SEL_V 0x1 +#define GPIO_FUNC24_IN_INV_SEL_S 6 + +/* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC24_IN_SEL 0x0000003F +#define GPIO_FUNC24_IN_SEL_M ((GPIO_FUNC24_IN_SEL_V)<<(GPIO_FUNC24_IN_SEL_S)) +#define GPIO_FUNC24_IN_SEL_V 0x3F +#define GPIO_FUNC24_IN_SEL_S 0 + +#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0194) + +/* GPIO_SIG25_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG25_IN_SEL (BIT(7)) +#define GPIO_SIG25_IN_SEL_M (BIT(7)) +#define GPIO_SIG25_IN_SEL_V 0x1 +#define GPIO_SIG25_IN_SEL_S 7 + +/* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC25_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC25_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC25_IN_INV_SEL_V 0x1 +#define GPIO_FUNC25_IN_INV_SEL_S 6 + +/* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC25_IN_SEL 0x0000003F +#define GPIO_FUNC25_IN_SEL_M ((GPIO_FUNC25_IN_SEL_V)<<(GPIO_FUNC25_IN_SEL_S)) +#define GPIO_FUNC25_IN_SEL_V 0x3F +#define GPIO_FUNC25_IN_SEL_S 0 + +#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0198) + +/* GPIO_SIG26_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG26_IN_SEL (BIT(7)) +#define GPIO_SIG26_IN_SEL_M (BIT(7)) +#define GPIO_SIG26_IN_SEL_V 0x1 +#define GPIO_SIG26_IN_SEL_S 7 + +/* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC26_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC26_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC26_IN_INV_SEL_V 0x1 +#define GPIO_FUNC26_IN_INV_SEL_S 6 + +/* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC26_IN_SEL 0x0000003F +#define GPIO_FUNC26_IN_SEL_M ((GPIO_FUNC26_IN_SEL_V)<<(GPIO_FUNC26_IN_SEL_S)) +#define GPIO_FUNC26_IN_SEL_V 0x3F +#define GPIO_FUNC26_IN_SEL_S 0 + +#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x019c) + +/* GPIO_SIG27_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG27_IN_SEL (BIT(7)) +#define GPIO_SIG27_IN_SEL_M (BIT(7)) +#define GPIO_SIG27_IN_SEL_V 0x1 +#define GPIO_SIG27_IN_SEL_S 7 + +/* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC27_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC27_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC27_IN_INV_SEL_V 0x1 +#define GPIO_FUNC27_IN_INV_SEL_S 6 + +/* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC27_IN_SEL 0x0000003F +#define GPIO_FUNC27_IN_SEL_M ((GPIO_FUNC27_IN_SEL_V)<<(GPIO_FUNC27_IN_SEL_S)) +#define GPIO_FUNC27_IN_SEL_V 0x3F +#define GPIO_FUNC27_IN_SEL_S 0 + +#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01a0) + +/* GPIO_SIG28_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG28_IN_SEL (BIT(7)) +#define GPIO_SIG28_IN_SEL_M (BIT(7)) +#define GPIO_SIG28_IN_SEL_V 0x1 +#define GPIO_SIG28_IN_SEL_S 7 + +/* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC28_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC28_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC28_IN_INV_SEL_V 0x1 +#define GPIO_FUNC28_IN_INV_SEL_S 6 + +/* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC28_IN_SEL 0x0000003F +#define GPIO_FUNC28_IN_SEL_M ((GPIO_FUNC28_IN_SEL_V)<<(GPIO_FUNC28_IN_SEL_S)) +#define GPIO_FUNC28_IN_SEL_V 0x3F +#define GPIO_FUNC28_IN_SEL_S 0 + +#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01a4) + +/* GPIO_SIG29_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG29_IN_SEL (BIT(7)) +#define GPIO_SIG29_IN_SEL_M (BIT(7)) +#define GPIO_SIG29_IN_SEL_V 0x1 +#define GPIO_SIG29_IN_SEL_S 7 + +/* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC29_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC29_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC29_IN_INV_SEL_V 0x1 +#define GPIO_FUNC29_IN_INV_SEL_S 6 + +/* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC29_IN_SEL 0x0000003F +#define GPIO_FUNC29_IN_SEL_M ((GPIO_FUNC29_IN_SEL_V)<<(GPIO_FUNC29_IN_SEL_S)) +#define GPIO_FUNC29_IN_SEL_V 0x3F +#define GPIO_FUNC29_IN_SEL_S 0 + +#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01a8) + +/* GPIO_SIG30_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG30_IN_SEL (BIT(7)) +#define GPIO_SIG30_IN_SEL_M (BIT(7)) +#define GPIO_SIG30_IN_SEL_V 0x1 +#define GPIO_SIG30_IN_SEL_S 7 + +/* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC30_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC30_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC30_IN_INV_SEL_V 0x1 +#define GPIO_FUNC30_IN_INV_SEL_S 6 + +/* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC30_IN_SEL 0x0000003F +#define GPIO_FUNC30_IN_SEL_M ((GPIO_FUNC30_IN_SEL_V)<<(GPIO_FUNC30_IN_SEL_S)) +#define GPIO_FUNC30_IN_SEL_V 0x3F +#define GPIO_FUNC30_IN_SEL_S 0 + +#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01ac) + +/* GPIO_SIG31_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG31_IN_SEL (BIT(7)) +#define GPIO_SIG31_IN_SEL_M (BIT(7)) +#define GPIO_SIG31_IN_SEL_V 0x1 +#define GPIO_SIG31_IN_SEL_S 7 + +/* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC31_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC31_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC31_IN_INV_SEL_V 0x1 +#define GPIO_FUNC31_IN_INV_SEL_S 6 + +/* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC31_IN_SEL 0x0000003F +#define GPIO_FUNC31_IN_SEL_M ((GPIO_FUNC31_IN_SEL_V)<<(GPIO_FUNC31_IN_SEL_S)) +#define GPIO_FUNC31_IN_SEL_V 0x3F +#define GPIO_FUNC31_IN_SEL_S 0 + +#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01b0) + +/* GPIO_SIG32_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG32_IN_SEL (BIT(7)) +#define GPIO_SIG32_IN_SEL_M (BIT(7)) +#define GPIO_SIG32_IN_SEL_V 0x1 +#define GPIO_SIG32_IN_SEL_S 7 + +/* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC32_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC32_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC32_IN_INV_SEL_V 0x1 +#define GPIO_FUNC32_IN_INV_SEL_S 6 + +/* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC32_IN_SEL 0x0000003F +#define GPIO_FUNC32_IN_SEL_M ((GPIO_FUNC32_IN_SEL_V)<<(GPIO_FUNC32_IN_SEL_S)) +#define GPIO_FUNC32_IN_SEL_V 0x3F +#define GPIO_FUNC32_IN_SEL_S 0 + +#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01b4) + +/* GPIO_SIG33_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG33_IN_SEL (BIT(7)) +#define GPIO_SIG33_IN_SEL_M (BIT(7)) +#define GPIO_SIG33_IN_SEL_V 0x1 +#define GPIO_SIG33_IN_SEL_S 7 + +/* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC33_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC33_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC33_IN_INV_SEL_V 0x1 +#define GPIO_FUNC33_IN_INV_SEL_S 6 + +/* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC33_IN_SEL 0x0000003F +#define GPIO_FUNC33_IN_SEL_M ((GPIO_FUNC33_IN_SEL_V)<<(GPIO_FUNC33_IN_SEL_S)) +#define GPIO_FUNC33_IN_SEL_V 0x3F +#define GPIO_FUNC33_IN_SEL_S 0 + +#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01b8) + +/* GPIO_SIG34_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG34_IN_SEL (BIT(7)) +#define GPIO_SIG34_IN_SEL_M (BIT(7)) +#define GPIO_SIG34_IN_SEL_V 0x1 +#define GPIO_SIG34_IN_SEL_S 7 + +/* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC34_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC34_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC34_IN_INV_SEL_V 0x1 +#define GPIO_FUNC34_IN_INV_SEL_S 6 + +/* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC34_IN_SEL 0x0000003F +#define GPIO_FUNC34_IN_SEL_M ((GPIO_FUNC34_IN_SEL_V)<<(GPIO_FUNC34_IN_SEL_S)) +#define GPIO_FUNC34_IN_SEL_V 0x3F +#define GPIO_FUNC34_IN_SEL_S 0 + +#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01bc) + +/* GPIO_SIG35_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG35_IN_SEL (BIT(7)) +#define GPIO_SIG35_IN_SEL_M (BIT(7)) +#define GPIO_SIG35_IN_SEL_V 0x1 +#define GPIO_SIG35_IN_SEL_S 7 + +/* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC35_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC35_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC35_IN_INV_SEL_V 0x1 +#define GPIO_FUNC35_IN_INV_SEL_S 6 + +/* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC35_IN_SEL 0x0000003F +#define GPIO_FUNC35_IN_SEL_M ((GPIO_FUNC35_IN_SEL_V)<<(GPIO_FUNC35_IN_SEL_S)) +#define GPIO_FUNC35_IN_SEL_V 0x3F +#define GPIO_FUNC35_IN_SEL_S 0 + +#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01c0) + +/* GPIO_SIG36_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG36_IN_SEL (BIT(7)) +#define GPIO_SIG36_IN_SEL_M (BIT(7)) +#define GPIO_SIG36_IN_SEL_V 0x1 +#define GPIO_SIG36_IN_SEL_S 7 + +/* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC36_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC36_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC36_IN_INV_SEL_V 0x1 +#define GPIO_FUNC36_IN_INV_SEL_S 6 + +/* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC36_IN_SEL 0x0000003F +#define GPIO_FUNC36_IN_SEL_M ((GPIO_FUNC36_IN_SEL_V)<<(GPIO_FUNC36_IN_SEL_S)) +#define GPIO_FUNC36_IN_SEL_V 0x3F +#define GPIO_FUNC36_IN_SEL_S 0 + +#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01c4) + +/* GPIO_SIG37_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG37_IN_SEL (BIT(7)) +#define GPIO_SIG37_IN_SEL_M (BIT(7)) +#define GPIO_SIG37_IN_SEL_V 0x1 +#define GPIO_SIG37_IN_SEL_S 7 + +/* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC37_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC37_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC37_IN_INV_SEL_V 0x1 +#define GPIO_FUNC37_IN_INV_SEL_S 6 + +/* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC37_IN_SEL 0x0000003F +#define GPIO_FUNC37_IN_SEL_M ((GPIO_FUNC37_IN_SEL_V)<<(GPIO_FUNC37_IN_SEL_S)) +#define GPIO_FUNC37_IN_SEL_V 0x3F +#define GPIO_FUNC37_IN_SEL_S 0 + +#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01c8) + +/* GPIO_SIG38_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG38_IN_SEL (BIT(7)) +#define GPIO_SIG38_IN_SEL_M (BIT(7)) +#define GPIO_SIG38_IN_SEL_V 0x1 +#define GPIO_SIG38_IN_SEL_S 7 + +/* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC38_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC38_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC38_IN_INV_SEL_V 0x1 +#define GPIO_FUNC38_IN_INV_SEL_S 6 + +/* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC38_IN_SEL 0x0000003F +#define GPIO_FUNC38_IN_SEL_M ((GPIO_FUNC38_IN_SEL_V)<<(GPIO_FUNC38_IN_SEL_S)) +#define GPIO_FUNC38_IN_SEL_V 0x3F +#define GPIO_FUNC38_IN_SEL_S 0 + +#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01cc) + +/* GPIO_SIG39_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG39_IN_SEL (BIT(7)) +#define GPIO_SIG39_IN_SEL_M (BIT(7)) +#define GPIO_SIG39_IN_SEL_V 0x1 +#define GPIO_SIG39_IN_SEL_S 7 + +/* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC39_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC39_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC39_IN_INV_SEL_V 0x1 +#define GPIO_FUNC39_IN_INV_SEL_S 6 + +/* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC39_IN_SEL 0x0000003F +#define GPIO_FUNC39_IN_SEL_M ((GPIO_FUNC39_IN_SEL_V)<<(GPIO_FUNC39_IN_SEL_S)) +#define GPIO_FUNC39_IN_SEL_V 0x3F +#define GPIO_FUNC39_IN_SEL_S 0 + +#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01d0) + +/* GPIO_SIG40_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG40_IN_SEL (BIT(7)) +#define GPIO_SIG40_IN_SEL_M (BIT(7)) +#define GPIO_SIG40_IN_SEL_V 0x1 +#define GPIO_SIG40_IN_SEL_S 7 + +/* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC40_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC40_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC40_IN_INV_SEL_V 0x1 +#define GPIO_FUNC40_IN_INV_SEL_S 6 + +/* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC40_IN_SEL 0x0000003F +#define GPIO_FUNC40_IN_SEL_M ((GPIO_FUNC40_IN_SEL_V)<<(GPIO_FUNC40_IN_SEL_S)) +#define GPIO_FUNC40_IN_SEL_V 0x3F +#define GPIO_FUNC40_IN_SEL_S 0 + +#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01d4) + +/* GPIO_SIG41_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG41_IN_SEL (BIT(7)) +#define GPIO_SIG41_IN_SEL_M (BIT(7)) +#define GPIO_SIG41_IN_SEL_V 0x1 +#define GPIO_SIG41_IN_SEL_S 7 + +/* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC41_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC41_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC41_IN_INV_SEL_V 0x1 +#define GPIO_FUNC41_IN_INV_SEL_S 6 + +/* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC41_IN_SEL 0x0000003F +#define GPIO_FUNC41_IN_SEL_M ((GPIO_FUNC41_IN_SEL_V)<<(GPIO_FUNC41_IN_SEL_S)) +#define GPIO_FUNC41_IN_SEL_V 0x3F +#define GPIO_FUNC41_IN_SEL_S 0 + +#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01d8) + +/* GPIO_SIG42_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG42_IN_SEL (BIT(7)) +#define GPIO_SIG42_IN_SEL_M (BIT(7)) +#define GPIO_SIG42_IN_SEL_V 0x1 +#define GPIO_SIG42_IN_SEL_S 7 + +/* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC42_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC42_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC42_IN_INV_SEL_V 0x1 +#define GPIO_FUNC42_IN_INV_SEL_S 6 + +/* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC42_IN_SEL 0x0000003F +#define GPIO_FUNC42_IN_SEL_M ((GPIO_FUNC42_IN_SEL_V)<<(GPIO_FUNC42_IN_SEL_S)) +#define GPIO_FUNC42_IN_SEL_V 0x3F +#define GPIO_FUNC42_IN_SEL_S 0 + +#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01dc) + +/* GPIO_SIG43_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG43_IN_SEL (BIT(7)) +#define GPIO_SIG43_IN_SEL_M (BIT(7)) +#define GPIO_SIG43_IN_SEL_V 0x1 +#define GPIO_SIG43_IN_SEL_S 7 + +/* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC43_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC43_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC43_IN_INV_SEL_V 0x1 +#define GPIO_FUNC43_IN_INV_SEL_S 6 + +/* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC43_IN_SEL 0x0000003F +#define GPIO_FUNC43_IN_SEL_M ((GPIO_FUNC43_IN_SEL_V)<<(GPIO_FUNC43_IN_SEL_S)) +#define GPIO_FUNC43_IN_SEL_V 0x3F +#define GPIO_FUNC43_IN_SEL_S 0 + +#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01e0) + +/* GPIO_SIG44_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG44_IN_SEL (BIT(7)) +#define GPIO_SIG44_IN_SEL_M (BIT(7)) +#define GPIO_SIG44_IN_SEL_V 0x1 +#define GPIO_SIG44_IN_SEL_S 7 + +/* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC44_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC44_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC44_IN_INV_SEL_V 0x1 +#define GPIO_FUNC44_IN_INV_SEL_S 6 + +/* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC44_IN_SEL 0x0000003F +#define GPIO_FUNC44_IN_SEL_M ((GPIO_FUNC44_IN_SEL_V)<<(GPIO_FUNC44_IN_SEL_S)) +#define GPIO_FUNC44_IN_SEL_V 0x3F +#define GPIO_FUNC44_IN_SEL_S 0 + +#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01e4) + +/* GPIO_SIG45_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG45_IN_SEL (BIT(7)) +#define GPIO_SIG45_IN_SEL_M (BIT(7)) +#define GPIO_SIG45_IN_SEL_V 0x1 +#define GPIO_SIG45_IN_SEL_S 7 + +/* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC45_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC45_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC45_IN_INV_SEL_V 0x1 +#define GPIO_FUNC45_IN_INV_SEL_S 6 + +/* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC45_IN_SEL 0x0000003F +#define GPIO_FUNC45_IN_SEL_M ((GPIO_FUNC45_IN_SEL_V)<<(GPIO_FUNC45_IN_SEL_S)) +#define GPIO_FUNC45_IN_SEL_V 0x3F +#define GPIO_FUNC45_IN_SEL_S 0 + +#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01e8) + +/* GPIO_SIG46_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG46_IN_SEL (BIT(7)) +#define GPIO_SIG46_IN_SEL_M (BIT(7)) +#define GPIO_SIG46_IN_SEL_V 0x1 +#define GPIO_SIG46_IN_SEL_S 7 + +/* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC46_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC46_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC46_IN_INV_SEL_V 0x1 +#define GPIO_FUNC46_IN_INV_SEL_S 6 + +/* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC46_IN_SEL 0x0000003F +#define GPIO_FUNC46_IN_SEL_M ((GPIO_FUNC46_IN_SEL_V)<<(GPIO_FUNC46_IN_SEL_S)) +#define GPIO_FUNC46_IN_SEL_V 0x3F +#define GPIO_FUNC46_IN_SEL_S 0 + +#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01ec) + +/* GPIO_SIG47_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG47_IN_SEL (BIT(7)) +#define GPIO_SIG47_IN_SEL_M (BIT(7)) +#define GPIO_SIG47_IN_SEL_V 0x1 +#define GPIO_SIG47_IN_SEL_S 7 + +/* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC47_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC47_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC47_IN_INV_SEL_V 0x1 +#define GPIO_FUNC47_IN_INV_SEL_S 6 + +/* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC47_IN_SEL 0x0000003F +#define GPIO_FUNC47_IN_SEL_M ((GPIO_FUNC47_IN_SEL_V)<<(GPIO_FUNC47_IN_SEL_S)) +#define GPIO_FUNC47_IN_SEL_V 0x3F +#define GPIO_FUNC47_IN_SEL_S 0 + +#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01f0) + +/* GPIO_SIG48_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG48_IN_SEL (BIT(7)) +#define GPIO_SIG48_IN_SEL_M (BIT(7)) +#define GPIO_SIG48_IN_SEL_V 0x1 +#define GPIO_SIG48_IN_SEL_S 7 + +/* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC48_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC48_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC48_IN_INV_SEL_V 0x1 +#define GPIO_FUNC48_IN_INV_SEL_S 6 + +/* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC48_IN_SEL 0x0000003F +#define GPIO_FUNC48_IN_SEL_M ((GPIO_FUNC48_IN_SEL_V)<<(GPIO_FUNC48_IN_SEL_S)) +#define GPIO_FUNC48_IN_SEL_V 0x3F +#define GPIO_FUNC48_IN_SEL_S 0 + +#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01f4) + +/* GPIO_SIG49_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG49_IN_SEL (BIT(7)) +#define GPIO_SIG49_IN_SEL_M (BIT(7)) +#define GPIO_SIG49_IN_SEL_V 0x1 +#define GPIO_SIG49_IN_SEL_S 7 + +/* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC49_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC49_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC49_IN_INV_SEL_V 0x1 +#define GPIO_FUNC49_IN_INV_SEL_S 6 + +/* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC49_IN_SEL 0x0000003F +#define GPIO_FUNC49_IN_SEL_M ((GPIO_FUNC49_IN_SEL_V)<<(GPIO_FUNC49_IN_SEL_S)) +#define GPIO_FUNC49_IN_SEL_V 0x3F +#define GPIO_FUNC49_IN_SEL_S 0 + +#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01f8) + +/* GPIO_SIG50_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG50_IN_SEL (BIT(7)) +#define GPIO_SIG50_IN_SEL_M (BIT(7)) +#define GPIO_SIG50_IN_SEL_V 0x1 +#define GPIO_SIG50_IN_SEL_S 7 + +/* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC50_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC50_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC50_IN_INV_SEL_V 0x1 +#define GPIO_FUNC50_IN_INV_SEL_S 6 + +/* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC50_IN_SEL 0x0000003F +#define GPIO_FUNC50_IN_SEL_M ((GPIO_FUNC50_IN_SEL_V)<<(GPIO_FUNC50_IN_SEL_S)) +#define GPIO_FUNC50_IN_SEL_V 0x3F +#define GPIO_FUNC50_IN_SEL_S 0 + +#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01fc) + +/* GPIO_SIG51_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG51_IN_SEL (BIT(7)) +#define GPIO_SIG51_IN_SEL_M (BIT(7)) +#define GPIO_SIG51_IN_SEL_V 0x1 +#define GPIO_SIG51_IN_SEL_S 7 + +/* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC51_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC51_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC51_IN_INV_SEL_V 0x1 +#define GPIO_FUNC51_IN_INV_SEL_S 6 + +/* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC51_IN_SEL 0x0000003F +#define GPIO_FUNC51_IN_SEL_M ((GPIO_FUNC51_IN_SEL_V)<<(GPIO_FUNC51_IN_SEL_S)) +#define GPIO_FUNC51_IN_SEL_V 0x3F +#define GPIO_FUNC51_IN_SEL_S 0 + +#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0200) + +/* GPIO_SIG52_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG52_IN_SEL (BIT(7)) +#define GPIO_SIG52_IN_SEL_M (BIT(7)) +#define GPIO_SIG52_IN_SEL_V 0x1 +#define GPIO_SIG52_IN_SEL_S 7 + +/* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC52_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC52_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC52_IN_INV_SEL_V 0x1 +#define GPIO_FUNC52_IN_INV_SEL_S 6 + +/* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC52_IN_SEL 0x0000003F +#define GPIO_FUNC52_IN_SEL_M ((GPIO_FUNC52_IN_SEL_V)<<(GPIO_FUNC52_IN_SEL_S)) +#define GPIO_FUNC52_IN_SEL_V 0x3F +#define GPIO_FUNC52_IN_SEL_S 0 + +#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0204) + +/* GPIO_SIG53_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG53_IN_SEL (BIT(7)) +#define GPIO_SIG53_IN_SEL_M (BIT(7)) +#define GPIO_SIG53_IN_SEL_V 0x1 +#define GPIO_SIG53_IN_SEL_S 7 + +/* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC53_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC53_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC53_IN_INV_SEL_V 0x1 +#define GPIO_FUNC53_IN_INV_SEL_S 6 + +/* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC53_IN_SEL 0x0000003F +#define GPIO_FUNC53_IN_SEL_M ((GPIO_FUNC53_IN_SEL_V)<<(GPIO_FUNC53_IN_SEL_S)) +#define GPIO_FUNC53_IN_SEL_V 0x3F +#define GPIO_FUNC53_IN_SEL_S 0 + +#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0208) + +/* GPIO_SIG54_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG54_IN_SEL (BIT(7)) +#define GPIO_SIG54_IN_SEL_M (BIT(7)) +#define GPIO_SIG54_IN_SEL_V 0x1 +#define GPIO_SIG54_IN_SEL_S 7 + +/* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC54_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC54_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC54_IN_INV_SEL_V 0x1 +#define GPIO_FUNC54_IN_INV_SEL_S 6 + +/* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC54_IN_SEL 0x0000003F +#define GPIO_FUNC54_IN_SEL_M ((GPIO_FUNC54_IN_SEL_V)<<(GPIO_FUNC54_IN_SEL_S)) +#define GPIO_FUNC54_IN_SEL_V 0x3F +#define GPIO_FUNC54_IN_SEL_S 0 + +#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x020c) + +/* GPIO_SIG55_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG55_IN_SEL (BIT(7)) +#define GPIO_SIG55_IN_SEL_M (BIT(7)) +#define GPIO_SIG55_IN_SEL_V 0x1 +#define GPIO_SIG55_IN_SEL_S 7 + +/* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC55_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC55_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC55_IN_INV_SEL_V 0x1 +#define GPIO_FUNC55_IN_INV_SEL_S 6 + +/* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC55_IN_SEL 0x0000003F +#define GPIO_FUNC55_IN_SEL_M ((GPIO_FUNC55_IN_SEL_V)<<(GPIO_FUNC55_IN_SEL_S)) +#define GPIO_FUNC55_IN_SEL_V 0x3F +#define GPIO_FUNC55_IN_SEL_S 0 + +#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0210) + +/* GPIO_SIG56_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG56_IN_SEL (BIT(7)) +#define GPIO_SIG56_IN_SEL_M (BIT(7)) +#define GPIO_SIG56_IN_SEL_V 0x1 +#define GPIO_SIG56_IN_SEL_S 7 + +/* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC56_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC56_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC56_IN_INV_SEL_V 0x1 +#define GPIO_FUNC56_IN_INV_SEL_S 6 + +/* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC56_IN_SEL 0x0000003F +#define GPIO_FUNC56_IN_SEL_M ((GPIO_FUNC56_IN_SEL_V)<<(GPIO_FUNC56_IN_SEL_S)) +#define GPIO_FUNC56_IN_SEL_V 0x3F +#define GPIO_FUNC56_IN_SEL_S 0 + +#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0214) + +/* GPIO_SIG57_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG57_IN_SEL (BIT(7)) +#define GPIO_SIG57_IN_SEL_M (BIT(7)) +#define GPIO_SIG57_IN_SEL_V 0x1 +#define GPIO_SIG57_IN_SEL_S 7 + +/* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC57_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC57_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC57_IN_INV_SEL_V 0x1 +#define GPIO_FUNC57_IN_INV_SEL_S 6 + +/* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC57_IN_SEL 0x0000003F +#define GPIO_FUNC57_IN_SEL_M ((GPIO_FUNC57_IN_SEL_V)<<(GPIO_FUNC57_IN_SEL_S)) +#define GPIO_FUNC57_IN_SEL_V 0x3F +#define GPIO_FUNC57_IN_SEL_S 0 + +#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0218) + +/* GPIO_SIG58_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG58_IN_SEL (BIT(7)) +#define GPIO_SIG58_IN_SEL_M (BIT(7)) +#define GPIO_SIG58_IN_SEL_V 0x1 +#define GPIO_SIG58_IN_SEL_S 7 + +/* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC58_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC58_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC58_IN_INV_SEL_V 0x1 +#define GPIO_FUNC58_IN_INV_SEL_S 6 + +/* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC58_IN_SEL 0x0000003F +#define GPIO_FUNC58_IN_SEL_M ((GPIO_FUNC58_IN_SEL_V)<<(GPIO_FUNC58_IN_SEL_S)) +#define GPIO_FUNC58_IN_SEL_V 0x3F +#define GPIO_FUNC58_IN_SEL_S 0 + +#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x021c) + +/* GPIO_SIG59_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG59_IN_SEL (BIT(7)) +#define GPIO_SIG59_IN_SEL_M (BIT(7)) +#define GPIO_SIG59_IN_SEL_V 0x1 +#define GPIO_SIG59_IN_SEL_S 7 + +/* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC59_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC59_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC59_IN_INV_SEL_V 0x1 +#define GPIO_FUNC59_IN_INV_SEL_S 6 + +/* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC59_IN_SEL 0x0000003F +#define GPIO_FUNC59_IN_SEL_M ((GPIO_FUNC59_IN_SEL_V)<<(GPIO_FUNC59_IN_SEL_S)) +#define GPIO_FUNC59_IN_SEL_V 0x3F +#define GPIO_FUNC59_IN_SEL_S 0 + +#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0220) + +/* GPIO_SIG60_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG60_IN_SEL (BIT(7)) +#define GPIO_SIG60_IN_SEL_M (BIT(7)) +#define GPIO_SIG60_IN_SEL_V 0x1 +#define GPIO_SIG60_IN_SEL_S 7 + +/* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC60_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC60_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC60_IN_INV_SEL_V 0x1 +#define GPIO_FUNC60_IN_INV_SEL_S 6 + +/* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC60_IN_SEL 0x0000003F +#define GPIO_FUNC60_IN_SEL_M ((GPIO_FUNC60_IN_SEL_V)<<(GPIO_FUNC60_IN_SEL_S)) +#define GPIO_FUNC60_IN_SEL_V 0x3F +#define GPIO_FUNC60_IN_SEL_S 0 + +#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0224) + +/* GPIO_SIG61_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG61_IN_SEL (BIT(7)) +#define GPIO_SIG61_IN_SEL_M (BIT(7)) +#define GPIO_SIG61_IN_SEL_V 0x1 +#define GPIO_SIG61_IN_SEL_S 7 + +/* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC61_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC61_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC61_IN_INV_SEL_V 0x1 +#define GPIO_FUNC61_IN_INV_SEL_S 6 + +/* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC61_IN_SEL 0x0000003F +#define GPIO_FUNC61_IN_SEL_M ((GPIO_FUNC61_IN_SEL_V)<<(GPIO_FUNC61_IN_SEL_S)) +#define GPIO_FUNC61_IN_SEL_V 0x3F +#define GPIO_FUNC61_IN_SEL_S 0 + +#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0228) + +/* GPIO_SIG62_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG62_IN_SEL (BIT(7)) +#define GPIO_SIG62_IN_SEL_M (BIT(7)) +#define GPIO_SIG62_IN_SEL_V 0x1 +#define GPIO_SIG62_IN_SEL_S 7 + +/* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC62_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC62_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC62_IN_INV_SEL_V 0x1 +#define GPIO_FUNC62_IN_INV_SEL_S 6 + +/* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC62_IN_SEL 0x0000003F +#define GPIO_FUNC62_IN_SEL_M ((GPIO_FUNC62_IN_SEL_V)<<(GPIO_FUNC62_IN_SEL_S)) +#define GPIO_FUNC62_IN_SEL_V 0x3F +#define GPIO_FUNC62_IN_SEL_S 0 + +#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x022c) + +/* GPIO_SIG63_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG63_IN_SEL (BIT(7)) +#define GPIO_SIG63_IN_SEL_M (BIT(7)) +#define GPIO_SIG63_IN_SEL_V 0x1 +#define GPIO_SIG63_IN_SEL_S 7 + +/* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC63_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC63_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC63_IN_INV_SEL_V 0x1 +#define GPIO_FUNC63_IN_INV_SEL_S 6 + +/* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC63_IN_SEL 0x0000003F +#define GPIO_FUNC63_IN_SEL_M ((GPIO_FUNC63_IN_SEL_V)<<(GPIO_FUNC63_IN_SEL_S)) +#define GPIO_FUNC63_IN_SEL_V 0x3F +#define GPIO_FUNC63_IN_SEL_S 0 + +#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0230) + +/* GPIO_SIG64_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG64_IN_SEL (BIT(7)) +#define GPIO_SIG64_IN_SEL_M (BIT(7)) +#define GPIO_SIG64_IN_SEL_V 0x1 +#define GPIO_SIG64_IN_SEL_S 7 + +/* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC64_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC64_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC64_IN_INV_SEL_V 0x1 +#define GPIO_FUNC64_IN_INV_SEL_S 6 + +/* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC64_IN_SEL 0x0000003F +#define GPIO_FUNC64_IN_SEL_M ((GPIO_FUNC64_IN_SEL_V)<<(GPIO_FUNC64_IN_SEL_S)) +#define GPIO_FUNC64_IN_SEL_V 0x3F +#define GPIO_FUNC64_IN_SEL_S 0 + +#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0234) + +/* GPIO_SIG65_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG65_IN_SEL (BIT(7)) +#define GPIO_SIG65_IN_SEL_M (BIT(7)) +#define GPIO_SIG65_IN_SEL_V 0x1 +#define GPIO_SIG65_IN_SEL_S 7 + +/* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC65_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC65_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC65_IN_INV_SEL_V 0x1 +#define GPIO_FUNC65_IN_INV_SEL_S 6 + +/* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC65_IN_SEL 0x0000003F +#define GPIO_FUNC65_IN_SEL_M ((GPIO_FUNC65_IN_SEL_V)<<(GPIO_FUNC65_IN_SEL_S)) +#define GPIO_FUNC65_IN_SEL_V 0x3F +#define GPIO_FUNC65_IN_SEL_S 0 + +#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0238) + +/* GPIO_SIG66_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG66_IN_SEL (BIT(7)) +#define GPIO_SIG66_IN_SEL_M (BIT(7)) +#define GPIO_SIG66_IN_SEL_V 0x1 +#define GPIO_SIG66_IN_SEL_S 7 + +/* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC66_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC66_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC66_IN_INV_SEL_V 0x1 +#define GPIO_FUNC66_IN_INV_SEL_S 6 + +/* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC66_IN_SEL 0x0000003F +#define GPIO_FUNC66_IN_SEL_M ((GPIO_FUNC66_IN_SEL_V)<<(GPIO_FUNC66_IN_SEL_S)) +#define GPIO_FUNC66_IN_SEL_V 0x3F +#define GPIO_FUNC66_IN_SEL_S 0 + +#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x023c) + +/* GPIO_SIG67_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG67_IN_SEL (BIT(7)) +#define GPIO_SIG67_IN_SEL_M (BIT(7)) +#define GPIO_SIG67_IN_SEL_V 0x1 +#define GPIO_SIG67_IN_SEL_S 7 + +/* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC67_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC67_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC67_IN_INV_SEL_V 0x1 +#define GPIO_FUNC67_IN_INV_SEL_S 6 + +/* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC67_IN_SEL 0x0000003F +#define GPIO_FUNC67_IN_SEL_M ((GPIO_FUNC67_IN_SEL_V)<<(GPIO_FUNC67_IN_SEL_S)) +#define GPIO_FUNC67_IN_SEL_V 0x3F +#define GPIO_FUNC67_IN_SEL_S 0 + +#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0240) + +/* GPIO_SIG68_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG68_IN_SEL (BIT(7)) +#define GPIO_SIG68_IN_SEL_M (BIT(7)) +#define GPIO_SIG68_IN_SEL_V 0x1 +#define GPIO_SIG68_IN_SEL_S 7 + +/* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC68_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC68_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC68_IN_INV_SEL_V 0x1 +#define GPIO_FUNC68_IN_INV_SEL_S 6 + +/* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC68_IN_SEL 0x0000003F +#define GPIO_FUNC68_IN_SEL_M ((GPIO_FUNC68_IN_SEL_V)<<(GPIO_FUNC68_IN_SEL_S)) +#define GPIO_FUNC68_IN_SEL_V 0x3F +#define GPIO_FUNC68_IN_SEL_S 0 + +#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0244) + +/* GPIO_SIG69_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG69_IN_SEL (BIT(7)) +#define GPIO_SIG69_IN_SEL_M (BIT(7)) +#define GPIO_SIG69_IN_SEL_V 0x1 +#define GPIO_SIG69_IN_SEL_S 7 + +/* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC69_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC69_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC69_IN_INV_SEL_V 0x1 +#define GPIO_FUNC69_IN_INV_SEL_S 6 + +/* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC69_IN_SEL 0x0000003F +#define GPIO_FUNC69_IN_SEL_M ((GPIO_FUNC69_IN_SEL_V)<<(GPIO_FUNC69_IN_SEL_S)) +#define GPIO_FUNC69_IN_SEL_V 0x3F +#define GPIO_FUNC69_IN_SEL_S 0 + +#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0248) + +/* GPIO_SIG70_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG70_IN_SEL (BIT(7)) +#define GPIO_SIG70_IN_SEL_M (BIT(7)) +#define GPIO_SIG70_IN_SEL_V 0x1 +#define GPIO_SIG70_IN_SEL_S 7 + +/* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC70_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC70_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC70_IN_INV_SEL_V 0x1 +#define GPIO_FUNC70_IN_INV_SEL_S 6 + +/* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC70_IN_SEL 0x0000003F +#define GPIO_FUNC70_IN_SEL_M ((GPIO_FUNC70_IN_SEL_V)<<(GPIO_FUNC70_IN_SEL_S)) +#define GPIO_FUNC70_IN_SEL_V 0x3F +#define GPIO_FUNC70_IN_SEL_S 0 + +#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x024c) + +/* GPIO_SIG71_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG71_IN_SEL (BIT(7)) +#define GPIO_SIG71_IN_SEL_M (BIT(7)) +#define GPIO_SIG71_IN_SEL_V 0x1 +#define GPIO_SIG71_IN_SEL_S 7 + +/* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC71_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC71_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC71_IN_INV_SEL_V 0x1 +#define GPIO_FUNC71_IN_INV_SEL_S 6 + +/* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC71_IN_SEL 0x0000003F +#define GPIO_FUNC71_IN_SEL_M ((GPIO_FUNC71_IN_SEL_V)<<(GPIO_FUNC71_IN_SEL_S)) +#define GPIO_FUNC71_IN_SEL_V 0x3F +#define GPIO_FUNC71_IN_SEL_S 0 + +#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0250) + +/* GPIO_SIG72_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG72_IN_SEL (BIT(7)) +#define GPIO_SIG72_IN_SEL_M (BIT(7)) +#define GPIO_SIG72_IN_SEL_V 0x1 +#define GPIO_SIG72_IN_SEL_S 7 + +/* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC72_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC72_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC72_IN_INV_SEL_V 0x1 +#define GPIO_FUNC72_IN_INV_SEL_S 6 + +/* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC72_IN_SEL 0x0000003F +#define GPIO_FUNC72_IN_SEL_M ((GPIO_FUNC72_IN_SEL_V)<<(GPIO_FUNC72_IN_SEL_S)) +#define GPIO_FUNC72_IN_SEL_V 0x3F +#define GPIO_FUNC72_IN_SEL_S 0 + +#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0254) + +/* GPIO_SIG73_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG73_IN_SEL (BIT(7)) +#define GPIO_SIG73_IN_SEL_M (BIT(7)) +#define GPIO_SIG73_IN_SEL_V 0x1 +#define GPIO_SIG73_IN_SEL_S 7 + +/* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC73_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC73_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC73_IN_INV_SEL_V 0x1 +#define GPIO_FUNC73_IN_INV_SEL_S 6 + +/* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC73_IN_SEL 0x0000003F +#define GPIO_FUNC73_IN_SEL_M ((GPIO_FUNC73_IN_SEL_V)<<(GPIO_FUNC73_IN_SEL_S)) +#define GPIO_FUNC73_IN_SEL_V 0x3F +#define GPIO_FUNC73_IN_SEL_S 0 + +#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0258) + +/* GPIO_SIG74_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG74_IN_SEL (BIT(7)) +#define GPIO_SIG74_IN_SEL_M (BIT(7)) +#define GPIO_SIG74_IN_SEL_V 0x1 +#define GPIO_SIG74_IN_SEL_S 7 + +/* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC74_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC74_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC74_IN_INV_SEL_V 0x1 +#define GPIO_FUNC74_IN_INV_SEL_S 6 + +/* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC74_IN_SEL 0x0000003F +#define GPIO_FUNC74_IN_SEL_M ((GPIO_FUNC74_IN_SEL_V)<<(GPIO_FUNC74_IN_SEL_S)) +#define GPIO_FUNC74_IN_SEL_V 0x3F +#define GPIO_FUNC74_IN_SEL_S 0 + +#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x025c) + +/* GPIO_SIG75_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG75_IN_SEL (BIT(7)) +#define GPIO_SIG75_IN_SEL_M (BIT(7)) +#define GPIO_SIG75_IN_SEL_V 0x1 +#define GPIO_SIG75_IN_SEL_S 7 + +/* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC75_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC75_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC75_IN_INV_SEL_V 0x1 +#define GPIO_FUNC75_IN_INV_SEL_S 6 + +/* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC75_IN_SEL 0x0000003F +#define GPIO_FUNC75_IN_SEL_M ((GPIO_FUNC75_IN_SEL_V)<<(GPIO_FUNC75_IN_SEL_S)) +#define GPIO_FUNC75_IN_SEL_V 0x3F +#define GPIO_FUNC75_IN_SEL_S 0 + +#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0260) + +/* GPIO_SIG76_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG76_IN_SEL (BIT(7)) +#define GPIO_SIG76_IN_SEL_M (BIT(7)) +#define GPIO_SIG76_IN_SEL_V 0x1 +#define GPIO_SIG76_IN_SEL_S 7 + +/* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC76_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC76_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC76_IN_INV_SEL_V 0x1 +#define GPIO_FUNC76_IN_INV_SEL_S 6 + +/* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC76_IN_SEL 0x0000003F +#define GPIO_FUNC76_IN_SEL_M ((GPIO_FUNC76_IN_SEL_V)<<(GPIO_FUNC76_IN_SEL_S)) +#define GPIO_FUNC76_IN_SEL_V 0x3F +#define GPIO_FUNC76_IN_SEL_S 0 + +#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0264) + +/* GPIO_SIG77_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG77_IN_SEL (BIT(7)) +#define GPIO_SIG77_IN_SEL_M (BIT(7)) +#define GPIO_SIG77_IN_SEL_V 0x1 +#define GPIO_SIG77_IN_SEL_S 7 + +/* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC77_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC77_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC77_IN_INV_SEL_V 0x1 +#define GPIO_FUNC77_IN_INV_SEL_S 6 + +/* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC77_IN_SEL 0x0000003F +#define GPIO_FUNC77_IN_SEL_M ((GPIO_FUNC77_IN_SEL_V)<<(GPIO_FUNC77_IN_SEL_S)) +#define GPIO_FUNC77_IN_SEL_V 0x3F +#define GPIO_FUNC77_IN_SEL_S 0 + +#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0268) + +/* GPIO_SIG78_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG78_IN_SEL (BIT(7)) +#define GPIO_SIG78_IN_SEL_M (BIT(7)) +#define GPIO_SIG78_IN_SEL_V 0x1 +#define GPIO_SIG78_IN_SEL_S 7 + +/* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC78_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC78_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC78_IN_INV_SEL_V 0x1 +#define GPIO_FUNC78_IN_INV_SEL_S 6 + +/* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC78_IN_SEL 0x0000003F +#define GPIO_FUNC78_IN_SEL_M ((GPIO_FUNC78_IN_SEL_V)<<(GPIO_FUNC78_IN_SEL_S)) +#define GPIO_FUNC78_IN_SEL_V 0x3F +#define GPIO_FUNC78_IN_SEL_S 0 + +#define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x026c) + +/* GPIO_SIG79_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG79_IN_SEL (BIT(7)) +#define GPIO_SIG79_IN_SEL_M (BIT(7)) +#define GPIO_SIG79_IN_SEL_V 0x1 +#define GPIO_SIG79_IN_SEL_S 7 + +/* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC79_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC79_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC79_IN_INV_SEL_V 0x1 +#define GPIO_FUNC79_IN_INV_SEL_S 6 + +/* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC79_IN_SEL 0x0000003F +#define GPIO_FUNC79_IN_SEL_M ((GPIO_FUNC79_IN_SEL_V)<<(GPIO_FUNC79_IN_SEL_S)) +#define GPIO_FUNC79_IN_SEL_V 0x3F +#define GPIO_FUNC79_IN_SEL_S 0 + +#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0270) + +/* GPIO_SIG80_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG80_IN_SEL (BIT(7)) +#define GPIO_SIG80_IN_SEL_M (BIT(7)) +#define GPIO_SIG80_IN_SEL_V 0x1 +#define GPIO_SIG80_IN_SEL_S 7 + +/* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC80_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC80_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC80_IN_INV_SEL_V 0x1 +#define GPIO_FUNC80_IN_INV_SEL_S 6 + +/* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC80_IN_SEL 0x0000003F +#define GPIO_FUNC80_IN_SEL_M ((GPIO_FUNC80_IN_SEL_V)<<(GPIO_FUNC80_IN_SEL_S)) +#define GPIO_FUNC80_IN_SEL_V 0x3F +#define GPIO_FUNC80_IN_SEL_S 0 + +#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0274) + +/* GPIO_SIG81_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG81_IN_SEL (BIT(7)) +#define GPIO_SIG81_IN_SEL_M (BIT(7)) +#define GPIO_SIG81_IN_SEL_V 0x1 +#define GPIO_SIG81_IN_SEL_S 7 + +/* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC81_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC81_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC81_IN_INV_SEL_V 0x1 +#define GPIO_FUNC81_IN_INV_SEL_S 6 + +/* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC81_IN_SEL 0x0000003F +#define GPIO_FUNC81_IN_SEL_M ((GPIO_FUNC81_IN_SEL_V)<<(GPIO_FUNC81_IN_SEL_S)) +#define GPIO_FUNC81_IN_SEL_V 0x3F +#define GPIO_FUNC81_IN_SEL_S 0 + +#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0278) + +/* GPIO_SIG82_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG82_IN_SEL (BIT(7)) +#define GPIO_SIG82_IN_SEL_M (BIT(7)) +#define GPIO_SIG82_IN_SEL_V 0x1 +#define GPIO_SIG82_IN_SEL_S 7 + +/* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC82_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC82_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC82_IN_INV_SEL_V 0x1 +#define GPIO_FUNC82_IN_INV_SEL_S 6 + +/* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC82_IN_SEL 0x0000003F +#define GPIO_FUNC82_IN_SEL_M ((GPIO_FUNC82_IN_SEL_V)<<(GPIO_FUNC82_IN_SEL_S)) +#define GPIO_FUNC82_IN_SEL_V 0x3F +#define GPIO_FUNC82_IN_SEL_S 0 + +#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x027c) + +/* GPIO_SIG83_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG83_IN_SEL (BIT(7)) +#define GPIO_SIG83_IN_SEL_M (BIT(7)) +#define GPIO_SIG83_IN_SEL_V 0x1 +#define GPIO_SIG83_IN_SEL_S 7 + +/* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC83_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC83_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC83_IN_INV_SEL_V 0x1 +#define GPIO_FUNC83_IN_INV_SEL_S 6 + +/* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC83_IN_SEL 0x0000003F +#define GPIO_FUNC83_IN_SEL_M ((GPIO_FUNC83_IN_SEL_V)<<(GPIO_FUNC83_IN_SEL_S)) +#define GPIO_FUNC83_IN_SEL_V 0x3F +#define GPIO_FUNC83_IN_SEL_S 0 + +#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0280) + +/* GPIO_SIG84_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG84_IN_SEL (BIT(7)) +#define GPIO_SIG84_IN_SEL_M (BIT(7)) +#define GPIO_SIG84_IN_SEL_V 0x1 +#define GPIO_SIG84_IN_SEL_S 7 + +/* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC84_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC84_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC84_IN_INV_SEL_V 0x1 +#define GPIO_FUNC84_IN_INV_SEL_S 6 + +/* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC84_IN_SEL 0x0000003F +#define GPIO_FUNC84_IN_SEL_M ((GPIO_FUNC84_IN_SEL_V)<<(GPIO_FUNC84_IN_SEL_S)) +#define GPIO_FUNC84_IN_SEL_V 0x3F +#define GPIO_FUNC84_IN_SEL_S 0 + +#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0284) + +/* GPIO_SIG85_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG85_IN_SEL (BIT(7)) +#define GPIO_SIG85_IN_SEL_M (BIT(7)) +#define GPIO_SIG85_IN_SEL_V 0x1 +#define GPIO_SIG85_IN_SEL_S 7 + +/* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC85_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC85_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC85_IN_INV_SEL_V 0x1 +#define GPIO_FUNC85_IN_INV_SEL_S 6 + +/* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC85_IN_SEL 0x0000003F +#define GPIO_FUNC85_IN_SEL_M ((GPIO_FUNC85_IN_SEL_V)<<(GPIO_FUNC85_IN_SEL_S)) +#define GPIO_FUNC85_IN_SEL_V 0x3F +#define GPIO_FUNC85_IN_SEL_S 0 + +#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0288) + +/* GPIO_SIG86_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG86_IN_SEL (BIT(7)) +#define GPIO_SIG86_IN_SEL_M (BIT(7)) +#define GPIO_SIG86_IN_SEL_V 0x1 +#define GPIO_SIG86_IN_SEL_S 7 + +/* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC86_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC86_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC86_IN_INV_SEL_V 0x1 +#define GPIO_FUNC86_IN_INV_SEL_S 6 + +/* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC86_IN_SEL 0x0000003F +#define GPIO_FUNC86_IN_SEL_M ((GPIO_FUNC86_IN_SEL_V)<<(GPIO_FUNC86_IN_SEL_S)) +#define GPIO_FUNC86_IN_SEL_V 0x3F +#define GPIO_FUNC86_IN_SEL_S 0 + +#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x028c) + +/* GPIO_SIG87_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG87_IN_SEL (BIT(7)) +#define GPIO_SIG87_IN_SEL_M (BIT(7)) +#define GPIO_SIG87_IN_SEL_V 0x1 +#define GPIO_SIG87_IN_SEL_S 7 + +/* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC87_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC87_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC87_IN_INV_SEL_V 0x1 +#define GPIO_FUNC87_IN_INV_SEL_S 6 + +/* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC87_IN_SEL 0x0000003F +#define GPIO_FUNC87_IN_SEL_M ((GPIO_FUNC87_IN_SEL_V)<<(GPIO_FUNC87_IN_SEL_S)) +#define GPIO_FUNC87_IN_SEL_V 0x3F +#define GPIO_FUNC87_IN_SEL_S 0 + +#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0290) + +/* GPIO_SIG88_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG88_IN_SEL (BIT(7)) +#define GPIO_SIG88_IN_SEL_M (BIT(7)) +#define GPIO_SIG88_IN_SEL_V 0x1 +#define GPIO_SIG88_IN_SEL_S 7 + +/* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC88_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC88_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC88_IN_INV_SEL_V 0x1 +#define GPIO_FUNC88_IN_INV_SEL_S 6 + +/* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC88_IN_SEL 0x0000003F +#define GPIO_FUNC88_IN_SEL_M ((GPIO_FUNC88_IN_SEL_V)<<(GPIO_FUNC88_IN_SEL_S)) +#define GPIO_FUNC88_IN_SEL_V 0x3F +#define GPIO_FUNC88_IN_SEL_S 0 + +#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0294) + +/* GPIO_SIG89_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG89_IN_SEL (BIT(7)) +#define GPIO_SIG89_IN_SEL_M (BIT(7)) +#define GPIO_SIG89_IN_SEL_V 0x1 +#define GPIO_SIG89_IN_SEL_S 7 + +/* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC89_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC89_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC89_IN_INV_SEL_V 0x1 +#define GPIO_FUNC89_IN_INV_SEL_S 6 + +/* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC89_IN_SEL 0x0000003F +#define GPIO_FUNC89_IN_SEL_M ((GPIO_FUNC89_IN_SEL_V)<<(GPIO_FUNC89_IN_SEL_S)) +#define GPIO_FUNC89_IN_SEL_V 0x3F +#define GPIO_FUNC89_IN_SEL_S 0 + +#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0298) + +/* GPIO_SIG90_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG90_IN_SEL (BIT(7)) +#define GPIO_SIG90_IN_SEL_M (BIT(7)) +#define GPIO_SIG90_IN_SEL_V 0x1 +#define GPIO_SIG90_IN_SEL_S 7 + +/* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC90_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC90_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC90_IN_INV_SEL_V 0x1 +#define GPIO_FUNC90_IN_INV_SEL_S 6 + +/* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC90_IN_SEL 0x0000003F +#define GPIO_FUNC90_IN_SEL_M ((GPIO_FUNC90_IN_SEL_V)<<(GPIO_FUNC90_IN_SEL_S)) +#define GPIO_FUNC90_IN_SEL_V 0x3F +#define GPIO_FUNC90_IN_SEL_S 0 + +#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x029c) + +/* GPIO_SIG91_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG91_IN_SEL (BIT(7)) +#define GPIO_SIG91_IN_SEL_M (BIT(7)) +#define GPIO_SIG91_IN_SEL_V 0x1 +#define GPIO_SIG91_IN_SEL_S 7 + +/* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC91_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC91_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC91_IN_INV_SEL_V 0x1 +#define GPIO_FUNC91_IN_INV_SEL_S 6 + +/* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC91_IN_SEL 0x0000003F +#define GPIO_FUNC91_IN_SEL_M ((GPIO_FUNC91_IN_SEL_V)<<(GPIO_FUNC91_IN_SEL_S)) +#define GPIO_FUNC91_IN_SEL_V 0x3F +#define GPIO_FUNC91_IN_SEL_S 0 + +#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02a0) + +/* GPIO_SIG92_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG92_IN_SEL (BIT(7)) +#define GPIO_SIG92_IN_SEL_M (BIT(7)) +#define GPIO_SIG92_IN_SEL_V 0x1 +#define GPIO_SIG92_IN_SEL_S 7 + +/* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC92_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC92_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC92_IN_INV_SEL_V 0x1 +#define GPIO_FUNC92_IN_INV_SEL_S 6 + +/* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC92_IN_SEL 0x0000003F +#define GPIO_FUNC92_IN_SEL_M ((GPIO_FUNC92_IN_SEL_V)<<(GPIO_FUNC92_IN_SEL_S)) +#define GPIO_FUNC92_IN_SEL_V 0x3F +#define GPIO_FUNC92_IN_SEL_S 0 + +#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02a4) + +/* GPIO_SIG93_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG93_IN_SEL (BIT(7)) +#define GPIO_SIG93_IN_SEL_M (BIT(7)) +#define GPIO_SIG93_IN_SEL_V 0x1 +#define GPIO_SIG93_IN_SEL_S 7 + +/* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC93_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC93_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC93_IN_INV_SEL_V 0x1 +#define GPIO_FUNC93_IN_INV_SEL_S 6 + +/* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC93_IN_SEL 0x0000003F +#define GPIO_FUNC93_IN_SEL_M ((GPIO_FUNC93_IN_SEL_V)<<(GPIO_FUNC93_IN_SEL_S)) +#define GPIO_FUNC93_IN_SEL_V 0x3F +#define GPIO_FUNC93_IN_SEL_S 0 + +#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02a8) + +/* GPIO_SIG94_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG94_IN_SEL (BIT(7)) +#define GPIO_SIG94_IN_SEL_M (BIT(7)) +#define GPIO_SIG94_IN_SEL_V 0x1 +#define GPIO_SIG94_IN_SEL_S 7 + +/* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC94_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC94_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC94_IN_INV_SEL_V 0x1 +#define GPIO_FUNC94_IN_INV_SEL_S 6 + +/* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC94_IN_SEL 0x0000003F +#define GPIO_FUNC94_IN_SEL_M ((GPIO_FUNC94_IN_SEL_V)<<(GPIO_FUNC94_IN_SEL_S)) +#define GPIO_FUNC94_IN_SEL_V 0x3F +#define GPIO_FUNC94_IN_SEL_S 0 + +#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02ac) + +/* GPIO_SIG95_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG95_IN_SEL (BIT(7)) +#define GPIO_SIG95_IN_SEL_M (BIT(7)) +#define GPIO_SIG95_IN_SEL_V 0x1 +#define GPIO_SIG95_IN_SEL_S 7 + +/* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC95_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC95_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC95_IN_INV_SEL_V 0x1 +#define GPIO_FUNC95_IN_INV_SEL_S 6 + +/* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC95_IN_SEL 0x0000003F +#define GPIO_FUNC95_IN_SEL_M ((GPIO_FUNC95_IN_SEL_V)<<(GPIO_FUNC95_IN_SEL_S)) +#define GPIO_FUNC95_IN_SEL_V 0x3F +#define GPIO_FUNC95_IN_SEL_S 0 + +#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02b0) + +/* GPIO_SIG96_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG96_IN_SEL (BIT(7)) +#define GPIO_SIG96_IN_SEL_M (BIT(7)) +#define GPIO_SIG96_IN_SEL_V 0x1 +#define GPIO_SIG96_IN_SEL_S 7 + +/* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC96_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC96_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC96_IN_INV_SEL_V 0x1 +#define GPIO_FUNC96_IN_INV_SEL_S 6 + +/* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC96_IN_SEL 0x0000003F +#define GPIO_FUNC96_IN_SEL_M ((GPIO_FUNC96_IN_SEL_V)<<(GPIO_FUNC96_IN_SEL_S)) +#define GPIO_FUNC96_IN_SEL_V 0x3F +#define GPIO_FUNC96_IN_SEL_S 0 + +#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02b4) + +/* GPIO_SIG97_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG97_IN_SEL (BIT(7)) +#define GPIO_SIG97_IN_SEL_M (BIT(7)) +#define GPIO_SIG97_IN_SEL_V 0x1 +#define GPIO_SIG97_IN_SEL_S 7 + +/* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC97_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC97_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC97_IN_INV_SEL_V 0x1 +#define GPIO_FUNC97_IN_INV_SEL_S 6 + +/* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC97_IN_SEL 0x0000003F +#define GPIO_FUNC97_IN_SEL_M ((GPIO_FUNC97_IN_SEL_V)<<(GPIO_FUNC97_IN_SEL_S)) +#define GPIO_FUNC97_IN_SEL_V 0x3F +#define GPIO_FUNC97_IN_SEL_S 0 + +#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02b8) + +/* GPIO_SIG98_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG98_IN_SEL (BIT(7)) +#define GPIO_SIG98_IN_SEL_M (BIT(7)) +#define GPIO_SIG98_IN_SEL_V 0x1 +#define GPIO_SIG98_IN_SEL_S 7 + +/* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC98_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC98_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC98_IN_INV_SEL_V 0x1 +#define GPIO_FUNC98_IN_INV_SEL_S 6 + +/* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC98_IN_SEL 0x0000003F +#define GPIO_FUNC98_IN_SEL_M ((GPIO_FUNC98_IN_SEL_V)<<(GPIO_FUNC98_IN_SEL_S)) +#define GPIO_FUNC98_IN_SEL_V 0x3F +#define GPIO_FUNC98_IN_SEL_S 0 + +#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02bc) + +/* GPIO_SIG99_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG99_IN_SEL (BIT(7)) +#define GPIO_SIG99_IN_SEL_M (BIT(7)) +#define GPIO_SIG99_IN_SEL_V 0x1 +#define GPIO_SIG99_IN_SEL_S 7 + +/* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC99_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC99_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC99_IN_INV_SEL_V 0x1 +#define GPIO_FUNC99_IN_INV_SEL_S 6 + +/* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC99_IN_SEL 0x0000003F +#define GPIO_FUNC99_IN_SEL_M ((GPIO_FUNC99_IN_SEL_V)<<(GPIO_FUNC99_IN_SEL_S)) +#define GPIO_FUNC99_IN_SEL_V 0x3F +#define GPIO_FUNC99_IN_SEL_S 0 + +#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02c0) + +/* GPIO_SIG100_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG100_IN_SEL (BIT(7)) +#define GPIO_SIG100_IN_SEL_M (BIT(7)) +#define GPIO_SIG100_IN_SEL_V 0x1 +#define GPIO_SIG100_IN_SEL_S 7 + +/* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC100_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC100_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC100_IN_INV_SEL_V 0x1 +#define GPIO_FUNC100_IN_INV_SEL_S 6 + +/* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC100_IN_SEL 0x0000003F +#define GPIO_FUNC100_IN_SEL_M ((GPIO_FUNC100_IN_SEL_V)<<(GPIO_FUNC100_IN_SEL_S)) +#define GPIO_FUNC100_IN_SEL_V 0x3F +#define GPIO_FUNC100_IN_SEL_S 0 + +#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02c4) + +/* GPIO_SIG101_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG101_IN_SEL (BIT(7)) +#define GPIO_SIG101_IN_SEL_M (BIT(7)) +#define GPIO_SIG101_IN_SEL_V 0x1 +#define GPIO_SIG101_IN_SEL_S 7 + +/* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC101_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC101_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC101_IN_INV_SEL_V 0x1 +#define GPIO_FUNC101_IN_INV_SEL_S 6 + +/* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC101_IN_SEL 0x0000003F +#define GPIO_FUNC101_IN_SEL_M ((GPIO_FUNC101_IN_SEL_V)<<(GPIO_FUNC101_IN_SEL_S)) +#define GPIO_FUNC101_IN_SEL_V 0x3F +#define GPIO_FUNC101_IN_SEL_S 0 + +#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02c8) + +/* GPIO_SIG102_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG102_IN_SEL (BIT(7)) +#define GPIO_SIG102_IN_SEL_M (BIT(7)) +#define GPIO_SIG102_IN_SEL_V 0x1 +#define GPIO_SIG102_IN_SEL_S 7 + +/* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC102_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC102_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC102_IN_INV_SEL_V 0x1 +#define GPIO_FUNC102_IN_INV_SEL_S 6 + +/* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC102_IN_SEL 0x0000003F +#define GPIO_FUNC102_IN_SEL_M ((GPIO_FUNC102_IN_SEL_V)<<(GPIO_FUNC102_IN_SEL_S)) +#define GPIO_FUNC102_IN_SEL_V 0x3F +#define GPIO_FUNC102_IN_SEL_S 0 + +#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02cc) + +/* GPIO_SIG103_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG103_IN_SEL (BIT(7)) +#define GPIO_SIG103_IN_SEL_M (BIT(7)) +#define GPIO_SIG103_IN_SEL_V 0x1 +#define GPIO_SIG103_IN_SEL_S 7 + +/* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC103_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC103_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC103_IN_INV_SEL_V 0x1 +#define GPIO_FUNC103_IN_INV_SEL_S 6 + +/* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC103_IN_SEL 0x0000003F +#define GPIO_FUNC103_IN_SEL_M ((GPIO_FUNC103_IN_SEL_V)<<(GPIO_FUNC103_IN_SEL_S)) +#define GPIO_FUNC103_IN_SEL_V 0x3F +#define GPIO_FUNC103_IN_SEL_S 0 + +#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02d0) + +/* GPIO_SIG104_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG104_IN_SEL (BIT(7)) +#define GPIO_SIG104_IN_SEL_M (BIT(7)) +#define GPIO_SIG104_IN_SEL_V 0x1 +#define GPIO_SIG104_IN_SEL_S 7 + +/* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC104_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC104_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC104_IN_INV_SEL_V 0x1 +#define GPIO_FUNC104_IN_INV_SEL_S 6 + +/* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC104_IN_SEL 0x0000003F +#define GPIO_FUNC104_IN_SEL_M ((GPIO_FUNC104_IN_SEL_V)<<(GPIO_FUNC104_IN_SEL_S)) +#define GPIO_FUNC104_IN_SEL_V 0x3F +#define GPIO_FUNC104_IN_SEL_S 0 + +#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02d4) + +/* GPIO_SIG105_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG105_IN_SEL (BIT(7)) +#define GPIO_SIG105_IN_SEL_M (BIT(7)) +#define GPIO_SIG105_IN_SEL_V 0x1 +#define GPIO_SIG105_IN_SEL_S 7 + +/* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC105_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC105_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC105_IN_INV_SEL_V 0x1 +#define GPIO_FUNC105_IN_INV_SEL_S 6 + +/* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC105_IN_SEL 0x0000003F +#define GPIO_FUNC105_IN_SEL_M ((GPIO_FUNC105_IN_SEL_V)<<(GPIO_FUNC105_IN_SEL_S)) +#define GPIO_FUNC105_IN_SEL_V 0x3F +#define GPIO_FUNC105_IN_SEL_S 0 + +#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02d8) + +/* GPIO_SIG106_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG106_IN_SEL (BIT(7)) +#define GPIO_SIG106_IN_SEL_M (BIT(7)) +#define GPIO_SIG106_IN_SEL_V 0x1 +#define GPIO_SIG106_IN_SEL_S 7 + +/* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC106_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC106_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC106_IN_INV_SEL_V 0x1 +#define GPIO_FUNC106_IN_INV_SEL_S 6 + +/* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC106_IN_SEL 0x0000003F +#define GPIO_FUNC106_IN_SEL_M ((GPIO_FUNC106_IN_SEL_V)<<(GPIO_FUNC106_IN_SEL_S)) +#define GPIO_FUNC106_IN_SEL_V 0x3F +#define GPIO_FUNC106_IN_SEL_S 0 + +#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02dc) + +/* GPIO_SIG107_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG107_IN_SEL (BIT(7)) +#define GPIO_SIG107_IN_SEL_M (BIT(7)) +#define GPIO_SIG107_IN_SEL_V 0x1 +#define GPIO_SIG107_IN_SEL_S 7 + +/* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC107_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC107_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC107_IN_INV_SEL_V 0x1 +#define GPIO_FUNC107_IN_INV_SEL_S 6 + +/* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC107_IN_SEL 0x0000003F +#define GPIO_FUNC107_IN_SEL_M ((GPIO_FUNC107_IN_SEL_V)<<(GPIO_FUNC107_IN_SEL_S)) +#define GPIO_FUNC107_IN_SEL_V 0x3F +#define GPIO_FUNC107_IN_SEL_S 0 + +#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02e0) + +/* GPIO_SIG108_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG108_IN_SEL (BIT(7)) +#define GPIO_SIG108_IN_SEL_M (BIT(7)) +#define GPIO_SIG108_IN_SEL_V 0x1 +#define GPIO_SIG108_IN_SEL_S 7 + +/* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC108_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC108_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC108_IN_INV_SEL_V 0x1 +#define GPIO_FUNC108_IN_INV_SEL_S 6 + +/* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC108_IN_SEL 0x0000003F +#define GPIO_FUNC108_IN_SEL_M ((GPIO_FUNC108_IN_SEL_V)<<(GPIO_FUNC108_IN_SEL_S)) +#define GPIO_FUNC108_IN_SEL_V 0x3F +#define GPIO_FUNC108_IN_SEL_S 0 + +#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02e4) + +/* GPIO_SIG109_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG109_IN_SEL (BIT(7)) +#define GPIO_SIG109_IN_SEL_M (BIT(7)) +#define GPIO_SIG109_IN_SEL_V 0x1 +#define GPIO_SIG109_IN_SEL_S 7 + +/* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC109_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC109_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC109_IN_INV_SEL_V 0x1 +#define GPIO_FUNC109_IN_INV_SEL_S 6 + +/* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC109_IN_SEL 0x0000003F +#define GPIO_FUNC109_IN_SEL_M ((GPIO_FUNC109_IN_SEL_V)<<(GPIO_FUNC109_IN_SEL_S)) +#define GPIO_FUNC109_IN_SEL_V 0x3F +#define GPIO_FUNC109_IN_SEL_S 0 + +#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02e8) + +/* GPIO_SIG110_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG110_IN_SEL (BIT(7)) +#define GPIO_SIG110_IN_SEL_M (BIT(7)) +#define GPIO_SIG110_IN_SEL_V 0x1 +#define GPIO_SIG110_IN_SEL_S 7 + +/* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC110_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC110_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC110_IN_INV_SEL_V 0x1 +#define GPIO_FUNC110_IN_INV_SEL_S 6 + +/* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC110_IN_SEL 0x0000003F +#define GPIO_FUNC110_IN_SEL_M ((GPIO_FUNC110_IN_SEL_V)<<(GPIO_FUNC110_IN_SEL_S)) +#define GPIO_FUNC110_IN_SEL_V 0x3F +#define GPIO_FUNC110_IN_SEL_S 0 + +#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02ec) + +/* GPIO_SIG111_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG111_IN_SEL (BIT(7)) +#define GPIO_SIG111_IN_SEL_M (BIT(7)) +#define GPIO_SIG111_IN_SEL_V 0x1 +#define GPIO_SIG111_IN_SEL_S 7 + +/* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC111_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC111_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC111_IN_INV_SEL_V 0x1 +#define GPIO_FUNC111_IN_INV_SEL_S 6 + +/* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC111_IN_SEL 0x0000003F +#define GPIO_FUNC111_IN_SEL_M ((GPIO_FUNC111_IN_SEL_V)<<(GPIO_FUNC111_IN_SEL_S)) +#define GPIO_FUNC111_IN_SEL_V 0x3F +#define GPIO_FUNC111_IN_SEL_S 0 + +#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02f0) + +/* GPIO_SIG112_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG112_IN_SEL (BIT(7)) +#define GPIO_SIG112_IN_SEL_M (BIT(7)) +#define GPIO_SIG112_IN_SEL_V 0x1 +#define GPIO_SIG112_IN_SEL_S 7 + +/* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC112_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC112_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC112_IN_INV_SEL_V 0x1 +#define GPIO_FUNC112_IN_INV_SEL_S 6 + +/* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC112_IN_SEL 0x0000003F +#define GPIO_FUNC112_IN_SEL_M ((GPIO_FUNC112_IN_SEL_V)<<(GPIO_FUNC112_IN_SEL_S)) +#define GPIO_FUNC112_IN_SEL_V 0x3F +#define GPIO_FUNC112_IN_SEL_S 0 + +#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02f4) + +/* GPIO_SIG113_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG113_IN_SEL (BIT(7)) +#define GPIO_SIG113_IN_SEL_M (BIT(7)) +#define GPIO_SIG113_IN_SEL_V 0x1 +#define GPIO_SIG113_IN_SEL_S 7 + +/* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC113_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC113_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC113_IN_INV_SEL_V 0x1 +#define GPIO_FUNC113_IN_INV_SEL_S 6 + +/* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC113_IN_SEL 0x0000003F +#define GPIO_FUNC113_IN_SEL_M ((GPIO_FUNC113_IN_SEL_V)<<(GPIO_FUNC113_IN_SEL_S)) +#define GPIO_FUNC113_IN_SEL_V 0x3F +#define GPIO_FUNC113_IN_SEL_S 0 + +#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02f8) + +/* GPIO_SIG114_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG114_IN_SEL (BIT(7)) +#define GPIO_SIG114_IN_SEL_M (BIT(7)) +#define GPIO_SIG114_IN_SEL_V 0x1 +#define GPIO_SIG114_IN_SEL_S 7 + +/* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC114_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC114_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC114_IN_INV_SEL_V 0x1 +#define GPIO_FUNC114_IN_INV_SEL_S 6 + +/* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC114_IN_SEL 0x0000003F +#define GPIO_FUNC114_IN_SEL_M ((GPIO_FUNC114_IN_SEL_V)<<(GPIO_FUNC114_IN_SEL_S)) +#define GPIO_FUNC114_IN_SEL_V 0x3F +#define GPIO_FUNC114_IN_SEL_S 0 + +#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02fc) + +/* GPIO_SIG115_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG115_IN_SEL (BIT(7)) +#define GPIO_SIG115_IN_SEL_M (BIT(7)) +#define GPIO_SIG115_IN_SEL_V 0x1 +#define GPIO_SIG115_IN_SEL_S 7 + +/* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC115_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC115_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC115_IN_INV_SEL_V 0x1 +#define GPIO_FUNC115_IN_INV_SEL_S 6 + +/* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC115_IN_SEL 0x0000003F +#define GPIO_FUNC115_IN_SEL_M ((GPIO_FUNC115_IN_SEL_V)<<(GPIO_FUNC115_IN_SEL_S)) +#define GPIO_FUNC115_IN_SEL_V 0x3F +#define GPIO_FUNC115_IN_SEL_S 0 + +#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0300) + +/* GPIO_SIG116_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG116_IN_SEL (BIT(7)) +#define GPIO_SIG116_IN_SEL_M (BIT(7)) +#define GPIO_SIG116_IN_SEL_V 0x1 +#define GPIO_SIG116_IN_SEL_S 7 + +/* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC116_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC116_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC116_IN_INV_SEL_V 0x1 +#define GPIO_FUNC116_IN_INV_SEL_S 6 + +/* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC116_IN_SEL 0x0000003F +#define GPIO_FUNC116_IN_SEL_M ((GPIO_FUNC116_IN_SEL_V)<<(GPIO_FUNC116_IN_SEL_S)) +#define GPIO_FUNC116_IN_SEL_V 0x3F +#define GPIO_FUNC116_IN_SEL_S 0 + +#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0304) + +/* GPIO_SIG117_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG117_IN_SEL (BIT(7)) +#define GPIO_SIG117_IN_SEL_M (BIT(7)) +#define GPIO_SIG117_IN_SEL_V 0x1 +#define GPIO_SIG117_IN_SEL_S 7 + +/* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC117_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC117_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC117_IN_INV_SEL_V 0x1 +#define GPIO_FUNC117_IN_INV_SEL_S 6 + +/* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC117_IN_SEL 0x0000003F +#define GPIO_FUNC117_IN_SEL_M ((GPIO_FUNC117_IN_SEL_V)<<(GPIO_FUNC117_IN_SEL_S)) +#define GPIO_FUNC117_IN_SEL_V 0x3F +#define GPIO_FUNC117_IN_SEL_S 0 + +#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0308) + +/* GPIO_SIG118_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG118_IN_SEL (BIT(7)) +#define GPIO_SIG118_IN_SEL_M (BIT(7)) +#define GPIO_SIG118_IN_SEL_V 0x1 +#define GPIO_SIG118_IN_SEL_S 7 + +/* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC118_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC118_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC118_IN_INV_SEL_V 0x1 +#define GPIO_FUNC118_IN_INV_SEL_S 6 + +/* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC118_IN_SEL 0x0000003F +#define GPIO_FUNC118_IN_SEL_M ((GPIO_FUNC118_IN_SEL_V)<<(GPIO_FUNC118_IN_SEL_S)) +#define GPIO_FUNC118_IN_SEL_V 0x3F +#define GPIO_FUNC118_IN_SEL_S 0 + +#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x030c) + +/* GPIO_SIG119_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG119_IN_SEL (BIT(7)) +#define GPIO_SIG119_IN_SEL_M (BIT(7)) +#define GPIO_SIG119_IN_SEL_V 0x1 +#define GPIO_SIG119_IN_SEL_S 7 + +/* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC119_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC119_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC119_IN_INV_SEL_V 0x1 +#define GPIO_FUNC119_IN_INV_SEL_S 6 + +/* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC119_IN_SEL 0x0000003F +#define GPIO_FUNC119_IN_SEL_M ((GPIO_FUNC119_IN_SEL_V)<<(GPIO_FUNC119_IN_SEL_S)) +#define GPIO_FUNC119_IN_SEL_V 0x3F +#define GPIO_FUNC119_IN_SEL_S 0 + +#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0310) + +/* GPIO_SIG120_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG120_IN_SEL (BIT(7)) +#define GPIO_SIG120_IN_SEL_M (BIT(7)) +#define GPIO_SIG120_IN_SEL_V 0x1 +#define GPIO_SIG120_IN_SEL_S 7 + +/* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC120_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC120_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC120_IN_INV_SEL_V 0x1 +#define GPIO_FUNC120_IN_INV_SEL_S 6 + +/* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC120_IN_SEL 0x0000003F +#define GPIO_FUNC120_IN_SEL_M ((GPIO_FUNC120_IN_SEL_V)<<(GPIO_FUNC120_IN_SEL_S)) +#define GPIO_FUNC120_IN_SEL_V 0x3F +#define GPIO_FUNC120_IN_SEL_S 0 + +#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0314) + +/* GPIO_SIG121_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG121_IN_SEL (BIT(7)) +#define GPIO_SIG121_IN_SEL_M (BIT(7)) +#define GPIO_SIG121_IN_SEL_V 0x1 +#define GPIO_SIG121_IN_SEL_S 7 + +/* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC121_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC121_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC121_IN_INV_SEL_V 0x1 +#define GPIO_FUNC121_IN_INV_SEL_S 6 + +/* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC121_IN_SEL 0x0000003F +#define GPIO_FUNC121_IN_SEL_M ((GPIO_FUNC121_IN_SEL_V)<<(GPIO_FUNC121_IN_SEL_S)) +#define GPIO_FUNC121_IN_SEL_V 0x3F +#define GPIO_FUNC121_IN_SEL_S 0 + +#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0318) + +/* GPIO_SIG122_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG122_IN_SEL (BIT(7)) +#define GPIO_SIG122_IN_SEL_M (BIT(7)) +#define GPIO_SIG122_IN_SEL_V 0x1 +#define GPIO_SIG122_IN_SEL_S 7 + +/* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC122_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC122_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC122_IN_INV_SEL_V 0x1 +#define GPIO_FUNC122_IN_INV_SEL_S 6 + +/* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC122_IN_SEL 0x0000003F +#define GPIO_FUNC122_IN_SEL_M ((GPIO_FUNC122_IN_SEL_V)<<(GPIO_FUNC122_IN_SEL_S)) +#define GPIO_FUNC122_IN_SEL_V 0x3F +#define GPIO_FUNC122_IN_SEL_S 0 + +#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x031c) + +/* GPIO_SIG123_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG123_IN_SEL (BIT(7)) +#define GPIO_SIG123_IN_SEL_M (BIT(7)) +#define GPIO_SIG123_IN_SEL_V 0x1 +#define GPIO_SIG123_IN_SEL_S 7 + +/* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC123_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC123_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC123_IN_INV_SEL_V 0x1 +#define GPIO_FUNC123_IN_INV_SEL_S 6 + +/* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC123_IN_SEL 0x0000003F +#define GPIO_FUNC123_IN_SEL_M ((GPIO_FUNC123_IN_SEL_V)<<(GPIO_FUNC123_IN_SEL_S)) +#define GPIO_FUNC123_IN_SEL_V 0x3F +#define GPIO_FUNC123_IN_SEL_S 0 + +#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0320) + +/* GPIO_SIG124_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG124_IN_SEL (BIT(7)) +#define GPIO_SIG124_IN_SEL_M (BIT(7)) +#define GPIO_SIG124_IN_SEL_V 0x1 +#define GPIO_SIG124_IN_SEL_S 7 + +/* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC124_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC124_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC124_IN_INV_SEL_V 0x1 +#define GPIO_FUNC124_IN_INV_SEL_S 6 + +/* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC124_IN_SEL 0x0000003F +#define GPIO_FUNC124_IN_SEL_M ((GPIO_FUNC124_IN_SEL_V)<<(GPIO_FUNC124_IN_SEL_S)) +#define GPIO_FUNC124_IN_SEL_V 0x3F +#define GPIO_FUNC124_IN_SEL_S 0 + +#define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0324) + +/* GPIO_SIG125_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG125_IN_SEL (BIT(7)) +#define GPIO_SIG125_IN_SEL_M (BIT(7)) +#define GPIO_SIG125_IN_SEL_V 0x1 +#define GPIO_SIG125_IN_SEL_S 7 + +/* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC125_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC125_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC125_IN_INV_SEL_V 0x1 +#define GPIO_FUNC125_IN_INV_SEL_S 6 + +/* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC125_IN_SEL 0x0000003F +#define GPIO_FUNC125_IN_SEL_M ((GPIO_FUNC125_IN_SEL_V)<<(GPIO_FUNC125_IN_SEL_S)) +#define GPIO_FUNC125_IN_SEL_V 0x3F +#define GPIO_FUNC125_IN_SEL_S 0 + +#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0328) + +/* GPIO_SIG126_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG126_IN_SEL (BIT(7)) +#define GPIO_SIG126_IN_SEL_M (BIT(7)) +#define GPIO_SIG126_IN_SEL_V 0x1 +#define GPIO_SIG126_IN_SEL_S 7 + +/* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC126_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC126_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC126_IN_INV_SEL_V 0x1 +#define GPIO_FUNC126_IN_INV_SEL_S 6 + +/* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC126_IN_SEL 0x0000003F +#define GPIO_FUNC126_IN_SEL_M ((GPIO_FUNC126_IN_SEL_V)<<(GPIO_FUNC126_IN_SEL_S)) +#define GPIO_FUNC126_IN_SEL_V 0x3F +#define GPIO_FUNC126_IN_SEL_S 0 + +#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x032c) + +/* GPIO_SIG127_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG127_IN_SEL (BIT(7)) +#define GPIO_SIG127_IN_SEL_M (BIT(7)) +#define GPIO_SIG127_IN_SEL_V 0x1 +#define GPIO_SIG127_IN_SEL_S 7 + +/* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC127_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC127_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC127_IN_INV_SEL_V 0x1 +#define GPIO_FUNC127_IN_INV_SEL_S 6 + +/* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC127_IN_SEL 0x0000003F +#define GPIO_FUNC127_IN_SEL_M ((GPIO_FUNC127_IN_SEL_V)<<(GPIO_FUNC127_IN_SEL_S)) +#define GPIO_FUNC127_IN_SEL_V 0x3F +#define GPIO_FUNC127_IN_SEL_S 0 + +#define GPIO_FUNC128_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0330) + +/* GPIO_SIG128_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG128_IN_SEL (BIT(7)) +#define GPIO_SIG128_IN_SEL_M (BIT(7)) +#define GPIO_SIG128_IN_SEL_V 0x1 +#define GPIO_SIG128_IN_SEL_S 7 + +/* GPIO_FUNC128_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC128_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC128_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC128_IN_INV_SEL_V 0x1 +#define GPIO_FUNC128_IN_INV_SEL_S 6 + +/* GPIO_FUNC128_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC128_IN_SEL 0x0000003F +#define GPIO_FUNC128_IN_SEL_M ((GPIO_FUNC128_IN_SEL_V)<<(GPIO_FUNC128_IN_SEL_S)) +#define GPIO_FUNC128_IN_SEL_V 0x3F +#define GPIO_FUNC128_IN_SEL_S 0 + +#define GPIO_FUNC129_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0334) + +/* GPIO_SIG129_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG129_IN_SEL (BIT(7)) +#define GPIO_SIG129_IN_SEL_M (BIT(7)) +#define GPIO_SIG129_IN_SEL_V 0x1 +#define GPIO_SIG129_IN_SEL_S 7 + +/* GPIO_FUNC129_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC129_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC129_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC129_IN_INV_SEL_V 0x1 +#define GPIO_FUNC129_IN_INV_SEL_S 6 + +/* GPIO_FUNC129_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC129_IN_SEL 0x0000003F +#define GPIO_FUNC129_IN_SEL_M ((GPIO_FUNC129_IN_SEL_V)<<(GPIO_FUNC129_IN_SEL_S)) +#define GPIO_FUNC129_IN_SEL_V 0x3F +#define GPIO_FUNC129_IN_SEL_S 0 + +#define GPIO_FUNC130_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0338) + +/* GPIO_SIG130_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG130_IN_SEL (BIT(7)) +#define GPIO_SIG130_IN_SEL_M (BIT(7)) +#define GPIO_SIG130_IN_SEL_V 0x1 +#define GPIO_SIG130_IN_SEL_S 7 + +/* GPIO_FUNC130_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC130_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC130_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC130_IN_INV_SEL_V 0x1 +#define GPIO_FUNC130_IN_INV_SEL_S 6 + +/* GPIO_FUNC130_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC130_IN_SEL 0x0000003F +#define GPIO_FUNC130_IN_SEL_M ((GPIO_FUNC130_IN_SEL_V)<<(GPIO_FUNC130_IN_SEL_S)) +#define GPIO_FUNC130_IN_SEL_V 0x3F +#define GPIO_FUNC130_IN_SEL_S 0 + +#define GPIO_FUNC131_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x033c) + +/* GPIO_SIG131_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG131_IN_SEL (BIT(7)) +#define GPIO_SIG131_IN_SEL_M (BIT(7)) +#define GPIO_SIG131_IN_SEL_V 0x1 +#define GPIO_SIG131_IN_SEL_S 7 + +/* GPIO_FUNC131_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC131_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC131_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC131_IN_INV_SEL_V 0x1 +#define GPIO_FUNC131_IN_INV_SEL_S 6 + +/* GPIO_FUNC131_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC131_IN_SEL 0x0000003F +#define GPIO_FUNC131_IN_SEL_M ((GPIO_FUNC131_IN_SEL_V)<<(GPIO_FUNC131_IN_SEL_S)) +#define GPIO_FUNC131_IN_SEL_V 0x3F +#define GPIO_FUNC131_IN_SEL_S 0 + +#define GPIO_FUNC132_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0340) + +/* GPIO_SIG132_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG132_IN_SEL (BIT(7)) +#define GPIO_SIG132_IN_SEL_M (BIT(7)) +#define GPIO_SIG132_IN_SEL_V 0x1 +#define GPIO_SIG132_IN_SEL_S 7 + +/* GPIO_FUNC132_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC132_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC132_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC132_IN_INV_SEL_V 0x1 +#define GPIO_FUNC132_IN_INV_SEL_S 6 + +/* GPIO_FUNC132_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC132_IN_SEL 0x0000003F +#define GPIO_FUNC132_IN_SEL_M ((GPIO_FUNC132_IN_SEL_V)<<(GPIO_FUNC132_IN_SEL_S)) +#define GPIO_FUNC132_IN_SEL_V 0x3F +#define GPIO_FUNC132_IN_SEL_S 0 + +#define GPIO_FUNC133_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0344) + +/* GPIO_SIG133_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG133_IN_SEL (BIT(7)) +#define GPIO_SIG133_IN_SEL_M (BIT(7)) +#define GPIO_SIG133_IN_SEL_V 0x1 +#define GPIO_SIG133_IN_SEL_S 7 + +/* GPIO_FUNC133_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC133_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC133_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC133_IN_INV_SEL_V 0x1 +#define GPIO_FUNC133_IN_INV_SEL_S 6 + +/* GPIO_FUNC133_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC133_IN_SEL 0x0000003F +#define GPIO_FUNC133_IN_SEL_M ((GPIO_FUNC133_IN_SEL_V)<<(GPIO_FUNC133_IN_SEL_S)) +#define GPIO_FUNC133_IN_SEL_V 0x3F +#define GPIO_FUNC133_IN_SEL_S 0 + +#define GPIO_FUNC134_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0348) + +/* GPIO_SIG134_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG134_IN_SEL (BIT(7)) +#define GPIO_SIG134_IN_SEL_M (BIT(7)) +#define GPIO_SIG134_IN_SEL_V 0x1 +#define GPIO_SIG134_IN_SEL_S 7 + +/* GPIO_FUNC134_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC134_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC134_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC134_IN_INV_SEL_V 0x1 +#define GPIO_FUNC134_IN_INV_SEL_S 6 + +/* GPIO_FUNC134_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC134_IN_SEL 0x0000003F +#define GPIO_FUNC134_IN_SEL_M ((GPIO_FUNC134_IN_SEL_V)<<(GPIO_FUNC134_IN_SEL_S)) +#define GPIO_FUNC134_IN_SEL_V 0x3F +#define GPIO_FUNC134_IN_SEL_S 0 + +#define GPIO_FUNC135_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x034c) + +/* GPIO_SIG135_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG135_IN_SEL (BIT(7)) +#define GPIO_SIG135_IN_SEL_M (BIT(7)) +#define GPIO_SIG135_IN_SEL_V 0x1 +#define GPIO_SIG135_IN_SEL_S 7 + +/* GPIO_FUNC135_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC135_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC135_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC135_IN_INV_SEL_V 0x1 +#define GPIO_FUNC135_IN_INV_SEL_S 6 + +/* GPIO_FUNC135_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC135_IN_SEL 0x0000003F +#define GPIO_FUNC135_IN_SEL_M ((GPIO_FUNC135_IN_SEL_V)<<(GPIO_FUNC135_IN_SEL_S)) +#define GPIO_FUNC135_IN_SEL_V 0x3F +#define GPIO_FUNC135_IN_SEL_S 0 + +#define GPIO_FUNC136_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0350) + +/* GPIO_SIG136_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG136_IN_SEL (BIT(7)) +#define GPIO_SIG136_IN_SEL_M (BIT(7)) +#define GPIO_SIG136_IN_SEL_V 0x1 +#define GPIO_SIG136_IN_SEL_S 7 + +/* GPIO_FUNC136_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC136_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC136_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC136_IN_INV_SEL_V 0x1 +#define GPIO_FUNC136_IN_INV_SEL_S 6 + +/* GPIO_FUNC136_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC136_IN_SEL 0x0000003F +#define GPIO_FUNC136_IN_SEL_M ((GPIO_FUNC136_IN_SEL_V)<<(GPIO_FUNC136_IN_SEL_S)) +#define GPIO_FUNC136_IN_SEL_V 0x3F +#define GPIO_FUNC136_IN_SEL_S 0 + +#define GPIO_FUNC137_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0354) + +/* GPIO_SIG137_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG137_IN_SEL (BIT(7)) +#define GPIO_SIG137_IN_SEL_M (BIT(7)) +#define GPIO_SIG137_IN_SEL_V 0x1 +#define GPIO_SIG137_IN_SEL_S 7 + +/* GPIO_FUNC137_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC137_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC137_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC137_IN_INV_SEL_V 0x1 +#define GPIO_FUNC137_IN_INV_SEL_S 6 + +/* GPIO_FUNC137_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC137_IN_SEL 0x0000003F +#define GPIO_FUNC137_IN_SEL_M ((GPIO_FUNC137_IN_SEL_V)<<(GPIO_FUNC137_IN_SEL_S)) +#define GPIO_FUNC137_IN_SEL_V 0x3F +#define GPIO_FUNC137_IN_SEL_S 0 + +#define GPIO_FUNC138_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0358) + +/* GPIO_SIG138_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG138_IN_SEL (BIT(7)) +#define GPIO_SIG138_IN_SEL_M (BIT(7)) +#define GPIO_SIG138_IN_SEL_V 0x1 +#define GPIO_SIG138_IN_SEL_S 7 + +/* GPIO_FUNC138_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC138_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC138_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC138_IN_INV_SEL_V 0x1 +#define GPIO_FUNC138_IN_INV_SEL_S 6 + +/* GPIO_FUNC138_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC138_IN_SEL 0x0000003F +#define GPIO_FUNC138_IN_SEL_M ((GPIO_FUNC138_IN_SEL_V)<<(GPIO_FUNC138_IN_SEL_S)) +#define GPIO_FUNC138_IN_SEL_V 0x3F +#define GPIO_FUNC138_IN_SEL_S 0 + +#define GPIO_FUNC139_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x035c) + +/* GPIO_SIG139_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG139_IN_SEL (BIT(7)) +#define GPIO_SIG139_IN_SEL_M (BIT(7)) +#define GPIO_SIG139_IN_SEL_V 0x1 +#define GPIO_SIG139_IN_SEL_S 7 + +/* GPIO_FUNC139_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC139_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC139_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC139_IN_INV_SEL_V 0x1 +#define GPIO_FUNC139_IN_INV_SEL_S 6 + +/* GPIO_FUNC139_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC139_IN_SEL 0x0000003F +#define GPIO_FUNC139_IN_SEL_M ((GPIO_FUNC139_IN_SEL_V)<<(GPIO_FUNC139_IN_SEL_S)) +#define GPIO_FUNC139_IN_SEL_V 0x3F +#define GPIO_FUNC139_IN_SEL_S 0 + +#define GPIO_FUNC140_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0360) + +/* GPIO_SIG140_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG140_IN_SEL (BIT(7)) +#define GPIO_SIG140_IN_SEL_M (BIT(7)) +#define GPIO_SIG140_IN_SEL_V 0x1 +#define GPIO_SIG140_IN_SEL_S 7 + +/* GPIO_FUNC140_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC140_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC140_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC140_IN_INV_SEL_V 0x1 +#define GPIO_FUNC140_IN_INV_SEL_S 6 + +/* GPIO_FUNC140_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC140_IN_SEL 0x0000003F +#define GPIO_FUNC140_IN_SEL_M ((GPIO_FUNC140_IN_SEL_V)<<(GPIO_FUNC140_IN_SEL_S)) +#define GPIO_FUNC140_IN_SEL_V 0x3F +#define GPIO_FUNC140_IN_SEL_S 0 + +#define GPIO_FUNC141_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0364) + +/* GPIO_SIG141_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG141_IN_SEL (BIT(7)) +#define GPIO_SIG141_IN_SEL_M (BIT(7)) +#define GPIO_SIG141_IN_SEL_V 0x1 +#define GPIO_SIG141_IN_SEL_S 7 + +/* GPIO_FUNC141_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC141_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC141_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC141_IN_INV_SEL_V 0x1 +#define GPIO_FUNC141_IN_INV_SEL_S 6 + +/* GPIO_FUNC141_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC141_IN_SEL 0x0000003F +#define GPIO_FUNC141_IN_SEL_M ((GPIO_FUNC141_IN_SEL_V)<<(GPIO_FUNC141_IN_SEL_S)) +#define GPIO_FUNC141_IN_SEL_V 0x3F +#define GPIO_FUNC141_IN_SEL_S 0 + +#define GPIO_FUNC142_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0368) + +/* GPIO_SIG142_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG142_IN_SEL (BIT(7)) +#define GPIO_SIG142_IN_SEL_M (BIT(7)) +#define GPIO_SIG142_IN_SEL_V 0x1 +#define GPIO_SIG142_IN_SEL_S 7 + +/* GPIO_FUNC142_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC142_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC142_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC142_IN_INV_SEL_V 0x1 +#define GPIO_FUNC142_IN_INV_SEL_S 6 + +/* GPIO_FUNC142_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC142_IN_SEL 0x0000003F +#define GPIO_FUNC142_IN_SEL_M ((GPIO_FUNC142_IN_SEL_V)<<(GPIO_FUNC142_IN_SEL_S)) +#define GPIO_FUNC142_IN_SEL_V 0x3F +#define GPIO_FUNC142_IN_SEL_S 0 + +#define GPIO_FUNC143_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x036c) + +/* GPIO_SIG143_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG143_IN_SEL (BIT(7)) +#define GPIO_SIG143_IN_SEL_M (BIT(7)) +#define GPIO_SIG143_IN_SEL_V 0x1 +#define GPIO_SIG143_IN_SEL_S 7 + +/* GPIO_FUNC143_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC143_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC143_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC143_IN_INV_SEL_V 0x1 +#define GPIO_FUNC143_IN_INV_SEL_S 6 + +/* GPIO_FUNC143_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC143_IN_SEL 0x0000003F +#define GPIO_FUNC143_IN_SEL_M ((GPIO_FUNC143_IN_SEL_V)<<(GPIO_FUNC143_IN_SEL_S)) +#define GPIO_FUNC143_IN_SEL_V 0x3F +#define GPIO_FUNC143_IN_SEL_S 0 + +#define GPIO_FUNC144_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0370) + +/* GPIO_SIG144_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG144_IN_SEL (BIT(7)) +#define GPIO_SIG144_IN_SEL_M (BIT(7)) +#define GPIO_SIG144_IN_SEL_V 0x1 +#define GPIO_SIG144_IN_SEL_S 7 + +/* GPIO_FUNC144_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC144_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC144_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC144_IN_INV_SEL_V 0x1 +#define GPIO_FUNC144_IN_INV_SEL_S 6 + +/* GPIO_FUNC144_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC144_IN_SEL 0x0000003F +#define GPIO_FUNC144_IN_SEL_M ((GPIO_FUNC144_IN_SEL_V)<<(GPIO_FUNC144_IN_SEL_S)) +#define GPIO_FUNC144_IN_SEL_V 0x3F +#define GPIO_FUNC144_IN_SEL_S 0 + +#define GPIO_FUNC145_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0374) + +/* GPIO_SIG145_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG145_IN_SEL (BIT(7)) +#define GPIO_SIG145_IN_SEL_M (BIT(7)) +#define GPIO_SIG145_IN_SEL_V 0x1 +#define GPIO_SIG145_IN_SEL_S 7 + +/* GPIO_FUNC145_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC145_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC145_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC145_IN_INV_SEL_V 0x1 +#define GPIO_FUNC145_IN_INV_SEL_S 6 + +/* GPIO_FUNC145_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC145_IN_SEL 0x0000003F +#define GPIO_FUNC145_IN_SEL_M ((GPIO_FUNC145_IN_SEL_V)<<(GPIO_FUNC145_IN_SEL_S)) +#define GPIO_FUNC145_IN_SEL_V 0x3F +#define GPIO_FUNC145_IN_SEL_S 0 + +#define GPIO_FUNC146_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0378) + +/* GPIO_SIG146_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG146_IN_SEL (BIT(7)) +#define GPIO_SIG146_IN_SEL_M (BIT(7)) +#define GPIO_SIG146_IN_SEL_V 0x1 +#define GPIO_SIG146_IN_SEL_S 7 + +/* GPIO_FUNC146_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC146_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC146_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC146_IN_INV_SEL_V 0x1 +#define GPIO_FUNC146_IN_INV_SEL_S 6 + +/* GPIO_FUNC146_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC146_IN_SEL 0x0000003F +#define GPIO_FUNC146_IN_SEL_M ((GPIO_FUNC146_IN_SEL_V)<<(GPIO_FUNC146_IN_SEL_S)) +#define GPIO_FUNC146_IN_SEL_V 0x3F +#define GPIO_FUNC146_IN_SEL_S 0 + +#define GPIO_FUNC147_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x037c) + +/* GPIO_SIG147_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG147_IN_SEL (BIT(7)) +#define GPIO_SIG147_IN_SEL_M (BIT(7)) +#define GPIO_SIG147_IN_SEL_V 0x1 +#define GPIO_SIG147_IN_SEL_S 7 + +/* GPIO_FUNC147_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC147_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC147_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC147_IN_INV_SEL_V 0x1 +#define GPIO_FUNC147_IN_INV_SEL_S 6 + +/* GPIO_FUNC147_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC147_IN_SEL 0x0000003F +#define GPIO_FUNC147_IN_SEL_M ((GPIO_FUNC147_IN_SEL_V)<<(GPIO_FUNC147_IN_SEL_S)) +#define GPIO_FUNC147_IN_SEL_V 0x3F +#define GPIO_FUNC147_IN_SEL_S 0 + +#define GPIO_FUNC148_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0380) + +/* GPIO_SIG148_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG148_IN_SEL (BIT(7)) +#define GPIO_SIG148_IN_SEL_M (BIT(7)) +#define GPIO_SIG148_IN_SEL_V 0x1 +#define GPIO_SIG148_IN_SEL_S 7 + +/* GPIO_FUNC148_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC148_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC148_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC148_IN_INV_SEL_V 0x1 +#define GPIO_FUNC148_IN_INV_SEL_S 6 + +/* GPIO_FUNC148_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC148_IN_SEL 0x0000003F +#define GPIO_FUNC148_IN_SEL_M ((GPIO_FUNC148_IN_SEL_V)<<(GPIO_FUNC148_IN_SEL_S)) +#define GPIO_FUNC148_IN_SEL_V 0x3F +#define GPIO_FUNC148_IN_SEL_S 0 + +#define GPIO_FUNC149_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0384) + +/* GPIO_SIG149_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG149_IN_SEL (BIT(7)) +#define GPIO_SIG149_IN_SEL_M (BIT(7)) +#define GPIO_SIG149_IN_SEL_V 0x1 +#define GPIO_SIG149_IN_SEL_S 7 + +/* GPIO_FUNC149_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC149_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC149_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC149_IN_INV_SEL_V 0x1 +#define GPIO_FUNC149_IN_INV_SEL_S 6 + +/* GPIO_FUNC149_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC149_IN_SEL 0x0000003F +#define GPIO_FUNC149_IN_SEL_M ((GPIO_FUNC149_IN_SEL_V)<<(GPIO_FUNC149_IN_SEL_S)) +#define GPIO_FUNC149_IN_SEL_V 0x3F +#define GPIO_FUNC149_IN_SEL_S 0 + +#define GPIO_FUNC150_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0388) + +/* GPIO_SIG150_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG150_IN_SEL (BIT(7)) +#define GPIO_SIG150_IN_SEL_M (BIT(7)) +#define GPIO_SIG150_IN_SEL_V 0x1 +#define GPIO_SIG150_IN_SEL_S 7 + +/* GPIO_FUNC150_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC150_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC150_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC150_IN_INV_SEL_V 0x1 +#define GPIO_FUNC150_IN_INV_SEL_S 6 + +/* GPIO_FUNC150_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC150_IN_SEL 0x0000003F +#define GPIO_FUNC150_IN_SEL_M ((GPIO_FUNC150_IN_SEL_V)<<(GPIO_FUNC150_IN_SEL_S)) +#define GPIO_FUNC150_IN_SEL_V 0x3F +#define GPIO_FUNC150_IN_SEL_S 0 + +#define GPIO_FUNC151_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x038c) + +/* GPIO_SIG151_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG151_IN_SEL (BIT(7)) +#define GPIO_SIG151_IN_SEL_M (BIT(7)) +#define GPIO_SIG151_IN_SEL_V 0x1 +#define GPIO_SIG151_IN_SEL_S 7 + +/* GPIO_FUNC151_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC151_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC151_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC151_IN_INV_SEL_V 0x1 +#define GPIO_FUNC151_IN_INV_SEL_S 6 + +/* GPIO_FUNC151_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC151_IN_SEL 0x0000003F +#define GPIO_FUNC151_IN_SEL_M ((GPIO_FUNC151_IN_SEL_V)<<(GPIO_FUNC151_IN_SEL_S)) +#define GPIO_FUNC151_IN_SEL_V 0x3F +#define GPIO_FUNC151_IN_SEL_S 0 + +#define GPIO_FUNC152_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0390) + +/* GPIO_SIG152_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG152_IN_SEL (BIT(7)) +#define GPIO_SIG152_IN_SEL_M (BIT(7)) +#define GPIO_SIG152_IN_SEL_V 0x1 +#define GPIO_SIG152_IN_SEL_S 7 + +/* GPIO_FUNC152_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC152_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC152_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC152_IN_INV_SEL_V 0x1 +#define GPIO_FUNC152_IN_INV_SEL_S 6 + +/* GPIO_FUNC152_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC152_IN_SEL 0x0000003F +#define GPIO_FUNC152_IN_SEL_M ((GPIO_FUNC152_IN_SEL_V)<<(GPIO_FUNC152_IN_SEL_S)) +#define GPIO_FUNC152_IN_SEL_V 0x3F +#define GPIO_FUNC152_IN_SEL_S 0 + +#define GPIO_FUNC153_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0394) + +/* GPIO_SIG153_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG153_IN_SEL (BIT(7)) +#define GPIO_SIG153_IN_SEL_M (BIT(7)) +#define GPIO_SIG153_IN_SEL_V 0x1 +#define GPIO_SIG153_IN_SEL_S 7 + +/* GPIO_FUNC153_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC153_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC153_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC153_IN_INV_SEL_V 0x1 +#define GPIO_FUNC153_IN_INV_SEL_S 6 + +/* GPIO_FUNC153_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC153_IN_SEL 0x0000003F +#define GPIO_FUNC153_IN_SEL_M ((GPIO_FUNC153_IN_SEL_V)<<(GPIO_FUNC153_IN_SEL_S)) +#define GPIO_FUNC153_IN_SEL_V 0x3F +#define GPIO_FUNC153_IN_SEL_S 0 + +#define GPIO_FUNC154_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0398) + +/* GPIO_SIG154_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG154_IN_SEL (BIT(7)) +#define GPIO_SIG154_IN_SEL_M (BIT(7)) +#define GPIO_SIG154_IN_SEL_V 0x1 +#define GPIO_SIG154_IN_SEL_S 7 + +/* GPIO_FUNC154_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC154_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC154_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC154_IN_INV_SEL_V 0x1 +#define GPIO_FUNC154_IN_INV_SEL_S 6 + +/* GPIO_FUNC154_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC154_IN_SEL 0x0000003F +#define GPIO_FUNC154_IN_SEL_M ((GPIO_FUNC154_IN_SEL_V)<<(GPIO_FUNC154_IN_SEL_S)) +#define GPIO_FUNC154_IN_SEL_V 0x3F +#define GPIO_FUNC154_IN_SEL_S 0 + +#define GPIO_FUNC155_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x039c) + +/* GPIO_SIG155_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG155_IN_SEL (BIT(7)) +#define GPIO_SIG155_IN_SEL_M (BIT(7)) +#define GPIO_SIG155_IN_SEL_V 0x1 +#define GPIO_SIG155_IN_SEL_S 7 + +/* GPIO_FUNC155_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC155_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC155_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC155_IN_INV_SEL_V 0x1 +#define GPIO_FUNC155_IN_INV_SEL_S 6 + +/* GPIO_FUNC155_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC155_IN_SEL 0x0000003F +#define GPIO_FUNC155_IN_SEL_M ((GPIO_FUNC155_IN_SEL_V)<<(GPIO_FUNC155_IN_SEL_S)) +#define GPIO_FUNC155_IN_SEL_V 0x3F +#define GPIO_FUNC155_IN_SEL_S 0 + +#define GPIO_FUNC156_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03a0) + +/* GPIO_SIG156_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG156_IN_SEL (BIT(7)) +#define GPIO_SIG156_IN_SEL_M (BIT(7)) +#define GPIO_SIG156_IN_SEL_V 0x1 +#define GPIO_SIG156_IN_SEL_S 7 + +/* GPIO_FUNC156_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC156_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC156_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC156_IN_INV_SEL_V 0x1 +#define GPIO_FUNC156_IN_INV_SEL_S 6 + +/* GPIO_FUNC156_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC156_IN_SEL 0x0000003F +#define GPIO_FUNC156_IN_SEL_M ((GPIO_FUNC156_IN_SEL_V)<<(GPIO_FUNC156_IN_SEL_S)) +#define GPIO_FUNC156_IN_SEL_V 0x3F +#define GPIO_FUNC156_IN_SEL_S 0 + +#define GPIO_FUNC157_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03a4) + +/* GPIO_SIG157_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG157_IN_SEL (BIT(7)) +#define GPIO_SIG157_IN_SEL_M (BIT(7)) +#define GPIO_SIG157_IN_SEL_V 0x1 +#define GPIO_SIG157_IN_SEL_S 7 + +/* GPIO_FUNC157_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC157_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC157_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC157_IN_INV_SEL_V 0x1 +#define GPIO_FUNC157_IN_INV_SEL_S 6 + +/* GPIO_FUNC157_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC157_IN_SEL 0x0000003F +#define GPIO_FUNC157_IN_SEL_M ((GPIO_FUNC157_IN_SEL_V)<<(GPIO_FUNC157_IN_SEL_S)) +#define GPIO_FUNC157_IN_SEL_V 0x3F +#define GPIO_FUNC157_IN_SEL_S 0 + +#define GPIO_FUNC158_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03a8) + +/* GPIO_SIG158_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG158_IN_SEL (BIT(7)) +#define GPIO_SIG158_IN_SEL_M (BIT(7)) +#define GPIO_SIG158_IN_SEL_V 0x1 +#define GPIO_SIG158_IN_SEL_S 7 + +/* GPIO_FUNC158_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC158_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC158_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC158_IN_INV_SEL_V 0x1 +#define GPIO_FUNC158_IN_INV_SEL_S 6 + +/* GPIO_FUNC158_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC158_IN_SEL 0x0000003F +#define GPIO_FUNC158_IN_SEL_M ((GPIO_FUNC158_IN_SEL_V)<<(GPIO_FUNC158_IN_SEL_S)) +#define GPIO_FUNC158_IN_SEL_V 0x3F +#define GPIO_FUNC158_IN_SEL_S 0 + +#define GPIO_FUNC159_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03ac) + +/* GPIO_SIG159_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG159_IN_SEL (BIT(7)) +#define GPIO_SIG159_IN_SEL_M (BIT(7)) +#define GPIO_SIG159_IN_SEL_V 0x1 +#define GPIO_SIG159_IN_SEL_S 7 + +/* GPIO_FUNC159_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC159_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC159_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC159_IN_INV_SEL_V 0x1 +#define GPIO_FUNC159_IN_INV_SEL_S 6 + +/* GPIO_FUNC159_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC159_IN_SEL 0x0000003F +#define GPIO_FUNC159_IN_SEL_M ((GPIO_FUNC159_IN_SEL_V)<<(GPIO_FUNC159_IN_SEL_S)) +#define GPIO_FUNC159_IN_SEL_V 0x3F +#define GPIO_FUNC159_IN_SEL_S 0 + +#define GPIO_FUNC160_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03b0) + +/* GPIO_SIG160_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG160_IN_SEL (BIT(7)) +#define GPIO_SIG160_IN_SEL_M (BIT(7)) +#define GPIO_SIG160_IN_SEL_V 0x1 +#define GPIO_SIG160_IN_SEL_S 7 + +/* GPIO_FUNC160_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC160_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC160_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC160_IN_INV_SEL_V 0x1 +#define GPIO_FUNC160_IN_INV_SEL_S 6 + +/* GPIO_FUNC160_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC160_IN_SEL 0x0000003F +#define GPIO_FUNC160_IN_SEL_M ((GPIO_FUNC160_IN_SEL_V)<<(GPIO_FUNC160_IN_SEL_S)) +#define GPIO_FUNC160_IN_SEL_V 0x3F +#define GPIO_FUNC160_IN_SEL_S 0 + +#define GPIO_FUNC161_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03b4) + +/* GPIO_SIG161_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG161_IN_SEL (BIT(7)) +#define GPIO_SIG161_IN_SEL_M (BIT(7)) +#define GPIO_SIG161_IN_SEL_V 0x1 +#define GPIO_SIG161_IN_SEL_S 7 + +/* GPIO_FUNC161_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC161_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC161_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC161_IN_INV_SEL_V 0x1 +#define GPIO_FUNC161_IN_INV_SEL_S 6 + +/* GPIO_FUNC161_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC161_IN_SEL 0x0000003F +#define GPIO_FUNC161_IN_SEL_M ((GPIO_FUNC161_IN_SEL_V)<<(GPIO_FUNC161_IN_SEL_S)) +#define GPIO_FUNC161_IN_SEL_V 0x3F +#define GPIO_FUNC161_IN_SEL_S 0 + +#define GPIO_FUNC162_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03b8) + +/* GPIO_SIG162_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG162_IN_SEL (BIT(7)) +#define GPIO_SIG162_IN_SEL_M (BIT(7)) +#define GPIO_SIG162_IN_SEL_V 0x1 +#define GPIO_SIG162_IN_SEL_S 7 + +/* GPIO_FUNC162_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC162_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC162_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC162_IN_INV_SEL_V 0x1 +#define GPIO_FUNC162_IN_INV_SEL_S 6 + +/* GPIO_FUNC162_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC162_IN_SEL 0x0000003F +#define GPIO_FUNC162_IN_SEL_M ((GPIO_FUNC162_IN_SEL_V)<<(GPIO_FUNC162_IN_SEL_S)) +#define GPIO_FUNC162_IN_SEL_V 0x3F +#define GPIO_FUNC162_IN_SEL_S 0 + +#define GPIO_FUNC163_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03bc) + +/* GPIO_SIG163_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG163_IN_SEL (BIT(7)) +#define GPIO_SIG163_IN_SEL_M (BIT(7)) +#define GPIO_SIG163_IN_SEL_V 0x1 +#define GPIO_SIG163_IN_SEL_S 7 + +/* GPIO_FUNC163_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC163_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC163_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC163_IN_INV_SEL_V 0x1 +#define GPIO_FUNC163_IN_INV_SEL_S 6 + +/* GPIO_FUNC163_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC163_IN_SEL 0x0000003F +#define GPIO_FUNC163_IN_SEL_M ((GPIO_FUNC163_IN_SEL_V)<<(GPIO_FUNC163_IN_SEL_S)) +#define GPIO_FUNC163_IN_SEL_V 0x3F +#define GPIO_FUNC163_IN_SEL_S 0 + +#define GPIO_FUNC164_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03c0) + +/* GPIO_SIG164_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG164_IN_SEL (BIT(7)) +#define GPIO_SIG164_IN_SEL_M (BIT(7)) +#define GPIO_SIG164_IN_SEL_V 0x1 +#define GPIO_SIG164_IN_SEL_S 7 + +/* GPIO_FUNC164_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC164_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC164_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC164_IN_INV_SEL_V 0x1 +#define GPIO_FUNC164_IN_INV_SEL_S 6 + +/* GPIO_FUNC164_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC164_IN_SEL 0x0000003F +#define GPIO_FUNC164_IN_SEL_M ((GPIO_FUNC164_IN_SEL_V)<<(GPIO_FUNC164_IN_SEL_S)) +#define GPIO_FUNC164_IN_SEL_V 0x3F +#define GPIO_FUNC164_IN_SEL_S 0 + +#define GPIO_FUNC165_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03c4) + +/* GPIO_SIG165_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG165_IN_SEL (BIT(7)) +#define GPIO_SIG165_IN_SEL_M (BIT(7)) +#define GPIO_SIG165_IN_SEL_V 0x1 +#define GPIO_SIG165_IN_SEL_S 7 + +/* GPIO_FUNC165_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC165_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC165_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC165_IN_INV_SEL_V 0x1 +#define GPIO_FUNC165_IN_INV_SEL_S 6 + +/* GPIO_FUNC165_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC165_IN_SEL 0x0000003F +#define GPIO_FUNC165_IN_SEL_M ((GPIO_FUNC165_IN_SEL_V)<<(GPIO_FUNC165_IN_SEL_S)) +#define GPIO_FUNC165_IN_SEL_V 0x3F +#define GPIO_FUNC165_IN_SEL_S 0 + +#define GPIO_FUNC166_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03c8) + +/* GPIO_SIG166_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG166_IN_SEL (BIT(7)) +#define GPIO_SIG166_IN_SEL_M (BIT(7)) +#define GPIO_SIG166_IN_SEL_V 0x1 +#define GPIO_SIG166_IN_SEL_S 7 + +/* GPIO_FUNC166_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC166_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC166_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC166_IN_INV_SEL_V 0x1 +#define GPIO_FUNC166_IN_INV_SEL_S 6 + +/* GPIO_FUNC166_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC166_IN_SEL 0x0000003F +#define GPIO_FUNC166_IN_SEL_M ((GPIO_FUNC166_IN_SEL_V)<<(GPIO_FUNC166_IN_SEL_S)) +#define GPIO_FUNC166_IN_SEL_V 0x3F +#define GPIO_FUNC166_IN_SEL_S 0 + +#define GPIO_FUNC167_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03cc) + +/* GPIO_SIG167_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG167_IN_SEL (BIT(7)) +#define GPIO_SIG167_IN_SEL_M (BIT(7)) +#define GPIO_SIG167_IN_SEL_V 0x1 +#define GPIO_SIG167_IN_SEL_S 7 + +/* GPIO_FUNC167_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC167_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC167_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC167_IN_INV_SEL_V 0x1 +#define GPIO_FUNC167_IN_INV_SEL_S 6 + +/* GPIO_FUNC167_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC167_IN_SEL 0x0000003F +#define GPIO_FUNC167_IN_SEL_M ((GPIO_FUNC167_IN_SEL_V)<<(GPIO_FUNC167_IN_SEL_S)) +#define GPIO_FUNC167_IN_SEL_V 0x3F +#define GPIO_FUNC167_IN_SEL_S 0 + +#define GPIO_FUNC168_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03d0) + +/* GPIO_SIG168_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG168_IN_SEL (BIT(7)) +#define GPIO_SIG168_IN_SEL_M (BIT(7)) +#define GPIO_SIG168_IN_SEL_V 0x1 +#define GPIO_SIG168_IN_SEL_S 7 + +/* GPIO_FUNC168_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC168_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC168_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC168_IN_INV_SEL_V 0x1 +#define GPIO_FUNC168_IN_INV_SEL_S 6 + +/* GPIO_FUNC168_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC168_IN_SEL 0x0000003F +#define GPIO_FUNC168_IN_SEL_M ((GPIO_FUNC168_IN_SEL_V)<<(GPIO_FUNC168_IN_SEL_S)) +#define GPIO_FUNC168_IN_SEL_V 0x3F +#define GPIO_FUNC168_IN_SEL_S 0 + +#define GPIO_FUNC169_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03d4) + +/* GPIO_SIG169_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG169_IN_SEL (BIT(7)) +#define GPIO_SIG169_IN_SEL_M (BIT(7)) +#define GPIO_SIG169_IN_SEL_V 0x1 +#define GPIO_SIG169_IN_SEL_S 7 + +/* GPIO_FUNC169_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC169_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC169_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC169_IN_INV_SEL_V 0x1 +#define GPIO_FUNC169_IN_INV_SEL_S 6 + +/* GPIO_FUNC169_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC169_IN_SEL 0x0000003F +#define GPIO_FUNC169_IN_SEL_M ((GPIO_FUNC169_IN_SEL_V)<<(GPIO_FUNC169_IN_SEL_S)) +#define GPIO_FUNC169_IN_SEL_V 0x3F +#define GPIO_FUNC169_IN_SEL_S 0 + +#define GPIO_FUNC170_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03d8) + +/* GPIO_SIG170_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG170_IN_SEL (BIT(7)) +#define GPIO_SIG170_IN_SEL_M (BIT(7)) +#define GPIO_SIG170_IN_SEL_V 0x1 +#define GPIO_SIG170_IN_SEL_S 7 + +/* GPIO_FUNC170_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC170_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC170_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC170_IN_INV_SEL_V 0x1 +#define GPIO_FUNC170_IN_INV_SEL_S 6 + +/* GPIO_FUNC170_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC170_IN_SEL 0x0000003F +#define GPIO_FUNC170_IN_SEL_M ((GPIO_FUNC170_IN_SEL_V)<<(GPIO_FUNC170_IN_SEL_S)) +#define GPIO_FUNC170_IN_SEL_V 0x3F +#define GPIO_FUNC170_IN_SEL_S 0 + +#define GPIO_FUNC171_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03dc) + +/* GPIO_SIG171_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG171_IN_SEL (BIT(7)) +#define GPIO_SIG171_IN_SEL_M (BIT(7)) +#define GPIO_SIG171_IN_SEL_V 0x1 +#define GPIO_SIG171_IN_SEL_S 7 + +/* GPIO_FUNC171_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC171_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC171_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC171_IN_INV_SEL_V 0x1 +#define GPIO_FUNC171_IN_INV_SEL_S 6 + +/* GPIO_FUNC171_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC171_IN_SEL 0x0000003F +#define GPIO_FUNC171_IN_SEL_M ((GPIO_FUNC171_IN_SEL_V)<<(GPIO_FUNC171_IN_SEL_S)) +#define GPIO_FUNC171_IN_SEL_V 0x3F +#define GPIO_FUNC171_IN_SEL_S 0 + +#define GPIO_FUNC172_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03e0) + +/* GPIO_SIG172_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG172_IN_SEL (BIT(7)) +#define GPIO_SIG172_IN_SEL_M (BIT(7)) +#define GPIO_SIG172_IN_SEL_V 0x1 +#define GPIO_SIG172_IN_SEL_S 7 + +/* GPIO_FUNC172_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC172_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC172_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC172_IN_INV_SEL_V 0x1 +#define GPIO_FUNC172_IN_INV_SEL_S 6 + +/* GPIO_FUNC172_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC172_IN_SEL 0x0000003F +#define GPIO_FUNC172_IN_SEL_M ((GPIO_FUNC172_IN_SEL_V)<<(GPIO_FUNC172_IN_SEL_S)) +#define GPIO_FUNC172_IN_SEL_V 0x3F +#define GPIO_FUNC172_IN_SEL_S 0 + +#define GPIO_FUNC173_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03e4) + +/* GPIO_SIG173_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG173_IN_SEL (BIT(7)) +#define GPIO_SIG173_IN_SEL_M (BIT(7)) +#define GPIO_SIG173_IN_SEL_V 0x1 +#define GPIO_SIG173_IN_SEL_S 7 + +/* GPIO_FUNC173_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC173_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC173_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC173_IN_INV_SEL_V 0x1 +#define GPIO_FUNC173_IN_INV_SEL_S 6 + +/* GPIO_FUNC173_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC173_IN_SEL 0x0000003F +#define GPIO_FUNC173_IN_SEL_M ((GPIO_FUNC173_IN_SEL_V)<<(GPIO_FUNC173_IN_SEL_S)) +#define GPIO_FUNC173_IN_SEL_V 0x3F +#define GPIO_FUNC173_IN_SEL_S 0 + +#define GPIO_FUNC174_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03e8) + +/* GPIO_SIG174_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG174_IN_SEL (BIT(7)) +#define GPIO_SIG174_IN_SEL_M (BIT(7)) +#define GPIO_SIG174_IN_SEL_V 0x1 +#define GPIO_SIG174_IN_SEL_S 7 + +/* GPIO_FUNC174_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC174_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC174_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC174_IN_INV_SEL_V 0x1 +#define GPIO_FUNC174_IN_INV_SEL_S 6 + +/* GPIO_FUNC174_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC174_IN_SEL 0x0000003F +#define GPIO_FUNC174_IN_SEL_M ((GPIO_FUNC174_IN_SEL_V)<<(GPIO_FUNC174_IN_SEL_S)) +#define GPIO_FUNC174_IN_SEL_V 0x3F +#define GPIO_FUNC174_IN_SEL_S 0 + +#define GPIO_FUNC175_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03ec) + +/* GPIO_SIG175_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG175_IN_SEL (BIT(7)) +#define GPIO_SIG175_IN_SEL_M (BIT(7)) +#define GPIO_SIG175_IN_SEL_V 0x1 +#define GPIO_SIG175_IN_SEL_S 7 + +/* GPIO_FUNC175_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC175_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC175_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC175_IN_INV_SEL_V 0x1 +#define GPIO_FUNC175_IN_INV_SEL_S 6 + +/* GPIO_FUNC175_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC175_IN_SEL 0x0000003F +#define GPIO_FUNC175_IN_SEL_M ((GPIO_FUNC175_IN_SEL_V)<<(GPIO_FUNC175_IN_SEL_S)) +#define GPIO_FUNC175_IN_SEL_V 0x3F +#define GPIO_FUNC175_IN_SEL_S 0 + +#define GPIO_FUNC176_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03f0) + +/* GPIO_SIG176_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG176_IN_SEL (BIT(7)) +#define GPIO_SIG176_IN_SEL_M (BIT(7)) +#define GPIO_SIG176_IN_SEL_V 0x1 +#define GPIO_SIG176_IN_SEL_S 7 + +/* GPIO_FUNC176_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC176_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC176_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC176_IN_INV_SEL_V 0x1 +#define GPIO_FUNC176_IN_INV_SEL_S 6 + +/* GPIO_FUNC176_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC176_IN_SEL 0x0000003F +#define GPIO_FUNC176_IN_SEL_M ((GPIO_FUNC176_IN_SEL_V)<<(GPIO_FUNC176_IN_SEL_S)) +#define GPIO_FUNC176_IN_SEL_V 0x3F +#define GPIO_FUNC176_IN_SEL_S 0 + +#define GPIO_FUNC177_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03f4) + +/* GPIO_SIG177_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG177_IN_SEL (BIT(7)) +#define GPIO_SIG177_IN_SEL_M (BIT(7)) +#define GPIO_SIG177_IN_SEL_V 0x1 +#define GPIO_SIG177_IN_SEL_S 7 + +/* GPIO_FUNC177_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC177_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC177_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC177_IN_INV_SEL_V 0x1 +#define GPIO_FUNC177_IN_INV_SEL_S 6 + +/* GPIO_FUNC177_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC177_IN_SEL 0x0000003F +#define GPIO_FUNC177_IN_SEL_M ((GPIO_FUNC177_IN_SEL_V)<<(GPIO_FUNC177_IN_SEL_S)) +#define GPIO_FUNC177_IN_SEL_V 0x3F +#define GPIO_FUNC177_IN_SEL_S 0 + +#define GPIO_FUNC178_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03f8) + +/* GPIO_SIG178_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG178_IN_SEL (BIT(7)) +#define GPIO_SIG178_IN_SEL_M (BIT(7)) +#define GPIO_SIG178_IN_SEL_V 0x1 +#define GPIO_SIG178_IN_SEL_S 7 + +/* GPIO_FUNC178_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC178_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC178_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC178_IN_INV_SEL_V 0x1 +#define GPIO_FUNC178_IN_INV_SEL_S 6 + +/* GPIO_FUNC178_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC178_IN_SEL 0x0000003F +#define GPIO_FUNC178_IN_SEL_M ((GPIO_FUNC178_IN_SEL_V)<<(GPIO_FUNC178_IN_SEL_S)) +#define GPIO_FUNC178_IN_SEL_V 0x3F +#define GPIO_FUNC178_IN_SEL_S 0 + +#define GPIO_FUNC179_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03fc) + +/* GPIO_SIG179_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG179_IN_SEL (BIT(7)) +#define GPIO_SIG179_IN_SEL_M (BIT(7)) +#define GPIO_SIG179_IN_SEL_V 0x1 +#define GPIO_SIG179_IN_SEL_S 7 + +/* GPIO_FUNC179_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC179_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC179_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC179_IN_INV_SEL_V 0x1 +#define GPIO_FUNC179_IN_INV_SEL_S 6 + +/* GPIO_FUNC179_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC179_IN_SEL 0x0000003F +#define GPIO_FUNC179_IN_SEL_M ((GPIO_FUNC179_IN_SEL_V)<<(GPIO_FUNC179_IN_SEL_S)) +#define GPIO_FUNC179_IN_SEL_V 0x3F +#define GPIO_FUNC179_IN_SEL_S 0 + +#define GPIO_FUNC180_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0400) + +/* GPIO_SIG180_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG180_IN_SEL (BIT(7)) +#define GPIO_SIG180_IN_SEL_M (BIT(7)) +#define GPIO_SIG180_IN_SEL_V 0x1 +#define GPIO_SIG180_IN_SEL_S 7 + +/* GPIO_FUNC180_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC180_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC180_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC180_IN_INV_SEL_V 0x1 +#define GPIO_FUNC180_IN_INV_SEL_S 6 + +/* GPIO_FUNC180_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC180_IN_SEL 0x0000003F +#define GPIO_FUNC180_IN_SEL_M ((GPIO_FUNC180_IN_SEL_V)<<(GPIO_FUNC180_IN_SEL_S)) +#define GPIO_FUNC180_IN_SEL_V 0x3F +#define GPIO_FUNC180_IN_SEL_S 0 + +#define GPIO_FUNC181_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0404) + +/* GPIO_SIG181_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG181_IN_SEL (BIT(7)) +#define GPIO_SIG181_IN_SEL_M (BIT(7)) +#define GPIO_SIG181_IN_SEL_V 0x1 +#define GPIO_SIG181_IN_SEL_S 7 + +/* GPIO_FUNC181_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC181_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC181_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC181_IN_INV_SEL_V 0x1 +#define GPIO_FUNC181_IN_INV_SEL_S 6 + +/* GPIO_FUNC181_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC181_IN_SEL 0x0000003F +#define GPIO_FUNC181_IN_SEL_M ((GPIO_FUNC181_IN_SEL_V)<<(GPIO_FUNC181_IN_SEL_S)) +#define GPIO_FUNC181_IN_SEL_V 0x3F +#define GPIO_FUNC181_IN_SEL_S 0 + +#define GPIO_FUNC182_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0408) + +/* GPIO_SIG182_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG182_IN_SEL (BIT(7)) +#define GPIO_SIG182_IN_SEL_M (BIT(7)) +#define GPIO_SIG182_IN_SEL_V 0x1 +#define GPIO_SIG182_IN_SEL_S 7 + +/* GPIO_FUNC182_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC182_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC182_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC182_IN_INV_SEL_V 0x1 +#define GPIO_FUNC182_IN_INV_SEL_S 6 + +/* GPIO_FUNC182_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC182_IN_SEL 0x0000003F +#define GPIO_FUNC182_IN_SEL_M ((GPIO_FUNC182_IN_SEL_V)<<(GPIO_FUNC182_IN_SEL_S)) +#define GPIO_FUNC182_IN_SEL_V 0x3F +#define GPIO_FUNC182_IN_SEL_S 0 + +#define GPIO_FUNC183_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x040c) + +/* GPIO_SIG183_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG183_IN_SEL (BIT(7)) +#define GPIO_SIG183_IN_SEL_M (BIT(7)) +#define GPIO_SIG183_IN_SEL_V 0x1 +#define GPIO_SIG183_IN_SEL_S 7 + +/* GPIO_FUNC183_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC183_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC183_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC183_IN_INV_SEL_V 0x1 +#define GPIO_FUNC183_IN_INV_SEL_S 6 + +/* GPIO_FUNC183_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC183_IN_SEL 0x0000003F +#define GPIO_FUNC183_IN_SEL_M ((GPIO_FUNC183_IN_SEL_V)<<(GPIO_FUNC183_IN_SEL_S)) +#define GPIO_FUNC183_IN_SEL_V 0x3F +#define GPIO_FUNC183_IN_SEL_S 0 + +#define GPIO_FUNC184_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0410) + +/* GPIO_SIG184_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG184_IN_SEL (BIT(7)) +#define GPIO_SIG184_IN_SEL_M (BIT(7)) +#define GPIO_SIG184_IN_SEL_V 0x1 +#define GPIO_SIG184_IN_SEL_S 7 + +/* GPIO_FUNC184_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC184_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC184_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC184_IN_INV_SEL_V 0x1 +#define GPIO_FUNC184_IN_INV_SEL_S 6 + +/* GPIO_FUNC184_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC184_IN_SEL 0x0000003F +#define GPIO_FUNC184_IN_SEL_M ((GPIO_FUNC184_IN_SEL_V)<<(GPIO_FUNC184_IN_SEL_S)) +#define GPIO_FUNC184_IN_SEL_V 0x3F +#define GPIO_FUNC184_IN_SEL_S 0 + +#define GPIO_FUNC185_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0414) + +/* GPIO_SIG185_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG185_IN_SEL (BIT(7)) +#define GPIO_SIG185_IN_SEL_M (BIT(7)) +#define GPIO_SIG185_IN_SEL_V 0x1 +#define GPIO_SIG185_IN_SEL_S 7 + +/* GPIO_FUNC185_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC185_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC185_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC185_IN_INV_SEL_V 0x1 +#define GPIO_FUNC185_IN_INV_SEL_S 6 + +/* GPIO_FUNC185_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC185_IN_SEL 0x0000003F +#define GPIO_FUNC185_IN_SEL_M ((GPIO_FUNC185_IN_SEL_V)<<(GPIO_FUNC185_IN_SEL_S)) +#define GPIO_FUNC185_IN_SEL_V 0x3F +#define GPIO_FUNC185_IN_SEL_S 0 + +#define GPIO_FUNC186_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0418) + +/* GPIO_SIG186_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG186_IN_SEL (BIT(7)) +#define GPIO_SIG186_IN_SEL_M (BIT(7)) +#define GPIO_SIG186_IN_SEL_V 0x1 +#define GPIO_SIG186_IN_SEL_S 7 + +/* GPIO_FUNC186_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC186_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC186_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC186_IN_INV_SEL_V 0x1 +#define GPIO_FUNC186_IN_INV_SEL_S 6 + +/* GPIO_FUNC186_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC186_IN_SEL 0x0000003F +#define GPIO_FUNC186_IN_SEL_M ((GPIO_FUNC186_IN_SEL_V)<<(GPIO_FUNC186_IN_SEL_S)) +#define GPIO_FUNC186_IN_SEL_V 0x3F +#define GPIO_FUNC186_IN_SEL_S 0 + +#define GPIO_FUNC187_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x041c) + +/* GPIO_SIG187_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG187_IN_SEL (BIT(7)) +#define GPIO_SIG187_IN_SEL_M (BIT(7)) +#define GPIO_SIG187_IN_SEL_V 0x1 +#define GPIO_SIG187_IN_SEL_S 7 + +/* GPIO_FUNC187_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC187_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC187_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC187_IN_INV_SEL_V 0x1 +#define GPIO_FUNC187_IN_INV_SEL_S 6 + +/* GPIO_FUNC187_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC187_IN_SEL 0x0000003F +#define GPIO_FUNC187_IN_SEL_M ((GPIO_FUNC187_IN_SEL_V)<<(GPIO_FUNC187_IN_SEL_S)) +#define GPIO_FUNC187_IN_SEL_V 0x3F +#define GPIO_FUNC187_IN_SEL_S 0 + +#define GPIO_FUNC188_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0420) + +/* GPIO_SIG188_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG188_IN_SEL (BIT(7)) +#define GPIO_SIG188_IN_SEL_M (BIT(7)) +#define GPIO_SIG188_IN_SEL_V 0x1 +#define GPIO_SIG188_IN_SEL_S 7 + +/* GPIO_FUNC188_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC188_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC188_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC188_IN_INV_SEL_V 0x1 +#define GPIO_FUNC188_IN_INV_SEL_S 6 + +/* GPIO_FUNC188_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC188_IN_SEL 0x0000003F +#define GPIO_FUNC188_IN_SEL_M ((GPIO_FUNC188_IN_SEL_V)<<(GPIO_FUNC188_IN_SEL_S)) +#define GPIO_FUNC188_IN_SEL_V 0x3F +#define GPIO_FUNC188_IN_SEL_S 0 + +#define GPIO_FUNC189_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0424) + +/* GPIO_SIG189_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG189_IN_SEL (BIT(7)) +#define GPIO_SIG189_IN_SEL_M (BIT(7)) +#define GPIO_SIG189_IN_SEL_V 0x1 +#define GPIO_SIG189_IN_SEL_S 7 + +/* GPIO_FUNC189_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC189_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC189_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC189_IN_INV_SEL_V 0x1 +#define GPIO_FUNC189_IN_INV_SEL_S 6 + +/* GPIO_FUNC189_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC189_IN_SEL 0x0000003F +#define GPIO_FUNC189_IN_SEL_M ((GPIO_FUNC189_IN_SEL_V)<<(GPIO_FUNC189_IN_SEL_S)) +#define GPIO_FUNC189_IN_SEL_V 0x3F +#define GPIO_FUNC189_IN_SEL_S 0 + +#define GPIO_FUNC190_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0428) + +/* GPIO_SIG190_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG190_IN_SEL (BIT(7)) +#define GPIO_SIG190_IN_SEL_M (BIT(7)) +#define GPIO_SIG190_IN_SEL_V 0x1 +#define GPIO_SIG190_IN_SEL_S 7 + +/* GPIO_FUNC190_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC190_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC190_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC190_IN_INV_SEL_V 0x1 +#define GPIO_FUNC190_IN_INV_SEL_S 6 + +/* GPIO_FUNC190_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC190_IN_SEL 0x0000003F +#define GPIO_FUNC190_IN_SEL_M ((GPIO_FUNC190_IN_SEL_V)<<(GPIO_FUNC190_IN_SEL_S)) +#define GPIO_FUNC190_IN_SEL_V 0x3F +#define GPIO_FUNC190_IN_SEL_S 0 + +#define GPIO_FUNC191_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x042c) + +/* GPIO_SIG191_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG191_IN_SEL (BIT(7)) +#define GPIO_SIG191_IN_SEL_M (BIT(7)) +#define GPIO_SIG191_IN_SEL_V 0x1 +#define GPIO_SIG191_IN_SEL_S 7 + +/* GPIO_FUNC191_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC191_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC191_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC191_IN_INV_SEL_V 0x1 +#define GPIO_FUNC191_IN_INV_SEL_S 6 + +/* GPIO_FUNC191_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC191_IN_SEL 0x0000003F +#define GPIO_FUNC191_IN_SEL_M ((GPIO_FUNC191_IN_SEL_V)<<(GPIO_FUNC191_IN_SEL_S)) +#define GPIO_FUNC191_IN_SEL_V 0x3F +#define GPIO_FUNC191_IN_SEL_S 0 + +#define GPIO_FUNC192_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0430) + +/* GPIO_SIG192_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG192_IN_SEL (BIT(7)) +#define GPIO_SIG192_IN_SEL_M (BIT(7)) +#define GPIO_SIG192_IN_SEL_V 0x1 +#define GPIO_SIG192_IN_SEL_S 7 + +/* GPIO_FUNC192_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC192_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC192_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC192_IN_INV_SEL_V 0x1 +#define GPIO_FUNC192_IN_INV_SEL_S 6 + +/* GPIO_FUNC192_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC192_IN_SEL 0x0000003F +#define GPIO_FUNC192_IN_SEL_M ((GPIO_FUNC192_IN_SEL_V)<<(GPIO_FUNC192_IN_SEL_S)) +#define GPIO_FUNC192_IN_SEL_V 0x3F +#define GPIO_FUNC192_IN_SEL_S 0 + +#define GPIO_FUNC193_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0434) + +/* GPIO_SIG193_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG193_IN_SEL (BIT(7)) +#define GPIO_SIG193_IN_SEL_M (BIT(7)) +#define GPIO_SIG193_IN_SEL_V 0x1 +#define GPIO_SIG193_IN_SEL_S 7 + +/* GPIO_FUNC193_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC193_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC193_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC193_IN_INV_SEL_V 0x1 +#define GPIO_FUNC193_IN_INV_SEL_S 6 + +/* GPIO_FUNC193_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC193_IN_SEL 0x0000003F +#define GPIO_FUNC193_IN_SEL_M ((GPIO_FUNC193_IN_SEL_V)<<(GPIO_FUNC193_IN_SEL_S)) +#define GPIO_FUNC193_IN_SEL_V 0x3F +#define GPIO_FUNC193_IN_SEL_S 0 + +#define GPIO_FUNC194_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0438) + +/* GPIO_SIG194_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG194_IN_SEL (BIT(7)) +#define GPIO_SIG194_IN_SEL_M (BIT(7)) +#define GPIO_SIG194_IN_SEL_V 0x1 +#define GPIO_SIG194_IN_SEL_S 7 + +/* GPIO_FUNC194_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC194_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC194_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC194_IN_INV_SEL_V 0x1 +#define GPIO_FUNC194_IN_INV_SEL_S 6 + +/* GPIO_FUNC194_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC194_IN_SEL 0x0000003F +#define GPIO_FUNC194_IN_SEL_M ((GPIO_FUNC194_IN_SEL_V)<<(GPIO_FUNC194_IN_SEL_S)) +#define GPIO_FUNC194_IN_SEL_V 0x3F +#define GPIO_FUNC194_IN_SEL_S 0 + +#define GPIO_FUNC195_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x043c) + +/* GPIO_SIG195_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG195_IN_SEL (BIT(7)) +#define GPIO_SIG195_IN_SEL_M (BIT(7)) +#define GPIO_SIG195_IN_SEL_V 0x1 +#define GPIO_SIG195_IN_SEL_S 7 + +/* GPIO_FUNC195_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC195_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC195_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC195_IN_INV_SEL_V 0x1 +#define GPIO_FUNC195_IN_INV_SEL_S 6 + +/* GPIO_FUNC195_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC195_IN_SEL 0x0000003F +#define GPIO_FUNC195_IN_SEL_M ((GPIO_FUNC195_IN_SEL_V)<<(GPIO_FUNC195_IN_SEL_S)) +#define GPIO_FUNC195_IN_SEL_V 0x3F +#define GPIO_FUNC195_IN_SEL_S 0 + +#define GPIO_FUNC196_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0440) + +/* GPIO_SIG196_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG196_IN_SEL (BIT(7)) +#define GPIO_SIG196_IN_SEL_M (BIT(7)) +#define GPIO_SIG196_IN_SEL_V 0x1 +#define GPIO_SIG196_IN_SEL_S 7 + +/* GPIO_FUNC196_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC196_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC196_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC196_IN_INV_SEL_V 0x1 +#define GPIO_FUNC196_IN_INV_SEL_S 6 + +/* GPIO_FUNC196_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC196_IN_SEL 0x0000003F +#define GPIO_FUNC196_IN_SEL_M ((GPIO_FUNC196_IN_SEL_V)<<(GPIO_FUNC196_IN_SEL_S)) +#define GPIO_FUNC196_IN_SEL_V 0x3F +#define GPIO_FUNC196_IN_SEL_S 0 + +#define GPIO_FUNC197_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0444) + +/* GPIO_SIG197_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG197_IN_SEL (BIT(7)) +#define GPIO_SIG197_IN_SEL_M (BIT(7)) +#define GPIO_SIG197_IN_SEL_V 0x1 +#define GPIO_SIG197_IN_SEL_S 7 + +/* GPIO_FUNC197_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC197_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC197_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC197_IN_INV_SEL_V 0x1 +#define GPIO_FUNC197_IN_INV_SEL_S 6 + +/* GPIO_FUNC197_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC197_IN_SEL 0x0000003F +#define GPIO_FUNC197_IN_SEL_M ((GPIO_FUNC197_IN_SEL_V)<<(GPIO_FUNC197_IN_SEL_S)) +#define GPIO_FUNC197_IN_SEL_V 0x3F +#define GPIO_FUNC197_IN_SEL_S 0 + +#define GPIO_FUNC198_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0448) + +/* GPIO_SIG198_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG198_IN_SEL (BIT(7)) +#define GPIO_SIG198_IN_SEL_M (BIT(7)) +#define GPIO_SIG198_IN_SEL_V 0x1 +#define GPIO_SIG198_IN_SEL_S 7 + +/* GPIO_FUNC198_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC198_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC198_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC198_IN_INV_SEL_V 0x1 +#define GPIO_FUNC198_IN_INV_SEL_S 6 + +/* GPIO_FUNC198_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC198_IN_SEL 0x0000003F +#define GPIO_FUNC198_IN_SEL_M ((GPIO_FUNC198_IN_SEL_V)<<(GPIO_FUNC198_IN_SEL_S)) +#define GPIO_FUNC198_IN_SEL_V 0x3F +#define GPIO_FUNC198_IN_SEL_S 0 + +#define GPIO_FUNC199_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x044c) + +/* GPIO_SIG199_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG199_IN_SEL (BIT(7)) +#define GPIO_SIG199_IN_SEL_M (BIT(7)) +#define GPIO_SIG199_IN_SEL_V 0x1 +#define GPIO_SIG199_IN_SEL_S 7 + +/* GPIO_FUNC199_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC199_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC199_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC199_IN_INV_SEL_V 0x1 +#define GPIO_FUNC199_IN_INV_SEL_S 6 + +/* GPIO_FUNC199_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC199_IN_SEL 0x0000003F +#define GPIO_FUNC199_IN_SEL_M ((GPIO_FUNC199_IN_SEL_V)<<(GPIO_FUNC199_IN_SEL_S)) +#define GPIO_FUNC199_IN_SEL_V 0x3F +#define GPIO_FUNC199_IN_SEL_S 0 + +#define GPIO_FUNC200_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0450) + +/* GPIO_SIG200_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG200_IN_SEL (BIT(7)) +#define GPIO_SIG200_IN_SEL_M (BIT(7)) +#define GPIO_SIG200_IN_SEL_V 0x1 +#define GPIO_SIG200_IN_SEL_S 7 + +/* GPIO_FUNC200_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC200_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC200_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC200_IN_INV_SEL_V 0x1 +#define GPIO_FUNC200_IN_INV_SEL_S 6 + +/* GPIO_FUNC200_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC200_IN_SEL 0x0000003F +#define GPIO_FUNC200_IN_SEL_M ((GPIO_FUNC200_IN_SEL_V)<<(GPIO_FUNC200_IN_SEL_S)) +#define GPIO_FUNC200_IN_SEL_V 0x3F +#define GPIO_FUNC200_IN_SEL_S 0 + +#define GPIO_FUNC201_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0454) + +/* GPIO_SIG201_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG201_IN_SEL (BIT(7)) +#define GPIO_SIG201_IN_SEL_M (BIT(7)) +#define GPIO_SIG201_IN_SEL_V 0x1 +#define GPIO_SIG201_IN_SEL_S 7 + +/* GPIO_FUNC201_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC201_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC201_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC201_IN_INV_SEL_V 0x1 +#define GPIO_FUNC201_IN_INV_SEL_S 6 + +/* GPIO_FUNC201_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC201_IN_SEL 0x0000003F +#define GPIO_FUNC201_IN_SEL_M ((GPIO_FUNC201_IN_SEL_V)<<(GPIO_FUNC201_IN_SEL_S)) +#define GPIO_FUNC201_IN_SEL_V 0x3F +#define GPIO_FUNC201_IN_SEL_S 0 + +#define GPIO_FUNC202_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0458) + +/* GPIO_SIG202_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG202_IN_SEL (BIT(7)) +#define GPIO_SIG202_IN_SEL_M (BIT(7)) +#define GPIO_SIG202_IN_SEL_V 0x1 +#define GPIO_SIG202_IN_SEL_S 7 + +/* GPIO_FUNC202_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC202_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC202_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC202_IN_INV_SEL_V 0x1 +#define GPIO_FUNC202_IN_INV_SEL_S 6 + +/* GPIO_FUNC202_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC202_IN_SEL 0x0000003F +#define GPIO_FUNC202_IN_SEL_M ((GPIO_FUNC202_IN_SEL_V)<<(GPIO_FUNC202_IN_SEL_S)) +#define GPIO_FUNC202_IN_SEL_V 0x3F +#define GPIO_FUNC202_IN_SEL_S 0 + +#define GPIO_FUNC203_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x045c) + +/* GPIO_SIG203_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG203_IN_SEL (BIT(7)) +#define GPIO_SIG203_IN_SEL_M (BIT(7)) +#define GPIO_SIG203_IN_SEL_V 0x1 +#define GPIO_SIG203_IN_SEL_S 7 + +/* GPIO_FUNC203_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC203_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC203_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC203_IN_INV_SEL_V 0x1 +#define GPIO_FUNC203_IN_INV_SEL_S 6 + +/* GPIO_FUNC203_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC203_IN_SEL 0x0000003F +#define GPIO_FUNC203_IN_SEL_M ((GPIO_FUNC203_IN_SEL_V)<<(GPIO_FUNC203_IN_SEL_S)) +#define GPIO_FUNC203_IN_SEL_V 0x3F +#define GPIO_FUNC203_IN_SEL_S 0 + +#define GPIO_FUNC204_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0460) + +/* GPIO_SIG204_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG204_IN_SEL (BIT(7)) +#define GPIO_SIG204_IN_SEL_M (BIT(7)) +#define GPIO_SIG204_IN_SEL_V 0x1 +#define GPIO_SIG204_IN_SEL_S 7 + +/* GPIO_FUNC204_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC204_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC204_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC204_IN_INV_SEL_V 0x1 +#define GPIO_FUNC204_IN_INV_SEL_S 6 + +/* GPIO_FUNC204_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC204_IN_SEL 0x0000003F +#define GPIO_FUNC204_IN_SEL_M ((GPIO_FUNC204_IN_SEL_V)<<(GPIO_FUNC204_IN_SEL_S)) +#define GPIO_FUNC204_IN_SEL_V 0x3F +#define GPIO_FUNC204_IN_SEL_S 0 + +#define GPIO_FUNC205_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0464) + +/* GPIO_SIG205_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG205_IN_SEL (BIT(7)) +#define GPIO_SIG205_IN_SEL_M (BIT(7)) +#define GPIO_SIG205_IN_SEL_V 0x1 +#define GPIO_SIG205_IN_SEL_S 7 + +/* GPIO_FUNC205_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC205_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC205_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC205_IN_INV_SEL_V 0x1 +#define GPIO_FUNC205_IN_INV_SEL_S 6 + +/* GPIO_FUNC205_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC205_IN_SEL 0x0000003F +#define GPIO_FUNC205_IN_SEL_M ((GPIO_FUNC205_IN_SEL_V)<<(GPIO_FUNC205_IN_SEL_S)) +#define GPIO_FUNC205_IN_SEL_V 0x3F +#define GPIO_FUNC205_IN_SEL_S 0 + +#define GPIO_FUNC206_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0468) + +/* GPIO_SIG206_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG206_IN_SEL (BIT(7)) +#define GPIO_SIG206_IN_SEL_M (BIT(7)) +#define GPIO_SIG206_IN_SEL_V 0x1 +#define GPIO_SIG206_IN_SEL_S 7 + +/* GPIO_FUNC206_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC206_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC206_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC206_IN_INV_SEL_V 0x1 +#define GPIO_FUNC206_IN_INV_SEL_S 6 + +/* GPIO_FUNC206_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC206_IN_SEL 0x0000003F +#define GPIO_FUNC206_IN_SEL_M ((GPIO_FUNC206_IN_SEL_V)<<(GPIO_FUNC206_IN_SEL_S)) +#define GPIO_FUNC206_IN_SEL_V 0x3F +#define GPIO_FUNC206_IN_SEL_S 0 + +#define GPIO_FUNC207_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x046c) + +/* GPIO_SIG207_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG207_IN_SEL (BIT(7)) +#define GPIO_SIG207_IN_SEL_M (BIT(7)) +#define GPIO_SIG207_IN_SEL_V 0x1 +#define GPIO_SIG207_IN_SEL_S 7 + +/* GPIO_FUNC207_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC207_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC207_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC207_IN_INV_SEL_V 0x1 +#define GPIO_FUNC207_IN_INV_SEL_S 6 + +/* GPIO_FUNC207_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC207_IN_SEL 0x0000003F +#define GPIO_FUNC207_IN_SEL_M ((GPIO_FUNC207_IN_SEL_V)<<(GPIO_FUNC207_IN_SEL_S)) +#define GPIO_FUNC207_IN_SEL_V 0x3F +#define GPIO_FUNC207_IN_SEL_S 0 + +#define GPIO_FUNC208_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0470) + +/* GPIO_SIG208_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG208_IN_SEL (BIT(7)) +#define GPIO_SIG208_IN_SEL_M (BIT(7)) +#define GPIO_SIG208_IN_SEL_V 0x1 +#define GPIO_SIG208_IN_SEL_S 7 + +/* GPIO_FUNC208_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC208_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC208_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC208_IN_INV_SEL_V 0x1 +#define GPIO_FUNC208_IN_INV_SEL_S 6 + +/* GPIO_FUNC208_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC208_IN_SEL 0x0000003F +#define GPIO_FUNC208_IN_SEL_M ((GPIO_FUNC208_IN_SEL_V)<<(GPIO_FUNC208_IN_SEL_S)) +#define GPIO_FUNC208_IN_SEL_V 0x3F +#define GPIO_FUNC208_IN_SEL_S 0 + +#define GPIO_FUNC209_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0474) + +/* GPIO_SIG209_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG209_IN_SEL (BIT(7)) +#define GPIO_SIG209_IN_SEL_M (BIT(7)) +#define GPIO_SIG209_IN_SEL_V 0x1 +#define GPIO_SIG209_IN_SEL_S 7 + +/* GPIO_FUNC209_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC209_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC209_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC209_IN_INV_SEL_V 0x1 +#define GPIO_FUNC209_IN_INV_SEL_S 6 + +/* GPIO_FUNC209_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC209_IN_SEL 0x0000003F +#define GPIO_FUNC209_IN_SEL_M ((GPIO_FUNC209_IN_SEL_V)<<(GPIO_FUNC209_IN_SEL_S)) +#define GPIO_FUNC209_IN_SEL_V 0x3F +#define GPIO_FUNC209_IN_SEL_S 0 + +#define GPIO_FUNC210_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0478) + +/* GPIO_SIG210_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG210_IN_SEL (BIT(7)) +#define GPIO_SIG210_IN_SEL_M (BIT(7)) +#define GPIO_SIG210_IN_SEL_V 0x1 +#define GPIO_SIG210_IN_SEL_S 7 + +/* GPIO_FUNC210_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC210_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC210_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC210_IN_INV_SEL_V 0x1 +#define GPIO_FUNC210_IN_INV_SEL_S 6 + +/* GPIO_FUNC210_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC210_IN_SEL 0x0000003F +#define GPIO_FUNC210_IN_SEL_M ((GPIO_FUNC210_IN_SEL_V)<<(GPIO_FUNC210_IN_SEL_S)) +#define GPIO_FUNC210_IN_SEL_V 0x3F +#define GPIO_FUNC210_IN_SEL_S 0 + +#define GPIO_FUNC211_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x047c) + +/* GPIO_SIG211_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG211_IN_SEL (BIT(7)) +#define GPIO_SIG211_IN_SEL_M (BIT(7)) +#define GPIO_SIG211_IN_SEL_V 0x1 +#define GPIO_SIG211_IN_SEL_S 7 + +/* GPIO_FUNC211_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC211_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC211_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC211_IN_INV_SEL_V 0x1 +#define GPIO_FUNC211_IN_INV_SEL_S 6 + +/* GPIO_FUNC211_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC211_IN_SEL 0x0000003F +#define GPIO_FUNC211_IN_SEL_M ((GPIO_FUNC211_IN_SEL_V)<<(GPIO_FUNC211_IN_SEL_S)) +#define GPIO_FUNC211_IN_SEL_V 0x3F +#define GPIO_FUNC211_IN_SEL_S 0 + +#define GPIO_FUNC212_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0480) + +/* GPIO_SIG212_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG212_IN_SEL (BIT(7)) +#define GPIO_SIG212_IN_SEL_M (BIT(7)) +#define GPIO_SIG212_IN_SEL_V 0x1 +#define GPIO_SIG212_IN_SEL_S 7 + +/* GPIO_FUNC212_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC212_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC212_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC212_IN_INV_SEL_V 0x1 +#define GPIO_FUNC212_IN_INV_SEL_S 6 + +/* GPIO_FUNC212_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC212_IN_SEL 0x0000003F +#define GPIO_FUNC212_IN_SEL_M ((GPIO_FUNC212_IN_SEL_V)<<(GPIO_FUNC212_IN_SEL_S)) +#define GPIO_FUNC212_IN_SEL_V 0x3F +#define GPIO_FUNC212_IN_SEL_S 0 + +#define GPIO_FUNC213_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0484) + +/* GPIO_SIG213_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG213_IN_SEL (BIT(7)) +#define GPIO_SIG213_IN_SEL_M (BIT(7)) +#define GPIO_SIG213_IN_SEL_V 0x1 +#define GPIO_SIG213_IN_SEL_S 7 + +/* GPIO_FUNC213_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC213_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC213_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC213_IN_INV_SEL_V 0x1 +#define GPIO_FUNC213_IN_INV_SEL_S 6 + +/* GPIO_FUNC213_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC213_IN_SEL 0x0000003F +#define GPIO_FUNC213_IN_SEL_M ((GPIO_FUNC213_IN_SEL_V)<<(GPIO_FUNC213_IN_SEL_S)) +#define GPIO_FUNC213_IN_SEL_V 0x3F +#define GPIO_FUNC213_IN_SEL_S 0 + +#define GPIO_FUNC214_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0488) + +/* GPIO_SIG214_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG214_IN_SEL (BIT(7)) +#define GPIO_SIG214_IN_SEL_M (BIT(7)) +#define GPIO_SIG214_IN_SEL_V 0x1 +#define GPIO_SIG214_IN_SEL_S 7 + +/* GPIO_FUNC214_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC214_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC214_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC214_IN_INV_SEL_V 0x1 +#define GPIO_FUNC214_IN_INV_SEL_S 6 + +/* GPIO_FUNC214_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC214_IN_SEL 0x0000003F +#define GPIO_FUNC214_IN_SEL_M ((GPIO_FUNC214_IN_SEL_V)<<(GPIO_FUNC214_IN_SEL_S)) +#define GPIO_FUNC214_IN_SEL_V 0x3F +#define GPIO_FUNC214_IN_SEL_S 0 + +#define GPIO_FUNC215_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x048c) + +/* GPIO_SIG215_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG215_IN_SEL (BIT(7)) +#define GPIO_SIG215_IN_SEL_M (BIT(7)) +#define GPIO_SIG215_IN_SEL_V 0x1 +#define GPIO_SIG215_IN_SEL_S 7 + +/* GPIO_FUNC215_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC215_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC215_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC215_IN_INV_SEL_V 0x1 +#define GPIO_FUNC215_IN_INV_SEL_S 6 + +/* GPIO_FUNC215_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC215_IN_SEL 0x0000003F +#define GPIO_FUNC215_IN_SEL_M ((GPIO_FUNC215_IN_SEL_V)<<(GPIO_FUNC215_IN_SEL_S)) +#define GPIO_FUNC215_IN_SEL_V 0x3F +#define GPIO_FUNC215_IN_SEL_S 0 + +#define GPIO_FUNC216_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0490) + +/* GPIO_SIG216_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG216_IN_SEL (BIT(7)) +#define GPIO_SIG216_IN_SEL_M (BIT(7)) +#define GPIO_SIG216_IN_SEL_V 0x1 +#define GPIO_SIG216_IN_SEL_S 7 + +/* GPIO_FUNC216_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC216_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC216_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC216_IN_INV_SEL_V 0x1 +#define GPIO_FUNC216_IN_INV_SEL_S 6 + +/* GPIO_FUNC216_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC216_IN_SEL 0x0000003F +#define GPIO_FUNC216_IN_SEL_M ((GPIO_FUNC216_IN_SEL_V)<<(GPIO_FUNC216_IN_SEL_S)) +#define GPIO_FUNC216_IN_SEL_V 0x3F +#define GPIO_FUNC216_IN_SEL_S 0 + +#define GPIO_FUNC217_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0494) + +/* GPIO_SIG217_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG217_IN_SEL (BIT(7)) +#define GPIO_SIG217_IN_SEL_M (BIT(7)) +#define GPIO_SIG217_IN_SEL_V 0x1 +#define GPIO_SIG217_IN_SEL_S 7 + +/* GPIO_FUNC217_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC217_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC217_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC217_IN_INV_SEL_V 0x1 +#define GPIO_FUNC217_IN_INV_SEL_S 6 + +/* GPIO_FUNC217_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC217_IN_SEL 0x0000003F +#define GPIO_FUNC217_IN_SEL_M ((GPIO_FUNC217_IN_SEL_V)<<(GPIO_FUNC217_IN_SEL_S)) +#define GPIO_FUNC217_IN_SEL_V 0x3F +#define GPIO_FUNC217_IN_SEL_S 0 + +#define GPIO_FUNC218_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0498) + +/* GPIO_SIG218_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG218_IN_SEL (BIT(7)) +#define GPIO_SIG218_IN_SEL_M (BIT(7)) +#define GPIO_SIG218_IN_SEL_V 0x1 +#define GPIO_SIG218_IN_SEL_S 7 + +/* GPIO_FUNC218_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC218_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC218_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC218_IN_INV_SEL_V 0x1 +#define GPIO_FUNC218_IN_INV_SEL_S 6 + +/* GPIO_FUNC218_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC218_IN_SEL 0x0000003F +#define GPIO_FUNC218_IN_SEL_M ((GPIO_FUNC218_IN_SEL_V)<<(GPIO_FUNC218_IN_SEL_S)) +#define GPIO_FUNC218_IN_SEL_V 0x3F +#define GPIO_FUNC218_IN_SEL_S 0 + +#define GPIO_FUNC219_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x049c) + +/* GPIO_SIG219_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG219_IN_SEL (BIT(7)) +#define GPIO_SIG219_IN_SEL_M (BIT(7)) +#define GPIO_SIG219_IN_SEL_V 0x1 +#define GPIO_SIG219_IN_SEL_S 7 + +/* GPIO_FUNC219_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC219_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC219_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC219_IN_INV_SEL_V 0x1 +#define GPIO_FUNC219_IN_INV_SEL_S 6 + +/* GPIO_FUNC219_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC219_IN_SEL 0x0000003F +#define GPIO_FUNC219_IN_SEL_M ((GPIO_FUNC219_IN_SEL_V)<<(GPIO_FUNC219_IN_SEL_S)) +#define GPIO_FUNC219_IN_SEL_V 0x3F +#define GPIO_FUNC219_IN_SEL_S 0 + +#define GPIO_FUNC220_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04a0) + +/* GPIO_SIG220_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG220_IN_SEL (BIT(7)) +#define GPIO_SIG220_IN_SEL_M (BIT(7)) +#define GPIO_SIG220_IN_SEL_V 0x1 +#define GPIO_SIG220_IN_SEL_S 7 + +/* GPIO_FUNC220_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC220_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC220_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC220_IN_INV_SEL_V 0x1 +#define GPIO_FUNC220_IN_INV_SEL_S 6 + +/* GPIO_FUNC220_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC220_IN_SEL 0x0000003F +#define GPIO_FUNC220_IN_SEL_M ((GPIO_FUNC220_IN_SEL_V)<<(GPIO_FUNC220_IN_SEL_S)) +#define GPIO_FUNC220_IN_SEL_V 0x3F +#define GPIO_FUNC220_IN_SEL_S 0 + +#define GPIO_FUNC221_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04a4) + +/* GPIO_SIG221_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG221_IN_SEL (BIT(7)) +#define GPIO_SIG221_IN_SEL_M (BIT(7)) +#define GPIO_SIG221_IN_SEL_V 0x1 +#define GPIO_SIG221_IN_SEL_S 7 + +/* GPIO_FUNC221_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC221_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC221_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC221_IN_INV_SEL_V 0x1 +#define GPIO_FUNC221_IN_INV_SEL_S 6 + +/* GPIO_FUNC221_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC221_IN_SEL 0x0000003F +#define GPIO_FUNC221_IN_SEL_M ((GPIO_FUNC221_IN_SEL_V)<<(GPIO_FUNC221_IN_SEL_S)) +#define GPIO_FUNC221_IN_SEL_V 0x3F +#define GPIO_FUNC221_IN_SEL_S 0 + +#define GPIO_FUNC222_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04a8) + +/* GPIO_SIG222_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG222_IN_SEL (BIT(7)) +#define GPIO_SIG222_IN_SEL_M (BIT(7)) +#define GPIO_SIG222_IN_SEL_V 0x1 +#define GPIO_SIG222_IN_SEL_S 7 + +/* GPIO_FUNC222_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC222_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC222_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC222_IN_INV_SEL_V 0x1 +#define GPIO_FUNC222_IN_INV_SEL_S 6 + +/* GPIO_FUNC222_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC222_IN_SEL 0x0000003F +#define GPIO_FUNC222_IN_SEL_M ((GPIO_FUNC222_IN_SEL_V)<<(GPIO_FUNC222_IN_SEL_S)) +#define GPIO_FUNC222_IN_SEL_V 0x3F +#define GPIO_FUNC222_IN_SEL_S 0 + +#define GPIO_FUNC223_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04ac) + +/* GPIO_SIG223_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG223_IN_SEL (BIT(7)) +#define GPIO_SIG223_IN_SEL_M (BIT(7)) +#define GPIO_SIG223_IN_SEL_V 0x1 +#define GPIO_SIG223_IN_SEL_S 7 + +/* GPIO_FUNC223_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC223_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC223_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC223_IN_INV_SEL_V 0x1 +#define GPIO_FUNC223_IN_INV_SEL_S 6 + +/* GPIO_FUNC223_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC223_IN_SEL 0x0000003F +#define GPIO_FUNC223_IN_SEL_M ((GPIO_FUNC223_IN_SEL_V)<<(GPIO_FUNC223_IN_SEL_S)) +#define GPIO_FUNC223_IN_SEL_V 0x3F +#define GPIO_FUNC223_IN_SEL_S 0 + +#define GPIO_FUNC224_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04b0) + +/* GPIO_SIG224_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG224_IN_SEL (BIT(7)) +#define GPIO_SIG224_IN_SEL_M (BIT(7)) +#define GPIO_SIG224_IN_SEL_V 0x1 +#define GPIO_SIG224_IN_SEL_S 7 + +/* GPIO_FUNC224_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC224_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC224_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC224_IN_INV_SEL_V 0x1 +#define GPIO_FUNC224_IN_INV_SEL_S 6 + +/* GPIO_FUNC224_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC224_IN_SEL 0x0000003F +#define GPIO_FUNC224_IN_SEL_M ((GPIO_FUNC224_IN_SEL_V)<<(GPIO_FUNC224_IN_SEL_S)) +#define GPIO_FUNC224_IN_SEL_V 0x3F +#define GPIO_FUNC224_IN_SEL_S 0 + +#define GPIO_FUNC225_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04b4) + +/* GPIO_SIG225_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG225_IN_SEL (BIT(7)) +#define GPIO_SIG225_IN_SEL_M (BIT(7)) +#define GPIO_SIG225_IN_SEL_V 0x1 +#define GPIO_SIG225_IN_SEL_S 7 + +/* GPIO_FUNC225_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC225_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC225_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC225_IN_INV_SEL_V 0x1 +#define GPIO_FUNC225_IN_INV_SEL_S 6 + +/* GPIO_FUNC225_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC225_IN_SEL 0x0000003F +#define GPIO_FUNC225_IN_SEL_M ((GPIO_FUNC225_IN_SEL_V)<<(GPIO_FUNC225_IN_SEL_S)) +#define GPIO_FUNC225_IN_SEL_V 0x3F +#define GPIO_FUNC225_IN_SEL_S 0 + +#define GPIO_FUNC226_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04b8) + +/* GPIO_SIG226_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG226_IN_SEL (BIT(7)) +#define GPIO_SIG226_IN_SEL_M (BIT(7)) +#define GPIO_SIG226_IN_SEL_V 0x1 +#define GPIO_SIG226_IN_SEL_S 7 + +/* GPIO_FUNC226_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC226_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC226_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC226_IN_INV_SEL_V 0x1 +#define GPIO_FUNC226_IN_INV_SEL_S 6 + +/* GPIO_FUNC226_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC226_IN_SEL 0x0000003F +#define GPIO_FUNC226_IN_SEL_M ((GPIO_FUNC226_IN_SEL_V)<<(GPIO_FUNC226_IN_SEL_S)) +#define GPIO_FUNC226_IN_SEL_V 0x3F +#define GPIO_FUNC226_IN_SEL_S 0 + +#define GPIO_FUNC227_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04bc) + +/* GPIO_SIG227_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG227_IN_SEL (BIT(7)) +#define GPIO_SIG227_IN_SEL_M (BIT(7)) +#define GPIO_SIG227_IN_SEL_V 0x1 +#define GPIO_SIG227_IN_SEL_S 7 + +/* GPIO_FUNC227_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC227_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC227_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC227_IN_INV_SEL_V 0x1 +#define GPIO_FUNC227_IN_INV_SEL_S 6 + +/* GPIO_FUNC227_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC227_IN_SEL 0x0000003F +#define GPIO_FUNC227_IN_SEL_M ((GPIO_FUNC227_IN_SEL_V)<<(GPIO_FUNC227_IN_SEL_S)) +#define GPIO_FUNC227_IN_SEL_V 0x3F +#define GPIO_FUNC227_IN_SEL_S 0 + +#define GPIO_FUNC228_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04c0) + +/* GPIO_SIG228_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG228_IN_SEL (BIT(7)) +#define GPIO_SIG228_IN_SEL_M (BIT(7)) +#define GPIO_SIG228_IN_SEL_V 0x1 +#define GPIO_SIG228_IN_SEL_S 7 + +/* GPIO_FUNC228_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC228_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC228_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC228_IN_INV_SEL_V 0x1 +#define GPIO_FUNC228_IN_INV_SEL_S 6 + +/* GPIO_FUNC228_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC228_IN_SEL 0x0000003F +#define GPIO_FUNC228_IN_SEL_M ((GPIO_FUNC228_IN_SEL_V)<<(GPIO_FUNC228_IN_SEL_S)) +#define GPIO_FUNC228_IN_SEL_V 0x3F +#define GPIO_FUNC228_IN_SEL_S 0 + +#define GPIO_FUNC229_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04c4) + +/* GPIO_SIG229_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG229_IN_SEL (BIT(7)) +#define GPIO_SIG229_IN_SEL_M (BIT(7)) +#define GPIO_SIG229_IN_SEL_V 0x1 +#define GPIO_SIG229_IN_SEL_S 7 + +/* GPIO_FUNC229_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC229_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC229_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC229_IN_INV_SEL_V 0x1 +#define GPIO_FUNC229_IN_INV_SEL_S 6 + +/* GPIO_FUNC229_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC229_IN_SEL 0x0000003F +#define GPIO_FUNC229_IN_SEL_M ((GPIO_FUNC229_IN_SEL_V)<<(GPIO_FUNC229_IN_SEL_S)) +#define GPIO_FUNC229_IN_SEL_V 0x3F +#define GPIO_FUNC229_IN_SEL_S 0 + +#define GPIO_FUNC230_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04c8) + +/* GPIO_SIG230_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG230_IN_SEL (BIT(7)) +#define GPIO_SIG230_IN_SEL_M (BIT(7)) +#define GPIO_SIG230_IN_SEL_V 0x1 +#define GPIO_SIG230_IN_SEL_S 7 + +/* GPIO_FUNC230_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC230_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC230_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC230_IN_INV_SEL_V 0x1 +#define GPIO_FUNC230_IN_INV_SEL_S 6 + +/* GPIO_FUNC230_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC230_IN_SEL 0x0000003F +#define GPIO_FUNC230_IN_SEL_M ((GPIO_FUNC230_IN_SEL_V)<<(GPIO_FUNC230_IN_SEL_S)) +#define GPIO_FUNC230_IN_SEL_V 0x3F +#define GPIO_FUNC230_IN_SEL_S 0 + +#define GPIO_FUNC231_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04cc) + +/* GPIO_SIG231_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG231_IN_SEL (BIT(7)) +#define GPIO_SIG231_IN_SEL_M (BIT(7)) +#define GPIO_SIG231_IN_SEL_V 0x1 +#define GPIO_SIG231_IN_SEL_S 7 + +/* GPIO_FUNC231_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC231_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC231_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC231_IN_INV_SEL_V 0x1 +#define GPIO_FUNC231_IN_INV_SEL_S 6 + +/* GPIO_FUNC231_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC231_IN_SEL 0x0000003F +#define GPIO_FUNC231_IN_SEL_M ((GPIO_FUNC231_IN_SEL_V)<<(GPIO_FUNC231_IN_SEL_S)) +#define GPIO_FUNC231_IN_SEL_V 0x3F +#define GPIO_FUNC231_IN_SEL_S 0 + +#define GPIO_FUNC232_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04d0) + +/* GPIO_SIG232_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG232_IN_SEL (BIT(7)) +#define GPIO_SIG232_IN_SEL_M (BIT(7)) +#define GPIO_SIG232_IN_SEL_V 0x1 +#define GPIO_SIG232_IN_SEL_S 7 + +/* GPIO_FUNC232_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC232_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC232_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC232_IN_INV_SEL_V 0x1 +#define GPIO_FUNC232_IN_INV_SEL_S 6 + +/* GPIO_FUNC232_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC232_IN_SEL 0x0000003F +#define GPIO_FUNC232_IN_SEL_M ((GPIO_FUNC232_IN_SEL_V)<<(GPIO_FUNC232_IN_SEL_S)) +#define GPIO_FUNC232_IN_SEL_V 0x3F +#define GPIO_FUNC232_IN_SEL_S 0 + +#define GPIO_FUNC233_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04d4) + +/* GPIO_SIG233_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG233_IN_SEL (BIT(7)) +#define GPIO_SIG233_IN_SEL_M (BIT(7)) +#define GPIO_SIG233_IN_SEL_V 0x1 +#define GPIO_SIG233_IN_SEL_S 7 + +/* GPIO_FUNC233_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC233_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC233_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC233_IN_INV_SEL_V 0x1 +#define GPIO_FUNC233_IN_INV_SEL_S 6 + +/* GPIO_FUNC233_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC233_IN_SEL 0x0000003F +#define GPIO_FUNC233_IN_SEL_M ((GPIO_FUNC233_IN_SEL_V)<<(GPIO_FUNC233_IN_SEL_S)) +#define GPIO_FUNC233_IN_SEL_V 0x3F +#define GPIO_FUNC233_IN_SEL_S 0 + +#define GPIO_FUNC234_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04d8) + +/* GPIO_SIG234_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG234_IN_SEL (BIT(7)) +#define GPIO_SIG234_IN_SEL_M (BIT(7)) +#define GPIO_SIG234_IN_SEL_V 0x1 +#define GPIO_SIG234_IN_SEL_S 7 + +/* GPIO_FUNC234_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC234_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC234_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC234_IN_INV_SEL_V 0x1 +#define GPIO_FUNC234_IN_INV_SEL_S 6 + +/* GPIO_FUNC234_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC234_IN_SEL 0x0000003F +#define GPIO_FUNC234_IN_SEL_M ((GPIO_FUNC234_IN_SEL_V)<<(GPIO_FUNC234_IN_SEL_S)) +#define GPIO_FUNC234_IN_SEL_V 0x3F +#define GPIO_FUNC234_IN_SEL_S 0 + +#define GPIO_FUNC235_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04dc) + +/* GPIO_SIG235_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG235_IN_SEL (BIT(7)) +#define GPIO_SIG235_IN_SEL_M (BIT(7)) +#define GPIO_SIG235_IN_SEL_V 0x1 +#define GPIO_SIG235_IN_SEL_S 7 + +/* GPIO_FUNC235_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC235_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC235_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC235_IN_INV_SEL_V 0x1 +#define GPIO_FUNC235_IN_INV_SEL_S 6 + +/* GPIO_FUNC235_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC235_IN_SEL 0x0000003F +#define GPIO_FUNC235_IN_SEL_M ((GPIO_FUNC235_IN_SEL_V)<<(GPIO_FUNC235_IN_SEL_S)) +#define GPIO_FUNC235_IN_SEL_V 0x3F +#define GPIO_FUNC235_IN_SEL_S 0 + +#define GPIO_FUNC236_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04e0) + +/* GPIO_SIG236_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG236_IN_SEL (BIT(7)) +#define GPIO_SIG236_IN_SEL_M (BIT(7)) +#define GPIO_SIG236_IN_SEL_V 0x1 +#define GPIO_SIG236_IN_SEL_S 7 + +/* GPIO_FUNC236_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC236_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC236_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC236_IN_INV_SEL_V 0x1 +#define GPIO_FUNC236_IN_INV_SEL_S 6 + +/* GPIO_FUNC236_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC236_IN_SEL 0x0000003F +#define GPIO_FUNC236_IN_SEL_M ((GPIO_FUNC236_IN_SEL_V)<<(GPIO_FUNC236_IN_SEL_S)) +#define GPIO_FUNC236_IN_SEL_V 0x3F +#define GPIO_FUNC236_IN_SEL_S 0 + +#define GPIO_FUNC237_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04e4) + +/* GPIO_SIG237_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG237_IN_SEL (BIT(7)) +#define GPIO_SIG237_IN_SEL_M (BIT(7)) +#define GPIO_SIG237_IN_SEL_V 0x1 +#define GPIO_SIG237_IN_SEL_S 7 + +/* GPIO_FUNC237_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC237_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC237_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC237_IN_INV_SEL_V 0x1 +#define GPIO_FUNC237_IN_INV_SEL_S 6 + +/* GPIO_FUNC237_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC237_IN_SEL 0x0000003F +#define GPIO_FUNC237_IN_SEL_M ((GPIO_FUNC237_IN_SEL_V)<<(GPIO_FUNC237_IN_SEL_S)) +#define GPIO_FUNC237_IN_SEL_V 0x3F +#define GPIO_FUNC237_IN_SEL_S 0 + +#define GPIO_FUNC238_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04e8) + +/* GPIO_SIG238_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG238_IN_SEL (BIT(7)) +#define GPIO_SIG238_IN_SEL_M (BIT(7)) +#define GPIO_SIG238_IN_SEL_V 0x1 +#define GPIO_SIG238_IN_SEL_S 7 + +/* GPIO_FUNC238_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC238_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC238_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC238_IN_INV_SEL_V 0x1 +#define GPIO_FUNC238_IN_INV_SEL_S 6 + +/* GPIO_FUNC238_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC238_IN_SEL 0x0000003F +#define GPIO_FUNC238_IN_SEL_M ((GPIO_FUNC238_IN_SEL_V)<<(GPIO_FUNC238_IN_SEL_S)) +#define GPIO_FUNC238_IN_SEL_V 0x3F +#define GPIO_FUNC238_IN_SEL_S 0 + +#define GPIO_FUNC239_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04ec) + +/* GPIO_SIG239_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG239_IN_SEL (BIT(7)) +#define GPIO_SIG239_IN_SEL_M (BIT(7)) +#define GPIO_SIG239_IN_SEL_V 0x1 +#define GPIO_SIG239_IN_SEL_S 7 + +/* GPIO_FUNC239_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC239_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC239_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC239_IN_INV_SEL_V 0x1 +#define GPIO_FUNC239_IN_INV_SEL_S 6 + +/* GPIO_FUNC239_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC239_IN_SEL 0x0000003F +#define GPIO_FUNC239_IN_SEL_M ((GPIO_FUNC239_IN_SEL_V)<<(GPIO_FUNC239_IN_SEL_S)) +#define GPIO_FUNC239_IN_SEL_V 0x3F +#define GPIO_FUNC239_IN_SEL_S 0 + +#define GPIO_FUNC240_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04f0) + +/* GPIO_SIG240_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG240_IN_SEL (BIT(7)) +#define GPIO_SIG240_IN_SEL_M (BIT(7)) +#define GPIO_SIG240_IN_SEL_V 0x1 +#define GPIO_SIG240_IN_SEL_S 7 + +/* GPIO_FUNC240_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC240_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC240_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC240_IN_INV_SEL_V 0x1 +#define GPIO_FUNC240_IN_INV_SEL_S 6 + +/* GPIO_FUNC240_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC240_IN_SEL 0x0000003F +#define GPIO_FUNC240_IN_SEL_M ((GPIO_FUNC240_IN_SEL_V)<<(GPIO_FUNC240_IN_SEL_S)) +#define GPIO_FUNC240_IN_SEL_V 0x3F +#define GPIO_FUNC240_IN_SEL_S 0 + +#define GPIO_FUNC241_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04f4) + +/* GPIO_SIG241_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG241_IN_SEL (BIT(7)) +#define GPIO_SIG241_IN_SEL_M (BIT(7)) +#define GPIO_SIG241_IN_SEL_V 0x1 +#define GPIO_SIG241_IN_SEL_S 7 + +/* GPIO_FUNC241_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC241_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC241_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC241_IN_INV_SEL_V 0x1 +#define GPIO_FUNC241_IN_INV_SEL_S 6 + +/* GPIO_FUNC241_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC241_IN_SEL 0x0000003F +#define GPIO_FUNC241_IN_SEL_M ((GPIO_FUNC241_IN_SEL_V)<<(GPIO_FUNC241_IN_SEL_S)) +#define GPIO_FUNC241_IN_SEL_V 0x3F +#define GPIO_FUNC241_IN_SEL_S 0 + +#define GPIO_FUNC242_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04f8) + +/* GPIO_SIG242_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG242_IN_SEL (BIT(7)) +#define GPIO_SIG242_IN_SEL_M (BIT(7)) +#define GPIO_SIG242_IN_SEL_V 0x1 +#define GPIO_SIG242_IN_SEL_S 7 + +/* GPIO_FUNC242_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC242_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC242_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC242_IN_INV_SEL_V 0x1 +#define GPIO_FUNC242_IN_INV_SEL_S 6 + +/* GPIO_FUNC242_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC242_IN_SEL 0x0000003F +#define GPIO_FUNC242_IN_SEL_M ((GPIO_FUNC242_IN_SEL_V)<<(GPIO_FUNC242_IN_SEL_S)) +#define GPIO_FUNC242_IN_SEL_V 0x3F +#define GPIO_FUNC242_IN_SEL_S 0 + +#define GPIO_FUNC243_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04fc) + +/* GPIO_SIG243_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG243_IN_SEL (BIT(7)) +#define GPIO_SIG243_IN_SEL_M (BIT(7)) +#define GPIO_SIG243_IN_SEL_V 0x1 +#define GPIO_SIG243_IN_SEL_S 7 + +/* GPIO_FUNC243_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC243_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC243_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC243_IN_INV_SEL_V 0x1 +#define GPIO_FUNC243_IN_INV_SEL_S 6 + +/* GPIO_FUNC243_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC243_IN_SEL 0x0000003F +#define GPIO_FUNC243_IN_SEL_M ((GPIO_FUNC243_IN_SEL_V)<<(GPIO_FUNC243_IN_SEL_S)) +#define GPIO_FUNC243_IN_SEL_V 0x3F +#define GPIO_FUNC243_IN_SEL_S 0 + +#define GPIO_FUNC244_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0500) + +/* GPIO_SIG244_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG244_IN_SEL (BIT(7)) +#define GPIO_SIG244_IN_SEL_M (BIT(7)) +#define GPIO_SIG244_IN_SEL_V 0x1 +#define GPIO_SIG244_IN_SEL_S 7 + +/* GPIO_FUNC244_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC244_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC244_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC244_IN_INV_SEL_V 0x1 +#define GPIO_FUNC244_IN_INV_SEL_S 6 + +/* GPIO_FUNC244_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC244_IN_SEL 0x0000003F +#define GPIO_FUNC244_IN_SEL_M ((GPIO_FUNC244_IN_SEL_V)<<(GPIO_FUNC244_IN_SEL_S)) +#define GPIO_FUNC244_IN_SEL_V 0x3F +#define GPIO_FUNC244_IN_SEL_S 0 + +#define GPIO_FUNC245_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0504) + +/* GPIO_SIG245_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG245_IN_SEL (BIT(7)) +#define GPIO_SIG245_IN_SEL_M (BIT(7)) +#define GPIO_SIG245_IN_SEL_V 0x1 +#define GPIO_SIG245_IN_SEL_S 7 + +/* GPIO_FUNC245_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC245_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC245_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC245_IN_INV_SEL_V 0x1 +#define GPIO_FUNC245_IN_INV_SEL_S 6 + +/* GPIO_FUNC245_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC245_IN_SEL 0x0000003F +#define GPIO_FUNC245_IN_SEL_M ((GPIO_FUNC245_IN_SEL_V)<<(GPIO_FUNC245_IN_SEL_S)) +#define GPIO_FUNC245_IN_SEL_V 0x3F +#define GPIO_FUNC245_IN_SEL_S 0 + +#define GPIO_FUNC246_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0508) + +/* GPIO_SIG246_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG246_IN_SEL (BIT(7)) +#define GPIO_SIG246_IN_SEL_M (BIT(7)) +#define GPIO_SIG246_IN_SEL_V 0x1 +#define GPIO_SIG246_IN_SEL_S 7 + +/* GPIO_FUNC246_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC246_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC246_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC246_IN_INV_SEL_V 0x1 +#define GPIO_FUNC246_IN_INV_SEL_S 6 + +/* GPIO_FUNC246_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC246_IN_SEL 0x0000003F +#define GPIO_FUNC246_IN_SEL_M ((GPIO_FUNC246_IN_SEL_V)<<(GPIO_FUNC246_IN_SEL_S)) +#define GPIO_FUNC246_IN_SEL_V 0x3F +#define GPIO_FUNC246_IN_SEL_S 0 + +#define GPIO_FUNC247_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x050c) + +/* GPIO_SIG247_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG247_IN_SEL (BIT(7)) +#define GPIO_SIG247_IN_SEL_M (BIT(7)) +#define GPIO_SIG247_IN_SEL_V 0x1 +#define GPIO_SIG247_IN_SEL_S 7 + +/* GPIO_FUNC247_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC247_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC247_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC247_IN_INV_SEL_V 0x1 +#define GPIO_FUNC247_IN_INV_SEL_S 6 + +/* GPIO_FUNC247_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC247_IN_SEL 0x0000003F +#define GPIO_FUNC247_IN_SEL_M ((GPIO_FUNC247_IN_SEL_V)<<(GPIO_FUNC247_IN_SEL_S)) +#define GPIO_FUNC247_IN_SEL_V 0x3F +#define GPIO_FUNC247_IN_SEL_S 0 + +#define GPIO_FUNC248_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0510) + +/* GPIO_SIG248_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG248_IN_SEL (BIT(7)) +#define GPIO_SIG248_IN_SEL_M (BIT(7)) +#define GPIO_SIG248_IN_SEL_V 0x1 +#define GPIO_SIG248_IN_SEL_S 7 + +/* GPIO_FUNC248_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC248_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC248_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC248_IN_INV_SEL_V 0x1 +#define GPIO_FUNC248_IN_INV_SEL_S 6 + +/* GPIO_FUNC248_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC248_IN_SEL 0x0000003F +#define GPIO_FUNC248_IN_SEL_M ((GPIO_FUNC248_IN_SEL_V)<<(GPIO_FUNC248_IN_SEL_S)) +#define GPIO_FUNC248_IN_SEL_V 0x3F +#define GPIO_FUNC248_IN_SEL_S 0 + +#define GPIO_FUNC249_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0514) + +/* GPIO_SIG249_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG249_IN_SEL (BIT(7)) +#define GPIO_SIG249_IN_SEL_M (BIT(7)) +#define GPIO_SIG249_IN_SEL_V 0x1 +#define GPIO_SIG249_IN_SEL_S 7 + +/* GPIO_FUNC249_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC249_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC249_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC249_IN_INV_SEL_V 0x1 +#define GPIO_FUNC249_IN_INV_SEL_S 6 + +/* GPIO_FUNC249_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC249_IN_SEL 0x0000003F +#define GPIO_FUNC249_IN_SEL_M ((GPIO_FUNC249_IN_SEL_V)<<(GPIO_FUNC249_IN_SEL_S)) +#define GPIO_FUNC249_IN_SEL_V 0x3F +#define GPIO_FUNC249_IN_SEL_S 0 + +#define GPIO_FUNC250_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0518) + +/* GPIO_SIG250_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG250_IN_SEL (BIT(7)) +#define GPIO_SIG250_IN_SEL_M (BIT(7)) +#define GPIO_SIG250_IN_SEL_V 0x1 +#define GPIO_SIG250_IN_SEL_S 7 + +/* GPIO_FUNC250_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC250_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC250_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC250_IN_INV_SEL_V 0x1 +#define GPIO_FUNC250_IN_INV_SEL_S 6 + +/* GPIO_FUNC250_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC250_IN_SEL 0x0000003F +#define GPIO_FUNC250_IN_SEL_M ((GPIO_FUNC250_IN_SEL_V)<<(GPIO_FUNC250_IN_SEL_S)) +#define GPIO_FUNC250_IN_SEL_V 0x3F +#define GPIO_FUNC250_IN_SEL_S 0 + +#define GPIO_FUNC251_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x051c) + +/* GPIO_SIG251_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG251_IN_SEL (BIT(7)) +#define GPIO_SIG251_IN_SEL_M (BIT(7)) +#define GPIO_SIG251_IN_SEL_V 0x1 +#define GPIO_SIG251_IN_SEL_S 7 + +/* GPIO_FUNC251_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC251_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC251_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC251_IN_INV_SEL_V 0x1 +#define GPIO_FUNC251_IN_INV_SEL_S 6 + +/* GPIO_FUNC251_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC251_IN_SEL 0x0000003F +#define GPIO_FUNC251_IN_SEL_M ((GPIO_FUNC251_IN_SEL_V)<<(GPIO_FUNC251_IN_SEL_S)) +#define GPIO_FUNC251_IN_SEL_V 0x3F +#define GPIO_FUNC251_IN_SEL_S 0 + +#define GPIO_FUNC252_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0520) + +/* GPIO_SIG252_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG252_IN_SEL (BIT(7)) +#define GPIO_SIG252_IN_SEL_M (BIT(7)) +#define GPIO_SIG252_IN_SEL_V 0x1 +#define GPIO_SIG252_IN_SEL_S 7 + +/* GPIO_FUNC252_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC252_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC252_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC252_IN_INV_SEL_V 0x1 +#define GPIO_FUNC252_IN_INV_SEL_S 6 + +/* GPIO_FUNC252_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC252_IN_SEL 0x0000003F +#define GPIO_FUNC252_IN_SEL_M ((GPIO_FUNC252_IN_SEL_V)<<(GPIO_FUNC252_IN_SEL_S)) +#define GPIO_FUNC252_IN_SEL_V 0x3F +#define GPIO_FUNC252_IN_SEL_S 0 + +#define GPIO_FUNC253_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0524) + +/* GPIO_SIG253_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG253_IN_SEL (BIT(7)) +#define GPIO_SIG253_IN_SEL_M (BIT(7)) +#define GPIO_SIG253_IN_SEL_V 0x1 +#define GPIO_SIG253_IN_SEL_S 7 + +/* GPIO_FUNC253_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC253_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC253_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC253_IN_INV_SEL_V 0x1 +#define GPIO_FUNC253_IN_INV_SEL_S 6 + +/* GPIO_FUNC253_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC253_IN_SEL 0x0000003F +#define GPIO_FUNC253_IN_SEL_M ((GPIO_FUNC253_IN_SEL_V)<<(GPIO_FUNC253_IN_SEL_S)) +#define GPIO_FUNC253_IN_SEL_V 0x3F +#define GPIO_FUNC253_IN_SEL_S 0 + +#define GPIO_FUNC254_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0528) + +/* GPIO_SIG254_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG254_IN_SEL (BIT(7)) +#define GPIO_SIG254_IN_SEL_M (BIT(7)) +#define GPIO_SIG254_IN_SEL_V 0x1 +#define GPIO_SIG254_IN_SEL_S 7 + +/* GPIO_FUNC254_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC254_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC254_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC254_IN_INV_SEL_V 0x1 +#define GPIO_FUNC254_IN_INV_SEL_S 6 + +/* GPIO_FUNC254_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC254_IN_SEL 0x0000003F +#define GPIO_FUNC254_IN_SEL_M ((GPIO_FUNC254_IN_SEL_V)<<(GPIO_FUNC254_IN_SEL_S)) +#define GPIO_FUNC254_IN_SEL_V 0x3F +#define GPIO_FUNC254_IN_SEL_S 0 + +#define GPIO_FUNC255_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x052c) + +/* GPIO_SIG255_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ +/* Description: if the slow signal bypass the io matrix or not if you want setting + the value to 1 */ + +#define GPIO_SIG255_IN_SEL (BIT(7)) +#define GPIO_SIG255_IN_SEL_M (BIT(7)) +#define GPIO_SIG255_IN_SEL_V 0x1 +#define GPIO_SIG255_IN_SEL_S 7 + +/* GPIO_FUNC255_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ +/* Description: revert the value of the input if you want to revert please set the value to 1 */ + +#define GPIO_FUNC255_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC255_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC255_IN_INV_SEL_V 0x1 +#define GPIO_FUNC255_IN_INV_SEL_S 6 + +/* GPIO_FUNC255_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ +/* Description: select one of the 256 inputs */ + +#define GPIO_FUNC255_IN_SEL 0x0000003F +#define GPIO_FUNC255_IN_SEL_M ((GPIO_FUNC255_IN_SEL_V)<<(GPIO_FUNC255_IN_SEL_S)) +#define GPIO_FUNC255_IN_SEL_V 0x3F +#define GPIO_FUNC255_IN_SEL_S 0 + +#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0530) + +/* GPIO_FUNC0_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC0_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC0_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC0_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC0_OEN_INV_SEL_S 11 + +/* GPIO_FUNC0_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC0_OEN_SEL (BIT(10)) +#define GPIO_FUNC0_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC0_OEN_SEL_V 0x1 +#define GPIO_FUNC0_OEN_SEL_S 10 + +/* GPIO_FUNC0_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC0_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC0_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC0_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC0_OUT_INV_SEL_S 9 + +/* GPIO_FUNC0_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC0_OUT_SEL 0x000001FF +#define GPIO_FUNC0_OUT_SEL_M ((GPIO_FUNC0_OUT_SEL_V)<<(GPIO_FUNC0_OUT_SEL_S)) +#define GPIO_FUNC0_OUT_SEL_V 0x1FF +#define GPIO_FUNC0_OUT_SEL_S 0 + +#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0534) + +/* GPIO_FUNC1_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC1_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC1_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC1_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC1_OEN_INV_SEL_S 11 + +/* GPIO_FUNC1_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC1_OEN_SEL (BIT(10)) +#define GPIO_FUNC1_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC1_OEN_SEL_V 0x1 +#define GPIO_FUNC1_OEN_SEL_S 10 + +/* GPIO_FUNC1_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC1_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC1_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC1_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC1_OUT_INV_SEL_S 9 + +/* GPIO_FUNC1_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC1_OUT_SEL 0x000001FF +#define GPIO_FUNC1_OUT_SEL_M ((GPIO_FUNC1_OUT_SEL_V)<<(GPIO_FUNC1_OUT_SEL_S)) +#define GPIO_FUNC1_OUT_SEL_V 0x1FF +#define GPIO_FUNC1_OUT_SEL_S 0 + +#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0538) + +/* GPIO_FUNC2_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC2_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC2_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC2_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC2_OEN_INV_SEL_S 11 + +/* GPIO_FUNC2_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC2_OEN_SEL (BIT(10)) +#define GPIO_FUNC2_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC2_OEN_SEL_V 0x1 +#define GPIO_FUNC2_OEN_SEL_S 10 + +/* GPIO_FUNC2_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC2_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC2_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC2_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC2_OUT_INV_SEL_S 9 + +/* GPIO_FUNC2_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC2_OUT_SEL 0x000001FF +#define GPIO_FUNC2_OUT_SEL_M ((GPIO_FUNC2_OUT_SEL_V)<<(GPIO_FUNC2_OUT_SEL_S)) +#define GPIO_FUNC2_OUT_SEL_V 0x1FF +#define GPIO_FUNC2_OUT_SEL_S 0 + +#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x053c) + +/* GPIO_FUNC3_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC3_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC3_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC3_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC3_OEN_INV_SEL_S 11 + +/* GPIO_FUNC3_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC3_OEN_SEL (BIT(10)) +#define GPIO_FUNC3_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC3_OEN_SEL_V 0x1 +#define GPIO_FUNC3_OEN_SEL_S 10 + +/* GPIO_FUNC3_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC3_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC3_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC3_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC3_OUT_INV_SEL_S 9 + +/* GPIO_FUNC3_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC3_OUT_SEL 0x000001FF +#define GPIO_FUNC3_OUT_SEL_M ((GPIO_FUNC3_OUT_SEL_V)<<(GPIO_FUNC3_OUT_SEL_S)) +#define GPIO_FUNC3_OUT_SEL_V 0x1FF +#define GPIO_FUNC3_OUT_SEL_S 0 + +#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0540) + +/* GPIO_FUNC4_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC4_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC4_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC4_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC4_OEN_INV_SEL_S 11 + +/* GPIO_FUNC4_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC4_OEN_SEL (BIT(10)) +#define GPIO_FUNC4_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC4_OEN_SEL_V 0x1 +#define GPIO_FUNC4_OEN_SEL_S 10 + +/* GPIO_FUNC4_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC4_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC4_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC4_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC4_OUT_INV_SEL_S 9 + +/* GPIO_FUNC4_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC4_OUT_SEL 0x000001FF +#define GPIO_FUNC4_OUT_SEL_M ((GPIO_FUNC4_OUT_SEL_V)<<(GPIO_FUNC4_OUT_SEL_S)) +#define GPIO_FUNC4_OUT_SEL_V 0x1FF +#define GPIO_FUNC4_OUT_SEL_S 0 + +#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0544) + +/* GPIO_FUNC5_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC5_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC5_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC5_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC5_OEN_INV_SEL_S 11 + +/* GPIO_FUNC5_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC5_OEN_SEL (BIT(10)) +#define GPIO_FUNC5_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC5_OEN_SEL_V 0x1 +#define GPIO_FUNC5_OEN_SEL_S 10 + +/* GPIO_FUNC5_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC5_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC5_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC5_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC5_OUT_INV_SEL_S 9 + +/* GPIO_FUNC5_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC5_OUT_SEL 0x000001FF +#define GPIO_FUNC5_OUT_SEL_M ((GPIO_FUNC5_OUT_SEL_V)<<(GPIO_FUNC5_OUT_SEL_S)) +#define GPIO_FUNC5_OUT_SEL_V 0x1FF +#define GPIO_FUNC5_OUT_SEL_S 0 + +#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0548) + +/* GPIO_FUNC6_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC6_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC6_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC6_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC6_OEN_INV_SEL_S 11 + +/* GPIO_FUNC6_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC6_OEN_SEL (BIT(10)) +#define GPIO_FUNC6_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC6_OEN_SEL_V 0x1 +#define GPIO_FUNC6_OEN_SEL_S 10 + +/* GPIO_FUNC6_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC6_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC6_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC6_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC6_OUT_INV_SEL_S 9 + +/* GPIO_FUNC6_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC6_OUT_SEL 0x000001FF +#define GPIO_FUNC6_OUT_SEL_M ((GPIO_FUNC6_OUT_SEL_V)<<(GPIO_FUNC6_OUT_SEL_S)) +#define GPIO_FUNC6_OUT_SEL_V 0x1FF +#define GPIO_FUNC6_OUT_SEL_S 0 + +#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x054c) + +/* GPIO_FUNC7_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC7_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC7_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC7_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC7_OEN_INV_SEL_S 11 + +/* GPIO_FUNC7_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC7_OEN_SEL (BIT(10)) +#define GPIO_FUNC7_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC7_OEN_SEL_V 0x1 +#define GPIO_FUNC7_OEN_SEL_S 10 + +/* GPIO_FUNC7_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC7_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC7_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC7_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC7_OUT_INV_SEL_S 9 + +/* GPIO_FUNC7_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC7_OUT_SEL 0x000001FF +#define GPIO_FUNC7_OUT_SEL_M ((GPIO_FUNC7_OUT_SEL_V)<<(GPIO_FUNC7_OUT_SEL_S)) +#define GPIO_FUNC7_OUT_SEL_V 0x1FF +#define GPIO_FUNC7_OUT_SEL_S 0 + +#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0550) + +/* GPIO_FUNC8_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC8_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC8_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC8_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC8_OEN_INV_SEL_S 11 + +/* GPIO_FUNC8_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC8_OEN_SEL (BIT(10)) +#define GPIO_FUNC8_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC8_OEN_SEL_V 0x1 +#define GPIO_FUNC8_OEN_SEL_S 10 + +/* GPIO_FUNC8_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC8_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC8_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC8_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC8_OUT_INV_SEL_S 9 + +/* GPIO_FUNC8_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC8_OUT_SEL 0x000001FF +#define GPIO_FUNC8_OUT_SEL_M ((GPIO_FUNC8_OUT_SEL_V)<<(GPIO_FUNC8_OUT_SEL_S)) +#define GPIO_FUNC8_OUT_SEL_V 0x1FF +#define GPIO_FUNC8_OUT_SEL_S 0 + +#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0554) + +/* GPIO_FUNC9_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC9_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC9_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC9_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC9_OEN_INV_SEL_S 11 + +/* GPIO_FUNC9_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC9_OEN_SEL (BIT(10)) +#define GPIO_FUNC9_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC9_OEN_SEL_V 0x1 +#define GPIO_FUNC9_OEN_SEL_S 10 + +/* GPIO_FUNC9_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC9_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC9_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC9_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC9_OUT_INV_SEL_S 9 + +/* GPIO_FUNC9_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC9_OUT_SEL 0x000001FF +#define GPIO_FUNC9_OUT_SEL_M ((GPIO_FUNC9_OUT_SEL_V)<<(GPIO_FUNC9_OUT_SEL_S)) +#define GPIO_FUNC9_OUT_SEL_V 0x1FF +#define GPIO_FUNC9_OUT_SEL_S 0 + +#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0558) + +/* GPIO_FUNC10_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC10_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC10_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC10_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC10_OEN_INV_SEL_S 11 + +/* GPIO_FUNC10_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC10_OEN_SEL (BIT(10)) +#define GPIO_FUNC10_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC10_OEN_SEL_V 0x1 +#define GPIO_FUNC10_OEN_SEL_S 10 + +/* GPIO_FUNC10_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC10_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC10_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC10_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC10_OUT_INV_SEL_S 9 + +/* GPIO_FUNC10_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC10_OUT_SEL 0x000001FF +#define GPIO_FUNC10_OUT_SEL_M ((GPIO_FUNC10_OUT_SEL_V)<<(GPIO_FUNC10_OUT_SEL_S)) +#define GPIO_FUNC10_OUT_SEL_V 0x1FF +#define GPIO_FUNC10_OUT_SEL_S 0 + +#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x055c) + +/* GPIO_FUNC11_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC11_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC11_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC11_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC11_OEN_INV_SEL_S 11 + +/* GPIO_FUNC11_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC11_OEN_SEL (BIT(10)) +#define GPIO_FUNC11_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC11_OEN_SEL_V 0x1 +#define GPIO_FUNC11_OEN_SEL_S 10 + +/* GPIO_FUNC11_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC11_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC11_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC11_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC11_OUT_INV_SEL_S 9 + +/* GPIO_FUNC11_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC11_OUT_SEL 0x000001FF +#define GPIO_FUNC11_OUT_SEL_M ((GPIO_FUNC11_OUT_SEL_V)<<(GPIO_FUNC11_OUT_SEL_S)) +#define GPIO_FUNC11_OUT_SEL_V 0x1FF +#define GPIO_FUNC11_OUT_SEL_S 0 + +#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0560) + +/* GPIO_FUNC12_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC12_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC12_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC12_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC12_OEN_INV_SEL_S 11 + +/* GPIO_FUNC12_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC12_OEN_SEL (BIT(10)) +#define GPIO_FUNC12_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC12_OEN_SEL_V 0x1 +#define GPIO_FUNC12_OEN_SEL_S 10 + +/* GPIO_FUNC12_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC12_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC12_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC12_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC12_OUT_INV_SEL_S 9 + +/* GPIO_FUNC12_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC12_OUT_SEL 0x000001FF +#define GPIO_FUNC12_OUT_SEL_M ((GPIO_FUNC12_OUT_SEL_V)<<(GPIO_FUNC12_OUT_SEL_S)) +#define GPIO_FUNC12_OUT_SEL_V 0x1FF +#define GPIO_FUNC12_OUT_SEL_S 0 + +#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0564) + +/* GPIO_FUNC13_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC13_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC13_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC13_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC13_OEN_INV_SEL_S 11 + +/* GPIO_FUNC13_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC13_OEN_SEL (BIT(10)) +#define GPIO_FUNC13_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC13_OEN_SEL_V 0x1 +#define GPIO_FUNC13_OEN_SEL_S 10 + +/* GPIO_FUNC13_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC13_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC13_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC13_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC13_OUT_INV_SEL_S 9 + +/* GPIO_FUNC13_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC13_OUT_SEL 0x000001FF +#define GPIO_FUNC13_OUT_SEL_M ((GPIO_FUNC13_OUT_SEL_V)<<(GPIO_FUNC13_OUT_SEL_S)) +#define GPIO_FUNC13_OUT_SEL_V 0x1FF +#define GPIO_FUNC13_OUT_SEL_S 0 + +#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0568) + +/* GPIO_FUNC14_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC14_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC14_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC14_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC14_OEN_INV_SEL_S 11 + +/* GPIO_FUNC14_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC14_OEN_SEL (BIT(10)) +#define GPIO_FUNC14_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC14_OEN_SEL_V 0x1 +#define GPIO_FUNC14_OEN_SEL_S 10 + +/* GPIO_FUNC14_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC14_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC14_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC14_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC14_OUT_INV_SEL_S 9 + +/* GPIO_FUNC14_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC14_OUT_SEL 0x000001FF +#define GPIO_FUNC14_OUT_SEL_M ((GPIO_FUNC14_OUT_SEL_V)<<(GPIO_FUNC14_OUT_SEL_S)) +#define GPIO_FUNC14_OUT_SEL_V 0x1FF +#define GPIO_FUNC14_OUT_SEL_S 0 + +#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x056c) + +/* GPIO_FUNC15_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC15_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC15_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC15_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC15_OEN_INV_SEL_S 11 + +/* GPIO_FUNC15_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC15_OEN_SEL (BIT(10)) +#define GPIO_FUNC15_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC15_OEN_SEL_V 0x1 +#define GPIO_FUNC15_OEN_SEL_S 10 + +/* GPIO_FUNC15_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC15_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC15_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC15_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC15_OUT_INV_SEL_S 9 + +/* GPIO_FUNC15_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC15_OUT_SEL 0x000001FF +#define GPIO_FUNC15_OUT_SEL_M ((GPIO_FUNC15_OUT_SEL_V)<<(GPIO_FUNC15_OUT_SEL_S)) +#define GPIO_FUNC15_OUT_SEL_V 0x1FF +#define GPIO_FUNC15_OUT_SEL_S 0 + +#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0570) + +/* GPIO_FUNC16_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC16_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC16_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC16_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC16_OEN_INV_SEL_S 11 + +/* GPIO_FUNC16_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC16_OEN_SEL (BIT(10)) +#define GPIO_FUNC16_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC16_OEN_SEL_V 0x1 +#define GPIO_FUNC16_OEN_SEL_S 10 + +/* GPIO_FUNC16_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC16_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC16_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC16_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC16_OUT_INV_SEL_S 9 + +/* GPIO_FUNC16_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC16_OUT_SEL 0x000001FF +#define GPIO_FUNC16_OUT_SEL_M ((GPIO_FUNC16_OUT_SEL_V)<<(GPIO_FUNC16_OUT_SEL_S)) +#define GPIO_FUNC16_OUT_SEL_V 0x1FF +#define GPIO_FUNC16_OUT_SEL_S 0 + +#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0574) + +/* GPIO_FUNC17_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC17_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC17_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC17_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC17_OEN_INV_SEL_S 11 + +/* GPIO_FUNC17_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC17_OEN_SEL (BIT(10)) +#define GPIO_FUNC17_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC17_OEN_SEL_V 0x1 +#define GPIO_FUNC17_OEN_SEL_S 10 + +/* GPIO_FUNC17_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC17_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC17_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC17_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC17_OUT_INV_SEL_S 9 + +/* GPIO_FUNC17_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC17_OUT_SEL 0x000001FF +#define GPIO_FUNC17_OUT_SEL_M ((GPIO_FUNC17_OUT_SEL_V)<<(GPIO_FUNC17_OUT_SEL_S)) +#define GPIO_FUNC17_OUT_SEL_V 0x1FF +#define GPIO_FUNC17_OUT_SEL_S 0 + +#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0578) + +/* GPIO_FUNC18_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC18_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC18_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC18_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC18_OEN_INV_SEL_S 11 + +/* GPIO_FUNC18_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC18_OEN_SEL (BIT(10)) +#define GPIO_FUNC18_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC18_OEN_SEL_V 0x1 +#define GPIO_FUNC18_OEN_SEL_S 10 + +/* GPIO_FUNC18_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC18_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC18_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC18_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC18_OUT_INV_SEL_S 9 + +/* GPIO_FUNC18_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC18_OUT_SEL 0x000001FF +#define GPIO_FUNC18_OUT_SEL_M ((GPIO_FUNC18_OUT_SEL_V)<<(GPIO_FUNC18_OUT_SEL_S)) +#define GPIO_FUNC18_OUT_SEL_V 0x1FF +#define GPIO_FUNC18_OUT_SEL_S 0 + +#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x057c) + +/* GPIO_FUNC19_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC19_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC19_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC19_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC19_OEN_INV_SEL_S 11 + +/* GPIO_FUNC19_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC19_OEN_SEL (BIT(10)) +#define GPIO_FUNC19_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC19_OEN_SEL_V 0x1 +#define GPIO_FUNC19_OEN_SEL_S 10 + +/* GPIO_FUNC19_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC19_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC19_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC19_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC19_OUT_INV_SEL_S 9 + +/* GPIO_FUNC19_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC19_OUT_SEL 0x000001FF +#define GPIO_FUNC19_OUT_SEL_M ((GPIO_FUNC19_OUT_SEL_V)<<(GPIO_FUNC19_OUT_SEL_S)) +#define GPIO_FUNC19_OUT_SEL_V 0x1FF +#define GPIO_FUNC19_OUT_SEL_S 0 + +#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0580) + +/* GPIO_FUNC20_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC20_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC20_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC20_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC20_OEN_INV_SEL_S 11 + +/* GPIO_FUNC20_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC20_OEN_SEL (BIT(10)) +#define GPIO_FUNC20_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC20_OEN_SEL_V 0x1 +#define GPIO_FUNC20_OEN_SEL_S 10 + +/* GPIO_FUNC20_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC20_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC20_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC20_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC20_OUT_INV_SEL_S 9 + +/* GPIO_FUNC20_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC20_OUT_SEL 0x000001FF +#define GPIO_FUNC20_OUT_SEL_M ((GPIO_FUNC20_OUT_SEL_V)<<(GPIO_FUNC20_OUT_SEL_S)) +#define GPIO_FUNC20_OUT_SEL_V 0x1FF +#define GPIO_FUNC20_OUT_SEL_S 0 + +#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0584) + +/* GPIO_FUNC21_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC21_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC21_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC21_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC21_OEN_INV_SEL_S 11 + +/* GPIO_FUNC21_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC21_OEN_SEL (BIT(10)) +#define GPIO_FUNC21_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC21_OEN_SEL_V 0x1 +#define GPIO_FUNC21_OEN_SEL_S 10 + +/* GPIO_FUNC21_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC21_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC21_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC21_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC21_OUT_INV_SEL_S 9 + +/* GPIO_FUNC21_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC21_OUT_SEL 0x000001FF +#define GPIO_FUNC21_OUT_SEL_M ((GPIO_FUNC21_OUT_SEL_V)<<(GPIO_FUNC21_OUT_SEL_S)) +#define GPIO_FUNC21_OUT_SEL_V 0x1FF +#define GPIO_FUNC21_OUT_SEL_S 0 + +#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0588) + +/* GPIO_FUNC22_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC22_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC22_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC22_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC22_OEN_INV_SEL_S 11 + +/* GPIO_FUNC22_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC22_OEN_SEL (BIT(10)) +#define GPIO_FUNC22_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC22_OEN_SEL_V 0x1 +#define GPIO_FUNC22_OEN_SEL_S 10 + +/* GPIO_FUNC22_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC22_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC22_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC22_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC22_OUT_INV_SEL_S 9 + +/* GPIO_FUNC22_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC22_OUT_SEL 0x000001FF +#define GPIO_FUNC22_OUT_SEL_M ((GPIO_FUNC22_OUT_SEL_V)<<(GPIO_FUNC22_OUT_SEL_S)) +#define GPIO_FUNC22_OUT_SEL_V 0x1FF +#define GPIO_FUNC22_OUT_SEL_S 0 + +#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x058c) + +/* GPIO_FUNC23_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC23_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC23_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC23_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC23_OEN_INV_SEL_S 11 + +/* GPIO_FUNC23_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC23_OEN_SEL (BIT(10)) +#define GPIO_FUNC23_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC23_OEN_SEL_V 0x1 +#define GPIO_FUNC23_OEN_SEL_S 10 + +/* GPIO_FUNC23_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC23_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC23_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC23_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC23_OUT_INV_SEL_S 9 + +/* GPIO_FUNC23_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC23_OUT_SEL 0x000001FF +#define GPIO_FUNC23_OUT_SEL_M ((GPIO_FUNC23_OUT_SEL_V)<<(GPIO_FUNC23_OUT_SEL_S)) +#define GPIO_FUNC23_OUT_SEL_V 0x1FF +#define GPIO_FUNC23_OUT_SEL_S 0 + +#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0590) + +/* GPIO_FUNC24_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC24_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC24_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC24_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC24_OEN_INV_SEL_S 11 + +/* GPIO_FUNC24_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC24_OEN_SEL (BIT(10)) +#define GPIO_FUNC24_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC24_OEN_SEL_V 0x1 +#define GPIO_FUNC24_OEN_SEL_S 10 + +/* GPIO_FUNC24_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC24_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC24_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC24_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC24_OUT_INV_SEL_S 9 + +/* GPIO_FUNC24_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC24_OUT_SEL 0x000001FF +#define GPIO_FUNC24_OUT_SEL_M ((GPIO_FUNC24_OUT_SEL_V)<<(GPIO_FUNC24_OUT_SEL_S)) +#define GPIO_FUNC24_OUT_SEL_V 0x1FF +#define GPIO_FUNC24_OUT_SEL_S 0 + +#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0594) + +/* GPIO_FUNC25_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC25_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC25_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC25_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC25_OEN_INV_SEL_S 11 + +/* GPIO_FUNC25_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC25_OEN_SEL (BIT(10)) +#define GPIO_FUNC25_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC25_OEN_SEL_V 0x1 +#define GPIO_FUNC25_OEN_SEL_S 10 + +/* GPIO_FUNC25_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC25_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC25_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC25_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC25_OUT_INV_SEL_S 9 + +/* GPIO_FUNC25_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC25_OUT_SEL 0x000001FF +#define GPIO_FUNC25_OUT_SEL_M ((GPIO_FUNC25_OUT_SEL_V)<<(GPIO_FUNC25_OUT_SEL_S)) +#define GPIO_FUNC25_OUT_SEL_V 0x1FF +#define GPIO_FUNC25_OUT_SEL_S 0 + +#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0598) + +/* GPIO_FUNC26_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC26_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC26_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC26_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC26_OEN_INV_SEL_S 11 + +/* GPIO_FUNC26_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC26_OEN_SEL (BIT(10)) +#define GPIO_FUNC26_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC26_OEN_SEL_V 0x1 +#define GPIO_FUNC26_OEN_SEL_S 10 + +/* GPIO_FUNC26_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC26_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC26_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC26_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC26_OUT_INV_SEL_S 9 + +/* GPIO_FUNC26_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC26_OUT_SEL 0x000001FF +#define GPIO_FUNC26_OUT_SEL_M ((GPIO_FUNC26_OUT_SEL_V)<<(GPIO_FUNC26_OUT_SEL_S)) +#define GPIO_FUNC26_OUT_SEL_V 0x1FF +#define GPIO_FUNC26_OUT_SEL_S 0 + +#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x059c) + +/* GPIO_FUNC27_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC27_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC27_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC27_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC27_OEN_INV_SEL_S 11 + +/* GPIO_FUNC27_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC27_OEN_SEL (BIT(10)) +#define GPIO_FUNC27_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC27_OEN_SEL_V 0x1 +#define GPIO_FUNC27_OEN_SEL_S 10 + +/* GPIO_FUNC27_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC27_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC27_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC27_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC27_OUT_INV_SEL_S 9 + +/* GPIO_FUNC27_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC27_OUT_SEL 0x000001FF +#define GPIO_FUNC27_OUT_SEL_M ((GPIO_FUNC27_OUT_SEL_V)<<(GPIO_FUNC27_OUT_SEL_S)) +#define GPIO_FUNC27_OUT_SEL_V 0x1FF +#define GPIO_FUNC27_OUT_SEL_S 0 + +#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05a0) + +/* GPIO_FUNC28_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC28_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC28_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC28_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC28_OEN_INV_SEL_S 11 + +/* GPIO_FUNC28_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC28_OEN_SEL (BIT(10)) +#define GPIO_FUNC28_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC28_OEN_SEL_V 0x1 +#define GPIO_FUNC28_OEN_SEL_S 10 + +/* GPIO_FUNC28_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC28_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC28_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC28_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC28_OUT_INV_SEL_S 9 + +/* GPIO_FUNC28_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC28_OUT_SEL 0x000001FF +#define GPIO_FUNC28_OUT_SEL_M ((GPIO_FUNC28_OUT_SEL_V)<<(GPIO_FUNC28_OUT_SEL_S)) +#define GPIO_FUNC28_OUT_SEL_V 0x1FF +#define GPIO_FUNC28_OUT_SEL_S 0 + +#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05a4) + +/* GPIO_FUNC29_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC29_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC29_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC29_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC29_OEN_INV_SEL_S 11 + +/* GPIO_FUNC29_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC29_OEN_SEL (BIT(10)) +#define GPIO_FUNC29_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC29_OEN_SEL_V 0x1 +#define GPIO_FUNC29_OEN_SEL_S 10 + +/* GPIO_FUNC29_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC29_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC29_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC29_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC29_OUT_INV_SEL_S 9 + +/* GPIO_FUNC29_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC29_OUT_SEL 0x000001FF +#define GPIO_FUNC29_OUT_SEL_M ((GPIO_FUNC29_OUT_SEL_V)<<(GPIO_FUNC29_OUT_SEL_S)) +#define GPIO_FUNC29_OUT_SEL_V 0x1FF +#define GPIO_FUNC29_OUT_SEL_S 0 + +#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05a8) + +/* GPIO_FUNC30_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC30_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC30_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC30_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC30_OEN_INV_SEL_S 11 + +/* GPIO_FUNC30_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC30_OEN_SEL (BIT(10)) +#define GPIO_FUNC30_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC30_OEN_SEL_V 0x1 +#define GPIO_FUNC30_OEN_SEL_S 10 + +/* GPIO_FUNC30_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC30_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC30_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC30_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC30_OUT_INV_SEL_S 9 + +/* GPIO_FUNC30_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC30_OUT_SEL 0x000001FF +#define GPIO_FUNC30_OUT_SEL_M ((GPIO_FUNC30_OUT_SEL_V)<<(GPIO_FUNC30_OUT_SEL_S)) +#define GPIO_FUNC30_OUT_SEL_V 0x1FF +#define GPIO_FUNC30_OUT_SEL_S 0 + +#define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05ac) + +/* GPIO_FUNC31_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC31_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC31_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC31_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC31_OEN_INV_SEL_S 11 + +/* GPIO_FUNC31_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC31_OEN_SEL (BIT(10)) +#define GPIO_FUNC31_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC31_OEN_SEL_V 0x1 +#define GPIO_FUNC31_OEN_SEL_S 10 + +/* GPIO_FUNC31_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC31_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC31_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC31_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC31_OUT_INV_SEL_S 9 + +/* GPIO_FUNC31_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC31_OUT_SEL 0x000001FF +#define GPIO_FUNC31_OUT_SEL_M ((GPIO_FUNC31_OUT_SEL_V)<<(GPIO_FUNC31_OUT_SEL_S)) +#define GPIO_FUNC31_OUT_SEL_V 0x1FF +#define GPIO_FUNC31_OUT_SEL_S 0 + +#define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05b0) + +/* GPIO_FUNC32_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC32_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC32_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC32_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC32_OEN_INV_SEL_S 11 + +/* GPIO_FUNC32_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC32_OEN_SEL (BIT(10)) +#define GPIO_FUNC32_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC32_OEN_SEL_V 0x1 +#define GPIO_FUNC32_OEN_SEL_S 10 + +/* GPIO_FUNC32_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC32_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC32_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC32_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC32_OUT_INV_SEL_S 9 + +/* GPIO_FUNC32_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC32_OUT_SEL 0x000001FF +#define GPIO_FUNC32_OUT_SEL_M ((GPIO_FUNC32_OUT_SEL_V)<<(GPIO_FUNC32_OUT_SEL_S)) +#define GPIO_FUNC32_OUT_SEL_V 0x1FF +#define GPIO_FUNC32_OUT_SEL_S 0 + +#define GPIO_FUNC33_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05b4) + +/* GPIO_FUNC33_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC33_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC33_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC33_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC33_OEN_INV_SEL_S 11 + +/* GPIO_FUNC33_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC33_OEN_SEL (BIT(10)) +#define GPIO_FUNC33_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC33_OEN_SEL_V 0x1 +#define GPIO_FUNC33_OEN_SEL_S 10 + +/* GPIO_FUNC33_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC33_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC33_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC33_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC33_OUT_INV_SEL_S 9 + +/* GPIO_FUNC33_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC33_OUT_SEL 0x000001FF +#define GPIO_FUNC33_OUT_SEL_M ((GPIO_FUNC33_OUT_SEL_V)<<(GPIO_FUNC33_OUT_SEL_S)) +#define GPIO_FUNC33_OUT_SEL_V 0x1FF +#define GPIO_FUNC33_OUT_SEL_S 0 + +#define GPIO_FUNC34_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05b8) + +/* GPIO_FUNC34_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC34_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC34_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC34_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC34_OEN_INV_SEL_S 11 + +/* GPIO_FUNC34_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC34_OEN_SEL (BIT(10)) +#define GPIO_FUNC34_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC34_OEN_SEL_V 0x1 +#define GPIO_FUNC34_OEN_SEL_S 10 + +/* GPIO_FUNC34_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC34_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC34_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC34_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC34_OUT_INV_SEL_S 9 + +/* GPIO_FUNC34_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC34_OUT_SEL 0x000001FF +#define GPIO_FUNC34_OUT_SEL_M ((GPIO_FUNC34_OUT_SEL_V)<<(GPIO_FUNC34_OUT_SEL_S)) +#define GPIO_FUNC34_OUT_SEL_V 0x1FF +#define GPIO_FUNC34_OUT_SEL_S 0 + +#define GPIO_FUNC35_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05bc) + +/* GPIO_FUNC35_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC35_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC35_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC35_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC35_OEN_INV_SEL_S 11 + +/* GPIO_FUNC35_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC35_OEN_SEL (BIT(10)) +#define GPIO_FUNC35_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC35_OEN_SEL_V 0x1 +#define GPIO_FUNC35_OEN_SEL_S 10 + +/* GPIO_FUNC35_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC35_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC35_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC35_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC35_OUT_INV_SEL_S 9 + +/* GPIO_FUNC35_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC35_OUT_SEL 0x000001FF +#define GPIO_FUNC35_OUT_SEL_M ((GPIO_FUNC35_OUT_SEL_V)<<(GPIO_FUNC35_OUT_SEL_S)) +#define GPIO_FUNC35_OUT_SEL_V 0x1FF +#define GPIO_FUNC35_OUT_SEL_S 0 + +#define GPIO_FUNC36_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05c0) + +/* GPIO_FUNC36_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC36_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC36_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC36_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC36_OEN_INV_SEL_S 11 + +/* GPIO_FUNC36_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC36_OEN_SEL (BIT(10)) +#define GPIO_FUNC36_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC36_OEN_SEL_V 0x1 +#define GPIO_FUNC36_OEN_SEL_S 10 + +/* GPIO_FUNC36_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC36_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC36_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC36_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC36_OUT_INV_SEL_S 9 + +/* GPIO_FUNC36_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC36_OUT_SEL 0x000001FF +#define GPIO_FUNC36_OUT_SEL_M ((GPIO_FUNC36_OUT_SEL_V)<<(GPIO_FUNC36_OUT_SEL_S)) +#define GPIO_FUNC36_OUT_SEL_V 0x1FF +#define GPIO_FUNC36_OUT_SEL_S 0 + +#define GPIO_FUNC37_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05c4) + +/* GPIO_FUNC37_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC37_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC37_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC37_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC37_OEN_INV_SEL_S 11 + +/* GPIO_FUNC37_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC37_OEN_SEL (BIT(10)) +#define GPIO_FUNC37_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC37_OEN_SEL_V 0x1 +#define GPIO_FUNC37_OEN_SEL_S 10 + +/* GPIO_FUNC37_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC37_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC37_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC37_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC37_OUT_INV_SEL_S 9 + +/* GPIO_FUNC37_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC37_OUT_SEL 0x000001FF +#define GPIO_FUNC37_OUT_SEL_M ((GPIO_FUNC37_OUT_SEL_V)<<(GPIO_FUNC37_OUT_SEL_S)) +#define GPIO_FUNC37_OUT_SEL_V 0x1FF +#define GPIO_FUNC37_OUT_SEL_S 0 + +#define GPIO_FUNC38_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05c8) + +/* GPIO_FUNC38_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC38_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC38_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC38_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC38_OEN_INV_SEL_S 11 + +/* GPIO_FUNC38_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC38_OEN_SEL (BIT(10)) +#define GPIO_FUNC38_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC38_OEN_SEL_V 0x1 +#define GPIO_FUNC38_OEN_SEL_S 10 + +/* GPIO_FUNC38_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC38_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC38_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC38_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC38_OUT_INV_SEL_S 9 + +/* GPIO_FUNC38_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC38_OUT_SEL 0x000001FF +#define GPIO_FUNC38_OUT_SEL_M ((GPIO_FUNC38_OUT_SEL_V)<<(GPIO_FUNC38_OUT_SEL_S)) +#define GPIO_FUNC38_OUT_SEL_V 0x1FF +#define GPIO_FUNC38_OUT_SEL_S 0 + +#define GPIO_FUNC39_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05cc) + +/* GPIO_FUNC39_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ +/* Description: invert the output enable value if you want to revert the output + enable value setting the value to 1 */ + +#define GPIO_FUNC39_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC39_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC39_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC39_OEN_INV_SEL_S 11 + +/* GPIO_FUNC39_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ +/* Description: weather using the logical oen signal or not using the value setting + by the register */ + +#define GPIO_FUNC39_OEN_SEL (BIT(10)) +#define GPIO_FUNC39_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC39_OEN_SEL_V 0x1 +#define GPIO_FUNC39_OEN_SEL_S 10 + +/* GPIO_FUNC39_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ +/* Description: invert the output value if you want to revert the output value + setting the value to 1 */ + +#define GPIO_FUNC39_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC39_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC39_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC39_OUT_INV_SEL_S 9 + +/* GPIO_FUNC39_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ +/* Description: select one of the 256 output to 40 GPIO */ + +#define GPIO_FUNC39_OUT_SEL 0x000001FF +#define GPIO_FUNC39_OUT_SEL_M ((GPIO_FUNC39_OUT_SEL_V)<<(GPIO_FUNC39_OUT_SEL_S)) +#define GPIO_FUNC39_OUT_SEL_V 0x1FF +#define GPIO_FUNC39_OUT_SEL_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_GPIO_H */ -- GitLab From 6acc831e775a7b419d92fdaf1ac9ea96741e5d8b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 26 Oct 2016 07:00:24 -0600 Subject: [PATCH 215/734] Remove duplicate select from Kconfig --- arch/arm/src/stm32l4/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index cec02a9cbb..a365dd4783 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -1277,7 +1277,6 @@ config STM32L4_TIM5_PWM default n depends on STM32L4_TIM5 select PWM - select PWM select ARCH_HAVE_PWM_PULSECOUNT ---help--- Reserve timer 5 for use by PWM -- GitLab From 3e13ed240070a11a8fade137f481e766619572dc Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 26 Oct 2016 07:23:15 -0600 Subject: [PATCH 216/734] Within the OS, when a thread obtains a semaphore count it must call sem_addholder() if CONFIG_PRIORITY_INHERITANCE is enabled. If a count is available, then sem_wait() calls sem_addholder(), otherwise it waited for the semaphore and called sem_addholder() when it eventually received the count. This caused a problem when the thread calling sem_wait() was very low priority. When it received the count, there may be higher priority threads "hogging" the CPU that prevent the lower priority task from running and, as a result, the sem_addholder() may be delayed indefinitely. The fix was to have sem_post() call sem_addholder() just before restarting the thread waiting for the semaphore count. This problem was noted by Benix Vincent who also suggested the solution. --- sched/semaphore/sem_holder.c | 42 ++++++++++++++++++++++++++++-------- sched/semaphore/sem_post.c | 8 ++++++- sched/semaphore/sem_wait.c | 7 ++++-- sched/semaphore/semaphore.h | 6 ++++-- 4 files changed, 49 insertions(+), 14 deletions(-) diff --git a/sched/semaphore/sem_holder.c b/sched/semaphore/sem_holder.c index f56eb1bc8d..769444fd99 100644 --- a/sched/semaphore/sem_holder.c +++ b/sched/semaphore/sem_holder.c @@ -1,7 +1,7 @@ /**************************************************************************** * sched/semaphore/sem_holder.c * - * Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2011, 2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -833,40 +833,64 @@ void sem_destroyholder(FAR sem_t *sem) } /**************************************************************************** - * Name: sem_addholder + * Name: sem_addholder_tcb * * Description: - * Called from sem_wait() when the calling thread obtains the semaphore + * Called from sem_wait() when the calling thread obtains the semaphore; + * Called from sem_post() when the waiting thread obtains the semaphore. * * Parameters: - * sem - A reference to the incremented semaphore + * htcb - TCB of the thread that just obtained the semaphore + * sem - A reference to the incremented semaphore * * Return Value: * 0 (OK) or -1 (ERROR) if unsuccessful * * Assumptions: + * Interrupts are disabled. * ****************************************************************************/ -void sem_addholder(FAR sem_t *sem) +void sem_addholder_tcb(FAR struct tcb_s *htcb, FAR sem_t *sem) { - FAR struct tcb_s *rtcb = this_task(); FAR struct semholder_s *pholder; /* Find or allocate a container for this new holder */ - pholder = sem_findorallocateholder(sem, rtcb); - if (pholder) + pholder = sem_findorallocateholder(sem, htcb); + if (pholder != NULL) { /* Then set the holder and increment the number of counts held by this * holder */ - pholder->htcb = rtcb; + pholder->htcb = htcb; pholder->counts++; } } +/**************************************************************************** + * Name: sem_addholder + * + * Description: + * Called from sem_wait() when the calling thread obtains the semaphore + * + * Parameters: + * sem - A reference to the incremented semaphore + * + * Return Value: + * 0 (OK) or -1 (ERROR) if unsuccessful + * + * Assumptions: + * Interrupts are disabled. + * + ****************************************************************************/ + +void sem_addholder(FAR sem_t *sem) +{ + sem_addholder_tcb(this_task(), sem); +} + /**************************************************************************** * Name: void sem_boostpriority(sem_t *sem) * diff --git a/sched/semaphore/sem_post.c b/sched/semaphore/sem_post.c index c985ceb9c4..1c90449953 100644 --- a/sched/semaphore/sem_post.c +++ b/sched/semaphore/sem_post.c @@ -131,8 +131,14 @@ int sem_post(FAR sem_t *sem) (stcb && stcb->waitsem != sem); stcb = stcb->flink); - if (stcb) + if (stcb != NULL) { + /* The task will be the new holder of the semaphore when + * it is awakened. + */ + + sem_addholder_tcb(stcb, sem); + /* It is, let the task take the semaphore */ stcb->waitsem = NULL; diff --git a/sched/semaphore/sem_wait.c b/sched/semaphore/sem_wait.c index 49371e0ae6..9c19d406d7 100644 --- a/sched/semaphore/sem_wait.c +++ b/sched/semaphore/sem_wait.c @@ -173,9 +173,12 @@ int sem_wait(FAR sem_t *sem) if (get_errno() != EINTR && get_errno() != ETIMEDOUT) { - /* Not awakened by a signal or a timeout... We hold the semaphore */ + /* Not awakened by a signal or a timeout... + * + * NOTE that in this case sem_addholder() was called by logic + * in sem_wait() fore this thread was restarted. + */ - sem_addholder(sem); ret = OK; } diff --git a/sched/semaphore/semaphore.h b/sched/semaphore/semaphore.h index 85f4e6c876..cc7a929816 100644 --- a/sched/semaphore/semaphore.h +++ b/sched/semaphore/semaphore.h @@ -1,7 +1,7 @@ /**************************************************************************** * sched/semaphore/semaphore.h * - * Copyright (C) 2007, 2009-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2007, 2009-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -89,6 +89,7 @@ void sem_recover(FAR struct tcb_s *tcb); void sem_initholders(void); void sem_destroyholder(FAR sem_t *sem); void sem_addholder(FAR sem_t *sem); +void sem_addholder_tcb(FAR struct tcb_s *htcb, FAR sem_t *sem); void sem_boostpriority(FAR sem_t *sem); void sem_releaseholder(FAR sem_t *sem); void sem_restorebaseprio(FAR struct tcb_s *stcb, FAR sem_t *sem); @@ -101,10 +102,11 @@ void sem_canceled(FAR struct tcb_s *stcb, FAR sem_t *sem); # define sem_initholders() # define sem_destroyholder(sem) # define sem_addholder(sem) +# define sem_addholder_tcb(htcb,sem) # define sem_boostpriority(sem) # define sem_releaseholder(sem) # define sem_restorebaseprio(stcb,sem) -# define sem_canceled(stcb, sem) +# define sem_canceled(stcb,sem) #endif #undef EXTERN -- GitLab From 946045075eaad9c44549125e614ce34ab0967a97 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 26 Oct 2016 08:23:09 -0600 Subject: [PATCH 217/734] ESP32: Remove some long lines in header file --- arch/xtensa/src/esp32/chip/esp32_gpio.h | 5175 ++++++++++++++--------- 1 file changed, 3113 insertions(+), 2062 deletions(-) diff --git a/arch/xtensa/src/esp32/chip/esp32_gpio.h b/arch/xtensa/src/esp32/chip/esp32_gpio.h index 454e378c49..ebdfc44292 100644 --- a/arch/xtensa/src/esp32/chip/esp32_gpio.h +++ b/arch/xtensa/src/esp32/chip/esp32_gpio.h @@ -22,20 +22,20 @@ * See the License for the specific language governing permissions and * limitations under the License. * - *************************************************************************** */ + ****************************************************************************/ #ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_GPIO_H #define __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_GPIO_H /**************************************************************************** * Included Files - *************************************************************************** */ + ****************************************************************************/ #include "chip/esp32_soc.h" /**************************************************************************** * Pre-preprocessor Definitions - *************************************************************************** */ + ****************************************************************************/ #include "soc.h" #define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0000) @@ -43,7 +43,7 @@ /* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: x ; */ /* Description: NA */ -#define GPIO_BT_SEL 0xFFFFFFFF +#define GPIO_BT_SEL 0xFFFFFFFF #define GPIO_BT_SEL_M ((GPIO_BT_SEL_V)<<(GPIO_BT_SEL_S)) #define GPIO_BT_SEL_V 0xFFFFFFFF #define GPIO_BT_SEL_S 0 @@ -113,7 +113,7 @@ /* GPIO_SDIO_SEL : R/W ;bitpos:[7:0] ;default: x ; */ /* Description: SDIO PADS on/off control from outside */ -#define GPIO_SDIO_SEL 0x000000FF +#define GPIO_SDIO_SEL 0x000000FF #define GPIO_SDIO_SEL_M ((GPIO_SDIO_SEL_V)<<(GPIO_SDIO_SEL_S)) #define GPIO_SDIO_SEL_V 0xFF #define GPIO_SDIO_SEL_S 0 @@ -181,8 +181,11 @@ #define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0038) /* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default: ; */ -/* Description: GPIO strapping results: {2'd0 boot_sel_dig[7:1] vsdio_boot_sel - boot_sel_chip[5:0]}. Boot_sel_dig[7:1]: {U0RXD SD_CLK SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3}. vsdio_boot_sel: MTDI. boot_sel_chip[5:0]: {GPIO0 U0TXD GPIO2 GPIO4 MTDO GPIO5} */ +/* Description: GPIO strapping results: {2'd0 boot_sel_dig[7:1] + * vsdio_boot_sel boot_sel_chip[5:0]}. Boot_sel_dig[7:1]: {U0RXD SD_CLK + * SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3}. vsdio_boot_sel: MTDI. + * boot_sel_chip[5:0]: {GPIO0 U0TXD GPIO2 GPIO4 MTDO GPIO5} + */ #define GPIO_STRAPPING 0x0000FFFF #define GPIO_STRAPPING_M ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S)) @@ -394,8 +397,10 @@ #define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x0088) /* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN0_INT_ENA 0x0000001F #define GPIO_PIN0_INT_ENA_M ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S)) @@ -420,7 +425,9 @@ /* GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN0_INT_TYPE 0x00000007 #define GPIO_PIN0_INT_TYPE_M ((GPIO_PIN0_INT_TYPE_V)<<(GPIO_PIN0_INT_TYPE_S)) @@ -438,8 +445,10 @@ #define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x008c) /* GPIO_PIN1_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN1_INT_ENA 0x0000001F #define GPIO_PIN1_INT_ENA_M ((GPIO_PIN1_INT_ENA_V)<<(GPIO_PIN1_INT_ENA_S)) @@ -464,7 +473,9 @@ /* GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN1_INT_TYPE 0x00000007 #define GPIO_PIN1_INT_TYPE_M ((GPIO_PIN1_INT_TYPE_V)<<(GPIO_PIN1_INT_TYPE_S)) @@ -482,8 +493,10 @@ #define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x0090) /* GPIO_PIN2_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN2_INT_ENA 0x0000001F #define GPIO_PIN2_INT_ENA_M ((GPIO_PIN2_INT_ENA_V)<<(GPIO_PIN2_INT_ENA_S)) @@ -508,7 +521,9 @@ /* GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN2_INT_TYPE 0x00000007 #define GPIO_PIN2_INT_TYPE_M ((GPIO_PIN2_INT_TYPE_V)<<(GPIO_PIN2_INT_TYPE_S)) @@ -526,8 +541,10 @@ #define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x0094) /* GPIO_PIN3_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN3_INT_ENA 0x0000001F #define GPIO_PIN3_INT_ENA_M ((GPIO_PIN3_INT_ENA_V)<<(GPIO_PIN3_INT_ENA_S)) @@ -552,7 +569,9 @@ /* GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN3_INT_TYPE 0x00000007 #define GPIO_PIN3_INT_TYPE_M ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S)) @@ -570,8 +589,10 @@ #define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x0098) /* GPIO_PIN4_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN4_INT_ENA 0x0000001F #define GPIO_PIN4_INT_ENA_M ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S)) @@ -596,7 +617,9 @@ /* GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN4_INT_TYPE 0x00000007 #define GPIO_PIN4_INT_TYPE_M ((GPIO_PIN4_INT_TYPE_V)<<(GPIO_PIN4_INT_TYPE_S)) @@ -614,8 +637,10 @@ #define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x009c) /* GPIO_PIN5_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN5_INT_ENA 0x0000001F #define GPIO_PIN5_INT_ENA_M ((GPIO_PIN5_INT_ENA_V)<<(GPIO_PIN5_INT_ENA_S)) @@ -640,7 +665,9 @@ /* GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN5_INT_TYPE 0x00000007 #define GPIO_PIN5_INT_TYPE_M ((GPIO_PIN5_INT_TYPE_V)<<(GPIO_PIN5_INT_TYPE_S)) @@ -658,8 +685,10 @@ #define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x00a0) /* GPIO_PIN6_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN6_INT_ENA 0x0000001F #define GPIO_PIN6_INT_ENA_M ((GPIO_PIN6_INT_ENA_V)<<(GPIO_PIN6_INT_ENA_S)) @@ -684,7 +713,9 @@ /* GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN6_INT_TYPE 0x00000007 #define GPIO_PIN6_INT_TYPE_M ((GPIO_PIN6_INT_TYPE_V)<<(GPIO_PIN6_INT_TYPE_S)) @@ -702,8 +733,10 @@ #define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x00a4) /* GPIO_PIN7_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN7_INT_ENA 0x0000001F #define GPIO_PIN7_INT_ENA_M ((GPIO_PIN7_INT_ENA_V)<<(GPIO_PIN7_INT_ENA_S)) @@ -728,7 +761,9 @@ /* GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN7_INT_TYPE 0x00000007 #define GPIO_PIN7_INT_TYPE_M ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S)) @@ -746,8 +781,10 @@ #define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x00a8) /* GPIO_PIN8_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN8_INT_ENA 0x0000001F #define GPIO_PIN8_INT_ENA_M ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S)) @@ -772,7 +809,9 @@ /* GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN8_INT_TYPE 0x00000007 #define GPIO_PIN8_INT_TYPE_M ((GPIO_PIN8_INT_TYPE_V)<<(GPIO_PIN8_INT_TYPE_S)) @@ -790,8 +829,10 @@ #define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x00ac) /* GPIO_PIN9_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN9_INT_ENA 0x0000001F #define GPIO_PIN9_INT_ENA_M ((GPIO_PIN9_INT_ENA_V)<<(GPIO_PIN9_INT_ENA_S)) @@ -816,7 +857,9 @@ /* GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN9_INT_TYPE 0x00000007 #define GPIO_PIN9_INT_TYPE_M ((GPIO_PIN9_INT_TYPE_V)<<(GPIO_PIN9_INT_TYPE_S)) @@ -834,8 +877,10 @@ #define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x00b0) /* GPIO_PIN10_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN10_INT_ENA 0x0000001F #define GPIO_PIN10_INT_ENA_M ((GPIO_PIN10_INT_ENA_V)<<(GPIO_PIN10_INT_ENA_S)) @@ -860,7 +905,9 @@ /* GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN10_INT_TYPE 0x00000007 #define GPIO_PIN10_INT_TYPE_M ((GPIO_PIN10_INT_TYPE_V)<<(GPIO_PIN10_INT_TYPE_S)) @@ -878,8 +925,10 @@ #define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0x00b4) /* GPIO_PIN11_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN11_INT_ENA 0x0000001F #define GPIO_PIN11_INT_ENA_M ((GPIO_PIN11_INT_ENA_V)<<(GPIO_PIN11_INT_ENA_S)) @@ -904,7 +953,9 @@ /* GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN11_INT_TYPE 0x00000007 #define GPIO_PIN11_INT_TYPE_M ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S)) @@ -922,8 +973,10 @@ #define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0x00b8) /* GPIO_PIN12_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN12_INT_ENA 0x0000001F #define GPIO_PIN12_INT_ENA_M ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S)) @@ -948,7 +1001,9 @@ /* GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN12_INT_TYPE 0x00000007 #define GPIO_PIN12_INT_TYPE_M ((GPIO_PIN12_INT_TYPE_V)<<(GPIO_PIN12_INT_TYPE_S)) @@ -966,8 +1021,10 @@ #define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0x00bc) /* GPIO_PIN13_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN13_INT_ENA 0x0000001F #define GPIO_PIN13_INT_ENA_M ((GPIO_PIN13_INT_ENA_V)<<(GPIO_PIN13_INT_ENA_S)) @@ -992,7 +1049,9 @@ /* GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN13_INT_TYPE 0x00000007 #define GPIO_PIN13_INT_TYPE_M ((GPIO_PIN13_INT_TYPE_V)<<(GPIO_PIN13_INT_TYPE_S)) @@ -1010,8 +1069,10 @@ #define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0x00c0) /* GPIO_PIN14_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN14_INT_ENA 0x0000001F #define GPIO_PIN14_INT_ENA_M ((GPIO_PIN14_INT_ENA_V)<<(GPIO_PIN14_INT_ENA_S)) @@ -1036,7 +1097,9 @@ /* GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN14_INT_TYPE 0x00000007 #define GPIO_PIN14_INT_TYPE_M ((GPIO_PIN14_INT_TYPE_V)<<(GPIO_PIN14_INT_TYPE_S)) @@ -1054,8 +1117,10 @@ #define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0x00c4) /* GPIO_PIN15_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN15_INT_ENA 0x0000001F #define GPIO_PIN15_INT_ENA_M ((GPIO_PIN15_INT_ENA_V)<<(GPIO_PIN15_INT_ENA_S)) @@ -1080,7 +1145,9 @@ /* GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN15_INT_TYPE 0x00000007 #define GPIO_PIN15_INT_TYPE_M ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S)) @@ -1098,8 +1165,10 @@ #define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0x00c8) /* GPIO_PIN16_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN16_INT_ENA 0x0000001F #define GPIO_PIN16_INT_ENA_M ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S)) @@ -1124,7 +1193,9 @@ /* GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN16_INT_TYPE 0x00000007 #define GPIO_PIN16_INT_TYPE_M ((GPIO_PIN16_INT_TYPE_V)<<(GPIO_PIN16_INT_TYPE_S)) @@ -1142,8 +1213,10 @@ #define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0x00cc) /* GPIO_PIN17_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN17_INT_ENA 0x0000001F #define GPIO_PIN17_INT_ENA_M ((GPIO_PIN17_INT_ENA_V)<<(GPIO_PIN17_INT_ENA_S)) @@ -1168,7 +1241,9 @@ /* GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN17_INT_TYPE 0x00000007 #define GPIO_PIN17_INT_TYPE_M ((GPIO_PIN17_INT_TYPE_V)<<(GPIO_PIN17_INT_TYPE_S)) @@ -1186,8 +1261,10 @@ #define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0x00d0) /* GPIO_PIN18_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN18_INT_ENA 0x0000001F #define GPIO_PIN18_INT_ENA_M ((GPIO_PIN18_INT_ENA_V)<<(GPIO_PIN18_INT_ENA_S)) @@ -1212,7 +1289,9 @@ /* GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN18_INT_TYPE 0x00000007 #define GPIO_PIN18_INT_TYPE_M ((GPIO_PIN18_INT_TYPE_V)<<(GPIO_PIN18_INT_TYPE_S)) @@ -1230,8 +1309,10 @@ #define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0x00d4) /* GPIO_PIN19_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN19_INT_ENA 0x0000001F #define GPIO_PIN19_INT_ENA_M ((GPIO_PIN19_INT_ENA_V)<<(GPIO_PIN19_INT_ENA_S)) @@ -1256,7 +1337,9 @@ /* GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN19_INT_TYPE 0x00000007 #define GPIO_PIN19_INT_TYPE_M ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S)) @@ -1274,8 +1357,10 @@ #define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0x00d8) /* GPIO_PIN20_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-mask interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-mask interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN20_INT_ENA 0x0000001F #define GPIO_PIN20_INT_ENA_M ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S)) @@ -1300,7 +1385,9 @@ /* GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN20_INT_TYPE 0x00000007 #define GPIO_PIN20_INT_TYPE_M ((GPIO_PIN20_INT_TYPE_V)<<(GPIO_PIN20_INT_TYPE_S)) @@ -1318,8 +1405,10 @@ #define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0x00dc) /* GPIO_PIN21_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN21_INT_ENA 0x0000001F #define GPIO_PIN21_INT_ENA_M ((GPIO_PIN21_INT_ENA_V)<<(GPIO_PIN21_INT_ENA_S)) @@ -1344,7 +1433,9 @@ /* GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN21_INT_TYPE 0x00000007 #define GPIO_PIN21_INT_TYPE_M ((GPIO_PIN21_INT_TYPE_V)<<(GPIO_PIN21_INT_TYPE_S)) @@ -1370,8 +1461,10 @@ #define GPIO_PIN22_INT_ENA_S 13 /* GPIO_PIN22_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN22_CONFIG 0x00000003 #define GPIO_PIN22_CONFIG_M ((GPIO_PIN22_CONFIG_V)<<(GPIO_PIN22_CONFIG_S)) @@ -1405,8 +1498,10 @@ #define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0x00e4) /* GPIO_PIN23_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN23_INT_ENA 0x0000001F #define GPIO_PIN23_INT_ENA_M ((GPIO_PIN23_INT_ENA_V)<<(GPIO_PIN23_INT_ENA_S)) @@ -1431,7 +1526,9 @@ /* GPIO_PIN23_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN23_INT_TYPE 0x00000007 #define GPIO_PIN23_INT_TYPE_M ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S)) @@ -1449,8 +1546,10 @@ #define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0x00e8) /* GPIO_PIN24_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN24_INT_ENA 0x0000001F #define GPIO_PIN24_INT_ENA_M ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S)) @@ -1475,7 +1574,9 @@ /* GPIO_PIN24_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN24_INT_TYPE 0x00000007 #define GPIO_PIN24_INT_TYPE_M ((GPIO_PIN24_INT_TYPE_V)<<(GPIO_PIN24_INT_TYPE_S)) @@ -1493,8 +1594,10 @@ #define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0x00ec) /* GPIO_PIN25_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN25_INT_ENA 0x0000001F #define GPIO_PIN25_INT_ENA_M ((GPIO_PIN25_INT_ENA_V)<<(GPIO_PIN25_INT_ENA_S)) @@ -1519,7 +1622,9 @@ /* GPIO_PIN25_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN25_INT_TYPE 0x00000007 #define GPIO_PIN25_INT_TYPE_M ((GPIO_PIN25_INT_TYPE_V)<<(GPIO_PIN25_INT_TYPE_S)) @@ -1537,8 +1642,10 @@ #define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0x00f0) /* GPIO_PIN26_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN26_INT_ENA 0x0000001F #define GPIO_PIN26_INT_ENA_M ((GPIO_PIN26_INT_ENA_V)<<(GPIO_PIN26_INT_ENA_S)) @@ -1563,7 +1670,9 @@ /* GPIO_PIN26_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN26_INT_TYPE 0x00000007 #define GPIO_PIN26_INT_TYPE_M ((GPIO_PIN26_INT_TYPE_V)<<(GPIO_PIN26_INT_TYPE_S)) @@ -1581,8 +1690,10 @@ #define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0x00f4) /* GPIO_PIN27_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN27_INT_ENA 0x0000001F #define GPIO_PIN27_INT_ENA_M ((GPIO_PIN27_INT_ENA_V)<<(GPIO_PIN27_INT_ENA_S)) @@ -1607,7 +1718,9 @@ /* GPIO_PIN27_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN27_INT_TYPE 0x00000007 #define GPIO_PIN27_INT_TYPE_M ((GPIO_PIN27_INT_TYPE_V)<<(GPIO_PIN27_INT_TYPE_S)) @@ -1625,8 +1738,10 @@ #define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0x00f8) /* GPIO_PIN28_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN28_INT_ENA 0x0000001F #define GPIO_PIN28_INT_ENA_M ((GPIO_PIN28_INT_ENA_V)<<(GPIO_PIN28_INT_ENA_S)) @@ -1651,7 +1766,9 @@ /* GPIO_PIN28_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN28_INT_TYPE 0x00000007 #define GPIO_PIN28_INT_TYPE_M ((GPIO_PIN28_INT_TYPE_V)<<(GPIO_PIN28_INT_TYPE_S)) @@ -1669,8 +1786,10 @@ #define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0x00fc) /* GPIO_PIN29_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN29_INT_ENA 0x0000001F #define GPIO_PIN29_INT_ENA_M ((GPIO_PIN29_INT_ENA_V)<<(GPIO_PIN29_INT_ENA_S)) @@ -1695,7 +1814,9 @@ /* GPIO_PIN29_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN29_INT_TYPE 0x00000007 #define GPIO_PIN29_INT_TYPE_M ((GPIO_PIN29_INT_TYPE_V)<<(GPIO_PIN29_INT_TYPE_S)) @@ -1713,8 +1834,10 @@ #define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0x0100) /* GPIO_PIN30_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN30_INT_ENA 0x0000001F #define GPIO_PIN30_INT_ENA_M ((GPIO_PIN30_INT_ENA_V)<<(GPIO_PIN30_INT_ENA_S)) @@ -1739,7 +1862,9 @@ /* GPIO_PIN30_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN30_INT_TYPE 0x00000007 #define GPIO_PIN30_INT_TYPE_M ((GPIO_PIN30_INT_TYPE_V)<<(GPIO_PIN30_INT_TYPE_S)) @@ -1757,8 +1882,10 @@ #define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0x0104) /* GPIO_PIN31_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN31_INT_ENA 0x0000001F #define GPIO_PIN31_INT_ENA_M ((GPIO_PIN31_INT_ENA_V)<<(GPIO_PIN31_INT_ENA_S)) @@ -1783,7 +1910,9 @@ /* GPIO_PIN31_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN31_INT_TYPE 0x00000007 #define GPIO_PIN31_INT_TYPE_M ((GPIO_PIN31_INT_TYPE_V)<<(GPIO_PIN31_INT_TYPE_S)) @@ -1801,8 +1930,10 @@ #define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0x0108) /* GPIO_PIN32_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN32_INT_ENA 0x0000001F #define GPIO_PIN32_INT_ENA_M ((GPIO_PIN32_INT_ENA_V)<<(GPIO_PIN32_INT_ENA_S)) @@ -1827,7 +1958,9 @@ /* GPIO_PIN32_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN32_INT_TYPE 0x00000007 #define GPIO_PIN32_INT_TYPE_M ((GPIO_PIN32_INT_TYPE_V)<<(GPIO_PIN32_INT_TYPE_S)) @@ -1845,8 +1978,10 @@ #define GPIO_PIN33_REG (DR_REG_GPIO_BASE + 0x010c) /* GPIO_PIN33_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN33_INT_ENA 0x0000001F #define GPIO_PIN33_INT_ENA_M ((GPIO_PIN33_INT_ENA_V)<<(GPIO_PIN33_INT_ENA_S)) @@ -1871,7 +2006,9 @@ /* GPIO_PIN33_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN33_INT_TYPE 0x00000007 #define GPIO_PIN33_INT_TYPE_M ((GPIO_PIN33_INT_TYPE_V)<<(GPIO_PIN33_INT_TYPE_S)) @@ -1889,8 +2026,10 @@ #define GPIO_PIN34_REG (DR_REG_GPIO_BASE + 0x0110) /* GPIO_PIN34_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN34_INT_ENA 0x0000001F #define GPIO_PIN34_INT_ENA_M ((GPIO_PIN34_INT_ENA_V)<<(GPIO_PIN34_INT_ENA_S)) @@ -1915,7 +2054,9 @@ /* GPIO_PIN34_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN34_INT_TYPE 0x00000007 #define GPIO_PIN34_INT_TYPE_M ((GPIO_PIN34_INT_TYPE_V)<<(GPIO_PIN34_INT_TYPE_S)) @@ -1933,8 +2074,10 @@ #define GPIO_PIN35_REG (DR_REG_GPIO_BASE + 0x0114) /* GPIO_PIN35_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN35_INT_ENA 0x0000001F #define GPIO_PIN35_INT_ENA_M ((GPIO_PIN35_INT_ENA_V)<<(GPIO_PIN35_INT_ENA_S)) @@ -1959,7 +2102,9 @@ /* GPIO_PIN35_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN35_INT_TYPE 0x00000007 #define GPIO_PIN35_INT_TYPE_M ((GPIO_PIN35_INT_TYPE_V)<<(GPIO_PIN35_INT_TYPE_S)) @@ -1977,8 +2122,10 @@ #define GPIO_PIN36_REG (DR_REG_GPIO_BASE + 0x0118) /* GPIO_PIN36_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN36_INT_ENA 0x0000001F #define GPIO_PIN36_INT_ENA_M ((GPIO_PIN36_INT_ENA_V)<<(GPIO_PIN36_INT_ENA_S)) @@ -2003,7 +2150,9 @@ /* GPIO_PIN36_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN36_INT_TYPE 0x00000007 #define GPIO_PIN36_INT_TYPE_M ((GPIO_PIN36_INT_TYPE_V)<<(GPIO_PIN36_INT_TYPE_S)) @@ -2021,8 +2170,10 @@ #define GPIO_PIN37_REG (DR_REG_GPIO_BASE + 0x011c) /* GPIO_PIN37_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN37_INT_ENA 0x0000001F #define GPIO_PIN37_INT_ENA_M ((GPIO_PIN37_INT_ENA_V)<<(GPIO_PIN37_INT_ENA_S)) @@ -2047,7 +2198,9 @@ /* GPIO_PIN37_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN37_INT_TYPE 0x00000007 #define GPIO_PIN37_INT_TYPE_M ((GPIO_PIN37_INT_TYPE_V)<<(GPIO_PIN37_INT_TYPE_S)) @@ -2065,8 +2218,10 @@ #define GPIO_PIN38_REG (DR_REG_GPIO_BASE + 0x0120) /* GPIO_PIN38_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN38_INT_ENA 0x0000001F #define GPIO_PIN38_INT_ENA_M ((GPIO_PIN38_INT_ENA_V)<<(GPIO_PIN38_INT_ENA_S)) @@ -2091,7 +2246,9 @@ /* GPIO_PIN38_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN38_INT_TYPE 0x00000007 #define GPIO_PIN38_INT_TYPE_M ((GPIO_PIN38_INT_TYPE_V)<<(GPIO_PIN38_INT_TYPE_S)) @@ -2109,8 +2266,10 @@ #define GPIO_PIN39_REG (DR_REG_GPIO_BASE + 0x0124) /* GPIO_PIN39_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ -/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt - enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable */ +/* Description: bit0: APP CPU interrupt enable bit1: APP CPU non-maskable + * interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU + * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. + */ #define GPIO_PIN39_INT_ENA 0x0000001F #define GPIO_PIN39_INT_ENA_M ((GPIO_PIN39_INT_ENA_V)<<(GPIO_PIN39_INT_ENA_S)) @@ -2135,7 +2294,9 @@ /* GPIO_PIN39_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: if set to 0: GPIO interrupt disable if set to 1: rising edge - trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger */ + * trigger if set to 2: falling edge trigger if set to 3: any edge + * trigger if set to 4: low level trigger if set to 5: high level trigger. + */ #define GPIO_PIN39_INT_TYPE 0x00000007 #define GPIO_PIN39_INT_TYPE_M ((GPIO_PIN39_INT_TYPE_V)<<(GPIO_PIN39_INT_TYPE_S)) @@ -2197,18 +2358,21 @@ #define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0130) /* GPIO_SIG0_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG0_IN_SEL (BIT(7)) +#define GPIO_SIG0_IN_SEL (BIT(7)) #define GPIO_SIG0_IN_SEL_M (BIT(7)) #define GPIO_SIG0_IN_SEL_V 0x1 #define GPIO_SIG0_IN_SEL_S 7 /* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC0_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC0_IN_INV_SEL (BIT(6)) #define GPIO_FUNC0_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC0_IN_INV_SEL_V 0x1 #define GPIO_FUNC0_IN_INV_SEL_S 6 @@ -2216,7 +2380,7 @@ /* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC0_IN_SEL 0x0000003F +#define GPIO_FUNC0_IN_SEL 0x0000003F #define GPIO_FUNC0_IN_SEL_M ((GPIO_FUNC0_IN_SEL_V)<<(GPIO_FUNC0_IN_SEL_S)) #define GPIO_FUNC0_IN_SEL_V 0x3F #define GPIO_FUNC0_IN_SEL_S 0 @@ -2224,18 +2388,21 @@ #define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0134) /* GPIO_SIG1_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG1_IN_SEL (BIT(7)) +#define GPIO_SIG1_IN_SEL (BIT(7)) #define GPIO_SIG1_IN_SEL_M (BIT(7)) #define GPIO_SIG1_IN_SEL_V 0x1 #define GPIO_SIG1_IN_SEL_S 7 /* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC1_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC1_IN_INV_SEL (BIT(6)) #define GPIO_FUNC1_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC1_IN_INV_SEL_V 0x1 #define GPIO_FUNC1_IN_INV_SEL_S 6 @@ -2243,7 +2410,7 @@ /* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC1_IN_SEL 0x0000003F +#define GPIO_FUNC1_IN_SEL 0x0000003F #define GPIO_FUNC1_IN_SEL_M ((GPIO_FUNC1_IN_SEL_V)<<(GPIO_FUNC1_IN_SEL_S)) #define GPIO_FUNC1_IN_SEL_V 0x3F #define GPIO_FUNC1_IN_SEL_S 0 @@ -2251,18 +2418,21 @@ #define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0138) /* GPIO_SIG2_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG2_IN_SEL (BIT(7)) +#define GPIO_SIG2_IN_SEL (BIT(7)) #define GPIO_SIG2_IN_SEL_M (BIT(7)) #define GPIO_SIG2_IN_SEL_V 0x1 #define GPIO_SIG2_IN_SEL_S 7 /* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC2_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC2_IN_INV_SEL (BIT(6)) #define GPIO_FUNC2_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC2_IN_INV_SEL_V 0x1 #define GPIO_FUNC2_IN_INV_SEL_S 6 @@ -2270,7 +2440,7 @@ /* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC2_IN_SEL 0x0000003F +#define GPIO_FUNC2_IN_SEL 0x0000003F #define GPIO_FUNC2_IN_SEL_M ((GPIO_FUNC2_IN_SEL_V)<<(GPIO_FUNC2_IN_SEL_S)) #define GPIO_FUNC2_IN_SEL_V 0x3F #define GPIO_FUNC2_IN_SEL_S 0 @@ -2278,18 +2448,21 @@ #define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x013c) /* GPIO_SIG3_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG3_IN_SEL (BIT(7)) +#define GPIO_SIG3_IN_SEL (BIT(7)) #define GPIO_SIG3_IN_SEL_M (BIT(7)) #define GPIO_SIG3_IN_SEL_V 0x1 #define GPIO_SIG3_IN_SEL_S 7 /* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC3_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC3_IN_INV_SEL (BIT(6)) #define GPIO_FUNC3_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC3_IN_INV_SEL_V 0x1 #define GPIO_FUNC3_IN_INV_SEL_S 6 @@ -2297,7 +2470,7 @@ /* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC3_IN_SEL 0x0000003F +#define GPIO_FUNC3_IN_SEL 0x0000003F #define GPIO_FUNC3_IN_SEL_M ((GPIO_FUNC3_IN_SEL_V)<<(GPIO_FUNC3_IN_SEL_S)) #define GPIO_FUNC3_IN_SEL_V 0x3F #define GPIO_FUNC3_IN_SEL_S 0 @@ -2305,18 +2478,21 @@ #define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0140) /* GPIO_SIG4_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG4_IN_SEL (BIT(7)) +#define GPIO_SIG4_IN_SEL (BIT(7)) #define GPIO_SIG4_IN_SEL_M (BIT(7)) #define GPIO_SIG4_IN_SEL_V 0x1 #define GPIO_SIG4_IN_SEL_S 7 /* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC4_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC4_IN_INV_SEL (BIT(6)) #define GPIO_FUNC4_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC4_IN_INV_SEL_V 0x1 #define GPIO_FUNC4_IN_INV_SEL_S 6 @@ -2324,7 +2500,7 @@ /* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC4_IN_SEL 0x0000003F +#define GPIO_FUNC4_IN_SEL 0x0000003F #define GPIO_FUNC4_IN_SEL_M ((GPIO_FUNC4_IN_SEL_V)<<(GPIO_FUNC4_IN_SEL_S)) #define GPIO_FUNC4_IN_SEL_V 0x3F #define GPIO_FUNC4_IN_SEL_S 0 @@ -2332,18 +2508,21 @@ #define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0144) /* GPIO_SIG5_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG5_IN_SEL (BIT(7)) +#define GPIO_SIG5_IN_SEL (BIT(7)) #define GPIO_SIG5_IN_SEL_M (BIT(7)) #define GPIO_SIG5_IN_SEL_V 0x1 #define GPIO_SIG5_IN_SEL_S 7 /* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC5_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC5_IN_INV_SEL (BIT(6)) #define GPIO_FUNC5_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC5_IN_INV_SEL_V 0x1 #define GPIO_FUNC5_IN_INV_SEL_S 6 @@ -2351,7 +2530,7 @@ /* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC5_IN_SEL 0x0000003F +#define GPIO_FUNC5_IN_SEL 0x0000003F #define GPIO_FUNC5_IN_SEL_M ((GPIO_FUNC5_IN_SEL_V)<<(GPIO_FUNC5_IN_SEL_S)) #define GPIO_FUNC5_IN_SEL_V 0x3F #define GPIO_FUNC5_IN_SEL_S 0 @@ -2359,18 +2538,21 @@ #define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0148) /* GPIO_SIG6_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG6_IN_SEL (BIT(7)) +#define GPIO_SIG6_IN_SEL (BIT(7)) #define GPIO_SIG6_IN_SEL_M (BIT(7)) #define GPIO_SIG6_IN_SEL_V 0x1 #define GPIO_SIG6_IN_SEL_S 7 /* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC6_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC6_IN_INV_SEL (BIT(6)) #define GPIO_FUNC6_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC6_IN_INV_SEL_V 0x1 #define GPIO_FUNC6_IN_INV_SEL_S 6 @@ -2378,7 +2560,7 @@ /* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC6_IN_SEL 0x0000003F +#define GPIO_FUNC6_IN_SEL 0x0000003F #define GPIO_FUNC6_IN_SEL_M ((GPIO_FUNC6_IN_SEL_V)<<(GPIO_FUNC6_IN_SEL_S)) #define GPIO_FUNC6_IN_SEL_V 0x3F #define GPIO_FUNC6_IN_SEL_S 0 @@ -2386,18 +2568,21 @@ #define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x014c) /* GPIO_SIG7_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG7_IN_SEL (BIT(7)) +#define GPIO_SIG7_IN_SEL (BIT(7)) #define GPIO_SIG7_IN_SEL_M (BIT(7)) #define GPIO_SIG7_IN_SEL_V 0x1 #define GPIO_SIG7_IN_SEL_S 7 /* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC7_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC7_IN_INV_SEL (BIT(6)) #define GPIO_FUNC7_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC7_IN_INV_SEL_V 0x1 #define GPIO_FUNC7_IN_INV_SEL_S 6 @@ -2405,7 +2590,7 @@ /* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC7_IN_SEL 0x0000003F +#define GPIO_FUNC7_IN_SEL 0x0000003F #define GPIO_FUNC7_IN_SEL_M ((GPIO_FUNC7_IN_SEL_V)<<(GPIO_FUNC7_IN_SEL_S)) #define GPIO_FUNC7_IN_SEL_V 0x3F #define GPIO_FUNC7_IN_SEL_S 0 @@ -2413,18 +2598,21 @@ #define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0150) /* GPIO_SIG8_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG8_IN_SEL (BIT(7)) +#define GPIO_SIG8_IN_SEL (BIT(7)) #define GPIO_SIG8_IN_SEL_M (BIT(7)) #define GPIO_SIG8_IN_SEL_V 0x1 #define GPIO_SIG8_IN_SEL_S 7 /* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC8_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC8_IN_INV_SEL (BIT(6)) #define GPIO_FUNC8_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC8_IN_INV_SEL_V 0x1 #define GPIO_FUNC8_IN_INV_SEL_S 6 @@ -2432,7 +2620,7 @@ /* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC8_IN_SEL 0x0000003F +#define GPIO_FUNC8_IN_SEL 0x0000003F #define GPIO_FUNC8_IN_SEL_M ((GPIO_FUNC8_IN_SEL_V)<<(GPIO_FUNC8_IN_SEL_S)) #define GPIO_FUNC8_IN_SEL_V 0x3F #define GPIO_FUNC8_IN_SEL_S 0 @@ -2440,18 +2628,21 @@ #define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0154) /* GPIO_SIG9_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG9_IN_SEL (BIT(7)) +#define GPIO_SIG9_IN_SEL (BIT(7)) #define GPIO_SIG9_IN_SEL_M (BIT(7)) #define GPIO_SIG9_IN_SEL_V 0x1 #define GPIO_SIG9_IN_SEL_S 7 /* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC9_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC9_IN_INV_SEL (BIT(6)) #define GPIO_FUNC9_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC9_IN_INV_SEL_V 0x1 #define GPIO_FUNC9_IN_INV_SEL_S 6 @@ -2459,7 +2650,7 @@ /* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC9_IN_SEL 0x0000003F +#define GPIO_FUNC9_IN_SEL 0x0000003F #define GPIO_FUNC9_IN_SEL_M ((GPIO_FUNC9_IN_SEL_V)<<(GPIO_FUNC9_IN_SEL_S)) #define GPIO_FUNC9_IN_SEL_V 0x3F #define GPIO_FUNC9_IN_SEL_S 0 @@ -2467,18 +2658,21 @@ #define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0158) /* GPIO_SIG10_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG10_IN_SEL (BIT(7)) +#define GPIO_SIG10_IN_SEL (BIT(7)) #define GPIO_SIG10_IN_SEL_M (BIT(7)) #define GPIO_SIG10_IN_SEL_V 0x1 #define GPIO_SIG10_IN_SEL_S 7 /* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC10_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC10_IN_INV_SEL (BIT(6)) #define GPIO_FUNC10_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC10_IN_INV_SEL_V 0x1 #define GPIO_FUNC10_IN_INV_SEL_S 6 @@ -2486,7 +2680,7 @@ /* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC10_IN_SEL 0x0000003F +#define GPIO_FUNC10_IN_SEL 0x0000003F #define GPIO_FUNC10_IN_SEL_M ((GPIO_FUNC10_IN_SEL_V)<<(GPIO_FUNC10_IN_SEL_S)) #define GPIO_FUNC10_IN_SEL_V 0x3F #define GPIO_FUNC10_IN_SEL_S 0 @@ -2494,18 +2688,21 @@ #define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x015c) /* GPIO_SIG11_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG11_IN_SEL (BIT(7)) +#define GPIO_SIG11_IN_SEL (BIT(7)) #define GPIO_SIG11_IN_SEL_M (BIT(7)) #define GPIO_SIG11_IN_SEL_V 0x1 #define GPIO_SIG11_IN_SEL_S 7 /* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC11_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC11_IN_INV_SEL (BIT(6)) #define GPIO_FUNC11_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC11_IN_INV_SEL_V 0x1 #define GPIO_FUNC11_IN_INV_SEL_S 6 @@ -2513,7 +2710,7 @@ /* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC11_IN_SEL 0x0000003F +#define GPIO_FUNC11_IN_SEL 0x0000003F #define GPIO_FUNC11_IN_SEL_M ((GPIO_FUNC11_IN_SEL_V)<<(GPIO_FUNC11_IN_SEL_S)) #define GPIO_FUNC11_IN_SEL_V 0x3F #define GPIO_FUNC11_IN_SEL_S 0 @@ -2521,18 +2718,21 @@ #define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0160) /* GPIO_SIG12_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG12_IN_SEL (BIT(7)) +#define GPIO_SIG12_IN_SEL (BIT(7)) #define GPIO_SIG12_IN_SEL_M (BIT(7)) #define GPIO_SIG12_IN_SEL_V 0x1 #define GPIO_SIG12_IN_SEL_S 7 /* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC12_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC12_IN_INV_SEL (BIT(6)) #define GPIO_FUNC12_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC12_IN_INV_SEL_V 0x1 #define GPIO_FUNC12_IN_INV_SEL_S 6 @@ -2540,7 +2740,7 @@ /* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC12_IN_SEL 0x0000003F +#define GPIO_FUNC12_IN_SEL 0x0000003F #define GPIO_FUNC12_IN_SEL_M ((GPIO_FUNC12_IN_SEL_V)<<(GPIO_FUNC12_IN_SEL_S)) #define GPIO_FUNC12_IN_SEL_V 0x3F #define GPIO_FUNC12_IN_SEL_S 0 @@ -2548,18 +2748,21 @@ #define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0164) /* GPIO_SIG13_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG13_IN_SEL (BIT(7)) +#define GPIO_SIG13_IN_SEL (BIT(7)) #define GPIO_SIG13_IN_SEL_M (BIT(7)) #define GPIO_SIG13_IN_SEL_V 0x1 #define GPIO_SIG13_IN_SEL_S 7 /* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC13_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC13_IN_INV_SEL (BIT(6)) #define GPIO_FUNC13_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC13_IN_INV_SEL_V 0x1 #define GPIO_FUNC13_IN_INV_SEL_S 6 @@ -2567,7 +2770,7 @@ /* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC13_IN_SEL 0x0000003F +#define GPIO_FUNC13_IN_SEL 0x0000003F #define GPIO_FUNC13_IN_SEL_M ((GPIO_FUNC13_IN_SEL_V)<<(GPIO_FUNC13_IN_SEL_S)) #define GPIO_FUNC13_IN_SEL_V 0x3F #define GPIO_FUNC13_IN_SEL_S 0 @@ -2575,18 +2778,21 @@ #define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0168) /* GPIO_SIG14_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG14_IN_SEL (BIT(7)) +#define GPIO_SIG14_IN_SEL (BIT(7)) #define GPIO_SIG14_IN_SEL_M (BIT(7)) #define GPIO_SIG14_IN_SEL_V 0x1 #define GPIO_SIG14_IN_SEL_S 7 /* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC14_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC14_IN_INV_SEL (BIT(6)) #define GPIO_FUNC14_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC14_IN_INV_SEL_V 0x1 #define GPIO_FUNC14_IN_INV_SEL_S 6 @@ -2594,7 +2800,7 @@ /* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC14_IN_SEL 0x0000003F +#define GPIO_FUNC14_IN_SEL 0x0000003F #define GPIO_FUNC14_IN_SEL_M ((GPIO_FUNC14_IN_SEL_V)<<(GPIO_FUNC14_IN_SEL_S)) #define GPIO_FUNC14_IN_SEL_V 0x3F #define GPIO_FUNC14_IN_SEL_S 0 @@ -2602,18 +2808,21 @@ #define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x016c) /* GPIO_SIG15_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG15_IN_SEL (BIT(7)) +#define GPIO_SIG15_IN_SEL (BIT(7)) #define GPIO_SIG15_IN_SEL_M (BIT(7)) #define GPIO_SIG15_IN_SEL_V 0x1 #define GPIO_SIG15_IN_SEL_S 7 /* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC15_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC15_IN_INV_SEL (BIT(6)) #define GPIO_FUNC15_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC15_IN_INV_SEL_V 0x1 #define GPIO_FUNC15_IN_INV_SEL_S 6 @@ -2621,7 +2830,7 @@ /* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC15_IN_SEL 0x0000003F +#define GPIO_FUNC15_IN_SEL 0x0000003F #define GPIO_FUNC15_IN_SEL_M ((GPIO_FUNC15_IN_SEL_V)<<(GPIO_FUNC15_IN_SEL_S)) #define GPIO_FUNC15_IN_SEL_V 0x3F #define GPIO_FUNC15_IN_SEL_S 0 @@ -2629,18 +2838,21 @@ #define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0170) /* GPIO_SIG16_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG16_IN_SEL (BIT(7)) +#define GPIO_SIG16_IN_SEL (BIT(7)) #define GPIO_SIG16_IN_SEL_M (BIT(7)) #define GPIO_SIG16_IN_SEL_V 0x1 #define GPIO_SIG16_IN_SEL_S 7 /* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC16_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC16_IN_INV_SEL (BIT(6)) #define GPIO_FUNC16_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC16_IN_INV_SEL_V 0x1 #define GPIO_FUNC16_IN_INV_SEL_S 6 @@ -2648,7 +2860,7 @@ /* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC16_IN_SEL 0x0000003F +#define GPIO_FUNC16_IN_SEL 0x0000003F #define GPIO_FUNC16_IN_SEL_M ((GPIO_FUNC16_IN_SEL_V)<<(GPIO_FUNC16_IN_SEL_S)) #define GPIO_FUNC16_IN_SEL_V 0x3F #define GPIO_FUNC16_IN_SEL_S 0 @@ -2656,18 +2868,21 @@ #define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0174) /* GPIO_SIG17_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG17_IN_SEL (BIT(7)) +#define GPIO_SIG17_IN_SEL (BIT(7)) #define GPIO_SIG17_IN_SEL_M (BIT(7)) #define GPIO_SIG17_IN_SEL_V 0x1 #define GPIO_SIG17_IN_SEL_S 7 /* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC17_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC17_IN_INV_SEL (BIT(6)) #define GPIO_FUNC17_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC17_IN_INV_SEL_V 0x1 #define GPIO_FUNC17_IN_INV_SEL_S 6 @@ -2675,7 +2890,7 @@ /* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC17_IN_SEL 0x0000003F +#define GPIO_FUNC17_IN_SEL 0x0000003F #define GPIO_FUNC17_IN_SEL_M ((GPIO_FUNC17_IN_SEL_V)<<(GPIO_FUNC17_IN_SEL_S)) #define GPIO_FUNC17_IN_SEL_V 0x3F #define GPIO_FUNC17_IN_SEL_S 0 @@ -2683,18 +2898,21 @@ #define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0178) /* GPIO_SIG18_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG18_IN_SEL (BIT(7)) +#define GPIO_SIG18_IN_SEL (BIT(7)) #define GPIO_SIG18_IN_SEL_M (BIT(7)) #define GPIO_SIG18_IN_SEL_V 0x1 #define GPIO_SIG18_IN_SEL_S 7 /* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC18_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC18_IN_INV_SEL (BIT(6)) #define GPIO_FUNC18_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC18_IN_INV_SEL_V 0x1 #define GPIO_FUNC18_IN_INV_SEL_S 6 @@ -2702,7 +2920,7 @@ /* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC18_IN_SEL 0x0000003F +#define GPIO_FUNC18_IN_SEL 0x0000003F #define GPIO_FUNC18_IN_SEL_M ((GPIO_FUNC18_IN_SEL_V)<<(GPIO_FUNC18_IN_SEL_S)) #define GPIO_FUNC18_IN_SEL_V 0x3F #define GPIO_FUNC18_IN_SEL_S 0 @@ -2710,18 +2928,21 @@ #define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x017c) /* GPIO_SIG19_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG19_IN_SEL (BIT(7)) +#define GPIO_SIG19_IN_SEL (BIT(7)) #define GPIO_SIG19_IN_SEL_M (BIT(7)) #define GPIO_SIG19_IN_SEL_V 0x1 #define GPIO_SIG19_IN_SEL_S 7 /* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC19_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC19_IN_INV_SEL (BIT(6)) #define GPIO_FUNC19_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC19_IN_INV_SEL_V 0x1 #define GPIO_FUNC19_IN_INV_SEL_S 6 @@ -2729,7 +2950,7 @@ /* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC19_IN_SEL 0x0000003F +#define GPIO_FUNC19_IN_SEL 0x0000003F #define GPIO_FUNC19_IN_SEL_M ((GPIO_FUNC19_IN_SEL_V)<<(GPIO_FUNC19_IN_SEL_S)) #define GPIO_FUNC19_IN_SEL_V 0x3F #define GPIO_FUNC19_IN_SEL_S 0 @@ -2737,18 +2958,21 @@ #define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0180) /* GPIO_SIG20_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG20_IN_SEL (BIT(7)) +#define GPIO_SIG20_IN_SEL (BIT(7)) #define GPIO_SIG20_IN_SEL_M (BIT(7)) #define GPIO_SIG20_IN_SEL_V 0x1 #define GPIO_SIG20_IN_SEL_S 7 /* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC20_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC20_IN_INV_SEL (BIT(6)) #define GPIO_FUNC20_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC20_IN_INV_SEL_V 0x1 #define GPIO_FUNC20_IN_INV_SEL_S 6 @@ -2756,7 +2980,7 @@ /* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC20_IN_SEL 0x0000003F +#define GPIO_FUNC20_IN_SEL 0x0000003F #define GPIO_FUNC20_IN_SEL_M ((GPIO_FUNC20_IN_SEL_V)<<(GPIO_FUNC20_IN_SEL_S)) #define GPIO_FUNC20_IN_SEL_V 0x3F #define GPIO_FUNC20_IN_SEL_S 0 @@ -2764,18 +2988,21 @@ #define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0184) /* GPIO_SIG21_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG21_IN_SEL (BIT(7)) +#define GPIO_SIG21_IN_SEL (BIT(7)) #define GPIO_SIG21_IN_SEL_M (BIT(7)) #define GPIO_SIG21_IN_SEL_V 0x1 #define GPIO_SIG21_IN_SEL_S 7 /* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC21_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC21_IN_INV_SEL (BIT(6)) #define GPIO_FUNC21_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC21_IN_INV_SEL_V 0x1 #define GPIO_FUNC21_IN_INV_SEL_S 6 @@ -2783,7 +3010,7 @@ /* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC21_IN_SEL 0x0000003F +#define GPIO_FUNC21_IN_SEL 0x0000003F #define GPIO_FUNC21_IN_SEL_M ((GPIO_FUNC21_IN_SEL_V)<<(GPIO_FUNC21_IN_SEL_S)) #define GPIO_FUNC21_IN_SEL_V 0x3F #define GPIO_FUNC21_IN_SEL_S 0 @@ -2791,18 +3018,21 @@ #define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0188) /* GPIO_SIG22_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG22_IN_SEL (BIT(7)) +#define GPIO_SIG22_IN_SEL (BIT(7)) #define GPIO_SIG22_IN_SEL_M (BIT(7)) #define GPIO_SIG22_IN_SEL_V 0x1 #define GPIO_SIG22_IN_SEL_S 7 /* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC22_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC22_IN_INV_SEL (BIT(6)) #define GPIO_FUNC22_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC22_IN_INV_SEL_V 0x1 #define GPIO_FUNC22_IN_INV_SEL_S 6 @@ -2810,7 +3040,7 @@ /* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC22_IN_SEL 0x0000003F +#define GPIO_FUNC22_IN_SEL 0x0000003F #define GPIO_FUNC22_IN_SEL_M ((GPIO_FUNC22_IN_SEL_V)<<(GPIO_FUNC22_IN_SEL_S)) #define GPIO_FUNC22_IN_SEL_V 0x3F #define GPIO_FUNC22_IN_SEL_S 0 @@ -2818,18 +3048,21 @@ #define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x018c) /* GPIO_SIG23_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG23_IN_SEL (BIT(7)) +#define GPIO_SIG23_IN_SEL (BIT(7)) #define GPIO_SIG23_IN_SEL_M (BIT(7)) #define GPIO_SIG23_IN_SEL_V 0x1 #define GPIO_SIG23_IN_SEL_S 7 /* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC23_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC23_IN_INV_SEL (BIT(6)) #define GPIO_FUNC23_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC23_IN_INV_SEL_V 0x1 #define GPIO_FUNC23_IN_INV_SEL_S 6 @@ -2837,7 +3070,7 @@ /* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC23_IN_SEL 0x0000003F +#define GPIO_FUNC23_IN_SEL 0x0000003F #define GPIO_FUNC23_IN_SEL_M ((GPIO_FUNC23_IN_SEL_V)<<(GPIO_FUNC23_IN_SEL_S)) #define GPIO_FUNC23_IN_SEL_V 0x3F #define GPIO_FUNC23_IN_SEL_S 0 @@ -2845,18 +3078,21 @@ #define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0190) /* GPIO_SIG24_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG24_IN_SEL (BIT(7)) +#define GPIO_SIG24_IN_SEL (BIT(7)) #define GPIO_SIG24_IN_SEL_M (BIT(7)) #define GPIO_SIG24_IN_SEL_V 0x1 #define GPIO_SIG24_IN_SEL_S 7 /* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC24_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC24_IN_INV_SEL (BIT(6)) #define GPIO_FUNC24_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC24_IN_INV_SEL_V 0x1 #define GPIO_FUNC24_IN_INV_SEL_S 6 @@ -2864,7 +3100,7 @@ /* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC24_IN_SEL 0x0000003F +#define GPIO_FUNC24_IN_SEL 0x0000003F #define GPIO_FUNC24_IN_SEL_M ((GPIO_FUNC24_IN_SEL_V)<<(GPIO_FUNC24_IN_SEL_S)) #define GPIO_FUNC24_IN_SEL_V 0x3F #define GPIO_FUNC24_IN_SEL_S 0 @@ -2872,18 +3108,21 @@ #define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0194) /* GPIO_SIG25_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG25_IN_SEL (BIT(7)) +#define GPIO_SIG25_IN_SEL (BIT(7)) #define GPIO_SIG25_IN_SEL_M (BIT(7)) #define GPIO_SIG25_IN_SEL_V 0x1 #define GPIO_SIG25_IN_SEL_S 7 /* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC25_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC25_IN_INV_SEL (BIT(6)) #define GPIO_FUNC25_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC25_IN_INV_SEL_V 0x1 #define GPIO_FUNC25_IN_INV_SEL_S 6 @@ -2891,7 +3130,7 @@ /* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC25_IN_SEL 0x0000003F +#define GPIO_FUNC25_IN_SEL 0x0000003F #define GPIO_FUNC25_IN_SEL_M ((GPIO_FUNC25_IN_SEL_V)<<(GPIO_FUNC25_IN_SEL_S)) #define GPIO_FUNC25_IN_SEL_V 0x3F #define GPIO_FUNC25_IN_SEL_S 0 @@ -2899,18 +3138,21 @@ #define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0198) /* GPIO_SIG26_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG26_IN_SEL (BIT(7)) +#define GPIO_SIG26_IN_SEL (BIT(7)) #define GPIO_SIG26_IN_SEL_M (BIT(7)) #define GPIO_SIG26_IN_SEL_V 0x1 #define GPIO_SIG26_IN_SEL_S 7 /* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC26_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC26_IN_INV_SEL (BIT(6)) #define GPIO_FUNC26_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC26_IN_INV_SEL_V 0x1 #define GPIO_FUNC26_IN_INV_SEL_S 6 @@ -2918,7 +3160,7 @@ /* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC26_IN_SEL 0x0000003F +#define GPIO_FUNC26_IN_SEL 0x0000003F #define GPIO_FUNC26_IN_SEL_M ((GPIO_FUNC26_IN_SEL_V)<<(GPIO_FUNC26_IN_SEL_S)) #define GPIO_FUNC26_IN_SEL_V 0x3F #define GPIO_FUNC26_IN_SEL_S 0 @@ -2926,18 +3168,21 @@ #define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x019c) /* GPIO_SIG27_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG27_IN_SEL (BIT(7)) +#define GPIO_SIG27_IN_SEL (BIT(7)) #define GPIO_SIG27_IN_SEL_M (BIT(7)) #define GPIO_SIG27_IN_SEL_V 0x1 #define GPIO_SIG27_IN_SEL_S 7 /* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC27_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC27_IN_INV_SEL (BIT(6)) #define GPIO_FUNC27_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC27_IN_INV_SEL_V 0x1 #define GPIO_FUNC27_IN_INV_SEL_S 6 @@ -2945,7 +3190,7 @@ /* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC27_IN_SEL 0x0000003F +#define GPIO_FUNC27_IN_SEL 0x0000003F #define GPIO_FUNC27_IN_SEL_M ((GPIO_FUNC27_IN_SEL_V)<<(GPIO_FUNC27_IN_SEL_S)) #define GPIO_FUNC27_IN_SEL_V 0x3F #define GPIO_FUNC27_IN_SEL_S 0 @@ -2953,18 +3198,21 @@ #define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01a0) /* GPIO_SIG28_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG28_IN_SEL (BIT(7)) +#define GPIO_SIG28_IN_SEL (BIT(7)) #define GPIO_SIG28_IN_SEL_M (BIT(7)) #define GPIO_SIG28_IN_SEL_V 0x1 #define GPIO_SIG28_IN_SEL_S 7 /* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC28_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC28_IN_INV_SEL (BIT(6)) #define GPIO_FUNC28_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC28_IN_INV_SEL_V 0x1 #define GPIO_FUNC28_IN_INV_SEL_S 6 @@ -2972,7 +3220,7 @@ /* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC28_IN_SEL 0x0000003F +#define GPIO_FUNC28_IN_SEL 0x0000003F #define GPIO_FUNC28_IN_SEL_M ((GPIO_FUNC28_IN_SEL_V)<<(GPIO_FUNC28_IN_SEL_S)) #define GPIO_FUNC28_IN_SEL_V 0x3F #define GPIO_FUNC28_IN_SEL_S 0 @@ -2980,18 +3228,21 @@ #define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01a4) /* GPIO_SIG29_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG29_IN_SEL (BIT(7)) +#define GPIO_SIG29_IN_SEL (BIT(7)) #define GPIO_SIG29_IN_SEL_M (BIT(7)) #define GPIO_SIG29_IN_SEL_V 0x1 #define GPIO_SIG29_IN_SEL_S 7 /* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC29_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC29_IN_INV_SEL (BIT(6)) #define GPIO_FUNC29_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC29_IN_INV_SEL_V 0x1 #define GPIO_FUNC29_IN_INV_SEL_S 6 @@ -2999,7 +3250,7 @@ /* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC29_IN_SEL 0x0000003F +#define GPIO_FUNC29_IN_SEL 0x0000003F #define GPIO_FUNC29_IN_SEL_M ((GPIO_FUNC29_IN_SEL_V)<<(GPIO_FUNC29_IN_SEL_S)) #define GPIO_FUNC29_IN_SEL_V 0x3F #define GPIO_FUNC29_IN_SEL_S 0 @@ -3007,18 +3258,21 @@ #define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01a8) /* GPIO_SIG30_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG30_IN_SEL (BIT(7)) +#define GPIO_SIG30_IN_SEL (BIT(7)) #define GPIO_SIG30_IN_SEL_M (BIT(7)) #define GPIO_SIG30_IN_SEL_V 0x1 #define GPIO_SIG30_IN_SEL_S 7 /* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC30_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC30_IN_INV_SEL (BIT(6)) #define GPIO_FUNC30_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC30_IN_INV_SEL_V 0x1 #define GPIO_FUNC30_IN_INV_SEL_S 6 @@ -3026,7 +3280,7 @@ /* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC30_IN_SEL 0x0000003F +#define GPIO_FUNC30_IN_SEL 0x0000003F #define GPIO_FUNC30_IN_SEL_M ((GPIO_FUNC30_IN_SEL_V)<<(GPIO_FUNC30_IN_SEL_S)) #define GPIO_FUNC30_IN_SEL_V 0x3F #define GPIO_FUNC30_IN_SEL_S 0 @@ -3034,18 +3288,21 @@ #define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01ac) /* GPIO_SIG31_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG31_IN_SEL (BIT(7)) +#define GPIO_SIG31_IN_SEL (BIT(7)) #define GPIO_SIG31_IN_SEL_M (BIT(7)) #define GPIO_SIG31_IN_SEL_V 0x1 #define GPIO_SIG31_IN_SEL_S 7 /* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC31_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC31_IN_INV_SEL (BIT(6)) #define GPIO_FUNC31_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC31_IN_INV_SEL_V 0x1 #define GPIO_FUNC31_IN_INV_SEL_S 6 @@ -3053,7 +3310,7 @@ /* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC31_IN_SEL 0x0000003F +#define GPIO_FUNC31_IN_SEL 0x0000003F #define GPIO_FUNC31_IN_SEL_M ((GPIO_FUNC31_IN_SEL_V)<<(GPIO_FUNC31_IN_SEL_S)) #define GPIO_FUNC31_IN_SEL_V 0x3F #define GPIO_FUNC31_IN_SEL_S 0 @@ -3061,18 +3318,21 @@ #define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01b0) /* GPIO_SIG32_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG32_IN_SEL (BIT(7)) +#define GPIO_SIG32_IN_SEL (BIT(7)) #define GPIO_SIG32_IN_SEL_M (BIT(7)) #define GPIO_SIG32_IN_SEL_V 0x1 #define GPIO_SIG32_IN_SEL_S 7 /* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC32_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC32_IN_INV_SEL (BIT(6)) #define GPIO_FUNC32_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC32_IN_INV_SEL_V 0x1 #define GPIO_FUNC32_IN_INV_SEL_S 6 @@ -3080,7 +3340,7 @@ /* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC32_IN_SEL 0x0000003F +#define GPIO_FUNC32_IN_SEL 0x0000003F #define GPIO_FUNC32_IN_SEL_M ((GPIO_FUNC32_IN_SEL_V)<<(GPIO_FUNC32_IN_SEL_S)) #define GPIO_FUNC32_IN_SEL_V 0x3F #define GPIO_FUNC32_IN_SEL_S 0 @@ -3088,18 +3348,21 @@ #define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01b4) /* GPIO_SIG33_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG33_IN_SEL (BIT(7)) +#define GPIO_SIG33_IN_SEL (BIT(7)) #define GPIO_SIG33_IN_SEL_M (BIT(7)) #define GPIO_SIG33_IN_SEL_V 0x1 #define GPIO_SIG33_IN_SEL_S 7 /* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC33_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC33_IN_INV_SEL (BIT(6)) #define GPIO_FUNC33_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC33_IN_INV_SEL_V 0x1 #define GPIO_FUNC33_IN_INV_SEL_S 6 @@ -3107,7 +3370,7 @@ /* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC33_IN_SEL 0x0000003F +#define GPIO_FUNC33_IN_SEL 0x0000003F #define GPIO_FUNC33_IN_SEL_M ((GPIO_FUNC33_IN_SEL_V)<<(GPIO_FUNC33_IN_SEL_S)) #define GPIO_FUNC33_IN_SEL_V 0x3F #define GPIO_FUNC33_IN_SEL_S 0 @@ -3115,18 +3378,21 @@ #define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01b8) /* GPIO_SIG34_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG34_IN_SEL (BIT(7)) +#define GPIO_SIG34_IN_SEL (BIT(7)) #define GPIO_SIG34_IN_SEL_M (BIT(7)) #define GPIO_SIG34_IN_SEL_V 0x1 #define GPIO_SIG34_IN_SEL_S 7 /* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC34_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC34_IN_INV_SEL (BIT(6)) #define GPIO_FUNC34_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC34_IN_INV_SEL_V 0x1 #define GPIO_FUNC34_IN_INV_SEL_S 6 @@ -3134,7 +3400,7 @@ /* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC34_IN_SEL 0x0000003F +#define GPIO_FUNC34_IN_SEL 0x0000003F #define GPIO_FUNC34_IN_SEL_M ((GPIO_FUNC34_IN_SEL_V)<<(GPIO_FUNC34_IN_SEL_S)) #define GPIO_FUNC34_IN_SEL_V 0x3F #define GPIO_FUNC34_IN_SEL_S 0 @@ -3142,18 +3408,21 @@ #define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01bc) /* GPIO_SIG35_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG35_IN_SEL (BIT(7)) +#define GPIO_SIG35_IN_SEL (BIT(7)) #define GPIO_SIG35_IN_SEL_M (BIT(7)) #define GPIO_SIG35_IN_SEL_V 0x1 #define GPIO_SIG35_IN_SEL_S 7 /* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC35_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC35_IN_INV_SEL (BIT(6)) #define GPIO_FUNC35_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC35_IN_INV_SEL_V 0x1 #define GPIO_FUNC35_IN_INV_SEL_S 6 @@ -3161,7 +3430,7 @@ /* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC35_IN_SEL 0x0000003F +#define GPIO_FUNC35_IN_SEL 0x0000003F #define GPIO_FUNC35_IN_SEL_M ((GPIO_FUNC35_IN_SEL_V)<<(GPIO_FUNC35_IN_SEL_S)) #define GPIO_FUNC35_IN_SEL_V 0x3F #define GPIO_FUNC35_IN_SEL_S 0 @@ -3169,18 +3438,21 @@ #define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01c0) /* GPIO_SIG36_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG36_IN_SEL (BIT(7)) +#define GPIO_SIG36_IN_SEL (BIT(7)) #define GPIO_SIG36_IN_SEL_M (BIT(7)) #define GPIO_SIG36_IN_SEL_V 0x1 #define GPIO_SIG36_IN_SEL_S 7 /* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC36_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC36_IN_INV_SEL (BIT(6)) #define GPIO_FUNC36_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC36_IN_INV_SEL_V 0x1 #define GPIO_FUNC36_IN_INV_SEL_S 6 @@ -3188,7 +3460,7 @@ /* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC36_IN_SEL 0x0000003F +#define GPIO_FUNC36_IN_SEL 0x0000003F #define GPIO_FUNC36_IN_SEL_M ((GPIO_FUNC36_IN_SEL_V)<<(GPIO_FUNC36_IN_SEL_S)) #define GPIO_FUNC36_IN_SEL_V 0x3F #define GPIO_FUNC36_IN_SEL_S 0 @@ -3196,18 +3468,21 @@ #define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01c4) /* GPIO_SIG37_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG37_IN_SEL (BIT(7)) +#define GPIO_SIG37_IN_SEL (BIT(7)) #define GPIO_SIG37_IN_SEL_M (BIT(7)) #define GPIO_SIG37_IN_SEL_V 0x1 #define GPIO_SIG37_IN_SEL_S 7 /* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC37_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC37_IN_INV_SEL (BIT(6)) #define GPIO_FUNC37_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC37_IN_INV_SEL_V 0x1 #define GPIO_FUNC37_IN_INV_SEL_S 6 @@ -3215,7 +3490,7 @@ /* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC37_IN_SEL 0x0000003F +#define GPIO_FUNC37_IN_SEL 0x0000003F #define GPIO_FUNC37_IN_SEL_M ((GPIO_FUNC37_IN_SEL_V)<<(GPIO_FUNC37_IN_SEL_S)) #define GPIO_FUNC37_IN_SEL_V 0x3F #define GPIO_FUNC37_IN_SEL_S 0 @@ -3223,18 +3498,21 @@ #define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01c8) /* GPIO_SIG38_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG38_IN_SEL (BIT(7)) +#define GPIO_SIG38_IN_SEL (BIT(7)) #define GPIO_SIG38_IN_SEL_M (BIT(7)) #define GPIO_SIG38_IN_SEL_V 0x1 #define GPIO_SIG38_IN_SEL_S 7 /* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC38_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC38_IN_INV_SEL (BIT(6)) #define GPIO_FUNC38_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC38_IN_INV_SEL_V 0x1 #define GPIO_FUNC38_IN_INV_SEL_S 6 @@ -3242,7 +3520,7 @@ /* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC38_IN_SEL 0x0000003F +#define GPIO_FUNC38_IN_SEL 0x0000003F #define GPIO_FUNC38_IN_SEL_M ((GPIO_FUNC38_IN_SEL_V)<<(GPIO_FUNC38_IN_SEL_S)) #define GPIO_FUNC38_IN_SEL_V 0x3F #define GPIO_FUNC38_IN_SEL_S 0 @@ -3250,18 +3528,21 @@ #define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01cc) /* GPIO_SIG39_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG39_IN_SEL (BIT(7)) +#define GPIO_SIG39_IN_SEL (BIT(7)) #define GPIO_SIG39_IN_SEL_M (BIT(7)) #define GPIO_SIG39_IN_SEL_V 0x1 #define GPIO_SIG39_IN_SEL_S 7 /* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC39_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC39_IN_INV_SEL (BIT(6)) #define GPIO_FUNC39_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC39_IN_INV_SEL_V 0x1 #define GPIO_FUNC39_IN_INV_SEL_S 6 @@ -3269,7 +3550,7 @@ /* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC39_IN_SEL 0x0000003F +#define GPIO_FUNC39_IN_SEL 0x0000003F #define GPIO_FUNC39_IN_SEL_M ((GPIO_FUNC39_IN_SEL_V)<<(GPIO_FUNC39_IN_SEL_S)) #define GPIO_FUNC39_IN_SEL_V 0x3F #define GPIO_FUNC39_IN_SEL_S 0 @@ -3277,18 +3558,21 @@ #define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01d0) /* GPIO_SIG40_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG40_IN_SEL (BIT(7)) +#define GPIO_SIG40_IN_SEL (BIT(7)) #define GPIO_SIG40_IN_SEL_M (BIT(7)) #define GPIO_SIG40_IN_SEL_V 0x1 #define GPIO_SIG40_IN_SEL_S 7 /* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC40_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC40_IN_INV_SEL (BIT(6)) #define GPIO_FUNC40_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC40_IN_INV_SEL_V 0x1 #define GPIO_FUNC40_IN_INV_SEL_S 6 @@ -3296,7 +3580,7 @@ /* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC40_IN_SEL 0x0000003F +#define GPIO_FUNC40_IN_SEL 0x0000003F #define GPIO_FUNC40_IN_SEL_M ((GPIO_FUNC40_IN_SEL_V)<<(GPIO_FUNC40_IN_SEL_S)) #define GPIO_FUNC40_IN_SEL_V 0x3F #define GPIO_FUNC40_IN_SEL_S 0 @@ -3304,18 +3588,21 @@ #define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01d4) /* GPIO_SIG41_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG41_IN_SEL (BIT(7)) +#define GPIO_SIG41_IN_SEL (BIT(7)) #define GPIO_SIG41_IN_SEL_M (BIT(7)) #define GPIO_SIG41_IN_SEL_V 0x1 #define GPIO_SIG41_IN_SEL_S 7 /* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC41_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC41_IN_INV_SEL (BIT(6)) #define GPIO_FUNC41_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC41_IN_INV_SEL_V 0x1 #define GPIO_FUNC41_IN_INV_SEL_S 6 @@ -3323,7 +3610,7 @@ /* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC41_IN_SEL 0x0000003F +#define GPIO_FUNC41_IN_SEL 0x0000003F #define GPIO_FUNC41_IN_SEL_M ((GPIO_FUNC41_IN_SEL_V)<<(GPIO_FUNC41_IN_SEL_S)) #define GPIO_FUNC41_IN_SEL_V 0x3F #define GPIO_FUNC41_IN_SEL_S 0 @@ -3331,18 +3618,21 @@ #define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01d8) /* GPIO_SIG42_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG42_IN_SEL (BIT(7)) +#define GPIO_SIG42_IN_SEL (BIT(7)) #define GPIO_SIG42_IN_SEL_M (BIT(7)) #define GPIO_SIG42_IN_SEL_V 0x1 #define GPIO_SIG42_IN_SEL_S 7 /* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC42_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC42_IN_INV_SEL (BIT(6)) #define GPIO_FUNC42_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC42_IN_INV_SEL_V 0x1 #define GPIO_FUNC42_IN_INV_SEL_S 6 @@ -3350,7 +3640,7 @@ /* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC42_IN_SEL 0x0000003F +#define GPIO_FUNC42_IN_SEL 0x0000003F #define GPIO_FUNC42_IN_SEL_M ((GPIO_FUNC42_IN_SEL_V)<<(GPIO_FUNC42_IN_SEL_S)) #define GPIO_FUNC42_IN_SEL_V 0x3F #define GPIO_FUNC42_IN_SEL_S 0 @@ -3358,18 +3648,21 @@ #define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01dc) /* GPIO_SIG43_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG43_IN_SEL (BIT(7)) +#define GPIO_SIG43_IN_SEL (BIT(7)) #define GPIO_SIG43_IN_SEL_M (BIT(7)) #define GPIO_SIG43_IN_SEL_V 0x1 #define GPIO_SIG43_IN_SEL_S 7 /* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC43_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC43_IN_INV_SEL (BIT(6)) #define GPIO_FUNC43_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC43_IN_INV_SEL_V 0x1 #define GPIO_FUNC43_IN_INV_SEL_S 6 @@ -3377,7 +3670,7 @@ /* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC43_IN_SEL 0x0000003F +#define GPIO_FUNC43_IN_SEL 0x0000003F #define GPIO_FUNC43_IN_SEL_M ((GPIO_FUNC43_IN_SEL_V)<<(GPIO_FUNC43_IN_SEL_S)) #define GPIO_FUNC43_IN_SEL_V 0x3F #define GPIO_FUNC43_IN_SEL_S 0 @@ -3385,18 +3678,21 @@ #define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01e0) /* GPIO_SIG44_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG44_IN_SEL (BIT(7)) +#define GPIO_SIG44_IN_SEL (BIT(7)) #define GPIO_SIG44_IN_SEL_M (BIT(7)) #define GPIO_SIG44_IN_SEL_V 0x1 #define GPIO_SIG44_IN_SEL_S 7 /* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC44_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC44_IN_INV_SEL (BIT(6)) #define GPIO_FUNC44_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC44_IN_INV_SEL_V 0x1 #define GPIO_FUNC44_IN_INV_SEL_S 6 @@ -3404,7 +3700,7 @@ /* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC44_IN_SEL 0x0000003F +#define GPIO_FUNC44_IN_SEL 0x0000003F #define GPIO_FUNC44_IN_SEL_M ((GPIO_FUNC44_IN_SEL_V)<<(GPIO_FUNC44_IN_SEL_S)) #define GPIO_FUNC44_IN_SEL_V 0x3F #define GPIO_FUNC44_IN_SEL_S 0 @@ -3412,18 +3708,21 @@ #define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01e4) /* GPIO_SIG45_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG45_IN_SEL (BIT(7)) +#define GPIO_SIG45_IN_SEL (BIT(7)) #define GPIO_SIG45_IN_SEL_M (BIT(7)) #define GPIO_SIG45_IN_SEL_V 0x1 #define GPIO_SIG45_IN_SEL_S 7 /* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC45_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC45_IN_INV_SEL (BIT(6)) #define GPIO_FUNC45_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC45_IN_INV_SEL_V 0x1 #define GPIO_FUNC45_IN_INV_SEL_S 6 @@ -3431,7 +3730,7 @@ /* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC45_IN_SEL 0x0000003F +#define GPIO_FUNC45_IN_SEL 0x0000003F #define GPIO_FUNC45_IN_SEL_M ((GPIO_FUNC45_IN_SEL_V)<<(GPIO_FUNC45_IN_SEL_S)) #define GPIO_FUNC45_IN_SEL_V 0x3F #define GPIO_FUNC45_IN_SEL_S 0 @@ -3439,18 +3738,21 @@ #define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01e8) /* GPIO_SIG46_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG46_IN_SEL (BIT(7)) +#define GPIO_SIG46_IN_SEL (BIT(7)) #define GPIO_SIG46_IN_SEL_M (BIT(7)) #define GPIO_SIG46_IN_SEL_V 0x1 #define GPIO_SIG46_IN_SEL_S 7 /* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC46_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC46_IN_INV_SEL (BIT(6)) #define GPIO_FUNC46_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC46_IN_INV_SEL_V 0x1 #define GPIO_FUNC46_IN_INV_SEL_S 6 @@ -3458,7 +3760,7 @@ /* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC46_IN_SEL 0x0000003F +#define GPIO_FUNC46_IN_SEL 0x0000003F #define GPIO_FUNC46_IN_SEL_M ((GPIO_FUNC46_IN_SEL_V)<<(GPIO_FUNC46_IN_SEL_S)) #define GPIO_FUNC46_IN_SEL_V 0x3F #define GPIO_FUNC46_IN_SEL_S 0 @@ -3466,18 +3768,21 @@ #define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01ec) /* GPIO_SIG47_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG47_IN_SEL (BIT(7)) +#define GPIO_SIG47_IN_SEL (BIT(7)) #define GPIO_SIG47_IN_SEL_M (BIT(7)) #define GPIO_SIG47_IN_SEL_V 0x1 #define GPIO_SIG47_IN_SEL_S 7 /* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC47_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC47_IN_INV_SEL (BIT(6)) #define GPIO_FUNC47_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC47_IN_INV_SEL_V 0x1 #define GPIO_FUNC47_IN_INV_SEL_S 6 @@ -3485,7 +3790,7 @@ /* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC47_IN_SEL 0x0000003F +#define GPIO_FUNC47_IN_SEL 0x0000003F #define GPIO_FUNC47_IN_SEL_M ((GPIO_FUNC47_IN_SEL_V)<<(GPIO_FUNC47_IN_SEL_S)) #define GPIO_FUNC47_IN_SEL_V 0x3F #define GPIO_FUNC47_IN_SEL_S 0 @@ -3493,18 +3798,21 @@ #define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01f0) /* GPIO_SIG48_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG48_IN_SEL (BIT(7)) +#define GPIO_SIG48_IN_SEL (BIT(7)) #define GPIO_SIG48_IN_SEL_M (BIT(7)) #define GPIO_SIG48_IN_SEL_V 0x1 #define GPIO_SIG48_IN_SEL_S 7 /* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC48_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC48_IN_INV_SEL (BIT(6)) #define GPIO_FUNC48_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC48_IN_INV_SEL_V 0x1 #define GPIO_FUNC48_IN_INV_SEL_S 6 @@ -3512,7 +3820,7 @@ /* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC48_IN_SEL 0x0000003F +#define GPIO_FUNC48_IN_SEL 0x0000003F #define GPIO_FUNC48_IN_SEL_M ((GPIO_FUNC48_IN_SEL_V)<<(GPIO_FUNC48_IN_SEL_S)) #define GPIO_FUNC48_IN_SEL_V 0x3F #define GPIO_FUNC48_IN_SEL_S 0 @@ -3520,18 +3828,22 @@ #define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01f4) /* GPIO_SIG49_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG49_IN_SEL (BIT(7)) +#define GPIO_SIG49_IN_SEL (BIT(7)) #define GPIO_SIG49_IN_SEL_M (BIT(7)) #define GPIO_SIG49_IN_SEL_V 0x1 #define GPIO_SIG49_IN_SEL_S 7 /* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. +. + */ -#define GPIO_FUNC49_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC49_IN_INV_SEL (BIT(6)) #define GPIO_FUNC49_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC49_IN_INV_SEL_V 0x1 #define GPIO_FUNC49_IN_INV_SEL_S 6 @@ -3539,7 +3851,7 @@ /* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC49_IN_SEL 0x0000003F +#define GPIO_FUNC49_IN_SEL 0x0000003F #define GPIO_FUNC49_IN_SEL_M ((GPIO_FUNC49_IN_SEL_V)<<(GPIO_FUNC49_IN_SEL_S)) #define GPIO_FUNC49_IN_SEL_V 0x3F #define GPIO_FUNC49_IN_SEL_S 0 @@ -3547,18 +3859,21 @@ #define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01f8) /* GPIO_SIG50_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG50_IN_SEL (BIT(7)) +#define GPIO_SIG50_IN_SEL (BIT(7)) #define GPIO_SIG50_IN_SEL_M (BIT(7)) #define GPIO_SIG50_IN_SEL_V 0x1 #define GPIO_SIG50_IN_SEL_S 7 /* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC50_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC50_IN_INV_SEL (BIT(6)) #define GPIO_FUNC50_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC50_IN_INV_SEL_V 0x1 #define GPIO_FUNC50_IN_INV_SEL_S 6 @@ -3566,7 +3881,7 @@ /* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC50_IN_SEL 0x0000003F +#define GPIO_FUNC50_IN_SEL 0x0000003F #define GPIO_FUNC50_IN_SEL_M ((GPIO_FUNC50_IN_SEL_V)<<(GPIO_FUNC50_IN_SEL_S)) #define GPIO_FUNC50_IN_SEL_V 0x3F #define GPIO_FUNC50_IN_SEL_S 0 @@ -3574,18 +3889,22 @@ #define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x01fc) /* GPIO_SIG51_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG51_IN_SEL (BIT(7)) +#define GPIO_SIG51_IN_SEL (BIT(7)) #define GPIO_SIG51_IN_SEL_M (BIT(7)) #define GPIO_SIG51_IN_SEL_V 0x1 #define GPIO_SIG51_IN_SEL_S 7 /* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. +. + */ -#define GPIO_FUNC51_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC51_IN_INV_SEL (BIT(6)) #define GPIO_FUNC51_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC51_IN_INV_SEL_V 0x1 #define GPIO_FUNC51_IN_INV_SEL_S 6 @@ -3593,7 +3912,7 @@ /* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC51_IN_SEL 0x0000003F +#define GPIO_FUNC51_IN_SEL 0x0000003F #define GPIO_FUNC51_IN_SEL_M ((GPIO_FUNC51_IN_SEL_V)<<(GPIO_FUNC51_IN_SEL_S)) #define GPIO_FUNC51_IN_SEL_V 0x3F #define GPIO_FUNC51_IN_SEL_S 0 @@ -3601,18 +3920,21 @@ #define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0200) /* GPIO_SIG52_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG52_IN_SEL (BIT(7)) +#define GPIO_SIG52_IN_SEL (BIT(7)) #define GPIO_SIG52_IN_SEL_M (BIT(7)) #define GPIO_SIG52_IN_SEL_V 0x1 #define GPIO_SIG52_IN_SEL_S 7 /* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC52_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC52_IN_INV_SEL (BIT(6)) #define GPIO_FUNC52_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC52_IN_INV_SEL_V 0x1 #define GPIO_FUNC52_IN_INV_SEL_S 6 @@ -3620,7 +3942,7 @@ /* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC52_IN_SEL 0x0000003F +#define GPIO_FUNC52_IN_SEL 0x0000003F #define GPIO_FUNC52_IN_SEL_M ((GPIO_FUNC52_IN_SEL_V)<<(GPIO_FUNC52_IN_SEL_S)) #define GPIO_FUNC52_IN_SEL_V 0x3F #define GPIO_FUNC52_IN_SEL_S 0 @@ -3628,18 +3950,21 @@ #define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0204) /* GPIO_SIG53_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG53_IN_SEL (BIT(7)) +#define GPIO_SIG53_IN_SEL (BIT(7)) #define GPIO_SIG53_IN_SEL_M (BIT(7)) #define GPIO_SIG53_IN_SEL_V 0x1 #define GPIO_SIG53_IN_SEL_S 7 /* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC53_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC53_IN_INV_SEL (BIT(6)) #define GPIO_FUNC53_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC53_IN_INV_SEL_V 0x1 #define GPIO_FUNC53_IN_INV_SEL_S 6 @@ -3647,7 +3972,7 @@ /* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC53_IN_SEL 0x0000003F +#define GPIO_FUNC53_IN_SEL 0x0000003F #define GPIO_FUNC53_IN_SEL_M ((GPIO_FUNC53_IN_SEL_V)<<(GPIO_FUNC53_IN_SEL_S)) #define GPIO_FUNC53_IN_SEL_V 0x3F #define GPIO_FUNC53_IN_SEL_S 0 @@ -3655,18 +3980,21 @@ #define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0208) /* GPIO_SIG54_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG54_IN_SEL (BIT(7)) +#define GPIO_SIG54_IN_SEL (BIT(7)) #define GPIO_SIG54_IN_SEL_M (BIT(7)) #define GPIO_SIG54_IN_SEL_V 0x1 #define GPIO_SIG54_IN_SEL_S 7 /* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC54_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC54_IN_INV_SEL (BIT(6)) #define GPIO_FUNC54_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC54_IN_INV_SEL_V 0x1 #define GPIO_FUNC54_IN_INV_SEL_S 6 @@ -3674,7 +4002,7 @@ /* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC54_IN_SEL 0x0000003F +#define GPIO_FUNC54_IN_SEL 0x0000003F #define GPIO_FUNC54_IN_SEL_M ((GPIO_FUNC54_IN_SEL_V)<<(GPIO_FUNC54_IN_SEL_S)) #define GPIO_FUNC54_IN_SEL_V 0x3F #define GPIO_FUNC54_IN_SEL_S 0 @@ -3682,18 +4010,21 @@ #define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x020c) /* GPIO_SIG55_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG55_IN_SEL (BIT(7)) +#define GPIO_SIG55_IN_SEL (BIT(7)) #define GPIO_SIG55_IN_SEL_M (BIT(7)) #define GPIO_SIG55_IN_SEL_V 0x1 #define GPIO_SIG55_IN_SEL_S 7 /* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC55_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC55_IN_INV_SEL (BIT(6)) #define GPIO_FUNC55_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC55_IN_INV_SEL_V 0x1 #define GPIO_FUNC55_IN_INV_SEL_S 6 @@ -3701,7 +4032,7 @@ /* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC55_IN_SEL 0x0000003F +#define GPIO_FUNC55_IN_SEL 0x0000003F #define GPIO_FUNC55_IN_SEL_M ((GPIO_FUNC55_IN_SEL_V)<<(GPIO_FUNC55_IN_SEL_S)) #define GPIO_FUNC55_IN_SEL_V 0x3F #define GPIO_FUNC55_IN_SEL_S 0 @@ -3709,18 +4040,21 @@ #define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0210) /* GPIO_SIG56_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG56_IN_SEL (BIT(7)) +#define GPIO_SIG56_IN_SEL (BIT(7)) #define GPIO_SIG56_IN_SEL_M (BIT(7)) #define GPIO_SIG56_IN_SEL_V 0x1 #define GPIO_SIG56_IN_SEL_S 7 /* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC56_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC56_IN_INV_SEL (BIT(6)) #define GPIO_FUNC56_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC56_IN_INV_SEL_V 0x1 #define GPIO_FUNC56_IN_INV_SEL_S 6 @@ -3728,7 +4062,7 @@ /* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC56_IN_SEL 0x0000003F +#define GPIO_FUNC56_IN_SEL 0x0000003F #define GPIO_FUNC56_IN_SEL_M ((GPIO_FUNC56_IN_SEL_V)<<(GPIO_FUNC56_IN_SEL_S)) #define GPIO_FUNC56_IN_SEL_V 0x3F #define GPIO_FUNC56_IN_SEL_S 0 @@ -3736,18 +4070,21 @@ #define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0214) /* GPIO_SIG57_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG57_IN_SEL (BIT(7)) +#define GPIO_SIG57_IN_SEL (BIT(7)) #define GPIO_SIG57_IN_SEL_M (BIT(7)) #define GPIO_SIG57_IN_SEL_V 0x1 #define GPIO_SIG57_IN_SEL_S 7 /* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC57_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC57_IN_INV_SEL (BIT(6)) #define GPIO_FUNC57_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC57_IN_INV_SEL_V 0x1 #define GPIO_FUNC57_IN_INV_SEL_S 6 @@ -3755,7 +4092,7 @@ /* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC57_IN_SEL 0x0000003F +#define GPIO_FUNC57_IN_SEL 0x0000003F #define GPIO_FUNC57_IN_SEL_M ((GPIO_FUNC57_IN_SEL_V)<<(GPIO_FUNC57_IN_SEL_S)) #define GPIO_FUNC57_IN_SEL_V 0x3F #define GPIO_FUNC57_IN_SEL_S 0 @@ -3763,18 +4100,21 @@ #define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0218) /* GPIO_SIG58_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG58_IN_SEL (BIT(7)) +#define GPIO_SIG58_IN_SEL (BIT(7)) #define GPIO_SIG58_IN_SEL_M (BIT(7)) #define GPIO_SIG58_IN_SEL_V 0x1 #define GPIO_SIG58_IN_SEL_S 7 /* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC58_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC58_IN_INV_SEL (BIT(6)) #define GPIO_FUNC58_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC58_IN_INV_SEL_V 0x1 #define GPIO_FUNC58_IN_INV_SEL_S 6 @@ -3782,7 +4122,7 @@ /* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC58_IN_SEL 0x0000003F +#define GPIO_FUNC58_IN_SEL 0x0000003F #define GPIO_FUNC58_IN_SEL_M ((GPIO_FUNC58_IN_SEL_V)<<(GPIO_FUNC58_IN_SEL_S)) #define GPIO_FUNC58_IN_SEL_V 0x3F #define GPIO_FUNC58_IN_SEL_S 0 @@ -3790,18 +4130,21 @@ #define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x021c) /* GPIO_SIG59_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG59_IN_SEL (BIT(7)) +#define GPIO_SIG59_IN_SEL (BIT(7)) #define GPIO_SIG59_IN_SEL_M (BIT(7)) #define GPIO_SIG59_IN_SEL_V 0x1 #define GPIO_SIG59_IN_SEL_S 7 /* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC59_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC59_IN_INV_SEL (BIT(6)) #define GPIO_FUNC59_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC59_IN_INV_SEL_V 0x1 #define GPIO_FUNC59_IN_INV_SEL_S 6 @@ -3809,7 +4152,7 @@ /* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC59_IN_SEL 0x0000003F +#define GPIO_FUNC59_IN_SEL 0x0000003F #define GPIO_FUNC59_IN_SEL_M ((GPIO_FUNC59_IN_SEL_V)<<(GPIO_FUNC59_IN_SEL_S)) #define GPIO_FUNC59_IN_SEL_V 0x3F #define GPIO_FUNC59_IN_SEL_S 0 @@ -3817,18 +4160,21 @@ #define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0220) /* GPIO_SIG60_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG60_IN_SEL (BIT(7)) +#define GPIO_SIG60_IN_SEL (BIT(7)) #define GPIO_SIG60_IN_SEL_M (BIT(7)) #define GPIO_SIG60_IN_SEL_V 0x1 #define GPIO_SIG60_IN_SEL_S 7 /* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC60_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC60_IN_INV_SEL (BIT(6)) #define GPIO_FUNC60_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC60_IN_INV_SEL_V 0x1 #define GPIO_FUNC60_IN_INV_SEL_S 6 @@ -3836,7 +4182,7 @@ /* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC60_IN_SEL 0x0000003F +#define GPIO_FUNC60_IN_SEL 0x0000003F #define GPIO_FUNC60_IN_SEL_M ((GPIO_FUNC60_IN_SEL_V)<<(GPIO_FUNC60_IN_SEL_S)) #define GPIO_FUNC60_IN_SEL_V 0x3F #define GPIO_FUNC60_IN_SEL_S 0 @@ -3844,18 +4190,21 @@ #define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0224) /* GPIO_SIG61_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG61_IN_SEL (BIT(7)) +#define GPIO_SIG61_IN_SEL (BIT(7)) #define GPIO_SIG61_IN_SEL_M (BIT(7)) #define GPIO_SIG61_IN_SEL_V 0x1 #define GPIO_SIG61_IN_SEL_S 7 /* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC61_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC61_IN_INV_SEL (BIT(6)) #define GPIO_FUNC61_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC61_IN_INV_SEL_V 0x1 #define GPIO_FUNC61_IN_INV_SEL_S 6 @@ -3863,7 +4212,7 @@ /* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC61_IN_SEL 0x0000003F +#define GPIO_FUNC61_IN_SEL 0x0000003F #define GPIO_FUNC61_IN_SEL_M ((GPIO_FUNC61_IN_SEL_V)<<(GPIO_FUNC61_IN_SEL_S)) #define GPIO_FUNC61_IN_SEL_V 0x3F #define GPIO_FUNC61_IN_SEL_S 0 @@ -3871,18 +4220,21 @@ #define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0228) /* GPIO_SIG62_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG62_IN_SEL (BIT(7)) +#define GPIO_SIG62_IN_SEL (BIT(7)) #define GPIO_SIG62_IN_SEL_M (BIT(7)) #define GPIO_SIG62_IN_SEL_V 0x1 #define GPIO_SIG62_IN_SEL_S 7 /* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC62_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC62_IN_INV_SEL (BIT(6)) #define GPIO_FUNC62_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC62_IN_INV_SEL_V 0x1 #define GPIO_FUNC62_IN_INV_SEL_S 6 @@ -3890,7 +4242,7 @@ /* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC62_IN_SEL 0x0000003F +#define GPIO_FUNC62_IN_SEL 0x0000003F #define GPIO_FUNC62_IN_SEL_M ((GPIO_FUNC62_IN_SEL_V)<<(GPIO_FUNC62_IN_SEL_S)) #define GPIO_FUNC62_IN_SEL_V 0x3F #define GPIO_FUNC62_IN_SEL_S 0 @@ -3898,18 +4250,21 @@ #define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x022c) /* GPIO_SIG63_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG63_IN_SEL (BIT(7)) +#define GPIO_SIG63_IN_SEL (BIT(7)) #define GPIO_SIG63_IN_SEL_M (BIT(7)) #define GPIO_SIG63_IN_SEL_V 0x1 #define GPIO_SIG63_IN_SEL_S 7 /* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC63_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC63_IN_INV_SEL (BIT(6)) #define GPIO_FUNC63_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC63_IN_INV_SEL_V 0x1 #define GPIO_FUNC63_IN_INV_SEL_S 6 @@ -3917,7 +4272,7 @@ /* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC63_IN_SEL 0x0000003F +#define GPIO_FUNC63_IN_SEL 0x0000003F #define GPIO_FUNC63_IN_SEL_M ((GPIO_FUNC63_IN_SEL_V)<<(GPIO_FUNC63_IN_SEL_S)) #define GPIO_FUNC63_IN_SEL_V 0x3F #define GPIO_FUNC63_IN_SEL_S 0 @@ -3925,18 +4280,21 @@ #define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0230) /* GPIO_SIG64_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG64_IN_SEL (BIT(7)) +#define GPIO_SIG64_IN_SEL (BIT(7)) #define GPIO_SIG64_IN_SEL_M (BIT(7)) #define GPIO_SIG64_IN_SEL_V 0x1 #define GPIO_SIG64_IN_SEL_S 7 /* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC64_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC64_IN_INV_SEL (BIT(6)) #define GPIO_FUNC64_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC64_IN_INV_SEL_V 0x1 #define GPIO_FUNC64_IN_INV_SEL_S 6 @@ -3944,7 +4302,7 @@ /* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC64_IN_SEL 0x0000003F +#define GPIO_FUNC64_IN_SEL 0x0000003F #define GPIO_FUNC64_IN_SEL_M ((GPIO_FUNC64_IN_SEL_V)<<(GPIO_FUNC64_IN_SEL_S)) #define GPIO_FUNC64_IN_SEL_V 0x3F #define GPIO_FUNC64_IN_SEL_S 0 @@ -3952,18 +4310,21 @@ #define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0234) /* GPIO_SIG65_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG65_IN_SEL (BIT(7)) +#define GPIO_SIG65_IN_SEL (BIT(7)) #define GPIO_SIG65_IN_SEL_M (BIT(7)) #define GPIO_SIG65_IN_SEL_V 0x1 #define GPIO_SIG65_IN_SEL_S 7 /* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC65_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC65_IN_INV_SEL (BIT(6)) #define GPIO_FUNC65_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC65_IN_INV_SEL_V 0x1 #define GPIO_FUNC65_IN_INV_SEL_S 6 @@ -3971,7 +4332,7 @@ /* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC65_IN_SEL 0x0000003F +#define GPIO_FUNC65_IN_SEL 0x0000003F #define GPIO_FUNC65_IN_SEL_M ((GPIO_FUNC65_IN_SEL_V)<<(GPIO_FUNC65_IN_SEL_S)) #define GPIO_FUNC65_IN_SEL_V 0x3F #define GPIO_FUNC65_IN_SEL_S 0 @@ -3979,18 +4340,21 @@ #define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0238) /* GPIO_SIG66_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG66_IN_SEL (BIT(7)) +#define GPIO_SIG66_IN_SEL (BIT(7)) #define GPIO_SIG66_IN_SEL_M (BIT(7)) #define GPIO_SIG66_IN_SEL_V 0x1 #define GPIO_SIG66_IN_SEL_S 7 /* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC66_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC66_IN_INV_SEL (BIT(6)) #define GPIO_FUNC66_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC66_IN_INV_SEL_V 0x1 #define GPIO_FUNC66_IN_INV_SEL_S 6 @@ -3998,7 +4362,7 @@ /* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC66_IN_SEL 0x0000003F +#define GPIO_FUNC66_IN_SEL 0x0000003F #define GPIO_FUNC66_IN_SEL_M ((GPIO_FUNC66_IN_SEL_V)<<(GPIO_FUNC66_IN_SEL_S)) #define GPIO_FUNC66_IN_SEL_V 0x3F #define GPIO_FUNC66_IN_SEL_S 0 @@ -4006,18 +4370,21 @@ #define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x023c) /* GPIO_SIG67_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG67_IN_SEL (BIT(7)) +#define GPIO_SIG67_IN_SEL (BIT(7)) #define GPIO_SIG67_IN_SEL_M (BIT(7)) #define GPIO_SIG67_IN_SEL_V 0x1 #define GPIO_SIG67_IN_SEL_S 7 /* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC67_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC67_IN_INV_SEL (BIT(6)) #define GPIO_FUNC67_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC67_IN_INV_SEL_V 0x1 #define GPIO_FUNC67_IN_INV_SEL_S 6 @@ -4025,7 +4392,7 @@ /* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC67_IN_SEL 0x0000003F +#define GPIO_FUNC67_IN_SEL 0x0000003F #define GPIO_FUNC67_IN_SEL_M ((GPIO_FUNC67_IN_SEL_V)<<(GPIO_FUNC67_IN_SEL_S)) #define GPIO_FUNC67_IN_SEL_V 0x3F #define GPIO_FUNC67_IN_SEL_S 0 @@ -4033,18 +4400,21 @@ #define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0240) /* GPIO_SIG68_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG68_IN_SEL (BIT(7)) +#define GPIO_SIG68_IN_SEL (BIT(7)) #define GPIO_SIG68_IN_SEL_M (BIT(7)) #define GPIO_SIG68_IN_SEL_V 0x1 #define GPIO_SIG68_IN_SEL_S 7 /* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC68_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC68_IN_INV_SEL (BIT(6)) #define GPIO_FUNC68_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC68_IN_INV_SEL_V 0x1 #define GPIO_FUNC68_IN_INV_SEL_S 6 @@ -4052,7 +4422,7 @@ /* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC68_IN_SEL 0x0000003F +#define GPIO_FUNC68_IN_SEL 0x0000003F #define GPIO_FUNC68_IN_SEL_M ((GPIO_FUNC68_IN_SEL_V)<<(GPIO_FUNC68_IN_SEL_S)) #define GPIO_FUNC68_IN_SEL_V 0x3F #define GPIO_FUNC68_IN_SEL_S 0 @@ -4060,18 +4430,21 @@ #define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0244) /* GPIO_SIG69_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG69_IN_SEL (BIT(7)) +#define GPIO_SIG69_IN_SEL (BIT(7)) #define GPIO_SIG69_IN_SEL_M (BIT(7)) #define GPIO_SIG69_IN_SEL_V 0x1 #define GPIO_SIG69_IN_SEL_S 7 /* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC69_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC69_IN_INV_SEL (BIT(6)) #define GPIO_FUNC69_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC69_IN_INV_SEL_V 0x1 #define GPIO_FUNC69_IN_INV_SEL_S 6 @@ -4079,7 +4452,7 @@ /* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC69_IN_SEL 0x0000003F +#define GPIO_FUNC69_IN_SEL 0x0000003F #define GPIO_FUNC69_IN_SEL_M ((GPIO_FUNC69_IN_SEL_V)<<(GPIO_FUNC69_IN_SEL_S)) #define GPIO_FUNC69_IN_SEL_V 0x3F #define GPIO_FUNC69_IN_SEL_S 0 @@ -4087,18 +4460,21 @@ #define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0248) /* GPIO_SIG70_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG70_IN_SEL (BIT(7)) +#define GPIO_SIG70_IN_SEL (BIT(7)) #define GPIO_SIG70_IN_SEL_M (BIT(7)) #define GPIO_SIG70_IN_SEL_V 0x1 #define GPIO_SIG70_IN_SEL_S 7 /* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC70_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC70_IN_INV_SEL (BIT(6)) #define GPIO_FUNC70_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC70_IN_INV_SEL_V 0x1 #define GPIO_FUNC70_IN_INV_SEL_S 6 @@ -4106,7 +4482,7 @@ /* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC70_IN_SEL 0x0000003F +#define GPIO_FUNC70_IN_SEL 0x0000003F #define GPIO_FUNC70_IN_SEL_M ((GPIO_FUNC70_IN_SEL_V)<<(GPIO_FUNC70_IN_SEL_S)) #define GPIO_FUNC70_IN_SEL_V 0x3F #define GPIO_FUNC70_IN_SEL_S 0 @@ -4114,18 +4490,21 @@ #define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x024c) /* GPIO_SIG71_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG71_IN_SEL (BIT(7)) +#define GPIO_SIG71_IN_SEL (BIT(7)) #define GPIO_SIG71_IN_SEL_M (BIT(7)) #define GPIO_SIG71_IN_SEL_V 0x1 #define GPIO_SIG71_IN_SEL_S 7 /* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC71_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC71_IN_INV_SEL (BIT(6)) #define GPIO_FUNC71_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC71_IN_INV_SEL_V 0x1 #define GPIO_FUNC71_IN_INV_SEL_S 6 @@ -4133,7 +4512,7 @@ /* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC71_IN_SEL 0x0000003F +#define GPIO_FUNC71_IN_SEL 0x0000003F #define GPIO_FUNC71_IN_SEL_M ((GPIO_FUNC71_IN_SEL_V)<<(GPIO_FUNC71_IN_SEL_S)) #define GPIO_FUNC71_IN_SEL_V 0x3F #define GPIO_FUNC71_IN_SEL_S 0 @@ -4141,18 +4520,21 @@ #define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0250) /* GPIO_SIG72_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG72_IN_SEL (BIT(7)) +#define GPIO_SIG72_IN_SEL (BIT(7)) #define GPIO_SIG72_IN_SEL_M (BIT(7)) #define GPIO_SIG72_IN_SEL_V 0x1 #define GPIO_SIG72_IN_SEL_S 7 /* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC72_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC72_IN_INV_SEL (BIT(6)) #define GPIO_FUNC72_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC72_IN_INV_SEL_V 0x1 #define GPIO_FUNC72_IN_INV_SEL_S 6 @@ -4160,7 +4542,7 @@ /* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC72_IN_SEL 0x0000003F +#define GPIO_FUNC72_IN_SEL 0x0000003F #define GPIO_FUNC72_IN_SEL_M ((GPIO_FUNC72_IN_SEL_V)<<(GPIO_FUNC72_IN_SEL_S)) #define GPIO_FUNC72_IN_SEL_V 0x3F #define GPIO_FUNC72_IN_SEL_S 0 @@ -4168,18 +4550,21 @@ #define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0254) /* GPIO_SIG73_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG73_IN_SEL (BIT(7)) +#define GPIO_SIG73_IN_SEL (BIT(7)) #define GPIO_SIG73_IN_SEL_M (BIT(7)) #define GPIO_SIG73_IN_SEL_V 0x1 #define GPIO_SIG73_IN_SEL_S 7 /* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC73_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC73_IN_INV_SEL (BIT(6)) #define GPIO_FUNC73_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC73_IN_INV_SEL_V 0x1 #define GPIO_FUNC73_IN_INV_SEL_S 6 @@ -4187,7 +4572,7 @@ /* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC73_IN_SEL 0x0000003F +#define GPIO_FUNC73_IN_SEL 0x0000003F #define GPIO_FUNC73_IN_SEL_M ((GPIO_FUNC73_IN_SEL_V)<<(GPIO_FUNC73_IN_SEL_S)) #define GPIO_FUNC73_IN_SEL_V 0x3F #define GPIO_FUNC73_IN_SEL_S 0 @@ -4195,18 +4580,21 @@ #define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0258) /* GPIO_SIG74_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG74_IN_SEL (BIT(7)) +#define GPIO_SIG74_IN_SEL (BIT(7)) #define GPIO_SIG74_IN_SEL_M (BIT(7)) #define GPIO_SIG74_IN_SEL_V 0x1 #define GPIO_SIG74_IN_SEL_S 7 /* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC74_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC74_IN_INV_SEL (BIT(6)) #define GPIO_FUNC74_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC74_IN_INV_SEL_V 0x1 #define GPIO_FUNC74_IN_INV_SEL_S 6 @@ -4214,7 +4602,7 @@ /* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC74_IN_SEL 0x0000003F +#define GPIO_FUNC74_IN_SEL 0x0000003F #define GPIO_FUNC74_IN_SEL_M ((GPIO_FUNC74_IN_SEL_V)<<(GPIO_FUNC74_IN_SEL_S)) #define GPIO_FUNC74_IN_SEL_V 0x3F #define GPIO_FUNC74_IN_SEL_S 0 @@ -4222,18 +4610,21 @@ #define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x025c) /* GPIO_SIG75_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG75_IN_SEL (BIT(7)) +#define GPIO_SIG75_IN_SEL (BIT(7)) #define GPIO_SIG75_IN_SEL_M (BIT(7)) #define GPIO_SIG75_IN_SEL_V 0x1 #define GPIO_SIG75_IN_SEL_S 7 /* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC75_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC75_IN_INV_SEL (BIT(6)) #define GPIO_FUNC75_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC75_IN_INV_SEL_V 0x1 #define GPIO_FUNC75_IN_INV_SEL_S 6 @@ -4241,7 +4632,7 @@ /* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC75_IN_SEL 0x0000003F +#define GPIO_FUNC75_IN_SEL 0x0000003F #define GPIO_FUNC75_IN_SEL_M ((GPIO_FUNC75_IN_SEL_V)<<(GPIO_FUNC75_IN_SEL_S)) #define GPIO_FUNC75_IN_SEL_V 0x3F #define GPIO_FUNC75_IN_SEL_S 0 @@ -4249,18 +4640,21 @@ #define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0260) /* GPIO_SIG76_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG76_IN_SEL (BIT(7)) +#define GPIO_SIG76_IN_SEL (BIT(7)) #define GPIO_SIG76_IN_SEL_M (BIT(7)) #define GPIO_SIG76_IN_SEL_V 0x1 #define GPIO_SIG76_IN_SEL_S 7 /* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC76_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC76_IN_INV_SEL (BIT(6)) #define GPIO_FUNC76_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC76_IN_INV_SEL_V 0x1 #define GPIO_FUNC76_IN_INV_SEL_S 6 @@ -4268,7 +4662,7 @@ /* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC76_IN_SEL 0x0000003F +#define GPIO_FUNC76_IN_SEL 0x0000003F #define GPIO_FUNC76_IN_SEL_M ((GPIO_FUNC76_IN_SEL_V)<<(GPIO_FUNC76_IN_SEL_S)) #define GPIO_FUNC76_IN_SEL_V 0x3F #define GPIO_FUNC76_IN_SEL_S 0 @@ -4276,18 +4670,21 @@ #define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0264) /* GPIO_SIG77_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG77_IN_SEL (BIT(7)) +#define GPIO_SIG77_IN_SEL (BIT(7)) #define GPIO_SIG77_IN_SEL_M (BIT(7)) #define GPIO_SIG77_IN_SEL_V 0x1 #define GPIO_SIG77_IN_SEL_S 7 /* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC77_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC77_IN_INV_SEL (BIT(6)) #define GPIO_FUNC77_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC77_IN_INV_SEL_V 0x1 #define GPIO_FUNC77_IN_INV_SEL_S 6 @@ -4295,7 +4692,7 @@ /* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC77_IN_SEL 0x0000003F +#define GPIO_FUNC77_IN_SEL 0x0000003F #define GPIO_FUNC77_IN_SEL_M ((GPIO_FUNC77_IN_SEL_V)<<(GPIO_FUNC77_IN_SEL_S)) #define GPIO_FUNC77_IN_SEL_V 0x3F #define GPIO_FUNC77_IN_SEL_S 0 @@ -4303,18 +4700,21 @@ #define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0268) /* GPIO_SIG78_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG78_IN_SEL (BIT(7)) +#define GPIO_SIG78_IN_SEL (BIT(7)) #define GPIO_SIG78_IN_SEL_M (BIT(7)) #define GPIO_SIG78_IN_SEL_V 0x1 #define GPIO_SIG78_IN_SEL_S 7 /* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC78_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC78_IN_INV_SEL (BIT(6)) #define GPIO_FUNC78_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC78_IN_INV_SEL_V 0x1 #define GPIO_FUNC78_IN_INV_SEL_S 6 @@ -4322,7 +4722,7 @@ /* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC78_IN_SEL 0x0000003F +#define GPIO_FUNC78_IN_SEL 0x0000003F #define GPIO_FUNC78_IN_SEL_M ((GPIO_FUNC78_IN_SEL_V)<<(GPIO_FUNC78_IN_SEL_S)) #define GPIO_FUNC78_IN_SEL_V 0x3F #define GPIO_FUNC78_IN_SEL_S 0 @@ -4330,18 +4730,21 @@ #define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x026c) /* GPIO_SIG79_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG79_IN_SEL (BIT(7)) +#define GPIO_SIG79_IN_SEL (BIT(7)) #define GPIO_SIG79_IN_SEL_M (BIT(7)) #define GPIO_SIG79_IN_SEL_V 0x1 #define GPIO_SIG79_IN_SEL_S 7 /* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC79_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC79_IN_INV_SEL (BIT(6)) #define GPIO_FUNC79_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC79_IN_INV_SEL_V 0x1 #define GPIO_FUNC79_IN_INV_SEL_S 6 @@ -4349,7 +4752,7 @@ /* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC79_IN_SEL 0x0000003F +#define GPIO_FUNC79_IN_SEL 0x0000003F #define GPIO_FUNC79_IN_SEL_M ((GPIO_FUNC79_IN_SEL_V)<<(GPIO_FUNC79_IN_SEL_S)) #define GPIO_FUNC79_IN_SEL_V 0x3F #define GPIO_FUNC79_IN_SEL_S 0 @@ -4357,18 +4760,21 @@ #define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0270) /* GPIO_SIG80_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG80_IN_SEL (BIT(7)) +#define GPIO_SIG80_IN_SEL (BIT(7)) #define GPIO_SIG80_IN_SEL_M (BIT(7)) #define GPIO_SIG80_IN_SEL_V 0x1 #define GPIO_SIG80_IN_SEL_S 7 /* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC80_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC80_IN_INV_SEL (BIT(6)) #define GPIO_FUNC80_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC80_IN_INV_SEL_V 0x1 #define GPIO_FUNC80_IN_INV_SEL_S 6 @@ -4376,7 +4782,7 @@ /* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC80_IN_SEL 0x0000003F +#define GPIO_FUNC80_IN_SEL 0x0000003F #define GPIO_FUNC80_IN_SEL_M ((GPIO_FUNC80_IN_SEL_V)<<(GPIO_FUNC80_IN_SEL_S)) #define GPIO_FUNC80_IN_SEL_V 0x3F #define GPIO_FUNC80_IN_SEL_S 0 @@ -4384,18 +4790,21 @@ #define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0274) /* GPIO_SIG81_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG81_IN_SEL (BIT(7)) +#define GPIO_SIG81_IN_SEL (BIT(7)) #define GPIO_SIG81_IN_SEL_M (BIT(7)) #define GPIO_SIG81_IN_SEL_V 0x1 #define GPIO_SIG81_IN_SEL_S 7 /* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC81_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC81_IN_INV_SEL (BIT(6)) #define GPIO_FUNC81_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC81_IN_INV_SEL_V 0x1 #define GPIO_FUNC81_IN_INV_SEL_S 6 @@ -4403,7 +4812,7 @@ /* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC81_IN_SEL 0x0000003F +#define GPIO_FUNC81_IN_SEL 0x0000003F #define GPIO_FUNC81_IN_SEL_M ((GPIO_FUNC81_IN_SEL_V)<<(GPIO_FUNC81_IN_SEL_S)) #define GPIO_FUNC81_IN_SEL_V 0x3F #define GPIO_FUNC81_IN_SEL_S 0 @@ -4411,18 +4820,21 @@ #define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0278) /* GPIO_SIG82_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG82_IN_SEL (BIT(7)) +#define GPIO_SIG82_IN_SEL (BIT(7)) #define GPIO_SIG82_IN_SEL_M (BIT(7)) #define GPIO_SIG82_IN_SEL_V 0x1 #define GPIO_SIG82_IN_SEL_S 7 /* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC82_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC82_IN_INV_SEL (BIT(6)) #define GPIO_FUNC82_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC82_IN_INV_SEL_V 0x1 #define GPIO_FUNC82_IN_INV_SEL_S 6 @@ -4430,7 +4842,7 @@ /* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC82_IN_SEL 0x0000003F +#define GPIO_FUNC82_IN_SEL 0x0000003F #define GPIO_FUNC82_IN_SEL_M ((GPIO_FUNC82_IN_SEL_V)<<(GPIO_FUNC82_IN_SEL_S)) #define GPIO_FUNC82_IN_SEL_V 0x3F #define GPIO_FUNC82_IN_SEL_S 0 @@ -4438,18 +4850,21 @@ #define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x027c) /* GPIO_SIG83_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG83_IN_SEL (BIT(7)) +#define GPIO_SIG83_IN_SEL (BIT(7)) #define GPIO_SIG83_IN_SEL_M (BIT(7)) #define GPIO_SIG83_IN_SEL_V 0x1 #define GPIO_SIG83_IN_SEL_S 7 /* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC83_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC83_IN_INV_SEL (BIT(6)) #define GPIO_FUNC83_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC83_IN_INV_SEL_V 0x1 #define GPIO_FUNC83_IN_INV_SEL_S 6 @@ -4457,7 +4872,7 @@ /* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC83_IN_SEL 0x0000003F +#define GPIO_FUNC83_IN_SEL 0x0000003F #define GPIO_FUNC83_IN_SEL_M ((GPIO_FUNC83_IN_SEL_V)<<(GPIO_FUNC83_IN_SEL_S)) #define GPIO_FUNC83_IN_SEL_V 0x3F #define GPIO_FUNC83_IN_SEL_S 0 @@ -4465,18 +4880,21 @@ #define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0280) /* GPIO_SIG84_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG84_IN_SEL (BIT(7)) +#define GPIO_SIG84_IN_SEL (BIT(7)) #define GPIO_SIG84_IN_SEL_M (BIT(7)) #define GPIO_SIG84_IN_SEL_V 0x1 #define GPIO_SIG84_IN_SEL_S 7 /* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC84_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC84_IN_INV_SEL (BIT(6)) #define GPIO_FUNC84_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC84_IN_INV_SEL_V 0x1 #define GPIO_FUNC84_IN_INV_SEL_S 6 @@ -4484,7 +4902,7 @@ /* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC84_IN_SEL 0x0000003F +#define GPIO_FUNC84_IN_SEL 0x0000003F #define GPIO_FUNC84_IN_SEL_M ((GPIO_FUNC84_IN_SEL_V)<<(GPIO_FUNC84_IN_SEL_S)) #define GPIO_FUNC84_IN_SEL_V 0x3F #define GPIO_FUNC84_IN_SEL_S 0 @@ -4492,18 +4910,21 @@ #define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0284) /* GPIO_SIG85_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG85_IN_SEL (BIT(7)) +#define GPIO_SIG85_IN_SEL (BIT(7)) #define GPIO_SIG85_IN_SEL_M (BIT(7)) #define GPIO_SIG85_IN_SEL_V 0x1 #define GPIO_SIG85_IN_SEL_S 7 /* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC85_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC85_IN_INV_SEL (BIT(6)) #define GPIO_FUNC85_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC85_IN_INV_SEL_V 0x1 #define GPIO_FUNC85_IN_INV_SEL_S 6 @@ -4511,7 +4932,7 @@ /* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC85_IN_SEL 0x0000003F +#define GPIO_FUNC85_IN_SEL 0x0000003F #define GPIO_FUNC85_IN_SEL_M ((GPIO_FUNC85_IN_SEL_V)<<(GPIO_FUNC85_IN_SEL_S)) #define GPIO_FUNC85_IN_SEL_V 0x3F #define GPIO_FUNC85_IN_SEL_S 0 @@ -4519,18 +4940,21 @@ #define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0288) /* GPIO_SIG86_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG86_IN_SEL (BIT(7)) +#define GPIO_SIG86_IN_SEL (BIT(7)) #define GPIO_SIG86_IN_SEL_M (BIT(7)) #define GPIO_SIG86_IN_SEL_V 0x1 #define GPIO_SIG86_IN_SEL_S 7 /* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC86_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC86_IN_INV_SEL (BIT(6)) #define GPIO_FUNC86_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC86_IN_INV_SEL_V 0x1 #define GPIO_FUNC86_IN_INV_SEL_S 6 @@ -4538,7 +4962,7 @@ /* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC86_IN_SEL 0x0000003F +#define GPIO_FUNC86_IN_SEL 0x0000003F #define GPIO_FUNC86_IN_SEL_M ((GPIO_FUNC86_IN_SEL_V)<<(GPIO_FUNC86_IN_SEL_S)) #define GPIO_FUNC86_IN_SEL_V 0x3F #define GPIO_FUNC86_IN_SEL_S 0 @@ -4546,18 +4970,21 @@ #define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x028c) /* GPIO_SIG87_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG87_IN_SEL (BIT(7)) +#define GPIO_SIG87_IN_SEL (BIT(7)) #define GPIO_SIG87_IN_SEL_M (BIT(7)) #define GPIO_SIG87_IN_SEL_V 0x1 #define GPIO_SIG87_IN_SEL_S 7 /* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC87_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC87_IN_INV_SEL (BIT(6)) #define GPIO_FUNC87_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC87_IN_INV_SEL_V 0x1 #define GPIO_FUNC87_IN_INV_SEL_S 6 @@ -4565,7 +4992,7 @@ /* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC87_IN_SEL 0x0000003F +#define GPIO_FUNC87_IN_SEL 0x0000003F #define GPIO_FUNC87_IN_SEL_M ((GPIO_FUNC87_IN_SEL_V)<<(GPIO_FUNC87_IN_SEL_S)) #define GPIO_FUNC87_IN_SEL_V 0x3F #define GPIO_FUNC87_IN_SEL_S 0 @@ -4573,18 +5000,21 @@ #define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0290) /* GPIO_SIG88_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG88_IN_SEL (BIT(7)) +#define GPIO_SIG88_IN_SEL (BIT(7)) #define GPIO_SIG88_IN_SEL_M (BIT(7)) #define GPIO_SIG88_IN_SEL_V 0x1 #define GPIO_SIG88_IN_SEL_S 7 /* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC88_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC88_IN_INV_SEL (BIT(6)) #define GPIO_FUNC88_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC88_IN_INV_SEL_V 0x1 #define GPIO_FUNC88_IN_INV_SEL_S 6 @@ -4592,7 +5022,7 @@ /* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC88_IN_SEL 0x0000003F +#define GPIO_FUNC88_IN_SEL 0x0000003F #define GPIO_FUNC88_IN_SEL_M ((GPIO_FUNC88_IN_SEL_V)<<(GPIO_FUNC88_IN_SEL_S)) #define GPIO_FUNC88_IN_SEL_V 0x3F #define GPIO_FUNC88_IN_SEL_S 0 @@ -4600,18 +5030,21 @@ #define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0294) /* GPIO_SIG89_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG89_IN_SEL (BIT(7)) +#define GPIO_SIG89_IN_SEL (BIT(7)) #define GPIO_SIG89_IN_SEL_M (BIT(7)) #define GPIO_SIG89_IN_SEL_V 0x1 #define GPIO_SIG89_IN_SEL_S 7 /* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC89_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC89_IN_INV_SEL (BIT(6)) #define GPIO_FUNC89_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC89_IN_INV_SEL_V 0x1 #define GPIO_FUNC89_IN_INV_SEL_S 6 @@ -4619,7 +5052,7 @@ /* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC89_IN_SEL 0x0000003F +#define GPIO_FUNC89_IN_SEL 0x0000003F #define GPIO_FUNC89_IN_SEL_M ((GPIO_FUNC89_IN_SEL_V)<<(GPIO_FUNC89_IN_SEL_S)) #define GPIO_FUNC89_IN_SEL_V 0x3F #define GPIO_FUNC89_IN_SEL_S 0 @@ -4627,18 +5060,21 @@ #define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0298) /* GPIO_SIG90_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG90_IN_SEL (BIT(7)) +#define GPIO_SIG90_IN_SEL (BIT(7)) #define GPIO_SIG90_IN_SEL_M (BIT(7)) #define GPIO_SIG90_IN_SEL_V 0x1 #define GPIO_SIG90_IN_SEL_S 7 /* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC90_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC90_IN_INV_SEL (BIT(6)) #define GPIO_FUNC90_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC90_IN_INV_SEL_V 0x1 #define GPIO_FUNC90_IN_INV_SEL_S 6 @@ -4646,7 +5082,7 @@ /* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC90_IN_SEL 0x0000003F +#define GPIO_FUNC90_IN_SEL 0x0000003F #define GPIO_FUNC90_IN_SEL_M ((GPIO_FUNC90_IN_SEL_V)<<(GPIO_FUNC90_IN_SEL_S)) #define GPIO_FUNC90_IN_SEL_V 0x3F #define GPIO_FUNC90_IN_SEL_S 0 @@ -4654,18 +5090,21 @@ #define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x029c) /* GPIO_SIG91_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG91_IN_SEL (BIT(7)) +#define GPIO_SIG91_IN_SEL (BIT(7)) #define GPIO_SIG91_IN_SEL_M (BIT(7)) #define GPIO_SIG91_IN_SEL_V 0x1 #define GPIO_SIG91_IN_SEL_S 7 /* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC91_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC91_IN_INV_SEL (BIT(6)) #define GPIO_FUNC91_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC91_IN_INV_SEL_V 0x1 #define GPIO_FUNC91_IN_INV_SEL_S 6 @@ -4673,7 +5112,7 @@ /* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC91_IN_SEL 0x0000003F +#define GPIO_FUNC91_IN_SEL 0x0000003F #define GPIO_FUNC91_IN_SEL_M ((GPIO_FUNC91_IN_SEL_V)<<(GPIO_FUNC91_IN_SEL_S)) #define GPIO_FUNC91_IN_SEL_V 0x3F #define GPIO_FUNC91_IN_SEL_S 0 @@ -4681,18 +5120,21 @@ #define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02a0) /* GPIO_SIG92_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG92_IN_SEL (BIT(7)) +#define GPIO_SIG92_IN_SEL (BIT(7)) #define GPIO_SIG92_IN_SEL_M (BIT(7)) #define GPIO_SIG92_IN_SEL_V 0x1 #define GPIO_SIG92_IN_SEL_S 7 /* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC92_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC92_IN_INV_SEL (BIT(6)) #define GPIO_FUNC92_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC92_IN_INV_SEL_V 0x1 #define GPIO_FUNC92_IN_INV_SEL_S 6 @@ -4700,7 +5142,7 @@ /* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC92_IN_SEL 0x0000003F +#define GPIO_FUNC92_IN_SEL 0x0000003F #define GPIO_FUNC92_IN_SEL_M ((GPIO_FUNC92_IN_SEL_V)<<(GPIO_FUNC92_IN_SEL_S)) #define GPIO_FUNC92_IN_SEL_V 0x3F #define GPIO_FUNC92_IN_SEL_S 0 @@ -4708,18 +5150,21 @@ #define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02a4) /* GPIO_SIG93_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG93_IN_SEL (BIT(7)) +#define GPIO_SIG93_IN_SEL (BIT(7)) #define GPIO_SIG93_IN_SEL_M (BIT(7)) #define GPIO_SIG93_IN_SEL_V 0x1 #define GPIO_SIG93_IN_SEL_S 7 /* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC93_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC93_IN_INV_SEL (BIT(6)) #define GPIO_FUNC93_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC93_IN_INV_SEL_V 0x1 #define GPIO_FUNC93_IN_INV_SEL_S 6 @@ -4727,7 +5172,7 @@ /* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC93_IN_SEL 0x0000003F +#define GPIO_FUNC93_IN_SEL 0x0000003F #define GPIO_FUNC93_IN_SEL_M ((GPIO_FUNC93_IN_SEL_V)<<(GPIO_FUNC93_IN_SEL_S)) #define GPIO_FUNC93_IN_SEL_V 0x3F #define GPIO_FUNC93_IN_SEL_S 0 @@ -4735,18 +5180,21 @@ #define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02a8) /* GPIO_SIG94_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG94_IN_SEL (BIT(7)) +#define GPIO_SIG94_IN_SEL (BIT(7)) #define GPIO_SIG94_IN_SEL_M (BIT(7)) #define GPIO_SIG94_IN_SEL_V 0x1 #define GPIO_SIG94_IN_SEL_S 7 /* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC94_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC94_IN_INV_SEL (BIT(6)) #define GPIO_FUNC94_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC94_IN_INV_SEL_V 0x1 #define GPIO_FUNC94_IN_INV_SEL_S 6 @@ -4754,7 +5202,7 @@ /* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC94_IN_SEL 0x0000003F +#define GPIO_FUNC94_IN_SEL 0x0000003F #define GPIO_FUNC94_IN_SEL_M ((GPIO_FUNC94_IN_SEL_V)<<(GPIO_FUNC94_IN_SEL_S)) #define GPIO_FUNC94_IN_SEL_V 0x3F #define GPIO_FUNC94_IN_SEL_S 0 @@ -4762,18 +5210,21 @@ #define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02ac) /* GPIO_SIG95_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG95_IN_SEL (BIT(7)) +#define GPIO_SIG95_IN_SEL (BIT(7)) #define GPIO_SIG95_IN_SEL_M (BIT(7)) #define GPIO_SIG95_IN_SEL_V 0x1 #define GPIO_SIG95_IN_SEL_S 7 /* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC95_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC95_IN_INV_SEL (BIT(6)) #define GPIO_FUNC95_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC95_IN_INV_SEL_V 0x1 #define GPIO_FUNC95_IN_INV_SEL_S 6 @@ -4781,7 +5232,7 @@ /* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC95_IN_SEL 0x0000003F +#define GPIO_FUNC95_IN_SEL 0x0000003F #define GPIO_FUNC95_IN_SEL_M ((GPIO_FUNC95_IN_SEL_V)<<(GPIO_FUNC95_IN_SEL_S)) #define GPIO_FUNC95_IN_SEL_V 0x3F #define GPIO_FUNC95_IN_SEL_S 0 @@ -4789,18 +5240,21 @@ #define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02b0) /* GPIO_SIG96_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG96_IN_SEL (BIT(7)) +#define GPIO_SIG96_IN_SEL (BIT(7)) #define GPIO_SIG96_IN_SEL_M (BIT(7)) #define GPIO_SIG96_IN_SEL_V 0x1 #define GPIO_SIG96_IN_SEL_S 7 /* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC96_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC96_IN_INV_SEL (BIT(6)) #define GPIO_FUNC96_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC96_IN_INV_SEL_V 0x1 #define GPIO_FUNC96_IN_INV_SEL_S 6 @@ -4808,7 +5262,7 @@ /* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC96_IN_SEL 0x0000003F +#define GPIO_FUNC96_IN_SEL 0x0000003F #define GPIO_FUNC96_IN_SEL_M ((GPIO_FUNC96_IN_SEL_V)<<(GPIO_FUNC96_IN_SEL_S)) #define GPIO_FUNC96_IN_SEL_V 0x3F #define GPIO_FUNC96_IN_SEL_S 0 @@ -4816,18 +5270,21 @@ #define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02b4) /* GPIO_SIG97_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG97_IN_SEL (BIT(7)) +#define GPIO_SIG97_IN_SEL (BIT(7)) #define GPIO_SIG97_IN_SEL_M (BIT(7)) #define GPIO_SIG97_IN_SEL_V 0x1 #define GPIO_SIG97_IN_SEL_S 7 /* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC97_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC97_IN_INV_SEL (BIT(6)) #define GPIO_FUNC97_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC97_IN_INV_SEL_V 0x1 #define GPIO_FUNC97_IN_INV_SEL_S 6 @@ -4835,7 +5292,7 @@ /* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC97_IN_SEL 0x0000003F +#define GPIO_FUNC97_IN_SEL 0x0000003F #define GPIO_FUNC97_IN_SEL_M ((GPIO_FUNC97_IN_SEL_V)<<(GPIO_FUNC97_IN_SEL_S)) #define GPIO_FUNC97_IN_SEL_V 0x3F #define GPIO_FUNC97_IN_SEL_S 0 @@ -4843,18 +5300,21 @@ #define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02b8) /* GPIO_SIG98_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG98_IN_SEL (BIT(7)) +#define GPIO_SIG98_IN_SEL (BIT(7)) #define GPIO_SIG98_IN_SEL_M (BIT(7)) #define GPIO_SIG98_IN_SEL_V 0x1 #define GPIO_SIG98_IN_SEL_S 7 /* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC98_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC98_IN_INV_SEL (BIT(6)) #define GPIO_FUNC98_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC98_IN_INV_SEL_V 0x1 #define GPIO_FUNC98_IN_INV_SEL_S 6 @@ -4862,7 +5322,7 @@ /* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC98_IN_SEL 0x0000003F +#define GPIO_FUNC98_IN_SEL 0x0000003F #define GPIO_FUNC98_IN_SEL_M ((GPIO_FUNC98_IN_SEL_V)<<(GPIO_FUNC98_IN_SEL_S)) #define GPIO_FUNC98_IN_SEL_V 0x3F #define GPIO_FUNC98_IN_SEL_S 0 @@ -4870,18 +5330,21 @@ #define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02bc) /* GPIO_SIG99_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG99_IN_SEL (BIT(7)) +#define GPIO_SIG99_IN_SEL (BIT(7)) #define GPIO_SIG99_IN_SEL_M (BIT(7)) #define GPIO_SIG99_IN_SEL_V 0x1 #define GPIO_SIG99_IN_SEL_S 7 /* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC99_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC99_IN_INV_SEL (BIT(6)) #define GPIO_FUNC99_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC99_IN_INV_SEL_V 0x1 #define GPIO_FUNC99_IN_INV_SEL_S 6 @@ -4889,7 +5352,7 @@ /* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC99_IN_SEL 0x0000003F +#define GPIO_FUNC99_IN_SEL 0x0000003F #define GPIO_FUNC99_IN_SEL_M ((GPIO_FUNC99_IN_SEL_V)<<(GPIO_FUNC99_IN_SEL_S)) #define GPIO_FUNC99_IN_SEL_V 0x3F #define GPIO_FUNC99_IN_SEL_S 0 @@ -4897,18 +5360,21 @@ #define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02c0) /* GPIO_SIG100_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG100_IN_SEL (BIT(7)) +#define GPIO_SIG100_IN_SEL (BIT(7)) #define GPIO_SIG100_IN_SEL_M (BIT(7)) #define GPIO_SIG100_IN_SEL_V 0x1 #define GPIO_SIG100_IN_SEL_S 7 /* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC100_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC100_IN_INV_SEL (BIT(6)) #define GPIO_FUNC100_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC100_IN_INV_SEL_V 0x1 #define GPIO_FUNC100_IN_INV_SEL_S 6 @@ -4916,7 +5382,7 @@ /* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC100_IN_SEL 0x0000003F +#define GPIO_FUNC100_IN_SEL 0x0000003F #define GPIO_FUNC100_IN_SEL_M ((GPIO_FUNC100_IN_SEL_V)<<(GPIO_FUNC100_IN_SEL_S)) #define GPIO_FUNC100_IN_SEL_V 0x3F #define GPIO_FUNC100_IN_SEL_S 0 @@ -4924,18 +5390,21 @@ #define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02c4) /* GPIO_SIG101_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG101_IN_SEL (BIT(7)) +#define GPIO_SIG101_IN_SEL (BIT(7)) #define GPIO_SIG101_IN_SEL_M (BIT(7)) #define GPIO_SIG101_IN_SEL_V 0x1 #define GPIO_SIG101_IN_SEL_S 7 /* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC101_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC101_IN_INV_SEL (BIT(6)) #define GPIO_FUNC101_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC101_IN_INV_SEL_V 0x1 #define GPIO_FUNC101_IN_INV_SEL_S 6 @@ -4943,7 +5412,7 @@ /* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC101_IN_SEL 0x0000003F +#define GPIO_FUNC101_IN_SEL 0x0000003F #define GPIO_FUNC101_IN_SEL_M ((GPIO_FUNC101_IN_SEL_V)<<(GPIO_FUNC101_IN_SEL_S)) #define GPIO_FUNC101_IN_SEL_V 0x3F #define GPIO_FUNC101_IN_SEL_S 0 @@ -4951,18 +5420,21 @@ #define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02c8) /* GPIO_SIG102_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG102_IN_SEL (BIT(7)) +#define GPIO_SIG102_IN_SEL (BIT(7)) #define GPIO_SIG102_IN_SEL_M (BIT(7)) #define GPIO_SIG102_IN_SEL_V 0x1 #define GPIO_SIG102_IN_SEL_S 7 /* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC102_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC102_IN_INV_SEL (BIT(6)) #define GPIO_FUNC102_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC102_IN_INV_SEL_V 0x1 #define GPIO_FUNC102_IN_INV_SEL_S 6 @@ -4970,7 +5442,7 @@ /* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC102_IN_SEL 0x0000003F +#define GPIO_FUNC102_IN_SEL 0x0000003F #define GPIO_FUNC102_IN_SEL_M ((GPIO_FUNC102_IN_SEL_V)<<(GPIO_FUNC102_IN_SEL_S)) #define GPIO_FUNC102_IN_SEL_V 0x3F #define GPIO_FUNC102_IN_SEL_S 0 @@ -4978,18 +5450,21 @@ #define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02cc) /* GPIO_SIG103_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG103_IN_SEL (BIT(7)) +#define GPIO_SIG103_IN_SEL (BIT(7)) #define GPIO_SIG103_IN_SEL_M (BIT(7)) #define GPIO_SIG103_IN_SEL_V 0x1 #define GPIO_SIG103_IN_SEL_S 7 /* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC103_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC103_IN_INV_SEL (BIT(6)) #define GPIO_FUNC103_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC103_IN_INV_SEL_V 0x1 #define GPIO_FUNC103_IN_INV_SEL_S 6 @@ -4997,7 +5472,7 @@ /* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC103_IN_SEL 0x0000003F +#define GPIO_FUNC103_IN_SEL 0x0000003F #define GPIO_FUNC103_IN_SEL_M ((GPIO_FUNC103_IN_SEL_V)<<(GPIO_FUNC103_IN_SEL_S)) #define GPIO_FUNC103_IN_SEL_V 0x3F #define GPIO_FUNC103_IN_SEL_S 0 @@ -5005,18 +5480,21 @@ #define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02d0) /* GPIO_SIG104_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG104_IN_SEL (BIT(7)) +#define GPIO_SIG104_IN_SEL (BIT(7)) #define GPIO_SIG104_IN_SEL_M (BIT(7)) #define GPIO_SIG104_IN_SEL_V 0x1 #define GPIO_SIG104_IN_SEL_S 7 /* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC104_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC104_IN_INV_SEL (BIT(6)) #define GPIO_FUNC104_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC104_IN_INV_SEL_V 0x1 #define GPIO_FUNC104_IN_INV_SEL_S 6 @@ -5024,7 +5502,7 @@ /* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC104_IN_SEL 0x0000003F +#define GPIO_FUNC104_IN_SEL 0x0000003F #define GPIO_FUNC104_IN_SEL_M ((GPIO_FUNC104_IN_SEL_V)<<(GPIO_FUNC104_IN_SEL_S)) #define GPIO_FUNC104_IN_SEL_V 0x3F #define GPIO_FUNC104_IN_SEL_S 0 @@ -5032,18 +5510,21 @@ #define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02d4) /* GPIO_SIG105_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG105_IN_SEL (BIT(7)) +#define GPIO_SIG105_IN_SEL (BIT(7)) #define GPIO_SIG105_IN_SEL_M (BIT(7)) #define GPIO_SIG105_IN_SEL_V 0x1 #define GPIO_SIG105_IN_SEL_S 7 /* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC105_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC105_IN_INV_SEL (BIT(6)) #define GPIO_FUNC105_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC105_IN_INV_SEL_V 0x1 #define GPIO_FUNC105_IN_INV_SEL_S 6 @@ -5051,7 +5532,7 @@ /* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC105_IN_SEL 0x0000003F +#define GPIO_FUNC105_IN_SEL 0x0000003F #define GPIO_FUNC105_IN_SEL_M ((GPIO_FUNC105_IN_SEL_V)<<(GPIO_FUNC105_IN_SEL_S)) #define GPIO_FUNC105_IN_SEL_V 0x3F #define GPIO_FUNC105_IN_SEL_S 0 @@ -5059,18 +5540,21 @@ #define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02d8) /* GPIO_SIG106_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG106_IN_SEL (BIT(7)) +#define GPIO_SIG106_IN_SEL (BIT(7)) #define GPIO_SIG106_IN_SEL_M (BIT(7)) #define GPIO_SIG106_IN_SEL_V 0x1 #define GPIO_SIG106_IN_SEL_S 7 /* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC106_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC106_IN_INV_SEL (BIT(6)) #define GPIO_FUNC106_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC106_IN_INV_SEL_V 0x1 #define GPIO_FUNC106_IN_INV_SEL_S 6 @@ -5078,7 +5562,7 @@ /* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC106_IN_SEL 0x0000003F +#define GPIO_FUNC106_IN_SEL 0x0000003F #define GPIO_FUNC106_IN_SEL_M ((GPIO_FUNC106_IN_SEL_V)<<(GPIO_FUNC106_IN_SEL_S)) #define GPIO_FUNC106_IN_SEL_V 0x3F #define GPIO_FUNC106_IN_SEL_S 0 @@ -5086,18 +5570,21 @@ #define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02dc) /* GPIO_SIG107_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG107_IN_SEL (BIT(7)) +#define GPIO_SIG107_IN_SEL (BIT(7)) #define GPIO_SIG107_IN_SEL_M (BIT(7)) #define GPIO_SIG107_IN_SEL_V 0x1 #define GPIO_SIG107_IN_SEL_S 7 /* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC107_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC107_IN_INV_SEL (BIT(6)) #define GPIO_FUNC107_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC107_IN_INV_SEL_V 0x1 #define GPIO_FUNC107_IN_INV_SEL_S 6 @@ -5105,7 +5592,7 @@ /* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC107_IN_SEL 0x0000003F +#define GPIO_FUNC107_IN_SEL 0x0000003F #define GPIO_FUNC107_IN_SEL_M ((GPIO_FUNC107_IN_SEL_V)<<(GPIO_FUNC107_IN_SEL_S)) #define GPIO_FUNC107_IN_SEL_V 0x3F #define GPIO_FUNC107_IN_SEL_S 0 @@ -5113,18 +5600,21 @@ #define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02e0) /* GPIO_SIG108_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG108_IN_SEL (BIT(7)) +#define GPIO_SIG108_IN_SEL (BIT(7)) #define GPIO_SIG108_IN_SEL_M (BIT(7)) #define GPIO_SIG108_IN_SEL_V 0x1 #define GPIO_SIG108_IN_SEL_S 7 /* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC108_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC108_IN_INV_SEL (BIT(6)) #define GPIO_FUNC108_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC108_IN_INV_SEL_V 0x1 #define GPIO_FUNC108_IN_INV_SEL_S 6 @@ -5132,7 +5622,7 @@ /* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC108_IN_SEL 0x0000003F +#define GPIO_FUNC108_IN_SEL 0x0000003F #define GPIO_FUNC108_IN_SEL_M ((GPIO_FUNC108_IN_SEL_V)<<(GPIO_FUNC108_IN_SEL_S)) #define GPIO_FUNC108_IN_SEL_V 0x3F #define GPIO_FUNC108_IN_SEL_S 0 @@ -5140,18 +5630,21 @@ #define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02e4) /* GPIO_SIG109_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG109_IN_SEL (BIT(7)) +#define GPIO_SIG109_IN_SEL (BIT(7)) #define GPIO_SIG109_IN_SEL_M (BIT(7)) #define GPIO_SIG109_IN_SEL_V 0x1 #define GPIO_SIG109_IN_SEL_S 7 /* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC109_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC109_IN_INV_SEL (BIT(6)) #define GPIO_FUNC109_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC109_IN_INV_SEL_V 0x1 #define GPIO_FUNC109_IN_INV_SEL_S 6 @@ -5159,7 +5652,7 @@ /* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC109_IN_SEL 0x0000003F +#define GPIO_FUNC109_IN_SEL 0x0000003F #define GPIO_FUNC109_IN_SEL_M ((GPIO_FUNC109_IN_SEL_V)<<(GPIO_FUNC109_IN_SEL_S)) #define GPIO_FUNC109_IN_SEL_V 0x3F #define GPIO_FUNC109_IN_SEL_S 0 @@ -5167,18 +5660,21 @@ #define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02e8) /* GPIO_SIG110_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG110_IN_SEL (BIT(7)) +#define GPIO_SIG110_IN_SEL (BIT(7)) #define GPIO_SIG110_IN_SEL_M (BIT(7)) #define GPIO_SIG110_IN_SEL_V 0x1 #define GPIO_SIG110_IN_SEL_S 7 /* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC110_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC110_IN_INV_SEL (BIT(6)) #define GPIO_FUNC110_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC110_IN_INV_SEL_V 0x1 #define GPIO_FUNC110_IN_INV_SEL_S 6 @@ -5186,7 +5682,7 @@ /* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC110_IN_SEL 0x0000003F +#define GPIO_FUNC110_IN_SEL 0x0000003F #define GPIO_FUNC110_IN_SEL_M ((GPIO_FUNC110_IN_SEL_V)<<(GPIO_FUNC110_IN_SEL_S)) #define GPIO_FUNC110_IN_SEL_V 0x3F #define GPIO_FUNC110_IN_SEL_S 0 @@ -5194,18 +5690,21 @@ #define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02ec) /* GPIO_SIG111_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG111_IN_SEL (BIT(7)) +#define GPIO_SIG111_IN_SEL (BIT(7)) #define GPIO_SIG111_IN_SEL_M (BIT(7)) #define GPIO_SIG111_IN_SEL_V 0x1 #define GPIO_SIG111_IN_SEL_S 7 /* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC111_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC111_IN_INV_SEL (BIT(6)) #define GPIO_FUNC111_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC111_IN_INV_SEL_V 0x1 #define GPIO_FUNC111_IN_INV_SEL_S 6 @@ -5213,7 +5712,7 @@ /* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC111_IN_SEL 0x0000003F +#define GPIO_FUNC111_IN_SEL 0x0000003F #define GPIO_FUNC111_IN_SEL_M ((GPIO_FUNC111_IN_SEL_V)<<(GPIO_FUNC111_IN_SEL_S)) #define GPIO_FUNC111_IN_SEL_V 0x3F #define GPIO_FUNC111_IN_SEL_S 0 @@ -5221,18 +5720,21 @@ #define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02f0) /* GPIO_SIG112_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG112_IN_SEL (BIT(7)) +#define GPIO_SIG112_IN_SEL (BIT(7)) #define GPIO_SIG112_IN_SEL_M (BIT(7)) #define GPIO_SIG112_IN_SEL_V 0x1 #define GPIO_SIG112_IN_SEL_S 7 /* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC112_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC112_IN_INV_SEL (BIT(6)) #define GPIO_FUNC112_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC112_IN_INV_SEL_V 0x1 #define GPIO_FUNC112_IN_INV_SEL_S 6 @@ -5240,7 +5742,7 @@ /* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC112_IN_SEL 0x0000003F +#define GPIO_FUNC112_IN_SEL 0x0000003F #define GPIO_FUNC112_IN_SEL_M ((GPIO_FUNC112_IN_SEL_V)<<(GPIO_FUNC112_IN_SEL_S)) #define GPIO_FUNC112_IN_SEL_V 0x3F #define GPIO_FUNC112_IN_SEL_S 0 @@ -5248,18 +5750,21 @@ #define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02f4) /* GPIO_SIG113_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG113_IN_SEL (BIT(7)) +#define GPIO_SIG113_IN_SEL (BIT(7)) #define GPIO_SIG113_IN_SEL_M (BIT(7)) #define GPIO_SIG113_IN_SEL_V 0x1 #define GPIO_SIG113_IN_SEL_S 7 /* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC113_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC113_IN_INV_SEL (BIT(6)) #define GPIO_FUNC113_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC113_IN_INV_SEL_V 0x1 #define GPIO_FUNC113_IN_INV_SEL_S 6 @@ -5267,7 +5772,7 @@ /* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC113_IN_SEL 0x0000003F +#define GPIO_FUNC113_IN_SEL 0x0000003F #define GPIO_FUNC113_IN_SEL_M ((GPIO_FUNC113_IN_SEL_V)<<(GPIO_FUNC113_IN_SEL_S)) #define GPIO_FUNC113_IN_SEL_V 0x3F #define GPIO_FUNC113_IN_SEL_S 0 @@ -5275,18 +5780,21 @@ #define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02f8) /* GPIO_SIG114_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG114_IN_SEL (BIT(7)) +#define GPIO_SIG114_IN_SEL (BIT(7)) #define GPIO_SIG114_IN_SEL_M (BIT(7)) #define GPIO_SIG114_IN_SEL_V 0x1 #define GPIO_SIG114_IN_SEL_S 7 /* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC114_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC114_IN_INV_SEL (BIT(6)) #define GPIO_FUNC114_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC114_IN_INV_SEL_V 0x1 #define GPIO_FUNC114_IN_INV_SEL_S 6 @@ -5294,7 +5802,7 @@ /* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC114_IN_SEL 0x0000003F +#define GPIO_FUNC114_IN_SEL 0x0000003F #define GPIO_FUNC114_IN_SEL_M ((GPIO_FUNC114_IN_SEL_V)<<(GPIO_FUNC114_IN_SEL_S)) #define GPIO_FUNC114_IN_SEL_V 0x3F #define GPIO_FUNC114_IN_SEL_S 0 @@ -5302,18 +5810,21 @@ #define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x02fc) /* GPIO_SIG115_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG115_IN_SEL (BIT(7)) +#define GPIO_SIG115_IN_SEL (BIT(7)) #define GPIO_SIG115_IN_SEL_M (BIT(7)) #define GPIO_SIG115_IN_SEL_V 0x1 #define GPIO_SIG115_IN_SEL_S 7 /* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC115_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC115_IN_INV_SEL (BIT(6)) #define GPIO_FUNC115_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC115_IN_INV_SEL_V 0x1 #define GPIO_FUNC115_IN_INV_SEL_S 6 @@ -5321,7 +5832,7 @@ /* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC115_IN_SEL 0x0000003F +#define GPIO_FUNC115_IN_SEL 0x0000003F #define GPIO_FUNC115_IN_SEL_M ((GPIO_FUNC115_IN_SEL_V)<<(GPIO_FUNC115_IN_SEL_S)) #define GPIO_FUNC115_IN_SEL_V 0x3F #define GPIO_FUNC115_IN_SEL_S 0 @@ -5329,18 +5840,21 @@ #define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0300) /* GPIO_SIG116_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG116_IN_SEL (BIT(7)) +#define GPIO_SIG116_IN_SEL (BIT(7)) #define GPIO_SIG116_IN_SEL_M (BIT(7)) #define GPIO_SIG116_IN_SEL_V 0x1 #define GPIO_SIG116_IN_SEL_S 7 /* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC116_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC116_IN_INV_SEL (BIT(6)) #define GPIO_FUNC116_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC116_IN_INV_SEL_V 0x1 #define GPIO_FUNC116_IN_INV_SEL_S 6 @@ -5348,7 +5862,7 @@ /* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC116_IN_SEL 0x0000003F +#define GPIO_FUNC116_IN_SEL 0x0000003F #define GPIO_FUNC116_IN_SEL_M ((GPIO_FUNC116_IN_SEL_V)<<(GPIO_FUNC116_IN_SEL_S)) #define GPIO_FUNC116_IN_SEL_V 0x3F #define GPIO_FUNC116_IN_SEL_S 0 @@ -5356,18 +5870,21 @@ #define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0304) /* GPIO_SIG117_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG117_IN_SEL (BIT(7)) +#define GPIO_SIG117_IN_SEL (BIT(7)) #define GPIO_SIG117_IN_SEL_M (BIT(7)) #define GPIO_SIG117_IN_SEL_V 0x1 #define GPIO_SIG117_IN_SEL_S 7 /* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC117_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC117_IN_INV_SEL (BIT(6)) #define GPIO_FUNC117_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC117_IN_INV_SEL_V 0x1 #define GPIO_FUNC117_IN_INV_SEL_S 6 @@ -5375,7 +5892,7 @@ /* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC117_IN_SEL 0x0000003F +#define GPIO_FUNC117_IN_SEL 0x0000003F #define GPIO_FUNC117_IN_SEL_M ((GPIO_FUNC117_IN_SEL_V)<<(GPIO_FUNC117_IN_SEL_S)) #define GPIO_FUNC117_IN_SEL_V 0x3F #define GPIO_FUNC117_IN_SEL_S 0 @@ -5383,18 +5900,21 @@ #define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0308) /* GPIO_SIG118_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG118_IN_SEL (BIT(7)) +#define GPIO_SIG118_IN_SEL (BIT(7)) #define GPIO_SIG118_IN_SEL_M (BIT(7)) #define GPIO_SIG118_IN_SEL_V 0x1 #define GPIO_SIG118_IN_SEL_S 7 /* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC118_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC118_IN_INV_SEL (BIT(6)) #define GPIO_FUNC118_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC118_IN_INV_SEL_V 0x1 #define GPIO_FUNC118_IN_INV_SEL_S 6 @@ -5402,7 +5922,7 @@ /* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC118_IN_SEL 0x0000003F +#define GPIO_FUNC118_IN_SEL 0x0000003F #define GPIO_FUNC118_IN_SEL_M ((GPIO_FUNC118_IN_SEL_V)<<(GPIO_FUNC118_IN_SEL_S)) #define GPIO_FUNC118_IN_SEL_V 0x3F #define GPIO_FUNC118_IN_SEL_S 0 @@ -5410,18 +5930,21 @@ #define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x030c) /* GPIO_SIG119_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG119_IN_SEL (BIT(7)) +#define GPIO_SIG119_IN_SEL (BIT(7)) #define GPIO_SIG119_IN_SEL_M (BIT(7)) #define GPIO_SIG119_IN_SEL_V 0x1 #define GPIO_SIG119_IN_SEL_S 7 /* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC119_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC119_IN_INV_SEL (BIT(6)) #define GPIO_FUNC119_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC119_IN_INV_SEL_V 0x1 #define GPIO_FUNC119_IN_INV_SEL_S 6 @@ -5429,7 +5952,7 @@ /* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC119_IN_SEL 0x0000003F +#define GPIO_FUNC119_IN_SEL 0x0000003F #define GPIO_FUNC119_IN_SEL_M ((GPIO_FUNC119_IN_SEL_V)<<(GPIO_FUNC119_IN_SEL_S)) #define GPIO_FUNC119_IN_SEL_V 0x3F #define GPIO_FUNC119_IN_SEL_S 0 @@ -5437,18 +5960,21 @@ #define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0310) /* GPIO_SIG120_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG120_IN_SEL (BIT(7)) +#define GPIO_SIG120_IN_SEL (BIT(7)) #define GPIO_SIG120_IN_SEL_M (BIT(7)) #define GPIO_SIG120_IN_SEL_V 0x1 #define GPIO_SIG120_IN_SEL_S 7 /* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC120_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC120_IN_INV_SEL (BIT(6)) #define GPIO_FUNC120_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC120_IN_INV_SEL_V 0x1 #define GPIO_FUNC120_IN_INV_SEL_S 6 @@ -5456,7 +5982,7 @@ /* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC120_IN_SEL 0x0000003F +#define GPIO_FUNC120_IN_SEL 0x0000003F #define GPIO_FUNC120_IN_SEL_M ((GPIO_FUNC120_IN_SEL_V)<<(GPIO_FUNC120_IN_SEL_S)) #define GPIO_FUNC120_IN_SEL_V 0x3F #define GPIO_FUNC120_IN_SEL_S 0 @@ -5464,18 +5990,21 @@ #define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0314) /* GPIO_SIG121_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG121_IN_SEL (BIT(7)) +#define GPIO_SIG121_IN_SEL (BIT(7)) #define GPIO_SIG121_IN_SEL_M (BIT(7)) #define GPIO_SIG121_IN_SEL_V 0x1 #define GPIO_SIG121_IN_SEL_S 7 /* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC121_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC121_IN_INV_SEL (BIT(6)) #define GPIO_FUNC121_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC121_IN_INV_SEL_V 0x1 #define GPIO_FUNC121_IN_INV_SEL_S 6 @@ -5483,7 +6012,7 @@ /* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC121_IN_SEL 0x0000003F +#define GPIO_FUNC121_IN_SEL 0x0000003F #define GPIO_FUNC121_IN_SEL_M ((GPIO_FUNC121_IN_SEL_V)<<(GPIO_FUNC121_IN_SEL_S)) #define GPIO_FUNC121_IN_SEL_V 0x3F #define GPIO_FUNC121_IN_SEL_S 0 @@ -5491,18 +6020,21 @@ #define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0318) /* GPIO_SIG122_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG122_IN_SEL (BIT(7)) +#define GPIO_SIG122_IN_SEL (BIT(7)) #define GPIO_SIG122_IN_SEL_M (BIT(7)) #define GPIO_SIG122_IN_SEL_V 0x1 #define GPIO_SIG122_IN_SEL_S 7 /* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC122_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC122_IN_INV_SEL (BIT(6)) #define GPIO_FUNC122_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC122_IN_INV_SEL_V 0x1 #define GPIO_FUNC122_IN_INV_SEL_S 6 @@ -5510,7 +6042,7 @@ /* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC122_IN_SEL 0x0000003F +#define GPIO_FUNC122_IN_SEL 0x0000003F #define GPIO_FUNC122_IN_SEL_M ((GPIO_FUNC122_IN_SEL_V)<<(GPIO_FUNC122_IN_SEL_S)) #define GPIO_FUNC122_IN_SEL_V 0x3F #define GPIO_FUNC122_IN_SEL_S 0 @@ -5518,18 +6050,21 @@ #define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x031c) /* GPIO_SIG123_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG123_IN_SEL (BIT(7)) +#define GPIO_SIG123_IN_SEL (BIT(7)) #define GPIO_SIG123_IN_SEL_M (BIT(7)) #define GPIO_SIG123_IN_SEL_V 0x1 #define GPIO_SIG123_IN_SEL_S 7 /* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC123_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC123_IN_INV_SEL (BIT(6)) #define GPIO_FUNC123_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC123_IN_INV_SEL_V 0x1 #define GPIO_FUNC123_IN_INV_SEL_S 6 @@ -5537,7 +6072,7 @@ /* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC123_IN_SEL 0x0000003F +#define GPIO_FUNC123_IN_SEL 0x0000003F #define GPIO_FUNC123_IN_SEL_M ((GPIO_FUNC123_IN_SEL_V)<<(GPIO_FUNC123_IN_SEL_S)) #define GPIO_FUNC123_IN_SEL_V 0x3F #define GPIO_FUNC123_IN_SEL_S 0 @@ -5545,18 +6080,21 @@ #define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0320) /* GPIO_SIG124_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG124_IN_SEL (BIT(7)) +#define GPIO_SIG124_IN_SEL (BIT(7)) #define GPIO_SIG124_IN_SEL_M (BIT(7)) #define GPIO_SIG124_IN_SEL_V 0x1 #define GPIO_SIG124_IN_SEL_S 7 /* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC124_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC124_IN_INV_SEL (BIT(6)) #define GPIO_FUNC124_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC124_IN_INV_SEL_V 0x1 #define GPIO_FUNC124_IN_INV_SEL_S 6 @@ -5564,7 +6102,7 @@ /* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC124_IN_SEL 0x0000003F +#define GPIO_FUNC124_IN_SEL 0x0000003F #define GPIO_FUNC124_IN_SEL_M ((GPIO_FUNC124_IN_SEL_V)<<(GPIO_FUNC124_IN_SEL_S)) #define GPIO_FUNC124_IN_SEL_V 0x3F #define GPIO_FUNC124_IN_SEL_S 0 @@ -5572,18 +6110,21 @@ #define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0324) /* GPIO_SIG125_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG125_IN_SEL (BIT(7)) +#define GPIO_SIG125_IN_SEL (BIT(7)) #define GPIO_SIG125_IN_SEL_M (BIT(7)) #define GPIO_SIG125_IN_SEL_V 0x1 #define GPIO_SIG125_IN_SEL_S 7 /* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC125_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC125_IN_INV_SEL (BIT(6)) #define GPIO_FUNC125_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC125_IN_INV_SEL_V 0x1 #define GPIO_FUNC125_IN_INV_SEL_S 6 @@ -5591,7 +6132,7 @@ /* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC125_IN_SEL 0x0000003F +#define GPIO_FUNC125_IN_SEL 0x0000003F #define GPIO_FUNC125_IN_SEL_M ((GPIO_FUNC125_IN_SEL_V)<<(GPIO_FUNC125_IN_SEL_S)) #define GPIO_FUNC125_IN_SEL_V 0x3F #define GPIO_FUNC125_IN_SEL_S 0 @@ -5599,18 +6140,21 @@ #define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0328) /* GPIO_SIG126_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG126_IN_SEL (BIT(7)) +#define GPIO_SIG126_IN_SEL (BIT(7)) #define GPIO_SIG126_IN_SEL_M (BIT(7)) #define GPIO_SIG126_IN_SEL_V 0x1 #define GPIO_SIG126_IN_SEL_S 7 /* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC126_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC126_IN_INV_SEL (BIT(6)) #define GPIO_FUNC126_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC126_IN_INV_SEL_V 0x1 #define GPIO_FUNC126_IN_INV_SEL_S 6 @@ -5618,7 +6162,7 @@ /* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC126_IN_SEL 0x0000003F +#define GPIO_FUNC126_IN_SEL 0x0000003F #define GPIO_FUNC126_IN_SEL_M ((GPIO_FUNC126_IN_SEL_V)<<(GPIO_FUNC126_IN_SEL_S)) #define GPIO_FUNC126_IN_SEL_V 0x3F #define GPIO_FUNC126_IN_SEL_S 0 @@ -5626,18 +6170,21 @@ #define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x032c) /* GPIO_SIG127_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG127_IN_SEL (BIT(7)) +#define GPIO_SIG127_IN_SEL (BIT(7)) #define GPIO_SIG127_IN_SEL_M (BIT(7)) #define GPIO_SIG127_IN_SEL_V 0x1 #define GPIO_SIG127_IN_SEL_S 7 /* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC127_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC127_IN_INV_SEL (BIT(6)) #define GPIO_FUNC127_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC127_IN_INV_SEL_V 0x1 #define GPIO_FUNC127_IN_INV_SEL_S 6 @@ -5645,7 +6192,7 @@ /* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC127_IN_SEL 0x0000003F +#define GPIO_FUNC127_IN_SEL 0x0000003F #define GPIO_FUNC127_IN_SEL_M ((GPIO_FUNC127_IN_SEL_V)<<(GPIO_FUNC127_IN_SEL_S)) #define GPIO_FUNC127_IN_SEL_V 0x3F #define GPIO_FUNC127_IN_SEL_S 0 @@ -5653,18 +6200,21 @@ #define GPIO_FUNC128_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0330) /* GPIO_SIG128_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG128_IN_SEL (BIT(7)) +#define GPIO_SIG128_IN_SEL (BIT(7)) #define GPIO_SIG128_IN_SEL_M (BIT(7)) #define GPIO_SIG128_IN_SEL_V 0x1 #define GPIO_SIG128_IN_SEL_S 7 /* GPIO_FUNC128_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC128_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC128_IN_INV_SEL (BIT(6)) #define GPIO_FUNC128_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC128_IN_INV_SEL_V 0x1 #define GPIO_FUNC128_IN_INV_SEL_S 6 @@ -5672,7 +6222,7 @@ /* GPIO_FUNC128_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC128_IN_SEL 0x0000003F +#define GPIO_FUNC128_IN_SEL 0x0000003F #define GPIO_FUNC128_IN_SEL_M ((GPIO_FUNC128_IN_SEL_V)<<(GPIO_FUNC128_IN_SEL_S)) #define GPIO_FUNC128_IN_SEL_V 0x3F #define GPIO_FUNC128_IN_SEL_S 0 @@ -5680,18 +6230,21 @@ #define GPIO_FUNC129_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0334) /* GPIO_SIG129_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG129_IN_SEL (BIT(7)) +#define GPIO_SIG129_IN_SEL (BIT(7)) #define GPIO_SIG129_IN_SEL_M (BIT(7)) #define GPIO_SIG129_IN_SEL_V 0x1 #define GPIO_SIG129_IN_SEL_S 7 /* GPIO_FUNC129_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC129_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC129_IN_INV_SEL (BIT(6)) #define GPIO_FUNC129_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC129_IN_INV_SEL_V 0x1 #define GPIO_FUNC129_IN_INV_SEL_S 6 @@ -5699,7 +6252,7 @@ /* GPIO_FUNC129_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC129_IN_SEL 0x0000003F +#define GPIO_FUNC129_IN_SEL 0x0000003F #define GPIO_FUNC129_IN_SEL_M ((GPIO_FUNC129_IN_SEL_V)<<(GPIO_FUNC129_IN_SEL_S)) #define GPIO_FUNC129_IN_SEL_V 0x3F #define GPIO_FUNC129_IN_SEL_S 0 @@ -5707,18 +6260,21 @@ #define GPIO_FUNC130_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0338) /* GPIO_SIG130_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG130_IN_SEL (BIT(7)) +#define GPIO_SIG130_IN_SEL (BIT(7)) #define GPIO_SIG130_IN_SEL_M (BIT(7)) #define GPIO_SIG130_IN_SEL_V 0x1 #define GPIO_SIG130_IN_SEL_S 7 /* GPIO_FUNC130_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC130_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC130_IN_INV_SEL (BIT(6)) #define GPIO_FUNC130_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC130_IN_INV_SEL_V 0x1 #define GPIO_FUNC130_IN_INV_SEL_S 6 @@ -5726,7 +6282,7 @@ /* GPIO_FUNC130_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC130_IN_SEL 0x0000003F +#define GPIO_FUNC130_IN_SEL 0x0000003F #define GPIO_FUNC130_IN_SEL_M ((GPIO_FUNC130_IN_SEL_V)<<(GPIO_FUNC130_IN_SEL_S)) #define GPIO_FUNC130_IN_SEL_V 0x3F #define GPIO_FUNC130_IN_SEL_S 0 @@ -5734,18 +6290,21 @@ #define GPIO_FUNC131_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x033c) /* GPIO_SIG131_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG131_IN_SEL (BIT(7)) +#define GPIO_SIG131_IN_SEL (BIT(7)) #define GPIO_SIG131_IN_SEL_M (BIT(7)) #define GPIO_SIG131_IN_SEL_V 0x1 #define GPIO_SIG131_IN_SEL_S 7 /* GPIO_FUNC131_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC131_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC131_IN_INV_SEL (BIT(6)) #define GPIO_FUNC131_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC131_IN_INV_SEL_V 0x1 #define GPIO_FUNC131_IN_INV_SEL_S 6 @@ -5753,7 +6312,7 @@ /* GPIO_FUNC131_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC131_IN_SEL 0x0000003F +#define GPIO_FUNC131_IN_SEL 0x0000003F #define GPIO_FUNC131_IN_SEL_M ((GPIO_FUNC131_IN_SEL_V)<<(GPIO_FUNC131_IN_SEL_S)) #define GPIO_FUNC131_IN_SEL_V 0x3F #define GPIO_FUNC131_IN_SEL_S 0 @@ -5761,18 +6320,21 @@ #define GPIO_FUNC132_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0340) /* GPIO_SIG132_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG132_IN_SEL (BIT(7)) +#define GPIO_SIG132_IN_SEL (BIT(7)) #define GPIO_SIG132_IN_SEL_M (BIT(7)) #define GPIO_SIG132_IN_SEL_V 0x1 #define GPIO_SIG132_IN_SEL_S 7 /* GPIO_FUNC132_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC132_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC132_IN_INV_SEL (BIT(6)) #define GPIO_FUNC132_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC132_IN_INV_SEL_V 0x1 #define GPIO_FUNC132_IN_INV_SEL_S 6 @@ -5780,7 +6342,7 @@ /* GPIO_FUNC132_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC132_IN_SEL 0x0000003F +#define GPIO_FUNC132_IN_SEL 0x0000003F #define GPIO_FUNC132_IN_SEL_M ((GPIO_FUNC132_IN_SEL_V)<<(GPIO_FUNC132_IN_SEL_S)) #define GPIO_FUNC132_IN_SEL_V 0x3F #define GPIO_FUNC132_IN_SEL_S 0 @@ -5788,18 +6350,21 @@ #define GPIO_FUNC133_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0344) /* GPIO_SIG133_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG133_IN_SEL (BIT(7)) +#define GPIO_SIG133_IN_SEL (BIT(7)) #define GPIO_SIG133_IN_SEL_M (BIT(7)) #define GPIO_SIG133_IN_SEL_V 0x1 #define GPIO_SIG133_IN_SEL_S 7 /* GPIO_FUNC133_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC133_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC133_IN_INV_SEL (BIT(6)) #define GPIO_FUNC133_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC133_IN_INV_SEL_V 0x1 #define GPIO_FUNC133_IN_INV_SEL_S 6 @@ -5807,7 +6372,7 @@ /* GPIO_FUNC133_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC133_IN_SEL 0x0000003F +#define GPIO_FUNC133_IN_SEL 0x0000003F #define GPIO_FUNC133_IN_SEL_M ((GPIO_FUNC133_IN_SEL_V)<<(GPIO_FUNC133_IN_SEL_S)) #define GPIO_FUNC133_IN_SEL_V 0x3F #define GPIO_FUNC133_IN_SEL_S 0 @@ -5815,18 +6380,21 @@ #define GPIO_FUNC134_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0348) /* GPIO_SIG134_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG134_IN_SEL (BIT(7)) +#define GPIO_SIG134_IN_SEL (BIT(7)) #define GPIO_SIG134_IN_SEL_M (BIT(7)) #define GPIO_SIG134_IN_SEL_V 0x1 #define GPIO_SIG134_IN_SEL_S 7 /* GPIO_FUNC134_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC134_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC134_IN_INV_SEL (BIT(6)) #define GPIO_FUNC134_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC134_IN_INV_SEL_V 0x1 #define GPIO_FUNC134_IN_INV_SEL_S 6 @@ -5834,7 +6402,7 @@ /* GPIO_FUNC134_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC134_IN_SEL 0x0000003F +#define GPIO_FUNC134_IN_SEL 0x0000003F #define GPIO_FUNC134_IN_SEL_M ((GPIO_FUNC134_IN_SEL_V)<<(GPIO_FUNC134_IN_SEL_S)) #define GPIO_FUNC134_IN_SEL_V 0x3F #define GPIO_FUNC134_IN_SEL_S 0 @@ -5842,18 +6410,21 @@ #define GPIO_FUNC135_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x034c) /* GPIO_SIG135_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG135_IN_SEL (BIT(7)) +#define GPIO_SIG135_IN_SEL (BIT(7)) #define GPIO_SIG135_IN_SEL_M (BIT(7)) #define GPIO_SIG135_IN_SEL_V 0x1 #define GPIO_SIG135_IN_SEL_S 7 /* GPIO_FUNC135_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC135_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC135_IN_INV_SEL (BIT(6)) #define GPIO_FUNC135_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC135_IN_INV_SEL_V 0x1 #define GPIO_FUNC135_IN_INV_SEL_S 6 @@ -5861,7 +6432,7 @@ /* GPIO_FUNC135_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC135_IN_SEL 0x0000003F +#define GPIO_FUNC135_IN_SEL 0x0000003F #define GPIO_FUNC135_IN_SEL_M ((GPIO_FUNC135_IN_SEL_V)<<(GPIO_FUNC135_IN_SEL_S)) #define GPIO_FUNC135_IN_SEL_V 0x3F #define GPIO_FUNC135_IN_SEL_S 0 @@ -5869,18 +6440,21 @@ #define GPIO_FUNC136_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0350) /* GPIO_SIG136_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG136_IN_SEL (BIT(7)) +#define GPIO_SIG136_IN_SEL (BIT(7)) #define GPIO_SIG136_IN_SEL_M (BIT(7)) #define GPIO_SIG136_IN_SEL_V 0x1 #define GPIO_SIG136_IN_SEL_S 7 /* GPIO_FUNC136_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC136_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC136_IN_INV_SEL (BIT(6)) #define GPIO_FUNC136_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC136_IN_INV_SEL_V 0x1 #define GPIO_FUNC136_IN_INV_SEL_S 6 @@ -5888,7 +6462,7 @@ /* GPIO_FUNC136_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC136_IN_SEL 0x0000003F +#define GPIO_FUNC136_IN_SEL 0x0000003F #define GPIO_FUNC136_IN_SEL_M ((GPIO_FUNC136_IN_SEL_V)<<(GPIO_FUNC136_IN_SEL_S)) #define GPIO_FUNC136_IN_SEL_V 0x3F #define GPIO_FUNC136_IN_SEL_S 0 @@ -5896,18 +6470,21 @@ #define GPIO_FUNC137_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0354) /* GPIO_SIG137_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG137_IN_SEL (BIT(7)) +#define GPIO_SIG137_IN_SEL (BIT(7)) #define GPIO_SIG137_IN_SEL_M (BIT(7)) #define GPIO_SIG137_IN_SEL_V 0x1 #define GPIO_SIG137_IN_SEL_S 7 /* GPIO_FUNC137_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC137_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC137_IN_INV_SEL (BIT(6)) #define GPIO_FUNC137_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC137_IN_INV_SEL_V 0x1 #define GPIO_FUNC137_IN_INV_SEL_S 6 @@ -5915,7 +6492,7 @@ /* GPIO_FUNC137_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC137_IN_SEL 0x0000003F +#define GPIO_FUNC137_IN_SEL 0x0000003F #define GPIO_FUNC137_IN_SEL_M ((GPIO_FUNC137_IN_SEL_V)<<(GPIO_FUNC137_IN_SEL_S)) #define GPIO_FUNC137_IN_SEL_V 0x3F #define GPIO_FUNC137_IN_SEL_S 0 @@ -5923,18 +6500,21 @@ #define GPIO_FUNC138_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0358) /* GPIO_SIG138_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG138_IN_SEL (BIT(7)) +#define GPIO_SIG138_IN_SEL (BIT(7)) #define GPIO_SIG138_IN_SEL_M (BIT(7)) #define GPIO_SIG138_IN_SEL_V 0x1 #define GPIO_SIG138_IN_SEL_S 7 /* GPIO_FUNC138_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC138_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC138_IN_INV_SEL (BIT(6)) #define GPIO_FUNC138_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC138_IN_INV_SEL_V 0x1 #define GPIO_FUNC138_IN_INV_SEL_S 6 @@ -5942,7 +6522,7 @@ /* GPIO_FUNC138_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC138_IN_SEL 0x0000003F +#define GPIO_FUNC138_IN_SEL 0x0000003F #define GPIO_FUNC138_IN_SEL_M ((GPIO_FUNC138_IN_SEL_V)<<(GPIO_FUNC138_IN_SEL_S)) #define GPIO_FUNC138_IN_SEL_V 0x3F #define GPIO_FUNC138_IN_SEL_S 0 @@ -5950,18 +6530,21 @@ #define GPIO_FUNC139_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x035c) /* GPIO_SIG139_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG139_IN_SEL (BIT(7)) +#define GPIO_SIG139_IN_SEL (BIT(7)) #define GPIO_SIG139_IN_SEL_M (BIT(7)) #define GPIO_SIG139_IN_SEL_V 0x1 #define GPIO_SIG139_IN_SEL_S 7 /* GPIO_FUNC139_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC139_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC139_IN_INV_SEL (BIT(6)) #define GPIO_FUNC139_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC139_IN_INV_SEL_V 0x1 #define GPIO_FUNC139_IN_INV_SEL_S 6 @@ -5969,7 +6552,7 @@ /* GPIO_FUNC139_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC139_IN_SEL 0x0000003F +#define GPIO_FUNC139_IN_SEL 0x0000003F #define GPIO_FUNC139_IN_SEL_M ((GPIO_FUNC139_IN_SEL_V)<<(GPIO_FUNC139_IN_SEL_S)) #define GPIO_FUNC139_IN_SEL_V 0x3F #define GPIO_FUNC139_IN_SEL_S 0 @@ -5977,18 +6560,21 @@ #define GPIO_FUNC140_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0360) /* GPIO_SIG140_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG140_IN_SEL (BIT(7)) +#define GPIO_SIG140_IN_SEL (BIT(7)) #define GPIO_SIG140_IN_SEL_M (BIT(7)) #define GPIO_SIG140_IN_SEL_V 0x1 #define GPIO_SIG140_IN_SEL_S 7 /* GPIO_FUNC140_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC140_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC140_IN_INV_SEL (BIT(6)) #define GPIO_FUNC140_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC140_IN_INV_SEL_V 0x1 #define GPIO_FUNC140_IN_INV_SEL_S 6 @@ -5996,7 +6582,7 @@ /* GPIO_FUNC140_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC140_IN_SEL 0x0000003F +#define GPIO_FUNC140_IN_SEL 0x0000003F #define GPIO_FUNC140_IN_SEL_M ((GPIO_FUNC140_IN_SEL_V)<<(GPIO_FUNC140_IN_SEL_S)) #define GPIO_FUNC140_IN_SEL_V 0x3F #define GPIO_FUNC140_IN_SEL_S 0 @@ -6004,18 +6590,21 @@ #define GPIO_FUNC141_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0364) /* GPIO_SIG141_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG141_IN_SEL (BIT(7)) +#define GPIO_SIG141_IN_SEL (BIT(7)) #define GPIO_SIG141_IN_SEL_M (BIT(7)) #define GPIO_SIG141_IN_SEL_V 0x1 #define GPIO_SIG141_IN_SEL_S 7 /* GPIO_FUNC141_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC141_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC141_IN_INV_SEL (BIT(6)) #define GPIO_FUNC141_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC141_IN_INV_SEL_V 0x1 #define GPIO_FUNC141_IN_INV_SEL_S 6 @@ -6023,7 +6612,7 @@ /* GPIO_FUNC141_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC141_IN_SEL 0x0000003F +#define GPIO_FUNC141_IN_SEL 0x0000003F #define GPIO_FUNC141_IN_SEL_M ((GPIO_FUNC141_IN_SEL_V)<<(GPIO_FUNC141_IN_SEL_S)) #define GPIO_FUNC141_IN_SEL_V 0x3F #define GPIO_FUNC141_IN_SEL_S 0 @@ -6031,18 +6620,21 @@ #define GPIO_FUNC142_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0368) /* GPIO_SIG142_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG142_IN_SEL (BIT(7)) +#define GPIO_SIG142_IN_SEL (BIT(7)) #define GPIO_SIG142_IN_SEL_M (BIT(7)) #define GPIO_SIG142_IN_SEL_V 0x1 #define GPIO_SIG142_IN_SEL_S 7 /* GPIO_FUNC142_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC142_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC142_IN_INV_SEL (BIT(6)) #define GPIO_FUNC142_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC142_IN_INV_SEL_V 0x1 #define GPIO_FUNC142_IN_INV_SEL_S 6 @@ -6050,7 +6642,7 @@ /* GPIO_FUNC142_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC142_IN_SEL 0x0000003F +#define GPIO_FUNC142_IN_SEL 0x0000003F #define GPIO_FUNC142_IN_SEL_M ((GPIO_FUNC142_IN_SEL_V)<<(GPIO_FUNC142_IN_SEL_S)) #define GPIO_FUNC142_IN_SEL_V 0x3F #define GPIO_FUNC142_IN_SEL_S 0 @@ -6058,18 +6650,21 @@ #define GPIO_FUNC143_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x036c) /* GPIO_SIG143_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG143_IN_SEL (BIT(7)) +#define GPIO_SIG143_IN_SEL (BIT(7)) #define GPIO_SIG143_IN_SEL_M (BIT(7)) #define GPIO_SIG143_IN_SEL_V 0x1 #define GPIO_SIG143_IN_SEL_S 7 /* GPIO_FUNC143_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC143_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC143_IN_INV_SEL (BIT(6)) #define GPIO_FUNC143_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC143_IN_INV_SEL_V 0x1 #define GPIO_FUNC143_IN_INV_SEL_S 6 @@ -6077,7 +6672,7 @@ /* GPIO_FUNC143_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC143_IN_SEL 0x0000003F +#define GPIO_FUNC143_IN_SEL 0x0000003F #define GPIO_FUNC143_IN_SEL_M ((GPIO_FUNC143_IN_SEL_V)<<(GPIO_FUNC143_IN_SEL_S)) #define GPIO_FUNC143_IN_SEL_V 0x3F #define GPIO_FUNC143_IN_SEL_S 0 @@ -6085,18 +6680,21 @@ #define GPIO_FUNC144_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0370) /* GPIO_SIG144_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG144_IN_SEL (BIT(7)) +#define GPIO_SIG144_IN_SEL (BIT(7)) #define GPIO_SIG144_IN_SEL_M (BIT(7)) #define GPIO_SIG144_IN_SEL_V 0x1 #define GPIO_SIG144_IN_SEL_S 7 /* GPIO_FUNC144_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC144_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC144_IN_INV_SEL (BIT(6)) #define GPIO_FUNC144_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC144_IN_INV_SEL_V 0x1 #define GPIO_FUNC144_IN_INV_SEL_S 6 @@ -6104,7 +6702,7 @@ /* GPIO_FUNC144_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC144_IN_SEL 0x0000003F +#define GPIO_FUNC144_IN_SEL 0x0000003F #define GPIO_FUNC144_IN_SEL_M ((GPIO_FUNC144_IN_SEL_V)<<(GPIO_FUNC144_IN_SEL_S)) #define GPIO_FUNC144_IN_SEL_V 0x3F #define GPIO_FUNC144_IN_SEL_S 0 @@ -6112,18 +6710,21 @@ #define GPIO_FUNC145_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0374) /* GPIO_SIG145_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG145_IN_SEL (BIT(7)) +#define GPIO_SIG145_IN_SEL (BIT(7)) #define GPIO_SIG145_IN_SEL_M (BIT(7)) #define GPIO_SIG145_IN_SEL_V 0x1 #define GPIO_SIG145_IN_SEL_S 7 /* GPIO_FUNC145_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC145_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC145_IN_INV_SEL (BIT(6)) #define GPIO_FUNC145_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC145_IN_INV_SEL_V 0x1 #define GPIO_FUNC145_IN_INV_SEL_S 6 @@ -6131,7 +6732,7 @@ /* GPIO_FUNC145_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC145_IN_SEL 0x0000003F +#define GPIO_FUNC145_IN_SEL 0x0000003F #define GPIO_FUNC145_IN_SEL_M ((GPIO_FUNC145_IN_SEL_V)<<(GPIO_FUNC145_IN_SEL_S)) #define GPIO_FUNC145_IN_SEL_V 0x3F #define GPIO_FUNC145_IN_SEL_S 0 @@ -6139,18 +6740,21 @@ #define GPIO_FUNC146_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0378) /* GPIO_SIG146_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG146_IN_SEL (BIT(7)) +#define GPIO_SIG146_IN_SEL (BIT(7)) #define GPIO_SIG146_IN_SEL_M (BIT(7)) #define GPIO_SIG146_IN_SEL_V 0x1 #define GPIO_SIG146_IN_SEL_S 7 /* GPIO_FUNC146_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC146_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC146_IN_INV_SEL (BIT(6)) #define GPIO_FUNC146_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC146_IN_INV_SEL_V 0x1 #define GPIO_FUNC146_IN_INV_SEL_S 6 @@ -6158,7 +6762,7 @@ /* GPIO_FUNC146_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC146_IN_SEL 0x0000003F +#define GPIO_FUNC146_IN_SEL 0x0000003F #define GPIO_FUNC146_IN_SEL_M ((GPIO_FUNC146_IN_SEL_V)<<(GPIO_FUNC146_IN_SEL_S)) #define GPIO_FUNC146_IN_SEL_V 0x3F #define GPIO_FUNC146_IN_SEL_S 0 @@ -6166,18 +6770,21 @@ #define GPIO_FUNC147_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x037c) /* GPIO_SIG147_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG147_IN_SEL (BIT(7)) +#define GPIO_SIG147_IN_SEL (BIT(7)) #define GPIO_SIG147_IN_SEL_M (BIT(7)) #define GPIO_SIG147_IN_SEL_V 0x1 #define GPIO_SIG147_IN_SEL_S 7 /* GPIO_FUNC147_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC147_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC147_IN_INV_SEL (BIT(6)) #define GPIO_FUNC147_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC147_IN_INV_SEL_V 0x1 #define GPIO_FUNC147_IN_INV_SEL_S 6 @@ -6185,7 +6792,7 @@ /* GPIO_FUNC147_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC147_IN_SEL 0x0000003F +#define GPIO_FUNC147_IN_SEL 0x0000003F #define GPIO_FUNC147_IN_SEL_M ((GPIO_FUNC147_IN_SEL_V)<<(GPIO_FUNC147_IN_SEL_S)) #define GPIO_FUNC147_IN_SEL_V 0x3F #define GPIO_FUNC147_IN_SEL_S 0 @@ -6193,18 +6800,21 @@ #define GPIO_FUNC148_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0380) /* GPIO_SIG148_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG148_IN_SEL (BIT(7)) +#define GPIO_SIG148_IN_SEL (BIT(7)) #define GPIO_SIG148_IN_SEL_M (BIT(7)) #define GPIO_SIG148_IN_SEL_V 0x1 #define GPIO_SIG148_IN_SEL_S 7 /* GPIO_FUNC148_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC148_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC148_IN_INV_SEL (BIT(6)) #define GPIO_FUNC148_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC148_IN_INV_SEL_V 0x1 #define GPIO_FUNC148_IN_INV_SEL_S 6 @@ -6212,7 +6822,7 @@ /* GPIO_FUNC148_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC148_IN_SEL 0x0000003F +#define GPIO_FUNC148_IN_SEL 0x0000003F #define GPIO_FUNC148_IN_SEL_M ((GPIO_FUNC148_IN_SEL_V)<<(GPIO_FUNC148_IN_SEL_S)) #define GPIO_FUNC148_IN_SEL_V 0x3F #define GPIO_FUNC148_IN_SEL_S 0 @@ -6220,18 +6830,21 @@ #define GPIO_FUNC149_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0384) /* GPIO_SIG149_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG149_IN_SEL (BIT(7)) +#define GPIO_SIG149_IN_SEL (BIT(7)) #define GPIO_SIG149_IN_SEL_M (BIT(7)) #define GPIO_SIG149_IN_SEL_V 0x1 #define GPIO_SIG149_IN_SEL_S 7 /* GPIO_FUNC149_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC149_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC149_IN_INV_SEL (BIT(6)) #define GPIO_FUNC149_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC149_IN_INV_SEL_V 0x1 #define GPIO_FUNC149_IN_INV_SEL_S 6 @@ -6239,7 +6852,7 @@ /* GPIO_FUNC149_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC149_IN_SEL 0x0000003F +#define GPIO_FUNC149_IN_SEL 0x0000003F #define GPIO_FUNC149_IN_SEL_M ((GPIO_FUNC149_IN_SEL_V)<<(GPIO_FUNC149_IN_SEL_S)) #define GPIO_FUNC149_IN_SEL_V 0x3F #define GPIO_FUNC149_IN_SEL_S 0 @@ -6247,18 +6860,21 @@ #define GPIO_FUNC150_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0388) /* GPIO_SIG150_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG150_IN_SEL (BIT(7)) +#define GPIO_SIG150_IN_SEL (BIT(7)) #define GPIO_SIG150_IN_SEL_M (BIT(7)) #define GPIO_SIG150_IN_SEL_V 0x1 #define GPIO_SIG150_IN_SEL_S 7 /* GPIO_FUNC150_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC150_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC150_IN_INV_SEL (BIT(6)) #define GPIO_FUNC150_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC150_IN_INV_SEL_V 0x1 #define GPIO_FUNC150_IN_INV_SEL_S 6 @@ -6266,7 +6882,7 @@ /* GPIO_FUNC150_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC150_IN_SEL 0x0000003F +#define GPIO_FUNC150_IN_SEL 0x0000003F #define GPIO_FUNC150_IN_SEL_M ((GPIO_FUNC150_IN_SEL_V)<<(GPIO_FUNC150_IN_SEL_S)) #define GPIO_FUNC150_IN_SEL_V 0x3F #define GPIO_FUNC150_IN_SEL_S 0 @@ -6274,18 +6890,21 @@ #define GPIO_FUNC151_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x038c) /* GPIO_SIG151_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG151_IN_SEL (BIT(7)) +#define GPIO_SIG151_IN_SEL (BIT(7)) #define GPIO_SIG151_IN_SEL_M (BIT(7)) #define GPIO_SIG151_IN_SEL_V 0x1 #define GPIO_SIG151_IN_SEL_S 7 /* GPIO_FUNC151_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC151_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC151_IN_INV_SEL (BIT(6)) #define GPIO_FUNC151_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC151_IN_INV_SEL_V 0x1 #define GPIO_FUNC151_IN_INV_SEL_S 6 @@ -6293,7 +6912,7 @@ /* GPIO_FUNC151_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC151_IN_SEL 0x0000003F +#define GPIO_FUNC151_IN_SEL 0x0000003F #define GPIO_FUNC151_IN_SEL_M ((GPIO_FUNC151_IN_SEL_V)<<(GPIO_FUNC151_IN_SEL_S)) #define GPIO_FUNC151_IN_SEL_V 0x3F #define GPIO_FUNC151_IN_SEL_S 0 @@ -6301,18 +6920,21 @@ #define GPIO_FUNC152_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0390) /* GPIO_SIG152_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG152_IN_SEL (BIT(7)) +#define GPIO_SIG152_IN_SEL (BIT(7)) #define GPIO_SIG152_IN_SEL_M (BIT(7)) #define GPIO_SIG152_IN_SEL_V 0x1 #define GPIO_SIG152_IN_SEL_S 7 /* GPIO_FUNC152_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC152_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC152_IN_INV_SEL (BIT(6)) #define GPIO_FUNC152_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC152_IN_INV_SEL_V 0x1 #define GPIO_FUNC152_IN_INV_SEL_S 6 @@ -6320,7 +6942,7 @@ /* GPIO_FUNC152_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC152_IN_SEL 0x0000003F +#define GPIO_FUNC152_IN_SEL 0x0000003F #define GPIO_FUNC152_IN_SEL_M ((GPIO_FUNC152_IN_SEL_V)<<(GPIO_FUNC152_IN_SEL_S)) #define GPIO_FUNC152_IN_SEL_V 0x3F #define GPIO_FUNC152_IN_SEL_S 0 @@ -6328,18 +6950,21 @@ #define GPIO_FUNC153_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0394) /* GPIO_SIG153_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG153_IN_SEL (BIT(7)) +#define GPIO_SIG153_IN_SEL (BIT(7)) #define GPIO_SIG153_IN_SEL_M (BIT(7)) #define GPIO_SIG153_IN_SEL_V 0x1 #define GPIO_SIG153_IN_SEL_S 7 /* GPIO_FUNC153_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC153_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC153_IN_INV_SEL (BIT(6)) #define GPIO_FUNC153_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC153_IN_INV_SEL_V 0x1 #define GPIO_FUNC153_IN_INV_SEL_S 6 @@ -6347,7 +6972,7 @@ /* GPIO_FUNC153_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC153_IN_SEL 0x0000003F +#define GPIO_FUNC153_IN_SEL 0x0000003F #define GPIO_FUNC153_IN_SEL_M ((GPIO_FUNC153_IN_SEL_V)<<(GPIO_FUNC153_IN_SEL_S)) #define GPIO_FUNC153_IN_SEL_V 0x3F #define GPIO_FUNC153_IN_SEL_S 0 @@ -6355,18 +6980,21 @@ #define GPIO_FUNC154_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0398) /* GPIO_SIG154_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG154_IN_SEL (BIT(7)) +#define GPIO_SIG154_IN_SEL (BIT(7)) #define GPIO_SIG154_IN_SEL_M (BIT(7)) #define GPIO_SIG154_IN_SEL_V 0x1 #define GPIO_SIG154_IN_SEL_S 7 /* GPIO_FUNC154_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC154_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC154_IN_INV_SEL (BIT(6)) #define GPIO_FUNC154_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC154_IN_INV_SEL_V 0x1 #define GPIO_FUNC154_IN_INV_SEL_S 6 @@ -6374,7 +7002,7 @@ /* GPIO_FUNC154_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC154_IN_SEL 0x0000003F +#define GPIO_FUNC154_IN_SEL 0x0000003F #define GPIO_FUNC154_IN_SEL_M ((GPIO_FUNC154_IN_SEL_V)<<(GPIO_FUNC154_IN_SEL_S)) #define GPIO_FUNC154_IN_SEL_V 0x3F #define GPIO_FUNC154_IN_SEL_S 0 @@ -6382,18 +7010,21 @@ #define GPIO_FUNC155_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x039c) /* GPIO_SIG155_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG155_IN_SEL (BIT(7)) +#define GPIO_SIG155_IN_SEL (BIT(7)) #define GPIO_SIG155_IN_SEL_M (BIT(7)) #define GPIO_SIG155_IN_SEL_V 0x1 #define GPIO_SIG155_IN_SEL_S 7 /* GPIO_FUNC155_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC155_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC155_IN_INV_SEL (BIT(6)) #define GPIO_FUNC155_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC155_IN_INV_SEL_V 0x1 #define GPIO_FUNC155_IN_INV_SEL_S 6 @@ -6401,7 +7032,7 @@ /* GPIO_FUNC155_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC155_IN_SEL 0x0000003F +#define GPIO_FUNC155_IN_SEL 0x0000003F #define GPIO_FUNC155_IN_SEL_M ((GPIO_FUNC155_IN_SEL_V)<<(GPIO_FUNC155_IN_SEL_S)) #define GPIO_FUNC155_IN_SEL_V 0x3F #define GPIO_FUNC155_IN_SEL_S 0 @@ -6409,18 +7040,21 @@ #define GPIO_FUNC156_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03a0) /* GPIO_SIG156_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG156_IN_SEL (BIT(7)) +#define GPIO_SIG156_IN_SEL (BIT(7)) #define GPIO_SIG156_IN_SEL_M (BIT(7)) #define GPIO_SIG156_IN_SEL_V 0x1 #define GPIO_SIG156_IN_SEL_S 7 /* GPIO_FUNC156_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC156_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC156_IN_INV_SEL (BIT(6)) #define GPIO_FUNC156_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC156_IN_INV_SEL_V 0x1 #define GPIO_FUNC156_IN_INV_SEL_S 6 @@ -6428,7 +7062,7 @@ /* GPIO_FUNC156_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC156_IN_SEL 0x0000003F +#define GPIO_FUNC156_IN_SEL 0x0000003F #define GPIO_FUNC156_IN_SEL_M ((GPIO_FUNC156_IN_SEL_V)<<(GPIO_FUNC156_IN_SEL_S)) #define GPIO_FUNC156_IN_SEL_V 0x3F #define GPIO_FUNC156_IN_SEL_S 0 @@ -6436,18 +7070,21 @@ #define GPIO_FUNC157_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03a4) /* GPIO_SIG157_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG157_IN_SEL (BIT(7)) +#define GPIO_SIG157_IN_SEL (BIT(7)) #define GPIO_SIG157_IN_SEL_M (BIT(7)) #define GPIO_SIG157_IN_SEL_V 0x1 #define GPIO_SIG157_IN_SEL_S 7 /* GPIO_FUNC157_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC157_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC157_IN_INV_SEL (BIT(6)) #define GPIO_FUNC157_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC157_IN_INV_SEL_V 0x1 #define GPIO_FUNC157_IN_INV_SEL_S 6 @@ -6455,7 +7092,7 @@ /* GPIO_FUNC157_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC157_IN_SEL 0x0000003F +#define GPIO_FUNC157_IN_SEL 0x0000003F #define GPIO_FUNC157_IN_SEL_M ((GPIO_FUNC157_IN_SEL_V)<<(GPIO_FUNC157_IN_SEL_S)) #define GPIO_FUNC157_IN_SEL_V 0x3F #define GPIO_FUNC157_IN_SEL_S 0 @@ -6463,18 +7100,21 @@ #define GPIO_FUNC158_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03a8) /* GPIO_SIG158_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG158_IN_SEL (BIT(7)) +#define GPIO_SIG158_IN_SEL (BIT(7)) #define GPIO_SIG158_IN_SEL_M (BIT(7)) #define GPIO_SIG158_IN_SEL_V 0x1 #define GPIO_SIG158_IN_SEL_S 7 /* GPIO_FUNC158_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC158_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC158_IN_INV_SEL (BIT(6)) #define GPIO_FUNC158_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC158_IN_INV_SEL_V 0x1 #define GPIO_FUNC158_IN_INV_SEL_S 6 @@ -6482,7 +7122,7 @@ /* GPIO_FUNC158_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC158_IN_SEL 0x0000003F +#define GPIO_FUNC158_IN_SEL 0x0000003F #define GPIO_FUNC158_IN_SEL_M ((GPIO_FUNC158_IN_SEL_V)<<(GPIO_FUNC158_IN_SEL_S)) #define GPIO_FUNC158_IN_SEL_V 0x3F #define GPIO_FUNC158_IN_SEL_S 0 @@ -6490,18 +7130,21 @@ #define GPIO_FUNC159_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03ac) /* GPIO_SIG159_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG159_IN_SEL (BIT(7)) +#define GPIO_SIG159_IN_SEL (BIT(7)) #define GPIO_SIG159_IN_SEL_M (BIT(7)) #define GPIO_SIG159_IN_SEL_V 0x1 #define GPIO_SIG159_IN_SEL_S 7 /* GPIO_FUNC159_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC159_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC159_IN_INV_SEL (BIT(6)) #define GPIO_FUNC159_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC159_IN_INV_SEL_V 0x1 #define GPIO_FUNC159_IN_INV_SEL_S 6 @@ -6509,7 +7152,7 @@ /* GPIO_FUNC159_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC159_IN_SEL 0x0000003F +#define GPIO_FUNC159_IN_SEL 0x0000003F #define GPIO_FUNC159_IN_SEL_M ((GPIO_FUNC159_IN_SEL_V)<<(GPIO_FUNC159_IN_SEL_S)) #define GPIO_FUNC159_IN_SEL_V 0x3F #define GPIO_FUNC159_IN_SEL_S 0 @@ -6517,18 +7160,21 @@ #define GPIO_FUNC160_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03b0) /* GPIO_SIG160_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG160_IN_SEL (BIT(7)) +#define GPIO_SIG160_IN_SEL (BIT(7)) #define GPIO_SIG160_IN_SEL_M (BIT(7)) #define GPIO_SIG160_IN_SEL_V 0x1 #define GPIO_SIG160_IN_SEL_S 7 /* GPIO_FUNC160_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC160_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC160_IN_INV_SEL (BIT(6)) #define GPIO_FUNC160_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC160_IN_INV_SEL_V 0x1 #define GPIO_FUNC160_IN_INV_SEL_S 6 @@ -6536,7 +7182,7 @@ /* GPIO_FUNC160_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC160_IN_SEL 0x0000003F +#define GPIO_FUNC160_IN_SEL 0x0000003F #define GPIO_FUNC160_IN_SEL_M ((GPIO_FUNC160_IN_SEL_V)<<(GPIO_FUNC160_IN_SEL_S)) #define GPIO_FUNC160_IN_SEL_V 0x3F #define GPIO_FUNC160_IN_SEL_S 0 @@ -6544,18 +7190,21 @@ #define GPIO_FUNC161_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03b4) /* GPIO_SIG161_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG161_IN_SEL (BIT(7)) +#define GPIO_SIG161_IN_SEL (BIT(7)) #define GPIO_SIG161_IN_SEL_M (BIT(7)) #define GPIO_SIG161_IN_SEL_V 0x1 #define GPIO_SIG161_IN_SEL_S 7 /* GPIO_FUNC161_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC161_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC161_IN_INV_SEL (BIT(6)) #define GPIO_FUNC161_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC161_IN_INV_SEL_V 0x1 #define GPIO_FUNC161_IN_INV_SEL_S 6 @@ -6563,7 +7212,7 @@ /* GPIO_FUNC161_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC161_IN_SEL 0x0000003F +#define GPIO_FUNC161_IN_SEL 0x0000003F #define GPIO_FUNC161_IN_SEL_M ((GPIO_FUNC161_IN_SEL_V)<<(GPIO_FUNC161_IN_SEL_S)) #define GPIO_FUNC161_IN_SEL_V 0x3F #define GPIO_FUNC161_IN_SEL_S 0 @@ -6571,18 +7220,21 @@ #define GPIO_FUNC162_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03b8) /* GPIO_SIG162_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG162_IN_SEL (BIT(7)) +#define GPIO_SIG162_IN_SEL (BIT(7)) #define GPIO_SIG162_IN_SEL_M (BIT(7)) #define GPIO_SIG162_IN_SEL_V 0x1 #define GPIO_SIG162_IN_SEL_S 7 /* GPIO_FUNC162_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC162_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC162_IN_INV_SEL (BIT(6)) #define GPIO_FUNC162_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC162_IN_INV_SEL_V 0x1 #define GPIO_FUNC162_IN_INV_SEL_S 6 @@ -6590,7 +7242,7 @@ /* GPIO_FUNC162_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC162_IN_SEL 0x0000003F +#define GPIO_FUNC162_IN_SEL 0x0000003F #define GPIO_FUNC162_IN_SEL_M ((GPIO_FUNC162_IN_SEL_V)<<(GPIO_FUNC162_IN_SEL_S)) #define GPIO_FUNC162_IN_SEL_V 0x3F #define GPIO_FUNC162_IN_SEL_S 0 @@ -6598,18 +7250,21 @@ #define GPIO_FUNC163_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03bc) /* GPIO_SIG163_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG163_IN_SEL (BIT(7)) +#define GPIO_SIG163_IN_SEL (BIT(7)) #define GPIO_SIG163_IN_SEL_M (BIT(7)) #define GPIO_SIG163_IN_SEL_V 0x1 #define GPIO_SIG163_IN_SEL_S 7 /* GPIO_FUNC163_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC163_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC163_IN_INV_SEL (BIT(6)) #define GPIO_FUNC163_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC163_IN_INV_SEL_V 0x1 #define GPIO_FUNC163_IN_INV_SEL_S 6 @@ -6617,7 +7272,7 @@ /* GPIO_FUNC163_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC163_IN_SEL 0x0000003F +#define GPIO_FUNC163_IN_SEL 0x0000003F #define GPIO_FUNC163_IN_SEL_M ((GPIO_FUNC163_IN_SEL_V)<<(GPIO_FUNC163_IN_SEL_S)) #define GPIO_FUNC163_IN_SEL_V 0x3F #define GPIO_FUNC163_IN_SEL_S 0 @@ -6625,18 +7280,21 @@ #define GPIO_FUNC164_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03c0) /* GPIO_SIG164_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG164_IN_SEL (BIT(7)) +#define GPIO_SIG164_IN_SEL (BIT(7)) #define GPIO_SIG164_IN_SEL_M (BIT(7)) #define GPIO_SIG164_IN_SEL_V 0x1 #define GPIO_SIG164_IN_SEL_S 7 /* GPIO_FUNC164_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC164_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC164_IN_INV_SEL (BIT(6)) #define GPIO_FUNC164_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC164_IN_INV_SEL_V 0x1 #define GPIO_FUNC164_IN_INV_SEL_S 6 @@ -6644,7 +7302,7 @@ /* GPIO_FUNC164_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC164_IN_SEL 0x0000003F +#define GPIO_FUNC164_IN_SEL 0x0000003F #define GPIO_FUNC164_IN_SEL_M ((GPIO_FUNC164_IN_SEL_V)<<(GPIO_FUNC164_IN_SEL_S)) #define GPIO_FUNC164_IN_SEL_V 0x3F #define GPIO_FUNC164_IN_SEL_S 0 @@ -6652,18 +7310,21 @@ #define GPIO_FUNC165_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03c4) /* GPIO_SIG165_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG165_IN_SEL (BIT(7)) +#define GPIO_SIG165_IN_SEL (BIT(7)) #define GPIO_SIG165_IN_SEL_M (BIT(7)) #define GPIO_SIG165_IN_SEL_V 0x1 #define GPIO_SIG165_IN_SEL_S 7 /* GPIO_FUNC165_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC165_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC165_IN_INV_SEL (BIT(6)) #define GPIO_FUNC165_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC165_IN_INV_SEL_V 0x1 #define GPIO_FUNC165_IN_INV_SEL_S 6 @@ -6671,7 +7332,7 @@ /* GPIO_FUNC165_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC165_IN_SEL 0x0000003F +#define GPIO_FUNC165_IN_SEL 0x0000003F #define GPIO_FUNC165_IN_SEL_M ((GPIO_FUNC165_IN_SEL_V)<<(GPIO_FUNC165_IN_SEL_S)) #define GPIO_FUNC165_IN_SEL_V 0x3F #define GPIO_FUNC165_IN_SEL_S 0 @@ -6679,18 +7340,21 @@ #define GPIO_FUNC166_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03c8) /* GPIO_SIG166_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG166_IN_SEL (BIT(7)) +#define GPIO_SIG166_IN_SEL (BIT(7)) #define GPIO_SIG166_IN_SEL_M (BIT(7)) #define GPIO_SIG166_IN_SEL_V 0x1 #define GPIO_SIG166_IN_SEL_S 7 /* GPIO_FUNC166_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC166_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC166_IN_INV_SEL (BIT(6)) #define GPIO_FUNC166_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC166_IN_INV_SEL_V 0x1 #define GPIO_FUNC166_IN_INV_SEL_S 6 @@ -6698,7 +7362,7 @@ /* GPIO_FUNC166_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC166_IN_SEL 0x0000003F +#define GPIO_FUNC166_IN_SEL 0x0000003F #define GPIO_FUNC166_IN_SEL_M ((GPIO_FUNC166_IN_SEL_V)<<(GPIO_FUNC166_IN_SEL_S)) #define GPIO_FUNC166_IN_SEL_V 0x3F #define GPIO_FUNC166_IN_SEL_S 0 @@ -6706,18 +7370,21 @@ #define GPIO_FUNC167_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03cc) /* GPIO_SIG167_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG167_IN_SEL (BIT(7)) +#define GPIO_SIG167_IN_SEL (BIT(7)) #define GPIO_SIG167_IN_SEL_M (BIT(7)) #define GPIO_SIG167_IN_SEL_V 0x1 #define GPIO_SIG167_IN_SEL_S 7 /* GPIO_FUNC167_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC167_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC167_IN_INV_SEL (BIT(6)) #define GPIO_FUNC167_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC167_IN_INV_SEL_V 0x1 #define GPIO_FUNC167_IN_INV_SEL_S 6 @@ -6725,7 +7392,7 @@ /* GPIO_FUNC167_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC167_IN_SEL 0x0000003F +#define GPIO_FUNC167_IN_SEL 0x0000003F #define GPIO_FUNC167_IN_SEL_M ((GPIO_FUNC167_IN_SEL_V)<<(GPIO_FUNC167_IN_SEL_S)) #define GPIO_FUNC167_IN_SEL_V 0x3F #define GPIO_FUNC167_IN_SEL_S 0 @@ -6733,18 +7400,21 @@ #define GPIO_FUNC168_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03d0) /* GPIO_SIG168_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG168_IN_SEL (BIT(7)) +#define GPIO_SIG168_IN_SEL (BIT(7)) #define GPIO_SIG168_IN_SEL_M (BIT(7)) #define GPIO_SIG168_IN_SEL_V 0x1 #define GPIO_SIG168_IN_SEL_S 7 /* GPIO_FUNC168_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC168_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC168_IN_INV_SEL (BIT(6)) #define GPIO_FUNC168_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC168_IN_INV_SEL_V 0x1 #define GPIO_FUNC168_IN_INV_SEL_S 6 @@ -6752,7 +7422,7 @@ /* GPIO_FUNC168_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC168_IN_SEL 0x0000003F +#define GPIO_FUNC168_IN_SEL 0x0000003F #define GPIO_FUNC168_IN_SEL_M ((GPIO_FUNC168_IN_SEL_V)<<(GPIO_FUNC168_IN_SEL_S)) #define GPIO_FUNC168_IN_SEL_V 0x3F #define GPIO_FUNC168_IN_SEL_S 0 @@ -6760,18 +7430,21 @@ #define GPIO_FUNC169_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03d4) /* GPIO_SIG169_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG169_IN_SEL (BIT(7)) +#define GPIO_SIG169_IN_SEL (BIT(7)) #define GPIO_SIG169_IN_SEL_M (BIT(7)) #define GPIO_SIG169_IN_SEL_V 0x1 #define GPIO_SIG169_IN_SEL_S 7 /* GPIO_FUNC169_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC169_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC169_IN_INV_SEL (BIT(6)) #define GPIO_FUNC169_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC169_IN_INV_SEL_V 0x1 #define GPIO_FUNC169_IN_INV_SEL_S 6 @@ -6779,7 +7452,7 @@ /* GPIO_FUNC169_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC169_IN_SEL 0x0000003F +#define GPIO_FUNC169_IN_SEL 0x0000003F #define GPIO_FUNC169_IN_SEL_M ((GPIO_FUNC169_IN_SEL_V)<<(GPIO_FUNC169_IN_SEL_S)) #define GPIO_FUNC169_IN_SEL_V 0x3F #define GPIO_FUNC169_IN_SEL_S 0 @@ -6787,18 +7460,21 @@ #define GPIO_FUNC170_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03d8) /* GPIO_SIG170_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG170_IN_SEL (BIT(7)) +#define GPIO_SIG170_IN_SEL (BIT(7)) #define GPIO_SIG170_IN_SEL_M (BIT(7)) #define GPIO_SIG170_IN_SEL_V 0x1 #define GPIO_SIG170_IN_SEL_S 7 /* GPIO_FUNC170_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC170_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC170_IN_INV_SEL (BIT(6)) #define GPIO_FUNC170_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC170_IN_INV_SEL_V 0x1 #define GPIO_FUNC170_IN_INV_SEL_S 6 @@ -6806,7 +7482,7 @@ /* GPIO_FUNC170_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC170_IN_SEL 0x0000003F +#define GPIO_FUNC170_IN_SEL 0x0000003F #define GPIO_FUNC170_IN_SEL_M ((GPIO_FUNC170_IN_SEL_V)<<(GPIO_FUNC170_IN_SEL_S)) #define GPIO_FUNC170_IN_SEL_V 0x3F #define GPIO_FUNC170_IN_SEL_S 0 @@ -6814,18 +7490,21 @@ #define GPIO_FUNC171_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03dc) /* GPIO_SIG171_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG171_IN_SEL (BIT(7)) +#define GPIO_SIG171_IN_SEL (BIT(7)) #define GPIO_SIG171_IN_SEL_M (BIT(7)) #define GPIO_SIG171_IN_SEL_V 0x1 #define GPIO_SIG171_IN_SEL_S 7 /* GPIO_FUNC171_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC171_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC171_IN_INV_SEL (BIT(6)) #define GPIO_FUNC171_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC171_IN_INV_SEL_V 0x1 #define GPIO_FUNC171_IN_INV_SEL_S 6 @@ -6833,7 +7512,7 @@ /* GPIO_FUNC171_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC171_IN_SEL 0x0000003F +#define GPIO_FUNC171_IN_SEL 0x0000003F #define GPIO_FUNC171_IN_SEL_M ((GPIO_FUNC171_IN_SEL_V)<<(GPIO_FUNC171_IN_SEL_S)) #define GPIO_FUNC171_IN_SEL_V 0x3F #define GPIO_FUNC171_IN_SEL_S 0 @@ -6841,18 +7520,21 @@ #define GPIO_FUNC172_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03e0) /* GPIO_SIG172_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG172_IN_SEL (BIT(7)) +#define GPIO_SIG172_IN_SEL (BIT(7)) #define GPIO_SIG172_IN_SEL_M (BIT(7)) #define GPIO_SIG172_IN_SEL_V 0x1 #define GPIO_SIG172_IN_SEL_S 7 /* GPIO_FUNC172_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC172_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC172_IN_INV_SEL (BIT(6)) #define GPIO_FUNC172_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC172_IN_INV_SEL_V 0x1 #define GPIO_FUNC172_IN_INV_SEL_S 6 @@ -6860,7 +7542,7 @@ /* GPIO_FUNC172_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC172_IN_SEL 0x0000003F +#define GPIO_FUNC172_IN_SEL 0x0000003F #define GPIO_FUNC172_IN_SEL_M ((GPIO_FUNC172_IN_SEL_V)<<(GPIO_FUNC172_IN_SEL_S)) #define GPIO_FUNC172_IN_SEL_V 0x3F #define GPIO_FUNC172_IN_SEL_S 0 @@ -6868,18 +7550,21 @@ #define GPIO_FUNC173_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03e4) /* GPIO_SIG173_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG173_IN_SEL (BIT(7)) +#define GPIO_SIG173_IN_SEL (BIT(7)) #define GPIO_SIG173_IN_SEL_M (BIT(7)) #define GPIO_SIG173_IN_SEL_V 0x1 #define GPIO_SIG173_IN_SEL_S 7 /* GPIO_FUNC173_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC173_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC173_IN_INV_SEL (BIT(6)) #define GPIO_FUNC173_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC173_IN_INV_SEL_V 0x1 #define GPIO_FUNC173_IN_INV_SEL_S 6 @@ -6887,7 +7572,7 @@ /* GPIO_FUNC173_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC173_IN_SEL 0x0000003F +#define GPIO_FUNC173_IN_SEL 0x0000003F #define GPIO_FUNC173_IN_SEL_M ((GPIO_FUNC173_IN_SEL_V)<<(GPIO_FUNC173_IN_SEL_S)) #define GPIO_FUNC173_IN_SEL_V 0x3F #define GPIO_FUNC173_IN_SEL_S 0 @@ -6895,18 +7580,21 @@ #define GPIO_FUNC174_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03e8) /* GPIO_SIG174_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG174_IN_SEL (BIT(7)) +#define GPIO_SIG174_IN_SEL (BIT(7)) #define GPIO_SIG174_IN_SEL_M (BIT(7)) #define GPIO_SIG174_IN_SEL_V 0x1 #define GPIO_SIG174_IN_SEL_S 7 /* GPIO_FUNC174_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC174_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC174_IN_INV_SEL (BIT(6)) #define GPIO_FUNC174_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC174_IN_INV_SEL_V 0x1 #define GPIO_FUNC174_IN_INV_SEL_S 6 @@ -6914,7 +7602,7 @@ /* GPIO_FUNC174_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC174_IN_SEL 0x0000003F +#define GPIO_FUNC174_IN_SEL 0x0000003F #define GPIO_FUNC174_IN_SEL_M ((GPIO_FUNC174_IN_SEL_V)<<(GPIO_FUNC174_IN_SEL_S)) #define GPIO_FUNC174_IN_SEL_V 0x3F #define GPIO_FUNC174_IN_SEL_S 0 @@ -6922,18 +7610,21 @@ #define GPIO_FUNC175_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03ec) /* GPIO_SIG175_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG175_IN_SEL (BIT(7)) +#define GPIO_SIG175_IN_SEL (BIT(7)) #define GPIO_SIG175_IN_SEL_M (BIT(7)) #define GPIO_SIG175_IN_SEL_V 0x1 #define GPIO_SIG175_IN_SEL_S 7 /* GPIO_FUNC175_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC175_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC175_IN_INV_SEL (BIT(6)) #define GPIO_FUNC175_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC175_IN_INV_SEL_V 0x1 #define GPIO_FUNC175_IN_INV_SEL_S 6 @@ -6941,7 +7632,7 @@ /* GPIO_FUNC175_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC175_IN_SEL 0x0000003F +#define GPIO_FUNC175_IN_SEL 0x0000003F #define GPIO_FUNC175_IN_SEL_M ((GPIO_FUNC175_IN_SEL_V)<<(GPIO_FUNC175_IN_SEL_S)) #define GPIO_FUNC175_IN_SEL_V 0x3F #define GPIO_FUNC175_IN_SEL_S 0 @@ -6949,18 +7640,21 @@ #define GPIO_FUNC176_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03f0) /* GPIO_SIG176_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG176_IN_SEL (BIT(7)) +#define GPIO_SIG176_IN_SEL (BIT(7)) #define GPIO_SIG176_IN_SEL_M (BIT(7)) #define GPIO_SIG176_IN_SEL_V 0x1 #define GPIO_SIG176_IN_SEL_S 7 /* GPIO_FUNC176_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC176_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC176_IN_INV_SEL (BIT(6)) #define GPIO_FUNC176_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC176_IN_INV_SEL_V 0x1 #define GPIO_FUNC176_IN_INV_SEL_S 6 @@ -6968,7 +7662,7 @@ /* GPIO_FUNC176_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC176_IN_SEL 0x0000003F +#define GPIO_FUNC176_IN_SEL 0x0000003F #define GPIO_FUNC176_IN_SEL_M ((GPIO_FUNC176_IN_SEL_V)<<(GPIO_FUNC176_IN_SEL_S)) #define GPIO_FUNC176_IN_SEL_V 0x3F #define GPIO_FUNC176_IN_SEL_S 0 @@ -6976,18 +7670,21 @@ #define GPIO_FUNC177_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03f4) /* GPIO_SIG177_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG177_IN_SEL (BIT(7)) +#define GPIO_SIG177_IN_SEL (BIT(7)) #define GPIO_SIG177_IN_SEL_M (BIT(7)) #define GPIO_SIG177_IN_SEL_V 0x1 #define GPIO_SIG177_IN_SEL_S 7 /* GPIO_FUNC177_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC177_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC177_IN_INV_SEL (BIT(6)) #define GPIO_FUNC177_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC177_IN_INV_SEL_V 0x1 #define GPIO_FUNC177_IN_INV_SEL_S 6 @@ -6995,7 +7692,7 @@ /* GPIO_FUNC177_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC177_IN_SEL 0x0000003F +#define GPIO_FUNC177_IN_SEL 0x0000003F #define GPIO_FUNC177_IN_SEL_M ((GPIO_FUNC177_IN_SEL_V)<<(GPIO_FUNC177_IN_SEL_S)) #define GPIO_FUNC177_IN_SEL_V 0x3F #define GPIO_FUNC177_IN_SEL_S 0 @@ -7003,18 +7700,21 @@ #define GPIO_FUNC178_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03f8) /* GPIO_SIG178_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG178_IN_SEL (BIT(7)) +#define GPIO_SIG178_IN_SEL (BIT(7)) #define GPIO_SIG178_IN_SEL_M (BIT(7)) #define GPIO_SIG178_IN_SEL_V 0x1 #define GPIO_SIG178_IN_SEL_S 7 /* GPIO_FUNC178_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC178_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC178_IN_INV_SEL (BIT(6)) #define GPIO_FUNC178_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC178_IN_INV_SEL_V 0x1 #define GPIO_FUNC178_IN_INV_SEL_S 6 @@ -7022,7 +7722,7 @@ /* GPIO_FUNC178_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC178_IN_SEL 0x0000003F +#define GPIO_FUNC178_IN_SEL 0x0000003F #define GPIO_FUNC178_IN_SEL_M ((GPIO_FUNC178_IN_SEL_V)<<(GPIO_FUNC178_IN_SEL_S)) #define GPIO_FUNC178_IN_SEL_V 0x3F #define GPIO_FUNC178_IN_SEL_S 0 @@ -7030,18 +7730,21 @@ #define GPIO_FUNC179_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x03fc) /* GPIO_SIG179_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG179_IN_SEL (BIT(7)) +#define GPIO_SIG179_IN_SEL (BIT(7)) #define GPIO_SIG179_IN_SEL_M (BIT(7)) #define GPIO_SIG179_IN_SEL_V 0x1 #define GPIO_SIG179_IN_SEL_S 7 /* GPIO_FUNC179_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC179_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC179_IN_INV_SEL (BIT(6)) #define GPIO_FUNC179_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC179_IN_INV_SEL_V 0x1 #define GPIO_FUNC179_IN_INV_SEL_S 6 @@ -7049,7 +7752,7 @@ /* GPIO_FUNC179_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC179_IN_SEL 0x0000003F +#define GPIO_FUNC179_IN_SEL 0x0000003F #define GPIO_FUNC179_IN_SEL_M ((GPIO_FUNC179_IN_SEL_V)<<(GPIO_FUNC179_IN_SEL_S)) #define GPIO_FUNC179_IN_SEL_V 0x3F #define GPIO_FUNC179_IN_SEL_S 0 @@ -7057,18 +7760,21 @@ #define GPIO_FUNC180_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0400) /* GPIO_SIG180_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG180_IN_SEL (BIT(7)) +#define GPIO_SIG180_IN_SEL (BIT(7)) #define GPIO_SIG180_IN_SEL_M (BIT(7)) #define GPIO_SIG180_IN_SEL_V 0x1 #define GPIO_SIG180_IN_SEL_S 7 /* GPIO_FUNC180_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC180_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC180_IN_INV_SEL (BIT(6)) #define GPIO_FUNC180_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC180_IN_INV_SEL_V 0x1 #define GPIO_FUNC180_IN_INV_SEL_S 6 @@ -7076,7 +7782,7 @@ /* GPIO_FUNC180_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC180_IN_SEL 0x0000003F +#define GPIO_FUNC180_IN_SEL 0x0000003F #define GPIO_FUNC180_IN_SEL_M ((GPIO_FUNC180_IN_SEL_V)<<(GPIO_FUNC180_IN_SEL_S)) #define GPIO_FUNC180_IN_SEL_V 0x3F #define GPIO_FUNC180_IN_SEL_S 0 @@ -7084,18 +7790,21 @@ #define GPIO_FUNC181_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0404) /* GPIO_SIG181_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG181_IN_SEL (BIT(7)) +#define GPIO_SIG181_IN_SEL (BIT(7)) #define GPIO_SIG181_IN_SEL_M (BIT(7)) #define GPIO_SIG181_IN_SEL_V 0x1 #define GPIO_SIG181_IN_SEL_S 7 /* GPIO_FUNC181_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC181_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC181_IN_INV_SEL (BIT(6)) #define GPIO_FUNC181_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC181_IN_INV_SEL_V 0x1 #define GPIO_FUNC181_IN_INV_SEL_S 6 @@ -7103,7 +7812,7 @@ /* GPIO_FUNC181_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC181_IN_SEL 0x0000003F +#define GPIO_FUNC181_IN_SEL 0x0000003F #define GPIO_FUNC181_IN_SEL_M ((GPIO_FUNC181_IN_SEL_V)<<(GPIO_FUNC181_IN_SEL_S)) #define GPIO_FUNC181_IN_SEL_V 0x3F #define GPIO_FUNC181_IN_SEL_S 0 @@ -7111,18 +7820,21 @@ #define GPIO_FUNC182_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0408) /* GPIO_SIG182_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG182_IN_SEL (BIT(7)) +#define GPIO_SIG182_IN_SEL (BIT(7)) #define GPIO_SIG182_IN_SEL_M (BIT(7)) #define GPIO_SIG182_IN_SEL_V 0x1 #define GPIO_SIG182_IN_SEL_S 7 /* GPIO_FUNC182_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC182_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC182_IN_INV_SEL (BIT(6)) #define GPIO_FUNC182_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC182_IN_INV_SEL_V 0x1 #define GPIO_FUNC182_IN_INV_SEL_S 6 @@ -7130,7 +7842,7 @@ /* GPIO_FUNC182_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC182_IN_SEL 0x0000003F +#define GPIO_FUNC182_IN_SEL 0x0000003F #define GPIO_FUNC182_IN_SEL_M ((GPIO_FUNC182_IN_SEL_V)<<(GPIO_FUNC182_IN_SEL_S)) #define GPIO_FUNC182_IN_SEL_V 0x3F #define GPIO_FUNC182_IN_SEL_S 0 @@ -7138,18 +7850,21 @@ #define GPIO_FUNC183_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x040c) /* GPIO_SIG183_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG183_IN_SEL (BIT(7)) +#define GPIO_SIG183_IN_SEL (BIT(7)) #define GPIO_SIG183_IN_SEL_M (BIT(7)) #define GPIO_SIG183_IN_SEL_V 0x1 #define GPIO_SIG183_IN_SEL_S 7 /* GPIO_FUNC183_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC183_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC183_IN_INV_SEL (BIT(6)) #define GPIO_FUNC183_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC183_IN_INV_SEL_V 0x1 #define GPIO_FUNC183_IN_INV_SEL_S 6 @@ -7157,7 +7872,7 @@ /* GPIO_FUNC183_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC183_IN_SEL 0x0000003F +#define GPIO_FUNC183_IN_SEL 0x0000003F #define GPIO_FUNC183_IN_SEL_M ((GPIO_FUNC183_IN_SEL_V)<<(GPIO_FUNC183_IN_SEL_S)) #define GPIO_FUNC183_IN_SEL_V 0x3F #define GPIO_FUNC183_IN_SEL_S 0 @@ -7165,18 +7880,21 @@ #define GPIO_FUNC184_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0410) /* GPIO_SIG184_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG184_IN_SEL (BIT(7)) +#define GPIO_SIG184_IN_SEL (BIT(7)) #define GPIO_SIG184_IN_SEL_M (BIT(7)) #define GPIO_SIG184_IN_SEL_V 0x1 #define GPIO_SIG184_IN_SEL_S 7 /* GPIO_FUNC184_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC184_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC184_IN_INV_SEL (BIT(6)) #define GPIO_FUNC184_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC184_IN_INV_SEL_V 0x1 #define GPIO_FUNC184_IN_INV_SEL_S 6 @@ -7184,7 +7902,7 @@ /* GPIO_FUNC184_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC184_IN_SEL 0x0000003F +#define GPIO_FUNC184_IN_SEL 0x0000003F #define GPIO_FUNC184_IN_SEL_M ((GPIO_FUNC184_IN_SEL_V)<<(GPIO_FUNC184_IN_SEL_S)) #define GPIO_FUNC184_IN_SEL_V 0x3F #define GPIO_FUNC184_IN_SEL_S 0 @@ -7192,18 +7910,21 @@ #define GPIO_FUNC185_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0414) /* GPIO_SIG185_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG185_IN_SEL (BIT(7)) +#define GPIO_SIG185_IN_SEL (BIT(7)) #define GPIO_SIG185_IN_SEL_M (BIT(7)) #define GPIO_SIG185_IN_SEL_V 0x1 #define GPIO_SIG185_IN_SEL_S 7 /* GPIO_FUNC185_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC185_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC185_IN_INV_SEL (BIT(6)) #define GPIO_FUNC185_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC185_IN_INV_SEL_V 0x1 #define GPIO_FUNC185_IN_INV_SEL_S 6 @@ -7211,7 +7932,7 @@ /* GPIO_FUNC185_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC185_IN_SEL 0x0000003F +#define GPIO_FUNC185_IN_SEL 0x0000003F #define GPIO_FUNC185_IN_SEL_M ((GPIO_FUNC185_IN_SEL_V)<<(GPIO_FUNC185_IN_SEL_S)) #define GPIO_FUNC185_IN_SEL_V 0x3F #define GPIO_FUNC185_IN_SEL_S 0 @@ -7219,18 +7940,21 @@ #define GPIO_FUNC186_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0418) /* GPIO_SIG186_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG186_IN_SEL (BIT(7)) +#define GPIO_SIG186_IN_SEL (BIT(7)) #define GPIO_SIG186_IN_SEL_M (BIT(7)) #define GPIO_SIG186_IN_SEL_V 0x1 #define GPIO_SIG186_IN_SEL_S 7 /* GPIO_FUNC186_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC186_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC186_IN_INV_SEL (BIT(6)) #define GPIO_FUNC186_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC186_IN_INV_SEL_V 0x1 #define GPIO_FUNC186_IN_INV_SEL_S 6 @@ -7238,7 +7962,7 @@ /* GPIO_FUNC186_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC186_IN_SEL 0x0000003F +#define GPIO_FUNC186_IN_SEL 0x0000003F #define GPIO_FUNC186_IN_SEL_M ((GPIO_FUNC186_IN_SEL_V)<<(GPIO_FUNC186_IN_SEL_S)) #define GPIO_FUNC186_IN_SEL_V 0x3F #define GPIO_FUNC186_IN_SEL_S 0 @@ -7246,18 +7970,21 @@ #define GPIO_FUNC187_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x041c) /* GPIO_SIG187_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG187_IN_SEL (BIT(7)) +#define GPIO_SIG187_IN_SEL (BIT(7)) #define GPIO_SIG187_IN_SEL_M (BIT(7)) #define GPIO_SIG187_IN_SEL_V 0x1 #define GPIO_SIG187_IN_SEL_S 7 /* GPIO_FUNC187_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC187_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC187_IN_INV_SEL (BIT(6)) #define GPIO_FUNC187_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC187_IN_INV_SEL_V 0x1 #define GPIO_FUNC187_IN_INV_SEL_S 6 @@ -7265,7 +7992,7 @@ /* GPIO_FUNC187_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC187_IN_SEL 0x0000003F +#define GPIO_FUNC187_IN_SEL 0x0000003F #define GPIO_FUNC187_IN_SEL_M ((GPIO_FUNC187_IN_SEL_V)<<(GPIO_FUNC187_IN_SEL_S)) #define GPIO_FUNC187_IN_SEL_V 0x3F #define GPIO_FUNC187_IN_SEL_S 0 @@ -7273,18 +8000,21 @@ #define GPIO_FUNC188_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0420) /* GPIO_SIG188_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG188_IN_SEL (BIT(7)) +#define GPIO_SIG188_IN_SEL (BIT(7)) #define GPIO_SIG188_IN_SEL_M (BIT(7)) #define GPIO_SIG188_IN_SEL_V 0x1 #define GPIO_SIG188_IN_SEL_S 7 /* GPIO_FUNC188_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC188_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC188_IN_INV_SEL (BIT(6)) #define GPIO_FUNC188_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC188_IN_INV_SEL_V 0x1 #define GPIO_FUNC188_IN_INV_SEL_S 6 @@ -7292,7 +8022,7 @@ /* GPIO_FUNC188_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC188_IN_SEL 0x0000003F +#define GPIO_FUNC188_IN_SEL 0x0000003F #define GPIO_FUNC188_IN_SEL_M ((GPIO_FUNC188_IN_SEL_V)<<(GPIO_FUNC188_IN_SEL_S)) #define GPIO_FUNC188_IN_SEL_V 0x3F #define GPIO_FUNC188_IN_SEL_S 0 @@ -7300,18 +8030,21 @@ #define GPIO_FUNC189_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0424) /* GPIO_SIG189_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG189_IN_SEL (BIT(7)) +#define GPIO_SIG189_IN_SEL (BIT(7)) #define GPIO_SIG189_IN_SEL_M (BIT(7)) #define GPIO_SIG189_IN_SEL_V 0x1 #define GPIO_SIG189_IN_SEL_S 7 /* GPIO_FUNC189_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC189_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC189_IN_INV_SEL (BIT(6)) #define GPIO_FUNC189_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC189_IN_INV_SEL_V 0x1 #define GPIO_FUNC189_IN_INV_SEL_S 6 @@ -7319,7 +8052,7 @@ /* GPIO_FUNC189_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC189_IN_SEL 0x0000003F +#define GPIO_FUNC189_IN_SEL 0x0000003F #define GPIO_FUNC189_IN_SEL_M ((GPIO_FUNC189_IN_SEL_V)<<(GPIO_FUNC189_IN_SEL_S)) #define GPIO_FUNC189_IN_SEL_V 0x3F #define GPIO_FUNC189_IN_SEL_S 0 @@ -7327,18 +8060,21 @@ #define GPIO_FUNC190_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0428) /* GPIO_SIG190_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG190_IN_SEL (BIT(7)) +#define GPIO_SIG190_IN_SEL (BIT(7)) #define GPIO_SIG190_IN_SEL_M (BIT(7)) #define GPIO_SIG190_IN_SEL_V 0x1 #define GPIO_SIG190_IN_SEL_S 7 /* GPIO_FUNC190_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC190_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC190_IN_INV_SEL (BIT(6)) #define GPIO_FUNC190_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC190_IN_INV_SEL_V 0x1 #define GPIO_FUNC190_IN_INV_SEL_S 6 @@ -7346,7 +8082,7 @@ /* GPIO_FUNC190_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC190_IN_SEL 0x0000003F +#define GPIO_FUNC190_IN_SEL 0x0000003F #define GPIO_FUNC190_IN_SEL_M ((GPIO_FUNC190_IN_SEL_V)<<(GPIO_FUNC190_IN_SEL_S)) #define GPIO_FUNC190_IN_SEL_V 0x3F #define GPIO_FUNC190_IN_SEL_S 0 @@ -7354,18 +8090,21 @@ #define GPIO_FUNC191_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x042c) /* GPIO_SIG191_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG191_IN_SEL (BIT(7)) +#define GPIO_SIG191_IN_SEL (BIT(7)) #define GPIO_SIG191_IN_SEL_M (BIT(7)) #define GPIO_SIG191_IN_SEL_V 0x1 #define GPIO_SIG191_IN_SEL_S 7 /* GPIO_FUNC191_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC191_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC191_IN_INV_SEL (BIT(6)) #define GPIO_FUNC191_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC191_IN_INV_SEL_V 0x1 #define GPIO_FUNC191_IN_INV_SEL_S 6 @@ -7373,7 +8112,7 @@ /* GPIO_FUNC191_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC191_IN_SEL 0x0000003F +#define GPIO_FUNC191_IN_SEL 0x0000003F #define GPIO_FUNC191_IN_SEL_M ((GPIO_FUNC191_IN_SEL_V)<<(GPIO_FUNC191_IN_SEL_S)) #define GPIO_FUNC191_IN_SEL_V 0x3F #define GPIO_FUNC191_IN_SEL_S 0 @@ -7381,18 +8120,21 @@ #define GPIO_FUNC192_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0430) /* GPIO_SIG192_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG192_IN_SEL (BIT(7)) +#define GPIO_SIG192_IN_SEL (BIT(7)) #define GPIO_SIG192_IN_SEL_M (BIT(7)) #define GPIO_SIG192_IN_SEL_V 0x1 #define GPIO_SIG192_IN_SEL_S 7 /* GPIO_FUNC192_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC192_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC192_IN_INV_SEL (BIT(6)) #define GPIO_FUNC192_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC192_IN_INV_SEL_V 0x1 #define GPIO_FUNC192_IN_INV_SEL_S 6 @@ -7400,7 +8142,7 @@ /* GPIO_FUNC192_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC192_IN_SEL 0x0000003F +#define GPIO_FUNC192_IN_SEL 0x0000003F #define GPIO_FUNC192_IN_SEL_M ((GPIO_FUNC192_IN_SEL_V)<<(GPIO_FUNC192_IN_SEL_S)) #define GPIO_FUNC192_IN_SEL_V 0x3F #define GPIO_FUNC192_IN_SEL_S 0 @@ -7408,18 +8150,21 @@ #define GPIO_FUNC193_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0434) /* GPIO_SIG193_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG193_IN_SEL (BIT(7)) +#define GPIO_SIG193_IN_SEL (BIT(7)) #define GPIO_SIG193_IN_SEL_M (BIT(7)) #define GPIO_SIG193_IN_SEL_V 0x1 #define GPIO_SIG193_IN_SEL_S 7 /* GPIO_FUNC193_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC193_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC193_IN_INV_SEL (BIT(6)) #define GPIO_FUNC193_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC193_IN_INV_SEL_V 0x1 #define GPIO_FUNC193_IN_INV_SEL_S 6 @@ -7427,7 +8172,7 @@ /* GPIO_FUNC193_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC193_IN_SEL 0x0000003F +#define GPIO_FUNC193_IN_SEL 0x0000003F #define GPIO_FUNC193_IN_SEL_M ((GPIO_FUNC193_IN_SEL_V)<<(GPIO_FUNC193_IN_SEL_S)) #define GPIO_FUNC193_IN_SEL_V 0x3F #define GPIO_FUNC193_IN_SEL_S 0 @@ -7435,18 +8180,21 @@ #define GPIO_FUNC194_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0438) /* GPIO_SIG194_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG194_IN_SEL (BIT(7)) +#define GPIO_SIG194_IN_SEL (BIT(7)) #define GPIO_SIG194_IN_SEL_M (BIT(7)) #define GPIO_SIG194_IN_SEL_V 0x1 #define GPIO_SIG194_IN_SEL_S 7 /* GPIO_FUNC194_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC194_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC194_IN_INV_SEL (BIT(6)) #define GPIO_FUNC194_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC194_IN_INV_SEL_V 0x1 #define GPIO_FUNC194_IN_INV_SEL_S 6 @@ -7454,7 +8202,7 @@ /* GPIO_FUNC194_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC194_IN_SEL 0x0000003F +#define GPIO_FUNC194_IN_SEL 0x0000003F #define GPIO_FUNC194_IN_SEL_M ((GPIO_FUNC194_IN_SEL_V)<<(GPIO_FUNC194_IN_SEL_S)) #define GPIO_FUNC194_IN_SEL_V 0x3F #define GPIO_FUNC194_IN_SEL_S 0 @@ -7462,18 +8210,21 @@ #define GPIO_FUNC195_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x043c) /* GPIO_SIG195_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG195_IN_SEL (BIT(7)) +#define GPIO_SIG195_IN_SEL (BIT(7)) #define GPIO_SIG195_IN_SEL_M (BIT(7)) #define GPIO_SIG195_IN_SEL_V 0x1 #define GPIO_SIG195_IN_SEL_S 7 /* GPIO_FUNC195_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC195_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC195_IN_INV_SEL (BIT(6)) #define GPIO_FUNC195_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC195_IN_INV_SEL_V 0x1 #define GPIO_FUNC195_IN_INV_SEL_S 6 @@ -7481,7 +8232,7 @@ /* GPIO_FUNC195_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC195_IN_SEL 0x0000003F +#define GPIO_FUNC195_IN_SEL 0x0000003F #define GPIO_FUNC195_IN_SEL_M ((GPIO_FUNC195_IN_SEL_V)<<(GPIO_FUNC195_IN_SEL_S)) #define GPIO_FUNC195_IN_SEL_V 0x3F #define GPIO_FUNC195_IN_SEL_S 0 @@ -7489,18 +8240,21 @@ #define GPIO_FUNC196_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0440) /* GPIO_SIG196_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG196_IN_SEL (BIT(7)) +#define GPIO_SIG196_IN_SEL (BIT(7)) #define GPIO_SIG196_IN_SEL_M (BIT(7)) #define GPIO_SIG196_IN_SEL_V 0x1 #define GPIO_SIG196_IN_SEL_S 7 /* GPIO_FUNC196_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC196_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC196_IN_INV_SEL (BIT(6)) #define GPIO_FUNC196_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC196_IN_INV_SEL_V 0x1 #define GPIO_FUNC196_IN_INV_SEL_S 6 @@ -7508,7 +8262,7 @@ /* GPIO_FUNC196_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC196_IN_SEL 0x0000003F +#define GPIO_FUNC196_IN_SEL 0x0000003F #define GPIO_FUNC196_IN_SEL_M ((GPIO_FUNC196_IN_SEL_V)<<(GPIO_FUNC196_IN_SEL_S)) #define GPIO_FUNC196_IN_SEL_V 0x3F #define GPIO_FUNC196_IN_SEL_S 0 @@ -7516,18 +8270,21 @@ #define GPIO_FUNC197_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0444) /* GPIO_SIG197_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG197_IN_SEL (BIT(7)) +#define GPIO_SIG197_IN_SEL (BIT(7)) #define GPIO_SIG197_IN_SEL_M (BIT(7)) #define GPIO_SIG197_IN_SEL_V 0x1 #define GPIO_SIG197_IN_SEL_S 7 /* GPIO_FUNC197_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC197_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC197_IN_INV_SEL (BIT(6)) #define GPIO_FUNC197_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC197_IN_INV_SEL_V 0x1 #define GPIO_FUNC197_IN_INV_SEL_S 6 @@ -7535,7 +8292,7 @@ /* GPIO_FUNC197_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC197_IN_SEL 0x0000003F +#define GPIO_FUNC197_IN_SEL 0x0000003F #define GPIO_FUNC197_IN_SEL_M ((GPIO_FUNC197_IN_SEL_V)<<(GPIO_FUNC197_IN_SEL_S)) #define GPIO_FUNC197_IN_SEL_V 0x3F #define GPIO_FUNC197_IN_SEL_S 0 @@ -7543,18 +8300,21 @@ #define GPIO_FUNC198_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0448) /* GPIO_SIG198_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG198_IN_SEL (BIT(7)) +#define GPIO_SIG198_IN_SEL (BIT(7)) #define GPIO_SIG198_IN_SEL_M (BIT(7)) #define GPIO_SIG198_IN_SEL_V 0x1 #define GPIO_SIG198_IN_SEL_S 7 /* GPIO_FUNC198_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC198_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC198_IN_INV_SEL (BIT(6)) #define GPIO_FUNC198_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC198_IN_INV_SEL_V 0x1 #define GPIO_FUNC198_IN_INV_SEL_S 6 @@ -7562,7 +8322,7 @@ /* GPIO_FUNC198_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC198_IN_SEL 0x0000003F +#define GPIO_FUNC198_IN_SEL 0x0000003F #define GPIO_FUNC198_IN_SEL_M ((GPIO_FUNC198_IN_SEL_V)<<(GPIO_FUNC198_IN_SEL_S)) #define GPIO_FUNC198_IN_SEL_V 0x3F #define GPIO_FUNC198_IN_SEL_S 0 @@ -7570,18 +8330,21 @@ #define GPIO_FUNC199_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x044c) /* GPIO_SIG199_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG199_IN_SEL (BIT(7)) +#define GPIO_SIG199_IN_SEL (BIT(7)) #define GPIO_SIG199_IN_SEL_M (BIT(7)) #define GPIO_SIG199_IN_SEL_V 0x1 #define GPIO_SIG199_IN_SEL_S 7 /* GPIO_FUNC199_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC199_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC199_IN_INV_SEL (BIT(6)) #define GPIO_FUNC199_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC199_IN_INV_SEL_V 0x1 #define GPIO_FUNC199_IN_INV_SEL_S 6 @@ -7589,7 +8352,7 @@ /* GPIO_FUNC199_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC199_IN_SEL 0x0000003F +#define GPIO_FUNC199_IN_SEL 0x0000003F #define GPIO_FUNC199_IN_SEL_M ((GPIO_FUNC199_IN_SEL_V)<<(GPIO_FUNC199_IN_SEL_S)) #define GPIO_FUNC199_IN_SEL_V 0x3F #define GPIO_FUNC199_IN_SEL_S 0 @@ -7597,18 +8360,21 @@ #define GPIO_FUNC200_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0450) /* GPIO_SIG200_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG200_IN_SEL (BIT(7)) +#define GPIO_SIG200_IN_SEL (BIT(7)) #define GPIO_SIG200_IN_SEL_M (BIT(7)) #define GPIO_SIG200_IN_SEL_V 0x1 #define GPIO_SIG200_IN_SEL_S 7 /* GPIO_FUNC200_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC200_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC200_IN_INV_SEL (BIT(6)) #define GPIO_FUNC200_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC200_IN_INV_SEL_V 0x1 #define GPIO_FUNC200_IN_INV_SEL_S 6 @@ -7616,7 +8382,7 @@ /* GPIO_FUNC200_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC200_IN_SEL 0x0000003F +#define GPIO_FUNC200_IN_SEL 0x0000003F #define GPIO_FUNC200_IN_SEL_M ((GPIO_FUNC200_IN_SEL_V)<<(GPIO_FUNC200_IN_SEL_S)) #define GPIO_FUNC200_IN_SEL_V 0x3F #define GPIO_FUNC200_IN_SEL_S 0 @@ -7624,18 +8390,21 @@ #define GPIO_FUNC201_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0454) /* GPIO_SIG201_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG201_IN_SEL (BIT(7)) +#define GPIO_SIG201_IN_SEL (BIT(7)) #define GPIO_SIG201_IN_SEL_M (BIT(7)) #define GPIO_SIG201_IN_SEL_V 0x1 #define GPIO_SIG201_IN_SEL_S 7 /* GPIO_FUNC201_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC201_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC201_IN_INV_SEL (BIT(6)) #define GPIO_FUNC201_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC201_IN_INV_SEL_V 0x1 #define GPIO_FUNC201_IN_INV_SEL_S 6 @@ -7643,7 +8412,7 @@ /* GPIO_FUNC201_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC201_IN_SEL 0x0000003F +#define GPIO_FUNC201_IN_SEL 0x0000003F #define GPIO_FUNC201_IN_SEL_M ((GPIO_FUNC201_IN_SEL_V)<<(GPIO_FUNC201_IN_SEL_S)) #define GPIO_FUNC201_IN_SEL_V 0x3F #define GPIO_FUNC201_IN_SEL_S 0 @@ -7651,18 +8420,21 @@ #define GPIO_FUNC202_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0458) /* GPIO_SIG202_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG202_IN_SEL (BIT(7)) +#define GPIO_SIG202_IN_SEL (BIT(7)) #define GPIO_SIG202_IN_SEL_M (BIT(7)) #define GPIO_SIG202_IN_SEL_V 0x1 #define GPIO_SIG202_IN_SEL_S 7 /* GPIO_FUNC202_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC202_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC202_IN_INV_SEL (BIT(6)) #define GPIO_FUNC202_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC202_IN_INV_SEL_V 0x1 #define GPIO_FUNC202_IN_INV_SEL_S 6 @@ -7670,7 +8442,7 @@ /* GPIO_FUNC202_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC202_IN_SEL 0x0000003F +#define GPIO_FUNC202_IN_SEL 0x0000003F #define GPIO_FUNC202_IN_SEL_M ((GPIO_FUNC202_IN_SEL_V)<<(GPIO_FUNC202_IN_SEL_S)) #define GPIO_FUNC202_IN_SEL_V 0x3F #define GPIO_FUNC202_IN_SEL_S 0 @@ -7678,18 +8450,21 @@ #define GPIO_FUNC203_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x045c) /* GPIO_SIG203_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG203_IN_SEL (BIT(7)) +#define GPIO_SIG203_IN_SEL (BIT(7)) #define GPIO_SIG203_IN_SEL_M (BIT(7)) #define GPIO_SIG203_IN_SEL_V 0x1 #define GPIO_SIG203_IN_SEL_S 7 /* GPIO_FUNC203_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC203_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC203_IN_INV_SEL (BIT(6)) #define GPIO_FUNC203_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC203_IN_INV_SEL_V 0x1 #define GPIO_FUNC203_IN_INV_SEL_S 6 @@ -7697,7 +8472,7 @@ /* GPIO_FUNC203_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC203_IN_SEL 0x0000003F +#define GPIO_FUNC203_IN_SEL 0x0000003F #define GPIO_FUNC203_IN_SEL_M ((GPIO_FUNC203_IN_SEL_V)<<(GPIO_FUNC203_IN_SEL_S)) #define GPIO_FUNC203_IN_SEL_V 0x3F #define GPIO_FUNC203_IN_SEL_S 0 @@ -7705,18 +8480,21 @@ #define GPIO_FUNC204_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0460) /* GPIO_SIG204_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG204_IN_SEL (BIT(7)) +#define GPIO_SIG204_IN_SEL (BIT(7)) #define GPIO_SIG204_IN_SEL_M (BIT(7)) #define GPIO_SIG204_IN_SEL_V 0x1 #define GPIO_SIG204_IN_SEL_S 7 /* GPIO_FUNC204_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC204_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC204_IN_INV_SEL (BIT(6)) #define GPIO_FUNC204_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC204_IN_INV_SEL_V 0x1 #define GPIO_FUNC204_IN_INV_SEL_S 6 @@ -7724,7 +8502,7 @@ /* GPIO_FUNC204_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC204_IN_SEL 0x0000003F +#define GPIO_FUNC204_IN_SEL 0x0000003F #define GPIO_FUNC204_IN_SEL_M ((GPIO_FUNC204_IN_SEL_V)<<(GPIO_FUNC204_IN_SEL_S)) #define GPIO_FUNC204_IN_SEL_V 0x3F #define GPIO_FUNC204_IN_SEL_S 0 @@ -7732,18 +8510,21 @@ #define GPIO_FUNC205_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0464) /* GPIO_SIG205_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG205_IN_SEL (BIT(7)) +#define GPIO_SIG205_IN_SEL (BIT(7)) #define GPIO_SIG205_IN_SEL_M (BIT(7)) #define GPIO_SIG205_IN_SEL_V 0x1 #define GPIO_SIG205_IN_SEL_S 7 /* GPIO_FUNC205_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC205_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC205_IN_INV_SEL (BIT(6)) #define GPIO_FUNC205_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC205_IN_INV_SEL_V 0x1 #define GPIO_FUNC205_IN_INV_SEL_S 6 @@ -7751,7 +8532,7 @@ /* GPIO_FUNC205_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC205_IN_SEL 0x0000003F +#define GPIO_FUNC205_IN_SEL 0x0000003F #define GPIO_FUNC205_IN_SEL_M ((GPIO_FUNC205_IN_SEL_V)<<(GPIO_FUNC205_IN_SEL_S)) #define GPIO_FUNC205_IN_SEL_V 0x3F #define GPIO_FUNC205_IN_SEL_S 0 @@ -7759,18 +8540,21 @@ #define GPIO_FUNC206_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0468) /* GPIO_SIG206_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG206_IN_SEL (BIT(7)) +#define GPIO_SIG206_IN_SEL (BIT(7)) #define GPIO_SIG206_IN_SEL_M (BIT(7)) #define GPIO_SIG206_IN_SEL_V 0x1 #define GPIO_SIG206_IN_SEL_S 7 /* GPIO_FUNC206_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC206_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC206_IN_INV_SEL (BIT(6)) #define GPIO_FUNC206_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC206_IN_INV_SEL_V 0x1 #define GPIO_FUNC206_IN_INV_SEL_S 6 @@ -7778,7 +8562,7 @@ /* GPIO_FUNC206_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC206_IN_SEL 0x0000003F +#define GPIO_FUNC206_IN_SEL 0x0000003F #define GPIO_FUNC206_IN_SEL_M ((GPIO_FUNC206_IN_SEL_V)<<(GPIO_FUNC206_IN_SEL_S)) #define GPIO_FUNC206_IN_SEL_V 0x3F #define GPIO_FUNC206_IN_SEL_S 0 @@ -7786,18 +8570,21 @@ #define GPIO_FUNC207_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x046c) /* GPIO_SIG207_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG207_IN_SEL (BIT(7)) +#define GPIO_SIG207_IN_SEL (BIT(7)) #define GPIO_SIG207_IN_SEL_M (BIT(7)) #define GPIO_SIG207_IN_SEL_V 0x1 #define GPIO_SIG207_IN_SEL_S 7 /* GPIO_FUNC207_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC207_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC207_IN_INV_SEL (BIT(6)) #define GPIO_FUNC207_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC207_IN_INV_SEL_V 0x1 #define GPIO_FUNC207_IN_INV_SEL_S 6 @@ -7805,7 +8592,7 @@ /* GPIO_FUNC207_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC207_IN_SEL 0x0000003F +#define GPIO_FUNC207_IN_SEL 0x0000003F #define GPIO_FUNC207_IN_SEL_M ((GPIO_FUNC207_IN_SEL_V)<<(GPIO_FUNC207_IN_SEL_S)) #define GPIO_FUNC207_IN_SEL_V 0x3F #define GPIO_FUNC207_IN_SEL_S 0 @@ -7813,18 +8600,21 @@ #define GPIO_FUNC208_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0470) /* GPIO_SIG208_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG208_IN_SEL (BIT(7)) +#define GPIO_SIG208_IN_SEL (BIT(7)) #define GPIO_SIG208_IN_SEL_M (BIT(7)) #define GPIO_SIG208_IN_SEL_V 0x1 #define GPIO_SIG208_IN_SEL_S 7 /* GPIO_FUNC208_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC208_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC208_IN_INV_SEL (BIT(6)) #define GPIO_FUNC208_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC208_IN_INV_SEL_V 0x1 #define GPIO_FUNC208_IN_INV_SEL_S 6 @@ -7832,7 +8622,7 @@ /* GPIO_FUNC208_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC208_IN_SEL 0x0000003F +#define GPIO_FUNC208_IN_SEL 0x0000003F #define GPIO_FUNC208_IN_SEL_M ((GPIO_FUNC208_IN_SEL_V)<<(GPIO_FUNC208_IN_SEL_S)) #define GPIO_FUNC208_IN_SEL_V 0x3F #define GPIO_FUNC208_IN_SEL_S 0 @@ -7840,18 +8630,21 @@ #define GPIO_FUNC209_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0474) /* GPIO_SIG209_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG209_IN_SEL (BIT(7)) +#define GPIO_SIG209_IN_SEL (BIT(7)) #define GPIO_SIG209_IN_SEL_M (BIT(7)) #define GPIO_SIG209_IN_SEL_V 0x1 #define GPIO_SIG209_IN_SEL_S 7 /* GPIO_FUNC209_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC209_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC209_IN_INV_SEL (BIT(6)) #define GPIO_FUNC209_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC209_IN_INV_SEL_V 0x1 #define GPIO_FUNC209_IN_INV_SEL_S 6 @@ -7859,7 +8652,7 @@ /* GPIO_FUNC209_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC209_IN_SEL 0x0000003F +#define GPIO_FUNC209_IN_SEL 0x0000003F #define GPIO_FUNC209_IN_SEL_M ((GPIO_FUNC209_IN_SEL_V)<<(GPIO_FUNC209_IN_SEL_S)) #define GPIO_FUNC209_IN_SEL_V 0x3F #define GPIO_FUNC209_IN_SEL_S 0 @@ -7867,18 +8660,21 @@ #define GPIO_FUNC210_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0478) /* GPIO_SIG210_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG210_IN_SEL (BIT(7)) +#define GPIO_SIG210_IN_SEL (BIT(7)) #define GPIO_SIG210_IN_SEL_M (BIT(7)) #define GPIO_SIG210_IN_SEL_V 0x1 #define GPIO_SIG210_IN_SEL_S 7 /* GPIO_FUNC210_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC210_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC210_IN_INV_SEL (BIT(6)) #define GPIO_FUNC210_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC210_IN_INV_SEL_V 0x1 #define GPIO_FUNC210_IN_INV_SEL_S 6 @@ -7886,7 +8682,7 @@ /* GPIO_FUNC210_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC210_IN_SEL 0x0000003F +#define GPIO_FUNC210_IN_SEL 0x0000003F #define GPIO_FUNC210_IN_SEL_M ((GPIO_FUNC210_IN_SEL_V)<<(GPIO_FUNC210_IN_SEL_S)) #define GPIO_FUNC210_IN_SEL_V 0x3F #define GPIO_FUNC210_IN_SEL_S 0 @@ -7894,18 +8690,21 @@ #define GPIO_FUNC211_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x047c) /* GPIO_SIG211_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG211_IN_SEL (BIT(7)) +#define GPIO_SIG211_IN_SEL (BIT(7)) #define GPIO_SIG211_IN_SEL_M (BIT(7)) #define GPIO_SIG211_IN_SEL_V 0x1 #define GPIO_SIG211_IN_SEL_S 7 /* GPIO_FUNC211_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC211_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC211_IN_INV_SEL (BIT(6)) #define GPIO_FUNC211_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC211_IN_INV_SEL_V 0x1 #define GPIO_FUNC211_IN_INV_SEL_S 6 @@ -7913,7 +8712,7 @@ /* GPIO_FUNC211_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC211_IN_SEL 0x0000003F +#define GPIO_FUNC211_IN_SEL 0x0000003F #define GPIO_FUNC211_IN_SEL_M ((GPIO_FUNC211_IN_SEL_V)<<(GPIO_FUNC211_IN_SEL_S)) #define GPIO_FUNC211_IN_SEL_V 0x3F #define GPIO_FUNC211_IN_SEL_S 0 @@ -7921,18 +8720,21 @@ #define GPIO_FUNC212_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0480) /* GPIO_SIG212_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG212_IN_SEL (BIT(7)) +#define GPIO_SIG212_IN_SEL (BIT(7)) #define GPIO_SIG212_IN_SEL_M (BIT(7)) #define GPIO_SIG212_IN_SEL_V 0x1 #define GPIO_SIG212_IN_SEL_S 7 /* GPIO_FUNC212_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC212_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC212_IN_INV_SEL (BIT(6)) #define GPIO_FUNC212_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC212_IN_INV_SEL_V 0x1 #define GPIO_FUNC212_IN_INV_SEL_S 6 @@ -7940,7 +8742,7 @@ /* GPIO_FUNC212_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC212_IN_SEL 0x0000003F +#define GPIO_FUNC212_IN_SEL 0x0000003F #define GPIO_FUNC212_IN_SEL_M ((GPIO_FUNC212_IN_SEL_V)<<(GPIO_FUNC212_IN_SEL_S)) #define GPIO_FUNC212_IN_SEL_V 0x3F #define GPIO_FUNC212_IN_SEL_S 0 @@ -7948,18 +8750,21 @@ #define GPIO_FUNC213_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0484) /* GPIO_SIG213_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG213_IN_SEL (BIT(7)) +#define GPIO_SIG213_IN_SEL (BIT(7)) #define GPIO_SIG213_IN_SEL_M (BIT(7)) #define GPIO_SIG213_IN_SEL_V 0x1 #define GPIO_SIG213_IN_SEL_S 7 /* GPIO_FUNC213_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC213_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC213_IN_INV_SEL (BIT(6)) #define GPIO_FUNC213_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC213_IN_INV_SEL_V 0x1 #define GPIO_FUNC213_IN_INV_SEL_S 6 @@ -7967,7 +8772,7 @@ /* GPIO_FUNC213_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC213_IN_SEL 0x0000003F +#define GPIO_FUNC213_IN_SEL 0x0000003F #define GPIO_FUNC213_IN_SEL_M ((GPIO_FUNC213_IN_SEL_V)<<(GPIO_FUNC213_IN_SEL_S)) #define GPIO_FUNC213_IN_SEL_V 0x3F #define GPIO_FUNC213_IN_SEL_S 0 @@ -7975,18 +8780,21 @@ #define GPIO_FUNC214_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0488) /* GPIO_SIG214_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG214_IN_SEL (BIT(7)) +#define GPIO_SIG214_IN_SEL (BIT(7)) #define GPIO_SIG214_IN_SEL_M (BIT(7)) #define GPIO_SIG214_IN_SEL_V 0x1 #define GPIO_SIG214_IN_SEL_S 7 /* GPIO_FUNC214_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC214_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC214_IN_INV_SEL (BIT(6)) #define GPIO_FUNC214_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC214_IN_INV_SEL_V 0x1 #define GPIO_FUNC214_IN_INV_SEL_S 6 @@ -7994,7 +8802,7 @@ /* GPIO_FUNC214_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC214_IN_SEL 0x0000003F +#define GPIO_FUNC214_IN_SEL 0x0000003F #define GPIO_FUNC214_IN_SEL_M ((GPIO_FUNC214_IN_SEL_V)<<(GPIO_FUNC214_IN_SEL_S)) #define GPIO_FUNC214_IN_SEL_V 0x3F #define GPIO_FUNC214_IN_SEL_S 0 @@ -8002,18 +8810,21 @@ #define GPIO_FUNC215_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x048c) /* GPIO_SIG215_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG215_IN_SEL (BIT(7)) +#define GPIO_SIG215_IN_SEL (BIT(7)) #define GPIO_SIG215_IN_SEL_M (BIT(7)) #define GPIO_SIG215_IN_SEL_V 0x1 #define GPIO_SIG215_IN_SEL_S 7 /* GPIO_FUNC215_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC215_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC215_IN_INV_SEL (BIT(6)) #define GPIO_FUNC215_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC215_IN_INV_SEL_V 0x1 #define GPIO_FUNC215_IN_INV_SEL_S 6 @@ -8021,7 +8832,7 @@ /* GPIO_FUNC215_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC215_IN_SEL 0x0000003F +#define GPIO_FUNC215_IN_SEL 0x0000003F #define GPIO_FUNC215_IN_SEL_M ((GPIO_FUNC215_IN_SEL_V)<<(GPIO_FUNC215_IN_SEL_S)) #define GPIO_FUNC215_IN_SEL_V 0x3F #define GPIO_FUNC215_IN_SEL_S 0 @@ -8029,18 +8840,21 @@ #define GPIO_FUNC216_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0490) /* GPIO_SIG216_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG216_IN_SEL (BIT(7)) +#define GPIO_SIG216_IN_SEL (BIT(7)) #define GPIO_SIG216_IN_SEL_M (BIT(7)) #define GPIO_SIG216_IN_SEL_V 0x1 #define GPIO_SIG216_IN_SEL_S 7 /* GPIO_FUNC216_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC216_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC216_IN_INV_SEL (BIT(6)) #define GPIO_FUNC216_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC216_IN_INV_SEL_V 0x1 #define GPIO_FUNC216_IN_INV_SEL_S 6 @@ -8048,7 +8862,7 @@ /* GPIO_FUNC216_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC216_IN_SEL 0x0000003F +#define GPIO_FUNC216_IN_SEL 0x0000003F #define GPIO_FUNC216_IN_SEL_M ((GPIO_FUNC216_IN_SEL_V)<<(GPIO_FUNC216_IN_SEL_S)) #define GPIO_FUNC216_IN_SEL_V 0x3F #define GPIO_FUNC216_IN_SEL_S 0 @@ -8056,18 +8870,21 @@ #define GPIO_FUNC217_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0494) /* GPIO_SIG217_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG217_IN_SEL (BIT(7)) +#define GPIO_SIG217_IN_SEL (BIT(7)) #define GPIO_SIG217_IN_SEL_M (BIT(7)) #define GPIO_SIG217_IN_SEL_V 0x1 #define GPIO_SIG217_IN_SEL_S 7 /* GPIO_FUNC217_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC217_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC217_IN_INV_SEL (BIT(6)) #define GPIO_FUNC217_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC217_IN_INV_SEL_V 0x1 #define GPIO_FUNC217_IN_INV_SEL_S 6 @@ -8075,7 +8892,7 @@ /* GPIO_FUNC217_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC217_IN_SEL 0x0000003F +#define GPIO_FUNC217_IN_SEL 0x0000003F #define GPIO_FUNC217_IN_SEL_M ((GPIO_FUNC217_IN_SEL_V)<<(GPIO_FUNC217_IN_SEL_S)) #define GPIO_FUNC217_IN_SEL_V 0x3F #define GPIO_FUNC217_IN_SEL_S 0 @@ -8083,18 +8900,21 @@ #define GPIO_FUNC218_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0498) /* GPIO_SIG218_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG218_IN_SEL (BIT(7)) +#define GPIO_SIG218_IN_SEL (BIT(7)) #define GPIO_SIG218_IN_SEL_M (BIT(7)) #define GPIO_SIG218_IN_SEL_V 0x1 #define GPIO_SIG218_IN_SEL_S 7 /* GPIO_FUNC218_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC218_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC218_IN_INV_SEL (BIT(6)) #define GPIO_FUNC218_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC218_IN_INV_SEL_V 0x1 #define GPIO_FUNC218_IN_INV_SEL_S 6 @@ -8102,7 +8922,7 @@ /* GPIO_FUNC218_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC218_IN_SEL 0x0000003F +#define GPIO_FUNC218_IN_SEL 0x0000003F #define GPIO_FUNC218_IN_SEL_M ((GPIO_FUNC218_IN_SEL_V)<<(GPIO_FUNC218_IN_SEL_S)) #define GPIO_FUNC218_IN_SEL_V 0x3F #define GPIO_FUNC218_IN_SEL_S 0 @@ -8110,18 +8930,21 @@ #define GPIO_FUNC219_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x049c) /* GPIO_SIG219_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG219_IN_SEL (BIT(7)) +#define GPIO_SIG219_IN_SEL (BIT(7)) #define GPIO_SIG219_IN_SEL_M (BIT(7)) #define GPIO_SIG219_IN_SEL_V 0x1 #define GPIO_SIG219_IN_SEL_S 7 /* GPIO_FUNC219_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC219_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC219_IN_INV_SEL (BIT(6)) #define GPIO_FUNC219_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC219_IN_INV_SEL_V 0x1 #define GPIO_FUNC219_IN_INV_SEL_S 6 @@ -8129,7 +8952,7 @@ /* GPIO_FUNC219_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC219_IN_SEL 0x0000003F +#define GPIO_FUNC219_IN_SEL 0x0000003F #define GPIO_FUNC219_IN_SEL_M ((GPIO_FUNC219_IN_SEL_V)<<(GPIO_FUNC219_IN_SEL_S)) #define GPIO_FUNC219_IN_SEL_V 0x3F #define GPIO_FUNC219_IN_SEL_S 0 @@ -8137,18 +8960,21 @@ #define GPIO_FUNC220_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04a0) /* GPIO_SIG220_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG220_IN_SEL (BIT(7)) +#define GPIO_SIG220_IN_SEL (BIT(7)) #define GPIO_SIG220_IN_SEL_M (BIT(7)) #define GPIO_SIG220_IN_SEL_V 0x1 #define GPIO_SIG220_IN_SEL_S 7 /* GPIO_FUNC220_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC220_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC220_IN_INV_SEL (BIT(6)) #define GPIO_FUNC220_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC220_IN_INV_SEL_V 0x1 #define GPIO_FUNC220_IN_INV_SEL_S 6 @@ -8156,7 +8982,7 @@ /* GPIO_FUNC220_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC220_IN_SEL 0x0000003F +#define GPIO_FUNC220_IN_SEL 0x0000003F #define GPIO_FUNC220_IN_SEL_M ((GPIO_FUNC220_IN_SEL_V)<<(GPIO_FUNC220_IN_SEL_S)) #define GPIO_FUNC220_IN_SEL_V 0x3F #define GPIO_FUNC220_IN_SEL_S 0 @@ -8164,18 +8990,21 @@ #define GPIO_FUNC221_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04a4) /* GPIO_SIG221_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG221_IN_SEL (BIT(7)) +#define GPIO_SIG221_IN_SEL (BIT(7)) #define GPIO_SIG221_IN_SEL_M (BIT(7)) #define GPIO_SIG221_IN_SEL_V 0x1 #define GPIO_SIG221_IN_SEL_S 7 /* GPIO_FUNC221_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC221_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC221_IN_INV_SEL (BIT(6)) #define GPIO_FUNC221_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC221_IN_INV_SEL_V 0x1 #define GPIO_FUNC221_IN_INV_SEL_S 6 @@ -8183,7 +9012,7 @@ /* GPIO_FUNC221_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC221_IN_SEL 0x0000003F +#define GPIO_FUNC221_IN_SEL 0x0000003F #define GPIO_FUNC221_IN_SEL_M ((GPIO_FUNC221_IN_SEL_V)<<(GPIO_FUNC221_IN_SEL_S)) #define GPIO_FUNC221_IN_SEL_V 0x3F #define GPIO_FUNC221_IN_SEL_S 0 @@ -8191,18 +9020,21 @@ #define GPIO_FUNC222_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04a8) /* GPIO_SIG222_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG222_IN_SEL (BIT(7)) +#define GPIO_SIG222_IN_SEL (BIT(7)) #define GPIO_SIG222_IN_SEL_M (BIT(7)) #define GPIO_SIG222_IN_SEL_V 0x1 #define GPIO_SIG222_IN_SEL_S 7 /* GPIO_FUNC222_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC222_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC222_IN_INV_SEL (BIT(6)) #define GPIO_FUNC222_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC222_IN_INV_SEL_V 0x1 #define GPIO_FUNC222_IN_INV_SEL_S 6 @@ -8210,7 +9042,7 @@ /* GPIO_FUNC222_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC222_IN_SEL 0x0000003F +#define GPIO_FUNC222_IN_SEL 0x0000003F #define GPIO_FUNC222_IN_SEL_M ((GPIO_FUNC222_IN_SEL_V)<<(GPIO_FUNC222_IN_SEL_S)) #define GPIO_FUNC222_IN_SEL_V 0x3F #define GPIO_FUNC222_IN_SEL_S 0 @@ -8218,18 +9050,21 @@ #define GPIO_FUNC223_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04ac) /* GPIO_SIG223_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG223_IN_SEL (BIT(7)) +#define GPIO_SIG223_IN_SEL (BIT(7)) #define GPIO_SIG223_IN_SEL_M (BIT(7)) #define GPIO_SIG223_IN_SEL_V 0x1 #define GPIO_SIG223_IN_SEL_S 7 /* GPIO_FUNC223_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC223_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC223_IN_INV_SEL (BIT(6)) #define GPIO_FUNC223_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC223_IN_INV_SEL_V 0x1 #define GPIO_FUNC223_IN_INV_SEL_S 6 @@ -8237,7 +9072,7 @@ /* GPIO_FUNC223_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC223_IN_SEL 0x0000003F +#define GPIO_FUNC223_IN_SEL 0x0000003F #define GPIO_FUNC223_IN_SEL_M ((GPIO_FUNC223_IN_SEL_V)<<(GPIO_FUNC223_IN_SEL_S)) #define GPIO_FUNC223_IN_SEL_V 0x3F #define GPIO_FUNC223_IN_SEL_S 0 @@ -8245,18 +9080,21 @@ #define GPIO_FUNC224_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04b0) /* GPIO_SIG224_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG224_IN_SEL (BIT(7)) +#define GPIO_SIG224_IN_SEL (BIT(7)) #define GPIO_SIG224_IN_SEL_M (BIT(7)) #define GPIO_SIG224_IN_SEL_V 0x1 #define GPIO_SIG224_IN_SEL_S 7 /* GPIO_FUNC224_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC224_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC224_IN_INV_SEL (BIT(6)) #define GPIO_FUNC224_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC224_IN_INV_SEL_V 0x1 #define GPIO_FUNC224_IN_INV_SEL_S 6 @@ -8264,7 +9102,7 @@ /* GPIO_FUNC224_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC224_IN_SEL 0x0000003F +#define GPIO_FUNC224_IN_SEL 0x0000003F #define GPIO_FUNC224_IN_SEL_M ((GPIO_FUNC224_IN_SEL_V)<<(GPIO_FUNC224_IN_SEL_S)) #define GPIO_FUNC224_IN_SEL_V 0x3F #define GPIO_FUNC224_IN_SEL_S 0 @@ -8272,18 +9110,21 @@ #define GPIO_FUNC225_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04b4) /* GPIO_SIG225_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG225_IN_SEL (BIT(7)) +#define GPIO_SIG225_IN_SEL (BIT(7)) #define GPIO_SIG225_IN_SEL_M (BIT(7)) #define GPIO_SIG225_IN_SEL_V 0x1 #define GPIO_SIG225_IN_SEL_S 7 /* GPIO_FUNC225_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC225_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC225_IN_INV_SEL (BIT(6)) #define GPIO_FUNC225_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC225_IN_INV_SEL_V 0x1 #define GPIO_FUNC225_IN_INV_SEL_S 6 @@ -8291,7 +9132,7 @@ /* GPIO_FUNC225_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC225_IN_SEL 0x0000003F +#define GPIO_FUNC225_IN_SEL 0x0000003F #define GPIO_FUNC225_IN_SEL_M ((GPIO_FUNC225_IN_SEL_V)<<(GPIO_FUNC225_IN_SEL_S)) #define GPIO_FUNC225_IN_SEL_V 0x3F #define GPIO_FUNC225_IN_SEL_S 0 @@ -8299,18 +9140,21 @@ #define GPIO_FUNC226_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04b8) /* GPIO_SIG226_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG226_IN_SEL (BIT(7)) +#define GPIO_SIG226_IN_SEL (BIT(7)) #define GPIO_SIG226_IN_SEL_M (BIT(7)) #define GPIO_SIG226_IN_SEL_V 0x1 #define GPIO_SIG226_IN_SEL_S 7 /* GPIO_FUNC226_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC226_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC226_IN_INV_SEL (BIT(6)) #define GPIO_FUNC226_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC226_IN_INV_SEL_V 0x1 #define GPIO_FUNC226_IN_INV_SEL_S 6 @@ -8318,7 +9162,7 @@ /* GPIO_FUNC226_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC226_IN_SEL 0x0000003F +#define GPIO_FUNC226_IN_SEL 0x0000003F #define GPIO_FUNC226_IN_SEL_M ((GPIO_FUNC226_IN_SEL_V)<<(GPIO_FUNC226_IN_SEL_S)) #define GPIO_FUNC226_IN_SEL_V 0x3F #define GPIO_FUNC226_IN_SEL_S 0 @@ -8326,18 +9170,21 @@ #define GPIO_FUNC227_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04bc) /* GPIO_SIG227_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG227_IN_SEL (BIT(7)) +#define GPIO_SIG227_IN_SEL (BIT(7)) #define GPIO_SIG227_IN_SEL_M (BIT(7)) #define GPIO_SIG227_IN_SEL_V 0x1 #define GPIO_SIG227_IN_SEL_S 7 /* GPIO_FUNC227_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC227_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC227_IN_INV_SEL (BIT(6)) #define GPIO_FUNC227_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC227_IN_INV_SEL_V 0x1 #define GPIO_FUNC227_IN_INV_SEL_S 6 @@ -8345,7 +9192,7 @@ /* GPIO_FUNC227_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC227_IN_SEL 0x0000003F +#define GPIO_FUNC227_IN_SEL 0x0000003F #define GPIO_FUNC227_IN_SEL_M ((GPIO_FUNC227_IN_SEL_V)<<(GPIO_FUNC227_IN_SEL_S)) #define GPIO_FUNC227_IN_SEL_V 0x3F #define GPIO_FUNC227_IN_SEL_S 0 @@ -8353,18 +9200,21 @@ #define GPIO_FUNC228_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04c0) /* GPIO_SIG228_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG228_IN_SEL (BIT(7)) +#define GPIO_SIG228_IN_SEL (BIT(7)) #define GPIO_SIG228_IN_SEL_M (BIT(7)) #define GPIO_SIG228_IN_SEL_V 0x1 #define GPIO_SIG228_IN_SEL_S 7 /* GPIO_FUNC228_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC228_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC228_IN_INV_SEL (BIT(6)) #define GPIO_FUNC228_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC228_IN_INV_SEL_V 0x1 #define GPIO_FUNC228_IN_INV_SEL_S 6 @@ -8372,7 +9222,7 @@ /* GPIO_FUNC228_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC228_IN_SEL 0x0000003F +#define GPIO_FUNC228_IN_SEL 0x0000003F #define GPIO_FUNC228_IN_SEL_M ((GPIO_FUNC228_IN_SEL_V)<<(GPIO_FUNC228_IN_SEL_S)) #define GPIO_FUNC228_IN_SEL_V 0x3F #define GPIO_FUNC228_IN_SEL_S 0 @@ -8380,18 +9230,21 @@ #define GPIO_FUNC229_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04c4) /* GPIO_SIG229_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG229_IN_SEL (BIT(7)) +#define GPIO_SIG229_IN_SEL (BIT(7)) #define GPIO_SIG229_IN_SEL_M (BIT(7)) #define GPIO_SIG229_IN_SEL_V 0x1 #define GPIO_SIG229_IN_SEL_S 7 /* GPIO_FUNC229_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC229_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC229_IN_INV_SEL (BIT(6)) #define GPIO_FUNC229_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC229_IN_INV_SEL_V 0x1 #define GPIO_FUNC229_IN_INV_SEL_S 6 @@ -8399,7 +9252,7 @@ /* GPIO_FUNC229_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC229_IN_SEL 0x0000003F +#define GPIO_FUNC229_IN_SEL 0x0000003F #define GPIO_FUNC229_IN_SEL_M ((GPIO_FUNC229_IN_SEL_V)<<(GPIO_FUNC229_IN_SEL_S)) #define GPIO_FUNC229_IN_SEL_V 0x3F #define GPIO_FUNC229_IN_SEL_S 0 @@ -8407,18 +9260,21 @@ #define GPIO_FUNC230_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04c8) /* GPIO_SIG230_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG230_IN_SEL (BIT(7)) +#define GPIO_SIG230_IN_SEL (BIT(7)) #define GPIO_SIG230_IN_SEL_M (BIT(7)) #define GPIO_SIG230_IN_SEL_V 0x1 #define GPIO_SIG230_IN_SEL_S 7 /* GPIO_FUNC230_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC230_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC230_IN_INV_SEL (BIT(6)) #define GPIO_FUNC230_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC230_IN_INV_SEL_V 0x1 #define GPIO_FUNC230_IN_INV_SEL_S 6 @@ -8426,7 +9282,7 @@ /* GPIO_FUNC230_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC230_IN_SEL 0x0000003F +#define GPIO_FUNC230_IN_SEL 0x0000003F #define GPIO_FUNC230_IN_SEL_M ((GPIO_FUNC230_IN_SEL_V)<<(GPIO_FUNC230_IN_SEL_S)) #define GPIO_FUNC230_IN_SEL_V 0x3F #define GPIO_FUNC230_IN_SEL_S 0 @@ -8434,18 +9290,21 @@ #define GPIO_FUNC231_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04cc) /* GPIO_SIG231_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG231_IN_SEL (BIT(7)) +#define GPIO_SIG231_IN_SEL (BIT(7)) #define GPIO_SIG231_IN_SEL_M (BIT(7)) #define GPIO_SIG231_IN_SEL_V 0x1 #define GPIO_SIG231_IN_SEL_S 7 /* GPIO_FUNC231_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC231_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC231_IN_INV_SEL (BIT(6)) #define GPIO_FUNC231_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC231_IN_INV_SEL_V 0x1 #define GPIO_FUNC231_IN_INV_SEL_S 6 @@ -8453,7 +9312,7 @@ /* GPIO_FUNC231_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC231_IN_SEL 0x0000003F +#define GPIO_FUNC231_IN_SEL 0x0000003F #define GPIO_FUNC231_IN_SEL_M ((GPIO_FUNC231_IN_SEL_V)<<(GPIO_FUNC231_IN_SEL_S)) #define GPIO_FUNC231_IN_SEL_V 0x3F #define GPIO_FUNC231_IN_SEL_S 0 @@ -8461,18 +9320,21 @@ #define GPIO_FUNC232_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04d0) /* GPIO_SIG232_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG232_IN_SEL (BIT(7)) +#define GPIO_SIG232_IN_SEL (BIT(7)) #define GPIO_SIG232_IN_SEL_M (BIT(7)) #define GPIO_SIG232_IN_SEL_V 0x1 #define GPIO_SIG232_IN_SEL_S 7 /* GPIO_FUNC232_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC232_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC232_IN_INV_SEL (BIT(6)) #define GPIO_FUNC232_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC232_IN_INV_SEL_V 0x1 #define GPIO_FUNC232_IN_INV_SEL_S 6 @@ -8480,7 +9342,7 @@ /* GPIO_FUNC232_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC232_IN_SEL 0x0000003F +#define GPIO_FUNC232_IN_SEL 0x0000003F #define GPIO_FUNC232_IN_SEL_M ((GPIO_FUNC232_IN_SEL_V)<<(GPIO_FUNC232_IN_SEL_S)) #define GPIO_FUNC232_IN_SEL_V 0x3F #define GPIO_FUNC232_IN_SEL_S 0 @@ -8488,18 +9350,21 @@ #define GPIO_FUNC233_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04d4) /* GPIO_SIG233_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG233_IN_SEL (BIT(7)) +#define GPIO_SIG233_IN_SEL (BIT(7)) #define GPIO_SIG233_IN_SEL_M (BIT(7)) #define GPIO_SIG233_IN_SEL_V 0x1 #define GPIO_SIG233_IN_SEL_S 7 /* GPIO_FUNC233_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC233_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC233_IN_INV_SEL (BIT(6)) #define GPIO_FUNC233_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC233_IN_INV_SEL_V 0x1 #define GPIO_FUNC233_IN_INV_SEL_S 6 @@ -8507,7 +9372,7 @@ /* GPIO_FUNC233_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC233_IN_SEL 0x0000003F +#define GPIO_FUNC233_IN_SEL 0x0000003F #define GPIO_FUNC233_IN_SEL_M ((GPIO_FUNC233_IN_SEL_V)<<(GPIO_FUNC233_IN_SEL_S)) #define GPIO_FUNC233_IN_SEL_V 0x3F #define GPIO_FUNC233_IN_SEL_S 0 @@ -8515,18 +9380,21 @@ #define GPIO_FUNC234_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04d8) /* GPIO_SIG234_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG234_IN_SEL (BIT(7)) +#define GPIO_SIG234_IN_SEL (BIT(7)) #define GPIO_SIG234_IN_SEL_M (BIT(7)) #define GPIO_SIG234_IN_SEL_V 0x1 #define GPIO_SIG234_IN_SEL_S 7 /* GPIO_FUNC234_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC234_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC234_IN_INV_SEL (BIT(6)) #define GPIO_FUNC234_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC234_IN_INV_SEL_V 0x1 #define GPIO_FUNC234_IN_INV_SEL_S 6 @@ -8534,7 +9402,7 @@ /* GPIO_FUNC234_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC234_IN_SEL 0x0000003F +#define GPIO_FUNC234_IN_SEL 0x0000003F #define GPIO_FUNC234_IN_SEL_M ((GPIO_FUNC234_IN_SEL_V)<<(GPIO_FUNC234_IN_SEL_S)) #define GPIO_FUNC234_IN_SEL_V 0x3F #define GPIO_FUNC234_IN_SEL_S 0 @@ -8542,18 +9410,21 @@ #define GPIO_FUNC235_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04dc) /* GPIO_SIG235_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG235_IN_SEL (BIT(7)) +#define GPIO_SIG235_IN_SEL (BIT(7)) #define GPIO_SIG235_IN_SEL_M (BIT(7)) #define GPIO_SIG235_IN_SEL_V 0x1 #define GPIO_SIG235_IN_SEL_S 7 /* GPIO_FUNC235_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC235_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC235_IN_INV_SEL (BIT(6)) #define GPIO_FUNC235_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC235_IN_INV_SEL_V 0x1 #define GPIO_FUNC235_IN_INV_SEL_S 6 @@ -8561,7 +9432,7 @@ /* GPIO_FUNC235_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC235_IN_SEL 0x0000003F +#define GPIO_FUNC235_IN_SEL 0x0000003F #define GPIO_FUNC235_IN_SEL_M ((GPIO_FUNC235_IN_SEL_V)<<(GPIO_FUNC235_IN_SEL_S)) #define GPIO_FUNC235_IN_SEL_V 0x3F #define GPIO_FUNC235_IN_SEL_S 0 @@ -8569,18 +9440,21 @@ #define GPIO_FUNC236_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04e0) /* GPIO_SIG236_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG236_IN_SEL (BIT(7)) +#define GPIO_SIG236_IN_SEL (BIT(7)) #define GPIO_SIG236_IN_SEL_M (BIT(7)) #define GPIO_SIG236_IN_SEL_V 0x1 #define GPIO_SIG236_IN_SEL_S 7 /* GPIO_FUNC236_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC236_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC236_IN_INV_SEL (BIT(6)) #define GPIO_FUNC236_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC236_IN_INV_SEL_V 0x1 #define GPIO_FUNC236_IN_INV_SEL_S 6 @@ -8588,7 +9462,7 @@ /* GPIO_FUNC236_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC236_IN_SEL 0x0000003F +#define GPIO_FUNC236_IN_SEL 0x0000003F #define GPIO_FUNC236_IN_SEL_M ((GPIO_FUNC236_IN_SEL_V)<<(GPIO_FUNC236_IN_SEL_S)) #define GPIO_FUNC236_IN_SEL_V 0x3F #define GPIO_FUNC236_IN_SEL_S 0 @@ -8596,18 +9470,21 @@ #define GPIO_FUNC237_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04e4) /* GPIO_SIG237_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG237_IN_SEL (BIT(7)) +#define GPIO_SIG237_IN_SEL (BIT(7)) #define GPIO_SIG237_IN_SEL_M (BIT(7)) #define GPIO_SIG237_IN_SEL_V 0x1 #define GPIO_SIG237_IN_SEL_S 7 /* GPIO_FUNC237_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC237_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC237_IN_INV_SEL (BIT(6)) #define GPIO_FUNC237_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC237_IN_INV_SEL_V 0x1 #define GPIO_FUNC237_IN_INV_SEL_S 6 @@ -8615,7 +9492,7 @@ /* GPIO_FUNC237_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC237_IN_SEL 0x0000003F +#define GPIO_FUNC237_IN_SEL 0x0000003F #define GPIO_FUNC237_IN_SEL_M ((GPIO_FUNC237_IN_SEL_V)<<(GPIO_FUNC237_IN_SEL_S)) #define GPIO_FUNC237_IN_SEL_V 0x3F #define GPIO_FUNC237_IN_SEL_S 0 @@ -8623,18 +9500,21 @@ #define GPIO_FUNC238_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04e8) /* GPIO_SIG238_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG238_IN_SEL (BIT(7)) +#define GPIO_SIG238_IN_SEL (BIT(7)) #define GPIO_SIG238_IN_SEL_M (BIT(7)) #define GPIO_SIG238_IN_SEL_V 0x1 #define GPIO_SIG238_IN_SEL_S 7 /* GPIO_FUNC238_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC238_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC238_IN_INV_SEL (BIT(6)) #define GPIO_FUNC238_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC238_IN_INV_SEL_V 0x1 #define GPIO_FUNC238_IN_INV_SEL_S 6 @@ -8642,7 +9522,7 @@ /* GPIO_FUNC238_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC238_IN_SEL 0x0000003F +#define GPIO_FUNC238_IN_SEL 0x0000003F #define GPIO_FUNC238_IN_SEL_M ((GPIO_FUNC238_IN_SEL_V)<<(GPIO_FUNC238_IN_SEL_S)) #define GPIO_FUNC238_IN_SEL_V 0x3F #define GPIO_FUNC238_IN_SEL_S 0 @@ -8650,18 +9530,21 @@ #define GPIO_FUNC239_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04ec) /* GPIO_SIG239_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG239_IN_SEL (BIT(7)) +#define GPIO_SIG239_IN_SEL (BIT(7)) #define GPIO_SIG239_IN_SEL_M (BIT(7)) #define GPIO_SIG239_IN_SEL_V 0x1 #define GPIO_SIG239_IN_SEL_S 7 /* GPIO_FUNC239_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC239_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC239_IN_INV_SEL (BIT(6)) #define GPIO_FUNC239_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC239_IN_INV_SEL_V 0x1 #define GPIO_FUNC239_IN_INV_SEL_S 6 @@ -8669,7 +9552,7 @@ /* GPIO_FUNC239_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC239_IN_SEL 0x0000003F +#define GPIO_FUNC239_IN_SEL 0x0000003F #define GPIO_FUNC239_IN_SEL_M ((GPIO_FUNC239_IN_SEL_V)<<(GPIO_FUNC239_IN_SEL_S)) #define GPIO_FUNC239_IN_SEL_V 0x3F #define GPIO_FUNC239_IN_SEL_S 0 @@ -8677,18 +9560,21 @@ #define GPIO_FUNC240_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04f0) /* GPIO_SIG240_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG240_IN_SEL (BIT(7)) +#define GPIO_SIG240_IN_SEL (BIT(7)) #define GPIO_SIG240_IN_SEL_M (BIT(7)) #define GPIO_SIG240_IN_SEL_V 0x1 #define GPIO_SIG240_IN_SEL_S 7 /* GPIO_FUNC240_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC240_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC240_IN_INV_SEL (BIT(6)) #define GPIO_FUNC240_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC240_IN_INV_SEL_V 0x1 #define GPIO_FUNC240_IN_INV_SEL_S 6 @@ -8696,7 +9582,7 @@ /* GPIO_FUNC240_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC240_IN_SEL 0x0000003F +#define GPIO_FUNC240_IN_SEL 0x0000003F #define GPIO_FUNC240_IN_SEL_M ((GPIO_FUNC240_IN_SEL_V)<<(GPIO_FUNC240_IN_SEL_S)) #define GPIO_FUNC240_IN_SEL_V 0x3F #define GPIO_FUNC240_IN_SEL_S 0 @@ -8704,18 +9590,21 @@ #define GPIO_FUNC241_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04f4) /* GPIO_SIG241_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG241_IN_SEL (BIT(7)) +#define GPIO_SIG241_IN_SEL (BIT(7)) #define GPIO_SIG241_IN_SEL_M (BIT(7)) #define GPIO_SIG241_IN_SEL_V 0x1 #define GPIO_SIG241_IN_SEL_S 7 /* GPIO_FUNC241_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC241_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC241_IN_INV_SEL (BIT(6)) #define GPIO_FUNC241_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC241_IN_INV_SEL_V 0x1 #define GPIO_FUNC241_IN_INV_SEL_S 6 @@ -8723,7 +9612,7 @@ /* GPIO_FUNC241_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC241_IN_SEL 0x0000003F +#define GPIO_FUNC241_IN_SEL 0x0000003F #define GPIO_FUNC241_IN_SEL_M ((GPIO_FUNC241_IN_SEL_V)<<(GPIO_FUNC241_IN_SEL_S)) #define GPIO_FUNC241_IN_SEL_V 0x3F #define GPIO_FUNC241_IN_SEL_S 0 @@ -8731,18 +9620,21 @@ #define GPIO_FUNC242_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04f8) /* GPIO_SIG242_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG242_IN_SEL (BIT(7)) +#define GPIO_SIG242_IN_SEL (BIT(7)) #define GPIO_SIG242_IN_SEL_M (BIT(7)) #define GPIO_SIG242_IN_SEL_V 0x1 #define GPIO_SIG242_IN_SEL_S 7 /* GPIO_FUNC242_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC242_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC242_IN_INV_SEL (BIT(6)) #define GPIO_FUNC242_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC242_IN_INV_SEL_V 0x1 #define GPIO_FUNC242_IN_INV_SEL_S 6 @@ -8750,7 +9642,7 @@ /* GPIO_FUNC242_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC242_IN_SEL 0x0000003F +#define GPIO_FUNC242_IN_SEL 0x0000003F #define GPIO_FUNC242_IN_SEL_M ((GPIO_FUNC242_IN_SEL_V)<<(GPIO_FUNC242_IN_SEL_S)) #define GPIO_FUNC242_IN_SEL_V 0x3F #define GPIO_FUNC242_IN_SEL_S 0 @@ -8758,18 +9650,21 @@ #define GPIO_FUNC243_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x04fc) /* GPIO_SIG243_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG243_IN_SEL (BIT(7)) +#define GPIO_SIG243_IN_SEL (BIT(7)) #define GPIO_SIG243_IN_SEL_M (BIT(7)) #define GPIO_SIG243_IN_SEL_V 0x1 #define GPIO_SIG243_IN_SEL_S 7 /* GPIO_FUNC243_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC243_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC243_IN_INV_SEL (BIT(6)) #define GPIO_FUNC243_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC243_IN_INV_SEL_V 0x1 #define GPIO_FUNC243_IN_INV_SEL_S 6 @@ -8777,7 +9672,7 @@ /* GPIO_FUNC243_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC243_IN_SEL 0x0000003F +#define GPIO_FUNC243_IN_SEL 0x0000003F #define GPIO_FUNC243_IN_SEL_M ((GPIO_FUNC243_IN_SEL_V)<<(GPIO_FUNC243_IN_SEL_S)) #define GPIO_FUNC243_IN_SEL_V 0x3F #define GPIO_FUNC243_IN_SEL_S 0 @@ -8785,18 +9680,21 @@ #define GPIO_FUNC244_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0500) /* GPIO_SIG244_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG244_IN_SEL (BIT(7)) +#define GPIO_SIG244_IN_SEL (BIT(7)) #define GPIO_SIG244_IN_SEL_M (BIT(7)) #define GPIO_SIG244_IN_SEL_V 0x1 #define GPIO_SIG244_IN_SEL_S 7 /* GPIO_FUNC244_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC244_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC244_IN_INV_SEL (BIT(6)) #define GPIO_FUNC244_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC244_IN_INV_SEL_V 0x1 #define GPIO_FUNC244_IN_INV_SEL_S 6 @@ -8804,7 +9702,7 @@ /* GPIO_FUNC244_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC244_IN_SEL 0x0000003F +#define GPIO_FUNC244_IN_SEL 0x0000003F #define GPIO_FUNC244_IN_SEL_M ((GPIO_FUNC244_IN_SEL_V)<<(GPIO_FUNC244_IN_SEL_S)) #define GPIO_FUNC244_IN_SEL_V 0x3F #define GPIO_FUNC244_IN_SEL_S 0 @@ -8812,18 +9710,21 @@ #define GPIO_FUNC245_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0504) /* GPIO_SIG245_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG245_IN_SEL (BIT(7)) +#define GPIO_SIG245_IN_SEL (BIT(7)) #define GPIO_SIG245_IN_SEL_M (BIT(7)) #define GPIO_SIG245_IN_SEL_V 0x1 #define GPIO_SIG245_IN_SEL_S 7 /* GPIO_FUNC245_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC245_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC245_IN_INV_SEL (BIT(6)) #define GPIO_FUNC245_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC245_IN_INV_SEL_V 0x1 #define GPIO_FUNC245_IN_INV_SEL_S 6 @@ -8831,7 +9732,7 @@ /* GPIO_FUNC245_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC245_IN_SEL 0x0000003F +#define GPIO_FUNC245_IN_SEL 0x0000003F #define GPIO_FUNC245_IN_SEL_M ((GPIO_FUNC245_IN_SEL_V)<<(GPIO_FUNC245_IN_SEL_S)) #define GPIO_FUNC245_IN_SEL_V 0x3F #define GPIO_FUNC245_IN_SEL_S 0 @@ -8839,18 +9740,21 @@ #define GPIO_FUNC246_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0508) /* GPIO_SIG246_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG246_IN_SEL (BIT(7)) +#define GPIO_SIG246_IN_SEL (BIT(7)) #define GPIO_SIG246_IN_SEL_M (BIT(7)) #define GPIO_SIG246_IN_SEL_V 0x1 #define GPIO_SIG246_IN_SEL_S 7 /* GPIO_FUNC246_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC246_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC246_IN_INV_SEL (BIT(6)) #define GPIO_FUNC246_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC246_IN_INV_SEL_V 0x1 #define GPIO_FUNC246_IN_INV_SEL_S 6 @@ -8858,7 +9762,7 @@ /* GPIO_FUNC246_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC246_IN_SEL 0x0000003F +#define GPIO_FUNC246_IN_SEL 0x0000003F #define GPIO_FUNC246_IN_SEL_M ((GPIO_FUNC246_IN_SEL_V)<<(GPIO_FUNC246_IN_SEL_S)) #define GPIO_FUNC246_IN_SEL_V 0x3F #define GPIO_FUNC246_IN_SEL_S 0 @@ -8866,18 +9770,21 @@ #define GPIO_FUNC247_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x050c) /* GPIO_SIG247_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG247_IN_SEL (BIT(7)) +#define GPIO_SIG247_IN_SEL (BIT(7)) #define GPIO_SIG247_IN_SEL_M (BIT(7)) #define GPIO_SIG247_IN_SEL_V 0x1 #define GPIO_SIG247_IN_SEL_S 7 /* GPIO_FUNC247_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC247_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC247_IN_INV_SEL (BIT(6)) #define GPIO_FUNC247_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC247_IN_INV_SEL_V 0x1 #define GPIO_FUNC247_IN_INV_SEL_S 6 @@ -8885,7 +9792,7 @@ /* GPIO_FUNC247_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC247_IN_SEL 0x0000003F +#define GPIO_FUNC247_IN_SEL 0x0000003F #define GPIO_FUNC247_IN_SEL_M ((GPIO_FUNC247_IN_SEL_V)<<(GPIO_FUNC247_IN_SEL_S)) #define GPIO_FUNC247_IN_SEL_V 0x3F #define GPIO_FUNC247_IN_SEL_S 0 @@ -8893,18 +9800,21 @@ #define GPIO_FUNC248_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0510) /* GPIO_SIG248_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG248_IN_SEL (BIT(7)) +#define GPIO_SIG248_IN_SEL (BIT(7)) #define GPIO_SIG248_IN_SEL_M (BIT(7)) #define GPIO_SIG248_IN_SEL_V 0x1 #define GPIO_SIG248_IN_SEL_S 7 /* GPIO_FUNC248_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC248_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC248_IN_INV_SEL (BIT(6)) #define GPIO_FUNC248_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC248_IN_INV_SEL_V 0x1 #define GPIO_FUNC248_IN_INV_SEL_S 6 @@ -8912,7 +9822,7 @@ /* GPIO_FUNC248_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC248_IN_SEL 0x0000003F +#define GPIO_FUNC248_IN_SEL 0x0000003F #define GPIO_FUNC248_IN_SEL_M ((GPIO_FUNC248_IN_SEL_V)<<(GPIO_FUNC248_IN_SEL_S)) #define GPIO_FUNC248_IN_SEL_V 0x3F #define GPIO_FUNC248_IN_SEL_S 0 @@ -8920,18 +9830,21 @@ #define GPIO_FUNC249_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0514) /* GPIO_SIG249_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG249_IN_SEL (BIT(7)) +#define GPIO_SIG249_IN_SEL (BIT(7)) #define GPIO_SIG249_IN_SEL_M (BIT(7)) #define GPIO_SIG249_IN_SEL_V 0x1 #define GPIO_SIG249_IN_SEL_S 7 /* GPIO_FUNC249_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC249_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC249_IN_INV_SEL (BIT(6)) #define GPIO_FUNC249_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC249_IN_INV_SEL_V 0x1 #define GPIO_FUNC249_IN_INV_SEL_S 6 @@ -8939,7 +9852,7 @@ /* GPIO_FUNC249_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC249_IN_SEL 0x0000003F +#define GPIO_FUNC249_IN_SEL 0x0000003F #define GPIO_FUNC249_IN_SEL_M ((GPIO_FUNC249_IN_SEL_V)<<(GPIO_FUNC249_IN_SEL_S)) #define GPIO_FUNC249_IN_SEL_V 0x3F #define GPIO_FUNC249_IN_SEL_S 0 @@ -8947,18 +9860,21 @@ #define GPIO_FUNC250_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0518) /* GPIO_SIG250_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG250_IN_SEL (BIT(7)) +#define GPIO_SIG250_IN_SEL (BIT(7)) #define GPIO_SIG250_IN_SEL_M (BIT(7)) #define GPIO_SIG250_IN_SEL_V 0x1 #define GPIO_SIG250_IN_SEL_S 7 /* GPIO_FUNC250_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC250_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC250_IN_INV_SEL (BIT(6)) #define GPIO_FUNC250_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC250_IN_INV_SEL_V 0x1 #define GPIO_FUNC250_IN_INV_SEL_S 6 @@ -8966,7 +9882,7 @@ /* GPIO_FUNC250_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC250_IN_SEL 0x0000003F +#define GPIO_FUNC250_IN_SEL 0x0000003F #define GPIO_FUNC250_IN_SEL_M ((GPIO_FUNC250_IN_SEL_V)<<(GPIO_FUNC250_IN_SEL_S)) #define GPIO_FUNC250_IN_SEL_V 0x3F #define GPIO_FUNC250_IN_SEL_S 0 @@ -8974,18 +9890,21 @@ #define GPIO_FUNC251_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x051c) /* GPIO_SIG251_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG251_IN_SEL (BIT(7)) +#define GPIO_SIG251_IN_SEL (BIT(7)) #define GPIO_SIG251_IN_SEL_M (BIT(7)) #define GPIO_SIG251_IN_SEL_V 0x1 #define GPIO_SIG251_IN_SEL_S 7 /* GPIO_FUNC251_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC251_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC251_IN_INV_SEL (BIT(6)) #define GPIO_FUNC251_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC251_IN_INV_SEL_V 0x1 #define GPIO_FUNC251_IN_INV_SEL_S 6 @@ -8993,7 +9912,7 @@ /* GPIO_FUNC251_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC251_IN_SEL 0x0000003F +#define GPIO_FUNC251_IN_SEL 0x0000003F #define GPIO_FUNC251_IN_SEL_M ((GPIO_FUNC251_IN_SEL_V)<<(GPIO_FUNC251_IN_SEL_S)) #define GPIO_FUNC251_IN_SEL_V 0x3F #define GPIO_FUNC251_IN_SEL_S 0 @@ -9001,18 +9920,21 @@ #define GPIO_FUNC252_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0520) /* GPIO_SIG252_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG252_IN_SEL (BIT(7)) +#define GPIO_SIG252_IN_SEL (BIT(7)) #define GPIO_SIG252_IN_SEL_M (BIT(7)) #define GPIO_SIG252_IN_SEL_V 0x1 #define GPIO_SIG252_IN_SEL_S 7 /* GPIO_FUNC252_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC252_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC252_IN_INV_SEL (BIT(6)) #define GPIO_FUNC252_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC252_IN_INV_SEL_V 0x1 #define GPIO_FUNC252_IN_INV_SEL_S 6 @@ -9020,7 +9942,7 @@ /* GPIO_FUNC252_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC252_IN_SEL 0x0000003F +#define GPIO_FUNC252_IN_SEL 0x0000003F #define GPIO_FUNC252_IN_SEL_M ((GPIO_FUNC252_IN_SEL_V)<<(GPIO_FUNC252_IN_SEL_S)) #define GPIO_FUNC252_IN_SEL_V 0x3F #define GPIO_FUNC252_IN_SEL_S 0 @@ -9028,18 +9950,21 @@ #define GPIO_FUNC253_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0524) /* GPIO_SIG253_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG253_IN_SEL (BIT(7)) +#define GPIO_SIG253_IN_SEL (BIT(7)) #define GPIO_SIG253_IN_SEL_M (BIT(7)) #define GPIO_SIG253_IN_SEL_V 0x1 #define GPIO_SIG253_IN_SEL_S 7 /* GPIO_FUNC253_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC253_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC253_IN_INV_SEL (BIT(6)) #define GPIO_FUNC253_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC253_IN_INV_SEL_V 0x1 #define GPIO_FUNC253_IN_INV_SEL_S 6 @@ -9047,7 +9972,7 @@ /* GPIO_FUNC253_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC253_IN_SEL 0x0000003F +#define GPIO_FUNC253_IN_SEL 0x0000003F #define GPIO_FUNC253_IN_SEL_M ((GPIO_FUNC253_IN_SEL_V)<<(GPIO_FUNC253_IN_SEL_S)) #define GPIO_FUNC253_IN_SEL_V 0x3F #define GPIO_FUNC253_IN_SEL_S 0 @@ -9055,18 +9980,21 @@ #define GPIO_FUNC254_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0528) /* GPIO_SIG254_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG254_IN_SEL (BIT(7)) +#define GPIO_SIG254_IN_SEL (BIT(7)) #define GPIO_SIG254_IN_SEL_M (BIT(7)) #define GPIO_SIG254_IN_SEL_V 0x1 #define GPIO_SIG254_IN_SEL_S 7 /* GPIO_FUNC254_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC254_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC254_IN_INV_SEL (BIT(6)) #define GPIO_FUNC254_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC254_IN_INV_SEL_V 0x1 #define GPIO_FUNC254_IN_INV_SEL_S 6 @@ -9074,7 +10002,7 @@ /* GPIO_FUNC254_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC254_IN_SEL 0x0000003F +#define GPIO_FUNC254_IN_SEL 0x0000003F #define GPIO_FUNC254_IN_SEL_M ((GPIO_FUNC254_IN_SEL_V)<<(GPIO_FUNC254_IN_SEL_S)) #define GPIO_FUNC254_IN_SEL_V 0x3F #define GPIO_FUNC254_IN_SEL_S 0 @@ -9082,18 +10010,21 @@ #define GPIO_FUNC255_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x052c) /* GPIO_SIG255_IN_SEL : R/W ;bitpos:[7] ;default: x ; */ -/* Description: if the slow signal bypass the io matrix or not if you want setting - the value to 1 */ +/* Description: if the slow signal bypass the io matrix or not if you want + * setting the value to 1. + */ -#define GPIO_SIG255_IN_SEL (BIT(7)) +#define GPIO_SIG255_IN_SEL (BIT(7)) #define GPIO_SIG255_IN_SEL_M (BIT(7)) #define GPIO_SIG255_IN_SEL_V 0x1 #define GPIO_SIG255_IN_SEL_S 7 /* GPIO_FUNC255_IN_INV_SEL : R/W ;bitpos:[6] ;default: x ; */ -/* Description: revert the value of the input if you want to revert please set the value to 1 */ +/* Description: revert the value of the input if you want to revert please + * set the value to 1. + */ -#define GPIO_FUNC255_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC255_IN_INV_SEL (BIT(6)) #define GPIO_FUNC255_IN_INV_SEL_M (BIT(6)) #define GPIO_FUNC255_IN_INV_SEL_V 0x1 #define GPIO_FUNC255_IN_INV_SEL_S 6 @@ -9101,7 +10032,7 @@ /* GPIO_FUNC255_IN_SEL : R/W ;bitpos:[5:0] ;default: x ; */ /* Description: select one of the 256 inputs */ -#define GPIO_FUNC255_IN_SEL 0x0000003F +#define GPIO_FUNC255_IN_SEL 0x0000003F #define GPIO_FUNC255_IN_SEL_M ((GPIO_FUNC255_IN_SEL_V)<<(GPIO_FUNC255_IN_SEL_S)) #define GPIO_FUNC255_IN_SEL_V 0x3F #define GPIO_FUNC255_IN_SEL_S 0 @@ -9109,28 +10040,31 @@ #define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0530) /* GPIO_FUNC0_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC0_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC0_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC0_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC0_OEN_INV_SEL_V 0x1 #define GPIO_FUNC0_OEN_INV_SEL_S 11 /* GPIO_FUNC0_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC0_OEN_SEL (BIT(10)) +#define GPIO_FUNC0_OEN_SEL (BIT(10)) #define GPIO_FUNC0_OEN_SEL_M (BIT(10)) #define GPIO_FUNC0_OEN_SEL_V 0x1 #define GPIO_FUNC0_OEN_SEL_S 10 /* GPIO_FUNC0_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC0_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC0_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC0_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC0_OUT_INV_SEL_V 0x1 #define GPIO_FUNC0_OUT_INV_SEL_S 9 @@ -9138,7 +10072,7 @@ /* GPIO_FUNC0_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC0_OUT_SEL 0x000001FF +#define GPIO_FUNC0_OUT_SEL 0x000001FF #define GPIO_FUNC0_OUT_SEL_M ((GPIO_FUNC0_OUT_SEL_V)<<(GPIO_FUNC0_OUT_SEL_S)) #define GPIO_FUNC0_OUT_SEL_V 0x1FF #define GPIO_FUNC0_OUT_SEL_S 0 @@ -9146,28 +10080,31 @@ #define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0534) /* GPIO_FUNC1_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC1_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC1_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC1_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC1_OEN_INV_SEL_V 0x1 #define GPIO_FUNC1_OEN_INV_SEL_S 11 /* GPIO_FUNC1_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC1_OEN_SEL (BIT(10)) +#define GPIO_FUNC1_OEN_SEL (BIT(10)) #define GPIO_FUNC1_OEN_SEL_M (BIT(10)) #define GPIO_FUNC1_OEN_SEL_V 0x1 #define GPIO_FUNC1_OEN_SEL_S 10 /* GPIO_FUNC1_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC1_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC1_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC1_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC1_OUT_INV_SEL_V 0x1 #define GPIO_FUNC1_OUT_INV_SEL_S 9 @@ -9175,7 +10112,7 @@ /* GPIO_FUNC1_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC1_OUT_SEL 0x000001FF +#define GPIO_FUNC1_OUT_SEL 0x000001FF #define GPIO_FUNC1_OUT_SEL_M ((GPIO_FUNC1_OUT_SEL_V)<<(GPIO_FUNC1_OUT_SEL_S)) #define GPIO_FUNC1_OUT_SEL_V 0x1FF #define GPIO_FUNC1_OUT_SEL_S 0 @@ -9183,28 +10120,31 @@ #define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0538) /* GPIO_FUNC2_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC2_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC2_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC2_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC2_OEN_INV_SEL_V 0x1 #define GPIO_FUNC2_OEN_INV_SEL_S 11 /* GPIO_FUNC2_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC2_OEN_SEL (BIT(10)) +#define GPIO_FUNC2_OEN_SEL (BIT(10)) #define GPIO_FUNC2_OEN_SEL_M (BIT(10)) #define GPIO_FUNC2_OEN_SEL_V 0x1 #define GPIO_FUNC2_OEN_SEL_S 10 /* GPIO_FUNC2_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC2_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC2_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC2_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC2_OUT_INV_SEL_V 0x1 #define GPIO_FUNC2_OUT_INV_SEL_S 9 @@ -9212,7 +10152,7 @@ /* GPIO_FUNC2_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC2_OUT_SEL 0x000001FF +#define GPIO_FUNC2_OUT_SEL 0x000001FF #define GPIO_FUNC2_OUT_SEL_M ((GPIO_FUNC2_OUT_SEL_V)<<(GPIO_FUNC2_OUT_SEL_S)) #define GPIO_FUNC2_OUT_SEL_V 0x1FF #define GPIO_FUNC2_OUT_SEL_S 0 @@ -9220,28 +10160,31 @@ #define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x053c) /* GPIO_FUNC3_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC3_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC3_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC3_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC3_OEN_INV_SEL_V 0x1 #define GPIO_FUNC3_OEN_INV_SEL_S 11 /* GPIO_FUNC3_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC3_OEN_SEL (BIT(10)) +#define GPIO_FUNC3_OEN_SEL (BIT(10)) #define GPIO_FUNC3_OEN_SEL_M (BIT(10)) #define GPIO_FUNC3_OEN_SEL_V 0x1 #define GPIO_FUNC3_OEN_SEL_S 10 /* GPIO_FUNC3_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC3_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC3_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC3_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC3_OUT_INV_SEL_V 0x1 #define GPIO_FUNC3_OUT_INV_SEL_S 9 @@ -9249,7 +10192,7 @@ /* GPIO_FUNC3_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC3_OUT_SEL 0x000001FF +#define GPIO_FUNC3_OUT_SEL 0x000001FF #define GPIO_FUNC3_OUT_SEL_M ((GPIO_FUNC3_OUT_SEL_V)<<(GPIO_FUNC3_OUT_SEL_S)) #define GPIO_FUNC3_OUT_SEL_V 0x1FF #define GPIO_FUNC3_OUT_SEL_S 0 @@ -9257,28 +10200,31 @@ #define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0540) /* GPIO_FUNC4_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC4_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC4_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC4_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC4_OEN_INV_SEL_V 0x1 #define GPIO_FUNC4_OEN_INV_SEL_S 11 /* GPIO_FUNC4_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC4_OEN_SEL (BIT(10)) +#define GPIO_FUNC4_OEN_SEL (BIT(10)) #define GPIO_FUNC4_OEN_SEL_M (BIT(10)) #define GPIO_FUNC4_OEN_SEL_V 0x1 #define GPIO_FUNC4_OEN_SEL_S 10 /* GPIO_FUNC4_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC4_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC4_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC4_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC4_OUT_INV_SEL_V 0x1 #define GPIO_FUNC4_OUT_INV_SEL_S 9 @@ -9286,7 +10232,7 @@ /* GPIO_FUNC4_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC4_OUT_SEL 0x000001FF +#define GPIO_FUNC4_OUT_SEL 0x000001FF #define GPIO_FUNC4_OUT_SEL_M ((GPIO_FUNC4_OUT_SEL_V)<<(GPIO_FUNC4_OUT_SEL_S)) #define GPIO_FUNC4_OUT_SEL_V 0x1FF #define GPIO_FUNC4_OUT_SEL_S 0 @@ -9294,28 +10240,31 @@ #define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0544) /* GPIO_FUNC5_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC5_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC5_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC5_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC5_OEN_INV_SEL_V 0x1 #define GPIO_FUNC5_OEN_INV_SEL_S 11 /* GPIO_FUNC5_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC5_OEN_SEL (BIT(10)) +#define GPIO_FUNC5_OEN_SEL (BIT(10)) #define GPIO_FUNC5_OEN_SEL_M (BIT(10)) #define GPIO_FUNC5_OEN_SEL_V 0x1 #define GPIO_FUNC5_OEN_SEL_S 10 /* GPIO_FUNC5_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC5_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC5_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC5_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC5_OUT_INV_SEL_V 0x1 #define GPIO_FUNC5_OUT_INV_SEL_S 9 @@ -9323,7 +10272,7 @@ /* GPIO_FUNC5_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC5_OUT_SEL 0x000001FF +#define GPIO_FUNC5_OUT_SEL 0x000001FF #define GPIO_FUNC5_OUT_SEL_M ((GPIO_FUNC5_OUT_SEL_V)<<(GPIO_FUNC5_OUT_SEL_S)) #define GPIO_FUNC5_OUT_SEL_V 0x1FF #define GPIO_FUNC5_OUT_SEL_S 0 @@ -9331,28 +10280,31 @@ #define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0548) /* GPIO_FUNC6_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC6_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC6_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC6_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC6_OEN_INV_SEL_V 0x1 #define GPIO_FUNC6_OEN_INV_SEL_S 11 /* GPIO_FUNC6_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC6_OEN_SEL (BIT(10)) +#define GPIO_FUNC6_OEN_SEL (BIT(10)) #define GPIO_FUNC6_OEN_SEL_M (BIT(10)) #define GPIO_FUNC6_OEN_SEL_V 0x1 #define GPIO_FUNC6_OEN_SEL_S 10 /* GPIO_FUNC6_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC6_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC6_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC6_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC6_OUT_INV_SEL_V 0x1 #define GPIO_FUNC6_OUT_INV_SEL_S 9 @@ -9360,7 +10312,7 @@ /* GPIO_FUNC6_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC6_OUT_SEL 0x000001FF +#define GPIO_FUNC6_OUT_SEL 0x000001FF #define GPIO_FUNC6_OUT_SEL_M ((GPIO_FUNC6_OUT_SEL_V)<<(GPIO_FUNC6_OUT_SEL_S)) #define GPIO_FUNC6_OUT_SEL_V 0x1FF #define GPIO_FUNC6_OUT_SEL_S 0 @@ -9368,28 +10320,31 @@ #define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x054c) /* GPIO_FUNC7_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC7_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC7_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC7_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC7_OEN_INV_SEL_V 0x1 #define GPIO_FUNC7_OEN_INV_SEL_S 11 /* GPIO_FUNC7_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC7_OEN_SEL (BIT(10)) +#define GPIO_FUNC7_OEN_SEL (BIT(10)) #define GPIO_FUNC7_OEN_SEL_M (BIT(10)) #define GPIO_FUNC7_OEN_SEL_V 0x1 #define GPIO_FUNC7_OEN_SEL_S 10 /* GPIO_FUNC7_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC7_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC7_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC7_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC7_OUT_INV_SEL_V 0x1 #define GPIO_FUNC7_OUT_INV_SEL_S 9 @@ -9397,7 +10352,7 @@ /* GPIO_FUNC7_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC7_OUT_SEL 0x000001FF +#define GPIO_FUNC7_OUT_SEL 0x000001FF #define GPIO_FUNC7_OUT_SEL_M ((GPIO_FUNC7_OUT_SEL_V)<<(GPIO_FUNC7_OUT_SEL_S)) #define GPIO_FUNC7_OUT_SEL_V 0x1FF #define GPIO_FUNC7_OUT_SEL_S 0 @@ -9405,28 +10360,31 @@ #define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0550) /* GPIO_FUNC8_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC8_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC8_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC8_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC8_OEN_INV_SEL_V 0x1 #define GPIO_FUNC8_OEN_INV_SEL_S 11 /* GPIO_FUNC8_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC8_OEN_SEL (BIT(10)) +#define GPIO_FUNC8_OEN_SEL (BIT(10)) #define GPIO_FUNC8_OEN_SEL_M (BIT(10)) #define GPIO_FUNC8_OEN_SEL_V 0x1 #define GPIO_FUNC8_OEN_SEL_S 10 /* GPIO_FUNC8_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC8_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC8_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC8_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC8_OUT_INV_SEL_V 0x1 #define GPIO_FUNC8_OUT_INV_SEL_S 9 @@ -9434,7 +10392,7 @@ /* GPIO_FUNC8_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC8_OUT_SEL 0x000001FF +#define GPIO_FUNC8_OUT_SEL 0x000001FF #define GPIO_FUNC8_OUT_SEL_M ((GPIO_FUNC8_OUT_SEL_V)<<(GPIO_FUNC8_OUT_SEL_S)) #define GPIO_FUNC8_OUT_SEL_V 0x1FF #define GPIO_FUNC8_OUT_SEL_S 0 @@ -9442,28 +10400,31 @@ #define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0554) /* GPIO_FUNC9_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC9_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC9_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC9_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC9_OEN_INV_SEL_V 0x1 #define GPIO_FUNC9_OEN_INV_SEL_S 11 /* GPIO_FUNC9_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC9_OEN_SEL (BIT(10)) +#define GPIO_FUNC9_OEN_SEL (BIT(10)) #define GPIO_FUNC9_OEN_SEL_M (BIT(10)) #define GPIO_FUNC9_OEN_SEL_V 0x1 #define GPIO_FUNC9_OEN_SEL_S 10 /* GPIO_FUNC9_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC9_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC9_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC9_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC9_OUT_INV_SEL_V 0x1 #define GPIO_FUNC9_OUT_INV_SEL_S 9 @@ -9471,7 +10432,7 @@ /* GPIO_FUNC9_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC9_OUT_SEL 0x000001FF +#define GPIO_FUNC9_OUT_SEL 0x000001FF #define GPIO_FUNC9_OUT_SEL_M ((GPIO_FUNC9_OUT_SEL_V)<<(GPIO_FUNC9_OUT_SEL_S)) #define GPIO_FUNC9_OUT_SEL_V 0x1FF #define GPIO_FUNC9_OUT_SEL_S 0 @@ -9479,28 +10440,31 @@ #define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0558) /* GPIO_FUNC10_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC10_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC10_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC10_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC10_OEN_INV_SEL_V 0x1 #define GPIO_FUNC10_OEN_INV_SEL_S 11 /* GPIO_FUNC10_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC10_OEN_SEL (BIT(10)) +#define GPIO_FUNC10_OEN_SEL (BIT(10)) #define GPIO_FUNC10_OEN_SEL_M (BIT(10)) #define GPIO_FUNC10_OEN_SEL_V 0x1 #define GPIO_FUNC10_OEN_SEL_S 10 /* GPIO_FUNC10_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC10_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC10_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC10_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC10_OUT_INV_SEL_V 0x1 #define GPIO_FUNC10_OUT_INV_SEL_S 9 @@ -9508,7 +10472,7 @@ /* GPIO_FUNC10_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC10_OUT_SEL 0x000001FF +#define GPIO_FUNC10_OUT_SEL 0x000001FF #define GPIO_FUNC10_OUT_SEL_M ((GPIO_FUNC10_OUT_SEL_V)<<(GPIO_FUNC10_OUT_SEL_S)) #define GPIO_FUNC10_OUT_SEL_V 0x1FF #define GPIO_FUNC10_OUT_SEL_S 0 @@ -9516,28 +10480,31 @@ #define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x055c) /* GPIO_FUNC11_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC11_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC11_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC11_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC11_OEN_INV_SEL_V 0x1 #define GPIO_FUNC11_OEN_INV_SEL_S 11 /* GPIO_FUNC11_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC11_OEN_SEL (BIT(10)) +#define GPIO_FUNC11_OEN_SEL (BIT(10)) #define GPIO_FUNC11_OEN_SEL_M (BIT(10)) #define GPIO_FUNC11_OEN_SEL_V 0x1 #define GPIO_FUNC11_OEN_SEL_S 10 /* GPIO_FUNC11_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC11_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC11_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC11_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC11_OUT_INV_SEL_V 0x1 #define GPIO_FUNC11_OUT_INV_SEL_S 9 @@ -9545,7 +10512,7 @@ /* GPIO_FUNC11_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC11_OUT_SEL 0x000001FF +#define GPIO_FUNC11_OUT_SEL 0x000001FF #define GPIO_FUNC11_OUT_SEL_M ((GPIO_FUNC11_OUT_SEL_V)<<(GPIO_FUNC11_OUT_SEL_S)) #define GPIO_FUNC11_OUT_SEL_V 0x1FF #define GPIO_FUNC11_OUT_SEL_S 0 @@ -9553,28 +10520,31 @@ #define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0560) /* GPIO_FUNC12_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC12_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC12_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC12_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC12_OEN_INV_SEL_V 0x1 #define GPIO_FUNC12_OEN_INV_SEL_S 11 /* GPIO_FUNC12_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC12_OEN_SEL (BIT(10)) +#define GPIO_FUNC12_OEN_SEL (BIT(10)) #define GPIO_FUNC12_OEN_SEL_M (BIT(10)) #define GPIO_FUNC12_OEN_SEL_V 0x1 #define GPIO_FUNC12_OEN_SEL_S 10 /* GPIO_FUNC12_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC12_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC12_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC12_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC12_OUT_INV_SEL_V 0x1 #define GPIO_FUNC12_OUT_INV_SEL_S 9 @@ -9582,7 +10552,7 @@ /* GPIO_FUNC12_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC12_OUT_SEL 0x000001FF +#define GPIO_FUNC12_OUT_SEL 0x000001FF #define GPIO_FUNC12_OUT_SEL_M ((GPIO_FUNC12_OUT_SEL_V)<<(GPIO_FUNC12_OUT_SEL_S)) #define GPIO_FUNC12_OUT_SEL_V 0x1FF #define GPIO_FUNC12_OUT_SEL_S 0 @@ -9590,28 +10560,31 @@ #define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0564) /* GPIO_FUNC13_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC13_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC13_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC13_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC13_OEN_INV_SEL_V 0x1 #define GPIO_FUNC13_OEN_INV_SEL_S 11 /* GPIO_FUNC13_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC13_OEN_SEL (BIT(10)) +#define GPIO_FUNC13_OEN_SEL (BIT(10)) #define GPIO_FUNC13_OEN_SEL_M (BIT(10)) #define GPIO_FUNC13_OEN_SEL_V 0x1 #define GPIO_FUNC13_OEN_SEL_S 10 /* GPIO_FUNC13_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC13_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC13_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC13_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC13_OUT_INV_SEL_V 0x1 #define GPIO_FUNC13_OUT_INV_SEL_S 9 @@ -9619,7 +10592,7 @@ /* GPIO_FUNC13_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC13_OUT_SEL 0x000001FF +#define GPIO_FUNC13_OUT_SEL 0x000001FF #define GPIO_FUNC13_OUT_SEL_M ((GPIO_FUNC13_OUT_SEL_V)<<(GPIO_FUNC13_OUT_SEL_S)) #define GPIO_FUNC13_OUT_SEL_V 0x1FF #define GPIO_FUNC13_OUT_SEL_S 0 @@ -9627,28 +10600,31 @@ #define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0568) /* GPIO_FUNC14_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC14_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC14_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC14_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC14_OEN_INV_SEL_V 0x1 #define GPIO_FUNC14_OEN_INV_SEL_S 11 /* GPIO_FUNC14_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC14_OEN_SEL (BIT(10)) +#define GPIO_FUNC14_OEN_SEL (BIT(10)) #define GPIO_FUNC14_OEN_SEL_M (BIT(10)) #define GPIO_FUNC14_OEN_SEL_V 0x1 #define GPIO_FUNC14_OEN_SEL_S 10 /* GPIO_FUNC14_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC14_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC14_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC14_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC14_OUT_INV_SEL_V 0x1 #define GPIO_FUNC14_OUT_INV_SEL_S 9 @@ -9656,7 +10632,7 @@ /* GPIO_FUNC14_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC14_OUT_SEL 0x000001FF +#define GPIO_FUNC14_OUT_SEL 0x000001FF #define GPIO_FUNC14_OUT_SEL_M ((GPIO_FUNC14_OUT_SEL_V)<<(GPIO_FUNC14_OUT_SEL_S)) #define GPIO_FUNC14_OUT_SEL_V 0x1FF #define GPIO_FUNC14_OUT_SEL_S 0 @@ -9664,28 +10640,31 @@ #define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x056c) /* GPIO_FUNC15_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC15_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC15_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC15_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC15_OEN_INV_SEL_V 0x1 #define GPIO_FUNC15_OEN_INV_SEL_S 11 /* GPIO_FUNC15_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC15_OEN_SEL (BIT(10)) +#define GPIO_FUNC15_OEN_SEL (BIT(10)) #define GPIO_FUNC15_OEN_SEL_M (BIT(10)) #define GPIO_FUNC15_OEN_SEL_V 0x1 #define GPIO_FUNC15_OEN_SEL_S 10 /* GPIO_FUNC15_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC15_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC15_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC15_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC15_OUT_INV_SEL_V 0x1 #define GPIO_FUNC15_OUT_INV_SEL_S 9 @@ -9693,7 +10672,7 @@ /* GPIO_FUNC15_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC15_OUT_SEL 0x000001FF +#define GPIO_FUNC15_OUT_SEL 0x000001FF #define GPIO_FUNC15_OUT_SEL_M ((GPIO_FUNC15_OUT_SEL_V)<<(GPIO_FUNC15_OUT_SEL_S)) #define GPIO_FUNC15_OUT_SEL_V 0x1FF #define GPIO_FUNC15_OUT_SEL_S 0 @@ -9701,28 +10680,31 @@ #define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0570) /* GPIO_FUNC16_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC16_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC16_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC16_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC16_OEN_INV_SEL_V 0x1 #define GPIO_FUNC16_OEN_INV_SEL_S 11 /* GPIO_FUNC16_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC16_OEN_SEL (BIT(10)) +#define GPIO_FUNC16_OEN_SEL (BIT(10)) #define GPIO_FUNC16_OEN_SEL_M (BIT(10)) #define GPIO_FUNC16_OEN_SEL_V 0x1 #define GPIO_FUNC16_OEN_SEL_S 10 /* GPIO_FUNC16_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC16_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC16_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC16_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC16_OUT_INV_SEL_V 0x1 #define GPIO_FUNC16_OUT_INV_SEL_S 9 @@ -9730,7 +10712,7 @@ /* GPIO_FUNC16_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC16_OUT_SEL 0x000001FF +#define GPIO_FUNC16_OUT_SEL 0x000001FF #define GPIO_FUNC16_OUT_SEL_M ((GPIO_FUNC16_OUT_SEL_V)<<(GPIO_FUNC16_OUT_SEL_S)) #define GPIO_FUNC16_OUT_SEL_V 0x1FF #define GPIO_FUNC16_OUT_SEL_S 0 @@ -9738,28 +10720,31 @@ #define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0574) /* GPIO_FUNC17_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC17_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC17_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC17_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC17_OEN_INV_SEL_V 0x1 #define GPIO_FUNC17_OEN_INV_SEL_S 11 /* GPIO_FUNC17_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC17_OEN_SEL (BIT(10)) +#define GPIO_FUNC17_OEN_SEL (BIT(10)) #define GPIO_FUNC17_OEN_SEL_M (BIT(10)) #define GPIO_FUNC17_OEN_SEL_V 0x1 #define GPIO_FUNC17_OEN_SEL_S 10 /* GPIO_FUNC17_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC17_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC17_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC17_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC17_OUT_INV_SEL_V 0x1 #define GPIO_FUNC17_OUT_INV_SEL_S 9 @@ -9767,7 +10752,7 @@ /* GPIO_FUNC17_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC17_OUT_SEL 0x000001FF +#define GPIO_FUNC17_OUT_SEL 0x000001FF #define GPIO_FUNC17_OUT_SEL_M ((GPIO_FUNC17_OUT_SEL_V)<<(GPIO_FUNC17_OUT_SEL_S)) #define GPIO_FUNC17_OUT_SEL_V 0x1FF #define GPIO_FUNC17_OUT_SEL_S 0 @@ -9775,28 +10760,31 @@ #define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0578) /* GPIO_FUNC18_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC18_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC18_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC18_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC18_OEN_INV_SEL_V 0x1 #define GPIO_FUNC18_OEN_INV_SEL_S 11 /* GPIO_FUNC18_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC18_OEN_SEL (BIT(10)) +#define GPIO_FUNC18_OEN_SEL (BIT(10)) #define GPIO_FUNC18_OEN_SEL_M (BIT(10)) #define GPIO_FUNC18_OEN_SEL_V 0x1 #define GPIO_FUNC18_OEN_SEL_S 10 /* GPIO_FUNC18_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC18_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC18_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC18_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC18_OUT_INV_SEL_V 0x1 #define GPIO_FUNC18_OUT_INV_SEL_S 9 @@ -9804,7 +10792,7 @@ /* GPIO_FUNC18_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC18_OUT_SEL 0x000001FF +#define GPIO_FUNC18_OUT_SEL 0x000001FF #define GPIO_FUNC18_OUT_SEL_M ((GPIO_FUNC18_OUT_SEL_V)<<(GPIO_FUNC18_OUT_SEL_S)) #define GPIO_FUNC18_OUT_SEL_V 0x1FF #define GPIO_FUNC18_OUT_SEL_S 0 @@ -9812,28 +10800,31 @@ #define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x057c) /* GPIO_FUNC19_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC19_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC19_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC19_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC19_OEN_INV_SEL_V 0x1 #define GPIO_FUNC19_OEN_INV_SEL_S 11 /* GPIO_FUNC19_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC19_OEN_SEL (BIT(10)) +#define GPIO_FUNC19_OEN_SEL (BIT(10)) #define GPIO_FUNC19_OEN_SEL_M (BIT(10)) #define GPIO_FUNC19_OEN_SEL_V 0x1 #define GPIO_FUNC19_OEN_SEL_S 10 /* GPIO_FUNC19_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC19_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC19_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC19_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC19_OUT_INV_SEL_V 0x1 #define GPIO_FUNC19_OUT_INV_SEL_S 9 @@ -9841,7 +10832,7 @@ /* GPIO_FUNC19_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC19_OUT_SEL 0x000001FF +#define GPIO_FUNC19_OUT_SEL 0x000001FF #define GPIO_FUNC19_OUT_SEL_M ((GPIO_FUNC19_OUT_SEL_V)<<(GPIO_FUNC19_OUT_SEL_S)) #define GPIO_FUNC19_OUT_SEL_V 0x1FF #define GPIO_FUNC19_OUT_SEL_S 0 @@ -9849,28 +10840,31 @@ #define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0580) /* GPIO_FUNC20_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC20_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC20_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC20_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC20_OEN_INV_SEL_V 0x1 #define GPIO_FUNC20_OEN_INV_SEL_S 11 /* GPIO_FUNC20_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC20_OEN_SEL (BIT(10)) +#define GPIO_FUNC20_OEN_SEL (BIT(10)) #define GPIO_FUNC20_OEN_SEL_M (BIT(10)) #define GPIO_FUNC20_OEN_SEL_V 0x1 #define GPIO_FUNC20_OEN_SEL_S 10 /* GPIO_FUNC20_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC20_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC20_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC20_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC20_OUT_INV_SEL_V 0x1 #define GPIO_FUNC20_OUT_INV_SEL_S 9 @@ -9878,7 +10872,7 @@ /* GPIO_FUNC20_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC20_OUT_SEL 0x000001FF +#define GPIO_FUNC20_OUT_SEL 0x000001FF #define GPIO_FUNC20_OUT_SEL_M ((GPIO_FUNC20_OUT_SEL_V)<<(GPIO_FUNC20_OUT_SEL_S)) #define GPIO_FUNC20_OUT_SEL_V 0x1FF #define GPIO_FUNC20_OUT_SEL_S 0 @@ -9886,28 +10880,31 @@ #define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0584) /* GPIO_FUNC21_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC21_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC21_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC21_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC21_OEN_INV_SEL_V 0x1 #define GPIO_FUNC21_OEN_INV_SEL_S 11 /* GPIO_FUNC21_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC21_OEN_SEL (BIT(10)) +#define GPIO_FUNC21_OEN_SEL (BIT(10)) #define GPIO_FUNC21_OEN_SEL_M (BIT(10)) #define GPIO_FUNC21_OEN_SEL_V 0x1 #define GPIO_FUNC21_OEN_SEL_S 10 /* GPIO_FUNC21_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC21_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC21_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC21_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC21_OUT_INV_SEL_V 0x1 #define GPIO_FUNC21_OUT_INV_SEL_S 9 @@ -9915,7 +10912,7 @@ /* GPIO_FUNC21_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC21_OUT_SEL 0x000001FF +#define GPIO_FUNC21_OUT_SEL 0x000001FF #define GPIO_FUNC21_OUT_SEL_M ((GPIO_FUNC21_OUT_SEL_V)<<(GPIO_FUNC21_OUT_SEL_S)) #define GPIO_FUNC21_OUT_SEL_V 0x1FF #define GPIO_FUNC21_OUT_SEL_S 0 @@ -9923,28 +10920,31 @@ #define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0588) /* GPIO_FUNC22_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC22_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC22_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC22_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC22_OEN_INV_SEL_V 0x1 #define GPIO_FUNC22_OEN_INV_SEL_S 11 /* GPIO_FUNC22_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC22_OEN_SEL (BIT(10)) +#define GPIO_FUNC22_OEN_SEL (BIT(10)) #define GPIO_FUNC22_OEN_SEL_M (BIT(10)) #define GPIO_FUNC22_OEN_SEL_V 0x1 #define GPIO_FUNC22_OEN_SEL_S 10 /* GPIO_FUNC22_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC22_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC22_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC22_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC22_OUT_INV_SEL_V 0x1 #define GPIO_FUNC22_OUT_INV_SEL_S 9 @@ -9952,7 +10952,7 @@ /* GPIO_FUNC22_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC22_OUT_SEL 0x000001FF +#define GPIO_FUNC22_OUT_SEL 0x000001FF #define GPIO_FUNC22_OUT_SEL_M ((GPIO_FUNC22_OUT_SEL_V)<<(GPIO_FUNC22_OUT_SEL_S)) #define GPIO_FUNC22_OUT_SEL_V 0x1FF #define GPIO_FUNC22_OUT_SEL_S 0 @@ -9960,28 +10960,31 @@ #define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x058c) /* GPIO_FUNC23_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC23_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC23_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC23_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC23_OEN_INV_SEL_V 0x1 #define GPIO_FUNC23_OEN_INV_SEL_S 11 /* GPIO_FUNC23_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC23_OEN_SEL (BIT(10)) +#define GPIO_FUNC23_OEN_SEL (BIT(10)) #define GPIO_FUNC23_OEN_SEL_M (BIT(10)) #define GPIO_FUNC23_OEN_SEL_V 0x1 #define GPIO_FUNC23_OEN_SEL_S 10 /* GPIO_FUNC23_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC23_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC23_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC23_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC23_OUT_INV_SEL_V 0x1 #define GPIO_FUNC23_OUT_INV_SEL_S 9 @@ -9989,7 +10992,7 @@ /* GPIO_FUNC23_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC23_OUT_SEL 0x000001FF +#define GPIO_FUNC23_OUT_SEL 0x000001FF #define GPIO_FUNC23_OUT_SEL_M ((GPIO_FUNC23_OUT_SEL_V)<<(GPIO_FUNC23_OUT_SEL_S)) #define GPIO_FUNC23_OUT_SEL_V 0x1FF #define GPIO_FUNC23_OUT_SEL_S 0 @@ -9997,28 +11000,31 @@ #define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0590) /* GPIO_FUNC24_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC24_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC24_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC24_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC24_OEN_INV_SEL_V 0x1 #define GPIO_FUNC24_OEN_INV_SEL_S 11 /* GPIO_FUNC24_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC24_OEN_SEL (BIT(10)) +#define GPIO_FUNC24_OEN_SEL (BIT(10)) #define GPIO_FUNC24_OEN_SEL_M (BIT(10)) #define GPIO_FUNC24_OEN_SEL_V 0x1 #define GPIO_FUNC24_OEN_SEL_S 10 /* GPIO_FUNC24_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC24_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC24_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC24_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC24_OUT_INV_SEL_V 0x1 #define GPIO_FUNC24_OUT_INV_SEL_S 9 @@ -10026,7 +11032,7 @@ /* GPIO_FUNC24_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC24_OUT_SEL 0x000001FF +#define GPIO_FUNC24_OUT_SEL 0x000001FF #define GPIO_FUNC24_OUT_SEL_M ((GPIO_FUNC24_OUT_SEL_V)<<(GPIO_FUNC24_OUT_SEL_S)) #define GPIO_FUNC24_OUT_SEL_V 0x1FF #define GPIO_FUNC24_OUT_SEL_S 0 @@ -10034,28 +11040,31 @@ #define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0594) /* GPIO_FUNC25_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC25_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC25_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC25_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC25_OEN_INV_SEL_V 0x1 #define GPIO_FUNC25_OEN_INV_SEL_S 11 /* GPIO_FUNC25_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC25_OEN_SEL (BIT(10)) +#define GPIO_FUNC25_OEN_SEL (BIT(10)) #define GPIO_FUNC25_OEN_SEL_M (BIT(10)) #define GPIO_FUNC25_OEN_SEL_V 0x1 #define GPIO_FUNC25_OEN_SEL_S 10 /* GPIO_FUNC25_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC25_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC25_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC25_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC25_OUT_INV_SEL_V 0x1 #define GPIO_FUNC25_OUT_INV_SEL_S 9 @@ -10063,7 +11072,7 @@ /* GPIO_FUNC25_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC25_OUT_SEL 0x000001FF +#define GPIO_FUNC25_OUT_SEL 0x000001FF #define GPIO_FUNC25_OUT_SEL_M ((GPIO_FUNC25_OUT_SEL_V)<<(GPIO_FUNC25_OUT_SEL_S)) #define GPIO_FUNC25_OUT_SEL_V 0x1FF #define GPIO_FUNC25_OUT_SEL_S 0 @@ -10071,28 +11080,31 @@ #define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x0598) /* GPIO_FUNC26_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC26_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC26_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC26_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC26_OEN_INV_SEL_V 0x1 #define GPIO_FUNC26_OEN_INV_SEL_S 11 /* GPIO_FUNC26_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC26_OEN_SEL (BIT(10)) +#define GPIO_FUNC26_OEN_SEL (BIT(10)) #define GPIO_FUNC26_OEN_SEL_M (BIT(10)) #define GPIO_FUNC26_OEN_SEL_V 0x1 #define GPIO_FUNC26_OEN_SEL_S 10 /* GPIO_FUNC26_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC26_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC26_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC26_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC26_OUT_INV_SEL_V 0x1 #define GPIO_FUNC26_OUT_INV_SEL_S 9 @@ -10100,7 +11112,7 @@ /* GPIO_FUNC26_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC26_OUT_SEL 0x000001FF +#define GPIO_FUNC26_OUT_SEL 0x000001FF #define GPIO_FUNC26_OUT_SEL_M ((GPIO_FUNC26_OUT_SEL_V)<<(GPIO_FUNC26_OUT_SEL_S)) #define GPIO_FUNC26_OUT_SEL_V 0x1FF #define GPIO_FUNC26_OUT_SEL_S 0 @@ -10108,28 +11120,31 @@ #define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x059c) /* GPIO_FUNC27_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC27_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC27_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC27_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC27_OEN_INV_SEL_V 0x1 #define GPIO_FUNC27_OEN_INV_SEL_S 11 /* GPIO_FUNC27_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC27_OEN_SEL (BIT(10)) +#define GPIO_FUNC27_OEN_SEL (BIT(10)) #define GPIO_FUNC27_OEN_SEL_M (BIT(10)) #define GPIO_FUNC27_OEN_SEL_V 0x1 #define GPIO_FUNC27_OEN_SEL_S 10 /* GPIO_FUNC27_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC27_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC27_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC27_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC27_OUT_INV_SEL_V 0x1 #define GPIO_FUNC27_OUT_INV_SEL_S 9 @@ -10137,7 +11152,7 @@ /* GPIO_FUNC27_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC27_OUT_SEL 0x000001FF +#define GPIO_FUNC27_OUT_SEL 0x000001FF #define GPIO_FUNC27_OUT_SEL_M ((GPIO_FUNC27_OUT_SEL_V)<<(GPIO_FUNC27_OUT_SEL_S)) #define GPIO_FUNC27_OUT_SEL_V 0x1FF #define GPIO_FUNC27_OUT_SEL_S 0 @@ -10145,28 +11160,31 @@ #define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05a0) /* GPIO_FUNC28_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC28_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC28_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC28_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC28_OEN_INV_SEL_V 0x1 #define GPIO_FUNC28_OEN_INV_SEL_S 11 /* GPIO_FUNC28_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC28_OEN_SEL (BIT(10)) +#define GPIO_FUNC28_OEN_SEL (BIT(10)) #define GPIO_FUNC28_OEN_SEL_M (BIT(10)) #define GPIO_FUNC28_OEN_SEL_V 0x1 #define GPIO_FUNC28_OEN_SEL_S 10 /* GPIO_FUNC28_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC28_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC28_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC28_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC28_OUT_INV_SEL_V 0x1 #define GPIO_FUNC28_OUT_INV_SEL_S 9 @@ -10174,7 +11192,7 @@ /* GPIO_FUNC28_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC28_OUT_SEL 0x000001FF +#define GPIO_FUNC28_OUT_SEL 0x000001FF #define GPIO_FUNC28_OUT_SEL_M ((GPIO_FUNC28_OUT_SEL_V)<<(GPIO_FUNC28_OUT_SEL_S)) #define GPIO_FUNC28_OUT_SEL_V 0x1FF #define GPIO_FUNC28_OUT_SEL_S 0 @@ -10182,28 +11200,31 @@ #define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05a4) /* GPIO_FUNC29_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC29_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC29_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC29_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC29_OEN_INV_SEL_V 0x1 #define GPIO_FUNC29_OEN_INV_SEL_S 11 /* GPIO_FUNC29_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC29_OEN_SEL (BIT(10)) +#define GPIO_FUNC29_OEN_SEL (BIT(10)) #define GPIO_FUNC29_OEN_SEL_M (BIT(10)) #define GPIO_FUNC29_OEN_SEL_V 0x1 #define GPIO_FUNC29_OEN_SEL_S 10 /* GPIO_FUNC29_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC29_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC29_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC29_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC29_OUT_INV_SEL_V 0x1 #define GPIO_FUNC29_OUT_INV_SEL_S 9 @@ -10211,7 +11232,7 @@ /* GPIO_FUNC29_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC29_OUT_SEL 0x000001FF +#define GPIO_FUNC29_OUT_SEL 0x000001FF #define GPIO_FUNC29_OUT_SEL_M ((GPIO_FUNC29_OUT_SEL_V)<<(GPIO_FUNC29_OUT_SEL_S)) #define GPIO_FUNC29_OUT_SEL_V 0x1FF #define GPIO_FUNC29_OUT_SEL_S 0 @@ -10219,28 +11240,31 @@ #define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05a8) /* GPIO_FUNC30_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC30_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC30_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC30_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC30_OEN_INV_SEL_V 0x1 #define GPIO_FUNC30_OEN_INV_SEL_S 11 /* GPIO_FUNC30_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC30_OEN_SEL (BIT(10)) +#define GPIO_FUNC30_OEN_SEL (BIT(10)) #define GPIO_FUNC30_OEN_SEL_M (BIT(10)) #define GPIO_FUNC30_OEN_SEL_V 0x1 #define GPIO_FUNC30_OEN_SEL_S 10 /* GPIO_FUNC30_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC30_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC30_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC30_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC30_OUT_INV_SEL_V 0x1 #define GPIO_FUNC30_OUT_INV_SEL_S 9 @@ -10248,7 +11272,7 @@ /* GPIO_FUNC30_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC30_OUT_SEL 0x000001FF +#define GPIO_FUNC30_OUT_SEL 0x000001FF #define GPIO_FUNC30_OUT_SEL_M ((GPIO_FUNC30_OUT_SEL_V)<<(GPIO_FUNC30_OUT_SEL_S)) #define GPIO_FUNC30_OUT_SEL_V 0x1FF #define GPIO_FUNC30_OUT_SEL_S 0 @@ -10256,28 +11280,31 @@ #define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05ac) /* GPIO_FUNC31_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC31_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC31_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC31_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC31_OEN_INV_SEL_V 0x1 #define GPIO_FUNC31_OEN_INV_SEL_S 11 /* GPIO_FUNC31_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC31_OEN_SEL (BIT(10)) +#define GPIO_FUNC31_OEN_SEL (BIT(10)) #define GPIO_FUNC31_OEN_SEL_M (BIT(10)) #define GPIO_FUNC31_OEN_SEL_V 0x1 #define GPIO_FUNC31_OEN_SEL_S 10 /* GPIO_FUNC31_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC31_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC31_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC31_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC31_OUT_INV_SEL_V 0x1 #define GPIO_FUNC31_OUT_INV_SEL_S 9 @@ -10285,7 +11312,7 @@ /* GPIO_FUNC31_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC31_OUT_SEL 0x000001FF +#define GPIO_FUNC31_OUT_SEL 0x000001FF #define GPIO_FUNC31_OUT_SEL_M ((GPIO_FUNC31_OUT_SEL_V)<<(GPIO_FUNC31_OUT_SEL_S)) #define GPIO_FUNC31_OUT_SEL_V 0x1FF #define GPIO_FUNC31_OUT_SEL_S 0 @@ -10293,28 +11320,31 @@ #define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05b0) /* GPIO_FUNC32_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC32_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC32_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC32_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC32_OEN_INV_SEL_V 0x1 #define GPIO_FUNC32_OEN_INV_SEL_S 11 /* GPIO_FUNC32_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC32_OEN_SEL (BIT(10)) +#define GPIO_FUNC32_OEN_SEL (BIT(10)) #define GPIO_FUNC32_OEN_SEL_M (BIT(10)) #define GPIO_FUNC32_OEN_SEL_V 0x1 #define GPIO_FUNC32_OEN_SEL_S 10 /* GPIO_FUNC32_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC32_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC32_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC32_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC32_OUT_INV_SEL_V 0x1 #define GPIO_FUNC32_OUT_INV_SEL_S 9 @@ -10322,7 +11352,7 @@ /* GPIO_FUNC32_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC32_OUT_SEL 0x000001FF +#define GPIO_FUNC32_OUT_SEL 0x000001FF #define GPIO_FUNC32_OUT_SEL_M ((GPIO_FUNC32_OUT_SEL_V)<<(GPIO_FUNC32_OUT_SEL_S)) #define GPIO_FUNC32_OUT_SEL_V 0x1FF #define GPIO_FUNC32_OUT_SEL_S 0 @@ -10330,28 +11360,31 @@ #define GPIO_FUNC33_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05b4) /* GPIO_FUNC33_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC33_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC33_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC33_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC33_OEN_INV_SEL_V 0x1 #define GPIO_FUNC33_OEN_INV_SEL_S 11 /* GPIO_FUNC33_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC33_OEN_SEL (BIT(10)) +#define GPIO_FUNC33_OEN_SEL (BIT(10)) #define GPIO_FUNC33_OEN_SEL_M (BIT(10)) #define GPIO_FUNC33_OEN_SEL_V 0x1 #define GPIO_FUNC33_OEN_SEL_S 10 /* GPIO_FUNC33_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC33_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC33_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC33_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC33_OUT_INV_SEL_V 0x1 #define GPIO_FUNC33_OUT_INV_SEL_S 9 @@ -10359,7 +11392,7 @@ /* GPIO_FUNC33_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC33_OUT_SEL 0x000001FF +#define GPIO_FUNC33_OUT_SEL 0x000001FF #define GPIO_FUNC33_OUT_SEL_M ((GPIO_FUNC33_OUT_SEL_V)<<(GPIO_FUNC33_OUT_SEL_S)) #define GPIO_FUNC33_OUT_SEL_V 0x1FF #define GPIO_FUNC33_OUT_SEL_S 0 @@ -10367,28 +11400,31 @@ #define GPIO_FUNC34_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05b8) /* GPIO_FUNC34_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC34_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC34_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC34_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC34_OEN_INV_SEL_V 0x1 #define GPIO_FUNC34_OEN_INV_SEL_S 11 /* GPIO_FUNC34_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC34_OEN_SEL (BIT(10)) +#define GPIO_FUNC34_OEN_SEL (BIT(10)) #define GPIO_FUNC34_OEN_SEL_M (BIT(10)) #define GPIO_FUNC34_OEN_SEL_V 0x1 #define GPIO_FUNC34_OEN_SEL_S 10 /* GPIO_FUNC34_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC34_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC34_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC34_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC34_OUT_INV_SEL_V 0x1 #define GPIO_FUNC34_OUT_INV_SEL_S 9 @@ -10396,7 +11432,7 @@ /* GPIO_FUNC34_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC34_OUT_SEL 0x000001FF +#define GPIO_FUNC34_OUT_SEL 0x000001FF #define GPIO_FUNC34_OUT_SEL_M ((GPIO_FUNC34_OUT_SEL_V)<<(GPIO_FUNC34_OUT_SEL_S)) #define GPIO_FUNC34_OUT_SEL_V 0x1FF #define GPIO_FUNC34_OUT_SEL_S 0 @@ -10404,28 +11440,31 @@ #define GPIO_FUNC35_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05bc) /* GPIO_FUNC35_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC35_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC35_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC35_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC35_OEN_INV_SEL_V 0x1 #define GPIO_FUNC35_OEN_INV_SEL_S 11 /* GPIO_FUNC35_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC35_OEN_SEL (BIT(10)) +#define GPIO_FUNC35_OEN_SEL (BIT(10)) #define GPIO_FUNC35_OEN_SEL_M (BIT(10)) #define GPIO_FUNC35_OEN_SEL_V 0x1 #define GPIO_FUNC35_OEN_SEL_S 10 /* GPIO_FUNC35_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC35_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC35_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC35_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC35_OUT_INV_SEL_V 0x1 #define GPIO_FUNC35_OUT_INV_SEL_S 9 @@ -10433,7 +11472,7 @@ /* GPIO_FUNC35_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC35_OUT_SEL 0x000001FF +#define GPIO_FUNC35_OUT_SEL 0x000001FF #define GPIO_FUNC35_OUT_SEL_M ((GPIO_FUNC35_OUT_SEL_V)<<(GPIO_FUNC35_OUT_SEL_S)) #define GPIO_FUNC35_OUT_SEL_V 0x1FF #define GPIO_FUNC35_OUT_SEL_S 0 @@ -10441,28 +11480,31 @@ #define GPIO_FUNC36_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05c0) /* GPIO_FUNC36_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC36_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC36_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC36_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC36_OEN_INV_SEL_V 0x1 #define GPIO_FUNC36_OEN_INV_SEL_S 11 /* GPIO_FUNC36_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC36_OEN_SEL (BIT(10)) +#define GPIO_FUNC36_OEN_SEL (BIT(10)) #define GPIO_FUNC36_OEN_SEL_M (BIT(10)) #define GPIO_FUNC36_OEN_SEL_V 0x1 #define GPIO_FUNC36_OEN_SEL_S 10 /* GPIO_FUNC36_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC36_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC36_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC36_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC36_OUT_INV_SEL_V 0x1 #define GPIO_FUNC36_OUT_INV_SEL_S 9 @@ -10470,7 +11512,7 @@ /* GPIO_FUNC36_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC36_OUT_SEL 0x000001FF +#define GPIO_FUNC36_OUT_SEL 0x000001FF #define GPIO_FUNC36_OUT_SEL_M ((GPIO_FUNC36_OUT_SEL_V)<<(GPIO_FUNC36_OUT_SEL_S)) #define GPIO_FUNC36_OUT_SEL_V 0x1FF #define GPIO_FUNC36_OUT_SEL_S 0 @@ -10478,28 +11520,31 @@ #define GPIO_FUNC37_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05c4) /* GPIO_FUNC37_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC37_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC37_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC37_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC37_OEN_INV_SEL_V 0x1 #define GPIO_FUNC37_OEN_INV_SEL_S 11 /* GPIO_FUNC37_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC37_OEN_SEL (BIT(10)) +#define GPIO_FUNC37_OEN_SEL (BIT(10)) #define GPIO_FUNC37_OEN_SEL_M (BIT(10)) #define GPIO_FUNC37_OEN_SEL_V 0x1 #define GPIO_FUNC37_OEN_SEL_S 10 /* GPIO_FUNC37_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC37_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC37_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC37_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC37_OUT_INV_SEL_V 0x1 #define GPIO_FUNC37_OUT_INV_SEL_S 9 @@ -10507,7 +11552,7 @@ /* GPIO_FUNC37_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC37_OUT_SEL 0x000001FF +#define GPIO_FUNC37_OUT_SEL 0x000001FF #define GPIO_FUNC37_OUT_SEL_M ((GPIO_FUNC37_OUT_SEL_V)<<(GPIO_FUNC37_OUT_SEL_S)) #define GPIO_FUNC37_OUT_SEL_V 0x1FF #define GPIO_FUNC37_OUT_SEL_S 0 @@ -10515,28 +11560,31 @@ #define GPIO_FUNC38_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05c8) /* GPIO_FUNC38_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC38_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC38_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC38_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC38_OEN_INV_SEL_V 0x1 #define GPIO_FUNC38_OEN_INV_SEL_S 11 /* GPIO_FUNC38_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC38_OEN_SEL (BIT(10)) +#define GPIO_FUNC38_OEN_SEL (BIT(10)) #define GPIO_FUNC38_OEN_SEL_M (BIT(10)) #define GPIO_FUNC38_OEN_SEL_V 0x1 #define GPIO_FUNC38_OEN_SEL_S 10 /* GPIO_FUNC38_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC38_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC38_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC38_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC38_OUT_INV_SEL_V 0x1 #define GPIO_FUNC38_OUT_INV_SEL_S 9 @@ -10544,7 +11592,7 @@ /* GPIO_FUNC38_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC38_OUT_SEL 0x000001FF +#define GPIO_FUNC38_OUT_SEL 0x000001FF #define GPIO_FUNC38_OUT_SEL_M ((GPIO_FUNC38_OUT_SEL_V)<<(GPIO_FUNC38_OUT_SEL_S)) #define GPIO_FUNC38_OUT_SEL_V 0x1FF #define GPIO_FUNC38_OUT_SEL_S 0 @@ -10552,28 +11600,31 @@ #define GPIO_FUNC39_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x05cc) /* GPIO_FUNC39_OEN_INV_SEL : R/W ;bitpos:[11] ;default: x ; */ -/* Description: invert the output enable value if you want to revert the output - enable value setting the value to 1 */ +/* Description: invert the output enable value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC39_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC39_OEN_INV_SEL (BIT(11)) #define GPIO_FUNC39_OEN_INV_SEL_M (BIT(11)) #define GPIO_FUNC39_OEN_INV_SEL_V 0x1 #define GPIO_FUNC39_OEN_INV_SEL_S 11 /* GPIO_FUNC39_OEN_SEL : R/W ;bitpos:[10] ;default: x ; */ -/* Description: weather using the logical oen signal or not using the value setting - by the register */ +/* Description: weather using the logical oen signal or not using the + * value setting by the register. + */ -#define GPIO_FUNC39_OEN_SEL (BIT(10)) +#define GPIO_FUNC39_OEN_SEL (BIT(10)) #define GPIO_FUNC39_OEN_SEL_M (BIT(10)) #define GPIO_FUNC39_OEN_SEL_V 0x1 #define GPIO_FUNC39_OEN_SEL_S 10 /* GPIO_FUNC39_OUT_INV_SEL : R/W ;bitpos:[9] ;default: x ; */ -/* Description: invert the output value if you want to revert the output value - setting the value to 1 */ +/* Description: invert the output value if you want to revert the + * output enable value setting the value to 1. + */ -#define GPIO_FUNC39_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC39_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC39_OUT_INV_SEL_M (BIT(9)) #define GPIO_FUNC39_OUT_INV_SEL_V 0x1 #define GPIO_FUNC39_OUT_INV_SEL_S 9 @@ -10581,7 +11632,7 @@ /* GPIO_FUNC39_OUT_SEL : R/W ;bitpos:[8:0] ;default: x ; */ /* Description: select one of the 256 output to 40 GPIO */ -#define GPIO_FUNC39_OUT_SEL 0x000001FF +#define GPIO_FUNC39_OUT_SEL 0x000001FF #define GPIO_FUNC39_OUT_SEL_M ((GPIO_FUNC39_OUT_SEL_V)<<(GPIO_FUNC39_OUT_SEL_S)) #define GPIO_FUNC39_OUT_SEL_V 0x1FF #define GPIO_FUNC39_OUT_SEL_S 0 -- GitLab From 650757bbf05073b91cba52f7022a0c55039013f4 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 26 Oct 2016 12:11:24 -0600 Subject: [PATCH 218/734] ESP32: Add GPIO support --- arch/xtensa/include/esp32/irq.h | 33 +- arch/xtensa/src/common/xtensa_context.S | 1 + arch/xtensa/src/esp32/Kconfig | 5 + arch/xtensa/src/esp32/chip/esp32_gpio.h | 418 +++++++++++----------- arch/xtensa/src/esp32/chip/esp32_iomux.h | 288 +++++++++++++++ arch/xtensa/src/esp32/esp32_cpuint.c | 222 +++++------- arch/xtensa/src/esp32/esp32_cpuint.h | 22 +- arch/xtensa/src/esp32/esp32_cpustart.c | 2 +- arch/xtensa/src/esp32/esp32_gpio.c | 423 +++++++++++++++++++++++ arch/xtensa/src/esp32/esp32_gpio.h | 185 ++++++++++ arch/xtensa/src/esp32/esp32_irq.c | 4 +- 11 files changed, 1241 insertions(+), 362 deletions(-) create mode 100644 arch/xtensa/src/esp32/chip/esp32_iomux.h create mode 100644 arch/xtensa/src/esp32/esp32_gpio.c create mode 100644 arch/xtensa/src/esp32/esp32_gpio.h diff --git a/arch/xtensa/include/esp32/irq.h b/arch/xtensa/include/esp32/irq.h index 46b20fb552..590e6d28cb 100644 --- a/arch/xtensa/include/esp32/irq.h +++ b/arch/xtensa/include/esp32/irq.h @@ -163,7 +163,7 @@ /* Total number of peripherals */ -#define NR_PERIPHERALS 69 +#define ESP32_NPERIPHERALS 69 /* Exceptions * @@ -192,6 +192,7 @@ #define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */ #define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */ +#define XTENSA_NIRQ_INTERNAL 3 /* Number of dispatch internal interrupts */ #define XTENSA_IRQ_FIRSTPERIPH 3 /* First peripheral IRQ number */ /* IRQ numbers for peripheral interrupts coming throught the Interrupt @@ -287,9 +288,26 @@ #define ESP32_IRQ_SREG2 ESP32_IRQ_TG1_WDT_EDGE #define ESP32_NIRQS_SREG2 5 +#define ESP32_NIRQ_PERIPH ESP32_NPERIPHERALS + +/* Second level GPIO interrupts. GPIO interrupts are decoded and dispatched as + * a second level of decoding: The first level dispatches to the GPIO interrupt + * handler. The second to the decoded GPIO interrupt handler. + */ + +#ifdef CONFIG_ESP32_GPIO_IRQ +# define ESP32_NIRQ_GPIO 40 +# define ESP32_FIRST_GPIOIRQ (XTENSA_NIRQ_INTERNAL+ESP32_NIRQ_PERIPH) +# define ESP32_LAST_GPIOIRQ (ESP32_FIRST_GPIOIRQ+ESP32_NIRQ_GPIO-1) +# define ESP32_PIN2IRQ(p) ((p) + ESP32_FIRST_GPIOIRQ) +# define ESP32_IRQ2PIN(i) ((i) - ESP32_FIRST_GPIOIRQ) +#else +# define ESP32_NIRQ_GPIO 0 +#endif + /* Total number of interrupts */ -#define NR_IRQS (ESP32_IRQ_CACHE_IA+1) +#define NR_IRQS (XTENSA_NIRQ_INTERNAL+ESP32_NIRQ_PERIPH+ESP32_NIRQ_GPIO) /* CPU Interrupts. * @@ -347,23 +365,32 @@ #define ESP32_CPUINT_LEVELPERIPH_18 26 #define ESP32_CPUINT_LEVELPERIPH_19 27 #define ESP32_CPUINT_LEVELPERIPH_20 31 + #define ESP32_CPUINT_NLEVELPERIPHS 21 +#define EPS32_CPUINT_LEVELSET 0x8fbe333f #define ESP32_CPUINT_EDGEPERIPH_0 10 #define ESP32_CPUINT_EDGEPERIPH_1 22 #define ESP32_CPUINT_EDGEPERIPH_2 28 #define ESP32_CPUINT_EDGEPERIPH_3 30 + #define ESP32_CPUINT_NEDGEPERIPHS 4 +#define EPS32_CPUINT_EDGESET 0x50400400 + +#define ESP32_CPUINT_NNMIPERIPHS 4 +#define EPS32_CPUINT_NMISET 0x00004000 #define ESP32_CPUINT_TIMER0 6 #define ESP32_CPUINT_SOFTWARE0 7 +#define ESP32_CPUINT_PROFILING 11 #define ESP32_CPUINT_TIMER1 15 #define ESP32_CPUINT_TIMER2 16 #define ESP32_CPUINT_SOFTWARE1 29 + #define ESP32_CPUINT_NINTERNAL 5 #define ESP32_CPUINT_MAX 31 -#define EPS32_CPUINT_PERIPHSET 0xdffe7f3f +#define EPS32_CPUINT_PERIPHSET 0xdffe6f3f #define EPS32_CPUINT_INTERNALSET 0x200180c0 /* Priority 1: 0-10, 12-13, 17-18 (15) diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index c3c0835232..3e41111a60 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -419,3 +419,4 @@ xtensa_context_restore: l32i a0, a2, (4 * REG_A0) /* Restore a0 */ l32i a2, a2, (4 * REG_A2) /* Restore A2 */ rfe /* And return from "exception" */ + diff --git a/arch/xtensa/src/esp32/Kconfig b/arch/xtensa/src/esp32/Kconfig index 3d7592362c..a3ad7fcaa9 100644 --- a/arch/xtensa/src/esp32/Kconfig +++ b/arch/xtensa/src/esp32/Kconfig @@ -193,6 +193,11 @@ config ESP32_WIRELESS endmenu # ESP32 Peripheral Selection +config ESP32_GPIO_IRQ + bool "GPIO pin interrupts" + ---help--- + Enable support for interrupting GPIO pins + config ESP32_BT_RESERVE_DRAM int "Reserved BT DRAM" default 0 diff --git a/arch/xtensa/src/esp32/chip/esp32_gpio.h b/arch/xtensa/src/esp32/chip/esp32_gpio.h index ebdfc44292..14321ff103 100644 --- a/arch/xtensa/src/esp32/chip/esp32_gpio.h +++ b/arch/xtensa/src/esp32/chip/esp32_gpio.h @@ -367,29 +367,33 @@ /* GPIO_SDIO_INT_H : RO ;bitpos:[7:0] ;default: x ; */ /* Description: SDIO's extent GPIO32~39 interrupt */ -#define GPIO_SDIO_INT_H 0x000000FF +#define GPIO_SDIO_INT_H 0x000000FF #define GPIO_SDIO_INT_H_M ((GPIO_SDIO_INT_H_V)<<(GPIO_SDIO_INT_H_S)) #define GPIO_SDIO_INT_H_V 0xFF #define GPIO_SDIO_INT_H_S 0 -#define GPIO_REG(io_num) (GPIO_PIN0_REG + (io_num)*0x4) -#define GPIO_PIN_INT_ENA 0x0000001F +#define GPIO_REG(io_num) (GPIO_PIN0_REG + (io_num)*0x4) +#define GPIO_PIN_INT_ENA 0x0000001F #define GPIO_PIN_INT_ENA_M ((GPIO_PIN_INT_ENA_V)<<(GPIO_PIN_INT_ENA_S)) #define GPIO_PIN_INT_ENA_V 0x0000001F #define GPIO_PIN_INT_ENA_S 13 -#define GPIO_PIN_CONFIG 0x00000003 + +#define GPIO_PIN_CONFIG 0x00000003 #define GPIO_PIN_CONFIG_M ((GPIO_PIN_CONFIG_V)<<(GPIO_PIN_CONFIG_S)) #define GPIO_PIN_CONFIG_V 0x00000003 #define GPIO_PIN_CONFIG_S 11 -#define GPIO_PIN_WAKEUP_ENABLE (BIT(10)) + +#define GPIO_PIN_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN_WAKEUP_ENABLE_S 10 -#define GPIO_PIN_INT_TYPE 0x00000007 + +#define GPIO_PIN_INT_TYPE 0x00000007 #define GPIO_PIN_INT_TYPE_M ((GPIO_PIN_INT_TYPE_V)<<(GPIO_PIN_INT_TYPE_S)) #define GPIO_PIN_INT_TYPE_V 0x00000007 #define GPIO_PIN_INT_TYPE_S 7 -#define GPIO_PIN_PAD_DRIVER (BIT(2)) + +#define GPIO_PIN_PAD_DRIVER (BIT(2)) #define GPIO_PIN_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN_PAD_DRIVER_V 0x1 #define GPIO_PIN_PAD_DRIVER_S 2 @@ -402,7 +406,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN0_INT_ENA 0x0000001F +#define GPIO_PIN0_INT_ENA 0x0000001F #define GPIO_PIN0_INT_ENA_M ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S)) #define GPIO_PIN0_INT_ENA_V 0x1F #define GPIO_PIN0_INT_ENA_S 13 @@ -410,7 +414,7 @@ /* GPIO_PIN0_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN0_CONFIG 0x00000003 +#define GPIO_PIN0_CONFIG 0x00000003 #define GPIO_PIN0_CONFIG_M ((GPIO_PIN0_CONFIG_V)<<(GPIO_PIN0_CONFIG_S)) #define GPIO_PIN0_CONFIG_V 0x3 #define GPIO_PIN0_CONFIG_S 11 @@ -418,7 +422,7 @@ /* GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN0_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN0_WAKEUP_ENABLE_S 10 @@ -429,7 +433,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN0_INT_TYPE 0x00000007 +#define GPIO_PIN0_INT_TYPE 0x00000007 #define GPIO_PIN0_INT_TYPE_M ((GPIO_PIN0_INT_TYPE_V)<<(GPIO_PIN0_INT_TYPE_S)) #define GPIO_PIN0_INT_TYPE_V 0x7 #define GPIO_PIN0_INT_TYPE_S 7 @@ -437,7 +441,7 @@ /* GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER (BIT(2)) #define GPIO_PIN0_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN0_PAD_DRIVER_V 0x1 #define GPIO_PIN0_PAD_DRIVER_S 2 @@ -450,7 +454,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN1_INT_ENA 0x0000001F +#define GPIO_PIN1_INT_ENA 0x0000001F #define GPIO_PIN1_INT_ENA_M ((GPIO_PIN1_INT_ENA_V)<<(GPIO_PIN1_INT_ENA_S)) #define GPIO_PIN1_INT_ENA_V 0x1F #define GPIO_PIN1_INT_ENA_S 13 @@ -458,7 +462,7 @@ /* GPIO_PIN1_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN1_CONFIG 0x00000003 +#define GPIO_PIN1_CONFIG 0x00000003 #define GPIO_PIN1_CONFIG_M ((GPIO_PIN1_CONFIG_V)<<(GPIO_PIN1_CONFIG_S)) #define GPIO_PIN1_CONFIG_V 0x3 #define GPIO_PIN1_CONFIG_S 11 @@ -466,7 +470,7 @@ /* GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN1_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN1_WAKEUP_ENABLE_S 10 @@ -477,7 +481,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN1_INT_TYPE 0x00000007 +#define GPIO_PIN1_INT_TYPE 0x00000007 #define GPIO_PIN1_INT_TYPE_M ((GPIO_PIN1_INT_TYPE_V)<<(GPIO_PIN1_INT_TYPE_S)) #define GPIO_PIN1_INT_TYPE_V 0x7 #define GPIO_PIN1_INT_TYPE_S 7 @@ -485,7 +489,7 @@ /* GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER (BIT(2)) #define GPIO_PIN1_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN1_PAD_DRIVER_V 0x1 #define GPIO_PIN1_PAD_DRIVER_S 2 @@ -498,7 +502,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN2_INT_ENA 0x0000001F +#define GPIO_PIN2_INT_ENA 0x0000001F #define GPIO_PIN2_INT_ENA_M ((GPIO_PIN2_INT_ENA_V)<<(GPIO_PIN2_INT_ENA_S)) #define GPIO_PIN2_INT_ENA_V 0x1F #define GPIO_PIN2_INT_ENA_S 13 @@ -506,7 +510,7 @@ /* GPIO_PIN2_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN2_CONFIG 0x00000003 +#define GPIO_PIN2_CONFIG 0x00000003 #define GPIO_PIN2_CONFIG_M ((GPIO_PIN2_CONFIG_V)<<(GPIO_PIN2_CONFIG_S)) #define GPIO_PIN2_CONFIG_V 0x3 #define GPIO_PIN2_CONFIG_S 11 @@ -514,7 +518,7 @@ /* GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN2_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN2_WAKEUP_ENABLE_S 10 @@ -525,7 +529,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN2_INT_TYPE 0x00000007 +#define GPIO_PIN2_INT_TYPE 0x00000007 #define GPIO_PIN2_INT_TYPE_M ((GPIO_PIN2_INT_TYPE_V)<<(GPIO_PIN2_INT_TYPE_S)) #define GPIO_PIN2_INT_TYPE_V 0x7 #define GPIO_PIN2_INT_TYPE_S 7 @@ -533,7 +537,7 @@ /* GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER (BIT(2)) #define GPIO_PIN2_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN2_PAD_DRIVER_V 0x1 #define GPIO_PIN2_PAD_DRIVER_S 2 @@ -546,7 +550,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN3_INT_ENA 0x0000001F +#define GPIO_PIN3_INT_ENA 0x0000001F #define GPIO_PIN3_INT_ENA_M ((GPIO_PIN3_INT_ENA_V)<<(GPIO_PIN3_INT_ENA_S)) #define GPIO_PIN3_INT_ENA_V 0x1F #define GPIO_PIN3_INT_ENA_S 13 @@ -554,7 +558,7 @@ /* GPIO_PIN3_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN3_CONFIG 0x00000003 +#define GPIO_PIN3_CONFIG 0x00000003 #define GPIO_PIN3_CONFIG_M ((GPIO_PIN3_CONFIG_V)<<(GPIO_PIN3_CONFIG_S)) #define GPIO_PIN3_CONFIG_V 0x3 #define GPIO_PIN3_CONFIG_S 11 @@ -562,7 +566,7 @@ /* GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN3_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN3_WAKEUP_ENABLE_S 10 @@ -573,7 +577,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN3_INT_TYPE 0x00000007 +#define GPIO_PIN3_INT_TYPE 0x00000007 #define GPIO_PIN3_INT_TYPE_M ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S)) #define GPIO_PIN3_INT_TYPE_V 0x7 #define GPIO_PIN3_INT_TYPE_S 7 @@ -581,7 +585,7 @@ /* GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER (BIT(2)) #define GPIO_PIN3_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN3_PAD_DRIVER_V 0x1 #define GPIO_PIN3_PAD_DRIVER_S 2 @@ -594,7 +598,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN4_INT_ENA 0x0000001F +#define GPIO_PIN4_INT_ENA 0x0000001F #define GPIO_PIN4_INT_ENA_M ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S)) #define GPIO_PIN4_INT_ENA_V 0x1F #define GPIO_PIN4_INT_ENA_S 13 @@ -602,7 +606,7 @@ /* GPIO_PIN4_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN4_CONFIG 0x00000003 +#define GPIO_PIN4_CONFIG 0x00000003 #define GPIO_PIN4_CONFIG_M ((GPIO_PIN4_CONFIG_V)<<(GPIO_PIN4_CONFIG_S)) #define GPIO_PIN4_CONFIG_V 0x3 #define GPIO_PIN4_CONFIG_S 11 @@ -610,7 +614,7 @@ /* GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN4_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN4_WAKEUP_ENABLE_S 10 @@ -621,7 +625,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN4_INT_TYPE 0x00000007 +#define GPIO_PIN4_INT_TYPE 0x00000007 #define GPIO_PIN4_INT_TYPE_M ((GPIO_PIN4_INT_TYPE_V)<<(GPIO_PIN4_INT_TYPE_S)) #define GPIO_PIN4_INT_TYPE_V 0x7 #define GPIO_PIN4_INT_TYPE_S 7 @@ -629,7 +633,7 @@ /* GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER (BIT(2)) #define GPIO_PIN4_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN4_PAD_DRIVER_V 0x1 #define GPIO_PIN4_PAD_DRIVER_S 2 @@ -642,7 +646,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN5_INT_ENA 0x0000001F +#define GPIO_PIN5_INT_ENA 0x0000001F #define GPIO_PIN5_INT_ENA_M ((GPIO_PIN5_INT_ENA_V)<<(GPIO_PIN5_INT_ENA_S)) #define GPIO_PIN5_INT_ENA_V 0x1F #define GPIO_PIN5_INT_ENA_S 13 @@ -650,7 +654,7 @@ /* GPIO_PIN5_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN5_CONFIG 0x00000003 +#define GPIO_PIN5_CONFIG 0x00000003 #define GPIO_PIN5_CONFIG_M ((GPIO_PIN5_CONFIG_V)<<(GPIO_PIN5_CONFIG_S)) #define GPIO_PIN5_CONFIG_V 0x3 #define GPIO_PIN5_CONFIG_S 11 @@ -658,7 +662,7 @@ /* GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN5_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN5_WAKEUP_ENABLE_S 10 @@ -669,7 +673,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN5_INT_TYPE 0x00000007 +#define GPIO_PIN5_INT_TYPE 0x00000007 #define GPIO_PIN5_INT_TYPE_M ((GPIO_PIN5_INT_TYPE_V)<<(GPIO_PIN5_INT_TYPE_S)) #define GPIO_PIN5_INT_TYPE_V 0x7 #define GPIO_PIN5_INT_TYPE_S 7 @@ -677,7 +681,7 @@ /* GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER (BIT(2)) #define GPIO_PIN5_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN5_PAD_DRIVER_V 0x1 #define GPIO_PIN5_PAD_DRIVER_S 2 @@ -690,7 +694,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN6_INT_ENA 0x0000001F +#define GPIO_PIN6_INT_ENA 0x0000001F #define GPIO_PIN6_INT_ENA_M ((GPIO_PIN6_INT_ENA_V)<<(GPIO_PIN6_INT_ENA_S)) #define GPIO_PIN6_INT_ENA_V 0x1F #define GPIO_PIN6_INT_ENA_S 13 @@ -698,7 +702,7 @@ /* GPIO_PIN6_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN6_CONFIG 0x00000003 +#define GPIO_PIN6_CONFIG 0x00000003 #define GPIO_PIN6_CONFIG_M ((GPIO_PIN6_CONFIG_V)<<(GPIO_PIN6_CONFIG_S)) #define GPIO_PIN6_CONFIG_V 0x3 #define GPIO_PIN6_CONFIG_S 11 @@ -706,7 +710,7 @@ /* GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN6_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN6_WAKEUP_ENABLE_S 10 @@ -717,7 +721,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN6_INT_TYPE 0x00000007 +#define GPIO_PIN6_INT_TYPE 0x00000007 #define GPIO_PIN6_INT_TYPE_M ((GPIO_PIN6_INT_TYPE_V)<<(GPIO_PIN6_INT_TYPE_S)) #define GPIO_PIN6_INT_TYPE_V 0x7 #define GPIO_PIN6_INT_TYPE_S 7 @@ -725,7 +729,7 @@ /* GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER (BIT(2)) #define GPIO_PIN6_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN6_PAD_DRIVER_V 0x1 #define GPIO_PIN6_PAD_DRIVER_S 2 @@ -738,7 +742,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN7_INT_ENA 0x0000001F +#define GPIO_PIN7_INT_ENA 0x0000001F #define GPIO_PIN7_INT_ENA_M ((GPIO_PIN7_INT_ENA_V)<<(GPIO_PIN7_INT_ENA_S)) #define GPIO_PIN7_INT_ENA_V 0x1F #define GPIO_PIN7_INT_ENA_S 13 @@ -746,7 +750,7 @@ /* GPIO_PIN7_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN7_CONFIG 0x00000003 +#define GPIO_PIN7_CONFIG 0x00000003 #define GPIO_PIN7_CONFIG_M ((GPIO_PIN7_CONFIG_V)<<(GPIO_PIN7_CONFIG_S)) #define GPIO_PIN7_CONFIG_V 0x3 #define GPIO_PIN7_CONFIG_S 11 @@ -754,7 +758,7 @@ /* GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN7_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN7_WAKEUP_ENABLE_S 10 @@ -765,7 +769,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN7_INT_TYPE 0x00000007 +#define GPIO_PIN7_INT_TYPE 0x00000007 #define GPIO_PIN7_INT_TYPE_M ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S)) #define GPIO_PIN7_INT_TYPE_V 0x7 #define GPIO_PIN7_INT_TYPE_S 7 @@ -773,7 +777,7 @@ /* GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER (BIT(2)) #define GPIO_PIN7_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN7_PAD_DRIVER_V 0x1 #define GPIO_PIN7_PAD_DRIVER_S 2 @@ -786,7 +790,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN8_INT_ENA 0x0000001F +#define GPIO_PIN8_INT_ENA 0x0000001F #define GPIO_PIN8_INT_ENA_M ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S)) #define GPIO_PIN8_INT_ENA_V 0x1F #define GPIO_PIN8_INT_ENA_S 13 @@ -794,7 +798,7 @@ /* GPIO_PIN8_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN8_CONFIG 0x00000003 +#define GPIO_PIN8_CONFIG 0x00000003 #define GPIO_PIN8_CONFIG_M ((GPIO_PIN8_CONFIG_V)<<(GPIO_PIN8_CONFIG_S)) #define GPIO_PIN8_CONFIG_V 0x3 #define GPIO_PIN8_CONFIG_S 11 @@ -802,7 +806,7 @@ /* GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN8_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN8_WAKEUP_ENABLE_S 10 @@ -813,7 +817,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN8_INT_TYPE 0x00000007 +#define GPIO_PIN8_INT_TYPE 0x00000007 #define GPIO_PIN8_INT_TYPE_M ((GPIO_PIN8_INT_TYPE_V)<<(GPIO_PIN8_INT_TYPE_S)) #define GPIO_PIN8_INT_TYPE_V 0x7 #define GPIO_PIN8_INT_TYPE_S 7 @@ -821,7 +825,7 @@ /* GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER (BIT(2)) #define GPIO_PIN8_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN8_PAD_DRIVER_V 0x1 #define GPIO_PIN8_PAD_DRIVER_S 2 @@ -834,7 +838,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN9_INT_ENA 0x0000001F +#define GPIO_PIN9_INT_ENA 0x0000001F #define GPIO_PIN9_INT_ENA_M ((GPIO_PIN9_INT_ENA_V)<<(GPIO_PIN9_INT_ENA_S)) #define GPIO_PIN9_INT_ENA_V 0x1F #define GPIO_PIN9_INT_ENA_S 13 @@ -842,7 +846,7 @@ /* GPIO_PIN9_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN9_CONFIG 0x00000003 +#define GPIO_PIN9_CONFIG 0x00000003 #define GPIO_PIN9_CONFIG_M ((GPIO_PIN9_CONFIG_V)<<(GPIO_PIN9_CONFIG_S)) #define GPIO_PIN9_CONFIG_V 0x3 #define GPIO_PIN9_CONFIG_S 11 @@ -850,7 +854,7 @@ /* GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN9_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN9_WAKEUP_ENABLE_S 10 @@ -861,7 +865,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN9_INT_TYPE 0x00000007 +#define GPIO_PIN9_INT_TYPE 0x00000007 #define GPIO_PIN9_INT_TYPE_M ((GPIO_PIN9_INT_TYPE_V)<<(GPIO_PIN9_INT_TYPE_S)) #define GPIO_PIN9_INT_TYPE_V 0x7 #define GPIO_PIN9_INT_TYPE_S 7 @@ -869,7 +873,7 @@ /* GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER (BIT(2)) #define GPIO_PIN9_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN9_PAD_DRIVER_V 0x1 #define GPIO_PIN9_PAD_DRIVER_S 2 @@ -882,7 +886,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN10_INT_ENA 0x0000001F +#define GPIO_PIN10_INT_ENA 0x0000001F #define GPIO_PIN10_INT_ENA_M ((GPIO_PIN10_INT_ENA_V)<<(GPIO_PIN10_INT_ENA_S)) #define GPIO_PIN10_INT_ENA_V 0x1F #define GPIO_PIN10_INT_ENA_S 13 @@ -890,7 +894,7 @@ /* GPIO_PIN10_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN10_CONFIG 0x00000003 +#define GPIO_PIN10_CONFIG 0x00000003 #define GPIO_PIN10_CONFIG_M ((GPIO_PIN10_CONFIG_V)<<(GPIO_PIN10_CONFIG_S)) #define GPIO_PIN10_CONFIG_V 0x3 #define GPIO_PIN10_CONFIG_S 11 @@ -898,7 +902,7 @@ /* GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN10_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN10_WAKEUP_ENABLE_S 10 @@ -909,7 +913,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN10_INT_TYPE 0x00000007 +#define GPIO_PIN10_INT_TYPE 0x00000007 #define GPIO_PIN10_INT_TYPE_M ((GPIO_PIN10_INT_TYPE_V)<<(GPIO_PIN10_INT_TYPE_S)) #define GPIO_PIN10_INT_TYPE_V 0x7 #define GPIO_PIN10_INT_TYPE_S 7 @@ -917,7 +921,7 @@ /* GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER (BIT(2)) #define GPIO_PIN10_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN10_PAD_DRIVER_V 0x1 #define GPIO_PIN10_PAD_DRIVER_S 2 @@ -930,7 +934,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN11_INT_ENA 0x0000001F +#define GPIO_PIN11_INT_ENA 0x0000001F #define GPIO_PIN11_INT_ENA_M ((GPIO_PIN11_INT_ENA_V)<<(GPIO_PIN11_INT_ENA_S)) #define GPIO_PIN11_INT_ENA_V 0x1F #define GPIO_PIN11_INT_ENA_S 13 @@ -938,7 +942,7 @@ /* GPIO_PIN11_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN11_CONFIG 0x00000003 +#define GPIO_PIN11_CONFIG 0x00000003 #define GPIO_PIN11_CONFIG_M ((GPIO_PIN11_CONFIG_V)<<(GPIO_PIN11_CONFIG_S)) #define GPIO_PIN11_CONFIG_V 0x3 #define GPIO_PIN11_CONFIG_S 11 @@ -946,7 +950,7 @@ /* GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN11_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN11_WAKEUP_ENABLE_S 10 @@ -957,7 +961,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN11_INT_TYPE 0x00000007 +#define GPIO_PIN11_INT_TYPE 0x00000007 #define GPIO_PIN11_INT_TYPE_M ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S)) #define GPIO_PIN11_INT_TYPE_V 0x7 #define GPIO_PIN11_INT_TYPE_S 7 @@ -965,7 +969,7 @@ /* GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER (BIT(2)) #define GPIO_PIN11_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN11_PAD_DRIVER_V 0x1 #define GPIO_PIN11_PAD_DRIVER_S 2 @@ -978,7 +982,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN12_INT_ENA 0x0000001F +#define GPIO_PIN12_INT_ENA 0x0000001F #define GPIO_PIN12_INT_ENA_M ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S)) #define GPIO_PIN12_INT_ENA_V 0x1F #define GPIO_PIN12_INT_ENA_S 13 @@ -986,7 +990,7 @@ /* GPIO_PIN12_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN12_CONFIG 0x00000003 +#define GPIO_PIN12_CONFIG 0x00000003 #define GPIO_PIN12_CONFIG_M ((GPIO_PIN12_CONFIG_V)<<(GPIO_PIN12_CONFIG_S)) #define GPIO_PIN12_CONFIG_V 0x3 #define GPIO_PIN12_CONFIG_S 11 @@ -994,7 +998,7 @@ /* GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN12_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN12_WAKEUP_ENABLE_S 10 @@ -1005,7 +1009,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN12_INT_TYPE 0x00000007 +#define GPIO_PIN12_INT_TYPE 0x00000007 #define GPIO_PIN12_INT_TYPE_M ((GPIO_PIN12_INT_TYPE_V)<<(GPIO_PIN12_INT_TYPE_S)) #define GPIO_PIN12_INT_TYPE_V 0x7 #define GPIO_PIN12_INT_TYPE_S 7 @@ -1013,7 +1017,7 @@ /* GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER (BIT(2)) #define GPIO_PIN12_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN12_PAD_DRIVER_V 0x1 #define GPIO_PIN12_PAD_DRIVER_S 2 @@ -1026,7 +1030,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN13_INT_ENA 0x0000001F +#define GPIO_PIN13_INT_ENA 0x0000001F #define GPIO_PIN13_INT_ENA_M ((GPIO_PIN13_INT_ENA_V)<<(GPIO_PIN13_INT_ENA_S)) #define GPIO_PIN13_INT_ENA_V 0x1F #define GPIO_PIN13_INT_ENA_S 13 @@ -1034,7 +1038,7 @@ /* GPIO_PIN13_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN13_CONFIG 0x00000003 +#define GPIO_PIN13_CONFIG 0x00000003 #define GPIO_PIN13_CONFIG_M ((GPIO_PIN13_CONFIG_V)<<(GPIO_PIN13_CONFIG_S)) #define GPIO_PIN13_CONFIG_V 0x3 #define GPIO_PIN13_CONFIG_S 11 @@ -1042,7 +1046,7 @@ /* GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN13_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN13_WAKEUP_ENABLE_S 10 @@ -1053,7 +1057,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN13_INT_TYPE 0x00000007 +#define GPIO_PIN13_INT_TYPE 0x00000007 #define GPIO_PIN13_INT_TYPE_M ((GPIO_PIN13_INT_TYPE_V)<<(GPIO_PIN13_INT_TYPE_S)) #define GPIO_PIN13_INT_TYPE_V 0x7 #define GPIO_PIN13_INT_TYPE_S 7 @@ -1061,7 +1065,7 @@ /* GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER (BIT(2)) #define GPIO_PIN13_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN13_PAD_DRIVER_V 0x1 #define GPIO_PIN13_PAD_DRIVER_S 2 @@ -1074,7 +1078,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN14_INT_ENA 0x0000001F +#define GPIO_PIN14_INT_ENA 0x0000001F #define GPIO_PIN14_INT_ENA_M ((GPIO_PIN14_INT_ENA_V)<<(GPIO_PIN14_INT_ENA_S)) #define GPIO_PIN14_INT_ENA_V 0x1F #define GPIO_PIN14_INT_ENA_S 13 @@ -1082,7 +1086,7 @@ /* GPIO_PIN14_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN14_CONFIG 0x00000003 +#define GPIO_PIN14_CONFIG 0x00000003 #define GPIO_PIN14_CONFIG_M ((GPIO_PIN14_CONFIG_V)<<(GPIO_PIN14_CONFIG_S)) #define GPIO_PIN14_CONFIG_V 0x3 #define GPIO_PIN14_CONFIG_S 11 @@ -1090,7 +1094,7 @@ /* GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN14_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN14_WAKEUP_ENABLE_S 10 @@ -1101,7 +1105,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN14_INT_TYPE 0x00000007 +#define GPIO_PIN14_INT_TYPE 0x00000007 #define GPIO_PIN14_INT_TYPE_M ((GPIO_PIN14_INT_TYPE_V)<<(GPIO_PIN14_INT_TYPE_S)) #define GPIO_PIN14_INT_TYPE_V 0x7 #define GPIO_PIN14_INT_TYPE_S 7 @@ -1109,7 +1113,7 @@ /* GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER (BIT(2)) #define GPIO_PIN14_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN14_PAD_DRIVER_V 0x1 #define GPIO_PIN14_PAD_DRIVER_S 2 @@ -1122,7 +1126,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN15_INT_ENA 0x0000001F +#define GPIO_PIN15_INT_ENA 0x0000001F #define GPIO_PIN15_INT_ENA_M ((GPIO_PIN15_INT_ENA_V)<<(GPIO_PIN15_INT_ENA_S)) #define GPIO_PIN15_INT_ENA_V 0x1F #define GPIO_PIN15_INT_ENA_S 13 @@ -1130,7 +1134,7 @@ /* GPIO_PIN15_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN15_CONFIG 0x00000003 +#define GPIO_PIN15_CONFIG 0x00000003 #define GPIO_PIN15_CONFIG_M ((GPIO_PIN15_CONFIG_V)<<(GPIO_PIN15_CONFIG_S)) #define GPIO_PIN15_CONFIG_V 0x3 #define GPIO_PIN15_CONFIG_S 11 @@ -1138,7 +1142,7 @@ /* GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN15_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN15_WAKEUP_ENABLE_S 10 @@ -1149,7 +1153,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN15_INT_TYPE 0x00000007 +#define GPIO_PIN15_INT_TYPE 0x00000007 #define GPIO_PIN15_INT_TYPE_M ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S)) #define GPIO_PIN15_INT_TYPE_V 0x7 #define GPIO_PIN15_INT_TYPE_S 7 @@ -1157,7 +1161,7 @@ /* GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER (BIT(2)) #define GPIO_PIN15_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN15_PAD_DRIVER_V 0x1 #define GPIO_PIN15_PAD_DRIVER_S 2 @@ -1170,7 +1174,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN16_INT_ENA 0x0000001F +#define GPIO_PIN16_INT_ENA 0x0000001F #define GPIO_PIN16_INT_ENA_M ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S)) #define GPIO_PIN16_INT_ENA_V 0x1F #define GPIO_PIN16_INT_ENA_S 13 @@ -1178,7 +1182,7 @@ /* GPIO_PIN16_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN16_CONFIG 0x00000003 +#define GPIO_PIN16_CONFIG 0x00000003 #define GPIO_PIN16_CONFIG_M ((GPIO_PIN16_CONFIG_V)<<(GPIO_PIN16_CONFIG_S)) #define GPIO_PIN16_CONFIG_V 0x3 #define GPIO_PIN16_CONFIG_S 11 @@ -1186,7 +1190,7 @@ /* GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN16_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN16_WAKEUP_ENABLE_S 10 @@ -1197,7 +1201,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN16_INT_TYPE 0x00000007 +#define GPIO_PIN16_INT_TYPE 0x00000007 #define GPIO_PIN16_INT_TYPE_M ((GPIO_PIN16_INT_TYPE_V)<<(GPIO_PIN16_INT_TYPE_S)) #define GPIO_PIN16_INT_TYPE_V 0x7 #define GPIO_PIN16_INT_TYPE_S 7 @@ -1205,7 +1209,7 @@ /* GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER (BIT(2)) #define GPIO_PIN16_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN16_PAD_DRIVER_V 0x1 #define GPIO_PIN16_PAD_DRIVER_S 2 @@ -1218,7 +1222,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN17_INT_ENA 0x0000001F +#define GPIO_PIN17_INT_ENA 0x0000001F #define GPIO_PIN17_INT_ENA_M ((GPIO_PIN17_INT_ENA_V)<<(GPIO_PIN17_INT_ENA_S)) #define GPIO_PIN17_INT_ENA_V 0x1F #define GPIO_PIN17_INT_ENA_S 13 @@ -1226,7 +1230,7 @@ /* GPIO_PIN17_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN17_CONFIG 0x00000003 +#define GPIO_PIN17_CONFIG 0x00000003 #define GPIO_PIN17_CONFIG_M ((GPIO_PIN17_CONFIG_V)<<(GPIO_PIN17_CONFIG_S)) #define GPIO_PIN17_CONFIG_V 0x3 #define GPIO_PIN17_CONFIG_S 11 @@ -1234,7 +1238,7 @@ /* GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN17_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN17_WAKEUP_ENABLE_S 10 @@ -1245,7 +1249,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN17_INT_TYPE 0x00000007 +#define GPIO_PIN17_INT_TYPE 0x00000007 #define GPIO_PIN17_INT_TYPE_M ((GPIO_PIN17_INT_TYPE_V)<<(GPIO_PIN17_INT_TYPE_S)) #define GPIO_PIN17_INT_TYPE_V 0x7 #define GPIO_PIN17_INT_TYPE_S 7 @@ -1253,7 +1257,7 @@ /* GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER (BIT(2)) #define GPIO_PIN17_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN17_PAD_DRIVER_V 0x1 #define GPIO_PIN17_PAD_DRIVER_S 2 @@ -1266,7 +1270,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN18_INT_ENA 0x0000001F +#define GPIO_PIN18_INT_ENA 0x0000001F #define GPIO_PIN18_INT_ENA_M ((GPIO_PIN18_INT_ENA_V)<<(GPIO_PIN18_INT_ENA_S)) #define GPIO_PIN18_INT_ENA_V 0x1F #define GPIO_PIN18_INT_ENA_S 13 @@ -1274,7 +1278,7 @@ /* GPIO_PIN18_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN18_CONFIG 0x00000003 +#define GPIO_PIN18_CONFIG 0x00000003 #define GPIO_PIN18_CONFIG_M ((GPIO_PIN18_CONFIG_V)<<(GPIO_PIN18_CONFIG_S)) #define GPIO_PIN18_CONFIG_V 0x3 #define GPIO_PIN18_CONFIG_S 11 @@ -1282,7 +1286,7 @@ /* GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN18_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN18_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN18_WAKEUP_ENABLE_S 10 @@ -1293,7 +1297,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN18_INT_TYPE 0x00000007 +#define GPIO_PIN18_INT_TYPE 0x00000007 #define GPIO_PIN18_INT_TYPE_M ((GPIO_PIN18_INT_TYPE_V)<<(GPIO_PIN18_INT_TYPE_S)) #define GPIO_PIN18_INT_TYPE_V 0x7 #define GPIO_PIN18_INT_TYPE_S 7 @@ -1301,7 +1305,7 @@ /* GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN18_PAD_DRIVER (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER (BIT(2)) #define GPIO_PIN18_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN18_PAD_DRIVER_V 0x1 #define GPIO_PIN18_PAD_DRIVER_S 2 @@ -1314,7 +1318,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN19_INT_ENA 0x0000001F +#define GPIO_PIN19_INT_ENA 0x0000001F #define GPIO_PIN19_INT_ENA_M ((GPIO_PIN19_INT_ENA_V)<<(GPIO_PIN19_INT_ENA_S)) #define GPIO_PIN19_INT_ENA_V 0x1F #define GPIO_PIN19_INT_ENA_S 13 @@ -1322,7 +1326,7 @@ /* GPIO_PIN19_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN19_CONFIG 0x00000003 +#define GPIO_PIN19_CONFIG 0x00000003 #define GPIO_PIN19_CONFIG_M ((GPIO_PIN19_CONFIG_V)<<(GPIO_PIN19_CONFIG_S)) #define GPIO_PIN19_CONFIG_V 0x3 #define GPIO_PIN19_CONFIG_S 11 @@ -1330,7 +1334,7 @@ /* GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN19_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN19_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN19_WAKEUP_ENABLE_S 10 @@ -1341,7 +1345,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN19_INT_TYPE 0x00000007 +#define GPIO_PIN19_INT_TYPE 0x00000007 #define GPIO_PIN19_INT_TYPE_M ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S)) #define GPIO_PIN19_INT_TYPE_V 0x7 #define GPIO_PIN19_INT_TYPE_S 7 @@ -1349,7 +1353,7 @@ /* GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN19_PAD_DRIVER (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER (BIT(2)) #define GPIO_PIN19_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN19_PAD_DRIVER_V 0x1 #define GPIO_PIN19_PAD_DRIVER_S 2 @@ -1362,7 +1366,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN20_INT_ENA 0x0000001F +#define GPIO_PIN20_INT_ENA 0x0000001F #define GPIO_PIN20_INT_ENA_M ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S)) #define GPIO_PIN20_INT_ENA_V 0x1F #define GPIO_PIN20_INT_ENA_S 13 @@ -1370,7 +1374,7 @@ /* GPIO_PIN20_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN20_CONFIG 0x00000003 +#define GPIO_PIN20_CONFIG 0x00000003 #define GPIO_PIN20_CONFIG_M ((GPIO_PIN20_CONFIG_V)<<(GPIO_PIN20_CONFIG_S)) #define GPIO_PIN20_CONFIG_V 0x3 #define GPIO_PIN20_CONFIG_S 11 @@ -1378,7 +1382,7 @@ /* GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN20_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN20_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN20_WAKEUP_ENABLE_S 10 @@ -1389,7 +1393,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN20_INT_TYPE 0x00000007 +#define GPIO_PIN20_INT_TYPE 0x00000007 #define GPIO_PIN20_INT_TYPE_M ((GPIO_PIN20_INT_TYPE_V)<<(GPIO_PIN20_INT_TYPE_S)) #define GPIO_PIN20_INT_TYPE_V 0x7 #define GPIO_PIN20_INT_TYPE_S 7 @@ -1397,7 +1401,7 @@ /* GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN20_PAD_DRIVER (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER (BIT(2)) #define GPIO_PIN20_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN20_PAD_DRIVER_V 0x1 #define GPIO_PIN20_PAD_DRIVER_S 2 @@ -1410,7 +1414,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN21_INT_ENA 0x0000001F +#define GPIO_PIN21_INT_ENA 0x0000001F #define GPIO_PIN21_INT_ENA_M ((GPIO_PIN21_INT_ENA_V)<<(GPIO_PIN21_INT_ENA_S)) #define GPIO_PIN21_INT_ENA_V 0x1F #define GPIO_PIN21_INT_ENA_S 13 @@ -1418,7 +1422,7 @@ /* GPIO_PIN21_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN21_CONFIG 0x00000003 +#define GPIO_PIN21_CONFIG 0x00000003 #define GPIO_PIN21_CONFIG_M ((GPIO_PIN21_CONFIG_V)<<(GPIO_PIN21_CONFIG_S)) #define GPIO_PIN21_CONFIG_V 0x3 #define GPIO_PIN21_CONFIG_S 11 @@ -1426,7 +1430,7 @@ /* GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN21_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN21_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN21_WAKEUP_ENABLE_S 10 @@ -1437,7 +1441,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN21_INT_TYPE 0x00000007 +#define GPIO_PIN21_INT_TYPE 0x00000007 #define GPIO_PIN21_INT_TYPE_M ((GPIO_PIN21_INT_TYPE_V)<<(GPIO_PIN21_INT_TYPE_S)) #define GPIO_PIN21_INT_TYPE_V 0x7 #define GPIO_PIN21_INT_TYPE_S 7 @@ -1445,7 +1449,7 @@ /* GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN21_PAD_DRIVER (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER (BIT(2)) #define GPIO_PIN21_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN21_PAD_DRIVER_V 0x1 #define GPIO_PIN21_PAD_DRIVER_S 2 @@ -1455,7 +1459,7 @@ /* GPIO_PIN22_INT_ENA : R/W ;bitpos:[17:13] ;default: x ; */ /* Description: */ -#define GPIO_PIN22_INT_ENA 0x0000001F +#define GPIO_PIN22_INT_ENA 0x0000001F #define GPIO_PIN22_INT_ENA_M ((GPIO_PIN22_INT_ENA_V)<<(GPIO_PIN22_INT_ENA_S)) #define GPIO_PIN22_INT_ENA_V 0x1F #define GPIO_PIN22_INT_ENA_S 13 @@ -1466,7 +1470,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN22_CONFIG 0x00000003 +#define GPIO_PIN22_CONFIG 0x00000003 #define GPIO_PIN22_CONFIG_M ((GPIO_PIN22_CONFIG_V)<<(GPIO_PIN22_CONFIG_S)) #define GPIO_PIN22_CONFIG_V 0x3 #define GPIO_PIN22_CONFIG_S 11 @@ -1474,7 +1478,7 @@ /* GPIO_PIN22_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN22_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN22_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN22_WAKEUP_ENABLE_S 10 @@ -1482,7 +1486,7 @@ /* GPIO_PIN22_INT_TYPE : R/W ;bitpos:[9:7] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN22_INT_TYPE 0x00000007 +#define GPIO_PIN22_INT_TYPE 0x00000007 #define GPIO_PIN22_INT_TYPE_M ((GPIO_PIN22_INT_TYPE_V)<<(GPIO_PIN22_INT_TYPE_S)) #define GPIO_PIN22_INT_TYPE_V 0x7 #define GPIO_PIN22_INT_TYPE_S 7 @@ -1490,7 +1494,7 @@ /* GPIO_PIN22_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: */ -#define GPIO_PIN22_PAD_DRIVER (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER (BIT(2)) #define GPIO_PIN22_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN22_PAD_DRIVER_V 0x1 #define GPIO_PIN22_PAD_DRIVER_S 2 @@ -1503,7 +1507,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN23_INT_ENA 0x0000001F +#define GPIO_PIN23_INT_ENA 0x0000001F #define GPIO_PIN23_INT_ENA_M ((GPIO_PIN23_INT_ENA_V)<<(GPIO_PIN23_INT_ENA_S)) #define GPIO_PIN23_INT_ENA_V 0x1F #define GPIO_PIN23_INT_ENA_S 13 @@ -1511,7 +1515,7 @@ /* GPIO_PIN23_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN23_CONFIG 0x00000003 +#define GPIO_PIN23_CONFIG 0x00000003 #define GPIO_PIN23_CONFIG_M ((GPIO_PIN23_CONFIG_V)<<(GPIO_PIN23_CONFIG_S)) #define GPIO_PIN23_CONFIG_V 0x3 #define GPIO_PIN23_CONFIG_S 11 @@ -1519,7 +1523,7 @@ /* GPIO_PIN23_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN23_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN23_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN23_WAKEUP_ENABLE_S 10 @@ -1530,7 +1534,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN23_INT_TYPE 0x00000007 +#define GPIO_PIN23_INT_TYPE 0x00000007 #define GPIO_PIN23_INT_TYPE_M ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S)) #define GPIO_PIN23_INT_TYPE_V 0x7 #define GPIO_PIN23_INT_TYPE_S 7 @@ -1538,7 +1542,7 @@ /* GPIO_PIN23_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN23_PAD_DRIVER (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER (BIT(2)) #define GPIO_PIN23_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN23_PAD_DRIVER_V 0x1 #define GPIO_PIN23_PAD_DRIVER_S 2 @@ -1551,7 +1555,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN24_INT_ENA 0x0000001F +#define GPIO_PIN24_INT_ENA 0x0000001F #define GPIO_PIN24_INT_ENA_M ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S)) #define GPIO_PIN24_INT_ENA_V 0x1F #define GPIO_PIN24_INT_ENA_S 13 @@ -1559,7 +1563,7 @@ /* GPIO_PIN24_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN24_CONFIG 0x00000003 +#define GPIO_PIN24_CONFIG 0x00000003 #define GPIO_PIN24_CONFIG_M ((GPIO_PIN24_CONFIG_V)<<(GPIO_PIN24_CONFIG_S)) #define GPIO_PIN24_CONFIG_V 0x3 #define GPIO_PIN24_CONFIG_S 11 @@ -1567,7 +1571,7 @@ /* GPIO_PIN24_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN24_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN24_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN24_WAKEUP_ENABLE_S 10 @@ -1578,7 +1582,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN24_INT_TYPE 0x00000007 +#define GPIO_PIN24_INT_TYPE 0x00000007 #define GPIO_PIN24_INT_TYPE_M ((GPIO_PIN24_INT_TYPE_V)<<(GPIO_PIN24_INT_TYPE_S)) #define GPIO_PIN24_INT_TYPE_V 0x7 #define GPIO_PIN24_INT_TYPE_S 7 @@ -1586,7 +1590,7 @@ /* GPIO_PIN24_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN24_PAD_DRIVER (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER (BIT(2)) #define GPIO_PIN24_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN24_PAD_DRIVER_V 0x1 #define GPIO_PIN24_PAD_DRIVER_S 2 @@ -1599,7 +1603,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN25_INT_ENA 0x0000001F +#define GPIO_PIN25_INT_ENA 0x0000001F #define GPIO_PIN25_INT_ENA_M ((GPIO_PIN25_INT_ENA_V)<<(GPIO_PIN25_INT_ENA_S)) #define GPIO_PIN25_INT_ENA_V 0x1F #define GPIO_PIN25_INT_ENA_S 13 @@ -1607,7 +1611,7 @@ /* GPIO_PIN25_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN25_CONFIG 0x00000003 +#define GPIO_PIN25_CONFIG 0x00000003 #define GPIO_PIN25_CONFIG_M ((GPIO_PIN25_CONFIG_V)<<(GPIO_PIN25_CONFIG_S)) #define GPIO_PIN25_CONFIG_V 0x3 #define GPIO_PIN25_CONFIG_S 11 @@ -1615,7 +1619,7 @@ /* GPIO_PIN25_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN25_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN25_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN25_WAKEUP_ENABLE_S 10 @@ -1626,7 +1630,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN25_INT_TYPE 0x00000007 +#define GPIO_PIN25_INT_TYPE 0x00000007 #define GPIO_PIN25_INT_TYPE_M ((GPIO_PIN25_INT_TYPE_V)<<(GPIO_PIN25_INT_TYPE_S)) #define GPIO_PIN25_INT_TYPE_V 0x7 #define GPIO_PIN25_INT_TYPE_S 7 @@ -1634,7 +1638,7 @@ /* GPIO_PIN25_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN25_PAD_DRIVER (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER (BIT(2)) #define GPIO_PIN25_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN25_PAD_DRIVER_V 0x1 #define GPIO_PIN25_PAD_DRIVER_S 2 @@ -1647,7 +1651,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN26_INT_ENA 0x0000001F +#define GPIO_PIN26_INT_ENA 0x0000001F #define GPIO_PIN26_INT_ENA_M ((GPIO_PIN26_INT_ENA_V)<<(GPIO_PIN26_INT_ENA_S)) #define GPIO_PIN26_INT_ENA_V 0x1F #define GPIO_PIN26_INT_ENA_S 13 @@ -1655,7 +1659,7 @@ /* GPIO_PIN26_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN26_CONFIG 0x00000003 +#define GPIO_PIN26_CONFIG 0x00000003 #define GPIO_PIN26_CONFIG_M ((GPIO_PIN26_CONFIG_V)<<(GPIO_PIN26_CONFIG_S)) #define GPIO_PIN26_CONFIG_V 0x3 #define GPIO_PIN26_CONFIG_S 11 @@ -1663,7 +1667,7 @@ /* GPIO_PIN26_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN26_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN26_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN26_WAKEUP_ENABLE_S 10 @@ -1674,7 +1678,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN26_INT_TYPE 0x00000007 +#define GPIO_PIN26_INT_TYPE 0x00000007 #define GPIO_PIN26_INT_TYPE_M ((GPIO_PIN26_INT_TYPE_V)<<(GPIO_PIN26_INT_TYPE_S)) #define GPIO_PIN26_INT_TYPE_V 0x7 #define GPIO_PIN26_INT_TYPE_S 7 @@ -1682,7 +1686,7 @@ /* GPIO_PIN26_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN26_PAD_DRIVER (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER (BIT(2)) #define GPIO_PIN26_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN26_PAD_DRIVER_V 0x1 #define GPIO_PIN26_PAD_DRIVER_S 2 @@ -1695,7 +1699,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN27_INT_ENA 0x0000001F +#define GPIO_PIN27_INT_ENA 0x0000001F #define GPIO_PIN27_INT_ENA_M ((GPIO_PIN27_INT_ENA_V)<<(GPIO_PIN27_INT_ENA_S)) #define GPIO_PIN27_INT_ENA_V 0x1F #define GPIO_PIN27_INT_ENA_S 13 @@ -1703,7 +1707,7 @@ /* GPIO_PIN27_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN27_CONFIG 0x00000003 +#define GPIO_PIN27_CONFIG 0x00000003 #define GPIO_PIN27_CONFIG_M ((GPIO_PIN27_CONFIG_V)<<(GPIO_PIN27_CONFIG_S)) #define GPIO_PIN27_CONFIG_V 0x3 #define GPIO_PIN27_CONFIG_S 11 @@ -1711,7 +1715,7 @@ /* GPIO_PIN27_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN27_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN27_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN27_WAKEUP_ENABLE_S 10 @@ -1722,7 +1726,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN27_INT_TYPE 0x00000007 +#define GPIO_PIN27_INT_TYPE 0x00000007 #define GPIO_PIN27_INT_TYPE_M ((GPIO_PIN27_INT_TYPE_V)<<(GPIO_PIN27_INT_TYPE_S)) #define GPIO_PIN27_INT_TYPE_V 0x7 #define GPIO_PIN27_INT_TYPE_S 7 @@ -1730,7 +1734,7 @@ /* GPIO_PIN27_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN27_PAD_DRIVER (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER (BIT(2)) #define GPIO_PIN27_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN27_PAD_DRIVER_V 0x1 #define GPIO_PIN27_PAD_DRIVER_S 2 @@ -1743,7 +1747,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN28_INT_ENA 0x0000001F +#define GPIO_PIN28_INT_ENA 0x0000001F #define GPIO_PIN28_INT_ENA_M ((GPIO_PIN28_INT_ENA_V)<<(GPIO_PIN28_INT_ENA_S)) #define GPIO_PIN28_INT_ENA_V 0x1F #define GPIO_PIN28_INT_ENA_S 13 @@ -1751,7 +1755,7 @@ /* GPIO_PIN28_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN28_CONFIG 0x00000003 +#define GPIO_PIN28_CONFIG 0x00000003 #define GPIO_PIN28_CONFIG_M ((GPIO_PIN28_CONFIG_V)<<(GPIO_PIN28_CONFIG_S)) #define GPIO_PIN28_CONFIG_V 0x3 #define GPIO_PIN28_CONFIG_S 11 @@ -1759,7 +1763,7 @@ /* GPIO_PIN28_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN28_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN28_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN28_WAKEUP_ENABLE_S 10 @@ -1770,7 +1774,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN28_INT_TYPE 0x00000007 +#define GPIO_PIN28_INT_TYPE 0x00000007 #define GPIO_PIN28_INT_TYPE_M ((GPIO_PIN28_INT_TYPE_V)<<(GPIO_PIN28_INT_TYPE_S)) #define GPIO_PIN28_INT_TYPE_V 0x7 #define GPIO_PIN28_INT_TYPE_S 7 @@ -1778,7 +1782,7 @@ /* GPIO_PIN28_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN28_PAD_DRIVER (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER (BIT(2)) #define GPIO_PIN28_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN28_PAD_DRIVER_V 0x1 #define GPIO_PIN28_PAD_DRIVER_S 2 @@ -1791,7 +1795,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN29_INT_ENA 0x0000001F +#define GPIO_PIN29_INT_ENA 0x0000001F #define GPIO_PIN29_INT_ENA_M ((GPIO_PIN29_INT_ENA_V)<<(GPIO_PIN29_INT_ENA_S)) #define GPIO_PIN29_INT_ENA_V 0x1F #define GPIO_PIN29_INT_ENA_S 13 @@ -1799,7 +1803,7 @@ /* GPIO_PIN29_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN29_CONFIG 0x00000003 +#define GPIO_PIN29_CONFIG 0x00000003 #define GPIO_PIN29_CONFIG_M ((GPIO_PIN29_CONFIG_V)<<(GPIO_PIN29_CONFIG_S)) #define GPIO_PIN29_CONFIG_V 0x3 #define GPIO_PIN29_CONFIG_S 11 @@ -1807,7 +1811,7 @@ /* GPIO_PIN29_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN29_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN29_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN29_WAKEUP_ENABLE_S 10 @@ -1818,7 +1822,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN29_INT_TYPE 0x00000007 +#define GPIO_PIN29_INT_TYPE 0x00000007 #define GPIO_PIN29_INT_TYPE_M ((GPIO_PIN29_INT_TYPE_V)<<(GPIO_PIN29_INT_TYPE_S)) #define GPIO_PIN29_INT_TYPE_V 0x7 #define GPIO_PIN29_INT_TYPE_S 7 @@ -1826,7 +1830,7 @@ /* GPIO_PIN29_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN29_PAD_DRIVER (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER (BIT(2)) #define GPIO_PIN29_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN29_PAD_DRIVER_V 0x1 #define GPIO_PIN29_PAD_DRIVER_S 2 @@ -1839,7 +1843,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN30_INT_ENA 0x0000001F +#define GPIO_PIN30_INT_ENA 0x0000001F #define GPIO_PIN30_INT_ENA_M ((GPIO_PIN30_INT_ENA_V)<<(GPIO_PIN30_INT_ENA_S)) #define GPIO_PIN30_INT_ENA_V 0x1F #define GPIO_PIN30_INT_ENA_S 13 @@ -1847,7 +1851,7 @@ /* GPIO_PIN30_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN30_CONFIG 0x00000003 +#define GPIO_PIN30_CONFIG 0x00000003 #define GPIO_PIN30_CONFIG_M ((GPIO_PIN30_CONFIG_V)<<(GPIO_PIN30_CONFIG_S)) #define GPIO_PIN30_CONFIG_V 0x3 #define GPIO_PIN30_CONFIG_S 11 @@ -1855,7 +1859,7 @@ /* GPIO_PIN30_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN30_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN30_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN30_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN30_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN30_WAKEUP_ENABLE_S 10 @@ -1866,7 +1870,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN30_INT_TYPE 0x00000007 +#define GPIO_PIN30_INT_TYPE 0x00000007 #define GPIO_PIN30_INT_TYPE_M ((GPIO_PIN30_INT_TYPE_V)<<(GPIO_PIN30_INT_TYPE_S)) #define GPIO_PIN30_INT_TYPE_V 0x7 #define GPIO_PIN30_INT_TYPE_S 7 @@ -1874,7 +1878,7 @@ /* GPIO_PIN30_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN30_PAD_DRIVER (BIT(2)) +#define GPIO_PIN30_PAD_DRIVER (BIT(2)) #define GPIO_PIN30_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN30_PAD_DRIVER_V 0x1 #define GPIO_PIN30_PAD_DRIVER_S 2 @@ -1887,7 +1891,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN31_INT_ENA 0x0000001F +#define GPIO_PIN31_INT_ENA 0x0000001F #define GPIO_PIN31_INT_ENA_M ((GPIO_PIN31_INT_ENA_V)<<(GPIO_PIN31_INT_ENA_S)) #define GPIO_PIN31_INT_ENA_V 0x1F #define GPIO_PIN31_INT_ENA_S 13 @@ -1895,7 +1899,7 @@ /* GPIO_PIN31_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN31_CONFIG 0x00000003 +#define GPIO_PIN31_CONFIG 0x00000003 #define GPIO_PIN31_CONFIG_M ((GPIO_PIN31_CONFIG_V)<<(GPIO_PIN31_CONFIG_S)) #define GPIO_PIN31_CONFIG_V 0x3 #define GPIO_PIN31_CONFIG_S 11 @@ -1903,7 +1907,7 @@ /* GPIO_PIN31_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN31_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN31_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN31_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN31_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN31_WAKEUP_ENABLE_S 10 @@ -1914,7 +1918,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN31_INT_TYPE 0x00000007 +#define GPIO_PIN31_INT_TYPE 0x00000007 #define GPIO_PIN31_INT_TYPE_M ((GPIO_PIN31_INT_TYPE_V)<<(GPIO_PIN31_INT_TYPE_S)) #define GPIO_PIN31_INT_TYPE_V 0x7 #define GPIO_PIN31_INT_TYPE_S 7 @@ -1922,7 +1926,7 @@ /* GPIO_PIN31_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN31_PAD_DRIVER (BIT(2)) +#define GPIO_PIN31_PAD_DRIVER (BIT(2)) #define GPIO_PIN31_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN31_PAD_DRIVER_V 0x1 #define GPIO_PIN31_PAD_DRIVER_S 2 @@ -1935,7 +1939,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN32_INT_ENA 0x0000001F +#define GPIO_PIN32_INT_ENA 0x0000001F #define GPIO_PIN32_INT_ENA_M ((GPIO_PIN32_INT_ENA_V)<<(GPIO_PIN32_INT_ENA_S)) #define GPIO_PIN32_INT_ENA_V 0x1F #define GPIO_PIN32_INT_ENA_S 13 @@ -1943,7 +1947,7 @@ /* GPIO_PIN32_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN32_CONFIG 0x00000003 +#define GPIO_PIN32_CONFIG 0x00000003 #define GPIO_PIN32_CONFIG_M ((GPIO_PIN32_CONFIG_V)<<(GPIO_PIN32_CONFIG_S)) #define GPIO_PIN32_CONFIG_V 0x3 #define GPIO_PIN32_CONFIG_S 11 @@ -1951,7 +1955,7 @@ /* GPIO_PIN32_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN32_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN32_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN32_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN32_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN32_WAKEUP_ENABLE_S 10 @@ -1962,7 +1966,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN32_INT_TYPE 0x00000007 +#define GPIO_PIN32_INT_TYPE 0x00000007 #define GPIO_PIN32_INT_TYPE_M ((GPIO_PIN32_INT_TYPE_V)<<(GPIO_PIN32_INT_TYPE_S)) #define GPIO_PIN32_INT_TYPE_V 0x7 #define GPIO_PIN32_INT_TYPE_S 7 @@ -1970,7 +1974,7 @@ /* GPIO_PIN32_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN32_PAD_DRIVER (BIT(2)) +#define GPIO_PIN32_PAD_DRIVER (BIT(2)) #define GPIO_PIN32_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN32_PAD_DRIVER_V 0x1 #define GPIO_PIN32_PAD_DRIVER_S 2 @@ -1983,7 +1987,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN33_INT_ENA 0x0000001F +#define GPIO_PIN33_INT_ENA 0x0000001F #define GPIO_PIN33_INT_ENA_M ((GPIO_PIN33_INT_ENA_V)<<(GPIO_PIN33_INT_ENA_S)) #define GPIO_PIN33_INT_ENA_V 0x1F #define GPIO_PIN33_INT_ENA_S 13 @@ -1991,7 +1995,7 @@ /* GPIO_PIN33_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN33_CONFIG 0x00000003 +#define GPIO_PIN33_CONFIG 0x00000003 #define GPIO_PIN33_CONFIG_M ((GPIO_PIN33_CONFIG_V)<<(GPIO_PIN33_CONFIG_S)) #define GPIO_PIN33_CONFIG_V 0x3 #define GPIO_PIN33_CONFIG_S 11 @@ -1999,7 +2003,7 @@ /* GPIO_PIN33_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN33_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN33_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN33_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN33_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN33_WAKEUP_ENABLE_S 10 @@ -2010,7 +2014,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN33_INT_TYPE 0x00000007 +#define GPIO_PIN33_INT_TYPE 0x00000007 #define GPIO_PIN33_INT_TYPE_M ((GPIO_PIN33_INT_TYPE_V)<<(GPIO_PIN33_INT_TYPE_S)) #define GPIO_PIN33_INT_TYPE_V 0x7 #define GPIO_PIN33_INT_TYPE_S 7 @@ -2018,7 +2022,7 @@ /* GPIO_PIN33_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN33_PAD_DRIVER (BIT(2)) +#define GPIO_PIN33_PAD_DRIVER (BIT(2)) #define GPIO_PIN33_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN33_PAD_DRIVER_V 0x1 #define GPIO_PIN33_PAD_DRIVER_S 2 @@ -2031,7 +2035,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN34_INT_ENA 0x0000001F +#define GPIO_PIN34_INT_ENA 0x0000001F #define GPIO_PIN34_INT_ENA_M ((GPIO_PIN34_INT_ENA_V)<<(GPIO_PIN34_INT_ENA_S)) #define GPIO_PIN34_INT_ENA_V 0x1F #define GPIO_PIN34_INT_ENA_S 13 @@ -2039,7 +2043,7 @@ /* GPIO_PIN34_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN34_CONFIG 0x00000003 +#define GPIO_PIN34_CONFIG 0x00000003 #define GPIO_PIN34_CONFIG_M ((GPIO_PIN34_CONFIG_V)<<(GPIO_PIN34_CONFIG_S)) #define GPIO_PIN34_CONFIG_V 0x3 #define GPIO_PIN34_CONFIG_S 11 @@ -2047,7 +2051,7 @@ /* GPIO_PIN34_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN34_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN34_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN34_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN34_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN34_WAKEUP_ENABLE_S 10 @@ -2058,7 +2062,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN34_INT_TYPE 0x00000007 +#define GPIO_PIN34_INT_TYPE 0x00000007 #define GPIO_PIN34_INT_TYPE_M ((GPIO_PIN34_INT_TYPE_V)<<(GPIO_PIN34_INT_TYPE_S)) #define GPIO_PIN34_INT_TYPE_V 0x7 #define GPIO_PIN34_INT_TYPE_S 7 @@ -2066,7 +2070,7 @@ /* GPIO_PIN34_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN34_PAD_DRIVER (BIT(2)) +#define GPIO_PIN34_PAD_DRIVER (BIT(2)) #define GPIO_PIN34_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN34_PAD_DRIVER_V 0x1 #define GPIO_PIN34_PAD_DRIVER_S 2 @@ -2079,7 +2083,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN35_INT_ENA 0x0000001F +#define GPIO_PIN35_INT_ENA 0x0000001F #define GPIO_PIN35_INT_ENA_M ((GPIO_PIN35_INT_ENA_V)<<(GPIO_PIN35_INT_ENA_S)) #define GPIO_PIN35_INT_ENA_V 0x1F #define GPIO_PIN35_INT_ENA_S 13 @@ -2087,7 +2091,7 @@ /* GPIO_PIN35_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN35_CONFIG 0x00000003 +#define GPIO_PIN35_CONFIG 0x00000003 #define GPIO_PIN35_CONFIG_M ((GPIO_PIN35_CONFIG_V)<<(GPIO_PIN35_CONFIG_S)) #define GPIO_PIN35_CONFIG_V 0x3 #define GPIO_PIN35_CONFIG_S 11 @@ -2095,7 +2099,7 @@ /* GPIO_PIN35_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN35_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN35_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN35_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN35_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN35_WAKEUP_ENABLE_S 10 @@ -2106,7 +2110,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN35_INT_TYPE 0x00000007 +#define GPIO_PIN35_INT_TYPE 0x00000007 #define GPIO_PIN35_INT_TYPE_M ((GPIO_PIN35_INT_TYPE_V)<<(GPIO_PIN35_INT_TYPE_S)) #define GPIO_PIN35_INT_TYPE_V 0x7 #define GPIO_PIN35_INT_TYPE_S 7 @@ -2114,7 +2118,7 @@ /* GPIO_PIN35_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN35_PAD_DRIVER (BIT(2)) +#define GPIO_PIN35_PAD_DRIVER (BIT(2)) #define GPIO_PIN35_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN35_PAD_DRIVER_V 0x1 #define GPIO_PIN35_PAD_DRIVER_S 2 @@ -2127,7 +2131,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN36_INT_ENA 0x0000001F +#define GPIO_PIN36_INT_ENA 0x0000001F #define GPIO_PIN36_INT_ENA_M ((GPIO_PIN36_INT_ENA_V)<<(GPIO_PIN36_INT_ENA_S)) #define GPIO_PIN36_INT_ENA_V 0x1F #define GPIO_PIN36_INT_ENA_S 13 @@ -2135,7 +2139,7 @@ /* GPIO_PIN36_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN36_CONFIG 0x00000003 +#define GPIO_PIN36_CONFIG 0x00000003 #define GPIO_PIN36_CONFIG_M ((GPIO_PIN36_CONFIG_V)<<(GPIO_PIN36_CONFIG_S)) #define GPIO_PIN36_CONFIG_V 0x3 #define GPIO_PIN36_CONFIG_S 11 @@ -2143,7 +2147,7 @@ /* GPIO_PIN36_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN36_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN36_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN36_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN36_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN36_WAKEUP_ENABLE_S 10 @@ -2154,7 +2158,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN36_INT_TYPE 0x00000007 +#define GPIO_PIN36_INT_TYPE 0x00000007 #define GPIO_PIN36_INT_TYPE_M ((GPIO_PIN36_INT_TYPE_V)<<(GPIO_PIN36_INT_TYPE_S)) #define GPIO_PIN36_INT_TYPE_V 0x7 #define GPIO_PIN36_INT_TYPE_S 7 @@ -2162,7 +2166,7 @@ /* GPIO_PIN36_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN36_PAD_DRIVER (BIT(2)) +#define GPIO_PIN36_PAD_DRIVER (BIT(2)) #define GPIO_PIN36_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN36_PAD_DRIVER_V 0x1 #define GPIO_PIN36_PAD_DRIVER_S 2 @@ -2175,7 +2179,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN37_INT_ENA 0x0000001F +#define GPIO_PIN37_INT_ENA 0x0000001F #define GPIO_PIN37_INT_ENA_M ((GPIO_PIN37_INT_ENA_V)<<(GPIO_PIN37_INT_ENA_S)) #define GPIO_PIN37_INT_ENA_V 0x1F #define GPIO_PIN37_INT_ENA_S 13 @@ -2183,7 +2187,7 @@ /* GPIO_PIN37_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN37_CONFIG 0x00000003 +#define GPIO_PIN37_CONFIG 0x00000003 #define GPIO_PIN37_CONFIG_M ((GPIO_PIN37_CONFIG_V)<<(GPIO_PIN37_CONFIG_S)) #define GPIO_PIN37_CONFIG_V 0x3 #define GPIO_PIN37_CONFIG_S 11 @@ -2191,7 +2195,7 @@ /* GPIO_PIN37_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN37_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN37_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN37_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN37_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN37_WAKEUP_ENABLE_S 10 @@ -2202,7 +2206,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN37_INT_TYPE 0x00000007 +#define GPIO_PIN37_INT_TYPE 0x00000007 #define GPIO_PIN37_INT_TYPE_M ((GPIO_PIN37_INT_TYPE_V)<<(GPIO_PIN37_INT_TYPE_S)) #define GPIO_PIN37_INT_TYPE_V 0x7 #define GPIO_PIN37_INT_TYPE_S 7 @@ -2210,7 +2214,7 @@ /* GPIO_PIN37_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN37_PAD_DRIVER (BIT(2)) +#define GPIO_PIN37_PAD_DRIVER (BIT(2)) #define GPIO_PIN37_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN37_PAD_DRIVER_V 0x1 #define GPIO_PIN37_PAD_DRIVER_S 2 @@ -2223,7 +2227,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN38_INT_ENA 0x0000001F +#define GPIO_PIN38_INT_ENA 0x0000001F #define GPIO_PIN38_INT_ENA_M ((GPIO_PIN38_INT_ENA_V)<<(GPIO_PIN38_INT_ENA_S)) #define GPIO_PIN38_INT_ENA_V 0x1F #define GPIO_PIN38_INT_ENA_S 13 @@ -2231,7 +2235,7 @@ /* GPIO_PIN38_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN38_CONFIG 0x00000003 +#define GPIO_PIN38_CONFIG 0x00000003 #define GPIO_PIN38_CONFIG_M ((GPIO_PIN38_CONFIG_V)<<(GPIO_PIN38_CONFIG_S)) #define GPIO_PIN38_CONFIG_V 0x3 #define GPIO_PIN38_CONFIG_S 11 @@ -2239,7 +2243,7 @@ /* GPIO_PIN38_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN38_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN38_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN38_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN38_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN38_WAKEUP_ENABLE_S 10 @@ -2250,7 +2254,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN38_INT_TYPE 0x00000007 +#define GPIO_PIN38_INT_TYPE 0x00000007 #define GPIO_PIN38_INT_TYPE_M ((GPIO_PIN38_INT_TYPE_V)<<(GPIO_PIN38_INT_TYPE_S)) #define GPIO_PIN38_INT_TYPE_V 0x7 #define GPIO_PIN38_INT_TYPE_S 7 @@ -2258,7 +2262,7 @@ /* GPIO_PIN38_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN38_PAD_DRIVER (BIT(2)) +#define GPIO_PIN38_PAD_DRIVER (BIT(2)) #define GPIO_PIN38_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN38_PAD_DRIVER_V 0x1 #define GPIO_PIN38_PAD_DRIVER_S 2 @@ -2271,7 +2275,7 @@ * non-maskable interrupt enable bit5: SDIO's extent interrupt enable. */ -#define GPIO_PIN39_INT_ENA 0x0000001F +#define GPIO_PIN39_INT_ENA 0x0000001F #define GPIO_PIN39_INT_ENA_M ((GPIO_PIN39_INT_ENA_V)<<(GPIO_PIN39_INT_ENA_S)) #define GPIO_PIN39_INT_ENA_V 0x1F #define GPIO_PIN39_INT_ENA_S 13 @@ -2279,7 +2283,7 @@ /* GPIO_PIN39_CONFIG : R/W ;bitpos:[12:11] ;default: x ; */ /* Description: NA */ -#define GPIO_PIN39_CONFIG 0x00000003 +#define GPIO_PIN39_CONFIG 0x00000003 #define GPIO_PIN39_CONFIG_M ((GPIO_PIN39_CONFIG_V)<<(GPIO_PIN39_CONFIG_S)) #define GPIO_PIN39_CONFIG_V 0x3 #define GPIO_PIN39_CONFIG_S 11 @@ -2287,7 +2291,7 @@ /* GPIO_PIN39_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: x ; */ /* Description: GPIO wake up enable only available in light sleep */ -#define GPIO_PIN39_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN39_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN39_WAKEUP_ENABLE_M (BIT(10)) #define GPIO_PIN39_WAKEUP_ENABLE_V 0x1 #define GPIO_PIN39_WAKEUP_ENABLE_S 10 @@ -2298,7 +2302,7 @@ * trigger if set to 4: low level trigger if set to 5: high level trigger. */ -#define GPIO_PIN39_INT_TYPE 0x00000007 +#define GPIO_PIN39_INT_TYPE 0x00000007 #define GPIO_PIN39_INT_TYPE_M ((GPIO_PIN39_INT_TYPE_V)<<(GPIO_PIN39_INT_TYPE_S)) #define GPIO_PIN39_INT_TYPE_V 0x7 #define GPIO_PIN39_INT_TYPE_S 7 @@ -2306,7 +2310,7 @@ /* GPIO_PIN39_PAD_DRIVER : R/W ;bitpos:[2] ;default: x ; */ /* Description: if set to 0: normal output if set to 1: open drain */ -#define GPIO_PIN39_PAD_DRIVER (BIT(2)) +#define GPIO_PIN39_PAD_DRIVER (BIT(2)) #define GPIO_PIN39_PAD_DRIVER_M (BIT(2)) #define GPIO_PIN39_PAD_DRIVER_V 0x1 #define GPIO_PIN39_PAD_DRIVER_S 2 diff --git a/arch/xtensa/src/esp32/chip/esp32_iomux.h b/arch/xtensa/src/esp32/chip/esp32_iomux.h new file mode 100644 index 0000000000..f424fae1e2 --- /dev/null +++ b/arch/xtensa/src/esp32/chip/esp32_iomux.h @@ -0,0 +1,288 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_gpio.c + * + * Developed for NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derivies from sample code provided by Expressif Systems: + * + * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_MUX_H +#define __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_MUX_H 1 + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "chip/esp32_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SLP_OE (BIT(0)) +#define SLP_SEL (BIT(1)) +#define SLP_PD (BIT(2)) +#define SLP_PU (BIT(3)) +#define SLP_IE (BIT(4)) +#define SLP_DRV 0x3 +#define SLP_DRV_S 5 +#define FUN_PD (BIT(7)) +#define FUN_PU (BIT(8)) +#define FUN_IE (BIT(9)) +#define FUN_DRV 0x3 +#define FUN_DRV_S 10 +#define MCU_SEL 0x7 +#define MCU_SEL_S 12 + +#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); +#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) +#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) +#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) + +#define PIN_FUNC_GPIO 2 + +#define PIN_CTRL (DR_REG_IO_MUX_BASE +0x00) +#define CLK_OUT3 0xf +#define CLK_OUT3_S 8 +#define CLK_OUT2 0xf +#define CLK_OUT2_S 4 +#define CLK_OUT1 0xf +#define CLK_OUT1_S 0 + +#define PERIPHS_IO_MUX_GPIO0_U (DR_REG_IO_MUX_BASE +0x44) +#define FUNC_GPIO0_EMAC_TX_CLK 5 +#define FUNC_GPIO0_GPIO0 2 +#define FUNC_GPIO0_CLK_OUT1 1 +#define FUNC_GPIO0_GPIO0_0 0 + +#define PERIPHS_IO_MUX_U0TXD_U (DR_REG_IO_MUX_BASE +0x88) +#define FUNC_U0TXD_EMAC_RXD2 3 +#define FUNC_U0TXD_GPIO1 2 +#define FUNC_U0TXD_CLK_OUT3 1 +#define FUNC_U0TXD_U0TXD 0 + +#define PERIPHS_IO_MUX_GPIO2_U (DR_REG_IO_MUX_BASE +0x40) +#define FUNC_GPIO2_SD_DATA0 4 +#define FUNC_GPIO2_HS2_DATA0 3 +#define FUNC_GPIO2_GPIO2 2 +#define FUNC_GPIO2_HSPIWP 1 +#define FUNC_GPIO2_GPIO2_0 0 + +#define PERIPHS_IO_MUX_U0RXD_U (DR_REG_IO_MUX_BASE +0x84) +#define FUNC_U0RXD_GPIO3 2 +#define FUNC_U0RXD_CLK_OUT2 1 +#define FUNC_U0RXD_U0RXD 0 + +#define PERIPHS_IO_MUX_GPIO4_U (DR_REG_IO_MUX_BASE +0x48) +#define FUNC_GPIO4_EMAC_TX_ER 5 +#define FUNC_GPIO4_SD_DATA1 4 +#define FUNC_GPIO4_HS2_DATA1 3 +#define FUNC_GPIO4_GPIO4 2 +#define FUNC_GPIO4_HSPIHD 1 +#define FUNC_GPIO4_GPIO4_0 0 + +#define PERIPHS_IO_MUX_GPIO5_U (DR_REG_IO_MUX_BASE +0x6c) +#define FUNC_GPIO5_EMAC_RX_CLK 5 +#define FUNC_GPIO5_HS1_DATA6 3 +#define FUNC_GPIO5_GPIO5 2 +#define FUNC_GPIO5_VSPICS0 1 +#define FUNC_GPIO5_GPIO5_0 0 + +#define PERIPHS_IO_MUX_SD_CLK_U (DR_REG_IO_MUX_BASE +0x60) +#define FUNC_SD_CLK_U1CTS 4 +#define FUNC_SD_CLK_HS1_CLK 3 +#define FUNC_SD_CLK_GPIO6 2 +#define FUNC_SD_CLK_SPICLK 1 +#define FUNC_SD_CLK_SD_CLK 0 + +#define PERIPHS_IO_MUX_SD_DATA0_U (DR_REG_IO_MUX_BASE +0x64) +#define FUNC_SD_DATA0_U2RTS 4 +#define FUNC_SD_DATA0_HS1_DATA0 3 +#define FUNC_SD_DATA0_GPIO7 2 +#define FUNC_SD_DATA0_SPIQ 1 +#define FUNC_SD_DATA0_SD_DATA0 0 + +#define PERIPHS_IO_MUX_SD_DATA1_U (DR_REG_IO_MUX_BASE +0x68) +#define FUNC_SD_DATA1_U2CTS 4 +#define FUNC_SD_DATA1_HS1_DATA1 3 +#define FUNC_SD_DATA1_GPIO8 2 +#define FUNC_SD_DATA1_SPID 1 +#define FUNC_SD_DATA1_SD_DATA1 0 + +#define PERIPHS_IO_MUX_SD_DATA2_U (DR_REG_IO_MUX_BASE +0x54) +#define FUNC_SD_DATA2_U1RXD 4 +#define FUNC_SD_DATA2_HS1_DATA2 3 +#define FUNC_SD_DATA2_GPIO9 2 +#define FUNC_SD_DATA2_SPIHD 1 +#define FUNC_SD_DATA2_SD_DATA2 0 + +#define PERIPHS_IO_MUX_SD_DATA3_U (DR_REG_IO_MUX_BASE +0x58) +#define FUNC_SD_DATA3_U1TXD 4 +#define FUNC_SD_DATA3_HS1_DATA3 3 +#define FUNC_SD_DATA3_GPIO10 2 +#define FUNC_SD_DATA3_SPIWP 1 +#define FUNC_SD_DATA3_SD_DATA3 0 + +#define PERIPHS_IO_MUX_SD_CMD_U (DR_REG_IO_MUX_BASE +0x5c) +#define FUNC_SD_CMD_U1RTS 4 +#define FUNC_SD_CMD_HS1_CMD 3 +#define FUNC_SD_CMD_GPIO11 2 +#define FUNC_SD_CMD_SPICS0 1 +#define FUNC_SD_CMD_SD_CMD 0 + +#define PERIPHS_IO_MUX_MTDI_U (DR_REG_IO_MUX_BASE +0x34) +#define FUNC_MTDI_EMAC_TXD3 5 +#define FUNC_MTDI_SD_DATA2 4 +#define FUNC_MTDI_HS2_DATA2 3 +#define FUNC_MTDI_GPIO12 2 +#define FUNC_MTDI_HSPIQ 1 +#define FUNC_MTDI_MTDI 0 + +#define PERIPHS_IO_MUX_MTCK_U (DR_REG_IO_MUX_BASE +0x38) +#define FUNC_MTCK_EMAC_RX_ER 5 +#define FUNC_MTCK_SD_DATA3 4 +#define FUNC_MTCK_HS2_DATA3 3 +#define FUNC_MTCK_GPIO13 2 +#define FUNC_MTCK_HSPID 1 +#define FUNC_MTCK_MTCK 0 + +#define PERIPHS_IO_MUX_MTMS_U (DR_REG_IO_MUX_BASE +0x30) +#define FUNC_MTMS_EMAC_TXD2 5 +#define FUNC_MTMS_SD_CLK 4 +#define FUNC_MTMS_HS2_CLk 3 +#define FUNC_MTMS_GPIO14 2 +#define FUNC_MTMS_HSPICLK 1 +#define FUNC_MTMS_MTMS 0 + +#define PERIPHS_IO_MUX_MTDO_U (DR_REG_IO_MUX_BASE +0x3c) +#define FUNC_MTDO_EMAC_RXD3 5 +#define FUNC_MTDO_SD_CMD 4 +#define FUNC_MTDO_HS2_CMD 3 +#define FUNC_MTDO_GPIO15 2 +#define FUNC_MTDO_HSPICS0 1 +#define FUNC_MTDO_MTDO 0 + +#define PERIPHS_IO_MUX_GPIO16_U (DR_REG_IO_MUX_BASE +0x4c) +#define FUNC_GPIO16_EMAC_CLK_OUT 5 +#define FUNC_GPIO16_U2RXD 4 +#define FUNC_GPIO16_HS1_DATA4 3 +#define FUNC_GPIO16_GPIO16 2 +#define FUNC_GPIO16_GPIO16_0 0 + +#define PERIPHS_IO_MUX_GPIO17_U (DR_REG_IO_MUX_BASE +0x50) +#define FUNC_GPIO17_EMAC_CLK_OUT_180 5 +#define FUNC_GPIO17_U2TXD 4 +#define FUNC_GPIO17_HS1_DATA5 3 +#define FUNC_GPIO17_GPIO17 2 +#define FUNC_GPIO17_GPIO17_0 0 + +#define PERIPHS_IO_MUX_GPIO18_U (DR_REG_IO_MUX_BASE +0x70) +#define FUNC_GPIO18_HS1_DATA7 3 +#define FUNC_GPIO18_GPIO18 2 +#define FUNC_GPIO18_VSPICLK 1 +#define FUNC_GPIO18_GPIO18_0 0 + +#define PERIPHS_IO_MUX_GPIO19_U (DR_REG_IO_MUX_BASE +0x74) +#define FUNC_GPIO19_EMAC_TXD0 5 +#define FUNC_GPIO19_U0CTS 3 +#define FUNC_GPIO19_GPIO19 2 +#define FUNC_GPIO19_VSPIQ 1 +#define FUNC_GPIO19_GPIO19_0 0 + +#define PERIPHS_IO_MUX_GPIO20_U (DR_REG_IO_MUX_BASE +0x78) +#define FUNC_GPIO20_GPIO20 2 +#define FUNC_GPIO20_GPIO20_0 0 + +#define PERIPHS_IO_MUX_GPIO21_U (DR_REG_IO_MUX_BASE +0x7c) +#define FUNC_GPIO21_EMAC_TX_EN 5 +#define FUNC_GPIO21_GPIO21 2 +#define FUNC_GPIO21_VSPIHD 1 +#define FUNC_GPIO21_GPIO21_0 0 + +#define PERIPHS_IO_MUX_GPIO22_U (DR_REG_IO_MUX_BASE +0x80) +#define FUNC_GPIO22_EMAC_TXD1 5 +#define FUNC_GPIO22_U0RTS 3 +#define FUNC_GPIO22_GPIO22 2 +#define FUNC_GPIO22_VSPIWP 1 +#define FUNC_GPIO22_GPIO22_0 0 + +#define PERIPHS_IO_MUX_GPIO23_U (DR_REG_IO_MUX_BASE +0x8c) +#define FUNC_GPIO23_HS1_STROBE 3 +#define FUNC_GPIO23_GPIO23 2 +#define FUNC_GPIO23_VSPID 1 +#define FUNC_GPIO23_GPIO23_0 0 + +#define PERIPHS_IO_MUX_GPIO24_U (DR_REG_IO_MUX_BASE +0x90) +#define FUNC_GPIO24_GPIO24 2 +#define FUNC_GPIO24_GPIO24_0 0 + +#define PERIPHS_IO_MUX_GPIO25_U (DR_REG_IO_MUX_BASE +0x24) +#define FUNC_GPIO25_EMAC_RXD0 5 +#define FUNC_GPIO25_GPIO25 2 +#define FUNC_GPIO25_GPIO25_0 0 + +#define PERIPHS_IO_MUX_GPIO26_U (DR_REG_IO_MUX_BASE +0x28) +#define FUNC_GPIO26_EMAC_RXD1 5 +#define FUNC_GPIO26_GPIO26 2 +#define FUNC_GPIO26_GPIO26_0 0 + +#define PERIPHS_IO_MUX_GPIO27_U (DR_REG_IO_MUX_BASE +0x2c) +#define FUNC_GPIO27_EMAC_RX_DV 5 +#define FUNC_GPIO27_GPIO27 2 +#define FUNC_GPIO27_GPIO27_0 0 + +#define PERIPHS_IO_MUX_GPIO32_U (DR_REG_IO_MUX_BASE +0x1c) +#define FUNC_GPIO32_GPIO32 2 +#define FUNC_GPIO32_GPIO32_0 0 + +#define PERIPHS_IO_MUX_GPIO33_U (DR_REG_IO_MUX_BASE +0x20) +#define FUNC_GPIO33_GPIO33 2 +#define FUNC_GPIO33_GPIO33_0 0 + +#define PERIPHS_IO_MUX_GPIO34_U (DR_REG_IO_MUX_BASE +0x14) +#define FUNC_GPIO34_GPIO34 2 +#define FUNC_GPIO34_GPIO34_0 0 + +#define PERIPHS_IO_MUX_GPIO35_U (DR_REG_IO_MUX_BASE +0x18) +#define FUNC_GPIO35_GPIO35 2 +#define FUNC_GPIO35_GPIO35_0 0 + +#define PERIPHS_IO_MUX_GPIO36_U (DR_REG_IO_MUX_BASE +0x04) +#define FUNC_GPIO36_GPIO36 2 +#define FUNC_GPIO36_GPIO36_0 0 + +#define PERIPHS_IO_MUX_GPIO37_U (DR_REG_IO_MUX_BASE +0x08) +#define FUNC_GPIO37_GPIO37 2 +#define FUNC_GPIO37_GPIO37_0 0 + +#define PERIPHS_IO_MUX_GPIO38_U (DR_REG_IO_MUX_BASE +0x0c) +#define FUNC_GPIO38_GPIO38 2 +#define FUNC_GPIO38_GPIO38_0 0 + +#define PERIPHS_IO_MUX_GPIO39_U (DR_REG_IO_MUX_BASE +0x10) +#define FUNC_GPIO39_GPIO39 2 +#define FUNC_GPIO39_GPIO39_0 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_MUX_H */ diff --git a/arch/xtensa/src/esp32/esp32_cpuint.c b/arch/xtensa/src/esp32/esp32_cpuint.c index 6a6aec7fe5..c02c9483d8 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.c +++ b/arch/xtensa/src/esp32/esp32_cpuint.c @@ -54,10 +54,6 @@ * Pre-processor Definitions ****************************************************************************/ -#define ESP32_INTSET(n) ((1 << (n)) - 1) -#define ESP32_LEVEL_SET ESP32_INTSET(ESP32_CPUINT_NLEVELPERIPHS) -#define ESP32_EDGE_SET ESP32_INTSET(ESP32_CPUINT_NEDGEPERIPHS) - /* Mapping Peripheral IDs to map register addresses * * PERIPHERAL ID DPORT REGISTER OFFSET @@ -169,12 +165,11 @@ static uint32_t g_intenable[1]; /* Bitsets for free, unallocated CPU interrupts */ -static uint32_t g_level_ints = ESP32_LEVEL_SET; -static uint32_t g_edge_ints = ESP32_EDGE_SET; +static uint32_t g_free_cpuints = 0xffffffff; /* Bitsets for each interrupt priority 1-5 */ -static uint32_t g_priority[5] = +static const uint32_t g_priority[5] = { ESP32_INTPRI1_MASK, ESP32_INTPRI2_MASK, @@ -187,6 +182,75 @@ static uint32_t g_priority[5] = * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: esp32_alloc_cpuint + * + * Description: + * Allocate a CPU interrupt + * + * Input Parameters: + * mask - mask of candidate CPU interrupts. The CPU interrupt will be + * be allocated from free interrupts within this set + * + * Returned Value: + * On success, the allocated level-sensitive, CPU interrupt numbr is + * returned. A negated errno is returned on failure. The only possible + * failure is that all level-sensitive CPU interrupts have already been + * allocated. + * + ****************************************************************************/ + +int esp32_alloc_levelint(uint32_t mask) +{ + irqstate_t flags; + uint32_t mask; + uint32_t intset; + int cpuint; + int ret = -ENOMEM; + + /* Check if there are is CPU interrupts with the requrested properties + * available. + */ + + flags = enter_critical_section(); + + intset = g_free_cpuints & mask; + if (intset != 0) + { + /* Skip over initial unavailable CPU interrupts quickly in groups + * of 8 interrupt. + */ + + for (cpuint = 0, mask = 0xff; + cpuint <= ESP32_CPUINT_MAX; + cpuint += 8, mask <<= 8); + + /* Search for an unallocated CPU interrupt number in the remaining + * intset. + */ + + for (; cpuint <= ESP32_CPUINT_MAX; cpuint++) + { + /* If the bit corresponding to the CPU interrupt is '1', then + * that CPU interrupt is available. + */ + + mask = (1ul << cpuint); + if ((intset & mask) != 0) + { + /* Got it! */ + + g_free_cpuints &= ~mask; + ret = cpuint; + break; + } + } + } + + leave_critical_section(flags); + return ret; +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -258,83 +322,17 @@ void up_enable_irq(int cpuint) int esp32_alloc_levelint(int priority) { - irqstate_t flags; - uint32_t mask; - uint32_t intset; - int cpuint; - int ret = -ENOMEM; - - DEBUGASSERT(priority >= ESP32_MIN_PRIORITY && priority <= ESP32_MAX_PRIORITY) - - /* Check if there are any level CPU interrupts available */ - - flags = enter_critical_section(); - - intset = g_level_ints & g_priority[ESP32_PRIO_INDEX(priority)] & ESP32_LEVEL_SET; - if (intset != 0) - { - /* Skip over initial zeroes as quickly in groups of 8 bits. */ - - for (cpuint = 0, mask = 0xff; - cpuint <= ESP32_CPUINT_MAX && (intset & mask) == 0; - cpuint += 8, mask <<= 8); - - /* Search for an unallocated CPU interrupt number in the remaining intset. */ - - for (; cpuint <= ESP32_CPUINT_MAX && intset != 0; cpuint++) - { - /* If the bit corresponding to the CPU interrupt is '1', then - * that CPU interrupt is available. - */ - - mask = (1ul << cpuint); - if ((intset & mask) != 0) - { - /* Got it! */ - - g_level_ints &= ~mask; - ret = cpuint; - break; - } - - /* Clear the bit in intset so that we may exit the loop sooner */ - - intset &= ~mask; - } - } - - leave_critical_section(flags); - return ret; -} - -/**************************************************************************** - * Name: esp32_free_levelint - * - * Description: - * Free a previoulsy allocated level CPU interrupt - * - * Input Parameters: - * The CPU interrupt number to be freed - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_free_levelint(int cpuint) -{ - irqstate_t flags; uint32_t mask; - DEBUGASSERT(cpuint >= 0 && cpuint < ESP32_CPUINT_NLEVELPERIPHS); + DEBUGASSERT(priority >= ESP32_MIN_PRIORITY && + priority <= ESP32_MAX_PRIORITY) - /* Mark the CPU interrupt as available */ + /* Check if there are any level CPU interrupts available at the requested + * interrupt priority. + */ - mask = (1ul << cpuint); - flags = enter_critical_section(); - DEBUGASSERT((g_level_ints & mask) == 0); - g_level_ints |= mask; - leave_critical_section(flags); + mask = g_priority[ESP32_PRIO_INDEX(priority)] & EPS32_CPUINT_LEVELSET; + return esp_alloc_cpuint(mask); } /**************************************************************************** @@ -356,60 +354,24 @@ void esp32_free_levelint(int cpuint) int esp32_alloc_edgeint(int priority) { - irqstate_t flags; uint32_t mask; - uint32_t intset; - int cpuint; - int ret = -ENOMEM; - - DEBUGASSERT(priority >= ESP32_MIN_PRIORITY && priority <= ESP32_MAX_PRIORITY) - - /* Check if there are any level CPU interrupts available */ - - flags = enter_critical_section(); - intset = g_edge_ints & g_priority[ESP32_PRIO_INDEX(priority)] & ESP32_EDGE_SET; - if (intset != 0) - { - /* Skip over initial zeroes as quickly in groups of 8 bits. */ + DEBUGASSERT(priority >= ESP32_MIN_PRIORITY && + priority <= ESP32_MAX_PRIORITY) - for (cpuint = 0, mask = 0xff; - cpuint <= ESP32_CPUINT_MAX && (intset & mask) == 0; - cpuint += 8, mask <<= 8); + /* Check if there are any edge CPU interrupts available at the requested + * interrupt priority. + */ - /* Search for an unallocated CPU interrupt number in the remaining intset. */ - - for (; cpuint <= ESP32_CPUINT_MAX && intset != 0; cpuint++) - { - /* If the bit corresponding to the CPU interrupt is '1', then - * that CPU interrupt is available. - */ - - mask = (1ul << cpuint); - if ((intset & mask) != 0) - { - /* Got it! */ - - g_edge_ints &= ~mask; - ret = cpuint; - break; - } - - /* Clear the bit in intset so that we may exit the loop sooner */ - - intset &= ~mask; - } - } - - leave_critical_section(flags); - return ret; + mask = g_priority[ESP32_PRIO_INDEX(priority)] & EPS32_CPUINT_EDGESET; + return esp_alloc_cpuint(mask); } /**************************************************************************** - * Name: esp32_free_edgeint + * Name: esp32_free_cpuint * * Description: - * Free a previoulsy allocated edge CPU interrupt + * Free a previoulsy allocated CPU interrupt * * Input Parameters: * The CPU interrupt number to be freed @@ -419,7 +381,7 @@ int esp32_alloc_edgeint(int priority) * ****************************************************************************/ -void esp32_free_edgeint(int cpuint) +void esp32_free_cpuint(int cpuint) { irqstate_t flags; uint32_t mask; @@ -430,8 +392,8 @@ void esp32_free_edgeint(int cpuint) mask = (1ul << cpuint); flags = enter_critical_section(); - DEBUGASSERT((g_edge_ints & mask) == 0); - g_edge_ints |= mask; + DEBUGASSERT((g_free_cpuints & mask) == 0); + g_free_cpuints |= mask; leave_critical_section(flags); } @@ -455,7 +417,7 @@ void esp32_attach_peripheral(int cpu, int periphid, int cpuint) { uintptr_t regaddr; - DEBUGASSERT(periphid >= 0 && periphid < NR_PERIPHERALS); + DEBUGASSERT(periphid >= 0 && periphid < ESP32_NPERIPHERALS); DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32_CPUINT_MAX); #ifdef CONFIG_SMP DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); @@ -492,7 +454,7 @@ void esp32_detach_peripheral(int cpu, int periphid) { uintptr_t regaddr; - DEBUGASSERT(periphid >= 0 && periphid < NR_PERIPHERALS); + DEBUGASSERT(periphid >= 0 && periphid < ESP32_NPERIPHERALS); #ifdef CONFIG_SMP DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); diff --git a/arch/xtensa/src/esp32/esp32_cpuint.h b/arch/xtensa/src/esp32/esp32_cpuint.h index 746248456d..f67354db44 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.h +++ b/arch/xtensa/src/esp32/esp32_cpuint.h @@ -65,22 +65,6 @@ int esp32_alloc_levelint(int priority); -/**************************************************************************** - * Name: esp32_free_levelint - * - * Description: - * Free a previoulsy allocated level CPU interrupt - * - * Input Parameters: - * cpuint - The CPU interrupt number to be freed - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_free_levelint(int cpuint); - /**************************************************************************** * Name: esp32_alloc_edgeint * @@ -101,10 +85,10 @@ void esp32_free_levelint(int cpuint); int esp32_alloc_edgeint(int priority); /**************************************************************************** - * Name: esp32_free_edgeint + * Name: esp32_free_cpuint * * Description: - * Free a previoulsy allocated edge CPU interrupt + * Free a previoulsy allocated CPU interrupt * * Input Parameters: * cpuint - The CPU interrupt number to be freed @@ -114,7 +98,7 @@ int esp32_alloc_edgeint(int priority); * ****************************************************************************/ -void esp32_free_edgeint(int cpuint, int priority); +void esp32_free_cpuint(int cpuint, int priority); /**************************************************************************** * Name: esp32_attach_peripheral diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c index ec5d0c7d06..5bf82dfd42 100644 --- a/arch/xtensa/src/esp32/esp32_cpustart.c +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -148,7 +148,7 @@ int xtensa_start_handler(int irq, FAR void *context) /* Detach all peripheral sources APP CPU interrupts */ - for (i = 0; i < NR_PERIPHERALS) + for (i = 0; i < ESP32_NPERIPHERALS; i++) { esp32_detach_peripheral(1, i);; } diff --git a/arch/xtensa/src/esp32/esp32_gpio.c b/arch/xtensa/src/esp32/esp32_gpio.c new file mode 100644 index 0000000000..831fd4542a --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_gpio.c @@ -0,0 +1,423 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_gpio.c + * + * Developed for NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derivies from sample code provided by Expressif Systems: + * + * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip/esp32_iomux.h" +#include "chip/esp32_gpio.h" +#include "esp32_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NGPIO_HPINS (ESP32_NIRQ_GPIO - 32) +#define NGPIO_HMASK ((1ul << NGPIO_HPINS) - 1) +#define _NA_ 0xff + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint8_t g_gpio_cpuint; + +static const uint8_t g_pin2func[40] = +{ + 0x44, 0x88, 0x40, 0x84, 0x48, 0x6c, 0x60, 0x64, /* 0-7 */ + 0x68, 0x54, 0x58, 0x5c, 0x34, 0x38, 0x30, 0x3c, /* 8-15 */ + 0x4c, 0x50, 0x70, 0x74, 0x78, 0x7c, 0x80, 0x8c, /* 16-23 */ + _NA_, 0x24, 0x28, 0x2c, _NA_, _NA_, _NA_, _NA_, /* N/A, 25-27, N/A, N/A, N/A, N/A */ + 0x1c, 0x20, 0x14, 0x18, 0x04, 0x08, 0x0c, 0x10 /* 32-39 */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gpio_dispatch + * + * Description: + * Second level dispatch for GPIO interrupt handling. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32_GPIO_IRQ +static void gpio_dispatch(int irq, uint32_t status, uint32_t *regs) +{ + uint32_t mask; + int i; + + /* Check each bit in the status register */ + + for (i = 0; i < 32 && status != 0; i++) + { + /* Check if there is an interrupt pending for this pin */ + + mask = (1ul << i); + if ((status & mask) != 0) + { + /* Yes... perform the second level dispatch */ + + irq_dispatch(irq + i, regs); + + /* Clear the bit in the status so that we might execute this loop + * sooner. + */ + + status &= ~mask; + } + } +} +#endif + +/**************************************************************************** + * Name: gpio_interrupt + * + * Description: + * GPIO interrupt handler. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32_GPIO_IRQ +static int gpio_interrupt(int irq, FAR void *context) +{ + uint32_t status; + uint32_t gpio_intr_status_h = 0; + + /* Read and clear the lower GPIO interrupt status */ + + status = getreg32(GPIO_STATUS_REG); + putreg32(status, GPIO_STATUS_W1TC_REG); + + /* Dispatch pending interrupts in the lower GPIO status register */ + + gpio_dispatch(ESP32_FIRST_GPIOIRQ, status, (uint32_t *)context); + + /* Read and clear the upper GPIO interrupt status */ + + status = getreg32(GPIO_STATUS1_REG) & NGPIO_HMASK; + putreg32(status, GPIO_STATUS1_W1TC_REG); + + /* Dispatch pending interrupts in the lower GPIO status register */ + + gpio_dispatch(ESP32_FIRST_GPIOIRQ + 32, status, (uint32_t *)context); + reutnr OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_configgpio + * + * Description: + * Configure a GPIO pin based on encoded pin attributes. + * + ****************************************************************************/ + +int esp32_configgpio(int pin, gpio_pinattr_t attr) +{ + uintptr_t regaddr; + uint32_t func; + uint32_t cntl; + + DEBUGASSERT(pin >=0 && pin <= ESP32_NIRQ_GPIO); + DEBUGASSERT(pin >=0 && pin <= ESP32_NIRQ_GPIO); + + /* Handle input pins */ + + func = 0; + cntrl = 0; + + if ((attr & INPUT) != 0) + { + if (pin < 32) + { + putreg32((1ul << pin), GPIO_ENABLE_W1TC_REG); + } + else + { + putreg32((1ul << (pin - 32), GPIO_ENABLE1_DATA_W1TC); + } + + if ((attr & PULLUP) != 0) + { + func |= FUN_PU; + } + else if (attr & PULLDOWN) + { + func |= FUN_PD; + } + } + + /* Handle output pins */ + + else if ((attr & OUTPUT) != 0) + { + if (pin < 32) + { + putreg32((1ul << pin), GPIO_ENABLE_DATA_W1TS); + } + else + { + putreg32((1ul << (pin - 32), GPIO_ENABLE1_DATA_W1TS); + } + } + + /* Add drivers */ + + func |= ((uint32_t)(2ul << FUN_DRV_S); + + /* Input enable... Required for output as well? */ + + func |= FUN_IE; + + + if ((attr & (INPUT | OUTPUT)) != 0) + { + func |= ((uint32_t)(2 << MCU_SEL_S); + } + else if (attr == SPECIAL) + { + func |= ((uint32_t)(((pin) == 1 || (pin) == 3) ? 0 : 1) << MCU_SEL_S); + } + else + { + func |= ((uint32_t)(attr >> 5) << MCU_SEL_S); + } + + if ((attr & OPEN_DRAIN) != 0) + { + cntl = (1 << GPIO_PIN_PAD_DRIVER_S); + } + + regaddr = DR_REG_IO_MUX_BASE + g_pin2func[pin]; + putreg32(func, regaddr); + + regaddr = GPIO_REG(pin); + putreg32(cntl, regaddr); +} + +/**************************************************************************** + * Name: esp32_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void esp32_gpiowrite(int pin, bool value) +{ + if (pin > 39) + { + return; + } + if (value) + { + if (pin < 32) + { + GPIO.out_w1ts = ((uint32_t) 1 << pin); + } + else + { + GPIO.out1_w1ts.val = ((uint32_t) 1 << (pin - 32)); + } + } + else + { + if (pin < 32) + { + GPIO.out_w1tc = ((uint32_t) 1 << pin); + } + else + { + GPIO.out1_w1tc.val = ((uint32_t) 1 << (pin - 32)); + } + } +} + +/**************************************************************************** + * Name: esp32_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool esp32_gpioread(int pin) +{ + if (pin > 39) + { + return false; + } + if (pin < 32) + { + return ((GPIO.in >> pin) & 1) != 0; + } + else + { + return ((GPIO.in1.val >> (pin - 32)) & 1) != 0; + } +} + +/**************************************************************************** + * Name: esp32_gpioirqinitialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32_GPIO_IRQ +void esp32_gpioirqinitialize(void) +{ + int cpu; + + /* Allocate a level-sensitive, priority 1 CPU interrupt */ + + g_gpio_cpuint = esp32_alloc_levelint(1); + DEBUGASSERT(g_gpio_cpuint >= 0); + + /* Attach the GPIO peripheral to the allocated CPU interrupt */ + + up_disable_irq(g_gpio_cpuint); + cpu = up_cpu_index(); + esp32_attach_peripheral(cpu, ESP32_PERIPH_CPU_GPIO, g_gpio_cpuint); + + /* Attach and enable the interrupt handler */ + + DEBUGVERIFY(irq_attach(ESP32_IRQ_CPU_GPIO, gpio_interrupt)); + up_enable_irq(g_gpio_cpuint); +} +#endif + +/**************************************************************************** + * Name: esp32_gpioirqenable + * + * Description: + * Enable the COPY interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32_GPIO_IRQ +void esp32_gpioirqenable(int irq, gpio_intrtype_t intrtype) +{ + uintptr_t regaddr; + uint32_t regval; + int cpu; + int pin; + + DEBUGASSERT(irq <= ESP32_FIRST_GPIOIRQ && irq <= ESP32_LAST_GPIOIRQ); + + /* Convert the IRQ number to a pin number */ + + pin = ESP32_IRQ2PIN(irq); + + /* Get the address of the GPIO PIN register for this pin */ + + up_disable_irq(g_gpio_cpuint); + + regaddr = GPIO_REG(pin); + regval = getreg32(regaddr); + regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M); + + /* Set the pin ENA field: + * + * Bit 0: APP CPU interrupt enable + * Bit 1: APP CPU non-maskable interrupt enable + * Bit 3: PRO CPU interrupt enable + * Bit 4: PRO CPU non-maskable interrupt enable + * Bit 5: SDIO's extent interrupt enable. + */ + + cpu = up_cpu_index(); + if (cpu == 0) + { + /* PRO_CPU */ + + regval |= ((1 << 2) << GPIO_PIN_INT_ENA_S); + } + else + { + /* APP_CPU */ + + regval |= ((1 << 0) << GPIO_PIN_INT_ENA_S); + } + + regval |= (intrtype << GPIO_PIN_INT_TYPE_S); + puttreg32(regval, regaddr); + + up_enable_irq(g_gpio_cpuint); +} +#endif + +/**************************************************************************** + * Name: esp32_gpioirqdisable + * + * Description: + * Disable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32_GPIO_IRQ +void esp32_gpioirqdisable(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + int pin; + + DEBUGASSERT(irq <= ESP32_FIRST_GPIOIRQ && irq <= ESP32_LAST_GPIOIRQ); + + /* Convert the IRQ number to a pin number */ + + pin = ESP32_IRQ2PIN(irq); + + /* Get the address of the GPIO PIN register for this pin */ + + up_disable_irq(g_gpio_cpuint); + + regaddr = GPIO_REG(pin); + regval = getreg32(regaddr); + regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M); + puttreg32(regval, regaddr); + + up_enable_irq(g_gpio_cpuint); +} +#endif diff --git a/arch/xtensa/src/esp32/esp32_gpio.h b/arch/xtensa/src/esp32/esp32_gpio.h new file mode 100644 index 0000000000..59f6380cbc --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_gpio.h @@ -0,0 +1,185 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_gpio.h + * + * Developed for NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derivies in part from sample code provided by Expressif Systems: + * + * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_GPIO_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Bit-encoded input to esp32_configgpio() **********************************/ + +/* Encoded pin attributes used with esp32_configgpio() */ + +#define INPUT 0x01 +#define OUTPUT 0x02 +#define PULLUP 0x04 +#define INPUT_PULLUP 0x05 +#define PULLDOWN 0x08 +#define INPUT_PULLDOWN 0x09 +#define OPEN_DRAIN 0x10 +#define OUTPUT_OPEN_DRAIN 0x12 +#define SPECIAL 0xf0 +#define FUNCTION_0 0x00 +#define FUNCTION_1 0x20 +#define FUNCTION_2 0x40 +#define FUNCTION_3 0x70 +#define FUNCTION_4 0x80 + +/* Interrupt type used with esp32_gpioirqenable() */ + +#define DISABLED 0x00 +#define RISING 0x01 +#define FALLING 0x02 +#define CHANGE 0x03 +#define ONLOW 0x04 +#define ONHIGH 0x05 +#define ONLOW_WE 0x0c +#define ONHIGH_WE 0x0d + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* Must be big enough to hold the the above encodings */ + +typedef uint8_t gpio_pinattr_t; +typedef uint8_t gpio_intrtype_t; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_gpioirqinitialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32_GPIO_IRQ +void esp32_gpioirqinitialize(void); +#else +# define esp32_gpioirqinitialize() +#endif + +/**************************************************************************** + * Name: esp32_configgpio + * + * Description: + * Configure a GPIO pin based on encoded pin attributes. + * + ****************************************************************************/ + +int esp32_configgpio(int pin, gpio_pinattr_t attr); + +/**************************************************************************** + * Name: esp32_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void esp32_gpiowrite(int pin, bool value); + +/**************************************************************************** + * Name: esp32_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool esp32_gpioread(int pin); + +/**************************************************************************** + * Name: esp32_gpioirqenable + * + * Description: + * Enable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32_GPIO_IRQ +void esp32_gpioirqenable(int irq, gpio_intrtype_t intrtype); +#else +# define esp32_gpioirqenable(irq,intrtype) +#endif + +/**************************************************************************** + * Name: esp32_gpioirqdisable + * + * Description: + * Disable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32_GPIO_IRQ +void esp32_gpioirqdisable(int irq); +#else +# define esp32_gpioirqdisable(irq) +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +int digitalRead(uint8_t pin); + +void attachInterrupt(uint8_t pin, void (*)(void), int mode); +void detachInterrupt(uint8_t pin); + +#ifdef __cplusplus +} +#endif + +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_GPIO_H */ diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c index 010f05eb99..9e82ae550b 100644 --- a/arch/xtensa/src/esp32/esp32_irq.c +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -128,9 +128,9 @@ void xtensa_irq_initialize(void) /* Detach all peripheral sources PRO CPU interrupts */ - for (i = 0; i < NR_PERIPHERALS) + for (i = 0; i < ESP32_NPERIPHERALS; i++) { - esp32_detach_peripheral(0, i);; + esp32_detach_peripheral(0, i); } #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 -- GitLab From 6a20560ba29f117f72b917af6a155ede4437ff3b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 26 Oct 2016 12:29:36 -0600 Subject: [PATCH 219/734] Trivia fix to typo in comment --- sched/init/os_start.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sched/init/os_start.c b/sched/init/os_start.c index 54ef7b4a27..17e1f40cde 100644 --- a/sched/init/os_start.c +++ b/sched/init/os_start.c @@ -219,8 +219,8 @@ volatile pid_t g_lastpid; * 1. This hash table greatly speeds the determination of a new unique * process ID for a task, and * 2. Is used to quickly map a process ID into a TCB. - * It has the side effects of using more memory and limiting * + * It has the side effects of using more memory and limiting * the number of tasks to CONFIG_MAX_TASKS. */ -- GitLab From 0a96f3a8c8aad8af75a2017295b9457f3863bdbb Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 26 Oct 2016 12:50:10 -0600 Subject: [PATCH 220/734] ESP32: Fix some compilation issues --- arch/xtensa/src/esp32/Make.defs | 4 +- arch/xtensa/src/esp32/chip/esp32_gpio.h | 3 +- arch/xtensa/src/esp32/esp32_cpuint.c | 46 +++++++++++---------- arch/xtensa/src/esp32/esp32_cpuint.h | 2 +- arch/xtensa/src/esp32/esp32_gpio.c | 54 +++++++++++++------------ arch/xtensa/src/esp32/esp32_gpio.h | 9 +++++ arch/xtensa/src/esp32/esp32_irq.c | 7 ++++ configs/esp32-core/nsh/defconfig | 14 +++++-- 8 files changed, 84 insertions(+), 55 deletions(-) diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 5952d79377..cc3d6a59c1 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -78,8 +78,8 @@ endif CHIP_ASRCS = CHIP_CSRCS = esp32_allocateheap.c esp32_clockconfig.c esp32_cpuint.c -CHIP_CSRCS += esp32_intdecode.c esp32_irq.c esp32_region.c esp32_start.c -CHIP_CSRCS += esp32_timerisr.c +CHIP_CSRCS += esp32_gpio.c esp32_intdecode.c esp32_irq.c esp32_region.c +CHIP_CSRCS += esp32_start.c esp32_timerisr.c # Configuration-dependent ESP32 files diff --git a/arch/xtensa/src/esp32/chip/esp32_gpio.h b/arch/xtensa/src/esp32/chip/esp32_gpio.h index 14321ff103..17cc102ed4 100644 --- a/arch/xtensa/src/esp32/chip/esp32_gpio.h +++ b/arch/xtensa/src/esp32/chip/esp32_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/esp32/chip/esp32_uart.h + * arch/xtensa/src/esp32/chip/esp32_gpio.h * * Adapted from use in NuttX by: * @@ -37,7 +37,6 @@ * Pre-preprocessor Definitions ****************************************************************************/ -#include "soc.h" #define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0000) /* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: x ; */ diff --git a/arch/xtensa/src/esp32/esp32_cpuint.c b/arch/xtensa/src/esp32/esp32_cpuint.c index c02c9483d8..7d62e6bd77 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.c +++ b/arch/xtensa/src/esp32/esp32_cpuint.c @@ -48,6 +48,8 @@ #include #include +#include "chip/esp32_dport.h" +#include "esp32_cpuint.h" #include "xtensa.h" /**************************************************************************** @@ -189,8 +191,8 @@ static const uint32_t g_priority[5] = * Allocate a CPU interrupt * * Input Parameters: - * mask - mask of candidate CPU interrupts. The CPU interrupt will be - * be allocated from free interrupts within this set + * intmask - mask of candidate CPU interrupts. The CPU interrupt will be + * be allocated from free interrupts within this set * * Returned Value: * On success, the allocated level-sensitive, CPU interrupt numbr is @@ -200,10 +202,10 @@ static const uint32_t g_priority[5] = * ****************************************************************************/ -int esp32_alloc_levelint(uint32_t mask) +int esp32_alloc_cpuint(uint32_t intmask) { irqstate_t flags; - uint32_t mask; + uint32_t bitmask; uint32_t intset; int cpuint; int ret = -ENOMEM; @@ -214,16 +216,16 @@ int esp32_alloc_levelint(uint32_t mask) flags = enter_critical_section(); - intset = g_free_cpuints & mask; + intset = g_free_cpuints & intmask; if (intset != 0) { /* Skip over initial unavailable CPU interrupts quickly in groups * of 8 interrupt. */ - for (cpuint = 0, mask = 0xff; + for (cpuint = 0, bitmask = 0xff; cpuint <= ESP32_CPUINT_MAX; - cpuint += 8, mask <<= 8); + cpuint += 8, bitmask <<= 8); /* Search for an unallocated CPU interrupt number in the remaining * intset. @@ -235,12 +237,12 @@ int esp32_alloc_levelint(uint32_t mask) * that CPU interrupt is available. */ - mask = (1ul << cpuint); - if ((intset & mask) != 0) + bitmask = (1ul << cpuint); + if ((intset & bitmask) != 0) { /* Got it! */ - g_free_cpuints &= ~mask; + g_free_cpuints &= ~bitmask; ret = cpuint; break; } @@ -322,7 +324,7 @@ void up_enable_irq(int cpuint) int esp32_alloc_levelint(int priority) { - uint32_t mask; + uint32_t intmask; DEBUGASSERT(priority >= ESP32_MIN_PRIORITY && priority <= ESP32_MAX_PRIORITY) @@ -331,8 +333,8 @@ int esp32_alloc_levelint(int priority) * interrupt priority. */ - mask = g_priority[ESP32_PRIO_INDEX(priority)] & EPS32_CPUINT_LEVELSET; - return esp_alloc_cpuint(mask); + intmask = g_priority[ESP32_PRIO_INDEX(priority)] & EPS32_CPUINT_LEVELSET; + return esp32_alloc_cpuint(intmask); } /**************************************************************************** @@ -354,7 +356,7 @@ int esp32_alloc_levelint(int priority) int esp32_alloc_edgeint(int priority) { - uint32_t mask; + uint32_t intmask; DEBUGASSERT(priority >= ESP32_MIN_PRIORITY && priority <= ESP32_MAX_PRIORITY) @@ -363,8 +365,8 @@ int esp32_alloc_edgeint(int priority) * interrupt priority. */ - mask = g_priority[ESP32_PRIO_INDEX(priority)] & EPS32_CPUINT_EDGESET; - return esp_alloc_cpuint(mask); + intmask = g_priority[ESP32_PRIO_INDEX(priority)] & EPS32_CPUINT_EDGESET; + return esp32_alloc_cpuint(intmask); } /**************************************************************************** @@ -384,16 +386,16 @@ int esp32_alloc_edgeint(int priority) void esp32_free_cpuint(int cpuint) { irqstate_t flags; - uint32_t mask; + uint32_t bitmask; DEBUGASSERT(cpuint >= 0 && cpuint < ESP32_CPUINT_NEDGEPERIPHS); /* Mark the CPU interrupt as available */ - mask = (1ul << cpuint); + bitmask = (1ul << cpuint); flags = enter_critical_section(); - DEBUGASSERT((g_free_cpuints & mask) == 0); - g_free_cpuints |= mask; + DEBUGASSERT((g_free_cpuints & bitmask) == 0); + g_free_cpuints |= bitmask; leave_critical_section(flags); } @@ -432,7 +434,7 @@ void esp32_attach_peripheral(int cpu, int periphid, int cpuint) regaddr = DPORT_PRO_MAP_REGADDR(periphid); } - putreg(cpuint, regaddr); + putreg32(cpuint, regaddr); } /**************************************************************************** @@ -468,5 +470,5 @@ void esp32_detach_peripheral(int cpu, int periphid) regaddr = DPORT_PRO_MAP_REGADDR(periphid); } - putreg(NO_CPUINT, regaddr); + putreg32(NO_CPUINT, regaddr); } diff --git a/arch/xtensa/src/esp32/esp32_cpuint.h b/arch/xtensa/src/esp32/esp32_cpuint.h index f67354db44..a3b599cf54 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.h +++ b/arch/xtensa/src/esp32/esp32_cpuint.h @@ -98,7 +98,7 @@ int esp32_alloc_edgeint(int priority); * ****************************************************************************/ -void esp32_free_cpuint(int cpuint, int priority); +void esp32_free_cpuint(int cpuint); /**************************************************************************** * Name: esp32_attach_peripheral diff --git a/arch/xtensa/src/esp32/esp32_gpio.c b/arch/xtensa/src/esp32/esp32_gpio.c index 831fd4542a..85fbd73d73 100644 --- a/arch/xtensa/src/esp32/esp32_gpio.c +++ b/arch/xtensa/src/esp32/esp32_gpio.c @@ -30,6 +30,7 @@ #include +#include #include #include @@ -38,6 +39,8 @@ #include "chip/esp32_iomux.h" #include "chip/esp32_gpio.h" +#include "xtensa.h" + #include "esp32_gpio.h" /**************************************************************************** @@ -52,7 +55,9 @@ * Private Data ****************************************************************************/ +#ifdef CONFIG_ESP32_GPIO_IRQ static uint8_t g_gpio_cpuint; +#endif static const uint8_t g_pin2func[40] = { @@ -155,9 +160,8 @@ int esp32_configgpio(int pin, gpio_pinattr_t attr) { uintptr_t regaddr; uint32_t func; - uint32_t cntl; + uint32_t cntrl; - DEBUGASSERT(pin >=0 && pin <= ESP32_NIRQ_GPIO); DEBUGASSERT(pin >=0 && pin <= ESP32_NIRQ_GPIO); /* Handle input pins */ @@ -173,7 +177,7 @@ int esp32_configgpio(int pin, gpio_pinattr_t attr) } else { - putreg32((1ul << (pin - 32), GPIO_ENABLE1_DATA_W1TC); + putreg32((1ul << (pin - 32)), GPIO_ENABLE1_DATA_W1TC); } if ((attr & PULLUP) != 0) @@ -196,42 +200,42 @@ int esp32_configgpio(int pin, gpio_pinattr_t attr) } else { - putreg32((1ul << (pin - 32), GPIO_ENABLE1_DATA_W1TS); + putreg32((1ul << (pin - 32)), GPIO_ENABLE1_DATA_W1TS); } } /* Add drivers */ - func |= ((uint32_t)(2ul << FUN_DRV_S); + func |= (uint32_t)(2ul << FUN_DRV_S); /* Input enable... Required for output as well? */ func |= FUN_IE; - if ((attr & (INPUT | OUTPUT)) != 0) { - func |= ((uint32_t)(2 << MCU_SEL_S); + func |= (uint32_t)(2 << MCU_SEL_S); } else if (attr == SPECIAL) { - func |= ((uint32_t)(((pin) == 1 || (pin) == 3) ? 0 : 1) << MCU_SEL_S); + func |= (uint32_t)((((pin) == 1 || (pin) == 3) ? 0 : 1) << MCU_SEL_S); } else { - func |= ((uint32_t)(attr >> 5) << MCU_SEL_S); + func |= (uint32_t)((attr >> 5) << MCU_SEL_S); } if ((attr & OPEN_DRAIN) != 0) { - cntl = (1 << GPIO_PIN_PAD_DRIVER_S); + cntrl = (1 << GPIO_PIN_PAD_DRIVER_S); } regaddr = DR_REG_IO_MUX_BASE + g_pin2func[pin]; putreg32(func, regaddr); regaddr = GPIO_REG(pin); - putreg32(cntl, regaddr); + putreg32(cntrl, regaddr); + return OK; } /**************************************************************************** @@ -244,30 +248,28 @@ int esp32_configgpio(int pin, gpio_pinattr_t attr) void esp32_gpiowrite(int pin, bool value) { - if (pin > 39) - { - return; - } + DEBUGASSERT(pin >=0 && pin <= ESP32_NIRQ_GPIO); + if (value) { if (pin < 32) { - GPIO.out_w1ts = ((uint32_t) 1 << pin); + putreg32((uint32_t)(1ul << pin), GPIO_OUT_W1TS_REG); } else { - GPIO.out1_w1ts.val = ((uint32_t) 1 << (pin - 32)); + putreg32((uint32_t)(1ul << (pin - 32)), GPIO_OUT1_W1TS_REG); } } else { if (pin < 32) { - GPIO.out_w1tc = ((uint32_t) 1 << pin); + putreg32((uint32_t)(1ul << pin), GPIO_OUT_W1TC_REG); } else { - GPIO.out1_w1tc.val = ((uint32_t) 1 << (pin - 32)); + putreg32((uint32_t)(1ul << (pin - 32)), GPIO_OUT1_W1TC_REG); } } } @@ -282,17 +284,19 @@ void esp32_gpiowrite(int pin, bool value) bool esp32_gpioread(int pin) { - if (pin > 39) - { - return false; - } + uint32_t regval; + + DEBUGASSERT(pin >=0 && pin <= ESP32_NIRQ_GPIO); + if (pin < 32) { - return ((GPIO.in >> pin) & 1) != 0; + regval = getreg32(GPIO_IN_REG); + return ((regval >> pin) & 1) != 0; } else { - return ((GPIO.in1.val >> (pin - 32)) & 1) != 0; + regval = getreg32(GPIO_IN1_REG); + return ((regval >> (pin - 32)) & 1) != 0; } } diff --git a/arch/xtensa/src/esp32/esp32_gpio.h b/arch/xtensa/src/esp32/esp32_gpio.h index 59f6380cbc..f765917d43 100644 --- a/arch/xtensa/src/esp32/esp32_gpio.h +++ b/arch/xtensa/src/esp32/esp32_gpio.h @@ -31,6 +31,15 @@ * Included Files ****************************************************************************/ +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + /* Bit-encoded input to esp32_configgpio() **********************************/ /* Encoded pin attributes used with esp32_configgpio() */ diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c index 9e82ae550b..33f94576bd 100644 --- a/arch/xtensa/src/esp32/esp32_irq.c +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -144,6 +144,13 @@ void xtensa_irq_initialize(void) esp32_irq_dump("initial", NR_IRQS); +#ifdef CONFIG_ESP32_GPIO_IRQ + /* Initialize GPIO interrupt support */ + + esp32_gpioirqinitialize(); +#endif + + #ifndef CONFIG_SUPPRESS_INTERRUPTS /* And finally, enable interrupts */ diff --git a/configs/esp32-core/nsh/defconfig b/configs/esp32-core/nsh/defconfig index f78400225a..f2d2b47017 100644 --- a/configs/esp32-core/nsh/defconfig +++ b/configs/esp32-core/nsh/defconfig @@ -74,14 +74,22 @@ CONFIG_ARCH="xtensa" CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_FAMILY_LX6=y -CONFIG_XTENSA_NCOPROCESSORS=1 -# CONFIG_XTENSA_USE_SWPRI is not set CONFIG_XTENSA_CALL0_ABI=y # CONFIG_XTENSA_USE_OVLY is not set +# CONFIG_ESP32_SPI2 is not set +# CONFIG_XTENSA_TIMER1 is not set +# CONFIG_XTENSA_TIMER2 is not set +CONFIG_ESP32_UART0=y +# CONFIG_ESP32_UART1 is not set +# CONFIG_ESP32_UART2 is not set CONFIG_ESP32_BT_RESERVE_DRAM=0 CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0 CONFIG_ESP32_ULP_COPROC_RESERVE_MEM=0 +# +# ESP32 Peripheral Selection +# + # # Architecture Options # @@ -558,10 +566,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set -- GitLab From ca7ca0eb5771a389d8eadacd4379f9add24e164d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 26 Oct 2016 12:59:31 -0600 Subject: [PATCH 221/734] ESP32: More compilation issues --- arch/xtensa/src/esp32/esp32_clockconfig.c | 2 +- arch/xtensa/src/esp32/esp32_gpio.c | 12 ++++++------ arch/xtensa/src/esp32/esp32_start.c | 7 ------- 3 files changed, 7 insertions(+), 14 deletions(-) diff --git a/arch/xtensa/src/esp32/esp32_clockconfig.c b/arch/xtensa/src/esp32/esp32_clockconfig.c index 7ccc12090e..88f3351cb4 100644 --- a/arch/xtensa/src/esp32/esp32_clockconfig.c +++ b/arch/xtensa/src/esp32/esp32_clockconfig.c @@ -22,7 +22,7 @@ * See the License for the specific language governing permissions and * limitations under the License. * - **************************************************************************** + ****************************************************************************/ /**************************************************************************** * Included Files diff --git a/arch/xtensa/src/esp32/esp32_gpio.c b/arch/xtensa/src/esp32/esp32_gpio.c index 85fbd73d73..e4bfc63699 100644 --- a/arch/xtensa/src/esp32/esp32_gpio.c +++ b/arch/xtensa/src/esp32/esp32_gpio.c @@ -34,13 +34,14 @@ #include #include +#include #include #include +#include "xtensa.h" #include "chip/esp32_iomux.h" #include "chip/esp32_gpio.h" -#include "xtensa.h" - +#include "esp32_cpuint.h" #include "esp32_gpio.h" /**************************************************************************** @@ -121,7 +122,6 @@ static void gpio_dispatch(int irq, uint32_t status, uint32_t *regs) static int gpio_interrupt(int irq, FAR void *context) { uint32_t status; - uint32_t gpio_intr_status_h = 0; /* Read and clear the lower GPIO interrupt status */ @@ -140,7 +140,7 @@ static int gpio_interrupt(int irq, FAR void *context) /* Dispatch pending interrupts in the lower GPIO status register */ gpio_dispatch(ESP32_FIRST_GPIOIRQ + 32, status, (uint32_t *)context); - reutnr OK; + return OK; } #endif @@ -386,7 +386,7 @@ void esp32_gpioirqenable(int irq, gpio_intrtype_t intrtype) } regval |= (intrtype << GPIO_PIN_INT_TYPE_S); - puttreg32(regval, regaddr); + putreg32(regval, regaddr); up_enable_irq(g_gpio_cpuint); } @@ -420,7 +420,7 @@ void esp32_gpioirqdisable(int irq) regaddr = GPIO_REG(pin); regval = getreg32(regaddr); regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M); - puttreg32(regval, regaddr); + putreg32(regval, regaddr); up_enable_irq(g_gpio_cpuint); } diff --git a/arch/xtensa/src/esp32/esp32_start.c b/arch/xtensa/src/esp32/esp32_start.c index c52924a94e..7d6ef7d5dc 100644 --- a/arch/xtensa/src/esp32/esp32_start.c +++ b/arch/xtensa/src/esp32/esp32_start.c @@ -105,13 +105,6 @@ void IRAM_ATTR __start(void) esp32_board_initialize(); -#warning These belong elsewhere -#if 0 - ets_setup_syscalls(); - esp_ipc_init(); - spi_flash_init(); -#endif - /* Bring up NuttX */ os_start(); -- GitLab From 4d29b898a6fb36c657cab1c6820e10ef5c2bb4a0 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Wed, 26 Oct 2016 13:27:58 -0600 Subject: [PATCH 222/734] Add RGB LED support on STM32F103 Minimum board --- configs/stm32f103-minimum/include/board.h | 14 ++ configs/stm32f103-minimum/src/Makefile | 4 + configs/stm32f103-minimum/src/stm32_bringup.c | 11 + configs/stm32f103-minimum/src/stm32_rgbled.c | 194 ++++++++++++++++++ .../stm32f103-minimum/src/stm32f103_minimum.h | 20 ++ 5 files changed, 243 insertions(+) create mode 100644 configs/stm32f103-minimum/src/stm32_rgbled.c diff --git a/configs/stm32f103-minimum/include/board.h b/configs/stm32f103-minimum/include/board.h index 1dc84378c7..321d5b40fb 100644 --- a/configs/stm32f103-minimum/include/board.h +++ b/configs/stm32f103-minimum/include/board.h @@ -186,6 +186,20 @@ * Note: we don't need redefine GPIO_TIM3_CH3OUT because PB0 is not remap pin. */ +/* RGB LED + * + * R = TIM1 CH1 on PA8 | G = TIM2 CH2 on PA1 | B = TIM4 CH4 on PB9 + * + * Note: Pin configs: GPIO_TIM1_CH1OUT ; GPIO_TIM2_CH2OUT ; GPIO_TIM4_CH4OUT + */ + +#define RGBLED_RPWMTIMER 1 +#define RGBLED_RPWMCHANNEL 1 +#define RGBLED_GPWMTIMER 2 +#define RGBLED_GPWMCHANNEL 2 +#define RGBLED_BPWMTIMER 4 +#define RGBLED_BPWMCHANNEL 4 + /************************************************************************************ * Public Data ************************************************************************************/ diff --git a/configs/stm32f103-minimum/src/Makefile b/configs/stm32f103-minimum/src/Makefile index 3259d5ab12..3baf4b64dc 100644 --- a/configs/stm32f103-minimum/src/Makefile +++ b/configs/stm32f103-minimum/src/Makefile @@ -57,6 +57,10 @@ ifeq ($(CONFIG_PWM),y) CSRCS += stm32_pwm.c endif +ifeq ($(CONFIG_RGBLED),y) +CSRCS += stm32_rgbled.c +endif + ifeq ($(CONFIG_AUDIO_TONE),y) CSRCS += stm32_tone.c endif diff --git a/configs/stm32f103-minimum/src/stm32_bringup.c b/configs/stm32f103-minimum/src/stm32_bringup.c index fac7292c58..7c81c59c07 100644 --- a/configs/stm32f103-minimum/src/stm32_bringup.c +++ b/configs/stm32f103-minimum/src/stm32_bringup.c @@ -116,6 +116,17 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_RGBLED + /* Configure and initialize the RGB LED. */ + + ret = stm32_rgbled_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_rgbled_setup() failed: %d\n", ret); + } +#endif + + #ifdef CONFIG_CL_MFRC522 ret = stm32_mfrc522initialize("/dev/rfid0"); if (ret < 0) diff --git a/configs/stm32f103-minimum/src/stm32_rgbled.c b/configs/stm32f103-minimum/src/stm32_rgbled.c new file mode 100644 index 0000000000..21b7a0b78c --- /dev/null +++ b/configs/stm32f103-minimum/src/stm32_rgbled.c @@ -0,0 +1,194 @@ +/************************************************************************************ + * configs/stm32f4discovery/src/stm32_rgbled.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "stm32_pwm.h" +#include "stm32f103_minimum.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Configuration ********************************************************************/ + +#define HAVE_RGBLED 1 + +#ifndef CONFIG_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM1 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM2 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM4 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM1_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM2_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM4_PWM +# undef HAVE_RGBLED +#endif + +#if CONFIG_STM32_TIM1_CHANNEL != RGBLED_RPWMCHANNEL +# undef HAVE_PWM +#endif + +#if CONFIG_STM32_TIM2_CHANNEL != RGBLED_GPWMCHANNEL +# undef HAVE_PWM +#endif + +#if CONFIG_STM32_TIM4_CHANNEL != RGBLED_BPWMCHANNEL +# undef HAVE_PWM +#endif + +#ifdef HAVE_RGBLED + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_rgbled_setup + * + * Description: + * Initial for support of a connected RGB LED using PWM. + * + ************************************************************************************/ + +int stm32_rgbled_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *ledr; + struct pwm_lowerhalf_s *ledg; + struct pwm_lowerhalf_s *ledb; + struct pwm_info_s info; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledr = stm32_pwminitialize(RGBLED_RPWMTIMER); + if (!ledr) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDR\n"); + return -ENODEV; + } + + /* Define frequency and duty cycle */ + + info.frequency = 100; + info.duty = 0; + + /* Initialize LED R */ + + ledr->ops->setup(ledr); + ledr->ops->start(ledr, &info); + + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledg = stm32_pwminitialize(RGBLED_GPWMTIMER); + if (!ledg) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDG\n"); + return -ENODEV; + } + + /* Initialize LED G */ + + ledg->ops->setup(ledg); + ledg->ops->start(ledg, &info); + + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledb = stm32_pwminitialize(RGBLED_BPWMTIMER); + if (!ledb) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDB\n"); + return -ENODEV; + } + + /* Initialize LED B */ + + ledb->ops->setup(ledb); + ledb->ops->start(ledb, &info); + + /* Register the RGB LED diver at "/dev/rgbled0" */ + + ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb); + if (ret < 0) + { + lederr("ERROR: rgbled_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#else +# error "HAVE_RGBLED is undefined" +#endif /* HAVE_RGBLED */ diff --git a/configs/stm32f103-minimum/src/stm32f103_minimum.h b/configs/stm32f103-minimum/src/stm32f103_minimum.h index 7b0ae80221..b3d4ff0a91 100644 --- a/configs/stm32f103-minimum/src/stm32f103_minimum.h +++ b/configs/stm32f103-minimum/src/stm32f103_minimum.h @@ -138,6 +138,26 @@ int stm32_bringup(void); void stm32_spidev_initialize(void); +/**************************************************************************** + * Name stm32_rgbled_setup + * + * Description: + * This function is called by board initialization logic to configure the + * RGB LED driver. This function will register the driver as /dev/rgbled0. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RGBLED +int stm32_rgbled_setup(void); +#endif + /************************************************************************************ * Name: stm32_usbinitialize * -- GitLab From 0bab23fb1bc03e3fcb43b3f5c58b4130af849609 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Wed, 26 Oct 2016 21:00:50 +0000 Subject: [PATCH 223/734] stm32_i2c.c Dejavu --- arch/arm/src/stm32f7/stm32_i2c.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c index 3786e7d52c..845dc0e24b 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.c +++ b/arch/arm/src/stm32f7/stm32_i2c.c @@ -2245,6 +2245,10 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv) * - Provide means to set peripheral clock source via RCC_CFGR3_I2CxSW * - Set to HSI by default, make Kconfig option */ + + /* Force a frequency update */ + + priv->frequency = 0; stm32_i2c_setclock(priv, 100000); -- GitLab From 314dd62dd5c3fd0a810ee7310cc7313146eb137e Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Wed, 26 Oct 2016 21:10:59 +0000 Subject: [PATCH 224/734] stm32f76xx77xx_pinmap.h Missed one --- arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h index ef5fec6610..6054d70242 100644 --- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h @@ -630,6 +630,7 @@ #define GPIO_I2C4_SDA_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN13) #define GPIO_I2C4_SDA_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN15) #define GPIO_I2C4_SDA_3 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN12) +#define GPIO_I2C4_SDA_4 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) #define GPIO_I2C4_SMBA_1 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN11) #define GPIO_I2C4_SMBA_2 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN13) #define GPIO_I2C4_SMBA_3 (GPIO_ALT|GPIO_AF4 |GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN10) -- GitLab From 76788040d58d5bfd98c452eb23bd528917a09776 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 26 Oct 2016 15:44:39 -0600 Subject: [PATCH 225/734] ESP32: Add esp32_config.h --- arch/arm/src/stm32f7/stm32_i2c.c | 1 - arch/xtensa/include/esp32/chip.h | 5 + arch/xtensa/src/esp32/esp32_config.h | 146 +++++++++++++++++++++++++++ 3 files changed, 151 insertions(+), 1 deletion(-) create mode 100644 arch/xtensa/src/esp32/esp32_config.h diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c index 845dc0e24b..eda1fba72a 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.c +++ b/arch/arm/src/stm32f7/stm32_i2c.c @@ -2249,7 +2249,6 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv) /* Force a frequency update */ priv->frequency = 0; - stm32_i2c_setclock(priv, 100000); /* Enable I2C peripheral */ diff --git a/arch/xtensa/include/esp32/chip.h b/arch/xtensa/include/esp32/chip.h index 95e9e2cac3..e3cbc193c5 100644 --- a/arch/xtensa/include/esp32/chip.h +++ b/arch/xtensa/include/esp32/chip.h @@ -46,6 +46,11 @@ * Pre-processor Definitions ****************************************************************************/ +/* Characterize each supported ESP32 part */ + +#define ESP32_NSPI 4 /* SPI0-3 */ +#define ESP32_NUARTS 3 /* UART0-2 */ + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/arch/xtensa/src/esp32/esp32_config.h b/arch/xtensa/src/esp32/esp32_config.h new file mode 100644 index 0000000000..102ee81f65 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_config.h @@ -0,0 +1,146 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_config.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_CONFIG_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_CONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* GPIO IRQs ****************************************************************/ + +/* UARTs ********************************************************************/ +/* Don't enable UARTs not supported by the chip. */ + +#if ESP32_NUART < 1 +# undef CONFIG_ESP32_UART0 +# undef CONFIG_ESP32_UART1 +# undef CONFIG_ESP32_UART2 +#elif ESP32_NUART < 2 +# undef CONFIG_ESP32_UART1 +# undef CONFIG_ESP32_UART2 +#elif ESP32_NUART < 3 +# undef CONFIG_ESP32_UART2 +#endif + +/* Are any UARTs enabled? */ + +#undef HAVE_UART_DEVICE +#if defined(CONFIG_ESP32_UART0) || defined(CONFIG_ESP32_UART1) || \ + defined(CONFIG_ESP32_UART2) +# define HAVE_UART_DEVICE 1 +#endif + +/* UART Flow Control ********************************************************/ + +#ifndef CONFIG_ESP32_UART0 +# undef CONFIG_UART0_IFLOWCONTROL +#endif +#ifndef CONFIG_ESP32_UART1 +# undef CONFIG_UART1_IFLOWCONTROL +#endif +#ifndef CONFIG_ESP32_UART2 +# undef CONFIG_UART2_IFLOWCONTROL +#endif + +/* Serial Console ***********************************************************/ +/* Is there a serial console? There should be no more than one defined. It + * could be on any UARTn, n=1,..,ESP32_NUART, or USARTn, n=1,.., ESP32_NUSART + */ + +#undef HAVE_SERIAL_CONSOLE +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_ESP32_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_ESP32_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_ESP32_UART2) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#else +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +#endif + +/* SPI ******************************************************************************/ +/* Don't enable SPI peripherals not supported by the chip. */ + +#if ESP32_NSPI < 1 +# undef CONFIG_ESP32_SPI0 +# undef CONFIG_ESP32_SPI1 +# undef CONFIG_ESP32_SPI2 +# undef CONFIG_ESP32_SPI3 +#elif ESP32_NSPI < 2 +# undef CONFIG_ESP32_SPI1 +# undef CONFIG_ESP32_SPI2 +# undef CONFIG_ESP32_SPI3 +#elif ESP32_NSPI < 3 +# undef CONFIG_ESP32_SPI2 +# undef CONFIG_ESP32_SPI3 +#elif ESP32_NSPI < 4 +# undef CONFIG_ESP32_SPI3 +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_CONFIG_H */ -- GitLab From d9c2789253f44d6e0e27eedbec65c1ec65d66f7f Mon Sep 17 00:00:00 2001 From: Vytautas Lukenskas Date: Thu, 27 Oct 2016 07:00:32 -0600 Subject: [PATCH 226/734] LPC32xx serial: Fix a typo in ioctl TIOCSRS485 ioctl. --- arch/arm/src/lpc43xx/lpc43_serial.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/lpc43xx/lpc43_serial.c b/arch/arm/src/lpc43xx/lpc43_serial.c index 3fa30e87e2..def68b88b5 100644 --- a/arch/arm/src/lpc43xx/lpc43_serial.c +++ b/arch/arm/src/lpc43xx/lpc43_serial.c @@ -933,7 +933,7 @@ static inline int up_set_rs485_mode(struct up_dev_s *priv, /* Are we enabling or disabling RS-485 support? */ - if ((mode->flags && SER_RS485_RTS_ON_SEND) != 0) + if ((mode->flags & SER_RS485_ENABLED) == 0) { /* Disable all RS-485 features */ @@ -961,7 +961,7 @@ static inline int up_set_rs485_mode(struct up_dev_s *priv, * be inverted. */ - if ((mode->flags && SER_RS485_RTS_ON_SEND) != 0) + if ((mode->flags & SER_RS485_RTS_ON_SEND) != 0) { regval |= UART_RS485CTRL_OINV; } -- GitLab From 1796a25e537ec5f144c1eba9920c6c287d400b6e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marc=20Recht=C3=A9?= Date: Thu, 27 Oct 2016 07:10:36 -0600 Subject: [PATCH 227/734] Correct a problem in clock_gettime(CLOCK_REALTIME, &time); which is ahead by 1 month of the specified CONFIG_START_MONTH --- libc/time/lib_daysbeforemonth.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libc/time/lib_daysbeforemonth.c b/libc/time/lib_daysbeforemonth.c index 8c09c2203e..8c66dc808b 100644 --- a/libc/time/lib_daysbeforemonth.c +++ b/libc/time/lib_daysbeforemonth.c @@ -91,8 +91,8 @@ static const uint16_t g_daysbeforemonth[13] = int clock_daysbeforemonth(int month, bool leapyear) { - int retval = g_daysbeforemonth[month]; - if (month >= 2 && leapyear) + int retval = g_daysbeforemonth[month-1]; + if (month > 2 && leapyear) { retval++; } -- GitLab From 57ad019fba24e2040ff6760cff9a0efedecf3236 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 27 Oct 2016 08:20:16 -0600 Subject: [PATCH 228/734] Revert "Correct a problem in clock_gettime(CLOCK_REALTIME, &time); which is ahead by 1 month of the specified CONFIG_START_MONTH" I don't believe this change is correct in general. Nomralling clock_isleapyear() is called with tm_mon which is in the range of 0-11. That change would be bad for that range. It would make sense for a range of 1-12, but that is not how tm_mon is defined. This reverts commit 1796a25e537ec5f144c1eba9920c6c287d400b6e. --- libc/time/lib_daysbeforemonth.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libc/time/lib_daysbeforemonth.c b/libc/time/lib_daysbeforemonth.c index 8c66dc808b..8c09c2203e 100644 --- a/libc/time/lib_daysbeforemonth.c +++ b/libc/time/lib_daysbeforemonth.c @@ -91,8 +91,8 @@ static const uint16_t g_daysbeforemonth[13] = int clock_daysbeforemonth(int month, bool leapyear) { - int retval = g_daysbeforemonth[month-1]; - if (month > 2 && leapyear) + int retval = g_daysbeforemonth[month]; + if (month >= 2 && leapyear) { retval++; } -- GitLab From 0967864c9208ac010099ad780ef3fcf6b07f4753 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 27 Oct 2016 08:32:23 -0600 Subject: [PATCH 229/734] Correct clock initialization. The correct range for the month is 0-11 but is entered as 1-12 in the .config file --- arch/xtensa/src/esp32/esp32_gpio.c | 9 ++++++++- libc/time/lib_calendar2utc.c | 24 ------------------------ 2 files changed, 8 insertions(+), 25 deletions(-) diff --git a/arch/xtensa/src/esp32/esp32_gpio.c b/arch/xtensa/src/esp32/esp32_gpio.c index e4bfc63699..c40b6b097a 100644 --- a/arch/xtensa/src/esp32/esp32_gpio.c +++ b/arch/xtensa/src/esp32/esp32_gpio.c @@ -319,10 +319,17 @@ void esp32_gpioirqinitialize(void) g_gpio_cpuint = esp32_alloc_levelint(1); DEBUGASSERT(g_gpio_cpuint >= 0); + /* Set up to receive peripheral interrupts on the current CPU */ + +#ifdef CONFIG_SMP + cpu = up_cpu_index(); +#else + cpu = 0; +#endif + /* Attach the GPIO peripheral to the allocated CPU interrupt */ up_disable_irq(g_gpio_cpuint); - cpu = up_cpu_index(); esp32_attach_peripheral(cpu, ESP32_PERIPH_CPU_GPIO, g_gpio_cpuint); /* Attach and enable the interrupt handler */ diff --git a/libc/time/lib_calendar2utc.c b/libc/time/lib_calendar2utc.c index 2c2d507d9d..51a8581af4 100644 --- a/libc/time/lib_calendar2utc.c +++ b/libc/time/lib_calendar2utc.c @@ -45,30 +45,6 @@ #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Type Declarations - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Public Constant Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ -- GitLab From 123c520db42113c8553c2741b8fdcd8cb95400c2 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 27 Oct 2016 08:36:24 -0600 Subject: [PATCH 230/734] Correct time initialization for the case where time is initialized from settings in the .config file. The correct range for month (tm_mon) internally is 0-11, not 1-12 as it is in the .config file. --- libc/time/lib_daysbeforemonth.c | 36 ++++++++++----------------------- libc/time/lib_gmtimer.c | 7 +------ sched/clock/clock_initialize.c | 3 ++- 3 files changed, 14 insertions(+), 32 deletions(-) diff --git a/libc/time/lib_daysbeforemonth.c b/libc/time/lib_daysbeforemonth.c index 8c09c2203e..d17d05b57e 100644 --- a/libc/time/lib_daysbeforemonth.c +++ b/libc/time/lib_daysbeforemonth.c @@ -44,26 +44,6 @@ #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Type Declarations - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Public Constant Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - /**************************************************************************** * Private Data ****************************************************************************/ @@ -73,10 +53,6 @@ static const uint16_t g_daysbeforemonth[13] = 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334, 365 }; -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -85,7 +61,16 @@ static const uint16_t g_daysbeforemonth[13] = * Function: clock_daysbeforemonth * * Description: - * Get the number of days that occurred before the beginning of the month. + * Get the number of days that occurred before the beginning of the + * month. + * + * Input Parameters: + * month - The month in the form of tm_mon, that is a range of 0-11. + * leapyear - True if leap year and there are 29 days in February. + * NOTE the month=1 is February. + * + * Returned Value: + * The number of days that occurred before the month * ****************************************************************************/ @@ -96,6 +81,7 @@ int clock_daysbeforemonth(int month, bool leapyear) { retval++; } + return retval; } diff --git a/libc/time/lib_gmtimer.c b/libc/time/lib_gmtimer.c index a9624747c9..10173d8c97 100644 --- a/libc/time/lib_gmtimer.c +++ b/libc/time/lib_gmtimer.c @@ -54,10 +54,6 @@ #define SEC_PER_HOUR ((time_t)60 * SEC_PER_MIN) #define SEC_PER_DAY ((time_t)24 * SEC_PER_HOUR) -/**************************************************************************** - * Private Type Declarations - ****************************************************************************/ - /**************************************************************************** * Private Function Prototypes ****************************************************************************/ @@ -90,8 +86,7 @@ static void clock_utc2julian(time_t jdn, int *year, int *month, int *day); ****************************************************************************/ /**************************************************************************** - * Function: clock_calendar2utc, clock_gregorian2utc, - * and clock_julian2utc + * Function: clock_utc2calendar, clock_utc2gregorian, and clock_utc2julian * * Description: * Calendar to UTC conversion routines. These conversions diff --git a/sched/clock/clock_initialize.c b/sched/clock/clock_initialize.c index 9e5d9f93f4..0113e5e0fc 100644 --- a/sched/clock/clock_initialize.c +++ b/sched/clock/clock_initialize.c @@ -61,6 +61,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Standard time definitions (in units of seconds) */ #define SEC_PER_MIN ((time_t)60) @@ -151,7 +152,7 @@ static inline int clock_basetime(FAR struct timespec *tp) * month, and date */ - jdn = clock_calendar2utc(CONFIG_START_YEAR, CONFIG_START_MONTH, + jdn = clock_calendar2utc(CONFIG_START_YEAR, CONFIG_START_MONTH - 1, CONFIG_START_DAY); /* Set the base time as seconds into this julian day. */ -- GitLab From cf73c9e1d1246ea655e8202e8a30f5f432d33f12 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 27 Oct 2016 10:43:58 -0600 Subject: [PATCH 231/734] EPS32: Add GPIO ROM interface definitions --- arch/xtensa/src/esp32/Kconfig | 107 ++++++- arch/xtensa/src/esp32/Make.defs | 4 + arch/xtensa/src/esp32/rom/esp32_gpio.h | 424 +++++++++++++++++++++++++ configs/esp32-core/nsh/defconfig | 40 ++- 4 files changed, 565 insertions(+), 10 deletions(-) create mode 100644 arch/xtensa/src/esp32/rom/esp32_gpio.h diff --git a/arch/xtensa/src/esp32/Kconfig b/arch/xtensa/src/esp32/Kconfig index a3ad7fcaa9..6ef278294e 100644 --- a/arch/xtensa/src/esp32/Kconfig +++ b/arch/xtensa/src/esp32/Kconfig @@ -7,6 +7,10 @@ if ARCH_CHIP_ESP32 menu "ESP32 Peripheral Selection" +config ESP32_UART + bool + default n + config ESP32_BT bool "Bluetooth" default n @@ -175,14 +179,23 @@ config ESP32_RWDT config ESP32_UART0 bool "UART 0" default n + select ESP32_UART + select UART0_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS config ESP32_UART1 bool "UART 1" default n + select ESP32_UART + select UART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS config ESP32_UART2 bool "UART 2" default n + select ESP32_UART + select UART2_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS config ESP32_WIRELESS bool "Wireless" @@ -193,10 +206,7 @@ config ESP32_WIRELESS endmenu # ESP32 Peripheral Selection -config ESP32_GPIO_IRQ - bool "GPIO pin interrupts" - ---help--- - Enable support for interrupting GPIO pins +menu "Memory Configuration" config ESP32_BT_RESERVE_DRAM int "Reserved BT DRAM" @@ -210,4 +220,93 @@ config ESP32_ULP_COPROC_RESERVE_MEM int "Reserved ULP co-processor DRAM" default 0 +endmenu # Memory Configuration + +config ESP32_GPIO_IRQ + bool "GPIO pin interrupts" + ---help--- + Enable support for interrupting GPIO pins + +menu "UART configuration" + depends on ESP32_UART + +if ESP32_UART0 + +config ESP32_UART0_TXPIN + int "UART0 Tx Pin" + default 0 + range 0 39 + +config ESP32_UART0_TXPIN + int "UART0 Tx Pin" + default 0 + range 0 39 + +if SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL +config ESP32_UART0_RTSPIN + int "UART0 RTS Pin" + default 0 + range 0 39 + +config ESP32_UART0_CTSPIN + int "UART0 CTS Pin" + default 0 + range 0 39 + +endif # SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL +endif # ESP32_UART0 + +if ESP32_UART1 + +config ESP32_UART1_TXPIN + int "UART1 Tx Pin" + default 0 + range 0 39 + +config ESP32_UART1_TXPIN + int "UART1 Tx Pin" + default 0 + range 0 39 + +if SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL +config ESP32_UART1_RTSPIN + int "UART1 RTS Pin" + default 0 + range 0 39 + +config ESP32_UART1_CTSPIN + int "UART1 CTS Pin" + default 0 + range 0 39 + +endif # SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL +endif # ESP32_UART1 + +if ESP32_UART2 + +config ESP32_UART2_TXPIN + int "UART2 Tx Pin" + default 0 + range 0 39 + +config ESP32_UART2_TXPIN + int "UART2 Tx Pin" + default 0 + range 0 39 + +if SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL +config ESP32_UART2_RTSPIN + int "UART2 RTS Pin" + default 0 + range 0 39 + +config ESP32_UART2_CTSPIN + int "UART2 CTS Pin" + default 0 + range 0 39 + +endif # SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL +endif # ESP32_UART2 + +endmenu # UART configuration endif # ARCH_CHIP_ESP32 diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index cc3d6a59c1..64c855df37 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -88,3 +88,7 @@ CHIP_ASRCS = esp32_cpuindex.S #CMN_CSRCS += esp32_cpustart.c esp32_cpupause.c esp32_cpuidlestack.c CMN_CSRCS += esp32_cpustart.c endif + +ifeq ($(CONFIG_ESP32_UART),y) +CMN_CSRCS += esp32_serial.c +endif diff --git a/arch/xtensa/src/esp32/rom/esp32_gpio.h b/arch/xtensa/src/esp32/rom/esp32_gpio.h new file mode 100644 index 0000000000..8e426e0cb7 --- /dev/null +++ b/arch/xtensa/src/esp32/rom/esp32_gpio.h @@ -0,0 +1,424 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_gpio.c + * + * Developed for NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derivies from sample code provided by Expressif Systems: + * + * Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +#ifndef __XTENSA_SRC_ESP32_ROM_ESP32_GPIO_H +#define __XTENSA_SRC_ESP32_ROM_ESP32_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip/gpio_reg.h" + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +enum gpio_inttype_e +{ + GPIO_PIN_INTR_DISABLE = 0, + GPIO_PIN_INTR_POSEDGE = 1, + GPIO_PIN_INTR_NEGEDGE = 2, + GPIO_PIN_INTR_ANYEGDE = 3, + GPIO_PIN_INTR_LOLEVEL = 4, + GPIO_PIN_INTR_HILEVEL = 5 +}; + +typedef enum gpio_inttype_e GPIO_INT_TYPE; + +/* GPIO interrupt handler, registered through gpio_intr_handler_register */ + +typedef void (*gpio_intr_handler_fn_t)(uint32_t intr_mask, bool high, void *arg); + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/**************************************************************************** + * Name: gpio_init + * + * Description: + * Initialize GPIO. This includes reading the GPIO Configuration DataSet + * to initialize "output enables" and pin configurations for each gpio pin. + * Please do not call this function in SDK. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void gpio_init(void); + +/**************************************************************************** + * Name: gpio_output_set + * + * Description: + * Change GPIO(0-31) pin output by setting, clearing, or disabling pins, + * GPIO0<->BIT(0). There is no particular ordering guaranteed; so if the + * order of writes is significant, calling code should divide a single + * call into multiple calls. + * + * Input Parameters: + * set_mask - the gpios that need high level. + * clear_mask - the gpios that need low level. + * enable_mask - the gpios that need be changed. + * disable_mask - the gpios that need diable output. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, + uint32_t enable_mask, uint32_t disable_mask); + +/**************************************************************************** + * Name: gpio_output_set_high + * + * Description: + * Change GPIO(32-39) pin output by setting, clearing, or disabling pins, + * GPIO32<->BIT(0). There is no particular ordering guaranteed; so if the + * order of writes is significant, calling code should divide a single call + * into multiple calls. + * + * Input Parameters: + * set_mask - the gpios that need high level. + * clear_mask - the gpios that need low level. + * enable_mask - the gpios that need be changed. + * disable_mask - the gpios that need diable output. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void gpio_output_set_high(uint32_t set_mask, uint32_t clear_mask, + uint32_t enable_mask, uint32_t disable_mask); + +/**************************************************************************** + * Name: gpio_input_get + * + * Description: + * Sample the value of GPIO input pins(0-31) and returns a bitmask. + * + * Input Parameters: + * None + * + * Returned Value: + * Bitmask for GPIO input pins, BIT(0) for GPIO0. + * + ****************************************************************************/ + +uint32_t gpio_input_get(void); + +/**************************************************************************** + * Name: gpio_input_get_high + * + * Description: + * Sample the value of GPIO input pins(32-39) and returns a bitmask. + * + * Input Parameters: + * None + * + * Returned Value: + * Bitmask for GPIO input pins, BIT(0) for GPIO32. + * + ****************************************************************************/ + +uint32_t gpio_input_get_high(void); + +/**************************************************************************** + * Name: gpio_intr_handler_register + * + * Description: + * Register an application-specific interrupt handler for GPIO pin + * interrupts. Once the interrupt handler is called, it will not be + * called again until after a call to gpio_intr_ack. + * + * Input Parameters: + * fn - gpio application-specific interrupt handler + * arg - gpio application-specific interrupt handler argument. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void gpio_intr_handler_register(gpio_intr_handler_fn_t fn, void *arg); + +/**************************************************************************** + * Name: gpio_intr_pending + * + * Description: + * Get gpio interrupts which happens but not processed. + * + * Input Parameters: + * + * Returned Value: + * Bitmask for GPIO pending interrupts, BIT(0) for GPIO0. + * + ****************************************************************************/ + +uint32_t gpio_intr_pending(void); + +/**************************************************************************** + * Name: gpio_intr_pending_high + * + * Description: + * Get gpio interrupts which happens but not processed. + * + * Input Parameters: + * + * Returned Value: + * Bitmask for GPIO pending interrupts, BIT(0) for GPIO32. + * + ****************************************************************************/ + +uint32_t gpio_intr_pending_high(void); + +/**************************************************************************** + * Name: gpio_intr_ack + * + * Description: + * Ack gpio interrupts to process pending interrupts. + * + * Input Parameters: + * ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO0. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void gpio_intr_ack(uint32_t ack_mask); + +/**************************************************************************** + * Name: gpio_intr_ack_high + * + * Description: + * Ack gpio interrupts to process pending interrupts. + * + * Input Parameters: + * ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO32. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void gpio_intr_ack_high(uint32_t ack_mask); + +/**************************************************************************** + * Name: gpio_pin_wakeup_enable + * + * Description: + * Set GPIO to wakeup the ESP32. + * + * Input Parameters: + * i - gpio number. + * intr_state - only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used + * + * Returned Value: + * None + * + ****************************************************************************/ + +void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state); + +/**************************************************************************** + * Name: gpio_pin_wakeup_disable + * + * Description: + * disable GPIOs to wakeup the ESP32. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void gpio_pin_wakeup_disable(void); + +/**************************************************************************** + * Name: gpio_matrix_in + * + * Description: + * Set gpio input to a signal, one gpio can input to several signals. + * + * Input Parameters: + * gpio - gpio number, 0~0x27 + * gpio == 0x30, input 0 to signal + * gpio == 0x34, ??? + * gpio == 0x38, input 1 to signal + * + * signal_idx - signal index. + * inv - the signal is inv or not + * + * Returned Value: + * None + * + ****************************************************************************/ + +void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv); + +/**************************************************************************** + * Name: gpio_matrix_out + * + * Description: + * Set signal output to gpio, one signal can output to several gpios. + * + * Input Parameters: + * gpio - gpio number, 0~0x27 + * signal_idx - signal index. + * signal_idx == 0x100, cancel output put to the gpio + * out_inv - the signal output is inv or not + * oen_inv - the signal output enable is inv or not + * + * Returned Value: + * None + * + ****************************************************************************/ + +void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, + bool oen_inv); + +/**************************************************************************** + * Name: + * + * Description: + * Select pad as a gpio function from IOMUX. + * + * Input Parameters: + * gpio_num - gpio number, 0~0x27 + * + * Returned Value: + * None + * + ****************************************************************************/ + +void gpio_pad_select_gpio(uint8_t gpio_num); + +/**************************************************************************** + * Name: gpio_pad_set_drv + * + * Description: + * Set pad driver capability. + * + * Input Parameters: + * gpio_num - gpio number, 0~0x27 + * drv - 0-3 + * + * Returned Value: + * None + * + ****************************************************************************/ + +void gpio_pad_set_drv(uint8_t gpio_num, uint8_t drv); + +/**************************************************************************** + * Name: gpio_pad_pullup + * + * Description: + * Pull up the pad from gpio number. + * + * Input Parameters: + * gpio_num - gpio number, 0~0x27 + * + * Returned Value: + * None + * + ****************************************************************************/ + +void gpio_pad_pullup(uint8_t gpio_num); + +/**************************************************************************** + * Name: gpio_pad_pulldown + * + * Description: + * Pull down the pad from gpio number. + * + * Input Parameters: + * gpio_num - gpio number, 0~0x27 + * + * Returned Value: + * None + * + ****************************************************************************/ + +void gpio_pad_pulldown(uint8_t gpio_num); + +/**************************************************************************** + * Name: gpio_pad_unhold + * + * Description: + * Unhold the pad from gpio number. + * + * Input Parameters: + * gpio_num - gpio number, 0~0x27 + * + * Returned Value: + * None + * + ****************************************************************************/ + +void gpio_pad_unhold(uint8_t gpio_num); + +/**************************************************************************** + * Name: gpio_pad_hold + * + * Description: + * Hold the pad from gpio number. + * + * Input Parameters: + * gpio_num - gpio number, 0~0x27 + * + * Returned Value: + * None + * + ****************************************************************************/ + +void gpio_pad_hold(uint8_t gpio_num); + +#ifdef __cplusplus +} +#endif + +#endif /* __XTENSA_SRC_ESP32_ROM_ESP32_GPIO_H */ diff --git a/configs/esp32-core/nsh/defconfig b/configs/esp32-core/nsh/defconfig index f2d2b47017..8d40ba790f 100644 --- a/configs/esp32-core/nsh/defconfig +++ b/configs/esp32-core/nsh/defconfig @@ -72,10 +72,12 @@ CONFIG_ARCH_XTENSA=y # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="xtensa" CONFIG_ARCH_CHIP="esp32" +# CONFIG_SERIAL_TERMIOS is not set CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_FAMILY_LX6=y CONFIG_XTENSA_CALL0_ABI=y # CONFIG_XTENSA_USE_OVLY is not set +CONFIG_ESP32_UART=y # CONFIG_ESP32_SPI2 is not set # CONFIG_XTENSA_TIMER1 is not set # CONFIG_XTENSA_TIMER2 is not set @@ -85,11 +87,21 @@ CONFIG_ESP32_UART0=y CONFIG_ESP32_BT_RESERVE_DRAM=0 CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0 CONFIG_ESP32_ULP_COPROC_RESERVE_MEM=0 +# CONFIG_ESP32_GPIO_IRQ is not set +CONFIG_ESP32_UART0_TXPIN=0 # # ESP32 Peripheral Selection # +# +# Memory Configuration +# + +# +# UART configuration +# + # # Architecture Options # @@ -341,10 +353,10 @@ CONFIG_SPI_EXCHANGE=y CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set -# CONFIG_SERIAL_CONSOLE is not set +CONFIG_SERIAL_CONSOLE=y # CONFIG_16550_UART is not set # CONFIG_UART_SERIALDRIVER is not set -# CONFIG_UART0_SERIALDRIVER is not set +CONFIG_UART0_SERIALDRIVER=y # CONFIG_UART1_SERIALDRIVER is not set # CONFIG_UART2_SERIALDRIVER is not set # CONFIG_UART3_SERIALDRIVER is not set @@ -365,12 +377,28 @@ CONFIG_SERIAL=y # CONFIG_USART7_SERIALDRIVER is not set # CONFIG_USART8_SERIALDRIVER is not set # CONFIG_OTHER_UART_SERIALDRIVER is not set -# CONFIG_MCU_SERIAL is not set +CONFIG_MCU_SERIAL=y CONFIG_STANDARD_SERIAL=y # CONFIG_SERIAL_IFLOWCONTROL is not set # CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_SERIAL_DMA is not set -# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +CONFIG_UART0_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART0 Configuration +# +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 +# CONFIG_UART0_IFLOWCONTROL is not set +# CONFIG_UART0_OFLOWCONTROL is not set +# CONFIG_UART0_DMA is not set # CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set @@ -385,7 +413,7 @@ CONFIG_STANDARD_SERIAL=y # CONFIG_RAMLOG is not set # CONFIG_SYSLOG_INTBUFFER is not set # CONFIG_SYSLOG_TIMESTAMP is not set -# CONFIG_SYSLOG_SERIAL_CONSOLE is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y # CONFIG_SYSLOG_CHAR is not set CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set @@ -566,10 +594,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set -- GitLab From bc51fdb96c0b68a305c5d4b9ca4ab0af0c89022d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 27 Oct 2016 11:04:24 -0600 Subject: [PATCH 232/734] ESP32: Add GPIO signal mapping file --- arch/xtensa/src/esp32/chip/esp32_dport.h | 2 +- .../xtensa/src/esp32/chip/esp32_gpio_sigmap.h | 439 ++++++++++++++++++ arch/xtensa/src/esp32/chip/esp32_rtccntl.h | 2 +- arch/xtensa/src/esp32/rom/esp32_gpio.h | 2 +- 4 files changed, 442 insertions(+), 3 deletions(-) create mode 100644 arch/xtensa/src/esp32/chip/esp32_gpio_sigmap.h diff --git a/arch/xtensa/src/esp32/chip/esp32_dport.h b/arch/xtensa/src/esp32/chip/esp32_dport.h index 202e4824c3..6175b29f0d 100644 --- a/arch/xtensa/src/esp32/chip/esp32_dport.h +++ b/arch/xtensa/src/esp32/chip/esp32_dport.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/common/esp32_dport.h + * arch/xtensa/src/esp32/chip/esp32_dport.h * * Adapted from use in NuttX by: * diff --git a/arch/xtensa/src/esp32/chip/esp32_gpio_sigmap.h b/arch/xtensa/src/esp32/chip/esp32_gpio_sigmap.h new file mode 100644 index 0000000000..f6a6ce7ba8 --- /dev/null +++ b/arch/xtensa/src/esp32/chip/esp32_gpio_sigmap.h @@ -0,0 +1,439 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/chip/esp32_gpio_sigmap.h + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Espressif Systems: + * + * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_GPIO_SIGMAP_H +#define __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_GPIO_SIGMAP_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SPICLK_IN_IDX 0 +#define SPICLK_OUT_IDX 0 +#define SPIQ_IN_IDX 1 +#define SPIQ_OUT_IDX 1 +#define SPID_IN_IDX 2 +#define SPID_OUT_IDX 2 +#define SPIHD_IN_IDX 3 +#define SPIHD_OUT_IDX 3 +#define SPIWP_IN_IDX 4 +#define SPIWP_OUT_IDX 4 +#define SPICS0_IN_IDX 5 +#define SPICS0_OUT_IDX 5 +#define SPICS1_IN_IDX 6 +#define SPICS1_OUT_IDX 6 +#define SPICS2_IN_IDX 7 +#define SPICS2_OUT_IDX 7 +#define HSPICLK_IN_IDX 8 +#define HSPICLK_OUT_IDX 8 +#define HSPIQ_IN_IDX 9 +#define HSPIQ_OUT_IDX 9 +#define HSPID_IN_IDX 10 +#define HSPID_OUT_IDX 10 +#define HSPICS0_IN_IDX 11 +#define HSPICS0_OUT_IDX 11 +#define HSPIHD_IN_IDX 12 +#define HSPIHD_OUT_IDX 12 +#define HSPIWP_IN_IDX 13 +#define HSPIWP_OUT_IDX 13 +#define U0RXD_IN_IDX 14 +#define U0TXD_OUT_IDX 14 +#define U0CTS_IN_IDX 15 +#define U0RTS_OUT_IDX 15 +#define U0DSR_IN_IDX 16 +#define U0DTR_OUT_IDX 16 +#define U1RXD_IN_IDX 17 +#define U1TXD_OUT_IDX 17 +#define U1CTS_IN_IDX 18 +#define U1RTS_OUT_IDX 18 +#define I2CM_SCL_O_IDX 19 +#define I2CM_SDA_I_IDX 20 +#define I2CM_SDA_O_IDX 20 +#define EXT_I2C_SCL_O_IDX 21 +#define EXT_I2C_SDA_O_IDX 22 +#define EXT_I2C_SDA_I_IDX 22 +#define I2S0O_BCK_IN_IDX 23 +#define I2S0O_BCK_OUT_IDX 23 +#define I2S1O_BCK_IN_IDX 24 +#define I2S1O_BCK_OUT_IDX 24 +#define I2S0O_WS_IN_IDX 25 +#define I2S0O_WS_OUT_IDX 25 +#define I2S1O_WS_IN_IDX 26 +#define I2S1O_WS_OUT_IDX 26 +#define I2S0I_BCK_IN_IDX 27 +#define I2S0I_BCK_OUT_IDX 27 +#define I2S0I_WS_IN_IDX 28 +#define I2S0I_WS_OUT_IDX 28 +#define I2CEXT0_SCL_IN_IDX 29 +#define I2CEXT0_SCL_OUT_IDX 29 +#define I2CEXT0_SDA_IN_IDX 30 +#define I2CEXT0_SDA_OUT_IDX 30 +#define PWM0_SYNC0_IN_IDX 31 +#define SDIO_TOHOST_INT_OUT_IDX 31 +#define PWM0_SYNC1_IN_IDX 32 +#define PWM0_OUT0A_IDX 32 +#define PWM0_SYNC2_IN_IDX 33 +#define PWM0_OUT0B_IDX 33 +#define PWM0_F0_IN_IDX 34 +#define PWM0_OUT1A_IDX 34 +#define PWM0_F1_IN_IDX 35 +#define PWM0_OUT1B_IDX 35 +#define PWM0_F2_IN_IDX 36 +#define PWM0_OUT2A_IDX 36 +#define GPIO_BT_ACTIVE_IDX 37 +#define PWM0_OUT2B_IDX 37 +#define GPIO_BT_PRIORITY_IDX 38 +#define PCNT_SIG_CH0_IN0_IDX 39 +#define PCNT_SIG_CH1_IN0_IDX 40 +#define GPIO_WLAN_ACTIVE_IDX 40 +#define PCNT_CTRL_CH0_IN0_IDX 41 +#define BB_DIAG0_IDX 41 +#define PCNT_CTRL_CH1_IN0_IDX 42 +#define BB_DIAG1_IDX 42 +#define PCNT_SIG_CH0_IN1_IDX 43 +#define BB_DIAG2_IDX 43 +#define PCNT_SIG_CH1_IN1_IDX 44 +#define BB_DIAG3_IDX 44 +#define PCNT_CTRL_CH0_IN1_IDX 45 +#define BB_DIAG4_IDX 45 +#define PCNT_CTRL_CH1_IN1_IDX 46 +#define BB_DIAG5_IDX 46 +#define PCNT_SIG_CH0_IN2_IDX 47 +#define BB_DIAG6_IDX 47 +#define PCNT_SIG_CH1_IN2_IDX 48 +#define BB_DIAG7_IDX 48 +#define PCNT_CTRL_CH0_IN2_IDX 49 +#define BB_DIAG8_IDX 49 +#define PCNT_CTRL_CH1_IN2_IDX 50 +#define BB_DIAG9_IDX 50 +#define PCNT_SIG_CH0_IN3_IDX 51 +#define BB_DIAG10_IDX 51 +#define PCNT_SIG_CH1_IN3_IDX 52 +#define BB_DIAG11_IDX 52 +#define PCNT_CTRL_CH0_IN3_IDX 53 +#define BB_DIAG12_IDX 53 +#define PCNT_CTRL_CH1_IN3_IDX 54 +#define BB_DIAG13_IDX 54 +#define PCNT_SIG_CH0_IN4_IDX 55 +#define BB_DIAG14_IDX 55 +#define PCNT_SIG_CH1_IN4_IDX 56 +#define BB_DIAG15_IDX 56 +#define PCNT_CTRL_CH0_IN4_IDX 57 +#define BB_DIAG16_IDX 57 +#define PCNT_CTRL_CH1_IN4_IDX 58 +#define BB_DIAG17_IDX 58 +#define BB_DIAG18_IDX 59 +#define BB_DIAG19_IDX 60 +#define HSPICS1_IN_IDX 61 +#define HSPICS1_OUT_IDX 61 +#define HSPICS2_IN_IDX 62 +#define HSPICS2_OUT_IDX 62 +#define VSPICLK_IN_IDX 63 +#define VSPICLK_OUT_MUX_IDX 63 +#define VSPIQ_IN_IDX 64 +#define VSPIQ_OUT_IDX 64 +#define VSPID_IN_IDX 65 +#define VSPID_OUT_IDX 65 +#define VSPIHD_IN_IDX 66 +#define VSPIHD_OUT_IDX 66 +#define VSPIWP_IN_IDX 67 +#define VSPIWP_OUT_IDX 67 +#define VSPICS0_IN_IDX 68 +#define VSPICS0_OUT_IDX 68 +#define VSPICS1_IN_IDX 69 +#define VSPICS1_OUT_IDX 69 +#define VSPICS2_IN_IDX 70 +#define VSPICS2_OUT_IDX 70 +#define PCNT_SIG_CH0_IN5_IDX 71 +#define LEDC_HS_SIG_OUT0_IDX 71 +#define PCNT_SIG_CH1_IN5_IDX 72 +#define LEDC_HS_SIG_OUT1_IDX 72 +#define PCNT_CTRL_CH0_IN5_IDX 73 +#define LEDC_HS_SIG_OUT2_IDX 73 +#define PCNT_CTRL_CH1_IN5_IDX 74 +#define LEDC_HS_SIG_OUT3_IDX 74 +#define PCNT_SIG_CH0_IN6_IDX 75 +#define LEDC_HS_SIG_OUT4_IDX 75 +#define PCNT_SIG_CH1_IN6_IDX 76 +#define LEDC_HS_SIG_OUT5_IDX 76 +#define PCNT_CTRL_CH0_IN6_IDX 77 +#define LEDC_HS_SIG_OUT6_IDX 77 +#define PCNT_CTRL_CH1_IN6_IDX 78 +#define LEDC_HS_SIG_OUT7_IDX 78 +#define PCNT_SIG_CH0_IN7_IDX 79 +#define LEDC_LS_SIG_OUT0_IDX 79 +#define PCNT_SIG_CH1_IN7_IDX 80 +#define LEDC_LS_SIG_OUT1_IDX 80 +#define PCNT_CTRL_CH0_IN7_IDX 81 +#define LEDC_LS_SIG_OUT2_IDX 81 +#define PCNT_CTRL_CH1_IN7_IDX 82 +#define LEDC_LS_SIG_OUT3_IDX 82 +#define RMT_SIG_IN0_IDX 83 +#define LEDC_LS_SIG_OUT4_IDX 83 +#define RMT_SIG_IN1_IDX 84 +#define LEDC_LS_SIG_OUT5_IDX 84 +#define RMT_SIG_IN2_IDX 85 +#define LEDC_LS_SIG_OUT6_IDX 85 +#define RMT_SIG_IN3_IDX 86 +#define LEDC_LS_SIG_OUT7_IDX 86 +#define RMT_SIG_IN4_IDX 87 +#define RMT_SIG_OUT0_IDX 87 +#define RMT_SIG_IN5_IDX 88 +#define RMT_SIG_OUT1_IDX 88 +#define RMT_SIG_IN6_IDX 89 +#define RMT_SIG_OUT2_IDX 89 +#define RMT_SIG_IN7_IDX 90 +#define RMT_SIG_OUT3_IDX 90 +#define RMT_SIG_OUT4_IDX 91 +#define RMT_SIG_OUT5_IDX 92 +#define EXT_ADC_START_IDX 93 +#define RMT_SIG_OUT6_IDX 93 +#define CAN_RX_IDX 94 +#define RMT_SIG_OUT7_IDX 94 +#define I2CEXT1_SCL_IN_IDX 95 +#define I2CEXT1_SCL_OUT_IDX 95 +#define I2CEXT1_SDA_IN_IDX 96 +#define I2CEXT1_SDA_OUT_IDX 96 +#define HOST_CARD_DETECT_N_1_IDX 97 +#define HOST_CCMD_OD_PULLUP_EN_N_IDX 97 +#define HOST_CARD_DETECT_N_2_IDX 98 +#define HOST_RST_N_1_IDX 98 +#define HOST_CARD_WRITE_PRT_1_IDX 99 +#define HOST_RST_N_2_IDX 99 +#define HOST_CARD_WRITE_PRT_2_IDX 100 +#define GPIO_SD0_OUT_IDX 100 +#define HOST_CARD_INT_N_1_IDX 101 +#define GPIO_SD1_OUT_IDX 101 +#define HOST_CARD_INT_N_2_IDX 102 +#define GPIO_SD2_OUT_IDX 102 +#define PWM1_SYNC0_IN_IDX 103 +#define GPIO_SD3_OUT_IDX 103 +#define PWM1_SYNC1_IN_IDX 104 +#define GPIO_SD4_OUT_IDX 104 +#define PWM1_SYNC2_IN_IDX 105 +#define GPIO_SD5_OUT_IDX 105 +#define PWM1_F0_IN_IDX 106 +#define GPIO_SD6_OUT_IDX 106 +#define PWM1_F1_IN_IDX 107 +#define GPIO_SD7_OUT_IDX 107 +#define PWM1_F2_IN_IDX 108 +#define PWM1_OUT0A_IDX 108 +#define PWM0_CAP0_IN_IDX 109 +#define PWM1_OUT0B_IDX 109 +#define PWM0_CAP1_IN_IDX 110 +#define PWM1_OUT1A_IDX 110 +#define PWM0_CAP2_IN_IDX 111 +#define PWM1_OUT1B_IDX 111 +#define PWM1_CAP0_IN_IDX 112 +#define PWM1_OUT2A_IDX 112 +#define PWM1_CAP1_IN_IDX 113 +#define PWM1_OUT2B_IDX 113 +#define PWM1_CAP2_IN_IDX 114 +#define PWM2_OUT1H_IDX 114 +#define PWM2_FLTA_IDX 115 +#define PWM2_OUT1L_IDX 115 +#define PWM2_FLTB_IDX 116 +#define PWM2_OUT2H_IDX 116 +#define PWM2_CAP1_IN_IDX 117 +#define PWM2_OUT2L_IDX 117 +#define PWM2_CAP2_IN_IDX 118 +#define PWM2_OUT3H_IDX 118 +#define PWM2_CAP3_IN_IDX 119 +#define PWM2_OUT3L_IDX 119 +#define PWM3_FLTA_IDX 120 +#define PWM2_OUT4H_IDX 120 +#define PWM3_FLTB_IDX 121 +#define PWM2_OUT4L_IDX 121 +#define PWM3_CAP1_IN_IDX 122 +#define PWM3_CAP2_IN_IDX 123 +#define CAN_TX_IDX 123 +#define PWM3_CAP3_IN_IDX 124 +#define CAN_BUS_OFF_ON_IDX 124 +#define CAN_CLKOUT_IDX 125 +#define SPID4_IN_IDX 128 +#define SPID4_OUT_IDX 128 +#define SPID5_IN_IDX 129 +#define SPID5_OUT_IDX 129 +#define SPID6_IN_IDX 130 +#define SPID6_OUT_IDX 130 +#define SPID7_IN_IDX 131 +#define SPID7_OUT_IDX 131 +#define HSPID4_IN_IDX 132 +#define HSPID4_OUT_IDX 132 +#define HSPID5_IN_IDX 133 +#define HSPID5_OUT_IDX 133 +#define HSPID6_IN_IDX 134 +#define HSPID6_OUT_IDX 134 +#define HSPID7_IN_IDX 135 +#define HSPID7_OUT_IDX 135 +#define VSPID4_IN_IDX 136 +#define VSPID4_OUT_IDX 136 +#define VSPID5_IN_IDX 137 +#define VSPID5_OUT_IDX 137 +#define VSPID6_IN_IDX 138 +#define VSPID6_OUT_IDX 138 +#define VSPID7_IN_IDX 139 +#define VSPID7_OUT_IDX 139 +#define I2S0I_DATA_IN0_IDX 140 +#define I2S0O_DATA_OUT0_IDX 140 +#define I2S0I_DATA_IN1_IDX 141 +#define I2S0O_DATA_OUT1_IDX 141 +#define I2S0I_DATA_IN2_IDX 142 +#define I2S0O_DATA_OUT2_IDX 142 +#define I2S0I_DATA_IN3_IDX 143 +#define I2S0O_DATA_OUT3_IDX 143 +#define I2S0I_DATA_IN4_IDX 144 +#define I2S0O_DATA_OUT4_IDX 144 +#define I2S0I_DATA_IN5_IDX 145 +#define I2S0O_DATA_OUT5_IDX 145 +#define I2S0I_DATA_IN6_IDX 146 +#define I2S0O_DATA_OUT6_IDX 146 +#define I2S0I_DATA_IN7_IDX 147 +#define I2S0O_DATA_OUT7_IDX 147 +#define I2S0I_DATA_IN8_IDX 148 +#define I2S0O_DATA_OUT8_IDX 148 +#define I2S0I_DATA_IN9_IDX 149 +#define I2S0O_DATA_OUT9_IDX 149 +#define I2S0I_DATA_IN10_IDX 150 +#define I2S0O_DATA_OUT10_IDX 150 +#define I2S0I_DATA_IN11_IDX 151 +#define I2S0O_DATA_OUT11_IDX 151 +#define I2S0I_DATA_IN12_IDX 152 +#define I2S0O_DATA_OUT12_IDX 152 +#define I2S0I_DATA_IN13_IDX 153 +#define I2S0O_DATA_OUT13_IDX 153 +#define I2S0I_DATA_IN14_IDX 154 +#define I2S0O_DATA_OUT14_IDX 154 +#define I2S0I_DATA_IN15_IDX 155 +#define I2S0O_DATA_OUT15_IDX 155 +#define I2S0O_DATA_OUT16_IDX 156 +#define I2S0O_DATA_OUT17_IDX 157 +#define I2S0O_DATA_OUT18_IDX 158 +#define I2S0O_DATA_OUT19_IDX 159 +#define I2S0O_DATA_OUT20_IDX 160 +#define I2S0O_DATA_OUT21_IDX 161 +#define I2S0O_DATA_OUT22_IDX 162 +#define I2S0O_DATA_OUT23_IDX 163 +#define I2S1I_BCK_IN_IDX 164 +#define I2S1I_BCK_OUT_IDX 164 +#define I2S1I_WS_IN_IDX 165 +#define I2S1I_WS_OUT_IDX 165 +#define I2S1I_DATA_IN0_IDX 166 +#define I2S1O_DATA_OUT0_IDX 166 +#define I2S1I_DATA_IN1_IDX 167 +#define I2S1O_DATA_OUT1_IDX 167 +#define I2S1I_DATA_IN2_IDX 168 +#define I2S1O_DATA_OUT2_IDX 168 +#define I2S1I_DATA_IN3_IDX 169 +#define I2S1O_DATA_OUT3_IDX 169 +#define I2S1I_DATA_IN4_IDX 170 +#define I2S1O_DATA_OUT4_IDX 170 +#define I2S1I_DATA_IN5_IDX 171 +#define I2S1O_DATA_OUT5_IDX 171 +#define I2S1I_DATA_IN6_IDX 172 +#define I2S1O_DATA_OUT6_IDX 172 +#define I2S1I_DATA_IN7_IDX 173 +#define I2S1O_DATA_OUT7_IDX 173 +#define I2S1I_DATA_IN8_IDX 174 +#define I2S1O_DATA_OUT8_IDX 174 +#define I2S1I_DATA_IN9_IDX 175 +#define I2S1O_DATA_OUT9_IDX 175 +#define I2S1I_DATA_IN10_IDX 176 +#define I2S1O_DATA_OUT10_IDX 176 +#define I2S1I_DATA_IN11_IDX 177 +#define I2S1O_DATA_OUT11_IDX 177 +#define I2S1I_DATA_IN12_IDX 178 +#define I2S1O_DATA_OUT12_IDX 178 +#define I2S1I_DATA_IN13_IDX 179 +#define I2S1O_DATA_OUT13_IDX 179 +#define I2S1I_DATA_IN14_IDX 180 +#define I2S1O_DATA_OUT14_IDX 180 +#define I2S1I_DATA_IN15_IDX 181 +#define I2S1O_DATA_OUT15_IDX 181 +#define I2S1O_DATA_OUT16_IDX 182 +#define I2S1O_DATA_OUT17_IDX 183 +#define I2S1O_DATA_OUT18_IDX 184 +#define I2S1O_DATA_OUT19_IDX 185 +#define I2S1O_DATA_OUT20_IDX 186 +#define I2S1O_DATA_OUT21_IDX 187 +#define I2S1O_DATA_OUT22_IDX 188 +#define I2S1O_DATA_OUT23_IDX 189 +#define I2S0I_H_SYNC_IDX 190 +#define PWM3_OUT1H_IDX 190 +#define I2S0I_V_SYNC_IDX 191 +#define PWM3_OUT1L_IDX 191 +#define I2S0I_H_ENABLE_IDX 192 +#define PWM3_OUT2H_IDX 192 +#define I2S1I_H_SYNC_IDX 193 +#define PWM3_OUT2L_IDX 193 +#define I2S1I_V_SYNC_IDX 194 +#define PWM3_OUT3H_IDX 194 +#define I2S1I_H_ENABLE_IDX 195 +#define PWM3_OUT3L_IDX 195 +#define PWM3_OUT4H_IDX 196 +#define PWM3_OUT4L_IDX 197 +#define U2RXD_IN_IDX 198 +#define U2TXD_OUT_IDX 198 +#define U2CTS_IN_IDX 199 +#define U2RTS_OUT_IDX 199 +#define EMAC_MDC_I_IDX 200 +#define EMAC_MDC_O_IDX 200 +#define EMAC_MDI_I_IDX 201 +#define EMAC_MDO_O_IDX 201 +#define EMAC_CRS_I_IDX 202 +#define EMAC_CRS_O_IDX 202 +#define EMAC_COL_I_IDX 203 +#define EMAC_COL_O_IDX 203 +#define PCMFSYNC_IN_IDX 204 +#define BT_AUDIO0_IRQ_IDX 204 +#define PCMCLK_IN_IDX 205 +#define BT_AUDIO1_IRQ_IDX 205 +#define PCMDIN_IDX 206 +#define BT_AUDIO2_IRQ_IDX 206 +#define BLE_AUDIO0_IRQ_IDX 207 +#define BLE_AUDIO1_IRQ_IDX 208 +#define BLE_AUDIO2_IRQ_IDX 209 +#define PCMFSYNC_OUT_IDX 210 +#define PCMCLK_OUT_IDX 211 +#define PCMDOUT_IDX 212 +#define BLE_AUDIO_SYNC0_P_IDX 213 +#define BLE_AUDIO_SYNC1_P_IDX 214 +#define BLE_AUDIO_SYNC2_P_IDX 215 +#define ANT_SEL0_IDX 216 +#define ANT_SEL1_IDX 217 +#define ANT_SEL2_IDX 218 +#define ANT_SEL3_IDX 219 +#define ANT_SEL4_IDX 220 +#define ANT_SEL5_IDX 221 +#define ANT_SEL6_IDX 222 +#define ANT_SEL7_IDX 223 +#define SIG_IN_FUNC224_IDX 224 +#define SIG_IN_FUNC225_IDX 225 +#define SIG_IN_FUNC226_IDX 226 +#define SIG_IN_FUNC227_IDX 227 +#define SIG_IN_FUNC228_IDX 228 + +#endif /* __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_GPIO_SIGMAP_H */ diff --git a/arch/xtensa/src/esp32/chip/esp32_rtccntl.h b/arch/xtensa/src/esp32/chip/esp32_rtccntl.h index 12f5ba07a9..23a0102234 100644 --- a/arch/xtensa/src/esp32/chip/esp32_rtccntl.h +++ b/arch/xtensa/src/esp32/chip/esp32_rtccntl.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/common/esp32_rtccnt.h + * arch/xtensa/src/esp32/chip/esp32_rtccnt.h * * Adapted from use in NuttX by: * diff --git a/arch/xtensa/src/esp32/rom/esp32_gpio.h b/arch/xtensa/src/esp32/rom/esp32_gpio.h index 8e426e0cb7..a6089d33b7 100644 --- a/arch/xtensa/src/esp32/rom/esp32_gpio.h +++ b/arch/xtensa/src/esp32/rom/esp32_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/esp32/esp32_gpio.c + * arch/xtensa/src/esp32/rom/esp32_gpio.h * * Developed for NuttX by: * -- GitLab From 6f7c03bd71314a84f113e05cf83e39f205fda8c8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 27 Oct 2016 13:55:58 -0600 Subject: [PATCH 233/734] ESP32: Add initial serial driver. Taken from SAMV7; not fully converted. Does not yet compile. --- arch/xtensa/src/esp32/chip/esp32_uart.h | 82 +- arch/xtensa/src/esp32/esp32_gpio.c | 10 +- arch/xtensa/src/esp32/esp32_gpio.h | 58 +- arch/xtensa/src/esp32/esp32_serial.c | 1212 +++++++++++++++++++++++ arch/xtensa/src/esp32/rom/esp32_gpio.h | 8 + 5 files changed, 1323 insertions(+), 47 deletions(-) create mode 100644 arch/xtensa/src/esp32/esp32_serial.c diff --git a/arch/xtensa/src/esp32/chip/esp32_uart.h b/arch/xtensa/src/esp32/chip/esp32_uart.h index f13a5c234c..8e86e436b3 100644 --- a/arch/xtensa/src/esp32/chip/esp32_uart.h +++ b/arch/xtensa/src/esp32/chip/esp32_uart.h @@ -39,7 +39,8 @@ #define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000 + (i > 1 ? 0xe000 : 0)) -#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) +#define UART_FIFO_OFFSET 0x00 +#define UART_FIFO_REG(i) (REG_UART_BASE(i) + UART_FIFO_OFFSET) /* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */ /* Description: This register stores one byte data read by rx fifo.*/ @@ -49,7 +50,8 @@ #define UART_RXFIFO_RD_BYTE_V 0xFF #define UART_RXFIFO_RD_BYTE_S 0 -#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) +#define UART_INT_RAW_OFFSET 0x04 +#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + UART_INT_RAW_OFFSET) /* UART_AT_CMD_CHAR_DET_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ /* Description: This interrupt raw bit turns to high level when receiver @@ -241,7 +243,8 @@ #define UART_RXFIFO_FULL_INT_RAW_V 0x1 #define UART_RXFIFO_FULL_INT_RAW_S 0 -#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) +#define UART_INT_ST_OFFSET 0x08 +#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + UART_INT_ST_OFFSET) /* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ /* Description: This is the status bit for at_cmd_det_int_raw when @@ -432,7 +435,8 @@ #define UART_RXFIFO_FULL_INT_ST_V 0x1 #define UART_RXFIFO_FULL_INT_ST_S 0 -#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xC) +#define UART_INT_ENA_OFFSET 0x0c +#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + UART_INT_ENA_OFFSET) /* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ /* Description: This is the enable bit for at_cmd_char_det_int_st register.*/ @@ -586,7 +590,8 @@ #define UART_RXFIFO_FULL_INT_ENA_V 0x1 #define UART_RXFIFO_FULL_INT_ENA_S 0 -#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) +#define UART_INT_CLR_OFFSET 0x10 +#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + UART_INT_CLR_OFFSET) /* UART_AT_CMD_CHAR_DET_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ /* Description: Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ @@ -744,7 +749,8 @@ #define UART_RXFIFO_FULL_INT_CLR_V 0x1 #define UART_RXFIFO_FULL_INT_CLR_S 0 -#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14) +#define UART_CLKDIV_OFFSET 0x14 +#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + UART_CLKDIV_OFFSET) /* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ /* Description: The register value is the decimal part of the frequency @@ -766,7 +772,8 @@ #define UART_CLKDIV_V 0xFFFFF #define UART_CLKDIV_S 0 -#define UART_AUTOBAUD_REG(i) (REG_UART_BASE(i) + 0x18) +#define UART_AUTOBAUD_OFFSET 0x18 +#define UART_AUTOBAUD_REG(i) (REG_UART_BASE(i) + UART_AUTOBAUD_OFFSET) /* UART_GLITCH_FILT : R/W ;bitpos:[15:8] ;default: 8'h10 ; */ /* Description: when input pulse width is lower then this value igore this @@ -786,7 +793,8 @@ #define UART_AUTOBAUD_EN_V 0x1 #define UART_AUTOBAUD_EN_S 0 -#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1C) +#define UART_STATUS_OFFSET 0x1c +#define UART_STATUS_REG(i) (REG_UART_BASE(i) + UART_STATUS_OFFSET) /* UART_TXD : RO ;bitpos:[31] ;default: 8'h0 ; */ /* Description: This register represent the level value of the internal @@ -895,7 +903,8 @@ #define UART_RXFIFO_CNT_V 0xFF #define UART_RXFIFO_CNT_S 0 -#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20) +#define UART_CONF0_OFFSET 0x20 +#define UART_CONF0_REG(i) (REG_UART_BASE(i) + UART_CONF0_OFFSET) /* UART_TICK_REF_ALWAYS_ON : R/W ;bitpos:[27] ;default: 1'b1 ; */ /* Description: This register is used to select the clock.1.apb clock @@ -1127,7 +1136,8 @@ #define UART_PARITY_V 0x1 #define UART_PARITY_S 0 -#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) +#define UART_CONF1_OFFSET 0x24 +#define UART_CONF1_REG(i) (REG_UART_BASE(i) + UART_CONF1_OFFSET) /* UART_RX_TOUT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ /* Description: This is the enble bit for uart receiver's timeout function.*/ @@ -1190,7 +1200,8 @@ #define UART_RXFIFO_FULL_THRHD_V 0x7F #define UART_RXFIFO_FULL_THRHD_S 0 -#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28) +#define UART_LOWPULSE_OFFSET 0x28 +#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + UART_LOWPULSE_OFFSET) /* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ /* Description: This register stores the value of the minimum duration time @@ -1202,7 +1213,8 @@ #define UART_LOWPULSE_MIN_CNT_V 0xFFFFF #define UART_LOWPULSE_MIN_CNT_S 0 -#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C) +#define UART_HIGHPULSE_OFFSET 0x2c +#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + UART_HIGHPULSE_OFFSET) /* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ /* Description: This register stores the value of the maxinum duration time @@ -1214,7 +1226,8 @@ #define UART_HIGHPULSE_MIN_CNT_V 0xFFFFF #define UART_HIGHPULSE_MIN_CNT_S 0 -#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30) +#define UART_RXD_CNT_OFFSET 0x30 +#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + UART_RXD_CNT_OFFSET) /* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */ /* Description: This register stores the count of rxd edge change. it is @@ -1226,7 +1239,8 @@ #define UART_RXD_EDGE_CNT_V 0x3FF #define UART_RXD_EDGE_CNT_S 0 -#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34) +#define UART_FLOW_CONF_OFFSET 0x34 +#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + UART_FLOW_CONF_OFFSET) /* UART_SEND_XOFF : R/W ;bitpos:[5] ;default: 1'b0 ; */ /* Description: Set this bit to send xoff char. it is cleared by hardware @@ -1288,7 +1302,8 @@ #define UART_SW_FLOW_CON_EN_V 0x1 #define UART_SW_FLOW_CON_EN_S 0 -#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38) +#define UART_SLEEP_CONF_OFFSET 0x38 +#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + UART_SLEEP_CONF_OFFSET) /* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */ /* Description: When the input rxd edge changes more than this register @@ -1300,7 +1315,8 @@ #define UART_ACTIVE_THRESHOLD_V 0x3FF #define UART_ACTIVE_THRESHOLD_S 0 -#define UART_SWFC_CONF_REG(i) (REG_UART_BASE(i) + 0x3C) +#define UART_SWFC_CONF_OFFSET 0x3c +#define UART_SWFC_CONF_REG(i) (REG_UART_BASE(i) + UART_SWFC_CONF_OFFSET) /* UART_XOFF_CHAR : R/W ;bitpos:[31:24] ;default: 8'h13 ; */ /* Description: This register stores the xoff flow control char.*/ @@ -1340,7 +1356,8 @@ #define UART_XON_THRESHOLD_V 0xFF #define UART_XON_THRESHOLD_S 0 -#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x40) +#define UART_IDLE_CONF_OFFSET 0x40 +#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + UART_IDLE_CONF_OFFSET) /* UART_TX_BRK_NUM : R/W ;bitpos:[27:20] ;default: 8'ha ; */ /* Description: This register is used to configure the num of 0 send after @@ -1374,7 +1391,8 @@ #define UART_RX_IDLE_THRHD_V 0x3FF #define UART_RX_IDLE_THRHD_S 0 -#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x44) +#define UART_RS485_CONF_OFFSET 0x44 +#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + UART_RS485_CONF_OFFSET) /* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */ /* Description: This register is used to delay the transmitter's internal @@ -1441,6 +1459,7 @@ #define UART_RS485_EN_V 0x1 #define UART_RS485_EN_S 0 +#define UART_AT_CMD_PRECNT_OFFSET 0x48 #define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x48) /* UART_PRE_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */ @@ -1455,7 +1474,8 @@ #define UART_PRE_IDLE_NUM_V 0xFFFFFF #define UART_PRE_IDLE_NUM_S 0 -#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x4c) +#define UART_AT_CMD_POSTCNT_OFFSET 0x4c +#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + UART_AT_CMD_POSTCNT_OFFSET) /* UART_POST_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */ /* Description: This register is used to configure the duration time between @@ -1468,6 +1488,7 @@ #define UART_POST_IDLE_NUM_V 0xFFFFFF #define UART_POST_IDLE_NUM_S 0 +#define UART_AT_CMD_GAPTOUT_OFFSET 0x50 #define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x50) /* UART_RX_GAP_TOUT : R/W ;bitpos:[23:0] ;default: 24'h1e00 ; */ @@ -1481,7 +1502,8 @@ #define UART_RX_GAP_TOUT_V 0xFFFFFF #define UART_RX_GAP_TOUT_S 0 -#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x54) +#define UART_AT_CMD_CHAR_OFFSET 0x54 +#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + UART_AT_CMD_CHAR_OFFSET) /* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */ /* Description: This register is used to configure the num of continous @@ -1503,7 +1525,8 @@ #define UART_AT_CMD_CHAR_V 0xFF #define UART_AT_CMD_CHAR_S 0 -#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x58) +#define UART_MEM_CONF_OFFSET 0x58 +#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + UART_MEM_CONF_OFFSET) /* UART_TX_MEM_EMPTY_THRHD : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ /* Description: refer to txfifo_empty_thrhd 's describtion.*/ @@ -1583,7 +1606,8 @@ #define UART_MEM_PD_V 0x1 #define UART_MEM_PD_S 0 -#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x5c) +#define UART_MEM_TX_STATUS_OFFSET 0x5c +#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + UART_MEM_TX_STATUS_OFFSET) /* UART_MEM_TX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */ /* Description: */ @@ -1593,7 +1617,8 @@ #define UART_MEM_TX_STATUS_V 0xFFFFFF #define UART_MEM_TX_STATUS_S 0 -#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x60) +#define UART_MEM_RX_STATUS_OFFSET 0x60 +#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + UART_MEM_RX_STATUS_OFFSET) /* UART_MEM_RX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */ /* Description: */ @@ -1603,7 +1628,8 @@ #define UART_MEM_RX_STATUS_V 0xFFFFFF #define UART_MEM_RX_STATUS_S 0 -#define UART_MEM_CNT_STATUS_REG(i) (REG_UART_BASE(i) + 0x64) +#define UART_MEM_CNT_STATUS_OFFSET 0x64 +#define UART_MEM_CNT_STATUS_REG(i) (REG_UART_BASE(i) + UART_MEM_CNT_STATUS_OFFSET) /* UART_TX_MEM_CNT : RO ;bitpos:[5:3] ;default: 3'b0 ; */ /* Description: refer to the txfifo_cnt's describtion.*/ @@ -1621,6 +1647,7 @@ #define UART_RX_MEM_CNT_V 0x7 #define UART_RX_MEM_CNT_S 0 +#define UART_POSPULSE_OFFSET 0x68 #define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x68) /* UART_POSEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ @@ -1633,7 +1660,8 @@ #define UART_POSEDGE_MIN_CNT_V 0xFFFFF #define UART_POSEDGE_MIN_CNT_S 0 -#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x6c) +#define UART_NEGPULSE_OFFSET 0x6c +#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + UART_NEGPULSE_OFFSET) /* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ /* Description: This register stores the count of rxd negedge edge. it is @@ -1645,6 +1673,7 @@ #define UART_NEGEDGE_MIN_CNT_V 0xFFFFF #define UART_NEGEDGE_MIN_CNT_S 0 +#define UART_DATE_OFFSET 0x78 #define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x78) /* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h15122500 ; */ @@ -1655,7 +1684,8 @@ #define UART_DATE_V 0xFFFFFFFF #define UART_DATE_S 0 -#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x7C) +#define UART_ID_OFFSET 0x7c +#define UART_ID_REG(i) (REG_UART_BASE(i) + UART_ID_OFFSET) /* UART_ID : R/W ;bitpos:[31:0] ;default: 32'h0500 ; */ /* Description: */ diff --git a/arch/xtensa/src/esp32/esp32_gpio.c b/arch/xtensa/src/esp32/esp32_gpio.c index c40b6b097a..6b5bd108f1 100644 --- a/arch/xtensa/src/esp32/esp32_gpio.c +++ b/arch/xtensa/src/esp32/esp32_gpio.c @@ -161,6 +161,7 @@ int esp32_configgpio(int pin, gpio_pinattr_t attr) uintptr_t regaddr; uint32_t func; uint32_t cntrl; + unsigned int pinmode; DEBUGASSERT(pin >=0 && pin <= ESP32_NIRQ_GPIO); @@ -212,17 +213,18 @@ int esp32_configgpio(int pin, gpio_pinattr_t attr) func |= FUN_IE; - if ((attr & (INPUT | OUTPUT)) != 0) + pinmode = (attr & PINMODE_MASK); + if (pinmode == INPUT | pinmode == OUTPUT) { func |= (uint32_t)(2 << MCU_SEL_S); } - else if (attr == SPECIAL) + else if ((attr & FUNCTION_MASK) == SPECIAL) { func |= (uint32_t)((((pin) == 1 || (pin) == 3) ? 0 : 1) << MCU_SEL_S); } - else + else /* if ((attr & FUNCTION) != 0) */ { - func |= (uint32_t)((attr >> 5) << MCU_SEL_S); + func |= (uint32_t)((attr >> FUNCTION_SHIFT) << MCU_SEL_S); } if ((attr & OPEN_DRAIN) != 0) diff --git a/arch/xtensa/src/esp32/esp32_gpio.h b/arch/xtensa/src/esp32/esp32_gpio.h index f765917d43..ea09df2439 100644 --- a/arch/xtensa/src/esp32/esp32_gpio.h +++ b/arch/xtensa/src/esp32/esp32_gpio.h @@ -42,22 +42,46 @@ /* Bit-encoded input to esp32_configgpio() **********************************/ -/* Encoded pin attributes used with esp32_configgpio() */ - -#define INPUT 0x01 -#define OUTPUT 0x02 -#define PULLUP 0x04 -#define INPUT_PULLUP 0x05 -#define PULLDOWN 0x08 -#define INPUT_PULLDOWN 0x09 -#define OPEN_DRAIN 0x10 -#define OUTPUT_OPEN_DRAIN 0x12 -#define SPECIAL 0xf0 -#define FUNCTION_0 0x00 -#define FUNCTION_1 0x20 -#define FUNCTION_2 0x40 -#define FUNCTION_3 0x70 -#define FUNCTION_4 0x80 +/* Encoded pin attributes used with esp32_configgpio() + * + * 8 7 6 5 4 3 2 1 0 + * -- -- -- -- -- -- -- -- -- + * FN FN FN OD PD PU F O I + */ + +#define PINMODE_SHIFT 0 +#define PINMODE_MASK (7 << PINMODE_SHIFT) +# define INPUT (1 << 0) +# define OUTPUT (1 << 1) +# define FUNCTION (1 << 2) + +#define PULLUP (1 << 3) +#define PULLDOWN (1 << 4) +#define OPEN_DRAIN (1 << 5) +#define FUNCTION_SHIFT 6 +#define FUNCTION_MASK (7 << FUNCTION_SHIFT) +# define FUNCTION_0 (0 << FUNCTION_SHIFT) +# define FUNCTION_1 (1 << FUNCTION_SHIFT) +# define FUNCTION_2 (2 << FUNCTION_SHIFT) +# define FUNCTION_3 (3 << FUNCTION_SHIFT) +# define FUNCTION_4 (4 << FUNCTION_SHIFT) +# define SPECIAL (7 << FUNCTION_SHIFT) + +#define INPUT_PULLUP (INPUT | PULLUP) +#define INPUT_PULLDOWN (INPUT | PULLDOWN) +#define OUTPUT_OPEN_DRAIN (OUTPUT | OPEN_DRAIN) +#define INPUT_FUNCTION (INPUT | FUNCTION) +# define INPUT_FUNCTION_0 (INPUT_FUNCTION | FUNCTION_0) +# define INPUT_FUNCTION_1 (INPUT_FUNCTION | FUNCTION_1) +# define INPUT_FUNCTION_2 (INPUT_FUNCTION | FUNCTION_2) +# define INPUT_FUNCTION_3 (INPUT_FUNCTION | FUNCTION_3) +# define INPUT_FUNCTION_4 (INPUT_FUNCTION | FUNCTION_4) +#define OUTPUT_FUNCTION (OUTPUT | FUNCTION) +# define OUTPUT_FUNCTION_0 (OUTPUT_FUNCTION | FUNCTION_0) +# define OUTPUT_FUNCTION_1 (OUTPUT_FUNCTION | FUNCTION_1) +# define OUTPUT_FUNCTION_2 (OUTPUT_FUNCTION | FUNCTION_2) +# define OUTPUT_FUNCTION_3 (OUTPUT_FUNCTION | FUNCTION_3) +# define OUTPUT_FUNCTION_4 (OUTPUT_FUNCTION | FUNCTION_4) /* Interrupt type used with esp32_gpioirqenable() */ @@ -78,7 +102,7 @@ /* Must be big enough to hold the the above encodings */ -typedef uint8_t gpio_pinattr_t; +typedef uint16_t gpio_pinattr_t; typedef uint8_t gpio_intrtype_t; /**************************************************************************** diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c new file mode 100644 index 0000000000..eb6bd3c8cf --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_serial.c @@ -0,0 +1,1212 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_serial.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include +#include +#include + +#include +#include + +#include "xtensa.h" +#include "chip/esp32_soc.h" +#include "chip/esp32_iomux.h" +#include "chip/esp32_gpio_sigmap.h" +#include "chip/esp32_uart.h" +#include "esp32_config.h" +#include "esp32_cpuint.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef USE_SERIALDRIVER + +/* Which UART with be tty0/console and which tty1-2? */ + +/* First pick the console and ttys0. This could be any of UART0-5 */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0port /* UART0 is console */ +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +# define UART0_ASSIGNED 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1 is console */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart2port /* UART2 is console */ +# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */ +# define UART2_ASSIGNED 1 +#else +# undef CONSOLE_DEV /* No console */ +# if defined(CONFIG_ESP32_UART0) +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +# define UART0_ASSIGNED 1 +# elif defined(CONFIG_ESP32_UART1) +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +# elif defined(CONFIG_ESP32_UART2) +# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */ +# define UART2_ASSIGNED 1 +#endif + +/* Pick ttys1. This could be any of UART0-2 excluding the console + * UART. + */ + +#if defined(CONFIG_ESP32_UART0) && !defined(UART0_ASSIGNED) +# define TTYS1_DEV g_uart0port /* UART0 is ttyS1 */ +# define UART0_ASSIGNED 1 +#elif defined(CONFIG_ESP32_UART1) && !defined(UART1_ASSIGNED) +# define TTYS1_DEV g_uart1port /* UART1 is ttyS1 */ +# define UART1_ASSIGNED 1 +#elif defined(CONFIG_ESP32_UART2) && !defined(UART2_ASSIGNED) +# define TTYS1_DEV g_uart2port /* UART2 is ttyS1 */ +# define UART2_ASSIGNED 1 +#endif + +/* Pick ttys2. This could be one of UART1-2. It can't be UART0 + * because that was either assigned as ttyS0 or ttys1. One of these + * could also be the console. + */ + +#if defined(CONFIG_ESP32_UART1) && !defined(UART1_ASSIGNED) +# define TTYS2_DEV g_uart1port /* UART1 is ttyS2 */ +# define UART1_ASSIGNED 1 +#elif defined(CONFIG_ESP32_UART2) && !defined(UART2_ASSIGNED) +# define TTYS2_DEV g_uart2port /* UART2 is ttyS2 */ +# define UART2_ASSIGNED 1 +#endif + +/* UART source clock for BAUD generation */ + +#define UART_CLK_FREQ APB_CLK_FREQ + +/**************************************************************************** + * Private Types + ****************************************************************************/ +/* Constant properties of the UART. Other configuration setting may be + * changable via Termios IOCTL calls. + */ + +struct esp32_config_s +{ + const uint32_t uartbase; /* Base address of UART registers */ + xcpt_t handler; /* Interrupt handler */ + uint8_t periph; /* UART peripheral ID */ + uint8_t irq; /* IRQ number assigned to the peripheral */ + uint8_t txpin; /* Tx pin number (0-39) */ + uint8_t rxpin; /* Rx pin number (0-39) */ + uint8_t txsig; /* Tx signal */ + uint8_t rxsig; /* Rx signal */ +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + uint8_t rtspin; /* RTS pin number (0-39) */ + uint8_t ctspin; /* CTS pin number (0-39) */ + uint8_t rtssig; /* RTS signal */ + uint8_t ctssig; /* CTS signal */ +#endif +}; + +/* Current state of the UART */ + +struct esp32_dev_s +{ + const struct esp32_config_s *config /* Constant configuration */ + uint32_t baud; /* Configured baud */ + uint32_t sr; /* Saved status bits */ + uint8_t cpuint; /* CPU interrupt assigned to this UART */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (5-9) */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + bool flowc; /* Input flow control (RTS) enabled */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int esp32_setup(struct uart_dev_s *dev); +static void esp32_shutdown(struct uart_dev_s *dev); +static int esp32_attach(struct uart_dev_s *dev); +static void esp32_detach(struct uart_dev_s *dev); +static int esp32_interrupt(struct uart_dev_s *dev); +#ifdef CONFIG_ESP32_UART0 +static int esp32_uart0_interrupt(int cpuint, void *context); +#endif +#ifdef CONFIG_ESP32_UART1 +static int esp32_uart1_interrupt(int cpuint, void *context); +#endif +#ifdef CONFIG_ESP32_UART2 +static int esp32_uart2_interrupt(int cpuint, void *context); +#endif +static int esp32_ioctl(struct file *filep, int cmd, unsigned long arg); +static int esp32_receive(struct uart_dev_s *dev, uint32_t *status); +static void esp32_rxint(struct uart_dev_s *dev, bool enable); +static bool esp32_rxavailable(struct uart_dev_s *dev); +static void esp32_send(struct uart_dev_s *dev, int ch); +static void esp32_txint(struct uart_dev_s *dev, bool enable); +static bool esp32_txready(struct uart_dev_s *dev); +static bool esp32_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = esp32_setup, + .shutdown = esp32_shutdown, + .attach = esp32_attach, + .detach = esp32_detach, + .ioctl = esp32_ioctl, + .receive = esp32_receive, + .rxint = esp32_rxint, + .rxavailable = esp32_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = esp32_send, + .txint = esp32_txint, + .txready = esp32_txready, + .txempty = esp32_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_ESP32_UART0 +static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; +#endif +#ifdef CONFIG_ESP32_UART1 +static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; +#endif +#ifdef CONFIG_ESP32_UART2 +static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE]; +static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; +#endif + +/* This describes the state of the UART0 port. */ + +#ifdef CONFIG_ESP32_UART0 +static struct const esp32_config_s g_uart0config = +{ + .uartbase = DR_REG_UART_BASE, + .handler = esp32_uart0_interrupt, + .periph = ESP32_PERIPH_UART, + .irq = ESP32_IRQ_UART, + .txpin = CONFIG_ESP32_UART0_TXPIN, + .rxpin = CONFIG_ESP32_UART0_RXPIN, + .txsig = U0TXD_OUT_IDX, + .rxsig = U0RXD_IN_IDX, +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + .rtspin = CONFIG_ESP32_UART0_RTSPIN, + .ctspin = CONFIG_ESP32_UART0_CTSPIN, + .rtssig = U0RTS_OUT_IDX, + .ctssig = U0CTS_IN_IDX, +#endif +}; + +static struct esp32_dev_s g_uart0priv = +{ + .config = &g_uart0config; + .baud = CONFIG_UART0_BAUD, + .parity = CONFIG_UART0_PARITY, + .bits = CONFIG_UART0_BITS, + .stopbits2 = CONFIG_UART0_2STOP, +}; + +static uart_dev_t g_uart0port = +{ + .recv = + { + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart0priv, +}; +#endif + +/* This describes the state of the UART1 port. */ + +#ifdef CONFIG_ESP32_UART1 +static struct const esp32_config_s g_uart1config = +{ + .uartbase = DR_REG_UART1_BASE, + .handler = esp32_uart1_interrupt, + .periph = ESP32_PERIPH_UART1, + .irq = ESP32_IRQ_UART1, + .txpin = CONFIG_ESP32_UART1_TXPIN, + .rxpin = CONFIG_ESP32_UART1_RXPIN, + .txsig = U1TXD_OUT_IDX, + .rxsig = U1RXD_IN_IDX, +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + .rtspin = CONFIG_ESP32_UART1_RTSPIN, + .ctspin = CONFIG_ESP32_UART1_CTSPIN, + .rtssig = U1RTS_OUT_IDX, + .ctssig = U1CTS_IN_IDX, +#endif +}; + +static struct esp32_dev_s g_uart1priv = +{ + .config = &g_uart1config; + .baud = CONFIG_UART1_BAUD, + .parity = CONFIG_UART1_PARITY, + .bits = CONFIG_UART1_BITS, + .stopbits2 = CONFIG_UART1_2STOP, +}; + +static uart_dev_t g_uart1port = +{ + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; +#endif + +/* This describes the state of the UART2 port. */ + +#ifdef CONFIG_ESP32_UART2 +static struct const esp32_config_s g_uart2config = +{ + .uartbase = DR_REG_UART2_BASE, + .handler = esp32_uart2_interrupt, + .periph = ESP32_PERIPH_UART2, + .irq = ESP32_IRQ_UART2, + .txpin = CONFIG_ESP32_UART2_TXPIN, + .rxpin = CONFIG_ESP32_UART2_RXPIN, + .txsig = U2TXD_OUT_IDX, + .rxsig = U2RXD_IN_IDX, +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + .rtspin = CONFIG_ESP32_UART2_RTSPIN, + .ctspin = CONFIG_ESP32_UART2_CTSPIN, + .rtssig = U2RTS_OUT_IDX, + .ctssig = U2CTS_IN_IDX, +#endif +}; + +static struct esp32_dev_s g_uart2priv = +{ + .config = &g_uart2config; + .baud = CONFIG_UART2_BAUD, + .parity = CONFIG_UART2_PARITY, + .bits = CONFIG_UART2_BITS, + .stopbits2 = CONFIG_UART2_2STOP, +}; + +static uart_dev_t g_uart2port = +{ + .recv = + { + .size = CONFIG_UART2_RXBUFSIZE, + .buffer = g_uart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART2_TXBUFSIZE, + .buffer = g_uart2txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart2priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_serialin + ****************************************************************************/ + +static inline uint32_t esp32_serialin(struct esp32_dev_s *priv, int offset) +{ + return getreg32(priv->config->uartbase + offset); +} + +/**************************************************************************** + * Name: esp32_serialout + ****************************************************************************/ + +static inline void esp32_serialout(struct esp32_dev_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->config->uartbase + offset); +} + +/**************************************************************************** + * Name: esp32_restoreuartint + ****************************************************************************/ + +static inline void esp32_restoreuartint(struct esp32_dev_s *priv, + uint32_t intena) +{ + /* Restore the previous interrupt state (assuming all interrupts disabled) */ + + esp32_serialout(priv, UART_INT_ENA_OFFSET, intena); +} + +/**************************************************************************** + * Name: esp32_disableallints + ****************************************************************************/ + +static void esp32_disableallints(struct esp32_dev_s *priv, uint32_t *intena) +{ + irqstate_t flags; + + /* The following must be atomic */ + + flags = enter_critical_section(); + + if (intena) + { + /* Return the current interrupt mask */ + + *intena = esp32_serialin(priv, UART_INT_ENA_OFFSET); + } + + /* Disable all interrupts */ + + esp32_serialout(priv, UART_INT_ENA_OFFSET, 0); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: esp32_setup + * + * Description: + * Configure the UART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int esp32_setup(struct uart_dev_s *dev) +{ + struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; +#ifndef CONFIG_SUPPRESS_UART_CONFIG + uint32_t clkdiv; + uint32_t regval; + uint32_t conf0; + + /* Note: The logic here depends on the fact that that the UART module + * was enabled and the pins were configured in esp32_lowsetup(). + */ + + /* The shutdown method will put the UART in a known, disabled state */ + + esp32_shutdown(dev); + + /* Set up the CONF0 register. */ + + conf0 = UART_TICK_REF_ALWAYS_ON; + +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + /* Check if flow control is enabled */ + + if (priv->flowc) + { + /* Enable hardware flow control */ + + conf0 |= UART_TX_FLOW_EN; + } +#endif + + /* OR in settings for the selected number of bits */ + + if (priv->bits == 5) + { + /* 0=5 bits */ + } + else if (priv->bits == 6) + { + conf0 |= (1 << UART_BIT_NUM_S); /* 1=6 bits */ + } + else if (priv->bits == 7) + { + conf0 |= (2 << UART_BIT_NUM_S); /* 2=7 bits */ + } + else /* if (priv->bits == 8) */ + { + conf0 |= (3 << UART_BIT_NUM_S); /* 3=8 bits */ + } + + /* OR in settings for the selected parity */ + + if (priv->parity == 1) + { + conf0 |= UART_PARITY_EN; + } + else if (priv->parity == 2) + { + conf0 |= UART_PARITY_EN | UART_PARITY; + } + + /* OR in settings for the number of stop bits */ + + if (priv->stopbits2) + { + conf0 |= 3 << UART_STOP_BIT_NUM_S; + } + else + { + conf0 |= 1 << UART_STOP_BIT_NUM_S; + } + + /* Configure the UART BAUD */ + + clkdiv = (UART_CLK_FREQ << 4) / priv->baud; + + regval = (clkdiv >> 4) << UART_CLKDIV_S; + regval |= (clkdiv & 15) << UART_CLKDIV_FRAG_S; + esp32_serialout(priv, UART_CLKDIV_OFFSET, regval); + + /* Configure UART pins + * + * Internal signals can be output to multiple GPIO pads. + * But only one GPIO pad can connect with input signal + */ + + esp32_configgpio(priv->config->txpin, OUTPUT_FUNCTION_2); + gpio_matrix_out(priv->config->txpin, priv->config->txsig, 0, 0); + + esp32_configgpio(priv->config->rxpin, INPUT_FUNCTION_2); + gpio_matrix_in(priv->config->rxpin, priv->config->rxsig, 0); + +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + esp32_configgpio(priv->config->rtspin, OUTPUT_FUNCTION_2); + gpio_matrix_out(priv->config->rtspin, priv->config->rtssig, 0, 0); + + esp32_configgpio(priv->config->ctspin, INPUT_FUNCTION_2); + gpio_matrix_in(priv->config->ctspin, priv->config->ctssig, 0); +#endif + + /* Enable RX and error interrupts. Clear and pending interrtupt */ + + regval = UART_RXFIFO_FULL_INT_ENA | UART_FRM_ERR_INT_ENA | + UART_RXFIFO_TOUT_INT_ENA; + esp32_serialout(priv, UART_INT_ENA_OFFSET, regval); + + esp32_serialout(priv, UART_INT_CLR_OFFSET, 0xffffffff); + + /* Configure and enable the UART */ + + esp32_serialout(priv, UART_CONF0_OFFSET, conf0); + regval = (112 << UART_RXFIFO_FULL_THRHD_S) | + (0x02 << UART_RX_TOUT_THRHD_S) | + UART_RX_TOUT_EN; + esp32_serialout(priv, UART_CONF1_OFFSET, regval); +#endif + + return OK; +} + +/**************************************************************************** + * Name: esp32_shutdown + * + * Description: + * Disable the UART. This method is called when the serial port is + * closed. It is assumed that esp32_detach was called earlier in the + * shutdown sequence. + * + ****************************************************************************/ + +static void esp32_shutdown(struct uart_dev_s *dev) +{ + struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; + + /* Disable all UART interrupts */ + + esp32_disableallints(priv, NULL); + + /* Revert pins to inputs and detach UART signals */ + + esp32_configgpio(priv->config->txpin, INPUT); + gpio_matrix_out(MATRIX_DETACH_OUT_SIG, priv->txsig, true, false); + + esp32_configgpio(priv->config->rxpin, INPUT); + gpio_matrix_in(MATRIX_DETACH_IN_LOW_PIN, priv->rxsig, false); + +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + esp32_configgpio(priv->config->rtspin, INPUT); + gpio_matrix_out(MATRIX_DETACH_OUT_SIG, priv->rtssig, true, false); + + esp32_configgpio(priv->config->ctspin, INPUT); + gpio_matrix_in(MATRIX_DETACH_IN_LOW_PIN, priv->ctssig, false); +#endif + + /* Unconfigure and disable the UART */ + + esp32_serialout(priv, UART_CONF0_OFFSET, 0); + esp32_serialout(priv, UART_CONF1_OFFSET, 0); + + esp32_serialout(priv, UART_INT_ENA_OFFSET, 0); + esp32_serialout(priv, UART_INT_CLR_OFFSET, 0xffffffff); +} + +/**************************************************************************** + * Name: esp32_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless the + * hardware supports multiple levels of interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() methods are called. + * + ****************************************************************************/ + +static int esp32_attach(struct uart_dev_s *dev) +{ + struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; + int cpu; + int ret = OK; + + /* Allocate a level-sensitive, priority 1 CPU interrupt for the UART */ + + priv->cpuint = esp32_alloc_levelint(1); + if (priv->cpuint < 0) + { + ret = priv->cpuint; + } + + /* Set up to receive peripheral interrupts on the current CPU */ + +#ifdef CONFIG_SMP + cpu = up_cpu_index(); +#else + cpu = 0; +#endif + + /* Attach the GPIO peripheral to the allocated CPU interrupt */ + + up_disable_irq(g_gpio_cpuint); + esp32_attach_peripheral(cpu, priv->config->periph, priv->cpuint); + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->config->irq, priv->config->handler); + if (ret == OK) + { + /* Enable the CPU interrupt (RX and TX interrupts are still disabled + * in the UART + */ + + up_enable_irq(priv->cpuint); + } + + return ret; +} + +/**************************************************************************** + * Name: esp32_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception + * is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void esp32_detach(struct uart_dev_s *dev) +{ + struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; + + /* Disable and detach the CPU interrupt */ + + up_disable_irq(priv->cpuint); + irq_detach(priv->config->irq); + + /* Disassociate the peripheral interrupt from the CPU interrupt */ + + esp32_detach_peripheral(cpu, priv->config->periph); + + /* And release the CPU interrupt */ + + esp32_free_cpuint(priv->cpuint); + priv->cpuint = 0xff; +} + +/**************************************************************************** + * Name: esp32_interrupt + * + * Description: + * This is the common UART interrupt handler. It will be invoked + * when an interrupt received on the device. It should call + * uart_transmitchars or uart_receivechar to perform the appropriate data + * transfers. + * + ****************************************************************************/ + +static int esp32_interrupt(struct uart_dev_s *dev) +{ + struct esp32_dev_s *priv; + uint32_t pending; + uint32_t intena; + int passes; + bool handled; + + DEBUGASSERT(dev && dev->priv); + priv = (struct esp32_dev_s *)dev->priv; + + /* Loop until there are no characters to be transferred or, until we have + * been looping for a long time. + */ + + handled = true; + for (passes = 0; passes < 256 && handled; passes++) + { + handled = false; + + /* Get the UART status (we are only interested in the unmasked interrupts). */ + + priv->sr = esp32_serialin(priv, ESP32_UART_SR_OFFSET); + intena = esp32_serialin(priv, ESP32_UART_IMR_OFFSET); + pending = priv->sr & intena; + + /* Handle an incoming, receive byte. RXRDY: At least one complete character + * has been received and US_RHR has not yet been read. + */ + + if ((pending & UART_INT_RXRDY) != 0) + { + /* Received data ready... process incoming bytes */ + + uart_recvchars(dev); + handled = true; + } + + /* Handle outgoing, transmit bytes. TXRDY: There is no character in the + * US_THR. + */ + + if ((pending & UART_INT_TXRDY) != 0) + { + /* Transmit data register empty ... process outgoing bytes */ + + uart_xmitchars(dev); + handled = true; + } + } + + return OK; +} + +/**************************************************************************** + * Name: esp32_uart[n]_interrupt + * + * Description: + * UART interrupt handlers + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32_UART0 +static int esp32_uart0_interrupt(int cpuint, void *context) +{ + return esp32_interrupt(&g_uart0port); +} +#endif +#ifdef CONFIG_ESP32_UART1 +static int esp32_uart1_interrupt(int cpuint, void *context) +{ + return esp32_interrupt(&g_uart1port); +} +#endif +#ifdef CONFIG_ESP32_UART2 +static int esp32_uart2_interrupt(int cpuint, void *context) +{ + return esp32_interrupt(&g_uart2port); +} +#endif + +/**************************************************************************** + * Name: esp32_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int esp32_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; +#endif + int ret = OK; + + switch (cmd) + { +#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT + case TIOCSERGSTRUCT: + { + struct esp32_dev_s *user = (struct esp32_dev_s *)arg; + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev, sizeof(struct esp32_dev_s)); + } + } + break; +#endif + +#ifdef CONFIG_SERIAL_TERMIOS + case TCGETS: + { + struct termios *termiosp = (struct termios *)arg; + struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Return baud */ + + cfsetispeed(termiosp, priv->baud); + + /* Return parity */ + + termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) | + ((priv->parity == 1) ? PARODD : 0); + + /* Return stop bits */ + + termiosp->c_cflag |= (priv->stopbits2) ? CSTOPB : 0; + + /* Return flow control */ + +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + termiosp->c_cflag |= (priv->flowc) ? (CCTS_OFLOW | CRTS_IFLOW): 0; +#endif + /* Return number of bits */ + + switch (priv->bits) + { + case 5: + termiosp->c_cflag |= CS5; + break; + + case 6: + termiosp->c_cflag |= CS6; + break; + + case 7: + termiosp->c_cflag |= CS7; + break; + + default: + case 8: + termiosp->c_cflag |= CS8; + break; + + case 9: + termiosp->c_cflag |= CS8 /* CS9 */; + break; + } + } + break; + + case TCSETS: + { + struct termios *termiosp = (struct termios *)arg; + struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; + uint32_t baud; + uint32_t intena; + uint8_t parity; + uint8_t nbits; + bool stop2; +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + bool flowc; +#endif + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Decode baud. */ + + ret = OK; + baud = cfgetispeed(termiosp); + + /* Decode number of bits */ + + switch (termiosp->c_cflag & CSIZE) + { + case CS5: + nbits = 5; + break; + + case CS6: + nbits = 6; + break; + + case CS7: + nbits = 7; + break; + + case CS8: + nbits = 8; + break; +#if 0 + case CS9: + nbits = 9; + break; +#endif + default: + ret = -EINVAL; + break; + } + + /* Decode parity */ + + if ((termiosp->c_cflag & PARENB) != 0) + { + parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + parity = 0; + } + + /* Decode stop bits */ + + stop2 = (termiosp->c_cflag & CSTOPB) != 0; + + /* Decode flow control */ + +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + flowc = (termiosp->c_cflag & (CCTS_OFLOW | CRTS_IFLOW)) != 0; +#endif + /* Verify that all settings are valid before committing */ + + if (ret == OK) + { + /* Commit */ + + priv->baud = baud; + priv->parity = parity; + priv->bits = nbits; + priv->stopbits2 = stop2; +#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) + priv->flowc = flowc; +#endif + /* effect the changes immediately - note that we do not + * implement TCSADRAIN / TCSAFLUSH + */ + + esp32_disableallints(priv, &intena); + ret = esp32_setup(dev); + + /* Restore the interrupt state */ + + esp32_restoreuartint(priv, intena); + } + } + break; +#endif /* CONFIG_SERIAL_TERMIOS */ + + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: esp32_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int esp32_receive(struct uart_dev_s *dev, uint32_t *status) +{ + struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; + + /* Return the error information in the saved status */ + + *status = priv->sr; + priv->sr = 0; + + /* Then return the actual received byte */ + + return (int)(esp32_serialin(priv, ESP32_UART_RHR_OFFSET) & 0xff); +} + +/**************************************************************************** + * Name: esp32_rxint + * + * Description: + * Call to enable or disable RXRDY interrupts + * + ****************************************************************************/ + +static void esp32_rxint(struct uart_dev_s *dev, bool enable) +{ + struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; + + if (enable) + { + /* Receive an interrupt when their is anything in the Rx data register (or an Rx + * timeout occurs). + */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + esp32_serialout(priv, ESP32_UART_IER_OFFSET, UART_INT_RXRDY); +#endif + } + else + { + esp32_serialout(priv, ESP32_UART_IDR_OFFSET, UART_INT_RXRDY); + } +} + +/**************************************************************************** + * Name: esp32_rxavailable + * + * Description: + * Return true if the receive holding register is not empty + * + ****************************************************************************/ + +static bool esp32_rxavailable(struct uart_dev_s *dev) +{ + struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; + return ((esp32_serialin(priv, ESP32_UART_SR_OFFSET) & UART_INT_RXRDY) != 0); +} + +/**************************************************************************** + * Name: esp32_send + * + * Description: + * This method will send one byte on the UART. + * + ****************************************************************************/ + +static void esp32_send(struct uart_dev_s *dev, int ch) +{ + struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; + esp32_serialout(priv, ESP32_UART_THR_OFFSET, (uint32_t)ch); +} + +/**************************************************************************** + * Name: esp32_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void esp32_txint(struct uart_dev_s *dev, bool enable) +{ + struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; + irqstate_t flags; + + flags = enter_critical_section(); + if (enable) + { + /* Set to receive an interrupt when the TX holding register register + * is empty + */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + esp32_serialout(priv, ESP32_UART_IER_OFFSET, UART_INT_TXRDY); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); + +#endif + } + else + { + /* Disable the TX interrupt */ + + esp32_serialout(priv, ESP32_UART_IDR_OFFSET, UART_INT_TXRDY); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: esp32_txready + * + * Description: + * Return true if the transmit holding register is empty (TXRDY) + * + ****************************************************************************/ + +static bool esp32_txready(struct uart_dev_s *dev) +{ + struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; + return ((esp32_serialin(priv, ESP32_UART_SR_OFFSET) & UART_INT_TXRDY) != 0); +} + +/**************************************************************************** + * Name: esp32_txempty + * + * Description: + * Return true if the transmit holding and shift registers are empty + * + ****************************************************************************/ + +static bool esp32_txempty(struct uart_dev_s *dev) +{ + struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; + return ((esp32_serialin(priv, ESP32_UART_SR_OFFSET) & UART_INT_TXEMPTY) != 0); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before up_serialinit. + * + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT +void up_earlyserialinit(void) +{ + /* NOTE: All GPIO configuration for the UARTs was performed in + * esp32_lowsetup + */ + + /* Disable all UARTS */ + + esp32_disableallints(TTYS0_DEV.priv, NULL); +#ifdef TTYS1_DEV + esp32_disableallints(TTYS1_DEV.priv, NULL); +#endif +#ifdef TTYS2_DEV + esp32_disableallints(TTYS2_DEV.priv, NULL); +#endif + + /* Configuration whichever one is the console */ + +#ifdef HAVE_SERIAL_CONSOLE + CONSOLE_DEV.isconsole = true; + esp32_setup(&CONSOLE_DEV); +#endif +} +#endif + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that up_earlyserialinit was called previously. + * + ****************************************************************************/ + +void up_serialinit(void) +{ + /* Register the console */ + +#ifdef HAVE_SERIAL_CONSOLE + (void)uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* Register all UARTs */ + + (void)uart_register("/dev/ttyS0", &TTYS0_DEV); +#ifdef TTYS1_DEV + (void)uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +#ifdef TTYS2_DEV + (void)uart_register("/dev/ttyS2", &TTYS2_DEV); +#endif +} + +#endif /* USE_SERIALDRIVER */ diff --git a/arch/xtensa/src/esp32/rom/esp32_gpio.h b/arch/xtensa/src/esp32/rom/esp32_gpio.h index a6089d33b7..fc2e6ded25 100644 --- a/arch/xtensa/src/esp32/rom/esp32_gpio.h +++ b/arch/xtensa/src/esp32/rom/esp32_gpio.h @@ -38,6 +38,14 @@ #include "chip/gpio_reg.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MATRIX_DETACH_OUT_SIG 0x100 /* Detach an OUTPUT signal */ +#define MATRIX_DETACH_IN_LOW_PIN 0x30 /* Detach non-inverted INPUT signal */ +#define MATRIX_DETACH_IN_LOW_HIGH 0x38 /* Detach inverted INPUT signal */ + /**************************************************************************** * Public Types ****************************************************************************/ -- GitLab From 912fe06a86df238918bfae7d37179d1fba7a4120 Mon Sep 17 00:00:00 2001 From: "Paul A. Patience" Date: Thu, 27 Oct 2016 14:52:57 -0400 Subject: [PATCH 234/734] Add architecture-specific inttypes.h --- arch/arm/include/inttypes.h | 245 +++++++++++++++ arch/avr/include/avr/inttypes.h | 245 +++++++++++++++ arch/avr/include/avr32/inttypes.h | 245 +++++++++++++++ arch/avr/include/inttypes.h | 53 ++++ arch/hc/include/inttypes.h | 449 +++++++++++++++++++++++++++ arch/mips/include/inttypes.h | 245 +++++++++++++++ arch/renesas/include/inttypes.h | 49 +++ arch/renesas/include/m16c/inttypes.h | 245 +++++++++++++++ arch/renesas/include/sh1/inttypes.h | 245 +++++++++++++++ arch/rgmp/include/inttypes.h | 245 +++++++++++++++ arch/risc-v/include/inttypes.h | 245 +++++++++++++++ arch/sim/include/inttypes.h | 449 +++++++++++++++++++++++++++ arch/x86/include/i486/inttypes.h | 245 +++++++++++++++ arch/x86/include/inttypes.h | 51 +++ arch/xtensa/include/inttypes.h | 245 +++++++++++++++ arch/z16/include/inttypes.h | 212 +++++++++++++ arch/z80/include/ez80/inttypes.h | 372 ++++++++++++++++++++++ arch/z80/include/inttypes.h | 49 +++ arch/z80/include/z180/inttypes.h | 212 +++++++++++++ arch/z80/include/z8/inttypes.h | 212 +++++++++++++ arch/z80/include/z80/inttypes.h | 212 +++++++++++++ include/inttypes.h | 2 + 22 files changed, 4772 insertions(+) create mode 100644 arch/arm/include/inttypes.h create mode 100644 arch/avr/include/avr/inttypes.h create mode 100644 arch/avr/include/avr32/inttypes.h create mode 100644 arch/avr/include/inttypes.h create mode 100644 arch/hc/include/inttypes.h create mode 100644 arch/mips/include/inttypes.h create mode 100644 arch/renesas/include/inttypes.h create mode 100644 arch/renesas/include/m16c/inttypes.h create mode 100644 arch/renesas/include/sh1/inttypes.h create mode 100644 arch/rgmp/include/inttypes.h create mode 100644 arch/risc-v/include/inttypes.h create mode 100644 arch/sim/include/inttypes.h create mode 100644 arch/x86/include/i486/inttypes.h create mode 100644 arch/x86/include/inttypes.h create mode 100644 arch/xtensa/include/inttypes.h create mode 100644 arch/z16/include/inttypes.h create mode 100644 arch/z80/include/ez80/inttypes.h create mode 100644 arch/z80/include/inttypes.h create mode 100644 arch/z80/include/z180/inttypes.h create mode 100644 arch/z80/include/z8/inttypes.h create mode 100644 arch/z80/include/z80/inttypes.h diff --git a/arch/arm/include/inttypes.h b/arch/arm/include/inttypes.h new file mode 100644 index 0000000000..280d4a5eca --- /dev/null +++ b/arch/arm/include/inttypes.h @@ -0,0 +1,245 @@ +/**************************************************************************** + * arch/arm/include/inttypes.h + * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_INTTYPES_H +#define __ARCH_ARM_INCLUDE_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PRId8 "d" +#define PRId16 "d" +#define PRId32 "d" +#define PRId64 "lld" + +#define PRIdLEAST8 "d" +#define PRIdLEAST16 "d" +#define PRIdLEAST32 "d" +#define PRIdLEAST64 "lld" + +#define PRIdFAST8 "d" +#define PRIdFAST16 "d" +#define PRIdFAST32 "d" +#define PRIdFAST64 "lld" + +#define PRIdMAX "lld" +#define PRIdPTR "d" + +#define PRIi8 "i" +#define PRIi16 "i" +#define PRIi32 "i" +#define PRIi64 "lli" + +#define PRIiLEAST8 "i" +#define PRIiLEAST16 "i" +#define PRIiLEAST32 "i" +#define PRIiLEAST64 "lli" + +#define PRIiFAST8 "i" +#define PRIiFAST16 "i" +#define PRIiFAST32 "i" +#define PRIiFAST64 "lli" + +#define PRIiMAX "lli" +#define PRIiPTR "i" + +#define PRIo8 "o" +#define PRIo16 "o" +#define PRIo32 "o" +#define PRIo64 "llo" + +#define PRIoLEAST8 "o" +#define PRIoLEAST16 "o" +#define PRIoLEAST32 "o" +#define PRIoLEAST64 "llo" + +#define PRIoFAST8 "o" +#define PRIoFAST16 "o" +#define PRIoFAST32 "o" +#define PRIoFAST64 "llo" + +#define PRIoMAX "llo" +#define PRIoPTR "o" + +#define PRIu8 "u" +#define PRIu16 "u" +#define PRIu32 "u" +#define PRIu64 "llu" + +#define PRIuLEAST8 "u" +#define PRIuLEAST16 "u" +#define PRIuLEAST32 "u" +#define PRIuLEAST64 "llu" + +#define PRIuFAST8 "u" +#define PRIuFAST16 "u" +#define PRIuFAST32 "u" +#define PRIuFAST64 "llu" + +#define PRIuMAX "llu" +#define PRIuPTR "u" + +#define PRIx8 "x" +#define PRIx16 "x" +#define PRIx32 "x" +#define PRIx64 "llx" + +#define PRIxLEAST8 "x" +#define PRIxLEAST16 "x" +#define PRIxLEAST32 "x" +#define PRIxLEAST64 "llx" + +#define PRIxFAST8 "x" +#define PRIxFAST16 "x" +#define PRIxFAST32 "x" +#define PRIxFAST64 "llx" + +#define PRIxMAX "llx" +#define PRIxPTR "x" + +#define PRIX8 "X" +#define PRIX16 "X" +#define PRIX32 "X" +#define PRIX64 "llX" + +#define PRIXLEAST8 "X" +#define PRIXLEAST16 "X" +#define PRIXLEAST32 "X" +#define PRIXLEAST64 "llX" + +#define PRIXFAST8 "X" +#define PRIXFAST16 "X" +#define PRIXFAST32 "X" +#define PRIXFAST64 "llX" + +#define PRIXMAX "llX" +#define PRIXPTR "X" + +#define SCNd8 "hhd" +#define SCNd16 "hd" +#define SCNd32 "d" +#define SCNd64 "lld" + +#define SCNdLEAST8 "hhd" +#define SCNdLEAST16 "hd" +#define SCNdLEAST32 "d" +#define SCNdLEAST64 "lld" + +#define SCNdFAST8 "hhd" +#define SCNdFAST16 "hd" +#define SCNdFAST32 "d" +#define SCNdFAST64 "lld" + +#define SCNdMAX "lld" +#define SCNdPTR "d" + +#define SCNi8 "hhi" +#define SCNi16 "hi" +#define SCNi32 "i" +#define SCNi64 "lli" + +#define SCNiLEAST8 "hhi" +#define SCNiLEAST16 "hi" +#define SCNiLEAST32 "i" +#define SCNiLEAST64 "lli" + +#define SCNiFAST8 "hhi" +#define SCNiFAST16 "hi" +#define SCNiFAST32 "i" +#define SCNiFAST64 "lli" + +#define SCNiMAX "lli" +#define SCNiPTR "i" + +#define SCNo8 "hho" +#define SCNo16 "ho" +#define SCNo32 "o" +#define SCNo64 "llo" + +#define SCNoLEAST8 "hho" +#define SCNoLEAST16 "ho" +#define SCNoLEAST32 "o" +#define SCNoLEAST64 "llo" + +#define SCNoFAST8 "hho" +#define SCNoFAST16 "ho" +#define SCNoFAST32 "o" +#define SCNoFAST64 "llo" + +#define SCNoMAX "llo" +#define SCNoPTR "o" + +#define SCNu8 "hhu" +#define SCNu16 "hu" +#define SCNu32 "u" +#define SCNu64 "llu" + +#define SCNuLEAST8 "hhu" +#define SCNuLEAST16 "hu" +#define SCNuLEAST32 "u" +#define SCNuLEAST64 "llu" + +#define SCNuFAST8 "hhu" +#define SCNuFAST16 "hu" +#define SCNuFAST32 "u" +#define SCNuFAST64 "llu" + +#define SCNuMAX "llu" +#define SCNuPTR "u" + +#define SCNx8 "hhx" +#define SCNx16 "hx" +#define SCNx32 "x" +#define SCNx64 "llx" + +#define SCNxLEAST8 "hhx" +#define SCNxLEAST16 "hx" +#define SCNxLEAST32 "x" +#define SCNxLEAST64 "llx" + +#define SCNxFAST8 "hhx" +#define SCNxFAST16 "hx" +#define SCNxFAST32 "x" +#define SCNxFAST64 "llx" + +#define SCNxMAX "llx" +#define SCNxPTR "x" + +#endif /* __ARCH_ARM_INCLUDE_INTTYPES_H */ diff --git a/arch/avr/include/avr/inttypes.h b/arch/avr/include/avr/inttypes.h new file mode 100644 index 0000000000..0b2213533c --- /dev/null +++ b/arch/avr/include/avr/inttypes.h @@ -0,0 +1,245 @@ +/**************************************************************************** + * arch/avr/include/avr/inttypes.h + * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_AVR_INCLUDE_AVR_INTTYPES_H +#define __ARCH_AVR_INCLUDE_AVR_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PRId8 "d" +#define PRId16 "d" +#define PRId32 "ld" +#define PRId64 "lld" + +#define PRIdLEAST8 "d" +#define PRIdLEAST16 "d" +#define PRIdLEAST32 "ld" +#define PRIdLEAST64 "lld" + +#define PRIdFAST8 "d" +#define PRIdFAST16 "d" +#define PRIdFAST32 "ld" +#define PRIdFAST64 "lld" + +#define PRIdMAX "lld" +#define PRIdPTR "d" + +#define PRIi8 "i" +#define PRIi16 "i" +#define PRIi32 "li" +#define PRIi64 "lli" + +#define PRIiLEAST8 "i" +#define PRIiLEAST16 "i" +#define PRIiLEAST32 "li" +#define PRIiLEAST64 "lli" + +#define PRIiFAST8 "i" +#define PRIiFAST16 "i" +#define PRIiFAST32 "li" +#define PRIiFAST64 "lli" + +#define PRIiMAX "lli" +#define PRIiPTR "i" + +#define PRIo8 "o" +#define PRIo16 "o" +#define PRIo32 "lo" +#define PRIo64 "llo" + +#define PRIoLEAST8 "o" +#define PRIoLEAST16 "o" +#define PRIoLEAST32 "lo" +#define PRIoLEAST64 "llo" + +#define PRIoFAST8 "o" +#define PRIoFAST16 "o" +#define PRIoFAST32 "lo" +#define PRIoFAST64 "llo" + +#define PRIoMAX "llo" +#define PRIoPTR "o" + +#define PRIu8 "u" +#define PRIu16 "u" +#define PRIu32 "lu" +#define PRIu64 "llu" + +#define PRIuLEAST8 "u" +#define PRIuLEAST16 "u" +#define PRIuLEAST32 "lu" +#define PRIuLEAST64 "llu" + +#define PRIuFAST8 "u" +#define PRIuFAST16 "u" +#define PRIuFAST32 "lu" +#define PRIuFAST64 "llu" + +#define PRIuMAX "llu" +#define PRIuPTR "u" + +#define PRIx8 "x" +#define PRIx16 "x" +#define PRIx32 "lx" +#define PRIx64 "llx" + +#define PRIxLEAST8 "x" +#define PRIxLEAST16 "x" +#define PRIxLEAST32 "lx" +#define PRIxLEAST64 "llx" + +#define PRIxFAST8 "x" +#define PRIxFAST16 "x" +#define PRIxFAST32 "lx" +#define PRIxFAST64 "llx" + +#define PRIxMAX "llx" +#define PRIxPTR "x" + +#define PRIX8 "X" +#define PRIX16 "X" +#define PRIX32 "lX" +#define PRIX64 "llX" + +#define PRIXLEAST8 "X" +#define PRIXLEAST16 "X" +#define PRIXLEAST32 "lX" +#define PRIXLEAST64 "llX" + +#define PRIXFAST8 "X" +#define PRIXFAST16 "X" +#define PRIXFAST32 "lX" +#define PRIXFAST64 "llX" + +#define PRIXMAX "llX" +#define PRIXPTR "X" + +#define SCNd8 "hhd" +#define SCNd16 "d" +#define SCNd32 "ld" +#define SCNd64 "lld" + +#define SCNdLEAST8 "hhd" +#define SCNdLEAST16 "d" +#define SCNdLEAST32 "ld" +#define SCNdLEAST64 "lld" + +#define SCNdFAST8 "hhd" +#define SCNdFAST16 "d" +#define SCNdFAST32 "ld" +#define SCNdFAST64 "lld" + +#define SCNdMAX "lld" +#define SCNdPTR "d" + +#define SCNi8 "hhi" +#define SCNi16 "i" +#define SCNi32 "li" +#define SCNi64 "lli" + +#define SCNiLEAST8 "hhi" +#define SCNiLEAST16 "i" +#define SCNiLEAST32 "li" +#define SCNiLEAST64 "lli" + +#define SCNiFAST8 "hhi" +#define SCNiFAST16 "i" +#define SCNiFAST32 "li" +#define SCNiFAST64 "lli" + +#define SCNiMAX "lli" +#define SCNiPTR "i" + +#define SCNo8 "hho" +#define SCNo16 "o" +#define SCNo32 "lo" +#define SCNo64 "llo" + +#define SCNoLEAST8 "hho" +#define SCNoLEAST16 "o" +#define SCNoLEAST32 "lo" +#define SCNoLEAST64 "llo" + +#define SCNoFAST8 "hho" +#define SCNoFAST16 "o" +#define SCNoFAST32 "lo" +#define SCNoFAST64 "llo" + +#define SCNoMAX "llo" +#define SCNoPTR "o" + +#define SCNu8 "hhu" +#define SCNu16 "u" +#define SCNu32 "lu" +#define SCNu64 "llu" + +#define SCNuLEAST8 "hhu" +#define SCNuLEAST16 "u" +#define SCNuLEAST32 "lu" +#define SCNuLEAST64 "llu" + +#define SCNuFAST8 "hhu" +#define SCNuFAST16 "u" +#define SCNuFAST32 "lu" +#define SCNuFAST64 "llu" + +#define SCNuMAX "llu" +#define SCNuPTR "u" + +#define SCNx8 "hhx" +#define SCNx16 "x" +#define SCNx32 "lx" +#define SCNx64 "llx" + +#define SCNxLEAST8 "hhx" +#define SCNxLEAST16 "x" +#define SCNxLEAST32 "lx" +#define SCNxLEAST64 "llx" + +#define SCNxFAST8 "hhx" +#define SCNxFAST16 "x" +#define SCNxFAST32 "lx" +#define SCNxFAST64 "llx" + +#define SCNxMAX "llx" +#define SCNxPTR "x" + +#endif /* __ARCH_AVR_INCLUDE_AVR_INTTYPES_H */ diff --git a/arch/avr/include/avr32/inttypes.h b/arch/avr/include/avr32/inttypes.h new file mode 100644 index 0000000000..cf6207429b --- /dev/null +++ b/arch/avr/include/avr32/inttypes.h @@ -0,0 +1,245 @@ +/**************************************************************************** + * arch/avr/include/avr32/inttypes.h + * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_AVR_INCLUDE_AVR32_INTTYPES_H +#define __ARCH_AVR_INCLUDE_AVR32_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PRId8 "d" +#define PRId16 "d" +#define PRId32 "d" +#define PRId64 "lld" + +#define PRIdLEAST8 "d" +#define PRIdLEAST16 "d" +#define PRIdLEAST32 "d" +#define PRIdLEAST64 "lld" + +#define PRIdFAST8 "d" +#define PRIdFAST16 "d" +#define PRIdFAST32 "d" +#define PRIdFAST64 "lld" + +#define PRIdMAX "lld" +#define PRIdPTR "d" + +#define PRIi8 "i" +#define PRIi16 "i" +#define PRIi32 "i" +#define PRIi64 "lli" + +#define PRIiLEAST8 "i" +#define PRIiLEAST16 "i" +#define PRIiLEAST32 "i" +#define PRIiLEAST64 "lli" + +#define PRIiFAST8 "i" +#define PRIiFAST16 "i" +#define PRIiFAST32 "i" +#define PRIiFAST64 "lli" + +#define PRIiMAX "lli" +#define PRIiPTR "i" + +#define PRIo8 "o" +#define PRIo16 "o" +#define PRIo32 "o" +#define PRIo64 "llo" + +#define PRIoLEAST8 "o" +#define PRIoLEAST16 "o" +#define PRIoLEAST32 "o" +#define PRIoLEAST64 "llo" + +#define PRIoFAST8 "o" +#define PRIoFAST16 "o" +#define PRIoFAST32 "o" +#define PRIoFAST64 "llo" + +#define PRIoMAX "llo" +#define PRIoPTR "o" + +#define PRIu8 "u" +#define PRIu16 "u" +#define PRIu32 "u" +#define PRIu64 "llu" + +#define PRIuLEAST8 "u" +#define PRIuLEAST16 "u" +#define PRIuLEAST32 "u" +#define PRIuLEAST64 "llu" + +#define PRIuFAST8 "u" +#define PRIuFAST16 "u" +#define PRIuFAST32 "u" +#define PRIuFAST64 "llu" + +#define PRIuMAX "llu" +#define PRIuPTR "u" + +#define PRIx8 "x" +#define PRIx16 "x" +#define PRIx32 "x" +#define PRIx64 "llx" + +#define PRIxLEAST8 "x" +#define PRIxLEAST16 "x" +#define PRIxLEAST32 "x" +#define PRIxLEAST64 "llx" + +#define PRIxFAST8 "x" +#define PRIxFAST16 "x" +#define PRIxFAST32 "x" +#define PRIxFAST64 "llx" + +#define PRIxMAX "llx" +#define PRIxPTR "x" + +#define PRIX8 "X" +#define PRIX16 "X" +#define PRIX32 "X" +#define PRIX64 "llX" + +#define PRIXLEAST8 "X" +#define PRIXLEAST16 "X" +#define PRIXLEAST32 "X" +#define PRIXLEAST64 "llX" + +#define PRIXFAST8 "X" +#define PRIXFAST16 "X" +#define PRIXFAST32 "X" +#define PRIXFAST64 "llX" + +#define PRIXMAX "llX" +#define PRIXPTR "X" + +#define SCNd8 "hhd" +#define SCNd16 "hd" +#define SCNd32 "d" +#define SCNd64 "lld" + +#define SCNdLEAST8 "hhd" +#define SCNdLEAST16 "hd" +#define SCNdLEAST32 "d" +#define SCNdLEAST64 "lld" + +#define SCNdFAST8 "hhd" +#define SCNdFAST16 "hd" +#define SCNdFAST32 "d" +#define SCNdFAST64 "lld" + +#define SCNdMAX "lld" +#define SCNdPTR "d" + +#define SCNi8 "hhi" +#define SCNi16 "hi" +#define SCNi32 "i" +#define SCNi64 "lli" + +#define SCNiLEAST8 "hhi" +#define SCNiLEAST16 "hi" +#define SCNiLEAST32 "i" +#define SCNiLEAST64 "lli" + +#define SCNiFAST8 "hhi" +#define SCNiFAST16 "hi" +#define SCNiFAST32 "i" +#define SCNiFAST64 "lli" + +#define SCNiMAX "lli" +#define SCNiPTR "i" + +#define SCNo8 "hho" +#define SCNo16 "ho" +#define SCNo32 "o" +#define SCNo64 "llo" + +#define SCNoLEAST8 "hho" +#define SCNoLEAST16 "ho" +#define SCNoLEAST32 "o" +#define SCNoLEAST64 "llo" + +#define SCNoFAST8 "hho" +#define SCNoFAST16 "ho" +#define SCNoFAST32 "o" +#define SCNoFAST64 "llo" + +#define SCNoMAX "llo" +#define SCNoPTR "o" + +#define SCNu8 "hhu" +#define SCNu16 "hu" +#define SCNu32 "u" +#define SCNu64 "llu" + +#define SCNuLEAST8 "hhu" +#define SCNuLEAST16 "hu" +#define SCNuLEAST32 "u" +#define SCNuLEAST64 "llu" + +#define SCNuFAST8 "hhu" +#define SCNuFAST16 "hu" +#define SCNuFAST32 "u" +#define SCNuFAST64 "llu" + +#define SCNuMAX "llu" +#define SCNuPTR "u" + +#define SCNx8 "hhx" +#define SCNx16 "hx" +#define SCNx32 "x" +#define SCNx64 "llx" + +#define SCNxLEAST8 "hhx" +#define SCNxLEAST16 "hx" +#define SCNxLEAST32 "x" +#define SCNxLEAST64 "llx" + +#define SCNxFAST8 "hhx" +#define SCNxFAST16 "hx" +#define SCNxFAST32 "x" +#define SCNxFAST64 "llx" + +#define SCNxMAX "llx" +#define SCNxPTR "x" + +#endif /* __ARCH_AVR_INCLUDE_AVR32_INTTYPES_H */ diff --git a/arch/avr/include/inttypes.h b/arch/avr/include/inttypes.h new file mode 100644 index 0000000000..7d5025968a --- /dev/null +++ b/arch/avr/include/inttypes.h @@ -0,0 +1,53 @@ +/**************************************************************************** + * arch/avr/include/inttypes.h + * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_AVR_INCLUDE_INTTYPES_H +#define __ARCH_AVR_INCLUDE_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifdef CONFIG_ARCH_FAMILY_AVR32 +# include +#else +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_AVR_INCLUDE_INTTYPES_H */ diff --git a/arch/hc/include/inttypes.h b/arch/hc/include/inttypes.h new file mode 100644 index 0000000000..2ff0e79369 --- /dev/null +++ b/arch/hc/include/inttypes.h @@ -0,0 +1,449 @@ +/**************************************************************************** + * arch/hc/include/inttypes.h + * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_HC_INCLUDE_INTTYPES_H +#define __ARCH_HC_INCLUDE_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if __INT__ == 16 + +# define PRId8 "d" +# define PRId16 "d" +# define PRId32 "ld" +# define PRId64 "lld" + +# define PRIdLEAST8 "d" +# define PRIdLEAST16 "d" +# define PRIdLEAST32 "ld" +# define PRIdLEAST64 "lld" + +# define PRIdFAST8 "d" +# define PRIdFAST16 "d" +# define PRIdFAST32 "ld" +# define PRIdFAST64 "lld" + +# define PRIdMAX "lld" +# define PRIdPTR "d" + +# define PRIi8 "i" +# define PRIi16 "i" +# define PRIi32 "li" +# define PRIi64 "lli" + +# define PRIiLEAST8 "i" +# define PRIiLEAST16 "i" +# define PRIiLEAST32 "li" +# define PRIiLEAST64 "lli" + +# define PRIiFAST8 "i" +# define PRIiFAST16 "i" +# define PRIiFAST32 "li" +# define PRIiFAST64 "lli" + +# define PRIiMAX "lli" +# define PRIiPTR "i" + +# define PRIo8 "o" +# define PRIo16 "o" +# define PRIo32 "lo" +# define PRIo64 "llo" + +# define PRIoLEAST8 "o" +# define PRIoLEAST16 "o" +# define PRIoLEAST32 "lo" +# define PRIoLEAST64 "llo" + +# define PRIoFAST8 "o" +# define PRIoFAST16 "o" +# define PRIoFAST32 "lo" +# define PRIoFAST64 "llo" + +# define PRIoMAX "llo" +# define PRIoPTR "o" + +# define PRIu8 "u" +# define PRIu16 "u" +# define PRIu32 "lu" +# define PRIu64 "llu" + +# define PRIuLEAST8 "u" +# define PRIuLEAST16 "u" +# define PRIuLEAST32 "lu" +# define PRIuLEAST64 "llu" + +# define PRIuFAST8 "u" +# define PRIuFAST16 "u" +# define PRIuFAST32 "lu" +# define PRIuFAST64 "llu" + +# define PRIuMAX "llu" +# define PRIuPTR "u" + +# define PRIx8 "x" +# define PRIx16 "x" +# define PRIx32 "lx" +# define PRIx64 "llx" + +# define PRIxLEAST8 "x" +# define PRIxLEAST16 "x" +# define PRIxLEAST32 "lx" +# define PRIxLEAST64 "llx" + +# define PRIxFAST8 "x" +# define PRIxFAST16 "x" +# define PRIxFAST32 "lx" +# define PRIxFAST64 "llx" + +# define PRIxMAX "llx" +# define PRIxPTR "x" + +# define PRIX8 "X" +# define PRIX16 "X" +# define PRIX32 "lX" +# define PRIX64 "llX" + +# define PRIXLEAST8 "X" +# define PRIXLEAST16 "X" +# define PRIXLEAST32 "lX" +# define PRIXLEAST64 "llX" + +# define PRIXFAST8 "X" +# define PRIXFAST16 "X" +# define PRIXFAST32 "lX" +# define PRIXFAST64 "llX" + +# define PRIXMAX "llX" +# define PRIXPTR "X" + +# define SCNd8 "hhd" +# define SCNd16 "d" +# define SCNd32 "ld" +# define SCNd64 "lld" + +# define SCNdLEAST8 "hhd" +# define SCNdLEAST16 "d" +# define SCNdLEAST32 "ld" +# define SCNdLEAST64 "lld" + +# define SCNdFAST8 "hhd" +# define SCNdFAST16 "d" +# define SCNdFAST32 "ld" +# define SCNdFAST64 "lld" + +# define SCNdMAX "lld" +# define SCNdPTR "d" + +# define SCNi8 "hhi" +# define SCNi16 "i" +# define SCNi32 "li" +# define SCNi64 "lli" + +# define SCNiLEAST8 "hhi" +# define SCNiLEAST16 "i" +# define SCNiLEAST32 "li" +# define SCNiLEAST64 "lli" + +# define SCNiFAST8 "hhi" +# define SCNiFAST16 "i" +# define SCNiFAST32 "li" +# define SCNiFAST64 "lli" + +# define SCNiMAX "lli" +# define SCNiPTR "i" + +# define SCNo8 "hho" +# define SCNo16 "o" +# define SCNo32 "lo" +# define SCNo64 "llo" + +# define SCNoLEAST8 "hho" +# define SCNoLEAST16 "o" +# define SCNoLEAST32 "lo" +# define SCNoLEAST64 "llo" + +# define SCNoFAST8 "hho" +# define SCNoFAST16 "o" +# define SCNoFAST32 "lo" +# define SCNoFAST64 "llo" + +# define SCNoMAX "llo" +# define SCNoPTR "o" + +# define SCNu8 "hhu" +# define SCNu16 "u" +# define SCNu32 "lu" +# define SCNu64 "llu" + +# define SCNuLEAST8 "hhu" +# define SCNuLEAST16 "u" +# define SCNuLEAST32 "lu" +# define SCNuLEAST64 "llu" + +# define SCNuFAST8 "hhu" +# define SCNuFAST16 "u" +# define SCNuFAST32 "lu" +# define SCNuFAST64 "llu" + +# define SCNuMAX "llu" +# define SCNuPTR "u" + +# define SCNx8 "hhx" +# define SCNx16 "x" +# define SCNx32 "lx" +# define SCNx64 "llx" + +# define SCNxLEAST8 "hhx" +# define SCNxLEAST16 "x" +# define SCNxLEAST32 "lx" +# define SCNxLEAST64 "llx" + +# define SCNxFAST8 "hhx" +# define SCNxFAST16 "x" +# define SCNxFAST32 "lx" +# define SCNxFAST64 "llx" + +# define SCNxMAX "llx" +# define SCNxPTR "x" + +#else + +# define PRId8 "d" +# define PRId16 "d" +# define PRId32 "d" +# define PRId64 "lld" + +# define PRIdLEAST8 "d" +# define PRIdLEAST16 "d" +# define PRIdLEAST32 "d" +# define PRIdLEAST64 "lld" + +# define PRIdFAST8 "d" +# define PRIdFAST16 "d" +# define PRIdFAST32 "d" +# define PRIdFAST64 "lld" + +# define PRIdMAX "lld" +# define PRIdPTR "d" + +# define PRIi8 "i" +# define PRIi16 "i" +# define PRIi32 "i" +# define PRIi64 "lli" + +# define PRIiLEAST8 "i" +# define PRIiLEAST16 "i" +# define PRIiLEAST32 "i" +# define PRIiLEAST64 "lli" + +# define PRIiFAST8 "i" +# define PRIiFAST16 "i" +# define PRIiFAST32 "i" +# define PRIiFAST64 "lli" + +# define PRIiMAX "lli" +# define PRIiPTR "i" + +# define PRIo8 "o" +# define PRIo16 "o" +# define PRIo32 "o" +# define PRIo64 "llo" + +# define PRIoLEAST8 "o" +# define PRIoLEAST16 "o" +# define PRIoLEAST32 "o" +# define PRIoLEAST64 "llo" + +# define PRIoFAST8 "o" +# define PRIoFAST16 "o" +# define PRIoFAST32 "o" +# define PRIoFAST64 "llo" + +# define PRIoMAX "llo" +# define PRIoPTR "o" + +# define PRIu8 "u" +# define PRIu16 "u" +# define PRIu32 "u" +# define PRIu64 "llu" + +# define PRIuLEAST8 "u" +# define PRIuLEAST16 "u" +# define PRIuLEAST32 "u" +# define PRIuLEAST64 "llu" + +# define PRIuFAST8 "u" +# define PRIuFAST16 "u" +# define PRIuFAST32 "u" +# define PRIuFAST64 "llu" + +# define PRIuMAX "llu" +# define PRIuPTR "u" + +# define PRIx8 "x" +# define PRIx16 "x" +# define PRIx32 "x" +# define PRIx64 "llx" + +# define PRIxLEAST8 "x" +# define PRIxLEAST16 "x" +# define PRIxLEAST32 "x" +# define PRIxLEAST64 "llx" + +# define PRIxFAST8 "x" +# define PRIxFAST16 "x" +# define PRIxFAST32 "x" +# define PRIxFAST64 "llx" + +# define PRIxMAX "llx" +# define PRIxPTR "x" + +# define PRIX8 "X" +# define PRIX16 "X" +# define PRIX32 "X" +# define PRIX64 "llX" + +# define PRIXLEAST8 "X" +# define PRIXLEAST16 "X" +# define PRIXLEAST32 "X" +# define PRIXLEAST64 "llX" + +# define PRIXFAST8 "X" +# define PRIXFAST16 "X" +# define PRIXFAST32 "X" +# define PRIXFAST64 "llX" + +# define PRIXMAX "llX" +# define PRIXPTR "X" + +# define SCNd8 "hhd" +# define SCNd16 "hd" +# define SCNd32 "d" +# define SCNd64 "lld" + +# define SCNdLEAST8 "hhd" +# define SCNdLEAST16 "hd" +# define SCNdLEAST32 "d" +# define SCNdLEAST64 "lld" + +# define SCNdFAST8 "hhd" +# define SCNdFAST16 "hd" +# define SCNdFAST32 "d" +# define SCNdFAST64 "lld" + +# define SCNdMAX "lld" +# define SCNdPTR "d" + +# define SCNi8 "hhi" +# define SCNi16 "hi" +# define SCNi32 "i" +# define SCNi64 "lli" + +# define SCNiLEAST8 "hhi" +# define SCNiLEAST16 "hi" +# define SCNiLEAST32 "i" +# define SCNiLEAST64 "lli" + +# define SCNiFAST8 "hhi" +# define SCNiFAST16 "hi" +# define SCNiFAST32 "i" +# define SCNiFAST64 "lli" + +# define SCNiMAX "lli" +# define SCNiPTR "i" + +# define SCNo8 "hho" +# define SCNo16 "ho" +# define SCNo32 "o" +# define SCNo64 "llo" + +# define SCNoLEAST8 "hho" +# define SCNoLEAST16 "ho" +# define SCNoLEAST32 "o" +# define SCNoLEAST64 "llo" + +# define SCNoFAST8 "hho" +# define SCNoFAST16 "ho" +# define SCNoFAST32 "o" +# define SCNoFAST64 "llo" + +# define SCNoMAX "llo" +# define SCNoPTR "o" + +# define SCNu8 "hhu" +# define SCNu16 "hu" +# define SCNu32 "u" +# define SCNu64 "llu" + +# define SCNuLEAST8 "hhu" +# define SCNuLEAST16 "hu" +# define SCNuLEAST32 "u" +# define SCNuLEAST64 "llu" + +# define SCNuFAST8 "hhu" +# define SCNuFAST16 "hu" +# define SCNuFAST32 "u" +# define SCNuFAST64 "llu" + +# define SCNuMAX "llu" +# define SCNuPTR "u" + +# define SCNx8 "hhx" +# define SCNx16 "hx" +# define SCNx32 "x" +# define SCNx64 "llx" + +# define SCNxLEAST8 "hhx" +# define SCNxLEAST16 "hx" +# define SCNxLEAST32 "x" +# define SCNxLEAST64 "llx" + +# define SCNxFAST8 "hhx" +# define SCNxFAST16 "hx" +# define SCNxFAST32 "x" +# define SCNxFAST64 "llx" + +# define SCNxMAX "llx" +# define SCNxPTR "x" + +#endif + +#endif /* __ARCH_HC_INCLUDE_INTTYPES_H */ diff --git a/arch/mips/include/inttypes.h b/arch/mips/include/inttypes.h new file mode 100644 index 0000000000..81006c8eac --- /dev/null +++ b/arch/mips/include/inttypes.h @@ -0,0 +1,245 @@ +/**************************************************************************** + * arch/mips/include/inttypes.h + * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MIPS_INCLUDE_INTTYPES_H +#define __ARCH_MIPS_INCLUDE_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PRId8 "d" +#define PRId16 "d" +#define PRId32 "d" +#define PRId64 "lld" + +#define PRIdLEAST8 "d" +#define PRIdLEAST16 "d" +#define PRIdLEAST32 "d" +#define PRIdLEAST64 "lld" + +#define PRIdFAST8 "d" +#define PRIdFAST16 "d" +#define PRIdFAST32 "d" +#define PRIdFAST64 "lld" + +#define PRIdMAX "lld" +#define PRIdPTR "d" + +#define PRIi8 "i" +#define PRIi16 "i" +#define PRIi32 "i" +#define PRIi64 "lli" + +#define PRIiLEAST8 "i" +#define PRIiLEAST16 "i" +#define PRIiLEAST32 "i" +#define PRIiLEAST64 "lli" + +#define PRIiFAST8 "i" +#define PRIiFAST16 "i" +#define PRIiFAST32 "i" +#define PRIiFAST64 "lli" + +#define PRIiMAX "lli" +#define PRIiPTR "i" + +#define PRIo8 "o" +#define PRIo16 "o" +#define PRIo32 "o" +#define PRIo64 "llo" + +#define PRIoLEAST8 "o" +#define PRIoLEAST16 "o" +#define PRIoLEAST32 "o" +#define PRIoLEAST64 "llo" + +#define PRIoFAST8 "o" +#define PRIoFAST16 "o" +#define PRIoFAST32 "o" +#define PRIoFAST64 "llo" + +#define PRIoMAX "llo" +#define PRIoPTR "o" + +#define PRIu8 "u" +#define PRIu16 "u" +#define PRIu32 "u" +#define PRIu64 "llu" + +#define PRIuLEAST8 "u" +#define PRIuLEAST16 "u" +#define PRIuLEAST32 "u" +#define PRIuLEAST64 "llu" + +#define PRIuFAST8 "u" +#define PRIuFAST16 "u" +#define PRIuFAST32 "u" +#define PRIuFAST64 "llu" + +#define PRIuMAX "llu" +#define PRIuPTR "u" + +#define PRIx8 "x" +#define PRIx16 "x" +#define PRIx32 "x" +#define PRIx64 "llx" + +#define PRIxLEAST8 "x" +#define PRIxLEAST16 "x" +#define PRIxLEAST32 "x" +#define PRIxLEAST64 "llx" + +#define PRIxFAST8 "x" +#define PRIxFAST16 "x" +#define PRIxFAST32 "x" +#define PRIxFAST64 "llx" + +#define PRIxMAX "llx" +#define PRIxPTR "x" + +#define PRIX8 "X" +#define PRIX16 "X" +#define PRIX32 "X" +#define PRIX64 "llX" + +#define PRIXLEAST8 "X" +#define PRIXLEAST16 "X" +#define PRIXLEAST32 "X" +#define PRIXLEAST64 "llX" + +#define PRIXFAST8 "X" +#define PRIXFAST16 "X" +#define PRIXFAST32 "X" +#define PRIXFAST64 "llX" + +#define PRIXMAX "llX" +#define PRIXPTR "X" + +#define SCNd8 "hhd" +#define SCNd16 "hd" +#define SCNd32 "d" +#define SCNd64 "lld" + +#define SCNdLEAST8 "hhd" +#define SCNdLEAST16 "hd" +#define SCNdLEAST32 "d" +#define SCNdLEAST64 "lld" + +#define SCNdFAST8 "hhd" +#define SCNdFAST16 "hd" +#define SCNdFAST32 "d" +#define SCNdFAST64 "lld" + +#define SCNdMAX "lld" +#define SCNdPTR "d" + +#define SCNi8 "hhi" +#define SCNi16 "hi" +#define SCNi32 "i" +#define SCNi64 "lli" + +#define SCNiLEAST8 "hhi" +#define SCNiLEAST16 "hi" +#define SCNiLEAST32 "i" +#define SCNiLEAST64 "lli" + +#define SCNiFAST8 "hhi" +#define SCNiFAST16 "hi" +#define SCNiFAST32 "i" +#define SCNiFAST64 "lli" + +#define SCNiMAX "lli" +#define SCNiPTR "i" + +#define SCNo8 "hho" +#define SCNo16 "ho" +#define SCNo32 "o" +#define SCNo64 "llo" + +#define SCNoLEAST8 "hho" +#define SCNoLEAST16 "ho" +#define SCNoLEAST32 "o" +#define SCNoLEAST64 "llo" + +#define SCNoFAST8 "hho" +#define SCNoFAST16 "ho" +#define SCNoFAST32 "o" +#define SCNoFAST64 "llo" + +#define SCNoMAX "llo" +#define SCNoPTR "o" + +#define SCNu8 "hhu" +#define SCNu16 "hu" +#define SCNu32 "u" +#define SCNu64 "llu" + +#define SCNuLEAST8 "hhu" +#define SCNuLEAST16 "hu" +#define SCNuLEAST32 "u" +#define SCNuLEAST64 "llu" + +#define SCNuFAST8 "hhu" +#define SCNuFAST16 "hu" +#define SCNuFAST32 "u" +#define SCNuFAST64 "llu" + +#define SCNuMAX "llu" +#define SCNuPTR "u" + +#define SCNx8 "hhx" +#define SCNx16 "hx" +#define SCNx32 "x" +#define SCNx64 "llx" + +#define SCNxLEAST8 "hhx" +#define SCNxLEAST16 "hx" +#define SCNxLEAST32 "x" +#define SCNxLEAST64 "llx" + +#define SCNxFAST8 "hhx" +#define SCNxFAST16 "hx" +#define SCNxFAST32 "x" +#define SCNxFAST64 "llx" + +#define SCNxMAX "llx" +#define SCNxPTR "x" + +#endif /* __ARCH_MIPS_INCLUDE_INTTYPES_H */ diff --git a/arch/renesas/include/inttypes.h b/arch/renesas/include/inttypes.h new file mode 100644 index 0000000000..241a7dafe6 --- /dev/null +++ b/arch/renesas/include/inttypes.h @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/renesas/include/inttypes.h + * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RENESAS_INCLUDE_INTTYPES_H +#define __ARCH_RENESAS_INCLUDE_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_RENESAS_INCLUDE_INTTYPES_H */ diff --git a/arch/renesas/include/m16c/inttypes.h b/arch/renesas/include/m16c/inttypes.h new file mode 100644 index 0000000000..9850184734 --- /dev/null +++ b/arch/renesas/include/m16c/inttypes.h @@ -0,0 +1,245 @@ +/**************************************************************************** + * arch/renesas/include/m16c/inttypes.h + * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_AVR_INCLUDE_M16C_INTTYPES_H +#define __ARCH_AVR_INCLUDE_M16C_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PRId8 "d" +#define PRId16 "d" +#define PRId32 "ld" +#define PRId64 "lld" + +#define PRIdLEAST8 "d" +#define PRIdLEAST16 "d" +#define PRIdLEAST32 "ld" +#define PRIdLEAST64 "lld" + +#define PRIdFAST8 "d" +#define PRIdFAST16 "d" +#define PRIdFAST32 "ld" +#define PRIdFAST64 "lld" + +#define PRIdMAX "lld" +#define PRIdPTR "d" + +#define PRIi8 "i" +#define PRIi16 "i" +#define PRIi32 "li" +#define PRIi64 "lli" + +#define PRIiLEAST8 "i" +#define PRIiLEAST16 "i" +#define PRIiLEAST32 "li" +#define PRIiLEAST64 "lli" + +#define PRIiFAST8 "i" +#define PRIiFAST16 "i" +#define PRIiFAST32 "li" +#define PRIiFAST64 "lli" + +#define PRIiMAX "lli" +#define PRIiPTR "i" + +#define PRIo8 "o" +#define PRIo16 "o" +#define PRIo32 "lo" +#define PRIo64 "llo" + +#define PRIoLEAST8 "o" +#define PRIoLEAST16 "o" +#define PRIoLEAST32 "lo" +#define PRIoLEAST64 "llo" + +#define PRIoFAST8 "o" +#define PRIoFAST16 "o" +#define PRIoFAST32 "lo" +#define PRIoFAST64 "llo" + +#define PRIoMAX "llo" +#define PRIoPTR "o" + +#define PRIu8 "u" +#define PRIu16 "u" +#define PRIu32 "lu" +#define PRIu64 "llu" + +#define PRIuLEAST8 "u" +#define PRIuLEAST16 "u" +#define PRIuLEAST32 "lu" +#define PRIuLEAST64 "llu" + +#define PRIuFAST8 "u" +#define PRIuFAST16 "u" +#define PRIuFAST32 "lu" +#define PRIuFAST64 "llu" + +#define PRIuMAX "llu" +#define PRIuPTR "u" + +#define PRIx8 "x" +#define PRIx16 "x" +#define PRIx32 "lx" +#define PRIx64 "llx" + +#define PRIxLEAST8 "x" +#define PRIxLEAST16 "x" +#define PRIxLEAST32 "lx" +#define PRIxLEAST64 "llx" + +#define PRIxFAST8 "x" +#define PRIxFAST16 "x" +#define PRIxFAST32 "lx" +#define PRIxFAST64 "llx" + +#define PRIxMAX "llx" +#define PRIxPTR "x" + +#define PRIX8 "X" +#define PRIX16 "X" +#define PRIX32 "lX" +#define PRIX64 "llX" + +#define PRIXLEAST8 "X" +#define PRIXLEAST16 "X" +#define PRIXLEAST32 "lX" +#define PRIXLEAST64 "llX" + +#define PRIXFAST8 "X" +#define PRIXFAST16 "X" +#define PRIXFAST32 "lX" +#define PRIXFAST64 "llX" + +#define PRIXMAX "llX" +#define PRIXPTR "X" + +#define SCNd8 "hhd" +#define SCNd16 "d" +#define SCNd32 "ld" +#define SCNd64 "lld" + +#define SCNdLEAST8 "hhd" +#define SCNdLEAST16 "d" +#define SCNdLEAST32 "ld" +#define SCNdLEAST64 "lld" + +#define SCNdFAST8 "hhd" +#define SCNdFAST16 "d" +#define SCNdFAST32 "ld" +#define SCNdFAST64 "lld" + +#define SCNdMAX "lld" +#define SCNdPTR "d" + +#define SCNi8 "hhi" +#define SCNi16 "i" +#define SCNi32 "li" +#define SCNi64 "lli" + +#define SCNiLEAST8 "hhi" +#define SCNiLEAST16 "i" +#define SCNiLEAST32 "li" +#define SCNiLEAST64 "lli" + +#define SCNiFAST8 "hhi" +#define SCNiFAST16 "i" +#define SCNiFAST32 "li" +#define SCNiFAST64 "lli" + +#define SCNiMAX "lli" +#define SCNiPTR "i" + +#define SCNo8 "hho" +#define SCNo16 "o" +#define SCNo32 "lo" +#define SCNo64 "llo" + +#define SCNoLEAST8 "hho" +#define SCNoLEAST16 "o" +#define SCNoLEAST32 "lo" +#define SCNoLEAST64 "llo" + +#define SCNoFAST8 "hho" +#define SCNoFAST16 "o" +#define SCNoFAST32 "lo" +#define SCNoFAST64 "llo" + +#define SCNoMAX "llo" +#define SCNoPTR "o" + +#define SCNu8 "hhu" +#define SCNu16 "u" +#define SCNu32 "lu" +#define SCNu64 "llu" + +#define SCNuLEAST8 "hhu" +#define SCNuLEAST16 "u" +#define SCNuLEAST32 "lu" +#define SCNuLEAST64 "llu" + +#define SCNuFAST8 "hhu" +#define SCNuFAST16 "u" +#define SCNuFAST32 "lu" +#define SCNuFAST64 "llu" + +#define SCNuMAX "llu" +#define SCNuPTR "u" + +#define SCNx8 "hhx" +#define SCNx16 "x" +#define SCNx32 "lx" +#define SCNx64 "llx" + +#define SCNxLEAST8 "hhx" +#define SCNxLEAST16 "x" +#define SCNxLEAST32 "lx" +#define SCNxLEAST64 "llx" + +#define SCNxFAST8 "hhx" +#define SCNxFAST16 "x" +#define SCNxFAST32 "lx" +#define SCNxFAST64 "llx" + +#define SCNxMAX "llx" +#define SCNxPTR "x" + +#endif /* __ARCH_AVR_INCLUDE_M16C_INTTYPES_H */ diff --git a/arch/renesas/include/sh1/inttypes.h b/arch/renesas/include/sh1/inttypes.h new file mode 100644 index 0000000000..e2ceee2e5b --- /dev/null +++ b/arch/renesas/include/sh1/inttypes.h @@ -0,0 +1,245 @@ +/**************************************************************************** + * arch/renesas/include/sh1/inttypes.h + * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_AVR_INCLUDE_SH1_INTTYPES_H +#define __ARCH_AVR_INCLUDE_SH1_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PRId8 "d" +#define PRId16 "d" +#define PRId32 "d" +#define PRId64 "lld" + +#define PRIdLEAST8 "d" +#define PRIdLEAST16 "d" +#define PRIdLEAST32 "d" +#define PRIdLEAST64 "lld" + +#define PRIdFAST8 "d" +#define PRIdFAST16 "d" +#define PRIdFAST32 "d" +#define PRIdFAST64 "lld" + +#define PRIdMAX "lld" +#define PRIdPTR "d" + +#define PRIi8 "i" +#define PRIi16 "i" +#define PRIi32 "i" +#define PRIi64 "lli" + +#define PRIiLEAST8 "i" +#define PRIiLEAST16 "i" +#define PRIiLEAST32 "i" +#define PRIiLEAST64 "lli" + +#define PRIiFAST8 "i" +#define PRIiFAST16 "i" +#define PRIiFAST32 "i" +#define PRIiFAST64 "lli" + +#define PRIiMAX "lli" +#define PRIiPTR "i" + +#define PRIo8 "o" +#define PRIo16 "o" +#define PRIo32 "o" +#define PRIo64 "llo" + +#define PRIoLEAST8 "o" +#define PRIoLEAST16 "o" +#define PRIoLEAST32 "o" +#define PRIoLEAST64 "llo" + +#define PRIoFAST8 "o" +#define PRIoFAST16 "o" +#define PRIoFAST32 "o" +#define PRIoFAST64 "llo" + +#define PRIoMAX "llo" +#define PRIoPTR "o" + +#define PRIu8 "u" +#define PRIu16 "u" +#define PRIu32 "u" +#define PRIu64 "llu" + +#define PRIuLEAST8 "u" +#define PRIuLEAST16 "u" +#define PRIuLEAST32 "u" +#define PRIuLEAST64 "llu" + +#define PRIuFAST8 "u" +#define PRIuFAST16 "u" +#define PRIuFAST32 "u" +#define PRIuFAST64 "llu" + +#define PRIuMAX "llu" +#define PRIuPTR "u" + +#define PRIx8 "x" +#define PRIx16 "x" +#define PRIx32 "x" +#define PRIx64 "llx" + +#define PRIxLEAST8 "x" +#define PRIxLEAST16 "x" +#define PRIxLEAST32 "x" +#define PRIxLEAST64 "llx" + +#define PRIxFAST8 "x" +#define PRIxFAST16 "x" +#define PRIxFAST32 "x" +#define PRIxFAST64 "llx" + +#define PRIxMAX "llx" +#define PRIxPTR "x" + +#define PRIX8 "X" +#define PRIX16 "X" +#define PRIX32 "X" +#define PRIX64 "llX" + +#define PRIXLEAST8 "X" +#define PRIXLEAST16 "X" +#define PRIXLEAST32 "X" +#define PRIXLEAST64 "llX" + +#define PRIXFAST8 "X" +#define PRIXFAST16 "X" +#define PRIXFAST32 "X" +#define PRIXFAST64 "llX" + +#define PRIXMAX "llX" +#define PRIXPTR "X" + +#define SCNd8 "hhd" +#define SCNd16 "hd" +#define SCNd32 "d" +#define SCNd64 "lld" + +#define SCNdLEAST8 "hhd" +#define SCNdLEAST16 "hd" +#define SCNdLEAST32 "d" +#define SCNdLEAST64 "lld" + +#define SCNdFAST8 "hhd" +#define SCNdFAST16 "hd" +#define SCNdFAST32 "d" +#define SCNdFAST64 "lld" + +#define SCNdMAX "lld" +#define SCNdPTR "d" + +#define SCNi8 "hhi" +#define SCNi16 "hi" +#define SCNi32 "i" +#define SCNi64 "lli" + +#define SCNiLEAST8 "hhi" +#define SCNiLEAST16 "hi" +#define SCNiLEAST32 "i" +#define SCNiLEAST64 "lli" + +#define SCNiFAST8 "hhi" +#define SCNiFAST16 "hi" +#define SCNiFAST32 "i" +#define SCNiFAST64 "lli" + +#define SCNiMAX "lli" +#define SCNiPTR "i" + +#define SCNo8 "hho" +#define SCNo16 "ho" +#define SCNo32 "o" +#define SCNo64 "llo" + +#define SCNoLEAST8 "hho" +#define SCNoLEAST16 "ho" +#define SCNoLEAST32 "o" +#define SCNoLEAST64 "llo" + +#define SCNoFAST8 "hho" +#define SCNoFAST16 "ho" +#define SCNoFAST32 "o" +#define SCNoFAST64 "llo" + +#define SCNoMAX "llo" +#define SCNoPTR "o" + +#define SCNu8 "hhu" +#define SCNu16 "hu" +#define SCNu32 "u" +#define SCNu64 "llu" + +#define SCNuLEAST8 "hhu" +#define SCNuLEAST16 "hu" +#define SCNuLEAST32 "u" +#define SCNuLEAST64 "llu" + +#define SCNuFAST8 "hhu" +#define SCNuFAST16 "hu" +#define SCNuFAST32 "u" +#define SCNuFAST64 "llu" + +#define SCNuMAX "llu" +#define SCNuPTR "u" + +#define SCNx8 "hhx" +#define SCNx16 "hx" +#define SCNx32 "x" +#define SCNx64 "llx" + +#define SCNxLEAST8 "hhx" +#define SCNxLEAST16 "hx" +#define SCNxLEAST32 "x" +#define SCNxLEAST64 "llx" + +#define SCNxFAST8 "hhx" +#define SCNxFAST16 "hx" +#define SCNxFAST32 "x" +#define SCNxFAST64 "llx" + +#define SCNxMAX "llx" +#define SCNxPTR "x" + +#endif /* __ARCH_AVR_INCLUDE_SH1_INTTYPES_H */ diff --git a/arch/rgmp/include/inttypes.h b/arch/rgmp/include/inttypes.h new file mode 100644 index 0000000000..4d3d40aef2 --- /dev/null +++ b/arch/rgmp/include/inttypes.h @@ -0,0 +1,245 @@ +/**************************************************************************** + * arch/rgmp/include/inttypes.h + * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RGMP_INCLUDE_INTTYPES_H +#define __ARCH_RGMP_INCLUDE_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PRId8 "d" +#define PRId16 "d" +#define PRId32 "d" +#define PRId64 "lld" + +#define PRIdLEAST8 "d" +#define PRIdLEAST16 "d" +#define PRIdLEAST32 "d" +#define PRIdLEAST64 "lld" + +#define PRIdFAST8 "d" +#define PRIdFAST16 "d" +#define PRIdFAST32 "d" +#define PRIdFAST64 "lld" + +#define PRIdMAX "lld" +#define PRIdPTR "d" + +#define PRIi8 "i" +#define PRIi16 "i" +#define PRIi32 "i" +#define PRIi64 "lli" + +#define PRIiLEAST8 "i" +#define PRIiLEAST16 "i" +#define PRIiLEAST32 "i" +#define PRIiLEAST64 "lli" + +#define PRIiFAST8 "i" +#define PRIiFAST16 "i" +#define PRIiFAST32 "i" +#define PRIiFAST64 "lli" + +#define PRIiMAX "lli" +#define PRIiPTR "i" + +#define PRIo8 "o" +#define PRIo16 "o" +#define PRIo32 "o" +#define PRIo64 "llo" + +#define PRIoLEAST8 "o" +#define PRIoLEAST16 "o" +#define PRIoLEAST32 "o" +#define PRIoLEAST64 "llo" + +#define PRIoFAST8 "o" +#define PRIoFAST16 "o" +#define PRIoFAST32 "o" +#define PRIoFAST64 "llo" + +#define PRIoMAX "llo" +#define PRIoPTR "o" + +#define PRIu8 "u" +#define PRIu16 "u" +#define PRIu32 "u" +#define PRIu64 "llu" + +#define PRIuLEAST8 "u" +#define PRIuLEAST16 "u" +#define PRIuLEAST32 "u" +#define PRIuLEAST64 "llu" + +#define PRIuFAST8 "u" +#define PRIuFAST16 "u" +#define PRIuFAST32 "u" +#define PRIuFAST64 "llu" + +#define PRIuMAX "llu" +#define PRIuPTR "u" + +#define PRIx8 "x" +#define PRIx16 "x" +#define PRIx32 "x" +#define PRIx64 "llx" + +#define PRIxLEAST8 "x" +#define PRIxLEAST16 "x" +#define PRIxLEAST32 "x" +#define PRIxLEAST64 "llx" + +#define PRIxFAST8 "x" +#define PRIxFAST16 "x" +#define PRIxFAST32 "x" +#define PRIxFAST64 "llx" + +#define PRIxMAX "llx" +#define PRIxPTR "x" + +#define PRIX8 "X" +#define PRIX16 "X" +#define PRIX32 "X" +#define PRIX64 "llX" + +#define PRIXLEAST8 "X" +#define PRIXLEAST16 "X" +#define PRIXLEAST32 "X" +#define PRIXLEAST64 "llX" + +#define PRIXFAST8 "X" +#define PRIXFAST16 "X" +#define PRIXFAST32 "X" +#define PRIXFAST64 "llX" + +#define PRIXMAX "llX" +#define PRIXPTR "X" + +#define SCNd8 "hhd" +#define SCNd16 "hd" +#define SCNd32 "d" +#define SCNd64 "lld" + +#define SCNdLEAST8 "hhd" +#define SCNdLEAST16 "hd" +#define SCNdLEAST32 "d" +#define SCNdLEAST64 "lld" + +#define SCNdFAST8 "hhd" +#define SCNdFAST16 "hd" +#define SCNdFAST32 "d" +#define SCNdFAST64 "lld" + +#define SCNdMAX "lld" +#define SCNdPTR "d" + +#define SCNi8 "hhi" +#define SCNi16 "hi" +#define SCNi32 "i" +#define SCNi64 "lli" + +#define SCNiLEAST8 "hhi" +#define SCNiLEAST16 "hi" +#define SCNiLEAST32 "i" +#define SCNiLEAST64 "lli" + +#define SCNiFAST8 "hhi" +#define SCNiFAST16 "hi" +#define SCNiFAST32 "i" +#define SCNiFAST64 "lli" + +#define SCNiMAX "lli" +#define SCNiPTR "i" + +#define SCNo8 "hho" +#define SCNo16 "ho" +#define SCNo32 "o" +#define SCNo64 "llo" + +#define SCNoLEAST8 "hho" +#define SCNoLEAST16 "ho" +#define SCNoLEAST32 "o" +#define SCNoLEAST64 "llo" + +#define SCNoFAST8 "hho" +#define SCNoFAST16 "ho" +#define SCNoFAST32 "o" +#define SCNoFAST64 "llo" + +#define SCNoMAX "llo" +#define SCNoPTR "o" + +#define SCNu8 "hhu" +#define SCNu16 "hu" +#define SCNu32 "u" +#define SCNu64 "llu" + +#define SCNuLEAST8 "hhu" +#define SCNuLEAST16 "hu" +#define SCNuLEAST32 "u" +#define SCNuLEAST64 "llu" + +#define SCNuFAST8 "hhu" +#define SCNuFAST16 "hu" +#define SCNuFAST32 "u" +#define SCNuFAST64 "llu" + +#define SCNuMAX "llu" +#define SCNuPTR "u" + +#define SCNx8 "hhx" +#define SCNx16 "hx" +#define SCNx32 "x" +#define SCNx64 "llx" + +#define SCNxLEAST8 "hhx" +#define SCNxLEAST16 "hx" +#define SCNxLEAST32 "x" +#define SCNxLEAST64 "llx" + +#define SCNxFAST8 "hhx" +#define SCNxFAST16 "hx" +#define SCNxFAST32 "x" +#define SCNxFAST64 "llx" + +#define SCNxMAX "llx" +#define SCNxPTR "x" + +#endif /* __ARCH_RGMP_INCLUDE_INTTYPES_H */ diff --git a/arch/risc-v/include/inttypes.h b/arch/risc-v/include/inttypes.h new file mode 100644 index 0000000000..a87bf6b5b3 --- /dev/null +++ b/arch/risc-v/include/inttypes.h @@ -0,0 +1,245 @@ +/**************************************************************************** + * arch/risc-v/include/inttypes.h + * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_INTTYPES_H +#define __ARCH_RISCV_INCLUDE_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PRId8 "d" +#define PRId16 "d" +#define PRId32 "d" +#define PRId64 "lld" + +#define PRIdLEAST8 "d" +#define PRIdLEAST16 "d" +#define PRIdLEAST32 "d" +#define PRIdLEAST64 "lld" + +#define PRIdFAST8 "d" +#define PRIdFAST16 "d" +#define PRIdFAST32 "d" +#define PRIdFAST64 "lld" + +#define PRIdMAX "lld" +#define PRIdPTR "d" + +#define PRIi8 "i" +#define PRIi16 "i" +#define PRIi32 "i" +#define PRIi64 "lli" + +#define PRIiLEAST8 "i" +#define PRIiLEAST16 "i" +#define PRIiLEAST32 "i" +#define PRIiLEAST64 "lli" + +#define PRIiFAST8 "i" +#define PRIiFAST16 "i" +#define PRIiFAST32 "i" +#define PRIiFAST64 "lli" + +#define PRIiMAX "lli" +#define PRIiPTR "i" + +#define PRIo8 "o" +#define PRIo16 "o" +#define PRIo32 "o" +#define PRIo64 "llo" + +#define PRIoLEAST8 "o" +#define PRIoLEAST16 "o" +#define PRIoLEAST32 "o" +#define PRIoLEAST64 "llo" + +#define PRIoFAST8 "o" +#define PRIoFAST16 "o" +#define PRIoFAST32 "o" +#define PRIoFAST64 "llo" + +#define PRIoMAX "llo" +#define PRIoPTR "o" + +#define PRIu8 "u" +#define PRIu16 "u" +#define PRIu32 "u" +#define PRIu64 "llu" + +#define PRIuLEAST8 "u" +#define PRIuLEAST16 "u" +#define PRIuLEAST32 "u" +#define PRIuLEAST64 "llu" + +#define PRIuFAST8 "u" +#define PRIuFAST16 "u" +#define PRIuFAST32 "u" +#define PRIuFAST64 "llu" + +#define PRIuMAX "llu" +#define PRIuPTR "u" + +#define PRIx8 "x" +#define PRIx16 "x" +#define PRIx32 "x" +#define PRIx64 "llx" + +#define PRIxLEAST8 "x" +#define PRIxLEAST16 "x" +#define PRIxLEAST32 "x" +#define PRIxLEAST64 "llx" + +#define PRIxFAST8 "x" +#define PRIxFAST16 "x" +#define PRIxFAST32 "x" +#define PRIxFAST64 "llx" + +#define PRIxMAX "llx" +#define PRIxPTR "x" + +#define PRIX8 "X" +#define PRIX16 "X" +#define PRIX32 "X" +#define PRIX64 "llX" + +#define PRIXLEAST8 "X" +#define PRIXLEAST16 "X" +#define PRIXLEAST32 "X" +#define PRIXLEAST64 "llX" + +#define PRIXFAST8 "X" +#define PRIXFAST16 "X" +#define PRIXFAST32 "X" +#define PRIXFAST64 "llX" + +#define PRIXMAX "llX" +#define PRIXPTR "X" + +#define SCNd8 "hhd" +#define SCNd16 "hd" +#define SCNd32 "d" +#define SCNd64 "lld" + +#define SCNdLEAST8 "hhd" +#define SCNdLEAST16 "hd" +#define SCNdLEAST32 "d" +#define SCNdLEAST64 "lld" + +#define SCNdFAST8 "hhd" +#define SCNdFAST16 "hd" +#define SCNdFAST32 "d" +#define SCNdFAST64 "lld" + +#define SCNdMAX "lld" +#define SCNdPTR "d" + +#define SCNi8 "hhi" +#define SCNi16 "hi" +#define SCNi32 "i" +#define SCNi64 "lli" + +#define SCNiLEAST8 "hhi" +#define SCNiLEAST16 "hi" +#define SCNiLEAST32 "i" +#define SCNiLEAST64 "lli" + +#define SCNiFAST8 "hhi" +#define SCNiFAST16 "hi" +#define SCNiFAST32 "i" +#define SCNiFAST64 "lli" + +#define SCNiMAX "lli" +#define SCNiPTR "i" + +#define SCNo8 "hho" +#define SCNo16 "ho" +#define SCNo32 "o" +#define SCNo64 "llo" + +#define SCNoLEAST8 "hho" +#define SCNoLEAST16 "ho" +#define SCNoLEAST32 "o" +#define SCNoLEAST64 "llo" + +#define SCNoFAST8 "hho" +#define SCNoFAST16 "ho" +#define SCNoFAST32 "o" +#define SCNoFAST64 "llo" + +#define SCNoMAX "llo" +#define SCNoPTR "o" + +#define SCNu8 "hhu" +#define SCNu16 "hu" +#define SCNu32 "u" +#define SCNu64 "llu" + +#define SCNuLEAST8 "hhu" +#define SCNuLEAST16 "hu" +#define SCNuLEAST32 "u" +#define SCNuLEAST64 "llu" + +#define SCNuFAST8 "hhu" +#define SCNuFAST16 "hu" +#define SCNuFAST32 "u" +#define SCNuFAST64 "llu" + +#define SCNuMAX "llu" +#define SCNuPTR "u" + +#define SCNx8 "hhx" +#define SCNx16 "hx" +#define SCNx32 "x" +#define SCNx64 "llx" + +#define SCNxLEAST8 "hhx" +#define SCNxLEAST16 "hx" +#define SCNxLEAST32 "x" +#define SCNxLEAST64 "llx" + +#define SCNxFAST8 "hhx" +#define SCNxFAST16 "hx" +#define SCNxFAST32 "x" +#define SCNxFAST64 "llx" + +#define SCNxMAX "llx" +#define SCNxPTR "x" + +#endif /* __ARCH_RISCV_INCLUDE_INTTYPES_H */ diff --git a/arch/sim/include/inttypes.h b/arch/sim/include/inttypes.h new file mode 100644 index 0000000000..6fcf9a56e7 --- /dev/null +++ b/arch/sim/include/inttypes.h @@ -0,0 +1,449 @@ +/**************************************************************************** + * arch/sim/include/inttypes.h + * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_SIM_INCLUDE_INTTYPES_H +#define __ARCH_SIM_INCLUDE_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_HOST_X86_64) && !defined(CONFIG_SIM_M32) + +# define PRId8 "d" +# define PRId16 "d" +# define PRId32 "d" +# define PRId64 "lld" + +# define PRIdLEAST8 "d" +# define PRIdLEAST16 "d" +# define PRIdLEAST32 "d" +# define PRIdLEAST64 "lld" + +# define PRIdFAST8 "d" +# define PRIdFAST16 "d" +# define PRIdFAST32 "d" +# define PRIdFAST64 "lld" + +# define PRIdMAX "lld" +# define PRIdPTR "lld" + +# define PRIi8 "i" +# define PRIi16 "i" +# define PRIi32 "i" +# define PRIi64 "lli" + +# define PRIiLEAST8 "i" +# define PRIiLEAST16 "i" +# define PRIiLEAST32 "i" +# define PRIiLEAST64 "lli" + +# define PRIiFAST8 "i" +# define PRIiFAST16 "i" +# define PRIiFAST32 "i" +# define PRIiFAST64 "lli" + +# define PRIiMAX "lli" +# define PRIiPTR "lli" + +# define PRIo8 "o" +# define PRIo16 "o" +# define PRIo32 "o" +# define PRIo64 "llo" + +# define PRIoLEAST8 "o" +# define PRIoLEAST16 "o" +# define PRIoLEAST32 "o" +# define PRIoLEAST64 "llo" + +# define PRIoFAST8 "o" +# define PRIoFAST16 "o" +# define PRIoFAST32 "o" +# define PRIoFAST64 "llo" + +# define PRIoMAX "llo" +# define PRIoPTR "llo" + +# define PRIu8 "u" +# define PRIu16 "u" +# define PRIu32 "u" +# define PRIu64 "llu" + +# define PRIuLEAST8 "u" +# define PRIuLEAST16 "u" +# define PRIuLEAST32 "u" +# define PRIuLEAST64 "llu" + +# define PRIuFAST8 "u" +# define PRIuFAST16 "u" +# define PRIuFAST32 "u" +# define PRIuFAST64 "llu" + +# define PRIuMAX "llu" +# define PRIuPTR "llu" + +# define PRIx8 "x" +# define PRIx16 "x" +# define PRIx32 "x" +# define PRIx64 "llx" + +# define PRIxLEAST8 "x" +# define PRIxLEAST16 "x" +# define PRIxLEAST32 "x" +# define PRIxLEAST64 "llx" + +# define PRIxFAST8 "x" +# define PRIxFAST16 "x" +# define PRIxFAST32 "x" +# define PRIxFAST64 "llx" + +# define PRIxMAX "llx" +# define PRIxPTR "llx" + +# define PRIX8 "X" +# define PRIX16 "X" +# define PRIX32 "X" +# define PRIX64 "llX" + +# define PRIXLEAST8 "X" +# define PRIXLEAST16 "X" +# define PRIXLEAST32 "X" +# define PRIXLEAST64 "llX" + +# define PRIXFAST8 "X" +# define PRIXFAST16 "X" +# define PRIXFAST32 "X" +# define PRIXFAST64 "llX" + +# define PRIXMAX "llX" +# define PRIXPTR "llX" + +# define SCNd8 "hhd" +# define SCNd16 "hd" +# define SCNd32 "d" +# define SCNd64 "lld" + +# define SCNdLEAST8 "hhd" +# define SCNdLEAST16 "hd" +# define SCNdLEAST32 "d" +# define SCNdLEAST64 "lld" + +# define SCNdFAST8 "hhd" +# define SCNdFAST16 "hd" +# define SCNdFAST32 "d" +# define SCNdFAST64 "lld" + +# define SCNdMAX "lld" +# define SCNdPTR "lld" + +# define SCNi8 "hhi" +# define SCNi16 "hi" +# define SCNi32 "i" +# define SCNi64 "lli" + +# define SCNiLEAST8 "hhi" +# define SCNiLEAST16 "hi" +# define SCNiLEAST32 "i" +# define SCNiLEAST64 "lli" + +# define SCNiFAST8 "hhi" +# define SCNiFAST16 "hi" +# define SCNiFAST32 "i" +# define SCNiFAST64 "lli" + +# define SCNiMAX "lli" +# define SCNiPTR "lli" + +# define SCNo8 "hho" +# define SCNo16 "ho" +# define SCNo32 "o" +# define SCNo64 "llo" + +# define SCNoLEAST8 "hho" +# define SCNoLEAST16 "ho" +# define SCNoLEAST32 "o" +# define SCNoLEAST64 "llo" + +# define SCNoFAST8 "hho" +# define SCNoFAST16 "ho" +# define SCNoFAST32 "o" +# define SCNoFAST64 "llo" + +# define SCNoMAX "llo" +# define SCNoPTR "llo" + +# define SCNu8 "hhu" +# define SCNu16 "hu" +# define SCNu32 "u" +# define SCNu64 "llu" + +# define SCNuLEAST8 "hhu" +# define SCNuLEAST16 "hu" +# define SCNuLEAST32 "u" +# define SCNuLEAST64 "llu" + +# define SCNuFAST8 "hhu" +# define SCNuFAST16 "hu" +# define SCNuFAST32 "u" +# define SCNuFAST64 "llu" + +# define SCNuMAX "llu" +# define SCNuPTR "llu" + +# define SCNx8 "hhx" +# define SCNx16 "hx" +# define SCNx32 "x" +# define SCNx64 "llx" + +# define SCNxLEAST8 "hhx" +# define SCNxLEAST16 "hx" +# define SCNxLEAST32 "x" +# define SCNxLEAST64 "llx" + +# define SCNxFAST8 "hhx" +# define SCNxFAST16 "hx" +# define SCNxFAST32 "x" +# define SCNxFAST64 "llx" + +# define SCNxMAX "llx" +# define SCNxPTR "llx" + +#else + +# define PRId8 "d" +# define PRId16 "d" +# define PRId32 "d" +# define PRId64 "lld" + +# define PRIdLEAST8 "d" +# define PRIdLEAST16 "d" +# define PRIdLEAST32 "d" +# define PRIdLEAST64 "lld" + +# define PRIdFAST8 "d" +# define PRIdFAST16 "d" +# define PRIdFAST32 "d" +# define PRIdFAST64 "lld" + +# define PRIdMAX "lld" +# define PRIdPTR "d" + +# define PRIi8 "i" +# define PRIi16 "i" +# define PRIi32 "i" +# define PRIi64 "lli" + +# define PRIiLEAST8 "i" +# define PRIiLEAST16 "i" +# define PRIiLEAST32 "i" +# define PRIiLEAST64 "lli" + +# define PRIiFAST8 "i" +# define PRIiFAST16 "i" +# define PRIiFAST32 "i" +# define PRIiFAST64 "lli" + +# define PRIiMAX "lli" +# define PRIiPTR "i" + +# define PRIo8 "o" +# define PRIo16 "o" +# define PRIo32 "o" +# define PRIo64 "llo" + +# define PRIoLEAST8 "o" +# define PRIoLEAST16 "o" +# define PRIoLEAST32 "o" +# define PRIoLEAST64 "llo" + +# define PRIoFAST8 "o" +# define PRIoFAST16 "o" +# define PRIoFAST32 "o" +# define PRIoFAST64 "llo" + +# define PRIoMAX "llo" +# define PRIoPTR "o" + +# define PRIu8 "u" +# define PRIu16 "u" +# define PRIu32 "u" +# define PRIu64 "llu" + +# define PRIuLEAST8 "u" +# define PRIuLEAST16 "u" +# define PRIuLEAST32 "u" +# define PRIuLEAST64 "llu" + +# define PRIuFAST8 "u" +# define PRIuFAST16 "u" +# define PRIuFAST32 "u" +# define PRIuFAST64 "llu" + +# define PRIuMAX "llu" +# define PRIuPTR "u" + +# define PRIx8 "x" +# define PRIx16 "x" +# define PRIx32 "x" +# define PRIx64 "llx" + +# define PRIxLEAST8 "x" +# define PRIxLEAST16 "x" +# define PRIxLEAST32 "x" +# define PRIxLEAST64 "llx" + +# define PRIxFAST8 "x" +# define PRIxFAST16 "x" +# define PRIxFAST32 "x" +# define PRIxFAST64 "llx" + +# define PRIxMAX "llx" +# define PRIxPTR "x" + +# define PRIX8 "X" +# define PRIX16 "X" +# define PRIX32 "X" +# define PRIX64 "llX" + +# define PRIXLEAST8 "X" +# define PRIXLEAST16 "X" +# define PRIXLEAST32 "X" +# define PRIXLEAST64 "llX" + +# define PRIXFAST8 "X" +# define PRIXFAST16 "X" +# define PRIXFAST32 "X" +# define PRIXFAST64 "llX" + +# define PRIXMAX "llX" +# define PRIXPTR "X" + +# define SCNd8 "hhd" +# define SCNd16 "hd" +# define SCNd32 "d" +# define SCNd64 "lld" + +# define SCNdLEAST8 "hhd" +# define SCNdLEAST16 "hd" +# define SCNdLEAST32 "d" +# define SCNdLEAST64 "lld" + +# define SCNdFAST8 "hhd" +# define SCNdFAST16 "hd" +# define SCNdFAST32 "d" +# define SCNdFAST64 "lld" + +# define SCNdMAX "lld" +# define SCNdPTR "d" + +# define SCNi8 "hhi" +# define SCNi16 "hi" +# define SCNi32 "i" +# define SCNi64 "lli" + +# define SCNiLEAST8 "hhi" +# define SCNiLEAST16 "hi" +# define SCNiLEAST32 "i" +# define SCNiLEAST64 "lli" + +# define SCNiFAST8 "hhi" +# define SCNiFAST16 "hi" +# define SCNiFAST32 "i" +# define SCNiFAST64 "lli" + +# define SCNiMAX "lli" +# define SCNiPTR "i" + +# define SCNo8 "hho" +# define SCNo16 "ho" +# define SCNo32 "o" +# define SCNo64 "llo" + +# define SCNoLEAST8 "hho" +# define SCNoLEAST16 "ho" +# define SCNoLEAST32 "o" +# define SCNoLEAST64 "llo" + +# define SCNoFAST8 "hho" +# define SCNoFAST16 "ho" +# define SCNoFAST32 "o" +# define SCNoFAST64 "llo" + +# define SCNoMAX "llo" +# define SCNoPTR "o" + +# define SCNu8 "hhu" +# define SCNu16 "hu" +# define SCNu32 "u" +# define SCNu64 "llu" + +# define SCNuLEAST8 "hhu" +# define SCNuLEAST16 "hu" +# define SCNuLEAST32 "u" +# define SCNuLEAST64 "llu" + +# define SCNuFAST8 "hhu" +# define SCNuFAST16 "hu" +# define SCNuFAST32 "u" +# define SCNuFAST64 "llu" + +# define SCNuMAX "llu" +# define SCNuPTR "u" + +# define SCNx8 "hhx" +# define SCNx16 "hx" +# define SCNx32 "x" +# define SCNx64 "llx" + +# define SCNxLEAST8 "hhx" +# define SCNxLEAST16 "hx" +# define SCNxLEAST32 "x" +# define SCNxLEAST64 "llx" + +# define SCNxFAST8 "hhx" +# define SCNxFAST16 "hx" +# define SCNxFAST32 "x" +# define SCNxFAST64 "llx" + +# define SCNxMAX "llx" +# define SCNxPTR "x" + +#endif + +#endif /* __ARCH_SIM_INCLUDE_INTTYPES_H */ diff --git a/arch/x86/include/i486/inttypes.h b/arch/x86/include/i486/inttypes.h new file mode 100644 index 0000000000..1cfe55f9a9 --- /dev/null +++ b/arch/x86/include/i486/inttypes.h @@ -0,0 +1,245 @@ +/**************************************************************************** + * arch/x86/include/i486/inttypes.h + * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_X86_INCLUDE_I486_INTTYPES_H +#define __ARCH_X86_INCLUDE_I486_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PRId8 "d" +#define PRId16 "d" +#define PRId32 "d" +#define PRId64 "lld" + +#define PRIdLEAST8 "d" +#define PRIdLEAST16 "d" +#define PRIdLEAST32 "d" +#define PRIdLEAST64 "lld" + +#define PRIdFAST8 "d" +#define PRIdFAST16 "d" +#define PRIdFAST32 "d" +#define PRIdFAST64 "lld" + +#define PRIdMAX "lld" +#define PRIdPTR "d" + +#define PRIi8 "i" +#define PRIi16 "i" +#define PRIi32 "i" +#define PRIi64 "lli" + +#define PRIiLEAST8 "i" +#define PRIiLEAST16 "i" +#define PRIiLEAST32 "i" +#define PRIiLEAST64 "lli" + +#define PRIiFAST8 "i" +#define PRIiFAST16 "i" +#define PRIiFAST32 "i" +#define PRIiFAST64 "lli" + +#define PRIiMAX "lli" +#define PRIiPTR "i" + +#define PRIo8 "o" +#define PRIo16 "o" +#define PRIo32 "o" +#define PRIo64 "llo" + +#define PRIoLEAST8 "o" +#define PRIoLEAST16 "o" +#define PRIoLEAST32 "o" +#define PRIoLEAST64 "llo" + +#define PRIoFAST8 "o" +#define PRIoFAST16 "o" +#define PRIoFAST32 "o" +#define PRIoFAST64 "llo" + +#define PRIoMAX "llo" +#define PRIoPTR "o" + +#define PRIu8 "u" +#define PRIu16 "u" +#define PRIu32 "u" +#define PRIu64 "llu" + +#define PRIuLEAST8 "u" +#define PRIuLEAST16 "u" +#define PRIuLEAST32 "u" +#define PRIuLEAST64 "llu" + +#define PRIuFAST8 "u" +#define PRIuFAST16 "u" +#define PRIuFAST32 "u" +#define PRIuFAST64 "llu" + +#define PRIuMAX "llu" +#define PRIuPTR "u" + +#define PRIx8 "x" +#define PRIx16 "x" +#define PRIx32 "x" +#define PRIx64 "llx" + +#define PRIxLEAST8 "x" +#define PRIxLEAST16 "x" +#define PRIxLEAST32 "x" +#define PRIxLEAST64 "llx" + +#define PRIxFAST8 "x" +#define PRIxFAST16 "x" +#define PRIxFAST32 "x" +#define PRIxFAST64 "llx" + +#define PRIxMAX "llx" +#define PRIxPTR "x" + +#define PRIX8 "X" +#define PRIX16 "X" +#define PRIX32 "X" +#define PRIX64 "llX" + +#define PRIXLEAST8 "X" +#define PRIXLEAST16 "X" +#define PRIXLEAST32 "X" +#define PRIXLEAST64 "llX" + +#define PRIXFAST8 "X" +#define PRIXFAST16 "X" +#define PRIXFAST32 "X" +#define PRIXFAST64 "llX" + +#define PRIXMAX "llX" +#define PRIXPTR "X" + +#define SCNd8 "hhd" +#define SCNd16 "hd" +#define SCNd32 "d" +#define SCNd64 "lld" + +#define SCNdLEAST8 "hhd" +#define SCNdLEAST16 "hd" +#define SCNdLEAST32 "d" +#define SCNdLEAST64 "lld" + +#define SCNdFAST8 "hhd" +#define SCNdFAST16 "hd" +#define SCNdFAST32 "d" +#define SCNdFAST64 "lld" + +#define SCNdMAX "lld" +#define SCNdPTR "d" + +#define SCNi8 "hhi" +#define SCNi16 "hi" +#define SCNi32 "i" +#define SCNi64 "lli" + +#define SCNiLEAST8 "hhi" +#define SCNiLEAST16 "hi" +#define SCNiLEAST32 "i" +#define SCNiLEAST64 "lli" + +#define SCNiFAST8 "hhi" +#define SCNiFAST16 "hi" +#define SCNiFAST32 "i" +#define SCNiFAST64 "lli" + +#define SCNiMAX "lli" +#define SCNiPTR "i" + +#define SCNo8 "hho" +#define SCNo16 "ho" +#define SCNo32 "o" +#define SCNo64 "llo" + +#define SCNoLEAST8 "hho" +#define SCNoLEAST16 "ho" +#define SCNoLEAST32 "o" +#define SCNoLEAST64 "llo" + +#define SCNoFAST8 "hho" +#define SCNoFAST16 "ho" +#define SCNoFAST32 "o" +#define SCNoFAST64 "llo" + +#define SCNoMAX "llo" +#define SCNoPTR "o" + +#define SCNu8 "hhu" +#define SCNu16 "hu" +#define SCNu32 "u" +#define SCNu64 "llu" + +#define SCNuLEAST8 "hhu" +#define SCNuLEAST16 "hu" +#define SCNuLEAST32 "u" +#define SCNuLEAST64 "llu" + +#define SCNuFAST8 "hhu" +#define SCNuFAST16 "hu" +#define SCNuFAST32 "u" +#define SCNuFAST64 "llu" + +#define SCNuMAX "llu" +#define SCNuPTR "u" + +#define SCNx8 "hhx" +#define SCNx16 "hx" +#define SCNx32 "x" +#define SCNx64 "llx" + +#define SCNxLEAST8 "hhx" +#define SCNxLEAST16 "hx" +#define SCNxLEAST32 "x" +#define SCNxLEAST64 "llx" + +#define SCNxFAST8 "hhx" +#define SCNxFAST16 "hx" +#define SCNxFAST32 "x" +#define SCNxFAST64 "llx" + +#define SCNxMAX "llx" +#define SCNxPTR "x" + +#endif /* __ARCH_X86_INCLUDE_I486_INTTYPES_H */ diff --git a/arch/x86/include/inttypes.h b/arch/x86/include/inttypes.h new file mode 100644 index 0000000000..1ee4484b14 --- /dev/null +++ b/arch/x86/include/inttypes.h @@ -0,0 +1,51 @@ +/**************************************************************************** + * arch/x86/include/inttypes.h + * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_X86_INCLUDE_INTTYPES_H +#define __ARCH_X86_INCLUDE_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifdef CONFIG_ARCH_I486 +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_X86_INCLUDE_INTTYPES_H */ diff --git a/arch/xtensa/include/inttypes.h b/arch/xtensa/include/inttypes.h new file mode 100644 index 0000000000..06a5e10591 --- /dev/null +++ b/arch/xtensa/include/inttypes.h @@ -0,0 +1,245 @@ +/**************************************************************************** + * arch/xtensa/include/inttypes.h + * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_INCLUDE_INTTYPES_H +#define __ARCH_XTENSA_INCLUDE_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PRId8 "d" +#define PRId16 "d" +#define PRId32 "d" +#define PRId64 "lld" + +#define PRIdLEAST8 "d" +#define PRIdLEAST16 "d" +#define PRIdLEAST32 "d" +#define PRIdLEAST64 "lld" + +#define PRIdFAST8 "d" +#define PRIdFAST16 "d" +#define PRIdFAST32 "d" +#define PRIdFAST64 "lld" + +#define PRIdMAX "lld" +#define PRIdPTR "d" + +#define PRIi8 "i" +#define PRIi16 "i" +#define PRIi32 "i" +#define PRIi64 "lli" + +#define PRIiLEAST8 "i" +#define PRIiLEAST16 "i" +#define PRIiLEAST32 "i" +#define PRIiLEAST64 "lli" + +#define PRIiFAST8 "i" +#define PRIiFAST16 "i" +#define PRIiFAST32 "i" +#define PRIiFAST64 "lli" + +#define PRIiMAX "lli" +#define PRIiPTR "i" + +#define PRIo8 "o" +#define PRIo16 "o" +#define PRIo32 "o" +#define PRIo64 "llo" + +#define PRIoLEAST8 "o" +#define PRIoLEAST16 "o" +#define PRIoLEAST32 "o" +#define PRIoLEAST64 "llo" + +#define PRIoFAST8 "o" +#define PRIoFAST16 "o" +#define PRIoFAST32 "o" +#define PRIoFAST64 "llo" + +#define PRIoMAX "llo" +#define PRIoPTR "o" + +#define PRIu8 "u" +#define PRIu16 "u" +#define PRIu32 "u" +#define PRIu64 "llu" + +#define PRIuLEAST8 "u" +#define PRIuLEAST16 "u" +#define PRIuLEAST32 "u" +#define PRIuLEAST64 "llu" + +#define PRIuFAST8 "u" +#define PRIuFAST16 "u" +#define PRIuFAST32 "u" +#define PRIuFAST64 "llu" + +#define PRIuMAX "llu" +#define PRIuPTR "u" + +#define PRIx8 "x" +#define PRIx16 "x" +#define PRIx32 "x" +#define PRIx64 "llx" + +#define PRIxLEAST8 "x" +#define PRIxLEAST16 "x" +#define PRIxLEAST32 "x" +#define PRIxLEAST64 "llx" + +#define PRIxFAST8 "x" +#define PRIxFAST16 "x" +#define PRIxFAST32 "x" +#define PRIxFAST64 "llx" + +#define PRIxMAX "llx" +#define PRIxPTR "x" + +#define PRIX8 "X" +#define PRIX16 "X" +#define PRIX32 "X" +#define PRIX64 "llX" + +#define PRIXLEAST8 "X" +#define PRIXLEAST16 "X" +#define PRIXLEAST32 "X" +#define PRIXLEAST64 "llX" + +#define PRIXFAST8 "X" +#define PRIXFAST16 "X" +#define PRIXFAST32 "X" +#define PRIXFAST64 "llX" + +#define PRIXMAX "llX" +#define PRIXPTR "X" + +#define SCNd8 "hhd" +#define SCNd16 "hd" +#define SCNd32 "d" +#define SCNd64 "lld" + +#define SCNdLEAST8 "hhd" +#define SCNdLEAST16 "hd" +#define SCNdLEAST32 "d" +#define SCNdLEAST64 "lld" + +#define SCNdFAST8 "hhd" +#define SCNdFAST16 "hd" +#define SCNdFAST32 "d" +#define SCNdFAST64 "lld" + +#define SCNdMAX "lld" +#define SCNdPTR "d" + +#define SCNi8 "hhi" +#define SCNi16 "hi" +#define SCNi32 "i" +#define SCNi64 "lli" + +#define SCNiLEAST8 "hhi" +#define SCNiLEAST16 "hi" +#define SCNiLEAST32 "i" +#define SCNiLEAST64 "lli" + +#define SCNiFAST8 "hhi" +#define SCNiFAST16 "hi" +#define SCNiFAST32 "i" +#define SCNiFAST64 "lli" + +#define SCNiMAX "lli" +#define SCNiPTR "i" + +#define SCNo8 "hho" +#define SCNo16 "ho" +#define SCNo32 "o" +#define SCNo64 "llo" + +#define SCNoLEAST8 "hho" +#define SCNoLEAST16 "ho" +#define SCNoLEAST32 "o" +#define SCNoLEAST64 "llo" + +#define SCNoFAST8 "hho" +#define SCNoFAST16 "ho" +#define SCNoFAST32 "o" +#define SCNoFAST64 "llo" + +#define SCNoMAX "llo" +#define SCNoPTR "o" + +#define SCNu8 "hhu" +#define SCNu16 "hu" +#define SCNu32 "u" +#define SCNu64 "llu" + +#define SCNuLEAST8 "hhu" +#define SCNuLEAST16 "hu" +#define SCNuLEAST32 "u" +#define SCNuLEAST64 "llu" + +#define SCNuFAST8 "hhu" +#define SCNuFAST16 "hu" +#define SCNuFAST32 "u" +#define SCNuFAST64 "llu" + +#define SCNuMAX "llu" +#define SCNuPTR "u" + +#define SCNx8 "hhx" +#define SCNx16 "hx" +#define SCNx32 "x" +#define SCNx64 "llx" + +#define SCNxLEAST8 "hhx" +#define SCNxLEAST16 "hx" +#define SCNxLEAST32 "x" +#define SCNxLEAST64 "llx" + +#define SCNxFAST8 "hhx" +#define SCNxFAST16 "hx" +#define SCNxFAST32 "x" +#define SCNxFAST64 "llx" + +#define SCNxMAX "llx" +#define SCNxPTR "x" + +#endif /* __ARCH_XTENSA_INCLUDE_INTTYPES_H */ diff --git a/arch/z16/include/inttypes.h b/arch/z16/include/inttypes.h new file mode 100644 index 0000000000..93664c5947 --- /dev/null +++ b/arch/z16/include/inttypes.h @@ -0,0 +1,212 @@ +/**************************************************************************** + * arch/z16/include/inttypes.h + * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_Z16_INCLUDE_INTTYPES_H +#define __ARCH_Z16_INCLUDE_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PRId8 "d" +#define PRId16 "d" +#define PRId32 "d" + +#define PRIdLEAST8 "d" +#define PRIdLEAST16 "d" +#define PRIdLEAST32 "d" + +#define PRIdFAST8 "d" +#define PRIdFAST16 "d" +#define PRIdFAST32 "d" + +#define PRIdMAX "d" +#define PRIdPTR "d" + +#define PRIi8 "i" +#define PRIi16 "i" +#define PRIi32 "i" + +#define PRIiLEAST8 "i" +#define PRIiLEAST16 "i" +#define PRIiLEAST32 "i" + +#define PRIiFAST8 "i" +#define PRIiFAST16 "i" +#define PRIiFAST32 "i" + +#define PRIiMAX "i" +#define PRIiPTR "i" + +#define PRIo8 "o" +#define PRIo16 "o" +#define PRIo32 "o" + +#define PRIoLEAST8 "o" +#define PRIoLEAST16 "o" +#define PRIoLEAST32 "o" + +#define PRIoFAST8 "o" +#define PRIoFAST16 "o" +#define PRIoFAST32 "o" + +#define PRIoMAX "o" +#define PRIoPTR "o" + +#define PRIu8 "u" +#define PRIu16 "u" +#define PRIu32 "u" + +#define PRIuLEAST8 "u" +#define PRIuLEAST16 "u" +#define PRIuLEAST32 "u" + +#define PRIuFAST8 "u" +#define PRIuFAST16 "u" +#define PRIuFAST32 "u" + +#define PRIuMAX "u" +#define PRIuPTR "u" + +#define PRIx8 "x" +#define PRIx16 "x" +#define PRIx32 "x" + +#define PRIxLEAST8 "x" +#define PRIxLEAST16 "x" +#define PRIxLEAST32 "x" + +#define PRIxFAST8 "x" +#define PRIxFAST16 "x" +#define PRIxFAST32 "x" + +#define PRIxMAX "x" +#define PRIxPTR "x" + +#define PRIX8 "X" +#define PRIX16 "X" +#define PRIX32 "X" + +#define PRIXLEAST8 "X" +#define PRIXLEAST16 "X" +#define PRIXLEAST32 "X" + +#define PRIXFAST8 "X" +#define PRIXFAST16 "X" +#define PRIXFAST32 "X" + +#define PRIXMAX "X" +#define PRIXPTR "X" + +#define SCNd8 "hhd" +#define SCNd16 "hd" +#define SCNd32 "d" + +#define SCNdLEAST8 "hhd" +#define SCNdLEAST16 "hd" +#define SCNdLEAST32 "d" + +#define SCNdFAST8 "hhd" +#define SCNdFAST16 "hd" +#define SCNdFAST32 "d" + +#define SCNdMAX "d" +#define SCNdPTR "d" + +#define SCNi8 "hhi" +#define SCNi16 "hi" +#define SCNi32 "i" + +#define SCNiLEAST8 "hhi" +#define SCNiLEAST16 "hi" +#define SCNiLEAST32 "i" + +#define SCNiFAST8 "hhi" +#define SCNiFAST16 "hi" +#define SCNiFAST32 "i" + +#define SCNiMAX "i" +#define SCNiPTR "i" + +#define SCNo8 "hho" +#define SCNo16 "ho" +#define SCNo32 "o" + +#define SCNoLEAST8 "hho" +#define SCNoLEAST16 "ho" +#define SCNoLEAST32 "o" + +#define SCNoFAST8 "hho" +#define SCNoFAST16 "ho" +#define SCNoFAST32 "o" + +#define SCNoMAX "o" +#define SCNoPTR "o" + +#define SCNu8 "hhu" +#define SCNu16 "hu" +#define SCNu32 "u" + +#define SCNuLEAST8 "hhu" +#define SCNuLEAST16 "hu" +#define SCNuLEAST32 "u" + +#define SCNuFAST8 "hhu" +#define SCNuFAST16 "hu" +#define SCNuFAST32 "u" + +#define SCNuMAX "u" +#define SCNuPTR "u" + +#define SCNx8 "hhx" +#define SCNx16 "hx" +#define SCNx32 "x" + +#define SCNxLEAST8 "hhx" +#define SCNxLEAST16 "hx" +#define SCNxLEAST32 "x" + +#define SCNxFAST8 "hhx" +#define SCNxFAST16 "hx" +#define SCNxFAST32 "x" + +#define SCNxMAX "x" +#define SCNxPTR "x" + +#endif /* __ARCH_Z16_INCLUDE_INTTYPES_H */ diff --git a/arch/z80/include/ez80/inttypes.h b/arch/z80/include/ez80/inttypes.h new file mode 100644 index 0000000000..ee7cfb2861 --- /dev/null +++ b/arch/z80/include/ez80/inttypes.h @@ -0,0 +1,372 @@ +/**************************************************************************** + * arch/z80/include/ez80/inttypes.h + * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_Z80_INCLUDE_EZ80_INTTYPES_H +#define __ARCH_Z80_INCLUDE_EZ80_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_EZ80_Z80MODE + +# define PRId8 "d" +# define PRId16 "d" +# define PRId32 "ld" + +# define PRIdLEAST8 "d" +# define PRIdLEAST16 "d" +# define PRIdLEAST32 "ld" + +# define PRIdFAST8 "d" +# define PRIdFAST16 "d" +# define PRIdFAST32 "ld" + +# define PRIdMAX "ld" +# define PRIdPTR "d" + +# define PRIi8 "i" +# define PRIi16 "i" +# define PRIi32 "li" + +# define PRIiLEAST8 "i" +# define PRIiLEAST16 "i" +# define PRIiLEAST32 "li" + +# define PRIiFAST8 "i" +# define PRIiFAST16 "i" +# define PRIiFAST32 "li" + +# define PRIiMAX "li" +# define PRIiPTR "i" + +# define PRIo8 "o" +# define PRIo16 "o" +# define PRIo32 "lo" + +# define PRIoLEAST8 "o" +# define PRIoLEAST16 "o" +# define PRIoLEAST32 "lo" + +# define PRIoFAST8 "o" +# define PRIoFAST16 "o" +# define PRIoFAST32 "lo" + +# define PRIoMAX "lo" +# define PRIoPTR "o" + +# define PRIu8 "u" +# define PRIu16 "u" +# define PRIu32 "lu" + +# define PRIuLEAST8 "u" +# define PRIuLEAST16 "u" +# define PRIuLEAST32 "lu" + +# define PRIuFAST8 "u" +# define PRIuFAST16 "u" +# define PRIuFAST32 "lu" + +# define PRIuMAX "lu" +# define PRIuPTR "u" + +# define PRIx8 "x" +# define PRIx16 "x" +# define PRIx32 "lx" + +# define PRIxLEAST8 "x" +# define PRIxLEAST16 "x" +# define PRIxLEAST32 "lx" + +# define PRIxFAST8 "x" +# define PRIxFAST16 "x" +# define PRIxFAST32 "lx" + +# define PRIxMAX "lx" +# define PRIxPTR "x" + +# define PRIX8 "X" +# define PRIX16 "X" +# define PRIX32 "lX" + +# define PRIXLEAST8 "X" +# define PRIXLEAST16 "X" +# define PRIXLEAST32 "lX" + +# define PRIXFAST8 "X" +# define PRIXFAST16 "X" +# define PRIXFAST32 "lX" + +# define PRIXMAX "lX" +# define PRIXPTR "X" + +# define SCNd8 "hhd" +# define SCNd16 "hd" +# define SCNd32 "ld" + +# define SCNdLEAST8 "hhd" +# define SCNdLEAST16 "hd" +# define SCNdLEAST32 "ld" + +# define SCNdFAST8 "hhd" +# define SCNdFAST16 "hd" +# define SCNdFAST32 "ld" + +# define SCNdMAX "ld" +# define SCNdPTR "hd" + +# define SCNi8 "hhi" +# define SCNi16 "hi" +# define SCNi32 "li" + +# define SCNiLEAST8 "hhi" +# define SCNiLEAST16 "hi" +# define SCNiLEAST32 "li" + +# define SCNiFAST8 "hhi" +# define SCNiFAST16 "hi" +# define SCNiFAST32 "li" + +# define SCNiMAX "li" +# define SCNiPTR "hi" + +# define SCNo8 "hho" +# define SCNo16 "ho" +# define SCNo32 "lo" + +# define SCNoLEAST8 "hho" +# define SCNoLEAST16 "ho" +# define SCNoLEAST32 "lo" + +# define SCNoFAST8 "hho" +# define SCNoFAST16 "ho" +# define SCNoFAST32 "lo" + +# define SCNoMAX "lo" +# define SCNoPTR "ho" + +# define SCNu8 "hhu" +# define SCNu16 "hu" +# define SCNu32 "lu" + +# define SCNuLEAST8 "hhu" +# define SCNuLEAST16 "hu" +# define SCNuLEAST32 "lu" + +# define SCNuFAST8 "hhu" +# define SCNuFAST16 "hu" +# define SCNuFAST32 "lu" + +# define SCNuMAX "lu" +# define SCNuPTR "hu" + +# define SCNx8 "hhx" +# define SCNx16 "hx" +# define SCNx32 "lx" + +# define SCNxLEAST8 "hhx" +# define SCNxLEAST16 "hx" +# define SCNxLEAST32 "lx" + +# define SCNxFAST8 "hhx" +# define SCNxFAST16 "hx" +# define SCNxFAST32 "lx" + +# define SCNxMAX "lx" +# define SCNxPTR "hx" + +#else + +# define PRId8 "d" +# define PRId16 "d" +# define PRId32 "ld" + +# define PRIdLEAST8 "d" +# define PRIdLEAST16 "d" +# define PRIdLEAST32 "ld" + +# define PRIdFAST8 "d" +# define PRIdFAST16 "d" +# define PRIdFAST32 "ld" + +# define PRIdMAX "ld" + +# define PRIi8 "i" +# define PRIi16 "i" +# define PRIi32 "li" + +# define PRIiLEAST8 "i" +# define PRIiLEAST16 "i" +# define PRIiLEAST32 "li" + +# define PRIiFAST8 "i" +# define PRIiFAST16 "i" +# define PRIiFAST32 "li" + +# define PRIiMAX "li" + +# define PRIo8 "o" +# define PRIo16 "o" +# define PRIo32 "lo" + +# define PRIoLEAST8 "o" +# define PRIoLEAST16 "o" +# define PRIoLEAST32 "lo" + +# define PRIoFAST8 "o" +# define PRIoFAST16 "o" +# define PRIoFAST32 "lo" + +# define PRIoMAX "lo" + +# define PRIu8 "u" +# define PRIu16 "u" +# define PRIu32 "lu" + +# define PRIuLEAST8 "u" +# define PRIuLEAST16 "u" +# define PRIuLEAST32 "lu" + +# define PRIuFAST8 "u" +# define PRIuFAST16 "u" +# define PRIuFAST32 "lu" + +# define PRIuMAX "lu" + +# define PRIx8 "x" +# define PRIx16 "x" +# define PRIx32 "lx" + +# define PRIxLEAST8 "x" +# define PRIxLEAST16 "x" +# define PRIxLEAST32 "lx" + +# define PRIxFAST8 "x" +# define PRIxFAST16 "x" +# define PRIxFAST32 "lx" + +# define PRIxMAX "lx" + +# define PRIX8 "X" +# define PRIX16 "X" +# define PRIX32 "lX" + +# define PRIXLEAST8 "X" +# define PRIXLEAST16 "X" +# define PRIXLEAST32 "lX" + +# define PRIXFAST8 "X" +# define PRIXFAST16 "X" +# define PRIXFAST32 "lX" + +# define PRIXMAX "lX" + +# define SCNd8 "hhd" +# define SCNd16 "hd" +# define SCNd32 "ld" + +# define SCNdLEAST8 "hhd" +# define SCNdLEAST16 "hd" +# define SCNdLEAST32 "ld" + +# define SCNdFAST8 "hhd" +# define SCNdFAST16 "hd" +# define SCNdFAST32 "ld" + +# define SCNdMAX "ld" + +# define SCNi8 "hhi" +# define SCNi16 "hi" +# define SCNi32 "li" + +# define SCNiLEAST8 "hhi" +# define SCNiLEAST16 "hi" +# define SCNiLEAST32 "li" + +# define SCNiFAST8 "hhi" +# define SCNiFAST16 "hi" +# define SCNiFAST32 "li" + +# define SCNiMAX "li" + +# define SCNo8 "hho" +# define SCNo16 "ho" +# define SCNo32 "lo" + +# define SCNoLEAST8 "hho" +# define SCNoLEAST16 "ho" +# define SCNoLEAST32 "lo" + +# define SCNoFAST8 "hho" +# define SCNoFAST16 "ho" +# define SCNoFAST32 "lo" + +# define SCNoMAX "lo" + +# define SCNu8 "hhu" +# define SCNu16 "hu" +# define SCNu32 "lu" + +# define SCNuLEAST8 "hhu" +# define SCNuLEAST16 "hu" +# define SCNuLEAST32 "lu" + +# define SCNuFAST8 "hhu" +# define SCNuFAST16 "hu" +# define SCNuFAST32 "lu" + +# define SCNuMAX "lu" + +# define SCNx8 "hhx" +# define SCNx16 "hx" +# define SCNx32 "lx" + +# define SCNxLEAST8 "hhx" +# define SCNxLEAST16 "hx" +# define SCNxLEAST32 "lx" + +# define SCNxFAST8 "hhx" +# define SCNxFAST16 "hx" +# define SCNxFAST32 "lx" + +# define SCNxMAX "lx" + +#endif + +#endif /* __ARCH_Z80_INCLUDE_EZ80_INTTYPES_H */ diff --git a/arch/z80/include/inttypes.h b/arch/z80/include/inttypes.h new file mode 100644 index 0000000000..0ff8561a31 --- /dev/null +++ b/arch/z80/include/inttypes.h @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/z80/include/inttypes.h + * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_Z80_INCLUDE_INTTYPES_H +#define __ARCH_Z80_INCLUDE_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_Z80_INCLUDE_INTTYPES_H */ diff --git a/arch/z80/include/z180/inttypes.h b/arch/z80/include/z180/inttypes.h new file mode 100644 index 0000000000..efd4cdca2f --- /dev/null +++ b/arch/z80/include/z180/inttypes.h @@ -0,0 +1,212 @@ +/**************************************************************************** + * arch/z80/include/z180/inttypes.h + * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_Z80_INCLUDE_Z180_INTTYPES_H +#define __ARCH_Z80_INCLUDE_Z180_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PRId8 "d" +#define PRId16 "d" +#define PRId32 "ld" + +#define PRIdLEAST8 "d" +#define PRIdLEAST16 "d" +#define PRIdLEAST32 "ld" + +#define PRIdFAST8 "d" +#define PRIdFAST16 "d" +#define PRIdFAST32 "ld" + +#define PRIdMAX "ld" +#define PRIdPTR "d" + +#define PRIi8 "i" +#define PRIi16 "i" +#define PRIi32 "li" + +#define PRIiLEAST8 "i" +#define PRIiLEAST16 "i" +#define PRIiLEAST32 "li" + +#define PRIiFAST8 "i" +#define PRIiFAST16 "i" +#define PRIiFAST32 "li" + +#define PRIiMAX "li" +#define PRIiPTR "i" + +#define PRIo8 "o" +#define PRIo16 "o" +#define PRIo32 "lo" + +#define PRIoLEAST8 "o" +#define PRIoLEAST16 "o" +#define PRIoLEAST32 "lo" + +#define PRIoFAST8 "o" +#define PRIoFAST16 "o" +#define PRIoFAST32 "lo" + +#define PRIoMAX "lo" +#define PRIoPTR "o" + +#define PRIu8 "u" +#define PRIu16 "u" +#define PRIu32 "lu" + +#define PRIuLEAST8 "u" +#define PRIuLEAST16 "u" +#define PRIuLEAST32 "lu" + +#define PRIuFAST8 "u" +#define PRIuFAST16 "u" +#define PRIuFAST32 "lu" + +#define PRIuMAX "lu" +#define PRIuPTR "u" + +#define PRIx8 "x" +#define PRIx16 "x" +#define PRIx32 "lx" + +#define PRIxLEAST8 "x" +#define PRIxLEAST16 "x" +#define PRIxLEAST32 "lx" + +#define PRIxFAST8 "x" +#define PRIxFAST16 "x" +#define PRIxFAST32 "lx" + +#define PRIxMAX "lx" +#define PRIxPTR "x" + +#define PRIX8 "X" +#define PRIX16 "X" +#define PRIX32 "lX" + +#define PRIXLEAST8 "X" +#define PRIXLEAST16 "X" +#define PRIXLEAST32 "lX" + +#define PRIXFAST8 "X" +#define PRIXFAST16 "X" +#define PRIXFAST32 "lX" + +#define PRIXMAX "lX" +#define PRIXPTR "X" + +#define SCNd8 "hhd" +#define SCNd16 "d" +#define SCNd32 "ld" + +#define SCNdLEAST8 "hhd" +#define SCNdLEAST16 "d" +#define SCNdLEAST32 "ld" + +#define SCNdFAST8 "hhd" +#define SCNdFAST16 "d" +#define SCNdFAST32 "ld" + +#define SCNdMAX "ld" +#define SCNdPTR "d" + +#define SCNi8 "hhi" +#define SCNi16 "i" +#define SCNi32 "li" + +#define SCNiLEAST8 "hhi" +#define SCNiLEAST16 "i" +#define SCNiLEAST32 "li" + +#define SCNiFAST8 "hhi" +#define SCNiFAST16 "i" +#define SCNiFAST32 "li" + +#define SCNiMAX "li" +#define SCNiPTR "i" + +#define SCNo8 "hho" +#define SCNo16 "o" +#define SCNo32 "lo" + +#define SCNoLEAST8 "hho" +#define SCNoLEAST16 "o" +#define SCNoLEAST32 "lo" + +#define SCNoFAST8 "hho" +#define SCNoFAST16 "o" +#define SCNoFAST32 "lo" + +#define SCNoMAX "lo" +#define SCNoPTR "o" + +#define SCNu8 "hhu" +#define SCNu16 "u" +#define SCNu32 "lu" + +#define SCNuLEAST8 "hhu" +#define SCNuLEAST16 "u" +#define SCNuLEAST32 "lu" + +#define SCNuFAST8 "hhu" +#define SCNuFAST16 "u" +#define SCNuFAST32 "lu" + +#define SCNuMAX "lu" +#define SCNuPTR "u" + +#define SCNx8 "hhx" +#define SCNx16 "x" +#define SCNx32 "lx" + +#define SCNxLEAST8 "hhx" +#define SCNxLEAST16 "x" +#define SCNxLEAST32 "lx" + +#define SCNxFAST8 "hhx" +#define SCNxFAST16 "x" +#define SCNxFAST32 "lx" + +#define SCNxMAX "lx" +#define SCNxPTR "x" + +#endif /* __ARCH_Z80_INCLUDE_Z180_INTTYPES_H */ diff --git a/arch/z80/include/z8/inttypes.h b/arch/z80/include/z8/inttypes.h new file mode 100644 index 0000000000..9f7eb0a3e4 --- /dev/null +++ b/arch/z80/include/z8/inttypes.h @@ -0,0 +1,212 @@ +/**************************************************************************** + * arch/z80/include/z8/inttypes.h + * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_Z80_INCLUDE_Z8_INTTYPES_H +#define __ARCH_Z80_INCLUDE_Z8_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PRId8 "d" +#define PRId16 "d" +#define PRId32 "ld" + +#define PRIdLEAST8 "d" +#define PRIdLEAST16 "d" +#define PRIdLEAST32 "ld" + +#define PRIdFAST8 "d" +#define PRIdFAST16 "d" +#define PRIdFAST32 "ld" + +#define PRIdMAX "ld" +#define PRIdPTR "d" + +#define PRIi8 "i" +#define PRIi16 "i" +#define PRIi32 "li" + +#define PRIiLEAST8 "i" +#define PRIiLEAST16 "i" +#define PRIiLEAST32 "li" + +#define PRIiFAST8 "i" +#define PRIiFAST16 "i" +#define PRIiFAST32 "li" + +#define PRIiMAX "li" +#define PRIiPTR "i" + +#define PRIo8 "o" +#define PRIo16 "o" +#define PRIo32 "lo" + +#define PRIoLEAST8 "o" +#define PRIoLEAST16 "o" +#define PRIoLEAST32 "lo" + +#define PRIoFAST8 "o" +#define PRIoFAST16 "o" +#define PRIoFAST32 "lo" + +#define PRIoMAX "lo" +#define PRIoPTR "o" + +#define PRIu8 "u" +#define PRIu16 "u" +#define PRIu32 "lu" + +#define PRIuLEAST8 "u" +#define PRIuLEAST16 "u" +#define PRIuLEAST32 "lu" + +#define PRIuFAST8 "u" +#define PRIuFAST16 "u" +#define PRIuFAST32 "lu" + +#define PRIuMAX "lu" +#define PRIuPTR "u" + +#define PRIx8 "x" +#define PRIx16 "x" +#define PRIx32 "lx" + +#define PRIxLEAST8 "x" +#define PRIxLEAST16 "x" +#define PRIxLEAST32 "lx" + +#define PRIxFAST8 "x" +#define PRIxFAST16 "x" +#define PRIxFAST32 "lx" + +#define PRIxMAX "lx" +#define PRIxPTR "x" + +#define PRIX8 "X" +#define PRIX16 "X" +#define PRIX32 "lX" + +#define PRIXLEAST8 "X" +#define PRIXLEAST16 "X" +#define PRIXLEAST32 "lX" + +#define PRIXFAST8 "X" +#define PRIXFAST16 "X" +#define PRIXFAST32 "lX" + +#define PRIXMAX "lX" +#define PRIXPTR "X" + +#define SCNd8 "hhd" +#define SCNd16 "d" +#define SCNd32 "ld" + +#define SCNdLEAST8 "hhd" +#define SCNdLEAST16 "d" +#define SCNdLEAST32 "ld" + +#define SCNdFAST8 "hhd" +#define SCNdFAST16 "d" +#define SCNdFAST32 "ld" + +#define SCNdMAX "ld" +#define SCNdPTR "d" + +#define SCNi8 "hhi" +#define SCNi16 "i" +#define SCNi32 "li" + +#define SCNiLEAST8 "hhi" +#define SCNiLEAST16 "i" +#define SCNiLEAST32 "li" + +#define SCNiFAST8 "hhi" +#define SCNiFAST16 "i" +#define SCNiFAST32 "li" + +#define SCNiMAX "li" +#define SCNiPTR "i" + +#define SCNo8 "hho" +#define SCNo16 "o" +#define SCNo32 "lo" + +#define SCNoLEAST8 "hho" +#define SCNoLEAST16 "o" +#define SCNoLEAST32 "lo" + +#define SCNoFAST8 "hho" +#define SCNoFAST16 "o" +#define SCNoFAST32 "lo" + +#define SCNoMAX "lo" +#define SCNoPTR "o" + +#define SCNu8 "hhu" +#define SCNu16 "u" +#define SCNu32 "lu" + +#define SCNuLEAST8 "hhu" +#define SCNuLEAST16 "u" +#define SCNuLEAST32 "lu" + +#define SCNuFAST8 "hhu" +#define SCNuFAST16 "u" +#define SCNuFAST32 "lu" + +#define SCNuMAX "lu" +#define SCNuPTR "u" + +#define SCNx8 "hhx" +#define SCNx16 "x" +#define SCNx32 "lx" + +#define SCNxLEAST8 "hhx" +#define SCNxLEAST16 "x" +#define SCNxLEAST32 "lx" + +#define SCNxFAST8 "hhx" +#define SCNxFAST16 "x" +#define SCNxFAST32 "lx" + +#define SCNxMAX "lx" +#define SCNxPTR "x" + +#endif /* __ARCH_Z80_INCLUDE_Z8_INTTYPES_H */ diff --git a/arch/z80/include/z80/inttypes.h b/arch/z80/include/z80/inttypes.h new file mode 100644 index 0000000000..b8c3964355 --- /dev/null +++ b/arch/z80/include/z80/inttypes.h @@ -0,0 +1,212 @@ +/**************************************************************************** + * arch/z80/include/z80/inttypes.h + * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_Z80_INCLUDE_Z80_INTTYPES_H +#define __ARCH_Z80_INCLUDE_Z80_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PRId8 "d" +#define PRId16 "d" +#define PRId32 "ld" + +#define PRIdLEAST8 "d" +#define PRIdLEAST16 "d" +#define PRIdLEAST32 "ld" + +#define PRIdFAST8 "d" +#define PRIdFAST16 "d" +#define PRIdFAST32 "ld" + +#define PRIdMAX "ld" +#define PRIdPTR "d" + +#define PRIi8 "i" +#define PRIi16 "i" +#define PRIi32 "li" + +#define PRIiLEAST8 "i" +#define PRIiLEAST16 "i" +#define PRIiLEAST32 "li" + +#define PRIiFAST8 "i" +#define PRIiFAST16 "i" +#define PRIiFAST32 "li" + +#define PRIiMAX "li" +#define PRIiPTR "i" + +#define PRIo8 "o" +#define PRIo16 "o" +#define PRIo32 "lo" + +#define PRIoLEAST8 "o" +#define PRIoLEAST16 "o" +#define PRIoLEAST32 "lo" + +#define PRIoFAST8 "o" +#define PRIoFAST16 "o" +#define PRIoFAST32 "lo" + +#define PRIoMAX "lo" +#define PRIoPTR "o" + +#define PRIu8 "u" +#define PRIu16 "u" +#define PRIu32 "lu" + +#define PRIuLEAST8 "u" +#define PRIuLEAST16 "u" +#define PRIuLEAST32 "lu" + +#define PRIuFAST8 "u" +#define PRIuFAST16 "u" +#define PRIuFAST32 "lu" + +#define PRIuMAX "lu" +#define PRIuPTR "u" + +#define PRIx8 "x" +#define PRIx16 "x" +#define PRIx32 "lx" + +#define PRIxLEAST8 "x" +#define PRIxLEAST16 "x" +#define PRIxLEAST32 "lx" + +#define PRIxFAST8 "x" +#define PRIxFAST16 "x" +#define PRIxFAST32 "lx" + +#define PRIxMAX "lx" +#define PRIxPTR "x" + +#define PRIX8 "X" +#define PRIX16 "X" +#define PRIX32 "lX" + +#define PRIXLEAST8 "X" +#define PRIXLEAST16 "X" +#define PRIXLEAST32 "lX" + +#define PRIXFAST8 "X" +#define PRIXFAST16 "X" +#define PRIXFAST32 "lX" + +#define PRIXMAX "lX" +#define PRIXPTR "X" + +#define SCNd8 "hhd" +#define SCNd16 "d" +#define SCNd32 "ld" + +#define SCNdLEAST8 "hhd" +#define SCNdLEAST16 "d" +#define SCNdLEAST32 "ld" + +#define SCNdFAST8 "hhd" +#define SCNdFAST16 "d" +#define SCNdFAST32 "ld" + +#define SCNdMAX "ld" +#define SCNdPTR "d" + +#define SCNi8 "hhi" +#define SCNi16 "i" +#define SCNi32 "li" + +#define SCNiLEAST8 "hhi" +#define SCNiLEAST16 "i" +#define SCNiLEAST32 "li" + +#define SCNiFAST8 "hhi" +#define SCNiFAST16 "i" +#define SCNiFAST32 "li" + +#define SCNiMAX "li" +#define SCNiPTR "i" + +#define SCNo8 "hho" +#define SCNo16 "o" +#define SCNo32 "lo" + +#define SCNoLEAST8 "hho" +#define SCNoLEAST16 "o" +#define SCNoLEAST32 "lo" + +#define SCNoFAST8 "hho" +#define SCNoFAST16 "o" +#define SCNoFAST32 "lo" + +#define SCNoMAX "lo" +#define SCNoPTR "o" + +#define SCNu8 "hhu" +#define SCNu16 "u" +#define SCNu32 "lu" + +#define SCNuLEAST8 "hhu" +#define SCNuLEAST16 "u" +#define SCNuLEAST32 "lu" + +#define SCNuFAST8 "hhu" +#define SCNuFAST16 "u" +#define SCNuFAST32 "lu" + +#define SCNuMAX "lu" +#define SCNuPTR "u" + +#define SCNx8 "hhx" +#define SCNx16 "x" +#define SCNx32 "lx" + +#define SCNxLEAST8 "hhx" +#define SCNxLEAST16 "x" +#define SCNxLEAST32 "lx" + +#define SCNxFAST8 "hhx" +#define SCNxFAST16 "x" +#define SCNxFAST32 "lx" + +#define SCNxMAX "lx" +#define SCNxPTR "x" + +#endif /* __ARCH_Z80_INCLUDE_Z80_INTTYPES_H */ diff --git a/include/inttypes.h b/include/inttypes.h index 9aa1c04973..e9177c7e89 100644 --- a/include/inttypes.h +++ b/include/inttypes.h @@ -49,6 +49,8 @@ #include +#include + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -- GitLab From 544f9ccf8a7ff7a36a2b4674e505c58e2c01d434 Mon Sep 17 00:00:00 2001 From: "Paul A. Patience" Date: Thu, 27 Oct 2016 16:16:13 -0400 Subject: [PATCH 235/734] ez80: Add *PTR definitions to inttypes.h --- arch/z80/include/ez80/inttypes.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/z80/include/ez80/inttypes.h b/arch/z80/include/ez80/inttypes.h index ee7cfb2861..b4b0766293 100644 --- a/arch/z80/include/ez80/inttypes.h +++ b/arch/z80/include/ez80/inttypes.h @@ -226,6 +226,7 @@ # define PRIdFAST32 "ld" # define PRIdMAX "ld" +# define PRIdPTR "d" # define PRIi8 "i" # define PRIi16 "i" @@ -240,6 +241,7 @@ # define PRIiFAST32 "li" # define PRIiMAX "li" +# define PRIiPTR "i" # define PRIo8 "o" # define PRIo16 "o" @@ -254,6 +256,7 @@ # define PRIoFAST32 "lo" # define PRIoMAX "lo" +# define PRIoPTR "o" # define PRIu8 "u" # define PRIu16 "u" @@ -268,6 +271,7 @@ # define PRIuFAST32 "lu" # define PRIuMAX "lu" +# define PRIuPTR "u" # define PRIx8 "x" # define PRIx16 "x" @@ -282,6 +286,7 @@ # define PRIxFAST32 "lx" # define PRIxMAX "lx" +# define PRIxPTR "x" # define PRIX8 "X" # define PRIX16 "X" @@ -296,6 +301,7 @@ # define PRIXFAST32 "lX" # define PRIXMAX "lX" +# define PRIXPTR "X" # define SCNd8 "hhd" # define SCNd16 "hd" @@ -310,6 +316,7 @@ # define SCNdFAST32 "ld" # define SCNdMAX "ld" +# define SCNdPTR "d" # define SCNi8 "hhi" # define SCNi16 "hi" @@ -324,6 +331,7 @@ # define SCNiFAST32 "li" # define SCNiMAX "li" +# define SCNiPTR "i" # define SCNo8 "hho" # define SCNo16 "ho" @@ -338,6 +346,7 @@ # define SCNoFAST32 "lo" # define SCNoMAX "lo" +# define SCNoPTR "o" # define SCNu8 "hhu" # define SCNu16 "hu" @@ -352,6 +361,7 @@ # define SCNuFAST32 "lu" # define SCNuMAX "lu" +# define SCNuPTR "u" # define SCNx8 "hhx" # define SCNx16 "hx" @@ -366,6 +376,7 @@ # define SCNxFAST32 "lx" # define SCNxMAX "lx" +# define SCNxPTR "x" #endif -- GitLab From ac00982dc8ab0612c930f2f019740676da6a2c1f Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Thu, 27 Oct 2016 15:04:26 -0600 Subject: [PATCH 236/734] STM32F103 Minimum: Add rgbled configuration ommitted in previous commit --- configs/stm32f103-minimum/rgbled/Make.defs | 113 ++ configs/stm32f103-minimum/rgbled/defconfig | 1184 ++++++++++++++++++++ configs/stm32f103-minimum/rgbled/setenv.sh | 100 ++ 3 files changed, 1397 insertions(+) create mode 100644 configs/stm32f103-minimum/rgbled/Make.defs create mode 100644 configs/stm32f103-minimum/rgbled/defconfig create mode 100644 configs/stm32f103-minimum/rgbled/setenv.sh diff --git a/configs/stm32f103-minimum/rgbled/Make.defs b/configs/stm32f103-minimum/rgbled/Make.defs new file mode 100644 index 0000000000..8d3d478305 --- /dev/null +++ b/configs/stm32f103-minimum/rgbled/Make.defs @@ -0,0 +1,113 @@ +############################################################################ +# configs/stm32f103-minimum/nsh/Make.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/stm32f103-minimum/rgbled/defconfig b/configs/stm32f103-minimum/rgbled/defconfig new file mode 100644 index 0000000000..e058bd2e53 --- /dev/null +++ b/configs/stm32f103-minimum/rgbled/defconfig @@ -0,0 +1,1184 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_DEFAULT_SMALL=y +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +CONFIG_ARCH_HAVE_HEAPCHECK=y +# CONFIG_HEAP_COLORATION is not set +# CONFIG_DEBUG_SYMBOLS is not set +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +CONFIG_ARCH_CHIP_STM32=y +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +CONFIG_ARCH_CORTEXM3=y +# CONFIG_ARCH_CORTEXM4 is not set +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="stm32" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARMV7M_LAZYFPU is not set +# CONFIG_ARCH_HAVE_FPU is not set +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y +CONFIG_ARMV7M_HAVE_STACKCHECK=y +# CONFIG_ARMV7M_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set +CONFIG_SERIAL_TERMIOS=y + +# +# STM32 Configuration Options +# +# CONFIG_ARCH_CHIP_STM32L151C6 is not set +# CONFIG_ARCH_CHIP_STM32L151C8 is not set +# CONFIG_ARCH_CHIP_STM32L151CB is not set +# CONFIG_ARCH_CHIP_STM32L151R6 is not set +# CONFIG_ARCH_CHIP_STM32L151R8 is not set +# CONFIG_ARCH_CHIP_STM32L151RB is not set +# CONFIG_ARCH_CHIP_STM32L151V6 is not set +# CONFIG_ARCH_CHIP_STM32L151V8 is not set +# CONFIG_ARCH_CHIP_STM32L151VB is not set +# CONFIG_ARCH_CHIP_STM32L152C6 is not set +# CONFIG_ARCH_CHIP_STM32L152C8 is not set +# CONFIG_ARCH_CHIP_STM32L152CB is not set +# CONFIG_ARCH_CHIP_STM32L152R6 is not set +# CONFIG_ARCH_CHIP_STM32L152R8 is not set +# CONFIG_ARCH_CHIP_STM32L152RB is not set +# CONFIG_ARCH_CHIP_STM32L152V6 is not set +# CONFIG_ARCH_CHIP_STM32L152V8 is not set +# CONFIG_ARCH_CHIP_STM32L152VB is not set +# CONFIG_ARCH_CHIP_STM32L162ZD is not set +# CONFIG_ARCH_CHIP_STM32L162VE is not set +# CONFIG_ARCH_CHIP_STM32F100C8 is not set +# CONFIG_ARCH_CHIP_STM32F100CB is not set +# CONFIG_ARCH_CHIP_STM32F100R8 is not set +# CONFIG_ARCH_CHIP_STM32F100RB is not set +# CONFIG_ARCH_CHIP_STM32F100RC is not set +# CONFIG_ARCH_CHIP_STM32F100RD is not set +# CONFIG_ARCH_CHIP_STM32F100RE is not set +# CONFIG_ARCH_CHIP_STM32F100V8 is not set +# CONFIG_ARCH_CHIP_STM32F100VB is not set +# CONFIG_ARCH_CHIP_STM32F100VC is not set +# CONFIG_ARCH_CHIP_STM32F100VD is not set +# CONFIG_ARCH_CHIP_STM32F100VE is not set +# CONFIG_ARCH_CHIP_STM32F102CB is not set +# CONFIG_ARCH_CHIP_STM32F103T8 is not set +# CONFIG_ARCH_CHIP_STM32F103TB is not set +# CONFIG_ARCH_CHIP_STM32F103C4 is not set +CONFIG_ARCH_CHIP_STM32F103C8=y +# CONFIG_ARCH_CHIP_STM32F103CB is not set +# CONFIG_ARCH_CHIP_STM32F103R8 is not set +# CONFIG_ARCH_CHIP_STM32F103RB is not set +# CONFIG_ARCH_CHIP_STM32F103RC is not set +# CONFIG_ARCH_CHIP_STM32F103RD is not set +# CONFIG_ARCH_CHIP_STM32F103RE is not set +# CONFIG_ARCH_CHIP_STM32F103RG is not set +# CONFIG_ARCH_CHIP_STM32F103V8 is not set +# CONFIG_ARCH_CHIP_STM32F103VB is not set +# CONFIG_ARCH_CHIP_STM32F103VC is not set +# CONFIG_ARCH_CHIP_STM32F103VE is not set +# CONFIG_ARCH_CHIP_STM32F103ZE is not set +# CONFIG_ARCH_CHIP_STM32F105VB is not set +# CONFIG_ARCH_CHIP_STM32F105RB is not set +# CONFIG_ARCH_CHIP_STM32F107VC is not set +# CONFIG_ARCH_CHIP_STM32F205RG is not set +# CONFIG_ARCH_CHIP_STM32F207IG is not set +# CONFIG_ARCH_CHIP_STM32F207ZE is not set +# CONFIG_ARCH_CHIP_STM32F302K6 is not set +# CONFIG_ARCH_CHIP_STM32F302K8 is not set +# CONFIG_ARCH_CHIP_STM32F302CB is not set +# CONFIG_ARCH_CHIP_STM32F302CC is not set +# CONFIG_ARCH_CHIP_STM32F302RB is not set +# CONFIG_ARCH_CHIP_STM32F302RC is not set +# CONFIG_ARCH_CHIP_STM32F302VB is not set +# CONFIG_ARCH_CHIP_STM32F302VC is not set +# CONFIG_ARCH_CHIP_STM32F303K6 is not set +# CONFIG_ARCH_CHIP_STM32F303K8 is not set +# CONFIG_ARCH_CHIP_STM32F303C6 is not set +# CONFIG_ARCH_CHIP_STM32F303C8 is not set +# CONFIG_ARCH_CHIP_STM32F303CB is not set +# CONFIG_ARCH_CHIP_STM32F303CC is not set +# CONFIG_ARCH_CHIP_STM32F303RB is not set +# CONFIG_ARCH_CHIP_STM32F303RC is not set +# CONFIG_ARCH_CHIP_STM32F303RD is not set +# CONFIG_ARCH_CHIP_STM32F303RE is not set +# CONFIG_ARCH_CHIP_STM32F303VB is not set +# CONFIG_ARCH_CHIP_STM32F303VC is not set +# CONFIG_ARCH_CHIP_STM32F372C8 is not set +# CONFIG_ARCH_CHIP_STM32F372R8 is not set +# CONFIG_ARCH_CHIP_STM32F372V8 is not set +# CONFIG_ARCH_CHIP_STM32F372CB is not set +# CONFIG_ARCH_CHIP_STM32F372RB is not set +# CONFIG_ARCH_CHIP_STM32F372VB is not set +# CONFIG_ARCH_CHIP_STM32F372CC is not set +# CONFIG_ARCH_CHIP_STM32F372RC is not set +# CONFIG_ARCH_CHIP_STM32F372VC is not set +# CONFIG_ARCH_CHIP_STM32F373C8 is not set +# CONFIG_ARCH_CHIP_STM32F373R8 is not set +# CONFIG_ARCH_CHIP_STM32F373V8 is not set +# CONFIG_ARCH_CHIP_STM32F373CB is not set +# CONFIG_ARCH_CHIP_STM32F373RB is not set +# CONFIG_ARCH_CHIP_STM32F373VB is not set +# CONFIG_ARCH_CHIP_STM32F373CC is not set +# CONFIG_ARCH_CHIP_STM32F373RC is not set +# CONFIG_ARCH_CHIP_STM32F373VC is not set +# CONFIG_ARCH_CHIP_STM32F401RE is not set +# CONFIG_ARCH_CHIP_STM32F411RE is not set +# CONFIG_ARCH_CHIP_STM32F411VE is not set +# CONFIG_ARCH_CHIP_STM32F405RG is not set +# CONFIG_ARCH_CHIP_STM32F405VG is not set +# CONFIG_ARCH_CHIP_STM32F405ZG is not set +# CONFIG_ARCH_CHIP_STM32F407VE is not set +# CONFIG_ARCH_CHIP_STM32F407VG is not set +# CONFIG_ARCH_CHIP_STM32F407ZE is not set +# CONFIG_ARCH_CHIP_STM32F407ZG is not set +# CONFIG_ARCH_CHIP_STM32F407IE is not set +# CONFIG_ARCH_CHIP_STM32F407IG is not set +# CONFIG_ARCH_CHIP_STM32F427V is not set +# CONFIG_ARCH_CHIP_STM32F427Z is not set +# CONFIG_ARCH_CHIP_STM32F427I is not set +# CONFIG_ARCH_CHIP_STM32F429V is not set +# CONFIG_ARCH_CHIP_STM32F429Z is not set +# CONFIG_ARCH_CHIP_STM32F429I is not set +# CONFIG_ARCH_CHIP_STM32F429B is not set +# CONFIG_ARCH_CHIP_STM32F429N is not set +# CONFIG_ARCH_CHIP_STM32F446M is not set +# CONFIG_ARCH_CHIP_STM32F446R is not set +# CONFIG_ARCH_CHIP_STM32F446V is not set +# CONFIG_ARCH_CHIP_STM32F446Z is not set +# CONFIG_ARCH_CHIP_STM32F469A is not set +# CONFIG_ARCH_CHIP_STM32F469I is not set +# CONFIG_ARCH_CHIP_STM32F469B is not set +# CONFIG_ARCH_CHIP_STM32F469N is not set +CONFIG_STM32_FLASH_CONFIG_DEFAULT=y +# CONFIG_STM32_FLASH_CONFIG_4 is not set +# CONFIG_STM32_FLASH_CONFIG_6 is not set +# CONFIG_STM32_FLASH_CONFIG_8 is not set +# CONFIG_STM32_FLASH_CONFIG_B is not set +# CONFIG_STM32_FLASH_CONFIG_C is not set +# CONFIG_STM32_FLASH_CONFIG_D is not set +# CONFIG_STM32_FLASH_CONFIG_E is not set +# CONFIG_STM32_FLASH_CONFIG_F is not set +# CONFIG_STM32_FLASH_CONFIG_G is not set +# CONFIG_STM32_FLASH_CONFIG_I is not set +# CONFIG_STM32_STM32L15XX is not set +# CONFIG_STM32_ENERGYLITE is not set +CONFIG_STM32_STM32F10XX=y +# CONFIG_STM32_VALUELINE is not set +# CONFIG_STM32_CONNECTIVITYLINE is not set +CONFIG_STM32_PERFORMANCELINE=y +# CONFIG_STM32_USBACCESSLINE is not set +# CONFIG_STM32_HIGHDENSITY is not set +CONFIG_STM32_MEDIUMDENSITY=y +# CONFIG_STM32_LOWDENSITY is not set +# CONFIG_STM32_STM32F20XX is not set +# CONFIG_STM32_STM32F205 is not set +# CONFIG_STM32_STM32F207 is not set +# CONFIG_STM32_STM32F30XX is not set +# CONFIG_STM32_STM32F302 is not set +# CONFIG_STM32_STM32F303 is not set +# CONFIG_STM32_STM32F37XX is not set +# CONFIG_STM32_STM32F40XX is not set +# CONFIG_STM32_STM32F401 is not set +# CONFIG_STM32_STM32F411 is not set +# CONFIG_STM32_STM32F405 is not set +# CONFIG_STM32_STM32F407 is not set +# CONFIG_STM32_STM32F427 is not set +# CONFIG_STM32_STM32F429 is not set +# CONFIG_STM32_STM32F446 is not set +# CONFIG_STM32_STM32F469 is not set +# CONFIG_STM32_DFU is not set + +# +# STM32 Peripheral Support +# +# CONFIG_STM32_HAVE_CCM is not set +CONFIG_STM32_HAVE_USBDEV=y +# CONFIG_STM32_HAVE_OTGFS is not set +# CONFIG_STM32_HAVE_FSMC is not set +# CONFIG_STM32_HAVE_LTDC is not set +CONFIG_STM32_HAVE_USART3=y +CONFIG_STM32_HAVE_UART4=y +CONFIG_STM32_HAVE_UART5=y +# CONFIG_STM32_HAVE_USART6 is not set +# CONFIG_STM32_HAVE_UART7 is not set +# CONFIG_STM32_HAVE_UART8 is not set +CONFIG_STM32_HAVE_TIM1=y +# CONFIG_STM32_HAVE_TIM2 is not set +CONFIG_STM32_HAVE_TIM3=y +CONFIG_STM32_HAVE_TIM4=y +CONFIG_STM32_HAVE_TIM5=y +CONFIG_STM32_HAVE_TIM6=y +CONFIG_STM32_HAVE_TIM7=y +CONFIG_STM32_HAVE_TIM8=y +# CONFIG_STM32_HAVE_TIM9 is not set +# CONFIG_STM32_HAVE_TIM10 is not set +# CONFIG_STM32_HAVE_TIM11 is not set +# CONFIG_STM32_HAVE_TIM12 is not set +# CONFIG_STM32_HAVE_TIM13 is not set +# CONFIG_STM32_HAVE_TIM14 is not set +# CONFIG_STM32_HAVE_TIM15 is not set +# CONFIG_STM32_HAVE_TIM16 is not set +# CONFIG_STM32_HAVE_TIM17 is not set +CONFIG_STM32_HAVE_ADC2=y +CONFIG_STM32_HAVE_ADC3=y +# CONFIG_STM32_HAVE_ADC4 is not set +# CONFIG_STM32_HAVE_ADC1_DMA is not set +# CONFIG_STM32_HAVE_ADC2_DMA is not set +# CONFIG_STM32_HAVE_ADC3_DMA is not set +# CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set +CONFIG_STM32_HAVE_CAN1=y +# CONFIG_STM32_HAVE_CAN2 is not set +# CONFIG_STM32_HAVE_DAC1 is not set +# CONFIG_STM32_HAVE_DAC2 is not set +# CONFIG_STM32_HAVE_RNG is not set +# CONFIG_STM32_HAVE_ETHMAC is not set +CONFIG_STM32_HAVE_I2C2=y +# CONFIG_STM32_HAVE_I2C3 is not set +CONFIG_STM32_HAVE_SPI2=y +CONFIG_STM32_HAVE_SPI3=y +# CONFIG_STM32_HAVE_SPI4 is not set +# CONFIG_STM32_HAVE_SPI5 is not set +# CONFIG_STM32_HAVE_SPI6 is not set +# CONFIG_STM32_HAVE_SAIPLL is not set +# CONFIG_STM32_HAVE_I2SPLL is not set +# CONFIG_STM32_ADC1 is not set +# CONFIG_STM32_ADC2 is not set +# CONFIG_STM32_ADC3 is not set +# CONFIG_STM32_BKP is not set +# CONFIG_STM32_CAN1 is not set +# CONFIG_STM32_CRC is not set +# CONFIG_STM32_DMA1 is not set +# CONFIG_STM32_DMA2 is not set +# CONFIG_STM32_I2C1 is not set +# CONFIG_STM32_I2C2 is not set +# CONFIG_STM32_PWR is not set +# CONFIG_STM32_SDIO is not set +# CONFIG_STM32_SPI1 is not set +# CONFIG_STM32_SPI2 is not set +# CONFIG_STM32_SPI3 is not set +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM4=y +# CONFIG_STM32_TIM5 is not set +# CONFIG_STM32_TIM6 is not set +# CONFIG_STM32_TIM7 is not set +# CONFIG_STM32_TIM8 is not set +CONFIG_STM32_USART1=y +# CONFIG_STM32_USART2 is not set +# CONFIG_STM32_USART3 is not set +# CONFIG_STM32_UART4 is not set +# CONFIG_STM32_UART5 is not set +# CONFIG_STM32_USB is not set +# CONFIG_STM32_IWDG is not set +# CONFIG_STM32_WWDG is not set +# CONFIG_STM32_NOEXT_VECTORS is not set + +# +# Alternate Pin Mapping +# +CONFIG_STM32_TIM1_NO_REMAP=y +# CONFIG_STM32_TIM1_FULL_REMAP is not set +# CONFIG_STM32_TIM1_PARTIAL_REMAP is not set +CONFIG_STM32_TIM2_NO_REMAP=y +# CONFIG_STM32_TIM2_FULL_REMAP is not set +# CONFIG_STM32_TIM2_PARTIAL_REMAP_1 is not set +# CONFIG_STM32_TIM2_PARTIAL_REMAP_2 is not set +CONFIG_STM32_TIM3_NO_REMAP=y +# CONFIG_STM32_TIM3_FULL_REMAP is not set +# CONFIG_STM32_TIM3_PARTIAL_REMAP is not set +# CONFIG_STM32_TIM4_REMAP is not set +# CONFIG_STM32_USART1_REMAP is not set +# CONFIG_STM32_JTAG_DISABLE is not set +CONFIG_STM32_JTAG_FULL_ENABLE=y +# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set +# CONFIG_STM32_JTAG_SW_ENABLE is not set +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +# CONFIG_STM32_FORCEPOWER is not set +# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set + +# +# Timer Configuration +# +# CONFIG_STM32_ONESHOT is not set +# CONFIG_STM32_FREERUN is not set +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM1_MODE=0 +CONFIG_STM32_TIM1_CHANNEL=1 +CONFIG_STM32_TIM1_CHMODE=0 +CONFIG_STM32_TIM2_PWM=y +CONFIG_STM32_TIM2_MODE=0 +CONFIG_STM32_TIM2_CHANNEL=2 +CONFIG_STM32_TIM2_CHMODE=0 +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_TIM3_MODE=0 +CONFIG_STM32_TIM3_CHANNEL=3 +CONFIG_STM32_TIM3_CHMODE=0 +CONFIG_STM32_TIM4_PWM=y +CONFIG_STM32_TIM4_MODE=0 +CONFIG_STM32_TIM4_CHANNEL=4 +CONFIG_STM32_TIM4_CHMODE=0 +# CONFIG_STM32_PWM_MULTICHAN is not set +# CONFIG_STM32_TIM1_CAP is not set +# CONFIG_STM32_TIM3_CAP is not set +# CONFIG_STM32_TIM4_CAP is not set +# CONFIG_STM32_TIM5_CAP is not set +# CONFIG_STM32_TIM8_CAP is not set +CONFIG_STM32_USART=y +CONFIG_STM32_SERIALDRIVER=y + +# +# U[S]ART Configuration +# + +# +# U[S]ART Device Configuration +# +CONFIG_STM32_USART1_SERIALDRIVER=y +# CONFIG_STM32_USART1_1WIREDRIVER is not set +# CONFIG_USART1_RS485 is not set + +# +# Serial Driver Configuration +# +# CONFIG_SERIAL_DISABLE_REORDERING is not set +# CONFIG_STM32_FLOWCONTROL_BROKEN is not set +# CONFIG_STM32_USART_BREAKS is not set +# CONFIG_STM32_USART_SINGLEWIRE is not set +CONFIG_STM32_HAVE_RTC_COUNTER=y +# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set + +# +# USB FS Host Configuration +# + +# +# USB HS Host Configuration +# + +# +# USB Host Debug Configuration +# + +# +# USB Device Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=5483 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_SIZE=20480 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +# CONFIG_ARCH_BOARD_STM32_TINY is not set +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="stm32f103-minimum" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +# CONFIG_ARCH_BUTTONS is not set +CONFIG_ARCH_HAVE_IRQBUTTONS=y + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_RESET is not set +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_ADCTEST is not set +# CONFIG_BOARDCTL_PWMTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set + +# +# RTOS Features +# +# CONFIG_DISABLE_OS_API is not set + +# +# Clocks and Timers +# +CONFIG_ARCH_HAVE_TICKLESS=y +# CONFIG_SCHED_TICKLESS is not set +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +CONFIG_ARCH_HAVE_TIMEKEEPING=y +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2011 +CONFIG_START_MONTH=7 +CONFIG_START_DAY=5 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=0 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +# CONFIG_DISABLE_POLL is not set +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +CONFIG_ARCH_HAVE_PWM_PULSECOUNT=y +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +CONFIG_PWM=y +# CONFIG_PWM_PULSECOUNT is not set +CONFIG_ARCH_HAVE_I2CRESET=y +# CONFIG_I2C is not set +# CONFIG_SPI is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +CONFIG_RGBLED=y +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +CONFIG_USART1_SERIALDRIVER=y +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_SERIAL_NPOLLWAITERS=2 +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +CONFIG_USART1_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# USART1 Configuration +# +CONFIG_USART1_RXBUFSIZE=256 +CONFIG_USART1_TXBUFSIZE=256 +CONFIG_USART1_BAUD=115200 +CONFIG_USART1_BITS=8 +CONFIG_USART1_PARITY=0 +CONFIG_USART1_2STOP=0 +# CONFIG_USART1_IFLOWCONTROL is not set +# CONFIG_USART1_OFLOWCONTROL is not set +# CONFIG_USART1_DMA is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +# CONFIG_FS_READABLE is not set +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +CONFIG_SYMTAB_ORDEREDBYNAME=y + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_LIBC_LONG_LONG is not set +# CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set +# CONFIG_LIBC_NETDB is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_PWM is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +CONFIG_EXAMPLES_RGBLED=y +CONFIG_EXAMPLES_RGBLED_DEVNAME="/dev/rgbled0" +CONFIG_EXAMPLES_RGBLED_PRIORITY=100 +CONFIG_EXAMPLES_RGBLED_STACKSIZE=2048 +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CHAT is not set +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=80 +CONFIG_NSH_DISABLE_SEMICOLON=y +# CONFIG_NSH_CMDPARMS is not set +CONFIG_NSH_MAXARGUMENTS=6 +# CONFIG_NSH_ARGCAT is not set +CONFIG_NSH_NESTDEPTH=3 +CONFIG_NSH_DISABLEBG=y +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +CONFIG_NSH_DISABLE_ADDROUTE=y +CONFIG_NSH_DISABLE_BASENAME=y +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +CONFIG_NSH_DISABLE_DF=y +CONFIG_NSH_DISABLE_DELROUTE=y +CONFIG_NSH_DISABLE_DIRNAME=y +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +CONFIG_NSH_DISABLE_IFCONFIG=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_KILL is not set +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +CONFIG_NSH_DISABLE_TIME=y +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +CONFIG_NSH_DISABLE_UNAME=y +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Configure Command Options +# +CONFIG_NSH_CODECS_BUFSIZE=128 +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_NSH_FILEIOSIZE=1024 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +CONFIG_NSH_DISABLE_ITEF=y +CONFIG_NSH_DISABLE_LOOPS=y + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm32f103-minimum/rgbled/setenv.sh b/configs/stm32f103-minimum/rgbled/setenv.sh new file mode 100644 index 0000000000..73dfab5a4d --- /dev/null +++ b/configs/stm32f103-minimum/rgbled/setenv.sh @@ -0,0 +1,100 @@ +#!/bin/bash +# configs//stm32f103-minimum/nsh/setenv.sh +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" +# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" +# You can this free toolchain here https://launchpad.net/gcc-arm-embedded +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" + +# This is the path to the location where I installed the devkitARM toolchain +# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/ +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" -- GitLab From c52ee46f5faafcb8cf63cd2fcae1c8984379c5fe Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 27 Oct 2016 16:02:04 -0600 Subject: [PATCH 237/734] ESP32: More logic added to serial driver. --- arch/xtensa/src/esp32/chip/esp32_uart.h | 102 ++++++++++++------------ arch/xtensa/src/esp32/esp32_serial.c | 57 ++++++------- 2 files changed, 80 insertions(+), 79 deletions(-) diff --git a/arch/xtensa/src/esp32/chip/esp32_uart.h b/arch/xtensa/src/esp32/chip/esp32_uart.h index 8e86e436b3..0e248a4ea9 100644 --- a/arch/xtensa/src/esp32/chip/esp32_uart.h +++ b/arch/xtensa/src/esp32/chip/esp32_uart.h @@ -43,10 +43,10 @@ #define UART_FIFO_REG(i) (REG_UART_BASE(i) + UART_FIFO_OFFSET) /* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */ -/* Description: This register stores one byte data read by rx fifo.*/ +/* Description: This register stores one byte data read by rx fifo.*/ #define UART_RXFIFO_RD_BYTE 0x000000FF -#define UART_RXFIFO_RD_BYTE_M ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S)) +#define UART_RXFIFO_RD_BYTE_M ((UART_RXFIFO_RD_BYTE_V) << (UART_RXFIFO_RD_BYTE_S)) #define UART_RXFIFO_RD_BYTE_V 0xFF #define UART_RXFIFO_RD_BYTE_S 0 @@ -55,7 +55,7 @@ /* UART_AT_CMD_CHAR_DET_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ /* Description: This interrupt raw bit turns to high level when receiver - * detects the configured at_cmd chars. + * detects the configured at_cmd chars. */ #define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) @@ -575,7 +575,7 @@ #define UART_PARITY_ERR_INT_ENA_S 2 /* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/* Description: This is the enable bit for rxfifo_full_int_st register.*/ +/* Description: This is the enable bit for txfifo_fifo_int_st register.*/ #define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) #define UART_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) @@ -758,7 +758,7 @@ */ #define UART_CLKDIV_FRAG 0x0000000F -#define UART_CLKDIV_FRAG_M ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S)) +#define UART_CLKDIV_FRAG_M ((UART_CLKDIV_FRAG_V) << (UART_CLKDIV_FRAG_S)) #define UART_CLKDIV_FRAG_V 0xF #define UART_CLKDIV_FRAG_S 20 @@ -768,7 +768,7 @@ */ #define UART_CLKDIV 0x000FFFFF -#define UART_CLKDIV_M ((UART_CLKDIV_V)<<(UART_CLKDIV_S)) +#define UART_CLKDIV_M ((UART_CLKDIV_V) << (UART_CLKDIV_S)) #define UART_CLKDIV_V 0xFFFFF #define UART_CLKDIV_S 0 @@ -781,7 +781,7 @@ */ #define UART_GLITCH_FILT 0x000000FF -#define UART_GLITCH_FILT_M ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S)) +#define UART_GLITCH_FILT_M ((UART_GLITCH_FILT_V) << (UART_GLITCH_FILT_S)) #define UART_GLITCH_FILT_V 0xFF #define UART_GLITCH_FILT_S 8 @@ -797,7 +797,7 @@ #define UART_STATUS_REG(i) (REG_UART_BASE(i) + UART_STATUS_OFFSET) /* UART_TXD : RO ;bitpos:[31] ;default: 8'h0 ; */ -/* Description: This register represent the level value of the internal +/* Description: This register represent the level value of the internal * uart rxd signal. */ @@ -834,7 +834,7 @@ */ #define UART_ST_UTX_OUT 0x0000000F -#define UART_ST_UTX_OUT_M ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S)) +#define UART_ST_UTX_OUT_M ((UART_ST_UTX_OUT_V) << (UART_ST_UTX_OUT_S)) #define UART_ST_UTX_OUT_V 0xF #define UART_ST_UTX_OUT_S 24 @@ -845,7 +845,7 @@ */ #define UART_TXFIFO_CNT 0x000000FF -#define UART_TXFIFO_CNT_M ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S)) +#define UART_TXFIFO_CNT_M ((UART_TXFIFO_CNT_V) << (UART_TXFIFO_CNT_S)) #define UART_TXFIFO_CNT_V 0xFF #define UART_TXFIFO_CNT_S 16 @@ -888,7 +888,7 @@ */ #define UART_ST_URX_OUT 0x0000000F -#define UART_ST_URX_OUT_M ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S)) +#define UART_ST_URX_OUT_M ((UART_ST_URX_OUT_V) << (UART_ST_URX_OUT_S)) #define UART_ST_URX_OUT_V 0xF #define UART_ST_URX_OUT_S 8 @@ -899,7 +899,7 @@ */ #define UART_RXFIFO_CNT 0x000000FF -#define UART_RXFIFO_CNT_M ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S)) +#define UART_RXFIFO_CNT_M ((UART_RXFIFO_CNT_V) << (UART_RXFIFO_CNT_S)) #define UART_RXFIFO_CNT_V 0xFF #define UART_RXFIFO_CNT_S 0 @@ -1104,7 +1104,7 @@ */ #define UART_STOP_BIT_NUM 0x00000003 -#define UART_STOP_BIT_NUM_M ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S)) +#define UART_STOP_BIT_NUM_M ((UART_STOP_BIT_NUM_V) << (UART_STOP_BIT_NUM_S)) #define UART_STOP_BIT_NUM_V 0x3 #define UART_STOP_BIT_NUM_S 4 @@ -1114,7 +1114,7 @@ */ #define UART_BIT_NUM 0x00000003 -#define UART_BIT_NUM_M ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S)) +#define UART_BIT_NUM_M ((UART_BIT_NUM_V) << (UART_BIT_NUM_S)) #define UART_BIT_NUM_V 0x3 #define UART_BIT_NUM_S 2 @@ -1153,7 +1153,7 @@ */ #define UART_RX_TOUT_THRHD 0x0000007F -#define UART_RX_TOUT_THRHD_M ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S)) +#define UART_RX_TOUT_THRHD_M ((UART_RX_TOUT_THRHD_V) << (UART_RX_TOUT_THRHD_S)) #define UART_RX_TOUT_THRHD_V 0x7F #define UART_RX_TOUT_THRHD_S 24 @@ -1174,7 +1174,7 @@ */ #define UART_RX_FLOW_THRHD 0x0000007F -#define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S)) +#define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V) << (UART_RX_FLOW_THRHD_S)) #define UART_RX_FLOW_THRHD_V 0x7F #define UART_RX_FLOW_THRHD_S 16 @@ -1185,7 +1185,7 @@ */ #define UART_TXFIFO_EMPTY_THRHD 0x0000007F -#define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S)) +#define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V) << (UART_TXFIFO_EMPTY_THRHD_S)) #define UART_TXFIFO_EMPTY_THRHD_V 0x7F #define UART_TXFIFO_EMPTY_THRHD_S 8 @@ -1196,7 +1196,7 @@ */ #define UART_RXFIFO_FULL_THRHD 0x0000007F -#define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S)) +#define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V) << (UART_RXFIFO_FULL_THRHD_S)) #define UART_RXFIFO_FULL_THRHD_V 0x7F #define UART_RXFIFO_FULL_THRHD_S 0 @@ -1209,7 +1209,7 @@ */ #define UART_LOWPULSE_MIN_CNT 0x000FFFFF -#define UART_LOWPULSE_MIN_CNT_M ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S)) +#define UART_LOWPULSE_MIN_CNT_M ((UART_LOWPULSE_MIN_CNT_V) << (UART_LOWPULSE_MIN_CNT_S)) #define UART_LOWPULSE_MIN_CNT_V 0xFFFFF #define UART_LOWPULSE_MIN_CNT_S 0 @@ -1222,7 +1222,7 @@ */ #define UART_HIGHPULSE_MIN_CNT 0x000FFFFF -#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S)) +#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V) << (UART_HIGHPULSE_MIN_CNT_S)) #define UART_HIGHPULSE_MIN_CNT_V 0xFFFFF #define UART_HIGHPULSE_MIN_CNT_S 0 @@ -1235,7 +1235,7 @@ */ #define UART_RXD_EDGE_CNT 0x000003FF -#define UART_RXD_EDGE_CNT_M ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S)) +#define UART_RXD_EDGE_CNT_M ((UART_RXD_EDGE_CNT_V) << (UART_RXD_EDGE_CNT_S)) #define UART_RXD_EDGE_CNT_V 0x3FF #define UART_RXD_EDGE_CNT_S 0 @@ -1311,7 +1311,7 @@ */ #define UART_ACTIVE_THRESHOLD 0x000003FF -#define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S)) +#define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V) << (UART_ACTIVE_THRESHOLD_S)) #define UART_ACTIVE_THRESHOLD_V 0x3FF #define UART_ACTIVE_THRESHOLD_S 0 @@ -1322,7 +1322,7 @@ /* Description: This register stores the xoff flow control char.*/ #define UART_XOFF_CHAR 0x000000FF -#define UART_XOFF_CHAR_M ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S)) +#define UART_XOFF_CHAR_M ((UART_XOFF_CHAR_V) << (UART_XOFF_CHAR_S)) #define UART_XOFF_CHAR_V 0xFF #define UART_XOFF_CHAR_S 24 @@ -1330,7 +1330,7 @@ /* Description: This register stores the xon flow control char.*/ #define UART_XON_CHAR 0x000000FF -#define UART_XON_CHAR_M ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S)) +#define UART_XON_CHAR_M ((UART_XON_CHAR_V) << (UART_XON_CHAR_S)) #define UART_XON_CHAR_V 0xFF #define UART_XON_CHAR_S 16 @@ -1341,7 +1341,7 @@ */ #define UART_XOFF_THRESHOLD 0x000000FF -#define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S)) +#define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V) << (UART_XOFF_THRESHOLD_S)) #define UART_XOFF_THRESHOLD_V 0xFF #define UART_XOFF_THRESHOLD_S 8 @@ -1352,7 +1352,7 @@ */ #define UART_XON_THRESHOLD 0x000000FF -#define UART_XON_THRESHOLD_M ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S)) +#define UART_XON_THRESHOLD_M ((UART_XON_THRESHOLD_V) << (UART_XON_THRESHOLD_S)) #define UART_XON_THRESHOLD_V 0xFF #define UART_XON_THRESHOLD_S 0 @@ -1366,7 +1366,7 @@ */ #define UART_TX_BRK_NUM 0x000000FF -#define UART_TX_BRK_NUM_M ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S)) +#define UART_TX_BRK_NUM_M ((UART_TX_BRK_NUM_V) << (UART_TX_BRK_NUM_S)) #define UART_TX_BRK_NUM_V 0xFF #define UART_TX_BRK_NUM_S 20 @@ -1376,7 +1376,7 @@ */ #define UART_TX_IDLE_NUM 0x000003FF -#define UART_TX_IDLE_NUM_M ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S)) +#define UART_TX_IDLE_NUM_M ((UART_TX_IDLE_NUM_V) << (UART_TX_IDLE_NUM_S)) #define UART_TX_IDLE_NUM_V 0x3FF #define UART_TX_IDLE_NUM_S 10 @@ -1387,7 +1387,7 @@ */ #define UART_RX_IDLE_THRHD 0x000003FF -#define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S)) +#define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V) << (UART_RX_IDLE_THRHD_S)) #define UART_RX_IDLE_THRHD_V 0x3FF #define UART_RX_IDLE_THRHD_S 0 @@ -1400,7 +1400,7 @@ */ #define UART_RS485_TX_DLY_NUM 0x0000000F -#define UART_RS485_TX_DLY_NUM_M ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S)) +#define UART_RS485_TX_DLY_NUM_M ((UART_RS485_TX_DLY_NUM_V) << (UART_RS485_TX_DLY_NUM_S)) #define UART_RS485_TX_DLY_NUM_V 0xF #define UART_RS485_TX_DLY_NUM_S 6 @@ -1470,7 +1470,7 @@ */ #define UART_PRE_IDLE_NUM 0x00FFFFFF -#define UART_PRE_IDLE_NUM_M ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S)) +#define UART_PRE_IDLE_NUM_M ((UART_PRE_IDLE_NUM_V) << (UART_PRE_IDLE_NUM_S)) #define UART_PRE_IDLE_NUM_V 0xFFFFFF #define UART_PRE_IDLE_NUM_S 0 @@ -1484,7 +1484,7 @@ */ #define UART_POST_IDLE_NUM 0x00FFFFFF -#define UART_POST_IDLE_NUM_M ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S)) +#define UART_POST_IDLE_NUM_M ((UART_POST_IDLE_NUM_V) << (UART_POST_IDLE_NUM_S)) #define UART_POST_IDLE_NUM_V 0xFFFFFF #define UART_POST_IDLE_NUM_S 0 @@ -1498,7 +1498,7 @@ */ #define UART_RX_GAP_TOUT 0x00FFFFFF -#define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S)) +#define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V) << (UART_RX_GAP_TOUT_S)) #define UART_RX_GAP_TOUT_V 0xFFFFFF #define UART_RX_GAP_TOUT_S 0 @@ -1511,7 +1511,7 @@ */ #define UART_CHAR_NUM 0x000000FF -#define UART_CHAR_NUM_M ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S)) +#define UART_CHAR_NUM_M ((UART_CHAR_NUM_V) << (UART_CHAR_NUM_S)) #define UART_CHAR_NUM_V 0xFF #define UART_CHAR_NUM_S 8 @@ -1521,7 +1521,7 @@ */ #define UART_AT_CMD_CHAR 0x000000FF -#define UART_AT_CMD_CHAR_M ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S)) +#define UART_AT_CMD_CHAR_M ((UART_AT_CMD_CHAR_V) << (UART_AT_CMD_CHAR_S)) #define UART_AT_CMD_CHAR_V 0xFF #define UART_AT_CMD_CHAR_S 0 @@ -1532,7 +1532,7 @@ /* Description: refer to txfifo_empty_thrhd 's describtion.*/ #define UART_TX_MEM_EMPTY_THRHD 0x00000007 -#define UART_TX_MEM_EMPTY_THRHD_M ((UART_TX_MEM_EMPTY_THRHD_V)<<(UART_TX_MEM_EMPTY_THRHD_S)) +#define UART_TX_MEM_EMPTY_THRHD_M ((UART_TX_MEM_EMPTY_THRHD_V) << (UART_TX_MEM_EMPTY_THRHD_S)) #define UART_TX_MEM_EMPTY_THRHD_V 0x7 #define UART_TX_MEM_EMPTY_THRHD_S 28 @@ -1540,7 +1540,7 @@ /* Description: refer to the rxfifo_full_thrhd's describtion.*/ #define UART_RX_MEM_FULL_THRHD 0x00000007 -#define UART_RX_MEM_FULL_THRHD_M ((UART_RX_MEM_FULL_THRHD_V)<<(UART_RX_MEM_FULL_THRHD_S)) +#define UART_RX_MEM_FULL_THRHD_M ((UART_RX_MEM_FULL_THRHD_V) << (UART_RX_MEM_FULL_THRHD_S)) #define UART_RX_MEM_FULL_THRHD_V 0x7 #define UART_RX_MEM_FULL_THRHD_S 25 @@ -1548,7 +1548,7 @@ /* Description: refer to the uart_xoff_threshold's describtion.*/ #define UART_XOFF_THRESHOLD_H2 0x00000003 -#define UART_XOFF_THRESHOLD_H2_M ((UART_XOFF_THRESHOLD_H2_V)<<(UART_XOFF_THRESHOLD_H2_S)) +#define UART_XOFF_THRESHOLD_H2_M ((UART_XOFF_THRESHOLD_H2_V) << (UART_XOFF_THRESHOLD_H2_S)) #define UART_XOFF_THRESHOLD_H2_V 0x3 #define UART_XOFF_THRESHOLD_H2_S 23 @@ -1556,7 +1556,7 @@ /* Description: refer to the uart_xon_threshold's describtion.*/ #define UART_XON_THRESHOLD_H2 0x00000003 -#define UART_XON_THRESHOLD_H2_M ((UART_XON_THRESHOLD_H2_V)<<(UART_XON_THRESHOLD_H2_S)) +#define UART_XON_THRESHOLD_H2_M ((UART_XON_THRESHOLD_H2_V) << (UART_XON_THRESHOLD_H2_S)) #define UART_XON_THRESHOLD_H2_V 0x3 #define UART_XON_THRESHOLD_H2_S 21 @@ -1564,7 +1564,7 @@ /* Description: refer to the rx_tout_thrhd's describtion.*/ #define UART_RX_TOUT_THRHD_H3 0x00000007 -#define UART_RX_TOUT_THRHD_H3_M ((UART_RX_TOUT_THRHD_H3_V)<<(UART_RX_TOUT_THRHD_H3_S)) +#define UART_RX_TOUT_THRHD_H3_M ((UART_RX_TOUT_THRHD_H3_V) << (UART_RX_TOUT_THRHD_H3_S)) #define UART_RX_TOUT_THRHD_H3_V 0x7 #define UART_RX_TOUT_THRHD_H3_S 18 @@ -1572,7 +1572,7 @@ /* Description: refer to the rx_flow_thrhd's describtion.*/ #define UART_RX_FLOW_THRHD_H3 0x00000007 -#define UART_RX_FLOW_THRHD_H3_M ((UART_RX_FLOW_THRHD_H3_V)<<(UART_RX_FLOW_THRHD_H3_S)) +#define UART_RX_FLOW_THRHD_H3_M ((UART_RX_FLOW_THRHD_H3_V) << (UART_RX_FLOW_THRHD_H3_S)) #define UART_RX_FLOW_THRHD_H3_V 0x7 #define UART_RX_FLOW_THRHD_H3_S 15 @@ -1582,7 +1582,7 @@ */ #define UART_TX_SIZE 0x0000000F -#define UART_TX_SIZE_M ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S)) +#define UART_TX_SIZE_M ((UART_TX_SIZE_V) << (UART_TX_SIZE_S)) #define UART_TX_SIZE_V 0xF #define UART_TX_SIZE_S 7 @@ -1592,7 +1592,7 @@ */ #define UART_RX_SIZE 0x0000000F -#define UART_RX_SIZE_M ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S)) +#define UART_RX_SIZE_M ((UART_RX_SIZE_V) << (UART_RX_SIZE_S)) #define UART_RX_SIZE_V 0xF #define UART_RX_SIZE_S 3 @@ -1613,7 +1613,7 @@ /* Description: */ #define UART_MEM_TX_STATUS 0x00FFFFFF -#define UART_MEM_TX_STATUS_M ((UART_MEM_TX_STATUS_V)<<(UART_MEM_TX_STATUS_S)) +#define UART_MEM_TX_STATUS_M ((UART_MEM_TX_STATUS_V) << (UART_MEM_TX_STATUS_S)) #define UART_MEM_TX_STATUS_V 0xFFFFFF #define UART_MEM_TX_STATUS_S 0 @@ -1624,7 +1624,7 @@ /* Description: */ #define UART_MEM_RX_STATUS 0x00FFFFFF -#define UART_MEM_RX_STATUS_M ((UART_MEM_RX_STATUS_V)<<(UART_MEM_RX_STATUS_S)) +#define UART_MEM_RX_STATUS_M ((UART_MEM_RX_STATUS_V) << (UART_MEM_RX_STATUS_S)) #define UART_MEM_RX_STATUS_V 0xFFFFFF #define UART_MEM_RX_STATUS_S 0 @@ -1635,7 +1635,7 @@ /* Description: refer to the txfifo_cnt's describtion.*/ #define UART_TX_MEM_CNT 0x00000007 -#define UART_TX_MEM_CNT_M ((UART_TX_MEM_CNT_V)<<(UART_TX_MEM_CNT_S)) +#define UART_TX_MEM_CNT_M ((UART_TX_MEM_CNT_V) << (UART_TX_MEM_CNT_S)) #define UART_TX_MEM_CNT_V 0x7 #define UART_TX_MEM_CNT_S 3 @@ -1643,7 +1643,7 @@ /* Description: refer to the rxfifo_cnt's describtion.*/ #define UART_RX_MEM_CNT 0x00000007 -#define UART_RX_MEM_CNT_M ((UART_RX_MEM_CNT_V)<<(UART_RX_MEM_CNT_S)) +#define UART_RX_MEM_CNT_M ((UART_RX_MEM_CNT_V) << (UART_RX_MEM_CNT_S)) #define UART_RX_MEM_CNT_V 0x7 #define UART_RX_MEM_CNT_S 0 @@ -1656,7 +1656,7 @@ */ #define UART_POSEDGE_MIN_CNT 0x000FFFFF -#define UART_POSEDGE_MIN_CNT_M ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S)) +#define UART_POSEDGE_MIN_CNT_M ((UART_POSEDGE_MIN_CNT_V) << (UART_POSEDGE_MIN_CNT_S)) #define UART_POSEDGE_MIN_CNT_V 0xFFFFF #define UART_POSEDGE_MIN_CNT_S 0 @@ -1669,7 +1669,7 @@ */ #define UART_NEGEDGE_MIN_CNT 0x000FFFFF -#define UART_NEGEDGE_MIN_CNT_M ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S)) +#define UART_NEGEDGE_MIN_CNT_M ((UART_NEGEDGE_MIN_CNT_V) << (UART_NEGEDGE_MIN_CNT_S)) #define UART_NEGEDGE_MIN_CNT_V 0xFFFFF #define UART_NEGEDGE_MIN_CNT_S 0 @@ -1680,7 +1680,7 @@ /* Description: */ #define UART_DATE 0xFFFFFFFF -#define UART_DATE_M ((UART_DATE_V)<<(UART_DATE_S)) +#define UART_DATE_M ((UART_DATE_V) << (UART_DATE_S)) #define UART_DATE_V 0xFFFFFFFF #define UART_DATE_S 0 @@ -1691,7 +1691,7 @@ /* Description: */ #define UART_ID 0xFFFFFFFF -#define UART_ID_M ((UART_ID_V)<<(UART_ID_S)) +#define UART_ID_M ((UART_ID_V) << (UART_ID_S)) #define UART_ID_V 0xFFFFFFFF #define UART_ID_S 0 diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c index eb6bd3c8cf..08dd5d84bf 100644 --- a/arch/xtensa/src/esp32/esp32_serial.c +++ b/arch/xtensa/src/esp32/esp32_serial.c @@ -713,12 +713,11 @@ static void esp32_detach(struct uart_dev_s *dev) static int esp32_interrupt(struct uart_dev_s *dev) { struct esp32_dev_s *priv; - uint32_t pending; - uint32_t intena; - int passes; - bool handled; + uint32_t regval; + int passes; + bool handled; - DEBUGASSERT(dev && dev->priv); + DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct esp32_dev_s *)dev->priv; /* Loop until there are no characters to be transferred or, until we have @@ -730,31 +729,24 @@ static int esp32_interrupt(struct uart_dev_s *dev) { handled = false; - /* Get the UART status (we are only interested in the unmasked interrupts). */ - - priv->sr = esp32_serialin(priv, ESP32_UART_SR_OFFSET); - intena = esp32_serialin(priv, ESP32_UART_IMR_OFFSET); - pending = priv->sr & intena; + /* Clear pending interrupts */ - /* Handle an incoming, receive byte. RXRDY: At least one complete character - * has been received and US_RHR has not yet been read. - */ + regval = (UART_RXFIFO_FULL_INT_CLR_S | UART_FRM_ERR_INT_CLR_S | + UART_RXFIFO_TOUT_INT_CLR_S | UART_TX_DONE_INT_CLR_S | + UART_TXFIFO_EMPTY_INT_CLR_S); + esp32_serialout(priv, UART_INT_CLR_OFFSET, regval); - if ((pending & UART_INT_RXRDY) != 0) + if ((esp32_serialin(priv, UART_STATUS_OFFSET) & UART_RXFIFO_CNT_M) > 0) { - /* Received data ready... process incoming bytes */ + /* Received data in the RXFIFO ... process incoming bytes */ uart_recvchars(dev); handled = true; } - /* Handle outgoing, transmit bytes. TXRDY: There is no character in the - * US_THR. - */ - - if ((pending & UART_INT_TXRDY) != 0) + if ((esp32_serialin(priv, UART_STATUS_OFFSET) & UART_TXFIFO_CNT_M) < 0x7f) { - /* Transmit data register empty ... process outgoing bytes */ + /* The TXFIFO is not full ... process outgoing bytes */ uart_xmitchars(dev); handled = true; @@ -1055,7 +1047,8 @@ static void esp32_rxint(struct uart_dev_s *dev, bool enable) static bool esp32_rxavailable(struct uart_dev_s *dev) { struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; - return ((esp32_serialin(priv, ESP32_UART_SR_OFFSET) & UART_INT_RXRDY) != 0); + + return ((esp32_serialin(priv, UART_STATUS_OFFSET) & UART_RXFIFO_CNT_M) > 0); } /**************************************************************************** @@ -1069,7 +1062,8 @@ static bool esp32_rxavailable(struct uart_dev_s *dev) static void esp32_send(struct uart_dev_s *dev, int ch) { struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; - esp32_serialout(priv, ESP32_UART_THR_OFFSET, (uint32_t)ch); + + esp32_serialout(priv, UART_FIFO_OFFSET, (uint32_t)ch); } /**************************************************************************** @@ -1086,28 +1080,33 @@ static void esp32_txint(struct uart_dev_s *dev, bool enable) irqstate_t flags; flags = enter_critical_section(); + if (enable) { + uint32_t regval; + /* Set to receive an interrupt when the TX holding register register * is empty */ #ifndef CONFIG_SUPPRESS_SERIAL_INTS - esp32_serialout(priv, ESP32_UART_IER_OFFSET, UART_INT_TXRDY); + regval = esp32_serialin(priv, UART_INT_ENA_OFFSET); + regval |= (UART_TX_DONE_INT_S | UART_TXFIFO_EMPTY_INT_RAW); + esp32_serialout(priv, UART_INT_ENA_OFFSET, regval); /* Fake a TX interrupt here by just calling uart_xmitchars() with * interrupts disabled (note this may recurse). */ uart_xmitchars(dev); - #endif } else { /* Disable the TX interrupt */ - esp32_serialout(priv, ESP32_UART_IDR_OFFSET, UART_INT_TXRDY); + esp32_serialout(priv, UART_INT_CLR_OFFSET, + (UART_TX_DONE_INT_CLR_S | UART_TXFIFO_EMPTY_INT_CLR_S)); } leave_critical_section(flags); @@ -1124,7 +1123,8 @@ static void esp32_txint(struct uart_dev_s *dev, bool enable) static bool esp32_txready(struct uart_dev_s *dev) { struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; - return ((esp32_serialin(priv, ESP32_UART_SR_OFFSET) & UART_INT_TXRDY) != 0); + + return ((esp32_serialin(priv, UART_STATUS_OFFSET) & UART_TXFIFO_CNT_M) < 0x7f); } /**************************************************************************** @@ -1138,7 +1138,8 @@ static bool esp32_txready(struct uart_dev_s *dev) static bool esp32_txempty(struct uart_dev_s *dev) { struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; - return ((esp32_serialin(priv, ESP32_UART_SR_OFFSET) & UART_INT_TXEMPTY) != 0); + + return ((esp32_serialin(priv, UART_STATUS_OFFSET) & UART_TXFIFO_CNT_M) > 0); } /**************************************************************************** -- GitLab From 6ed5d4b20cc9b4a48cbcfc91afd27a85ae2512d0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 27 Oct 2016 16:36:22 -0600 Subject: [PATCH 238/734] ESP32: Fix some compilation errors --- arch/xtensa/include/serial.h | 58 ++++++++++++++++++++ arch/xtensa/src/esp32/Kconfig | 12 ++--- arch/xtensa/src/esp32/esp32_config.h | 22 ++------ arch/xtensa/src/esp32/esp32_gpio.c | 2 +- arch/xtensa/src/esp32/esp32_serial.c | 73 +++++++++++++++++--------- arch/xtensa/src/esp32/rom/esp32_gpio.h | 2 +- configs/esp32-core/nsh/defconfig | 3 +- 7 files changed, 118 insertions(+), 54 deletions(-) create mode 100644 arch/xtensa/include/serial.h diff --git a/arch/xtensa/include/serial.h b/arch/xtensa/include/serial.h new file mode 100644 index 0000000000..df5b4b7ce7 --- /dev/null +++ b/arch/xtensa/include/serial.h @@ -0,0 +1,58 @@ +/**************************************************************************** + * arch/xtensa/include/serial.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_INCLUDE_SERIAL_H +#define __ARCH_XTENSA_INCLUDE_SERIAL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* __ARCH_XTENSA_INCLUDE_SERIAL_H */ diff --git a/arch/xtensa/src/esp32/Kconfig b/arch/xtensa/src/esp32/Kconfig index 6ef278294e..92e6002125 100644 --- a/arch/xtensa/src/esp32/Kconfig +++ b/arch/xtensa/src/esp32/Kconfig @@ -237,8 +237,8 @@ config ESP32_UART0_TXPIN default 0 range 0 39 -config ESP32_UART0_TXPIN - int "UART0 Tx Pin" +config ESP32_UART0_RXPIN + int "UART0 Rx Pin" default 0 range 0 39 @@ -263,8 +263,8 @@ config ESP32_UART1_TXPIN default 0 range 0 39 -config ESP32_UART1_TXPIN - int "UART1 Tx Pin" +config ESP32_UART1_RXPIN + int "UART1 Rx Pin" default 0 range 0 39 @@ -289,8 +289,8 @@ config ESP32_UART2_TXPIN default 0 range 0 39 -config ESP32_UART2_TXPIN - int "UART2 Tx Pin" +config ESP32_UART2_RXPIN + int "UART2 Rx Pin" default 0 range 0 39 diff --git a/arch/xtensa/src/esp32/esp32_config.h b/arch/xtensa/src/esp32/esp32_config.h index 102ee81f65..23c0d06169 100644 --- a/arch/xtensa/src/esp32/esp32_config.h +++ b/arch/xtensa/src/esp32/esp32_config.h @@ -53,14 +53,14 @@ /* UARTs ********************************************************************/ /* Don't enable UARTs not supported by the chip. */ -#if ESP32_NUART < 1 +#if ESP32_NUARTS < 1 # undef CONFIG_ESP32_UART0 # undef CONFIG_ESP32_UART1 # undef CONFIG_ESP32_UART2 -#elif ESP32_NUART < 2 +#elif ESP32_NUARTS < 2 # undef CONFIG_ESP32_UART1 # undef CONFIG_ESP32_UART2 -#elif ESP32_NUART < 3 +#elif ESP32_NUARTS < 3 # undef CONFIG_ESP32_UART2 #endif @@ -127,20 +127,4 @@ # undef CONFIG_ESP32_SPI3 #endif -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - #endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_CONFIG_H */ diff --git a/arch/xtensa/src/esp32/esp32_gpio.c b/arch/xtensa/src/esp32/esp32_gpio.c index 6b5bd108f1..a86110c0fb 100644 --- a/arch/xtensa/src/esp32/esp32_gpio.c +++ b/arch/xtensa/src/esp32/esp32_gpio.c @@ -214,7 +214,7 @@ int esp32_configgpio(int pin, gpio_pinattr_t attr) func |= FUN_IE; pinmode = (attr & PINMODE_MASK); - if (pinmode == INPUT | pinmode == OUTPUT) + if (pinmode == INPUT || pinmode == OUTPUT) { func |= (uint32_t)(2 << MCU_SEL_S); } diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c index 08dd5d84bf..b6ebb6c253 100644 --- a/arch/xtensa/src/esp32/esp32_serial.c +++ b/arch/xtensa/src/esp32/esp32_serial.c @@ -52,7 +52,7 @@ # include #endif -#include +#include #include #include @@ -64,7 +64,9 @@ #include "chip/esp32_iomux.h" #include "chip/esp32_gpio_sigmap.h" #include "chip/esp32_uart.h" +#include "rom/esp32_gpio.h" #include "esp32_config.h" +#include "esp32_gpio.h" #include "esp32_cpuint.h" /**************************************************************************** @@ -100,6 +102,7 @@ # elif defined(CONFIG_ESP32_UART2) # define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */ # define UART2_ASSIGNED 1 +# endif #endif /* Pick ttys1. This could be any of UART0-2 excluding the console @@ -163,9 +166,9 @@ struct esp32_config_s struct esp32_dev_s { - const struct esp32_config_s *config /* Constant configuration */ + const struct esp32_config_s *config; /* Constant configuration */ uint32_t baud; /* Configured baud */ - uint32_t sr; /* Saved status bits */ + uint32_t status; /* Saved status bits */ uint8_t cpuint; /* CPU interrupt assigned to this UART */ uint8_t parity; /* 0=none, 1=odd, 2=even */ uint8_t bits; /* Number of bits (5-9) */ @@ -194,7 +197,7 @@ static int esp32_uart1_interrupt(int cpuint, void *context); static int esp32_uart2_interrupt(int cpuint, void *context); #endif static int esp32_ioctl(struct file *filep, int cmd, unsigned long arg); -static int esp32_receive(struct uart_dev_s *dev, uint32_t *status); +static int esp32_receive(struct uart_dev_s *dev, unsigned int *status); static void esp32_rxint(struct uart_dev_s *dev, bool enable); static bool esp32_rxavailable(struct uart_dev_s *dev); static void esp32_send(struct uart_dev_s *dev, int ch); @@ -243,7 +246,7 @@ static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; /* This describes the state of the UART0 port. */ #ifdef CONFIG_ESP32_UART0 -static struct const esp32_config_s g_uart0config = +static const struct esp32_config_s g_uart0config = { .uartbase = DR_REG_UART_BASE, .handler = esp32_uart0_interrupt, @@ -263,7 +266,7 @@ static struct const esp32_config_s g_uart0config = static struct esp32_dev_s g_uart0priv = { - .config = &g_uart0config; + .config = &g_uart0config, .baud = CONFIG_UART0_BAUD, .parity = CONFIG_UART0_PARITY, .bits = CONFIG_UART0_BITS, @@ -290,7 +293,7 @@ static uart_dev_t g_uart0port = /* This describes the state of the UART1 port. */ #ifdef CONFIG_ESP32_UART1 -static struct const esp32_config_s g_uart1config = +static const struct esp32_config_s g_uart1config = { .uartbase = DR_REG_UART1_BASE, .handler = esp32_uart1_interrupt, @@ -310,7 +313,7 @@ static struct const esp32_config_s g_uart1config = static struct esp32_dev_s g_uart1priv = { - .config = &g_uart1config; + .config = &g_uart1config, .baud = CONFIG_UART1_BAUD, .parity = CONFIG_UART1_PARITY, .bits = CONFIG_UART1_BITS, @@ -337,7 +340,7 @@ static uart_dev_t g_uart1port = /* This describes the state of the UART2 port. */ #ifdef CONFIG_ESP32_UART2 -static struct const esp32_config_s g_uart2config = +static const struct esp32_config_s g_uart2config = { .uartbase = DR_REG_UART2_BASE, .handler = esp32_uart2_interrupt, @@ -357,7 +360,7 @@ static struct const esp32_config_s g_uart2config = static struct esp32_dev_s g_uart2priv = { - .config = &g_uart2config; + .config = &g_uart2config, .baud = CONFIG_UART2_BAUD, .parity = CONFIG_UART2_PARITY, .bits = CONFIG_UART2_BITS, @@ -591,17 +594,17 @@ static void esp32_shutdown(struct uart_dev_s *dev) /* Revert pins to inputs and detach UART signals */ esp32_configgpio(priv->config->txpin, INPUT); - gpio_matrix_out(MATRIX_DETACH_OUT_SIG, priv->txsig, true, false); + gpio_matrix_out(MATRIX_DETACH_OUT_SIG, priv->config->txsig, true, false); esp32_configgpio(priv->config->rxpin, INPUT); - gpio_matrix_in(MATRIX_DETACH_IN_LOW_PIN, priv->rxsig, false); + gpio_matrix_in(MATRIX_DETACH_IN_LOW_PIN, priv->config->rxsig, false); #if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) esp32_configgpio(priv->config->rtspin, INPUT); - gpio_matrix_out(MATRIX_DETACH_OUT_SIG, priv->rtssig, true, false); + gpio_matrix_out(MATRIX_DETACH_OUT_SIG, priv->config->rtssig, true, false); esp32_configgpio(priv->config->ctspin, INPUT); - gpio_matrix_in(MATRIX_DETACH_IN_LOW_PIN, priv->ctssig, false); + gpio_matrix_in(MATRIX_DETACH_IN_LOW_PIN, priv->config->ctssig, false); #endif /* Unconfigure and disable the UART */ @@ -652,7 +655,7 @@ static int esp32_attach(struct uart_dev_s *dev) /* Attach the GPIO peripheral to the allocated CPU interrupt */ - up_disable_irq(g_gpio_cpuint); + up_disable_irq(priv->cpuint); esp32_attach_peripheral(cpu, priv->config->periph, priv->cpuint); /* Attach and enable the IRQ */ @@ -683,6 +686,7 @@ static int esp32_attach(struct uart_dev_s *dev) static void esp32_detach(struct uart_dev_s *dev) { struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; + int cpu; /* Disable and detach the CPU interrupt */ @@ -691,6 +695,12 @@ static void esp32_detach(struct uart_dev_s *dev) /* Disassociate the peripheral interrupt from the CPU interrupt */ +#ifdef CONFIG_SMP + cpu = up_cpu_index(); +#else + cpu = 0; +#endif + esp32_detach_peripheral(cpu, priv->config->periph); /* And release the CPU interrupt */ @@ -714,6 +724,7 @@ static int esp32_interrupt(struct uart_dev_s *dev) { struct esp32_dev_s *priv; uint32_t regval; + uint32_t status; int passes; bool handled; @@ -727,7 +738,9 @@ static int esp32_interrupt(struct uart_dev_s *dev) handled = true; for (passes = 0; passes < 256 && handled; passes++) { - handled = false; + handled = false; + priv->status = esp32_serialin(priv, UART_INT_RAW_OFFSET); + status = esp32_serialin(priv, UART_STATUS_OFFSET); /* Clear pending interrupts */ @@ -736,7 +749,7 @@ static int esp32_interrupt(struct uart_dev_s *dev) UART_TXFIFO_EMPTY_INT_CLR_S); esp32_serialout(priv, UART_INT_CLR_OFFSET, regval); - if ((esp32_serialin(priv, UART_STATUS_OFFSET) & UART_RXFIFO_CNT_M) > 0) + if ((status & UART_RXFIFO_CNT_M) > 0) { /* Received data in the RXFIFO ... process incoming bytes */ @@ -744,7 +757,7 @@ static int esp32_interrupt(struct uart_dev_s *dev) handled = true; } - if ((esp32_serialin(priv, UART_STATUS_OFFSET) & UART_TXFIFO_CNT_M) < 0x7f) + if ((status & UART_TXFIFO_CNT_M) < 0x7f) { /* The TXFIFO is not full ... process outgoing bytes */ @@ -994,18 +1007,18 @@ static int esp32_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -static int esp32_receive(struct uart_dev_s *dev, uint32_t *status) +static int esp32_receive(struct uart_dev_s *dev, unsigned int *status) { struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; /* Return the error information in the saved status */ - *status = priv->sr; - priv->sr = 0; + *status = (unsigned int)priv->status; + priv->status = 0; /* Then return the actual received byte */ - return (int)(esp32_serialin(priv, ESP32_UART_RHR_OFFSET) & 0xff); + return (int)(esp32_serialin(priv, UART_FIFO_OFFSET) & UART_RXFIFO_RD_BYTE_M); } /**************************************************************************** @@ -1019,6 +1032,7 @@ static int esp32_receive(struct uart_dev_s *dev, uint32_t *status) static void esp32_rxint(struct uart_dev_s *dev, bool enable) { struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; + int regval; if (enable) { @@ -1027,12 +1041,19 @@ static void esp32_rxint(struct uart_dev_s *dev, bool enable) */ #ifndef CONFIG_SUPPRESS_SERIAL_INTS - esp32_serialout(priv, ESP32_UART_IER_OFFSET, UART_INT_RXRDY); + regval = esp32_serialin(priv, UART_INT_ENA_OFFSET); + regval |= (UART_RXFIFO_FULL_INT_CLR_S | UART_FRM_ERR_INT_CLR_S | + UART_RXFIFO_TOUT_INT_CLR_S); + esp32_serialout(priv, UART_INT_ENA_OFFSET, regval); #endif } else { - esp32_serialout(priv, ESP32_UART_IDR_OFFSET, UART_INT_RXRDY); + /* Disable the RX interrupts */ + + esp32_serialout(priv, UART_INT_CLR_OFFSET, + (UART_RXFIFO_FULL_INT_CLR_S | UART_FRM_ERR_INT_CLR_S | + UART_RXFIFO_TOUT_INT_CLR_S)); } } @@ -1091,7 +1112,7 @@ static void esp32_txint(struct uart_dev_s *dev, bool enable) #ifndef CONFIG_SUPPRESS_SERIAL_INTS regval = esp32_serialin(priv, UART_INT_ENA_OFFSET); - regval |= (UART_TX_DONE_INT_S | UART_TXFIFO_EMPTY_INT_RAW); + regval |= (UART_TX_DONE_INT_ENA_S | UART_TXFIFO_EMPTY_INT_ENA_S); esp32_serialout(priv, UART_INT_ENA_OFFSET, regval); /* Fake a TX interrupt here by just calling uart_xmitchars() with @@ -1191,7 +1212,7 @@ void up_earlyserialinit(void) * ****************************************************************************/ -void up_serialinit(void) +void xtensa_serial_initialize(void) { /* Register the console */ diff --git a/arch/xtensa/src/esp32/rom/esp32_gpio.h b/arch/xtensa/src/esp32/rom/esp32_gpio.h index fc2e6ded25..00680ff995 100644 --- a/arch/xtensa/src/esp32/rom/esp32_gpio.h +++ b/arch/xtensa/src/esp32/rom/esp32_gpio.h @@ -36,7 +36,7 @@ #include #include -#include "chip/gpio_reg.h" +#include "chip/esp32_gpio.h" /**************************************************************************** * Pre-processor Definitions diff --git a/configs/esp32-core/nsh/defconfig b/configs/esp32-core/nsh/defconfig index 8d40ba790f..4d8658e0e3 100644 --- a/configs/esp32-core/nsh/defconfig +++ b/configs/esp32-core/nsh/defconfig @@ -89,6 +89,7 @@ CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0 CONFIG_ESP32_ULP_COPROC_RESERVE_MEM=0 # CONFIG_ESP32_GPIO_IRQ is not set CONFIG_ESP32_UART0_TXPIN=0 +CONFIG_ESP32_UART0_RXPIN=0 # # ESP32 Peripheral Selection @@ -594,10 +595,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set -- GitLab From afcda29646fe98e0d75bda3982c15116f34904ec Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 27 Oct 2016 16:46:34 -0600 Subject: [PATCH 239/734] ESP32: Fix some warnings --- arch/xtensa/src/common/xtensa.h | 2 +- arch/xtensa/src/esp32/esp32_irq.c | 1 + arch/xtensa/src/esp32/esp32_serial.c | 2 +- arch/xtensa/src/esp32/esp32_start.c | 2 +- 4 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index bde2eaba5f..6cd35c9d08 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -278,7 +278,7 @@ void xtensa_add_region(void); void up_lowputc(char ch); #if CONFIG_NFILE_DESCRIPTORS > 0 -void xtensa_earlyserialinit(void); +void xtensa_early_serial_initialize(void); void xtensa_serial_initialize(void); #else # define xtensa_earlyserialinit() diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c index 33f94576bd..c407b991e8 100644 --- a/arch/xtensa/src/esp32/esp32_irq.c +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -47,6 +47,7 @@ #include #include "xtensa.h" +#include "esp32_cpuint.h" /**************************************************************************** * Public Data diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c index b6ebb6c253..69423e4ccc 100644 --- a/arch/xtensa/src/esp32/esp32_serial.c +++ b/arch/xtensa/src/esp32/esp32_serial.c @@ -1178,7 +1178,7 @@ static bool esp32_txempty(struct uart_dev_s *dev) ****************************************************************************/ #ifdef USE_EARLYSERIALINIT -void up_earlyserialinit(void) +void xtensa_early_serial_initialize(void) { /* NOTE: All GPIO configuration for the UARTs was performed in * esp32_lowsetup diff --git a/arch/xtensa/src/esp32/esp32_start.c b/arch/xtensa/src/esp32/esp32_start.c index 7d6ef7d5dc..a468e83a9c 100644 --- a/arch/xtensa/src/esp32/esp32_start.c +++ b/arch/xtensa/src/esp32/esp32_start.c @@ -98,7 +98,7 @@ void IRAM_ATTR __start(void) #ifdef USE_EARLYSERIALINIT /* Perform early serial initialization */ - xtensa_earlyserialinit(); + xtensa_early_serial_initialize(); #endif /* Initialize onboard resources */ -- GitLab From e6377641a8461cc4fc0ac8daa9dbfba704ec9325 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 27 Oct 2016 18:04:14 -0600 Subject: [PATCH 240/734] sched/Kconfig: Add ranges to START_YEAR, MONTH, and DAY --- arch/xtensa/src/esp32/esp32_serial.c | 6 +++--- sched/Kconfig | 8 +++++++- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c index b6ebb6c253..53557b7344 100644 --- a/arch/xtensa/src/esp32/esp32_serial.c +++ b/arch/xtensa/src/esp32/esp32_serial.c @@ -1168,7 +1168,7 @@ static bool esp32_txempty(struct uart_dev_s *dev) ****************************************************************************/ /**************************************************************************** - * Name: up_earlyserialinit + * Name: xtensa_serial_initialize * * Description: * Performs the low level UART initialization early in debug so that the @@ -1178,7 +1178,7 @@ static bool esp32_txempty(struct uart_dev_s *dev) ****************************************************************************/ #ifdef USE_EARLYSERIALINIT -void up_earlyserialinit(void) +void xtensa_serial_initialize(void) { /* NOTE: All GPIO configuration for the UARTs was performed in * esp32_lowsetup @@ -1204,7 +1204,7 @@ void up_earlyserialinit(void) #endif /**************************************************************************** - * Name: up_serialinit + * Name: xtensa_serial_initialize * * Description: * Register serial console and serial ports. This assumes diff --git a/sched/Kconfig b/sched/Kconfig index bf40372785..b10d3e3caf 100644 --- a/sched/Kconfig +++ b/sched/Kconfig @@ -188,15 +188,21 @@ if !RTC config START_YEAR int "Start year" - default 2014 + default 2016 + range 1970 2106 + ---help--- + NuttX uses an unsigned 32-bit integer for time_t which provides a + range from 1970 to 2106. config START_MONTH int "Start month" default 1 + range 1 12 config START_DAY int "Start day" default 1 + range 1 31 endif # !RTC -- GitLab From 1e7f78e5c061e6312af063fffd533251e4ad3b14 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 27 Oct 2016 18:27:19 -0600 Subject: [PATCH 241/734] ESP32: Add implementation of up_putc --- arch/xtensa/src/esp32/esp32_serial.c | 33 ++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c index 073c040503..f48b06e304 100644 --- a/arch/xtensa/src/esp32/esp32_serial.c +++ b/arch/xtensa/src/esp32/esp32_serial.c @@ -1231,4 +1231,37 @@ void xtensa_serial_initialize(void) #endif } +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + uint32_t intena; + + esp32_disableallints(CONSOLE_DEV.priv, &intena); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + while(!esp32_txready(&CONSOLE_DEV)); + esp32_send(&CONSOLE_DEV, 'r'); + } + + while(!esp32_txready(&CONSOLE_DEV)); + esp32_send(&CONSOLE_DEV, ch); + + esp32_restoreuartint(CONSOLE_DEV.priv, intena); +#endif + + return ch; +} #endif /* USE_SERIALDRIVER */ -- GitLab From d58f9d842603155f6c58895af1195e88092f151e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marc=20Recht=C3=A9?= Date: Fri, 28 Oct 2016 07:15:15 -0600 Subject: [PATCH 242/734] Add STM32 F303RE hello configuration; remove duplicate setting from board.h --- configs/nucleo-f303re/hello/Make.defs | 113 +++ configs/nucleo-f303re/hello/defconfig | 1052 +++++++++++++++++++++++++ 2 files changed, 1165 insertions(+) create mode 100644 configs/nucleo-f303re/hello/Make.defs create mode 100644 configs/nucleo-f303re/hello/defconfig diff --git a/configs/nucleo-f303re/hello/Make.defs b/configs/nucleo-f303re/hello/Make.defs new file mode 100644 index 0000000000..e6c2bdd70e --- /dev/null +++ b/configs/nucleo-f303re/hello/Make.defs @@ -0,0 +1,113 @@ +############################################################################ +# configs/nucleo-f303re/hello/Make.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/nucleo-f303re/hello/defconfig b/configs/nucleo-f303re/hello/defconfig new file mode 100644 index 0000000000..b35c6c70d2 --- /dev/null +++ b/configs/nucleo-f303re/hello/defconfig @@ -0,0 +1,1052 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +CONFIG_ARCH_HAVE_HEAPCHECK=y +# CONFIG_HEAP_COLORATION is not set +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ARCH_HAVE_CUSTOMOPT=y +CONFIG_DEBUG_NOOPT=y +# CONFIG_DEBUG_CUSTOMOPT is not set +# CONFIG_DEBUG_FULLOPT is not set + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +CONFIG_ARCH_CHIP_STM32=y +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM3 is not set +CONFIG_ARCH_CORTEXM4=y +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="stm32" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARMV7M_LAZYFPU is not set +CONFIG_ARCH_HAVE_FPU=y +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y +CONFIG_ARMV7M_HAVE_STACKCHECK=y +# CONFIG_ARMV7M_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set +# CONFIG_SERIAL_TERMIOS is not set + +# +# STM32 Configuration Options +# +# CONFIG_ARCH_CHIP_STM32L151C6 is not set +# CONFIG_ARCH_CHIP_STM32L151C8 is not set +# CONFIG_ARCH_CHIP_STM32L151CB is not set +# CONFIG_ARCH_CHIP_STM32L151R6 is not set +# CONFIG_ARCH_CHIP_STM32L151R8 is not set +# CONFIG_ARCH_CHIP_STM32L151RB is not set +# CONFIG_ARCH_CHIP_STM32L151V6 is not set +# CONFIG_ARCH_CHIP_STM32L151V8 is not set +# CONFIG_ARCH_CHIP_STM32L151VB is not set +# CONFIG_ARCH_CHIP_STM32L152C6 is not set +# CONFIG_ARCH_CHIP_STM32L152C8 is not set +# CONFIG_ARCH_CHIP_STM32L152CB is not set +# CONFIG_ARCH_CHIP_STM32L152R6 is not set +# CONFIG_ARCH_CHIP_STM32L152R8 is not set +# CONFIG_ARCH_CHIP_STM32L152RB is not set +# CONFIG_ARCH_CHIP_STM32L152V6 is not set +# CONFIG_ARCH_CHIP_STM32L152V8 is not set +# CONFIG_ARCH_CHIP_STM32L152VB is not set +# CONFIG_ARCH_CHIP_STM32L162ZD is not set +# CONFIG_ARCH_CHIP_STM32L162VE is not set +# CONFIG_ARCH_CHIP_STM32F100C8 is not set +# CONFIG_ARCH_CHIP_STM32F100CB is not set +# CONFIG_ARCH_CHIP_STM32F100R8 is not set +# CONFIG_ARCH_CHIP_STM32F100RB is not set +# CONFIG_ARCH_CHIP_STM32F100RC is not set +# CONFIG_ARCH_CHIP_STM32F100RD is not set +# CONFIG_ARCH_CHIP_STM32F100RE is not set +# CONFIG_ARCH_CHIP_STM32F100V8 is not set +# CONFIG_ARCH_CHIP_STM32F100VB is not set +# CONFIG_ARCH_CHIP_STM32F100VC is not set +# CONFIG_ARCH_CHIP_STM32F100VD is not set +# CONFIG_ARCH_CHIP_STM32F100VE is not set +# CONFIG_ARCH_CHIP_STM32F102CB is not set +# CONFIG_ARCH_CHIP_STM32F103T8 is not set +# CONFIG_ARCH_CHIP_STM32F103TB is not set +# CONFIG_ARCH_CHIP_STM32F103C4 is not set +# CONFIG_ARCH_CHIP_STM32F103C8 is not set +# CONFIG_ARCH_CHIP_STM32F103CB is not set +# CONFIG_ARCH_CHIP_STM32F103R8 is not set +# CONFIG_ARCH_CHIP_STM32F103RB is not set +# CONFIG_ARCH_CHIP_STM32F103RC is not set +# CONFIG_ARCH_CHIP_STM32F103RD is not set +# CONFIG_ARCH_CHIP_STM32F103RE is not set +# CONFIG_ARCH_CHIP_STM32F103RG is not set +# CONFIG_ARCH_CHIP_STM32F103V8 is not set +# CONFIG_ARCH_CHIP_STM32F103VB is not set +# CONFIG_ARCH_CHIP_STM32F103VC is not set +# CONFIG_ARCH_CHIP_STM32F103VE is not set +# CONFIG_ARCH_CHIP_STM32F103ZE is not set +# CONFIG_ARCH_CHIP_STM32F105VB is not set +# CONFIG_ARCH_CHIP_STM32F105RB is not set +# CONFIG_ARCH_CHIP_STM32F107VC is not set +# CONFIG_ARCH_CHIP_STM32F205RG is not set +# CONFIG_ARCH_CHIP_STM32F207IG is not set +# CONFIG_ARCH_CHIP_STM32F207ZE is not set +# CONFIG_ARCH_CHIP_STM32F302K6 is not set +# CONFIG_ARCH_CHIP_STM32F302K8 is not set +# CONFIG_ARCH_CHIP_STM32F302CB is not set +# CONFIG_ARCH_CHIP_STM32F302CC is not set +# CONFIG_ARCH_CHIP_STM32F302RB is not set +# CONFIG_ARCH_CHIP_STM32F302RC is not set +# CONFIG_ARCH_CHIP_STM32F302VB is not set +# CONFIG_ARCH_CHIP_STM32F302VC is not set +# CONFIG_ARCH_CHIP_STM32F303K6 is not set +# CONFIG_ARCH_CHIP_STM32F303K8 is not set +# CONFIG_ARCH_CHIP_STM32F303C6 is not set +# CONFIG_ARCH_CHIP_STM32F303C8 is not set +# CONFIG_ARCH_CHIP_STM32F303CB is not set +# CONFIG_ARCH_CHIP_STM32F303CC is not set +# CONFIG_ARCH_CHIP_STM32F303RB is not set +# CONFIG_ARCH_CHIP_STM32F303RC is not set +# CONFIG_ARCH_CHIP_STM32F303RD is not set +CONFIG_ARCH_CHIP_STM32F303RE=y +# CONFIG_ARCH_CHIP_STM32F303VB is not set +# CONFIG_ARCH_CHIP_STM32F303VC is not set +# CONFIG_ARCH_CHIP_STM32F372C8 is not set +# CONFIG_ARCH_CHIP_STM32F372R8 is not set +# CONFIG_ARCH_CHIP_STM32F372V8 is not set +# CONFIG_ARCH_CHIP_STM32F372CB is not set +# CONFIG_ARCH_CHIP_STM32F372RB is not set +# CONFIG_ARCH_CHIP_STM32F372VB is not set +# CONFIG_ARCH_CHIP_STM32F372CC is not set +# CONFIG_ARCH_CHIP_STM32F372RC is not set +# CONFIG_ARCH_CHIP_STM32F372VC is not set +# CONFIG_ARCH_CHIP_STM32F373C8 is not set +# CONFIG_ARCH_CHIP_STM32F373R8 is not set +# CONFIG_ARCH_CHIP_STM32F373V8 is not set +# CONFIG_ARCH_CHIP_STM32F373CB is not set +# CONFIG_ARCH_CHIP_STM32F373RB is not set +# CONFIG_ARCH_CHIP_STM32F373VB is not set +# CONFIG_ARCH_CHIP_STM32F373CC is not set +# CONFIG_ARCH_CHIP_STM32F373RC is not set +# CONFIG_ARCH_CHIP_STM32F373VC is not set +# CONFIG_ARCH_CHIP_STM32F401RE is not set +# CONFIG_ARCH_CHIP_STM32F411RE is not set +# CONFIG_ARCH_CHIP_STM32F411VE is not set +# CONFIG_ARCH_CHIP_STM32F405RG is not set +# CONFIG_ARCH_CHIP_STM32F405VG is not set +# CONFIG_ARCH_CHIP_STM32F405ZG is not set +# CONFIG_ARCH_CHIP_STM32F407VE is not set +# CONFIG_ARCH_CHIP_STM32F407VG is not set +# CONFIG_ARCH_CHIP_STM32F407ZE is not set +# CONFIG_ARCH_CHIP_STM32F407ZG is not set +# CONFIG_ARCH_CHIP_STM32F407IE is not set +# CONFIG_ARCH_CHIP_STM32F407IG is not set +# CONFIG_ARCH_CHIP_STM32F427V is not set +# CONFIG_ARCH_CHIP_STM32F427Z is not set +# CONFIG_ARCH_CHIP_STM32F427I is not set +# CONFIG_ARCH_CHIP_STM32F429V is not set +# CONFIG_ARCH_CHIP_STM32F429Z is not set +# CONFIG_ARCH_CHIP_STM32F429I is not set +# CONFIG_ARCH_CHIP_STM32F429B is not set +# CONFIG_ARCH_CHIP_STM32F429N is not set +# CONFIG_ARCH_CHIP_STM32F446M is not set +# CONFIG_ARCH_CHIP_STM32F446R is not set +# CONFIG_ARCH_CHIP_STM32F446V is not set +# CONFIG_ARCH_CHIP_STM32F446Z is not set +# CONFIG_ARCH_CHIP_STM32F469A is not set +# CONFIG_ARCH_CHIP_STM32F469I is not set +# CONFIG_ARCH_CHIP_STM32F469B is not set +# CONFIG_ARCH_CHIP_STM32F469N is not set +CONFIG_STM32_FLASH_CONFIG_DEFAULT=y +# CONFIG_STM32_FLASH_CONFIG_4 is not set +# CONFIG_STM32_FLASH_CONFIG_6 is not set +# CONFIG_STM32_FLASH_CONFIG_8 is not set +# CONFIG_STM32_FLASH_CONFIG_B is not set +# CONFIG_STM32_FLASH_CONFIG_C is not set +# CONFIG_STM32_FLASH_CONFIG_D is not set +# CONFIG_STM32_FLASH_CONFIG_E is not set +# CONFIG_STM32_FLASH_CONFIG_F is not set +# CONFIG_STM32_FLASH_CONFIG_G is not set +# CONFIG_STM32_FLASH_CONFIG_I is not set +# CONFIG_STM32_STM32L15XX is not set +# CONFIG_STM32_ENERGYLITE is not set +# CONFIG_STM32_STM32F10XX is not set +# CONFIG_STM32_VALUELINE is not set +# CONFIG_STM32_CONNECTIVITYLINE is not set +# CONFIG_STM32_PERFORMANCELINE is not set +# CONFIG_STM32_USBACCESSLINE is not set +# CONFIG_STM32_HIGHDENSITY is not set +# CONFIG_STM32_MEDIUMDENSITY is not set +# CONFIG_STM32_LOWDENSITY is not set +# CONFIG_STM32_STM32F20XX is not set +# CONFIG_STM32_STM32F205 is not set +# CONFIG_STM32_STM32F207 is not set +CONFIG_STM32_STM32F30XX=y +# CONFIG_STM32_STM32F302 is not set +CONFIG_STM32_STM32F303=y +# CONFIG_STM32_STM32F37XX is not set +# CONFIG_STM32_STM32F40XX is not set +# CONFIG_STM32_STM32F401 is not set +# CONFIG_STM32_STM32F411 is not set +# CONFIG_STM32_STM32F405 is not set +# CONFIG_STM32_STM32F407 is not set +# CONFIG_STM32_STM32F427 is not set +# CONFIG_STM32_STM32F429 is not set +# CONFIG_STM32_STM32F446 is not set +# CONFIG_STM32_STM32F469 is not set +# CONFIG_STM32_DFU is not set + +# +# STM32 Peripheral Support +# +CONFIG_STM32_HAVE_CCM=y +CONFIG_STM32_HAVE_USBDEV=y +# CONFIG_STM32_HAVE_OTGFS is not set +# CONFIG_STM32_HAVE_FSMC is not set +# CONFIG_STM32_HAVE_LTDC is not set +CONFIG_STM32_HAVE_USART3=y +CONFIG_STM32_HAVE_UART4=y +CONFIG_STM32_HAVE_UART5=y +# CONFIG_STM32_HAVE_USART6 is not set +# CONFIG_STM32_HAVE_UART7 is not set +# CONFIG_STM32_HAVE_UART8 is not set +CONFIG_STM32_HAVE_TIM1=y +# CONFIG_STM32_HAVE_TIM2 is not set +CONFIG_STM32_HAVE_TIM3=y +CONFIG_STM32_HAVE_TIM4=y +# CONFIG_STM32_HAVE_TIM5 is not set +CONFIG_STM32_HAVE_TIM6=y +CONFIG_STM32_HAVE_TIM7=y +CONFIG_STM32_HAVE_TIM8=y +# CONFIG_STM32_HAVE_TIM9 is not set +# CONFIG_STM32_HAVE_TIM10 is not set +# CONFIG_STM32_HAVE_TIM11 is not set +# CONFIG_STM32_HAVE_TIM12 is not set +# CONFIG_STM32_HAVE_TIM13 is not set +# CONFIG_STM32_HAVE_TIM14 is not set +CONFIG_STM32_HAVE_TIM15=y +CONFIG_STM32_HAVE_TIM16=y +CONFIG_STM32_HAVE_TIM17=y +CONFIG_STM32_HAVE_ADC2=y +CONFIG_STM32_HAVE_ADC3=y +CONFIG_STM32_HAVE_ADC4=y +# CONFIG_STM32_HAVE_ADC1_DMA is not set +# CONFIG_STM32_HAVE_ADC2_DMA is not set +# CONFIG_STM32_HAVE_ADC3_DMA is not set +# CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set +CONFIG_STM32_HAVE_CAN1=y +# CONFIG_STM32_HAVE_CAN2 is not set +CONFIG_STM32_HAVE_DAC1=y +CONFIG_STM32_HAVE_DAC2=y +# CONFIG_STM32_HAVE_RNG is not set +# CONFIG_STM32_HAVE_ETHMAC is not set +CONFIG_STM32_HAVE_I2C2=y +CONFIG_STM32_HAVE_I2C3=y +CONFIG_STM32_HAVE_SPI2=y +CONFIG_STM32_HAVE_SPI3=y +CONFIG_STM32_HAVE_SPI4=y +# CONFIG_STM32_HAVE_SPI5 is not set +# CONFIG_STM32_HAVE_SPI6 is not set +# CONFIG_STM32_HAVE_SAIPLL is not set +# CONFIG_STM32_HAVE_I2SPLL is not set +# CONFIG_STM32_ADC1 is not set +# CONFIG_STM32_ADC2 is not set +# CONFIG_STM32_ADC3 is not set +# CONFIG_STM32_ADC4 is not set +# CONFIG_STM32_CAN1 is not set +# CONFIG_STM32_CRC is not set +# CONFIG_STM32_DMA1 is not set +# CONFIG_STM32_DMA2 is not set +# CONFIG_STM32_DAC1 is not set +# CONFIG_STM32_DAC2 is not set +# CONFIG_STM32_I2C1 is not set +# CONFIG_STM32_I2C2 is not set +# CONFIG_STM32_I2C3 is not set +# CONFIG_STM32_PWR is not set +# CONFIG_STM32_SDIO is not set +# CONFIG_STM32_SPI1 is not set +# CONFIG_STM32_SPI2 is not set +# CONFIG_STM32_SPI3 is not set +# CONFIG_STM32_SPI4 is not set +CONFIG_STM32_SYSCFG=y +# CONFIG_STM32_TIM1 is not set +# CONFIG_STM32_TIM2 is not set +# CONFIG_STM32_TIM3 is not set +# CONFIG_STM32_TIM4 is not set +# CONFIG_STM32_TIM6 is not set +# CONFIG_STM32_TIM7 is not set +# CONFIG_STM32_TIM8 is not set +# CONFIG_STM32_TIM15 is not set +# CONFIG_STM32_TIM16 is not set +# CONFIG_STM32_TIM17 is not set +# CONFIG_STM32_TSC is not set +# CONFIG_STM32_USART1 is not set +CONFIG_STM32_USART2=y +# CONFIG_STM32_USART3 is not set +# CONFIG_STM32_UART4 is not set +# CONFIG_STM32_UART5 is not set +# CONFIG_STM32_USB is not set +# CONFIG_STM32_IWDG is not set +# CONFIG_STM32_WWDG is not set +# CONFIG_STM32_NOEXT_VECTORS is not set + +# +# Alternate Pin Mapping +# +# CONFIG_STM32_JTAG_DISABLE is not set +# CONFIG_STM32_JTAG_FULL_ENABLE is not set +# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set +CONFIG_STM32_JTAG_SW_ENABLE=y +# CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG is not set +# CONFIG_STM32_FORCEPOWER is not set +# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set +# CONFIG_STM32_CCMEXCLUDE is not set + +# +# Timer Configuration +# +# CONFIG_STM32_ONESHOT is not set +# CONFIG_STM32_FREERUN is not set +# CONFIG_STM32_TIM1_CAP is not set +# CONFIG_STM32_TIM3_CAP is not set +# CONFIG_STM32_TIM4_CAP is not set +# CONFIG_STM32_TIM8_CAP is not set +CONFIG_STM32_USART=y +CONFIG_STM32_SERIALDRIVER=y + +# +# U[S]ART Configuration +# + +# +# U[S]ART Device Configuration +# +CONFIG_STM32_USART2_SERIALDRIVER=y +# CONFIG_STM32_USART2_1WIREDRIVER is not set +# CONFIG_USART2_RS485 is not set + +# +# Serial Driver Configuration +# +# CONFIG_SERIAL_DISABLE_REORDERING is not set +# CONFIG_STM32_FLOWCONTROL_BROKEN is not set +# CONFIG_STM32_USART_BREAKS is not set +# CONFIG_STM32_USART_SINGLEWIRE is not set +# CONFIG_STM32_HAVE_RTC_COUNTER is not set +# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set + +# +# USB FS Host Configuration +# + +# +# USB HS Host Configuration +# + +# +# USB Host Debug Configuration +# + +# +# USB Device Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=6522 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_SIZE=65536 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_NUCLEO_F303RE=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="nucleo-f303re" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_HAVE_IRQBUTTONS=y +# CONFIG_ARCH_IRQBUTTONS is not set + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +# CONFIG_LIB_BOARDCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Clocks and Timers +# +CONFIG_ARCH_HAVE_TICKLESS=y +# CONFIG_SCHED_TICKLESS is not set +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +CONFIG_ARCH_HAVE_TIMEKEEPING=y +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2013 +CONFIG_START_MONTH=1 +CONFIG_START_DAY=27 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=8 +CONFIG_WDOG_INTRESERVE=1 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="hello_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=0 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_HPWORK is not set +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +CONFIG_ARCH_HAVE_I2CRESET=y +# CONFIG_I2C is not set +# CONFIG_SPI is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +CONFIG_USART2_SERIALDRIVER=y +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +CONFIG_USART2_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# USART2 Configuration +# +CONFIG_USART2_RXBUFSIZE=256 +CONFIG_USART2_TXBUFSIZE=256 +CONFIG_USART2_BAUD=115200 +CONFIG_USART2_BITS=8 +CONFIG_USART2_PARITY=0 +CONFIG_USART2_2STOP=0 +# CONFIG_USART2_IFLOWCONTROL is not set +# CONFIG_USART2_OFLOWCONTROL is not set +# CONFIG_USART2_DMA is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +# CONFIG_SYSLOG_SERIAL_CONSOLE is not set +# CONFIG_SYSLOG_CHAR is not set +# CONFIG_SYSLOG_CONSOLE is not set +CONFIG_SYSLOG_NONE=y +# CONFIG_SYSLOG_FILE is not set +# CONFIG_CONSOLE_SYSLOG is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_FS_READABLE is not set +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=2 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_BUILTIN is not set +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set +# CONFIG_LIBC_NETDB is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_ARCHBUTTONS is not set +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLO_PRIORITY=100 +CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +# CONFIG_EXAMPLES_NSH is not set +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +# CONFIG_NSH_LIBRARY is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +# CONFIG_READLINE_HAVE_EXTMATCH is not set +# CONFIG_SYSTEM_READLINE is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set -- GitLab From 54972a16682759722d993bf5bdea0d42c5b1805c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marc=20Recht=C3=A9?= Date: Fri, 28 Oct 2016 07:16:01 -0600 Subject: [PATCH 243/734] Add STM32 F303RE hello configuration; remove duplicate setting from board.h --- configs/nucleo-f303re/include/board.h | 7 ------- 1 file changed, 7 deletions(-) diff --git a/configs/nucleo-f303re/include/board.h b/configs/nucleo-f303re/include/board.h index 3a8d91c6c4..0960f3e6b0 100644 --- a/configs/nucleo-f303re/include/board.h +++ b/configs/nucleo-f303re/include/board.h @@ -125,13 +125,6 @@ #define STM32_CFGR_USBPRE 0 - -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - - /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 -- GitLab From 3bacda15655a0806d997dd01dd67fe3159be199e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 28 Oct 2016 07:16:52 -0600 Subject: [PATCH 244/734] STM32 Serial: Trivial removal of an extra space in a comment --- arch/arm/src/stm32/stm32_serial.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c index 6152d5795d..644c810817 100644 --- a/arch/arm/src/stm32/stm32_serial.c +++ b/arch/arm/src/stm32/stm32_serial.c @@ -3006,7 +3006,7 @@ void stm32_serial_dma_poll(void) * Name: up_putc * * Description: - * Provide priority, low-level access to support OS debug writes + * Provide priority, low-level access to support OS debug writes * ****************************************************************************/ -- GitLab From e93bcda8ae4bfb4b3ade6c66426e44b1b30e7d36 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 28 Oct 2016 09:05:39 -0600 Subject: [PATCH 245/734] ESP32: Partial co-processor state save logic. Incomplete and will probably be redesigned. --- arch/xtensa/Kconfig | 11 + arch/xtensa/src/common/xtensa.h | 6 +- arch/xtensa/src/common/xtensa_context.S | 11 +- arch/xtensa/src/common/xtensa_coproc.S | 341 ++++++++++++++++++++ arch/xtensa/src/common/xtensa_initialize.c | 6 + arch/xtensa/src/common/xtensa_inthandlers.S | 1 - arch/xtensa/src/common/xtensa_irqdispatch.c | 47 ++- 7 files changed, 412 insertions(+), 11 deletions(-) diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index a163955de3..e90643c82f 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -38,6 +38,17 @@ config XTENSA_CALL0_ABI The Window ABI is not supported. Only the CALL0 ABI is supported in the current implementation. +config XTENSA_CP_LAZY + bool "Lazy Co-processor Save" + default y + ---help--- + If this option is selected, then the co-processor state will be saved + only on context switches. As a consequency of this, co-processors + may NOT be used within interrupt handlers. If you must use co- + processors in interrupt handling, then disable this option. There + will be a significant interrupt latency performance impact if this + option is disabled. + config XTENSA_USE_OVLY bool default n diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index 6cd35c9d08..df81f64ba4 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -226,12 +226,16 @@ void lowconsole_init(void); /* Debug */ #ifdef CONFIG_ARCH_STACKDUMP -void xtensa_dumpstate(void); +void xtensa_dumpstate(void);s #else # define xtensa_dumpstate() #endif /* Common XTENSA functions */ +/* Initialization */ + +void xtensa_coproc_init(void); + /* IRQs */ uint32_t *xtensa_int_decode(uint32_t *regs); diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index 3e41111a60..50cfda14db 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -148,7 +148,7 @@ _xtensa_context_save: #if XTENSA_EXTRA_SA_SIZE > 0 || !defined(CONFIG_XTENSA_CALL0_ABI) mov a9, a0 /* Preserve ret addr */ - #endif +#endif #ifndef CONFIG_XTENSA_CALL0_ABI /* To spill the reg windows, temp. need pre-interrupt stack ptr and @@ -208,6 +208,8 @@ _xtensa_context_save: ret + .size _xtensa_context_save, . - _xtensa_context_save + /**************************************************************************** * Name: xtensa_context_save * @@ -267,8 +269,11 @@ xtensa_context_save: l32i a0, a2, (4 * REG_A0) /* Recover return addess */ movi a2, 0 /* Return zero */ + ret + .size xtensa_context_save, . - xtensa_context_save + /**************************************************************************** * Name: _xtensa_context_restore * @@ -370,6 +375,8 @@ _xtensa_context_restore: ret + .size _xtensa_context_restore, . - _xtensa_context_restore + /**************************************************************************** * Name: xtensa_context_restore * @@ -418,5 +425,7 @@ xtensa_context_restore: rsr a0, EPC l32i a0, a2, (4 * REG_A0) /* Restore a0 */ l32i a2, a2, (4 * REG_A2) /* Restore A2 */ + rfe /* And return from "exception" */ + .size xtensa_context_restore, . - xtensa_context_restore diff --git a/arch/xtensa/src/common/xtensa_coproc.S b/arch/xtensa/src/common/xtensa_coproc.S index 7e9843c796..18e1efda59 100644 --- a/arch/xtensa/src/common/xtensa_coproc.S +++ b/arch/xtensa/src/common/xtensa_coproc.S @@ -37,9 +37,350 @@ * Included Files ****************************************************************************/ +#include + +#include +#include + +#if XCHAL_CP_NUM > 0 + /**************************************************************************** * Public Functions ****************************************************************************/ .text +/**************************************************************************** + * Name: xtensa_coproc_init + * + * Description: + * Initializes.global co-processor management data, setting all co- + * processors to "unowned". Leaves CPENABLE as it found it (does NOT clear + * it). + * + * Called during initialization of the NuttX, before any threads run. + * + * This may be called from normal Xtensa single-threaded application code + * which might use co-processors. The Xtensa run-time initialization + * enables all co-processors. They must remain enabled here, else a co- + * processor exception might occur outside of a thread, which the exception + * handler doesn't expect. + * + * Entry Conditions: + * Xtensa single-threaded run-time environment is in effect. + * No thread is yet running. + * + * Exit conditions: + * None. + * + * Obeys ABI conventions per prototype: + * void xtensa_coproc_init(void) + * + ****************************************************************************/ + + .global xtensa_coproc_init + .type xtensa_coproc_init, @function + + .align 4 + .literal_position + .align 4 + +xtensa_coproc_init: + + /* Initialize thread co-processor ownerships to 0 (unowned). */ + + movi a2, _xt_coproc_owner_sa /* a2 = base of owner array */ + addi a3, a2, (XTENSA_CP_MAX*portNUM_PROCESSORS) << 2 /* a3 = top+1 of owner array */ + movi a4, 0 /* a4 = 0 (unowned) */ +1: s32i a4, a2, 0 + addi a2, a2, 4 + bltu a2, a3, 1b + + ret + + .size xtensa_coproc_init, . - xtensa_coproc_init + +/**************************************************************************** + * Name: xtensa_coproc_release + * + * Description: + * Releases any and all co-processors owned by a given thread. The thread + * is identified by it's co-processor state save area defined in + * xtensa_context.h . + * + * Must be called before a thread's co-proc save area is deleted to avoid + * memory corruption when the exception handler tries to save the state. + * May be called when a thread terminates or completes but does not delete + * the co-proc save area, to avoid the exception handler having to save the + * thread's co-proc state before another thread can use it (optimization). + * + * Entry Conditions: + * A2 = Pointer to base of co-processor state save area. + * + * Exit conditions: + * None. + * + * Obeys ABI conventions per prototype: + * void xtensa_coproc_release(void * coproc_sa_base) + * + ****************************************************************************/ + +#if 0 /* Not used in current design */ + .global xtensa_coproc_release + .type xtensa_coproc_release, @function + + .align 4 + .literal_position + .align 4 + +xtensa_coproc_release: + getcoreid a5 + movi a3, XTENSA_CP_MAX << 2 + mull a5, a5, a3 + movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */ + add a3, a3, a5 + + addi a4, a3, XTENSA_CP_MAX << 2 /* a4 = top+1 of owner array */ + movi a5, 0 /* a5 = 0 (unowned) */ + + rsil a6, XCHAL_EXCM_LEVEL /* Lock interrupts */ + +1: l32i a7, a3, 0 /* a7 = owner at a3 */ + bne a2, a7, 2f /* if (coproc_sa_base == owner) */ + s32i a5, a3, 0 /* owner = unowned */ +2: addi a3, a3, 1<<2 /* a3 = next entry in owner array */ + bltu a3, a4, 1b /* repeat until end of array */ + +3: wsr a6, PS /* Restore interrupts */ + + ret + + .size xtensa_coproc_release, . - xtensa_coproc_release +#endif + +/**************************************************************************** + * Name: _xtensa_coproc_savestate + * + * Description: + * If there is a current thread and it has a coprocessor state save area, + * then save all callee-saved state into this area. This function is + * called from the solicited context switch handler. It calls a system- + * specific function to get the coprocessor save area base address. + * + * Entry Conditions: + * - The thread being switched out is still the current thread. + * - CPENABLE state reflects which coprocessors are active. + * - Registers have been saved/spilled already. + * + * Exit conditions: + * - All necessary CP callee-saved state has been saved. + * - Registers a2-a7, a13-a15 have been trashed. + * + * Must be called from assembly code only, using CALL0. + * + ****************************************************************************/ + + .extern _xt_coproc_sa_offset /* External reference */ + + .global _xtensa_coproc_savestate + .type _xtensa_coproc_savestate, @function + + .align 4 + .literal_position + .align 4 + +_xtensa_coproc_savestate: + + /* At entry, CPENABLE should be showing which CPs are enabled. */ + + rsr a2, CPENABLE /* a2 = which CPs are enabled */ + beqz a2, .Ldone /* Quick exit if none */ + mov a14, a0 /* Save return address */ + call0 XT_RTOS_CP_STATE /* Get address of CP save area */ + mov a0, a14 /* Restore return address */ + beqz a15, .Ldone /* if none then nothing to do */ + s16i a2, a15, XT_CP_CS_ST /* Save mask of CPs being stored */ + movi a13, _xt_coproc_sa_offset /* Array of CP save offsets */ + l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ + +#if XTENSA_CP0_SA_SIZE > 0 + bbci.l a2, 0, 2f /* CP 0 not enabled */ + l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ + add a3, a14, a15 /* a3 = save area for CP 0 */ + xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XTENSA_CP1_SA_SIZE > 0 + bbci.l a2, 1, 2f /* CP 1 not enabled */ + l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ + add a3, a14, a15 /* a3 = save area for CP 1 */ + xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XTENSA_CP2_SA_SIZE > 0 + bbci.l a2, 2, 2f + l32i a14, a13, 8 + add a3, a14, a15 + xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XTENSA_CP3_SA_SIZE > 0 + bbci.l a2, 3, 2f + l32i a14, a13, 12 + add a3, a14, a15 + xchal_cp3store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XTENSA_CP4_SA_SIZE > 0 + bbci.l a2, 4, 2f + l32i a14, a13, 16 + add a3, a14, a15 + xchal_cp4store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XTENSA_CP5_SA_SIZE > 0 + bbci.l a2, 5, 2f + l32i a14, a13, 20 + add a3, a14, a15 + xchal_cp5store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XTENSA_CP6_SA_SIZE > 0 + bbci.l a2, 6, 2f + l32i a14, a13, 24 + add a3, a14, a15 + xchal_cp6store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XTENSA_CP7_SA_SIZE > 0 + bbci.l a2, 7, 2f + l32i a14, a13, 28 + add a3, a14, a15 + xchal_cp7store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +.Ldone: + ret + + .size _xtensa_coproc_savestate, . - _xtensa_coproc_savestate + +/**************************************************************************** + * Name: _xtensa_coproc_restorestate + * + * Description: + * Restore any callee-saved coprocessor state for the incoming thread. + * This function is called from coprocessor exception handling, when + * giving ownership to a thread that solicited a context switch earlier. + * It calls a system-specific function to get the coprocessor save area base address. + * + * Entry Conditions: + * - The incoming thread is set as the current thread. + * - CPENABLE is set up correctly for all required coprocessors. + * - a2 = mask of coprocessors to be restored. + * + * Exit conditions: + * - All necessary CP callee-saved state has been restored. + * - CPENABLE - unchanged. + * - Registers a2-a7, a13-a15 have been trashed. + * + * Must be called from assembly code only, using CALL0. + * + ****************************************************************************/ + + .global _xtensa_coproc_restorestate + .type _xtensa_coproc_restorestate, @function + + .align 4 + .literal_position + .align 4 + +_xtensa_coproc_restorestate: + + mov a14, a0 /* Save return address */ + call0 XT_RTOS_CP_STATE /* Get address of CP save area */ + mov a0, a14 /* Restore return address */ + beqz a15, .Ldone2 /* if none then nothing to do */ + l16ui a3, a15, XT_CP_CS_ST /* a3 = which CPs have been saved */ + xor a3, a3, a2 /* Clear the ones being restored */ + s32i a3, a15, XT_CP_CS_ST /* Update saved CP mask */ + movi a13, _xt_coproc_sa_offset /* Array of CP save offsets */ + l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ + +#if XTENSA_CP0_SA_SIZE + bbci.l a2, 0, 2f /* CP 0 not enabled */ + l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ + add a3, a14, a15 /* a3 = save area for CP 0 */ + xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XTENSA_CP1_SA_SIZE + bbci.l a2, 1, 2f /* CP 1 not enabled */ + l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ + add a3, a14, a15 /* a3 = save area for CP 1 */ + xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XTENSA_CP2_SA_SIZE + bbci.l a2, 2, 2f + l32i a14, a13, 8 + add a3, a14, a15 + xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XTENSA_CP3_SA_SIZE + bbci.l a2, 3, 2f + l32i a14, a13, 12 + add a3, a14, a15 + xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XTENSA_CP4_SA_SIZE + bbci.l a2, 4, 2f + l32i a14, a13, 16 + add a3, a14, a15 + xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XTENSA_CP5_SA_SIZE + bbci.l a2, 5, 2f + l32i a14, a13, 20 + add a3, a14, a15 + xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XTENSA_CP6_SA_SIZE + bbci.l a2, 6, 2f + l32i a14, a13, 24 + add a3, a14, a15 + xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +#if XTENSA_CP7_SA_SIZE + bbci.l a2, 7, 2f + l32i a14, a13, 28 + add a3, a14, a15 + xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL +2: +#endif + +.Ldone2: + ret + + .size _xtensa_coproc_restorestate, . - _xtensa_coproc_restorestate + +#endif /* XCHAL_CP_NUM > 0 */ diff --git a/arch/xtensa/src/common/xtensa_initialize.c b/arch/xtensa/src/common/xtensa_initialize.c index 2041548b17..979ffd2c11 100644 --- a/arch/xtensa/src/common/xtensa_initialize.c +++ b/arch/xtensa/src/common/xtensa_initialize.c @@ -134,6 +134,12 @@ void up_initialize(void) xtensa_add_region(); +#if XCHAL_CP_NUM > 0 + /* Initialize co-processor management. */ + + xtensa_coproc_init(); +#endif + /* Initialize the interrupt subsystem */ xtensa_irq_initialize(); diff --git a/arch/xtensa/src/common/xtensa_inthandlers.S b/arch/xtensa/src/common/xtensa_inthandlers.S index b716c9f1f2..cc34881b78 100644 --- a/arch/xtensa/src/common/xtensa_inthandlers.S +++ b/arch/xtensa/src/common/xtensa_inthandlers.S @@ -170,7 +170,6 @@ beq a2, sp, 3f /* If timer interrupt then skip table */ /* Switch stacks */ -#warning REVIST: Should use register save are on stack. l32i a4, sp, (4 * REG_A1) /* Retrieve stack ptr and replace */ addi sp, a4, -(4 * XCPTCONTEXT_SIZE) diff --git a/arch/xtensa/src/common/xtensa_irqdispatch.c b/arch/xtensa/src/common/xtensa_irqdispatch.c index 2a3e9920e0..1ed07feb21 100644 --- a/arch/xtensa/src/common/xtensa_irqdispatch.c +++ b/arch/xtensa/src/common/xtensa_irqdispatch.c @@ -46,6 +46,7 @@ #include #include +#include #include "xtensa.h" @@ -57,10 +58,19 @@ uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs) { - board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS + board_autoled_on(LED_INIRQ); PANIC(); + #else +#if XCHAL_CP_NUM > 0 + /* Save the TCB of in case we need to save co-processor state */ + + struct tcb_s *tcb = this_task(); +#endif + + board_autoled_on(LED_INIRQ); + /* Nested interrupts are not supported */ DEBUGASSERT(CURRENT_REGS == NULL); @@ -71,24 +81,45 @@ uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs) CURRENT_REGS = regs; +#if XCHAL_CP_NUM > 0 && !defined(CONFIG_XTENSA_CP_LAZY) + /* Save the current co processor state on entry int each interrupt. */ + + esp32_coproc_savestate(tcb->xcp.cpstate); +#endif + /* Deliver the IRQ */ irq_dispatch(irq, regs); #if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV) /* Check for a context switch. If a context switch occurred, then - * CURRENT_REGS will have a different value than it did on entry. If an - * interrupt level context switch has occurred, then restore the floating - * point state and the establish the correct address environment before - * returning from the interrupt. + * CURRENT_REGS will have a different value than it did on entry. */ if (regs != CURRENT_REGS) { -#ifdef CONFIG_ARCH_FPU - /* Restore floating point registers */ +#if XCHAL_CP_NUM > 0 +#ifdef CONFIG_XTENSA_CP_LAZY + /* If an interrupt level context switch has occurred, then save the + * co-processor state in in the suspended thread's co-processor save + * area. + * + * NOTE 1. The state of the co-processor has not been altered and + * still represents the to-be-suspended thread. + * NOTE 2. We saved a reference TCB of the original thread on entry. + */ + + esp32_coproc_savestate(tcb->xcp.cpstate); +#endif + + /* Set up the co-processor state for the to-be-started thread. + * + * NOTE: The current thread for this CPU is the to-be-started + * thread. + */ - up_restorefpu((uint32_t *)CURRENT_REGS); + tcb = this_task(); + esp32_coproc_restorestate(tcb->xcp.cpstate); #endif #ifdef CONFIG_ARCH_ADDRENV -- GitLab From 5b1a3e6fe085ffcf32168166aebebfff15c792ea Mon Sep 17 00:00:00 2001 From: Vytautas Lukenskas Date: Fri, 28 Oct 2016 09:10:11 -0600 Subject: [PATCH 246/734] Restore RS485 mode on serial port open (if RS485 is enabled via menuconfig). --- arch/arm/src/lpc43xx/lpc43_serial.c | 60 +++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm/src/lpc43xx/lpc43_serial.c b/arch/arm/src/lpc43xx/lpc43_serial.c index def68b88b5..77d9dd3222 100644 --- a/arch/arm/src/lpc43xx/lpc43_serial.c +++ b/arch/arm/src/lpc43xx/lpc43_serial.c @@ -92,6 +92,8 @@ struct up_dev_s uint8_t bits; /* Number of bits (7 or 8) */ bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ #ifdef HAVE_RS485 + bool dctrl; /* Hardware RS485 direction control */ + bool diroinv; /* Direction pin polarity invert */ bool dtrdir; /* DTR pin is the direction bit */ #endif }; @@ -106,6 +108,13 @@ static int up_attach(struct uart_dev_s *dev); static void up_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context); static int up_ioctl(struct file *filep, int cmd, unsigned long arg); +#ifdef HAVE_RS485 +static inline int up_set_rs485_mode(struct up_dev_s *priv, + const struct serial_rs485 *mode); + +static inline int up_get_rs485_mode(struct up_dev_s *priv, + struct serial_rs485 *mode); +#endif static int up_receive(struct uart_dev_s *dev, uint32_t *status); static void up_rxint(struct uart_dev_s *dev, bool enable); static bool up_rxavailable(struct uart_dev_s *dev); @@ -169,6 +178,16 @@ static struct up_dev_s g_uart0priv = .parity = CONFIG_USART0_PARITY, .bits = CONFIG_USART0_BITS, .stopbits2 = CONFIG_USART0_2STOP, +#if defined(CONFIG_USART0_RS485MODE) + .dctrl = true, +# if defined(CONFIG_USART0_RS485DIROIN) + .diroinv = true, +# else + .diroinv = false, +# endif +#elif defined(HAVE_RS485) /* RS485 supported, but not on USART0 */ + .dctrl = false, +#endif }; static uart_dev_t g_uart0port = @@ -236,6 +255,16 @@ static struct up_dev_s g_uart2priv = .parity = CONFIG_USART2_PARITY, .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, +#if defined(CONFIG_USART2_RS485MODE) + .dctrl = true, +# if defined(CONFIG_USART2_RS485DIROIN) + .diroinv = true, +# else + .diroinv = false, +# endif +#elif defined(HAVE_RS485) /* RS485 supported, but not on USART2 */ + .dctrl = false, +#endif }; static uart_dev_t g_uart2port = @@ -268,6 +297,16 @@ static struct up_dev_s g_uart3priv = .parity = CONFIG_USART3_PARITY, .bits = CONFIG_USART3_BITS, .stopbits2 = CONFIG_USART3_2STOP, +#if defined(CONFIG_USART3_RS485MODE) + .dctrl = true, +# if defined(CONFIG_USART3_RS485DIROIN) + .diroinv = true, +# else + .diroinv = false, +# endif +#elif defined(HAVE_RS485) /* RS485 supported, but not on USART3 */ + .dctrl = false, +#endif }; static uart_dev_t g_uart3port = @@ -572,6 +611,9 @@ static int up_setup(struct uart_dev_s *dev) { #ifndef CONFIG_SUPPRESS_UART_CONFIG struct up_dev_s *priv = (struct up_dev_s *)dev->priv; +#ifdef HAVE_RS485 + struct serial_rs485 rs485mode; +#endif uint32_t lcr; /* Clear fifos */ @@ -636,6 +678,24 @@ static int up_setup(struct uart_dev_s *dev) } #endif + /* Setup initial RS485 settings */ + +#ifdef HAVE_RS485 + if (priv->dctrl) + { + rs485mode.flags = SER_RS485_ENABLED; + rs485mode.delay_rts_after_send = 0; + rs485mode.delay_rts_before_send = 0; + + if (priv->diroinv) + { + rs485mode.flags |= SER_RS485_RTS_ON_SEND; + } + + up_set_rs485_mode(priv, &rs485mode); + } +#endif + #endif return OK; } -- GitLab From be2a801e309071cb80686fc1c90ae8087a390dbb Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 28 Oct 2016 10:33:20 -0600 Subject: [PATCH 247/734] Xtensa: Add xtensa_coproc.h --- arch/xtensa/Kconfig | 11 -- arch/xtensa/include/irq.h | 7 + arch/xtensa/include/xtensa/xtensa_coproc.h | 152 +++++++++++++++++++ arch/xtensa/src/common/xtensa_coproc.S | 14 +- arch/xtensa/src/common/xtensa_createstack.c | 63 ++++++-- arch/xtensa/src/common/xtensa_initialstate.c | 21 --- arch/xtensa/src/common/xtensa_irqdispatch.c | 10 +- 7 files changed, 219 insertions(+), 59 deletions(-) create mode 100644 arch/xtensa/include/xtensa/xtensa_coproc.h diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index e90643c82f..a163955de3 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -38,17 +38,6 @@ config XTENSA_CALL0_ABI The Window ABI is not supported. Only the CALL0 ABI is supported in the current implementation. -config XTENSA_CP_LAZY - bool "Lazy Co-processor Save" - default y - ---help--- - If this option is selected, then the co-processor state will be saved - only on context switches. As a consequency of this, co-processors - may NOT be used within interrupt handlers. If you must use co- - processors in interrupt handling, then disable this option. There - will be a significant interrupt latency performance impact if this - option is disabled. - config XTENSA_USE_OVLY bool default n diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index c973d0fe45..863b8ddc61 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -52,6 +52,7 @@ #include #include #include +#include /* Include architecture-specific IRQ definitions */ @@ -158,6 +159,12 @@ struct xcptcontext uint32_t regs[XCPTCONTEXT_REGS]; +#if XCHAL_CP_NUM > 0 + /* Co-processor save area */ + + struct struct xtensa_cpstate_s cpstate; +#endif + #ifdef CONFIG_LIB_SYSCALL /* The following array holds the return address and the exc_return value * needed to return from each nested system call. diff --git a/arch/xtensa/include/xtensa/xtensa_coproc.h b/arch/xtensa/include/xtensa/xtensa_coproc.h new file mode 100644 index 0000000000..70bc31e82a --- /dev/null +++ b/arch/xtensa/include/xtensa/xtensa_coproc.h @@ -0,0 +1,152 @@ +/**************************************************************************** + * arch/xtensa/include/xtensa/xtensa_coproc.h + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * + * Copyright (c) 2006-2015 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_INCLUDE_XTENSA_XTENSA_COPROC_H +#define __ARCH_XTENSA_INCLUDE_XTENSA_XTENSA_COPROC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if XCHAL_CP_NUM > 0 + +/* Align a value up/down to nearest n-byte boundary, where n is a power of 2. */ + +#define _CP_MASK(n) ((n) - 1) +#define _CP_ALIGNUP(n,val) (((val) + _CP_MASK(n)) & ~_CP_MASK(n)) +#define _CP_ALIGNDOWN(n,val) ((val) & ~_CP_MASK(n)) + +/* CO-PROCESSOR STATE SAVE AREA FOR A THREAD + * + * NuttX provides an area per thread to save the state of co-processors when + * that thread does not have control. Co-processors are context-switched + * lazily (on demand) only when a new thread uses a co-processor instruction, + * otherwise a thread retains ownership of the co-processor even when it + * loses control of the processor. An Xtensa co-processor exception is + * triggered when any co-processor instruction is executed by a thread that + * is not the owner, and the context switch of that co-processor is then + * peformed by the handler. Ownership represents which thread's state is + * currently in the co-processor. + * + * Co-processors may not be used by interrupt or exception handlers. If an + * co-processor instruction is executed by an interrupt or exception handler, + * the co-processor exception handler will trigger a kernel panic and freeze. + * This restriction is introduced to reduce the overhead of saving and + * restoring co-processor state (which can be quite large) and in particular + * remove that overhead from interrupt handlers. + * + * The co-processor state save area may be in any convenient per-thread + * location such as in the thread control block or above the thread stack + * area. It need not be in the interrupt stack frame since interrupts don't + * use co-processors. + * + * Along with the save area for each co-processor, two bitmasks with flags + * per co-processor (laid out as in the CPENABLE reg) help manage context- + * switching co-processors as efficiently as possible: + * + * XTENSA_CPENABLE + * The contents of a non-running thread's CPENABLE register. + * It represents the co-processors owned (and whose state is still needed) + * by the thread. When a thread is preempted, its CPENABLE is saved here. + * When a thread solicits a context-swtich, its CPENABLE is cleared - the + * compiler has saved the (caller-saved) co-proc state if it needs to. + * When a non-running thread loses ownership of a CP, its bit is cleared. + * When a thread runs, it's XTENSA_CPENABLE is loaded into the CPENABLE reg. + * Avoids co-processor exceptions when no change of ownership is needed. + * + * XTENSA_CPSTORED + * A bitmask with the same layout as CPENABLE, a bit per co-processor. + * Indicates whether the state of each co-processor is saved in the state + * save area. When a thread enters the kernel, only the state of co-procs + * still enabled in CPENABLE is saved. When the co-processor exception + * handler assigns ownership of a co-processor to a thread, it restores + * the saved state only if this bit is set, and clears this bit. + * + * XTENSA_CPCSST + * A bitmask with the same layout as CPENABLE, a bit per co-processor. + * Indicates whether callee-saved state is saved in the state save area. + * Callee-saved state is saved by itself on a solicited context switch, + * and restored when needed by the coprocessor exception handler. + * Unsolicited switches will cause the entire coprocessor to be saved + * when necessary. + * + * XTENSA_CPASA + * Pointer to the aligned save area. Allows it to be aligned more than + * the overall save area (which might only be stack-aligned or TCB-aligned). + * Especially relevant for Xtensa cores configured with a very large data + * path that requires alignment greater than 16 bytes (ABI stack alignment). + */ + +/* Offsets of each coprocessor save area within the 'aligned save area': */ + +#define XTENSA_CP0_SA 0 +#define XTENSA_CP1_SA _CP_ALIGNUP(XCHAL_CP1_SA_ALIGN, XTENSA_CP0_SA + XCHAL_CP0_SA_SIZE) +#define XTENSA_CP2_SA _CP_ALIGNUP(XCHAL_CP2_SA_ALIGN, XTENSA_CP1_SA + XCHAL_CP1_SA_SIZE) +#define XTENSA_CP3_SA _CP_ALIGNUP(XCHAL_CP3_SA_ALIGN, XTENSA_CP2_SA + XCHAL_CP2_SA_SIZE) +#define XTENSA_CP4_SA _CP_ALIGNUP(XCHAL_CP4_SA_ALIGN, XTENSA_CP3_SA + XCHAL_CP3_SA_SIZE) +#define XTENSA_CP5_SA _CP_ALIGNUP(XCHAL_CP5_SA_ALIGN, XTENSA_CP4_SA + XCHAL_CP4_SA_SIZE) +#define XTENSA_CP6_SA _CP_ALIGNUP(XCHAL_CP6_SA_ALIGN, XTENSA_CP5_SA + XCHAL_CP5_SA_SIZE) +#define XTENSA_CP7_SA _CP_ALIGNUP(XCHAL_CP7_SA_ALIGN, XTENSA_CP6_SA + XCHAL_CP6_SA_SIZE) +#define XTENSA_CP_SA_SIZE _CP_ALIGNUP(16, XTENSA_CP7_SA + XCHAL_CP7_SA_SIZE) + +/* Offsets within the overall save area: */ + +#define XTENSA_CPENABLE 0 /* (2 bytes) coprocessors active for this thread */ +#define XTENSA_CPSTORED 2 /* (2 bytes) coprocessors saved for this thread */ +#define XTENSA_CPCSST 4 /* (2 bytes) coprocessor callee-saved regs stored for this thread */ +#define XTENSA_CPASA 8 /* (4 bytes) ptr to aligned save area */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +struct xtensa_cpstate_s +{ + uint16_t cpenable; /* (2 bytes) coprocessors active for this thread */ + uint16_t cpstored; /* (2 bytes) coprocessors saved for this thread */ + uint16_t cpcsst /* (2 bytes) coprocessor callee-saved regs stored for this thread */ + uint16_t unused; /* (2 bytes) unused */ + uint32_t *cpasa; /* (4 bytes) ptr to aligned save area */ +} + +#endif /* __ASSEMBLY__ */ +#endif /* #if XCHAL_CP_NUM > 0 */ +#endif /* __ARCH_XTENSA_INCLUDE_XTENSA_XTENSA_COPROC_H */ diff --git a/arch/xtensa/src/common/xtensa_coproc.S b/arch/xtensa/src/common/xtensa_coproc.S index 18e1efda59..5b0eb0caf4 100644 --- a/arch/xtensa/src/common/xtensa_coproc.S +++ b/arch/xtensa/src/common/xtensa_coproc.S @@ -195,13 +195,15 @@ _xtensa_coproc_savestate: rsr a2, CPENABLE /* a2 = which CPs are enabled */ beqz a2, .Ldone /* Quick exit if none */ + mov a14, a0 /* Save return address */ call0 XT_RTOS_CP_STATE /* Get address of CP save area */ mov a0, a14 /* Restore return address */ beqz a15, .Ldone /* if none then nothing to do */ - s16i a2, a15, XT_CP_CS_ST /* Save mask of CPs being stored */ + + s16i a2, a15, XTENSA_CPCSST /* Save mask of CPs being stored */ movi a13, _xt_coproc_sa_offset /* Array of CP save offsets */ - l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ + l32i a15, a15, XTENSA_CPASA /* a15 = base of aligned save area */ #if XTENSA_CP0_SA_SIZE > 0 bbci.l a2, 0, 2f /* CP 0 not enabled */ @@ -308,11 +310,13 @@ _xtensa_coproc_restorestate: call0 XT_RTOS_CP_STATE /* Get address of CP save area */ mov a0, a14 /* Restore return address */ beqz a15, .Ldone2 /* if none then nothing to do */ - l16ui a3, a15, XT_CP_CS_ST /* a3 = which CPs have been saved */ + + l16ui a3, a15, XTENSA_CPCSST /* a3 = which CPs have been saved */ xor a3, a3, a2 /* Clear the ones being restored */ - s32i a3, a15, XT_CP_CS_ST /* Update saved CP mask */ + s32i a3, a15, XTENSA_CPCSST /* Update saved CP mask */ + movi a13, _xt_coproc_sa_offset /* Array of CP save offsets */ - l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */ + l32i a15, a15, XTENSA_CPASA /* a15 = base of aligned save area */ #if XTENSA_CP0_SA_SIZE bbci.l a2, 0, 2f /* CP 0 not enabled */ diff --git a/arch/xtensa/src/common/xtensa_createstack.c b/arch/xtensa/src/common/xtensa_createstack.c index 5e1ca5a447..88058eb7f1 100644 --- a/arch/xtensa/src/common/xtensa_createstack.c +++ b/arch/xtensa/src/common/xtensa_createstack.c @@ -47,6 +47,8 @@ #include #include #include + +#include #include #include "xtensa.h" @@ -57,13 +59,11 @@ /* XTENSA requires at least a 4-byte stack alignment. For floating point use, * however, the stack must be aligned to 8-byte addresses. + * + * REVIST: Is this true? Comes from ARM EABI */ -#ifdef CONFIG_LIBC_FLOATINGPOINT -# define STACK_ALIGNMENT 8 -#else -# define STACK_ALIGNMENT 4 -#endif +#define STACK_ALIGNMENT 8 /* Stack alignment macros */ @@ -114,6 +114,12 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) { +#if XCHAL_CP_NUM > 0 + uintptr_t cpstart; + uintptr_t cpend; + size_t cpsize; +#endif + /* Is there already a stack allocated of a different size? Because of * alignment issues, stack_size might erroneously appear to be of a * different size. Fortunately, this is not a critical operation. @@ -126,6 +132,16 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) up_release_stack(tcb, ttype); } +#if XCHAL_CP_NUM > 0 + /* Add the size of the co-processor save area to the stack allocation. + * REVISIT: This may waste memory. Increasing the caller's requested + * stack size should only be necessary if the requested size could not + * hold the co-processor save area. + */ + + stack_size += XTENSA_CP_SA_SIZE; +#endif + /* Do we need to allocate a new stack? */ if (!tcb->stack_alloc_ptr) @@ -163,15 +179,15 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) if (tcb->stack_alloc_ptr) { - size_t top_of_stack; + uintptr_t top_of_stack; size_t size_of_stack; +#ifdef CONFIG_STACK_COLORATION /* Yes.. If stack debug is enabled, then fill the stack with a * recognizable value that we can use later to test for high * water marks. */ -#ifdef CONFIG_STACK_COLORATION memset(tcb->stack_alloc_ptr, 0xaa, stack_size); #endif @@ -181,15 +197,36 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) * the stack are referenced as positive word offsets from sp. */ - top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4; + top_of_stack = (uintptr_t)tcb->stack_alloc_ptr + stack_size - 4; + +#if XCHAL_CP_NUM > 0 + /* Allocate the co-processor save area at the top of the (push down) + * stack. + * + * REVISIT: This is not secure. In secure built configurations it + * be more appropriate to use kmm_memalign() to allocte protected + * memory rather than using the stack. + */ + + cpstart = (uintptr_t)_CP_ALIGNDOWN(top_of_stack - XCHAL_CP1_SA_ALIGN); + top_of_stack = cpstart; + + /* Initialize the coprocessor save area (see xtensa_coproc.h) */ + + xcp->cpstate.cpenable = 0; /* No coprocessors active for this thread */ + xcp->cpstate.cpstored = 0; /* No coprocessors saved for this thread */ + xcp->cpstate.cpcsst = 0; /* No oprocessor callee-saved regs stored for this thread */ + xcp->cpstate.unused = 0; /* unused */ + xcp->cpstate.cpasa = (uint32_t *)cpstart; /* Start of aligned save area */ +#endif - /* The XTENSA stack must be aligned at word (4 byte) boundaries; for - * floating point use, the stack must be aligned to 8-byte addresses. - * If necessary top_of_stack must be rounded down to the next - * boundary to meet these alignment requirements. + /* The XTENSA stack must be aligned. If necessary top_of_stack must be + * rounded down to the next boundary to meet this alignment requirement. + * + * NOTE: Co-processor save area not included in the size of the stack. */ - top_of_stack = STACK_ALIGN_DOWN(top_of_stack); + top_of_stack = STACK_ALIGN_DOWN(top_of_stack); size_of_stack = top_of_stack - (uint32_t)tcb->stack_alloc_ptr + 4; /* Save the adjusted stack values in the struct tcb_s */ diff --git a/arch/xtensa/src/common/xtensa_initialstate.c b/arch/xtensa/src/common/xtensa_initialstate.c index a5e76565f1..6c029a881e 100644 --- a/arch/xtensa/src/common/xtensa_initialstate.c +++ b/arch/xtensa/src/common/xtensa_initialstate.c @@ -71,11 +71,6 @@ void up_initial_state(struct tcb_s *tcb) { struct xcptcontext *xcp = &tcb->xcp; -#if 0 /* REVISIT */ -#if XCHAL_CP_NUM > 0 - uint32_t *ptr; -#endif -#endif /* REVISIT */ /* Initialize the initial exception register context structure */ @@ -99,20 +94,4 @@ void up_initial_state(struct tcb_s *tcb) xcp->regs[REG_PS] = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1); #endif - -#warning REVISIT co-processor support -#if 0 /* REVISIT */ -#if XCHAL_CP_NUM > 0 - /* Init the coprocessor save area (see xtensa_context.h) - * - * No access to TCB here, so derive indirectly. Stack growth is top to bottom. - * //ptr = (uint32_t *) xMPUSettings->coproc_area; - */ - - ptr = (uint32_t *)(((uint32_t)tcb->adj_stack_ptr - XT_CP_SIZE) & ~0xf); - ptr[0] = 0; - ptr[1] = 0; - ptr[2] = (((uint32_t)ptr) + 12 + XTENSA_TOTAL_SA_ALIGN - 1) & -XTENSA_TOTAL_SA_ALIGN; -#endif -#endif /* REVISIT */ } diff --git a/arch/xtensa/src/common/xtensa_irqdispatch.c b/arch/xtensa/src/common/xtensa_irqdispatch.c index 1ed07feb21..aa43b7a9a3 100644 --- a/arch/xtensa/src/common/xtensa_irqdispatch.c +++ b/arch/xtensa/src/common/xtensa_irqdispatch.c @@ -81,12 +81,6 @@ uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs) CURRENT_REGS = regs; -#if XCHAL_CP_NUM > 0 && !defined(CONFIG_XTENSA_CP_LAZY) - /* Save the current co processor state on entry int each interrupt. */ - - esp32_coproc_savestate(tcb->xcp.cpstate); -#endif - /* Deliver the IRQ */ irq_dispatch(irq, regs); @@ -99,7 +93,6 @@ uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs) if (regs != CURRENT_REGS) { #if XCHAL_CP_NUM > 0 -#ifdef CONFIG_XTENSA_CP_LAZY /* If an interrupt level context switch has occurred, then save the * co-processor state in in the suspended thread's co-processor save * area. @@ -110,9 +103,8 @@ uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs) */ esp32_coproc_savestate(tcb->xcp.cpstate); -#endif - /* Set up the co-processor state for the to-be-started thread. + /* Then set up the co-processor state for the to-be-started thread. * * NOTE: The current thread for this CPU is the to-be-started * thread. -- GitLab From b4b26285f17ee461b0d7e343d07f661ba7a1941a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 28 Oct 2016 10:53:14 -0600 Subject: [PATCH 248/734] ESP32: Add tie-asm.h --- arch/xtensa/include/esp32/tie-asm.h | 401 +++++++++++++++++++++++++ arch/xtensa/src/common/xtensa.h | 2 +- arch/xtensa/src/common/xtensa_coproc.S | 1 + 3 files changed, 403 insertions(+), 1 deletion(-) create mode 100644 arch/xtensa/include/esp32/tie-asm.h diff --git a/arch/xtensa/include/esp32/tie-asm.h b/arch/xtensa/include/esp32/tie-asm.h new file mode 100644 index 0000000000..649beaf79e --- /dev/null +++ b/arch/xtensa/include/esp32/tie-asm.h @@ -0,0 +1,401 @@ +/**************************************************************************** + * arch/xtensa/include/esp32/tie-asm.h + * Compile-time assembler definitions dependent on CORE & TIE + * + * This header file contains assembly-language definitions (assembly + * macros, etc.) for this specific Xtensa processor's TIE extensions + * and options. It is customized to this Xtensa processor configuration. + * + * Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_INCLUDE_ESP32_TIE_ASM_H +#define __ARCH_XTENSA_INCLUDE_ESP32_TIE_ASM_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Selection parameter values for save-area save/restore macros: */ +/* Option vs. TIE: + */ + +#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ +#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ +#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ + +/* Whether used automatically by compiler: */ + +#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ +#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ +#define XTHAL_SAS_ANYCC 0x000c /* both of the above */ + +/* ABI handling across function calls: */ + +#define XTHAL_SAS_CALR 0x0010 /* caller-saved */ +#define XTHAL_SAS_CALE 0x0020 /* callee-saved */ +#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ +#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ + +/* Misc */ + +#define XTHAL_SAS_ALL 0xffff /* include all default NCP contents */ +#define XTHAL_SAS3(optie,ccuse,abi) (((optie) & XTHAL_SAS_ANYOT) | \ + ((ccuse) & XTHAL_SAS_ANYCC) | \ + ((abi) & XTHAL_SAS_ANYABI)) + +/**************************************************************************** + * Assembly Language Macros + ****************************************************************************/ + +/* Macro to store all non-coprocessor (extra) custom TIE and optional state + * (not including zero-overhead loop registers). + * + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 4 byte aligned address). + * at1..at4 Four temporary address registers (first XTENSA_NCP_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * + * Optional parameters: + * continue If macro invoked as part of a larger store sequence, set to 1 + * if this is not the first in the sequence. Defaults to 0. + * ofs Offset from start of larger sequence (from value of first ptr + * in sequence) at which to store. Defaults to next available space + * (or 0 if is 0). + * select Select what category(ies) of registers to store, as a bitmask + * (see XTHAL_SAS_xxx constants). Defaults to all registers. + * alloc Select what category(ies) of registers to allocate; if any + * category is selected here that is not in , space for + * the corresponding registers is skipped without doing any load. + */ + + .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + + /* Optional global registers used by default by the compiler: */ + + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) + + xchal_sa_align \ptr, 0, 1016, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wur.THREADPTR \at1 /* threadptr option */ + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 + + xchal_sa_align \ptr, 0, 1016, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + + .endif + + /* Optional caller-saved registers used by default by the compiler: */ + + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) + + xchal_sa_align \ptr, 0, 1012, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wsr.ACCLO \at1 /* MAC16 option */ + l32i \at1, \ptr, .Lxchal_ofs_+4 + wsr.ACCHI \at1 /* MAC16 option */ + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 + + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + + xchal_sa_align \ptr, 0, 1012, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 + + .endif + + /* Optional caller-saved registers not used by default by the compiler: */ + + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + + xchal_sa_align \ptr, 0, 996, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wsr.BR \at1 /* boolean option */ + l32i \at1, \ptr, .Lxchal_ofs_+4 + wsr.SCOMPARE1 \at1 /* conditional store option */ + l32i \at1, \ptr, .Lxchal_ofs_+8 + wsr.M0 \at1 /* MAC16 option */ + l32i \at1, \ptr, .Lxchal_ofs_+12 + wsr.M1 \at1 /* MAC16 option */ + l32i \at1, \ptr, .Lxchal_ofs_+16 + wsr.M2 \at1 /* MAC16 option */ + l32i \at1, \ptr, .Lxchal_ofs_+20 + wsr.M3 \at1 /* MAC16 option */ + .set .Lxchal_ofs_, .Lxchal_ofs_ + 24 + + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + + xchal_sa_align \ptr, 0, 996, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 24 + + .endif + + /* Custom caller-saved registers not used by default by the compiler: */ + + .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + + xchal_sa_align \ptr, 0, 1008, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wur.F64R_LO \at1 /* ureg 234 */ + l32i \at1, \ptr, .Lxchal_ofs_+4 + wur.F64R_HI \at1 /* ureg 235 */ + l32i \at1, \ptr, .Lxchal_ofs_+8 + wur.F64S \at1 /* ureg 236 */ + .set .Lxchal_ofs_, .Lxchal_ofs_ + 12 + + .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + + xchal_sa_align \ptr, 0, 1008, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 12 + + .endif + .endm /* xchal_ncp_load */ + +#define XTENSA_NCP_NUM_ATMPS 1 + +/* Macro to store the state of TIE coprocessor FPU. + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 4 byte aligned address). + * at1..at4 Four temporary address registers (first XTENSA_CP0_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters are the same as for xchal_ncp_store. + */ + +#define xchal_cp_FPU_store xchal_cp0_store + .macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + + /* Custom caller-saved registers not used by default by the compiler: */ + + .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + + xchal_sa_align \ptr, 0, 948, 4, 4 + rur.FCR \at1 /* ureg 232 */ + s32i \at1, \ptr, .Lxchal_ofs_+0 + rur.FSR \at1 /* ureg 233 */ + s32i \at1, \ptr, .Lxchal_ofs_+4 + ssi f0, \ptr, .Lxchal_ofs_+8 + ssi f1, \ptr, .Lxchal_ofs_+12 + ssi f2, \ptr, .Lxchal_ofs_+16 + ssi f3, \ptr, .Lxchal_ofs_+20 + ssi f4, \ptr, .Lxchal_ofs_+24 + ssi f5, \ptr, .Lxchal_ofs_+28 + ssi f6, \ptr, .Lxchal_ofs_+32 + ssi f7, \ptr, .Lxchal_ofs_+36 + ssi f8, \ptr, .Lxchal_ofs_+40 + ssi f9, \ptr, .Lxchal_ofs_+44 + ssi f10, \ptr, .Lxchal_ofs_+48 + ssi f11, \ptr, .Lxchal_ofs_+52 + ssi f12, \ptr, .Lxchal_ofs_+56 + ssi f13, \ptr, .Lxchal_ofs_+60 + ssi f14, \ptr, .Lxchal_ofs_+64 + ssi f15, \ptr, .Lxchal_ofs_+68 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 + + .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + + xchal_sa_align \ptr, 0, 948, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 + + .endif + .endm /* xchal_cp0_store */ + +/* Macro to load the state of TIE coprocessor FPU. + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 4 byte aligned address). + * at1..at4 Four temporary address registers (first XTENSA_CP0_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters are the same as for xchal_ncp_load. + */ + +#define xchal_cp_FPU_load xchal_cp0_load + .macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + + /* Custom caller-saved registers not used by default by the compiler: */ + + .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + + xchal_sa_align \ptr, 0, 948, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wur.FCR \at1 /* ureg 232 */ + l32i \at1, \ptr, .Lxchal_ofs_+4 + wur.FSR \at1 /* ureg 233 */ + lsi f0, \ptr, .Lxchal_ofs_+8 + lsi f1, \ptr, .Lxchal_ofs_+12 + lsi f2, \ptr, .Lxchal_ofs_+16 + lsi f3, \ptr, .Lxchal_ofs_+20 + lsi f4, \ptr, .Lxchal_ofs_+24 + lsi f5, \ptr, .Lxchal_ofs_+28 + lsi f6, \ptr, .Lxchal_ofs_+32 + lsi f7, \ptr, .Lxchal_ofs_+36 + lsi f8, \ptr, .Lxchal_ofs_+40 + lsi f9, \ptr, .Lxchal_ofs_+44 + lsi f10, \ptr, .Lxchal_ofs_+48 + lsi f11, \ptr, .Lxchal_ofs_+52 + lsi f12, \ptr, .Lxchal_ofs_+56 + lsi f13, \ptr, .Lxchal_ofs_+60 + lsi f14, \ptr, .Lxchal_ofs_+64 + lsi f15, \ptr, .Lxchal_ofs_+68 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 + + .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + + xchal_sa_align \ptr, 0, 948, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 + + .endif + .endm /* xchal_cp0_load */ + +#define XTENSA_CP0_NUM_ATMPS 1 +#define XTENSA_SA_NUM_ATMPS 1 + + /* Empty macros for unconfigured coprocessors: */ + + .macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm + .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm + +#endif /*__ARCH_XTENSA_INCLUDE_ESP32_TIE_ASM_H*/ diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index df81f64ba4..6627cf8e62 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -226,7 +226,7 @@ void lowconsole_init(void); /* Debug */ #ifdef CONFIG_ARCH_STACKDUMP -void xtensa_dumpstate(void);s +void xtensa_dumpstate(void); #else # define xtensa_dumpstate() #endif diff --git a/arch/xtensa/src/common/xtensa_coproc.S b/arch/xtensa/src/common/xtensa_coproc.S index 5b0eb0caf4..64f141092f 100644 --- a/arch/xtensa/src/common/xtensa_coproc.S +++ b/arch/xtensa/src/common/xtensa_coproc.S @@ -40,6 +40,7 @@ #include #include +#include #include #if XCHAL_CP_NUM > 0 -- GitLab From a90d0bbf2e7f2e85c30262692e9187ab7e64834b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 28 Oct 2016 11:19:23 -0600 Subject: [PATCH 249/734] ESP32: A little more co-processor logic. Still not complete. --- arch/xtensa/src/common/xtensa_coproc.S | 34 ++++++++++++++----- arch/xtensa/src/common/xtensa_cpsave.c | 46 ++++++++++++++++++++++++++ arch/xtensa/src/esp32/Make.defs | 6 ++-- 3 files changed, 75 insertions(+), 11 deletions(-) create mode 100644 arch/xtensa/src/common/xtensa_cpsave.c diff --git a/arch/xtensa/src/common/xtensa_coproc.S b/arch/xtensa/src/common/xtensa_coproc.S index 64f141092f..16327e2191 100644 --- a/arch/xtensa/src/common/xtensa_coproc.S +++ b/arch/xtensa/src/common/xtensa_coproc.S @@ -41,10 +41,30 @@ #include #include +#include #include #if XCHAL_CP_NUM > 0 +/**************************************************************************** + * Public Data + ****************************************************************************/ + + .section .rodata, "a" + + /* Offset to CP n save area in thread's CP save area. */ + + .global _xtensa_coproc_saoffsets + .type _xtensa_coproc_saoffsets, @object + .align 16 /* Minimize crossing cache boundaries */ + +_xtensa_coproc_saoffsets: + + .word XTENSA_CP0_SA, XTENSA_CP1_SA, XTENSA_CP2_SA, XTENSA_CP3_SA + .word XTENSA_CP4_SA, XTENSA_CP5_SA, XTENSA_CP6_SA, XTENSA_CP7_SA + + .size _xtensa_coproc_saoffsets, . - _xtensa_coproc_saoffsets + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -181,8 +201,6 @@ xtensa_coproc_release: * ****************************************************************************/ - .extern _xt_coproc_sa_offset /* External reference */ - .global _xtensa_coproc_savestate .type _xtensa_coproc_savestate, @function @@ -203,12 +221,12 @@ _xtensa_coproc_savestate: beqz a15, .Ldone /* if none then nothing to do */ s16i a2, a15, XTENSA_CPCSST /* Save mask of CPs being stored */ - movi a13, _xt_coproc_sa_offset /* Array of CP save offsets */ + movi a13, _xtensa_coproc_saoffsets /* Array of CP save offsets */ l32i a15, a15, XTENSA_CPASA /* a15 = base of aligned save area */ #if XTENSA_CP0_SA_SIZE > 0 bbci.l a2, 0, 2f /* CP 0 not enabled */ - l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ + l32i a14, a13, 0 /* a14 = _xtensa_coproc_saoffsets[0] */ add a3, a14, a15 /* a3 = save area for CP 0 */ xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL 2: @@ -216,7 +234,7 @@ _xtensa_coproc_savestate: #if XTENSA_CP1_SA_SIZE > 0 bbci.l a2, 1, 2f /* CP 1 not enabled */ - l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ + l32i a14, a13, 4 /* a14 = _xtensa_coproc_saoffsets[1] */ add a3, a14, a15 /* a3 = save area for CP 1 */ xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL 2: @@ -316,12 +334,12 @@ _xtensa_coproc_restorestate: xor a3, a3, a2 /* Clear the ones being restored */ s32i a3, a15, XTENSA_CPCSST /* Update saved CP mask */ - movi a13, _xt_coproc_sa_offset /* Array of CP save offsets */ + movi a13, _xtensa_coproc_saoffsets /* Array of CP save offsets */ l32i a15, a15, XTENSA_CPASA /* a15 = base of aligned save area */ #if XTENSA_CP0_SA_SIZE bbci.l a2, 0, 2f /* CP 0 not enabled */ - l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */ + l32i a14, a13, 0 /* a14 = _xtensa_coproc_saoffsets[0] */ add a3, a14, a15 /* a3 = save area for CP 0 */ xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL 2: @@ -329,7 +347,7 @@ _xtensa_coproc_restorestate: #if XTENSA_CP1_SA_SIZE bbci.l a2, 1, 2f /* CP 1 not enabled */ - l32i a14, a13, 4 /* a14 = _xt_coproc_sa_offset[1] */ + l32i a14, a13, 4 /* a14 = _xtensa_coproc_saoffsets[1] */ add a3, a14, a15 /* a3 = save area for CP 1 */ xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL 2: diff --git a/arch/xtensa/src/common/xtensa_cpsave.c b/arch/xtensa/src/common/xtensa_cpsave.c new file mode 100644 index 0000000000..12fadeaabd --- /dev/null +++ b/arch/xtensa/src/common/xtensa_cpsave.c @@ -0,0 +1,46 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_cpsave.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "xtensa.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 64c855df37..e14655286d 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -40,11 +40,11 @@ HEAD_CSRC = esp32_start.c # Common XTENSA files (arch/xtensa/src/common) -CMN_ASRCS = xtensa_context.S xtensa_cpuint.S xtensa_vectors.S -CMN_ASRCS += xtensa_inthandlers.S xtensa_nmihandler.S +CMN_ASRCS = xtensa_context.S xtensa_coproc.S xtensa_cpuint.S +CMN_ASRCS += xtensa_inthandlers.S xtensa_nmihandler.S xtensa_vectors.S CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c -CMN_CSRCS += xtensa_createstack.c xtensa_exit.c xtensa_idle.c +CMN_CSRCS += xtensa_cpsave.c xtensa_createstack.c xtensa_exit.c xtensa_idle.c CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c xtensa_interruptcontext.c CMN_CSRCS += xtensa_irqdispatch.c xtensa_lowputs.c xtensa_mdelay.c CMN_CSRCS += xtensa_modifyreg8.c xtensa_modifyreg16.c xtensa_modifyreg32.c -- GitLab From 9345c6f4db196e38fde3f17099dc4b128a9e286d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 28 Oct 2016 11:56:35 -0600 Subject: [PATCH 250/734] Xtensa: More co-processor save logic. Still not complete. --- arch/xtensa/src/common/xtensa.h | 7 +++ arch/xtensa/src/common/xtensa_coproc.S | 46 +++++++------- arch/xtensa/src/common/xtensa_cpsave.c | 70 +++++++++++++++++++++ arch/xtensa/src/common/xtensa_irqdispatch.c | 4 +- 4 files changed, 104 insertions(+), 23 deletions(-) diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index 6627cf8e62..1f06126b2a 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -45,6 +45,8 @@ # include #endif +#include + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -252,6 +254,11 @@ int xtensa_swint(int irq, FAR void *context); int xtensa_context_save(uint32_t *regs); void xtensa_context_restore(uint32_t *regs) noreturn_function; +#if XCHAL_CP_NUM > 0 +void xtensa_coproc_savestate(struct tcb_s *tcb); +void xtensa_coproc_restorestate(struct tcb_s *tcb); +#endif + /* Signals */ void xtensa_sigdeliver(void); diff --git a/arch/xtensa/src/common/xtensa_coproc.S b/arch/xtensa/src/common/xtensa_coproc.S index 16327e2191..62e88570c1 100644 --- a/arch/xtensa/src/common/xtensa_coproc.S +++ b/arch/xtensa/src/common/xtensa_coproc.S @@ -146,7 +146,6 @@ xtensa_coproc_init: * ****************************************************************************/ -#if 0 /* Not used in current design */ .global xtensa_coproc_release .type xtensa_coproc_release, @function @@ -177,7 +176,6 @@ xtensa_coproc_release: ret .size xtensa_coproc_release, . - xtensa_coproc_release -#endif /**************************************************************************** * Name: _xtensa_coproc_savestate @@ -188,7 +186,12 @@ xtensa_coproc_release: * called from the solicited context switch handler. It calls a system- * specific function to get the coprocessor save area base address. * + * It is also called from xtensa_coproc_savestate() for synchronous + * context switches. xtensa_coproc_savestate() is simply a C wrapper + * around the assembly language call to _xtensa_coproc_savestate. + * * Entry Conditions: + * - A2 holds the address of the threads state save area * - The thread being switched out is still the current thread. * - CPENABLE state reflects which coprocessors are active. * - Registers have been saved/spilled already. @@ -210,18 +213,17 @@ xtensa_coproc_release: _xtensa_coproc_savestate: - /* At entry, CPENABLE should be showing which CPs are enabled. */ + /* Move the address of the thread state save area to R15 */ - rsr a2, CPENABLE /* a2 = which CPs are enabled */ - beqz a2, .Ldone /* Quick exit if none */ + mov a15, a2 /* A15 is now the address of the save area */ - mov a14, a0 /* Save return address */ - call0 XT_RTOS_CP_STATE /* Get address of CP save area */ - mov a0, a14 /* Restore return address */ - beqz a15, .Ldone /* if none then nothing to do */ + /* CPENABLE should show which CPs are enabled. */ + + rsr a2, CPENABLE /* a2 = which CPs are enabled */ + beqz a2, .Ldone1 /* Quick exit if none */ s16i a2, a15, XTENSA_CPCSST /* Save mask of CPs being stored */ - movi a13, _xtensa_coproc_saoffsets /* Array of CP save offsets */ + movi a13, _xtensa_coproc_saoffsets /* Array of CP save offsets */ l32i a15, a15, XTENSA_CPASA /* a15 = base of aligned save area */ #if XTENSA_CP0_SA_SIZE > 0 @@ -288,7 +290,7 @@ _xtensa_coproc_savestate: 2: #endif -.Ldone: +.Ldone1: ret .size _xtensa_coproc_savestate, . - _xtensa_coproc_savestate @@ -300,12 +302,17 @@ _xtensa_coproc_savestate: * Restore any callee-saved coprocessor state for the incoming thread. * This function is called from coprocessor exception handling, when * giving ownership to a thread that solicited a context switch earlier. - * It calls a system-specific function to get the coprocessor save area base address. + * It calls a system-specific function to get the coprocessor save area + * base address. + * + * It is also called from xtensa_coproc_restorestate() for synchronous + * context switches. xtensa_coproc_restorestate() is simply a C wrapper + * around the assembly language call to _xtensa_coproc_restorestate. * * Entry Conditions: + * - A2 holds the address of the threads state save area * - The incoming thread is set as the current thread. * - CPENABLE is set up correctly for all required coprocessors. - * - a2 = mask of coprocessors to be restored. * * Exit conditions: * - All necessary CP callee-saved state has been restored. @@ -325,16 +332,14 @@ _xtensa_coproc_savestate: _xtensa_coproc_restorestate: - mov a14, a0 /* Save return address */ - call0 XT_RTOS_CP_STATE /* Get address of CP save area */ - mov a0, a14 /* Restore return address */ - beqz a15, .Ldone2 /* if none then nothing to do */ + /* Move the address of the thread state save area to R15 */ - l16ui a3, a15, XTENSA_CPCSST /* a3 = which CPs have been saved */ - xor a3, a3, a2 /* Clear the ones being restored */ + mov a15, a2 /* A15 is now the address of the save area */ + l16ui a2, a15, XTENSA_CPCSST /* a3 = which CPs have been saved */ + movi a3, 0 /* Clear the ones being restored (all of them) */ s32i a3, a15, XTENSA_CPCSST /* Update saved CP mask */ - movi a13, _xtensa_coproc_saoffsets /* Array of CP save offsets */ + movi a13, _xtensa_coproc_saoffsets /* Array of CP save offsets */ l32i a15, a15, XTENSA_CPASA /* a15 = base of aligned save area */ #if XTENSA_CP0_SA_SIZE @@ -401,7 +406,6 @@ _xtensa_coproc_restorestate: 2: #endif -.Ldone2: ret .size _xtensa_coproc_restorestate, . - _xtensa_coproc_restorestate diff --git a/arch/xtensa/src/common/xtensa_cpsave.c b/arch/xtensa/src/common/xtensa_cpsave.c index 12fadeaabd..3e1f57e563 100644 --- a/arch/xtensa/src/common/xtensa_cpsave.c +++ b/arch/xtensa/src/common/xtensa_cpsave.c @@ -39,8 +39,78 @@ #include +#include + #include "xtensa.h" +#if XCHAL_CP_NUM > 0 + /**************************************************************************** * Public Functions ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_coproc_savestate + * + * Description: + * If there is a current thread and it has a coprocessor state save area, + * then save all callee-saved state into this area. xtensa_coproc_savestate() + * is simply a C wrapper around the assembly language call to + * _xtensa_coproc_savestate. + * + * Entry Conditions: + * - The thread being switched out is still the current thread. + * - CPENABLE state reflects which coprocessors are active. + * + * Exit conditions: + * - All necessary CP callee-saved state has been saved. + * + ****************************************************************************/ + +void xtensa_coproc_savestate(struct tcb_s *tcb) +{ + uint32_t cpsave = (uint32_t)((uintptr_t)&tcp->xcp.cpsave); + + __asm__ __volatile__ + ( + "mov a2, %0\n" + "call0 _xtensa_coproc_savestate\n" + : + : "r" (cpsave) + : "a0", "a2", "a3", "a4", "a5", "a6", "a7", "a13", "a14", "a15" + ) +} + +/**************************************************************************** + * Name: xtensa_coproc_restorestate + * + * Description: + * Restore any callee-saved coprocessor state for the incoming thread. + * xtensa_coproc_restorestate() is simply a C wrapper around the assembly + * language call to _xtensa_coproc_restorestate. + * + * Entry Conditions: + * - CPENABLE is set up correctly for all required coprocessors. + * + * Exit conditions: + * - All necessary CP callee-saved state has been restored. + * - CPENABLE - unchanged. + * + ****************************************************************************/ + +void xtensa_coproc_restorestate(struct tcb_s *tcb) +{ + uint32_t cpsave = (uint32_t)((uintptr_t)&tcp->xcp.cpsave); + + __asm__ __volatile__ + ( + "mov a2, %0\n" + "mov a3, %1\n" + "call0 _xtensa_coproc_restorestate\n" + : + : "r" (cpmask) "r" (cpsave) + : "a0", "a2", "a3", "a4", "a5", "a6", "a7", "a13", "a14", "a15" + ) +} + +#endif /* XCHAL_CP_NUM */ diff --git a/arch/xtensa/src/common/xtensa_irqdispatch.c b/arch/xtensa/src/common/xtensa_irqdispatch.c index aa43b7a9a3..b7ba9a3982 100644 --- a/arch/xtensa/src/common/xtensa_irqdispatch.c +++ b/arch/xtensa/src/common/xtensa_irqdispatch.c @@ -102,7 +102,7 @@ uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs) * NOTE 2. We saved a reference TCB of the original thread on entry. */ - esp32_coproc_savestate(tcb->xcp.cpstate); + xtensa_coproc_savestate(tcb); /* Then set up the co-processor state for the to-be-started thread. * @@ -111,7 +111,7 @@ uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs) */ tcb = this_task(); - esp32_coproc_restorestate(tcb->xcp.cpstate); + esp32_coproc_restorestate(tcb); #endif #ifdef CONFIG_ARCH_ADDRENV -- GitLab From 2fa8b9ba34d73bd0157c1d4f407a060fae796c2b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 28 Oct 2016 13:03:25 -0600 Subject: [PATCH 251/734] Xtensa ESP32: Co-processor state is code complete but uncompiled and untested. --- arch/xtensa/src/common/xtensa.h | 5 +++++ arch/xtensa/src/common/xtensa_blocktask.c | 15 +++++++++++++++ arch/xtensa/src/common/xtensa_coproc.S | 1 + arch/xtensa/src/common/xtensa_exit.c | 13 +++++++++++++ arch/xtensa/src/common/xtensa_irqdispatch.c | 2 +- arch/xtensa/src/common/xtensa_releasepending.c | 15 +++++++++++++++ arch/xtensa/src/common/xtensa_reprioritizertr.c | 15 +++++++++++++++ arch/xtensa/src/common/xtensa_sigdeliver.c | 4 +++- arch/xtensa/src/common/xtensa_unblocktask.c | 16 ++++++++++++++++ arch/xtensa/src/esp32/esp32_cpustart.c | 2 ++ arch/xtensa/src/esp32/esp32_start.c | 2 ++ 11 files changed, 88 insertions(+), 2 deletions(-) diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index 1f06126b2a..c646ca4fca 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -236,8 +236,13 @@ void xtensa_dumpstate(void); /* Common XTENSA functions */ /* Initialization */ +#if XCHAL_CP_NUM > 0 void xtensa_coproc_init(void); +struct xtensa_cpstate_s; +void xtensa_coproc_release(struct xtensa_cpstate_s *cpstate); +#endif + /* IRQs */ uint32_t *xtensa_int_decode(uint32_t *regs); diff --git a/arch/xtensa/src/common/xtensa_blocktask.c b/arch/xtensa/src/common/xtensa_blocktask.c index 82eb5e30c9..d2fb62bf48 100644 --- a/arch/xtensa/src/common/xtensa_blocktask.c +++ b/arch/xtensa/src/common/xtensa_blocktask.c @@ -45,6 +45,7 @@ #include #include +#include #include "sched/sched.h" #include "group/group.h" @@ -148,12 +149,26 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) else if (!xtensa_context_save(rtcb->xcp.regs)) { +#if XCHAL_CP_NUM > 0 + /* Save the co-processor state in in the suspended thread's co- + * processor save area. + */ + + xtensa_coproc_savestate(rtcb); +#endif + /* Restore the exception context of the rtcb at the (new) head * of the ready-to-run task list. */ rtcb = this_task(); +#if XCHAL_CP_NUM > 0 + /* Set up the co-processor state for the newly started thread. */ + + xtensa_coproc_restorestate(rtcb); +#endif + #ifdef CONFIG_ARCH_ADDRENV /* Make sure that the address environment for the previously * running task is closed down gracefully (data caches dump, diff --git a/arch/xtensa/src/common/xtensa_coproc.S b/arch/xtensa/src/common/xtensa_coproc.S index 62e88570c1..434f090684 100644 --- a/arch/xtensa/src/common/xtensa_coproc.S +++ b/arch/xtensa/src/common/xtensa_coproc.S @@ -167,6 +167,7 @@ xtensa_coproc_release: 1: l32i a7, a3, 0 /* a7 = owner at a3 */ bne a2, a7, 2f /* if (coproc_sa_base == owner) */ + s32i a5, a3, 0 /* owner = unowned */ 2: addi a3, a3, 1<<2 /* a3 = next entry in owner array */ bltu a3, a4, 1b /* repeat until end of array */ diff --git a/arch/xtensa/src/common/xtensa_exit.c b/arch/xtensa/src/common/xtensa_exit.c index e6c64aaecd..6eaba07c51 100644 --- a/arch/xtensa/src/common/xtensa_exit.c +++ b/arch/xtensa/src/common/xtensa_exit.c @@ -155,6 +155,13 @@ void _exit(int status) sched_foreach(_xtensa_dumponexit, NULL); #endif +#if XCHAL_CP_NUM > 0 + /* Disable preprocessor support fo the task that is exit-ing. */ + + tcb = this_task(); + xtensa_coproc_release(&tcb->xcp.cpstate); +#endif + /* Destroy the task at the head of the ready to run list. */ (void)task_exit(); @@ -165,6 +172,12 @@ void _exit(int status) tcb = this_task(); +#if XCHAL_CP_NUM > 0 + /* Set up the co-processor state for the newly started thread. */ + + xtensa_coproc_restorestate(tcb); +#endif + #ifdef CONFIG_ARCH_ADDRENV /* Make sure that the address environment for the previously running * task is closed down gracefully (data caches dump, MMU flushed) and diff --git a/arch/xtensa/src/common/xtensa_irqdispatch.c b/arch/xtensa/src/common/xtensa_irqdispatch.c index b7ba9a3982..d509f83e42 100644 --- a/arch/xtensa/src/common/xtensa_irqdispatch.c +++ b/arch/xtensa/src/common/xtensa_irqdispatch.c @@ -111,7 +111,7 @@ uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs) */ tcb = this_task(); - esp32_coproc_restorestate(tcb); + xtensa_coproc_restorestate(tcb); #endif #ifdef CONFIG_ARCH_ADDRENV diff --git a/arch/xtensa/src/common/xtensa_releasepending.c b/arch/xtensa/src/common/xtensa_releasepending.c index 99dc0c39b8..4328d78a7e 100644 --- a/arch/xtensa/src/common/xtensa_releasepending.c +++ b/arch/xtensa/src/common/xtensa_releasepending.c @@ -41,8 +41,10 @@ #include #include + #include #include +#include #include "sched/sched.h" #include "group/group.h" @@ -117,12 +119,25 @@ void up_release_pending(void) else if (!xtensa_context_save(rtcb->xcp.regs)) { +#if XCHAL_CP_NUM > 0 + /* Save the co-processor state in in the suspended thread's co- + * processor save area. + */ + + xtensa_coproc_savestate(rtcb); +#endif /* Restore the exception context of the rtcb at the (new) head * of the ready-to-run task list. */ rtcb = this_task(); +#if XCHAL_CP_NUM > 0 + /* Set up the co-processor state for the newly started thread. */ + + xtensa_coproc_restorestate(rtcb); +#endif + #ifdef CONFIG_ARCH_ADDRENV /* Make sure that the address environment for the previously * running task is closed down gracefully (data caches dump, diff --git a/arch/xtensa/src/common/xtensa_reprioritizertr.c b/arch/xtensa/src/common/xtensa_reprioritizertr.c index 3cc2978f47..eb5255ece8 100644 --- a/arch/xtensa/src/common/xtensa_reprioritizertr.c +++ b/arch/xtensa/src/common/xtensa_reprioritizertr.c @@ -43,8 +43,10 @@ #include #include #include + #include #include +#include #include "sched/sched.h" #include "group/group.h" @@ -170,12 +172,25 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) else if (!xtensa_context_save(rtcb->xcp.regs)) { +#if XCHAL_CP_NUM > 0 + /* Save the co-processor state in in the suspended thread's co- + * processor save area. + */ + + xtensa_coproc_savestate(rtcb); +#endif /* Restore the exception context of the rtcb at the (new) head * of the ready-to-run task list. */ rtcb = this_task(); +#if XCHAL_CP_NUM > 0 + /* Set up the co-processor state for the newly started thread. */ + + xtensa_coproc_restorestate(rtcb); +#endif + #ifdef CONFIG_ARCH_ADDRENV /* Make sure that the address environment for the previously * running task is closed down gracefully (data caches dump, diff --git a/arch/xtensa/src/common/xtensa_sigdeliver.c b/arch/xtensa/src/common/xtensa_sigdeliver.c index 5f54c4035c..ce43441928 100644 --- a/arch/xtensa/src/common/xtensa_sigdeliver.c +++ b/arch/xtensa/src/common/xtensa_sigdeliver.c @@ -117,7 +117,9 @@ void xtensa_sigdeliver(void) (void)up_irq_save(); rtcb->pterrno = saved_errno; - /* Then restore the correct state for this thread of execution. */ + /* Then restore the correct state for this thread of execution. + * NOTE: The co-processor state should already be correct. + */ board_autoled_off(LED_SIGNAL); xtensa_context_restore(regs); diff --git a/arch/xtensa/src/common/xtensa_unblocktask.c b/arch/xtensa/src/common/xtensa_unblocktask.c index e7a37ba410..c7788927c6 100644 --- a/arch/xtensa/src/common/xtensa_unblocktask.c +++ b/arch/xtensa/src/common/xtensa_unblocktask.c @@ -41,8 +41,10 @@ #include #include + #include #include +#include #include "sched/sched.h" #include "group/group.h" @@ -131,6 +133,14 @@ void up_unblock_task(struct tcb_s *tcb) else if (!xtensa_context_save(rtcb->xcp.regs)) { +#if XCHAL_CP_NUM > 0 + /* Save the co-processor state in in the suspended thread's co- + * processor save area. + */ + + xtensa_coproc_savestate(rtcb); +#endif + /* Restore the exception context of the new task that is ready to * run (probably tcb). This is the new rtcb at the head of the * ready-to-run task list. @@ -138,6 +148,12 @@ void up_unblock_task(struct tcb_s *tcb) rtcb = this_task(); +#if XCHAL_CP_NUM > 0 + /* Set up the co-processor state for the newly started thread. */ + + xtensa_coproc_restorestate(rtcb); +#endif + #ifdef CONFIG_ARCH_ADDRENV /* Make sure that the address environment for the previously * running task is closed down gracefully (data caches dump, diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c index 5bf82dfd42..b3c2e90c9c 100644 --- a/arch/xtensa/src/esp32/esp32_cpustart.c +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -146,6 +146,8 @@ int xtensa_start_handler(int irq, FAR void *context) xtensa_disable_all(); +#warning REVISIT: Do we need to disable co-processors here? + /* Detach all peripheral sources APP CPU interrupts */ for (i = 0; i < ESP32_NPERIPHERALS; i++) diff --git a/arch/xtensa/src/esp32/esp32_start.c b/arch/xtensa/src/esp32/esp32_start.c index a468e83a9c..409bcf8813 100644 --- a/arch/xtensa/src/esp32/esp32_start.c +++ b/arch/xtensa/src/esp32/esp32_start.c @@ -85,6 +85,8 @@ void IRAM_ATTR __start(void) memset(&_sbss, 0, (&_ebss - &_sbss) * sizeof(_sbss)); +#warning REVISIT: Do we need to disable co-processors here? + /* Make sure that the APP_CPU is disabled for now */ regval = getreg32(DPORT_APPCPU_CTRL_B_REG); -- GitLab From b344936c7b4467371e69072152b80cca42761d68 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Fri, 28 Oct 2016 23:20:53 +0000 Subject: [PATCH 252/734] STM32F7:otgdev fixed typo --- arch/arm/src/stm32f7/stm32_otgdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/stm32f7/stm32_otgdev.c b/arch/arm/src/stm32f7/stm32_otgdev.c index f06175cb5b..3cdb2a9cae 100644 --- a/arch/arm/src/stm32f7/stm32_otgdev.c +++ b/arch/arm/src/stm32f7/stm32_otgdev.c @@ -3560,7 +3560,7 @@ static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv) /* Clear OTG interrupt */ - stm32_putreg(retval, STM32_OTG_GOTGINT); + stm32_putreg(regval, STM32_OTG_GOTGINT); } #endif -- GitLab From ccf5b4e357de1dbbb42e71bdfdad220203ead63b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 29 Oct 2016 09:36:33 -0600 Subject: [PATCH 253/734] Xtensa: Cleanup of co-processor logic; remove some unnecessary things. --- arch/xtensa/Kconfig | 11 ++ arch/xtensa/include/irq.h | 2 +- arch/xtensa/include/xtensa/xtensa_coproc.h | 56 ++++--- arch/xtensa/src/common/xtensa.h | 2 + arch/xtensa/src/common/xtensa_coproc.S | 7 +- arch/xtensa/src/common/xtensa_cpsave.c | 145 +++++++++++++++++-- arch/xtensa/src/common/xtensa_createstack.c | 2 - arch/xtensa/src/common/xtensa_exit.c | 3 +- arch/xtensa/src/common/xtensa_initialstate.c | 9 ++ arch/xtensa/src/common/xtensa_vectors.S | 1 + 10 files changed, 202 insertions(+), 36 deletions(-) diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index a163955de3..3c1fcacb82 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -44,6 +44,17 @@ config XTENSA_USE_OVLY ---help--- Enable code overlay support. This option is currently unsupported. +config XTENSA_CP_INITSET + bool "Default co-processor enables" + default 1 + range 0 65535 + ---help--- + Co-processors may be enabled on a thread by calling xtensa_coproc_enable() + and disabled by calling xtensa_coproc_disable(). Some co-processors + should be enabled on all threads by default. That set of co-processors + is provided by CONFIG_XTENSA_CP_INITSET. Each bit corresponds to one + coprocessor with the same bit layout as for the CPENABLE register. + config ARCH_CHIP string default "esp32" if ARCH_CHIP_ESP32 diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index 863b8ddc61..015bb16fe4 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -162,7 +162,7 @@ struct xcptcontext #if XCHAL_CP_NUM > 0 /* Co-processor save area */ - struct struct xtensa_cpstate_s cpstate; + struct xtensa_cpstate_s cpstate; #endif #ifdef CONFIG_LIB_SYSCALL diff --git a/arch/xtensa/include/xtensa/xtensa_coproc.h b/arch/xtensa/include/xtensa/xtensa_coproc.h index 70bc31e82a..c744393cbb 100644 --- a/arch/xtensa/include/xtensa/xtensa_coproc.h +++ b/arch/xtensa/include/xtensa/xtensa_coproc.h @@ -52,6 +52,10 @@ #define _CP_ALIGNUP(n,val) (((val) + _CP_MASK(n)) & ~_CP_MASK(n)) #define _CP_ALIGNDOWN(n,val) ((val) & ~_CP_MASK(n)) +/* A set of all co-processors */ + +#define XTENSA_CP_ALLSET ((1 << XCHAL_CP_NUM) - 1) + /* CO-PROCESSOR STATE SAVE AREA FOR A THREAD * * NuttX provides an area per thread to save the state of co-processors when @@ -93,18 +97,11 @@ * XTENSA_CPSTORED * A bitmask with the same layout as CPENABLE, a bit per co-processor. * Indicates whether the state of each co-processor is saved in the state - * save area. When a thread enters the kernel, only the state of co-procs - * still enabled in CPENABLE is saved. When the co-processor exception - * handler assigns ownership of a co-processor to a thread, it restores - * the saved state only if this bit is set, and clears this bit. - * - * XTENSA_CPCSST - * A bitmask with the same layout as CPENABLE, a bit per co-processor. - * Indicates whether callee-saved state is saved in the state save area. - * Callee-saved state is saved by itself on a solicited context switch, - * and restored when needed by the coprocessor exception handler. - * Unsolicited switches will cause the entire coprocessor to be saved - * when necessary. + * save area. When the state of a thread is saved, only the state of co-procs + * still enabled in CPENABLE is saved. When the co-processor state is + * is restored, the state is only resotred for a co-processor if this bit + * is set. This bist set is cleared after after co-processor state has + * been restored. * * XTENSA_CPASA * Pointer to the aligned save area. Allows it to be aligned more than @@ -129,8 +126,7 @@ #define XTENSA_CPENABLE 0 /* (2 bytes) coprocessors active for this thread */ #define XTENSA_CPSTORED 2 /* (2 bytes) coprocessors saved for this thread */ -#define XTENSA_CPCSST 4 /* (2 bytes) coprocessor callee-saved regs stored for this thread */ -#define XTENSA_CPASA 8 /* (4 bytes) ptr to aligned save area */ +#define XTENSA_CPASA 4 /* (4 bytes) ptr to aligned save area */ /**************************************************************************** * Public Types @@ -140,11 +136,33 @@ struct xtensa_cpstate_s { - uint16_t cpenable; /* (2 bytes) coprocessors active for this thread */ - uint16_t cpstored; /* (2 bytes) coprocessors saved for this thread */ - uint16_t cpcsst /* (2 bytes) coprocessor callee-saved regs stored for this thread */ - uint16_t unused; /* (2 bytes) unused */ - uint32_t *cpasa; /* (4 bytes) ptr to aligned save area */ + uint16_t cpenable; /* (2 bytes) Co-processors active for this thread */ + uint16_t cpstored; /* (2 bytes) Co-processors saved for this thread */ + uint32_t *cpasa; /* (4 bytes) Pointer to aligned save area */ +} + +/* Return the current value of the CPENABLE register */ + +static inline uint32_t xtensa_get_cpenable(void) +{ + uint32_t cpenable; + + __asm__ __volatile__ + ( + "rsr %0, CPENABLE" : "=r"(cpenable) + ); + + return cpenable; +} + +/* Set the value of the CPENABLE register */ + +static inline void xtensa_set_cpenable(uint32_t cpenable) +{ + __asm__ __volatile__ + ( + "wsr %0, PS" : : "r"(cpenable) + ); } #endif /* __ASSEMBLY__ */ diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index c646ca4fca..5d2448728e 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -241,6 +241,8 @@ void xtensa_coproc_init(void); struct xtensa_cpstate_s; void xtensa_coproc_release(struct xtensa_cpstate_s *cpstate); +void xtensa_coproc_enable(struct xtensa_cpstate_s *cpstate, int cpset); +void xtensa_coproc_disable(struct xtensa_cpstate_s *cpstate, int cpset); #endif /* IRQs */ diff --git a/arch/xtensa/src/common/xtensa_coproc.S b/arch/xtensa/src/common/xtensa_coproc.S index 434f090684..419507fbdf 100644 --- a/arch/xtensa/src/common/xtensa_coproc.S +++ b/arch/xtensa/src/common/xtensa_coproc.S @@ -113,6 +113,7 @@ xtensa_coproc_init: movi a2, _xt_coproc_owner_sa /* a2 = base of owner array */ addi a3, a2, (XTENSA_CP_MAX*portNUM_PROCESSORS) << 2 /* a3 = top+1 of owner array */ movi a4, 0 /* a4 = 0 (unowned) */ + 1: s32i a4, a2, 0 addi a2, a2, 4 bltu a2, a3, 1b @@ -223,7 +224,7 @@ _xtensa_coproc_savestate: rsr a2, CPENABLE /* a2 = which CPs are enabled */ beqz a2, .Ldone1 /* Quick exit if none */ - s16i a2, a15, XTENSA_CPCSST /* Save mask of CPs being stored */ + s16i a2, a15, XTENSA_CPSTORED /* Save mask of CPs being stored */ movi a13, _xtensa_coproc_saoffsets /* Array of CP save offsets */ l32i a15, a15, XTENSA_CPASA /* a15 = base of aligned save area */ @@ -336,9 +337,9 @@ _xtensa_coproc_restorestate: /* Move the address of the thread state save area to R15 */ mov a15, a2 /* A15 is now the address of the save area */ - l16ui a2, a15, XTENSA_CPCSST /* a3 = which CPs have been saved */ + l16ui a2, a15, XTENSA_CPSTORED /* a2 = which CPs have been saved */ movi a3, 0 /* Clear the ones being restored (all of them) */ - s32i a3, a15, XTENSA_CPCSST /* Update saved CP mask */ + s16i a3, a15, XTENSA_CPSTORED /* Clear saved CP mask */ movi a13, _xtensa_coproc_saoffsets /* Array of CP save offsets */ l32i a15, a15, XTENSA_CPASA /* a15 = base of aligned save area */ diff --git a/arch/xtensa/src/common/xtensa_cpsave.c b/arch/xtensa/src/common/xtensa_cpsave.c index 3e1f57e563..7a128c6aa1 100644 --- a/arch/xtensa/src/common/xtensa_cpsave.c +++ b/arch/xtensa/src/common/xtensa_cpsave.c @@ -39,6 +39,8 @@ #include +#include +#include #include #include "xtensa.h" @@ -58,12 +60,22 @@ * is simply a C wrapper around the assembly language call to * _xtensa_coproc_savestate. * - * Entry Conditions: - * - The thread being switched out is still the current thread. - * - CPENABLE state reflects which coprocessors are active. + * Entry Conditions: + * - The thread being switched out is still the current thread. + * - CPENABLE state reflects which coprocessors are active. * - * Exit conditions: - * - All necessary CP callee-saved state has been saved. + * Exit conditions: + * - All necessary CP callee-saved state has been saved. + * + * Input Parameters: + * tcb - A pointer to the TCB of thread whose co-processor state is to + * be saved. + * + * Returned Value: + * None + * + * Assumptions: + * Called with interrupts disabled. * ****************************************************************************/ @@ -89,12 +101,22 @@ void xtensa_coproc_savestate(struct tcb_s *tcb) * xtensa_coproc_restorestate() is simply a C wrapper around the assembly * language call to _xtensa_coproc_restorestate. * - * Entry Conditions: - * - CPENABLE is set up correctly for all required coprocessors. + * Entry Conditions: + * - CPENABLE is set up correctly for all required coprocessors. + * + * Exit conditions: + * - All necessary CP callee-saved state has been restored. + * - CPENABLE - unchanged. + * + * Input Parameters: + * tcb - A pointer to the TCB of thread whose co-processor state is to + * be restored. + * + * Returned Value: + * None * - * Exit conditions: - * - All necessary CP callee-saved state has been restored. - * - CPENABLE - unchanged. + * Assumptions: + * Called with interrupts disabled. * ****************************************************************************/ @@ -113,4 +135,107 @@ void xtensa_coproc_restorestate(struct tcb_s *tcb) ) } +/**************************************************************************** + * Name: xtensa_coproc_enable + * + * Description: + * Enable a set of co-processors. + * + * Input Parameters: + * cpstate - A pointer to the Co-processor state save structure. + * cpset - A bit set of co-processors to be enabled. Matches bit layout + * of the CPENABLE register. Bit 0-XCHAL_CP_NUM: 0 = no change + * 1 = enable + * + * Returned Value: + * None + * + ****************************************************************************/ + +void xtensa_coproc_enable(struct xtensa_cpstate_s *cpstate, int cpset) +{ + irqstate_t flags; + uint32_t cpenable; + + /* These operations must be atomic */ + + flags = enter_critical_section(); + + /* Don't enable co-processors that may already be enabled + * + * cpenable + * 0 1 + * --- --- + * cpset 0 | 0 0 + * 1 | 1 0 + */ + + cpset ^= (cpset & cpstate->cpenable); + if (cpset != 0) + { + /* Enable the co-processors */ + + cpenable = xtensa_get_cpenable(); + cpenable |= cpset; + xtensa_put_cpenable(cpenable); + + cpstate->cpenable = cpenable; + cpsates->cpstored &= ~cpset; + } + + leave_critical_section(); +} + +/**************************************************************************** + * Name: xtensa_coproc_disable + * + * Description: + * Enable a set of co-processors. + * + * Input Parameters: + * cpstate - A pointer to the Co-processor state save structure. + * cpset - A bit set of co-processors to be enabled. Matches bit layout + * of the CPENABLE register. Bit 0-XCHAL_CP_NUM: 0 = no change + * 1 = disable + * + * Returned Value: + * None + * + ****************************************************************************/ + +void xtensa_coproc_disable(struct xtensa_cpstate_s *cpstate, int cpset) +{ + irqstate_t flags; + uint32_t cpenable; + + /* These operations must be atomic */ + + flags = enter_critical_section(); + + /* Don't disable co-processors that are already be disabled. + * + * cpenable + * 0 1 + * --- --- + * cpset 0 | 0 0 + * 1 | 0 1 + */ + + cpset &= cpstate->cpenable; + if (cpset != 0) + { + /* Disable the co-processors */ + + cpenable = xtensa_get_cpenable(); + cpenable &= ~cpset; + xtensa_put_cpenable(cpenable); + + cpstate->cpenable = cpenable; + cpsates->cpstored &= ~cpset; + } + + leave_critical_section(); +} + + #endif /* XCHAL_CP_NUM */ diff --git a/arch/xtensa/src/common/xtensa_createstack.c b/arch/xtensa/src/common/xtensa_createstack.c index 88058eb7f1..000f0dd990 100644 --- a/arch/xtensa/src/common/xtensa_createstack.c +++ b/arch/xtensa/src/common/xtensa_createstack.c @@ -215,8 +215,6 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) xcp->cpstate.cpenable = 0; /* No coprocessors active for this thread */ xcp->cpstate.cpstored = 0; /* No coprocessors saved for this thread */ - xcp->cpstate.cpcsst = 0; /* No oprocessor callee-saved regs stored for this thread */ - xcp->cpstate.unused = 0; /* unused */ xcp->cpstate.cpasa = (uint32_t *)cpstart; /* Start of aligned save area */ #endif diff --git a/arch/xtensa/src/common/xtensa_exit.c b/arch/xtensa/src/common/xtensa_exit.c index 6eaba07c51..98ec9b6c5a 100644 --- a/arch/xtensa/src/common/xtensa_exit.c +++ b/arch/xtensa/src/common/xtensa_exit.c @@ -156,10 +156,11 @@ void _exit(int status) #endif #if XCHAL_CP_NUM > 0 - /* Disable preprocessor support fo the task that is exit-ing. */ + /* Disable co-processor support for the task that is exit-ing. */ tcb = this_task(); xtensa_coproc_release(&tcb->xcp.cpstate); + xtensa_coproc_disable(&tcb->xcp.cpstate, XTENSA_CP_ALLSET); #endif /* Destroy the task at the head of the ready to run list. */ diff --git a/arch/xtensa/src/common/xtensa_initialstate.c b/arch/xtensa/src/common/xtensa_initialstate.c index 6c029a881e..8fc10a6d03 100644 --- a/arch/xtensa/src/common/xtensa_initialstate.c +++ b/arch/xtensa/src/common/xtensa_initialstate.c @@ -94,4 +94,13 @@ void up_initial_state(struct tcb_s *tcb) xcp->regs[REG_PS] = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1); #endif + +#if XCHAL_CP_NUM > 0 + /* Set up the co-processors that will be enabled initially when the thread + * starts (see xtensa_coproc.h) + */ + + xcp->cpstate.cpenable = CONFIG_XTENSA_CP_INITSET; + xcp->cpstate.cpstored = 0; /* No coprocessors haved statee saved for this thread */ +#endif } diff --git a/arch/xtensa/src/common/xtensa_vectors.S b/arch/xtensa/src/common/xtensa_vectors.S index 19773e7e8a..a9b440e770 100644 --- a/arch/xtensa/src/common/xtensa_vectors.S +++ b/arch/xtensa/src/common/xtensa_vectors.S @@ -174,6 +174,7 @@ _xtensa_level6_vector: .align 4 _xtensa_nmi_vector: + wsr a0, EXCSAVE + XCHAL_NMILEVEL _ /* preserve a0 */ call0 _xt_nmi /* load interrupt handler */ -- GitLab From 4943b09ffa62213b5dfba58b4477cefb4645b60c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 29 Oct 2016 09:50:51 -0600 Subject: [PATCH 254/734] Xtensa: Remove co-processor ownership array. I think that this is not needed (but I might be wrong). --- arch/xtensa/src/common/xtensa.h | 3 - arch/xtensa/src/common/xtensa_coproc.S | 108 --------------------- arch/xtensa/src/common/xtensa_exit.c | 1 - arch/xtensa/src/common/xtensa_initialize.c | 6 -- 4 files changed, 118 deletions(-) diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index 5d2448728e..6827428c11 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -237,10 +237,7 @@ void xtensa_dumpstate(void); /* Initialization */ #if XCHAL_CP_NUM > 0 -void xtensa_coproc_init(void); - struct xtensa_cpstate_s; -void xtensa_coproc_release(struct xtensa_cpstate_s *cpstate); void xtensa_coproc_enable(struct xtensa_cpstate_s *cpstate, int cpset); void xtensa_coproc_disable(struct xtensa_cpstate_s *cpstate, int cpset); #endif diff --git a/arch/xtensa/src/common/xtensa_coproc.S b/arch/xtensa/src/common/xtensa_coproc.S index 419507fbdf..3ae4dea3d6 100644 --- a/arch/xtensa/src/common/xtensa_coproc.S +++ b/arch/xtensa/src/common/xtensa_coproc.S @@ -71,114 +71,6 @@ _xtensa_coproc_saoffsets: .text -/**************************************************************************** - * Name: xtensa_coproc_init - * - * Description: - * Initializes.global co-processor management data, setting all co- - * processors to "unowned". Leaves CPENABLE as it found it (does NOT clear - * it). - * - * Called during initialization of the NuttX, before any threads run. - * - * This may be called from normal Xtensa single-threaded application code - * which might use co-processors. The Xtensa run-time initialization - * enables all co-processors. They must remain enabled here, else a co- - * processor exception might occur outside of a thread, which the exception - * handler doesn't expect. - * - * Entry Conditions: - * Xtensa single-threaded run-time environment is in effect. - * No thread is yet running. - * - * Exit conditions: - * None. - * - * Obeys ABI conventions per prototype: - * void xtensa_coproc_init(void) - * - ****************************************************************************/ - - .global xtensa_coproc_init - .type xtensa_coproc_init, @function - - .align 4 - .literal_position - .align 4 - -xtensa_coproc_init: - - /* Initialize thread co-processor ownerships to 0 (unowned). */ - - movi a2, _xt_coproc_owner_sa /* a2 = base of owner array */ - addi a3, a2, (XTENSA_CP_MAX*portNUM_PROCESSORS) << 2 /* a3 = top+1 of owner array */ - movi a4, 0 /* a4 = 0 (unowned) */ - -1: s32i a4, a2, 0 - addi a2, a2, 4 - bltu a2, a3, 1b - - ret - - .size xtensa_coproc_init, . - xtensa_coproc_init - -/**************************************************************************** - * Name: xtensa_coproc_release - * - * Description: - * Releases any and all co-processors owned by a given thread. The thread - * is identified by it's co-processor state save area defined in - * xtensa_context.h . - * - * Must be called before a thread's co-proc save area is deleted to avoid - * memory corruption when the exception handler tries to save the state. - * May be called when a thread terminates or completes but does not delete - * the co-proc save area, to avoid the exception handler having to save the - * thread's co-proc state before another thread can use it (optimization). - * - * Entry Conditions: - * A2 = Pointer to base of co-processor state save area. - * - * Exit conditions: - * None. - * - * Obeys ABI conventions per prototype: - * void xtensa_coproc_release(void * coproc_sa_base) - * - ****************************************************************************/ - - .global xtensa_coproc_release - .type xtensa_coproc_release, @function - - .align 4 - .literal_position - .align 4 - -xtensa_coproc_release: - getcoreid a5 - movi a3, XTENSA_CP_MAX << 2 - mull a5, a5, a3 - movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */ - add a3, a3, a5 - - addi a4, a3, XTENSA_CP_MAX << 2 /* a4 = top+1 of owner array */ - movi a5, 0 /* a5 = 0 (unowned) */ - - rsil a6, XCHAL_EXCM_LEVEL /* Lock interrupts */ - -1: l32i a7, a3, 0 /* a7 = owner at a3 */ - bne a2, a7, 2f /* if (coproc_sa_base == owner) */ - - s32i a5, a3, 0 /* owner = unowned */ -2: addi a3, a3, 1<<2 /* a3 = next entry in owner array */ - bltu a3, a4, 1b /* repeat until end of array */ - -3: wsr a6, PS /* Restore interrupts */ - - ret - - .size xtensa_coproc_release, . - xtensa_coproc_release - /**************************************************************************** * Name: _xtensa_coproc_savestate * diff --git a/arch/xtensa/src/common/xtensa_exit.c b/arch/xtensa/src/common/xtensa_exit.c index 98ec9b6c5a..bf568f10d4 100644 --- a/arch/xtensa/src/common/xtensa_exit.c +++ b/arch/xtensa/src/common/xtensa_exit.c @@ -159,7 +159,6 @@ void _exit(int status) /* Disable co-processor support for the task that is exit-ing. */ tcb = this_task(); - xtensa_coproc_release(&tcb->xcp.cpstate); xtensa_coproc_disable(&tcb->xcp.cpstate, XTENSA_CP_ALLSET); #endif diff --git a/arch/xtensa/src/common/xtensa_initialize.c b/arch/xtensa/src/common/xtensa_initialize.c index 979ffd2c11..2041548b17 100644 --- a/arch/xtensa/src/common/xtensa_initialize.c +++ b/arch/xtensa/src/common/xtensa_initialize.c @@ -134,12 +134,6 @@ void up_initialize(void) xtensa_add_region(); -#if XCHAL_CP_NUM > 0 - /* Initialize co-processor management. */ - - xtensa_coproc_init(); -#endif - /* Initialize the interrupt subsystem */ xtensa_irq_initialize(); -- GitLab From d346f25aae4fd16e755f984c1d664f1466090935 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 29 Oct 2016 10:27:46 -0600 Subject: [PATCH 255/734] Xtensa/ESP32: Fix some compile issues related to new co-processor logic --- arch/xtensa/Kconfig | 6 ++-- arch/xtensa/include/irq.h | 3 ++ arch/xtensa/include/xtensa/xtensa_coproc.h | 8 +++-- arch/xtensa/src/common/xtensa.h | 2 ++ arch/xtensa/src/common/xtensa_context.S | 1 + arch/xtensa/src/common/xtensa_coproc.S | 38 ++++++++++---------- arch/xtensa/src/common/xtensa_cpsave.c | 27 +++++++------- arch/xtensa/src/common/xtensa_createstack.c | 8 +++-- arch/xtensa/src/common/xtensa_initialstate.c | 3 +- arch/xtensa/src/common/xtensa_irqdispatch.c | 1 + arch/xtensa/src/esp32/esp32_intdecode.c | 1 + configs/esp32-core/nsh/defconfig | 1 + 12 files changed, 59 insertions(+), 40 deletions(-) diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 3c1fcacb82..124cb96a99 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -45,9 +45,9 @@ config XTENSA_USE_OVLY Enable code overlay support. This option is currently unsupported. config XTENSA_CP_INITSET - bool "Default co-processor enables" - default 1 - range 0 65535 + hex "Default co-processor enables" + default 0x0001 + range 0 0xffff ---help--- Co-processors may be enabled on a thread by calling xtensa_coproc_enable() and disabled by calling xtensa_coproc_disable(). Some co-processors diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index 015bb16fe4..1ee9721e38 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -48,8 +48,11 @@ #include #include + #include +#include #include + #include #include #include diff --git a/arch/xtensa/include/xtensa/xtensa_coproc.h b/arch/xtensa/include/xtensa/xtensa_coproc.h index c744393cbb..5479444703 100644 --- a/arch/xtensa/include/xtensa/xtensa_coproc.h +++ b/arch/xtensa/include/xtensa/xtensa_coproc.h @@ -38,7 +38,7 @@ * Included Files ****************************************************************************/ -#include +#include /**************************************************************************** * Pre-processor Definitions @@ -139,7 +139,11 @@ struct xtensa_cpstate_s uint16_t cpenable; /* (2 bytes) Co-processors active for this thread */ uint16_t cpstored; /* (2 bytes) Co-processors saved for this thread */ uint32_t *cpasa; /* (4 bytes) Pointer to aligned save area */ -} +}; + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ /* Return the current value of the CPENABLE register */ diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index 6827428c11..fb1ba85dd6 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -46,6 +46,7 @@ #endif #include +#include /**************************************************************************** * Pre-processor Definitions @@ -259,6 +260,7 @@ int xtensa_context_save(uint32_t *regs); void xtensa_context_restore(uint32_t *regs) noreturn_function; #if XCHAL_CP_NUM > 0 +struct tcb_s; void xtensa_coproc_savestate(struct tcb_s *tcb); void xtensa_coproc_restorestate(struct tcb_s *tcb); #endif diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index 50cfda14db..6d32fc92b3 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -62,6 +62,7 @@ #include #include +#include #include #warning REVIST XTENSA_EXTRA_SA_SIZE is not yet provided diff --git a/arch/xtensa/src/common/xtensa_coproc.S b/arch/xtensa/src/common/xtensa_coproc.S index 3ae4dea3d6..2445eaecf3 100644 --- a/arch/xtensa/src/common/xtensa_coproc.S +++ b/arch/xtensa/src/common/xtensa_coproc.S @@ -39,10 +39,12 @@ #include -#include -#include +#include #include #include +#include +#include +#include #if XCHAL_CP_NUM > 0 @@ -120,7 +122,7 @@ _xtensa_coproc_savestate: movi a13, _xtensa_coproc_saoffsets /* Array of CP save offsets */ l32i a15, a15, XTENSA_CPASA /* a15 = base of aligned save area */ -#if XTENSA_CP0_SA_SIZE > 0 +#if XCHAL_CP0_SA_SIZE > 0 bbci.l a2, 0, 2f /* CP 0 not enabled */ l32i a14, a13, 0 /* a14 = _xtensa_coproc_saoffsets[0] */ add a3, a14, a15 /* a3 = save area for CP 0 */ @@ -128,7 +130,7 @@ _xtensa_coproc_savestate: 2: #endif -#if XTENSA_CP1_SA_SIZE > 0 +#if XCHAL_CP1_SA_SIZE > 0 bbci.l a2, 1, 2f /* CP 1 not enabled */ l32i a14, a13, 4 /* a14 = _xtensa_coproc_saoffsets[1] */ add a3, a14, a15 /* a3 = save area for CP 1 */ @@ -136,7 +138,7 @@ _xtensa_coproc_savestate: 2: #endif -#if XTENSA_CP2_SA_SIZE > 0 +#if XCHAL_CP2_SA_SIZE > 0 bbci.l a2, 2, 2f l32i a14, a13, 8 add a3, a14, a15 @@ -144,7 +146,7 @@ _xtensa_coproc_savestate: 2: #endif -#if XTENSA_CP3_SA_SIZE > 0 +#if XCHAL_CP3_SA_SIZE > 0 bbci.l a2, 3, 2f l32i a14, a13, 12 add a3, a14, a15 @@ -152,7 +154,7 @@ _xtensa_coproc_savestate: 2: #endif -#if XTENSA_CP4_SA_SIZE > 0 +#if XCHAL_CP4_SA_SIZE > 0 bbci.l a2, 4, 2f l32i a14, a13, 16 add a3, a14, a15 @@ -160,7 +162,7 @@ _xtensa_coproc_savestate: 2: #endif -#if XTENSA_CP5_SA_SIZE > 0 +#if XCHAL_CP5_SA_SIZE > 0 bbci.l a2, 5, 2f l32i a14, a13, 20 add a3, a14, a15 @@ -168,7 +170,7 @@ _xtensa_coproc_savestate: 2: #endif -#if XTENSA_CP6_SA_SIZE > 0 +#if XCHAL_CP6_SA_SIZE > 0 bbci.l a2, 6, 2f l32i a14, a13, 24 add a3, a14, a15 @@ -176,7 +178,7 @@ _xtensa_coproc_savestate: 2: #endif -#if XTENSA_CP7_SA_SIZE > 0 +#if XCHAL_CP7_SA_SIZE > 0 bbci.l a2, 7, 2f l32i a14, a13, 28 add a3, a14, a15 @@ -236,7 +238,7 @@ _xtensa_coproc_restorestate: movi a13, _xtensa_coproc_saoffsets /* Array of CP save offsets */ l32i a15, a15, XTENSA_CPASA /* a15 = base of aligned save area */ -#if XTENSA_CP0_SA_SIZE +#if XCHAL_CP0_SA_SIZE bbci.l a2, 0, 2f /* CP 0 not enabled */ l32i a14, a13, 0 /* a14 = _xtensa_coproc_saoffsets[0] */ add a3, a14, a15 /* a3 = save area for CP 0 */ @@ -244,7 +246,7 @@ _xtensa_coproc_restorestate: 2: #endif -#if XTENSA_CP1_SA_SIZE +#if XCHAL_CP1_SA_SIZE bbci.l a2, 1, 2f /* CP 1 not enabled */ l32i a14, a13, 4 /* a14 = _xtensa_coproc_saoffsets[1] */ add a3, a14, a15 /* a3 = save area for CP 1 */ @@ -252,7 +254,7 @@ _xtensa_coproc_restorestate: 2: #endif -#if XTENSA_CP2_SA_SIZE +#if XCHAL_CP2_SA_SIZE bbci.l a2, 2, 2f l32i a14, a13, 8 add a3, a14, a15 @@ -260,7 +262,7 @@ _xtensa_coproc_restorestate: 2: #endif -#if XTENSA_CP3_SA_SIZE +#if XCHAL_CP3_SA_SIZE bbci.l a2, 3, 2f l32i a14, a13, 12 add a3, a14, a15 @@ -268,7 +270,7 @@ _xtensa_coproc_restorestate: 2: #endif -#if XTENSA_CP4_SA_SIZE +#if XCHAL_CP4_SA_SIZE bbci.l a2, 4, 2f l32i a14, a13, 16 add a3, a14, a15 @@ -276,7 +278,7 @@ _xtensa_coproc_restorestate: 2: #endif -#if XTENSA_CP5_SA_SIZE +#if XCHAL_CP5_SA_SIZE bbci.l a2, 5, 2f l32i a14, a13, 20 add a3, a14, a15 @@ -284,7 +286,7 @@ _xtensa_coproc_restorestate: 2: #endif -#if XTENSA_CP6_SA_SIZE +#if XCHAL_CP6_SA_SIZE bbci.l a2, 6, 2f l32i a14, a13, 24 add a3, a14, a15 @@ -292,7 +294,7 @@ _xtensa_coproc_restorestate: 2: #endif -#if XTENSA_CP7_SA_SIZE +#if XCHAL_CP7_SA_SIZE bbci.l a2, 7, 2f l32i a14, a13, 28 add a3, a14, a15 diff --git a/arch/xtensa/src/common/xtensa_cpsave.c b/arch/xtensa/src/common/xtensa_cpsave.c index 7a128c6aa1..bd4a50ffdf 100644 --- a/arch/xtensa/src/common/xtensa_cpsave.c +++ b/arch/xtensa/src/common/xtensa_cpsave.c @@ -40,6 +40,8 @@ #include #include +#include + #include #include @@ -81,16 +83,16 @@ void xtensa_coproc_savestate(struct tcb_s *tcb) { - uint32_t cpsave = (uint32_t)((uintptr_t)&tcp->xcp.cpsave); + uint32_t cpstate = (uint32_t)((uintptr_t)&tcb->xcp.cpstate); __asm__ __volatile__ ( "mov a2, %0\n" "call0 _xtensa_coproc_savestate\n" : - : "r" (cpsave) + : "r" (cpstate) : "a0", "a2", "a3", "a4", "a5", "a6", "a7", "a13", "a14", "a15" - ) + ); } /**************************************************************************** @@ -122,17 +124,16 @@ void xtensa_coproc_savestate(struct tcb_s *tcb) void xtensa_coproc_restorestate(struct tcb_s *tcb) { - uint32_t cpsave = (uint32_t)((uintptr_t)&tcp->xcp.cpsave); + uint32_t cpstate = (uint32_t)((uintptr_t)&tcb->xcp.cpstate); __asm__ __volatile__ ( "mov a2, %0\n" - "mov a3, %1\n" "call0 _xtensa_coproc_restorestate\n" : - : "r" (cpmask) "r" (cpsave) + : "r" (cpstate) : "a0", "a2", "a3", "a4", "a5", "a6", "a7", "a13", "a14", "a15" - ) + ); } /**************************************************************************** @@ -177,13 +178,13 @@ void xtensa_coproc_enable(struct xtensa_cpstate_s *cpstate, int cpset) cpenable = xtensa_get_cpenable(); cpenable |= cpset; - xtensa_put_cpenable(cpenable); + xtensa_set_cpenable(cpenable); cpstate->cpenable = cpenable; - cpsates->cpstored &= ~cpset; + cpstate->cpstored &= ~cpset; } - leave_critical_section(); + leave_critical_section(flags); } /**************************************************************************** @@ -228,13 +229,13 @@ void xtensa_coproc_disable(struct xtensa_cpstate_s *cpstate, int cpset) cpenable = xtensa_get_cpenable(); cpenable &= ~cpset; - xtensa_put_cpenable(cpenable); + xtensa_set_cpenable(cpenable); cpstate->cpenable = cpenable; - cpsates->cpstored &= ~cpset; + cpstate->cpstored &= ~cpset; } - leave_critical_section(); + leave_critical_section(flags); } diff --git a/arch/xtensa/src/common/xtensa_createstack.c b/arch/xtensa/src/common/xtensa_createstack.c index 000f0dd990..c25d64cfa4 100644 --- a/arch/xtensa/src/common/xtensa_createstack.c +++ b/arch/xtensa/src/common/xtensa_createstack.c @@ -49,6 +49,7 @@ #include #include +#include #include #include "xtensa.h" @@ -115,9 +116,8 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) { #if XCHAL_CP_NUM > 0 + struct xcptcontext *xcp; uintptr_t cpstart; - uintptr_t cpend; - size_t cpsize; #endif /* Is there already a stack allocated of a different size? Because of @@ -208,11 +208,13 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) * memory rather than using the stack. */ - cpstart = (uintptr_t)_CP_ALIGNDOWN(top_of_stack - XCHAL_CP1_SA_ALIGN); + cpstart = (uintptr_t)_CP_ALIGNDOWN(XCHAL_CP0_SA_ALIGN, + top_of_stack - XCHAL_CP1_SA_ALIGN); top_of_stack = cpstart; /* Initialize the coprocessor save area (see xtensa_coproc.h) */ + xcp = &tcb->xcp; xcp->cpstate.cpenable = 0; /* No coprocessors active for this thread */ xcp->cpstate.cpstored = 0; /* No coprocessors saved for this thread */ xcp->cpstate.cpasa = (uint32_t *)cpstart; /* Start of aligned save area */ diff --git a/arch/xtensa/src/common/xtensa_initialstate.c b/arch/xtensa/src/common/xtensa_initialstate.c index 8fc10a6d03..d2b0744460 100644 --- a/arch/xtensa/src/common/xtensa_initialstate.c +++ b/arch/xtensa/src/common/xtensa_initialstate.c @@ -48,6 +48,7 @@ #include #include #include +#include #include "xtensa.h" @@ -100,7 +101,7 @@ void up_initial_state(struct tcb_s *tcb) * starts (see xtensa_coproc.h) */ - xcp->cpstate.cpenable = CONFIG_XTENSA_CP_INITSET; + xcp->cpstate.cpenable = (CONFIG_XTENSA_CP_INITSET & XTENSA_CP_ALLSET); xcp->cpstate.cpstored = 0; /* No coprocessors haved statee saved for this thread */ #endif } diff --git a/arch/xtensa/src/common/xtensa_irqdispatch.c b/arch/xtensa/src/common/xtensa_irqdispatch.c index d509f83e42..67192e0634 100644 --- a/arch/xtensa/src/common/xtensa_irqdispatch.c +++ b/arch/xtensa/src/common/xtensa_irqdispatch.c @@ -51,6 +51,7 @@ #include "xtensa.h" #include "group/group.h" +#include "sched/sched.h" /**************************************************************************** * Public Functions diff --git a/arch/xtensa/src/esp32/esp32_intdecode.c b/arch/xtensa/src/esp32/esp32_intdecode.c index d75cf08914..675c5327e6 100644 --- a/arch/xtensa/src/esp32/esp32_intdecode.c +++ b/arch/xtensa/src/esp32/esp32_intdecode.c @@ -39,6 +39,7 @@ #include +#include #include #include "chip/esp32_dport.h" diff --git a/configs/esp32-core/nsh/defconfig b/configs/esp32-core/nsh/defconfig index 4d8658e0e3..b163053233 100644 --- a/configs/esp32-core/nsh/defconfig +++ b/configs/esp32-core/nsh/defconfig @@ -77,6 +77,7 @@ CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_FAMILY_LX6=y CONFIG_XTENSA_CALL0_ABI=y # CONFIG_XTENSA_USE_OVLY is not set +CONFIG_XTENSA_CP_INITSET=0x0001 CONFIG_ESP32_UART=y # CONFIG_ESP32_SPI2 is not set # CONFIG_XTENSA_TIMER1 is not set -- GitLab From 804f9c5de773a12a8e914584eb2c55af080c83e3 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 29 Oct 2016 11:24:02 -0600 Subject: [PATCH 256/734] Xtensa: Rename some files. --- .../common/{xtensa_inthandlers.S => xtensa_int_handlers.S} | 4 ++-- .../src/common/{xtensa_nmihandler.S => xtensa_nmi_handler.S} | 4 ++-- arch/xtensa/src/esp32/Make.defs | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) rename arch/xtensa/src/common/{xtensa_inthandlers.S => xtensa_int_handlers.S} (99%) rename arch/xtensa/src/common/{xtensa_nmihandler.S => xtensa_nmi_handler.S} (98%) diff --git a/arch/xtensa/src/common/xtensa_inthandlers.S b/arch/xtensa/src/common/xtensa_int_handlers.S similarity index 99% rename from arch/xtensa/src/common/xtensa_inthandlers.S rename to arch/xtensa/src/common/xtensa_int_handlers.S index cc34881b78..fd59b6c662 100644 --- a/arch/xtensa/src/common/xtensa_inthandlers.S +++ b/arch/xtensa/src/common/xtensa_int_handlers.S @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/common/xtensa_inthandlers.S + * arch/xtensa/src/common/xtensa_int_handlers.S * * Adapted from use in NuttX by: * @@ -30,7 +30,7 @@ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ****************************************************************************/ - .file "xtensa_inthandlers.S" + .file "xtensa_int_handlers.S" /* NOTES on the use of 'call0' for long jumps instead of 'j': * diff --git a/arch/xtensa/src/common/xtensa_nmihandler.S b/arch/xtensa/src/common/xtensa_nmi_handler.S similarity index 98% rename from arch/xtensa/src/common/xtensa_nmihandler.S rename to arch/xtensa/src/common/xtensa_nmi_handler.S index 7f10b2ae6a..9f2e08ff9f 100644 --- a/arch/xtensa/src/common/xtensa_nmihandler.S +++ b/arch/xtensa/src/common/xtensa_nmi_handler.S @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/common/xtensa_nmihandler.S + * arch/xtensa/src/common/xtensa_nmi_handler.S * * Adapted from use in NuttX by: * @@ -30,7 +30,7 @@ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ****************************************************************************/ - .file "xtensa_nmihandler.S" + .file "xtensa_nmi_handler.S" /* NOTES on the use of 'call0' for long jumps instead of 'j': * diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index e14655286d..6e1c44113f 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -41,7 +41,7 @@ HEAD_CSRC = esp32_start.c # Common XTENSA files (arch/xtensa/src/common) CMN_ASRCS = xtensa_context.S xtensa_coproc.S xtensa_cpuint.S -CMN_ASRCS += xtensa_inthandlers.S xtensa_nmihandler.S xtensa_vectors.S +CMN_ASRCS += xtensa_int_handlers.S xtensa_nmi_handler.S xtensa_vectors.S CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c CMN_CSRCS += xtensa_cpsave.c xtensa_createstack.c xtensa_exit.c xtensa_idle.c -- GitLab From c993a0267cc4ba643438880f6fa8edc60a354451 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 29 Oct 2016 12:30:24 -0600 Subject: [PATCH 257/734] Xtensa: Add Window vector --- arch/xtensa/src/common/xtensa_abi.h | 114 +++++++ arch/xtensa/src/common/xtensa_window_vector.S | 279 ++++++++++++++++++ configs/esp32-core/scripts/esp32_common.ld | 2 +- 3 files changed, 394 insertions(+), 1 deletion(-) create mode 100644 arch/xtensa/src/common/xtensa_abi.h create mode 100644 arch/xtensa/src/common/xtensa_window_vector.S diff --git a/arch/xtensa/src/common/xtensa_abi.h b/arch/xtensa/src/common/xtensa_abi.h new file mode 100644 index 0000000000..e4c0878c15 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_abi.h @@ -0,0 +1,114 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_cpuint.S + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * + * Copyright (c) 2006-2015 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_ABI_H +#define __ARCH_XTENSA_SRC_COMMON_XTENSA_ABI_H 1 + +/* Windowed ABI + * + * Windowed Register Usage + * Callee Register Usage + * Register Name + * a0 Return address + * a1/sp Stack pointer + * a2..a7 In, out, inout, and return values + * + * Calls to routines that use only a2..a3 as parameters may use the CALL4, + * CALL8, or CALL12 instructions to save 4, 8, or 12 live registers. Calls + * to routines that use a2..a7 for parameters may use only CALL8 or CALL12. + * + * Call 0 ABI + * + * CALL0 AR Register Usage + * Callee Register Usage + * Register Name + * a0 Return Address + * a1/sp Stack pointer + * a2..a7 In, out, inout, and return values + * a8 Static Chain + * a12..a15 Callee-saved + * a15 Stack-Frame Pointer (optional) + * + * CALL0 is used. The return address is placed in A0 and the CPU simply + * jumps to the CALL0 function entry point. + */ + +/**************************************************************************** + * Pre-processor Defintions + ****************************************************************************/ + +/* MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN + * + * Convenient where the frame size requirements are the same for both ABIs. + * ENTRY(sz), RET(sz) are for framed functions (have locals or make calls). + * ENTRY0, RET0 are for frameless functions (no locals, no calls). + * + * where size = size of stack frame in bytes (must be >0 and aligned to 16). + * For framed functions the frame is created and the return address saved at + * base of frame (Call0 ABI) or as determined by hardware (Windowed ABI). + * For frameless functions, there is no frame and return address remains in a0. + * Note: Because CPP macros expand to a single line, macros requiring multi-line + * expansions are implemented as assembler macros. + */ + +#ifdef __ASSEMBLY__ +#ifdef CONFIG_XTENSA_CALL0_ABI + /* Call0 */ + + .macro entry1 size=0x10 + addi sp, sp, -\size + s32i a0, sp, 0 + .endm + + .macro ret1 size=0x10 + l32i a0, sp, 0 + addi sp, sp, \size + ret + .endm + +# define ENTRY(sz) entry1 sz +# define ENTRY0 +# define RET(sz) ret1 sz +# define RET0 ret + +#else + /* Windowed */ + +# define ENTRY(sz) entry sp, sz +# define ENTRY0 entry sp, 0x10 +# define RET(sz) retw +# define RET0 retw +#endif +#endif /* __ASSEMBLY_ */ + +#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_ABI_H */ diff --git a/arch/xtensa/src/common/xtensa_window_vector.S b/arch/xtensa/src/common/xtensa_window_vector.S new file mode 100644 index 0000000000..5b8314042e --- /dev/null +++ b/arch/xtensa/src/common/xtensa_window_vector.S @@ -0,0 +1,279 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_window_vector.S + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * + * Copyright (c) 2006-2015 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + + .file "xtensa_vectors.S" + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Window Vectors + ****************************************************************************/ + +/* WINDOW OVERFLOW AND UNDERFLOW EXCEPTION VECTORS AND ALLOCA EXCEPTION HANDLER + * + * Here is the code for each window overflow/underflow exception vector and + * (interspersed) efficient code for handling the alloca exception cause. + * Window exceptions are handled entirely in the vector area and are very + * tight for performance. The alloca exception is also handled entirely in + * the window vector area so comes at essentially no cost in code size. + * Users should never need to modify them and Cadence Design Systems recommends + * they do not. + * + * Window handlers go at predetermined vector locations according to the + * Xtensa hardware configuration, which is ensured by their placement in a + * special section known to the Xtensa linker support package (LSP). Since + * their offsets in that section are always the same, the LSPs do not define + * a section per vector. + * + * These things are coded for XEA2 only (XEA1 is not supported). + * + * Note on Underflow Handlers: + * The underflow handler for returning from call[i+1] to call[i] + * must preserve all the registers from call[i+1]'s window. + * In particular, a0 and a1 must be preserved because the RETW instruction + * will be reexecuted (and may even underflow if an intervening exception + * has flushed call[i]'s registers). + * Registers a2 and up may contain return values. + */ + +*******************************************************************************/ + +#if XCHAL_HAVE_WINDOWED + + .section .window_vectors.text, "ax" + +/* Window Overflow Exception for Call4. + * + * Invoked if a call[i] referenced a register (a4-a15) that contains data from + * ancestor call[j]; call[j] had done a call4 to call[j+1]. + * + * On entry here: + * window rotated to call[j] start point; + * a0-a3 are registers to be saved; + * a4-a15 must be preserved; + * a5 is call[j+1]'s stack pointer. + */ + + .org 0x0 + .global _window_overflow4 +_window_overflow4: + + s32e a0, a5, -16 /* save a0 to call[j+1]'s stack frame */ + s32e a1, a5, -12 /* save a1 to call[j+1]'s stack frame */ + s32e a2, a5, -8 /* save a2 to call[j+1]'s stack frame */ + s32e a3, a5, -4 /* save a3 to call[j+1]'s stack frame */ + rfwo /* rotates back to call[i] position */ + +/* Window Underflow Exception for Call4 + * + * Invoked by RETW returning from call[i+1] to call[i] where call[i]'s + * registers must be reloaded (not live in ARs); where call[i] had done a + * call4 to call[i+1]. + * + * On entry here: + * window rotated to call[i] start point; + * a0-a3 are undefined, must be reloaded with call[i].reg[0..3]; + * a4-a15 must be preserved (they are call[i+1].reg[0..11]); + * a5 is call[i+1]'s stack pointer. + */ + + .org 0x40 + .global _window_underflow4 +_window_underflow4: + + l32e a0, a5, -16 /* restore a0 from call[i+1]'s stack frame */ + l32e a1, a5, -12 /* restore a1 from call[i+1]'s stack frame */ + l32e a2, a5, -8 /* restore a2 from call[i+1]'s stack frame */ + l32e a3, a5, -4 /* restore a3 from call[i+1]'s stack frame */ + rfwu + +/* Handle alloca exception generated by interruptee executing 'movsp'. + * This uses space between the window vectors, so is essentially "free". + * All interruptee's regs are intact except a0 which is saved in EXCSAVE_1, + * and PS.EXCM has been set by the exception hardware (can't be interrupted). + * The fact the alloca exception was taken means the registers associated with + * the base-save area have been spilled and will be restored by the underflow + * handler, so those 4 registers are available for scratch. + * The code is optimized to avoid unaligned branches and minimize cache misses. + */ + + .align 4 + .global _xt_alloca_exc +_xt_alloca_exc: + + rsr a0, WINDOWBASE /* grab WINDOWBASE before rotw changes it */ + rotw -1 /* WINDOWBASE goes to a4, new a0-a3 are scratch */ + rsr a2, PS + extui a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS + xor a3, a3, a4 /* bits changed from old to current windowbase */ + rsr a4, EXCSAVE_1 /* restore original a0 (now in a4) */ + slli a3, a3, XCHAL_PS_OWB_SHIFT + xor a2, a2, a3 /* flip changed bits in old window base */ + wsr a2, PS /* update PS.OWB to new window base */ + rsync + + _bbci.l a4, 31, _window_underflow4 + rotw -1 /* original a0 goes to a8 */ + _bbci.l a8, 30, _window_underflow8 + rotw -1 + j _window_underflow12 + +/* Window Overflow Exception for Call8 + * + * Invoked if a call[i] referenced a register (a4-a15) that contains data from + * ancestor call[j]; call[j] had done a call8 to call[j+1]. + * + * On entry here: + * window rotated to call[j] start point; + * a0-a7 are registers to be saved; + * a8-a15 must be preserved; + * a9 is call[j+1]'s stack pointer. + */ + + .org 0x80 + .global _window_overflow8 +_window_overflow8: + + s32e a0, a9, -16 /* save a0 to call[j+1]'s stack frame */ + l32e a0, a1, -12 /* a0 <- call[j-1]'s sp + * (used to find end of call[j]'s frame) */ + s32e a1, a9, -12 /* save a1 to call[j+1]'s stack frame */ + s32e a2, a9, -8 /* save a2 to call[j+1]'s stack frame */ + s32e a3, a9, -4 /* save a3 to call[j+1]'s stack frame */ + s32e a4, a0, -32 /* save a4 to call[j]'s stack frame */ + s32e a5, a0, -28 /* save a5 to call[j]'s stack frame */ + s32e a6, a0, -24 /* save a6 to call[j]'s stack frame */ + s32e a7, a0, -20 /* save a7 to call[j]'s stack frame */ + rfwo /* rotates back to call[i] position */ + +/* Window Underflow Exception for Call8 + * + * Invoked by RETW returning from call[i+1] to call[i] where call[i]'s + * registers must be reloaded (not live in ARs); where call[i] had done a + * call8 to call[i+1]. + * + * On entry here: + * window rotated to call[i] start point; + * a0-a7 are undefined, must be reloaded with call[i].reg[0..7]; + * a8-a15 must be preserved (they are call[i+1].reg[0..7]); + * a9 is call[i+1]'s stack pointer. + */ + + .org 0xC0 + .global _window_underflow8 +_window_underflow8: + + l32e a0, a9, -16 /* restore a0 from call[i+1]'s stack frame */ + l32e a1, a9, -12 /* restore a1 from call[i+1]'s stack frame */ + l32e a2, a9, -8 /* restore a2 from call[i+1]'s stack frame */ + l32e a7, a1, -12 /* a7 <- call[i-1]'s sp + * (used to find end of call[i]'s frame) */ + l32e a3, a9, -4 /* restore a3 from call[i+1]'s stack frame */ + l32e a4, a7, -32 /* restore a4 from call[i]'s stack frame */ + l32e a5, a7, -28 /* restore a5 from call[i]'s stack frame */ + l32e a6, a7, -24 /* restore a6 from call[i]'s stack frame */ + l32e a7, a7, -20 /* restore a7 from call[i]'s stack frame */ + rfwu + +/* Window Overflow Exception for Call12 + * + * Invoked if a call[i] referenced a register (a4-a15) that contains data + * from ancestor call[j]; call[j] had done a call12 to call[j+1]. + * + * On entry here: + * window rotated to call[j] start point; + * a0-a11 are registers to be saved; + * a12-a15 must be preserved; + * a13 is call[j+1]'s stack pointer. + */ + + .org 0x100 + .global _window_overflow12 +_window_overflow12: + + s32e a0, a13, -16 /* save a0 to call[j+1]'s stack frame */ + l32e a0, a1, -12 /* a0 <- call[j-1]'s sp + * (used to find end of call[j]'s frame) */ + s32e a1, a13, -12 /* save a1 to call[j+1]'s stack frame */ + s32e a2, a13, -8 /* save a2 to call[j+1]'s stack frame */ + s32e a3, a13, -4 /* save a3 to call[j+1]'s stack frame */ + s32e a4, a0, -48 /* save a4 to end of call[j]'s stack frame */ + s32e a5, a0, -44 /* save a5 to end of call[j]'s stack frame */ + s32e a6, a0, -40 /* save a6 to end of call[j]'s stack frame */ + s32e a7, a0, -36 /* save a7 to end of call[j]'s stack frame */ + s32e a8, a0, -32 /* save a8 to end of call[j]'s stack frame */ + s32e a9, a0, -28 /* save a9 to end of call[j]'s stack frame */ + s32e a10, a0, -24 /* save a10 to end of call[j]'s stack frame */ + s32e a11, a0, -20 /* save a11 to end of call[j]'s stack frame */ + rfwo /* rotates back to call[i] position */ + +/* Window Underflow Exception for Call12 + * + * Invoked by RETW returning from call[i+1] to call[i] where call[i]'s + * registers must be reloaded (not live in ARs); where call[i] had done a + * call12 to call[i+1]. + * + * On entry here: + * window rotated to call[i] start point; + * a0-a11 are undefined, must be reloaded with call[i].reg[0..11]; + * a12-a15 must be preserved (they are call[i+1].reg[0..3]); + * a13 is call[i+1]'s stack pointer. + */ + + .org 0x140 + .global _window_underflow12 +_window_underflow12: + + l32e a0, a13, -16 /* restore a0 from call[i+1]'s stack frame */ + l32e a1, a13, -12 /* restore a1 from call[i+1]'s stack frame */ + l32e a2, a13, -8 /* restore a2 from call[i+1]'s stack frame */ + l32e a11, a1, -12 /* a11 <- call[i-1]'s sp + * (used to find end of call[i]'s frame) */ + l32e a3, a13, -4 /* restore a3 from call[i+1]'s stack frame */ + l32e a4, a11, -48 /* restore a4 from end of call[i]'s stack frame */ + l32e a5, a11, -44 /* restore a5 from end of call[i]'s stack frame */ + l32e a6, a11, -40 /* restore a6 from end of call[i]'s stack frame */ + l32e a7, a11, -36 /* restore a7 from end of call[i]'s stack frame */ + l32e a8, a11, -32 /* restore a8 from end of call[i]'s stack frame */ + l32e a9, a11, -28 /* restore a9 from end of call[i]'s stack frame */ + l32e a10, a11, -24 /* restore a10 from end of call[i]'s stack frame */ + l32e a11, a11, -20 /* restore a11 from end of call[i]'s stack frame */ + rfwu + +#endif /* XCHAL_HAVE_WINDOWED */ diff --git a/configs/esp32-core/scripts/esp32_common.ld b/configs/esp32-core/scripts/esp32_common.ld index 540a4f4ad6..680c71a784 100644 --- a/configs/esp32-core/scripts/esp32_common.ld +++ b/configs/esp32-core/scripts/esp32_common.ld @@ -19,7 +19,7 @@ SECTIONS /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ . = 0x0; - KEEP(*(.WindowVectors.text)); + KEEP(*(.window_vectors.text)); . = 0x180; KEEP(*(.xtensa_level2_vector.text)); . = 0x1c0; -- GitLab From 4997ec7a1e3f7aad940e189eaaff0dbf754290ce Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 29 Oct 2016 14:56:07 -0600 Subject: [PATCH 258/734] ESP32 Core V2: Add an SMP configuration to support development (not yet usable). --- arch/xtensa/src/common/xtensa_testset.c | 5 +- arch/xtensa/src/esp32/esp32_cpustart.c | 11 +- configs/esp32-core/README.txt | 7 + configs/esp32-core/smp/Make.defs | 114 ++++ configs/esp32-core/smp/defconfig | 803 ++++++++++++++++++++++++ configs/esp32-core/smp/setenv.sh | 57 ++ sched/Kconfig | 2 +- 7 files changed, 992 insertions(+), 7 deletions(-) create mode 100644 configs/esp32-core/smp/Make.defs create mode 100644 configs/esp32-core/smp/defconfig create mode 100755 configs/esp32-core/smp/setenv.sh diff --git a/arch/xtensa/src/common/xtensa_testset.c b/arch/xtensa/src/common/xtensa_testset.c index b4b3baa0fb..8dd15fdec9 100644 --- a/arch/xtensa/src/common/xtensa_testset.c +++ b/arch/xtensa/src/common/xtensa_testset.c @@ -39,8 +39,7 @@ #include -#include - +#include #include #include "xtensa.h" @@ -139,3 +138,5 @@ spinlock_t up_testset(volatile FAR spinlock_t *lock) return (prev == SP_UNLOCKED) ? SP_UNLOCKED : SP_LOCKED; } + +#endif /* CONFIG_SPINLOCK */ diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c index b3c2e90c9c..5b17abb0f9 100644 --- a/arch/xtensa/src/esp32/esp32_cpustart.c +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -49,7 +49,9 @@ #include "sched/sched.h" #include "xtensa.h" +#include "chip/esp32_dport.h" #include "esp32_region.h" +#include "esp32_cpuint.h" #ifdef CONFIG_SMP @@ -60,7 +62,7 @@ void ets_set_appcpu_boot_addr(uint32_t); * Private Data ****************************************************************************/ -static bool g_appcpu_started; +static volatile bool g_appcpu_started; static sem_t g_appcpu_interlock; /**************************************************************************** @@ -207,14 +209,14 @@ int up_cpu_start(int cpu) /* Start CPU1 */ sinfo("Starting CPU%d\n", cpu); - sem_init(&g_appcpu_interlock, 0, 0) + sem_init(&g_appcpu_interlock, 0, 0); regval = getreg32(DPORT_APPCPU_CTRL_B_REG); regval |= DPORT_APPCPU_CLKGATE_EN; putreg32(regval, DPORT_APPCPU_CTRL_B_REG); regval = getreg32(DPORT_APPCPU_CTRL_C_REG); - regval ~= DPORT_APPCPU_RUNSTALL; + regval &= ~DPORT_APPCPU_RUNSTALL; putreg32(regval, DPORT_APPCPU_CTRL_C_REG); regval = getreg32(DPORT_APPCPU_CTRL_A_REG); @@ -231,7 +233,7 @@ int up_cpu_start(int cpu) /* And way for the initial task to run on CPU1 */ - while (!app_cpu_started) + while (!g_appcpu_started) { ret = sem_wait(&g_appcpu_interlock); if (ret < 0) @@ -241,6 +243,7 @@ int up_cpu_start(int cpu) } sem_destroy(&g_appcpu_interlock); + return OK; } } diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index 1f0ff0d717..f823864307 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -155,3 +155,10 @@ NOTES: Configures the NuttShell (nsh) located at apps/examples/nsh. NOTES: + + smp: + + Another NSH configuration, similar to nsh, but also enables + SMP operation. + + NOTES: diff --git a/configs/esp32-core/smp/Make.defs b/configs/esp32-core/smp/Make.defs new file mode 100644 index 0000000000..f8901d0f8b --- /dev/null +++ b/configs/esp32-core/smp/Make.defs @@ -0,0 +1,114 @@ +############################################################################ +# configs/esp32-core/nsh/Make.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/xtensa/src/lx6/Toolchain.defs + +LDSCRIPT1 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_out.ld +LDSCRIPT2 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_common.ld +LDSCRIPT3 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_rom.ld +LDSCRIPT4 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_peripherals.ld + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(LDSCRIPT1)}" + ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT2)}" + ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT3)}" + ARCHSCRIPT += -T "${shell cygpath -w $(LDSCRIPT4)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(LDSCRIPT1) -T$(LDSCRIPT2) -T$(LDSCRIPT3) -T$(LDSCRIPT4) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -mlongcalls -MMD -MP +ARCHCXXFLAGS = $(ARCHCFLAGS) -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +LDFLAGS += -nostartfiles -nodefaultlibs +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/esp32-core/smp/defconfig b/configs/esp32-core/smp/defconfig new file mode 100644 index 0000000000..104c7c89ba --- /dev/null +++ b/configs/esp32-core/smp/defconfig @@ -0,0 +1,803 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +# CONFIG_HOST_LINUX is not set +# CONFIG_HOST_OSX is not set +CONFIG_HOST_WINDOWS=y +# CONFIG_HOST_OTHER is not set +# CONFIG_WINDOWS_NATIVE is not set +CONFIG_WINDOWS_CYGWIN=y +# CONFIG_WINDOWS_MSYS is not set +# CONFIG_WINDOWS_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +# CONFIG_ARCH_HAVE_STACKCHECK is not set +# CONFIG_ARCH_HAVE_HEAPCHECK is not set +# CONFIG_DEBUG_SYMBOLS is not set +# CONFIG_ARCH_HAVE_CUSTOMOPT is not set +# CONFIG_DEBUG_NOOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +CONFIG_ARCH_XTENSA=y +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_CHIP="esp32" +# CONFIG_SERIAL_TERMIOS is not set +CONFIG_ARCH_CHIP_ESP32=y +CONFIG_ARCH_FAMILY_LX6=y +CONFIG_XTENSA_CALL0_ABI=y +# CONFIG_XTENSA_USE_OVLY is not set +CONFIG_XTENSA_CP_INITSET=0x0001 +CONFIG_ESP32_UART=y +# CONFIG_ESP32_SPI2 is not set +# CONFIG_XTENSA_TIMER1 is not set +# CONFIG_XTENSA_TIMER2 is not set +CONFIG_ESP32_UART0=y +# CONFIG_ESP32_UART1 is not set +# CONFIG_ESP32_UART2 is not set +CONFIG_ESP32_BT_RESERVE_DRAM=0 +CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0 +CONFIG_ESP32_ULP_COPROC_RESERVE_MEM=0 +# CONFIG_ESP32_GPIO_IRQ is not set +CONFIG_ESP32_UART0_TXPIN=0 +CONFIG_ESP32_UART0_RXPIN=0 + +# +# ESP32 Peripheral Selection +# + +# +# Memory Configuration +# + +# +# UART configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +# CONFIG_ARCH_HAVE_IRQPRIO is not set +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +CONFIG_ARCH_HAVE_MULTICPU=y +# CONFIG_ARCH_HAVE_VFORK is not set +# CONFIG_ARCH_HAVE_MMU is not set +# CONFIG_ARCH_HAVE_MPU is not set +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +# CONFIG_ARCH_HAVE_RESET is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +# CONFIG_ARCH_HAVE_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=16717 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +# CONFIG_ARCH_HAVE_INTERRUPTSTACK is not set +# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_SIZE=114688 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_ESP32CORE=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="esp32-core" + +# +# Common Board Options +# + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +# CONFIG_LIB_BOARDCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Clocks and Timers +# +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2011 +CONFIG_START_MONTH=12 +CONFIG_START_DAY=6 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_WDOG_INTRESERVE=4 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +CONFIG_SPINLOCK=y +CONFIG_SMP=y +CONFIG_SMP_NCPUS=2 +CONFIG_SMP_IDLETHREAD_STACKSIZE=2048 +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=31 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_HPWORK is not set +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +# CONFIG_ARCH_HAVE_I2CRESET is not set +# CONFIG_I2C is not set +CONFIG_SPI=y +# CONFIG_SPI_SLAVE is not set +CONFIG_SPI_EXCHANGE=y +# CONFIG_SPI_CMDDATA is not set +# CONFIG_SPI_CALLBACK is not set +# CONFIG_SPI_HWFEATURES is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set +# CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +CONFIG_UART0_SERIALDRIVER=y +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +CONFIG_UART0_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART0 Configuration +# +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 +# CONFIG_UART0_IFLOWCONTROL is not set +# CONFIG_UART0_OFLOWCONTROL is not set +# CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +CONFIG_FS_READABLE=y +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +CONFIG_FS_PROCFS=y +# CONFIG_FS_PROCFS_REGISTER is not set + +# +# Exclude individual procfs entries +# +# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set +# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=2 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +# CONFIG_ARCH_HAVE_TLS is not set +# CONFIG_LIBC_NETDB is not set +# CONFIG_NETDB_HOSTFILE is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +# CONFIG_CXX_NEWLONG is not set + +# +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_CCTYPE is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_CXXTEST is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +CONFIG_EXAMPLES_SMP=y +CONFIG_EXAMPLES_SMP_NBARRIER_THREADS=8 +CONFIG_EXAMPLES_SMP_PRIORITY=100 +CONFIG_EXAMPLES_SMP_STACKSIZE=2048 +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set +# CONFIG_FSUTILS_PASSWD is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_BAS is not set +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=64 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_NSH_MAXARGUMENTS=6 +# CONFIG_NSH_ARGCAT is not set +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_IFUPDOWN is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Configure Command Options +# +# CONFIG_NSH_CMDOPT_DF_H is not set +CONFIG_NSH_CODECS_BUFSIZE=128 +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_NSH_PROC_MOUNTPOINT="/proc" +CONFIG_NSH_FILEIOSIZE=512 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +# CONFIG_NSH_ARCHINIT is not set +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/esp32-core/smp/setenv.sh b/configs/esp32-core/smp/setenv.sh new file mode 100755 index 0000000000..3c57c18b55 --- /dev/null +++ b/configs/esp32-core/smp/setenv.sh @@ -0,0 +1,57 @@ +#!/bin/bash +# configs/esp32-core/nsh/setenv.sh +# +# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the path to the location where I installed the Expressif crosstools-NG +# toolchaing +export TOOLCHAIN_BIN="/home/patacongo/projects/nuttx/crosstool-NG/builds/xtensa-esp32-elf/bin" + +# Add the path to the toolchain to the PATH variable +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/sched/Kconfig b/sched/Kconfig index b10d3e3caf..d06143d7d5 100644 --- a/sched/Kconfig +++ b/sched/Kconfig @@ -257,7 +257,7 @@ config SPINLOCK config SMP bool "Symmetric Multi-Processing (SMP)" default n - depends on ARCH_HAVE_MULTICPU && EXPERIMENTAL + depends on ARCH_HAVE_MULTICPU select SPINLOCK ---help--- Enables support for Symmetric Multi-Processing (SMP) on a multi-CPU -- GitLab From dc82fa81b8feadc94eb5e446caaf7f42dd2437c6 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 30 Oct 2016 07:09:24 -0600 Subject: [PATCH 259/734] Xtensa: Remove XTENSA_EXTRA_SA_SIZE. It is not used. --- arch/xtensa/src/common/xtensa_context.S | 57 ++------- arch/xtensa/src/common/xtensa_window_vector.S | 118 +++++++++--------- 2 files changed, 66 insertions(+), 109 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index 6d32fc92b3..0e163a475e 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -65,8 +65,7 @@ #include #include -#warning REVIST XTENSA_EXTRA_SA_SIZE is not yet provided -#define XTENSA_EXTRA_SA_SIZE 0 /* REMOVE ME */ +#include "xtensa_abi.h" /**************************************************************************** * Public Functions @@ -147,7 +146,7 @@ _xtensa_context_save: s32i a3, a2, (4 * REG_LCOUNT) #endif -#if XTENSA_EXTRA_SA_SIZE > 0 || !defined(CONFIG_XTENSA_CALL0_ABI) +#ifndef CONFIG_XTENSA_CALL0_ABI mov a9, a0 /* Preserve ret addr */ #endif @@ -185,28 +184,6 @@ _xtensa_context_save: l32i a9, sp, (4 * REG_TMP2) #endif -#if XTENSA_EXTRA_SA_SIZE > 0 - /* NOTE: Normally the xthal_save_extra_nw macro only affects address - * registers a2-a5. It is theoretically possible for Xtensa processor - * designers to write TIE that causes more address registers to be - * affected, but it is generally unlikely. If that ever happens, - * more registers need to be saved/restored around this macro invocation. - * Here we assume a9,12,13 are preserved. - * Future Xtensa tools releases might limit the regs that can be affected. - */ - - addi a2, a2, (4 * REG_EXTRA) /* Where to save it */ -#if XTENSA_EXTRA_SA_ALIGN > 16 - movi a3, -XTENSA_EXTRA_SA_ALIGN - and a2, a2, a3 /* Align dynamically >16 bytes */ -#endif - call0 xthal_save_extra_nw /* Destroys a0,2,3,4,5 */ -#endif - -#if XTENSA_EXTRA_SA_SIZE > 0 || !defined(CONFIG_XTENSA_CALL0_ABI) - mov a0, a9 /* Retrieve ret addr */ -#endif - ret .size _xtensa_context_save, . - _xtensa_context_save @@ -309,27 +286,6 @@ xtensa_context_save: _xtensa_context_restore: -#if XTENSA_EXTRA_SA_SIZE > 0 - /* NOTE: Normally the xthal_restore_extra_nw macro only affects address - * registers a2-a5. It is theoretically possible for Xtensa processor - * designers to write TIE that causes more address registers to be - * affected, but it is generally unlikely. If that ever happens, - * more registers need to be saved/restored around this macro invocation. - * Here we only assume a13 is preserved. - * Future Xtensa tools releases might limit the regs that can be affected. - */ - - mov a13, a0 /* Preserve ret addr */ - addi a2, a2, (4 * REG_EXTRA) /* Where to find it */ - -#if XTENSA_EXTRA_SA_ALIGN > 16 - movi a3, -XTENSA_EXTRA_SA_ALIGN - and a2, a2, a3 /* Align dynamically >16 bytes */ -#endif - call0 xthal_restore_extra_nw /* Destroys a0,2,3,4,5 */ - mov a0, a13 /* Retrieve ret addr */ -#endif - #ifdef XCHAL_HAVE_LOOPS l32i a2, a2, (4 * REG_LBEG) l32i a3, a2, (4 * REG_LEND) @@ -387,8 +343,10 @@ _xtensa_context_restore: * * This functions implements the moral equivalent of longjmp(). It is * called from user code (with interrupts disabled) to restor the current - * state of the running thread. This function always returns 1 because - * the saved value of A2 was set to 1 in xtensa_context_save(). + * state of the running thread. This function always appears to be a + * second return from xtensa_context_save except that that it returns the + * value 1 (because the saved value of A2 was set to 1 + * inxtensa_context_save()). * * The counterpart to this function is xtensa_context_save(). * @@ -398,7 +356,8 @@ _xtensa_context_restore: * * Exit conditions: * NOTE: That this function does NOT return to the caller but rather - * to a new threading context. + * to a new threading context. It is not necessary to save any of the + * caller's registers. * * Assumptions: * - Interrupts are disabled. diff --git a/arch/xtensa/src/common/xtensa_window_vector.S b/arch/xtensa/src/common/xtensa_window_vector.S index 5b8314042e..de68c2010e 100644 --- a/arch/xtensa/src/common/xtensa_window_vector.S +++ b/arch/xtensa/src/common/xtensa_window_vector.S @@ -72,8 +72,6 @@ * Registers a2 and up may contain return values. */ -*******************************************************************************/ - #if XCHAL_HAVE_WINDOWED .section .window_vectors.text, "ax" @@ -94,11 +92,11 @@ .global _window_overflow4 _window_overflow4: - s32e a0, a5, -16 /* save a0 to call[j+1]'s stack frame */ - s32e a1, a5, -12 /* save a1 to call[j+1]'s stack frame */ - s32e a2, a5, -8 /* save a2 to call[j+1]'s stack frame */ - s32e a3, a5, -4 /* save a3 to call[j+1]'s stack frame */ - rfwo /* rotates back to call[i] position */ + s32e a0, a5, -16 /* Save a0 to call[j+1]'s stack frame */ + s32e a1, a5, -12 /* Save a1 to call[j+1]'s stack frame */ + s32e a2, a5, -8 /* Save a2 to call[j+1]'s stack frame */ + s32e a3, a5, -4 /* Save a3 to call[j+1]'s stack frame */ + rfwo /* Rotates back to call[i] position */ /* Window Underflow Exception for Call4 * @@ -117,10 +115,10 @@ _window_overflow4: .global _window_underflow4 _window_underflow4: - l32e a0, a5, -16 /* restore a0 from call[i+1]'s stack frame */ - l32e a1, a5, -12 /* restore a1 from call[i+1]'s stack frame */ - l32e a2, a5, -8 /* restore a2 from call[i+1]'s stack frame */ - l32e a3, a5, -4 /* restore a3 from call[i+1]'s stack frame */ + l32e a0, a5, -16 /* Restore a0 from call[i+1]'s stack frame */ + l32e a1, a5, -12 /* Restore a1 from call[i+1]'s stack frame */ + l32e a2, a5, -8 /* Restore a2 from call[i+1]'s stack frame */ + l32e a3, a5, -4 /* Restore a3 from call[i+1]'s stack frame */ rfwu /* Handle alloca exception generated by interruptee executing 'movsp'. @@ -137,19 +135,19 @@ _window_underflow4: .global _xt_alloca_exc _xt_alloca_exc: - rsr a0, WINDOWBASE /* grab WINDOWBASE before rotw changes it */ + rsr a0, WINDOWBASE /* Grab WINDOWBASE before rotw changes it */ rotw -1 /* WINDOWBASE goes to a4, new a0-a3 are scratch */ rsr a2, PS extui a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS - xor a3, a3, a4 /* bits changed from old to current windowbase */ - rsr a4, EXCSAVE_1 /* restore original a0 (now in a4) */ + xor a3, a3, a4 /* Bits changed from old to current windowbase */ + rsr a4, EXCSAVE_1 /* Restore original a0 (now in a4) */ slli a3, a3, XCHAL_PS_OWB_SHIFT - xor a2, a2, a3 /* flip changed bits in old window base */ - wsr a2, PS /* update PS.OWB to new window base */ + xor a2, a2, a3 /* Flip changed bits in old window base */ + wsr a2, PS /* Update PS.OWB to new window base */ rsync _bbci.l a4, 31, _window_underflow4 - rotw -1 /* original a0 goes to a8 */ + rotw -1 /* Original a0 goes to a8 */ _bbci.l a8, 30, _window_underflow8 rotw -1 j _window_underflow12 @@ -170,17 +168,17 @@ _xt_alloca_exc: .global _window_overflow8 _window_overflow8: - s32e a0, a9, -16 /* save a0 to call[j+1]'s stack frame */ + s32e a0, a9, -16 /* Save a0 to call[j+1]'s stack frame */ l32e a0, a1, -12 /* a0 <- call[j-1]'s sp * (used to find end of call[j]'s frame) */ - s32e a1, a9, -12 /* save a1 to call[j+1]'s stack frame */ - s32e a2, a9, -8 /* save a2 to call[j+1]'s stack frame */ - s32e a3, a9, -4 /* save a3 to call[j+1]'s stack frame */ - s32e a4, a0, -32 /* save a4 to call[j]'s stack frame */ - s32e a5, a0, -28 /* save a5 to call[j]'s stack frame */ - s32e a6, a0, -24 /* save a6 to call[j]'s stack frame */ - s32e a7, a0, -20 /* save a7 to call[j]'s stack frame */ - rfwo /* rotates back to call[i] position */ + s32e a1, a9, -12 /* Save a1 to call[j+1]'s stack frame */ + s32e a2, a9, -8 /* Save a2 to call[j+1]'s stack frame */ + s32e a3, a9, -4 /* Save a3 to call[j+1]'s stack frame */ + s32e a4, a0, -32 /* Save a4 to call[j]'s stack frame */ + s32e a5, a0, -28 /* Save a5 to call[j]'s stack frame */ + s32e a6, a0, -24 /* Save a6 to call[j]'s stack frame */ + s32e a7, a0, -20 /* Save a7 to call[j]'s stack frame */ + rfwo /* Rotates back to call[i] position */ /* Window Underflow Exception for Call8 * @@ -199,16 +197,16 @@ _window_overflow8: .global _window_underflow8 _window_underflow8: - l32e a0, a9, -16 /* restore a0 from call[i+1]'s stack frame */ - l32e a1, a9, -12 /* restore a1 from call[i+1]'s stack frame */ - l32e a2, a9, -8 /* restore a2 from call[i+1]'s stack frame */ + l32e a0, a9, -16 /* Restore a0 from call[i+1]'s stack frame */ + l32e a1, a9, -12 /* Restore a1 from call[i+1]'s stack frame */ + l32e a2, a9, -8 /* Restore a2 from call[i+1]'s stack frame */ l32e a7, a1, -12 /* a7 <- call[i-1]'s sp * (used to find end of call[i]'s frame) */ - l32e a3, a9, -4 /* restore a3 from call[i+1]'s stack frame */ - l32e a4, a7, -32 /* restore a4 from call[i]'s stack frame */ - l32e a5, a7, -28 /* restore a5 from call[i]'s stack frame */ - l32e a6, a7, -24 /* restore a6 from call[i]'s stack frame */ - l32e a7, a7, -20 /* restore a7 from call[i]'s stack frame */ + l32e a3, a9, -4 /* Restore a3 from call[i+1]'s stack frame */ + l32e a4, a7, -32 /* Restore a4 from call[i]'s stack frame */ + l32e a5, a7, -28 /* Restore a5 from call[i]'s stack frame */ + l32e a6, a7, -24 /* Restore a6 from call[i]'s stack frame */ + l32e a7, a7, -20 /* Restore a7 from call[i]'s stack frame */ rfwu /* Window Overflow Exception for Call12 @@ -227,21 +225,21 @@ _window_underflow8: .global _window_overflow12 _window_overflow12: - s32e a0, a13, -16 /* save a0 to call[j+1]'s stack frame */ + s32e a0, a13, -16 /* Save a0 to call[j+1]'s stack frame */ l32e a0, a1, -12 /* a0 <- call[j-1]'s sp * (used to find end of call[j]'s frame) */ - s32e a1, a13, -12 /* save a1 to call[j+1]'s stack frame */ - s32e a2, a13, -8 /* save a2 to call[j+1]'s stack frame */ - s32e a3, a13, -4 /* save a3 to call[j+1]'s stack frame */ - s32e a4, a0, -48 /* save a4 to end of call[j]'s stack frame */ - s32e a5, a0, -44 /* save a5 to end of call[j]'s stack frame */ - s32e a6, a0, -40 /* save a6 to end of call[j]'s stack frame */ - s32e a7, a0, -36 /* save a7 to end of call[j]'s stack frame */ - s32e a8, a0, -32 /* save a8 to end of call[j]'s stack frame */ - s32e a9, a0, -28 /* save a9 to end of call[j]'s stack frame */ - s32e a10, a0, -24 /* save a10 to end of call[j]'s stack frame */ - s32e a11, a0, -20 /* save a11 to end of call[j]'s stack frame */ - rfwo /* rotates back to call[i] position */ + s32e a1, a13, -12 /* Save a1 to call[j+1]'s stack frame */ + s32e a2, a13, -8 /* Save a2 to call[j+1]'s stack frame */ + s32e a3, a13, -4 /* Save a3 to call[j+1]'s stack frame */ + s32e a4, a0, -48 /* Save a4 to end of call[j]'s stack frame */ + s32e a5, a0, -44 /* Save a5 to end of call[j]'s stack frame */ + s32e a6, a0, -40 /* Save a6 to end of call[j]'s stack frame */ + s32e a7, a0, -36 /* Save a7 to end of call[j]'s stack frame */ + s32e a8, a0, -32 /* Save a8 to end of call[j]'s stack frame */ + s32e a9, a0, -28 /* Save a9 to end of call[j]'s stack frame */ + s32e a10, a0, -24 /* Save a10 to end of call[j]'s stack frame */ + s32e a11, a0, -20 /* Save a11 to end of call[j]'s stack frame */ + rfwo /* Rotates back to call[i] position */ /* Window Underflow Exception for Call12 * @@ -260,20 +258,20 @@ _window_overflow12: .global _window_underflow12 _window_underflow12: - l32e a0, a13, -16 /* restore a0 from call[i+1]'s stack frame */ - l32e a1, a13, -12 /* restore a1 from call[i+1]'s stack frame */ - l32e a2, a13, -8 /* restore a2 from call[i+1]'s stack frame */ + l32e a0, a13, -16 /* Restore a0 from call[i+1]'s stack frame */ + l32e a1, a13, -12 /* Restore a1 from call[i+1]'s stack frame */ + l32e a2, a13, -8 /* Restore a2 from call[i+1]'s stack frame */ l32e a11, a1, -12 /* a11 <- call[i-1]'s sp - * (used to find end of call[i]'s frame) */ - l32e a3, a13, -4 /* restore a3 from call[i+1]'s stack frame */ - l32e a4, a11, -48 /* restore a4 from end of call[i]'s stack frame */ - l32e a5, a11, -44 /* restore a5 from end of call[i]'s stack frame */ - l32e a6, a11, -40 /* restore a6 from end of call[i]'s stack frame */ - l32e a7, a11, -36 /* restore a7 from end of call[i]'s stack frame */ - l32e a8, a11, -32 /* restore a8 from end of call[i]'s stack frame */ - l32e a9, a11, -28 /* restore a9 from end of call[i]'s stack frame */ - l32e a10, a11, -24 /* restore a10 from end of call[i]'s stack frame */ - l32e a11, a11, -20 /* restore a11 from end of call[i]'s stack frame */ + * (used to find end of call[i]'s frame) */ + l32e a3, a13, -4 /* Restore a3 from call[i+1]'s stack frame */ + l32e a4, a11, -48 /* Restore a4 from end of call[i]'s stack frame */ + l32e a5, a11, -44 /* Restore a5 from end of call[i]'s stack frame */ + l32e a6, a11, -40 /* Restore a6 from end of call[i]'s stack frame */ + l32e a7, a11, -36 /* Restore a7 from end of call[i]'s stack frame */ + l32e a8, a11, -32 /* Restore a8 from end of call[i]'s stack frame */ + l32e a9, a11, -28 /* Restore a9 from end of call[i]'s stack frame */ + l32e a10, a11, -24 /* Restore a10 from end of call[i]'s stack frame */ + l32e a11, a11, -20 /* Restore a11 from end of call[i]'s stack frame */ rfwu #endif /* XCHAL_HAVE_WINDOWED */ -- GitLab From 8c962210937fcd4e4c0baa0b6f95ce1439ed34cb Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 30 Oct 2016 07:37:51 -0600 Subject: [PATCH 260/734] Xtensa: Replace CONFIG_XTENSA_CALL0_ABI with compiler defined __XTENSA_CALL0_ABI__ --- arch/xtensa/Kconfig | 7 --- arch/xtensa/include/irq.h | 6 +- arch/xtensa/src/common/xtensa_abi.h | 60 +++++++++++++------ arch/xtensa/src/common/xtensa_context.S | 4 +- arch/xtensa/src/common/xtensa_dumpstate.c | 2 +- arch/xtensa/src/common/xtensa_initialstate.c | 2 +- arch/xtensa/src/common/xtensa_int_handlers.S | 6 +- arch/xtensa/src/common/xtensa_macros.h | 4 +- .../xtensa/src/common/xtensa_schedsigaction.c | 4 +- 9 files changed, 55 insertions(+), 40 deletions(-) diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 124cb96a99..71be453e17 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -31,13 +31,6 @@ config ARCH_FAMILY_LX6 Cadence® Tensilica® Xtensa® LX6 data plane processing unit (DPU). The LX6 is a configurable and extensible processor core. -config XTENSA_CALL0_ABI - bool - default y - ---help--- - The Window ABI is not supported. Only the CALL0 ABI is supported in the - current implementation. - config XTENSA_USE_OVLY bool default n diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index 1ee9721e38..0e8f7c33b0 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -113,7 +113,7 @@ # define _REG_CALL0_START _REG_LOOPS_START #endif -#ifndef CONFIG_XTENSA_CALL0_ABI +#ifndef __XTENSA_CALL0_ABI__ /* Temporary space for saving stuff during window spill */ # define REG_TMP0 (_REG_CALL0_START + 0) @@ -243,7 +243,7 @@ static inline uint32_t up_irq_save(void) static inline void up_irq_enable(void) { -#ifdef CONFIG_XTENSA_CALL0_ABI +#ifdef __XTENSA_CALL0_ABI__ xtensa_setps(PS_INTLEVEL(0) | PS_UM); #else xtensa_setps(PS_INTLEVEL(0) | PS_UM | PS_WOE); @@ -254,7 +254,7 @@ static inline void up_irq_enable(void) static inline void up_irq_disable(void) { -#ifdef CONFIG_XTENSA_CALL0_ABI +#ifdef __XTENSA_CALL0_ABI__ xtensa_setps(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM); #else xtensa_setps(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE); diff --git a/arch/xtensa/src/common/xtensa_abi.h b/arch/xtensa/src/common/xtensa_abi.h index e4c0878c15..6fa4456f83 100644 --- a/arch/xtensa/src/common/xtensa_abi.h +++ b/arch/xtensa/src/common/xtensa_abi.h @@ -36,31 +36,53 @@ /* Windowed ABI * - * Windowed Register Usage - * Callee Register Usage - * Register Name - * a0 Return address - * a1/sp Stack pointer - * a2..a7 In, out, inout, and return values + * The Windowed Register Option replaces the simple 16-entry AR register + * file with a larger register file from which a window of 16 entries is + * visible at any given time. The window is rotated on subroutine entry + * and exit, automatically saving and restoring some registers. When the + * window is rotated far enough to require registers to be saved to or + * restored from the program stack, an exception is raised to move some + * of the register values between the register file and the program stack. + * + * Windowed Register Usage: + * ---------------- ---------------------------------- + * Callee Register Usage + * Register Name + * ---------------- ---------------------------------- + * a0 Return address + * a1/sp Stack pointer + * a2..a7 In, out, inout, and return values + * ---------------- ---------------------------------- * * Calls to routines that use only a2..a3 as parameters may use the CALL4, * CALL8, or CALL12 instructions to save 4, 8, or 12 live registers. Calls * to routines that use a2..a7 for parameters may use only CALL8 or CALL12. * + * The stack pointer SP should only be modified by ENTRY and MOVSP + * instructions (except for initialization and restoration). If some other + * instruction modifies SP, any values in the register-spill area will not + * be moved. + * * Call 0 ABI * - * CALL0 AR Register Usage - * Callee Register Usage - * Register Name - * a0 Return Address - * a1/sp Stack pointer - * a2..a7 In, out, inout, and return values - * a8 Static Chain - * a12..a15 Callee-saved - * a15 Stack-Frame Pointer (optional) - * - * CALL0 is used. The return address is placed in A0 and the CPU simply - * jumps to the CALL0 function entry point. + * CALL0 AR Register Usage + * ---------------- ---------------------------------- + * Callee Register Usage + * Register Name + * ---------------- ---------------------------------- + * a0 Return Address + * a1/sp Stack pointer + * a2..a7 In, out, inout, and return values + * a8 Static Chain + * a12..a15 Callee-saved + * a15 Stack-Frame Pointer (optional) + * + * a0, a2-a11 Caller-saved + * a1, a12..a15 Callee-saved + * ---------------- ---------------------------------- + * + * CALL0 is used. The return address is placed in A0 and the CPU simply + * jumps to the CALL0 function entry point. */ /**************************************************************************** @@ -82,7 +104,7 @@ */ #ifdef __ASSEMBLY__ -#ifdef CONFIG_XTENSA_CALL0_ABI +#ifdef __XTENSA_CALL0_ABI__ /* Call0 */ .macro entry1 size=0x10 diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index 0e163a475e..a2e69bee5a 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -146,11 +146,11 @@ _xtensa_context_save: s32i a3, a2, (4 * REG_LCOUNT) #endif -#ifndef CONFIG_XTENSA_CALL0_ABI +#ifndef __XTENSA_CALL0_ABI__ mov a9, a0 /* Preserve ret addr */ #endif -#ifndef CONFIG_XTENSA_CALL0_ABI +#ifndef __XTENSA_CALL0_ABI__ /* To spill the reg windows, temp. need pre-interrupt stack ptr and * a4-15. Need to save a9,12,13 temporarily (in frame temps) and * recover originals. Interrupts need to be disabled below diff --git a/arch/xtensa/src/common/xtensa_dumpstate.c b/arch/xtensa/src/common/xtensa_dumpstate.c index f99f3d905c..b1afe927fc 100644 --- a/arch/xtensa/src/common/xtensa_dumpstate.c +++ b/arch/xtensa/src/common/xtensa_dumpstate.c @@ -123,7 +123,7 @@ static inline void xtensa_registerdump(void) (unsigned long)regs[REG_LBEG], (unsigned long)regs[REG_LEND], (unsigned long)regs[REG_LCOUNT]); #endif -#ifndef CONFIG_XTENSA_CALL0_ABI +#ifndef __XTENSA_CALL0_ABI__ _alert(" TMP0: %08lx TMP1: %08lx TMP2: %08lx\n", (unsigned long)regs[REG_TMP0], (unsigned long)regs[REG_TMP1], (unsigned long)regs[REG_TMP2]); diff --git a/arch/xtensa/src/common/xtensa_initialstate.c b/arch/xtensa/src/common/xtensa_initialstate.c index d2b0744460..fb74503ad5 100644 --- a/arch/xtensa/src/common/xtensa_initialstate.c +++ b/arch/xtensa/src/common/xtensa_initialstate.c @@ -87,7 +87,7 @@ void up_initial_state(struct tcb_s *tcb) * mode. */ -#ifdef CONFIG_XTENSA_CALL0_ABI +#ifdef __XTENSA_CALL0_ABI__ xcp->regs[REG_PS] = PS_UM | PS_EXCM; #else diff --git a/arch/xtensa/src/common/xtensa_int_handlers.S b/arch/xtensa/src/common/xtensa_int_handlers.S index fd59b6c662..9ecb529988 100644 --- a/arch/xtensa/src/common/xtensa_int_handlers.S +++ b/arch/xtensa/src/common/xtensa_int_handlers.S @@ -134,7 +134,7 @@ l32i a4, a4, \level << 2 beqz a4, 2f -#ifdef CONFIG_XTENSA_CALL0_ABI +#ifdef __XTENSA_CALL0_ABI__ callx0 a4 beqz a2, 5f #else @@ -221,7 +221,7 @@ .macro ps_setup level tmp #if 0 /* Nested interrupts no yet supported */ -# ifdef CONFIG_XTENSA_CALL0_ABI +# ifdef __XTENSA_CALL0_ABI__ /* Disable interrupts at level and below */ movi \tmp, PS_INTLEVEL(\level) | PS_UM @@ -229,7 +229,7 @@ movi \tmp, PS_INTLEVEL(\level) | PS_UM | PS_WOE # endif #else -# ifdef CONFIG_XTENSA_CALL0_ABI +# ifdef __XTENSA_CALL0_ABI__ /* Disable all low- and medium-priority interrupts. Nested are not yet * supported. */ diff --git a/arch/xtensa/src/common/xtensa_macros.h b/arch/xtensa/src/common/xtensa_macros.h index aabe43b848..9b88671207 100644 --- a/arch/xtensa/src/common/xtensa_macros.h +++ b/arch/xtensa/src/common/xtensa_macros.h @@ -59,7 +59,7 @@ * expansions are implemented as assembler macros. */ -#ifdef CONFIG_XTENSA_CALL0_ABI +#ifdef __XTENSA_CALL0_ABI__ /* Call0 */ .macro entry1 size=0x10 @@ -86,7 +86,7 @@ # define RET(sz) retw # define RET0 retw -#endif /* CONFIG_XTENSA_CALL0_ABI */ +#endif /* __XTENSA_CALL0_ABI__ */ #endif /* __ASSEMBLY */ #endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_MACROS_H */ diff --git a/arch/xtensa/src/common/xtensa_schedsigaction.c b/arch/xtensa/src/common/xtensa_schedsigaction.c index 8090bb262d..438f712768 100644 --- a/arch/xtensa/src/common/xtensa_schedsigaction.c +++ b/arch/xtensa/src/common/xtensa_schedsigaction.c @@ -151,7 +151,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) */ CURRENT_REGS[REG_PC] = (uint32_t)xtensa_sigdeliver; -#ifdef CONFIG_XTENSA_CALL0_ABI +#ifdef __XTENSA_CALL0_ABI__ CURRENT_REGS[REG_PS] = (uint32_t)(PS_INTLEVEL(0) | PS_UM); #else CURRENT_REGS[REG_PS] = (uint32_t)(PS_INTLEVEL(0) | PS_UM | PS_WOE); @@ -186,7 +186,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) */ tcb->xcp.regs[REG_PC] = (uint32_t)xtensa_sigdeliver; -#ifdef CONFIG_XTENSA_CALL0_ABI +#ifdef __XTENSA_CALL0_ABI__ tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(0) | PS_UM); #else tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(0) | PS_UM | PS_WOE); -- GitLab From c0da94fc3e6236d0a3fe7e6dfe7e4ea6485e5e02 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 30 Oct 2016 07:45:28 -0600 Subject: [PATCH 261/734] Xtensa: Remove xtensa_macros.h; duplicates xtensa_abi.h --- arch/xtensa/src/common/xtensa_int_handlers.S | 2 +- arch/xtensa/src/common/xtensa_macros.h | 92 -------------------- arch/xtensa/src/common/xtensa_nmi_handler.S | 2 +- arch/xtensa/src/common/xtensa_vectors.S | 2 +- 4 files changed, 3 insertions(+), 95 deletions(-) delete mode 100644 arch/xtensa/src/common/xtensa_macros.h diff --git a/arch/xtensa/src/common/xtensa_int_handlers.S b/arch/xtensa/src/common/xtensa_int_handlers.S index 9ecb529988..7796ab0594 100644 --- a/arch/xtensa/src/common/xtensa_int_handlers.S +++ b/arch/xtensa/src/common/xtensa_int_handlers.S @@ -63,7 +63,7 @@ #include #include -#include "xtensa_macros.h" +#include "xtensa_abi.h" #include "chip_macros.h" #include "xtensa_timer.h" diff --git a/arch/xtensa/src/common/xtensa_macros.h b/arch/xtensa/src/common/xtensa_macros.h deleted file mode 100644 index 9b88671207..0000000000 --- a/arch/xtensa/src/common/xtensa_macros.h +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/common/xtensa_macros.h - * - * Adapted from use in NuttX by: - * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Derives from logic originally provided by Cadence Design Systems Inc. - * - * Copyright (c) 2006-2015 Cadence Design Systems Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_MACROS_H -#define __ARCH_XTENSA_SRC_COMMON_XTENSA_MACROS_H 1 - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip_macros.h" - -/**************************************************************************** - * Assembly Language Macros - ****************************************************************************/ - -#ifdef __ASSEMBLY__ -/* Macros to handle ABI specifics of function entry and return. - * - * Convenient where the frame size requirements are the same for both ABIs. - * ENTRY(sz), RET(sz) are for framed functions (have locals or make calls). - * ENTRY0, RET0 are for frameless functions (no locals, no calls). - * - * where size = size of stack frame in bytes (must be >0 and aligned to 16). - * For framed functions the frame is created and the return address saved at - * base of frame (Call0 ABI) or as determined by hardware (Windowed ABI). - * For frameless functions, there is no frame and return address remains in a0. - * Note: Because CPP macros expand to a single line, macros requiring multi-line - * expansions are implemented as assembler macros. - */ - -#ifdef __XTENSA_CALL0_ABI__ - /* Call0 */ - - .macro entry1 size=0x10 - addi sp, sp, -\size - s32i a0, sp, 0 - .endm - - .macro ret1 size=0x10 - l32i a0, sp, 0 - addi sp, sp, \size - ret - .endm - -# define ENTRY(sz) entry1 sz -# define ENTRY0 -# define RET(sz) ret1 sz -# define RET0 ret - -#else - /* Windowed */ - -# define ENTRY(sz) entry sp, sz -# define ENTRY0 entry sp, 0x10 -# define RET(sz) retw -# define RET0 retw - -#endif /* __XTENSA_CALL0_ABI__ */ - -#endif /* __ASSEMBLY */ -#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_MACROS_H */ diff --git a/arch/xtensa/src/common/xtensa_nmi_handler.S b/arch/xtensa/src/common/xtensa_nmi_handler.S index 9f2e08ff9f..67510aa41c 100644 --- a/arch/xtensa/src/common/xtensa_nmi_handler.S +++ b/arch/xtensa/src/common/xtensa_nmi_handler.S @@ -63,7 +63,7 @@ #include #include "chip_macros.h" -#include "xtensa_macros.h" +#include "xtensa_abi.h" /**************************************************************************** * Assembly Language Macros diff --git a/arch/xtensa/src/common/xtensa_vectors.S b/arch/xtensa/src/common/xtensa_vectors.S index a9b440e770..6f84444aeb 100644 --- a/arch/xtensa/src/common/xtensa_vectors.S +++ b/arch/xtensa/src/common/xtensa_vectors.S @@ -41,7 +41,7 @@ #include #include -#include "xtensa_macros.h" +#include "xtensa_abi.h" /**************************************************************************** * Public Functions -- GitLab From 261e0edc61e23feed2291aa31d3c2e9378e47c2e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 30 Oct 2016 08:35:09 -0600 Subject: [PATCH 262/734] Xtensa: Adapt co-processor state save/restore functions so that they are call-able from C with Windows ABI. --- arch/xtensa/src/common/xtensa.h | 5 +- arch/xtensa/src/common/xtensa_abi.h | 8 + arch/xtensa/src/common/xtensa_blocktask.c | 4 +- arch/xtensa/src/common/xtensa_coproc.S | 151 +++++++++++++++++- .../{xtensa_cpsave.c => xtensa_cpenable.c} | 86 +--------- arch/xtensa/src/common/xtensa_exit.c | 2 +- arch/xtensa/src/common/xtensa_irqdispatch.c | 4 +- .../xtensa/src/common/xtensa_releasepending.c | 4 +- .../src/common/xtensa_reprioritizertr.c | 4 +- .../xtensa/src/common/xtensa_schedsigaction.c | 8 +- arch/xtensa/src/common/xtensa_unblocktask.c | 4 +- arch/xtensa/src/esp32/Make.defs | 2 +- 12 files changed, 176 insertions(+), 106 deletions(-) rename arch/xtensa/src/common/{xtensa_cpsave.c => xtensa_cpenable.c} (66%) diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index fb1ba85dd6..d6af111d04 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -260,9 +260,8 @@ int xtensa_context_save(uint32_t *regs); void xtensa_context_restore(uint32_t *regs) noreturn_function; #if XCHAL_CP_NUM > 0 -struct tcb_s; -void xtensa_coproc_savestate(struct tcb_s *tcb); -void xtensa_coproc_restorestate(struct tcb_s *tcb); +void xtensa_coproc_savestate(struct xtensa_cpstate_s *cpstate); +void xtensa_coproc_restorestate(struct xtensa_cpstate_s *cpstate); #endif /* Signals */ diff --git a/arch/xtensa/src/common/xtensa_abi.h b/arch/xtensa/src/common/xtensa_abi.h index 6fa4456f83..63e53f26c5 100644 --- a/arch/xtensa/src/common/xtensa_abi.h +++ b/arch/xtensa/src/common/xtensa_abi.h @@ -104,6 +104,8 @@ */ #ifdef __ASSEMBLY__ +/* Function prologues and epilogues */ + #ifdef __XTENSA_CALL0_ABI__ /* Call0 */ @@ -130,7 +132,13 @@ # define ENTRY0 entry sp, 0x10 # define RET(sz) retw # define RET0 retw + #endif + +/* Index into stack frame (skipping over saved A0) */ + +#define LOCAL_OFFSET(n) ((n) << 2) /* n = 1 .. ((size >> 2) - 1) */ + #endif /* __ASSEMBLY_ */ #endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_ABI_H */ diff --git a/arch/xtensa/src/common/xtensa_blocktask.c b/arch/xtensa/src/common/xtensa_blocktask.c index d2fb62bf48..fb1c0f910b 100644 --- a/arch/xtensa/src/common/xtensa_blocktask.c +++ b/arch/xtensa/src/common/xtensa_blocktask.c @@ -154,7 +154,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) * processor save area. */ - xtensa_coproc_savestate(rtcb); + xtensa_coproc_savestate(&rtcb->xcp.cpstate); #endif /* Restore the exception context of the rtcb at the (new) head @@ -166,7 +166,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state) #if XCHAL_CP_NUM > 0 /* Set up the co-processor state for the newly started thread. */ - xtensa_coproc_restorestate(rtcb); + xtensa_coproc_restorestate(&rtcb->xcp.cpstate); #endif #ifdef CONFIG_ARCH_ADDRENV diff --git a/arch/xtensa/src/common/xtensa_coproc.S b/arch/xtensa/src/common/xtensa_coproc.S index 2445eaecf3..2bcba0185f 100644 --- a/arch/xtensa/src/common/xtensa_coproc.S +++ b/arch/xtensa/src/common/xtensa_coproc.S @@ -46,6 +46,8 @@ #include #include +#include "xtensa_abi.h" + #if XCHAL_CP_NUM > 0 /**************************************************************************** @@ -87,7 +89,7 @@ _xtensa_coproc_saoffsets: * around the assembly language call to _xtensa_coproc_savestate. * * Entry Conditions: - * - A2 holds the address of the threads state save area + * - A2 holds the address of the co-processor state save area * - The thread being switched out is still the current thread. * - CPENABLE state reflects which coprocessors are active. * - Registers have been saved/spilled already. @@ -191,6 +193,79 @@ _xtensa_coproc_savestate: .size _xtensa_coproc_savestate, . - _xtensa_coproc_savestate +/**************************************************************************** + * Name: xtensa_coproc_savestate + * + * Description: + * If there is a current thread and it has a coprocessor state save area, + * then save all callee-saved state into this area. xtensa_coproc_savestate() + * is simply a C wrapper around the assembly language call to + * _xtensa_coproc_savestate. + * + * Input Parameters: + * A2 - Address of co-processor save area + * + * Returned Value: + * None + * + * Assumptions: + * Called with interrupts disabled. + * + ****************************************************************************/ + + .global xtensa_coproc_savestate + .type xtensa_coproc_savestate, @function + + .align 4 + .literal_position + .align 4 + +xtensa_coproc_savestate: + +#ifdef __XTENSA_CALL0_ABI__ + + /* Need to preserve a8-11. _xtensa_coproc_savestate modifies a2-a7, + * a13-a15. So no registers need be saved. + */ + + ENTRY(16) + + /* Call _xtensa_coproc_savestate() with A2=address of co-processor + * save area. + */ + + call0 _xtensa_coproc_savestate + RET(16) + +#else + + /* Need to preserve a8-15. _xtensa_coproc_savestate modifies a2-a7, + * a13-a15. So only a13-a15 need be preserved. + */ + + ENTRY(16) + s32i a13, sp, LOCAL_OFFSET(1) + s32i a14, sp, LOCAL_OFFSET(2) + s32i a15, sp, LOCAL_OFFSET(3) + + /* Call _xtensa_coproc_savestate() with A2=address of co-processor + * save area. + */ + + call0 _xtensa_coproc_savestate + + /* Restore a13-15 and return */ + + 132i a13, sp, LOCAL_OFFSET(1) + 132i a14, sp, LOCAL_OFFSET(2) + 132i a15, sp, LOCAL_OFFSET(3) + + RET(16) + +#endif + + .size xtensa_coproc_savestate, . - xtensa_coproc_savestate + /**************************************************************************** * Name: _xtensa_coproc_restorestate * @@ -206,7 +281,7 @@ _xtensa_coproc_savestate: * around the assembly language call to _xtensa_coproc_restorestate. * * Entry Conditions: - * - A2 holds the address of the threads state save area + * - A2 holds the address of the co-processor state save area * - The incoming thread is set as the current thread. * - CPENABLE is set up correctly for all required coprocessors. * @@ -306,4 +381,76 @@ _xtensa_coproc_restorestate: .size _xtensa_coproc_restorestate, . - _xtensa_coproc_restorestate +/**************************************************************************** + * Name: xtensa_coproc_restorestate + * + * Description: + * Restore any callee-saved coprocessor state for the incoming thread. + * xtensa_coproc_restorestate() is simply a C wrapper around the assembly + * language call to _xtensa_coproc_restorestate. + * + * Input Parameters: + * - A2 holds the address of the threads state save area + * + * Returned Value: + * None + * + * Assumptions: + * Called with interrupts disabled. + * + ****************************************************************************/ + + .global xtensa_coproc_restorestate + .type xtensa_coproc_restorestate, @function + + .align 4 + .literal_position + .align 4 + +xtensa_coproc_restorestate: + +#ifdef __XTENSA_CALL0_ABI__ + + /* Need to preserve a8-11. _xtensa_coproc_restorestate modifies a2-a7, + * a13-a15. So no registers need be saved. + */ + + ENTRY(16) + + /* Call _xtensa_coproc_restorestate() with A2=address of co-processor + * save area. + */ + + call0 _xtensa_coproc_restorestate + RET(16) + +#else + + /* Need to preserve a8-15. _xtensa_coproc_savestate modifies a2-a7, + * a13-a15. So only a13-a15 need be preserved. + */ + + ENTRY(16) + s32i a13, sp, LOCAL_OFFSET(1) + s32i a14, sp, LOCAL_OFFSET(2) + s32i a15, sp, LOCAL_OFFSET(3) + + /* Call _xtensa_coproc_restorestate() with A2=address of co-processor + * save area. + */ + + call0 _xtensa_coproc_restorestate + + /* Restore a13-15 and return */ + + 132i a13, sp, LOCAL_OFFSET(1) + 132i a14, sp, LOCAL_OFFSET(2) + 132i a15, sp, LOCAL_OFFSET(3) + + RET(16) + +#endif + + .size xtensa_coproc_restorestate, . - xtensa_coproc_restorestate + #endif /* XCHAL_CP_NUM > 0 */ diff --git a/arch/xtensa/src/common/xtensa_cpsave.c b/arch/xtensa/src/common/xtensa_cpenable.c similarity index 66% rename from arch/xtensa/src/common/xtensa_cpsave.c rename to arch/xtensa/src/common/xtensa_cpenable.c index bd4a50ffdf..894cb028bc 100644 --- a/arch/xtensa/src/common/xtensa_cpsave.c +++ b/arch/xtensa/src/common/xtensa_cpenable.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/common/xtensa_cpsave.c + * arch/xtensa/src/common/xtensa_cpenable.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -53,89 +53,6 @@ * Public Functions ****************************************************************************/ -/**************************************************************************** - * Name: xtensa_coproc_savestate - * - * Description: - * If there is a current thread and it has a coprocessor state save area, - * then save all callee-saved state into this area. xtensa_coproc_savestate() - * is simply a C wrapper around the assembly language call to - * _xtensa_coproc_savestate. - * - * Entry Conditions: - * - The thread being switched out is still the current thread. - * - CPENABLE state reflects which coprocessors are active. - * - * Exit conditions: - * - All necessary CP callee-saved state has been saved. - * - * Input Parameters: - * tcb - A pointer to the TCB of thread whose co-processor state is to - * be saved. - * - * Returned Value: - * None - * - * Assumptions: - * Called with interrupts disabled. - * - ****************************************************************************/ - -void xtensa_coproc_savestate(struct tcb_s *tcb) -{ - uint32_t cpstate = (uint32_t)((uintptr_t)&tcb->xcp.cpstate); - - __asm__ __volatile__ - ( - "mov a2, %0\n" - "call0 _xtensa_coproc_savestate\n" - : - : "r" (cpstate) - : "a0", "a2", "a3", "a4", "a5", "a6", "a7", "a13", "a14", "a15" - ); -} - -/**************************************************************************** - * Name: xtensa_coproc_restorestate - * - * Description: - * Restore any callee-saved coprocessor state for the incoming thread. - * xtensa_coproc_restorestate() is simply a C wrapper around the assembly - * language call to _xtensa_coproc_restorestate. - * - * Entry Conditions: - * - CPENABLE is set up correctly for all required coprocessors. - * - * Exit conditions: - * - All necessary CP callee-saved state has been restored. - * - CPENABLE - unchanged. - * - * Input Parameters: - * tcb - A pointer to the TCB of thread whose co-processor state is to - * be restored. - * - * Returned Value: - * None - * - * Assumptions: - * Called with interrupts disabled. - * - ****************************************************************************/ - -void xtensa_coproc_restorestate(struct tcb_s *tcb) -{ - uint32_t cpstate = (uint32_t)((uintptr_t)&tcb->xcp.cpstate); - - __asm__ __volatile__ - ( - "mov a2, %0\n" - "call0 _xtensa_coproc_restorestate\n" - : - : "r" (cpstate) - : "a0", "a2", "a3", "a4", "a5", "a6", "a7", "a13", "a14", "a15" - ); -} - /**************************************************************************** * Name: xtensa_coproc_enable * @@ -238,5 +155,4 @@ void xtensa_coproc_disable(struct xtensa_cpstate_s *cpstate, int cpset) leave_critical_section(flags); } - #endif /* XCHAL_CP_NUM */ diff --git a/arch/xtensa/src/common/xtensa_exit.c b/arch/xtensa/src/common/xtensa_exit.c index bf568f10d4..e653690162 100644 --- a/arch/xtensa/src/common/xtensa_exit.c +++ b/arch/xtensa/src/common/xtensa_exit.c @@ -175,7 +175,7 @@ void _exit(int status) #if XCHAL_CP_NUM > 0 /* Set up the co-processor state for the newly started thread. */ - xtensa_coproc_restorestate(tcb); + xtensa_coproc_restorestate(&tcb->xcp.cpstate); #endif #ifdef CONFIG_ARCH_ADDRENV diff --git a/arch/xtensa/src/common/xtensa_irqdispatch.c b/arch/xtensa/src/common/xtensa_irqdispatch.c index 67192e0634..9ce5bba087 100644 --- a/arch/xtensa/src/common/xtensa_irqdispatch.c +++ b/arch/xtensa/src/common/xtensa_irqdispatch.c @@ -103,7 +103,7 @@ uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs) * NOTE 2. We saved a reference TCB of the original thread on entry. */ - xtensa_coproc_savestate(tcb); + xtensa_coproc_savestate(&tcb->xcp.cpstate); /* Then set up the co-processor state for the to-be-started thread. * @@ -112,7 +112,7 @@ uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs) */ tcb = this_task(); - xtensa_coproc_restorestate(tcb); + xtensa_coproc_restorestate(&tcb->xcp.cpstate); #endif #ifdef CONFIG_ARCH_ADDRENV diff --git a/arch/xtensa/src/common/xtensa_releasepending.c b/arch/xtensa/src/common/xtensa_releasepending.c index 4328d78a7e..cae473243f 100644 --- a/arch/xtensa/src/common/xtensa_releasepending.c +++ b/arch/xtensa/src/common/xtensa_releasepending.c @@ -124,7 +124,7 @@ void up_release_pending(void) * processor save area. */ - xtensa_coproc_savestate(rtcb); + xtensa_coproc_savestate(&rtcb->xcp.cpstate); #endif /* Restore the exception context of the rtcb at the (new) head * of the ready-to-run task list. @@ -135,7 +135,7 @@ void up_release_pending(void) #if XCHAL_CP_NUM > 0 /* Set up the co-processor state for the newly started thread. */ - xtensa_coproc_restorestate(rtcb); + xtensa_coproc_restorestate(&rtcb->xcp.cpstate); #endif #ifdef CONFIG_ARCH_ADDRENV diff --git a/arch/xtensa/src/common/xtensa_reprioritizertr.c b/arch/xtensa/src/common/xtensa_reprioritizertr.c index eb5255ece8..0226d18f72 100644 --- a/arch/xtensa/src/common/xtensa_reprioritizertr.c +++ b/arch/xtensa/src/common/xtensa_reprioritizertr.c @@ -177,7 +177,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) * processor save area. */ - xtensa_coproc_savestate(rtcb); + xtensa_coproc_savestate(&rtcb->xcp.cpstate); #endif /* Restore the exception context of the rtcb at the (new) head * of the ready-to-run task list. @@ -188,7 +188,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) #if XCHAL_CP_NUM > 0 /* Set up the co-processor state for the newly started thread. */ - xtensa_coproc_restorestate(rtcb); + xtensa_coproc_restorestate(&rtcb->xcp.cpstate); #endif #ifdef CONFIG_ARCH_ADDRENV diff --git a/arch/xtensa/src/common/xtensa_schedsigaction.c b/arch/xtensa/src/common/xtensa_schedsigaction.c index 438f712768..db0f5fa9c3 100644 --- a/arch/xtensa/src/common/xtensa_schedsigaction.c +++ b/arch/xtensa/src/common/xtensa_schedsigaction.c @@ -152,9 +152,9 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) CURRENT_REGS[REG_PC] = (uint32_t)xtensa_sigdeliver; #ifdef __XTENSA_CALL0_ABI__ - CURRENT_REGS[REG_PS] = (uint32_t)(PS_INTLEVEL(0) | PS_UM); + CURRENT_REGS[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM); #else - CURRENT_REGS[REG_PS] = (uint32_t)(PS_INTLEVEL(0) | PS_UM | PS_WOE); + CURRENT_REGS[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE); #endif /* And make sure that the saved context in the TCB is the same @@ -187,9 +187,9 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) tcb->xcp.regs[REG_PC] = (uint32_t)xtensa_sigdeliver; #ifdef __XTENSA_CALL0_ABI__ - tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(0) | PS_UM); + tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM); #else - tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(0) | PS_UM | PS_WOE); + tcb->xcp.regs[REG_PS] = (uint32_t)(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE); #endif } } diff --git a/arch/xtensa/src/common/xtensa_unblocktask.c b/arch/xtensa/src/common/xtensa_unblocktask.c index c7788927c6..40ecf73c56 100644 --- a/arch/xtensa/src/common/xtensa_unblocktask.c +++ b/arch/xtensa/src/common/xtensa_unblocktask.c @@ -138,7 +138,7 @@ void up_unblock_task(struct tcb_s *tcb) * processor save area. */ - xtensa_coproc_savestate(rtcb); + xtensa_coproc_savestate(&rtcb->xcp.cpstate); #endif /* Restore the exception context of the new task that is ready to @@ -151,7 +151,7 @@ void up_unblock_task(struct tcb_s *tcb) #if XCHAL_CP_NUM > 0 /* Set up the co-processor state for the newly started thread. */ - xtensa_coproc_restorestate(rtcb); + xtensa_coproc_restorestate(&rtcb->xcp.cpstate); #endif #ifdef CONFIG_ARCH_ADDRENV diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 6e1c44113f..b1fea99b58 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -44,7 +44,7 @@ CMN_ASRCS = xtensa_context.S xtensa_coproc.S xtensa_cpuint.S CMN_ASRCS += xtensa_int_handlers.S xtensa_nmi_handler.S xtensa_vectors.S CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c -CMN_CSRCS += xtensa_cpsave.c xtensa_createstack.c xtensa_exit.c xtensa_idle.c +CMN_CSRCS += xtensa_cpenable.c xtensa_createstack.c xtensa_exit.c xtensa_idle.c CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c xtensa_interruptcontext.c CMN_CSRCS += xtensa_irqdispatch.c xtensa_lowputs.c xtensa_mdelay.c CMN_CSRCS += xtensa_modifyreg8.c xtensa_modifyreg16.c xtensa_modifyreg32.c -- GitLab From eaa5968a22f7847520029a3590773ff51033bcfb Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 30 Oct 2016 08:46:35 -0600 Subject: [PATCH 263/734] Xtensa: Convert some CALL0 C calls to be compatible with Window ABI --- arch/xtensa/src/common/xtensa_int_handlers.S | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/xtensa/src/common/xtensa_int_handlers.S b/arch/xtensa/src/common/xtensa_int_handlers.S index 7796ab0594..f5fda35b57 100644 --- a/arch/xtensa/src/common/xtensa_int_handlers.S +++ b/arch/xtensa/src/common/xtensa_int_handlers.S @@ -159,7 +159,11 @@ */ mov a2, sp /* Argument: Top of stack = register save area */ +#ifdef __XTENSA_CALL0_ABI__ call0 xtensa_int_decode /* Call xtensa_int_decode */ +#else + call4 xtensa_int_decode /* Call xtensa_int_decode */ +#endif /* On return from xtensa_int_decode, A2 will contain the address of the new * register save area. Usually this would be the same as the current SP. @@ -189,7 +193,12 @@ mov a12, a6 /* Preserve a6 */ movi a2, XTENSA_IRQ_TIMER&level& /* Arg 1: IRQ number */ mov a3, sp /* Arg 2: Top of stack = register save area */ +#ifdef __XTENSA_CALL0_ABI__ call0 xtensa_irq_dispatch /* Call xtensa_int_decode */ +#else + call4 xtensa_irq_dispatch /* Call xtensa_int_decode */ +#endif + mov a6, a12 /* Preserve a6 */ .endif -- GitLab From fdede8099b017600fa5f6af2fad01f26177798aa Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 30 Oct 2016 10:57:57 -0600 Subject: [PATCH 264/734] Xtensa/ESP32: Add Level1 handler, panic handler, remove EXECHOOKS. --- arch/xtensa/include/esp32/irq.h | 13 + arch/xtensa/src/common/xtensa.h | 1 + arch/xtensa/src/common/xtensa_assert.c | 35 +++ arch/xtensa/src/common/xtensa_int_handlers.S | 243 ++++++++++++------- arch/xtensa/src/common/xtensa_nmi_handler.S | 31 ++- arch/xtensa/src/common/xtensa_panic.S | 129 ++++++++++ arch/xtensa/src/common/xtensa_vectors.S | 4 +- 7 files changed, 350 insertions(+), 106 deletions(-) create mode 100644 arch/xtensa/src/common/xtensa_panic.S diff --git a/arch/xtensa/include/esp32/irq.h b/arch/xtensa/include/esp32/irq.h index 590e6d28cb..a5f521f8b6 100644 --- a/arch/xtensa/include/esp32/irq.h +++ b/arch/xtensa/include/esp32/irq.h @@ -50,6 +50,19 @@ * Pre-processor Definitions ****************************************************************************/ +/* Exception Codes */ + +#define XTENSA_NMI_EXCEPTION 0 +#define XTENSA_DEBUG_EXCEPTION 1 +#define XTENSA_DOUBLE_EXCEPTION 2 +#define XTENSA_KERNEL_EXCEPTION 3 +#define XTENSA_COPROC_EXCEPTION 4 +#define XTENSA_LEVEL2_EXCEPTION 5 +#define XTENSA_LEVEL3_EXCEPTION 6 +#define XTENSA_LEVEL4_EXCEPTION 7 +#define XTENSA_LEVEL5_EXCEPTION 8 +#define XTENSA_LEVEL6_EXCEPTION 9 + /* Interrupt Matrix * * The Interrupt Matrix embedded in the ESP32 independently allocates diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index d6af111d04..2dce849d85 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -249,6 +249,7 @@ uint32_t *xtensa_int_decode(uint32_t *regs); uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs); uint32_t xtensa_enable_cpuint(uint32_t *shadow, uint32_t intmask); uint32_t xtensa_disable_cpuint(uint32_t *shadow, uint32_t intmask); +void xtensa_panic(int xptcode, uint32_t *regs) noreturn_function; /* Software interrupt handler */ diff --git a/arch/xtensa/src/common/xtensa_assert.c b/arch/xtensa/src/common/xtensa_assert.c index 98c5562d92..41adf94a48 100644 --- a/arch/xtensa/src/common/xtensa_assert.c +++ b/arch/xtensa/src/common/xtensa_assert.c @@ -158,3 +158,38 @@ void up_assert(const uint8_t *filename, int lineno) xtensa_assert(EXIT_FAILURE); } + +/**************************************************************************** + * Name: xtensa_panic + ****************************************************************************/ + +void xtensa_panic(int xptcode, uint32_t *regs) +{ +#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT) + struct tcb_s *rtcb = this_task(); +#endif + + /* We get here when a un-dispatch-able, irrecoverable excpetion occurs */ + + board_autoled_on(LED_ASSERTION); + +#if CONFIG_TASK_NAME_SIZE > 0 + _alert("Unhandled Exception %d task: %s\n", xptcode, rtcb->name); +#else + _alert("Unhandled Exception %d\n", xptcode); +#endif + + xtensa_dumpstate(); + +#ifdef CONFIG_ARCH_USBDUMP + /* Dump USB trace data */ + + (void)usbtrace_enumerate(assert_tracecallback, NULL); +#endif + +#ifdef CONFIG_BOARD_CRASHDUMP + board_crashdump(up_getsp(), this_task(), filename, lineno); +#endif + + xtensa_assert(EXIT_FAILURE); +} diff --git a/arch/xtensa/src/common/xtensa_int_handlers.S b/arch/xtensa/src/common/xtensa_int_handlers.S index f5fda35b57..db358ff734 100644 --- a/arch/xtensa/src/common/xtensa_int_handlers.S +++ b/arch/xtensa/src/common/xtensa_int_handlers.S @@ -127,25 +127,6 @@ and a2, a2, a4 beqz a2, 5f /* Nothing to do */ -#ifdef XT_INTEXC_HOOKS - /* Call interrupt hook if present to (pre)handle interrupts. */ - - movi a4, _xt_intexc_hooks - l32i a4, a4, \level << 2 - beqz a4, 2f - -#ifdef __XTENSA_CALL0_ABI__ - callx0 a4 - beqz a2, 5f -#else - mov a6, a2 - callx4 a4 - beqz a6, 5f - mov a2, a6 -#endif -2: -#endif - /* If multiple bits are set then MSB has highest priority. */ extract_msb a4, a2 /* a4 = MSB of a2, a2 trashed */ @@ -259,10 +240,63 @@ ****************************************************************************/ /**************************************************************************** - * LOW PRIORITY (LEVEL 1) LOW LEVEL HANDLER. + * LEVEL 1 INTERRUPT HANDLER ****************************************************************************/ +/* The level1 interrupt vector is invoked via the User exception vector. */ -#warning REVISIT level 1 interrupt handlers + .section HANDLER_SECTION, "ax" + .type _xtensa_level1_handler, @function + .align 4 + +_xtensa_level1_handler: + + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, PS /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EPC_1 /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE_1 /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) + + /* Save rest of interrupt context. */ + + s32i a2, sp, (4 * REG_A2) + mov a2, sp /* Address of state save on stack */ + call0 _xtensa_context_save /* Save full register state */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + + ps_setup 1 a0 + + /* Decode and dispatch the interrupt. In the event of an interrupt + * level context dispatch_c_isr() will switch stacks to the new task's + * context save area. + */ + + dispatch_c_isr 1 XCHAL_INTLEVEL1_MASK + + /* Restore registers in preparation to return from interrupt */ + + call0 _xtensa_context_restore + + /* Restore only level-specific regs (the rest were already restored) */ + + l32i a0, sp, (4 * REG_PS) /* Retrieve interruptee's PS */ + wsr a0, EPS_1 + l32i a0, sp, (4 * REG_PC) /* Retrieve interruptee's PC */ + wsr a0, EPC_1 + l32i a0, sp, (4 * REG_A0) /* Retrieve interruptee's A0 */ + l32i a2, sp, (4 * REG_A2) /* Retrieve interruptee's A2 */ + l32i sp, sp, (4 * REG_A1) /* Remove interrupt stack frame */ + rsync /* Ensure EPS and EPC written */ + + /* Return from interrupt. RFI restores the PS from EPS_1 and jumps to + * the address in EPC_1. + */ + + rfi 1 /**************************************************************************** * MEDIUM PRIORITY (LEVEL 2+) INTERRUPT LOW LEVEL HANDLERS. @@ -310,7 +344,7 @@ _xtensa_level2_handler: /* Save rest of interrupt context. */ s32i a2, sp, (4 * REG_A2) - movi a2, sp /* Address of state save on stack */ + mov a2, sp /* Address of state save on stack */ call0 _xtensa_context_save /* Save full register state */ /* Set up PS for C, enable interrupts above this level and clear EXCM. */ @@ -367,7 +401,7 @@ _xtensa_level3_handler: /* Save rest of interrupt context. */ s32i a2, sp, (4 * REG_A2) - movi a2, sp /* Address of state save on stack */ + mov a2, sp /* Address of state save on stack */ call0 _xtensa_context_save /* Save full register state */ /* Set up PS for C, enable interrupts above this level and clear EXCM. */ @@ -424,7 +458,7 @@ _xtensa_level4_handler: /* Save rest of interrupt context. */ s32i a2, sp, (4 * REG_A2) - movi a2, sp /* Address of state save on stack */ + mov a2, sp /* Address of state save on stack */ call0 _xtensa_context_save /* Save full register state */ /* Set up PS for C, enable interrupts above this level and clear EXCM. */ @@ -481,7 +515,7 @@ _xtensa_level5_handler: /* Save rest of interrupt context. */ s32i a2, sp, (4 * REG_A2) - movi a2, sp /* Address of state save on stack */ + mov a2, sp /* Address of state save on stack */ call0 _xtensa_context_save /* Save full register state */ /* Set up PS for C, enable interrupts above this level and clear EXCM. */ @@ -538,7 +572,7 @@ _xtensa_level6_handler: /* Save rest of interrupt context. */ s32i a2, sp, (4 * REG_A2) - movi a2, sp /* Address of state save on stack */ + mov a2, sp /* Address of state save on stack */ call0 _xtensa_context_save /* Save full register state */ /* Set up PS for C, enable interrupts above this level and clear EXCM. */ @@ -618,29 +652,30 @@ _xtensa_level6_handler: _xtensa_level2_handler: -#ifdef XT_INTEXC_HOOKS - /* Call interrupt hook if present to (pre)handle interrupts. */ - - movi a0, _xt_intexc_hooks - l32i a0, a0, 2 << 2 - beqz a0, 1f - -.Ln_xtensa_level2_handler_call_hook: +#if 1 + /* For now, just panic */ - callx0 a0 /* Must NOT disturb stack! */ - -1: -#endif + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS_2 /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EPC_2 /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE_2 /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) - /* USER_EDIT: - * ADD HIGH PRIORITY LEVEL 2 INTERRUPT HANDLER CODE HERE. - */ + s32i a2, sp, (4 * REG_A2) + movi a2, XTENSA_LEVEL2_EXCEPTION /* Address of state save on stack */ + call0 _xtensa_panic /* Does not return */ - .align 4 +#else + /* Add high priority level 2 interrupt handler code here. */ rsr a0, EXCSAVE_2 /* Restore a0 */ rfi 2 +#endif #endif /* XCHAL_INT_NLEVELS >=2 && XCHAL_EXCM_LEVEL < 2 && XCHAL_DEBUGLEVEL !=2 */ #if XCHAL_INT_NLEVELS >=3 && XCHAL_EXCM_LEVEL < 3 && XCHAL_DEBUGLEVEL !=3 @@ -650,28 +685,32 @@ _xtensa_level2_handler: _xtensa_level3_handler: -#ifdef XT_INTEXC_HOOKS - /* Call interrupt hook if present to (pre)handle interrupts. */ - - movi a0, _xt_intexc_hooks - l32i a0, a0, 3 << 2 - beqz a0, 1f +#if 1 + /* For now, just panic */ -.Ln_xtensa_level3_handler_call_hook: + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS_3 /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EPC_3 /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE_3 /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) - callx0 a0 /* Must NOT disturb stack! */ -1: -#endif + s32i a2, sp, (4 * REG_A2) + movi a2, XTENSA_LEVEL3_EXCEPTION /* Address of state save on stack */ + call0 _xtensa_panic /* Does not return */ - /* USER_EDIT: - * ADD HIGH PRIORITY LEVEL 3 INTERRUPT HANDLER CODE HERE. - */ +#else + wsr a0, EXCSAVE_3 /* Save a0 */ - .align 4 + /* Add high priority level 2 interrupt handler code here. */ rsr a0, EXCSAVE_3 /* Restore a0 */ rfi 3 +#endif #endif /* XCHAL_INT_NLEVELS >=3 && XCHAL_EXCM_LEVEL < 3 && XCHAL_DEBUGLEVEL !=3 */ #if XCHAL_INT_NLEVELS >=4 && XCHAL_EXCM_LEVEL < 4 && XCHAL_DEBUGLEVEL !=4 @@ -681,28 +720,32 @@ _xtensa_level3_handler: _xtensa_level4_handler: -#ifdef XT_INTEXC_HOOKS - /* Call interrupt hook if present to (pre)handle interrupts. */ +#if 1 + /* For now, just panic */ - movi a0, _xt_intexc_hooks - l32i a0, a0, 4 << 2 - beqz a0, 1f + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS_4 /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EPC_4 /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE_4 /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) -.Ln_xtensa_level4_handler_call_hook: + s32i a2, sp, (4 * REG_A2) + movi a2, XTENSA_LEVEL4_EXCEPTION /* Address of state save on stack */ + call0 _xtensa_panic /* Does not return */ - callx0 a0 /* Must NOT disturb stack! */ -1: -#endif +#else + wsr a0, EXCSAVE_4 /* Save a0 */ - /* USER_EDIT: - * ADD HIGH PRIORITY LEVEL 4 INTERRUPT HANDLER CODE HERE. - */ - - .align 4 + /* Add high priority level 2 interrupt handler code here. */ rsr a0, EXCSAVE_4 /* Restore a0 */ rfi 4 +#endif #endif /* XCHAL_INT_NLEVELS >=4 && XCHAL_EXCM_LEVEL < 4 && XCHAL_DEBUGLEVEL !=4 */ #if XCHAL_INT_NLEVELS >=5 && XCHAL_EXCM_LEVEL < 5 && XCHAL_DEBUGLEVEL !=5 @@ -712,26 +755,32 @@ _xtensa_level4_handler: _xtensa_level5_handler: -#ifdef XT_INTEXC_HOOKS - /* Call interrupt hook if present to (pre)handle interrupts. */ +#if 1 + /* For now, just panic */ - movi a0, _xt_intexc_hooks - l32i a0, a0, 5 << 2 - beqz a0, 1f + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS_5 /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EPC_5 /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE_5 /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) -.Ln_xtensa_level5_handler_call_hook: + s32i a2, sp, (4 * REG_A2) + movi a2, XTENSA_LEVEL5_EXCEPTION /* Address of state save on stack */ + call0 _xtensa_panic /* Does not return */ - callx0 a0 /* Must NOT disturb stack! */ -1: -#endif +#else + wsr a0, EXCSAVE_5 /* Save a0 */ - /* USER_EDIT: - * ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE. - */ + /* Add high priority level 2 interrupt handler code here. */ rsr a0, EXCSAVE_5 /* Restore a0 */ rfi 5 +#endif #endif /* XCHAL_INT_NLEVELS >=5 && XCHAL_EXCM_LEVEL < 5 && XCHAL_DEBUGLEVEL !=5 */ #if XCHAL_INT_NLEVELS >=6 && XCHAL_EXCM_LEVEL < 6 && XCHAL_DEBUGLEVEL !=6 @@ -741,24 +790,30 @@ _xtensa_level5_handler: _xtensa_level6_handler: -#ifdef XT_INTEXC_HOOKS - /* Call interrupt hook if present to (pre)handle interrupts. */ +#if 1 + /* For now, just panic */ - movi a0, _xt_intexc_hooks - l32i a0, a0, 6 << 2 - beqz a0, 1f + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS_6 /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EPC_6 /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE_6 /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) -.Ln_xtensa_level6_handler_call_hook: + s32i a2, sp, (4 * REG_A2) + movi a2, XTENSA_LEVEL6_EXCEPTION /* Address of state save on stack */ + call0 _xtensa_panic /* Does not return */ - callx0 a0 /* Must NOT disturb stack! */ -1: -#endif +#else + wsr a0, EXCSAVE_6 /* Save a0 */ - /* USER_EDIT: - * ADD HIGH PRIORITY LEVEL 6 INTERRUPT HANDLER CODE HERE. - */ + /* Add high priority level 2 interrupt handler code here. */ rsr a0, EXCSAVE_6 /* Restore a0 */ rfi 6 +#endif #endif /* XCHAL_INT_NLEVELS >=6 && XCHAL_EXCM_LEVEL < 6 && XCHAL_DEBUGLEVEL !=6 */ diff --git a/arch/xtensa/src/common/xtensa_nmi_handler.S b/arch/xtensa/src/common/xtensa_nmi_handler.S index 67510aa41c..bbf08cfe4a 100644 --- a/arch/xtensa/src/common/xtensa_nmi_handler.S +++ b/arch/xtensa/src/common/xtensa_nmi_handler.S @@ -59,6 +59,7 @@ #include +#include #include #include @@ -103,23 +104,33 @@ #if XCHAL_HAVE_NMI .section HANDLER_SECTION, "ax" - .type _xt_nmi, @function + .type _xtensa_nmi, @function .align 4 -_xt_nmi: -#ifdef XT_INTEXC_HOOKS - /* Call interrupt hook if present to (pre)handle interrupts. */ +_xtensa_nmi: - movi a0, _xt_intexc_hooks - l32i a0, a0, XCHAL_NMILEVEL << 2 - beqz a0, 1f - callx0 a0 /* Must NOT disturb stack! */ -1: -#endif +#if 1 + /* For now, just panic */ + + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS_2 /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EPC_2 /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE_2 /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) + s32i a2, sp, (4 * REG_A2) + movi a2, XTENSA_NMI_EXCEPTION /* Address of state save on stack */ + call0 _xtensa_panic /* Does not return */ + +#else /* Add high priority non-maskable interrupt (NMI) handler code here. */ rsr a0, EXCSAVE + XCHAL_NMILEVEL /* Restore a0 */ rfi XCHAL_NMILEVEL +#endif #endif /* XCHAL_HAVE_NMI */ diff --git a/arch/xtensa/src/common/xtensa_panic.S b/arch/xtensa/src/common/xtensa_panic.S new file mode 100644 index 0000000000..8b6608d795 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_panic.S @@ -0,0 +1,129 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_panic.S + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * + * Copyright (c) 2006-2015 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + + .file "xtensa_panic.S" + +/* NOTES on the use of 'call0' for long jumps instead of 'j': + * + * 1. This file should be assembled with the -mlongcalls option to xt-xcc. + * + * 2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to + * a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the + * distance from the call to the destination. The linker then relaxes + * it back to 'call0 dest' if it determines that dest is within range. + * This allows more flexibility in locating code without the performance + * overhead of the 'l32r' literal data load in cases where the destination + * is in range of 'call0'. There is an additional benefit in that 'call0' + * has a longer range than 'j' due to the target being word-aligned, so + * the 'l32r' sequence is less likely needed. + * + * 3. The use of 'call0' with -mlongcalls requires that register a0 not be + * live at the time of the call, which is always the case for a function + * call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'. + * + * 4. This use of 'call0' is independent of the C function call ABI. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +/**************************************************************************** + * Assembly Language Marcros + ****************************************************************************/ + +/**************************************************************************** + * Name: _xtensa_panic + * + * Description: + * Should be reached by call0 (preferable) or jump only. If call0, a0 says + * where from. If on simulator, display panic message and abort, else loop + * indefinitely. + * + * Entry Conditions: + * - A1 = Stack frame already allocated. SP points to beginning of the + * register frame. + * - A0, A1, A2, PC and PS = Already saved in the stack frame + * - A2 = Exception code + * + * Exit conditions: + * Does not return. + * + ****************************************************************************/ + + .section HANDLER_SECTION, "ax" + .global _xtensa_panic + .type _xtensa_panic, @function + + .align 4 + .literal_position + .align 4 + +_xtensa_panic: + /* Save rest of interrupt context (A2=address of state save area on + * stack. + */ + + mov a2, sp /* Address of state save on stack */ + call0 _xtensa_context_save /* Save full register state */ + + /* Save exc cause and vaddr into exception frame */ + + rsr a0, EXCCAUSE + s32i a0, sp, (4 * REG_EXCCAUSE) + rsr a0, EXCVADDR + s32i a0, sp, (4 * REG_EXCVADDR) + + /* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */ + + mov a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE + wsr a0, PS + + /* Call C panic handler: Arg1 (A2) = Exception code; Arg 2 (A3) = start + * of the register save area. + */ + + mov a3, sp +#ifdef __XTENSA_CALL0_ABI__ + call0 xtensa_panic /* Call xtensa_panic. Should not return */ +#else + call4 xtensa_panic /* Call xtensa_panic. Should not return */ +#endif + +1: j 1b /* loop infinitely */ + retw diff --git a/arch/xtensa/src/common/xtensa_vectors.S b/arch/xtensa/src/common/xtensa_vectors.S index 6f84444aeb..9e9a1ab28e 100644 --- a/arch/xtensa/src/common/xtensa_vectors.S +++ b/arch/xtensa/src/common/xtensa_vectors.S @@ -175,8 +175,8 @@ _xtensa_level6_vector: _xtensa_nmi_vector: - wsr a0, EXCSAVE + XCHAL_NMILEVEL _ /* preserve a0 */ - call0 _xt_nmi /* load interrupt handler */ + wsr a0, EXCSAVE + XCHAL_NMILEVEL /* Preserve a0 */ + call0 _xtensa_nmi /* Load interrupt handler */ /* Never returns here - call0 is used as a jump */ -- GitLab From a4c3fef0b792239afbfc05efd47e9b7bd60cadba Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 30 Oct 2016 12:20:11 -0600 Subject: [PATCH 265/734] Xtensa: Add more exception vectors. All just cause a PANIC now. --- arch/xtensa/src/common/xtensa_nmi_handler.S | 136 --------------- arch/xtensa/src/common/xtensa_panic.S | 4 +- arch/xtensa/src/common/xtensa_vectors.S | 174 ++++++++++++++++++-- arch/xtensa/src/esp32/Make.defs | 2 +- configs/esp32-core/scripts/esp32_common.ld | 6 +- 5 files changed, 163 insertions(+), 159 deletions(-) delete mode 100644 arch/xtensa/src/common/xtensa_nmi_handler.S diff --git a/arch/xtensa/src/common/xtensa_nmi_handler.S b/arch/xtensa/src/common/xtensa_nmi_handler.S deleted file mode 100644 index bbf08cfe4a..0000000000 --- a/arch/xtensa/src/common/xtensa_nmi_handler.S +++ /dev/null @@ -1,136 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/common/xtensa_nmi_handler.S - * - * Adapted from use in NuttX by: - * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Derives from logic originally provided by Cadence Design Systems Inc. - * - * Copyright (c) 2006-2015 Cadence Design Systems Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY - * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - ****************************************************************************/ - - .file "xtensa_nmi_handler.S" - -/* NOTES on the use of 'call0' for long jumps instead of 'j': - * - * 1. This file should be assembled with the -mlongcalls option to xt-xcc. - * - * 2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to - * a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the - * distance from the call to the destination. The linker then relaxes - * it back to 'call0 dest' if it determines that dest is within range. - * This allows more flexibility in locating code without the performance - * overhead of the 'l32r' literal data load in cases where the destination - * is in range of 'call0'. There is an additional benefit in that 'call0' - * has a longer range than 'j' due to the target being word-aligned, so - * the 'l32r' sequence is less likely needed. - * - * 3. The use of 'call0' with -mlongcalls requires that register a0 not be - * live at the time of the call, which is always the case for a function - * call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'. - * - * 4. This use of 'call0' is independent of the C function call ABI. - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include "chip_macros.h" -#include "xtensa_abi.h" - -/**************************************************************************** - * Assembly Language Macros - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * HIGH PRIORITY NMI LOW-LEVEL HANDLER - * - * High priority interrupts are by definition those with priorities greater - * than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority - * interrupts cannot interact with the RTOS, that is they must save all regs - * they use and not call any RTOS function. - * - * A further restriction imposed by the Xtensa windowed architecture is that - * high priority interrupts must not modify the stack area even logically - * "above" the top of the interrupted stack (they need to provide their - * own stack or static save area). - * - * Cadence Design Systems recommends high priority interrupt handlers be - * coded in assembly and used for purposes requiring very short service - * times. - * - * The NMI vector goes at a predetermined location according to the Xtensa - * hardware configuration, which is ensured by its placement in a special - * section known to the Xtensa linker support package (LSP). It performs - * the minimum necessary before jumping to the NMI andler. - * - * Below is a template for the high priority NMI interrupt handler. - * A template and example can be found in the Cadence Design Systems tools - * documentation: "Microprocessor Programmer's Guide". - * - ****************************************************************************/ - -#if XCHAL_HAVE_NMI - .section HANDLER_SECTION, "ax" - .type _xtensa_nmi, @function - .align 4 - -_xtensa_nmi: - -#if 1 - /* For now, just panic */ - - mov a0, sp /* sp == a1 */ - addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ - s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ - rsr a0, EPS_2 /* Save interruptee's PS */ - s32i a0, sp, (4 * REG_PS) - rsr a0, EPC_2 /* Save interruptee's PC */ - s32i a0, sp, (4 * REG_PC) - rsr a0, EXCSAVE_2 /* Save interruptee's a0 */ - s32i a0, sp, (4 * REG_A0) - - s32i a2, sp, (4 * REG_A2) - movi a2, XTENSA_NMI_EXCEPTION /* Address of state save on stack */ - call0 _xtensa_panic /* Does not return */ - -#else - /* Add high priority non-maskable interrupt (NMI) handler code here. */ - - rsr a0, EXCSAVE + XCHAL_NMILEVEL /* Restore a0 */ - rfi XCHAL_NMILEVEL - -#endif -#endif /* XCHAL_HAVE_NMI */ diff --git a/arch/xtensa/src/common/xtensa_panic.S b/arch/xtensa/src/common/xtensa_panic.S index 8b6608d795..e24acc12fa 100644 --- a/arch/xtensa/src/common/xtensa_panic.S +++ b/arch/xtensa/src/common/xtensa_panic.S @@ -64,7 +64,7 @@ #include /**************************************************************************** - * Assembly Language Marcros + * Public Functions ****************************************************************************/ /**************************************************************************** @@ -111,7 +111,7 @@ _xtensa_panic: /* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */ - mov a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE + movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE wsr a0, PS /* Call C panic handler: Arg1 (A2) = Exception code; Arg 2 (A3) = start diff --git a/arch/xtensa/src/common/xtensa_vectors.S b/arch/xtensa/src/common/xtensa_vectors.S index 9e9a1ab28e..5f5c16248b 100644 --- a/arch/xtensa/src/common/xtensa_vectors.S +++ b/arch/xtensa/src/common/xtensa_vectors.S @@ -48,15 +48,14 @@ ****************************************************************************/ /**************************************************************************** - * C Prototype: - * void _xtensa_levelN_vector(void) + * Name: _xtensa_level[n]_vector, n=2..6 * * Description: - * Xtensa interrupt vectors. Each vector goes at a predetermined location - * according to the Xtensa hardware configuration, which is ensured by its - * placement in a special section known to the NuttX linker script. The - * vector logic performs the minimum necessary operations before jumping - * to the handler. + * Xtensa medium/nigh priority interrupt vectors. Each vector goes at a + * predetermined location according to the Xtensa hardware configuration, + * which is ensured by its placement in a special section known to the + * NuttX linker script. The vector logic performs the minimum necessary + * operations before jumping to the handler. * ****************************************************************************/ @@ -154,15 +153,26 @@ _xtensa_level6_vector: #endif /**************************************************************************** - * C Prototype: - * void _xtensa_nmi_vector(void) + * Exception Vectors (except User, Co-processor and window exception + * vectors). + * + * Each vector goes at a predetermined location according to the Xtensa + * hardware configuration, which is ensured by its placement in a special + * section known to the Xtensa linker support package (LSP). It performs + * the minimum necessary before jumping to the handler in the .text section. + * + * The corresponding handler goes in the normal .text section. It sets up + * the appropriate stack frame, saves a few vector-specific registers and + * calls _xtensa_panic() to save the rest of the interrupted context + * and enter the NuttX panic handler + * + ****************************************************************************/ + +/**************************************************************************** + * Name: _xtensa_nmi_vector * * Description: - * Xtensa NMI vectors. This vector goes at a predetermined location - * according to the Xtensa hardware configuration, which is ensured by its - * placement in a special section known to the NuttX linker script. The - * vector logic performs the minimum necessary operations before jumping - * to the handler. + * NMI Exception * ****************************************************************************/ @@ -175,11 +185,141 @@ _xtensa_level6_vector: _xtensa_nmi_vector: - wsr a0, EXCSAVE + XCHAL_NMILEVEL /* Preserve a0 */ - call0 _xtensa_nmi /* Load interrupt handler */ +#if 1 + /* For now, just panic */ - /* Never returns here - call0 is used as a jump */ + wsr a0, EXCSAVE + XCHAL_NMILEVEL /* Preserve a0 */ + + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS + XCHAL_NMILEVEL /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EPC_2 /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE + XCHAL_NMILEVEL /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) + + s32i a2, sp, (4 * REG_A2) + movi a2, XTENSA_NMI_EXCEPTION /* Address of state save on stack */ + call0 _xtensa_panic /* Does not return */ + +#else + /* Add high priority non-maskable interrupt (NMI) handler code here. */ + + rfi XCHAL_NMILEVEL + +#endif .size _xtensa_nmi_vector, . - _xtensa_nmi_vector .end literal_prefix + +/**************************************************************************** + * Name: _debug_exception_vector + * + * Description: + * Debug exception vector + * + ****************************************************************************/ + +#if XCHAL_HAVE_DEBUG + .begin literal_prefix .debug_exception_vector + .section .debug_exception_vector.text, "ax" + .global _debug_exception_vector + .align 4 + +_debug_exception_vector: + + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS + XCHAL_DEBUGLEVEL /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EPC + XCHAL_DEBUGLEVEL /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE + XCHAL_DEBUGLEVEL /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) + + s32i a2, sp, (4 * REG_A2) + movi a2, XTENSA_DEBUG_EXCEPTION /* Address of state save on stack */ + call0 _xtensa_panic /* Does not return */ + + .end literal_prefix + +#endif /* XCHAL_HAVE_DEBUG */ + +/**************************************************************************** + * Name: _double_exception_vector + * + * Description: + * Double Exception Vector. Double exceptions are not a normal occurrence. + * They indicate a bug of some kind. + * + ****************************************************************************/ + +#ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR + .begin literal_prefix .double_exception_vector + .section .double_exception_vector.text, "ax" + .global _double_exception_vector + .align 4 + +_double_exception_vector: + +#if XCHAL_HAVE_DEBUG + break 1, 4 /* Unhandled double exception */ +#endif + + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS_1 /* Save interruptee's PS -- REVISIT */ + s32i a0, sp, (4 * REG_PS) + rsr a0, DEPC /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE_1 /* Save interruptee's a0 -- REVISIT */ + s32i a0, sp, (4 * REG_A0) + + s32i a2, sp, (4 * REG_A2) + movi a2, XTENSA_DOUBLE_EXCEPTION /* Address of state save on stack */ + call0 _xtensa_panic /* Does not return */ + + .end literal_prefix + +#endif /* XCHAL_DOUBLEEXC_VECTOR_VADDR */ + +/**************************************************************************** + * Name: _kernel_exception_vector + * + * Description: + * Kernel Exception (including Level 1 Interrupt from kernel mode). + * + ****************************************************************************/ + + .begin literal_prefix .kernel_exception_vector + .section .kernel_exception_vector.text, "ax" + .global _kernel_exception_vector + .align 4 + +_kernel_exception_vector: + +#if XCHAL_HAVE_DEBUG + break 1, 0 /* Unhandled kernel exception */ +#endif + + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS_1 /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EPC_1 /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE_1 /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) + + s32i a2, sp, (4 * REG_A2) + movi a2, XTENSA_KERNEL_EXCEPTION /* Address of state save on stack */ + call0 _xtensa_panic /* Does not return */ + + .end literal_prefix + #endif diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index b1fea99b58..3cb7c2b0c6 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -41,7 +41,7 @@ HEAD_CSRC = esp32_start.c # Common XTENSA files (arch/xtensa/src/common) CMN_ASRCS = xtensa_context.S xtensa_coproc.S xtensa_cpuint.S -CMN_ASRCS += xtensa_int_handlers.S xtensa_nmi_handler.S xtensa_vectors.S +CMN_ASRCS += xtensa_int_handlers.S xtensa_panic.S xtensa_vectors.S CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c CMN_CSRCS += xtensa_cpenable.c xtensa_createstack.c xtensa_exit.c xtensa_idle.c diff --git a/configs/esp32-core/scripts/esp32_common.ld b/configs/esp32-core/scripts/esp32_common.ld index 680c71a784..606cc814d0 100644 --- a/configs/esp32-core/scripts/esp32_common.ld +++ b/configs/esp32-core/scripts/esp32_common.ld @@ -29,15 +29,15 @@ SECTIONS . = 0x240; KEEP(*(.xtensa_level5_vector.text)); . = 0x280; - KEEP(*(.DebugExceptionVector.text)); + KEEP(*(.debug_exception_vector.text)); . = 0x2c0; KEEP(*(.nmi_vector.text)); . = 0x300; - KEEP(*(.KernelExceptionVector.text)); + KEEP(*(.kernel_exception_vector.text)); . = 0x340; KEEP(*(.UserExceptionVector.text)); . = 0x3C0; - KEEP(*(.DoubleExceptionVector.text)); + KEEP(*(.double_exception_vector.text)); . = 0x400; *(.*Vector.literal) -- GitLab From 2a17786f98566bee41e5316bdb9bf1e095f39ed3 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 30 Oct 2016 12:24:22 -0600 Subject: [PATCH 266/734] Xtensa/ESP32: Fix some compilation issues --- arch/xtensa/src/common/xtensa_coproc.S | 12 ++++++------ arch/xtensa/src/common/xtensa_dumpstate.c | 8 +++++++- arch/xtensa/src/common/xtensa_int_handlers.S | 2 +- arch/xtensa/src/common/xtensa_irqdispatch.c | 2 +- arch/xtensa/src/common/xtensa_vectors.S | 5 +++-- configs/esp32-core/nsh/defconfig | 2 +- configs/esp32-core/smp/defconfig | 1 - 7 files changed, 19 insertions(+), 13 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_coproc.S b/arch/xtensa/src/common/xtensa_coproc.S index 2bcba0185f..c29e23a33b 100644 --- a/arch/xtensa/src/common/xtensa_coproc.S +++ b/arch/xtensa/src/common/xtensa_coproc.S @@ -256,9 +256,9 @@ xtensa_coproc_savestate: /* Restore a13-15 and return */ - 132i a13, sp, LOCAL_OFFSET(1) - 132i a14, sp, LOCAL_OFFSET(2) - 132i a15, sp, LOCAL_OFFSET(3) + l32i a13, sp, LOCAL_OFFSET(1) + l32i a14, sp, LOCAL_OFFSET(2) + l32i a15, sp, LOCAL_OFFSET(3) RET(16) @@ -443,9 +443,9 @@ xtensa_coproc_restorestate: /* Restore a13-15 and return */ - 132i a13, sp, LOCAL_OFFSET(1) - 132i a14, sp, LOCAL_OFFSET(2) - 132i a15, sp, LOCAL_OFFSET(3) + l32i a13, sp, LOCAL_OFFSET(1) + l32i a14, sp, LOCAL_OFFSET(2) + l32i a15, sp, LOCAL_OFFSET(3) RET(16) diff --git a/arch/xtensa/src/common/xtensa_dumpstate.c b/arch/xtensa/src/common/xtensa_dumpstate.c index b1afe927fc..975993af62 100644 --- a/arch/xtensa/src/common/xtensa_dumpstate.c +++ b/arch/xtensa/src/common/xtensa_dumpstate.c @@ -68,7 +68,13 @@ static inline uint32_t xtensa_getsp(void) { register uint32_t sp; -#warning Missing logic + + __asm__ __volatile__ + ( + "mov %0, sp\n" + : "=r" (sp) + ); + return sp; } diff --git a/arch/xtensa/src/common/xtensa_int_handlers.S b/arch/xtensa/src/common/xtensa_int_handlers.S index db358ff734..c8dc0c4569 100644 --- a/arch/xtensa/src/common/xtensa_int_handlers.S +++ b/arch/xtensa/src/common/xtensa_int_handlers.S @@ -284,7 +284,7 @@ _xtensa_level1_handler: /* Restore only level-specific regs (the rest were already restored) */ l32i a0, sp, (4 * REG_PS) /* Retrieve interruptee's PS */ - wsr a0, EPS_1 + wsr a0, PS l32i a0, sp, (4 * REG_PC) /* Retrieve interruptee's PC */ wsr a0, EPC_1 l32i a0, sp, (4 * REG_A0) /* Retrieve interruptee's A0 */ diff --git a/arch/xtensa/src/common/xtensa_irqdispatch.c b/arch/xtensa/src/common/xtensa_irqdispatch.c index 9ce5bba087..e2ce51f29e 100644 --- a/arch/xtensa/src/common/xtensa_irqdispatch.c +++ b/arch/xtensa/src/common/xtensa_irqdispatch.c @@ -86,7 +86,7 @@ uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs) irq_dispatch(irq, regs); -#if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV) +#if XCHAL_CP_NUM > 0 || defined(CONFIG_ARCH_ADDRENV) /* Check for a context switch. If a context switch occurred, then * CURRENT_REGS will have a different value than it did on entry. */ diff --git a/arch/xtensa/src/common/xtensa_vectors.S b/arch/xtensa/src/common/xtensa_vectors.S index 5f5c16248b..42158964e4 100644 --- a/arch/xtensa/src/common/xtensa_vectors.S +++ b/arch/xtensa/src/common/xtensa_vectors.S @@ -38,6 +38,7 @@ #include +#include #include #include @@ -272,7 +273,7 @@ _double_exception_vector: mov a0, sp /* sp == a1 */ addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ - rsr a0, EPS_1 /* Save interruptee's PS -- REVISIT */ + rsr a0, EPS /* Save interruptee's PS -- REVISIT */ s32i a0, sp, (4 * REG_PS) rsr a0, DEPC /* Save interruptee's PC */ s32i a0, sp, (4 * REG_PC) @@ -309,7 +310,7 @@ _kernel_exception_vector: mov a0, sp /* sp == a1 */ addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ - rsr a0, EPS_1 /* Save interruptee's PS */ + rsr a0, EPS /* Save interruptee's PS */ s32i a0, sp, (4 * REG_PS) rsr a0, EPC_1 /* Save interruptee's PC */ s32i a0, sp, (4 * REG_PC) diff --git a/configs/esp32-core/nsh/defconfig b/configs/esp32-core/nsh/defconfig index b163053233..96bb1c7bd3 100644 --- a/configs/esp32-core/nsh/defconfig +++ b/configs/esp32-core/nsh/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH_CHIP="esp32" # CONFIG_SERIAL_TERMIOS is not set CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_FAMILY_LX6=y -CONFIG_XTENSA_CALL0_ABI=y # CONFIG_XTENSA_USE_OVLY is not set CONFIG_XTENSA_CP_INITSET=0x0001 CONFIG_ESP32_UART=y @@ -203,6 +202,7 @@ CONFIG_PREALLOC_TIMERS=4 # # Tasks and Scheduling # +# CONFIG_SMP is not set # CONFIG_INIT_NONE is not set CONFIG_INIT_ENTRYPOINT=y # CONFIG_INIT_FILEPATH is not set diff --git a/configs/esp32-core/smp/defconfig b/configs/esp32-core/smp/defconfig index 104c7c89ba..403a5e3c8d 100644 --- a/configs/esp32-core/smp/defconfig +++ b/configs/esp32-core/smp/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH_CHIP="esp32" # CONFIG_SERIAL_TERMIOS is not set CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_FAMILY_LX6=y -CONFIG_XTENSA_CALL0_ABI=y # CONFIG_XTENSA_USE_OVLY is not set CONFIG_XTENSA_CP_INITSET=0x0001 CONFIG_ESP32_UART=y -- GitLab From 85ed3dae9a8f8941224ff35ef9857e6d357ca37d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 30 Oct 2016 15:38:51 -0600 Subject: [PATCH 267/734] Update some compilation issues --- arch/xtensa/include/esp32/irq.h | 2 +- arch/xtensa/src/common/xtensa.h | 28 ++++--- arch/xtensa/src/common/xtensa_coproc.S | 12 +-- arch/xtensa/src/common/xtensa_dumpstate.c | 8 +- arch/xtensa/src/common/xtensa_int_handlers.S | 2 +- arch/xtensa/src/common/xtensa_irqdispatch.c | 2 +- arch/xtensa/src/common/xtensa_vectors.S | 5 +- arch/xtensa/src/esp32/Make.defs | 8 +- arch/xtensa/src/esp32/esp32_cpu_interrupt.c | 87 ++++++++++++++++++++ arch/xtensa/src/esp32/esp32_cpu_interrupt.h | 62 ++++++++++++++ configs/esp32-core/nsh/defconfig | 2 +- configs/esp32-core/smp/defconfig | 1 - 12 files changed, 192 insertions(+), 27 deletions(-) create mode 100644 arch/xtensa/src/esp32/esp32_cpu_interrupt.c create mode 100644 arch/xtensa/src/esp32/esp32_cpu_interrupt.h diff --git a/arch/xtensa/include/esp32/irq.h b/arch/xtensa/include/esp32/irq.h index a5f521f8b6..98ce3c08db 100644 --- a/arch/xtensa/include/esp32/irq.h +++ b/arch/xtensa/include/esp32/irq.h @@ -322,7 +322,7 @@ #define NR_IRQS (XTENSA_NIRQ_INTERNAL+ESP32_NIRQ_PERIPH+ESP32_NIRQ_GPIO) -/* CPU Interrupts. +/* Xtensa CPU Interrupts. * * Each of the two CPUs (PRO and APP) have 32 interrupts each, of which * 26 can be mapped to peripheral interrupts: diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index 2dce849d85..ad35c34f09 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -110,28 +110,31 @@ /* In the XTENSA model, the state is copied from the stack to the TCB, but * only a referenced is passed to get the state from the TCB. + * + * REVISIT: It would not be too difficult to save only a pointer to the + * state save area in the TCB and thus avoid the copy. */ #define xtensa_savestate(regs) xtensa_copystate(regs, (uint32_t*)CURRENT_REGS) #define xtensa_restorestate(regs) do { CURRENT_REGS = regs; } while (0) +/* Interrupt codes from other CPUs: */ + +#define CPU_INTCODE_PAUSE 0 + /* Register access macros */ -# define getreg8(a) (*(volatile uint8_t *)(a)) -# define putreg8(v,a) (*(volatile uint8_t *)(a) = (v)) -# define getreg16(a) (*(volatile uint16_t *)(a)) -# define putreg16(v,a) (*(volatile uint16_t *)(a) = (v)) -# define getreg32(a) (*(volatile uint32_t *)(a)) -# define putreg32(v,a) (*(volatile uint32_t *)(a) = (v)) +#define getreg8(a) (*(volatile uint8_t *)(a)) +#define putreg8(v,a) (*(volatile uint8_t *)(a) = (v)) +#define getreg16(a) (*(volatile uint16_t *)(a)) +#define putreg16(v,a) (*(volatile uint16_t *)(a) = (v)) +#define getreg32(a) (*(volatile uint32_t *)(a)) +#define putreg32(v,a) (*(volatile uint32_t *)(a) = (v)) /**************************************************************************** * Public Types ****************************************************************************/ -#ifndef __ASSEMBLY__ -typedef void (*xtensa_vector_t)(void); -#endif - /**************************************************************************** * Public Data ****************************************************************************/ @@ -253,7 +256,10 @@ void xtensa_panic(int xptcode, uint32_t *regs) noreturn_function; /* Software interrupt handler */ -int xtensa_swint(int irq, FAR void *context); +#ifdef CONFIG_SMP +int xtensa_cpu_interrupt(int cpu, int intcode); +void xtensa_pause_handler(void); +#endif /* Synchronous context switching */ diff --git a/arch/xtensa/src/common/xtensa_coproc.S b/arch/xtensa/src/common/xtensa_coproc.S index 2bcba0185f..c29e23a33b 100644 --- a/arch/xtensa/src/common/xtensa_coproc.S +++ b/arch/xtensa/src/common/xtensa_coproc.S @@ -256,9 +256,9 @@ xtensa_coproc_savestate: /* Restore a13-15 and return */ - 132i a13, sp, LOCAL_OFFSET(1) - 132i a14, sp, LOCAL_OFFSET(2) - 132i a15, sp, LOCAL_OFFSET(3) + l32i a13, sp, LOCAL_OFFSET(1) + l32i a14, sp, LOCAL_OFFSET(2) + l32i a15, sp, LOCAL_OFFSET(3) RET(16) @@ -443,9 +443,9 @@ xtensa_coproc_restorestate: /* Restore a13-15 and return */ - 132i a13, sp, LOCAL_OFFSET(1) - 132i a14, sp, LOCAL_OFFSET(2) - 132i a15, sp, LOCAL_OFFSET(3) + l32i a13, sp, LOCAL_OFFSET(1) + l32i a14, sp, LOCAL_OFFSET(2) + l32i a15, sp, LOCAL_OFFSET(3) RET(16) diff --git a/arch/xtensa/src/common/xtensa_dumpstate.c b/arch/xtensa/src/common/xtensa_dumpstate.c index b1afe927fc..975993af62 100644 --- a/arch/xtensa/src/common/xtensa_dumpstate.c +++ b/arch/xtensa/src/common/xtensa_dumpstate.c @@ -68,7 +68,13 @@ static inline uint32_t xtensa_getsp(void) { register uint32_t sp; -#warning Missing logic + + __asm__ __volatile__ + ( + "mov %0, sp\n" + : "=r" (sp) + ); + return sp; } diff --git a/arch/xtensa/src/common/xtensa_int_handlers.S b/arch/xtensa/src/common/xtensa_int_handlers.S index db358ff734..c8dc0c4569 100644 --- a/arch/xtensa/src/common/xtensa_int_handlers.S +++ b/arch/xtensa/src/common/xtensa_int_handlers.S @@ -284,7 +284,7 @@ _xtensa_level1_handler: /* Restore only level-specific regs (the rest were already restored) */ l32i a0, sp, (4 * REG_PS) /* Retrieve interruptee's PS */ - wsr a0, EPS_1 + wsr a0, PS l32i a0, sp, (4 * REG_PC) /* Retrieve interruptee's PC */ wsr a0, EPC_1 l32i a0, sp, (4 * REG_A0) /* Retrieve interruptee's A0 */ diff --git a/arch/xtensa/src/common/xtensa_irqdispatch.c b/arch/xtensa/src/common/xtensa_irqdispatch.c index 9ce5bba087..e2ce51f29e 100644 --- a/arch/xtensa/src/common/xtensa_irqdispatch.c +++ b/arch/xtensa/src/common/xtensa_irqdispatch.c @@ -86,7 +86,7 @@ uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs) irq_dispatch(irq, regs); -#if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV) +#if XCHAL_CP_NUM > 0 || defined(CONFIG_ARCH_ADDRENV) /* Check for a context switch. If a context switch occurred, then * CURRENT_REGS will have a different value than it did on entry. */ diff --git a/arch/xtensa/src/common/xtensa_vectors.S b/arch/xtensa/src/common/xtensa_vectors.S index 5f5c16248b..42158964e4 100644 --- a/arch/xtensa/src/common/xtensa_vectors.S +++ b/arch/xtensa/src/common/xtensa_vectors.S @@ -38,6 +38,7 @@ #include +#include #include #include @@ -272,7 +273,7 @@ _double_exception_vector: mov a0, sp /* sp == a1 */ addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ - rsr a0, EPS_1 /* Save interruptee's PS -- REVISIT */ + rsr a0, EPS /* Save interruptee's PS -- REVISIT */ s32i a0, sp, (4 * REG_PS) rsr a0, DEPC /* Save interruptee's PC */ s32i a0, sp, (4 * REG_PC) @@ -309,7 +310,7 @@ _kernel_exception_vector: mov a0, sp /* sp == a1 */ addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ - rsr a0, EPS_1 /* Save interruptee's PS */ + rsr a0, EPS /* Save interruptee's PS */ s32i a0, sp, (4 * REG_PS) rsr a0, EPC_1 /* Save interruptee's PC */ s32i a0, sp, (4 * REG_PC) diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 3cb7c2b0c6..516d39bebd 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -63,6 +63,10 @@ ifeq ($(CONFIG_SPINLOCK),y) CMN_CSRCS += xtensa_testset.c endif +ifeq ($(CONFIG_SMP),y) + CMN_CSRCS += xtensa_cpu_pause.c +endif + # Use of common/xtensa_etherstub.c is deprecated. The preferred mechanism # is to use CONFIG_NETDEV_LATEINIT=y to suppress the call to # up_netinitialize() in xtensa_initialize.c. Then this stub would not be @@ -85,8 +89,8 @@ CHIP_CSRCS += esp32_start.c esp32_timerisr.c ifeq ($(CONFIG_SMP),y) CHIP_ASRCS = esp32_cpuindex.S -#CMN_CSRCS += esp32_cpustart.c esp32_cpupause.c esp32_cpuidlestack.c -CMN_CSRCS += esp32_cpustart.c +CMN_CSRCS += esp32_cpustart.c esp32_cpu_interrupt.c +#CMN_CSRCS += esp32_cpuidlestack.c endif ifeq ($(CONFIG_ESP32_UART),y) diff --git a/arch/xtensa/src/esp32/esp32_cpu_interrupt.c b/arch/xtensa/src/esp32/esp32_cpu_interrupt.c new file mode 100644 index 0000000000..981fd76f4e --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_cpu_interrupt.c @@ -0,0 +1,87 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_cpu_interrupt.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt > + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "xtensa.h" + +#ifdef CONFIG_SMP + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_cpu_interrupt + * + * Description: + * Called to handle the CPU0-4 interrupts. + * + ****************************************************************************/ + +int esp32_cpu_interrupt(int irq, FAR void *context) +{ + uint32_t *regs = (uint32_t *)context; + int intcode; + + DEBUGASSERT(regs != NULL); + intcode = regs[REG_A2]; + + /* Dispatch the inter-CPU interrupt based on the intcode value */ + + switch (intcode) + { + case CPU_INTCODE_PAUSE: + xtensa_pause_handler(); + break; + + default: + DEBUGPANIC(); + break; + } + + return OK; +} + +#endif /* CONFIG_SMP */ diff --git a/arch/xtensa/src/esp32/esp32_cpu_interrupt.h b/arch/xtensa/src/esp32/esp32_cpu_interrupt.h new file mode 100644 index 0000000000..d46f162b2b --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_cpu_interrupt.h @@ -0,0 +1,62 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_cpu_interrupt.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt > + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_CPU_INTERRUPT_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_CPU_INTERRUPT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_SMP + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_cpu_interrupt + * + * Description: + * Called to handle the CPU0-4 interrupts. + * + ****************************************************************************/ + +int esp32_cpu_interrupt(int irq, FAR void *context); + +#endif /* CONFIG_SMP */ +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_CPU_INTERRUPT_H */ diff --git a/configs/esp32-core/nsh/defconfig b/configs/esp32-core/nsh/defconfig index b163053233..96bb1c7bd3 100644 --- a/configs/esp32-core/nsh/defconfig +++ b/configs/esp32-core/nsh/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH_CHIP="esp32" # CONFIG_SERIAL_TERMIOS is not set CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_FAMILY_LX6=y -CONFIG_XTENSA_CALL0_ABI=y # CONFIG_XTENSA_USE_OVLY is not set CONFIG_XTENSA_CP_INITSET=0x0001 CONFIG_ESP32_UART=y @@ -203,6 +202,7 @@ CONFIG_PREALLOC_TIMERS=4 # # Tasks and Scheduling # +# CONFIG_SMP is not set # CONFIG_INIT_NONE is not set CONFIG_INIT_ENTRYPOINT=y # CONFIG_INIT_FILEPATH is not set diff --git a/configs/esp32-core/smp/defconfig b/configs/esp32-core/smp/defconfig index 104c7c89ba..403a5e3c8d 100644 --- a/configs/esp32-core/smp/defconfig +++ b/configs/esp32-core/smp/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH_CHIP="esp32" # CONFIG_SERIAL_TERMIOS is not set CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_FAMILY_LX6=y -CONFIG_XTENSA_CALL0_ABI=y # CONFIG_XTENSA_USE_OVLY is not set CONFIG_XTENSA_CP_INITSET=0x0001 CONFIG_ESP32_UART=y -- GitLab From 6ff833e56eb43ba941665773b88f5d43a7f52d32 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 30 Oct 2016 15:40:42 -0600 Subject: [PATCH 268/734] Forgot to add a file in the last commit --- arch/xtensa/src/common/xtensa_cpupause.c | 232 +++++++++++++++++++++++ 1 file changed, 232 insertions(+) create mode 100644 arch/xtensa/src/common/xtensa_cpupause.c diff --git a/arch/xtensa/src/common/xtensa_cpupause.c b/arch/xtensa/src/common/xtensa_cpupause.c new file mode 100644 index 0000000000..e13e3ea3e8 --- /dev/null +++ b/arch/xtensa/src/common/xtensa_cpupause.c @@ -0,0 +1,232 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_cpupause.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "xtensa.h" +#include "sched/sched.h" + +#ifdef CONFIG_SMP + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_cpu_wait[CONFIG_SMP_NCPUS]; +static spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_pause_handler + * + * Description: + * This is the handler for CPU_INTCODE_PAUSE CPU interrupt. This + * implements up_cpu_pause() by performing the following operations: + * + * 1. The current task state at the head of the current assigned task + * list was saved when the interrupt was entered. + * 2. This function simply waits on a spinlock, then returns. + * 3. Upon return, the interrupt exit logic will restore the state of + * the new task at the head of the ready to run list. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void xtensa_pause_handler(void) +{ + FAR struct tcb_s *otcb = this_task(); + FAR struct tcb_s *ntcb; + int cpu = up_cpu_index(); + + /* Update scheduler parameters */ + + sched_suspend_scheduler(otcb); + + /* Copy the CURRENT_REGS into the OLD TCB (otcb). The co-processor state + * will be saved as part of the return from xtensa_irq_dispatch(). + */ + + xtensa_savestate(otcb->xcp.regs); + + /* Wait for the spinlock to be released */ + + spin_unlock(&g_cpu_paused[cpu]); + spin_lock(&g_cpu_wait[cpu]); + + /* Upon return, we will restore the exception context of the new TCB + * (ntcb) at the head of the ready-to-run task list. + */ + + ntcb = this_task(); + + /* Reset scheduler parameters */ + + sched_resume_scheduler(ntcb); + + /* Did the task at the head of the list change? */ + + if (otcb != ntcb) + { + /* Set CURRENT_REGS to the context save are of the new TCB to start. + * This will inform the return-from-interrupt logic that a context + * switch must be performed. + */ + + xtensa_restorestate(ntcb->xcp.regs); + } + + spin_unlock(&g_cpu_wait[cpu]); +} + +/**************************************************************************** + * Name: up_cpu_pause + * + * Description: + * Save the state of the current task at the head of the + * g_assignedtasks[cpu] task list and then pause task execution on the + * CPU. + * + * This function is called by the OS when the logic executing on one CPU + * needs to modify the state of the g_assignedtasks[cpu] list for another + * CPU. + * + * Input Parameters: + * cpu - The index of the CPU to be stopped. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +int up_cpu_pause(int cpu) +{ + int ret; + + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu()); + + /* Take the both spinlocks. The g_cpu_wait spinlock will prevent the SGI2 + * handler from returning until up_cpu_resume() is called; g_cpu_paused + * is a handshake that will prefent this function from returning until + * the CPU is actually paused. + */ + + DEBUGASSERT(!spin_islocked(&g_cpu_wait[cpu]) && + !spin_islocked(&g_cpu_paused[cpu])); + + spin_lock(&g_cpu_wait[cpu]); + spin_lock(&g_cpu_paused[cpu]); + + /* Execute SGI2 */ + + ret = xtensa_cpu_interrupt(cpu, CPU_INTCODE_PAUSE); + if (ret < 0) + { + /* What happened? Unlock the g_cpu_wait spinlock */ + + spin_unlock(&g_cpu_wait[cpu]); + } + else + { + /* Wait for the other CPU to unlock g_cpu_paused meaning that + * it is fully paused and ready for up_cpu_resume(); + */ + + spin_lock(&g_cpu_paused[cpu]); + } + + spin_unlock(&g_cpu_paused[cpu]); + + /* On successful return g_cpu_wait will be locked, the other CPU will be + * spinninf on g_cpu_wait and will not continue until g_cpu_resume() is + * called. g_cpu_paused will be unlocked in any case. + */ + + return ret; +} + +/**************************************************************************** + * Name: up_cpu_resume + * + * Description: + * Restart the cpu after it was paused via up_cpu_pause(), restoring the + * state of the task at the head of the g_assignedtasks[cpu] list, and + * resume normal tasking. + * + * This function is called after up_cpu_pause in order resume operation of + * the CPU after modifying its g_assignedtasks[cpu] list. + * + * Input Parameters: + * cpu - The index of the CPU being re-started. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +int up_cpu_resume(int cpu) +{ + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu()); + + /* Release the spinlock. Releasing the spinlock will cause the SGI2 + * handler on 'cpu' to continue and return from interrupt to the newly + * established thread. + */ + + DEBUGASSERT(spin_islocked(&g_cpu_wait[cpu]) && + !spin_islocked(&g_cpu_paused[cpu])); + + spin_unlock(&g_cpu_wait[cpu]); + return OK; +} + +#endif /* CONFIG_SMP */ -- GitLab From 63d5ab5b67310e2ef9b847626993cbaf326a2e70 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 30 Oct 2016 16:15:04 -0600 Subject: [PATCH 269/734] Add logic to attach inter-CPU interrupts. Fix some compilation errors. --- arch/xtensa/include/xtensa/core.h | 13 ------- arch/xtensa/src/esp32/Make.defs | 2 +- arch/xtensa/src/esp32/esp32_clockconfig.c | 2 +- arch/xtensa/src/esp32/esp32_cpu_interrupt.c | 18 ++++++++- arch/xtensa/src/esp32/esp32_cpustart.c | 41 ++++++++++++++++++++- arch/xtensa/src/esp32/esp32_irq.c | 39 +++++++++++++++++++- arch/xtensa/src/esp32/esp32_start.c | 2 - arch/xtensa/src/esp32/esp32_timerisr.c | 2 +- 8 files changed, 96 insertions(+), 23 deletions(-) diff --git a/arch/xtensa/include/xtensa/core.h b/arch/xtensa/include/xtensa/core.h index 77ecb5aa76..b138aa558a 100644 --- a/arch/xtensa/include/xtensa/core.h +++ b/arch/xtensa/include/xtensa/core.h @@ -45,22 +45,9 @@ * Included Files ****************************************************************************/ -/* Configuration independent definitions: */ - -#warning REVISIT: Missing header files: -//#include -//#include - -/* Configuration specific definitions: */ - #include -//#include #include -#ifdef __ASSEMBLY__ -//# include -#endif - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 516d39bebd..2598bf3d6d 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -64,7 +64,7 @@ ifeq ($(CONFIG_SPINLOCK),y) endif ifeq ($(CONFIG_SMP),y) - CMN_CSRCS += xtensa_cpu_pause.c + CMN_CSRCS += xtensa_cpupause.c endif # Use of common/xtensa_etherstub.c is deprecated. The preferred mechanism diff --git a/arch/xtensa/src/esp32/esp32_clockconfig.c b/arch/xtensa/src/esp32/esp32_clockconfig.c index 88f3351cb4..4f841b11be 100644 --- a/arch/xtensa/src/esp32/esp32_clockconfig.c +++ b/arch/xtensa/src/esp32/esp32_clockconfig.c @@ -77,7 +77,7 @@ enum xtal_freq_e void esp32_clockconfig(void) { #ifdef CONFIG_SUPPRESS_CLOCK_CONFIG -# warning WARNING: Clock coniguration disabled +# warning WARNING: Clock configuration disabled #else uint32_t freq_mhz = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ; enum xtal_freq_e freq; diff --git a/arch/xtensa/src/esp32/esp32_cpu_interrupt.c b/arch/xtensa/src/esp32/esp32_cpu_interrupt.c index 981fd76f4e..93315163ed 100644 --- a/arch/xtensa/src/esp32/esp32_cpu_interrupt.c +++ b/arch/xtensa/src/esp32/esp32_cpu_interrupt.c @@ -39,8 +39,10 @@ #include +#include #include #include +#include #include @@ -56,7 +58,7 @@ * Name: esp32_cpu_interrupt * * Description: - * Called to handle the CPU0-4 interrupts. + * Called to handle the CPU0/1 interrupts. * ****************************************************************************/ @@ -84,4 +86,18 @@ int esp32_cpu_interrupt(int irq, FAR void *context) return OK; } +/**************************************************************************** + * Name: xtensa_cpu_interrupt + * + * Description: + * Called to trigger a CPU interrupt + * + ****************************************************************************/ + +int xtensa_cpu_interrupt(int cpu, int intcode) +{ +#warning Missing logic -- How do we do this? + return -ENOSYS; +} + #endif /* CONFIG_SMP */ diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c index 5b17abb0f9..d471525a3b 100644 --- a/arch/xtensa/src/esp32/esp32_cpustart.c +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -52,6 +52,7 @@ #include "chip/esp32_dport.h" #include "esp32_region.h" #include "esp32_cpuint.h" +#include "esp32_cpu_interrupt.h" #ifdef CONFIG_SMP @@ -99,6 +100,35 @@ static inline void xtensa_disable_all(void) ); } +/**************************************************************************** + * Name: xtensa_attach_cpu_interrupt + ****************************************************************************/ + +#ifdef CONFIG_SMP +static inline void xtensa_attach_cpu_interrupt(void) +{ + int cpuint; + + /* Allocate a level-sensitive, priority 1 CPU interrupt for the UART */ + + cpuint = esp32_alloc_levelint(1); + DEBUGASSERT(cpuint >= 0); + + /* Connect all CPU peripheral source to allocated CPU interrupt */ + + up_disable_irq(cpuint); + esp32_attach_peripheral(1, ESP32_PERIPH_CPU_CPU0, cpuint); + + /* Attach the inter-CPU interrupt. */ + + (void)irq_attach(ESP32_IRQ_CPU_CPU0, (xcpt_t)esp32_cpu_interrupt); + + /* Enable the inter 0 CPU interrupts. */ + + up_enable_irq(cpuint); +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -148,7 +178,13 @@ int xtensa_start_handler(int irq, FAR void *context) xtensa_disable_all(); -#warning REVISIT: Do we need to disable co-processors here? + /* Attach and emable internal interrupts */ + +#ifdef CONFIG_SMP + /* Attach and enable the inter-CPU interrupt */ + + xtensa_attach_cpu_interrupt(); +#endif /* Detach all peripheral sources APP CPU interrupts */ @@ -243,8 +279,9 @@ int up_cpu_start(int cpu) } sem_destroy(&g_appcpu_interlock); - return OK; } + + return OK; } #endif /* CONFIG_SMP */ diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c index c407b991e8..13792b0c48 100644 --- a/arch/xtensa/src/esp32/esp32_irq.c +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -48,6 +48,7 @@ #include "xtensa.h" #include "esp32_cpuint.h" +#include "esp32_cpu_interrupt.h" /**************************************************************************** * Public Data @@ -111,6 +112,35 @@ static inline void xtensa_disable_all(void) ); } +/**************************************************************************** + * Name: xtensa_attach_cpu_interrupt + ****************************************************************************/ + +#ifdef CONFIG_SMP +static inline void xtensa_attach_cpu_interrupt(void) +{ + int cpuint; + + /* Allocate a level-sensitive, priority 1 CPU interrupt for the UART */ + + cpuint = esp32_alloc_levelint(1); + DEBUGASSERT(cpuint >= 0); + + /* Connect all CPU peripheral source to allocated CPU interrupt */ + + up_disable_irq(cpuint); + esp32_attach_peripheral(0, ESP32_PERIPH_CPU_CPU1, cpuint); + + /* Attach the inter-CPU interrupt. */ + + (void)irq_attach(ESP32_IRQ_CPU_CPU1, (xcpt_t)esp32_cpu_interrupt); + + /* Enable the inter 0 CPU interrupt. */ + + up_enable_irq(cpuint); +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -140,8 +170,13 @@ void xtensa_irq_initialize(void) #warning Missing logic #endif - /* Attach all processor exceptions */ -#warning Missing logic + /* Attach and emable internal interrupts */ + +#ifdef CONFIG_SMP + /* Attach and enable the inter-CPU interrupt */ + + xtensa_attach_cpu_interrupt(); +#endif esp32_irq_dump("initial", NR_IRQS); diff --git a/arch/xtensa/src/esp32/esp32_start.c b/arch/xtensa/src/esp32/esp32_start.c index 409bcf8813..a468e83a9c 100644 --- a/arch/xtensa/src/esp32/esp32_start.c +++ b/arch/xtensa/src/esp32/esp32_start.c @@ -85,8 +85,6 @@ void IRAM_ATTR __start(void) memset(&_sbss, 0, (&_ebss - &_sbss) * sizeof(_sbss)); -#warning REVISIT: Do we need to disable co-processors here? - /* Make sure that the APP_CPU is disabled for now */ regval = getreg32(DPORT_APPCPU_CTRL_B_REG); diff --git a/arch/xtensa/src/esp32/esp32_timerisr.c b/arch/xtensa/src/esp32/esp32_timerisr.c index 3d031dc776..90ba8ecaae 100644 --- a/arch/xtensa/src/esp32/esp32_timerisr.c +++ b/arch/xtensa/src/esp32/esp32_timerisr.c @@ -195,7 +195,7 @@ void xtensa_timer_initialize(void) * attach any peripheral ID to the dedicated CPU interrupt. */ - /* Attach the timer interrupt vector */ + /* Attach the timer interrupt */ (void)irq_attach(XTENSA_IRQ_TIMER0, (xcpt_t)esp32_timerisr); -- GitLab From a787a99071fbfd8ca3ea0834905c8299baa08952 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 31 Oct 2016 08:29:28 -0600 Subject: [PATCH 270/734] ESP32: Add inter-cpu interrupts --- arch/xtensa/include/esp32/tie.h | 4 +- arch/xtensa/src/common/xtensa.h | 5 +- arch/xtensa/src/common/xtensa_assert.c | 96 ++++----- arch/xtensa/src/common/xtensa_cpupause.c | 2 +- arch/xtensa/src/esp32/Make.defs | 2 +- arch/xtensa/src/esp32/esp32_cpu_interrupt.c | 103 --------- arch/xtensa/src/esp32/esp32_cpustart.c | 10 +- .../src/esp32/esp32_intercpu_interrupt.c | 199 ++++++++++++++++++ ...interrupt.h => esp32_intercpu_interrupt.h} | 15 +- arch/xtensa/src/esp32/esp32_irq.c | 10 +- configs/esp32-core/README.txt | 34 +++ 11 files changed, 304 insertions(+), 176 deletions(-) delete mode 100644 arch/xtensa/src/esp32/esp32_cpu_interrupt.c create mode 100644 arch/xtensa/src/esp32/esp32_intercpu_interrupt.c rename arch/xtensa/src/esp32/{esp32_cpu_interrupt.h => esp32_intercpu_interrupt.h} (84%) diff --git a/arch/xtensa/include/esp32/tie.h b/arch/xtensa/include/esp32/tie.h index 8bc24b342d..cd72bfc934 100644 --- a/arch/xtensa/include/esp32/tie.h +++ b/arch/xtensa/include/esp32/tie.h @@ -75,8 +75,8 @@ /* Total save area for optional and custom state (NCP + CPn): */ -#define XCHAL_TOTAL_SA_SIZE 128 /* with 16-byte align padding */ -#define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */ +#define XCHAL_TOTAL_SA_SIZE 128 /* With 16-byte align padding */ +#define XCHAL_TOTAL_SA_ALIGN 4 /* Actual minimum alignment */ /* Detailed contents of save areas. * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index ad35c34f09..e6167a7f83 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -120,7 +120,8 @@ /* Interrupt codes from other CPUs: */ -#define CPU_INTCODE_PAUSE 0 +#define CPU_INTCODE_NONE 0 +#define CPU_INTCODE_PAUSE 1 /* Register access macros */ @@ -257,7 +258,7 @@ void xtensa_panic(int xptcode, uint32_t *regs) noreturn_function; /* Software interrupt handler */ #ifdef CONFIG_SMP -int xtensa_cpu_interrupt(int cpu, int intcode); +int xtensa_intercpu_interrupt(int tocpu, int intcode); void xtensa_pause_handler(void); #endif diff --git a/arch/xtensa/src/common/xtensa_assert.c b/arch/xtensa/src/common/xtensa_assert.c index 41adf94a48..4fb0ef3bc1 100644 --- a/arch/xtensa/src/common/xtensa_assert.c +++ b/arch/xtensa/src/common/xtensa_assert.c @@ -67,6 +67,31 @@ * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: assert_tracecallback + ****************************************************************************/ + +#ifdef CONFIG_ARCH_USBDUMP +static int usbtrace_syslog(FAR const char *fmt, ...) +{ + va_list ap; + int ret; + + /* Let vsyslog do the real work */ + + va_start(ap, fmt); + ret = vsyslog(LOG_EMERG, fmt, ap); + va_end(ap); + return ret; +} + +static int assert_tracecallback(FAR struct usbtrace_s *trace, FAR void *arg) +{ + usbtrace_trprintf(usbtrace_syslog, trace->event, trace->value); + return 0; +} +#endif + /**************************************************************************** * Name: xtensa_assert ****************************************************************************/ @@ -74,10 +99,28 @@ static void xtensa_assert(int errorcode) noreturn_function; static void xtensa_assert(int errorcode) { + /* Dump the processor state */ + + xtensa_dumpstate(); + +#ifdef CONFIG_ARCH_USBDUMP + /* Dump USB trace data */ + + (void)usbtrace_enumerate(assert_tracecallback, NULL); +#endif + +#ifdef CONFIG_BOARD_CRASHDUMP + /* Perform board-specific crash dump */ + + board_crashdump(up_getsp(), this_task(), filename, lineno); +#endif + /* Are we in an interrupt handler or the idle task? */ if (CURRENT_REGS || this_task()->pid == 0) { + /* Blink the LEDs forever */ + (void)up_irq_save(); for (; ; ) { @@ -91,35 +134,12 @@ static void xtensa_assert(int errorcode) } else { + /* Assertions in other contexts only cause the thread to exit */ + exit(errorcode); } } -/**************************************************************************** - * Name: assert_tracecallback - ****************************************************************************/ - -#ifdef CONFIG_ARCH_USBDUMP -static int usbtrace_syslog(FAR const char *fmt, ...) -{ - va_list ap; - int ret; - - /* Let vsyslog do the real work */ - - va_start(ap, fmt); - ret = vsyslog(LOG_EMERG, fmt, ap); - va_end(ap); - return ret; -} - -static int assert_tracecallback(FAR struct usbtrace_s *trace, FAR void *arg) -{ - usbtrace_trprintf(usbtrace_syslog, trace->event, trace->value); - return 0; -} -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -144,18 +164,6 @@ void up_assert(const uint8_t *filename, int lineno) filename, lineno); #endif - xtensa_dumpstate(); - -#ifdef CONFIG_ARCH_USBDUMP - /* Dump USB trace data */ - - (void)usbtrace_enumerate(assert_tracecallback, NULL); -#endif - -#ifdef CONFIG_BOARD_CRASHDUMP - board_crashdump(up_getsp(), this_task(), filename, lineno); -#endif - xtensa_assert(EXIT_FAILURE); } @@ -179,17 +187,5 @@ void xtensa_panic(int xptcode, uint32_t *regs) _alert("Unhandled Exception %d\n", xptcode); #endif - xtensa_dumpstate(); - -#ifdef CONFIG_ARCH_USBDUMP - /* Dump USB trace data */ - - (void)usbtrace_enumerate(assert_tracecallback, NULL); -#endif - -#ifdef CONFIG_BOARD_CRASHDUMP - board_crashdump(up_getsp(), this_task(), filename, lineno); -#endif - - xtensa_assert(EXIT_FAILURE); + xtensa_assert(EXIT_FAILURE); /* Should not return */ } diff --git a/arch/xtensa/src/common/xtensa_cpupause.c b/arch/xtensa/src/common/xtensa_cpupause.c index e13e3ea3e8..46bac69bbd 100644 --- a/arch/xtensa/src/common/xtensa_cpupause.c +++ b/arch/xtensa/src/common/xtensa_cpupause.c @@ -168,7 +168,7 @@ int up_cpu_pause(int cpu) /* Execute SGI2 */ - ret = xtensa_cpu_interrupt(cpu, CPU_INTCODE_PAUSE); + ret = xtensa_intercpu_interrupt(cpu, CPU_INTCODE_PAUSE); if (ret < 0) { /* What happened? Unlock the g_cpu_wait spinlock */ diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 2598bf3d6d..d16874c4bc 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -89,7 +89,7 @@ CHIP_CSRCS += esp32_start.c esp32_timerisr.c ifeq ($(CONFIG_SMP),y) CHIP_ASRCS = esp32_cpuindex.S -CMN_CSRCS += esp32_cpustart.c esp32_cpu_interrupt.c +CMN_CSRCS += esp32_cpustart.c esp32_intercpu_interrupt.c #CMN_CSRCS += esp32_cpuidlestack.c endif diff --git a/arch/xtensa/src/esp32/esp32_cpu_interrupt.c b/arch/xtensa/src/esp32/esp32_cpu_interrupt.c deleted file mode 100644 index 93315163ed..0000000000 --- a/arch/xtensa/src/esp32/esp32_cpu_interrupt.c +++ /dev/null @@ -1,103 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32/esp32_cpu_interrupt.c - * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt > - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include "xtensa.h" - -#ifdef CONFIG_SMP - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32_cpu_interrupt - * - * Description: - * Called to handle the CPU0/1 interrupts. - * - ****************************************************************************/ - -int esp32_cpu_interrupt(int irq, FAR void *context) -{ - uint32_t *regs = (uint32_t *)context; - int intcode; - - DEBUGASSERT(regs != NULL); - intcode = regs[REG_A2]; - - /* Dispatch the inter-CPU interrupt based on the intcode value */ - - switch (intcode) - { - case CPU_INTCODE_PAUSE: - xtensa_pause_handler(); - break; - - default: - DEBUGPANIC(); - break; - } - - return OK; -} - -/**************************************************************************** - * Name: xtensa_cpu_interrupt - * - * Description: - * Called to trigger a CPU interrupt - * - ****************************************************************************/ - -int xtensa_cpu_interrupt(int cpu, int intcode) -{ -#warning Missing logic -- How do we do this? - return -ENOSYS; -} - -#endif /* CONFIG_SMP */ diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c index d471525a3b..6fe42912eb 100644 --- a/arch/xtensa/src/esp32/esp32_cpustart.c +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -52,7 +52,7 @@ #include "chip/esp32_dport.h" #include "esp32_region.h" #include "esp32_cpuint.h" -#include "esp32_cpu_interrupt.h" +#include "esp32_intercpu_interrupt.h" #ifdef CONFIG_SMP @@ -101,11 +101,11 @@ static inline void xtensa_disable_all(void) } /**************************************************************************** - * Name: xtensa_attach_cpu_interrupt + * Name: xtensa_attach_fromcpu0_interrupt ****************************************************************************/ #ifdef CONFIG_SMP -static inline void xtensa_attach_cpu_interrupt(void) +static inline void xtensa_attach_fromcpu0_interrupt(void) { int cpuint; @@ -121,7 +121,7 @@ static inline void xtensa_attach_cpu_interrupt(void) /* Attach the inter-CPU interrupt. */ - (void)irq_attach(ESP32_IRQ_CPU_CPU0, (xcpt_t)esp32_cpu_interrupt); + (void)irq_attach(ESP32_IRQ_CPU_CPU0, (xcpt_t)esp32_fromcpu0_interrupt); /* Enable the inter 0 CPU interrupts. */ @@ -183,7 +183,7 @@ int xtensa_start_handler(int irq, FAR void *context) #ifdef CONFIG_SMP /* Attach and enable the inter-CPU interrupt */ - xtensa_attach_cpu_interrupt(); + xtensa_attach_fromcpu0_interrupt(); #endif /* Detach all peripheral sources APP CPU interrupts */ diff --git a/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c b/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c new file mode 100644 index 0000000000..963e1d5156 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c @@ -0,0 +1,199 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_intercpu_interrupt.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt > + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "xtensa.h" + +#ifdef CONFIG_SMP + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Single parameter passed with the inter-CPU interrupt */ + +static volatile uint8_t g_intcode[CONFIG_SMP_NCPUS]; + +/* Spinlock protects parameter array */ + +static volatile spinlock_t g_intercpu_spin[CONFIG_SMP_NCPUS] = +{ + SP_UNLOCKED, SP_UNLOCKED +}; + +/**************************************************************************** + * Private Function + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_fromcpu_interrupt + * + * Description: + * Common logic called to handle the from CPU0/1 interrupts. + * + ****************************************************************************/ + +static int esp32_fromcpu_interrupt(int fromcpu) +{ + uintptr_t regaddr; + int intcode; + int tocpu; + + DEBUGASSERT(regs != NULL); + + /* Clear the interrupt from the other CPU */ + + regaddr = (fromcpu == 0) ? DPORT_CPU_INTR_FROM_CPU_0_REG : + DPORT_CPU_INTR_FROM_CPU_1_REG; + putreg32(0, regaddr); + + /* Get the the inter-CPU interrupt code */ + + tocpu = up_cpu_index(); + intcode = g_intcode[tocpu]; + g_intcode[tocpu] = CPU_INTCODE_NONE; + + spin_unlock(&g_intercpu_spin[tocpu]); + + /* Dispatch the inter-CPU interrupt based on the intcode value */ + + switch (intcode) + { + case CPU_INTCODE_NONE: + break; + + case CPU_INTCODE_PAUSE: + xtensa_pause_handler(); + break; + + default: + DEBUGPANIC(); + break; + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_fromcpu[0,1]_interrupt + * + * Description: + * Called to handle the from CPU0/1 interrupts. + * + ****************************************************************************/ + +int esp32_fromcpu0_interrupt(int irq, FAR void *context) +{ + return esp32_fromcpu_interrupt(0); +} + +int esp32_fromcpu1_interrupt(int irq, FAR void *context) +{ + return esp32_fromcpu_interrupt(1); +} + +/**************************************************************************** + * Name: xtensa_intercpu_interrupt + * + * Description: + * Called to trigger a CPU interrupt + * + ****************************************************************************/ + +int xtensa_intercpu_interrupt(int tocpu, int intcode) +{ + int fromcpu; + + DEBUGASSERT((unsigned)cpu < CONFIG_SMP_NCPUS && + (unsigned)incode <= UINT8_MAX); + + /* Disable context switching so that some other thread does not attempt to + * take the spinlock on the same CPU. + */ + + sched_lock(); + + /* Make sure that each inter-cpu event is atomic. The spinlock should + * only be locked if we just completed sending an interrupt to this + * CPU but the other CPU has not yet processed it. + */ + + spin_lock(&g_intercpu_spin[tocpu]); + + /* Save the passed parameter. The previous interrupt code should be + * CPU_INTCODE_NONE or we have overrun the other CPU. + */ + + DEBUGASSERT(g_intcode[tocpu] == CPU_INTCODE_NONE); + g_intcode[tocpu] = intcode; + + /* Interrupt the other CPU (tocpu) form this CPU. NOTE: that this logic + * fails in numerous ways if fromcpu == tocpu (for example because non- + * reentrant spinlocks are used). + */ + + fromcpu = up_cpu_index(); + DEBUGASSERT(fromcpu != tocpu); + + if (fromcpu == 0) + { + putreg32(DPORT_CPU_INTR_FROM_CPU_0, DPORT_CPU_INTR_FROM_CPU_0_REG); + } + else + { + putreg32(DPORT_CPU_INTR_FROM_CPU_1, DPORT_CPU_INTR_FROM_CPU_1_REG); + } + + sched_unlock(); + return OK; +} + +#endif /* CONFIG_SMP */ diff --git a/arch/xtensa/src/esp32/esp32_cpu_interrupt.h b/arch/xtensa/src/esp32/esp32_intercpu_interrupt.h similarity index 84% rename from arch/xtensa/src/esp32/esp32_cpu_interrupt.h rename to arch/xtensa/src/esp32/esp32_intercpu_interrupt.h index d46f162b2b..5b2c7eeae7 100644 --- a/arch/xtensa/src/esp32/esp32_cpu_interrupt.h +++ b/arch/xtensa/src/esp32/esp32_intercpu_interrupt.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/esp32/esp32_cpu_interrupt.h + * arch/xtensa/src/esp32/esp32_intercpu_interrupt.h * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt > @@ -33,8 +33,8 @@ * ****************************************************************************/ -#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_CPU_INTERRUPT_H -#define __ARCH_XTENSA_SRC_ESP32_ESP32_CPU_INTERRUPT_H +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_INTERCPU_INTERRUPT_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_INTERCPU_INTERRUPT_H /**************************************************************************** * Included Files @@ -49,14 +49,15 @@ ****************************************************************************/ /**************************************************************************** - * Name: esp32_cpu_interrupt + * Name: esp32_fromcpu[0,1]_interrupt * * Description: - * Called to handle the CPU0-4 interrupts. + * Called to handle the from CPU0/1 interrupts. * ****************************************************************************/ -int esp32_cpu_interrupt(int irq, FAR void *context); +int esp32_fromcpu0_interrupt(int irq, FAR void *context); +int esp32_fromcpu1_interrupt(int irq, FAR void *context); #endif /* CONFIG_SMP */ -#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_CPU_INTERRUPT_H */ +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_INTERCPU_INTERRUPT_H */ diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c index 13792b0c48..fae4687d5a 100644 --- a/arch/xtensa/src/esp32/esp32_irq.c +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -48,7 +48,7 @@ #include "xtensa.h" #include "esp32_cpuint.h" -#include "esp32_cpu_interrupt.h" +#include "esp32_intercpu_interrupt.h" /**************************************************************************** * Public Data @@ -113,11 +113,11 @@ static inline void xtensa_disable_all(void) } /**************************************************************************** - * Name: xtensa_attach_cpu_interrupt + * Name: xtensa_attach_fromcpu1_interrupt ****************************************************************************/ #ifdef CONFIG_SMP -static inline void xtensa_attach_cpu_interrupt(void) +static inline void xtensa_attach_fromcpu1_interrupt(void) { int cpuint; @@ -133,7 +133,7 @@ static inline void xtensa_attach_cpu_interrupt(void) /* Attach the inter-CPU interrupt. */ - (void)irq_attach(ESP32_IRQ_CPU_CPU1, (xcpt_t)esp32_cpu_interrupt); + (void)irq_attach(ESP32_IRQ_CPU_CPU1, (xcpt_t)esp32_fromcpu1_interrupt); /* Enable the inter 0 CPU interrupt. */ @@ -175,7 +175,7 @@ void xtensa_irq_initialize(void) #ifdef CONFIG_SMP /* Attach and enable the inter-CPU interrupt */ - xtensa_attach_cpu_interrupt(); + xtensa_attach_fromcpu1_interrupt(); #endif esp32_irq_dump("initial", NR_IRQS); diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index f823864307..1f2d6e2be5 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -21,6 +21,7 @@ Contents o ESP32 Toolchain o Serial Console o Buttons and LEDs + o SMP o Configurations STATUS @@ -100,6 +101,39 @@ Buttons and LEDs There are several on-board LEDs for that indicate the presence of power and USB activity. None of these are available for use by sofware. +SMP +=== + + The ESP32 has 2 CPUs. Support is included for testing an SMP configuration. + That configuration is still not yet ready for usage but can be enabled with + the following configuration settings: + + RTOS Features -> Tasks and Scheduling + CONFIG_SPINLOCK=y + CONFIG_SMP=y + CONFIG_SMP_NCPUS=2 + CONFIG_SMP_IDLETHREAD_STACKSIZE=2048 + + Open Issues: + + 1. Currently all device interrupts are handled on the PRO CPU only. Critical + sections will attempt to disable interrupts but will now disable interrupts + only on the current CPU (which may not be CPU0). Perhaps that should be a + spinlock to prohibit execution of interrupts on CPU0 when other CPUs are in + a critical section? + + 2. Cache Issues. I have not though about this yet, but certainly caching is + an issue in an SMP system: + + - Cache coherency. Are there separate caches for each CPU? Or a single + shared cache? If the are separate then keep the caches coherent will + be an issue. + - Caching MAY interfere with spinlocks as they are currently implemented. + Waiting on a cached copy of the spinlock may result in a hang or a + failure to wait. + + 3. Assertions. On a fatal assertions, other CPUs need to be stopped. + Configurations ============== -- GitLab From a8e3f79494cea4b995f95d1047f78bd3b604f2f7 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 31 Oct 2016 12:04:52 -0600 Subject: [PATCH 271/734] Xtensa/ESP32: Add User Exception handler --- arch/xtensa/include/esp32/irq.h | 18 +- arch/xtensa/src/common/xtensa.h | 14 + arch/xtensa/src/common/xtensa_assert.c | 123 ++++- arch/xtensa/src/common/xtensa_int_handlers.S | 108 ++-- arch/xtensa/src/common/xtensa_user_handler.S | 480 ++++++++++++++++++ arch/xtensa/src/common/xtensa_vectors.S | 21 +- arch/xtensa/src/common/xtensa_window_vector.S | 10 +- configs/esp32-core/scripts/esp32_common.ld | 8 +- 8 files changed, 722 insertions(+), 60 deletions(-) create mode 100644 arch/xtensa/src/common/xtensa_user_handler.S diff --git a/arch/xtensa/include/esp32/irq.h b/arch/xtensa/include/esp32/irq.h index 98ce3c08db..4c8e6c47ca 100644 --- a/arch/xtensa/include/esp32/irq.h +++ b/arch/xtensa/include/esp32/irq.h @@ -50,19 +50,6 @@ * Pre-processor Definitions ****************************************************************************/ -/* Exception Codes */ - -#define XTENSA_NMI_EXCEPTION 0 -#define XTENSA_DEBUG_EXCEPTION 1 -#define XTENSA_DOUBLE_EXCEPTION 2 -#define XTENSA_KERNEL_EXCEPTION 3 -#define XTENSA_COPROC_EXCEPTION 4 -#define XTENSA_LEVEL2_EXCEPTION 5 -#define XTENSA_LEVEL3_EXCEPTION 6 -#define XTENSA_LEVEL4_EXCEPTION 7 -#define XTENSA_LEVEL5_EXCEPTION 8 -#define XTENSA_LEVEL6_EXCEPTION 9 - /* Interrupt Matrix * * The Interrupt Matrix embedded in the ESP32 independently allocates @@ -204,9 +191,10 @@ #define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */ #define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */ #define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */ +#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */ -#define XTENSA_NIRQ_INTERNAL 3 /* Number of dispatch internal interrupts */ -#define XTENSA_IRQ_FIRSTPERIPH 3 /* First peripheral IRQ number */ +#define XTENSA_NIRQ_INTERNAL 4 /* Number of dispatch internal interrupts */ +#define XTENSA_IRQ_FIRSTPERIPH 4 /* First peripheral IRQ number */ /* IRQ numbers for peripheral interrupts coming throught the Interrupt * Matrix. diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index e6167a7f83..5a5ab2f88c 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -123,6 +123,19 @@ #define CPU_INTCODE_NONE 0 #define CPU_INTCODE_PAUSE 1 +/* Exception Codes that may be received by xtensa_panic(). */ + +#define XTENSA_NMI_EXCEPTION 0 +#define XTENSA_DEBUG_EXCEPTION 1 +#define XTENSA_DOUBLE_EXCEPTION 2 +#define XTENSA_KERNEL_EXCEPTION 3 +#define XTENSA_COPROC_EXCEPTION 4 +#define XTENSA_LEVEL2_EXCEPTION 5 +#define XTENSA_LEVEL3_EXCEPTION 6 +#define XTENSA_LEVEL4_EXCEPTION 7 +#define XTENSA_LEVEL5_EXCEPTION 8 +#define XTENSA_LEVEL6_EXCEPTION 9 + /* Register access macros */ #define getreg8(a) (*(volatile uint8_t *)(a)) @@ -254,6 +267,7 @@ uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs); uint32_t xtensa_enable_cpuint(uint32_t *shadow, uint32_t intmask); uint32_t xtensa_disable_cpuint(uint32_t *shadow, uint32_t intmask); void xtensa_panic(int xptcode, uint32_t *regs) noreturn_function; +void xtensa_user(int exccause, uint32_t *regs) noreturn_function; /* Software interrupt handler */ diff --git a/arch/xtensa/src/common/xtensa_assert.c b/arch/xtensa/src/common/xtensa_assert.c index 4fb0ef3bc1..565e71ff5c 100644 --- a/arch/xtensa/src/common/xtensa_assert.c +++ b/arch/xtensa/src/common/xtensa_assert.c @@ -164,11 +164,30 @@ void up_assert(const uint8_t *filename, int lineno) filename, lineno); #endif + CURRENT_REGS = regs; xtensa_assert(EXIT_FAILURE); } /**************************************************************************** * Name: xtensa_panic + * + * Description: + * PANIC if an unhandled exception is received: + * + * - NMI exception + * - Debug exception + * - Double exception + * - Kernel exception + * - Co-processor exception + * - High priority level2-6 Exception. + * + * Input parameters: + * xcptcode - Identifies the unhandled exception (see include/esp32/irq.h) + * regs - The register save are at the time of the interrupt. + * + * Returned Value: + * Does not return + * ****************************************************************************/ void xtensa_panic(int xptcode, uint32_t *regs) @@ -177,7 +196,7 @@ void xtensa_panic(int xptcode, uint32_t *regs) struct tcb_s *rtcb = this_task(); #endif - /* We get here when a un-dispatch-able, irrecoverable excpetion occurs */ + /* We get here when a un-dispatch-able, irrecoverable exception occurs */ board_autoled_on(LED_ASSERTION); @@ -187,5 +206,107 @@ void xtensa_panic(int xptcode, uint32_t *regs) _alert("Unhandled Exception %d\n", xptcode); #endif + CURRENT_REGS = regs; + xtensa_assert(EXIT_FAILURE); /* Should not return */ + for (; ; ); +} + +/**************************************************************************** + * Name: xtensa_user + * + * Description: + * PANIC if certain User Exceptions are received received. All values for + * EXCCAUSE are listed below (not all generate PANICs): + * + * 0 IllegalInstructionCause + * Illegal instruction + * 1 SyscallCause + * SYSCALL instruction + * 2 InstructionFetchErrorCause + * Processor internal physical address or data error during instruction + * fetch. + * 3 LoadStoreErrorCause + * Processor internal physical address or data error during load or + * store. + * 4 Level1InterruptCause + * Level-1 interrupt as indicated by set level-1 bits in the INTERRUPT + * register. + * 5 AllocaCause + * MOVSP instruction, if caller’s registers are not in the register file. + * 6 IntegerDivideByZeroCause + * QUOS, QUOU, REMS, or REMU divisor operand is zero. + * 7 PCValueErrorCause Next PC Value Illegal + * 8 PrivilegedCause + * Attempt to execute a privileged operation when CRING != 0 + * 9 LoadStoreAlignmentCause + * Load or store to an unaligned address. + * 10..11 Reserved for Cadence + * 12 InstrPIFDataErrorCause + * PIF data error during instruction fetch. + * 13 LoadStorePIFDataErrorCause + * Synchronous PIF data error during LoadStore access. + * 14 InstrPIFAddrErrorCause + * PIF address error during instruction fetch. + * 15 LoadStorePIFAddrErrorCause + * Synchronous PIF address error during LoadStore access. + * 16 InstTLBMissCause + * Error during Instruction TLB refill + * 17 InstTLBMultiHitCause + * Multiple instruction TLB entries matched + * 18 InstFetchPrivilegeCause + * An instruction fetch referenced a virtual address at a ring leve + * less than CRING. + * 19 Reserved for Cadence + * 20 InstFetchProhibitedCause + * An instruction fetch referenced a page mapped with an attribute + * that does not permit instruction fetch. + * 21..23 Reserved for Cadence + * 24 LoadStoreTLBMissCause + * Error during TLB refill for a load or store. + * 25 LoadStoreTLBMultiHitCause + * Multiple TLB entries matched for a load or store. + * 26 LoadStorePrivilegeCause + * A load or store referenced a virtual address at a ring level less + * than CRING. + * 27 Reserved for Cadence + * 28 LoadProhibitedCause + * A load referenced a page mapped with an attribute that does not + * permit loads. + * 29 StoreProhibitedCause + * A store referenced a page mapped with an attribute that does not + * permit stores. + * 30..31 Reserved for Cadence + * 32..39 CoprocessornDisabled + * Coprocessor n instruction when cpn disabled. n varies 0..7 as the + * cause varies 32..39. + * 40..63 Reserved + * + * Input parameters: + * exccause - Identifies the EXCCAUSE of the user exception + * regs - The register save are at the time of the interrupt. + * + * Returned Value: + * Does not return + * + ****************************************************************************/ + +void xtensa_user(int exccause, uint32_t *regs) +{ +#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT) + struct tcb_s *rtcb = this_task(); +#endif + + /* We get here when a un-dispatch-able, irrecoverable exception occurs */ + + board_autoled_on(LED_ASSERTION); + +#if CONFIG_TASK_NAME_SIZE > 0 + _alert("User Exception: EXCCAUSE=%04x task: %s\n", exccause, rtcb->name); +#else + _alert("User Exception: EXCCAUSE=%04x\n", exccause); +#endif + + CURRENT_REGS = regs; xtensa_assert(EXIT_FAILURE); /* Should not return */ + for (; ; ); } diff --git a/arch/xtensa/src/common/xtensa_int_handlers.S b/arch/xtensa/src/common/xtensa_int_handlers.S index c8dc0c4569..6946aa9b17 100644 --- a/arch/xtensa/src/common/xtensa_int_handlers.S +++ b/arch/xtensa/src/common/xtensa_int_handlers.S @@ -109,17 +109,28 @@ * - PS.EXCM = 0, C calling enabled * * Entry Conditions/Side Effects: - * This macro will use registers a0 and a2-a6. The arguments are: - * level - interrupt level - * mask - interrupt bitmask for this level + * level - interrupt level + * mask - interrupt bitmask for this level + * + * Exit Conditions: + * This macro will use registers a0 and a2-a5 and a12. + * a1 - May point to the new thread's SP + * a12 - Points to the register save area (which may not be on the stack). * ****************************************************************************/ .macro dispatch_c_isr level mask + /* Initially the register save area is in SP, but that could change as + * a consequence of context switching. + */ + + mov s12, sp /* a12 = address of save area */ + +._xtensa_dispatch_level&level&: + /* Get mask of pending, enabled interrupts at this level into a2. */ -.L_xt_user_int_&level&: rsr a2, INTENABLE rsr a3, INTERRUPT movi a4, \mask @@ -139,51 +150,64 @@ * area as a parameter (A2). */ - mov a2, sp /* Argument: Top of stack = register save area */ + mov a2, a12 /* Argument: Top of stack = register save area */ #ifdef __XTENSA_CALL0_ABI__ call0 xtensa_int_decode /* Call xtensa_int_decode */ #else call4 xtensa_int_decode /* Call xtensa_int_decode */ #endif - /* On return from xtensa_int_decode, A2 will contain the address of the new + /* On return from xtensa_int_decode, a2 will contain the address of the new * register save area. Usually this would be the same as the current SP. - * But in the event of a context switch, A2 will instead refer to the TCB - * register save area. + * But in the event of a context switch, a2 will instead refer to the TCB + * register save area. This may or may not reside on a stack. */ - beq a2, sp, 3f /* If timer interrupt then skip table */ + beq a2, a12, 3f /* If timer interrupt then skip table */ /* Switch stacks */ - l32i a4, sp, (4 * REG_A1) /* Retrieve stack ptr and replace */ - addi sp, a4, -(4 * XCPTCONTEXT_SIZE) + mov a12, a2 /* Switch to the save area of the new thread */ + l32i a2, a12, (4 * REG_A1) /* Retrieve stack ptr and replace */ + addi sp, a2, -(4 * XCPTCONTEXT_SIZE) 3: - j .L_xt_user_int_&level& /* Check for more interrupts */ + j ._xtensa_dispatch_level&level& /* Check for more interrupts */ 4: .ifeq XT_TIMER_INTPRI - \level - /* Interrupt handler for the RTOS tick timer if at this level. + /* Interrupt handler for the NuttX system timer if at this level. * We'll be reading the interrupt state again after this call - * so no need to preserve any registers except a6 (vpri_mask). + * so no need to preserve any registers except a7 (pointer to + * state save area). */ - mov a12, a6 /* Preserve a6 */ - movi a2, XTENSA_IRQ_TIMER&level& /* Arg 1: IRQ number */ - mov a3, sp /* Arg 2: Top of stack = register save area */ + movi a2, XTENSA_IRQ_TIMER&level& /* Argument 1: IRQ number */ + mov a3, a12 /* Argument 2: Top of stack = register save area */ #ifdef __XTENSA_CALL0_ABI__ call0 xtensa_irq_dispatch /* Call xtensa_int_decode */ #else call4 xtensa_irq_dispatch /* Call xtensa_int_decode */ #endif - mov a6, a12 /* Preserve a6 */ + /* On return from xtensa_irq_dispatch, A2 will contain the address of the new + * register save area. Usually this would be the same as the current SP. + * But in the event of a context switch, A2 will instead refer to the TCB + * register save area. + */ + + beq a2, a12, 5f /* If timer interrupt then skip table */ + + /* Switch stacks */ + + mov a12, a2 /* Switch to the save area of the new thread */ + l32i a2, a12, (4 * REG_A1) /* Retrieve stack ptr and replace */ + addi sp, a2, -(4 * XCPTCONTEXT_SIZE) .endif - j .L_xt_user_int_&level& /* Check for more interrupts */ + j ._xtensa_dispatch_level&level& /* Check for more interrupts */ 5: /* done */ @@ -271,14 +295,17 @@ _xtensa_level1_handler: ps_setup 1 a0 /* Decode and dispatch the interrupt. In the event of an interrupt - * level context dispatch_c_isr() will switch stacks to the new task's - * context save area. + * level context dispatch_c_isr() will (1) switch stacks to the new + * thread's and (2) provide the address of the register state save + * area in a12. NOTE that the state save area may or may not lie + * in the new thread's stack. */ dispatch_c_isr 1 XCHAL_INTLEVEL1_MASK /* Restore registers in preparation to return from interrupt */ + mov a2, a12 /* a2 = address of new state save area */ call0 _xtensa_context_restore /* Restore only level-specific regs (the rest were already restored) */ @@ -352,14 +379,17 @@ _xtensa_level2_handler: ps_setup 2 a0 /* Decode and dispatch the interrupt. In the event of an interrupt - * level context dispatch_c_isr() will switch stacks to the new task's - * context save area. + * level context dispatch_c_isr() will (1) switch stacks to the new + * thread's and (2) provide the address of the register state save + * area in a12. NOTE that the state save area may or may not lie + * in the new thread's stack. */ dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK /* Restore registers in preparation to return from interrupt */ + mov a2, a12 /* a2 = address of new state save area */ call0 _xtensa_context_restore /* Restore only level-specific regs (the rest were already restored) */ @@ -409,14 +439,17 @@ _xtensa_level3_handler: ps_setup 3 a0 /* Decode and dispatch the interrupt. In the event of an interrupt - * level context dispatch_c_isr() will switch stacks to the new task's - * context save area. + * level context dispatch_c_isr() will (1) switch stacks to the new + * thread's and (2) provide the address of the register state save + * area in a12. NOTE that the state save area may or may not lie + * in the new thread's stack. */ dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK /* Restore registers in preparation to return from interrupt */ + mov a2, a12 /* a2 = address of new state save area */ call0 _xtensa_context_restore /* Restore only level-specific regs (the rest were already restored) */ @@ -466,14 +499,17 @@ _xtensa_level4_handler: ps_setup 4 a0 /* Decode and dispatch the interrupt. In the event of an interrupt - * level context dispatch_c_isr() will switch stacks to the new task's - * context save area. + * level context dispatch_c_isr() will (1) switch stacks to the new + * thread's and (2) provide the address of the register state save + * area in a12. NOTE that the state save area may or may not lie + * in the new thread's stack. */ dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK /* Restore registers in preparation to return from interrupt */ + mov a2, a12 /* a2 = address of new state save area */ call0 _xtensa_context_restore /* Restore only level-specific regs (the rest were already restored) */ @@ -523,14 +559,17 @@ _xtensa_level5_handler: ps_setup 5 a0 /* Decode and dispatch the interrupt. In the event of an interrupt - * level context dispatch_c_isr() will switch stacks to the new task's - * context save area. + * level context dispatch_c_isr() will (1) switch stacks to the new + * thread's and (2) provide the address of the register state save + * area in a12. NOTE that the state save area may or may not lie + * in the new thread's stack. */ dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK /* Restore registers in preparation to return from interrupt */ + mov a2, a12 /* a2 = address of new state save area */ call0 _xtensa_context_restore /* Restore only level-specific regs (the rest were already restored) */ @@ -580,14 +619,17 @@ _xtensa_level6_handler: ps_setup 6 a0 /* Decode and dispatch the interrupt. In the event of an interrupt - * level context dispatch_c_isr() will switch stacks to the new task's - * context save area. + * level context dispatch_c_isr() will (1) switch stacks to the new + * thread's and (2) provide the address of the register state save + * area in a12. NOTE that the state save area may or may not lie + * in the new thread's stack. */ dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK /* Restore registers in preparation to return from interrupt */ + mov a2, a12 /* a2 = address of new state save area */ call0 _xtensa_context_restore /* Restore only level-specific regs (the rest were already restored) */ @@ -614,8 +656,8 @@ _xtensa_level6_handler: * * High priority interrupts are by definition those with priorities greater * than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority - * interrupts cannot interact with the RTOS, that is they must save all regs - * they use and not call any RTOS function. + * interrupts cannot interact with NuttX, that is they must save all regs + * they use and not call any NuttX function. * * A further restriction imposed by the Xtensa windowed architecture is that * high priority interrupts must not modify the stack area even logically diff --git a/arch/xtensa/src/common/xtensa_user_handler.S b/arch/xtensa/src/common/xtensa_user_handler.S new file mode 100644 index 0000000000..75776a5eee --- /dev/null +++ b/arch/xtensa/src/common/xtensa_user_handler.S @@ -0,0 +1,480 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_user_handler.S + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * + * Copyright (c) 2006-2015 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + + .file "xtensa_user_handler.S" + +/* NOTES on the use of 'call0' for long jumps instead of 'j': + * + * 1. This file should be assembled with the -mlongcalls option to xt-xcc. + * + * 2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to + * a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the + * distance from the call to the destination. The linker then relaxes + * it back to 'call0 dest' if it determines that dest is within range. + * This allows more flexibility in locating code without the performance + * overhead of the 'l32r' literal data load in cases where the destination + * is in range of 'call0'. There is an additional benefit in that 'call0' + * has a longer range than 'j' due to the target being word-aligned, so + * the 'l32r' sequence is less likely needed. + * + * 3. The use of 'call0' with -mlongcalls requires that register a0 not be + * live at the time of the call, which is always the case for a function + * call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'. + * + * 4. This use of 'call0' is independent of the C function call ABI. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LAZY_COPROC + +/**************************************************************************** + * Assembly Language Macros + ****************************************************************************/ + +/**************************************************************************** + * Macro: ps_setup + * + * Description: + * Set up PS for C, enable interrupts above this level and clear EXCM. + * + * Entry Conditions: + * level - interrupt level + * tmp - scratch register + * + * Side Effects: + * PS and scratch register modified + * + * Assumptions: + * - PS.EXCM = 1, C calling disabled + * + ****************************************************************************/ + + .macro ps_setup level tmp + +#if 0 /* Nested interrupts no yet supported */ +# ifdef __XTENSA_CALL0_ABI__ + /* Disable interrupts at level and below */ + + movi \tmp, PS_INTLEVEL(\level) | PS_UM +# else + movi \tmp, PS_INTLEVEL(\level) | PS_UM | PS_WOE +# endif +#else +# ifdef __XTENSA_CALL0_ABI__ + /* Disable all low- and medium-priority interrupts. Nested are not yet + * supported. + */ + + movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM +# else + movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE +# endif +#endif + + wsr \tmp, PS + rsync + + .endm + +/**************************************************************************** + * Waypoints + ****************************************************************************/ + +/* Insert some waypoints for jumping beyond the signed 8-bit range of + * conditional branch instructions, so the conditional branchces to specific + * exception handlers are not taken in the mainline. Saves some cycles in the + * mainline. + */ + + .section HANDLER_SECTION, "ax" + + .align 4 +_xtensa_to_level1_handler: + call0 _xtensa_level1_handler /* Jump to level1 interrupt handler */ + +#if XCHAL_HAVE_WINDOWED + .align 4 +_xtensa_to_alloca_handler: + call0 _xtensa_alloca_handler /* Jump to window vectors section */ +#endif + + .align 4 +_xtensa_to_syscall_handler: + call0 _xtensa_syscall_handler /* Jump to syscall exception handler */ + +#ifdef HAVE_LAZY_COPROC +#if XCHAL_CP_NUM > 0 + .align 4 +_xtensa_to_coproc_handler: + call0 _xtensa_coproc_handler /* Jump to copressor exception handler */ +#endif +#endif /* HAVE_LAZY_COPROC */ + +/**************************************************************************** + * Name: _xtensa_user_handler + * + * Description: + * User exception handler. + * + * Entry Conditions: + * A0 saved in EXCSAVE_1. All other register as upon exception. + * + ****************************************************************************/ + + .type _xtensa_user_handler, @function + .align 4 + +_xtensa_user_handler: + + /* If level 1 interrupt then jump to the dispatcher */ + + rsr a0, EXCCAUSE + beqi a0, EXCCAUSE_LEVEL1INTERRUPT, _xtensa_to_level1_handler + +#ifdef HAVE_LAZY_COPROC +#if XCHAL_CP_NUM > 0 + /* Handle any coprocessor exceptions. Rely on the fact that exception + * numbers above EXCCAUSE_CP0_DISABLED all relate to the coprocessors. + */ + + bgeui a0, EXCCAUSE_CP0_DISABLED, _xtensa_to_coproc_handler +#endif +#endif /* HAVE_LAZY_COPROC */ + + /* Handle alloca and syscall exceptions */ + +#if XCHAL_HAVE_WINDOWED + beqi a0, EXCCAUSE_ALLOCA, _xtensa_to_alloca_handler +#endif + beqi a0, EXCCAUSE_SYSCALL, _xtensa_to_syscall_handler + + /* Handle all other exceptions. All can have user-defined handlers. */ + /* NOTE: we'll stay on the user stack for exception handling. */ + + /* Allocate exception frame and save minimal context. */ + + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EPC_1 /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE_1 /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) + + /* Save rest of interrupt context. */ + + s32i a2, sp, (4 * REG_A2) + mov a2, sp /* Address of state save on stack */ + call0 _xtensa_context_save /* Save full register state */ + + /* Save exc cause and vaddr into exception frame */ + + rsr a0, EXCCAUSE + s32i a0, sp, (4 * REG_EXCCAUSE) + rsr a0, EXCVADDR + s32i a0, sp, (4 * REG_EXCVADDR) + + /* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */ + +#ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM +#else + movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE +#endif + wsr a0, PS + + /* Call xtensa_user, passing both the EXCCAUSE and a pointer to the + * beginning of the register save area. + */ + + rsr a2, EXCCAUSE /* Argument 1 (a2) = EXCCAUSE */ + mov a3, sp /* Argument 2 (a2) = pointer to register save area */ + +#ifdef __XTENSA_CALL0_ABI__ + calx0 xtensa_user /* Call xtensa_user */ +#else + call4 xtensa_user /* Call xtensa_user */ +#endif + + /* xtensa_user should not return */ + +1: j 1b + +/**************************************************************************** + * Name: _xtensa_syscall_handler + * + * Description: + * Syscall Exception Handler (jumped to from User Exception Handler). + * Syscall 0 is required to spill the register windows (no-op in Call 0 ABI). + * Only syscall 0 is handled here. Other syscalls return -1 to caller in a2. + * + * Entry Conditions: + * A0 saved in EXCSAVE_1. All other register as upon exception. + * + ****************************************************************************/ + + .section HANDLER_SECTION, "ax" + .type _xtensa_syscall_handler, @function + .align 4 +_xtensa_syscall_handler: + + /* Allocate stack frame and save A0, A1, and PS */ + + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EXCSAVE_1 /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) + + /* Save EPC */ + +#ifidef XCHAL_HAVE_LOOPS + /* Save A2 and A3 now to give us some registers to work with. A0, A2 + * and A3 are now available. NOTE that A3 will get saved again in + * _xtensa_context_save(). + */ + + s32i a2, sp, (4 * REG_A2) /* Save interruptee's A2 */ + s32i a2, sp, (4 * REG_A2) /* Save interruptee's A2 */ + + /* Get the interruptee's PC and skip over the 'syscall' instruction. + * If it's at the end of a zero-overhead loop and it's not on the last + * iteration, decrement loop counter and skip to beginning of loop. + */ + + rsr a2, EPC_1 /* a2 = PC of 'syscall' */ + addi a3, a2, 3 /* Increment PC */ + + rsr a0, LEND /* Skip if PC != LEND */ + bne a3, a0, 1f + + rsr a0, LCOUNT /* Skip if LCOUNT == 0 */ + beqz a0, 1f + + addi a0, a0, -1 /* Decrement LCOUNT */ + rsr a3, LBEG /* Set PC = LBEG */ + wsr a0, LCOUNT /* Save the new LCOUNT */ + +1: + wsr a3, EPC_1 /* Update PC */ + s32i a3, sp, (4 * REG_PC) + +#else + /* Get the interruptee's PC and skip over the 'syscall' instruction. */ + + rsr a1, EPC_1 /* a2 = PC of 'syscall' */ + addi a0, a1, 3 /* ++PC */ + + wsr a0, EPC_1 /* Update PC */ + s32i a0, sp, (4 * REG_PC) + + /* Save a2 which will hold the argument to _xtensa_context_save*/ + + s32i a2, sp, (4 * REG_A2) /* Save interruptee's A2 */ +#endif + + /* Save rest of interrupt context. */ + + mov a2, sp /* Address of state save on stack */ + call0 _xtensa_context_save /* Save full register state */ + + /* Set up PS for C, enable interrupts above this level and clear EXCM. */ + + ps_setup 1 a0 + + /* Dispatch the sycall as with other interrupts. */ + /* At this point, sp holds the pointer to the register save area. That, + * however, may change as a consequence of context switching. + */ + + mov a12, sp /* a12 = address of register save area */ + movi a2, XTENSA_IRQ_SYSCALL /* Argument 1: IRQ number */ + mov a3, a12 /* Argument 2: Top of stack = register save area */ +#ifdef __XTENSA_CALL0_ABI__ + call0 xtensa_irq_dispatch /* Call xtensa_int_decode */ +#else + call4 xtensa_irq_dispatch /* Call xtensa_int_decode */ +#endif + + /* On return from xtensa_irq_dispatch, A2 will contain the address of the new + * register save area. Usually this would be the same as the current SP. + * But in the event of a context switch, A2 will instead refer to the TCB + * register save area. + */ + + beq a2, a12, 2f /* If timer interrupt then skip table */ + + /* Switch stacks */ + + mov a12, a2 /* Switch to the save area of the new thread */ + l32i a2, a12, (4 * REG_A1) /* Retrieve stack ptr and replace */ + addi sp, a2, -(4 * XCPTCONTEXT_SIZE) + +2: + + /* Restore registers in preparation to return from interrupt */ + + mov a2, a12 /* a2 = address of new state save area */ + call0 _xtensa_context_restore + + /* Restore only level-specific regs (the rest were already restored) */ + + l32i a0, sp, (4 * REG_PS) /* Retrieve interruptee's PS */ + wsr a0, PS + l32i a0, sp, (4 * REG_PC) /* Retrieve interruptee's PC */ + wsr a0, EPC_1 + l32i a0, sp, (4 * REG_A0) /* Retrieve interruptee's A0 */ + l32i a2, sp, (4 * REG_A2) /* Retrieve interruptee's A2 */ + l32i sp, sp, (4 * REG_A1) /* Remove interrupt stack frame */ + rsync /* Ensure EPS and EPC written */ + + /* Return from exception. RFE returns from either the UserExceptionVector + * or the KernelExceptionVector. RFE sets PS.EXCM back to 0 and then jumps + * to the address in EPC[1]. + */ + + rfe + +/**************************************************************************** + * Name: _xtensa_coproc_handler + * + * Description: + * Co-Processor Exception Handler (jumped to from User Exception Handler). + * This logic handlers handles the User Coprocessor[n]Disabled exceptions, + * n=0-7. A User Coprocessor[n]Disabled exception occurs when if logic + * executes a co-processor n instruction while coprocessor n is disabled. + * + * This exception allows for lazy context switch of co-processor state: + * CPENABLE can be cleared on each context switch. When logic on the + * thread next accesses the co-processor, this exception will occur and + * the exception handler may then enable the co-processor on behalf of + * the thread. + * + * NuttX does not currently implement this lazy co-process enable. Rather, + * NuttX follows the model: + * + * 1. A set of co-processors may be enable when each thread starts as determined by CONFIG_XTENSA_CP_INITSET. + * 2. Additional co-processors may be enabled for the thread by explicitly setting the CPENABLE register when the thread starts. + * 3. Co-processor state, including CPENABLE, is saved an restored on each context switch. + * 4. Any Coprocessor[n]Disabled exceptions result in a system PANIC. + + * These exceptions are generated by co-processor instructions, which are + * only allowed in thread code (not in interrupts or kernel code). This + * restriction is deliberately imposed to reduce the burden of state-save/ + * restore in interrupts. + * + * Entry Conditions: + * A0 saved in EXCSAVE_1. All other register as upon exception. + * + ****************************************************************************/ + +/* Disabled for now: The following logic is redundant. It simply duplicates the + * the logic in _xtensa_user_handler + */ + +#ifdef HAVE_LAZY_COPROC +#if XCHAL_CP_NUM > 0 + .type _xtensa_coproc_handler, @function + .align 4 + +_xtensa_coproc_handler: + + /* For now, just panic */ + + mov a0, sp /* sp == a1 */ + addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */ + s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */ + rsr a0, EPS /* Save interruptee's PS */ + s32i a0, sp, (4 * REG_PS) + rsr a0, EPC_1 /* Save interruptee's PC */ + s32i a0, sp, (4 * REG_PC) + rsr a0, EXCSAVE_1 /* Save interruptee's a0 */ + s32i a0, sp, (4 * REG_A0) + + /* Save rest of interrupt context. */ + + s32i a2, sp, (4 * REG_A2) + mov a2, sp /* Address of state save on stack */ + call0 _xtensa_context_save /* Save full register state */ + + /* Save exc cause and vaddr into exception frame */ + + rsr a0, EXCCAUSE + s32i a0, sp, (4 * REG_EXCCAUSE) + rsr a0, EXCVADDR + s32i a0, sp, (4 * REG_EXCVADDR) + + /* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */ + +#ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM +#else + movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE +#endif + wsr a0, PS + + /* Call xtensa_user, passing both the EXCCAUSE and a pointer to the + * beginning of the register save area. + */ + + rsr a2, EXCCAUSE /* Argument 1 (a2) = EXCCAUSE */ + mov a3, sp /* Argument 2 (a2) = pointer to register save area */ + +#ifdef __XTENSA_CALL0_ABI__ + calx0 xtensa_user /* Call xtensa_user */ +#else + call4 xtensa_user /* Call xtensa_user */ +#endif + + /* xtensa_user should not return */ + +1: j 1b + +#endif /* XCHAL_CP_NUM */ +#endif /* HAVE_LAZY_COPROC */ diff --git a/arch/xtensa/src/common/xtensa_vectors.S b/arch/xtensa/src/common/xtensa_vectors.S index 42158964e4..99af68c442 100644 --- a/arch/xtensa/src/common/xtensa_vectors.S +++ b/arch/xtensa/src/common/xtensa_vectors.S @@ -323,4 +323,23 @@ _kernel_exception_vector: .end literal_prefix -#endif +/**************************************************************************** + * Name: _user_exception_vector + * + * Description: + * User Exception (including Level 1 Interrupt from user mode). + * + ****************************************************************************/ + + .begin literal_prefix .user_exception_vector + .section .user_exception_vector.text, "ax" + .global _user_exception_vector + .type _user_exception_vector, @function + .align 4 + +_user_exception_vector: + + wsr a0, EXCSAVE_1 /* Preserve a0 */ + call0 xtensa_user_handler /* And jump to user exception handler */ + + .end literal_prefix diff --git a/arch/xtensa/src/common/xtensa_window_vector.S b/arch/xtensa/src/common/xtensa_window_vector.S index de68c2010e..853e1210c3 100644 --- a/arch/xtensa/src/common/xtensa_window_vector.S +++ b/arch/xtensa/src/common/xtensa_window_vector.S @@ -47,12 +47,12 @@ /* WINDOW OVERFLOW AND UNDERFLOW EXCEPTION VECTORS AND ALLOCA EXCEPTION HANDLER * - * Here is the code for each window overflow/underflow exception vector and + * Here is the code for each window overflow/underflow exception vector and * (interspersed) efficient code for handling the alloca exception cause. * Window exceptions are handled entirely in the vector area and are very - * tight for performance. The alloca exception is also handled entirely in + * tight for performance. The alloca exception is also handled entirely in * the window vector area so comes at essentially no cost in code size. - * Users should never need to modify them and Cadence Design Systems recommends + * Users should never need to modify them and Cadence Design Systems recommends * they do not. * * Window handlers go at predetermined vector locations according to the @@ -132,8 +132,8 @@ _window_underflow4: */ .align 4 - .global _xt_alloca_exc -_xt_alloca_exc: + .global _xtensa_alloca_handler +_xtensa_alloca_handler: rsr a0, WINDOWBASE /* Grab WINDOWBASE before rotw changes it */ rotw -1 /* WINDOWBASE goes to a4, new a0-a3 are scratch */ diff --git a/configs/esp32-core/scripts/esp32_common.ld b/configs/esp32-core/scripts/esp32_common.ld index 606cc814d0..25a49affbd 100644 --- a/configs/esp32-core/scripts/esp32_common.ld +++ b/configs/esp32-core/scripts/esp32_common.ld @@ -35,14 +35,12 @@ SECTIONS . = 0x300; KEEP(*(.kernel_exception_vector.text)); . = 0x340; - KEEP(*(.UserExceptionVector.text)); - . = 0x3C0; + KEEP(*(.user_exception_vector.text)); + . = 0x3c0; KEEP(*(.double_exception_vector.text)); . = 0x400; - *(.*Vector.literal) + *(.*_vector.literal) - *(.UserEnter.literal); - *(.UserEnter.text); . = ALIGN (16); *(.entry.text) *(.init.literal) -- GitLab From 28d1478480b698e73670a6a0a4e230fb6a4e4830 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 31 Oct 2016 13:15:15 -0600 Subject: [PATCH 272/734] Xtensa/ESP32: Add CPU1 startup logic --- arch/xtensa/src/common/xtensa.h | 4 + arch/xtensa/src/common/xtensa_createstack.c | 10 +- arch/xtensa/src/esp32/Make.defs | 5 +- arch/xtensa/src/esp32/esp32_cpuhead.S | 139 ++++++++++++++++++++ arch/xtensa/src/esp32/esp32_cpustart.c | 8 +- arch/xtensa/src/esp32/esp32_irq.c | 1 - 6 files changed, 162 insertions(+), 5 deletions(-) create mode 100644 arch/xtensa/src/esp32/esp32_cpuhead.S diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index 5a5ab2f88c..97e59788e8 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -108,6 +108,10 @@ # define CONFIG_ARCH_INTERRUPTSTACK 0 #endif +/* Used for stack usage measurements */ + +#define STACK_COLOR 0xdeadbeef + /* In the XTENSA model, the state is copied from the stack to the TCB, but * only a referenced is passed to get the state from the TCB. * diff --git a/arch/xtensa/src/common/xtensa_createstack.c b/arch/xtensa/src/common/xtensa_createstack.c index c25d64cfa4..68308fb527 100644 --- a/arch/xtensa/src/common/xtensa_createstack.c +++ b/arch/xtensa/src/common/xtensa_createstack.c @@ -183,12 +183,20 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) size_t size_of_stack; #ifdef CONFIG_STACK_COLORATION + uint32_t *ptr; + int i; + /* Yes.. If stack debug is enabled, then fill the stack with a * recognizable value that we can use later to test for high * water marks. */ - memset(tcb->stack_alloc_ptr, 0xaa, stack_size); + for (i = 0, ptr = (uint32_t *)tcb->stack_alloc_ptr; + i < stack_size; + i += sizeof(uint32_t)) + { + *ptr++ = STACK_COLOR; + } #endif /* XTENSA uses a push-down stack: the stack grows toward lower diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index d16874c4bc..6ea97e9bcb 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -41,7 +41,8 @@ HEAD_CSRC = esp32_start.c # Common XTENSA files (arch/xtensa/src/common) CMN_ASRCS = xtensa_context.S xtensa_coproc.S xtensa_cpuint.S -CMN_ASRCS += xtensa_int_handlers.S xtensa_panic.S xtensa_vectors.S +CMN_ASRCS += xtensa_int_handlers.S xtensa_panic.S xtensa_user_handlers.S +CMN_ASRCS += xtensa_vectors.S CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c CMN_CSRCS += xtensa_cpenable.c xtensa_createstack.c xtensa_exit.c xtensa_idle.c @@ -80,7 +81,7 @@ endif # Required ESP32 files (arch/xtensa/src/lx6) -CHIP_ASRCS = +CHIP_ASRCS = esp32_cpuhead.S CHIP_CSRCS = esp32_allocateheap.c esp32_clockconfig.c esp32_cpuint.c CHIP_CSRCS += esp32_gpio.c esp32_intdecode.c esp32_irq.c esp32_region.c CHIP_CSRCS += esp32_start.c esp32_timerisr.c diff --git a/arch/xtensa/src/esp32/esp32_cpuhead.S b/arch/xtensa/src/esp32/esp32_cpuhead.S new file mode 100644 index 0000000000..9afae45d82 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_cpuhead.S @@ -0,0 +1,139 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_cpuhead.S + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + + .file "esp32_cpuhead.S" + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Private Data + ****************************************************************************/ + + section .noinit, "aw" + .align 16 + .global g_cpu1_idlestack + .type g_cpu1_idlestack, @object + +g_cpu1_idlestack: + .space (CONFIG_SMP_IDLETHREAD_STACKSIZE & ~15) +.Lcpu1_stacktop: + .size g_cpu1_idlestack, . - g_cpu1_idlestack + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + + .text + +/**************************************************************************** + * Name: __cpu[n]_start + * + * Description: + * Boot functions for each CPU (other than CPU0). These functions set up + * the ARM operating mode, the initial stack, and configure co-processor + * registers. At the end of the boot, esp32_cpu_boot() is called. + * + * These functions are provided by the common ARMv7-A logic. + * + * Input parameters: + * None + * + * Returned Value: + * Do not return. + * + ****************************************************************************/ + +#if CONFIG_SMP_NCPUS > 1 + + .global __cpu1_start + .type __cpu1_start, #function + +.Lcpu1_bottomofstack: + long .Lcpu1_stacktop + .size .Lcpu1_bottomofstack, . - .Lcpu1_bottomofstack + +#ifdef CONFIG_STACK_COLORATION +.Lcpu1_bottomofstack: + long .Lcpu1_stacktop + .size .Lcpu1_bottomofstack, . - .Lcpu1_bottomofstack + +.Lcpu1_stackcolor: + long STACK_COLOR + .size .Lcpu1_stackcolor, . - .Lcpu1_stackcolor +#endif + +__cpu1_start: + + /* Set up the stack pointer and the CPU index */ + + l32r .Lcpu1_bottomofstack + +#ifdef CONFIG_STACK_COLORATION + /* Write a known value to the IDLE thread stack to support stack + * monitoring logic + */ + + mov a0, sp + l32r a1, .Lcpu1_bottomofstack + l32r a2, .Lcpu1_stackcolor + +1: + s32i a2, a1, 0 + addi a2, a2, 4 + bne a1, a2, 1b +#endif + + /* Set up the intiali PS */ + +#ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_EXCM; +#else + movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1); +#endif + wsr a0, PS + + /* Finish initialization in C */ + + movi a2, 1 /* Argument 1: CPU ID */ + call0 xtensa_start_handler + + /* xtensa_start_handler() does not return */ + +2: b 2b + .size __cpu1_start, . - __cpu1_start diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c index 6fe42912eb..6bb2a57f3c 100644 --- a/arch/xtensa/src/esp32/esp32_cpustart.c +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -197,6 +197,12 @@ int xtensa_start_handler(int irq, FAR void *context) xtensa_registerdump(tcb); +#ifndef CONFIG_SUPPRESS_INTERRUPTS + /* And Enable interrupts */ + + up_irq_enable(); +#endif + /* Then switch contexts. This instantiates the exception context of the * tcb at the head of the assigned task list. In this case, this should * be the CPUs NULL task. @@ -265,7 +271,7 @@ int up_cpu_start(int cpu) /* Set the CPU1 start address */ - ets_set_appcpu_boot_addr((uint32_t)xtensa_start_handler); + ets_set_appcpu_boot_addr((uint32_t)__cpu1_start); /* And way for the initial task to run on CPU1 */ diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c index fae4687d5a..bf4eec3be6 100644 --- a/arch/xtensa/src/esp32/esp32_irq.c +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -186,7 +186,6 @@ void xtensa_irq_initialize(void) esp32_gpioirqinitialize(); #endif - #ifndef CONFIG_SUPPRESS_INTERRUPTS /* And finally, enable interrupts */ -- GitLab From 4d0b0e44f10816e2c6200ba26c3348add3c1f830 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 31 Oct 2016 14:56:48 -0600 Subject: [PATCH 273/734] Xtensa/ESP32: Add up_cpu_idlestack() and fix some compile issues. --- arch/xtensa/src/common/xtensa.h | 1 + arch/xtensa/src/common/xtensa_assert.c | 1 - arch/xtensa/src/common/xtensa_int_handlers.S | 2 +- arch/xtensa/src/common/xtensa_user_handler.S | 2 +- arch/xtensa/src/common/xtensa_vectors.S | 2 + arch/xtensa/src/esp32/Make.defs | 9 +- arch/xtensa/src/esp32/esp32_clockconfig.c | 2 +- arch/xtensa/src/esp32/esp32_cpuhead.S | 35 ++++-- arch/xtensa/src/esp32/esp32_cpuidlestack.c | 114 ++++++++++++++++++ arch/xtensa/src/esp32/esp32_cpuindex.S | 2 +- arch/xtensa/src/esp32/esp32_cpustart.c | 10 +- .../src/esp32/esp32_intercpu_interrupt.c | 3 + arch/xtensa/src/esp32/esp32_irq.c | 2 +- ...esp32_intercpu_interrupt.h => esp32_smp.h} | 20 ++- 14 files changed, 176 insertions(+), 29 deletions(-) create mode 100644 arch/xtensa/src/esp32/esp32_cpuidlestack.c rename arch/xtensa/src/esp32/{esp32_intercpu_interrupt.h => esp32_smp.h} (82%) diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index 97e59788e8..422ec0b96f 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -276,6 +276,7 @@ void xtensa_user(int exccause, uint32_t *regs) noreturn_function; /* Software interrupt handler */ #ifdef CONFIG_SMP +void __cpu1_start(void) noreturn_function; int xtensa_intercpu_interrupt(int tocpu, int intcode); void xtensa_pause_handler(void); #endif diff --git a/arch/xtensa/src/common/xtensa_assert.c b/arch/xtensa/src/common/xtensa_assert.c index 565e71ff5c..24b7fd7e23 100644 --- a/arch/xtensa/src/common/xtensa_assert.c +++ b/arch/xtensa/src/common/xtensa_assert.c @@ -164,7 +164,6 @@ void up_assert(const uint8_t *filename, int lineno) filename, lineno); #endif - CURRENT_REGS = regs; xtensa_assert(EXIT_FAILURE); } diff --git a/arch/xtensa/src/common/xtensa_int_handlers.S b/arch/xtensa/src/common/xtensa_int_handlers.S index 6946aa9b17..0cf3c2f129 100644 --- a/arch/xtensa/src/common/xtensa_int_handlers.S +++ b/arch/xtensa/src/common/xtensa_int_handlers.S @@ -125,7 +125,7 @@ * a consequence of context switching. */ - mov s12, sp /* a12 = address of save area */ + mov a12, sp /* a12 = address of save area */ ._xtensa_dispatch_level&level&: diff --git a/arch/xtensa/src/common/xtensa_user_handler.S b/arch/xtensa/src/common/xtensa_user_handler.S index 75776a5eee..abf043da2b 100644 --- a/arch/xtensa/src/common/xtensa_user_handler.S +++ b/arch/xtensa/src/common/xtensa_user_handler.S @@ -274,7 +274,7 @@ _xtensa_syscall_handler: /* Save EPC */ -#ifidef XCHAL_HAVE_LOOPS +#ifdef XCHAL_HAVE_LOOPS /* Save A2 and A3 now to give us some registers to work with. A0, A2 * and A3 are now available. NOTE that A3 will get saved again in * _xtensa_context_save(). diff --git a/arch/xtensa/src/common/xtensa_vectors.S b/arch/xtensa/src/common/xtensa_vectors.S index 99af68c442..726824f058 100644 --- a/arch/xtensa/src/common/xtensa_vectors.S +++ b/arch/xtensa/src/common/xtensa_vectors.S @@ -215,6 +215,8 @@ _xtensa_nmi_vector: .size _xtensa_nmi_vector, . - _xtensa_nmi_vector .end literal_prefix +#endif /* XCHAL_HAVE_NMI */ + /**************************************************************************** * Name: _debug_exception_vector * diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 6ea97e9bcb..5d6beb98d0 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -41,7 +41,7 @@ HEAD_CSRC = esp32_start.c # Common XTENSA files (arch/xtensa/src/common) CMN_ASRCS = xtensa_context.S xtensa_coproc.S xtensa_cpuint.S -CMN_ASRCS += xtensa_int_handlers.S xtensa_panic.S xtensa_user_handlers.S +CMN_ASRCS += xtensa_int_handlers.S xtensa_panic.S xtensa_user_handler.S CMN_ASRCS += xtensa_vectors.S CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c @@ -81,7 +81,7 @@ endif # Required ESP32 files (arch/xtensa/src/lx6) -CHIP_ASRCS = esp32_cpuhead.S +CHIP_ASRCS = CHIP_CSRCS = esp32_allocateheap.c esp32_clockconfig.c esp32_cpuint.c CHIP_CSRCS += esp32_gpio.c esp32_intdecode.c esp32_irq.c esp32_region.c CHIP_CSRCS += esp32_start.c esp32_timerisr.c @@ -89,9 +89,8 @@ CHIP_CSRCS += esp32_start.c esp32_timerisr.c # Configuration-dependent ESP32 files ifeq ($(CONFIG_SMP),y) -CHIP_ASRCS = esp32_cpuindex.S -CMN_CSRCS += esp32_cpustart.c esp32_intercpu_interrupt.c -#CMN_CSRCS += esp32_cpuidlestack.c +CHIP_ASRCS = esp32_cpuhead.S esp32_cpuindex.S +CMN_CSRCS += esp32_cpuidlestack.c esp32_cpustart.c esp32_intercpu_interrupt.c endif ifeq ($(CONFIG_ESP32_UART),y) diff --git a/arch/xtensa/src/esp32/esp32_clockconfig.c b/arch/xtensa/src/esp32/esp32_clockconfig.c index 4f841b11be..f2f7df08ea 100644 --- a/arch/xtensa/src/esp32/esp32_clockconfig.c +++ b/arch/xtensa/src/esp32/esp32_clockconfig.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/esp32/exp32_cpuindex.S + * arch/xtensa/src/esp32/esp32_clockconfig.C * * Mofidifed by use in NuttX by: * diff --git a/arch/xtensa/src/esp32/esp32_cpuhead.S b/arch/xtensa/src/esp32/esp32_cpuhead.S index 9afae45d82..9fb05f66ea 100644 --- a/arch/xtensa/src/esp32/esp32_cpuhead.S +++ b/arch/xtensa/src/esp32/esp32_cpuhead.S @@ -40,15 +40,19 @@ ****************************************************************************/ #include +#include +#include + +#ifdef CONFIG_SMP /**************************************************************************** * Private Data ****************************************************************************/ - section .noinit, "aw" - .align 16 + .section .noinit, "aw" .global g_cpu1_idlestack .type g_cpu1_idlestack, @object + .align 16 g_cpu1_idlestack: .space (CONFIG_SMP_IDLETHREAD_STACKSIZE & ~15) @@ -79,30 +83,36 @@ g_cpu1_idlestack: * ****************************************************************************/ -#if CONFIG_SMP_NCPUS > 1 - .global __cpu1_start - .type __cpu1_start, #function + .type __cpu1_start, @function + + .align 4 .Lcpu1_bottomofstack: - long .Lcpu1_stacktop + .long .Lcpu1_stacktop .size .Lcpu1_bottomofstack, . - .Lcpu1_bottomofstack #ifdef CONFIG_STACK_COLORATION .Lcpu1_bottomofstack: - long .Lcpu1_stacktop + .long .Lcpu1_stacktop .size .Lcpu1_bottomofstack, . - .Lcpu1_bottomofstack .Lcpu1_stackcolor: - long STACK_COLOR + .long STACK_COLOR .size .Lcpu1_stackcolor, . - .Lcpu1_stackcolor #endif + .align 4 + __cpu1_start: /* Set up the stack pointer and the CPU index */ - l32r .Lcpu1_bottomofstack + l32r sp, .Lcpu1_bottomofstack + + /* Does it make since to have co-processors enabled on the IDLE thread? */ + +//#warning REVISIT: Must set aside co-processor save ares #ifdef CONFIG_STACK_COLORATION /* Write a known value to the IDLE thread stack to support stack @@ -122,9 +132,9 @@ __cpu1_start: /* Set up the intiali PS */ #ifdef __XTENSA_CALL0_ABI__ - movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_EXCM; + movi a0, (PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_EXCM) #else - movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1); + movi a0, (PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1)) #endif wsr a0, PS @@ -135,5 +145,6 @@ __cpu1_start: /* xtensa_start_handler() does not return */ -2: b 2b +2: j 2b .size __cpu1_start, . - __cpu1_start +#endif /* CONFIG_SMP */ diff --git a/arch/xtensa/src/esp32/esp32_cpuidlestack.c b/arch/xtensa/src/esp32/esp32_cpuidlestack.c new file mode 100644 index 0000000000..e1f0941ce9 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_cpuidlestack.c @@ -0,0 +1,114 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_cpuidlestack.c + * + * Mofidifed by use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from software originally provided by Expressif Systems: + * + * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "xtensa.h" +#include "esp32_smp.h" + +#ifdef CONFIG_SMP + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_cpu_idlestack + * + * Description: + * Allocate a stack for the CPU[n] IDLE task (n > 0) if appropriate and + * setup up stack-related information in the IDLE task's TCB. This + * function is always called before up_cpu_start(). This function is + * only called for the CPU's initial IDLE task; up_create_task is used for + * all normal tasks, pthreads, and kernel threads for all CPUs. + * + * The initial IDLE task is a special case because the CPUs can be started + * in different wans in different environments: + * + * 1. The CPU may already have been started and waiting in a low power + * state for up_cpu_start(). In this case, the IDLE thread's stack + * has already been allocated and is already in use. Here + * up_cpu_idlestack() only has to provide information about the + * already allocated stack. + * + * 2. The CPU may be disabled but started when up_cpu_start() is called. + * In this case, a new stack will need to be created for the IDLE + * thread and this function is then equivalent to: + * + * return up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL); + * + * The following TCB fields must be initialized by this function: + * + * - adj_stack_size: Stack size after adjustment for hardware, processor, + * etc. This value is retained only for debug purposes. + * - stack_alloc_ptr: Pointer to allocated stack + * - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of + * the stack pointer. + * + * Inputs: + * - cpu: CPU index that indicates which CPU the IDLE task is + * being created for. + * - tcb: The TCB of new CPU IDLE task + * - stack_size: The requested stack size for the IDLE task. At least + * this much must be allocated. This should be + * CONFIG_SMP_IDLETHREAD_STACKSIZE. + * + ****************************************************************************/ + +int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size) +{ + uintptr_t topofstack; + + /* XTENSA uses a push-down stack: the stack grows toward lower* addresses + * in memory. The stack pointer register points to the lowest, valid + * working address (the "top" of the stack). Items on the stack are + * referenced as positive word offsets from sp. + */ + + /* Save information about pre-allocated IDLE thread stack */ + + + tcb->stack_alloc_ptr = g_cpu1_idlestack; + tcb->adj_stack_size = CPU1_IDLETHREAD_STACKSIZE; + topofstack = (uintptr_t)g_cpu1_idlestack + CPU1_IDLETHREAD_STACKSIZE; + tcb->adj_stack_ptr = (uint32_t *)topofstack; + +#if XCHAL_CP_NUM > 0 + /* Does it make since to have co-processors enabled on the IDLE thread? */ + +//#warning REVISIT: Need to set co-processor save are in TCB +#endif + + return OK; +} + +#endif /* CONFIG_SMP */ + diff --git a/arch/xtensa/src/esp32/esp32_cpuindex.S b/arch/xtensa/src/esp32/esp32_cpuindex.S index 0059f256e2..f62eed1202 100644 --- a/arch/xtensa/src/esp32/esp32_cpuindex.S +++ b/arch/xtensa/src/esp32/esp32_cpuindex.S @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/esp32/exp32_cpuindex.S + * arch/xtensa/src/esp32/esp32_cpuindex.S * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c index 6bb2a57f3c..40f9882a5e 100644 --- a/arch/xtensa/src/esp32/esp32_cpustart.c +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -52,7 +52,7 @@ #include "chip/esp32_dport.h" #include "esp32_region.h" #include "esp32_cpuint.h" -#include "esp32_intercpu_interrupt.h" +#include "esp32_smp.h" #ifdef CONFIG_SMP @@ -193,6 +193,14 @@ int xtensa_start_handler(int irq, FAR void *context) esp32_detach_peripheral(1, i);; } +#if 0 /* Does it make since to have co-processors enabled on the IDLE thread? */ +#if XTENSA_CP_ALLSET != 0 + /* Set initial co-processor state */ + + xtensa_coproc_enable(struct xtensa_cpstate_s *cpstate, int cpset); +#endif +#endif + /* Dump registers so that we can see what is going to happen on return */ xtensa_registerdump(tcb); diff --git a/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c b/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c index 963e1d5156..66ae7bac06 100644 --- a/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c +++ b/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c @@ -41,11 +41,14 @@ #include #include +#include #include #include +#include #include +#include "chip/esp32_dport.h" #include "xtensa.h" #ifdef CONFIG_SMP diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c index bf4eec3be6..4c1d15008f 100644 --- a/arch/xtensa/src/esp32/esp32_irq.c +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -48,7 +48,7 @@ #include "xtensa.h" #include "esp32_cpuint.h" -#include "esp32_intercpu_interrupt.h" +#include "esp32_smp.h" /**************************************************************************** * Public Data diff --git a/arch/xtensa/src/esp32/esp32_intercpu_interrupt.h b/arch/xtensa/src/esp32/esp32_smp.h similarity index 82% rename from arch/xtensa/src/esp32/esp32_intercpu_interrupt.h rename to arch/xtensa/src/esp32/esp32_smp.h index 5b2c7eeae7..22d934e7a6 100644 --- a/arch/xtensa/src/esp32/esp32_intercpu_interrupt.h +++ b/arch/xtensa/src/esp32/esp32_smp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/esp32/esp32_intercpu_interrupt.h + * arch/xtensa/src/esp32/esp32_smp.h * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt > @@ -33,8 +33,8 @@ * ****************************************************************************/ -#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_INTERCPU_INTERRUPT_H -#define __ARCH_XTENSA_SRC_ESP32_ESP32_INTERCPU_INTERRUPT_H +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_SMP_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_SMP_H /**************************************************************************** * Included Files @@ -44,8 +44,18 @@ #ifdef CONFIG_SMP + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* This is the CPU1 IDLE stack */ + +#define CPU1_IDLETHREAD_STACKSIZE (CONFIG_SMP_IDLETHREAD_STACKSIZE & ~15) +extern uint32_t g_cpu1_idlestack[CPU1_IDLETHREAD_STACKSIZE / 34]; + /**************************************************************************** - * Pre-processor Definitions + * Public Functions ****************************************************************************/ /**************************************************************************** @@ -60,4 +70,4 @@ int esp32_fromcpu0_interrupt(int irq, FAR void *context); int esp32_fromcpu1_interrupt(int irq, FAR void *context); #endif /* CONFIG_SMP */ -#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_INTERCPU_INTERRUPT_H */ +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_SMP_H */ -- GitLab From 1eb15d0d4e1187ac2240db09091e020031f875a3 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 31 Oct 2016 15:43:28 -0600 Subject: [PATCH 274/734] ESP32: Update linker script to use naming expected by CXX initialization --- configs/esp32-core/scripts/esp32_common.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/esp32-core/scripts/esp32_common.ld b/configs/esp32-core/scripts/esp32_common.ld index 25a49affbd..38bb03e533 100644 --- a/configs/esp32-core/scripts/esp32_common.ld +++ b/configs/esp32-core/scripts/esp32_common.ld @@ -123,12 +123,12 @@ SECTIONS . = (. + 3) & ~ 3; /* C++ constructor and destructor tables, properly ordered: */ - __init_array_start = ABSOLUTE(.); + __sinit = ABSOLUTE(.); KEEP (*crtbegin.o(.ctors)) KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) - __init_array_end = ABSOLUTE(.); + _einit = ABSOLUTE(.); KEEP (*crtbegin.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) KEEP (*(SORT(.dtors.*))) -- GitLab From cfcc7edded6441ff1f60a5033ed93c278bc2b96f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 31 Oct 2016 17:51:48 -0600 Subject: [PATCH 275/734] Xtensa/ESP32: Add window spill logic; Add C++ support to linker script --- arch/xtensa/src/common/xtensa_context.S | 2 +- arch/xtensa/src/common/xtensa_irqdispatch.c | 7 +- arch/xtensa/src/common/xtensa_windowspill.S | 422 ++++++++++++++++++++ arch/xtensa/src/esp32/Make.defs | 2 +- configs/esp32-core/scripts/esp32_common.ld | 18 +- 5 files changed, 445 insertions(+), 6 deletions(-) create mode 100644 arch/xtensa/src/common/xtensa_windowspill.S diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index a2e69bee5a..8d9462e5a6 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -177,7 +177,7 @@ _xtensa_context_save: #warning REVISIT: The following is probably not correct due to changes in registers addi sp, sp, (4 * XCPTCONTEXT_SIZE) /* Restore the interruptee's SP */ - call0 xthal_window_spill_nw /* Preserves only a4,5,8,9,12,13 */ + call0 _xtensa_window_spill /* Preserves only a4,5,8,9,12,13 */ addi sp, sp, -(4 * XCPTCONTEXT_SIZE) l32i a12, sp, (4 * REG_TMP0) /* Recover stuff from stack frame */ l32i a13, sp, (4 * REG_TMP1) diff --git a/arch/xtensa/src/common/xtensa_irqdispatch.c b/arch/xtensa/src/common/xtensa_irqdispatch.c index e2ce51f29e..2f05eab152 100644 --- a/arch/xtensa/src/common/xtensa_irqdispatch.c +++ b/arch/xtensa/src/common/xtensa_irqdispatch.c @@ -82,7 +82,12 @@ uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs) CURRENT_REGS = regs; - /* Deliver the IRQ */ + /* Deliver the IRQ + * + * NOTE: Co-process state has not been saved yet (see below). As a + * consequence, no interrupt level logic may perform co-processor + * operations. This includes use of the FPU. + */ irq_dispatch(irq, regs); diff --git a/arch/xtensa/src/common/xtensa_windowspill.S b/arch/xtensa/src/common/xtensa_windowspill.S new file mode 100644 index 0000000000..bba79e14ee --- /dev/null +++ b/arch/xtensa/src/common/xtensa_windowspill.S @@ -0,0 +1,422 @@ +/**************************************************************************** + * arch/xtensa/src/common/xtensa_windowspill.S + * Register window spill routine + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Tensilica Inc. + * + * $Id: //depot/rel/Eaglenest/Xtensa/OS/hal/windowspill_asm.S#1 $ + * Copyright (c) 1999-2010 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + + .file "xtensa_windowspill.S" + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include "xtensa_abi.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _xtensa_window_spill + * + * Description: + * Spill live register windows to the stack. + * + * All non-spilled register windows will be spilled. Beware that this may + * include a4..a15 of the current window, so generally these should not + * have been clobbered by the caller if it is at all possible that these + * registers are part of an unspilled window (it often is possible) + * (otherwise the spilled stack would be invalid). + * + * THIS MEANS: the caller is responsible for saving a0-a15 but the caller + * must leave a4-a15 intact when control is transferred here. + * + * It may be reentrant (but stack pointer is invalid during execution due + * to window rotations, so can't take interrupts and exceptions in the + * usual manner, so ... what does reentrancy really mean here?). + * + * Required entry conditions: + * PS.WOE = 0 + * PS.INTLEVEL >= XCHAL_EXCM_LEVEL + * a1 = valid stack pointer (note: some regs may be spilled at a1-16) + * a0 = return PC (usually set by call0 or callx0 when calling this function) + * a2,a3 undefined + * a4 thru a15 valid, if they are part of window(s) to be spilled + * (Current window a0..a15 saved if necessary.) + * WINDOWSTART[WINDOWBASE] = 1 + * + * Exit conditions: + * PS.WOE, PS.INTLEVEL = same as on entry + * WINDOWBASE = same as on entry + * WINDOWSTART updated to reflect spilled windows + * (equals 1< successful + * (WINDOWSTART = 1< invalid WINDOWSTART (WINDOWBASE bit not set) + * (WINDOWSTART unchanged) + * 2 --> invalid window size (not 4, 8 or 12 regs) + * (WINDOWSTART bits of successfully spilled + * windows are cleared, others left intact) + * a3 clobbered + * a4,a5,a8,a9,a12,a13 = same as on entry + * a6,a7,a10,a11,a14,a15 clobbered if they were part of window(s) + * to be spilled, otherwise they are the same as on entry + * loop registers (LCOUNT,LBEG,LEND) are NOT affected (they were in + * earlier versions) + * SAR clobbered + * + ****************************************************************************/ + + .text + .align 4 + .global _xtensa_window_spill + +_xtensa_window_spill: + +#ifndef XCHAL_HAVE_WINDOWED + /* Nothing to do -- window option was not selected. */ + + movi a2, 0 /* Always report success */ + ret + +#else /* XCHAL_HAVE_WINDOWED */ +# define WSBITS (XCHAL_NUM_AREGS / 4) /* Width of WINDOWSTART register in bits */ +# define WBBITS (XCHAL_NUM_AREGS_LOG2 - 2) /* Width of WINDOWBASE register in bits */ + + /* + * Rearrange (rotate) window start bits relative to the current + * window (WINDOWBASE). WINDOWSTART currently looks like this: + * + * a15-a0 + * NAREG-1 | | 0 + * | vvvv | + * xxxxxxxxxx1yyyyy + * ^ + * | + * WINDOWBASE + * + * The start bit pointed to by WINDOWBASE must be set + * (we return an error if it isn't), as it corresponds + * to the start of the current window (shown as a0-a15). + * + * We want the window start bits rotated to look like this: + * 1yyyyyxxxxxxxxxx + * + * Note that there is one start bit for every four registers; + * and the total number of registers (NAREG) can be 32 or 64; + * so the number of start bits in WINDOWSTART is NAREG/4, + * and the size of WINDOWSTART can be 8 or 16. + */ + + rsr a2, WINDOWBASE + addi a2, a2, 1 + ssr a2 /* sar = WINDOWBASE + 1 */ + rsr a3, WINDOWSTART + srl a2, a3 /* a2 is 0... | 000000xxxxxxxxxx = WINDOWSTART >> sar */ + sll a3, a3 /* a3 is 1yyyyy0000000000 | 0... = WINDOWSTART << (32 - sar) */ + bgez a3, .Linvalid_ws /* verify that msbit is indeed set + + srli a3, a3, 32-WSBITS /* a3 is 0... | 1yyyyy0000000000 = a3 >> (32-NAREG/4) */ + or a2, a2, a3 /* a2 is 0... | 1yyyyyxxxxxxxxxx */ + + /* FIND THE FIRST ONE + * + * Now we have (in a2) the window start bits rotated in order + * from oldest (closest to lsbit) to current (msbit set). + * Each start bit (that is set), other than the current one, + * corresponds to a window frame to spill. + * + * Now find the first start bit, ie. the first frame to spill, + * by looking for the first bit set in a2 (from lsbit side). + */ + +#if XCHAL_HAVE_NSA + neg a3, a2 /* Keep only the least-significant bit set of a2 ... */ + and a3, a3, a2 /* ... in a3 */ + nsau a3, a3 /* Get index of that bit, numbered from msbit (32 if absent) */ + ssl a3 /* Set sar = 32 - a3 = bit index numbered from lsbit + 1 */ +#else /* XCHAL_HAVE_NSA */ + wsr a2, WINDOWSTART /* temporarily save rotated start bits + * (we can use WINDOWSTART because WOE=0) */ + + /* NOTE: this could be optimized a bit, by explicit coding rather than the macro. + */ + + find_ls_one a3, a2 /* Set a3 to index of lsmost bit set in a2 (a2 clobbered) */ + + addi a2, a3, 1 /* Index+1 */ + ssr a2 /* Set sar = index + 1 */ + rsr a2, WINDOWSTART /* Restore a2 (rotated start bits) */ +#endif /* XCHAL_HAVE_NSA */ + + srl a2, a2 /* Right-justify the rotated start bits (dropping lsbit set) */ + wsr a2, WINDOWSTART /* Save rotated + justified window start bits, + * because a2 will disappear when modifying WINDOWBASE + * again, we can use WINDOWSTART because WOE=0 */ + + /* Rotate WindowBase so that a0 of the next window to spill is in a4 + * (ie. leaving us with a2 and a3 to play with, because a0 and a1 + * may be those of the original window which we must preserve). + */ + + rsr a2, WINDOWBASE + +#if XCHAL_HAVE_NSA + addi a2, a2, 31 + sub a3, a2, a3 /* a3 = WINDOWBASE + index = WINDOWBASE + (31 - msbit_index) */ +#else /* XCHAL_HAVE_NSA */ + add a3, a2, a3 /* a3 = WINDOWBASE + index */ +#endif /* XCHAL_HAVE_NSA */ + + wsr a 3, WINDOWBASE /* Effectively do: rotw index */ + rsync /* Wait for write to WINDOWBASE to complete */ + + /* Now our registers have changed! */ + + rsr a2, WINDOWSTART /* Restore a2 (rotated + justified window start bits) */ + + /* We are now ready to start the window spill loop. + * Relative to the above, a2 and WINDOWBASE are now as follows: + * + * 1yyyyyxxxxxxxxxx = rotated start bits as shown above + * 1yyyyyxxxx100000 = actual rotated start bits (example) + * 0000001yyyyyxxxx ^ = a2 = rotated + justified start bits + * ^ xxx1^ = window being spilled + * ^ ^ + * | | + * original current + * WINDOWBASE WINDOWBASE + * + * The first window to spill (save) starts at what is now a4. + * The spill loop maintains the adjusted start bits in a2, + * shifting them right as each window is spilled. + */ + +.Lspill_loop: + /* Top of save loop. */ + /* Find the size of this call and branch to the appropriate save routine. */ + + beqz a2, .Ldone /* If no start bit remaining, we're done */ + bbsi.l a2, 0, .Lspill4 /* If next start bit is set, it's a call4 */ + bbsi.l a2, 1, .Lspill8 /* If 2nd next bit set, it's a call8 */ + bbsi.l a2, 2, .Lspill12 /* If 3rd next bit set, it's a call12 */ + j .Linvalid_window /* Else it's an invalid window! */ + + /* SAVE A CALL4 */ + +.Lspill4: + addi a3, a9, -16 /* a3 gets call[i+1]'s sp - 16 */ + s32i a4, a3, 0 /* Store call[i]'s a0 */ + s32i a5, a3, 4 /* Store call[i]'s a1 */ + s32i a6, a3, 8 /* Store call[i]'s a2 */ + s32i a7, a3, 12 /* Store call[i]'s a3 */ + + srli a6, a2, 1 /* Move and shift the start bits */ + rotw 1 /* Rotate the window */ + + j .Lspill_loop + + /* SAVE A CALL8 */ + +.Lspill8: + addi a3, a13, -16 /* a0 gets call[i+1]'s sp - 16 */ + s32i a4, a3, 0 /* Store call[i]'s a0 */ + s32i a5, a3, 4 /* Store call[i]'s a1 */ + s32i a6, a3, 8 /* Store call[i]'s a2 */ + s32i a7, a3, 12 /* Store call[i]'s a3 */ + + addi a3, a5, -12 /* Call[i-1]'s sp address */ + l32i a3, a3, 0 /* a3 is call[i-1]'s sp + * (load slot) */ + addi a3, a3, -32 /* a3 points to our spill area */ + + s32i a8, a3, 0 /* Store call[i]'s a4 */ + s32i a9, a3, 4 /* Store call[i]'s a5 */ + s32i a10, a3, 8 /* Store call[i]'s a6 */ + s32i a11, a3, 12 /* Store call[i]'s a7 */ + + srli a10, a2, 2 /* Move and shift the start bits */ + rotw 2 /* Rotate the window */ + + j .Lspill_loop + + /* SAVE A CALL12 */ + +.Lspill12: + rotw 1 /* Rotate to see call[i+1]'s sp */ + + addi a13, a13, -16 /* Set to the reg save area */ + s32i a0, a13, 0 /* Store call[i]'s a0 */ + s32i a1, a13, 4 /* Store call[i]'s a1 */ + s32i a2, a13, 8 /* Store call[i]'s a2 */ + s32i a3, a13, 12 /* Store call[i]'s a3 */ + + addi a3, a1, -12 /* Call[i-1]'s sp address */ + l32i a3, a3, 0 /* a3 has call[i-1]'s sp */ + addi a13, a13, 16 /* Restore call[i+1]'s sp (here to fill load slot) */ + addi a3, a3, -48 /* a3 points to our save area */ + + s32i a4, a3, 0 /* Store call[i]'s a4 */ + s32i a5, a3, 4 /* Store call[i]'s a5 */ + s32i a6, a3, 8 /* Store call[i]'s a6 */ + s32i a7, a3, 12 /* Store call[i]'s a7 */ + s32i a8, a3, 16 /* Store call[i]'s a4 */ + s32i a9, a3, 20 /* Store call[i]'s a5 */ + s32i a10, a3, 24 /* Store call[i]'s a6 */ + s32i a11, a3, 28 /* Store call[i]'s a7 */ + + rotw -1 /* Rotate to see start bits (a2) */ + srli a14, a2, 3 /* Move and shift the start bits */ + rotw 3 /* Rotate to next window */ + + j .Lspill_loop + +.Ldone: + rotw 1 /* Back to the original window */ + rsr a2, WINDOWBASE /* Get (original) window base */ + ssl a2 /* Setup for shift left by WINDOWBASE */ + movi a2, 1 + sll a2, a2 /* Compute new WINDOWSTART = 1<dram0_0_seg .dram0.data : { + /* .data initialized on power-up in ROMed configurations. */ + _sdata = ABSOLUTE(.); KEEP(*(.data)) KEEP(*(.data.*)) @@ -102,6 +110,9 @@ SECTIONS *(.dram1 .dram1.*) _edata = ABSOLUTE(.); . = ALIGN(4); + + /* Heap starts at the end of .data */ + _sheap = ABSOLUTE(.); } >dram0_0_seg @@ -122,7 +133,8 @@ SECTIONS . = (. + 3) & ~ 3; - /* C++ constructor and destructor tables, properly ordered: */ + /* C++ constructor and destructor tables, properly ordered: */ + __sinit = ABSOLUTE(.); KEEP (*crtbegin.o(.ctors)) KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) @@ -134,7 +146,7 @@ SECTIONS KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) - /* C++ exception handlers table: */ + /* C++ exception handlers table: */ __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); *(.xt_except_desc) -- GitLab From 6ff1c96017f0abc891d9a700c744dfc5b0718d4d Mon Sep 17 00:00:00 2001 From: Ramtin Amin Date: Mon, 31 Oct 2016 18:41:36 -0600 Subject: [PATCH 276/734] LM32: First commit adds only reviewed architecture header files --- arch/Kconfig | 9 ++ arch/misoc/include/arch.h | 0 arch/misoc/include/irq.h | 80 ++++++++++++ arch/misoc/include/limits.h | 88 +++++++++++++ arch/misoc/include/lm32/irq.h | 193 ++++++++++++++++++++++++++++ arch/misoc/include/lm32/syscall.h | 207 ++++++++++++++++++++++++++++++ arch/misoc/include/lm32/types.h | 94 ++++++++++++++ arch/misoc/include/syscall.h | 88 +++++++++++++ arch/misoc/include/types.h | 94 ++++++++++++++ 9 files changed, 853 insertions(+) create mode 100644 arch/misoc/include/arch.h create mode 100644 arch/misoc/include/irq.h create mode 100644 arch/misoc/include/limits.h create mode 100644 arch/misoc/include/lm32/irq.h create mode 100644 arch/misoc/include/lm32/syscall.h create mode 100644 arch/misoc/include/lm32/types.h create mode 100644 arch/misoc/include/syscall.h create mode 100644 arch/misoc/include/types.h diff --git a/arch/Kconfig b/arch/Kconfig index 32ecb06410..0125994830 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -39,6 +39,13 @@ config ARCH_MIPS ---help--- MIPS architectures (PIC32) +config ARCH_MISOC + bool "MISOC" + select ARCH_HAVE_INTERRUPTSTACK + select ARCH_HAVE_CUSTOMOPT + ---help--- + MISOC + config ARCH_RGMP bool "RGMP" ---help--- @@ -99,6 +106,7 @@ config ARCH default "avr" if ARCH_AVR default "hc" if ARCH_HC default "mips" if ARCH_MIPS + default "misoc" if ARCH_MISOC default "rgmp" if ARCH_RGMP default "renesas" if ARCH_RENESAS default "risc-v" if ARCH_RISCV @@ -112,6 +120,7 @@ source arch/arm/Kconfig source arch/avr/Kconfig source arch/hc/Kconfig source arch/mips/Kconfig +source arch/misoc/Kconfig source arch/rgmp/Kconfig source arch/renesas/Kconfig source arch/risc-v/Kconfig diff --git a/arch/misoc/include/arch.h b/arch/misoc/include/arch.h new file mode 100644 index 0000000000..e69de29bb2 diff --git a/arch/misoc/include/irq.h b/arch/misoc/include/irq.h new file mode 100644 index 0000000000..1fbf884fc3 --- /dev/null +++ b/arch/misoc/include/irq.h @@ -0,0 +1,80 @@ +/**************************************************************************** + * arch/misoc/include/irq.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_MISOC_INCLUDE_IRQ_H +#define __ARCH_MISOC_INCLUDE_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NR_IRQS 32 + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +irqstate_t up_irq_save(void); +void up_irq_restore(irqstate_t flags); + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_MISOC_INCLUDE_IRQ_H */ diff --git a/arch/misoc/include/limits.h b/arch/misoc/include/limits.h new file mode 100644 index 0000000000..12dd86efb2 --- /dev/null +++ b/arch/misoc/include/limits.h @@ -0,0 +1,88 @@ +/**************************************************************************** + * arch/misoc/include/limits.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MISOC_INCLUDE_LIMITS_H +#define __ARCH_MISOC_INCLUDE_LIMITS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CHAR_BIT 8 +#define SCHAR_MIN (-SCHAR_MAX - 1) +#define SCHAR_MAX 127 +#define UCHAR_MAX 255 + +/* These could be different on machines where char is unsigned */ + +#ifdef __CHAR_UNSIGNED__ +#define CHAR_MIN 0 +#define CHAR_MAX UCHAR_MAX +#else +#define CHAR_MIN SCHAR_MIN +#define CHAR_MAX SCHAR_MAX +#endif + +#define SHRT_MIN (-SHRT_MAX - 1) +#define SHRT_MAX 32767 +#define USHRT_MAX 65535U + +/* Integer is four bytes */ + +#define INT_MIN (-INT_MAX - 1) +#define INT_MAX 2147483647 +#define UINT_MAX 4294967295U + +/* These change on 32-bit and 64-bit platforms */ + +#define LONG_MIN (-LONG_MAX - 1) +#define LONG_MAX 2147483647L +#define ULONG_MAX 4294967295UL + +#define LLONG_MIN (-LLONG_MAX - 1) +#define LLONG_MAX 9223372036854775807LL +#define ULLONG_MAX 18446744073709551615ULL + +/* A pointer is four bytes */ + +#define PTR_MIN (-PTR_MAX - 1) +#define PTR_MAX 2147483647 +#define UPTR_MAX 4294967295U + +#endif /* __ARCH_MISOC_INCLUDE_LIMITS_H */ diff --git a/arch/misoc/include/lm32/irq.h b/arch/misoc/include/lm32/irq.h new file mode 100644 index 0000000000..a98bcab8e3 --- /dev/null +++ b/arch/misoc/include/lm32/irq.h @@ -0,0 +1,193 @@ +/**************************************************************************** + * arch/misoc/include/lm32/syscall.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MISOC_INCLUDE_LM32_IRQ_H +#define __ARCH_MISOC_INCLUDE_LM32_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Registers */ + +#define REG_X0_NDX 0 /* Holds the value zero */ +#define REG_X1_NDX 1 /* General-purpose/argument 0/return value 0 */ +#define REG_X2_NDX 2 /* General-purpose/argument 1/return value 1 */ +#define REG_X3_NDX 3 /* General-purpose/argument 2 */ +#define REG_X4_NDX 4 /* General-purpose/argument 3 */ +#define REG_X5_NDX 5 /* General-purpose/argument 4 */ +#define REG_X6_NDX 6 /* General-purpose/argument 5 */ +#define REG_X7_NDX 7 /* General-purpose/argument 6 */ +#define REG_X8_NDX 8 /* General-purpose/argument 7 */ +#define REG_X9_NDX 9 /* General-purpose */ +#define REG_X10_NDX 10 /* General-purpose */ +#define REG_X11_NDX 11 /* General-purpose */ +#define REG_X12_NDX 12 /* General-purpose */ +#define REG_X13_NDX 13 /* General-purpose */ +#define REG_X14_NDX 14 /* General-purpose */ +#define REG_X15_NDX 15 /* General-purpose */ +#define REG_X16_NDX 16 /* General-purpose */ +#define REG_X17_NDX 17 /* General-purpose */ +#define REG_X18_NDX 18 /* General-purpose */ +#define REG_X19_NDX 19 /* General-purpose */ +#define REG_X20_NDX 20 /* General-purpose */ +#define REG_X21_NDX 21 /* General-purpose */ +#define REG_X22_NDX 22 /* General-purpose */ +#define REG_X23_NDX 23 /* General-purpose */ +#define REG_X24_NDX 24 /* General-purpose */ +#define REG_X25_NDX 25 /* General-purpose */ +#define REG_X26_NDX 26 /* General-purpose/global pointer */ +#define REG_X27_NDX 27 /* General-purpose/frame pointer */ +#define REG_X28_NDX 28 /* Stack pointer */ +#define REG_X29_NDX 29 /* General-purpose/return address */ +#define REG_X30_NDX 30 /* Exception address */ +#define REG_X31_NDX 31 /* Breakpoint address */ + +/* Interrupt Context register */ + +#define XCPTCONTEXT_REGS 32 +#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS) + +#ifdef __ASSEMBLY__ +# define REG_X0 (4*REG_X0_NDX) +# define REG_X1 (4*REG_X1_NDX) +# define REG_X2 (4*REG_X2_NDX) +# define REG_X3 (4*REG_X3_NDX) +# define REG_X4 (4*REG_X4_NDX) +# define REG_X5 (4*REG_X5_NDX) +# define REG_X6 (4*REG_X6_NDX) +# define REG_X7 (4*REG_X7_NDX) +# define REG_X8 (4*REG_X8_NDX) +# define REG_X9 (4*REG_X9_NDX) +# define REG_X10 (4*REG_X10_NDX) +# define REG_X11 (4*REG_X11_NDX) +# define REG_X12 (4*REG_X12_NDX) +# define REG_X13 (4*REG_X13_NDX) +# define REG_X14 (4*REG_X14_NDX) +# define REG_X15 (4*REG_X15_NDX) +# define REG_X16 (4*REG_X16_NDX) +# define REG_X17 (4*REG_X17_NDX) +# define REG_X18 (4*REG_X18_NDX) +# define REG_X19 (4*REG_X19_NDX) +# define REG_X20 (4*REG_X20_NDX) +# define REG_X21 (4*REG_X21_NDX) +# define REG_X22 (4*REG_X22_NDX) +# define REG_X23 (4*REG_X23_NDX) +# define REG_X24 (4*REG_X24_NDX) +# define REG_X25 (4*REG_X25_NDX) +# define REG_X26 (4*REG_X26_NDX) +# define REG_X27 (4*REG_X27_NDX) +# define REG_X28 (4*REG_X28_NDX) +# define REG_X29 (4*REG_X29_NDX) +# define REG_X30 (4*REG_X30_NDX) +# define REG_X31 (4*REG_X31_NDX) +#else +# define REG_X0 REG_X0_NDX +# define REG_X1 REG_X1_NDX +# define REG_X2 REG_X2_NDX +# define REG_X3 REG_X3_NDX +# define REG_X4 REG_X4_NDX +# define REG_X5 REG_X5_NDX +# define REG_X6 REG_X6_NDX +# define REG_X7 REG_X7_NDX +# define REG_X8 REG_X8_NDX +# define REG_X9 REG_X9_NDX +# define REG_X10 REG_X10_NDX +# define REG_X11 REG_X11_NDX +# define REG_X12 REG_X12_NDX +# define REG_X13 REG_X13_NDX +# define REG_X14 REG_X14_NDX +# define REG_X15 REG_X15_NDX +# define REG_X16 REG_X16_NDX +# define REG_X17 REG_X17_NDX +# define REG_X18 REG_X18_NDX +# define REG_X19 REG_X19_NDX +# define REG_X20 REG_X20_NDX +# define REG_X21 REG_X21_NDX +# define REG_X22 REG_X22_NDX +# define REG_X23 REG_X23_NDX +# define REG_X24 REG_X24_NDX +# define REG_X25 REG_X25_NDX +# define REG_X26 REG_X26_NDX +# define REG_X27 REG_X27_NDX +# define REG_X28 REG_X28_NDX +# define REG_X29 REG_X29_NDX +# define REG_X30 REG_X30_NDX +# define REG_X31 REG_X31_NDX +#endif + +/* Register aliases */ + +#define REG_GP REG_X26 +#define REG_FP REG_X27 +#define REG_SP REG_X28 +#define REG_RA REG_X29 +#define REG_EA REG_X30 +#define REG_BA REG_X31 + +#define REG_EPC REG_X30 + +#define REG_A0 REG_X1 +#define REG_A1 REG_X2 +#define REG_A2 REG_X3 +#define REG_A3 REG_X4 +#define REG_A4 REG_X5 +#define REG_A5 REG_X6 +#define REG_A6 REG_X7 +#define REG_A7 REG_X8 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +struct xcptcontext +{ + /* Register save area */ + + uint32_t regs[XCPTCONTEXT_REGS]; +}; + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_MISOC_INCLUDE_LM32_IRQ_H */ diff --git a/arch/misoc/include/lm32/syscall.h b/arch/misoc/include/lm32/syscall.h new file mode 100644 index 0000000000..7c0c2b1066 --- /dev/null +++ b/arch/misoc/include/lm32/syscall.h @@ -0,0 +1,207 @@ +/**************************************************************************** + * arch/misoc/include/lm32/syscall.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through include/syscall.h or include/sys/sycall.h + */ + +#ifndef __ARCH_MISOC_INCLUDE_LM32_SYSCALL_H +#define __ARCH_MISOC_INCLUDE_LM32_SYSCALL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SYS_syscall 0x00 + +/* Configuration ********************************************************************/ +/* SYS call 1 and 2 are defined for internal use by the RISC-V port (see + * arch/riscv/include/mips32/syscall.h). In addition, SYS call 3 is the return from + * a SYS call in kernel mode. The first four syscall values must, therefore, be + * reserved (0 is not used). + */ + +#ifdef CONFIG_BUILD_KERNEL +# ifndef CONFIG_SYS_RESERVED +# error "CONFIG_SYS_RESERVED must be defined to the value 4" +# elif CONFIG_SYS_RESERVED != 4 +# error "CONFIG_SYS_RESERVED must have the value 4" +# endif +#endif + +/* sys_call macros ******************************************************************/ + +#ifndef __ASSEMBLY__ + +/* Context switching system calls ***************************************************/ + +/* SYS call 0: (not used) */ + +/* SYS call 1: + * + * void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function; + */ + +#define SYS_restore_context (1) +#define up_fullcontextrestore(restoreregs) \ + (void)sys_call1(SYS_restore_context, (uintptr_t)restoreregs) + +/* SYS call 2: + * + * void up_switchcontext(uint32_t *saveregs, uint32_t *restoreregs); + */ + +#define SYS_switch_context (2) +#define up_switchcontext(saveregs, restoreregs) \ + (void)sys_call2(SYS_switch_context, (uintptr_t)saveregs, (uintptr_t)restoreregs) + +#ifdef CONFIG_BUILD_KERNEL +/* SYS call 3: + * + * void up_syscall_return(void); + */ + +#define SYS_syscall_return (3) +#define up_syscall_return() (void)sys_call0(SYS_syscall_return) + +#endif +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: up_syscall0 + * + * Description: + * System call SYS_ argument and no additional parameters. + * + ****************************************************************************/ + +uintptr_t sys_call0(unsigned int nbr); + +/**************************************************************************** + * Name: up_syscall1 + * + * Description: + * System call SYS_ argument and one additional parameter. + * + ****************************************************************************/ + +uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1); + +/**************************************************************************** + * Name: up_syscall2 + * + * Description: + * System call SYS_ argument and two additional parameters. + * + ****************************************************************************/ + +uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1, uintptr_t parm2); + +/**************************************************************************** + * Name: up_syscall3 + * + * Description: + * System call SYS_ argument and three additional parameters. + * + ****************************************************************************/ + +uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1, uintptr_t parm2, + uintptr_t parm3); + +/**************************************************************************** + * Name: up_syscall4 + * + * Description: + * System call SYS_ argument and four additional parameters. + * + ****************************************************************************/ + +uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1, uintptr_t parm2, + uintptr_t parm3, uintptr_t parm4); + +/**************************************************************************** + * Name: up_syscall5 + * + * Description: + * System call SYS_ argument and five additional parameters. + * + ****************************************************************************/ + +uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1, uintptr_t parm2, + uintptr_t parm3, uintptr_t parm4, uintptr_t parm5); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MISOC_INCLUDE_LM32_SYSCALL_H */ diff --git a/arch/misoc/include/lm32/types.h b/arch/misoc/include/lm32/types.h new file mode 100644 index 0000000000..dbaaff28d2 --- /dev/null +++ b/arch/misoc/include/lm32/types.h @@ -0,0 +1,94 @@ +/**************************************************************************** + * arch/misoc/include/lm32/types.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through stdint.h + */ + +#ifndef __ARCH_MISOC_INCLUDE_LM32_TYPES_H +#define __ARCH_MISOC_INCLUDE_LM32_TYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Type Declarations + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* These are the sizes of the standard integer types. NOTE that these type + * names have a leading underscore character. This file will be included + * (indirectly) by include/stdint.h and typedef'ed to the final name without + * the underscore character. This roundabout way of doings things allows + * the stdint.h to be removed from the include/ directory in the event that + * the user prefers to use the definitions provided by their toolchain header + * files + */ + +typedef signed char _int8_t; +typedef unsigned char _uint8_t; + +typedef signed short _int16_t; +typedef unsigned short _uint16_t; + +typedef signed int _int32_t; +typedef unsigned int _uint32_t; + +typedef signed long long _int64_t; +typedef unsigned long long _uint64_t; +#define __INT64_DEFINED + +/* A pointer is 4 bytes */ + +typedef signed int _intptr_t; +typedef unsigned int _uintptr_t; + +/* This is the size of the interrupt state save returned by up_irq_save(). */ + +typedef unsigned int irqstate_t; + +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_MISOC_INCLUDE_LM32_TYPES_H */ diff --git a/arch/misoc/include/syscall.h b/arch/misoc/include/syscall.h new file mode 100644 index 0000000000..3a8f2e9df0 --- /dev/null +++ b/arch/misoc/include/syscall.h @@ -0,0 +1,88 @@ +/**************************************************************************** + * arch/misoc/include/syscall.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through include/syscall.h or include/sys/sycall.h + */ + +#ifndef __ARCH_MISOC_INCLUDE_SYSCALL_H +#define __ARCH_MISOC_INCLUDE_SYSCALL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include RISC-V architecture-specific syscall macros */ + +#ifdef CONFIG_ARCH_MISOC +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_MISOC_INCLUDE_SYSCALL_H */ diff --git a/arch/misoc/include/types.h b/arch/misoc/include/types.h new file mode 100644 index 0000000000..f63ab15f19 --- /dev/null +++ b/arch/misoc/include/types.h @@ -0,0 +1,94 @@ +/**************************************************************************** + * arch/misoc/include/types.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through stdint.h + */ + +#ifndef __ARCH_MISOC_INCLUDE_TYPESL_H +#define __ARCH_MISOC_INCLUDE_TYPESL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Type Declarations + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* These are the sizes of the standard integer types. NOTE that these type + * names have a leading underscore character. This file will be included + * (indirectly) by include/stdint.h and typedef'ed to the final name without + * the underscore character. This roundabout way of doings things allows + * the stdint.h to be removed from the include/ directory in the event that + * the user prefers to use the definitions provided by their toolchain header + * files + */ + +typedef signed char _int8_t; +typedef unsigned char _uint8_t; + +typedef signed short _int16_t; +typedef unsigned short _uint16_t; + +typedef signed int _int32_t; +typedef unsigned int _uint32_t; + +typedef signed long long _int64_t; +typedef unsigned long long _uint64_t; +#define __INT64_DEFINED + +/* A pointer is 4 bytes */ + +typedef signed int _intptr_t; +typedef unsigned int _uintptr_t; + +/* This is the size of the interrupt state save returned by up_irq_save(). */ + +typedef unsigned int irqstate_t; + +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_MISOC_INCLUDE_TYPESL_H */ -- GitLab From 6662c75679a7e5b03b9076c24cdfe5c8267f8e70 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 31 Oct 2016 19:29:30 -0600 Subject: [PATCH 277/734] LM32: Add arch/misoc/Kconfig file --- arch/misoc/Kconfig | 64 +++++++++++++++++++++++++++++++++++ arch/misoc/include/lm32/irq.h | 2 +- 2 files changed, 65 insertions(+), 1 deletion(-) create mode 100644 arch/misoc/Kconfig diff --git a/arch/misoc/Kconfig b/arch/misoc/Kconfig new file mode 100644 index 0000000000..7f3ae0dab4 --- /dev/null +++ b/arch/misoc/Kconfig @@ -0,0 +1,64 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_MISOC + +choice + prompt "Misoc Chip Selection" + default ARCH_CHIP_LM32 + +config ARCH_CHIP_LM32 + bool "LM32" + select MISOC_HAVE_UART0 + ---help--- + LM32 Chip Selected + +config ARCH_CHIP_MOR1K + bool "MOR1K" + ---help--- + MOR1K Chip Selected + +endchoice # Misoc Chip Selection + +config ARCH_CHIP + string + default "lm32" if ARCH_CHIP_LM32 + +menu "MISOC Peripheral Support" + +# These "hidden" settings determine is a peripheral option is available for the +# selection MCU + +config MISOC_HAVE_UART0 + bool + default n + select UART0_SERIALDRIVER + +config MISOC_UART0 + bool "UART0" + default n + select ARCH_HAVE_UART0 + select MISOC_UART + +endmenu # MISOC Peripheral Support + +config MISOC_UART + bool + +config MISOC_UART_RX_BUF_SIZE + int "UART RX Bufer size" + default 64 + depends on MISOC_UART + ---help--- + Size of RX buffers for MISOC UARTs + +config MISOC_UART_TX_BUF_SIZE + int "UART TX Bufer size" + default 64 + depends on MISOC_UART + ---help--- + Size of TX buffers for MISOC UARTs + +endif # ARCH_MISOC diff --git a/arch/misoc/include/lm32/irq.h b/arch/misoc/include/lm32/irq.h index a98bcab8e3..f12fcb7db6 100644 --- a/arch/misoc/include/lm32/irq.h +++ b/arch/misoc/include/lm32/irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/misoc/include/lm32/syscall.h + * arch/misoc/include/lm32/irq.h * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt -- GitLab From 6a78c0f1130a9c314aa00d7a5c2531ffe8d00ab0 Mon Sep 17 00:00:00 2001 From: Ramtin Amin Date: Tue, 1 Nov 2016 07:20:44 -0600 Subject: [PATCH 278/734] LM32: Add Kconfig files --- arch/misoc/Kconfig | 9 ++ arch/misoc/include/lm32/irq.h | 1 + arch/misoc/include/lm32/syscall.h | 1 + arch/misoc/include/lm32/types.h | 1 + arch/misoc/src/Makefile | 189 ++++++++++++++++++++++++++++++ arch/misoc/src/common/Kconfig | 8 ++ arch/misoc/src/lm32/Kconfig | 8 ++ 7 files changed, 217 insertions(+) create mode 100644 arch/misoc/src/Makefile create mode 100644 arch/misoc/src/common/Kconfig create mode 100644 arch/misoc/src/lm32/Kconfig diff --git a/arch/misoc/Kconfig b/arch/misoc/Kconfig index 7f3ae0dab4..74a2a7649b 100644 --- a/arch/misoc/Kconfig +++ b/arch/misoc/Kconfig @@ -25,6 +25,7 @@ endchoice # Misoc Chip Selection config ARCH_CHIP string default "lm32" if ARCH_CHIP_LM32 + default "mor1k" if ARCH_CHIP_MOR1K menu "MISOC Peripheral Support" @@ -61,4 +62,12 @@ config MISOC_UART_TX_BUF_SIZE ---help--- Size of TX buffers for MISOC UARTs +source arch/misoc/src/common/Kconfig +ifdef ARCH_CHIP_LM32 +source arch/misoc/src/lm32/Kconfig +endif +ifdef ARCH_CHIP_MOR1K +source arch/misoc/src/mor1k/Kconfig +endif + endif # ARCH_MISOC diff --git a/arch/misoc/include/lm32/irq.h b/arch/misoc/include/lm32/irq.h index f12fcb7db6..e73d3815d5 100644 --- a/arch/misoc/include/lm32/irq.h +++ b/arch/misoc/include/lm32/irq.h @@ -3,6 +3,7 @@ * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt + * Ramtin Amin * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/misoc/include/lm32/syscall.h b/arch/misoc/include/lm32/syscall.h index 7c0c2b1066..9e4b0d9ee0 100644 --- a/arch/misoc/include/lm32/syscall.h +++ b/arch/misoc/include/lm32/syscall.h @@ -3,6 +3,7 @@ * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt + * Ramtin Amin * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/misoc/include/lm32/types.h b/arch/misoc/include/lm32/types.h index dbaaff28d2..0e113100f9 100644 --- a/arch/misoc/include/lm32/types.h +++ b/arch/misoc/include/lm32/types.h @@ -3,6 +3,7 @@ * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt + * Ramtin Amin * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/misoc/src/Makefile b/arch/misoc/src/Makefile new file mode 100644 index 0000000000..6a92f22910 --- /dev/null +++ b/arch/misoc/src/Makefile @@ -0,0 +1,189 @@ +############################################################################ +# arch/misoc/src/Makefile +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs +-include chip/Make.defs + +ARCH_SUBDIR = lm32 + +ifeq ($(CONFIG_WINDOWS_NATIVE),y) + ARCH_SRCDIR = $(TOPDIR)\arch\$(CONFIG_ARCH)\src + NUTTX = "$(TOPDIR)\nuttx$(EXEEXT)" + INCLUDES += -I "$(ARCH_SRCDIR)\chip" + INCLUDES += -I "$(ARCH_SRCDIR)\common" + INCLUDES += -I "$(ARCH_SRCDIR)\generated" + INCLUDES += -I "$(ARCH_SRCDIR)\$(ARCH_SUBDIR)" + INCLUDES += -I "$(TOPDIR)\sched" +else + ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src +ifeq ($(WINTOOL),y) + NUTTX = "${shell cygpath -w $(TOPDIR)/nuttx$(EXEEXT)}" + INCLUDES += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" + INCLUDES += -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" + INCLUDES += -I "${shell cygpath -w $(ARCH_SRCDIR)/generated}" + INCLUDES += -I "${shell cygpath -w $(ARCH_SRCDIR)/$(ARCH_SUBDIR)}" + INCLUDES += -I "${shell cygpath -w $(TOPDIR)/sched}" +else + NUTTX = "$(TOPDIR)/nuttx$(EXEEXT)" + INCLUDES += -I "$(ARCH_SRCDIR)/chip" + INCLUDES += -I "$(ARCH_SRCDIR)/common" + INCLUDES += -I "$(ARCH_SRCDIR)/generated" + INCLUDES += -I "$(ARCH_SRCDIR)/$(ARCH_SUBDIR)" + INCLUDES += -I "$(TOPDIR)/sched" +endif +endif + +CPPFLAGS += $(INCLUDES) $(EXTRADEFINES) +CFLAGS += $(INCLUDES) $(EXTRADEFINES) +CXXFLAGS += $(INCLUDES) $(EXTRADEFINES) +AFLAGS += $(INCLUDES) $(EXTRADEFINES) + +HEAD_OBJ = $(HEAD_ASRC:.S=$(OBJEXT)) +STARTUP_OBJS ?= $(HEAD_OBJ) + +ASRCS = $(CHIP_ASRCS) $(CMN_ASRCS) +AOBJS = $(ASRCS:.S=$(OBJEXT)) + +CSRCS = $(CHIP_CSRCS) $(CMN_CSRCS) +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +# Override in Make.defs if linker is not 'ld' + +LDSTARTGROUP ?= --start-group +LDENDGROUP ?= --end-group + +LDFLAGS += $(ARCHSCRIPT) +EXTRA_LIBS ?= +LINKLIBS ?= + +ifeq ($(CONFIG_WINDOWS_NATIVE),y) + BOARDMAKE = $(if $(wildcard .\board\Makefile),y,) + LIBPATHS += -L"$(TOPDIR)\lib" +ifeq ($(BOARDMAKE),y) + LIBPATHS += -L"$(TOPDIR)\arch\$(CONFIG_ARCH)\src\board" +endif + +else + BOARDMAKE = $(if $(wildcard ./board/Makefile),y,) + +ifeq ($(WINTOOL),y) + LIBPATHS += -L"${shell cygpath -w "$(TOPDIR)/lib"}" +ifeq ($(BOARDMAKE),y) + LIBPATHS += -L"${shell cygpath -w "$(TOPDIR)/arch/$(CONFIG_ARCH)/src/board"}" +endif + +else + LIBPATHS += -L"$(TOPDIR)/lib" +ifeq ($(BOARDMAKE),y) + LIBPATHS += -L"$(TOPDIR)/arch/$(CONFIG_ARCH)/src/board" +endif +endif +endif + +LDLIBS = $(patsubst %.a,%,$(patsubst lib%,-l%,$(LINKLIBS))) +ifeq ($(BOARDMAKE),y) + LDLIBS += -lboard +endif + +LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" + +VPATH = chip:common:$(ARCH_SUBDIR) + +all: $(HEAD_OBJ) libarch$(LIBEXT) + +.PHONY: board/libboard$(LIBEXT) + +$(AOBJS) $(HEAD_OBJ): %$(OBJEXT): %.S + $(call ASSEMBLE, $<, $@) + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +libarch$(LIBEXT): $(OBJS) + $(call ARCHIVE, $@, $(OBJS)) + +board/libboard$(LIBEXT): + $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" libboard$(LIBEXT) EXTRADEFINES=$(EXTRADEFINES) + +nuttx$(EXEEXT): $(HEAD_OBJ) board/libboard$(LIBEXT) + @echo "LD: nuttx toto $(LIBGCC)" + $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) -o $(NUTTX) $(HEAD_OBJ) $(EXTRA_OBJS) \ + $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LDENDGROUP) +ifneq ($(CONFIG_WINDOWS_NATIVE),y) + $(Q) $(NM) $(NUTTX) | \ + grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ + sort > $(TOPDIR)/System.map +endif + +# This is part of the top-level export target + +export_startup: board/libboard$(LIBEXT) $(STARTUP_OBJS) + $(Q) if [ -d "$(EXPORT_DIR)/startup" ]; then \ + cp -f $(STARTUP_OBJS) "$(EXPORT_DIR)/startup"; \ + else \ + echo "$(EXPORT_DIR)/startup does not exist"; \ + exit 1; \ + fi + +# Dependencies + +.depend: Makefile chip/Make.defs $(SRCS) +ifeq ($(BOARDMAKE),y) + $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" depend +endif + $(Q) $(MKDEP) --dep-path chip --dep-path common --dep-path $(ARCH_SUBDIR) \ + "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) touch $@ + +depend: .depend + +clean: +ifeq ($(BOARDMAKE),y) + $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" clean +endif + $(call DELFILE, libarch$(LIBEXT)) + $(call CLEAN) + +distclean: clean +ifeq ($(BOARDMAKE),y) + $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" distclean +endif + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + +-include Make.dep diff --git a/arch/misoc/src/common/Kconfig b/arch/misoc/src/common/Kconfig new file mode 100644 index 0000000000..6cd8cd8175 --- /dev/null +++ b/arch/misoc/src/common/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_MISOC + +endif # ARCH_MISOC diff --git a/arch/misoc/src/lm32/Kconfig b/arch/misoc/src/lm32/Kconfig new file mode 100644 index 0000000000..75814271c6 --- /dev/null +++ b/arch/misoc/src/lm32/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_LM32 + +endif # ARCH_CHIP_LM32 -- GitLab From 62b394d06fc01cc211a9c2963b4a1fd389350104 Mon Sep 17 00:00:00 2001 From: Ramtin Amin Date: Tue, 1 Nov 2016 08:10:14 -0600 Subject: [PATCH 279/734] LM32: First of many LM32 source files --- arch/misoc/src/lm32/lm32.h | 173 ++++++++++++++++++++++++ arch/misoc/src/lm32/lm32_allocateheap.c | 104 ++++++++++++++ 2 files changed, 277 insertions(+) create mode 100644 arch/misoc/src/lm32/lm32.h create mode 100644 arch/misoc/src/lm32/lm32_allocateheap.c diff --git a/arch/misoc/src/lm32/lm32.h b/arch/misoc/src/lm32/lm32.h new file mode 100644 index 0000000000..8335c6917d --- /dev/null +++ b/arch/misoc/src/lm32/lm32.h @@ -0,0 +1,173 @@ +/**************************************************************************** + * arch/misoc/src/common/lm32.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MISOC_SRC_COMMON_LM32_H +#define __ARCH_MISOC_SRC_COMMON_LM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* This is the value used to mark the stack for subsequent stack monitoring + * logic. + */ + +#define STACK_COLOR 0xdeadbeef +#define INTSTACK_COLOR 0xdeadbeef +#define HEAP_COLOR 'h' + +/* In the RISC_V model, the state is copied from the stack to the TCB, but + * only a referenced is passed to get the state from the TCB. + */ + +#define up_savestate(regs) lm32_copystate(regs, (uint32_t*)g_current_regs) +#define up_restorestate(regs) (g_current_regs = regs) + +/* Determine which (if any) console driver to use. If a console is enabled + * and no other console device is specified, then a serial console is + * assumed. + */ + +#if !defined(CONFIG_DEV_CONSOLE) || CONFIG_NFILE_DESCRIPTORS <= 0 +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +# undef CONFIG_DEV_LOWCONSOLE +# undef CONFIG_RAMLOG_CONSOLE +#else +# if defined(CONFIG_RAMLOG_CONSOLE) +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +# undef CONFIG_DEV_LOWCONSOLE +# elif defined(CONFIG_DEV_LOWCONSOLE) +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +# else +# define USE_SERIALDRIVER 1 +# define USE_EARLYSERIALINIT 1 +# endif +#endif + +/* Low-level register access */ + +#define getreg8(a) (*(volatile uint8_t *)(a)) +#define putreg8(v,a) (*(volatile uint8_t *)(a) = (v)) +#define getreg16(a) (*(volatile uint16_t *)(a)) +#define putreg16(v,a) (*(volatile uint16_t *)(a) = (v)) +#define getreg32(a) (*(volatile uint32_t *)(a)) +#define putreg32(v,a) (*(volatile uint32_t *)(a) = (v)) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +extern volatile uint32_t *g_current_regs; + +extern uint32_t g_idle_topstack; + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* Low level initialization provided by board-level logic ******************/ + +void lm32_board_initialize(void); + +/* Memory allocation ********************************************************/ + +#if CONFIG_MM_REGIONS > 1 +void lm32_add_region(void); +#endif + +/* Context switching ********************************************************/ + +void lm32_copystate(uint32_t *dest, uint32_t *src); + +/* IRQ initialization *******************************************************/ + +void lm32_irq_initialize(void); + +/* System timer *************************************************************/ + +void lm32_timer_initialize(void); +int lm32_timerisr(int irq, void *context); + +/* Software interrupts ******************************************************/ + +uint32_t lm32_swint(int irq, FAR void *context); + +/* Signal handling **********************************************************/ + +void lm32_sigdeliver(void); + +/* Atomic modification of registers *****************************************/ + +void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits); +void modifyreg16(unsigned int addr, uint16_t clearbits, uint16_t setbits); +void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits); + +/* Debug ********************************************************************/ + +void lm32_dumpstate(void); + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_MISOC_SRC_COMMON_LM32_H */ diff --git a/arch/misoc/src/lm32/lm32_allocateheap.c b/arch/misoc/src/lm32/lm32_allocateheap.c new file mode 100644 index 0000000000..4df88cecaf --- /dev/null +++ b/arch/misoc/src/lm32/lm32_allocateheap.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * arch/misoc/src/common/lm32_allocateheap.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "lm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * For the kernel build (CONFIG_BUILD_KERNEL=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the + * size of the unprotected, user-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated (and protected) by an analogous up_allocate_kheap(). + * + ****************************************************************************/ + +void up_allocate_heap(FAR void **heap_start, size_t *heap_size) +{ + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (FAR void *)g_idle_topstack; + *heap_size = CONFIG_RAM_END - g_idle_topstack; +} + +/**************************************************************************** + * Name: lm32_add_region + * + * Description: + * Memory may be added in non-contiguous chunks. Additional chunks are + * added by calling this function. + * + ****************************************************************************/ + +#if CONFIG_MM_REGIONS > 1 +void lm32_add_region(void) +{ +#warning Missing logic +} +#endif -- GitLab From 000e10470c79ba5393a437ef4aa48af3b9466940 Mon Sep 17 00:00:00 2001 From: Ramtin Amin Date: Tue, 1 Nov 2016 11:35:27 -0600 Subject: [PATCH 280/734] MISOC LM32: Add arch/src/lm32 directory --- arch/misoc/src/Makefile | 4 +- arch/misoc/src/common/misoc_isr.c | 20 ++ arch/misoc/src/common/misoc_uart.c | 141 +++++++++ arch/misoc/src/lm32/Make.defs | 49 +++ arch/misoc/src/lm32/lm32.h | 3 +- arch/misoc/src/lm32/lm32_allocateheap.c | 2 +- arch/misoc/src/lm32/lm32_assert.c | 162 ++++++++++ arch/misoc/src/lm32/lm32_blocktask.c | 180 +++++++++++ arch/misoc/src/lm32/lm32_copystate.c | 87 ++++++ arch/misoc/src/lm32/lm32_createstack.c | 214 +++++++++++++ arch/misoc/src/lm32/lm32_doirq.c | 147 +++++++++ arch/misoc/src/lm32/lm32_dumpstate.c | 228 ++++++++++++++ arch/misoc/src/lm32/lm32_exit.c | 82 +++++ arch/misoc/src/lm32/lm32_idle.c | 96 ++++++ arch/misoc/src/lm32/lm32_initialize.c | 77 +++++ arch/misoc/src/lm32/lm32_initialstate.c | 120 +++++++ arch/misoc/src/lm32/lm32_interruptcontext.c | 62 ++++ arch/misoc/src/lm32/lm32_irq.c | 121 +++++++ arch/misoc/src/lm32/lm32_releasepending.c | 149 +++++++++ arch/misoc/src/lm32/lm32_releasestack.c | 115 +++++++ arch/misoc/src/lm32/lm32_stackframe.c | 136 ++++++++ arch/misoc/src/lm32/lm32_swint.c | 330 ++++++++++++++++++++ arch/misoc/src/lm32/lm32_syscall.S | 103 ++++++ arch/misoc/src/lm32/lm32_unblocktask.c | 164 ++++++++++ arch/misoc/src/lm32/lm32_vectors.S | 251 +++++++++++++++ 25 files changed, 3037 insertions(+), 6 deletions(-) create mode 100644 arch/misoc/src/common/misoc_isr.c create mode 100644 arch/misoc/src/common/misoc_uart.c create mode 100644 arch/misoc/src/lm32/Make.defs create mode 100644 arch/misoc/src/lm32/lm32_assert.c create mode 100644 arch/misoc/src/lm32/lm32_blocktask.c create mode 100644 arch/misoc/src/lm32/lm32_copystate.c create mode 100644 arch/misoc/src/lm32/lm32_createstack.c create mode 100644 arch/misoc/src/lm32/lm32_doirq.c create mode 100644 arch/misoc/src/lm32/lm32_dumpstate.c create mode 100644 arch/misoc/src/lm32/lm32_exit.c create mode 100644 arch/misoc/src/lm32/lm32_idle.c create mode 100644 arch/misoc/src/lm32/lm32_initialize.c create mode 100644 arch/misoc/src/lm32/lm32_initialstate.c create mode 100644 arch/misoc/src/lm32/lm32_interruptcontext.c create mode 100644 arch/misoc/src/lm32/lm32_irq.c create mode 100644 arch/misoc/src/lm32/lm32_releasepending.c create mode 100644 arch/misoc/src/lm32/lm32_releasestack.c create mode 100644 arch/misoc/src/lm32/lm32_stackframe.c create mode 100644 arch/misoc/src/lm32/lm32_swint.c create mode 100644 arch/misoc/src/lm32/lm32_syscall.S create mode 100644 arch/misoc/src/lm32/lm32_unblocktask.c create mode 100644 arch/misoc/src/lm32/lm32_vectors.S diff --git a/arch/misoc/src/Makefile b/arch/misoc/src/Makefile index 6a92f22910..6a0285810b 100644 --- a/arch/misoc/src/Makefile +++ b/arch/misoc/src/Makefile @@ -3,6 +3,7 @@ # # Copyright (C) 2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt +# Ramtin Amin # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions @@ -43,7 +44,6 @@ ifeq ($(CONFIG_WINDOWS_NATIVE),y) NUTTX = "$(TOPDIR)\nuttx$(EXEEXT)" INCLUDES += -I "$(ARCH_SRCDIR)\chip" INCLUDES += -I "$(ARCH_SRCDIR)\common" - INCLUDES += -I "$(ARCH_SRCDIR)\generated" INCLUDES += -I "$(ARCH_SRCDIR)\$(ARCH_SUBDIR)" INCLUDES += -I "$(TOPDIR)\sched" else @@ -52,14 +52,12 @@ ifeq ($(WINTOOL),y) NUTTX = "${shell cygpath -w $(TOPDIR)/nuttx$(EXEEXT)}" INCLUDES += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" INCLUDES += -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" - INCLUDES += -I "${shell cygpath -w $(ARCH_SRCDIR)/generated}" INCLUDES += -I "${shell cygpath -w $(ARCH_SRCDIR)/$(ARCH_SUBDIR)}" INCLUDES += -I "${shell cygpath -w $(TOPDIR)/sched}" else NUTTX = "$(TOPDIR)/nuttx$(EXEEXT)" INCLUDES += -I "$(ARCH_SRCDIR)/chip" INCLUDES += -I "$(ARCH_SRCDIR)/common" - INCLUDES += -I "$(ARCH_SRCDIR)/generated" INCLUDES += -I "$(ARCH_SRCDIR)/$(ARCH_SUBDIR)" INCLUDES += -I "$(TOPDIR)/sched" endif diff --git a/arch/misoc/src/common/misoc_isr.c b/arch/misoc/src/common/misoc_isr.c new file mode 100644 index 0000000000..96c726b17c --- /dev/null +++ b/arch/misoc/src/common/misoc_isr.c @@ -0,0 +1,20 @@ +#include + +void uart_isr(); +void uart_isr() +{ + +} + +void isr(void); +void isr(void) +{ + unsigned int irqs; + + irqs = irq_pending() & irq_getmask(); + + if (irqs & (1 << UART_INTERRUPT)) + { + uart_isr(); + } +} diff --git a/arch/misoc/src/common/misoc_uart.c b/arch/misoc/src/common/misoc_uart.c new file mode 100644 index 0000000000..7a36e78199 --- /dev/null +++ b/arch/misoc/src/common/misoc_uart.c @@ -0,0 +1,141 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include +#include +#include + +#include +#include + +#include "hw/flags.h" +#include "misoc_irqasm.h" +#include "misoc_uart.h" + +#include "lm32.h" + +/* Buffer sizes must be a power of 2 so that modulos can be computed + * with logical AND. + */ + +#define UART_RINGBUFFER_SIZE_RX 128 +#define UART_RINGBUFFER_MASK_RX (UART_RINGBUFFER_SIZE_RX-1) + +static char rx_buf[UART_RINGBUFFER_SIZE_RX]; +static volatile unsigned int rx_produce; +static unsigned int rx_consume; + +#define UART_RINGBUFFER_SIZE_TX 128 +#define UART_RINGBUFFER_MASK_TX (UART_RINGBUFFER_SIZE_TX-1) + +static char tx_buf[UART_RINGBUFFER_SIZE_TX]; +static unsigned int tx_produce; +static volatile unsigned int tx_consume; + +static int uart_interrupt(int irq, void *context); + +static int uart_interrupt(int irq, void *context) +{ + unsigned int stat, rx_produce_next; + + stat = uart_ev_pending_read(); + + if(stat & UART_EV_RX) { + while(!uart_rxempty_read()) { + rx_produce_next = (rx_produce + 1) & UART_RINGBUFFER_MASK_RX; + if(rx_produce_next != rx_consume) { + rx_buf[rx_produce] = uart_rxtx_read(); + rx_produce = rx_produce_next; + } + uart_ev_pending_write(UART_EV_RX); + } + } + + if(stat & UART_EV_TX) { + uart_ev_pending_write(UART_EV_TX); + while((tx_consume != tx_produce) && !uart_txfull_read()) { + uart_rxtx_write(tx_buf[tx_consume]); + tx_consume = (tx_consume + 1) & UART_RINGBUFFER_MASK_TX; + } + } + + return OK; +} + +/* Do not use in interrupt handlers! */ +char uart_read(void) +{ + char c; + + if(irq_getie()) { + while(rx_consume == rx_produce); + } else if (rx_consume == rx_produce) { + return 0; + } + + c = rx_buf[rx_consume]; + rx_consume = (rx_consume + 1) & UART_RINGBUFFER_MASK_RX; + return c; +} + +int uart_read_nonblock(void) +{ + return (rx_consume != rx_produce); +} + +int up_putc(int ch) +{ + unsigned int oldmask; + unsigned int tx_produce_next = (tx_produce + 1) & UART_RINGBUFFER_MASK_TX; + + if(irq_getie()) { + while(tx_produce_next == tx_consume); + } else if(tx_produce_next == tx_consume) { + return ch; + } + + oldmask = irq_getmask(); + irq_setmask(oldmask & ~(1 << UART_INTERRUPT)); + if((tx_consume != tx_produce) || uart_txfull_read()) { + tx_buf[tx_produce] = ch; + tx_produce = tx_produce_next; + } else { + uart_rxtx_write(ch); + } + irq_setmask(oldmask); + return ch; +} + +void uart_init(void) +{ + rx_produce = 0; + rx_consume = 0; + + tx_produce = 0; + tx_consume = 0; + + uart_ev_pending_write(uart_ev_pending_read()); + uart_ev_enable_write(UART_EV_TX | UART_EV_RX); + irq_setmask(irq_getmask() | (1 << UART_INTERRUPT)); + + irq_attach(1 << UART_INTERRUPT, uart_interrupt); +} + +void uart_sync(void) +{ + while(tx_consume != tx_produce); +} + + + diff --git a/arch/misoc/src/lm32/Make.defs b/arch/misoc/src/lm32/Make.defs new file mode 100644 index 0000000000..1c12e0c527 --- /dev/null +++ b/arch/misoc/src/lm32/Make.defs @@ -0,0 +1,49 @@ +############################################################################ +# arch/misoc/src/Makefile +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# Ramtin Amin +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +HEAD_ASRC = lm32_vectors.S + +CMN_ASRCS = +CMN_CSRCS = misoc_uart.c + +CHIP_ASRCS = lm32_start.S lm32_syscall.S + +CHIP_CSRCS = lm32_allocateheap.c lm32_assert.c lm32_blocktask.c +CHIP_CSRCS += lm32_copystate.c lm32_createstack.c lm32_doirq.c lm32_dumpstate.c +CHIP_CSRCS += lm32_dumpstate.c lm32_exit.c lm32_idle.c lm32_initialize.c +CHIP_CSRCS += lm32_initialstate.c lm32_interruptcontext.c lm32_irq.c +CHIP_CSRCS += lm32_releasepending.c lm32_releasestack.c lm32_stackframe.c +CHIP_CSRCS += lm32_swint.c lm32_unblocktask.c diff --git a/arch/misoc/src/lm32/lm32.h b/arch/misoc/src/lm32/lm32.h index 8335c6917d..fe18969c75 100644 --- a/arch/misoc/src/lm32/lm32.h +++ b/arch/misoc/src/lm32/lm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/misoc/src/common/lm32.h + * arch/misoc/src/lm32/lm32.h * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -144,7 +144,6 @@ void lm32_irq_initialize(void); /* System timer *************************************************************/ void lm32_timer_initialize(void); -int lm32_timerisr(int irq, void *context); /* Software interrupts ******************************************************/ diff --git a/arch/misoc/src/lm32/lm32_allocateheap.c b/arch/misoc/src/lm32/lm32_allocateheap.c index 4df88cecaf..882bed891a 100644 --- a/arch/misoc/src/lm32/lm32_allocateheap.c +++ b/arch/misoc/src/lm32/lm32_allocateheap.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/misoc/src/common/lm32_allocateheap.c + * arch/misoc/src/lm32/lm32_allocateheap.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/arch/misoc/src/lm32/lm32_assert.c b/arch/misoc/src/lm32/lm32_assert.c new file mode 100644 index 0000000000..78e7d2b668 --- /dev/null +++ b/arch/misoc/src/lm32/lm32_assert.c @@ -0,0 +1,162 @@ +/**************************************************************************** + * arch/misoc/src/lm32/lm32_assert.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "sched/sched.h" +#include "lm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* USB trace dumping */ + +#ifndef CONFIG_USBDEV_TRACE +# undef CONFIG_ARCH_USBDUMP +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _up_assert + ****************************************************************************/ + +static void _up_assert(int errorcode) noreturn_function; +static void _up_assert(int errorcode) +{ + /* Are we in an interrupt handler or the idle task? */ + + if (g_current_regs || this_task()->pid == 0) + { + (void)up_irq_save(); + for (; ; ) + { +#ifdef CONFIG_ARCH_LEDS + board_autoled_on(LED_PANIC); + up_mdelay(250); + board_autoled_off(LED_PANIC); + up_mdelay(250); +#endif + } + } + else + { + exit(errorcode); + } +} + +/**************************************************************************** + * Name: assert_tracecallback + ****************************************************************************/ + +#ifdef CONFIG_ARCH_USBDUMP +static int usbtrace_syslog(FAR const char *fmt, ...) +{ + va_list ap; + int ret; + + /* Let vsyslog do the real work */ + + va_start(ap, fmt); + ret = vsyslog(LOG_EMERG, fmt, ap); + va_end(ap); + return ret; +} + +static int assert_tracecallback(FAR struct usbtrace_s *trace, FAR void *arg) +{ + usbtrace_trprintf(usbtrace_syslog, trace->event, trace->value); + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_assert + ****************************************************************************/ + +void up_assert(const uint8_t *filename, int lineno) +{ +#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT) + struct tcb_s *rtcb = this_task(); +#endif + + board_autoled_on(LED_ASSERTION); + +#if CONFIG_TASK_NAME_SIZE > 0 + _alert("Assertion failed at file:%s line: %d task: %s\n", + filename, lineno, rtcb->name); +#else + _alert("Assertion failed at file:%s line: %d\n", + filename, lineno); +#endif + + lm32_dumpstate(); + +#ifdef CONFIG_ARCH_USBDUMP + /* Dump USB trace data */ + + (void)usbtrace_enumerate(assert_tracecallback, NULL); +#endif + +#ifdef CONFIG_BOARD_CRASHDUMP + board_crashdump(up_getsp(), this_task(), filename, lineno); +#endif + + _up_assert(EXIT_FAILURE); +} diff --git a/arch/misoc/src/lm32/lm32_blocktask.c b/arch/misoc/src/lm32/lm32_blocktask.c new file mode 100644 index 0000000000..f313da11cc --- /dev/null +++ b/arch/misoc/src/lm32/lm32_blocktask.c @@ -0,0 +1,180 @@ +/**************************************************************************** + * arch/misoc/src/lm32/lm32_blocktask.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "group/group.h" +#include "lm32.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_block_task + * + * Description: + * The currently executing task at the head of + * the ready to run list must be stopped. Save its context + * and move it to the inactive list specified by task_state. + * + * Inputs: + * tcb: Refers to a task in the ready-to-run list (normally + * the task at the head of the list). It most be + * stopped, its context saved and moved into one of the + * waiting task lists. It it was the task at the head + * of the ready-to-run list, then a context to the new + * ready to run task must be performed. + * task_state: Specifies which waiting task list should be + * hold the blocked task TCB. + * + ****************************************************************************/ + +void up_block_task(struct tcb_s *tcb, tstate_t task_state) +{ + struct tcb_s *rtcb = this_task(); + bool switch_needed; + + /* Verify that the context switch can be performed */ + + ASSERT((tcb->task_state >= FIRST_READY_TO_RUN_STATE) && + (tcb->task_state <= LAST_READY_TO_RUN_STATE)); + + /* Remove the tcb task from the ready-to-run list. If we + * are blocking the task at the head of the task list (the + * most likely case), then a context switch to the next + * ready-to-run task is needed. In this case, it should + * also be true that rtcb == tcb. + */ + + switch_needed = sched_removereadytorun(tcb); + + /* Add the task to the specified blocked task list */ + + sched_addblocked(tcb, (tstate_t)task_state); + + /* If there are any pending tasks, then add them to the ready-to-run + * task list now + */ + + if (g_pendingtasks.head) + { + switch_needed |= sched_mergepending(); + } + + /* Now, perform the context switch if one is needed */ + + if (switch_needed) + { + /* Update scheduler parameters */ + + sched_suspend_scheduler(rtcb); + + /* Are we in an interrupt handler? */ + + if (g_current_regs) + { + /* Yes, then we have to do things differently. + * Just copy the g_current_regs into the OLD rtcb. + */ + + up_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + + /* Reset scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + up_restorestate(rtcb->xcp.regs); + } + + /* No, then we will need to perform the user context switch */ + + else + { + /* Get the context of the task at the head of the ready to + * run list. + */ + + struct tcb_s *nexttcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(nexttcb); +#endif + /* Reset scheduler parameters */ + + sched_resume_scheduler(nexttcb); + + /* Then switch contexts */ + + up_switchcontext(rtcb->xcp.regs, nexttcb->xcp.regs); + + /* up_switchcontext forces a context switch to the task at the + * head of the ready-to-run list. It does not 'return' in the + * normal sense. When it does return, it is because the blocked + * task is again ready to run and has execution priority. + */ + } + } +} diff --git a/arch/misoc/src/lm32/lm32_copystate.c b/arch/misoc/src/lm32/lm32_copystate.c new file mode 100644 index 0000000000..b3afa387b8 --- /dev/null +++ b/arch/misoc/src/lm32/lm32_copystate.c @@ -0,0 +1,87 @@ +/**************************************************************************** + * arch/misoc/src/lm32/lm32_copystate.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "lm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm32_copystate + ****************************************************************************/ + +/* A little faster than most memcpy's */ + +void lm32_copystate(uint32_t *dest, uint32_t *src) +{ + int i; + + /* In the LM32 model, the state is copied from the stack to the TCB, + * but only a reference is passed to get the state from the TCB. So the + * following check avoids copying the TCB save area onto itself: + */ + + if (src != dest) + { + for (i = 0; i < XCPTCONTEXT_REGS; i++) + { + *dest++ = *src++; + } + } +} + diff --git a/arch/misoc/src/lm32/lm32_createstack.c b/arch/misoc/src/lm32/lm32_createstack.c new file mode 100644 index 0000000000..31c7f24226 --- /dev/null +++ b/arch/misoc/src/lm32/lm32_createstack.c @@ -0,0 +1,214 @@ +/**************************************************************************** + * arch/misoc/src/lm32/lm32_createstack.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "lm32.h" + +/**************************************************************************** + * Pre-processor Macros + ****************************************************************************/ + +/* LM32 requires at least a 4-byte stack alignment. For floating point use, + * however, the stack must be aligned to 8-byte addresses. + */ + +#ifdef CONFIG_LIBC_FLOATINGPOINT +# define STACK_ALIGNMENT 8 +#else +# define STACK_ALIGNMENT 4 +#endif + +/* Stack alignment macros */ + +#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1) +#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK) +#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_create_stack + * + * Description: + * Allocate a stack for a new thread and setup up stack-related information + * in the TCB. + * + * The following TCB fields must be initialized by this function: + * + * - adj_stack_size: Stack size after adjustment for hardware, processor, + * etc. This value is retained only for debug purposes. + * - stack_alloc_ptr: Pointer to allocated stack + * - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of + * the stack pointer. + * + * Inputs: + * - tcb: The TCB of new task + * - stack_size: The requested stack size. At least this much + * must be allocated. + * - ttype: The thread type. This may be one of following (defined in + * include/nuttx/sched.h): + * + * TCB_FLAG_TTYPE_TASK Normal user task + * TCB_FLAG_TTYPE_PTHREAD User pthread + * TCB_FLAG_TTYPE_KERNEL Kernel thread + * + * This thread type is normally available in the flags field of the TCB, + * however, there are certain contexts where the TCB may not be fully + * initialized when up_create_stack is called. + * + * If CONFIG_BUILD_KERNEL is defined, then this thread type may affect + * how the stack is allocated. For example, kernel thread stacks should + * be allocated from protected kernel memory. Stacks for user tasks and + * threads must come from memory that is accessible to user code. + * + ****************************************************************************/ + +int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) +{ + /* Is there already a stack allocated of a different size? Because of + * alignment issues, stack_size might erroneously appear to be of a + * different size. Fortunately, this is not a critical operation. + */ + + if (tcb->stack_alloc_ptr && tcb->adj_stack_size != stack_size) + { + /* Yes.. Release the old stack */ + + up_release_stack(tcb, ttype); + } + + /* Do we need to allocate a new stack? */ + + if (!tcb->stack_alloc_ptr) + { + /* Allocate the stack. If DEBUG is enabled (but not stack debug), + * then create a zeroed stack to make stack dumps easier to trace. + */ + +#if defined(CONFIG_BUILD_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP) + /* Use the kernel allocator if this is a kernel thread */ + + if (ttype == TCB_FLAG_TTYPE_KERNEL) + { + tcb->stack_alloc_ptr = (uint32_t *)kmm_malloc(stack_size); + } + else +#endif + { + /* Use the user-space allocator if this is a task or pthread */ + + tcb->stack_alloc_ptr = (uint32_t *)kumm_malloc(stack_size); + } + +#ifdef CONFIG_DEBUG_FEATURES + /* Was the allocation successful? */ + + if (!tcb->stack_alloc_ptr) + { + serr("ERROR: Failed to allocate stack, size %d\n", stack_size); + } +#endif + } + + /* Did we successfully allocate a stack? */ + + if (tcb->stack_alloc_ptr) + { + size_t top_of_stack; + size_t size_of_stack; + + /* Yes.. If stack debug is enabled, then fill the stack with a + * recognizable value that we can use later to test for high + * water marks. + */ + +#ifdef CONFIG_STACK_COLORATION + memset(tcb->stack_alloc_ptr, 0xaa, stack_size); +#endif + + /* LM32 uses a push-down stack: the stack grows toward lower + * addresses in memory. The stack pointer register points to the + * lowest, valid working address (the "top" of the stack). Items on + * the stack are referenced as positive word offsets from sp. + */ + + top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4; + + /* The LM32 stack must be aligned at word (4 byte) boundaries; for + * floating point use, the stack must be aligned to 8-byte addresses. + * If necessary top_of_stack must be rounded down to the next + * boundary to meet these alignment requirements. + */ + + top_of_stack = STACK_ALIGN_DOWN(top_of_stack); + size_of_stack = top_of_stack - (uint32_t)tcb->stack_alloc_ptr + 4; + + /* Save the adjusted stack values in the struct tcb_s */ + + tcb->adj_stack_ptr = (FAR uint32_t *)top_of_stack; + tcb->adj_stack_size = size_of_stack; + + board_autoled_on(LED_STACKCREATED); + return OK; + } + + return ERROR; +} diff --git a/arch/misoc/src/lm32/lm32_doirq.c b/arch/misoc/src/lm32/lm32_doirq.c new file mode 100644 index 0000000000..50b2e745fc --- /dev/null +++ b/arch/misoc/src/lm32/lm32_doirq.c @@ -0,0 +1,147 @@ +/**************************************************************************** + * arch/misoc/src/lm32/lm32_doirq.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include "group/group.h" +#include "lm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +uint32_t *up_doirq(int irq, uint32_t *regs) +{ + board_autoled_on(LED_INIRQ); +#ifdef CONFIG_SUPPRESS_INTERRUPTS + PANIC(); +#else + /* Current regs non-zero indicates that we are processing an interrupt; + * g_current_regs is also used to manage interrupt level context switches. + * + * Nested interrupts are not supported + */ + + DEBUGASSERT(g_current_regs == NULL); + g_current_regs = regs; + + /* Disable further occurrences of this interrupt (until the interrupt sources + * have been clear by the driver). + */ + + up_disable_irq(irq); + + /* Deliver the IRQ */ + + irq_dispatch(irq, regs); + +#if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV) + /* Check for a context switch. If a context switch occurred, then + * g_current_regs will have a different value than it did on entry. If an + * interrupt level context switch has occurred, then restore the floating + * point state and the establish the correct address environment before + * returning from the interrupt. + */ + + if (regs != g_current_regs) + { +#ifdef CONFIG_ARCH_FPU + /* Restore floating point registers */ + + up_restorefpu((uint32_t *)g_current_regs); +#endif + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(NULL); +#endif + } +#endif + + /* If a context switch occurred while processing the interrupt then + * g_current_regs may have change value. If we return any value different + * from the input regs, then the lower level will know that a context + * switch occurred during interrupt processing. + */ + + regs = (uint32_t *)g_current_regs; + + /* Set g_current_regs to NULL to indicate that we are no longer in an + * interrupt handler. + */ + + g_current_regs = NULL; + + /* Unmask the last interrupt (global interrupts are still disabled) */ + + up_enable_irq(irq); +#endif + board_autoled_off(LED_INIRQ); + return regs; +} diff --git a/arch/misoc/src/lm32/lm32_dumpstate.c b/arch/misoc/src/lm32/lm32_dumpstate.c new file mode 100644 index 0000000000..e847bec40c --- /dev/null +++ b/arch/misoc/src/lm32/lm32_dumpstate.c @@ -0,0 +1,228 @@ +/**************************************************************************** + * arch/misoc/src/lm32/lm32_dumpstate.c + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "sched/sched.h" +#include "lm32.h" + +#ifdef CONFIG_ARCH_STACKDUMP + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_getsp + ****************************************************************************/ + +static inline uint32_t up_getsp(void) +{ + register uint32_t sp; + + __asm__ __volatile__("addi %0, sp, 0" : "=r" (sp)); + + return sp; +} + +/**************************************************************************** + * Name: up_stackdump + ****************************************************************************/ + +static void up_stackdump(uint32_t sp, uint32_t stack_base) +{ +# if 0 + uint32_t stack ; + + for (stack = sp & ~0x1f; stack < stack_base; stack += 32) + { + uint32_t *ptr = (uint32_t *)stack; + _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", + stack, ptr[0], ptr[1], ptr[2], ptr[3], + ptr[4], ptr[5], ptr[6], ptr[7]); + } +#endif +} + +/**************************************************************************** + * Name: up_registerdump + ****************************************************************************/ + +static inline void up_registerdump(void) +{ +#if 0 + /* Are user registers available from interrupt processing? */ + + if (g_current_regs) + { + _alert("EPC:%08x \n", + g_current_regs[REG_EPC]); + _alert("A0:%08x A1:%08x A2:%08x A3:%08x A4:%08x A5:%08x A6:%08x A7:%08x\n", + g_current_regs[REG_A0], g_current_regs[REG_A1], g_current_regs[REG_A2], + g_current_regs[REG_A3], g_current_regs[REG_A4], g_current_regs[REG_A5], + g_current_regs[REG_A6], g_current_regs[REG_A7]); + _alert("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x\n", + g_current_regs[REG_T0], g_current_regs[REG_T1], g_current_regs[REG_T2], + g_current_regs[REG_T3], g_current_regs[REG_T4], g_current_regs[REG_T5], + g_current_regs[REG_T6]); + _alert("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n", + g_current_regs[REG_S0], g_current_regs[REG_S1], g_current_regs[REG_S2], + g_current_regs[REG_S3], g_current_regs[REG_S4], g_current_regs[REG_S5], + g_current_regs[REG_S6], g_current_regs[REG_S7]); + _alert("S8:%08x S9:%08x S10:%08x S11:%08x\n", + g_current_regs[REG_S8], g_current_regs[REG_S9], g_current_regs[REG_S10], + g_current_regs[REG_S11]); +#ifdef RISCV_SAVE_GP + _alert("GP:%08x SP:%08x FP:%08x TP:%08x RA:%08x\n", + g_current_regs[REG_GP], g_current_regs[REG_SP], g_current_regs[REG_FP], + g_current_regs[REG_TP], g_current_regs[REG_RA]); +#else + _alert("SP:%08x FP:%08x TP:%08x RA:%08x\n", + g_current_regs[REG_SP], g_current_regs[REG_FP], g_current_regs[REG_TP], + g_current_regs[REG_RA]); +#endif + } +#endif +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm32_dumpstate + ****************************************************************************/ + +void lm32_dumpstate(void) +{ + struct tcb_s *rtcb = this_task(); + uint32_t sp = up_getsp(); + uint32_t ustackbase; + uint32_t ustacksize; +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + uint32_t istackbase; + uint32_t istacksize; +#endif + + /* Get the limits on the user stack memory */ + + if (rtcb->pid == 0) + { + ustackbase = g_idle_topstack - 4; + ustacksize = CONFIG_IDLETHREAD_STACKSIZE; + } + else + { + ustackbase = (uint32_t)rtcb->adj_stack_ptr; + ustacksize = (uint32_t)rtcb->adj_stack_size; + } + + /* Get the limits on the interrupt stack memory */ + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + istackbase = (uint32_t)&g_intstackbase; + istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4; + + /* Show interrupt stack info */ + + _alert("sp: %08x\n", sp); + _alert("IRQ stack:\n"); + _alert(" base: %08x\n", istackbase); + _alert(" size: %08x\n", istacksize); + + /* Does the current stack pointer lie within the interrupt + * stack? + */ + + if (sp <= istackbase && sp > istackbase - istacksize) + { + /* Yes.. dump the interrupt stack */ + + up_stackdump(sp, istackbase); + + /* Extract the user stack pointer which should lie + * at the base of the interrupt stack. + */ + + sp = g_intstackbase; + _alert("sp: %08x\n", sp); + } + + /* Show user stack info */ + + _alert("User stack:\n"); + _alert(" base: %08x\n", ustackbase); + _alert(" size: %08x\n", ustacksize); +#else + _alert("sp: %08x\n", sp); + _alert("stack base: %08x\n", ustackbase); + _alert("stack size: %08x\n", ustacksize); +#endif + + /* Dump the user stack if the stack pointer lies within the allocated user + * stack memory. + */ + + if (sp > ustackbase || sp <= ustackbase - ustacksize) + { +#if !defined(CONFIG_ARCH_INTERRUPTSTACK) || CONFIG_ARCH_INTERRUPTSTACK < 4 + _alert("ERROR: Stack pointer is not within allocated stack\n"); +#endif + } + else + { + up_stackdump(sp, ustackbase); + } + + /* Then dump the registers (if available) */ + + up_registerdump(); +} + +#endif /* CONFIG_ARCH_STACKDUMP */ diff --git a/arch/misoc/src/lm32/lm32_exit.c b/arch/misoc/src/lm32/lm32_exit.c new file mode 100644 index 0000000000..688f085426 --- /dev/null +++ b/arch/misoc/src/lm32/lm32_exit.c @@ -0,0 +1,82 @@ +/**************************************************************************** + * arch/misoc/src/lm32/lm32_exit.c + * + * Copyright (C) 2010, 2013-2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#ifdef CONFIG_DUMP_ON_EXIT +# include +#endif + +#include "task/task.h" +#include "sched/sched.h" +#include "group/group.h" +#include "lm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _exit + * + * Description: + * This function causes the currently executing task to cease + * to exist. This is a special case of task_delete() where the task to + * be deleted is the currently executing task. It is more complex because + * a context switch must be perform to the next ready to run task. + * + ****************************************************************************/ + +void _exit(int status) +{ +#warning Missing logic +} diff --git a/arch/misoc/src/lm32/lm32_idle.c b/arch/misoc/src/lm32/lm32_idle.c new file mode 100644 index 0000000000..5b85bcc0c0 --- /dev/null +++ b/arch/misoc/src/lm32/lm32_idle.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * arch/misoc/src/lm32/lm32_idle.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "lm32.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + sched_process_timer(); +#else + + /* This would be an appropriate place to put some MCU-specific logic to + * sleep in a reduced power mode until an interrupt occurs to save power + */ + + /* This is a kludge that I still don't understand. The call to kmm_trysemaphore() + * in the os_start.c IDLE loop seems necessary for the good health of the IDLE + * loop. When the work queue is enabled, this logic is removed from the IDLE + * loop and it appears that we are somehow left idling with interrupts non- + * functional. The following should be no-op, it just disables then re-enables + * interrupts. But it fixes the problem and will stay here until I understand + * the problem/fix better. + * + * And no, the contents of the CP0 status register are not incorrect. But for + * some reason the status register needs to be re-written again on this thread + * for it to take effect. This might be a PIC32-only issue? + */ + +#ifdef CONFIG_SCHED_WORKQUEUE + irqstate_t flags = enter_critical_section(); + leave_critical_section(flags); +#endif +#endif +} diff --git a/arch/misoc/src/lm32/lm32_initialize.c b/arch/misoc/src/lm32/lm32_initialize.c new file mode 100644 index 0000000000..4efa2ecbf0 --- /dev/null +++ b/arch/misoc/src/lm32/lm32_initialize.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * arch/misoc/src/lm32/lm32_initialize.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "lm32.h" + +/**************************************************************************** + * Public Functionis + ****************************************************************************/ + +void up_initialize(void) +{ + /* Initialize the System Timer */ + + lm32_irq_initialize(); + + /* Initialize the serial driver */ + +#warning REVISIT: Here you should all lm32_serial_initialize(). That initializes the entire serial driver, a part of the operation is the uart initialization. + + uart_init(); +} diff --git a/arch/misoc/src/lm32/lm32_initialstate.c b/arch/misoc/src/lm32/lm32_initialstate.c new file mode 100644 index 0000000000..e42107e145 --- /dev/null +++ b/arch/misoc/src/lm32/lm32_initialstate.c @@ -0,0 +1,120 @@ +/**************************************************************************** + * arch/misoc/src/lm32/up_initialstate.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "lm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_initial_state + * + * Description: + * A new thread is being started and a new TCB + * has been created. This function is called to initialize + * the processor specific portions of the new TCB. + * + * This function must setup the intial architecture registers + * and/or stack so that execution will begin at tcb->start + * on the next context switch. + * + ****************************************************************************/ + +void up_initial_state(struct tcb_s *tcb) +{ + struct xcptcontext *xcp = &tcb->xcp; + + /* Initialize the initial exception register context structure */ + + memset(xcp, 0, sizeof(struct xcptcontext)); + + /* Save the initial stack pointer. Hmmm.. the stack is set to the very + * beginning of the stack region. Some functions may want to store data on + * the caller's stack and it might be good to reserve some space. However, + * only the start function would do that and we have control over that one + */ + + xcp->regs[REG_SP] = (uint32_t)tcb->adj_stack_ptr; + + /* Save the task entry point */ + + xcp->regs[REG_EPC] = (uint32_t)tcb->start; + + /* If this task is running PIC, then set the PIC base register to the + * address of the allocated D-Space region. + */ + +#ifdef CONFIG_PIC +# warning "Missing logic" +#endif + + /* Set privileged- or unprivileged-mode, depending on how NuttX is + * configured and what kind of thread is being started. + * + * If the kernel build is not selected, then all threads run in + * privileged thread mode. + */ + +#ifdef CONFIG_BUILD_KERNEL +# warning "Missing logic" +#endif +} diff --git a/arch/misoc/src/lm32/lm32_interruptcontext.c b/arch/misoc/src/lm32/lm32_interruptcontext.c new file mode 100644 index 0000000000..8edd553853 --- /dev/null +++ b/arch/misoc/src/lm32/lm32_interruptcontext.c @@ -0,0 +1,62 @@ +/**************************************************************************** + * arch/misoc/src/lm32/up_interruptcontext.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "lm32.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_interrupt_context + * + * Description: Return true is we are currently executing in + * the interrupt handler context. + ****************************************************************************/ + +bool up_interrupt_context(void) +{ + return g_current_regs != NULL; +} diff --git a/arch/misoc/src/lm32/lm32_irq.c b/arch/misoc/src/lm32/lm32_irq.c new file mode 100644 index 0000000000..b99bb443b4 --- /dev/null +++ b/arch/misoc/src/lm32/lm32_irq.c @@ -0,0 +1,121 @@ +/**************************************************************************** + * arch/misoc/src/lm32/_irq.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include +#include +#include + +#include "misoc_irqasm.h" +#include "lm32.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uint32_t *g_current_regs; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm32_irq_initialize + ****************************************************************************/ + +void lm32_irq_initialize(void) +{ + /* currents_regs is non-NULL only while processing an interrupt */ + + g_current_regs = NULL; + + /* Enable interrupt */ + + irq_setie(1); +} + +irqstate_t up_irq_save(void) +{ + irqstate_t flags; + irq_setie(0); + +#warning Return value MUST be the previous IE value. Returning 1 will not work. + return 1; +} + +void up_irq_restore(irqstate_t flags) +{ + irq_setie(1); +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + irqstate_t flags; + flags = irq_getmask(); + flags &= ~(1 < + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "group/group.h" +#include "lm32.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_release_pending + * + * Description: + * Release and ready-to-run tasks that have + * collected in the pending task list. This can call a + * context switch if a new task is placed at the head of + * the ready to run list. + * + ****************************************************************************/ + +void up_release_pending(void) +{ + struct tcb_s *rtcb = this_task(); + + sinfo("From TCB=%p\n", rtcb); + + /* Merge the g_pendingtasks list into the ready-to-run task list */ + + /* sched_lock(); */ + if (sched_mergepending()) + { + /* The currently active task has changed! We will need to switch + * contexts. + * + * Update scheduler parameters. + */ + + sched_suspend_scheduler(rtcb); + + /* Are we operating in interrupt context? */ + + if (g_current_regs) + { + /* Yes, then we have to do things differently. + * Just copy the g_current_regs into the OLD rtcb. + */ + + up_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + + /* Update scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + up_restorestate(rtcb->xcp.regs); + } + + /* No, then we will need to perform the user context switch */ + + else + { + /* Switch context to the context of the task at the head of the + * ready to run list. + */ + + struct tcb_s *nexttcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(nexttcb); +#endif + /* Update scheduler parameters */ + + sched_resume_scheduler(nexttcb); + + /* Then switch contexts */ + + up_switchcontext(rtcb->xcp.regs, nexttcb->xcp.regs); + + /* up_switchcontext forces a context switch to the task at the + * head of the ready-to-run list. It does not 'return' in the + * normal sense. When it does return, it is because the blocked + * task is again ready to run and has execution priority. + */ + } + } +} diff --git a/arch/misoc/src/lm32/lm32_releasestack.c b/arch/misoc/src/lm32/lm32_releasestack.c new file mode 100644 index 0000000000..fa88500bf9 --- /dev/null +++ b/arch/misoc/src/lm32/lm32_releasestack.c @@ -0,0 +1,115 @@ +/**************************************************************************** + * arch/misoc/src/lm32/up_releasestack.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "lm32.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_release_stack + * + * Description: + * A task has been stopped. Free all stack related resources retained in + * the defunct TCB. + * + * Input Parmeters + * - dtcb: The TCB containing information about the stack to be released + * - ttype: The thread type. This may be one of following (defined in + * include/nuttx/sched.h): + * + * TCB_FLAG_TTYPE_TASK Normal user task + * TCB_FLAG_TTYPE_PTHREAD User pthread + * TCB_FLAG_TTYPE_KERNEL Kernel thread + * + * This thread type is normally available in the flags field of the TCB, + * however, there are certain error recovery contexts where the TCB may + * not be fully initialized when up_release_stack is called. + * + * If CONFIG_BUILD_KERNEL is defined, then this thread type may affect + * how the stack is freed. For example, kernel thread stacks may have + * been allocated from protected kernel memory. Stacks for user tasks + * and threads must have come from memory that is accessible to user + * code. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_release_stack(FAR struct tcb_s *dtcb, uint8_t ttype) +{ + /* Is there a stack allocated? */ + + if (dtcb->stack_alloc_ptr) + { +#if defined(CONFIG_BUILD_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP) + /* Use the kernel allocator if this is a kernel thread */ + + if (ttype == TCB_FLAG_TTYPE_KERNEL) + { + sched_kfree(dtcb->stack_alloc_ptr); + } + else +#endif + { + /* Use the user-space allocator if this is a task or pthread */ + + sched_ufree(dtcb->stack_alloc_ptr); + } + + /* Mark the stack freed */ + + dtcb->stack_alloc_ptr = NULL; + } + + /* The size of the allocated stack is now zero */ + + dtcb->adj_stack_size = 0; +} diff --git a/arch/misoc/src/lm32/lm32_stackframe.c b/arch/misoc/src/lm32/lm32_stackframe.c new file mode 100644 index 0000000000..981c655f81 --- /dev/null +++ b/arch/misoc/src/lm32/lm32_stackframe.c @@ -0,0 +1,136 @@ +/**************************************************************************** + * arch/misoc/src/lm32/lm32_stackframe.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "lm32.h" + +/**************************************************************************** + * Pre-processor Macros + ****************************************************************************/ + +/* LM32 requires at least a 4-byte stack alignment. For floating point use, + * however, the stack must be aligned to 8-byte addresses. + */ + +#ifdef CONFIG_LIBC_FLOATINGPOINT +# define STACK_ALIGNMENT 8 +#else +# define STACK_ALIGNMENT 4 +#endif + +/* Stack alignment macros */ + +#define STACK_ALIGN_MASK (STACK_ALIGNMENT-1) +#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK) +#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_stack_frame + * + * Description: + * Allocate a stack frame in the TCB's stack to hold thread-specific data. + * This function may be called anytime after up_create_stack() or + * up_use_stack() have been called but before the task has been started. + * + * Thread data may be kept in the stack (instead of in the TCB) if it is + * accessed by the user code directly. This includes such things as + * argv[]. The stack memory is guaranteed to be in the same protection + * domain as the thread. + * + * The following TCB fields will be re-initialized: + * + * - adj_stack_size: Stack size after removal of the stack frame from + * the stack + * - adj_stack_ptr: Adjusted initial stack pointer after the frame has + * been removed from the stack. This will still be the initial value + * of the stack pointer when the task is started. + * + * Inputs: + * - tcb: The TCB of new task + * - frame_size: The size of the stack frame to allocate. + * + * Returned Value: + * - A pointer to bottom of the allocated stack frame. NULL will be + * returned on any failures. The alignment of the returned value is + * the same as the alignment of the stack itself. + * + ****************************************************************************/ + +FAR void *up_stack_frame(FAR struct tcb_s *tcb, size_t frame_size) +{ + uintptr_t topaddr; + + /* Align the frame_size */ + + frame_size = STACK_ALIGN_UP(frame_size); + + /* Is there already a stack allocated? Is it big enough? */ + + if (!tcb->stack_alloc_ptr || tcb->adj_stack_size <= frame_size) + { + return NULL; + } + + /* Save the adjusted stack values in the struct tcb_s */ + + topaddr = (uintptr_t)tcb->adj_stack_ptr - frame_size; + tcb->adj_stack_ptr = (FAR void *)topaddr; + tcb->adj_stack_size -= frame_size; + + /* Reset the initial stack pointer */ + + tcb->xcp.regs[REG_SP] = (uint32_t)tcb->adj_stack_ptr; + + /* And return the pointer to the allocated region */ + + return (FAR void *)(topaddr + sizeof(uint32_t)); +} diff --git a/arch/misoc/src/lm32/lm32_swint.c b/arch/misoc/src/lm32/lm32_swint.c new file mode 100644 index 0000000000..c8148812cc --- /dev/null +++ b/arch/misoc/src/lm32/lm32_swint.c @@ -0,0 +1,330 @@ +/**************************************************************************** + * arch/misoc/src/lm32/lm32_swint.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "lm32.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_registerdump + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_SYSCALL_INFO +static void up_registerdump(const uint32_t *regs) +{ +#if 0 + svcinfo("EPC:%08x\n", + regs[REG_EPC]); + svcinfo("A0:%08x A1:%08x A2:%08x A3:%08x A4:%08x A5:%08x A6:%08x A7:%08x\n", + regs[REG_A0], regs[REG_A1], regs[REG_A2], regs[REG_A3], + regs[REG_A4], regs[REG_A5], regs[REG_A6], regs[REG_A7]); + svcinfo("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x\n", + regs[REG_T0], regs[REG_T1], regs[REG_T2], regs[REG_T3], + regs[REG_T4], regs[REG_T5], regs[REG_T6]); + svcinfo("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n", + regs[REG_S0], regs[REG_S1], regs[REG_S2], regs[REG_S3], + regs[REG_S4], regs[REG_S5], regs[REG_S6], regs[REG_S7]); + svcinfo("S8:%08x S9:%08x S10:%08x S11:%08x\n", + regs[REG_S8], regs[REG_S9], regs[REG_S10], regs[REG_S11]); +#ifdef LM3232_SAVE_GP + svcinfo("GP:%08x SP:%08x FP:%08x TP:%08x RA:%08x\n", + regs[REG_GP], regs[REG_SP], regs[REG_FP], regs[REG_TP], regs[REG_RA]); +#else + svcinfo("SP:%08x FP:%08x TP:%08x RA:%08x\n", + regs[REG_SP], regs[REG_FP], regs[REG_TP], regs[REG_RA]); +#endif +#endif +} +#else +# define up_registerdump(regs) +#endif + +/**************************************************************************** + * Name: dispatch_syscall + * + * Description: + * Call the stub function corresponding to the system call. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_KERNEL +static void dispatch_syscall(void) naked_function; +static void dispatch_syscall(void) +{ +# error "Missing logic" + +/* Refer to arch/arm/src/armv7-m/up_svcall.h for how this is done for ARM */ +/* __asm__ __volatile__ */ +/* ( */ +/* Save registers */ +/* Get the base of the stub lookup table */ +/* Get the offset of the stub for this syscall */ +/* Load the entry of the stub for this syscall */ +/* Call the stub */ +/* Restore regsisters */ +/* Return from the syscall */ +/* ); */ +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm32_swint + * + * Description: + * This is software interrupt exception handler that performs context + * switching and manages system calls + * + ****************************************************************************/ + +uint32_t lm32_swint(int irq, FAR void *context) +{ + uint32_t *regs = (uint32_t *)context; + + DEBUGASSERT(g_current_regs == NULL); + g_current_regs = regs; + + /* Software interrupt 0 is invoked with REG_A0 (REG_X10) = system call + * command and REG_A1-6 = variable number of + * arguments depending on the system call. + */ + +#ifdef CONFIG_DEBUG_SYSCALL_INFO + svcinfo("Entry: regs: %p cmd: %d\n", regs, regs[REG_A0]); + up_registerdump(regs); +#endif + + /* Handle the SWInt according to the command in $a0 */ + + switch (regs[REG_A0]) + { + /* A0=SYS_restore_context: This a restore context command: + * + * void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function; + * + * At this point, the following values are saved in context: + * + * A0 = SYS_restore_context + * A1 = restoreregs + * + * In this case, we simply need to set g_current_regs to restore register + * area referenced in the saved R1. context == g_current_regs is the normal + * exception return. By setting g_current_regs = context[R1], we force + * the return to the saved context referenced in $a1. + */ + + case SYS_restore_context: + { + DEBUGASSERT(regs[REG_A1] != 0); + g_current_regs = (uint32_t *)regs[REG_A1]; + } + break; + + /* A0=SYS_switch_context: This a switch context command: + * + * void up_switchcontext(uint32_t *saveregs, uint32_t *restoreregs); + * + * At this point, the following values are saved in context: + * + * A0 = SYS_switch_context + * A1 = saveregs + * A2 = restoreregs + * + * In this case, we save the context registers to the save register + * area reference by the saved contents of R5 and then set + * g_current_regs to to the save register area referenced by the saved + * contents of R6. + */ + + case SYS_switch_context: + { + DEBUGASSERT(regs[REG_A1] != 0 && regs[REG_A2] != 0); + lm32_copystate((uint32_t *)regs[REG_A1], regs); + g_current_regs = (uint32_t *)regs[REG_A2]; + } + break; + + /* A0=SYS_syscall_return: This a switch context command: + * + * void up_sycall_return(void); + * + * At this point, the following values are saved in context: + * + * A0 = SYS_syscall_return + * + * We need to restore the saved return address and return in + * unprivileged thread mode. + */ + +#ifdef CONFIG_BUILD_KERNEL + case SYS_syscall_return: + { + struct tcb_s *rtcb = sched_self(); + int index = (int)rtcb->xcp.nsyscalls - 1; + + /* Make sure that there is a saved syscall return address. */ + + DEBUGASSERT(index >= 0); + + /* Setup to return to the saved syscall return address in + * the original mode. + */ + + g_current_regs[REG_EPC] = rtcb->xcp.syscall[index].sysreturn; +#error "Missing logic -- need to restore the original mode" + rtcb->xcp.nsyscalls = index; + } + break; +#endif + + /* This is not an architecture-specify system call. If NuttX is built + * as a standalone kernel with a system call interface, then all of the + * additional system calls must be handled as in the default case. + */ + + default: + { +#ifdef CONFIG_BUILD_KERNEL + FAR struct tcb_s *rtcb = sched_self(); + int index = rtcb->xcp.nsyscalls; + + /* Verify that the SYS call number is within range */ + + DEBUGASSERT(g_current_regs[REG_A0] < SYS_maxsyscall); + + /* Make sure that we got here that there is a no saved syscall + * return address. We cannot yet handle nested system calls. + */ + + DEBUGASSERT(index < CONFIG_SYS_NNEST); + + /* Setup to return to dispatch_syscall in privileged mode. */ + + rtcb->xcpsyscall[index].sysreturn = regs[REG_EPC]; +#error "Missing logic -- Need to save mode" + rtcb->xcp.nsyscalls = index + 1; + + regs[REG_EPC] = (uint32_t)dispatch_syscall; +#error "Missing logic -- Need to set privileged mode" + + /* Offset R0 to account for the reserved values */ + + g_current_regs[REG_A0] -= CONFIG_SYS_RESERVED; +#else + svcerr("ERROR: Bad SYS call: %d\n", regs[REG_A0]); +#endif + } + break; + } + + /* Report what happened. That might difficult in the case of a context switch */ + +#ifdef CONFIG_DEBUG_SYSCALL_INFO + if (regs != g_current_regs) + { + svcinfo("SWInt Return: Context switch!\n"); + up_registerdump((const uint32_t *)g_current_regs); + } + else + { + svcinfo("SWInt Return: %d\n", regs[REG_A0]); + } +#endif + + +#if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV) + /* Check for a context switch. If a context switch occurred, then + * g_current_regs will have a different value than it did on entry. If an + * interrupt level context switch has occurred, then restore the floating + * point state and the establish the correct address environment before + * returning from the interrupt. + */ + + if (regs != g_current_regs) + { +#ifdef CONFIG_ARCH_FPU + /* Restore floating point registers */ + + up_restorefpu((uint32_t *)g_current_regs); +#endif + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(NULL); +#endif + } +#endif + + /* If a context switch occurred while processing the interrupt then + * g_current_regs may have change value. If we return any value different + * from the input regs, then the lower level will know that a context + * switch occurred during interrupt processing. + */ + + regs = (uint32_t *)g_current_regs; + + /* Set g_current_regs to NULL to indicate that we are no longer in an + * interrupt handler. + */ + + g_current_regs = NULL; + return regs; +} diff --git a/arch/misoc/src/lm32/lm32_syscall.S b/arch/misoc/src/lm32/lm32_syscall.S new file mode 100644 index 0000000000..61b0b6ca7c --- /dev/null +++ b/arch/misoc/src/lm32/lm32_syscall.S @@ -0,0 +1,103 @@ +/**************************************************************************** + * arch/misoc/src/lm32/lm32_syscall.S + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Ramtin Amin + * + * Derives from RISC-V version: + * + * Copyright (C) 2016 Ken Pettit. All rights reserved. + * Author: Ken Pettit + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Symbols + ****************************************************************************/ + + .file "up_syscall.S" + .global sys_call0 + .global sys_call1 + .global sys_call2 + .global sys_call3 + .global sys_call4 + .global sys_call5 + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_syscall0, up_syscall1, up_syscall2, up_syscall3 + * + * Description: + * up_syscall0 - System call SYS_ argument and no additional parameters. + * up_syscall1 - System call SYS_ argument and one additional parameter. + * up_syscall2 - System call SYS_ argument and two additional parameters. + * up_syscall3 - System call SYS_ argument and three additional parameters. + * up_syscall4 - System call SYS_ argument and four additional parameters. + * up_syscall5 - System call SYS_ argument and five additional parameters. + * + * Assumption: + * All interrupts are disabled except for the software interrupts. + * + ****************************************************************************/ + + .text + +sys_call0: /* a0 holds the syscall number */ +sys_call1: /* a0 holds the syscall number, argument in a1 */ +sys_call2: /* a0 holds the syscall number, arguments in a1 and a2 */ +sys_call3: /* a0 holds the syscall number, arguments in a1, a2, and a3 */ +sys_call4: /* a0 holds the syscall number, arguments in a1, a2, a3 and a4 */ +sys_call5: /* a0 holds the syscall number, arguments in a1, a2, a3, a4 and a5 */ + + /* Issue the ECALL opcode to perform a SW interrupt to the OS */ + + scall + + /* The actual interrupt may not a occur for a few more cycles. Let's + * put a few nop's here in hope that the SW interrupt occurs during + * the sequence of nops. + */ + + nop + nop + + /* Then return with the result of the software interrupt in v0 */ + + ret + nop diff --git a/arch/misoc/src/lm32/lm32_unblocktask.c b/arch/misoc/src/lm32/lm32_unblocktask.c new file mode 100644 index 0000000000..74b1d92472 --- /dev/null +++ b/arch/misoc/src/lm32/lm32_unblocktask.c @@ -0,0 +1,164 @@ +/**************************************************************************** + * arch/misoc/src/lm32/lm32_unblocktask.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "group/group.h" +#include "clock/clock.h" +#include "lm32.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_unblock_task + * + * Description: + * A task is currently in an inactive task list + * but has been prepped to execute. Move the TCB to the + * ready-to-run list, restore its context, and start execution. + * + * Inputs: + * tcb: Refers to the tcb to be unblocked. This tcb is + * in one of the waiting tasks lists. It must be moved to + * the ready-to-run list and, if it is the highest priority + * ready to run task, executed. + * + ****************************************************************************/ + +void up_unblock_task(struct tcb_s *tcb) +{ + struct tcb_s *rtcb = this_task(); + + /* Verify that the context switch can be performed */ + + ASSERT((tcb->task_state >= FIRST_BLOCKED_STATE) && + (tcb->task_state <= LAST_BLOCKED_STATE)); + + /* Remove the task from the blocked task list */ + + sched_removeblocked(tcb); + + /* Add the task in the correct location in the prioritized + * ready-to-run task list + */ + + if (sched_addreadytorun(tcb)) + { + /* The currently active task has changed! We need to do + * a context switch to the new task. + */ + + /* Update scheduler parameters */ + + sched_suspend_scheduler(rtcb); + + /* Are we in an interrupt handler? */ + + if (g_current_regs) + { + /* Yes, then we have to do things differently. + * Just copy the g_current_regs into the OLD rtcb. + */ + + up_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + + /* Update scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + up_restorestate(rtcb->xcp.regs); + } + + /* No, then we will need to perform the user context switch */ + + else + { + /* Restore the exception context of the new task that is ready to + * run (probably tcb). This is the new rtcb at the head of the + * ready-to-run task list. + */ + + struct tcb_s *nexttcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(nexttcb); +#endif + /* Update scheduler parameters */ + + sched_resume_scheduler(nexttcb); + + /* Then switch contexts */ + + up_switchcontext(rtcb->xcp.regs, nexttcb->xcp.regs); + + /* up_switchcontext forces a context switch to the task at the + * head of the ready-to-run list. It does not 'return' in the + * normal sense. When it does return, it is because the blocked + * task is again ready to run and has execution priority. + */ + } + } +} diff --git a/arch/misoc/src/lm32/lm32_vectors.S b/arch/misoc/src/lm32/lm32_vectors.S new file mode 100644 index 0000000000..a5ca7a550d --- /dev/null +++ b/arch/misoc/src/lm32/lm32_vectors.S @@ -0,0 +1,251 @@ +/**************************************************************************** + * arch/misoc/src/lm32/lm32_allocateheap.c + * LM32 C startup code. + * + * Adapted for NuttX: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Ramtin Amin + * + * Derives from LatticeMico32 C startup code. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Exception handlers - Must be 32 bytes long. + ****************************************************************************/ + + .section .text, "ax", @progbits + .global __start + +__start: +_reset_handler: + xor r0, r0, r0 + wcsr IE, r0 + mvhi r1, hi(_reset_handler) + ori r1, r1, lo(_reset_handler) + wcsr EBA, r1 + bi _do_reset + nop + nop + +_breakpoint_handler: + bi _breakpoint_handler + nop + nop + nop + nop + nop + nop + nop + +_instruction_bus_error_handler: + bi _instruction_bus_error_handler + nop + nop + nop + nop + nop + nop + nop + +_watchpoint_hander: + bi _watchpoint_hander + nop + nop + nop + nop + nop + nop + nop + +_data_bus_error_handler: + bi _data_bus_error_handler + nop + nop + nop + nop + nop + nop + nop + +_divide_by_zero_handler: + bi _divide_by_zero_handler + nop + nop + nop + nop + nop + nop + nop + +_interrupt_handler: + sw (sp+0), ra + calli .save_all + rcsr r1, IP + calli up_doirq + bi .restore_all_and_eret + nop + nop + nop + +_syscall_handler: + sw (sp+0), ra + calli .save_all + rcsr r1, IP + calli lm32_swint + bi .restore_all_and_eret + nop + nop + nop + +_do_reset: + /* Setup stack and global pointer */ + + mvhi sp, hi(_fstack) + ori sp, sp, lo(_fstack) + + /* Clear BSS */ + + mvhi r1, hi(_sbss) + ori r1, r1, lo(_sbss) + mvhi r3, hi(_ebss) + ori r3, r3, lo(_ebss) + +.clearBSS: + be r1, r3, .callMain + sw (r1+0), r0 + addi r1, r1, 4 + bi .clearBSS + +.callMain: + bi os_start + +.save_all: + addi sp, sp, -132 + sw (sp+REG_X0), r0 + sw (sp+REG_X1), r1 + sw (sp+REG_X2), r2 + sw (sp+REG_X3), r3 + sw (sp+REG_X4), r4 + sw (sp+REG_X5), r5 + sw (sp+REG_X6), r6 + sw (sp+REG_X7), r7 + sw (sp+REG_X8), r8 + sw (sp+REG_X9), r9 + sw (sp+REG_X10), r10 + sw (sp+REG_X11), r11 + sw (sp+REG_X12), r12 + sw (sp+REG_X13), r13 + sw (sp+REG_X14), r14 + sw (sp+REG_X15), r15 + sw (sp+REG_X16), r16 + sw (sp+REG_X17), r17 + sw (sp+REG_X18), r18 + sw (sp+REG_X19), r19 + sw (sp+REG_X20), r20 + sw (sp+REG_X21), r21 + sw (sp+REG_X22), r22 + sw (sp+REG_X23), r23 + sw (sp+REG_X24), r24 + sw (sp+REG_X25), r25 + + sw (sp+REG_GP), r26 + sw (sp+REG_FP), r27 + sw (sp+REG_SP), r28 + + /* reg RA done later */ + + sw (sp+REG_EA), r30 + sw (sp+REG_BA), r31 + + /* ra needs to be moved from initial stack location */ + + lw r1, (sp+ 132) + sw (sp+REG_RA), r1 + + /* the 2nd argument is the regs pointer */ + + addi r2, sp, 0 + ret + +.restore_all_and_eret: + /* r1 should have the place where we restore ! */ + + lw r2, (r1+REG_X2) + lw r3, (r1+REG_X3) + lw r4, (r1+REG_X4) + lw r5, (r1+REG_X5) + lw r6, (r1+REG_X6) + lw r7, (r1+REG_X7) + lw r8, (r1+REG_X8) + lw r9, (r1+REG_X9) + lw r10, (r1+REG_X10) + lw r11, (r1+REG_X11) + lw r12, (r1+REG_X12) + lw r13, (r1+REG_X13) + lw r14, (r1+REG_X14) + lw r15, (r1+REG_X15) + lw r16, (r1+REG_X16) + lw r17, (r1+REG_X17) + lw r18, (r1+REG_X18) + lw r19, (r1+REG_X19) + lw r20, (r1+REG_X20) + lw r21, (r1+REG_X21) + lw r22, (r1+REG_X22) + lw r23, (r1+REG_X23) + lw r24, (r1+REG_X24) + lw r25, (r1+REG_X25) + lw r26, (r1+REG_GP) + lw r27, (r1+REG_FP) + lw r28, (r1+REG_SP) + lw r29, (r1+REG_RA) + lw r30, (r1+REG_EA) + lw r31, (r1+REG_BA) + lw r1, (r1+REG_X1) + addi sp, sp, 132 + eret + + /* This global variable is unsigned long g_idle_topstack and is + * exported from here only because of its coupling to other + * uses of _ebss in this file + */ + + .data + .align 4 + .globl g_idle_topstack + .type g_idle_topstack, object + +g_idle_topstack: + .long _ebss+CONFIG_IDLETHREAD_STACKSIZE + .size g_idle_topstack, .-g_idle_topstack + .end -- GitLab From 0088f24603a5e73d503e0ea779712e1ff124f270 Mon Sep 17 00:00:00 2001 From: Ramtin Amin Date: Tue, 1 Nov 2016 12:47:35 -0600 Subject: [PATCH 281/734] MISOC LM32: Add arch/src/common directory --- arch/misoc/Kconfig | 1 - arch/misoc/src/common/Kconfig | 8 -- arch/misoc/src/common/hw/common.h | 49 +++++++ arch/misoc/src/common/hw/ethmac_mem.h | 54 ++++++++ arch/misoc/src/common/hw/flags.h | 79 ++++++++++++ arch/misoc/src/common/misoc_isr.c | 20 --- arch/misoc/src/common/misoc_uart.c | 177 ++++++++++++++++++++------ arch/misoc/src/common/misoc_uart.h | 60 +++++++++ arch/misoc/src/lm32/Make.defs | 4 +- arch/misoc/src/lm32/chip.h | 92 +++++++++++++ arch/misoc/src/lm32/lm32_irq.c | 2 +- arch/misoc/src/lm32/lm32_isr.c | 61 +++++++++ 12 files changed, 533 insertions(+), 74 deletions(-) delete mode 100644 arch/misoc/src/common/Kconfig create mode 100644 arch/misoc/src/common/hw/common.h create mode 100644 arch/misoc/src/common/hw/ethmac_mem.h create mode 100644 arch/misoc/src/common/hw/flags.h delete mode 100644 arch/misoc/src/common/misoc_isr.c create mode 100644 arch/misoc/src/common/misoc_uart.h create mode 100644 arch/misoc/src/lm32/chip.h create mode 100644 arch/misoc/src/lm32/lm32_isr.c diff --git a/arch/misoc/Kconfig b/arch/misoc/Kconfig index 74a2a7649b..5cfbf0268c 100644 --- a/arch/misoc/Kconfig +++ b/arch/misoc/Kconfig @@ -62,7 +62,6 @@ config MISOC_UART_TX_BUF_SIZE ---help--- Size of TX buffers for MISOC UARTs -source arch/misoc/src/common/Kconfig ifdef ARCH_CHIP_LM32 source arch/misoc/src/lm32/Kconfig endif diff --git a/arch/misoc/src/common/Kconfig b/arch/misoc/src/common/Kconfig deleted file mode 100644 index 6cd8cd8175..0000000000 --- a/arch/misoc/src/common/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -if ARCH_MISOC - -endif # ARCH_MISOC diff --git a/arch/misoc/src/common/hw/common.h b/arch/misoc/src/common/hw/common.h new file mode 100644 index 0000000000..a6a7a92159 --- /dev/null +++ b/arch/misoc/src/common/hw/common.h @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/misoc/src/common/hw/common.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MISOC_SRC_COMMON_HW_COMMON_H +#define __ARCH_MISOC_SRC_COMMON_HW_COMMON_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef __ASSEMBLER__ +# define MMPTR(x) x +#else +# define MMPTR(x) (*((volatile unsigned int *)(x))) +#endif + +#endif /* __ARCH_MISOC_SRC_COMMON_HW_COMMON_H */ diff --git a/arch/misoc/src/common/hw/ethmac_mem.h b/arch/misoc/src/common/hw/ethmac_mem.h new file mode 100644 index 0000000000..6196480912 --- /dev/null +++ b/arch/misoc/src/common/hw/ethmac_mem.h @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/misoc/src/common/hw/emac_mem.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MISOC_SRC_COMMON_HW_EMAC_MEM_H +#define __ARCH_MISOC_SRC_COMMON_HW_EMAC_MEM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ETHMAC_RX0_BASE ETHMAC_BASE +#define ETHMAC_RX1_BASE (ETHMAC_BASE+0x0800) +#define ETHMAC_TX0_BASE (ETHMAC_BASE+0x1000) +#define ETHMAC_TX1_BASE (ETHMAC_BASE+0x1800) + +#endif /* __ARCH_MISOC_SRC_COMMON_HW_EMAC_MEM_H */ diff --git a/arch/misoc/src/common/hw/flags.h b/arch/misoc/src/common/hw/flags.h new file mode 100644 index 0000000000..7ed2f4bf42 --- /dev/null +++ b/arch/misoc/src/common/hw/flags.h @@ -0,0 +1,79 @@ +/**************************************************************************** + * arch/misoc/src/common/hw/emac_mem.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MISOC_SRC_COMMON_HW_FLAGS_H +#define __ARCH_MISOC_SRC_COMMON_HW_FLAGS_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define UART_EV_TX 0x1 +#define UART_EV_RX 0x2 + +#define DFII_CONTROL_SEL 0x01 +#define DFII_CONTROL_CKE 0x02 +#define DFII_CONTROL_ODT 0x04 +#define DFII_CONTROL_RESET_N 0x08 + +#define DFII_COMMAND_CS 0x01 +#define DFII_COMMAND_WE 0x02 +#define DFII_COMMAND_CAS 0x04 +#define DFII_COMMAND_RAS 0x08 +#define DFII_COMMAND_WRDATA 0x10 +#define DFII_COMMAND_RDDATA 0x20 + +#define ETHMAC_EV_SRAM_WRITER 0x1 +#define ETHMAC_EV_SRAM_READER 0x1 + +#define CLKGEN_STATUS_BUSY 0x1 +#define CLKGEN_STATUS_PROGDONE 0x2 +#define CLKGEN_STATUS_LOCKED 0x4 + +#define DVISAMPLER_TOO_LATE 0x1 +#define DVISAMPLER_TOO_EARLY 0x2 + +#define DVISAMPLER_DELAY_MASTER_CAL 0x01 +#define DVISAMPLER_DELAY_MASTER_RST 0x02 +#define DVISAMPLER_DELAY_SLAVE_CAL 0x04 +#define DVISAMPLER_DELAY_SLAVE_RST 0x08 +#define DVISAMPLER_DELAY_INC 0x10 +#define DVISAMPLER_DELAY_DEC 0x20 + +#define DVISAMPLER_SLOT_EMPTY 0 +#define DVISAMPLER_SLOT_LOADED 1 +#define DVISAMPLER_SLOT_PENDING 2 + +#endif /* __ARCH_MISOC_SRC_COMMON_HW_FLAGS_H */ diff --git a/arch/misoc/src/common/misoc_isr.c b/arch/misoc/src/common/misoc_isr.c deleted file mode 100644 index 96c726b17c..0000000000 --- a/arch/misoc/src/common/misoc_isr.c +++ /dev/null @@ -1,20 +0,0 @@ -#include - -void uart_isr(); -void uart_isr() -{ - -} - -void isr(void); -void isr(void) -{ - unsigned int irqs; - - irqs = irq_pending() & irq_getmask(); - - if (irqs & (1 << UART_INTERRUPT)) - { - uart_isr(); - } -} diff --git a/arch/misoc/src/common/misoc_uart.c b/arch/misoc/src/common/misoc_uart.c index 7a36e78199..77410f5071 100644 --- a/arch/misoc/src/common/misoc_uart.c +++ b/arch/misoc/src/common/misoc_uart.c @@ -1,3 +1,42 @@ +/**************************************************************************** + * arch/misoc/src/common/misoc_uart.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + #include #include #include @@ -20,11 +59,15 @@ #include #include "hw/flags.h" -#include "misoc_irqasm.h" +#include "chip.h" #include "misoc_uart.h" #include "lm32.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + /* Buffer sizes must be a power of 2 so that modulos can be computed * with logical AND. */ @@ -32,91 +75,140 @@ #define UART_RINGBUFFER_SIZE_RX 128 #define UART_RINGBUFFER_MASK_RX (UART_RINGBUFFER_SIZE_RX-1) +#define UART_RINGBUFFER_SIZE_TX 128 +#define UART_RINGBUFFER_MASK_TX (UART_RINGBUFFER_SIZE_TX-1) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + static char rx_buf[UART_RINGBUFFER_SIZE_RX]; static volatile unsigned int rx_produce; static unsigned int rx_consume; -#define UART_RINGBUFFER_SIZE_TX 128 -#define UART_RINGBUFFER_MASK_TX (UART_RINGBUFFER_SIZE_TX-1) - static char tx_buf[UART_RINGBUFFER_SIZE_TX]; static unsigned int tx_produce; static volatile unsigned int tx_consume; -static int uart_interrupt(int irq, void *context); - +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: uart_interrupt + ****************************************************************************/ + static int uart_interrupt(int irq, void *context) { unsigned int stat, rx_produce_next; stat = uart_ev_pending_read(); - if(stat & UART_EV_RX) { - while(!uart_rxempty_read()) { - rx_produce_next = (rx_produce + 1) & UART_RINGBUFFER_MASK_RX; - if(rx_produce_next != rx_consume) { - rx_buf[rx_produce] = uart_rxtx_read(); - rx_produce = rx_produce_next; - } - uart_ev_pending_write(UART_EV_RX); + if ((stat & UART_EV_RX) != 0) + { + while (!uart_rxempty_read()) + { + rx_produce_next = (rx_produce + 1) & UART_RINGBUFFER_MASK_RX; + if (rx_produce_next != rx_consume) + { + rx_buf[rx_produce] = uart_rxtx_read(); + rx_produce = rx_produce_next; + } + + uart_ev_pending_write(UART_EV_RX); + } } - } - if(stat & UART_EV_TX) { - uart_ev_pending_write(UART_EV_TX); - while((tx_consume != tx_produce) && !uart_txfull_read()) { - uart_rxtx_write(tx_buf[tx_consume]); - tx_consume = (tx_consume + 1) & UART_RINGBUFFER_MASK_TX; + if ((stat & UART_EV_TX) != 0) + { + uart_ev_pending_write(UART_EV_TX); + while ((tx_consume != tx_produce) && !uart_txfull_read()) + { + uart_rxtx_write(tx_buf[tx_consume]); + tx_consume = (tx_consume + 1) & UART_RINGBUFFER_MASK_TX; + } } - } return OK; } -/* Do not use in interrupt handlers! */ +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: uart_read + * + * Do not use in interrupt handlers! + * + ****************************************************************************/ + char uart_read(void) { char c; - if(irq_getie()) { - while(rx_consume == rx_produce); - } else if (rx_consume == rx_produce) { - return 0; - } + if (irq_getie()) + { + while (rx_consume == rx_produce); + } + else if (rx_consume == rx_produce) + { + return 0; + } c = rx_buf[rx_consume]; rx_consume = (rx_consume + 1) & UART_RINGBUFFER_MASK_RX; return c; } +/**************************************************************************** + * Name: uart_read_nonblock + ****************************************************************************/ + int uart_read_nonblock(void) { return (rx_consume != rx_produce); } +/**************************************************************************** + * Name: up_putc + ****************************************************************************/ + int up_putc(int ch) { unsigned int oldmask; unsigned int tx_produce_next = (tx_produce + 1) & UART_RINGBUFFER_MASK_TX; - if(irq_getie()) { - while(tx_produce_next == tx_consume); - } else if(tx_produce_next == tx_consume) { - return ch; - } + if (irq_getie()) + { + while (tx_produce_next == tx_consume); + } + else if (tx_produce_next == tx_consume) + { + return ch; + } oldmask = irq_getmask(); irq_setmask(oldmask & ~(1 << UART_INTERRUPT)); - if((tx_consume != tx_produce) || uart_txfull_read()) { - tx_buf[tx_produce] = ch; - tx_produce = tx_produce_next; - } else { - uart_rxtx_write(ch); - } + + if ((tx_consume != tx_produce) || uart_txfull_read()) + { + tx_buf[tx_produce] = ch; + tx_produce = tx_produce_next; + } + else + { + uart_rxtx_write(ch); + } + irq_setmask(oldmask); return ch; } +/**************************************************************************** + * Name: uart_init + ****************************************************************************/ + void uart_init(void) { rx_produce = 0; @@ -132,10 +224,11 @@ void uart_init(void) irq_attach(1 << UART_INTERRUPT, uart_interrupt); } +/**************************************************************************** + * Name: uart_sync + ****************************************************************************/ + void uart_sync(void) { - while(tx_consume != tx_produce); + while (tx_consume != tx_produce); } - - - diff --git a/arch/misoc/src/common/misoc_uart.h b/arch/misoc/src/common/misoc_uart.h new file mode 100644 index 0000000000..74fcc7c0ac --- /dev/null +++ b/arch/misoc/src/common/misoc_uart.h @@ -0,0 +1,60 @@ +/**************************************************************************** + * arch/misoc/src/common/misoc_uart.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MISOC_SRC_COMMON_MISOC_UART_H +#define __ARCH_MISOC_SRC_COMMON_MISOC_UART_H 1 + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif + +void uart_init(void); +void uart_isr(void); +void uart_sync(void); + +void uart_write(char c); +char uart_read(void); +int uart_read_nonblock(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __ARCH_MISOC_SRC_COMMON_MISOC_UART_H */ diff --git a/arch/misoc/src/lm32/Make.defs b/arch/misoc/src/lm32/Make.defs index 1c12e0c527..1a0ce75de2 100644 --- a/arch/misoc/src/lm32/Make.defs +++ b/arch/misoc/src/lm32/Make.defs @@ -45,5 +45,5 @@ CHIP_CSRCS = lm32_allocateheap.c lm32_assert.c lm32_blocktask.c CHIP_CSRCS += lm32_copystate.c lm32_createstack.c lm32_doirq.c lm32_dumpstate.c CHIP_CSRCS += lm32_dumpstate.c lm32_exit.c lm32_idle.c lm32_initialize.c CHIP_CSRCS += lm32_initialstate.c lm32_interruptcontext.c lm32_irq.c -CHIP_CSRCS += lm32_releasepending.c lm32_releasestack.c lm32_stackframe.c -CHIP_CSRCS += lm32_swint.c lm32_unblocktask.c +CHIP_CSRCS += lm32_isr.c lm32_releasepending.c lm32_releasestack.c +CHIP_CSRCS += lm32_stackframe.c lm32_swint.c lm32_unblocktask.c diff --git a/arch/misoc/src/lm32/chip.h b/arch/misoc/src/lm32/chip.h new file mode 100644 index 0000000000..0683bd5a28 --- /dev/null +++ b/arch/misoc/src/lm32/chip.h @@ -0,0 +1,92 @@ +/**************************************************************************** + * arch/misoc/src/lm32/chip.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MISOC_SRC_LM32_CHIP_H +#define __ARCH_MISOC_SRC_LM32_CHIP_H 1 + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif + +static inline unsigned int irq_getie(void) +{ + unsigned int ie; + __asm__ __volatile__("rcsr %0, IE" : "=r" (ie)); + return ie; +} + +static inline void irq_setie(unsigned int ie) +{ + __asm__ __volatile__("wcsr IE, %0" : : "r" (ie)); +} + +static inline unsigned int irq_getmask(void) +{ + + unsigned int mask; + __asm__ __volatile__("rcsr %0, IM" : "=r" (mask)); + return mask; +} + +static inline void irq_setmask(unsigned int mask) +{ + __asm__ __volatile__("wcsr IM, %0" : : "r" (mask)); +} + +static inline unsigned int irq_pending(void) +{ + + unsigned int pending; + __asm__ __volatile__("rcsr %0, IP" : "=r" (pending)); + return pending; +} + +#ifdef __cplusplus +} +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +void uart_isr(void); +void isr(void); + +#endif /* __ARCH_MISOC_SRC_LM32_CHIP_H */ diff --git a/arch/misoc/src/lm32/lm32_irq.c b/arch/misoc/src/lm32/lm32_irq.c index b99bb443b4..2e01b511fd 100644 --- a/arch/misoc/src/lm32/lm32_irq.c +++ b/arch/misoc/src/lm32/lm32_irq.c @@ -46,7 +46,7 @@ #include #include -#include "misoc_irqasm.h" +#include "chip_irqasm.h" #include "lm32.h" /**************************************************************************** diff --git a/arch/misoc/src/lm32/lm32_isr.c b/arch/misoc/src/lm32/lm32_isr.c new file mode 100644 index 0000000000..539614d317 --- /dev/null +++ b/arch/misoc/src/lm32/lm32_isr.c @@ -0,0 +1,61 @@ +/**************************************************************************** + * arch/misoc/src/lm32/lm32_isr.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip_irqasm.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void uart_isr() +{ +} + +void isr(void) +{ + unsigned int irqs; + + irqs = irq_pending() & irq_getmask(); + + if (irqs & (1 << UART_INTERRUPT)) + { + uart_isr(); + } +} -- GitLab From 1787a8143ee405ca0b64b7e6f9466893d388036e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 1 Nov 2016 14:18:21 -0600 Subject: [PATCH 282/734] Misoc: Logic on common directory should not include ANY lm32 specific header file. The generic header file chip.h can be exported by all architectures and that is what should be included instead of lm32.h which is an inappropriate dependency. --- arch/misoc/src/common/misoc_uart.c | 3 +-- arch/misoc/src/lm32/chip.h | 6 ++++++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/misoc/src/common/misoc_uart.c b/arch/misoc/src/common/misoc_uart.c index 77410f5071..76cdd48703 100644 --- a/arch/misoc/src/common/misoc_uart.c +++ b/arch/misoc/src/common/misoc_uart.c @@ -59,10 +59,9 @@ #include #include "hw/flags.h" -#include "chip.h" #include "misoc_uart.h" -#include "lm32.h" +#include "chip.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/misoc/src/lm32/chip.h b/arch/misoc/src/lm32/chip.h index 0683bd5a28..bdb8823c5a 100644 --- a/arch/misoc/src/lm32/chip.h +++ b/arch/misoc/src/lm32/chip.h @@ -36,6 +36,12 @@ #ifndef __ARCH_MISOC_SRC_LM32_CHIP_H #define __ARCH_MISOC_SRC_LM32_CHIP_H 1 +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#include "lm32.h" + /**************************************************************************** * Inline Functions ****************************************************************************/ -- GitLab From 20a1642552e1d8254294867a06fdd6cd6dddeec1 Mon Sep 17 00:00:00 2001 From: Aleksandr Vyhovanec Date: Tue, 1 Nov 2016 23:34:30 +0300 Subject: [PATCH 283/734] To write the last page --- arch/arm/src/stm32/stm32_flash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/stm32/stm32_flash.c b/arch/arm/src/stm32/stm32_flash.c index 56aa1f75ed..73f1419506 100644 --- a/arch/arm/src/stm32/stm32_flash.c +++ b/arch/arm/src/stm32/stm32_flash.c @@ -313,7 +313,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) addr -= STM32_FLASH_BASE; } - if ((addr+count) >= STM32_FLASH_SIZE) + if ((addr+count) > STM32_FLASH_SIZE) { return -EFAULT; } -- GitLab From 51f345ff88277baf5ff328962fd051c533faa8d3 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Tue, 1 Nov 2016 14:42:54 -0600 Subject: [PATCH 284/734] Add basic support to Micromint Bambino 200E board. This includes contributions from Jim Wolfman. --- Documentation/README.html | 4 +- README.txt | 2 + configs/Kconfig | 13 + configs/README.txt | 3 + configs/bambino-200e/Kconfig | 7 + configs/bambino-200e/README.txt | 453 +++++++++ configs/bambino-200e/include/board.h | 360 +++++++ configs/bambino-200e/nsh/Make.defs | 132 +++ configs/bambino-200e/nsh/defconfig | 989 ++++++++++++++++++++ configs/bambino-200e/nsh/setenv.sh | 92 ++ configs/bambino-200e/scripts/flash.sh | 156 +++ configs/bambino-200e/scripts/ramconfig.ld | 151 +++ configs/bambino-200e/scripts/spificonfig.ld | 147 +++ configs/bambino-200e/src/.gitignore | 2 + configs/bambino-200e/src/Makefile | 82 ++ configs/bambino-200e/src/bambino-200e.h | 127 +++ configs/bambino-200e/src/lpc43_appinit.c | 166 ++++ configs/bambino-200e/src/lpc43_autoleds.c | 177 ++++ configs/bambino-200e/src/lpc43_boot.c | 74 ++ configs/bambino-200e/src/lpc43_buttons.c | 220 +++++ configs/bambino-200e/src/lpc43_ostest.c | 112 +++ configs/bambino-200e/src/lpc43_userleds.c | 134 +++ 22 files changed, 3602 insertions(+), 1 deletion(-) create mode 100644 configs/bambino-200e/Kconfig create mode 100644 configs/bambino-200e/README.txt create mode 100644 configs/bambino-200e/include/board.h create mode 100644 configs/bambino-200e/nsh/Make.defs create mode 100644 configs/bambino-200e/nsh/defconfig create mode 100644 configs/bambino-200e/nsh/setenv.sh create mode 100644 configs/bambino-200e/scripts/flash.sh create mode 100644 configs/bambino-200e/scripts/ramconfig.ld create mode 100644 configs/bambino-200e/scripts/spificonfig.ld create mode 100644 configs/bambino-200e/src/.gitignore create mode 100644 configs/bambino-200e/src/Makefile create mode 100644 configs/bambino-200e/src/bambino-200e.h create mode 100644 configs/bambino-200e/src/lpc43_appinit.c create mode 100644 configs/bambino-200e/src/lpc43_autoleds.c create mode 100644 configs/bambino-200e/src/lpc43_boot.c create mode 100644 configs/bambino-200e/src/lpc43_buttons.c create mode 100644 configs/bambino-200e/src/lpc43_ostest.c create mode 100644 configs/bambino-200e/src/lpc43_userleds.c diff --git a/Documentation/README.html b/Documentation/README.html index bdc92c660c..baf534cf50 100644 --- a/Documentation/README.html +++ b/Documentation/README.html @@ -8,7 +8,7 @@

    NuttX README Files

    -

    Last Updated: July 3, 2016

    +

    Last Updated: November 1, 2016

    @@ -62,6 +62,8 @@ nuttx/ | | `- README.txt | |- avr32dev1/ | | `- README.txt + | |- bambino-200e/ + | | `- README.txt | |- c5471evm/ | | `- README.txt | |- cc3200-launchpad/ diff --git a/README.txt b/README.txt index 599200988d..9915949d2a 100644 --- a/README.txt +++ b/README.txt @@ -1279,6 +1279,8 @@ nuttx/ | | `- README.txt | |- avr32dev1/ | | `- README.txt + | |- bambino-200e/ + | | `- README.txt | |- c5471evm/ | | `- README.txt | |- cc3200-launchpad/ diff --git a/configs/Kconfig b/configs/Kconfig index 0c5135513a..21a4becacc 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -318,6 +318,15 @@ config ARCH_BOARD_LPCXPRESSO Embedded Artists base board with NXP LPCExpresso LPC1768. This board is based on the NXP LPC1768. The Code Red toolchain is used by default. +config ARCH_BOARD_BAMBINO_200E + bool "Micromint Bambino 200E" + depends on ARCH_CHIP_LPC4330FBD144 + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + Micromint Bambino board. This board is based on the LPC4330FBD144. + config ARCH_BOARD_LPC4330_XPLORER bool "NXG LPC4330-Xplorer" depends on ARCH_CHIP_LPC4330FET100 @@ -1381,6 +1390,7 @@ config ARCH_BOARD default "arduino-mega2560" if ARCH_BOARD_ARDUINO_MEGA2560 default "arduino-due" if ARCH_BOARD_ARDUINO_DUE default "avr32dev1" if ARCH_BOARD_AVR32DEV1 + default "bambino-200e" if ARCH_BOARD_BAMBINO_200E default "c5471evm" if ARCH_BOARD_C5471EVM default "cloudctrl" if ARCH_BOARD_CLOUDCTRL default "compal_e86" if ARCH_BOARD_COMPALE86 @@ -1555,6 +1565,9 @@ endif if ARCH_BOARD_AVR32DEV1 source "configs/avr32dev1/Kconfig" endif +if ARCH_BOARD_BAMBINO_200E +source "configs/bambino-200e/Kconfig" +endif if ARCH_BOARD_C5471EVM source "configs/c5471evm/Kconfig" endif diff --git a/configs/README.txt b/configs/README.txt index c95087f42a..de1342ced2 100644 --- a/configs/README.txt +++ b/configs/README.txt @@ -191,6 +191,9 @@ configs/avr32dev1 Atmel website. STATUS: This port is functional but very basic. There are configurations for NSH and the OS test. +configs/bambino-200e + Micromint Bambino board. This board is based on the LPC4330FBD144. + configs/c5471evm This is a port to the Spectrum Digital C5471 evaluation board. The TMS320C5471 is a dual core processor from TI with an ARM7TDMI general diff --git a/configs/bambino-200e/Kconfig b/configs/bambino-200e/Kconfig new file mode 100644 index 0000000000..3892c96da7 --- /dev/null +++ b/configs/bambino-200e/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_BAMBINO_200E +endif diff --git a/configs/bambino-200e/README.txt b/configs/bambino-200e/README.txt new file mode 100644 index 0000000000..d56e44ab92 --- /dev/null +++ b/configs/bambino-200e/README.txt @@ -0,0 +1,453 @@ +README +====== + +README for NuttX port to the "Bambino 200E" board from Micromint USA +featuring the NXP LPC4330FBD144 MCU + +Contents +======== + + - Bambino 200E board + - Status + - Serial Console + - FPU + - Bambino-200e Configuration Options + - Configurations + +Bambino 200E board +===================== + + Memory Map + ---------- + + Block Start Length + Name Address + --------------------- ---------- ------ + RAM 0x10000000 128K + RAM2 0x10080000 72K + RAMAHB 0x20000000 32K + RAMAHB2 0x20008000 16K + RAMAHB3 0x2000c000 16K + SPIFI flash 0x1e000000 4096K + + GPIO Usage: + ----------- + + GPIO PIN SIGNAL NAME + -------------------------------- ------- -------------- + gpio3[7] - LED1 101 GPIO3[7] + gpio5[5] - LED2 91 GPIO5[5] + gpio0[7] - BTN1 96 GPIO0[7] + + Console + ------- + + The Bambino 200E default console is the UART1 on Gadgeteer Sockets 5 (U). + +Status +====== + + Many drivers are working (USB0 Device, Ethernet, etc), but many drivers are + missing. + +Development Environment +======================= + + Either Linux or Cygwin on Windows can be used for the development environment. + The source has been built only using the GNU toolchain (see below). Other + toolchains will likely cause problems. Testing was performed using the Cygwin + environment. + +Serial Console +============== + +The LPC4330 Xplorer does not have RS-232 drivers or serial connectors on board. +USART0 and UART1 are available on J8 as follows: + + ------ ------ ----------------------- + SIGNAL J8 PIN LPC4330FET100 PIN + (TFBGA100 package) + ------ ------ ----------------------- + U0_TXD pin 9 F6 P6_4 U0_TXD=Alt 2 + U0_RXD pin 10 F9 P6_5 U0_RXD=Alt 2 + U1_TXD pin 13 H8 P1_13 U1_TXD=Alt 1 + U1_RXD pin 14 J8 P1_14 U1_RXD=Alt 1 + ------ ------ ----------------------- + + GND is available on J8 pin 1 + 5V is available on J8 pin 2 + VBAT is available on J8 pin 3 + +FPU +=== + +FPU Configuration Options +------------------------- + +There are two version of the FPU support built into the most NuttX Cortex-M4 +ports. The current LPC43xx port support only one of these options, the "Non- +Lazy Floating Point Register Save". As a consequence, CONFIG_ARMV7M_CMNVECTOR +must be defined in *all* LPC43xx configuration files. + +1. Lazy Floating Point Register Save. + + This is an untested implementation that saves and restores FPU registers + only on context switches. This means: (1) floating point registers are + not stored on each context switch and, hence, possibly better interrupt + performance. But, (2) since floating point registers are not saved, + you cannot use floating point operations within interrupt handlers. + + This logic can be enabled by simply adding the following to your .config + file: + + CONFIG_ARCH_FPU=y + +2. Non-Lazy Floating Point Register Save + + Mike Smith has contributed an extensive re-write of the ARMv7-M exception + handling logic. This includes verified support for the FPU. These changes + have not yet been incorporated into the mainline and are still considered + experimental. These FPU logic can be enabled with: + + CONFIG_ARCH_FPU=y + CONFIG_ARMV7M_CMNVECTOR=y + + You will probably also changes to the ld.script in if this option is selected. + This should work: + + -ENTRY(_stext) + +ENTRY(__start) /* Treat __start as the anchor for dead code stripping */ + +EXTERN(_vectors) /* Force the vectors to be included in the output */ + +CFLAGS +------ + +Only the recent toolchains have built-in support for the Cortex-M4 FPU. You will see +the following lines in each Make.defs file: + + ifeq ($(CONFIG_ARCH_FPU),y) + ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -march=armv7e-m -mfpu=fpv4-sp-d16 -mfloat-abi=hard + else + ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft + endif + +Configuration Changes +--------------------- + +Below are all of the configuration changes that I had to make to configs/stm3240g-eval/nsh2 +in order to successfully build NuttX using the Atollic toolchain WITH FPU support: + + -CONFIG_ARCH_FPU=n : Enable FPU support + +CONFIG_ARCH_FPU=y + + -CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : Disable the CodeSourcery toolchain + +CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=n + + -CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=n : Enable the Atollic toolchains + +CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC=y : + + -CONFIG_INTELHEX_BINARY=y : Suppress generation FLASH download formats + +CONFIG_INTELHEX_BINARY=n : (Only necessary with the "Lite" version) + + -CONFIG_HAVE_CXX=y : Suppress generation of C++ code + +CONFIG_HAVE_CXX=n : (Only necessary with the "Lite" version) + +See the section above on Toolchains, NOTE 2, for explanations for some of +the configuration settings. Some of the usual settings are just not supported +by the "Lite" version of the Atollic toolchain. + +Bambino-200e Configuration Options +================================== + + CONFIG_ARCH - Identifies the arch/ subdirectory. This should + be set to: + + CONFIG_ARCH=arm + + CONFIG_ARCH_family - For use in C code: + + CONFIG_ARCH_ARM=y + + CONFIG_ARCH_architecture - For use in C code: + + CONFIG_ARCH_CORTEXM4=y + + CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory + + CONFIG_ARCH_CHIP=lpc43xx + + CONFIG_ARCH_CHIP_name - For use in C code to identify the exact + chip: + + CONFIG_ARCH_CHIP_LPC4330=y + + CONFIG_ARCH_BOARD - Identifies the configs subdirectory and + hence, the board that supports the particular chip or SoC. + + CONFIG_ARCH_BOARD=bambino-200e (for the Bambino-200e board) + + CONFIG_ARCH_BOARD_name - For use in C code + + CONFIG_ARCH_BOARD_BAMBINO_200E=y + + CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation + of delay loops + + CONFIG_ENDIAN_BIG - define if big endian (default is little + endian) + + CONFIG_RAM_SIZE - Describes the installed DRAM (CPU SRAM in this case): + + CONFIG_RAM_SIZE=(32*1024) (32Kb) + + There is an additional 32Kb of SRAM in AHB SRAM banks 0 and 1. + + CONFIG_RAM_START - The start address of installed DRAM + + CONFIG_RAM_START=0x10000000 + + CONFIG_ARCH_FPU - The LPC43xxx supports a floating point unit (FPU) + + CONFIG_ARCH_FPU=y + + CONFIG_LPC43_BOOT_xxx - The startup code needs to know if the code is running + from internal FLASH, external FLASH, SPIFI, or SRAM in order to + initialize properly. Note that a boot device is not specified for + cases where the code is copied into SRAM; those cases are all covered + by CONFIG_LPC43_BOOT_SRAM. + + CONFIG_LPC43_BOOT_SRAM=y : Running from SRAM (0x1000:0000) + CONFIG_LPC43_BOOT_SPIFI=y : Running from QuadFLASH (0x1400:0000) + CONFIG_LPC43_BOOT_FLASHA=y : Running in internal FLASHA (0x1a00:0000) + CONFIG_LPC43_BOOT_FLASHB=y : Running in internal FLASHA (0x1b00:0000) + CONFIG_LPC43_BOOT_CS0FLASH=y : Running in external FLASH CS0 (0x1c00:0000) + CONFIG_LPC43_BOOT_CS1FLASH=y : Running in external FLASH CS1 (0x1d00:0000) + CONFIG_LPC43_BOOT_CS2FLASH=y : Running in external FLASH CS2 (0x1e00:0000) + CONFIG_LPC43_BOOT_CS3FLASH=y : Running in external FLASH CS3 (0x1f00:0000) + + CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that + have LEDs + + CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt + stack. If defined, this symbol is the size of the interrupt + stack in bytes. If not defined, the user task stacks will be + used during interrupt handling. + + CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions + + CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture. + + CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that + cause a 100 second delay during boot-up. This 100 second delay + serves no purpose other than it allows you to calibratre + CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure + the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until + the delay actually is 100 seconds. + + Individual subsystems can be enabled: + + CONFIG_LPC43_ADC0=y + CONFIG_LPC43_ADC1=y + CONFIG_LPC43_ATIMER=y + CONFIG_LPC43_CAN1=y + CONFIG_LPC43_CAN2=y + CONFIG_LPC43_DAC=y + CONFIG_LPC43_EMC=y + CONFIG_LPC43_ETHERNET=y + CONFIG_LPC43_EVNTMNTR=y + CONFIG_LPC43_GPDMA=y + CONFIG_LPC43_I2C0=y + CONFIG_LPC43_I2C1=y + CONFIG_LPC43_I2S0=y + CONFIG_LPC43_I2S1=y + CONFIG_LPC43_LCD=y + CONFIG_LPC43_MCPWM=y + CONFIG_LPC43_QEI=y + CONFIG_LPC43_RIT=y + CONFIG_LPC43_RTC=y + CONFIG_LPC43_SCT=y + CONFIG_LPC43_SDMMC=y + CONFIG_LPC43_SPI=y + CONFIG_LPC43_SPIFI=y + CONFIG_LPC43_SSP0=y + CONFIG_LPC43_SSP1=y + CONFIG_LPC43_TMR0=y + CONFIG_LPC43_TMR1=y + CONFIG_LPC43_TMR2=y + CONFIG_LPC43_TMR3=y + CONFIG_LPC43_USART0=y + CONFIG_LPC43_UART1=y + CONFIG_LPC43_USART2=y + CONFIG_LPC43_USART3=y + CONFIG_LPC43_USB0=y + CONFIG_LPC43_USB1=y + CONFIG_LPC43_USB1_ULPI=y + CONFIG_LPC43_WWDT=y + + LPC43xx specific U[S]ART device driver settings + + CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the UARTn for the + console and ttys0 (default is the USART0). + CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received. + This specific the size of the receive buffer + CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before + being sent. This specific the size of the transmit buffer + CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be + CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8. + CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity + CONFIG_U[S]ARTn_2STOP - Two stop bits + + CONFIG_USARTn_RS485MODE - Support LPC43xx USART0,2,3 RS485 mode + ioctls (TIOCSRS485 and TIOCGRS485) to enable and disable + RS-485 mode. + + LPC43xx specific CAN device driver settings. These settings all + require CONFIG_CAN: + + CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default + Standard 11-bit IDs. + CONFIG_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC43_CAN1 is defined. + CONFIG_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC43_CAN2 is defined. + CONFIG_CAN1_DIVISOR - CAN1 is clocked at CCLK divided by this number. + (the CCLK frequency is divided by this number to get the CAN clock). + Options = {1,2,4,6}. Default: 4. + CONFIG_CAN2_DIVISOR - CAN2 is clocked at CCLK divided by this number. + (the CCLK frequency is divided by this number to get the CAN clock). + Options = {1,2,4,6}. Default: 4. + CONFIG_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6 + CONFIG_CAN_TSEG2 = the number of CAN time quanta in segment 2. Default: 7 + + LPC43xx specific PHY/Ethernet device driver settings. These setting + also require CONFIG_NET and CONFIG_LPC43_ETHERNET. + + CONFIG_ETH0_PHY_KS8721 - Selects Micrel KS8721 PHY + CONFIG_PHY_AUTONEG - Enable auto-negotion + CONFIG_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed. + CONFIG_PHY_FDUPLEX - Select full (vs. half) duplex + + CONFIG_NET_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb + CONFIG_NET_NTXDESC - Configured number of Tx descriptors. Default: 18 + CONFIG_NET_NRXDESC - Configured number of Rx descriptors. Default: 18 + CONFIG_NET_WOL - Enable Wake-up on Lan (not fully implemented). + CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs + CONFIG_DEBUG_FEATURES. + CONFIG_NET_DUMPPACKET - Dump all received and transmitted packets. + Also needs CONFIG_DEBUG_FEATURES. + CONFIG_NET_HASH - Enable receipt of near-perfect match frames. + + LPC43xx USB Device Configuration + + CONFIG_LPC43_USBDEV_FRAME_INTERRUPT + Handle USB Start-Of-Frame events. + Enable reading SOF from interrupt handler vs. simply reading on demand. + Probably a bad idea... Unless there is some issue with sampling the SOF + from hardware asynchronously. + CONFIG_LPC43_USBDEV_EPFAST_INTERRUPT + Enable high priority interrupts. I have no idea why you might want to + do that + CONFIG_LPC43_USBDEV_NDMADESCRIPTORS + Number of DMA descriptors to allocate in SRAM. + CONFIG_LPC43_USBDEV_DMA + Enable lpc17xx-specific DMA support + CONFIG_LPC43_USBDEV_NOVBUS + Define if the hardware implementation does not support the VBUS signal + CONFIG_LPC43_USBDEV_NOLED + Define if the hardware implementation does not support the LED output + + LPC43xx USB Host Configuration + + CONFIG_USBHOST_OHCIRAM_SIZE + Total size of OHCI RAM (in AHB SRAM Bank 1) + CONFIG_USBHOST_NEDS + Number of endpoint descriptors + CONFIG_USBHOST_NTDS + Number of transfer descriptors + CONFIG_USBHOST_TDBUFFERS + Number of transfer descriptor buffers + CONFIG_USBHOST_TDBUFSIZE + Size of one transfer descriptor buffer + CONFIG_USBHOST_IOBUFSIZE + Size of one end-user I/O buffer. This can be zero if the + application can guarantee that all end-user I/O buffers + reside in AHB SRAM. + +Configurations +============== + +Each Bambino-200e configuration is maintained in a sub-directory and can be selected +as follow: + + cd tools + ./configure.sh bambino-200e/ + cd - + . ./setenv.sh + +Where is one of the following: + + nsh: + ---- + This configuration is the NuttShell (NSH) example at examples/nsh/. + + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configurations using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository. + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. By default, this project assumes that you are executing directly from + SRAM. + + CONFIG_LPC43_BOOT_SRAM=y : Executing in SRAM + CONFIG_ARMV7M_TOOLCHAIN_CODEREDW=y : Code Red under Windows + + 3. To execute from SPIFI, you would need to set: + + CONFIG_LPC43_BOOT_SPIFI=y : Executing from SPIFI + CONFIG_RAM_SIZE=(128*1024) : SRAM Bank0 size + CONFIG_RAM_START=0x10000000 : SRAM Bank0 base address + CONFIG_SPIFI_OFFSET=(512*1024) : SPIFI file system offset + + CONFIG_MM_REGIONS should also be increased if you want to other SRAM banks + to the memory pool. + + 4. This configuration an also be used create a block device on the SPIFI + FLASH. CONFIG_LPC43_SPIFI=y must also be defined to enable SPIFI setup + support: + + SPIFI device geometry: + + CONFIG_SPIFI_OFFSET - Offset the beginning of the block driver this many + bytes into the device address space. This offset must be an exact + multiple of the erase block size (CONFIG_SPIFI_BLKSIZE). Default 0. + CONFIG_SPIFI_BLKSIZE - The size of one device erase block. If not defined + then the driver will try to determine the correct erase block size by + examining that data returned from spifi_initialize (which sometimes + seems bad). + + Other SPIFI options + + CONFIG_SPIFI_SECTOR512 - If defined, then the driver will report a more + FAT friendly 512 byte sector size and will manage the read-modify-write + operations on the larger erase block. + CONFIG_SPIFI_READONLY - Define to support only read-only operations. + CONFIG_SPIFI_LIBRARY - Don't use the LPC43xx ROM routines but, instead, + use an external library implementation of the SPIFI interface. + CONFIG_SPIFI_VERIFY - Verify all spifi_program() operations by reading + from the SPI address space after each write. + CONFIG_DEBUG_SPIFI_DUMP - Debug option to dump read/write buffers. You + probably do not want to enable this unless you want to dig through a + *lot* of debug output! Also required CONFIG_DEBUG_FEATURES, CONFIG_DEBUG_INFO, + and CONFIG_DEBUG_FS, + + 5. In my experience, there were some missing function pointers in the LPC43xx + SPIFI ROM routines and the SPIFI configuration could only be built with + CONFIG_SPIFI_LIBRARY=y. The SPIFI library is proprietary and cannot be + provided within NuttX open source repository; SPIFI library binaries can + be found on the lpcware.com website. In this build sceneario, you must + also provide the patch to the external SPIFI library be defining the make + variable EXTRA_LIBS in the top-level Make.defs file. Good luck! diff --git a/configs/bambino-200e/include/board.h b/configs/bambino-200e/include/board.h new file mode 100644 index 0000000000..d84320a8d3 --- /dev/null +++ b/configs/bambino-200e/include/board.h @@ -0,0 +1,360 @@ +/**************************************************************************** + * configs/bambino-200e/include/board.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis acassis@gmail.com [nuttx] + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIG_BAMBINO_200E_INCLUDE_BOARD_H +#define __CONFIG_BAMBINO_200E_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC43_GPIO_IRQ) +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking ****************************************************************/ +/* NOTE: The following definitions require lpc43_cgu.h. It is not included + * here because the including C file may not have that file in its include + * path. + * + * The Xplorer board has four crystals on board: + * + * Y1 - RTC 32.768 MHz oscillator input, + * Y2 - 24.576 MHz input to the UDA 1380 audio codec, + * Y3 - 12.000 MHz LPC43xx crystal oscillator input + * Y4 - 50 MHz input for Ethernet + */ + +#define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency (Y3) */ +#define BOARD_RTCCLK_FREQUENCY (32768) /* RTC oscillator frequency (Y1) */ +#define BOARD_INTRCOSC_FREQUENCY (4000000) /* Internal RC oscillator frequency */ + +/* Integer and direct modes are supported: + * + * In integer mode (Fclkout < 156000000): + * Fclkin = BOARD_XTAL_FREQUENCY + * Fclkout = Msel * FClkin / Nsel + * Fcco = 2 * Psel * Fclkout + * In direct mode (Fclkout > 156000000): + * Fclkin = BOARD_XTAL_FREQUENCY + * Fclkout = Msel * FClkin / Nsel + * Fcco = Fclkout + */ + +#ifdef CONFIG_LPC43_72MHz + +/* NOTE: At 72MHz, the calibrated value of CONFIG_BOARD_LOOPSPERMSEC was + * determined to be: + * + * CONFIG_BOARD_LOOPSPERMSEC=7191 + * + * executing from SRAM. + */ + +/* Final clocking (Integer mode with no ramp-up) + * + * Fclkout = 6 * 12MHz / 1 = 72MHz + * Fcco = 2 * 2 * 72MHz = 216MHz + */ + +# define BOARD_PLL_MSEL (6) /* Msel = 6 */ +# define BOARD_PLL_NSEL (1) /* Nsel = 1 */ +# define BOARD_PLL_PSEL (2) /* Psel = 2 */ + +# define BOARD_FCLKOUT_FREQUENCY (72000000) /* 6 * 12,000,000 / 1 */ +# define BOARD_FCCO_FREQUENCY (244000000) /* 2 * 2 * Fclkout */ + +#else + +/* NOTE: At 72MHz, the calibrated value of CONFIG_BOARD_LOOPSPERMSEC was + * determined to be: + * + * CONFIG_BOARD_LOOPSPERMSEC=18535 + * + * executing from SRAM. + */ + +/* Intermediate ramp-up clocking (Integer mode). If BOARD_PLL_RAMP_MSEL + * is not defined, there will be no ramp-up. + * + * Fclkout = 9 * 12MHz / 1 = 108MHz + * Fcco = 2 * 1 * 108MHz = 216MHz + */ + +# define BOARD_PLL_RAMP_MSEL (9) /* Msel = 9 */ +# define BOARD_PLL_RAMP_NSEL (1) /* Nsel = 1 */ +# define BOARD_PLL_RAMP_PSEL (1) /* Psel = 1 */ + +# define BOARD_RAMP_FCLKOUT (108000000) /* 9 * 12,000,000 / 1 */ +# define BOARD_RAMP_FCCO (216000000) /* 2 * 1 * Fclkout */ + +/* Final clocking (Direct mode). + * + * Fclkout = 17 * 12MHz / 1 = 204MHz + * Fcco = Fclockout = 204MHz + */ + +# define BOARD_PLL_MSEL (17) /* Msel = 17 */ +# define BOARD_PLL_NSEL (1) /* Nsel = 1 */ + +# define BOARD_FCLKOUT_FREQUENCY (204000000) /* 17 * 12,000,000 / 1 */ +# define BOARD_FCCO_FREQUENCY (204000000) /* Fclockout */ + +#endif + +/* This is the clock setup we configure for: + * + * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for source + * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> PLL0 multipler=20, pre-divider=1 + * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 + */ + +#define LPC43_CCLK BOARD_FCLKOUT_FREQUENCY + +/* APB Clocking */ + +#if defined(CONFIG_LPC43_BUS) || defined(CONFIG_LPC43_MCPWM) || \ + defined(CONFIG_LPC43_I2C0) || defined(CONFIG_LPC43_I2S0) || \ + defined(CONFIG_LPC43_I2S1) || defined(CONFIG_LPC43_CAN1) +# define BOARD_ABP1_CLKSRC BASE_APB_CLKSEL_XTAL +# define BOARD_ABP1_FREQUENCY BOARD_XTAL_FREQUENCY +#endif + + +#if defined(CONFIG_LPC43_BUS) || defined(CONFIG_LPC43_I2C1) || \ + defined(CONFIG_LPC43_DAC) || defined(CONFIG_LPC43_ADC0) || \ + defined(CONFIG_LPC43_ADC1) || defined(CONFIG_LPC43_CAN0) +# define BOARD_ABP3_CLKSRC BASE_APB_CLKSEL_XTAL +# define BOARD_ABP3_FREQUENCY BOARD_XTAL_FREQUENCY +#endif + +/* SSP Clocking */ + +#define BOARD_IDIVA_DIVIDER (2) +#define BOARD_IDIVA_CLKSRC IDIVA_CLKSEL_PLL1 +#define BOARD_IDIVA_FREQUENCY (BOARD_FCLKOUT_FREQUENCY/BOARD_IDIVA_DIVIDER) + +#define BOARD_SSP0_CLKSRC BASE_SSP0_CLKSEL_IDIVA +#define BOARD_SSP0_BASEFREQ BOARD_IDIVA_FREQUENCY + +#define BOARD_SSP1_CLKSRC BASE_SSP1_CLKSEL_IDIVA +#define BOARD_SSP1_BASEFREQ BOARD_IDIVA_FREQUENCY + +/* USB0 ********************************************************************/ +/* Settings needed in lpc43_cpu.c */ + +#define BOARD_USB0_CLKSRC PLL0USB_CLKSEL_XTAL +#define BOARD_USB0_MDIV 0x06167ffa /* Table 149 datsheet, valid for 12Mhz Fclkin */ +#define BOARD_USB0_NP_DIV 0x00302062 /* Table 149 datsheet, valid for 12Mhz Fclkin */ + +/* SPIFI clocking **********************************************************/ +/* The SPIFI will receive clocking from a divider per the settings provided + * in this file. The NuttX code will configure PLL1 as the input clock + * for the selected divider + */ + +#undef BOARD_SPIFI_PLL1 /* No division */ +#undef BOARD_SPIFI_DIVA /* Supports division by 1-4 */ +#undef BOARD_SPIFI_DIVB /* Supports division by 1-16 */ +#undef BOARD_SPIFI_DIVC /* Supports division by 1-16 */ +#undef BOARD_SPIFI_DIVD /* Supports division by 1-16 */ +#undef BOARD_SPIFI_DIVE /* Supports division by 1-256 */ + +#if BOARD_FCLKOUT_FREQUENCY < 20000000 +# define BOARD_SPIFI_PLL1 1 /* Use PLL1 directly */ +#else +# define BOARD_SPIFI_DIVB 1 /* Use IDIVB */ +#endif + + +/* We need to configure the divider so that its output is as close to the + * desired SCLK value. The peak data transfer rate will be about half of + * this frequency in bytes per second. + */ + +#if BOARD_FCLKOUT_FREQUENCY < 20000000 +# define BOARD_SPIFI_FREQUENCY BOARD_FCLKOUT_FREQUENCY /* 72Mhz? */ +#else +# define BOARD_SPIFI_DIVIDER (14) /* 204MHz / 14 = 14.57MHz */ +# define BOARD_SPIFI_FREQUENCY (102000000) /* 204MHz / 14 = 14.57MHz */ +#endif + +/* UART clocking ***********************************************************/ +/* Configure all U[S]ARTs to use the XTAL input frequency */ + +#define BOARD_USART0_CLKSRC BASE_USART0_CLKSEL_XTAL +#define BOARD_USART0_BASEFREQ BOARD_XTAL_FREQUENCY + +#define BOARD_UART1_CLKSRC BASE_UART1_CLKSEL_XTAL +#define BOARD_UART1_BASEFREQ BOARD_XTAL_FREQUENCY + +#define BOARD_USART2_CLKSRC BASE_USART2_CLKSEL_XTAL +#define BOARD_USART2_BASEFREQ BOARD_XTAL_FREQUENCY + +#define BOARD_USART3_CLKSRC BASE_USART3_CLKSEL_XTAL +#define BOARD_USART3_BASEFREQ BOARD_XTAL_FREQUENCY + +/* LED definitions *********************************************************/ +/* The Bambino 200E has 2 user-controllable LEDs labeled LED1 and LED2 in the + * schematic and on bus referred to has GPIO3[7] and GPIO5[5], respectively. + * + * LED1 GPIO3[7] + * LED2 GPIO5[5] + * + * LEDs are pulled high to a low output illuminates the LED. + * + * LED index values for use with board_userled() + */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_NLEDS 2 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) + +/* If CONFIG_ARCH_LEDS is defined, the LEDs will be controlled as follows + * for NuttX debug functionality (where NC means "No Change"). If + * CONFIG_ARCH_LEDS is not defined, then the LEDs are completely under + * control of the application. The following interfaces are then available + * for application control of the LEDs: + * + * void board_userled_initialize(void); + * void board_userled(int led, bool ledon); + * void board_userled_all(uint8_t ledset); + */ + /* ON OFF */ + /* LED1 LED2 LED1 LED2 */ +#define LED_STARTED 0 /* OFF OFF - - */ +#define LED_HEAPALLOCATE 1 /* ON OFF - - */ +#define LED_IRQSENABLED 1 /* ON OFF - - */ +#define LED_STACKCREATED 1 /* ON OFF - - */ +#define LED_INIRQ 2 /* NC ON NC OFF */ +#define LED_SIGNAL 2 /* NC ON NC OFF */ +#define LED_ASSERTION 2 /* NC ON NC OFF */ +#define LED_PANIC 2 /* NC ON NC OFF */ + +/* UART Pins ****************************************************************/ +/* The Bambino 200E does not have RS-232 drivers or serial connectors on + * board. UART1 and USART2 are availables on Socket 5 and 10, recpectively: + * + * ------ ---------- ----------------------- + * SIGNAL Socket/Pin LPC4330FBD144 PIN + * ------ ---------- ----------------------- + * U1_TXD s:5 / p:4 63 P5_6 U1_TXD=Alt 1 + * U1_RXD s:5 / p:5 61 P1_14 U1_RXD=Alt 1 + * U2_TXD s:10 / p:4 104 P2_10 U2_TXD=Alt 1 + * U2_RXD s:10 / p:5 105 P2_11 U2_RXD=Alt 1 + * ------ ---------- ----------------------- + * + * The following definitions must be provided so that the LPC43 serial + * driver can set up the U[S]ART for the serial console properly (see the + * file arch/arc/src/lpc43xx/lpc4310203050_pinconf.h for more info). + */ + +#define PINCONF_U0_TXD PINCONF_U0_TXD_3 +#define PINCONF_U0_RXD PINCONF_U0_RXD_3 +#define PINCONF_U0_DIR PINCONF_U0_DIR_3 + +#define PINCONF_U1_TXD PINCONF_U1_TXD_5 +#define PINCONF_U1_RXD PINCONF_U1_RXD_1 + +#define PINCONF_U2_TXD PINCONF_U2_TXD_2 +#define PINCONF_U2_RXD PINCONF_U2_RXD_2 +#define PINCONF_U2_DIR PINCONF_U2_DIR_2 + +#define PINCONF_U3_TXD PINCONF_U3_TXD_2 +#define PINCONF_U3_RXD PINCONF_U3_RXD_2 +#define PINCONF_U3_DIR PINCONF_U3_DIR_2 + +/* Ethernet */ + +#define PINCONF_ENET_RX_DV PINCONF_ENET_RX_DV_2 +#define PINCONF_ENET_RESET PINCONF_GPIO0p4 +#define GPIO_ENET_RESET (GPIO_MODE_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT0 | GPIO_PIN4) +#define PINCONF_ENET_MDC PINCONF_ENET_MDC_3 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc43_boardinitialize + * + * Description: + * All LPC43xx architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ****************************************************************************/ + +void lpc43_boardinitialize(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIG_BAMBINO_200E_INCLUDE_BOARD_H */ diff --git a/configs/bambino-200e/nsh/Make.defs b/configs/bambino-200e/nsh/Make.defs new file mode 100644 index 0000000000..105969c6b1 --- /dev/null +++ b/configs/bambino-200e/nsh/Make.defs @@ -0,0 +1,132 @@ +############################################################################ +# configs/bambino-200e/nsh/Make.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# Alan Carvalho de Assis acassis@gmail.com [nuttx] +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +# Setup for the kind of memory that we are executing from + +ifeq ($(CONFIG_LPC43_BOOT_SRAM),y) + LDSCRIPT = ramconfig.ld +endif +ifeq ($(CONFIG_LPC43_BOOT_SPIFI),y) + LDSCRIPT = spificonfig.ld +endif +ifeq ($(CONFIG_LPC43_BOOT_FLASHA),y) + LDSCRIPT = flashaconfig.ld +endif +ifeq ($(CONFIG_LPC43_BOOT_FLASHB),y) + LDSCRIPT = flashaconfig.ld +endif +ifeq ($(CONFIG_LPC43_BOOT_CS0FLASH),y) + LDSCRIPT = cs0flash.ld +endif + +# Setup for Windows vs Linux/Cygwin/OSX environments + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/bambino-200e/nsh/defconfig b/configs/bambino-200e/nsh/defconfig new file mode 100644 index 0000000000..1593440d4b --- /dev/null +++ b/configs/bambino-200e/nsh/defconfig @@ -0,0 +1,989 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +CONFIG_ARCH_STDARG_H=y +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +# CONFIG_ARCH_HAVE_HEAPCHECK is not set +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ARCH_HAVE_CUSTOMOPT=y +CONFIG_DEBUG_NOOPT=y +# CONFIG_DEBUG_CUSTOMOPT is not set +# CONFIG_DEBUG_FULLOPT is not set + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +CONFIG_ARCH_CHIP_LPC43XX=y +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM3 is not set +CONFIG_ARCH_CORTEXM4=y +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="lpc43xx" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +CONFIG_ARMV7M_CMNVECTOR=y +# CONFIG_ARMV7M_LAZYFPU is not set +CONFIG_ARCH_HAVE_FPU=y +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y +# CONFIG_ARMV7M_HAVE_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set +# CONFIG_SERIAL_TERMIOS is not set + +# +# LPC43xx Configuration Options +# +# CONFIG_ARCH_CHIP_LPC4310FBD144 is not set +# CONFIG_ARCH_CHIP_LPC4310FET100 is not set +# CONFIG_ARCH_CHIP_LPC4320FBD144 is not set +# CONFIG_ARCH_CHIP_LPC4320FET100 is not set +CONFIG_ARCH_CHIP_LPC4330FBD144=y +# CONFIG_ARCH_CHIP_LPC4330FET100 is not set +# CONFIG_ARCH_CHIP_LPC4330FET180 is not set +# CONFIG_ARCH_CHIP_LPC4330FET256 is not set +# CONFIG_ARCH_CHIP_LPC4337JBD144 is not set +# CONFIG_ARCH_CHIP_LPC4337JET100 is not set +# CONFIG_ARCH_CHIP_LPC4350FBD208 is not set +# CONFIG_ARCH_CHIP_LPC4350FET180 is not set +# CONFIG_ARCH_CHIP_LPC4350FET256 is not set +# CONFIG_ARCH_CHIP_LPC4353FBD208 is not set +# CONFIG_ARCH_CHIP_LPC4353FET180 is not set +# CONFIG_ARCH_CHIP_LPC4353FET256 is not set +# CONFIG_ARCH_CHIP_LPC4357FET180 is not set +# CONFIG_ARCH_CHIP_LPC4357FBD208 is not set +# CONFIG_ARCH_CHIP_LPC4357FET256 is not set +# CONFIG_ARCH_CHIP_LPC4370FET100 is not set +CONFIG_ARCH_FAMILY_LPC4330=y +# CONFIG_LPC43_BOOT_SRAM is not set +CONFIG_LPC43_BOOT_SPIFI=y +# CONFIG_LPC43_BOOT_FLASHA is not set +# CONFIG_LPC43_BOOT_FLASHB is not set +# CONFIG_LPC43_BOOT_CS0FLASH is not set +# CONFIG_LPC43_BOOT_CS1FLASH is not set +# CONFIG_LPC43_BOOT_CS2FLASH is not set +# CONFIG_LPC43_BOOT_CS3FLASH is not set + +# +# LPC43xx Peripheral Support +# +# CONFIG_LPC43_ADC0 is not set +# CONFIG_LPC43_ADC1 is not set +# CONFIG_LPC43_ATIMER is not set +# CONFIG_LPC43_CAN1 is not set +# CONFIG_LPC43_CAN2 is not set +# CONFIG_LPC43_DAC is not set +# CONFIG_LPC43_EMC is not set +# CONFIG_LPC43_ETHERNET is not set +# CONFIG_LPC43_EVNTMNTR is not set +# CONFIG_LPC43_GPDMA is not set +# CONFIG_LPC43_I2C0 is not set +# CONFIG_LPC43_I2C1 is not set +# CONFIG_LPC43_I2S0 is not set +# CONFIG_LPC43_I2S1 is not set +# CONFIG_LPC43_LCD is not set +# CONFIG_LPC43_MCPWM is not set +# CONFIG_LPC43_QEI is not set +# CONFIG_LPC43_RIT is not set +# CONFIG_LPC43_RTC is not set +# CONFIG_LPC43_SCT is not set +# CONFIG_LPC43_SDMMC is not set +# CONFIG_LPC43_SPI is not set +# CONFIG_LPC43_SPIFI is not set +# CONFIG_LPC43_SSP0 is not set +# CONFIG_LPC43_SSP1 is not set +# CONFIG_LPC43_TMR0 is not set +# CONFIG_LPC43_TMR1 is not set +# CONFIG_LPC43_TMR2 is not set +# CONFIG_LPC43_TMR3 is not set +# CONFIG_LPC43_USART0 is not set +CONFIG_LPC43_UART1=y +# CONFIG_LPC43_USART2 is not set +# CONFIG_LPC43_USART3 is not set +# CONFIG_LPC43_USBOTG is not set +CONFIG_LPC43_USB0=y +# CONFIG_LPC43_USB1 is not set +# CONFIG_LPC43_WWDT is not set +# CONFIG_LPC43_GPIO_IRQ is not set + +# +# Internal Memory Configuration +# +CONFIG_ARCH_HAVE_AHB_SRAM_BANK1=y +# CONFIG_LPC43_USE_LOCSRAM_BANK1 is not set +# CONFIG_LPC43_USE_AHBSRAM_BANK0 is not set +# CONFIG_LPC43_USE_AHBSRAM_BANK1 is not set +# CONFIG_LPC43_HEAP_AHBSRAM_BANK2 is not set + +# +# External Memory Configuration +# + +# +# RS-485 Configuration +# +# CONFIG_USART2_RS485MODE is not set + +# +# USB device controller driver (DCD) options +# +# CONFIG_LPC43_USB0DEV_NOVBUS is not set + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=18535 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x10000000 +CONFIG_RAM_SIZE=131072 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_BAMBINO_200E=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="bambino-200e" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +# CONFIG_ARCH_BUTTONS is not set +CONFIG_ARCH_HAVE_IRQBUTTONS=y + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_RESET is not set +# CONFIG_BOARDCTL_UNIQUEID is not set +CONFIG_BOARDCTL_USBDEVCTRL=y +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_ADCTEST is not set +# CONFIG_BOARDCTL_PWMTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Clocks and Timers +# +CONFIG_ARCH_HAVE_TICKLESS=y +# CONFIG_SCHED_TICKLESS is not set +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2012 +CONFIG_START_MONTH=7 +CONFIG_START_DAY=11 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=0 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_HPWORK is not set +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +# CONFIG_DISABLE_POLL is not set +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +# CONFIG_ARCH_HAVE_I2CRESET is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +CONFIG_SERIAL_REMOVABLE=y +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +CONFIG_UART1_SERIALDRIVER=y +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_SERIAL_NPOLLWAITERS=2 +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +# CONFIG_SERIAL_TIOCSERGSTRUCT is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +CONFIG_UART1_SERIAL_CONSOLE=y +# CONFIG_USART2_SERIAL_CONSOLE is not set +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART1 Configuration +# +CONFIG_UART1_RXBUFSIZE=256 +CONFIG_UART1_TXBUFSIZE=256 +CONFIG_UART1_BAUD=115200 +CONFIG_UART1_BITS=8 +CONFIG_UART1_PARITY=0 +CONFIG_UART1_2STOP=0 +# CONFIG_UART1_IFLOWCONTROL is not set +# CONFIG_UART1_OFLOWCONTROL is not set +# CONFIG_UART1_DMA is not set +# CONFIG_PSEUDOTERM is not set +CONFIG_USBDEV=y + +# +# USB Device Controller Driver Options +# +# CONFIG_USBDEV_ISOCHRONOUS is not set +# CONFIG_USBDEV_DUALSPEED is not set +CONFIG_USBDEV_SELFPOWERED=y +# CONFIG_USBDEV_BUSPOWERED is not set +CONFIG_USBDEV_MAXPOWER=100 +# CONFIG_USBDEV_DMA is not set +# CONFIG_ARCH_USBDEV_STALLQUEUE is not set +# CONFIG_USBDEV_TRACE is not set + +# +# USB Device Class Driver Options +# +# CONFIG_USBDEV_COMPOSITE is not set +# CONFIG_PL2303 is not set +CONFIG_CDCACM=y +# CONFIG_CDCACM_CONSOLE is not set +CONFIG_CDCACM_EP0MAXPACKET=64 +CONFIG_CDCACM_EPINTIN=1 +CONFIG_CDCACM_EPINTIN_FSSIZE=64 +CONFIG_CDCACM_EPINTIN_HSSIZE=64 +CONFIG_CDCACM_EPBULKOUT=3 +CONFIG_CDCACM_EPBULKOUT_FSSIZE=64 +CONFIG_CDCACM_EPBULKOUT_HSSIZE=512 +CONFIG_CDCACM_EPBULKIN=2 +CONFIG_CDCACM_EPBULKIN_FSSIZE=64 +CONFIG_CDCACM_EPBULKIN_HSSIZE=512 +CONFIG_CDCACM_NRDREQS=4 +CONFIG_CDCACM_NWRREQS=4 +CONFIG_CDCACM_BULKIN_REQLEN=96 +CONFIG_CDCACM_RXBUFSIZE=257 +CONFIG_CDCACM_TXBUFSIZE=193 +CONFIG_CDCACM_VENDORID=0x0525 +CONFIG_CDCACM_PRODUCTID=0xa4a7 +CONFIG_CDCACM_VENDORSTR="NuttX" +CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial" +# CONFIG_USBMSC is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +CONFIG_FS_READABLE=y +CONFIG_FS_WRITABLE=y +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +CONFIG_FS_FAT=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=32 +# CONFIG_FS_FATTIME is not set +# CONFIG_FAT_FORCE_INDIRECT is not set +# CONFIG_FAT_DMAMEMORY is not set +# CONFIG_FAT_DIRECT_RETRY is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=2 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +CONFIG_SYMTAB_ORDEREDBYNAME=y + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_LIBC_TMPDIR="/tmp" +CONFIG_LIBC_MAX_TMPFILE=32 +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set +# CONFIG_LIBC_NETDB is not set +# CONFIG_NETDB_HOSTFILE is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FSTEST is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set +# CONFIG_FSUTILS_PASSWD is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_BAS is not set +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CHAT is not set +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=64 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +CONFIG_NSH_CMDPARMS=y +CONFIG_NSH_MAXARGUMENTS=6 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFATFS is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Configure Command Options +# +CONFIG_NSH_CMDOPT_DF_H=y +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_CMDOPT_HEXDUMP=y +CONFIG_NSH_FILEIOSIZE=512 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_USBCONSOLE is not set +# CONFIG_NSH_ALTCONDEV is not set +CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +CONFIG_SYSTEM_CDCACM=y +CONFIG_SYSTEM_CDCACM_DEVMINOR=1 +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/bambino-200e/nsh/setenv.sh b/configs/bambino-200e/nsh/setenv.sh new file mode 100644 index 0000000000..9c39a440b6 --- /dev/null +++ b/configs/bambino-200e/nsh/setenv.sh @@ -0,0 +1,92 @@ +#!/bin/bash +# configs/bambino-200e/nsh/setenv.sh +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# Alan Carvalho de Assis acassis@gmail.com [nuttx] +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the Code Red +# toolchain under windows. You will have to edit this if you install the +# Code Red toolchain in any other location or if you install a different +# version +export TOOLCHAIN_BIN="/cygdrive/c/code_red/RedSuite_4.2.3_379/redsuite/Tools/bin" +#export SCRIPT_BIN="/cygdrive/c/code_red/RedSuite_4.2.3_379/redsuite/bin" +export SCRIPT_BIN="/cygdrive/c/nxp/LPCXpresso_4.2.3_292/lpcxpresso/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +#export SCRIPT_BIN= + +# These are the Cygwin paths to the locations where I installed the Atollic +# toolchain under windows. You will also have to edit this if you install +# the Atollic toolchain in any other location. /usr/bin is added before +# the Atollic bin path because there is are binaries named gcc.exe and g++.exe +# at those locations as well. +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" +#export SCRIPT_BIN= + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +#export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" +#export SCRIPT_BIN= + +# And add the selected toolchain path[s] to the PATH variable + +export PATH="/sbin:/usr/sbin:${PATH_ORIG}" + +if [ ! -z ${SCRIPT_BIN} ]; then + export PATH="${SCRIPT_BIN}:${PATH}" +fi + +export PATH="${TOOLCHAIN_BIN}:${PATH}" +echo "PATH : ${PATH}" + +# Set an alias that can be used to put the LPC43xx in boot mode + +alias lpc43xx='${SCRIPT_BIN}/Scripts/bootLPCXpresso.cmd winusb' diff --git a/configs/bambino-200e/scripts/flash.sh b/configs/bambino-200e/scripts/flash.sh new file mode 100644 index 0000000000..f738b460bc --- /dev/null +++ b/configs/bambino-200e/scripts/flash.sh @@ -0,0 +1,156 @@ +#!/bin/bash +#################################################################################### +# flash.sh +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# Alan Carvalho de Assis acassis@gmail.com [nuttx] +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +#################################################################################### +set -x + +USAGE="$0 " + +# LPCXpresso 3.6 installed at /cygdrive/c/nxp/lpcxpresso_3.6" + +BINDIR="/cygdrive/c/nxp/LPCXpresso_4.2.3_292/lpcxpresso/bin" + +# RedSuite with LPC4330 support installed at /cygdrive/c/code_red/RedSuite_4.2.3_379 " + +#BINDIR="/cygdrive/c/code_red/RedSuite_4.2.3_379/redsuite/bin" + +TARGET=LPC4330 + +echo "############################################################################" +echo "# Assumptions:" +echo "#" +echo "# - Windows 7" +echo "# - Binaries installed at ${BINDIR}" +echo "# - AXF image built with Code Red" +echo "# - ${TARGET}" +echo "#" +echo "# You will need to edit this is any of the above are false" +echo "#" +echo "############################################################################" +echo "" + +# This is the default install location for binaries on Windows (note that this +# path could change with the Code Red version number) + +if [ ! -d "${BINDIR}" ]; then + echo "Directory ${BINDIR} does not exist" + exit 1 +fi + +# This is the relative path to the booLPCXpresso utility. + +BOOTLPC="Scripts/bootLPCXpresso.cmd" +if [ ! -x "${BINDIR}/${BOOTLPC}" ]; then + echo "No executable at ${BINDIR}/${BOOTLPC}" + exit 1 +fi + +# bootLPCXpresso arguments + +BOOTLPC_ARG=winusb # Win7 + +# Use the LPC18xx/LPC43xx flash utility + +FLASHUTIL="crt_emu_lpc18_43_nxp" # for LPC18xx/LPC43xx parts + +if [ ! -x "${BINDIR}/${FLASHUTIL}" ]; then + echo "No executable file at ${BINDIR}/${FLASHUTIL}" + exit 1 +fi + +# FLUSHUTIL arguements + +WIRE="-wire=winusb" # for LPC-Link on Windows Vista/Windows 7) + +# The nuttx directory must be provided as an argument + +NUTTX=$1 +if [ -z "${NUTTX}" ]; then + echo "Missing argument" + echo $USAGE + exit 1 +fi + +if [ ! -d "${NUTTX}" ]; then + echo "Directory ${NUTTX} does not exist" + echo $USAGE + exit 1 +fi + +# The binary to download: + +if [ ! -f "${NUTTX}/nuttx.axf" ]; then + if [ -f "${NUTTX}/nuttx" ]; then + echo "Renaming ${NUTTX}/nuttx to ${NUTTX}/nuttx.axf" + mv ${NUTTX}/nuttx ${NUTTX}/nuttx.axf + fi +else + if [ -f "${NUTTX}/nuttx" ]; then + echo "Both ${NUTTX}/nuttx ${NUTTX}/nuttx.axf exist.." + echo " Deleting ${NUTTX}/nuttx.axf" + rm -f ${NUTTX}/nuttx.axf + echo "Renaming ${NUTTX}/nuttx to ${NUTTX}/nuttx.axf" + mv ${NUTTX}/nuttx ${NUTTX}/nuttx.axf + fi +fi +NUTTXPATH=`cygpath -w "${NUTTX}/nuttx.axf"` + +# First of all boot the LPC-Link using the script: ${BINDIR}/${BOOTLPC} + +cd ${BINDIR} || \ + { echo "Failed to CD to ${BINDIR}"; exit 1; } +./${BOOTLPC} ${BOOTLPC_ARG} || \ + { echo "'${BOOTLPC} ${BOOTLPC_ARG}' Failed"; } + +echo "" +echo "Wait a bit" +echo "5..." +sleep 1 +echo "4..." +sleep 1 +echo "3..." +sleep 1 +echo "2..." +sleep 1 +echo "1..." +sleep 1 +echo "0..." +echo "" + +# Then program the FLASH + +cd ${BINDIR} || \ + { echo "Failed to CD to ${BINDIR}"; exit 1; } +./${FLASHUTIL} ${WIRE} -p${TARGET} -flash-load-exec="${NUTTXPATH}" diff --git a/configs/bambino-200e/scripts/ramconfig.ld b/configs/bambino-200e/scripts/ramconfig.ld new file mode 100644 index 0000000000..c524bf25bf --- /dev/null +++ b/configs/bambino-200e/scripts/ramconfig.ld @@ -0,0 +1,151 @@ +/**************************************************************************** + * configs/bambino-200e/scripts/ramconfig.ld + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis acassis@gmail.com [nuttx] + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ +/* + * Power-Up Reset Overview + * ----------------------- + * + * The ARM core starts executing code on reset with the program counter set + * to 0x0000 0000. The LPC43xx contains a shadow pointer register that + * allows areas of memory to be mapped to address 0x0000 0000. The default, + * reset value of the shadow pointer is 0x1040 0000 so that on reset code in + * the boot ROM is always executed first. + * + * The boot starts after reset is released. The IRC is selected as CPU clock + * and the Cortex-M4 starts the boot loader. By default the JTAG access to the + * chip is disabled at reset. The boot ROM determines the boot mode based on + * the OTP BOOT_SRC value or reset state pins. For flash-based parts, the part + * boots from internal flash by default. Otherwse, the boot ROM copies the + * image to internal SRAM at location 0x1000 0000, sets the ARM's shadow + * pointer to 0x1000 0000, and jumps to that location. + * + * However, using JTAG the executable image can be also loaded directly into + * and executed from SRAM. + */ + +/* The LPC4330 on the LPC4330-Xplorer has the following memory resources: + * + * 1. 4096Kb of SPIFI FLASH beginning at address 0x1400:0000 + * 2. 264KB of total SRAM: + * a. 128KB of SRAM in the CPU block beginning at address 0x1000:0000 + * b. 72KB beginning at address 0x1008:0000 and + * c. 64KB of AHB SRAM in three banks beginning at addresses 0x2000:0000, + * 0x2000:8000 and 0x2000:C000. + * 3. No internal FLASH + * + * Here we assume that: + * + * 1. We will be running out of SRAM at 0x1000:0000, and + * 2. All .data and .bss will all fit into the 72KB SRAM block. + * + * NOTE: That initialized data is kept in the program memory SRAM and copied + * to .data SRAM. This is wasteful and unnecessary but provides a good test + * for future, FLASH-resident code. + */ + +MEMORY +{ + progmem (rx) : ORIGIN = 0x10000000, LENGTH = 128K + datamem (rwx) : ORIGIN = 0x10080000, LENGTH = 72K +} + +OUTPUT_ARCH(arm) +ENTRY(__start) /* Treat __start as the anchor for dead code stripping */ +EXTERN(_vectors) /* Force the vectors to be included in the output */ +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > progmem + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > progmem + + .ARM.extab : { + *(.ARM.extab*) + } > progmem + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > progmem + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > datamem AT > progmem + + .bss : { /* BSS */ + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > datamem + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/bambino-200e/scripts/spificonfig.ld b/configs/bambino-200e/scripts/spificonfig.ld new file mode 100644 index 0000000000..283672e7e0 --- /dev/null +++ b/configs/bambino-200e/scripts/spificonfig.ld @@ -0,0 +1,147 @@ +/**************************************************************************** + * configs/bambino-200e/scripts/spificonfig.ld + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis acassis@gmail.com [nuttx] + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ +/* + * Power-Up Reset Overview + * ----------------------- + * + * The ARM core starts executing code on reset with the program counter set + * to 0x0000 0000. The LPC43xx contains a shadow pointer register that + * allows areas of memory to be mapped to address 0x0000 0000. The default, + * reset value of the shadow pointer is 0x1040 0000 so that on reset code in + * the boot ROM is always executed first. + * + * The boot starts after reset is released. The IRC is selected as CPU clock + * and the Cortex-M4 starts the boot loader. By default the JTAG access to the + * chip is disabled at reset. The boot ROM determines the boot mode based on + * the OTP BOOT_SRC value or reset state pins. For flash-based parts, the part + * boots from internal flash by default. Otherwse, the boot ROM copies the + * image to internal SRAM at location 0x1000 0000, sets the ARM's shadow + * pointer to 0x1000 0000, and jumps to that location. + * + * Of course, using JTAG the executable image can be also loaded directly + * into and executed from SRAM. + */ + +/* The LPC4330 on the LPC4330-Xplorer has the following memory resources: + * + * 1. 4096Kb of SPIFI FLASH beginning at address 0x1400:0000 + * 2. 264KB of total SRAM: + * a. 128KB of SRAM in the CPU block beginning at address 0x1000:0000 + * b. 72KB beginning at address 0x1008:0000 and + * c. 64KB of AHB SRAM in three banks beginning at addresses 0x2000:0000, + * 0x2000:8000 and 0x2000:C000. + * 3. No internal FLASH + * + * Here we assume that: + * + * 1. We will be running out of SPIFI flash at 0x1400:0000, and + * 2. All .data and .bss will all fit into the 128KB CPU SRAM block. + */ + +MEMORY +{ + progmem (rx) : ORIGIN = 0x14000000, LENGTH = 1024K + datamem (rwx) : ORIGIN = 0x10000000, LENGTH = 128K +} + +OUTPUT_ARCH(arm) +ENTRY(__start) /* Treat __start as the anchor for dead code stripping */ +EXTERN(_vectors) /* Force the vectors to be included in the output */ +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > progmem + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > progmem + + .ARM.extab : { + *(.ARM.extab*) + } > progmem + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > progmem + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > datamem AT > progmem + + .bss : { /* BSS */ + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > datamem + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/bambino-200e/src/.gitignore b/configs/bambino-200e/src/.gitignore new file mode 100644 index 0000000000..726d936e1e --- /dev/null +++ b/configs/bambino-200e/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/configs/bambino-200e/src/Makefile b/configs/bambino-200e/src/Makefile new file mode 100644 index 0000000000..fa49acd104 --- /dev/null +++ b/configs/bambino-200e/src/Makefile @@ -0,0 +1,82 @@ +############################################################################ +# configs/bambino-200e/src/Makefile +# +# Copyright (C) 2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# Alan Carvalho de Assis acassis@gmail.com [nuttx] +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = lpc43_boot.c + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += lpc43_appinit.c +endif + +ifeq ($(CONFIG_ARCH_FPU),y) +CSRCS += lpc43_ostest.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += lpc43_autoleds.c +else +CSRCS += lpc43_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += lpc43_buttons.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += lpc43_usbmsc.c +endif + +ifeq ($(CONFIG_SPIFI_LIBRARY),y) +CFLAGS += -DEUROBIRD +SPIFI_LIB = spifi_lib +CSRCS += $(SPIFI_LIB)/spifi_rom_api.c +#CSRCS += $(SPIFI_LIB)/amic.c +#CSRCS += $(SPIFI_LIB)/atmel.c +#CSRCS += $(SPIFI_LIB)/chi.c +#CSRCS += $(SPIFI_LIB)/eon.c +#CSRCS += $(SPIFI_LIB)/esmt.c +#CSRCS += $(SPIFI_LIB)/esmt.c +#CSRCS += $(SPIFI_LIB)/giga.c +#CSRCS += $(SPIFI_LIB)/macronix.c +#CSRCS += $(SPIFI_LIB)/numonyx.c +CSRCS += $(SPIFI_LIB)/spansion.c +#CSRCS += $(SPIFI_LIB)/sst.c +CSRCS += $(SPIFI_LIB)/winbond.c +endif + +include $(TOPDIR)/configs/Board.mk diff --git a/configs/bambino-200e/src/bambino-200e.h b/configs/bambino-200e/src/bambino-200e.h new file mode 100644 index 0000000000..2ec6d17479 --- /dev/null +++ b/configs/bambino-200e/src/bambino-200e.h @@ -0,0 +1,127 @@ +/**************************************************************************** + * configs/bambino-200e/src/bambino-200e.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis acassis@gmail.com [nuttx] + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef _CONFIGS_BAMBINO_200E_SRC_BAMBINO_H +#define _CONFIGS_BAMBINO_200E_SRC_BAMBINO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "lpc43_pinconfig.h" +#include "lpc43_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * LEDs GPIO PIN SIGNAL NAME + * -------------------------------- ------- -------------- + * gpio3[7] - LED1 101 GPIO3[7] + * gpio5[5] - LED2 91 GPIO5[5] + * + ****************************************************************************/ + +/* Definitions to configure LED pins as GPIOs: + * + * - Floating + * - Normal drive + * - No buffering, glitch filtering, slew=slow + */ + +#define PINCONFIG_LED1 PINCONF_GPIO3p7 +#define PINCONFIG_LED2 PINCONF_GPIO5p5 +#define GPIO_LED1 (GPIO_MODE_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT3 | GPIO_PIN7) +#define GPIO_LED2 (GPIO_MODE_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT5 | GPIO_PIN5) + +/**************************************************************************** + * Buttons GPIO + * ---------------------------- + * gpio0[7] - User Button USR1 + ****************************************************************************/ + +#define BAMBINO_BUT1 (GPIO_INTBOTH | GPIO_FLOAT | GPIO_PORT0 | GPIO_PIN7) + +/* Button IRQ numbers */ + +#define BAMBINO_BUT1_IRQ LPC43_IRQ_P0p23 + +#define GPIO_SSP0_SCK GPIO_SSP0_SCK_1 +#define GPIO_SSP0_SSEL GPIO_SSP0_SSEL_1 +#define GPIO_SSP0_MISO GPIO_SSP0_MISO_1 +#define GPIO_SSP0_MOSI GPIO_SSP0_MOSI_1 + +/* We need to redefine USB_PWRD as GPIO to get USB Host working + * Also remember to add 2 resistors of 15K to D+ and D- pins. + */ + +#ifdef CONFIG_USBHOST +# ifdef GPIO_USB_PWRD +# undef GPIO_USB_PWRD +# define GPIO_USB_PWRD (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN22) +# endif +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc43_sspdev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Lincoln 80 board. + * + ****************************************************************************/ + +void weak_function lpc43_sspdev_initialize(void); + +#endif /* __ASSEMBLY__ */ +#endif /* _CONFIGS_BAMBINO_200E_SRC_BAMBINO_H */ diff --git a/configs/bambino-200e/src/lpc43_appinit.c b/configs/bambino-200e/src/lpc43_appinit.c new file mode 100644 index 0000000000..eae609cf2e --- /dev/null +++ b/configs/bambino-200e/src/lpc43_appinit.c @@ -0,0 +1,166 @@ +/**************************************************************************** + * config/bambino-200e/src/lpc43_appinit.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis acassis@gmail.com [nuttx] + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" + +#ifdef CONFIG_LPC43_SPIFI +# include +# include "lpc43_spifi.h" + +# ifdef CONFIG_SPFI_NXFFS +# include +# include +# endif +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SPIFI_DEVNO +# define CONFIG_SPIFI_DEVNO 0 +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nsh_spifi_initialize + * + * Description: + * Make the SPIFI (or part of it) into a block driver that can hold a + * file system. + * + ****************************************************************************/ + +#ifdef CONFIG_LPC43_SPIFI +static int nsh_spifi_initialize(void) +{ + FAR struct mtd_dev_s *mtd; + int ret; + + /* Initialize the SPIFI interface and create the MTD driver instance */ + + mtd = lpc43_spifi_initialize(); + if (!mtd) + { + ferr("ERROR: lpc43_spifi_initialize failed\n"); + return -ENODEV; + } + +#ifndef CONFIG_SPFI_NXFFS + /* And finally, use the FTL layer to wrap the MTD driver as a block driver */ + + ret = ftl_initialize(CONFIG_SPIFI_DEVNO, mtd); + if (ret < 0) + { + ferr("ERROR: Initializing the FTL layer: %d\n", ret); + return ret; + } +#else + /* Initialize to provide NXFFS on the MTD interface */ + + ret = nxffs_initialize(mtd); + if (ret < 0) + { + ferr("ERROR: NXFFS initialization failed: %d\n", ret); + return ret; + } + + /* Mount the file system at /mnt/spifi */ + + ret = mount(NULL, "/mnt/spifi", "nxffs", 0, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to mount the NXFFS volume: %d\n", errno); + return ret; + } +#endif + + return OK; +} +#else +# define nsh_spifi_initialize() (OK) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform architecture specific initialization + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ + /* Initialize the SPIFI block device */ + + return nsh_spifi_initialize(); +} diff --git a/configs/bambino-200e/src/lpc43_autoleds.c b/configs/bambino-200e/src/lpc43_autoleds.c new file mode 100644 index 0000000000..5fe074b10e --- /dev/null +++ b/configs/bambino-200e/src/lpc43_autoleds.c @@ -0,0 +1,177 @@ +/**************************************************************************** + * configs/bambino-200e/src/lpc43_autoleds.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis acassis@gmail.com [nuttx] + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" + +#include "bambino-200e.h" + +#ifdef CONFIG_ARCH_LEDS + +/* LED definitions **********************************************************/ +/* The LPC4330-Xplorer has 2 user-controllable LEDs labeled D2 an D3 in the + * schematic and on but referred to has LED1 and LED2 here, respectively. + * + * LED1 D2 GPIO1[12] + * LED2 D3 GPIO1[11] + * + * LEDs are pulled high to a low output illuminates the LED. + * + * If CONFIG_ARCH_LEDS is defined, the LEDs will be controlled as follows + * for NuttX debug functionality (where NC means "No Change"). + * + * ON OFF + * LED1 LED2 LED1 LED2 + * LED_STARTED 0 OFF OFF - - + * LED_HEAPALLOCATE 1 ON OFF - - + * LED_IRQSENABLED 1 ON OFF - - + * LED_STACKCREATED 1 ON OFF - - + * LED_INIRQ 2 NC ON NC OFF + * LED_SIGNAL 2 NC ON NC OFF + * LED_ASSERTION 2 NC ON NC OFF + * LED_PANIC 2 NC ON NC OFF + * + * If CONFIG_ARCH_LEDS is not defined, then the LEDs are completely under + * control of the application. The following interfaces are then available + * for application control of the LEDs: + * + * void board_userled_initialize(void); + * void board_userled(int led, bool ledon); + * void board_userled_all(uint8_t ledset); + */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_dumppins + ****************************************************************************/ + +#ifdef LED_VERBOSE +static void led_dumppins(FAR const char *msg) +{ + lpc43_pin_dump(PINCONFIG_LED1, msg); + lpc43_gpio_dump(GPIO_LED2, msg); +} +#else +# define led_dumppins(m) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure all LED pins as GPIO outputs */ + + led_dumppins("board_autoled_initialize() Entry)"); + + /* Configure LED pins as GPIOs, then configure GPIOs as outputs */ + + lpc43_pin_config(PINCONFIG_LED1); + lpc43_gpio_config(GPIO_LED1); + + lpc43_pin_config(PINCONFIG_LED2); + lpc43_gpio_config(GPIO_LED2); + + led_dumppins("board_autoled_initialize() Exit"); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + default: + case 0: + lpc43_gpio_write(GPIO_LED1, true); /* LED1 OFF */ + lpc43_gpio_write(GPIO_LED2, true); /* LED2 OFF */ + break; + + case 1: + lpc43_gpio_write(GPIO_LED1, false); /* LED1 ON */ + lpc43_gpio_write(GPIO_LED2, true); /* LED2 OFF */ + break; + + case 2: + lpc43_gpio_write(GPIO_LED2, false); /* LED2 ON */ + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + default: + case 0: + case 1: + break; + + case 2: + lpc43_gpio_write(GPIO_LED2, true); /* LED2 OFF */ + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/bambino-200e/src/lpc43_boot.c b/configs/bambino-200e/src/lpc43_boot.c new file mode 100644 index 0000000000..10c4237eff --- /dev/null +++ b/configs/bambino-200e/src/lpc43_boot.c @@ -0,0 +1,74 @@ +/************************************************************************************ + * configs/bambino-200e/src/lpc43_boot.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis acassis@gmail.com [nuttx] + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "bambino-200e.h" + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lpc43_boardinitialize + * + * Description: + * All LPC43xx architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void lpc43_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} diff --git a/configs/bambino-200e/src/lpc43_buttons.c b/configs/bambino-200e/src/lpc43_buttons.c new file mode 100644 index 0000000000..95755ccb79 --- /dev/null +++ b/configs/bambino-200e/src/lpc43_buttons.c @@ -0,0 +1,220 @@ +/**************************************************************************** + * configs/bambino-200e/src/lpc43_buttons.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis acassis@gmail.com [nuttx] + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include + +#include "bambino-200e.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each LPC4330 Xplorer button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint16_t g_buttoncfg[BOARD_NUM_BUTTONS] = +{ + BAMBINO_BUT1 +}; + +/* This array defines all of the interrupt handlers current attached to + * button events. + */ + +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC43_GPIO_IRQ) +static xcpt_t g_buttonisr[BOARD_NUM_BUTTONS]; + +/* This array provides the mapping from button ID numbers to button IRQ + * numbers. + */ + +static uint8_t g_buttonirq[BOARD_NUM_BUTTONS] = +{ + BAMBINO_BUT1_IRQ +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +void board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as interrupting inputs. */ + + for (i = 0; i < BOARD_NUM_BUTTONS; i++) + { + lpc43_configgpio(g_buttoncfg[i]); + } +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * board_button_initialize() must be called to initialize button resources. After + * that, board_buttons() may be called to collect the current state of all + * buttons. + * + * board_buttons() may be called at any time to harvest the state of every + * button. The state of the buttons is returned as a bitset with one + * bit corresponding to each button: If the bit is set, then the button + * is pressed. See the BOARD_BUTTON_*_BIT and BOARD_JOYSTICK_*_BIT + * definitions in board.h for the meaning of each bit. + * + ****************************************************************************/ + +uint8_t board_buttons(void) +{ + uint8_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < BOARD_NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = lpc43_gpio_read(g_buttoncfg[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. After + * that, board_button_irq() may be called to register button interrupt handlers. + * + * board_button_irq() may be called to register an interrupt handler that will + * be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See the + * BOARD_BUTTON_* and BOARD_JOYSTICK_* definitions in board.h for the meaning + * of enumeration values. The previous interrupt handler address is returned + * (so that it may restored, if so desired). + * + * Note that board_button_irq() also enables button interrupts. Button + * interrupts will remain enabled after the interrupt handler is attached. + * Interrupts may be disabled (and detached) by calling board_button_irq with + * irqhandler equal to NULL. + * + ****************************************************************************/ + +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_LPC43_GPIO_IRQ) +xcpt_t board_button_irq(int id, xcpt_t irqhandler) +{ + xcpt_t oldhandler = NULL; + irqstate_t flags; + int irq; + + /* Verify that the button ID is within range */ + + if ((unsigned)id < BOARD_NUM_BUTTONS) + { + /* Return the current button handler and set the new interrupt handler */ + + oldhandler = g_buttonisr[id]; + g_buttonisr[id] = irqhandler; + + /* Disable interrupts until we are done */ + + flags = enter_critical_section(); + + /* Configure the interrupt. Either attach and enable the new + * interrupt or disable and detach the old interrupt handler. + */ + + irq = g_buttonirq[id]; + if (irqhandler) + { + /* Attach then enable the new interrupt handler */ + + (void)irq_attach(irq, irqhandler); + up_enable_irq(irq); + } + else + { + /* Disable then detach the old interrupt handler */ + + up_disable_irq(irq); + (void)irq_detach(irq); + } + leave_critical_section(flags); + } + + return oldhandler; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/configs/bambino-200e/src/lpc43_ostest.c b/configs/bambino-200e/src/lpc43_ostest.c new file mode 100644 index 0000000000..5be6241373 --- /dev/null +++ b/configs/bambino-200e/src/lpc43_ostest.c @@ -0,0 +1,112 @@ +/************************************************************************************ + * configs/bambino-200e/src/lpc43_ostest.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis acassis@gmail.com [nuttx] + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" +#include "bambino-200e.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Configuration ********************************************************************/ + +#undef HAVE_FPU +#if defined(CONFIG_ARCH_FPU) && defined(CONFIG_EXAMPLES_OSTEST_FPUSIZE) && \ + defined(CONFIG_SCHED_WAITPID) && !defined(CONFIG_DISABLE_SIGNALS) && \ + !defined(CONFIG_ARMV7M_CMNVECTOR) +# define HAVE_FPU 1 +#endif + +#ifdef HAVE_FPU + +#if CONFIG_EXAMPLES_OSTEST_FPUSIZE != (4*SW_FPU_REGS) +# error "CONFIG_EXAMPLES_OSTEST_FPUSIZE has the wrong size" +#endif + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +static uint32_t g_saveregs[XCPTCONTEXT_REGS]; + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/* Given an array of size CONFIG_EXAMPLES_OSTEST_FPUSIZE, this function will return + * the current FPU registers. + */ + +void arch_getfpu(FAR uint32_t *fpusave) +{ + irqstate_t flags; + + /* Take a snapshot of the thread context right now */ + + flags = enter_critical_section(); + up_saveusercontext(g_saveregs); + + /* Return only the floating register values */ + + memcpy(fpusave, &g_saveregs[REG_S0], (4*SW_FPU_REGS)); + leave_critical_section(flags); +} + +/* Given two arrays of size CONFIG_EXAMPLES_OSTEST_FPUSIZE this function + * will compare them and return true if they are identical. + */ + +bool arch_cmpfpu(FAR const uint32_t *fpusave1, FAR const uint32_t *fpusave2) +{ + return memcmp(fpusave1, fpusave2, (4*SW_FPU_REGS)) == 0; +} + +#endif /* HAVE_FPU */ diff --git a/configs/bambino-200e/src/lpc43_userleds.c b/configs/bambino-200e/src/lpc43_userleds.c new file mode 100644 index 0000000000..46f223f675 --- /dev/null +++ b/configs/bambino-200e/src/lpc43_userleds.c @@ -0,0 +1,134 @@ +/**************************************************************************** + * configs/bambino-200e/src/lpc43_userleds.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis acassis@gmail.com [nuttx] + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" + +#include "bambino-200e.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LED definitions **********************************************************/ +/* The LPC4330-Xplorer has 2 user-controllable LEDs labeled D2 an D3 in the + * schematic and on but referred to has LED1 and LED2 here, respectively. + * + * LED1 D2 GPIO1[12] + * LED2 D3 GPIO1[11] + * + * LEDs are pulled high to a low output illuminates the LED. + */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_dumppins + ****************************************************************************/ + +#ifdef LED_VERBOSE +static void led_dumppins(FAR const char *msg) +{ + lpc43_pin_dump(PINCONFIG_LED1, msg); + lpc43_gpio_dump(GPIO_LED2, msg); +} +#else +# define led_dumppins(m) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ + /* Configure all LED GPIO lines */ + + led_dumppins("board_userled_initialize() Entry)"); + + /* Configure LED pins as GPIOs, then configure GPIOs as outputs */ + + lpc43_pin_config(PINCONFIG_LED1); + lpc43_gpio_config(GPIO_LED1); + + lpc43_pin_config(PINCONFIG_LED2); + lpc43_gpio_config(GPIO_LED2); + + led_dumppins("board_userled_initialize() Exit"); +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + uint16_t gpiocfg = (led == BOARD_LED1 ? GPIO_LED1 : GPIO_LED2); + lpc43_gpio_write(gpiocfg, !ledon); +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ + lpc43_gpio_write(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); + lpc43_gpio_write(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ -- GitLab From 2bb15fe789bd5fedc6fc71b22998cec4c909941e Mon Sep 17 00:00:00 2001 From: Aleksandr Vyhovanec Date: Tue, 1 Nov 2016 23:48:44 +0300 Subject: [PATCH 285/734] Minor changes --- arch/arm/src/stm32/stm32_1wire.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm/src/stm32/stm32_1wire.c b/arch/arm/src/stm32/stm32_1wire.c index d0afa9d8bb..00f24fc019 100644 --- a/arch/arm/src/stm32/stm32_1wire.c +++ b/arch/arm/src/stm32/stm32_1wire.c @@ -81,7 +81,11 @@ #define WRITE_TX0 0x00 #define WRITE_TX1 0xFF -#define PIN_OPENDRAIN(GPIO) ((GPIO) | GPIO_OPENDRAIN) +#define PIN_OPENDRAIN(GPIO) ((GPIO) | GPIO_CNF_OUTOD) + +#if defined(CONFIG_STM32_STM32F10XX) +# define USART_CR3_ONEBIT (0) +#endif /**************************************************************************** * Private Types @@ -568,13 +572,13 @@ static void stm32_1wire_set_apb_clock(struct stm32_1wire_priv_s *priv, regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32_UART4 +#ifdef CONFIG_STM32_UART4_1WIREDRIVER case STM32_UART4_BASE: rcc_en = RCC_APB1ENR_UART4EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32_UART5 +#ifdef CONFIG_STM32_UART5_1WIREDRIVER case STM32_UART5_BASE: rcc_en = RCC_APB1ENR_UART5EN; regaddr = STM32_RCC_APB1ENR; @@ -586,13 +590,13 @@ static void stm32_1wire_set_apb_clock(struct stm32_1wire_priv_s *priv, regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32_UART7 +#ifdef CONFIG_STM32_UART7_1WIREDRIVER case STM32_UART7_BASE: rcc_en = RCC_APB1ENR_UART7EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32_UART8 +#ifdef CONFIG_STM32_UART8_1WIREDRIVER case STM32_UART8_BASE: rcc_en = RCC_APB1ENR_UART8EN; regaddr = STM32_RCC_APB1ENR; -- GitLab From be1626ad7bcc597c34cdd7561b8236e0e31a54ab Mon Sep 17 00:00:00 2001 From: Aleksandr Vyhovanec Date: Wed, 2 Nov 2016 00:03:16 +0300 Subject: [PATCH 286/734] Added EEPROM timeout --- drivers/mtd/at24xx.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/mtd/at24xx.c b/drivers/mtd/at24xx.c index 91c8951193..7b4e38962e 100644 --- a/drivers/mtd/at24xx.c +++ b/drivers/mtd/at24xx.c @@ -139,6 +139,10 @@ # define CONFIG_AT24XX_MTD_BLOCKSIZE AT24XX_PAGESIZE #endif +#ifndef CONFIG_AT24XX_TIMEOUT_MS +# define CONFIG_AT24XX_TIMEOUT_MS 10 +#endif + /************************************************************************************ * Private Types ************************************************************************************/ @@ -252,6 +256,7 @@ static int at24c_eraseall(FAR struct at24c_dev_s *priv) { uint8_t buf[AT24XX_PAGESIZE + AT24XX_ADDRSIZE]; int startblock = 0; + uint16_t wait; memset(&buf[AT24XX_ADDRSIZE], 0xff, priv->pagesize); @@ -269,8 +274,14 @@ static int at24c_eraseall(FAR struct at24c_dev_s *priv) at24addr = (priv->addr | ((offset >> 8) & 0x07)); #endif + wait = CONFIG_AT24XX_TIMEOUT_MS; while (at24c_i2c_write(priv, at24addr, buf, AT24XX_ADDRSIZE) < 0) { + finfo("wait\n"); + if (!wait--) + { + return ERROR; + } usleep(1000); } @@ -301,6 +312,7 @@ static ssize_t at24c_read_internal(FAR struct at24c_dev_s *priv, off_t offset, { uint8_t buf[AT24XX_ADDRSIZE]; uint16_t at24addr; + uint16_t wait; finfo("offset: %lu nbytes: %lu address: %02x\n", (unsigned long)offset, (unsigned long)nbytes, address); @@ -327,9 +339,14 @@ static ssize_t at24c_read_internal(FAR struct at24c_dev_s *priv, off_t offset, at24addr = (address | ((offset >> 8) & 0x07)); #endif + wait = CONFIG_AT24XX_TIMEOUT_MS; while (at24c_i2c_write(priv, at24addr, buf, AT24XX_ADDRSIZE) < 0) { finfo("wait\n"); + if (!wait--) + { + return ERROR; + } usleep(1000); } @@ -410,6 +427,7 @@ static ssize_t at24c_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t FAR struct at24c_dev_s *priv = (FAR struct at24c_dev_s *)dev; size_t blocksleft; uint8_t buf[AT24XX_PAGESIZE + AT24XX_ADDRSIZE]; + uint16_t wait; #if CONFIG_AT24XX_MTD_BLOCKSIZE > AT24XX_PAGESIZE startblock *= (CONFIG_AT24XX_MTD_BLOCKSIZE / AT24XX_PAGESIZE); @@ -443,9 +461,14 @@ static ssize_t at24c_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t at24addr = (priv->addr | ((offset >> 8) & 0x07)); #endif + wait = CONFIG_AT24XX_TIMEOUT_MS; while (at24c_i2c_write(priv, at24addr, buf, AT24XX_ADDRSIZE) < 0) { finfo("wait\n"); + if (!wait--) + { + return ERROR; + } usleep(1000); } -- GitLab From abf5b011b5195835da0c0bd2a55c08626708f5ee Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 1 Nov 2016 15:12:30 -0600 Subject: [PATCH 287/734] Update README files --- README.txt | 2 +- configs/esp32-core/README.txt | 19 ++++++++++++++++++- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/README.txt b/README.txt index 9915949d2a..6203ab4cd1 100644 --- a/README.txt +++ b/README.txt @@ -987,7 +987,7 @@ Native Windows Build The windows native build logic initiated if CONFIG_WINDOWS_NATIVE=y is defined in the NuttX configuration file: - + This build: - Uses all Windows style paths diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index 1f2d6e2be5..933420fc00 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -23,6 +23,7 @@ Contents o Buttons and LEDs o SMP o Configurations + o Things to Do STATUS ====== @@ -116,7 +117,7 @@ SMP Open Issues: - 1. Currently all device interrupts are handled on the PRO CPU only. Critical + 1. Currently all device interrupts are handled on the PRO CPU only. Critical sections will attempt to disable interrupts but will now disable interrupts only on the current CPU (which may not be CPU0). Perhaps that should be a spinlock to prohibit execution of interrupts on CPU0 when other CPUs are in @@ -196,3 +197,19 @@ NOTES: SMP operation. NOTES: + +Things to Do +============ + + 1. There is no support for an interrupt stack yet. + 2. I did not implement the lazy co-processor save logic supported by Xtensa. That logic works like this: + + a. CPENABLE is set to zero on each context switch, disabling all co-processors. + b. If/when the task attempts to use the disabled co-processor, an exception occurs + c. The co-processor exception handler re-enables the co-processor. + + Instead, the NuttX logic saves and restores CPENABLE on each context switch. + + 3. Currently the Xtensa port copies register state save information from the stack into the TCB. A more efficient alternative would be to just save a pointer to a register state save area in the TCB. This would add some complexity to signal handling and also also the the up_initialstate(). But the performance improvement might be worth the effort. + + 4. See SMP-related issues above \ No newline at end of file -- GitLab From 8dd249440704444e285f4e5b440f8b291f2fff3b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 1 Nov 2016 15:13:09 -0600 Subject: [PATCH 288/734] Review of last PR: Fix return value (ERROR is not a value return value in this context). Fix some spacing. --- drivers/mtd/at24xx.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/at24xx.c b/drivers/mtd/at24xx.c index 7b4e38962e..936008a567 100644 --- a/drivers/mtd/at24xx.c +++ b/drivers/mtd/at24xx.c @@ -280,8 +280,9 @@ static int at24c_eraseall(FAR struct at24c_dev_s *priv) finfo("wait\n"); if (!wait--) { - return ERROR; + return -ETIMEDOUT; } + usleep(1000); } @@ -345,8 +346,9 @@ static ssize_t at24c_read_internal(FAR struct at24c_dev_s *priv, off_t offset, finfo("wait\n"); if (!wait--) { - return ERROR; + return -ETIMEDOUT; } + usleep(1000); } @@ -467,8 +469,9 @@ static ssize_t at24c_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t finfo("wait\n"); if (!wait--) { - return ERROR; + return -ETIMEDOUT; } + usleep(1000); } -- GitLab From 19f5a5f49de34dd62f22e5114d2b783d2ef9837b Mon Sep 17 00:00:00 2001 From: Ramtin Amin Date: Tue, 1 Nov 2016 16:14:18 -0600 Subject: [PATCH 289/734] MISOC LM32: configs/misoc board support for testing --- configs/misoc/Kconfig | 4 + configs/misoc/hello/Make.defs | 101 +++ configs/misoc/hello/defconfig | 609 ++++++++++++++++++ configs/misoc/hello/setenv.sh | 64 ++ configs/misoc/include/board.h | 100 +++ configs/misoc/include/generated/common.h | 49 ++ configs/misoc/include/generated/csr.h | 397 ++++++++++++ configs/misoc/include/generated/mem.h | 52 ++ .../misoc/include/generated/output_format.ld | 1 + configs/misoc/include/generated/regions.ld | 6 + configs/misoc/include/generated/sdram_phy.h | 144 +++++ configs/misoc/include/generated/variables.mak | 11 + configs/misoc/scripts/ld.script | 106 +++ configs/misoc/src/.gitignore | 2 + configs/misoc/src/Makefile | 42 ++ configs/misoc/src/lm32_boot.c | 68 ++ configs/misoc/src/misoc.h | 102 +++ 17 files changed, 1858 insertions(+) create mode 100644 configs/misoc/Kconfig create mode 100644 configs/misoc/hello/Make.defs create mode 100644 configs/misoc/hello/defconfig create mode 100644 configs/misoc/hello/setenv.sh create mode 100644 configs/misoc/include/board.h create mode 100644 configs/misoc/include/generated/common.h create mode 100644 configs/misoc/include/generated/csr.h create mode 100644 configs/misoc/include/generated/mem.h create mode 100644 configs/misoc/include/generated/output_format.ld create mode 100644 configs/misoc/include/generated/regions.ld create mode 100644 configs/misoc/include/generated/sdram_phy.h create mode 100644 configs/misoc/include/generated/variables.mak create mode 100644 configs/misoc/scripts/ld.script create mode 100644 configs/misoc/src/.gitignore create mode 100644 configs/misoc/src/Makefile create mode 100644 configs/misoc/src/lm32_boot.c create mode 100644 configs/misoc/src/misoc.h diff --git a/configs/misoc/Kconfig b/configs/misoc/Kconfig new file mode 100644 index 0000000000..f72f3c094c --- /dev/null +++ b/configs/misoc/Kconfig @@ -0,0 +1,4 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# diff --git a/configs/misoc/hello/Make.defs b/configs/misoc/hello/Make.defs new file mode 100644 index 0000000000..b6124b7759 --- /dev/null +++ b/configs/misoc/hello/Make.defs @@ -0,0 +1,101 @@ +############################################################################ +# configs/misoc/hello/Make.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# Ramtin Amin +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +CROSSDEV = lm32-elf- + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = $(ARCHINCLUDES) "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem "$(TOPDIR)/include" + ARCHXXINCLUDES = $(ARCHINCLUDES) -isystem "$(TOPDIR)/include/cxx" + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD_CUSTOM_NAME)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = diff --git a/configs/misoc/hello/defconfig b/configs/misoc/hello/defconfig new file mode 100644 index 0000000000..99c0c9ef2c --- /dev/null +++ b/configs/misoc/hello/defconfig @@ -0,0 +1,609 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_DEFAULT_SMALL=y +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +CONFIG_DEBUG_FEATURES=y + +# +# Debug SYSLOG Output Controls +# +# CONFIG_DEBUG_ERROR is not set +# CONFIG_DEBUG_ASSERTIONS is not set + +# +# Subsystem Debug Options +# +# CONFIG_DEBUG_BINFMT is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_DEBUG_GRAPHICS is not set +# CONFIG_DEBUG_LIB is not set +# CONFIG_DEBUG_MM is not set +# CONFIG_DEBUG_SCHED is not set + +# +# OS Function Debug Options +# +# CONFIG_DEBUG_IRQ is not set + +# +# Driver Debug Options +# +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_TIMER is not set +# CONFIG_ARCH_HAVE_STACKCHECK is not set +# CONFIG_ARCH_HAVE_HEAPCHECK is not set +CONFIG_DEBUG_SYMBOLS=y +# CONFIG_ARCH_HAVE_CUSTOMOPT is not set +CONFIG_DEBUG_NOOPT=y +# CONFIG_DEBUG_FULLOPT is not set + +# +# System Type +# +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +CONFIG_ARCH_MISOC=y +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="misoc" +CONFIG_ARCH_CHIP="lm32" +CONFIG_ARCH_CHIP_LM32=y +# CONFIG_ARCH_CHIP_MOR1K is not set + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +# CONFIG_ARCH_HAVE_IRQPRIO is not set +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +# CONFIG_ARCH_HAVE_VFORK is not set +# CONFIG_ARCH_HAVE_MMU is not set +# CONFIG_ARCH_HAVE_MPU is not set +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +# CONFIG_ARCH_HAVE_RESET is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +# CONFIG_ARCH_HAVE_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=800 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +# CONFIG_ARCH_HAVE_INTERRUPTSTACK is not set +# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x40000000 +CONFIG_RAM_SIZE=524288 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_CUSTOM=y + +# +# Custom Board Configuration +# +CONFIG_ARCH_BOARD_CUSTOM_NAME="misoc" +CONFIG_ARCH_BOARD_CUSTOM_DIR="/configs/misoc/" +CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y +# CONFIG_BOARD_CUSTOM_LEDS is not set +# CONFIG_BOARD_CUSTOM_BUTTONS is not set + +# +# Common Board Options +# + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +# CONFIG_LIB_BOARDCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_DISABLE_SIGNALS=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_ENVIRON=y + +# +# Clocks and Timers +# +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2011 +CONFIG_START_MONTH=6 +CONFIG_START_DAY=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_TIMERS=0 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="hello_main" +CONFIG_RR_INTERVAL=0 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=0 +CONFIG_MAX_TASKS=4 +# CONFIG_SCHED_HAVE_PARENT is not set +# CONFIG_SCHED_WAITPID is not set + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=4 +CONFIG_NFILE_STREAMS=4 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +# CONFIG_MODULE is not set + +# +# Work queue support +# + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=512 +CONFIG_USERMAIN_STACKSIZE=512 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +# CONFIG_ARCH_HAVE_I2CRESET is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +CONFIG_DEV_LOWCONSOLE=y +# CONFIG_SERIAL_REMOVABLE is not set +# CONFIG_SERIAL_CONSOLE is not set +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +# CONFIG_MCU_SERIAL is not set +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +# CONFIG_SYSLOG_SERIAL_CONSOLE is not set +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +# CONFIG_FS_READABLE is not set +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +CONFIG_MM_SMALL=y +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_BUILTIN is not set +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=0 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=0 +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_LIBC_LONG_LONG is not set +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +# CONFIG_ARCH_HAVE_TLS is not set +# CONFIG_LIBC_NETDB is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLO_PRIORITY=100 +CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +# CONFIG_EXAMPLES_NSH is not set +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +# CONFIG_NSH_LIBRARY is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +# CONFIG_READLINE_HAVE_EXTMATCH is not set +# CONFIG_SYSTEM_READLINE is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/misoc/hello/setenv.sh b/configs/misoc/hello/setenv.sh new file mode 100644 index 0000000000..c66c878239 --- /dev/null +++ b/configs/misoc/hello/setenv.sh @@ -0,0 +1,64 @@ +#!/bin/bash +# configs/amber/hello/setenv.sh +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# Ramtin Amin +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the WinAVR +# toolchain under windows. This is *not* the default install +# location so you will probably have to edit this. You will also have +# to edit this if you install the Linux AVR toolchain as well +#export TOOLCHAIN_BIN="/cygdrive/c/WinAVR/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +#export TOOLCHAIN_BIN="${WD}/../buildroot/build_avr/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +#export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/configs/misoc/include/board.h b/configs/misoc/include/board.h new file mode 100644 index 0000000000..8db2fcc7cf --- /dev/null +++ b/configs/misoc/include/board.h @@ -0,0 +1,100 @@ +/**************************************************************************** + * configs/misoc/include/board.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIGS_AMBER_INCLUDE_BOARD_H +#define __CONFIGS_AMBER_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ +/* Assume default CLKDIV8 fuse setting is overridden to CLKDIV1 */ + +#define BOARD_XTAL_FREQ 14745600 /* 14.7456MHz crystal */ +#define BOARD_CPU_CLOCK BOARD_XTAL_FREQ /* F_CPU = 14.7456MHz */ +#define BOARD_TOSCK_CLOCK 32768 /* TOSC = 32.768KHz */ + +/* LED definitions **********************************************************/ +/* The Amber Web Server has a reset switch and four LEDs. The LEDs indicate + * the status of power, programming state, Ethernet link status and reset + * status (Active). None are available for software use. + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 1 +#define LED_IRQSENABLED 2 +#define LED_STACKCREATED 3 +#define LED_INIRQ 4 +#define LED_SIGNAL 5 +#define LED_ASSERTION 6 +#define LED_PANIC 7 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_AMBER_INCLUDE_BOARD_H */ diff --git a/configs/misoc/include/generated/common.h b/configs/misoc/include/generated/common.h new file mode 100644 index 0000000000..38859deefa --- /dev/null +++ b/configs/misoc/include/generated/common.h @@ -0,0 +1,49 @@ +/**************************************************************************** + * configs/misoc/include/generated/common.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIGS_MISOC_INCLUDE_GENERATED_COMMON_H +#define __CONFIGS_MISOC_INCLUDE_GENERATED_COMMON_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef __ASSEMBLER__ +# define MMPTR(x) x +#else +# define MMPTR(x) (*((volatile unsigned int *)(x))) +#endif + +#endif /* __CONFIGS_MISOC_INCLUDE_GENERATED_COMMON_H */ diff --git a/configs/misoc/include/generated/csr.h b/configs/misoc/include/generated/csr.h new file mode 100644 index 0000000000..64bd1915a1 --- /dev/null +++ b/configs/misoc/include/generated/csr.h @@ -0,0 +1,397 @@ +/**************************************************************************** + * configs/misoc/include/generated/csr.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIGS_MISOC_INCLUDE_GENERATED_CSR_H +#define __CONFIGS_MISOC_INCLUDE_GENERATED_CSR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hw/common.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SDRAM */ + +#define CSR_SDRAM_BASE 0xe0004000 +#define CSR_SDRAM_DFII_CONTROL_ADDR 0xe0004000 +#define CSR_SDRAM_DFII_CONTROL_SIZE 1 + +#define CSR_SDRAM_DFII_PI0_COMMAND_ADDR 0xe0004004 +#define CSR_SDRAM_DFII_PI0_COMMAND_SIZE 1 + +#define CSR_SDRAM_DFII_PI0_COMMAND_ISSUE_ADDR 0xe0004008 +#define CSR_SDRAM_DFII_PI0_COMMAND_ISSUE_SIZE 1 + +#define CSR_SDRAM_DFII_PI0_ADDRESS_ADDR 0xe000400c +#define CSR_SDRAM_DFII_PI0_ADDRESS_SIZE 2 + +#define CSR_SDRAM_DFII_PI0_BADDRESS_ADDR 0xe0004014 +#define CSR_SDRAM_DFII_PI0_BADDRESS_SIZE 1 + +#define CSR_SDRAM_DFII_PI0_WRDATA_ADDR 0xe0004018 +#define CSR_SDRAM_DFII_PI0_WRDATA_SIZE 2 + +#define CSR_SDRAM_DFII_PI0_RDDATA_ADDR 0xe0004020 +#define CSR_SDRAM_DFII_PI0_RDDATA_SIZE 2 + +#define CSR_TIMER0_BASE 0xe0002000 +#define CSR_TIMER0_LOAD_ADDR 0xe0002000 +#define CSR_TIMER0_LOAD_SIZE 4 + +#define CSR_TIMER0_RELOAD_ADDR 0xe0002010 +#define CSR_TIMER0_RELOAD_SIZE 4 + +#define CSR_TIMER0_EN_ADDR 0xe0002020 +#define CSR_TIMER0_EN_SIZE 1 + +#define CSR_TIMER0_UPDATE_VALUE_ADDR 0xe0002024 +#define CSR_TIMER0_UPDATE_VALUE_SIZE 1 + +#define CSR_TIMER0_VALUE_ADDR 0xe0002028 +#define CSR_TIMER0_VALUE_SIZE 4 + +#define CSR_TIMER0_EV_STATUS_ADDR 0xe0002038 +#define CSR_TIMER0_EV_STATUS_SIZE 1 + +#define CSR_TIMER0_EV_PENDING_ADDR 0xe000203c +#define CSR_TIMER0_EV_PENDING_SIZE 1 + +#define CSR_TIMER0_EV_ENABLE_ADDR 0xe0002040 +#define CSR_TIMER0_EV_ENABLE_SIZE 1 + +#define CSR_UART_TXFULL_ADDR 0xe0001004 +#define CSR_UART_TXFULL_SIZE 1 + +#define CSR_UART_RXEMPTY_ADDR 0xe0001008 +#define CSR_UART_RXEMPTY_SIZE 1 + +#define CSR_UART_EV_STATUS_ADDR 0xe000100c +#define CSR_UART_EV_STATUS_SIZE 1 + +#define CSR_UART_EV_PENDING_ADDR 0xe0001010 +#define CSR_UART_EV_PENDING_SIZE 1 + +#define CSR_UART_EV_ENABLE_ADDR 0xe0001014 +#define CSR_UART_EV_ENABLE_SIZE 1 + +#define CSR_UART_PHY_BASE 0xe0000800 +#define CSR_UART_PHY_TUNING_WORD_ADDR 0xe0000800 +#define CSR_UART_PHY_TUNING_WORD_SIZE 4 + +/* Constants */ + +#define UART_INTERRUPT 0 +#define TIMER0_INTERRUPT 1 +#define SYSTEM_CLOCK_FREQUENCY 80000000 +#define L2_SIZE 8192 + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +static inline unsigned char sdram_dfii_control_read(void) +{ + unsigned char r = MMPTR(0xe0004000); + return r; +} + +static inline void sdram_dfii_control_write(unsigned char value) +{ + MMPTR(0xe0004000) = value; +} + +static inline unsigned char sdram_dfii_pi0_command_read(void) +{ + unsigned char r = MMPTR(0xe0004004); + return r; +} + +static inline void sdram_dfii_pi0_command_write(unsigned char value) +{ + MMPTR(0xe0004004) = value; +} + +static inline unsigned char sdram_dfii_pi0_command_issue_read(void) +{ + unsigned char r = MMPTR(0xe0004008); + return r; +} + +static inline void sdram_dfii_pi0_command_issue_write(unsigned char value) +{ + MMPTR(0xe0004008) = value; +} + +static inline unsigned short int sdram_dfii_pi0_address_read(void) +{ + unsigned short int r = MMPTR(0xe000400c); + r <<= 8; + r |= MMPTR(0xe0004010); + return r; +} + +static inline void sdram_dfii_pi0_address_write(unsigned short int value) +{ + MMPTR(0xe000400c) = value >> 8; + MMPTR(0xe0004010) = value; +} + +static inline unsigned char sdram_dfii_pi0_baddress_read(void) +{ + unsigned char r = MMPTR(0xe0004014); + return r; +} + +static inline void sdram_dfii_pi0_baddress_write(unsigned char value) +{ + MMPTR(0xe0004014) = value; +} + +static inline unsigned short int sdram_dfii_pi0_wrdata_read(void) +{ + unsigned short int r = MMPTR(0xe0004018); + r <<= 8; + r |= MMPTR(0xe000401c); + return r; +} + +static inline void sdram_dfii_pi0_wrdata_write(unsigned short int value) +{ + MMPTR(0xe0004018) = value >> 8; + MMPTR(0xe000401c) = value; +} + +static inline unsigned short int sdram_dfii_pi0_rddata_read(void) +{ + unsigned short int r = MMPTR(0xe0004020); + r <<= 8; + r |= MMPTR(0xe0004024); + return r; +} + +/* Timer0 */ + +static inline unsigned int timer0_load_read(void) +{ + unsigned int r = MMPTR(0xe0002000); + r <<= 8; + r |= MMPTR(0xe0002004); + r <<= 8; + r |= MMPTR(0xe0002008); + r <<= 8; + r |= MMPTR(0xe000200c); + return r; +} + +static inline void timer0_load_write(unsigned int value) +{ + MMPTR(0xe0002000) = value >> 24; + MMPTR(0xe0002004) = value >> 16; + MMPTR(0xe0002008) = value >> 8; + MMPTR(0xe000200c) = value; +} + +static inline unsigned int timer0_reload_read(void) +{ + unsigned int r = MMPTR(0xe0002010); + r <<= 8; + r |= MMPTR(0xe0002014); + r <<= 8; + r |= MMPTR(0xe0002018); + r <<= 8; + r |= MMPTR(0xe000201c); + return r; +} + +static inline void timer0_reload_write(unsigned int value) +{ + MMPTR(0xe0002010) = value >> 24; + MMPTR(0xe0002014) = value >> 16; + MMPTR(0xe0002018) = value >> 8; + MMPTR(0xe000201c) = value; +} + +static inline unsigned char timer0_en_read(void) +{ + unsigned char r = MMPTR(0xe0002020); + return r; +} + +static inline void timer0_en_write(unsigned char value) +{ + MMPTR(0xe0002020) = value; +} + +static inline unsigned char timer0_update_value_read(void) +{ + unsigned char r = MMPTR(0xe0002024); + return r; +} + +static inline void timer0_update_value_write(unsigned char value) +{ + MMPTR(0xe0002024) = value; +} + +static inline unsigned int timer0_value_read(void) +{ + unsigned int r = MMPTR(0xe0002028); + r <<= 8; + r |= MMPTR(0xe000202c); + r <<= 8; + r |= MMPTR(0xe0002030); + r <<= 8; + r |= MMPTR(0xe0002034); + return r; +} + +static inline unsigned char timer0_ev_status_read(void) +{ + unsigned char r = MMPTR(0xe0002038); + return r; +} + +static inline void timer0_ev_status_write(unsigned char value) +{ + MMPTR(0xe0002038) = value; +} + +static inline unsigned char timer0_ev_pending_read(void) +{ + unsigned char r = MMPTR(0xe000203c); + return r; +} + +static inline void timer0_ev_pending_write(unsigned char value) +{ + MMPTR(0xe000203c) = value; +} + +static inline unsigned char timer0_ev_enable_read(void) +{ + unsigned char r = MMPTR(0xe0002040); + return r; +} + +static inline void timer0_ev_enable_write(unsigned char value) +{ + MMPTR(0xe0002040) = value; +} + +/* UART */ + +static inline unsigned char uart_rxtx_read(void) +{ + unsigned char r = MMPTR(0xe0001000); + return r; +} + +static inline void uart_rxtx_write(unsigned char value) +{ + MMPTR(0xe0001000) = value; +} + +static inline unsigned char uart_txfull_read(void) +{ + unsigned char r = MMPTR(0xe0001004); + return r; +} + +static inline unsigned char uart_rxempty_read(void) +{ + unsigned char r = MMPTR(0xe0001008); + return r; +} + +static inline unsigned char uart_ev_status_read(void) +{ + unsigned char r = MMPTR(0xe000100c); + return r; +} + +static inline void uart_ev_status_write(unsigned char value) +{ + MMPTR(0xe000100c) = value; +} + +static inline unsigned char uart_ev_pending_read(void) +{ + unsigned char r = MMPTR(0xe0001010); + return r; +} + +static inline void uart_ev_pending_write(unsigned char value) +{ + MMPTR(0xe0001010) = value; +} + +static inline unsigned char uart_ev_enable_read(void) +{ + unsigned char r = MMPTR(0xe0001014); + return r; +} + +static inline void uart_ev_enable_write(unsigned char value) +{ + MMPTR(0xe0001014) = value; +} + +/* uart_phy */ + +static inline unsigned int uart_phy_tuning_word_read(void) +{ + unsigned int r = MMPTR(0xe0000800); + r <<= 8; + r |= MMPTR(0xe0000804); + r <<= 8; + r |= MMPTR(0xe0000808); + r <<= 8; + r |= MMPTR(0xe000080c); + return r; +} + +static inline void uart_phy_tuning_word_write(unsigned int value) +{ + MMPTR(0xe0000800) = value >> 24; + MMPTR(0xe0000804) = value >> 16; + MMPTR(0xe0000808) = value >> 8; + MMPTR(0xe000080c) = value; +} + +#endif /* __CONFIGS_MISOC_INCLUDE_GENERATED_CSR_H */ diff --git a/configs/misoc/include/generated/mem.h b/configs/misoc/include/generated/mem.h new file mode 100644 index 0000000000..dd6b512e91 --- /dev/null +++ b/configs/misoc/include/generated/mem.h @@ -0,0 +1,52 @@ +/**************************************************************************** + * configs/misoc/include/generated/mem.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIGS_MISOC_INCLUDE_GENERATED_MEM_H +#define __CONFIGS_MISOC_INCLUDE_GENERATED_MEM_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ROM_BASE 0x00000000 +#define ROM_SIZE 0x00008000 + +#define SRAM_BASE 0x10000000 +#define SRAM_SIZE 0x00001000 + +#define MAIN_RAM_BASE 0x40000000 +#define MAIN_RAM_SIZE 0x00800000 + +#endif /* __CONFIGS_MISOC_INCLUDE_GENERATED_MEM_H / diff --git a/configs/misoc/include/generated/output_format.ld b/configs/misoc/include/generated/output_format.ld new file mode 100644 index 0000000000..72acc74d0f --- /dev/null +++ b/configs/misoc/include/generated/output_format.ld @@ -0,0 +1 @@ +OUTPUT_FORMAT("elf32-lm32") diff --git a/configs/misoc/include/generated/regions.ld b/configs/misoc/include/generated/regions.ld new file mode 100644 index 0000000000..bd7502729b --- /dev/null +++ b/configs/misoc/include/generated/regions.ld @@ -0,0 +1,6 @@ +MEMORY +{ + rom : ORIGIN = 0x00000000, LENGTH = 0x00008000 + sram : ORIGIN = 0x10000000, LENGTH = 0x00001000 + main_ram : ORIGIN = 0x40000000, LENGTH = 0x00800000 +} diff --git a/configs/misoc/include/generated/sdram_phy.h b/configs/misoc/include/generated/sdram_phy.h new file mode 100644 index 0000000000..2161b7d5b9 --- /dev/null +++ b/configs/misoc/include/generated/sdram_phy.h @@ -0,0 +1,144 @@ +/**************************************************************************** + * configs/misoc/include/generated/common.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIGS_MISOC_INCLUDE_GENERATED_SDRAM_PHY_H +#define __CONFIGS_MISOC_INCLUDE_GENERATED_SDRAM_PHY_H + +/**************************************************************************** + * Included Filese + ****************************************************************************/ + +#include "hw/common.h" +#include "hw/flags.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define DFII_NPHASES 1 + +#define sdram_dfii_pird_address_write(X) sdram_dfii_pi0_address_write(X) +#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi0_address_write(X) + +#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi0_baddress_write(X) +#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi0_baddress_write(X) + +#define command_prd(X) command_p0(X) +#define command_pwr(X) command_p0(X) + +#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +const unsigned int sdram_dfii_pix_wrdata_addr[1] = +{ + CSR_SDRAM_DFII_PI0_WRDATA_ADDR +}; + +const unsigned int sdram_dfii_pix_rddata_addr[1] = +{ + CSR_SDRAM_DFII_PI0_RDDATA_ADDR +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void cdelay(int i); + +static void command_p0(int cmd) +{ + sdram_dfii_pi0_command_write(cmd); + sdram_dfii_pi0_command_issue_write(1); +} + +static void init_sequence(void) +{ + /* Bring CKE high */ + + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + sdram_dfii_control_write(DFII_CONTROL_CKE | DFII_CONTROL_ODT | + DFII_CONTROL_RESET_N); + cdelay(20000); + + /* Precharge All */ + + sdram_dfii_pi0_address_write(0x400); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS | DFII_COMMAND_WE | DFII_COMMAND_CS); + + /* Load Mode Register / Reset DLL, CL=2, BL=1 */ + + sdram_dfii_pi0_address_write(0x120); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS | DFII_COMMAND_CAS | DFII_COMMAND_WE | + DFII_COMMAND_CS); + cdelay(200); + + /* Precharge All */ + + sdram_dfii_pi0_address_write(0x400); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS | DFII_COMMAND_WE | DFII_COMMAND_CS); + + /* Auto Refresh */ + + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS | DFII_COMMAND_CAS | DFII_COMMAND_CS); + cdelay(4); + + /* Auto Refresh */ + + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS | DFII_COMMAND_CAS | DFII_COMMAND_CS); + cdelay(4); + + /* Load Mode Register / CL=2, BL=1 */ + + sdram_dfii_pi0_address_write(0x20); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS | DFII_COMMAND_CAS | DFII_COMMAND_WE | + DFII_COMMAND_CS); + cdelay(200); +} + +#endif /* __CONFIGS_MISOC_INCLUDE_GENERATED_SDRAM_PHY_H diff --git a/configs/misoc/include/generated/variables.mak b/configs/misoc/include/generated/variables.mak new file mode 100644 index 0000000000..a5e6478ad4 --- /dev/null +++ b/configs/misoc/include/generated/variables.mak @@ -0,0 +1,11 @@ +TRIPLE=lm32-elf +CPU=lm32 +CPUFLAGS=-mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled +CPUENDIANNESS=big +CLANG=0 +SOC_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc +BUILDINC_DIRECTORY=/home/lenovo/fpga/litex/litex/boards/targets/soc_basesoc_papilio_pro/software/include +LIBBASE_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/libbase +LIBCOMPILER_RT_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/libcompiler_rt +LIBNET_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/libnet +BIOS_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/bios diff --git a/configs/misoc/scripts/ld.script b/configs/misoc/scripts/ld.script new file mode 100644 index 0000000000..806aa57928 --- /dev/null +++ b/configs/misoc/scripts/ld.script @@ -0,0 +1,106 @@ +/**************************************************************************** + * configs/misoc/hello/script/ld.script + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +OUTPUT_FORMAT("elf32-lm32") +ENTRY(_stext) + +MEMORY +{ + rom : ORIGIN = 0x00000000, LENGTH = 0x00008000 + sram : ORIGIN = 0x10000000, LENGTH = 0x00004000 + main_ram : ORIGIN = 0x40000000, LENGTH = 0x00080000 +} + +/* +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x80002000, LENGTH = 256K - 8K + intram (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 32K + userpage : ORIGIN = 0x80800000, LENGTH = 512 + factorypage : ORIGIN = 0x80800200, LENGTH = 512 +} +*/ + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > main_ram + + _eronly = ABSOLUTE(.); /* See below */ + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > main_ram + + .bss : { /* BSS */ + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > main_ram + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} + +PROVIDE(_fstack = ORIGIN(main_ram) + LENGTH(main_ram) - 4); diff --git a/configs/misoc/src/.gitignore b/configs/misoc/src/.gitignore new file mode 100644 index 0000000000..726d936e1e --- /dev/null +++ b/configs/misoc/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/configs/misoc/src/Makefile b/configs/misoc/src/Makefile new file mode 100644 index 0000000000..b52ee91e5c --- /dev/null +++ b/configs/misoc/src/Makefile @@ -0,0 +1,42 @@ +############################################################################ +# configs/misoc/src/Makefile +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# Ramtin Amin +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = atmega_boot.c + +include $(TOPDIR)/configs/Board.mk diff --git a/configs/misoc/src/lm32_boot.c b/configs/misoc/src/lm32_boot.c new file mode 100644 index 0000000000..8d23d5dc63 --- /dev/null +++ b/configs/misoc/src/lm32_boot.c @@ -0,0 +1,68 @@ +/************************************************************************************ + * configs/misoc/src/lm32_boot.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: lm32_board_initialize + * + * Description: + * All LM32 architectures must provide the following entry point. This entry + * point is called early in the initialization -- after all memory has been + * configured and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void lm32_board_initialize(void) +{ + /* Configure SSP chip selects if 1) at least one SSP is enabled, and 2) the weak + * function atmega_spidev_initialize() has been brought into the link. + */ + + /* Configure on-board LEDs if LED support has been selected. */ +} diff --git a/configs/misoc/src/misoc.h b/configs/misoc/src/misoc.h new file mode 100644 index 0000000000..24fe09a452 --- /dev/null +++ b/configs/misoc/src/misoc.h @@ -0,0 +1,102 @@ +/**************************************************************************** + * configs/misoc/src/misoc.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIGS_MISOC_SRC_MISOC_H +#define __CONFIGS_MISOC_SRC_MISOC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Name: lm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Amber Web Server. + * + ************************************************************************************/ + +#if defined(CONFIG_AVR_SPI1) || defined(CONFIG_AVR_SPI2) +void weak_function lm32_spidev_initialize(void); +#endif + +/************************************************************************************ + * Name: lm32_led_initialize + * + * Description: + * Configure on-board LEDs if LED support has been selected. + * + ************************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void lm32_led_initialize(void); +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_MISOC_SRC_MISOC_H */ -- GitLab From d870f4ab29529291d2ccfbf95bddb0458bc12350 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Tue, 1 Nov 2016 22:27:35 +0000 Subject: [PATCH 290/734] I think, that Size is (highest address+1 - Base address) Base address has been removed and if address+count >= size we are outside of the Flash --- arch/arm/src/stm32/stm32_flash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/stm32/stm32_flash.c b/arch/arm/src/stm32/stm32_flash.c index 73f1419506..56aa1f75ed 100644 --- a/arch/arm/src/stm32/stm32_flash.c +++ b/arch/arm/src/stm32/stm32_flash.c @@ -313,7 +313,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) addr -= STM32_FLASH_BASE; } - if ((addr+count) > STM32_FLASH_SIZE) + if ((addr+count) >= STM32_FLASH_SIZE) { return -EFAULT; } -- GitLab From 14e06a3ce3316379b52bb0a8f20e3137a3af4536 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 2 Nov 2016 07:37:56 -0600 Subject: [PATCH 291/734] libc/pthread: Rename long files so that they are more readable --- libc/pthread/Make.defs | 24 +++++++++---------- ...d_attrdestroy.c => pthread_attr_destroy.c} | 2 +- ...taffinity.c => pthread_attr_getaffinity.c} | 2 +- ...sched.c => pthread_attr_getinheritsched.c} | 2 +- ...edparam.c => pthread_attr_getschedparam.c} | 2 +- ...policy.c => pthread_attr_getschedpolicy.c} | 2 +- ...tacksize.c => pthread_attr_getstacksize.c} | 2 +- ...pthread_attrinit.c => pthread_attr_init.c} | 2 +- ...taffinity.c => pthread_attr_setaffinity.c} | 2 +- ...sched.c => pthread_attr_setinheritsched.c} | 2 +- ...edparam.c => pthread_attr_setschedparam.c} | 2 +- ...policy.c => pthread_attr_setschedpolicy.c} | 2 +- ...tacksize.c => pthread_attr_setstacksize.c} | 2 +- ...estroy.c => pthread_barrierattr_destroy.c} | 2 +- ...red.c => pthread_barrierattr_getpshared.c} | 2 +- ...rattrinit.c => pthread_barrierattr_init.c} | 2 +- ...red.c => pthread_barrierattr_setpshared.c} | 2 +- ...trdestroy.c => pthread_condattr_destroy.c} | 2 +- ...condattrinit.c => pthread_condattr_init.c} | 2 +- ...rdestroy.c => pthread_mutexattr_destroy.c} | 2 +- ...hared.c => pthread_mutexattr_getpshared.c} | 2 +- ...rgettype.c => pthread_mutexattr_gettype.c} | 3 ++- ...texattrinit.c => pthread_mutexattr_init.c} | 2 +- ...hared.c => pthread_mutexattr_setpshared.c} | 2 +- ...rsettype.c => pthread_mutexattr_settype.c} | 2 +- 25 files changed, 37 insertions(+), 36 deletions(-) rename libc/pthread/{pthread_attrdestroy.c => pthread_attr_destroy.c} (98%) rename libc/pthread/{pthread_attrgetaffinity.c => pthread_attr_getaffinity.c} (98%) rename libc/pthread/{pthread_attrgetinheritsched.c => pthread_attr_getinheritsched.c} (98%) rename libc/pthread/{pthread_attrgetschedparam.c => pthread_attr_getschedparam.c} (98%) rename libc/pthread/{pthread_attrgetschedpolicy.c => pthread_attr_getschedpolicy.c} (98%) rename libc/pthread/{pthread_attrgetstacksize.c => pthread_attr_getstacksize.c} (98%) rename libc/pthread/{pthread_attrinit.c => pthread_attr_init.c} (99%) rename libc/pthread/{pthread_attrsetaffinity.c => pthread_attr_setaffinity.c} (98%) rename libc/pthread/{pthread_attrsetinheritsched.c => pthread_attr_setinheritsched.c} (98%) rename libc/pthread/{pthread_attrsetschedparam.c => pthread_attr_setschedparam.c} (98%) rename libc/pthread/{pthread_attrsetschedpolicy.c => pthread_attr_setschedpolicy.c} (98%) rename libc/pthread/{pthread_attrsetstacksize.c => pthread_attr_setstacksize.c} (98%) rename libc/pthread/{pthread_barrierattrdestroy.c => pthread_barrierattr_destroy.c} (98%) rename libc/pthread/{pthread_barrierattrgetpshared.c => pthread_barrierattr_getpshared.c} (98%) rename libc/pthread/{pthread_barrierattrinit.c => pthread_barrierattr_init.c} (98%) rename libc/pthread/{pthread_barrierattrsetpshared.c => pthread_barrierattr_setpshared.c} (98%) rename libc/pthread/{pthread_condattrdestroy.c => pthread_condattr_destroy.c} (98%) rename libc/pthread/{pthread_condattrinit.c => pthread_condattr_init.c} (98%) rename libc/pthread/{pthread_mutexattrdestroy.c => pthread_mutexattr_destroy.c} (98%) rename libc/pthread/{pthread_mutexattrgetpshared.c => pthread_mutexattr_getpshared.c} (98%) rename libc/pthread/{pthread_mutexattrgettype.c => pthread_mutexattr_gettype.c} (98%) rename libc/pthread/{pthread_mutexattrinit.c => pthread_mutexattr_init.c} (98%) rename libc/pthread/{pthread_mutexattrsetpshared.c => pthread_mutexattr_setpshared.c} (98%) rename libc/pthread/{pthread_mutexattrsettype.c => pthread_mutexattr_settype.c} (98%) diff --git a/libc/pthread/Make.defs b/libc/pthread/Make.defs index 44a2d8b2d6..0d783c07fd 100644 --- a/libc/pthread/Make.defs +++ b/libc/pthread/Make.defs @@ -35,23 +35,23 @@ # Add the pthread C files to the build -CSRCS += pthread_attrinit.c pthread_attrdestroy.c \ - pthread_attrsetschedpolicy.c pthread_attrgetschedpolicy.c \ - pthread_attrsetinheritsched.c pthread_attrgetinheritsched.c \ - pthread_attrsetstacksize.c pthread_attrgetstacksize.c \ - pthread_attrsetschedparam.c pthread_attrgetschedparam.c \ - pthread_barrierattrinit.c pthread_barrierattrdestroy.c \ - pthread_barrierattrgetpshared.c pthread_barrierattrsetpshared.c \ - pthread_condattrinit.c pthread_condattrdestroy.c \ - pthread_mutexattrinit.c pthread_mutexattrdestroy.c \ - pthread_mutexattrgetpshared.c pthread_mutexattrsetpshared.c +CSRCS += pthread_attr_init.c pthread_attr_destroy.c \ + pthread_attr_setschedpolicy.c pthread_attr_getschedpolicy.c \ + pthread_attr_setinheritsched.c pthread_attr_getinheritsched.c \ + pthread_attr_setstacksize.c pthread_attr_getstacksize.c \ + pthread_attr_setschedparam.c pthread_attr_getschedparam.c \ + pthread_barrierattr_init.c pthread_barrierattr_destroy.c \ + pthread_barrierattr_getpshared.c pthread_barrierattr_setpshared.c \ + pthread_condattr_init.c pthread_condattr_destroy.c \ + pthread_mutexattr_init.c pthread_mutexattr_destroy.c \ + pthread_mutexattr_getpshared.c pthread_mutexattr_setpshared.c ifeq ($(CONFIG_SMP),y) -CSRCS += pthread_attrgetaffinity.c pthread_attrsetaffinity.c +CSRCS += pthread_attr_getaffinity.c pthread_attr_setaffinity.c endif ifeq ($(CONFIG_MUTEX_TYPES),y) -CSRCS += pthread_mutexattrsettype.c pthread_mutexattrgettype.c +CSRCS += pthread_mutexattr_settype.c pthread_mutexattr_gettype.c endif ifeq ($(CONFIG_BUILD_PROTECTED),y) diff --git a/libc/pthread/pthread_attrdestroy.c b/libc/pthread/pthread_attr_destroy.c similarity index 98% rename from libc/pthread/pthread_attrdestroy.c rename to libc/pthread/pthread_attr_destroy.c index 7dc431f808..084946cf72 100644 --- a/libc/pthread/pthread_attrdestroy.c +++ b/libc/pthread/pthread_attr_destroy.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/pthread/pthread_attrdestroy.c + * libc/pthread/pthread_attr_destroy.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/pthread/pthread_attrgetaffinity.c b/libc/pthread/pthread_attr_getaffinity.c similarity index 98% rename from libc/pthread/pthread_attrgetaffinity.c rename to libc/pthread/pthread_attr_getaffinity.c index a08f18cb00..706f059ec5 100644 --- a/libc/pthread/pthread_attrgetaffinity.c +++ b/libc/pthread/pthread_attr_getaffinity.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/pthread/pthread_attrgetaffinity.c + * libc/pthread/pthread_attr_getaffinity.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/pthread/pthread_attrgetinheritsched.c b/libc/pthread/pthread_attr_getinheritsched.c similarity index 98% rename from libc/pthread/pthread_attrgetinheritsched.c rename to libc/pthread/pthread_attr_getinheritsched.c index 0f6b42a879..0760c5e265 100644 --- a/libc/pthread/pthread_attrgetinheritsched.c +++ b/libc/pthread/pthread_attr_getinheritsched.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/pthread/pthread_attrgetinheritsched.c + * libc/pthread/pthread_attr_getinheritsched.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/pthread/pthread_attrgetschedparam.c b/libc/pthread/pthread_attr_getschedparam.c similarity index 98% rename from libc/pthread/pthread_attrgetschedparam.c rename to libc/pthread/pthread_attr_getschedparam.c index beea2a595b..d3280ffde3 100644 --- a/libc/pthread/pthread_attrgetschedparam.c +++ b/libc/pthread/pthread_attr_getschedparam.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/pthread/pthread_attrgetschedparam.c + * libc/pthread/pthread_attr_getschedparam.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/pthread/pthread_attrgetschedpolicy.c b/libc/pthread/pthread_attr_getschedpolicy.c similarity index 98% rename from libc/pthread/pthread_attrgetschedpolicy.c rename to libc/pthread/pthread_attr_getschedpolicy.c index 601b3cebea..f4f624f4f0 100644 --- a/libc/pthread/pthread_attrgetschedpolicy.c +++ b/libc/pthread/pthread_attr_getschedpolicy.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/pthread/pthread_attrgetschedpolicy.c + * libc/pthread/pthread_attr_getschedpolicy.c * * Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/pthread/pthread_attrgetstacksize.c b/libc/pthread/pthread_attr_getstacksize.c similarity index 98% rename from libc/pthread/pthread_attrgetstacksize.c rename to libc/pthread/pthread_attr_getstacksize.c index 130bed7fb6..15de1b38f9 100644 --- a/libc/pthread/pthread_attrgetstacksize.c +++ b/libc/pthread/pthread_attr_getstacksize.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/pthread/pthread_attrgetstacksize.c + * libc/pthread/pthread_attr_getstacksize.c * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/pthread/pthread_attrinit.c b/libc/pthread/pthread_attr_init.c similarity index 99% rename from libc/pthread/pthread_attrinit.c rename to libc/pthread/pthread_attr_init.c index 1d303a05f0..b6c7c39ed6 100644 --- a/libc/pthread/pthread_attrinit.c +++ b/libc/pthread/pthread_attr_init.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/pthread/pthread_attrinit.c + * libc/pthread/pthread_attr_init.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/pthread/pthread_attrsetaffinity.c b/libc/pthread/pthread_attr_setaffinity.c similarity index 98% rename from libc/pthread/pthread_attrsetaffinity.c rename to libc/pthread/pthread_attr_setaffinity.c index c8e7c3607d..6705e87aa0 100644 --- a/libc/pthread/pthread_attrsetaffinity.c +++ b/libc/pthread/pthread_attr_setaffinity.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/pthread/pthread_attrsetaffinity.c + * libc/pthread/pthread_attr_setaffinity.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/pthread/pthread_attrsetinheritsched.c b/libc/pthread/pthread_attr_setinheritsched.c similarity index 98% rename from libc/pthread/pthread_attrsetinheritsched.c rename to libc/pthread/pthread_attr_setinheritsched.c index 89d29d07bb..c61be6f4f6 100644 --- a/libc/pthread/pthread_attrsetinheritsched.c +++ b/libc/pthread/pthread_attr_setinheritsched.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/pthread/pthread_attrsetinheritsched.c + * libc/pthread/pthread_attr_setinheritsched.c * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/pthread/pthread_attrsetschedparam.c b/libc/pthread/pthread_attr_setschedparam.c similarity index 98% rename from libc/pthread/pthread_attrsetschedparam.c rename to libc/pthread/pthread_attr_setschedparam.c index 602f76eafa..b37d3aad27 100644 --- a/libc/pthread/pthread_attrsetschedparam.c +++ b/libc/pthread/pthread_attr_setschedparam.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/pthread/pthread_attrsetschedparam.c + * libc/pthread/pthread_attr_setschedparam.c * * Copyright (C) 2007-2009, 2011, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/pthread/pthread_attrsetschedpolicy.c b/libc/pthread/pthread_attr_setschedpolicy.c similarity index 98% rename from libc/pthread/pthread_attrsetschedpolicy.c rename to libc/pthread/pthread_attr_setschedpolicy.c index 2aa2686157..75a58e105b 100644 --- a/libc/pthread/pthread_attrsetschedpolicy.c +++ b/libc/pthread/pthread_attr_setschedpolicy.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/pthread/pthread_attrsetschedpolicy.c + * libc/pthread/pthread_attr_setschedpolicy.c * * Copyright (C) 2007-2009, 2011, 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/pthread/pthread_attrsetstacksize.c b/libc/pthread/pthread_attr_setstacksize.c similarity index 98% rename from libc/pthread/pthread_attrsetstacksize.c rename to libc/pthread/pthread_attr_setstacksize.c index 3ed309981c..0501f76aa6 100644 --- a/libc/pthread/pthread_attrsetstacksize.c +++ b/libc/pthread/pthread_attr_setstacksize.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/pthread/pthread_attrsetstacksize.c + * libc/pthread/pthread_attr_setstacksize.c * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/pthread/pthread_barrierattrdestroy.c b/libc/pthread/pthread_barrierattr_destroy.c similarity index 98% rename from libc/pthread/pthread_barrierattrdestroy.c rename to libc/pthread/pthread_barrierattr_destroy.c index 98342e28c1..7ab23b7b84 100644 --- a/libc/pthread/pthread_barrierattrdestroy.c +++ b/libc/pthread/pthread_barrierattr_destroy.c @@ -1,5 +1,5 @@ /******************************************************************************** - * libc/pthread/pthread_barrierattrdestroy.c + * libc/pthread/pthread_barrierattr_destroy.c * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/pthread/pthread_barrierattrgetpshared.c b/libc/pthread/pthread_barrierattr_getpshared.c similarity index 98% rename from libc/pthread/pthread_barrierattrgetpshared.c rename to libc/pthread/pthread_barrierattr_getpshared.c index ce186f230a..d74d54dcbf 100644 --- a/libc/pthread/pthread_barrierattrgetpshared.c +++ b/libc/pthread/pthread_barrierattr_getpshared.c @@ -1,5 +1,5 @@ /******************************************************************************** - * libc/pthread/pthread_barrierattrgetpshared.c + * libc/pthread/pthread_barrierattr_getpshared.c * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/pthread/pthread_barrierattrinit.c b/libc/pthread/pthread_barrierattr_init.c similarity index 98% rename from libc/pthread/pthread_barrierattrinit.c rename to libc/pthread/pthread_barrierattr_init.c index 16c31922d7..9b3f577552 100644 --- a/libc/pthread/pthread_barrierattrinit.c +++ b/libc/pthread/pthread_barrierattr_init.c @@ -1,5 +1,5 @@ /******************************************************************************** - * libc/pthread/pthread_barrierattrinit.c + * libc/pthread/pthread_barrierattr_init.c * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/pthread/pthread_barrierattrsetpshared.c b/libc/pthread/pthread_barrierattr_setpshared.c similarity index 98% rename from libc/pthread/pthread_barrierattrsetpshared.c rename to libc/pthread/pthread_barrierattr_setpshared.c index 6839511df5..1736a4e430 100644 --- a/libc/pthread/pthread_barrierattrsetpshared.c +++ b/libc/pthread/pthread_barrierattr_setpshared.c @@ -1,5 +1,5 @@ /******************************************************************************** - * libc/pthread/pthread_barrierattrsetpshared.c + * libc/pthread/pthread_barrierattr_setpshared.c * * Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/pthread/pthread_condattrdestroy.c b/libc/pthread/pthread_condattr_destroy.c similarity index 98% rename from libc/pthread/pthread_condattrdestroy.c rename to libc/pthread/pthread_condattr_destroy.c index d538891f82..5833de44cf 100644 --- a/libc/pthread/pthread_condattrdestroy.c +++ b/libc/pthread/pthread_condattr_destroy.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/pthread/pthread_condattrdestroy.c + * libc/pthread/pthread_condattr_destroy.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/pthread/pthread_condattrinit.c b/libc/pthread/pthread_condattr_init.c similarity index 98% rename from libc/pthread/pthread_condattrinit.c rename to libc/pthread/pthread_condattr_init.c index 64d2d0ac25..7f5602ce76 100644 --- a/libc/pthread/pthread_condattrinit.c +++ b/libc/pthread/pthread_condattr_init.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/pthread/pthread_condattrinit.c + * libc/pthread/pthread_condattr_init.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/pthread/pthread_mutexattrdestroy.c b/libc/pthread/pthread_mutexattr_destroy.c similarity index 98% rename from libc/pthread/pthread_mutexattrdestroy.c rename to libc/pthread/pthread_mutexattr_destroy.c index c20a67bdf7..a5ada87790 100644 --- a/libc/pthread/pthread_mutexattrdestroy.c +++ b/libc/pthread/pthread_mutexattr_destroy.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/pthread/pthread_mutexattrdestroy.c + * libc/pthread/pthread_mutexattr_destroy.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/pthread/pthread_mutexattrgetpshared.c b/libc/pthread/pthread_mutexattr_getpshared.c similarity index 98% rename from libc/pthread/pthread_mutexattrgetpshared.c rename to libc/pthread/pthread_mutexattr_getpshared.c index b8f0b77ec4..51e515cbbb 100644 --- a/libc/pthread/pthread_mutexattrgetpshared.c +++ b/libc/pthread/pthread_mutexattr_getpshared.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/pthread/pthread_mutexattrgetpshared.c + * libc/pthread/pthread_mutexattr_getpshared.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/pthread/pthread_mutexattrgettype.c b/libc/pthread/pthread_mutexattr_gettype.c similarity index 98% rename from libc/pthread/pthread_mutexattrgettype.c rename to libc/pthread/pthread_mutexattr_gettype.c index cc553c8350..c9703f5c01 100644 --- a/libc/pthread/pthread_mutexattrgettype.c +++ b/libc/pthread/pthread_mutexattr_gettype.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/pthread/pthread_mutexattrgettype.c + * libc/pthread/pthread_mutexattr_gettype.c * * Copyright (C) 2008, 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -72,6 +72,7 @@ int pthread_mutexattr_gettype(const pthread_mutexattr_t *attr, int *type) *type = attr->type; return 0; } + return EINVAL; } diff --git a/libc/pthread/pthread_mutexattrinit.c b/libc/pthread/pthread_mutexattr_init.c similarity index 98% rename from libc/pthread/pthread_mutexattrinit.c rename to libc/pthread/pthread_mutexattr_init.c index 95f5ba8ab8..01c3bb867d 100644 --- a/libc/pthread/pthread_mutexattrinit.c +++ b/libc/pthread/pthread_mutexattr_init.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/pthread/pthread_mutexattrinit.c + * libc/pthread/pthread_mutexattr_init.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/pthread/pthread_mutexattrsetpshared.c b/libc/pthread/pthread_mutexattr_setpshared.c similarity index 98% rename from libc/pthread/pthread_mutexattrsetpshared.c rename to libc/pthread/pthread_mutexattr_setpshared.c index 3418521ee8..22b915c4f0 100644 --- a/libc/pthread/pthread_mutexattrsetpshared.c +++ b/libc/pthread/pthread_mutexattr_setpshared.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/pthread/pthread_mutexattrsetpshared.c + * libc/pthread/pthread_mutexattr_setpshared.c * * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/libc/pthread/pthread_mutexattrsettype.c b/libc/pthread/pthread_mutexattr_settype.c similarity index 98% rename from libc/pthread/pthread_mutexattrsettype.c rename to libc/pthread/pthread_mutexattr_settype.c index ef8b263686..9922a34355 100644 --- a/libc/pthread/pthread_mutexattrsettype.c +++ b/libc/pthread/pthread_mutexattr_settype.c @@ -1,5 +1,5 @@ /**************************************************************************** - * libc/pthread/pthread_mutexattrsettype.c + * libc/pthread/pthread_mutexattr_settype.c * * Copyright (C) 2008, 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt -- GitLab From 92d3022411f363fce0f925a5b0a66d773e0560f9 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 2 Nov 2016 09:05:18 -0600 Subject: [PATCH 292/734] Add pthread_mutexattr_get/set_protocol and non-standard sem_get/set_protocol. These may use to enable or disable priority inheritance on a single semaphore. --- include/nuttx/semaphore.h | 3 +- include/pthread.h | 26 ++++- include/semaphore.h | 23 +++- include/sys/syscall.h | 18 ++- libc/pthread/Make.defs | 4 + libc/pthread/pthread_attr_destroy.c | 3 +- libc/pthread/pthread_mutexattr_destroy.c | 1 - libc/pthread/pthread_mutexattr_getprotocol.c | 73 ++++++++++++ libc/pthread/pthread_mutexattr_setprotocol.c | 79 +++++++++++++ libc/semaphore/sem_init.c | 23 +--- sched/pthread/pthread_mutexinit.c | 27 ++++- sched/semaphore/Make.defs | 3 + sched/semaphore/sem_getprotocol.c | 85 ++++++++++++++ sched/semaphore/sem_holder.c | 26 +++-- sched/semaphore/sem_setprotocol.c | 110 +++++++++++++++++++ syscall/syscall.csv | 2 + syscall/syscall_lookup.h | 7 +- syscall/syscall_stublookup.c | 3 + 18 files changed, 465 insertions(+), 51 deletions(-) create mode 100644 libc/pthread/pthread_mutexattr_getprotocol.c create mode 100644 libc/pthread/pthread_mutexattr_setprotocol.c create mode 100644 sched/semaphore/sem_getprotocol.c create mode 100644 sched/semaphore/sem_setprotocol.c diff --git a/include/nuttx/semaphore.h b/include/nuttx/semaphore.h index 4a5bb32d32..1d0afca38e 100644 --- a/include/nuttx/semaphore.h +++ b/include/nuttx/semaphore.h @@ -61,12 +61,13 @@ struct inode; struct nsem_inode_s { + sem_t ns_sem; /* The contained semaphore */ + /* Inode payload unique to named semaphores. ns_inode must appear first * in this structure in order to support casting between type sem_t and * types of struct nsem_inode_s. */ FAR struct inode *ns_inode; /* Containing inode */ - sem_t ns_sem; /* The semaphore */ }; #endif diff --git a/include/pthread.h b/include/pthread.h index 64228154f7..e25e63d41f 100644 --- a/include/pthread.h +++ b/include/pthread.h @@ -135,6 +135,12 @@ #define PTHREAD_BARRIER_SERIAL_THREAD 0x1000 +/* Values for protocol attribute */ + +#define PTHREAD_PRIO_NONE SEM_PRIO_NONE +#define PTHREAD_PRIO_INHERIT SEM_PRIO_INHERIT +#define PTHREAD_PRIO_PROTECT SEM_PRIO_PROTECT + /* Definitions to map some non-standard, BSD thread management interfaces to * the non-standard Linux-like prctl() interface. Since these are simple * mappings to prctl, they will return 0 on success and -1 on failure with the @@ -212,6 +218,9 @@ typedef struct pthread_cond_s pthread_cond_t; struct pthread_mutexattr_s { uint8_t pshared; /* PTHREAD_PROCESS_PRIVATE or PTHREAD_PROCESS_SHARED */ +#ifdef CONFIG_PRIORITY_INHERITANCE + uint8_t proto; /* See PTHREAD_PRIO_* definitions */ +#endif #ifdef CONFIG_MUTEX_TYPES uint8_t type; /* Type of the mutex. See PTHREAD_MUTEX_* definitions */ #endif @@ -222,11 +231,11 @@ typedef struct pthread_mutexattr_s pthread_mutexattr_t; struct pthread_mutex_s { - int pid; /* ID of the holder of the mutex */ - sem_t sem; /* Semaphore underlying the implementation of the mutex */ + int pid; /* ID of the holder of the mutex */ + sem_t sem; /* Semaphore underlying the implementation of the mutex */ #ifdef CONFIG_MUTEX_TYPES - uint8_t type; /* Type of the mutex. See PTHREAD_MUTEX_* definitions */ - int nlocks; /* The number of recursive locks held */ + uint8_t type; /* Type of the mutex. See PTHREAD_MUTEX_* definitions */ + int nlocks; /* The number of recursive locks held */ #endif }; @@ -395,6 +404,15 @@ int pthread_mutex_lock(FAR pthread_mutex_t *mutex); int pthread_mutex_trylock(FAR pthread_mutex_t *mutex); int pthread_mutex_unlock(FAR pthread_mutex_t *mutex); +#ifdef CONFIG_PRIORITY_INHERITANCE +/* Manage priority inheritance */ + +int pthread_mutexattr_getprotocol(FAR const pthread_mutexattr_t *attr, + FAR int *protocol); +int pthread_mutexattr_setprotocol(FAR pthread_mutexattr_t *attr, + int protocol); +#endif + /* Operations on condition variables */ int pthread_condattr_init(FAR pthread_condattr_t *attr); diff --git a/include/semaphore.h b/include/semaphore.h index 142ef51ada..41db9caa8b 100644 --- a/include/semaphore.h +++ b/include/semaphore.h @@ -57,6 +57,17 @@ extern "C" * Pre-processor Definitions ****************************************************************************/ +/* Values for protocol attribute */ + +#define SEM_PRIO_NONE 0 +#define SEM_PRIO_INHERIT 1 +#define SEM_PRIO_PROTECT 2 + +/* Bit definitions for the struct sem_s flags field */ + +#define PRIOINHERIT_FLAGS_DISABLE (1 << 0) /* Bit 0: Priority inheritance + * is disabled for this semaphore. */ + /**************************************************************************** * Public Type Declarations ****************************************************************************/ @@ -92,6 +103,7 @@ struct sem_s */ #ifdef CONFIG_PRIORITY_INHERITANCE + uint8_t flags; /* See PRIOINHERIT_FLAGS_* definitions */ # if CONFIG_SEM_PREALLOCHOLDERS > 0 FAR struct semholder_s *hhead; /* List of holders of semaphore counts */ # else @@ -106,9 +118,9 @@ typedef struct sem_s sem_t; #ifdef CONFIG_PRIORITY_INHERITANCE # if CONFIG_SEM_PREALLOCHOLDERS > 0 -# define SEM_INITIALIZER(c) {(c), NULL} /* semcount, hhead */ +# define SEM_INITIALIZER(c) {(c), 0, NULL} /* semcount, flags, hhead */ # else -# define SEM_INITIALIZER(c) {(c), SEMHOLDER_INITIALIZER} /* semcount, holder */ +# define SEM_INITIALIZER(c) {(c), 0, SEMHOLDER_INITIALIZER} /* semcount, flags, holder */ # endif #else # define SEM_INITIALIZER(c) {(c)} /* semcount */ @@ -141,6 +153,13 @@ int sem_close(FAR sem_t *sem); int sem_unlink(FAR const char *name); #endif +#ifdef CONFIG_PRIORITY_INHERITANCE +/* Non-standard interfaces to manage priority inheritance */ + +int sem_getprotocol(FAR sem_t *sem, FAR int *protocol); +int sem_setprotocol(FAR sem_t *sem, int protocol); +#endif + #undef EXTERN #ifdef __cplusplus } diff --git a/include/sys/syscall.h b/include/sys/syscall.h index 2fba44de34..134b2cb27d 100644 --- a/include/sys/syscall.h +++ b/include/sys/syscall.h @@ -91,15 +91,23 @@ #define SYS_sem_trywait (CONFIG_SYS_RESERVED+18) #define SYS_sem_wait (CONFIG_SYS_RESERVED+19) +#ifdef CONFIG_PRIORITY_INHERITANCE +# define SYS_sem_getprotocol (CONFIG_SYS_RESERVED+20) +# define SYS_sem_setprotocol (CONFIG_SYS_RESERVED+21) +# define __SYS_named_sem (CONFIG_SYS_RESERVED+22) +#else +# define __SYS_named_sem (CONFIG_SYS_RESERVED+20) +#endif + /* Named semaphores */ #ifdef CONFIG_FS_NAMED_SEMAPHORES -# define SYS_sem_open (CONFIG_SYS_RESERVED+20) -# define SYS_sem_close (CONFIG_SYS_RESERVED+21) -# define SYS_sem_unlink (CONFIG_SYS_RESERVED+22) -# define __SYS_task_create (CONFIG_SYS_RESERVED+23) +# define SYS_sem_open __SYS_named_sem +# define SYS_sem_close (__SYS_named_sem+1) +# define SYS_sem_unlink (__SYS_named_sem+2) +# define __SYS_task_create (__SYS_named_sem+3) #else -# define __SYS_task_create (CONFIG_SYS_RESERVED+20) +# define __SYS_task_create __SYS_named_sem #endif /* Task creation APIs based on global entry points cannot be use with diff --git a/libc/pthread/Make.defs b/libc/pthread/Make.defs index 0d783c07fd..9d343f6052 100644 --- a/libc/pthread/Make.defs +++ b/libc/pthread/Make.defs @@ -54,6 +54,10 @@ ifeq ($(CONFIG_MUTEX_TYPES),y) CSRCS += pthread_mutexattr_settype.c pthread_mutexattr_gettype.c endif +ifeq ($(CONFIG_PRIORITY_INHERITANCE),y) +CSRCS += pthread_mutexattr_setprotocol.c pthread_mutexattr_getprotocol.c +endif + ifeq ($(CONFIG_BUILD_PROTECTED),y) CSRCS += pthread_startup.c endif diff --git a/libc/pthread/pthread_attr_destroy.c b/libc/pthread/pthread_attr_destroy.c index 084946cf72..7d39a19278 100644 --- a/libc/pthread/pthread_attr_destroy.c +++ b/libc/pthread/pthread_attr_destroy.c @@ -52,8 +52,7 @@ * Function: pthread_attr_destroy * * Description: - * An attributes object can be deleted when it is no longer - * needed. + * An attributes object can be deleted when it is no longer needed. * * Parameters: * attr diff --git a/libc/pthread/pthread_mutexattr_destroy.c b/libc/pthread/pthread_mutexattr_destroy.c index a5ada87790..62d5de4a92 100644 --- a/libc/pthread/pthread_mutexattr_destroy.c +++ b/libc/pthread/pthread_mutexattr_destroy.c @@ -55,7 +55,6 @@ * * Parameters: * attr - * pshared * * Return Value: * 0 if successful. Otherwise, an error code. diff --git a/libc/pthread/pthread_mutexattr_getprotocol.c b/libc/pthread/pthread_mutexattr_getprotocol.c new file mode 100644 index 0000000000..f7851855ac --- /dev/null +++ b/libc/pthread/pthread_mutexattr_getprotocol.c @@ -0,0 +1,73 @@ +/**************************************************************************** + * libc/pthread/pthread_mutexattr_getprotocol.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: pthread_mutexattr_getprotocol + * + * Description: + * Return the value of the mutex protocol attribute. + * + * Parameters: + * attr - A pointer to the mutex attributes to be queried. + * protocol - The user provided location in which to store the protocol + * value. + * + * Return Value: + * 0 if successful. Otherwise, an error code. + * + ****************************************************************************/ + +int pthread_mutexattr_getprotocol(FAR const pthread_mutexattr_t *attr, + FAR int *protocol) +{ + DEBUGASSERT(attr != NULL && protocol != NULL); + + linfo("Returning %d\n", attr->proto); + return attr->proto; +} diff --git a/libc/pthread/pthread_mutexattr_setprotocol.c b/libc/pthread/pthread_mutexattr_setprotocol.c new file mode 100644 index 0000000000..621a94d1c1 --- /dev/null +++ b/libc/pthread/pthread_mutexattr_setprotocol.c @@ -0,0 +1,79 @@ +/**************************************************************************** + * libc/pthread/pthread_mutexattr_setprotocol.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: pthread_mutexattr_setprotocol + * + * Description: + * Set mutex protocol attribute. + * + * Parameters: + * attr - A pointer to the mutex attributes to be modified + * protocol - The new protocol to use + * + * Return Value: + * 0 if successful. Otherwise, an error code. + * + ****************************************************************************/ + +int pthread_mutexattr_setprotocol(FAR pthread_mutexattr_t *attr, + int protocol) +{ + linfo("attr=0x%p protocol=%d\n", attr, protocol); + DEBUGASSERT(attr != NULL); + + if (protocol >= PTHREAD_PRIO_NONE && protocol <= PTHREAD_PRIO_PROTECT) + { + attr->proto = protocol; + return OK; + } + + return EINVAL; +} diff --git a/libc/semaphore/sem_init.c b/libc/semaphore/sem_init.c index 861acb6cde..f4037d342c 100644 --- a/libc/semaphore/sem_init.c +++ b/libc/semaphore/sem_init.c @@ -1,7 +1,7 @@ /**************************************************************************** * libc/sem/sem_init.c * - * Copyright (C) 2007-2009, 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2011-2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -44,26 +44,6 @@ #include #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Type Declarations - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -108,6 +88,7 @@ int sem_init(FAR sem_t *sem, int pshared, unsigned int value) /* Initialize to support priority inheritance */ #ifdef CONFIG_PRIORITY_INHERITANCE + sem->flags = 0; # if CONFIG_SEM_PREALLOCHOLDERS > 0 sem->hhead = NULL; # else diff --git a/sched/pthread/pthread_mutexinit.c b/sched/pthread/pthread_mutexinit.c index 31d18e2f46..0c65fbc7ed 100644 --- a/sched/pthread/pthread_mutexinit.c +++ b/sched/pthread/pthread_mutexinit.c @@ -1,7 +1,7 @@ /**************************************************************************** * sched/pthread/pthread_mutexinit.c * - * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -66,13 +66,17 @@ * ****************************************************************************/ -int pthread_mutex_init(FAR pthread_mutex_t *mutex, FAR const pthread_mutexattr_t *attr) +int pthread_mutex_init(FAR pthread_mutex_t *mutex, + FAR const pthread_mutexattr_t *attr) { int pshared = 0; #ifdef CONFIG_MUTEX_TYPES - uint8_t type = PTHREAD_MUTEX_DEFAULT; + uint8_t type = PTHREAD_MUTEX_DEFAULT; #endif - int ret = OK; +#ifdef CONFIG_PRIORITY_INHERITANCE + uint8_t proto = PTHREAD_PRIO_INHERIT; +#endif + int ret = OK; int status; sinfo("mutex=0x%p attr=0x%p\n", mutex, attr); @@ -88,6 +92,9 @@ int pthread_mutex_init(FAR pthread_mutex_t *mutex, FAR const pthread_mutexattr_t if (attr) { pshared = attr->pshared; +#ifdef CONFIG_PRIORITY_INHERITANCE + proto = attr->proto; +#endif #ifdef CONFIG_MUTEX_TYPES type = attr->type; #endif @@ -102,8 +109,18 @@ int pthread_mutex_init(FAR pthread_mutex_t *mutex, FAR const pthread_mutexattr_t status = sem_init((FAR sem_t *)&mutex->sem, pshared, 1); if (status != OK) { - ret = EINVAL; + ret = get_errno(); + } + +#ifdef CONFIG_PRIORITY_INHERITANCE + /* Initialize the semaphore protocol */ + + status = sem_setprotocol((FAR sem_t *)&mutex->sem, proto); + if (status != OK) + { + ret = get_errno(); } +#endif /* Set up attributes unique to the mutex type */ diff --git a/sched/semaphore/Make.defs b/sched/semaphore/Make.defs index 39ba7cd2dc..70b9e356bd 100644 --- a/sched/semaphore/Make.defs +++ b/sched/semaphore/Make.defs @@ -33,12 +33,15 @@ # ############################################################################ +# Add semaphore-related files to the build + CSRCS += sem_destroy.c sem_wait.c sem_trywait.c sem_tickwait.c CSRCS += sem_timedwait.c sem_timeout.c sem_post.c sem_recover.c CSRCS += sem_reset.c sem_waitirq.c ifeq ($(CONFIG_PRIORITY_INHERITANCE),y) CSRCS += sem_initialize.c sem_holder.c +CSRCS += sem_setprotocol.c sem_getprotocol.c endif ifeq ($(CONFIG_SPINLOCK),y) diff --git a/sched/semaphore/sem_getprotocol.c b/sched/semaphore/sem_getprotocol.c new file mode 100644 index 0000000000..f3dc169e6e --- /dev/null +++ b/sched/semaphore/sem_getprotocol.c @@ -0,0 +1,85 @@ +/**************************************************************************** + * sched/semaphore/sem_getprotocol.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "semaphore/semaphore.h" + +#ifdef CONFIG_PRIORITY_INHERITANCE + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: sem_getprotocol + * + * Description: + * Return the value of the semaphore protocol attribute. + * + * Parameters: + * sem - A pointer to the semaphore whose attributes are to be + * queried. + * protocol - The user provided location in which to store the protocol + * value. + * + * Return Value: + * 0 if successful. Otherwise, -1 is returned and the errno value is set + * appropriately. + * + ****************************************************************************/ + +int sem_getprotocol(FAR sem_t *sem, FAR int *protocol) +{ + DEBUGASSERT(sem != NULL); + + if ((sem->flags & PRIOINHERIT_FLAGS_DISABLE) != 0) + { + return SEM_PRIO_NONE; + } + else + { + return SEM_PRIO_INHERIT; + } +} + +#endif /* CONFIG_PRIORITY_INHERITANCE */ diff --git a/sched/semaphore/sem_holder.c b/sched/semaphore/sem_holder.c index 769444fd99..6b9f05af3e 100644 --- a/sched/semaphore/sem_holder.c +++ b/sched/semaphore/sem_holder.c @@ -790,7 +790,7 @@ void sem_initholders(void) * Name: sem_destroyholder * * Description: - * Called from sem_destroy() to handle any holders of a semaphore when + * Called from sem_destroyholder() to handle any holders of a semaphore when * it is destroyed. * * Parameters: @@ -855,17 +855,25 @@ void sem_addholder_tcb(FAR struct tcb_s *htcb, FAR sem_t *sem) { FAR struct semholder_s *pholder; - /* Find or allocate a container for this new holder */ + /* If priority inheritance is disabled for this thread, then do not add + * the holder. If there are never holders of the semaphore, the priority + * inheritance is effectively disabled. + */ - pholder = sem_findorallocateholder(sem, htcb); - if (pholder != NULL) + if ((sem->flags & PRIOINHERIT_FLAGS_DISABLE) == 0) { - /* Then set the holder and increment the number of counts held by this - * holder - */ + /* Find or allocate a container for this new holder */ + + pholder = sem_findorallocateholder(sem, htcb); + if (pholder != NULL) + { + /* Then set the holder and increment the number of counts held by this + * holder + */ - pholder->htcb = htcb; - pholder->counts++; + pholder->htcb = htcb; + pholder->counts++; + } } } diff --git a/sched/semaphore/sem_setprotocol.c b/sched/semaphore/sem_setprotocol.c new file mode 100644 index 0000000000..c5609fdcd5 --- /dev/null +++ b/sched/semaphore/sem_setprotocol.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * sched/semaphore/sem_setprotocol.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "semaphore/semaphore.h" + +#ifdef CONFIG_PRIORITY_INHERITANCE + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: sem_setprotocol + * + * Description: + * Set semaphore protocol attribute. + * + * Parameters: + * sem - A pointer to the semaphore whose attributes are to be + * modified + * protocol - The new protocol to use + * + * Return Value: + * 0 if successful. Otherwise, -1 is returned and the errno value is set + * appropriately. + * + ****************************************************************************/ + +int sem_setprotocol(FAR sem_t *sem, int protocol) +{ + int errcode; + + DEBUGASSERT(sem != NULL); + + switch (protocol) + { + case SEM_PRIO_NONE: + /* Disable priority inheritance */ + + sem->flags |= PRIOINHERIT_FLAGS_DISABLE; + + /* Remove any current holders */ + + sem_destroyholder(sem); + return OK; + + case SEM_PRIO_INHERIT: + /* Enable priority inheritance (dangerous) */ + + sem->flags &= ~PRIOINHERIT_FLAGS_DISABLE; + return OK; + + case SEM_PRIO_PROTECT: + /* Not yet supported */ + + errcode = ENOSYS; + break; + + default: + errcode = EINVAL; + break; + } + + set_errno(errcode); + return ERROR; +} + +#endif /* CONFIG_PRIORITY_INHERITANCE */ diff --git a/syscall/syscall.csv b/syscall/syscall.csv index c1fdd2e291..b745998c4b 100644 --- a/syscall/syscall.csv +++ b/syscall/syscall.csv @@ -117,7 +117,9 @@ "sem_close","semaphore.h","defined(CONFIG_FS_NAMED_SEMAPHORES)","int","FAR sem_t*" "sem_destroy","semaphore.h","","int","FAR sem_t*" "sem_open","semaphore.h","defined(CONFIG_FS_NAMED_SEMAPHORES)","FAR sem_t*","FAR const char*","int","..." +"sem_getprotocol","semaphore.h","defined(CONFIG_PRIORITY_INHERITANCE)","int","FAR sem_t*","FAR int*" "sem_post","semaphore.h","","int","FAR sem_t*" +"sem_setprotocol","semaphore.h","defined(CONFIG_PRIORITY_INHERITANCE)","int","FAR sem_t*","int" "sem_timedwait","semaphore.h","","int","FAR sem_t*","FAR const struct timespec *" "sem_trywait","semaphore.h","","int","FAR sem_t*" "sem_unlink","semaphore.h","defined(CONFIG_FS_NAMED_SEMAPHORES)","int","FAR const char*" diff --git a/syscall/syscall_lookup.h b/syscall/syscall_lookup.h index d0f304fbad..e3506707d8 100644 --- a/syscall/syscall_lookup.h +++ b/syscall/syscall_lookup.h @@ -61,12 +61,17 @@ SYSCALL_LOOKUP(uname, 1, STUB_uname) /* Semaphores */ -SYSCALL_LOOKUP(sem_destroy, 2, STUB_sem_destroy) +SYSCALL_LOOKUP(sem_destroy, 1, STUB_sem_destroy) SYSCALL_LOOKUP(sem_post, 1, STUB_sem_post) SYSCALL_LOOKUP(sem_timedwait, 2, STUB_sem_timedwait) SYSCALL_LOOKUP(sem_trywait, 1, STUB_sem_trywait) SYSCALL_LOOKUP(sem_wait, 1, STUB_sem_wait) +#ifdef CONFIG_PRIORITY_INHERITANCE +SYSCALL_LOOKUP(sem_getprotocol, 2, STUB_sem_getprotocol) +SYSCALL_LOOKUP(sem_setprotocol, 2, STUB_sem_setprotocol) +#endif + /* Named semaphores */ #ifdef CONFIG_FS_NAMED_SEMAPHORES diff --git a/syscall/syscall_stublookup.c b/syscall/syscall_stublookup.c index 868eca6f13..996763daea 100644 --- a/syscall/syscall_stublookup.c +++ b/syscall/syscall_stublookup.c @@ -82,13 +82,16 @@ uintptr_t STUB_uname(int nbr, uintptr_t parm1); uintptr_t STUB_sem_close(int nbr, uintptr_t parm1); uintptr_t STUB_sem_destroy(int nbr, uintptr_t parm1); +uintptr_t STUB_sem_getprotocol(int nbr, uintptr_t parm1, uintptr_t parm2); uintptr_t STUB_sem_open(int nbr, uintptr_t parm1, uintptr_t parm2, uintptr_t parm3, uintptr_t parm4, uintptr_t parm5, uintptr_t parm6); uintptr_t STUB_sem_post(int nbr, uintptr_t parm1); +uintptr_t STUB_sem_setprotocol(int nbr, uintptr_t parm1, uintptr_t parm2); uintptr_t STUB_sem_timedwait(int nbr, uintptr_t parm1, uintptr_t parm2); uintptr_t STUB_sem_trywait(int nbr, uintptr_t parm1); uintptr_t STUB_sem_unlink(int nbr, uintptr_t parm1); uintptr_t STUB_sem_wait(int nbr, uintptr_t parm1); + uintptr_t STUB_pgalloc(int nbr, uintptr_t parm1, uintptr_t parm2); uintptr_t STUB_task_create(int nbr, uintptr_t parm1, uintptr_t parm2, uintptr_t parm3, uintptr_t parm4, uintptr_t parm5); -- GitLab From b738a646adb577c0e6514e128131bc24030eb9b3 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 2 Nov 2016 09:29:16 -0600 Subject: [PATCH 293/734] sem_getprotocol() can be in C library --- include/sys/syscall.h | 5 ++--- libc/semaphore/Make.defs | 6 +++++- {sched => libc}/semaphore/sem_getprotocol.c | 6 ++---- sched/semaphore/Make.defs | 3 +-- syscall/syscall.csv | 1 - syscall/syscall_lookup.h | 1 - syscall/syscall_stublookup.c | 1 - 7 files changed, 10 insertions(+), 13 deletions(-) rename {sched => libc}/semaphore/sem_getprotocol.c (96%) diff --git a/include/sys/syscall.h b/include/sys/syscall.h index 134b2cb27d..d0bfcd9597 100644 --- a/include/sys/syscall.h +++ b/include/sys/syscall.h @@ -92,9 +92,8 @@ #define SYS_sem_wait (CONFIG_SYS_RESERVED+19) #ifdef CONFIG_PRIORITY_INHERITANCE -# define SYS_sem_getprotocol (CONFIG_SYS_RESERVED+20) -# define SYS_sem_setprotocol (CONFIG_SYS_RESERVED+21) -# define __SYS_named_sem (CONFIG_SYS_RESERVED+22) +# define SYS_sem_setprotocol (CONFIG_SYS_RESERVED+20) +# define __SYS_named_sem (CONFIG_SYS_RESERVED+21) #else # define __SYS_named_sem (CONFIG_SYS_RESERVED+20) #endif diff --git a/libc/semaphore/Make.defs b/libc/semaphore/Make.defs index b6551ff96a..d456f07520 100644 --- a/libc/semaphore/Make.defs +++ b/libc/semaphore/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # libc/semaphore/Make.defs # -# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -37,6 +37,10 @@ CSRCS += sem_init.c sem_getvalue.c +ifeq ($(CONFIG_PRIORITY_INHERITANCE),y) +CSRCS += sem_getprotocol.c +endif + # Add the semaphore directory to the build DEPPATH += --dep-path semaphore diff --git a/sched/semaphore/sem_getprotocol.c b/libc/semaphore/sem_getprotocol.c similarity index 96% rename from sched/semaphore/sem_getprotocol.c rename to libc/semaphore/sem_getprotocol.c index f3dc169e6e..abbc4c02db 100644 --- a/sched/semaphore/sem_getprotocol.c +++ b/libc/semaphore/sem_getprotocol.c @@ -1,5 +1,5 @@ /**************************************************************************** - * sched/semaphore/sem_getprotocol.c + * libc/semaphore/sem_getprotocol.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -42,8 +42,6 @@ #include #include -#include "semaphore/semaphore.h" - #ifdef CONFIG_PRIORITY_INHERITANCE /**************************************************************************** @@ -70,7 +68,7 @@ int sem_getprotocol(FAR sem_t *sem, FAR int *protocol) { - DEBUGASSERT(sem != NULL); + DEBUGASSERT(sem != NULL && protocol != NULL); if ((sem->flags & PRIOINHERIT_FLAGS_DISABLE) != 0) { diff --git a/sched/semaphore/Make.defs b/sched/semaphore/Make.defs index 70b9e356bd..7eb1740424 100644 --- a/sched/semaphore/Make.defs +++ b/sched/semaphore/Make.defs @@ -40,8 +40,7 @@ CSRCS += sem_timedwait.c sem_timeout.c sem_post.c sem_recover.c CSRCS += sem_reset.c sem_waitirq.c ifeq ($(CONFIG_PRIORITY_INHERITANCE),y) -CSRCS += sem_initialize.c sem_holder.c -CSRCS += sem_setprotocol.c sem_getprotocol.c +CSRCS += sem_initialize.c sem_holder.c sem_setprotocol.c endif ifeq ($(CONFIG_SPINLOCK),y) diff --git a/syscall/syscall.csv b/syscall/syscall.csv index b745998c4b..8d8307f42a 100644 --- a/syscall/syscall.csv +++ b/syscall/syscall.csv @@ -117,7 +117,6 @@ "sem_close","semaphore.h","defined(CONFIG_FS_NAMED_SEMAPHORES)","int","FAR sem_t*" "sem_destroy","semaphore.h","","int","FAR sem_t*" "sem_open","semaphore.h","defined(CONFIG_FS_NAMED_SEMAPHORES)","FAR sem_t*","FAR const char*","int","..." -"sem_getprotocol","semaphore.h","defined(CONFIG_PRIORITY_INHERITANCE)","int","FAR sem_t*","FAR int*" "sem_post","semaphore.h","","int","FAR sem_t*" "sem_setprotocol","semaphore.h","defined(CONFIG_PRIORITY_INHERITANCE)","int","FAR sem_t*","int" "sem_timedwait","semaphore.h","","int","FAR sem_t*","FAR const struct timespec *" diff --git a/syscall/syscall_lookup.h b/syscall/syscall_lookup.h index e3506707d8..0c16b8ce1e 100644 --- a/syscall/syscall_lookup.h +++ b/syscall/syscall_lookup.h @@ -68,7 +68,6 @@ SYSCALL_LOOKUP(sem_trywait, 1, STUB_sem_trywait) SYSCALL_LOOKUP(sem_wait, 1, STUB_sem_wait) #ifdef CONFIG_PRIORITY_INHERITANCE -SYSCALL_LOOKUP(sem_getprotocol, 2, STUB_sem_getprotocol) SYSCALL_LOOKUP(sem_setprotocol, 2, STUB_sem_setprotocol) #endif diff --git a/syscall/syscall_stublookup.c b/syscall/syscall_stublookup.c index 996763daea..f655e0800d 100644 --- a/syscall/syscall_stublookup.c +++ b/syscall/syscall_stublookup.c @@ -82,7 +82,6 @@ uintptr_t STUB_uname(int nbr, uintptr_t parm1); uintptr_t STUB_sem_close(int nbr, uintptr_t parm1); uintptr_t STUB_sem_destroy(int nbr, uintptr_t parm1); -uintptr_t STUB_sem_getprotocol(int nbr, uintptr_t parm1, uintptr_t parm2); uintptr_t STUB_sem_open(int nbr, uintptr_t parm1, uintptr_t parm2, uintptr_t parm3, uintptr_t parm4, uintptr_t parm5, uintptr_t parm6); uintptr_t STUB_sem_post(int nbr, uintptr_t parm1); -- GitLab From 93e938768985b851dae1d7e4b7a21fa0258ff476 Mon Sep 17 00:00:00 2001 From: "Paul A. Patience" Date: Wed, 2 Nov 2016 12:46:04 -0400 Subject: [PATCH 294/734] STM32 ADC: Fix compilation error when DMA isn't enabled --- arch/arm/src/stm32/stm32_adc.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c index acbb707d34..83939499c8 100644 --- a/arch/arm/src/stm32/stm32_adc.c +++ b/arch/arm/src/stm32/stm32_adc.c @@ -2203,6 +2203,7 @@ static void adc_shutdown(FAR struct adc_dev_s *dev) static void adc_rxint(FAR struct adc_dev_s *dev, bool enable) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; + uint32_t regval; ainfo("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0); @@ -2212,8 +2213,15 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable) * end-of-conversion ADC. */ - adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, - priv->hasdma ? ADC_IER_AWD | ADC_ISR_OVR : ADC_IER_ALLINTS); + regval = ADC_IER_ALLINTS; +#ifdef ADC_HAVE_DMA + if (priv->hasdma) + { + regval &= ~(ADC_IER_EOC | ADC_IER_JEOC); + } +#endif + + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, regval); } else { @@ -2803,7 +2811,7 @@ static int adc_interrupt(FAR struct adc_dev_s *dev) /* by MR regval &= ~pending; */ /* by MR adc_putreg(priv, STM32_ADC_ISR_OFFSET, regval); - + adc_putreg(priv, STM32_ADC_ISR_OFFSET, pending); */ return OK; } -- GitLab From d89765e1d05527ec8121708c0c6f31fdd5b97dcd Mon Sep 17 00:00:00 2001 From: "Paul A. Patience" Date: Wed, 2 Nov 2016 12:58:29 -0400 Subject: [PATCH 295/734] spi: Fix Kconfig warning This commit moves the ARCH_HAVE_SPI options outside the check for SPI. Those options don't depend on SPI, and Kconfig files in arch/ enable them even if SPI isn't enabled. Sourcing the driver's Kconfig in drivers/Kconfig only if support for the driver is enabled prevents us from defining these ARCH_HAVE options in the driver's Kconfig. We should probably remove the other checks in drivers/Kconfig and check if the drivers are enabled only in their Kconfig. --- drivers/Kconfig | 2 -- drivers/spi/Kconfig | 24 ++++++++++++------------ 2 files changed, 12 insertions(+), 14 deletions(-) diff --git a/drivers/Kconfig b/drivers/Kconfig index 9b508fdd7f..4ac8a9d0c6 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -345,9 +345,7 @@ menuconfig SPI should be enabled by all platforms that support SPI interfaces. See include/nuttx/spi/spi.h for further SPI driver information. -if SPI source drivers/spi/Kconfig -endif menuconfig I2S bool "I2S Driver Support" diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index ea8b8ac9ab..177d863ee2 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -3,6 +3,18 @@ # see the file kconfig-language.txt in the NuttX tools repository. # +config ARCH_HAVE_SPI_CRCGENERATION + bool + default n + +config ARCH_HAVE_SPI_CS_CONTROL + bool + default n + +config ARCH_HAVE_SPI_BITORDER + bool + default n + if SPI config SPI_SLAVE @@ -55,10 +67,6 @@ config SPI_HWFEATURES basically the OR of any specific hardware feature and eanbles the SPI hwfeatures() interface method. -config ARCH_HAVE_SPI_CRCGENERATION - bool - default n - config SPI_CRCGENERATION bool default n @@ -69,10 +77,6 @@ config SPI_CRCGENERATION generation of SPI CRCs. Enables the HWFEAT_CRCGENERATION option as well as the hwfeartures() interface method. -config ARCH_HAVE_SPI_CS_CONTROL - bool - default n - config SPI_CS_CONTROL bool "SPI CS Behavior Control" default n @@ -82,10 +86,6 @@ config SPI_CS_CONTROL Enables possibilities to define the behavior of CS. Also enables the hwfeatures() interface method. -config ARCH_HAVE_SPI_BITORDER - bool - default n - config SPI_BITORDER bool "SPI Bit Order Control" default n -- GitLab From b5a94e255aaa4410b59b2e950fa1834af21fabbf Mon Sep 17 00:00:00 2001 From: Ramtin Amin Date: Wed, 2 Nov 2016 12:07:52 -0600 Subject: [PATCH 296/734] Misoc/LM32: Changes to get a clean compilation after initial review and commit --- arch/misoc/Kconfig | 6 +- arch/misoc/include/inttypes.h | 245 +++++++++++++++++++++++++++++++ arch/misoc/src/Makefile | 4 +- arch/misoc/src/lm32/Make.defs | 4 +- arch/misoc/src/lm32/chip.h | 3 - arch/misoc/src/lm32/lm32.h | 2 +- arch/misoc/src/lm32/lm32_irq.c | 2 +- arch/misoc/src/lm32/lm32_isr.c | 61 -------- arch/misoc/src/lm32/lm32_swint.c | 2 +- configs/misoc/scripts/ld.script | 17 +-- configs/misoc/src/Makefile | 2 +- 11 files changed, 259 insertions(+), 89 deletions(-) create mode 100644 arch/misoc/include/inttypes.h delete mode 100644 arch/misoc/src/lm32/lm32_isr.c diff --git a/arch/misoc/Kconfig b/arch/misoc/Kconfig index 5cfbf0268c..f0acc68046 100644 --- a/arch/misoc/Kconfig +++ b/arch/misoc/Kconfig @@ -62,11 +62,11 @@ config MISOC_UART_TX_BUF_SIZE ---help--- Size of TX buffers for MISOC UARTs -ifdef ARCH_CHIP_LM32 +if ARCH_CHIP_LM32 source arch/misoc/src/lm32/Kconfig endif -ifdef ARCH_CHIP_MOR1K -source arch/misoc/src/mor1k/Kconfig +if ARCH_CHIP_MOR1K +#source arch/misoc/src/mor1k/Kconfig endif endif # ARCH_MISOC diff --git a/arch/misoc/include/inttypes.h b/arch/misoc/include/inttypes.h new file mode 100644 index 0000000000..16c4046f7a --- /dev/null +++ b/arch/misoc/include/inttypes.h @@ -0,0 +1,245 @@ +/**************************************************************************** + * arch/misoc/include/inttypes.h + * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MISOC_INCLUDE_INTTYPES_H +#define __ARCH_MISOC_INCLUDE_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PRId8 "d" +#define PRId16 "d" +#define PRId32 "d" +#define PRId64 "lld" + +#define PRIdLEAST8 "d" +#define PRIdLEAST16 "d" +#define PRIdLEAST32 "d" +#define PRIdLEAST64 "lld" + +#define PRIdFAST8 "d" +#define PRIdFAST16 "d" +#define PRIdFAST32 "d" +#define PRIdFAST64 "lld" + +#define PRIdMAX "lld" +#define PRIdPTR "d" + +#define PRIi8 "i" +#define PRIi16 "i" +#define PRIi32 "i" +#define PRIi64 "lli" + +#define PRIiLEAST8 "i" +#define PRIiLEAST16 "i" +#define PRIiLEAST32 "i" +#define PRIiLEAST64 "lli" + +#define PRIiFAST8 "i" +#define PRIiFAST16 "i" +#define PRIiFAST32 "i" +#define PRIiFAST64 "lli" + +#define PRIiMAX "lli" +#define PRIiPTR "i" + +#define PRIo8 "o" +#define PRIo16 "o" +#define PRIo32 "o" +#define PRIo64 "llo" + +#define PRIoLEAST8 "o" +#define PRIoLEAST16 "o" +#define PRIoLEAST32 "o" +#define PRIoLEAST64 "llo" + +#define PRIoFAST8 "o" +#define PRIoFAST16 "o" +#define PRIoFAST32 "o" +#define PRIoFAST64 "llo" + +#define PRIoMAX "llo" +#define PRIoPTR "o" + +#define PRIu8 "u" +#define PRIu16 "u" +#define PRIu32 "u" +#define PRIu64 "llu" + +#define PRIuLEAST8 "u" +#define PRIuLEAST16 "u" +#define PRIuLEAST32 "u" +#define PRIuLEAST64 "llu" + +#define PRIuFAST8 "u" +#define PRIuFAST16 "u" +#define PRIuFAST32 "u" +#define PRIuFAST64 "llu" + +#define PRIuMAX "llu" +#define PRIuPTR "u" + +#define PRIx8 "x" +#define PRIx16 "x" +#define PRIx32 "x" +#define PRIx64 "llx" + +#define PRIxLEAST8 "x" +#define PRIxLEAST16 "x" +#define PRIxLEAST32 "x" +#define PRIxLEAST64 "llx" + +#define PRIxFAST8 "x" +#define PRIxFAST16 "x" +#define PRIxFAST32 "x" +#define PRIxFAST64 "llx" + +#define PRIxMAX "llx" +#define PRIxPTR "x" + +#define PRIX8 "X" +#define PRIX16 "X" +#define PRIX32 "X" +#define PRIX64 "llX" + +#define PRIXLEAST8 "X" +#define PRIXLEAST16 "X" +#define PRIXLEAST32 "X" +#define PRIXLEAST64 "llX" + +#define PRIXFAST8 "X" +#define PRIXFAST16 "X" +#define PRIXFAST32 "X" +#define PRIXFAST64 "llX" + +#define PRIXMAX "llX" +#define PRIXPTR "X" + +#define SCNd8 "hhd" +#define SCNd16 "hd" +#define SCNd32 "d" +#define SCNd64 "lld" + +#define SCNdLEAST8 "hhd" +#define SCNdLEAST16 "hd" +#define SCNdLEAST32 "d" +#define SCNdLEAST64 "lld" + +#define SCNdFAST8 "hhd" +#define SCNdFAST16 "hd" +#define SCNdFAST32 "d" +#define SCNdFAST64 "lld" + +#define SCNdMAX "lld" +#define SCNdPTR "d" + +#define SCNi8 "hhi" +#define SCNi16 "hi" +#define SCNi32 "i" +#define SCNi64 "lli" + +#define SCNiLEAST8 "hhi" +#define SCNiLEAST16 "hi" +#define SCNiLEAST32 "i" +#define SCNiLEAST64 "lli" + +#define SCNiFAST8 "hhi" +#define SCNiFAST16 "hi" +#define SCNiFAST32 "i" +#define SCNiFAST64 "lli" + +#define SCNiMAX "lli" +#define SCNiPTR "i" + +#define SCNo8 "hho" +#define SCNo16 "ho" +#define SCNo32 "o" +#define SCNo64 "llo" + +#define SCNoLEAST8 "hho" +#define SCNoLEAST16 "ho" +#define SCNoLEAST32 "o" +#define SCNoLEAST64 "llo" + +#define SCNoFAST8 "hho" +#define SCNoFAST16 "ho" +#define SCNoFAST32 "o" +#define SCNoFAST64 "llo" + +#define SCNoMAX "llo" +#define SCNoPTR "o" + +#define SCNu8 "hhu" +#define SCNu16 "hu" +#define SCNu32 "u" +#define SCNu64 "llu" + +#define SCNuLEAST8 "hhu" +#define SCNuLEAST16 "hu" +#define SCNuLEAST32 "u" +#define SCNuLEAST64 "llu" + +#define SCNuFAST8 "hhu" +#define SCNuFAST16 "hu" +#define SCNuFAST32 "u" +#define SCNuFAST64 "llu" + +#define SCNuMAX "llu" +#define SCNuPTR "u" + +#define SCNx8 "hhx" +#define SCNx16 "hx" +#define SCNx32 "x" +#define SCNx64 "llx" + +#define SCNxLEAST8 "hhx" +#define SCNxLEAST16 "hx" +#define SCNxLEAST32 "x" +#define SCNxLEAST64 "llx" + +#define SCNxFAST8 "hhx" +#define SCNxFAST16 "hx" +#define SCNxFAST32 "x" +#define SCNxFAST64 "llx" + +#define SCNxMAX "llx" +#define SCNxPTR "x" + +#endif /* __ARCH_MISOC_INCLUDE_INTTYPES_H */ diff --git a/arch/misoc/src/Makefile b/arch/misoc/src/Makefile index 6a0285810b..19bd124422 100644 --- a/arch/misoc/src/Makefile +++ b/arch/misoc/src/Makefile @@ -3,7 +3,6 @@ # # Copyright (C) 2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt -# Ramtin Amin # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions @@ -139,9 +138,8 @@ board/libboard$(LIBEXT): $(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" libboard$(LIBEXT) EXTRADEFINES=$(EXTRADEFINES) nuttx$(EXEEXT): $(HEAD_OBJ) board/libboard$(LIBEXT) - @echo "LD: nuttx toto $(LIBGCC)" $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) -o $(NUTTX) $(HEAD_OBJ) $(EXTRA_OBJS) \ - $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LDENDGROUP) + $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) $(LDENDGROUP) ifneq ($(CONFIG_WINDOWS_NATIVE),y) $(Q) $(NM) $(NUTTX) | \ grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ diff --git a/arch/misoc/src/lm32/Make.defs b/arch/misoc/src/lm32/Make.defs index 1a0ce75de2..8338154388 100644 --- a/arch/misoc/src/lm32/Make.defs +++ b/arch/misoc/src/lm32/Make.defs @@ -39,11 +39,11 @@ HEAD_ASRC = lm32_vectors.S CMN_ASRCS = CMN_CSRCS = misoc_uart.c -CHIP_ASRCS = lm32_start.S lm32_syscall.S +CHIP_ASRCS = lm32_syscall.S CHIP_CSRCS = lm32_allocateheap.c lm32_assert.c lm32_blocktask.c CHIP_CSRCS += lm32_copystate.c lm32_createstack.c lm32_doirq.c lm32_dumpstate.c CHIP_CSRCS += lm32_dumpstate.c lm32_exit.c lm32_idle.c lm32_initialize.c CHIP_CSRCS += lm32_initialstate.c lm32_interruptcontext.c lm32_irq.c -CHIP_CSRCS += lm32_isr.c lm32_releasepending.c lm32_releasestack.c +CHIP_CSRCS += lm32_releasepending.c lm32_releasestack.c CHIP_CSRCS += lm32_stackframe.c lm32_swint.c lm32_unblocktask.c diff --git a/arch/misoc/src/lm32/chip.h b/arch/misoc/src/lm32/chip.h index bdb8823c5a..78d671f7f9 100644 --- a/arch/misoc/src/lm32/chip.h +++ b/arch/misoc/src/lm32/chip.h @@ -92,7 +92,4 @@ static inline unsigned int irq_pending(void) * Public Function Prototypes ****************************************************************************/ -void uart_isr(void); -void isr(void); - #endif /* __ARCH_MISOC_SRC_LM32_CHIP_H */ diff --git a/arch/misoc/src/lm32/lm32.h b/arch/misoc/src/lm32/lm32.h index fe18969c75..8098da7492 100644 --- a/arch/misoc/src/lm32/lm32.h +++ b/arch/misoc/src/lm32/lm32.h @@ -147,7 +147,7 @@ void lm32_timer_initialize(void); /* Software interrupts ******************************************************/ -uint32_t lm32_swint(int irq, FAR void *context); +uint32_t *lm32_swint(int irq, FAR void *context); /* Signal handling **********************************************************/ diff --git a/arch/misoc/src/lm32/lm32_irq.c b/arch/misoc/src/lm32/lm32_irq.c index 2e01b511fd..726d60c297 100644 --- a/arch/misoc/src/lm32/lm32_irq.c +++ b/arch/misoc/src/lm32/lm32_irq.c @@ -46,7 +46,7 @@ #include #include -#include "chip_irqasm.h" +#include "chip.h" #include "lm32.h" /**************************************************************************** diff --git a/arch/misoc/src/lm32/lm32_isr.c b/arch/misoc/src/lm32/lm32_isr.c deleted file mode 100644 index 539614d317..0000000000 --- a/arch/misoc/src/lm32/lm32_isr.c +++ /dev/null @@ -1,61 +0,0 @@ -/**************************************************************************** - * arch/misoc/src/lm32/lm32_isr.c - * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Ramtin Amin - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip_irqasm.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void uart_isr() -{ -} - -void isr(void) -{ - unsigned int irqs; - - irqs = irq_pending() & irq_getmask(); - - if (irqs & (1 << UART_INTERRUPT)) - { - uart_isr(); - } -} diff --git a/arch/misoc/src/lm32/lm32_swint.c b/arch/misoc/src/lm32/lm32_swint.c index c8148812cc..f8c7b280ee 100644 --- a/arch/misoc/src/lm32/lm32_swint.c +++ b/arch/misoc/src/lm32/lm32_swint.c @@ -130,7 +130,7 @@ static void dispatch_syscall(void) * ****************************************************************************/ -uint32_t lm32_swint(int irq, FAR void *context) +uint32_t *lm32_swint(int irq, FAR void *context) { uint32_t *regs = (uint32_t *)context; diff --git a/configs/misoc/scripts/ld.script b/configs/misoc/scripts/ld.script index 806aa57928..0a3aa7e3d0 100644 --- a/configs/misoc/scripts/ld.script +++ b/configs/misoc/scripts/ld.script @@ -36,23 +36,14 @@ OUTPUT_FORMAT("elf32-lm32") ENTRY(_stext) +/*INCLUDE configs/misoc/include/generated/regions.ld*/ MEMORY { - rom : ORIGIN = 0x00000000, LENGTH = 0x00008000 - sram : ORIGIN = 0x10000000, LENGTH = 0x00004000 - main_ram : ORIGIN = 0x40000000, LENGTH = 0x00080000 + rom : ORIGIN = 0x00000000, LENGTH = 0x00008000 + sram : ORIGIN = 0x10000000, LENGTH = 0x00004000 + main_ram : ORIGIN = 0x40000000, LENGTH = 0x00080000 } -/* -MEMORY -{ - flash (rxai!w) : ORIGIN = 0x80002000, LENGTH = 256K - 8K - intram (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 32K - userpage : ORIGIN = 0x80800000, LENGTH = 512 - factorypage : ORIGIN = 0x80800200, LENGTH = 512 -} -*/ - SECTIONS { .text : { diff --git a/configs/misoc/src/Makefile b/configs/misoc/src/Makefile index b52ee91e5c..0607a11ed3 100644 --- a/configs/misoc/src/Makefile +++ b/configs/misoc/src/Makefile @@ -37,6 +37,6 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = atmega_boot.c +CSRCS = lm32_boot.c include $(TOPDIR)/configs/Board.mk -- GitLab From 6c51544e56cf4d568d176d0ae5ffa268f07717af Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 2 Nov 2016 14:24:16 -0600 Subject: [PATCH 297/734] Update some comments --- include/nuttx/semaphore.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/nuttx/semaphore.h b/include/nuttx/semaphore.h index 1d0afca38e..a4bec12cd2 100644 --- a/include/nuttx/semaphore.h +++ b/include/nuttx/semaphore.h @@ -61,6 +61,10 @@ struct inode; struct nsem_inode_s { + /* This must be the first element of the structure. In sem_close() this + * structure must be cast compatible with sem_t. + */ + sem_t ns_sem; /* The contained semaphore */ /* Inode payload unique to named semaphores. ns_inode must appear first -- GitLab From d5b4d848d3ed481b1d74ff8117af4c859a1dfb3b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 2 Nov 2016 14:43:03 -0600 Subject: [PATCH 298/734] Move protoypes for the non-standard include/semaphore.h file to the non-standard include/nuttx/semaphore.h with the other non-standard semaphore interfaces. --- include/nuttx/semaphore.h | 43 +++++++++++++++++++++++++++++++ include/semaphore.h | 7 ----- libc/semaphore/sem_getprotocol.c | 3 ++- sched/pthread/pthread_mutexinit.c | 2 ++ sched/semaphore/sem_setprotocol.c | 3 ++- syscall/syscall.csv | 2 +- 6 files changed, 50 insertions(+), 10 deletions(-) diff --git a/include/nuttx/semaphore.h b/include/nuttx/semaphore.h index a4bec12cd2..7fef2a91c5 100644 --- a/include/nuttx/semaphore.h +++ b/include/nuttx/semaphore.h @@ -138,6 +138,49 @@ int sem_tickwait(FAR sem_t *sem, systime_t start, uint32_t delay); int sem_reset(FAR sem_t *sem, int16_t count); +/**************************************************************************** + * Function: sem_getprotocol + * + * Description: + * Return the value of the semaphore protocol attribute. + * + * Parameters: + * sem - A pointer to the semaphore whose attributes are to be + * queried. + * protocol - The user provided location in which to store the protocol + * value. + * + * Return Value: + * 0 if successful. Otherwise, -1 is returned and the errno value is set + * appropriately. + * + ****************************************************************************/ + +#ifdef CONFIG_PRIORITY_INHERITANCE +int sem_getprotocol(FAR sem_t *sem, FAR int *protocol); +#endif + +/**************************************************************************** + * Function: sem_setprotocol + * + * Description: + * Set semaphore protocol attribute. + * + * Parameters: + * sem - A pointer to the semaphore whose attributes are to be + * modified + * protocol - The new protocol to use + * + * Return Value: + * 0 if successful. Otherwise, -1 is returned and the errno value is set + * appropriately. + * + ****************************************************************************/ + +#ifdef CONFIG_PRIORITY_INHERITANCE +int sem_setprotocol(FAR sem_t *sem, int protocol); +#endif + #undef EXTERN #ifdef __cplusplus } diff --git a/include/semaphore.h b/include/semaphore.h index 41db9caa8b..964d753bd9 100644 --- a/include/semaphore.h +++ b/include/semaphore.h @@ -153,13 +153,6 @@ int sem_close(FAR sem_t *sem); int sem_unlink(FAR const char *name); #endif -#ifdef CONFIG_PRIORITY_INHERITANCE -/* Non-standard interfaces to manage priority inheritance */ - -int sem_getprotocol(FAR sem_t *sem, FAR int *protocol); -int sem_setprotocol(FAR sem_t *sem, int protocol); -#endif - #undef EXTERN #ifdef __cplusplus } diff --git a/libc/semaphore/sem_getprotocol.c b/libc/semaphore/sem_getprotocol.c index abbc4c02db..4ae1606ff7 100644 --- a/libc/semaphore/sem_getprotocol.c +++ b/libc/semaphore/sem_getprotocol.c @@ -39,9 +39,10 @@ #include -#include #include +#include + #ifdef CONFIG_PRIORITY_INHERITANCE /**************************************************************************** diff --git a/sched/pthread/pthread_mutexinit.c b/sched/pthread/pthread_mutexinit.c index 0c65fbc7ed..fe9620da0b 100644 --- a/sched/pthread/pthread_mutexinit.c +++ b/sched/pthread/pthread_mutexinit.c @@ -44,6 +44,8 @@ #include #include +#include + #include "pthread/pthread.h" /**************************************************************************** diff --git a/sched/semaphore/sem_setprotocol.c b/sched/semaphore/sem_setprotocol.c index c5609fdcd5..daacca9f30 100644 --- a/sched/semaphore/sem_setprotocol.c +++ b/sched/semaphore/sem_setprotocol.c @@ -39,10 +39,11 @@ #include -#include #include #include +#include + #include "semaphore/semaphore.h" #ifdef CONFIG_PRIORITY_INHERITANCE diff --git a/syscall/syscall.csv b/syscall/syscall.csv index 8d8307f42a..8ecf52854f 100644 --- a/syscall/syscall.csv +++ b/syscall/syscall.csv @@ -118,7 +118,7 @@ "sem_destroy","semaphore.h","","int","FAR sem_t*" "sem_open","semaphore.h","defined(CONFIG_FS_NAMED_SEMAPHORES)","FAR sem_t*","FAR const char*","int","..." "sem_post","semaphore.h","","int","FAR sem_t*" -"sem_setprotocol","semaphore.h","defined(CONFIG_PRIORITY_INHERITANCE)","int","FAR sem_t*","int" +"sem_setprotocol","nuttx/semaphore.h","defined(CONFIG_PRIORITY_INHERITANCE)","int","FAR sem_t*","int" "sem_timedwait","semaphore.h","","int","FAR sem_t*","FAR const struct timespec *" "sem_trywait","semaphore.h","","int","FAR sem_t*" "sem_unlink","semaphore.h","defined(CONFIG_FS_NAMED_SEMAPHORES)","int","FAR const char*" -- GitLab From 9a49ab8260435da6ba3cf26d7a7f0fcc5c2b8efa Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 2 Nov 2016 16:32:59 -0600 Subject: [PATCH 299/734] Correct a wrong comment --- include/nuttx/semaphore.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/include/nuttx/semaphore.h b/include/nuttx/semaphore.h index 7fef2a91c5..d9df434fef 100644 --- a/include/nuttx/semaphore.h +++ b/include/nuttx/semaphore.h @@ -67,9 +67,7 @@ struct nsem_inode_s sem_t ns_sem; /* The contained semaphore */ - /* Inode payload unique to named semaphores. ns_inode must appear first - * in this structure in order to support casting between type sem_t and - * types of struct nsem_inode_s. */ + /* Inode payload unique to named semaphores. */ FAR struct inode *ns_inode; /* Containing inode */ }; -- GitLab From 97bf82ee05036a26a15c1df6f27574ca60888df6 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 2 Nov 2016 18:21:46 -0600 Subject: [PATCH 300/734] Semaphores: Provide macros for sem_setprotobol() and sem_getprotocol() if priority inheritance is not enabled. More SEM_PRIO_* definitions to include/nuttx/semaphore.h --- TODO | 51 ++++++++++++++++++++++++++++++- include/nuttx/semaphore.h | 33 ++++++++++++++++++-- include/pthread.h | 27 ++++++++-------- include/semaphore.h | 22 +++++-------- sched/semaphore/sem_setprotocol.c | 19 ++++++++++++ 5 files changed, 120 insertions(+), 32 deletions(-) diff --git a/TODO b/TODO index 3c187e017e..97d9f00719 100644 --- a/TODO +++ b/TODO @@ -9,7 +9,7 @@ issues related to each board port. nuttx/: - (13) Task/Scheduler (sched/) + (14) Task/Scheduler (sched/) (1) Memory Management (mm/) (1) Power Management (drivers/pm) (3) Signals (sched/signal, arch/) @@ -216,6 +216,55 @@ o Task/Scheduler (sched/) Status: Open Priority: Medium-ish + Title: ISSUES WITH PRIORITY INHERITANCE WHEN SEMAPHORE USED AS IPC + Description: The semaphores have multiple uses. The typical usage is where + the semaphore is used as lock on one or more resources. In + this typical case, priority inheritance works perfectly: The + holder of a semaphore count must be remembered so that its + priority can be boosted if a higher priority task requires a + count from the semaphore. It remains the holder until is + calls sem_post() to release the count on the semaphore. + + But a different usage model for semaphores is for signalling + events. In this case, the semaphore count is initialized to + zero and the receiving task calls sem_wait() to wait for the + next event of interest. When an event of interest is + detected by another task (or even an interrupt handler), + sem_post() is called which increments the count to 1 and + wakes up the receiving task. + + For example, in the following TASK A waits for events and + TASK B (or perhaps an interrupt handler) signals task A of + the occurence of the events by posting the semaphore: + + TASK A TASK B + sem_init(sem, 0, 0); + sem_wait(sem); + sem_post(sem); + Awakens as holder + + These two usage models are really very different and priority + inheritance simply does not apply when the semaphore is used for + signalling rather than locking. In this signalling case + priority inheritance can interfere with the operation of the + semaphore. The problem is that when TASK A is awakened it is + a holder of the semaphore. Normally, a task is removed from + the holder list when it finally release the + + However, TASK A never calls sem_post(sem) so it becomes + *permanently* a holder of the semaphore and may have its + priority boosted when any other task tries to acquire the + semaphore. + + The fix is to call sem_setprotocol(SEM_PRIO_NONE) immediately + after the sem_init() call so that there will be no priority + inheritance operations on this semaphore used for signalling. + Status: Open + Priority: High. If you have priority inheritance enabled and you use + semaphores for signalling events, then you *must* call + sem_setprotocol(SEM_PRIO_NONE) immediately after initializing + the semaphore. + Title: SCALABILITY Description: Task control information is retained in simple lists. This is completely appropriate for small embedded systems where diff --git a/include/nuttx/semaphore.h b/include/nuttx/semaphore.h index 7fef2a91c5..04fde1bacb 100644 --- a/include/nuttx/semaphore.h +++ b/include/nuttx/semaphore.h @@ -51,6 +51,12 @@ * Pre-processor Definitions ****************************************************************************/ +/* Values for protocol attribute */ + +#define SEM_PRIO_NONE 0 +#define SEM_PRIO_INHERIT 1 +#define SEM_PRIO_PROTECT 2 + /**************************************************************************** * Public Type Definitions ****************************************************************************/ @@ -67,9 +73,7 @@ struct nsem_inode_s sem_t ns_sem; /* The contained semaphore */ - /* Inode payload unique to named semaphores. ns_inode must appear first - * in this structure in order to support casting between type sem_t and - * types of struct nsem_inode_s. */ + /* Inode payload unique to named semaphores. */ FAR struct inode *ns_inode; /* Containing inode */ }; @@ -158,6 +162,8 @@ int sem_reset(FAR sem_t *sem, int16_t count); #ifdef CONFIG_PRIORITY_INHERITANCE int sem_getprotocol(FAR sem_t *sem, FAR int *protocol); +#else +# define sem_getprotocol(s,p) do { *(p) == SEM_PRIO_NONE); } while (0) #endif /**************************************************************************** @@ -166,6 +172,25 @@ int sem_getprotocol(FAR sem_t *sem, FAR int *protocol); * Description: * Set semaphore protocol attribute. * + * One particularly important use of this function is when a semaphore + * is used for inter-task communication like: + * + * TASK A TASK B + * sem_init(sem, 0, 0); + * sem_wait(sem); + * sem_post(sem); + * Awakens as holder + * + * In this case priority inheritance can interfere with the operation of + * the semaphore. The problem is that when TASK A is restarted it is a + * holder of the semaphore. However, it never calls sem_post(sem) so it + * becomes *permanently* a holder of the semaphore and may have its + * priority boosted when any other task tries to acquire the semaphore. + * + * The fix is to call sem_setprotocol(SEM_PRIO_NONE) immediately after + * the sem_init() call so that there will be no priority inheritance + * operations on this semaphore. + * * Parameters: * sem - A pointer to the semaphore whose attributes are to be * modified @@ -179,6 +204,8 @@ int sem_getprotocol(FAR sem_t *sem, FAR int *protocol); #ifdef CONFIG_PRIORITY_INHERITANCE int sem_setprotocol(FAR sem_t *sem, int protocol); +#else +# define sem_setprotocol(s,p) DEBUGASSERT((p) == SEM_PRIO_NONE); #endif #undef EXTERN diff --git a/include/pthread.h b/include/pthread.h index e25e63d41f..1c368d737b 100644 --- a/include/pthread.h +++ b/include/pthread.h @@ -40,18 +40,19 @@ * Included Files ********************************************************************************/ -#include /* Default settings */ -#include /* Compiler settings, noreturn_function */ +#include /* Default settings */ +#include /* Compiler settings, noreturn_function */ -#include /* Needed for general types */ -#include /* Needed by pthread_[set|get]name_np */ +#include /* Needed for general types */ +#include /* Needed by pthread_[set|get]name_np */ -#include /* C99 fixed width integer types */ -#include /* C99 boolean types */ -#include /* For getpid */ -#include /* Needed for sem_t */ -#include /* Needed for sigset_t, includes this file */ -#include /* Needed for struct timespec */ +#include /* C99 fixed width integer types */ +#include /* C99 boolean types */ +#include /* For getpid */ +#include /* Needed for sigset_t, includes this file */ +#include /* Needed for struct timespec */ + +#include /* For sem_t and SEM_PRIO_* defines */ /******************************************************************************** * Pre-processor Definitions @@ -112,9 +113,7 @@ #define PTHREAD_INHERIT_SCHED 0 #define PTHREAD_EXPLICIT_SCHED 1 -#define PTHREAD_PRIO_NONE 0 -#define PTHREAD_PRIO_INHERIT 1 -#define PTHREAD_PRIO_PROTECT 2 +/* Default priority */ #define PTHREAD_DEFAULT_PRIORITY 100 @@ -135,7 +134,7 @@ #define PTHREAD_BARRIER_SERIAL_THREAD 0x1000 -/* Values for protocol attribute */ +/* Values for protocol mutex attribute */ #define PTHREAD_PRIO_NONE SEM_PRIO_NONE #define PTHREAD_PRIO_INHERIT SEM_PRIO_INHERIT diff --git a/include/semaphore.h b/include/semaphore.h index 964d753bd9..8821b129d0 100644 --- a/include/semaphore.h +++ b/include/semaphore.h @@ -45,24 +45,10 @@ #include #include -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Values for protocol attribute */ - -#define SEM_PRIO_NONE 0 -#define SEM_PRIO_INHERIT 1 -#define SEM_PRIO_PROTECT 2 - /* Bit definitions for the struct sem_s flags field */ #define PRIOINHERIT_FLAGS_DISABLE (1 << 0) /* Bit 0: Priority inheritance @@ -130,6 +116,14 @@ typedef struct sem_s sem_t; * Public Data ****************************************************************************/ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ diff --git a/sched/semaphore/sem_setprotocol.c b/sched/semaphore/sem_setprotocol.c index daacca9f30..1350206941 100644 --- a/sched/semaphore/sem_setprotocol.c +++ b/sched/semaphore/sem_setprotocol.c @@ -58,6 +58,25 @@ * Description: * Set semaphore protocol attribute. * + * One particularly important use of this furnction is when a semaphore + * is used for inter-task communication like: + * + * TASK A TASK B + * sem_init(sem, 0, 0); + * sem_wait(sem); + * sem_post(sem); + * Awakens as holder + * + * In this case priority inheritance can interfere with the operation of + * the semaphore. The problem is that when TASK A is restarted it is a + * holder of the semaphore. However, it never calls sem_post(sem) so it + * becomes *permanently* a holder of the semaphore and may have its + * priority boosted when any other task tries to acquire the semaphore. + * + * The fix is to call sem_setprotocol(SEM_PRIO_NONE) immediately after + * the sem_init() call so that there will be no priority inheritance + * operations on this semaphore. + * * Parameters: * sem - A pointer to the semaphore whose attributes are to be * modified -- GitLab From 470c692dbf79098b5fdf18169bbf87c7ad9a2138 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 2 Nov 2016 18:31:22 -0600 Subject: [PATCH 301/734] Update TODO list --- TODO | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/TODO b/TODO index 97d9f00719..62d2e562ce 100644 --- a/TODO +++ b/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated October 9, 2016) +NuttX TODO List (Last updated November 2, 2016) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with @@ -217,13 +217,14 @@ o Task/Scheduler (sched/) Priority: Medium-ish Title: ISSUES WITH PRIORITY INHERITANCE WHEN SEMAPHORE USED AS IPC - Description: The semaphores have multiple uses. The typical usage is where + Description: Semaphores have multiple uses. The typical usage is where the semaphore is used as lock on one or more resources. In this typical case, priority inheritance works perfectly: The holder of a semaphore count must be remembered so that its priority can be boosted if a higher priority task requires a - count from the semaphore. It remains the holder until is - calls sem_post() to release the count on the semaphore. + count from the semaphore. It remains the holder until the + same task calls sem_post() to release the count on the + semaphore. But a different usage model for semaphores is for signalling events. In this case, the semaphore count is initialized to @@ -237,11 +238,14 @@ o Task/Scheduler (sched/) TASK B (or perhaps an interrupt handler) signals task A of the occurence of the events by posting the semaphore: + ---------------------- --------------- TASK A TASK B + ---------------------- --------------- sem_init(sem, 0, 0); sem_wait(sem); sem_post(sem); Awakens as holder + ---------------------- --------------- These two usage models are really very different and priority inheritance simply does not apply when the semaphore is used for @@ -249,12 +253,13 @@ o Task/Scheduler (sched/) priority inheritance can interfere with the operation of the semaphore. The problem is that when TASK A is awakened it is a holder of the semaphore. Normally, a task is removed from - the holder list when it finally release the + the holder list when it finally releases the semaphore via + sem_post(). However, TASK A never calls sem_post(sem) so it becomes *permanently* a holder of the semaphore and may have its - priority boosted when any other task tries to acquire the - semaphore. + priority boosted at any time when any other task tries to + acquire the semaphore. The fix is to call sem_setprotocol(SEM_PRIO_NONE) immediately after the sem_init() call so that there will be no priority -- GitLab From 54d7656f18375215e30bcfda74ded9c408ef4f37 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 07:04:03 -0600 Subject: [PATCH 302/734] Update some comments --- arch/xtensa/src/esp32/esp32_cpuhead.S | 4 +--- arch/xtensa/src/esp32/esp32_cpuidlestack.c | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/xtensa/src/esp32/esp32_cpuhead.S b/arch/xtensa/src/esp32/esp32_cpuhead.S index 9fb05f66ea..40cbf2e85d 100644 --- a/arch/xtensa/src/esp32/esp32_cpuhead.S +++ b/arch/xtensa/src/esp32/esp32_cpuhead.S @@ -110,9 +110,7 @@ __cpu1_start: l32r sp, .Lcpu1_bottomofstack - /* Does it make since to have co-processors enabled on the IDLE thread? */ - -//#warning REVISIT: Must set aside co-processor save ares + /* REVIST: Does it make since to have co-processors enabled on the IDLE thread? */ #ifdef CONFIG_STACK_COLORATION /* Write a known value to the IDLE thread stack to support stack diff --git a/arch/xtensa/src/esp32/esp32_cpuidlestack.c b/arch/xtensa/src/esp32/esp32_cpuidlestack.c index e1f0941ce9..7b2e90364e 100644 --- a/arch/xtensa/src/esp32/esp32_cpuidlestack.c +++ b/arch/xtensa/src/esp32/esp32_cpuidlestack.c @@ -102,9 +102,7 @@ int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size) tcb->adj_stack_ptr = (uint32_t *)topofstack; #if XCHAL_CP_NUM > 0 - /* Does it make since to have co-processors enabled on the IDLE thread? */ - -//#warning REVISIT: Need to set co-processor save are in TCB + /* REVISIT: Does it make since to have co-processors enabled on the IDLE thread? */ #endif return OK; -- GitLab From cb96e632faf84ccaa98d401160b41f78ed3cdf1b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 07:21:25 -0600 Subject: [PATCH 303/734] LM32: Add toolchain configuration; Add Toolchain.defs. --- arch/arm/src/armv7-r/Kconfig | 2 +- arch/misoc/src/lm32/Kconfig | 24 +++++++ arch/misoc/src/lm32/Toolchain.defs | 104 +++++++++++++++++++++++++++++ configs/misoc/hello/Make.defs | 2 +- 4 files changed, 130 insertions(+), 2 deletions(-) create mode 100644 arch/misoc/src/lm32/Toolchain.defs diff --git a/arch/arm/src/armv7-r/Kconfig b/arch/arm/src/armv7-r/Kconfig index 0582a4fee3..810e80601d 100644 --- a/arch/arm/src/armv7-r/Kconfig +++ b/arch/arm/src/armv7-r/Kconfig @@ -162,7 +162,7 @@ config ARMV7R_TOOLCHAIN_GNU_OABI ---help--- This option should work for any GNU toolchain configured for arm-elf-. -endchoice # ARMV7R_HAVE_L2CC +endchoice # Toolchain Selection config ARMV7R_OABI_TOOLCHAIN bool "OABI (vs EABI)" diff --git a/arch/misoc/src/lm32/Kconfig b/arch/misoc/src/lm32/Kconfig index 75814271c6..b9178978e7 100644 --- a/arch/misoc/src/lm32/Kconfig +++ b/arch/misoc/src/lm32/Kconfig @@ -5,4 +5,28 @@ if ARCH_CHIP_LM32 +choice + prompt "Toolchain Selection" + default LM32_TOOLCHAIN_GNUW if HOST_WINDOWS + default LM32_TOOLCHAIN_GNUL if !HOST_WINDOWS + +config LM32_TOOLCHAIN_BUILDROOT + bool "Buildroot (Cygwin or Linux)" + depends on !WINDOWS_NATIVE + +config LM32_TOOLCHAIN_GNUL + bool "Generic GNU toolchain under Linux (or other POSIX environment)" + ---help--- + This option should work for any modern GNU toolchain (GCC 4.5 or newer) + configured for lm32-elf-. + +config LM32_TOOLCHAIN_GNUW + bool "Generic GNU toolchain under Windows" + depends on HOST_WINDOWS + ---help--- + This option should work for any modern GNU toolchain (GCC 4.5 or newer) + configured for lm32-elf-. + +endchoice # Toolchain Selection + endif # ARCH_CHIP_LM32 diff --git a/arch/misoc/src/lm32/Toolchain.defs b/arch/misoc/src/lm32/Toolchain.defs new file mode 100644 index 0000000000..e0227e2e16 --- /dev/null +++ b/arch/misoc/src/lm32/Toolchain.defs @@ -0,0 +1,104 @@ +############################################################################ +# arch/misco/src/lm32/Toolchain.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# Setup for the selected toolchain + +# +# Select and allow the selected toolchain to be overridden by a command-line +#selection. +# + +ifeq ($(filter y, \ + $(CONFIG_LM32_TOOLCHAIN_BUILDROOT) \ + ),y) + CONFIG_LM32_TOOLCHAIN ?= BUILDROOT +endif + +ifeq ($(filter y, \ + $(CONFIG_LM32_TOOLCHAIN_GNUL) \ + ),y) + CONFIG_LM32_TOOLCHAIN ?= GNUL +endif + +ifeq ($(filter y, \ + $(CONFIG_LM32_TOOLCHAIN_GNUW) \ + ),y) + CONFIG_LM32_TOOLCHAIN ?= GNUW +endif + +# +# Supported toolchains +# +# Each toolchain definition should set: +# +# CROSSDEV The GNU toolchain triple (command prefix) +# ARCROSSDEV If required, an alternative prefix used when +# invoking ar and nm. +# ARCHCPUFLAGS CPU-specific flags selecting the instruction set +# FPU options, etc. +# MAXOPTIMIZATION The maximum optimization level that results in +# reliable code generation. +# + +ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) + MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL) +endif + +# NuttX buildroot under Linux or Cygwin + +ifeq ($(CONFIG_LM32_TOOLCHAIN),BUILDROOT) + CROSSDEV ?= lm32-nuttx-elf- + ARCROSSDEV ?= lm32-nuttx-elf- + MAXOPTIMIZATION ?= -Os +endif + +# Generic GNU toolchain on OS X, Linux or any typical Posix system + +ifeq ($(CONFIG_LM32_TOOLCHAIN),GNUL) + CROSSDEV ?= lm32-elf-- + ARCROSSDEV ?= lm32-elf-- + MAXOPTIMIZATION ?= -Os +endif + +# Generic GNU toolchain under Windows (native) + +ifeq ($(CONFIG_LM32_TOOLCHAIN),GNUW) + CROSSDEV ?= lm32-elf-- + ARCROSSDEV ?= lm32-elf-- + MAXOPTIMIZATION ?= -Os + ifeq ($(CONFIG_WINDOWS_CYGWIN),y) + WINTOOL = y + endif +endif diff --git a/configs/misoc/hello/Make.defs b/configs/misoc/hello/Make.defs index b6124b7759..f82c1cb223 100644 --- a/configs/misoc/hello/Make.defs +++ b/configs/misoc/hello/Make.defs @@ -36,7 +36,7 @@ include ${TOPDIR}/.config include ${TOPDIR}/tools/Config.mk -CROSSDEV = lm32-elf- +include ${TOPDIR}/arch/misoc/src/lm32/Toolchain.defs LDSCRIPT = ld.script -- GitLab From 47b043df1eff60b4ed6368dd34dc69a6d48240b0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 08:16:59 -0600 Subject: [PATCH 304/734] drivers/serial.c: Make sure that priority inheritance is not enabled for the signaling semaphores used in the serial driver. --- drivers/serial/serial.c | 38 +++++++++++++++++--------------------- 1 file changed, 17 insertions(+), 21 deletions(-) diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 2b6d7ec8e5..64354e2a76 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -43,7 +43,6 @@ #include #include #include -#include #include #include #include @@ -52,6 +51,7 @@ #include #include +#include #include #include #include @@ -112,16 +112,6 @@ static const struct file_operations g_serialops = * Private Functions ************************************************************************************/ -/************************************************************************************ - * Name: sem_reinit - ************************************************************************************/ - -static int sem_reinit(FAR sem_t *sem, int pshared, unsigned int value) -{ - sem_destroy(sem); - return sem_init(sem, pshared, value); -} - /************************************************************************************ * Name: uart_takesem ************************************************************************************/ @@ -1253,19 +1243,14 @@ static int uart_close(FAR struct file *filep) /* We need to re-initialize the semaphores if this is the last close * of the device, as the close might be caused by pthread_cancel() of * a thread currently blocking on any of them. - * - * REVISIT: This logic *only* works in the case where the cancelled - * thread had the only reference to the serial driver. If there other - * references, then the this logic will not be executed and the - * semaphore count will still be incorrect. */ - sem_reinit(&dev->xmitsem, 0, 0); - sem_reinit(&dev->recvsem, 0, 0); - sem_reinit(&dev->xmit.sem, 0, 1); - sem_reinit(&dev->recv.sem, 0, 1); + sem_reset(&dev->xmitsem, 0); + sem_reset(&dev->recvsem, 0); + sem_reset(&dev->xmit.sem, 1); + sem_reset(&dev->recv.sem, 1); #ifndef CONFIG_DISABLE_POLL - sem_reinit(&dev->pollsem, 0, 1); + sem_reset(&dev->pollsem, 1); #endif uart_givesem(&dev->closesem); @@ -1416,6 +1401,8 @@ errout_with_sem: int uart_register(FAR const char *path, FAR uart_dev_t *dev) { + /* Initialize semaphores */ + sem_init(&dev->xmit.sem, 0, 1); sem_init(&dev->recv.sem, 0, 1); sem_init(&dev->closesem, 0, 1); @@ -1425,6 +1412,15 @@ int uart_register(FAR const char *path, FAR uart_dev_t *dev) sem_init(&dev->pollsem, 0, 1); #endif + /* The recvsem and xmitsem are used for signaling and, hence, should not have + * priroity inheritance enabled. + */ + + sem_setprotocol(&dev->xmitsem, SEM_PRIO_NONE); + sem_setprotocol(&dev->recvsem, SEM_PRIO_NONE); + + /* Register the serial driver */ + _info("Registering %s\n", path); return register_driver(path, &g_serialops, 0666, dev); } -- GitLab From 1e754402b86e10c28ada5949d33c8b759ab463fb Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Thu, 3 Nov 2016 08:50:58 -0600 Subject: [PATCH 305/734] Add C++ support linking with GNU toolchain newlib/stdlibc++ --- arch/arm/src/Makefile | 12 +- configs/bambino-200e/gnutoolcpp/Make.defs | 141 +++ configs/bambino-200e/gnutoolcpp/defconfig | 1004 +++++++++++++++++++++ configs/bambino-200e/gnutoolcpp/setenv.sh | 92 ++ configs/samv71-xult/nsh/defconfig | 8 +- include/cxx/cwchar | 2 +- libxx/Kconfig | 8 + 7 files changed, 1261 insertions(+), 6 deletions(-) create mode 100644 configs/bambino-200e/gnutoolcpp/Make.defs create mode 100644 configs/bambino-200e/gnutoolcpp/defconfig create mode 100644 configs/bambino-200e/gnutoolcpp/setenv.sh diff --git a/arch/arm/src/Makefile b/arch/arm/src/Makefile index e505b956da..b182a97e7e 100644 --- a/arch/arm/src/Makefile +++ b/arch/arm/src/Makefile @@ -168,6 +168,14 @@ endif LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" GCC_LIBDIR := ${shell dirname $(LIBGCC)} +ifeq ($(CONFIG_CXX_LINK_GNUTOOL_LIB),y) + LIBGXX = "${shell "$(CXX)" $(ARCHCPUFLAGS) -print-file-name=$(LIBSTDCXX)}" + GXX_LIBDIR := ${shell dirname $(LIBGXX)} + LIBCXXPATH = -L"$(GXX_LIBDIR)" +else + LIBCXXPATH ?= +endif + VPATH += chip VPATH += common VPATH += $(ARCH_SUBDIR) @@ -201,9 +209,9 @@ board$(DELIM)libboard$(LIBEXT): nuttx$(EXEEXT): $(HEAD_OBJ) board$(DELIM)libboard$(LIBEXT) $(Q) echo "LD: nuttx" - $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ + $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(LIBCXXPATH) $(EXTRA_LIBPATHS) \ -o $(NUTTX) $(HEAD_OBJ) $(EXTRA_OBJS) \ - $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) $(LDENDGROUP) + $(LDSTARTGROUP) $(LDLIBS) $(LDLIBSCXX) $(EXTRA_LIBS) $(LIBGCC) $(LDENDGROUP) ifneq ($(CONFIG_WINDOWS_NATIVE),y) $(Q) $(NM) $(NUTTX) | \ grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ diff --git a/configs/bambino-200e/gnutoolcpp/Make.defs b/configs/bambino-200e/gnutoolcpp/Make.defs new file mode 100644 index 0000000000..a7d6e8d274 --- /dev/null +++ b/configs/bambino-200e/gnutoolcpp/Make.defs @@ -0,0 +1,141 @@ +############################################################################ +# configs/bambino-200e/nsh/Make.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# Alan Carvalho de Assis +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +# Setup for the kind of memory that we are executing from + +ifeq ($(CONFIG_LPC43_BOOT_SRAM),y) + LDSCRIPT = ramconfig.ld +endif +ifeq ($(CONFIG_LPC43_BOOT_SPIFI),y) + LDSCRIPT = spificonfig.ld +endif +ifeq ($(CONFIG_LPC43_BOOT_FLASHA),y) + LDSCRIPT = flashaconfig.ld +endif +ifeq ($(CONFIG_LPC43_BOOT_FLASHB),y) + LDSCRIPT = flashaconfig.ld +endif +ifeq ($(CONFIG_LPC43_BOOT_CS0FLASH),y) + LDSCRIPT = cs0flash.ld +endif + +# Setup for Windows vs Linux/Cygwin/OSX environments + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ifeq ($(CONFIG_CXX_LINK_GNUTOOL_LIB),y) +ARCHCXXFLAGS = -fno-builtin -fno-use-cxa-atexit -fcheck-new -specs=nano.specs -lstdc++ -lsupc++ -lm -lgcc -lc -lnosys -std=gnu++11 +else +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +endif +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +ifeq ($(CONFIG_CXX_LINK_GNUTOOL_LIB),y) +LDLIBSCXX = -lstdc++_nano -lsupc++_nano -lnosys -lm +LIBSTDCXX = libstdc++_nano.a +endif + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs --no-wchar-size-warning +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/bambino-200e/gnutoolcpp/defconfig b/configs/bambino-200e/gnutoolcpp/defconfig new file mode 100644 index 0000000000..1c7bbf0c87 --- /dev/null +++ b/configs/bambino-200e/gnutoolcpp/defconfig @@ -0,0 +1,1004 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +CONFIG_ARCH_STDARG_H=y +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +# CONFIG_ARCH_HAVE_HEAPCHECK is not set +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ARCH_HAVE_CUSTOMOPT=y +CONFIG_DEBUG_NOOPT=y +# CONFIG_DEBUG_CUSTOMOPT is not set +# CONFIG_DEBUG_FULLOPT is not set + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +CONFIG_ARCH_CHIP_LPC43XX=y +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM3 is not set +CONFIG_ARCH_CORTEXM4=y +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="lpc43xx" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +CONFIG_ARMV7M_CMNVECTOR=y +# CONFIG_ARMV7M_LAZYFPU is not set +CONFIG_ARCH_HAVE_FPU=y +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y +# CONFIG_ARMV7M_HAVE_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set +# CONFIG_SERIAL_TERMIOS is not set + +# +# LPC43xx Configuration Options +# +# CONFIG_ARCH_CHIP_LPC4310FBD144 is not set +# CONFIG_ARCH_CHIP_LPC4310FET100 is not set +# CONFIG_ARCH_CHIP_LPC4320FBD144 is not set +# CONFIG_ARCH_CHIP_LPC4320FET100 is not set +CONFIG_ARCH_CHIP_LPC4330FBD144=y +# CONFIG_ARCH_CHIP_LPC4330FET100 is not set +# CONFIG_ARCH_CHIP_LPC4330FET180 is not set +# CONFIG_ARCH_CHIP_LPC4330FET256 is not set +# CONFIG_ARCH_CHIP_LPC4337JBD144 is not set +# CONFIG_ARCH_CHIP_LPC4337JET100 is not set +# CONFIG_ARCH_CHIP_LPC4350FBD208 is not set +# CONFIG_ARCH_CHIP_LPC4350FET180 is not set +# CONFIG_ARCH_CHIP_LPC4350FET256 is not set +# CONFIG_ARCH_CHIP_LPC4353FBD208 is not set +# CONFIG_ARCH_CHIP_LPC4353FET180 is not set +# CONFIG_ARCH_CHIP_LPC4353FET256 is not set +# CONFIG_ARCH_CHIP_LPC4357FET180 is not set +# CONFIG_ARCH_CHIP_LPC4357FBD208 is not set +# CONFIG_ARCH_CHIP_LPC4357FET256 is not set +# CONFIG_ARCH_CHIP_LPC4370FET100 is not set +CONFIG_ARCH_FAMILY_LPC4330=y +# CONFIG_LPC43_BOOT_SRAM is not set +CONFIG_LPC43_BOOT_SPIFI=y +# CONFIG_LPC43_BOOT_FLASHA is not set +# CONFIG_LPC43_BOOT_FLASHB is not set +# CONFIG_LPC43_BOOT_CS0FLASH is not set +# CONFIG_LPC43_BOOT_CS1FLASH is not set +# CONFIG_LPC43_BOOT_CS2FLASH is not set +# CONFIG_LPC43_BOOT_CS3FLASH is not set + +# +# LPC43xx Peripheral Support +# +# CONFIG_LPC43_ADC0 is not set +# CONFIG_LPC43_ADC1 is not set +# CONFIG_LPC43_ATIMER is not set +# CONFIG_LPC43_CAN1 is not set +# CONFIG_LPC43_CAN2 is not set +# CONFIG_LPC43_DAC is not set +# CONFIG_LPC43_EMC is not set +# CONFIG_LPC43_ETHERNET is not set +# CONFIG_LPC43_EVNTMNTR is not set +# CONFIG_LPC43_GPDMA is not set +# CONFIG_LPC43_I2C0 is not set +# CONFIG_LPC43_I2C1 is not set +# CONFIG_LPC43_I2S0 is not set +# CONFIG_LPC43_I2S1 is not set +# CONFIG_LPC43_LCD is not set +# CONFIG_LPC43_MCPWM is not set +# CONFIG_LPC43_QEI is not set +# CONFIG_LPC43_RIT is not set +# CONFIG_LPC43_RTC is not set +# CONFIG_LPC43_SCT is not set +# CONFIG_LPC43_SDMMC is not set +# CONFIG_LPC43_SPI is not set +# CONFIG_LPC43_SPIFI is not set +# CONFIG_LPC43_SSP0 is not set +# CONFIG_LPC43_SSP1 is not set +# CONFIG_LPC43_TMR0 is not set +# CONFIG_LPC43_TMR1 is not set +# CONFIG_LPC43_TMR2 is not set +# CONFIG_LPC43_TMR3 is not set +# CONFIG_LPC43_USART0 is not set +CONFIG_LPC43_UART1=y +# CONFIG_LPC43_USART2 is not set +# CONFIG_LPC43_USART3 is not set +# CONFIG_LPC43_USBOTG is not set +CONFIG_LPC43_USB0=y +# CONFIG_LPC43_USB1 is not set +# CONFIG_LPC43_WWDT is not set +# CONFIG_LPC43_GPIO_IRQ is not set + +# +# Internal Memory Configuration +# +CONFIG_ARCH_HAVE_AHB_SRAM_BANK1=y +# CONFIG_LPC43_USE_LOCSRAM_BANK1 is not set +# CONFIG_LPC43_USE_AHBSRAM_BANK0 is not set +# CONFIG_LPC43_USE_AHBSRAM_BANK1 is not set +# CONFIG_LPC43_HEAP_AHBSRAM_BANK2 is not set + +# +# External Memory Configuration +# + +# +# RS-485 Configuration +# +# CONFIG_UART1_RS485MODE is not set +# CONFIG_UART1_RS485_DTRDIR is not set + +# +# USB device controller driver (DCD) options +# +# CONFIG_LPC43_USB0DEV_NOVBUS is not set + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=18535 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x10000000 +CONFIG_RAM_SIZE=131072 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_BAMBINO_200E=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="bambino-200e" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +# CONFIG_ARCH_BUTTONS is not set +CONFIG_ARCH_HAVE_IRQBUTTONS=y + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_RESET is not set +# CONFIG_BOARDCTL_UNIQUEID is not set +CONFIG_BOARDCTL_USBDEVCTRL=y +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_ADCTEST is not set +# CONFIG_BOARDCTL_PWMTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Clocks and Timers +# +CONFIG_ARCH_HAVE_TICKLESS=y +# CONFIG_SCHED_TICKLESS is not set +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2012 +CONFIG_START_MONTH=7 +CONFIG_START_DAY=11 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=0 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_HPWORK is not set +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +# CONFIG_DISABLE_POLL is not set +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +# CONFIG_ARCH_HAVE_I2CRESET is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +CONFIG_SERIAL_REMOVABLE=y +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +CONFIG_UART1_SERIALDRIVER=y +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_SERIAL_NPOLLWAITERS=2 +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +CONFIG_UART1_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART1 Configuration +# +CONFIG_UART1_RXBUFSIZE=256 +CONFIG_UART1_TXBUFSIZE=256 +CONFIG_UART1_BAUD=115200 +CONFIG_UART1_BITS=8 +CONFIG_UART1_PARITY=0 +CONFIG_UART1_2STOP=0 +# CONFIG_UART1_IFLOWCONTROL is not set +# CONFIG_UART1_OFLOWCONTROL is not set +# CONFIG_UART1_DMA is not set +# CONFIG_PSEUDOTERM is not set +CONFIG_USBDEV=y + +# +# USB Device Controller Driver Options +# +# CONFIG_USBDEV_ISOCHRONOUS is not set +# CONFIG_USBDEV_DUALSPEED is not set +CONFIG_USBDEV_SELFPOWERED=y +# CONFIG_USBDEV_BUSPOWERED is not set +CONFIG_USBDEV_MAXPOWER=100 +# CONFIG_USBDEV_DMA is not set +# CONFIG_ARCH_USBDEV_STALLQUEUE is not set +# CONFIG_USBDEV_TRACE is not set + +# +# USB Device Class Driver Options +# +# CONFIG_USBDEV_COMPOSITE is not set +# CONFIG_PL2303 is not set +CONFIG_CDCACM=y +# CONFIG_CDCACM_CONSOLE is not set +CONFIG_CDCACM_EP0MAXPACKET=64 +CONFIG_CDCACM_EPINTIN=1 +CONFIG_CDCACM_EPINTIN_FSSIZE=64 +CONFIG_CDCACM_EPINTIN_HSSIZE=64 +CONFIG_CDCACM_EPBULKOUT=3 +CONFIG_CDCACM_EPBULKOUT_FSSIZE=64 +CONFIG_CDCACM_EPBULKOUT_HSSIZE=512 +CONFIG_CDCACM_EPBULKIN=2 +CONFIG_CDCACM_EPBULKIN_FSSIZE=64 +CONFIG_CDCACM_EPBULKIN_HSSIZE=512 +CONFIG_CDCACM_NRDREQS=4 +CONFIG_CDCACM_NWRREQS=4 +CONFIG_CDCACM_BULKIN_REQLEN=96 +CONFIG_CDCACM_RXBUFSIZE=257 +CONFIG_CDCACM_TXBUFSIZE=193 +CONFIG_CDCACM_VENDORID=0x0525 +CONFIG_CDCACM_PRODUCTID=0xa4a7 +CONFIG_CDCACM_VENDORSTR="NuttX" +CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial" +# CONFIG_USBMSC is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +CONFIG_FS_READABLE=y +CONFIG_FS_WRITABLE=y +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +CONFIG_FS_FAT=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=32 +# CONFIG_FS_FATTIME is not set +# CONFIG_FAT_FORCE_INDIRECT is not set +# CONFIG_FAT_DMAMEMORY is not set +# CONFIG_FAT_DIRECT_RETRY is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=2 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +CONFIG_SYMTAB_ORDEREDBYNAME=y + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_LIBC_TMPDIR="/tmp" +CONFIG_LIBC_MAX_TMPFILE=32 +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set +# CONFIG_LIBC_NETDB is not set +# CONFIG_NETDB_HOSTFILE is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +# CONFIG_CXX_NEWLONG is not set +CONFIG_CXX_LINK_GNUTOOL_LIB=y + +# +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_CXXTEST is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FSTEST is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HELLOXX is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NSH_CXXINITIALIZE is not set +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set +# CONFIG_FSUTILS_PASSWD is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_BAS is not set +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CHAT is not set +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=64 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +CONFIG_NSH_CMDPARMS=y +CONFIG_NSH_MAXARGUMENTS=6 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFATFS is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Configure Command Options +# +CONFIG_NSH_CMDOPT_DF_H=y +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_CMDOPT_HEXDUMP=y +CONFIG_NSH_FILEIOSIZE=512 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_USBCONSOLE is not set +# CONFIG_NSH_ALTCONDEV is not set +CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +CONFIG_SYSTEM_CDCACM=y +CONFIG_SYSTEM_CDCACM_DEVMINOR=1 +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/bambino-200e/gnutoolcpp/setenv.sh b/configs/bambino-200e/gnutoolcpp/setenv.sh new file mode 100644 index 0000000000..600b6c5f72 --- /dev/null +++ b/configs/bambino-200e/gnutoolcpp/setenv.sh @@ -0,0 +1,92 @@ +#!/bin/bash +# configs/bambino-200e/nsh/setenv.sh +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# Alan Carvalho de Assis +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the Code Red +# toolchain under windows. You will have to edit this if you install the +# Code Red toolchain in any other location or if you install a different +# version +export TOOLCHAIN_BIN="/cygdrive/c/code_red/RedSuite_4.2.3_379/redsuite/Tools/bin" +#export SCRIPT_BIN="/cygdrive/c/code_red/RedSuite_4.2.3_379/redsuite/bin" +export SCRIPT_BIN="/cygdrive/c/nxp/LPCXpresso_4.2.3_292/lpcxpresso/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +#export SCRIPT_BIN= + +# These are the Cygwin paths to the locations where I installed the Atollic +# toolchain under windows. You will also have to edit this if you install +# the Atollic toolchain in any other location. /usr/bin is added before +# the Atollic bin path because there is are binaries named gcc.exe and g++.exe +# at those locations as well. +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" +#export SCRIPT_BIN= + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +#export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" +#export SCRIPT_BIN= + +# And add the selected toolchain path[s] to the PATH variable + +export PATH="/sbin:/usr/sbin:${PATH_ORIG}" + +if [ ! -z ${SCRIPT_BIN} ]; then + export PATH="${SCRIPT_BIN}:${PATH}" +fi + +export PATH="${TOOLCHAIN_BIN}:${PATH}" +echo "PATH : ${PATH}" + +# Set an alias that can be used to put the LPC43xx in boot mode + +alias lpc43xx='${SCRIPT_BIN}/Scripts/bootLPCXpresso.cmd winusb' diff --git a/configs/samv71-xult/nsh/defconfig b/configs/samv71-xult/nsh/defconfig index b135609f71..a35e82a9b8 100644 --- a/configs/samv71-xult/nsh/defconfig +++ b/configs/samv71-xult/nsh/defconfig @@ -69,6 +69,7 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -528,15 +529,15 @@ CONFIG_I2C_RESET=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y # CONFIG_SPI_CS_CONTROL is not set -# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set # CONFIG_SPI_BITBANG is not set @@ -877,6 +878,7 @@ CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set diff --git a/include/cxx/cwchar b/include/cxx/cwchar index 67716abbe0..847eb98c47 100755 --- a/include/cxx/cwchar +++ b/include/cxx/cwchar @@ -48,7 +48,7 @@ namespace std { -#if 0 /* Not defined */ +#if __cplusplus >= 201103L using ::mbstate_t; #endif using ::wint_t; diff --git a/libxx/Kconfig b/libxx/Kconfig index 4707bb8715..03871c3f1a 100644 --- a/libxx/Kconfig +++ b/libxx/Kconfig @@ -38,6 +38,14 @@ config CXX_NEWLONG C++ library routines because the NuttX size_t might not have the same underlying type as your toolchain's size_t. +config CXX_LINK_GNUTOOL_LIB + bool "Link to GNU Toolchain Libraries" + default n + depends on ARM_TOOLCHAIN_GNU + ---help--- + This option enable NuttX build system to link with GNU Toolchain + libraries. Mainly stdlib++ and newlib nano. + comment "uClibc++ Standard C++ Library" config UCLIBCXX -- GitLab From 8190e089489cbd6117f5fd0522171ab3fdda4662 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 08:57:55 -0600 Subject: [PATCH 306/734] Back out part of previous commit --- arch/arm/src/Makefile | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/arm/src/Makefile b/arch/arm/src/Makefile index b182a97e7e..e505b956da 100644 --- a/arch/arm/src/Makefile +++ b/arch/arm/src/Makefile @@ -168,14 +168,6 @@ endif LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" GCC_LIBDIR := ${shell dirname $(LIBGCC)} -ifeq ($(CONFIG_CXX_LINK_GNUTOOL_LIB),y) - LIBGXX = "${shell "$(CXX)" $(ARCHCPUFLAGS) -print-file-name=$(LIBSTDCXX)}" - GXX_LIBDIR := ${shell dirname $(LIBGXX)} - LIBCXXPATH = -L"$(GXX_LIBDIR)" -else - LIBCXXPATH ?= -endif - VPATH += chip VPATH += common VPATH += $(ARCH_SUBDIR) @@ -209,9 +201,9 @@ board$(DELIM)libboard$(LIBEXT): nuttx$(EXEEXT): $(HEAD_OBJ) board$(DELIM)libboard$(LIBEXT) $(Q) echo "LD: nuttx" - $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(LIBCXXPATH) $(EXTRA_LIBPATHS) \ + $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ -o $(NUTTX) $(HEAD_OBJ) $(EXTRA_OBJS) \ - $(LDSTARTGROUP) $(LDLIBS) $(LDLIBSCXX) $(EXTRA_LIBS) $(LIBGCC) $(LDENDGROUP) + $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) $(LDENDGROUP) ifneq ($(CONFIG_WINDOWS_NATIVE),y) $(Q) $(NM) $(NUTTX) | \ grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ -- GitLab From ea9ac4417188179d9f5f7247f4da40938ac4be7b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 09:06:24 -0600 Subject: [PATCH 307/734] Move CONFIG_CXX_LINK_GNUTOOL_LIB from libxx/Kconfig to configs/bambino-200e/Kconfig --- configs/bambino-200e/Kconfig | 9 +++++++++ libxx/Kconfig | 8 -------- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/configs/bambino-200e/Kconfig b/configs/bambino-200e/Kconfig index 3892c96da7..dba37f0c0f 100644 --- a/configs/bambino-200e/Kconfig +++ b/configs/bambino-200e/Kconfig @@ -4,4 +4,13 @@ # if ARCH_BOARD_BAMBINO_200E + +config CXX_LINK_GNUTOOL_LIB + bool "Link to GNU Toolchain Libraries" + default n + depends on ARM_TOOLCHAIN_GNU + ---help--- + This option enable NuttX build system to link with GNU Toolchain + libraries. Mainly stdlib++ and newlib nano. + endif diff --git a/libxx/Kconfig b/libxx/Kconfig index 03871c3f1a..4707bb8715 100644 --- a/libxx/Kconfig +++ b/libxx/Kconfig @@ -38,14 +38,6 @@ config CXX_NEWLONG C++ library routines because the NuttX size_t might not have the same underlying type as your toolchain's size_t. -config CXX_LINK_GNUTOOL_LIB - bool "Link to GNU Toolchain Libraries" - default n - depends on ARM_TOOLCHAIN_GNU - ---help--- - This option enable NuttX build system to link with GNU Toolchain - libraries. Mainly stdlib++ and newlib nano. - comment "uClibc++ Standard C++ Library" config UCLIBCXX -- GitLab From 96aba62fdac4c05c713c19740a4080afb29a26e8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 09:15:30 -0600 Subject: [PATCH 308/734] bambino-200e: Add EXTRA_LIBS and EXTRA_LIBPATHS to nsh/Make.defs --- configs/bambino-200e/nsh/Make.defs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/configs/bambino-200e/nsh/Make.defs b/configs/bambino-200e/nsh/Make.defs index 105969c6b1..ea9aafb4d6 100644 --- a/configs/bambino-200e/nsh/Make.defs +++ b/configs/bambino-200e/nsh/Make.defs @@ -117,6 +117,12 @@ OBJEXT = .o LIBEXT = .a EXEEXT = +ifeq ($(CONFIG_CXX_LINK_GNUTOOL_LIB),y) + EXTRA_LIBS = "${shell "$(CXX)" $(ARCHCPUFLAGS) -print-file-name=$(LIBSTDCXX)}" + GXX_LIBDIR := ${shell dirname $(LIBGXX)} + EXTRA_LIBPATHS = -L"$(GXX_LIBDIR)" +endif + ifneq ($(CROSSDEV),arm-nuttx-elf-) LDFLAGS += -nostartfiles -nodefaultlibs endif -- GitLab From 77caf4180f8809dbc425ff2c20544333ff29583b Mon Sep 17 00:00:00 2001 From: "Spahlinger, Michael" Date: Thu, 3 Nov 2016 09:22:33 -0600 Subject: [PATCH 309/734] SAMV7: Fix to SPI-Master driver. Without this the chip select decoding feature will not work properly --- arch/arm/src/samv7/sam_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c index 06c18b70f1..959a3cd290 100644 --- a/arch/arm/src/samv7/sam_spi.c +++ b/arch/arm/src/samv7/sam_spi.c @@ -626,7 +626,7 @@ static inline uint32_t spi_cs2pcs(struct sam_spics_s *spics) #ifndef CONFIG_SAMV7_SPI_CS_DECODING return ((uint32_t)1 << (spics->cs)) - 1; #else - return spics->cs; + return spics->cs - 1; #endif } -- GitLab From de30c2e5ddc78f1a44b85fcddf1339a96f893af3 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 09:41:38 -0600 Subject: [PATCH 310/734] Back out the rest of commit 1e754402b86e10c28ada5949d33c8b759ab463fb. Newlib support will not be accepted into the NuttX repository. --- configs/bambino-200e/Kconfig | 8 - configs/bambino-200e/gnutoolcpp/Make.defs | 141 --- configs/bambino-200e/gnutoolcpp/defconfig | 1004 --------------------- configs/bambino-200e/gnutoolcpp/setenv.sh | 92 -- include/cxx/cwchar | 2 +- 5 files changed, 1 insertion(+), 1246 deletions(-) delete mode 100644 configs/bambino-200e/gnutoolcpp/Make.defs delete mode 100644 configs/bambino-200e/gnutoolcpp/defconfig delete mode 100644 configs/bambino-200e/gnutoolcpp/setenv.sh diff --git a/configs/bambino-200e/Kconfig b/configs/bambino-200e/Kconfig index dba37f0c0f..12ce8d77f5 100644 --- a/configs/bambino-200e/Kconfig +++ b/configs/bambino-200e/Kconfig @@ -5,12 +5,4 @@ if ARCH_BOARD_BAMBINO_200E -config CXX_LINK_GNUTOOL_LIB - bool "Link to GNU Toolchain Libraries" - default n - depends on ARM_TOOLCHAIN_GNU - ---help--- - This option enable NuttX build system to link with GNU Toolchain - libraries. Mainly stdlib++ and newlib nano. - endif diff --git a/configs/bambino-200e/gnutoolcpp/Make.defs b/configs/bambino-200e/gnutoolcpp/Make.defs deleted file mode 100644 index a7d6e8d274..0000000000 --- a/configs/bambino-200e/gnutoolcpp/Make.defs +++ /dev/null @@ -1,141 +0,0 @@ -############################################################################ -# configs/bambino-200e/nsh/Make.defs -# -# Copyright (C) 2016 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# Alan Carvalho de Assis -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk -include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs - -# Setup for the kind of memory that we are executing from - -ifeq ($(CONFIG_LPC43_BOOT_SRAM),y) - LDSCRIPT = ramconfig.ld -endif -ifeq ($(CONFIG_LPC43_BOOT_SPIFI),y) - LDSCRIPT = spificonfig.ld -endif -ifeq ($(CONFIG_LPC43_BOOT_FLASHA),y) - LDSCRIPT = flashaconfig.ld -endif -ifeq ($(CONFIG_LPC43_BOOT_FLASHB),y) - LDSCRIPT = flashaconfig.ld -endif -ifeq ($(CONFIG_LPC43_BOOT_CS0FLASH),y) - LDSCRIPT = cs0flash.ld -endif - -# Setup for Windows vs Linux/Cygwin/OSX environments - -ifeq ($(WINTOOL),y) - # Windows-native toolchains - DIRLINK = $(TOPDIR)/tools/copydir.sh - DIRUNLINK = $(TOPDIR)/tools/unlink.sh - MKDEP = $(TOPDIR)/tools/mkwindeps.sh - ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" - ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" - ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" -else - # Linux/Cygwin-native toolchain - MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) - ARCHINCLUDES = -I. -isystem $(TOPDIR)/include - ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx - ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) -endif - -CC = $(CROSSDEV)gcc -CXX = $(CROSSDEV)g++ -CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld -AR = $(ARCROSSDEV)ar rcs -NM = $(ARCROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} -ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION = -g -endif - -ifneq ($(CONFIG_DEBUG_NOOPT),y) - ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer -endif - -ARCHCFLAGS = -fno-builtin -ifeq ($(CONFIG_CXX_LINK_GNUTOOL_LIB),y) -ARCHCXXFLAGS = -fno-builtin -fno-use-cxa-atexit -fcheck-new -specs=nano.specs -lstdc++ -lsupc++ -lm -lgcc -lc -lnosys -std=gnu++11 -else -ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti -endif -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -ARCHWARNINGSXX = -Wall -Wshadow -Wundef -ARCHDEFINES = -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -AFLAGS = $(CFLAGS) -D__ASSEMBLY__ - -ifeq ($(CONFIG_CXX_LINK_GNUTOOL_LIB),y) -LDLIBSCXX = -lstdc++_nano -lsupc++_nano -lnosys -lm -LIBSTDCXX = libstdc++_nano.a -endif - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -ASMEXT = .S -OBJEXT = .o -LIBEXT = .a -EXEEXT = - -ifneq ($(CROSSDEV),arm-nuttx-elf-) - LDFLAGS += -nostartfiles -nodefaultlibs --no-wchar-size-warning -endif -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - LDFLAGS += -g -endif - - -HOSTCC = gcc -HOSTINCLUDES = -I. -HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe -HOSTLDFLAGS = - diff --git a/configs/bambino-200e/gnutoolcpp/defconfig b/configs/bambino-200e/gnutoolcpp/defconfig deleted file mode 100644 index 1c7bbf0c87..0000000000 --- a/configs/bambino-200e/gnutoolcpp/defconfig +++ /dev/null @@ -1,1004 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Nuttx/ Configuration -# - -# -# Build Setup -# -# CONFIG_EXPERIMENTAL is not set -# CONFIG_DEFAULT_SMALL is not set -CONFIG_HOST_LINUX=y -# CONFIG_HOST_OSX is not set -# CONFIG_HOST_WINDOWS is not set -# CONFIG_HOST_OTHER is not set - -# -# Build Configuration -# -# CONFIG_APPS_DIR="../apps" -CONFIG_BUILD_FLAT=y -# CONFIG_BUILD_2PASS is not set - -# -# Binary Output Formats -# -# CONFIG_RRLOAD_BINARY is not set -# CONFIG_INTELHEX_BINARY is not set -# CONFIG_MOTOROLA_SREC is not set -CONFIG_RAW_BINARY=y -# CONFIG_UBOOT_UIMAGE is not set - -# -# Customize Header Files -# -# CONFIG_ARCH_STDINT_H is not set -# CONFIG_ARCH_STDBOOL_H is not set -# CONFIG_ARCH_MATH_H is not set -# CONFIG_ARCH_FLOAT_H is not set -CONFIG_ARCH_STDARG_H=y -# CONFIG_ARCH_DEBUG_H is not set - -# -# Debug Options -# -CONFIG_DEBUG_ALERT=y -# CONFIG_DEBUG_FEATURES is not set -CONFIG_ARCH_HAVE_STACKCHECK=y -# CONFIG_STACK_COLORATION is not set -# CONFIG_ARCH_HAVE_HEAPCHECK is not set -CONFIG_DEBUG_SYMBOLS=y -CONFIG_ARCH_HAVE_CUSTOMOPT=y -CONFIG_DEBUG_NOOPT=y -# CONFIG_DEBUG_CUSTOMOPT is not set -# CONFIG_DEBUG_FULLOPT is not set - -# -# System Type -# -CONFIG_ARCH_ARM=y -# CONFIG_ARCH_AVR is not set -# CONFIG_ARCH_HC is not set -# CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set -# CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_RISCV is not set -# CONFIG_ARCH_SIM is not set -# CONFIG_ARCH_X86 is not set -# CONFIG_ARCH_XTENSA is not set -# CONFIG_ARCH_Z16 is not set -# CONFIG_ARCH_Z80 is not set -CONFIG_ARCH="arm" - -# -# ARM Options -# -# CONFIG_ARCH_CHIP_A1X is not set -# CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set -# CONFIG_ARCH_CHIP_DM320 is not set -# CONFIG_ARCH_CHIP_EFM32 is not set -# CONFIG_ARCH_CHIP_IMX1 is not set -# CONFIG_ARCH_CHIP_IMX6 is not set -# CONFIG_ARCH_CHIP_KINETIS is not set -# CONFIG_ARCH_CHIP_KL is not set -# CONFIG_ARCH_CHIP_LM is not set -# CONFIG_ARCH_CHIP_TIVA is not set -# CONFIG_ARCH_CHIP_LPC11XX is not set -# CONFIG_ARCH_CHIP_LPC17XX is not set -# CONFIG_ARCH_CHIP_LPC214X is not set -# CONFIG_ARCH_CHIP_LPC2378 is not set -# CONFIG_ARCH_CHIP_LPC31XX is not set -CONFIG_ARCH_CHIP_LPC43XX=y -# CONFIG_ARCH_CHIP_NUC1XX is not set -# CONFIG_ARCH_CHIP_SAMA5 is not set -# CONFIG_ARCH_CHIP_SAMD is not set -# CONFIG_ARCH_CHIP_SAML is not set -# CONFIG_ARCH_CHIP_SAM34 is not set -# CONFIG_ARCH_CHIP_SAMV7 is not set -# CONFIG_ARCH_CHIP_STM32 is not set -# CONFIG_ARCH_CHIP_STM32F7 is not set -# CONFIG_ARCH_CHIP_STM32L4 is not set -# CONFIG_ARCH_CHIP_STR71X is not set -# CONFIG_ARCH_CHIP_TMS570 is not set -# CONFIG_ARCH_CHIP_MOXART is not set -# CONFIG_ARCH_ARM7TDMI is not set -# CONFIG_ARCH_ARM926EJS is not set -# CONFIG_ARCH_ARM920T is not set -# CONFIG_ARCH_CORTEXM0 is not set -# CONFIG_ARCH_CORTEXM3 is not set -CONFIG_ARCH_CORTEXM4=y -# CONFIG_ARCH_CORTEXM7 is not set -# CONFIG_ARCH_CORTEXA5 is not set -# CONFIG_ARCH_CORTEXA8 is not set -# CONFIG_ARCH_CORTEXA9 is not set -# CONFIG_ARCH_CORTEXR4 is not set -# CONFIG_ARCH_CORTEXR4F is not set -# CONFIG_ARCH_CORTEXR5 is not set -# CONFIG_ARCH_CORTEX5F is not set -# CONFIG_ARCH_CORTEXR7 is not set -# CONFIG_ARCH_CORTEXR7F is not set -CONFIG_ARCH_FAMILY="armv7-m" -CONFIG_ARCH_CHIP="lpc43xx" -# CONFIG_ARM_TOOLCHAIN_IAR is not set -CONFIG_ARM_TOOLCHAIN_GNU=y -# CONFIG_ARMV7M_USEBASEPRI is not set -CONFIG_ARCH_HAVE_CMNVECTOR=y -CONFIG_ARMV7M_CMNVECTOR=y -# CONFIG_ARMV7M_LAZYFPU is not set -CONFIG_ARCH_HAVE_FPU=y -# CONFIG_ARCH_HAVE_DPFPU is not set -# CONFIG_ARCH_FPU is not set -# CONFIG_ARCH_HAVE_TRUSTZONE is not set -CONFIG_ARM_HAVE_MPU_UNIFIED=y -# CONFIG_ARM_MPU is not set - -# -# ARMV7M Configuration Options -# -# CONFIG_ARMV7M_HAVE_ICACHE is not set -# CONFIG_ARMV7M_HAVE_DCACHE is not set -# CONFIG_ARMV7M_HAVE_ITCM is not set -# CONFIG_ARMV7M_HAVE_DTCM is not set -# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set -# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set -# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set -# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set -CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y -# CONFIG_ARMV7M_HAVE_STACKCHECK is not set -# CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_SERIAL_TERMIOS is not set - -# -# LPC43xx Configuration Options -# -# CONFIG_ARCH_CHIP_LPC4310FBD144 is not set -# CONFIG_ARCH_CHIP_LPC4310FET100 is not set -# CONFIG_ARCH_CHIP_LPC4320FBD144 is not set -# CONFIG_ARCH_CHIP_LPC4320FET100 is not set -CONFIG_ARCH_CHIP_LPC4330FBD144=y -# CONFIG_ARCH_CHIP_LPC4330FET100 is not set -# CONFIG_ARCH_CHIP_LPC4330FET180 is not set -# CONFIG_ARCH_CHIP_LPC4330FET256 is not set -# CONFIG_ARCH_CHIP_LPC4337JBD144 is not set -# CONFIG_ARCH_CHIP_LPC4337JET100 is not set -# CONFIG_ARCH_CHIP_LPC4350FBD208 is not set -# CONFIG_ARCH_CHIP_LPC4350FET180 is not set -# CONFIG_ARCH_CHIP_LPC4350FET256 is not set -# CONFIG_ARCH_CHIP_LPC4353FBD208 is not set -# CONFIG_ARCH_CHIP_LPC4353FET180 is not set -# CONFIG_ARCH_CHIP_LPC4353FET256 is not set -# CONFIG_ARCH_CHIP_LPC4357FET180 is not set -# CONFIG_ARCH_CHIP_LPC4357FBD208 is not set -# CONFIG_ARCH_CHIP_LPC4357FET256 is not set -# CONFIG_ARCH_CHIP_LPC4370FET100 is not set -CONFIG_ARCH_FAMILY_LPC4330=y -# CONFIG_LPC43_BOOT_SRAM is not set -CONFIG_LPC43_BOOT_SPIFI=y -# CONFIG_LPC43_BOOT_FLASHA is not set -# CONFIG_LPC43_BOOT_FLASHB is not set -# CONFIG_LPC43_BOOT_CS0FLASH is not set -# CONFIG_LPC43_BOOT_CS1FLASH is not set -# CONFIG_LPC43_BOOT_CS2FLASH is not set -# CONFIG_LPC43_BOOT_CS3FLASH is not set - -# -# LPC43xx Peripheral Support -# -# CONFIG_LPC43_ADC0 is not set -# CONFIG_LPC43_ADC1 is not set -# CONFIG_LPC43_ATIMER is not set -# CONFIG_LPC43_CAN1 is not set -# CONFIG_LPC43_CAN2 is not set -# CONFIG_LPC43_DAC is not set -# CONFIG_LPC43_EMC is not set -# CONFIG_LPC43_ETHERNET is not set -# CONFIG_LPC43_EVNTMNTR is not set -# CONFIG_LPC43_GPDMA is not set -# CONFIG_LPC43_I2C0 is not set -# CONFIG_LPC43_I2C1 is not set -# CONFIG_LPC43_I2S0 is not set -# CONFIG_LPC43_I2S1 is not set -# CONFIG_LPC43_LCD is not set -# CONFIG_LPC43_MCPWM is not set -# CONFIG_LPC43_QEI is not set -# CONFIG_LPC43_RIT is not set -# CONFIG_LPC43_RTC is not set -# CONFIG_LPC43_SCT is not set -# CONFIG_LPC43_SDMMC is not set -# CONFIG_LPC43_SPI is not set -# CONFIG_LPC43_SPIFI is not set -# CONFIG_LPC43_SSP0 is not set -# CONFIG_LPC43_SSP1 is not set -# CONFIG_LPC43_TMR0 is not set -# CONFIG_LPC43_TMR1 is not set -# CONFIG_LPC43_TMR2 is not set -# CONFIG_LPC43_TMR3 is not set -# CONFIG_LPC43_USART0 is not set -CONFIG_LPC43_UART1=y -# CONFIG_LPC43_USART2 is not set -# CONFIG_LPC43_USART3 is not set -# CONFIG_LPC43_USBOTG is not set -CONFIG_LPC43_USB0=y -# CONFIG_LPC43_USB1 is not set -# CONFIG_LPC43_WWDT is not set -# CONFIG_LPC43_GPIO_IRQ is not set - -# -# Internal Memory Configuration -# -CONFIG_ARCH_HAVE_AHB_SRAM_BANK1=y -# CONFIG_LPC43_USE_LOCSRAM_BANK1 is not set -# CONFIG_LPC43_USE_AHBSRAM_BANK0 is not set -# CONFIG_LPC43_USE_AHBSRAM_BANK1 is not set -# CONFIG_LPC43_HEAP_AHBSRAM_BANK2 is not set - -# -# External Memory Configuration -# - -# -# RS-485 Configuration -# -# CONFIG_UART1_RS485MODE is not set -# CONFIG_UART1_RS485_DTRDIR is not set - -# -# USB device controller driver (DCD) options -# -# CONFIG_LPC43_USB0DEV_NOVBUS is not set - -# -# Architecture Options -# -# CONFIG_ARCH_NOINTC is not set -# CONFIG_ARCH_VECNOTIRQ is not set -# CONFIG_ARCH_DMA is not set -CONFIG_ARCH_HAVE_IRQPRIO=y -# CONFIG_ARCH_L2CACHE is not set -# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set -# CONFIG_ARCH_HAVE_ADDRENV is not set -# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set -# CONFIG_ARCH_HAVE_MULTICPU is not set -CONFIG_ARCH_HAVE_VFORK=y -# CONFIG_ARCH_HAVE_MMU is not set -CONFIG_ARCH_HAVE_MPU=y -# CONFIG_ARCH_NAND_HWECC is not set -# CONFIG_ARCH_HAVE_EXTCLK is not set -# CONFIG_ARCH_HAVE_POWEROFF is not set -CONFIG_ARCH_HAVE_RESET=y -# CONFIG_ARCH_USE_MPU is not set -# CONFIG_ARCH_IRQPRIO is not set -CONFIG_ARCH_STACKDUMP=y -# CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_IDLE_CUSTOM is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set -CONFIG_ARCH_HAVE_RAMVECTORS=y -# CONFIG_ARCH_RAMVECTORS is not set - -# -# Board Settings -# -CONFIG_BOARD_LOOPSPERMSEC=18535 -# CONFIG_ARCH_CALIBRATION is not set - -# -# Interrupt options -# -CONFIG_ARCH_HAVE_INTERRUPTSTACK=y -CONFIG_ARCH_INTERRUPTSTACK=0 -CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y -# CONFIG_ARCH_HIPRI_INTERRUPT is not set - -# -# Boot options -# -# CONFIG_BOOT_RUNFROMEXTSRAM is not set -CONFIG_BOOT_RUNFROMFLASH=y -# CONFIG_BOOT_RUNFROMISRAM is not set -# CONFIG_BOOT_RUNFROMSDRAM is not set -# CONFIG_BOOT_COPYTORAM is not set - -# -# Boot Memory Configuration -# -CONFIG_RAM_START=0x10000000 -CONFIG_RAM_SIZE=131072 -# CONFIG_ARCH_HAVE_SDRAM is not set - -# -# Board Selection -# -CONFIG_ARCH_BOARD_BAMBINO_200E=y -# CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD="bambino-200e" - -# -# Common Board Options -# -CONFIG_ARCH_HAVE_LEDS=y -CONFIG_ARCH_LEDS=y -CONFIG_ARCH_HAVE_BUTTONS=y -# CONFIG_ARCH_BUTTONS is not set -CONFIG_ARCH_HAVE_IRQBUTTONS=y - -# -# Board-Specific Options -# -# CONFIG_BOARD_CRASHDUMP is not set -CONFIG_LIB_BOARDCTL=y -# CONFIG_BOARDCTL_RESET is not set -# CONFIG_BOARDCTL_UNIQUEID is not set -CONFIG_BOARDCTL_USBDEVCTRL=y -# CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set -# CONFIG_BOARDCTL_GRAPHICS is not set -# CONFIG_BOARDCTL_IOCTL is not set - -# -# RTOS Features -# -CONFIG_DISABLE_OS_API=y -# CONFIG_DISABLE_POSIX_TIMERS is not set -# CONFIG_DISABLE_PTHREAD is not set -# CONFIG_DISABLE_SIGNALS is not set -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_ENVIRON is not set - -# -# Clocks and Timers -# -CONFIG_ARCH_HAVE_TICKLESS=y -# CONFIG_SCHED_TICKLESS is not set -CONFIG_USEC_PER_TICK=10000 -# CONFIG_SYSTEM_TIME64 is not set -# CONFIG_CLOCK_MONOTONIC is not set -# CONFIG_ARCH_HAVE_TIMEKEEPING is not set -# CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2012 -CONFIG_START_MONTH=7 -CONFIG_START_DAY=11 -CONFIG_MAX_WDOGPARMS=2 -CONFIG_PREALLOC_WDOGS=4 -CONFIG_WDOG_INTRESERVE=0 -CONFIG_PREALLOC_TIMERS=4 - -# -# Tasks and Scheduling -# -# CONFIG_INIT_NONE is not set -CONFIG_INIT_ENTRYPOINT=y -# CONFIG_INIT_FILEPATH is not set -CONFIG_USER_ENTRYPOINT="nsh_main" -CONFIG_RR_INTERVAL=200 -# CONFIG_SCHED_SPORADIC is not set -CONFIG_TASK_NAME_SIZE=0 -CONFIG_MAX_TASKS=16 -# CONFIG_SCHED_HAVE_PARENT is not set -CONFIG_SCHED_WAITPID=y - -# -# Pthread Options -# -# CONFIG_MUTEX_TYPES is not set -CONFIG_NPTHREAD_KEYS=4 - -# -# Performance Monitoring -# -# CONFIG_SCHED_CPULOAD is not set -# CONFIG_SCHED_INSTRUMENTATION is not set - -# -# Files and I/O -# -CONFIG_DEV_CONSOLE=y -# CONFIG_FDCLONE_DISABLE is not set -# CONFIG_FDCLONE_STDIO is not set -CONFIG_SDCLONE_DISABLE=y -CONFIG_NFILE_DESCRIPTORS=8 -CONFIG_NFILE_STREAMS=8 -CONFIG_NAME_MAX=32 -# CONFIG_PRIORITY_INHERITANCE is not set - -# -# RTOS hooks -# -# CONFIG_BOARD_INITIALIZE is not set -# CONFIG_SCHED_STARTHOOK is not set -# CONFIG_SCHED_ATEXIT is not set -# CONFIG_SCHED_ONEXIT is not set - -# -# Signal Numbers -# -CONFIG_SIG_SIGUSR1=1 -CONFIG_SIG_SIGUSR2=2 -CONFIG_SIG_SIGALARM=3 -CONFIG_SIG_SIGCONDTIMEDOUT=16 - -# -# POSIX Message Queue Options -# -CONFIG_PREALLOC_MQ_MSGS=4 -CONFIG_MQ_MAXMSGSIZE=32 -# CONFIG_MODULE is not set - -# -# Work queue support -# -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set -# CONFIG_SCHED_LPWORK is not set - -# -# Stack and heap information -# -CONFIG_IDLETHREAD_STACKSIZE=1024 -CONFIG_USERMAIN_STACKSIZE=2048 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=2048 -# CONFIG_LIB_SYSCALL is not set - -# -# Device Drivers -# -# CONFIG_DISABLE_POLL is not set -CONFIG_DEV_NULL=y -# CONFIG_DEV_ZERO is not set -# CONFIG_DEV_URANDOM is not set -# CONFIG_DEV_LOOP is not set - -# -# Buffering -# -# CONFIG_DRVR_WRITEBUFFER is not set -# CONFIG_DRVR_READAHEAD is not set -# CONFIG_RAMDISK is not set -# CONFIG_CAN is not set -# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set -# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set -# CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set -# CONFIG_I2C is not set -# CONFIG_SPI is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -# CONFIG_ARCH_HAVE_SPI_BITORDER is not set -# CONFIG_I2S is not set - -# -# Timer Driver Support -# -# CONFIG_TIMER is not set -# CONFIG_ONESHOT is not set -# CONFIG_RTC is not set -# CONFIG_WATCHDOG is not set -# CONFIG_ANALOG is not set -# CONFIG_AUDIO_DEVICES is not set -# CONFIG_VIDEO_DEVICES is not set -# CONFIG_BCH is not set -# CONFIG_INPUT is not set - -# -# IO Expander/GPIO Support -# -# CONFIG_IOEXPANDER is not set -# CONFIG_DEV_GPIO is not set - -# -# LCD Driver Support -# -# CONFIG_LCD is not set -# CONFIG_SLCD is not set - -# -# LED Support -# -# CONFIG_USERLED is not set -# CONFIG_RGBLED is not set -# CONFIG_PCA9635PW is not set -# CONFIG_NCP5623C is not set -# CONFIG_MMCSD is not set -# CONFIG_MODEM is not set -# CONFIG_MTD is not set -# CONFIG_EEPROM is not set -# CONFIG_PIPES is not set -# CONFIG_PM is not set -# CONFIG_POWER is not set -# CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set -CONFIG_SERIAL=y -# CONFIG_DEV_LOWCONSOLE is not set -CONFIG_SERIAL_REMOVABLE=y -CONFIG_SERIAL_CONSOLE=y -# CONFIG_16550_UART is not set -# CONFIG_UART_SERIALDRIVER is not set -# CONFIG_UART0_SERIALDRIVER is not set -CONFIG_UART1_SERIALDRIVER=y -# CONFIG_UART2_SERIALDRIVER is not set -# CONFIG_UART3_SERIALDRIVER is not set -# CONFIG_UART4_SERIALDRIVER is not set -# CONFIG_UART5_SERIALDRIVER is not set -# CONFIG_UART6_SERIALDRIVER is not set -# CONFIG_UART7_SERIALDRIVER is not set -# CONFIG_UART8_SERIALDRIVER is not set -# CONFIG_SCI0_SERIALDRIVER is not set -# CONFIG_SCI1_SERIALDRIVER is not set -# CONFIG_USART0_SERIALDRIVER is not set -# CONFIG_USART1_SERIALDRIVER is not set -# CONFIG_USART2_SERIALDRIVER is not set -# CONFIG_USART3_SERIALDRIVER is not set -# CONFIG_USART4_SERIALDRIVER is not set -# CONFIG_USART5_SERIALDRIVER is not set -# CONFIG_USART6_SERIALDRIVER is not set -# CONFIG_USART7_SERIALDRIVER is not set -# CONFIG_USART8_SERIALDRIVER is not set -# CONFIG_OTHER_UART_SERIALDRIVER is not set -CONFIG_MCU_SERIAL=y -CONFIG_STANDARD_SERIAL=y -CONFIG_SERIAL_NPOLLWAITERS=2 -# CONFIG_SERIAL_IFLOWCONTROL is not set -# CONFIG_SERIAL_OFLOWCONTROL is not set -# CONFIG_SERIAL_DMA is not set -CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y -CONFIG_UART1_SERIAL_CONSOLE=y -# CONFIG_OTHER_SERIAL_CONSOLE is not set -# CONFIG_NO_SERIAL_CONSOLE is not set - -# -# UART1 Configuration -# -CONFIG_UART1_RXBUFSIZE=256 -CONFIG_UART1_TXBUFSIZE=256 -CONFIG_UART1_BAUD=115200 -CONFIG_UART1_BITS=8 -CONFIG_UART1_PARITY=0 -CONFIG_UART1_2STOP=0 -# CONFIG_UART1_IFLOWCONTROL is not set -# CONFIG_UART1_OFLOWCONTROL is not set -# CONFIG_UART1_DMA is not set -# CONFIG_PSEUDOTERM is not set -CONFIG_USBDEV=y - -# -# USB Device Controller Driver Options -# -# CONFIG_USBDEV_ISOCHRONOUS is not set -# CONFIG_USBDEV_DUALSPEED is not set -CONFIG_USBDEV_SELFPOWERED=y -# CONFIG_USBDEV_BUSPOWERED is not set -CONFIG_USBDEV_MAXPOWER=100 -# CONFIG_USBDEV_DMA is not set -# CONFIG_ARCH_USBDEV_STALLQUEUE is not set -# CONFIG_USBDEV_TRACE is not set - -# -# USB Device Class Driver Options -# -# CONFIG_USBDEV_COMPOSITE is not set -# CONFIG_PL2303 is not set -CONFIG_CDCACM=y -# CONFIG_CDCACM_CONSOLE is not set -CONFIG_CDCACM_EP0MAXPACKET=64 -CONFIG_CDCACM_EPINTIN=1 -CONFIG_CDCACM_EPINTIN_FSSIZE=64 -CONFIG_CDCACM_EPINTIN_HSSIZE=64 -CONFIG_CDCACM_EPBULKOUT=3 -CONFIG_CDCACM_EPBULKOUT_FSSIZE=64 -CONFIG_CDCACM_EPBULKOUT_HSSIZE=512 -CONFIG_CDCACM_EPBULKIN=2 -CONFIG_CDCACM_EPBULKIN_FSSIZE=64 -CONFIG_CDCACM_EPBULKIN_HSSIZE=512 -CONFIG_CDCACM_NRDREQS=4 -CONFIG_CDCACM_NWRREQS=4 -CONFIG_CDCACM_BULKIN_REQLEN=96 -CONFIG_CDCACM_RXBUFSIZE=257 -CONFIG_CDCACM_TXBUFSIZE=193 -CONFIG_CDCACM_VENDORID=0x0525 -CONFIG_CDCACM_PRODUCTID=0xa4a7 -CONFIG_CDCACM_VENDORSTR="NuttX" -CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial" -# CONFIG_USBMSC is not set -# CONFIG_USBHOST is not set -# CONFIG_HAVE_USBTRACE is not set -# CONFIG_DRIVERS_WIRELESS is not set -# CONFIG_DRIVERS_CONTACTLESS is not set - -# -# System Logging -# -# CONFIG_ARCH_SYSLOG is not set -# CONFIG_RAMLOG is not set -# CONFIG_SYSLOG_INTBUFFER is not set -# CONFIG_SYSLOG_TIMESTAMP is not set -CONFIG_SYSLOG_SERIAL_CONSOLE=y -# CONFIG_SYSLOG_CHAR is not set -CONFIG_SYSLOG_CONSOLE=y -# CONFIG_SYSLOG_NONE is not set -# CONFIG_SYSLOG_FILE is not set -# CONFIG_SYSLOG_CHARDEV is not set - -# -# Networking Support -# -# CONFIG_ARCH_HAVE_NET is not set -# CONFIG_ARCH_HAVE_PHY is not set -# CONFIG_NET is not set - -# -# Crypto API -# -# CONFIG_CRYPTO is not set - -# -# File Systems -# - -# -# File system configuration -# -# CONFIG_DISABLE_MOUNTPOINT is not set -# CONFIG_FS_AUTOMOUNTER is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -CONFIG_FS_READABLE=y -CONFIG_FS_WRITABLE=y -# CONFIG_FS_NAMED_SEMAPHORES is not set -CONFIG_FS_MQUEUE_MPATH="/var/mqueue" -# CONFIG_FS_RAMMAP is not set -CONFIG_FS_FAT=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FAT_MAXFNAME=32 -# CONFIG_FS_FATTIME is not set -# CONFIG_FAT_FORCE_INDIRECT is not set -# CONFIG_FAT_DMAMEMORY is not set -# CONFIG_FAT_DIRECT_RETRY is not set -# CONFIG_FS_NXFFS is not set -# CONFIG_FS_ROMFS is not set -# CONFIG_FS_TMPFS is not set -# CONFIG_FS_SMARTFS is not set -# CONFIG_FS_BINFS is not set -# CONFIG_FS_PROCFS is not set -# CONFIG_FS_UNIONFS is not set - -# -# Graphics Support -# -# CONFIG_NX is not set - -# -# Memory Management -# -# CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=2 -# CONFIG_ARCH_HAVE_HEAP2 is not set -# CONFIG_GRAN is not set - -# -# Audio Support -# -# CONFIG_AUDIO is not set - -# -# Wireless Support -# - -# -# Binary Loader -# -# CONFIG_BINFMT_DISABLE is not set -# CONFIG_BINFMT_EXEPATH is not set -# CONFIG_NXFLAT is not set -# CONFIG_ELF is not set -CONFIG_BUILTIN=y -# CONFIG_PIC is not set -CONFIG_SYMTAB_ORDEREDBYNAME=y - -# -# Library Routines -# - -# -# Standard C Library Options -# -CONFIG_STDIO_BUFFER_SIZE=64 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=2 -CONFIG_LIB_HOMEDIR="/" -# CONFIG_LIBM is not set -# CONFIG_NOPRINTF_FIELDWIDTH is not set -# CONFIG_LIBC_FLOATINGPOINT is not set -CONFIG_LIBC_LONG_LONG=y -# CONFIG_LIBC_IOCTL_VARIADIC is not set -# CONFIG_LIBC_WCHAR is not set -# CONFIG_LIBC_LOCALE is not set -CONFIG_LIB_RAND_ORDER=1 -# CONFIG_EOL_IS_CR is not set -# CONFIG_EOL_IS_LF is not set -# CONFIG_EOL_IS_BOTH_CRLF is not set -CONFIG_EOL_IS_EITHER_CRLF=y -# CONFIG_LIBC_EXECFUNCS is not set -CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 -# CONFIG_LIBC_STRERROR is not set -# CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_LIBC_TMPDIR="/tmp" -CONFIG_LIBC_MAX_TMPFILE=32 -CONFIG_ARCH_LOWPUTC=y -# CONFIG_LIBC_LOCALTIME is not set -# CONFIG_TIME_EXTENDED is not set -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set -# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set -CONFIG_ARCH_HAVE_TLS=y -# CONFIG_TLS is not set -# CONFIG_LIBC_NETDB is not set -# CONFIG_NETDB_HOSTFILE is not set - -# -# Non-standard Library Support -# -# CONFIG_LIB_CRC64_FAST is not set -# CONFIG_LIB_KBDCODEC is not set -# CONFIG_LIB_SLCDCODEC is not set -# CONFIG_LIB_HEX2BIN is not set - -# -# Basic CXX Support -# -# CONFIG_C99_BOOL8 is not set -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -# CONFIG_CXX_NEWLONG is not set -CONFIG_CXX_LINK_GNUTOOL_LIB=y - -# -# uClibc++ Standard C++ Library -# -# CONFIG_UCLIBCXX is not set - -# -# Application Configuration -# - -# -# Built-In Applications -# -CONFIG_BUILTIN_PROXY_STACKSIZE=1024 - -# -# CAN Utilities -# - -# -# Examples -# -# CONFIG_EXAMPLES_BUTTONS is not set -# CONFIG_EXAMPLES_CCTYPE is not set -# CONFIG_EXAMPLES_CHAT is not set -# CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CXXTEST is not set -# CONFIG_EXAMPLES_DHCPD is not set -# CONFIG_EXAMPLES_ELF is not set -# CONFIG_EXAMPLES_FSTEST is not set -# CONFIG_EXAMPLES_FTPC is not set -# CONFIG_EXAMPLES_FTPD is not set -# CONFIG_EXAMPLES_HELLO is not set -# CONFIG_EXAMPLES_HELLOXX is not set -# CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_IGMP is not set -# CONFIG_EXAMPLES_JSON is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set -# CONFIG_EXAMPLES_MEDIA is not set -# CONFIG_EXAMPLES_MM is not set -# CONFIG_EXAMPLES_MODBUS is not set -# CONFIG_EXAMPLES_MOUNT is not set -# CONFIG_EXAMPLES_NRF24L01TERM is not set -CONFIG_EXAMPLES_NSH=y -# CONFIG_EXAMPLES_NSH_CXXINITIALIZE is not set -# CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NXFFS is not set -# CONFIG_EXAMPLES_NXHELLO is not set -# CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXLINES is not set -# CONFIG_EXAMPLES_NXTERM is not set -# CONFIG_EXAMPLES_NXTEXT is not set -# CONFIG_EXAMPLES_OSTEST is not set -# CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_PPPD is not set -# CONFIG_EXAMPLES_RFID_READUID is not set -# CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set -# CONFIG_EXAMPLES_SENDMAIL is not set -# CONFIG_EXAMPLES_SERIALBLASTER is not set -# CONFIG_EXAMPLES_SERIALRX is not set -# CONFIG_EXAMPLES_SERLOOP is not set -# CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART is not set -# CONFIG_EXAMPLES_SMART_TEST is not set -# CONFIG_EXAMPLES_SMP is not set -# CONFIG_EXAMPLES_TCPECHO is not set -# CONFIG_EXAMPLES_TELNETD is not set -# CONFIG_EXAMPLES_TIFF is not set -# CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_USBSERIAL is not set -# CONFIG_EXAMPLES_USBTERM is not set -# CONFIG_EXAMPLES_WATCHDOG is not set -# CONFIG_EXAMPLES_WEBSERVER is not set - -# -# File System Utilities -# -# CONFIG_FSUTILS_INIFILE is not set -# CONFIG_FSUTILS_PASSWD is not set - -# -# GPS Utilities -# -# CONFIG_GPSUTILS_MINMEA_LIB is not set - -# -# Graphics Support -# -# CONFIG_TIFF is not set -# CONFIG_GRAPHICS_TRAVELER is not set - -# -# Interpreters -# -# CONFIG_INTERPRETERS_BAS is not set -# CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_MICROPYTHON is not set -# CONFIG_INTERPRETERS_MINIBASIC is not set -# CONFIG_INTERPRETERS_PCODE is not set - -# -# FreeModBus -# -# CONFIG_MODBUS is not set - -# -# Network Utilities -# -# CONFIG_NETUTILS_CHAT is not set -# CONFIG_NETUTILS_CODECS is not set -# CONFIG_NETUTILS_ESP8266 is not set -# CONFIG_NETUTILS_FTPC is not set -# CONFIG_NETUTILS_JSON is not set -# CONFIG_NETUTILS_SMTP is not set - -# -# NSH Library -# -CONFIG_NSH_LIBRARY=y -# CONFIG_NSH_MOTD is not set - -# -# Command Line Configuration -# -CONFIG_NSH_READLINE=y -# CONFIG_NSH_CLE is not set -CONFIG_NSH_LINELEN=64 -# CONFIG_NSH_DISABLE_SEMICOLON is not set -CONFIG_NSH_CMDPARMS=y -CONFIG_NSH_MAXARGUMENTS=6 -CONFIG_NSH_ARGCAT=y -CONFIG_NSH_NESTDEPTH=3 -# CONFIG_NSH_DISABLEBG is not set -CONFIG_NSH_BUILTIN_APPS=y - -# -# Disable Individual commands -# -# CONFIG_NSH_DISABLE_ADDROUTE is not set -# CONFIG_NSH_DISABLE_BASENAME is not set -# CONFIG_NSH_DISABLE_CAT is not set -# CONFIG_NSH_DISABLE_CD is not set -# CONFIG_NSH_DISABLE_CP is not set -# CONFIG_NSH_DISABLE_CMP is not set -CONFIG_NSH_DISABLE_DATE=y -# CONFIG_NSH_DISABLE_DD is not set -# CONFIG_NSH_DISABLE_DF is not set -# CONFIG_NSH_DISABLE_DELROUTE is not set -# CONFIG_NSH_DISABLE_DIRNAME is not set -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HELP is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -CONFIG_NSH_DISABLE_IFUPDOWN=y -# CONFIG_NSH_DISABLE_KILL is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -CONFIG_NSH_DISABLE_LOSMART=y -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_MB is not set -# CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_MH is not set -# CONFIG_NSH_DISABLE_MOUNT is not set -# CONFIG_NSH_DISABLE_MV is not set -# CONFIG_NSH_DISABLE_MW is not set -CONFIG_NSH_DISABLE_PRINTF=y -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_PWD is not set -# CONFIG_NSH_DISABLE_RM is not set -# CONFIG_NSH_DISABLE_RMDIR is not set -# CONFIG_NSH_DISABLE_SET is not set -# CONFIG_NSH_DISABLE_SH is not set -# CONFIG_NSH_DISABLE_SLEEP is not set -# CONFIG_NSH_DISABLE_TIME is not set -# CONFIG_NSH_DISABLE_TEST is not set -# CONFIG_NSH_DISABLE_UMOUNT is not set -# CONFIG_NSH_DISABLE_UNAME is not set -# CONFIG_NSH_DISABLE_UNSET is not set -# CONFIG_NSH_DISABLE_USLEEP is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_NSH_MMCSDMINOR=0 - -# -# Configure Command Options -# -CONFIG_NSH_CMDOPT_DF_H=y -CONFIG_NSH_CODECS_BUFSIZE=128 -CONFIG_NSH_CMDOPT_HEXDUMP=y -CONFIG_NSH_FILEIOSIZE=512 - -# -# Scripting Support -# -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_ITEF is not set -# CONFIG_NSH_DISABLE_LOOPS is not set - -# -# Console Configuration -# -CONFIG_NSH_CONSOLE=y -# CONFIG_NSH_USBCONSOLE is not set -# CONFIG_NSH_ALTCONDEV is not set -CONFIG_NSH_ARCHINIT=y -# CONFIG_NSH_LOGIN is not set -# CONFIG_NSH_CONSOLE_LOGIN is not set - -# -# NxWidgets/NxWM -# - -# -# Platform-specific Support -# -# CONFIG_PLATFORM_CONFIGDATA is not set - -# -# System Libraries and NSH Add-Ons -# -CONFIG_SYSTEM_CDCACM=y -CONFIG_SYSTEM_CDCACM_DEVMINOR=1 -# CONFIG_SYSTEM_CLE is not set -# CONFIG_SYSTEM_CUTERM is not set -# CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set -# CONFIG_SYSTEM_HEXED is not set -# CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_RAMTEST is not set -CONFIG_READLINE_HAVE_EXTMATCH=y -CONFIG_SYSTEM_READLINE=y -CONFIG_READLINE_ECHO=y -# CONFIG_READLINE_TABCOMPLETION is not set -# CONFIG_READLINE_CMD_HISTORY is not set -# CONFIG_SYSTEM_SUDOKU is not set -# CONFIG_SYSTEM_SYSTEM is not set -# CONFIG_SYSTEM_TEE is not set -# CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_VI is not set -# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/bambino-200e/gnutoolcpp/setenv.sh b/configs/bambino-200e/gnutoolcpp/setenv.sh deleted file mode 100644 index 600b6c5f72..0000000000 --- a/configs/bambino-200e/gnutoolcpp/setenv.sh +++ /dev/null @@ -1,92 +0,0 @@ -#!/bin/bash -# configs/bambino-200e/nsh/setenv.sh -# -# Copyright (C) 2016 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# Alan Carvalho de Assis -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if [ "$_" = "$0" ] ; then - echo "You must source this script, not run it!" 1>&2 - exit 1 -fi - -WD=`pwd` -if [ ! -x "setenv.sh" ]; then - echo "This script must be executed from the top-level NuttX build directory" - exit 1 -fi - -if [ -z "${PATH_ORIG}" ]; then - export PATH_ORIG="${PATH}" -fi - -# This is the Cygwin path to the location where I installed the Code Red -# toolchain under windows. You will have to edit this if you install the -# Code Red toolchain in any other location or if you install a different -# version -export TOOLCHAIN_BIN="/cygdrive/c/code_red/RedSuite_4.2.3_379/redsuite/Tools/bin" -#export SCRIPT_BIN="/cygdrive/c/code_red/RedSuite_4.2.3_379/redsuite/bin" -export SCRIPT_BIN="/cygdrive/c/nxp/LPCXpresso_4.2.3_292/lpcxpresso/bin" - -# This is the Cygwin path to the location where I installed the CodeSourcery -# toolchain under windows. You will also have to edit this if you install -# the CodeSourcery toolchain in any other location -#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" -#export SCRIPT_BIN= - -# These are the Cygwin paths to the locations where I installed the Atollic -# toolchain under windows. You will also have to edit this if you install -# the Atollic toolchain in any other location. /usr/bin is added before -# the Atollic bin path because there is are binaries named gcc.exe and g++.exe -# at those locations as well. -#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" -#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" -#export SCRIPT_BIN= - -# This is the Cygwin path to the location where I build the buildroot -# toolchain. -#export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" -#export SCRIPT_BIN= - -# And add the selected toolchain path[s] to the PATH variable - -export PATH="/sbin:/usr/sbin:${PATH_ORIG}" - -if [ ! -z ${SCRIPT_BIN} ]; then - export PATH="${SCRIPT_BIN}:${PATH}" -fi - -export PATH="${TOOLCHAIN_BIN}:${PATH}" -echo "PATH : ${PATH}" - -# Set an alias that can be used to put the LPC43xx in boot mode - -alias lpc43xx='${SCRIPT_BIN}/Scripts/bootLPCXpresso.cmd winusb' diff --git a/include/cxx/cwchar b/include/cxx/cwchar index 847eb98c47..7c29791570 100755 --- a/include/cxx/cwchar +++ b/include/cxx/cwchar @@ -48,7 +48,7 @@ namespace std { -#if __cplusplus >= 201103L +#if 0 // Not defined using ::mbstate_t; #endif using ::wint_t; -- GitLab From bdde5720ca9ee245b6b13bc50baa57582b4f616a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 09:43:27 -0600 Subject: [PATCH 311/734] Back out the rest of commit 1e754402b86e10c28ada5949d33c8b759ab463fb. Newlib support will not be accepted into the NuttX repository. --- configs/bambino-200e/nsh/Make.defs | 6 ------ 1 file changed, 6 deletions(-) diff --git a/configs/bambino-200e/nsh/Make.defs b/configs/bambino-200e/nsh/Make.defs index ea9aafb4d6..105969c6b1 100644 --- a/configs/bambino-200e/nsh/Make.defs +++ b/configs/bambino-200e/nsh/Make.defs @@ -117,12 +117,6 @@ OBJEXT = .o LIBEXT = .a EXEEXT = -ifeq ($(CONFIG_CXX_LINK_GNUTOOL_LIB),y) - EXTRA_LIBS = "${shell "$(CXX)" $(ARCHCPUFLAGS) -print-file-name=$(LIBSTDCXX)}" - GXX_LIBDIR := ${shell dirname $(LIBGXX)} - EXTRA_LIBPATHS = -L"$(GXX_LIBDIR)" -endif - ifneq ($(CROSSDEV),arm-nuttx-elf-) LDFLAGS += -nostartfiles -nodefaultlibs endif -- GitLab From 4fcbe8e4104f5d82e72f31b9ce256cf65f652f6b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 11:00:47 -0600 Subject: [PATCH 312/734] drivers: Disable priority inheritance on all semaphores used for signaling --- drivers/analog/adc.c | 9 +++++++++ drivers/analog/dac.c | 11 ++++++++++- drivers/can.c | 10 +++++++++- drivers/input/ads7843e.c | 9 +++++++++ drivers/input/max11802.c | 9 +++++++++ drivers/input/mxt.c | 9 +++++++++ drivers/net/slip.c | 4 +++- drivers/net/tun.c | 8 +++++++- drivers/pipes/pipe_common.c | 16 ++++++++++++---- drivers/pwm.c | 12 ++++++++++-- drivers/sercomm/console.c | 4 ++++ drivers/serial/pty.c | 10 ++++++++++ drivers/serial/serial.c | 2 +- drivers/syslog/ramlog.c | 13 ++++++++++--- drivers/usbdev/usbmsc.c | 12 +++++++++++- drivers/usbhost/usbhost_hidkbd.c | 13 +++++++++++++ drivers/usbhost/usbhost_hidmouse.c | 13 +++++++++++++ drivers/wireless/cc3000/cc3000.c | 20 +++++++++++++++++++- drivers/wireless/ieee802154/mrf24j40.c | 11 +++++++++++ drivers/wireless/nrf24l01.c | 4 +++- 20 files changed, 182 insertions(+), 17 deletions(-) diff --git a/drivers/analog/adc.c b/drivers/analog/adc.c index 0dac979d60..d81971f101 100644 --- a/drivers/analog/adc.c +++ b/drivers/analog/adc.c @@ -58,6 +58,7 @@ #include #include +#include #include #include @@ -441,9 +442,17 @@ int adc_register(FAR const char *path, FAR struct adc_dev_s *dev) dev->ad_ocount = 0; + /* Initialize semaphores */ + sem_init(&dev->ad_recv.af_sem, 0, 0); sem_init(&dev->ad_closesem, 0, 1); + /* The receive semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&dev->ad_recv.af_sem, SEM_PRIO_NONE); + /* Reset the ADC hardware */ DEBUGASSERT(dev->ad_ops->ao_reset != NULL); diff --git a/drivers/analog/dac.c b/drivers/analog/dac.c index fbbc761833..131b7e800f 100644 --- a/drivers/analog/dac.c +++ b/drivers/analog/dac.c @@ -55,8 +55,9 @@ #include #include -#include #include +#include +#include #include #include @@ -515,9 +516,17 @@ int dac_register(FAR const char *path, FAR struct dac_dev_s *dev) dev->ad_ocount = 0; + /* Initialize semaphores */ + sem_init(&dev->ad_xmit.af_sem, 0, 0); sem_init(&dev->ad_closesem, 0, 1); + /* The transmit semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&dev->ad_xmit.af_sem, SEM_PRIO_NONE); + dev->ad_ops->ao_reset(dev); return register_driver(path, &dac_fops, 0555, dev); diff --git a/drivers/can.c b/drivers/can.c index 483769d7db..e896d492f4 100644 --- a/drivers/can.c +++ b/drivers/can.c @@ -54,8 +54,9 @@ #include #include -#include #include +#include +#include #include #ifdef CONFIG_CAN_TXREADY @@ -1166,6 +1167,8 @@ int can_register(FAR const char *path, FAR struct can_dev_s *dev) dev->cd_error = 0; #endif + /* Initialize semaphores */ + sem_init(&dev->cd_xmit.tx_sem, 0, 1); sem_init(&dev->cd_recv.rx_sem, 0, 1); sem_init(&dev->cd_closesem, 0, 1); @@ -1175,7 +1178,12 @@ int can_register(FAR const char *path, FAR struct can_dev_s *dev) for (i = 0; i < CONFIG_CAN_NPENDINGRTR; i++) { + /* Initialize wait semahores. These semaphores are used for signaling + * and should not have priority inheritance enabled. + */ + sem_init(&dev->cd_rtr[i].cr_sem, 0, 0); + sem_setprotocol(&dev->cd_rtr[i].cr_sem, SEM_PRIO_NONE); dev->cd_rtr[i].cr_msg = NULL; } diff --git a/drivers/input/ads7843e.c b/drivers/input/ads7843e.c index 5f4c159a9f..f7019639de 100644 --- a/drivers/input/ads7843e.c +++ b/drivers/input/ads7843e.c @@ -71,6 +71,7 @@ #include #include +#include #include #include @@ -1184,9 +1185,17 @@ int ads7843e_register(FAR struct spi_dev_s *spi, priv->threshx = INVALID_THRESHOLD; /* Initialize thresholding logic */ priv->threshy = INVALID_THRESHOLD; /* Initialize thresholding logic */ + /* Initialize semaphores */ + sem_init(&priv->devsem, 0, 1); /* Initialize device structure semaphore */ sem_init(&priv->waitsem, 0, 0); /* Initialize pen event wait semaphore */ + /* The pen event semaphore is used for signaling and, hence, should not + * have priority inheritance enabled. + */ + + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); + /* Make sure that interrupts are disabled */ config->clear(config); diff --git a/drivers/input/max11802.c b/drivers/input/max11802.c index 2394cd2e5e..82ad1f6689 100644 --- a/drivers/input/max11802.c +++ b/drivers/input/max11802.c @@ -65,6 +65,7 @@ #include #include +#include #include #include @@ -1187,9 +1188,17 @@ int max11802_register(FAR struct spi_dev_s *spi, priv->threshx = INVALID_THRESHOLD; /* Initialize thresholding logic */ priv->threshy = INVALID_THRESHOLD; /* Initialize thresholding logic */ + /* Initialize semaphores */ + sem_init(&priv->devsem, 0, 1); /* Initialize device structure semaphore */ sem_init(&priv->waitsem, 0, 0); /* Initialize pen event wait semaphore */ + /* The pen event semaphore is used for signaling and, hence, should not + * have priority inheritance enabled. + */ + + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); + /* Make sure that interrupts are disabled */ config->clear(config); diff --git a/drivers/input/mxt.c b/drivers/input/mxt.c index 891f781120..5d617ba764 100644 --- a/drivers/input/mxt.c +++ b/drivers/input/mxt.c @@ -65,6 +65,7 @@ #include #include +#include #include #include @@ -1884,9 +1885,17 @@ int mxt_register(FAR struct i2c_master_s *i2c, priv->i2c = i2c; /* Save the SPI device handle */ priv->lower = lower; /* Save the board configuration */ + /* Initialize semaphores */ + sem_init(&priv->devsem, 0, 1); /* Initialize device semaphore */ sem_init(&priv->waitsem, 0, 0); /* Initialize event wait semaphore */ + /* The event wait semaphore is used for signaling and, hence, should not + * have priority inheritance enabled. + */ + + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); + /* Make sure that interrupts are disabled */ MXT_CLEAR(lower); diff --git a/drivers/net/slip.c b/drivers/net/slip.c index 07fac24fc3..744126971e 100644 --- a/drivers/net/slip.c +++ b/drivers/net/slip.c @@ -55,8 +55,9 @@ #include #include -#include #include +#include +#include #include #include #include @@ -965,6 +966,7 @@ int slip_initialize(int intf, FAR const char *devname) /* Initialize the wait semaphore */ sem_init(&priv->waitsem, 0, 0); + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); /* Put the interface in the down state. This usually amounts to resetting * the device and/or calling slip_ifdown(). diff --git a/drivers/net/tun.c b/drivers/net/tun.c index d14fb7ed28..b4938c4e50 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -884,11 +884,17 @@ static int tun_dev_init(FAR struct tun_device_s *priv, FAR struct file *filep, #endif priv->dev.d_private = (FAR void *)priv; /* Used to recover private state from dev */ - /* Initialize the wait semaphore */ + /* Initialize the mutual exlcusion and wait semaphore */ sem_init(&priv->waitsem, 0, 1); sem_init(&priv->read_wait_sem, 0, 0); + /* The wait semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->read_wait_sem, SEM_PRIO_NONE); + /* Create a watchdog for timing polling for and timing of transmisstions */ priv->txpoll = wd_create(); /* Create periodic poll timer */ diff --git a/drivers/pipes/pipe_common.c b/drivers/pipes/pipe_common.c index 730e0228de..6fc0711dcf 100644 --- a/drivers/pipes/pipe_common.c +++ b/drivers/pipes/pipe_common.c @@ -1,7 +1,7 @@ /**************************************************************************** * drivers/pipes/pipe_common.c * - * Copyright (C) 2008-2009, 2011, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2008-2009, 2011, 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -53,12 +53,13 @@ #include #include -#include -#include -#include #ifdef CONFIG_DEBUG_FEATURES # include #endif +#include +#include +#include +#include #include "pipe_common.h" @@ -172,6 +173,13 @@ FAR struct pipe_dev_s *pipecommon_allocdev(size_t bufsize) sem_init(&dev->d_rdsem, 0, 0); sem_init(&dev->d_wrsem, 0, 0); + /* The read/write wait semaphores are used for signaling and, hence, + * should not have priority inheritance enabled. + */ + + sem_setprotocol(&dev->d_rdsem, SEM_PRIO_NONE); + sem_setprotocol(&dev->d_wrsem, SEM_PRIO_NONE); + dev->d_bufsize = bufsize; } diff --git a/drivers/pwm.c b/drivers/pwm.c index f3de79a387..03958b6778 100644 --- a/drivers/pwm.c +++ b/drivers/pwm.c @@ -1,7 +1,7 @@ /**************************************************************************** * drivers/pwm.c * - * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -55,9 +55,10 @@ #include #include +#include #include +#include #include -#include #include #include @@ -601,7 +602,14 @@ int pwm_register(FAR const char *path, FAR struct pwm_lowerhalf_s *dev) sem_init(&upper->exclsem, 0, 1); #ifdef CONFIG_PWM_PULSECOUNT sem_init(&upper->waitsem, 0, 0); + + /* The wait semaphore is used for signaling and, hence, should not have priority + * inheritance enabled. + */ + + sem_setprotocol(&upper->waitsem, SEM_PRIO_NONE); #endif + upper->dev = dev; /* Register the PWM device */ diff --git a/drivers/sercomm/console.c b/drivers/sercomm/console.c index c12c35af5f..efd1174ba3 100644 --- a/drivers/sercomm/console.c +++ b/drivers/sercomm/console.c @@ -47,6 +47,7 @@ #include #include "uart.h" +#include #include /************************************************************************************ @@ -187,6 +188,9 @@ int sercomm_register(FAR const char *path, FAR uart_dev_t *dev) sem_init(&dev->pollsem, 0, 1); #endif + sem_setprotocol(&dev->xmitsem, SEM_PRIO_NONE); + sem_setprotocol(&dev->recvsem, SEM_PRIO_NONE); + _info("Registering %s\n", path); return register_driver(path, &g_sercom_console_ops, 0666, NULL); } diff --git a/drivers/serial/pty.c b/drivers/serial/pty.c index 03c844b5f9..4c27cd89bb 100644 --- a/drivers/serial/pty.c +++ b/drivers/serial/pty.c @@ -97,6 +97,7 @@ #include #include +#include #include #include #include @@ -1016,8 +1017,17 @@ int pty_register(int minor) return -ENOMEM; } + /* Initialize semaphores */ + sem_init(&devpair->pp_slavesem, 0, 0); sem_init(&devpair->pp_exclsem, 0, 1); + + /* The pp_slavesem semaphore is used for signaling and, hence, should not + * have priority inheritance enabled. + */ + + sem_setprotocol(&devpair->pp_slavesem, SEM_PRIO_NONE); + #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS devpair->pp_minor = minor; #endif diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 64354e2a76..80c6fa3f1a 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -1413,7 +1413,7 @@ int uart_register(FAR const char *path, FAR uart_dev_t *dev) #endif /* The recvsem and xmitsem are used for signaling and, hence, should not have - * priroity inheritance enabled. + * priority inheritance enabled. */ sem_setprotocol(&dev->xmitsem, SEM_PRIO_NONE); diff --git a/drivers/syslog/ramlog.c b/drivers/syslog/ramlog.c index 6044b7157b..d322710433 100644 --- a/drivers/syslog/ramlog.c +++ b/drivers/syslog/ramlog.c @@ -1,7 +1,7 @@ /**************************************************************************** * drivers/syslog/ramlog.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -53,10 +53,10 @@ #include #include -#include +#include #include +#include #include -#include #include #include @@ -694,7 +694,14 @@ int ramlog_register(FAR const char *devpath, FAR char *buffer, size_t buflen) sem_init(&priv->rl_exclsem, 0, 1); #ifndef CONFIG_RAMLOG_NONBLOCKING sem_init(&priv->rl_waitsem, 0, 0); + + /* The rl_waitsem semaphore is used for signaling and, hence, should + * not have priority inheritance enabled. + */ + + sem_setprotocol(&priv->rl_waitsem, SEM_PRIO_NONE); #endif + priv->rl_bufsize = buflen; priv->rl_buffer = buffer; diff --git a/drivers/usbdev/usbmsc.c b/drivers/usbdev/usbmsc.c index 35fc5cf5a3..c83febb011 100644 --- a/drivers/usbdev/usbmsc.c +++ b/drivers/usbdev/usbmsc.c @@ -75,6 +75,7 @@ #include #include #include +#include #include #include #include @@ -1339,11 +1340,20 @@ int usbmsc_configure(unsigned int nluns, void **handle) priv = &alloc->dev; memset(priv, 0, sizeof(struct usbmsc_dev_s)); + /* Initialize semaphores */ + sem_init(&priv->thsynch, 0, 0); sem_init(&priv->thlock, 0, 1); sem_init(&priv->thwaitsem, 0, 0); - sq_init(&priv->wrreqlist); + /* The thsynch and thwaitsem semaphores are used for signaling and, hence, + * should not have priority inheritance enabled. + */ + + sem_setprotocol(&priv->thsynch, SEM_PRIO_NONE); + sem_setprotocol(&priv->thwaitsem, SEM_PRIO_NONE); + + sq_init(&priv->wrreqlist); priv->nluns = nluns; /* Allocate the LUN table */ diff --git a/drivers/usbhost/usbhost_hidkbd.c b/drivers/usbhost/usbhost_hidkbd.c index c8a3c582f7..6a5be0e9ba 100644 --- a/drivers/usbhost/usbhost_hidkbd.c +++ b/drivers/usbhost/usbhost_hidkbd.c @@ -60,6 +60,7 @@ #include #include #include +#include #include #include @@ -1864,6 +1865,12 @@ static FAR struct usbhost_class_s * sem_init(&priv->exclsem, 0, 1); sem_init(&priv->waitsem, 0, 0); + /* The waitsem semaphore is used for signaling and, hence, should + * not have priority inheritance enabled. + */ + + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); + /* Return the instance of the USB keyboard class driver */ return &priv->usbclass; @@ -2423,6 +2430,12 @@ int usbhost_kbdinit(void) sem_init(&g_exclsem, 0, 1); sem_init(&g_syncsem, 0, 0); + /* The g_syncsem semaphore is used for signaling and, hence, should not + * have priority inheritance enabled. + */ + + sem_setprotocol(&g_syncsem, SEM_PRIO_NONE); + /* Advertise our availability to support (certain) devices */ return usbhost_registerclass(&g_hidkbd); diff --git a/drivers/usbhost/usbhost_hidmouse.c b/drivers/usbhost/usbhost_hidmouse.c index 922e133c8b..dbd0033920 100644 --- a/drivers/usbhost/usbhost_hidmouse.c +++ b/drivers/usbhost/usbhost_hidmouse.c @@ -57,6 +57,7 @@ #include #include #include +#include #include #include @@ -1934,6 +1935,12 @@ static FAR struct usbhost_class_s * sem_init(&priv->exclsem, 0, 1); sem_init(&priv->waitsem, 0, 0); + /* The waitsem semaphore is used for signaling and, hence, should + * not have priority inheritance enabled. + */ + + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); + /* Return the instance of the USB mouse class driver */ return &priv->usbclass; @@ -2553,6 +2560,12 @@ int usbhost_mouse_init(void) sem_init(&g_exclsem, 0, 1); sem_init(&g_syncsem, 0, 0); + /* The g_syncsem semaphore is used for signaling and, hence, should not + * have priority inheritance enabled. + */ + + sem_setprotocol(&g_syncsem, SEM_PRIO_NONE); + /* Advertise our availability to support (certain) mouse devices */ return usbhost_registerclass(&g_hidmouse); diff --git a/drivers/wireless/cc3000/cc3000.c b/drivers/wireless/cc3000/cc3000.c index 6c0fb74828..2a651cd19c 100644 --- a/drivers/wireless/cc3000/cc3000.c +++ b/drivers/wireless/cc3000/cc3000.c @@ -63,13 +63,15 @@ #include #include +#include + #include #include #include #include +#include #include #include -#include #include #include @@ -822,19 +824,33 @@ static int cc3000_open(FAR struct file *filep) if (tmp == 1) { + /* Initialize semaphores */ + sem_init(&priv->waitsem, 0, 0); /* Initialize event wait semaphore */ sem_init(&priv->irqsem, 0, 0); /* Initialize IRQ Ready semaphore */ sem_init(&priv->readysem, 0, 0); /* Initialize Device Ready semaphore */ + /* These semaphores are all used for signaling and, hence, should + * not have priority inheritance enabled. + */ + + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); + sem_setprotocol(&priv->irqsem, SEM_PRIO_NONE); + sem_setprotocol(&priv->readysem, SEM_PRIO_NONE); + #ifdef CONFIG_CC3000_MT priv->accepting_socket.acc.sd = FREE_SLOT; sem_init(&priv->accepting_socket.acc.semwait, 0, 0); + sem_setprotocol(&priv->accepting_socket.acc.semwait, SEM_PRIO_NONE); + for (s = 0; s < CONFIG_WL_MAX_SOCKETS; s++) { priv->sockets[s].sd = FREE_SLOT; priv->sockets[s].received_closed_event = false; priv->sockets[s].emptied_and_remotely_closed = false; + sem_init(&priv->sockets[s].semwait, 0, 0); + sem_setprotocol(&priv->sockets[s].semwait, SEM_PRIO_NONE); } #endif @@ -884,6 +900,8 @@ static int cc3000_open(FAR struct file *filep) pthread_attr_setschedparam(&tattr, ¶m); sem_init(&priv->selectsem, 0, 0); + sem_setprotocol(&priv->selectsem, SEM_PRIO_NONE); + ret = pthread_create(&priv->selecttid, &tattr, select_thread_func, (pthread_addr_t)priv); if (ret != 0) diff --git a/drivers/wireless/ieee802154/mrf24j40.c b/drivers/wireless/ieee802154/mrf24j40.c index 77079fe468..9e216acabc 100644 --- a/drivers/wireless/ieee802154/mrf24j40.c +++ b/drivers/wireless/ieee802154/mrf24j40.c @@ -51,6 +51,7 @@ #include #include #include +#include #include #include @@ -1370,9 +1371,19 @@ FAR struct ieee802154_dev_s *mrf24j40_init(FAR struct spi_dev_s *spi, } dev->ieee.ops = &mrf24j40_devops; + + /* Initialize semaphores */ + sem_init(&dev->ieee.rxsem, 0, 0); sem_init(&dev->ieee.txsem, 0, 0); + /* These semaphores are all used for signaling and, hence, should + * not have priority inheritance enabled. + */ + + sem_setprotocol(&dev->ieee.rxsem, SEM_PRIO_NONE); + sem_setprotocol(&dev->ieee.txsem, SEM_PRIO_NONE); + dev->lower = lower; dev->spi = spi; diff --git a/drivers/wireless/nrf24l01.c b/drivers/wireless/nrf24l01.c index ff79034ad6..8b088e9857 100644 --- a/drivers/wireless/nrf24l01.c +++ b/drivers/wireless/nrf24l01.c @@ -1224,7 +1224,8 @@ int nrf24l01_register(FAR struct spi_dev_s *spi, FAR struct nrf24l01_config_s *c dev->pfd = NULL; #endif - sem_init(&(dev->sem_tx), 0, 0); + sem_init(&dev->sem_tx, 0, 0); + sem_setprotocol(&dev->sem_tx, SEM_PRIO_NONE); #ifdef CONFIG_WL_NRF24L01_RXSUPPORT if ((rx_fifo = kmm_malloc(CONFIG_WL_NRF24L01_RXFIFO_LEN)) == NULL) @@ -1240,6 +1241,7 @@ int nrf24l01_register(FAR struct spi_dev_s *spi, FAR struct nrf24l01_config_s *c sem_init(&(dev->sem_fifo), 0, 1); sem_init(&(dev->sem_rx), 0, 0); + sem_setprotocol(&dev->sem_rx, SEM_PRIO_NONE); #endif /* Set the global reference */ -- GitLab From 2d057c28c8e33a578b9b2bd82b5a1c9cf795a98f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 12:17:02 -0600 Subject: [PATCH 313/734] net: Disable priority inheritance on all semaphores used for signaling --- net/arp/arp_notify.c | 11 +++++++++-- net/arp/arp_send.c | 9 ++++++++- net/icmp/icmp_ping.c | 9 ++++++++- net/icmpv6/icmpv6_autoconfig.c | 8 +++++++- net/icmpv6/icmpv6_neighbor.c | 11 +++++++++-- net/icmpv6/icmpv6_notify.c | 11 +++++++++-- net/icmpv6/icmpv6_ping.c | 9 ++++++++- net/icmpv6/icmpv6_rnotify.c | 17 +++++++++++++++-- net/igmp/igmp_group.c | 9 ++++++++- net/local/local_conn.c | 10 +++++++++- net/pkt/pkt_send.c | 11 ++++++++++- net/socket/connect.c | 10 +++++++++- net/socket/net_close.c | 10 +++++++++- net/socket/net_sendfile.c | 11 +++++++++-- net/socket/recvfrom.c | 8 ++++++++ net/tcp/tcp_accept.c | 9 ++++++++- net/tcp/tcp_send_unbuffered.c | 9 +++++++++ net/udp/udp_psock_sendto.c | 8 ++++++++ 18 files changed, 160 insertions(+), 20 deletions(-) diff --git a/net/arp/arp_notify.c b/net/arp/arp_notify.c index 727d765651..7b92bfc25a 100644 --- a/net/arp/arp_notify.c +++ b/net/arp/arp_notify.c @@ -1,7 +1,7 @@ /**************************************************************************** * net/arp/arp_notify.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -47,8 +47,9 @@ #include -#include #include +#include +#include #include "arp/arp.h" @@ -88,7 +89,13 @@ void arp_wait_setup(in_addr_t ipaddr, FAR struct arp_notify_s *notify) notify->nt_ipaddr = ipaddr; notify->nt_result = -ETIMEDOUT; + + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + (void)sem_init(¬ify->nt_sem, 0, 0); + sem_setprotocol(¬ify->nt_sem, SEM_PRIO_NONE); /* Add the wait structure to the list with interrupts disabled */ diff --git a/net/arp/arp_send.c b/net/arp/arp_send.c index faec0a13f4..0a525c7d68 100644 --- a/net/arp/arp_send.c +++ b/net/arp/arp_send.c @@ -1,7 +1,7 @@ /**************************************************************************** * net/arp/arp_send.c * - * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2014-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -48,6 +48,7 @@ #include #include +#include #include #include #include @@ -294,7 +295,13 @@ int arp_send(in_addr_t ipaddr) * disabled */ + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + (void)sem_init(&state.snd_sem, 0, 0); /* Doesn't really fail */ + sem_setprotocol(&state.snd_sem, SEM_PRIO_NONE); + state.snd_retries = 0; /* No retries yet */ state.snd_ipaddr = ipaddr; /* IP address to query */ diff --git a/net/icmp/icmp_ping.c b/net/icmp/icmp_ping.c index a121ddfbbd..0c7f6e1627 100644 --- a/net/icmp/icmp_ping.c +++ b/net/icmp/icmp_ping.c @@ -1,7 +1,7 @@ /**************************************************************************** * net/icmp/icmp_ping.c * - * Copyright (C) 2008-2012, 2014-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2008-2012, 2014-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -51,6 +51,7 @@ #include #include +#include #include #include #include @@ -364,7 +365,13 @@ int icmp_ping(in_addr_t addr, uint16_t id, uint16_t seqno, uint16_t datalen, /* Initialize the state structure */ + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + sem_init(&state.png_sem, 0, 0); + sem_setprotocol(&state.png_sem, SEM_PRIO_NONE); + state.png_ticks = DSEC2TICK(dsecs); /* System ticks to wait */ state.png_result = -ENOMEM; /* Assume allocation failure */ state.png_addr = addr; /* Address of the peer to be ping'ed */ diff --git a/net/icmpv6/icmpv6_autoconfig.c b/net/icmpv6/icmpv6_autoconfig.c index eb404e7812..0e8fc688cd 100644 --- a/net/icmpv6/icmpv6_autoconfig.c +++ b/net/icmpv6/icmpv6_autoconfig.c @@ -1,7 +1,7 @@ /**************************************************************************** * net/icmpv6/icmpv6_autoconfig.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -47,6 +47,7 @@ #include +#include #include #include @@ -208,7 +209,12 @@ static int icmpv6_send_message(FAR struct net_driver_s *dev, bool advertise) * disabled */ + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + (void)sem_init(&state.snd_sem, 0, 0); /* Doesn't really fail */ + sem_setprotocol(&state.snd_sem, SEM_PRIO_NONE); #ifdef CONFIG_NETDEV_MULTINIC /* Remember the routing device name */ diff --git a/net/icmpv6/icmpv6_neighbor.c b/net/icmpv6/icmpv6_neighbor.c index 9bb02f34b4..60f63660bd 100644 --- a/net/icmpv6/icmpv6_neighbor.c +++ b/net/icmpv6/icmpv6_neighbor.c @@ -1,7 +1,7 @@ /**************************************************************************** * net/icmpv6/icmpv6_neighbor.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -48,6 +48,7 @@ #include #include +#include #include #include #include @@ -307,8 +308,14 @@ int icmpv6_neighbor(const net_ipv6addr_t ipaddr) * disabled */ + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + (void)sem_init(&state.snd_sem, 0, 0); /* Doesn't really fail */ - state.snd_retries = 0; /* No retries yet */ + sem_setprotocol(&state.snd_sem, SEM_PRIO_NONE); + + state.snd_retries = 0; /* No retries yet */ net_ipv6addr_copy(state.snd_ipaddr, lookup); /* IP address to query */ #ifdef CONFIG_NETDEV_MULTINIC diff --git a/net/icmpv6/icmpv6_notify.c b/net/icmpv6/icmpv6_notify.c index 4185b5a352..ad0ddbd8c1 100644 --- a/net/icmpv6/icmpv6_notify.c +++ b/net/icmpv6/icmpv6_notify.c @@ -1,7 +1,7 @@ /**************************************************************************** * net/icmpv6/icmpv6_notify.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -47,8 +47,9 @@ #include -#include #include +#include +#include #include "icmpv6/icmpv6.h" @@ -101,7 +102,13 @@ void icmpv6_wait_setup(const net_ipv6addr_t ipaddr, net_ipv6addr_copy(notify->nt_ipaddr, ipaddr); notify->nt_result = -ETIMEDOUT; + + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + (void)sem_init(¬ify->nt_sem, 0, 0); + sem_setprotocol(¬ify->nt_sem, SEM_PRIO_NONE); /* Add the wait structure to the list with interrupts disabled */ diff --git a/net/icmpv6/icmpv6_ping.c b/net/icmpv6/icmpv6_ping.c index 507d09a266..839ac06e07 100644 --- a/net/icmpv6/icmpv6_ping.c +++ b/net/icmpv6/icmpv6_ping.c @@ -1,7 +1,7 @@ /**************************************************************************** * net/icmpv6/icmpv6_ping.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -50,6 +50,7 @@ #include #include +#include #include #include #include @@ -437,7 +438,13 @@ int icmpv6_ping(net_ipv6addr_t addr, uint16_t id, uint16_t seqno, /* Initialize the state structure */ + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + sem_init(&state.png_sem, 0, 0); + sem_setprotocol(&state.png_sem, SEM_PRIO_NONE); + state.png_ticks = DSEC2TICK(dsecs); /* System ticks to wait */ state.png_result = -ENOMEM; /* Assume allocation failure */ state.png_id = id; /* The ID to use in the ECHO request */ diff --git a/net/icmpv6/icmpv6_rnotify.c b/net/icmpv6/icmpv6_rnotify.c index bf1f1beffd..b43d825702 100644 --- a/net/icmpv6/icmpv6_rnotify.c +++ b/net/icmpv6/icmpv6_rnotify.c @@ -1,7 +1,7 @@ /**************************************************************************** * net/icmpv6/icmpv6_rnotify.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -47,9 +47,10 @@ #include +#include +#include #include #include -#include #include "netdev/netdev.h" #include "utils/utils.h" @@ -166,7 +167,13 @@ void icmpv6_rwait_setup(FAR struct net_driver_s *dev, memcpy(notify->rn_ifname, dev->d_ifname, IFNAMSIZ); notify->rn_result = -ETIMEDOUT; + + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + (void)sem_init(¬ify->rn_sem, 0, 0); + sem_setprotocol(¬ify->rn_sem, SEM_PRIO_NONE); /* Add the wait structure to the list with interrupts disabled */ @@ -183,7 +190,13 @@ void icmpv6_rwait_setup(FAR struct net_driver_s *dev, /* Initialize and remember wait structure */ notify->rn_result = -ETIMEDOUT; + + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + (void)sem_init(¬ify->rn_sem, 0, 0); + sem_setprotocol(¬ify->rn_sem, SEM_PRIO_NONE); DEBUGASSERT(g_icmpv6_rwaiters == NULL); g_icmpv6_rwaiters = notify; diff --git a/net/igmp/igmp_group.c b/net/igmp/igmp_group.c index 90e8fb6579..e93a502052 100644 --- a/net/igmp/igmp_group.c +++ b/net/igmp/igmp_group.c @@ -2,7 +2,7 @@ * net/igmp/igmp_group.c * IGMP group data structure management logic * - * Copyright (C) 2010, 2013-2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2010, 2013-2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * The NuttX implementation of IGMP was inspired by the IGMP add-on for the @@ -55,6 +55,7 @@ #include #include #include +#include #include #include #include @@ -240,7 +241,13 @@ FAR struct igmp_group_s *igmp_grpalloc(FAR struct net_driver_s *dev, /* Initialize the non-zero elements of the group structure */ net_ipv4addr_copy(group->grpaddr, *addr); + + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + sem_init(&group->sem, 0, 0); + sem_setprotocol(&group->sem, SEM_PRIO_NONE); /* Initialize the group timer (but don't start it yet) */ diff --git a/net/local/local_conn.c b/net/local/local_conn.c index a369f04b7c..e70f8df7ab 100644 --- a/net/local/local_conn.c +++ b/net/local/local_conn.c @@ -1,7 +1,7 @@ /**************************************************************************** * net/local/local_conn.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -48,6 +48,7 @@ #include #include +#include #include "local/local.h" @@ -92,8 +93,15 @@ FAR struct local_conn_s *local_alloc(void) conn->lc_infd = -1; conn->lc_outfd = -1; + #ifdef CONFIG_NET_LOCAL_STREAM + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + sem_init(&conn->lc_waitsem, 0, 0); + sem_setprotocol(&conn->lc_waitsem, SEM_PRIO_NONE); + #ifdef HAVE_LOCAL_POLL memset(conn->lc_accept_fds, 0, sizeof(conn->lc_accept_fds)); #endif diff --git a/net/pkt/pkt_send.c b/net/pkt/pkt_send.c index a419d69d8f..b4dc0d6d45 100644 --- a/net/pkt/pkt_send.c +++ b/net/pkt/pkt_send.c @@ -1,7 +1,8 @@ /**************************************************************************** * net/pkt/pkt_send.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -52,6 +53,7 @@ #include #include +#include #include #include #include @@ -245,7 +247,14 @@ ssize_t psock_pkt_send(FAR struct socket *psock, FAR const void *buf, save = net_lock(); memset(&state, 0, sizeof(struct send_s)); + + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + (void)sem_init(&state.snd_sem, 0, 0); /* Doesn't really fail */ + (void)sem_setprotocol(&state.snd_sem, SEM_PRIO_NONE); + state.snd_sock = psock; /* Socket descriptor to use */ state.snd_buflen = len; /* Number of bytes to send */ state.snd_buffer = buf; /* Buffer to send from */ diff --git a/net/socket/connect.c b/net/socket/connect.c index 22c9cbbe31..3e174ae0b3 100644 --- a/net/socket/connect.c +++ b/net/socket/connect.c @@ -1,7 +1,7 @@ /**************************************************************************** * net/socket/connect.c * - * Copyright (C) 2007-2012, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2012, 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -49,6 +49,8 @@ #include #include + +#include #include #include #include @@ -107,7 +109,13 @@ static inline int psock_setup_callbacks(FAR struct socket *psock, /* Initialize the TCP state structure */ + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + (void)sem_init(&pstate->tc_sem, 0, 0); /* Doesn't really fail */ + (void)sem_setprotocol(&pstate->tc_sem, SEM_PRIO_NONE); + pstate->tc_conn = conn; pstate->tc_psock = psock; pstate->tc_result = -EAGAIN; diff --git a/net/socket/net_close.c b/net/socket/net_close.c index 261e1d4a88..3ca53d30de 100644 --- a/net/socket/net_close.c +++ b/net/socket/net_close.c @@ -1,7 +1,7 @@ /**************************************************************************** * net/socket/net_close.c * - * Copyright (C) 2007-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -49,6 +49,8 @@ #include #include + +#include #include #include #include @@ -388,7 +390,13 @@ static inline int netclose_disconnect(FAR struct socket *psock) state.cl_psock = psock; state.cl_result = -EBUSY; + + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + sem_init(&state.cl_sem, 0, 0); + sem_setprotocol(&state.cl_sem, SEM_PRIO_NONE); /* Record the time that we started the wait (in ticks) */ diff --git a/net/socket/net_sendfile.c b/net/socket/net_sendfile.c index 6c70cab18e..1efb22d1c8 100644 --- a/net/socket/net_sendfile.c +++ b/net/socket/net_sendfile.c @@ -57,6 +57,7 @@ #include #include +#include #include #include #include @@ -673,9 +674,15 @@ ssize_t net_sendfile(int outfd, struct file *infile, off_t *offset, */ save = net_lock(); - memset(&state, 0, sizeof(struct sendfile_s)); - sem_init(&state. snd_sem, 0, 0); /* Doesn't really fail */ + + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_init(&state.snd_sem, 0, 0); /* Doesn't really fail */ + sem_setprotocol(&state.snd_sem, SEM_PRIO_NONE); + state.snd_sock = psock; /* Socket descriptor to use */ state.snd_foffset = offset ? *offset : 0; /* Input file offset */ state.snd_flen = count; /* Number of bytes to send */ diff --git a/net/socket/recvfrom.c b/net/socket/recvfrom.c index 8b318bb6df..046860b75f 100644 --- a/net/socket/recvfrom.c +++ b/net/socket/recvfrom.c @@ -56,6 +56,7 @@ #include #include +#include #include #include #include @@ -1217,7 +1218,14 @@ static void recvfrom_init(FAR struct socket *psock, FAR void *buf, /* Initialize the state structure. */ memset(pstate, 0, sizeof(struct recvfrom_s)); + + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + (void)sem_init(&pstate->rf_sem, 0, 0); /* Doesn't really fail */ + (void)sem_setprotocol(&pstate->rf_sem, SEM_PRIO_NONE); + pstate->rf_buflen = len; pstate->rf_buffer = buf; pstate->rf_from = infrom; diff --git a/net/tcp/tcp_accept.c b/net/tcp/tcp_accept.c index d2b7d426ed..95d8bfbf40 100644 --- a/net/tcp/tcp_accept.c +++ b/net/tcp/tcp_accept.c @@ -1,7 +1,7 @@ /**************************************************************************** * net/tcp/tcp_accept.c * - * Copyright (C) 2007-2012, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2012, 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -49,6 +49,7 @@ #include #include +#include #include #include "socket/socket.h" @@ -279,7 +280,13 @@ int psock_tcp_accept(FAR struct socket *psock, FAR struct sockaddr *addr, state.acpt_addrlen = addrlen; state.acpt_newconn = NULL; state.acpt_result = OK; + + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + sem_init(&state.acpt_sem, 0, 0); + sem_setprotocol(&state.acpt_sem, SEM_PRIO_NONE); /* Set up the callback in the connection */ diff --git a/net/tcp/tcp_send_unbuffered.c b/net/tcp/tcp_send_unbuffered.c index f0f7c60121..4710c41fe7 100644 --- a/net/tcp/tcp_send_unbuffered.c +++ b/net/tcp/tcp_send_unbuffered.c @@ -52,7 +52,9 @@ #include #include + #include +#include #include #include #include @@ -792,7 +794,14 @@ ssize_t psock_tcp_send(FAR struct socket *psock, save = net_lock(); memset(&state, 0, sizeof(struct send_s)); + + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + (void)sem_init(&state.snd_sem, 0, 0); /* Doesn't really fail */ + (void)sem_setprotocol(&state.snd_sem, SEM_PRIO_NONE); + state.snd_sock = psock; /* Socket descriptor to use */ state.snd_buflen = len; /* Number of bytes to send */ state.snd_buffer = buf; /* Buffer to send from */ diff --git a/net/udp/udp_psock_sendto.c b/net/udp/udp_psock_sendto.c index 9210a5dcef..7ae830c5b7 100644 --- a/net/udp/udp_psock_sendto.c +++ b/net/udp/udp_psock_sendto.c @@ -47,6 +47,7 @@ #include #include +#include #include #include #include @@ -391,7 +392,14 @@ ssize_t psock_udp_sendto(FAR struct socket *psock, FAR const void *buf, save = net_lock(); memset(&state, 0, sizeof(struct sendto_s)); + + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + sem_init(&state.st_sem, 0, 0); + sem_setprotocol(&state.st_sem, SEM_PRIO_NONE); + state.st_buflen = len; state.st_buffer = buf; -- GitLab From dbbe46a2bce9b88266e7e40ee3717eca188c4f3a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 12:23:31 -0600 Subject: [PATCH 314/734] fs: Disable priority inheritance on all semaphores used for signaling --- fs/vfs/fs_poll.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/fs/vfs/fs_poll.c b/fs/vfs/fs_poll.c index 605147ec7f..e2c66abf7b 100644 --- a/fs/vfs/fs_poll.c +++ b/fs/vfs/fs_poll.c @@ -47,9 +47,9 @@ #include #include +#include #include #include -#include #include @@ -365,7 +365,13 @@ int poll(FAR struct pollfd *fds, nfds_t nfds, int timeout) int errcode; int ret; + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + sem_init(&sem, 0, 0); + sem_setprotocol(&sem, SEM_PRIO_NONE); + ret = poll_setup(fds, nfds, &sem); if (ret >= 0) { -- GitLab From 1da3a5fa61d8a0f7d0f5047791c2db2a6f3cd735 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 12:42:02 -0600 Subject: [PATCH 315/734] sched: Disable priority inheritance on all semaphores used for signaling --- include/nuttx/semaphore.h | 2 +- sched/group/group_create.c | 8 +++++++- sched/pthread/pthread_create.c | 17 ++++++++++++++++- 3 files changed, 24 insertions(+), 3 deletions(-) diff --git a/include/nuttx/semaphore.h b/include/nuttx/semaphore.h index 04fde1bacb..1b90a1b6a0 100644 --- a/include/nuttx/semaphore.h +++ b/include/nuttx/semaphore.h @@ -205,7 +205,7 @@ int sem_getprotocol(FAR sem_t *sem, FAR int *protocol); #ifdef CONFIG_PRIORITY_INHERITANCE int sem_setprotocol(FAR sem_t *sem, int protocol); #else -# define sem_setprotocol(s,p) DEBUGASSERT((p) == SEM_PRIO_NONE); +# define sem_setprotocol(s,p) ((p) == SEM_PRIO_NONE ? 0 : -ENOSYS); #endif #undef EXTERN diff --git a/sched/group/group_create.c b/sched/group/group_create.c index 2aecb9c12b..d5cee38002 100644 --- a/sched/group/group_create.c +++ b/sched/group/group_create.c @@ -46,6 +46,7 @@ #include #include +#include #include "environ/environ.h" #include "group/group.h" @@ -248,9 +249,14 @@ int group_allocate(FAR struct task_tcb_s *tcb, uint8_t ttype) #endif #if defined(CONFIG_SCHED_WAITPID) && !defined(CONFIG_SCHED_HAVE_PARENT) - /* Initialize the exit/wait semaphores */ + /* Initialize the exit/wait semaphores + * + * This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ (void)sem_init(&group->tg_exitsem, 0, 0); + (void)sem_setprotocol(&group->tg_exitsem, SEM_PRIO_NONE); #endif return OK; diff --git a/sched/pthread/pthread_create.c b/sched/pthread/pthread_create.c index be81a5f0ff..dccee1b965 100644 --- a/sched/pthread/pthread_create.c +++ b/sched/pthread/pthread_create.c @@ -49,9 +49,10 @@ #include #include +#include +#include #include #include -#include #include "sched/sched.h" #include "group/group.h" @@ -498,6 +499,20 @@ int pthread_create(FAR pthread_t *thread, FAR const pthread_attr_t *attr, ret = sem_init(&pjoin->exit_sem, 0, 0); } + /* Thse semaphores are used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + if (ret == OK) + { + ret = sem_setprotocol(&pjoin->data_sem, SEM_PRIO_NONE); + } + + if (ret == OK) + { + ret = sem_setprotocol(&pjoin->exit_sem, SEM_PRIO_NONE); + } + /* If the priority of the new pthread is lower than the priority of the * parent thread, then starting the pthread could result in both the * parent and the pthread to be blocked. This is a recipe for priority -- GitLab From 4c8ec0d2cae3da81787824642a4166a51416c94b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 12:49:44 -0600 Subject: [PATCH 316/734] include/nuttx/semaphore.h: Fix broken macros --- include/nuttx/semaphore.h | 8 -------- libc/semaphore/Make.defs | 6 +----- libc/semaphore/sem_getprotocol.c | 15 +++++++++------ sched/semaphore/Make.defs | 4 ++-- sched/semaphore/sem_setprotocol.c | 8 ++++---- syscall/syscall.csv | 2 +- 6 files changed, 17 insertions(+), 26 deletions(-) diff --git a/include/nuttx/semaphore.h b/include/nuttx/semaphore.h index 1b90a1b6a0..579a0c4a10 100644 --- a/include/nuttx/semaphore.h +++ b/include/nuttx/semaphore.h @@ -160,11 +160,7 @@ int sem_reset(FAR sem_t *sem, int16_t count); * ****************************************************************************/ -#ifdef CONFIG_PRIORITY_INHERITANCE int sem_getprotocol(FAR sem_t *sem, FAR int *protocol); -#else -# define sem_getprotocol(s,p) do { *(p) == SEM_PRIO_NONE); } while (0) -#endif /**************************************************************************** * Function: sem_setprotocol @@ -202,11 +198,7 @@ int sem_getprotocol(FAR sem_t *sem, FAR int *protocol); * ****************************************************************************/ -#ifdef CONFIG_PRIORITY_INHERITANCE int sem_setprotocol(FAR sem_t *sem, int protocol); -#else -# define sem_setprotocol(s,p) ((p) == SEM_PRIO_NONE ? 0 : -ENOSYS); -#endif #undef EXTERN #ifdef __cplusplus diff --git a/libc/semaphore/Make.defs b/libc/semaphore/Make.defs index d456f07520..cafa18b65a 100644 --- a/libc/semaphore/Make.defs +++ b/libc/semaphore/Make.defs @@ -35,11 +35,7 @@ # Add the semaphore C files to the build -CSRCS += sem_init.c sem_getvalue.c - -ifeq ($(CONFIG_PRIORITY_INHERITANCE),y) -CSRCS += sem_getprotocol.c -endif +CSRCS += sem_init.c sem_getprotocol.c sem_getvalue.c # Add the semaphore directory to the build diff --git a/libc/semaphore/sem_getprotocol.c b/libc/semaphore/sem_getprotocol.c index 4ae1606ff7..614d5da72a 100644 --- a/libc/semaphore/sem_getprotocol.c +++ b/libc/semaphore/sem_getprotocol.c @@ -43,8 +43,6 @@ #include -#ifdef CONFIG_PRIORITY_INHERITANCE - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -71,14 +69,19 @@ int sem_getprotocol(FAR sem_t *sem, FAR int *protocol) { DEBUGASSERT(sem != NULL && protocol != NULL); +#ifdef CONFIG_PRIORITY_INHERITANCE if ((sem->flags & PRIOINHERIT_FLAGS_DISABLE) != 0) { - return SEM_PRIO_NONE; + *protocol = SEM_PRIO_NONE; } else { - return SEM_PRIO_INHERIT; + *protocol = SEM_PRIO_INHERIT; } -} -#endif /* CONFIG_PRIORITY_INHERITANCE */ +#else + *protocol = SEM_PRIO_NONE; +#endif + + return OK; +} diff --git a/sched/semaphore/Make.defs b/sched/semaphore/Make.defs index 7eb1740424..93fd35a0d0 100644 --- a/sched/semaphore/Make.defs +++ b/sched/semaphore/Make.defs @@ -37,10 +37,10 @@ CSRCS += sem_destroy.c sem_wait.c sem_trywait.c sem_tickwait.c CSRCS += sem_timedwait.c sem_timeout.c sem_post.c sem_recover.c -CSRCS += sem_reset.c sem_waitirq.c +CSRCS += sem_reset.c sem_setprotocol.c sem_waitirq.c ifeq ($(CONFIG_PRIORITY_INHERITANCE),y) -CSRCS += sem_initialize.c sem_holder.c sem_setprotocol.c +CSRCS += sem_initialize.c sem_holder.c endif ifeq ($(CONFIG_SPINLOCK),y) diff --git a/sched/semaphore/sem_setprotocol.c b/sched/semaphore/sem_setprotocol.c index 1350206941..6f4392bcce 100644 --- a/sched/semaphore/sem_setprotocol.c +++ b/sched/semaphore/sem_setprotocol.c @@ -46,8 +46,6 @@ #include "semaphore/semaphore.h" -#ifdef CONFIG_PRIORITY_INHERITANCE - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -97,6 +95,7 @@ int sem_setprotocol(FAR sem_t *sem, int protocol) switch (protocol) { case SEM_PRIO_NONE: +#ifdef CONFIG_PRIORITY_INHERITANCE /* Disable priority inheritance */ sem->flags |= PRIOINHERIT_FLAGS_DISABLE; @@ -104,13 +103,16 @@ int sem_setprotocol(FAR sem_t *sem, int protocol) /* Remove any current holders */ sem_destroyholder(sem); +#endif return OK; case SEM_PRIO_INHERIT: +#ifdef CONFIG_PRIORITY_INHERITANCE /* Enable priority inheritance (dangerous) */ sem->flags &= ~PRIOINHERIT_FLAGS_DISABLE; return OK; +#endif case SEM_PRIO_PROTECT: /* Not yet supported */ @@ -126,5 +128,3 @@ int sem_setprotocol(FAR sem_t *sem, int protocol) set_errno(errcode); return ERROR; } - -#endif /* CONFIG_PRIORITY_INHERITANCE */ diff --git a/syscall/syscall.csv b/syscall/syscall.csv index 8ecf52854f..99071ea27d 100644 --- a/syscall/syscall.csv +++ b/syscall/syscall.csv @@ -118,7 +118,7 @@ "sem_destroy","semaphore.h","","int","FAR sem_t*" "sem_open","semaphore.h","defined(CONFIG_FS_NAMED_SEMAPHORES)","FAR sem_t*","FAR const char*","int","..." "sem_post","semaphore.h","","int","FAR sem_t*" -"sem_setprotocol","nuttx/semaphore.h","defined(CONFIG_PRIORITY_INHERITANCE)","int","FAR sem_t*","int" +"sem_setprotocol","nuttx/semaphore.h","","int","FAR sem_t*","int" "sem_timedwait","semaphore.h","","int","FAR sem_t*","FAR const struct timespec *" "sem_trywait","semaphore.h","","int","FAR sem_t*" "sem_unlink","semaphore.h","defined(CONFIG_FS_NAMED_SEMAPHORES)","int","FAR const char*" -- GitLab From 0d5bd30943ede5a5bdc8584a6616936d5811f7ee Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 12:58:02 -0600 Subject: [PATCH 317/734] Fix a type in include file name --- sched/pthread/pthread_create.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sched/pthread/pthread_create.c b/sched/pthread/pthread_create.c index dccee1b965..6efc9aa21a 100644 --- a/sched/pthread/pthread_create.c +++ b/sched/pthread/pthread_create.c @@ -50,7 +50,7 @@ #include #include -#include +#include #include #include -- GitLab From e1cd9febbff41db30475fa8f2fde0270adfccacd Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 14:23:42 -0600 Subject: [PATCH 318/734] arch: Disable priority inheritance on all semaphores used for signaling in all I2C/TWI drivers --- arch/arm/src/efm32/efm32_i2c.c | 9 ++++++++- arch/arm/src/kinetis/kinetis_i2c.c | 9 +++++++++ arch/arm/src/lpc11xx/lpc11_i2c.c | 9 +++++++++ arch/arm/src/lpc17xx/lpc17_i2c.c | 9 +++++++++ arch/arm/src/lpc2378/lpc23xx_i2c.c | 9 +++++++++ arch/arm/src/lpc31xx/lpc31_i2c.c | 9 +++++++++ arch/arm/src/lpc43xx/lpc43_i2c.c | 9 +++++++++ arch/arm/src/sam34/sam_twi.c | 9 +++++++++ arch/arm/src/sama5/sam_twi.c | 9 +++++++++ arch/arm/src/samv7/sam_twihs.c | 9 +++++++++ arch/arm/src/stm32/stm32_i2c.c | 9 ++++++++- arch/arm/src/stm32/stm32_i2c_alt.c | 9 ++++++++- arch/arm/src/stm32/stm32f30xxx_i2c.c | 9 ++++++++- arch/arm/src/stm32/stm32f40xxx_i2c.c | 9 ++++++++- arch/arm/src/stm32f7/stm32_i2c.c | 9 ++++++++- arch/arm/src/stm32l4/stm32l4_i2c.c | 9 ++++++++- arch/arm/src/tiva/tiva_i2c.c | 9 ++++++++- 17 files changed, 145 insertions(+), 8 deletions(-) diff --git a/arch/arm/src/efm32/efm32_i2c.c b/arch/arm/src/efm32/efm32_i2c.c index d05f9ae22a..1c10e5b14c 100644 --- a/arch/arm/src/efm32/efm32_i2c.c +++ b/arch/arm/src/efm32/efm32_i2c.c @@ -71,8 +71,9 @@ #include #include -#include #include +#include +#include #include @@ -681,8 +682,14 @@ static inline void efm32_i2c_sem_post(FAR struct efm32_i2c_priv_s *priv) static inline void efm32_i2c_sem_init(FAR struct efm32_i2c_priv_s *priv) { sem_init(&priv->sem_excl, 0, 1); + #ifndef CONFIG_I2C_POLLED + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + sem_init(&priv->sem_isr, 0, 0); + sem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE); #endif } diff --git a/arch/arm/src/kinetis/kinetis_i2c.c b/arch/arm/src/kinetis/kinetis_i2c.c index 520534b3a5..337e24b4d3 100644 --- a/arch/arm/src/kinetis/kinetis_i2c.c +++ b/arch/arm/src/kinetis/kinetis_i2c.c @@ -49,6 +49,7 @@ #include #include +#include #include #include @@ -1105,9 +1106,17 @@ struct i2c_master_s *kinetis_i2cbus_initialize(int port) leave_critical_section(flags); + /* Initialize semaphores */ + sem_init(&priv->mutex, 0, 1); sem_init(&priv->wait, 0, 0); + /* The wait semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->wait, SEM_PRIO_NONE); + /* Allocate a watchdog timer */ priv->timeout = wd_create(); diff --git a/arch/arm/src/lpc11xx/lpc11_i2c.c b/arch/arm/src/lpc11xx/lpc11_i2c.c index 184290a602..b8f91daee7 100644 --- a/arch/arm/src/lpc11xx/lpc11_i2c.c +++ b/arch/arm/src/lpc11xx/lpc11_i2c.c @@ -59,6 +59,7 @@ #include #include +#include #include #include @@ -584,9 +585,17 @@ struct i2c_master_s *lpc11_i2cbus_initialize(int port) putreg32(I2C_CONSET_I2EN, priv->base + LPC11_I2C_CONSET_OFFSET); + /* Initialize semaphores */ + sem_init(&priv->mutex, 0, 1); sem_init(&priv->wait, 0, 0); + /* The wait semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->wait, SEM_PRIO_NONE); + /* Allocate a watchdog timer */ priv->timeout = wd_create(); diff --git a/arch/arm/src/lpc17xx/lpc17_i2c.c b/arch/arm/src/lpc17xx/lpc17_i2c.c index 58bb2de898..554659818f 100644 --- a/arch/arm/src/lpc17xx/lpc17_i2c.c +++ b/arch/arm/src/lpc17xx/lpc17_i2c.c @@ -59,6 +59,7 @@ #include #include +#include #include #include @@ -589,9 +590,17 @@ struct i2c_master_s *lpc17_i2cbus_initialize(int port) putreg32(I2C_CONSET_I2EN, priv->base + LPC17_I2C_CONSET_OFFSET); + /* Initialize semaphores */ + sem_init(&priv->mutex, 0, 1); sem_init(&priv->wait, 0, 0); + /* The wait semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->wait, SEM_PRIO_NONE); + /* Allocate a watchdog timer */ priv->timeout = wd_create(); diff --git a/arch/arm/src/lpc2378/lpc23xx_i2c.c b/arch/arm/src/lpc2378/lpc23xx_i2c.c index 1c281e8857..5de046a39f 100644 --- a/arch/arm/src/lpc2378/lpc23xx_i2c.c +++ b/arch/arm/src/lpc2378/lpc23xx_i2c.c @@ -64,6 +64,7 @@ #include #include +#include #include #include @@ -600,9 +601,17 @@ struct i2c_master_s *lpc2378_i2cbus_initialize(int port) putreg32(I2C_CONSET_I2EN, priv->base + I2C_CONSET_OFFSET); + /* Initialize semaphores */ + sem_init(&priv->mutex, 0, 1); sem_init(&priv->wait, 0, 0); + /* The wait semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->wait, SEM_PRIO_NONE); + /* Allocate a watchdog timer */ priv->timeout = wd_create(); diff --git a/arch/arm/src/lpc31xx/lpc31_i2c.c b/arch/arm/src/lpc31xx/lpc31_i2c.c index 79d9667a9d..1f27c4d1ff 100644 --- a/arch/arm/src/lpc31xx/lpc31_i2c.c +++ b/arch/arm/src/lpc31xx/lpc31_i2c.c @@ -51,6 +51,7 @@ #include #include +#include #include #include @@ -554,9 +555,17 @@ struct i2c_master_s *lpc31_i2cbus_initialize(int port) priv->rstid = (port == 0) ? RESETID_I2C0RST : RESETID_I2C1RST; priv->irqid = (port == 0) ? LPC31_IRQ_I2C0 : LPC31_IRQ_I2C1; + /* Initialize semaphores */ + sem_init(&priv->mutex, 0, 1); sem_init(&priv->wait, 0, 0); + /* The wait semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->wait, SEM_PRIO_NONE); + /* Enable I2C system clocks */ lpc31_enableclock(priv->clkid); diff --git a/arch/arm/src/lpc43xx/lpc43_i2c.c b/arch/arm/src/lpc43xx/lpc43_i2c.c index fed79db207..49a77bb8b5 100644 --- a/arch/arm/src/lpc43xx/lpc43_i2c.c +++ b/arch/arm/src/lpc43xx/lpc43_i2c.c @@ -62,6 +62,7 @@ #include #include +#include #include #include @@ -539,9 +540,17 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port) putreg32(I2C_CONSET_I2EN, priv->base + LPC43_I2C_CONSET_OFFSET); + /* Initialize semaphores */ + sem_init(&priv->mutex, 0, 1); sem_init(&priv->wait, 0, 0); + /* The wait semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->wait, SEM_PRIO_NONE); + /* Allocate a watchdog timer */ priv->timeout = wd_create(); diff --git a/arch/arm/src/sam34/sam_twi.c b/arch/arm/src/sam34/sam_twi.c index 74d0e7d6ed..1ed9c03f64 100644 --- a/arch/arm/src/sam34/sam_twi.c +++ b/arch/arm/src/sam34/sam_twi.c @@ -56,6 +56,7 @@ #include #include +#include #include #include @@ -982,9 +983,17 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus) priv->dev.ops = &g_twiops; + /* Initialize semaphores */ + sem_init(&priv->exclsem, 0, 1); sem_init(&priv->waitsem, 0, 0); + /* The waitsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); + /* Allocate a watchdog timer */ priv->timeout = wd_create(); diff --git a/arch/arm/src/sama5/sam_twi.c b/arch/arm/src/sama5/sam_twi.c index 4af5f702b0..52f3e0950d 100644 --- a/arch/arm/src/sama5/sam_twi.c +++ b/arch/arm/src/sama5/sam_twi.c @@ -57,6 +57,7 @@ #include #include #include +#include #include #include @@ -1306,9 +1307,17 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus) priv->dev.ops = &g_twiops; + /* Initialize semaphores */ + (void)sem_init(&priv->exclsem, 0, 1); (void)sem_init(&priv->waitsem, 0, 0); + /* The waitsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); + /* Perform repeatable TWI hardware initialization */ twi_hw_initialize(priv, frequency); diff --git a/arch/arm/src/samv7/sam_twihs.c b/arch/arm/src/samv7/sam_twihs.c index 6800ecbba8..bdb5523ace 100644 --- a/arch/arm/src/samv7/sam_twihs.c +++ b/arch/arm/src/samv7/sam_twihs.c @@ -57,6 +57,7 @@ #include #include #include +#include #include #include @@ -1454,9 +1455,17 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus) priv->dev.ops = &g_twiops; + /* Initialize semaphores */ + (void)sem_init(&priv->exclsem, 0, 1); (void)sem_init(&priv->waitsem, 0, 0); + /* The waitsem semaphore is used for signaling and, hence, should not + * have priority inheritance enabled. + */ + + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); + /* Perform repeatable TWIHS hardware initialization */ twi_hw_initialize(priv, frequency); diff --git a/arch/arm/src/stm32/stm32_i2c.c b/arch/arm/src/stm32/stm32_i2c.c index 9f41597f04..631ba66501 100644 --- a/arch/arm/src/stm32/stm32_i2c.c +++ b/arch/arm/src/stm32/stm32_i2c.c @@ -84,8 +84,9 @@ #include #include -#include #include +#include +#include #include @@ -784,8 +785,14 @@ static inline void stm32_i2c_sem_post(struct stm32_i2c_priv_s *priv) static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv) { sem_init(&priv->sem_excl, 0, 1); + #ifndef CONFIG_I2C_POLLED + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + sem_init(&priv->sem_isr, 0, 0); + sem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE); #endif } diff --git a/arch/arm/src/stm32/stm32_i2c_alt.c b/arch/arm/src/stm32/stm32_i2c_alt.c index ac2ea5f607..545a647334 100644 --- a/arch/arm/src/stm32/stm32_i2c_alt.c +++ b/arch/arm/src/stm32/stm32_i2c_alt.c @@ -91,8 +91,9 @@ #include #include -#include #include +#include +#include #include @@ -792,8 +793,14 @@ static inline void stm32_i2c_sem_post(FAR struct stm32_i2c_priv_s *priv) static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv) { sem_init(&priv->sem_excl, 0, 1); + #ifndef CONFIG_I2C_POLLED + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + sem_init(&priv->sem_isr, 0, 0); + sem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE); #endif } diff --git a/arch/arm/src/stm32/stm32f30xxx_i2c.c b/arch/arm/src/stm32/stm32f30xxx_i2c.c index 27b1c92488..312e0b4bb8 100644 --- a/arch/arm/src/stm32/stm32f30xxx_i2c.c +++ b/arch/arm/src/stm32/stm32f30xxx_i2c.c @@ -85,8 +85,9 @@ #include #include -#include #include +#include +#include #include @@ -899,8 +900,14 @@ static inline void stm32_i2c_sem_post(FAR struct stm32_i2c_priv_s *priv) static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv) { sem_init(&priv->sem_excl, 0, 1); + #ifndef CONFIG_I2C_POLLED + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + sem_init(&priv->sem_isr, 0, 0); + sem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE); #endif } diff --git a/arch/arm/src/stm32/stm32f40xxx_i2c.c b/arch/arm/src/stm32/stm32f40xxx_i2c.c index 155add73ae..2bb715c4a8 100644 --- a/arch/arm/src/stm32/stm32f40xxx_i2c.c +++ b/arch/arm/src/stm32/stm32f40xxx_i2c.c @@ -84,8 +84,9 @@ #include #include -#include #include +#include +#include #include @@ -786,8 +787,14 @@ static inline void stm32_i2c_sem_post(struct stm32_i2c_priv_s *priv) static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv) { sem_init(&priv->sem_excl, 0, 1); + #ifndef CONFIG_I2C_POLLED + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + sem_init(&priv->sem_isr, 0, 0); + sem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE); #endif } diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c index eda1fba72a..5da613f528 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.c +++ b/arch/arm/src/stm32f7/stm32_i2c.c @@ -231,9 +231,10 @@ #include #include -#include +#include #include #include +#include #include @@ -1089,8 +1090,14 @@ static inline void stm32_i2c_sem_post(FAR struct i2c_master_s *dev) static inline void stm32_i2c_sem_init(FAR struct i2c_master_s *dev) { sem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl, 0, 1); + #ifndef CONFIG_I2C_POLLED + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + sem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, 0, 0); + sem_setprotocol(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, SEM_PRIO_NONE); #endif } diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.c b/arch/arm/src/stm32l4/stm32l4_i2c.c index 278885fc58..eed199f86d 100644 --- a/arch/arm/src/stm32l4/stm32l4_i2c.c +++ b/arch/arm/src/stm32l4/stm32l4_i2c.c @@ -81,8 +81,9 @@ #include #include -#include #include +#include +#include #include @@ -843,8 +844,14 @@ static inline void stm32l4_i2c_sem_post(FAR struct stm32l4_i2c_priv_s *priv) static inline void stm32l4_i2c_sem_init(FAR struct stm32l4_i2c_priv_s *priv) { sem_init(&priv->sem_excl, 0, 1); + #ifndef CONFIG_I2C_POLLED + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + sem_init(&priv->sem_isr, 0, 0); + sem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE); #endif } diff --git a/arch/arm/src/tiva/tiva_i2c.c b/arch/arm/src/tiva/tiva_i2c.c index 1d0127aa04..13b9c7b5ad 100644 --- a/arch/arm/src/tiva/tiva_i2c.c +++ b/arch/arm/src/tiva/tiva_i2c.c @@ -57,8 +57,9 @@ #include #include -#include #include +#include +#include #include @@ -891,8 +892,14 @@ static inline void tiva_i2c_sem_post(struct tiva_i2c_priv_s *priv) static inline void tiva_i2c_sem_init(struct tiva_i2c_priv_s *priv) { sem_init(&priv->exclsem, 0, 1); + #ifndef CONFIG_I2C_POLLED + /* This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + sem_init(&priv->waitsem, 0, 0); + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); #endif } -- GitLab From 8b07aa6f7cf1f37e2c5a690547c8d5bd0c3b79b2 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 14:51:44 -0600 Subject: [PATCH 319/734] arch: Disable priority inheritance on all semaphores used for signaling in all SPI drivers --- arch/arm/src/efm32/efm32_spi.c | 8 ++++++++ arch/arm/src/imx1/imx_spi.c | 7 +++++++ arch/arm/src/sam34/sam_spi.c | 5 ++++- arch/arm/src/sama5/sam_spi.c | 5 ++++- arch/arm/src/samv7/sam_qspi.c | 5 ++++- arch/arm/src/samv7/sam_spi.c | 5 ++++- arch/arm/src/stm32/stm32_spi.c | 11 +++++++++-- arch/arm/src/stm32f7/stm32_spi.c | 13 ++++++++++--- arch/arm/src/stm32l4/stm32l4_qspi.c | 12 +++++++++--- arch/arm/src/stm32l4/stm32l4_spi.c | 8 ++++++++ 10 files changed, 67 insertions(+), 12 deletions(-) diff --git a/arch/arm/src/efm32/efm32_spi.c b/arch/arm/src/efm32/efm32_spi.c index 0bf2c31a86..d0ae6d378a 100644 --- a/arch/arm/src/efm32/efm32_spi.c +++ b/arch/arm/src/efm32/efm32_spi.c @@ -53,6 +53,7 @@ #include #include #include +#include #include #include @@ -1640,6 +1641,13 @@ static int spi_portinitialize(struct efm32_spidev_s *priv) (void)sem_init(&priv->rxdmasem, 0, 0); (void)sem_init(&priv->txdmasem, 0, 0); + + /* These semaphores are used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->rxdmasem, SEM_PRIO_NONE); + sem_setprotocol(&priv->txdmasem, SEM_PRIO_NONE); #endif /* Enable SPI */ diff --git a/arch/arm/src/imx1/imx_spi.c b/arch/arm/src/imx1/imx_spi.c index fb58314386..d63c65ed2e 100644 --- a/arch/arm/src/imx1/imx_spi.c +++ b/arch/arm/src/imx1/imx_spi.c @@ -50,6 +50,7 @@ #include #include +#include #include #include "up_internal.h" @@ -1116,7 +1117,13 @@ FAR struct spi_dev_s *imx_spibus_initialize(int port) /* Initialize the state structure */ #ifndef CONFIG_SPI_POLLWAIT + /* Initialize the semaphore that is used to wake up the waiting + * thread when the DMA transfer completes. This semaphore is used for + * signaling and, hence, should not have priority inheritance enabled. + */ + sem_init(&priv->waitsem, 0, 0); + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); #endif sem_init(&priv->exclsem, 0, 1); diff --git a/arch/arm/src/sam34/sam_spi.c b/arch/arm/src/sam34/sam_spi.c index 4b7f1dba7e..2cbe3614b6 100644 --- a/arch/arm/src/sam34/sam_spi.c +++ b/arch/arm/src/sam34/sam_spi.c @@ -56,6 +56,7 @@ #include #include #include +#include #include #include "up_internal.h" @@ -1882,10 +1883,12 @@ struct spi_dev_s *sam_spibus_initialize(int port) #ifdef CONFIG_SAM34_SPI_DMA /* Initialize the SPI semaphore that is used to wake up the waiting - * thread when the DMA transfer completes. + * thread when the DMA transfer completes. This semaphore is used for + * signaling and, hence, should not have priority inheritance enabled. */ sem_init(&spics->dmawait, 0, 0); + sem_setprotocol(&spics->dmawait, SEM_PRIO_NONE); /* Create a watchdog time to catch DMA timeouts */ diff --git a/arch/arm/src/sama5/sam_spi.c b/arch/arm/src/sama5/sam_spi.c index 0386fcc681..459e949cad 100644 --- a/arch/arm/src/sama5/sam_spi.c +++ b/arch/arm/src/sama5/sam_spi.c @@ -60,6 +60,7 @@ #include #include #include +#include #include #include "up_internal.h" @@ -1810,10 +1811,12 @@ struct spi_dev_s *sam_spibus_initialize(int port) #ifdef CONFIG_SAMA5_SPI_DMA /* Initialize the SPI semaphore that is used to wake up the waiting - * thread when the DMA transfer completes. + * thread when the DMA transfer completes. This semaphore is used for + * signaling and, hence, should not have priority inheritance enabled. */ sem_init(&spics->dmawait, 0, 0); + sem_setprotocol(&spics->dmawait, SEM_PRIO_NONE); /* Create a watchdog time to catch DMA timeouts */ diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c index b90a515d8b..a37245c7e6 100644 --- a/arch/arm/src/samv7/sam_qspi.c +++ b/arch/arm/src/samv7/sam_qspi.c @@ -55,6 +55,7 @@ #include #include #include +#include #include #include "up_internal.h" @@ -1790,10 +1791,12 @@ struct qspi_dev_s *sam_qspi_initialize(int intf) } /* Initialize the QSPI semaphore that is used to wake up the waiting - * thread when the DMA transfer completes. + * thread when the DMA transfer completes. This semaphore is used for + * signaling and, hence, should not have priority inheritance enabled. */ sem_init(&priv->dmawait, 0, 0); + sem_setprotocol(&priv->dmawait, SEM_PRIO_NONE); /* Create a watchdog time to catch DMA timeouts */ diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c index 959a3cd290..d0b40e8694 100644 --- a/arch/arm/src/samv7/sam_spi.c +++ b/arch/arm/src/samv7/sam_spi.c @@ -56,6 +56,7 @@ #include #include #include +#include #include #include "up_internal.h" @@ -2164,10 +2165,12 @@ FAR struct spi_dev_s *sam_spibus_initialize(int port) #ifdef CONFIG_SAMV7_SPI_DMA /* Initialize the SPI semaphore that is used to wake up the waiting - * thread when the DMA transfer completes. + * thread when the DMA transfer completes. This semaphore is used for + * signaling and, hence, should not have priority inheritance enabled. */ sem_init(&spics->dmawait, 0, 0); + sem_setprotocol(&spics->dmawait, SEM_PRIO_NONE); /* Create a watchdog time to catch DMA timeouts */ diff --git a/arch/arm/src/stm32/stm32_spi.c b/arch/arm/src/stm32/stm32_spi.c index c70bf8f6f1..ad6d2fc47c 100644 --- a/arch/arm/src/stm32/stm32_spi.c +++ b/arch/arm/src/stm32/stm32_spi.c @@ -70,6 +70,7 @@ #include #include +#include #include #include @@ -1719,12 +1720,18 @@ static void spi_bus_initialize(FAR struct stm32_spidev_s *priv) sem_init(&priv->exclsem, 0, 1); - /* Initialize the SPI semaphores that is used to wait for DMA completion */ - #ifdef CONFIG_STM32_SPI_DMA + /* Initialize the SPI semaphores that is used to wait for DMA completion. + * This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + sem_init(&priv->rxsem, 0, 0); sem_init(&priv->txsem, 0, 0); + sem_setprotocol(&priv->rxsem, SEM_PRIO_NONE); + sem_setprotocol(&priv->txsem, SEM_PRIO_NONE); + /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA channel. * if the channel is not available, then stm32_dmachannel() will block and wait * until the channel becomes available. WARNING: If you have another device sharing diff --git a/arch/arm/src/stm32f7/stm32_spi.c b/arch/arm/src/stm32f7/stm32_spi.c index 4b0fceba54..c00e717a09 100644 --- a/arch/arm/src/stm32f7/stm32_spi.c +++ b/arch/arm/src/stm32f7/stm32_spi.c @@ -72,6 +72,7 @@ #include #include +#include #include #include @@ -1665,16 +1666,22 @@ static void spi_bus_initialize(FAR struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); - /* Initialize the SPI semaphore that enforces mutually exclusive access */ + /* Initialize the SPI semaphore that enforces mutually exclusive access. */ sem_init(&priv->exclsem, 0, 1); - /* Initialize the SPI semaphores that is used to wait for DMA completion */ - #ifdef CONFIG_STM32F7_SPI_DMA + /* Initialize the SPI semaphores that is used to wait for DMA completion. + * This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + sem_init(&priv->rxsem, 0, 0); sem_init(&priv->txsem, 0, 0); + sem_setprotocol(&priv->rxsem, SEM_PRIO_NONE); + sem_setprotocol(&priv->txsem, SEM_PRIO_NONE); + /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA channel. * if the channel is not available, then stm32_dmachannel() will block and wait * until the channel becomes available. WARNING: If you have another device sharing diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.c b/arch/arm/src/stm32l4/stm32l4_qspi.c index db01e22bba..95d2da540b 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.c +++ b/arch/arm/src/stm32l4/stm32l4_qspi.c @@ -55,6 +55,7 @@ #include #include #include +#include #include #include "up_internal.h" @@ -2501,10 +2502,12 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) } /* Initialize the QSPI semaphore that is used to wake up the waiting - * thread when the DMA transfer completes. + * thread when the DMA transfer completes. This semaphore is used for + * signaling and, hence, should not have priority inheritance enabled. */ sem_init(&priv->dmawait, 0, 0); + sem_setprotocol(&priv->dmawait, SEM_PRIO_NONE); /* Create a watchdog time to catch DMA timeouts */ @@ -2526,10 +2529,13 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) goto errout_with_dmadog; } - /* Initialize the semaphore that blocks until the operation completes */ + /* Initialize the semaphore that blocks until the operation completes. + * This semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ sem_init(&priv->op_sem, 0, 0); - + sem_setprotocol(&priv->op_sem, SEM_PRIO_NONE); #endif /* Perform hardware initialization. Puts the QSPI into an active diff --git a/arch/arm/src/stm32l4/stm32l4_spi.c b/arch/arm/src/stm32l4/stm32l4_spi.c index bc61ed7446..9d9db706e0 100644 --- a/arch/arm/src/stm32l4/stm32l4_spi.c +++ b/arch/arm/src/stm32l4/stm32l4_spi.c @@ -76,6 +76,7 @@ #include #include +#include #include #include @@ -1517,6 +1518,13 @@ static void spi_bus_initialize(FAR struct stm32l4_spidev_s *priv) sem_init(&priv->rxsem, 0, 0); sem_init(&priv->txsem, 0, 0); + /* These semaphores are used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->rxsem, SEM_PRIO_NONE); + sem_setprotocol(&priv->txsem, SEM_PRIO_NONE); + /* Get DMA channels. NOTE: stm32l4_dmachannel() will always assign the DMA channel. * if the channel is not available, then stm32l4_dmachannel() will block and wait * until the channel becomes available. WARNING: If you have another device sharing -- GitLab From bb6bfa633eb8e8fcf4155b7ded61d4095284ecad Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 15:13:27 -0600 Subject: [PATCH 320/734] arch: Disable priority inheritance on all semaphores used for signaling in all SD card drivers --- arch/arm/src/kinetis/kinetis_sdhc.c | 11 +++++++++++ arch/arm/src/lpc17xx/lpc17_sdcard.c | 13 ++++++++++++- arch/arm/src/sam34/sam_hsmci.c | 13 ++++++++++++- arch/arm/src/sama5/sam_hsmci.c | 13 ++++++++++++- arch/arm/src/samv7/sam_hsmci.c | 13 ++++++++++++- arch/arm/src/stm32/stm32_sdio.c | 13 ++++++++++++- arch/arm/src/stm32f7/stm32_sdmmc.c | 11 +++++++++++ 7 files changed, 82 insertions(+), 5 deletions(-) diff --git a/arch/arm/src/kinetis/kinetis_sdhc.c b/arch/arm/src/kinetis/kinetis_sdhc.c index 0f1197b6e7..b724bfec91 100644 --- a/arch/arm/src/kinetis/kinetis_sdhc.c +++ b/arch/arm/src/kinetis/kinetis_sdhc.c @@ -52,6 +52,7 @@ #include #include #include +#include #include #include @@ -2774,8 +2775,18 @@ FAR struct sdio_dev_s *sdhc_initialize(int slotno) DEBUGASSERT(slotno == 0); /* Initialize the SDHC slot structure data structure */ + /* Initialize semaphores */ sem_init(&priv->waitsem, 0, 0); + + /* The waitsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); + + /* Create a watchdog timer */ + priv->waitwdog = wd_create(); DEBUGASSERT(priv->waitwdog); diff --git a/arch/arm/src/lpc17xx/lpc17_sdcard.c b/arch/arm/src/lpc17xx/lpc17_sdcard.c index 2ea6c17c45..532c8ed35d 100644 --- a/arch/arm/src/lpc17xx/lpc17_sdcard.c +++ b/arch/arm/src/lpc17xx/lpc17_sdcard.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/lpc17xx/lpc17_sdcard.c * - * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -52,6 +52,7 @@ #include #include #include +#include #include #include @@ -2699,8 +2700,18 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) putreg32(regval, LPC17_SYSCON_PCONP); /* Initialize the SD card slot structure */ + /* Initialize semaphores */ sem_init(&priv->waitsem, 0, 0); + + /* The waitsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); + + /* Create a watchdog timer */ + priv->waitwdog = wd_create(); DEBUGASSERT(priv->waitwdog); diff --git a/arch/arm/src/sam34/sam_hsmci.c b/arch/arm/src/sam34/sam_hsmci.c index fa4073d6a2..2ad23303c4 100644 --- a/arch/arm/src/sam34/sam_hsmci.c +++ b/arch/arm/src/sam34/sam_hsmci.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/sam34/sam_hsmci.c * - * Copyright (C) 2010, 2012-2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2010, 2012-2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -52,6 +52,7 @@ #include #include #include +#include #include #include @@ -2668,8 +2669,18 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) mcinfo("slotno: %d\n", slotno); /* Initialize the HSMCI slot structure */ + /* Initialize semaphores */ sem_init(&priv->waitsem, 0, 0); + + /* The waitsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); + + /* Create a watchdog timer */ + priv->waitwdog = wd_create(); DEBUGASSERT(priv->waitwdog); diff --git a/arch/arm/src/sama5/sam_hsmci.c b/arch/arm/src/sama5/sam_hsmci.c index 2b4eb8361a..165a8f1a12 100644 --- a/arch/arm/src/sama5/sam_hsmci.c +++ b/arch/arm/src/sama5/sam_hsmci.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/sama5/sam_hsmci.c * - * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -52,6 +52,7 @@ #include #include #include +#include #include #include @@ -3331,8 +3332,18 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) priv, priv->base, priv->hsmci, dmac, pid); /* Initialize the HSMCI slot structure */ + /* Initialize semaphores */ sem_init(&priv->waitsem, 0, 0); + + /* The waitsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); + + /* Create a watchdog timer */ + priv->waitwdog = wd_create(); DEBUGASSERT(priv->waitwdog); diff --git a/arch/arm/src/samv7/sam_hsmci.c b/arch/arm/src/samv7/sam_hsmci.c index cffada9e47..589a8cbf87 100644 --- a/arch/arm/src/samv7/sam_hsmci.c +++ b/arch/arm/src/samv7/sam_hsmci.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/samv7/sam_hsmci.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -52,6 +52,7 @@ #include #include #include +#include #include #include @@ -3352,8 +3353,18 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) priv, priv->base, priv->hsmci, pid); /* Initialize the HSMCI slot structure */ + /* Initialize semaphores */ sem_init(&priv->waitsem, 0, 0); + + /* The waitsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); + + /* Create a watchdog timer */ + priv->waitwdog = wd_create(); DEBUGASSERT(priv->waitwdog); diff --git a/arch/arm/src/stm32/stm32_sdio.c b/arch/arm/src/stm32/stm32_sdio.c index 6cd372b7fd..be060c7026 100644 --- a/arch/arm/src/stm32/stm32_sdio.c +++ b/arch/arm/src/stm32/stm32_sdio.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_sdio.c * - * Copyright (C) 2009, 2011-2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2011-2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -52,6 +52,7 @@ #include #include #include +#include #include #include @@ -2853,8 +2854,18 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) struct stm32_dev_s *priv = &g_sdiodev; /* Initialize the SDIO slot structure */ + /* Initialize semaphores */ sem_init(&priv->waitsem, 0, 0); + + /* The waitsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); + + /* Create a watchdog timer */ + priv->waitwdog = wd_create(); DEBUGASSERT(priv->waitwdog); diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index 3e6aff9620..47ac3abf39 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -53,6 +53,7 @@ #include #include #include +#include #include #include @@ -3214,8 +3215,18 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) } /* Initialize the SDIO slot structure */ + /* Initialize semaphores */ sem_init(&priv->waitsem, 0, 0); + + /* The waitsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); + + /* Create a watchdog timer */ + priv->waitwdog = wd_create(); DEBUGASSERT(priv->waitwdog); -- GitLab From d28181da1042f8527f57b656c917c840d3a8285e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 17:05:53 -0600 Subject: [PATCH 321/734] arch: Disable priority inheritance on all semaphores used for signaling in all USB host drivers --- arch/arm/src/efm32/efm32_usbhost.c | 14 ++++++++++++++ arch/arm/src/lpc17xx/lpc17_usbhost.c | 19 +++++++++++++++++-- arch/arm/src/lpc31xx/lpc31_ehci.c | 19 +++++++++++++++++++ arch/arm/src/lpc43xx/lpc43_ehci.c | 19 +++++++++++++++++++ arch/arm/src/sama5/sam_ehci.c | 19 +++++++++++++++++++ arch/arm/src/sama5/sam_ohci.c | 15 ++++++++++++++- arch/arm/src/stm32/stm32_otgfshost.c | 14 ++++++++++++++ arch/arm/src/stm32/stm32_otghshost.c | 14 ++++++++++++++ arch/arm/src/stm32f7/stm32_otghost.c | 14 ++++++++++++++ arch/arm/src/stm32l4/stm32l4_otgfshost.c | 14 ++++++++++++++ 10 files changed, 158 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/efm32/efm32_usbhost.c b/arch/arm/src/efm32/efm32_usbhost.c index 19f80bc43d..be9bbccf23 100644 --- a/arch/arm/src/efm32/efm32_usbhost.c +++ b/arch/arm/src/efm32/efm32_usbhost.c @@ -52,6 +52,7 @@ #include #include #include +#include #include #include #include @@ -5157,6 +5158,12 @@ static inline void efm32_sw_initialize(FAR struct efm32_usbhost_s *priv) sem_init(&priv->pscsem, 0, 0); sem_init(&priv->exclsem, 0, 1); + /* The pscsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->pscsem, SEM_PRIO_NONE); + /* Initialize the driver state data */ priv->smstate = SMSTATE_DETACHED; @@ -5172,8 +5179,15 @@ static inline void efm32_sw_initialize(FAR struct efm32_usbhost_s *priv) for (i = 0; i < EFM32_MAX_TX_FIFOS; i++) { FAR struct efm32_chan_s *chan = &priv->chan[i]; + chan->chidx = i; + + /* The waitsem semaphore is used for signaling and, hence, should not + * have priority inheritance enabled. + */ + sem_init(&chan->waitsem, 0, 0); + sem_setprotocol(&chan->waitsem, SEM_PRIO_NONE); } } diff --git a/arch/arm/src/lpc17xx/lpc17_usbhost.c b/arch/arm/src/lpc17xx/lpc17_usbhost.c index d8d02f629c..59268f94a5 100644 --- a/arch/arm/src/lpc17xx/lpc17_usbhost.c +++ b/arch/arm/src/lpc17xx/lpc17_usbhost.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/lpc17xx/lpc17_usbhost.c * - * Copyright (C) 2010-2012, 2014-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2010-2012, 2014-2016 Gregory Nutt. All rights reserved. * Authors: Rafael Noronha * Gregory Nutt * @@ -51,6 +51,7 @@ #include #include +#include #include #include #include @@ -2262,10 +2263,12 @@ static int lpc17_epalloc(struct usbhost_driver_s *drvr, uinfo("EP%d CTRL:%08x\n", epdesc->addr, ed->hw.ctrl); /* Initialize the semaphore that is used to wait for the endpoint - * WDH event. + * WDH event. The wdhsem semaphore is used for signaling and, hence, + * should not have priority inheritance enabled. */ sem_init(&ed->wdhsem, 0, 0); + sem_setprotocol(&priv->wdhsem, SEM_PRIO_NONE); /* Link the common tail TD to the ED's TD list */ @@ -3639,6 +3642,12 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller) sem_init(&priv->pscsem, 0, 0); sem_init(&priv->exclsem, 0, 1); + /* The pscsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->pscsem, SEM_PRIO_NONE); + #ifndef CONFIG_USBHOST_INT_DISABLE priv->ininterval = MAX_PERINTERVAL; priv->outinterval = MAX_PERINTERVAL; @@ -3719,7 +3728,13 @@ struct usbhost_connection_s *lpc17_usbhost_initialize(int controller) memset((void *)HCCA, 0, sizeof(struct ohci_hcca_s)); memset((void *)TDTAIL, 0, sizeof(struct ohci_gtd_s)); memset((void *)EDCTRL, 0, sizeof(struct lpc17_ed_s)); + + /* The EDCTRL wdhsem semaphore is used for signaling and, hence, should + * not have priority inheritance enabled. + */ + sem_init(&EDCTRL->wdhsem, 0, 0); + sem_setprotocol(&EDCTRL->wdhsem, SEM_PRIO_NONE); /* Initialize user-configurable EDs */ diff --git a/arch/arm/src/lpc31xx/lpc31_ehci.c b/arch/arm/src/lpc31xx/lpc31_ehci.c index e37abe4997..345ec24dc6 100644 --- a/arch/arm/src/lpc31xx/lpc31_ehci.c +++ b/arch/arm/src/lpc31xx/lpc31_ehci.c @@ -52,6 +52,7 @@ #include #include #include +#include #include #include #include @@ -3931,7 +3932,13 @@ static int lpc31_epalloc(FAR struct usbhost_driver_s *drvr, epinfo->maxpacket = epdesc->mxpacketsize; epinfo->xfrtype = epdesc->xfrtype; epinfo->speed = hport->speed; + + /* The iocsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + sem_init(&epinfo->iocsem, 0, 0); + sem_setprotocol(&epinfo->iocsem, SEM_PRIO_NONE); /* Success.. return an opaque reference to the endpoint information structure * instance @@ -4916,6 +4923,12 @@ FAR struct usbhost_connection_s *lpc31_ehci_initialize(int controller) sem_init(&g_ehci.exclsem, 0, 1); sem_init(&g_ehci.pscsem, 0, 0); + /* The pscsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&g_ehci.pscsem, SEM_PRIO_NONE); + /* Initialize EP0 */ sem_init(&g_ehci.ep0.iocsem, 0, 1); @@ -4952,7 +4965,13 @@ FAR struct usbhost_connection_s *lpc31_ehci_initialize(int controller) rhport->ep0.xfrtype = USB_EP_ATTR_XFER_CONTROL; rhport->ep0.speed = USB_SPEED_FULL; rhport->ep0.maxpacket = 8; + + /* The port iocsem semaphore is used for signaling and, hence, + * should not have priority inheritance enabled. + */ + sem_init(&rhport->ep0.iocsem, 0, 0); + sem_setprotocol(&rhport->iocsem, SEM_PRIO_NONE); /* Initialize the public port representation */ diff --git a/arch/arm/src/lpc43xx/lpc43_ehci.c b/arch/arm/src/lpc43xx/lpc43_ehci.c index ae462f80b4..2893369ced 100644 --- a/arch/arm/src/lpc43xx/lpc43_ehci.c +++ b/arch/arm/src/lpc43xx/lpc43_ehci.c @@ -51,6 +51,7 @@ #include #include #include +#include #include #include #include @@ -3768,7 +3769,13 @@ static int lpc43_epalloc(FAR struct usbhost_driver_s *drvr, epinfo->maxpacket = epdesc->mxpacketsize; epinfo->xfrtype = epdesc->xfrtype; epinfo->speed = hport->speed; + + /* The endpoint iocsem semaphore is used for signaling and, hence, + * should not have priority inheritance enabled. + */ + sem_init(&epinfo->iocsem, 0, 0); + sem_setprotocol(&epinfo->iocsem, SEM_PRIO_NONE); /* Success.. return an opaque reference to the endpoint information structure * instance @@ -4747,6 +4754,12 @@ FAR struct usbhost_connection_s *lpc43_ehci_initialize(int controller) sem_init(&g_ehci.exclsem, 0, 1); sem_init(&g_ehci.pscsem, 0, 0); + /* The pscsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&g_ehci.pscsem, SEM_PRIO_NONE); + /* Initialize EP0 */ sem_init(&g_ehci.ep0.iocsem, 0, 1); @@ -4783,7 +4796,13 @@ FAR struct usbhost_connection_s *lpc43_ehci_initialize(int controller) rhport->ep0.xfrtype = USB_EP_ATTR_XFER_CONTROL; rhport->ep0.speed = USB_SPEED_FULL; rhport->ep0.maxpacket = 8; + + /* The EP0 iocsem semaphore is used for signaling and, hence, should + * not have priority inheritance enabled. + */ + sem_init(&rhport->ep0.iocsem, 0, 0); + sem_setprotocol(&rhport->ep0.iocsem, SEM_PRIO_NONE); /* Initialize the public port representation */ diff --git a/arch/arm/src/sama5/sam_ehci.c b/arch/arm/src/sama5/sam_ehci.c index 78135e3e8d..6065a04d50 100644 --- a/arch/arm/src/sama5/sam_ehci.c +++ b/arch/arm/src/sama5/sam_ehci.c @@ -51,6 +51,7 @@ #include #include #include +#include #include #include #include @@ -3752,7 +3753,13 @@ static int sam_epalloc(FAR struct usbhost_driver_s *drvr, epinfo->maxpacket = epdesc->mxpacketsize; epinfo->xfrtype = epdesc->xfrtype; epinfo->speed = hport->speed; + + /* The endpoint iocsem semaphore is used for signaling and, hence, + * should not have priority inheritance enabled. + */ + sem_init(&epinfo->iocsem, 0, 0); + sem_setprotocol(&epinfo->iocsem, SEM_PRIO_NONE); /* Success.. return an opaque reference to the endpoint information structure * instance @@ -4787,6 +4794,12 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller) sem_init(&g_ehci.exclsem, 0, 1); sem_init(&g_ehci.pscsem, 0, 0); + /* The pscsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&g_ehci.pscsem, SEM_PRIO_NONE); + /* Initialize EP0 */ sem_init(&g_ehci.ep0.iocsem, 0, 1); @@ -4823,7 +4836,13 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller) rhport->ep0.xfrtype = USB_EP_ATTR_XFER_CONTROL; rhport->ep0.speed = USB_SPEED_FULL; rhport->ep0.maxpacket = 8; + + /* The endpoint 0 iocsem semaphore is used for signaling and, hence, + * should not have priority inheritance enabled. + */ + sem_init(&rhport->ep0.iocsem, 0, 0); + sem_setprotocol(&rhport->ep0.iocsem, SEM_PRIO_NONE); /* Initialize the public port representation */ diff --git a/arch/arm/src/sama5/sam_ohci.c b/arch/arm/src/sama5/sam_ohci.c index 7d4533dca6..b4a6b03f92 100644 --- a/arch/arm/src/sama5/sam_ohci.c +++ b/arch/arm/src/sama5/sam_ohci.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/sama5/sam_ohci.c * - * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2015-2016 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -51,6 +51,7 @@ #include #include #include +#include #include #include #include @@ -2664,6 +2665,12 @@ static int sam_epalloc(struct usbhost_driver_s *drvr, sem_init(&eplist->wdhsem, 0, 0); + /* The wdhsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&eplist->wdhsem, SEM_PRIO_NONE); + /* We must have exclusive access to the ED pool, the bulk list, the periodic list * and the interrupt table. */ @@ -3903,6 +3910,12 @@ struct usbhost_connection_s *sam_ohci_initialize(int controller) sem_init(&g_ohci.pscsem, 0, 0); sem_init(&g_ohci.exclsem, 0, 1); + /* The pscsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&g_ohci.pscsem, SEM_PRIO_NONE); + #ifndef CONFIG_USBHOST_INT_DISABLE g_ohci.ininterval = MAX_PERINTERVAL; g_ohci.outinterval = MAX_PERINTERVAL; diff --git a/arch/arm/src/stm32/stm32_otgfshost.c b/arch/arm/src/stm32/stm32_otgfshost.c index 9b3c48102d..3feb0924c0 100644 --- a/arch/arm/src/stm32/stm32_otgfshost.c +++ b/arch/arm/src/stm32/stm32_otgfshost.c @@ -52,6 +52,7 @@ #include #include #include +#include #include #include #include @@ -5091,6 +5092,12 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv) sem_init(&priv->pscsem, 0, 0); sem_init(&priv->exclsem, 0, 1); + /* The pscsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->pscsem, SEM_PRIO_NONE); + /* Initialize the driver state data */ priv->smstate = SMSTATE_DETACHED; @@ -5106,8 +5113,15 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv) for (i = 0; i < STM32_MAX_TX_FIFOS; i++) { FAR struct stm32_chan_s *chan = &priv->chan[i]; + chan->chidx = i; + + /* The waitsem semaphore is used for signaling and, hence, should not + * have priority inheritance enabled. + */ + sem_init(&chan->waitsem, 0, 0); + sem_setprotocol(&chan->waitsem, SEM_PRIO_NONE); } } diff --git a/arch/arm/src/stm32/stm32_otghshost.c b/arch/arm/src/stm32/stm32_otghshost.c index da0a114aa8..aec4fc37d5 100644 --- a/arch/arm/src/stm32/stm32_otghshost.c +++ b/arch/arm/src/stm32/stm32_otghshost.c @@ -52,6 +52,7 @@ #include #include #include +#include #include #include #include @@ -5091,6 +5092,12 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv) sem_init(&priv->pscsem, 0, 0); sem_init(&priv->exclsem, 0, 1); + /* The pscsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->pscsem, SEM_PRIO_NONE); + /* Initialize the driver state data */ priv->smstate = SMSTATE_DETACHED; @@ -5106,8 +5113,15 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv) for (i = 0; i < STM32_MAX_TX_FIFOS; i++) { FAR struct stm32_chan_s *chan = &priv->chan[i]; + chan->chidx = i; + + /* The waitsem semaphore is used for signaling and, hence, should not + * have priority inheritance enabled. + */ + sem_init(&chan->waitsem, 0, 0); + sem_setprotocol(&chan->waitsem, SEM_PRIO_NONE); } } diff --git a/arch/arm/src/stm32f7/stm32_otghost.c b/arch/arm/src/stm32f7/stm32_otghost.c index 37677a614d..12488c262f 100644 --- a/arch/arm/src/stm32f7/stm32_otghost.c +++ b/arch/arm/src/stm32f7/stm32_otghost.c @@ -53,6 +53,7 @@ #include #include #include +#include #include #include #include @@ -5089,6 +5090,12 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv) sem_init(&priv->pscsem, 0, 0); sem_init(&priv->exclsem, 0, 1); + /* The pscsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->pscsem, SEM_PRIO_NONE); + /* Initialize the driver state data */ priv->smstate = SMSTATE_DETACHED; @@ -5104,8 +5111,15 @@ static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv) for (i = 0; i < STM32_MAX_TX_FIFOS; i++) { FAR struct stm32_chan_s *chan = &priv->chan[i]; + chan->chidx = i; + + /* The waitsem semaphore is used for signaling and, hence, should not + * have priority inheritance enabled. + */ + sem_init(&chan->waitsem, 0, 0); + sem_setprotocol(&chan->waitsem, SEM_PRIO_NONE); } } diff --git a/arch/arm/src/stm32l4/stm32l4_otgfshost.c b/arch/arm/src/stm32l4/stm32l4_otgfshost.c index 428a7f80cf..d47295f429 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfshost.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfshost.c @@ -53,6 +53,7 @@ #include #include #include +#include #include #include #include @@ -5096,6 +5097,12 @@ static inline void stm32l4_sw_initialize(FAR struct stm32l4_usbhost_s *priv) sem_init(&priv->pscsem, 0, 0); sem_init(&priv->exclsem, 0, 1); + /* The pscsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->pscsem, SEM_PRIO_NONE); + /* Initialize the driver state data */ priv->smstate = SMSTATE_DETACHED; @@ -5111,8 +5118,15 @@ static inline void stm32l4_sw_initialize(FAR struct stm32l4_usbhost_s *priv) for (i = 0; i < STM32L4_MAX_TX_FIFOS; i++) { FAR struct stm32l4_chan_s *chan = &priv->chan[i]; + chan->chidx = i; + + /* The waitsem semaphore is used for signaling and, hence, should not + * have priority inheritance enabled. + */ + sem_init(&chan->waitsem, 0, 0); + sem_setprotocol(&chan->waitsem, SEM_PRIO_NONE); } } -- GitLab From 77a0b6c26aa95cb89b7466b9fc534245bfbbf9b8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 17:12:49 -0600 Subject: [PATCH 322/734] graphics/, libnx/: Disable priority inheritance on all semaphores used for signaling --- graphics/nxterm/nxterm_register.c | 20 +++++++------------- libnx/nxmu/nx_bitmap.c | 28 ++++++++-------------------- libnx/nxmu/nx_getrectangle.c | 28 ++++++++-------------------- 3 files changed, 23 insertions(+), 53 deletions(-) diff --git a/graphics/nxterm/nxterm_register.c b/graphics/nxterm/nxterm_register.c index 41cd456789..d1d99d16a4 100644 --- a/graphics/nxterm/nxterm_register.c +++ b/graphics/nxterm/nxterm_register.c @@ -1,7 +1,7 @@ /**************************************************************************** * nuttx/graphics/nxterm/nxterm_register.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -48,22 +48,11 @@ #include #include +#include #include #include "nxterm.h" -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -104,7 +93,12 @@ FAR struct nxterm_state_s * #endif #ifdef CONFIG_NXTERM_NXKBDIN + /* The waitsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + sem_init(&priv->waitsem, 0, 0); + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); #endif /* Select the font */ diff --git a/libnx/nxmu/nx_bitmap.c b/libnx/nxmu/nx_bitmap.c index 0d8ec93f40..9c69291572 100644 --- a/libnx/nxmu/nx_bitmap.c +++ b/libnx/nxmu/nx_bitmap.c @@ -1,7 +1,7 @@ /**************************************************************************** * libnx/nxmu/nx_bitmap.c * - * Copyright (C) 2008-2009, 2011-2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2008-2009, 2011-2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -46,25 +46,7 @@ #include #include -/**************************************************************************** - * Pre-Processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ +#include /**************************************************************************** * Public Functions @@ -137,6 +119,12 @@ int nx_bitmap(NXWINDOW hwnd, FAR const struct nxgl_rect_s *dest, return ret; } + /* The sem_done semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + (void)sem_setprotocol(&sem_done, SEM_PRIO_NONE); + /* Forward the fill command to the server */ ret = nxmu_sendwindow(wnd, &outmsg, sizeof(struct nxsvrmsg_bitmap_s)); diff --git a/libnx/nxmu/nx_getrectangle.c b/libnx/nxmu/nx_getrectangle.c index 3bac5a3ae9..9420d02df5 100644 --- a/libnx/nxmu/nx_getrectangle.c +++ b/libnx/nxmu/nx_getrectangle.c @@ -1,7 +1,7 @@ /**************************************************************************** * libnx/nxmu/nx_getrectangle.c * - * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -47,25 +47,7 @@ #include #include -/**************************************************************************** - * Pre-Processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ +#include /**************************************************************************** * Public Functions @@ -131,6 +113,12 @@ int nx_getrectangle(NXWINDOW hwnd, FAR const struct nxgl_rect_s *rect, return ret; } + /* The sem_done semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + (void)sem_setprotocol(&sem_done, SEM_PRIO_NONE); + /* Forward the fill command to the server */ ret = nxmu_sendwindow(wnd, &outmsg, sizeof(struct nxsvrmsg_getrectangle_s)); -- GitLab From d8fecba333d166b363184f1252b7dff286085493 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 17:19:51 -0600 Subject: [PATCH 323/734] arch: Disable priority inheritance on all semaphores used for signaling in all RNG drivers --- arch/arm/src/sama5/sam_trng.c | 10 ++++++++++ arch/arm/src/samv7/sam_trng.c | 10 ++++++++++ arch/arm/src/stm32l4/stm32l4_rng.c | 8 ++++++-- 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/sama5/sam_trng.c b/arch/arm/src/sama5/sam_trng.c index 4c0f5ab1bc..c724612456 100644 --- a/arch/arm/src/sama5/sam_trng.c +++ b/arch/arm/src/sama5/sam_trng.c @@ -52,6 +52,7 @@ #include #include +#include #include #include @@ -352,9 +353,18 @@ static int sam_rng_initialize(void) /* Initialize the device structure */ memset(&g_trngdev, 0, sizeof(struct trng_dev_s)); + + /* Initialize semphores */ + sem_init(&g_trngdev.exclsem, 0, 1); sem_init(&g_trngdev.waitsem, 0, 0); + /* The waitsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&g_trngdev.waitsem, SEM_PRIO_NONE); + /* Enable clocking to the TRNG */ sam_trng_enableclk(); diff --git a/arch/arm/src/samv7/sam_trng.c b/arch/arm/src/samv7/sam_trng.c index d6cc16eb0b..6fee91e850 100644 --- a/arch/arm/src/samv7/sam_trng.c +++ b/arch/arm/src/samv7/sam_trng.c @@ -53,6 +53,7 @@ #include #include +#include #include #include @@ -353,9 +354,18 @@ static int sam_rng_initialize(void) /* Initialize the device structure */ memset(&g_trngdev, 0, sizeof(struct trng_dev_s)); + + /* Initialize semaphores */ + sem_init(&g_trngdev.exclsem, 0, 1); sem_init(&g_trngdev.waitsem, 0, 0); + /* The waitsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&g_trngdev.waitsem, SEM_PRIO_NONE); + /* Enable clocking to the TRNG */ sam_trng_enableclk(); diff --git a/arch/arm/src/stm32l4/stm32l4_rng.c b/arch/arm/src/stm32l4/stm32l4_rng.c index a544847061..abd2851037 100644 --- a/arch/arm/src/stm32l4/stm32l4_rng.c +++ b/arch/arm/src/stm32l4/stm32l4_rng.c @@ -47,6 +47,7 @@ #include #include +#include #include #include @@ -259,11 +260,14 @@ static ssize_t stm32l4_rngread(struct file *filep, char *buffer, size_t buflen) { /* We've got the device semaphore, proceed with reading */ - /* Initialize the operation semaphore with 0 for blocking until - * the buffer is filled from interrupts. + /* Initialize the operation semaphore with 0 for blocking until the + * buffer is filled from interrupts. The waitsem semaphore is used + * for signaling and, hence, should not have priority inheritance + * enabled. */ sem_init(&g_rngdev.rd_readsem, 0, 0); + sem_setprotocol(&g_rngdev.rd_readsem, SEM_PRIO_NONE); g_rngdev.rd_buflen = buflen; g_rngdev.rd_buf = buffer; -- GitLab From 0a5b4f684a86a7a4c50cc5f84b52c65e2d868cff Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 17:38:26 -0600 Subject: [PATCH 324/734] arch: Disable priority inheritance on all semaphores used for signaling in the rest of the MCU drivers --- arch/arm/src/calypso/calypso_keypad.c | 7 ++++++- arch/arm/src/sama5/sam_nand.c | 14 +++++++++++++- arch/arm/src/sama5/sam_tsd.c | 8 +++++++- arch/arm/src/stm32/stm32_1wire.c | 7 +++++++ arch/arm/src/stm32/stm32_dma2d.c | 9 +++++++-- arch/arm/src/stm32/stm32_ltdc.c | 9 +++++++-- arch/arm/src/tiva/tiva_ssi.c | 6 ++++++ arch/sim/src/up_touchscreen.c | 10 ++++++++++ arch/sim/src/up_uartwait.c | 7 +++++++ arch/xtensa/src/esp32/esp32_cpustart.c | 7 +++++++ 10 files changed, 77 insertions(+), 7 deletions(-) diff --git a/arch/arm/src/calypso/calypso_keypad.c b/arch/arm/src/calypso/calypso_keypad.c index 2430667ca5..1d9b11b98a 100644 --- a/arch/arm/src/calypso/calypso_keypad.c +++ b/arch/arm/src/calypso/calypso_keypad.c @@ -36,6 +36,7 @@ #include #include +#include #include #include @@ -360,9 +361,13 @@ int calypso_kbd_irq(int irq, uint32_t * regs) void up_keypad(void) { - /* Semaphore; helps leaving IRQ ctx as soon as possible */ + /* kbssem semaphore helps leaving IRQ ctx as soon as possible. This + * semaphore is used for signaling and, hence, should not have priority + * inheritance enabled. + */ sem_init(&kbdsem, 0, 0); + sem_setprotocol(&kbdsem, SEM_PRIO_NONE); /* Drive cols low in idle state such that all buttons cause events */ diff --git a/arch/arm/src/sama5/sam_nand.c b/arch/arm/src/sama5/sam_nand.c index 0e6757c073..1ac8e2a9ba 100644 --- a/arch/arm/src/sama5/sam_nand.c +++ b/arch/arm/src/sama5/sam_nand.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/sama5/sam_nand.c * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: @@ -58,6 +58,7 @@ #include #include +#include #include #include #include @@ -2944,7 +2945,12 @@ struct mtd_dev_s *sam_nand_initialize(int cs) priv->cs = cs; #ifdef CONFIG_SAMA5_NAND_DMA + /* The waitsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + sem_init(&priv->waitsem, 0, 0); + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); #endif /* Perform one-time, global NFC/PMECC initialization */ @@ -2956,8 +2962,14 @@ struct mtd_dev_s *sam_nand_initialize(int cs) #if NAND_NBANKS > 1 sem_init(&g_nand.exclsem, 0, 1); #endif + #ifdef CONFIG_SAMA5_NAND_HSMCINTERRUPTS + /* The waitsem semaphore is used for signaling and, hence, should not + * have priority inheritance enabled. + */ + sem_init(&g_nand.waitsem, 0, 0); + sem_setprotocol(&g_nand.waitsem, SEM_PRIO_NONE); #endif /* Enable the NAND FLASH Controller (The NFC is always used) */ diff --git a/arch/arm/src/sama5/sam_tsd.c b/arch/arm/src/sama5/sam_tsd.c index edb2199f36..403aa93f75 100644 --- a/arch/arm/src/sama5/sam_tsd.c +++ b/arch/arm/src/sama5/sam_tsd.c @@ -66,6 +66,7 @@ #include #include #include +#include #include #include @@ -1669,7 +1670,12 @@ int sam_tsd_register(struct sam_adc_s *adc, int minor) priv->threshx = INVALID_THRESHOLD; /* Initialize thresholding logic */ priv->threshy = INVALID_THRESHOLD; /* Initialize thresholding logic */ - sem_init(&priv->waitsem, 0, 0); /* Initialize pen event wait semaphore */ + /* Initialize pen event wait semaphore. This semaphore is used for + * signaling and, hence, should not have priority inheritance enabled. + */ + + sem_init(&priv->waitsem, 0, 0); + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); /* Register the device as an input device */ diff --git a/arch/arm/src/stm32/stm32_1wire.c b/arch/arm/src/stm32/stm32_1wire.c index 00f24fc019..952f2777ec 100644 --- a/arch/arm/src/stm32/stm32_1wire.c +++ b/arch/arm/src/stm32/stm32_1wire.c @@ -56,6 +56,7 @@ #include #include #include +#include #include #include @@ -744,6 +745,12 @@ static inline void stm32_1wire_sem_init(FAR struct stm32_1wire_priv_s *priv) { sem_init(&priv->sem_excl, 0, 1); sem_init(&priv->sem_isr, 0, 0); + + /* The sem_isr semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE); } /**************************************************************************** diff --git a/arch/arm/src/stm32/stm32_dma2d.c b/arch/arm/src/stm32/stm32_dma2d.c index db76245708..c4ef73fc2b 100644 --- a/arch/arm/src/stm32/stm32_dma2d.c +++ b/arch/arm/src/stm32/stm32_dma2d.c @@ -49,8 +49,9 @@ #include #include -#include #include +#include +#include #include #include @@ -2167,9 +2168,13 @@ int up_dma2dinitialize(void) sem_init(&g_lock, 0, 1); - /* Initialize the semaphore for interrupt handling */ + /* Initialize the semaphore for interrupt handling. This waitsem + * semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ sem_init(g_interrupt.sem, 0, 0); + sem_setprotocol(g_interrupt.sem, SEM_PRIO_NONE); #ifdef CONFIG_STM32_DMA2D_L8 /* Enable dma2d transfer and clut loading interrupts only */ diff --git a/arch/arm/src/stm32/stm32_ltdc.c b/arch/arm/src/stm32/stm32_ltdc.c index 442af257dd..ebaeff8d47 100644 --- a/arch/arm/src/stm32/stm32_ltdc.c +++ b/arch/arm/src/stm32/stm32_ltdc.c @@ -49,8 +49,9 @@ #include #include -#include #include +#include +#include #include #include @@ -1287,9 +1288,13 @@ static void stm32_global_configure(void) sem_init(&g_lock, 0, 1); - /* Initialize the semaphore for interrupt handling */ + /* Initialize the semaphore for interrupt handling. This waitsem + * semaphore is used for signaling and, hence, should not have priority + * inheritance enabled. + */ sem_init(g_interrupt.sem, 0, 0); + sem_setprotocol(g_interrupt.sem, SEM_PRIO_NONE); /* Attach LTDC interrupt vector */ diff --git a/arch/arm/src/tiva/tiva_ssi.c b/arch/arm/src/tiva/tiva_ssi.c index 882d6460df..6c2a92fbcc 100644 --- a/arch/arm/src/tiva/tiva_ssi.c +++ b/arch/arm/src/tiva/tiva_ssi.c @@ -47,6 +47,7 @@ #include #include +#include #include #include @@ -1635,7 +1636,12 @@ FAR struct spi_dev_s *tiva_ssibus_initialize(int port) /* Initialize the state structure */ #ifndef CONFIG_SSI_POLLWAIT + /* The xfrsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + sem_init(&priv->xfrsem, 0, 0); + sem_setprotocol(&priv->xfrsem, SEM_PRIO_NONE); #endif sem_init(&priv->exclsem, 0, 1); diff --git a/arch/sim/src/up_touchscreen.c b/arch/sim/src/up_touchscreen.c index a56870c850..4c327bb683 100644 --- a/arch/sim/src/up_touchscreen.c +++ b/arch/sim/src/up_touchscreen.c @@ -56,6 +56,7 @@ #include #include #include +#include #include #include @@ -657,9 +658,18 @@ int board_tsc_setup(int minor) /* Initialize the touchscreen device driver instance */ memset(priv, 0, sizeof(struct up_dev_s)); + + /* Initialize semaphores */ + sem_init(&priv->devsem, 0, 1); /* Initialize device structure semaphore */ sem_init(&priv->waitsem, 0, 0); /* Initialize pen event wait semaphore */ + /* The waitsem semaphore is used for signaling and, hence, should not have + * priority inheritance enabled. + */ + + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); + priv->minor = minor; /* Register the device as an input device */ diff --git a/arch/sim/src/up_uartwait.c b/arch/sim/src/up_uartwait.c index 9f69717116..50f6b5f281 100644 --- a/arch/sim/src/up_uartwait.c +++ b/arch/sim/src/up_uartwait.c @@ -39,6 +39,8 @@ #include +#include + #include "up_internal.h" /**************************************************************************** @@ -57,7 +59,12 @@ static sem_t g_uartavail; void simuart_initialize(void) { + /* The g_uartavail semaphore is used for signaling and, hence, should not + * have priority inheritance enabled. + */ + sem_init(&g_uartavail, 0, 0); + sem_setprotocol(&g_uartavail, SEM_PRIO_NONE); } /**************************************************************************** diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c index 40f9882a5e..3a603579b6 100644 --- a/arch/xtensa/src/esp32/esp32_cpustart.c +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -46,6 +46,7 @@ #include #include +#include #include "sched/sched.h" #include "xtensa.h" @@ -259,7 +260,13 @@ int up_cpu_start(int cpu) /* Start CPU1 */ sinfo("Starting CPU%d\n", cpu); + + /* The waitsem semaphore is used for signaling and, hence, should not + * have priority inheritance enabled. + */ + sem_init(&g_appcpu_interlock, 0, 0); + sem_setprotocol(&g_appcpu_interlock, SEM_PRIO_NONE); regval = getreg32(DPORT_APPCPU_CTRL_B_REG); regval |= DPORT_APPCPU_CLKGATE_EN; -- GitLab From 5cfb83ec81cf87702b15a6b7e3561f2f83f7719b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 17:47:09 -0600 Subject: [PATCH 325/734] ESP32: File repeated in Make.defs --- arch/xtensa/src/esp32/Make.defs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 0e13e3b1db..39a67813c6 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -84,7 +84,7 @@ endif CHIP_ASRCS = CHIP_CSRCS = esp32_allocateheap.c esp32_clockconfig.c esp32_cpuint.c CHIP_CSRCS += esp32_gpio.c esp32_intdecode.c esp32_irq.c esp32_region.c -CHIP_CSRCS += esp32_start.c esp32_timerisr.c +CHIP_CSRCS += esp32_timerisr.c # Configuration-dependent ESP32 files -- GitLab From 6ff6cca1a03ad2db924a5a9963412c07189cb096 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 17:48:36 -0600 Subject: [PATCH 326/734] Fix some mispellings of semaphore --- drivers/can.c | 2 +- net/icmp/icmp_ping.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/can.c b/drivers/can.c index e896d492f4..dd810ebcd1 100644 --- a/drivers/can.c +++ b/drivers/can.c @@ -1178,7 +1178,7 @@ int can_register(FAR const char *path, FAR struct can_dev_s *dev) for (i = 0; i < CONFIG_CAN_NPENDINGRTR; i++) { - /* Initialize wait semahores. These semaphores are used for signaling + /* Initialize wait semaphores. These semaphores are used for signaling * and should not have priority inheritance enabled. */ diff --git a/net/icmp/icmp_ping.c b/net/icmp/icmp_ping.c index 0c7f6e1627..96dd811cce 100644 --- a/net/icmp/icmp_ping.c +++ b/net/icmp/icmp_ping.c @@ -51,7 +51,7 @@ #include #include -#include +#include #include #include #include -- GitLab From 73fc186beb1ddec498c874da5f4da00ac6ff1cd4 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 18:51:38 -0600 Subject: [PATCH 327/734] sem_setprotocol: Handle a case of missing proxy for sem_setprotocol. Reorder so that (1) this error is avoided, and (2) >No proxy is needed if priority inheritance is not enabled. --- libc/semaphore/Make.defs | 4 ++ libc/semaphore/sem_setprotocol.c | 114 ++++++++++++++++++++++++++++++ sched/semaphore/Make.defs | 4 +- sched/semaphore/sem_setprotocol.c | 8 +-- syscall/syscall.csv | 2 +- 5 files changed, 125 insertions(+), 7 deletions(-) create mode 100644 libc/semaphore/sem_setprotocol.c diff --git a/libc/semaphore/Make.defs b/libc/semaphore/Make.defs index cafa18b65a..6c91f068cd 100644 --- a/libc/semaphore/Make.defs +++ b/libc/semaphore/Make.defs @@ -37,6 +37,10 @@ CSRCS += sem_init.c sem_getprotocol.c sem_getvalue.c +ifneq ($(CONFIG_PRIORITY_INHERITANCE),y) +CSRCS += sem_setprotocol.c +endif + # Add the semaphore directory to the build DEPPATH += --dep-path semaphore diff --git a/libc/semaphore/sem_setprotocol.c b/libc/semaphore/sem_setprotocol.c new file mode 100644 index 0000000000..38336a31a0 --- /dev/null +++ b/libc/semaphore/sem_setprotocol.c @@ -0,0 +1,114 @@ +/**************************************************************************** + * libc/semaphore/sem_setprotocol.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#ifndef CONFIG_PRIORITY_INHERITANCE + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: sem_setprotocol + * + * Description: + * Set semaphore protocol attribute. + * + * One particularly important use of this furnction is when a semaphore + * is used for inter-task communication like: + * + * TASK A TASK B + * sem_init(sem, 0, 0); + * sem_wait(sem); + * sem_post(sem); + * Awakens as holder + * + * In this case priority inheritance can interfere with the operation of + * the semaphore. The problem is that when TASK A is restarted it is a + * holder of the semaphore. However, it never calls sem_post(sem) so it + * becomes *permanently* a holder of the semaphore and may have its + * priority boosted when any other task tries to acquire the semaphore. + * + * The fix is to call sem_setprotocol(SEM_PRIO_NONE) immediately after + * the sem_init() call so that there will be no priority inheritance + * operations on this semaphore. + * + * Parameters: + * sem - A pointer to the semaphore whose attributes are to be + * modified + * protocol - The new protocol to use + * + * Return Value: + * 0 if successful. Otherwise, -1 is returned and the errno value is set + * appropriately. + * + ****************************************************************************/ + +int sem_setprotocol(FAR sem_t *sem, int protocol) +{ + int errcode; + + DEBUGASSERT(sem != NULL); + + switch (protocol) + { + case SEM_PRIO_NONE: + return OK; + + case SEM_PRIO_INHERIT: + case SEM_PRIO_PROTECT: + errcode = ENOSYS; + break; + + default: + errcode = EINVAL; + break; + } + + set_errno(errcode); + return ERROR; +} + +#endif /* !CONFIG_PRIORITY_INHERITANCE */ diff --git a/sched/semaphore/Make.defs b/sched/semaphore/Make.defs index 93fd35a0d0..7eb1740424 100644 --- a/sched/semaphore/Make.defs +++ b/sched/semaphore/Make.defs @@ -37,10 +37,10 @@ CSRCS += sem_destroy.c sem_wait.c sem_trywait.c sem_tickwait.c CSRCS += sem_timedwait.c sem_timeout.c sem_post.c sem_recover.c -CSRCS += sem_reset.c sem_setprotocol.c sem_waitirq.c +CSRCS += sem_reset.c sem_waitirq.c ifeq ($(CONFIG_PRIORITY_INHERITANCE),y) -CSRCS += sem_initialize.c sem_holder.c +CSRCS += sem_initialize.c sem_holder.c sem_setprotocol.c endif ifeq ($(CONFIG_SPINLOCK),y) diff --git a/sched/semaphore/sem_setprotocol.c b/sched/semaphore/sem_setprotocol.c index 6f4392bcce..89764f6ad7 100644 --- a/sched/semaphore/sem_setprotocol.c +++ b/sched/semaphore/sem_setprotocol.c @@ -46,6 +46,8 @@ #include "semaphore/semaphore.h" +#ifdef CONFIG_PRIORITY_INHERITANCE + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -95,7 +97,6 @@ int sem_setprotocol(FAR sem_t *sem, int protocol) switch (protocol) { case SEM_PRIO_NONE: -#ifdef CONFIG_PRIORITY_INHERITANCE /* Disable priority inheritance */ sem->flags |= PRIOINHERIT_FLAGS_DISABLE; @@ -103,16 +104,13 @@ int sem_setprotocol(FAR sem_t *sem, int protocol) /* Remove any current holders */ sem_destroyholder(sem); -#endif return OK; case SEM_PRIO_INHERIT: -#ifdef CONFIG_PRIORITY_INHERITANCE /* Enable priority inheritance (dangerous) */ sem->flags &= ~PRIOINHERIT_FLAGS_DISABLE; return OK; -#endif case SEM_PRIO_PROTECT: /* Not yet supported */ @@ -128,3 +126,5 @@ int sem_setprotocol(FAR sem_t *sem, int protocol) set_errno(errcode); return ERROR; } + +endif /* CONFIG_PRIORITY_INHERITANCE */ diff --git a/syscall/syscall.csv b/syscall/syscall.csv index 99071ea27d..8ecf52854f 100644 --- a/syscall/syscall.csv +++ b/syscall/syscall.csv @@ -118,7 +118,7 @@ "sem_destroy","semaphore.h","","int","FAR sem_t*" "sem_open","semaphore.h","defined(CONFIG_FS_NAMED_SEMAPHORES)","FAR sem_t*","FAR const char*","int","..." "sem_post","semaphore.h","","int","FAR sem_t*" -"sem_setprotocol","nuttx/semaphore.h","","int","FAR sem_t*","int" +"sem_setprotocol","nuttx/semaphore.h","defined(CONFIG_PRIORITY_INHERITANCE)","int","FAR sem_t*","int" "sem_timedwait","semaphore.h","","int","FAR sem_t*","FAR const struct timespec *" "sem_trywait","semaphore.h","","int","FAR sem_t*" "sem_unlink","semaphore.h","defined(CONFIG_FS_NAMED_SEMAPHORES)","int","FAR const char*" -- GitLab From b78ee72a0745f832c23f6c993c9a087b352b3d46 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 20:20:25 -0600 Subject: [PATCH 328/734] defconfgs: More fallout from name change of apps/examples/buttons to archbuttons. --- configs/hymini-stm32v/buttons/defconfig | 2 +- configs/stm3210e-eval/buttons/defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/hymini-stm32v/buttons/defconfig b/configs/hymini-stm32v/buttons/defconfig index 39464dac3d..c314821a14 100644 --- a/configs/hymini-stm32v/buttons/defconfig +++ b/configs/hymini-stm32v/buttons/defconfig @@ -578,7 +578,7 @@ CONFIG_PREALLOC_TIMERS=4 # # CONFIG_INIT_NONE is not set CONFIG_INIT_ENTRYPOINT=y -CONFIG_USER_ENTRYPOINT="buttons_main" +CONFIG_USER_ENTRYPOINT="archbuttons_main" CONFIG_RR_INTERVAL=200 # CONFIG_SCHED_SPORADIC is not set CONFIG_TASK_NAME_SIZE=0 diff --git a/configs/stm3210e-eval/buttons/defconfig b/configs/stm3210e-eval/buttons/defconfig index 5cbbaebc25..202b99f6c8 100644 --- a/configs/stm3210e-eval/buttons/defconfig +++ b/configs/stm3210e-eval/buttons/defconfig @@ -596,7 +596,7 @@ CONFIG_PREALLOC_TIMERS=4 # CONFIG_INIT_NONE is not set CONFIG_INIT_ENTRYPOINT=y # CONFIG_INIT_FILEPATH is not set -CONFIG_USER_ENTRYPOINT="buttons_main" +CONFIG_USER_ENTRYPOINT="archbuttons_main" CONFIG_RR_INTERVAL=200 # CONFIG_SCHED_SPORADIC is not set CONFIG_TASK_NAME_SIZE=0 -- GitLab From 1d0d2fb8e1e06ad32b3ad0e35224edd450006694 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 21:08:17 -0600 Subject: [PATCH 329/734] Fix typo introduced with big set of sem_setprotocol() changes. --- arch/arm/src/lpc17xx/lpc17_usbhost.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/lpc17xx/lpc17_usbhost.c b/arch/arm/src/lpc17xx/lpc17_usbhost.c index 59268f94a5..e81f9f676e 100644 --- a/arch/arm/src/lpc17xx/lpc17_usbhost.c +++ b/arch/arm/src/lpc17xx/lpc17_usbhost.c @@ -2268,7 +2268,7 @@ static int lpc17_epalloc(struct usbhost_driver_s *drvr, */ sem_init(&ed->wdhsem, 0, 0); - sem_setprotocol(&priv->wdhsem, SEM_PRIO_NONE); + sem_setprotocol(&ed->wdhsem, SEM_PRIO_NONE); /* Link the common tail TD to the ED's TD list */ @@ -3308,7 +3308,9 @@ errout_with_sem: static int lpc17_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) { +#ifdef CONFIG_USBHOST_ASYNCH struct lpc17_usbhost_s *priv = (struct lpc17_usbhost_s *)drvr; +#endif struct lpc17_ed_s *ed = (struct lpc17_ed_s *)ep; struct lpc17_gtd_s *td; struct lpc17_gtd_s *next; @@ -3316,7 +3318,7 @@ static int lpc17_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) uint32_t ctrl; irqstate_t flags; - DEBUGASSERT(priv != NULL && ed != NULL); + DEBUGASSERT(drvr != NULL && ed != NULL); /* These first steps must be atomic as possible */ -- GitLab From 4b0372e542e0288171d73623b4613cf4a42734fc Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Nov 2016 21:27:52 -0600 Subject: [PATCH 330/734] Missing # on endif --- sched/semaphore/sem_setprotocol.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sched/semaphore/sem_setprotocol.c b/sched/semaphore/sem_setprotocol.c index 89764f6ad7..1350206941 100644 --- a/sched/semaphore/sem_setprotocol.c +++ b/sched/semaphore/sem_setprotocol.c @@ -127,4 +127,4 @@ int sem_setprotocol(FAR sem_t *sem, int protocol) return ERROR; } -endif /* CONFIG_PRIORITY_INHERITANCE */ +#endif /* CONFIG_PRIORITY_INHERITANCE */ -- GitLab From 8bd8ab1a45238c46a6b7d69a1f4d12d2cc9ce80a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 4 Nov 2016 06:59:28 -0600 Subject: [PATCH 331/734] configs/nucleo_f303re: Various fixes to get the adc configuration building again after PR. Refresh all configurations. --- arch/arm/src/stm32/stm32_adc.c | 2 +- configs/nucleo-f303re/adc/defconfig | 22 ++++++++++++++-- configs/nucleo-f303re/can/defconfig | 20 +++++++++++++- configs/nucleo-f303re/hello/defconfig | 2 ++ configs/nucleo-f303re/nxlines/defconfig | 25 +++++++++++++++--- configs/nucleo-f303re/pwm/defconfig | 22 +++++++++++++++- configs/nucleo-f303re/src/stm32_adc.c | 26 ++++++++++--------- .../nucleo-f303re/src/stm32_appinitialize.c | 17 ++++++++++-- configs/nucleo-f303re/uavcan/defconfig | 20 +++++++++++++- 9 files changed, 132 insertions(+), 24 deletions(-) diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c index 83939499c8..5ede920b24 100644 --- a/arch/arm/src/stm32/stm32_adc.c +++ b/arch/arm/src/stm32/stm32_adc.c @@ -226,7 +226,7 @@ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \ (ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT)) #elif defined(CONFIG_STM32_STM32F30XX) -# ifdef ADC_HAVE_DMA || (ADC_MAX_SAMPLES == 1) +# if defined(ADC_HAVE_DMA) || (ADC_MAX_SAMPLES == 1) # define ADC_SMPR_DEFAULT ADC_SMPR_61p5 # else /* Slow down sampling frequency */ # define ADC_SMPR_DEFAULT ADC_SMPR_601p5 diff --git a/configs/nucleo-f303re/adc/defconfig b/configs/nucleo-f303re/adc/defconfig index 630f5b8918..4b67445407 100644 --- a/configs/nucleo-f303re/adc/defconfig +++ b/configs/nucleo-f303re/adc/defconfig @@ -63,8 +63,10 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -349,6 +351,12 @@ CONFIG_STM32_HAVE_ADC1_DMA=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y # CONFIG_STM32_HAVE_CAN2 is not set CONFIG_STM32_HAVE_DAC1=y @@ -432,7 +440,7 @@ CONFIG_STM32_CCMEXCLUDE=y # # ADC Configuration # -CONFIG_STM32_ADC1_DMA=y +# CONFIG_STM32_ADC1_DMA is not set # CONFIG_STM32_HAVE_RTC_COUNTER is not set # CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set @@ -667,6 +675,8 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -674,6 +684,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set CONFIG_ANALOG=y @@ -722,6 +733,7 @@ CONFIG_ADC_FIFOSIZE=8 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -820,6 +832,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -870,7 +884,9 @@ CONFIG_EXAMPLES_ADC_DEVPATH="/dev/adc0" CONFIG_EXAMPLES_ADC_NSAMPLES=0 CONFIG_EXAMPLES_ADC_GROUPSIZE=4 CONFIG_EXAMPLES_ADC_SWTRIG=y +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -889,10 +905,10 @@ CONFIG_EXAMPLES_ADC_SWTRIG=y # CONFIG_EXAMPLES_NRF24L01TERM is not set # CONFIG_EXAMPLES_NSH is not set # CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set @@ -940,6 +956,7 @@ CONFIG_EXAMPLES_ADC_SWTRIG=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -983,6 +1000,7 @@ CONFIG_EXAMPLES_ADC_SWTRIG=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/nucleo-f303re/can/defconfig b/configs/nucleo-f303re/can/defconfig index 47529ba808..3450575cbf 100644 --- a/configs/nucleo-f303re/can/defconfig +++ b/configs/nucleo-f303re/can/defconfig @@ -63,8 +63,10 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -354,6 +356,12 @@ CONFIG_STM32_HAVE_ADC4=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y # CONFIG_STM32_HAVE_CAN2 is not set CONFIG_STM32_HAVE_DAC1=y @@ -676,6 +684,8 @@ CONFIG_CAN_NPENDINGRTR=4 CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -683,6 +693,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -724,6 +735,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -822,6 +834,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -868,12 +882,14 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set CONFIG_EXAMPLES_CAN=y CONFIG_EXAMPLES_CAN_DEVPATH="/dev/can0" # CONFIG_EXAMPLES_CAN_READ is not set # CONFIG_EXAMPLES_CAN_WRITE is not set CONFIG_EXAMPLES_CAN_READWRITE=y +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -892,10 +908,10 @@ CONFIG_EXAMPLES_CAN_READWRITE=y # CONFIG_EXAMPLES_NRF24L01TERM is not set # CONFIG_EXAMPLES_NSH is not set # CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set @@ -943,6 +959,7 @@ CONFIG_EXAMPLES_CAN_READWRITE=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -986,6 +1003,7 @@ CONFIG_EXAMPLES_CAN_READWRITE=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/nucleo-f303re/hello/defconfig b/configs/nucleo-f303re/hello/defconfig index b35c6c70d2..9c434786e3 100644 --- a/configs/nucleo-f303re/hello/defconfig +++ b/configs/nucleo-f303re/hello/defconfig @@ -683,6 +683,8 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set diff --git a/configs/nucleo-f303re/nxlines/defconfig b/configs/nucleo-f303re/nxlines/defconfig index c77961855f..6eb9debcdb 100644 --- a/configs/nucleo-f303re/nxlines/defconfig +++ b/configs/nucleo-f303re/nxlines/defconfig @@ -63,8 +63,10 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -351,6 +353,12 @@ CONFIG_STM32_HAVE_ADC4=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y # CONFIG_STM32_HAVE_CAN2 is not set CONFIG_STM32_HAVE_DAC1=y @@ -675,14 +683,14 @@ CONFIG_CAN_NPENDINGRTR=4 CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y CONFIG_SPI_CMDDATA=y # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -693,6 +701,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -728,6 +737,7 @@ CONFIG_LCD_MAXPOWER=1 # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set # CONFIG_LCD_UG9664HSWAG01 is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set CONFIG_LCD_SSD1351=y @@ -789,6 +799,7 @@ CONFIG_LCD_LANDSCAPE=y # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -977,6 +988,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1023,8 +1036,10 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1044,10 +1059,10 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_NRF24L01TERM is not set # CONFIG_EXAMPLES_NSH is not set # CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set CONFIG_EXAMPLES_NXLINES=y CONFIG_EXAMPLES_NXLINES_VPLANE=0 CONFIG_EXAMPLES_NXLINES_DEVNO=0 @@ -1102,6 +1117,7 @@ CONFIG_EXAMPLES_NXLINES_EXTERNINIT=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1145,6 +1161,7 @@ CONFIG_EXAMPLES_NXLINES_EXTERNINIT=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/nucleo-f303re/pwm/defconfig b/configs/nucleo-f303re/pwm/defconfig index c0b27a94ee..0e54eba6eb 100644 --- a/configs/nucleo-f303re/pwm/defconfig +++ b/configs/nucleo-f303re/pwm/defconfig @@ -63,8 +63,10 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -349,6 +351,12 @@ CONFIG_STM32_HAVE_ADC4=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y # CONFIG_STM32_HAVE_CAN2 is not set CONFIG_STM32_HAVE_DAC1=y @@ -674,6 +682,8 @@ CONFIG_PWM_NCHANNELS=2 CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -681,6 +691,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -722,6 +733,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -825,6 +837,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -875,7 +889,9 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -894,10 +910,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_NRF24L01TERM is not set # CONFIG_EXAMPLES_NSH is not set # CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set @@ -954,6 +970,7 @@ CONFIG_EXAMPLES_PWM_CHANNEL2=2 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1024,6 +1041,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1089,6 +1107,8 @@ CONFIG_SYSTEM_CLE_DEBUGLEVEL=0 CONFIG_READLINE_HAVE_EXTMATCH=y # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/nucleo-f303re/src/stm32_adc.c b/configs/nucleo-f303re/src/stm32_adc.c index 2c2e0bed28..10183458ec 100644 --- a/configs/nucleo-f303re/src/stm32_adc.c +++ b/configs/nucleo-f303re/src/stm32_adc.c @@ -58,13 +58,23 @@ * Pre-processor Definitions ****************************************************************************/ +/* Configuration ************************************************************/ + +#if defined(ADC1_HAVE_DMA) && defined(CONFIG_STM32_ADC1) +# warning "ADC1 with DMA support is not fully implemented" +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(ADC2_HAVE_DMA) && defined(CONFIG_STM32_ADC2) +# warning "ADC2 with DMA support is not fully implemented" +# undef CONFIG_STM32_ADC2 +#endif + #if (defined(CONFIG_STM32_ADC1) && defined(CONFIG_STM32_ADC2)) || \ (defined(CONFIG_STM32_ADC3) && defined(CONFIG_STM32_ADC4)) # error "will not work with this combination of ADCs" #endif -/* Configuration ************************************************************/ - /* 1 or 2 ADC devices (DEV1, DEV2) */ #if defined(CONFIG_STM32_ADC1) @@ -106,16 +116,8 @@ /* The number of ADC channels in the conversion list */ /* TODO DMA */ -#if defined(ADC1_HAVE_DMA) -# error "ADC1 with DMA support is not fully implemented" -#else -# define ADC1_NCHANNELS 4 -#endif -#if defined(ADC2_HAVE_DMA) -# error "ADC2 with DMA support is not fully implemented" -#else -# define ADC2_NCHANNELS 3 -#endif +#define ADC1_NCHANNELS 4 +#define ADC2_NCHANNELS 3 #define ADC3_NCHANNELS 3 #define ADC4_NCHANNELS 1 diff --git a/configs/nucleo-f303re/src/stm32_appinitialize.c b/configs/nucleo-f303re/src/stm32_appinitialize.c index 3ce7e293bd..7157606edb 100644 --- a/configs/nucleo-f303re/src/stm32_appinitialize.c +++ b/configs/nucleo-f303re/src/stm32_appinitialize.c @@ -53,6 +53,17 @@ * Pre-processor Definitions ****************************************************************************/ +#undef HAVE_LEDS +#undef HAVE_DAC + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +#if defined(CONFIG_DAC) +# define HAVE_DAC 1 +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -84,9 +95,11 @@ int board_app_initialize(uintptr_t arg) { +#if defined(HAVE_LEDS) || defined(HAVE_DAC) int ret; +#endif -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +#ifdef HAVE_LEDS /* Register the LED driver */ ret = userled_lower_initialize(LED_DRIVER_PATH); @@ -101,7 +114,7 @@ int board_app_initialize(uintptr_t arg) * faut le faire ici */ -#if defined(CONFIG_DAC) +#ifdef HAVE_DAC ret = board_dac_setup(); if (ret < 0) { diff --git a/configs/nucleo-f303re/uavcan/defconfig b/configs/nucleo-f303re/uavcan/defconfig index 836893eafc..944984f2d5 100644 --- a/configs/nucleo-f303re/uavcan/defconfig +++ b/configs/nucleo-f303re/uavcan/defconfig @@ -63,8 +63,10 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -349,6 +351,12 @@ CONFIG_STM32_HAVE_ADC4=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y # CONFIG_STM32_HAVE_CAN2 is not set CONFIG_STM32_HAVE_DAC1=y @@ -653,6 +661,8 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -660,6 +670,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -701,6 +712,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -799,6 +811,8 @@ CONFIG_LIBM=y # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -881,7 +895,9 @@ CONFIG_LIBUAVCAN_INIT_RETRIES=0 # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -902,10 +918,10 @@ CONFIG_LIBUAVCAN_INIT_RETRIES=0 # CONFIG_EXAMPLES_NRF24L01TERM is not set # CONFIG_EXAMPLES_NSH is not set # CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set @@ -956,6 +972,7 @@ CONFIG_EXAMPLES_UAVCAN_NODE_NAME="org.nuttx.apps.examples.uavcan" # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1000,6 +1017,7 @@ CONFIG_EXAMPLES_UAVCAN_NODE_NAME="org.nuttx.apps.examples.uavcan" # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set -- GitLab From e6435c28d0f866f8f348e4e4015ed5e2e802323b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 4 Nov 2016 09:58:27 -0600 Subject: [PATCH 332/734] Fix some name errors in port: RISC-V -> LM32 --- arch/misoc/include/lm32/syscall.h | 4 ++-- arch/misoc/include/syscall.h | 2 +- arch/misoc/src/lm32/lm32.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/misoc/include/lm32/syscall.h b/arch/misoc/include/lm32/syscall.h index 9e4b0d9ee0..d0816c7a21 100644 --- a/arch/misoc/include/lm32/syscall.h +++ b/arch/misoc/include/lm32/syscall.h @@ -58,8 +58,8 @@ #define SYS_syscall 0x00 /* Configuration ********************************************************************/ -/* SYS call 1 and 2 are defined for internal use by the RISC-V port (see - * arch/riscv/include/mips32/syscall.h). In addition, SYS call 3 is the return from +/* SYS call 1 and 2 are defined for internal use by the LM32 port (see + * arch/miscoc/include/lm32/syscall.h). In addition, SYS call 3 is the return from * a SYS call in kernel mode. The first four syscall values must, therefore, be * reserved (0 is not used). */ diff --git a/arch/misoc/include/syscall.h b/arch/misoc/include/syscall.h index 3a8f2e9df0..71b9e85a6c 100644 --- a/arch/misoc/include/syscall.h +++ b/arch/misoc/include/syscall.h @@ -44,7 +44,7 @@ * Included Files ****************************************************************************/ -/* Include RISC-V architecture-specific syscall macros */ +/* Include LM32 architecture-specific syscall macros */ #ifdef CONFIG_ARCH_MISOC # include diff --git a/arch/misoc/src/lm32/lm32.h b/arch/misoc/src/lm32/lm32.h index 8098da7492..280c2ff17f 100644 --- a/arch/misoc/src/lm32/lm32.h +++ b/arch/misoc/src/lm32/lm32.h @@ -61,7 +61,7 @@ #define INTSTACK_COLOR 0xdeadbeef #define HEAP_COLOR 'h' -/* In the RISC_V model, the state is copied from the stack to the TCB, but +/* In the LM32 model, the state is copied from the stack to the TCB, but * only a referenced is passed to get the state from the TCB. */ -- GitLab From 8f3c59b0d60dc37c6edf6c26ed929c0ddff37fcc Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 4 Nov 2016 10:21:55 -0600 Subject: [PATCH 333/734] LM32: Rename up_doirq() to lm32_doirq() --- arch/misoc/src/lm32/lm32_doirq.c | 2 +- arch/misoc/src/lm32/lm32_vectors.S | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/misoc/src/lm32/lm32_doirq.c b/arch/misoc/src/lm32/lm32_doirq.c index 50b2e745fc..50a001ea69 100644 --- a/arch/misoc/src/lm32/lm32_doirq.c +++ b/arch/misoc/src/lm32/lm32_doirq.c @@ -71,7 +71,7 @@ * Public Functions ****************************************************************************/ -uint32_t *up_doirq(int irq, uint32_t *regs) +uint32_t *lm32_doirq(int irq, uint32_t *regs) { board_autoled_on(LED_INIRQ); #ifdef CONFIG_SUPPRESS_INTERRUPTS diff --git a/arch/misoc/src/lm32/lm32_vectors.S b/arch/misoc/src/lm32/lm32_vectors.S index a5ca7a550d..70187767dd 100644 --- a/arch/misoc/src/lm32/lm32_vectors.S +++ b/arch/misoc/src/lm32/lm32_vectors.S @@ -112,7 +112,7 @@ _interrupt_handler: sw (sp+0), ra calli .save_all rcsr r1, IP - calli up_doirq + calli lm32_doirq bi .restore_all_and_eret nop nop -- GitLab From 145ee2e6f157245c3311213d8f6eaa1124a3cde5 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 4 Nov 2016 10:39:57 -0600 Subject: [PATCH 334/734] LM32: Add prototype for lm32_decodeirq(). --- arch/misoc/src/lm32/Make.defs | 11 ++-- arch/misoc/src/lm32/lm32_decodeirq.c | 92 ++++++++++++++++++++++++++++ arch/misoc/src/lm32/lm32_vectors.S | 2 +- 3 files changed, 99 insertions(+), 6 deletions(-) create mode 100644 arch/misoc/src/lm32/lm32_decodeirq.c diff --git a/arch/misoc/src/lm32/Make.defs b/arch/misoc/src/lm32/Make.defs index 8338154388..cc4b72da66 100644 --- a/arch/misoc/src/lm32/Make.defs +++ b/arch/misoc/src/lm32/Make.defs @@ -42,8 +42,9 @@ CMN_CSRCS = misoc_uart.c CHIP_ASRCS = lm32_syscall.S CHIP_CSRCS = lm32_allocateheap.c lm32_assert.c lm32_blocktask.c -CHIP_CSRCS += lm32_copystate.c lm32_createstack.c lm32_doirq.c lm32_dumpstate.c -CHIP_CSRCS += lm32_dumpstate.c lm32_exit.c lm32_idle.c lm32_initialize.c -CHIP_CSRCS += lm32_initialstate.c lm32_interruptcontext.c lm32_irq.c -CHIP_CSRCS += lm32_releasepending.c lm32_releasestack.c -CHIP_CSRCS += lm32_stackframe.c lm32_swint.c lm32_unblocktask.c +CHIP_CSRCS += lm32_copystate.c lm32_createstack.c lm32_decodeirq.c +CHIP_CSRCS += lm32_doirq.c lm32_dumpstate.c lm32_dumpstate.c lm32_exit.c +CHIP_CSRCS += lm32_idle.c lm32_initialize.c lm32_initialstate.c +CHIP_CSRCS += lm32_interruptcontext.c lm32_irq.c lm32_releasepending.c +CHIP_CSRCS += lm32_releasestack.c lm32_stackframe.c lm32_swint.c +CHIP_CSRCS += lm32_unblocktask.c diff --git a/arch/misoc/src/lm32/lm32_decodeirq.c b/arch/misoc/src/lm32/lm32_decodeirq.c new file mode 100644 index 0000000000..a532331ca3 --- /dev/null +++ b/arch/misoc/src/lm32/lm32_decodeirq.c @@ -0,0 +1,92 @@ +/******************************************************************************** + * arch/misoc/src/lm32/lm32_decodeirq.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************/ + +/******************************************************************************** + * Included Files + ********************************************************************************/ + +#include + +#include "chip.h" +#include "lm32.h" + +/******************************************************************************** + * Public Functions + ********************************************************************************/ + +/**************************************************************************** + * Name: lm32_decodeirq + * + * Description: + * This function is called from the IRQ vector handler in lm32_vectors.S. + * At this point, the interrupt has been taken and the registers have + * been saved on the stack. This function simply needs to determine the + * the irq number of the interrupt and then to call lm32_doirq to dispatch + * the interrupt. + * + * Input parameters: + * regs - A pointer to the register save area on the stack. + * + ****************************************************************************/ + +uint32_t *lm32_decodeirq(uint32_t *regs) +{ + uint32_t im; + int irq; + + /* Read the interrupt acknowledge register and get the interrupt ID */ + + im = getreg32(GIC_ICCIAR); + irq = (im & GIC_ICCIAR_INTID_MASK) >> GIC_ICCIAR_INTID_SHIFT; + + irqinfo("irq=%d\n", irq); + + /* Ignore spurions IRQs. ICCIAR will report 1023 if there is no pending + * interrupt. + */ + + DEBUGASSERT(irq < NR_IRQS || irq == 1023); + if (irq < NR_IRQS) + { + /* Dispatch the interrupt */ + + regs = lm32_doirq(irq, regs); + } + + /* Write to the end-of-interrupt register */ + + putreg32(im, GIC_ICCEOIR); + return regs; +} diff --git a/arch/misoc/src/lm32/lm32_vectors.S b/arch/misoc/src/lm32/lm32_vectors.S index 70187767dd..f672fa7fda 100644 --- a/arch/misoc/src/lm32/lm32_vectors.S +++ b/arch/misoc/src/lm32/lm32_vectors.S @@ -112,7 +112,7 @@ _interrupt_handler: sw (sp+0), ra calli .save_all rcsr r1, IP - calli lm32_doirq + calli lm32_decodeirq bi .restore_all_and_eret nop nop -- GitLab From ddd871618937104d069fac7687036e3a3171c3c7 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 4 Nov 2016 10:42:05 -0600 Subject: [PATCH 335/734] LM32: Ooops.. last version still in editor --- arch/misoc/src/lm32/lm32_decodeirq.c | 45 +++++++++++++++++++--------- arch/misoc/src/lm32/lm32_doirq.c | 16 ---------- 2 files changed, 31 insertions(+), 30 deletions(-) diff --git a/arch/misoc/src/lm32/lm32_decodeirq.c b/arch/misoc/src/lm32/lm32_decodeirq.c index a532331ca3..bdf0abe240 100644 --- a/arch/misoc/src/lm32/lm32_decodeirq.c +++ b/arch/misoc/src/lm32/lm32_decodeirq.c @@ -63,30 +63,47 @@ uint32_t *lm32_decodeirq(uint32_t *regs) { - uint32_t im; + uint32_t intstat; int irq; - /* Read the interrupt acknowledge register and get the interrupt ID */ + /* Read the pending interrupts */ + /* REVISIT: How do I get the interupt status */ +#warning Missing logic + intstat = 0; - im = getreg32(GIC_ICCIAR); - irq = (im & GIC_ICCIAR_INTID_MASK) >> GIC_ICCIAR_INTID_SHIFT; + /* REVIST: Do I need to mask the interrupt status with the IM? */ - irqinfo("irq=%d\n", irq); + irqinfo("intstat=%08lx\n", (unsigned long)intstat); - /* Ignore spurions IRQs. ICCIAR will report 1023 if there is no pending - * interrupt. - */ + /* Decode and dispatch interrupts */ - DEBUGASSERT(irq < NR_IRQS || irq == 1023); - if (irq < NR_IRQS) + for (irq = 0; irq < NR_IRQS & instat != 0; i++) { - /* Dispatch the interrupt */ + uint32_t bit = (1 << irq); + + /* Is this interrupt pending? */ + + if ((instat & bit) != 0) + { + /* Yes.. Dispatch the interrupt */ + /* REVIST: Do I need to acknowledge the interrupt first? */ - regs = lm32_doirq(irq, regs); + irqinfo("irq=%d\n", irq); + regs = lm32_doirq(irq, regs); + + /* Clear the bit in the interrupt status copy so that maybe we can + * break out of the loop early. + */ + + instat &= ~bit; + } } - /* Write to the end-of-interrupt register */ + /* Return the final task register save area. This will typically be the + * same as the value of regs on input. In the event of a context switch, + * however, it will differ. It will refere to the register save are in the + * TCB of the new thread. + */ - putreg32(im, GIC_ICCEOIR); return regs; } diff --git a/arch/misoc/src/lm32/lm32_doirq.c b/arch/misoc/src/lm32/lm32_doirq.c index 50a001ea69..6d44eeb95c 100644 --- a/arch/misoc/src/lm32/lm32_doirq.c +++ b/arch/misoc/src/lm32/lm32_doirq.c @@ -51,22 +51,6 @@ #include "group/group.h" #include "lm32.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ -- GitLab From b2126738cd2091cf5e079b1f08a8f7ec39720b55 Mon Sep 17 00:00:00 2001 From: Ramtin Amin Date: Fri, 4 Nov 2016 10:54:10 -0600 Subject: [PATCH 336/734] LM32: Fix implementation of up_irq_save() and up_irq_restore() --- arch/misoc/include/lm32/irq.h | 7 +++- arch/misoc/src/lm32/lm32_doirq.c | 4 +- arch/misoc/src/lm32/lm32_initialstate.c | 4 ++ arch/misoc/src/lm32/lm32_irq.c | 32 +++++++++++---- arch/misoc/src/lm32/lm32_swint.c | 1 + arch/misoc/src/lm32/lm32_vectors.S | 13 ++++-- configs/misoc/hello/defconfig | 53 +++++++++++++++++++++---- 7 files changed, 90 insertions(+), 24 deletions(-) diff --git a/arch/misoc/include/lm32/irq.h b/arch/misoc/include/lm32/irq.h index e73d3815d5..782bb06ae9 100644 --- a/arch/misoc/include/lm32/irq.h +++ b/arch/misoc/include/lm32/irq.h @@ -82,10 +82,11 @@ #define REG_X29_NDX 29 /* General-purpose/return address */ #define REG_X30_NDX 30 /* Exception address */ #define REG_X31_NDX 31 /* Breakpoint address */ +#define REG_X32_NDX 32 /* Reg IE */ /* Interrupt Context register */ -#define XCPTCONTEXT_REGS 32 +#define XCPTCONTEXT_REGS 33 #define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS) #ifdef __ASSEMBLY__ @@ -121,6 +122,7 @@ # define REG_X29 (4*REG_X29_NDX) # define REG_X30 (4*REG_X30_NDX) # define REG_X31 (4*REG_X31_NDX) +# define REG_INT_CTX (4*REG_X32_NDX) #else # define REG_X0 REG_X0_NDX # define REG_X1 REG_X1_NDX @@ -154,6 +156,7 @@ # define REG_X29 REG_X29_NDX # define REG_X30 REG_X30_NDX # define REG_X31 REG_X31_NDX +# define REG_INT_CTX REG_X32_NDX #endif /* Register aliases */ @@ -176,6 +179,8 @@ #define REG_A6 REG_X7 #define REG_A7 REG_X8 +#define REG_IE REG_INT_CTX + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/arch/misoc/src/lm32/lm32_doirq.c b/arch/misoc/src/lm32/lm32_doirq.c index 6d44eeb95c..e318a65adf 100644 --- a/arch/misoc/src/lm32/lm32_doirq.c +++ b/arch/misoc/src/lm32/lm32_doirq.c @@ -58,9 +58,7 @@ uint32_t *lm32_doirq(int irq, uint32_t *regs) { board_autoled_on(LED_INIRQ); -#ifdef CONFIG_SUPPRESS_INTERRUPTS - PANIC(); -#else + /* Current regs non-zero indicates that we are processing an interrupt; * g_current_regs is also used to manage interrupt level context switches. * diff --git a/arch/misoc/src/lm32/lm32_initialstate.c b/arch/misoc/src/lm32/lm32_initialstate.c index e42107e145..6064e186c8 100644 --- a/arch/misoc/src/lm32/lm32_initialstate.c +++ b/arch/misoc/src/lm32/lm32_initialstate.c @@ -99,6 +99,10 @@ void up_initial_state(struct tcb_s *tcb) xcp->regs[REG_EPC] = (uint32_t)tcb->start; + /* Initial state of IE: Interrupts enabled */ + + xcp->regs[REG_INT_CTX] = 1; + /* If this task is running PIC, then set the PIC base register to the * address of the allocated D-Space region. */ diff --git a/arch/misoc/src/lm32/lm32_irq.c b/arch/misoc/src/lm32/lm32_irq.c index 726d60c297..d64623dfa3 100644 --- a/arch/misoc/src/lm32/lm32_irq.c +++ b/arch/misoc/src/lm32/lm32_irq.c @@ -69,7 +69,7 @@ void lm32_irq_initialize(void) g_current_regs = NULL; - /* Enable interrupt */ + /* Enable interrupts */ irq_setie(1); } @@ -77,15 +77,22 @@ void lm32_irq_initialize(void) irqstate_t up_irq_save(void) { irqstate_t flags; - irq_setie(0); -#warning Return value MUST be the previous IE value. Returning 1 will not work. - return 1; + /* Get the previous value of IE */ + + flags = irq_getie(); + + /* Disable interrupts and return the previous interrupt state */ + + irq_setie(0); + return flags; } void up_irq_restore(irqstate_t flags) { - irq_setie(1); + /* Restore the interrupt state returned by up_save_irq() */ + + irq_setie(flags); } /**************************************************************************** @@ -99,8 +106,13 @@ void up_irq_restore(irqstate_t flags) void up_disable_irq(int irq) { irqstate_t flags; - flags = irq_getmask(); - flags &= ~(1 <= 0 && irq < NR_IRQS); + + /* Disable interrupts by clearing the bit that corresponds to the irq */ + + flags = irq_getmask(); + flags &= ~(1 << irq); irq_setmask(flags); } @@ -115,7 +127,11 @@ void up_disable_irq(int irq) void up_enable_irq(int irq) { irqstate_t flags; - flags = irq_getmask(); + DEBUGASSERT(irq >= 0 && irq < NR_IRQS); + + /* Enable interrupts by setting the bit that corresponds to the irq */ + + flags = irq_getmask(); flags |= (1 << irq); irq_setmask(flags); } diff --git a/arch/misoc/src/lm32/lm32_swint.c b/arch/misoc/src/lm32/lm32_swint.c index f8c7b280ee..9e5f932d46 100644 --- a/arch/misoc/src/lm32/lm32_swint.c +++ b/arch/misoc/src/lm32/lm32_swint.c @@ -326,5 +326,6 @@ uint32_t *lm32_swint(int irq, FAR void *context) */ g_current_regs = NULL; + return regs; } diff --git a/arch/misoc/src/lm32/lm32_vectors.S b/arch/misoc/src/lm32/lm32_vectors.S index f672fa7fda..f501059997 100644 --- a/arch/misoc/src/lm32/lm32_vectors.S +++ b/arch/misoc/src/lm32/lm32_vectors.S @@ -151,7 +151,7 @@ _do_reset: bi os_start .save_all: - addi sp, sp, -132 + addi sp, sp, -136 sw (sp+REG_X0), r0 sw (sp+REG_X1), r1 sw (sp+REG_X2), r2 @@ -190,11 +190,14 @@ _do_reset: /* ra needs to be moved from initial stack location */ - lw r1, (sp+ 132) + lw r1, (sp+ 136) sw (sp+REG_RA), r1 - /* the 2nd argument is the regs pointer */ + /* get IE/REG_INT_CTX */ + rcsr r1, IE + sw (sp+REG_INT_CTX), r1 + /* the 2nd argument is the regs pointer */ addi r2, sp, 0 ret @@ -231,8 +234,10 @@ _do_reset: lw r29, (r1+REG_RA) lw r30, (r1+REG_EA) lw r31, (r1+REG_BA) + lw r1, (r1+REG_INT_CTX) + wcsr IE, r1 lw r1, (r1+REG_X1) - addi sp, sp, 132 + addi sp, sp, 136 eret /* This global variable is unsigned long g_idle_topstack and is diff --git a/configs/misoc/hello/defconfig b/configs/misoc/hello/defconfig index 99c0c9ef2c..f7b4a0082d 100644 --- a/configs/misoc/hello/defconfig +++ b/configs/misoc/hello/defconfig @@ -16,7 +16,7 @@ CONFIG_HOST_LINUX=y # # Build Configuration # -# CONFIG_APPS_DIR="../apps" +CONFIG_APPS_DIR="../apps" CONFIG_BUILD_FLAT=y # CONFIG_BUILD_2PASS is not set @@ -74,8 +74,9 @@ CONFIG_DEBUG_FEATURES=y # CONFIG_ARCH_HAVE_STACKCHECK is not set # CONFIG_ARCH_HAVE_HEAPCHECK is not set CONFIG_DEBUG_SYMBOLS=y -# CONFIG_ARCH_HAVE_CUSTOMOPT is not set +CONFIG_ARCH_HAVE_CUSTOMOPT=y CONFIG_DEBUG_NOOPT=y +# CONFIG_DEBUG_CUSTOMOPT is not set # CONFIG_DEBUG_FULLOPT is not set # @@ -88,8 +89,10 @@ CONFIG_DEBUG_NOOPT=y CONFIG_ARCH_MISOC=y # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="misoc" @@ -97,6 +100,15 @@ CONFIG_ARCH_CHIP="lm32" CONFIG_ARCH_CHIP_LM32=y # CONFIG_ARCH_CHIP_MOR1K is not set +# +# MISOC Peripheral Support +# +CONFIG_MISOC_HAVE_UART1=y +CONFIG_MISOC_UART1=y +CONFIG_MISOC_UART=y +CONFIG_MISOC_UART_RX_BUF_SIZE=64 +CONFIG_MISOC_UART_TX_BUF_SIZE=64 + # # Architecture Options # @@ -131,7 +143,8 @@ CONFIG_BOARD_LOOPSPERMSEC=800 # # Interrupt options # -# CONFIG_ARCH_HAVE_INTERRUPTSTACK is not set +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 # CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set # @@ -276,6 +289,9 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # @@ -319,13 +335,13 @@ CONFIG_DEV_NULL=y # CONFIG_SENSORS is not set # CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y -CONFIG_DEV_LOWCONSOLE=y +# CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set -# CONFIG_SERIAL_CONSOLE is not set +CONFIG_SERIAL_CONSOLE=y # CONFIG_16550_UART is not set # CONFIG_UART_SERIALDRIVER is not set # CONFIG_UART0_SERIALDRIVER is not set -# CONFIG_UART1_SERIALDRIVER is not set +CONFIG_UART1_SERIALDRIVER=y # CONFIG_UART2_SERIALDRIVER is not set # CONFIG_UART3_SERIALDRIVER is not set # CONFIG_UART4_SERIALDRIVER is not set @@ -345,11 +361,29 @@ CONFIG_DEV_LOWCONSOLE=y # CONFIG_USART7_SERIALDRIVER is not set # CONFIG_USART8_SERIALDRIVER is not set # CONFIG_OTHER_UART_SERIALDRIVER is not set -# CONFIG_MCU_SERIAL is not set +CONFIG_MCU_SERIAL=y +# CONFIG_STANDARD_SERIAL is not set # CONFIG_SERIAL_IFLOWCONTROL is not set # CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_SERIAL_DMA is not set +# CONFIG_SERIAL_TIOCSERGSTRUCT is not set # CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set +CONFIG_UART1_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART1 Configuration +# +CONFIG_UART1_RXBUFSIZE=256 +CONFIG_UART1_TXBUFSIZE=256 +CONFIG_UART1_BAUD=115200 +CONFIG_UART1_BITS=8 +CONFIG_UART1_PARITY=0 +CONFIG_UART1_2STOP=0 +# CONFIG_UART1_IFLOWCONTROL is not set +# CONFIG_UART1_OFLOWCONTROL is not set +# CONFIG_UART1_DMA is not set # CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set @@ -364,7 +398,7 @@ CONFIG_DEV_LOWCONSOLE=y # CONFIG_RAMLOG is not set # CONFIG_SYSLOG_INTBUFFER is not set # CONFIG_SYSLOG_TIMESTAMP is not set -# CONFIG_SYSLOG_SERIAL_CONSOLE is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y # CONFIG_SYSLOG_CHAR is not set CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set @@ -446,6 +480,8 @@ CONFIG_NUNGET_CHARS=0 # CONFIG_LIBC_FLOATINGPOINT is not set # CONFIG_LIBC_LONG_LONG is not set # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -489,6 +525,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set -- GitLab From 50efe4a906f82eda23b9dc9d4ed75e683bcd2bbd Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 4 Nov 2016 11:17:12 -0600 Subject: [PATCH 337/734] LM32: Add a fake IRQ number for a software interrupt. --- arch/misoc/include/irq.h | 6 ++++- arch/misoc/src/lm32/lm32_decodeirq.c | 2 +- arch/misoc/src/lm32/lm32_irq.c | 40 ++++++++++++++++++++++------ 3 files changed, 38 insertions(+), 10 deletions(-) diff --git a/arch/misoc/include/irq.h b/arch/misoc/include/irq.h index 1fbf884fc3..a21987b00a 100644 --- a/arch/misoc/include/irq.h +++ b/arch/misoc/include/irq.h @@ -53,7 +53,11 @@ * Pre-processor Definitions ****************************************************************************/ -#define NR_IRQS 32 +/* 32 True interrupts plus the sofware interrupt */ + +#define MISOC_NINTERRUPTS 32 +#define MISOC_IRQ_SWINT 32 +#define NR_IRQS 33 /**************************************************************************** * Public Function Prototypes diff --git a/arch/misoc/src/lm32/lm32_decodeirq.c b/arch/misoc/src/lm32/lm32_decodeirq.c index bdf0abe240..0df3f73ed9 100644 --- a/arch/misoc/src/lm32/lm32_decodeirq.c +++ b/arch/misoc/src/lm32/lm32_decodeirq.c @@ -77,7 +77,7 @@ uint32_t *lm32_decodeirq(uint32_t *regs) /* Decode and dispatch interrupts */ - for (irq = 0; irq < NR_IRQS & instat != 0; i++) + for (irq = 0; irq < MISOC_NINTERRUPTS & instat != 0; i++) { uint32_t bit = (1 << irq); diff --git a/arch/misoc/src/lm32/lm32_irq.c b/arch/misoc/src/lm32/lm32_irq.c index d64623dfa3..4218d8872b 100644 --- a/arch/misoc/src/lm32/lm32_irq.c +++ b/arch/misoc/src/lm32/lm32_irq.c @@ -74,6 +74,13 @@ void lm32_irq_initialize(void) irq_setie(1); } +/**************************************************************************** + * Name: up_irq_save + * + * Description: + * + ****************************************************************************/ + irqstate_t up_irq_save(void) { irqstate_t flags; @@ -88,6 +95,13 @@ irqstate_t up_irq_save(void) return flags; } +/**************************************************************************** + * Name: up_irq_restore + * + * Description: + * + ****************************************************************************/ + void up_irq_restore(irqstate_t flags) { /* Restore the interrupt state returned by up_save_irq() */ @@ -109,11 +123,16 @@ void up_disable_irq(int irq) DEBUGASSERT(irq >= 0 && irq < NR_IRQS); - /* Disable interrupts by clearing the bit that corresponds to the irq */ + /* Ignore any attempt to disable software interrupts */ + + if (irq < MISOC_NINTERRUPTS) + { + /* Disable interrupts by clearing the bit that corresponds to the irq */ - flags = irq_getmask(); - flags &= ~(1 << irq); - irq_setmask(flags); + flags = irq_getmask(); + flags &= ~(1 << irq); + irq_setmask(flags); + } } /**************************************************************************** @@ -129,9 +148,14 @@ void up_enable_irq(int irq) irqstate_t flags; DEBUGASSERT(irq >= 0 && irq < NR_IRQS); - /* Enable interrupts by setting the bit that corresponds to the irq */ + /* Ignore any attempt to enable software interrupts */ + + if (irq < MISOC_NINTERRUPTS) + { + /* Enable interrupts by setting the bit that corresponds to the irq */ - flags = irq_getmask(); - flags |= (1 << irq); - irq_setmask(flags); + flags = irq_getmask(); + flags |= (1 << irq); + irq_setmask(flags); + } } -- GitLab From 8fe916e13384fd9f7a76fde167cea38470e3bf2e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 4 Nov 2016 11:23:33 -0600 Subject: [PATCH 338/734] Attach the software interrupt handler when interrupts are intialized. --- arch/misoc/src/lm32/lm32_irq.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/misoc/src/lm32/lm32_irq.c b/arch/misoc/src/lm32/lm32_irq.c index 4218d8872b..dab24189e6 100644 --- a/arch/misoc/src/lm32/lm32_irq.c +++ b/arch/misoc/src/lm32/lm32_irq.c @@ -69,6 +69,10 @@ void lm32_irq_initialize(void) g_current_regs = NULL; + /* Attach the software interrupt */ + + (void)irq_attach(MISOC_IRQ_SWINT, lm32_swint); + /* Enable interrupts */ irq_setie(1); -- GitLab From 45caca804a01205cb7cebb1e21dda76419d183a6 Mon Sep 17 00:00:00 2001 From: Ramtin Amin Date: Fri, 4 Nov 2016 14:04:43 -0600 Subject: [PATCH 339/734] LM32: Progress on interrupt and serial driver. --- arch/misoc/Kconfig | 12 +- arch/misoc/src/common/misoc.h | 64 ++ arch/misoc/src/common/misoc_mdelay.c | 70 ++ arch/misoc/src/common/misoc_serial.c | 685 ++++++++++++++++++++ arch/misoc/src/lm32/Make.defs | 2 +- arch/misoc/src/lm32/Toolchain.defs | 4 +- arch/misoc/src/lm32/lm32.h | 21 +- arch/misoc/src/lm32/lm32_config.h | 97 +++ arch/misoc/src/lm32/lm32_decodeirq.c | 10 +- arch/misoc/src/lm32/lm32_doirq.c | 3 + arch/misoc/src/lm32/lm32_initialize.c | 5 +- arch/misoc/src/lm32/lm32_swint.c | 18 +- arch/misoc/src/lm32/lm32_vectors.S | 150 ++--- configs/misoc/include/generated/csr.h | 539 ++++++--------- configs/misoc/include/generated/mem.h | 45 +- configs/misoc/include/generated/regions.ld | 3 +- configs/misoc/include/generated/sdram_phy.h | 180 ++--- 17 files changed, 1278 insertions(+), 630 deletions(-) create mode 100644 arch/misoc/src/common/misoc.h create mode 100644 arch/misoc/src/common/misoc_mdelay.c create mode 100644 arch/misoc/src/common/misoc_serial.c create mode 100644 arch/misoc/src/lm32/lm32_config.h diff --git a/arch/misoc/Kconfig b/arch/misoc/Kconfig index f0acc68046..615b741c52 100644 --- a/arch/misoc/Kconfig +++ b/arch/misoc/Kconfig @@ -11,7 +11,7 @@ choice config ARCH_CHIP_LM32 bool "LM32" - select MISOC_HAVE_UART0 + select MISOC_HAVE_UART1 ---help--- LM32 Chip Selected @@ -32,15 +32,15 @@ menu "MISOC Peripheral Support" # These "hidden" settings determine is a peripheral option is available for the # selection MCU -config MISOC_HAVE_UART0 +config MISOC_HAVE_UART1 bool default n - select UART0_SERIALDRIVER + select UART1_SERIALDRIVER -config MISOC_UART0 - bool "UART0" +config MISOC_UART1 + bool "UART1" default n - select ARCH_HAVE_UART0 + select ARCH_HAVE_UART1 select MISOC_UART endmenu # MISOC Peripheral Support diff --git a/arch/misoc/src/common/misoc.h b/arch/misoc/src/common/misoc.h new file mode 100644 index 0000000000..d487babab2 --- /dev/null +++ b/arch/misoc/src/common/misoc.h @@ -0,0 +1,64 @@ +/**************************************************************************** + * arch/misoc/src/common/serial.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MISOC_SRC_COMMON_MISOC_H +#define __ARCH_MISOC_SRC_COMMON_MISOC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Register serial console and serial ports. This assumes that + * misoc_earlyserialinit was called previously. + * + ****************************************************************************/ + +void misoc_serial_initialize(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MISOC_SRC_COMMON_MISOC_H */ diff --git a/arch/misoc/src/common/misoc_mdelay.c b/arch/misoc/src/common/misoc_mdelay.c new file mode 100644 index 0000000000..2a1ccaa1a1 --- /dev/null +++ b/arch/misoc/src/common/misoc_mdelay.c @@ -0,0 +1,70 @@ +/**************************************************************************** + * arch/misoc/src/common/misoc_mdelay.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_mdelay + * + * Description: + * Delay inline for the requested number of milliseconds. + * *** NOT multi-tasking friendly *** + * + * ASSUMPTIONS: + * The setting CONFIG_BOARD_LOOPSPERMSEC has been calibrated + * + ****************************************************************************/ + +void up_mdelay(unsigned int milliseconds) +{ + volatile int i; + volatile int j; + + for (i = 0; i < milliseconds; i++) + { + for (j = 0; j < CONFIG_BOARD_LOOPSPERMSEC; j++) + { + } + } +} diff --git a/arch/misoc/src/common/misoc_serial.c b/arch/misoc/src/common/misoc_serial.c new file mode 100644 index 0000000000..af05eb1bb1 --- /dev/null +++ b/arch/misoc/src/common/misoc_serial.c @@ -0,0 +1,685 @@ +/**************************************************************************** + * arch/misoc/src/lm32/lm32_blocktask.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include + +#include "chip.h" +#include "hw/flags.h +#include "misoc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_UART_DEVICE +#if defined(CONFIG_MISOC_UART1) || defined(CONFIG_MISOC_UART2) +# define HAVE_UART_DEVICE 1 +#endif + +/* Is there a serial console? There should be no more than one defined. It + * could be on any UARTn, n=1,.. CHIP_NUARTS + */ + +#if defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_MISOC_UART1) +# undef CONFIG_UART2_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_MISOC_UART2) +# undef CONFIG_UART1_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#else +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef HAVE_SERIAL_CONSOLE +#endif + +/* If we are not using the serial driver for the console, then we still must + * provide some minimal implementation of misoc_putc. + */ + +#ifdef USE_SERIALDRIVER + +/* Which UART with be tty0/console and which tty1? The console will always + * be ttyS0. If there is no console then will use the lowest numbered UART. + */ + +#ifdef HAVE_SERIAL_CONSOLE +# if defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1 is console */ +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# undef TTYS1_DEV /* No ttyS1 */ +# define SERIAL_CONSOLE 1 +# else +# error "I'm confused... Do we have a serial console or not?" +# endif +#else +# undef CONSOLE_DEV /* No console */ +# undef CONFIG_UART1_SERIAL_CONSOLE +# if defined(CONFIG_NR5_UART1) +# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ +# undef TTYS1_DEV /* No ttyS1 */ +# define SERIAL_CONSOLE 1 +# else +# undef TTYS0_DEV +# undef TTYS1_DEV +# endif +#endif + +/* Common initialization logic will not not know that the all of the UARTs + * have been disabled. So, as a result, we may still have to provide + * stub implementations of misoc_earlyserialinit(), misoc_serial_initialize(), and + * misoc_putc(). + */ + +#ifdef HAVE_UART_DEVICE + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct misoc_dev_s +{ + uintptr_t uartbase; + uintptr_t rxtx_addr; + uintptr_t txfull_addr; + uintptr_t rxempty_addr; + uintptr_t ev_status_addr; + uintptr_t ev_pending_addr; + uintptr_t ev_enable_addr; + uint8_t irq; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Low-level helpers */ + +static inline uint32_t misoc_serialin(struct misoc_dev_s *priv, int offset); +static inline void misoc_serialout(struct misoc_dev_s *priv, int offset, + uint32_t value); +static void misoc_restoreuartint(struct uart_dev_s *dev, uint8_t im); +static void misoc_disableuartint(struct uart_dev_s *dev, uint8_t *im); + +/* Serial driver methods */ + +static int misoc_setup(struct uart_dev_s *dev); +static void misoc_shutdown(struct uart_dev_s *dev); +static int misoc_attach(struct uart_dev_s *dev); +static void misoc_detach(struct uart_dev_s *dev); +static int misoc_uart_interrupt(int irq, void *context); +static int misoc_ioctl(struct file *filep, int cmd, unsigned long arg); +static int misoc_receive(struct uart_dev_s *dev, uint32_t *status); +static void misoc_rxint(struct uart_dev_s *dev, bool enable); +static bool misoc_rxavailable(struct uart_dev_s *dev); +static void misoc_send(struct uart_dev_s *dev, int ch); +static void misoc_txint(struct uart_dev_s *dev, bool enable); +static bool misoc_txready(struct uart_dev_s *dev); +static bool misoc_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = misoc_setup, + .shutdown = misoc_shutdown, + .attach = misoc_attach, + .detach = misoc_detach, + .ioctl = misoc_ioctl, + .receive = misoc_receive, + .rxint = misoc_rxint, + .rxavailable = misoc_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = misoc_send, + .txint = misoc_txint, + .txready = misoc_txready, + .txempty = misoc_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_MISOC_UART1 +static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; +#endif + +/* This describes the state of the NR5 UART1 port. */ + +#ifdef CONFIG_MISOC_UART1 +#ifndef CONFIG_MISOC_UART1PRIO +# define CONFIG_MISOC_UART1PRIO 4 +#endif + +static struct misoc_dev_s g_uart1priv = +{ + .uartbase = CSR_UART_BASE, + .irq = UART_INTERRUPT, + .rxtx_addr = CSR_UART_RXTX_ADDR, + .rxempty_addr = CSR_UART_RXEMPTY_ADDR, + .txfull_addr = CSR_UART_TXFULL_ADDR, + .ev_status_addr = CSR_UART_EV_STATUS_ADDR, + .ev_pending_addr = CSR_UART_EV_PENDING_ADDR, + .ev_enable_addr = CSR_UART_EV_ENABLE_ADDR, +}; + +static uart_dev_t g_uart1port = +{ +#if SERIAL_CONSOLE == 1 + .isconsole = 1, +#endif + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: misoc_restoreuartint + ****************************************************************************/ + +static void misoc_restoreuartint(struct uart_dev_s *dev, uint8_t im) +{ + /* Re-enable/re-disable interrupts corresponding to the state of bits in + * im. + */ + + uart_ev_enable_write(im); +} + +/**************************************************************************** + * Name: misoc_disableuartint + ****************************************************************************/ + +static void misoc_disableuartint(struct uart_dev_s *dev, uint8_t *im) +{ + struct misoc_dev_s *priv = (struct misoc_dev_s *)dev->priv; + + if (im) + { + *im = uart_ev_enable_read(); + } + + misoc_restoreuartint(dev, 0); +} + +/**************************************************************************** + * Name: misoc_setup + * + * Description: + * Configure the UART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int misoc_setup(struct uart_dev_s *dev) +{ + uart_ev_pending_write(uart_ev_pending_read()); + return OK; +} + +/**************************************************************************** + * Name: misoc_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void misoc_shutdown(struct uart_dev_s *dev) +{ +} + +/**************************************************************************** + * Name: misoc_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled by the attach method (unless the + * hardware supports multiple levels of interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() methods are called. + * + ****************************************************************************/ + +static int misoc_attach(struct uart_dev_s *dev) +{ + struct misoc_dev_s *priv = (struct misoc_dev_s *)dev->priv; + uint32_t im; + + irq_attach(priv->irq, misoc_uart_interrupt); + + /* enable interrupt */ + /* TODO: move that somewhere proper ! */ + + im = irq_getmask(); + im |= (1 << UART_INTERRUPT); + irq_setmask(im); + + return OK; +} + +/**************************************************************************** + * Name: misoc_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception + * is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void misoc_detach(struct uart_dev_s *dev) +{ + struct misoc_dev_s *priv = (struct misoc_dev_s *)dev->priv; + uint32_t im; + + /* TODO: move that somewhere proper */ + + im = irq_getmask(); + im &= ~(1 << UART_INTERRUPT); + irq_setmask(im); + + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: misoc_interrupt + * + * Description: + * This is the UART interrupt handler. It will be invoked when an + * interrupt received on the 'irq' It should call uart_transmitchars or + * uart_receivechar to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'irq' number into the + * approprite uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int misoc_uart_interrupt(int irq, void *context) +{ + uint32_t stat; + struct uart_dev_s *dev = NULL; + int i; + + dev = &g_uart1port; + + /* Read as much as we can */ + + stat = uart_ev_pending_read(); + if (stat & UART_EV_RX) + { + while (!uart_rxempty_read()) + { + uart_recvchars(dev); + } + } + + /* Try to send all the buffer that were not sent. Does uart_xmitchars + * send only if there is something to send ??? + */ + + if ((stat & UART_EV_TX) != 0) + { + uart_ev_pending_write(UART_EV_TX); + uart_xmitchars(dev); + } + + return OK; +} + +/**************************************************************************** + * Name: misoc_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int misoc_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#ifdef CONFIG_SERIAL_TERMIOS + return -ENOSYS; +#else + return -ENOTTY; +#endif +} + +/**************************************************************************** + * Name: misoc_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int misoc_receive(struct uart_dev_s *dev, uint32_t *status) +{ + int ret; + + if (status != NULL) + { + *status = 0; + } + + ret = uart_rxtx_read(); + + uart_ev_pending_write(UART_EV_RX); + + return ret; +} + +/**************************************************************************** + * Name: misoc_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void misoc_rxint(struct uart_dev_s *dev, bool enable) +{ + uint8_t im; + + im = uart_ev_enable_read(); + if (enable) + { + im |= UART_EV_RX; + } + else + { + im &= ~UART_EV_RX; + } + + uart_ev_enable_write(im); +} + +/**************************************************************************** + * Name: misoc_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +static bool misoc_rxavailable(struct uart_dev_s *dev) +{ + return !uart_rxempty_read(); +} + +/**************************************************************************** + * Name: misoc_send + * + * Description: + * This method will send one byte on the UART. + * + ****************************************************************************/ + +static void misoc_send(struct uart_dev_s *dev, int ch) +{ + uart_rxtx_write(ch); +} + +/**************************************************************************** + * Name: misoc_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void misoc_txint(struct uart_dev_s *dev, bool enable) +{ + uint8_t im; + int i; + + im = uart_ev_enable_read(); + if (enable) + { + im |= UART_EV_TX; + uart_ev_enable_write(im); + + /* Fake an uart INT */ + + uart_xmitchars(dev); + } + else + { + im &= ~UART_EV_TX; + uart_ev_enable_write(im); + } +} + +/**************************************************************************** + * Name: misoc_txready + * + * Description: + * Return true if the tranmsit data register is empty + * + ****************************************************************************/ + +static bool misoc_txready(struct uart_dev_s *dev) +{ + return !uart_txfull_read(); +} + +/**************************************************************************** + * Name: misoc_txempty + * + * Description: + * Return true if the tranmsit data register is empty + * + ****************************************************************************/ + +static bool misoc_txempty(struct uart_dev_s *dev) +{ + return !uart_txfull_read(); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: misoc_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before misoc_serial_initialize. + * + ****************************************************************************/ + +void misoc_earlyserialinit(void) +{ +} + +/**************************************************************************** + * Name: misoc_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + struct uart_dev_s *dev = (struct uart_dev_s *)&CONSOLE_DEV; + uint8_t imr; + + misoc_disableuartint(dev, &imr); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + misoc_lowputc('\r'); + } + + misoc_lowputc(ch); + misoc_restoreuartint(dev, imr); +#endif + return ch; +} + +/**************************************************************************** + * Name: misoc_earlyserialinit, misoc_serial_initialize, and misoc_putc + * + * Description: + * stubs that may be needed. These stubs would be used if all UARTs are + * disabled. In that case, the logic in common/misoc_initialize() is not + * smart enough to know that there are not UARTs and will still expect + * these interfaces to be provided. + * + ****************************************************************************/ + +#else /* HAVE_UART_DEVICE */ +void misoc_earlyserialinit(void) +{ +} + +void misoc_serial_initialize(void) +{ +} + +int up_putc(int ch) +{ + return ch; +} + +#endif /* HAVE_UART_DEVICE */ +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: misoc_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + misoc_lowputc('\r'); + } + + misoc_lowputc(ch); +#endif + + return ch; +} + +#endif /* USE_SERIALDRIVER */ + +void misoc_lowputc(char ch) +{ + while (uart_txfull_read()); + uart_rxtx_write(ch); + uart_ev_pending_write(UART_EV_TX); +} + +/**************************************************************************** + * Name: misoc_serial_initialize + * + * Description: + * Register serial console and serial ports. This assumes + * that misoc_earlyserialinit was called previously. + * + ****************************************************************************/ + +void misoc_serial_initialize(void) +{ +#ifdef USE_SERIALDRIVER + /* Register the console */ + +#ifdef HAVE_SERIAL_CONSOLE + (void)uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* Register all UARTs */ + (void)uart_register("/dev/ttyS0", &TTYS0_DEV); +#endif +} diff --git a/arch/misoc/src/lm32/Make.defs b/arch/misoc/src/lm32/Make.defs index cc4b72da66..4548e6fe32 100644 --- a/arch/misoc/src/lm32/Make.defs +++ b/arch/misoc/src/lm32/Make.defs @@ -37,7 +37,7 @@ HEAD_ASRC = lm32_vectors.S CMN_ASRCS = -CMN_CSRCS = misoc_uart.c +CMN_CSRCS = misoc_serial.c misoc_mdelay.c CHIP_ASRCS = lm32_syscall.S diff --git a/arch/misoc/src/lm32/Toolchain.defs b/arch/misoc/src/lm32/Toolchain.defs index e0227e2e16..f59fa1ab45 100644 --- a/arch/misoc/src/lm32/Toolchain.defs +++ b/arch/misoc/src/lm32/Toolchain.defs @@ -87,8 +87,8 @@ endif # Generic GNU toolchain on OS X, Linux or any typical Posix system ifeq ($(CONFIG_LM32_TOOLCHAIN),GNUL) - CROSSDEV ?= lm32-elf-- - ARCROSSDEV ?= lm32-elf-- + CROSSDEV ?= lm32-elf- + ARCROSSDEV ?= lm32-elf- MAXOPTIMIZATION ?= -Os endif diff --git a/arch/misoc/src/lm32/lm32.h b/arch/misoc/src/lm32/lm32.h index 280c2ff17f..ddfd2320e1 100644 --- a/arch/misoc/src/lm32/lm32.h +++ b/arch/misoc/src/lm32/lm32.h @@ -34,8 +34,8 @@ * ****************************************************************************/ -#ifndef __ARCH_MISOC_SRC_COMMON_LM32_H -#define __ARCH_MISOC_SRC_COMMON_LM32_H +#ifndef __ARCH_MISOC_SRC_LM32_LM32_H +#define __ARCH_MISOC_SRC_LM32_LM32_H /**************************************************************************** * Included Files @@ -141,13 +141,17 @@ void lm32_copystate(uint32_t *dest, uint32_t *src); void lm32_irq_initialize(void); -/* System timer *************************************************************/ +/* Interrupt decode *********************************************************/ -void lm32_timer_initialize(void); +uint32_t *lm32_decodeirq(uint32_t intstat, uint32_t *regs); /* Software interrupts ******************************************************/ -uint32_t *lm32_swint(int irq, FAR void *context); +int lm32_swint(int irq, FAR void *context); + +/* System timer *************************************************************/ + +void lm32_timer_initialize(void); /* Signal handling **********************************************************/ @@ -163,10 +167,5 @@ void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits); void lm32_dumpstate(void); -#undef EXTERN -#ifdef __cplusplus -} -#endif #endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_MISOC_SRC_COMMON_LM32_H */ +#endif /* __ARCH_MISOC_SRC_LM32_LM32_H */ diff --git a/arch/misoc/src/lm32/lm32_config.h b/arch/misoc/src/lm32/lm32_config.h new file mode 100644 index 0000000000..5b0d5d9b03 --- /dev/null +++ b/arch/misoc/src/lm32/lm32_config.h @@ -0,0 +1,97 @@ +/************************************************************************************ + * arch/misoc/src/lm32/lm32_config.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for LM32: + * + * Copyright (C) 2016 Ramin Amin. All rights reserved. + * Author: Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_MISOC_SRC_LM32_LM32_CONFIG_H +#define __ARCH_MISOC_SRC_LM32_LM32_CONFIG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* UARTs ****************************************************************************/ + +/* Are any UARTs enabled? */ + +#undef HAVE_UART_DEVICE +#if defined(CONFIG_MISOC_UART1) || defined(CONFIG_MISOC_UART2) +# define HAVE_UART_DEVICE 1 +#endif + +/* Is there a serial console? There should be no more than one defined. It + * could be on any UARTn, n=1,.. CHIP_NUARTS + */ + +#if defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_MISOC_UART1) +# undef CONFIG_UART2_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_MISOC_UART2) +# undef CONFIG_UART1_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#else +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef HAVE_SERIAL_CONSOLE +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_MISOC_SRC_LM32_LM32_CONFIG_H */ diff --git a/arch/misoc/src/lm32/lm32_decodeirq.c b/arch/misoc/src/lm32/lm32_decodeirq.c index 0df3f73ed9..198445deed 100644 --- a/arch/misoc/src/lm32/lm32_decodeirq.c +++ b/arch/misoc/src/lm32/lm32_decodeirq.c @@ -61,18 +61,10 @@ * ****************************************************************************/ -uint32_t *lm32_decodeirq(uint32_t *regs) +uint32_t *lm32_decodeirq(uint32_t intstat, uint32_t *regs) { - uint32_t intstat; int irq; - /* Read the pending interrupts */ - /* REVISIT: How do I get the interupt status */ -#warning Missing logic - intstat = 0; - - /* REVIST: Do I need to mask the interrupt status with the IM? */ - irqinfo("intstat=%08lx\n", (unsigned long)intstat); /* Decode and dispatch interrupts */ diff --git a/arch/misoc/src/lm32/lm32_doirq.c b/arch/misoc/src/lm32/lm32_doirq.c index e318a65adf..25cc30e2a0 100644 --- a/arch/misoc/src/lm32/lm32_doirq.c +++ b/arch/misoc/src/lm32/lm32_doirq.c @@ -42,10 +42,13 @@ #include #include +#include #include #include #include + +#include #include #include "group/group.h" diff --git a/arch/misoc/src/lm32/lm32_initialize.c b/arch/misoc/src/lm32/lm32_initialize.c index 4efa2ecbf0..23e6e8fc1f 100644 --- a/arch/misoc/src/lm32/lm32_initialize.c +++ b/arch/misoc/src/lm32/lm32_initialize.c @@ -57,6 +57,7 @@ #include +#include "misoc.h" #include "lm32.h" /**************************************************************************** @@ -71,7 +72,7 @@ void up_initialize(void) /* Initialize the serial driver */ -#warning REVISIT: Here you should all lm32_serial_initialize(). That initializes the entire serial driver, a part of the operation is the uart initialization. +#warning REVISIT: Here you should all misoc_serial_initialize(). That initializes the entire serial driver, a part of the operation is the uart initialization. - uart_init(); + misoc_serial_initialize(); } diff --git a/arch/misoc/src/lm32/lm32_swint.c b/arch/misoc/src/lm32/lm32_swint.c index 9e5f932d46..cdfbeeb389 100644 --- a/arch/misoc/src/lm32/lm32_swint.c +++ b/arch/misoc/src/lm32/lm32_swint.c @@ -130,7 +130,7 @@ static void dispatch_syscall(void) * ****************************************************************************/ -uint32_t *lm32_swint(int irq, FAR void *context) +int lm32_swint(int irq, FAR void *context) { uint32_t *regs = (uint32_t *)context; @@ -313,19 +313,5 @@ uint32_t *lm32_swint(int irq, FAR void *context) } #endif - /* If a context switch occurred while processing the interrupt then - * g_current_regs may have change value. If we return any value different - * from the input regs, then the lower level will know that a context - * switch occurred during interrupt processing. - */ - - regs = (uint32_t *)g_current_regs; - - /* Set g_current_regs to NULL to indicate that we are no longer in an - * interrupt handler. - */ - - g_current_regs = NULL; - - return regs; + return OK; } diff --git a/arch/misoc/src/lm32/lm32_vectors.S b/arch/misoc/src/lm32/lm32_vectors.S index f501059997..a7d7d9b621 100644 --- a/arch/misoc/src/lm32/lm32_vectors.S +++ b/arch/misoc/src/lm32/lm32_vectors.S @@ -143,101 +143,103 @@ _do_reset: .clearBSS: be r1, r3, .callMain - sw (r1+0), r0 - addi r1, r1, 4 + sw (r1+0), r0 + addi r1, r1, 4 bi .clearBSS .callMain: bi os_start .save_all: - addi sp, sp, -136 - sw (sp+REG_X0), r0 - sw (sp+REG_X1), r1 - sw (sp+REG_X2), r2 - sw (sp+REG_X3), r3 - sw (sp+REG_X4), r4 - sw (sp+REG_X5), r5 - sw (sp+REG_X6), r6 - sw (sp+REG_X7), r7 - sw (sp+REG_X8), r8 - sw (sp+REG_X9), r9 - sw (sp+REG_X10), r10 - sw (sp+REG_X11), r11 - sw (sp+REG_X12), r12 - sw (sp+REG_X13), r13 - sw (sp+REG_X14), r14 - sw (sp+REG_X15), r15 - sw (sp+REG_X16), r16 - sw (sp+REG_X17), r17 - sw (sp+REG_X18), r18 - sw (sp+REG_X19), r19 - sw (sp+REG_X20), r20 - sw (sp+REG_X21), r21 - sw (sp+REG_X22), r22 - sw (sp+REG_X23), r23 - sw (sp+REG_X24), r24 - sw (sp+REG_X25), r25 - - sw (sp+REG_GP), r26 - sw (sp+REG_FP), r27 - sw (sp+REG_SP), r28 + addi sp, sp, -136 + sw (sp+REG_X0), r0 + sw (sp+REG_X1), r1 + sw (sp+REG_X2), r2 + sw (sp+REG_X3), r3 + sw (sp+REG_X4), r4 + sw (sp+REG_X5), r5 + sw (sp+REG_X6), r6 + sw (sp+REG_X7), r7 + sw (sp+REG_X8), r8 + sw (sp+REG_X9), r9 + sw (sp+REG_X10), r10 + sw (sp+REG_X11), r11 + sw (sp+REG_X12), r12 + sw (sp+REG_X13), r13 + sw (sp+REG_X14), r14 + sw (sp+REG_X15), r15 + sw (sp+REG_X16), r16 + sw (sp+REG_X17), r17 + sw (sp+REG_X18), r18 + sw (sp+REG_X19), r19 + sw (sp+REG_X20), r20 + sw (sp+REG_X21), r21 + sw (sp+REG_X22), r22 + sw (sp+REG_X23), r23 + sw (sp+REG_X24), r24 + sw (sp+REG_X25), r25 + + sw (sp+REG_GP), r26 + sw (sp+REG_FP), r27 + sw (sp+REG_SP), r28 /* reg RA done later */ - sw (sp+REG_EA), r30 - sw (sp+REG_BA), r31 + sw (sp+REG_EA), r30 + sw (sp+REG_BA), r31 /* ra needs to be moved from initial stack location */ - lw r1, (sp+ 136) - sw (sp+REG_RA), r1 + w r1, (sp+ 136) + sw (sp+REG_RA), r1 + + /* Get IE/REG_INT_CTX */ - /* get IE/REG_INT_CTX */ rcsr r1, IE - sw (sp+REG_INT_CTX), r1 + sw (sp+REG_INT_CTX), r1 + + /* The 2nd argument is the regs pointer */ - /* the 2nd argument is the regs pointer */ - addi r2, sp, 0 + addi r2, sp, 0 ret .restore_all_and_eret: /* r1 should have the place where we restore ! */ - lw r2, (r1+REG_X2) - lw r3, (r1+REG_X3) - lw r4, (r1+REG_X4) - lw r5, (r1+REG_X5) - lw r6, (r1+REG_X6) - lw r7, (r1+REG_X7) - lw r8, (r1+REG_X8) - lw r9, (r1+REG_X9) - lw r10, (r1+REG_X10) - lw r11, (r1+REG_X11) - lw r12, (r1+REG_X12) - lw r13, (r1+REG_X13) - lw r14, (r1+REG_X14) - lw r15, (r1+REG_X15) - lw r16, (r1+REG_X16) - lw r17, (r1+REG_X17) - lw r18, (r1+REG_X18) - lw r19, (r1+REG_X19) - lw r20, (r1+REG_X20) - lw r21, (r1+REG_X21) - lw r22, (r1+REG_X22) - lw r23, (r1+REG_X23) - lw r24, (r1+REG_X24) - lw r25, (r1+REG_X25) - lw r26, (r1+REG_GP) - lw r27, (r1+REG_FP) - lw r28, (r1+REG_SP) - lw r29, (r1+REG_RA) - lw r30, (r1+REG_EA) - lw r31, (r1+REG_BA) - lw r1, (r1+REG_INT_CTX) + w r2, (r1+REG_X2) + w r3, (r1+REG_X3) + w r4, (r1+REG_X4) + w r5, (r1+REG_X5) + w r6, (r1+REG_X6) + w r7, (r1+REG_X7) + w r8, (r1+REG_X8) + w r9, (r1+REG_X9) + w r10, (r1+REG_X10) + w r11, (r1+REG_X11) + w r12, (r1+REG_X12) + w r13, (r1+REG_X13) + w r14, (r1+REG_X14) + w r15, (r1+REG_X15) + w r16, (r1+REG_X16) + w r17, (r1+REG_X17) + w r18, (r1+REG_X18) + w r19, (r1+REG_X19) + w r20, (r1+REG_X20) + w r21, (r1+REG_X21) + w r22, (r1+REG_X22) + w r23, (r1+REG_X23) + w r24, (r1+REG_X24) + w r25, (r1+REG_X25) + w r26, (r1+REG_GP) + w r27, (r1+REG_FP) + w r28, (r1+REG_SP) + w r29, (r1+REG_RA) + w r30, (r1+REG_EA) + w r31, (r1+REG_BA) + lw r1, (r1+REG_INT_CTX) wcsr IE, r1 - lw r1, (r1+REG_X1) - addi sp, sp, 136 + w r1, (r1+REG_X1) + addi sp, sp, 136 eret /* This global variable is unsigned long g_idle_topstack and is diff --git a/configs/misoc/include/generated/csr.h b/configs/misoc/include/generated/csr.h index 64bd1915a1..abfa8b39cd 100644 --- a/configs/misoc/include/generated/csr.h +++ b/configs/misoc/include/generated/csr.h @@ -1,397 +1,250 @@ -/**************************************************************************** - * configs/misoc/include/generated/csr.h - * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Ramtin Amin - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __CONFIGS_MISOC_INCLUDE_GENERATED_CSR_H -#define __CONFIGS_MISOC_INCLUDE_GENERATED_CSR_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "hw/common.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* SDRAM */ +#ifndef __GENERATED_CSR_H +#define __GENERATED_CSR_H +#include +/* sdram */ #define CSR_SDRAM_BASE 0xe0004000 #define CSR_SDRAM_DFII_CONTROL_ADDR 0xe0004000 #define CSR_SDRAM_DFII_CONTROL_SIZE 1 - +static inline unsigned char sdram_dfii_control_read(void) { + unsigned char r = MMPTR(0xe0004000); + return r; +} +static inline void sdram_dfii_control_write(unsigned char value) { + MMPTR(0xe0004000) = value; +} #define CSR_SDRAM_DFII_PI0_COMMAND_ADDR 0xe0004004 #define CSR_SDRAM_DFII_PI0_COMMAND_SIZE 1 - +static inline unsigned char sdram_dfii_pi0_command_read(void) { + unsigned char r = MMPTR(0xe0004004); + return r; +} +static inline void sdram_dfii_pi0_command_write(unsigned char value) { + MMPTR(0xe0004004) = value; +} #define CSR_SDRAM_DFII_PI0_COMMAND_ISSUE_ADDR 0xe0004008 #define CSR_SDRAM_DFII_PI0_COMMAND_ISSUE_SIZE 1 - +static inline unsigned char sdram_dfii_pi0_command_issue_read(void) { + unsigned char r = MMPTR(0xe0004008); + return r; +} +static inline void sdram_dfii_pi0_command_issue_write(unsigned char value) { + MMPTR(0xe0004008) = value; +} #define CSR_SDRAM_DFII_PI0_ADDRESS_ADDR 0xe000400c #define CSR_SDRAM_DFII_PI0_ADDRESS_SIZE 2 - +static inline unsigned short int sdram_dfii_pi0_address_read(void) { + unsigned short int r = MMPTR(0xe000400c); + r <<= 8; + r |= MMPTR(0xe0004010); + return r; +} +static inline void sdram_dfii_pi0_address_write(unsigned short int value) { + MMPTR(0xe000400c) = value >> 8; + MMPTR(0xe0004010) = value; +} #define CSR_SDRAM_DFII_PI0_BADDRESS_ADDR 0xe0004014 #define CSR_SDRAM_DFII_PI0_BADDRESS_SIZE 1 - +static inline unsigned char sdram_dfii_pi0_baddress_read(void) { + unsigned char r = MMPTR(0xe0004014); + return r; +} +static inline void sdram_dfii_pi0_baddress_write(unsigned char value) { + MMPTR(0xe0004014) = value; +} #define CSR_SDRAM_DFII_PI0_WRDATA_ADDR 0xe0004018 #define CSR_SDRAM_DFII_PI0_WRDATA_SIZE 2 - +static inline unsigned short int sdram_dfii_pi0_wrdata_read(void) { + unsigned short int r = MMPTR(0xe0004018); + r <<= 8; + r |= MMPTR(0xe000401c); + return r; +} +static inline void sdram_dfii_pi0_wrdata_write(unsigned short int value) { + MMPTR(0xe0004018) = value >> 8; + MMPTR(0xe000401c) = value; +} #define CSR_SDRAM_DFII_PI0_RDDATA_ADDR 0xe0004020 #define CSR_SDRAM_DFII_PI0_RDDATA_SIZE 2 +static inline unsigned short int sdram_dfii_pi0_rddata_read(void) { + unsigned short int r = MMPTR(0xe0004020); + r <<= 8; + r |= MMPTR(0xe0004024); + return r; +} +/* timer0 */ #define CSR_TIMER0_BASE 0xe0002000 #define CSR_TIMER0_LOAD_ADDR 0xe0002000 #define CSR_TIMER0_LOAD_SIZE 4 - +static inline unsigned int timer0_load_read(void) { + unsigned int r = MMPTR(0xe0002000); + r <<= 8; + r |= MMPTR(0xe0002004); + r <<= 8; + r |= MMPTR(0xe0002008); + r <<= 8; + r |= MMPTR(0xe000200c); + return r; +} +static inline void timer0_load_write(unsigned int value) { + MMPTR(0xe0002000) = value >> 24; + MMPTR(0xe0002004) = value >> 16; + MMPTR(0xe0002008) = value >> 8; + MMPTR(0xe000200c) = value; +} #define CSR_TIMER0_RELOAD_ADDR 0xe0002010 #define CSR_TIMER0_RELOAD_SIZE 4 - +static inline unsigned int timer0_reload_read(void) { + unsigned int r = MMPTR(0xe0002010); + r <<= 8; + r |= MMPTR(0xe0002014); + r <<= 8; + r |= MMPTR(0xe0002018); + r <<= 8; + r |= MMPTR(0xe000201c); + return r; +} +static inline void timer0_reload_write(unsigned int value) { + MMPTR(0xe0002010) = value >> 24; + MMPTR(0xe0002014) = value >> 16; + MMPTR(0xe0002018) = value >> 8; + MMPTR(0xe000201c) = value; +} #define CSR_TIMER0_EN_ADDR 0xe0002020 #define CSR_TIMER0_EN_SIZE 1 - +static inline unsigned char timer0_en_read(void) { + unsigned char r = MMPTR(0xe0002020); + return r; +} +static inline void timer0_en_write(unsigned char value) { + MMPTR(0xe0002020) = value; +} #define CSR_TIMER0_UPDATE_VALUE_ADDR 0xe0002024 #define CSR_TIMER0_UPDATE_VALUE_SIZE 1 - +static inline unsigned char timer0_update_value_read(void) { + unsigned char r = MMPTR(0xe0002024); + return r; +} +static inline void timer0_update_value_write(unsigned char value) { + MMPTR(0xe0002024) = value; +} #define CSR_TIMER0_VALUE_ADDR 0xe0002028 #define CSR_TIMER0_VALUE_SIZE 4 - +static inline unsigned int timer0_value_read(void) { + unsigned int r = MMPTR(0xe0002028); + r <<= 8; + r |= MMPTR(0xe000202c); + r <<= 8; + r |= MMPTR(0xe0002030); + r <<= 8; + r |= MMPTR(0xe0002034); + return r; +} #define CSR_TIMER0_EV_STATUS_ADDR 0xe0002038 #define CSR_TIMER0_EV_STATUS_SIZE 1 - +static inline unsigned char timer0_ev_status_read(void) { + unsigned char r = MMPTR(0xe0002038); + return r; +} +static inline void timer0_ev_status_write(unsigned char value) { + MMPTR(0xe0002038) = value; +} #define CSR_TIMER0_EV_PENDING_ADDR 0xe000203c #define CSR_TIMER0_EV_PENDING_SIZE 1 - +static inline unsigned char timer0_ev_pending_read(void) { + unsigned char r = MMPTR(0xe000203c); + return r; +} +static inline void timer0_ev_pending_write(unsigned char value) { + MMPTR(0xe000203c) = value; +} #define CSR_TIMER0_EV_ENABLE_ADDR 0xe0002040 #define CSR_TIMER0_EV_ENABLE_SIZE 1 +static inline unsigned char timer0_ev_enable_read(void) { + unsigned char r = MMPTR(0xe0002040); + return r; +} +static inline void timer0_ev_enable_write(unsigned char value) { + MMPTR(0xe0002040) = value; +} +/* uart */ +#define CSR_UART_BASE 0xe0001000 +#define CSR_UART_RXTX_ADDR 0xe0001000 +#define CSR_UART_RXTX_SIZE 1 +static inline unsigned char uart_rxtx_read(void) { + unsigned char r = MMPTR(0xe0001000); + return r; +} +static inline void uart_rxtx_write(unsigned char value) { + MMPTR(0xe0001000) = value; +} #define CSR_UART_TXFULL_ADDR 0xe0001004 #define CSR_UART_TXFULL_SIZE 1 - +static inline unsigned char uart_txfull_read(void) { + unsigned char r = MMPTR(0xe0001004); + return r; +} #define CSR_UART_RXEMPTY_ADDR 0xe0001008 #define CSR_UART_RXEMPTY_SIZE 1 - +static inline unsigned char uart_rxempty_read(void) { + unsigned char r = MMPTR(0xe0001008); + return r; +} #define CSR_UART_EV_STATUS_ADDR 0xe000100c #define CSR_UART_EV_STATUS_SIZE 1 - +static inline unsigned char uart_ev_status_read(void) { + unsigned char r = MMPTR(0xe000100c); + return r; +} +static inline void uart_ev_status_write(unsigned char value) { + MMPTR(0xe000100c) = value; +} #define CSR_UART_EV_PENDING_ADDR 0xe0001010 #define CSR_UART_EV_PENDING_SIZE 1 - +static inline unsigned char uart_ev_pending_read(void) { + unsigned char r = MMPTR(0xe0001010); + return r; +} +static inline void uart_ev_pending_write(unsigned char value) { + MMPTR(0xe0001010) = value; +} #define CSR_UART_EV_ENABLE_ADDR 0xe0001014 #define CSR_UART_EV_ENABLE_SIZE 1 +static inline unsigned char uart_ev_enable_read(void) { + unsigned char r = MMPTR(0xe0001014); + return r; +} +static inline void uart_ev_enable_write(unsigned char value) { + MMPTR(0xe0001014) = value; +} +/* uart_phy */ #define CSR_UART_PHY_BASE 0xe0000800 #define CSR_UART_PHY_TUNING_WORD_ADDR 0xe0000800 #define CSR_UART_PHY_TUNING_WORD_SIZE 4 - -/* Constants */ - +static inline unsigned int uart_phy_tuning_word_read(void) { + unsigned int r = MMPTR(0xe0000800); + r <<= 8; + r |= MMPTR(0xe0000804); + r <<= 8; + r |= MMPTR(0xe0000808); + r <<= 8; + r |= MMPTR(0xe000080c); + return r; +} +static inline void uart_phy_tuning_word_write(unsigned int value) { + MMPTR(0xe0000800) = value >> 24; + MMPTR(0xe0000804) = value >> 16; + MMPTR(0xe0000808) = value >> 8; + MMPTR(0xe000080c) = value; +} + +/* constants */ #define UART_INTERRUPT 0 #define TIMER0_INTERRUPT 1 #define SYSTEM_CLOCK_FREQUENCY 80000000 #define L2_SIZE 8192 -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -static inline unsigned char sdram_dfii_control_read(void) -{ - unsigned char r = MMPTR(0xe0004000); - return r; -} - -static inline void sdram_dfii_control_write(unsigned char value) -{ - MMPTR(0xe0004000) = value; -} - -static inline unsigned char sdram_dfii_pi0_command_read(void) -{ - unsigned char r = MMPTR(0xe0004004); - return r; -} - -static inline void sdram_dfii_pi0_command_write(unsigned char value) -{ - MMPTR(0xe0004004) = value; -} - -static inline unsigned char sdram_dfii_pi0_command_issue_read(void) -{ - unsigned char r = MMPTR(0xe0004008); - return r; -} - -static inline void sdram_dfii_pi0_command_issue_write(unsigned char value) -{ - MMPTR(0xe0004008) = value; -} - -static inline unsigned short int sdram_dfii_pi0_address_read(void) -{ - unsigned short int r = MMPTR(0xe000400c); - r <<= 8; - r |= MMPTR(0xe0004010); - return r; -} - -static inline void sdram_dfii_pi0_address_write(unsigned short int value) -{ - MMPTR(0xe000400c) = value >> 8; - MMPTR(0xe0004010) = value; -} - -static inline unsigned char sdram_dfii_pi0_baddress_read(void) -{ - unsigned char r = MMPTR(0xe0004014); - return r; -} - -static inline void sdram_dfii_pi0_baddress_write(unsigned char value) -{ - MMPTR(0xe0004014) = value; -} - -static inline unsigned short int sdram_dfii_pi0_wrdata_read(void) -{ - unsigned short int r = MMPTR(0xe0004018); - r <<= 8; - r |= MMPTR(0xe000401c); - return r; -} - -static inline void sdram_dfii_pi0_wrdata_write(unsigned short int value) -{ - MMPTR(0xe0004018) = value >> 8; - MMPTR(0xe000401c) = value; -} - -static inline unsigned short int sdram_dfii_pi0_rddata_read(void) -{ - unsigned short int r = MMPTR(0xe0004020); - r <<= 8; - r |= MMPTR(0xe0004024); - return r; -} - -/* Timer0 */ - -static inline unsigned int timer0_load_read(void) -{ - unsigned int r = MMPTR(0xe0002000); - r <<= 8; - r |= MMPTR(0xe0002004); - r <<= 8; - r |= MMPTR(0xe0002008); - r <<= 8; - r |= MMPTR(0xe000200c); - return r; -} - -static inline void timer0_load_write(unsigned int value) -{ - MMPTR(0xe0002000) = value >> 24; - MMPTR(0xe0002004) = value >> 16; - MMPTR(0xe0002008) = value >> 8; - MMPTR(0xe000200c) = value; -} - -static inline unsigned int timer0_reload_read(void) -{ - unsigned int r = MMPTR(0xe0002010); - r <<= 8; - r |= MMPTR(0xe0002014); - r <<= 8; - r |= MMPTR(0xe0002018); - r <<= 8; - r |= MMPTR(0xe000201c); - return r; -} - -static inline void timer0_reload_write(unsigned int value) -{ - MMPTR(0xe0002010) = value >> 24; - MMPTR(0xe0002014) = value >> 16; - MMPTR(0xe0002018) = value >> 8; - MMPTR(0xe000201c) = value; -} - -static inline unsigned char timer0_en_read(void) -{ - unsigned char r = MMPTR(0xe0002020); - return r; -} - -static inline void timer0_en_write(unsigned char value) -{ - MMPTR(0xe0002020) = value; -} - -static inline unsigned char timer0_update_value_read(void) -{ - unsigned char r = MMPTR(0xe0002024); - return r; -} - -static inline void timer0_update_value_write(unsigned char value) -{ - MMPTR(0xe0002024) = value; -} - -static inline unsigned int timer0_value_read(void) -{ - unsigned int r = MMPTR(0xe0002028); - r <<= 8; - r |= MMPTR(0xe000202c); - r <<= 8; - r |= MMPTR(0xe0002030); - r <<= 8; - r |= MMPTR(0xe0002034); - return r; -} - -static inline unsigned char timer0_ev_status_read(void) -{ - unsigned char r = MMPTR(0xe0002038); - return r; -} - -static inline void timer0_ev_status_write(unsigned char value) -{ - MMPTR(0xe0002038) = value; -} - -static inline unsigned char timer0_ev_pending_read(void) -{ - unsigned char r = MMPTR(0xe000203c); - return r; -} - -static inline void timer0_ev_pending_write(unsigned char value) -{ - MMPTR(0xe000203c) = value; -} - -static inline unsigned char timer0_ev_enable_read(void) -{ - unsigned char r = MMPTR(0xe0002040); - return r; -} - -static inline void timer0_ev_enable_write(unsigned char value) -{ - MMPTR(0xe0002040) = value; -} - -/* UART */ - -static inline unsigned char uart_rxtx_read(void) -{ - unsigned char r = MMPTR(0xe0001000); - return r; -} - -static inline void uart_rxtx_write(unsigned char value) -{ - MMPTR(0xe0001000) = value; -} - -static inline unsigned char uart_txfull_read(void) -{ - unsigned char r = MMPTR(0xe0001004); - return r; -} - -static inline unsigned char uart_rxempty_read(void) -{ - unsigned char r = MMPTR(0xe0001008); - return r; -} - -static inline unsigned char uart_ev_status_read(void) -{ - unsigned char r = MMPTR(0xe000100c); - return r; -} - -static inline void uart_ev_status_write(unsigned char value) -{ - MMPTR(0xe000100c) = value; -} - -static inline unsigned char uart_ev_pending_read(void) -{ - unsigned char r = MMPTR(0xe0001010); - return r; -} - -static inline void uart_ev_pending_write(unsigned char value) -{ - MMPTR(0xe0001010) = value; -} - -static inline unsigned char uart_ev_enable_read(void) -{ - unsigned char r = MMPTR(0xe0001014); - return r; -} - -static inline void uart_ev_enable_write(unsigned char value) -{ - MMPTR(0xe0001014) = value; -} - -/* uart_phy */ - -static inline unsigned int uart_phy_tuning_word_read(void) -{ - unsigned int r = MMPTR(0xe0000800); - r <<= 8; - r |= MMPTR(0xe0000804); - r <<= 8; - r |= MMPTR(0xe0000808); - r <<= 8; - r |= MMPTR(0xe000080c); - return r; -} - -static inline void uart_phy_tuning_word_write(unsigned int value) -{ - MMPTR(0xe0000800) = value >> 24; - MMPTR(0xe0000804) = value >> 16; - MMPTR(0xe0000808) = value >> 8; - MMPTR(0xe000080c) = value; -} - -#endif /* __CONFIGS_MISOC_INCLUDE_GENERATED_CSR_H */ +#endif diff --git a/configs/misoc/include/generated/mem.h b/configs/misoc/include/generated/mem.h index dd6b512e91..7b6839d2a9 100644 --- a/configs/misoc/include/generated/mem.h +++ b/configs/misoc/include/generated/mem.h @@ -1,44 +1,5 @@ -/**************************************************************************** - * configs/misoc/include/generated/mem.h - * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Ramtin Amin - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __CONFIGS_MISOC_INCLUDE_GENERATED_MEM_H -#define __CONFIGS_MISOC_INCLUDE_GENERATED_MEM_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ +#ifndef __GENERATED_MEM_H +#define __GENERATED_MEM_H #define ROM_BASE 0x00000000 #define ROM_SIZE 0x00008000 @@ -49,4 +10,4 @@ #define MAIN_RAM_BASE 0x40000000 #define MAIN_RAM_SIZE 0x00800000 -#endif /* __CONFIGS_MISOC_INCLUDE_GENERATED_MEM_H / +#endif diff --git a/configs/misoc/include/generated/regions.ld b/configs/misoc/include/generated/regions.ld index bd7502729b..eb3a45be98 100644 --- a/configs/misoc/include/generated/regions.ld +++ b/configs/misoc/include/generated/regions.ld @@ -1,5 +1,4 @@ -MEMORY -{ +MEMORY { rom : ORIGIN = 0x00000000, LENGTH = 0x00008000 sram : ORIGIN = 0x10000000, LENGTH = 0x00001000 main_ram : ORIGIN = 0x40000000, LENGTH = 0x00800000 diff --git a/configs/misoc/include/generated/sdram_phy.h b/configs/misoc/include/generated/sdram_phy.h index 2161b7d5b9..9fa49eec22 100644 --- a/configs/misoc/include/generated/sdram_phy.h +++ b/configs/misoc/include/generated/sdram_phy.h @@ -1,56 +1,20 @@ -/**************************************************************************** - * configs/misoc/include/generated/common.h - * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Ramtin Amin - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __CONFIGS_MISOC_INCLUDE_GENERATED_SDRAM_PHY_H -#define __CONFIGS_MISOC_INCLUDE_GENERATED_SDRAM_PHY_H - -/**************************************************************************** - * Included Filese - ****************************************************************************/ - -#include "hw/common.h" -#include "hw/flags.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ +#ifndef __GENERATED_SDRAM_PHY_H +#define __GENERATED_SDRAM_PHY_H +#include +#include +#include #define DFII_NPHASES 1 +static void cdelay(int i); + +static void command_p0(int cmd) +{ + sdram_dfii_pi0_command_write(cmd); + sdram_dfii_pi0_command_issue_write(1); +} + + #define sdram_dfii_pird_address_write(X) sdram_dfii_pi0_address_write(X) #define sdram_dfii_piwr_address_write(X) sdram_dfii_pi0_address_write(X) @@ -62,83 +26,55 @@ #define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE -/**************************************************************************** - * Private Data - ****************************************************************************/ - -const unsigned int sdram_dfii_pix_wrdata_addr[1] = -{ - CSR_SDRAM_DFII_PI0_WRDATA_ADDR +const unsigned int sdram_dfii_pix_wrdata_addr[1] = { + CSR_SDRAM_DFII_PI0_WRDATA_ADDR }; -const unsigned int sdram_dfii_pix_rddata_addr[1] = -{ - CSR_SDRAM_DFII_PI0_RDDATA_ADDR +const unsigned int sdram_dfii_pix_rddata_addr[1] = { + CSR_SDRAM_DFII_PI0_RDDATA_ADDR }; -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static void cdelay(int i); - -static void command_p0(int cmd) -{ - sdram_dfii_pi0_command_write(cmd); - sdram_dfii_pi0_command_issue_write(1); -} - static void init_sequence(void) { - /* Bring CKE high */ - - sdram_dfii_pi0_address_write(0x0); - sdram_dfii_pi0_baddress_write(0); - sdram_dfii_control_write(DFII_CONTROL_CKE | DFII_CONTROL_ODT | - DFII_CONTROL_RESET_N); - cdelay(20000); - - /* Precharge All */ - - sdram_dfii_pi0_address_write(0x400); - sdram_dfii_pi0_baddress_write(0); - command_p0(DFII_COMMAND_RAS | DFII_COMMAND_WE | DFII_COMMAND_CS); - - /* Load Mode Register / Reset DLL, CL=2, BL=1 */ - - sdram_dfii_pi0_address_write(0x120); - sdram_dfii_pi0_baddress_write(0); - command_p0(DFII_COMMAND_RAS | DFII_COMMAND_CAS | DFII_COMMAND_WE | - DFII_COMMAND_CS); - cdelay(200); - - /* Precharge All */ + /* Bring CKE high */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N); + cdelay(20000); + + /* Precharge All */ + sdram_dfii_pi0_address_write(0x400); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register / Reset DLL, CL=2, BL=1 */ + sdram_dfii_pi0_address_write(0x120); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + cdelay(200); + + /* Precharge All */ + sdram_dfii_pi0_address_write(0x400); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Auto Refresh */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS); + cdelay(4); + + /* Auto Refresh */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS); + cdelay(4); + + /* Load Mode Register / CL=2, BL=1 */ + sdram_dfii_pi0_address_write(0x20); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + cdelay(200); - sdram_dfii_pi0_address_write(0x400); - sdram_dfii_pi0_baddress_write(0); - command_p0(DFII_COMMAND_RAS | DFII_COMMAND_WE | DFII_COMMAND_CS); - - /* Auto Refresh */ - - sdram_dfii_pi0_address_write(0x0); - sdram_dfii_pi0_baddress_write(0); - command_p0(DFII_COMMAND_RAS | DFII_COMMAND_CAS | DFII_COMMAND_CS); - cdelay(4); - - /* Auto Refresh */ - - sdram_dfii_pi0_address_write(0x0); - sdram_dfii_pi0_baddress_write(0); - command_p0(DFII_COMMAND_RAS | DFII_COMMAND_CAS | DFII_COMMAND_CS); - cdelay(4); - - /* Load Mode Register / CL=2, BL=1 */ - - sdram_dfii_pi0_address_write(0x20); - sdram_dfii_pi0_baddress_write(0); - command_p0(DFII_COMMAND_RAS | DFII_COMMAND_CAS | DFII_COMMAND_WE | - DFII_COMMAND_CS); - cdelay(200); } - -#endif /* __CONFIGS_MISOC_INCLUDE_GENERATED_SDRAM_PHY_H +#endif -- GitLab From af0d7a96fe1fc6969611eecfd0c3dde48caa6af8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 4 Nov 2016 14:42:17 -0600 Subject: [PATCH 340/734] LM32: More standard, common helper functions --- arch/misoc/src/common/misoc.h | 42 ++++++++ arch/misoc/src/common/misoc_lowputs.c | 62 ++++++++++++ arch/misoc/src/common/misoc_modifyreg16.c | 73 ++++++++++++++ arch/misoc/src/common/misoc_modifyreg32.c | 73 ++++++++++++++ arch/misoc/src/common/misoc_modifyreg8.c | 73 ++++++++++++++ arch/misoc/src/common/misoc_puts.c | 63 ++++++++++++ arch/misoc/src/common/misoc_udelay.c | 117 ++++++++++++++++++++++ arch/misoc/src/lm32/Make.defs | 4 +- arch/misoc/src/lm32/lm32.h | 6 -- 9 files changed, 506 insertions(+), 7 deletions(-) create mode 100644 arch/misoc/src/common/misoc_lowputs.c create mode 100644 arch/misoc/src/common/misoc_modifyreg16.c create mode 100644 arch/misoc/src/common/misoc_modifyreg32.c create mode 100644 arch/misoc/src/common/misoc_modifyreg8.c create mode 100644 arch/misoc/src/common/misoc_puts.c create mode 100644 arch/misoc/src/common/misoc_udelay.c diff --git a/arch/misoc/src/common/misoc.h b/arch/misoc/src/common/misoc.h index d487babab2..e95a60e5d7 100644 --- a/arch/misoc/src/common/misoc.h +++ b/arch/misoc/src/common/misoc.h @@ -60,5 +60,47 @@ void misoc_serial_initialize(void); +/**************************************************************************** + * Name: misoc_puts + * + * Description: + * This is a low-level helper function used to support debug. + * + ****************************************************************************/ + +void misoc_puts(const char *str); + +/**************************************************************************** + * Name: misoc_lowputc + * + * Description: + * Low-level, blocking character output the the serial console. + * + ****************************************************************************/ + +void misoc_lowputc(char ch); + +/**************************************************************************** + * Name: misoc_lowputs + * + * Description: + * This is a low-level helper function used to support debug. + * + ****************************************************************************/ + +void misoc_lowputs(const char *str); + +/**************************************************************************** + * Name: modifyreg[N] + * + * Description: + * Atomic modification of registers. + * + ****************************************************************************/ + +void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits); +void modifyreg16(unsigned int addr, uint16_t clearbits, uint16_t setbits); +void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits); + #endif /* __ASSEMBLY__ */ #endif /* __ARCH_MISOC_SRC_COMMON_MISOC_H */ diff --git a/arch/misoc/src/common/misoc_lowputs.c b/arch/misoc/src/common/misoc_lowputs.c new file mode 100644 index 0000000000..d384883816 --- /dev/null +++ b/arch/misoc/src/common/misoc_lowputs.c @@ -0,0 +1,62 @@ +/**************************************************************************** + * arch/misoc/src/common/misoc_lowputs.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "misoc.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: misoc_lowputs + * + * Description: + * This is a low-level helper function used to support debug. + * + ****************************************************************************/ + +void misoc_lowputs(const char *str) +{ + while (*str) + { + up_lowputc(*str++); + } +} diff --git a/arch/misoc/src/common/misoc_modifyreg16.c b/arch/misoc/src/common/misoc_modifyreg16.c new file mode 100644 index 0000000000..a8502dbe54 --- /dev/null +++ b/arch/misoc/src/common/misoc_modifyreg16.c @@ -0,0 +1,73 @@ +/**************************************************************************** + * arch/misoc/src/common/misoc_modifyreg16.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "misoc.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: modifyreg16 + * + * Description: + * Atomically modify the specified bits in a memory mapped register + * + ****************************************************************************/ + +void modifyreg16(unsigned int addr, uint16_t clearbits, uint16_t setbits) +{ + irqstate_t flags; + uint16_t regval; + + flags = enter_critical_section(); + regval = getreg16(addr); + regval &= ~clearbits; + regval |= setbits; + putreg16(regval, addr); + leave_critical_section(flags); +} diff --git a/arch/misoc/src/common/misoc_modifyreg32.c b/arch/misoc/src/common/misoc_modifyreg32.c new file mode 100644 index 0000000000..3e7c2d5419 --- /dev/null +++ b/arch/misoc/src/common/misoc_modifyreg32.c @@ -0,0 +1,73 @@ +/**************************************************************************** + * arch/misoc/src/common/misoc_modifyreg32.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "misoc_arch.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: modifyreg32 + * + * Description: + * Atomically modify the specified bits in a memory mapped register + * + ****************************************************************************/ + +void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits) +{ + irqstate_t flags; + uint32_t regval; + + flags = enter_critical_section(); + regval = getreg32(addr); + regval &= ~clearbits; + regval |= setbits; + putreg32(regval, addr); + leave_critical_section(flags); +} diff --git a/arch/misoc/src/common/misoc_modifyreg8.c b/arch/misoc/src/common/misoc_modifyreg8.c new file mode 100644 index 0000000000..88ba788e7b --- /dev/null +++ b/arch/misoc/src/common/misoc_modifyreg8.c @@ -0,0 +1,73 @@ +/**************************************************************************** + * arch/misoc/src/common/misoc_modifyreg8.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "misoc.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: modifyreg8 + * + * Description: + * Atomically modify the specified bits in a memory mapped register + * + ****************************************************************************/ + +void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits) +{ + irqstate_t flags; + uint8_t regval; + + flags = enter_critical_section(); + regval = getreg8(addr); + regval &= ~clearbits; + regval |= setbits; + putreg8(regval, addr); + leave_critical_section(flags); +} diff --git a/arch/misoc/src/common/misoc_puts.c b/arch/misoc/src/common/misoc_puts.c new file mode 100644 index 0000000000..556c23f829 --- /dev/null +++ b/arch/misoc/src/common/misoc_puts.c @@ -0,0 +1,63 @@ +/**************************************************************************** + * arch/misoc/src/common/misoc_puts.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "misoc.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: misoc_puts + * + * Description: + * This is a low-level helper function used to support debug. + * + ****************************************************************************/ + +void misoc_puts(const char *str) +{ + while (*str) + { + misoc_putc(*str++); + } +} diff --git a/arch/misoc/src/common/misoc_udelay.c b/arch/misoc/src/common/misoc_udelay.c new file mode 100644 index 0000000000..42bbc1f95a --- /dev/null +++ b/arch/misoc/src/common/misoc_udelay.c @@ -0,0 +1,117 @@ +/**************************************************************************** + * arch/misoc/src/common/up_udelay.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CONFIG_BOARD_LOOPSPER100USEC ((CONFIG_BOARD_LOOPSPERMSEC+5)/10) +#define CONFIG_BOARD_LOOPSPER10USEC ((CONFIG_BOARD_LOOPSPERMSEC+50)/100) +#define CONFIG_BOARD_LOOPSPERUSEC ((CONFIG_BOARD_LOOPSPERMSEC+500)/1000) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_udelay + * + * Description: + * Delay inline for the requested number of microseconds. NOTE: Because + * of all of the setup, several microseconds will be lost before the actual + * timing looop begins. Thus, the delay will always be a few microseconds + * longer than requested. + * + * *** NOT multi-tasking friendly *** + * + * ASSUMPTIONS: + * The setting CONFIG_BOARD_LOOPSPERMSEC has been calibrated + * + ****************************************************************************/ + +void up_udelay(useconds_t microseconds) +{ + volatile int i; + + /* We'll do this a little at a time because we expect that the + * CONFIG_BOARD_LOOPSPERUSEC is very inaccurate during to truncation in + * the divisions of its calculation. We'll use the largest values that + * we can in order to prevent significant error buildup in the loops. + */ + + while (microseconds > 1000) + { + for (i = 0; i < CONFIG_BOARD_LOOPSPERMSEC; i++) + { + } + + microseconds -= 1000; + } + + while (microseconds > 100) + { + for (i = 0; i < CONFIG_BOARD_LOOPSPER100USEC; i++) + { + } + + microseconds -= 100; + } + + while (microseconds > 10) + { + for (i = 0; i < CONFIG_BOARD_LOOPSPER10USEC; i++) + { + } + + microseconds -= 10; + } + + while (microseconds > 0) + { + for (i = 0; i < CONFIG_BOARD_LOOPSPERUSEC; i++) + { + } + + microseconds--; + } +} diff --git a/arch/misoc/src/lm32/Make.defs b/arch/misoc/src/lm32/Make.defs index 4548e6fe32..e31fd7f50f 100644 --- a/arch/misoc/src/lm32/Make.defs +++ b/arch/misoc/src/lm32/Make.defs @@ -37,7 +37,9 @@ HEAD_ASRC = lm32_vectors.S CMN_ASRCS = -CMN_CSRCS = misoc_serial.c misoc_mdelay.c +CMN_CSRCS = misoc_lowputs.c misoc_serial.c misoc_mdelay.c +CMN_CSRCS += misoc_modifyreg8.cmisoc_modifyreg16.c misoc_modifyreg32.c +CMN_CSRCS += misoc_puts.c misoc_udelay.c CHIP_ASRCS = lm32_syscall.S diff --git a/arch/misoc/src/lm32/lm32.h b/arch/misoc/src/lm32/lm32.h index ddfd2320e1..a04fb5e571 100644 --- a/arch/misoc/src/lm32/lm32.h +++ b/arch/misoc/src/lm32/lm32.h @@ -157,12 +157,6 @@ void lm32_timer_initialize(void); void lm32_sigdeliver(void); -/* Atomic modification of registers *****************************************/ - -void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits); -void modifyreg16(unsigned int addr, uint16_t clearbits, uint16_t setbits); -void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits); - /* Debug ********************************************************************/ void lm32_dumpstate(void); -- GitLab From 82f880227569c70e24cadd57f7ac9be73b3d867a Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Fri, 4 Nov 2016 21:58:31 +0100 Subject: [PATCH 341/734] typo, missing ( --- arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h | 2 +- arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h index 70c9a2a5aa..f7bf4d122c 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h @@ -580,7 +580,7 @@ # define RCC_PLLI2SCFGR_PLLI2SQ(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT) #define RCC_PLLI2SCFGR_PLLI2SR_SHIFT (28) /* Bits 28-30: PLLI2S division factor for I2S clocks */ #define RCC_PLLI2SCFGR_PLLI2SR_MASK (7 << RCC_PLLI2SCFGR_PLLI2SR_SHIFT) -# define RCC_PLLI2SCFGR_PLLI2SR(n) (uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SR_SHIFT) +# define RCC_PLLI2SCFGR_PLLI2SR(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SR_SHIFT) /* PLLSAI configuration register */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h index a1b9ed4e32..6c8a784068 100644 --- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h @@ -601,7 +601,7 @@ # define RCC_PLLI2SCFGR_PLLI2SQ(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT) #define RCC_PLLI2SCFGR_PLLI2SR_SHIFT (28) /* Bits 28-30: PLLI2S division factor for I2S clocks */ #define RCC_PLLI2SCFGR_PLLI2SR_MASK (7 << RCC_PLLI2SCFGR_PLLI2SR_SHIFT) -# define RCC_PLLI2SCFGR_PLLI2SR(n) (uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SR_SHIFT) +# define RCC_PLLI2SCFGR_PLLI2SR(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SR_SHIFT) /* PLLSAI configuration register */ -- GitLab From b1b20080372e2ce32be7be1f3a63d0b3ab129b81 Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Fri, 4 Nov 2016 22:02:15 +0100 Subject: [PATCH 342/734] bad offset --- arch/arm/src/stm32f7/chip/stm32_otg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/stm32f7/chip/stm32_otg.h b/arch/arm/src/stm32f7/chip/stm32_otg.h index aca7365552..b69ef1a9dd 100644 --- a/arch/arm/src/stm32f7/chip/stm32_otg.h +++ b/arch/arm/src/stm32f7/chip/stm32_otg.h @@ -77,7 +77,7 @@ #define STM32_OTG_CID_OFFSET 0x003c /* Core ID register */ #define STM32_OTG_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ -#define STM32_OTG_DIEPTXF_OFFSET(n) (104+(((n)-1) << 2)) +#define STM32_OTG_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) /* Host-mode control and status registers */ -- GitLab From 0fd38c28836b47ba86321a7a673ce07f06451930 Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Fri, 4 Nov 2016 22:02:46 +0100 Subject: [PATCH 343/734] enable mmc --- configs/stm32f746-ws/nsh/defconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig index 5c0a529820..3da3bc4b5f 100644 --- a/configs/stm32f746-ws/nsh/defconfig +++ b/configs/stm32f746-ws/nsh/defconfig @@ -127,7 +127,7 @@ CONFIG_ARCH_FAMILY="armv7-m" CONFIG_ARCH_CHIP="stm32f7" # CONFIG_ARM_TOOLCHAIN_IAR is not set CONFIG_ARM_TOOLCHAIN_GNU=y -# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARMV7M_USEBASEPRI=y CONFIG_ARCH_HAVE_CMNVECTOR=y CONFIG_ARMV7M_CMNVECTOR=y # CONFIG_ARMV7M_LAZYFPU is not set @@ -312,7 +312,7 @@ CONFIG_STM32F7_OTGFS=y # CONFIG_STM32F7_RNG is not set # CONFIG_STM32F7_SAI1 is not set # CONFIG_STM32F7_SAI2 is not set -##CONFIG_STM32F7_SDMMC1=y +CONFIG_STM32F7_SDMMC1=y # CONFIG_STM32F7_SPDIFRX is not set CONFIG_STM32F7_SPI1=y # CONFIG_STM32F7_SPI2 is not set -- GitLab From 5a9d3b20fab4c07b3a1a735b1699281543338ba0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 4 Nov 2016 17:19:42 -0600 Subject: [PATCH 344/734] LM32: Add README. Update hello defconfig and setenv.sh --- Documentation/README.html | 4 ++- README.txt | 2 ++ arch/misoc/src/lm32/lm32.h | 5 ++-- configs/misoc/README.txt | 54 +++++++++++++++++++++++++++++++++++ configs/misoc/hello/defconfig | 6 ++-- configs/misoc/hello/setenv.sh | 10 ++----- 6 files changed, 67 insertions(+), 14 deletions(-) create mode 100644 configs/misoc/README.txt diff --git a/Documentation/README.html b/Documentation/README.html index baf534cf50..8751b6b37c 100644 --- a/Documentation/README.html +++ b/Documentation/README.html @@ -8,7 +8,7 @@

    NuttX README Files

    -

    Last Updated: November 1, 2016

    +

    Last Updated: November 4, 2016

    @@ -150,6 +150,8 @@ nuttx/ | | `- README.txt | |- mirtoo/ | | `- README.txt + | |- misoc/ + | | `- README.txt | |- moteino-mega/ | | `- README.txt | |- mx1ads/ diff --git a/README.txt b/README.txt index 6203ab4cd1..d2a9a7b9fe 100644 --- a/README.txt +++ b/README.txt @@ -1366,6 +1366,8 @@ nuttx/ | | `- README.txt | |- mirtoo/ | | `- README.txt + | |- misoc/ + | | `- README.txt | |- moteino-mega/ | | `- README.txt | |- mx1ads/ diff --git a/arch/misoc/src/lm32/lm32.h b/arch/misoc/src/lm32/lm32.h index a04fb5e571..7b125578f0 100644 --- a/arch/misoc/src/lm32/lm32.h +++ b/arch/misoc/src/lm32/lm32.h @@ -109,8 +109,9 @@ * Public Data ****************************************************************************/ -extern volatile uint32_t *g_current_regs; +#ifndef __ASSEMBLY__ +extern volatile uint32_t *g_current_regs; extern uint32_t g_idle_topstack; /**************************************************************************** @@ -121,8 +122,6 @@ extern uint32_t g_idle_topstack; * Public Functions ****************************************************************************/ -#ifndef __ASSEMBLY__ - /* Low level initialization provided by board-level logic ******************/ void lm32_board_initialize(void); diff --git a/configs/misoc/README.txt b/configs/misoc/README.txt new file mode 100644 index 0000000000..1c20544513 --- /dev/null +++ b/configs/misoc/README.txt @@ -0,0 +1,54 @@ +Misoc README +============ + +Buildroot Toolchain +=================== + + A GNU GCC-based toolchain is assumed. The files */setenv.sh should + be modified to point to the correct path to the LM32 GCC toolchain (if + different from the default in your PATH variable). + + If you have no LM32 toolchain, one can be cloned from the NuttX + Bitbucket GIT repository (https://bitbucket.org/nuttx/buildroot). + This GNU toolchain builds and executes in the Linux or Cygwin environment. + + 1. You must have already configured Nuttx in /nuttx. + + cd tools + ./configure.sh misoc/ + + 2. Clone the latest buildroot package into + + git clone git@bitbucket.org:nuttx/buildroot.git + + or + + git clone https://patacongo@bitbucket.org/nuttx/buildroot.git + + 3. cd + + 4. cp lm32-elf-defconfig-6.1.0 .config + + 5. make oldconfig + + 6. make + + 7. Edit setenv.h, if necessary, so that the PATH variable includes + the path to the newly built binaries. + + By default, the tools will be at: + + /build_lm32/staging_dir/bin + + That location can be changed by reconfiguring the .config file. + + See the file configs/README.txt in the buildroot source tree. That has more + detailed PLUS some special instructions that you will need to follow if you + are building a LM32 toolchain for Cygwin under Windows. Also included in + that README file is a FAQ of frequent build issues that their work-arounds. + + In order to use the buildroot toolchain, you also must set the following + in your .config file: + + CONFIG_LM3S_TOOLCHAIN_BUILDROOT=y + diff --git a/configs/misoc/hello/defconfig b/configs/misoc/hello/defconfig index f7b4a0082d..b859e4ab2d 100644 --- a/configs/misoc/hello/defconfig +++ b/configs/misoc/hello/defconfig @@ -16,7 +16,7 @@ CONFIG_HOST_LINUX=y # # Build Configuration # -CONFIG_APPS_DIR="../apps" +# CONFIG_APPS_DIR="../apps" CONFIG_BUILD_FLAT=y # CONFIG_BUILD_2PASS is not set @@ -108,6 +108,8 @@ CONFIG_MISOC_UART1=y CONFIG_MISOC_UART=y CONFIG_MISOC_UART_RX_BUF_SIZE=64 CONFIG_MISOC_UART_TX_BUF_SIZE=64 +# CONFIG_LM32_TOOLCHAIN_BUILDROOT is not set +CONFIG_LM32_TOOLCHAIN_GNUL=y # # Architecture Options @@ -546,10 +548,10 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 # CONFIG_EXAMPLES_NRF24L01TERM is not set # CONFIG_EXAMPLES_NSH is not set # CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set diff --git a/configs/misoc/hello/setenv.sh b/configs/misoc/hello/setenv.sh index c66c878239..7ba5ee60e7 100644 --- a/configs/misoc/hello/setenv.sh +++ b/configs/misoc/hello/setenv.sh @@ -48,17 +48,11 @@ if [ -z "${PATH_ORIG}" ]; then export PATH_ORIG="${PATH}" fi -# This is the Cygwin path to the location where I installed the WinAVR -# toolchain under windows. This is *not* the default install -# location so you will probably have to edit this. You will also have -# to edit this if you install the Linux AVR toolchain as well -#export TOOLCHAIN_BIN="/cygdrive/c/WinAVR/bin" - # This is the Cygwin path to the location where I build the buildroot # toolchain. -#export TOOLCHAIN_BIN="${WD}/../buildroot/build_avr/staging_dir/bin" +export TOOLCHAIN_BIN="${WD}/../buildroot/build_lm32/staging_dir/bin" # Add the path to the toolchain to the PATH varialble -#export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" echo "PATH : ${PATH}" -- GitLab From 911e5abb2c7a2eb7a6b4c200871b20390dfab380 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 4 Nov 2016 17:37:10 -0600 Subject: [PATCH 345/734] LM32: Fix various compilation errors that I introduced. --- arch/misoc/include/.gitignore | 3 +++ arch/misoc/src/.gitignore | 5 +++++ arch/misoc/src/common/misoc.h | 14 ++++++++++++++ arch/misoc/src/common/misoc_lowputs.c | 2 +- arch/misoc/src/common/misoc_modifyreg32.c | 2 +- arch/misoc/src/common/misoc_puts.c | 2 +- arch/misoc/src/common/misoc_serial.c | 2 +- arch/misoc/src/lm32/Make.defs | 11 +++++------ arch/misoc/src/lm32/lm32.h | 10 +--------- arch/misoc/src/lm32/lm32_decodeirq.c | 11 ++++++++--- arch/misoc/src/lm32/lm32_doirq.c | 1 - 11 files changed, 40 insertions(+), 23 deletions(-) create mode 100644 arch/misoc/include/.gitignore create mode 100644 arch/misoc/src/.gitignore diff --git a/arch/misoc/include/.gitignore b/arch/misoc/include/.gitignore new file mode 100644 index 0000000000..e6460c4a67 --- /dev/null +++ b/arch/misoc/include/.gitignore @@ -0,0 +1,3 @@ +/board +/chip + diff --git a/arch/misoc/src/.gitignore b/arch/misoc/src/.gitignore new file mode 100644 index 0000000000..dfdfc93543 --- /dev/null +++ b/arch/misoc/src/.gitignore @@ -0,0 +1,5 @@ +/.depend +/Make.dep +/locked.r +/board +/chip diff --git a/arch/misoc/src/common/misoc.h b/arch/misoc/src/common/misoc.h index e95a60e5d7..4726759ea5 100644 --- a/arch/misoc/src/common/misoc.h +++ b/arch/misoc/src/common/misoc.h @@ -42,6 +42,20 @@ ****************************************************************************/ #include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Low-level register access */ + +#define getreg8(a) (*(volatile uint8_t *)(a)) +#define putreg8(v,a) (*(volatile uint8_t *)(a) = (v)) +#define getreg16(a) (*(volatile uint16_t *)(a)) +#define putreg16(v,a) (*(volatile uint16_t *)(a) = (v)) +#define getreg32(a) (*(volatile uint32_t *)(a)) +#define putreg32(v,a) (*(volatile uint32_t *)(a) = (v)) /**************************************************************************** * Public Functions diff --git a/arch/misoc/src/common/misoc_lowputs.c b/arch/misoc/src/common/misoc_lowputs.c index d384883816..7b8b962678 100644 --- a/arch/misoc/src/common/misoc_lowputs.c +++ b/arch/misoc/src/common/misoc_lowputs.c @@ -57,6 +57,6 @@ void misoc_lowputs(const char *str) { while (*str) { - up_lowputc(*str++); + misoc_lowputc(*str++); } } diff --git a/arch/misoc/src/common/misoc_modifyreg32.c b/arch/misoc/src/common/misoc_modifyreg32.c index 3e7c2d5419..65eda199ab 100644 --- a/arch/misoc/src/common/misoc_modifyreg32.c +++ b/arch/misoc/src/common/misoc_modifyreg32.c @@ -45,7 +45,7 @@ #include #include -#include "misoc_arch.h" +#include "misoc.h" /**************************************************************************** * Public Functions diff --git a/arch/misoc/src/common/misoc_puts.c b/arch/misoc/src/common/misoc_puts.c index 556c23f829..f048b74795 100644 --- a/arch/misoc/src/common/misoc_puts.c +++ b/arch/misoc/src/common/misoc_puts.c @@ -58,6 +58,6 @@ void misoc_puts(const char *str) { while (*str) { - misoc_putc(*str++); + up_putc(*str++); } } diff --git a/arch/misoc/src/common/misoc_serial.c b/arch/misoc/src/common/misoc_serial.c index af05eb1bb1..c46e83775a 100644 --- a/arch/misoc/src/common/misoc_serial.c +++ b/arch/misoc/src/common/misoc_serial.c @@ -57,7 +57,7 @@ #include #include "chip.h" -#include "hw/flags.h +#include "hw/flags.h" #include "misoc.h" /**************************************************************************** diff --git a/arch/misoc/src/lm32/Make.defs b/arch/misoc/src/lm32/Make.defs index e31fd7f50f..9c0768b2a4 100644 --- a/arch/misoc/src/lm32/Make.defs +++ b/arch/misoc/src/lm32/Make.defs @@ -38,15 +38,14 @@ HEAD_ASRC = lm32_vectors.S CMN_ASRCS = CMN_CSRCS = misoc_lowputs.c misoc_serial.c misoc_mdelay.c -CMN_CSRCS += misoc_modifyreg8.cmisoc_modifyreg16.c misoc_modifyreg32.c +CMN_CSRCS += misoc_modifyreg8.c misoc_modifyreg16.c misoc_modifyreg32.c CMN_CSRCS += misoc_puts.c misoc_udelay.c CHIP_ASRCS = lm32_syscall.S CHIP_CSRCS = lm32_allocateheap.c lm32_assert.c lm32_blocktask.c CHIP_CSRCS += lm32_copystate.c lm32_createstack.c lm32_decodeirq.c -CHIP_CSRCS += lm32_doirq.c lm32_dumpstate.c lm32_dumpstate.c lm32_exit.c -CHIP_CSRCS += lm32_idle.c lm32_initialize.c lm32_initialstate.c -CHIP_CSRCS += lm32_interruptcontext.c lm32_irq.c lm32_releasepending.c -CHIP_CSRCS += lm32_releasestack.c lm32_stackframe.c lm32_swint.c -CHIP_CSRCS += lm32_unblocktask.c +CHIP_CSRCS += lm32_doirq.c lm32_dumpstate.c lm32_exit.c lm32_idle.c +CHIP_CSRCS += lm32_initialize.c lm32_initialstate.c lm32_interruptcontext.c +CHIP_CSRCS += lm32_irq.c lm32_releasepending.c lm32_releasestack.c +CHIP_CSRCS += lm32_stackframe.c lm32_swint.c lm32_unblocktask.c diff --git a/arch/misoc/src/lm32/lm32.h b/arch/misoc/src/lm32/lm32.h index 7b125578f0..eac1fe7651 100644 --- a/arch/misoc/src/lm32/lm32.h +++ b/arch/misoc/src/lm32/lm32.h @@ -92,15 +92,6 @@ # endif #endif -/* Low-level register access */ - -#define getreg8(a) (*(volatile uint8_t *)(a)) -#define putreg8(v,a) (*(volatile uint8_t *)(a) = (v)) -#define getreg16(a) (*(volatile uint16_t *)(a)) -#define putreg16(v,a) (*(volatile uint16_t *)(a) = (v)) -#define getreg32(a) (*(volatile uint32_t *)(a)) -#define putreg32(v,a) (*(volatile uint32_t *)(a) = (v)) - /**************************************************************************** * Public Types ****************************************************************************/ @@ -143,6 +134,7 @@ void lm32_irq_initialize(void); /* Interrupt decode *********************************************************/ uint32_t *lm32_decodeirq(uint32_t intstat, uint32_t *regs); +uint32_t *lm32_doirq(int irq, uint32_t *regs); /* Software interrupts ******************************************************/ diff --git a/arch/misoc/src/lm32/lm32_decodeirq.c b/arch/misoc/src/lm32/lm32_decodeirq.c index 198445deed..1cb792cedf 100644 --- a/arch/misoc/src/lm32/lm32_decodeirq.c +++ b/arch/misoc/src/lm32/lm32_decodeirq.c @@ -39,6 +39,11 @@ #include +#include +#include + +#include + #include "chip.h" #include "lm32.h" @@ -69,13 +74,13 @@ uint32_t *lm32_decodeirq(uint32_t intstat, uint32_t *regs) /* Decode and dispatch interrupts */ - for (irq = 0; irq < MISOC_NINTERRUPTS & instat != 0; i++) + for (irq = 0; irq < MISOC_NINTERRUPTS && intstat != 0; irq++) { uint32_t bit = (1 << irq); /* Is this interrupt pending? */ - if ((instat & bit) != 0) + if ((intstat & bit) != 0) { /* Yes.. Dispatch the interrupt */ /* REVIST: Do I need to acknowledge the interrupt first? */ @@ -87,7 +92,7 @@ uint32_t *lm32_decodeirq(uint32_t intstat, uint32_t *regs) * break out of the loop early. */ - instat &= ~bit; + intstat &= ~bit; } } diff --git a/arch/misoc/src/lm32/lm32_doirq.c b/arch/misoc/src/lm32/lm32_doirq.c index 25cc30e2a0..cf42f4e699 100644 --- a/arch/misoc/src/lm32/lm32_doirq.c +++ b/arch/misoc/src/lm32/lm32_doirq.c @@ -126,7 +126,6 @@ uint32_t *lm32_doirq(int irq, uint32_t *regs) /* Unmask the last interrupt (global interrupts are still disabled) */ up_enable_irq(irq); -#endif board_autoled_off(LED_INIRQ); return regs; } -- GitLab From 6cc73f04057d737e2fa6079a5733fb9e5f036e00 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 4 Nov 2016 17:42:10 -0600 Subject: [PATCH 346/734] LM32: Fix a copy/paste error in lm32_vectors.S that I introduced. --- arch/misoc/src/lm32/lm32_vectors.S | 64 +++++++++++++++--------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/arch/misoc/src/lm32/lm32_vectors.S b/arch/misoc/src/lm32/lm32_vectors.S index a7d7d9b621..aa66237565 100644 --- a/arch/misoc/src/lm32/lm32_vectors.S +++ b/arch/misoc/src/lm32/lm32_vectors.S @@ -190,7 +190,7 @@ _do_reset: /* ra needs to be moved from initial stack location */ - w r1, (sp+ 136) + lw r1, (sp+ 136) sw (sp+REG_RA), r1 /* Get IE/REG_INT_CTX */ @@ -206,39 +206,39 @@ _do_reset: .restore_all_and_eret: /* r1 should have the place where we restore ! */ - w r2, (r1+REG_X2) - w r3, (r1+REG_X3) - w r4, (r1+REG_X4) - w r5, (r1+REG_X5) - w r6, (r1+REG_X6) - w r7, (r1+REG_X7) - w r8, (r1+REG_X8) - w r9, (r1+REG_X9) - w r10, (r1+REG_X10) - w r11, (r1+REG_X11) - w r12, (r1+REG_X12) - w r13, (r1+REG_X13) - w r14, (r1+REG_X14) - w r15, (r1+REG_X15) - w r16, (r1+REG_X16) - w r17, (r1+REG_X17) - w r18, (r1+REG_X18) - w r19, (r1+REG_X19) - w r20, (r1+REG_X20) - w r21, (r1+REG_X21) - w r22, (r1+REG_X22) - w r23, (r1+REG_X23) - w r24, (r1+REG_X24) - w r25, (r1+REG_X25) - w r26, (r1+REG_GP) - w r27, (r1+REG_FP) - w r28, (r1+REG_SP) - w r29, (r1+REG_RA) - w r30, (r1+REG_EA) - w r31, (r1+REG_BA) + lw r2, (r1+REG_X2) + lw r3, (r1+REG_X3) + lw r4, (r1+REG_X4) + lw r5, (r1+REG_X5) + lw r6, (r1+REG_X6) + lw r7, (r1+REG_X7) + lw r8, (r1+REG_X8) + lw r9, (r1+REG_X9) + lw r10, (r1+REG_X10) + lw r11, (r1+REG_X11) + lw r12, (r1+REG_X12) + lw r13, (r1+REG_X13) + lw r14, (r1+REG_X14) + lw r15, (r1+REG_X15) + lw r16, (r1+REG_X16) + lw r17, (r1+REG_X17) + lw r18, (r1+REG_X18) + lw r19, (r1+REG_X19) + lw r20, (r1+REG_X20) + lw r21, (r1+REG_X21) + lw r22, (r1+REG_X22) + lw r23, (r1+REG_X23) + lw r24, (r1+REG_X24) + lw r25, (r1+REG_X25) + lw r26, (r1+REG_GP) + lw r27, (r1+REG_FP) + lw r28, (r1+REG_SP) + lw r29, (r1+REG_RA) + lw r30, (r1+REG_EA) + lw r31, (r1+REG_BA) lw r1, (r1+REG_INT_CTX) wcsr IE, r1 - w r1, (r1+REG_X1) + lw r1, (r1+REG_X1) addi sp, sp, 136 eret -- GitLab From 0b83e8afaa900d89148846ec0c8e0e5a83c8475a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 4 Nov 2016 17:48:24 -0600 Subject: [PATCH 347/734] LM32: Remove some extra spacing --- arch/misoc/src/lm32/lm32_vectors.S | 60 +++++++++++++++--------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/arch/misoc/src/lm32/lm32_vectors.S b/arch/misoc/src/lm32/lm32_vectors.S index aa66237565..80645f834d 100644 --- a/arch/misoc/src/lm32/lm32_vectors.S +++ b/arch/misoc/src/lm32/lm32_vectors.S @@ -206,39 +206,39 @@ _do_reset: .restore_all_and_eret: /* r1 should have the place where we restore ! */ - lw r2, (r1+REG_X2) - lw r3, (r1+REG_X3) - lw r4, (r1+REG_X4) - lw r5, (r1+REG_X5) - lw r6, (r1+REG_X6) - lw r7, (r1+REG_X7) - lw r8, (r1+REG_X8) - lw r9, (r1+REG_X9) + lw r2, (r1+REG_X2) + lw r3, (r1+REG_X3) + lw r4, (r1+REG_X4) + lw r5, (r1+REG_X5) + lw r6, (r1+REG_X6) + lw r7, (r1+REG_X7) + lw r8, (r1+REG_X8) + lw r9, (r1+REG_X9) lw r10, (r1+REG_X10) - lw r11, (r1+REG_X11) - lw r12, (r1+REG_X12) - lw r13, (r1+REG_X13) - lw r14, (r1+REG_X14) - lw r15, (r1+REG_X15) - lw r16, (r1+REG_X16) - lw r17, (r1+REG_X17) - lw r18, (r1+REG_X18) - lw r19, (r1+REG_X19) - lw r20, (r1+REG_X20) - lw r21, (r1+REG_X21) - lw r22, (r1+REG_X22) - lw r23, (r1+REG_X23) - lw r24, (r1+REG_X24) - lw r25, (r1+REG_X25) - lw r26, (r1+REG_GP) - lw r27, (r1+REG_FP) - lw r28, (r1+REG_SP) - lw r29, (r1+REG_RA) - lw r30, (r1+REG_EA) - lw r31, (r1+REG_BA) + lw r11, (r1+REG_X11) + lw r12, (r1+REG_X12) + lw r13, (r1+REG_X13) + lw r14, (r1+REG_X14) + lw r15, (r1+REG_X15) + lw r16, (r1+REG_X16) + lw r17, (r1+REG_X17) + lw r18, (r1+REG_X18) + lw r19, (r1+REG_X19) + lw r20, (r1+REG_X20) + lw r21, (r1+REG_X21) + lw r22, (r1+REG_X22) + lw r23, (r1+REG_X23) + lw r24, (r1+REG_X24) + lw r25, (r1+REG_X25) + lw r26, (r1+REG_GP) + lw r27, (r1+REG_FP) + lw r28, (r1+REG_SP) + lw r29, (r1+REG_RA) + lw r30, (r1+REG_EA) + lw r31, (r1+REG_BA) lw r1, (r1+REG_INT_CTX) wcsr IE, r1 - lw r1, (r1+REG_X1) + lw r1, (r1+REG_X1) addi sp, sp, 136 eret -- GitLab From 1c05eb651c45830ae6f4256883493a4d5e8f6f68 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 4 Nov 2016 19:29:54 -0600 Subject: [PATCH 348/734] LM32: lm32_vectors.S needs to call lm32_doirq(), passing two parameters --- arch/misoc/src/lm32/lm32_vectors.S | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/misoc/src/lm32/lm32_vectors.S b/arch/misoc/src/lm32/lm32_vectors.S index 80645f834d..f3dd955f86 100644 --- a/arch/misoc/src/lm32/lm32_vectors.S +++ b/arch/misoc/src/lm32/lm32_vectors.S @@ -38,7 +38,7 @@ * Included Files ****************************************************************************/ -#include +#include /**************************************************************************** * Exception handlers - Must be 32 bytes long. @@ -121,12 +121,11 @@ _interrupt_handler: _syscall_handler: sw (sp+0), ra calli .save_all - rcsr r1, IP - calli lm32_swint + mvi r1, MISOC_IRQ_SWINT + rcsr r2, IP + calli lm32_doirq bi .restore_all_and_eret nop - nop - nop _do_reset: /* Setup stack and global pointer */ -- GitLab From 3f150daf9657df24b3049ed2844c1a1f104a3fa0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 4 Nov 2016 19:41:43 -0600 Subject: [PATCH 349/734] LM32: Oops, missed one line of code in the manual application of a patch --- arch/misoc/src/lm32/lm32_vectors.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/misoc/src/lm32/lm32_vectors.S b/arch/misoc/src/lm32/lm32_vectors.S index f3dd955f86..4a0e6cd095 100644 --- a/arch/misoc/src/lm32/lm32_vectors.S +++ b/arch/misoc/src/lm32/lm32_vectors.S @@ -120,6 +120,7 @@ _interrupt_handler: _syscall_handler: sw (sp+0), ra + addi ea, ea, 4 calli .save_all mvi r1, MISOC_IRQ_SWINT rcsr r2, IP -- GitLab From b0dffdc2ca9a6d177dcf5114f32a96d934cc92b4 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 5 Nov 2016 07:25:05 -0600 Subject: [PATCH 350/734] Fix a number of header files with mismatched 'extern C {' and '}' --- arch/arm/src/kl/kl_spi.h | 5 +++++ arch/arm/src/lpc43xx/chip/lpc43_ethernet.h | 10 ---------- arch/arm/src/lpc43xx/lpc43_ethernet.h | 3 ++- arch/mips/src/pic32mz/pic32mz-dma.h | 5 +++++ arch/risc-v/src/common/up_internal.h | 16 ++++++++++------ arch/xtensa/src/esp32/esp32_gpio.h | 9 ++------- configs/fire-stm32v2/include/board.h | 8 +++++++- drivers/usbhost/usbhost_composite.h | 9 +++++++++ fs/aio/aio.h | 5 +++++ include/nuttx/arch.h | 3 +-- include/nuttx/binfmt/symtab.h | 5 +++++ libc/aio/aio.h | 5 +++++ net/loopback/loopback.h | 5 +++++ 13 files changed, 61 insertions(+), 27 deletions(-) diff --git a/arch/arm/src/kl/kl_spi.h b/arch/arm/src/kl/kl_spi.h index 466ab832f8..227ab9e6c5 100644 --- a/arch/arm/src/kl/kl_spi.h +++ b/arch/arm/src/kl/kl_spi.h @@ -126,6 +126,11 @@ int kl_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); #endif #endif +#if defined(__cplusplus) +} +#endif +#undef EXTERN + #endif /* __ASSEMBLY__ */ #endif /* CONFIG_KL_SPI0 || CONFIG_KL_SPI1 */ #endif /* __ARCH_ARM_SRC_KL_KL_SPI_H */ diff --git a/arch/arm/src/lpc43xx/chip/lpc43_ethernet.h b/arch/arm/src/lpc43xx/chip/lpc43_ethernet.h index 6da125a6fe..d03ed7123b 100644 --- a/arch/arm/src/lpc43xx/chip/lpc43_ethernet.h +++ b/arch/arm/src/lpc43xx/chip/lpc43_ethernet.h @@ -653,15 +653,5 @@ struct eth_rxdesc_s * Public Functions ****************************************************************************************************/ -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - #endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ETHERNET_H */ - diff --git a/arch/arm/src/lpc43xx/lpc43_ethernet.h b/arch/arm/src/lpc43xx/lpc43_ethernet.h index 55888fc727..7d60a43697 100644 --- a/arch/arm/src/lpc43xx/lpc43_ethernet.h +++ b/arch/arm/src/lpc43xx/lpc43_ethernet.h @@ -55,7 +55,8 @@ #undef EXTERN #if defined(__cplusplus) #define EXTERN extern "C" -extern "C" { +extern "C" +{ #else #define EXTERN extern #endif diff --git a/arch/mips/src/pic32mz/pic32mz-dma.h b/arch/mips/src/pic32mz/pic32mz-dma.h index 99cc6c47c5..3bea2172ee 100644 --- a/arch/mips/src/pic32mz/pic32mz-dma.h +++ b/arch/mips/src/pic32mz/pic32mz-dma.h @@ -224,5 +224,10 @@ void pic32mx_dmadump(DMA_HANDLE handle, const struct pic32mx_dmaregs_s *regs, #endif #endif +#if defined(__cplusplus) +} +#endif +#undef EXTERN + #endif /* __ASSEMBLY__ */ #endif /* __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_DMA_H */ diff --git a/arch/risc-v/src/common/up_internal.h b/arch/risc-v/src/common/up_internal.h index f4481a2269..f18d937150 100644 --- a/arch/risc-v/src/common/up_internal.h +++ b/arch/risc-v/src/common/up_internal.h @@ -104,13 +104,17 @@ * Public Variables ****************************************************************************/ -extern volatile uint32_t *g_current_regs; - -extern uint32_t g_idle_topstack; +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif -/**************************************************************************** - * Inline Functions - ****************************************************************************/ +EXTERN volatile uint32_t *g_current_regs; +EXTERN uint32_t g_idle_topstack; /**************************************************************************** * Public Functions diff --git a/arch/xtensa/src/esp32/esp32_gpio.h b/arch/xtensa/src/esp32/esp32_gpio.h index ea09df2439..e4b647b976 100644 --- a/arch/xtensa/src/esp32/esp32_gpio.h +++ b/arch/xtensa/src/esp32/esp32_gpio.h @@ -199,13 +199,6 @@ void esp32_gpioirqdisable(int irq); # define esp32_gpioirqdisable(irq) #endif -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ - int digitalRead(uint8_t pin); void attachInterrupt(uint8_t pin, void (*)(void), int mode); @@ -214,5 +207,7 @@ void detachInterrupt(uint8_t pin); #ifdef __cplusplus } #endif +#undef EXTERN +#endif /* __ASSEMBLY__ */ #endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_GPIO_H */ diff --git a/configs/fire-stm32v2/include/board.h b/configs/fire-stm32v2/include/board.h index 0f9e7c11aa..4319e397a9 100644 --- a/configs/fire-stm32v2/include/board.h +++ b/configs/fire-stm32v2/include/board.h @@ -371,7 +371,8 @@ #undef EXTERN #if defined(__cplusplus) #define EXTERN extern "C" -extern "C" { +extern "C" +{ #else #define EXTERN extern #endif @@ -406,5 +407,10 @@ void stm32_boardinitialize(void); void fire_lcdclear(uint16_t color); #endif +#if defined(__cplusplus) +} +#endif +#undef EXTERN + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_FIRE_STM32V2_INCLUDE_BOARD_H */ diff --git a/drivers/usbhost/usbhost_composite.h b/drivers/usbhost/usbhost_composite.h index 4d1e35d0d1..765624da2a 100644 --- a/drivers/usbhost/usbhost_composite.h +++ b/drivers/usbhost/usbhost_composite.h @@ -51,6 +51,15 @@ * Public Function Prototypes ****************************************************************************/ +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + /**************************************************************************** * Name: usbhost_composite * diff --git a/fs/aio/aio.h b/fs/aio/aio.h index f74269a19a..73ff7faa79 100644 --- a/fs/aio/aio.h +++ b/fs/aio/aio.h @@ -277,5 +277,10 @@ int aio_queue(FAR struct aio_container_s *aioc, worker_t worker); int aio_signal(pid_t pid, FAR struct aiocb *aiocbp); +#undef EXTERN +#if defined(__cplusplus) +} +#endif + #endif /* CONFIG_FS_AIO */ #endif /* __FS_AIO_AIO_H */ diff --git a/include/nuttx/arch.h b/include/nuttx/arch.h index 1ef8efe4b1..8b83308fc8 100644 --- a/include/nuttx/arch.h +++ b/include/nuttx/arch.h @@ -2294,9 +2294,8 @@ void arch_sporadic_resume(FAR struct tcb_s *tcb); #endif #undef EXTERN -#ifdef __cplusplus +#if defined(__cplusplus) } #endif #endif /* __INCLUDE_NUTTX_ARCH_H */ - diff --git a/include/nuttx/binfmt/symtab.h b/include/nuttx/binfmt/symtab.h index 9e51ca3539..affb7cda17 100644 --- a/include/nuttx/binfmt/symtab.h +++ b/include/nuttx/binfmt/symtab.h @@ -90,4 +90,9 @@ void exec_getsymtab(FAR const struct symtab_s **symtab, FAR int *nsymbols); void exec_setsymtab(FAR const struct symtab_s *symtab, int nsymbols); +#undef EXTERN +#if defined(__cplusplus) +} +#endif + #endif /* __INCLUDE_NUTTX_BINFMT_SYMTAB_H */ diff --git a/libc/aio/aio.h b/libc/aio/aio.h index f28340f3c2..f61e6908f5 100644 --- a/libc/aio/aio.h +++ b/libc/aio/aio.h @@ -69,5 +69,10 @@ extern "C" * Public Function Prototypes ****************************************************************************/ +#undef EXTERN +#if defined(__cplusplus) +} +#endif + #endif /* CONFIG_FS_AIO */ #endif /* __LIBC_AIO_AIO_H */ diff --git a/net/loopback/loopback.h b/net/loopback/loopback.h index 8529fdbd1c..a881f46fdb 100644 --- a/net/loopback/loopback.h +++ b/net/loopback/loopback.h @@ -68,5 +68,10 @@ extern "C" * Public Function Prototypes ****************************************************************************/ +#undef EXTERN +#ifdef __cplusplus +} +#endif + #endif /* CONFIG_NET_LOOPBACK */ #endif /* __NET_LOOPBACK_LOOBACK_H */ -- GitLab From 479c9776a78f551dca293df611947f6722503e8c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 5 Nov 2016 08:42:33 -0600 Subject: [PATCH 351/734] configs/misoc: Should not have CONFIG_MM_SMALL set in defconfig. --- configs/misoc/hello/defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/misoc/hello/defconfig b/configs/misoc/hello/defconfig index b859e4ab2d..39eddd2435 100644 --- a/configs/misoc/hello/defconfig +++ b/configs/misoc/hello/defconfig @@ -443,7 +443,7 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y # # Memory Management # -CONFIG_MM_SMALL=y +# CONFIG_MM_SMALL is not set CONFIG_MM_REGIONS=1 # CONFIG_ARCH_HAVE_HEAP2 is not set # CONFIG_GRAN is not set -- GitLab From 5dc9d963f64364aee3bcea5d153ce722e1cef569 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 5 Nov 2016 08:49:50 -0600 Subject: [PATCH 352/734] configs/misco: CONFIG_DEFAULT_SMALL should not be set either. It is really too late now, hoever, because all of the small defaults have already been set. --- configs/misoc/hello/defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/misoc/hello/defconfig b/configs/misoc/hello/defconfig index 39eddd2435..dddddfd3ee 100644 --- a/configs/misoc/hello/defconfig +++ b/configs/misoc/hello/defconfig @@ -7,7 +7,7 @@ # Build Setup # # CONFIG_EXPERIMENTAL is not set -CONFIG_DEFAULT_SMALL=y +# CONFIG_DEFAULT_SMALL is not set CONFIG_HOST_LINUX=y # CONFIG_HOST_OSX is not set # CONFIG_HOST_WINDOWS is not set -- GitLab From 6f1c5e7b43b4a9ef3be51d1f8a54fe426ee1e247 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 5 Nov 2016 09:44:29 -0600 Subject: [PATCH 353/734] Add some comments. --- mm/mm_heap/mm_initialize.c | 2 +- sched/semaphore/sem_post.c | 17 ++++++++++++++++- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/mm/mm_heap/mm_initialize.c b/mm/mm_heap/mm_initialize.c index cacff9c047..7696676fde 100644 --- a/mm/mm_heap/mm_initialize.c +++ b/mm/mm_heap/mm_initialize.c @@ -79,12 +79,12 @@ void mm_addregion(FAR struct mm_heap_s *heap, FAR void *heapstart, # define IDX 0 #endif +#if defined(CONFIG_MM_SMALL) && !defined(CONFIG_SMALL_MEMORY) /* If the MCU handles wide addresses but the memory manager is configured * for a small heap, then verify that the caller is not doing something * crazy. */ -#if defined(CONFIG_MM_SMALL) && !defined(CONFIG_SMALL_MEMORY) DEBUGASSERT(heapsize <= MMSIZE_MAX+1); #endif diff --git a/sched/semaphore/sem_post.c b/sched/semaphore/sem_post.c index 1c90449953..47487db42a 100644 --- a/sched/semaphore/sem_post.c +++ b/sched/semaphore/sem_post.c @@ -98,7 +98,22 @@ int sem_post(FAR sem_t *sem) flags = enter_critical_section(); - /* Perform the semaphore unlock operation. */ + /* Perform the semaphore unlock operation, releasing this task as a + * holder then also incrementing the count on the semaphore. + * + * NOTE: When semaphores are used for signaling purposes, the holder + * of the semaphore may not be this thread! In this case, + * sem_releaseholder() will do nothing. + * + * In the case of a mutex this could be simply resolved since there is + * only one holder but for the case of counting semaphores, there may + * be many holders and if the holder is not this thread, then it is + * not possible to know which thread/holder should be released. + * + * For this reason, it is recommended that priority inheritance be + * disabled via sem_setprotocol(SEM_PRIO_NONE) when the semahore is + * initialixed if the semaphore is to used for signaling purposes. + */ ASSERT(sem->semcount < SEM_VALUE_MAX); sem_releaseholder(sem); -- GitLab From 796969f6b650b9d025c6c77c32b5944dc7cd22d5 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 5 Nov 2016 11:06:52 -0600 Subject: [PATCH 354/734] Update TODO. Provide do-nothing stubs for mutex attribute interfaces if features not enabled. pthread_cond includes a signaling semaphore and should call sem_setprotocol. --- TODO | 16 +++++++++++- arch/sim/src/up_uartwait.c | 2 +- include/pthread.h | 25 ++++++------------ libc/pthread/Make.defs | 27 +++++++++----------- libc/pthread/pthread_mutexattr_getprotocol.c | 5 ++++ libc/pthread/pthread_mutexattr_gettype.c | 10 ++++---- libc/pthread/pthread_mutexattr_setprotocol.c | 11 ++++++++ libc/pthread/pthread_mutexattr_settype.c | 13 +++++++--- sched/pthread/pthread_condinit.c | 22 +++++++++++----- 9 files changed, 81 insertions(+), 50 deletions(-) diff --git a/TODO b/TODO index 62d2e562ce..f770f9a2f6 100644 --- a/TODO +++ b/TODO @@ -216,7 +216,7 @@ o Task/Scheduler (sched/) Status: Open Priority: Medium-ish - Title: ISSUES WITH PRIORITY INHERITANCE WHEN SEMAPHORE USED AS IPC + Title: ISSUES WITH PRIORITY INHERITANCE WHEN SEMAPHORE/MUTX IS USED AS IPC Description: Semaphores have multiple uses. The typical usage is where the semaphore is used as lock on one or more resources. In this typical case, priority inheritance works perfectly: The @@ -264,6 +264,20 @@ o Task/Scheduler (sched/) The fix is to call sem_setprotocol(SEM_PRIO_NONE) immediately after the sem_init() call so that there will be no priority inheritance operations on this semaphore used for signalling. + + NOTE also that in NuttX, pthread mutexes are build on top of + binary semaphores. As a result, the above recommendation also + applies when pthread mutexes are used for inter-thread + signaling. That is, a mutex that is used for signaling should + be initialize like this (simplified, no error checking here): + + pthread_mutexattr_t attr; + pthread_mutex_t mutex; + + pthread_mutexattr_init(&attr); + pthread_mutexattr_settype(&attr, PTHREAD_PRIO_NONE); + pthread_mutex_init(&mutex, &attr); + Status: Open Priority: High. If you have priority inheritance enabled and you use semaphores for signalling events, then you *must* call diff --git a/arch/sim/src/up_uartwait.c b/arch/sim/src/up_uartwait.c index 50f6b5f281..681e87dcdd 100644 --- a/arch/sim/src/up_uartwait.c +++ b/arch/sim/src/up_uartwait.c @@ -39,7 +39,7 @@ #include -#include +#include #include "up_internal.h" diff --git a/include/pthread.h b/include/pthread.h index 1c368d737b..ac495e44c2 100644 --- a/include/pthread.h +++ b/include/pthread.h @@ -96,12 +96,10 @@ * An implementation is allowed to map this mutex to one of the other mutex types. */ -#ifdef CONFIG_MUTEX_TYPES -# define PTHREAD_MUTEX_NORMAL 0 -# define PTHREAD_MUTEX_ERRORCHECK 1 -# define PTHREAD_MUTEX_RECURSIVE 2 -# define PTHREAD_MUTEX_DEFAULT PTHREAD_MUTEX_NORMAL -#endif +#define PTHREAD_MUTEX_NORMAL 0 +#define PTHREAD_MUTEX_ERRORCHECK 1 +#define PTHREAD_MUTEX_RECURSIVE 2 +#define PTHREAD_MUTEX_DEFAULT PTHREAD_MUTEX_NORMAL /* Valid ranges for the pthread stacksize attribute */ @@ -389,10 +387,12 @@ int pthread_mutexattr_getpshared(FAR const pthread_mutexattr_t *attr, FAR int *pshared); int pthread_mutexattr_setpshared(FAR pthread_mutexattr_t *attr, int pshared); -#ifdef CONFIG_MUTEX_TYPES int pthread_mutexattr_gettype(const pthread_mutexattr_t *attr, int *type); int pthread_mutexattr_settype(pthread_mutexattr_t *attr, int type); -#endif +int pthread_mutexattr_getprotocol(FAR const pthread_mutexattr_t *attr, + FAR int *protocol); +int pthread_mutexattr_setprotocol(FAR pthread_mutexattr_t *attr, + int protocol); /* The following routines create, delete, lock and unlock mutexes. */ @@ -403,15 +403,6 @@ int pthread_mutex_lock(FAR pthread_mutex_t *mutex); int pthread_mutex_trylock(FAR pthread_mutex_t *mutex); int pthread_mutex_unlock(FAR pthread_mutex_t *mutex); -#ifdef CONFIG_PRIORITY_INHERITANCE -/* Manage priority inheritance */ - -int pthread_mutexattr_getprotocol(FAR const pthread_mutexattr_t *attr, - FAR int *protocol); -int pthread_mutexattr_setprotocol(FAR pthread_mutexattr_t *attr, - int protocol); -#endif - /* Operations on condition variables */ int pthread_condattr_init(FAR pthread_condattr_t *attr); diff --git a/libc/pthread/Make.defs b/libc/pthread/Make.defs index 9d343f6052..bbb3280959 100644 --- a/libc/pthread/Make.defs +++ b/libc/pthread/Make.defs @@ -35,27 +35,24 @@ # Add the pthread C files to the build -CSRCS += pthread_attr_init.c pthread_attr_destroy.c \ - pthread_attr_setschedpolicy.c pthread_attr_getschedpolicy.c \ - pthread_attr_setinheritsched.c pthread_attr_getinheritsched.c \ - pthread_attr_setstacksize.c pthread_attr_getstacksize.c \ - pthread_attr_setschedparam.c pthread_attr_getschedparam.c \ - pthread_barrierattr_init.c pthread_barrierattr_destroy.c \ - pthread_barrierattr_getpshared.c pthread_barrierattr_setpshared.c \ - pthread_condattr_init.c pthread_condattr_destroy.c \ - pthread_mutexattr_init.c pthread_mutexattr_destroy.c \ - pthread_mutexattr_getpshared.c pthread_mutexattr_setpshared.c +CSRCS += pthread_attr_init.c pthread_attr_destroy.c +CSRCS += pthread_attr_setschedpolicy.c pthread_attr_getschedpolicy.c +CSRCS += pthread_attr_setinheritsched.c pthread_attr_getinheritsched.c +CSRCS += pthread_attr_setstacksize.c pthread_attr_getstacksize.c +CSRCS += pthread_attr_setschedparam.c pthread_attr_getschedparam.c +CSRCS += pthread_barrierattr_init.c pthread_barrierattr_destroy.c +CSRCS += pthread_barrierattr_getpshared.c pthread_barrierattr_setpshared.c +CSRCS += pthread_condattr_init.c pthread_condattr_destroy.c +CSRCS += pthread_mutexattr_init.c pthread_mutexattr_destroy.c +CSRCS += pthread_mutexattr_getpshared.c pthread_mutexattr_setpshared.c +CSRCS += pthread_mutexattr_setprotocol.c pthread_mutexattr_getprotocol.c +CSRCS += pthread_mutexattr_settype.c pthread_mutexattr_gettype.c ifeq ($(CONFIG_SMP),y) CSRCS += pthread_attr_getaffinity.c pthread_attr_setaffinity.c endif ifeq ($(CONFIG_MUTEX_TYPES),y) -CSRCS += pthread_mutexattr_settype.c pthread_mutexattr_gettype.c -endif - -ifeq ($(CONFIG_PRIORITY_INHERITANCE),y) -CSRCS += pthread_mutexattr_setprotocol.c pthread_mutexattr_getprotocol.c endif ifeq ($(CONFIG_BUILD_PROTECTED),y) diff --git a/libc/pthread/pthread_mutexattr_getprotocol.c b/libc/pthread/pthread_mutexattr_getprotocol.c index f7851855ac..f803006bb2 100644 --- a/libc/pthread/pthread_mutexattr_getprotocol.c +++ b/libc/pthread/pthread_mutexattr_getprotocol.c @@ -68,6 +68,11 @@ int pthread_mutexattr_getprotocol(FAR const pthread_mutexattr_t *attr, { DEBUGASSERT(attr != NULL && protocol != NULL); +#ifdef CONFIG_PRIORITY_INHERITANCE linfo("Returning %d\n", attr->proto); return attr->proto; +#else + linfo("Returning %d\n", PTHREAD_PRIO_NONE); + return PTHREAD_PRIO_NONE; +#endif } diff --git a/libc/pthread/pthread_mutexattr_gettype.c b/libc/pthread/pthread_mutexattr_gettype.c index c9703f5c01..9f057ae11d 100644 --- a/libc/pthread/pthread_mutexattr_gettype.c +++ b/libc/pthread/pthread_mutexattr_gettype.c @@ -41,8 +41,6 @@ #include #include -#ifdef CONFIG_MUTEX_TYPES - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -67,13 +65,15 @@ int pthread_mutexattr_gettype(const pthread_mutexattr_t *attr, int *type) { - if (attr && type) + if (attr != NULL && type != NULL) { +#ifdef CONFIG_MUTEX_TYPES *type = attr->type; +#else + *type = PTHREAD_MUTEX_NORMAL; +#endif return 0; } return EINVAL; } - -#endif /* CONFIG_MUTEX_TYPES */ diff --git a/libc/pthread/pthread_mutexattr_setprotocol.c b/libc/pthread/pthread_mutexattr_setprotocol.c index 621a94d1c1..0d128e0480 100644 --- a/libc/pthread/pthread_mutexattr_setprotocol.c +++ b/libc/pthread/pthread_mutexattr_setprotocol.c @@ -69,6 +69,7 @@ int pthread_mutexattr_setprotocol(FAR pthread_mutexattr_t *attr, linfo("attr=0x%p protocol=%d\n", attr, protocol); DEBUGASSERT(attr != NULL); +#ifdef CONFIG_PRIORITY_INHERITANCE if (protocol >= PTHREAD_PRIO_NONE && protocol <= PTHREAD_PRIO_PROTECT) { attr->proto = protocol; @@ -76,4 +77,14 @@ int pthread_mutexattr_setprotocol(FAR pthread_mutexattr_t *attr, } return EINVAL; + +#else + if (protocol == PTHREAD_PRIO_NONE) + { + return OK; + } + + return ENOSYS; +#endif + } diff --git a/libc/pthread/pthread_mutexattr_settype.c b/libc/pthread/pthread_mutexattr_settype.c index 9922a34355..b43e86fc12 100644 --- a/libc/pthread/pthread_mutexattr_settype.c +++ b/libc/pthread/pthread_mutexattr_settype.c @@ -41,8 +41,6 @@ #include #include -#ifdef CONFIG_MUTEX_TYPES - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -69,10 +67,17 @@ int pthread_mutexattr_settype(pthread_mutexattr_t *attr, int type) { if (attr && type >= PTHREAD_MUTEX_NORMAL && type <= PTHREAD_MUTEX_RECURSIVE) { +#ifdef CONFIG_MUTEX_TYPES attr->type = type; +#else + if (type != PTHREAD_MUTEX_NORMAL) + { + return ENOSYS; + } +#endif + return OK; } + return EINVAL; } - -#endif /* CONFIG_MUTEX_TYPES */ diff --git a/sched/pthread/pthread_condinit.c b/sched/pthread/pthread_condinit.c index 73a6423c69..7368e0fb5a 100644 --- a/sched/pthread/pthread_condinit.c +++ b/sched/pthread/pthread_condinit.c @@ -1,7 +1,7 @@ /**************************************************************************** * sched/pthread/pthread_condinit.c * - * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -40,9 +40,12 @@ #include #include +#include #include #include +#include + #include "pthread/pthread.h" /**************************************************************************** @@ -71,23 +74,28 @@ int pthread_cond_init(FAR pthread_cond_t *cond, FAR const pthread_condattr_t *at sinfo("cond=0x%p attr=0x%p\n", cond, attr); - if (!cond) + if (cond == NULL) { ret = EINVAL; } - /* Initialize the semaphore contained in the condition structure - * with initial count = 0 + /* Initialize the semaphore contained in the condition structure with + * initial count = 0 */ else if (sem_init((FAR sem_t *)&cond->sem, 0, 0) != OK) { ret = EINVAL; } + else + { + /* The contained semaphore is used for signaling and, hence, should + * not have priority inheritance enabled. + */ + + sem_setprotocol(&cond->sem, SEM_PRIO_NONE); + } sinfo("Returning %d\n", ret); return ret; } - - - -- GitLab From 45f549d2b833fbfebf2439108c805de678646d3a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 5 Nov 2016 17:39:06 -0600 Subject: [PATCH 355/734] LM32: Back out part of last change --- arch/misoc/src/lm32/lm32_vectors.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/misoc/src/lm32/lm32_vectors.S b/arch/misoc/src/lm32/lm32_vectors.S index 4a0e6cd095..dc62cfe25e 100644 --- a/arch/misoc/src/lm32/lm32_vectors.S +++ b/arch/misoc/src/lm32/lm32_vectors.S @@ -123,10 +123,10 @@ _syscall_handler: addi ea, ea, 4 calli .save_all mvi r1, MISOC_IRQ_SWINT - rcsr r2, IP calli lm32_doirq bi .restore_all_and_eret nop + nop _do_reset: /* Setup stack and global pointer */ -- GitLab From 96a200a71cf956019954a475cb3eaf784b4dab3a Mon Sep 17 00:00:00 2001 From: Heesub Shin Date: Tue, 22 Mar 2016 15:15:53 +0900 Subject: [PATCH 356/734] ARMv7-R: fix typo fix trivial typo: s/ARMv7-A/ARMv7-R/ Signed-off-by: Heesub Shin --- arch/arm/src/armv7-r/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/armv7-r/Kconfig b/arch/arm/src/armv7-r/Kconfig index 0582a4fee3..e87315574d 100644 --- a/arch/arm/src/armv7-r/Kconfig +++ b/arch/arm/src/armv7-r/Kconfig @@ -3,7 +3,7 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -comment "ARMv7-A Configuration Options" +comment "ARMv7-R Configuration Options" config ARMV7R_MEMINIT bool -- GitLab From af6e4f59c646017edf5fec9061cf280024705fbe Mon Sep 17 00:00:00 2001 From: Heesub Shin Date: Tue, 22 Mar 2016 15:32:03 +0900 Subject: [PATCH 357/734] ARMv7-R: fix compilation error This commit fixes compilation errors on MPU support for ARMv7-R. Signed-off-by: Heesub Shin --- arch/arm/src/armv7-r/mpu.h | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/arm/src/armv7-r/mpu.h b/arch/arm/src/armv7-r/mpu.h index e9e29cf13f..762bd92e7e 100644 --- a/arch/arm/src/armv7-r/mpu.h +++ b/arch/arm/src/armv7-r/mpu.h @@ -49,6 +49,8 @@ # include # include "up_arch.h" +# include "cache.h" +# include "sctlr.h" # include "cp15.h" #endif @@ -66,7 +68,7 @@ /* Region Base Address Register Definitions */ -#define MPU_RBAR_MASK 0xfffffffc +#define MPU_RBAR_ADDR_MASK 0xfffffffc /* Region Size and Enable Register */ @@ -201,7 +203,7 @@ static inline unsigned int mpu_get_mpuir(void) unsigned int mpuir; __asm__ __volatile__ ( - "\tmrc " CP15_MPUIR(%0) + "\tmrc p15, 0, %0, c0, c0, 4" : "=r" (mpuir) : : "memory" @@ -222,7 +224,7 @@ static inline void mpu_set_drbar(unsigned int drbar) { __asm__ __volatile__ ( - "\tmcr " CP15_DRBAR(%0) + "\tmcr p15, 0, %0, c6, c1, 0" : : "r" (drbar) : "memory" @@ -241,7 +243,7 @@ static inline void mpu_set_drsr(unsigned int drsr) { __asm__ __volatile__ ( - "\tmcr " CP15_DRSR(%0) + "\tmcr p15, 0, %0, c6, c1, 2" : : "r" (drsr) : "memory" @@ -260,7 +262,7 @@ static inline void mpu_set_dracr(unsigned int dracr) { __asm__ __volatile__ ( - "\tmcr " CP15_DRACR(%0) + "\tmcr p15, 0, %0, c6, c1, 4" : : "r" (dracr) : "memory" @@ -280,7 +282,7 @@ static inline void mpu_set_irbar(unsigned int irbar) { __asm__ __volatile__ ( - "\tmcr " CP15_IRBAR(%0) + "\tmcr p15, 0, %0, c6, c1, 1" : : "r" (irbar) : "memory" @@ -301,7 +303,7 @@ static inline void mpu_set_irsr(unsigned int irsr) { __asm__ __volatile__ ( - "\tmcr " CP15_IRSR(%0) + "\tmcr p15, 0, %0, c6, c1, 3" : : "r" (irsr) : "memory" @@ -322,7 +324,7 @@ static inline void mpu_set_iracr(unsigned int iracr) { __asm__ __volatile__ ( - "\tmcr " CP15_IRACR(%0) + "\tmcr p15, 0, %0, c6, c1, 5" : : "r" (iracr) : "memory" @@ -342,7 +344,7 @@ static inline void mpu_set_rgnr(unsigned int rgnr) { __asm__ __volatile__ ( - "\tmcr " CP15_RGNR(%0) + "\tmcr p15, 0, %0, c6, c2, 0" : : "r" (rgnr) : "memory" @@ -422,7 +424,7 @@ static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size) /* Select the region base address */ - mpu_set_drbar(base & MPU_RBAR_ADDR_MASK) | region | MPU_RBAR_VALID); + mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region | MPU_RBAR_VALID); /* Select the region size and the sub-region map */ -- GitLab From 05d477661b3f81a899597c3216ad5d89a8b81ea8 Mon Sep 17 00:00:00 2001 From: Heesub Shin Date: Wed, 23 Mar 2016 16:06:49 +0900 Subject: [PATCH 358/734] ARMv7-R: fix invalid drbar handling In ARMv7-R, [31:5] bits of DRBAR is physical base address and other bits are reserved and SBZ. Thus, there is no point in passing other than the base address. Signed-off-by: Heesub Shin --- arch/arm/src/armv7-r/mpu.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/src/armv7-r/mpu.h b/arch/arm/src/armv7-r/mpu.h index 762bd92e7e..9d11df1997 100644 --- a/arch/arm/src/armv7-r/mpu.h +++ b/arch/arm/src/armv7-r/mpu.h @@ -424,7 +424,7 @@ static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size) /* Select the region base address */ - mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region | MPU_RBAR_VALID); + mpu_set_drbar(base & MPU_RBAR_ADDR_MASK); /* Select the region size and the sub-region map */ @@ -467,7 +467,7 @@ static inline void mpu_user_flash(uintptr_t base, size_t size) /* Select the region base address */ - mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region); + mpu_set_drbar(base & MPU_RBAR_ADDR_MASK); /* Select the region size and the sub-region map */ @@ -508,7 +508,7 @@ static inline void mpu_priv_flash(uintptr_t base, size_t size) /* Select the region base address */ - mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region); + mpu_set_drbar(base & MPU_RBAR_ADDR_MASK); /* Select the region size and the sub-region map */ @@ -548,7 +548,7 @@ static inline void mpu_user_intsram(uintptr_t base, size_t size) /* Select the region base address */ - mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region); + mpu_set_drbar(base & MPU_RBAR_ADDR_MASK); /* Select the region size and the sub-region map */ @@ -589,7 +589,7 @@ static inline void mpu_priv_intsram(uintptr_t base, size_t size) /* Select the region base address */ - mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region); + mpu_set_drbar(base & MPU_RBAR_ADDR_MASK); /* Select the region size and the sub-region map */ @@ -630,7 +630,7 @@ static inline void mpu_user_extsram(uintptr_t base, size_t size) /* Select the region base address */ - mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region); + mpu_set_drbar(base & MPU_RBAR_ADDR_MASK); /* Select the region size and the sub-region map */ @@ -672,7 +672,7 @@ static inline void mpu_priv_extsram(uintptr_t base, size_t size) /* Select the region base address */ - mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region); + mpu_set_drbar(base & MPU_RBAR_ADDR_MASK); /* Select the region size and the sub-region map */ @@ -714,7 +714,7 @@ static inline void mpu_peripheral(uintptr_t base, size_t size) /* Select the region base address */ - mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region); + mpu_set_drbar(base & MPU_RBAR_ADDR_MASK); /* Select the region size and the sub-region map */ -- GitLab From 2b922fcdbd511da9d970c5a24cb1169420aa9356 Mon Sep 17 00:00:00 2001 From: Heesub Shin Date: Tue, 22 Mar 2016 15:40:40 +0900 Subject: [PATCH 359/734] ARMv7-R: remove the redundant update on SCTLR mpu_control() is invoking cp15_wrsctlr() around SCTLR update redundantly. Signed-off-by: Heesub Shin --- arch/arm/src/armv7-r/mpu.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/src/armv7-r/mpu.h b/arch/arm/src/armv7-r/mpu.h index 9d11df1997..5245375bb0 100644 --- a/arch/arm/src/armv7-r/mpu.h +++ b/arch/arm/src/armv7-r/mpu.h @@ -392,7 +392,6 @@ static inline void mpu_control(bool enable) if (enable) { regval |= (SCTLR_M | SCTLR_BR); - cp15_wrsctlr(regval); } else { -- GitLab From 6a1a8460111fae211ce94fefd1318f8017008367 Mon Sep 17 00:00:00 2001 From: Heesub Shin Date: Tue, 22 Mar 2016 15:21:26 +0900 Subject: [PATCH 360/734] ARMv7-R: add new Kconfig entries for d/i-cache Unlike in ARMv7-A/M, Kconfig entries for data and instruction caches are currently missing in ARMv7-R. This commit adds those missing Kconfig entries. Actual implmenetation for those functions will be added in the subsequent patches. Signed-off-by: Heesub Shin --- arch/arm/src/armv7-r/Kconfig | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/src/armv7-r/Kconfig b/arch/arm/src/armv7-r/Kconfig index e87315574d..e4b50492aa 100644 --- a/arch/arm/src/armv7-r/Kconfig +++ b/arch/arm/src/armv7-r/Kconfig @@ -19,6 +19,29 @@ config ARMV7R_MEMINIT the memory initialization first, then explicitly call arm_data_initialize(). +config ARMV7R_HAVE_ICACHE + bool + default n + +config ARMV7R_HAVE_DCACHE + bool + default n + +config ARMV7R_ICACHE + bool "Use I-Cache" + default n + depends on ARMV7R_HAVE_ICACHE + +config ARMV7R_DCACHE + bool "Use D-Cache" + default n + depends on ARMV7R_HAVE_DCACHE + +config ARMV7R_DCACHE_WRITETHROUGH + bool "D-Cache Write-Through" + default n + depends on ARMV7R_DCACHE + config ARMV7R_HAVE_L2CC bool default n -- GitLab From 003511d198ac1ee68363e6d79c16d9a5ad82762b Mon Sep 17 00:00:00 2001 From: Heesub Shin Date: Tue, 22 Mar 2016 15:50:12 +0900 Subject: [PATCH 361/734] ARMv7-R: add cache handling functions This commit adds functions for enabling and disabling d/i-caches which were missing for ARMv7-R. Signed-off-by: Heesub Shin --- arch/arm/src/armv7-r/cache.h | 75 ++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm/src/armv7-r/cache.h b/arch/arm/src/armv7-r/cache.h index 2c60fe2c3d..a0d25c8941 100644 --- a/arch/arm/src/armv7-r/cache.h +++ b/arch/arm/src/armv7-r/cache.h @@ -43,6 +43,7 @@ #include #include +#include "sctlr.h" #include "cp15_cacheops.h" #include "l2cc.h" @@ -50,6 +51,16 @@ * Pre-processor Definitions ************************************************************************************/ +/* intrinsics are used in these inline functions */ + +#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory") +#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory") +#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory") + +#define ARM_DSB() arm_dsb(15) +#define ARM_ISB() arm_isb(15) +#define ARM_DMB() arm_dmb(15) + /************************************************************************************ * Inline Functions ************************************************************************************/ @@ -183,6 +194,70 @@ static inline void arch_flush_dcache(uintptr_t start, uintptr_t end) l2cc_flush(start, end); } +/**************************************************************************** + * Name: arch_enable_icache + * + * Description: + * Enable the I-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void arch_enable_icache(void) +{ +#ifdef CONFIG_ARMV7R_ICACHE + uint32_t regval; + + ARM_DSB(); + ARM_ISB(); + + /* Enable the I-Cache */ + + regval = cp15_rdsctlr(); + if ((regval & SCTLR_I) == 0) + { + cp15_wrsctlr(regval | SCTLR_I); + } + + ARM_DSB(); + ARM_ISB(); +#endif +} + +/**************************************************************************** +* Name: arch_enable_dcache +* +* Description: +* Enable the D-Cache +* +* Input Parameters: +* None +* +* Returned Value: +* None +* +****************************************************************************/ + +static inline void arch_enable_dcache(void) +{ +#ifdef CONFIG_ARMV7R_DCACHE + uint32_t regval; + + /* Enable the D-Cache */ + + regval = cp15_rdsctlr(); + if ((regval & SCTLR_C) == 0) + { + cp15_wrsctlr(regval | SCTLR_C); + } +#endif +} + /**************************************************************************** * Public Data ****************************************************************************/ -- GitLab From 6bfc6b4d238d0b561ed31ebaac74dbaeed186ad3 Mon Sep 17 00:00:00 2001 From: Heesub Shin Date: Tue, 5 Apr 2016 15:09:17 +0900 Subject: [PATCH 362/734] ARMv7-R: fix typo in mpu support s/ARMV7M/ARMV7R/g Reported-by: Eunbong Song Signed-off-by: Heesub Shin --- arch/arm/src/armv7-r/mpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/armv7-r/mpu.h b/arch/arm/src/armv7-r/mpu.h index 5245375bb0..7c1a201567 100644 --- a/arch/arm/src/armv7-r/mpu.h +++ b/arch/arm/src/armv7-r/mpu.h @@ -409,7 +409,7 @@ static inline void mpu_control(bool enable) * ****************************************************************************/ -#if defined(CONFIG_ARMV7M_HAVE_ICACHE) || defined(CONFIG_ARMV7M_DCACHE) +#if defined(CONFIG_ARMV7R_HAVE_ICACHE) || defined(CONFIG_ARMV7R_DCACHE) static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size) { unsigned int region = mpu_allocregion(); -- GitLab From 343243c7c0de3d0696fa19c08d8d81e8d6cf0a1c Mon Sep 17 00:00:00 2001 From: Heesub Shin Date: Thu, 7 Apr 2016 15:51:48 +0900 Subject: [PATCH 363/734] ARMv7-R: fix CPSR corruption after exception handling A sporadic hang with consequent crash is observed when booting: arm_prefetchabort: Prefetch abort. PC: 04d34a00 IFAR: 04d34a00 IFSR: 00000008 up_assert: Assertion failed at file:armv7-r/arm_prefetchabort.c line: 87 task: init up_dumpstate: Current sp: 004c3df0 up_dumpstate: Interrupt stack: up_dumpstate: base: 004c05fc up_dumpstate: size: 00000800 up_dumpstate: User stack: up_dumpstate: base: 004c3f58 up_dumpstate: size: 00000fec up_dumpstate: User Stack up_stackdump: 004c3de0: 004a0d14 004c3df0 004c3f58 004a0d20 00000057 004c2c58 09000000 004a42a4 up_stackdump: 004c3e00: 00000003 004c3e10 004a0f1c 004bbcef 33c44b00 004a0f28 04d34a00 00000008 up_stackdump: 004c3e20: 00000008 004a01bc 004bfd38 00000001 00007fff 00000001 34134a00 d83e4c00 up_stackdump: 004c3e40: 09000000 00000000 33c44b00 d83e4c00 0c3f4c00 00000000 00000000 00000003 up_stackdump: 004c3e60: 004c3e70 004a1494 04d34a00 200b0253 004c3ed8 004a5298 004c3ed8 6d00006d up_stackdump: 004c3e80: 0000006d 004bc3f4 00000009 004a4f64 00000009 b9e0784f 333f3ed0 69d4227d up_stackdump: 004c3ea0: d81f09bd 0f867344 5a7e2c12 8acefd34 5d00dc1b 004bc432 004c3f08 004c0e08 up_stackdump: 004c3ec0: 00000000 00000000 00000000 00000000 00000000 004a4210 004a5258 004a5300 up_stackdump: 004c3ee0: 00000000 00000001 ffffffff 004c3f80 000002b0 004a4234 00000007 004c3f08 up_stackdump: 004c3f00: 004a58b4 004bc432 004bc3f4 004c3f80 000002b0 0000029c 00000000 0000029c up_stackdump: 004c3f20: 00000000 004a5900 0000ff01 00000000 00000000 004a61f4 00000000 004a5fa4 up_stackdump: 004c3f40: 00000000 004a5f6c 00000000 004a2668 00000000 00000000 b7509f04 004c3f64 up_registerdump: R0: 00000001 00007fff 00000001 34134a00 d83e4c00 09000000 00000000 33c44b00 up_registerdump: R8: d83e4c00 0c3f4c00 00000000 00000000 00000003 004c3e70 004a1494 04d34a00 up_registerdump: CPSR: 200b0253 It seems to be caused by the corrupted or wrong CPSR restored on return from exception. NuttX restores the context using code like this: msr spsr, r1 GCC translates this to: msr spsr_fc, r1 As a result, not all SPSR fields are updated on exception return. This should be: msr spsr_fsxc, r1 On some evaluation boards, spsr_svc may have totally invalid value at power-on-reset. As it is not initialized at boot, the code above may result in the corruption of cpsr and thus unexpected behavior. Reported-by: Eunbong Song Signed-off-by: Heesub Shin --- arch/arm/src/armv7-r/arm_vectors.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/armv7-r/arm_vectors.S b/arch/arm/src/armv7-r/arm_vectors.S index 216633e3a3..0f088b7358 100644 --- a/arch/arm/src/armv7-r/arm_vectors.S +++ b/arch/arm/src/armv7-r/arm_vectors.S @@ -202,7 +202,7 @@ arm_vectorirq: /* Restore the CPSR, SVC mode registers and return */ ldr r1, [r0, #(4*REG_CPSR)] /* Fetch the return SPSR */ - msr spsr, r1 /* Set the return mode SPSR */ + msr spsr_cxsf, r1 /* Set the return mode SPSR */ #ifdef CONFIG_BUILD_PROTECTED /* Are we leaving in user mode? If so then we need to restore the @@ -331,7 +331,7 @@ arm_vectorsvc: /* Restore the CPSR, SVC mode registers and return */ ldr r1, [r0, #(4*REG_CPSR)] /* Fetch the return SPSR */ - msr spsr, r1 /* Set the return mode SPSR */ + msr spsr_cxsf, r1 /* Set the return mode SPSR */ #ifdef CONFIG_BUILD_PROTECTED /* Are we leaving in user mode? If so then we need to restore the @@ -913,7 +913,7 @@ arm_vectorfiq: /* Restore the CPSR, SVC mode registers and return */ ldr r1, [r0, #(4*REG_CPSR)] /* Fetch the return SPSR */ - msr spsr, r1 /* Set the return mode SPSR */ + msr spsr_cxsf, r1 /* Set the return mode SPSR */ #ifdef CONFIG_BUILD_PROTECTED /* Are we leaving in user mode? If so then we need to restore the -- GitLab From bda7d9ee4d18a66cbeede91617938223b4f3c7b3 Mon Sep 17 00:00:00 2001 From: Heesub Shin Date: Sun, 6 Nov 2016 15:45:51 +0900 Subject: [PATCH 364/734] ARMv7-R: fix to restore the Thumb flag in CPSR Thumb flag in CPSR is not restored back when the context switch occurs while executing thumb instruction. Reported-by: Eunbong Song Signed-off-by: Byoungtae Cho Signed-off-by: Heesub Shin --- arch/arm/src/armv7-r/arm_fullcontextrestore.S | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/arch/arm/src/armv7-r/arm_fullcontextrestore.S b/arch/arm/src/armv7-r/arm_fullcontextrestore.S index 9f197063b2..b23f613354 100644 --- a/arch/arm/src/armv7-r/arm_fullcontextrestore.S +++ b/arch/arm/src/armv7-r/arm_fullcontextrestore.S @@ -157,20 +157,10 @@ up_fullcontextrestore: */ ldr r1, [r0, #(4*REG_CPSR)] /* Fetch the stored CPSR value */ - msr cpsr, r1 /* Set the CPSR */ - - /* Now recover r0 and r1 */ - - ldr r0, [sp] - ldr r1, [sp, #4] - add sp, sp, #(2*4) - - /* Then return to the address at the stop of the stack, - * destroying the stack frame - */ - - ldr pc, [sp], #4 + msr spsr_cxsf, r1 /* Set the SPSR */ + /* Now recover r0-r1, pc and cpsr, destroying the stack frame */ + ldmia sp!, {r0-r1, pc}^ #endif .size up_fullcontextrestore, . - up_fullcontextrestore -- GitLab From 3c2a00bc4bd4bb93b6217183d8366ebdcd4d9b26 Mon Sep 17 00:00:00 2001 From: Heesub Shin Date: Sun, 6 Nov 2016 07:56:38 -0600 Subject: [PATCH 365/734] LP worker: When queuing new work, don't signal any threads if they are all busy --- sched/wqueue/kwork_queue.c | 4 ++-- sched/wqueue/kwork_signal.c | 17 ++++++++++------- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/sched/wqueue/kwork_queue.c b/sched/wqueue/kwork_queue.c index 3c4acb2d00..0ac27a87b7 100644 --- a/sched/wqueue/kwork_queue.c +++ b/sched/wqueue/kwork_queue.c @@ -152,7 +152,7 @@ int work_queue(int qid, FAR struct work_s *work, worker_t worker, #ifdef CONFIG_SCHED_HPWORK if (qid == HPWORK) { - /* Cancel high priority work */ + /* Queue high priority work */ work_qqueue((FAR struct kwork_wqueue_s *)&g_hpwork, work, worker, arg, delay); return work_signal(HPWORK); @@ -162,7 +162,7 @@ int work_queue(int qid, FAR struct work_s *work, worker_t worker, #ifdef CONFIG_SCHED_LPWORK if (qid == LPWORK) { - /* Cancel low priority work */ + /* Queue low priority work */ work_qqueue((FAR struct kwork_wqueue_s *)&g_lpwork, work, worker, arg, delay); return work_signal(LPWORK); diff --git a/sched/wqueue/kwork_signal.c b/sched/wqueue/kwork_signal.c index 9359fb2e2a..9c5b9a8e97 100644 --- a/sched/wqueue/kwork_signal.c +++ b/sched/wqueue/kwork_signal.c @@ -85,12 +85,11 @@ int work_signal(int qid) #ifdef CONFIG_SCHED_LPWORK if (qid == LPWORK) { - int wndx; int i; /* Find an IDLE worker thread */ - for (wndx = 0, i = 0; i < CONFIG_SCHED_LPNTHREADS; i++) + for (i = 0; i < CONFIG_SCHED_LPNTHREADS; i++) { /* Is this worker thread busy? */ @@ -98,16 +97,20 @@ int work_signal(int qid) { /* No.. select this thread */ - wndx = i; break; } } - /* Use the process ID of the IDLE worker thread (or the ID of worker - * thread 0 if all of the worker threads are busy). - */ + /* If all of the IDLE threads are busy, then just return successfully */ - pid = g_lpwork.worker[wndx].pid; + if (i >= CONFIG_SCHED_LPNTHREADS) + { + return OK; + } + + /* Otherwise, signal the first IDLE thread found */ + + pid = g_lpwork.worker[i].pid; } else #endif -- GitLab From 8e94d8e7cc31f1ec6afb6c8880dc444a7ff92f8a Mon Sep 17 00:00:00 2001 From: Heesub Shin Date: Sun, 6 Nov 2016 07:56:38 -0600 Subject: [PATCH 366/734] Signal sent from work_signal() may interrupt the low priority worker thread that is already running. For example, the worker thread that is waiting for a semaphore could be woken up by the signal and break any synchronization assumption as a result. It also does not make any sense to send signal if it is already running and busy. This commit fixes it. --- sched/wqueue/kwork_queue.c | 4 ++-- sched/wqueue/kwork_signal.c | 17 ++++++++++------- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/sched/wqueue/kwork_queue.c b/sched/wqueue/kwork_queue.c index 3c4acb2d00..0ac27a87b7 100644 --- a/sched/wqueue/kwork_queue.c +++ b/sched/wqueue/kwork_queue.c @@ -152,7 +152,7 @@ int work_queue(int qid, FAR struct work_s *work, worker_t worker, #ifdef CONFIG_SCHED_HPWORK if (qid == HPWORK) { - /* Cancel high priority work */ + /* Queue high priority work */ work_qqueue((FAR struct kwork_wqueue_s *)&g_hpwork, work, worker, arg, delay); return work_signal(HPWORK); @@ -162,7 +162,7 @@ int work_queue(int qid, FAR struct work_s *work, worker_t worker, #ifdef CONFIG_SCHED_LPWORK if (qid == LPWORK) { - /* Cancel low priority work */ + /* Queue low priority work */ work_qqueue((FAR struct kwork_wqueue_s *)&g_lpwork, work, worker, arg, delay); return work_signal(LPWORK); diff --git a/sched/wqueue/kwork_signal.c b/sched/wqueue/kwork_signal.c index 9359fb2e2a..9c5b9a8e97 100644 --- a/sched/wqueue/kwork_signal.c +++ b/sched/wqueue/kwork_signal.c @@ -85,12 +85,11 @@ int work_signal(int qid) #ifdef CONFIG_SCHED_LPWORK if (qid == LPWORK) { - int wndx; int i; /* Find an IDLE worker thread */ - for (wndx = 0, i = 0; i < CONFIG_SCHED_LPNTHREADS; i++) + for (i = 0; i < CONFIG_SCHED_LPNTHREADS; i++) { /* Is this worker thread busy? */ @@ -98,16 +97,20 @@ int work_signal(int qid) { /* No.. select this thread */ - wndx = i; break; } } - /* Use the process ID of the IDLE worker thread (or the ID of worker - * thread 0 if all of the worker threads are busy). - */ + /* If all of the IDLE threads are busy, then just return successfully */ - pid = g_lpwork.worker[wndx].pid; + if (i >= CONFIG_SCHED_LPNTHREADS) + { + return OK; + } + + /* Otherwise, signal the first IDLE thread found */ + + pid = g_lpwork.worker[i].pid; } else #endif -- GitLab From c1a687a4e5c6e0c3938f87bb69eeb1b6a04a20bc Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 6 Nov 2016 08:11:01 -0600 Subject: [PATCH 367/734] Trivial changes from review of last PR --- arch/arm/src/armv7-r/arm_fullcontextrestore.S | 2 +- arch/arm/src/armv7-r/arm_vectors.S | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/src/armv7-r/arm_fullcontextrestore.S b/arch/arm/src/armv7-r/arm_fullcontextrestore.S index b23f613354..06daa22182 100644 --- a/arch/arm/src/armv7-r/arm_fullcontextrestore.S +++ b/arch/arm/src/armv7-r/arm_fullcontextrestore.S @@ -60,7 +60,6 @@ .cpu cortex-r4f #endif .syntax unified - .file "arm_fullcontextrestore.S" /**************************************************************************** * Public Functions @@ -160,6 +159,7 @@ up_fullcontextrestore: msr spsr_cxsf, r1 /* Set the SPSR */ /* Now recover r0-r1, pc and cpsr, destroying the stack frame */ + ldmia sp!, {r0-r1, pc}^ #endif diff --git a/arch/arm/src/armv7-r/arm_vectors.S b/arch/arm/src/armv7-r/arm_vectors.S index 0f088b7358..bea7c927bc 100644 --- a/arch/arm/src/armv7-r/arm_vectors.S +++ b/arch/arm/src/armv7-r/arm_vectors.S @@ -202,7 +202,7 @@ arm_vectorirq: /* Restore the CPSR, SVC mode registers and return */ ldr r1, [r0, #(4*REG_CPSR)] /* Fetch the return SPSR */ - msr spsr_cxsf, r1 /* Set the return mode SPSR */ + msr spsr_cxsf, r1 /* Set the return mode SPSR */ #ifdef CONFIG_BUILD_PROTECTED /* Are we leaving in user mode? If so then we need to restore the @@ -331,7 +331,7 @@ arm_vectorsvc: /* Restore the CPSR, SVC mode registers and return */ ldr r1, [r0, #(4*REG_CPSR)] /* Fetch the return SPSR */ - msr spsr_cxsf, r1 /* Set the return mode SPSR */ + msr spsr_cxsf, r1 /* Set the return mode SPSR */ #ifdef CONFIG_BUILD_PROTECTED /* Are we leaving in user mode? If so then we need to restore the @@ -913,7 +913,7 @@ arm_vectorfiq: /* Restore the CPSR, SVC mode registers and return */ ldr r1, [r0, #(4*REG_CPSR)] /* Fetch the return SPSR */ - msr spsr_cxsf, r1 /* Set the return mode SPSR */ + msr spsr_cxsf, r1 /* Set the return mode SPSR */ #ifdef CONFIG_BUILD_PROTECTED /* Are we leaving in user mode? If so then we need to restore the -- GitLab From 175394904528bd1f3c562d2cc56584731480e738 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 6 Nov 2016 08:55:15 -0600 Subject: [PATCH 368/734] Update README --- configs/misoc/README.txt | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/configs/misoc/README.txt b/configs/misoc/README.txt index 1c20544513..b75eaad7e8 100644 --- a/configs/misoc/README.txt +++ b/configs/misoc/README.txt @@ -16,16 +16,17 @@ Buildroot Toolchain cd tools ./configure.sh misoc/ + make oldconfig context - 2. Clone the latest buildroot package into + 2. Clone the latest buildroot package into /buildroot - git clone git@bitbucket.org:nuttx/buildroot.git + git clone git@bitbucket.org:nuttx/buildroot.git /buildroot or - git clone https://patacongo@bitbucket.org/nuttx/buildroot.git + git clone https://patacongo@bitbucket.org/nuttx/buildroot.git /buildroot - 3. cd + 3. cd /buildroot 4. cp lm32-elf-defconfig-6.1.0 .config @@ -33,14 +34,18 @@ Buildroot Toolchain 6. make - 7. Edit setenv.h, if necessary, so that the PATH variable includes - the path to the newly built binaries. + 7. By default, the tools will be at the absolute path: - By default, the tools will be at: + /buildroot/build_lm32/staging_dir/bin - /build_lm32/staging_dir/bin + Or the NuttX relative path: - That location can be changed by reconfiguring the .config file. + ../buildroot/build_lm32/staging_dir/bin + + The setenv.sh files in these sub-directories are already set to use + the relative path. It you choose to install the buildroot package + in some other location, you may need to edit the setenv.h file so + that the PATH variable includes the path to the newly built binaries. See the file configs/README.txt in the buildroot source tree. That has more detailed PLUS some special instructions that you will need to follow if you -- GitLab From 120d29b4804795579565d9ce4e3852f99b206ae2 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 6 Nov 2016 09:06:37 -0600 Subject: [PATCH 369/734] Update some Kconfig comments --- sched/Kconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/sched/Kconfig b/sched/Kconfig index d06143d7d5..60156e0368 100644 --- a/sched/Kconfig +++ b/sched/Kconfig @@ -803,6 +803,18 @@ menuconfig PRIORITY_INHERITANCE default n ---help--- Set to enable support for priority inheritance on mutexes and semaphores. + When this option is enabled, the initial configuration of all seamphores + and mutexes will be with priority inheritance enabled. That configuration + may not be appropriate in all cases (such as when the semaphore or mutex + is used for signaling). In such cases, priority inheritance be be + disabled for individual semaphores by calling: + + int ret = sem_setprotocol(&sem, SEM_PRIO_NONE); + + And for individual pthread mutexes by setting the protocol attribute + before initializing the mutex: + + int ret = pthread_mutexattr_setprotocol(&attr, PTHREAD_PRIO_NONE); if PRIORITY_INHERITANCE -- GitLab From 860c0f58734688751f41488b64366ebded85fd27 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 6 Nov 2016 10:15:01 -0600 Subject: [PATCH 370/734] Update TODO list. --- TODO | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/TODO b/TODO index f770f9a2f6..703cfad205 100644 --- a/TODO +++ b/TODO @@ -278,11 +278,11 @@ o Task/Scheduler (sched/) pthread_mutexattr_settype(&attr, PTHREAD_PRIO_NONE); pthread_mutex_init(&mutex, &attr); - Status: Open - Priority: High. If you have priority inheritance enabled and you use + Status: Closed. If you have priority inheritance enabled and you use semaphores for signalling events, then you *must* call sem_setprotocol(SEM_PRIO_NONE) immediately after initializing the semaphore. + Priority: High. Title: SCALABILITY Description: Task control information is retained in simple lists. This @@ -466,7 +466,7 @@ o pthreads (sched/pthreads) Priority: Low, probably not that useful Title: PTHREAD_PRIO_PROTECT - Description: Extended pthread_mutexattr_setprotocol() support PTHREAD_PRIO_PROTECT: + Description: Extend pthread_mutexattr_setprotocol() support PTHREAD_PRIO_PROTECT: "When a thread owns one or more mutexes initialized with the PTHREAD_PRIO_PROTECT protocol, it shall execute at the higher of its priority or the highest of the priority ceilings of all the mutexes -- GitLab From 5ac9136b21c4bf24e0286f87d6c39940311a287c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 6 Nov 2016 10:46:11 -0600 Subject: [PATCH 371/734] LM32: Implement some commented out logic in lm32_dumpstate --- arch/misoc/src/lm32/lm32_dumpstate.c | 50 ++++++++++++---------------- 1 file changed, 22 insertions(+), 28 deletions(-) diff --git a/arch/misoc/src/lm32/lm32_dumpstate.c b/arch/misoc/src/lm32/lm32_dumpstate.c index e847bec40c..229aee8bfd 100644 --- a/arch/misoc/src/lm32/lm32_dumpstate.c +++ b/arch/misoc/src/lm32/lm32_dumpstate.c @@ -77,7 +77,6 @@ static inline uint32_t up_getsp(void) static void up_stackdump(uint32_t sp, uint32_t stack_base) { -# if 0 uint32_t stack ; for (stack = sp & ~0x1f; stack < stack_base; stack += 32) @@ -87,7 +86,6 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base) stack, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7]); } -#endif } /**************************************************************************** @@ -96,39 +94,35 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base) static inline void up_registerdump(void) { -#if 0 /* Are user registers available from interrupt processing? */ if (g_current_regs) { _alert("EPC:%08x \n", g_current_regs[REG_EPC]); - _alert("A0:%08x A1:%08x A2:%08x A3:%08x A4:%08x A5:%08x A6:%08x A7:%08x\n", - g_current_regs[REG_A0], g_current_regs[REG_A1], g_current_regs[REG_A2], - g_current_regs[REG_A3], g_current_regs[REG_A4], g_current_regs[REG_A5], - g_current_regs[REG_A6], g_current_regs[REG_A7]); - _alert("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x\n", - g_current_regs[REG_T0], g_current_regs[REG_T1], g_current_regs[REG_T2], - g_current_regs[REG_T3], g_current_regs[REG_T4], g_current_regs[REG_T5], - g_current_regs[REG_T6]); - _alert("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n", - g_current_regs[REG_S0], g_current_regs[REG_S1], g_current_regs[REG_S2], - g_current_regs[REG_S3], g_current_regs[REG_S4], g_current_regs[REG_S5], - g_current_regs[REG_S6], g_current_regs[REG_S7]); - _alert("S8:%08x S9:%08x S10:%08x S11:%08x\n", - g_current_regs[REG_S8], g_current_regs[REG_S9], g_current_regs[REG_S10], - g_current_regs[REG_S11]); -#ifdef RISCV_SAVE_GP - _alert("GP:%08x SP:%08x FP:%08x TP:%08x RA:%08x\n", - g_current_regs[REG_GP], g_current_regs[REG_SP], g_current_regs[REG_FP], - g_current_regs[REG_TP], g_current_regs[REG_RA]); -#else - _alert("SP:%08x FP:%08x TP:%08x RA:%08x\n", - g_current_regs[REG_SP], g_current_regs[REG_FP], g_current_regs[REG_TP], - g_current_regs[REG_RA]); -#endif + _alert(" X0:%08x A0:%08x A1:%08x A2:%08x A3:%08x A4:%08x A5:%08x A6:%08x\n", + g_current_regs[REG_X0_NDX], g_current_regs[REG_X1_NDX], + g_current_regs[REG_X2_NDX], g_current_regs[REG_X3_NDX], + g_current_regs[REG_X4_NDX], g_current_regs[REG_X5_NDX], + g_current_regs[REG_X6_NDX], g_current_regs[REG_X7_NDX]); + _alert(" A7:%08x X9:%08x X10:%08x X11:%08x X12:%08x X13:%08x X14:%08x X15:%08x\n", + g_current_regs[REG_X8_NDX], g_current_regs[REG_X9_NDX], + g_current_regs[REG_X10_NDX], g_current_regs[REG_X11_NDX], + g_current_regs[REG_X12_NDX], g_current_regs[REG_X13_NDX], + g_current_regs[REG_X14_NDX], g_current_regs[REG_X15_NDX]); + _alert("X16:%08x X17:%08x X18:%08x X19:%08x X20:%08x X21:%08x X22:%08x X23:%08x\n", + g_current_regs[REG_X16_NDX], g_current_regs[REG_X17_NDX], + g_current_regs[REG_X18_NDX], g_current_regs[REG_X19_NDX], + g_current_regs[REG_X20_NDX], g_current_regs[REG_X21_NDX], + g_current_regs[REG_X22_NDX], g_current_regs[REG_X23_NDX]); + _alert("X24:%08x X25:%08x GP:%08x FP:%08x SP:%08x RA:%08x EA:%08x BA:%08x\n", + g_current_regs[REG_X24_NDX], g_current_regs[REG_X25_NDX], + g_current_regs[REG_X26_NDX], g_current_regs[REG_X27_NDX], + g_current_regs[REG_X28_NDX], g_current_regs[REG_X29_NDX], + g_current_regs[REG_X30_NDX], g_current_regs[REG_X31_NDX]); + _alert(" IE:%08x\n", + g_current_regs[REG_X32_NDX]); } -#endif } /**************************************************************************** -- GitLab From d6315a3084c1e7088ba31cc2e3671b7fc38d349a Mon Sep 17 00:00:00 2001 From: Lok Tep Date: Mon, 7 Nov 2016 13:11:59 +0100 Subject: [PATCH 372/734] del stm32f74xx75xx_sdmmc.h --- .../src/stm32f7/chip/stm32f74xx75xx_sdmmc.h | 268 ------------------ 1 file changed, 268 deletions(-) delete mode 100644 arch/arm/src/stm32f7/chip/stm32f74xx75xx_sdmmc.h diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_sdmmc.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_sdmmc.h deleted file mode 100644 index 117c4da2fa..0000000000 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_sdmmc.h +++ /dev/null @@ -1,268 +0,0 @@ -/************************************************************************************ - * arch/arm/src/stm32f7/chip/stm32_sdmmc.h - * - * Copyright (C) 2009, 2011-2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SDMMC_H -#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SDMMC_H - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register Offsets *****************************************************************/ - -#define STM32_SDMMC1_POWER_OFFSET 0x0000 /* SDIO power control register */ -#define STM32_SDMMC1_CLKCR_OFFSET 0x0004 /* SDI clock control register */ -#define STM32_SDMMC1_ARG_OFFSET 0x0008 /* SDIO argument register */ -#define STM32_SDMMC1_CMD_OFFSET 0x000c /* SDIO command register */ -#define STM32_SDMMC1_RESPCMD_OFFSET 0x0010 /* SDIO command response register */ -#define STM32_SDMMC1_RESP_OFFSET(n) (0x0010+4*(n)) -#define STM32_SDMMC1_RESP1_OFFSET 0x0014 /* SDIO response 1 register */ -#define STM32_SDMMC1_RESP2_OFFSET 0x0018 /* SDIO response 2 register */ -#define STM32_SDMMC1_RESP3_OFFSET 0x001c /* SDIO response 3 register */ -#define STM32_SDMMC1_RESP4_OFFSET 0x0020 /* SDIO response 4 register */ -#define STM32_SDMMC1_DTIMER_OFFSET 0x0024 /* SDIO data timer register */ -#define STM32_SDMMC1_DLEN_OFFSET 0x0028 /* SDIO data length register */ -#define STM32_SDMMC1_DCTRL_OFFSET 0x002c /* SDIO data control register */ -#define STM32_SDMMC1_DCOUNT_OFFSET 0x0030 /* SDIO data counter register */ -#define STM32_SDMMC1_STA_OFFSET 0x0034 /* SDIO status register */ -#define STM32_SDMMC1_ICR_OFFSET 0x0038 /* SDIO interrupt clear register */ -#define STM32_SDMMC1_MASK_OFFSET 0x003c /* SDIO mask register */ -#define STM32_SDMMC1_FIFOCNT_OFFSET 0x0048 /* SDIO FIFO counter register */ -#define STM32_SDMMC1_FIFO_OFFSET 0x0080 /* SDIO data FIFO register */ - -/* Register Addresses ***************************************************************/ - -#define STM32_SDMMC1_POWER (STM32_SDMMC1_BASE+STM32_SDMMC1_POWER_OFFSET) -#define STM32_SDMMC1_CLKCR (STM32_SDMMC1_BASE+STM32_SDMMC1_CLKCR_OFFSET) -#define STM32_SDMMC1_ARG (STM32_SDMMC1_BASE+STM32_SDMMC1_ARG_OFFSET) -#define STM32_SDMMC1_CMD (STM32_SDMMC1_BASE+STM32_SDMMC1_CMD_OFFSET) -#define STM32_SDMMC1_RESPCMD (STM32_SDMMC1_BASE+STM32_SDMMC1_RESPCMD_OFFSET) -#define STM32_SDMMC1_RESP(n) (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP_OFFSET(n)) -#define STM32_SDMMC1_RESP1 (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP1_OFFSET) -#define STM32_SDMMC1_RESP2 (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP2_OFFSET) -#define STM32_SDMMC1_RESP3 (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP3_OFFSET) -#define STM32_SDMMC1_RESP4 (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP4_OFFSET) -#define STM32_SDMMC1_DTIMER (STM32_SDMMC1_BASE+STM32_SDMMC1_DTIMER_OFFSET) -#define STM32_SDMMC1_DLEN (STM32_SDMMC1_BASE+STM32_SDMMC1_DLEN_OFFSET) -#define STM32_SDMMC1_DCTRL (STM32_SDMMC1_BASE+STM32_SDMMC1_DCTRL_OFFSET) -#define STM32_SDMMC1_DCOUNT (STM32_SDMMC1_BASE+STM32_SDMMC1_DCOUNT_OFFSET) -#define STM32_SDMMC1_STA (STM32_SDMMC1_BASE+STM32_SDMMC1_STA_OFFSET) -#define STM32_SDMMC1_ICR (STM32_SDMMC1_BASE+STM32_SDMMC1_ICR_OFFSET) -#define STM32_SDMMC1_MASK (STM32_SDMMC1_BASE+STM32_SDMMC1_MASK_OFFSET) -#define STM32_SDMMC1_FIFOCNT (STM32_SDMMC1_BASE+STM32_SDMMC1_FIFOCNT_OFFSET) -#define STM32_SDMMC1_FIFO (STM32_SDMMC1_BASE+STM32_SDMMC1_FIFO_OFFSET) - - -/* Register Bitfield Definitions ****************************************************/ - -#define SDIO_POWER_PWRCTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */ -#define SDIO_POWER_PWRCTRL_MASK (3 << SDIO_POWER_PWRCTRL_SHIFT) -# define SDIO_POWER_PWRCTRL_OFF (0 << SDIO_POWER_PWRCTRL_SHIFT) /* 00: Power-off: card clock stopped */ -# define SDIO_POWER_PWRCTRL_PWRUP (2 << SDIO_POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */ -# define SDIO_POWER_PWRCTRL_ON (3 << SDIO_POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */ - -#define SDIO_POWER_RESET (0) /* Reset value */ - -#define SDIO_CLKCR_CLKDIV_SHIFT (0) /* Bits 7-0: Clock divide factor */ -#define SDIO_CLKCR_CLKDIV_MASK (0xff << SDIO_CLKCR_CLKDIV_SHIFT) -#define SDIO_CLKCR_CLKEN (1 << 8) /* Bit 8: Clock enable bit */ -#define SDIO_CLKCR_PWRSAV (1 << 9) /* Bit 9: Power saving configuration bit */ -#define SDIO_CLKCR_BYPASS (1 << 10) /* Bit 10: Clock divider bypass enable bit */ -#define SDIO_CLKCR_WIDBUS_SHIFT (11) /* Bits 12-11: Wide bus mode enable bits */ -#define SDIO_CLKCR_WIDBUS_MASK (3 << SDIO_CLKCR_WIDBUS_SHIFT) -# define SDIO_CLKCR_WIDBUS_D1 (0 << SDIO_CLKCR_WIDBUS_SHIFT) /* 00: Default (SDIO_D0) */ -# define SDIO_CLKCR_WIDBUS_D4 (1 << SDIO_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (SDIO_D[3:0]) */ -# define SDIO_CLKCR_WIDBUS_D8 (2 << SDIO_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (SDIO_D[7:0]) */ -#define SDIO_CLKCR_NEGEDGE (1 << 13) /* Bit 13: SDIO_CK dephasing selection bit */ -#define SDIO_CLKCR_HWFC_EN (1 << 14) /* Bit 14: HW Flow Control enable */ - -#define SDIO_CLKCR_RESET (0) /* Reset value */ -#define SDIO_ARG_RESET (0) /* Reset value */ - -#define SDIO_CLKCR_CLKEN_BB (STM32_SDMMC1_CLKCR_BB + (8 * 4)) -#define SDIO_CLKCR_PWRSAV_BB (STM32_SDMMC1_CLKCR_BB + (9 * 4)) -#define SDIO_CLKCR_BYPASS_BB (STM32_SDMMC1_CLKCR_BB + (10 * 4)) -#define SDIO_CLKCR_NEGEDGE_BB (STM32_SDMMC1_CLKCR_BB + (13 * 4)) -#define SDIO_CLKCR_HWFC_EN_BB (STM32_SDMMC1_CLKCR_BB + (14 * 4)) - -#define SDIO_CMD_CMDINDEX_SHIFT (0) -#define SDIO_CMD_CMDINDEX_MASK (0x3f << SDIO_CMD_CMDINDEX_SHIFT) -#define SDIO_CMD_WAITRESP_SHIFT (6) /* Bits 7-6: Wait for response bits */ -#define SDIO_CMD_WAITRESP_MASK (3 << SDIO_CMD_WAITRESP_SHIFT) -# define SDIO_CMD_NORESPONSE (0 << SDIO_CMD_WAITRESP_SHIFT) /* 00/10: No response */ -# define SDIO_CMD_SHORTRESPONSE (1 << SDIO_CMD_WAITRESP_SHIFT) /* 01: Short response */ -# define SDIO_CMD_LONGRESPONSE (3 << SDIO_CMD_WAITRESP_SHIFT) /* 11: Long response */ -#define SDIO_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */ -#define SDIO_CMD_WAITPEND (1 << 9) /* Bit 9: CPSM Waits for ends of data transfer */ -#define SDIO_CMD_CPSMEN (1 << 10) /* Bit 10: Command path state machine enable */ -#define SDIO_CMD_SUSPEND (1 << 11) /* Bit 11: SD I/O suspend command */ -#define SDIO_CMD_ENDCMD (1 << 12) /* Bit 12: Enable CMD completion */ -#define SDIO_CMD_NIEN (1 << 13) /* Bit 13: not Interrupt Enable */ -#define SDIO_CMD_ATACMD (1 << 14) /* Bit 14: CE-ATA command */ - -#define SDIO_CMD_RESET (0) /* Reset value */ - -#define SDIO_CMD_WAITINT_BB (STM32_SDMMC1_CMD_BB + (8 * 4)) -#define SDIO_CMD_WAITPEND_BB (STM32_SDMMC1_CMD_BB + (9 * 4)) -#define SDIO_CMD_CPSMEN_BB (STM32_SDMMC1_CMD_BB + (10 * 4)) -#define SDIO_CMD_SUSPEND_BB (STM32_SDMMC1_CMD_BB + (11 * 4)) -#define SDIO_CMD_ENCMD_BB (STM32_SDMMC1_CMD_BB + (12 * 4)) -#define SDIO_CMD_NIEN_BB (STM32_SDMMC1_CMD_BB + (13 * 4)) -#define SDIO_CMD_ATACMD_BB (STM32_SDMMC1_CMD_BB + (14 * 4)) - -#define SDIO_RESPCMD_SHIFT (0) -#define SDIO_RESPCMD_MASK (0x3f << SDIO_RESPCMD_SHIFT) - -#define SDIO_DTIMER_RESET (0) /* Reset value */ - -#define SDIO_DLEN_SHIFT (0) -#define SDIO_DLEN_MASK (0x01ffffff << SDIO_DLEN_SHIFT) - -#define SDIO_DLEN_RESET (0) /* Reset value */ - -#define SDIO_DCTRL_DTEN (1 << 0) /* Bit 0: Data transfer enabled bit */ -#define SDIO_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */ -#define SDIO_DCTRL_DTMODE (1 << 2) /* Bit 2: Data transfer mode */ -#define SDIO_DCTRL_DMAEN (1 << 3) /* Bit 3: DMA enable bit */ -#define SDIO_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 7-4: Data block size */ -#define SDIO_DCTRL_DBLOCKSIZE_MASK (15 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_1BYTE (0 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_2BYTES (1 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_4BYTES (2 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_8BYTES (3 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_16BYTES (4 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_32BYTES (5 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_64BYTES (6 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_128BYTES (7 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_256BYTES (8 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_512BYTES (9 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_1KBYTE (10 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_2KBYTES (11 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_4KBYTES (12 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_8KBYTES (13 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_16KBYTES (14 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -#define SDIO_DCTRL_RWSTART (1 << 8) /* Bit 8: Read wait start */ -#define SDIO_DCTRL_RWSTOP (1 << 9) /* Bit 9: Read wait stop */ -#define SDIO_DCTRL_RWMOD (1 << 10) /* Bit 10: Read wait mode */ -#define SDIO_DCTRL_SDIOEN (1 << 11) /* Bit 11: SD I/O enable functions */ - -#define SDIO_DCTRL_RESET (0) /* Reset value */ - -#define SDIO_DCTRL_DTEN_BB (STM32_SDMMC1_DCTRL_BB + (0 * 4)) -#define SDIO_DCTRL_DTDIR_BB (STM32_SDMMC1_DCTRL_BB + (1 * 4)) -#define SDIO_DCTRL_DTMODE_BB (STM32_SDMMC1_DCTRL_BB + (2 * 4)) -#define SDIO_DCTRL_DMAEN_BB (STM32_SDMMC1_DCTRL_BB + (3 * 4)) -#define SDIO_DCTRL_RWSTART_BB (STM32_SDMMC1_DCTRL_BB + (8 * 4)) -#define SDIO_DCTRL_RWSTOP_BB (STM32_SDMMC1_DCTRL_BB + (9 * 4)) -#define SDIO_DCTRL_RWMOD_BB (STM32_SDMMC1_DCTRL_BB + (10 * 4)) -#define SDIO_DCTRL_SDIOEN_BB (STM32_SDMMC1_DCTRL_BB + (11 * 4)) - -#define SDIO_DATACOUNT_SHIFT (0) -#define SDIO_DATACOUNT_MASK (0x01ffffff << SDIO_DATACOUNT_SHIFT) - -#define SDIO_STA_CCRCFAIL (1 << 0) /* Bit 0: Command response CRC fail */ -#define SDIO_STA_DCRCFAIL (1 << 1) /* Bit 1: Data block CRC fail */ -#define SDIO_STA_CTIMEOUT (1 << 2) /* Bit 2: Command response timeout */ -#define SDIO_STA_DTIMEOUT (1 << 3) /* Bit 3: Data timeout */ -#define SDIO_STA_TXUNDERR (1 << 4) /* Bit 4: Transmit FIFO underrun error */ -#define SDIO_STA_RXOVERR (1 << 5) /* Bit 5: Received FIFO overrun error */ -#define SDIO_STA_CMDREND (1 << 6) /* Bit 6: Command response received */ -#define SDIO_STA_CMDSENT (1 << 7) /* Bit 7: Command sent */ -#define SDIO_STA_DATAEND (1 << 8) /* Bit 8: Data end */ -#define SDIO_STA_STBITERR (1 << 9) /* Bit 9: Start bit not detected */ -#define SDIO_STA_DBCKEND (1 << 10) /* Bit 10: Data block sent/received */ -#define SDIO_STA_CMDACT (1 << 11) /* Bit 11: Command transfer in progress */ -#define SDIO_STA_TXACT (1 << 12) /* Bit 12: Data transmit in progress */ -#define SDIO_STA_RXACT (1 << 13) /* Bit 13: Data receive in progress */ -#define SDIO_STA_TXFIFOHE (1 << 14) /* Bit 14: Transmit FIFO half empty */ -#define SDIO_STA_RXFIFOHF (1 << 15) /* Bit 15: Receive FIFO half full */ -#define SDIO_STA_TXFIFOF (1 << 16) /* Bit 16: Transmit FIFO full */ -#define SDIO_STA_RXFIFOF (1 << 17) /* Bit 17: Receive FIFO full */ -#define SDIO_STA_TXFIFOE (1 << 18) /* Bit 18: Transmit FIFO empty */ -#define SDIO_STA_RXFIFOE (1 << 19) /* Bit 19: Receive FIFO empty */ -#define SDIO_STA_TXDAVL (1 << 20) /* Bit 20: Data available in transmit FIFO */ -#define SDIO_STA_RXDAVL (1 << 21) /* Bit 21: Data available in receive FIFO */ -#define SDIO_STA_SDIOIT (1 << 22) /* Bit 22: SDIO interrupt received */ -#define SDIO_STA_CEATAEND (1 << 23) /* Bit 23: CMD6 CE-ATA command completion */ - -#define SDIO_ICR_CCRCFAILC (1 << 0) /* Bit 0: CCRCFAIL flag clear bit */ -#define SDIO_ICR_DCRCFAILC (1 << 1) /* Bit 1: DCRCFAIL flag clear bit */ -#define SDIO_ICR_CTIMEOUTC (1 << 2) /* Bit 2: CTIMEOUT flag clear bit */ -#define SDIO_ICR_DTIMEOUTC (1 << 3) /* Bit 3: DTIMEOUT flag clear bit */ -#define SDIO_ICR_TXUNDERRC (1 << 4) /* Bit 4: TXUNDERR flag clear bit */ -#define SDIO_ICR_RXOVERRC (1 << 5) /* Bit 5: RXOVERR flag clear bit */ -#define SDIO_ICR_CMDRENDC (1 << 6) /* Bit 6: CMDREND flag clear bit */ -#define SDIO_ICR_CMDSENTC (1 << 7) /* Bit 7: CMDSENT flag clear bit */ -#define SDIO_ICR_DATAENDC (1 << 8) /* Bit 8: DATAEND flag clear bit */ -#define SDIO_ICR_STBITERRC (1 << 9) /* Bit 9: STBITERR flag clear bit */ -#define SDIO_ICR_DBCKENDC (1 << 10) /* Bit 10: DBCKEND flag clear bit */ -#define SDIO_ICR_SDIOITC (1 << 22) /* Bit 22: SDIOIT flag clear bit */ -#define SDIO_ICR_CEATAENDC (1 << 23) /* Bit 23: CEATAEND flag clear bit */ - -#define SDIO_ICR_RESET 0x00c007ff -#define SDIO_ICR_STATICFLAGS 0x000005ff - -#define SDIO_MASK_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */ -#define SDIO_MASK_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */ -#define SDIO_MASK_CTIMEOUTIE (1 << 2) /* Bit 2: Command timeout interrupt enable */ -#define SDIO_MASK_DTIMEOUTIE (1 << 3) /* Bit 3: Data timeout interrupt enable */ -#define SDIO_MASK_TXUNDERRIE (1 << 4) /* Bit 4: Tx FIFO underrun error interrupt enable */ -#define SDIO_MASK_RXOVERRIE (1 << 5) /* Bit 5: Rx FIFO overrun error interrupt enable */ -#define SDIO_MASK_CMDRENDIE (1 << 6) /* Bit 6: Command response received interrupt enable */ -#define SDIO_MASK_CMDSENTIE (1 << 7) /* Bit 7: Command sent interrupt enable */ -#define SDIO_MASK_DATAENDIE (1 << 8) /* Bit 8: Data end interrupt enable */ -#define SDIO_MASK_STBITERRIE (1 << 9) /* Bit 9: Start bit error interrupt enable */ -#define SDIO_MASK_DBCKENDIE (1 << 10) /* Bit 10: Data block end interrupt enable */ -#define SDIO_MASK_CMDACTIE (1 << 11) /* Bit 11: Command acting interrupt enable */ -#define SDIO_MASK_TXACTIE (1 << 12) /* Bit 12: Data transmit acting interrupt enable */ -#define SDIO_MASK_RXACTIE (1 << 13) /* Bit 13: Data receive acting interrupt enable */ -#define SDIO_MASK_TXFIFOHEIE (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */ -#define SDIO_MASK_RXFIFOHFIE (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */ -#define SDIO_MASK_TXFIFOFIE (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */ -#define SDIO_MASK_RXFIFOFIE (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */ -#define SDIO_MASK_TXFIFOEIE (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */ -#define SDIO_MASK_RXFIFOEIE (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */ -#define SDIO_MASK_TXDAVLIE (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */ -#define SDIO_MASK_RXDAVLIE (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */ -#define SDIO_MASK_SDIOITIE (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */ -#define SDIO_MASK_CEATAENDIE (1 << 23) /* Bit 23: CE-ATA command completion interrupt enable */ - -#define SDIO_MASK_RESET (0) - -#define SDIO_FIFOCNT_SHIFT (0) -#define SDIO_FIFOCNT_MASK (0x01ffffff << SDIO_FIFOCNT_SHIFT) - -#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SDMMC_H */ - -- GitLab From fe2b75579115818be2093cc7608626e6003303df Mon Sep 17 00:00:00 2001 From: Ramtin Amin Date: Mon, 7 Nov 2016 06:54:57 -0600 Subject: [PATCH 373/734] LM32: Correct some assembly language interrupt handling issues. Now the basic port seems functional. --- arch/misoc/src/lm32/lm32_vectors.S | 59 +++++++++++++++++++++++------- 1 file changed, 46 insertions(+), 13 deletions(-) diff --git a/arch/misoc/src/lm32/lm32_vectors.S b/arch/misoc/src/lm32/lm32_vectors.S index dc62cfe25e..a71cf63b98 100644 --- a/arch/misoc/src/lm32/lm32_vectors.S +++ b/arch/misoc/src/lm32/lm32_vectors.S @@ -38,13 +38,43 @@ * Included Files ****************************************************************************/ +#include #include +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Linker memory organization ***********************************************/ +/* Data memory is organized as follows: + * + * 1) Initialized data (.data): + * Start: _sdata + * End(+1): _edata + * 2) Uninitialized data (.bss): + * Start: _sbss + * End(+1): _ebss + * + * The following are placed outside of the "normal" memory segments -- mostly + * so that they do not have to be cleared on power up. + * + * 3) Idle thread stack: + * Start: _ebss + * End(+1): _ebss+CONFIG_IDLETHREAD_STACKSIZE + * 4) Heap: + * Start: _ebss+CONFIG_IDLETHREAD_STACKSIZE + * End(+1): to the end of memory + */ + +#define LM32_STACK_BASE _ebss +#define LM32_STACK_TOP _ebss+CONFIG_IDLETHREAD_STACKSIZE +#define LM32_HEAP_BASE LM32_STACK_TOP + /**************************************************************************** * Exception handlers - Must be 32 bytes long. ****************************************************************************/ .section .text, "ax", @progbits + .global g_idle_topstack .global __start __start: @@ -131,24 +161,24 @@ _syscall_handler: _do_reset: /* Setup stack and global pointer */ - mvhi sp, hi(_fstack) - ori sp, sp, lo(_fstack) + mvhi sp, hi(LM32_STACK_TOP) + ori sp, sp, lo(LM32_STACK_TOP) /* Clear BSS */ - mvhi r1, hi(_sbss) - ori r1, r1, lo(_sbss) - mvhi r3, hi(_ebss) - ori r3, r3, lo(_ebss) + mvhi r1, hi(_sbss) + ori r1, r1, lo(_sbss) + mvhi r3, hi(_ebss) + ori r3, r3, lo(_ebss) .clearBSS: - be r1, r3, .callMain + be r1, r3, .callMain sw (r1+0), r0 addi r1, r1, 4 - bi .clearBSS + bi .clearBSS .callMain: - bi os_start + bi os_start .save_all: addi sp, sp, -136 @@ -181,7 +211,11 @@ _do_reset: sw (sp+REG_GP), r26 sw (sp+REG_FP), r27 - sw (sp+REG_SP), r28 + + /* Save SP before we add 136 */ + + addi r1, sp, 136 + sw (sp+REG_SP), r1 /* reg RA done later */ @@ -239,7 +273,7 @@ _do_reset: lw r1, (r1+REG_INT_CTX) wcsr IE, r1 lw r1, (r1+REG_X1) - addi sp, sp, 136 + eret /* This global variable is unsigned long g_idle_topstack and is @@ -249,10 +283,9 @@ _do_reset: .data .align 4 - .globl g_idle_topstack .type g_idle_topstack, object g_idle_topstack: - .long _ebss+CONFIG_IDLETHREAD_STACKSIZE + .long _LM32_STACK_TOP .size g_idle_topstack, .-g_idle_topstack .end -- GitLab From 155f863ca16f9ca8f5d89dda084be7872f2c271a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 7 Nov 2016 07:04:44 -0600 Subject: [PATCH 374/734] Update README --- configs/misoc/README.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/misoc/README.txt b/configs/misoc/README.txt index b75eaad7e8..285b6a4724 100644 --- a/configs/misoc/README.txt +++ b/configs/misoc/README.txt @@ -1,6 +1,9 @@ Misoc README ============ + This README applies to a port to NuttX running on a Qemu LM32 system. You + can find the Qemu setup at https://bitbucket.org/key2/qemu + Buildroot Toolchain =================== -- GitLab From 86ef659ee56f53a49aece6b8fba2f9655e682e05 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 7 Nov 2016 07:16:53 -0600 Subject: [PATCH 375/734] LM32: Fix a typo in my many patching; eliminate some warnings --- arch/misoc/src/common/misoc_serial.c | 7 ------- arch/misoc/src/lm32/lm32_vectors.S | 2 +- 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/arch/misoc/src/common/misoc_serial.c b/arch/misoc/src/common/misoc_serial.c index c46e83775a..9b15ba8e12 100644 --- a/arch/misoc/src/common/misoc_serial.c +++ b/arch/misoc/src/common/misoc_serial.c @@ -147,9 +147,6 @@ struct misoc_dev_s /* Low-level helpers */ -static inline uint32_t misoc_serialin(struct misoc_dev_s *priv, int offset); -static inline void misoc_serialout(struct misoc_dev_s *priv, int offset, - uint32_t value); static void misoc_restoreuartint(struct uart_dev_s *dev, uint8_t im); static void misoc_disableuartint(struct uart_dev_s *dev, uint8_t *im); @@ -261,8 +258,6 @@ static void misoc_restoreuartint(struct uart_dev_s *dev, uint8_t im) static void misoc_disableuartint(struct uart_dev_s *dev, uint8_t *im) { - struct misoc_dev_s *priv = (struct misoc_dev_s *)dev->priv; - if (im) { *im = uart_ev_enable_read(); @@ -371,7 +366,6 @@ static int misoc_uart_interrupt(int irq, void *context) { uint32_t stat; struct uart_dev_s *dev = NULL; - int i; dev = &g_uart1port; @@ -504,7 +498,6 @@ static void misoc_send(struct uart_dev_s *dev, int ch) static void misoc_txint(struct uart_dev_s *dev, bool enable) { uint8_t im; - int i; im = uart_ev_enable_read(); if (enable) diff --git a/arch/misoc/src/lm32/lm32_vectors.S b/arch/misoc/src/lm32/lm32_vectors.S index a71cf63b98..95cfd26001 100644 --- a/arch/misoc/src/lm32/lm32_vectors.S +++ b/arch/misoc/src/lm32/lm32_vectors.S @@ -286,6 +286,6 @@ _do_reset: .type g_idle_topstack, object g_idle_topstack: - .long _LM32_STACK_TOP + .long LM32_STACK_TOP .size g_idle_topstack, .-g_idle_topstack .end -- GitLab From 424ffc76dc6706a9222996222e24ebd229658b93 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 7 Nov 2016 07:31:15 -0600 Subject: [PATCH 376/734] LM32: Add missing _exit() logic (untested) --- arch/misoc/include/syscall.h | 37 +------------ arch/misoc/src/lm32/lm32_exit.c | 98 ++++++++++++++++++++++++++++++++- 2 files changed, 98 insertions(+), 37 deletions(-) diff --git a/arch/misoc/include/syscall.h b/arch/misoc/include/syscall.h index 71b9e85a6c..709ac8fa07 100644 --- a/arch/misoc/include/syscall.h +++ b/arch/misoc/include/syscall.h @@ -46,43 +46,8 @@ /* Include LM32 architecture-specific syscall macros */ -#ifdef CONFIG_ARCH_MISOC +#ifdef CONFIG_ARCH_CHIP_LM32 # include #endif -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Inline functions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - #endif /* __ARCH_MISOC_INCLUDE_SYSCALL_H */ diff --git a/arch/misoc/src/lm32/lm32_exit.c b/arch/misoc/src/lm32/lm32_exit.c index 688f085426..a5f0cd3743 100644 --- a/arch/misoc/src/lm32/lm32_exit.c +++ b/arch/misoc/src/lm32/lm32_exit.c @@ -48,6 +48,8 @@ # include #endif +#include + #include "task/task.h" #include "sched/sched.h" #include "group/group.h" @@ -61,6 +63,63 @@ * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: _up_dumponexit + * + * Description: + * Dump the state of all tasks whenever on task exits. This is debug + * instrumentation that was added to check file-related reference counting + * but could be useful again sometime in the future. + * + ****************************************************************************/ + +#ifdef CONFIG_DUMP_ON_EXIT +static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) +{ +#if CONFIG_NFILE_DESCRIPTORS > 0 + FAR struct filelist *filelist; +#if CONFIG_NFILE_STREAMS > 0 + FAR struct streamlist *streamlist; +#endif + int i; +#endif + + sinfo(" TCB=%p name=%s pid=%d\n", tcb, tcb->argv[0], tcb->pid); + sinfo(" priority=%d state=%d\n", tcb->sched_priority, tcb->task_state); + +#if CONFIG_NFILE_DESCRIPTORS > 0 + filelist = tcb->group->tg_filelist; + for (i = 0; i < CONFIG_NFILE_DESCRIPTORS; i++) + { + struct inode *inode = filelist->fl_files[i].f_inode; + if (inode) + { + sinfo(" fd=%d refcount=%d\n", + i, inode->i_crefssinfo); + } + } +#endif + +#if CONFIG_NFILE_STREAMS > 0 + streamlist = tcb->group->tg_streamlist; + for (i = 0; i < CONFIG_NFILE_STREAMS; i++) + { + struct file_struct *filep = &streamlist->sl_streams[i]; + if (filep->fs_fd >= 0) + { +#if CONFIG_STDIO_BUFFER_SIZE > 0 + sinfo(" fd=%d nbytes=%d\n", + filep->fs_fd, + filep->fs_bufpos - filep->fs_bufstart); +#else + sinfo(" fd=%d\n", filep->fs_fd); +#endif + } + } +#endif +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -78,5 +137,42 @@ void _exit(int status) { -#warning Missing logic + struct tcb_s *tcb; + + /* Disable interrupts. They will be restored when the next + * task is started. + */ + + (void)up_irq_save(); + + sinfo("TCB=%p exiting\n", this_task()); + +#ifdef CONFIG_DUMP_ON_EXIT + sinfo("Other tasks:\n"); + sched_foreach(_up_dumponexit, NULL); +#endif + + /* Destroy the task at the head of the ready to run list. */ + + (void)task_exit(); + + /* Now, perform the context switch to the new ready-to-run task at the + * head of the list. + */ + + tcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously running + * task is closed down gracefully (data caches dump, MMU flushed) and + * set up the address environment for the new thread at the head of + * the ready-to-run list. + */ + + (void)group_addrenv(tcb); +#endif + + /* Then switch contexts */ + + up_fullcontextrestore(tcb->xcp.regs); } -- GitLab From c0af10125780b4ed0aa72d768f5f4924d3191251 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 7 Nov 2016 08:12:33 -0600 Subject: [PATCH 377/734] Remove Eclipse project garbage --- .cproject | 52 ---------------------------------------------------- .gitignore | 2 -- .project | 26 -------------------------- 3 files changed, 80 deletions(-) delete mode 100644 .cproject delete mode 100644 .project diff --git a/.cproject b/.cproject deleted file mode 100644 index 623b3f8a2a..0000000000 --- a/.cproject +++ /dev/null @@ -1,52 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/.gitignore b/.gitignore index 839c74cb5e..3ec700458d 100644 --- a/.gitignore +++ b/.gitignore @@ -28,5 +28,3 @@ cscope.out /*.hex /pcode /tags -.cproject -.project \ No newline at end of file diff --git a/.project b/.project deleted file mode 100644 index 2fa85124b0..0000000000 --- a/.project +++ /dev/null @@ -1,26 +0,0 @@ - - - nuttx - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - -- GitLab From ac6581acecac998e673e67891754cb836a165994 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 7 Nov 2016 08:28:39 -0600 Subject: [PATCH 378/734] Changes from review of last PR --- arch/arm/src/stm32f7/stm32_otgdev.c | 1 - configs/stm32f746-ws/include/board.h | 20 ++-- configs/stm32f746-ws/nsh/defconfig | 111 ++++++------------ .../stm32f746-ws/src/stm32_appinitialize.c | 6 +- configs/stm32f746-ws/src/stm32_sdmmc.c | 2 +- configs/stm32f746-ws/src/stm32_usb.c | 3 +- configs/stm32f746-ws/src/stm32f746-ws.h | 60 +++++----- 7 files changed, 83 insertions(+), 120 deletions(-) diff --git a/arch/arm/src/stm32f7/stm32_otgdev.c b/arch/arm/src/stm32f7/stm32_otgdev.c index 59a0db983d..9bf818182b 100644 --- a/arch/arm/src/stm32f7/stm32_otgdev.c +++ b/arch/arm/src/stm32f7/stm32_otgdev.c @@ -4234,7 +4234,6 @@ static void stm32_epin_disable(FAR struct stm32_ep_s *privep) regval |= OTG_DIEPINT_EPDISD; stm32_putreg(regval, regaddr); - /* Flush any data remaining in the TxFIFO */ stm32_txfifo_flush(OTG_GRSTCTL_TXFNUM_D(privep->epphy)); diff --git a/configs/stm32f746-ws/include/board.h b/configs/stm32f746-ws/include/board.h index 65a27fc6b7..b58542d120 100644 --- a/configs/stm32f746-ws/include/board.h +++ b/configs/stm32f746-ws/include/board.h @@ -124,7 +124,7 @@ /* Configure factors for PLLSAI clock */ -#define CONFIG_STM32F7_PLLSAI 1 +#define CONFIG_STM32F7_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2) @@ -141,10 +141,9 @@ #define STM32_RCC_DCKCFGR1_DFSDM1SRC 0 #define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0 - - /* Configure factors for PLLI2S clock */ -#define CONFIG_STM32F7_PLLI2S 1 + +#define CONFIG_STM32F7_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) #define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) @@ -170,7 +169,6 @@ #define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ #define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_48MHZ - /* Several prescalers allow the configuration of the two AHB buses, the * high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum * frequency of the two AHB buses is 216 MHz while the maximum frequency of @@ -264,7 +262,7 @@ * DMAMAP_SDMMC1_2 = Channel 4, Stream 6 */ -#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1 +#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1 /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses @@ -274,16 +272,16 @@ * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz */ -#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) /* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz */ #ifdef CONFIG_SDIO_DMA -# define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +# define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) #else -# define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +# define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) #endif /* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz @@ -291,9 +289,9 @@ */ #ifdef CONFIG_SDIO_DMA -# define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +# define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) #else -# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) #endif /************************************************************************************ diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig index 3da3bc4b5f..ae75c897c2 100644 --- a/configs/stm32f746-ws/nsh/defconfig +++ b/configs/stm32f746-ws/nsh/defconfig @@ -53,12 +53,6 @@ CONFIG_ARCH_HAVE_CUSTOMOPT=y CONFIG_DEBUG_NOOPT=y # CONFIG_DEBUG_CUSTOMOPT is not set # CONFIG_DEBUG_FULLOPT is not set -CONFIG_DEBUG_ERROR=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_WARN=y -CONFIG_DEBUG_FS_INFO=y -CONFIG_DEBUG_FS_ERROR=y -CONFIG_DEBUG_FS_WARN=y # # System Type @@ -67,10 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -160,6 +157,7 @@ CONFIG_ARMV7M_HAVE_STACKCHECK=y # CONFIG_ARMV7M_ITMSYSLOG is not set # CONFIG_SERIAL_TERMIOS is not set # CONFIG_USART6_RS485 is not set +# CONFIG_USART6_RXDMA is not set # CONFIG_SERIAL_DISABLE_REORDERING is not set # @@ -263,7 +261,7 @@ CONFIG_STM32F7_HAVE_RNG=y CONFIG_STM32F7_HAVE_SPI5=y CONFIG_STM32F7_HAVE_SPI6=y # CONFIG_STM32F7_HAVE_SDMMC2 is not set -# CONFIG_STM32F7_HAVE_ADC1_DMA is not set +CONFIG_STM32F7_HAVE_ADC1_DMA=y # CONFIG_STM32F7_HAVE_ADC2_DMA is not set # CONFIG_STM32F7_HAVE_ADC3_DMA is not set # CONFIG_STM32F7_HAVE_CAN3 is not set @@ -365,10 +363,18 @@ CONFIG_STM32F7_I2CTIMEOSEC=0 CONFIG_STM32F7_I2CTIMEOMS=500 CONFIG_STM32F7_I2CTIMEOTICKS=500 # CONFIG_STM32F7_I2C_DUTY16_9 is not set + +# +# SDMMC1 Configuration +# +CONFIG_SDMMC1_DMA=y +CONFIG_SDMMC1_DMAPRIO=0x00010000 +# CONFIG_SDMMC1_WIDTH_D1_ONLY is not set # CONFIG_STM32F7_HAVE_RTC_COUNTER is not set # CONFIG_STM32F7_HAVE_RTC_SUBSECONDS is not set # CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set # CONFIG_STM32F7_DTCMEXCLUDE is not set +CONFIG_STM32F7_DMACAPABLE=y # # Timer Configuration @@ -377,6 +383,7 @@ CONFIG_STM32F7_I2CTIMEOTICKS=500 # # ADC Configuration # +# CONFIG_STM32F7_ADC1_DMA is not set # # Architecture Options @@ -446,8 +453,6 @@ CONFIG_ARCH_BOARD="stm32f746-ws" # # Common Board Options # -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 # # Board-Specific Options @@ -460,7 +465,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set -CONFIG_BOARDCTL_USBDEVCTRL=y # # RTOS Features @@ -586,17 +590,6 @@ CONFIG_DEV_NULL=y # CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set -CONFIG_MMCSD=y -CONFIG_MMCSD_NSLOTS=1 -# CONFIG_MMCSD_READONLY is not set -CONFIG_MMCSD_MULTIBLOCK_DISABLE=y -# CONFIG_MMCSD_MMCSUPPORT is not set -CONFIG_MMCSD_HAVECARDDETECT=y -# CONFIG_MMCSD_SPI is not set -CONFIG_ARCH_HAVE_SDIO=y -CONFIG_ARCH_HAVE_SDIOWAIT_WRCOMPLETE=y -CONFIG_MMCSD_SDIO=y - # # Buffering # @@ -615,26 +608,25 @@ CONFIG_I2C_RESET=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set # CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set -CONFIG_SDIO_DMA=y - # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set CONFIG_WATCHDOG=y CONFIG_WATCHDOG_DEVPATH="/dev/watchdog0" @@ -670,6 +662,9 @@ CONFIG_ADC_FIFOSIZE=8 # CONFIG_PCA9635PW is not set # CONFIG_NCP5623C is not set # CONFIG_MMCSD is not set +CONFIG_ARCH_HAVE_SDIO=y +CONFIG_ARCH_HAVE_SDIOWAIT_WRCOMPLETE=y +CONFIG_SDIO_PREFLIGHT=y # CONFIG_MODEM is not set # CONFIG_MTD is not set # CONFIG_EEPROM is not set @@ -731,54 +726,12 @@ CONFIG_USART6_2STOP=0 # CONFIG_USART6_IFLOWCONTROL is not set # CONFIG_USART6_OFLOWCONTROL is not set # CONFIG_USART6_DMA is not set -CONFIG_USBDEV=y -# CONFIG_USBHOST is not set -# CONFIG_DRIVERS_WIRELESS is not set - - -# -# USB Device Controller Driver Options -# -# CONFIG_USBDEV_ISOCHRONOUS is not set -# CONFIG_USBDEV_DUALSPEED is not set -CONFIG_USBDEV_SELFPOWERED=y -# CONFIG_USBDEV_BUSPOWERED is not set -CONFIG_USBDEV_MAXPOWER=100 -# CONFIG_USBDEV_DMA is not set -# CONFIG_ARCH_USBDEV_STALLQUEUE is not set -# CONFIG_USBDEV_TRACE is not set - -# -# USB Device Class Driver Options -# -# CONFIG_USBDEV_COMPOSITE is not set -# CONFIG_PL2303 is not set -CONFIG_CDCACM=y -CONFIG_CDCACM_EP0MAXPACKET=64 -CONFIG_CDCACM_EPINTIN=1 -CONFIG_CDCACM_EPINTIN_FSSIZE=64 -CONFIG_CDCACM_EPINTIN_HSSIZE=64 -CONFIG_CDCACM_EPBULKOUT=2 -CONFIG_CDCACM_EPBULKOUT_FSSIZE=64 -CONFIG_CDCACM_EPBULKOUT_HSSIZE=512 -CONFIG_CDCACM_EPBULKIN=2 -CONFIG_CDCACM_EPBULKIN_FSSIZE=64 -CONFIG_CDCACM_EPBULKIN_HSSIZE=512 -CONFIG_CDCACM_NRDREQS=4 -CONFIG_CDCACM_NWRREQS=4 -CONFIG_CDCACM_BULKIN_REQLEN=96 -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_CDCACM_VENDORID=0x03EB -CONFIG_CDCACM_PRODUCTID=0x2044 -CONFIG_CDCACM_VENDORSTR="NuttX" -CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial" -# CONFIG_USBMSC is not set # CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -827,7 +780,10 @@ CONFIG_FS_FAT=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FAT_MAXFNAME=32 +# CONFIG_FS_FATTIME is not set +# CONFIG_FAT_FORCE_INDIRECT is not set CONFIG_FAT_DMAMEMORY=y +CONFIG_FAT_DIRECT_RETRY=y # CONFIG_FS_NXFFS is not set # CONFIG_FS_ROMFS is not set # CONFIG_FS_TMPFS is not set @@ -887,6 +843,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -898,6 +856,8 @@ CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 CONFIG_LIBC_STRERROR=y # CONFIG_LIBC_STRERROR_SHORT is not set # CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_LIBC_TMPDIR="/tmp" +CONFIG_LIBC_MAX_TMPFILE=32 CONFIG_ARCH_LOWPUTC=y # CONFIG_LIBC_LOCALTIME is not set # CONFIG_TIME_EXTENDED is not set @@ -907,6 +867,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 CONFIG_ARCH_HAVE_TLS=y # CONFIG_TLS is not set # CONFIG_LIBC_NETDB is not set +# CONFIG_NETDB_HOSTFILE is not set # # Non-standard Library Support @@ -946,12 +907,14 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # Examples # # CONFIG_EXAMPLES_ADC is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FSTEST is not set # CONFIG_EXAMPLES_FTPC is not set # CONFIG_EXAMPLES_FTPD is not set # CONFIG_EXAMPLES_HELLO is not set @@ -1004,6 +967,7 @@ CONFIG_EXAMPLES_NSH=y # File System Utilities # # CONFIG_FSUTILS_INIFILE is not set +# CONFIG_FSUTILS_PASSWD is not set # # GPS Utilities @@ -1019,8 +983,10 @@ CONFIG_EXAMPLES_NSH=y # # Interpreters # +# CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1087,12 +1053,14 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_LS is not set # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFATFS is not set # CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PSSTACKUSAGE is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1170,9 +1138,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_STACKMONITOR is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set - -CONFIG_SYSTEM_CDCACM=y -CONFIG_SYSTEM_CDCACM_DEVMINOR=0 diff --git a/configs/stm32f746-ws/src/stm32_appinitialize.c b/configs/stm32f746-ws/src/stm32_appinitialize.c index 0a58e61e36..8079b43f69 100644 --- a/configs/stm32f746-ws/src/stm32_appinitialize.c +++ b/configs/stm32f746-ws/src/stm32_appinitialize.c @@ -108,9 +108,9 @@ int board_app_initialize(void) ret = stm32_sdio_initialize(); if (ret != OK) { - ferr("ERROR: Failed to initialize MMC/SD driver: %d\n", ret); - return ret; - } + ferr("ERROR: Failed to initialize MMC/SD driver: %d\n", ret); + return ret; + } #endif return OK; diff --git a/configs/stm32f746-ws/src/stm32_sdmmc.c b/configs/stm32f746-ws/src/stm32_sdmmc.c index 4169d511a2..9dfaaa34a7 100644 --- a/configs/stm32f746-ws/src/stm32_sdmmc.c +++ b/configs/stm32f746-ws/src/stm32_sdmmc.c @@ -1,7 +1,7 @@ /**************************************************************************** * config/stm32f746-ws/src/stm32_sdmmc.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without diff --git a/configs/stm32f746-ws/src/stm32_usb.c b/configs/stm32f746-ws/src/stm32_usb.c index d0c118af89..770f950fa0 100644 --- a/configs/stm32f746-ws/src/stm32_usb.c +++ b/configs/stm32f746-ws/src/stm32_usb.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/stm32f4discovery/src/stm32_usb.c * - * Copyright (C) 2012-2013, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -152,7 +152,6 @@ void stm32_usbinitialize(void) stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); #endif - #endif } diff --git a/configs/stm32f746-ws/src/stm32f746-ws.h b/configs/stm32f746-ws/src/stm32f746-ws.h index 0a61a7b162..681ceb3068 100644 --- a/configs/stm32f746-ws/src/stm32f746-ws.h +++ b/configs/stm32f746-ws/src/stm32f746-ws.h @@ -82,11 +82,11 @@ #define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | GPIO_PIN13) -#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|\ - GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9) +#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|\ + GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9) -#define SDIO_SLOTNO 0 -#define SDIO_MINOR 0 +#define SDIO_SLOTNO 0 +#define SDIO_MINOR 0 /**************************************************************************************************** * Public data @@ -108,32 +108,32 @@ void weak_function stm32_spidev_initialize(void); - /**************************************************************************** - * Name: stm32_sdio_initialize - * - * Description: - * Initialize SDIO-based MMC/SD card support - * - ****************************************************************************/ - - #if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32F7_SDMMC1) - int stm32_sdio_initialize(void); - #endif - - /************************************************************************************ - * Name: stm32_dma_alloc_init - * - * Description: - * Called to create a FAT DMA allocator - * - * Returned Value: - * 0 on success or -ENOMEM - * - ************************************************************************************/ - - #if defined (CONFIG_FAT_DMAMEMORY) - int stm32_dma_alloc_init(void); - #endif +/**************************************************************************** + * Name: stm32_sdio_initialize + * + * Description: + * Initialize SDIO-based MMC/SD card support + * + ****************************************************************************/ + +#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32F7_SDMMC1) +int stm32_sdio_initialize(void); +#endif + +/************************************************************************************ + * Name: stm32_dma_alloc_init + * + * Description: + * Called to create a FAT DMA allocator + * + * Returned Value: + * 0 on success or -ENOMEM + * + ************************************************************************************/ + +#if defined (CONFIG_FAT_DMAMEMORY) +int stm32_dma_alloc_init(void); +#endif #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_STM32F746_WS_SRC_STM32F746_WS_H */ -- GitLab From dd04d73afebb7de0cc965fadf05f4a94dfae80f4 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 7 Nov 2016 09:16:34 -0600 Subject: [PATCH 379/734] STM32F7 SD/MMC driver depends on CONFIG_SDIO_DMA which is only defined in stm32/Kconfig. Changed to CONFIG_STM32F7_SDMMC_DMA and defined in stm32f7/Kconfig. --- arch/arm/src/stm32f7/Kconfig | 20 +++++++- arch/arm/src/stm32f7/stm32_sdmmc.c | 76 +++++++++++++++--------------- configs/stm32f746-ws/nsh/defconfig | 63 +++++++++++++++++++++++-- 3 files changed, 116 insertions(+), 43 deletions(-) diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index 75dd21454b..c909a1d980 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -992,6 +992,10 @@ config STM32F7_SAI bool default n +config STM32F7_SDMMC + bool + default n + config STM32F7_SPI bool default n @@ -1006,7 +1010,6 @@ config STM32F7_USART # These are the peripheral selections proper - config STM32F7_ADC1 bool "ADC1" default n @@ -1218,6 +1221,7 @@ config STM32F7_SAI2 config STM32F7_SDMMC1 bool "SDMMC1" default n + select STM32F7_SDMMC select ARCH_HAVE_SDIO select ARCH_HAVE_SDIOWAIT_WRCOMPLETE select SDIO_PREFLIGHT @@ -1226,6 +1230,7 @@ config STM32F7_SDMMC2 bool "SDMMC2" default n depends on STM32F7_HAVE_SDMMC2 + select STM32F7_SDMMC select ARCH_HAVE_SDIO select ARCH_HAVE_SDIOWAIT_WRCOMPLETE select SDIO_PREFLIGHT @@ -1718,9 +1723,12 @@ config STM32F7_I2C_DUTY16_9 endmenu # "I2C Configuration" +menu "SD/MMC Configuration" + depends on STM32F7_SDMMC + config STM32F7_SDMMC_XFRDEBUG bool "SDMMC transfer debug" - depends on DEBUG_FS_INFO && (STM32F7_SDMMC1 || STM32F7_SDMMC2) + depends on DEBUG_FS_INFO default n ---help--- Enable special debug instrumentation analyze SDMMC data transfers. @@ -1730,6 +1738,13 @@ config STM32F7_SDMMC_XFRDEBUG enabled, then DMA register will be collected as well. Requires also DEBUG_FS and CONFIG_DEBUG_INFO. +config STM32F7_SDMMC_DMA + bool "Support DMA data transfers" + default n + depends on STM32F7_DMA + ---help--- + Support DMA data transfers. + menu "SDMMC1 Configuration" depends on STM32F7_SDMMC1 @@ -1797,6 +1812,7 @@ config SDMMC2_WIDTH_D1_ONLY Select 1-bit transfer mode. Default: 4-bit transfer mode. endmenu # "SDMMC2 Configuration" +endmenu # "SD/MMC Configuration" if STM32F7_BKPSRAM diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index 3a639472f3..52e7ef3878 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -87,7 +87,7 @@ * CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking * APIs to manage concurrent accesses on the SDMMC bus. This is not * needed for the simple case of a single SD card, for example. - * CONFIG_SDIO_DMA - Enable SDMMC. This is a marginally optional. For + * CONFIG_STM32F7_SDMMC_DMA - Enable SDMMC. This is a marginally optional. For * most usages, SDMMC will cause data overruns if used without DMA. * NOTE the above system DMA configuration options. * CONFIG_SDMMC_WIDTH_D1_ONLY - This may be selected to force the driver @@ -96,16 +96,16 @@ * CONFIG_SDMMC_PRI - SDMMC interrupt priority. This setting is not very * important since interrupt nesting is not currently supported. * CONFIG_SDMMMC_DMAPRIO - SDMMC DMA priority. This can be selecte if - * CONFIG_SDIO_DMA is enabled. + * CONFIG_STM32F7_SDMMC_DMA is enabled. * CONFIG_CONFIG_STM32F7_SDMMC_XFRDEBUG - Enables some very low-level debug output * This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_INFO */ -#if defined(CONFIG_SDIO_DMA) && !defined(CONFIG_STM32F7_DMA2) -# warning "CONFIG_SDIO_DMA support requires CONFIG_STM32F7_DMA2" +#if defined(CONFIG_STM32F7_SDMMC_DMA) && !defined(CONFIG_STM32F7_DMA2) +# warning "CONFIG_STM32F7_SDMMC_DMA support requires CONFIG_STM32F7_DMA2" #endif -#ifndef CONFIG_SDIO_DMA +#ifndef CONFIG_STM32F7_SDMMC_DMA # warning "Large Non-DMA transfer may result in RX overrun failures" #endif @@ -118,7 +118,7 @@ # define CONFIG_SDMMC1_PRI NVIC_SYSH_PRIORITY_DEFAULT # endif -# ifdef CONFIG_SDIO_DMA +# ifdef CONFIG_STM32F7_SDMMC_DMA # ifndef CONFIG_SDMMC1_DMAPRIO # define CONFIG_SDMMC1_DMAPRIO DMA_SCR_PRIVERYHI # endif @@ -135,7 +135,7 @@ # define CONFIG_SDMMC2_PRI NVIC_SYSH_PRIORITY_DEFAULT # endif -# ifdef CONFIG_SDIO_DMA +# ifdef CONFIG_STM32F7_SDMMC_DMA # ifndef CONFIG_SDMMC2_DMAPRIO # define CONFIG_SDMMC2_DMAPRIO DMA_SCR_PRIVERYHI # endif @@ -307,7 +307,7 @@ /* Register logging support */ #ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG -# ifdef CONFIG_SDIO_DMA +# ifdef CONFIG_STM32F7_SDMMC_DMA # define SAMPLENDX_BEFORE_SETUP 0 # define SAMPLENDX_BEFORE_ENABLE 1 # define SAMPLENDX_AFTER_SETUP 2 @@ -343,7 +343,7 @@ struct stm32_dev_s uint32_t d0_gpio; xcpt_t wrchandler; #endif -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA uint32_t dmapri; #endif @@ -372,7 +372,7 @@ struct stm32_dev_s /* DMA data transfer support */ bool widebus; /* Required for DMA support */ -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA volatile uint8_t xfrflags; /* Used to synchronize SDMMC and DMA completion events */ bool dmamode; /* true: DMA mode transfer */ DMA_HANDLE dma; /* Handle for DMA channel */ @@ -398,7 +398,7 @@ struct stm32_sdioregs_s struct stm32_sampleregs_s { struct stm32_sdioregs_s sdio; -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) struct stm32_dmaregs_s dma; #endif }; @@ -439,7 +439,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv); # define stm32_dumpsamples(priv) #endif -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg); #endif @@ -525,7 +525,7 @@ static int stm32_registercallback(FAR struct sdio_dev_s *dev, /* DMA */ -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA static bool stm32_dmasupported(FAR struct sdio_dev_s *dev); #ifdef CONFIG_SDIO_PREFLIGHT static int stm32_dmapreflight(FAR struct sdio_dev_s *dev, @@ -577,7 +577,7 @@ struct stm32_dev_s g_sdmmcdev1 = .eventwait = stm32_eventwait, .callbackenable = stm32_callbackenable, .registercallback = stm32_registercallback, -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA .dmasupported = stm32_dmasupported, #ifdef CONFIG_SDIO_PREFLIGHT .dmapreflight = stm32_dmapreflight, @@ -633,7 +633,7 @@ struct stm32_dev_s g_sdmmcdev2 = .eventwait = stm32_eventwait, .callbackenable = stm32_callbackenable, .registercallback = stm32_registercallback, -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA .dmasupported = stm32_dmasupported, #ifdef CONFIG_SDIO_PREFLIGHT .dmapreflight = stm32_dmapreflight, @@ -840,7 +840,7 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, priv->waitevents = waitevents; priv->wkupevent = wkupevent; priv->waitmask = waitmask; -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA priv->xfrflags = 0; #endif sdmmc_putreg32(priv, priv->xfrmask | priv->waitmask, STM32_SDMMC_MASK_OFFSET); @@ -975,7 +975,7 @@ static void stm32_sample(struct stm32_dev_s *priv, int index) { struct stm32_sampleregs_s *regs = &g_sampleregs[index]; -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) if (priv->dmamode) { stm32_dmasample(priv->dma, ®s->dma); @@ -1022,7 +1022,7 @@ static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) static void stm32_dumpsample(struct stm32_dev_s *priv, struct stm32_sampleregs_s *regs, const char *msg) { -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) if (priv->dmamode) { stm32_dmadump(priv->dma, ®s->dma, msg); @@ -1046,7 +1046,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], "Before setup"); -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) if (priv->dmamode) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_ENABLE], "Before DMA enable"); @@ -1056,7 +1056,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv) stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_AFTER_SETUP], "After setup"); stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_END_TRANSFER], "End of transfer"); -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_SDIO_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) if (priv->dmamode) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_DMA_CALLBACK], "DMA Callback"); @@ -1073,7 +1073,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)arg; @@ -1434,7 +1434,7 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, /* If this was a DMA transfer, make sure that DMA is stopped */ -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA if (priv->dmamode) { /* DMA debug instrumentation */ @@ -1537,7 +1537,7 @@ static int stm32_sdmmc_interrupt(struct stm32_dev_s *priv) pending = enabled & priv->xfrmask; if (pending != 0) { -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA if (!priv->dmamode) #endif { @@ -1576,7 +1576,7 @@ static int stm32_sdmmc_interrupt(struct stm32_dev_s *priv) /* Was this transfer performed in DMA mode? */ -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA if (priv->dmamode) { /* Yes.. Terminate the transfers only if the DMA has also @@ -1812,7 +1812,7 @@ static void stm32_reset(FAR struct sdio_dev_s *dev) priv->waitevents = 0; /* Set of events to be waited for */ priv->waitmask = 0; /* Interrupt enables for event waiting */ priv->wkupevent = 0; /* The event that caused the wakeup */ -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA priv->xfrflags = 0; /* Used to synchronize SDIO and DMA * completion events */ #endif @@ -1828,7 +1828,7 @@ static void stm32_reset(FAR struct sdio_dev_s *dev) /* DMA data transfer support */ priv->widebus = false; /* Required for DMA support */ -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA priv->dmamode = false; /* true: DMA mode transfer */ #endif @@ -2108,7 +2108,7 @@ static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, priv->buffer = (uint32_t *)buffer; priv->remaining = nbytes; -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA priv->dmamode = false; #endif @@ -2163,7 +2163,7 @@ static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const priv->buffer = (uint32_t *)buffer; priv->remaining = nbytes; -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA priv->dmamode = false; #endif @@ -2217,7 +2217,7 @@ static int stm32_cancel(FAR struct sdio_dev_s *dev) /* If this was a DMA transfer, make sure that DMA is stopped */ -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA if (priv->dmamode) { /* Make sure that the DMA is stopped (it will be stopped automatically @@ -2712,7 +2712,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev, /* Disable event-related interrupts */ stm32_configwaitints(priv, 0, 0, 0); -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA priv->xfrflags = 0; #endif @@ -2808,7 +2808,7 @@ static int stm32_registercallback(FAR struct sdio_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA static bool stm32_dmasupported(FAR struct sdio_dev_s *dev) { return true; @@ -2831,7 +2831,7 @@ static bool stm32_dmasupported(FAR struct sdio_dev_s *dev) * OK on success; a negated errno on failure ****************************************************************************/ -#if defined(CONFIG_SDIO_DMA) && defined(CONFIG_SDIO_PREFLIGHT) +#if defined(CONFIG_STM32F7_SDMMC_DMA) && defined(CONFIG_SDIO_PREFLIGHT) static int stm32_dmapreflight(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, size_t buflen) { @@ -2877,7 +2877,7 @@ static int stm32_dmapreflight(FAR struct sdio_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, size_t buflen) { @@ -2962,7 +2962,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, * ****************************************************************************/ -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, size_t buflen) { @@ -3152,7 +3152,7 @@ static void stm32_default(struct stm32_dev_s *priv) FAR struct sdio_dev_s *sdio_initialize(int slotno) { struct stm32_dev_s *priv = NULL; -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA unsigned int dmachan; #endif @@ -3162,7 +3162,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) /* Select SDMMC 1 */ priv = &g_sdmmcdev1; -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA dmachan = SDMMC1_DMACHAN; #endif @@ -3192,7 +3192,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) /* Select SDMMC 2 */ priv = &g_sdmmcdev2; -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA dmachan = SDMMC2_DMACHAN; #endif @@ -3232,7 +3232,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) /* Allocate a DMA channel */ -#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_STM32F7_SDMMC_DMA priv->dma = stm32_dmachannel(dmachan); DEBUGASSERT(priv->dma); #endif diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig index ae75c897c2..94ab01db9f 100644 --- a/configs/stm32f746-ws/nsh/defconfig +++ b/configs/stm32f746-ws/nsh/defconfig @@ -156,6 +156,8 @@ CONFIG_ARMV7M_HAVE_STACKCHECK=y # CONFIG_ARMV7M_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set # CONFIG_SERIAL_TERMIOS is not set +# CONFIG_SDIO_DMA is not set +# CONFIG_SDIO_WIDTH_D1_ONLY is not set # CONFIG_USART6_RS485 is not set # CONFIG_USART6_RXDMA is not set # CONFIG_SERIAL_DISABLE_REORDERING is not set @@ -460,6 +462,7 @@ CONFIG_ARCH_BOARD="stm32f746-ws" # CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set +CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_PWMTEST is not set @@ -661,10 +664,20 @@ CONFIG_ADC_FIFOSIZE=8 # CONFIG_RGBLED is not set # CONFIG_PCA9635PW is not set # CONFIG_NCP5623C is not set -# CONFIG_MMCSD is not set +CONFIG_MMCSD=y +CONFIG_MMCSD_NSLOTS=1 +# CONFIG_MMCSD_READONLY is not set +CONFIG_MMCSD_MULTIBLOCK_DISABLE=y +# CONFIG_MMCSD_MMCSUPPORT is not set +CONFIG_MMCSD_HAVECARDDETECT=y +# CONFIG_MMCSD_SPI is not set CONFIG_ARCH_HAVE_SDIO=y CONFIG_ARCH_HAVE_SDIOWAIT_WRCOMPLETE=y +CONFIG_MMCSD_SDIO=y CONFIG_SDIO_PREFLIGHT=y +# CONFIG_SDIO_MUXBUS is not set +# CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE is not set +# CONFIG_SDIO_BLOCKSETUP is not set # CONFIG_MODEM is not set # CONFIG_MTD is not set # CONFIG_EEPROM is not set @@ -678,7 +691,7 @@ CONFIG_DEV_FIFO_SIZE=1024 # CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set -# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_REMOVABLE=y CONFIG_SERIAL_CONSOLE=y # CONFIG_16550_UART is not set # CONFIG_UART_SERIALDRIVER is not set @@ -727,7 +740,47 @@ CONFIG_USART6_2STOP=0 # CONFIG_USART6_OFLOWCONTROL is not set # CONFIG_USART6_DMA is not set # CONFIG_PSEUDOTERM is not set -# CONFIG_USBDEV is not set +CONFIG_USBDEV=y + +# +# USB Device Controller Driver Options +# +# CONFIG_USBDEV_ISOCHRONOUS is not set +# CONFIG_USBDEV_DUALSPEED is not set +CONFIG_USBDEV_SELFPOWERED=y +# CONFIG_USBDEV_BUSPOWERED is not set +CONFIG_USBDEV_MAXPOWER=100 +# CONFIG_USBDEV_DMA is not set +# CONFIG_ARCH_USBDEV_STALLQUEUE is not set +# CONFIG_USBDEV_TRACE is not set + +# +# USB Device Class Driver Options +# +# CONFIG_USBDEV_COMPOSITE is not set +# CONFIG_PL2303 is not set +CONFIG_CDCACM=y +# CONFIG_CDCACM_CONSOLE is not set +CONFIG_CDCACM_EP0MAXPACKET=64 +CONFIG_CDCACM_EPINTIN=1 +CONFIG_CDCACM_EPINTIN_FSSIZE=64 +CONFIG_CDCACM_EPINTIN_HSSIZE=512 +CONFIG_CDCACM_EPBULKOUT=3 +CONFIG_CDCACM_EPBULKOUT_FSSIZE=64 +CONFIG_CDCACM_EPBULKOUT_HSSIZE=512 +CONFIG_CDCACM_EPBULKIN=2 +CONFIG_CDCACM_EPBULKIN_FSSIZE=64 +CONFIG_CDCACM_EPBULKIN_HSSIZE=512 +CONFIG_CDCACM_NRDREQS=4 +CONFIG_CDCACM_NWRREQS=4 +CONFIG_CDCACM_BULKIN_REQLEN=96 +CONFIG_CDCACM_RXBUFSIZE=257 +CONFIG_CDCACM_TXBUFSIZE=193 +CONFIG_CDCACM_VENDORID=0x0525 +CONFIG_CDCACM_PRODUCTID=0xa4a7 +CONFIG_CDCACM_VENDORSTR="NuttX" +CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial" +# CONFIG_USBMSC is not set # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set @@ -1079,6 +1132,7 @@ CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 # # Configure Command Options @@ -1100,6 +1154,7 @@ CONFIG_NSH_FILEIOSIZE=512 # Console Configuration # CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_USBCONSOLE is not set # CONFIG_NSH_ALTCONDEV is not set CONFIG_NSH_ARCHINIT=y # CONFIG_NSH_LOGIN is not set @@ -1117,6 +1172,8 @@ CONFIG_NSH_ARCHINIT=y # # System Libraries and NSH Add-Ons # +CONFIG_SYSTEM_CDCACM=y +CONFIG_SYSTEM_CDCACM_DEVMINOR=0 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -- GitLab From 1344d8b466d0e8d0c5eb8833104680a828caadb6 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 7 Nov 2016 09:20:47 -0600 Subject: [PATCH 380/734] STM32F746-WS: A few repairs to the nsh/defconfig for USB support. --- arch/arm/src/stm32f7/Kconfig | 4 ++-- configs/stm32f746-ws/nsh/defconfig | 6 ++++++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index c909a1d980..ced8f62ca3 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -1751,7 +1751,7 @@ menu "SDMMC1 Configuration" config SDMMC1_DMA bool "Support DMA data transfers on SDMMC1" default y if STM32F7_DMA2 - depends on STM32F7_DMA2 + depends on STM32F7_SDMMC_DMA && STM32F7_DMA2 ---help--- Support DMA data transfers on SDMMC1. Requires STM32F7_SDMMC1 and config STM32F7_DMA2. @@ -1785,7 +1785,7 @@ menu "SDMMC2 Configuration" config SDMMC2_DMA bool "Support DMA data transfers on SDMMC2" default y if STM32F7_DMA2 - depends on STM32F7_DMA2 + depends on STM32F7_SDMMC_DMA && STM32F7_DMA2 ---help--- Support DMA data transfers on SDMMC2. Requires STM32F7_SDMMC2 and config STM32F7_DMA2. diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig index 94ab01db9f..4ba7dddad4 100644 --- a/configs/stm32f746-ws/nsh/defconfig +++ b/configs/stm32f746-ws/nsh/defconfig @@ -280,6 +280,7 @@ CONFIG_STM32F7_ADC=y CONFIG_STM32F7_DMA=y CONFIG_STM32F7_I2C=y # CONFIG_STM32F7_SAI is not set +CONFIG_STM32F7_SDMMC=y CONFIG_STM32F7_SPI=y # CONFIG_STM32F7_TIM is not set CONFIG_STM32F7_USART=y @@ -366,6 +367,11 @@ CONFIG_STM32F7_I2CTIMEOMS=500 CONFIG_STM32F7_I2CTIMEOTICKS=500 # CONFIG_STM32F7_I2C_DUTY16_9 is not set +# +# SD/MMC Configuration +# +CONFIG_STM32F7_SDMMC_DMA=y + # # SDMMC1 Configuration # -- GitLab From eb9a8ed79098f328e2fc8ed66be85c10fa773c79 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marc=20Recht=C3=A9?= Date: Mon, 7 Nov 2016 09:35:48 -0600 Subject: [PATCH 381/734] STM37xx PWM: Add PWM driver support for STMF37xx. The changes have been tested successfuly for TIM4 and TIM17 (different IPs). --- arch/arm/src/stm32/chip/stm32_tim.h | 8 +- arch/arm/src/stm32/stm32_pwm.c | 433 ++++++++++++++++++++-------- 2 files changed, 318 insertions(+), 123 deletions(-) diff --git a/arch/arm/src/stm32/chip/stm32_tim.h b/arch/arm/src/stm32/chip/stm32_tim.h index 56c748a98f..f4113cd6dd 100644 --- a/arch/arm/src/stm32/chip/stm32_tim.h +++ b/arch/arm/src/stm32/chip/stm32_tim.h @@ -31,6 +31,10 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * + * This the lower half driver for PWM and the STM32 F1 to F4 family MCUs + * Athough this driver does make the difference between 16/32-bit timers, + * it does manage all of them as 16-bit. This will have to be improved. + * ****************************************************************************************************/ #ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_TIM_H @@ -824,7 +828,9 @@ #define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */ #define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX) +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX) || \ + defined(CONFIG_STM32_STM32L15XX) # define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */ #elif defined(CONFIG_STM32_STM32F30XX) # define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */ diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c index 425f256ba0..83a1a4cd7d 100644 --- a/arch/arm/src/stm32/stm32_pwm.c +++ b/arch/arm/src/stm32/stm32_pwm.c @@ -114,6 +114,159 @@ #define TIMTYPE_TIM16 TIMTYPE_COUNTUP16 #define TIMTYPE_TIM17 TIMTYPE_COUNTUP16 +/* Timer clock source, RCC EN offset, enable bit, + * RCC RST offset, reset bit to use + */ + +#if defined(CONFIG_STM32_STM32F37XX) +# define TIMCLK_TIM2 STM32_APB1_TIM2_CLKIN +# define TIMRCCEN_TIM2 STM32_RCC_APB1ENR +# define TIMEN_TIM2 RCC_APB1ENR_TIM2EN +# define TIMRCCRST_TIM2 STM32_RCC_APB1RSTR +# define TIMRST_TIM2 RCC_APB1RSTR_TIM2RST +# define TIMCLK_TIM3 STM32_APB1_TIM3_CLKIN +# define TIMRCCEN_TIM3 STM32_RCC_APB1ENR +# define TIMEN_TIM3 RCC_APB1ENR_TIM3EN +# define TIMRCCRST_TIM3 STM32_RCC_APB1RSTR +# define TIMRST_TIM3 RCC_APB1RSTR_TIM3RST +# define TIMCLK_TIM4 STM32_APB1_TIM4_CLKIN +# define TIMRCCEN_TIM4 STM32_RCC_APB1ENR +# define TIMEN_TIM4 RCC_APB1ENR_TIM4EN +# define TIMRCCRST_TIM4 STM32_RCC_APB1RSTR +# define TIMRST_TIM4 RCC_APB1RSTR_TIM4RST +# define TIMCLK_TIM5 STM32_APB1_TIM5_CLKIN +# define TIMRCCEN_TIM5 STM32_RCC_APB1ENR +# define TIMEN_TIM5 RCC_APB1ENR_TIM5EN +# define TIMRCCRST_TIM5 STM32_RCC_APB1RSTR +# define TIMRST_TIM5 RCC_APB1RSTR_TIM5RST +# define TIMCLK_TIM6 STM32_APB1_TIM6_CLKIN +# define TIMRCCEN_TIM6 STM32_RCC_APB1ENR +# define TIMEN_TIM6 RCC_APB1ENR_TIM6EN +# define TIMRCCRST_TIM6 STM32_RCC_APB1RSTR +# define TIMRST_TIM6 RCC_APB1RSTR_TIM6RST +# define TIMCLK_TIM7 STM32_APB1_TIM7_CLKIN +# define TIMRCCEN_TIM7 STM32_RCC_APB1ENR +# define TIMEN_TIM7 RCC_APB1ENR_TIM7EN +# define TIMRCCRST_TIM7 STM32_RCC_APB1RSTR +# define TIMRST_TIM7 RCC_APB1RSTR_TIM7RST +# define TIMCLK_TIM12 STM32_APB1_TIM12_CLKIN +# define TIMRCCEN_TIM12 STM32_RCC_APB1ENR +# define TIMEN_TIM12 RCC_APB1ENR_TIM12EN +# define TIMRCCRST_TIM12 STM32_RCC_APB1RSTR +# define TIMRST_TIM12 RCC_APB1RSTR_TIM12RST +# define TIMCLK_TIM13 STM32_APB1_TIM13_CLKIN +# define TIMRCCEN_TIM13 STM32_RCC_APB1ENR +# define TIMEN_TIM13 RCC_APB1ENR_TIM13EN +# define TIMRCCRST_TIM13 STM32_RCC_APB1RSTR +# define TIMRST_TIM13 RCC_APB1RSTR_TIM13RST +# define TIMCLK_TIM14 STM32_APB1_TIM14_CLKIN +# define TIMRCCEN_TIM14 STM32_RCC_APB1ENR +# define TIMEN_TIM14 RCC_APB1ENR_TIM14EN +# define TIMRCCRST_TIM14 STM32_RCC_APB1RSTR +# define TIMRST_TIM14 RCC_APB1RSTR_TIM14RST +# define TIMCLK_TIM15 STM32_APB2_TIM15_CLKIN +# define TIMRCCEN_TIM15 STM32_RCC_APB2ENR +# define TIMEN_TIM15 RCC_APB2ENR_TIM15EN +# define TIMRCCRST_TIM15 STM32_RCC_APB2RSTR +# define TIMRST_TIM15 RCC_APB2RSTR_TIM15RST +# define TIMCLK_TIM16 STM32_APB2_TIM16_CLKIN +# define TIMRCCEN_TIM16 STM32_RCC_APB2ENR +# define TIMEN_TIM16 RCC_APB2ENR_TIM16EN +# define TIMRCCRST_TIM16 STM32_RCC_APB2RSTR +# define TIMRST_TIM16 RCC_APB2RSTR_TIM16RST +# define TIMCLK_TIM17 STM32_APB2_TIM17_CLKIN +# define TIMRCCEN_TIM17 STM32_RCC_APB2ENR +# define TIMEN_TIM17 RCC_APB2ENR_TIM17EN +# define TIMRCCRST_TIM17 STM32_RCC_APB2RSTR +# define TIMRST_TIM17 RCC_APB2RSTR_TIM17RST +# define TIMCLK_TIM18 STM32_APB1_TIM18_CLKIN +# define TIMRCCEN_TIM18 STM32_RCC_APB1ENR +# define TIMEN_TIM18 RCC_APB1ENR_TIM18EN +# define TIMRCCRST_TIM18 STM32_RCC_APB1RSTR +# define TIMRST_TIM18 RCC_APB1RSTR_TIM18RST +# define TIMCLK_TIM19 STM32_APB2_TIM19_CLKIN +# define TIMRCCEN_TIM19 STM32_RCC_APB2ENR +# define TIMEN_TIM19 RCC_APB2ENR_TIM19EN +# define TIMRCCRST_TIM19 STM32_RCC_APB2RSTR +# define TIMRST_TIM19 RCC_APB2RSTR_TIM19RST +#else +# define TIMCLK_TIM1 STM32_APB2_TIM1_CLKIN +# define TIMRCCEN_TIM1 STM32_RCC_APB2ENR +# define TIMEN_TIM1 RCC_APB2ENR_TIM1EN +# define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR +# define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST +# define TIMCLK_TIM2 STM32_APB1_TIM2_CLKIN +# define TIMRCCEN_TIM2 STM32_RCC_APB1ENR +# define TIMEN_TIM2 RCC_APB1ENR_TIM2EN +# define TIMRCCRST_TIM2 STM32_RCC_APB1RSTR +# define TIMRST_TIM2 RCC_APB1RSTR_TIM2RST +# define TIMCLK_TIM3 STM32_APB1_TIM3_CLKIN +# define TIMRCCEN_TIM3 STM32_RCC_APB1ENR +# define TIMEN_TIM3 RCC_APB1ENR_TIM3EN +# define TIMRCCRST_TIM3 STM32_RCC_APB1RSTR +# define TIMRST_TIM3 RCC_APB1RSTR_TIM3RST +# define TIMCLK_TIM4 STM32_APB1_TIM4_CLKIN +# define TIMRCCEN_TIM4 STM32_RCC_APB1ENR +# define TIMEN_TIM4 RCC_APB1ENR_TIM4EN +# define TIMRCCRST_TIM4 STM32_RCC_APB1RSTR +# define TIMRST_TIM4 RCC_APB1RSTR_TIM4RST +# define TIMCLK_TIM5 STM32_APB1_TIM5_CLKIN +# define TIMRCCEN_TIM5 STM32_RCC_APB1ENR +# define TIMEN_TIM5 RCC_APB1ENR_TIM5EN +# define TIMRCCRST_TIM5 STM32_RCC_APB1RSTR +# define TIMRST_TIM5 RCC_APB1RSTR_TIM5RST +# define TIMCLK_TIM8 STM32_APB2_TIM8_CLKIN +# define TIMRCCEN_TIM8 STM32_RCC_APB2ENR +# define TIMEN_TIM8 RCC_APB2ENR_TIM8EN +# define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR +# define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST +# define TIMCLK_TIM9 STM32_APB2_TIM9_CLKIN +# define TIMRCCEN_TIM9 STM32_RCC_APB2ENR +# define TIMEN_TIM9 RCC_APB2ENR_TIM9EN +# define TIMRCCRST_TIM9 STM32_RCC_APB2RSTR +# define TIMRST_TIM9 RCC_APB2RSTR_TIM9RST +# define TIMCLK_TIM10 STM32_APB2_TIM10_CLKIN +# define TIMRCCEN_TIM10 STM32_RCC_APB2ENR +# define TIMEN_TIM10 RCC_APB2ENR_TIM10EN +# define TIMRCCRST_TIM10 STM32_RCC_APB2RSTR +# define TIMRST_TIM10 RCC_APB2RSTR_TIM10RST +# define TIMCLK_TIM11 STM32_APB2_TIM11_CLKIN +# define TIMRCCEN_TIM11 STM32_RCC_APB2ENR +# define TIMEN_TIM11 RCC_APB2ENR_TIM11EN +# define TIMRCCRST_TIM11 STM32_RCC_APB2RSTR +# define TIMRST_TIM11 RCC_APB2RSTR_TIM11RST +# define TIMCLK_TIM12 STM32_APB1_TIM12_CLKIN +# define TIMRCCEN_TIM12 STM32_RCC_APB1ENR +# define TIMEN_TIM12 RCC_APB1ENR_TIM12EN +# define TIMRCCRST_TIM12 STM32_RCC_APB1RSTR +# define TIMRST_TIM12 RCC_APB1RSTR_TIM12RST +# define TIMCLK_TIM13 STM32_APB1_TIM13_CLKIN +# define TIMRCCEN_TIM13 STM32_RCC_APB1ENR +# define TIMEN_TIM13 RCC_APB1ENR_TIM13EN +# define TIMRCCRST_TIM13 STM32_RCC_APB1RSTR +# define TIMRST_TIM13 RCC_APB1RSTR_TIM13RST +# define TIMCLK_TIM14 STM32_APB1_TIM14_CLKIN +# define TIMRCCEN_TIM14 STM32_RCC_APB1ENR +# define TIMEN_TIM14 RCC_APB1ENR_TIM14EN +# define TIMRCCRST_TIM14 STM32_RCC_APB1RSTR +# define TIMRST_TIM14 RCC_APB1RSTR_TIM14RST +# define TIMCLK_TIM15 STM32_APB1_TIM15_CLKIN +# define TIMRCCEN_TIM15 STM32_RCC_APB1ENR +# define TIMEN_TIM15 RCC_APB1ENR_TIM15EN +# define TIMRCCRST_TIM15 STM32_RCC_APB1RSTR +# define TIMRST_TIM15 RCC_APB1RSTR_TIM15RST +# define TIMCLK_TIM16 STM32_APB1_TIM16_CLKIN +# define TIMRCCEN_TIM16 STM32_RCC_APB1ENR +# define TIMEN_TIM16 RCC_APB1ENR_TIM16EN +# define TIMRCCRST_TIM16 STM32_RCC_APB1RSTR +# define TIMRST_TIM16 RCC_APB1RSTR_TIM16RST +# define TIMCLK_TIM17 STM32_APB1_TIM17_CLKIN +# define TIMRCCEN_TIM17 STM32_RCC_APB1ENR +# define TIMEN_TIM17 RCC_APB1ENR_TIM71EN +# define TIMRCCRST_TIM17 STM32_RCC_APB1RSTR +# define TIMRST_TIM17 RCC_APB1RSTR_TIM17RST +#endif + /* Debug ********************************************************************/ #ifdef CONFIG_DEBUG_PWM_INFO @@ -281,7 +434,7 @@ static struct stm32_pwmtimer_s g_pwm1dev = .irq = STM32_IRQ_TIM1UP, #endif .base = STM32_TIM1_BASE, - .pclk = STM32_APB2_TIM1_CLKIN, + .pclk = TIMCLK_TIM1, }; #endif @@ -327,7 +480,7 @@ static struct stm32_pwmtimer_s g_pwm2dev = .irq = STM32_IRQ_TIM2, #endif .base = STM32_TIM2_BASE, - .pclk = STM32_APB1_TIM2_CLKIN, + .pclk = TIMCLK_TIM2, }; #endif @@ -373,7 +526,7 @@ static struct stm32_pwmtimer_s g_pwm3dev = .irq = STM32_IRQ_TIM3, #endif .base = STM32_TIM3_BASE, - .pclk = STM32_APB1_TIM3_CLKIN, + .pclk = TIMCLK_TIM3, }; #endif @@ -419,7 +572,7 @@ static struct stm32_pwmtimer_s g_pwm4dev = .irq = STM32_IRQ_TIM4, #endif .base = STM32_TIM4_BASE, - .pclk = STM32_APB1_TIM4_CLKIN, + .pclk = TIMCLK_TIM4, }; #endif @@ -465,7 +618,7 @@ static struct stm32_pwmtimer_s g_pwm5dev = .irq = STM32_IRQ_TIM5, #endif .base = STM32_TIM5_BASE, - .pclk = STM32_APB1_TIM5_CLKIN, + .pclk = TIMCLK_TIM5, }; #endif @@ -511,7 +664,7 @@ static struct stm32_pwmtimer_s g_pwm8dev = .irq = STM32_IRQ_TIM8UP, #endif .base = STM32_TIM8_BASE, - .pclk = STM32_APB2_TIM8_CLKIN, + .pclk = TIMCLK_TIM8, }; #endif @@ -557,7 +710,7 @@ static struct stm32_pwmtimer_s g_pwm9dev = .irq = STM32_IRQ_TIM9, #endif .base = STM32_TIM9_BASE, - .pclk = STM32_APB2_TIM9_CLKIN, + .pclk = TIMCLK_TIM9, }; #endif @@ -603,7 +756,7 @@ static struct stm32_pwmtimer_s g_pwm10dev = .irq = STM32_IRQ_TIM10, #endif .base = STM32_TIM10_BASE, - .pclk = STM32_APB2_TIM10_CLKIN, + .pclk = TIMCLK_TIM10, }; #endif @@ -649,7 +802,7 @@ static struct stm32_pwmtimer_s g_pwm11dev = .irq = STM32_IRQ_TIM11, #endif .base = STM32_TIM11_BASE, - .pclk = STM32_APB2_TIM11_CLKIN, + .pclk = TIMCLK_TIM11, }; #endif @@ -695,7 +848,7 @@ static struct stm32_pwmtimer_s g_pwm12dev = .irq = STM32_IRQ_TIM12, #endif .base = STM32_TIM12_BASE, - .pclk = STM32_APB1_TIM12_CLKIN, + .pclk = TIMCLK_TIM12, }; #endif @@ -741,7 +894,7 @@ static struct stm32_pwmtimer_s g_pwm13dev = .irq = STM32_IRQ_TIM13, #endif .base = STM32_TIM13_BASE, - .pclk = STM32_APB1_TIM13_CLKIN, + .pclk = TIMCLK_TIM13, }; #endif @@ -787,7 +940,7 @@ static struct stm32_pwmtimer_s g_pwm14dev = .irq = STM32_IRQ_TIM14, #endif .base = STM32_TIM14_BASE, - .pclk = STM32_APB1_TIM14_CLKIN, + .pclk = TIMCLK_TIM14, }; #endif @@ -819,7 +972,7 @@ static struct stm32_pwmtimer_s g_pwm15dev = .irq = STM32_IRQ_TIM15, #endif .base = STM32_TIM15_BASE, - .pclk = STM32_APB1_TIM15_CLKIN, + .pclk = TIMCLK_TIM15, }; #endif @@ -844,7 +997,7 @@ static struct stm32_pwmtimer_s g_pwm16dev = .irq = STM32_IRQ_TIM16, #endif .base = STM32_TIM16_BASE, - .pclk = STM32_APB1_TIM16_CLKIN, + .pclk = TIMCLK_TIM16, }; #endif @@ -869,7 +1022,7 @@ static struct stm32_pwmtimer_s g_pwm17dev = .irq = STM32_IRQ_TIM17, #endif .base = STM32_TIM17_BASE, - .pclk = STM32_APB1_TIM17_CLKIN, + .pclk = TIMCLK_TIM17, }; #endif @@ -954,42 +1107,68 @@ static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, uint16_t value static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg) { pwminfo("%s:\n", msg); - pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - pwm_getreg(priv, STM32_GTIM_CR1_OFFSET), - pwm_getreg(priv, STM32_GTIM_CR2_OFFSET), - pwm_getreg(priv, STM32_GTIM_SMCR_OFFSET), - pwm_getreg(priv, STM32_GTIM_DIER_OFFSET)); - pwminfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - pwm_getreg(priv, STM32_GTIM_SR_OFFSET), - pwm_getreg(priv, STM32_GTIM_EGR_OFFSET), - pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET), - pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); + if (priv->timid == 16 || priv->timid == 17) + { + pwminfo(" CR1: %04x CR2: %04x DIER: %04x\n", + pwm_getreg(priv, STM32_GTIM_CR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CR2_OFFSET), + pwm_getreg(priv, STM32_GTIM_DIER_OFFSET)); + } + else + { + pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", + pwm_getreg(priv, STM32_GTIM_CR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CR2_OFFSET), + pwm_getreg(priv, STM32_GTIM_SMCR_OFFSET), + pwm_getreg(priv, STM32_GTIM_DIER_OFFSET)); + } + + if (priv->timid >= 15 || priv->timid <= 17) + { + pwminfo(" SR: %04x EGR: %04x CCMR1: %04x\n", + pwm_getreg(priv, STM32_GTIM_SR_OFFSET), + pwm_getreg(priv, STM32_GTIM_EGR_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET)); + } + else + { + pwminfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", + pwm_getreg(priv, STM32_GTIM_SR_OFFSET), + pwm_getreg(priv, STM32_GTIM_EGR_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); + } + pwminfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", pwm_getreg(priv, STM32_GTIM_CCER_OFFSET), pwm_getreg(priv, STM32_GTIM_CNT_OFFSET), pwm_getreg(priv, STM32_GTIM_PSC_OFFSET), pwm_getreg(priv, STM32_GTIM_ARR_OFFSET)); - pwminfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET), - pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET), - pwm_getreg(priv, STM32_GTIM_CCR3_OFFSET), - pwm_getreg(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) - if (priv->timtype == TIMTYPE_ADVANCED) + + if (priv->timid >= 15 || priv->timid <= 17) { - pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", + pwminfo(" RCR: %04x BDTR: %04x\n", pwm_getreg(priv, STM32_ATIM_RCR_OFFSET), - pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET), - pwm_getreg(priv, STM32_ATIM_DCR_OFFSET), - pwm_getreg(priv, STM32_ATIM_DMAR_OFFSET)); + pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET)); + } + + if (priv->timid == 16 || priv->timid == 17) + { + pwminfo(" CCR1: %04x\n", + pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET)); } else -#endif { - pwminfo(" DCR: %04x DMAR: %04x\n", - pwm_getreg(priv, STM32_GTIM_DCR_OFFSET), - pwm_getreg(priv, STM32_GTIM_DMAR_OFFSET)); + pwminfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", + pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR3_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR4_OFFSET)); } + + pwminfo(" DCR: %04x DMAR: %04x\n", + pwm_getreg(priv, STM32_GTIM_DCR_OFFSET), + pwm_getreg(priv, STM32_GTIM_DMAR_OFFSET)); } #endif @@ -1520,8 +1699,10 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, /* Some special setup for advanced timers */ -#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) - if (priv->timtype == TIMTYPE_ADVANCED) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) + if (priv->timtype == TIMTYPE_ADVANCED || priv->timtype == TIMTYPE_COUNTUP16) { uint16_t bdtr; @@ -1530,7 +1711,7 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, */ #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F40XX) + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX) ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | ATIM_CCER_CC2NE | ATIM_CCER_CC2NP | ATIM_CCER_CC3NE | ATIM_CCER_CC3NP | ATIM_CCER_CC4NP); #else @@ -1553,14 +1734,16 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv, pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); } #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F40XX) + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX) else #endif #endif #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F40XX) + defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX) { - ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP); + /* CCxNP must be cleared in any case */ + + ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP | GTIM_CCER_CC4NP); } #endif @@ -1875,98 +2058,100 @@ static void pwm_set_apb_clock(FAR struct stm32_pwmtimer_s *priv, bool on) uint32_t en_bit; uint32_t regaddr; + pwminfo("timer %d clock enable: %d\n", priv->timid, on ? 1 : 0); + /* Determine which timer to configure */ switch (priv->timid) { #ifdef CONFIG_STM32_TIM1_PWM case 1: - regaddr = STM32_RCC_APB2ENR; - en_bit = RCC_APB2ENR_TIM1EN; + regaddr = TIMRCCEN_TIM1; + en_bit = TIMEN_TIM1; break; #endif #ifdef CONFIG_STM32_TIM2_PWM case 2: - regaddr = STM32_RCC_APB1ENR; - en_bit = RCC_APB1ENR_TIM2EN; + regaddr = TIMRCCEN_TIM2; + en_bit = TIMEN_TIM2; break; #endif #ifdef CONFIG_STM32_TIM3_PWM case 3: - regaddr = STM32_RCC_APB1ENR; - en_bit = RCC_APB1ENR_TIM3EN; + regaddr = TIMRCCEN_TIM3; + en_bit = TIMEN_TIM3; break; #endif #ifdef CONFIG_STM32_TIM4_PWM case 4: - regaddr = STM32_RCC_APB1ENR; - en_bit = RCC_APB1ENR_TIM4EN; + regaddr = TIMRCCEN_TIM4; + en_bit = TIMEN_TIM4; break; #endif #ifdef CONFIG_STM32_TIM5_PWM case 5: - regaddr = STM32_RCC_APB1ENR; - en_bit = RCC_APB1ENR_TIM5EN; + regaddr = TIMRCCEN_TIM5; + en_bit = TIMEN_TIM5; break; #endif #ifdef CONFIG_STM32_TIM8_PWM case 8: - regaddr = STM32_RCC_APB2ENR; - en_bit = RCC_APB2ENR_TIM8EN; + regaddr = TIMRCCEN_TIM8; + en_bit = TIMEN_TIM8; break; #endif #ifdef CONFIG_STM32_TIM9_PWM case 9: - regaddr = STM32_RCC_APB2ENR; - en_bit = RCC_APB2ENR_TIM9EN; + regaddr = TIMRCCEN_TIM9; + en_bit = TIMEN_TIM9; break; #endif #ifdef CONFIG_STM32_TIM10_PWM case 10: - regaddr = STM32_RCC_APB2ENR; - en_bit = RCC_APB2ENR_TIM10EN; + regaddr = TIMRCCEN_TIM10; + en_bit = TIMEN_TIM10; break; #endif #ifdef CONFIG_STM32_TIM11_PWM case 11: - regaddr = STM32_RCC_APB2ENR; - en_bit = RCC_APB2ENR_TIM11EN; + regaddr = TIMRCCEN_TIM11; + en_bit = TIMEN_TIM11; break; #endif #ifdef CONFIG_STM32_TIM12_PWM case 12: - regaddr = STM32_RCC_APB1ENR; - en_bit = RCC_APB1ENR_TIM12EN; + regaddr = TIMRCCEN_TIM12; + en_bit = TIMEN_TIM12; break; #endif #ifdef CONFIG_STM32_TIM13_PWM case 13: - regaddr = STM32_RCC_APB1ENR; - en_bit = RCC_APB1ENR_TIM13EN; + regaddr = TIMRCCEN_TIM13; + en_bit = TIMEN_TIM13; break; #endif #ifdef CONFIG_STM32_TIM14_PWM case 14: - regaddr = STM32_RCC_APB1ENR; - en_bit = RCC_APB1ENR_TIM14EN; + regaddr = TIMRCCEN_TIM14; + en_bit = TIMEN_TIM14; break; #endif #ifdef CONFIG_STM32_TIM15_PWM case 15: - regaddr = STM32_RCC_APB2ENR; - en_bit = RCC_APB2ENR_TIM15EN; + regaddr = TIMRCCEN_TIM15; + en_bit = TIMEN_TIM15; break; #endif #ifdef CONFIG_STM32_TIM16_PWM case 16: - regaddr = STM32_RCC_APB2ENR; - en_bit = RCC_APB2ENR_TIM16EN; + regaddr = TIMRCCEN_TIM16; + en_bit = TIMEN_TIM16; break; #endif #ifdef CONFIG_STM32_TIM17_PWM case 17: - regaddr = STM32_RCC_APB2ENR; - en_bit = RCC_APB2ENR_TIM17EN; + regaddr = TIMRCCEN_TIM17; + en_bit = TIMEN_TIM17; break; #endif default: @@ -1975,6 +2160,8 @@ static void pwm_set_apb_clock(FAR struct stm32_pwmtimer_s *priv, bool on) /* Enable/disable APB 1/2 clock for timer */ + pwminfo("RCC_APBxENR base: %08x bits: %04x\n", regaddr, en_bit); + if (on) { modifyreg32(regaddr, 0, en_bit); @@ -2012,12 +2199,13 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev) int i; pwminfo("TIM%u\n", priv->timid); - pwm_dumpregs(priv, "Initially"); /* Enable APB1/2 clocking for timer. */ pwm_set_apb_clock(priv, true); + pwm_dumpregs(priv, "Initially"); + /* Configure the PWM output pins, but do not start the timer yet */ for (i = 0; i < PWM_NCHANNELS; i++) @@ -2087,6 +2275,7 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) pincfg |= GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT; #elif defined(CONFIG_STM32_STM32F20XX) || \ defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F37XX) || \ defined(CONFIG_STM32_STM32F40XX) || \ defined(CONFIG_STM32_STM32L15XX) pincfg |= GPIO_INPUT | GPIO_FLOAT; @@ -2216,119 +2405,119 @@ static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) pwminfo("TIM%u\n", priv->timid); - /* Disable interrupts momentary to stop any ongoing timer processing and - * to prevent any concurrent access to the reset register. - */ - - flags = enter_critical_section(); - - /* Stopped so frequency is zero */ - - priv->frequency = 0; - - /* Disable further interrupts and stop the timer */ - - pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); - pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - /* Determine which timer to reset */ switch (priv->timid) { #ifdef CONFIG_STM32_TIM1_PWM case 1: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM1RST; + regaddr = TIMRCCRST_TIM1; + resetbit = TIMRST_TIM1; break; #endif #ifdef CONFIG_STM32_TIM2_PWM case 2: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM2RST; + regaddr = TIMRCCRST_TIM2; + resetbit = TIMRST_TIM2; break; #endif #ifdef CONFIG_STM32_TIM3_PWM case 3: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM3RST; + regaddr = TIMRCCRST_TIM3; + resetbit = TIMRST_TIM3; break; #endif #ifdef CONFIG_STM32_TIM4_PWM case 4: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM4RST; + regaddr = TIMRCCRST_TIM4; + resetbit = TIMRST_TIM4; break; #endif #ifdef CONFIG_STM32_TIM5_PWM case 5: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM5RST; + regaddr = TIMRCCRST_TIM5; + resetbit = TIMRST_TIM5; break; #endif #ifdef CONFIG_STM32_TIM8_PWM case 8: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM8RST; + regaddr = TIMRCCRST_TIM8; + resetbit = TIMRST_TIM8; break; #endif #ifdef CONFIG_STM32_TIM9_PWM case 9: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM9RST; + regaddr = TIMRCCRST_TIM9; + resetbit = TIMRST_TIM9; break; #endif #ifdef CONFIG_STM32_TIM10_PWM case 10: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM10RST; + regaddr = TIMRCCRST_TIM10; + resetbit = TIMRST_TIM10; break; #endif #ifdef CONFIG_STM32_TIM11_PWM case 11: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM11RST; + regaddr = TIMRCCRST_TIM11; + resetbit = TIMRST_TIM11; break; #endif #ifdef CONFIG_STM32_TIM12_PWM case 12: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM12RST; + regaddr = TIMRCCRST_TIM12; + resetbit = TIMRST_TIM12; break; #endif #ifdef CONFIG_STM32_TIM13_PWM case 13: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM13RST; + regaddr = TIMRCCRST_TIM13; + resetbit = TIMRST_TIM13; break; #endif #ifdef CONFIG_STM32_TIM14_PWM case 14: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM14RST; + regaddr = TIMRCCRST_TIM14; + resetbit = TIMRST_TIM14; break; #endif #ifdef CONFIG_STM32_TIM15_PWM case 15: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM15RST; + regaddr = TIMRCCRST_TIM15; + resetbit = TIMRST_TIM15; break; #endif #ifdef CONFIG_STM32_TIM16_PWM case 16: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM16RST; + regaddr = TIMRCCRST_TIM16; + resetbit = TIMRST_TIM16; break; #endif #ifdef CONFIG_STM32_TIM17_PWM case 17: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM17RST; + regaddr = TIMRCCRST_TIM17; + resetbit = TIMRST_TIM17; break; #endif default: return -EINVAL; } + /* Disable interrupts momentary to stop any ongoing timer processing and + * to prevent any concurrent access to the reset register. + */ + + flags = enter_critical_section(); + + /* Stopped so frequency is zero */ + + priv->frequency = 0; + + /* Disable further interrupts and stop the timer */ + + pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0); + /* Reset the timer - stopping the output and putting the timer back * into a state where pwm_start() can be called. */ -- GitLab From 3cb1e0e67fb93767668b891bab389273113842a5 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 7 Nov 2016 09:37:22 -0600 Subject: [PATCH 382/734] STM32F7: Fix Make.defs. Would not work if only SDMMC2 were enabled. --- arch/arm/src/stm32f7/Make.defs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index ee6b3e0687..5f5344d9eb 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -161,7 +161,7 @@ ifeq ($(CONFIG_STM32F7_SPI),y) CHIP_CSRCS += stm32_spi.c endif -ifeq ($(CONFIG_STM32F7_SDMMC1),y) +ifeq ($(CONFIG_STM32F7_SDMMC),y) CHIP_CSRCS += stm32_sdmmc.c endif -- GitLab From 2964779985fb97249eca57f9a3ec512f6acd327c Mon Sep 17 00:00:00 2001 From: Ramtin Amin Date: Mon, 7 Nov 2016 10:10:44 -0600 Subject: [PATCH 383/734] configs/misoc: Add an NSH configuration --- configs/misoc/hello/setenv.sh | 2 +- configs/misoc/nsh/Make.defs | 101 +++++ configs/misoc/nsh/defconfig | 747 ++++++++++++++++++++++++++++++++++ configs/misoc/nsh/setenv.sh | 58 +++ 4 files changed, 907 insertions(+), 1 deletion(-) create mode 100644 configs/misoc/nsh/Make.defs create mode 100644 configs/misoc/nsh/defconfig create mode 100644 configs/misoc/nsh/setenv.sh diff --git a/configs/misoc/hello/setenv.sh b/configs/misoc/hello/setenv.sh index 7ba5ee60e7..9b84648e5c 100644 --- a/configs/misoc/hello/setenv.sh +++ b/configs/misoc/hello/setenv.sh @@ -1,5 +1,5 @@ #!/bin/bash -# configs/amber/hello/setenv.sh +# configs/misoc/hello/setenv.sh # # Copyright (C) 2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt diff --git a/configs/misoc/nsh/Make.defs b/configs/misoc/nsh/Make.defs new file mode 100644 index 0000000000..bf0aa6ba19 --- /dev/null +++ b/configs/misoc/nsh/Make.defs @@ -0,0 +1,101 @@ +############################################################################ +# configs/misoc/nsh/Make.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# Ramtin Amin +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/misoc/src/lm32/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = $(ARCHINCLUDES) "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem "$(TOPDIR)/include" + ARCHXXINCLUDES = $(ARCHINCLUDES) -isystem "$(TOPDIR)/include/cxx" + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD_CUSTOM_NAME)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = diff --git a/configs/misoc/nsh/defconfig b/configs/misoc/nsh/defconfig new file mode 100644 index 0000000000..71aea364a7 --- /dev/null +++ b/configs/misoc/nsh/defconfig @@ -0,0 +1,747 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +CONFIG_DEBUG_FEATURES=y + +# +# Debug SYSLOG Output Controls +# +# CONFIG_DEBUG_ERROR is not set +# CONFIG_DEBUG_ASSERTIONS is not set + +# +# Subsystem Debug Options +# +# CONFIG_DEBUG_BINFMT is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_DEBUG_GRAPHICS is not set +# CONFIG_DEBUG_LIB is not set +# CONFIG_DEBUG_MM is not set +# CONFIG_DEBUG_SCHED is not set + +# +# OS Function Debug Options +# +# CONFIG_DEBUG_IRQ is not set + +# +# Driver Debug Options +# +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_TIMER is not set +# CONFIG_ARCH_HAVE_STACKCHECK is not set +# CONFIG_ARCH_HAVE_HEAPCHECK is not set +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ARCH_HAVE_CUSTOMOPT=y +CONFIG_DEBUG_NOOPT=y +# CONFIG_DEBUG_CUSTOMOPT is not set +# CONFIG_DEBUG_FULLOPT is not set + +# +# System Type +# +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +CONFIG_ARCH_MISOC=y +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="misoc" +CONFIG_ARCH_CHIP="lm32" +CONFIG_ARCH_CHIP_LM32=y +# CONFIG_ARCH_CHIP_MOR1K is not set + +# +# MISOC Peripheral Support +# +CONFIG_MISOC_HAVE_UART1=y +CONFIG_MISOC_UART1=y +CONFIG_MISOC_UART=y +CONFIG_MISOC_UART_RX_BUF_SIZE=64 +CONFIG_MISOC_UART_TX_BUF_SIZE=64 +# CONFIG_LM32_TOOLCHAIN_BUILDROOT is not set +CONFIG_LM32_TOOLCHAIN_GNUL=y + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +# CONFIG_ARCH_HAVE_IRQPRIO is not set +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +# CONFIG_ARCH_HAVE_VFORK is not set +# CONFIG_ARCH_HAVE_MMU is not set +# CONFIG_ARCH_HAVE_MPU is not set +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +# CONFIG_ARCH_HAVE_RESET is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +# CONFIG_ARCH_HAVE_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=800 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x40000000 +CONFIG_RAM_SIZE=524288 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_CUSTOM=y + +# +# Custom Board Configuration +# +CONFIG_ARCH_BOARD_CUSTOM_NAME="misoc" +CONFIG_ARCH_BOARD_CUSTOM_DIR="/configs/misoc/" +CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y +# CONFIG_BOARD_CUSTOM_LEDS is not set +# CONFIG_BOARD_CUSTOM_BUTTONS is not set + +# +# Common Board Options +# + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +# CONFIG_LIB_BOARDCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_DISABLE_SIGNALS=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_ENVIRON=y + +# +# Clocks and Timers +# +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2011 +CONFIG_START_MONTH=6 +CONFIG_START_DAY=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_TIMERS=0 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=0 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=0 +CONFIG_MAX_TASKS=4 +# CONFIG_SCHED_HAVE_PARENT is not set +# CONFIG_SCHED_WAITPID is not set + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=4 +CONFIG_NFILE_STREAMS=4 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +# CONFIG_MODULE is not set + +# +# Work queue support +# + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=1024 +CONFIG_PTHREAD_STACK_MIN=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +# CONFIG_ARCH_HAVE_I2CRESET is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +CONFIG_UART1_SERIALDRIVER=y +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +# CONFIG_SERIAL_TIOCSERGSTRUCT is not set +# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set +CONFIG_UART1_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART1 Configuration +# +CONFIG_UART1_RXBUFSIZE=256 +CONFIG_UART1_TXBUFSIZE=256 +CONFIG_UART1_BAUD=115200 +CONFIG_UART1_BITS=8 +CONFIG_UART1_PARITY=0 +CONFIG_UART1_2STOP=0 +# CONFIG_UART1_IFLOWCONTROL is not set +# CONFIG_UART1_OFLOWCONTROL is not set +# CONFIG_UART1_DMA is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +# CONFIG_FS_READABLE is not set +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_BUILTIN is not set +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=0 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=0 +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_LIBC_LONG_LONG is not set +# CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +# CONFIG_ARCH_HAVE_TLS is not set +# CONFIG_LIBC_NETDB is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_CCTYPE is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLO_PRIORITY=100 +CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +CONFIG_EXAMPLES_OSTEST=y +CONFIG_EXAMPLES_OSTEST_LOOPS=1 +CONFIG_EXAMPLES_OSTEST_STACKSIZE=8192 +CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=8 +CONFIG_EXAMPLES_OSTEST_RR_RANGE=10000 +CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +# CONFIG_NSH_READLINE is not set +CONFIG_NSH_CLE=y +CONFIG_NSH_LINELEN=80 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +CONFIG_NSH_MAXARGUMENTS=6 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +CONFIG_NSH_DISABLE_IFCONFIG=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y +CONFIG_NSH_DISABLE_PS=y +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Configure Command Options +# +CONFIG_NSH_CMDOPT_DF_H=y +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_CMDOPT_HEXDUMP=y +CONFIG_NSH_FILEIOSIZE=1024 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +# CONFIG_NSH_ARCHINIT is not set +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +CONFIG_SYSTEM_CLE=y +CONFIG_SYSTEM_CLE_DEBUGLEVEL=0 +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/misoc/nsh/setenv.sh b/configs/misoc/nsh/setenv.sh new file mode 100644 index 0000000000..851cd9727d --- /dev/null +++ b/configs/misoc/nsh/setenv.sh @@ -0,0 +1,58 @@ +#!/bin/bash +# configs/misoc/nsh/setenv.sh +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# Ramtin Amin +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +export TOOLCHAIN_BIN="${WD}/../buildroot/build_lm32/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" -- GitLab From 693f8d743d218082a9f3b906ea25e27fc5fd78d3 Mon Sep 17 00:00:00 2001 From: Ramtin Amin Date: Mon, 7 Nov 2016 10:13:53 -0600 Subject: [PATCH 384/734] LM32: Move interrupt definitions from common irq.h to lm32/irq.h. Remove unused misoc_uart.c and .h --- arch/misoc/include/irq.h | 4 - arch/misoc/include/lm32/irq.h | 6 + arch/misoc/src/common/misoc_uart.c | 233 --------------------------- arch/misoc/src/common/misoc_uart.h | 60 ------- arch/misoc/src/lm32/lm32_decodeirq.c | 2 +- arch/misoc/src/lm32/lm32_irq.c | 6 +- arch/misoc/src/lm32/lm32_vectors.S | 2 +- 7 files changed, 11 insertions(+), 302 deletions(-) delete mode 100644 arch/misoc/src/common/misoc_uart.c delete mode 100644 arch/misoc/src/common/misoc_uart.h diff --git a/arch/misoc/include/irq.h b/arch/misoc/include/irq.h index a21987b00a..882c37a0fb 100644 --- a/arch/misoc/include/irq.h +++ b/arch/misoc/include/irq.h @@ -53,11 +53,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* 32 True interrupts plus the sofware interrupt */ -#define MISOC_NINTERRUPTS 32 -#define MISOC_IRQ_SWINT 32 -#define NR_IRQS 33 /**************************************************************************** * Public Function Prototypes diff --git a/arch/misoc/include/lm32/irq.h b/arch/misoc/include/lm32/irq.h index 782bb06ae9..2e5e51e83a 100644 --- a/arch/misoc/include/lm32/irq.h +++ b/arch/misoc/include/lm32/irq.h @@ -48,6 +48,12 @@ * Pre-processor Definitions ****************************************************************************/ +/* 32 True interrupts plus the sofware interrupt */ + +#define LM32_NINTERRUPTS 32 +#define LM32_IRQ_SWINT 32 +#define NR_IRQS 33 + /* Registers */ #define REG_X0_NDX 0 /* Holds the value zero */ diff --git a/arch/misoc/src/common/misoc_uart.c b/arch/misoc/src/common/misoc_uart.c deleted file mode 100644 index 76cdd48703..0000000000 --- a/arch/misoc/src/common/misoc_uart.c +++ /dev/null @@ -1,233 +0,0 @@ -/**************************************************************************** - * arch/misoc/src/common/misoc_uart.c - * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Ramtin Amin - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_SERIAL_TERMIOS -# include -#endif - -#include -#include -#include - -#include -#include - -#include "hw/flags.h" -#include "misoc_uart.h" - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Buffer sizes must be a power of 2 so that modulos can be computed - * with logical AND. - */ - -#define UART_RINGBUFFER_SIZE_RX 128 -#define UART_RINGBUFFER_MASK_RX (UART_RINGBUFFER_SIZE_RX-1) - -#define UART_RINGBUFFER_SIZE_TX 128 -#define UART_RINGBUFFER_MASK_TX (UART_RINGBUFFER_SIZE_TX-1) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static char rx_buf[UART_RINGBUFFER_SIZE_RX]; -static volatile unsigned int rx_produce; -static unsigned int rx_consume; - -static char tx_buf[UART_RINGBUFFER_SIZE_TX]; -static unsigned int tx_produce; -static volatile unsigned int tx_consume; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: uart_interrupt - ****************************************************************************/ - -static int uart_interrupt(int irq, void *context) -{ - unsigned int stat, rx_produce_next; - - stat = uart_ev_pending_read(); - - if ((stat & UART_EV_RX) != 0) - { - while (!uart_rxempty_read()) - { - rx_produce_next = (rx_produce + 1) & UART_RINGBUFFER_MASK_RX; - if (rx_produce_next != rx_consume) - { - rx_buf[rx_produce] = uart_rxtx_read(); - rx_produce = rx_produce_next; - } - - uart_ev_pending_write(UART_EV_RX); - } - } - - if ((stat & UART_EV_TX) != 0) - { - uart_ev_pending_write(UART_EV_TX); - while ((tx_consume != tx_produce) && !uart_txfull_read()) - { - uart_rxtx_write(tx_buf[tx_consume]); - tx_consume = (tx_consume + 1) & UART_RINGBUFFER_MASK_TX; - } - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: uart_read - * - * Do not use in interrupt handlers! - * - ****************************************************************************/ - -char uart_read(void) -{ - char c; - - if (irq_getie()) - { - while (rx_consume == rx_produce); - } - else if (rx_consume == rx_produce) - { - return 0; - } - - c = rx_buf[rx_consume]; - rx_consume = (rx_consume + 1) & UART_RINGBUFFER_MASK_RX; - return c; -} - -/**************************************************************************** - * Name: uart_read_nonblock - ****************************************************************************/ - -int uart_read_nonblock(void) -{ - return (rx_consume != rx_produce); -} - -/**************************************************************************** - * Name: up_putc - ****************************************************************************/ - -int up_putc(int ch) -{ - unsigned int oldmask; - unsigned int tx_produce_next = (tx_produce + 1) & UART_RINGBUFFER_MASK_TX; - - if (irq_getie()) - { - while (tx_produce_next == tx_consume); - } - else if (tx_produce_next == tx_consume) - { - return ch; - } - - oldmask = irq_getmask(); - irq_setmask(oldmask & ~(1 << UART_INTERRUPT)); - - if ((tx_consume != tx_produce) || uart_txfull_read()) - { - tx_buf[tx_produce] = ch; - tx_produce = tx_produce_next; - } - else - { - uart_rxtx_write(ch); - } - - irq_setmask(oldmask); - return ch; -} - -/**************************************************************************** - * Name: uart_init - ****************************************************************************/ - -void uart_init(void) -{ - rx_produce = 0; - rx_consume = 0; - - tx_produce = 0; - tx_consume = 0; - - uart_ev_pending_write(uart_ev_pending_read()); - uart_ev_enable_write(UART_EV_TX | UART_EV_RX); - irq_setmask(irq_getmask() | (1 << UART_INTERRUPT)); - - irq_attach(1 << UART_INTERRUPT, uart_interrupt); -} - -/**************************************************************************** - * Name: uart_sync - ****************************************************************************/ - -void uart_sync(void) -{ - while (tx_consume != tx_produce); -} diff --git a/arch/misoc/src/common/misoc_uart.h b/arch/misoc/src/common/misoc_uart.h deleted file mode 100644 index 74fcc7c0ac..0000000000 --- a/arch/misoc/src/common/misoc_uart.h +++ /dev/null @@ -1,60 +0,0 @@ -/**************************************************************************** - * arch/misoc/src/common/misoc_uart.c - * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Ramtin Amin - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_MISOC_SRC_COMMON_MISOC_UART_H -#define __ARCH_MISOC_SRC_COMMON_MISOC_UART_H 1 - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef __cplusplus -extern "C" -{ -#endif - -void uart_init(void); -void uart_isr(void); -void uart_sync(void); - -void uart_write(char c); -char uart_read(void); -int uart_read_nonblock(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __ARCH_MISOC_SRC_COMMON_MISOC_UART_H */ diff --git a/arch/misoc/src/lm32/lm32_decodeirq.c b/arch/misoc/src/lm32/lm32_decodeirq.c index 1cb792cedf..ea55e3a0b7 100644 --- a/arch/misoc/src/lm32/lm32_decodeirq.c +++ b/arch/misoc/src/lm32/lm32_decodeirq.c @@ -74,7 +74,7 @@ uint32_t *lm32_decodeirq(uint32_t intstat, uint32_t *regs) /* Decode and dispatch interrupts */ - for (irq = 0; irq < MISOC_NINTERRUPTS && intstat != 0; irq++) + for (irq = 0; irq < LM32_NINTERRUPTS && intstat != 0; irq++) { uint32_t bit = (1 << irq); diff --git a/arch/misoc/src/lm32/lm32_irq.c b/arch/misoc/src/lm32/lm32_irq.c index dab24189e6..eb5313810d 100644 --- a/arch/misoc/src/lm32/lm32_irq.c +++ b/arch/misoc/src/lm32/lm32_irq.c @@ -71,7 +71,7 @@ void lm32_irq_initialize(void) /* Attach the software interrupt */ - (void)irq_attach(MISOC_IRQ_SWINT, lm32_swint); + (void)irq_attach(LM32_IRQ_SWINT, lm32_swint); /* Enable interrupts */ @@ -129,7 +129,7 @@ void up_disable_irq(int irq) /* Ignore any attempt to disable software interrupts */ - if (irq < MISOC_NINTERRUPTS) + if (irq < LM32_NINTERRUPTS) { /* Disable interrupts by clearing the bit that corresponds to the irq */ @@ -154,7 +154,7 @@ void up_enable_irq(int irq) /* Ignore any attempt to enable software interrupts */ - if (irq < MISOC_NINTERRUPTS) + if (irq < LM32_NINTERRUPTS) { /* Enable interrupts by setting the bit that corresponds to the irq */ diff --git a/arch/misoc/src/lm32/lm32_vectors.S b/arch/misoc/src/lm32/lm32_vectors.S index 95cfd26001..94521a3a69 100644 --- a/arch/misoc/src/lm32/lm32_vectors.S +++ b/arch/misoc/src/lm32/lm32_vectors.S @@ -152,7 +152,7 @@ _syscall_handler: sw (sp+0), ra addi ea, ea, 4 calli .save_all - mvi r1, MISOC_IRQ_SWINT + mvi r1, LM32_IRQ_SWINT calli lm32_doirq bi .restore_all_and_eret nop -- GitLab From d6759019136ebae7d05d4dcb5aaf0cbff605e575 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 7 Nov 2016 11:03:01 -0600 Subject: [PATCH 385/734] ESP32: Update README. --- configs/esp32-core/README.txt | 75 +++++++++++++++++++++++++++++++---- 1 file changed, 68 insertions(+), 7 deletions(-) diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index 933420fc00..b1fd04a83d 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -22,6 +22,7 @@ Contents o Serial Console o Buttons and LEDs o SMP + o Debug Issues o Configurations o Things to Do @@ -135,6 +136,51 @@ SMP 3. Assertions. On a fatal assertions, other CPUs need to be stopped. +Debug Issues +============ + + I basically need the debug environment and a step-by-step procedure. + + - First in need some debug environment which would be a JTAG emulator + and software. + + - I don't see any way to connect JTAG to the ESP32 Core V2 board. There + is a USB/Serial converter chip, but that does not look it supports JTAG. + + - I need to understand how to use the secondary bootloader. My + understanding is that it will configure hardware, read a partition + table at address 0x5000, and then load code into memory. I do need to + download and build the bootloader? + + - Do I need to create a partition table at 0x5000? Should this be part + of the NuttX build? + + I see https://github.com/espressif/esp-idf/tree/master/components/bootloader + and https://github.com/espressif/esp-idf/tree/master/components/partition_table. + I suppose some of what I need is in there, but I am not sure what I am + looking at right now. + + There is an OpenOCD port here: https://github.com/espressif/openocd-esp32 + and I see some additional OpenOCD documentation in + https://github.com/espressif/esp-idf/tree/master/docs. This documentation + raises some more questions. It says I need to use and external JTAG like + the TIAO USB Multi-protocol Adapter and the Flyswatter2. I don't have + either of those. I am not sure if I have any USB serial JTAG. I have some + older ones that might work, however. + + My understanding when I started this was that I could use my trusty Segger + J-Link. But that won't work with OpenOCD. Is the J-Link that also a + possibility? + + I also see that I can now get an ESP32 board from Sparkfun: + https://www.sparkfun.com/products/13907 But I don't see JTAG there either: + https://cdn.sparkfun.com/assets/learn_tutorials/5/0/7/esp32-thing-schematic.pdf + + Right now, the NuttX port depends on the bootloader to initialize hardware, + including basic (slow) clocking. If I had the clock configuration logic, + would I be able to run directly out of IRAM without a bootloader? That + might be a simpler bring-up. + Configurations ============== @@ -202,14 +248,29 @@ Things to Do ============ 1. There is no support for an interrupt stack yet. - 2. I did not implement the lazy co-processor save logic supported by Xtensa. That logic works like this: - - a. CPENABLE is set to zero on each context switch, disabling all co-processors. - b. If/when the task attempts to use the disabled co-processor, an exception occurs + 2. There is no clock intialization logic in place. This depends on logic in + Expressif libriaries. The board comes up using that basic 40 Mhz crystal + for clocking. Getting to 80 MHz will require clocking initialization in + esp32_clockconfig.c. + 3. I did not implement the lazy co-processor save logic supported by Xtensa. + That logic works like this: + + a. CPENABLE is set to zero on each context switch, disabling all co- + processors. + b. If/when the task attempts to use the disabled co-processor, an + exception occurs c. The co-processor exception handler re-enables the co-processor. - Instead, the NuttX logic saves and restores CPENABLE on each context switch. + Instead, the NuttX logic saves and restores CPENABLE on each context + switch. + + 4. Currently the Xtensa port copies register state save information from + the stack into the TCB. A more efficient alternative would be to just + save a pointer to a register state save area in the TCB. This would + add some complexity to signal handling and also also the the + up_initialstate(). But the performance improvement might be worth + the effort. - 3. Currently the Xtensa port copies register state save information from the stack into the TCB. A more efficient alternative would be to just save a pointer to a register state save area in the TCB. This would add some complexity to signal handling and also also the the up_initialstate(). But the performance improvement might be worth the effort. + 5. See SMP-related issues above - 4. See SMP-related issues above \ No newline at end of file + 6. See Debug Issues above -- GitLab From 9045959aa694e73c2927cac1211a1c4e786319b9 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 8 Nov 2016 07:45:21 -0600 Subject: [PATCH 386/734] Update TODO and README --- TODO | 56 ++++++++++++++++++----------------- configs/esp32-core/README.txt | 7 ++++- 2 files changed, 35 insertions(+), 28 deletions(-) diff --git a/TODO b/TODO index 703cfad205..aa048fde33 100644 --- a/TODO +++ b/TODO @@ -467,21 +467,23 @@ o pthreads (sched/pthreads) Title: PTHREAD_PRIO_PROTECT Description: Extend pthread_mutexattr_setprotocol() support PTHREAD_PRIO_PROTECT: + "When a thread owns one or more mutexes initialized with the PTHREAD_PRIO_PROTECT protocol, it shall execute at the higher of its priority or the highest of the priority ceilings of all the mutexes owned by this thread and initialized with this attribute, regardless of whether other threads are blocked on any of these mutexes or not. - "While a thread is holding a mutex which has been initialized with + "While a thread is holding a mutex which has been initialized with the PTHREAD_PRIO_INHERIT or PTHREAD_PRIO_PROTECT protocol attributes, it shall not be subject to being moved to the tail of the scheduling queue at its priority in the event that its original priority is changed, such as by a call to sched_setparam(). Likewise, when a thread unlocks a mutex that has been initialized with the PTHREAD_PRIO_INHERIT or PTHREAD_PRIO_PROTECT protocol attributes, it shall not be subject to - being moved to the tail of the scheduling queue at its priority in the + being moved to the tail of the scheduling queue at its priority in the event that its original priority is changed." + Status: Open. No changes planned. Priority: Low -- about zero, probably not that useful. Priority inheritance is already supported and is a much better solution. And it turns out @@ -489,39 +491,39 @@ o pthreads (sched/pthreads) Excerpted from my post in a Linked-In discussion: "I started to implement this HLS/"PCP" semaphore in an RTOS that I - work with (http://www.nuttx.org) and I discovered after doing the - analysis and basic code framework that a complete solution for the - case of a counting semaphore is still quite complex -- essentially - as complex as is priority inheritance. + work with (http://www.nuttx.org) and I discovered after doing the + analysis and basic code framework that a complete solution for the + case of a counting semaphore is still quite complex -- essentially + as complex as is priority inheritance. "For example, suppose that a thread takes 3 different HLS semaphores - A, B, and C. Suppose that they are prioritized in that order with - A the lowest and C the highest. Suppose the thread takes 5 counts - from A, 3 counts from B, and 2 counts from C. What priority should - it run at? It would have to run at the priority of the highest - priority semaphore C. This means that the RTOS must maintain - internal information of the priority of every semaphore held by - the thread. + A, B, and C. Suppose that they are prioritized in that order with + A the lowest and C the highest. Suppose the thread takes 5 counts + from A, 3 counts from B, and 2 counts from C. What priority should + it run at? It would have to run at the priority of the highest + priority semaphore C. This means that the RTOS must maintain + internal information of the priority of every semaphore held by + the thread. "Now suppose it releases one count on semaphore B. How does the - RTOS know that it still holds 2 counts on B? With some complex - internal data structure. The RTOS would have to maintain internal - information about how many counts from each semaphore are held - by each thread. + RTOS know that it still holds 2 counts on B? With some complex + internal data structure. The RTOS would have to maintain internal + information about how many counts from each semaphore are held + by each thread. "How does the RTOS know that it should not decrement the priority - from the priority of C? Again, only with internal complexity. It - would have to know the priority of every semaphore held by - every thread. + from the priority of C? Again, only with internal complexity. It + would have to know the priority of every semaphore held by + every thread. "Providing the HLS capability on a simple pthread mutex would not - be such quite such a complex job if you allow only one mutex per - thread. However, the more general case seems almost as complex - as priority inheritance. I decided that the implementation does - not have value to me. I only wanted it for its reduced - complexity; in all other ways I believe that it is the inferior - solution. So I discarded a few hours of programming. Not a - big loss from the experience I gained." + be such quite such a complex job if you allow only one mutex per + thread. However, the more general case seems almost as complex + as priority inheritance. I decided that the implementation does + not have value to me. I only wanted it for its reduced + complexity; in all other ways I believe that it is the inferior + solution. So I discarded a few hours of programming. Not a + big loss from the experience I gained." o Message Queues (sched/mqueue) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index b1fd04a83d..12fdbc4581 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -145,7 +145,12 @@ Debug Issues and software. - I don't see any way to connect JTAG to the ESP32 Core V2 board. There - is a USB/Serial converter chip, but that does not look it supports JTAG. + is a USB/Serial converter chip, but that does not look like it + supports JTAG. + + It may be necessary to make cable. Refer to + http://www.esp32.com/viewtopic.php?t=381 "How to debug ESP32 with + JTAG / OpenOCD / GDB 1st part connect the hardware." - I need to understand how to use the secondary bootloader. My understanding is that it will configure hardware, read a partition -- GitLab From 58c2cd2843f02612a9e186574603328b9dd74ea9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marc=20Recht=C3=A9?= Date: Tue, 8 Nov 2016 07:46:25 -0600 Subject: [PATCH 387/734] drivers/ioexpander: Add some debug output. --- drivers/ioexpander/gpio.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/ioexpander/gpio.c b/drivers/ioexpander/gpio.c index bf256e8a0a..072687f1f8 100644 --- a/drivers/ioexpander/gpio.c +++ b/drivers/ioexpander/gpio.c @@ -372,6 +372,8 @@ int gpio_pin_register(FAR struct gpio_dev_s *dev, int minor) } snprintf(devname, 16, fmt, (unsigned int)minor); + gpioinfo("Registering %s\n", devname); + return register_driver(devname, &g_gpio_drvrops, 0666, dev); } -- GitLab From 6d2a10571f808561ca7109a6ec165d5781a302c8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 8 Nov 2016 08:22:07 -0600 Subject: [PATCH 388/734] Update README --- configs/misoc/README.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/misoc/README.txt b/configs/misoc/README.txt index 285b6a4724..2bb07dc699 100644 --- a/configs/misoc/README.txt +++ b/configs/misoc/README.txt @@ -4,6 +4,9 @@ Misoc README This README applies to a port to NuttX running on a Qemu LM32 system. You can find the Qemu setup at https://bitbucket.org/key2/qemu + This initial release supports two UARTs, but does not have a system timer + or other peripherals. More to come. + Buildroot Toolchain =================== -- GitLab From b6d6b774e9c78a6e9597b87a8b4658b33db66606 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 8 Nov 2016 08:23:52 -0600 Subject: [PATCH 389/734] Xtensa: In this model, co-processor state restore must enable co-processors in CPENABLE. --- arch/xtensa/src/common/xtensa_coproc.S | 50 ++++++++++++++------------ 1 file changed, 27 insertions(+), 23 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_coproc.S b/arch/xtensa/src/common/xtensa_coproc.S index c29e23a33b..371959b2de 100644 --- a/arch/xtensa/src/common/xtensa_coproc.S +++ b/arch/xtensa/src/common/xtensa_coproc.S @@ -113,29 +113,29 @@ _xtensa_coproc_savestate: /* Move the address of the thread state save area to R15 */ - mov a15, a2 /* A15 is now the address of the save area */ + mov a15, a2 /* A15 is now the address of the save area */ /* CPENABLE should show which CPs are enabled. */ - rsr a2, CPENABLE /* a2 = which CPs are enabled */ - beqz a2, .Ldone1 /* Quick exit if none */ + rsr a2, CPENABLE /* a2 = which CPs are enabled */ + beqz a2, .Ldone1 /* Quick exit if none */ - s16i a2, a15, XTENSA_CPSTORED /* Save mask of CPs being stored */ + s16i a2, a15, XTENSA_CPSTORED /* Save mask of CPs being stored */ movi a13, _xtensa_coproc_saoffsets /* Array of CP save offsets */ - l32i a15, a15, XTENSA_CPASA /* a15 = base of aligned save area */ + l32i a15, a15, XTENSA_CPASA /* a15 = base of aligned save area */ #if XCHAL_CP0_SA_SIZE > 0 - bbci.l a2, 0, 2f /* CP 0 not enabled */ - l32i a14, a13, 0 /* a14 = _xtensa_coproc_saoffsets[0] */ - add a3, a14, a15 /* a3 = save area for CP 0 */ + bbci.l a2, 0, 2f /* CP 0 not enabled */ + l32i a14, a13, 0 /* a14 = _xtensa_coproc_saoffsets[0] */ + add a3, a14, a15 /* a3 = save area for CP 0 */ xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL 2: #endif #if XCHAL_CP1_SA_SIZE > 0 - bbci.l a2, 1, 2f /* CP 1 not enabled */ - l32i a14, a13, 4 /* a14 = _xtensa_coproc_saoffsets[1] */ - add a3, a14, a15 /* a3 = save area for CP 1 */ + bbci.l a2, 1, 2f /* CP 1 not enabled */ + l32i a14, a13, 4 /* a14 = _xtensa_coproc_saoffsets[1] */ + add a3, a14, a15 /* a3 = save area for CP 1 */ xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL 2: #endif @@ -283,11 +283,10 @@ xtensa_coproc_savestate: * Entry Conditions: * - A2 holds the address of the co-processor state save area * - The incoming thread is set as the current thread. - * - CPENABLE is set up correctly for all required coprocessors. * * Exit conditions: * - All necessary CP callee-saved state has been restored. - * - CPENABLE - unchanged. + * - CPENABLE - Set up correctly for the current thread. * - Registers a2-a7, a13-a15 have been trashed. * * Must be called from assembly code only, using CALL0. @@ -305,26 +304,29 @@ _xtensa_coproc_restorestate: /* Move the address of the thread state save area to R15 */ - mov a15, a2 /* A15 is now the address of the save area */ - l16ui a2, a15, XTENSA_CPSTORED /* a2 = which CPs have been saved */ - movi a3, 0 /* Clear the ones being restored (all of them) */ + mov a15, a2 /* A15 is now the address of the save area */ + + l16ui a2, a15, XTENSA_CPENABLE /* a2 = Which CPs have been enable for this thread? */ + wsr a2, CPENABLE /* Set CPENABLE correctly for this thread */ + l16ui a2, a15, XTENSA_CPSTORED /* a2 = Which CPs have been saved for this thread? */ + movi a3, 0 /* Clear the ones being restored (all of them) */ s16i a3, a15, XTENSA_CPSTORED /* Clear saved CP mask */ movi a13, _xtensa_coproc_saoffsets /* Array of CP save offsets */ - l32i a15, a15, XTENSA_CPASA /* a15 = base of aligned save area */ + l32i a15, a15, XTENSA_CPASA /* a15 = base of aligned save area */ #if XCHAL_CP0_SA_SIZE - bbci.l a2, 0, 2f /* CP 0 not enabled */ - l32i a14, a13, 0 /* a14 = _xtensa_coproc_saoffsets[0] */ - add a3, a14, a15 /* a3 = save area for CP 0 */ + bbci.l a2, 0, 2f /* CP 0 not enabled */ + l32i a14, a13, 0 /* a14 = _xtensa_coproc_saoffsets[0] */ + add a3, a14, a15 /* a3 = save area for CP 0 */ xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL 2: #endif #if XCHAL_CP1_SA_SIZE - bbci.l a2, 1, 2f /* CP 1 not enabled */ - l32i a14, a13, 4 /* a14 = _xtensa_coproc_saoffsets[1] */ - add a3, a14, a15 /* a3 = save area for CP 1 */ + bbci.l a2, 1, 2f /* CP 1 not enabled */ + l32i a14, a13, 4 /* a14 = _xtensa_coproc_saoffsets[1] */ + add a3, a14, a15 /* a3 = save area for CP 1 */ xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL 2: #endif @@ -376,7 +378,9 @@ _xtensa_coproc_restorestate: xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL 2: #endif + /* Ensure wsr.CPENABLE has completed. */ + rsync ret .size _xtensa_coproc_restorestate, . - _xtensa_coproc_restorestate -- GitLab From ac1bb127b6e169aca86af8b0715ee622aeba1c18 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 8 Nov 2016 08:51:03 -0600 Subject: [PATCH 390/734] Correct some C++ style comments. --- arch/xtensa/src/esp32/esp32_clockconfig.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/xtensa/src/esp32/esp32_clockconfig.c b/arch/xtensa/src/esp32/esp32_clockconfig.c index f2f7df08ea..cabcb1197b 100644 --- a/arch/xtensa/src/esp32/esp32_clockconfig.c +++ b/arch/xtensa/src/esp32/esp32_clockconfig.c @@ -84,7 +84,7 @@ void esp32_clockconfig(void) phy_get_romfunc_addr(); - // freq will be changed to 40MHz in rtc_init_lite + /* Frequency will be changed to 40MHz in rtc_init_lite */ rtc_init_lite(); @@ -105,7 +105,7 @@ void esp32_clockconfig(void) break; } - // freq will be changed to freq in rtc_set_cpu_freq, + /* Frequency will be changed to freq in rtc_set_cpu_freq */ rtc_set_cpu_freq(XTAL_AUTO, freq); ets_update_cpu_frequency(freq_mhz); -- GitLab From 484a1b61049ca9927979216503d4a08abf9600b3 Mon Sep 17 00:00:00 2001 From: Freddie Chopin Date: Wed, 9 Nov 2016 07:01:49 -0600 Subject: [PATCH 391/734] sem_wait() and sem_trywait() no longer modify the errno value UNLESS an error occurs. This allows these functions to be used internallly without clobbering the errno value. --- sched/semaphore/sem_trywait.c | 24 ++++++++++++------------ sched/semaphore/sem_wait.c | 4 ++-- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/sched/semaphore/sem_trywait.c b/sched/semaphore/sem_trywait.c index 37ba0d66e2..c55116a2b7 100644 --- a/sched/semaphore/sem_trywait.c +++ b/sched/semaphore/sem_trywait.c @@ -84,13 +84,9 @@ int sem_trywait(FAR sem_t *sem) /* This API should not be called from interrupt handlers */ - DEBUGASSERT(up_interrupt_context() == false); + DEBUGASSERT(sem != NULL && up_interrupt_context() == false); - /* Assume any errors reported are due to invalid arguments. */ - - set_errno(EINVAL); - - if (sem) + if (sem != NULL) { /* The following operations must be performed with interrupts disabled * because sem_post() may be called from an interrupt handler. @@ -98,12 +94,6 @@ int sem_trywait(FAR sem_t *sem) flags = enter_critical_section(); - /* Any further errors could only occurr because the semaphore is not - * available. - */ - - set_errno(EAGAIN); - /* If the semaphore is available, give it to the requesting task */ if (sem->semcount > 0) @@ -114,11 +104,21 @@ int sem_trywait(FAR sem_t *sem) rtcb->waitsem = NULL; ret = OK; } + else + { + /* Semaphore is not available */ + + set_errno(EAGAIN); + } /* Interrupts may now be enabled. */ leave_critical_section(flags); } + else + { + set_errno(EINVAL); + } return ret; } diff --git a/sched/semaphore/sem_wait.c b/sched/semaphore/sem_wait.c index 9c19d406d7..da855bc70c 100644 --- a/sched/semaphore/sem_wait.c +++ b/sched/semaphore/sem_wait.c @@ -84,11 +84,11 @@ int sem_wait(FAR sem_t *sem) /* This API should not be called from interrupt handlers */ - DEBUGASSERT(up_interrupt_context() == false); + DEBUGASSERT(sem != NULL && up_interrupt_context() == false); /* Make sure we were supplied with a valid semaphore. */ - if (sem) + if (sem != NULL) { /* The following operations must be performed with interrupts * disabled because sem_post() may be called from an interrupt -- GitLab From a9c66683f285494f5182ad19c1b3e0790aa22f7a Mon Sep 17 00:00:00 2001 From: Sebastien Lorquet Date: Wed, 9 Nov 2016 19:16:44 +0100 Subject: [PATCH 392/734] Change the way to configure quadrature encoder prescalers. --- arch/arm/src/stm32l4/Kconfig | 54 +++++++++++---------- arch/arm/src/stm32l4/stm32l4_qencoder.c | 62 +++++++++++-------------- 2 files changed, 56 insertions(+), 60 deletions(-) diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index a365dd4783..6995a51421 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -2807,11 +2807,12 @@ config STM32L4_TIM1_QE if STM32L4_TIM1_QE -config STM32L4_TIM1_QECLKOUT - int "TIM1 output clock" - default 2800000 +config STM32L4_TIM1_QEPSC + int "TIM1 pulse prescaler" + default 1 ---help--- - The output clock of TIM1. + This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. + Replaces the obscure "output clock of TIM1." (CONFIG_TIM1_QECLKOUT). endif @@ -2824,11 +2825,12 @@ config STM32L4_TIM2_QE if STM32L4_TIM2_QE -config STM32L4_TIM2_QECLKOUT - int "TIM2 output clock" - default 2800000 +config STM32L4_TIM2_QEPSC + int "TIM2 pulse prescaler" + default 1 ---help--- - The output clock of TIM2. + This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. + Replaces the obscure "output clock of TIM2." (CONFIG_TIM2_QECLKOUT). endif @@ -2841,11 +2843,12 @@ config STM32L4_TIM3_QE if STM32L4_TIM3_QE -config STM32L4_TIM3_QECLKOUT - int "TIM3 output clock" - default 2800000 +config STM32L4_TIM3_QEPSC + int "TIM3 pulse prescaler" + default 1 ---help--- - The output clock of TIM3. + This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. + Replaces the obscure "output clock of TIM3." (CONFIG_TIM3_QECLKOUT). endif @@ -2858,11 +2861,12 @@ config STM32L4_TIM4_QE if STM32L4_TIM4_QE -config STM32L4_TIM4_QECLKOUT - int "TIM4 output clock" - default 2800000 +config STM32L4_TIM4_QEPSC + int "TIM4 pulse prescaler" + default 1 ---help--- - The output clock of TIM4. + This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. + Replaces the obscure "output clock of TIM4." (CONFIG_TIM4_QECLKOUT). endif @@ -2875,11 +2879,12 @@ config STM32L4_TIM5_QE if STM32L4_TIM5_QE -config STM32L4_TIM5_QECLKOUT - int "TIM5 output clock" - default 2800000 +config STM32L4_TIM5_QEPSC + int "TIM5 pulse prescaler" + default 1 ---help--- - The output clock of TIM5. + This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. + Replaces the obscure "output clock of TIM5." (CONFIG_TIM5_QECLKOUT). endif @@ -2892,11 +2897,12 @@ config STM32L4_TIM8_QE if STM32L4_TIM8_QE -config STM32L4_TIM8_QECLKOUT - int "TIM8 output clock" - default 2800000 +config STM32L4_TIM8_QEPSC + int "TIM8 pulse prescaler" + default 1 ---help--- - The output clock of TIM8. + This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. + Replaces the obscure "output clock of TIM8." (CONFIG_TIM8_QECLKOUT). endif diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.c b/arch/arm/src/stm32l4/stm32l4_qencoder.c index 19436b2e18..647d151fb3 100644 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.c +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.c @@ -66,31 +66,6 @@ * Pre-processor Definitions ************************************************************************************/ /* Clocking *************************************************************************/ -/* The CLKOUT value should not exceed the CLKIN value */ - -#if defined(CONFIG_STM32L4_TIM1_QE) && CONFIG_STM32L4_TIM1_QECLKOUT > STM32L4_APB2_TIM1_CLKIN -# warning "CONFIG_STM32L4_TIM1_QECLKOUT exceeds STM32L4_APB2_TIM1_CLKIN" -#endif - -#if defined(CONFIG_STM32L4_TIM2_QE) && CONFIG_STM32L4_TIM2_QECLKOUT > STM32L4_APB1_TIM2_CLKIN -# warning "CONFIG_STM32L4_TIM2_QECLKOUT exceeds STM32L4_APB2_TIM2_CLKIN" -#endif - -#if defined(CONFIG_STM32L4_TIM3_QE) && CONFIG_STM32L4_TIM3_QECLKOUT > STM32L4_APB1_TIM3_CLKIN -# warning "CONFIG_STM32L4_TIM3_QECLKOUT exceeds STM32L4_APB2_TIM3_CLKIN" -#endif - -#if defined(CONFIG_STM32L4_TIM4_QE) && CONFIG_STM32L4_TIM4_QECLKOUT > STM32L4_APB1_TIM4_CLKIN -# warning "CONFIG_STM32L4_TIM4_QECLKOUT exceeds STM32L4_APB2_TIM4_CLKIN" -#endif - -#if defined(CONFIG_STM32L4_TIM5_QE) && CONFIG_STM32L4_TIM5_QECLKOUT > STM32L4_APB1_TIM5_CLKIN -# warning "CONFIG_STM32L4_TIM5_QECLKOUT exceeds STM32L4_APB2_TIM5_CLKIN" -#endif - -#if defined(CONFIG_STM32L4_TIM8_QE) && CONFIG_STM32L4_TIM8_QECLKOUT > STM32L4_APB2_TIM8_CLKIN -# warning "CONFIG_STM32L4_TIM8_QECLKOUT exceeds STM32L4_APB2_TIM8_CLKIN" -#endif /* Timers ***************************************************************************/ @@ -223,7 +198,7 @@ struct stm32l4_qeconfig_s uint32_t ti1cfg; /* TI1 input pin configuration (20-bit encoding) */ uint32_t ti2cfg; /* TI2 input pin configuration (20-bit encoding) */ uint32_t base; /* Register base address */ - uint32_t psc; /* Timer input clock prescaler */ + uint32_t psc; /* Encoder pulses prescaler */ xcpt_t handler; /* Interrupt handler for this IRQ */ }; @@ -323,7 +298,7 @@ static const struct stm32l4_qeconfig_s g_tim1config = .width = TIM1_BITWIDTH, #endif .base = STM32L4_TIM1_BASE, - .psc = (STM32L4_APB2_TIM1_CLKIN / CONFIG_STM32L4_TIM1_QECLKOUT) - 1, + .psc = CONFIG_STM32L4_TIM1_QEPSC, .ti1cfg = GPIO_TIM1_CH1IN, .ti2cfg = GPIO_TIM1_CH2IN, #if TIM1_BITWIDTH == 16 @@ -349,7 +324,7 @@ static const struct stm32l4_qeconfig_s g_tim2config = .width = TIM2_BITWIDTH, #endif .base = STM32L4_TIM2_BASE, - .psc = (STM32L4_APB1_TIM2_CLKIN / CONFIG_STM32L4_TIM2_QECLKOUT) - 1, + .psc = CONFIG_STM32L4_TIM2_QEPSC, .ti1cfg = GPIO_TIM2_CH1IN, .ti2cfg = GPIO_TIM2_CH2IN, #if TIM2_BITWIDTH == 16 @@ -375,7 +350,7 @@ static const struct stm32l4_qeconfig_s g_tim3config = .width = TIM3_BITWIDTH, #endif .base = STM32L4_TIM3_BASE, - .psc = (STM32L4_APB1_TIM3_CLKIN / CONFIG_STM32L4_TIM3_QECLKOUT) - 1, + .psc = CONFIG_STM32L4_TIM3_QEPSC, .ti1cfg = GPIO_TIM3_CH1IN, .ti2cfg = GPIO_TIM3_CH2IN, #if TIM3_BITWIDTH == 16 @@ -401,7 +376,7 @@ static const struct stm32l4_qeconfig_s g_tim4config = .width = TIM4_BITWIDTH, #endif .base = STM32L4_TIM4_BASE, - .psc = (STM32L4_APB1_TIM4_CLKIN / CONFIG_STM32L4_TIM4_QECLKOUT) - 1, + .psc = CONFIG_STM32L4_TIM4_QEPSC, .ti1cfg = GPIO_TIM4_CH1IN, .ti2cfg = GPIO_TIM4_CH2IN, #if TIM4_BITWIDTH == 16 @@ -427,7 +402,7 @@ static const struct stm32l4_qeconfig_s g_tim5config = .width = TIM5_BITWIDTH, #endif .base = STM32L4_TIM5_BASE, - .psc = (STM32L4_APB1_TIM5_CLKIN / CONFIG_STM32L4_TIM5_QECLKOUT) - 1, + .psc = CONFIG_STM32L4_TI55_QEPSC, .ti1cfg = GPIO_TIM5_CH1IN, .ti2cfg = GPIO_TIM5_CH2IN, #if TIM5_BITWIDTH == 16 @@ -453,7 +428,7 @@ static const struct stm32l4_qeconfig_s g_tim8config = .width = TIM8_BITWIDTH, #endif .base = STM32L4_TIM8_BASE, - .psc = (STM32L4_APB2_TIM8_CLKIN / CONFIG_STM32L4_TIM8_QECLKOUT) - 1, + .psc = CONFIG_STM32L4_TIM8_QEPSC, .ti1cfg = GPIO_TIM8_CH1IN, .ti2cfg = GPIO_TIM8_CH2IN, #if TIM8_BITWIDTH == 16 @@ -804,10 +779,23 @@ static int stm32l4_setup(FAR struct qe_lowerhalf_s *lower) stm32l4_putreg16(priv, STM32L4_GTIM_ARR_OFFSET, 0xffff); #endif - /* Set the timer prescaler value. The clock input value (CLKIN) is based on the - * peripheral clock (PCLK) and a multiplier. These CLKIN values are provided in - * the board.h file. The prescaler value is then that CLKIN value divided by the - * configured CLKOUT value (minus one) + /* Set the timer prescaler value. + * + * Previously, and still in the stm32fx driver, the clock input value (CLKIN) + * was based on the peripheral clock (PCLK) and a multiplier. + * These CLKIN values are provided in the board.h file. + * The prescaler value is then that CLKIN value divided by the configured + * CLKOUT value (minus one). + * + * It was determined that this configration makes no sense for a qencoder. + * If we are doing precise shaft positioning, each qe pulse is important. + * So the STM32L4 has direct config control on the pulse count prescaler, + * instead of deriving this value from an obscure "output"setting AND the + * timer input clock. This input clock just limits the incoming pulse rate, + * which should be lower than the peripheral clock due to resynchronization, + * but it is the responsibility of the system designer to decide the + * correct prescaler value, because it has a direct influence on the + * encoder resolution. */ stm32l4_putreg16(priv, STM32L4_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); @@ -1184,6 +1172,8 @@ static int stm32l4_ioctl(FAR struct qe_lowerhalf_s *lower, int cmd, unsigned lon { /* No ioctl commands supported */ + /* TODO add an IOCTL to control the encoder pulse count prescaler */ + return -ENOTTY; } -- GitLab From 98088a7456b8f6280dc5dd6bdfa8e05969b948b5 Mon Sep 17 00:00:00 2001 From: Sebastien Lorquet Date: Wed, 9 Nov 2016 19:52:29 +0100 Subject: [PATCH 393/734] typos --- arch/arm/src/stm32l4/stm32l4_qencoder.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.c b/arch/arm/src/stm32l4/stm32l4_qencoder.c index 647d151fb3..4e0ebb0283 100644 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.c +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.c @@ -402,7 +402,7 @@ static const struct stm32l4_qeconfig_s g_tim5config = .width = TIM5_BITWIDTH, #endif .base = STM32L4_TIM5_BASE, - .psc = CONFIG_STM32L4_TI55_QEPSC, + .psc = CONFIG_STM32L4_TIM5_QEPSC, .ti1cfg = GPIO_TIM5_CH1IN, .ti2cfg = GPIO_TIM5_CH2IN, #if TIM5_BITWIDTH == 16 @@ -787,10 +787,10 @@ static int stm32l4_setup(FAR struct qe_lowerhalf_s *lower) * The prescaler value is then that CLKIN value divided by the configured * CLKOUT value (minus one). * - * It was determined that this configration makes no sense for a qencoder. + * It was determined that this configuration makes no sense for a qencoder. * If we are doing precise shaft positioning, each qe pulse is important. * So the STM32L4 has direct config control on the pulse count prescaler, - * instead of deriving this value from an obscure "output"setting AND the + * instead of deriving this value from an obscure "output" setting AND the * timer input clock. This input clock just limits the incoming pulse rate, * which should be lower than the peripheral clock due to resynchronization, * but it is the responsibility of the system designer to decide the -- GitLab From b7ed12ebd38bf3c70b51d5b40ef71d0bbb1860e2 Mon Sep 17 00:00:00 2001 From: Juha Niskanen Date: Thu, 10 Nov 2016 06:09:57 -0600 Subject: [PATCH 394/734] Patch brings strtol() and related functions more conformant with POSIX. Corner cases like strtol(-2147483648, NULL, 10) now pass clang -fsanitize=integer without warnings. --- libc/stdlib/lib_strtol.c | 27 ++++++++++++++++++++++++--- libc/stdlib/lib_strtoll.c | 29 +++++++++++++++++++++++++---- libc/stdlib/lib_strtoul.c | 7 ++++--- libc/stdlib/lib_strtoull.c | 7 ++++--- 4 files changed, 57 insertions(+), 13 deletions(-) diff --git a/libc/stdlib/lib_strtol.c b/libc/stdlib/lib_strtol.c index 8c7f639901..2c6c6a24de 100644 --- a/libc/stdlib/lib_strtol.c +++ b/libc/stdlib/lib_strtol.c @@ -41,6 +41,7 @@ #include #include +#include #include "libc.h" @@ -60,7 +61,13 @@ * nptr to a long integer value according to the given base, which must be * between 2 and 36 inclusive, or be the special value 0. * - * Warning: does not check for integer overflow! + * Returns: + * - The converted value, if the base and number are valid + * - 0 if an error occurs, and set errno to: + * * EINVAL if base < 2 or base > 36 + * - LONG_MIN or LONG_MAX, of correct sign, if an overflow occurs, + * and set errno to: + * * ERANGE if the number cannot be represented using long * ****************************************************************************/ @@ -91,11 +98,25 @@ long strtol(FAR const char *nptr, FAR char **endptr, int base) accum = strtoul(nptr, endptr, base); - /* Correct the sign of the result */ + /* Correct the sign of the result and check for overflow */ if (negate) { - return -(long)accum; + const unsigned long limit = ((unsigned long)-(LONG_MIN + 1)) + 1; + + if (accum > limit) + { + set_errno(ERANGE); + return LONG_MIN; + } + + return (accum == limit) ? LONG_MIN : -(long)accum; + } + + if (accum > LONG_MAX) + { + set_errno(ERANGE); + return LONG_MAX; } } diff --git a/libc/stdlib/lib_strtoll.c b/libc/stdlib/lib_strtoll.c index bc8cc2eb6f..a5f8b2cdc3 100644 --- a/libc/stdlib/lib_strtoll.c +++ b/libc/stdlib/lib_strtoll.c @@ -41,6 +41,7 @@ #include #include +#include #include "libc.h" @@ -58,11 +59,17 @@ * Name: strtoll * * Description: - * The strtol() function converts the initial part of the string in + * The strtoll() function converts the initial part of the string in * nptr to a long long integer value according to the given base, which * must be between 2 and 36 inclusive, or be the special value 0. * - * Warning: does not check for integer overflow! + * Returns: + * - The converted value, if the base and number are valid + * - 0 if an error occurs, and set errno to: + * * EINVAL if base < 2 or base > 36 + * - LLONG_MIN or LLONG_MAX, of correct sign, if an overflow occurs, + * and set errno to: + * * ERANGE if the number cannot be represented using long long * ****************************************************************************/ @@ -93,11 +100,25 @@ long long strtoll(FAR const char *nptr, FAR char **endptr, int base) accum = strtoull(nptr, endptr, base); - /* Correct the sign of the result */ + /* Correct the sign of the result and check for overflow */ if (negate) { - return -(long long)accum; + const unsigned long long limit = ((unsigned long long)-(LLONG_MIN + 1)) + 1; + + if (accum > limit) + { + set_errno(ERANGE); + return LLONG_MIN; + } + + return (accum == limit) ? LLONG_MIN : -(long long)accum; + } + + if (accum > LLONG_MAX) + { + set_errno(ERANGE); + return LLONG_MAX; } } diff --git a/libc/stdlib/lib_strtoul.c b/libc/stdlib/lib_strtoul.c index 30ffbd31c3..1dec49e146 100644 --- a/libc/stdlib/lib_strtoul.c +++ b/libc/stdlib/lib_strtoul.c @@ -52,14 +52,15 @@ * Name: strtoul * * Description: - * The strtol() function converts the initial part of the string in + * The strtoul() function converts the initial part of the string in * nptr to a long unsigned integer value according to the given base, which * must be between 2 and 36 inclusive, or be the special value 0. * * Returns: * - The converted value, if the base and number are valid - * - 0 if an error occurs, and seterrno to: + * - 0 if an error occurs, and set errno to: * * EINVAL if base < 2 or base > 36 + * - ULONG_MAX if an overflow occurs, and set errno to: * * ERANGE if the number cannot be represented using unsigned long * ****************************************************************************/ @@ -99,7 +100,7 @@ unsigned long strtoul(FAR const char *nptr, FAR char **endptr, int base) if (accum < prev) { set_errno(ERANGE); - accum = 0; + accum = ULONG_MAX; break; } } diff --git a/libc/stdlib/lib_strtoull.c b/libc/stdlib/lib_strtoull.c index fab588891b..fe13b63249 100644 --- a/libc/stdlib/lib_strtoull.c +++ b/libc/stdlib/lib_strtoull.c @@ -55,14 +55,15 @@ * Name: strtoull * * Description: - * The strtol() function converts the initial part of the string in + * The strtoull() function converts the initial part of the string in * nptr to a long unsigned integer value according to the given base, which * must be between 2 and 36 inclusive, or be the special value 0. * * Returns: * - The converted value, if the base and number are valid - * - 0 if an error occurs, and seterrno to: + * - 0 if an error occurs, and set errno to: * * EINVAL if base < 2 or base > 36 + * - ULLONG_MAX if an overflow occurs, and set errno to: * * ERANGE if the number cannot be represented using unsigned long long * ****************************************************************************/ @@ -102,7 +103,7 @@ unsigned long long strtoull(FAR const char *nptr, FAR char **endptr, int base) if (accum < prev) { set_errno(ERANGE); - accum = 0; + accum = ULLONG_MAX; break; } } -- GitLab From f22c41c7cd3c927b8f9f0487e30dc9aa01b2fc6e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 12 Nov 2016 15:10:23 -0600 Subject: [PATCH 395/734] Updae README --- configs/esp32-core/README.txt | 56 +++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index 12fdbc4581..acdebf3cfc 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -19,6 +19,7 @@ Contents o STATUS o ESP32 Features o ESP32 Toolchain + o Memory Map o Serial Console o Buttons and LEDs o SMP @@ -79,6 +80,61 @@ ESP32 Toolchain NOTE: The xtensa-esp32-elf configuration is only available in the xtensa-1.22.x branch. +Memory Map +========== + + Embedded Memory + --------------- + BUS TYPE START LAST DESCRIPTION NOTES + Data 0x3ff80000 0x3ff81fff RTC FAST Memory PRO_CPU Only + 0x3ff82000 0x3ff8ffff Reserved + Data 0x3ff90000 0x3ff9ffff Internal ROM 1 + 0x3ffa0000 0x3ffadfff Reserved + Data 0x3ffae000 0x3ffdffff Internal SRAM 2 DMA + Data 0x3ffe0000 0x3fffffff Internal SRAM 1 DMA + + Boundary Address + ---------------- + BUS TYPE START LAST DESCRIPTION NOTES + Instruction 0x40000000 0x40007fff Internal ROM 0 Remap + Instruction 0x40008000 0x4005ffff Internal ROM 0 + 0x40060000 0x4006ffff Reserved + Instruction 0x40070000 0x4007ffff Internal SRAM 0 Cache + Instruction 0x40080000 0x4009ffff Internal SRAM 0 + Instruction 0x400a0000 0x400affff Internal SRAM 1 + Instruction 0x400b0000 0x400b7FFF Internal SRAM 1 Remap + Instruction 0x400b8000 0x400bffff Internal SRAM 1 + Instruction 0x400c0000 0x400c1FFF RTC FAST Memory PRO_CPU Only + Data / 0x50000000 0x50001fff RTC SLOW Memory + Instruction + + External Memory + --------------- + BUS TYPE START LAST DESCRIPTION NOTES + Data 0x3f400000 0x3f7fffff External Flash Read + Data 0x3f800000 0x3fbfffff External SRAM Read and Write + + Boundary Address + ---------------- + Instruction 0x400c2000 0x40bfffff 11512 KB External Flash Read + + Linker Segments + --------------- + DESCRIPTION START END ATTR LINKER SEGMENT NAME + FLASH mapped data: 0x3f400010 - 0x3fc00010 R dram_0_seg + COMMON data RAM: 0x3ffb0000 - 0x40000000 RW dram_0_seg (NOTE 1,2) + IRAM for PRO cpu: 0x40080000 - 0x400a0000 RX iram0_0_seg + RTC fast memory: 0x400c0000 - 0x400c2000 RWX rtc_iram_seg + FLASH: 0x400d0018 - 0x40400018 RX iram0_2_seg (actually FLASH) + RTC slow memory: 0x50000000 - 0x50001000 RW rtc_slow_seg (NOTE 3) + + NOTE 1: Linker script will reserved space at the beginning of the segment + for BT and at the end for trace memory. + NOTE 2: Heap enads at the top of dram0_0_seg + NOTE 3: Linker script will reserved space at the beginning of the segment + for co-processor reserve memory and at the end for ULP coprocessor + reserve memory. + Serial Console ============== -- GitLab From e87f1360c6722e1c5401212a79cb73ab0227c949 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 12 Nov 2016 15:51:14 -0600 Subject: [PATCH 396/734] Update README --- configs/esp32-core/README.txt | 43 ++++++++++++++++++++++++++--------- 1 file changed, 32 insertions(+), 11 deletions(-) diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index acdebf3cfc..6d7e09c4b6 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -83,9 +83,27 @@ ESP32 Toolchain Memory Map ========== + Address Mapping + ----------- ---------- ---------- --------------- --------------- + BUS TYPE START LAST DESCRIPTION NOTES + ----------- ---------- ---------- --------------- --------------- + 0x00000000 0x3F3FFFFF Reserved + Data 0x3F400000 0x3F7FFFFF External Memory + Data 0x3F800000 0x3FBFFFFF External Memory + 0x3FC00000 0x3FEFFFFF Reserved + Data 0x3FF00000 0x3FF7FFFF Peripheral + Data 0x3FF80000 0x3FFFFFFF Embedded Memory + Instruction 0x40000000 0x400C1FFF Embedded Memory + Instruction 0x400C2000 0x40BFFFFF External Memory + 0x40C00000 0x4FFFFFFF Reserved + Data / 0x50000000 0x50001FFF Embedded Memory + Instruction + 0x50002000 0xFFFFFFFF Reserved + Embedded Memory - --------------- + ----------- ---------- ---------- --------------- --------------- BUS TYPE START LAST DESCRIPTION NOTES + ----------- ---------- ---------- --------------- --------------- Data 0x3ff80000 0x3ff81fff RTC FAST Memory PRO_CPU Only 0x3ff82000 0x3ff8ffff Reserved Data 0x3ff90000 0x3ff9ffff Internal ROM 1 @@ -94,8 +112,9 @@ Memory Map Data 0x3ffe0000 0x3fffffff Internal SRAM 1 DMA Boundary Address - ---------------- + ----------- ---------- ---------- --------------- --------------- BUS TYPE START LAST DESCRIPTION NOTES + ----------- ---------- ---------- --------------- --------------- Instruction 0x40000000 0x40007fff Internal ROM 0 Remap Instruction 0x40008000 0x4005ffff Internal ROM 0 0x40060000 0x4006ffff Reserved @@ -109,8 +128,9 @@ Memory Map Instruction External Memory - --------------- + ----------- ---------- ---------- --------------- --------------- BUS TYPE START LAST DESCRIPTION NOTES + ----------- ---------- ---------- --------------- --------------- Data 0x3f400000 0x3f7fffff External Flash Read Data 0x3f800000 0x3fbfffff External SRAM Read and Write @@ -119,14 +139,15 @@ Memory Map Instruction 0x400c2000 0x40bfffff 11512 KB External Flash Read Linker Segments - --------------- - DESCRIPTION START END ATTR LINKER SEGMENT NAME - FLASH mapped data: 0x3f400010 - 0x3fc00010 R dram_0_seg - COMMON data RAM: 0x3ffb0000 - 0x40000000 RW dram_0_seg (NOTE 1,2) - IRAM for PRO cpu: 0x40080000 - 0x400a0000 RX iram0_0_seg - RTC fast memory: 0x400c0000 - 0x400c2000 RWX rtc_iram_seg - FLASH: 0x400d0018 - 0x40400018 RX iram0_2_seg (actually FLASH) - RTC slow memory: 0x50000000 - 0x50001000 RW rtc_slow_seg (NOTE 3) + ------------------ ---------- ---------- ---- ---------------------------- + DESCRIPTION START END ATTR LINKER SEGMENT NAME + ------------------ ---------- ---------- ---- ---------------------------- + FLASH mapped data: 0x3f400010 0x3fc00010 R dram_0_seg + COMMON data RAM: 0x3ffb0000 0x40000000 RW dram_0_seg (NOTE 1,2) + IRAM for PRO cpu: 0x40080000 0x400a0000 RX iram0_0_seg + RTC fast memory: 0x400c0000 0x400c2000 RWX rtc_iram_seg + FLASH: 0x400d0018 0x40400018 RX iram0_2_seg (actually FLASH) + RTC slow memory: 0x50000000 0x50001000 RW rtc_slow_seg (NOTE 3) NOTE 1: Linker script will reserved space at the beginning of the segment for BT and at the end for trace memory. -- GitLab From 102abb380d6106676cc46685accd2c83bad7c191 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 13 Nov 2016 07:55:34 -0600 Subject: [PATCH 397/734] Update README --- configs/esp32-core/README.txt | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index 6d7e09c4b6..75fcf9442a 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -149,10 +149,10 @@ Memory Map FLASH: 0x400d0018 0x40400018 RX iram0_2_seg (actually FLASH) RTC slow memory: 0x50000000 0x50001000 RW rtc_slow_seg (NOTE 3) - NOTE 1: Linker script will reserved space at the beginning of the segment + NOTE 1: Linker script will reserve space at the beginning of the segment for BT and at the end for trace memory. NOTE 2: Heap enads at the top of dram0_0_seg - NOTE 3: Linker script will reserved space at the beginning of the segment + NOTE 3: Linker script will reserve space at the beginning of the segment for co-processor reserve memory and at the end for ULP coprocessor reserve memory. @@ -330,10 +330,12 @@ Things to Do ============ 1. There is no support for an interrupt stack yet. + 2. There is no clock intialization logic in place. This depends on logic in Expressif libriaries. The board comes up using that basic 40 Mhz crystal for clocking. Getting to 80 MHz will require clocking initialization in esp32_clockconfig.c. + 3. I did not implement the lazy co-processor save logic supported by Xtensa. That logic works like this: @@ -344,7 +346,9 @@ Things to Do c. The co-processor exception handler re-enables the co-processor. Instead, the NuttX logic saves and restores CPENABLE on each context - switch. + switch. This has disadvantages in that (1) co-processor context will + be saved and restored even if the co-processor was never used, and (2) + tasks must explicitly enable and disable co-processors. 4. Currently the Xtensa port copies register state save information from the stack into the TCB. A more efficient alternative would be to just -- GitLab From c7b5f20b5de82ddfc015be6e788700051bc55947 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 13 Nov 2016 09:30:45 -0600 Subject: [PATCH 398/734] Update README --- configs/esp32-core/README.txt | 132 +++++++++++++++++++++++++--------- 1 file changed, 97 insertions(+), 35 deletions(-) diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index 75fcf9442a..579978d1d7 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -142,16 +142,25 @@ Memory Map ------------------ ---------- ---------- ---- ---------------------------- DESCRIPTION START END ATTR LINKER SEGMENT NAME ------------------ ---------- ---------- ---- ---------------------------- - FLASH mapped data: 0x3f400010 0x3fc00010 R dram_0_seg - COMMON data RAM: 0x3ffb0000 0x40000000 RW dram_0_seg (NOTE 1,2) + FLASH mapped data: 0x3f400010 0x3fc00010 R drom0_0_seg + - .rodata + - Constructors/destructors + COMMON data RAM: 0x3ffb0000 0x40000000 RW dram0_0_seg (NOTE 1,2) + - .bss/.data IRAM for PRO cpu: 0x40080000 0x400a0000 RX iram0_0_seg - RTC fast memory: 0x400c0000 0x400c2000 RWX rtc_iram_seg - FLASH: 0x400d0018 0x40400018 RX iram0_2_seg (actually FLASH) + - Interrupt Vectors + - Low level handlers + - Xtensa/Expressif libraries + RTC fast memory: 0x400c0000 0x400c2000 RWX rtc_iram_seg (PRO_CPU only) + - .rtc.text (unused?) + FLASH: 0x400d0018 0x40400018 RX iram0_2_seg (actually FLASH) + - .text RTC slow memory: 0x50000000 0x50001000 RW rtc_slow_seg (NOTE 3) + - .rtc.data/rodata (unused?) NOTE 1: Linker script will reserve space at the beginning of the segment for BT and at the end for trace memory. - NOTE 2: Heap enads at the top of dram0_0_seg + NOTE 2: Heap enads at the top of dram_0_seg NOTE 3: Linker script will reserve space at the beginning of the segment for co-processor reserve memory and at the end for ULP coprocessor reserve memory. @@ -216,18 +225,50 @@ SMP Debug Issues ============ - I basically need the debug environment and a step-by-step procedure. + You basically need the debug environment and a step-by-step procedure. - First in need some debug environment which would be a JTAG emulator - and software. - - - I don't see any way to connect JTAG to the ESP32 Core V2 board. There - is a USB/Serial converter chip, but that does not look like it - supports JTAG. - - It may be necessary to make cable. Refer to - http://www.esp32.com/viewtopic.php?t=381 "How to debug ESP32 with - JTAG / OpenOCD / GDB 1st part connect the hardware." + and the ESP32 OpenOCD software which is available here: + https://github.com/espressif/openocd-esp32 + + - There is on overiew of the use of OpenOCD here: + https://dl.espressif.com/doc/esp-idf/latest/openocd.html + This document is also available in ESP-IDF source tree in docs + directory (https://github.com/espressif/esp-idf). + + A template ESP32 OpenOCD configuration file is provided in + ESP-IDF docs directory (esp32.cfg). Since you are not using + FreeRTOS, you will need to uncomment the "set ESP32_RTOS none" + line in OpenOCD configuration file. + + The documentation indicates that you need to use an external JTAG + like the TIAO USB Multi-protocol Adapter and the Flyswatter2. + The instructions at http://www.esp32.com/viewtopic.php?t=381 show + use of an FTDI C232HM-DDHSL-0 USB 2.0 high speed to MPSSE cable. + + - The ESP32 Core v2 board has no on board JTAG connector. It will + be necessary to make a cable or some other board to connect a JTAG + emulator. Refer to http://www.esp32.com/viewtopic.php?t=381 "How + to debug ESP32 with JTAG / OpenOCD / GDB 1st part connect the + hardware." + + Relevant pin-out: + + -------- ---------- + PIN JTAG + LABEL FUNCTION + -------- ---------- + IO14 TMS + IO12 TDI + GND GND + IO13 TCK + -------- ---------- + IO15 TDO + -------- ---------- + + You can find the mapping of JTAG signals to ESP32 GPIO numbers in + "ESP32 Pin List" document found here: + http://espressif.com/en/support/download/documents?keys=&field_type_tid%5B%5D=13 - I need to understand how to use the secondary bootloader. My understanding is that it will configure hardware, read a partition @@ -237,26 +278,47 @@ Debug Issues - Do I need to create a partition table at 0x5000? Should this be part of the NuttX build? - I see https://github.com/espressif/esp-idf/tree/master/components/bootloader - and https://github.com/espressif/esp-idf/tree/master/components/partition_table. - I suppose some of what I need is in there, but I am not sure what I am - looking at right now. - - There is an OpenOCD port here: https://github.com/espressif/openocd-esp32 - and I see some additional OpenOCD documentation in - https://github.com/espressif/esp-idf/tree/master/docs. This documentation - raises some more questions. It says I need to use and external JTAG like - the TIAO USB Multi-protocol Adapter and the Flyswatter2. I don't have - either of those. I am not sure if I have any USB serial JTAG. I have some - older ones that might work, however. - - My understanding when I started this was that I could use my trusty Segger - J-Link. But that won't work with OpenOCD. Is the J-Link that also a - possibility? - - I also see that I can now get an ESP32 board from Sparkfun: - https://www.sparkfun.com/products/13907 But I don't see JTAG there either: - https://cdn.sparkfun.com/assets/learn_tutorials/5/0/7/esp32-thing-schematic.pdf + See https://github.com/espressif/esp-idf/tree/master/components/bootloader + and https://github.com/espressif/esp-idf/tree/master/components/partition_table. + I suppose some of what I need is in there, but I am not sure what I am + looking at right now. + + It is possible to skip the secondary bootloader and run out of IRAM using + only the primary bootloader if your application of small enough (< 128KiB code, + <180KiB data), then you can simplify initial bring-up by avoiding second stage + bootloader. Your application will be loaded into IRAM using first stage + bootloader present in ESP32 ROM. To achieve this, you need two things: + + 1. Have a linker script which places all code into IRAM and all data into DRAM + + 2. Use "esptool.py" utility found in ESP-IDF to convert application .elf file + into binary format which can be loaded by first stage bootloader. + + The default linker script in ESP-IDF places most code into memory-mapped flash: + https://github.com/espressif/esp-idf/blob/master/components/esp32/ld/esp32.common.ld#L178-L186 + + You would need to remove this section and move its contents into the end of .iram0.text section: + https://github.com/espressif/esp-idf/blob/master/components/esp32/ld/esp32.common.ld#L85 + + Same with constant data: move contents of .flash.rodata section: + https://github.com/espressif/esp-idf/blob/master/components/esp32/ld/esp32.common.ld#L134-L173 + + into the end of .dram0.data section (before _heap_start): + https://github.com/espressif/esp-idf/blob/master/components/esp32/ld/esp32.common.ld#L128 + + With these modifications, all code and data should be moved into IRAM/DRAM. Next, you would + need to link the ELF file and convert it to binary format suitable for flashing into the + board. The xommand should to convert ELF file to binary image looks as follows: + + python esp-idf/components/esptool_py/esptool/esptool.py --chip esp32 elf2image --flash_mode "dio" --flash_freq "40m" --flash_size "2MB" -o app.bin app.elf + + To flash binary image to your development board, use the same esptool.py utility: + + python esp-idf/components/esptool_py/esptool/esptool.py --chip esp32 --port /dev/ttyUSB0 --baud 921600 write_flash -z --flash_mode dio --flash_freq 40m --flash_size 2MB 0x1000 app.bin + + The argument before app.bin (0x1000) indicates the offset in flash where binary + will be written. ROM bootloader expects to find an application (or second stage + bootloader) image at offset 0x1000, so we are writing the binary there. Right now, the NuttX port depends on the bootloader to initialize hardware, including basic (slow) clocking. If I had the clock configuration logic, -- GitLab From a6b7730f8c04e34361ccd93cef00e59322c0c8a2 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Sun, 13 Nov 2016 11:44:28 -0600 Subject: [PATCH 399/734] Add Vishay VEML6070 driver and support for STM32F103-Minimum board --- configs/stm32f103-minimum/README.txt | 6 + configs/stm32f103-minimum/src/Makefile | 4 + configs/stm32f103-minimum/src/stm32_bringup.c | 10 + .../stm32f103-minimum/src/stm32_veml6070.c | 105 ++ .../stm32f103-minimum/src/stm32f103_minimum.h | 13 + configs/stm32f103-minimum/veml6070/Make.defs | 113 ++ configs/stm32f103-minimum/veml6070/defconfig | 1201 +++++++++++++++++ configs/stm32f103-minimum/veml6070/setenv.sh | 100 ++ drivers/sensors/Kconfig | 7 + drivers/sensors/Make.defs | 6 + drivers/sensors/veml6070.c | 352 +++++ include/nuttx/sensors/veml6070.h | 121 ++ 12 files changed, 2038 insertions(+) create mode 100644 configs/stm32f103-minimum/src/stm32_veml6070.c create mode 100644 configs/stm32f103-minimum/veml6070/Make.defs create mode 100644 configs/stm32f103-minimum/veml6070/defconfig create mode 100644 configs/stm32f103-minimum/veml6070/setenv.sh create mode 100644 drivers/sensors/veml6070.c create mode 100644 include/nuttx/sensors/veml6070.h diff --git a/configs/stm32f103-minimum/README.txt b/configs/stm32f103-minimum/README.txt index 145f6af0e4..112182b032 100644 --- a/configs/stm32f103-minimum/README.txt +++ b/configs/stm32f103-minimum/README.txt @@ -636,3 +636,9 @@ Where is one of the following: CONFIG_CDCACM_CONSOLE=y : The CDC/ACM serial device is NOT the console CONFIG_PL2303=y : The Prolifics PL2303 emulation is enabled CONFIG_PL2303_CONSOLE=y : The PL2303 serial device is the console + + veml6070: + -------- + This is a config example to use the Vishay VEML6070 UV-A sensor. To use this + sensor you need to connect PB6 (I2C1 CLK) to SCL; PB7 (I2C1 SDA) to SDA of + sensor module. I used a GY-VEML6070 module to test this driver. diff --git a/configs/stm32f103-minimum/src/Makefile b/configs/stm32f103-minimum/src/Makefile index 3baf4b64dc..4ecd9086ae 100644 --- a/configs/stm32f103-minimum/src/Makefile +++ b/configs/stm32f103-minimum/src/Makefile @@ -73,4 +73,8 @@ ifeq ($(CONFIG_LCD_ST7567),y) CSRCS += stm32_lcd.c endif +ifeq ($(CONFIG_VEML6070),y) +CSRCS += stm32_veml6070.c +endif + include $(TOPDIR)/configs/Board.mk diff --git a/configs/stm32f103-minimum/src/stm32_bringup.c b/configs/stm32f103-minimum/src/stm32_bringup.c index 7c81c59c07..ed1cd3d415 100644 --- a/configs/stm32f103-minimum/src/stm32_bringup.c +++ b/configs/stm32f103-minimum/src/stm32_bringup.c @@ -163,5 +163,15 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_VEML6070 + /* Register the UV-A light sensor */ + + ret = stm32_veml6070initialize("/dev/uvlight0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_veml6070initialize() failed: %d\n", ret); + } +#endif + return ret; } diff --git a/configs/stm32f103-minimum/src/stm32_veml6070.c b/configs/stm32f103-minimum/src/stm32_veml6070.c new file mode 100644 index 0000000000..72c6583bbc --- /dev/null +++ b/configs/stm32f103-minimum/src/stm32_veml6070.c @@ -0,0 +1,105 @@ +/************************************************************************************ + * configs/stm32f103-minimum/src/stm32_veml6070.c + * + * Copyright (C) 2016 Alan Carvalho de Assis. All rights reserved. + * Author: Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32_i2c.h" +#include "stm32f103_minimum.h" + +#if defined(CONFIG_I2C) && defined(CONFIG_VEML6070) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#define VEML6070_I2C_PORTNO 1 /* On I2C1 */ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_veml6070initialize + * + * Description: + * Initialize and register the VEML6070 UV-A Light sensor. + * + * Input parameters: + * devpath - The full path to the driver to register. E.g., "/dev/uvlight0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ************************************************************************************/ + +int stm32_veml6070initialize(FAR const char *devpath) +{ + FAR struct i2c_master_s *i2c; + int ret; + + sninfo("Initializing VEML6070!\n"); + + /* Initialize I2C */ + + i2c = stm32_i2cbus_initialize(VEML6070_I2C_PORTNO); + + if (!i2c) + { + return -ENODEV; + } + + /* Then register the light sensor */ + + ret = veml6070_register(devpath, i2c, VEML6070_I2C_DATA_LSB_CMD_ADDR); + if (ret < 0) + { + snerr("ERROR: Error registering BM180\n"); + } + + return ret; +} + +#endif /* CONFIG_I2C && CONFIG_VEML6070 && CONFIG_STM32_I2C1 */ diff --git a/configs/stm32f103-minimum/src/stm32f103_minimum.h b/configs/stm32f103-minimum/src/stm32f103_minimum.h index b3d4ff0a91..7b0f69ddf3 100644 --- a/configs/stm32f103-minimum/src/stm32f103_minimum.h +++ b/configs/stm32f103-minimum/src/stm32f103_minimum.h @@ -192,5 +192,18 @@ int stm32_mfrc522initialize(FAR const char *devpath); int stm32_tone_setup(void); #endif +/*********************************************************************************** + * Name: stm32_veml6070initialize + * + * Description: + * Called to configure an I2C and to register VEML6070 for the stm32f103-minimum + * board. + * + ***********************************************************************************/ + +#ifdef CONFIG_VEML6070 +int stm32_veml6070initialize(FAR const char *devpath); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_STM32F103_MINIMUM_SRC_STM32F103_MINIMUM_H */ diff --git a/configs/stm32f103-minimum/veml6070/Make.defs b/configs/stm32f103-minimum/veml6070/Make.defs new file mode 100644 index 0000000000..c6d573f6ea --- /dev/null +++ b/configs/stm32f103-minimum/veml6070/Make.defs @@ -0,0 +1,113 @@ +############################################################################ +# configs/stm32f103-minimum/vem6070/Make.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/stm32f103-minimum/veml6070/defconfig b/configs/stm32f103-minimum/veml6070/defconfig new file mode 100644 index 0000000000..fa44438359 --- /dev/null +++ b/configs/stm32f103-minimum/veml6070/defconfig @@ -0,0 +1,1201 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_DEFAULT_SMALL=y +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +CONFIG_ARCH_HAVE_HEAPCHECK=y +# CONFIG_HEAP_COLORATION is not set +# CONFIG_DEBUG_SYMBOLS is not set +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +CONFIG_ARCH_CHIP_STM32=y +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +CONFIG_ARCH_CORTEXM3=y +# CONFIG_ARCH_CORTEXM4 is not set +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="stm32" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARMV7M_LAZYFPU is not set +# CONFIG_ARCH_HAVE_FPU is not set +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set +# CONFIG_DEBUG_HARDFAULT is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y +CONFIG_ARMV7M_HAVE_STACKCHECK=y +# CONFIG_ARMV7M_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set +CONFIG_SERIAL_TERMIOS=y + +# +# STM32 Configuration Options +# +# CONFIG_ARCH_CHIP_STM32L151C6 is not set +# CONFIG_ARCH_CHIP_STM32L151C8 is not set +# CONFIG_ARCH_CHIP_STM32L151CB is not set +# CONFIG_ARCH_CHIP_STM32L151R6 is not set +# CONFIG_ARCH_CHIP_STM32L151R8 is not set +# CONFIG_ARCH_CHIP_STM32L151RB is not set +# CONFIG_ARCH_CHIP_STM32L151V6 is not set +# CONFIG_ARCH_CHIP_STM32L151V8 is not set +# CONFIG_ARCH_CHIP_STM32L151VB is not set +# CONFIG_ARCH_CHIP_STM32L152C6 is not set +# CONFIG_ARCH_CHIP_STM32L152C8 is not set +# CONFIG_ARCH_CHIP_STM32L152CB is not set +# CONFIG_ARCH_CHIP_STM32L152R6 is not set +# CONFIG_ARCH_CHIP_STM32L152R8 is not set +# CONFIG_ARCH_CHIP_STM32L152RB is not set +# CONFIG_ARCH_CHIP_STM32L152V6 is not set +# CONFIG_ARCH_CHIP_STM32L152V8 is not set +# CONFIG_ARCH_CHIP_STM32L152VB is not set +# CONFIG_ARCH_CHIP_STM32L162ZD is not set +# CONFIG_ARCH_CHIP_STM32L162VE is not set +# CONFIG_ARCH_CHIP_STM32F100C8 is not set +# CONFIG_ARCH_CHIP_STM32F100CB is not set +# CONFIG_ARCH_CHIP_STM32F100R8 is not set +# CONFIG_ARCH_CHIP_STM32F100RB is not set +# CONFIG_ARCH_CHIP_STM32F100RC is not set +# CONFIG_ARCH_CHIP_STM32F100RD is not set +# CONFIG_ARCH_CHIP_STM32F100RE is not set +# CONFIG_ARCH_CHIP_STM32F100V8 is not set +# CONFIG_ARCH_CHIP_STM32F100VB is not set +# CONFIG_ARCH_CHIP_STM32F100VC is not set +# CONFIG_ARCH_CHIP_STM32F100VD is not set +# CONFIG_ARCH_CHIP_STM32F100VE is not set +# CONFIG_ARCH_CHIP_STM32F102CB is not set +# CONFIG_ARCH_CHIP_STM32F103T8 is not set +# CONFIG_ARCH_CHIP_STM32F103TB is not set +# CONFIG_ARCH_CHIP_STM32F103C4 is not set +CONFIG_ARCH_CHIP_STM32F103C8=y +# CONFIG_ARCH_CHIP_STM32F103CB is not set +# CONFIG_ARCH_CHIP_STM32F103R8 is not set +# CONFIG_ARCH_CHIP_STM32F103RB is not set +# CONFIG_ARCH_CHIP_STM32F103RC is not set +# CONFIG_ARCH_CHIP_STM32F103RD is not set +# CONFIG_ARCH_CHIP_STM32F103RE is not set +# CONFIG_ARCH_CHIP_STM32F103RG is not set +# CONFIG_ARCH_CHIP_STM32F103V8 is not set +# CONFIG_ARCH_CHIP_STM32F103VB is not set +# CONFIG_ARCH_CHIP_STM32F103VC is not set +# CONFIG_ARCH_CHIP_STM32F103VE is not set +# CONFIG_ARCH_CHIP_STM32F103ZE is not set +# CONFIG_ARCH_CHIP_STM32F105VB is not set +# CONFIG_ARCH_CHIP_STM32F105RB is not set +# CONFIG_ARCH_CHIP_STM32F107VC is not set +# CONFIG_ARCH_CHIP_STM32F205RG is not set +# CONFIG_ARCH_CHIP_STM32F207IG is not set +# CONFIG_ARCH_CHIP_STM32F207ZE is not set +# CONFIG_ARCH_CHIP_STM32F302K6 is not set +# CONFIG_ARCH_CHIP_STM32F302K8 is not set +# CONFIG_ARCH_CHIP_STM32F302CB is not set +# CONFIG_ARCH_CHIP_STM32F302CC is not set +# CONFIG_ARCH_CHIP_STM32F302RB is not set +# CONFIG_ARCH_CHIP_STM32F302RC is not set +# CONFIG_ARCH_CHIP_STM32F302VB is not set +# CONFIG_ARCH_CHIP_STM32F302VC is not set +# CONFIG_ARCH_CHIP_STM32F303K6 is not set +# CONFIG_ARCH_CHIP_STM32F303K8 is not set +# CONFIG_ARCH_CHIP_STM32F303C6 is not set +# CONFIG_ARCH_CHIP_STM32F303C8 is not set +# CONFIG_ARCH_CHIP_STM32F303CB is not set +# CONFIG_ARCH_CHIP_STM32F303CC is not set +# CONFIG_ARCH_CHIP_STM32F303RB is not set +# CONFIG_ARCH_CHIP_STM32F303RC is not set +# CONFIG_ARCH_CHIP_STM32F303RD is not set +# CONFIG_ARCH_CHIP_STM32F303RE is not set +# CONFIG_ARCH_CHIP_STM32F303VB is not set +# CONFIG_ARCH_CHIP_STM32F303VC is not set +# CONFIG_ARCH_CHIP_STM32F372C8 is not set +# CONFIG_ARCH_CHIP_STM32F372R8 is not set +# CONFIG_ARCH_CHIP_STM32F372V8 is not set +# CONFIG_ARCH_CHIP_STM32F372CB is not set +# CONFIG_ARCH_CHIP_STM32F372RB is not set +# CONFIG_ARCH_CHIP_STM32F372VB is not set +# CONFIG_ARCH_CHIP_STM32F372CC is not set +# CONFIG_ARCH_CHIP_STM32F372RC is not set +# CONFIG_ARCH_CHIP_STM32F372VC is not set +# CONFIG_ARCH_CHIP_STM32F373C8 is not set +# CONFIG_ARCH_CHIP_STM32F373R8 is not set +# CONFIG_ARCH_CHIP_STM32F373V8 is not set +# CONFIG_ARCH_CHIP_STM32F373CB is not set +# CONFIG_ARCH_CHIP_STM32F373RB is not set +# CONFIG_ARCH_CHIP_STM32F373VB is not set +# CONFIG_ARCH_CHIP_STM32F373CC is not set +# CONFIG_ARCH_CHIP_STM32F373RC is not set +# CONFIG_ARCH_CHIP_STM32F373VC is not set +# CONFIG_ARCH_CHIP_STM32F401RE is not set +# CONFIG_ARCH_CHIP_STM32F411RE is not set +# CONFIG_ARCH_CHIP_STM32F411VE is not set +# CONFIG_ARCH_CHIP_STM32F405RG is not set +# CONFIG_ARCH_CHIP_STM32F405VG is not set +# CONFIG_ARCH_CHIP_STM32F405ZG is not set +# CONFIG_ARCH_CHIP_STM32F407VE is not set +# CONFIG_ARCH_CHIP_STM32F407VG is not set +# CONFIG_ARCH_CHIP_STM32F407ZE is not set +# CONFIG_ARCH_CHIP_STM32F407ZG is not set +# CONFIG_ARCH_CHIP_STM32F407IE is not set +# CONFIG_ARCH_CHIP_STM32F407IG is not set +# CONFIG_ARCH_CHIP_STM32F427V is not set +# CONFIG_ARCH_CHIP_STM32F427Z is not set +# CONFIG_ARCH_CHIP_STM32F427I is not set +# CONFIG_ARCH_CHIP_STM32F429V is not set +# CONFIG_ARCH_CHIP_STM32F429Z is not set +# CONFIG_ARCH_CHIP_STM32F429I is not set +# CONFIG_ARCH_CHIP_STM32F429B is not set +# CONFIG_ARCH_CHIP_STM32F429N is not set +# CONFIG_ARCH_CHIP_STM32F446M is not set +# CONFIG_ARCH_CHIP_STM32F446R is not set +# CONFIG_ARCH_CHIP_STM32F446V is not set +# CONFIG_ARCH_CHIP_STM32F446Z is not set +# CONFIG_ARCH_CHIP_STM32F469A is not set +# CONFIG_ARCH_CHIP_STM32F469I is not set +# CONFIG_ARCH_CHIP_STM32F469B is not set +# CONFIG_ARCH_CHIP_STM32F469N is not set +CONFIG_STM32_FLASH_CONFIG_DEFAULT=y +# CONFIG_STM32_FLASH_CONFIG_4 is not set +# CONFIG_STM32_FLASH_CONFIG_6 is not set +# CONFIG_STM32_FLASH_CONFIG_8 is not set +# CONFIG_STM32_FLASH_CONFIG_B is not set +# CONFIG_STM32_FLASH_CONFIG_C is not set +# CONFIG_STM32_FLASH_CONFIG_D is not set +# CONFIG_STM32_FLASH_CONFIG_E is not set +# CONFIG_STM32_FLASH_CONFIG_F is not set +# CONFIG_STM32_FLASH_CONFIG_G is not set +# CONFIG_STM32_FLASH_CONFIG_I is not set +# CONFIG_STM32_STM32L15XX is not set +# CONFIG_STM32_ENERGYLITE is not set +CONFIG_STM32_STM32F10XX=y +# CONFIG_STM32_VALUELINE is not set +# CONFIG_STM32_CONNECTIVITYLINE is not set +CONFIG_STM32_PERFORMANCELINE=y +# CONFIG_STM32_USBACCESSLINE is not set +# CONFIG_STM32_HIGHDENSITY is not set +CONFIG_STM32_MEDIUMDENSITY=y +# CONFIG_STM32_LOWDENSITY is not set +# CONFIG_STM32_STM32F20XX is not set +# CONFIG_STM32_STM32F205 is not set +# CONFIG_STM32_STM32F207 is not set +# CONFIG_STM32_STM32F30XX is not set +# CONFIG_STM32_STM32F302 is not set +# CONFIG_STM32_STM32F303 is not set +# CONFIG_STM32_STM32F37XX is not set +# CONFIG_STM32_STM32F40XX is not set +# CONFIG_STM32_STM32F401 is not set +# CONFIG_STM32_STM32F411 is not set +# CONFIG_STM32_STM32F405 is not set +# CONFIG_STM32_STM32F407 is not set +# CONFIG_STM32_STM32F427 is not set +# CONFIG_STM32_STM32F429 is not set +# CONFIG_STM32_STM32F446 is not set +# CONFIG_STM32_STM32F469 is not set +# CONFIG_STM32_DFU is not set + +# +# STM32 Peripheral Support +# +# CONFIG_STM32_HAVE_CCM is not set +CONFIG_STM32_HAVE_USBDEV=y +# CONFIG_STM32_HAVE_OTGFS is not set +# CONFIG_STM32_HAVE_FSMC is not set +# CONFIG_STM32_HAVE_LTDC is not set +CONFIG_STM32_HAVE_USART3=y +CONFIG_STM32_HAVE_UART4=y +CONFIG_STM32_HAVE_UART5=y +# CONFIG_STM32_HAVE_USART6 is not set +# CONFIG_STM32_HAVE_UART7 is not set +# CONFIG_STM32_HAVE_UART8 is not set +CONFIG_STM32_HAVE_TIM1=y +# CONFIG_STM32_HAVE_TIM2 is not set +CONFIG_STM32_HAVE_TIM3=y +CONFIG_STM32_HAVE_TIM4=y +CONFIG_STM32_HAVE_TIM5=y +CONFIG_STM32_HAVE_TIM6=y +CONFIG_STM32_HAVE_TIM7=y +CONFIG_STM32_HAVE_TIM8=y +# CONFIG_STM32_HAVE_TIM9 is not set +# CONFIG_STM32_HAVE_TIM10 is not set +# CONFIG_STM32_HAVE_TIM11 is not set +# CONFIG_STM32_HAVE_TIM12 is not set +# CONFIG_STM32_HAVE_TIM13 is not set +# CONFIG_STM32_HAVE_TIM14 is not set +# CONFIG_STM32_HAVE_TIM15 is not set +# CONFIG_STM32_HAVE_TIM16 is not set +# CONFIG_STM32_HAVE_TIM17 is not set +CONFIG_STM32_HAVE_ADC2=y +CONFIG_STM32_HAVE_ADC3=y +# CONFIG_STM32_HAVE_ADC4 is not set +# CONFIG_STM32_HAVE_ADC1_DMA is not set +# CONFIG_STM32_HAVE_ADC2_DMA is not set +# CONFIG_STM32_HAVE_ADC3_DMA is not set +# CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set +CONFIG_STM32_HAVE_CAN1=y +# CONFIG_STM32_HAVE_CAN2 is not set +# CONFIG_STM32_HAVE_DAC1 is not set +# CONFIG_STM32_HAVE_DAC2 is not set +# CONFIG_STM32_HAVE_RNG is not set +# CONFIG_STM32_HAVE_ETHMAC is not set +CONFIG_STM32_HAVE_I2C2=y +# CONFIG_STM32_HAVE_I2C3 is not set +CONFIG_STM32_HAVE_SPI2=y +CONFIG_STM32_HAVE_SPI3=y +# CONFIG_STM32_HAVE_SPI4 is not set +# CONFIG_STM32_HAVE_SPI5 is not set +# CONFIG_STM32_HAVE_SPI6 is not set +# CONFIG_STM32_HAVE_SAIPLL is not set +# CONFIG_STM32_HAVE_I2SPLL is not set +# CONFIG_STM32_ADC1 is not set +# CONFIG_STM32_ADC2 is not set +# CONFIG_STM32_ADC3 is not set +# CONFIG_STM32_BKP is not set +# CONFIG_STM32_CAN1 is not set +# CONFIG_STM32_CRC is not set +# CONFIG_STM32_DMA1 is not set +# CONFIG_STM32_DMA2 is not set +CONFIG_STM32_I2C1=y +# CONFIG_STM32_I2C2 is not set +# CONFIG_STM32_PWR is not set +# CONFIG_STM32_SDIO is not set +# CONFIG_STM32_SPI1 is not set +# CONFIG_STM32_SPI2 is not set +# CONFIG_STM32_SPI3 is not set +# CONFIG_STM32_TIM1 is not set +# CONFIG_STM32_TIM2 is not set +# CONFIG_STM32_TIM3 is not set +# CONFIG_STM32_TIM4 is not set +# CONFIG_STM32_TIM5 is not set +# CONFIG_STM32_TIM6 is not set +# CONFIG_STM32_TIM7 is not set +# CONFIG_STM32_TIM8 is not set +CONFIG_STM32_USART1=y +# CONFIG_STM32_USART2 is not set +# CONFIG_STM32_USART3 is not set +# CONFIG_STM32_UART4 is not set +# CONFIG_STM32_UART5 is not set +# CONFIG_STM32_USB is not set +# CONFIG_STM32_IWDG is not set +# CONFIG_STM32_WWDG is not set +CONFIG_STM32_I2C=y +# CONFIG_STM32_NOEXT_VECTORS is not set + +# +# Alternate Pin Mapping +# +# CONFIG_STM32_I2C1_REMAP is not set +# CONFIG_STM32_USART1_REMAP is not set +# CONFIG_STM32_JTAG_DISABLE is not set +# CONFIG_STM32_JTAG_FULL_ENABLE is not set +# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +# CONFIG_STM32_FORCEPOWER is not set +# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set + +# +# Timer Configuration +# +# CONFIG_STM32_ONESHOT is not set +# CONFIG_STM32_FREERUN is not set +# CONFIG_STM32_TIM1_CAP is not set +# CONFIG_STM32_TIM3_CAP is not set +# CONFIG_STM32_TIM4_CAP is not set +# CONFIG_STM32_TIM5_CAP is not set +# CONFIG_STM32_TIM8_CAP is not set +CONFIG_STM32_USART=y +CONFIG_STM32_SERIALDRIVER=y + +# +# U[S]ART Configuration +# + +# +# U[S]ART Device Configuration +# +CONFIG_STM32_USART1_SERIALDRIVER=y +# CONFIG_STM32_USART1_1WIREDRIVER is not set +# CONFIG_USART1_RS485 is not set + +# +# Serial Driver Configuration +# +# CONFIG_SERIAL_DISABLE_REORDERING is not set +# CONFIG_STM32_FLOWCONTROL_BROKEN is not set +# CONFIG_STM32_USART_BREAKS is not set +# CONFIG_STM32_USART_SINGLEWIRE is not set + +# +# I2C Configuration +# +CONFIG_STM32_I2C_ALT=y +# CONFIG_STM32_I2C_DYNTIMEO is not set +CONFIG_STM32_I2CTIMEOSEC=0 +CONFIG_STM32_I2CTIMEOMS=500 +CONFIG_STM32_I2CTIMEOTICKS=500 +# CONFIG_STM32_I2C_DUTY16_9 is not set +CONFIG_STM32_HAVE_RTC_COUNTER=y +# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set + +# +# USB FS Host Configuration +# + +# +# USB HS Host Configuration +# + +# +# USB Host Debug Configuration +# + +# +# USB Device Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=5483 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_SIZE=20480 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +# CONFIG_ARCH_BOARD_STM32_TINY is not set +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="stm32f103-minimum" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +# CONFIG_ARCH_BUTTONS is not set +CONFIG_ARCH_HAVE_IRQBUTTONS=y + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_RESET is not set +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_ADCTEST is not set +# CONFIG_BOARDCTL_PWMTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set + +# +# RTOS Features +# +# CONFIG_DISABLE_OS_API is not set + +# +# Clocks and Timers +# +CONFIG_ARCH_HAVE_TICKLESS=y +# CONFIG_SCHED_TICKLESS is not set +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +CONFIG_ARCH_HAVE_TIMEKEEPING=y +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2011 +CONFIG_START_MONTH=7 +CONFIG_START_DAY=5 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=0 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +CONFIG_BOARD_INITIALIZE=y +# CONFIG_BOARD_INITTHREAD is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +# CONFIG_DISABLE_POLL is not set +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +CONFIG_ARCH_HAVE_I2CRESET=y +CONFIG_I2C=y +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_POLLED is not set +# CONFIG_I2C_RESET is not set +# CONFIG_I2C_TRACE is not set +# CONFIG_I2C_DRIVER is not set +# CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_TIMERS_CS2100CP is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +CONFIG_SENSORS=y +# CONFIG_AS5048B is not set +# CONFIG_BH1750FVI is not set +# CONFIG_BMG160 is not set +# CONFIG_BMP180 is not set +# CONFIG_SENSOR_KXTJ9 is not set +# CONFIG_LIS3DSH is not set +# CONFIG_LIS331DL is not set +# CONFIG_SN_LSM9DS1 is not set +# CONFIG_MB7040 is not set +# CONFIG_MLX90393 is not set +# CONFIG_MCP9844 is not set +# CONFIG_MS58XX is not set +CONFIG_MS58XX_VDD=30 +# CONFIG_MPL115A is not set +# CONFIG_SENSORS_ADXL345 is not set +# CONFIG_MAX31855 is not set +# CONFIG_MAX6675 is not set +# CONFIG_LIS3MDL is not set +# CONFIG_LM75 is not set +# CONFIG_LM92 is not set +# CONFIG_QENCODER is not set +CONFIG_VEML6070=y +# CONFIG_XEN1210 is not set +# CONFIG_ZEROCROSS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +CONFIG_USART1_SERIALDRIVER=y +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_SERIAL_NPOLLWAITERS=2 +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +# CONFIG_SERIAL_TIOCSERGSTRUCT is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +CONFIG_USART1_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# USART1 Configuration +# +CONFIG_USART1_RXBUFSIZE=256 +CONFIG_USART1_TXBUFSIZE=256 +CONFIG_USART1_BAUD=115200 +CONFIG_USART1_BITS=8 +CONFIG_USART1_PARITY=0 +CONFIG_USART1_2STOP=0 +# CONFIG_USART1_IFLOWCONTROL is not set +# CONFIG_USART1_OFLOWCONTROL is not set +# CONFIG_USART1_DMA is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +# CONFIG_FS_READABLE is not set +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +CONFIG_SYMTAB_ORDEREDBYNAME=y + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_LIBC_LONG_LONG is not set +# CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set +# CONFIG_LIBC_NETDB is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CHAT is not set +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=80 +CONFIG_NSH_DISABLE_SEMICOLON=y +# CONFIG_NSH_CMDPARMS is not set +CONFIG_NSH_MAXARGUMENTS=6 +# CONFIG_NSH_ARGCAT is not set +CONFIG_NSH_NESTDEPTH=3 +CONFIG_NSH_DISABLEBG=y +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +CONFIG_NSH_DISABLE_ADDROUTE=y +CONFIG_NSH_DISABLE_BASENAME=y +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +CONFIG_NSH_DISABLE_DF=y +CONFIG_NSH_DISABLE_DELROUTE=y +CONFIG_NSH_DISABLE_DIRNAME=y +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +CONFIG_NSH_DISABLE_IFCONFIG=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_KILL is not set +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +CONFIG_NSH_DISABLE_TIME=y +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +CONFIG_NSH_DISABLE_UNAME=y +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Configure Command Options +# +CONFIG_NSH_CODECS_BUFSIZE=128 +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_NSH_FILEIOSIZE=1024 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +CONFIG_NSH_DISABLE_ITEF=y +CONFIG_NSH_DISABLE_LOOPS=y + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_I2CTOOL is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm32f103-minimum/veml6070/setenv.sh b/configs/stm32f103-minimum/veml6070/setenv.sh new file mode 100644 index 0000000000..efcbfee142 --- /dev/null +++ b/configs/stm32f103-minimum/veml6070/setenv.sh @@ -0,0 +1,100 @@ +#!/bin/bash +# configs//stm32f103-minimum/veml6070/setenv.sh +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" +# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" +# You can this free toolchain here https://launchpad.net/gcc-arm-embedded +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" + +# This is the path to the location where I installed the devkitARM toolchain +# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/ +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/drivers/sensors/Kconfig b/drivers/sensors/Kconfig index 3b852a1cd4..d43362eb6c 100644 --- a/drivers/sensors/Kconfig +++ b/drivers/sensors/Kconfig @@ -234,6 +234,13 @@ config QENCODER bool "Qencoder" default n +config VEML6070 + bool "Vishay VEML6070 UV-A Light Sensor support" + default n + select I2C + ---help--- + Enable driver support for the Vishay VEML6070 UV-A light sensor. + config XEN1210 bool "Sensixs XEN1210 Magnetometer" default n diff --git a/drivers/sensors/Make.defs b/drivers/sensors/Make.defs index 9c2bce29e8..4a21504281 100644 --- a/drivers/sensors/Make.defs +++ b/drivers/sensors/Make.defs @@ -138,6 +138,12 @@ ifeq ($(CONFIG_QENCODER),y) CSRCS += qencoder.c endif +# Vishay VEML6070 + +ifeq ($(CONFIG_VEML6070),y) + CSRCS += veml6070.c +endif + # Sensixs XEN1210 ifeq ($(CONFIG_XEN1210),y) diff --git a/drivers/sensors/veml6070.c b/drivers/sensors/veml6070.c new file mode 100644 index 0000000000..28030ba7ce --- /dev/null +++ b/drivers/sensors/veml6070.c @@ -0,0 +1,352 @@ +/**************************************************************************** + * drivers/sensors/veml6070.c + * Character driver for the Vishay UV-A Light Sensor VEML6070 + * + * Copyright (C) 2016 Alan Carvalho de Assis. All rights reserved. + * Author: Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#if defined(CONFIG_I2C) && defined(CONFIG_VEML6070) + +/**************************************************************************** + * Pre-process Definitions + ****************************************************************************/ + +#ifndef CONFIG_VEML6070_I2C_FREQUENCY +# define CONFIG_VEML6070_I2C_FREQUENCY 100000 +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct veml6070_dev_s +{ + FAR struct i2c_master_s *i2c; /* I2C interface */ + uint8_t addr; /* I2C address */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* I2C Helpers */ + +static int veml6070_read8(FAR struct veml6070_dev_s *priv, int offset, + FAR uint8_t *regval); +static int veml6070_write8(FAR struct veml6070_dev_s *priv, + uint8_t regval); + +/* Character driver methods */ + +static int veml6070_open(FAR struct file *filep); +static int veml6070_close(FAR struct file *filep); +static ssize_t veml6070_read(FAR struct file *filep, FAR char *buffer, + size_t buflen); +static ssize_t veml6070_write(FAR struct file *filep, + FAR const char *buffer, size_t buflen); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct file_operations g_veml6070_fops = +{ + veml6070_open, /* open */ + veml6070_close, /* close */ + veml6070_read, /* read */ + veml6070_write, /* write */ + NULL, /* seek */ + NULL /* ioctl */ +#ifndef CONFIG_DISABLE_POLL + , NULL /* poll */ +#endif +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + , NULL /* unlink */ +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: veml6070_read8 + * + * Description: + * Read 8-bit register + * + ****************************************************************************/ + +static int veml6070_read8(FAR struct veml6070_dev_s *priv, int offset, + FAR uint8_t *regval) +{ + struct i2c_config_s config; + uint8_t data[1]; + int ret = -1; + + /* Set up the I2C configuration */ + + config.frequency = CONFIG_VEML6070_I2C_FREQUENCY; + config.address = priv->addr + offset; + config.addrlen = 7; + + /* Read 8-bits from the device */ + + ret = i2c_read(priv->i2c, &config, data, 1); + if (ret < 0) + { + snerr ("i2c_read failed: %d\n", ret); + return ret; + } + + /* Copy the content of the buffer to the location of the uint8_t pointer */ + + *regval = data[0]; + + sninfo("value: %08x ret: %d\n", *regval, ret); + return OK; +} + +/**************************************************************************** + * Name: veml6070_write8 + * + * Description: + * Write from an 8-bit register + * + ****************************************************************************/ + +static int veml6070_write8(FAR struct veml6070_dev_s *priv, uint8_t regval) +{ + struct i2c_config_s config; + int ret; + + sninfo("value: %02x\n", regval); + + /* Set up the I2C configuration */ + + config.frequency = CONFIG_VEML6070_I2C_FREQUENCY; + config.address = priv->addr; + config.addrlen = 7; + + /* Write 8 bits to device */ + + ret = i2c_write(priv->i2c, &config, ®val, 1); + if (ret < 0) + { + snerr("ERROR: i2c_write failed: %d\n", ret); + } + + return ret; +} + +/**************************************************************************** + * Name: veml6070_open + * + * Description: + * This function is called whenever the VEML6070 device is opened. + * + ****************************************************************************/ + +static int veml6070_open(FAR struct file *filep) +{ + return OK; +} + +/**************************************************************************** + * Name: veml6070_close + * + * Description: + * This routine is called when the VEML6070 device is closed. + * + ****************************************************************************/ + +static int veml6070_close(FAR struct file *filep) +{ + return OK; +} + +/**************************************************************************** + * Name: veml6070_read + ****************************************************************************/ + +static ssize_t veml6070_read(FAR struct file *filep, FAR char *buffer, + size_t buflen) +{ + int ret; + FAR struct inode *inode; + FAR struct veml6070_dev_s *priv; + int msb = 1; + uint16_t regdata; + + DEBUGASSERT(filep); + inode = filep->f_inode; + + DEBUGASSERT(inode && inode->i_private); + priv = (FAR struct veml6070_dev_s *)inode->i_private; + + /* Check if the user is reading the right size */ + + if (buflen != 2) + { + snerr("ERROR: You need to read 2 bytes from this sensor!\n"); + return -EINVAL; + } + + /* Enable the sensor */ + + ret = veml6070_write8(priv, VEML6070_CMD_RSV & ~VEML6070_CMD_SD); + if (ret < 0) + { + snerr("ERROR: Failed to enable the VEML6070!\n"); + return -EINVAL; + } + + /* 1T for Rset 270Kohms is 125ms */ + + usleep(125000); + + /* Read the MSB first */ + + ret = veml6070_read8(priv, msb, (FAR uint8_t *) ®data); + if (ret < 0) + { + snerr("ERROR: Error reading light sensor!\n"); + return ret; + } + + buffer[1] = regdata; + + /* Read the LSB */ + + msb = 0; + ret = veml6070_read8(priv, msb, (FAR uint8_t *) ®data); + if (ret < 0) + { + snerr("ERROR: Error reading light sensor!\n"); + return ret; + } + + buffer[0] = regdata; + + return buflen; +} + +/**************************************************************************** + * Name: veml6070_write + ****************************************************************************/ + +static ssize_t veml6070_write(FAR struct file *filep, + FAR const char *buffer, size_t buflen) +{ + return -ENOSYS; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: veml6070_register + * + * Description: + * Register the VEML6070 character device as 'devpath' + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/uvlight0" + * i2c - An instance of the I2C interface to use to communicate with VEML6070 + * addr - The I2C address of the VEML6070. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int veml6070_register(FAR const char *devpath, FAR struct i2c_master_s *i2c, + uint8_t addr) +{ + int ret; + + /* Sanity check */ + + DEBUGASSERT(i2c != NULL); + + /* Initialize the VEML6070 device structure */ + + FAR struct veml6070_dev_s *priv = + (FAR struct veml6070_dev_s *)kmm_malloc(sizeof(struct veml6070_dev_s)); + + if (priv == NULL) + { + snerr("ERROR: Failed to allocate instance\n"); + return -ENOMEM; + } + + priv->i2c = i2c; + priv->addr = addr; + + /* Initialize the device (shut it down) */ + + ret = veml6070_write8(priv, VEML6070_CMD_RSV | VEML6070_CMD_SD); + if (ret < 0) + { + snerr("ERROR: Failed to initialize the VEML6070!\n"); + return ret; + } + + /* Register the character driver */ + + ret = register_driver(devpath, &g_veml6070_fops, 0666, priv); + if (ret < 0) + { + snerr("ERROR: Failed to register driver: %d\n", ret); + kmm_free(priv); + } + + return ret; +} + +#endif /* CONFIG_I2C && CONFIG_VEML6070 */ diff --git a/include/nuttx/sensors/veml6070.h b/include/nuttx/sensors/veml6070.h new file mode 100644 index 0000000000..a143f1ee8d --- /dev/null +++ b/include/nuttx/sensors/veml6070.h @@ -0,0 +1,121 @@ +/**************************************************************************** + * include/nuttx/input/veml6070.h + * + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Alan Carvalho de Assis. All rights reserved. + * Author: Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_SENSORS_VEML6070_H +#define __INCLUDE_NUTTX_SENSORS_VEML6070_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#if defined(CONFIG_VEML6070) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Device I2C Address */ + +#define VEML6070_I2C_DATA_LSB_CMD_ADDR 0x38 +#define VEML6070_I2C_DATA_MSB_ADDR 0x39 + +/* Command Register Format + * Bits: + * 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | + * RSV | RSV | ACK | ACK_THD | IT1 | IT0 | RSV | SD | + * + * NOTE: The RSV Bit 1 needs to be always 1 + */ + + +#define VEML6070_CMD_SD 0x01 /* Shutdown command */ +#define VEML6070_CMD_RSV 0x02 +#define VEML6070_CMD_IT_0_5T 0x00 /* IT1=0 : IT0=0 */ +#define VEML6070_CMD_IT_1T 0x04 /* IT1=0 : IT0=1 */ +#define VEML6070_CMD_IT_2T 0x08 /* IT1=1 : IT0=0 */ +#define VEML6070_CMD_IT_4T 0x0c /* IT1=1 : IT0=1 */ +#define VEML6070_CMD_ACK_THD 0x10 /* Acknowledge thresold: + 0 = 102 steps + 1 = 145 steps */ +#define VEML6070_CMD_ACK 0x20 /* Acknowledge activity */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: veml6070_register + * + * Description: + * Register the VEML6070 character device as 'devpath' + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/uvlight0" + * i2c - An instance of the I2C interface to use to communicate with + * VEML6070 + * addr - The I2C address of the VEML6070. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int veml6070_register(FAR const char *devpath, FAR struct i2c_master_s *i2c, + uint8_t addr); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_VEML6070 */ +#endif /* __INCLUDE_NUTTX_SENSORS_VEML6070_H */ -- GitLab From 31d9565f0fea4b31f012f14455678509d50244a1 Mon Sep 17 00:00:00 2001 From: Ramtin Amin Date: Mon, 14 Nov 2016 07:18:33 -0600 Subject: [PATCH 400/734] Misoc LM32: Corrects a bug that never occured in qemu on simulation or real fpga. The error was that the r1 register was being modified out of context switching and not restoring it. --- arch/misoc/src/lm32/lm32_vectors.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/misoc/src/lm32/lm32_vectors.S b/arch/misoc/src/lm32/lm32_vectors.S index 94521a3a69..4cc83a3919 100644 --- a/arch/misoc/src/lm32/lm32_vectors.S +++ b/arch/misoc/src/lm32/lm32_vectors.S @@ -240,7 +240,6 @@ _do_reset: .restore_all_and_eret: /* r1 should have the place where we restore ! */ - lw r2, (r1+REG_X2) lw r3, (r1+REG_X3) lw r4, (r1+REG_X4) lw r5, (r1+REG_X5) @@ -270,8 +269,9 @@ _do_reset: lw r29, (r1+REG_RA) lw r30, (r1+REG_EA) lw r31, (r1+REG_BA) - lw r1, (r1+REG_INT_CTX) - wcsr IE, r1 + lw r2, (r1+REG_INT_CTX) + wcsr IE, r2 + lw r2, (r1+REG_X2) lw r1, (r1+REG_X1) eret -- GitLab From efbb622ab8baf09a11b273bec00b24218321792c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 14 Nov 2016 10:30:10 -0600 Subject: [PATCH 401/734] Update README --- configs/esp32-core/README.txt | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index 579978d1d7..eb97058275 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -270,6 +270,37 @@ Debug Issues "ESP32 Pin List" document found here: http://espressif.com/en/support/download/documents?keys=&field_type_tid%5B%5D=13 + I put the ESP32 on a prototyping board and used a standard JTAG 20-pin + connector with an older Olimex JTAG that I had. Here is how I wired + the 20-pin connector: + + ----------------- ---------- + 20-PIN JTAG ESP32 PIN + CONNECTOR LABEL + ----------------- ---------- + 1 VREF INPUT 3V3 + 3 nTRST OUTPUT N/C + 5 TDI OUTPUT IO12 + 7 TMS OUTPUT IO14 + 9 TCLK OUTPUT IO13 + 11 RTCK INPUT N/C + 13 TDO INPUT IO15 + 15 RESET I/O N/C + 17 DBGRQ OUTPUT N/C + 19 5V OUTPUT N/C + ------------ ---------- + 2 VCC INPUT 3V3 + 4 GND N/A GND + 6 GND N/A GND + 8 GND N/A GND + 10 GND N/A GND + 12 GND N/A GND + 14 GND N/A GND + 16 GND N/A GND + 18 GND N/A GND + 20 GND N/A GND + ------------ ---------- + - I need to understand how to use the secondary bootloader. My understanding is that it will configure hardware, read a partition table at address 0x5000, and then load code into memory. I do need to -- GitLab From bf096873a1b88ad600445b0b349a5d097dedfea4 Mon Sep 17 00:00:00 2001 From: "Kolb, Stefan" Date: Mon, 14 Nov 2016 10:32:49 -0600 Subject: [PATCH 402/734] SAMV7 USBDEVHS: A problem occurred if the USB cable is unplugged while a large amount of data is send over an IN endpoint using DMA. If the USB cable is plugged in again after a few seconds it is not possible to send data over this IN endpoint again, all other endpoints work as expected. The problem occurs because if the USB cable is unplugged while an DMA transfer is in flight the transfer is canceled but the register SAM_USBHS_DEVDMACTRL is left in an undefined state. The problem was fixed the problem by resetting the register SAM_USBHS_DEVDMACTRL to a known state. Additionally all pending interrupts are cleared. --- arch/arm/src/samv7/sam_usbdevhs.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/src/samv7/sam_usbdevhs.c b/arch/arm/src/samv7/sam_usbdevhs.c index 087db9c0e1..1d48ca410a 100644 --- a/arch/arm/src/samv7/sam_usbdevhs.c +++ b/arch/arm/src/samv7/sam_usbdevhs.c @@ -3333,6 +3333,17 @@ static void sam_ep_reset(struct sam_usbdev_s *priv, uint8_t epno) sam_putreg(USBHS_DEVINT_PEP(epno), SAM_USBHS_DEVIDR); + /* Clear all pending interrupts */ + + sam_putreg(USBHS_DEVEPTICR_ALLINTS, SAM_USBHS_DEVEPTICR(epno)); + + /* Set DMA control register to a defined state */ + + if ((SAM_EPSET_DMA & SAM_EP_BIT(epno)) != 0) + { + sam_putreg(0, SAM_USBHS_DEVDMACTRL(epno)); + } + /* Cancel any queued requests. Since they are cancelled with status * -ESHUTDOWN, then will not be requeued until the configuration is reset. * NOTE: This should not be necessary... the CLASS_DISCONNECT above -- GitLab From 74089c5198f70a575c16ccfd3a2ba5fabe042fa2 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 14 Nov 2016 11:30:40 -0600 Subject: [PATCH 403/734] ESP32 Core v2: Include a copy of the OpenOCD config file. --- configs/esp32-core/README.txt | 4 +++ configs/esp32-core/scripts/esp32.cfg | 51 ++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) create mode 100644 configs/esp32-core/scripts/esp32.cfg diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index eb97058275..081cfad732 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -241,6 +241,10 @@ Debug Issues FreeRTOS, you will need to uncomment the "set ESP32_RTOS none" line in OpenOCD configuration file. + NOTE: A copy of this OpenOCD configuration file (with the referenced + line uncommented). Is available in the NuttX source tree at + nuttx/config/esp32-core/scripts/esp32.cfg. + The documentation indicates that you need to use an external JTAG like the TIAO USB Multi-protocol Adapter and the Flyswatter2. The instructions at http://www.esp32.com/viewtopic.php?t=381 show diff --git a/configs/esp32-core/scripts/esp32.cfg b/configs/esp32-core/scripts/esp32.cfg new file mode 100644 index 0000000000..68c594c101 --- /dev/null +++ b/configs/esp32-core/scripts/esp32.cfg @@ -0,0 +1,51 @@ +# +# Example configuration file to hook up an ESP32 module or board to a JTAG +# adapter. Please modify this file to your local setup. +# +# + + +# Include the configuration for the JTAG adapter. We use the Tian TUMPA here. +# If you have a different interface, please edit this to include the +# configuration file of yours. +source [find interface/ftdi/tumpa.cfg] + +# The ESP32 only supports JTAG. +transport select jtag + +# The speed of the JTAG interface, in KHz. If you get DSR/DIR errors (and they +# do not relate to OpenOCD trying to read from a memory range without physical +# memory being present there), you can try lowering this. +adapter_khz 200 + +# With no variables set, openocd will configure JTAG for the two cores of the ESP32 and +# will do automatic RTOS detection. This can be be adjusted by uncommenting any of the +# following lines: + +# Only configure the PRO CPU +#set ESP32_ONLYCPU 1 +# Only configure the APP CPU +#set ESP32_ONLYCPU 2 +# Disable RTOS support +set ESP32_RTOS none +# Force RTOS to be FreeRTOS +#set ESP32_RTOS FreeRTOS + +#Source the ESP32 configuration file +source [find target/esp32.cfg] + + +# The TDI pin of ESP32 is also a bootstrap pin that selects the voltage the SPI flash +# chip runs at. When a hard reset happens (e.g. because someone switches the board off +# and on) the ESP32 will use the current TDI value as the bootstrap value because the +# JTAG adapter overrides the pull-up or pull-down resistor that is supposed to do the +# bootstrapping. These lines basically set the idle value of the TDO line to a +# specified value, therefore reducing the chance of a bad bootup due to a bad flash +# voltage greatly. + +# Enable this for 1.8V SPI flash +esp108 flashbootstrap 1.8 +# Enable this for 3.3V SPI flash +#esp108 flashbootstrap 3.3 + + -- GitLab From c7dad4ffe091625ec01e32f9ffa22d47bc58633c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 14 Nov 2016 11:52:33 -0600 Subject: [PATCH 404/734] Update README --- configs/esp32-core/README.txt | 238 ++++++++++++++++----------- configs/esp32-core/scripts/esp32.cfg | 6 +- 2 files changed, 149 insertions(+), 95 deletions(-) diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index 081cfad732..75f4e34307 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -225,99 +225,151 @@ SMP Debug Issues ============ - You basically need the debug environment and a step-by-step procedure. - - - First in need some debug environment which would be a JTAG emulator - and the ESP32 OpenOCD software which is available here: - https://github.com/espressif/openocd-esp32 - - - There is on overiew of the use of OpenOCD here: - https://dl.espressif.com/doc/esp-idf/latest/openocd.html - This document is also available in ESP-IDF source tree in docs - directory (https://github.com/espressif/esp-idf). - - A template ESP32 OpenOCD configuration file is provided in - ESP-IDF docs directory (esp32.cfg). Since you are not using - FreeRTOS, you will need to uncomment the "set ESP32_RTOS none" - line in OpenOCD configuration file. - - NOTE: A copy of this OpenOCD configuration file (with the referenced - line uncommented). Is available in the NuttX source tree at - nuttx/config/esp32-core/scripts/esp32.cfg. - - The documentation indicates that you need to use an external JTAG - like the TIAO USB Multi-protocol Adapter and the Flyswatter2. - The instructions at http://www.esp32.com/viewtopic.php?t=381 show - use of an FTDI C232HM-DDHSL-0 USB 2.0 high speed to MPSSE cable. - - - The ESP32 Core v2 board has no on board JTAG connector. It will - be necessary to make a cable or some other board to connect a JTAG - emulator. Refer to http://www.esp32.com/viewtopic.php?t=381 "How - to debug ESP32 with JTAG / OpenOCD / GDB 1st part connect the - hardware." - - Relevant pin-out: - - -------- ---------- - PIN JTAG - LABEL FUNCTION - -------- ---------- - IO14 TMS - IO12 TDI - GND GND - IO13 TCK - -------- ---------- - IO15 TDO - -------- ---------- - - You can find the mapping of JTAG signals to ESP32 GPIO numbers in - "ESP32 Pin List" document found here: - http://espressif.com/en/support/download/documents?keys=&field_type_tid%5B%5D=13 - - I put the ESP32 on a prototyping board and used a standard JTAG 20-pin - connector with an older Olimex JTAG that I had. Here is how I wired - the 20-pin connector: - - ----------------- ---------- - 20-PIN JTAG ESP32 PIN - CONNECTOR LABEL - ----------------- ---------- - 1 VREF INPUT 3V3 - 3 nTRST OUTPUT N/C - 5 TDI OUTPUT IO12 - 7 TMS OUTPUT IO14 - 9 TCLK OUTPUT IO13 - 11 RTCK INPUT N/C - 13 TDO INPUT IO15 - 15 RESET I/O N/C - 17 DBGRQ OUTPUT N/C - 19 5V OUTPUT N/C - ------------ ---------- - 2 VCC INPUT 3V3 - 4 GND N/A GND - 6 GND N/A GND - 8 GND N/A GND - 10 GND N/A GND - 12 GND N/A GND - 14 GND N/A GND - 16 GND N/A GND - 18 GND N/A GND - 20 GND N/A GND - ------------ ---------- - - - I need to understand how to use the secondary bootloader. My - understanding is that it will configure hardware, read a partition - table at address 0x5000, and then load code into memory. I do need to - download and build the bootloader? - - - Do I need to create a partition table at 0x5000? Should this be part - of the NuttX build? - - See https://github.com/espressif/esp-idf/tree/master/components/bootloader - and https://github.com/espressif/esp-idf/tree/master/components/partition_table. - I suppose some of what I need is in there, but I am not sure what I am - looking at right now. + First you in need some debug environment which would be a JTAG emulator + and the ESP32 OpenOCD software which is available here: + https://github.com/espressif/openocd-esp32 + OpenOCD Documentation + --------------------- + There is on overiew of the use of OpenOCD here: + https://dl.espressif.com/doc/esp-idf/latest/openocd.html + This document is also available in ESP-IDF source tree in docs + directory (https://github.com/espressif/esp-idf). + + OpenOCD Configuration File + -------------------------- + A template ESP32 OpenOCD configuration file is provided in + ESP-IDF docs directory (esp32.cfg). Since you are not using + FreeRTOS, you will need to uncomment the "set ESP32_RTOS none" + line in OpenOCD configuration file. + + You will still need to change the source line from: + + find interface/ftdi/tumpa.cfg line + + to reflect the physical JTAG adapter connected. + + NOTE: A copy of this OpenOCD configuration file (with the referenced + line RTOS uncommented but with no change to JTAG interface). Is + available in the NuttX source tree at + nuttx/config/esp32-core/scripts/esp32.cfg. + + General OpenOCD build instructions + ---------------------------------- + Installing OpenOCD. The sources for the ESP32-enabled variant of + OpenOCD are available from Espressifs Github. To download the source, + use the following commands: + + git clone https://github.com/espressif/openocd-esp32.git + cd openocd-esp32 + git submodule init + git submodule update + + Then look at the README file in the openocd-esp32 directory. + + Running OpenOCD + -------------- + + cd to openocd-esp32 directory + copy the modified esp32.cfg script to this directory + Run ./src/openocd -s ./tcl -f ./esp32.cfg to start OpenOCD + + Connecting a debugger to OpenOCD + -------------------------------- + OpenOCD should now be ready to accept gdb connections. If you have + compiled the ESP32 toolchain using Crosstool-NG, or if you have + downloaded a precompiled toolchain from the Espressif website, you + should already have xtensa-esp32-elf-gdb, a version of gdb that can + be used for this + + First, make sure the project you want to debug is compiled and + flashed into the ESP32’s SPI flash. Then, in a different console + than OpenOCD is running in, invoke gdb. For example, for the + template app, you would do this like such: + + cd esp-idf-template + xtensa-esp32-elf-gdb -ex 'target remote localhost:3333' ./build/app-template.elf + This should give you a gdb prompt. + + JTAG Emulator + ------------- + The documentation indicates that you need to use an external JTAG + like the TIAO USB Multi-protocol Adapter and the Flyswatter2. + The instructions at http://www.esp32.com/viewtopic.php?t=381 show + use of an FTDI C232HM-DDHSL-0 USB 2.0 high speed to MPSSE cable. + + The ESP32 Core v2 board has no on board JTAG connector. It will + be necessary to make a cable or some other board to connect a JTAG + emulator. Refer to http://www.esp32.com/viewtopic.php?t=381 "How + to debug ESP32 with JTAG / OpenOCD / GDB 1st part connect the + hardware." + + Relevant pin-out: + + -------- ---------- + PIN JTAG + LABEL FUNCTION + -------- ---------- + IO14 TMS + IO12 TDI + GND GND + IO13 TCK + -------- ---------- + IO15 TDO + -------- ---------- + + You can find the mapping of JTAG signals to ESP32 GPIO numbers in + "ESP32 Pin List" document found here: + http://espressif.com/en/support/download/documents?keys=&field_type_tid%5B%5D=13 + + I put the ESP32 on a prototyping board and used a standard JTAG 20-pin + connector with an older Olimex JTAG that I had. Here is how I wired + the 20-pin connector: + + ----------------- ---------- + 20-PIN JTAG ESP32 PIN + CONNECTOR LABEL + ----------------- ---------- + 1 VREF INPUT 3V3 + 3 nTRST OUTPUT N/C + 5 TDI OUTPUT IO12 + 7 TMS OUTPUT IO14 + 9 TCLK OUTPUT IO13 + 11 RTCK INPUT N/C + 13 TDO INPUT IO15 + 15 RESET I/O N/C + 17 DBGRQ OUTPUT N/C + 19 5V OUTPUT N/C + ------------ ---------- + 2 VCC INPUT 3V3 + 4 GND N/A GND + 6 GND N/A GND + 8 GND N/A GND + 10 GND N/A GND + 12 GND N/A GND + 14 GND N/A GND + 16 GND N/A GND + 18 GND N/A GND + 20 GND N/A GND + ------------ ---------- + + Secondary Boot Loader / Partition Table + --------------------------------------- + I need to understand how to use the secondary bootloader. My + understanding is that it will configure hardware, read a partition + table at address 0x5000, and then load code into memory. I do need to + download and build the bootloader? + + Do I need to create a partition table at 0x5000? Should this be part + of the NuttX build? + + See https://github.com/espressif/esp-idf/tree/master/components/bootloader + and https://github.com/espressif/esp-idf/tree/master/components/partition_table. + I suppose some of what I need is in there, but I am not sure what I am + looking at right now. + + Running from IRAM + ----------------- It is possible to skip the secondary bootloader and run out of IRAM using only the primary bootloader if your application of small enough (< 128KiB code, <180KiB data), then you can simplify initial bring-up by avoiding second stage @@ -355,6 +407,8 @@ Debug Issues will be written. ROM bootloader expects to find an application (or second stage bootloader) image at offset 0x1000, so we are writing the binary there. + Clocking + -------- Right now, the NuttX port depends on the bootloader to initialize hardware, including basic (slow) clocking. If I had the clock configuration logic, would I be able to run directly out of IRAM without a bootloader? That diff --git a/configs/esp32-core/scripts/esp32.cfg b/configs/esp32-core/scripts/esp32.cfg index 68c594c101..ec04c4a079 100644 --- a/configs/esp32-core/scripts/esp32.cfg +++ b/configs/esp32-core/scripts/esp32.cfg @@ -1,12 +1,12 @@ # -# Example configuration file to hook up an ESP32 module or board to a JTAG +# Example configuration file to hook up an ESP32 module or board to a JTAG # adapter. Please modify this file to your local setup. # # # Include the configuration for the JTAG adapter. We use the Tian TUMPA here. -# If you have a different interface, please edit this to include the +# If you have a different interface, please edit this to include the # configuration file of yours. source [find interface/ftdi/tumpa.cfg] @@ -39,7 +39,7 @@ source [find target/esp32.cfg] # chip runs at. When a hard reset happens (e.g. because someone switches the board off # and on) the ESP32 will use the current TDI value as the bootstrap value because the # JTAG adapter overrides the pull-up or pull-down resistor that is supposed to do the -# bootstrapping. These lines basically set the idle value of the TDO line to a +# bootstrapping. These lines basically set the idle value of the TDO line to a # specified value, therefore reducing the chance of a bad bootup due to a bad flash # voltage greatly. -- GitLab From 3b6c4b37b0c2325a943dca5d1b7f180f5b51c224 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 14 Nov 2016 12:54:29 -0600 Subject: [PATCH 405/734] Update README --- configs/esp32-core/README.txt | 53 +++++++++++++++++++++------- configs/esp32-core/scripts/esp32.cfg | 2 +- 2 files changed, 42 insertions(+), 13 deletions(-) diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index 75f4e34307..36a6468d2c 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -240,19 +240,25 @@ Debug Issues -------------------------- A template ESP32 OpenOCD configuration file is provided in ESP-IDF docs directory (esp32.cfg). Since you are not using - FreeRTOS, you will need to uncomment the "set ESP32_RTOS none" - line in OpenOCD configuration file. + FreeRTOS, you will need to uncomment the line: - You will still need to change the source line from: + set ESP32_RTOS none - find interface/ftdi/tumpa.cfg line + in the OpenOCD configuration file. You will also need to change + the source line from: + + find interface/ftdi/tumpa.cfg to reflect the physical JTAG adapter connected. - NOTE: A copy of this OpenOCD configuration file (with the referenced - line RTOS uncommented but with no change to JTAG interface). Is - available in the NuttX source tree at - nuttx/config/esp32-core/scripts/esp32.cfg. + NOTE: A copy of this OpenOCD configuration file available in the NuttX + source tree at nuttx/config/esp32-core/scripts/esp32.cfg.. It has these + modifications: + + - The referenced "set ESP32_RTOS none" line has been uncommented + - The "ind interface/ftdi/tumpa.cfg". This means that you will + need to specify the interface configuration file on the OpenOCD + command line. General OpenOCD build instructions ---------------------------------- @@ -265,14 +271,37 @@ Debug Issues git submodule init git submodule update - Then look at the README file in the openocd-esp32 directory. + Then look at the README and the docs/INSTALL.txt files in the + openocd-esp32 directory for further instructions. There area + separate README files for Linux/Cygwin, OSX, and Windows. Here + is what I ended up doing (under Linux): + + cd openocd-esp32 + ./bootstrap + ./configure + make + + If you do not do the install step, then you will have a localhost + version of the OpenOCD binary at openocd-esp32/src. Running OpenOCD -------------- - cd to openocd-esp32 directory - copy the modified esp32.cfg script to this directory - Run ./src/openocd -s ./tcl -f ./esp32.cfg to start OpenOCD + - cd to openocd-esp32 directory + - copy the modified esp32.cfg script to this directory + + Then start OpenOCD by executing a command like the following. Here + I assume that: + + - You did not install OpenOCD; binararies are avalable at + openocd-esp32/src and interface scripts are in + openocd-eps32/tcl/interface + - I select the configuration for the Olimex ARM-USB-OCD + debugger. + + Then the command to start OpenOCD is: + + sudo ./src/openocd -s ./tcl -f tcl/interface/ftdi/olimex-arm-usb-ocd.cfg -f ./esp32.cfg Connecting a debugger to OpenOCD -------------------------------- diff --git a/configs/esp32-core/scripts/esp32.cfg b/configs/esp32-core/scripts/esp32.cfg index ec04c4a079..0bd581f40a 100644 --- a/configs/esp32-core/scripts/esp32.cfg +++ b/configs/esp32-core/scripts/esp32.cfg @@ -8,7 +8,7 @@ # Include the configuration for the JTAG adapter. We use the Tian TUMPA here. # If you have a different interface, please edit this to include the # configuration file of yours. -source [find interface/ftdi/tumpa.cfg] +# source [find interface/ftdi/olimex-arm-usb-ocd.cfg] # The ESP32 only supports JTAG. transport select jtag -- GitLab From c84db681036b9f43f1301648e01e009b6aa636e5 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 14 Nov 2016 13:29:08 -0600 Subject: [PATCH 406/734] Xtensa ESP32: Fix some compilation errors that snuck with some of the last changes --- arch/xtensa/src/common/xtensa_windowspill.S | 6 +++--- configs/esp32-core/Kconfig | 11 +++++++++++ configs/esp32-core/README.txt | 17 ++++++++++++++++- configs/esp32-core/include/board.h | 8 ++++++-- configs/esp32-core/nsh/defconfig | 9 ++++++--- 5 files changed, 42 insertions(+), 9 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_windowspill.S b/arch/xtensa/src/common/xtensa_windowspill.S index bba79e14ee..336e5cd431 100644 --- a/arch/xtensa/src/common/xtensa_windowspill.S +++ b/arch/xtensa/src/common/xtensa_windowspill.S @@ -40,7 +40,7 @@ ****************************************************************************/ #include -#include +#include #include "xtensa_abi.h" /**************************************************************************** @@ -148,7 +148,7 @@ _xtensa_window_spill: rsr a3, WINDOWSTART srl a2, a3 /* a2 is 0... | 000000xxxxxxxxxx = WINDOWSTART >> sar */ sll a3, a3 /* a3 is 1yyyyy0000000000 | 0... = WINDOWSTART << (32 - sar) */ - bgez a3, .Linvalid_ws /* verify that msbit is indeed set + bgez a3, .Linvalid_ws /* verify that msbit is indeed set */ srli a3, a3, 32-WSBITS /* a3 is 0... | 1yyyyy0000000000 = a3 >> (32-NAREG/4) */ or a2, a2, a3 /* a2 is 0... | 1yyyyyxxxxxxxxxx */ @@ -202,7 +202,7 @@ _xtensa_window_spill: add a3, a2, a3 /* a3 = WINDOWBASE + index */ #endif /* XCHAL_HAVE_NSA */ - wsr a 3, WINDOWBASE /* Effectively do: rotw index */ + wsr a3, WINDOWBASE /* Effectively do: rotw index */ rsync /* Wait for write to WINDOWBASE to complete */ /* Now our registers have changed! */ diff --git a/configs/esp32-core/Kconfig b/configs/esp32-core/Kconfig index 719b83d1a5..8e3da8ac64 100644 --- a/configs/esp32-core/Kconfig +++ b/configs/esp32-core/Kconfig @@ -5,4 +5,15 @@ if ARCH_BOARD_ESP32CORE +choice + prompt "On-board Crystal Frequency" + default ESP32CORE_XTAL_40MZ + +config ESP32CORE_XTAL_40MZ + bool "40MHz" + +config ESP32CORE_XTAL_26MHz + bool "26MHz" + +endchoice # On-board Crystal Frequency endif # ARCH_BOARD_ESP32CORE diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index 36a6468d2c..c3fdd0795b 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -303,6 +303,20 @@ Debug Issues sudo ./src/openocd -s ./tcl -f tcl/interface/ftdi/olimex-arm-usb-ocd.cfg -f ./esp32.cfg + I then see: + + Open On-Chip Debugger 0.10.0-dev-g3098897 (2016-11-14-12:19) + Licensed under GNU GPL v2 + For bug reports, read + http://openocd.org/doc/doxygen/bugs.html + adapter speed: 200 kHz + force hard breakpoints + Info : clock speed 200 kHz + Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1) + Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1) + Info : esp32.cpu0: Debug controller was reset (pwrstat=0x5F, after clear 0x0F). + Info : esp32.cpu0: Core was reset (pwrstat=0x5F, after clear 0x0F). + Connecting a debugger to OpenOCD -------------------------------- OpenOCD should now be ready to accept gdb connections. If you have @@ -318,7 +332,8 @@ Debug Issues cd esp-idf-template xtensa-esp32-elf-gdb -ex 'target remote localhost:3333' ./build/app-template.elf - This should give you a gdb prompt. + + This should give you a gdb prompt. JTAG Emulator ------------- diff --git a/configs/esp32-core/include/board.h b/configs/esp32-core/include/board.h index a08840fbe0..e3b2e85a87 100644 --- a/configs/esp32-core/include/board.h +++ b/configs/esp32-core/include/board.h @@ -41,9 +41,13 @@ ****************************************************************************/ /* Clocking ****************************************************************/ -/* The ESP32 Core board V2 is fitted with a 40MHz crystal */ +/* The ESP32 Core board V2 is fitted with either a 26 a 40MHz crystal */ -#define BOARD_XTAL_FREQUENCY 40000000 +#ifdef CONFIG_ESP32CORE_XTAL_26MHz +# define BOARD_XTAL_FREQUENCY 26000000 +#else +# define BOARD_XTAL_FREQUENCY 40000000 +#endif /* Clock reconfiguration is currently disabled, so the CPU will be running * at the XTAL frequency. diff --git a/configs/esp32-core/nsh/defconfig b/configs/esp32-core/nsh/defconfig index 96bb1c7bd3..2d68310f33 100644 --- a/configs/esp32-core/nsh/defconfig +++ b/configs/esp32-core/nsh/defconfig @@ -62,6 +62,7 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set @@ -170,6 +171,8 @@ CONFIG_ARCH_BOARD="esp32-core" # # Board-Specific Options # +CONFIG_ESP32CORE_XTAL_40MZ=y +# CONFIG_ESP32CORE_XTAL26MHz is not set # CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set @@ -299,14 +302,14 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set # CONFIG_SPI_BITBANG is not set -- GitLab From 0ed0217be2e99b1a0d33879e5eb97ede3bb74a25 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 14 Nov 2016 13:41:30 -0600 Subject: [PATCH 407/734] ESP32: Trivial typo prevent good link --- configs/esp32-core/README.txt | 4 ++-- configs/esp32-core/scripts/esp32_common.ld | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index c3fdd0795b..59cc9d4ab8 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -330,8 +330,8 @@ Debug Issues than OpenOCD is running in, invoke gdb. For example, for the template app, you would do this like such: - cd esp-idf-template - xtensa-esp32-elf-gdb -ex 'target remote localhost:3333' ./build/app-template.elf + cd nuttx + xtensa-esp32-elf-gdb -ex 'target remote localhost:3333' nuttx This should give you a gdb prompt. diff --git a/configs/esp32-core/scripts/esp32_common.ld b/configs/esp32-core/scripts/esp32_common.ld index cfabd62087..ba67d87451 100644 --- a/configs/esp32-core/scripts/esp32_common.ld +++ b/configs/esp32-core/scripts/esp32_common.ld @@ -135,7 +135,7 @@ SECTIONS /* C++ constructor and destructor tables, properly ordered: */ - __sinit = ABSOLUTE(.); + _sinit = ABSOLUTE(.); KEEP (*crtbegin.o(.ctors)) KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) KEEP (*(SORT(.ctors.*))) -- GitLab From 96e7d1c310c316c980f15165bf8eb2ab0da580bf Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 14 Nov 2016 16:41:37 -0600 Subject: [PATCH 408/734] Update REAMME --- Documentation/README.html | 5 +++-- README.txt | 3 ++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/README.html b/Documentation/README.html index 8751b6b37c..a9577df8ce 100644 --- a/Documentation/README.html +++ b/Documentation/README.html @@ -8,7 +8,7 @@

    NuttX README Files

    -

    Last Updated: November 4, 2016

    +

    Last Updated: November 14, 2016

    @@ -384,7 +384,8 @@ apps/ |- gpsutils/ | `- "minmea/README.txt |- graphics/ - | `- "tiff/README.txt + | |- "tiff/README.txt + | `- "traveler/tools/tcledit/README.txt |- interpreters/ | |- bas/README.txt | |- ficl/README.txt diff --git a/README.txt b/README.txt index d2a9a7b9fe..3a673b7e9a 100644 --- a/README.txt +++ b/README.txt @@ -1597,7 +1597,8 @@ apps/ |- gpsutils/ | `- minmea/README.txt |- graphics/ - | `- tiff/README.txt + | |- tiff/README.txt + | `- traveler/tools/tcledit/README.txt |- interpreters/ | |- bas | | `- README.txt -- GitLab From 5dfc5f1da585d1bf2a87d68e3c1f6690a612bd6c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 14 Nov 2016 17:51:50 -0600 Subject: [PATCH 409/734] ESP32 Core v2: Add configuration to supporting linking NuttX for execution out of IRAM. --- configs/esp32-core/Kconfig | 11 + configs/esp32-core/README.txt | 98 ++++++--- configs/esp32-core/nsh/Make.defs | 7 +- .../{esp32_common.ld => esp32_flash.ld} | 2 +- configs/esp32-core/scripts/esp32_iram.ld | 191 ++++++++++++++++++ configs/esp32-core/smp/Make.defs | 7 +- 6 files changed, 282 insertions(+), 34 deletions(-) rename configs/esp32-core/scripts/{esp32_common.ld => esp32_flash.ld} (98%) create mode 100644 configs/esp32-core/scripts/esp32_iram.ld diff --git a/configs/esp32-core/Kconfig b/configs/esp32-core/Kconfig index 8e3da8ac64..3f73b4052a 100644 --- a/configs/esp32-core/Kconfig +++ b/configs/esp32-core/Kconfig @@ -16,4 +16,15 @@ config ESP32CORE_XTAL_26MHz bool "26MHz" endchoice # On-board Crystal Frequency + +config ESP32CORE_RUN_IRAM + bool "Run from IRAM" + default n + ---help--- + The default configuration is set up run from IRAM. However, the + current (2016-11-14) OpenOCD for ESP32 does not support writing to + FLASH. This option sets up the liner scripts to support execution + from IRAM. In this case, OpenOCD can be used to load directly into + IRAM. + endif # ARCH_BOARD_ESP32CORE diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index 59cc9d4ab8..59636eb113 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -23,7 +23,8 @@ Contents o Serial Console o Buttons and LEDs o SMP - o Debug Issues + o OpenOCD for the ESP32 + o Executing and Debugging from FLASH and IRAM o Configurations o Things to Do @@ -222,8 +223,8 @@ SMP 3. Assertions. On a fatal assertions, other CPUs need to be stopped. -Debug Issues -============ +OpenOCD for the ESP32 +===================== First you in need some debug environment which would be a JTAG emulator and the ESP32 OpenOCD software which is available here: @@ -335,6 +336,16 @@ Debug Issues This should give you a gdb prompt. + Breakpoints + ----------- + You can set up to 2 hardware breakpoints, which can be anywhere in the + address space. Also 2 hardware watchpoints. + + The openocd esp32.cfg file currently forces gdb to use hardware + breakpoints, I believe because software breakpoints (or, at least, the + memory map for automatically choosing them) aren't implemented yet + (as of 2016-11-14). + JTAG Emulator ------------- The documentation indicates that you need to use an external JTAG @@ -397,49 +408,74 @@ Debug Issues 20 GND N/A GND ------------ ---------- - Secondary Boot Loader / Partition Table - --------------------------------------- - I need to understand how to use the secondary bootloader. My - understanding is that it will configure hardware, read a partition - table at address 0x5000, and then load code into memory. I do need to - download and build the bootloader? + Executing and Debugging from FLASH and IRAM + =========================================== + + FLASH + ----- + OpenOCD currently doesn't have a FLASH driver for ESP32, so you can load + code into IRAM only via JTAG. FLASH-resident sections like .FLASH.rodata + will fail to load. The bootloader in ROM doesn't parse ELF, so any imag + which is bootloaded from FLASH has to be converted into a custom image + format first. + + The tool esp-idf uses for flashing is a command line Python tool called + "esptool.py" which talks to a serial bootloader in ROM. A version is + supplied in the esp-idf codebase in components/esptool_py/esptool, the + "upstream" for that tool is here: + + https://github.com/espressif/esptool/pull/121 + + The master branch for esptool.py is currently ESP8266-only (as of 2016-11-14), + this PR has the ESP32 support which still needs some final tidying up before + it's + merged. - Do I need to create a partition table at 0x5000? Should this be part - of the NuttX build? + To FLASH an ELF via the command line is a two step process, something like + this: + esptool.py --chip esp32 elf2image --flash_mode dio --flash_size 4MB -o ./nuttx.bin nuttx.elf + esptool.py --chip esp32 --port COMx write_flash 0x1000 bootloader.bin 0x4000 partition_table.bin 0x10000 nuttx.bin + + The first step converts an ELF image into an ESP32-compatible binary + image format, and the second step flashes it (along with bootloader image and + partition table binary.) + + To put the ESP32 into serial flashing mode, it needs to be reset with IO0 held + low. On the Core boards this can be accomplished by holding the button marked + "Boot" and pressing then releasing the button marked "EN". Actually, esptool.py + can enter bootloader mode automatically (via RTS/DTR control lines), but + unfortunately a timing interaction between the Windows CP2012 driver and the + hardware means this doesn't currently work on Windows. + + Secondary Boot Loader / Partition Table + --------------------------------------- See https://github.com/espressif/esp-idf/tree/master/components/bootloader and https://github.com/espressif/esp-idf/tree/master/components/partition_table. - I suppose some of what I need is in there, but I am not sure what I am - looking at right now. Running from IRAM ----------------- + Running from IRAM is a good debug option. You should be able to load the ELF directly via JTAG in this case, and you may not need the bootloader. The one "gotcha" for needing the bootloader is disabling the initial watchdog, there is code in bootloader_start.c that does this. + It is possible to skip the secondary bootloader and run out of IRAM using only the primary bootloader if your application of small enough (< 128KiB code, <180KiB data), then you can simplify initial bring-up by avoiding second stage bootloader. Your application will be loaded into IRAM using first stage bootloader present in ESP32 ROM. To achieve this, you need two things: - 1. Have a linker script which places all code into IRAM and all data into DRAM - - 2. Use "esptool.py" utility found in ESP-IDF to convert application .elf file - into binary format which can be loaded by first stage bootloader. - - The default linker script in ESP-IDF places most code into memory-mapped flash: - https://github.com/espressif/esp-idf/blob/master/components/esp32/ld/esp32.common.ld#L178-L186 - - You would need to remove this section and move its contents into the end of .iram0.text section: - https://github.com/espressif/esp-idf/blob/master/components/esp32/ld/esp32.common.ld#L85 + 1. Have a linker script which places all code into IRAM and all data into + IRAM/DRAM - Same with constant data: move contents of .flash.rodata section: - https://github.com/espressif/esp-idf/blob/master/components/esp32/ld/esp32.common.ld#L134-L173 + 2. Use "esptool.py" utility found in ESP-IDF to convert application .elf + file into binary format which can be loaded by first stage bootloader. - into the end of .dram0.data section (before _heap_start): - https://github.com/espressif/esp-idf/blob/master/components/esp32/ld/esp32.common.ld#L128 + NuttX supports a configuration option, CONFIG_ESP32CORE_RUN_IRAM, that may be + selected for execution from IRAM. This option simply selects the correct + linker script for IRAM execution. - With these modifications, all code and data should be moved into IRAM/DRAM. Next, you would - need to link the ELF file and convert it to binary format suitable for flashing into the - board. The xommand should to convert ELF file to binary image looks as follows: + Again you would need to link the ELF file and convert it to binary format suitable + for flashing into the board. The command should to convert ELF file to binary + image looks as follows: python esp-idf/components/esptool_py/esptool/esptool.py --chip esp32 elf2image --flash_mode "dio" --flash_freq "40m" --flash_size "2MB" -o app.bin app.elf @@ -554,4 +590,4 @@ Things to Do 5. See SMP-related issues above - 6. See Debug Issues above + 6. See OpenOCD for the ESP32 above diff --git a/configs/esp32-core/nsh/Make.defs b/configs/esp32-core/nsh/Make.defs index f8901d0f8b..8b4dd25b40 100644 --- a/configs/esp32-core/nsh/Make.defs +++ b/configs/esp32-core/nsh/Make.defs @@ -38,10 +38,15 @@ include ${TOPDIR}/tools/Config.mk include ${TOPDIR}/arch/xtensa/src/lx6/Toolchain.defs LDSCRIPT1 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_out.ld -LDSCRIPT2 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_common.ld LDSCRIPT3 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_rom.ld LDSCRIPT4 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_peripherals.ld +ifeq ($(CONFIG_ESP32CORE_RUN_IRAM),y) + LDSCRIPT2 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_iram.ld +else + LDSCRIPT2 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_flash.ld +endif + ifeq ($(WINTOOL),y) # Windows-native toolchains DIRLINK = $(TOPDIR)/tools/copydir.sh diff --git a/configs/esp32-core/scripts/esp32_common.ld b/configs/esp32-core/scripts/esp32_flash.ld similarity index 98% rename from configs/esp32-core/scripts/esp32_common.ld rename to configs/esp32-core/scripts/esp32_flash.ld index ba67d87451..5a1ffe0562 100644 --- a/configs/esp32-core/scripts/esp32_common.ld +++ b/configs/esp32-core/scripts/esp32_flash.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/elf32-core/scripts/esp32_common.ld + * configs/elf32-core/scripts/esp32_flash.ld ****************************************************************************/ /* Default entry point: */ diff --git a/configs/esp32-core/scripts/esp32_iram.ld b/configs/esp32-core/scripts/esp32_iram.ld new file mode 100644 index 0000000000..605ea54e5a --- /dev/null +++ b/configs/esp32-core/scripts/esp32_iram.ld @@ -0,0 +1,191 @@ +/**************************************************************************** + * configs/elf32-core/scripts/esp32_iram.ld + ****************************************************************************/ + +/* Default entry point: */ + +ENTRY(__start); + +SECTIONS +{ + /* Send .iram0 code to iram */ + + .iram0.vectors : + { + /* Vectors go to IRAM */ + + _init_start = ABSOLUTE(.); + + /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ + + . = 0x0; + KEEP(*(.window_vectors.text)); + . = 0x180; + KEEP(*(.xtensa_level2_vector.text)); + . = 0x1c0; + KEEP(*(.xtensa_level3_vector.text)); + . = 0x200; + KEEP(*(.xtensa_level4_vector.text)); + . = 0x240; + KEEP(*(.xtensa_level5_vector.text)); + . = 0x280; + KEEP(*(.debug_exception_vector.text)); + . = 0x2c0; + KEEP(*(.nmi_vector.text)); + . = 0x300; + KEEP(*(.kernel_exception_vector.text)); + . = 0x340; + KEEP(*(.user_exception_vector.text)); + . = 0x3c0; + KEEP(*(.double_exception_vector.text)); + . = 0x400; + *(.*_vector.literal) + + . = ALIGN (16); + *(.entry.text) + *(.init.literal) + *(.init) + _init_end = ABSOLUTE(.); + } > iram0_0_seg + + .iram0.text : + { + /* Code marked as runnning out of IRAM */ + + _iram_text_start = ABSOLUTE(.); + *(.iram1 .iram1.*) + *libphy.a:(.literal .text .literal.* .text.*) + *librtc.a:(.literal .text .literal.* .text.*) + *libpp.a:(.literal .text .literal.* .text.*) + *libhal.a:(.literal .text .literal.* .text.*) + _iram_text_end = ABSOLUTE(.); + + _stext = .; + _text_start = ABSOLUTE(.); + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + _text_end = ABSOLUTE(.); + _etext = .; + + } > iram0_0_seg + + /* Shared RAM */ + + .dram0.bss (NOLOAD) : + { + /* .bss initialized on power-up */ + + . = ALIGN (8); + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + KEEP(*(.bss)) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + _ebss = ABSOLUTE(.); + + /* Uninitialized .bss */ + + *(.noinit) + } >dram0_0_seg + + .dram0.data : + { + /* .data initialized on power-up in ROMed configurations. */ + + _sdata = ABSOLUTE(.); + KEEP(*(.data)) + KEEP(*(.data.*)) + KEEP(*(.gnu.linkonce.d.*)) + KEEP(*(.data1)) + KEEP(*(.sdata)) + KEEP(*(.sdata.*)) + KEEP(*(.gnu.linkonce.s.*)) + KEEP(*(.sdata2)) + KEEP(*(.sdata2.*)) + KEEP(*(.gnu.linkonce.s2.*)) + KEEP(*(.jcr)) + *(.dram1 .dram1.*) + _edata = ABSOLUTE(.); + . = ALIGN(4); + + _srodata = ABSOLUTE(.); + *(.rodata) + *(.rodata.*) + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + *(.eh_frame) + + . = (. + 3) & ~ 3; + + /* C++ constructor and destructor tables, properly ordered: */ + + _sinit = ABSOLUTE(.); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + _einit = ABSOLUTE(.); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + + /* C++ exception handlers table: */ + + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _erodata = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + + /* Heap starts at the end of .data */ + + _sheap = ABSOLUTE(.); + } >dram0_0_seg + + .flash.rodata : + { + } >drom0_0_seg + + .rtc.text : + { + . = ALIGN(4); + *(.rtc.literal .rtc.text) + } >rtc_iram_seg + + .rtc.data : + { + *(.rtc.data) + *(.rtc.rodata) + } > rtc_slow_seg +} diff --git a/configs/esp32-core/smp/Make.defs b/configs/esp32-core/smp/Make.defs index f8901d0f8b..8b4dd25b40 100644 --- a/configs/esp32-core/smp/Make.defs +++ b/configs/esp32-core/smp/Make.defs @@ -38,10 +38,15 @@ include ${TOPDIR}/tools/Config.mk include ${TOPDIR}/arch/xtensa/src/lx6/Toolchain.defs LDSCRIPT1 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_out.ld -LDSCRIPT2 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_common.ld LDSCRIPT3 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_rom.ld LDSCRIPT4 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_peripherals.ld +ifeq ($(CONFIG_ESP32CORE_RUN_IRAM),y) + LDSCRIPT2 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_iram.ld +else + LDSCRIPT2 = $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/esp32_flash.ld +endif + ifeq ($(WINTOOL),y) # Windows-native toolchains DIRLINK = $(TOPDIR)/tools/copydir.sh -- GitLab From 4545af3249485271ad91da1a3200fad35ad134de Mon Sep 17 00:00:00 2001 From: Eunbong Song Date: Tue, 15 Nov 2016 06:47:59 -0600 Subject: [PATCH 410/734] sleep() was returning remaining nanoseconds (kind of), instead the remaining seconds. --- libc/unistd/lib_sleep.c | 22 +--------------------- 1 file changed, 1 insertion(+), 21 deletions(-) diff --git a/libc/unistd/lib_sleep.c b/libc/unistd/lib_sleep.c index 785d76b63b..70f763f0ce 100644 --- a/libc/unistd/lib_sleep.c +++ b/libc/unistd/lib_sleep.c @@ -45,26 +45,6 @@ #include #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Type Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -150,7 +130,7 @@ unsigned int sleep(unsigned int seconds) if (ret < 0) { - remaining = rmtp.tv_nsec; + remaining = rmtp.tv_sec; if (remaining < seconds && rmtp.tv_nsec >= 500000000) { /* Round up */ -- GitLab From a2531cea0c2c276d9054bfa6a21e36513b01088d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 15 Nov 2016 07:28:37 -0600 Subject: [PATCH 411/734] ESP32: Refresh configurations, update README --- configs/esp32-core/README.txt | 22 ++++++++++++++++------ configs/esp32-core/nsh/defconfig | 5 +++-- configs/esp32-core/smp/defconfig | 12 ++++++++---- 3 files changed, 27 insertions(+), 12 deletions(-) diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index 59636eb113..193a51a7dd 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -169,7 +169,7 @@ Memory Map Serial Console ============== - USART0 is, by default, the serial console. It connects to the on-board + UART0 is, by default, the serial console. It connects to the on-board CP2102 converter and is available on the USB connector USB CON8 (J1). Buttons and LEDs @@ -532,14 +532,24 @@ NOTES: 1. These configurations use the mconf-based configuration tool. To change any of these configurations using that tool, you should: - a. Build and install the kconfig-mconf tool. See nuttx/README.txt - see additional README.txt files in the NuttX tools repository. + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository. - b. Execute 'make menuconfig' in nuttx/ in order to start the - reconfiguration process. + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. 2. Unless stated otherwise, all configurations generate console - output on [To be provided]. + output on UART0 (see the "Serial Console" section above). + + 3. By default, these configurations assume a 40MHz crystal on- + board: + + CONFIG_ESP32CORE_XTAL_40MZ=y + # CONFIG_ESP32CORE_XTAL_26MHz is not set + + 4. Default configurations are set to run from FLASH. You will need + to set CONFIG_ESP32CORE_RUN_IRAM=y for now (see the " Executing + and Debugging from FLASH and IRAM" section above). Configuration sub-directories ----------------------------- diff --git a/configs/esp32-core/nsh/defconfig b/configs/esp32-core/nsh/defconfig index 2d68310f33..18cdefc0be 100644 --- a/configs/esp32-core/nsh/defconfig +++ b/configs/esp32-core/nsh/defconfig @@ -172,7 +172,8 @@ CONFIG_ARCH_BOARD="esp32-core" # Board-Specific Options # CONFIG_ESP32CORE_XTAL_40MZ=y -# CONFIG_ESP32CORE_XTAL26MHz is not set +# CONFIG_ESP32CORE_XTAL_26MHz is not set +# CONFIG_ESP32CORE_RUN_IRAM is not set # CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set @@ -599,10 +600,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set diff --git a/configs/esp32-core/smp/defconfig b/configs/esp32-core/smp/defconfig index 403a5e3c8d..d9641480ce 100644 --- a/configs/esp32-core/smp/defconfig +++ b/configs/esp32-core/smp/defconfig @@ -62,6 +62,7 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set @@ -170,6 +171,9 @@ CONFIG_ARCH_BOARD="esp32-core" # # Board-Specific Options # +CONFIG_ESP32CORE_XTAL_40MZ=y +# CONFIG_ESP32CORE_XTAL_26MHz is not set +# CONFIG_ESP32CORE_RUN_IRAM is not set # CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set @@ -302,14 +306,14 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set # CONFIG_SPI_BITBANG is not set @@ -599,10 +603,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set -- GitLab From e2f999a5df3d3e188ca69ffe375ea320b33d0992 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 15 Nov 2016 07:35:30 -0600 Subject: [PATCH 412/734] Update Changelog --- configs/sabre-6quad/README.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/configs/sabre-6quad/README.txt b/configs/sabre-6quad/README.txt index f94614ae63..beb140cd8b 100644 --- a/configs/sabre-6quad/README.txt +++ b/configs/sabre-6quad/README.txt @@ -498,6 +498,15 @@ Open Issues: CPU (which may not be CPU0). Perhaps that should be a spinlock to prohibit execution of interrupts on CPU0 when other CPUs are in a critical section? + 2016-11-15: When the critical section is used to lock a resource that is also + used by interupt handling, I believe that what is required is that the interrupt + handling logic must also take the spinlock. This will cause the interrupt handlers + on other CPUs to spin until leave_critical_section() is called. + + NOTE: Currently enter_critical section takes the spinlock before disabling + (local) interrupts. That orderwould have to change or you could potentially get + deadlocks if the interrupt handler on the same CPU tries to take the spinlock. + 2. Cache Concurency. This is a complex problem. There is logic in place now to clean CPU0 D-cache before starting a new CPU and for invalidating the D-Cache when the new CPU is started. REVISIT: Seems that this should not be necessary. -- GitLab From b53866c8729590c9d585d624cd905cde79c86549 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 15 Nov 2016 07:54:18 -0600 Subject: [PATCH 413/734] sched/irq: Change order for SMP case in enter_critical_section: Disble local interrupts BEFORE taking spinlock. --- configs/sabre-6quad/README.txt | 4 ---- configs/sabre-6quad/nsh/defconfig | 37 ++++++++++++++++++++++++++----- configs/sabre-6quad/smp/defconfig | 36 +++++++++++++++++++++++++----- sched/irq/irq_csection.c | 21 ++++++++++++++---- 4 files changed, 80 insertions(+), 18 deletions(-) diff --git a/configs/sabre-6quad/README.txt b/configs/sabre-6quad/README.txt index beb140cd8b..e784bae735 100644 --- a/configs/sabre-6quad/README.txt +++ b/configs/sabre-6quad/README.txt @@ -503,10 +503,6 @@ Open Issues: handling logic must also take the spinlock. This will cause the interrupt handlers on other CPUs to spin until leave_critical_section() is called. - NOTE: Currently enter_critical section takes the spinlock before disabling - (local) interrupts. That orderwould have to change or you could potentially get - deadlocks if the interrupt handler on the same CPU tries to take the spinlock. - 2. Cache Concurency. This is a complex problem. There is logic in place now to clean CPU0 D-cache before starting a new CPU and for invalidating the D-Cache when the new CPU is started. REVISIT: Seems that this should not be necessary. diff --git a/configs/sabre-6quad/nsh/defconfig b/configs/sabre-6quad/nsh/defconfig index ee0f283912..dfc9ef8d6f 100644 --- a/configs/sabre-6quad/nsh/defconfig +++ b/configs/sabre-6quad/nsh/defconfig @@ -64,10 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -260,11 +263,11 @@ CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_HAVE_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set @@ -289,6 +292,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2016 CONFIG_START_MONTH=3 @@ -301,6 +305,7 @@ CONFIG_PREALLOC_TIMERS=4 # # Tasks and Scheduling # +# CONFIG_SMP is not set # CONFIG_INIT_NONE is not set CONFIG_INIT_ENTRYPOINT=y # CONFIG_INIT_FILEPATH is not set @@ -386,6 +391,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 # CONFIG_DISABLE_POLL is not set CONFIG_DEV_NULL=y CONFIG_DEV_ZERO=y +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -401,12 +407,16 @@ CONFIG_DEV_ZERO=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -414,7 +424,12 @@ CONFIG_DEV_ZERO=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -488,9 +503,12 @@ CONFIG_UART1_2STOP=0 # CONFIG_UART1_IFLOWCONTROL is not set # CONFIG_UART1_OFLOWCONTROL is not set # CONFIG_UART1_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -511,6 +529,7 @@ CONFIG_RAMLOG_SYSLOG=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set # CONFIG_CONSOLE_SYSLOG is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -606,6 +625,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -633,6 +654,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -663,10 +685,11 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set @@ -695,9 +718,9 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -740,6 +763,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -806,12 +830,12 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_LS is not set # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -828,6 +852,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -869,7 +894,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set @@ -879,6 +904,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sabre-6quad/smp/defconfig b/configs/sabre-6quad/smp/defconfig index 4205d00781..23afd07fe9 100644 --- a/configs/sabre-6quad/smp/defconfig +++ b/configs/sabre-6quad/smp/defconfig @@ -64,10 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -263,11 +266,11 @@ CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_HAVE_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set @@ -292,6 +295,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2016 CONFIG_START_MONTH=3 @@ -393,6 +397,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 # CONFIG_DISABLE_POLL is not set CONFIG_DEV_NULL=y CONFIG_DEV_ZERO=y +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -408,12 +413,16 @@ CONFIG_DEV_ZERO=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -421,7 +430,12 @@ CONFIG_DEV_ZERO=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -495,9 +509,12 @@ CONFIG_UART1_2STOP=0 # CONFIG_UART1_IFLOWCONTROL is not set # CONFIG_UART1_OFLOWCONTROL is not set # CONFIG_UART1_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -518,6 +535,7 @@ CONFIG_RAMLOG_SYSLOG=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set # CONFIG_CONSOLE_SYSLOG is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -614,6 +632,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -641,6 +661,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -671,10 +692,11 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set @@ -703,9 +725,9 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -748,6 +770,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -814,12 +837,12 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_LS is not set # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -836,6 +859,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -877,7 +901,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set @@ -887,6 +911,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 4cc2412ae7..115b717a18 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -86,6 +86,21 @@ volatile cpu_set_t g_cpu_irqset; irqstate_t enter_critical_section(void) { FAR struct tcb_s *rtcb; + irqstate_t ret; + + /* Disable interrupts. + * + * NOTE 1: Ideally this should disable interrupts on all CPUs, but most + * architectures only support disabling interrupts on the local CPU. + * NOTE 2: Interrupts may already be disabled, but we call up_irq_save() + * unconditionally because we need to return valid interrupt status in any + * event. + * NOTE 3: We disable local interrupts BEFORE taking the spinlock in order + * to prevent possible waits on the spinlock from interrupt handling on + * the local CPU. + */ + + ret = up_irq_save(); /* Check if we were called from an interrupt handler and that the tasks * lists have been initialized. @@ -133,11 +148,9 @@ irqstate_t enter_critical_section(void) } } - /* Then disable interrupts (they may already be disabled, be we need to - * return valid interrupt status in any event). - */ + /* Return interrupt status */ - return up_irq_save(); + return ret; } #else /* defined(CONFIG_SCHED_INSTRUMENTATION_CSECTION) */ irqstate_t enter_critical_section(void) -- GitLab From 65ab12fbb90accd50bd5602660394568ed18a1a2 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 15 Nov 2016 08:37:58 -0600 Subject: [PATCH 414/734] If SMP is enabled, if any interrupt handler calls enter_critical_section(), it should take the spinlock. --- sched/irq/irq_csection.c | 165 ++++++++++++++++++++++++--------------- 1 file changed, 103 insertions(+), 62 deletions(-) diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 115b717a18..29b917d7b1 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -102,51 +102,72 @@ irqstate_t enter_critical_section(void) ret = up_irq_save(); - /* Check if we were called from an interrupt handler and that the tasks - * lists have been initialized. + /* Verify that the system has sufficient initialized so that the task lists + * are valid. */ - if (!up_interrupt_context() && g_os_initstate >= OSINIT_TASKLISTS) + if (g_os_initstate >= OSINIT_TASKLISTS) { - /* Do we already have interrupts disabled? */ - - rtcb = this_task(); - DEBUGASSERT(rtcb != NULL); + /* If called from an interrupt handler, then just take the spinlock. + * If we are already in a critical section, this will lock the CPU + * in the interrupt handler. Sounds worse than it is. + */ - if (rtcb->irqcount > 0) + if (up_interrupt_context()) { - /* Yes... make sure that the spinlock is set and increment the IRQ - * lock count. + /* We are in an interrupt handler but within a critical section. + * Wait until we can get the spinlock (meaning that we are no + * longer in the critical section). */ - DEBUGASSERT(g_cpu_irqlock == SP_LOCKED && rtcb->irqcount < INT16_MAX); - rtcb->irqcount++; + spin_lock(&g_cpu_irqlock); } else { - /* NO.. Take the spinlock to get exclusive access and set the lock - * count to 1. - * - * We must avoid that case where a context occurs between taking the - * g_cpu_irqlock and disabling interrupts. Also interrupts disables - * must follow a stacked order. We cannot other context switches to - * re-order the enabling/disabling of interrupts. - * - * The scheduler accomplishes this by treating the irqcount like - * lockcount: Both will disable pre-emption. - */ + /* Normal tasking environment. */ + /* Do we already have interrupts disabled? */ + + rtcb = this_task(); + DEBUGASSERT(rtcb != NULL); + + if (rtcb->irqcount > 0) + { + /* Yes... make sure that the spinlock is set and increment the + * IRQ lock count. + */ - spin_setbit(&g_cpu_irqset, this_cpu(), &g_cpu_irqsetlock, - &g_cpu_irqlock); - rtcb->irqcount = 1; + DEBUGASSERT(g_cpu_irqlock == SP_LOCKED && + rtcb->irqcount < INT16_MAX); + rtcb->irqcount++; + } + else + { + /* NO.. Take the spinlock to get exclusive access and set the + * lock count to 1. + * + * We must avoid that case where a context occurs between + * taking the g_cpu_irqlock and disabling interrupts. Also + * interrupts disables must follow a stacked order. We + * cannot other context switches to re-order the enabling/ + * disabling of interrupts. + * + * The scheduler accomplishes this by treating the irqcount + * like lockcount: Both will disable pre-emption. + */ + + spin_setbit(&g_cpu_irqset, this_cpu(), &g_cpu_irqsetlock, + &g_cpu_irqlock); + rtcb->irqcount = 1; #ifdef CONFIG_SCHED_INSTRUMENTATION_CSECTION - /* Note that we have entered the critical section */ + /* Note that we have entered the critical section */ - sched_note_csection(rtcb, true); + sched_note_csection(rtcb, true); #endif + } } - } + } + /* Return interrupt status */ @@ -187,59 +208,79 @@ irqstate_t enter_critical_section(void) #ifdef CONFIG_SMP void leave_critical_section(irqstate_t flags) { - /* Check if we were called from an interrupt handler and that the tasks - * lists have been initialized. + /* Verify that the system has sufficient initialized so that the task lists + * are valid. */ - if (!up_interrupt_context() && g_os_initstate >= OSINIT_TASKLISTS) + if (g_os_initstate >= OSINIT_TASKLISTS) { - FAR struct tcb_s *rtcb = this_task(); - DEBUGASSERT(rtcb != 0 && rtcb->irqcount > 0); - - /* Will we still have interrupts disabled after decrementing the - * count? + /* If called from an interrupt handler, then just take the spinlock. + * If we are already in a critical section, this will lock the CPU + * in the interrupt handler. Sounds worse than it is. */ - if (rtcb->irqcount > 1) + if (up_interrupt_context()) { - /* Yes... make sure that the spinlock is set */ + /* We are in an interrupt handler but within a critical section. + * Wait until we can get the spinlock (meaning that we are no + * longer in the critical section). + */ DEBUGASSERT(g_cpu_irqlock == SP_LOCKED); - rtcb->irqcount--; + spin_unlock(&g_cpu_irqlock); } else { -#ifdef CONFIG_SCHED_INSTRUMENTATION_CSECTION - /* No.. Note that we have entered the critical section */ + FAR struct tcb_s *rtcb = this_task(); + DEBUGASSERT(rtcb != 0 && rtcb->irqcount > 0); - sched_note_csection(rtcb, false); -#endif - /* Decrement our count on the lock. If all CPUs have released, - * then unlock the spinlock. - */ + /* Normal tasking context */ + /* Will we still have interrupts disabled after decrementing the + * count? + */ - rtcb->irqcount = 0; - spin_clrbit(&g_cpu_irqset, this_cpu(), &g_cpu_irqsetlock, - &g_cpu_irqlock); - - /* Have all CPUs release the lock? */ + if (rtcb->irqcount > 1) + { + /* Yes... make sure that the spinlock is set */ - if (!spin_islocked(&g_cpu_irqlock)) + DEBUGASSERT(g_cpu_irqlock == SP_LOCKED); + rtcb->irqcount--; + } + else { - /* Check if there are pending tasks and that pre-emption is - * also enabled. +#ifdef CONFIG_SCHED_INSTRUMENTATION_CSECTION + /* No.. Note that we have entered the critical section */ + + sched_note_csection(rtcb, false); +#endif + /* Decrement our count on the lock. If all CPUs have + * released, then unlock the spinlock. */ - if (g_pendingtasks.head != NULL && !spin_islocked(&g_cpu_schedlock)) + rtcb->irqcount = 0; + spin_clrbit(&g_cpu_irqset, this_cpu(), &g_cpu_irqsetlock, + &g_cpu_irqlock); + + /* Have all CPUs release the lock? */ + + if (!spin_islocked(&g_cpu_irqlock)) { - /* Release any ready-to-run tasks that have collected in - * g_pendingtasks if the scheduler is not locked. - * - * NOTE: This operation has a very high likelihood of causing - * this task to be switched out! + /* Check if there are pending tasks and that pre-emption + * is also enabled. */ - up_release_pending(); + if (g_pendingtasks.head != NULL && + !spin_islocked(&g_cpu_schedlock)) + { + /* Release any ready-to-run tasks that have collected + * in g_pendingtasks if the scheduler is not locked. + * + * NOTE: This operation has a very high likelihood of + * causing this task to be switched out! + */ + + up_release_pending(); + } } } } -- GitLab From 21f92ba601f8286b057f4fc9c1582eef4018fd06 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 15 Nov 2016 09:24:00 -0600 Subject: [PATCH 415/734] Review some SMP logic; update comments; refresh configuration. --- configs/sim/README.txt | 3 --- configs/sim/ostest/defconfig | 22 +++++++++++++++++++--- sched/irq/irq_csection.c | 28 ++++++++++++++++------------ 3 files changed, 35 insertions(+), 18 deletions(-) diff --git a/configs/sim/README.txt b/configs/sim/README.txt index df8a231553..e3712b11f9 100644 --- a/configs/sim/README.txt +++ b/configs/sim/README.txt @@ -243,9 +243,6 @@ SMP You can enable SMP for ostest configuration by enabling: - -# CONFIG_EXPERIMENTAL is not set - +CONFIG_EXPERIMENTAL=y - +CONFIG_SPINLOCK=y +CONFIG_SMP=y +CONFIG_SMP_NCPUS=2 diff --git a/configs/sim/ostest/defconfig b/configs/sim/ostest/defconfig index e48035058d..182af156ed 100644 --- a/configs/sim/ostest/defconfig +++ b/configs/sim/ostest/defconfig @@ -58,10 +58,13 @@ CONFIG_DEBUG_NOOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set CONFIG_ARCH_SIM=y # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="sim" @@ -79,6 +82,7 @@ CONFIG_SIM_NET_HOST_ROUTE=y # CONFIG_SIM_NET_BRIDGE is not set # CONFIG_SIM_FRAMEBUFFER is not set # CONFIG_SIM_SPIFLASH is not set +# CONFIG_SIM_QSPIFLASH is not set # # Architecture Options @@ -168,6 +172,7 @@ CONFIG_ARCH_HAVE_TICKLESS=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2007 CONFIG_START_MONTH=2 @@ -180,6 +185,7 @@ CONFIG_PREALLOC_TIMERS=8 # # Tasks and Scheduling # +# CONFIG_SMP is not set # CONFIG_INIT_NONE is not set CONFIG_INIT_ENTRYPOINT=y # CONFIG_INIT_FILEPATH is not set @@ -262,6 +268,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=8192 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -277,12 +284,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -351,10 +362,12 @@ CONFIG_SERIAL_CONSOLE=y # CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_SERIAL_DMA is not set # CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -456,6 +469,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -501,9 +516,9 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set @@ -535,10 +550,9 @@ CONFIG_EXAMPLES_OSTEST_RR_RANGE=10000 CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 CONFIG_EXAMPLES_OSTEST_WAITRESULT=y # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -577,6 +591,7 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -620,6 +635,7 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 29b917d7b1..67383f4019 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -214,34 +214,38 @@ void leave_critical_section(irqstate_t flags) if (g_os_initstate >= OSINIT_TASKLISTS) { - /* If called from an interrupt handler, then just take the spinlock. - * If we are already in a critical section, this will lock the CPU - * in the interrupt handler. Sounds worse than it is. + /* If called from an interrupt handler, then just release the + * spinlock. The interrupt handling logic should already hold the + * spinlock if enter_critical_section() has been called. Unlocking + * the spinlock will allow interrupt handlers on other CPUs to execute + * again. */ if (up_interrupt_context()) { - /* We are in an interrupt handler but within a critical section. - * Wait until we can get the spinlock (meaning that we are no - * longer in the critical section). - */ + /* We are in an interrupt handler. Release the spinlock. */ DEBUGASSERT(g_cpu_irqlock == SP_LOCKED); - spin_unlock(&g_cpu_irqlock); + if (g_cpu_irqset == 0) + { + spin_unlock(&g_cpu_irqlock); + } } else { FAR struct tcb_s *rtcb = this_task(); DEBUGASSERT(rtcb != 0 && rtcb->irqcount > 0); - /* Normal tasking context */ - /* Will we still have interrupts disabled after decrementing the + /* Normal tasking context. We need to coordinate with other + * tasks. + * + * Will we still have interrupts disabled after decrementing the * count? - */ + */ if (rtcb->irqcount > 1) { - /* Yes... make sure that the spinlock is set */ + /* Yes... the spinlock should remain set */ DEBUGASSERT(g_cpu_irqlock == SP_LOCKED); rtcb->irqcount--; -- GitLab From 23d2915179986f33e6b1444529ba61c2a6ad3d56 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 15 Nov 2016 13:25:30 -0600 Subject: [PATCH 416/734] Update README --- configs/esp32-core/README.txt | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index 193a51a7dd..0688c2aad7 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -285,8 +285,8 @@ OpenOCD for the ESP32 If you do not do the install step, then you will have a localhost version of the OpenOCD binary at openocd-esp32/src. - Running OpenOCD - -------------- + Starting the OpenOCD Server + --------------------------- - cd to openocd-esp32 directory - copy the modified esp32.cfg script to this directory @@ -411,6 +411,18 @@ OpenOCD for the ESP32 Executing and Debugging from FLASH and IRAM =========================================== + Enable Debug Symbols + -------------------- + To debug with GDB, you will need to enable symbols in the build. You do this + with 'make menuconfig' then selecting: + + - "Build Setup" -> "Debug Options" -> "Generate Debug Symbols" + + And, to make debugging easier, also disable optimizations. This will make + your code a lot bigger: + + - "Build Setup" -> "Optimization Level" -> "Suppress Optimization" + FLASH ----- OpenOCD currently doesn't have a FLASH driver for ESP32, so you can load @@ -477,11 +489,11 @@ OpenOCD for the ESP32 for flashing into the board. The command should to convert ELF file to binary image looks as follows: - python esp-idf/components/esptool_py/esptool/esptool.py --chip esp32 elf2image --flash_mode "dio" --flash_freq "40m" --flash_size "2MB" -o app.bin app.elf + python esp-idf/components/esptool_py/esptool/esptool.py --chip esp32 elf2image --flash_mode "dio" --flash_freq "40m" --flash_size "2MB" -o nuttx.bin nuttx To flash binary image to your development board, use the same esptool.py utility: - python esp-idf/components/esptool_py/esptool/esptool.py --chip esp32 --port /dev/ttyUSB0 --baud 921600 write_flash -z --flash_mode dio --flash_freq 40m --flash_size 2MB 0x1000 app.bin + python esp-idf/components/esptool_py/esptool/esptool.py --chip esp32 --port /dev/ttyUSB0 --baud 921600 write_flash -z --flash_mode dio --flash_freq 40m --flash_size 2MB 0x1000 nuttx.bin The argument before app.bin (0x1000) indicates the offset in flash where binary will be written. ROM bootloader expects to find an application (or second stage @@ -551,6 +563,9 @@ NOTES: to set CONFIG_ESP32CORE_RUN_IRAM=y for now (see the " Executing and Debugging from FLASH and IRAM" section above). + To select this option, do 'make menuconfig'. Then you can find + the selection under the "Board Selection" menu as "Run from IRAM". + Configuration sub-directories ----------------------------- -- GitLab From 6683f014445f9ed062649a0e042f1054a98269c0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 15 Nov 2016 13:38:43 -0600 Subject: [PATCH 417/734] Trivial change to comment --- sched/irq/irq_csection.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 67383f4019..ee1c7da234 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -253,7 +253,7 @@ void leave_critical_section(irqstate_t flags) else { #ifdef CONFIG_SCHED_INSTRUMENTATION_CSECTION - /* No.. Note that we have entered the critical section */ + /* No.. Note that we have left the critical section */ sched_note_csection(rtcb, false); #endif -- GitLab From 40d7216a2259990e4922e361844aa8b9c0b78442 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 15 Nov 2016 15:44:43 -0600 Subject: [PATCH 418/734] Back out 65ab12 and parts of 21f92b --- sched/irq/irq_csection.c | 167 ++++++++++++++------------------------- 1 file changed, 61 insertions(+), 106 deletions(-) diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index ee1c7da234..115b717a18 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -102,72 +102,51 @@ irqstate_t enter_critical_section(void) ret = up_irq_save(); - /* Verify that the system has sufficient initialized so that the task lists - * are valid. + /* Check if we were called from an interrupt handler and that the tasks + * lists have been initialized. */ - if (g_os_initstate >= OSINIT_TASKLISTS) + if (!up_interrupt_context() && g_os_initstate >= OSINIT_TASKLISTS) { - /* If called from an interrupt handler, then just take the spinlock. - * If we are already in a critical section, this will lock the CPU - * in the interrupt handler. Sounds worse than it is. - */ + /* Do we already have interrupts disabled? */ + + rtcb = this_task(); + DEBUGASSERT(rtcb != NULL); - if (up_interrupt_context()) + if (rtcb->irqcount > 0) { - /* We are in an interrupt handler but within a critical section. - * Wait until we can get the spinlock (meaning that we are no - * longer in the critical section). + /* Yes... make sure that the spinlock is set and increment the IRQ + * lock count. */ - spin_lock(&g_cpu_irqlock); + DEBUGASSERT(g_cpu_irqlock == SP_LOCKED && rtcb->irqcount < INT16_MAX); + rtcb->irqcount++; } else { - /* Normal tasking environment. */ - /* Do we already have interrupts disabled? */ - - rtcb = this_task(); - DEBUGASSERT(rtcb != NULL); - - if (rtcb->irqcount > 0) - { - /* Yes... make sure that the spinlock is set and increment the - * IRQ lock count. - */ - - DEBUGASSERT(g_cpu_irqlock == SP_LOCKED && - rtcb->irqcount < INT16_MAX); - rtcb->irqcount++; - } - else - { - /* NO.. Take the spinlock to get exclusive access and set the - * lock count to 1. - * - * We must avoid that case where a context occurs between - * taking the g_cpu_irqlock and disabling interrupts. Also - * interrupts disables must follow a stacked order. We - * cannot other context switches to re-order the enabling/ - * disabling of interrupts. - * - * The scheduler accomplishes this by treating the irqcount - * like lockcount: Both will disable pre-emption. - */ + /* NO.. Take the spinlock to get exclusive access and set the lock + * count to 1. + * + * We must avoid that case where a context occurs between taking the + * g_cpu_irqlock and disabling interrupts. Also interrupts disables + * must follow a stacked order. We cannot other context switches to + * re-order the enabling/disabling of interrupts. + * + * The scheduler accomplishes this by treating the irqcount like + * lockcount: Both will disable pre-emption. + */ - spin_setbit(&g_cpu_irqset, this_cpu(), &g_cpu_irqsetlock, - &g_cpu_irqlock); - rtcb->irqcount = 1; + spin_setbit(&g_cpu_irqset, this_cpu(), &g_cpu_irqsetlock, + &g_cpu_irqlock); + rtcb->irqcount = 1; #ifdef CONFIG_SCHED_INSTRUMENTATION_CSECTION - /* Note that we have entered the critical section */ + /* Note that we have entered the critical section */ - sched_note_csection(rtcb, true); + sched_note_csection(rtcb, true); #endif - } } - } - + } /* Return interrupt status */ @@ -208,83 +187,59 @@ irqstate_t enter_critical_section(void) #ifdef CONFIG_SMP void leave_critical_section(irqstate_t flags) { - /* Verify that the system has sufficient initialized so that the task lists - * are valid. + /* Check if we were called from an interrupt handler and that the tasks + * lists have been initialized. */ - if (g_os_initstate >= OSINIT_TASKLISTS) + if (!up_interrupt_context() && g_os_initstate >= OSINIT_TASKLISTS) { - /* If called from an interrupt handler, then just release the - * spinlock. The interrupt handling logic should already hold the - * spinlock if enter_critical_section() has been called. Unlocking - * the spinlock will allow interrupt handlers on other CPUs to execute - * again. + FAR struct tcb_s *rtcb = this_task(); + DEBUGASSERT(rtcb != 0 && rtcb->irqcount > 0); + + /* Will we still have interrupts disabled after decrementing the + * count? */ - if (up_interrupt_context()) + if (rtcb->irqcount > 1) { - /* We are in an interrupt handler. Release the spinlock. */ + /* Yes... make sure that the spinlock is set */ DEBUGASSERT(g_cpu_irqlock == SP_LOCKED); - if (g_cpu_irqset == 0) - { - spin_unlock(&g_cpu_irqlock); - } + rtcb->irqcount--; } else { - FAR struct tcb_s *rtcb = this_task(); - DEBUGASSERT(rtcb != 0 && rtcb->irqcount > 0); +#ifdef CONFIG_SCHED_INSTRUMENTATION_CSECTION + /* No.. Note that we have entered the critical section */ - /* Normal tasking context. We need to coordinate with other - * tasks. - * - * Will we still have interrupts disabled after decrementing the - * count? + sched_note_csection(rtcb, false); +#endif + /* Decrement our count on the lock. If all CPUs have released, + * then unlock the spinlock. */ - if (rtcb->irqcount > 1) - { - /* Yes... the spinlock should remain set */ + rtcb->irqcount = 0; + spin_clrbit(&g_cpu_irqset, this_cpu(), &g_cpu_irqsetlock, + &g_cpu_irqlock); - DEBUGASSERT(g_cpu_irqlock == SP_LOCKED); - rtcb->irqcount--; - } - else - { -#ifdef CONFIG_SCHED_INSTRUMENTATION_CSECTION - /* No.. Note that we have left the critical section */ + /* Have all CPUs release the lock? */ - sched_note_csection(rtcb, false); -#endif - /* Decrement our count on the lock. If all CPUs have - * released, then unlock the spinlock. + if (!spin_islocked(&g_cpu_irqlock)) + { + /* Check if there are pending tasks and that pre-emption is + * also enabled. */ - rtcb->irqcount = 0; - spin_clrbit(&g_cpu_irqset, this_cpu(), &g_cpu_irqsetlock, - &g_cpu_irqlock); - - /* Have all CPUs release the lock? */ - - if (!spin_islocked(&g_cpu_irqlock)) + if (g_pendingtasks.head != NULL && !spin_islocked(&g_cpu_schedlock)) { - /* Check if there are pending tasks and that pre-emption - * is also enabled. + /* Release any ready-to-run tasks that have collected in + * g_pendingtasks if the scheduler is not locked. + * + * NOTE: This operation has a very high likelihood of causing + * this task to be switched out! */ - if (g_pendingtasks.head != NULL && - !spin_islocked(&g_cpu_schedlock)) - { - /* Release any ready-to-run tasks that have collected - * in g_pendingtasks if the scheduler is not locked. - * - * NOTE: This operation has a very high likelihood of - * causing this task to be switched out! - */ - - up_release_pending(); - } + up_release_pending(); } } } -- GitLab From 5ce3b399d596b1955dc2388a55a0570149d2c76e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 15 Nov 2016 16:48:40 -0600 Subject: [PATCH 419/734] Correct some typos in comments --- sched/irq/irq_csection.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 115b717a18..1c8d44de12 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -202,7 +202,7 @@ void leave_critical_section(irqstate_t flags) if (rtcb->irqcount > 1) { - /* Yes... make sure that the spinlock is set */ + /* Yes... Just decrement the count leaving the spinlock set */ DEBUGASSERT(g_cpu_irqlock == SP_LOCKED); rtcb->irqcount--; @@ -210,7 +210,7 @@ void leave_critical_section(irqstate_t flags) else { #ifdef CONFIG_SCHED_INSTRUMENTATION_CSECTION - /* No.. Note that we have entered the critical section */ + /* No.. Note that we have left the critical section */ sched_note_csection(rtcb, false); #endif @@ -222,7 +222,7 @@ void leave_critical_section(irqstate_t flags) spin_clrbit(&g_cpu_irqset, this_cpu(), &g_cpu_irqsetlock, &g_cpu_irqlock); - /* Have all CPUs release the lock? */ + /* Have all CPUs released the lock? */ if (!spin_islocked(&g_cpu_irqlock)) { -- GitLab From 6a875bcb61e9a150b914dc93dd3fe2b38611bfec Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 16 Nov 2016 06:48:13 -0600 Subject: [PATCH 420/734] Xtensa: Add EXPERIMENTAL hooks to support lazy co-processor state restore in the future. --- arch/xtensa/Kconfig | 29 +++++++++++++--- arch/xtensa/src/common/xtensa_coproc.S | 4 +++ arch/xtensa/src/common/xtensa_initialstate.c | 9 +++-- arch/xtensa/src/common/xtensa_user_handler.S | 36 ++++++++++---------- 4 files changed, 54 insertions(+), 24 deletions(-) diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 71be453e17..5c051980e6 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -31,6 +31,30 @@ config ARCH_FAMILY_LX6 Cadence® Tensilica® Xtensa® LX6 data plane processing unit (DPU). The LX6 is a configurable and extensible processor core. +config ARCH_CHIP + string + default "esp32" if ARCH_CHIP_ESP32 + +config XTENSA_CP_LAZY + bool "Lazy co-processor state restoration" + default n + depends on EXPERIMENTAL + ---help--- + NuttX logic saves and restores the co-processor enabled (CPENABLE) + register on each context switch. This has disadvantages in that (1) + co-processor context will be saved and restored even if the co- + processor was never used, and (2) tasks must explicitly enable and + disable co-processors. + + An alternative, "lazy" co-processor state restore is enabled with + this option. That logic works like as follows: + + a. CPENABLE is set to zero on each context switch, disabling all co- + processors. + b. If/when the task attempts to use the disabled co-processor, an + exception occurs + c. The co-processor exception handler re-enables the co-processor. + config XTENSA_USE_OVLY bool default n @@ -41,6 +65,7 @@ config XTENSA_CP_INITSET hex "Default co-processor enables" default 0x0001 range 0 0xffff + depends on !XTENSA_CP_LAZY ---help--- Co-processors may be enabled on a thread by calling xtensa_coproc_enable() and disabled by calling xtensa_coproc_disable(). Some co-processors @@ -48,10 +73,6 @@ config XTENSA_CP_INITSET is provided by CONFIG_XTENSA_CP_INITSET. Each bit corresponds to one coprocessor with the same bit layout as for the CPENABLE register. -config ARCH_CHIP - string - default "esp32" if ARCH_CHIP_ESP32 - source arch/xtensa/src/lx6/Kconfig if ARCH_CHIP_ESP32 source arch/xtensa/src/esp32/Kconfig diff --git a/arch/xtensa/src/common/xtensa_coproc.S b/arch/xtensa/src/common/xtensa_coproc.S index 371959b2de..8b01063bf3 100644 --- a/arch/xtensa/src/common/xtensa_coproc.S +++ b/arch/xtensa/src/common/xtensa_coproc.S @@ -306,7 +306,11 @@ _xtensa_coproc_restorestate: mov a15, a2 /* A15 is now the address of the save area */ +#ifdef CONFIG_XTENSA_CP_LAZY + movi a2, 0 /* a2 = Will disable all coprocessors */ +#else l16ui a2, a15, XTENSA_CPENABLE /* a2 = Which CPs have been enable for this thread? */ +#endif wsr a2, CPENABLE /* Set CPENABLE correctly for this thread */ l16ui a2, a15, XTENSA_CPSTORED /* a2 = Which CPs have been saved for this thread? */ movi a3, 0 /* Clear the ones being restored (all of them) */ diff --git a/arch/xtensa/src/common/xtensa_initialstate.c b/arch/xtensa/src/common/xtensa_initialstate.c index fb74503ad5..b8e14e5161 100644 --- a/arch/xtensa/src/common/xtensa_initialstate.c +++ b/arch/xtensa/src/common/xtensa_initialstate.c @@ -98,10 +98,15 @@ void up_initial_state(struct tcb_s *tcb) #if XCHAL_CP_NUM > 0 /* Set up the co-processors that will be enabled initially when the thread - * starts (see xtensa_coproc.h) + * starts (see xtensa_coproc.h). If the lazy co-processor state restore + * logic is selected, that would be the empty set. */ +#ifdef CONFIG_XTENSA_CP_LAZY + xcp->cpstate.cpenable = 0; /* No co-processors are enabled */ +#else xcp->cpstate.cpenable = (CONFIG_XTENSA_CP_INITSET & XTENSA_CP_ALLSET); - xcp->cpstate.cpstored = 0; /* No coprocessors haved statee saved for this thread */ +#endif + xcp->cpstate.cpstored = 0; /* No co-processors haved state saved */ #endif } diff --git a/arch/xtensa/src/common/xtensa_user_handler.S b/arch/xtensa/src/common/xtensa_user_handler.S index abf043da2b..fc789ccb5a 100644 --- a/arch/xtensa/src/common/xtensa_user_handler.S +++ b/arch/xtensa/src/common/xtensa_user_handler.S @@ -63,12 +63,6 @@ #include #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LAZY_COPROC - /**************************************************************************** * Assembly Language Macros ****************************************************************************/ @@ -144,13 +138,13 @@ _xtensa_to_alloca_handler: _xtensa_to_syscall_handler: call0 _xtensa_syscall_handler /* Jump to syscall exception handler */ -#ifdef HAVE_LAZY_COPROC +#ifdef CONFIG_XTENSA_CP_LAZY #if XCHAL_CP_NUM > 0 .align 4 _xtensa_to_coproc_handler: call0 _xtensa_coproc_handler /* Jump to copressor exception handler */ #endif -#endif /* HAVE_LAZY_COPROC */ +#endif /* CONFIG_XTENSA_CP_LAZY */ /**************************************************************************** * Name: _xtensa_user_handler @@ -173,7 +167,7 @@ _xtensa_user_handler: rsr a0, EXCCAUSE beqi a0, EXCCAUSE_LEVEL1INTERRUPT, _xtensa_to_level1_handler -#ifdef HAVE_LAZY_COPROC +#ifdef CONFIG_XTENSA_CP_LAZY #if XCHAL_CP_NUM > 0 /* Handle any coprocessor exceptions. Rely on the fact that exception * numbers above EXCCAUSE_CP0_DISABLED all relate to the coprocessors. @@ -181,7 +175,7 @@ _xtensa_user_handler: bgeui a0, EXCCAUSE_CP0_DISABLED, _xtensa_to_coproc_handler #endif -#endif /* HAVE_LAZY_COPROC */ +#endif /* CONFIG_XTENSA_CP_LAZY */ /* Handle alloca and syscall exceptions */ @@ -399,11 +393,14 @@ _xtensa_syscall_handler: * NuttX does not currently implement this lazy co-process enable. Rather, * NuttX follows the model: * - * 1. A set of co-processors may be enable when each thread starts as determined by CONFIG_XTENSA_CP_INITSET. - * 2. Additional co-processors may be enabled for the thread by explicitly setting the CPENABLE register when the thread starts. - * 3. Co-processor state, including CPENABLE, is saved an restored on each context switch. + * 1. A set of co-processors may be enable when each thread starts as + * determined by CONFIG_XTENSA_CP_INITSET. + * 2. Additional co-processors may be enabled for the thread by explicitly + * setting the CPENABLE register when the thread starts. + * 3. Co-processor state, including CPENABLE, is saved an restored on each + * context switch. * 4. Any Coprocessor[n]Disabled exceptions result in a system PANIC. - + * * These exceptions are generated by co-processor instructions, which are * only allowed in thread code (not in interrupts or kernel code). This * restriction is deliberately imposed to reduce the burden of state-save/ @@ -414,11 +411,14 @@ _xtensa_syscall_handler: * ****************************************************************************/ -/* Disabled for now: The following logic is redundant. It simply duplicates the - * the logic in _xtensa_user_handler +#ifdef CONFIG_XTENSA_CP_LAZY +/* Lazy co-processor restoration is not implemented. Below, the logic simply + * calls xtensa_user() which will crash the system with an unhandled error + * Duplicates logic above. */ -#ifdef HAVE_LAZY_COPROC +#error Lazy co-processor restoration is not implemented + #if XCHAL_CP_NUM > 0 .type _xtensa_coproc_handler, @function .align 4 @@ -477,4 +477,4 @@ _xtensa_coproc_handler: 1: j 1b #endif /* XCHAL_CP_NUM */ -#endif /* HAVE_LAZY_COPROC */ +#endif /* CONFIG_XTENSA_CP_LAZY */ -- GitLab From 4ca653a1cce8875a195684cbb6b15701a5d78485 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 16 Nov 2016 18:28:35 -0600 Subject: [PATCH 421/734] Add some experimental changes to enter/leave_critical_section to deal with the case where interrupts are disabled only on the local CPU --- sched/irq/irq_csection.c | 196 +++++++++++++++++++++++++++------------ 1 file changed, 136 insertions(+), 60 deletions(-) diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 1c8d44de12..b778de623a 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -102,49 +102,92 @@ irqstate_t enter_critical_section(void) ret = up_irq_save(); - /* Check if we were called from an interrupt handler and that the tasks - * lists have been initialized. + /* Verify that the system has sufficient initialized so that the task lists + * are valid. */ - if (!up_interrupt_context() && g_os_initstate >= OSINIT_TASKLISTS) + if (g_os_initstate >= OSINIT_TASKLISTS) { - /* Do we already have interrupts disabled? */ - - rtcb = this_task(); - DEBUGASSERT(rtcb != NULL); + /* If called from an interrupt handler, then just take the spinlock. + * If we are already in a critical section, this will lock the CPU + * in the interrupt handler. Sounds worse than it is. + */ - if (rtcb->irqcount > 0) + if (up_interrupt_context()) { - /* Yes... make sure that the spinlock is set and increment the IRQ - * lock count. + /* We are in an interrupt handler but within a critical section. How + * can this happen? + * + * 1. We are not in a critical section, OR + * 2. We are in critical section, but up_irq_restore only disables + * interrupts and this interrupt is from the other CPU. + * + * Assert if these conditions are not true. + */ + + DEBUGASSERT(!spin_islocked(&g_cpu_irqlock) || + (g_cpu_set & (1 << this_cpu())) == 0); + + /* Wait until we can get the spinlock (meaning that we are no + * longer in the critical section). */ - DEBUGASSERT(g_cpu_irqlock == SP_LOCKED && rtcb->irqcount < INT16_MAX); - rtcb->irqcount++; + spin_lock(&g_cpu_irqlock); } else { - /* NO.. Take the spinlock to get exclusive access and set the lock - * count to 1. - * - * We must avoid that case where a context occurs between taking the - * g_cpu_irqlock and disabling interrupts. Also interrupts disables - * must follow a stacked order. We cannot other context switches to - * re-order the enabling/disabling of interrupts. - * - * The scheduler accomplishes this by treating the irqcount like - * lockcount: Both will disable pre-emption. - */ + /* Normal tasking environment. */ + /* Do we already have interrupts disabled? */ + + rtcb = this_task(); + DEBUGASSERT(rtcb != NULL); + + if (rtcb->irqcount > 0) + { + /* Yes... make sure that the spinlock is set and increment the + * IRQ lock count. + * + * NOTE: If irqcount > 0 then (1) we are in a critical section, and + * this CPU should hold the lock. + */ + + DEBUGASSERT(spin_islocked(&g_cpu_irqlock) && + (g_cpu_set & (1 << this_cpu())) != 0 && + rtcb->irqcount < INT16_MAX); + rtcb->irqcount++; + } + else + { + /* If we get here with irqcount == 0, then we know that the + * current task running on this CPU is not in a current + * section. However other tasks on other CPUs may be in a + * critical setion. If so, we must wait until they release + * the spinlock. + */ - spin_setbit(&g_cpu_irqset, this_cpu(), &g_cpu_irqsetlock, - &g_cpu_irqlock); - rtcb->irqcount = 1; + DEBUGASSERT((g_cpu_set & (1 << this_cpu())) != 0); /* Really requires g_cpu_irqsetlock */ + spin_lock(&g_cpu_irqset); + + /* The set the lock count to 1. + * + * Interrupts disables must follow a stacked order. We + * cannot other context switches to re-order the enabling + * disabling of interrupts. + * + * The scheduler accomplishes this by treating the irqcount + * like lockcount: Both will disable pre-emption. + */ + + spin_setbit(&g_cpu_irqset, this_cpu(), &g_cpu_irqsetlock, + &g_cpu_irqlock); + rtcb->irqcount = 1; #ifdef CONFIG_SCHED_INSTRUMENTATION_CSECTION - /* Note that we have entered the critical section */ + /* Note that we have entered the critical section */ - sched_note_csection(rtcb, true); + sched_note_csection(rtcb, true); #endif + } } } @@ -187,59 +230,92 @@ irqstate_t enter_critical_section(void) #ifdef CONFIG_SMP void leave_critical_section(irqstate_t flags) { - /* Check if we were called from an interrupt handler and that the tasks - * lists have been initialized. + /* Verify that the system has sufficient initialized so that the task lists + * are valid. */ - if (!up_interrupt_context() && g_os_initstate >= OSINIT_TASKLISTS) + if (g_os_initstate >= OSINIT_TASKLISTS) { - FAR struct tcb_s *rtcb = this_task(); - DEBUGASSERT(rtcb != 0 && rtcb->irqcount > 0); - - /* Will we still have interrupts disabled after decrementing the - * count? + /* If called from an interrupt handler, then just release the + * spinlock. The interrupt handling logic should already hold the + * spinlock if enter_critical_section() has been called. Unlocking + * the spinlock will allow interrupt handlers on other CPUs to execute + * again. */ - if (rtcb->irqcount > 1) + if (up_interrupt_context()) { - /* Yes... Just decrement the count leaving the spinlock set */ + /* We are in an interrupt handler. Release the spinlock. */ DEBUGASSERT(g_cpu_irqlock == SP_LOCKED); - rtcb->irqcount--; + + spin_lock(&g_cpu_irqsetlock); /* Protects g_cpu_irqset */ + if (g_cpu_irqset == 0) + { + spin_unlock(&g_cpu_irqlock); + } + + spin_unlock(&g_cpu_irqsetlock); } else { -#ifdef CONFIG_SCHED_INSTRUMENTATION_CSECTION - /* No.. Note that we have left the critical section */ + FAR struct tcb_s *rtcb = this_task(); + DEBUGASSERT(rtcb != 0 && rtcb->irqcount > 0); - sched_note_csection(rtcb, false); -#endif - /* Decrement our count on the lock. If all CPUs have released, - * then unlock the spinlock. + /* Normal tasking context. We need to coordinate with other + * tasks. + * + * Will we still have interrupts disabled after decrementing the + * count? */ - rtcb->irqcount = 0; - spin_clrbit(&g_cpu_irqset, this_cpu(), &g_cpu_irqsetlock, - &g_cpu_irqlock); - - /* Have all CPUs released the lock? */ + if (rtcb->irqcount > 1) + { + /* Yes... the spinlock should remain set */ - if (!spin_islocked(&g_cpu_irqlock)) + DEBUGASSERT(g_cpu_irqlock == SP_LOCKED); + rtcb->irqcount--; + } + else { - /* Check if there are pending tasks and that pre-emption is - * also enabled. + #ifdef CONFIG_SCHED_INSTRUMENTATION_CSECTION + /* No.. Note that we have left the critical section */ + + sched_note_csection(rtcb, false); +#endif + /* Decrement our count on the lock. If all CPUs have + * released, then unlock the spinlock. */ - if (g_pendingtasks.head != NULL && !spin_islocked(&g_cpu_schedlock)) + DEBUGASSERT(spin_islocked(&g_cpu_irqlock) && + (g_cpu_set & (1 << this_cpu())) != 0); + rtcb->irqcount = 0; + spin_clrbit(&g_cpu_irqset, this_cpu(), &g_cpu_irqsetlock, + &g_cpu_irqlock); + + /* Have all CPUs released the lock? */ + + if (!spin_islocked(&g_cpu_irqlock)) { - /* Release any ready-to-run tasks that have collected in - * g_pendingtasks if the scheduler is not locked. - * - * NOTE: This operation has a very high likelihood of causing - * this task to be switched out! + /* Check if there are pending tasks and that pre-emption + * is also enabled. */ - up_release_pending(); + if (g_pendingtasks.head != NULL && + !spin_islocked(&g_cpu_schedlock)) + { + /* Release any ready-to-run tasks that have collected + * in g_pendingtasks if the scheduler is not locked. + * + * NOTE: This operation has a very high likelihood of + * causing this task to be switched out! + * + * REVISIT: Should this not be done while we are in the + * critical section. + */ + + up_release_pending(); + } } } } -- GitLab From f1e4951a8dab04f4043ec1291f192a7f2e25d051 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 16 Nov 2016 19:11:31 -0600 Subject: [PATCH 422/734] Fix some comments --- sched/irq/irq_csection.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index b778de623a..76a2ecad31 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -102,8 +102,8 @@ irqstate_t enter_critical_section(void) ret = up_irq_save(); - /* Verify that the system has sufficient initialized so that the task lists - * are valid. + /* Verify that the system has sufficiently initialized so that the task + * lists are valid. */ if (g_os_initstate >= OSINIT_TASKLISTS) @@ -115,12 +115,13 @@ irqstate_t enter_critical_section(void) if (up_interrupt_context()) { - /* We are in an interrupt handler but within a critical section. How - * can this happen? + /* We are in an interrupt handler. How can this happen? * - * 1. We are not in a critical section, OR - * 2. We are in critical section, but up_irq_restore only disables - * interrupts and this interrupt is from the other CPU. + * 1. We were not in a critical section when the interrupt + * occurred, OR + * 2. We were in critical section, but up_irq_restore only + * disabled local interrupts on a different CPU; + * Interrupts could still be enabled on this CPU. * * Assert if these conditions are not true. */ @@ -148,7 +149,7 @@ irqstate_t enter_critical_section(void) * IRQ lock count. * * NOTE: If irqcount > 0 then (1) we are in a critical section, and - * this CPU should hold the lock. + * (2) this CPU should hold the lock. */ DEBUGASSERT(spin_islocked(&g_cpu_irqlock) && @@ -161,7 +162,7 @@ irqstate_t enter_critical_section(void) /* If we get here with irqcount == 0, then we know that the * current task running on this CPU is not in a current * section. However other tasks on other CPUs may be in a - * critical setion. If so, we must wait until they release + * critical section. If so, we must wait until they release * the spinlock. */ @@ -198,7 +199,7 @@ irqstate_t enter_critical_section(void) #else /* defined(CONFIG_SCHED_INSTRUMENTATION_CSECTION) */ irqstate_t enter_critical_section(void) { - /* Check if we were called from an interrupt handler and that the tasks + /* Check if we were called from an interrupt handler and that the task * lists have been initialized. */ @@ -230,8 +231,8 @@ irqstate_t enter_critical_section(void) #ifdef CONFIG_SMP void leave_critical_section(irqstate_t flags) { - /* Verify that the system has sufficient initialized so that the task lists - * are valid. + /* Verify that the system has sufficiently initialized so that the task + * lists are valid. */ if (g_os_initstate >= OSINIT_TASKLISTS) @@ -247,7 +248,7 @@ void leave_critical_section(irqstate_t flags) { /* We are in an interrupt handler. Release the spinlock. */ - DEBUGASSERT(g_cpu_irqlock == SP_LOCKED); + DEBUGASSERT(spin_islocked(&g_cpu_irqlock)); spin_lock(&g_cpu_irqsetlock); /* Protects g_cpu_irqset */ if (g_cpu_irqset == 0) @@ -273,7 +274,7 @@ void leave_critical_section(irqstate_t flags) { /* Yes... the spinlock should remain set */ - DEBUGASSERT(g_cpu_irqlock == SP_LOCKED); + DEBUGASSERT(spin_islocked(&g_cpu_irqlock)); rtcb->irqcount--; } else -- GitLab From 16f0b8fa962b2a9bcdc21507a63191caf50b0711 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 16 Nov 2016 19:58:51 -0600 Subject: [PATCH 423/734] Fix typos in DEBUASSERT statements --- sched/irq/irq_csection.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 76a2ecad31..b217aa33bd 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -127,7 +127,7 @@ irqstate_t enter_critical_section(void) */ DEBUGASSERT(!spin_islocked(&g_cpu_irqlock) || - (g_cpu_set & (1 << this_cpu())) == 0); + (g_cpu_irqset & (1 << this_cpu())) == 0); /* Wait until we can get the spinlock (meaning that we are no * longer in the critical section). @@ -153,7 +153,7 @@ irqstate_t enter_critical_section(void) */ DEBUGASSERT(spin_islocked(&g_cpu_irqlock) && - (g_cpu_set & (1 << this_cpu())) != 0 && + (g_cpu_irqset & (1 << this_cpu())) != 0 && rtcb->irqcount < INT16_MAX); rtcb->irqcount++; } @@ -166,7 +166,7 @@ irqstate_t enter_critical_section(void) * the spinlock. */ - DEBUGASSERT((g_cpu_set & (1 << this_cpu())) != 0); /* Really requires g_cpu_irqsetlock */ + DEBUGASSERT((g_cpu_irqset & (1 << this_cpu())) != 0); /* Really requires g_cpu_irqsetlock */ spin_lock(&g_cpu_irqset); /* The set the lock count to 1. @@ -289,7 +289,7 @@ void leave_critical_section(irqstate_t flags) */ DEBUGASSERT(spin_islocked(&g_cpu_irqlock) && - (g_cpu_set & (1 << this_cpu())) != 0); + (g_cpu_irqset & (1 << this_cpu())) != 0); rtcb->irqcount = 0; spin_clrbit(&g_cpu_irqset, this_cpu(), &g_cpu_irqsetlock, &g_cpu_irqlock); -- GitLab From 0c3207e86ede19592e6950b11b7cd01f917d6658 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 16 Nov 2016 21:48:27 -0600 Subject: [PATCH 424/734] Fix backward logic in an assertion. --- sched/irq/irq_csection.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index b217aa33bd..6dadf92559 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -166,7 +166,7 @@ irqstate_t enter_critical_section(void) * the spinlock. */ - DEBUGASSERT((g_cpu_irqset & (1 << this_cpu())) != 0); /* Really requires g_cpu_irqsetlock */ + DEBUGASSERT((g_cpu_irqset & (1 << this_cpu())) == 0); /* Really requires g_cpu_irqsetlock */ spin_lock(&g_cpu_irqset); /* The set the lock count to 1. @@ -261,7 +261,7 @@ void leave_critical_section(irqstate_t flags) else { FAR struct tcb_s *rtcb = this_task(); - DEBUGASSERT(rtcb != 0 && rtcb->irqcount > 0); + DEBUGASSERT(rtcb != NULL && rtcb->irqcount > 0); /* Normal tasking context. We need to coordinate with other * tasks. -- GitLab From 1c1564f0c1307becf4dd1ac055544f0090bf3030 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 16 Nov 2016 22:45:08 -0600 Subject: [PATCH 425/734] Add logic to handled nested calls to enter_critical_section() from interrupts handlers (with SMP). --- sched/irq/irq_csection.c | 68 +++++++++++++++++++++++++++++++--------- 1 file changed, 54 insertions(+), 14 deletions(-) diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 6dadf92559..00dc092434 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -66,6 +66,10 @@ volatile spinlock_t g_cpu_irqlock = SP_UNLOCKED; volatile spinlock_t g_cpu_irqsetlock; volatile cpu_set_t g_cpu_irqset; + +/* Handles nested calls to enter_critical section from interrupt handlers */ + +volatile uint8_t g_cpu_nestcount[CONFIG_SMP_NCPUS]; #endif /**************************************************************************** @@ -115,6 +119,8 @@ irqstate_t enter_critical_section(void) if (up_interrupt_context()) { + int cpu = this_cpu(); + /* We are in an interrupt handler. How can this happen? * * 1. We were not in a critical section when the interrupt @@ -122,18 +128,34 @@ irqstate_t enter_critical_section(void) * 2. We were in critical section, but up_irq_restore only * disabled local interrupts on a different CPU; * Interrupts could still be enabled on this CPU. - * - * Assert if these conditions are not true. */ - DEBUGASSERT(!spin_islocked(&g_cpu_irqlock) || - (g_cpu_irqset & (1 << this_cpu())) == 0); - - /* Wait until we can get the spinlock (meaning that we are no - * longer in the critical section). + /* Handle nested calls to enter_critical_section() from the same + * interrupt. */ - spin_lock(&g_cpu_irqlock); + if (g_cpu_nestcount[cpu] > 0) + { + DEBUGASSERT(spin_islocked(&g_cpu_irqlock) && + g_cpu_nestcount[cpu] < UINT8_MAX); + g_cpu_nestcount[cpu]++; + } + else + { + /* First call enter_critical_section. Test assumptions, then + * wait until we have the lock. + */ + + DEBUGASSERT(!spin_islocked(&g_cpu_irqlock) || + (g_cpu_irqset & (1 << this_cpu())) == 0); + + /* Wait until we can get the spinlock (meaning that we are no + * longer in the critical section). + */ + + spin_lock(&g_cpu_irqlock); + g_cpu_nestcount[cpu] = 1; + } } else { @@ -246,17 +268,35 @@ void leave_critical_section(irqstate_t flags) if (up_interrupt_context()) { - /* We are in an interrupt handler. Release the spinlock. */ + int cpu = this_cpu(); - DEBUGASSERT(spin_islocked(&g_cpu_irqlock)); + /* We are in an interrupt handler. Check if the last call to + * enter_critical_section() was nested. + */ - spin_lock(&g_cpu_irqsetlock); /* Protects g_cpu_irqset */ - if (g_cpu_irqset == 0) + if (g_cpu_nestcount[cpu] > 1) { - spin_unlock(&g_cpu_irqlock); + /* Yes.. then just decrement the nesting count */ + + DEBUGASSERT(spin_islocked(&g_cpu_irqlock)); + g_cpu_nestcount[cpu]--; } + else + { + /* No, not nested. Release the spinlock. */ - spin_unlock(&g_cpu_irqsetlock); + DEBUGASSERT(spin_islocked(&g_cpu_irqlock) && + g_cpu_nestcount[cpu] == 1); + + spin_lock(&g_cpu_irqsetlock); /* Protects g_cpu_irqset */ + if (g_cpu_irqset == 0) + { + spin_unlock(&g_cpu_irqlock); + } + + spin_unlock(&g_cpu_irqsetlock); + g_cpu_nestcount[cpu] = 0; + } } else { -- GitLab From ccdc11d8ff11d0ac68e6bf35ef00c644d6dec409 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 17 Nov 2016 06:37:24 -0600 Subject: [PATCH 426/734] Fix typo in variable naming. g_cpu_irqset should be g_cpu_irqlock. --- sched/irq/irq_csection.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 00dc092434..b5a2f91364 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -66,10 +66,16 @@ volatile spinlock_t g_cpu_irqlock = SP_UNLOCKED; volatile spinlock_t g_cpu_irqsetlock; volatile cpu_set_t g_cpu_irqset; +#endif +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_SMP /* Handles nested calls to enter_critical section from interrupt handlers */ -volatile uint8_t g_cpu_nestcount[CONFIG_SMP_NCPUS]; +static uint8_t g_cpu_nestcount[CONFIG_SMP_NCPUS]; #endif /**************************************************************************** @@ -91,6 +97,7 @@ irqstate_t enter_critical_section(void) { FAR struct tcb_s *rtcb; irqstate_t ret; + int cpu; /* Disable interrupts. * @@ -119,8 +126,6 @@ irqstate_t enter_critical_section(void) if (up_interrupt_context()) { - int cpu = this_cpu(); - /* We are in an interrupt handler. How can this happen? * * 1. We were not in a critical section when the interrupt @@ -134,6 +139,7 @@ irqstate_t enter_critical_section(void) * interrupt. */ + cpu = this_cpu(); if (g_cpu_nestcount[cpu] > 0) { DEBUGASSERT(spin_islocked(&g_cpu_irqlock) && @@ -147,7 +153,7 @@ irqstate_t enter_critical_section(void) */ DEBUGASSERT(!spin_islocked(&g_cpu_irqlock) || - (g_cpu_irqset & (1 << this_cpu())) == 0); + (g_cpu_irqset & (1 << cpu)) == 0); /* Wait until we can get the spinlock (meaning that we are no * longer in the critical section). @@ -188,8 +194,9 @@ irqstate_t enter_critical_section(void) * the spinlock. */ - DEBUGASSERT((g_cpu_irqset & (1 << this_cpu())) == 0); /* Really requires g_cpu_irqsetlock */ - spin_lock(&g_cpu_irqset); + cpu = this_cpu(); + DEBUGASSERT((g_cpu_irqset & (1 << cpu)) == 0); + spin_lock(&g_cpu_irqlock); /* The set the lock count to 1. * @@ -201,7 +208,7 @@ irqstate_t enter_critical_section(void) * like lockcount: Both will disable pre-emption. */ - spin_setbit(&g_cpu_irqset, this_cpu(), &g_cpu_irqsetlock, + spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock, &g_cpu_irqlock); rtcb->irqcount = 1; @@ -253,6 +260,8 @@ irqstate_t enter_critical_section(void) #ifdef CONFIG_SMP void leave_critical_section(irqstate_t flags) { + int cpu; + /* Verify that the system has sufficiently initialized so that the task * lists are valid. */ @@ -268,12 +277,11 @@ void leave_critical_section(irqstate_t flags) if (up_interrupt_context()) { - int cpu = this_cpu(); - /* We are in an interrupt handler. Check if the last call to * enter_critical_section() was nested. */ + cpu = this_cpu(); if (g_cpu_nestcount[cpu] > 1) { /* Yes.. then just decrement the nesting count */ @@ -328,10 +336,12 @@ void leave_critical_section(irqstate_t flags) * released, then unlock the spinlock. */ + cpu = this_cpu(); DEBUGASSERT(spin_islocked(&g_cpu_irqlock) && - (g_cpu_irqset & (1 << this_cpu())) != 0); + (g_cpu_irqset & (1 << cpu)) != 0); + rtcb->irqcount = 0; - spin_clrbit(&g_cpu_irqset, this_cpu(), &g_cpu_irqsetlock, + spin_clrbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock, &g_cpu_irqlock); /* Have all CPUs released the lock? */ -- GitLab From 2c314464a8eab05cc3fd8d2ab4a8e870d924fbcd Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 17 Nov 2016 08:03:45 -0600 Subject: [PATCH 427/734] Fix a typo in a comment --- sched/irq/irq_csection.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index b5a2f91364..1167eba4e9 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -188,7 +188,7 @@ irqstate_t enter_critical_section(void) else { /* If we get here with irqcount == 0, then we know that the - * current task running on this CPU is not in a current + * current task running on this CPU is not in a critical * section. However other tasks on other CPUs may be in a * critical section. If so, we must wait until they release * the spinlock. -- GitLab From bb19f1b499a0fab5578ab84312f350ab8c6b18de Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 17 Nov 2016 10:04:22 -0600 Subject: [PATCH 428/734] spinlocks should be volatile. --- arch/arm/src/armv7-a/arm_cpupause.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_cpupause.c b/arch/arm/src/armv7-a/arm_cpupause.c index 585d574b06..7689598b55 100644 --- a/arch/arm/src/armv7-a/arm_cpupause.c +++ b/arch/arm/src/armv7-a/arm_cpupause.c @@ -55,8 +55,8 @@ * Private Data ****************************************************************************/ -static spinlock_t g_cpu_wait[CONFIG_SMP_NCPUS]; -static spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS]; +static volatile spinlock_t g_cpu_wait[CONFIG_SMP_NCPUS]; +static volatile spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS]; /**************************************************************************** * Public Functions -- GitLab From 10af1e173475d0c701f3101495a41d37a5435255 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 17 Nov 2016 11:50:58 -0600 Subject: [PATCH 429/734] sabre-6quad: Update TODO list --- configs/sabre-6quad/README.txt | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/configs/sabre-6quad/README.txt b/configs/sabre-6quad/README.txt index e784bae735..4284c6de2a 100644 --- a/configs/sabre-6quad/README.txt +++ b/configs/sabre-6quad/README.txt @@ -498,10 +498,11 @@ Open Issues: CPU (which may not be CPU0). Perhaps that should be a spinlock to prohibit execution of interrupts on CPU0 when other CPUs are in a critical section? - 2016-11-15: When the critical section is used to lock a resource that is also - used by interupt handling, I believe that what is required is that the interrupt - handling logic must also take the spinlock. This will cause the interrupt handlers - on other CPUs to spin until leave_critical_section() is called. + 2016-11-17: A fix was added to sched/irq/irq_csection that should correct this + problem. When the critical section is used to lock a resource that is also used by + interupt handling, the interrupt handling logic must also take the spinlock. This + will cause the interrupt handlers on other CPUs to spin until leave_critical_section() + is called. More verification is needed, however. 2. Cache Concurency. This is a complex problem. There is logic in place now to clean CPU0 D-cache before starting a new CPU and for invalidating the D-Cache @@ -537,6 +538,19 @@ Open Issues: PMD_SECT_DOM(0) | PMD_SECT_XN) #define MMU_STRONGLY_ORDERED (PMD_TYPE_SECT | PMD_SECT_AP_RW1 | \ + Another alternative would be to place all spinlocks in a non-cachable memory + region. That is problem what will have to be done. + + This is a VERIFIED PROBLEM: I have seen cases where CPU0 sets a spinlock=1 then + tries to lock the spinlock. CPU0 will wait in this case until CPU1 unlocks the + spinlock. Most of this happens correctly; I can see that CPU1 does set the + spinlock=0, but CPU0 never sees the change and spins forever. That is surely + a consequence of cache issues. + + This was observed between up_cpu_pause() and arm_pause_handler() with the + spinlock "g_cpu_paused[cpu]". CPU1 correctly sets g_cpu_paused[cpu] to zero + but CPU0 never sees the change. + 3. Assertions. On a fatal assertions, other CPUs need to be stopped. The SCR, however, only supports disabling CPUs 1 through 3. Perhaps if the assertion occurs on CPUn, n > 0, then it should use and SGI to perform the assertion -- GitLab From ecb2d4cbc19949759021315bdc1a6280c9ecb769 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 17 Nov 2016 11:52:42 -0600 Subject: [PATCH 430/734] drivers/timer: Remove the TIOC_SETHANDLER IOCTL call. This calls directly from the timer driver into application code. That is non-standard, non-portable, and cannot be supported --- TODO | 12 +---- drivers/timers/timer.c | 95 ++++++++++++++++++++---------------- include/nuttx/timers/timer.h | 39 ++++++++++----- 3 files changed, 84 insertions(+), 62 deletions(-) diff --git a/TODO b/TODO index aa048fde33..3d54ecf7f7 100644 --- a/TODO +++ b/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated November 2, 2016) +NuttX TODO List (Last updated November 17, 2016) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with @@ -15,7 +15,7 @@ nuttx/: (3) Signals (sched/signal, arch/) (2) pthreads (sched/pthread) (0) Message Queues (sched/mqueue) - (9) Kernel/Protected Build + (8) Kernel/Protected Build (3) C++ Support (6) Binary loaders (binfmt/) (12) Network (net/, drivers/net) @@ -683,14 +683,6 @@ o Kernel/Protected Build improvement. However, there is no strong motivation now do do that partitioning work. - Title: TIMER INTERRUPT CALLBACK - Description: The timer upper half driver at drivers/timers/timer.c performs - interrupt level callbacks into applications. This, of course, - will never work in anything but a non-secure, flat build. - Status: Open - Priority: Medium. The driver is only usable with all of its features - in a FLAT build. - Title: USER MODE TASKS CAN MODIFY PRIVILEGED TASKS Description: Certain interfaces, such as sched_setparam(), sched_setscheduler(), etc. can be used by user mode tasks to diff --git a/drivers/timers/timer.c b/drivers/timers/timer.c index 0186e9977f..ebe58dcd2f 100644 --- a/drivers/timers/timer.c +++ b/drivers/timers/timer.c @@ -322,46 +322,6 @@ static int timer_ioctl(FAR struct file *filep, int cmd, unsigned long arg) } break; - /* cmd: TCIOC_SETHANDLER - * Description: Call this handler on timeout - * Argument: A pointer to struct timer_sethandler_s. - * - * NOTE: This ioctl cannot be support in the kernel build mode. In that - * case direct callbacks from kernel space into user space is forbidden. - */ - -#if !defined(CONFIG_BUILD_PROTECTED) && !defined(CONFIG_BUILD_KERNEL) - case TCIOC_SETHANDLER: - { - FAR struct timer_sethandler_s *sethandler; - - /* Don't reset on timer timeout; instead, call this user - * provider timeout handler. NOTE: Providing handler==NULL will - * restore the reset behavior. - */ - - if (lower->ops->sethandler) /* Optional */ - { - sethandler = (FAR struct timer_sethandler_s *)((uintptr_t)arg); - if (sethandler) - { - sethandler->oldhandler = - lower->ops->sethandler(lower, sethandler->newhandler); - ret = OK; - } - else - { - ret = -EINVAL; - } - } - else - { - ret = -ENOSYS; - } - } - break; -#endif - /* Any unrecognized IOCTL commands might be platform-specific ioctl commands */ default: @@ -496,8 +456,8 @@ void timer_unregister(FAR void *handle) /* Recover the pointer to the upper-half driver state */ upper = (FAR struct timer_upperhalf_s *)handle; + DEBUGASSERT(upper != NULL && upper->lower != NULL); lower = upper->lower; - DEBUGASSERT(upper && lower); tmrinfo("Unregistering: %s\n", upper->path); @@ -516,4 +476,57 @@ void timer_unregister(FAR void *handle) kmm_free(upper); } +/**************************************************************************** + * Name: timer_sethandler + * + * Description: + * This function can be called to add a callback into driver-related code + * to handle timer expirations. This is a strictly OS internal interface + * and may NOT be used by appliction code. + * + * Input parameters: + * handle - This is the handle that was returned by timer_register() + * newhandler - The new timer interrupt handler + * oldhandler - The previous timer interrupt handler (if any) + * + * Returned Value: + * None + * + ****************************************************************************/ + +int timer_sethandler(FAR void *handle, tccb_t newhandler, + FAR tccb_t *oldhandler) +{ + FAR struct timer_upperhalf_s *upper; + FAR struct timer_lowerhalf_s *lower; + tccb_t tmphandler; + + /* Recover the pointer to the upper-half driver state */ + + upper = (FAR struct timer_upperhalf_s *)handle; + DEBUGASSERT(upper != NULL && upper->lower != NULL); + lower = upper->lower; + DEBUGASSERT(lower->ops != NULL); + + /* Check if the lower half driver supports the sethandler method */ + + if (lower->ops->sethandler != NULL) /* Optional */ + { + /* Yes.. Defer the hander attachment to the lower half driver */ + + tmphandler = lower->ops->sethandler(lower, newhandler); + + /* Return the oldhandler if a location to return it was provided */ + + if (oldhandler != NULL) + { + *oldhandler = tmphandler; + } + + return OK; + } + + return -ENOSYS; +} + #endif /* CONFIG_TIMER */ diff --git a/include/nuttx/timers/timer.h b/include/nuttx/timers/timer.h index 8df658376a..77946327fc 100644 --- a/include/nuttx/timers/timer.h +++ b/include/nuttx/timers/timer.h @@ -68,8 +68,6 @@ * Argument: A writeable pointer to struct timer_status_s. * TCIOC_SETTIMEOUT - Reset the timer timeout to this value * Argument: A 32-bit timeout value in microseconds. - * TCIOC_SETHANDLER - Call this handler on timer expiration - * Argument: A pointer to struct timer_sethandler_s. * * WARNING: May change TCIOC_SETTIMEOUT to pass pointer to 64bit nanoseconds * or timespec structure. @@ -105,15 +103,7 @@ * function can modify the next interval if desired. */ -typedef bool (*tccb_t)(FAR uint32_t *next_interval_us); - -/* This is the type of the argument passed to the TCIOC_SETHANDLER ioctl */ - -struct timer_sethandler_s -{ - CODE tccb_t newhandler; /* The new timer interrupt handler */ - CODE tccb_t oldhandler; /* The previous timer interrupt handler (if any) */ -}; +typedef CODE bool (*tccb_t)(FAR uint32_t *next_interval_us); /* This is the type of the argument passed to the TCIOC_GETSTATUS ioctl and * and returned by the "lower half" getstatus() method. @@ -254,6 +244,33 @@ FAR void *timer_register(FAR const char *path, void timer_unregister(FAR void *handle); +/**************************************************************************** + * Kernal internal interfaces. Thse may not be used by application logic + ****************************************************************************/ + +/**************************************************************************** + * Name: timer_sethandler + * + * Description: + * This function can be called to add a callback into driver-related code + * to handle timer expirations. This is a strictly OS internal interface + * and may NOT be used by appliction code. + * + * Input parameters: + * handle - This is the handle that was returned by timer_register() + * newhandler - The new timer interrupt handler + * oldhandler - The previous timer interrupt handler (if any) + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef __KERNEL__ +int timer_sethandler(FAR void *handle, tccb_t newhandler, + FAR tccb_t *oldhandler); +#endif + /**************************************************************************** * Platform-Independent "Lower-Half" Timer Driver Interfaces ****************************************************************************/ -- GitLab From d4a048c0c650ecb283843feaefea7f32aea91a8a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 17 Nov 2016 12:41:11 -0600 Subject: [PATCH 431/734] Timer driver: Add hooks to support signal notification of timer expiration. Commented out because invasive interface changes would also be required to complete the implementation. --- drivers/timers/timer.c | 83 +++++++++++++++++++++++++++++++++--- include/nuttx/timers/timer.h | 55 +++++++++++++++++------- 2 files changed, 116 insertions(+), 22 deletions(-) diff --git a/drivers/timers/timer.c b/drivers/timers/timer.c index ebe58dcd2f..16c85fa5d7 100644 --- a/drivers/timers/timer.c +++ b/drivers/timers/timer.c @@ -65,8 +65,13 @@ struct timer_upperhalf_s { - uint8_t crefs; /* The number of times the device has been opened */ - FAR char *path; /* Registration path */ + uint8_t crefs; /* The number of times the device has been opened */ +#ifdef HAVE_NOTIFICATION + uint8_t signal; /* The signal number to use in the notification */ + pid_t pid; /* The ID of the task/thread to receive the signal */ + FAR void *arg; /* An argument to pass with the signal */ +#endif + FAR char *path; /* Registration path */ /* The contained lower-half driver */ @@ -77,6 +82,12 @@ struct timer_upperhalf_s * Private Function Prototypes ****************************************************************************/ +#ifdef HAVE_NOTIFICATION + /* REVISIT: This function prototype is insufficient to support signaling */ + +static bool timer_notifier(FAR uint32_t *next_interval_us); +#endif + static int timer_open(FAR struct file *filep); static int timer_close(FAR struct file *filep); static ssize_t timer_read(FAR struct file *filep, FAR char *buffer, @@ -110,6 +121,36 @@ static const struct file_operations g_timerops = * Private Functions ****************************************************************************/ +/************************************************************************************ + * Name: timer_notifier + * + * Description: + * Notify the application via a signal when the timer interrupt occurs + * + * REVISIT: This function prototype is insufficient to support signaling + * + ************************************************************************************/ + +#ifdef HAVE_NOTIFICATION +static bool timer_notifier(FAR uint32_t *next_interval_us) +{ + FAR struct timer_upperhalf_s *upper = HOW?; +#ifdef CONFIG_CAN_PASS_STRUCTS + union sigval value; +#endif + int ret; + +#ifdef CONFIG_CAN_PASS_STRUCTS + value.sival_ptr = upper->arg; + ret = sigqueue(upper->pid, upper->signo, value); +#else + ret = sigqueue(upper->pid, upper->signo, upper->arg); +#endif + + return ret == OK; +} +#endif + /************************************************************************************ * Name: timer_open * @@ -120,10 +161,10 @@ static const struct file_operations g_timerops = static int timer_open(FAR struct file *filep) { - FAR struct inode *inode = filep->f_inode; + FAR struct inode *inode = filep->f_inode; FAR struct timer_upperhalf_s *upper = inode->i_private; - uint8_t tmp; - int ret; + uint8_t tmp; + int ret; tmrinfo("crefs: %d\n", upper->crefs); @@ -322,6 +363,36 @@ static int timer_ioctl(FAR struct file *filep, int cmd, unsigned long arg) } break; +#ifdef HAVE_NOTIFICATION + /* cmd: TCIOC_NOTIFICATION + * Description: Notify application via a signal when the timer expires. + * Argument: signal number + * + * NOTE: This ioctl cannot be support in the kernel build mode. In that + * case direct callbacks from kernel space into user space is forbidden. + */ + + case TCIOC_NOTIFICATION: + { + FAR struct timer_notify_s *notify = + (FAR struct timer_notify_s *)((uintptr_t)arg) + + if (notify != NULL) + { + upper->signo = notify->signal; + upper->get = notify->signal; + upper->arg = noify->arg; + + ret = timer_sethandler((FAR void *handle)upper, timer_notifier, NULL); + } + else + { + ret = -EINVAL; + } + } + break; +#endif + /* Any unrecognized IOCTL commands might be platform-specific ioctl commands */ default: @@ -500,7 +571,7 @@ int timer_sethandler(FAR void *handle, tccb_t newhandler, FAR struct timer_upperhalf_s *upper; FAR struct timer_lowerhalf_s *lower; tccb_t tmphandler; - + /* Recover the pointer to the upper-half driver state */ upper = (FAR struct timer_upperhalf_s *)handle; diff --git a/include/nuttx/timers/timer.h b/include/nuttx/timers/timer.h index 77946327fc..eb2830bd56 100644 --- a/include/nuttx/timers/timer.h +++ b/include/nuttx/timers/timer.h @@ -52,6 +52,12 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +/* It would require some interface modifcations in order to support + * notifications. + */ + +#undef HAVE_NOTIFICATION + /* IOCTL Commands ***********************************************************/ /* The timer driver uses a standard character driver framework. However, * since the timer driver is a device control interface and not a data @@ -60,14 +66,18 @@ * * These are detected and handled by the "upper half" timer driver. * - * TCIOC_START - Start the timer - * Argument: Ignored - * TCIOC_STOP - Stop the timer - * Argument: Ignored - * TCIOC_GETSTATUS - Get the status of the timer. - * Argument: A writeable pointer to struct timer_status_s. - * TCIOC_SETTIMEOUT - Reset the timer timeout to this value - * Argument: A 32-bit timeout value in microseconds. + * TCIOC_START - Start the timer + * Argument: Ignored + * TCIOC_STOP - Stop the timer + * Argument: Ignored + * TCIOC_GETSTATUS - Get the status of the timer. + * Argument: A writeable pointer to struct timer_status_s. + * TCIOC_SETTIMEOUT - Reset the timer timeout to this value + * Argument: A 32-bit timeout value in microseconds. + * TCIOC_NOTIFICATION - Set up to notify an application via a signal when + * the timer expires. + * Argument: A read-only pointer to an instance of + * stuct timer_notify_s. * * WARNING: May change TCIOC_SETTIMEOUT to pass pointer to 64bit nanoseconds * or timespec structure. @@ -82,18 +92,20 @@ * range. */ -#define TCIOC_START _TCIOC(0x0001) -#define TCIOC_STOP _TCIOC(0x0002) -#define TCIOC_GETSTATUS _TCIOC(0x0003) -#define TCIOC_SETTIMEOUT _TCIOC(0x0004) -#define TCIOC_SETHANDLER _TCIOC(0x0005) +#define TCIOC_START _TCIOC(0x0001) +#define TCIOC_STOP _TCIOC(0x0002) +#define TCIOC_GETSTATUS _TCIOC(0x0003) +#define TCIOC_SETTIMEOUT _TCIOC(0x0004) +#ifdef HAVE_NOTIFICATION +#define TCIOC_NOTIFICATION _TCIOC(0x0005) +#endif /* Bit Settings *************************************************************/ /* Bit settings for the struct timer_status_s flags field */ -#define TCFLAGS_ACTIVE (1 << 0) /* 1=The timer is running */ -#define TCFLAGS_HANDLER (1 << 1) /* 1=Call the user function when the - * timer expires */ +#define TCFLAGS_ACTIVE (1 << 0) /* 1=The timer is running */ +#define TCFLAGS_HANDLER (1 << 1) /* 1=Call the user function when the + * timer expires */ /**************************************************************************** * Public Types @@ -117,6 +129,17 @@ struct timer_status_s * (in microseconds) */ }; +#ifdef HAVE_NOTIFICATION +/* This is the type of the argument passed to the TCIOC_NOTIFICATION ioctl */ + +struct timer_notify_s +{ + FAR void *arg; /* An argument to pass with the signal */ + pid_t pid; /* The ID of the task/thread to receive the signal */ + uint8_t signal; /* The signal number to use in the notification */ +}; +#endif + /* This structure provides the "lower-half" driver operations available to * the "upper-half" driver. */ -- GitLab From 18ad40b98c69095f9a446e29379d51469edaadbd Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 17 Nov 2016 13:37:24 -0600 Subject: [PATCH 432/734] ARMv7-M: Fix double allocation of MPU region in mmu.h --- arch/arm/src/armv7-m/mpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/armv7-m/mpu.h b/arch/arm/src/armv7-m/mpu.h index 22348a23a6..4a5bab065b 100644 --- a/arch/arm/src/armv7-m/mpu.h +++ b/arch/arm/src/armv7-m/mpu.h @@ -357,7 +357,7 @@ static inline void mpu_priv_flash(uintptr_t base, size_t size) /* Select the region */ - putreg32(mpu_allocregion(), MPU_RNR); + putreg32(region, MPU_RNR); /* Select the region base address */ -- GitLab From 197cec58d2792445703887f585e6084d11fcf65f Mon Sep 17 00:00:00 2001 From: Sebastien Lorquet Date: Thu, 17 Nov 2016 14:38:21 -0600 Subject: [PATCH 433/734] timer driver: Use signal to notify of timer expiration. Add generic argument so that there can be additional usage. --- arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c | 125 +++++++++---------- drivers/timers/timer.c | 61 ++++----- include/nuttx/timers/timer.h | 35 ++---- 3 files changed, 98 insertions(+), 123 deletions(-) diff --git a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c index e7d0d72dbd..f99b4b2a9d 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c @@ -3,9 +3,11 @@ * * Copyright (C) 2015 Wail Khemir. All rights reserved. * Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved. + * Copyright (C) 2016 Sebastien Lorquet All rights reserved. * Authors: Wail Khemir * Paul Alexander Patience * dev@ziggurat29.com + * Sebastien Lorquet * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -91,7 +93,8 @@ struct stm32l4_lowerhalf_s { FAR const struct timer_ops_s *ops; /* Lower half operations */ FAR struct stm32l4_tim_dev_s *tim; /* stm32 timer driver */ - tccb_t usrhandler; /* Current user interrupt handler */ + tccb_t callback; /* Current upper half interrupt callback */ + FAR void *arg; /* Argument passed to upper half callback */ const xcpt_t timhandler; /* Current timer interrupt handler */ bool started; /* True: Timer has been started */ const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ @@ -145,8 +148,8 @@ static int stm32l4_start(FAR struct timer_lowerhalf_s *lower); static int stm32l4_stop(FAR struct timer_lowerhalf_s *lower); static int stm32l4_settimeout(FAR struct timer_lowerhalf_s *lower, uint32_t timeout); -static tccb_t stm32l4_sethandler(FAR struct timer_lowerhalf_s *lower, - tccb_t handler); +static tccb_t stm32l4_setcallback(FAR struct timer_lowerhalf_s *lower, + tccb_t callback, FAR void *arg); /**************************************************************************** * Private Data @@ -155,110 +158,110 @@ static tccb_t stm32l4_sethandler(FAR struct timer_lowerhalf_s *lower, static const struct timer_ops_s g_timer_ops = { - .start = stm32l4_start, - .stop = stm32l4_stop, - .getstatus = NULL, - .settimeout = stm32l4_settimeout, - .sethandler = stm32l4_sethandler, - .ioctl = NULL, + .start = stm32l4_start, + .stop = stm32l4_stop, + .getstatus = NULL, + .settimeout = stm32l4_settimeout, + .setcallback = stm32l4_setcallback, + .ioctl = NULL, }; #ifdef CONFIG_STM32L4_TIM1 static struct stm32l4_lowerhalf_s g_tim1_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32l4_tim1_interrupt, - .resolution = STM32L4_TIM1_RES, + .ops = &g_timer_ops, + .timhandler = stm32l4_tim1_interrupt, + .resolution = STM32L4_TIM1_RES, }; #endif #ifdef CONFIG_STM32L4_TIM2 static struct stm32l4_lowerhalf_s g_tim2_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32l4_tim2_interrupt, - .resolution = STM32L4_TIM2_RES, + .ops = &g_timer_ops, + .timhandler = stm32l4_tim2_interrupt, + .resolution = STM32L4_TIM2_RES, }; #endif #ifdef CONFIG_STM32L4_TIM3 static struct stm32l4_lowerhalf_s g_tim3_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32l4_tim3_interrupt, - .resolution = STM32L4_TIM3_RES, + .ops = &g_timer_ops, + .timhandler = stm32l4_tim3_interrupt, + .resolution = STM32L4_TIM3_RES, }; #endif #ifdef CONFIG_STM32L4_TIM4 static struct stm32l4_lowerhalf_s g_tim4_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32l4_tim4_interrupt, - .resolution = STM32L4_TIM4_RES, + .ops = &g_timer_ops, + .timhandler = stm32l4_tim4_interrupt, + .resolution = STM32L4_TIM4_RES, }; #endif #ifdef CONFIG_STM32L4_TIM5 static struct stm32l4_lowerhalf_s g_tim5_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32l4_tim5_interrupt, - .resolution = STM32L4_TIM5_RES, + .ops = &g_timer_ops, + .timhandler = stm32l4_tim5_interrupt, + .resolution = STM32L4_TIM5_RES, }; #endif #ifdef CONFIG_STM32L4_TIM6 static struct stm32l4_lowerhalf_s g_tim6_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32l4_tim6_interrupt, - .resolution = STM32L4_TIM6_RES, + .ops = &g_timer_ops, + .timhandler = stm32l4_tim6_interrupt, + .resolution = STM32L4_TIM6_RES, }; #endif #ifdef CONFIG_STM32L4_TIM7 static struct stm32l4_lowerhalf_s g_tim7_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32l4_tim7_interrupt, - .resolution = STM32L4_TIM7_RES, + .ops = &g_timer_ops, + .timhandler = stm32l4_tim7_interrupt, + .resolution = STM32L4_TIM7_RES, }; #endif #ifdef CONFIG_STM32L4_TIM8 static struct stm32l4_lowerhalf_s g_tim8_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32l4_tim8_interrupt, - .resolution = STM32L4_TIM8_RES, + .ops = &g_timer_ops, + .timhandler = stm32l4_tim8_interrupt, + .resolution = STM32L4_TIM8_RES, }; #endif #ifdef CONFIG_STM32L4_TIM15 static struct stm32l4_lowerhalf_s g_tim15_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32l4_tim15_interrupt, - .resolution = STM32L4_TIM15_RES, + .ops = &g_timer_ops, + .timhandler = stm32l4_tim15_interrupt, + .resolution = STM32L4_TIM15_RES, }; #endif #ifdef CONFIG_STM32L4_TIM16 static struct stm32l4_lowerhalf_s g_tim16_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32l4_tim16_interrupt, - .resolution = STM32L4_TIM16_RES, + .ops = &g_timer_ops, + .timhandler = stm32l4_tim16_interrupt, + .resolution = STM32L4_TIM16_RES, }; #endif #ifdef CONFIG_STM32L4_TIM17 static struct stm32l4_lowerhalf_s g_tim17_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32l4_tim17_interrupt, - .resolution = STM32L4_TIM17_RES, + .ops = &g_timer_ops, + .timhandler = stm32l4_tim17_interrupt, + .resolution = STM32L4_TIM17_RES, }; #endif @@ -369,7 +372,7 @@ static int stm32l4_timer_handler(FAR struct stm32l4_lowerhalf_s *lower) STM32L4_TIM_ACKINT(lower->tim, 0); - if (lower->usrhandler(&next_interval_us)) + if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { @@ -407,7 +410,7 @@ static int stm32l4_start(FAR struct timer_lowerhalf_s *lower) { STM32L4_TIM_SETMODE(priv->tim, STM32L4_TIM_MODE_UP); - if (priv->usrhandler != NULL) + if (priv->callback != NULL) { STM32L4_TIM_SETISR(priv->tim, priv->timhandler, 0); STM32L4_TIM_ENABLEINT(priv->tim, 0); @@ -505,11 +508,12 @@ static int stm32l4_settimeout(FAR struct timer_lowerhalf_s *lower, * Call this user provided timeout handler. * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. - * newhandler - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * callback - The new timer expiration function pointer. If this + * function pointer is NULL, then the reset-on-expiration + * behavior is restored, + * arg - Argument that will be provided in the callback * * Returned Values: * The previous timer expiration function pointer or NULL is there was @@ -517,22 +521,18 @@ static int stm32l4_settimeout(FAR struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static tccb_t stm32l4_sethandler(FAR struct timer_lowerhalf_s *lower, - tccb_t newhandler) +static void stm32l4_setcallback(FAR struct timer_lowerhalf_s *lower, + tccb_t callback, FAR void *arg) { FAR struct stm32l4_lowerhalf_s *priv = (FAR struct stm32l4_lowerhalf_s *)lower; - irqstate_t flags = enter_critical_section(); - /* Get the old handler return value */ - - tccb_t oldhandler = priv->usrhandler; - - /* Save the new handler */ + /* Save the new callback */ - priv->usrhandler = newhandler; + priv->callback = callback; + priv->arg = arg; - if (newhandler != NULL && priv->started) + if (callback != NULL && priv->started) { STM32L4_TIM_SETISR(priv->tim, priv->timhandler, 0); STM32L4_TIM_ENABLEINT(priv->tim, 0); @@ -544,7 +544,6 @@ static tccb_t stm32l4_sethandler(FAR struct timer_lowerhalf_s *lower, } leave_critical_section(flags); - return oldhandler; } /**************************************************************************** @@ -636,9 +635,9 @@ int stm32l4_timer_initialize(FAR const char *devpath, int timer) /* Initialize the elements of lower half state structure */ - lower->started = false; - lower->usrhandler = NULL; - lower->tim = stm32l4_tim_init(timer); + lower->started = false; + lower->callback = NULL; + lower->tim = stm32l4_tim_init(timer); if (lower->tim == NULL) { diff --git a/drivers/timers/timer.c b/drivers/timers/timer.c index 16c85fa5d7..ab71bb6ddb 100644 --- a/drivers/timers/timer.c +++ b/drivers/timers/timer.c @@ -46,6 +46,7 @@ #include #include #include +#include #include #include #include @@ -66,11 +67,9 @@ struct timer_upperhalf_s { uint8_t crefs; /* The number of times the device has been opened */ -#ifdef HAVE_NOTIFICATION - uint8_t signal; /* The signal number to use in the notification */ + uint8_t signo; /* The signal number to use in the notification */ pid_t pid; /* The ID of the task/thread to receive the signal */ FAR void *arg; /* An argument to pass with the signal */ -#endif FAR char *path; /* Registration path */ /* The contained lower-half driver */ @@ -82,12 +81,7 @@ struct timer_upperhalf_s * Private Function Prototypes ****************************************************************************/ -#ifdef HAVE_NOTIFICATION - /* REVISIT: This function prototype is insufficient to support signaling */ - -static bool timer_notifier(FAR uint32_t *next_interval_us); -#endif - +static bool timer_notifier(FAR uint32_t *next_interval_us, FAR void *arg); static int timer_open(FAR struct file *filep); static int timer_close(FAR struct file *filep); static ssize_t timer_read(FAR struct file *filep, FAR char *buffer, @@ -131,15 +125,18 @@ static const struct file_operations g_timerops = * ************************************************************************************/ -#ifdef HAVE_NOTIFICATION -static bool timer_notifier(FAR uint32_t *next_interval_us) +static bool timer_notifier(FAR uint32_t *next_interval_us, FAR void *arg) { - FAR struct timer_upperhalf_s *upper = HOW?; + FAR struct timer_upperhalf_s *upper = (FAR struct timer_upperhalf_s *)arg; #ifdef CONFIG_CAN_PASS_STRUCTS union sigval value; #endif int ret; + DEBUGASSERT(upper != NULL); + + /* Signal the waiter.. if there is one */ + #ifdef CONFIG_CAN_PASS_STRUCTS value.sival_ptr = upper->arg; ret = sigqueue(upper->pid, upper->signo, value); @@ -149,7 +146,6 @@ static bool timer_notifier(FAR uint32_t *next_interval_us) return ret == OK; } -#endif /************************************************************************************ * Name: timer_open @@ -363,7 +359,6 @@ static int timer_ioctl(FAR struct file *filep, int cmd, unsigned long arg) } break; -#ifdef HAVE_NOTIFICATION /* cmd: TCIOC_NOTIFICATION * Description: Notify application via a signal when the timer expires. * Argument: signal number @@ -375,15 +370,15 @@ static int timer_ioctl(FAR struct file *filep, int cmd, unsigned long arg) case TCIOC_NOTIFICATION: { FAR struct timer_notify_s *notify = - (FAR struct timer_notify_s *)((uintptr_t)arg) + (FAR struct timer_notify_s *)((uintptr_t)arg); if (notify != NULL) { - upper->signo = notify->signal; - upper->get = notify->signal; - upper->arg = noify->arg; + upper->signo = notify->signo; + upper->pid = notify->pid; + upper->arg = notify->arg; - ret = timer_sethandler((FAR void *handle)upper, timer_notifier, NULL); + ret = timer_setcallback((FAR void *)upper, timer_notifier, upper); } else { @@ -391,7 +386,6 @@ static int timer_ioctl(FAR struct file *filep, int cmd, unsigned long arg) } } break; -#endif /* Any unrecognized IOCTL commands might be platform-specific ioctl commands */ @@ -548,7 +542,7 @@ void timer_unregister(FAR void *handle) } /**************************************************************************** - * Name: timer_sethandler + * Name: timer_setcallback * * Description: * This function can be called to add a callback into driver-related code @@ -556,21 +550,20 @@ void timer_unregister(FAR void *handle) * and may NOT be used by appliction code. * * Input parameters: - * handle - This is the handle that was returned by timer_register() - * newhandler - The new timer interrupt handler - * oldhandler - The previous timer interrupt handler (if any) + * handle - This is the handle that was returned by timer_register() + * newcallback - The new timer interrupt callback + * oldcallback - The previous timer interrupt callback (if any) + * arg - Argument to be provided with the callback * * Returned Value: * None * ****************************************************************************/ -int timer_sethandler(FAR void *handle, tccb_t newhandler, - FAR tccb_t *oldhandler) +int timer_setcallback(FAR void *handle, tccb_t newcallback, FAR void *arg) { FAR struct timer_upperhalf_s *upper; FAR struct timer_lowerhalf_s *lower; - tccb_t tmphandler; /* Recover the pointer to the upper-half driver state */ @@ -579,21 +572,13 @@ int timer_sethandler(FAR void *handle, tccb_t newhandler, lower = upper->lower; DEBUGASSERT(lower->ops != NULL); - /* Check if the lower half driver supports the sethandler method */ + /* Check if the lower half driver supports the setcallback method */ - if (lower->ops->sethandler != NULL) /* Optional */ + if (lower->ops->setcallback != NULL) /* Optional */ { /* Yes.. Defer the hander attachment to the lower half driver */ - tmphandler = lower->ops->sethandler(lower, newhandler); - - /* Return the oldhandler if a location to return it was provided */ - - if (oldhandler != NULL) - { - *oldhandler = tmphandler; - } - + lower->ops->setcallback(lower, newcallback, arg); return OK; } diff --git a/include/nuttx/timers/timer.h b/include/nuttx/timers/timer.h index eb2830bd56..a89369d5df 100644 --- a/include/nuttx/timers/timer.h +++ b/include/nuttx/timers/timer.h @@ -52,11 +52,6 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* It would require some interface modifcations in order to support - * notifications. - */ - -#undef HAVE_NOTIFICATION /* IOCTL Commands ***********************************************************/ /* The timer driver uses a standard character driver framework. However, @@ -96,9 +91,7 @@ #define TCIOC_STOP _TCIOC(0x0002) #define TCIOC_GETSTATUS _TCIOC(0x0003) #define TCIOC_SETTIMEOUT _TCIOC(0x0004) -#ifdef HAVE_NOTIFICATION #define TCIOC_NOTIFICATION _TCIOC(0x0005) -#endif /* Bit Settings *************************************************************/ /* Bit settings for the struct timer_status_s flags field */ @@ -111,11 +104,11 @@ * Public Types ****************************************************************************/ -/* User function prototype. Returns true to reload the timer, and the +/* Upper half callback prototype. Returns true to reload the timer, and the * function can modify the next interval if desired. */ -typedef CODE bool (*tccb_t)(FAR uint32_t *next_interval_us); +typedef CODE bool (*tccb_t)(FAR uint32_t *next_interval_us, FAR void *arg); /* This is the type of the argument passed to the TCIOC_GETSTATUS ioctl and * and returned by the "lower half" getstatus() method. @@ -129,16 +122,14 @@ struct timer_status_s * (in microseconds) */ }; -#ifdef HAVE_NOTIFICATION /* This is the type of the argument passed to the TCIOC_NOTIFICATION ioctl */ struct timer_notify_s { FAR void *arg; /* An argument to pass with the signal */ pid_t pid; /* The ID of the task/thread to receive the signal */ - uint8_t signal; /* The signal number to use in the notification */ + uint8_t signo; /* The signal number to use in the notification */ }; -#endif /* This structure provides the "lower-half" driver operations available to * the "upper-half" driver. @@ -166,12 +157,13 @@ struct timer_ops_s CODE int (*settimeout)(FAR struct timer_lowerhalf_s *lower, uint32_t timeout); - /* Call this user provider timeout handler on timeout. - * NOTE: Providing handler==NULL disable. + /* Call the NuttX INTERNAL timeout callback on timeout. + * NOTE: Providing callback==NULL disable. + * NOT to call back into applications. */ - CODE tccb_t (*sethandler)(FAR struct timer_lowerhalf_s *lower, - CODE tccb_t handler); + CODE void (*setcallback)(FAR struct timer_lowerhalf_s *lower, + CODE tccb_t callback, FAR void *arg); /* Any ioctl commands that are not recognized by the "upper-half" driver * are forwarded to the lower half driver through this method. @@ -272,7 +264,7 @@ void timer_unregister(FAR void *handle); ****************************************************************************/ /**************************************************************************** - * Name: timer_sethandler + * Name: timer_setcallback * * Description: * This function can be called to add a callback into driver-related code @@ -280,9 +272,9 @@ void timer_unregister(FAR void *handle); * and may NOT be used by appliction code. * * Input parameters: - * handle - This is the handle that was returned by timer_register() - * newhandler - The new timer interrupt handler - * oldhandler - The previous timer interrupt handler (if any) + * handle - This is the handle that was returned by timer_register() + * callback - The new timer interrupt callback + * arg - Argument provided when the callback is called. * * Returned Value: * None @@ -290,8 +282,7 @@ void timer_unregister(FAR void *handle); ****************************************************************************/ #ifdef __KERNEL__ -int timer_sethandler(FAR void *handle, tccb_t newhandler, - FAR tccb_t *oldhandler); +int timer_setcallback(FAR void *handle, tccb_t callback, FAR void *arg); #endif /**************************************************************************** -- GitLab From 19c1c9d78b1c237b63e449fce5fc99b1ffb497cf Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 17 Nov 2016 15:03:31 -0600 Subject: [PATCH 434/734] All timer lower half drivers. Port Sebastien's changes to all all other implementations of the timer lower half. Very many just and untested. Expect some problems. --- arch/arm/src/sam34/sam_rtt.c | 70 +++++----- arch/arm/src/sam34/sam_tc.c | 61 ++++----- arch/arm/src/stm32/stm32_tim_lowerhalf.c | 136 +++++++++---------- arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c | 4 +- drivers/timers/timer.c | 2 +- 5 files changed, 133 insertions(+), 140 deletions(-) diff --git a/arch/arm/src/sam34/sam_rtt.c b/arch/arm/src/sam34/sam_rtt.c index 9df244ccce..f29e7ac8ee 100644 --- a/arch/arm/src/sam34/sam_rtt.c +++ b/arch/arm/src/sam34/sam_rtt.c @@ -92,12 +92,13 @@ struct sam34_lowerhalf_s /* Private data */ - tccb_t handler; /* Current user interrupt handler */ - uint32_t timeout; /* The current timeout value (us) */ - uint32_t clkticks; /* actual clock ticks for current interval */ - uint32_t val; /* rtt value of current timeout */ - uint32_t adjustment; /* time lost due to clock resolution truncation (us) */ - bool started; /* The timer has been started */ + tccb_t callback; /* Current user interrupt callback */ + FAR void *arg; /* Argument that accompanies the callback */ + uint32_t timeout; /* The current timeout value (us) */ + uint32_t clkticks; /* Actual clock ticks for current interval */ + uint32_t val; /* rtt value of current timeout */ + uint32_t adjustment; /* Time lost due to clock resolution truncation (us) */ + bool started; /* The timer has been started */ }; /**************************************************************************** @@ -125,8 +126,8 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower, FAR struct timer_status_s *status); static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower, uint32_t timeout); -static tccb_t sam34_sethandler(FAR struct timer_lowerhalf_s *lower, - tccb_t handler); +static void sam34_setcallback(FAR struct timer_lowerhalf_s *lower, + tccb_t callback, FAR void *arg); static int sam34_ioctl(FAR struct timer_lowerhalf_s *lower, int cmd, unsigned long arg); @@ -137,12 +138,12 @@ static int sam34_ioctl(FAR struct timer_lowerhalf_s *lower, int cmd, static const struct timer_ops_s g_tcops = { - .start = sam34_start, - .stop = sam34_stop, - .getstatus = sam34_getstatus, - .settimeout = sam34_settimeout, - .sethandler = sam34_sethandler, - .ioctl = sam34_ioctl, + .start = sam34_start, + .stop = sam34_stop, + .getstatus = sam34_getstatus, + .settimeout = sam34_settimeout, + .setcallback = sam34_setcallback, + .ioctl = sam34_ioctl, }; /* "Lower half" driver state */ @@ -160,6 +161,7 @@ static struct sam34_lowerhalf_s g_tcdev; * Get the contents of the value register. * ****************************************************************************/ + static inline uint32_t sam34_readvr(void) { register uint32_t v; @@ -289,9 +291,9 @@ static int sam34_interrupt(int irq, FAR void *context) uint32_t vr; uint32_t lateticks; - /* Is there a registered handler? */ + /* Is there a registered callback? */ - if (priv->handler && priv->handler(&priv->timeout)) + if (priv->callback && priv->callback(&priv->timeout, priv->arg)) { /* Disable int before writing new alarm */ @@ -388,7 +390,7 @@ static int sam34_start(FAR struct timer_lowerhalf_s *lower) priv->val = vr + priv->clkticks; /* value at end of interval */ sam34_putreg(priv->val-1, SAM_RTT_AR); /* Set interval */ - if (priv->handler) + if (priv->callback) { /* Clear status and enable interrupt */ @@ -475,7 +477,7 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower, status->flags |= TCFLAGS_ACTIVE; } - if (priv->handler) + if (priv->callback) { status->flags |= TCFLAGS_HANDLER; } @@ -544,17 +546,18 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: sam34_sethandler + * Name: sam34_setcallback * * Description: - * Call this user provided timeout handler. + * Call this user provided timeout callback. * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. - * newhandler - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * callback - The new timer expiration function pointer. If this + * function pointer is NULL, then the reset-on-expiration + * behavior is restored, + * arg - Argument that will be provided in the callback * * Returned Values: * The previous timer expiration function pointer or NULL is there was @@ -562,28 +565,23 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static tccb_t sam34_sethandler(FAR struct timer_lowerhalf_s *lower, - tccb_t handler) +static void sam34_setcallback(FAR struct timer_lowerhalf_s *lower, + tccb_t callback, FAR void *arg) { FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower; irqstate_t flags; - tccb_t oldhandler; flags = enter_critical_section(); DEBUGASSERT(priv); - tmrinfo("Entry: handler=%p\n", handler); - - /* Get the old handler return value */ - - oldhandler = priv->handler; + tmrinfo("Entry: callback=%p\n", callback); - /* Save the new handler */ + /* Save the new callback and argument */ - priv->handler = handler; + priv->callback = callback; + priv->arg = arg; leave_critical_section(flags); - return oldhandler; } /**************************************************************************** diff --git a/arch/arm/src/sam34/sam_tc.c b/arch/arm/src/sam34/sam_tc.c index 369aa7323a..1ddab1c20f 100644 --- a/arch/arm/src/sam34/sam_tc.c +++ b/arch/arm/src/sam34/sam_tc.c @@ -90,13 +90,14 @@ struct sam34_lowerhalf_s /* Private data */ - uint32_t base; /* Base address of the timer */ - tccb_t handler; /* Current user interrupt handler */ - uint32_t timeout; /* The current timeout value (us) */ - uint32_t adjustment; /* time lost due to clock resolution truncation (us) */ - uint32_t clkticks; /* actual clock ticks for current interval */ - bool started; /* The timer has been started */ - uint16_t periphid; /* peripheral id */ + uint32_t base; /* Base address of the timer */ + tccb_t callback; /* Current user interrupt callback */ + FAR void *arg; /* Argument passed to the callback function */ + uint32_t timeout; /* The current timeout value (us) */ + uint32_t adjustment; /* time lost due to clock resolution truncation (us) */ + uint32_t clkticks; /* actual clock ticks for current interval */ + bool started; /* The timer has been started */ + uint16_t periphid; /* peripheral id */ }; /**************************************************************************** @@ -124,8 +125,8 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower, FAR struct timer_status_s *status); static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower, uint32_t timeout); -static tccb_t sam34_sethandler(FAR struct timer_lowerhalf_s *lower, - tccb_t handler); +static void sam34_sethandler(FAR struct timer_lowerhalf_s *lower, + tccb_t callback, FAR void *arg); static int sam34_ioctl(FAR struct timer_lowerhalf_s *lower, int cmd, unsigned long arg); @@ -267,11 +268,11 @@ static int sam34_interrupt(int irq, FAR void *context) { uint32_t timeout; - /* Is there a registered handler? If the handler has been nullified, + /* Is there a registered callback? If the callback has been nullified, * the timer will be stopped. */ - if (priv->handler && priv->handler(&priv->timeout)) + if (priv->callback && priv->callback(&priv->timeout, priv->arg)) { /* Calculate new ticks / dither adjustment */ @@ -286,7 +287,7 @@ static int sam34_interrupt(int irq, FAR void *context) } else { - /* No handler or the handler returned false.. stop the timer */ + /* No callback or the callback returned false.. stop the timer */ sam34_stop((FAR struct timer_lowerhalf_s *)priv); tmrinfo("Stopped\n"); @@ -340,7 +341,7 @@ static int sam34_start(FAR struct timer_lowerhalf_s *lower) sam34_putreg(priv->clkticks, priv->base + SAM_TC_RC_OFFSET); /* Set interval */ - if (priv->handler) + if (priv->callback) { /* Clear status and enable interrupt */ @@ -422,7 +423,7 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower, status->flags |= TCFLAGS_ACTIVE; } - if (priv->handler) + if (priv->callback) { status->flags |= TCFLAGS_HANDLER; } @@ -493,17 +494,18 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: sam34_sethandler + * Name: sam34_setcallback * * Description: - * Call this user provided timeout handler. + * Call this user provided timeout callback. * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. - * newhandler - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * callback - The new timer expiration function pointer. If this + * function pointer is NULL, then the reset-on-expiration + * behavior is restored, + * arg - Argument to be provided with the callback. * * Returned Values: * The previous timer expiration function pointer or NULL is there was @@ -511,28 +513,23 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static tccb_t sam34_sethandler(FAR struct timer_lowerhalf_s *lower, - tccb_t handler) +static void sam34_sethandler(FAR struct timer_lowerhalf_s *lower, + tccb_t callback, FAR void *arg) { FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower; irqstate_t flags; - tccb_t oldhandler; flags = enter_critical_section(); DEBUGASSERT(priv); - tmrinfo("Entry: handler=%p\n", handler); + tmrinfo("Entry: callback=%p\n", callback); - /* Get the old handler return value */ + /* Save the new callback and its argument */ - oldhandler = priv->handler; - - /* Save the new handler */ - - priv->handler = handler; + priv->callback = callback; + priv->arg = arg; leave_critical_section(flags); - return oldhandler; } /**************************************************************************** diff --git a/arch/arm/src/stm32/stm32_tim_lowerhalf.c b/arch/arm/src/stm32/stm32_tim_lowerhalf.c index 5de8549c71..684381cc68 100644 --- a/arch/arm/src/stm32/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32/stm32_tim_lowerhalf.c @@ -107,7 +107,8 @@ struct stm32_lowerhalf_s { FAR const struct timer_ops_s *ops; /* Lower half operations */ FAR struct stm32_tim_dev_s *tim; /* stm32 timer driver */ - tccb_t usrhandler; /* Current user interrupt handler */ + tccb_t callback; /* Current user interrupt callback */ + FAR void *arg; /* Argument passed to upper half callback */ const xcpt_t timhandler; /* Current timer interrupt handler */ bool started; /* True: Timer has been started */ const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ @@ -170,8 +171,8 @@ static int stm32_start(FAR struct timer_lowerhalf_s *lower); static int stm32_stop(FAR struct timer_lowerhalf_s *lower); static int stm32_settimeout(FAR struct timer_lowerhalf_s *lower, uint32_t timeout); -static tccb_t stm32_sethandler(FAR struct timer_lowerhalf_s *lower, - tccb_t handler); +static void stm32_setcallback(FAR struct timer_lowerhalf_s *lower, + tccb_t callback, FAR void *arg); /**************************************************************************** * Private Data @@ -180,137 +181,137 @@ static tccb_t stm32_sethandler(FAR struct timer_lowerhalf_s *lower, static const struct timer_ops_s g_timer_ops = { - .start = stm32_start, - .stop = stm32_stop, - .getstatus = NULL, - .settimeout = stm32_settimeout, - .sethandler = stm32_sethandler, - .ioctl = NULL, + .start = stm32_start, + .stop = stm32_stop, + .getstatus = NULL, + .settimeout = stm32_settimeout, + .setcallback = stm32_setcallback, + .ioctl = NULL, }; #ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32_tim1_interrupt, - .resolution = STM32_TIM1_RES, + .ops = &g_timer_ops, + .timhandler = stm32_tim1_interrupt, + .resolution = STM32_TIM1_RES, }; #endif #ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32_tim2_interrupt, - .resolution = STM32_TIM2_RES, + .ops = &g_timer_ops, + .timhandler = stm32_tim2_interrupt, + .resolution = STM32_TIM2_RES, }; #endif #ifdef CONFIG_STM32_TIM3 static struct stm32_lowerhalf_s g_tim3_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32_tim3_interrupt, - .resolution = STM32_TIM3_RES, + .ops = &g_timer_ops, + .timhandler = stm32_tim3_interrupt, + .resolution = STM32_TIM3_RES, }; #endif #ifdef CONFIG_STM32_TIM4 static struct stm32_lowerhalf_s g_tim4_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32_tim4_interrupt, - .resolution = STM32_TIM4_RES, + .ops = &g_timer_ops, + .timhandler = stm32_tim4_interrupt, + .resolution = STM32_TIM4_RES, }; #endif #ifdef CONFIG_STM32_TIM5 static struct stm32_lowerhalf_s g_tim5_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32_tim5_interrupt, - .resolution = STM32_TIM5_RES, + .ops = &g_timer_ops, + .timhandler = stm32_tim5_interrupt, + .resolution = STM32_TIM5_RES, }; #endif #ifdef CONFIG_STM32_TIM6 static struct stm32_lowerhalf_s g_tim6_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32_tim6_interrupt, - .resolution = STM32_TIM6_RES, + .ops = &g_timer_ops, + .timhandler = stm32_tim6_interrupt, + .resolution = STM32_TIM6_RES, }; #endif #ifdef CONFIG_STM32_TIM7 static struct stm32_lowerhalf_s g_tim7_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32_tim7_interrupt, - .resolution = STM32_TIM7_RES, + .ops = &g_timer_ops, + .timhandler = stm32_tim7_interrupt, + .resolution = STM32_TIM7_RES, }; #endif #ifdef CONFIG_STM32_TIM8 static struct stm32_lowerhalf_s g_tim8_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32_tim8_interrupt, - .resolution = STM32_TIM8_RES, + .ops = &g_timer_ops, + .timhandler = stm32_tim8_interrupt, + .resolution = STM32_TIM8_RES, }; #endif #ifdef CONFIG_STM32_TIM9 static struct stm32_lowerhalf_s g_tim9_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32_tim9_interrupt, - .resolution = STM32_TIM9_RES, + .ops = &g_timer_ops, + .timhandler = stm32_tim9_interrupt, + .resolution = STM32_TIM9_RES, }; #endif #ifdef CONFIG_STM32_TIM10 static struct stm32_lowerhalf_s g_tim10_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32_tim10_interrupt, - .resolution = STM32_TIM10_RES, + .ops = &g_timer_ops, + .timhandler = stm32_tim10_interrupt, + .resolution = STM32_TIM10_RES, }; #endif #ifdef CONFIG_STM32_TIM11 static struct stm32_lowerhalf_s g_tim11_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32_tim11_interrupt, - .resolution = STM32_TIM11_RES, + .ops = &g_timer_ops, + .timhandler = stm32_tim11_interrupt, + .resolution = STM32_TIM11_RES, }; #endif #ifdef CONFIG_STM32_TIM12 static struct stm32_lowerhalf_s g_tim12_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32_tim12_interrupt, - .resolution = STM32_TIM12_RES, + .ops = &g_timer_ops, + .timhandler = stm32_tim12_interrupt, + .resolution = STM32_TIM12_RES, }; #endif #ifdef CONFIG_STM32_TIM13 static struct stm32_lowerhalf_s g_tim13_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32_tim13_interrupt, - .resolution = STM32_TIM13_RES, + .ops = &g_timer_ops, + .timhandler = stm32_tim13_interrupt, + .resolution = STM32_TIM13_RES, }; #endif #ifdef CONFIG_STM32_TIM14 static struct stm32_lowerhalf_s g_tim14_lowerhalf = { - .ops = &g_timer_ops, - .timhandler = stm32_tim14_interrupt, - .resolution = STM32_TIM14_RES, + .ops = &g_timer_ops, + .timhandler = stm32_tim14_interrupt, + .resolution = STM32_TIM14_RES, }; #endif @@ -442,7 +443,7 @@ static int stm32_timer_handler(FAR struct stm32_lowerhalf_s *lower) STM32_TIM_ACKINT(lower->tim, 0); - if (lower->usrhandler(&next_interval_us)) + if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { @@ -480,7 +481,7 @@ static int stm32_start(FAR struct timer_lowerhalf_s *lower) { STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); - if (priv->usrhandler != NULL) + if (priv->callback != NULL) { STM32_TIM_SETISR(priv->tim, priv->timhandler, 0); STM32_TIM_ENABLEINT(priv->tim, 0); @@ -571,17 +572,18 @@ static int stm32_settimeout(FAR struct timer_lowerhalf_s *lower, uint32_t timeou } /**************************************************************************** - * Name: stm32_sethandler + * Name: stm32_setcallback * * Description: - * Call this user provided timeout handler. + * Call this user provided timeout callback. * * Input Parameters: * lower - A pointer the publicly visible representation of the "lower-half" * driver state structure. - * newhandler - The new timer expiration function pointer. If this + * callback - The new timer expiration function pointer. If this * function pointer is NULL, then the reset-on-expiration * behavior is restored, + * arg - Argument that will be provided in the callback * * Returned Values: * The previous timer expiration function pointer or NULL is there was @@ -589,22 +591,19 @@ static int stm32_settimeout(FAR struct timer_lowerhalf_s *lower, uint32_t timeou * ****************************************************************************/ -static tccb_t stm32_sethandler(FAR struct timer_lowerhalf_s *lower, - tccb_t newhandler) +static void stm32_setcallback(FAR struct timer_lowerhalf_s *lower, + tccb_t callback, FAR void *arg) { FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower; irqstate_t flags = enter_critical_section(); - /* Get the old handler return value */ + /* Save the new callback */ - tccb_t oldhandler = priv->usrhandler; + priv->callback = callback; + priv->arg = arg; - /* Save the new handler */ - - priv->usrhandler = newhandler; - - if (newhandler != NULL && priv->started) + if (callback != NULL && priv->started) { STM32_TIM_SETISR(priv->tim, priv->timhandler, 0); STM32_TIM_ENABLEINT(priv->tim, 0); @@ -616,7 +615,6 @@ static tccb_t stm32_sethandler(FAR struct timer_lowerhalf_s *lower, } leave_critical_section(flags); - return oldhandler; } /**************************************************************************** @@ -723,9 +721,9 @@ int stm32_timer_initialize(FAR const char *devpath, int timer) /* Initialize the elements of lower half state structure */ - lower->started = false; - lower->usrhandler = NULL; - lower->tim = stm32_tim_init(timer); + lower->started = false; + lower->callback = NULL; + lower->tim = stm32_tim_init(timer); if (lower->tim == NULL) { diff --git a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c index f99b4b2a9d..7f872736a4 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c @@ -148,8 +148,8 @@ static int stm32l4_start(FAR struct timer_lowerhalf_s *lower); static int stm32l4_stop(FAR struct timer_lowerhalf_s *lower); static int stm32l4_settimeout(FAR struct timer_lowerhalf_s *lower, uint32_t timeout); -static tccb_t stm32l4_setcallback(FAR struct timer_lowerhalf_s *lower, - tccb_t callback, FAR void *arg); +static void stm32l4_setcallback(FAR struct timer_lowerhalf_s *lower, + tccb_t callback, FAR void *arg); /**************************************************************************** * Private Data diff --git a/drivers/timers/timer.c b/drivers/timers/timer.c index ab71bb6ddb..7440d9e4ea 100644 --- a/drivers/timers/timer.c +++ b/drivers/timers/timer.c @@ -1,7 +1,7 @@ /**************************************************************************** * drivers/timers/timer.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * Bob Doiron * -- GitLab From f92afbfbf3fc70c250be0e27673132cdef79c776 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 17 Nov 2016 15:18:52 -0600 Subject: [PATCH 435/734] apps/examples/timer: Restore the timer example, but adapt the interface to use the new signal logic from Sebastien, Lorquet. Totally untested and probably does not work! --- arch/arm/src/tiva/tiva_timerlow32.c | 57 +++++++++++++---------------- 1 file changed, 26 insertions(+), 31 deletions(-) diff --git a/arch/arm/src/tiva/tiva_timerlow32.c b/arch/arm/src/tiva/tiva_timerlow32.c index 2fcf969429..25478f6641 100644 --- a/arch/arm/src/tiva/tiva_timerlow32.c +++ b/arch/arm/src/tiva/tiva_timerlow32.c @@ -70,7 +70,7 @@ struct tiva_lowerhalf_s const struct timer_ops_s *ops; /* Lower half operations */ struct tiva_gptm32config_s config; /* Persistent timer configuration */ TIMER_HANDLE handle; /* Contained timer handle */ - tccb_t handler; /* Current user interrupt handler */ + tccb_t callback; /* Current user interrupt callback */ uint32_t clkin; /* Input clock frequency */ uint32_t timeout; /* The current timeout value (us) */ uint32_t clkticks; /* Actual clock ticks for current interval */ @@ -99,8 +99,8 @@ static int tiva_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status); static int tiva_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout); -static tccb_t tiva_sethandler(struct timer_lowerhalf_s *lower, - tccb_t handler); +static void tiva_setcallback(struct timer_lowerhalf_s *lower, + tccb_t callback, FAR void *arg); static int tiva_ioctl(struct timer_lowerhalf_s *lower, int cmd, unsigned long arg); @@ -111,12 +111,12 @@ static int tiva_ioctl(struct timer_lowerhalf_s *lower, int cmd, static const struct timer_ops_s g_timer_ops = { - .start = tiva_start, - .stop = tiva_stop, - .getstatus = tiva_getstatus, - .settimeout = tiva_settimeout, - .sethandler = tiva_sethandler, - .ioctl = tiva_ioctl, + .start = tiva_start, + .stop = tiva_stop, + .getstatus = tiva_getstatus, + .settimeout = tiva_settimeout, + .setcallback = tiva_setcallback, + .ioctl = tiva_ioctl, }; /**************************************************************************** @@ -242,11 +242,11 @@ static void tiva_timer_handler(TIMER_HANDLE handle, void *arg, uint32_t status) { uint32_t timeout; - /* Is there a registered handler? If the handler has been nullified, + /* Is there a registered callback? If the callback has been nullified, * the timer will be stopped. */ - if (priv->handler && priv->handler(&priv->timeout)) + if (priv->callback && priv->callback(&priv->timeout, priv->arg)) { /* Calculate new ticks / dither adjustment */ @@ -269,7 +269,7 @@ static void tiva_timer_handler(TIMER_HANDLE handle, void *arg, uint32_t status) } else { - /* No handler or the handler returned false.. stop the timer */ + /* No callback or the callback returned false.. stop the timer */ tiva_timer32_stop(priv->handle); tmrinfo("Stopped\n"); @@ -384,7 +384,7 @@ static int tiva_getstatus(struct timer_lowerhalf_s *lower, status->flags |= TCFLAGS_ACTIVE; } - if (priv->handler) + if (priv->callback) { status->flags |= TCFLAGS_HANDLER; } @@ -444,17 +444,17 @@ static int tiva_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout) } /**************************************************************************** - * Name: tiva_sethandler + * Name: tiva_setcallback * * Description: - * Call this user provided timeout handler. + * Call this user provided timeout callback. * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower-half" - * driver state structure. - * newhandler - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * callback - The new timer expiration function pointer. If this + * function pointer is NULL, then the reset-on-expiration + * behavior is restored, * * Returned Values: * The previous timer expiration function pointer or NULL is there was @@ -462,28 +462,23 @@ static int tiva_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout) * ****************************************************************************/ -static tccb_t tiva_sethandler(struct timer_lowerhalf_s *lower, - tccb_t handler) +static void tiva_setcallback(struct timer_lowerhalf_s *lower, + tccb_t callback, FAR void *arg) { struct tiva_lowerhalf_s *priv = (struct tiva_lowerhalf_s *)lower; irqstate_t flags; - tccb_t oldhandler; flags = enter_critical_section(); DEBUGASSERT(priv); - tmrinfo("Entry: handler=%p\n", handler); + tmrinfo("Entry: callback=%p\n", callback); - /* Get the old handler return value */ + /* Save the new callback */ - oldhandler = priv->handler; - - /* Save the new handler */ - - priv->handler = handler; + priv->callback = callback; + priv->arg = arg; leave_critical_section(flags); - return oldhandler; } /**************************************************************************** -- GitLab From 558f4049d4805c5c8f946d5787428be56eb5801d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 17 Nov 2016 15:36:27 -0600 Subject: [PATCH 436/734] sched/irq/irq_csection: Fix a bad DEBUG assertion when SMP is enabled. --- sched/irq/irq_csection.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 1167eba4e9..660dae6a62 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -129,10 +129,26 @@ irqstate_t enter_critical_section(void) /* We are in an interrupt handler. How can this happen? * * 1. We were not in a critical section when the interrupt - * occurred, OR + * occurred. In this case: + * + * g_cpu_irqlock = SP_UNLOCKED. + * g_cpu_nestcount = 0 + * All CPU bits in g_cpu_irqset should be zero + * * 2. We were in critical section, but up_irq_restore only * disabled local interrupts on a different CPU; * Interrupts could still be enabled on this CPU. + * + * g_cpu_irqlock = SP_LOCKED. + * g_cpu_nestcount = 0 + * The CPU bit in g_cpu_irqset should be zero + * + * 3. An extension of 2 is that we may be re-entered numerous + * times from the interrupt handler. In that case: + * + * g_cpu_irqlock = SP_LOCKED. + * g_cpu_nestcount > 0 + * The CPU bit in g_cpu_irqset should be zero */ /* Handle nested calls to enter_critical_section() from the same @@ -152,8 +168,7 @@ irqstate_t enter_critical_section(void) * wait until we have the lock. */ - DEBUGASSERT(!spin_islocked(&g_cpu_irqlock) || - (g_cpu_irqset & (1 << cpu)) == 0); + DEBUGASSERT((g_cpu_irqset & (1 << cpu)) == 0); /* Wait until we can get the spinlock (meaning that we are no * longer in the critical section). -- GitLab From 9acd57c81939529cd7f2750a8a4571e74806b01b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 17 Nov 2016 15:50:39 -0600 Subject: [PATCH 437/734] Fix up some naming and update some comments. --- drivers/timers/timer.c | 11 +++++------ sched/irq/irq_csection.c | 2 +- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/timers/timer.c b/drivers/timers/timer.c index 7440d9e4ea..d1d82d6fb3 100644 --- a/drivers/timers/timer.c +++ b/drivers/timers/timer.c @@ -550,17 +550,16 @@ void timer_unregister(FAR void *handle) * and may NOT be used by appliction code. * * Input parameters: - * handle - This is the handle that was returned by timer_register() - * newcallback - The new timer interrupt callback - * oldcallback - The previous timer interrupt callback (if any) - * arg - Argument to be provided with the callback + * handle - This is the handle that was returned by timer_register() + * callback - The new timer interrupt callback + * arg - Argument to be provided with the callback * * Returned Value: * None * ****************************************************************************/ -int timer_setcallback(FAR void *handle, tccb_t newcallback, FAR void *arg) +int timer_setcallback(FAR void *handle, tccb_t callback, FAR void *arg) { FAR struct timer_upperhalf_s *upper; FAR struct timer_lowerhalf_s *lower; @@ -578,7 +577,7 @@ int timer_setcallback(FAR void *handle, tccb_t newcallback, FAR void *arg) { /* Yes.. Defer the hander attachment to the lower half driver */ - lower->ops->setcallback(lower, newcallback, arg); + lower->ops->setcallback(lower, callback, arg); return OK; } diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 660dae6a62..63b17507a6 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -164,7 +164,7 @@ irqstate_t enter_critical_section(void) } else { - /* First call enter_critical_section. Test assumptions, then + /* First call to enter_critical_section. Test assumptions, then * wait until we have the lock. */ -- GitLab From 47b52a26333744d378171b049b8b36ade09eb5fd Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 17 Nov 2016 16:15:06 -0600 Subject: [PATCH 438/734] Fix an error in manually bringing in Sebastien's changes; Update some comments. --- drivers/timers/timer.c | 2 +- sched/irq/irq_csection.c | 9 ++++++--- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/timers/timer.c b/drivers/timers/timer.c index d1d82d6fb3..80c76a1b62 100644 --- a/drivers/timers/timer.c +++ b/drivers/timers/timer.c @@ -144,7 +144,7 @@ static bool timer_notifier(FAR uint32_t *next_interval_us, FAR void *arg) ret = sigqueue(upper->pid, upper->signo, upper->arg); #endif - return ret == OK; + return true; } /************************************************************************************ diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 63b17507a6..6eb5beca74 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -135,7 +135,10 @@ irqstate_t enter_critical_section(void) * g_cpu_nestcount = 0 * All CPU bits in g_cpu_irqset should be zero * - * 2. We were in critical section, but up_irq_restore only + * 2. We were in a critical section and interrupts on this + * this CPU were disabled -- this is an impossible case. + * + * 3. We were in critical section, but up_irq_save() only * disabled local interrupts on a different CPU; * Interrupts could still be enabled on this CPU. * @@ -143,8 +146,8 @@ irqstate_t enter_critical_section(void) * g_cpu_nestcount = 0 * The CPU bit in g_cpu_irqset should be zero * - * 3. An extension of 2 is that we may be re-entered numerous - * times from the interrupt handler. In that case: + * 4. An extension of 2 is that we may be re-entered numerous + * times from the same interrupt handler. In that case: * * g_cpu_irqlock = SP_LOCKED. * g_cpu_nestcount > 0 -- GitLab From 8e029f019bb5226aacee0ca825eff1cde11d7f06 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 17 Nov 2016 17:30:12 -0600 Subject: [PATCH 439/734] Update comments --- sched/irq/irq_csection.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 6eb5beca74..188445b1c7 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -144,14 +144,14 @@ irqstate_t enter_critical_section(void) * * g_cpu_irqlock = SP_LOCKED. * g_cpu_nestcount = 0 - * The CPU bit in g_cpu_irqset should be zero + * The bit in g_cpu_irqset for this CPU hould be zero * - * 4. An extension of 2 is that we may be re-entered numerous + * 4. An extension of 3 is that we may be re-entered numerous * times from the same interrupt handler. In that case: * * g_cpu_irqlock = SP_LOCKED. * g_cpu_nestcount > 0 - * The CPU bit in g_cpu_irqset should be zero + * The bit in g_cpu_irqset for this CPU hould be zero */ /* Handle nested calls to enter_critical_section() from the same -- GitLab From 8602e8a8a997cbb2bb345d1a8afa4314c3c97096 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 18 Nov 2016 07:38:16 -0600 Subject: [PATCH 440/734] SMP: irq_csection() has a bad assumption. It assumed that the state of certain variables. That was true on entry into the interrupt handler, but might change to the execution of logic within the interrupt handler. --- sched/irq/irq_csection.c | 31 +++++++++++++++++++++++-------- 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 188445b1c7..f2f54910c9 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -129,7 +129,7 @@ irqstate_t enter_critical_section(void) /* We are in an interrupt handler. How can this happen? * * 1. We were not in a critical section when the interrupt - * occurred. In this case: + * occurred. In this case, the interrupt was entered with: * * g_cpu_irqlock = SP_UNLOCKED. * g_cpu_nestcount = 0 @@ -152,6 +152,11 @@ irqstate_t enter_critical_section(void) * g_cpu_irqlock = SP_LOCKED. * g_cpu_nestcount > 0 * The bit in g_cpu_irqset for this CPU hould be zero + * + * NOTE: However, the interrupt entry conditions can change due + * to previous processing by the interrupt handler that may + * instantiate a new thread that has irqcount > 0 and may then + * set the bit in g_cpu_irqset and g_cpu_irqlock = SP_LOCKED */ /* Handle nested calls to enter_critical_section() from the same @@ -165,19 +170,29 @@ irqstate_t enter_critical_section(void) g_cpu_nestcount[cpu] < UINT8_MAX); g_cpu_nestcount[cpu]++; } + + /* This is the first call to enter_critical_section from the + * interrupt handler. + */ + else { - /* First call to enter_critical_section. Test assumptions, then - * wait until we have the lock. + /* Make sure that the g_cpu_irqlock() was not already set + * by previous logic on this CPU that was executed by the + * interrupt handler. */ - DEBUGASSERT((g_cpu_irqset & (1 << cpu)) == 0); + if ((g_cpu_irqset & (1 << cpu)) == 0) + { + /* Wait until we can get the spinlock (meaning that we are + * no longer in the critical section). + */ - /* Wait until we can get the spinlock (meaning that we are no - * longer in the critical section). - */ + spin_lock(&g_cpu_irqlock); + } + + /* In any event, the nesting count is now one */ - spin_lock(&g_cpu_irqlock); g_cpu_nestcount[cpu] = 1; } } -- GitLab From 78fd358023fc26fe335a175e484a0cb8b250dac7 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 18 Nov 2016 08:20:52 -0600 Subject: [PATCH 441/734] Update some comments. --- sched/irq/irq_csection.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index f2f54910c9..a03c090e63 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -179,7 +179,9 @@ irqstate_t enter_critical_section(void) { /* Make sure that the g_cpu_irqlock() was not already set * by previous logic on this CPU that was executed by the - * interrupt handler. + * interrupt handler. We know that the bit in g_cpu_irqset + * for this CPU was zero on entry into the interrupt handler, + * so if it is non-zero now then we know that was the case. */ if ((g_cpu_irqset & (1 << cpu)) == 0) @@ -383,6 +385,10 @@ void leave_critical_section(irqstate_t flags) { /* Check if there are pending tasks and that pre-emption * is also enabled. + * + * REVISIT: There is an issue here! up_release_pending() + * must be called from within a critical section but here + * we have just left the critical section. */ if (g_pendingtasks.head != NULL && -- GitLab From 5363d0619ae16ad3637cc62141dec8d5cffcbaa8 Mon Sep 17 00:00:00 2001 From: Sebastien Lorquet Date: Fri, 18 Nov 2016 15:26:08 +0100 Subject: [PATCH 442/734] Fix warnings --- drivers/timers/timer.c | 5 ++--- include/nuttx/timers/timer.h | 1 + 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/timers/timer.c b/drivers/timers/timer.c index 80c76a1b62..667be5276d 100644 --- a/drivers/timers/timer.c +++ b/drivers/timers/timer.c @@ -131,7 +131,6 @@ static bool timer_notifier(FAR uint32_t *next_interval_us, FAR void *arg) #ifdef CONFIG_CAN_PASS_STRUCTS union sigval value; #endif - int ret; DEBUGASSERT(upper != NULL); @@ -139,9 +138,9 @@ static bool timer_notifier(FAR uint32_t *next_interval_us, FAR void *arg) #ifdef CONFIG_CAN_PASS_STRUCTS value.sival_ptr = upper->arg; - ret = sigqueue(upper->pid, upper->signo, value); + (void)sigqueue(upper->pid, upper->signo, value); #else - ret = sigqueue(upper->pid, upper->signo, upper->arg); + (void)sigqueue(upper->pid, upper->signo, upper->arg); #endif return true; diff --git a/include/nuttx/timers/timer.h b/include/nuttx/timers/timer.h index a89369d5df..ab78f5ea97 100644 --- a/include/nuttx/timers/timer.h +++ b/include/nuttx/timers/timer.h @@ -46,6 +46,7 @@ #include #include #include +#include #ifdef CONFIG_TIMER -- GitLab From ddba6de8bcd10dc04f5fa1252d36f08d879d20a1 Mon Sep 17 00:00:00 2001 From: Sebastien Lorquet Date: Fri, 18 Nov 2016 15:26:31 +0100 Subject: [PATCH 443/734] Add support for timers to nucleo l476 --- configs/nucleo-l476rg/include/board.h | 9 ++- configs/nucleo-l476rg/src/Makefile | 4 ++ configs/nucleo-l476rg/src/nucleo-l476rg.h | 12 ++++ configs/nucleo-l476rg/src/stm32_appinit.c | 13 ++++ configs/nucleo-l476rg/src/stm32_timer.c | 82 +++++++++++++++++++++++ 5 files changed, 117 insertions(+), 3 deletions(-) create mode 100644 configs/nucleo-l476rg/src/stm32_timer.c diff --git a/configs/nucleo-l476rg/include/board.h b/configs/nucleo-l476rg/include/board.h index 986844bf33..103f5a2e00 100644 --- a/configs/nucleo-l476rg/include/board.h +++ b/configs/nucleo-l476rg/include/board.h @@ -206,12 +206,15 @@ * Default is to use timer 5 (32-bit) and encoder on PA0/PA1 */ -#define GPIO_TIM5_CH1IN GPIO_TIM5_CH1IN_1 -#define GPIO_TIM5_CH2IN GPIO_TIM5_CH2IN_1 - #define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_1 #define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_1 +#define GPIO_TIM3_CH1IN GPIO_TIM3_CH1IN_3 +#define GPIO_TIM3_CH2IN GPIO_TIM3_CH2IN_3 + +#define GPIO_TIM5_CH1IN GPIO_TIM5_CH1IN_1 +#define GPIO_TIM5_CH2IN GPIO_TIM5_CH2IN_1 + /* PWM output for full bridge, uses config 1, because port E is N/A on QFP64 * CH1 | 1(A8) 2(E9) * CH2 | 1(A9) 2(E11) diff --git a/configs/nucleo-l476rg/src/Makefile b/configs/nucleo-l476rg/src/Makefile index c47701ba2c..a27b0f3b84 100644 --- a/configs/nucleo-l476rg/src/Makefile +++ b/configs/nucleo-l476rg/src/Makefile @@ -70,6 +70,10 @@ ifeq ($(CONFIG_PWM),y) CSRCS += stm32_pwm.c endif +ifeq ($(CONFIG_TIMER),y) +CSRCS += stm32_timer.c +endif + ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += stm32_appinit.c endif diff --git a/configs/nucleo-l476rg/src/nucleo-l476rg.h b/configs/nucleo-l476rg/src/nucleo-l476rg.h index d35d247349..50151a3fe5 100644 --- a/configs/nucleo-l476rg/src/nucleo-l476rg.h +++ b/configs/nucleo-l476rg/src/nucleo-l476rg.h @@ -351,4 +351,16 @@ int board_adc_initialize(void); int board_ajoy_initialize(void); #endif +/**************************************************************************** + * Name: board_timer_driver_initialize + * + * Description: + * Initialize and register a timer + * + ****************************************************************************/ + +#ifdef CONFIG_TIMER +int board_timer_driver_initialize(FAR const char *devpath, int timer); +#endif + #endif /* __CONFIGS_NUCLEO_L476RG_SRC_NUCLEO_L476RG_H */ diff --git a/configs/nucleo-l476rg/src/stm32_appinit.c b/configs/nucleo-l476rg/src/stm32_appinit.c index 4f805ff147..bb134ee6aa 100644 --- a/configs/nucleo-l476rg/src/stm32_appinit.c +++ b/configs/nucleo-l476rg/src/stm32_appinit.c @@ -205,6 +205,19 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_TIMER + /* Initialize and register the timer driver */ + + ret = board_timer_driver_initialize("/dev/timer0", 2); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the timer driver: %d\n", + ret); + return ret; + } +#endif + return OK; } diff --git a/configs/nucleo-l476rg/src/stm32_timer.c b/configs/nucleo-l476rg/src/stm32_timer.c new file mode 100644 index 0000000000..2d6f83835e --- /dev/null +++ b/configs/nucleo-l476rg/src/stm32_timer.c @@ -0,0 +1,82 @@ +/**************************************************************************** + * config/nucleo-l476rg/src/stm32_timer.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Copied from nucleo-f303 by Sebastien Lorquet + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "stm32l4_tim.h" +#include "nucleo-l476rg.h" + +#ifdef CONFIG_TIMER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_timer_driver_initialize + * + * Description: + * Configure the timer driver. + * + * Input Parameters: + * devpath - The full path to the timer device. This should be of the + * form /dev/timer0 + * timer - The timer's number. + * + * Returned Values: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int board_timer_driver_initialize(FAR const char *devpath, int timer) +{ + return stm32l4_timer_initialize(devpath, timer); +} + +#endif -- GitLab From 52560bba37bbde74c00a51d6d645a76300355027 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 18 Nov 2016 08:41:27 -0600 Subject: [PATCH 444/734] ENC28J60: Allow either HP or LP work queue to be used. --- drivers/net/Kconfig | 18 ++++++++++++++++++ drivers/net/enc28j60.c | 16 ++++++++++++---- 2 files changed, 30 insertions(+), 4 deletions(-) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 8852ead7b8..adf7aa5f1a 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -218,6 +218,24 @@ config ENC28J60_FREQUENCY ---help--- Define to use a different bus frequency +choice + prompt "Work queue" + default ENC28J60_LPWORK if SCHED_LPWORK + default ENC28J60_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + depends on SCHED_WORKQUEUE + ---help--- + Work queue support is required to use the ENC28J60 driver. If the low priority work queue is available, then it should be used by the ENC28J60. + +config ENC28J60_HPWORK + bool "High priority" + depends on SCHED_HPWORK + +config ENC28J60_LPWORK + bool "Low priority" + depends on SCHED_LPWORK + +endchoice # Work queue + config ENC28J60_HALFDUPPLEX bool "Enable half dupplex" default n diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c index 98edc13417..78da85e04c 100644 --- a/drivers/net/enc28j60.c +++ b/drivers/net/enc28j60.c @@ -115,8 +115,16 @@ /* We need to have the work queue to handle SPI interrupts */ -#ifndef CONFIG_SCHED_WORKQUEUE +#if !defined(CONFIG_SCHED_WORKQUEUE) # error "Worker thread support is required (CONFIG_SCHED_WORKQUEUE)" +#else +# if defined(CONFIG_ENC28J60_HPWORK) +# define ENCWORK HPWORK +# elif defined(CONFIG_ENC28J60_LPWORK) +# define ENCWORK LPWORK +# else +# error "Neither CONFIG_ENC28J60_HPWORK nor CONFIG_ENC28J60_LPWORK defined" +# endif #endif /* CONFIG_ENC28J60_DUMPPACKET will dump the contents of each packet to the console. */ @@ -1852,7 +1860,7 @@ static int enc_interrupt(int irq, FAR void *context) */ priv->lower->disable(priv->lower); - return work_queue(HPWORK, &priv->irqwork, enc_irqworker, (FAR void *)priv, 0); + return work_queue(ENCWORK, &priv->irqwork, enc_irqworker, (FAR void *)priv, 0); } /**************************************************************************** @@ -1944,7 +1952,7 @@ static void enc_txtimeout(int argc, uint32_t arg, ...) * can occur until we restart the Tx timeout watchdog. */ - ret = work_queue(HPWORK, &priv->towork, enc_toworker, (FAR void *)priv, 0); + ret = work_queue(ENCWORK, &priv->towork, enc_toworker, (FAR void *)priv, 0); DEBUGASSERT(ret == OK); UNUSED(ret); } @@ -2040,7 +2048,7 @@ static void enc_polltimer(int argc, uint32_t arg, ...) * occur until we restart the poll timeout watchdog. */ - ret = work_queue(HPWORK, &priv->pollwork, enc_pollworker, (FAR void *)priv, 0); + ret = work_queue(ENCWORK, &priv->pollwork, enc_pollworker, (FAR void *)priv, 0); DEBUGASSERT(ret == OK); UNUSED(ret); } -- GitLab From 936b55f60829073f8a2e9e77d41c54818157fa2a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 18 Nov 2016 09:22:49 -0600 Subject: [PATCH 445/734] drivers/net: Add option to use low-priority work queue to all drivers in drivers/net. Not yet added to all architecture-specific network drivers. --- drivers/net/Kconfig | 57 ++++++++++++++++++++++++++++++++++++++++ drivers/net/enc28j60.c | 2 +- drivers/net/encx24j600.c | 20 +++++++++----- drivers/net/ftmac100.c | 32 +++++++++++++++------- drivers/net/loopback.c | 20 +++++++++++--- drivers/net/skeleton.c | 30 ++++++++++++++------- drivers/net/tun.c | 18 ++++++++++--- net/Kconfig | 38 +++++++++++++++++++-------- 8 files changed, 172 insertions(+), 45 deletions(-) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index adf7aa5f1a..9bb451ab3a 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -16,6 +16,27 @@ config NETDEV_LOOPBACK networking devices that are enabled must be compatible with CONFIG_NET_NOINTS. +if NETDEV_LOOPBACK + +choice + prompt "Work queue" + default LOOPBACK_LPWORK if SCHED_LPWORK + default LOOPBACK_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + depends on SCHED_WORKQUEUE + ---help--- + Work queue support is required to use the LOOPBACK driver. If the low priority work queue is available, then it should be used by the LOOPBACK. + +config LOOPBACK_HPWORK + bool "High priority" + depends on SCHED_HPWORK + +config LOOPBACK_LPWORK + bool "Low priority" + depends on SCHED_LPWORK + +endchoice # Work queue +endif # NETDEV_LOOPBACK + config NETDEV_TELNET bool "Telnet driver" default n @@ -305,6 +326,24 @@ config ENCX24J600_NRXDESCR The ENC has a relative large packet buffer of 24kB which can be used to buffer multiple packets silmutaneously +choice + prompt "Work queue" + default ENCX24J600_LPWORK if SCHED_LPWORK + default ENCX24J600_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + depends on SCHED_WORKQUEUE + ---help--- + Work queue support is required to use the ENCX24J600 driver. If the low priority work queue is available, then it should be used by the ENCX24J600. + +config ENCX24J600_HPWORK + bool "High priority" + depends on SCHED_HPWORK + +config ENCX24J600_LPWORK + bool "Low priority" + depends on SCHED_LPWORK + +endchoice # Work queue + config ENCX24J600_DUMPPACKET bool "Dump Packets" default n @@ -399,6 +438,24 @@ config FTMAC100_MAC0_ENV_ADDR hex "MAC0 address location" default 0 +choice + prompt "Work queue" + default FTMAC100_LPWORK if SCHED_LPWORK + default FTMAC100_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + depends on SCHED_WORKQUEUE + ---help--- + Work queue support is required to use the FTMAC100 driver. If the low priority work queue is available, then it should be used by the FTMAC100. + +config FTMAC100_HPWORK + bool "High priority" + depends on SCHED_HPWORK + +config FTMAC100_LPWORK + bool "Low priority" + depends on SCHED_LPWORK + +endchoice # Work queue + endif # NET_FTMAC100 menuconfig NET_VNET diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c index 78da85e04c..a1c052f73d 100644 --- a/drivers/net/enc28j60.c +++ b/drivers/net/enc28j60.c @@ -138,7 +138,7 @@ /* The ENC28J60 will not do interrupt level processing */ #ifndef CONFIG_NET_NOINTS -# warrning "CONFIG_NET_NOINTS should be set" +# warning "CONFIG_NET_NOINTS should be set" #endif /* Low-level register debug */ diff --git a/drivers/net/encx24j600.c b/drivers/net/encx24j600.c index b829d9cd97..af415ac6d3 100644 --- a/drivers/net/encx24j600.c +++ b/drivers/net/encx24j600.c @@ -120,8 +120,16 @@ /* We need to have the work queue to handle SPI interrupts */ -#ifndef CONFIG_SCHED_WORKQUEUE +#if !defined(CONFIG_SCHED_WORKQUEUE) # error "Worker thread support is required (CONFIG_SCHED_WORKQUEUE)" +#else +# if defined(CONFIG_ENCX24J600_HPWORK) +# define ENCWORK HPWORK +# elif defined(CONFIG_ENCX24J600_LPWORK) +# define ENCWORK LPWORK +# else +# error "Neither CONFIG_ENCX24J600_HPWORK nor CONFIG_ENCX24J600_LPWORK defined" +# endif #endif /* CONFIG_ENCX24J600_DUMPPACKET will dump the contents of each packet to the console. */ @@ -482,7 +490,7 @@ static inline void enc_setethrst(FAR struct enc_driver_s *priv) { DEBUGASSERT(priv && priv->spi); - /* Select ENC28J60 chip */ + /* Select ENCX24J600 chip */ SPI_SELECT(priv->spi, SPIDEV_ETHERNET, true); @@ -492,7 +500,7 @@ static inline void enc_setethrst(FAR struct enc_driver_s *priv) up_udelay(25); - /* De-select ENC28J60 chip. */ + /* De-select ENCX24J600 chip. */ SPI_SELECT(priv->spi, SPIDEV_ETHERNET, false); enc_cmddump(ENC_SETETHRST); @@ -2017,7 +2025,7 @@ static int enc_interrupt(int irq, FAR void *context) */ priv->lower->disable(priv->lower); - return work_queue(HPWORK, &priv->irqwork, enc_irqworker, (FAR void *)priv, 0); + return work_queue(ENCWORK, &priv->irqwork, enc_irqworker, (FAR void *)priv, 0); } /**************************************************************************** @@ -2109,7 +2117,7 @@ static void enc_txtimeout(int argc, uint32_t arg, ...) * can occur until we restart the Tx timeout watchdog. */ - ret = work_queue(HPWORK, &priv->towork, enc_toworker, (FAR void *)priv, 0); + ret = work_queue(ENCWORK, &priv->towork, enc_toworker, (FAR void *)priv, 0); (void)ret; DEBUGASSERT(ret == OK); } @@ -2204,7 +2212,7 @@ static void enc_polltimer(int argc, uint32_t arg, ...) * occur until we restart the poll timeout watchdog. */ - ret = work_queue(HPWORK, &priv->pollwork, enc_pollworker, (FAR void *)priv, 0); + ret = work_queue(ENCWORK, &priv->pollwork, enc_pollworker, (FAR void *)priv, 0); (void)ret; DEBUGASSERT(ret == OK); } diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c index 32890af906..c1fbec650a 100644 --- a/drivers/net/ftmac100.c +++ b/drivers/net/ftmac100.c @@ -72,12 +72,24 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* If processing is not done at the interrupt level, then high priority - * work queue support is required. +/* If processing is not done at the interrupt level, then work queue support + * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_HPWORK) -# error High priority work queue support is required +#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required in this configuration (CONFIG_SCHED_WORKQUEUE) +#endif + +/* Use the low priority work queue if possible */ + +#if defined(CONFIG_SCHED_WORKQUEUE) +# if defined(CONFIG_FTMAC100_HPWORK) +# define FTMAWORK HPWORK +# elif defined(CONFIG_FTMAC100_LPWORK) +# define FTMAWORK LPWORK +# else +# error Neither CONFIG_FTMAC100_HPWORK nor CONFIG_FTMAC100_LPWORK defined +# endif #endif /* CONFIG_FTMAC100_NINTERFACES determines the number of physical interfaces @@ -1049,11 +1061,11 @@ static int ftmac100_interrupt(int irq, FAR void *context) /* Cancel any pending poll work */ - work_cancel(HPWORK, &priv->ft_work); + work_cancel(FTMAWORK, &priv->ft_work); /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->ft_work, ftmac100_interrupt_work, priv, 0); + work_queue(FTMAWORK, &priv->ft_work, ftmac100_interrupt_work, priv, 0); leave_critical_section(flags); #else @@ -1160,11 +1172,11 @@ static void ftmac100_txtimeout_expiry(int argc, uint32_t arg, ...) * on work that has already been started. */ - work_cancel(HPWORK, &priv->ft_work); + work_cancel(FTMAWORK, &priv->ft_work); /* Schedule to perform the TX timeout processing on the worker thread. */ - work_queue(HPWORK, &priv->ft_work, ftmac100_txtimeout_work, priv, 0); + work_queue(FTMAWORK, &priv->ft_work, ftmac100_txtimeout_work, priv, 0); #else /* Process the timeout now */ @@ -1270,7 +1282,7 @@ static void ftmac100_poll_expiry(int argc, uint32_t arg, ...) { /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->ft_work, ftmac100_poll_work, priv, 0); + work_queue(FTMAWORK, &priv->ft_work, ftmac100_poll_work, priv, 0); } else { @@ -1491,7 +1503,7 @@ static int ftmac100_txavail(struct net_driver_s *dev) { /* Schedule to serialize the poll on the worker thread. */ - work_queue(HPWORK, &priv->ft_work, ftmac100_txavail_work, priv, 0); + work_queue(FTMAWORK, &priv->ft_work, ftmac100_txavail_work, priv, 0); } #else diff --git a/drivers/net/loopback.c b/drivers/net/loopback.c index f0aa532a01..a9c1b6a819 100644 --- a/drivers/net/loopback.c +++ b/drivers/net/loopback.c @@ -67,12 +67,24 @@ * Pre-processor Definitions ****************************************************************************/ +/* Non-network-driven configuration is required */ + #ifndef CONFIG_NET_NOINTS # error CONFIG_NET_NOINTS must be selected #endif -#ifndef CONFIG_SCHED_HPWORK -# error High priority work queue support is required (CONFIG_SCHED_HPWORK) +/* We need to have the work queue to handle SPI interrupts */ + +#if !defined(CONFIG_SCHED_WORKQUEUE) +# error Worker thread support is required (CONFIG_SCHED_WORKQUEUE) +#else +# if defined(CONFIG_LOOPBACK_HPWORK) +# define LPBKWORK HPWORK +# elif defined(CONFIG_LOOPBACK_LPWORK) +# define LPBKWORK LPWORK +# else +# error Neither CONFIG_LOOPBACK_HPWORK nor CONFIG_LOOPBACK_LPWORK defined +# endif #endif /* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per second */ @@ -289,7 +301,7 @@ static void lo_poll_expiry(int argc, wdparm_t arg, ...) { /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->lo_work, lo_poll_work, priv, 0); + work_queue(LPBKWORK, &priv->lo_work, lo_poll_work, priv, 0); } else { @@ -444,7 +456,7 @@ static int lo_txavail(FAR struct net_driver_s *dev) { /* Schedule to serialize the poll on the worker thread. */ - work_queue(HPWORK, &priv->lo_work, lo_txavail_work, priv, 0); + work_queue(LPBKWORK, &priv->lo_work, lo_txavail_work, priv, 0); } return OK; diff --git a/drivers/net/skeleton.c b/drivers/net/skeleton.c index 82568cb091..ea24cf688c 100644 --- a/drivers/net/skeleton.c +++ b/drivers/net/skeleton.c @@ -67,12 +67,24 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* If processing is not done at the interrupt level, then high priority - * work queue support is required. +/* If processing is not done at the interrupt level, then work queue support + * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_HPWORK) -# error High priority work queue support is required +#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required in this configuration (CONFIG_SCHED_WORKQUEUE) +#endif + +/* Use the low priority work queue if possible */ + +#if defined(CONFIG_SCHED_WORKQUEUE) +# if defined(CONFIG_skeleton_HPWORK) +# define skelWORK HPWORK +# elif defined(CONFIG_skeleton_LPWORK) +# define skelWORK LPWORK +# else +# error Neither CONFIG_skeleton_HPWORK nor CONFIG_skeleton_LPWORK defined +# endif #endif /* CONFIG_skeleton_NINTERFACES determines the number of physical interfaces @@ -598,7 +610,7 @@ static int skel_interrupt(int irq, FAR void *context) /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->sk_work, skel_interrupt_work, priv, 0); + work_queue(skelWORK, &priv->sk_work, skel_interrupt_work, priv, 0); #else /* Process the interrupt now */ @@ -705,11 +717,11 @@ static void skel_txtimeout_expiry(int argc, wdparm_t arg, ...) * on work that has already been started. */ - work_cancel(HPWORK, &priv->sk_work); + work_cancel(skelWORK, &priv->sk_work); /* Schedule to perform the TX timeout processing on the worker thread. */ - work_queue(HPWORK, &priv->sk_work, skel_txtimeout_work, priv, 0); + work_queue(skelWORK, &priv->sk_work, skel_txtimeout_work, priv, 0); #else /* Process the timeout now */ @@ -815,7 +827,7 @@ static void skel_poll_expiry(int argc, wdparm_t arg, ...) { /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->sk_work, skel_poll_work, priv, 0); + work_queue(skelWORK, &priv->sk_work, skel_poll_work, priv, 0); } else { @@ -1026,7 +1038,7 @@ static int skel_txavail(FAR struct net_driver_s *dev) { /* Schedule to serialize the poll on the worker thread. */ - work_queue(HPWORK, &priv->sk_work, skel_txavail_work, priv, 0); + work_queue(skelWORK, &priv->sk_work, skel_txavail_work, priv, 0); } #else diff --git a/drivers/net/tun.c b/drivers/net/tun.c index b4938c4e50..aaa411a613 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -79,8 +79,18 @@ * work queue support is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_HPWORK) -# error High priority work queue support is required +#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required in this configuration (CONFIG_SCHED_WORKQUEUE) +#endif + +#if defined(CONFIG_SCHED_WORKQUEUE) +# if defined(CONFIG_TUN_HPWORK) +# define TUNWORK HPWORK +# elif defined(CONFIG_TUN_LPWORK) +# define TUNWORK LPWORK +# else +# error "Neither CONFIG_TUN_HPWORK nor CONFIG_TUN_LPWORK defined" +# endif #endif /* CONFIG_TUN_NINTERFACES determines the number of physical interfaces @@ -622,9 +632,9 @@ static void tun_poll_expiry(int argc, wdparm_t arg, ...) if (work_available(&priv->work)) { - /* Schedule to perform the interrupt processing on the worker thread. */ + /* Schedule to perform the timer expiration on the worker thread. */ - work_queue(HPWORK, &priv->work, tun_poll_work, priv, 0); + work_queue(TUNWORK, &priv->work, tun_poll_work, priv, 0); } else { diff --git a/net/Kconfig b/net/Kconfig index 733e993f9d..2c1aecd291 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -117,17 +117,6 @@ config NET_SLIP_TCP_RECVWNDO incoming data, or high (32768 bytes) if the application processes data quickly. -config NET_TUN_MTU - int "TUN packet buffer size (MTU)" - default 296 - depends on NET_TUN - range 296 1518 - -config NET_TUN_TCP_RECVWNDO - int "TUN TCP receive window size" - default 256 - depends on NET_TUN && NET_TCP - config NET_GUARDSIZE int "Driver I/O guard size" default 2 @@ -242,6 +231,33 @@ config TUN_NINTERFACES interfaces to support. Default: 1 +config NET_TUN_MTU + int "TUN packet buffer size (MTU)" + default 296 + range 296 1518 + +config NET_TUN_TCP_RECVWNDO + int "TUN TCP receive window size" + default 256 + depends on NET_TCP + +choice + prompt "Work queue" + default LOOPBACK_LPWORK if SCHED_LPWORK + default TUN_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + depends on SCHED_WORKQUEUE + ---help--- + Work queue support is required to use the TUN driver. If the low priority work queue is available, then it should be used by the TUN. + +config TUN_HPWORK + bool "High priority" + depends on SCHED_HPWORK + +config TUN_LPWORK + bool "Low priority" + depends on SCHED_LPWORK + +endchoice # Work queue endif # NET_TUN endmenu # Data link support -- GitLab From 69e9f8638d17b4c33118d3892e66486cd67f1f56 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 18 Nov 2016 13:57:30 -0600 Subject: [PATCH 446/734] Most interrupt handling logic interacts with tasks via standard mechanism such as sem_post, sigqueue, mq_send, etc. This all call enter_critical_section and are assumed to be safe in the SMP case. But certain logic interacts with tasks in different ways. The only one that comes to mind are wdogs. There is a tasking interface that to manipulate wdogs, and a different interface in the timer interrupt handling logic to manage wdog expirations. In the normal case, this is fine. Since the tasking level code calls enter_critical_section, interrupts are disabled an no conflicts can occur. But that may not be the case in the SMP case. Most architectures do not permit disabling interrupts on other CPUs so enter_critical_section must work differently: Locks are required to protect code. So this change adds locking (via enter_critical section) to wdog expiration logic for the the case if the SMP configuration. --- sched/irq/irq_csection.c | 19 ++++++++++----- sched/wdog/wd_start.c | 50 +++++++++++++++++++++++++++++++++++++--- 2 files changed, 60 insertions(+), 9 deletions(-) diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index a03c090e63..8071da9758 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -263,6 +263,12 @@ irqstate_t enter_critical_section(void) #else /* defined(CONFIG_SCHED_INSTRUMENTATION_CSECTION) */ irqstate_t enter_critical_section(void) { + irqstate_t ret; + + /* Disable interrupts */ + + ret = up_irq_save(); + /* Check if we were called from an interrupt handler and that the task * lists have been initialized. */ @@ -272,14 +278,14 @@ irqstate_t enter_critical_section(void) FAR struct tcb_s *rtcb = this_task(); DEBUGASSERT(rtcb != NULL); - /* No.. note that we have entered the critical section */ + /* Yes.. Note that we have entered the critical section */ sched_note_csection(rtcb, true); } - /* And disable interrupts */ + /* Return interrupt status */ - return up_irq_save(); + return ret; } #endif @@ -386,9 +392,10 @@ void leave_critical_section(irqstate_t flags) /* Check if there are pending tasks and that pre-emption * is also enabled. * - * REVISIT: There is an issue here! up_release_pending() + * REVISIT: Is there an issue here? up_release_pending() * must be called from within a critical section but here - * we have just left the critical section. + * we have just left the critical section. At least we + * still have interrupts disabled on this CPU. */ if (g_pendingtasks.head != NULL && @@ -429,7 +436,7 @@ void leave_critical_section(irqstate_t flags) FAR struct tcb_s *rtcb = this_task(); DEBUGASSERT(rtcb != NULL); - /* Note that we have left the critical section */ + /* Yes.. Note that we have left the critical section */ sched_note_csection(rtcb, false); } diff --git a/sched/wdog/wd_start.c b/sched/wdog/wd_start.c index 898f80060f..149b95427e 100644 --- a/sched/wdog/wd_start.c +++ b/sched/wdog/wd_start.c @@ -421,11 +421,28 @@ int wd_start(WDOG_ID wdog, int32_t delay, wdentry_t wdentry, int argc, ...) unsigned int wd_timer(int ticks) { FAR struct wdog_s *wdog; +#ifdef CONFIG_SMP + irqstate_t flags; +#endif + unsigned int ret; int decr; +#ifdef CONFIG_SMP + /* We are in an interrupt handler as, as a consequence, interrupts are + * disabled. But in the SMP case, interrupst MAY be disabled only on + * the local CPU since most architectures do not permit disabling + * interrupts on other CPUS. + * + * Hence, we must follow rules for critical sections even here in the + * SMP case. + */ + + flags = enter_critical_section(); +#endif + /* Check if there are any active watchdogs to process */ - while (g_wdactivelist.head && ticks > 0) + while (g_wdactivelist.head != NULL && ticks > 0) { /* Get the watchdog at the head of the list */ @@ -455,13 +472,36 @@ unsigned int wd_timer(int ticks) /* Return the delay for the next watchdog to expire */ - return g_wdactivelist.head ? - ((FAR struct wdog_s *)g_wdactivelist.head)->lag : 0; + ret = g_wdactivelist.head ? + ((FAR struct wdog_s *)g_wdactivelist.head)->lag : 0; + +#ifdef CONFIG_SMP + leave_critical_section(flags); +#endif + + /* Return the delay for the next watchdog to expire */ + + return ret; } #else void wd_timer(void) { +#ifdef CONFIG_SMP + irqstate_t flags; + + /* We are in an interrupt handler as, as a consequence, interrupts are + * disabled. But in the SMP case, interrupst MAY be disabled only on + * the local CPU since most architectures do not permit disabling + * interrupts on other CPUS. + * + * Hence, we must follow rules for critical sections even here in the + * SMP case. + */ + + flags = enter_critical_section(); +#endif + /* Check if there are any active watchdogs to process */ if (g_wdactivelist.head) @@ -474,5 +514,9 @@ void wd_timer(void) wd_expiration(); } + +#ifdef CONFIG_SMP + leave_critical_section(flags); +#endif } #endif /* CONFIG_SCHED_TICKLESS */ -- GitLab From 48d9fff95abb700fc367a790b7f96df94fb7aad3 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 18 Nov 2016 17:18:35 -0600 Subject: [PATCH 447/734] Update ChangeLog --- ChangeLog | 362 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 360 insertions(+), 2 deletions(-) diff --git a/ChangeLog b/ChangeLog index 2ff44a1710..b5567cf8f3 100755 --- a/ChangeLog +++ b/ChangeLog @@ -1676,7 +1676,7 @@ * configs/*/ld.script: Removed 'sh_link not set for section .ARM.edix' for a few of the builds. In you have this warning, it can be removed with the following change to the ld.script file: - + + __exidx_start = ABSOLUTE(.); .ARM.exidx : { - __exidx_start = ABSOLUTE(.); @@ -4374,7 +4374,7 @@ significant amounts of time (2013-03-18). * arch/arm/src/armv7-h/ram_vectors.h, up_ramvec_*.c, arch/arm/src/*/*_irq.c, and Make.defs: Add support for modifiable interrupt vectors in RAM - (2013-03-18). + (2013-03-18). * arch/arm/src/armv7-m/up_exception.S, sam3u/sam3u_vectors.S, and lpc17xx/lpc17_vectors.S: In exception handling with CONFIG_NUTTX_KERNEL, need to explicity set and clear the privilege bit in the CONTROL @@ -12772,5 +12772,363 @@ * STM32 DMA2D: fix an error in up_dma2dcreatelayer where an invalid pointer was returned when a certain underlying function failed. From Jens Gräf (2016-10-07). + * include/nuttx/fs/nxffs.h: Needs forward reference to struct mtd_dev_s + and needs to include stdbool.h (2016-10-09). + * STM32F103 Minimum: Note in Kconfig that the board supports buttons. + From Alan Carvalho de Assis (2016-10-11). + * STM32F103 Minimum: Add button support. From Alan Carvalho de Assis + (2016-10-11). + * arch/arm/kinetis and configs/freedom-k64f: Add UID Unique ID. From + Neil Hancock (2016-10-13). + * arch/arm/src/stm32l4: (1) too many parentheses when calculating max + chan count and (2) channel 4 does not have a complementary output. From + Sebastien Lorquet (2016-10-14). + * arch/arm/src/stm32l4: Support Complementary PWM outputs on STM32L4. + From Sebastien Lorquet (2016-10-14). + * Support PWM testing on board nucleo-l476. From Sebastien Lorquet + (2016-10-14). + * arch/arm/src/stm32: Support oversampling by 8 for the STM32 F4. + From David Sidrane (2016-10-15). + * libc/stdio: Fixes sscanf %sn where strlen(data) < n. From David + Sidrane (2016-10-15). + * arch/risc-v: Add support for the RISC-V architecture and + configs/nr5m100-nexys4 board. I will be making the FPGA code for + this available soon (within a week I would say). The board support on + this is pretty thin, but it seems like maybe a good idea to get the base + RISC-V stuff in since there are people interested in it. From Ken + Pettit (2016-10-16). + * C library: Add a dummy setlocale() function to avoid drawing the + function from newlib (2016-10-17). + * libc/wchar: Add wcslen, wmemchr, wmemcmp, wmemcpy and wmemset to NuttX. + From Alan Carvalho de Assis (2016-10-17). + * syscalls: Add setlocale to libc.csv (2016-10-17). + * libc/locale: Add clocale header file (2016-10-18). + * libc/wchar: Add functions btowc, mbrtowc, mbtowc, wcscmp, wcscoll, + wmemmove. From Alan Carvalho de Assis (2016-10-18). + * usbhost/enumerate: fix possible buffer overwrite. From Janne Rosberg + (2016-10-18). + * configs/Board.mk: Add extra clean operations (2016-10-18). + * usbhost/composite: fix compile; missing semicolons. From Jann + Rosberg (2016-10-18). + * libc/stdio: Include wchar.h in lib_libvsprintf.c to fix compilation + error. From Alan Carvalho de Assis (2016-10-18). + * arch/arm/src/kinetis: Added missing headers. From David Sidrane + (2016-10-18). + * arch/arm/src/kinetis: Kinetis broke out SPI to kinetis/kinetis_spi.h. + From David Sidrane (2016-10-18). + * arch/arm/src/kinetis: Broke out DMA to use the modern Nuttx chip + inclusion - still STUBS. From David Sidrane (2016-10-18). + * arch/arm/src/kinetis: Kinetis Support ARMV7 Common Vector and FPU. + From David Sidrane (2016-10-18). + * arch/arm/src/kinetis: Kinetis Allow CONFIG_ARMV7M_CMNVECTOR, + CONFIG_STACK_COLORATION, CONFIG_ARCH_FPU. From David Sidrane + (2016-10-18). + * arch/arm/src/kinetis: Kinetis i2c driver offset swapped for value + in kinetis_i2c_putreg. From David Sidrane (2016-10-18). + * Add functions wcrtomb, wcslcpy, wcsxfrm, wctob, wctomb, wctype, + localeconv, strcoll, strxfrm. From Alan Carvalho de Assis + (2016-10-18). + * libc/wctype: Add wctype.h; Move lib_wctype.c to libc/wctype. + From Alan Carvalho de Assis (2016-10-18). + * include/: Modify locale.h to add localeconv() and lconv structure. + From Alan Carvalho de Assis (2016-10-18). + * include/sys/time.h: timersub macro modified per recommendations of + phreakuencies (2016-10-18). + * include/: Add isblank() macro to ctype.h. From Alan Carvalho de + Assis (2016-10-19). + * libc/wctype: Add iswctype, towlower, towupper and wcsftime functions. + From Alan Carvalho de Assis (2016-10-19). + * syslog: Fixes required for file syslog output. From Max Kriegleder + (2016-10-19). + * arch/arm/src/stm32: add TIM8 to STM32F103V pinmap. From Maciej Wójcik + (2016-10-19). + * libc/locale: Allows c++ code to compile with or without + CONFIG_LIBC_LOCALE and will generate a link error if CONFIG_LIBC_LOCALE + is not defined and setlocale is referneced. With CONFIG_LIBC_LOCALE + defined setlocale will act as if MB string is not supported and return + "C" for POSIX. C and "". From David Sidrane (2016-10-19). + * Add vectors for interrupt levels 2-6 (2016-10-20). + * strtof: Add strtof() as simply a copy of strtod with types and + limits changed (2016-10-20). + * arch/arm/src/stm32v7: Register the watchdog device at the configured + device path CONFIG_WATCHDOG_DEVPATH vs. hard-coded /dev/wdt. From Frank + Benkert (2016-10-21). + * configs/*/defdonf The buttons example was changed to archbuttons. As + a result all of the button configurations are broken and need some + renaming in the defconfig files. Noted by Frank Berkert (2016-10-21). + * configs/stm32f103-minimum: Add support to PWM on STM32F103-Minimum + board. From Alan Carvalho de Assis (2016-10-21). + * include/ctype.h and cxx/cctype: Implement ctype.h functions as inline + if possible. cctype can then properly select namespace (2016-10-22). + * libc/unisted: Add strtold() (2016-10-22). + * sscanf: Use strtof() instead of strtod() if a short floating point + value was requested. The should help performance with MCUs with 32-bit + FPU support with some additional code size (2016-10-22). + * Remove support for software prioritization of interrupts (2016-10-23). + * drivers/net/tun.c: Fix bug in TUN interface driver. From Max + Nekludov (2016-10-24). + * arch/arm/src/stm32: A new implementation of the STM32 F4 I2C bottom + half. The commin I2C as this did not handled correctly in the current + implementation (see also https://github.com/PX4/NuttX/issues/54). The + changes almost exclusively affect the ISR. From Max Kriegleder + (2016-10-24). + * arch/arm/src/stm32l4: Fix I2C devices RCC registers. From Sebastien + Lorquet (2016-10-25). + * arch/arm/src/stm32l4: Enable and renames for 32l4 UARTs 4 and 5. + From Sebastien Lorquet (2016-10-25). + * configs/stm32f103-minimum: Fix Timers 2 to 7 clock frequencies. + From Alan Carvalho de Assis (2016-10-25). + * arch/arm/src/stm32: Initial implemention of the STM32 F37xx SDADC + module. There are also changes to ADC, DAC modules. SDADC has only been + tested in DMA mode and does not support external TIMER triggers. This + is a work in progress. From Marc Rechté (2016-10-25). + * Add logic to attach peripheral interrupt sources to CPU interrupts + (2016-10-25). + * CHxN channels are always outputs. From Sebastien Lorquet + (2016-10-26). + * sched/semaphore: Within the OS, when a thread obtains a semaphore + count it must call sem_addholder() if CONFIG_PRIORITY_INHERITANCE is + enabled. If a count is available, then sem_wait() calls + sem_addholder(), otherwise it waited for the semaphore and called + sem_addholder() when it eventually received the count. + + This caused a problem when the thread calling sem_wait() was very + low priority. When it received the count, there may be higher + priority threads "hogging" the CPU that prevent the lower priority + task from running and, as a result, the sem_addholder() may be + elayed indefinitely. + + The fix was to have sem_post() call sem_addholder() just before + restarting the thread waiting for the semaphore count. + + This problem was noted by Benix Vincent who also suggested the + solution (2016-10-26). + * configs/stm32f103-minimum: Add RGB LED support on STM32F103 Minimum + board. From Alan Carvalho de Assis (2016-10-26). + * arch/arm/src/stm32f7: stm32_i2c.c Dejavu. Fixes a bug previously + found in the F4. From David Sidrane (2016-10-26). + * arch/arm/src/stm32f7: stm32f76xx77xx_pinmap.h Missed one. From + David Sidrane (2016-10-26). + * LPC32xx serial: Fix a typo in ioctl TIOCSRS485 ioctl. From Vytautas + Lukenskas (2016-10-27). + * sched/clock: Correct clock initialization. The correct range for + the month is 0-11 but is entered as 1-12 in the .config file + (2016-10-27). + * arch/*/include: Add architecture-specific inttypes.h. From Paul + A. Patience (2016-10-27). + * sched/Kconfig: Add ranges to START_YEAR, MONTH, and DAY (2016-10-28). + * configs/nucleo-f303re: Add STM32 F303RE hello configuration; remove + duplicate setting from board.h. From Marc Rechté (2016-10-18). + * arch/arm/src/lpc32xx: Restore RS485 mode on serial port open (if + RS485 is enabled via menuconfig). From Vytautas Lukenskas (2016-10-28). + * arch/arm/src/stm32f7: otgdev fixed typo. From David Sidrane + (2016-10-28). + * arch/xtensa: Basic architectural support for Xtensa processors and + the Expressif. ESP32 added. Totally untested on initial release + (2016-10-31). + * configs/esp32-core: Basic support for Expressif ESP32 Core v2 board + added. The initial release includes an NSH and an SMP test + configuration. Totally untested on initial relesae (2016-10-31). + * configs/bambino-200e: Add basic support to Micromint Bambino 200E + board. This includes contributions from Jim Wolfman. From Alan + Carvalho de Assis (2016-11-01). + * drivers/mtd/at24xx.c: Added EEPROM timeout. Fromo Aleksandr + Vyhovanec (2016-11-02). + * arch/misoc: Adds basic support for the Misoc procoessors and the + LM32 in particular. From Ramtin Amin (2016-11-01). + * configs/misoc. Board support for testing Misoc LM32 with Qemu. + From Ramtin Amin (2016-11-01). + * arch/arm/src/stm32: I think, that Size is (highest address+1 - Base + address). Base address has been removed and if address+count >= size + we are outside of the Flash. From David Sidrane (2016-11-01). + * sched/semaphore, sched/phread/, libc/semaphore, libc/pthread: Add + pthread_mutexattr_get/set_protocol and non-standard sem_get/set_protocol. + These may use to enable or disable priority inheritance on a single + semaphore (2016-11-02). + * arch/arm/src/stm32: Fix ADC compilation error when DMA isn't enabled. + From Paul A. Patience (2016-11-02). + * drivers/ and drivers/spi: Fix Kconfig warning. This commit moves the + ARCH_HAVE_SPI options outside the check for SPI. Those options don't + depend on SPI, and Kconfig files in arch/ enable them even if SPI isn't + enabled. + + Sourcing the driver's Kconfig in drivers/Kconfig only if support for + the driver is enabled prevents us from defining these ARCH_HAVE options + in the driver's Kconfig. We should probably remove the other checks in + drivers/Kconfig and check if the drivers are enabled only in their + Kconfig. From Paul A. Patience (2016-11-02). + * Move protoypes for the non-standard include/semaphore.h file to the + non-standard include/nuttx/semaphore.h with the other non-standard + semaphore interfaces (2016-11-02). + * include/semaphores.h: Provide macros for sem_setprotocol() and + sem_getprotocol() if priority inheritance is not enabled. More + SEM_PRIO_* definitions to include/nuttx/semaphore.h (2016-11-02). + * drivers/serial.c: Make sure that priority inheritance is not + enabled for the signaling semaphores used in the serial driver + (2016-11-03). + * arch/arm/src/stm32f7: Fix to SPI-Master driver. Without this the + chip select decoding feature will not work properly. From Michael + Spahlinger (2016-11-03). + * drivers/, net/, fs/, sched, arch/, graphics/, libnx,: Disable + priority inheritance on all semaphores used for signaling (2016-11-03). + * sched/semaphore: Handle a case of missing proxy for sem_setprotocol. + Reorder so that (1) this error is avoided, and (2) >No proxy is needed + if priority inheritance is not enabled (2016-11-03). + * config/*/defconfgs: More fallout from name change of + apps/examples/buttons to archbuttons (2016-11-03). + * configs/nucleo_f303re: Various fixes to get the adc configuration + building again after PR. Refresh all configurations (2016-11-03). + * arch/misoc/src/common: Add interrupting Misoc serial driver. From + Ramtin Amin (2016-11-04) + * Fix a number of header files with mismatched 'extern C {' and '}' + (2016-11-05). + * Provide do-nothing stubs for mutex attribute interfaces if features + ot enabled. pthread_cond includes a signaling semaphore and should + call sem_setprotocol (2016-11-05). + * arch/arm/src/armv7-r: Fix compilation error. This commit fixes + compilation errors on MPU support for ARMv7-R. From Heesub Shin + (2016-11-06). + * arch/arm/src/armv7-r: fix invalid drbar handling. In ARMv7-R, + [31:5] bits of DRBAR is physical base address and other bits are + reserved and SBZ. Thus, there is no point in passing other than the + base address. From Heesub Shin (2016-11-06). + * arch/arm/src/armv7-r: Remove the redundant update on SCTLR. + mpu_control() is invoking cp15_wrsctlr() around SCTLR update + redundantly. From Heesub Shin (2016-11-06). + * arch/arm/src/armv7-r: add new Kconfig entries for d/i-cache. + Unlike in ARMv7-A/M, Kconfig entries for data and instruction caches + are currently missing in ARMv7-R. This commit adds those missing + Kconfig entries. Actual implmenetation for those functions will be + added in the subsequent patches. From Heesub Shin (2016-11-06). + * arch/arm/src/armv7-r: add cache handling functions. This commit + adds functions for enabling and disabling d/i-caches which were + missing for ARMv7-R. From Heesub Shin (2016-11-06). + * arch/arm/src/armv7-r: fix typo in mpu support. s/ARMV7M/ARMV7R/g. + From Heesub Shin (2016-11-06). + * arch/arm/src/armv7-r: fix CPSR corruption after exception handling. + A sporadic hang with consequent crash was observed when booting. It + seemed to be caused by the corrupted or wrong CPSR restored on return + from exception. NuttX restores the context using code like this: + + msr spsr, r1 + + GCC translates this to: + + msr spsr_fc, r1 + + As a result, not all SPSR fields are updated on exception return. + This should be: + + msr spsr_fsxc, r1 + + On some evaluation boards, spsr_svc may have totally invalid value at + power-on-reset. As it is not initialized at boot, the code above may + result in the corruption of cpsr and thus unexpected behavior. + + From Heesub Shin (2016-11-06). + * arch/arm/src/armv7-r: fix to restore the Thumb flag in CPSR. Thumb + flag in CPSR is not restored back when the context switch occurs while + executing thumb instruction. From Heesub Shin (2016-11-06). + * sched/wqueue: When queuing new LP work, don't signal any threads + if they are all busy. From Heesub Shin (2016-11-06). + * sched/wqueue: Signal sent from work_signal() may interrupt the low + priority worker thread that is already running. For example, the worker + thread that is waiting for a semaphore could be woken up by the signal + and break any synchronization assumption as a result. It also does not + make any sense to send signal if it is already running and busy. This + commit fixes it. From Heesub Shin (2016-11-06). + * arch/arm/src/stm32f7: STM32F7 SD/MMC driver depends on + CONFIG_SDIO_DMA which is only defined in stm32/Kconfig. Changed to + CONFIG_STM32F7_SDMMC_DMA and defined in stm32f7/Kconfig (2016-11-07). + * arch/arm/src/stm32: Add PWM driver support for STMF37xx. The + changes have been tested successfuly for TIM4 and TIM17 (different + IPs). From Marc Rechté (2016-11-07). + * sched/semaphore: sem_trywait() no longer modifies the errno value + UNLESS an error occurs. This allows these functions to be used + internally without clobbering the errno value. From Freddie Chopin + (2016-11-09). + * arch/arm/src/stm32l4: Change the way to configure quadrature encoder + prescalers. From Sebastien Lorquet (2016-11-09). + * libc/unisted: Patch brings strtol() and related functions more + conformant with POSIX. Corner cases like strtol(-2147483648, NULL, 10) + now pass clang -fsanitize=integer without warnings. From Juha Niskanen + (2016-11-10). + * drivers/sensors and configs/stm32f103-minimum: Add Vishay VEML6070 + driver and support for STM32F103-Minimum board. From From Alan + Carvalho de Assis(2016-11-13). + * Misoc LM32: Corrects a bug that never occured in qemu on simulation or + real fpga. The error was that the r1 register was being modified out of + context switching and not restoring it. From Ramtin Amin (2016-11-14) + * arch/arm/src/samv71: A problem occurred with the SAMV7 USBDEVHS driver + if the USB cable is unplugged while a large amount of data is send over + an IN endpoint using DMA. If the USB cable is plugged in again after a + few seconds it is not possible to send data over this IN endpoint again, + all other endpoints work as expected. + + The problem occurs because if the USB cable is unplugged while an DMA + transfer is in flight the transfer is canceled but the register + SAM_USBHS_DEVDMACTRL is left in an undefined state. The problem was + fixed the problem by resetting the register SAM_USBHS_DEVDMACTRL to a + known state. Additionally all pending interrupts are cleared. + + From Stefan Kolb (2016-11-14). + * configs/esp32-core: ESP32 Core v2: Add configuration to supporting + linking NuttX for execution out of IRAM (2016-11-14). + * libc/unistd: sleep() was returning remaining nanoseconds (kind of), + instead the remaining seconds. From Eunbong Song (2016-11-15). + * sched/irq: Fixes for the SMP case: (1) Change order for SMP case in + enter_critical_section: (1) Disable local interrupts BEFORE taking + spinlock and (2) If SMP is enabled, if any interrupt handler calls + enter_critical_section(), it should take the spinlock. (2016-11-15). + * arch/xtensa: Add EXPERIMENTAL hooks to support lazy Xtensa co- + processor state restore in the future (2016-11-16). + * Add some experimental changes to enter/leave_critical_section to + deal with the case where interrupts are disabled only on the local + CPU (2016-11-16). + * sched/irq: Add logic to handled nested calls to + enter_critical_section() from interrupts handlers (with SMP) + (2016-11-16). + * drivers/timer: Remove the timer driver TIOC_SETHANDLER IOCTL call. + This calls directly from the timer driver into application code. That + is non-standard, non-portable, and cannot be supported (2016-11-17). + *drivers/timer: Add timer driver hooks to support signal notification + of timer expiration. Commented out because invasive interface changes + would also be required to complete the implementation (2016-11-17). + * arch/arm/src/armv7-m: Fix double allocation of MPU region in mmu.h + (2016-11-17). + * timer driver: Use signal to notify of timer expiration. Add generic + argument so that there can be additional usage. From Sebastien Lorquet + (2016-11-17). + * All timer lower half drivers. Port Sebastien's changes to all all + other implementations of the timer lower half. Very many just and + untested. Expect some problems. (2016-11-17). + * sched/irq: irq_csection() has a bad assumption in the SMP case. It + assumed that the state of certain variables. That was true on entry + into the interrupt handler, but might change to the execution of logic + within the interrupt handler (2016-11-18). + * config/ nucleo-l476rg: Add support for timers to nucleo l476. From + Sebastien Lorquet (2016-11-18). + * drivers/net: Add option to use low-priority work queue to all drivers + in drivers/net. Not yet added to all architecture-specific network + drivers (2016-11-18). + * sched/wdog: Most interrupt handling logic interacts with tasks via + standard mechanism such as sem_post, sigqueue, mq_send, etc. These all + call enter_critical_section and are assumed to be safe in the SMP case. + + But certain logic interacts with tasks in different ways. The only one + that comes to mind are wdogs. There is a tasking interface that to + manipulate wdogs, and a different interface in the timer interrupt + handling logic to manage wdog expirations. + + In the normal case, this is fine. Since the tasking level code calls + enter_critical_section, interrupts are disabled an no conflicts can + occur. But that may not be the case in the SMP case. Most + architectures do not permit disabling interrupts on other CPUs so + enter_critical_section must work differently: Locks are required to + protect code. + + So this change adds locking (via enter_critical section) to wdog + expiration logic for the the case if the SMP configuration + (2016-11-18). 7.19 2016-xx-xx Gregory Nutt -- GitLab From 8d9804d57ba5bf88f61b3221c98cf201f07b9991 Mon Sep 17 00:00:00 2001 From: "Paul A. Patience" Date: Fri, 18 Nov 2016 19:28:09 -0500 Subject: [PATCH 448/734] STM32: STM32F303xB and STM32F303xC chips have 4 ADCs --- arch/arm/src/stm32/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index abfdf71985..c0dc163d30 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -636,6 +636,7 @@ config ARCH_CHIP_STM32F303CB select STM32_STM32F303 select ARCH_HAVE_FPU select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 select STM32_HAVE_I2C2 select STM32_HAVE_SPI2 select STM32_HAVE_SPI3 @@ -651,6 +652,7 @@ config ARCH_CHIP_STM32F303CC select STM32_STM32F303 select ARCH_HAVE_FPU select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 select STM32_HAVE_I2C2 select STM32_HAVE_SPI2 select STM32_HAVE_SPI3 @@ -666,6 +668,7 @@ config ARCH_CHIP_STM32F303RB select STM32_STM32F303 select ARCH_HAVE_FPU select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 select STM32_HAVE_I2C2 select STM32_HAVE_SPI2 select STM32_HAVE_SPI3 @@ -683,6 +686,7 @@ config ARCH_CHIP_STM32F303RC select STM32_STM32F303 select ARCH_HAVE_FPU select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 select STM32_HAVE_I2C2 select STM32_HAVE_SPI2 select STM32_HAVE_SPI3 @@ -740,6 +744,7 @@ config ARCH_CHIP_STM32F303VB select STM32_STM32F303 select ARCH_HAVE_FPU select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 select STM32_HAVE_I2C2 select STM32_HAVE_SPI2 select STM32_HAVE_SPI3 @@ -757,6 +762,7 @@ config ARCH_CHIP_STM32F303VC select STM32_STM32F303 select ARCH_HAVE_FPU select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 select STM32_HAVE_I2C2 select STM32_HAVE_SPI2 select STM32_HAVE_SPI3 -- GitLab From c7ef82c546636daa4cc1b831019afb5ecec69f4e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Wolfgang=20Rei=C3=9Fnegger?= Date: Fri, 18 Nov 2016 16:27:08 -0800 Subject: [PATCH 449/734] SAM3/4: Add delay between setting and clearing the endpoint RESET bit in sam_ep_resume(). We need to add a delay between setting and clearing the endpoint reset bit in SAM_UDP_RSTEP. Without the delay the USB controller will (may?) not reset the endpoint. If the endpoint is not being reset, the Data Toggle (DTGLE) bit will not to be cleared which will cause the next transaction to fail if DTGLE is 1. If that happens the host will time-out and reset the bus. Adding this delay may also fix the USBMSC_STALL_RACEWAR in usbmsc_scsi.c, however this has not been verified yet. --- arch/arm/src/sam34/sam_udp.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/src/sam34/sam_udp.c b/arch/arm/src/sam34/sam_udp.c index 96a521d0ba..d2feca624d 100644 --- a/arch/arm/src/sam34/sam_udp.c +++ b/arch/arm/src/sam34/sam_udp.c @@ -2682,8 +2682,24 @@ static int sam_ep_resume(struct sam_ep_s *privep) /* Reset the endpoint FIFO */ sam_putreg(UDP_RSTEP(epno), SAM_UDP_RSTEP); + + /* + * We need to add a delay between setting and clearing the endpoint reset + * bit in SAM_UDP_RSTEP. Without the delay the USB controller will (may?) + * not reset the endpoint. + * + * If the endpoint is not being reset, the Data Toggle (DTGLE) bit will + * not to be cleared which will cause the next transaction to fail if + * DTGLE is 1. If that happens the host will time-out and reset the bus. + * + * Adding this delay may also fix the USBMSC_STALL_RACEWAR in + * usbmsc_scsi.c, however this has not been verified yet. + */ + + up_udelay(10); sam_putreg(0, SAM_UDP_RSTEP); + /* Copy any requests in the pending request queue to the working * request queue. */ -- GitLab From 9e349f4335932bd4b905f4a13f3554fdb9e25ce6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Wolfgang=20Rei=C3=9Fnegger?= Date: Fri, 18 Nov 2016 08:27:18 -0800 Subject: [PATCH 450/734] SAM3/4: Remove unused 'halted' flag in UDP driver. --- arch/arm/src/sam34/sam_udp.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/src/sam34/sam_udp.c b/arch/arm/src/sam34/sam_udp.c index d2feca624d..b33d982fd6 100644 --- a/arch/arm/src/sam34/sam_udp.c +++ b/arch/arm/src/sam34/sam_udp.c @@ -301,7 +301,6 @@ struct sam_ep_s volatile uint8_t epstate; /* State of the endpoint (see enum sam_epstate_e) */ uint8_t stalled:1; /* true: Endpoint is stalled */ uint8_t pending:1; /* true: IN Endpoint stall is pending */ - uint8_t halted:1; /* true: Endpoint feature halted */ uint8_t zlpneeded:1; /* Zero length packet needed at end of transfer */ uint8_t zlpsent:1; /* Zero length packet has been sent */ uint8_t txbusy:1; /* Write request queue is busy (recursion avoidance kludge) */ @@ -1547,7 +1546,6 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) { privep = &priv->eplist[epno]; - privep->halted = false; ret = sam_ep_resume(privep); if (ret < 0) @@ -1596,7 +1594,6 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) { privep = &priv->eplist[epno]; - privep->halted = true; ret = sam_ep_stall(privep); if (ret < 0) @@ -2561,7 +2558,6 @@ static void sam_ep_reset(struct sam_usbdev_s *priv, uint8_t epno) privep->epstate = UDP_EPSTATE_DISABLED; privep->stalled = false; privep->pending = false; - privep->halted = false; privep->zlpneeded = false; privep->zlpsent = false; privep->txbusy = false; @@ -3668,7 +3664,6 @@ static void sam_reset(struct sam_usbdev_s *priv) privep->stalled = false; privep->pending = false; - privep->halted = false; privep->zlpneeded = false; privep->zlpsent = false; privep->txbusy = false; -- GitLab From d135246a7d1b3e2705b51d3beef15545e450e6cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Wolfgang=20Rei=C3=9Fnegger?= Date: Fri, 18 Nov 2016 08:47:36 -0800 Subject: [PATCH 451/734] SAM3/4: Remove 'stalled' flag in UDP driver. The flag is not necessary. The state of the endpoint can be determined using 'epstate' instead. --- arch/arm/src/sam34/sam_udp.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/arch/arm/src/sam34/sam_udp.c b/arch/arm/src/sam34/sam_udp.c index b33d982fd6..ca4f0e29a8 100644 --- a/arch/arm/src/sam34/sam_udp.c +++ b/arch/arm/src/sam34/sam_udp.c @@ -299,7 +299,6 @@ struct sam_ep_s struct sam_rqhead_s reqq; /* Read/write request queue */ struct sam_rqhead_s pendq; /* Write requests pending stall sent */ volatile uint8_t epstate; /* State of the endpoint (see enum sam_epstate_e) */ - uint8_t stalled:1; /* true: Endpoint is stalled */ uint8_t pending:1; /* true: IN Endpoint stall is pending */ uint8_t zlpneeded:1; /* Zero length packet needed at end of transfer */ uint8_t zlpsent:1; /* Zero length packet has been sent */ @@ -819,7 +818,7 @@ static void sam_req_complete(struct sam_ep_s *privep, int16_t result) privreq->flink = NULL; privreq->req.callback(&privep->ep, &privreq->req); - /* Reset the endpoint state and restore the stalled indication */ + /* Reset the endpoint state */ privep->epstate = UDP_EPSTATE_IDLE; privep->zlpneeded = false; @@ -1403,7 +1402,6 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) /* Assume NOT stalled; no TX in progress */ - ep0->stalled = false; ep0->pending = false; ep0->epstate = UDP_EPSTATE_IDLE; @@ -1469,7 +1467,7 @@ static void sam_ep0_setup(struct sam_usbdev_s *priv) response.w = 0; /* Not stalled */ nbytes = 2; /* Response size: 2 bytes */ - if (privep->stalled) + if (privep->epstate == UDP_EPSTATE_STALLED) { /* Endpoint stalled */ @@ -2556,7 +2554,6 @@ static void sam_ep_reset(struct sam_usbdev_s *priv, uint8_t epno) /* Reset endpoint status */ privep->epstate = UDP_EPSTATE_DISABLED; - privep->stalled = false; privep->pending = false; privep->zlpneeded = false; privep->zlpsent = false; @@ -2629,7 +2626,6 @@ static int sam_ep_stall(struct sam_ep_s *privep) /* Put endpoint into stalled state */ privep->epstate = UDP_EPSTATE_STALLED; - privep->stalled = true; privep->pending = false; sam_csr_setbits(epno, UDPEP_CSR_FORCESTALL); @@ -2667,7 +2663,6 @@ static int sam_ep_resume(struct sam_ep_s *privep) /* Return endpoint to Idle state */ - privep->stalled = false; privep->pending = false; privep->epstate = UDP_EPSTATE_IDLE; @@ -3182,7 +3177,7 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { /* Check if the endpoint is stalled (or there is a stall pending) */ - if (privep->stalled || privep->pending) + if ((privep->epstate == UDP_EPSTATE_STALLED) || privep->pending) { /* Yes.. in this case, save the request in a special "pending" * queue. They will stay queuee until the stall is cleared. @@ -3662,7 +3657,6 @@ static void sam_reset(struct sam_usbdev_s *priv) /* Reset endpoint status */ - privep->stalled = false; privep->pending = false; privep->zlpneeded = false; privep->zlpsent = false; -- GitLab From 88539a7497e5c4880edffa0df2501a537ab1dd86 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Wolfgang=20Rei=C3=9Fnegger?= Date: Fri, 18 Nov 2016 16:57:24 -0800 Subject: [PATCH 452/734] USBMSC: Fix length of mode6 sense reply packet. --- drivers/usbdev/usbmsc_scsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usbdev/usbmsc_scsi.c b/drivers/usbdev/usbmsc_scsi.c index d088312ca9..30e06be071 100644 --- a/drivers/usbdev/usbmsc_scsi.c +++ b/drivers/usbdev/usbmsc_scsi.c @@ -827,7 +827,7 @@ static int inline usbmsc_cmdmodesense6(FAR struct usbmsc_dev_s *priv, { /* Store the mode data length and return the total message size */ - mph->mdlen = mdlen - 1; + mph->mdlen = mdlen + SCSIRESP_MODEPARAMETERHDR6_SIZEOF - 1; priv->nreqbytes = mdlen + SCSIRESP_MODEPARAMETERHDR6_SIZEOF; } } -- GitLab From 5d658a8915af55b4192f3855974bd7c5197c191b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Wolfgang=20Rei=C3=9Fnegger?= Date: Tue, 11 Oct 2016 09:36:03 -0700 Subject: [PATCH 453/734] configs/dk-tm4c129x: Typo fix. --- configs/dk-tm4c129x/README.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/dk-tm4c129x/README.txt b/configs/dk-tm4c129x/README.txt index 32e48d6e7e..138e69cd3e 100644 --- a/configs/dk-tm4c129x/README.txt +++ b/configs/dk-tm4c129x/README.txt @@ -449,7 +449,7 @@ f Application Configuration -> Network Utilities Timers ====== - Tiva timers may be enbled in 32-bit periodic mode using these settings. + Tiva timers may be enabled in 32-bit periodic mode using these settings. This settings enables the "upper half" timer driver: -- GitLab From b23c1f8817842d56b954ba6e169e5eb4f87c224a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Wolfgang=20Rei=C3=9Fnegger?= Date: Wed, 9 Nov 2016 19:04:01 -0800 Subject: [PATCH 454/734] Typo fix in sam_udp.c --- arch/arm/src/sam34/sam_udp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/sam34/sam_udp.c b/arch/arm/src/sam34/sam_udp.c index ca4f0e29a8..2cda6c107e 100644 --- a/arch/arm/src/sam34/sam_udp.c +++ b/arch/arm/src/sam34/sam_udp.c @@ -893,8 +893,8 @@ static void sam_req_wrsetup(struct sam_usbdev_s *priv, privep->epstate = UDP_EPSTATE_SENDING; /* Set TXPKTRDY to notify the USB hardware that there is TX data in the - * endpoint FIFO. We will be notified that the endpoint’s FIFO has been - * released by the USB device when TXCOMP in the endpoint’s UDPEP_CSRx + * endpoint FIFO. We will be notified that the endpoint's FIFO has been + * released by the USB device when TXCOMP in the endpoint's UDPEP_CSRx * register has been set. */ @@ -3180,7 +3180,7 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) if ((privep->epstate == UDP_EPSTATE_STALLED) || privep->pending) { /* Yes.. in this case, save the request in a special "pending" - * queue. They will stay queuee until the stall is cleared. + * queue. They will stay queued until the stall is cleared. */ uinfo("Pending stall clear\n"); -- GitLab From 0db99b8c89fa78baa44aa823f23945069bdbae6f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 19 Nov 2016 06:52:51 -0600 Subject: [PATCH 455/734] Trivial fix from review of last PR --- arch/arm/src/sam34/sam_udp.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/src/sam34/sam_udp.c b/arch/arm/src/sam34/sam_udp.c index 2cda6c107e..9e644c7631 100644 --- a/arch/arm/src/sam34/sam_udp.c +++ b/arch/arm/src/sam34/sam_udp.c @@ -2674,8 +2674,7 @@ static int sam_ep_resume(struct sam_ep_s *privep) sam_putreg(UDP_RSTEP(epno), SAM_UDP_RSTEP); - /* - * We need to add a delay between setting and clearing the endpoint reset + /* We need to add a delay between setting and clearing the endpoint reset * bit in SAM_UDP_RSTEP. Without the delay the USB controller will (may?) * not reset the endpoint. * -- GitLab From ceacacbc631f638949695c17d93bbe7354695f4f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 19 Nov 2016 07:30:01 -0600 Subject: [PATCH 456/734] vfork(): Fix a race condition in the SMP case. Existing logic depended on the fact that the child would not run until waitpid was called because the child had the same priority as the parent. BUT in the SMP case that is not true... the child may run immediately on a different CPU. --- sched/task/task_vfork.c | 40 ++++++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 18 deletions(-) diff --git a/sched/task/task_vfork.c b/sched/task/task_vfork.c index a427d7c000..284627cc9d 100644 --- a/sched/task/task_vfork.c +++ b/sched/task/task_vfork.c @@ -41,6 +41,7 @@ #include #include +#include #include #include #include @@ -396,36 +397,38 @@ pid_t task_vforkstart(FAR struct task_tcb_s *child) pid = (int)child->cmn.pid; + /* Eliminate a race condition by disabling pre-emption. The child task + * can be instantiated, but cannot run until we call waitpid(). This + * assures us that we cannot miss the the death-of-child signal (only + * needed in the SMP case). + */ + + sched_lock(); + /* Activate the task */ ret = task_activate((FAR struct tcb_s *)child); if (ret < OK) { task_vforkabort(child, -ret); + sched_unlock(); return ERROR; } - /* Since the child task has the same priority as the parent task, it is - * now ready to run, but has not yet ran. It is a requirement that - * the parent environment be stable while vfork runs; the child thread - * is still dependent on things in the parent thread... like the pointers - * into parent thread's stack which will still appear in the child's - * registers and environment. - * - * We do not have SIG_CHILD, so we have to do some silly things here. - * The simplest way to make sure that the child thread runs to completion - * is simply to yield here. Since the child can only do exit() or - * execv/l(), that should be all that is needed. + /* The child task has not yet ran because pre-emption is disabled. + * The child task has the same priority as the parent task, so that + * would be the case anyway. However, in the SMP case, the child + * thread may have already ran on another CPU. * - * Hmmm.. this is probably not sufficient. What if we are running - * SCHED_RR? What if the child thread is suspended and rescheduled - * after the parent thread again? + * It is a requirement that the parent environment be stable while + * vfork runs; the child thread is still dependent on things in the + * parent thread... like the pointers into parent thread's stack + * which will still appear in the child's registers and environment. */ - /* We can also exploit a bug in the execv() implementation: The PID - * of the task exec'ed by the child will not be the same as the PID of - * the child task. Therefore, waitpid() on the child task's PID will - * accomplish what we need to do. + /* Now wait for the child thread to exit before returning to the + * parent thread. NOTE that pre-emption will be re-enabled while + * we are waiting. */ rc = 0; @@ -440,6 +443,7 @@ pid_t task_vforkstart(FAR struct task_tcb_s *child) (void)waitpid(pid, &rc, 0); #endif + sched_unlock(); return pid; } -- GitLab From 5ca9128c381464a8c3263cc8809d42663357f83f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 19 Nov 2016 08:33:55 -0600 Subject: [PATCH 457/734] Update comments --- sched/task/task_vfork.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/sched/task/task_vfork.c b/sched/task/task_vfork.c index 284627cc9d..73246ac76e 100644 --- a/sched/task/task_vfork.c +++ b/sched/task/task_vfork.c @@ -417,18 +417,19 @@ pid_t task_vforkstart(FAR struct task_tcb_s *child) /* The child task has not yet ran because pre-emption is disabled. * The child task has the same priority as the parent task, so that - * would be the case anyway. However, in the SMP case, the child - * thread may have already ran on another CPU. + * would typically be the case anyway. However, in the SMP + * configuration, the child thread might have already ran on + * another CPU if pre-emption were not disabled. * * It is a requirement that the parent environment be stable while * vfork runs; the child thread is still dependent on things in the * parent thread... like the pointers into parent thread's stack * which will still appear in the child's registers and environment. - */ - - /* Now wait for the child thread to exit before returning to the - * parent thread. NOTE that pre-emption will be re-enabled while - * we are waiting. + * + * We assure that by waiting for the child thread to exit before + * returning to the parent thread. NOTE that pre-emption will be + * re-enabled while we are waiting, giving the child thread the + * opportunity to run. */ rc = 0; -- GitLab From 0804286ad3196e2f24a8ae42520921478b748c40 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 19 Nov 2016 09:20:01 -0600 Subject: [PATCH 458/734] arch/: Add option to use low-priority work queue to all Ethernet drivers in arch that support CONFIG_NET_NOINTS. --- arch/arm/src/kinetis/Kconfig | 19 ++++++++++++++ arch/arm/src/kinetis/kinetis_enet.c | 32 ++++++++++++++++-------- arch/arm/src/lpc17xx/Kconfig | 20 +++++++++++++++ arch/arm/src/lpc17xx/lpc17_ethernet.c | 36 ++++++++++++++++++--------- arch/arm/src/lpc43xx/Kconfig | 23 +++++++++++++++-- arch/arm/src/lpc43xx/lpc43_ethernet.c | 32 ++++++++++++++++-------- arch/arm/src/sam34/Kconfig | 33 ++++++++++++++++++------ arch/arm/src/sam34/sam_emac.c | 32 ++++++++++++++++-------- arch/arm/src/sama5/Kconfig | 32 +++++++++++++++++------- arch/arm/src/sama5/sam_emacb.c | 32 ++++++++++++++++-------- arch/arm/src/samv7/Kconfig | 20 +++++++++++++++ arch/arm/src/samv7/sam_emac.c | 32 ++++++++++++++++-------- arch/arm/src/samv7/sam_ethernet.c | 20 --------------- arch/arm/src/stm32/Kconfig | 25 ++++++++++++++++--- arch/arm/src/stm32/stm32_eth.c | 32 ++++++++++++++++-------- arch/arm/src/stm32f7/Kconfig | 27 +++++++++++++++++--- arch/arm/src/stm32f7/stm32_ethernet.c | 32 ++++++++++++++++-------- arch/arm/src/tiva/Kconfig | 19 ++++++++++++++ arch/arm/src/tiva/tm4c_ethernet.c | 32 ++++++++++++++++-------- drivers/net/Kconfig | 16 +++++++++--- net/Kconfig | 4 ++- 21 files changed, 407 insertions(+), 143 deletions(-) diff --git a/arch/arm/src/kinetis/Kconfig b/arch/arm/src/kinetis/Kconfig index 17923818b5..cf781ade5e 100644 --- a/arch/arm/src/kinetis/Kconfig +++ b/arch/arm/src/kinetis/Kconfig @@ -629,6 +629,25 @@ config KINETIS_ENET_NORXER If selected, then the MII/RMII RXER output will be configured as a GPIO and pulled low. +choice + prompt "Work queue" + default KINETIS_EMAC_LPWORK if SCHED_LPWORK + default KINETIS_EMAC_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + depends on SCHED_WORKQUEUE + ---help--- + Work queue support is required to use the Ethernet driver. If the + low priority work queue is available, then it should be used by the + driver. + +config KINETIS_EMAC_HPWORK + bool "High priority" + depends on SCHED_HPWORK + +config KINETIS_EMAC_LPWORK + bool "Low priority" + depends on SCHED_LPWORK + +endchoice # Work queue endmenu # Kinetis Ethernet Configuration menu "Kinetis SDHC Configuration" diff --git a/arch/arm/src/kinetis/kinetis_enet.c b/arch/arm/src/kinetis/kinetis_enet.c index dc0be25e16..a546103d36 100644 --- a/arch/arm/src/kinetis/kinetis_enet.c +++ b/arch/arm/src/kinetis/kinetis_enet.c @@ -80,12 +80,24 @@ * Pre-processor Definitions ****************************************************************************/ -/* If processing is not done at the interrupt level, then high priority - * work queue support is required. +/* If processing is not done at the interrupt level, then work queue support + * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_HPWORK) -# error High priority work queue support is required +#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required +#endif + +/* Select work queue */ + +#if defined(CONFIG_SCHED_WORKQUEUE) +# if defined(CONFIG_KINETIS_EMAC_HPWORK) +# define ETHWORK HPWORK +# elif defined(CONFIG_KINETIS_EMAC_LPWORK) +# define ETHWORK LPWORK +# else +# error Neither CONFIG_KINETIS_EMAC_HPWORK nor CONFIG_KINETIS_EMAC_LPWORK defined +# endif #endif /* CONFIG_KINETIS_ENETNETHIFS determines the number of physical interfaces @@ -974,11 +986,11 @@ static int kinetis_interrupt(int irq, FAR void *context) /* Cancel any pending poll work */ - work_cancel(HPWORK, &priv->work); + work_cancel(ETHWORK, &priv->work); /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->work, kinetis_interrupt_work, priv, 0); + work_queue(ETHWORK, &priv->work, kinetis_interrupt_work, priv, 0); #else /* Process the interrupt now */ @@ -1093,11 +1105,11 @@ static void kinetis_txtimeout_expiry(int argc, uint32_t arg, ...) * on work that has already been started. */ - work_cancel(HPWORK, &priv->work); + work_cancel(ETHWORK, &priv->work); /* Schedule to perform the TX timeout processing on the worker thread. */ - work_queue(HPWORK, &priv->work, kinetis_txtimeout_work, priv, 0); + work_queue(ETHWORK, &priv->work, kinetis_txtimeout_work, priv, 0); #else /* Process the timeout now */ @@ -1206,7 +1218,7 @@ static void kinetis_polltimer_expiry(int argc, uint32_t arg, ...) { /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->work, kinetis_poll_work, priv, 0); + work_queue(ETHWORK, &priv->work, kinetis_poll_work, priv, 0); } else { @@ -1513,7 +1525,7 @@ static int kinetis_txavail(struct net_driver_s *dev) { /* Schedule to serialize the poll on the worker thread. */ - work_queue(HPWORK, &priv->work, kinetis_txavail_work, priv, 0); + work_queue(ETHWORK, &priv->work, kinetis_txavail_work, priv, 0); } #else diff --git a/arch/arm/src/lpc17xx/Kconfig b/arch/arm/src/lpc17xx/Kconfig index 5038000d86..7691b48a0e 100644 --- a/arch/arm/src/lpc17xx/Kconfig +++ b/arch/arm/src/lpc17xx/Kconfig @@ -724,6 +724,26 @@ config LPC17_MULTICAST ---help--- Enable receipt of multicast (and unicast) frames. Automatically set if NET_IGMP is selected. + +choice + prompt "Work queue" + default LPC17_ETHERNET_LPWORK if SCHED_LPWORK + default LPC17_ETHERNET_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + depends on SCHED_WORKQUEUE + ---help--- + Work queue support is required to use the Ethernet driver. If the + low priority work queue is available, then it should be used by the + driver. + +config LPC17_ETHERNET_HPWORK + bool "High priority" + depends on SCHED_HPWORK + +config LPC17_ETHERNET_LPWORK + bool "Low priority" + depends on SCHED_LPWORK + +endchoice # Work queue endmenu menu "LCD device driver options" diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.c b/arch/arm/src/lpc17xx/lpc17_ethernet.c index 1373050682..d5ff009fd6 100644 --- a/arch/arm/src/lpc17xx/lpc17_ethernet.c +++ b/arch/arm/src/lpc17xx/lpc17_ethernet.c @@ -83,12 +83,24 @@ * Pre-processor Definitions ****************************************************************************/ /* Configuration ************************************************************/ -/* If processing is not done at the interrupt level, then high priority - * work queue support is required. +/* If processing is not done at the interrupt level, then work queue support + * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_HPWORK) -# error High priority work queue support is required +#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required +#endif + +/* Select work queue */ + +#if defined(CONFIG_SCHED_WORKQUEUE) +# if defined(CONFIG_LPC17_ETHERNET_HPWORK) +# define ETHWORK HPWORK +# elif defined(CONFIG_LPC17_ETHERNET_LPWORK) +# define ETHWORK LPWORK +# else +# error Neither CONFIG_LPC17_ETHERNET_HPWORK nor CONFIG_LPC17_ETHERNET_LPWORK defined +# endif #endif /* CONFIG_LPC17_NINTERFACES determines the number of physical interfaces @@ -1259,11 +1271,11 @@ static int lpc17_interrupt(int irq, void *context) /* Cancel any pending RX done work */ - work_cancel(HPWORK, &priv->lp_rxwork); + work_cancel(ETHWORK, &priv->lp_rxwork); /* Schedule RX-related work to be performed on the work thread */ - work_queue(HPWORK, &priv->lp_rxwork, (worker_t)lpc17_rxdone_work, + work_queue(ETHWORK, &priv->lp_rxwork, (worker_t)lpc17_rxdone_work, priv, 0); #else /* CONFIG_NET_NOINTS */ @@ -1323,7 +1335,7 @@ static int lpc17_interrupt(int irq, void *context) * to avoid race conditions with the TX timeout work) */ - work_cancel(HPWORK, &priv->lp_txwork); + work_cancel(ETHWORK, &priv->lp_txwork); /* Then make sure that the TX poll timer is running (if it is * already running, the following would restart it). This is @@ -1336,7 +1348,7 @@ static int lpc17_interrupt(int irq, void *context) /* Schedule TX-related work to be performed on the work thread */ - work_queue(HPWORK, &priv->lp_txwork, (worker_t)lpc17_txdone_work, + work_queue(ETHWORK, &priv->lp_txwork, (worker_t)lpc17_txdone_work, priv, 0); #else /* CONFIG_NET_NOINTS */ @@ -1468,7 +1480,7 @@ static void lpc17_txtimeout_expiry(int argc, uint32_t arg, ...) { /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->lp_txwork, lpc17_txtimeout_work, priv, 0); + work_queue(ETHWORK, &priv->lp_txwork, lpc17_txtimeout_work, priv, 0); } #else @@ -1526,7 +1538,7 @@ static void lpc17_poll_process(FAR struct lpc17_driver_s *priv) if (considx != prodidx) { #ifdef CONFIG_NET_NOINTS - work_queue(HPWORK, &priv->lp_rxwork, (worker_t)lpc17_rxdone_work, + work_queue(ETHWORK, &priv->lp_rxwork, (worker_t)lpc17_rxdone_work, priv, 0); #else /* CONFIG_NET_NOINTS */ @@ -1606,7 +1618,7 @@ static void lpc17_poll_expiry(int argc, uint32_t arg, ...) { /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->lp_pollwork, lpc17_poll_work, priv, 0); + work_queue(ETHWORK, &priv->lp_pollwork, lpc17_poll_work, priv, 0); } else { @@ -2013,7 +2025,7 @@ static int lpc17_txavail(struct net_driver_s *dev) { /* Schedule to serialize the poll on the worker thread. */ - work_queue(HPWORK, &priv->lp_pollwork, lpc17_txavail_work, priv, 0); + work_queue(ETHWORK, &priv->lp_pollwork, lpc17_txavail_work, priv, 0); } #else diff --git a/arch/arm/src/lpc43xx/Kconfig b/arch/arm/src/lpc43xx/Kconfig index 7c9a89c49d..c063fd86c7 100644 --- a/arch/arm/src/lpc43xx/Kconfig +++ b/arch/arm/src/lpc43xx/Kconfig @@ -485,8 +485,8 @@ endif # LCP43_EXTSDRAM3 endmenu # External Memory Configuration -if LPC43_ETHERNET menu "Ethernet MAC configuration" + depends on LPC43_ETHERNET config LPC43_PHYADDR int "PHY address" @@ -619,6 +619,26 @@ config LPC43_RMII bool default y if !LPC43_MII +choice + prompt "Work queue" + default LPC43_ETHERNET_LPWORK if SCHED_LPWORK + default LPC43_ETHERNET_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + depends on SCHED_WORKQUEUE + ---help--- + Work queue support is required to use the Ethernet driver. If the + low priority work queue is available, then it should be used by the + driver. + +config LPC43_ETHERNET_HPWORK + bool "High priority" + depends on SCHED_HPWORK + +config LPC43_ETHERNET_LPWORK + bool "Low priority" + depends on SCHED_LPWORK + +endchoice # Work queue + config LPC43_ETHERNET_REGDEBUG bool "Register-Level Debug" default n @@ -627,7 +647,6 @@ config LPC43_ETHERNET_REGDEBUG Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET_INFO. endmenu # Ethernet MAC configuration -endif # LPC43_ETHERNET menu "RS-485 Configuration" if LPC43_USART0 diff --git a/arch/arm/src/lpc43xx/lpc43_ethernet.c b/arch/arm/src/lpc43xx/lpc43_ethernet.c index 086dd0b8f3..c96f1a7551 100644 --- a/arch/arm/src/lpc43xx/lpc43_ethernet.c +++ b/arch/arm/src/lpc43xx/lpc43_ethernet.c @@ -83,12 +83,24 @@ ****************************************************************************/ /* Configuration ************************************************************/ -/* If processing is not done at the interrupt level, then high priority - * work queue support is required. +/* If processing is not done at the interrupt level, then work queue support + * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_HPWORK) -# error High priority work queue support is required +#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required +#endif + +/* Select work queue */ + +#if defined(CONFIG_SCHED_WORKQUEUE) +# if defined(CONFIG_LPC43_ETHERNET_HPWORK) +# define ETHWORK HPWORK +# elif defined(CONFIG_LPC43_ETHERNET_LPWORK) +# define ETHWORK LPWORK +# else +# error Neither CONFIG_LPC43_ETHERNET_HPWORK nor CONFIG_LPC43_ETHERNET_LPWORK defined +# endif #endif #ifndef CONFIG_LPC43_PHYADDR @@ -2075,11 +2087,11 @@ static int lpc43_interrupt(int irq, FAR void *context) /* Cancel any pending poll work */ - work_cancel(HPWORK, &priv->work); + work_cancel(ETHWORK, &priv->work); /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->work, lpc43_interrupt_work, priv, 0); + work_queue(ETHWORK, &priv->work, lpc43_interrupt_work, priv, 0); } #else @@ -2195,11 +2207,11 @@ static void lpc43_txtimeout_expiry(int argc, uint32_t arg, ...) * on work that has already been started. */ - work_cancel(HPWORK, &priv->work); + work_cancel(ETHWORK, &priv->work); /* Schedule to perform the TX timeout processing on the worker thread. */ - work_queue(HPWORK, &priv->work, lpc43_txtimeout_work, priv, 0); + work_queue(ETHWORK, &priv->work, lpc43_txtimeout_work, priv, 0); #else /* Process the timeout now */ @@ -2339,7 +2351,7 @@ static void lpc43_poll_expiry(int argc, uint32_t arg, ...) { /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->work, lpc43_poll_work, priv, 0); + work_queue(ETHWORK, &priv->work, lpc43_poll_work, priv, 0); } else { @@ -2556,7 +2568,7 @@ static int lpc43_txavail(struct net_driver_s *dev) { /* Schedule to serialize the poll on the worker thread. */ - work_queue(HPWORK, &priv->work, lpc43_txavail_work, priv, 0); + work_queue(ETHWORK, &priv->work, lpc43_txavail_work, priv, 0); } #else diff --git a/arch/arm/src/sam34/Kconfig b/arch/arm/src/sam34/Kconfig index 1f1f423e85..df13714792 100644 --- a/arch/arm/src/sam34/Kconfig +++ b/arch/arm/src/sam34/Kconfig @@ -1136,9 +1136,8 @@ config SAM34_SPI_REGDEBUG endmenu # AT91SAM3/4 SPI device driver options endif # SAM34_SPI0 || SAM34_SPI1 -if SAM34_EMAC - menu "AT91SAM3/4 EMAC device driver options" + depends on SAM34_EMAC config SAM34_EMAC_NRXBUFFERS int "Number of RX buffers" @@ -1332,6 +1331,30 @@ config SAM34_EMAC_PHYSR_100FD This must be provided if SAM34_EMAC_AUTONEG is defined. This is the value under the bit mask that represents the 100Mbps, full duplex setting. +config SAM34_EMAC_ISETH0 + bool + default y + +choice + prompt "Work queue" + default SAM34_EMAC_LPWORK if SCHED_LPWORK + default SAM34_EMAC_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + depends on SCHED_WORKQUEUE + ---help--- + Work queue support is required to use the Ethernet driver. If the + low priority work queue is available, then it should be used by the + driver. + +config SAM34_EMAC_HPWORK + bool "High priority" + depends on SCHED_HPWORK + +config SAM34_EMAC_LPWORK + bool "Low priority" + depends on SCHED_LPWORK + +endchoice # Work queue + config SAM34_EMAC_REGDEBUG bool "Register-Level Debug" default n @@ -1339,13 +1362,7 @@ config SAM34_EMAC_REGDEBUG ---help--- Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET_INFO. -config SAM34_EMAC_ISETH0 - bool - default y if !SAM34_EMAC || !SAM34_GMAC_ISETH0 - default n if SAM34_EMAC && SAM34_GMAC_ISETH0 - endmenu # EMAC device driver options -endif # SAM34_EMAC if SAM34_HSMCI menu "AT91SAM3/4 HSMCI device driver options" diff --git a/arch/arm/src/sam34/sam_emac.c b/arch/arm/src/sam34/sam_emac.c index a7a9bc2141..15e7b1b4ba 100644 --- a/arch/arm/src/sam34/sam_emac.c +++ b/arch/arm/src/sam34/sam_emac.c @@ -97,12 +97,24 @@ ****************************************************************************/ /* Configuration ************************************************************/ -/* If processing is not done at the interrupt level, then high priority - * work queue support is required. +/* If processing is not done at the interrupt level, then work queue support + * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_HPWORK) -# error High priority work queue support is required +#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required +#endif + +/* Select work queue */ + +#if defined(CONFIG_SCHED_WORKQUEUE) +# if defined(CONFIG_SAM34_EMAC_HPWORK) +# define ETHWORK HPWORK +# elif defined(CONFIG_SAM34_EMAC_LPWORK) +# define ETHWORK LPWORK +# else +# error Neither CONFIG_SAM34_EMAC_HPWORK nor CONFIG_SAM34_EMAC_LPWORK defined +# endif #endif /* Number of buffer for RX */ @@ -1690,11 +1702,11 @@ static int sam_emac_interrupt(int irq, void *context) /* Cancel any pending poll work */ - work_cancel(HPWORK, &priv->work); + work_cancel(ETHWORK, &priv->work); /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->work, sam_interrupt_work, priv, 0); + work_queue(ETHWORK, &priv->work, sam_interrupt_work, priv, 0); #else /* Process the interrupt now */ @@ -1807,11 +1819,11 @@ static void sam_txtimeout_expiry(int argc, uint32_t arg, ...) * on work that has already been started. */ - work_cancel(HPWORK, &priv->work); + work_cancel(ETHWORK, &priv->work); /* Schedule to perform the TX timeout processing on the worker thread. */ - work_queue(HPWORK, &priv->work, sam_txtimeout_work, priv, 0); + work_queue(ETHWORK, &priv->work, sam_txtimeout_work, priv, 0); #else /* Process the timeout now */ @@ -1918,7 +1930,7 @@ static void sam_poll_expiry(int argc, uint32_t arg, ...) { /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->work, sam_poll_work, priv, 0); + work_queue(ETHWORK, &priv->work, sam_poll_work, priv, 0); } else { @@ -2155,7 +2167,7 @@ static int sam_txavail(struct net_driver_s *dev) { /* Schedule to serialize the poll on the worker thread. */ - work_queue(HPWORK, &priv->work, sam_txavail_work, priv, 0); + work_queue(ETHWORK, &priv->work, sam_txavail_work, priv, 0); } #else diff --git a/arch/arm/src/sama5/Kconfig b/arch/arm/src/sama5/Kconfig index 121ee991ec..1400aea5c9 100644 --- a/arch/arm/src/sama5/Kconfig +++ b/arch/arm/src/sama5/Kconfig @@ -1685,13 +1685,11 @@ config SAMA5_EMACA_REGDEBUG endmenu # EMAC device driver options endif # SAMA5_EMACA -if SAMA5_EMACB - menu "EMAC device driver options" - -if SAMA5_EMAC0 + depends on SAMA5_EMACB menu "EMAC0 device driver options" + depends on SAMA5_EMAC0 config SAMA5_EMAC0_NRXBUFFERS int "Number of RX buffers" @@ -1871,11 +1869,9 @@ config SAMA5_EMAC0_PHYSR_FULLDUPLEX endif # !SAMA5_EMAC0_PHYSR_ALTCONFIG endif # SAMA5_EMAC0_AUTONEG endmenu # EMAC0 device driver options -endif # SAMA5_EMAC0 - -if SAMA5_EMAC1 menu "EMAC1 device driver options" + depends on SAMA5_EMAC1 config SAMA5_EMAC1_NRXBUFFERS int "Number of RX buffers" @@ -2055,7 +2051,6 @@ config SAMA5_EMAC1_PHYSR_FULLDUPLEX endif # !SAMA5_EMAC1_PHYSR_ALTCONFIG endif # SAMA5_EMAC1_AUTONEG endmenu # EMAC1 device driver options -endif # SAMA5_EMAC1 # These apply to both EMAC0 and EMAC1 @@ -2073,6 +2068,26 @@ config SAMA5_EMACB_NBC ---help--- Select to disable receipt of broadcast packets. +choice + prompt "Work queue" + default SAMA5_EMACB_LPWORK if SCHED_LPWORK + default SAMA5_EMACB_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + depends on SCHED_WORKQUEUE + ---help--- + Work queue support is required to use the Ethernet driver. If the + low priority work queue is available, then it should be used by the + driver. + +config SAMA5_EMACB_HPWORK + bool "High priority" + depends on SCHED_HPWORK + +config SAMA5_EMACB_LPWORK + bool "Low priority" + depends on SCHED_LPWORK + +endchoice # Work queue + config SAMA5_EMACB_DEBUG bool "Force EMAC0/1 DEBUG" default n @@ -2092,7 +2107,6 @@ config SAMA5_EMACB_REGDEBUG Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET_INFO. endmenu # EMAC device driver options -endif # SAMA5_EMACB if SAMA5_EMACA || SAMA5_EMAC0 || SAMA5_EMAC1 || SAMA5_GMAC choice diff --git a/arch/arm/src/sama5/sam_emacb.c b/arch/arm/src/sama5/sam_emacb.c index ba118484e1..3d9f282ce9 100644 --- a/arch/arm/src/sama5/sam_emacb.c +++ b/arch/arm/src/sama5/sam_emacb.c @@ -113,12 +113,24 @@ ****************************************************************************/ /* Configuration ************************************************************/ -/* If processing is not done at the interrupt level, then high priority - * work queue support is required. +/* If processing is not done at the interrupt level, then work queue support + * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_HPWORK) -# error High priority work queue support is required +#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required +#endif + +/* Select work queue */ + +#if defined(CONFIG_SCHED_WORKQUEUE) +# if defined(CONFIG_SAMA5_EMACB_HPWORK) +# define ETHWORK HPWORK +# elif defined(CONFIG_SAMA5_EMACB_LPWORK) +# define ETHWORK LPWORK +# else +# error Neither CONFIG_SAMA5_EMACB_HPWORK nor CONFIG_SAMA5_EMACB_LPWORK defined +# endif #endif /* EMAC0 Configuration ******************************************************/ @@ -2098,11 +2110,11 @@ static int sam_emac_interrupt(struct sam_emac_s *priv) /* Cancel any pending poll work */ - work_cancel(HPWORK, &priv->work); + work_cancel(ETHWORK, &priv->work); /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->work, sam_interrupt_work, priv, 0); + work_queue(ETHWORK, &priv->work, sam_interrupt_work, priv, 0); #else /* Process the interrupt now */ @@ -2244,11 +2256,11 @@ static void sam_txtimeout_expiry(int argc, uint32_t arg, ...) * on work that has already been started. */ - work_cancel(HPWORK, &priv->work); + work_cancel(ETHWORK, &priv->work); /* Schedule to perform the TX timeout processing on the worker thread. */ - work_queue(HPWORK, &priv->work, sam_txtimeout_work, priv, 0); + work_queue(ETHWORK, &priv->work, sam_txtimeout_work, priv, 0); #else /* Process the timeout now */ @@ -2355,7 +2367,7 @@ static void sam_poll_expiry(int argc, uint32_t arg, ...) { /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->work, sam_poll_work, priv, 0); + work_queue(ETHWORK, &priv->work, sam_poll_work, priv, 0); } else { @@ -2600,7 +2612,7 @@ static int sam_txavail(struct net_driver_s *dev) { /* Schedule to serialize the poll on the worker thread. */ - work_queue(HPWORK, &priv->work, sam_txavail_work, priv, 0); + work_queue(ETHWORK, &priv->work, sam_txavail_work, priv, 0); } #else diff --git a/arch/arm/src/samv7/Kconfig b/arch/arm/src/samv7/Kconfig index fc4f513507..9a79ec5428 100644 --- a/arch/arm/src/samv7/Kconfig +++ b/arch/arm/src/samv7/Kconfig @@ -1998,6 +1998,26 @@ config SAMV7_EMAC_NBC ---help--- Select to disable receipt of broadcast packets. +choice + prompt "Work queue" + default SAMV7_EMAC_LPWORK if SCHED_LPWORK + default SAMV7_EMAC_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + depends on SCHED_WORKQUEUE + ---help--- + Work queue support is required to use the Ethernet driver. If the + low priority work queue is available, then it should be used by the + driver. + +config SAMV7_EMAC_HPWORK + bool "High priority" + depends on SCHED_HPWORK + +config SAMV7_EMAC_LPWORK + bool "Low priority" + depends on SCHED_LPWORK + +endchoice # Work queue + config SAMV7_EMAC_DEBUG bool "Force EMAC0/1 DEBUG" default n diff --git a/arch/arm/src/samv7/sam_emac.c b/arch/arm/src/samv7/sam_emac.c index c246140138..2eefdcefa7 100644 --- a/arch/arm/src/samv7/sam_emac.c +++ b/arch/arm/src/samv7/sam_emac.c @@ -103,12 +103,24 @@ ****************************************************************************/ /* Configuration ************************************************************/ -/* If processing is not done at the interrupt level, then high priority - * work queue support is required. +/* If processing is not done at the interrupt level, then work queue support + * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_HPWORK) -# error High priority work queue support is required +#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required +#endif + +/* Select work queue */ + +#if defined(CONFIG_SCHED_WORKQUEUE) +# if defined(CONFIG_SAMV7_EMAC_HPWORK) +# define ETHWORK HPWORK +# elif defined(CONFIG_SAMV7_EMAC_LPWORK) +# define ETHWORK LPWORK +# else +# error Neither CONFIG_SAMV7_EMAC_HPWORK nor CONFIG_SAMV7_EMAC_LPWORK defined +# endif #endif /* EMAC0 Configuration ******************************************************/ @@ -2544,11 +2556,11 @@ static int sam_emac_interrupt(struct sam_emac_s *priv) /* Cancel any pending poll work */ - work_cancel(HPWORK, &priv->work); + work_cancel(ETHWORK, &priv->work); /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->work, sam_interrupt_work, priv, 0); + work_queue(ETHWORK, &priv->work, sam_interrupt_work, priv, 0); #else /* Process the interrupt now */ @@ -2691,11 +2703,11 @@ static void sam_txtimeout_expiry(int argc, uint32_t arg, ...) * on work that has already been started. */ - work_cancel(HPWORK, &priv->work); + work_cancel(ETHWORK, &priv->work); /* Schedule to perform the TX timeout processing on the worker thread. */ - work_queue(HPWORK, &priv->work, sam_txtimeout_work, priv, 0); + work_queue(ETHWORK, &priv->work, sam_txtimeout_work, priv, 0); #else /* Process the timeout now */ @@ -2802,7 +2814,7 @@ static void sam_poll_expiry(int argc, uint32_t arg, ...) { /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->work, sam_poll_work, priv, 0); + work_queue(ETHWORK, &priv->work, sam_poll_work, priv, 0); } else { @@ -3050,7 +3062,7 @@ static int sam_txavail(struct net_driver_s *dev) { /* Schedule to serialize the poll on the worker thread. */ - work_queue(HPWORK, &priv->work, sam_txavail_work, priv, 0); + work_queue(ETHWORK, &priv->work, sam_txavail_work, priv, 0); } #else diff --git a/arch/arm/src/samv7/sam_ethernet.c b/arch/arm/src/samv7/sam_ethernet.c index 0137b16115..847099fb92 100644 --- a/arch/arm/src/samv7/sam_ethernet.c +++ b/arch/arm/src/samv7/sam_ethernet.c @@ -44,26 +44,6 @@ #ifdef CONFIG_NET -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index c0dc163d30..57165d8ab0 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -6146,8 +6146,8 @@ config RTC_HSECLOCK endchoice -if STM32_ETHMAC menu "Ethernet MAC configuration" + depends on STM32_ETHMAC config STM32_PHYADDR int "PHY address" @@ -6351,6 +6351,26 @@ config STM32_RMII_EXTCLK endchoice +choice + prompt "Work queue" + default STM32_ETHMAC_LPWORK if SCHED_LPWORK + default STM32_ETHMAC_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + depends on SCHED_WORKQUEUE + ---help--- + Work queue support is required to use the Ethernet driver. If the + low priority work queue is available, then it should be used by the + driver. + +config STM32_ETHMAC_HPWORK + bool "High priority" + depends on SCHED_HPWORK + +config STM32_ETHMAC_LPWORK + bool "Low priority" + depends on SCHED_LPWORK + +endchoice # Work queue + config STM32_ETHMAC_REGDEBUG bool "Register-Level Debug" default n @@ -6358,8 +6378,7 @@ config STM32_ETHMAC_REGDEBUG ---help--- Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. -endmenu -endif +endmenu # Ethernet MAC configuration menu "USB FS Host Configuration" diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/stm32/stm32_eth.c index abf911f7ac..635940ac95 100644 --- a/arch/arm/src/stm32/stm32_eth.c +++ b/arch/arm/src/stm32/stm32_eth.c @@ -93,12 +93,24 @@ # error "Logic to support multiple Ethernet interfaces is incomplete" #endif -/* If processing is not done at the interrupt level, then high priority - * work queue support is required. +/* If processing is not done at the interrupt level, then work queue support + * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_HPWORK) -# error High priority work queue support is required +#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required +#endif + +/* Select work queue */ + +#if defined(CONFIG_SCHED_WORKQUEUE) +# if defined(CONFIG_STM32_ETHMAC_HPWORK) +# define ETHWORK HPWORK +# elif defined(CONFIG_STM32_ETHMAC_LPWORK) +# define ETHWORK LPWORK +# else +# error Neither CONFIG_STM32_ETHMAC_HPWORK nor CONFIG_STM32_ETHMAC_LPWORK defined +# endif #endif #if !defined(CONFIG_STM32_SYSCFG) && !defined(CONFIG_STM32_CONNECTIVITYLINE) @@ -2139,11 +2151,11 @@ static int stm32_interrupt(int irq, FAR void *context) /* Cancel any pending poll work */ - work_cancel(HPWORK, &priv->work); + work_cancel(ETHWORK, &priv->work); /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->work, stm32_interrupt_work, priv, 0); + work_queue(ETHWORK, &priv->work, stm32_interrupt_work, priv, 0); } #else @@ -2259,11 +2271,11 @@ static void stm32_txtimeout_expiry(int argc, uint32_t arg, ...) * on work that has already been started. */ - work_cancel(HPWORK, &priv->work); + work_cancel(ETHWORK, &priv->work); /* Schedule to perform the TX timeout processing on the worker thread. */ - work_queue(HPWORK, &priv->work, stm32_txtimeout_work, priv, 0); + work_queue(ETHWORK, &priv->work, stm32_txtimeout_work, priv, 0); #else /* Process the timeout now */ @@ -2403,7 +2415,7 @@ static void stm32_poll_expiry(int argc, uint32_t arg, ...) { /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->work, stm32_poll_work, priv, 0); + work_queue(ETHWORK, &priv->work, stm32_poll_work, priv, 0); } else { @@ -2618,7 +2630,7 @@ static int stm32_txavail(struct net_driver_s *dev) { /* Schedule to serialize the poll on the worker thread. */ - work_queue(HPWORK, &priv->work, stm32_txavail_work, priv, 0); + work_queue(ETHWORK, &priv->work, stm32_txavail_work, priv, 0); } #else diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index ced8f62ca3..1723b9dad0 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -4436,8 +4436,8 @@ config STM32F7_ADC3_DMA endmenu # "ADC Configuration" -if STM32F7_ETHMAC menu "Ethernet MAC configuration" + depends on STM32F7_ETHMAC config STM32F7_PHYADDR int "PHY address" @@ -4619,7 +4619,27 @@ config STM32F7_RMII_EXTCLK ---help--- Clocking is provided by external logic. -endchoice +endchoice # RMII clock configuration + +choice + prompt "Work queue" + default STM32F7_ETHMAC_LPWORK if SCHED_LPWORK + default STM32F7_ETHMAC_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + depends on SCHED_WORKQUEUE + ---help--- + Work queue support is required to use the Ethernet driver. If the + low priority work queue is available, then it should be used by the + driver. + +config STM32F7_ETHMAC_HPWORK + bool "High priority" + depends on SCHED_HPWORK + +config STM32F7_ETHMAC_LPWORK + bool "Low priority" + depends on SCHED_LPWORK + +endchoice # Work queue config STM32F7_ETHMAC_REGDEBUG bool "Register-Level Debug" @@ -4628,6 +4648,5 @@ config STM32F7_ETHMAC_REGDEBUG ---help--- Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. -endmenu -endif # STM32F7_ETHMAC +endmenu # Ethernet MAC configuration endif # ARCH_CHIP_STM32F7 diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c index 0d4485ac26..eccf15b348 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.c +++ b/arch/arm/src/stm32f7/stm32_ethernet.c @@ -94,12 +94,24 @@ # error "Logic to support multiple Ethernet interfaces is incomplete" #endif -/* If processing is not done at the interrupt level, then high priority - * work queue support is required. +/* If processing is not done at the interrupt level, then work queue support + * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_HPWORK) -# error High priority work queue support is required +#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required +#endif + +/* Select work queue */ + +#if defined(CONFIG_SCHED_WORKQUEUE) +# if defined(CONFIG_STM32F7_ETHMAC_HPWORK) +# define ETHWORK HPWORK +# elif defined(CONFIG_STM32F7_ETHMAC_LPWORK) +# define ETHWORK LPWORK +# else +# error Neither CONFIG_STM32F7_ETHMAC_HPWORK nor CONFIG_STM32F7_ETHMAC_LPWORK defined +# endif #endif #ifndef CONFIG_STM32F7_PHYADDR @@ -2252,11 +2264,11 @@ static int stm32_interrupt(int irq, void *context) /* Cancel any pending poll work */ - work_cancel(HPWORK, &priv->work); + work_cancel(ETHWORK, &priv->work); /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->work, stm32_interrupt_work, priv, 0); + work_queue(ETHWORK, &priv->work, stm32_interrupt_work, priv, 0); } #else @@ -2372,11 +2384,11 @@ static void stm32_txtimeout_expiry(int argc, uint32_t arg, ...) * on work that has already been started. */ - work_cancel(HPWORK, &priv->work); + work_cancel(ETHWORK, &priv->work); /* Schedule to perform the TX timeout processing on the worker thread. */ - work_queue(HPWORK, &priv->work, stm32_txtimeout_work, priv, 0); + work_queue(ETHWORK, &priv->work, stm32_txtimeout_work, priv, 0); #else /* Process the timeout now */ @@ -2516,7 +2528,7 @@ static void stm32_poll_expiry(int argc, uint32_t arg, ...) { /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->work, stm32_poll_work, priv, 0); + work_queue(ETHWORK, &priv->work, stm32_poll_work, priv, 0); } else { @@ -2732,7 +2744,7 @@ static int stm32_txavail(struct net_driver_s *dev) { /* Schedule to serialize the poll on the worker thread. */ - work_queue(HPWORK, &priv->work, stm32_txavail_work, priv, 0); + work_queue(ETHWORK, &priv->work, stm32_txavail_work, priv, 0); } #else diff --git a/arch/arm/src/tiva/Kconfig b/arch/arm/src/tiva/Kconfig index 174252528b..78a7ae07f1 100644 --- a/arch/arm/src/tiva/Kconfig +++ b/arch/arm/src/tiva/Kconfig @@ -1100,6 +1100,25 @@ config TIVA_EMAC_HWCHECKSUM ---help--- Use the hardware checksum capabilities of the Tiva chip +choice + prompt "Work queue" + default TIVA_ETHERNET_LPWORK if SCHED_LPWORK + default TIVA_ETHERNET_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + depends on SCHED_WORKQUEUE + ---help--- + Work queue support is required to use the Ethernet driver. If the + low priority work queue is available, then it should be used by the + driver. + +config TIVA_ETHERNET_HPWORK + bool "High priority" + depends on SCHED_HPWORK + +config TIVA_ETHERNET_LPWORK + bool "Low priority" + depends on SCHED_LPWORK + +endchoice # Work queue config TIVA_ETHERNET_REGDEBUG bool "Register-Level Debug" default n diff --git a/arch/arm/src/tiva/tm4c_ethernet.c b/arch/arm/src/tiva/tm4c_ethernet.c index e7d7d0a67b..3882a95db3 100644 --- a/arch/arm/src/tiva/tm4c_ethernet.c +++ b/arch/arm/src/tiva/tm4c_ethernet.c @@ -98,12 +98,24 @@ # error Logic to support multiple Ethernet interfaces is incomplete #endif -/* If processing is not done at the interrupt level, then high priority - * work queue support is required. +/* If processing is not done at the interrupt level, then work queue support + * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_HPWORK) -# error High priority work queue support is required +#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required +#endif + +/* Select work queue */ + +#if defined(CONFIG_SCHED_WORKQUEUE) +# if defined(CONFIG_TIVA_ETHERNET_HPWORK) +# define ETHWORK HPWORK +# elif defined(CONFIG_TIVA_ETHERNET_LPWORK) +# define ETHWORK LPWORK +# else +# error Neither CONFIG_TIVA_ETHERNET_HPWORK nor CONFIG_TIVA_ETHERNET_LPWORK defined +# endif #endif /* Are we using the internal PHY or an external PHY? */ @@ -2167,11 +2179,11 @@ static int tiva_interrupt(int irq, FAR void *context) /* Cancel any pending poll work */ - work_cancel(HPWORK, &priv->work); + work_cancel(ETHWORK, &priv->work); /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->work, tiva_interrupt_work, priv, 0); + work_queue(ETHWORK, &priv->work, tiva_interrupt_work, priv, 0); } #else @@ -2303,11 +2315,11 @@ static void tiva_txtimeout_expiry(int argc, uint32_t arg, ...) * on work that has already been started. */ - work_cancel(HPWORK, &priv->work); + work_cancel(ETHWORK, &priv->work); /* Schedule to perform the TX timeout processing on the worker thread. */ - work_queue(HPWORK, &priv->work, tiva_txtimeout_work, priv, 0); + work_queue(ETHWORK, &priv->work, tiva_txtimeout_work, priv, 0); #else /* Process the timeout now */ @@ -2447,7 +2459,7 @@ static void tiva_poll_expiry(int argc, uint32_t arg, ...) { /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(HPWORK, &priv->work, tiva_poll_work, priv, 0); + work_queue(ETHWORK, &priv->work, tiva_poll_work, priv, 0); } else { @@ -2662,7 +2674,7 @@ static int tiva_txavail(struct net_driver_s *dev) { /* Schedule to serialize the poll on the worker thread. */ - work_queue(HPWORK, &priv->work, tiva_txavail_work, priv, 0); + work_queue(ETHWORK, &priv->work, tiva_txavail_work, priv, 0); } #else diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 9bb451ab3a..5bcb225dd0 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -24,7 +24,9 @@ choice default LOOPBACK_HPWORK if !SCHED_LPWORK && SCHED_HPWORK depends on SCHED_WORKQUEUE ---help--- - Work queue support is required to use the LOOPBACK driver. If the low priority work queue is available, then it should be used by the LOOPBACK. + Work queue support is required to use the loopback driver. If the + low priority work queue is available, then it should be used by the + loopback driver. config LOOPBACK_HPWORK bool "High priority" @@ -245,7 +247,9 @@ choice default ENC28J60_HPWORK if !SCHED_LPWORK && SCHED_HPWORK depends on SCHED_WORKQUEUE ---help--- - Work queue support is required to use the ENC28J60 driver. If the low priority work queue is available, then it should be used by the ENC28J60. + Work queue support is required to use the ENC28J60 driver. If the + low priority work queue is available, then it should be used by the + ENC28J60 driver. config ENC28J60_HPWORK bool "High priority" @@ -332,7 +336,9 @@ choice default ENCX24J600_HPWORK if !SCHED_LPWORK && SCHED_HPWORK depends on SCHED_WORKQUEUE ---help--- - Work queue support is required to use the ENCX24J600 driver. If the low priority work queue is available, then it should be used by the ENCX24J600. + Work queue support is required to use the ENCX24J600 driver. If the + low priority work queue is available, then it should be used by the + ENCX24J600 driver. config ENCX24J600_HPWORK bool "High priority" @@ -444,7 +450,9 @@ choice default FTMAC100_HPWORK if !SCHED_LPWORK && SCHED_HPWORK depends on SCHED_WORKQUEUE ---help--- - Work queue support is required to use the FTMAC100 driver. If the low priority work queue is available, then it should be used by the FTMAC100. + Work queue support is required to use the FTMAC100 driver. If the + low priority work queue is available, then it should be used by the + FTMAC100 driver. config FTMAC100_HPWORK bool "High priority" diff --git a/net/Kconfig b/net/Kconfig index 2c1aecd291..a216650c76 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -247,7 +247,9 @@ choice default TUN_HPWORK if !SCHED_LPWORK && SCHED_HPWORK depends on SCHED_WORKQUEUE ---help--- - Work queue support is required to use the TUN driver. If the low priority work queue is available, then it should be used by the TUN. + Work queue support is required to use the TUN driver. If the + low priority work queue is available, then it should be used by the + TUN driver. config TUN_HPWORK bool "High priority" -- GitLab From 439c72e7c861d9c4d4f6e795cf8f357e6bbfc472 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 19 Nov 2016 09:41:24 -0600 Subject: [PATCH 459/734] Refresh all networking configurations due to changes in work-queue related configuration variables for Ethernet drivers. --- configs/c5471evm/httpd/defconfig | 31 ++++++- configs/c5471evm/nettest/defconfig | 31 ++++++- configs/c5471evm/nsh/defconfig | 35 ++++++-- configs/cloudctrl/nsh/defconfig | 28 +++++- configs/dk-tm4c129x/ipv6/defconfig | 44 ++++++++-- configs/dk-tm4c129x/nsh/defconfig | 44 ++++++++-- configs/eagle100/httpd/defconfig | 31 ++++++- configs/eagle100/nettest/defconfig | 31 ++++++- configs/eagle100/nsh/defconfig | 44 +++++++--- configs/eagle100/thttpd/defconfig | 15 ++++ configs/ekk-lm3s9b96/nsh/defconfig | 44 +++++++--- configs/ez80f910200zco/dhcpd/defconfig | 22 ++++- configs/ez80f910200zco/httpd/defconfig | 22 ++++- configs/ez80f910200zco/nettest/defconfig | 22 ++++- configs/ez80f910200zco/nsh/defconfig | 24 +++-- configs/ez80f910200zco/poll/defconfig | 19 +++- configs/fire-stm32v2/nsh/defconfig | 26 +++++- configs/freedom-k64f/netnsh/defconfig | 25 ++++++ configs/lincoln60/netnsh/defconfig | 39 ++++++-- configs/lincoln60/thttpd-binfs/defconfig | 19 +++- configs/lm3s6432-s2e/nsh/defconfig | 35 ++++++-- configs/lm3s6965-ek/discover/defconfig | 44 +++++++--- configs/lm3s6965-ek/nsh/defconfig | 44 +++++++--- configs/lm3s6965-ek/tcpecho/defconfig | 31 ++++++- configs/lm3s8962-ek/nsh/defconfig | 44 +++++++--- configs/lpcxpresso-lpc1768/dhcpd/defconfig | 34 +++++-- configs/lpcxpresso-lpc1768/nsh/defconfig | 47 +++++++--- configs/lpcxpresso-lpc1768/thttpd/defconfig | 18 +++- configs/moxa/nsh/defconfig | 38 ++++++-- configs/ntosd-dm320/nettest/defconfig | 31 ++++++- configs/ntosd-dm320/nsh/defconfig | 37 ++++++-- configs/ntosd-dm320/poll/defconfig | 17 +++- configs/ntosd-dm320/thttpd/defconfig | 15 ++++ configs/ntosd-dm320/udp/defconfig | 31 ++++++- configs/ntosd-dm320/webserver/defconfig | 31 ++++++- configs/olimex-lpc1766stk/ftpc/defconfig | 47 +++++++--- configs/olimex-lpc1766stk/hidmouse/defconfig | 39 ++++++-- configs/olimex-lpc1766stk/nettest/defconfig | 35 ++++++-- configs/olimex-lpc1766stk/nsh/defconfig | 47 +++++++--- .../olimex-lpc1766stk/slip-httpd/defconfig | 18 +++- .../olimex-lpc1766stk/thttpd-binfs/defconfig | 19 +++- .../olimex-lpc1766stk/thttpd-nxflat/defconfig | 19 +++- configs/olimex-lpc1766stk/zmodem/defconfig | 47 +++++++--- configs/olimex-stm32-e407/discover/defconfig | 33 ++++--- configs/olimex-stm32-e407/netnsh/defconfig | 36 +++++--- configs/olimex-stm32-e407/telnetd/defconfig | 35 +++++--- configs/olimex-stm32-e407/webserver/defconfig | 35 +++++--- configs/olimex-stm32-p107/nsh/defconfig | 23 +++++ configs/olimex-stm32-p207/nsh/defconfig | 12 +++ configs/olimex-strp711/nettest/defconfig | 37 ++++++-- configs/pic32mx-starterkit/nsh2/defconfig | 30 +++++-- configs/pic32mx7mmb/nsh/defconfig | 34 +++++-- configs/sam4e-ek/nsh/defconfig | 43 +++++++-- configs/sam4e-ek/nxwm/defconfig | 44 ++++++++-- configs/sam4e-ek/usbnsh/defconfig | 42 +++++++-- configs/sama5d3-xplained/bridge/defconfig | 32 ++++++- configs/sama5d4-ek/bridge/defconfig | 32 ++++++- configs/sama5d4-ek/ipv6/defconfig | 7 ++ configs/sama5d4-ek/nsh/defconfig | 7 ++ configs/sama5d4-ek/nxwm/defconfig | 7 ++ configs/same70-xplained/netnsh/defconfig | 10 ++- configs/samv71-xult/netnsh/defconfig | 10 ++- configs/samv71-xult/vnc/defconfig | 25 ++++-- configs/samv71-xult/vnxwm/defconfig | 25 ++++-- configs/shenzhou/nsh/defconfig | 27 +++++- configs/shenzhou/nxwm/defconfig | 28 +++++- configs/shenzhou/thttpd/defconfig | 28 +++++- configs/sim/nettest/defconfig | 88 +++++++++++++------ configs/sim/udgram/defconfig | 18 ++++ configs/sim/ustream/defconfig | 18 ++++ configs/stm3220g-eval/dhcpd/defconfig | 19 ++++ configs/stm3220g-eval/nettest/defconfig | 19 ++++ configs/stm3220g-eval/nsh/defconfig | 22 +++++ configs/stm3220g-eval/nsh2/defconfig | 23 +++++ configs/stm3220g-eval/nxwm/defconfig | 23 +++++ configs/stm3220g-eval/telnetd/defconfig | 19 ++++ configs/stm3240g-eval/dhcpd/defconfig | 19 ++++ configs/stm3240g-eval/discover/defconfig | 19 ++++ configs/stm3240g-eval/nettest/defconfig | 19 ++++ configs/stm3240g-eval/nsh/defconfig | 21 +++++ configs/stm3240g-eval/nsh2/defconfig | 23 +++++ configs/stm3240g-eval/nxterm/defconfig | 22 +++++ configs/stm3240g-eval/nxwm/defconfig | 23 +++++ configs/stm3240g-eval/telnetd/defconfig | 19 ++++ configs/stm3240g-eval/webserver/defconfig | 22 +++++ configs/stm3240g-eval/xmlrpc/defconfig | 19 ++++ configs/stm32butterfly2/nshnet/defconfig | 18 +++- configs/stm32f4discovery/ipv6/defconfig | 26 +++++- configs/stm32f4discovery/netnsh/defconfig | 26 +++++- configs/tm4c1294-launchpad/ipv6/defconfig | 37 ++++++-- configs/tm4c1294-launchpad/nsh/defconfig | 37 ++++++-- configs/u-blox-c027/nsh/defconfig | 29 ++++-- configs/viewtool-stm32f107/netnsh/defconfig | 23 +++++ configs/zkit-arm-1769/hello/defconfig | 34 +++++-- configs/zkit-arm-1769/nsh/defconfig | 47 +++++++--- configs/zkit-arm-1769/nxhello/defconfig | 48 +++++++--- configs/zkit-arm-1769/thttpd/defconfig | 18 +++- 97 files changed, 2368 insertions(+), 436 deletions(-) diff --git a/configs/c5471evm/httpd/defconfig b/configs/c5471evm/httpd/defconfig index b3979e7bc7..4d735ee6e2 100644 --- a/configs/c5471evm/httpd/defconfig +++ b/configs/c5471evm/httpd/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -236,6 +239,7 @@ CONFIG_ARCH_LEDS=y # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set # @@ -254,6 +258,7 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2007 CONFIG_START_MONTH=2 @@ -340,6 +345,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=4096 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -355,12 +361,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set CONFIG_WATCHDOG=y CONFIG_WATCHDOG_DEVPATH="/dev/watchdog0" @@ -369,7 +379,12 @@ CONFIG_WATCHDOG_DEVPATH="/dev/watchdog0" # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -430,9 +445,12 @@ CONFIG_MCU_SERIAL=y # CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set CONFIG_OTHER_SERIAL_CONSOLE=y # CONFIG_NO_SERIAL_CONSOLE is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -446,6 +464,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -625,6 +644,8 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -650,6 +671,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -668,9 +690,9 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set @@ -697,10 +719,9 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -744,6 +765,7 @@ CONFIG_EXAMPLES_WEBSERVER_NOMAC=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -796,13 +818,14 @@ CONFIG_NETUTILS_HTTPD_KEEPALIVE_DISABLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/c5471evm/nettest/defconfig b/configs/c5471evm/nettest/defconfig index 699e8aac8d..e16e805626 100644 --- a/configs/c5471evm/nettest/defconfig +++ b/configs/c5471evm/nettest/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -236,6 +239,7 @@ CONFIG_ARCH_LEDS=y # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set # @@ -254,6 +258,7 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2007 CONFIG_START_MONTH=2 @@ -333,6 +338,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=4096 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -348,12 +354,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set CONFIG_WATCHDOG=y CONFIG_WATCHDOG_DEVPATH="/dev/watchdog0" @@ -362,7 +372,12 @@ CONFIG_WATCHDOG_DEVPATH="/dev/watchdog0" # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -423,9 +438,12 @@ CONFIG_MCU_SERIAL=y # CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set CONFIG_OTHER_SERIAL_CONSOLE=y # CONFIG_NO_SERIAL_CONSOLE is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -439,6 +457,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -618,6 +637,8 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -643,6 +664,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -661,9 +683,9 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set @@ -703,10 +725,9 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -746,6 +767,7 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -787,13 +809,14 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/c5471evm/nsh/defconfig b/configs/c5471evm/nsh/defconfig index d0b2030305..e61a16c8f1 100644 --- a/configs/c5471evm/nsh/defconfig +++ b/configs/c5471evm/nsh/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -232,11 +235,11 @@ CONFIG_ARCH_BOARD="c5471evm" # CONFIG_ARCH_HAVE_LEDS=y CONFIG_ARCH_LEDS=y -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set # @@ -255,6 +258,7 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2007 CONFIG_START_MONTH=2 @@ -341,6 +345,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=4096 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -356,12 +361,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set CONFIG_WATCHDOG=y CONFIG_WATCHDOG_DEVPATH="/dev/watchdog0" @@ -370,7 +379,12 @@ CONFIG_WATCHDOG_DEVPATH="/dev/watchdog0" # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -432,9 +446,12 @@ CONFIG_MCU_SERIAL=y # CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set CONFIG_OTHER_SERIAL_CONSOLE=y # CONFIG_NO_SERIAL_CONSOLE is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -448,6 +465,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -632,6 +650,8 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -664,6 +684,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -682,9 +703,9 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -712,10 +733,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -757,6 +777,7 @@ CONFIG_EXAMPLES_NSH=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -834,13 +855,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_LS is not set # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -858,6 +879,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -931,7 +953,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -942,6 +964,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/cloudctrl/nsh/defconfig b/configs/cloudctrl/nsh/defconfig index 1c91205536..2b7a000923 100644 --- a/configs/cloudctrl/nsh/defconfig +++ b/configs/cloudctrl/nsh/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -357,6 +360,12 @@ CONFIG_STM32_HAVE_ADC2=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -389,6 +398,7 @@ CONFIG_STM32_PWR=y CONFIG_STM32_SPI1=y # CONFIG_STM32_SPI2 is not set # CONFIG_STM32_SPI3 is not set +CONFIG_STM32_SYSCFG=y # CONFIG_STM32_TIM1 is not set # CONFIG_STM32_TIM2 is not set # CONFIG_STM32_TIM3 is not set @@ -480,6 +490,7 @@ CONFIG_STM32_PHYSR_100FD=0x8000 CONFIG_STM32_RMII=y CONFIG_STM32_RMII_MCO=y # CONFIG_STM32_RMII_EXTCLK is not set +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -561,6 +572,7 @@ CONFIG_RAM_SIZE=65536 CONFIG_ARCH_BOARD_CLOUDCTRL=y # CONFIG_ARCH_BOARD_OLIMEX_STM32P107 is not set # CONFIG_ARCH_BOARD_SHENZHOU is not set +# CONFIG_ARCH_BOARD_STM32_BUTTERFLY2 is not set # CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107 is not set # CONFIG_ARCH_BOARD_CUSTOM is not set CONFIG_ARCH_BOARD="cloudctrl" @@ -716,14 +728,14 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -734,6 +746,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y # CONFIG_RTC_DATETIME is not set # CONFIG_RTC_HIRES is not set @@ -882,6 +895,7 @@ CONFIG_USART2_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1098,6 +1112,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1166,6 +1182,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1246,6 +1264,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1333,6 +1352,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1437,6 +1457,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/dk-tm4c129x/ipv6/defconfig b/configs/dk-tm4c129x/ipv6/defconfig index 7e10afee1a..31725598d3 100644 --- a/configs/dk-tm4c129x/ipv6/defconfig +++ b/configs/dk-tm4c129x/ipv6/defconfig @@ -64,10 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -279,6 +282,7 @@ CONFIG_TIVA_PHY_INTERRUPTS=y CONFIG_TIVA_EMAC_NRXDESC=8 CONFIG_TIVA_EMAC_NTXDESC=4 # CONFIG_TIVA_EMAC_ENHANCEDDESC is not set +CONFIG_TIVA_ETHERNET_HPWORK=y CONFIG_TIVA_BOARDMAC=y # @@ -355,11 +359,11 @@ CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_HAVE_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -385,6 +389,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2013 CONFIG_START_MONTH=3 @@ -482,6 +487,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -501,12 +507,16 @@ CONFIG_I2C=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_TIMERS_CS2100CP is not set @@ -515,7 +525,12 @@ CONFIG_I2C_DRIVER=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -562,10 +577,14 @@ CONFIG_ARCH_PHY_INTERRUPT=y CONFIG_SENSORS=y # CONFIG_AS5048B is not set # CONFIG_BH1750FVI is not set +# CONFIG_BMG160 is not set # CONFIG_BMP180 is not set +# CONFIG_SENSOR_KXTJ9 is not set +# CONFIG_LIS3DSH is not set # CONFIG_LIS331DL is not set # CONFIG_SN_LSM9DS1 is not set # CONFIG_MB7040 is not set +# CONFIG_MLX90393 is not set # CONFIG_MCP9844 is not set # CONFIG_MS58XX is not set CONFIG_MS58XX_VDD=30 @@ -574,10 +593,13 @@ CONFIG_MS58XX_VDD=30 # CONFIG_MAX31855 is not set # CONFIG_MAX6675 is not set CONFIG_I2C_LM75=y +# CONFIG_LIS3MDL is not set CONFIG_LM75=y CONFIG_LM75_I2C_FREQUENCY=100000 # CONFIG_LM92 is not set # CONFIG_QENCODER is not set +# CONFIG_VEML6070 is not set +# CONFIG_XEN1210 is not set # CONFIG_ZEROCROSS is not set # CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y @@ -629,9 +651,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -645,6 +670,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -841,6 +867,8 @@ CONFIG_LIBM=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -868,6 +896,7 @@ CONFIG_LIBC_NETDB=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -891,10 +920,11 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -922,9 +952,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -967,6 +997,7 @@ CONFIG_EXAMPLES_NSH=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1041,12 +1072,12 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_LS is not set # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1063,6 +1094,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -1156,7 +1188,7 @@ CONFIG_NSH_MAX_ROUNDTRIP=20 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=6 @@ -1181,6 +1213,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/dk-tm4c129x/nsh/defconfig b/configs/dk-tm4c129x/nsh/defconfig index 671ba7c4d8..86d440f9e4 100644 --- a/configs/dk-tm4c129x/nsh/defconfig +++ b/configs/dk-tm4c129x/nsh/defconfig @@ -64,10 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -279,6 +282,7 @@ CONFIG_TIVA_PHY_INTERRUPTS=y CONFIG_TIVA_EMAC_NRXDESC=8 CONFIG_TIVA_EMAC_NTXDESC=4 # CONFIG_TIVA_EMAC_ENHANCEDDESC is not set +CONFIG_TIVA_ETHERNET_HPWORK=y CONFIG_TIVA_BOARDMAC=y # @@ -355,11 +359,11 @@ CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_HAVE_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -385,6 +389,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2013 CONFIG_START_MONTH=3 @@ -482,6 +487,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -501,12 +507,16 @@ CONFIG_I2C=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_TIMERS_CS2100CP is not set @@ -515,7 +525,12 @@ CONFIG_I2C_DRIVER=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -564,10 +579,14 @@ CONFIG_ARCH_PHY_INTERRUPT=y CONFIG_SENSORS=y # CONFIG_AS5048B is not set # CONFIG_BH1750FVI is not set +# CONFIG_BMG160 is not set # CONFIG_BMP180 is not set +# CONFIG_SENSOR_KXTJ9 is not set +# CONFIG_LIS3DSH is not set # CONFIG_LIS331DL is not set # CONFIG_SN_LSM9DS1 is not set # CONFIG_MB7040 is not set +# CONFIG_MLX90393 is not set # CONFIG_MCP9844 is not set # CONFIG_MS58XX is not set CONFIG_MS58XX_VDD=30 @@ -576,10 +595,13 @@ CONFIG_MS58XX_VDD=30 # CONFIG_MAX31855 is not set # CONFIG_MAX6675 is not set CONFIG_I2C_LM75=y +# CONFIG_LIS3MDL is not set CONFIG_LM75=y CONFIG_LM75_I2C_FREQUENCY=100000 # CONFIG_LM92 is not set # CONFIG_QENCODER is not set +# CONFIG_VEML6070 is not set +# CONFIG_XEN1210 is not set # CONFIG_ZEROCROSS is not set # CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y @@ -631,9 +653,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -647,6 +672,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -845,6 +871,8 @@ CONFIG_LIBM=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -878,6 +906,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -901,10 +930,11 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -932,9 +962,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -977,6 +1007,7 @@ CONFIG_EXAMPLES_NSH=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1056,13 +1087,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_LS is not set # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1080,6 +1111,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -1156,7 +1188,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=6 @@ -1181,6 +1213,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/eagle100/httpd/defconfig b/configs/eagle100/httpd/defconfig index 5c8ace100e..9705928334 100644 --- a/configs/eagle100/httpd/defconfig +++ b/configs/eagle100/httpd/defconfig @@ -64,10 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -338,6 +341,7 @@ CONFIG_ARCH_LEDS=y # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set # @@ -356,6 +360,7 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2009 CONFIG_START_MONTH=5 @@ -442,6 +447,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -457,12 +463,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -470,7 +480,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -564,9 +579,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -580,6 +598,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -759,6 +778,8 @@ CONFIG_NUNGET_CHARS=0 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -784,6 +805,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -802,9 +824,9 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set @@ -831,10 +853,9 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -878,6 +899,7 @@ CONFIG_EXAMPLES_WEBSERVER_NOMAC=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -930,13 +952,14 @@ CONFIG_NETUTILS_HTTPD_KEEPALIVE_DISABLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/eagle100/nettest/defconfig b/configs/eagle100/nettest/defconfig index 4b22994e83..5d908c3893 100644 --- a/configs/eagle100/nettest/defconfig +++ b/configs/eagle100/nettest/defconfig @@ -64,10 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -338,6 +341,7 @@ CONFIG_ARCH_LEDS=y # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set # @@ -356,6 +360,7 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2009 CONFIG_START_MONTH=5 @@ -435,6 +440,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -450,12 +456,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -463,7 +473,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -556,9 +571,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -572,6 +590,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -751,6 +770,8 @@ CONFIG_NUNGET_CHARS=0 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -776,6 +797,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -794,9 +816,9 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set @@ -836,10 +858,9 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -879,6 +900,7 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -920,13 +942,14 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/eagle100/nsh/defconfig b/configs/eagle100/nsh/defconfig index c05da40e47..3551825edb 100644 --- a/configs/eagle100/nsh/defconfig +++ b/configs/eagle100/nsh/defconfig @@ -64,10 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -334,13 +337,11 @@ CONFIG_ARCH_BOARD="eagle100" # CONFIG_ARCH_HAVE_LEDS=y CONFIG_ARCH_LEDS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDSPIPORTNO=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -366,6 +367,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2012 CONFIG_START_MONTH=2 @@ -458,6 +460,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -473,21 +476,24 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set CONFIG_SPI_CALLBACK=y -# CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -495,7 +501,12 @@ CONFIG_SPI_CALLBACK=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -602,9 +613,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -618,6 +632,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -818,6 +833,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -855,6 +872,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -873,9 +891,9 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -904,10 +922,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -952,6 +969,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1031,13 +1049,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1055,6 +1073,9 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 +CONFIG_NSH_MMCSDSPIPORTNO=0 # # Configure Command Options @@ -1126,7 +1147,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -1137,6 +1158,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/eagle100/thttpd/defconfig b/configs/eagle100/thttpd/defconfig index 3d65f0d25f..7b2287eaf1 100644 --- a/configs/eagle100/thttpd/defconfig +++ b/configs/eagle100/thttpd/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -350,6 +353,7 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2009 CONFIG_START_MONTH=7 @@ -445,12 +449,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -564,6 +572,7 @@ CONFIG_UART0_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -765,6 +774,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -811,6 +822,7 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CPUHOG is not set @@ -845,6 +857,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set @@ -893,6 +906,7 @@ CONFIG_EXAMPLES_THTTPD_NETMASK=0xffffff00 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -975,6 +989,7 @@ CONFIG_THTTPD_TILDE_MAP_NONE=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/ekk-lm3s9b96/nsh/defconfig b/configs/ekk-lm3s9b96/nsh/defconfig index 242ef3b8cf..d1f6d9bf57 100644 --- a/configs/ekk-lm3s9b96/nsh/defconfig +++ b/configs/ekk-lm3s9b96/nsh/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -323,13 +326,11 @@ CONFIG_ARCH_BOARD="ekk-lm3s9b96" # CONFIG_ARCH_HAVE_LEDS=y CONFIG_ARCH_LEDS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDSPIPORTNO=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -355,6 +356,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2010 CONFIG_START_MONTH=5 @@ -447,6 +449,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -462,21 +465,24 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set CONFIG_SPI_CALLBACK=y -# CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -484,7 +490,12 @@ CONFIG_SPI_CALLBACK=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -591,9 +602,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -607,6 +621,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -808,6 +823,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -845,6 +862,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -863,9 +881,9 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -894,10 +912,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -942,6 +959,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1020,7 +1038,6 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set @@ -1028,6 +1045,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSFMOUNT is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1045,6 +1063,9 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 +CONFIG_NSH_MMCSDSPIPORTNO=0 # # Configure Command Options @@ -1118,7 +1139,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -1129,6 +1150,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/ez80f910200zco/dhcpd/defconfig b/configs/ez80f910200zco/dhcpd/defconfig index 77b5b02b10..9a740baa64 100644 --- a/configs/ez80f910200zco/dhcpd/defconfig +++ b/configs/ez80f910200zco/dhcpd/defconfig @@ -62,10 +62,13 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set CONFIG_ARCH_Z80=y CONFIG_ARCH="z80" @@ -204,7 +207,6 @@ CONFIG_RAM_SIZE=65536 # # Board Selection # -# CONFIG_ARCH_BOARD_EZ80F910200KITG is not set CONFIG_ARCH_BOARD_EZ80F910200ZCO=y # CONFIG_ARCH_BOARD_CUSTOM is not set CONFIG_ARCH_BOARD="ez80f910200zco" @@ -239,6 +241,7 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2009 CONFIG_START_MONTH=3 @@ -318,6 +321,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=1024 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -333,12 +337,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -462,10 +470,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -656,6 +666,8 @@ CONFIG_NUNGET_CHARS=0 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -700,9 +712,10 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set CONFIG_EXAMPLES_DHCPD=y CONFIG_EXAMPLES_DHCPD_NOMAC=y CONFIG_EXAMPLES_DHCPD_IPADDR=0x0a000001 @@ -733,10 +746,9 @@ CONFIG_EXAMPLES_DHCPD_NETMASK=0xffffff00 # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -777,6 +789,7 @@ CONFIG_EXAMPLES_DHCPD_NETMASK=0xffffff00 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -839,6 +852,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/ez80f910200zco/httpd/defconfig b/configs/ez80f910200zco/httpd/defconfig index 7121896701..60fb2abeb9 100644 --- a/configs/ez80f910200zco/httpd/defconfig +++ b/configs/ez80f910200zco/httpd/defconfig @@ -62,10 +62,13 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set CONFIG_ARCH_Z80=y CONFIG_ARCH="z80" @@ -204,7 +207,6 @@ CONFIG_RAM_SIZE=65536 # # Board Selection # -# CONFIG_ARCH_BOARD_EZ80F910200KITG is not set CONFIG_ARCH_BOARD_EZ80F910200ZCO=y # CONFIG_ARCH_BOARD_CUSTOM is not set CONFIG_ARCH_BOARD="ez80f910200zco" @@ -239,6 +241,7 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2009 CONFIG_START_MONTH=3 @@ -325,6 +328,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -340,12 +344,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -471,10 +479,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -670,6 +680,8 @@ CONFIG_NUNGET_CHARS=0 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -713,9 +725,10 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set @@ -742,10 +755,9 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -789,6 +801,7 @@ CONFIG_EXAMPLES_WEBSERVER_NOMAC=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -848,6 +861,7 @@ CONFIG_NETUTILS_HTTPD_KEEPALIVE_DISABLE=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/ez80f910200zco/nettest/defconfig b/configs/ez80f910200zco/nettest/defconfig index 333e68eadb..446c99cbb8 100644 --- a/configs/ez80f910200zco/nettest/defconfig +++ b/configs/ez80f910200zco/nettest/defconfig @@ -62,10 +62,13 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set CONFIG_ARCH_Z80=y CONFIG_ARCH="z80" @@ -204,7 +207,6 @@ CONFIG_RAM_SIZE=65536 # # Board Selection # -# CONFIG_ARCH_BOARD_EZ80F910200KITG is not set CONFIG_ARCH_BOARD_EZ80F910200ZCO=y # CONFIG_ARCH_BOARD_CUSTOM is not set CONFIG_ARCH_BOARD="ez80f910200zco" @@ -239,6 +241,7 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2009 CONFIG_START_MONTH=3 @@ -318,6 +321,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=1024 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -333,12 +337,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -463,10 +471,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -662,6 +672,8 @@ CONFIG_NUNGET_CHARS=0 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -705,9 +717,10 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set @@ -747,10 +760,9 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -790,6 +802,7 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -838,6 +851,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/ez80f910200zco/nsh/defconfig b/configs/ez80f910200zco/nsh/defconfig index a4ee41fe44..20c5d5e5e4 100644 --- a/configs/ez80f910200zco/nsh/defconfig +++ b/configs/ez80f910200zco/nsh/defconfig @@ -62,10 +62,13 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set CONFIG_ARCH_Z80=y CONFIG_ARCH="z80" @@ -204,7 +207,6 @@ CONFIG_RAM_SIZE=65536 # # Board Selection # -# CONFIG_ARCH_BOARD_EZ80F910200KITG is not set CONFIG_ARCH_BOARD_EZ80F910200ZCO=y # CONFIG_ARCH_BOARD_CUSTOM is not set CONFIG_ARCH_BOARD="ez80f910200zco" @@ -239,6 +241,7 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2009 CONFIG_START_MONTH=3 @@ -325,6 +328,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=1024 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -340,12 +344,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -474,10 +482,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -687,6 +697,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -738,9 +750,10 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -768,10 +781,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -813,6 +825,7 @@ CONFIG_EXAMPLES_NSH=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -891,13 +904,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_LS is not set # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1000,6 +1013,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/ez80f910200zco/poll/defconfig b/configs/ez80f910200zco/poll/defconfig index e70d6999a6..3a6fea2c6c 100644 --- a/configs/ez80f910200zco/poll/defconfig +++ b/configs/ez80f910200zco/poll/defconfig @@ -62,10 +62,13 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set CONFIG_ARCH_Z80=y CONFIG_ARCH="z80" @@ -204,7 +207,6 @@ CONFIG_RAM_SIZE=65536 # # Board Selection # -# CONFIG_ARCH_BOARD_EZ80F910200KITG is not set CONFIG_ARCH_BOARD_EZ80F910200ZCO=y # CONFIG_ARCH_BOARD_CUSTOM is not set CONFIG_ARCH_BOARD="ez80f910200zco" @@ -239,6 +241,7 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2009 CONFIG_START_MONTH=3 @@ -341,12 +344,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -479,6 +486,7 @@ CONFIG_UART0_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -674,6 +682,8 @@ CONFIG_NUNGET_CHARS=0 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -717,6 +727,8 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CPUHOG is not set @@ -737,10 +749,10 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_NRF24L01TERM is not set # CONFIG_EXAMPLES_NSH is not set # CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set @@ -754,6 +766,7 @@ CONFIG_EXAMPLES_POLL_DRIPADDR=0x0a000001 CONFIG_EXAMPLES_POLL_NETMASK=0xffffff00 # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -794,6 +807,7 @@ CONFIG_EXAMPLES_POLL_NETMASK=0xffffff00 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -844,6 +858,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/fire-stm32v2/nsh/defconfig b/configs/fire-stm32v2/nsh/defconfig index e1ecadbd75..56b6462675 100644 --- a/configs/fire-stm32v2/nsh/defconfig +++ b/configs/fire-stm32v2/nsh/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -359,6 +362,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y # CONFIG_STM32_HAVE_CAN2 is not set CONFIG_STM32_HAVE_DAC1=y @@ -733,14 +742,14 @@ CONFIG_I2C_POLLED=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -751,6 +760,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y # CONFIG_RTC_DATETIME is not set # CONFIG_RTC_HIRES is not set @@ -825,6 +835,7 @@ CONFIG_ENC28J60=y CONFIG_ENC28J60_NINTERFACES=1 CONFIG_ENC28J60_SPIMODE=0 CONFIG_ENC28J60_FREQUENCY=20000000 +CONFIG_ENC28J60_HPWORK=y # CONFIG_ENC28J60_HALFDUPPLEX is not set # CONFIG_ENC28J60_DUMPPACKET is not set # CONFIG_ENCX24J600 is not set @@ -940,6 +951,7 @@ CONFIG_USBMSC_SCSI_STACKSIZE=2048 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1156,6 +1168,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1217,6 +1231,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1294,6 +1310,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1380,6 +1397,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1491,6 +1509,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set CONFIG_SYSTEM_USBMSC=y CONFIG_SYSTEM_USBMSC_NLUNS=1 diff --git a/configs/freedom-k64f/netnsh/defconfig b/configs/freedom-k64f/netnsh/defconfig index 3b9a628960..7303dda872 100644 --- a/configs/freedom-k64f/netnsh/defconfig +++ b/configs/freedom-k64f/netnsh/defconfig @@ -64,10 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -125,6 +128,9 @@ CONFIG_ARCH_CHIP="kinetis" # CONFIG_ARM_TOOLCHAIN_IAR is not set CONFIG_ARM_TOOLCHAIN_GNU=y # CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARMV7M_LAZYFPU is not set CONFIG_ARCH_HAVE_FPU=y # CONFIG_ARCH_HAVE_DPFPU is not set # CONFIG_ARCH_FPU is not set @@ -191,6 +197,8 @@ CONFIG_ARCH_FAMILY_K64=y # # Kinetis Peripheral Support # +CONFIG_KINETIS_HAVE_I2C1=y +CONFIG_KINETIS_HAVE_I2C2=y # CONFIG_KINETIS_TRACE is not set # CONFIG_KINETIS_FLEXBUS is not set # CONFIG_KINETIS_UART0 is not set @@ -208,6 +216,7 @@ CONFIG_KINETIS_ENET=y # CONFIG_KINETIS_SPI2 is not set # CONFIG_KINETIS_I2C0 is not set # CONFIG_KINETIS_I2C1 is not set +# CONFIG_KINETIS_I2C2 is not set # CONFIG_KINETIS_I2S is not set # CONFIG_KINETIS_DAC0 is not set # CONFIG_KINETIS_DAC1 is not set @@ -248,6 +257,7 @@ CONFIG_KINETIS_ENETNTXBUFFERS=2 # CONFIG_KINETIS_ENETUSEMII is not set CONFIG_KINETIS_ENET_MDIOPULLUP=y # CONFIG_KINETIS_ENET_NORXER is not set +CONFIG_KINETIS_EMAC_HPWORK=y # # Kinetis UART Configuration @@ -357,6 +367,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2013 CONFIG_START_MONTH=3 @@ -470,12 +481,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -609,6 +624,7 @@ CONFIG_UART3_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -836,6 +852,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -898,6 +916,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -930,6 +950,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PCA9635 is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -974,6 +995,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1060,6 +1082,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1166,6 +1189,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/lincoln60/netnsh/defconfig b/configs/lincoln60/netnsh/defconfig index a323b8474e..6875687ca8 100644 --- a/configs/lincoln60/netnsh/defconfig +++ b/configs/lincoln60/netnsh/defconfig @@ -64,10 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -152,7 +155,6 @@ CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y # CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE is not set # CONFIG_ARMV7M_HAVE_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_LPC17_GPIOIRQ is not set # CONFIG_SERIAL_TERMIOS is not set # @@ -227,6 +229,7 @@ CONFIG_LPC17_SSP0=y # # Serial driver options # +# CONFIG_LPC17_GPIOIRQ is not set # # Ethernet driver options @@ -238,6 +241,7 @@ CONFIG_NET_NRXDESC=6 # CONFIG_NET_WOL is not set # CONFIG_NET_HASH is not set # CONFIG_LPC17_MULTICAST is not set +CONFIG_LPC17_ETHERNET_HPWORK=y # # Architecture Options @@ -312,11 +316,11 @@ CONFIG_ARCH_LEDS=y CONFIG_ARCH_HAVE_BUTTONS=y # CONFIG_ARCH_BUTTONS is not set CONFIG_ARCH_HAVE_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -342,6 +346,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2010 CONFIG_START_MONTH=6 @@ -439,6 +444,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -454,12 +460,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -467,7 +477,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -583,9 +598,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -599,6 +617,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -802,6 +821,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -839,6 +860,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -857,9 +879,10 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -888,10 +911,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -936,6 +958,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1015,13 +1038,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1039,6 +1062,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -1113,7 +1137,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -1124,6 +1148,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/lincoln60/thttpd-binfs/defconfig b/configs/lincoln60/thttpd-binfs/defconfig index 6637795fed..4d54e20560 100644 --- a/configs/lincoln60/thttpd-binfs/defconfig +++ b/configs/lincoln60/thttpd-binfs/defconfig @@ -64,10 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -152,7 +155,6 @@ CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y # CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE is not set # CONFIG_ARMV7M_HAVE_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_LPC17_GPIOIRQ is not set # CONFIG_SERIAL_TERMIOS is not set # @@ -227,6 +229,7 @@ CONFIG_LPC17_UART0=y # # Serial driver options # +# CONFIG_LPC17_GPIOIRQ is not set # # Ethernet driver options @@ -238,6 +241,7 @@ CONFIG_NET_NRXDESC=8 # CONFIG_NET_WOL is not set # CONFIG_NET_HASH is not set # CONFIG_LPC17_MULTICAST is not set +CONFIG_LPC17_ETHERNET_HPWORK=y # # Architecture Options @@ -335,6 +339,7 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2015 CONFIG_START_MONTH=6 @@ -435,12 +440,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -573,6 +582,7 @@ CONFIG_UART0_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -778,6 +788,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -829,6 +841,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CPUHOG is not set @@ -862,6 +876,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set @@ -910,6 +925,7 @@ CONFIG_EXAMPLES_THTTPD_NETMASK=0xffffff00 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -992,6 +1008,7 @@ CONFIG_THTTPD_TILDE_MAP_NONE=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/lm3s6432-s2e/nsh/defconfig b/configs/lm3s6432-s2e/nsh/defconfig index ddd1c6a354..16f56238ee 100644 --- a/configs/lm3s6432-s2e/nsh/defconfig +++ b/configs/lm3s6432-s2e/nsh/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -318,11 +321,11 @@ CONFIG_ARCH_BOARD="lm3s6432-s2e" # CONFIG_ARCH_HAVE_LEDS=y CONFIG_ARCH_LEDS=y -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -348,6 +351,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2010 CONFIG_START_MONTH=5 @@ -440,6 +444,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -455,12 +460,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -468,7 +477,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -579,9 +593,12 @@ CONFIG_UART1_2STOP=0 # CONFIG_UART1_IFLOWCONTROL is not set # CONFIG_UART1_OFLOWCONTROL is not set # CONFIG_UART1_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -595,6 +612,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -789,6 +807,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -822,6 +842,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -840,9 +861,9 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -870,10 +891,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -916,6 +936,7 @@ CONFIG_EXAMPLES_NSH=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -994,13 +1015,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_LS is not set # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1018,6 +1039,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -1089,7 +1111,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -1100,6 +1122,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/lm3s6965-ek/discover/defconfig b/configs/lm3s6965-ek/discover/defconfig index b5099e6034..6604cf2e5c 100644 --- a/configs/lm3s6965-ek/discover/defconfig +++ b/configs/lm3s6965-ek/discover/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -328,13 +331,11 @@ CONFIG_ARCH_BOARD="lm3s6965-ek" # CONFIG_ARCH_HAVE_LEDS=y CONFIG_ARCH_LEDS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDSPIPORTNO=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -360,6 +361,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2010 CONFIG_START_MONTH=5 @@ -452,6 +454,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -467,21 +470,24 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set CONFIG_SPI_CALLBACK=y -# CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -489,7 +495,12 @@ CONFIG_SPI_CALLBACK=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -596,9 +607,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -612,6 +626,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -812,6 +827,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -849,6 +866,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -867,9 +885,9 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -898,10 +916,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -946,6 +963,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1025,13 +1043,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1049,6 +1067,9 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 +CONFIG_NSH_MMCSDSPIPORTNO=0 # # Configure Command Options @@ -1123,7 +1144,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -1134,6 +1155,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/lm3s6965-ek/nsh/defconfig b/configs/lm3s6965-ek/nsh/defconfig index b5099e6034..6604cf2e5c 100644 --- a/configs/lm3s6965-ek/nsh/defconfig +++ b/configs/lm3s6965-ek/nsh/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -328,13 +331,11 @@ CONFIG_ARCH_BOARD="lm3s6965-ek" # CONFIG_ARCH_HAVE_LEDS=y CONFIG_ARCH_LEDS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDSPIPORTNO=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -360,6 +361,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2010 CONFIG_START_MONTH=5 @@ -452,6 +454,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -467,21 +470,24 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set CONFIG_SPI_CALLBACK=y -# CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -489,7 +495,12 @@ CONFIG_SPI_CALLBACK=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -596,9 +607,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -612,6 +626,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -812,6 +827,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -849,6 +866,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -867,9 +885,9 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -898,10 +916,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -946,6 +963,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1025,13 +1043,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1049,6 +1067,9 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 +CONFIG_NSH_MMCSDSPIPORTNO=0 # # Configure Command Options @@ -1123,7 +1144,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -1134,6 +1155,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/lm3s6965-ek/tcpecho/defconfig b/configs/lm3s6965-ek/tcpecho/defconfig index 3829162ce4..69824a4a7c 100644 --- a/configs/lm3s6965-ek/tcpecho/defconfig +++ b/configs/lm3s6965-ek/tcpecho/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -331,6 +334,7 @@ CONFIG_ARCH_LEDS=y # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set # @@ -344,6 +348,7 @@ CONFIG_ARCH_LEDS=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2010 CONFIG_START_MONTH=5 @@ -436,6 +441,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 # CONFIG_DISABLE_POLL is not set CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -451,12 +457,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -464,7 +474,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -562,9 +577,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -578,6 +596,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -778,6 +797,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -815,6 +836,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -833,9 +855,9 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -864,10 +886,9 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -920,6 +941,7 @@ CONFIG_EXAMPLES_TCPECHO_NETMASK=0xffffff00 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -971,7 +993,7 @@ CONFIG_WEBCLIENT_TIMEOUT=10 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -981,6 +1003,7 @@ CONFIG_SYSTEM_READLINE=y CONFIG_READLINE_ECHO=y # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/lm3s8962-ek/nsh/defconfig b/configs/lm3s8962-ek/nsh/defconfig index ca57326f75..d4c79ab20e 100644 --- a/configs/lm3s8962-ek/nsh/defconfig +++ b/configs/lm3s8962-ek/nsh/defconfig @@ -64,10 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -338,13 +341,11 @@ CONFIG_ARCH_BOARD="lm3s8962-ek" # CONFIG_ARCH_HAVE_LEDS=y CONFIG_ARCH_LEDS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDSPIPORTNO=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -370,6 +371,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2010 CONFIG_START_MONTH=5 @@ -462,6 +464,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -477,21 +480,24 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set CONFIG_SPI_CALLBACK=y -# CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -499,7 +505,12 @@ CONFIG_SPI_CALLBACK=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -606,9 +617,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -622,6 +636,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -822,6 +837,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -859,6 +876,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -877,9 +895,9 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -908,10 +926,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -956,6 +973,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1035,13 +1053,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1059,6 +1077,9 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 +CONFIG_NSH_MMCSDSPIPORTNO=0 # # Configure Command Options @@ -1132,7 +1153,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -1143,6 +1164,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/lpcxpresso-lpc1768/dhcpd/defconfig b/configs/lpcxpresso-lpc1768/dhcpd/defconfig index 05f8641ee2..da0cb8af8c 100644 --- a/configs/lpcxpresso-lpc1768/dhcpd/defconfig +++ b/configs/lpcxpresso-lpc1768/dhcpd/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -144,7 +147,6 @@ CONFIG_ARMV7M_TOOLCHAIN_CODEREDL=y # CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set # CONFIG_ARMV7M_HAVE_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_LPC17_GPIOIRQ is not set # CONFIG_SERIAL_TERMIOS is not set # @@ -219,6 +221,7 @@ CONFIG_LPC17_UART3=y # # Serial driver options # +# CONFIG_LPC17_GPIOIRQ is not set # # Ethernet driver options @@ -230,6 +233,7 @@ CONFIG_NET_NRXDESC=13 # CONFIG_NET_WOL is not set # CONFIG_NET_HASH is not set # CONFIG_LPC17_MULTICAST is not set +CONFIG_LPC17_ETHERNET_HPWORK=y # # Architecture Options @@ -308,6 +312,7 @@ CONFIG_ARCH_LEDS=y # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set # @@ -326,6 +331,7 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2011 CONFIG_START_MONTH=4 @@ -410,6 +416,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -425,12 +432,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -438,7 +449,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -550,9 +566,12 @@ CONFIG_UART3_2STOP=0 # CONFIG_UART3_IFLOWCONTROL is not set # CONFIG_UART3_OFLOWCONTROL is not set # CONFIG_UART3_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -566,6 +585,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -740,6 +760,8 @@ CONFIG_NUNGET_CHARS=0 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -766,6 +788,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -784,9 +807,9 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set CONFIG_EXAMPLES_DHCPD=y CONFIG_EXAMPLES_DHCPD_NOMAC=y CONFIG_EXAMPLES_DHCPD_IPADDR=0x0a000001 @@ -817,10 +840,9 @@ CONFIG_EXAMPLES_DHCPD_NETMASK=0xffffff00 # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -861,6 +883,7 @@ CONFIG_EXAMPLES_DHCPD_NETMASK=0xffffff00 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -916,13 +939,14 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/lpcxpresso-lpc1768/nsh/defconfig b/configs/lpcxpresso-lpc1768/nsh/defconfig index 0d195735b9..1cf8e78fbb 100644 --- a/configs/lpcxpresso-lpc1768/nsh/defconfig +++ b/configs/lpcxpresso-lpc1768/nsh/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -144,7 +147,6 @@ CONFIG_ARMV7M_TOOLCHAIN_CODEREDL=y # CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set # CONFIG_ARMV7M_HAVE_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_LPC17_GPIOIRQ is not set # CONFIG_SERIAL_TERMIOS is not set # @@ -219,6 +221,7 @@ CONFIG_LPC17_SSP1=y # # Serial driver options # +# CONFIG_LPC17_GPIOIRQ is not set # # Ethernet driver options @@ -230,6 +233,7 @@ CONFIG_NET_NRXDESC=6 # CONFIG_NET_WOL is not set # CONFIG_NET_HASH is not set # CONFIG_LPC17_MULTICAST is not set +CONFIG_LPC17_ETHERNET_HPWORK=y # # Architecture Options @@ -304,13 +308,11 @@ CONFIG_ARCH_BOARD="lpcxpresso-lpc1768" # CONFIG_ARCH_HAVE_LEDS=y CONFIG_ARCH_LEDS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDSPIPORTNO=1 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -336,6 +338,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2011 CONFIG_START_MONTH=4 @@ -433,6 +436,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -448,21 +452,23 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set # CONFIG_SPI_EXCHANGE is not set # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -470,7 +476,12 @@ CONFIG_SPI=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -519,6 +530,7 @@ CONFIG_MTD=y # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -626,9 +638,12 @@ CONFIG_UART3_2STOP=0 # CONFIG_UART3_IFLOWCONTROL is not set # CONFIG_UART3_OFLOWCONTROL is not set # CONFIG_UART3_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -642,6 +657,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -842,6 +858,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -879,6 +897,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -897,9 +916,9 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -928,10 +947,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -977,6 +995,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1056,13 +1075,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1080,6 +1099,9 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 +CONFIG_NSH_MMCSDSPIPORTNO=1 # # Configure Command Options @@ -1153,7 +1175,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -1164,6 +1186,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/lpcxpresso-lpc1768/thttpd/defconfig b/configs/lpcxpresso-lpc1768/thttpd/defconfig index 000402cb54..d227462fbf 100644 --- a/configs/lpcxpresso-lpc1768/thttpd/defconfig +++ b/configs/lpcxpresso-lpc1768/thttpd/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -144,7 +147,6 @@ CONFIG_ARMV7M_TOOLCHAIN_CODEREDL=y # CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set # CONFIG_ARMV7M_HAVE_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_LPC17_GPIOIRQ is not set # CONFIG_SERIAL_TERMIOS is not set # @@ -219,6 +221,7 @@ CONFIG_LPC17_UART3=y # # Serial driver options # +# CONFIG_LPC17_GPIOIRQ is not set # # Ethernet driver options @@ -230,6 +233,7 @@ CONFIG_NET_NRXDESC=13 # CONFIG_NET_WOL is not set # CONFIG_NET_HASH is not set # CONFIG_LPC17_MULTICAST is not set +CONFIG_LPC17_ETHERNET_HPWORK=y # # Architecture Options @@ -327,6 +331,7 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2011 CONFIG_START_MONTH=4 @@ -427,12 +432,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -565,6 +574,7 @@ CONFIG_UART3_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -766,6 +776,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -812,6 +824,7 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CPUHOG is not set @@ -846,6 +859,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set @@ -894,6 +908,7 @@ CONFIG_EXAMPLES_THTTPD_NETMASK=0xffffff00 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -976,6 +991,7 @@ CONFIG_THTTPD_TILDE_MAP_NONE=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/moxa/nsh/defconfig b/configs/moxa/nsh/defconfig index 51db5ca2ff..3b7043c04e 100644 --- a/configs/moxa/nsh/defconfig +++ b/configs/moxa/nsh/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -198,19 +201,19 @@ CONFIG_RAM_SIZE=2097152 # # Board Selection # -# CONFIG_ARCH_BOARD_CUSTOM is not set CONFIG_ARCH_BOARD_MOXA=y +# CONFIG_ARCH_BOARD_CUSTOM is not set CONFIG_ARCH_BOARD="moxa" # # Common Board Options # -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # CONFIG_MOXA_NP51X0=y +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_RESET=y # CONFIG_BOARDCTL_UNIQUEID is not set @@ -236,6 +239,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2013 CONFIG_START_MONTH=6 @@ -338,6 +342,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 # CONFIG_DISABLE_POLL is not set CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -353,12 +358,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -366,7 +375,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -412,6 +426,7 @@ CONFIG_FTMAC100_IRQ=25 CONFIG_FTMAC100_RX_DESC=64 CONFIG_FTMAC100_TX_DESC=32 CONFIG_FTMAC100_MAC0_ENV_ADDR=0x80000050 +CONFIG_FTMAC100_HPWORK=y # CONFIG_NET_VNET is not set # CONFIG_PIPES is not set # CONFIG_PM is not set @@ -474,9 +489,12 @@ CONFIG_SERIAL_NPOLLWAITERS=2 # CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_SERIAL_DMA is not set CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -490,6 +508,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -686,6 +705,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -713,6 +734,7 @@ CONFIG_LIBC_NETDB=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -743,9 +765,9 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set @@ -774,9 +796,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set @@ -823,6 +845,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -897,12 +920,12 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_LS is not set # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -922,6 +945,7 @@ CONFIG_NSH_DISABLE_TIME=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -999,7 +1023,7 @@ CONFIG_NSH_LOGIN_FAILCOUNT=3 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -1010,6 +1034,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/ntosd-dm320/nettest/defconfig b/configs/ntosd-dm320/nettest/defconfig index 159babcd83..a9ee527115 100644 --- a/configs/ntosd-dm320/nettest/defconfig +++ b/configs/ntosd-dm320/nettest/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -219,6 +222,7 @@ CONFIG_ARCH_LEDS=y # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set # @@ -237,6 +241,7 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2008 CONFIG_START_MONTH=8 @@ -316,6 +321,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=4096 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -331,12 +337,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -344,7 +354,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -464,9 +479,12 @@ CONFIG_UART1_2STOP=0 # CONFIG_UART1_IFLOWCONTROL is not set # CONFIG_UART1_OFLOWCONTROL is not set # CONFIG_UART1_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -480,6 +498,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -660,6 +679,8 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -685,6 +706,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -703,9 +725,9 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set @@ -745,10 +767,9 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -788,6 +809,7 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -829,13 +851,14 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/ntosd-dm320/nsh/defconfig b/configs/ntosd-dm320/nsh/defconfig index f644a93ed9..845e806b36 100644 --- a/configs/ntosd-dm320/nsh/defconfig +++ b/configs/ntosd-dm320/nsh/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -215,12 +218,11 @@ CONFIG_ARCH_BOARD="ntosd-dm320" # CONFIG_ARCH_HAVE_LEDS=y # CONFIG_ARCH_LEDS is not set -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set # @@ -239,6 +241,7 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2008 CONFIG_START_MONTH=9 @@ -325,6 +328,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=4096 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -340,12 +344,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -353,7 +361,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -482,9 +495,12 @@ CONFIG_UART1_2STOP=0 # CONFIG_UART1_IFLOWCONTROL is not set # CONFIG_UART1_OFLOWCONTROL is not set # CONFIG_UART1_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -498,6 +514,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -698,6 +715,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -735,6 +754,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -753,9 +773,9 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -785,10 +805,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set @@ -835,6 +854,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -914,13 +934,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -938,6 +958,8 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 # # Configure Command Options @@ -1022,7 +1044,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -1033,6 +1055,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/ntosd-dm320/poll/defconfig b/configs/ntosd-dm320/poll/defconfig index 234bb13bb5..5b357b8182 100644 --- a/configs/ntosd-dm320/poll/defconfig +++ b/configs/ntosd-dm320/poll/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -238,6 +241,7 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2008 CONFIG_START_MONTH=11 @@ -340,12 +344,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -487,6 +495,7 @@ CONFIG_UART1_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -681,6 +690,8 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -725,6 +736,7 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CPUHOG is not set @@ -746,10 +758,10 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_NRF24L01TERM is not set # CONFIG_EXAMPLES_NSH is not set # CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set @@ -763,6 +775,7 @@ CONFIG_EXAMPLES_POLL_DRIPADDR=0x0a000001 CONFIG_EXAMPLES_POLL_NETMASK=0xffffff00 # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -803,6 +816,7 @@ CONFIG_EXAMPLES_POLL_NETMASK=0xffffff00 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -853,6 +867,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/ntosd-dm320/thttpd/defconfig b/configs/ntosd-dm320/thttpd/defconfig index 1c872a4200..991f4c1875 100644 --- a/configs/ntosd-dm320/thttpd/defconfig +++ b/configs/ntosd-dm320/thttpd/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -238,6 +241,7 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2009 CONFIG_START_MONTH=8 @@ -333,12 +337,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -480,6 +488,7 @@ CONFIG_UART1_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -682,6 +691,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -728,6 +739,7 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CPUHOG is not set @@ -763,6 +775,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set @@ -811,6 +824,7 @@ CONFIG_EXAMPLES_THTTPD_NETMASK=0xffffff00 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -893,6 +907,7 @@ CONFIG_THTTPD_TILDE_MAP_NONE=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/ntosd-dm320/udp/defconfig b/configs/ntosd-dm320/udp/defconfig index 94bf2ad1a3..6fe1d2e373 100644 --- a/configs/ntosd-dm320/udp/defconfig +++ b/configs/ntosd-dm320/udp/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -219,6 +222,7 @@ CONFIG_ARCH_HAVE_LEDS=y # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set # @@ -237,6 +241,7 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2008 CONFIG_START_MONTH=8 @@ -316,6 +321,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=4096 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -331,12 +337,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -344,7 +354,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -463,9 +478,12 @@ CONFIG_UART1_2STOP=0 # CONFIG_UART1_IFLOWCONTROL is not set # CONFIG_UART1_OFLOWCONTROL is not set # CONFIG_UART1_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -479,6 +497,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -654,6 +673,8 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -680,6 +701,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -698,9 +720,9 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -728,10 +750,9 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -782,6 +803,7 @@ CONFIG_EXAMPLES_UDP_SERVERIP=0x0a000001 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -825,13 +847,14 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/ntosd-dm320/webserver/defconfig b/configs/ntosd-dm320/webserver/defconfig index 298dcae040..789fc76a73 100644 --- a/configs/ntosd-dm320/webserver/defconfig +++ b/configs/ntosd-dm320/webserver/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -219,6 +222,7 @@ CONFIG_ARCH_HAVE_LEDS=y # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set # @@ -237,6 +241,7 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2008 CONFIG_START_MONTH=8 @@ -323,6 +328,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=4096 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -338,12 +344,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -351,7 +361,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -471,9 +486,12 @@ CONFIG_UART1_2STOP=0 # CONFIG_UART1_IFLOWCONTROL is not set # CONFIG_UART1_OFLOWCONTROL is not set # CONFIG_UART1_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -487,6 +505,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -667,6 +686,8 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -692,6 +713,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -710,9 +732,9 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set @@ -740,10 +762,9 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -787,6 +808,7 @@ CONFIG_EXAMPLES_WEBSERVER_NOMAC=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -839,13 +861,14 @@ CONFIG_NETUTILS_HTTPD_KEEPALIVE_DISABLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/olimex-lpc1766stk/ftpc/defconfig b/configs/olimex-lpc1766stk/ftpc/defconfig index 04950934e5..bae7aac56b 100644 --- a/configs/olimex-lpc1766stk/ftpc/defconfig +++ b/configs/olimex-lpc1766stk/ftpc/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -144,7 +147,6 @@ CONFIG_ARM_HAVE_MPU_UNIFIED=y CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y # CONFIG_ARMV7M_HAVE_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_LPC17_GPIOIRQ is not set # CONFIG_SERIAL_TERMIOS is not set # @@ -219,6 +221,7 @@ CONFIG_LPC17_SSP1=y # # Serial driver options # +# CONFIG_LPC17_GPIOIRQ is not set # # Ethernet driver options @@ -230,6 +233,7 @@ CONFIG_NET_NRXDESC=7 # CONFIG_NET_WOL is not set # CONFIG_NET_HASH is not set # CONFIG_LPC17_MULTICAST is not set +CONFIG_LPC17_ETHERNET_HPWORK=y # # Architecture Options @@ -304,13 +308,11 @@ CONFIG_ARCH_LEDS=y CONFIG_ARCH_HAVE_BUTTONS=y # CONFIG_ARCH_BUTTONS is not set CONFIG_ARCH_HAVE_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDSPIPORTNO=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -336,6 +338,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2011 CONFIG_START_MONTH=6 @@ -433,6 +436,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 # CONFIG_DISABLE_POLL is not set CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -448,21 +452,23 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set # CONFIG_SPI_EXCHANGE is not set # CONFIG_SPI_CMDDATA is not set CONFIG_SPI_CALLBACK=y -# CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -470,7 +476,12 @@ CONFIG_SPI_CALLBACK=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -594,9 +605,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -610,6 +624,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -812,6 +827,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -850,6 +867,7 @@ CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0a000001 # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -873,9 +891,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -905,9 +924,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -953,6 +972,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1034,13 +1054,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set CONFIG_NSH_DISABLE_PUT=y @@ -1058,6 +1078,9 @@ CONFIG_NSH_DISABLE_PUT=y # CONFIG_NSH_DISABLE_USLEEP is not set CONFIG_NSH_DISABLE_WGET=y # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 +CONFIG_NSH_MMCSDSPIPORTNO=0 # # Configure Command Options @@ -1120,7 +1143,7 @@ CONFIG_NSH_MAX_ROUNDTRIP=20 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -1131,6 +1154,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/olimex-lpc1766stk/hidmouse/defconfig b/configs/olimex-lpc1766stk/hidmouse/defconfig index 0eaf08eb62..31bc863951 100644 --- a/configs/olimex-lpc1766stk/hidmouse/defconfig +++ b/configs/olimex-lpc1766stk/hidmouse/defconfig @@ -64,10 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -152,7 +155,6 @@ CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y # CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE is not set # CONFIG_ARMV7M_HAVE_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_LPC17_GPIOIRQ is not set # CONFIG_SERIAL_TERMIOS is not set # @@ -227,6 +229,7 @@ CONFIG_LPC17_UART0=y # # Serial driver options # +# CONFIG_LPC17_GPIOIRQ is not set # # USB host driver options @@ -315,13 +318,13 @@ CONFIG_ARCH_LEDS=y CONFIG_ARCH_HAVE_BUTTONS=y # CONFIG_ARCH_BUTTONS is not set CONFIG_ARCH_HAVE_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # CONFIG_LPC1766STK_USBHOST_STACKSIZE=1024 CONFIG_LPC1766STK_USBHOST_PRIO=100 +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -347,6 +350,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2011 CONFIG_START_MONTH=12 @@ -444,6 +448,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -459,12 +464,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -482,7 +491,12 @@ CONFIG_MOUSE=y # CONFIG_BUTTONS is not set # CONFIG_DJOYSTICK is not set # CONFIG_AJOYSTICK is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -558,12 +572,14 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set CONFIG_USBHOST=y CONFIG_USBHOST_NPREALLOC=4 CONFIG_USBHOST_HAVE_ASYNCH=y # CONFIG_USBHOST_ASYNCH is not set # CONFIG_USBHOST_HUB is not set +# CONFIG_USBHOST_COMPOSITE is not set # CONFIG_USBHOST_MSC is not set # CONFIG_USBHOST_CDCACM is not set # CONFIG_USBHOST_HIDKBD is not set @@ -581,7 +597,9 @@ CONFIG_HIDMOUSE_XTHRESH=12 CONFIG_HIDMOUSE_THRESHY=12 # CONFIG_USBHOST_RTL8187 is not set # CONFIG_USBHOST_TRACE is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -595,6 +613,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -798,6 +817,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -835,6 +856,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -858,9 +880,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -890,9 +913,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -941,6 +964,7 @@ CONFIG_EXAMPLES_TOUCHSCREEN_ARCHINIT=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1021,13 +1045,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1045,6 +1069,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -1119,7 +1144,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -1130,6 +1155,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/olimex-lpc1766stk/nettest/defconfig b/configs/olimex-lpc1766stk/nettest/defconfig index c4f85cf1e7..2b676ed872 100644 --- a/configs/olimex-lpc1766stk/nettest/defconfig +++ b/configs/olimex-lpc1766stk/nettest/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -145,7 +148,6 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y # CONFIG_ARMV7M_HAVE_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_LPC17_GPIOIRQ is not set # CONFIG_SERIAL_TERMIOS is not set # @@ -220,6 +222,7 @@ CONFIG_LPC17_UART0=y # # Serial driver options # +# CONFIG_LPC17_GPIOIRQ is not set # # Ethernet driver options @@ -231,6 +234,7 @@ CONFIG_NET_NRXDESC=6 # CONFIG_NET_WOL is not set # CONFIG_NET_HASH is not set # CONFIG_LPC17_MULTICAST is not set +CONFIG_LPC17_ETHERNET_HPWORK=y # # Architecture Options @@ -309,6 +313,7 @@ CONFIG_ARCH_HAVE_IRQBUTTONS=y # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set # @@ -327,6 +332,7 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2010 CONFIG_START_MONTH=11 @@ -411,6 +417,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -426,12 +433,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -439,7 +450,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -551,9 +567,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -567,6 +586,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -746,6 +766,8 @@ CONFIG_NUNGET_CHARS=0 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -771,6 +793,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -789,9 +812,10 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set @@ -831,10 +855,9 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -874,6 +897,7 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -915,13 +939,14 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/olimex-lpc1766stk/nsh/defconfig b/configs/olimex-lpc1766stk/nsh/defconfig index 9aa1a88511..1a67e4f8a6 100644 --- a/configs/olimex-lpc1766stk/nsh/defconfig +++ b/configs/olimex-lpc1766stk/nsh/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -145,7 +148,6 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y # CONFIG_ARMV7M_HAVE_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_LPC17_GPIOIRQ is not set # CONFIG_SERIAL_TERMIOS is not set # @@ -220,6 +222,7 @@ CONFIG_LPC17_SSP1=y # # Serial driver options # +# CONFIG_LPC17_GPIOIRQ is not set # # Ethernet driver options @@ -231,6 +234,7 @@ CONFIG_NET_NRXDESC=6 # CONFIG_NET_WOL is not set # CONFIG_NET_HASH is not set # CONFIG_LPC17_MULTICAST is not set +CONFIG_LPC17_ETHERNET_HPWORK=y # # Architecture Options @@ -305,13 +309,11 @@ CONFIG_ARCH_LEDS=y CONFIG_ARCH_HAVE_BUTTONS=y # CONFIG_ARCH_BUTTONS is not set CONFIG_ARCH_HAVE_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDSPIPORTNO=1 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -337,6 +339,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2011 CONFIG_START_MONTH=12 @@ -434,6 +437,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -449,21 +453,23 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set # CONFIG_SPI_EXCHANGE is not set # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -471,7 +477,12 @@ CONFIG_SPI=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -596,9 +607,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -612,6 +626,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -815,6 +830,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -852,6 +869,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -875,9 +893,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -907,9 +926,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -954,6 +973,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1034,13 +1054,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1058,6 +1078,9 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 +CONFIG_NSH_MMCSDSPIPORTNO=1 # # Configure Command Options @@ -1132,7 +1155,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -1143,6 +1166,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/olimex-lpc1766stk/slip-httpd/defconfig b/configs/olimex-lpc1766stk/slip-httpd/defconfig index e9a7a04a08..006083964e 100644 --- a/configs/olimex-lpc1766stk/slip-httpd/defconfig +++ b/configs/olimex-lpc1766stk/slip-httpd/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -145,7 +148,6 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y # CONFIG_ARMV7M_OABI_TOOLCHAIN is not set # CONFIG_ARMV7M_HAVE_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_LPC17_GPIOIRQ is not set # CONFIG_SERIAL_TERMIOS is not set # @@ -221,6 +223,7 @@ CONFIG_LPC17_UART1=y # Serial driver options # # CONFIG_UART1_RINGINDICATOR is not set +# CONFIG_LPC17_GPIOIRQ is not set # # Architecture Options @@ -318,6 +321,7 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2010 CONFIG_START_MONTH=11 @@ -413,12 +417,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -529,6 +537,7 @@ CONFIG_UART1_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -728,6 +737,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -774,6 +785,8 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CPUHOG is not set @@ -808,6 +821,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set @@ -856,6 +870,7 @@ CONFIG_EXAMPLES_THTTPD_NETMASK=0xffffff00 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -938,6 +953,7 @@ CONFIG_THTTPD_TILDE_MAP_NONE=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/olimex-lpc1766stk/thttpd-binfs/defconfig b/configs/olimex-lpc1766stk/thttpd-binfs/defconfig index a9ad06ecdf..cb2b172f2b 100644 --- a/configs/olimex-lpc1766stk/thttpd-binfs/defconfig +++ b/configs/olimex-lpc1766stk/thttpd-binfs/defconfig @@ -64,10 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -152,7 +155,6 @@ CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y # CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE is not set # CONFIG_ARMV7M_HAVE_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_LPC17_GPIOIRQ is not set # CONFIG_SERIAL_TERMIOS is not set # @@ -227,6 +229,7 @@ CONFIG_LPC17_UART0=y # # Serial driver options # +# CONFIG_LPC17_GPIOIRQ is not set # # Ethernet driver options @@ -238,6 +241,7 @@ CONFIG_NET_NRXDESC=13 # CONFIG_NET_WOL is not set # CONFIG_NET_HASH is not set # CONFIG_LPC17_MULTICAST is not set +CONFIG_LPC17_ETHERNET_HPWORK=y # # Architecture Options @@ -335,6 +339,7 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2010 CONFIG_START_MONTH=11 @@ -435,12 +440,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -573,6 +582,7 @@ CONFIG_UART0_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -775,6 +785,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -826,6 +838,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CPUHOG is not set @@ -859,6 +873,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set @@ -907,6 +922,7 @@ CONFIG_EXAMPLES_THTTPD_NETMASK=0xffffff00 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -989,6 +1005,7 @@ CONFIG_THTTPD_TILDE_MAP_NONE=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig b/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig index b42ed3303e..e82d0807e5 100644 --- a/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig +++ b/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -145,7 +148,6 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y # CONFIG_ARMV7M_OABI_TOOLCHAIN is not set # CONFIG_ARMV7M_HAVE_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_LPC17_GPIOIRQ is not set # CONFIG_SERIAL_TERMIOS is not set # @@ -220,6 +222,7 @@ CONFIG_LPC17_UART0=y # # Serial driver options # +# CONFIG_LPC17_GPIOIRQ is not set # # Ethernet driver options @@ -231,6 +234,7 @@ CONFIG_NET_NRXDESC=13 # CONFIG_NET_WOL is not set # CONFIG_NET_HASH is not set # CONFIG_LPC17_MULTICAST is not set +CONFIG_LPC17_ETHERNET_HPWORK=y # # Architecture Options @@ -328,6 +332,7 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2010 CONFIG_START_MONTH=11 @@ -428,12 +433,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -566,6 +575,7 @@ CONFIG_UART0_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -767,6 +777,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -813,6 +825,8 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CPUHOG is not set @@ -847,6 +861,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set @@ -895,6 +910,7 @@ CONFIG_EXAMPLES_THTTPD_NETMASK=0xffffff00 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -977,6 +993,7 @@ CONFIG_THTTPD_TILDE_MAP_NONE=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/olimex-lpc1766stk/zmodem/defconfig b/configs/olimex-lpc1766stk/zmodem/defconfig index adbf9f981e..4540805469 100644 --- a/configs/olimex-lpc1766stk/zmodem/defconfig +++ b/configs/olimex-lpc1766stk/zmodem/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -145,7 +148,6 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y # CONFIG_ARMV7M_HAVE_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_LPC17_GPIOIRQ is not set # CONFIG_SERIAL_TERMIOS is not set # @@ -221,6 +223,7 @@ CONFIG_LPC17_SSP1=y # Serial driver options # # CONFIG_UART1_RINGINDICATOR is not set +# CONFIG_LPC17_GPIOIRQ is not set # # Ethernet driver options @@ -232,6 +235,7 @@ CONFIG_NET_NRXDESC=6 # CONFIG_NET_WOL is not set # CONFIG_NET_HASH is not set # CONFIG_LPC17_MULTICAST is not set +CONFIG_LPC17_ETHERNET_HPWORK=y # # Architecture Options @@ -306,13 +310,11 @@ CONFIG_ARCH_LEDS=y CONFIG_ARCH_HAVE_BUTTONS=y # CONFIG_ARCH_BUTTONS is not set CONFIG_ARCH_HAVE_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDSPIPORTNO=1 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -338,6 +340,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2011 CONFIG_START_MONTH=12 @@ -435,6 +438,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -450,21 +454,23 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set # CONFIG_SPI_EXCHANGE is not set # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -472,7 +478,12 @@ CONFIG_SPI=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -611,9 +622,12 @@ CONFIG_UART1_2STOP=0 # CONFIG_UART1_IFLOWCONTROL is not set # CONFIG_UART1_OFLOWCONTROL is not set # CONFIG_UART1_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -627,6 +641,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -830,6 +845,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -867,6 +884,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -890,9 +908,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -922,9 +941,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -969,6 +988,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1048,13 +1068,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1072,6 +1092,9 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 +CONFIG_NSH_MMCSDSPIPORTNO=1 # # Configure Command Options @@ -1145,7 +1168,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -1156,6 +1179,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set CONFIG_SYSTEM_ZMODEM=y diff --git a/configs/olimex-stm32-e407/discover/defconfig b/configs/olimex-stm32-e407/discover/defconfig index 681313aec8..ee655a6e3f 100644 --- a/configs/olimex-stm32-e407/discover/defconfig +++ b/configs/olimex-stm32-e407/discover/defconfig @@ -16,7 +16,7 @@ CONFIG_HOST_LINUX=y # # Build Configuration # -CONFIG_APPS_DIR="../apps" +# CONFIG_APPS_DIR="../apps" CONFIG_BUILD_FLAT=y # CONFIG_BUILD_2PASS is not set @@ -61,10 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -351,6 +354,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -718,14 +727,14 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -1078,6 +1087,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1131,10 +1142,6 @@ CONFIG_HAVE_CXXINITIALIZE=y # Application Configuration # -# -# NxWidgets/NxWM -# - # # Built-In Applications # @@ -1147,7 +1154,9 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1207,10 +1216,6 @@ CONFIG_EXAMPLES_DISCOVER_NETMASK=0xffffff00 # CONFIG_EXAMPLES_WGET is not set # CONFIG_EXAMPLES_XMLRPC is not set -# -# External -# - # # File System Utilities # @@ -1273,6 +1278,10 @@ CONFIG_NETUTILS_NETLIB=y # # CONFIG_NSH_LIBRARY is not set +# +# NxWidgets/NxWM +# + # # Platform-specific Support # diff --git a/configs/olimex-stm32-e407/netnsh/defconfig b/configs/olimex-stm32-e407/netnsh/defconfig index 4ee6b4b742..3e13c92c6d 100644 --- a/configs/olimex-stm32-e407/netnsh/defconfig +++ b/configs/olimex-stm32-e407/netnsh/defconfig @@ -16,7 +16,7 @@ CONFIG_HOST_LINUX=y # # Build Configuration # -CONFIG_APPS_DIR="../apps" +# CONFIG_APPS_DIR="../apps" CONFIG_BUILD_FLAT=y # CONFIG_BUILD_2PASS is not set @@ -61,10 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -351,6 +354,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -718,14 +727,14 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -1080,6 +1089,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1133,10 +1144,6 @@ CONFIG_HAVE_CXXINITIALIZE=y # Application Configuration # -# -# NxWidgets/NxWM -# - # # Built-In Applications # @@ -1149,7 +1156,9 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1206,10 +1215,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_WEBSERVER is not set # CONFIG_EXAMPLES_XMLRPC is not set -# -# External -# - # # File System Utilities # @@ -1323,6 +1328,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y CONFIG_NSH_DISABLE_PS=y # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1399,6 +1405,10 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_NSH_CONSOLE_LOGIN is not set # CONFIG_NSH_TELNET_LOGIN is not set +# +# NxWidgets/NxWM +# + # # Platform-specific Support # @@ -1426,4 +1436,4 @@ CONFIG_READLINE_ECHO=y # CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set -# CONFIG_SYSTEM_ZMODEM is not set \ No newline at end of file +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/olimex-stm32-e407/telnetd/defconfig b/configs/olimex-stm32-e407/telnetd/defconfig index 70071a6b4f..5e3a351669 100644 --- a/configs/olimex-stm32-e407/telnetd/defconfig +++ b/configs/olimex-stm32-e407/telnetd/defconfig @@ -16,7 +16,7 @@ CONFIG_HOST_LINUX=y # # Build Configuration # -CONFIG_APPS_DIR="../apps" +# CONFIG_APPS_DIR="../apps" CONFIG_BUILD_FLAT=y # CONFIG_BUILD_2PASS is not set @@ -61,10 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -351,6 +354,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -718,14 +727,14 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -1080,6 +1089,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1133,10 +1144,6 @@ CONFIG_HAVE_CXXINITIALIZE=y # Application Configuration # -# -# NxWidgets/NxWM -# - # # Built-In Applications # @@ -1149,7 +1156,9 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1213,10 +1222,6 @@ CONFIG_EXAMPLES_TELNETD_CLIENTSTACKSIZE=2048 # CONFIG_EXAMPLES_WGET is not set # CONFIG_EXAMPLES_XMLRPC is not set -# -# External -# - # # File System Utilities # @@ -1279,6 +1284,10 @@ CONFIG_NETUTILS_TELNETD=y # # CONFIG_NSH_LIBRARY is not set +# +# NxWidgets/NxWM +# + # # Platform-specific Support # @@ -1301,4 +1310,4 @@ CONFIG_NETUTILS_TELNETD=y # CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set -# CONFIG_SYSTEM_ZMODEM is not set \ No newline at end of file +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/olimex-stm32-e407/webserver/defconfig b/configs/olimex-stm32-e407/webserver/defconfig index 9ba20f2d5c..7ab0ac66f8 100644 --- a/configs/olimex-stm32-e407/webserver/defconfig +++ b/configs/olimex-stm32-e407/webserver/defconfig @@ -16,7 +16,7 @@ CONFIG_HOST_LINUX=y # # Build Configuration # -CONFIG_APPS_DIR="../apps" +# CONFIG_APPS_DIR="../apps" CONFIG_BUILD_FLAT=y # CONFIG_BUILD_2PASS is not set @@ -61,10 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -351,6 +354,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -718,14 +727,14 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -1078,6 +1087,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1131,10 +1142,6 @@ CONFIG_HAVE_CXXINITIALIZE=y # Application Configuration # -# -# NxWidgets/NxWM -# - # # Built-In Applications # @@ -1147,7 +1154,9 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1200,17 +1209,13 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_USBTERM is not set # CONFIG_EXAMPLES_WATCHDOG is not set CONFIG_EXAMPLES_WEBSERVER=y -CONFIG_EXAMPLES_WEBSERVER_DHCPC=y +CONFIG_EXAMPLES_WEBSERVER_IPADDR=0x0a000002 CONFIG_EXAMPLES_WEBSERVER_DRIPADDR=0xc0a80101 CONFIG_EXAMPLES_WEBSERVER_NETMASK=0xffffff00 CONFIG_EXAMPLES_WEBSERVER_NOMAC=y # CONFIG_EXAMPLES_WGET is not set # CONFIG_EXAMPLES_XMLRPC is not set -# -# External -# - # # File System Utilities # @@ -1284,6 +1289,10 @@ CONFIG_NETUTILS_HTTPD_KEEPALIVE_DISABLE=y # # CONFIG_NSH_LIBRARY is not set +# +# NxWidgets/NxWM +# + # # Platform-specific Support # diff --git a/configs/olimex-stm32-p107/nsh/defconfig b/configs/olimex-stm32-p107/nsh/defconfig index 8b12ab0d32..210607d988 100644 --- a/configs/olimex-stm32-p107/nsh/defconfig +++ b/configs/olimex-stm32-p107/nsh/defconfig @@ -61,10 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -351,6 +354,12 @@ CONFIG_STM32_HAVE_ADC2=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -383,6 +392,7 @@ CONFIG_STM32_PWR=y # CONFIG_STM32_SPI1 is not set # CONFIG_STM32_SPI2 is not set # CONFIG_STM32_SPI3 is not set +CONFIG_STM32_SYSCFG=y # CONFIG_STM32_TIM1 is not set # CONFIG_STM32_TIM2 is not set # CONFIG_STM32_TIM3 is not set @@ -462,6 +472,7 @@ CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 CONFIG_STM32_RMII=y CONFIG_STM32_RMII_MCO=y # CONFIG_STM32_RMII_EXTCLK is not set +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -543,6 +554,7 @@ CONFIG_RAM_SIZE=65536 # CONFIG_ARCH_BOARD_CLOUDCTRL is not set CONFIG_ARCH_BOARD_OLIMEX_STM32P107=y # CONFIG_ARCH_BOARD_SHENZHOU is not set +# CONFIG_ARCH_BOARD_STM32_BUTTERFLY2 is not set # CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107 is not set # CONFIG_ARCH_BOARD_CUSTOM is not set CONFIG_ARCH_BOARD="olimex-stm32-p107" @@ -695,6 +707,8 @@ CONFIG_CAN_NPOLLWAITERS=2 CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -702,6 +716,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -759,6 +774,7 @@ CONFIG_MTD=y # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -869,6 +885,7 @@ CONFIG_USART2_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1078,6 +1095,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1136,6 +1155,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1211,6 +1231,7 @@ CONFIG_EXAMPLES_NSH=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1297,6 +1318,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1390,6 +1412,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/olimex-stm32-p207/nsh/defconfig b/configs/olimex-stm32-p207/nsh/defconfig index 3337b0d0b4..caa647b50d 100644 --- a/configs/olimex-stm32-p207/nsh/defconfig +++ b/configs/olimex-stm32-p207/nsh/defconfig @@ -61,11 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -359,6 +361,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -509,6 +517,7 @@ CONFIG_STM32_RMII=y # CONFIG_STM32_RMII_MCO1 is not set # CONFIG_STM32_RMII_MCO2 is not set CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -762,6 +771,8 @@ CONFIG_CAN_NPENDINGRTR=4 CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -1215,6 +1226,7 @@ CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CAN is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set diff --git a/configs/olimex-strp711/nettest/defconfig b/configs/olimex-strp711/nettest/defconfig index 71fdbf653a..631f41fc69 100644 --- a/configs/olimex-strp711/nettest/defconfig +++ b/configs/olimex-strp711/nettest/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -247,6 +250,7 @@ CONFIG_ARCH_BUTTONS=y # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set # @@ -265,6 +269,7 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2010 CONFIG_START_MONTH=5 @@ -362,6 +367,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -377,21 +383,23 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set # CONFIG_SPI_EXCHANGE is not set # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -399,7 +407,12 @@ CONFIG_SPI=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -438,6 +451,7 @@ CONFIG_ENC28J60=y CONFIG_ENC28J60_NINTERFACES=1 CONFIG_ENC28J60_SPIMODE=0 CONFIG_ENC28J60_FREQUENCY=20000000 +CONFIG_ENC28J60_HPWORK=y # CONFIG_ENC28J60_HALFDUPPLEX is not set # CONFIG_ENC28J60_DUMPPACKET is not set # CONFIG_ENCX24J600 is not set @@ -512,9 +526,12 @@ CONFIG_UART1_2STOP=0 # CONFIG_UART1_IFLOWCONTROL is not set # CONFIG_UART1_OFLOWCONTROL is not set # CONFIG_UART1_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -528,6 +545,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -708,6 +726,8 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -733,6 +753,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -751,10 +772,11 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set @@ -794,10 +816,9 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -837,6 +858,7 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -878,13 +900,14 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/pic32mx-starterkit/nsh2/defconfig b/configs/pic32mx-starterkit/nsh2/defconfig index 904b4f4a44..ec259a462b 100644 --- a/configs/pic32mx-starterkit/nsh2/defconfig +++ b/configs/pic32mx-starterkit/nsh2/defconfig @@ -63,10 +63,13 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set CONFIG_ARCH_MIPS=y +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="mips" @@ -329,8 +332,6 @@ CONFIG_RAM_SIZE=131072 CONFIG_ARCH_BOARD_PIC32MX_STARTERKIT=y # CONFIG_ARCH_BOARD_PIC32MX7MMB is not set # CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD_CUSTOM_DIR="configs/dummy" -CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y CONFIG_ARCH_BOARD="pic32mx-starterkit" # @@ -367,6 +368,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2012 CONFIG_START_MONTH=3 @@ -459,6 +461,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 # CONFIG_DISABLE_POLL is not set CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -474,12 +477,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -538,6 +545,7 @@ CONFIG_MTD=y # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -628,9 +636,12 @@ CONFIG_SERIAL=y # CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_SERIAL_DMA is not set CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -651,6 +662,7 @@ CONFIG_RAMLOG_SYSLOG=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set # CONFIG_CONSOLE_SYSLOG is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -853,6 +865,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -889,6 +903,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -912,9 +927,9 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -943,9 +958,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -992,6 +1007,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1074,13 +1090,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1172,7 +1188,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -1183,6 +1199,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/pic32mx7mmb/nsh/defconfig b/configs/pic32mx7mmb/nsh/defconfig index e7f5103e13..716e0a9e8b 100644 --- a/configs/pic32mx7mmb/nsh/defconfig +++ b/configs/pic32mx7mmb/nsh/defconfig @@ -63,10 +63,13 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set CONFIG_ARCH_MIPS=y +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="mips" @@ -337,8 +340,6 @@ CONFIG_RAM_SIZE=131072 # CONFIG_ARCH_BOARD_PIC32MX_STARTERKIT is not set CONFIG_ARCH_BOARD_PIC32MX7MMB=y # CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD_CUSTOM_DIR="configs/dummy" -CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y CONFIG_ARCH_BOARD="pic32mx7mmb" # @@ -376,6 +377,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2012 CONFIG_START_MONTH=6 @@ -468,6 +470,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -483,21 +486,23 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set # CONFIG_SPI_EXCHANGE is not set # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -559,6 +564,7 @@ CONFIG_MTD=y # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -665,6 +671,7 @@ CONFIG_UART1_2STOP=0 # CONFIG_UART1_IFLOWCONTROL is not set # CONFIG_UART1_OFLOWCONTROL is not set # CONFIG_UART1_DMA is not set +# CONFIG_PSEUDOTERM is not set CONFIG_USBDEV=y # @@ -702,7 +709,9 @@ CONFIG_USBMSC_REMOVABLE=y CONFIG_USBMSC_SCSI_PRIO=128 CONFIG_USBMSC_SCSI_STACKSIZE=2048 # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -716,6 +725,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -918,6 +928,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -954,6 +966,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -977,9 +990,9 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -1008,9 +1021,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -1056,6 +1069,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1136,13 +1150,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1235,7 +1249,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -1246,6 +1260,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set CONFIG_SYSTEM_USBMSC=y CONFIG_SYSTEM_USBMSC_NLUNS=1 diff --git a/configs/sam4e-ek/nsh/defconfig b/configs/sam4e-ek/nsh/defconfig index 2ca0505f83..ed3f03c24b 100644 --- a/configs/sam4e-ek/nsh/defconfig +++ b/configs/sam4e-ek/nsh/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -290,6 +293,7 @@ CONFIG_SAM34_EMAC_PHYSR_100HD=0x2 CONFIG_SAM34_EMAC_PHYSR_10FD=0x5 CONFIG_SAM34_EMAC_PHYSR_100FD=0x6 CONFIG_SAM34_EMAC_ISETH0=y +CONFIG_SAM34_EMAC_HPWORK=y # CONFIG_SAM34_TC is not set # @@ -367,7 +371,6 @@ CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_HAVE_IRQBUTTONS=y # CONFIG_ARCH_IRQBUTTONS is not set -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options @@ -376,6 +379,7 @@ CONFIG_NSH_MMCSDMINOR=0 CONFIG_SAM4EEK_120MHZ=y CONFIG_SAM4EEK_AT25_BLOCKMOUNT=y CONFIG_SAM4EEK_AT25_FTL=y +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -401,6 +405,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2014 CONFIG_START_MONTH=3 @@ -498,6 +503,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -513,21 +519,24 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -535,7 +544,12 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -576,6 +590,7 @@ CONFIG_AT25_SPIFREQUENCY=20000000 # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -696,9 +711,12 @@ CONFIG_USART1_2STOP=0 # CONFIG_USART1_IFLOWCONTROL is not set # CONFIG_USART1_OFLOWCONTROL is not set # CONFIG_USART1_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -712,6 +730,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -917,6 +936,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -954,6 +975,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -977,10 +999,11 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -1009,9 +1032,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -1057,6 +1080,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1137,13 +1161,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1161,6 +1185,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -1235,7 +1260,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -1246,6 +1271,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sam4e-ek/nxwm/defconfig b/configs/sam4e-ek/nxwm/defconfig index c80b0d0354..3d8dd79bb0 100644 --- a/configs/sam4e-ek/nxwm/defconfig +++ b/configs/sam4e-ek/nxwm/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -296,6 +299,7 @@ CONFIG_SAM34_EMAC_PHYSR_100HD=0x2 CONFIG_SAM34_EMAC_PHYSR_10FD=0x5 CONFIG_SAM34_EMAC_PHYSR_100FD=0x6 CONFIG_SAM34_EMAC_ISETH0=y +CONFIG_SAM34_EMAC_HPWORK=y # CONFIG_SAM34_TC is not set # @@ -373,7 +377,6 @@ CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_HAVE_IRQBUTTONS=y # CONFIG_ARCH_IRQBUTTONS is not set -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options @@ -388,6 +391,7 @@ CONFIG_SAM4EEK_LCD_RGB565=y # CONFIG_SAM4EEK_LCD_RGB24 is not set # CONFIG_SAM4EEK_LCD_RGB32 is not set CONFIG_SAM4EEK_LCD_BGCOLOR=0x95fa +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -408,6 +412,7 @@ CONFIG_LIB_BOARDCTL=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2014 CONFIG_START_MONTH=3 @@ -508,6 +513,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=1024 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -523,21 +529,24 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -562,7 +571,12 @@ CONFIG_ADS7843E_THRESHY=39 # CONFIG_BUTTONS is not set # CONFIG_DJOYSTICK is not set # CONFIG_AJOYSTICK is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -585,6 +599,7 @@ CONFIG_LCD_MAXPOWER=64 # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set # CONFIG_LCD_UG9664HSWAG01 is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -634,6 +649,7 @@ CONFIG_AT25_SPIFREQUENCY=20000000 # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -754,9 +770,12 @@ CONFIG_USART1_2STOP=0 # CONFIG_USART1_IFLOWCONTROL is not set # CONFIG_USART1_OFLOWCONTROL is not set # CONFIG_USART1_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -770,6 +789,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -1081,6 +1101,8 @@ CONFIG_LIBM=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1118,6 +1140,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -1148,10 +1171,11 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set @@ -1183,9 +1207,9 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -1231,6 +1255,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1311,13 +1336,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1335,6 +1360,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -1588,7 +1614,7 @@ CONFIG_NXWM_HEXCALCULATOR_FONTID=5 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -1599,6 +1625,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sam4e-ek/usbnsh/defconfig b/configs/sam4e-ek/usbnsh/defconfig index 2eb66473b9..b96a1ca08a 100644 --- a/configs/sam4e-ek/usbnsh/defconfig +++ b/configs/sam4e-ek/usbnsh/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -372,7 +375,6 @@ CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_HAVE_IRQBUTTONS=y # CONFIG_ARCH_IRQBUTTONS is not set -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options @@ -381,6 +383,7 @@ CONFIG_NSH_MMCSDMINOR=0 CONFIG_SAM4EEK_120MHZ=y CONFIG_SAM4EEK_AT25_BLOCKMOUNT=y CONFIG_SAM4EEK_AT25_FTL=y +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -407,6 +410,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2014 CONFIG_START_MONTH=3 @@ -499,6 +503,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -514,21 +519,24 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -536,7 +544,12 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -577,6 +590,7 @@ CONFIG_AT25_SPIFREQUENCY=20000000 # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -696,6 +710,7 @@ CONFIG_USART1_2STOP=0 # CONFIG_USART1_IFLOWCONTROL is not set # CONFIG_USART1_OFLOWCONTROL is not set # CONFIG_USART1_DMA is not set +# CONFIG_PSEUDOTERM is not set CONFIG_USBDEV=y # @@ -738,7 +753,9 @@ CONFIG_CDCACM_VENDORSTR="NuttX" CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial" # CONFIG_USBMSC is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -753,6 +770,7 @@ CONFIG_SYSLOG_CHAR=y # CONFIG_SYSLOG_FILE is not set CONFIG_SYSLOG_CHAR_CRLF=y CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -955,6 +973,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -992,6 +1012,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -1015,10 +1036,11 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -1047,9 +1069,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -1095,6 +1117,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1175,13 +1198,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1199,6 +1222,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -1275,7 +1299,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -1286,6 +1310,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sama5d3-xplained/bridge/defconfig b/configs/sama5d3-xplained/bridge/defconfig index 638a12e58e..fe883173cf 100644 --- a/configs/sama5d3-xplained/bridge/defconfig +++ b/configs/sama5d3-xplained/bridge/defconfig @@ -64,10 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -403,6 +406,7 @@ CONFIG_ARCH_HAVE_IRQBUTTONS=y CONFIG_SAMA5D3XPLAINED_396MHZ=y # CONFIG_SAMA5D3XPLAINED_528MHZ is not set # CONFIG_SAMA5D3XPLAINED_SLOWCLOCK is not set +# CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set # @@ -423,6 +427,7 @@ CONFIG_ARCH_HAVE_TICKLESS=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2014 CONFIG_START_MONTH=11 @@ -515,6 +520,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 # CONFIG_DISABLE_POLL is not set CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -530,12 +536,16 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -543,7 +553,12 @@ CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -652,9 +667,12 @@ CONFIG_SERIAL_NPOLLWAITERS=2 # CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set CONFIG_OTHER_SERIAL_CONSOLE=y # CONFIG_NO_SERIAL_CONSOLE is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -668,6 +686,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -860,6 +879,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -890,6 +911,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -955,9 +977,10 @@ CONFIG_EXAMPLES_BRIDGE_NET2_IPHOST=0x0a000001 CONFIG_EXAMPLES_BRIDGE_NET2_HOSTPORT=5472 CONFIG_EXAMPLES_BRIDGE_NET2_STACKSIZE=2048 CONFIG_EXAMPLES_BRIDGE_NET2_PRIORITY=100 +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set @@ -987,10 +1010,9 @@ CONFIG_EXAMPLES_BRIDGE_NET2_PRIORITY=100 # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -1033,6 +1055,7 @@ CONFIG_EXAMPLES_BRIDGE_NET2_PRIORITY=100 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1077,7 +1100,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set CONFIG_SYSTEM_RAMTEST=y @@ -1087,6 +1110,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sama5d4-ek/bridge/defconfig b/configs/sama5d4-ek/bridge/defconfig index 3df740b877..2fe78fac24 100644 --- a/configs/sama5d4-ek/bridge/defconfig +++ b/configs/sama5d4-ek/bridge/defconfig @@ -64,10 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -422,6 +425,7 @@ CONFIG_SAMA5D4_MB_REVE=y CONFIG_SAMA5D4EK_528MHZ=y CONFIG_SAMA5D4EK_DRAM_BOOT=y # CONFIG_SAMA5D4EK_SLOWCLOCK is not set +# CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set # @@ -442,6 +446,7 @@ CONFIG_ARCH_HAVE_TICKLESS=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2014 CONFIG_START_MONTH=11 @@ -534,6 +539,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 # CONFIG_DISABLE_POLL is not set CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -549,12 +555,16 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -562,7 +572,12 @@ CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -685,9 +700,12 @@ CONFIG_USART3_2STOP=0 # CONFIG_USART3_IFLOWCONTROL is not set # CONFIG_USART3_OFLOWCONTROL is not set # CONFIG_USART3_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -701,6 +719,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -893,6 +912,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -923,6 +944,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -988,9 +1010,10 @@ CONFIG_EXAMPLES_BRIDGE_NET2_IPHOST=0x0a000001 CONFIG_EXAMPLES_BRIDGE_NET2_HOSTPORT=5474 CONFIG_EXAMPLES_BRIDGE_NET2_STACKSIZE=2048 CONFIG_EXAMPLES_BRIDGE_NET2_PRIORITY=100 +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set @@ -1020,10 +1043,9 @@ CONFIG_EXAMPLES_BRIDGE_NET2_PRIORITY=100 # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -1066,6 +1088,7 @@ CONFIG_EXAMPLES_BRIDGE_NET2_PRIORITY=100 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1110,7 +1133,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set CONFIG_SYSTEM_RAMTEST=y @@ -1120,6 +1143,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sama5d4-ek/ipv6/defconfig b/configs/sama5d4-ek/ipv6/defconfig index 1e0f9b6ba6..c60fca0843 100644 --- a/configs/sama5d4-ek/ipv6/defconfig +++ b/configs/sama5d4-ek/ipv6/defconfig @@ -64,11 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -343,6 +345,7 @@ CONFIG_SAMA5_EMAC0_PHYSR_10FD=0x5 CONFIG_SAMA5_EMAC0_PHYSR_100FD=0x6 # CONFIG_SAMA5_EMACB_PREALLOCATE is not set # CONFIG_SAMA5_EMACB_NBC is not set +CONFIG_SAMA5_EMACB_HPWORK=y CONFIG_SAMA5_EMAC0_ISETH0=y # @@ -664,6 +667,9 @@ CONFIG_I2C_RESET=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set CONFIG_I2S=y # @@ -1306,6 +1312,7 @@ CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set diff --git a/configs/sama5d4-ek/nsh/defconfig b/configs/sama5d4-ek/nsh/defconfig index 32fefdc17d..446b2d3dfd 100644 --- a/configs/sama5d4-ek/nsh/defconfig +++ b/configs/sama5d4-ek/nsh/defconfig @@ -64,11 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -343,6 +345,7 @@ CONFIG_SAMA5_EMAC0_PHYSR_10FD=0x5 CONFIG_SAMA5_EMAC0_PHYSR_100FD=0x6 # CONFIG_SAMA5_EMACB_PREALLOCATE is not set # CONFIG_SAMA5_EMACB_NBC is not set +CONFIG_SAMA5_EMACB_HPWORK=y CONFIG_SAMA5_EMAC0_ISETH0=y # @@ -664,6 +667,9 @@ CONFIG_I2C_RESET=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set CONFIG_I2S=y # @@ -1317,6 +1323,7 @@ CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set diff --git a/configs/sama5d4-ek/nxwm/defconfig b/configs/sama5d4-ek/nxwm/defconfig index d8ca33141b..907dd01ff8 100644 --- a/configs/sama5d4-ek/nxwm/defconfig +++ b/configs/sama5d4-ek/nxwm/defconfig @@ -64,11 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -343,6 +345,7 @@ CONFIG_SAMA5_EMAC0_PHYSR_10FD=0x5 CONFIG_SAMA5_EMAC0_PHYSR_100FD=0x6 # CONFIG_SAMA5_EMACB_PREALLOCATE is not set # CONFIG_SAMA5_EMACB_NBC is not set +CONFIG_SAMA5_EMACB_HPWORK=y CONFIG_SAMA5_EMAC0_ISETH0=y # @@ -638,6 +641,9 @@ CONFIG_I2C_RESET=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # @@ -1305,6 +1311,7 @@ CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set diff --git a/configs/same70-xplained/netnsh/defconfig b/configs/same70-xplained/netnsh/defconfig index c173e39bfe..70c8117a63 100644 --- a/configs/same70-xplained/netnsh/defconfig +++ b/configs/same70-xplained/netnsh/defconfig @@ -64,11 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -313,6 +315,7 @@ CONFIG_SAMV7_EMAC0_PHYSR_100FD=0x6 CONFIG_SAMV7_EMAC0_ISETH0=y # CONFIG_SAMV7_EMAC_PREALLOCATE is not set # CONFIG_SAMV7_EMAC_NBC is not set +CONFIG_SAMV7_EMAC_HPWORK=y # # Architecture Options @@ -539,15 +542,15 @@ CONFIG_I2C=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y # CONFIG_SPI_CS_CONTROL is not set -# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set # CONFIG_SPI_BITBANG is not set @@ -1052,6 +1055,7 @@ CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set diff --git a/configs/samv71-xult/netnsh/defconfig b/configs/samv71-xult/netnsh/defconfig index a348cbc087..4cdc68ea28 100644 --- a/configs/samv71-xult/netnsh/defconfig +++ b/configs/samv71-xult/netnsh/defconfig @@ -65,11 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -315,6 +317,7 @@ CONFIG_SAMV7_EMAC0_PHYSR_100FD=0x6 CONFIG_SAMV7_EMAC0_ISETH0=y # CONFIG_SAMV7_EMAC_PREALLOCATE is not set # CONFIG_SAMV7_EMAC_NBC is not set +CONFIG_SAMV7_EMAC_HPWORK=y # # Architecture Options @@ -542,15 +545,15 @@ CONFIG_I2C=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y # CONFIG_SPI_CS_CONTROL is not set -# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set # CONFIG_SPI_BITBANG is not set @@ -1056,6 +1059,7 @@ CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set diff --git a/configs/samv71-xult/vnc/defconfig b/configs/samv71-xult/vnc/defconfig index 3c964dfae6..c956688f1c 100644 --- a/configs/samv71-xult/vnc/defconfig +++ b/configs/samv71-xult/vnc/defconfig @@ -64,10 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -195,7 +198,8 @@ CONFIG_ARCH_CHIP_SAMV71Q=y # CONFIG_ARCH_CHIP_SAMV71J is not set # CONFIG_SAMV7_MCAN is not set CONFIG_SAMV7_HAVE_MCAN1=y -CONFIG_SAMV7_HAVE_DAC1=y +# CONFIG_SAMV7_DAC is not set +# CONFIG_SAMV7_HAVE_DAC1 is not set CONFIG_SAMV7_HAVE_EBI=y CONFIG_SAMV7_EMAC=y CONFIG_SAMV7_HSMCI=y @@ -228,7 +232,6 @@ CONFIG_SAMV7_HAVE_USART2=y # CONFIG_SAMV7_MCAN0 is not set # CONFIG_SAMV7_MCAN1 is not set # CONFIG_SAMV7_DAC0 is not set -# CONFIG_SAMV7_DAC1 is not set # CONFIG_SAMV7_EBI is not set CONFIG_SAMV7_EMAC0=y CONFIG_SAMV7_XDMAC=y @@ -313,6 +316,7 @@ CONFIG_SAMV7_EMAC0_PHYSR_100FD=0x6 CONFIG_SAMV7_EMAC0_ISETH0=y # CONFIG_SAMV7_EMAC_PREALLOCATE is not set # CONFIG_SAMV7_EMAC_NBC is not set +CONFIG_SAMV7_EMAC_HPWORK=y # # Architecture Options @@ -541,15 +545,15 @@ CONFIG_I2C=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y # CONFIG_SPI_CS_CONTROL is not set -# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set # CONFIG_SPI_BITBANG is not set @@ -559,6 +563,7 @@ CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_TIMERS_CS2100CP is not set @@ -633,6 +638,7 @@ CONFIG_AT25_SPIFREQUENCY=20000000 # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -746,6 +752,7 @@ CONFIG_UART3_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1075,6 +1082,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1128,7 +1137,9 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1216,6 +1227,7 @@ CONFIG_EXAMPLES_NXIMAGE_YSCALE1p0=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1297,6 +1309,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1403,6 +1416,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/samv71-xult/vnxwm/defconfig b/configs/samv71-xult/vnxwm/defconfig index 8873901199..c5f417361a 100644 --- a/configs/samv71-xult/vnxwm/defconfig +++ b/configs/samv71-xult/vnxwm/defconfig @@ -64,10 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -195,7 +198,8 @@ CONFIG_ARCH_CHIP_SAMV71Q=y # CONFIG_ARCH_CHIP_SAMV71J is not set # CONFIG_SAMV7_MCAN is not set CONFIG_SAMV7_HAVE_MCAN1=y -CONFIG_SAMV7_HAVE_DAC1=y +# CONFIG_SAMV7_DAC is not set +# CONFIG_SAMV7_HAVE_DAC1 is not set CONFIG_SAMV7_HAVE_EBI=y CONFIG_SAMV7_EMAC=y CONFIG_SAMV7_HSMCI=y @@ -228,7 +232,6 @@ CONFIG_SAMV7_HAVE_USART2=y # CONFIG_SAMV7_MCAN0 is not set # CONFIG_SAMV7_MCAN1 is not set # CONFIG_SAMV7_DAC0 is not set -# CONFIG_SAMV7_DAC1 is not set # CONFIG_SAMV7_EBI is not set CONFIG_SAMV7_EMAC0=y CONFIG_SAMV7_XDMAC=y @@ -313,6 +316,7 @@ CONFIG_SAMV7_EMAC0_PHYSR_100FD=0x6 CONFIG_SAMV7_EMAC0_ISETH0=y # CONFIG_SAMV7_EMAC_PREALLOCATE is not set # CONFIG_SAMV7_EMAC_NBC is not set +CONFIG_SAMV7_EMAC_HPWORK=y # # Architecture Options @@ -544,15 +548,15 @@ CONFIG_I2C=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y # CONFIG_SPI_CS_CONTROL is not set -# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set # CONFIG_SPI_BITBANG is not set @@ -562,6 +566,7 @@ CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_TIMERS_CS2100CP is not set @@ -636,6 +641,7 @@ CONFIG_AT25_SPIFREQUENCY=20000000 # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -749,6 +755,7 @@ CONFIG_UART3_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1099,6 +1106,8 @@ CONFIG_LIBM=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1159,7 +1168,9 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1237,6 +1248,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1318,6 +1330,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1594,6 +1607,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/shenzhou/nsh/defconfig b/configs/shenzhou/nsh/defconfig index 4bd50cd1cd..1e440b536d 100644 --- a/configs/shenzhou/nsh/defconfig +++ b/configs/shenzhou/nsh/defconfig @@ -61,10 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -349,6 +352,12 @@ CONFIG_STM32_HAVE_ADC2=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -381,6 +390,7 @@ CONFIG_STM32_PWR=y CONFIG_STM32_SPI1=y # CONFIG_STM32_SPI2 is not set # CONFIG_STM32_SPI3 is not set +CONFIG_STM32_SYSCFG=y # CONFIG_STM32_TIM1 is not set # CONFIG_STM32_TIM2 is not set # CONFIG_STM32_TIM3 is not set @@ -553,6 +563,7 @@ CONFIG_RAM_SIZE=65536 # CONFIG_ARCH_BOARD_CLOUDCTRL is not set # CONFIG_ARCH_BOARD_OLIMEX_STM32P107 is not set CONFIG_ARCH_BOARD_SHENZHOU=y +# CONFIG_ARCH_BOARD_STM32_BUTTERFLY2 is not set # CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107 is not set # CONFIG_ARCH_BOARD_CUSTOM is not set CONFIG_ARCH_BOARD="shenzhou" @@ -703,14 +714,14 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -721,6 +732,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y # CONFIG_RTC_DATETIME is not set # CONFIG_RTC_HIRES is not set @@ -868,6 +880,7 @@ CONFIG_USART2_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1084,6 +1097,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1152,6 +1167,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1231,6 +1248,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1316,6 +1334,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1420,6 +1439,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/shenzhou/nxwm/defconfig b/configs/shenzhou/nxwm/defconfig index 27534c56c0..c785575fd7 100644 --- a/configs/shenzhou/nxwm/defconfig +++ b/configs/shenzhou/nxwm/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -357,6 +360,12 @@ CONFIG_STM32_HAVE_ADC2=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -389,6 +398,7 @@ CONFIG_STM32_ETHMAC=y # CONFIG_STM32_SPI1 is not set # CONFIG_STM32_SPI2 is not set CONFIG_STM32_SPI3=y +CONFIG_STM32_SYSCFG=y # CONFIG_STM32_TIM1 is not set # CONFIG_STM32_TIM2 is not set # CONFIG_STM32_TIM3 is not set @@ -477,6 +487,7 @@ CONFIG_STM32_PHYSR_100FD=0x8000 CONFIG_STM32_RMII=y CONFIG_STM32_RMII_MCO=y # CONFIG_STM32_RMII_EXTCLK is not set +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -558,6 +569,7 @@ CONFIG_RAM_SIZE=65536 # CONFIG_ARCH_BOARD_CLOUDCTRL is not set # CONFIG_ARCH_BOARD_OLIMEX_STM32P107 is not set CONFIG_ARCH_BOARD_SHENZHOU=y +# CONFIG_ARCH_BOARD_STM32_BUTTERFLY2 is not set # CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107 is not set # CONFIG_ARCH_BOARD_CUSTOM is not set CONFIG_ARCH_BOARD="shenzhou" @@ -733,14 +745,14 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -751,6 +763,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -803,6 +816,7 @@ CONFIG_LCD_MAXPOWER=1 # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set # CONFIG_LCD_UG9664HSWAG01 is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -934,6 +948,7 @@ CONFIG_USART2_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1252,6 +1267,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1311,6 +1328,8 @@ CONFIG_HAVE_CXXINITIALIZE=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1388,6 +1407,7 @@ CONFIG_HAVE_CXXINITIALIZE=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1471,6 +1491,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1746,6 +1767,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/shenzhou/thttpd/defconfig b/configs/shenzhou/thttpd/defconfig index d3e6aa6004..d5f58ab0b0 100644 --- a/configs/shenzhou/thttpd/defconfig +++ b/configs/shenzhou/thttpd/defconfig @@ -61,10 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -350,6 +353,12 @@ CONFIG_STM32_HAVE_ADC2=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -382,6 +391,7 @@ CONFIG_STM32_PWR=y CONFIG_STM32_SPI1=y # CONFIG_STM32_SPI2 is not set # CONFIG_STM32_SPI3 is not set +CONFIG_STM32_SYSCFG=y # CONFIG_STM32_TIM1 is not set # CONFIG_STM32_TIM2 is not set # CONFIG_STM32_TIM3 is not set @@ -554,6 +564,7 @@ CONFIG_RAM_SIZE=65536 # CONFIG_ARCH_BOARD_CLOUDCTRL is not set # CONFIG_ARCH_BOARD_OLIMEX_STM32P107 is not set CONFIG_ARCH_BOARD_SHENZHOU=y +# CONFIG_ARCH_BOARD_STM32_BUTTERFLY2 is not set # CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107 is not set # CONFIG_ARCH_BOARD_CUSTOM is not set CONFIG_ARCH_BOARD="shenzhou" @@ -704,14 +715,14 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -722,6 +733,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y # CONFIG_RTC_DATETIME is not set # CONFIG_RTC_HIRES is not set @@ -778,6 +790,7 @@ CONFIG_MTD=y # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -898,6 +911,7 @@ CONFIG_USART2_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1113,6 +1127,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1181,6 +1197,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CPUHOG is not set @@ -1271,6 +1289,7 @@ CONFIG_EXAMPLES_THTTPD_NETMASK=0xffffff00 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1391,6 +1410,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1495,6 +1515,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sim/nettest/defconfig b/configs/sim/nettest/defconfig index 4494a8a046..2cd4f87f85 100644 --- a/configs/sim/nettest/defconfig +++ b/configs/sim/nettest/defconfig @@ -42,9 +42,10 @@ CONFIG_BUILD_FLAT=y # # Debug Options # +# CONFIG_DEBUG_ALERT is not set # CONFIG_DEBUG_FEATURES is not set -# CONFIG_ARCH_HAVE_HEAPCHECK is not set # CONFIG_ARCH_HAVE_STACKCHECK is not set +# CONFIG_ARCH_HAVE_HEAPCHECK is not set # CONFIG_DEBUG_SYMBOLS is not set # CONFIG_ARCH_HAVE_CUSTOMOPT is not set # CONFIG_DEBUG_NOOPT is not set @@ -57,10 +58,13 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set CONFIG_ARCH_SIM=y # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="sim" @@ -78,6 +82,7 @@ CONFIG_SIM_NET_HOST_ROUTE=y # CONFIG_SIM_NET_BRIDGE is not set # CONFIG_SIM_FRAMEBUFFER is not set # CONFIG_SIM_SPIFLASH is not set +# CONFIG_SIM_QSPIFLASH is not set # # Architecture Options @@ -146,6 +151,7 @@ CONFIG_ARCH_BOARD="sim" # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set # @@ -166,6 +172,7 @@ CONFIG_ARCH_HAVE_TICKLESS=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2008 CONFIG_START_MONTH=8 @@ -178,6 +185,7 @@ CONFIG_PREALLOC_TIMERS=8 # # Tasks and Scheduling # +# CONFIG_SMP is not set # CONFIG_INIT_NONE is not set CONFIG_INIT_ENTRYPOINT=y # CONFIG_INIT_FILEPATH is not set @@ -258,6 +266,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=8192 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -273,12 +282,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -286,14 +299,25 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# # CONFIG_LCD is not set +# CONFIG_SLCD is not set # # LED Support # # CONFIG_RGBLED is not set # CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set # CONFIG_MMCSD is not set # CONFIG_MODEM is not set # CONFIG_MTD is not set @@ -307,6 +331,8 @@ CONFIG_DEV_NULL=y # CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y # CONFIG_16550_UART is not set # CONFIG_UART_SERIALDRIVER is not set # CONFIG_UART0_SERIALDRIVER is not set @@ -330,29 +356,32 @@ CONFIG_SERIAL=y # CONFIG_USART7_SERIALDRIVER is not set # CONFIG_USART8_SERIALDRIVER is not set # CONFIG_OTHER_UART_SERIALDRIVER is not set - -# -# USART Configuration -# # CONFIG_MCU_SERIAL is not set # CONFIG_STANDARD_SERIAL is not set # CONFIG_SERIAL_IFLOWCONTROL is not set # CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_SERIAL_DMA is not set # CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set - -# -# System Logging Device Options -# +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging # +# CONFIG_ARCH_SYSLOG is not set # CONFIG_RAMLOG is not set -# CONFIG_CONSOLE_SYSLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -499,11 +528,6 @@ CONFIG_FS_FAT=y # CONFIG_FS_UNIONFS is not set # CONFIG_FS_HOSTFS is not set -# -# System Logging -# -# CONFIG_SYSLOG_TIMESTAMP is not set - # # Graphics Support # @@ -553,6 +577,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -579,8 +605,10 @@ CONFIG_ARCH_HAVE_TLS=y # # Non-standard Library Support # +# CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -599,19 +627,19 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FSTEST is not set # CONFIG_EXAMPLES_FTPC is not set # CONFIG_EXAMPLES_FTPD is not set # CONFIG_EXAMPLES_HELLO is not set -# CONFIG_EXAMPLES_JSON is not set # CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set # CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set # CONFIG_EXAMPLES_MEDIA is not set # CONFIG_EXAMPLES_MM is not set # CONFIG_EXAMPLES_MODBUS is not set @@ -634,18 +662,17 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0xc0a8006a # CONFIG_EXAMPLES_NSH is not set # CONFIG_EXAMPLES_NULL is not set # CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set # CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set -# CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -659,9 +686,9 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0xc0a8006a # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_TIFF is not set # CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_WEBSERVER is not set # CONFIG_EXAMPLES_USBTERM is not set # CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set # CONFIG_EXAMPLES_WGET is not set # @@ -686,8 +713,9 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0xc0a8006a # # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_PCODE is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set # # FreeModBus @@ -698,11 +726,12 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0xc0a8006a # Network Utilities # # CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set # CONFIG_NETUTILS_FTPC is not set # CONFIG_NETUTILS_JSON is not set +CONFIG_NETUTILS_NETLIB=y # CONFIG_NETUTILS_SMTP is not set # CONFIG_NETUTILS_TELNETD is not set -CONFIG_NETUTILS_NETLIB=y # CONFIG_NETUTILS_WEBCLIENT is not set # CONFIG_NETUTILS_WEBSERVER is not set # CONFIG_NETUTILS_XMLRPC is not set @@ -724,16 +753,17 @@ CONFIG_NETUTILS_NETLIB=y # # System Libraries and NSH Add-Ons # -# CONFIG_SYSTEM_FREE is not set # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set -# CONFIG_SYSTEM_INSTALL is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set -# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sim/udgram/defconfig b/configs/sim/udgram/defconfig index 96d342f272..fa768fa7c2 100644 --- a/configs/sim/udgram/defconfig +++ b/configs/sim/udgram/defconfig @@ -58,10 +58,13 @@ CONFIG_DEBUG_NOOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set CONFIG_ARCH_SIM=y # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="sim" @@ -177,6 +180,7 @@ CONFIG_ARCH_HAVE_TICKLESS=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2008 CONFIG_START_MONTH=6 @@ -189,6 +193,7 @@ CONFIG_PREALLOC_TIMERS=8 # # Tasks and Scheduling # +# CONFIG_SMP is not set # CONFIG_INIT_NONE is not set CONFIG_INIT_ENTRYPOINT=y # CONFIG_INIT_FILEPATH is not set @@ -288,12 +293,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -372,6 +381,7 @@ CONFIG_SERIAL_CONSOLE=y # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -569,6 +579,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -625,6 +637,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CPUHOG is not set @@ -659,6 +672,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set @@ -713,6 +727,7 @@ CONFIG_EXAMPLES_UDGRAM_CLIENT_PRIORITY=100 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -787,6 +802,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -882,6 +898,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set # CONFIG_SYSTEM_SYMTAB is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sim/ustream/defconfig b/configs/sim/ustream/defconfig index 8c9a92db5f..0e9b3b7e70 100644 --- a/configs/sim/ustream/defconfig +++ b/configs/sim/ustream/defconfig @@ -58,10 +58,13 @@ CONFIG_DEBUG_NOOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set CONFIG_ARCH_SIM=y # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="sim" @@ -177,6 +180,7 @@ CONFIG_ARCH_HAVE_TICKLESS=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2008 CONFIG_START_MONTH=6 @@ -189,6 +193,7 @@ CONFIG_PREALLOC_TIMERS=8 # # Tasks and Scheduling # +# CONFIG_SMP is not set # CONFIG_INIT_NONE is not set CONFIG_INIT_ENTRYPOINT=y # CONFIG_INIT_FILEPATH is not set @@ -288,12 +293,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -372,6 +381,7 @@ CONFIG_SERIAL_CONSOLE=y # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -569,6 +579,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -625,6 +637,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CPUHOG is not set @@ -659,6 +672,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set @@ -708,6 +722,7 @@ CONFIG_EXAMPLES_USTREAM_ADDR="/dev/fifo" # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -782,6 +797,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -877,6 +893,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set # CONFIG_SYSTEM_SYMTAB is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3220g-eval/dhcpd/defconfig b/configs/stm3220g-eval/dhcpd/defconfig index 9d59eadc09..b574b0fde2 100644 --- a/configs/stm3220g-eval/dhcpd/defconfig +++ b/configs/stm3220g-eval/dhcpd/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -357,6 +360,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -704,6 +713,8 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -711,6 +722,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -840,6 +852,7 @@ CONFIG_USART3_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1028,6 +1041,8 @@ CONFIG_NUNGET_CHARS=0 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1080,6 +1095,8 @@ CONFIG_HAVE_CXXINITIALIZE=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1157,6 +1174,7 @@ CONFIG_EXAMPLES_DHCPD_NETMASK=0xffffff00 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1219,6 +1237,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3220g-eval/nettest/defconfig b/configs/stm3220g-eval/nettest/defconfig index 2d92070865..ad9239d239 100644 --- a/configs/stm3220g-eval/nettest/defconfig +++ b/configs/stm3220g-eval/nettest/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -357,6 +360,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -704,6 +713,8 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -711,6 +722,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -840,6 +852,7 @@ CONFIG_USART3_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1033,6 +1046,8 @@ CONFIG_NUNGET_CHARS=0 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1084,6 +1099,8 @@ CONFIG_HAVE_CXXINITIALIZE=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1169,6 +1186,7 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1217,6 +1235,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3220g-eval/nsh/defconfig b/configs/stm3220g-eval/nsh/defconfig index 59c9023236..dcda247266 100644 --- a/configs/stm3220g-eval/nsh/defconfig +++ b/configs/stm3220g-eval/nsh/defconfig @@ -61,10 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -349,6 +352,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -727,6 +736,8 @@ CONFIG_I2C_POLLED=y # CONFIG_I2C_TRACE is not set # CONFIG_I2C_DRIVER is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -734,6 +745,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y CONFIG_RTC_DATETIME=y # CONFIG_RTC_ALARM is not set @@ -797,6 +809,7 @@ CONFIG_MTD=y # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -906,6 +919,7 @@ CONFIG_USART3_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1122,6 +1136,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1191,6 +1207,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1271,6 +1289,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1357,6 +1376,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1449,6 +1469,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3220g-eval/nsh2/defconfig b/configs/stm3220g-eval/nsh2/defconfig index 94d37565c5..923e1dbda1 100644 --- a/configs/stm3220g-eval/nsh2/defconfig +++ b/configs/stm3220g-eval/nsh2/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -358,6 +361,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -495,6 +504,7 @@ CONFIG_STM32_PHYSR_100MBPS=0x0000 CONFIG_STM32_PHYSR_MODE=0x0004 CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 # CONFIG_STM32_ETH_PTP is not set +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -733,6 +743,8 @@ CONFIG_I2C_POLLED=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -740,6 +752,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y CONFIG_RTC_DATETIME=y # CONFIG_RTC_ALARM is not set @@ -808,6 +821,7 @@ CONFIG_MTD=y # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -902,6 +916,7 @@ CONFIG_SERIAL=y # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1122,6 +1137,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1190,6 +1207,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1272,6 +1291,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1360,6 +1380,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1471,6 +1492,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3220g-eval/nxwm/defconfig b/configs/stm3220g-eval/nxwm/defconfig index 95db35d531..9ddc3d2f30 100644 --- a/configs/stm3220g-eval/nxwm/defconfig +++ b/configs/stm3220g-eval/nxwm/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -357,6 +360,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -510,6 +519,7 @@ CONFIG_STM32_PHYSR_100MBPS=0x0000 CONFIG_STM32_PHYSR_MODE=0x0004 CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 # CONFIG_STM32_ETH_PTP is not set +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -753,6 +763,8 @@ CONFIG_I2C_POLLED=y # CONFIG_I2C_TRACE is not set # CONFIG_I2C_DRIVER is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -760,6 +772,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y CONFIG_RTC_DATETIME=y # CONFIG_RTC_ALARM is not set @@ -820,6 +833,7 @@ CONFIG_LCD_MAXPOWER=1 # CONFIG_LCD_NOKIA6100 is not set # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -955,6 +969,7 @@ CONFIG_USART3_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1280,6 +1295,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1336,6 +1353,8 @@ CONFIG_HAVE_CXXINITIALIZE=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1416,6 +1435,7 @@ CONFIG_HAVE_CXXINITIALIZE=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1499,6 +1519,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1780,6 +1801,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3220g-eval/telnetd/defconfig b/configs/stm3220g-eval/telnetd/defconfig index d1989d4107..2bb72cf565 100644 --- a/configs/stm3220g-eval/telnetd/defconfig +++ b/configs/stm3220g-eval/telnetd/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -357,6 +360,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -704,6 +713,8 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -711,6 +722,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -842,6 +854,7 @@ CONFIG_USART3_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1035,6 +1048,8 @@ CONFIG_NUNGET_CHARS=0 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1086,6 +1101,8 @@ CONFIG_HAVE_CXXINITIALIZE=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1166,6 +1183,7 @@ CONFIG_EXAMPLES_TELNETD_CLIENTSTACKSIZE=2048 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1214,6 +1232,7 @@ CONFIG_NETUTILS_TELNETD=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3240g-eval/dhcpd/defconfig b/configs/stm3240g-eval/dhcpd/defconfig index 975da224f5..091fc95372 100644 --- a/configs/stm3240g-eval/dhcpd/defconfig +++ b/configs/stm3240g-eval/dhcpd/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -358,6 +361,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -708,6 +717,8 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -715,6 +726,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -844,6 +856,7 @@ CONFIG_USART3_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1032,6 +1045,8 @@ CONFIG_NUNGET_CHARS=0 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1084,6 +1099,8 @@ CONFIG_HAVE_CXXINITIALIZE=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1161,6 +1178,7 @@ CONFIG_EXAMPLES_DHCPD_NETMASK=0xffffff00 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1223,6 +1241,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3240g-eval/discover/defconfig b/configs/stm3240g-eval/discover/defconfig index 2acba7767a..22b2acdc04 100644 --- a/configs/stm3240g-eval/discover/defconfig +++ b/configs/stm3240g-eval/discover/defconfig @@ -61,10 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -350,6 +353,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -729,6 +738,8 @@ CONFIG_I2C_POLLED=y # CONFIG_I2C_TRACE is not set # CONFIG_I2C_DRIVER is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -736,6 +747,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_TIMERS_CS2100CP is not set @@ -867,6 +879,7 @@ CONFIG_USART3_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1082,6 +1095,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1146,6 +1161,8 @@ CONFIG_HAVE_CXXINITIALIZE=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1228,6 +1245,7 @@ CONFIG_EXAMPLES_DISCOVER_NETMASK=0xffffff00 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1290,6 +1308,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3240g-eval/nettest/defconfig b/configs/stm3240g-eval/nettest/defconfig index 216bc7e7de..12c440b624 100644 --- a/configs/stm3240g-eval/nettest/defconfig +++ b/configs/stm3240g-eval/nettest/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -358,6 +361,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -708,6 +717,8 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -715,6 +726,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -844,6 +856,7 @@ CONFIG_USART3_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1037,6 +1050,8 @@ CONFIG_NUNGET_CHARS=0 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1088,6 +1103,8 @@ CONFIG_HAVE_CXXINITIALIZE=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1173,6 +1190,7 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1221,6 +1239,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3240g-eval/nsh/defconfig b/configs/stm3240g-eval/nsh/defconfig index 764b978628..d4d84d24c2 100644 --- a/configs/stm3240g-eval/nsh/defconfig +++ b/configs/stm3240g-eval/nsh/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -358,6 +361,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -741,6 +750,8 @@ CONFIG_I2C_POLLED=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -748,6 +759,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y CONFIG_RTC_DATETIME=y # CONFIG_RTC_ALARM is not set @@ -885,6 +897,7 @@ CONFIG_USART3_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1101,6 +1114,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1169,6 +1184,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1249,6 +1266,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1335,6 +1353,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1444,6 +1463,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3240g-eval/nsh2/defconfig b/configs/stm3240g-eval/nsh2/defconfig index ac0676ccc7..64d4a78045 100644 --- a/configs/stm3240g-eval/nsh2/defconfig +++ b/configs/stm3240g-eval/nsh2/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -359,6 +362,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -499,6 +508,7 @@ CONFIG_STM32_PHYSR_100MBPS=0x0000 CONFIG_STM32_PHYSR_MODE=0x0004 CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 # CONFIG_STM32_ETH_PTP is not set +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -737,6 +747,8 @@ CONFIG_I2C_POLLED=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -744,6 +756,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y CONFIG_RTC_DATETIME=y # CONFIG_RTC_ALARM is not set @@ -812,6 +825,7 @@ CONFIG_MTD=y # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -906,6 +920,7 @@ CONFIG_SERIAL=y # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1126,6 +1141,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1194,6 +1211,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1276,6 +1295,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1364,6 +1384,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1475,6 +1496,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3240g-eval/nxterm/defconfig b/configs/stm3240g-eval/nxterm/defconfig index 000a72380b..4226d88dc0 100644 --- a/configs/stm3240g-eval/nxterm/defconfig +++ b/configs/stm3240g-eval/nxterm/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -358,6 +361,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -744,6 +753,8 @@ CONFIG_I2C_POLLED=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -751,6 +762,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y CONFIG_RTC_DATETIME=y # CONFIG_RTC_ALARM is not set @@ -790,6 +802,7 @@ CONFIG_LCD_MAXPOWER=1 # CONFIG_LCD_NOKIA6100 is not set # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -918,6 +931,7 @@ CONFIG_USART3_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1239,6 +1253,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1303,6 +1319,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1379,6 +1397,7 @@ CONFIG_EXAMPLES_NXTERM=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1464,6 +1483,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1574,6 +1594,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3240g-eval/nxwm/defconfig b/configs/stm3240g-eval/nxwm/defconfig index 2f697b4b48..5b3f4a223d 100644 --- a/configs/stm3240g-eval/nxwm/defconfig +++ b/configs/stm3240g-eval/nxwm/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -358,6 +361,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -514,6 +523,7 @@ CONFIG_STM32_PHYSR_100MBPS=0x0000 CONFIG_STM32_PHYSR_MODE=0x0004 CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 # CONFIG_STM32_ETH_PTP is not set +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -757,6 +767,8 @@ CONFIG_I2C_POLLED=y # CONFIG_I2C_TRACE is not set # CONFIG_I2C_DRIVER is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -764,6 +776,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y CONFIG_RTC_DATETIME=y # CONFIG_RTC_ALARM is not set @@ -824,6 +837,7 @@ CONFIG_LCD_MAXPOWER=1 # CONFIG_LCD_NOKIA6100 is not set # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -952,6 +966,7 @@ CONFIG_USART3_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1277,6 +1292,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1340,6 +1357,8 @@ CONFIG_HAVE_CXXINITIALIZE=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1420,6 +1439,7 @@ CONFIG_HAVE_CXXINITIALIZE=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1504,6 +1524,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1785,6 +1806,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3240g-eval/telnetd/defconfig b/configs/stm3240g-eval/telnetd/defconfig index f18adcf52f..abdbc56841 100644 --- a/configs/stm3240g-eval/telnetd/defconfig +++ b/configs/stm3240g-eval/telnetd/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -358,6 +361,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -708,6 +717,8 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -715,6 +726,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -846,6 +858,7 @@ CONFIG_USART3_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1039,6 +1052,8 @@ CONFIG_NUNGET_CHARS=0 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1090,6 +1105,8 @@ CONFIG_HAVE_CXXINITIALIZE=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1170,6 +1187,7 @@ CONFIG_EXAMPLES_TELNETD_CLIENTSTACKSIZE=2048 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1218,6 +1236,7 @@ CONFIG_NETUTILS_TELNETD=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3240g-eval/webserver/defconfig b/configs/stm3240g-eval/webserver/defconfig index d7ff5a58a1..31a294000e 100644 --- a/configs/stm3240g-eval/webserver/defconfig +++ b/configs/stm3240g-eval/webserver/defconfig @@ -61,10 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -350,6 +353,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -731,6 +740,8 @@ CONFIG_I2C_POLLED=y # CONFIG_I2C_TRACE is not set # CONFIG_I2C_DRIVER is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -738,6 +749,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y CONFIG_RTC_DATETIME=y # CONFIG_RTC_ALARM is not set @@ -794,6 +806,7 @@ CONFIG_MTD=y # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -905,6 +918,7 @@ CONFIG_USART3_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1120,6 +1134,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1176,6 +1192,8 @@ CONFIG_HAVE_CXXINITIALIZE=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1272,6 +1290,7 @@ CONFIG_EXAMPLES_WEBSERVER_NOMAC=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1364,6 +1383,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1466,6 +1486,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3240g-eval/xmlrpc/defconfig b/configs/stm3240g-eval/xmlrpc/defconfig index f351cb4ee4..84f733db93 100644 --- a/configs/stm3240g-eval/xmlrpc/defconfig +++ b/configs/stm3240g-eval/xmlrpc/defconfig @@ -61,10 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -350,6 +353,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -724,6 +733,8 @@ CONFIG_I2C_POLLED=y # CONFIG_I2C_TRACE is not set # CONFIG_I2C_DRIVER is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -731,6 +742,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_TIMERS_CS2100CP is not set @@ -863,6 +875,7 @@ CONFIG_USART3_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1078,6 +1091,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1142,6 +1157,8 @@ CONFIG_HAVE_CXXINITIALIZE=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1226,6 +1243,7 @@ CONFIG_EXAMPLES_XMLRPC_NETMASK=0xffffff00 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1285,6 +1303,7 @@ CONFIG_XMLRPC_STRINGSIZE=64 # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm32butterfly2/nshnet/defconfig b/configs/stm32butterfly2/nshnet/defconfig index 4cc7757737..fe385454a6 100644 --- a/configs/stm32butterfly2/nshnet/defconfig +++ b/configs/stm32butterfly2/nshnet/defconfig @@ -61,11 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -351,6 +353,12 @@ CONFIG_STM32_HAVE_ADC2=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -472,6 +480,7 @@ CONFIG_STM32_MII_EXTCLK=y CONFIG_STM32_ETHFD=y CONFIG_STM32_ETH100MBPS=y # CONFIG_STM32_ETH_PTP is not set +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -596,7 +605,7 @@ CONFIG_CLOCK_MONOTONIC=y CONFIG_ARCH_HAVE_TIMEKEEPING=y # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=1970 -CONFIG_START_MONTH=0 +CONFIG_START_MONTH=1 CONFIG_START_DAY=1 CONFIG_MAX_WDOGPARMS=2 CONFIG_PREALLOC_WDOGS=8 @@ -709,14 +718,14 @@ CONFIG_RAMDISK=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set CONFIG_SPI_CALLBACK=y # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -1207,6 +1216,7 @@ CONFIG_EXAMPLES_ARCHBUTTONS=y CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 CONFIG_EXAMPLES_ARCHBUTTONS_MAX=4 # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CPUHOG is not set diff --git a/configs/stm32f4discovery/ipv6/defconfig b/configs/stm32f4discovery/ipv6/defconfig index 6ed6621ed1..3b01309477 100644 --- a/configs/stm32f4discovery/ipv6/defconfig +++ b/configs/stm32f4discovery/ipv6/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -360,6 +363,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -515,6 +524,7 @@ CONFIG_STM32_RMII=y # CONFIG_STM32_RMII_MCO1 is not set # CONFIG_STM32_RMII_MCO2 is not set CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -754,14 +764,14 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -772,6 +782,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -915,6 +926,7 @@ CONFIG_USART6_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1141,6 +1153,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1202,7 +1216,9 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1283,6 +1299,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1363,6 +1380,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1483,6 +1501,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm32f4discovery/netnsh/defconfig b/configs/stm32f4discovery/netnsh/defconfig index 9d5e5bfb53..2960a94caf 100644 --- a/configs/stm32f4discovery/netnsh/defconfig +++ b/configs/stm32f4discovery/netnsh/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -360,6 +363,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -515,6 +524,7 @@ CONFIG_STM32_RMII=y # CONFIG_STM32_RMII_MCO1 is not set # CONFIG_STM32_RMII_MCO2 is not set CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -754,14 +764,14 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -772,6 +782,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -917,6 +928,7 @@ CONFIG_USART6_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1145,6 +1157,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1213,7 +1227,9 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1294,6 +1310,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1380,6 +1397,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1489,6 +1507,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/tm4c1294-launchpad/ipv6/defconfig b/configs/tm4c1294-launchpad/ipv6/defconfig index 703b7c92a9..4de7a634ef 100644 --- a/configs/tm4c1294-launchpad/ipv6/defconfig +++ b/configs/tm4c1294-launchpad/ipv6/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -271,6 +274,7 @@ CONFIG_TIVA_PHY_INTERRUPTS=y CONFIG_TIVA_EMAC_NRXDESC=8 CONFIG_TIVA_EMAC_NTXDESC=4 # CONFIG_TIVA_EMAC_ENHANCEDDESC is not set +CONFIG_TIVA_ETHERNET_HPWORK=y CONFIG_TIVA_BOARDMAC=y # @@ -345,11 +349,11 @@ CONFIG_ARCH_HAVE_LEDS=y CONFIG_ARCH_LEDS=y CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_ARCH_BUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -375,6 +379,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2013 CONFIG_START_MONTH=3 @@ -472,6 +477,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -491,12 +497,16 @@ CONFIG_I2C=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_TIMERS_CS2100CP is not set @@ -505,7 +515,12 @@ CONFIG_I2C_DRIVER=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -600,9 +615,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -616,6 +634,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -810,6 +829,8 @@ CONFIG_LIBM=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -837,6 +858,7 @@ CONFIG_LIBC_NETDB=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -860,10 +882,11 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -891,9 +914,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -936,6 +959,7 @@ CONFIG_EXAMPLES_NSH=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1010,12 +1034,12 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_LS is not set # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1032,6 +1056,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -1125,7 +1150,7 @@ CONFIG_NSH_MAX_ROUNDTRIP=20 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=6 @@ -1144,6 +1169,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/tm4c1294-launchpad/nsh/defconfig b/configs/tm4c1294-launchpad/nsh/defconfig index a26e9d5f1b..922fe3c678 100644 --- a/configs/tm4c1294-launchpad/nsh/defconfig +++ b/configs/tm4c1294-launchpad/nsh/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -271,6 +274,7 @@ CONFIG_TIVA_PHY_INTERRUPTS=y CONFIG_TIVA_EMAC_NRXDESC=8 CONFIG_TIVA_EMAC_NTXDESC=4 # CONFIG_TIVA_EMAC_ENHANCEDDESC is not set +CONFIG_TIVA_ETHERNET_HPWORK=y CONFIG_TIVA_BOARDMAC=y # @@ -345,11 +349,11 @@ CONFIG_ARCH_HAVE_LEDS=y CONFIG_ARCH_LEDS=y CONFIG_ARCH_HAVE_BUTTONS=y # CONFIG_ARCH_BUTTONS is not set -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -375,6 +379,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2015 CONFIG_START_MONTH=1 @@ -472,6 +477,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -491,12 +497,16 @@ CONFIG_I2C=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_TIMERS_CS2100CP is not set @@ -505,7 +515,12 @@ CONFIG_I2C_DRIVER=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -602,9 +617,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -618,6 +636,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -816,6 +835,8 @@ CONFIG_LIBM=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -849,6 +870,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -872,9 +894,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -902,9 +925,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -947,6 +970,7 @@ CONFIG_EXAMPLES_NSH=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1026,13 +1050,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_LS is not set # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1050,6 +1074,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -1126,7 +1151,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=6 @@ -1145,6 +1170,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/u-blox-c027/nsh/defconfig b/configs/u-blox-c027/nsh/defconfig index 944ede078b..7f9acf9aff 100644 --- a/configs/u-blox-c027/nsh/defconfig +++ b/configs/u-blox-c027/nsh/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -144,7 +147,6 @@ CONFIG_ARM_HAVE_MPU_UNIFIED=y CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y # CONFIG_ARMV7M_HAVE_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_LPC17_GPIOIRQ is not set # CONFIG_SERIAL_TERMIOS is not set # @@ -220,6 +222,7 @@ CONFIG_LPC17_I2C1=y # Serial driver options # CONFIG_UART1_RINGINDICATOR=y +# CONFIG_LPC17_GPIOIRQ is not set # # I2C driver options @@ -237,6 +240,7 @@ CONFIG_NET_NRXDESC=6 # CONFIG_NET_WOL is not set # CONFIG_NET_HASH is not set # CONFIG_LPC17_MULTICAST is not set +CONFIG_LPC17_ETHERNET_HPWORK=y # # Architecture Options @@ -341,6 +345,7 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set CONFIG_CLOCK_MONOTONIC=y +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2016 CONFIG_START_MONTH=1 @@ -439,6 +444,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 # CONFIG_DISABLE_POLL is not set CONFIG_DEV_NULL=y CONFIG_DEV_ZERO=y +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -454,12 +460,16 @@ CONFIG_DEV_ZERO=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -644,10 +654,12 @@ CONFIG_UART3_2STOP=0 # CONFIG_UART3_IFLOWCONTROL is not set # CONFIG_UART3_OFLOWCONTROL is not set # CONFIG_UART3_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -678,8 +690,6 @@ CONFIG_NET_NOINTS=y CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 -CONFIG_NET_TUN_MTU=296 -CONFIG_NET_TUN_TCP_RECVWNDO=256 CONFIG_NET_GUARDSIZE=2 # @@ -690,6 +700,9 @@ CONFIG_NET_ETHERNET=y # CONFIG_NET_LOOPBACK is not set CONFIG_NET_TUN=y CONFIG_TUN_NINTERFACES=1 +CONFIG_NET_TUN_MTU=296 +CONFIG_NET_TUN_TCP_RECVWNDO=256 +CONFIG_TUN_HPWORK=y # # Network Device Operations @@ -877,6 +890,8 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -939,6 +954,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # Examples # # CONFIG_EXAMPLES_BRIDGE is not set +# CONFIG_EXAMPLES_CCTYPE is not set CONFIG_EXAMPLES_CHAT=y CONFIG_EXAMPLES_CHAT_TTY_DEVNODE="/dev/ttyS1" CONFIG_EXAMPLES_CHAT_TIMEOUT_SECONDS=20 @@ -948,7 +964,6 @@ CONFIG_EXAMPLES_CHAT_PRESET1="\"\" AT+UPSDA=0,3 OK AT+UPSND=0,8 OK AT+UPSND=0,0 CONFIG_EXAMPLES_CHAT_PRESET2="\"\" AT+USOCR=6 OK AT+USOCO=0,\\\"195.34.89.241\\\",7 PAUSE 10 OK AT+USORD=0,32 u-blox \\c" CONFIG_EXAMPLES_CHAT_PRESET3="\"\" AT+USOWR=0,5,\\\"NuttX\\\" PAUSE 10 OK AT+USORD=0,5 NuttX AT+USOCL=0" # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -977,9 +992,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set CONFIG_EXAMPLES_PPPD=y +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -1025,6 +1040,7 @@ CONFIG_EXAMPLES_PPPD=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1109,13 +1125,13 @@ CONFIG_NSH_BUILTIN_APPS=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1229,6 +1245,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set CONFIG_SYSTEM_UBLOXMODEM=y CONFIG_SYSTEM_UBLOXMODEM_TTY_DEVNODE="/dev/ttyS1" CONFIG_SYSTEM_UBLOXMODEM_DEVNODE="/dev/ubxmdm" diff --git a/configs/viewtool-stm32f107/netnsh/defconfig b/configs/viewtool-stm32f107/netnsh/defconfig index 67ffa627f6..3da3e1b85b 100644 --- a/configs/viewtool-stm32f107/netnsh/defconfig +++ b/configs/viewtool-stm32f107/netnsh/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -357,6 +360,12 @@ CONFIG_STM32_HAVE_ADC2=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -389,6 +398,7 @@ CONFIG_STM32_PWR=y # CONFIG_STM32_SPI1 is not set # CONFIG_STM32_SPI2 is not set # CONFIG_STM32_SPI3 is not set +CONFIG_STM32_SYSCFG=y # CONFIG_STM32_TIM1 is not set # CONFIG_STM32_TIM2 is not set # CONFIG_STM32_TIM3 is not set @@ -468,6 +478,7 @@ CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 CONFIG_STM32_RMII=y # CONFIG_STM32_RMII_MCO is not set CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -549,6 +560,7 @@ CONFIG_RAM_SIZE=65536 # CONFIG_ARCH_BOARD_CLOUDCTRL is not set # CONFIG_ARCH_BOARD_OLIMEX_STM32P107 is not set # CONFIG_ARCH_BOARD_SHENZHOU is not set +# CONFIG_ARCH_BOARD_STM32_BUTTERFLY2 is not set CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y # CONFIG_ARCH_BOARD_CUSTOM is not set CONFIG_ARCH_BOARD="viewtool-stm32f107" @@ -699,6 +711,8 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -706,6 +720,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -839,6 +854,7 @@ CONFIG_USART1_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1051,6 +1067,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1108,6 +1126,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1182,6 +1202,7 @@ CONFIG_EXAMPLES_NSH=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1269,6 +1290,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1374,6 +1396,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/zkit-arm-1769/hello/defconfig b/configs/zkit-arm-1769/hello/defconfig index eb65f867f3..d509b93944 100644 --- a/configs/zkit-arm-1769/hello/defconfig +++ b/configs/zkit-arm-1769/hello/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -145,7 +148,6 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y # CONFIG_ARMV7M_HAVE_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_LPC17_GPIOIRQ is not set # CONFIG_SERIAL_TERMIOS is not set # @@ -220,6 +222,7 @@ CONFIG_LPC17_UART0=y # # Serial driver options # +# CONFIG_LPC17_GPIOIRQ is not set # # Ethernet driver options @@ -231,6 +234,7 @@ CONFIG_NET_NRXDESC=13 # CONFIG_NET_WOL is not set # CONFIG_NET_HASH is not set # CONFIG_LPC17_MULTICAST is not set +CONFIG_LPC17_ETHERNET_HPWORK=y # # Architecture Options @@ -309,6 +313,7 @@ CONFIG_ARCH_LEDS=y # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set # @@ -327,6 +332,7 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2013 CONFIG_START_MONTH=3 @@ -411,6 +417,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 # CONFIG_DISABLE_POLL is not set CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -426,12 +433,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -439,7 +450,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -551,9 +567,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -567,6 +586,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -754,6 +774,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -781,6 +803,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -799,9 +822,9 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set @@ -831,10 +854,9 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set @@ -880,6 +902,7 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -924,13 +947,14 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/zkit-arm-1769/nsh/defconfig b/configs/zkit-arm-1769/nsh/defconfig index 14a6d97e04..4e3b92cbb2 100644 --- a/configs/zkit-arm-1769/nsh/defconfig +++ b/configs/zkit-arm-1769/nsh/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -145,7 +148,6 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y # CONFIG_ARMV7M_HAVE_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_LPC17_GPIOIRQ is not set # CONFIG_SERIAL_TERMIOS is not set # @@ -220,6 +222,7 @@ CONFIG_LPC17_SPI=y # # Serial driver options # +# CONFIG_LPC17_GPIOIRQ is not set # # Ethernet driver options @@ -231,6 +234,7 @@ CONFIG_NET_NRXDESC=6 # CONFIG_NET_WOL is not set # CONFIG_NET_HASH is not set # CONFIG_LPC17_MULTICAST is not set +CONFIG_LPC17_ETHERNET_HPWORK=y # # Architecture Options @@ -305,13 +309,11 @@ CONFIG_ARCH_BOARD="zkit-arm-1769" # CONFIG_ARCH_HAVE_LEDS=y CONFIG_ARCH_LEDS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDSPIPORTNO=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -337,6 +339,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2013 CONFIG_START_MONTH=2 @@ -434,6 +437,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -449,21 +453,23 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set # CONFIG_SPI_EXCHANGE is not set # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -471,7 +477,12 @@ CONFIG_SPI=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -596,9 +607,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -612,6 +626,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -814,6 +829,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -851,6 +868,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -869,9 +887,9 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -900,10 +918,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -948,6 +965,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1027,13 +1045,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1051,6 +1069,9 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 +CONFIG_NSH_MMCSDSPIPORTNO=0 # # Configure Command Options @@ -1125,7 +1146,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -1136,6 +1157,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/zkit-arm-1769/nxhello/defconfig b/configs/zkit-arm-1769/nxhello/defconfig index 1564d95803..a969f3a503 100644 --- a/configs/zkit-arm-1769/nxhello/defconfig +++ b/configs/zkit-arm-1769/nxhello/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -145,7 +148,6 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y # CONFIG_ARMV7M_HAVE_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_LPC17_GPIOIRQ is not set # CONFIG_SERIAL_TERMIOS is not set # @@ -220,6 +222,7 @@ CONFIG_LPC17_SSP0=y # # Serial driver options # +# CONFIG_LPC17_GPIOIRQ is not set # # Ethernet driver options @@ -231,6 +234,7 @@ CONFIG_NET_NRXDESC=6 # CONFIG_NET_WOL is not set # CONFIG_NET_HASH is not set # CONFIG_LPC17_MULTICAST is not set +CONFIG_LPC17_ETHERNET_HPWORK=y # # Architecture Options @@ -305,13 +309,11 @@ CONFIG_ARCH_BOARD="zkit-arm-1769" # CONFIG_ARCH_HAVE_LEDS=y CONFIG_ARCH_LEDS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDSPIPORTNO=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -337,6 +339,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2013 CONFIG_START_MONTH=2 @@ -434,6 +437,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -449,21 +453,23 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set # CONFIG_SPI_EXCHANGE is not set CONFIG_SPI_CMDDATA=y # CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -471,7 +477,12 @@ CONFIG_SPI_CMDDATA=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -494,6 +505,7 @@ CONFIG_LCD_MAXPOWER=1 # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set # CONFIG_LCD_UG9664HSWAG01 is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -633,9 +645,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -649,6 +664,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -933,6 +949,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -966,6 +984,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -984,9 +1003,9 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set @@ -1031,10 +1050,9 @@ CONFIG_EXAMPLES_NXHELLO_DEFAULT_FONT=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -1077,6 +1095,7 @@ CONFIG_EXAMPLES_NXHELLO_DEFAULT_FONT=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1155,13 +1174,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_LS is not set # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_NSLOOKUP is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set @@ -1179,6 +1198,9 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 +CONFIG_NSH_MMCSDSPIPORTNO=0 # # Configure Command Options @@ -1253,7 +1275,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set @@ -1264,6 +1286,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/zkit-arm-1769/thttpd/defconfig b/configs/zkit-arm-1769/thttpd/defconfig index eba9489305..d385519e2c 100644 --- a/configs/zkit-arm-1769/thttpd/defconfig +++ b/configs/zkit-arm-1769/thttpd/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -145,7 +148,6 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y CONFIG_ARMV7M_OABI_TOOLCHAIN=y # CONFIG_ARMV7M_HAVE_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_LPC17_GPIOIRQ is not set # CONFIG_SERIAL_TERMIOS is not set # @@ -220,6 +222,7 @@ CONFIG_LPC17_UART0=y # # Serial driver options # +# CONFIG_LPC17_GPIOIRQ is not set # # Ethernet driver options @@ -231,6 +234,7 @@ CONFIG_NET_NRXDESC=18 # CONFIG_NET_WOL is not set # CONFIG_NET_HASH is not set # CONFIG_LPC17_MULTICAST is not set +CONFIG_LPC17_ETHERNET_HPWORK=y # # Architecture Options @@ -328,6 +332,7 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2013 CONFIG_START_MONTH=2 @@ -428,12 +433,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -566,6 +575,7 @@ CONFIG_UART0_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -767,6 +777,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -813,6 +825,7 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CPUHOG is not set @@ -847,6 +860,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set @@ -895,6 +909,7 @@ CONFIG_EXAMPLES_THTTPD_NETMASK=0xffffff00 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -977,6 +992,7 @@ CONFIG_THTTPD_TILDE_MAP_NONE=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set -- GitLab From 0d8e191d699a44bff2dde971ae29189bfd239956 Mon Sep 17 00:00:00 2001 From: Rajan Gill Date: Sat, 19 Nov 2016 09:55:21 -0600 Subject: [PATCH 460/734] sched/clock: Correct calculation for the case of Tickless mode with a 32-bit timer. In that case, the calculation was returning millisecond accuracy. That is not good when the timer accuracy is < 1 msec. --- sched/clock/clock_systimer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sched/clock/clock_systimer.c b/sched/clock/clock_systimer.c index 6c9645fbf8..1b13451092 100644 --- a/sched/clock/clock_systimer.c +++ b/sched/clock/clock_systimer.c @@ -108,7 +108,7 @@ systime_t clock_systimer(void) /* Convert to a 64- then a 32-bit value */ - tmp = MSEC2TICK(1000 * (uint64_t)ts.tv_sec + (uint64_t)ts.tv_nsec / 1000000); + tmp = USEC2TICK(1000000 * (uint64_t)ts.tv_sec + (uint64_t)ts.tv_nsec / 1000); return (systime_t)(tmp & 0x00000000ffffffff); # endif /* CONFIG_SYSTEM_TIME64 */ -- GitLab From f40fbaa4b9a27c8c60cb9f427848ded8d19aa41e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 19 Nov 2016 11:41:05 -0600 Subject: [PATCH 461/734] sched/task: task_restart() test not supported on SMP systems. This is not fully implemented. --- include/sched.h | 4 +++- sched/task/Make.defs | 9 ++++++--- sched/task/task_restart.c | 4 ++++ 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/include/sched.h b/include/sched.h index 0c4443e93d..c12bf99d54 100644 --- a/include/sched.h +++ b/include/sched.h @@ -1,7 +1,7 @@ /******************************************************************************** * include/sched.h * - * Copyright (C) 2007-2009, 2011, 2013, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2011, 2013, 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -227,7 +227,9 @@ int task_create(FAR const char *name, int priority, int stack_size, main_t entry, FAR char * const argv[]); #endif int task_delete(pid_t pid); +#ifndef CONFIG_SMP /* Not yet supported for the SMP case */ int task_restart(pid_t pid); +#endif /* Task Scheduling Interfaces (based on POSIX APIs) */ diff --git a/sched/task/Make.defs b/sched/task/Make.defs index 32c21f3324..a9a85971e6 100644 --- a/sched/task/Make.defs +++ b/sched/task/Make.defs @@ -35,9 +35,12 @@ CSRCS += task_create.c task_init.c task_setup.c task_activate.c CSRCS += task_start.c task_delete.c task_exit.c task_exithook.c -CSRCS += task_recover.c task_restart.c task_spawnparms.c -CSRCS += task_terminate.c task_getgroup.c task_prctl.c task_getpid.c -CSRCS += exit.c +CSRCS += task_recover.c task_spawnparms.c task_terminate.c +CSRCS += task_getgroup.c task_prctl.c task_getpid.c exit.c + +ifneq ($(CONFIG_SMP),y) +CSRCS += task_restart.c +endif ifeq ($(CONFIG_ARCH_HAVE_VFORK),y) ifeq ($(CONFIG_SCHED_WAITPID),y) diff --git a/sched/task/task_restart.c b/sched/task/task_restart.c index 70da24df57..9ca6d4e88d 100644 --- a/sched/task/task_restart.c +++ b/sched/task/task_restart.c @@ -51,6 +51,8 @@ #include "signal/signal.h" #include "task/task.h" +#ifndef CONFIG_SMP /* Not yet supported for the SMP case */ + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -209,3 +211,5 @@ errout_with_lock: sched_unlock(); return ERROR; } + +#endif /* CONFIG_SMP */ -- GitLab From a2aba902523add693595709a5e177d94e6a90f11 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 19 Nov 2016 11:48:08 -0600 Subject: [PATCH 462/734] Update some comments --- include/nuttx/irq.h | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/include/nuttx/irq.h b/include/nuttx/irq.h index f7bfd75b3b..d0076d9ca0 100644 --- a/include/nuttx/irq.h +++ b/include/nuttx/irq.h @@ -108,9 +108,22 @@ int irq_attach(int irq, xcpt_t isr); * Take the CPU IRQ lock and disable interrupts on all CPUs. A thread- * specific counter is increment to indicate that the thread has IRQs * disabled and to support nested calls to enter_critical_section(). + * + * NOTE: Most architectures do not support disabling all CPUs from one + * CPU. ARM is an example. In such cases, logic in + * enter_critical_section() will still manage entrance into the + * protected logic using spinlocks. + * * If SMP is not enabled: * This function is equivalent to up_irq_save(). * + * Input Parameters: + * None + * + * Returned Value: + * An opaque, architecture-specific value that represents the state of + * the interrupts prior to the call to enter_critical_section(); + * ****************************************************************************/ #if defined(CONFIG_SMP) || defined(CONFIG_SCHED_INSTRUMENTATION_CSECTION) @@ -125,10 +138,19 @@ irqstate_t enter_critical_section(void); * Description: * If SMP is enabled: * Decrement the IRQ lock count and if it decrements to zero then release - * the spinlock. + * the spinlock and restore the interrupt state as it was prior to the + * previous call to enter_critical_section(). + * * If SMP is not enabled: * This function is equivalent to up_irq_restore(). * + * Input Parameters: + * flags - The architecture-specific value that represents the state of + * the interrupts prior to the call to enter_critical_section(); + * + * Returned Value: + * None + * ****************************************************************************/ #if defined(CONFIG_SMP) || defined(CONFIG_SCHED_INSTRUMENTATION_CSECTION) -- GitLab From 6a7619b6f049d54b77f1e6bf18e3190d73e512a3 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 19 Nov 2016 13:23:15 -0600 Subject: [PATCH 463/734] Update TODO list --- TODO | 31 ++++++++++++++++++++++++++++++- include/nuttx/irq.h | 2 +- 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/TODO b/TODO index 3d54ecf7f7..c4ff18e5f7 100644 --- a/TODO +++ b/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated November 17, 2016) +NuttX TODO List (Last updated November 19, 2016) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with @@ -304,6 +304,35 @@ o Task/Scheduler (sched/) Priority: Low. Things are just the way that we want them for the way that NuttX is used today. + Title: SMP ISSUES + Description: The interface task_restart() (and probably task_delete()) are + not usable in the SMP configuration in the current design. In + the non-SMP case, these are relatively simple: If the task is + are not restarting/deleting itself, then the task to-be-restarted/ + deleted is is supended and the restart/delete operation is a + simple operation on data structures. + + In the SMP configuration, on the other hand, the task to be + restarted/deleted my in fact be executing concurrently on + another CPU and the existing logic cannot support those + operations on the running another CPU. + + There might be a simple way to handler this; perhaps using + up_cpu_pause(), you could pause all of the other CPUs, perform + the restart/delete operation, then restart all other CPUs. But + this seems like a lot of work to support some garbage interfaces + that really should be removed anyway. These are unsafe, non- + standard interfaces that really have no place in an RTOS (unsafe + because you don't know what resources were held by the task when + it was restarted or deleted). + + NOTE: Currently task_restart() is not even built if CONFIG_SMP=y. + The task_restart() test is also disabled in apps/examples/ostest + in this configuration. task_delete(), on the other hand, is + built (but probably should not be). + Status: Open + Priority: Low. I do not plan to do anything with this in the near future. + o Memory Management (mm/) ^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/include/nuttx/irq.h b/include/nuttx/irq.h index d0076d9ca0..e5ae0807d9 100644 --- a/include/nuttx/irq.h +++ b/include/nuttx/irq.h @@ -163,6 +163,6 @@ void leave_critical_section(irqstate_t flags); #ifdef __cplusplus } #endif -#endif +#endif /* __ASSEMBLY__ */ #endif /* __INCLUDE_NUTTX_IRQ_H */ -- GitLab From ac9a11d9ab5591d59c256d7073fcb533e7314456 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 19 Nov 2016 13:31:14 -0600 Subject: [PATCH 464/734] Update TODO list --- TODO | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/TODO b/TODO index c4ff18e5f7..2410708a59 100644 --- a/TODO +++ b/TODO @@ -9,7 +9,7 @@ issues related to each board port. nuttx/: - (14) Task/Scheduler (sched/) + (15) Task/Scheduler (sched/) (1) Memory Management (mm/) (1) Power Management (drivers/pm) (3) Signals (sched/signal, arch/) @@ -333,6 +333,29 @@ o Task/Scheduler (sched/) Status: Open Priority: Low. I do not plan to do anything with this in the near future. + Title: SPINLOCKS AND DATA CACHES + Description: If spinlocks are used in a system with a data cache, then there + may be a problem with cache coherency in some CPU architectures: + When one CPU modifies the spinlock, the changes may not be + visible to another CPU if it does not share the data cache. + That would cause failure in the spinlock logic. + + Flushing the D-cache on writes and invalidating before a read is + not really an option. spinlocks are normally 8-bits in size and + cache lines are typically 32-bytes so that would have side effects + unless the spinlocks were made to be the same size as one cache + line. + + The better option is to add compiler independent "ornmentation" + to the spinlock so that the spinlocks are all linked together + into a separate, non-cacheable memory regions. Because of + region aligment and minimum region mapping sizes. This would + work in systems that have both data cache and either an MPU or + an MMU. + Status: Open + Priority: High. spinlocks, and hence SMP, will not work on such systems + without this change. + o Memory Management (mm/) ^^^^^^^^^^^^^^^^^^^^^^^ -- GitLab From 82cd27170bf69eafd338f64abd082cbee772c4fb Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 19 Nov 2016 16:37:09 -0600 Subject: [PATCH 465/734] Update TODO list --- TODO | 52 +++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 43 insertions(+), 9 deletions(-) diff --git a/TODO b/TODO index 2410708a59..94da63ddcc 100644 --- a/TODO +++ b/TODO @@ -9,7 +9,8 @@ issues related to each board port. nuttx/: - (15) Task/Scheduler (sched/) + (13) Task/Scheduler (sched/) + (3) SMP (1) Memory Management (mm/) (1) Power Management (drivers/pm) (3) Signals (sched/signal, arch/) @@ -255,7 +256,7 @@ o Task/Scheduler (sched/) a holder of the semaphore. Normally, a task is removed from the holder list when it finally releases the semaphore via sem_post(). - + However, TASK A never calls sem_post(sem) so it becomes *permanently* a holder of the semaphore and may have its priority boosted at any time when any other task tries to @@ -304,7 +305,9 @@ o Task/Scheduler (sched/) Priority: Low. Things are just the way that we want them for the way that NuttX is used today. - Title: SMP ISSUES +o SMP + ^^^ + Title: SMP ISSUES WITH task_restart() AND task_delete() Description: The interface task_restart() (and probably task_delete()) are not usable in the SMP configuration in the current design. In the non-SMP case, these are relatively simple: If the task is @@ -330,9 +333,39 @@ o Task/Scheduler (sched/) The task_restart() test is also disabled in apps/examples/ostest in this configuration. task_delete(), on the other hand, is built (but probably should not be). + Status: Open Priority: Low. I do not plan to do anything with this in the near future. + Title: SMP AND SIGNAL ACTIONS + Description: Suppose a task task is running on CPU1 and it is signaled from + another task running on CPU0. How does the signal handler run + on CPU1? I think it does not; I think that the signal will be + lost. I think all testing up to this point has used a task + waiting for a signal vs. a running task receiving a signal. + This case has never been tested, but I suspect an issues. + Here is why... this is the signal handling sequence: + + - sigueue() will set up the siginfo data structure and call + sig_dipatch(). + - sig_tcbdispach() or group_signal() depending on the + configuration. Let's assume the simpler sig_tcbdispatch(). + - sig_tcbdispatch() will call queue the signal action (via + sig_queueaction()) and then call the architecture-specific + up_schedule_signaction set up the invoke the signal handler + (for example in arch/arm/src/armv7-m/up_schedulesigaction.c). + - sig_queueaction() will assume that the other task is not + running and will simply modify data structures in the TCB. + This, will have no effect if the task is running and the + signal action will not be performed. + + This is really a variant of the problem described above under + "SMP ISSUES WITH task_restart() AND task_delete()" and the + same proposed solution applies: Call up_cpu_pause() to stop + all other CPUs before up_schedule_signaction runs. + Status: Open + Priority: High. This must be fixed. + Title: SPINLOCKS AND DATA CACHES Description: If spinlocks are used in a system with a data cache, then there may be a problem with cache coherency in some CPU architectures: @@ -346,12 +379,12 @@ o Task/Scheduler (sched/) unless the spinlocks were made to be the same size as one cache line. - The better option is to add compiler independent "ornmentation" + The better option is to add compiler independent "ornamentation" to the spinlock so that the spinlocks are all linked together into a separate, non-cacheable memory regions. Because of - region aligment and minimum region mapping sizes. This would - work in systems that have both data cache and either an MPU or - an MMU. + region aligment and minimum region mapping sizes this could + still be wasteful of memory. This would work in systems that + have both data cache and either an MPU or an MMU. Status: Open Priority: High. spinlocks, and hence SMP, will not work on such systems without this change. @@ -1360,8 +1393,8 @@ o USB (drivers/usbdev, drivers/usbhost) Status: Open Priority: Medium-Low unless you really need host CDC/ACM support. -o Libraries (libc/) - ^^^^^^^^^^^^^^^^^ +o Libraries (libc/, libm/) + ^^^^^^^^^^^^^^^^^^^^^^^^ Title: SIGNED time_t Description: The NuttX time_t is type uint32_t. I think this is consistent @@ -2080,3 +2113,4 @@ o Other Applications & Tests (apps/examples/) the artifact is larger. Status: Open Priority: Medium. + -- GitLab From f5b35e04614d33e6ed337db581ab2f4b81eedb74 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 19 Nov 2016 16:58:25 -0600 Subject: [PATCH 466/734] Clarify TODO list --- TODO | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/TODO b/TODO index 94da63ddcc..5b5ca8ac5f 100644 --- a/TODO +++ b/TODO @@ -322,12 +322,17 @@ o SMP There might be a simple way to handler this; perhaps using up_cpu_pause(), you could pause all of the other CPUs, perform - the restart/delete operation, then restart all other CPUs. But - this seems like a lot of work to support some garbage interfaces - that really should be removed anyway. These are unsafe, non- - standard interfaces that really have no place in an RTOS (unsafe - because you don't know what resources were held by the task when - it was restarted or deleted). + the restart/delete operation, then restart all other CPUs. A + better solution would be a new interface like up_cpu_stop(). + This would be sent to all CPUs and if the task is running on + any of them, it would suspend the task and put it in the INVALID + state. + + But this seems like a lot of work to support some garbage + interfaces that really should be removed anyway. These are + unsafe, non-standard interfaces that really have no place in an + RTOS (unsafe because you don't know what resources were held + by the task when it was restarted or deleted). NOTE: Currently task_restart() is not even built if CONFIG_SMP=y. The task_restart() test is also disabled in apps/examples/ostest -- GitLab From e24f2814015c6dcd9fc67edcd399ccbaf41c3669 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 20 Nov 2016 07:57:18 -0600 Subject: [PATCH 467/734] This commit adds a new internal interfaces and fixes a problem with three APIs in the SMP configuration. The new internal interface is sched_cpu_pause(tcb). This function will pause a CPU if the task associated with 'tcb' is running on that CPU. This allows a different CPU to modify that OS data stuctures associated with the CPU. When the other CPU is resumed, those modifications can safely take place. The three fixes are to handle cases in the SMP configuration where one CPU does need to make modifications to TCB and data structures on a task that could be running running on another CPU. Those three cases are task_delete(), task_restart(), and execution of signal handles. In all three cases the solutions is basically the same: (1) Call sched_cpu_pause(tcb) to pause the CPU on which the task is running, (2) perform the necessary operations, then (3) call up_cpu_resume() to restart the paused CPU. --- TODO | 65 +------------------ include/sched.h | 2 - sched/sched/Make.defs | 3 +- sched/sched/sched.h | 7 ++- sched/sched/sched_cpupause.c | 119 +++++++++++++++++++++++++++++++++++ sched/signal/sig_dispatch.c | 28 ++++++++- sched/task/Make.defs | 6 +- sched/task/task_restart.c | 69 ++++++++++---------- sched/task/task_terminate.c | 86 ++++++++++++++++--------- 9 files changed, 246 insertions(+), 139 deletions(-) create mode 100644 sched/sched/sched_cpupause.c diff --git a/TODO b/TODO index 5b5ca8ac5f..c0e268e3b0 100644 --- a/TODO +++ b/TODO @@ -10,7 +10,7 @@ issues related to each board port. nuttx/: (13) Task/Scheduler (sched/) - (3) SMP + (1) SMP (1) Memory Management (mm/) (1) Power Management (drivers/pm) (3) Signals (sched/signal, arch/) @@ -307,69 +307,6 @@ o Task/Scheduler (sched/) o SMP ^^^ - Title: SMP ISSUES WITH task_restart() AND task_delete() - Description: The interface task_restart() (and probably task_delete()) are - not usable in the SMP configuration in the current design. In - the non-SMP case, these are relatively simple: If the task is - are not restarting/deleting itself, then the task to-be-restarted/ - deleted is is supended and the restart/delete operation is a - simple operation on data structures. - - In the SMP configuration, on the other hand, the task to be - restarted/deleted my in fact be executing concurrently on - another CPU and the existing logic cannot support those - operations on the running another CPU. - - There might be a simple way to handler this; perhaps using - up_cpu_pause(), you could pause all of the other CPUs, perform - the restart/delete operation, then restart all other CPUs. A - better solution would be a new interface like up_cpu_stop(). - This would be sent to all CPUs and if the task is running on - any of them, it would suspend the task and put it in the INVALID - state. - - But this seems like a lot of work to support some garbage - interfaces that really should be removed anyway. These are - unsafe, non-standard interfaces that really have no place in an - RTOS (unsafe because you don't know what resources were held - by the task when it was restarted or deleted). - - NOTE: Currently task_restart() is not even built if CONFIG_SMP=y. - The task_restart() test is also disabled in apps/examples/ostest - in this configuration. task_delete(), on the other hand, is - built (but probably should not be). - - Status: Open - Priority: Low. I do not plan to do anything with this in the near future. - - Title: SMP AND SIGNAL ACTIONS - Description: Suppose a task task is running on CPU1 and it is signaled from - another task running on CPU0. How does the signal handler run - on CPU1? I think it does not; I think that the signal will be - lost. I think all testing up to this point has used a task - waiting for a signal vs. a running task receiving a signal. - This case has never been tested, but I suspect an issues. - Here is why... this is the signal handling sequence: - - - sigueue() will set up the siginfo data structure and call - sig_dipatch(). - - sig_tcbdispach() or group_signal() depending on the - configuration. Let's assume the simpler sig_tcbdispatch(). - - sig_tcbdispatch() will call queue the signal action (via - sig_queueaction()) and then call the architecture-specific - up_schedule_signaction set up the invoke the signal handler - (for example in arch/arm/src/armv7-m/up_schedulesigaction.c). - - sig_queueaction() will assume that the other task is not - running and will simply modify data structures in the TCB. - This, will have no effect if the task is running and the - signal action will not be performed. - - This is really a variant of the problem described above under - "SMP ISSUES WITH task_restart() AND task_delete()" and the - same proposed solution applies: Call up_cpu_pause() to stop - all other CPUs before up_schedule_signaction runs. - Status: Open - Priority: High. This must be fixed. Title: SPINLOCKS AND DATA CACHES Description: If spinlocks are used in a system with a data cache, then there diff --git a/include/sched.h b/include/sched.h index c12bf99d54..31526f923e 100644 --- a/include/sched.h +++ b/include/sched.h @@ -227,9 +227,7 @@ int task_create(FAR const char *name, int priority, int stack_size, main_t entry, FAR char * const argv[]); #endif int task_delete(pid_t pid); -#ifndef CONFIG_SMP /* Not yet supported for the SMP case */ int task_restart(pid_t pid); -#endif /* Task Scheduling Interfaces (based on POSIX APIs) */ diff --git a/sched/sched/Make.defs b/sched/sched/Make.defs index 353f26bb27..0626d9e39b 100644 --- a/sched/sched/Make.defs +++ b/sched/sched/Make.defs @@ -50,7 +50,8 @@ CSRCS += sched_reprioritize.c endif ifeq ($(CONFIG_SMP),y) -CSRCS += sched_getaffinity.c sched_setaffinity.c sched_cpuselect.c +CSRCS += sched_cpuselect.c sched_cpupause.c +CSRCS += sched_getaffinity.c sched_setaffinity.c endif ifeq ($(CONFIG_SCHED_WAITPID),y) diff --git a/sched/sched/sched.h b/sched/sched/sched.h index 2b62e9f660..9e4bd64ba3 100644 --- a/sched/sched/sched.h +++ b/sched/sched/sched.h @@ -419,12 +419,13 @@ void sched_sporadic_lowpriority(FAR struct tcb_s *tcb); #endif #ifdef CONFIG_SMP -int sched_cpu_select(cpu_set_t affinity); +int sched_cpu_select(cpu_set_t affinity); +int sched_cpu_pause(FAR struct tcb_s *tcb); # define sched_islocked(tcb) spin_islocked(&g_cpu_schedlock) #else -# define sched_islocked(tcb) ((tcb)->lockcount > 0) # define sched_cpu_select(a) (0) - +# define sched_cpu_pause(t) (-38) /* -ENOSYS */ +# define sched_islocked(tcb) ((tcb)->lockcount > 0) #endif /* CPU load measurement support */ diff --git a/sched/sched/sched_cpupause.c b/sched/sched/sched_cpupause.c new file mode 100644 index 0000000000..0233bc064f --- /dev/null +++ b/sched/sched/sched_cpupause.c @@ -0,0 +1,119 @@ +/**************************************************************************** + * sched/sched/sched_cpupause.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "sched/sched.h" + +#ifdef CONFIG_SMP + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sched_cpu_pause + * + * Description: + * Check if task associated with 'tcb' is running on a different CPU. If + * so then pause that CPU and return its CPU index. + * + * Input Parameters: + * tcb - The TCB of the task to be conditionally paused. + * + * Returned Value: + * If a CPU is pauses its non-negative CPU index is returned. This index + * may then be used to resume the CPU. If the task is not running at all + * (or if an error occurs), then a negated errno value is returned. -ESRCH + * is returned in the case where the task is not running on any CPU. + * + * Assumptions: + * This function was called in a critical section. In that case, no tasks + * may started or may exit until the we leave the critical section. This + * critical section should extend until up_cpu_resume() is called in the + * typical case. + * + ****************************************************************************/ + +int sched_cpu_pause(FAR struct tcb_s *tcb) +{ + int cpu; + int ret; + + DEBUGASSERT(tcb != NULL); + + /* If the task is not running at all then our job is easy */ + + cpu = tcb->cpu; + if (tcb->task_state != TSTATE_TASK_RUNNING) + { + return -ESRCH; + } + + /* Check the CPU that the task is running on */ + + DEBUGASSERT(cpu != this_cpu() && (unsigned int)cpu < CONFIG_SMP_NCPUS); + if (cpu == this_cpu()) + { + /* We can't pause ourself */ + + return -EACCES; + } + + /* Pause the CPU that the task is running on */ + + ret = up_cpu_pause(cpu); + if (ret < 0) + { + return ret; + } + + /* Return the CPU that the task is running on */ + + return cpu; +} + +#endif /* CONFIG_SMP */ + diff --git a/sched/signal/sig_dispatch.c b/sched/signal/sig_dispatch.c index 31ce56d9eb..4399dc01f5 100644 --- a/sched/signal/sig_dispatch.c +++ b/sched/signal/sig_dispatch.c @@ -345,22 +345,48 @@ int sig_tcbdispatch(FAR struct tcb_s *stcb, siginfo_t *info) else { +#ifdef CONFIG_SMP + int cpu; +#endif /* Queue any sigaction's requested by this task. */ ret = sig_queueaction(stcb, info); + /* Deliver of the signal must be performed in a critical section */ + + flags = enter_critical_section(); + +#ifdef CONFIG_SMP + /* If the thread is running on another CPU, then pause that CPU. We can + * then setup the for signal delivery on the running thread. When the + * CPU is resumed, the signal handler will then execute. + */ + + cpu = sched_cpu_pause(stcb); +#endif /* CONFIG_SMP */ + /* Then schedule execution of the signal handling action on the * recipient's thread. */ up_schedule_sigaction(stcb, sig_deliver); +#ifdef CONFIG_SMP + /* Resume the paused CPU (if any) */ + + if (cpu >= 0) + { + /* I am not yet sure how to handle a failure here. */ + + DEBUGVERIFY(up_cpu_resume(cpu)); + } +#endif /* CONFIG_SMP */ + /* Check if the task is waiting for an unmasked signal. If so, then * unblock it. This must be performed in a critical section because * signals can be queued from the interrupt level. */ - flags = enter_critical_section(); if (stcb->task_state == TSTATE_WAIT_SIG) { memcpy(&stcb->sigunbinfo, info, sizeof(siginfo_t)); diff --git a/sched/task/Make.defs b/sched/task/Make.defs index a9a85971e6..ddf3e972b7 100644 --- a/sched/task/Make.defs +++ b/sched/task/Make.defs @@ -35,13 +35,9 @@ CSRCS += task_create.c task_init.c task_setup.c task_activate.c CSRCS += task_start.c task_delete.c task_exit.c task_exithook.c -CSRCS += task_recover.c task_spawnparms.c task_terminate.c +CSRCS += task_recover.c task_restart.c task_spawnparms.c task_terminate.c CSRCS += task_getgroup.c task_prctl.c task_getpid.c exit.c -ifneq ($(CONFIG_SMP),y) -CSRCS += task_restart.c -endif - ifeq ($(CONFIG_ARCH_HAVE_VFORK),y) ifeq ($(CONFIG_SCHED_WAITPID),y) CSRCS += task_vfork.c diff --git a/sched/task/task_restart.c b/sched/task/task_restart.c index 9ca6d4e88d..068d0a47f7 100644 --- a/sched/task/task_restart.c +++ b/sched/task/task_restart.c @@ -51,8 +51,6 @@ #include "signal/signal.h" #include "task/task.h" -#ifndef CONFIG_SMP /* Not yet supported for the SMP case */ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -86,13 +84,10 @@ int task_restart(pid_t pid) FAR dq_queue_t *tasklist; irqstate_t flags; int errcode; - int status; - - /* Make sure this task does not become ready-to-run while we are futzing - * with its TCB - */ - - sched_lock(); +#ifdef CONFIG_SMP + int cpu; +#endif + int ret; /* Check if the task to restart is the calling task */ @@ -105,7 +100,15 @@ int task_restart(pid_t pid) goto errout_with_lock; } - /* We are restarting some other task than ourselves */ + /* We are restarting some other task than ourselves. Make sure that the + * task does not change its state while we are executing. In the single + * CPU state this could be done by disabling pre-emption. But we will + * a little stronger medicine on the SMP case: The task make be running + * on another CPU. + */ + + flags = enter_critical_section(); + /* Find for the TCB associated with matching pid */ tcb = (FAR struct task_tcb_s *)sched_gettcb(pid); @@ -122,22 +125,12 @@ int task_restart(pid_t pid) } #ifdef CONFIG_SMP - /* There is currently no capability to restart a task that is actively - * running on another CPU. This is not the calling task so if it is - * running, then it could only be running a a different CPU. - * - * Also, we will need some interlocks to assure that no tasks are - * rescheduled on any other CPU while we do this. + /* If the task is running on another CPU, then pause that CPU. We can + * then manipulate the TCB of the restarted task and when we resume the + * that CPU, the restart take effect. */ -#warning Missing SMP logic - if (tcb->cmn.task_state == TSTATE_TASK_RUNNING) - { - /* Not implemented */ - - errcode = ENOSYS; - goto errout_with_lock; - } + cpu = sched_cpu_pause(&tcb->cmn); #endif /* CONFIG_SMP */ /* Try to recover from any bad states */ @@ -160,10 +153,8 @@ int task_restart(pid_t pid) tasklist = TLIST_HEAD(tcb->cmn.task_state); #endif - flags = enter_critical_section(); dq_rem((FAR dq_entry_t *)tcb, tasklist); tcb->cmn.task_state = TSTATE_TASK_INVALID; - leave_critical_section(flags); /* Deallocate anything left in the TCB's queues */ @@ -193,23 +184,35 @@ int task_restart(pid_t pid) dq_addfirst((FAR dq_entry_t *)tcb, (FAR dq_queue_t *)&g_inactivetasks); tcb->cmn.task_state = TSTATE_TASK_INACTIVE; +#ifdef CONFIG_SMP + /* Resume the paused CPU (if any) */ + + if (cpu >= 0) + { + ret = up_cpu_resume(cpu); + if (ret < 0) + { + errcode = -ret; + goto errout_with_lock; + } + } +#endif /* CONFIG_SMP */ + /* Activate the task */ - status = task_activate((FAR struct tcb_s *)tcb); - if (status != OK) + ret = task_activate((FAR struct tcb_s *)tcb); + if (ret != OK) { (void)task_delete(pid); - errcode = -status; + errcode = -ret; goto errout_with_lock; } - sched_unlock(); + leave_critical_section(flags); return OK; errout_with_lock: set_errno(errcode); - sched_unlock(); + leave_critical_section(flags); return ERROR; } - -#endif /* CONFIG_SMP */ diff --git a/sched/task/task_terminate.c b/sched/task/task_terminate.c index f9b115f8e4..4a42c8232e 100644 --- a/sched/task/task_terminate.c +++ b/sched/task/task_terminate.c @@ -103,12 +103,17 @@ int task_terminate(pid_t pid, bool nonblocking) FAR struct tcb_s *dtcb; FAR dq_queue_t *tasklist; irqstate_t flags; +#ifdef CONFIG_SMP + int cpu; +#endif + int ret; - /* Make sure the task does not become ready-to-run while we are futzing with - * its TCB by locking ourselves as the executing task. + /* Make sure the task does not become ready-to-run while we are futzing + * with its TCB. Within the critical section, no new task may be started + * or terminated (even in the SMP case). */ - sched_lock(); + flags = enter_critical_section(); /* Find for the TCB associated with matching PID */ @@ -117,26 +122,60 @@ int task_terminate(pid_t pid, bool nonblocking) { /* This PID does not correspond to any known task */ - sched_unlock(); - return -ESRCH; + ret = -ESRCH; + goto errout_with_lock; } + /* Verify our internal sanity */ + +#ifdef CONFIG_SMP + DEBUGASSERT(dtcb->task_state < NUM_TASK_STATES); +#else + DEBUGASSERT(dtcb->task_state != TSTATE_TASK_RUNNING && + dtcb->task_state < NUM_TASK_STATES); +#endif + + /* Remove the task from the OS's task lists. We must be in a critical + * section and the must must not be running to do this. + */ + #ifdef CONFIG_SMP - /* We will need some interlocks to assure that no tasks are rescheduled - * on any other CPU while we do this. + /* In the SMP case, the thread may be running on another CPU. If that is + * the case, then we will pause the CPU that the thread is running on. */ -# warning Missing SMP logic + cpu = sched_cpu_pause(dtcb); + + /* Get the task list associated with the the thread's state and CPU */ + + tasklist = TLIST_HEAD(dtcb->task_state, cpu); +#else + /* In the non-SMP case, we can be assured that the task to be terminated + * is not running. get the task list associated with the task state. + */ + + tasklist = TLIST_HEAD(dtcb->task_state); #endif - /* Verify our internal sanity */ + /* Remove the task from the task list */ + + dq_rem((FAR dq_entry_t *)dtcb, tasklist); + dtcb->task_state = TSTATE_TASK_INVALID; + + /* At this point, the TCB should no longer be accessible to the system */ + +#ifdef CONFIG_SMP + /* Resume the paused CPU (if any) */ - if (dtcb->task_state == TSTATE_TASK_RUNNING || - dtcb->task_state >= NUM_TASK_STATES) + if (cpu >= 0) { - sched_unlock(); - PANIC(); + /* I am not yet sure how to handle a failure here. */ + + DEBUGVERIFY(up_cpu_resume(cpu)); } +#endif /* CONFIG_SMP */ + + leave_critical_section(flags); /* Perform common task termination logic (flushing streams, calling * functions registered by at_exit/on_exit, etc.). We need to do @@ -151,23 +190,6 @@ int task_terminate(pid_t pid, bool nonblocking) task_exithook(dtcb, EXIT_SUCCESS, nonblocking); - /* Remove the task from the OS's task lists. */ - -#ifdef CONFIG_SMP - tasklist = TLIST_HEAD(dtcb->task_state, dtcb->cpu); -#else - tasklist = TLIST_HEAD(dtcb->task_state); -#endif - - flags = enter_critical_section(); - dq_rem((FAR dq_entry_t *)dtcb, tasklist); - dtcb->task_state = TSTATE_TASK_INVALID; - leave_critical_section(flags); - - /* At this point, the TCB should no longer be accessible to the system */ - - sched_unlock(); - /* Since all tasks pass through this function as the final step in their * exit sequence, this is an appropriate place to inform any instrumentation * layer that the task no longer exists. @@ -178,4 +200,8 @@ int task_terminate(pid_t pid, bool nonblocking) /* Deallocate its TCB */ return sched_releasetcb(dtcb, dtcb->flags & TCB_FLAG_TTYPE_MASK); + +errout_with_lock: + leave_critical_section(flags); + return ret; } -- GitLab From 01ade4803a5722c5e8104cf7c959ee55d3cc2d27 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 20 Nov 2016 09:51:54 -0600 Subject: [PATCH 468/734] Update README and TODO list --- TODO | 41 +++++++++++++++++++++++++++-- configs/sabre-6quad/README.txt | 48 +++++++++++++++++++++++++--------- 2 files changed, 74 insertions(+), 15 deletions(-) diff --git a/TODO b/TODO index c0e268e3b0..252e195614 100644 --- a/TODO +++ b/TODO @@ -10,7 +10,7 @@ issues related to each board port. nuttx/: (13) Task/Scheduler (sched/) - (1) SMP + (2) SMP (1) Memory Management (mm/) (1) Power Management (drivers/pm) (3) Signals (sched/signal, arch/) @@ -324,13 +324,50 @@ o SMP The better option is to add compiler independent "ornamentation" to the spinlock so that the spinlocks are all linked together into a separate, non-cacheable memory regions. Because of - region aligment and minimum region mapping sizes this could + region alignment and minimum region mapping sizes this could still be wasteful of memory. This would work in systems that have both data cache and either an MPU or an MMU. Status: Open Priority: High. spinlocks, and hence SMP, will not work on such systems without this change. + Title: DEADLOCK SCENARIO WITH up_cpu_pause(). + Description: I think there is a possibilty for a hang in up_cpu_pause(). + Suppose this situation: + + - CPU1 is in a critical section and has the g_cpu_irqlock + spinlock. + - CPU0 takes an interrupt and attempts to enter the critical + section. It spins waiting on g_cpu_irqlock with interrupt + disabled. + - CPU1 calls up_cpu_pause() to pause operation on CPU1. This + will issue an inter-CPU interrupt to CPU0 + - But interrupts are disabled. What will happen? I think + that this is a deadlock: Interrupts will stay disabled on + CPU0 because it is spinning in the interrupt handler; + up_cpu_pause() will hang becuase the inter-CPU interrupt + is pending. + + Are inter-CPU interrupts maskable in the same way as other + interrupts? If the are not-maskable, then we must also handle + them as nested interrupts in some fashion. + + A work-around might be to check the state of other-CPU + interrupt handler inside the spin loop of up_cpu_pause(). + Having the other CPU spinning and waiting for up_cpu_pause() + provided that (1) the pending interrupt can be cleared, and + (2) leave_critical_section() is not called prior to the point + where up_cpu_resume() is called, and (3) up_cpu_resume() is + smart enough to know that it should not attempt to resume a + non-paused CPU. + + This would require some kind of information about each + interrupt handler: In an interrupt, waiting for spinlock, + have spinlock, etc. + + Status: Open + Priority: Medium-High. I don't know for certain that this is a problem but it seems like it could + o Memory Management (mm/) ^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/configs/sabre-6quad/README.txt b/configs/sabre-6quad/README.txt index 4284c6de2a..72bb78f952 100644 --- a/configs/sabre-6quad/README.txt +++ b/configs/sabre-6quad/README.txt @@ -495,14 +495,12 @@ Open Issues: 1. Currently all device interrupts are handled on CPU0 only. Critical sections will attempt to disable interrupts but will now disable interrupts only on the current - CPU (which may not be CPU0). Perhaps that should be a spinlock to prohibit - execution of interrupts on CPU0 when other CPUs are in a critical section? + CPU (which may not be CPU0). There is a spinlock to prohibit entrance into these critical sections in interrupt handlers of other CPUs. - 2016-11-17: A fix was added to sched/irq/irq_csection that should correct this - problem. When the critical section is used to lock a resource that is also used by - interupt handling, the interrupt handling logic must also take the spinlock. This - will cause the interrupt handlers on other CPUs to spin until leave_critical_section() - is called. More verification is needed, however. + When the critical section is used to lock a resource that is also used by + interupt handling, the interrupt handling logic must also take the spinlock. + This will cause the interrupt handlers on other CPUs to spin until + leave_critical_section() is called. More verification is needed, however. 2. Cache Concurency. This is a complex problem. There is logic in place now to clean CPU0 D-cache before starting a new CPU and for invalidating the D-Cache @@ -551,16 +549,40 @@ Open Issues: spinlock "g_cpu_paused[cpu]". CPU1 correctly sets g_cpu_paused[cpu] to zero but CPU0 never sees the change. -3. Assertions. On a fatal assertions, other CPUs need to be stopped. The SCR, +3. Caching probabaly interferes with spinlocks as they are currently implemented. + Waiting on a cached copy of the spinlock may result in a hang or a failure to + wait. + + Should all spinlocks go into a special "strongly ordered" memory region? + +5. Assertions. On a fatal assertions, other CPUs need to be stopped. The SCR, however, only supports disabling CPUs 1 through 3. Perhaps if the assertion occurs on CPUn, n > 0, then it should use and SGI to perform the assertion on CPU0 always. From CPU0, CPU1-3 can be disabled. -4. Caching probabaly interferes with spinlocks as they are currently implemented. - Waiting on a cached copy of the spinlock may result in a hang or a failure to - wait. - -5. Do spinlocks need to go into a special "strongly ordered" memory region? +6. I think there is a possibilty for a hang in up_cpu_pause(). Suppose this + situation: + + - CPU1 is in a critical section and has the g_cpu_irqlock spinlock. + - CPU0 takes an interrupt and attempts to enter the critical section. It + spins waiting on g_cpu_irqlock with interrupt disabled. + - CPU1 calls up_cpu_pause() to pause operation on CPU1. This will issue + an inter-CPU interrupt to CPU0 + - But interrupts are disabled. What will happen? I think that this is + a deadlock: Interrupts will stay disabled on CPU0 because it is spinning + in the interrupt handler; up_cpu_pause() will hang becuase the inter- + CPU interrupt is pending. + + Are inter-CPU interrupts maskable in the same way as other interrupts? If + the are not-maskable, then we must also handle them as nested interrupts + in some fashion. + + A work-around might be to check the state of other-CPU interrupt handler + inside the spin loop of up_cpu_pause(). Having the other CPU spinning and + waiting for up_cpu_pause() provided that (1) the pending interrupt can be + cleared, and (2) leave_critical_section() is not called prior to the point + where up_cpu_resume() is called, and (3) up_cpu_resume() is smart enough + to know that it should not attempt to resume a non-paused CPU. Configurations ============== -- GitLab From cee8d59b5884264c473f1ba6a02860c823c090ac Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 20 Nov 2016 12:26:08 -0600 Subject: [PATCH 469/734] Update TODO list --- TODO | 5 +++++ sched/sched/sched_cpupause.c | 1 - 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/TODO b/TODO index 252e195614..77fb109fe4 100644 --- a/TODO +++ b/TODO @@ -321,6 +321,11 @@ o SMP unless the spinlocks were made to be the same size as one cache line. + This might be doable if a write-through cache is used. Then you + could always safely invalidate the cache line before reading the + spinlock because there should never be any dirty cache lines in + this case. + The better option is to add compiler independent "ornamentation" to the spinlock so that the spinlocks are all linked together into a separate, non-cacheable memory regions. Because of diff --git a/sched/sched/sched_cpupause.c b/sched/sched/sched_cpupause.c index 0233bc064f..513e8deb48 100644 --- a/sched/sched/sched_cpupause.c +++ b/sched/sched/sched_cpupause.c @@ -116,4 +116,3 @@ int sched_cpu_pause(FAR struct tcb_s *tcb) } #endif /* CONFIG_SMP */ - -- GitLab From d83ad6296c733a459b4f1ebcb19a2f968eb9071f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 20 Nov 2016 16:12:58 -0600 Subject: [PATCH 470/734] Update README --- configs/sabre-6quad/README.txt | 27 +++------------------------ 1 file changed, 3 insertions(+), 24 deletions(-) diff --git a/configs/sabre-6quad/README.txt b/configs/sabre-6quad/README.txt index 72bb78f952..02e6acb6ec 100644 --- a/configs/sabre-6quad/README.txt +++ b/configs/sabre-6quad/README.txt @@ -555,35 +555,14 @@ Open Issues: Should all spinlocks go into a special "strongly ordered" memory region? + Update: Cache inconsistencies seem to be the root cause of all current SMP + issues. + 5. Assertions. On a fatal assertions, other CPUs need to be stopped. The SCR, however, only supports disabling CPUs 1 through 3. Perhaps if the assertion occurs on CPUn, n > 0, then it should use and SGI to perform the assertion on CPU0 always. From CPU0, CPU1-3 can be disabled. -6. I think there is a possibilty for a hang in up_cpu_pause(). Suppose this - situation: - - - CPU1 is in a critical section and has the g_cpu_irqlock spinlock. - - CPU0 takes an interrupt and attempts to enter the critical section. It - spins waiting on g_cpu_irqlock with interrupt disabled. - - CPU1 calls up_cpu_pause() to pause operation on CPU1. This will issue - an inter-CPU interrupt to CPU0 - - But interrupts are disabled. What will happen? I think that this is - a deadlock: Interrupts will stay disabled on CPU0 because it is spinning - in the interrupt handler; up_cpu_pause() will hang becuase the inter- - CPU interrupt is pending. - - Are inter-CPU interrupts maskable in the same way as other interrupts? If - the are not-maskable, then we must also handle them as nested interrupts - in some fashion. - - A work-around might be to check the state of other-CPU interrupt handler - inside the spin loop of up_cpu_pause(). Having the other CPU spinning and - waiting for up_cpu_pause() provided that (1) the pending interrupt can be - cleared, and (2) leave_critical_section() is not called prior to the point - where up_cpu_resume() is called, and (3) up_cpu_resume() is smart enough - to know that it should not attempt to resume a non-paused CPU. - Configurations ============== -- GitLab From 0029c04dad88a8e26d0be3cba2a75ce1b59371ec Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 21 Nov 2016 07:33:23 -0600 Subject: [PATCH 471/734] task_restart: Make sure new task starts with pre-emption disabled and not in a critical section. --- sched/task/task_restart.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/sched/task/task_restart.c b/sched/task/task_restart.c index 068d0a47f7..36251348ed 100644 --- a/sched/task/task_restart.c +++ b/sched/task/task_restart.c @@ -164,6 +164,15 @@ int task_restart(pid_t pid) tcb->cmn.sched_priority = tcb->cmn.init_priority; + /* The task should restart with pre-emption disabled and not in a critical + * secton. + */ + + tcb->cmn.lockcount = 0; +#ifdef CONFIG_SMP + tcb->cmn.irqcount = 0; +#endif + /* Reset the base task priority and the number of pending reprioritizations */ #ifdef CONFIG_PRIORITY_INHERITANCE @@ -198,7 +207,9 @@ int task_restart(pid_t pid) } #endif /* CONFIG_SMP */ - /* Activate the task */ + leave_critical_section(flags); + + /* Activate the task. */ ret = task_activate((FAR struct tcb_s *)tcb); if (ret != OK) @@ -208,7 +219,6 @@ int task_restart(pid_t pid) goto errout_with_lock; } - leave_critical_section(flags); return OK; errout_with_lock: -- GitLab From 2d1765a01461b63470717cf1e8e9ddf41e3d4d27 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 21 Nov 2016 07:34:27 -0600 Subject: [PATCH 472/734] Remove more of those annoying empty comment blocks. --- sched/sched/sched_cpuload.c | 12 ------------ sched/task/task_getgroup.c | 20 -------------------- sched/task/task_init.c | 24 ------------------------ sched/task/task_posixspawn.c | 12 ------------ sched/task/task_spawn.c | 16 ---------------- sched/task/task_start.c | 20 -------------------- sched/task/task_starthook.c | 24 ------------------------ 7 files changed, 128 deletions(-) diff --git a/sched/sched/sched_cpuload.c b/sched/sched/sched_cpuload.c index 6cfe027bed..e78ccf2f08 100644 --- a/sched/sched/sched_cpuload.c +++ b/sched/sched/sched_cpuload.c @@ -65,14 +65,6 @@ # define CPULOAD_TICKSPERSEC CLOCKS_PER_SEC #endif -/**************************************************************************** - * Private Type Declarations - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - /**************************************************************************** * Private Data ****************************************************************************/ @@ -83,10 +75,6 @@ volatile uint32_t g_cpuload_total; -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/sched/task/task_getgroup.c b/sched/task/task_getgroup.c index 6b18aaac14..34f52c2c9c 100644 --- a/sched/task/task_getgroup.c +++ b/sched/task/task_getgroup.c @@ -47,26 +47,6 @@ #ifdef HAVE_TASK_GROUP -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/sched/task/task_init.c b/sched/task/task_init.c index 8583c1ecc3..42d4e31be4 100644 --- a/sched/task/task_init.c +++ b/sched/task/task_init.c @@ -50,30 +50,6 @@ #include "group/group.h" #include "task/task.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Type Declarations - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/sched/task/task_posixspawn.c b/sched/task/task_posixspawn.c index a185dd8ae1..9a91ab963b 100644 --- a/sched/task/task_posixspawn.c +++ b/sched/task/task_posixspawn.c @@ -52,18 +52,6 @@ #include "task/spawn.h" #include "task/task.h" -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ diff --git a/sched/task/task_spawn.c b/sched/task/task_spawn.c index b2ae31c1f3..af3051ac5c 100644 --- a/sched/task/task_spawn.c +++ b/sched/task/task_spawn.c @@ -51,22 +51,6 @@ #ifndef CONFIG_BUILD_KERNEL -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ diff --git a/sched/task/task_start.c b/sched/task/task_start.c index acff33e66c..262c8f0b72 100644 --- a/sched/task/task_start.c +++ b/sched/task/task_start.c @@ -58,26 +58,6 @@ #define MAX_START_ARGS 256 -/**************************************************************************** - * Private Type Declarations - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/sched/task/task_starthook.c b/sched/task/task_starthook.c index f102afc0a7..cc021ca30b 100644 --- a/sched/task/task_starthook.c +++ b/sched/task/task_starthook.c @@ -45,30 +45,6 @@ #ifdef CONFIG_SCHED_STARTHOOK -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Type Declarations - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ -- GitLab From 337d0f1050cfce9ff1f2fee9a818b71ad1148ac0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 21 Nov 2016 08:27:51 -0600 Subject: [PATCH 473/734] Fix a typo in a spinlock macro --- include/nuttx/spinlock.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/nuttx/spinlock.h b/include/nuttx/spinlock.h index c749d9e329..65786a0c6d 100644 --- a/include/nuttx/spinlock.h +++ b/include/nuttx/spinlock.h @@ -116,7 +116,7 @@ spinlock_t up_testset(volatile FAR spinlock_t *lock); ****************************************************************************/ /* void spin_initialize(FAR spinlock_t *lock); */ -#define spin_initialize(i) do { (l) = SPI_UNLOCKED; } while (0) +#define spin_initialize(i) do { (l) = SP_UNLOCKED; } while (0) /**************************************************************************** * Name: spin_initializer -- GitLab From 558784d06fbbe00ba695008e978e9596591e1f54 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 21 Nov 2016 11:55:59 -0600 Subject: [PATCH 474/734] Spinlocks: Added capability to provide architecture-specific memory barriers. This was for i.MX6 but does not help with the SMP problems. It is still a good feature. --- arch/arm/include/spinlock.h | 22 +++++++++++++++++ include/nuttx/spinlock.h | 7 ++++-- sched/semaphore/spinlock.c | 47 ++++++++++++++++++++++++++++++++++--- 3 files changed, 71 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/spinlock.h b/arch/arm/include/spinlock.h index 44e405e630..84800fbf8d 100644 --- a/arch/arm/include/spinlock.h +++ b/arch/arm/include/spinlock.h @@ -48,9 +48,31 @@ * Pre-processor Definitions ****************************************************************************/ +/* Spinlock states */ + #define SP_UNLOCKED 0 /* The Un-locked state */ #define SP_LOCKED 1 /* The Locked state */ +/* Memory barriers for use with NuttX spinlock logic */ + +#ifndef arm_isb +# define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory") +#endif + +#define SP_ISB() arm_isb(15) + +#ifndef arm_dsb +# define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory") +#endif + +#define SP_DSB() arm_dsb(15) + +#ifndef arm_dmb +# define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory") +#endif + +#define SP_DMB() arm_dmb(15) + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/include/nuttx/spinlock.h b/include/nuttx/spinlock.h index 65786a0c6d..0a9cc88a5e 100644 --- a/include/nuttx/spinlock.h +++ b/include/nuttx/spinlock.h @@ -203,8 +203,11 @@ void spin_lockr(FAR struct spinlock_s *lock); * ****************************************************************************/ -/* void spin_unlock(FAR spinlock_t *lock); */ -#define spin_unlock(l) do { *(l) = SP_UNLOCKED; } while (0) +#ifdef SP_DMB +void spin_unlock(FAR volatile spinlock_t *lock); +#else +# define spin_unlock(l) do { *(l) = SP_UNLOCKED; } while (0) +#endif /**************************************************************************** * Name: spin_unlockr diff --git a/sched/semaphore/spinlock.c b/sched/semaphore/spinlock.c index 79d904e7ef..a3c5225adf 100644 --- a/sched/semaphore/spinlock.c +++ b/sched/semaphore/spinlock.c @@ -65,6 +65,22 @@ #undef CONFIG_SPINLOCK_LOCKDOWN /* Feature not yet available */ +/* Memory barriers may be provided in arch/spinlock.h + * + * DMB - Data memory barrier. Assures writes are completed to memory. + * DSB - Data syncrhonization barrier. + */ + +#define HAVE_DMB 1 +#ifndef SP_DMB +# define SP_DMB() +# undef HAVE_DMB +#endif + +#ifndef SP_DSB +# define SP_DSB() +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -121,12 +137,37 @@ void spin_lock(FAR volatile spinlock_t *lock) { while (up_testset(lock) == SP_LOCKED) { -#if 0 /* Would recurse */ - sched_yield(); -#endif + SP_DSB(); } + + SP_DMB(); } +/**************************************************************************** + * Name: spin_unlock + * + * Description: + * Release one count on a non-reentrant spinlock. + * + * Input Parameters: + * lock - A reference to the spinlock object to unlock. + * + * Returned Value: + * None. + * + * Assumptions: + * Not running at the interrupt level. + * + ****************************************************************************/ + +#ifdef HAVE_DMB +void spin_unlock(FAR volatile spinlock_t *lock) +{ + *lock = SP_UNLOCKED; + SP_DMB(); +} +#endif + /**************************************************************************** * Name: spin_lockr * -- GitLab From f53e48199f0539a891e0b84e0b53d4dfe52939f0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 21 Nov 2016 13:12:43 -0600 Subject: [PATCH 475/734] Simplify and document some macros --- arch/arm/include/spinlock.h | 40 ++++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 18 deletions(-) diff --git a/arch/arm/include/spinlock.h b/arch/arm/include/spinlock.h index 84800fbf8d..45f26e0006 100644 --- a/arch/arm/include/spinlock.h +++ b/arch/arm/include/spinlock.h @@ -53,25 +53,29 @@ #define SP_UNLOCKED 0 /* The Un-locked state */ #define SP_LOCKED 1 /* The Locked state */ -/* Memory barriers for use with NuttX spinlock logic */ - -#ifndef arm_isb -# define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory") -#endif - -#define SP_ISB() arm_isb(15) - -#ifndef arm_dsb -# define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory") -#endif - -#define SP_DSB() arm_dsb(15) - -#ifndef arm_dmb -# define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory") -#endif +/* Memory barriers for use with NuttX spinlock logic + * + * Data Memory Barrier (DMB) acts as a memory barrier. It ensures that all + * explicit memory accesses that appear in program order before the DMB + * instruction are observed before any explicit memory accesses that appear + * in program order after the DMB instruction. It does not affect the + * ordering of any other instructions executing on the processor + * + * dmb st - Data memory barrier. Wait for stores to complete. + * + * Data Synchronization Barrier (DSB) acts as a special kind of memory + * barrier. No instruction in program order after this instruction executes + * until this instruction completes. This instruction completes when: (1) All + * explicit memory accesses before this instruction complete, and (2) all + * Cache, Branch predictor and TLB maintenance operations before this + * instruction complete. + * + * dsb sy - Data syncrhonization barrier. Assures that the CPU waits until + * all memory accesses are complete + */ -#define SP_DMB() arm_dmb(15) +#define SP_DSB(n) __asm__ __volatile__ ("dsb sy" : : : "memory") +#define SP_DMB(n) __asm__ __volatile__ ("dmb st" : : : "memory") /**************************************************************************** * Public Types -- GitLab From 130bfa3f6b92a9e219337db929c4860de7568059 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 21 Nov 2016 14:43:56 -0600 Subject: [PATCH 476/734] Remove a assertion condition that appears to rarely cause false-alarm assertions. Teported by Petteri Aimonen --- arch/arm/src/armv7-a/mmu.h | 1 - sched/sched/sched_roundrobin.c | 15 ++++++--------- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/arch/arm/src/armv7-a/mmu.h b/arch/arm/src/armv7-a/mmu.h index 9ce8280b73..c84deda619 100644 --- a/arch/arm/src/armv7-a/mmu.h +++ b/arch/arm/src/armv7-a/mmu.h @@ -513,7 +513,6 @@ * NMRR registers. For the simple case where TEX[2:0] = 0b000, the control * is as follows: * - * * MEMORY INNER OUTER OUTER SHAREABLE * C B TYPE CACHEABILITY CACHEABILITY ATTRIBUTE * - - ---------- ------------- ------------ ----------------- diff --git a/sched/sched/sched_roundrobin.c b/sched/sched/sched_roundrobin.c index bf856004d6..9aa5a6b8ed 100644 --- a/sched/sched/sched_roundrobin.c +++ b/sched/sched/sched_roundrobin.c @@ -105,23 +105,20 @@ uint32_t sched_roundrobin_process(FAR struct tcb_s *tcb, uint32_t ticks, /* How much can we decrement the timeslice delay? If 'ticks' is greater * than the timeslice value, then we ignore any excess amount. * - * 'ticks' should never be greater than the remaining timeslice. We try - * to handle that gracefully but it would be an error in the scheduling - * if there ever were the case. + * 'ticks' should not be greater than the remaining timeslice. But that + * event seems to be possible, perhaps in cases where pre-emption has been + * disabled or the noswitches flag is set. This might cause jitter of a + * few ticks in the slicing because the excess amount is not handled. */ - DEBUGASSERT(tcb != NULL && ticks <= tcb->timeslice); + DEBUGASSERT(tcb != NULL); decr = MIN(tcb->timeslice, ticks); /* Decrement the timeslice counter */ tcb->timeslice -= decr; - /* Did decrementing the timeslice counter cause the timeslice to expire? - * - * If the task has pre-emption disabled. Then we will let the timeslice - * count go negative as a indication of this situation. - */ + /* Did decrementing the timeslice counter cause the timeslice to expire? */ ret = tcb->timeslice; if (tcb->timeslice <= 0 && !sched_islocked(tcb)) -- GitLab From ef1fc550b7969daa8254b0888bf98601bcfd238d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 21 Nov 2016 15:05:54 -0600 Subject: [PATCH 477/734] Refresh viewtool configurations --- configs/viewtool-stm32f107/highpri/defconfig | 19 +++++++++++++++++ configs/viewtool-stm32f107/nsh/defconfig | 22 ++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/configs/viewtool-stm32f107/highpri/defconfig b/configs/viewtool-stm32f107/highpri/defconfig index be27c3afcf..81e2ca9c17 100644 --- a/configs/viewtool-stm32f107/highpri/defconfig +++ b/configs/viewtool-stm32f107/highpri/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -357,6 +360,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y # CONFIG_STM32_HAVE_CAN2 is not set CONFIG_STM32_HAVE_DAC1=y @@ -685,6 +694,8 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -692,6 +703,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -783,6 +795,7 @@ CONFIG_USART1_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -882,6 +895,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -927,7 +942,9 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -996,6 +1013,7 @@ CONFIG_ARCH_HAVE_TLS=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1040,6 +1058,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/viewtool-stm32f107/nsh/defconfig b/configs/viewtool-stm32f107/nsh/defconfig index 8de03f0714..1baa61b9fc 100644 --- a/configs/viewtool-stm32f107/nsh/defconfig +++ b/configs/viewtool-stm32f107/nsh/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -357,6 +360,12 @@ CONFIG_STM32_HAVE_ADC2=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -389,6 +398,7 @@ CONFIG_STM32_PWR=y # CONFIG_STM32_SPI1 is not set # CONFIG_STM32_SPI2 is not set # CONFIG_STM32_SPI3 is not set +CONFIG_STM32_SYSCFG=y # CONFIG_STM32_TIM1 is not set # CONFIG_STM32_TIM2 is not set # CONFIG_STM32_TIM3 is not set @@ -530,6 +540,7 @@ CONFIG_RAM_SIZE=65536 # CONFIG_ARCH_BOARD_CLOUDCTRL is not set # CONFIG_ARCH_BOARD_OLIMEX_STM32P107 is not set # CONFIG_ARCH_BOARD_SHENZHOU is not set +# CONFIG_ARCH_BOARD_STM32_BUTTERFLY2 is not set CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y # CONFIG_ARCH_BOARD_CUSTOM is not set CONFIG_ARCH_BOARD="viewtool-stm32f107" @@ -680,6 +691,8 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -687,6 +700,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -778,6 +792,7 @@ CONFIG_USART1_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -878,6 +893,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -928,7 +945,9 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -998,6 +1017,7 @@ CONFIG_EXAMPLES_NSH=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1069,6 +1089,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1136,6 +1157,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set -- GitLab From dfa2d107b2863d3860cc1dc608cab037ecd4f822 Mon Sep 17 00:00:00 2001 From: Sebastien Lorquet Date: Tue, 22 Nov 2016 06:26:32 -0600 Subject: [PATCH 478/734] The examples/qencoder app was trying to init the encoder by a direct call into the board, cheating in a local header to declare the normally unavailable function prototype. --- configs/mikroe-stm32f4/src/mikroe-stm32f4.h | 14 ++- configs/mikroe-stm32f4/src/stm32_appinit.c | 23 +++-- configs/mikroe-stm32f4/src/stm32_qencoder.c | 98 ++----------------- configs/nucleo-f4x1re/src/nucleo-f4x1re.h | 14 ++- configs/nucleo-f4x1re/src/stm32_appinit.c | 31 +++--- configs/nucleo-f4x1re/src/stm32_qencoder.c | 94 ++---------------- configs/nucleo-l476rg/src/nucleo-l476rg.h | 12 +++ configs/nucleo-l476rg/src/stm32_appinit.c | 13 +++ configs/nucleo-l476rg/src/stm32_qencoder.c | 92 ++--------------- configs/stm32f3discovery/src/stm32_appinit.c | 19 +++- configs/stm32f3discovery/src/stm32_qencoder.c | 98 ++----------------- .../stm32f3discovery/src/stm32f3discovery.h | 14 ++- configs/stm32f4discovery/src/stm32_bringup.c | 13 +++ configs/stm32f4discovery/src/stm32_qencoder.c | 92 ++--------------- .../stm32f4discovery/src/stm32f4discovery.h | 14 ++- configs/stm32ldiscovery/src/stm32_appinit.c | 29 ++++-- configs/stm32ldiscovery/src/stm32_qencoder.c | 95 ++---------------- configs/stm32ldiscovery/src/stm32ldiscovery.h | 14 ++- 18 files changed, 222 insertions(+), 557 deletions(-) diff --git a/configs/mikroe-stm32f4/src/mikroe-stm32f4.h b/configs/mikroe-stm32f4/src/mikroe-stm32f4.h index 473d0a61fb..20158043ed 100644 --- a/configs/mikroe-stm32f4/src/mikroe-stm32f4.h +++ b/configs/mikroe-stm32f4/src/mikroe-stm32f4.h @@ -1,7 +1,7 @@ /**************************************************************************************************** * configs/mikroe-stm32f4/src/mikroe-stm32f4.h * - * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -240,6 +240,18 @@ void weak_function stm32_usbinitialize(void); # error "The Mikroe-STM32F4 board does not support HOST OTG, only device!" #endif +/**************************************************************************** + * Name: stm32_qencoder_initialize + * + * Description: + * Initialize and register a qencoder + * + ****************************************************************************/ + +#ifdef CONFIG_QENCODER +int stm32_qencoder_initialize(FAR const char *devpath, int timer); +#endif + /**************************************************************************************************** * Name: stm32_lcdinitialize * diff --git a/configs/mikroe-stm32f4/src/stm32_appinit.c b/configs/mikroe-stm32f4/src/stm32_appinit.c index 5cb5d17665..cfc907dd03 100644 --- a/configs/mikroe-stm32f4/src/stm32_appinit.c +++ b/configs/mikroe-stm32f4/src/stm32_appinit.c @@ -180,11 +180,7 @@ int board_app_initialize(uintptr_t arg) FAR struct spi_dev_s *spi; FAR struct mtd_dev_s *mtd; #endif -#if defined(NSH_HAVEMMCSD) || defined(HAVE_USBHOST) || \ - defined(HAVE_USBMONITOR) || defined(CONFIG_LCD_MIO283QT2) || \ - defined(CONFIG_LCD_MIO283QT9A) - int ret; -#endif + int ret = OK; /* Configure SPI-based devices */ @@ -367,13 +363,24 @@ int board_app_initialize(uintptr_t arg) #endif - /* Configure the Audio sub-system if enabled and bind it to SPI 3 */ +#ifdef CONFIG_QENCODER + /* Initialize and register the qencoder driver */ + + ret = stm32_qencoder_initialize("/dev/qe0", 3); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif #ifdef CONFIG_AUDIO + /* Configure the Audio sub-system if enabled and bind it to SPI 3 */ up_vs1053initialize(spi); - #endif - return OK; + return ret; } diff --git a/configs/mikroe-stm32f4/src/stm32_qencoder.c b/configs/mikroe-stm32f4/src/stm32_qencoder.c index 33855fbaf5..43b45729e8 100644 --- a/configs/mikroe-stm32f4/src/stm32_qencoder.c +++ b/configs/mikroe-stm32f4/src/stm32_qencoder.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/mikroe_stm32f4/src/stm32_qencoder.c * - * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -50,83 +50,12 @@ #include "stm32_qencoder.h" #include "mikroe-stm32f4.h" -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ -/* Configuration *******************************************************************/ -/* Check if we have a timer configured for quadrature encoder -- assume YES. */ - -#define HAVE_QENCODER 1 - -/* If TIMn is not enabled (via CONFIG_STM32_TIMn), then the configuration cannot - * specify TIMn as a quadrature encoder (via CONFIG_STM32_TIMn_QE). - */ - -#ifndef CONFIG_STM32_TIM1 -# undef CONFIG_STM32_TIM1_QE -#endif -#ifndef CONFIG_STM32_TIM2 -# undef CONFIG_STM32_TIM2_QE -#endif -#ifndef CONFIG_STM32_TIM3 -# undef CONFIG_STM32_TIM3_QE -#endif -#ifndef CONFIG_STM32_TIM4 -# undef CONFIG_STM32_TIM4_QE -#endif -#ifndef CONFIG_STM32_TIM5 -# undef CONFIG_STM32_TIM5_QE -#endif -#ifndef CONFIG_STM32_TIM8 -# undef CONFIG_STM32_TIM8_QE -#endif - -/* If the upper-half quadrature encoder driver is not enabled, then we cannot - * support the quadrature encoder. - */ - -#ifndef CONFIG_QENCODER -# undef HAVE_QENCODER -#endif - -/* Which Timer should we use, TIMID={1,2,3,4,5,8}. If multiple timers are - * configured as quadrature encoders, this logic will arbitrarily select - * the lowest numbered timer. - * - * At least one TIMn, n={1,2,3,4,5,8}, must be both enabled and configured - * as a quadrature encoder in order to support the lower half quadrature - * encoder driver. The above check assures that if CONFIG_STM32_TIMn_QE - * is defined, then the correspdonding TIMn is also enabled. - */ - -#if defined CONFIG_STM32_TIM1_QE -# define TIMID 1 -#elif defined CONFIG_STM32_TIM2_QE -# define TIMID 2 -#elif defined CONFIG_STM32_TIM3_QE -# define TIMID 3 -#elif defined CONFIG_STM32_TIM4_QE -# define TIMID 4 -#elif defined CONFIG_STM32_TIM5_QE -# define TIMID 5 -#elif defined CONFIG_STM32_TIM8_QE -# define TIMID 8 -#else -# undef HAVE_QENCODER -#endif - -#ifdef HAVE_QENCODER - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: qe_devinit + * Name: stm32_qencoder_initialize * * Description: * All STM32 architectures must provide the following interface to work with @@ -134,29 +63,20 @@ * ************************************************************************************/ -int qe_devinit(void) +int stm32_qencoder_initialize(FAR const char *devpath, int timer) { - static bool initialized = false; int ret; - /* Check if we are already initialized */ + /* Initialize a quadrature encoder interface. */ - if (!initialized) + sninfo("Initializing the quadrature encoder using TIM%d\n", timer); + ret = stm32_qeinitialize(devpath, timer); + if (ret < 0) { - /* Initialize a quadrature encoder interface. */ - - sninfo("Initializing the quadrature encoder using TIM%d\n", TIMID); - ret = stm32_qeinitialize("/dev/qe0", TIMID); - if (ret < 0) - { - snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); - return ret; - } - - initialized = true; + snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); } - return OK; + return ret; } #endif /* HAVE_QENCODER */ diff --git a/configs/nucleo-f4x1re/src/nucleo-f4x1re.h b/configs/nucleo-f4x1re/src/nucleo-f4x1re.h index 21e5f7b09d..14d1c042c6 100644 --- a/configs/nucleo-f4x1re/src/nucleo-f4x1re.h +++ b/configs/nucleo-f4x1re/src/nucleo-f4x1re.h @@ -1,7 +1,7 @@ /************************************************************************************ * configs/nucleo-f4x1re/src/nucleo-f4x1re.h * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. * Authors: Frank Bennett * Gregory Nutt * @@ -320,6 +320,18 @@ void stm32_usbinitialize(void); int board_adc_initialize(void); #endif +/**************************************************************************** + * Name: stm32_qencoder_initialize + * + * Description: + * Initialize and register a qencoder + * + ****************************************************************************/ + +#ifdef CONFIG_QENCODER +int stm32_qencoder_initialize(FAR const char *devpath, int timer); +#endif + /**************************************************************************** * Name: board_ajoy_initialize * diff --git a/configs/nucleo-f4x1re/src/stm32_appinit.c b/configs/nucleo-f4x1re/src/stm32_appinit.c index 97cbc4ffc4..06df903438 100644 --- a/configs/nucleo-f4x1re/src/stm32_appinit.c +++ b/configs/nucleo-f4x1re/src/stm32_appinit.c @@ -55,18 +55,6 @@ #include "nucleo-f4x1re.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -112,9 +100,7 @@ void up_netinitialize(void) int board_app_initialize(uintptr_t arg) { -#if defined(HAVE_MMCSD) || defined(CONFIG_AJOYSTICK) - int ret; -#endif + int ret = OK; /* Configure CPU load estimation */ @@ -153,6 +139,19 @@ int board_app_initialize(uintptr_t arg) syslog(LOG_INFO, "[boot] Initialized SDIO\n"); #endif +#ifdef CONFIG_QENCODER + /* Initialize and register the qencoder driver */ + + ret = stm32_qencoder_initialize("/dev/qe0", 3); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + #ifdef CONFIG_AJOYSTICK /* Initialize and register the joystick driver */ @@ -166,5 +165,5 @@ int board_app_initialize(uintptr_t arg) } #endif - return OK; + return ret; } diff --git a/configs/nucleo-f4x1re/src/stm32_qencoder.c b/configs/nucleo-f4x1re/src/stm32_qencoder.c index 6d72932844..bac52a803e 100644 --- a/configs/nucleo-f4x1re/src/stm32_qencoder.c +++ b/configs/nucleo-f4x1re/src/stm32_qencoder.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/stm32f4discovery/src/stm32_qencoder.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -50,79 +50,12 @@ #include "stm32_qencoder.h" #include "nucleo-f4x1re.h" -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ -/* Configuration *******************************************************************/ -/* Check if we have a timer configured for quadrature encoder -- assume YES. */ - -#define HAVE_QENCODER 1 - -/* If TIMn is not enabled (via CONFIG_STM32_TIMn), then the configuration cannot - * specify TIMn as a quadrature encoder (via CONFIG_STM32_TIMn_QE). - */ - -#ifndef CONFIG_STM32_TIM1 -# undef CONFIG_STM32_TIM1_QE -#endif -#ifndef CONFIG_STM32_TIM2 -# undef CONFIG_STM32_TIM2_QE -#endif -#ifndef CONFIG_STM32_TIM3 -# undef CONFIG_STM32_TIM3_QE -#endif -#ifndef CONFIG_STM32_TIM4 -# undef CONFIG_STM32_TIM4_QE -#endif -#ifndef CONFIG_STM32_TIM5 -# undef CONFIG_STM32_TIM5_QE -#endif -#ifndef CONFIG_STM32_TIM8 -# undef CONFIG_STM32_TIM8_QE -#endif - -/* If the upper-half quadrature encoder driver is not enabled, then we cannot - * support the quadrature encoder. - */ - -#ifndef CONFIG_QENCODER -# undef HAVE_QENCODER -#endif - -/* Which Timer should we use, TIMID={1,2,3,4,5,8}. If multiple timers are - * configured as quadrature encoders, this logic will arbitrarily select - * the lowest numbered timer. - * - * At least one TIMn, n={1,2,3,4,5,8}, must be both enabled and configured - * as a quadrature encoder in order to support the lower half quadrature - * encoder driver. The above check assures that if CONFIG_STM32_TIMn_QE - * is defined, then the correspdonding TIMn is also enabled. - */ - -#if defined CONFIG_STM32_TIM1_QE -# define TIMID 1 -#elif defined CONFIG_STM32_TIM2_QE -# define TIMID 2 -#elif defined CONFIG_STM32_TIM3_QE -# define TIMID 3 -#elif defined CONFIG_STM32_TIM4_QE -# define TIMID 4 -#elif defined CONFIG_STM32_TIM5_QE -# define TIMID 5 -#elif defined CONFIG_STM32_TIM8_QE -# define TIMID 8 -#else -# undef HAVE_QENCODER -#endif - -#ifdef HAVE_QENCODER - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: qe_devinit + * Name: stm32_qencoder_initialize * * Description: * All STM32 architectures must provide the following interface to work with @@ -130,29 +63,20 @@ * ************************************************************************************/ -int qe_devinit(void) +int stm32_qencoder_initialize(FAR const char *devpath, int timer) { - static bool initialized = false; int ret; - /* Check if we are already initialized */ + /* Initialize a quadrature encoder interface. */ - if (!initialized) + sninfo("Initializing the quadrature encoder using TIM%d\n", timer); + ret = stm32_qeinitialize(devpath, timer); + if (ret < 0) { - /* Initialize a quadrature encoder interface. */ - - sninfo("Initializing the quadrature encoder using TIM%d\n", TIMID); - ret = stm32_qeinitialize("/dev/qe0", TIMID); - if (ret < 0) - { - snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); - return ret; - } - - initialized = true; + snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); } - return OK; + return ret; } #endif /* HAVE_QENCODER */ diff --git a/configs/nucleo-l476rg/src/nucleo-l476rg.h b/configs/nucleo-l476rg/src/nucleo-l476rg.h index 50151a3fe5..53915d0393 100644 --- a/configs/nucleo-l476rg/src/nucleo-l476rg.h +++ b/configs/nucleo-l476rg/src/nucleo-l476rg.h @@ -363,4 +363,16 @@ int board_ajoy_initialize(void); int board_timer_driver_initialize(FAR const char *devpath, int timer); #endif +/**************************************************************************** + * Name: stm32l4_qencoder_initialize + * + * Description: + * Initialize and register a qencoder + * + ****************************************************************************/ + +#ifdef CONFIG_QENCODER +int stm32l4_qencoder_initialize(FAR const char *devpath, int timer); +#endif + #endif /* __CONFIGS_NUCLEO_L476RG_SRC_NUCLEO_L476RG_H */ diff --git a/configs/nucleo-l476rg/src/stm32_appinit.c b/configs/nucleo-l476rg/src/stm32_appinit.c index bb134ee6aa..6b279bd7a5 100644 --- a/configs/nucleo-l476rg/src/stm32_appinit.c +++ b/configs/nucleo-l476rg/src/stm32_appinit.c @@ -218,6 +218,19 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_QENCODER + /* Initialize and register the qencoder driver */ + + ret = stm32l4_qencoder_initialize("/dev/qe0", 3); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + return OK; } diff --git a/configs/nucleo-l476rg/src/stm32_qencoder.c b/configs/nucleo-l476rg/src/stm32_qencoder.c index 308b674477..d12f077ef0 100644 --- a/configs/nucleo-l476rg/src/stm32_qencoder.c +++ b/configs/nucleo-l476rg/src/stm32_qencoder.c @@ -53,73 +53,6 @@ #include "stm32l4_qencoder.h" #include "nucleo-l476rg.h" -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ -/* Configuration *******************************************************************/ -/* Check if we have a timer configured for quadrature encoder -- assume YES. */ - -#define HAVE_QENCODER 1 - -/* If TIMn is not enabled (via CONFIG_STM32L4_TIMn), then the configuration cannot - * specify TIMn as a quadrature encoder (via CONFIG_STM32L4_TIMn_QE). - */ - -#ifndef CONFIG_STM32L4_TIM1 -# undef CONFIG_STM32L4_TIM1_QE -#endif -#ifndef CONFIG_STM32L4_TIM2 -# undef CONFIG_STM32L4_TIM2_QE -#endif -#ifndef CONFIG_STM32L4_TIM3 -# undef CONFIG_STM32L4_TIM3_QE -#endif -#ifndef CONFIG_STM32L4_TIM4 -# undef CONFIG_STM32L4_TIM4_QE -#endif -#ifndef CONFIG_STM32L4_TIM5 -# undef CONFIG_STM32L4_TIM5_QE -#endif -#ifndef CONFIG_STM32L4_TIM8 -# undef CONFIG_STM32L4_TIM8_QE -#endif - -/* If the upper-half quadrature encoder driver is not enabled, then we cannot - * support the quadrature encoder. - */ - -#ifndef CONFIG_QENCODER -# undef HAVE_QENCODER -#endif - -/* Which Timer should we use, TIMID={1,2,3,4,5,8}. If multiple timers are - * configured as quadrature encoders, this logic will arbitrarily select - * the lowest numbered timer. - * - * At least one TIMn, n={1,2,3,4,5,8}, must be both enabled and configured - * as a quadrature encoder in order to support the lower half quadrature - * encoder driver. The above check assures that if CONFIG_STM32L4_TIMn_QE - * is defined, then the correspdonding TIMn is also enabled. - */ - -#if defined CONFIG_STM32L4_TIM1_QE -# define TIMID 1 -#elif defined CONFIG_STM32L4_TIM2_QE -# define TIMID 2 -#elif defined CONFIG_STM32L4_TIM3_QE -# define TIMID 3 -#elif defined CONFIG_STM32L4_TIM4_QE -# define TIMID 4 -#elif defined CONFIG_STM32L4_TIM5_QE -# define TIMID 5 -#elif defined CONFIG_STM32L4_TIM8_QE -# define TIMID 8 -#else -# undef HAVE_QENCODER -#endif - -#ifdef HAVE_QENCODER - /************************************************************************************ * Public Functions ************************************************************************************/ @@ -133,29 +66,18 @@ * ************************************************************************************/ -int qe_devinit(void) +int stm32l4_qencoder_initialize(FAR const char *devpath, int timer) { - static bool initialized = false; int ret; - /* Check if we are already initialized */ + /* Initialize a quadrature encoder interface. */ - if (!initialized) + sninfo("Initializing the quadrature encoder using TIM%d\n", timer); + ret = stm32l4_qeinitialize(devpath, timer); + if (ret < 0) { - /* Initialize a quadrature encoder interface. */ - - sninfo("Initializing the quadrature encoder using TIM%d\n", TIMID); - ret = stm32l4_qeinitialize("/dev/qe0", TIMID); - if (ret < 0) - { - snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); - return ret; - } - - initialized = true; + snerr("ERROR: stm32l4_qeinitialize failed: %d\n", ret); } - return OK; + return ret; } - -#endif /* HAVE_QENCODER */ diff --git a/configs/stm32f3discovery/src/stm32_appinit.c b/configs/stm32f3discovery/src/stm32_appinit.c index c95837c9c5..d4726c22b7 100644 --- a/configs/stm32f3discovery/src/stm32_appinit.c +++ b/configs/stm32f3discovery/src/stm32_appinit.c @@ -115,9 +115,9 @@ int board_app_initialize(uintptr_t arg) { -#ifdef HAVE_USBMONITOR - int ret; + int ret = OK; +#ifdef HAVE_USBMONITOR /* Start the USB Monitor */ ret = usbmonitor_start(); @@ -127,5 +127,18 @@ int board_app_initialize(uintptr_t arg) } #endif - return OK; +#ifdef CONFIG_QENCODER + /* Initialize and register the qencoder driver */ + + ret = stm32_qencoder_initialize("/dev/qe0", 3); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + + return ret; } diff --git a/configs/stm32f3discovery/src/stm32_qencoder.c b/configs/stm32f3discovery/src/stm32_qencoder.c index d4fa6051cc..76697af980 100644 --- a/configs/stm32f3discovery/src/stm32_qencoder.c +++ b/configs/stm32f3discovery/src/stm32_qencoder.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/stm32f3discovery/src/stm32_qencoder.c * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -50,83 +50,12 @@ #include "stm32_qencoder.h" #include "stm32f3discovery.h" -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ -/* Configuration *******************************************************************/ -/* Check if we have a timer configured for quadrature encoder -- assume YES. */ - -#define HAVE_QENCODER 1 - -/* If TIMn is not enabled (via CONFIG_STM32_TIMn), then the configuration cannot - * specify TIMn as a quadrature encoder (via CONFIG_STM32_TIMn_QE). - */ - -#ifndef CONFIG_STM32_TIM1 -# undef CONFIG_STM32_TIM1_QE -#endif -#ifndef CONFIG_STM32_TIM2 -# undef CONFIG_STM32_TIM2_QE -#endif -#ifndef CONFIG_STM32_TIM3 -# undef CONFIG_STM32_TIM3_QE -#endif -#ifndef CONFIG_STM32_TIM4 -# undef CONFIG_STM32_TIM4_QE -#endif -#ifndef CONFIG_STM32_TIM5 -# undef CONFIG_STM32_TIM5_QE -#endif -#ifndef CONFIG_STM32_TIM8 -# undef CONFIG_STM32_TIM8_QE -#endif - -/* If the upper-half quadrature encoder driver is not enabled, then we cannot - * support the quadrature encoder. - */ - -#ifndef CONFIG_QENCODER -# undef HAVE_QENCODER -#endif - -/* Which Timer should we use, TIMID={1,2,3,4,5,8}. If multiple timers are - * configured as quadrature encoders, this logic will arbitrarily select - * the lowest numbered timer. - * - * At least one TIMn, n={1,2,3,4,5,8}, must be both enabled and configured - * as a quadrature encoder in order to support the lower half quadrature - * encoder driver. The above check assures that if CONFIG_STM32_TIMn_QE - * is defined, then the correspdonding TIMn is also enabled. - */ - -#if defined CONFIG_STM32_TIM1_QE -# define TIMID 1 -#elif defined CONFIG_STM32_TIM2_QE -# define TIMID 2 -#elif defined CONFIG_STM32_TIM3_QE -# define TIMID 3 -#elif defined CONFIG_STM32_TIM4_QE -# define TIMID 4 -#elif defined CONFIG_STM32_TIM5_QE -# define TIMID 5 -#elif defined CONFIG_STM32_TIM8_QE -# define TIMID 8 -#else -# undef HAVE_QENCODER -#endif - -#ifdef HAVE_QENCODER - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: qe_devinit + * Name: stm32_qencoder_initialize * * Description: * All STM32 architectures must provide the following interface to work with @@ -134,29 +63,20 @@ * ************************************************************************************/ -int qe_devinit(void) +int stm32_qencoder_initialize(FAR const char *devpath, int timer) { - static bool initialized = false; int ret; - /* Check if we are already initialized */ + /* Initialize a quadrature encoder interface. */ - if (!initialized) + sninfo("Initializing the quadrature encoder using TIM%d\n", timer); + ret = stm32_qeinitialize(devpath, timer); + if (ret < 0) { - /* Initialize a quadrature encoder interface. */ - - sninfo("Initializing the quadrature encoder using TIM%d\n", TIMID); - ret = stm32_qeinitialize("/dev/qe0", TIMID); - if (ret < 0) - { - snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); - return ret; - } - - initialized = true; + snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); } - return OK; + return ret; } #endif /* HAVE_QENCODER */ diff --git a/configs/stm32f3discovery/src/stm32f3discovery.h b/configs/stm32f3discovery/src/stm32f3discovery.h index eb35061c01..5b2e2626a0 100644 --- a/configs/stm32f3discovery/src/stm32f3discovery.h +++ b/configs/stm32f3discovery/src/stm32f3discovery.h @@ -2,7 +2,7 @@ * configs/stm32f3discovery/src/stm32f3discovery.h * arch/arm/src/board/stm32f3discovery.n * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -162,6 +162,18 @@ void weak_function stm32_spidev_initialize(void); void weak_function stm32_usbinitialize(void); #endif +/**************************************************************************** + * Name: stm32_qencoder_initialize + * + * Description: + * Initialize and register a qencoder + * + ****************************************************************************/ + +#ifdef CONFIG_QENCODER +int stm32_qencoder_initialize(FAR const char *devpath, int timer); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_STM32F3DISCOVERY_SRC_STM32F3DISCOVERY_H */ diff --git a/configs/stm32f4discovery/src/stm32_bringup.c b/configs/stm32f4discovery/src/stm32_bringup.c index d0b002bb33..7805a71e05 100644 --- a/configs/stm32f4discovery/src/stm32_bringup.c +++ b/configs/stm32f4discovery/src/stm32_bringup.c @@ -159,6 +159,19 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_QENCODER + /* Initialize and register the qencoder driver */ + + ret = stm32_qencoder_initialize("/dev/qe0", 3); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + #ifdef HAVE_RTC_DRIVER /* Instantiate the STM32 lower-half RTC driver */ diff --git a/configs/stm32f4discovery/src/stm32_qencoder.c b/configs/stm32f4discovery/src/stm32_qencoder.c index 5d0ae6460a..9a8af84ddd 100644 --- a/configs/stm32f4discovery/src/stm32_qencoder.c +++ b/configs/stm32f4discovery/src/stm32_qencoder.c @@ -50,79 +50,12 @@ #include "stm32_qencoder.h" #include "stm32f4discovery.h" -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ -/* Configuration *******************************************************************/ -/* Check if we have a timer configured for quadrature encoder -- assume YES. */ - -#define HAVE_QENCODER 1 - -/* If TIMn is not enabled (via CONFIG_STM32_TIMn), then the configuration cannot - * specify TIMn as a quadrature encoder (via CONFIG_STM32_TIMn_QE). - */ - -#ifndef CONFIG_STM32_TIM1 -# undef CONFIG_STM32_TIM1_QE -#endif -#ifndef CONFIG_STM32_TIM2 -# undef CONFIG_STM32_TIM2_QE -#endif -#ifndef CONFIG_STM32_TIM3 -# undef CONFIG_STM32_TIM3_QE -#endif -#ifndef CONFIG_STM32_TIM4 -# undef CONFIG_STM32_TIM4_QE -#endif -#ifndef CONFIG_STM32_TIM5 -# undef CONFIG_STM32_TIM5_QE -#endif -#ifndef CONFIG_STM32_TIM8 -# undef CONFIG_STM32_TIM8_QE -#endif - -/* If the upper-half quadrature encoder driver is not enabled, then we cannot - * support the quadrature encoder. - */ - -#ifndef CONFIG_QENCODER -# undef HAVE_QENCODER -#endif - -/* Which Timer should we use, TIMID={1,2,3,4,5,8}. If multiple timers are - * configured as quadrature encoders, this logic will arbitrarily select - * the lowest numbered timer. - * - * At least one TIMn, n={1,2,3,4,5,8}, must be both enabled and configured - * as a quadrature encoder in order to support the lower half quadrature - * encoder driver. The above check assures that if CONFIG_STM32_TIMn_QE - * is defined, then the correspdonding TIMn is also enabled. - */ - -#if defined CONFIG_STM32_TIM1_QE -# define TIMID 1 -#elif defined CONFIG_STM32_TIM2_QE -# define TIMID 2 -#elif defined CONFIG_STM32_TIM3_QE -# define TIMID 3 -#elif defined CONFIG_STM32_TIM4_QE -# define TIMID 4 -#elif defined CONFIG_STM32_TIM5_QE -# define TIMID 5 -#elif defined CONFIG_STM32_TIM8_QE -# define TIMID 8 -#else -# undef HAVE_QENCODER -#endif - -#ifdef HAVE_QENCODER - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: qe_devinit + * Name: stm32_qencoder_initialize * * Description: * All STM32 architectures must provide the following interface to work with @@ -130,29 +63,20 @@ * ************************************************************************************/ -int qe_devinit(void) +int stm32_qencoder_initialize(FAR const char *devpath, int timer) { - static bool initialized = false; int ret; - /* Check if we are already initialized */ + /* Initialize a quadrature encoder interface. */ - if (!initialized) + sninfo("Initializing the quadrature encoder using TIM%d\n", timer); + ret = stm32_qeinitialize(devpath, timer); + if (ret < 0) { - /* Initialize a quadrature encoder interface. */ - - sninfo("Initializing the quadrature encoder using TIM%d\n", TIMID); - ret = stm32_qeinitialize("/dev/qe0", TIMID); - if (ret < 0) - { - snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); - return ret; - } - - initialized = true; + snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); } - return OK; + return ret; } #endif /* HAVE_QENCODER */ diff --git a/configs/stm32f4discovery/src/stm32f4discovery.h b/configs/stm32f4discovery/src/stm32f4discovery.h index 50495addf3..2d4f7a617a 100644 --- a/configs/stm32f4discovery/src/stm32f4discovery.h +++ b/configs/stm32f4discovery/src/stm32f4discovery.h @@ -1,7 +1,7 @@ /**************************************************************************** * configs/stm32f4discovery/src/stm32f4discovery.h * - * Copyright (C) 2011-2012, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2012, 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -564,6 +564,18 @@ int stm32_sdio_initialize(void); void weak_function stm32_netinitialize(void); #endif +/**************************************************************************** + * Name: stm32_qencoder_initialize + * + * Description: + * Initialize and register a qencoder + * + ****************************************************************************/ + +#ifdef CONFIG_QENCODER +int stm32_qencoder_initialize(FAR const char *devpath, int timer); +#endif + /**************************************************************************** * Name: stm32_zerocross_initialize * diff --git a/configs/stm32ldiscovery/src/stm32_appinit.c b/configs/stm32ldiscovery/src/stm32_appinit.c index 359e271eb9..eb60217e5e 100644 --- a/configs/stm32ldiscovery/src/stm32_appinit.c +++ b/configs/stm32ldiscovery/src/stm32_appinit.c @@ -47,10 +47,6 @@ #include "stm32ldiscovery.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -82,11 +78,30 @@ int board_app_initialize(uintptr_t arg) { + int ret = OK; + #ifdef CONFIG_STM32_LCD /* Initialize the SLCD and register the SLCD device as /dev/slcd */ - return stm32_slcd_initialize(); -#else - return OK; + ret = stm32_slcd_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: stm32_slcd_initialize failed: %d\n", ret); + return ret; + } #endif + +#ifdef CONFIG_QENCODER + /* Initialize and register the qencoder driver */ + + ret = stm32_qencoder_initialize("/dev/qe0", 3); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + } +#endif + + return ret; } diff --git a/configs/stm32ldiscovery/src/stm32_qencoder.c b/configs/stm32ldiscovery/src/stm32_qencoder.c index ebd78514aa..7306b14127 100644 --- a/configs/stm32ldiscovery/src/stm32_qencoder.c +++ b/configs/stm32ldiscovery/src/stm32_qencoder.c @@ -1,8 +1,7 @@ /************************************************************************************ * configs/stm32ldiscovery/src/up_qencoder.c - * arch/arm/src/board/up_qencoder.c * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -51,79 +50,12 @@ #include "stm32_qencoder.h" #include "stm32ldiscovery.h" -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ -/* Configuration *******************************************************************/ -/* Check if we have a timer configured for quadrature encoder -- assume YES. */ - -#define HAVE_QENCODER 1 - -/* If TIMn is not enabled (via CONFIG_STM32_TIMn), then the configuration cannot - * specify TIMn as a quadrature encoder (via CONFIG_STM32_TIMn_QE). - */ - -#ifndef CONFIG_STM32_TIM1 -# undef CONFIG_STM32_TIM1_QE -#endif -#ifndef CONFIG_STM32_TIM2 -# undef CONFIG_STM32_TIM2_QE -#endif -#ifndef CONFIG_STM32_TIM3 -# undef CONFIG_STM32_TIM3_QE -#endif -#ifndef CONFIG_STM32_TIM4 -# undef CONFIG_STM32_TIM4_QE -#endif -#ifndef CONFIG_STM32_TIM5 -# undef CONFIG_STM32_TIM5_QE -#endif -#ifndef CONFIG_STM32_TIM8 -# undef CONFIG_STM32_TIM8_QE -#endif - -/* If the upper-half quadrature encoder driver is not enabled, then we cannot - * support the quadrature encoder. - */ - -#ifndef CONFIG_QENCODER -# undef HAVE_QENCODER -#endif - -/* Which Timer should we use, TIMID={1,2,3,4,5,8}. If multiple timers are - * configured as quadrature encoders, this logic will arbitrarily select - * the lowest numbered timer. - * - * At least one TIMn, n={1,2,3,4,5,8}, must be both enabled and configured - * as a quadrature encoder in order to support the lower half quadrature - * encoder driver. The above check assures that if CONFIG_STM32_TIMn_QE - * is defined, then the correspdonding TIMn is also enabled. - */ - -#if defined CONFIG_STM32_TIM1_QE -# define TIMID 1 -#elif defined CONFIG_STM32_TIM2_QE -# define TIMID 2 -#elif defined CONFIG_STM32_TIM3_QE -# define TIMID 3 -#elif defined CONFIG_STM32_TIM4_QE -# define TIMID 4 -#elif defined CONFIG_STM32_TIM5_QE -# define TIMID 5 -#elif defined CONFIG_STM32_TIM8_QE -# define TIMID 8 -#else -# undef HAVE_QENCODER -#endif - -#ifdef HAVE_QENCODER - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: qe_devinit + * Name: stm32_qencoder_initialize * * Description: * All STM32 architectures must provide the following interface to work with @@ -131,29 +63,20 @@ * ************************************************************************************/ -int qe_devinit(void) +int stm32_qencoder_initialize(FAR const char *devpath, int timer) { - static bool initialized = false; int ret; - /* Check if we are already initialized */ + /* Initialize a quadrature encoder interface. */ - if (!initialized) + sninfo("Initializing the quadrature encoder using TIM%d\n", timer); + ret = stm32_qeinitialize(devpath, timer); + if (ret < 0) { - /* Initialize a quadrature encoder interface. */ - - sninfo("Initializing the quadrature encoder using TIM%d\n", TIMID); - ret = stm32_qeinitialize("/dev/qe0", TIMID); - if (ret < 0) - { - snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); - return ret; - } - - initialized = true; + snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); } - return OK; + return ret; } #endif /* HAVE_QENCODER */ diff --git a/configs/stm32ldiscovery/src/stm32ldiscovery.h b/configs/stm32ldiscovery/src/stm32ldiscovery.h index 1bd424f376..bf2f34e16e 100644 --- a/configs/stm32ldiscovery/src/stm32ldiscovery.h +++ b/configs/stm32ldiscovery/src/stm32ldiscovery.h @@ -2,7 +2,7 @@ * configs/stm32ldiscovery/src/stm32ldiscovery.h * arch/arm/src/board/stm32ldiscovery.h * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -243,6 +243,18 @@ void weak_function stm32_spidev_initialize(void); +/**************************************************************************** + * Name: stm32_qencoder_initialize + * + * Description: + * Initialize and register a qencoder + * + ****************************************************************************/ + +#ifdef CONFIG_QENCODER +int stm32_qencoder_initialize(FAR const char *devpath, int timer); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_STM32F3DISCOVERY_SRC_STM32F3DISCOVERY_H */ -- GitLab From a0711b1c192b200f873f37bf66c9657adb6d2112 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 22 Nov 2016 06:41:46 -0600 Subject: [PATCH 479/734] configs: All QE encoder files. Last change made timer hard-coded to 3. Make configurable. --- configs/mikroe-stm32f4/Kconfig | 5 +++++ configs/mikroe-stm32f4/src/stm32_appinit.c | 2 +- configs/nucleo-f4x1re/Kconfig | 5 +++++ configs/nucleo-f4x1re/src/stm32_appinit.c | 2 +- configs/nucleo-l476rg/Kconfig | 5 +++++ configs/nucleo-l476rg/src/stm32_appinit.c | 2 +- configs/stm32f3discovery/Kconfig | 5 +++++ configs/stm32f3discovery/src/stm32_appinit.c | 2 +- configs/stm32f4discovery/Kconfig | 5 +++++ configs/stm32f4discovery/README.txt | 2 ++ configs/stm32f4discovery/src/stm32_bringup.c | 2 +- configs/stm32f4discovery/src/stm32_qencoder.c | 2 +- configs/stm32ldiscovery/Kconfig | 6 ++++++ configs/stm32ldiscovery/src/stm32_appinit.c | 2 +- 14 files changed, 40 insertions(+), 7 deletions(-) diff --git a/configs/mikroe-stm32f4/Kconfig b/configs/mikroe-stm32f4/Kconfig index 836f13cf2b..00a5e41ee4 100644 --- a/configs/mikroe-stm32f4/Kconfig +++ b/configs/mikroe-stm32f4/Kconfig @@ -76,6 +76,11 @@ config MIKROE_RAMMTD_SIZE ---help--- Sets the size of static RAM allocation for the SMART RAM device +config MIKROE_QETIMER + int "Timer to use with QE encoder" + default 3 + depends on QENCODER + config PM_ALARM_SEC int "PM_STANDBY delay (seconds)" default 15 diff --git a/configs/mikroe-stm32f4/src/stm32_appinit.c b/configs/mikroe-stm32f4/src/stm32_appinit.c index cfc907dd03..89828b2872 100644 --- a/configs/mikroe-stm32f4/src/stm32_appinit.c +++ b/configs/mikroe-stm32f4/src/stm32_appinit.c @@ -366,7 +366,7 @@ int board_app_initialize(uintptr_t arg) #ifdef CONFIG_QENCODER /* Initialize and register the qencoder driver */ - ret = stm32_qencoder_initialize("/dev/qe0", 3); + ret = stm32_qencoder_initialize("/dev/qe0", CONFIG_MIKROE_QETIMER); if (ret != OK) { syslog(LOG_ERR, diff --git a/configs/nucleo-f4x1re/Kconfig b/configs/nucleo-f4x1re/Kconfig index 6449f5b673..27e172d841 100644 --- a/configs/nucleo-f4x1re/Kconfig +++ b/configs/nucleo-f4x1re/Kconfig @@ -5,6 +5,11 @@ if ARCH_BOARD_NUCLEO_F401RE +config NUCLEO_F401RE_QETIMER + int "Timer to use with QE encoder" + default 3 + depends on QENCODER + config NUCLEO_F401RE_AJOY_MINBUTTONS bool "Minimal Joystick Buttons" default n if !STM32_USART1 diff --git a/configs/nucleo-f4x1re/src/stm32_appinit.c b/configs/nucleo-f4x1re/src/stm32_appinit.c index 06df903438..a55f6a3c51 100644 --- a/configs/nucleo-f4x1re/src/stm32_appinit.c +++ b/configs/nucleo-f4x1re/src/stm32_appinit.c @@ -142,7 +142,7 @@ int board_app_initialize(uintptr_t arg) #ifdef CONFIG_QENCODER /* Initialize and register the qencoder driver */ - ret = stm32_qencoder_initialize("/dev/qe0", 3); + ret = stm32_qencoder_initialize("/dev/qe0", CONFIG_NUCLEO_F401RE_QETIMER); if (ret != OK) { syslog(LOG_ERR, diff --git a/configs/nucleo-l476rg/Kconfig b/configs/nucleo-l476rg/Kconfig index 7361b3f490..8edd703e42 100644 --- a/configs/nucleo-l476rg/Kconfig +++ b/configs/nucleo-l476rg/Kconfig @@ -5,6 +5,11 @@ if ARCH_BOARD_NUCLEO_L476RG +config NUCLEO_L476RG_QETIMER + int "Timer to use with QE encoder" + default 3 + depends on QENCODER + config NUCLEO_L476RG_AJOY_MINBUTTONS bool "Minimal Joystick Buttons" default n if !STM32_USART1 diff --git a/configs/nucleo-l476rg/src/stm32_appinit.c b/configs/nucleo-l476rg/src/stm32_appinit.c index 6b279bd7a5..ceeca0eff3 100644 --- a/configs/nucleo-l476rg/src/stm32_appinit.c +++ b/configs/nucleo-l476rg/src/stm32_appinit.c @@ -221,7 +221,7 @@ int board_app_initialize(uintptr_t arg) #ifdef CONFIG_QENCODER /* Initialize and register the qencoder driver */ - ret = stm32l4_qencoder_initialize("/dev/qe0", 3); + ret = stm32l4_qencoder_initialize("/dev/qe0", CONFIG_NUCLEO_L476RG_QETIMER); if (ret != OK) { syslog(LOG_ERR, diff --git a/configs/stm32f3discovery/Kconfig b/configs/stm32f3discovery/Kconfig index de0d2da5f8..71e736df11 100644 --- a/configs/stm32f3discovery/Kconfig +++ b/configs/stm32f3discovery/Kconfig @@ -5,6 +5,11 @@ if ARCH_BOARD_STM32F3_DISCOVERY +config STM32F3DISCO_QETIMER + int "Timer to use with QE encoder" + default 3 + depends on QENCODER + config PM_BUTTONS bool "PM Button support" default n diff --git a/configs/stm32f3discovery/src/stm32_appinit.c b/configs/stm32f3discovery/src/stm32_appinit.c index d4726c22b7..68cb782539 100644 --- a/configs/stm32f3discovery/src/stm32_appinit.c +++ b/configs/stm32f3discovery/src/stm32_appinit.c @@ -130,7 +130,7 @@ int board_app_initialize(uintptr_t arg) #ifdef CONFIG_QENCODER /* Initialize and register the qencoder driver */ - ret = stm32_qencoder_initialize("/dev/qe0", 3); + ret = stm32_qencoder_initialize("/dev/qe0", CONFIG_STM32F3DISCO_QETIMER); if (ret != OK) { syslog(LOG_ERR, diff --git a/configs/stm32f4discovery/Kconfig b/configs/stm32f4discovery/Kconfig index 3c84095efc..9703364210 100644 --- a/configs/stm32f4discovery/Kconfig +++ b/configs/stm32f4discovery/Kconfig @@ -22,6 +22,11 @@ config STM32F4DISCO_USBHOST_PRIO default 100 depends on USBHOST +config STM32F4DISCO_QETIMER + int "Timer to use with QE encoder" + default 3 + depends on QENCODER + config PM_BUTTONS bool "PM button support" default n diff --git a/configs/stm32f4discovery/README.txt b/configs/stm32f4discovery/README.txt index 2b1bb2501f..aaa37fe7f7 100644 --- a/configs/stm32f4discovery/README.txt +++ b/configs/stm32f4discovery/README.txt @@ -456,6 +456,8 @@ pins PA15 and PA1 for CH1 and CH2, respectively). If TIM8 is selected, then PC6 and PI5 will be used for CH1 and CH2 (see include board.h for pin definitions). +Selected via CONFIG_STM32F4DISCO_QETIMER + FPU === diff --git a/configs/stm32f4discovery/src/stm32_bringup.c b/configs/stm32f4discovery/src/stm32_bringup.c index 7805a71e05..8a800d59f3 100644 --- a/configs/stm32f4discovery/src/stm32_bringup.c +++ b/configs/stm32f4discovery/src/stm32_bringup.c @@ -162,7 +162,7 @@ int stm32_bringup(void) #ifdef CONFIG_QENCODER /* Initialize and register the qencoder driver */ - ret = stm32_qencoder_initialize("/dev/qe0", 3); + ret = stm32_qencoder_initialize("/dev/qe0", CONFIG_STM32F4DISCO_QETIMER); if (ret != OK) { syslog(LOG_ERR, diff --git a/configs/stm32f4discovery/src/stm32_qencoder.c b/configs/stm32f4discovery/src/stm32_qencoder.c index 9a8af84ddd..80264a7a2a 100644 --- a/configs/stm32f4discovery/src/stm32_qencoder.c +++ b/configs/stm32f4discovery/src/stm32_qencoder.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/stm32f4discovery/src/stm32_qencoder.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without diff --git a/configs/stm32ldiscovery/Kconfig b/configs/stm32ldiscovery/Kconfig index 2d37b4e88d..34e1f83388 100644 --- a/configs/stm32ldiscovery/Kconfig +++ b/configs/stm32ldiscovery/Kconfig @@ -4,4 +4,10 @@ # if ARCH_BOARD_STM32FL_DISCOVERY + +config STM32LDISCO_QETIMER + int "Timer to use with QE encoder" + default 3 + depends on QENCODER + endif diff --git a/configs/stm32ldiscovery/src/stm32_appinit.c b/configs/stm32ldiscovery/src/stm32_appinit.c index eb60217e5e..b0f4909a2e 100644 --- a/configs/stm32ldiscovery/src/stm32_appinit.c +++ b/configs/stm32ldiscovery/src/stm32_appinit.c @@ -94,7 +94,7 @@ int board_app_initialize(uintptr_t arg) #ifdef CONFIG_QENCODER /* Initialize and register the qencoder driver */ - ret = stm32_qencoder_initialize("/dev/qe0", 3); + ret = stm32_qencoder_initialize("/dev/qe0", CONFIG_STM32LDISCO_QETIMER); if (ret != OK) { syslog(LOG_ERR, -- GitLab From 8eec4ab0e8ac6b4c07cbf92b4bae5d624f251743 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 22 Nov 2016 06:58:34 -0600 Subject: [PATCH 480/734] Eliminate a warning --- include/nuttx/sensors/veml6070.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/nuttx/sensors/veml6070.h b/include/nuttx/sensors/veml6070.h index a143f1ee8d..487eb53959 100644 --- a/include/nuttx/sensors/veml6070.h +++ b/include/nuttx/sensors/veml6070.h @@ -109,6 +109,7 @@ extern "C" * ****************************************************************************/ +struct i2c_master_s; int veml6070_register(FAR const char *devpath, FAR struct i2c_master_s *i2c, uint8_t addr); -- GitLab From 7825dbb3a15aaa33bca6783fcee1e67d83a2a30f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 22 Nov 2016 07:23:23 -0600 Subject: [PATCH 481/734] configs: Remove all button configurations that depended on the obsoleted ARCHBUTTON example --- configs/hymini-stm32v/README.txt | 8 - configs/hymini-stm32v/buttons/Make.defs | 117 --- configs/hymini-stm32v/buttons/defconfig | 1050 ---------------------- configs/hymini-stm32v/buttons/setenv.sh | 47 - configs/stm3210e-eval/README.txt | 8 - configs/stm3210e-eval/buttons/Make.defs | 117 --- configs/stm3210e-eval/buttons/defconfig | 1056 ----------------------- configs/stm3210e-eval/buttons/setenv.sh | 47 - 8 files changed, 2450 deletions(-) delete mode 100644 configs/hymini-stm32v/buttons/Make.defs delete mode 100644 configs/hymini-stm32v/buttons/defconfig delete mode 100755 configs/hymini-stm32v/buttons/setenv.sh delete mode 100644 configs/stm3210e-eval/buttons/Make.defs delete mode 100644 configs/stm3210e-eval/buttons/defconfig delete mode 100755 configs/stm3210e-eval/buttons/setenv.sh diff --git a/configs/hymini-stm32v/README.txt b/configs/hymini-stm32v/README.txt index e6643aaed3..2a804a43a6 100644 --- a/configs/hymini-stm32v/README.txt +++ b/configs/hymini-stm32v/README.txt @@ -561,14 +561,6 @@ can be selected as follow: Where is one of the following: - buttons: - -------- - - Uses apps/examples/buttons to exercise HY-MiniSTM32V buttons and - button interrupts. - - CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y : Generic GNU EABI toolchain - nsh and nsh2: ------------ Configure the NuttShell (nsh) located at examples/nsh. diff --git a/configs/hymini-stm32v/buttons/Make.defs b/configs/hymini-stm32v/buttons/Make.defs deleted file mode 100644 index 8a2b9857ab..0000000000 --- a/configs/hymini-stm32v/buttons/Make.defs +++ /dev/null @@ -1,117 +0,0 @@ -############################################################################ -# configs/hymini-stm32v/buttons/Make.defs -# -# Copyright (C) 2011, 2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk -include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ifeq ($(WINTOOL),y) - # Windows-native toolchains - DIRLINK = $(TOPDIR)/tools/copydir.sh - DIRUNLINK = $(TOPDIR)/tools/unlink.sh - MKDEP = $(TOPDIR)/tools/mkwindeps.sh - ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" - ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" - ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" -else - # Linux/Cygwin-native toolchain - MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) - ARCHINCLUDES = -I. -isystem $(TOPDIR)/include - ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx - ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) -endif - -CC = $(CROSSDEV)gcc -CXX = $(CROSSDEV)g++ -CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld -AR = $(CROSSDEV)ar rcs -NM = $(CROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} -ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION = -g -endif - -ifneq ($(CONFIG_DEBUG_NOOPT),y) - ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer -endif - -ARCHCFLAGS = -fno-builtin -ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -ARCHWARNINGSXX = -Wall -Wshadow -Wundef -ARCHDEFINES = -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -AFLAGS = $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -ASMEXT = .S -OBJEXT = .o -LIBEXT = .a -EXEEXT = - -ifneq ($(CROSSDEV),arm-nuttx-elf-) - LDFLAGS += -nostartfiles -nodefaultlibs -endif -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - LDFLAGS += -g -endif - - -HOSTCC = gcc -HOSTINCLUDES = -I. -HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe -HOSTLDFLAGS = - diff --git a/configs/hymini-stm32v/buttons/defconfig b/configs/hymini-stm32v/buttons/defconfig deleted file mode 100644 index c314821a14..0000000000 --- a/configs/hymini-stm32v/buttons/defconfig +++ /dev/null @@ -1,1050 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Nuttx/ Configuration -# - -# -# Build Setup -# -# CONFIG_EXPERIMENTAL is not set -# CONFIG_DEFAULT_SMALL is not set -CONFIG_HOST_LINUX=y -# CONFIG_HOST_OSX is not set -# CONFIG_HOST_WINDOWS is not set -# CONFIG_HOST_OTHER is not set - -# -# Build Configuration -# -# CONFIG_APPS_DIR="../apps" -CONFIG_BUILD_FLAT=y -# CONFIG_BUILD_2PASS is not set - -# -# Binary Output Formats -# -# CONFIG_RRLOAD_BINARY is not set -# CONFIG_INTELHEX_BINARY is not set -# CONFIG_MOTOROLA_SREC is not set -CONFIG_RAW_BINARY=y -# CONFIG_UBOOT_UIMAGE is not set - -# -# Customize Header Files -# -# CONFIG_ARCH_STDINT_H is not set -# CONFIG_ARCH_STDBOOL_H is not set -# CONFIG_ARCH_MATH_H is not set -# CONFIG_ARCH_FLOAT_H is not set -# CONFIG_ARCH_STDARG_H is not set -# CONFIG_ARCH_DEBUG_H is not set - -# -# Debug Options -# -CONFIG_DEBUG_ALERT=y -# CONFIG_DEBUG_FEATURES is not set -CONFIG_ARCH_HAVE_STACKCHECK=y -# CONFIG_STACK_COLORATION is not set -CONFIG_ARCH_HAVE_HEAPCHECK=y -# CONFIG_HEAP_COLORATION is not set -# CONFIG_DEBUG_SYMBOLS is not set -CONFIG_ARCH_HAVE_CUSTOMOPT=y -# CONFIG_DEBUG_NOOPT is not set -# CONFIG_DEBUG_CUSTOMOPT is not set -CONFIG_DEBUG_FULLOPT=y - -# -# System Type -# -CONFIG_ARCH_ARM=y -# CONFIG_ARCH_AVR is not set -# CONFIG_ARCH_HC is not set -# CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set -# CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_RISCV is not set -# CONFIG_ARCH_SIM is not set -# CONFIG_ARCH_X86 is not set -# CONFIG_ARCH_Z16 is not set -# CONFIG_ARCH_Z80 is not set -CONFIG_ARCH="arm" - -# -# ARM Options -# -# CONFIG_ARCH_CHIP_A1X is not set -# CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set -# CONFIG_ARCH_CHIP_DM320 is not set -# CONFIG_ARCH_CHIP_EFM32 is not set -# CONFIG_ARCH_CHIP_IMX1 is not set -# CONFIG_ARCH_CHIP_IMX6 is not set -# CONFIG_ARCH_CHIP_KINETIS is not set -# CONFIG_ARCH_CHIP_KL is not set -# CONFIG_ARCH_CHIP_LM is not set -# CONFIG_ARCH_CHIP_TIVA is not set -# CONFIG_ARCH_CHIP_LPC11XX is not set -# CONFIG_ARCH_CHIP_LPC17XX is not set -# CONFIG_ARCH_CHIP_LPC214X is not set -# CONFIG_ARCH_CHIP_LPC2378 is not set -# CONFIG_ARCH_CHIP_LPC31XX is not set -# CONFIG_ARCH_CHIP_LPC43XX is not set -# CONFIG_ARCH_CHIP_NUC1XX is not set -# CONFIG_ARCH_CHIP_SAMA5 is not set -# CONFIG_ARCH_CHIP_SAMD is not set -# CONFIG_ARCH_CHIP_SAML is not set -# CONFIG_ARCH_CHIP_SAM34 is not set -# CONFIG_ARCH_CHIP_SAMV7 is not set -CONFIG_ARCH_CHIP_STM32=y -# CONFIG_ARCH_CHIP_STM32F7 is not set -# CONFIG_ARCH_CHIP_STM32L4 is not set -# CONFIG_ARCH_CHIP_STR71X is not set -# CONFIG_ARCH_CHIP_TMS570 is not set -# CONFIG_ARCH_CHIP_MOXART is not set -# CONFIG_ARCH_ARM7TDMI is not set -# CONFIG_ARCH_ARM926EJS is not set -# CONFIG_ARCH_ARM920T is not set -# CONFIG_ARCH_CORTEXM0 is not set -CONFIG_ARCH_CORTEXM3=y -# CONFIG_ARCH_CORTEXM4 is not set -# CONFIG_ARCH_CORTEXM7 is not set -# CONFIG_ARCH_CORTEXA5 is not set -# CONFIG_ARCH_CORTEXA8 is not set -# CONFIG_ARCH_CORTEXA9 is not set -# CONFIG_ARCH_CORTEXR4 is not set -# CONFIG_ARCH_CORTEXR4F is not set -# CONFIG_ARCH_CORTEXR5 is not set -# CONFIG_ARCH_CORTEX5F is not set -# CONFIG_ARCH_CORTEXR7 is not set -# CONFIG_ARCH_CORTEXR7F is not set -CONFIG_ARCH_FAMILY="armv7-m" -CONFIG_ARCH_CHIP="stm32" -# CONFIG_ARM_TOOLCHAIN_IAR is not set -CONFIG_ARM_TOOLCHAIN_GNU=y -# CONFIG_ARMV7M_USEBASEPRI is not set -CONFIG_ARCH_HAVE_CMNVECTOR=y -# CONFIG_ARMV7M_CMNVECTOR is not set -# CONFIG_ARMV7M_LAZYFPU is not set -# CONFIG_ARCH_HAVE_FPU is not set -# CONFIG_ARCH_HAVE_DPFPU is not set -# CONFIG_ARCH_HAVE_TRUSTZONE is not set -CONFIG_ARM_HAVE_MPU_UNIFIED=y -# CONFIG_ARM_MPU is not set - -# -# ARMV7M Configuration Options -# -# CONFIG_ARMV7M_HAVE_ICACHE is not set -# CONFIG_ARMV7M_HAVE_DCACHE is not set -# CONFIG_ARMV7M_HAVE_ITCM is not set -# CONFIG_ARMV7M_HAVE_DTCM is not set -# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set -# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set -# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set -# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set -CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y -CONFIG_ARMV7M_HAVE_STACKCHECK=y -# CONFIG_ARMV7M_STACKCHECK is not set -# CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_SERIAL_TERMIOS is not set - -# -# STM32 Configuration Options -# -# CONFIG_ARCH_CHIP_STM32L151C6 is not set -# CONFIG_ARCH_CHIP_STM32L151C8 is not set -# CONFIG_ARCH_CHIP_STM32L151CB is not set -# CONFIG_ARCH_CHIP_STM32L151R6 is not set -# CONFIG_ARCH_CHIP_STM32L151R8 is not set -# CONFIG_ARCH_CHIP_STM32L151RB is not set -# CONFIG_ARCH_CHIP_STM32L151V6 is not set -# CONFIG_ARCH_CHIP_STM32L151V8 is not set -# CONFIG_ARCH_CHIP_STM32L151VB is not set -# CONFIG_ARCH_CHIP_STM32L152C6 is not set -# CONFIG_ARCH_CHIP_STM32L152C8 is not set -# CONFIG_ARCH_CHIP_STM32L152CB is not set -# CONFIG_ARCH_CHIP_STM32L152R6 is not set -# CONFIG_ARCH_CHIP_STM32L152R8 is not set -# CONFIG_ARCH_CHIP_STM32L152RB is not set -# CONFIG_ARCH_CHIP_STM32L152V6 is not set -# CONFIG_ARCH_CHIP_STM32L152V8 is not set -# CONFIG_ARCH_CHIP_STM32L152VB is not set -# CONFIG_ARCH_CHIP_STM32L162ZD is not set -# CONFIG_ARCH_CHIP_STM32L162VE is not set -# CONFIG_ARCH_CHIP_STM32F100C8 is not set -# CONFIG_ARCH_CHIP_STM32F100CB is not set -# CONFIG_ARCH_CHIP_STM32F100R8 is not set -# CONFIG_ARCH_CHIP_STM32F100RB is not set -# CONFIG_ARCH_CHIP_STM32F100RC is not set -# CONFIG_ARCH_CHIP_STM32F100RD is not set -# CONFIG_ARCH_CHIP_STM32F100RE is not set -# CONFIG_ARCH_CHIP_STM32F100V8 is not set -# CONFIG_ARCH_CHIP_STM32F100VB is not set -# CONFIG_ARCH_CHIP_STM32F100VC is not set -# CONFIG_ARCH_CHIP_STM32F100VD is not set -# CONFIG_ARCH_CHIP_STM32F100VE is not set -# CONFIG_ARCH_CHIP_STM32F102CB is not set -# CONFIG_ARCH_CHIP_STM32F103T8 is not set -# CONFIG_ARCH_CHIP_STM32F103TB is not set -# CONFIG_ARCH_CHIP_STM32F103C4 is not set -# CONFIG_ARCH_CHIP_STM32F103C8 is not set -# CONFIG_ARCH_CHIP_STM32F103CB is not set -# CONFIG_ARCH_CHIP_STM32F103R8 is not set -# CONFIG_ARCH_CHIP_STM32F103RB is not set -# CONFIG_ARCH_CHIP_STM32F103RC is not set -# CONFIG_ARCH_CHIP_STM32F103RD is not set -# CONFIG_ARCH_CHIP_STM32F103RE is not set -# CONFIG_ARCH_CHIP_STM32F103RG is not set -# CONFIG_ARCH_CHIP_STM32F103V8 is not set -# CONFIG_ARCH_CHIP_STM32F103VB is not set -CONFIG_ARCH_CHIP_STM32F103VC=y -# CONFIG_ARCH_CHIP_STM32F103VE is not set -# CONFIG_ARCH_CHIP_STM32F103ZE is not set -# CONFIG_ARCH_CHIP_STM32F105VB is not set -# CONFIG_ARCH_CHIP_STM32F105RB is not set -# CONFIG_ARCH_CHIP_STM32F107VC is not set -# CONFIG_ARCH_CHIP_STM32F205RG is not set -# CONFIG_ARCH_CHIP_STM32F207IG is not set -# CONFIG_ARCH_CHIP_STM32F207ZE is not set -# CONFIG_ARCH_CHIP_STM32F302K6 is not set -# CONFIG_ARCH_CHIP_STM32F302K8 is not set -# CONFIG_ARCH_CHIP_STM32F302CB is not set -# CONFIG_ARCH_CHIP_STM32F302CC is not set -# CONFIG_ARCH_CHIP_STM32F302RB is not set -# CONFIG_ARCH_CHIP_STM32F302RC is not set -# CONFIG_ARCH_CHIP_STM32F302VB is not set -# CONFIG_ARCH_CHIP_STM32F302VC is not set -# CONFIG_ARCH_CHIP_STM32F303K6 is not set -# CONFIG_ARCH_CHIP_STM32F303K8 is not set -# CONFIG_ARCH_CHIP_STM32F303C6 is not set -# CONFIG_ARCH_CHIP_STM32F303C8 is not set -# CONFIG_ARCH_CHIP_STM32F303CB is not set -# CONFIG_ARCH_CHIP_STM32F303CC is not set -# CONFIG_ARCH_CHIP_STM32F303RB is not set -# CONFIG_ARCH_CHIP_STM32F303RC is not set -# CONFIG_ARCH_CHIP_STM32F303RD is not set -# CONFIG_ARCH_CHIP_STM32F303RE is not set -# CONFIG_ARCH_CHIP_STM32F303VB is not set -# CONFIG_ARCH_CHIP_STM32F303VC is not set -# CONFIG_ARCH_CHIP_STM32F372C8 is not set -# CONFIG_ARCH_CHIP_STM32F372R8 is not set -# CONFIG_ARCH_CHIP_STM32F372V8 is not set -# CONFIG_ARCH_CHIP_STM32F372CB is not set -# CONFIG_ARCH_CHIP_STM32F372RB is not set -# CONFIG_ARCH_CHIP_STM32F372VB is not set -# CONFIG_ARCH_CHIP_STM32F372CC is not set -# CONFIG_ARCH_CHIP_STM32F372RC is not set -# CONFIG_ARCH_CHIP_STM32F372VC is not set -# CONFIG_ARCH_CHIP_STM32F373C8 is not set -# CONFIG_ARCH_CHIP_STM32F373R8 is not set -# CONFIG_ARCH_CHIP_STM32F373V8 is not set -# CONFIG_ARCH_CHIP_STM32F373CB is not set -# CONFIG_ARCH_CHIP_STM32F373RB is not set -# CONFIG_ARCH_CHIP_STM32F373VB is not set -# CONFIG_ARCH_CHIP_STM32F373CC is not set -# CONFIG_ARCH_CHIP_STM32F373RC is not set -# CONFIG_ARCH_CHIP_STM32F373VC is not set -# CONFIG_ARCH_CHIP_STM32F401RE is not set -# CONFIG_ARCH_CHIP_STM32F411RE is not set -# CONFIG_ARCH_CHIP_STM32F411VE is not set -# CONFIG_ARCH_CHIP_STM32F405RG is not set -# CONFIG_ARCH_CHIP_STM32F405VG is not set -# CONFIG_ARCH_CHIP_STM32F405ZG is not set -# CONFIG_ARCH_CHIP_STM32F407VE is not set -# CONFIG_ARCH_CHIP_STM32F407VG is not set -# CONFIG_ARCH_CHIP_STM32F407ZE is not set -# CONFIG_ARCH_CHIP_STM32F407ZG is not set -# CONFIG_ARCH_CHIP_STM32F407IE is not set -# CONFIG_ARCH_CHIP_STM32F407IG is not set -# CONFIG_ARCH_CHIP_STM32F427V is not set -# CONFIG_ARCH_CHIP_STM32F427Z is not set -# CONFIG_ARCH_CHIP_STM32F427I is not set -# CONFIG_ARCH_CHIP_STM32F429V is not set -# CONFIG_ARCH_CHIP_STM32F429Z is not set -# CONFIG_ARCH_CHIP_STM32F429I is not set -# CONFIG_ARCH_CHIP_STM32F429B is not set -# CONFIG_ARCH_CHIP_STM32F429N is not set -# CONFIG_ARCH_CHIP_STM32F446M is not set -# CONFIG_ARCH_CHIP_STM32F446R is not set -# CONFIG_ARCH_CHIP_STM32F446V is not set -# CONFIG_ARCH_CHIP_STM32F446Z is not set -# CONFIG_ARCH_CHIP_STM32F469A is not set -# CONFIG_ARCH_CHIP_STM32F469I is not set -# CONFIG_ARCH_CHIP_STM32F469B is not set -# CONFIG_ARCH_CHIP_STM32F469N is not set -CONFIG_STM32_FLASH_CONFIG_DEFAULT=y -# CONFIG_STM32_FLASH_CONFIG_4 is not set -# CONFIG_STM32_FLASH_CONFIG_6 is not set -# CONFIG_STM32_FLASH_CONFIG_8 is not set -# CONFIG_STM32_FLASH_CONFIG_B is not set -# CONFIG_STM32_FLASH_CONFIG_C is not set -# CONFIG_STM32_FLASH_CONFIG_D is not set -# CONFIG_STM32_FLASH_CONFIG_E is not set -# CONFIG_STM32_FLASH_CONFIG_F is not set -# CONFIG_STM32_FLASH_CONFIG_G is not set -# CONFIG_STM32_FLASH_CONFIG_I is not set -# CONFIG_STM32_STM32L15XX is not set -# CONFIG_STM32_ENERGYLITE is not set -CONFIG_STM32_STM32F10XX=y -# CONFIG_STM32_VALUELINE is not set -# CONFIG_STM32_CONNECTIVITYLINE is not set -CONFIG_STM32_PERFORMANCELINE=y -# CONFIG_STM32_USBACCESSLINE is not set -CONFIG_STM32_HIGHDENSITY=y -# CONFIG_STM32_MEDIUMDENSITY is not set -# CONFIG_STM32_LOWDENSITY is not set -# CONFIG_STM32_STM32F20XX is not set -# CONFIG_STM32_STM32F205 is not set -# CONFIG_STM32_STM32F207 is not set -# CONFIG_STM32_STM32F30XX is not set -# CONFIG_STM32_STM32F302 is not set -# CONFIG_STM32_STM32F303 is not set -# CONFIG_STM32_STM32F37XX is not set -# CONFIG_STM32_STM32F40XX is not set -# CONFIG_STM32_STM32F401 is not set -# CONFIG_STM32_STM32F411 is not set -# CONFIG_STM32_STM32F405 is not set -# CONFIG_STM32_STM32F407 is not set -# CONFIG_STM32_STM32F427 is not set -# CONFIG_STM32_STM32F429 is not set -# CONFIG_STM32_STM32F446 is not set -# CONFIG_STM32_STM32F469 is not set -# CONFIG_STM32_DFU is not set - -# -# STM32 Peripheral Support -# -# CONFIG_STM32_HAVE_CCM is not set -CONFIG_STM32_HAVE_USBDEV=y -# CONFIG_STM32_HAVE_OTGFS is not set -CONFIG_STM32_HAVE_FSMC=y -# CONFIG_STM32_HAVE_LTDC is not set -CONFIG_STM32_HAVE_USART3=y -CONFIG_STM32_HAVE_UART4=y -CONFIG_STM32_HAVE_UART5=y -# CONFIG_STM32_HAVE_USART6 is not set -# CONFIG_STM32_HAVE_UART7 is not set -# CONFIG_STM32_HAVE_UART8 is not set -CONFIG_STM32_HAVE_TIM1=y -# CONFIG_STM32_HAVE_TIM2 is not set -CONFIG_STM32_HAVE_TIM3=y -CONFIG_STM32_HAVE_TIM4=y -CONFIG_STM32_HAVE_TIM5=y -CONFIG_STM32_HAVE_TIM6=y -CONFIG_STM32_HAVE_TIM7=y -CONFIG_STM32_HAVE_TIM8=y -# CONFIG_STM32_HAVE_TIM9 is not set -# CONFIG_STM32_HAVE_TIM10 is not set -# CONFIG_STM32_HAVE_TIM11 is not set -# CONFIG_STM32_HAVE_TIM12 is not set -# CONFIG_STM32_HAVE_TIM13 is not set -# CONFIG_STM32_HAVE_TIM14 is not set -# CONFIG_STM32_HAVE_TIM15 is not set -# CONFIG_STM32_HAVE_TIM16 is not set -# CONFIG_STM32_HAVE_TIM17 is not set -CONFIG_STM32_HAVE_ADC2=y -CONFIG_STM32_HAVE_ADC3=y -# CONFIG_STM32_HAVE_ADC4 is not set -# CONFIG_STM32_HAVE_ADC1_DMA is not set -# CONFIG_STM32_HAVE_ADC2_DMA is not set -# CONFIG_STM32_HAVE_ADC3_DMA is not set -# CONFIG_STM32_HAVE_ADC4_DMA is not set -CONFIG_STM32_HAVE_CAN1=y -# CONFIG_STM32_HAVE_CAN2 is not set -CONFIG_STM32_HAVE_DAC1=y -CONFIG_STM32_HAVE_DAC2=y -# CONFIG_STM32_HAVE_RNG is not set -# CONFIG_STM32_HAVE_ETHMAC is not set -CONFIG_STM32_HAVE_I2C2=y -# CONFIG_STM32_HAVE_I2C3 is not set -CONFIG_STM32_HAVE_SPI2=y -CONFIG_STM32_HAVE_SPI3=y -# CONFIG_STM32_HAVE_SPI4 is not set -# CONFIG_STM32_HAVE_SPI5 is not set -# CONFIG_STM32_HAVE_SPI6 is not set -# CONFIG_STM32_HAVE_SAIPLL is not set -# CONFIG_STM32_HAVE_I2SPLL is not set -# CONFIG_STM32_ADC1 is not set -# CONFIG_STM32_ADC2 is not set -# CONFIG_STM32_ADC3 is not set -# CONFIG_STM32_BKP is not set -# CONFIG_STM32_CAN1 is not set -# CONFIG_STM32_CRC is not set -# CONFIG_STM32_DMA1 is not set -# CONFIG_STM32_DMA2 is not set -# CONFIG_STM32_DAC1 is not set -# CONFIG_STM32_DAC2 is not set -# CONFIG_STM32_FSMC is not set -# CONFIG_STM32_I2C1 is not set -# CONFIG_STM32_I2C2 is not set -CONFIG_STM32_PWR=y -# CONFIG_STM32_SDIO is not set -# CONFIG_STM32_SPI1 is not set -# CONFIG_STM32_SPI2 is not set -# CONFIG_STM32_SPI3 is not set -# CONFIG_STM32_TIM1 is not set -# CONFIG_STM32_TIM2 is not set -# CONFIG_STM32_TIM3 is not set -# CONFIG_STM32_TIM4 is not set -# CONFIG_STM32_TIM5 is not set -# CONFIG_STM32_TIM6 is not set -# CONFIG_STM32_TIM7 is not set -# CONFIG_STM32_TIM8 is not set -CONFIG_STM32_USART1=y -# CONFIG_STM32_USART2 is not set -# CONFIG_STM32_USART3 is not set -# CONFIG_STM32_UART4 is not set -# CONFIG_STM32_UART5 is not set -# CONFIG_STM32_USB is not set -# CONFIG_STM32_IWDG is not set -# CONFIG_STM32_WWDG is not set -# CONFIG_STM32_NOEXT_VECTORS is not set - -# -# Alternate Pin Mapping -# -# CONFIG_STM32_USART1_REMAP is not set -CONFIG_STM32_JTAG_DISABLE=y -# CONFIG_STM32_JTAG_FULL_ENABLE is not set -# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set -# CONFIG_STM32_JTAG_SW_ENABLE is not set -# CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG is not set -# CONFIG_STM32_FORCEPOWER is not set -# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set - -# -# Timer Configuration -# -# CONFIG_STM32_ONESHOT is not set -# CONFIG_STM32_FREERUN is not set -# CONFIG_STM32_TIM1_CAP is not set -# CONFIG_STM32_TIM3_CAP is not set -# CONFIG_STM32_TIM4_CAP is not set -# CONFIG_STM32_TIM5_CAP is not set -# CONFIG_STM32_TIM8_CAP is not set -CONFIG_STM32_USART=y -CONFIG_STM32_SERIALDRIVER=y - -# -# U[S]ART Configuration -# - -# -# U[S]ART Device Configuration -# -CONFIG_STM32_USART1_SERIALDRIVER=y -# CONFIG_STM32_USART1_1WIREDRIVER is not set -# CONFIG_USART1_RS485 is not set - -# -# Serial Driver Configuration -# -# CONFIG_SERIAL_DISABLE_REORDERING is not set -# CONFIG_STM32_FLOWCONTROL_BROKEN is not set -# CONFIG_STM32_USART_BREAKS is not set -# CONFIG_STM32_USART_SINGLEWIRE is not set -CONFIG_STM32_HAVE_RTC_COUNTER=y -# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set - -# -# USB FS Host Configuration -# - -# -# USB HS Host Configuration -# - -# -# USB Host Debug Configuration -# - -# -# USB Device Configuration -# - -# -# Architecture Options -# -# CONFIG_ARCH_NOINTC is not set -# CONFIG_ARCH_VECNOTIRQ is not set -# CONFIG_ARCH_DMA is not set -CONFIG_ARCH_HAVE_IRQPRIO=y -# CONFIG_ARCH_L2CACHE is not set -# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set -# CONFIG_ARCH_HAVE_ADDRENV is not set -# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set -# CONFIG_ARCH_HAVE_MULTICPU is not set -CONFIG_ARCH_HAVE_VFORK=y -# CONFIG_ARCH_HAVE_MMU is not set -CONFIG_ARCH_HAVE_MPU=y -# CONFIG_ARCH_NAND_HWECC is not set -# CONFIG_ARCH_HAVE_EXTCLK is not set -# CONFIG_ARCH_HAVE_POWEROFF is not set -CONFIG_ARCH_HAVE_RESET=y -# CONFIG_ARCH_USE_MPU is not set -# CONFIG_ARCH_IRQPRIO is not set -CONFIG_ARCH_STACKDUMP=y -# CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_IDLE_CUSTOM is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set -CONFIG_ARCH_HAVE_RAMVECTORS=y -# CONFIG_ARCH_RAMVECTORS is not set - -# -# Board Settings -# -CONFIG_BOARD_LOOPSPERMSEC=5483 -# CONFIG_ARCH_CALIBRATION is not set - -# -# Interrupt options -# -CONFIG_ARCH_HAVE_INTERRUPTSTACK=y -CONFIG_ARCH_INTERRUPTSTACK=0 -CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y -# CONFIG_ARCH_HIPRI_INTERRUPT is not set - -# -# Boot options -# -# CONFIG_BOOT_RUNFROMEXTSRAM is not set -CONFIG_BOOT_RUNFROMFLASH=y -# CONFIG_BOOT_RUNFROMISRAM is not set -# CONFIG_BOOT_RUNFROMSDRAM is not set -# CONFIG_BOOT_COPYTORAM is not set - -# -# Boot Memory Configuration -# -CONFIG_RAM_START=0x20000000 -CONFIG_RAM_SIZE=49152 -# CONFIG_ARCH_HAVE_SDRAM is not set - -# -# Board Selection -# -CONFIG_ARCH_BOARD_HYMINI_STM32V=y -# CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107 is not set -# CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD="hymini-stm32v" - -# -# Common Board Options -# -CONFIG_ARCH_HAVE_LEDS=y -CONFIG_ARCH_LEDS=y -CONFIG_ARCH_HAVE_BUTTONS=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_HAVE_IRQBUTTONS=y -CONFIG_ARCH_IRQBUTTONS=y - -# -# Board-Specific Options -# -# CONFIG_BOARD_CRASHDUMP is not set -# CONFIG_LIB_BOARDCTL is not set - -# -# RTOS Features -# -CONFIG_DISABLE_OS_API=y -# CONFIG_DISABLE_POSIX_TIMERS is not set -# CONFIG_DISABLE_PTHREAD is not set -# CONFIG_DISABLE_SIGNALS is not set -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_ENVIRON is not set - -# -# Clocks and Timers -# -CONFIG_ARCH_HAVE_TICKLESS=y -# CONFIG_SCHED_TICKLESS is not set -CONFIG_USEC_PER_TICK=10000 -# CONFIG_SYSTEM_TIME64 is not set -# CONFIG_CLOCK_MONOTONIC is not set -CONFIG_ARCH_HAVE_TIMEKEEPING=y -# CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2011 -CONFIG_START_MONTH=7 -CONFIG_START_DAY=5 -CONFIG_MAX_WDOGPARMS=2 -CONFIG_PREALLOC_WDOGS=4 -CONFIG_WDOG_INTRESERVE=0 -CONFIG_PREALLOC_TIMERS=4 - -# -# Tasks and Scheduling -# -# CONFIG_INIT_NONE is not set -CONFIG_INIT_ENTRYPOINT=y -CONFIG_USER_ENTRYPOINT="archbuttons_main" -CONFIG_RR_INTERVAL=200 -# CONFIG_SCHED_SPORADIC is not set -CONFIG_TASK_NAME_SIZE=0 -CONFIG_MAX_TASKS=16 -# CONFIG_SCHED_HAVE_PARENT is not set -CONFIG_SCHED_WAITPID=y - -# -# Pthread Options -# -# CONFIG_MUTEX_TYPES is not set -CONFIG_NPTHREAD_KEYS=4 - -# -# Performance Monitoring -# -# CONFIG_SCHED_CPULOAD is not set -# CONFIG_SCHED_INSTRUMENTATION is not set - -# -# Files and I/O -# -CONFIG_DEV_CONSOLE=y -# CONFIG_FDCLONE_DISABLE is not set -# CONFIG_FDCLONE_STDIO is not set -CONFIG_SDCLONE_DISABLE=y -CONFIG_NFILE_DESCRIPTORS=8 -CONFIG_NFILE_STREAMS=8 -CONFIG_NAME_MAX=32 -# CONFIG_PRIORITY_INHERITANCE is not set - -# -# RTOS hooks -# -# CONFIG_BOARD_INITIALIZE is not set -# CONFIG_SCHED_STARTHOOK is not set -# CONFIG_SCHED_ATEXIT is not set -# CONFIG_SCHED_ONEXIT is not set -# CONFIG_SIG_EVTHREAD is not set - -# -# Signal Numbers -# -CONFIG_SIG_SIGUSR1=1 -CONFIG_SIG_SIGUSR2=2 -CONFIG_SIG_SIGALARM=3 -CONFIG_SIG_SIGCONDTIMEDOUT=16 -CONFIG_SIG_SIGWORK=17 - -# -# POSIX Message Queue Options -# -CONFIG_PREALLOC_MQ_MSGS=4 -CONFIG_MQ_MAXMSGSIZE=32 -# CONFIG_MODULE is not set - -# -# Work queue support -# -CONFIG_SCHED_WORKQUEUE=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKPERIOD=50000 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -# CONFIG_SCHED_LPWORK is not set - -# -# Stack and heap information -# -CONFIG_IDLETHREAD_STACKSIZE=1024 -CONFIG_USERMAIN_STACKSIZE=2048 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=2048 -# CONFIG_LIB_SYSCALL is not set - -# -# Device Drivers -# -CONFIG_DISABLE_POLL=y -CONFIG_DEV_NULL=y -# CONFIG_DEV_ZERO is not set -# CONFIG_DEV_URANDOM is not set -# CONFIG_DEV_LOOP is not set - -# -# Buffering -# -# CONFIG_DRVR_WRITEBUFFER is not set -# CONFIG_DRVR_READAHEAD is not set -# CONFIG_RAMDISK is not set -# CONFIG_CAN is not set -# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set -# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set -# CONFIG_PWM is not set -CONFIG_ARCH_HAVE_I2CRESET=y -# CONFIG_I2C is not set -# CONFIG_SPI is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y -# CONFIG_I2S is not set - -# -# Timer Driver Support -# -# CONFIG_TIMER is not set -# CONFIG_ONESHOT is not set -# CONFIG_RTC is not set -# CONFIG_WATCHDOG is not set -# CONFIG_ANALOG is not set -# CONFIG_AUDIO_DEVICES is not set -# CONFIG_VIDEO_DEVICES is not set -# CONFIG_BCH is not set -# CONFIG_INPUT is not set - -# -# IO Expander/GPIO Support -# -# CONFIG_IOEXPANDER is not set -# CONFIG_DEV_GPIO is not set - -# -# LCD Driver Support -# -# CONFIG_LCD is not set -# CONFIG_SLCD is not set - -# -# LED Support -# -# CONFIG_USERLED is not set -# CONFIG_RGBLED is not set -# CONFIG_PCA9635PW is not set -# CONFIG_NCP5623C is not set -# CONFIG_MMCSD is not set -# CONFIG_MODEM is not set -# CONFIG_MTD is not set -# CONFIG_EEPROM is not set -# CONFIG_PIPES is not set -# CONFIG_PM is not set -# CONFIG_POWER is not set -# CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set -CONFIG_SERIAL=y -# CONFIG_DEV_LOWCONSOLE is not set -# CONFIG_SERIAL_REMOVABLE is not set -CONFIG_SERIAL_CONSOLE=y -# CONFIG_16550_UART is not set -# CONFIG_UART_SERIALDRIVER is not set -# CONFIG_UART0_SERIALDRIVER is not set -# CONFIG_UART1_SERIALDRIVER is not set -# CONFIG_UART2_SERIALDRIVER is not set -# CONFIG_UART3_SERIALDRIVER is not set -# CONFIG_UART4_SERIALDRIVER is not set -# CONFIG_UART5_SERIALDRIVER is not set -# CONFIG_UART6_SERIALDRIVER is not set -# CONFIG_UART7_SERIALDRIVER is not set -# CONFIG_UART8_SERIALDRIVER is not set -# CONFIG_SCI0_SERIALDRIVER is not set -# CONFIG_SCI1_SERIALDRIVER is not set -# CONFIG_USART0_SERIALDRIVER is not set -CONFIG_USART1_SERIALDRIVER=y -# CONFIG_USART2_SERIALDRIVER is not set -# CONFIG_USART3_SERIALDRIVER is not set -# CONFIG_USART4_SERIALDRIVER is not set -# CONFIG_USART5_SERIALDRIVER is not set -# CONFIG_USART6_SERIALDRIVER is not set -# CONFIG_USART7_SERIALDRIVER is not set -# CONFIG_USART8_SERIALDRIVER is not set -# CONFIG_OTHER_UART_SERIALDRIVER is not set -CONFIG_MCU_SERIAL=y -CONFIG_STANDARD_SERIAL=y -# CONFIG_SERIAL_IFLOWCONTROL is not set -# CONFIG_SERIAL_OFLOWCONTROL is not set -# CONFIG_SERIAL_DMA is not set -CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y -CONFIG_USART1_SERIAL_CONSOLE=y -# CONFIG_OTHER_SERIAL_CONSOLE is not set -# CONFIG_NO_SERIAL_CONSOLE is not set - -# -# USART1 Configuration -# -CONFIG_USART1_RXBUFSIZE=256 -CONFIG_USART1_TXBUFSIZE=256 -CONFIG_USART1_BAUD=115200 -CONFIG_USART1_BITS=8 -CONFIG_USART1_PARITY=0 -CONFIG_USART1_2STOP=0 -# CONFIG_USART1_IFLOWCONTROL is not set -# CONFIG_USART1_OFLOWCONTROL is not set -# CONFIG_USART1_DMA is not set -# CONFIG_PSEUDOTERM is not set -# CONFIG_USBDEV is not set -# CONFIG_USBHOST is not set -# CONFIG_HAVE_USBTRACE is not set -# CONFIG_DRIVERS_WIRELESS is not set -# CONFIG_DRIVERS_CONTACTLESS is not set - -# -# System Logging -# -# CONFIG_ARCH_SYSLOG is not set -# CONFIG_RAMLOG is not set -# CONFIG_SYSLOG_INTBUFFER is not set -# CONFIG_SYSLOG_TIMESTAMP is not set -CONFIG_SYSLOG_SERIAL_CONSOLE=y -# CONFIG_SYSLOG_CHAR is not set -CONFIG_SYSLOG_CONSOLE=y -# CONFIG_SYSLOG_NONE is not set -# CONFIG_SYSLOG_FILE is not set -# CONFIG_SYSLOG_CHARDEV is not set - -# -# Networking Support -# -# CONFIG_ARCH_HAVE_NET is not set -# CONFIG_ARCH_HAVE_PHY is not set -# CONFIG_NET is not set - -# -# Crypto API -# -# CONFIG_CRYPTO is not set - -# -# File Systems -# - -# -# File system configuration -# -# CONFIG_DISABLE_MOUNTPOINT is not set -# CONFIG_FS_AUTOMOUNTER is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_FS_READABLE is not set -# CONFIG_FS_WRITABLE is not set -# CONFIG_FS_NAMED_SEMAPHORES is not set -CONFIG_FS_MQUEUE_MPATH="/var/mqueue" -# CONFIG_FS_RAMMAP is not set -# CONFIG_FS_FAT is not set -# CONFIG_FS_NXFFS is not set -# CONFIG_FS_ROMFS is not set -# CONFIG_FS_TMPFS is not set -# CONFIG_FS_SMARTFS is not set -# CONFIG_FS_PROCFS is not set -# CONFIG_FS_UNIONFS is not set - -# -# Graphics Support -# -# CONFIG_NX is not set - -# -# Memory Management -# -# CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=1 -# CONFIG_ARCH_HAVE_HEAP2 is not set -# CONFIG_GRAN is not set - -# -# Audio Support -# -# CONFIG_AUDIO is not set - -# -# Wireless Support -# - -# -# Binary Loader -# -CONFIG_BINFMT_DISABLE=y -# CONFIG_PIC is not set -CONFIG_SYMTAB_ORDEREDBYNAME=y - -# -# Library Routines -# - -# -# Standard C Library Options -# -CONFIG_STDIO_BUFFER_SIZE=64 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=2 -CONFIG_LIB_HOMEDIR="/" -# CONFIG_LIBM is not set -# CONFIG_NOPRINTF_FIELDWIDTH is not set -# CONFIG_LIBC_FLOATINGPOINT is not set -CONFIG_LIBC_LONG_LONG=y -# CONFIG_LIBC_IOCTL_VARIADIC is not set -# CONFIG_LIBC_WCHAR is not set -# CONFIG_LIBC_LOCALE is not set -CONFIG_LIB_RAND_ORDER=1 -# CONFIG_EOL_IS_CR is not set -# CONFIG_EOL_IS_LF is not set -# CONFIG_EOL_IS_BOTH_CRLF is not set -CONFIG_EOL_IS_EITHER_CRLF=y -CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 -# CONFIG_LIBC_STRERROR is not set -# CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_ARCH_LOWPUTC=y -# CONFIG_LIBC_LOCALTIME is not set -# CONFIG_TIME_EXTENDED is not set -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set -# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set -CONFIG_ARCH_HAVE_TLS=y -# CONFIG_TLS is not set -# CONFIG_LIBC_NETDB is not set - -# -# Non-standard Library Support -# -# CONFIG_LIB_CRC64_FAST is not set -# CONFIG_LIB_KBDCODEC is not set -# CONFIG_LIB_SLCDCODEC is not set -# CONFIG_LIB_HEX2BIN is not set - -# -# Basic CXX Support -# -# CONFIG_C99_BOOL8 is not set -# CONFIG_HAVE_CXX is not set - -# -# Application Configuration -# - -# -# CAN Utilities -# - -# -# Examples -# -CONFIG_EXAMPLES_ARCHBUTTONS=y -CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 -CONFIG_EXAMPLES_ARCHBUTTONS_MAX=1 -CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 -CONFIG_EXAMPLES_IRQBUTTONS_MAX=1 -CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="Key A" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Key B" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" -# CONFIG_EXAMPLES_BUTTONS is not set -# CONFIG_EXAMPLES_CHAT is not set -# CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_DHCPD is not set -# CONFIG_EXAMPLES_ELF is not set -# CONFIG_EXAMPLES_FTPC is not set -# CONFIG_EXAMPLES_FTPD is not set -# CONFIG_EXAMPLES_HELLO is not set -# CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_IGMP is not set -# CONFIG_EXAMPLES_JSON is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set -# CONFIG_EXAMPLES_MEDIA is not set -# CONFIG_EXAMPLES_MM is not set -# CONFIG_EXAMPLES_MODBUS is not set -# CONFIG_EXAMPLES_MOUNT is not set -# CONFIG_EXAMPLES_NRF24L01TERM is not set -# CONFIG_EXAMPLES_NSH is not set -# CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXFFS is not set -# CONFIG_EXAMPLES_NXHELLO is not set -# CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NXLINES is not set -# CONFIG_EXAMPLES_NXTERM is not set -# CONFIG_EXAMPLES_NXTEXT is not set -# CONFIG_EXAMPLES_OSTEST is not set -# CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_PPPD is not set -# CONFIG_EXAMPLES_RFID_READUID is not set -# CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set -# CONFIG_EXAMPLES_SENDMAIL is not set -# CONFIG_EXAMPLES_SERIALBLASTER is not set -# CONFIG_EXAMPLES_SERIALRX is not set -# CONFIG_EXAMPLES_SERLOOP is not set -# CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART is not set -# CONFIG_EXAMPLES_SMP is not set -# CONFIG_EXAMPLES_TCPECHO is not set -# CONFIG_EXAMPLES_TELNETD is not set -# CONFIG_EXAMPLES_TIFF is not set -# CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_USBTERM is not set -# CONFIG_EXAMPLES_WATCHDOG is not set -# CONFIG_EXAMPLES_WEBSERVER is not set - -# -# File System Utilities -# -# CONFIG_FSUTILS_INIFILE is not set - -# -# GPS Utilities -# -# CONFIG_GPSUTILS_MINMEA_LIB is not set - -# -# Graphics Support -# -# CONFIG_TIFF is not set -# CONFIG_GRAPHICS_TRAVELER is not set - -# -# Interpreters -# -# CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_MICROPYTHON is not set -# CONFIG_INTERPRETERS_MINIBASIC is not set -# CONFIG_INTERPRETERS_PCODE is not set - -# -# FreeModBus -# -# CONFIG_MODBUS is not set - -# -# Network Utilities -# -# CONFIG_NETUTILS_CODECS is not set -# CONFIG_NETUTILS_ESP8266 is not set -# CONFIG_NETUTILS_FTPC is not set -# CONFIG_NETUTILS_JSON is not set -# CONFIG_NETUTILS_SMTP is not set - -# -# NSH Library -# -# CONFIG_NSH_LIBRARY is not set - -# -# NxWidgets/NxWM -# - -# -# Platform-specific Support -# -# CONFIG_PLATFORM_CONFIGDATA is not set - -# -# System Libraries and NSH Add-Ons -# -# CONFIG_SYSTEM_CLE is not set -# CONFIG_SYSTEM_CUTERM is not set -# CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set -# CONFIG_SYSTEM_HEXED is not set -# CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_RAMTEST is not set -# CONFIG_READLINE_HAVE_EXTMATCH is not set -CONFIG_SYSTEM_READLINE=y -CONFIG_READLINE_ECHO=y -# CONFIG_READLINE_CMD_HISTORY is not set -# CONFIG_SYSTEM_SUDOKU is not set -# CONFIG_SYSTEM_TEE is not set -# CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_VI is not set -# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/hymini-stm32v/buttons/setenv.sh b/configs/hymini-stm32v/buttons/setenv.sh deleted file mode 100755 index df0dba3180..0000000000 --- a/configs/hymini-stm32v/buttons/setenv.sh +++ /dev/null @@ -1,47 +0,0 @@ -#!/bin/bash -# configs/hymini-stm32v/buttons/setenv.sh -# -# Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if [ "$(basename $0)" = "setenv.sh" ] ; then - echo "You must source this script, not run it!" 1>&2 - exit 1 -fi - -if [ -z "${PATH_ORIG}" ]; then export PATH_ORIG="${PATH}"; fi - -WD=`pwd` -export RIDE_BIN="/cygdrive/c/Program Files/Raisonance/Ride/arm-gcc/bin" -export BUILDROOT_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" -export PATH="${BUILDROOT_BIN}:${RIDE_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" - -echo "PATH : ${PATH}" diff --git a/configs/stm3210e-eval/README.txt b/configs/stm3210e-eval/README.txt index 1e70b125b5..050276b5bb 100644 --- a/configs/stm3210e-eval/README.txt +++ b/configs/stm3210e-eval/README.txt @@ -705,14 +705,6 @@ can be selected as follow: Where is one of the following: - buttons: - -------- - - Uses apps/examples/buttons to exercise STM3210E-EVAL buttons and - button interrupts. - - CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery under Windows - composite --------- diff --git a/configs/stm3210e-eval/buttons/Make.defs b/configs/stm3210e-eval/buttons/Make.defs deleted file mode 100644 index a0f6380297..0000000000 --- a/configs/stm3210e-eval/buttons/Make.defs +++ /dev/null @@ -1,117 +0,0 @@ -############################################################################ -# configs/stm3210e-eval/buttons/Make.defs -# -# Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk -include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ifeq ($(WINTOOL),y) - # Windows-native toolchains - DIRLINK = $(TOPDIR)/tools/copydir.sh - DIRUNLINK = $(TOPDIR)/tools/unlink.sh - MKDEP = $(TOPDIR)/tools/mkwindeps.sh - ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" - ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" - ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" -else - # Linux/Cygwin-native toolchain - MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) - ARCHINCLUDES = -I. -isystem $(TOPDIR)/include - ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx - ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) -endif - -CC = $(CROSSDEV)gcc -CXX = $(CROSSDEV)g++ -CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld -AR = $(CROSSDEV)ar rcs -NM = $(CROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} -ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION = -g -endif - -ifneq ($(CONFIG_DEBUG_NOOPT),y) - ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer -endif - -ARCHCFLAGS = -fno-builtin -ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -ARCHWARNINGSXX = -Wall -Wshadow -Wundef -ARCHDEFINES = -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -AFLAGS = $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -ASMEXT = .S -OBJEXT = .o -LIBEXT = .a -EXEEXT = - -ifneq ($(CROSSDEV),arm-nuttx-elf-) - LDFLAGS += -nostartfiles -nodefaultlibs -endif -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - LDFLAGS += -g -endif - - -HOSTCC = gcc -HOSTINCLUDES = -I. -HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe -HOSTLDFLAGS = - diff --git a/configs/stm3210e-eval/buttons/defconfig b/configs/stm3210e-eval/buttons/defconfig deleted file mode 100644 index 202b99f6c8..0000000000 --- a/configs/stm3210e-eval/buttons/defconfig +++ /dev/null @@ -1,1056 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Nuttx/ Configuration -# - -# -# Build Setup -# -# CONFIG_EXPERIMENTAL is not set -# CONFIG_DEFAULT_SMALL is not set -# CONFIG_HOST_LINUX is not set -# CONFIG_HOST_OSX is not set -CONFIG_HOST_WINDOWS=y -# CONFIG_HOST_OTHER is not set -# CONFIG_WINDOWS_NATIVE is not set -CONFIG_WINDOWS_CYGWIN=y -# CONFIG_WINDOWS_MSYS is not set -# CONFIG_WINDOWS_OTHER is not set - -# -# Build Configuration -# -# CONFIG_APPS_DIR="../apps" -CONFIG_BUILD_FLAT=y -# CONFIG_BUILD_2PASS is not set - -# -# Binary Output Formats -# -# CONFIG_RRLOAD_BINARY is not set -CONFIG_INTELHEX_BINARY=y -# CONFIG_MOTOROLA_SREC is not set -# CONFIG_RAW_BINARY is not set -# CONFIG_UBOOT_UIMAGE is not set - -# -# Customize Header Files -# -# CONFIG_ARCH_STDINT_H is not set -# CONFIG_ARCH_STDBOOL_H is not set -# CONFIG_ARCH_MATH_H is not set -# CONFIG_ARCH_FLOAT_H is not set -# CONFIG_ARCH_STDARG_H is not set -# CONFIG_ARCH_DEBUG_H is not set - -# -# Debug Options -# -CONFIG_DEBUG_ALERT=y -# CONFIG_DEBUG_FEATURES is not set -CONFIG_ARCH_HAVE_STACKCHECK=y -# CONFIG_STACK_COLORATION is not set -CONFIG_ARCH_HAVE_HEAPCHECK=y -# CONFIG_HEAP_COLORATION is not set -# CONFIG_DEBUG_SYMBOLS is not set -CONFIG_ARCH_HAVE_CUSTOMOPT=y -# CONFIG_DEBUG_NOOPT is not set -# CONFIG_DEBUG_CUSTOMOPT is not set -CONFIG_DEBUG_FULLOPT=y - -# -# System Type -# -CONFIG_ARCH_ARM=y -# CONFIG_ARCH_AVR is not set -# CONFIG_ARCH_HC is not set -# CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set -# CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_RISCV is not set -# CONFIG_ARCH_SIM is not set -# CONFIG_ARCH_X86 is not set -# CONFIG_ARCH_Z16 is not set -# CONFIG_ARCH_Z80 is not set -CONFIG_ARCH="arm" - -# -# ARM Options -# -# CONFIG_ARCH_CHIP_A1X is not set -# CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set -# CONFIG_ARCH_CHIP_DM320 is not set -# CONFIG_ARCH_CHIP_EFM32 is not set -# CONFIG_ARCH_CHIP_IMX1 is not set -# CONFIG_ARCH_CHIP_IMX6 is not set -# CONFIG_ARCH_CHIP_KINETIS is not set -# CONFIG_ARCH_CHIP_KL is not set -# CONFIG_ARCH_CHIP_LM is not set -# CONFIG_ARCH_CHIP_TIVA is not set -# CONFIG_ARCH_CHIP_LPC11XX is not set -# CONFIG_ARCH_CHIP_LPC17XX is not set -# CONFIG_ARCH_CHIP_LPC214X is not set -# CONFIG_ARCH_CHIP_LPC2378 is not set -# CONFIG_ARCH_CHIP_LPC31XX is not set -# CONFIG_ARCH_CHIP_LPC43XX is not set -# CONFIG_ARCH_CHIP_NUC1XX is not set -# CONFIG_ARCH_CHIP_SAMA5 is not set -# CONFIG_ARCH_CHIP_SAMD is not set -# CONFIG_ARCH_CHIP_SAML is not set -# CONFIG_ARCH_CHIP_SAM34 is not set -# CONFIG_ARCH_CHIP_SAMV7 is not set -CONFIG_ARCH_CHIP_STM32=y -# CONFIG_ARCH_CHIP_STM32F7 is not set -# CONFIG_ARCH_CHIP_STM32L4 is not set -# CONFIG_ARCH_CHIP_STR71X is not set -# CONFIG_ARCH_CHIP_TMS570 is not set -# CONFIG_ARCH_CHIP_MOXART is not set -# CONFIG_ARCH_ARM7TDMI is not set -# CONFIG_ARCH_ARM926EJS is not set -# CONFIG_ARCH_ARM920T is not set -# CONFIG_ARCH_CORTEXM0 is not set -CONFIG_ARCH_CORTEXM3=y -# CONFIG_ARCH_CORTEXM4 is not set -# CONFIG_ARCH_CORTEXM7 is not set -# CONFIG_ARCH_CORTEXA5 is not set -# CONFIG_ARCH_CORTEXA8 is not set -# CONFIG_ARCH_CORTEXA9 is not set -# CONFIG_ARCH_CORTEXR4 is not set -# CONFIG_ARCH_CORTEXR4F is not set -# CONFIG_ARCH_CORTEXR5 is not set -# CONFIG_ARCH_CORTEX5F is not set -# CONFIG_ARCH_CORTEXR7 is not set -# CONFIG_ARCH_CORTEXR7F is not set -CONFIG_ARCH_FAMILY="armv7-m" -CONFIG_ARCH_CHIP="stm32" -# CONFIG_ARM_TOOLCHAIN_IAR is not set -CONFIG_ARM_TOOLCHAIN_GNU=y -# CONFIG_ARMV7M_USEBASEPRI is not set -CONFIG_ARCH_HAVE_CMNVECTOR=y -# CONFIG_ARMV7M_CMNVECTOR is not set -# CONFIG_ARMV7M_LAZYFPU is not set -# CONFIG_ARCH_HAVE_FPU is not set -# CONFIG_ARCH_HAVE_DPFPU is not set -# CONFIG_ARCH_HAVE_TRUSTZONE is not set -CONFIG_ARM_HAVE_MPU_UNIFIED=y -# CONFIG_ARM_MPU is not set - -# -# ARMV7M Configuration Options -# -# CONFIG_ARMV7M_HAVE_ICACHE is not set -# CONFIG_ARMV7M_HAVE_DCACHE is not set -# CONFIG_ARMV7M_HAVE_ITCM is not set -# CONFIG_ARMV7M_HAVE_DTCM is not set -# CONFIG_ARMV7M_TOOLCHAIN_IARW is not set -# CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC is not set -# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set -# CONFIG_ARMV7M_TOOLCHAIN_CODEREDW is not set -CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y -# CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM is not set -# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set -# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW is not set -# CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE is not set -CONFIG_ARMV7M_HAVE_STACKCHECK=y -# CONFIG_ARMV7M_STACKCHECK is not set -# CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_SERIAL_TERMIOS is not set - -# -# STM32 Configuration Options -# -# CONFIG_ARCH_CHIP_STM32L151C6 is not set -# CONFIG_ARCH_CHIP_STM32L151C8 is not set -# CONFIG_ARCH_CHIP_STM32L151CB is not set -# CONFIG_ARCH_CHIP_STM32L151R6 is not set -# CONFIG_ARCH_CHIP_STM32L151R8 is not set -# CONFIG_ARCH_CHIP_STM32L151RB is not set -# CONFIG_ARCH_CHIP_STM32L151V6 is not set -# CONFIG_ARCH_CHIP_STM32L151V8 is not set -# CONFIG_ARCH_CHIP_STM32L151VB is not set -# CONFIG_ARCH_CHIP_STM32L152C6 is not set -# CONFIG_ARCH_CHIP_STM32L152C8 is not set -# CONFIG_ARCH_CHIP_STM32L152CB is not set -# CONFIG_ARCH_CHIP_STM32L152R6 is not set -# CONFIG_ARCH_CHIP_STM32L152R8 is not set -# CONFIG_ARCH_CHIP_STM32L152RB is not set -# CONFIG_ARCH_CHIP_STM32L152V6 is not set -# CONFIG_ARCH_CHIP_STM32L152V8 is not set -# CONFIG_ARCH_CHIP_STM32L152VB is not set -# CONFIG_ARCH_CHIP_STM32L162ZD is not set -# CONFIG_ARCH_CHIP_STM32L162VE is not set -# CONFIG_ARCH_CHIP_STM32F100C8 is not set -# CONFIG_ARCH_CHIP_STM32F100CB is not set -# CONFIG_ARCH_CHIP_STM32F100R8 is not set -# CONFIG_ARCH_CHIP_STM32F100RB is not set -# CONFIG_ARCH_CHIP_STM32F100RC is not set -# CONFIG_ARCH_CHIP_STM32F100RD is not set -# CONFIG_ARCH_CHIP_STM32F100RE is not set -# CONFIG_ARCH_CHIP_STM32F100V8 is not set -# CONFIG_ARCH_CHIP_STM32F100VB is not set -# CONFIG_ARCH_CHIP_STM32F100VC is not set -# CONFIG_ARCH_CHIP_STM32F100VD is not set -# CONFIG_ARCH_CHIP_STM32F100VE is not set -# CONFIG_ARCH_CHIP_STM32F102CB is not set -# CONFIG_ARCH_CHIP_STM32F103T8 is not set -# CONFIG_ARCH_CHIP_STM32F103TB is not set -# CONFIG_ARCH_CHIP_STM32F103C4 is not set -# CONFIG_ARCH_CHIP_STM32F103C8 is not set -# CONFIG_ARCH_CHIP_STM32F103CB is not set -# CONFIG_ARCH_CHIP_STM32F103R8 is not set -# CONFIG_ARCH_CHIP_STM32F103RB is not set -# CONFIG_ARCH_CHIP_STM32F103RC is not set -# CONFIG_ARCH_CHIP_STM32F103RD is not set -# CONFIG_ARCH_CHIP_STM32F103RE is not set -# CONFIG_ARCH_CHIP_STM32F103RG is not set -# CONFIG_ARCH_CHIP_STM32F103V8 is not set -# CONFIG_ARCH_CHIP_STM32F103VB is not set -# CONFIG_ARCH_CHIP_STM32F103VC is not set -# CONFIG_ARCH_CHIP_STM32F103VE is not set -CONFIG_ARCH_CHIP_STM32F103ZE=y -# CONFIG_ARCH_CHIP_STM32F105VB is not set -# CONFIG_ARCH_CHIP_STM32F105RB is not set -# CONFIG_ARCH_CHIP_STM32F107VC is not set -# CONFIG_ARCH_CHIP_STM32F205RG is not set -# CONFIG_ARCH_CHIP_STM32F207IG is not set -# CONFIG_ARCH_CHIP_STM32F207ZE is not set -# CONFIG_ARCH_CHIP_STM32F302K6 is not set -# CONFIG_ARCH_CHIP_STM32F302K8 is not set -# CONFIG_ARCH_CHIP_STM32F302CB is not set -# CONFIG_ARCH_CHIP_STM32F302CC is not set -# CONFIG_ARCH_CHIP_STM32F302RB is not set -# CONFIG_ARCH_CHIP_STM32F302RC is not set -# CONFIG_ARCH_CHIP_STM32F302VB is not set -# CONFIG_ARCH_CHIP_STM32F302VC is not set -# CONFIG_ARCH_CHIP_STM32F303K6 is not set -# CONFIG_ARCH_CHIP_STM32F303K8 is not set -# CONFIG_ARCH_CHIP_STM32F303C6 is not set -# CONFIG_ARCH_CHIP_STM32F303C8 is not set -# CONFIG_ARCH_CHIP_STM32F303CB is not set -# CONFIG_ARCH_CHIP_STM32F303CC is not set -# CONFIG_ARCH_CHIP_STM32F303RB is not set -# CONFIG_ARCH_CHIP_STM32F303RC is not set -# CONFIG_ARCH_CHIP_STM32F303RD is not set -# CONFIG_ARCH_CHIP_STM32F303RE is not set -# CONFIG_ARCH_CHIP_STM32F303VB is not set -# CONFIG_ARCH_CHIP_STM32F303VC is not set -# CONFIG_ARCH_CHIP_STM32F372C8 is not set -# CONFIG_ARCH_CHIP_STM32F372R8 is not set -# CONFIG_ARCH_CHIP_STM32F372V8 is not set -# CONFIG_ARCH_CHIP_STM32F372CB is not set -# CONFIG_ARCH_CHIP_STM32F372RB is not set -# CONFIG_ARCH_CHIP_STM32F372VB is not set -# CONFIG_ARCH_CHIP_STM32F372CC is not set -# CONFIG_ARCH_CHIP_STM32F372RC is not set -# CONFIG_ARCH_CHIP_STM32F372VC is not set -# CONFIG_ARCH_CHIP_STM32F373C8 is not set -# CONFIG_ARCH_CHIP_STM32F373R8 is not set -# CONFIG_ARCH_CHIP_STM32F373V8 is not set -# CONFIG_ARCH_CHIP_STM32F373CB is not set -# CONFIG_ARCH_CHIP_STM32F373RB is not set -# CONFIG_ARCH_CHIP_STM32F373VB is not set -# CONFIG_ARCH_CHIP_STM32F373CC is not set -# CONFIG_ARCH_CHIP_STM32F373RC is not set -# CONFIG_ARCH_CHIP_STM32F373VC is not set -# CONFIG_ARCH_CHIP_STM32F401RE is not set -# CONFIG_ARCH_CHIP_STM32F411RE is not set -# CONFIG_ARCH_CHIP_STM32F411VE is not set -# CONFIG_ARCH_CHIP_STM32F405RG is not set -# CONFIG_ARCH_CHIP_STM32F405VG is not set -# CONFIG_ARCH_CHIP_STM32F405ZG is not set -# CONFIG_ARCH_CHIP_STM32F407VE is not set -# CONFIG_ARCH_CHIP_STM32F407VG is not set -# CONFIG_ARCH_CHIP_STM32F407ZE is not set -# CONFIG_ARCH_CHIP_STM32F407ZG is not set -# CONFIG_ARCH_CHIP_STM32F407IE is not set -# CONFIG_ARCH_CHIP_STM32F407IG is not set -# CONFIG_ARCH_CHIP_STM32F427V is not set -# CONFIG_ARCH_CHIP_STM32F427Z is not set -# CONFIG_ARCH_CHIP_STM32F427I is not set -# CONFIG_ARCH_CHIP_STM32F429V is not set -# CONFIG_ARCH_CHIP_STM32F429Z is not set -# CONFIG_ARCH_CHIP_STM32F429I is not set -# CONFIG_ARCH_CHIP_STM32F429B is not set -# CONFIG_ARCH_CHIP_STM32F429N is not set -# CONFIG_ARCH_CHIP_STM32F446M is not set -# CONFIG_ARCH_CHIP_STM32F446R is not set -# CONFIG_ARCH_CHIP_STM32F446V is not set -# CONFIG_ARCH_CHIP_STM32F446Z is not set -# CONFIG_ARCH_CHIP_STM32F469A is not set -# CONFIG_ARCH_CHIP_STM32F469I is not set -# CONFIG_ARCH_CHIP_STM32F469B is not set -# CONFIG_ARCH_CHIP_STM32F469N is not set -CONFIG_STM32_FLASH_CONFIG_DEFAULT=y -# CONFIG_STM32_FLASH_CONFIG_4 is not set -# CONFIG_STM32_FLASH_CONFIG_6 is not set -# CONFIG_STM32_FLASH_CONFIG_8 is not set -# CONFIG_STM32_FLASH_CONFIG_B is not set -# CONFIG_STM32_FLASH_CONFIG_C is not set -# CONFIG_STM32_FLASH_CONFIG_D is not set -# CONFIG_STM32_FLASH_CONFIG_E is not set -# CONFIG_STM32_FLASH_CONFIG_F is not set -# CONFIG_STM32_FLASH_CONFIG_G is not set -# CONFIG_STM32_FLASH_CONFIG_I is not set -# CONFIG_STM32_STM32L15XX is not set -# CONFIG_STM32_ENERGYLITE is not set -CONFIG_STM32_STM32F10XX=y -# CONFIG_STM32_VALUELINE is not set -# CONFIG_STM32_CONNECTIVITYLINE is not set -CONFIG_STM32_PERFORMANCELINE=y -# CONFIG_STM32_USBACCESSLINE is not set -CONFIG_STM32_HIGHDENSITY=y -# CONFIG_STM32_MEDIUMDENSITY is not set -# CONFIG_STM32_LOWDENSITY is not set -# CONFIG_STM32_STM32F20XX is not set -# CONFIG_STM32_STM32F205 is not set -# CONFIG_STM32_STM32F207 is not set -# CONFIG_STM32_STM32F30XX is not set -# CONFIG_STM32_STM32F302 is not set -# CONFIG_STM32_STM32F303 is not set -# CONFIG_STM32_STM32F37XX is not set -# CONFIG_STM32_STM32F40XX is not set -# CONFIG_STM32_STM32F401 is not set -# CONFIG_STM32_STM32F411 is not set -# CONFIG_STM32_STM32F405 is not set -# CONFIG_STM32_STM32F407 is not set -# CONFIG_STM32_STM32F427 is not set -# CONFIG_STM32_STM32F429 is not set -# CONFIG_STM32_STM32F446 is not set -# CONFIG_STM32_STM32F469 is not set -CONFIG_STM32_DFU=y - -# -# STM32 Peripheral Support -# -# CONFIG_STM32_HAVE_CCM is not set -CONFIG_STM32_HAVE_USBDEV=y -# CONFIG_STM32_HAVE_OTGFS is not set -CONFIG_STM32_HAVE_FSMC=y -# CONFIG_STM32_HAVE_LTDC is not set -CONFIG_STM32_HAVE_USART3=y -CONFIG_STM32_HAVE_UART4=y -CONFIG_STM32_HAVE_UART5=y -# CONFIG_STM32_HAVE_USART6 is not set -# CONFIG_STM32_HAVE_UART7 is not set -# CONFIG_STM32_HAVE_UART8 is not set -CONFIG_STM32_HAVE_TIM1=y -# CONFIG_STM32_HAVE_TIM2 is not set -CONFIG_STM32_HAVE_TIM3=y -CONFIG_STM32_HAVE_TIM4=y -CONFIG_STM32_HAVE_TIM5=y -CONFIG_STM32_HAVE_TIM6=y -CONFIG_STM32_HAVE_TIM7=y -CONFIG_STM32_HAVE_TIM8=y -# CONFIG_STM32_HAVE_TIM9 is not set -# CONFIG_STM32_HAVE_TIM10 is not set -# CONFIG_STM32_HAVE_TIM11 is not set -# CONFIG_STM32_HAVE_TIM12 is not set -# CONFIG_STM32_HAVE_TIM13 is not set -# CONFIG_STM32_HAVE_TIM14 is not set -# CONFIG_STM32_HAVE_TIM15 is not set -# CONFIG_STM32_HAVE_TIM16 is not set -# CONFIG_STM32_HAVE_TIM17 is not set -CONFIG_STM32_HAVE_ADC2=y -CONFIG_STM32_HAVE_ADC3=y -# CONFIG_STM32_HAVE_ADC4 is not set -# CONFIG_STM32_HAVE_ADC1_DMA is not set -# CONFIG_STM32_HAVE_ADC2_DMA is not set -# CONFIG_STM32_HAVE_ADC3_DMA is not set -# CONFIG_STM32_HAVE_ADC4_DMA is not set -CONFIG_STM32_HAVE_CAN1=y -# CONFIG_STM32_HAVE_CAN2 is not set -CONFIG_STM32_HAVE_DAC1=y -CONFIG_STM32_HAVE_DAC2=y -# CONFIG_STM32_HAVE_RNG is not set -# CONFIG_STM32_HAVE_ETHMAC is not set -CONFIG_STM32_HAVE_I2C2=y -# CONFIG_STM32_HAVE_I2C3 is not set -CONFIG_STM32_HAVE_SPI2=y -CONFIG_STM32_HAVE_SPI3=y -# CONFIG_STM32_HAVE_SPI4 is not set -# CONFIG_STM32_HAVE_SPI5 is not set -# CONFIG_STM32_HAVE_SPI6 is not set -# CONFIG_STM32_HAVE_SAIPLL is not set -# CONFIG_STM32_HAVE_I2SPLL is not set -# CONFIG_STM32_ADC1 is not set -# CONFIG_STM32_ADC2 is not set -# CONFIG_STM32_ADC3 is not set -# CONFIG_STM32_BKP is not set -# CONFIG_STM32_CAN1 is not set -# CONFIG_STM32_CRC is not set -# CONFIG_STM32_DMA1 is not set -# CONFIG_STM32_DMA2 is not set -# CONFIG_STM32_DAC1 is not set -# CONFIG_STM32_DAC2 is not set -CONFIG_STM32_FSMC=y -# CONFIG_STM32_I2C1 is not set -# CONFIG_STM32_I2C2 is not set -# CONFIG_STM32_PWR is not set -# CONFIG_STM32_SDIO is not set -# CONFIG_STM32_SPI1 is not set -# CONFIG_STM32_SPI2 is not set -# CONFIG_STM32_SPI3 is not set -# CONFIG_STM32_TIM1 is not set -# CONFIG_STM32_TIM2 is not set -# CONFIG_STM32_TIM3 is not set -# CONFIG_STM32_TIM4 is not set -# CONFIG_STM32_TIM5 is not set -# CONFIG_STM32_TIM6 is not set -# CONFIG_STM32_TIM7 is not set -# CONFIG_STM32_TIM8 is not set -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -# CONFIG_STM32_USART3 is not set -# CONFIG_STM32_UART4 is not set -# CONFIG_STM32_UART5 is not set -# CONFIG_STM32_USB is not set -# CONFIG_STM32_IWDG is not set -# CONFIG_STM32_WWDG is not set -# CONFIG_STM32_NOEXT_VECTORS is not set - -# -# Alternate Pin Mapping -# -# CONFIG_STM32_USART1_REMAP is not set -# CONFIG_STM32_USART2_REMAP is not set -# CONFIG_STM32_JTAG_DISABLE is not set -CONFIG_STM32_JTAG_FULL_ENABLE=y -# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set -# CONFIG_STM32_JTAG_SW_ENABLE is not set -# CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG is not set -# CONFIG_STM32_FORCEPOWER is not set -# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set -# CONFIG_STM32_FSMC_SRAM is not set - -# -# Timer Configuration -# -# CONFIG_STM32_ONESHOT is not set -# CONFIG_STM32_FREERUN is not set -# CONFIG_STM32_TIM1_CAP is not set -# CONFIG_STM32_TIM3_CAP is not set -# CONFIG_STM32_TIM4_CAP is not set -# CONFIG_STM32_TIM5_CAP is not set -# CONFIG_STM32_TIM8_CAP is not set -CONFIG_STM32_USART=y -CONFIG_STM32_SERIALDRIVER=y - -# -# U[S]ART Configuration -# - -# -# U[S]ART Device Configuration -# -CONFIG_STM32_USART1_SERIALDRIVER=y -# CONFIG_STM32_USART1_1WIREDRIVER is not set -# CONFIG_USART1_RS485 is not set -CONFIG_STM32_USART2_SERIALDRIVER=y -# CONFIG_STM32_USART2_1WIREDRIVER is not set -# CONFIG_USART2_RS485 is not set - -# -# Serial Driver Configuration -# -# CONFIG_SERIAL_DISABLE_REORDERING is not set -# CONFIG_STM32_FLOWCONTROL_BROKEN is not set -# CONFIG_STM32_USART_BREAKS is not set -# CONFIG_STM32_USART_SINGLEWIRE is not set -CONFIG_STM32_HAVE_RTC_COUNTER=y -# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set - -# -# USB FS Host Configuration -# - -# -# USB HS Host Configuration -# - -# -# USB Host Debug Configuration -# - -# -# USB Device Configuration -# - -# -# Architecture Options -# -# CONFIG_ARCH_NOINTC is not set -# CONFIG_ARCH_VECNOTIRQ is not set -# CONFIG_ARCH_DMA is not set -CONFIG_ARCH_HAVE_IRQPRIO=y -# CONFIG_ARCH_L2CACHE is not set -# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set -# CONFIG_ARCH_HAVE_ADDRENV is not set -# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set -# CONFIG_ARCH_HAVE_MULTICPU is not set -CONFIG_ARCH_HAVE_VFORK=y -# CONFIG_ARCH_HAVE_MMU is not set -CONFIG_ARCH_HAVE_MPU=y -# CONFIG_ARCH_NAND_HWECC is not set -# CONFIG_ARCH_HAVE_EXTCLK is not set -# CONFIG_ARCH_HAVE_POWEROFF is not set -CONFIG_ARCH_HAVE_RESET=y -# CONFIG_ARCH_USE_MPU is not set -# CONFIG_ARCH_IRQPRIO is not set -CONFIG_ARCH_STACKDUMP=y -# CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_IDLE_CUSTOM is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set -CONFIG_ARCH_HAVE_RAMVECTORS=y -# CONFIG_ARCH_RAMVECTORS is not set - -# -# Board Settings -# -CONFIG_BOARD_LOOPSPERMSEC=5483 -# CONFIG_ARCH_CALIBRATION is not set - -# -# Interrupt options -# -CONFIG_ARCH_HAVE_INTERRUPTSTACK=y -CONFIG_ARCH_INTERRUPTSTACK=0 -CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y -# CONFIG_ARCH_HIPRI_INTERRUPT is not set - -# -# Boot options -# -# CONFIG_BOOT_RUNFROMEXTSRAM is not set -CONFIG_BOOT_RUNFROMFLASH=y -# CONFIG_BOOT_RUNFROMISRAM is not set -# CONFIG_BOOT_RUNFROMSDRAM is not set -# CONFIG_BOOT_COPYTORAM is not set - -# -# Boot Memory Configuration -# -CONFIG_RAM_START=0x20000000 -CONFIG_RAM_SIZE=65536 -# CONFIG_ARCH_HAVE_SDRAM is not set - -# -# Board Selection -# -CONFIG_ARCH_BOARD_STM3210E_EVAL=y -# CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD="stm3210e-eval" - -# -# Common Board Options -# -CONFIG_ARCH_HAVE_LEDS=y -CONFIG_ARCH_LEDS=y -CONFIG_ARCH_HAVE_BUTTONS=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_HAVE_IRQBUTTONS=y -CONFIG_ARCH_IRQBUTTONS=y - -# -# Board-Specific Options -# - -# -# STM3210E-EVAL LCD Hardware Configuration -# -# CONFIG_STM3210E_LCD is not set -# CONFIG_BOARD_CRASHDUMP is not set -# CONFIG_LIB_BOARDCTL is not set - -# -# RTOS Features -# -CONFIG_DISABLE_OS_API=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=y -# CONFIG_DISABLE_SIGNALS is not set -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_ENVIRON=y - -# -# Clocks and Timers -# -CONFIG_ARCH_HAVE_TICKLESS=y -# CONFIG_SCHED_TICKLESS is not set -CONFIG_USEC_PER_TICK=10000 -# CONFIG_SYSTEM_TIME64 is not set -# CONFIG_CLOCK_MONOTONIC is not set -CONFIG_ARCH_HAVE_TIMEKEEPING=y -# CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2011 -CONFIG_START_MONTH=7 -CONFIG_START_DAY=7 -CONFIG_MAX_WDOGPARMS=2 -CONFIG_PREALLOC_WDOGS=4 -CONFIG_WDOG_INTRESERVE=0 -CONFIG_PREALLOC_TIMERS=4 - -# -# Tasks and Scheduling -# -# CONFIG_INIT_NONE is not set -CONFIG_INIT_ENTRYPOINT=y -# CONFIG_INIT_FILEPATH is not set -CONFIG_USER_ENTRYPOINT="archbuttons_main" -CONFIG_RR_INTERVAL=200 -# CONFIG_SCHED_SPORADIC is not set -CONFIG_TASK_NAME_SIZE=0 -CONFIG_MAX_TASKS=8 -# CONFIG_SCHED_HAVE_PARENT is not set -# CONFIG_SCHED_WAITPID is not set - -# -# Performance Monitoring -# -# CONFIG_SCHED_CPULOAD is not set -# CONFIG_SCHED_INSTRUMENTATION is not set - -# -# Files and I/O -# -CONFIG_DEV_CONSOLE=y -# CONFIG_FDCLONE_DISABLE is not set -# CONFIG_FDCLONE_STDIO is not set -CONFIG_SDCLONE_DISABLE=y -CONFIG_NFILE_DESCRIPTORS=6 -CONFIG_NFILE_STREAMS=6 -CONFIG_NAME_MAX=32 -# CONFIG_PRIORITY_INHERITANCE is not set - -# -# RTOS hooks -# -# CONFIG_BOARD_INITIALIZE is not set -# CONFIG_SCHED_STARTHOOK is not set -# CONFIG_SCHED_ATEXIT is not set -# CONFIG_SCHED_ONEXIT is not set - -# -# Signal Numbers -# -CONFIG_SIG_SIGUSR1=1 -CONFIG_SIG_SIGUSR2=2 -CONFIG_SIG_SIGALARM=3 -# CONFIG_MODULE is not set - -# -# Work queue support -# -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set -# CONFIG_SCHED_LPWORK is not set - -# -# Stack and heap information -# -CONFIG_IDLETHREAD_STACKSIZE=1024 -CONFIG_USERMAIN_STACKSIZE=2048 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=2048 -# CONFIG_LIB_SYSCALL is not set - -# -# Device Drivers -# -CONFIG_DISABLE_POLL=y -CONFIG_DEV_NULL=y -# CONFIG_DEV_ZERO is not set -# CONFIG_DEV_URANDOM is not set -# CONFIG_DEV_LOOP is not set - -# -# Buffering -# -# CONFIG_DRVR_WRITEBUFFER is not set -# CONFIG_DRVR_READAHEAD is not set -# CONFIG_RAMDISK is not set -# CONFIG_CAN is not set -# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set -# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set -# CONFIG_PWM is not set -CONFIG_ARCH_HAVE_I2CRESET=y -# CONFIG_I2C is not set -# CONFIG_SPI is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y -# CONFIG_I2S is not set - -# -# Timer Driver Support -# -# CONFIG_TIMER is not set -# CONFIG_ONESHOT is not set -# CONFIG_RTC is not set -# CONFIG_WATCHDOG is not set -# CONFIG_ANALOG is not set -# CONFIG_AUDIO_DEVICES is not set -# CONFIG_VIDEO_DEVICES is not set -# CONFIG_BCH is not set -# CONFIG_INPUT is not set - -# -# IO Expander/GPIO Support -# -# CONFIG_IOEXPANDER is not set -# CONFIG_DEV_GPIO is not set - -# -# LCD Driver Support -# -# CONFIG_LCD is not set -# CONFIG_SLCD is not set - -# -# LED Support -# -# CONFIG_USERLED is not set -# CONFIG_RGBLED is not set -# CONFIG_PCA9635PW is not set -# CONFIG_NCP5623C is not set -# CONFIG_MMCSD is not set -# CONFIG_MODEM is not set -# CONFIG_MTD is not set -# CONFIG_EEPROM is not set -# CONFIG_PIPES is not set -# CONFIG_PM is not set -# CONFIG_POWER is not set -# CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set -CONFIG_SERIAL=y -CONFIG_DEV_LOWCONSOLE=y -# CONFIG_SERIAL_REMOVABLE is not set -CONFIG_SERIAL_CONSOLE=y -# CONFIG_16550_UART is not set -# CONFIG_UART_SERIALDRIVER is not set -# CONFIG_UART0_SERIALDRIVER is not set -# CONFIG_UART1_SERIALDRIVER is not set -# CONFIG_UART2_SERIALDRIVER is not set -# CONFIG_UART3_SERIALDRIVER is not set -# CONFIG_UART4_SERIALDRIVER is not set -# CONFIG_UART5_SERIALDRIVER is not set -# CONFIG_UART6_SERIALDRIVER is not set -# CONFIG_UART7_SERIALDRIVER is not set -# CONFIG_UART8_SERIALDRIVER is not set -# CONFIG_SCI0_SERIALDRIVER is not set -# CONFIG_SCI1_SERIALDRIVER is not set -# CONFIG_USART0_SERIALDRIVER is not set -CONFIG_USART1_SERIALDRIVER=y -CONFIG_USART2_SERIALDRIVER=y -# CONFIG_USART3_SERIALDRIVER is not set -# CONFIG_USART4_SERIALDRIVER is not set -# CONFIG_USART5_SERIALDRIVER is not set -# CONFIG_USART6_SERIALDRIVER is not set -# CONFIG_USART7_SERIALDRIVER is not set -# CONFIG_USART8_SERIALDRIVER is not set -# CONFIG_OTHER_UART_SERIALDRIVER is not set -CONFIG_MCU_SERIAL=y -# CONFIG_SERIAL_IFLOWCONTROL is not set -# CONFIG_SERIAL_OFLOWCONTROL is not set -# CONFIG_SERIAL_DMA is not set -CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y -CONFIG_USART1_SERIAL_CONSOLE=y -# CONFIG_USART2_SERIAL_CONSOLE is not set -# CONFIG_OTHER_SERIAL_CONSOLE is not set -# CONFIG_NO_SERIAL_CONSOLE is not set - -# -# USART1 Configuration -# -CONFIG_USART1_RXBUFSIZE=256 -CONFIG_USART1_TXBUFSIZE=256 -CONFIG_USART1_BAUD=115200 -CONFIG_USART1_BITS=8 -CONFIG_USART1_PARITY=0 -CONFIG_USART1_2STOP=0 -# CONFIG_USART1_IFLOWCONTROL is not set -# CONFIG_USART1_OFLOWCONTROL is not set -# CONFIG_USART1_DMA is not set - -# -# USART2 Configuration -# -CONFIG_USART2_RXBUFSIZE=256 -CONFIG_USART2_TXBUFSIZE=256 -CONFIG_USART2_BAUD=115200 -CONFIG_USART2_BITS=8 -CONFIG_USART2_PARITY=0 -CONFIG_USART2_2STOP=0 -# CONFIG_USART2_IFLOWCONTROL is not set -# CONFIG_USART2_OFLOWCONTROL is not set -# CONFIG_USART2_DMA is not set -# CONFIG_PSEUDOTERM is not set -# CONFIG_USBDEV is not set -# CONFIG_USBHOST is not set -# CONFIG_HAVE_USBTRACE is not set -# CONFIG_DRIVERS_WIRELESS is not set -# CONFIG_DRIVERS_CONTACTLESS is not set - -# -# System Logging -# -# CONFIG_ARCH_SYSLOG is not set -# CONFIG_RAMLOG is not set -# CONFIG_SYSLOG_INTBUFFER is not set -# CONFIG_SYSLOG_TIMESTAMP is not set -CONFIG_SYSLOG_SERIAL_CONSOLE=y -# CONFIG_SYSLOG_CHAR is not set -CONFIG_SYSLOG_CONSOLE=y -# CONFIG_SYSLOG_NONE is not set -# CONFIG_SYSLOG_FILE is not set -# CONFIG_SYSLOG_CHARDEV is not set - -# -# Networking Support -# -# CONFIG_ARCH_HAVE_NET is not set -# CONFIG_ARCH_HAVE_PHY is not set -# CONFIG_NET is not set - -# -# Crypto API -# -# CONFIG_CRYPTO is not set - -# -# File Systems -# - -# -# File system configuration -# -CONFIG_DISABLE_MOUNTPOINT=y -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_FS_READABLE is not set -# CONFIG_FS_WRITABLE is not set -# CONFIG_FS_NAMED_SEMAPHORES is not set -# CONFIG_FS_RAMMAP is not set -# CONFIG_FS_PROCFS is not set -# CONFIG_FS_UNIONFS is not set - -# -# Graphics Support -# -# CONFIG_NX is not set - -# -# Memory Management -# -# CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=1 -# CONFIG_ARCH_HAVE_HEAP2 is not set -# CONFIG_GRAN is not set - -# -# Audio Support -# -# CONFIG_AUDIO is not set - -# -# Wireless Support -# - -# -# Binary Loader -# -# CONFIG_BINFMT_DISABLE is not set -# CONFIG_NXFLAT is not set -# CONFIG_ELF is not set -# CONFIG_BUILTIN is not set -# CONFIG_PIC is not set -# CONFIG_SYMTAB_ORDEREDBYNAME is not set - -# -# Library Routines -# - -# -# Standard C Library Options -# -CONFIG_STDIO_BUFFER_SIZE=64 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=2 -# CONFIG_LIBM is not set -# CONFIG_NOPRINTF_FIELDWIDTH is not set -# CONFIG_LIBC_FLOATINGPOINT is not set -CONFIG_LIBC_LONG_LONG=y -# CONFIG_LIBC_IOCTL_VARIADIC is not set -# CONFIG_LIBC_WCHAR is not set -# CONFIG_LIBC_LOCALE is not set -CONFIG_LIB_RAND_ORDER=1 -# CONFIG_EOL_IS_CR is not set -# CONFIG_EOL_IS_LF is not set -# CONFIG_EOL_IS_BOTH_CRLF is not set -CONFIG_EOL_IS_EITHER_CRLF=y -# CONFIG_LIBC_EXECFUNCS is not set -CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 -# CONFIG_LIBC_STRERROR is not set -# CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_ARCH_LOWPUTC=y -# CONFIG_TIME_EXTENDED is not set -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set -# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set -CONFIG_ARCH_HAVE_TLS=y -# CONFIG_TLS is not set -# CONFIG_LIBC_NETDB is not set - -# -# Non-standard Library Support -# -# CONFIG_LIB_CRC64_FAST is not set -# CONFIG_LIB_KBDCODEC is not set -# CONFIG_LIB_SLCDCODEC is not set -# CONFIG_LIB_HEX2BIN is not set - -# -# Basic CXX Support -# -# CONFIG_C99_BOOL8 is not set -# CONFIG_HAVE_CXX is not set - -# -# Application Configuration -# - -# -# CAN Utilities -# - -# -# Examples -# -CONFIG_EXAMPLES_ARCHBUTTONS=y -CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 -CONFIG_EXAMPLES_ARCHBUTTONS_MAX=7 -CONFIG_EXAMPLES_IRQBUTTONS_MIN=2 -CONFIG_EXAMPLES_IRQBUTTONS_MAX=7 -CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="WAKEUP" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="TAMPER" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="KEY" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="SELECT" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="DOWN" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="LEFT" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="RIGHT" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="UP" -# CONFIG_EXAMPLES_BUTTONS is not set -# CONFIG_EXAMPLES_CHAT is not set -# CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_DHCPD is not set -# CONFIG_EXAMPLES_ELF is not set -# CONFIG_EXAMPLES_FTPC is not set -# CONFIG_EXAMPLES_FTPD is not set -# CONFIG_EXAMPLES_HELLO is not set -# CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_IGMP is not set -# CONFIG_EXAMPLES_JSON is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set -# CONFIG_EXAMPLES_MEDIA is not set -# CONFIG_EXAMPLES_MM is not set -# CONFIG_EXAMPLES_MODBUS is not set -# CONFIG_EXAMPLES_MOUNT is not set -# CONFIG_EXAMPLES_NRF24L01TERM is not set -# CONFIG_EXAMPLES_NSH is not set -# CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXFFS is not set -# CONFIG_EXAMPLES_NXHELLO is not set -# CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NXLINES is not set -# CONFIG_EXAMPLES_NXTERM is not set -# CONFIG_EXAMPLES_NXTEXT is not set -# CONFIG_EXAMPLES_OSTEST is not set -# CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_PPPD is not set -# CONFIG_EXAMPLES_RFID_READUID is not set -# CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set -# CONFIG_EXAMPLES_SENDMAIL is not set -# CONFIG_EXAMPLES_SERIALBLASTER is not set -# CONFIG_EXAMPLES_SERIALRX is not set -# CONFIG_EXAMPLES_SERLOOP is not set -# CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART is not set -# CONFIG_EXAMPLES_SMP is not set -# CONFIG_EXAMPLES_TCPECHO is not set -# CONFIG_EXAMPLES_TELNETD is not set -# CONFIG_EXAMPLES_TIFF is not set -# CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_USBTERM is not set -# CONFIG_EXAMPLES_WATCHDOG is not set -# CONFIG_EXAMPLES_WEBSERVER is not set - -# -# File System Utilities -# -# CONFIG_FSUTILS_INIFILE is not set - -# -# GPS Utilities -# -# CONFIG_GPSUTILS_MINMEA_LIB is not set - -# -# Graphics Support -# -# CONFIG_TIFF is not set -# CONFIG_GRAPHICS_TRAVELER is not set - -# -# Interpreters -# -# CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_MICROPYTHON is not set -# CONFIG_INTERPRETERS_MINIBASIC is not set -# CONFIG_INTERPRETERS_PCODE is not set - -# -# FreeModBus -# -# CONFIG_MODBUS is not set - -# -# Network Utilities -# -# CONFIG_NETUTILS_CODECS is not set -# CONFIG_NETUTILS_ESP8266 is not set -# CONFIG_NETUTILS_FTPC is not set -# CONFIG_NETUTILS_JSON is not set -# CONFIG_NETUTILS_SMTP is not set - -# -# NSH Library -# -# CONFIG_NSH_LIBRARY is not set - -# -# NxWidgets/NxWM -# - -# -# Platform-specific Support -# -# CONFIG_PLATFORM_CONFIGDATA is not set - -# -# System Libraries and NSH Add-Ons -# -# CONFIG_SYSTEM_CLE is not set -# CONFIG_SYSTEM_CUTERM is not set -# CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set -# CONFIG_SYSTEM_HEXED is not set -# CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_RAMTEST is not set -# CONFIG_READLINE_HAVE_EXTMATCH is not set -# CONFIG_SYSTEM_READLINE is not set -# CONFIG_SYSTEM_SUDOKU is not set -# CONFIG_SYSTEM_TEE is not set -# CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_VI is not set -# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3210e-eval/buttons/setenv.sh b/configs/stm3210e-eval/buttons/setenv.sh deleted file mode 100755 index 2bdf536742..0000000000 --- a/configs/stm3210e-eval/buttons/setenv.sh +++ /dev/null @@ -1,47 +0,0 @@ -#!/bin/bash -# configs/stm3210e-eval/buttons/setenv.sh -# -# Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if [ "$(basename $0)" = "setenv.sh" ] ; then - echo "You must source this script, not run it!" 1>&2 - exit 1 -fi - -if [ -z "${PATH_ORIG}" ]; then export PATH_ORIG="${PATH}"; fi - -WD=`pwd` -export RIDE_BIN="/cygdrive/c/Program Files/Raisonance/Ride/arm-gcc/bin" -export BUILDROOT_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" -export PATH="${BUILDROOT_BIN}:${RIDE_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" - -echo "PATH : ${PATH}" -- GitLab From 30318225180e2888a778c86228d5f48e42535366 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 22 Nov 2016 07:37:23 -0600 Subject: [PATCH 482/734] configs: Remove all traces of the no-longer existent ARCHBUTTONS example. --- configs/dk-tm4c129x/ipv6/defconfig | 1 - configs/dk-tm4c129x/nsh/defconfig | 1 - configs/hymini-stm32v/nsh2/defconfig | 28 ++++++++----------- configs/hymini-stm32v/usbnsh/defconfig | 24 ++++++++-------- configs/nucleo-f303re/adc/defconfig | 1 - configs/nucleo-f303re/can/defconfig | 1 - configs/nucleo-f303re/hello/defconfig | 1 - configs/nucleo-f303re/nxlines/defconfig | 1 - configs/nucleo-f303re/pwm/defconfig | 1 - configs/nucleo-f303re/uavcan/defconfig | 1 - configs/olimex-stm32-e407/discover/defconfig | 1 - configs/olimex-stm32-e407/netnsh/defconfig | 1 - configs/olimex-stm32-e407/telnetd/defconfig | 1 - configs/olimex-stm32-e407/webserver/defconfig | 1 - configs/olimex-stm32-h405/usbnsh/defconfig | 24 ++++++++-------- configs/olimex-stm32-p207/nsh/defconfig | 13 --------- configs/olimex-strp711/nettest/defconfig | 1 - configs/olimexino-stm32/composite/defconfig | 28 ++++++++----------- configs/olimexino-stm32/nsh/defconfig | 28 ++++++++----------- configs/sabre-6quad/nsh/defconfig | 1 - configs/sabre-6quad/smp/defconfig | 1 - configs/sam4e-ek/nsh/defconfig | 1 - configs/sam4e-ek/nxwm/defconfig | 1 - configs/sam4e-ek/usbnsh/defconfig | 1 - configs/sama5d4-ek/ipv6/defconfig | 13 --------- configs/sama5d4-ek/nsh/defconfig | 13 --------- configs/sama5d4-ek/nxwm/defconfig | 13 --------- configs/same70-xplained/netnsh/defconfig | 13 --------- configs/same70-xplained/nsh/defconfig | 22 ++++----------- configs/samv71-xult/mxtxplnd/defconfig | 22 ++++----------- configs/samv71-xult/netnsh/defconfig | 13 --------- configs/samv71-xult/nsh/defconfig | 14 +--------- configs/samv71-xult/vnc/defconfig | 1 - configs/samv71-xult/vnxwm/defconfig | 1 - configs/stm3210e-eval/pm/defconfig | 1 - configs/stm32butterfly2/nsh/defconfig | 20 ++++++++----- configs/stm32butterfly2/nshnet/defconfig | 3 -- configs/stm32butterfly2/nshusbdev/defconfig | 20 ++++++++----- configs/stm32butterfly2/nshusbhost/defconfig | 20 ++++++++----- configs/stm32f103-minimum/buttons/defconfig | 1 - configs/stm32f4discovery/ipv6/defconfig | 1 - configs/stm32f4discovery/netnsh/defconfig | 1 - configs/stm32l476vg-disco/nsh/defconfig | 28 +++++++------------ configs/tm4c1294-launchpad/ipv6/defconfig | 1 - configs/viewtool-stm32f107/highpri/defconfig | 1 - configs/viewtool-stm32f107/nsh/defconfig | 1 - 46 files changed, 120 insertions(+), 266 deletions(-) diff --git a/configs/dk-tm4c129x/ipv6/defconfig b/configs/dk-tm4c129x/ipv6/defconfig index 31725598d3..040b6d517a 100644 --- a/configs/dk-tm4c129x/ipv6/defconfig +++ b/configs/dk-tm4c129x/ipv6/defconfig @@ -920,7 +920,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/dk-tm4c129x/nsh/defconfig b/configs/dk-tm4c129x/nsh/defconfig index 86d440f9e4..b871146318 100644 --- a/configs/dk-tm4c129x/nsh/defconfig +++ b/configs/dk-tm4c129x/nsh/defconfig @@ -930,7 +930,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/hymini-stm32v/nsh2/defconfig b/configs/hymini-stm32v/nsh2/defconfig index 79ee362dc1..5777261820 100644 --- a/configs/hymini-stm32v/nsh2/defconfig +++ b/configs/hymini-stm32v/nsh2/defconfig @@ -61,11 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -352,6 +354,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y # CONFIG_STM32_HAVE_CAN2 is not set CONFIG_STM32_HAVE_DAC1=y @@ -707,14 +715,14 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -1170,20 +1178,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -CONFIG_EXAMPLES_ARCHBUTTONS=y -CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 -CONFIG_EXAMPLES_ARCHBUTTONS_MAX=1 -CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 -CONFIG_EXAMPLES_IRQBUTTONS_MAX=1 -CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="Key A" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Key B" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set diff --git a/configs/hymini-stm32v/usbnsh/defconfig b/configs/hymini-stm32v/usbnsh/defconfig index 1c7d14202f..37d610d61e 100644 --- a/configs/hymini-stm32v/usbnsh/defconfig +++ b/configs/hymini-stm32v/usbnsh/defconfig @@ -61,11 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -350,6 +352,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y # CONFIG_STM32_HAVE_CAN2 is not set CONFIG_STM32_HAVE_DAC1=y @@ -684,6 +692,8 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -967,20 +977,8 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # -CONFIG_EXAMPLES_ARCHBUTTONS=y -CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 -CONFIG_EXAMPLES_ARCHBUTTONS_MAX=1 -CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 -CONFIG_EXAMPLES_IRQBUTTONS_MAX=1 -CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="Key A" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Key B" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set diff --git a/configs/nucleo-f303re/adc/defconfig b/configs/nucleo-f303re/adc/defconfig index 4b67445407..0e2f3b1adc 100644 --- a/configs/nucleo-f303re/adc/defconfig +++ b/configs/nucleo-f303re/adc/defconfig @@ -884,7 +884,6 @@ CONFIG_EXAMPLES_ADC_DEVPATH="/dev/adc0" CONFIG_EXAMPLES_ADC_NSAMPLES=0 CONFIG_EXAMPLES_ADC_GROUPSIZE=4 CONFIG_EXAMPLES_ADC_SWTRIG=y -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/nucleo-f303re/can/defconfig b/configs/nucleo-f303re/can/defconfig index 3450575cbf..f6e0027a8a 100644 --- a/configs/nucleo-f303re/can/defconfig +++ b/configs/nucleo-f303re/can/defconfig @@ -882,7 +882,6 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set CONFIG_EXAMPLES_CAN=y CONFIG_EXAMPLES_CAN_DEVPATH="/dev/can0" diff --git a/configs/nucleo-f303re/hello/defconfig b/configs/nucleo-f303re/hello/defconfig index 9c434786e3..bc432a230b 100644 --- a/configs/nucleo-f303re/hello/defconfig +++ b/configs/nucleo-f303re/hello/defconfig @@ -931,7 +931,6 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/nucleo-f303re/nxlines/defconfig b/configs/nucleo-f303re/nxlines/defconfig index 6eb9debcdb..ba05ea87b6 100644 --- a/configs/nucleo-f303re/nxlines/defconfig +++ b/configs/nucleo-f303re/nxlines/defconfig @@ -1036,7 +1036,6 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CAN is not set # CONFIG_EXAMPLES_CCTYPE is not set diff --git a/configs/nucleo-f303re/pwm/defconfig b/configs/nucleo-f303re/pwm/defconfig index 0e54eba6eb..4a202c87cd 100644 --- a/configs/nucleo-f303re/pwm/defconfig +++ b/configs/nucleo-f303re/pwm/defconfig @@ -889,7 +889,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/nucleo-f303re/uavcan/defconfig b/configs/nucleo-f303re/uavcan/defconfig index 944984f2d5..a55127ce49 100644 --- a/configs/nucleo-f303re/uavcan/defconfig +++ b/configs/nucleo-f303re/uavcan/defconfig @@ -895,7 +895,6 @@ CONFIG_LIBUAVCAN_INIT_RETRIES=0 # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/olimex-stm32-e407/discover/defconfig b/configs/olimex-stm32-e407/discover/defconfig index ee655a6e3f..adb8afe01b 100644 --- a/configs/olimex-stm32-e407/discover/defconfig +++ b/configs/olimex-stm32-e407/discover/defconfig @@ -1154,7 +1154,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/olimex-stm32-e407/netnsh/defconfig b/configs/olimex-stm32-e407/netnsh/defconfig index 3e13c92c6d..c09c158e18 100644 --- a/configs/olimex-stm32-e407/netnsh/defconfig +++ b/configs/olimex-stm32-e407/netnsh/defconfig @@ -1156,7 +1156,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/olimex-stm32-e407/telnetd/defconfig b/configs/olimex-stm32-e407/telnetd/defconfig index 5e3a351669..a20c3d7cd6 100644 --- a/configs/olimex-stm32-e407/telnetd/defconfig +++ b/configs/olimex-stm32-e407/telnetd/defconfig @@ -1156,7 +1156,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/olimex-stm32-e407/webserver/defconfig b/configs/olimex-stm32-e407/webserver/defconfig index 7ab0ac66f8..124c1c88f9 100644 --- a/configs/olimex-stm32-e407/webserver/defconfig +++ b/configs/olimex-stm32-e407/webserver/defconfig @@ -1154,7 +1154,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/olimex-stm32-h405/usbnsh/defconfig b/configs/olimex-stm32-h405/usbnsh/defconfig index a0deb7cb54..dd4cc0fb40 100644 --- a/configs/olimex-stm32-h405/usbnsh/defconfig +++ b/configs/olimex-stm32-h405/usbnsh/defconfig @@ -61,11 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -357,6 +359,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -737,6 +745,8 @@ CONFIG_CAN_NPENDINGRTR=4 CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -1045,19 +1055,6 @@ CONFIG_EXAMPLES_ADC=y CONFIG_EXAMPLES_ADC_DEVPATH="/dev/adc0" CONFIG_EXAMPLES_ADC_GROUPSIZE=4 # CONFIG_EXAMPLES_ADC_SWTRIG is not set -CONFIG_EXAMPLES_ARCHBUTTONS=y -CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 -CONFIG_EXAMPLES_ARCHBUTTONS_MAX=0 -CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 -CONFIG_EXAMPLES_IRQBUTTONS_MAX=0 -CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="BUT" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Button 1" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_BUTTONS is not set CONFIG_EXAMPLES_CAN=y CONFIG_EXAMPLES_CAN_DEVPATH="/dev/can0" @@ -1065,6 +1062,7 @@ CONFIG_EXAMPLES_CAN_NMSGS=32 # CONFIG_EXAMPLES_CAN_READ is not set # CONFIG_EXAMPLES_CAN_WRITE is not set CONFIG_EXAMPLES_CAN_READWRITE=y +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set diff --git a/configs/olimex-stm32-p207/nsh/defconfig b/configs/olimex-stm32-p207/nsh/defconfig index caa647b50d..2c60b36650 100644 --- a/configs/olimex-stm32-p207/nsh/defconfig +++ b/configs/olimex-stm32-p207/nsh/defconfig @@ -1211,19 +1211,6 @@ CONFIG_EXAMPLES_ADC=y CONFIG_EXAMPLES_ADC_DEVPATH="/dev/adc0" CONFIG_EXAMPLES_ADC_GROUPSIZE=1 # CONFIG_EXAMPLES_ADC_SWTRIG is not set -CONFIG_EXAMPLES_ARCHBUTTONS=y -CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 -CONFIG_EXAMPLES_ARCHBUTTONS_MAX=6 -CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 -CONFIG_EXAMPLES_IRQBUTTONS_MAX=7 -CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="Button 0" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Button 1" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CAN is not set # CONFIG_EXAMPLES_CCTYPE is not set diff --git a/configs/olimex-strp711/nettest/defconfig b/configs/olimex-strp711/nettest/defconfig index 631f41fc69..05e90b4d78 100644 --- a/configs/olimex-strp711/nettest/defconfig +++ b/configs/olimex-strp711/nettest/defconfig @@ -772,7 +772,6 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/olimexino-stm32/composite/defconfig b/configs/olimexino-stm32/composite/defconfig index fcb7a0c8d7..6e75398ee7 100644 --- a/configs/olimexino-stm32/composite/defconfig +++ b/configs/olimexino-stm32/composite/defconfig @@ -61,11 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -350,6 +352,12 @@ CONFIG_STM32_HAVE_ADC1_DMA=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y # CONFIG_STM32_HAVE_CAN2 is not set # CONFIG_STM32_HAVE_DAC1 is not set @@ -717,14 +725,14 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -1101,20 +1109,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=768 # # Examples # -CONFIG_EXAMPLES_ARCHBUTTONS=y -CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 -CONFIG_EXAMPLES_ARCHBUTTONS_MAX=0 -CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 -CONFIG_EXAMPLES_IRQBUTTONS_MAX=0 -CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="BOOT 0" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Button 1" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set diff --git a/configs/olimexino-stm32/nsh/defconfig b/configs/olimexino-stm32/nsh/defconfig index 8b9fd359f9..43c0283f2d 100644 --- a/configs/olimexino-stm32/nsh/defconfig +++ b/configs/olimexino-stm32/nsh/defconfig @@ -61,11 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -350,6 +352,12 @@ CONFIG_STM32_HAVE_ADC1_DMA=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y # CONFIG_STM32_HAVE_CAN2 is not set # CONFIG_STM32_HAVE_DAC1 is not set @@ -716,14 +724,14 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -1030,20 +1038,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=768 # # Examples # -CONFIG_EXAMPLES_ARCHBUTTONS=y -CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 -CONFIG_EXAMPLES_ARCHBUTTONS_MAX=0 -CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 -CONFIG_EXAMPLES_IRQBUTTONS_MAX=0 -CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="BOOT 0" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Button 1" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set diff --git a/configs/sabre-6quad/nsh/defconfig b/configs/sabre-6quad/nsh/defconfig index dfc9ef8d6f..e49adfad3a 100644 --- a/configs/sabre-6quad/nsh/defconfig +++ b/configs/sabre-6quad/nsh/defconfig @@ -685,7 +685,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/sabre-6quad/smp/defconfig b/configs/sabre-6quad/smp/defconfig index 23afd07fe9..1e0d04e2f1 100644 --- a/configs/sabre-6quad/smp/defconfig +++ b/configs/sabre-6quad/smp/defconfig @@ -692,7 +692,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/sam4e-ek/nsh/defconfig b/configs/sam4e-ek/nsh/defconfig index ed3f03c24b..2ef13dd91f 100644 --- a/configs/sam4e-ek/nsh/defconfig +++ b/configs/sam4e-ek/nsh/defconfig @@ -999,7 +999,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/sam4e-ek/nxwm/defconfig b/configs/sam4e-ek/nxwm/defconfig index 3d8dd79bb0..e0f08e426d 100644 --- a/configs/sam4e-ek/nxwm/defconfig +++ b/configs/sam4e-ek/nxwm/defconfig @@ -1171,7 +1171,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/sam4e-ek/usbnsh/defconfig b/configs/sam4e-ek/usbnsh/defconfig index b96a1ca08a..79c11c7385 100644 --- a/configs/sam4e-ek/usbnsh/defconfig +++ b/configs/sam4e-ek/usbnsh/defconfig @@ -1036,7 +1036,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/sama5d4-ek/ipv6/defconfig b/configs/sama5d4-ek/ipv6/defconfig index c60fca0843..dc12843886 100644 --- a/configs/sama5d4-ek/ipv6/defconfig +++ b/configs/sama5d4-ek/ipv6/defconfig @@ -1298,19 +1298,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -CONFIG_EXAMPLES_ARCHBUTTONS=y -CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 -CONFIG_EXAMPLES_ARCHBUTTONS_MAX=0 -CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 -CONFIG_EXAMPLES_IRQBUTTONS_MAX=0 -CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="PB_USER" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Button 1" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/sama5d4-ek/nsh/defconfig b/configs/sama5d4-ek/nsh/defconfig index 446b2d3dfd..6e39bfc312 100644 --- a/configs/sama5d4-ek/nsh/defconfig +++ b/configs/sama5d4-ek/nsh/defconfig @@ -1309,19 +1309,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -CONFIG_EXAMPLES_ARCHBUTTONS=y -CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 -CONFIG_EXAMPLES_ARCHBUTTONS_MAX=0 -CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 -CONFIG_EXAMPLES_IRQBUTTONS_MAX=0 -CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="PB_USER" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Button 1" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/sama5d4-ek/nxwm/defconfig b/configs/sama5d4-ek/nxwm/defconfig index 907dd01ff8..491f250f7b 100644 --- a/configs/sama5d4-ek/nxwm/defconfig +++ b/configs/sama5d4-ek/nxwm/defconfig @@ -1297,19 +1297,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -CONFIG_EXAMPLES_ARCHBUTTONS=y -CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 -CONFIG_EXAMPLES_ARCHBUTTONS_MAX=0 -CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 -CONFIG_EXAMPLES_IRQBUTTONS_MAX=0 -CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="PB_USER" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Button 1" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/same70-xplained/netnsh/defconfig b/configs/same70-xplained/netnsh/defconfig index 70c8117a63..1313e21cb9 100644 --- a/configs/same70-xplained/netnsh/defconfig +++ b/configs/same70-xplained/netnsh/defconfig @@ -1041,19 +1041,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -CONFIG_EXAMPLES_ARCHBUTTONS=y -CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 -CONFIG_EXAMPLES_ARCHBUTTONS_MAX=0 -CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 -CONFIG_EXAMPLES_IRQBUTTONS_MAX=0 -CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="SW0" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Button 1" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/same70-xplained/nsh/defconfig b/configs/same70-xplained/nsh/defconfig index 183961eacf..d43cf6698c 100644 --- a/configs/same70-xplained/nsh/defconfig +++ b/configs/same70-xplained/nsh/defconfig @@ -64,11 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -525,15 +527,15 @@ CONFIG_I2C=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y # CONFIG_SPI_CS_CONTROL is not set -# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set # CONFIG_SPI_BITBANG is not set @@ -860,20 +862,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -CONFIG_EXAMPLES_ARCHBUTTONS=y -CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 -CONFIG_EXAMPLES_ARCHBUTTONS_MAX=0 -CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 -CONFIG_EXAMPLES_IRQBUTTONS_MAX=0 -CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="SW0" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Button 1" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set diff --git a/configs/samv71-xult/mxtxplnd/defconfig b/configs/samv71-xult/mxtxplnd/defconfig index 3ce521bbfb..940bcd430c 100644 --- a/configs/samv71-xult/mxtxplnd/defconfig +++ b/configs/samv71-xult/mxtxplnd/defconfig @@ -64,11 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -526,15 +528,15 @@ CONFIG_I2C=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y # CONFIG_SPI_CS_CONTROL is not set -# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set # CONFIG_SPI_BITBANG is not set @@ -990,20 +992,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -CONFIG_EXAMPLES_ARCHBUTTONS=y -CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 -CONFIG_EXAMPLES_ARCHBUTTONS_MAX=1 -CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 -CONFIG_EXAMPLES_IRQBUTTONS_MAX=1 -CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="SW0" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="SW1" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set diff --git a/configs/samv71-xult/netnsh/defconfig b/configs/samv71-xult/netnsh/defconfig index 4cdc68ea28..54877ac7e1 100644 --- a/configs/samv71-xult/netnsh/defconfig +++ b/configs/samv71-xult/netnsh/defconfig @@ -1045,19 +1045,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -CONFIG_EXAMPLES_ARCHBUTTONS=y -CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 -CONFIG_EXAMPLES_ARCHBUTTONS_MAX=1 -CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 -CONFIG_EXAMPLES_IRQBUTTONS_MAX=1 -CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="SW0" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="SW1" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/samv71-xult/nsh/defconfig b/configs/samv71-xult/nsh/defconfig index a35e82a9b8..c376395c8b 100644 --- a/configs/samv71-xult/nsh/defconfig +++ b/configs/samv71-xult/nsh/defconfig @@ -64,6 +64,7 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set @@ -864,19 +865,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -CONFIG_EXAMPLES_ARCHBUTTONS=y -CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 -CONFIG_EXAMPLES_ARCHBUTTONS_MAX=1 -CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 -CONFIG_EXAMPLES_IRQBUTTONS_MAX=1 -CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="SW0" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="SW1" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Button 2" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Button 3" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Button 4" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/samv71-xult/vnc/defconfig b/configs/samv71-xult/vnc/defconfig index c956688f1c..2e7a83721c 100644 --- a/configs/samv71-xult/vnc/defconfig +++ b/configs/samv71-xult/vnc/defconfig @@ -1137,7 +1137,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/samv71-xult/vnxwm/defconfig b/configs/samv71-xult/vnxwm/defconfig index c5f417361a..af19392428 100644 --- a/configs/samv71-xult/vnxwm/defconfig +++ b/configs/samv71-xult/vnxwm/defconfig @@ -1168,7 +1168,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/stm3210e-eval/pm/defconfig b/configs/stm3210e-eval/pm/defconfig index 957c9a57a1..86003dfefc 100644 --- a/configs/stm3210e-eval/pm/defconfig +++ b/configs/stm3210e-eval/pm/defconfig @@ -1133,7 +1133,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set diff --git a/configs/stm32butterfly2/nsh/defconfig b/configs/stm32butterfly2/nsh/defconfig index 76318ef95c..08a3f805de 100644 --- a/configs/stm32butterfly2/nsh/defconfig +++ b/configs/stm32butterfly2/nsh/defconfig @@ -61,11 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -354,6 +356,12 @@ CONFIG_STM32_HAVE_ADC2=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -589,7 +597,7 @@ CONFIG_CLOCK_MONOTONIC=y CONFIG_ARCH_HAVE_TIMEKEEPING=y # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=1970 -CONFIG_START_MONTH=0 +CONFIG_START_MONTH=1 CONFIG_START_DAY=1 CONFIG_MAX_WDOGPARMS=2 CONFIG_PREALLOC_WDOGS=8 @@ -702,14 +710,14 @@ CONFIG_RAMDISK=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set CONFIG_SPI_CALLBACK=y # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -1024,10 +1032,8 @@ CONFIG_EXAMPLES_ADC=y CONFIG_EXAMPLES_ADC_DEVPATH="/dev/adc0" CONFIG_EXAMPLES_ADC_GROUPSIZE=4 CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_EXAMPLES_ARCHBUTTONS=y -CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 -CONFIG_EXAMPLES_ARCHBUTTONS_MAX=4 # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set diff --git a/configs/stm32butterfly2/nshnet/defconfig b/configs/stm32butterfly2/nshnet/defconfig index fe385454a6..41bdf15b31 100644 --- a/configs/stm32butterfly2/nshnet/defconfig +++ b/configs/stm32butterfly2/nshnet/defconfig @@ -1212,9 +1212,6 @@ CONFIG_EXAMPLES_ADC=y CONFIG_EXAMPLES_ADC_DEVPATH="/dev/adc0" CONFIG_EXAMPLES_ADC_GROUPSIZE=4 CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_EXAMPLES_ARCHBUTTONS=y -CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 -CONFIG_EXAMPLES_ARCHBUTTONS_MAX=4 # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/stm32butterfly2/nshusbdev/defconfig b/configs/stm32butterfly2/nshusbdev/defconfig index e9ca79f09d..63dc8d5a1d 100644 --- a/configs/stm32butterfly2/nshusbdev/defconfig +++ b/configs/stm32butterfly2/nshusbdev/defconfig @@ -61,11 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -351,6 +353,12 @@ CONFIG_STM32_HAVE_ADC2=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -582,7 +590,7 @@ CONFIG_CLOCK_MONOTONIC=y CONFIG_ARCH_HAVE_TIMEKEEPING=y # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=1970 -CONFIG_START_MONTH=0 +CONFIG_START_MONTH=1 CONFIG_START_DAY=1 CONFIG_MAX_WDOGPARMS=2 CONFIG_PREALLOC_WDOGS=8 @@ -695,14 +703,14 @@ CONFIG_RAMDISK=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set CONFIG_SPI_CALLBACK=y # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -1033,10 +1041,8 @@ CONFIG_EXAMPLES_ADC=y CONFIG_EXAMPLES_ADC_DEVPATH="/dev/adc0" CONFIG_EXAMPLES_ADC_GROUPSIZE=4 CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_EXAMPLES_ARCHBUTTONS=y -CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 -CONFIG_EXAMPLES_ARCHBUTTONS_MAX=4 # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set diff --git a/configs/stm32butterfly2/nshusbhost/defconfig b/configs/stm32butterfly2/nshusbhost/defconfig index 76318ef95c..08a3f805de 100644 --- a/configs/stm32butterfly2/nshusbhost/defconfig +++ b/configs/stm32butterfly2/nshusbhost/defconfig @@ -61,11 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -354,6 +356,12 @@ CONFIG_STM32_HAVE_ADC2=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -589,7 +597,7 @@ CONFIG_CLOCK_MONOTONIC=y CONFIG_ARCH_HAVE_TIMEKEEPING=y # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=1970 -CONFIG_START_MONTH=0 +CONFIG_START_MONTH=1 CONFIG_START_DAY=1 CONFIG_MAX_WDOGPARMS=2 CONFIG_PREALLOC_WDOGS=8 @@ -702,14 +710,14 @@ CONFIG_RAMDISK=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set CONFIG_SPI_CALLBACK=y # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -1024,10 +1032,8 @@ CONFIG_EXAMPLES_ADC=y CONFIG_EXAMPLES_ADC_DEVPATH="/dev/adc0" CONFIG_EXAMPLES_ADC_GROUPSIZE=4 CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_EXAMPLES_ARCHBUTTONS=y -CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 -CONFIG_EXAMPLES_ARCHBUTTONS_MAX=4 # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set diff --git a/configs/stm32f103-minimum/buttons/defconfig b/configs/stm32f103-minimum/buttons/defconfig index b9acf84dce..37ad971e05 100644 --- a/configs/stm32f103-minimum/buttons/defconfig +++ b/configs/stm32f103-minimum/buttons/defconfig @@ -937,7 +937,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set CONFIG_EXAMPLES_BUTTONS=y CONFIG_EXAMPLES_BUTTONS_PRIORITY=100 CONFIG_EXAMPLES_BUTTONS_STACKSIZE=2048 diff --git a/configs/stm32f4discovery/ipv6/defconfig b/configs/stm32f4discovery/ipv6/defconfig index 3b01309477..9a828de914 100644 --- a/configs/stm32f4discovery/ipv6/defconfig +++ b/configs/stm32f4discovery/ipv6/defconfig @@ -1216,7 +1216,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/stm32f4discovery/netnsh/defconfig b/configs/stm32f4discovery/netnsh/defconfig index 2960a94caf..61d4db2c5b 100644 --- a/configs/stm32f4discovery/netnsh/defconfig +++ b/configs/stm32f4discovery/netnsh/defconfig @@ -1227,7 +1227,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/stm32l476vg-disco/nsh/defconfig b/configs/stm32l476vg-disco/nsh/defconfig index 25cfb5102c..4bebf44d35 100644 --- a/configs/stm32l476vg-disco/nsh/defconfig +++ b/configs/stm32l476vg-disco/nsh/defconfig @@ -61,11 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -244,6 +246,8 @@ CONFIG_STM32L4_PWR=y # CONFIG_STM32L4_USART1 is not set CONFIG_STM32L4_USART2=y # CONFIG_STM32L4_USART3 is not set +# CONFIG_STM32L4_UART4 is not set +# CONFIG_STM32L4_UART5 is not set # CONFIG_STM32L4_I2C1 is not set # CONFIG_STM32L4_I2C2 is not set # CONFIG_STM32L4_I2C3 is not set @@ -293,8 +297,8 @@ CONFIG_STM32L4_SAI1PLL=y # CONFIG_STM32L4_ONESHOT is not set # CONFIG_STM32L4_FREERUN is not set CONFIG_STM32L4_HAVE_USART3=y -# CONFIG_STM32L4_HAVE_USART4 is not set -# CONFIG_STM32L4_HAVE_USART5 is not set +CONFIG_STM32L4_HAVE_UART4=y +CONFIG_STM32L4_HAVE_UART5=y # # U[S]ART Configuration @@ -519,14 +523,14 @@ CONFIG_DEV_LOOP=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -852,20 +856,8 @@ CONFIG_EXAMPLES_ALARM_PRIORITY=100 CONFIG_EXAMPLES_ALARM_STACKSIZE=2048 CONFIG_EXAMPLES_ALARM_DEVPATH="/dev/rtc0" CONFIG_EXAMPLES_ALARM_SIGNO=1 -CONFIG_EXAMPLES_ARCHBUTTONS=y -CONFIG_EXAMPLES_ARCHBUTTONS_MIN=0 -CONFIG_EXAMPLES_ARCHBUTTONS_MAX=4 -CONFIG_EXAMPLES_IRQBUTTONS_MIN=0 -CONFIG_EXAMPLES_IRQBUTTONS_MAX=4 -CONFIG_EXAMPLES_ARCHBUTTONS_NAME0="Center" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME1="Left" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME2="Down" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME3="Right" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME4="Up" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME5="Button 5" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME6="Button 6" -CONFIG_EXAMPLES_ARCHBUTTONS_NAME7="Button 7" # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set diff --git a/configs/tm4c1294-launchpad/ipv6/defconfig b/configs/tm4c1294-launchpad/ipv6/defconfig index 4de7a634ef..25fc93d965 100644 --- a/configs/tm4c1294-launchpad/ipv6/defconfig +++ b/configs/tm4c1294-launchpad/ipv6/defconfig @@ -882,7 +882,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/viewtool-stm32f107/highpri/defconfig b/configs/viewtool-stm32f107/highpri/defconfig index 81e2ca9c17..ece24f6b88 100644 --- a/configs/viewtool-stm32f107/highpri/defconfig +++ b/configs/viewtool-stm32f107/highpri/defconfig @@ -942,7 +942,6 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set diff --git a/configs/viewtool-stm32f107/nsh/defconfig b/configs/viewtool-stm32f107/nsh/defconfig index 1baa61b9fc..243f7bfee4 100644 --- a/configs/viewtool-stm32f107/nsh/defconfig +++ b/configs/viewtool-stm32f107/nsh/defconfig @@ -945,7 +945,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # -# CONFIG_EXAMPLES_ARCHBUTTONS is not set # CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set -- GitLab From a3112b231ca7d65b08e0758c400e3edb739b0a19 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 22 Nov 2016 07:49:04 -0600 Subject: [PATCH 483/734] nucleo-l476rg: Add better selection of timer. --- configs/nucleo-l476rg/Kconfig | 5 -- configs/nucleo-l476rg/src/stm32_appinit.c | 72 ++++++++++++++++++++++- 2 files changed, 71 insertions(+), 6 deletions(-) diff --git a/configs/nucleo-l476rg/Kconfig b/configs/nucleo-l476rg/Kconfig index 8edd703e42..7361b3f490 100644 --- a/configs/nucleo-l476rg/Kconfig +++ b/configs/nucleo-l476rg/Kconfig @@ -5,11 +5,6 @@ if ARCH_BOARD_NUCLEO_L476RG -config NUCLEO_L476RG_QETIMER - int "Timer to use with QE encoder" - default 3 - depends on QENCODER - config NUCLEO_L476RG_AJOY_MINBUTTONS bool "Minimal Joystick Buttons" default n if !STM32_USART1 diff --git a/configs/nucleo-l476rg/src/stm32_appinit.c b/configs/nucleo-l476rg/src/stm32_appinit.c index ceeca0eff3..ab2665bc73 100644 --- a/configs/nucleo-l476rg/src/stm32_appinit.c +++ b/configs/nucleo-l476rg/src/stm32_appinit.c @@ -111,6 +111,10 @@ int board_app_initialize(uintptr_t arg) { #ifdef HAVE_RTC_DRIVER FAR struct rtc_lowerhalf_s *rtclower; +#endif +#ifdef CONFIG_QENCODER + int index; + char buf[9]; #endif int ret; @@ -219,9 +223,50 @@ int board_app_initialize(uintptr_t arg) #endif #ifdef CONFIG_QENCODER + /* Initialize and register the qencoder driver */ - ret = stm32l4_qencoder_initialize("/dev/qe0", CONFIG_NUCLEO_L476RG_QETIMER); + index = 0; + +#ifdef CONFIG_STM32L4_TIM1_QE + sprintf(buf, "/dev/qe%d", index++); + ret = stm32l4_qencoder_initialize(buf, 1); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_STM32L4_TIM2_QE + sprintf(buf, "/dev/qe%d", index++); + ret = stm32l4_qencoder_initialize(buf, 2); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_STM32L4_TIM3_QE + sprintf(buf, "/dev/qe%d", index++); + ret = stm32l4_qencoder_initialize(buf, 3); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_STM32L4_TIM4_QE + sprintf(buf, "/dev/qe%d", index++); + ret = stm32l4_qencoder_initialize(buf, 4); if (ret != OK) { syslog(LOG_ERR, @@ -231,6 +276,31 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_STM32L4_TIM5_QE + sprintf(buf, "/dev/qe%d", index++); + ret = stm32l4_qencoder_initialize(buf, 5); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_STM32L4_TIM8_QE + sprintf(buf, "/dev/qe%d", index++); + ret = stm32l4_qencoder_initialize(buf, 8); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#endif return OK; } -- GitLab From ec586ab3509c1d8f524a3ded2867ae45b8b20786 Mon Sep 17 00:00:00 2001 From: Sebastien Lorquet Date: Tue, 22 Nov 2016 07:57:21 -0600 Subject: [PATCH 484/734] implementation of dumpgpio for stm32l4, was required for pwm debug. --- arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h | 1 + arch/arm/src/stm32l4/stm32l4_dumpgpio.c | 153 ++++++++++++++++++++ 2 files changed, 154 insertions(+) diff --git a/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h b/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h index 0b184230b4..c56e59c811 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h +++ b/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h @@ -381,6 +381,7 @@ /* AHB2 peripheral reset register */ +#define RCC_AHB1ENR_GPIOEN(port) (1 << port) #define RCC_AHB2RSTR_GPIOARST (1 << 0) /* Bit 0: IO port A reset */ #define RCC_AHB2RSTR_GPIOBRST (1 << 1) /* Bit 1: IO port B reset */ #define RCC_AHB2RSTR_GPIOCRST (1 << 2) /* Bit 2: IO port C reset */ diff --git a/arch/arm/src/stm32l4/stm32l4_dumpgpio.c b/arch/arm/src/stm32l4/stm32l4_dumpgpio.c index e69de29bb2..c0eabb206c 100644 --- a/arch/arm/src/stm32l4/stm32l4_dumpgpio.c +++ b/arch/arm/src/stm32l4/stm32l4_dumpgpio.c @@ -0,0 +1,153 @@ +/**************************************************************************** + * arch/arm/src/stm32l4/stm32l4_dumpgpio.c + * + * Copyright (C) 2016 Sebastien Lorquet. All rights reserved. + * Author: Sebastien Lorquet + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Output debug info even if debug output is not selected. */ + +#undef CONFIG_DEBUG_INFO +#define CONFIG_DEBUG_INFO 1 + +#include +#include + +#include + +#include "up_arch.h" +#include "chip.h" +#include "stm32l4_gpio.h" +#include "stm32l4_rcc.h" + +#ifdef CONFIG_DEBUG_FEATURES + +/**************************************************************************** + * Private Data + ****************************************************************************/ +/* Port letters for prettier debug output */ + +static const char g_portchar[STM32L4_NPORTS] = +{ +#if STM32L4_NPORTS > 11 +# error "Additional support required for this number of GPIOs" +#elif STM32L4_NPORTS > 10 + 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K' +#elif STM32L4_NPORTS > 9 + 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J' +#elif STM32L4_NPORTS > 8 + 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I' +#elif STM32L4_NPORTS > 7 + 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' +#elif STM32L4_NPORTS > 6 + 'A', 'B', 'C', 'D', 'E', 'F', 'G' +#elif STM32L4_NPORTS > 5 + 'A', 'B', 'C', 'D', 'E', 'F' +#elif STM32L4_NPORTS > 4 + 'A', 'B', 'C', 'D', 'E' +#elif STM32L4_NPORTS > 3 + 'A', 'B', 'C', 'D' +#elif STM32L4_NPORTS > 2 + 'A', 'B', 'C' +#elif STM32L4_NPORTS > 1 + 'A', 'B' +#elif STM32L4_NPORTS > 0 + 'A' +#else +# error "Bad number of GPIOs" +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: stm32l4_dumpgpio + * + * Description: + * Dump all GPIO registers associated with the provided base address + * + ****************************************************************************/ + +int stm32l4_dumpgpio(uint32_t pinset, const char *msg) +{ + irqstate_t flags; + uint32_t base; + unsigned int port; + + /* Get the base address associated with the GPIO port */ + + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + base = g_gpiobase[port]; + + /* The following requires exclusive access to the GPIO registers */ + + flags = enter_critical_section(); + + DEBUGASSERT(port < STM32L4_NPORTS); + + _info("GPIO%c pinset: %08x base: %08x -- %s\n", + g_portchar[port], pinset, base, msg); + + if ((getreg32(STM32L4_RCC_AHB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0) + { + _info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", + getreg32(base + STM32L4_GPIO_MODER_OFFSET), + getreg32(base + STM32L4_GPIO_OTYPER_OFFSET), + getreg32(base + STM32L4_GPIO_OSPEED_OFFSET), + getreg32(base + STM32L4_GPIO_PUPDR_OFFSET)); + _info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n", + getreg32(base + STM32L4_GPIO_IDR_OFFSET), + getreg32(base + STM32L4_GPIO_ODR_OFFSET), + getreg32(base + STM32L4_GPIO_BSRR_OFFSET), + getreg32(base + STM32L4_GPIO_LCKR_OFFSET)); + _info(" AFRH: %08x AFRL: %08x\n", + getreg32(base + STM32L4_GPIO_AFRH_OFFSET), + getreg32(base + STM32L4_GPIO_AFRL_OFFSET)); + } + else + { + _info(" GPIO%c not enabled: AHB1ENR: %08x\n", + g_portchar[port], getreg32(STM32L4_RCC_AHB1ENR)); + } + + leave_critical_section(flags); + return OK; +} + +#endif /* CONFIG_DEBUG_FEATURES */ -- GitLab From b39556f625122d6565457860891d314c895adefd Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 22 Nov 2016 09:03:50 -0600 Subject: [PATCH 485/734] Update READMEs --- configs/hymini-stm32v/README.txt | 1 - configs/open1788/README.txt | 26 --------------------- configs/same70-xplained/README.txt | 37 ++++-------------------------- configs/samv71-xult/README.txt | 37 ++++-------------------------- 4 files changed, 8 insertions(+), 93 deletions(-) diff --git a/configs/hymini-stm32v/README.txt b/configs/hymini-stm32v/README.txt index 2a804a43a6..7fec3b1562 100644 --- a/configs/hymini-stm32v/README.txt +++ b/configs/hymini-stm32v/README.txt @@ -591,7 +591,6 @@ Where is one of the following: Built-in None apps/examples/nx Apps apps/examples/nxhello apps/system/usbmsc (4) - apps/examples/buttons apps/examples/nximage =========== ======================= ================================ diff --git a/configs/open1788/README.txt b/configs/open1788/README.txt index b7419b33aa..b8604d6346 100644 --- a/configs/open1788/README.txt +++ b/configs/open1788/README.txt @@ -467,32 +467,6 @@ CONFIGURATION CONFIG_DEBUG_INFO=y CONFIG_DEBUG_INPUT=y - 7. The button test (apps/examples/buttons) can be built-in by adding - the following options. See apps/examples/README.txt for further - information about the button test. - - System Type: - CONFIG_LPC17_GPIOIRQ=y - - Board Selection: - CONFIG_ARCH_BUTTONS=y - CONFIG_ARCH_IRQBUTTONS=y - - Application Configuration: - CONFIG_EXAMPLES_BUTTONS=y - CONFIG_EXAMPLES_BUTTONS_MIN=0 - CONFIG_EXAMPLES_BUTTONS_MAX=7 - CONFIG_EXAMPLES_IRQBUTTONS_MIN=1 - CONFIG_EXAMPLES_IRQBUTTONS_MAX=7 - CONFIG_EXAMPLES_BUTTONS_NAME0="USER1" - CONFIG_EXAMPLES_BUTTONS_NAME1="USER2" - CONFIG_EXAMPLES_BUTTONS_NAME2="USER3" - CONFIG_EXAMPLES_BUTTONS_NAME3="JOYSTICK_A" - CONFIG_EXAMPLES_BUTTONS_NAME4="JOYSTICK_B" - CONFIG_EXAMPLES_BUTTONS_NAME5="JOYSTICK_C" - CONFIG_EXAMPLES_BUTTONS_NAME6="JOYSTICK_D" - CONFIG_EXAMPLES_BUTTONS_NAME7="JOYSTICK_CTR" - nxlines ------- Configures the graphics example located at examples/nsh. This diff --git a/configs/same70-xplained/README.txt b/configs/same70-xplained/README.txt index 6f84f024fa..7d31d20e9d 100644 --- a/configs/same70-xplained/README.txt +++ b/configs/same70-xplained/README.txt @@ -1363,36 +1363,7 @@ Configuration sub-directories RAMTest: Address-in-address test: 70000000 2097152 nsh> - 5. The button test at apps/examples/buttons is included in the - configuration. This configuration illustrates (1) use of the buttons - on the evaluation board, and (2) the use of PIO interrupts. Example - usage: - - NuttShell (NSH) NuttX-7.8 - nsh> help - help usage: help [-v] [] - ... - Builtin Apps: - buttons - nsh> buttons 3 - maxbuttons: 3 - Attached handler at 4078f7 to button 0 [SW0], oldhandler:0 - Attached handler at 4078e9 to button 1 [SW1], oldhandler:0 - IRQ:125 Button 1:SW1 SET:00: - SW1 released - IRQ:125 Button 1:SW1 SET:02: - SW1 depressed - IRQ:125 Button 1:SW1 SET:00: - SW1 released - IRQ:90 Button 0:SW0 SET:01: - SW0 depressed - IRQ:90 Button 0:SW0 SET:00: - SW0 released - IRQ:125 Button 1:SW1 SET:02: - SW1 depressed - nsh> - - 6. TWI/I2C + 5. TWI/I2C TWIHS0 is enabled in this configuration. The SAM E70 Xplained supports one device on the one on-board I2C device on the TWIHS0 bus: @@ -1464,11 +1435,11 @@ Configuration sub-directories 0x5f are the addresses of the AT24 EEPROM (I am not sure what the other address, 0x37, is as this writing). - 7. TWIHS0 is also used to support 256 byte non-volatile storage for + 6. TWIHS0 is also used to support 256 byte non-volatile storage for configuration data using the MTD configuration as described above under the heading, "MTD Configuration Data". - 8. Support for HSMCI is built-in by default. The SAME70-XPLD provides + 7. Support for HSMCI is built-in by default. The SAME70-XPLD provides one full-size SD memory card slot. Refer to the section entitled "SD card" for configuration-related information. @@ -1477,7 +1448,7 @@ Configuration sub-directories The auto-mounter is not enabled. See the section above entitled "Auto-Mounter". - 9. Performance-related Configuration settings: + 8. Performance-related Configuration settings: CONFIG_ARMV7M_ICACHE=y : Instruction cache is enabled CONFIG_ARMV7M_DCACHE=y : Data cache is enabled diff --git a/configs/samv71-xult/README.txt b/configs/samv71-xult/README.txt index d51f23dfe1..f84223d5b8 100644 --- a/configs/samv71-xult/README.txt +++ b/configs/samv71-xult/README.txt @@ -2053,36 +2053,7 @@ Configuration sub-directories RAMTest: Address-in-address test: 70000000 2097152 nsh> - 5. The button test at apps/examples/buttons is included in the - configuration. This configuration illustrates (1) use of the buttons - on the evaluation board, and (2) the use of PIO interrupts. Example - usage: - - NuttShell (NSH) NuttX-7.8 - nsh> help - help usage: help [-v] [] - ... - Builtin Apps: - buttons - nsh> buttons 3 - maxbuttons: 3 - Attached handler at 4078f7 to button 0 [SW0], oldhandler:0 - Attached handler at 4078e9 to button 1 [SW1], oldhandler:0 - IRQ:125 Button 1:SW1 SET:00: - SW1 released - IRQ:125 Button 1:SW1 SET:02: - SW1 depressed - IRQ:125 Button 1:SW1 SET:00: - SW1 released - IRQ:90 Button 0:SW0 SET:01: - SW0 depressed - IRQ:90 Button 0:SW0 SET:00: - SW0 released - IRQ:125 Button 1:SW1 SET:02: - SW1 depressed - nsh> - - 6. TWI/I2C + 5. TWI/I2C TWIHS0 is enabled in this configuration. The SAM V71 Xplained Ultra supports two devices on the one on-board I2C device on the TWIHS0 bus: @@ -2159,11 +2130,11 @@ Configuration sub-directories the AT2 EEPROM (I am not sure what the other address, 0x37, is as this writing). - 7. TWIHS0 is also used to support 256 byte non-volatile storage for + 6. TWIHS0 is also used to support 256 byte non-volatile storage for configuration data using the MTD configuration as described above under the heading, "MTD Configuration Data". - 8. Support for HSMCI is built-in by default. The SAMV71-XULT provides + 7. Support for HSMCI is built-in by default. The SAMV71-XULT provides one full-size SD memory card slot. Refer to the section entitled "SD card" for configuration-related information. @@ -2172,7 +2143,7 @@ Configuration sub-directories The auto-mounter is not enabled. See the section above entitled "Auto-Mounter". - 9. Performance-related Configuration settings: + 8. Performance-related Configuration settings: CONFIG_ARMV7M_ICACHE=y : Instruction cache is enabled CONFIG_ARMV7M_DCACHE=y : Data cache is enabled -- GitLab From bac7153609dd8e9c7140fc24fb1a7957525aa150 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 22 Nov 2016 11:34:16 -0600 Subject: [PATCH 486/734] SMP: Add logic to avoid a deadlock condition when CPU1 is hung waiting for g_cpu_irqlock and CPU0 is waitin for g_cpu_paused --- TODO | 39 +---------- arch/arm/src/armv7-a/arm_cpupause.c | 100 +++++++++++++++++++++++++--- arch/sim/src/up_internal.h | 19 ++++++ arch/sim/src/up_simsmp.c | 33 ++++++--- arch/sim/src/up_smpsignal.c | 62 ++++++++++++----- include/nuttx/arch.h | 50 ++++++++++++++ include/nuttx/spinlock.h | 22 +++++- sched/irq/irq_csection.c | 77 ++++++++++++++++++++- sched/semaphore/spinlock.c | 16 ----- sched/task/task_restart.c | 5 +- 10 files changed, 328 insertions(+), 95 deletions(-) diff --git a/TODO b/TODO index 77fb109fe4..d50c610998 100644 --- a/TODO +++ b/TODO @@ -10,7 +10,7 @@ issues related to each board port. nuttx/: (13) Task/Scheduler (sched/) - (2) SMP + (1) SMP (1) Memory Management (mm/) (1) Power Management (drivers/pm) (3) Signals (sched/signal, arch/) @@ -336,43 +336,6 @@ o SMP Priority: High. spinlocks, and hence SMP, will not work on such systems without this change. - Title: DEADLOCK SCENARIO WITH up_cpu_pause(). - Description: I think there is a possibilty for a hang in up_cpu_pause(). - Suppose this situation: - - - CPU1 is in a critical section and has the g_cpu_irqlock - spinlock. - - CPU0 takes an interrupt and attempts to enter the critical - section. It spins waiting on g_cpu_irqlock with interrupt - disabled. - - CPU1 calls up_cpu_pause() to pause operation on CPU1. This - will issue an inter-CPU interrupt to CPU0 - - But interrupts are disabled. What will happen? I think - that this is a deadlock: Interrupts will stay disabled on - CPU0 because it is spinning in the interrupt handler; - up_cpu_pause() will hang becuase the inter-CPU interrupt - is pending. - - Are inter-CPU interrupts maskable in the same way as other - interrupts? If the are not-maskable, then we must also handle - them as nested interrupts in some fashion. - - A work-around might be to check the state of other-CPU - interrupt handler inside the spin loop of up_cpu_pause(). - Having the other CPU spinning and waiting for up_cpu_pause() - provided that (1) the pending interrupt can be cleared, and - (2) leave_critical_section() is not called prior to the point - where up_cpu_resume() is called, and (3) up_cpu_resume() is - smart enough to know that it should not attempt to resume a - non-paused CPU. - - This would require some kind of information about each - interrupt handler: In an interrupt, waiting for spinlock, - have spinlock, etc. - - Status: Open - Priority: Medium-High. I don't know for certain that this is a problem but it seems like it could - o Memory Management (mm/) ^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/arch/arm/src/armv7-a/arm_cpupause.c b/arch/arm/src/armv7-a/arm_cpupause.c index 7689598b55..4abfac25b1 100644 --- a/arch/arm/src/armv7-a/arm_cpupause.c +++ b/arch/arm/src/armv7-a/arm_cpupause.c @@ -55,6 +55,20 @@ * Private Data ****************************************************************************/ +/* These spinlocks are used in the SMP configuration in order to implement + * up_cpu_pause(). The protocol for CPUn to pause CPUm is as follows + * + * 1. The up_cpu_pause() implementation on CPUn locks both g_cpu_wait[m] + * and g_cpu_paused[m]. CPUn then waits spinning on g_cpu_wait[m]. + * 2. CPUm receives the interrupt it (1) unlocks g_cpu_paused[m] and + * (2) locks g_cpu_wait[m]. The first unblocks CPUn and the second + * blocks CPUm in the interrupt handler. + * + * When CPUm resumes, CPUn unlocks g_cpu_wait[m] and the interrupt handler + * on CPUm continues. CPUm must, of course, also then unlock g_cpu_wait[m] + * so that it will be ready for the next pause operation. + */ + static volatile spinlock_t g_cpu_wait[CONFIG_SMP_NCPUS]; static volatile spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS]; @@ -63,10 +77,36 @@ static volatile spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS]; ****************************************************************************/ /**************************************************************************** - * Name: arm_pause_handler + * Name: up_cpu_pausereq * * Description: - * This is the handler for SGI2. It performs the following operations: + * Return true if a pause request is pending for this CPU. + * + * Input Parameters: + * cpu - The index of the CPU to be queried + * + * Returned Value: + * true = a pause request is pending. + * false = no pasue request is pending. + * + ****************************************************************************/ + +bool up_cpu_pausereq(int cpu) +{ + return spin_islocked(&g_cpu_paused[cpu]); +} + +/**************************************************************************** + * Name: up_cpu_paused + * + * Description: + * Handle a pause request from another CPU. Normally, this logic is + * executed from interrupt handling logic within the architecture-specific + * However, it is sometimes necessary necessary to perform the pending + * pause operation in other contexts where the interrupt cannot be taken + * in order to avoid deadlocks. + * + * This function performs the following operations: * * 1. It saves the current task state at the head of the current assigned * task list. @@ -75,24 +115,24 @@ static volatile spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS]; * head of the ready to run list. * * Input Parameters: - * Standard interrupt handling + * cpu - The index of the CPU to be paused * * Returned Value: - * Zero on success; a negated errno value on failure. + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. * ****************************************************************************/ -int arm_pause_handler(int irq, FAR void *context) +int up_cpu_paused(int cpu) { FAR struct tcb_s *tcb = this_task(); - int cpu = up_cpu_index(); /* Update scheduler parameters */ sched_suspend_scheduler(tcb); - /* Save the current context at CURRENT_REGS into the TCB at the head of the - * assigned task list for this CPU. + /* Save the current context at CURRENT_REGS into the TCB at the head + * of the assigned task list for this CPU. */ up_savestate(tcb->xcp.regs); @@ -112,12 +152,50 @@ int arm_pause_handler(int irq, FAR void *context) sched_resume_scheduler(tcb); - /* Then switch contexts. Any necessary address environment changes will - * be made when the interrupt returns. + /* Then switch contexts. Any necessary address environment changes + * will be made when the interrupt returns. */ up_restorestate(tcb->xcp.regs); spin_unlock(&g_cpu_wait[cpu]); + + return OK; +} + +/**************************************************************************** + * Name: arm_pause_handler + * + * Description: + * This is the handler for SGI2. It performs the following operations: + * + * 1. It saves the current task state at the head of the current assigned + * task list. + * 2. It waits on a spinlock, then + * 3. Returns from interrupt, restoring the state of the new task at the + * head of the ready to run list. + * + * Input Parameters: + * Standard interrupt handling + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +int arm_pause_handler(int irq, FAR void *context) +{ + int cpu = this_cpu(); + + /* Check for false alarms. Such false could occur as a consequence of + * some deadlock breaking logic that might have already serviced the SG2 + * interrupt by calling up_cpu_paused. + */ + + if (spin_islocked(&g_cpu_paused[cpu])) + { + return up_cpu_paused(cpu); + } + return OK; } @@ -134,7 +212,7 @@ int arm_pause_handler(int irq, FAR void *context) * CPU. * * Input Parameters: - * cpu - The index of the CPU to be stopped/ + * cpu - The index of the CPU to be stopped * * Returned Value: * Zero on success; a negated errno value on failure. diff --git a/arch/sim/src/up_internal.h b/arch/sim/src/up_internal.h index 658ec0539b..ac0a2269ab 100644 --- a/arch/sim/src/up_internal.h +++ b/arch/sim/src/up_internal.h @@ -199,6 +199,25 @@ extern volatile int g_eventloop; extern volatile int g_uart_data_available; #endif +#ifdef CONFIG_SMP +/* These spinlocks are used in the SMP configuration in order to implement + * up_cpu_pause(). The protocol for CPUn to pause CPUm is as follows + * + * 1. The up_cpu_pause() implementation on CPUn locks both g_cpu_wait[m] + * and g_cpu_paused[m]. CPUn then waits spinning on g_cpu_wait[m]. + * 2. CPUm receives the interrupt it (1) unlocks g_cpu_paused[m] and + * (2) locks g_cpu_wait[m]. The first unblocks CPUn and the second + * blocks CPUm in the interrupt handler. + * + * When CPUm resumes, CPUn unlocks g_cpu_wait[m] and the interrupt handler + * on CPUm continues. CPUm must, of course, also then unlock g_cpu_wait[m] + * so that it will be ready for the next pause operation. + */ + +volatile spinlock_t g_cpu_wait[CONFIG_SMP_NCPUS]; +volatile spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS]; +#endif + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ diff --git a/arch/sim/src/up_simsmp.c b/arch/sim/src/up_simsmp.c index 7ff5cdb6d0..5b24f6015c 100644 --- a/arch/sim/src/up_simsmp.c +++ b/arch/sim/src/up_simsmp.c @@ -78,16 +78,30 @@ struct sim_cpuinfo_s static pthread_key_t g_cpukey; static pthread_t g_sim_cputhread[CONFIG_SMP_NCPUS]; -static volatile unsigned char g_sim_cpupaused[CONFIG_SMP_NCPUS]; -static volatile spinlock_t g_sim_cpuwait[CONFIG_SMP_NCPUS]; + +/* These spinlocks are used in the SMP configuration in order to implement + * up_cpu_pause(). The protocol for CPUn to pause CPUm is as follows + * + * 1. The up_cpu_pause() implementation on CPUn locks both g_cpu_wait[m] + * and g_cpu_paused[m]. CPUn then waits spinning on g_cpu_wait[m]. + * 2. CPUm receives the interrupt it (1) unlocks g_cpu_paused[m] and + * (2) locks g_cpu_wait[m]. The first unblocks CPUn and the second + * blocks CPUm in the interrupt handler. + * + * When CPUm resumes, CPUn unlocks g_cpu_wait[m] and the interrupt handler + * on CPUm continues. CPUm must, of course, also then unlock g_cpu_wait[m] + * so that it will be ready for the next pause operation. + */ + +volatile spinlock_t g_cpu_wait[CONFIG_SMP_NCPUS]; +volatile spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS]; /**************************************************************************** * NuttX domain function prototypes ****************************************************************************/ void os_start(void) __attribute__ ((noreturn)); -void sim_cpu_pause(int cpu, volatile spinlock_t *wait, - volatile unsigned char *paused); +void up_cpu_paused(int cpu); void sim_smp_hook(void); /**************************************************************************** @@ -222,9 +236,7 @@ static void sim_handle_signal(int signo, siginfo_t *info, void *context) { int cpu = (int)((uintptr_t)pthread_getspecific(g_cpukey)); - /* We need to perform the actual tasking operations in the NuttX domain */ - - sim_cpu_pause(cpu, &g_sim_cpuwait[cpu], &g_sim_cpupaused[cpu]); + (void)up_cpu_paused(cpu); } /**************************************************************************** @@ -446,7 +458,8 @@ int up_cpu_pause(int cpu) { /* Take the spinlock that will prevent the CPU thread from running */ - g_sim_cpuwait[cpu] = SP_LOCKED; + g_cpu_wait[cpu] = SP_LOCKED; + g_cpu_paused[cpu] = SP_LOCKED; /* Signal the CPU thread */ @@ -454,7 +467,7 @@ int up_cpu_pause(int cpu) /* Spin, waiting for the thread to pause */ - while (!g_sim_cpupaused[cpu]) + while (g_cpu_paused[cpu] != 0) { pthread_yield(); } @@ -485,6 +498,6 @@ int up_cpu_resume(int cpu) { /* Release the spinlock that will alloc the CPU thread to continue */ - g_sim_cpuwait[cpu] = SP_UNLOCKED; + g_cpu_wait[cpu] = SP_UNLOCKED; return 0; } diff --git a/arch/sim/src/up_smpsignal.c b/arch/sim/src/up_smpsignal.c index f921c7f3b4..5b5c761a07 100644 --- a/arch/sim/src/up_smpsignal.c +++ b/arch/sim/src/up_smpsignal.c @@ -52,26 +52,53 @@ ****************************************************************************/ /**************************************************************************** - * Name: sim_cpu_pause + * Name: up_cpu_pausereq * * Description: - * This is the SIGUSR1 signal handling logic. It implements the core - * logic of up_cpu_pause() on the thread of execution the simulated CPU. - * This is the part of the implementation that must be performed in the - * NuttX vs. the host domain. + * Return true if a pause request is pending for this CPU. * * Input Parameters: - * cpu - The CPU being paused. - * wait - Spinlock to wait on to be un-paused - * paused - A boolean to set when we are in the paused state. + * cpu - The index of the CPU to be queried * * Returned Value: - * None + * true = a pause request is pending. + * false = no pasue request is pending. * ****************************************************************************/ -void sim_cpu_pause(int cpu, volatile spinlock_t *wait, - volatile unsigned char *paused) +bool up_cpu_pausereq(int cpu) +{ + return spin_islocked(&g_cpu_paused[cpu]); +} + +/**************************************************************************** + * Name: up_cpu_paused + * + * Description: + * Handle a pause request from another CPU. Normally, this logic is + * executed from interrupt handling logic within the architecture-specific + * However, it is sometimes necessary necessary to perform the pending + * pause operation in other contexts where the interrupt cannot be taken + * in order to avoid deadlocks. + * + * This function performs the following operations: + * + * 1. It saves the current task state at the head of the current assigned + * task list. + * 2. It waits on a spinlock, then + * 3. Returns from interrupt, restoring the state of the new task at the + * head of the ready to run list. + * + * Input Parameters: + * cpu - The index of the CPU to be paused + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused(int cpu) { struct tcb_s *rtcb = current_task(cpu); @@ -86,16 +113,18 @@ void sim_cpu_pause(int cpu, volatile spinlock_t *wait, if (up_setjmp(rtcb->xcp.regs) == 0) { - /* Indicate that we are in the paused state */ + /* Unlock the g_cpu_paused spinlock to indicate that we are in the + * paused state + */ - *paused = 1; + spin_unlock(&g_cpu_paused[cpu]); /* Spin until we are asked to resume. When we resume, we need to * inicate that we are not longer paused. */ - spin_lock(wait); - *paused = 0; + spin_lock(&g_cpu_wait[cpu]); + spin_unlock(&g_cpu_wait[cpu]); /* While we were paused, logic on a different CPU probably changed * the task as that head of the assigned task list. So now we need @@ -125,7 +154,8 @@ void sim_cpu_pause(int cpu, volatile spinlock_t *wait, up_longjmp(rtcb->xcp.regs, 1); } + + return OK; } #endif /* CONFIG_SMP */ - diff --git a/include/nuttx/arch.h b/include/nuttx/arch.h index 8b83308fc8..4affda90da 100644 --- a/include/nuttx/arch.h +++ b/include/nuttx/arch.h @@ -1827,6 +1827,56 @@ int up_cpu_start(int cpu); int up_cpu_pause(int cpu); #endif +/**************************************************************************** + * Name: up_cpu_pausereq + * + * Description: + * Return true if a pause request is pending for this CPU. + * + * Input Parameters: + * cpu - The index of the CPU to be queried + * + * Returned Value: + * true = a pause request is pending. + * false = no pasue request is pending. + * + ****************************************************************************/ + +#ifdef CONFIG_SMP +bool up_cpu_pausereq(int cpu); +#endif + +/**************************************************************************** + * Name: up_cpu_paused + * + * Description: + * Handle a pause request from another CPU. Normally, this logic is + * executed from interrupt handling logic within the architecture-specific + * However, it is sometimes necessary necessary to perform the pending + * pause operation in other contexts where the interrupt cannot be taken + * in order to avoid deadlocks. + * + * This function performs the following operations: + * + * 1. It saves the current task state at the head of the current assigned + * task list. + * 2. It waits on a spinlock, then + * 3. Returns from interrupt, restoring the state of the new task at the + * head of the ready to run list. + * + * Input Parameters: + * cpu - The index of the CPU to be paused + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +#ifdef CONFIG_SMP +int up_cpu_paused(int cpu); +#endif + /**************************************************************************** * Name: up_cpu_resume * diff --git a/include/nuttx/spinlock.h b/include/nuttx/spinlock.h index 0a9cc88a5e..1ad7fef525 100644 --- a/include/nuttx/spinlock.h +++ b/include/nuttx/spinlock.h @@ -59,6 +59,26 @@ #include +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Memory barriers may be provided in arch/spinlock.h + * + * DMB - Data memory barrier. Assures writes are completed to memory. + * DSB - Data syncrhonization barrier. + */ + +#define HAVE_DMB 1 +#ifndef SP_DMB +# define SP_DMB() +# undef HAVE_DMB +#endif + +#ifndef SP_DSB +# define SP_DSB() +#endif + /**************************************************************************** * Public Types ****************************************************************************/ @@ -203,7 +223,7 @@ void spin_lockr(FAR struct spinlock_s *lock); * ****************************************************************************/ -#ifdef SP_DMB +#ifdef HAVE_DMB void spin_unlock(FAR volatile spinlock_t *lock); #else # define spin_unlock(l) do { *(l) = SP_UNLOCKED; } while (0) diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 8071da9758..cabe791587 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -78,6 +78,81 @@ volatile cpu_set_t g_cpu_irqset; static uint8_t g_cpu_nestcount[CONFIG_SMP_NCPUS]; #endif +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: irq_waitlock + * + * Description: + * Spin to get g_irq_waitlock, handling a known deadlock condition: + * + * Suppose this situation: + * + * - CPUn is in a critical section and has the g_cpu_irqlock spinlock. + * - CPUm takes an interrupt and attempts to enter the critical section. + * - It spins waiting on g_cpu_irqlock with interrupts disabled. + * - CPUn calls up_cpu_pause() to pause operation on CPUm. This will + * issue an inter-CPU interrupt to CPUm + * - But interrupts are disabled on CPUm so the up_cpu_pause() is never + * handled, causing the deadlock. + * + * This function detects this deadlock condition while spinning in an + * interrupt and calls up_cpu_pause() handler, breaking the deadlock. + * + ****************************************************************************/ + +#ifdef CONFIG_SMP +static void irq_waitlock(void) +{ + int cpu = this_cpu(); + + /* Duplicate the spin_lock() logic from spinlock.c, but adding the check + * for the deadlock condition. + */ + + while (up_testset(&g_cpu_irqlock) == SP_LOCKED) + { + /* The deadlock condition would occur if CPUn: + * + * 1. Holds the g_cpu_irqlock, and + * 2. Is trying to interrupt CPUm + * + * The protocol for CPUn to pause CPUm is as follows + * + * 1. The up_cpu_pause() implementation on CPUn locks both + * g_cpu_wait[m] and g_cpu_paused[m]. CPUn then waits + * spinning on g_cpu_wait[m]. + * 2. When CPUm receives the interrupt it (1) unlocks + * g_cpu_paused[m] and (2) locks g_cpu_wait[m]. The + * first unblocks CPUn and the second blocks CPUm in the + * interrupt handler. + * + * The problem in the deadlock case is that CPUm cannot receive + * the interrupt because it is locked up spinning. He we break + * the deadlock here be handling the pause interrupt request + * while waiting. + */ + + if (up_cpu_pausereq(cpu)) + { + /* Yes.. some CPU is requesting to pause us! Handle the + * pause interrupt now. + */ + + DEBUGVERIFY(up_cpu_paused(cpu)); + } + + SP_DSB(); + } + + /* We have g_cpu_irqlock! */ + + SP_DMB(); +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -190,7 +265,7 @@ irqstate_t enter_critical_section(void) * no longer in the critical section). */ - spin_lock(&g_cpu_irqlock); + irq_waitlock(); } /* In any event, the nesting count is now one */ diff --git a/sched/semaphore/spinlock.c b/sched/semaphore/spinlock.c index a3c5225adf..e03f14c72f 100644 --- a/sched/semaphore/spinlock.c +++ b/sched/semaphore/spinlock.c @@ -65,22 +65,6 @@ #undef CONFIG_SPINLOCK_LOCKDOWN /* Feature not yet available */ -/* Memory barriers may be provided in arch/spinlock.h - * - * DMB - Data memory barrier. Assures writes are completed to memory. - * DSB - Data syncrhonization barrier. - */ - -#define HAVE_DMB 1 -#ifndef SP_DMB -# define SP_DMB() -# undef HAVE_DMB -#endif - -#ifndef SP_DSB -# define SP_DSB() -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/sched/task/task_restart.c b/sched/task/task_restart.c index 36251348ed..21aec95b47 100644 --- a/sched/task/task_restart.c +++ b/sched/task/task_restart.c @@ -97,7 +97,7 @@ int task_restart(pid_t pid) /* Not implemented */ errcode = ENOSYS; - goto errout_with_lock; + goto errout; } /* We are restarting some other task than ourselves. Make sure that the @@ -222,7 +222,8 @@ int task_restart(pid_t pid) return OK; errout_with_lock: - set_errno(errcode); leave_critical_section(flags); +errout: + set_errno(errcode); return ERROR; } -- GitLab From d1e84fb788b78d818eee9b5af904470bab510336 Mon Sep 17 00:00:00 2001 From: Ramtin Amin Date: Tue, 22 Nov 2016 12:10:11 -0600 Subject: [PATCH 487/734] Misoc: Add timer driver --- arch/misoc/src/common/misoc_serial.c | 32 +--- arch/misoc/src/common/misoc_timerisr.c | 140 ++++++++++++++ arch/misoc/src/lm32/Make.defs | 3 +- arch/misoc/src/lm32/lm32_reprioritizertr.c | 203 +++++++++++++++++++++ configs/misoc/hello/defconfig | 119 +++++++++++- 5 files changed, 464 insertions(+), 33 deletions(-) create mode 100644 arch/misoc/src/common/misoc_timerisr.c create mode 100644 arch/misoc/src/lm32/lm32_reprioritizertr.c diff --git a/arch/misoc/src/common/misoc_serial.c b/arch/misoc/src/common/misoc_serial.c index 9b15ba8e12..de914c8f61 100644 --- a/arch/misoc/src/common/misoc_serial.c +++ b/arch/misoc/src/common/misoc_serial.c @@ -205,13 +205,13 @@ static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; static struct misoc_dev_s g_uart1priv = { - .uartbase = CSR_UART_BASE, - .irq = UART_INTERRUPT, - .rxtx_addr = CSR_UART_RXTX_ADDR, - .rxempty_addr = CSR_UART_RXEMPTY_ADDR, - .txfull_addr = CSR_UART_TXFULL_ADDR, - .ev_status_addr = CSR_UART_EV_STATUS_ADDR, - .ev_pending_addr = CSR_UART_EV_PENDING_ADDR, + .uartbase = CSR_UART_BASE, + .irq = UART_INTERRUPT, + .rxtx_addr = CSR_UART_RXTX_ADDR, + .rxempty_addr = CSR_UART_RXEMPTY_ADDR, + .txfull_addr = CSR_UART_TXFULL_ADDR, + .ev_status_addr = CSR_UART_EV_STATUS_ADDR, + .ev_pending_addr = CSR_UART_EV_PENDING_ADDR, .ev_enable_addr = CSR_UART_EV_ENABLE_ADDR, }; @@ -312,16 +312,9 @@ static void misoc_shutdown(struct uart_dev_s *dev) static int misoc_attach(struct uart_dev_s *dev) { struct misoc_dev_s *priv = (struct misoc_dev_s *)dev->priv; - uint32_t im; - irq_attach(priv->irq, misoc_uart_interrupt); - - /* enable interrupt */ - /* TODO: move that somewhere proper ! */ - - im = irq_getmask(); - im |= (1 << UART_INTERRUPT); - irq_setmask(im); + (void)irq_attach(priv->irq, misoc_uart_interrupt); + up_enable_irq(priv->irq); return OK; } @@ -339,13 +332,8 @@ static int misoc_attach(struct uart_dev_s *dev) static void misoc_detach(struct uart_dev_s *dev) { struct misoc_dev_s *priv = (struct misoc_dev_s *)dev->priv; - uint32_t im; - - /* TODO: move that somewhere proper */ - im = irq_getmask(); - im &= ~(1 << UART_INTERRUPT); - irq_setmask(im); + up_disable_irq(priv->irq); irq_detach(priv->irq); } diff --git a/arch/misoc/src/common/misoc_timerisr.c b/arch/misoc/src/common/misoc_timerisr.c new file mode 100644 index 0000000000..3ad75dccf7 --- /dev/null +++ b/arch/misoc/src/common/misoc_timerisr.c @@ -0,0 +1,140 @@ +/**************************************************************************** + * arch/risc-v/src/nr5m100/nr5_timerisr.c + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for MISOC: + * + * Copyright (C) 2016 Ramtin Amin. All rights reserved. + * Author: Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" +#include "misoc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The desired timer interrupt frequency is provided by the definition + * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of + * system clock ticks per second. That value is a user configurable setting + * that defaults to 100 (100 ticks per second = 10 MS interval). + * + * The RCC feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK) + * divided by 8. The SysTick can work either with this clock or with the + * Cortex clock (HCLK), configurable in the SysTick Control and Status + * register. + */ + +#define SYSTICK_RELOAD ((MISOC_CLK_FREQUENCY / CLOCKS_PER_SEC) - 1) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +int up_timerisr(int irq, void *context) +{ + /* Clear event pending */ + + timer0_ev_pending_write(timer0_ev_pending_read()); + + /* Process timer interrupt */ + + sched_process_timer(); + return 0; +} + +/**************************************************************************** + * Function: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void misoc_timer_initialize(void) +{ + uint32_t im; + + /* Clear event pending */ + + timer0_ev_pending_write(timer0_ev_pending_read()); + + /* Disable timer*/ + + timer0_en_write(0); + + /* FIX ME, PUT PROPER VALUE */ + + timer0_reload_write(80000); + timer0_load_write(80000); + + /* Enable timer */ + + timer0_en_write(1); + + /* Attach the timer interrupt vector */ + + (void)irq_attach(TIMER0_INTERRUPT, up_timerisr); + + /* And enable the timer interrupt */ + + up_enable_irq(TIMER0_INTERRUPT); + + /* Enable IRQ of the timer core */ + + timer0_ev_enable_write(1); +} diff --git a/arch/misoc/src/lm32/Make.defs b/arch/misoc/src/lm32/Make.defs index 9c0768b2a4..01a6702dcb 100644 --- a/arch/misoc/src/lm32/Make.defs +++ b/arch/misoc/src/lm32/Make.defs @@ -39,7 +39,7 @@ HEAD_ASRC = lm32_vectors.S CMN_ASRCS = CMN_CSRCS = misoc_lowputs.c misoc_serial.c misoc_mdelay.c CMN_CSRCS += misoc_modifyreg8.c misoc_modifyreg16.c misoc_modifyreg32.c -CMN_CSRCS += misoc_puts.c misoc_udelay.c +CMN_CSRCS += misoc_puts.c misoc_udelay.c misoc_timerisr.c CHIP_ASRCS = lm32_syscall.S @@ -49,3 +49,4 @@ CHIP_CSRCS += lm32_doirq.c lm32_dumpstate.c lm32_exit.c lm32_idle.c CHIP_CSRCS += lm32_initialize.c lm32_initialstate.c lm32_interruptcontext.c CHIP_CSRCS += lm32_irq.c lm32_releasepending.c lm32_releasestack.c CHIP_CSRCS += lm32_stackframe.c lm32_swint.c lm32_unblocktask.c +CHIP_CSRCS += lm32_reprioritizertr.c diff --git a/arch/misoc/src/lm32/lm32_reprioritizertr.c b/arch/misoc/src/lm32/lm32_reprioritizertr.c new file mode 100644 index 0000000000..e6b4261101 --- /dev/null +++ b/arch/misoc/src/lm32/lm32_reprioritizertr.c @@ -0,0 +1,203 @@ +/**************************************************************************** + * arch/misoc/src/lm32/lm32_reprioritizertr.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "group/group.h" +#include "lm32.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_reprioritize_rtr + * + * Description: + * Called when the priority of a running or + * ready-to-run task changes and the reprioritization will + * cause a context switch. Two cases: + * + * 1) The priority of the currently running task drops and the next + * task in the ready to run list has priority. + * 2) An idle, ready to run task's priority has been raised above the + * the priority of the current, running task and it now has the + * priority. + * + * Inputs: + * tcb: The TCB of the task that has been reprioritized + * priority: The new task priority + * + ****************************************************************************/ + +void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) +{ + /* Verify that the caller is sane */ + + if (tcb->task_state < FIRST_READY_TO_RUN_STATE || + tcb->task_state > LAST_READY_TO_RUN_STATE +#if SCHED_PRIORITY_MIN > 0 + || priority < SCHED_PRIORITY_MIN +#endif +#if SCHED_PRIORITY_MAX < UINT8_MAX + || priority > SCHED_PRIORITY_MAX +#endif + ) + { + PANIC(); + } + else + { + struct tcb_s *rtcb = this_task(); + bool switch_needed; + + sinfo("TCB=%p PRI=%d\n", tcb, priority); + + /* Remove the tcb task from the ready-to-run list. + * sched_removereadytorun will return true if we just + * remove the head of the ready to run list. + */ + + switch_needed = sched_removereadytorun(tcb); + + /* Setup up the new task priority */ + + tcb->sched_priority = (uint8_t)priority; + + /* Return the task to the specified blocked task list. + * sched_addreadytorun will return true if the task was + * added to the new list. We will need to perform a context + * switch only if the EXCLUSIVE or of the two calls is non-zero + * (i.e., one and only one the calls changes the head of the + * ready-to-run list). + */ + + switch_needed ^= sched_addreadytorun(tcb); + + /* Now, perform the context switch if one is needed */ + + if (switch_needed) + { + /* If we are going to do a context switch, then now is the right + * time to add any pending tasks back into the ready-to-run list. + * task list now + */ + + if (g_pendingtasks.head) + { + sched_mergepending(); + } + + /* Update scheduler parameters */ + + sched_suspend_scheduler(rtcb); + + /* Are we in an interrupt handler? */ + + if (g_current_regs) + { + /* Yes, then we have to do things differently. + * Just copy the g_current_regs into the OLD rtcb. + */ + + up_savestate(rtcb->xcp.regs); + + /* Restore the exception context of the rtcb at the (new) head + * of the ready-to-run task list. + */ + + rtcb = this_task(); + + /* Update scheduler parameters */ + + sched_resume_scheduler(rtcb); + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + up_restorestate(rtcb->xcp.regs); + } + + /* No, then we will need to perform the user context switch */ + + else + { + /* Switch context to the context of the task at the head of the + * ready to run list. + */ + + struct tcb_s *nexttcb = this_task(); + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(nexttcb); +#endif + /* Update scheduler parameters */ + + sched_resume_scheduler(nexttcb); + + /* Then switch contexts */ + + up_switchcontext(rtcb->xcp.regs, nexttcb->xcp.regs); + + /* up_switchcontext forces a context switch to the task at the + * head of the ready-to-run list. It does not 'return' in the + * normal sense. When it does return, it is because the blocked + * task is again ready to run and has execution priority. + */ + } + } + } +} diff --git a/configs/misoc/hello/defconfig b/configs/misoc/hello/defconfig index dddddfd3ee..71aea364a7 100644 --- a/configs/misoc/hello/defconfig +++ b/configs/misoc/hello/defconfig @@ -221,7 +221,7 @@ CONFIG_PREALLOC_TIMERS=0 # CONFIG_INIT_NONE is not set CONFIG_INIT_ENTRYPOINT=y # CONFIG_INIT_FILEPATH is not set -CONFIG_USER_ENTRYPOINT="hello_main" +CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_RR_INTERVAL=0 # CONFIG_SCHED_SPORADIC is not set CONFIG_TASK_NAME_SIZE=0 @@ -263,9 +263,9 @@ CONFIG_NAME_MAX=32 # # Stack and heap information # -CONFIG_IDLETHREAD_STACKSIZE=512 -CONFIG_USERMAIN_STACKSIZE=512 -CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=1024 +CONFIG_PTHREAD_STACK_MIN=512 CONFIG_PTHREAD_STACK_DEFAULT=1024 # CONFIG_LIB_SYSCALL is not set @@ -546,7 +546,7 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 # CONFIG_EXAMPLES_MODBUS is not set # CONFIG_EXAMPLES_MOUNT is not set # CONFIG_EXAMPLES_NRF24L01TERM is not set -# CONFIG_EXAMPLES_NSH is not set +CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NULL is not set # CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set @@ -555,7 +555,12 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set -# CONFIG_EXAMPLES_OSTEST is not set +CONFIG_EXAMPLES_OSTEST=y +CONFIG_EXAMPLES_OSTEST_LOOPS=1 +CONFIG_EXAMPLES_OSTEST_STACKSIZE=8192 +CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=8 +CONFIG_EXAMPLES_OSTEST_RR_RANGE=10000 +CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_EXAMPLES_PCA9635 is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set @@ -618,7 +623,97 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 # # NSH Library # -# CONFIG_NSH_LIBRARY is not set +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +# CONFIG_NSH_READLINE is not set +CONFIG_NSH_CLE=y +CONFIG_NSH_LINELEN=80 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +CONFIG_NSH_MAXARGUMENTS=6 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +CONFIG_NSH_DISABLE_IFCONFIG=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y +CONFIG_NSH_DISABLE_PS=y +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Configure Command Options +# +CONFIG_NSH_CMDOPT_DF_H=y +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_CMDOPT_HEXDUMP=y +CONFIG_NSH_FILEIOSIZE=1024 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +# CONFIG_NSH_ARCHINIT is not set +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set # # NxWidgets/NxWM @@ -632,15 +727,19 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 # # System Libraries and NSH Add-Ons # -# CONFIG_SYSTEM_CLE is not set +CONFIG_SYSTEM_CLE=y +CONFIG_SYSTEM_CLE_DEBUGLEVEL=0 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set # CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set -# CONFIG_READLINE_HAVE_EXTMATCH is not set -# CONFIG_SYSTEM_READLINE is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set # CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set -- GitLab From 054072d0544ce76229ad06c9fa88bb7ec4830848 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 22 Nov 2016 12:15:34 -0600 Subject: [PATCH 488/734] Misoc: Add commits and warnings about missing caculation of the timer reload value --- arch/misoc/src/common/misoc_timerisr.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/misoc/src/common/misoc_timerisr.c b/arch/misoc/src/common/misoc_timerisr.c index 3ad75dccf7..d6d5bfabd6 100644 --- a/arch/misoc/src/common/misoc_timerisr.c +++ b/arch/misoc/src/common/misoc_timerisr.c @@ -63,13 +63,13 @@ * system clock ticks per second. That value is a user configurable setting * that defaults to 100 (100 ticks per second = 10 MS interval). * - * The RCC feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK) - * divided by 8. The SysTick can work either with this clock or with the - * Cortex clock (HCLK), configurable in the SysTick Control and Status - * register. + * What clock feeds the timer? What rate does the timer increment by. The + * correct reload value is: + * + * reload = Finput / CLOCKS_PER_SEC */ -#define SYSTICK_RELOAD ((MISOC_CLK_FREQUENCY / CLOCKS_PER_SEC) - 1) +#warning Missing logic /**************************************************************************** * Public Functions @@ -118,6 +118,7 @@ void misoc_timer_initialize(void) timer0_en_write(0); /* FIX ME, PUT PROPER VALUE */ +#warning Missing logic timer0_reload_write(80000); timer0_load_write(80000); -- GitLab From 12f830ffd50e201926f2969ea6555828aae147b7 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 22 Nov 2016 11:15:37 -0600 Subject: [PATCH 489/734] SAM3/4: Name of method is now setcallback, not sethandler --- arch/arm/src/sam34/sam_tc.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/src/sam34/sam_tc.c b/arch/arm/src/sam34/sam_tc.c index 1ddab1c20f..4a1b2abf79 100644 --- a/arch/arm/src/sam34/sam_tc.c +++ b/arch/arm/src/sam34/sam_tc.c @@ -125,7 +125,7 @@ static int sam34_getstatus(FAR struct timer_lowerhalf_s *lower, FAR struct timer_status_s *status); static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower, uint32_t timeout); -static void sam34_sethandler(FAR struct timer_lowerhalf_s *lower, +static void sam34_setcallback(FAR struct timer_lowerhalf_s *lower, tccb_t callback, FAR void *arg); static int sam34_ioctl(FAR struct timer_lowerhalf_s *lower, int cmd, unsigned long arg); @@ -137,12 +137,12 @@ static int sam34_ioctl(FAR struct timer_lowerhalf_s *lower, int cmd, static const struct timer_ops_s g_tcops = { - .start = sam34_start, - .stop = sam34_stop, - .getstatus = sam34_getstatus, - .settimeout = sam34_settimeout, - .sethandler = sam34_sethandler, - .ioctl = sam34_ioctl, + .start = sam34_start, + .stop = sam34_stop, + .getstatus = sam34_getstatus, + .settimeout = sam34_settimeout, + .setcallback = sam34_setcallback, + .ioctl = sam34_ioctl, }; /* "Lower half" driver state */ @@ -513,8 +513,8 @@ static int sam34_settimeout(FAR struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static void sam34_sethandler(FAR struct timer_lowerhalf_s *lower, - tccb_t callback, FAR void *arg) +static void sam34_setcallback(FAR struct timer_lowerhalf_s *lower, + tccb_t callback, FAR void *arg) { FAR struct sam34_lowerhalf_s *priv = (FAR struct sam34_lowerhalf_s *)lower; irqstate_t flags; -- GitLab From 09b6af96ba9dcdf33f92da4e425c97108a906396 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 22 Nov 2016 11:38:52 -0600 Subject: [PATCH 490/734] sam4s-xplained-pro/nsh: Configuration uses old, improper timer timer interface. CONFIG_TIMER disabled in configuration.>> --- configs/sam4s-xplained-pro/nsh/defconfig | 25 ++++++++++++++++++---- configs/sam4s-xplained-pro/src/sam_tc.c | 27 +++++++++++++++--------- 2 files changed, 38 insertions(+), 14 deletions(-) diff --git a/configs/sam4s-xplained-pro/nsh/defconfig b/configs/sam4s-xplained-pro/nsh/defconfig index 45fbddf1c5..dd20b99e65 100644 --- a/configs/sam4s-xplained-pro/nsh/defconfig +++ b/configs/sam4s-xplained-pro/nsh/defconfig @@ -61,10 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -369,8 +372,6 @@ CONFIG_ARCH_HAVE_IRQBUTTONS=y # Board-Specific Options # CONFIG_SAM4S_XPLAINED_PRO_CDCACM_DEVMINOR=0 -CONFIG_SAM4S_XPLAINED_PRO_SCHED_TIMER_DEVPATH="/dev/rtt0" -CONFIG_SAM4S_XPLAINED_PRO_CPULOAD_TIMER_DEVPATH="/dev/tc0" # CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set @@ -399,6 +400,7 @@ CONFIG_USEC_PER_TICK=10000 CONFIG_SYSTEMTICK_EXTCLK=y # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set CONFIG_JULIAN_TIME=y CONFIG_MAX_WDOGPARMS=2 CONFIG_PREALLOC_WDOGS=32 @@ -431,6 +433,8 @@ CONFIG_NPTHREAD_KEYS=4 CONFIG_SCHED_CPULOAD=y CONFIG_SCHED_CPULOAD_EXTCLK=y CONFIG_SCHED_CPULOAD_TICKSPERSEC=222 +# CONFIG_CPULOAD_ONESHOT is not set +CONFIG_CPULOAD_ONESHOT_ENTROPY=6 CONFIG_SCHED_CPULOAD_TIMECONSTANT=2 # CONFIG_SCHED_INSTRUMENTATION is not set @@ -513,12 +517,16 @@ CONFIG_DEV_ZERO=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # -CONFIG_TIMER=y +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y # CONFIG_RTC_DATETIME is not set CONFIG_RTC_HIRES=y @@ -699,6 +707,7 @@ CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial" # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -812,6 +821,8 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -872,6 +883,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set CONFIG_EXAMPLES_CPUHOG=y @@ -909,6 +922,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -932,7 +946,6 @@ CONFIG_EXAMPLES_SERIALRX_PRINTHEX=y # CONFIG_EXAMPLES_TCPECHO is not set # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_TIFF is not set -# CONFIG_EXAMPLES_TIMER is not set # CONFIG_EXAMPLES_TOUCHSCREEN is not set # CONFIG_EXAMPLES_USBSERIAL is not set # CONFIG_EXAMPLES_USBTERM is not set @@ -962,6 +975,7 @@ CONFIG_EXAMPLES_SERIALRX_PRINTHEX=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1034,6 +1048,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1106,6 +1121,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sam4s-xplained-pro/src/sam_tc.c b/configs/sam4s-xplained-pro/src/sam_tc.c index f00fd42c04..8d25619c79 100644 --- a/configs/sam4s-xplained-pro/src/sam_tc.c +++ b/configs/sam4s-xplained-pro/src/sam_tc.c @@ -99,6 +99,8 @@ * Private Functions ****************************************************************************/ +#if 0 /* Cannot be used -- needs to be updated to current, signal based interface */ + #if defined(CONFIG_SYSTEMTICK_EXTCLK) && !defined(CONFIG_SUPPRESS_INTERRUPTS) && \ !defined(CONFIG_SUPPRESS_TIMER_INTS) @@ -119,6 +121,7 @@ static bool calc_cpuload(FAR uint32_t *next_interval_us) } #endif /* CONFIG_SCHED_CPULOAD && CONFIG_SCHED_CPULOAD_EXTCLK */ +#endif /* 0 */ /**************************************************************************** * Public Functions @@ -134,6 +137,7 @@ static bool calc_cpuload(FAR uint32_t *next_interval_us) int sam_timerinitialize(void) { +#if 0 /* Cannot be used -- needs to be updated to current, signal based interface */ int fd; int ret; @@ -200,14 +204,14 @@ int sam_timerinitialize(void) /* install user callback */ { - struct timer_sethandler_s tccb; - tccb.newhandler = systemtick; - tccb.oldhandler = NULL; + struct timer_notify_s notify; + notify.newhandler = systemtick; + notify.oldhandler = NULL; - ret = ioctl(fd, TCIOC_SETHANDLER, (unsigned long)&tccb); + ret = ioctl(fd, TCIOC_NOTIFICATION, (unsigned long)¬ify); if (ret < 0) { - tmrerr("ERROR: ioctl(TCIOC_SETHANDLER) failed: %d\n", errno); + tmrerr("ERROR: ioctl(TCIOC_NOTIFICATION) failed: %d\n", errno); goto errout_with_dev; } } @@ -251,14 +255,14 @@ int sam_timerinitialize(void) /* Install user callback */ { - struct timer_sethandler_s tccb; - tccb.newhandler = calc_cpuload; - tccb.oldhandler = NULL; + struct timer_notify_s notify; + notify.newhandler = calc_cpuload; + notify.oldhandler = NULL; - ret = ioctl(fd, TCIOC_SETHANDLER, (unsigned long)&tccb); + ret = ioctl(fd, TCIOC_NOTIFICATION, (unsigned long)¬ify); if (ret < 0) { - tmrerr("ERROR: ioctl(TCIOC_SETHANDLER) failed: %d\n", errno); + tmrerr("ERROR: ioctl(TCIOC_NOTIFICATION) failed: %d\n", errno); goto errout_with_dev; } } @@ -282,6 +286,9 @@ errout: success: return OK; +#else + return -ENOSYS; +#endif } -- GitLab From d95b8f64f53fede788ae027aace79d94e6d33c7e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 22 Nov 2016 12:25:57 -0600 Subject: [PATCH 491/734] sam4s-xplained-pro: Remove obsolete timer initialization logic --- arch/misoc/src/common/misoc_serial.c | 1 - configs/sam4s-xplained-pro/src/Makefile | 4 - .../src/sam4s-xplained-pro.h | 14 - configs/sam4s-xplained-pro/src/sam_appinit.c | 8 - configs/sam4s-xplained-pro/src/sam_boot.c | 17 +- configs/sam4s-xplained-pro/src/sam_tc.c | 295 ------------------ 6 files changed, 1 insertion(+), 338 deletions(-) delete mode 100644 configs/sam4s-xplained-pro/src/sam_tc.c diff --git a/arch/misoc/src/common/misoc_serial.c b/arch/misoc/src/common/misoc_serial.c index de914c8f61..c9b1f83863 100644 --- a/arch/misoc/src/common/misoc_serial.c +++ b/arch/misoc/src/common/misoc_serial.c @@ -334,7 +334,6 @@ static void misoc_detach(struct uart_dev_s *dev) struct misoc_dev_s *priv = (struct misoc_dev_s *)dev->priv; up_disable_irq(priv->irq); - irq_detach(priv->irq); } diff --git a/configs/sam4s-xplained-pro/src/Makefile b/configs/sam4s-xplained-pro/src/Makefile index 62b5b37250..e46e7c7eea 100644 --- a/configs/sam4s-xplained-pro/src/Makefile +++ b/configs/sam4s-xplained-pro/src/Makefile @@ -64,8 +64,4 @@ ifeq ($(CONFIG_SAM34_WDT),y) CSRCS += sam_wdt.c endif -ifeq ($(CONFIG_TIMER),y) -CSRCS += sam_tc.c -endif - include $(TOPDIR)/configs/Board.mk diff --git a/configs/sam4s-xplained-pro/src/sam4s-xplained-pro.h b/configs/sam4s-xplained-pro/src/sam4s-xplained-pro.h index 081e8f73f2..d995541bbb 100644 --- a/configs/sam4s-xplained-pro/src/sam4s-xplained-pro.h +++ b/configs/sam4s-xplained-pro/src/sam4s-xplained-pro.h @@ -215,20 +215,6 @@ bool sam_writeprotected(int slotno); # define sam_writeprotected(slotno) (false) #endif -/************************************************************************************ - * Name: sam_timerinitialize() - * - * Description: - * Perform architecture-specific initialization of the timer hardware. - * - ************************************************************************************/ - -#ifdef CONFIG_TIMER -int sam_timerinitialize(void); -#else -# define sam_timerinitialize() (0) -#endif - /**************************************************************************** * Name: sam_watchdog_initialize() * diff --git a/configs/sam4s-xplained-pro/src/sam_appinit.c b/configs/sam4s-xplained-pro/src/sam_appinit.c index 7ac7f1587c..6cb0cabe91 100644 --- a/configs/sam4s-xplained-pro/src/sam_appinit.c +++ b/configs/sam4s-xplained-pro/src/sam_appinit.c @@ -59,20 +59,12 @@ # include #endif -#ifdef CONFIG_TIMER -# include -#endif - #ifdef CONFIG_USBMONITOR # include #endif #include "sam4s-xplained-pro.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/configs/sam4s-xplained-pro/src/sam_boot.c b/configs/sam4s-xplained-pro/src/sam_boot.c index ce7ae2fad3..54767ee59c 100644 --- a/configs/sam4s-xplained-pro/src/sam_boot.c +++ b/configs/sam4s-xplained-pro/src/sam_boot.c @@ -42,19 +42,10 @@ #include #include -#include #include #include "sam4s-xplained-pro.h" -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ @@ -91,6 +82,7 @@ void sam_boardinitialize(void) * may be used, for example, to initialize board-specific device drivers. * ****************************************************************************/ + #ifdef CONFIG_BOARD_INITIALIZE void board_initialize(void) { @@ -105,12 +97,5 @@ void board_initialize(void) sam_led_initialize(); #endif - -#ifdef CONFIG_TIMER - /* Registers the timers and starts any async processes (which may include the scheduler) */ - - sam_timerinitialize(); -#endif - } #endif /* CONFIG_BOARD_INITIALIZE */ diff --git a/configs/sam4s-xplained-pro/src/sam_tc.c b/configs/sam4s-xplained-pro/src/sam_tc.c deleted file mode 100644 index 8d25619c79..0000000000 --- a/configs/sam4s-xplained-pro/src/sam_tc.c +++ /dev/null @@ -1,295 +0,0 @@ -/**************************************************************************** - * configs/sam4s-xplained-pro/src/sam_tc.c - * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Bob Doiron - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "sam_lowputc.h" -#include "sam_tc.h" -#include "sam_rtt.h" - -#ifdef CONFIG_TIMER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ -/* Configuration ************************************************************/ - -#if !(defined(CONFIG_SAM34_TC0) || defined(CONFIG_SAM34_TC1) || defined(CONFIG_SAM34_TC2) \ - || defined(CONFIG_SAM34_TC3) || defined(CONFIG_SAM34_TC4) || defined(CONFIG_SAM34_RTT) ) -# warning "CONFIG_SAM34_TCx or CONFIG_SAM34_RTT must be defined" -#endif - -/* Select the path to the registered watchdog timer device */ - -#ifndef CONFIG_TIMER0_DEVPATH -# define CONFIG_TIMER0_DEVPATH "/dev/tc0" -#endif -#ifndef CONFIG_TIMER1_DEVPATH -# define CONFIG_TIMER1_DEVPATH "/dev/tc1" -#endif -#ifndef CONFIG_TIMER2_DEVPATH -# define CONFIG_TIMER2_DEVPATH "/dev/tc2" -#endif -#ifndef CONFIG_TIMER3_DEVPATH -# define CONFIG_TIMER3_DEVPATH "/dev/tc3" -#endif -#ifndef CONFIG_TIMER4_DEVPATH -# define CONFIG_TIMER4_DEVPATH "/dev/tc4" -#endif -#ifndef CONFIG_TIMER5_DEVPATH -# define CONFIG_TIMER5_DEVPATH "/dev/tc5" -#endif -#ifndef CONFIG_RTT_DEVPATH -# define CONFIG_RTT_DEVPATH "/dev/rtt0" -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -#if 0 /* Cannot be used -- needs to be updated to current, signal based interface */ - -#if defined(CONFIG_SYSTEMTICK_EXTCLK) && !defined(CONFIG_SUPPRESS_INTERRUPTS) && \ - !defined(CONFIG_SUPPRESS_TIMER_INTS) - -static bool systemtick(FAR uint32_t *next_interval_us) -{ - sched_process_timer(); - return true; // reload, no change to interval -} - -#endif /* CONFIG_SYSTEMTICK_EXTCLK && !CONFIG_SUPPRESS_INTERRUPTS && !CONFIG_SUPPRESS_TIMER_INTS */ - -#if defined(CONFIG_SCHED_CPULOAD) && defined(CONFIG_SCHED_CPULOAD_EXTCLK) - -static bool calc_cpuload(FAR uint32_t *next_interval_us) -{ - sched_process_cpuload(); - return TRUE; /* Reload, no change to interval */ -} - -#endif /* CONFIG_SCHED_CPULOAD && CONFIG_SCHED_CPULOAD_EXTCLK */ -#endif /* 0 */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: sam_timerinitialize() - * - * Description: - * Perform architecture-specific initialization of the timer hardware. - * - ****************************************************************************/ - -int sam_timerinitialize(void) -{ -#if 0 /* Cannot be used -- needs to be updated to current, signal based interface */ - int fd; - int ret; - - /* Initialize and register the timer devices */ - -#if defined(CONFIG_SAM34_TC0) - tmrinfo("Initializing %s...\n", CONFIG_TIMER0_DEVPATH); - sam_tcinitialize(CONFIG_TIMER0_DEVPATH, SAM_IRQ_TC0); -#endif - -#if defined(CONFIG_SAM34_TC1) - tmrinfo("Initializing %s...\n", CONFIG_TIMER1_DEVPATH); - sam_tcinitialize(CONFIG_TIMER1_DEVPATH, SAM_IRQ_TC1); -#endif - -#if defined(CONFIG_SAM34_TC2) - tmrinfo("Initializing %s...\n", CONFIG_TIMER2_DEVPATH); - sam_tcinitialize(CONFIG_TIMER2_DEVPATH, SAM_IRQ_TC2); -#endif - -#if defined(CONFIG_SAM34_TC3) - tmrinfo("Initializing %s...\n", CONFIG_TIMER3_DEVPATH); - sam_tcinitialize(CONFIG_TIMER3_DEVPATH, SAM_IRQ_TC3); -#endif - -#if defined(CONFIG_SAM34_TC4) - tmrinfo("Initializing %s...\n", CONFIG_TIMER4_DEVPATH); - sam_tcinitialize(CONFIG_TIMER4_DEVPATH, SAM_IRQ_TC4); -#endif - -#if defined(CONFIG_SAM34_TC5) - tmrinfo("Initializing %s...\n", CONFIG_TIMER5_DEVPATH); - sam_tcinitialize(CONFIG_TIMER5_DEVPATH, SAM_IRQ_TC5); -#endif - -#if defined(CONFIG_SAM34_RTT) - tmrinfo("Initializing %s...\n", CONFIG_RTT_DEVPATH); - sam_rttinitialize(CONFIG_RTT_DEVPATH); -#endif - -#if defined(CONFIG_SYSTEMTICK_EXTCLK) && !defined(CONFIG_SUPPRESS_INTERRUPTS) && \ - !defined(CONFIG_SUPPRESS_TIMER_INTS) - /* System Timer Initialization */ - - tmrinfo("Opening %s\n", CONFIG_SAM4S_XPLAINED_PRO_SCHED_TIMER_DEVPATH); - - fd = open(CONFIG_SAM4S_XPLAINED_PRO_SCHED_TIMER_DEVPATH, O_RDONLY); - if (fd < 0) - { - tmrerr("ERROR: open %s failed: %d\n", - CONFIG_SAM4S_XPLAINED_PRO_SCHED_TIMER_DEVPATH, errno); - goto errout; - } - - /* Set the timeout */ - - tmrinfo("Interval = %d us.\n", (unsigned long)USEC_PER_TICK); - ret = ioctl(fd, TCIOC_SETTIMEOUT, (unsigned long)USEC_PER_TICK); - if (ret < 0) - { - tmrerr("ERROR: ioctl(TCIOC_SETTIMEOUT) failed: %d\n", errno); - goto errout_with_dev; - } - - /* install user callback */ - { - struct timer_notify_s notify; - notify.newhandler = systemtick; - notify.oldhandler = NULL; - - ret = ioctl(fd, TCIOC_NOTIFICATION, (unsigned long)¬ify); - if (ret < 0) - { - tmrerr("ERROR: ioctl(TCIOC_NOTIFICATION) failed: %d\n", errno); - goto errout_with_dev; - } - } - - /* Start the timer */ - - tmrinfo("Starting.\n"); - ret = ioctl(fd, TCIOC_START, 0); - if (ret < 0) - { - tmrerr("ERROR: ioctl(TCIOC_START) failed: %d\n", errno); - goto errout_with_dev; - } -#endif - -#if defined(CONFIG_SCHED_CPULOAD) && defined(CONFIG_SCHED_CPULOAD_EXTCLK) - /* CPU Load initialization */ - - tmrinfo("Opening %s\n", CONFIG_SAM4S_XPLAINED_PRO_CPULOAD_TIMER_DEVPATH); - - fd = open(CONFIG_SAM4S_XPLAINED_PRO_CPULOAD_TIMER_DEVPATH, O_RDONLY); - if (fd < 0) - { - tmrerr("ERROR: open %s failed: %d\n", - CONFIG_SAM4S_XPLAINED_PRO_CPULOAD_TIMER_DEVPATH, errno); - goto errout; - } - - /* Set the timeout */ - - tmrinfo("Interval = %d us.\n", (unsigned long)1000000 / CONFIG_SCHED_CPULOAD_TICKSPERSEC); - - ret = ioctl(fd, TCIOC_SETTIMEOUT, - (unsigned long)1000000 / CONFIG_SCHED_CPULOAD_TICKSPERSEC); - if (ret < 0) - { - tmrerr("ERROR: ioctl(TCIOC_SETTIMEOUT) failed: %d\n", errno); - goto errout_with_dev; - } - - /* Install user callback */ - - { - struct timer_notify_s notify; - notify.newhandler = calc_cpuload; - notify.oldhandler = NULL; - - ret = ioctl(fd, TCIOC_NOTIFICATION, (unsigned long)¬ify); - if (ret < 0) - { - tmrerr("ERROR: ioctl(TCIOC_NOTIFICATION) failed: %d\n", errno); - goto errout_with_dev; - } - } - - /* Start the timer */ - - tmrinfo("Starting.\n"); - ret = ioctl(fd, TCIOC_START, 0); - if (ret < 0) - { - tmrerr("ERROR: ioctl(TCIOC_START) failed: %d\n", errno); - goto errout_with_dev; - } -#endif - - goto success; -errout_with_dev: - close(fd); -errout: - return ERROR; - -success: - return OK; -#else - return -ENOSYS; -#endif - -} - -#endif /* CONFIG_TIMER */ -- GitLab From f90525a5d1a0a9b427c1880730ffb3d684e32eee Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 22 Nov 2016 16:48:57 -0600 Subject: [PATCH 492/734] SMP: Update some comments; trivial improvement by inlining static function. --- arch/arm/src/armv7-a/arm_cpupause.c | 2 +- arch/sim/src/up_internal.h | 2 +- arch/sim/src/up_simsmp.c | 2 +- sched/irq/irq_csection.c | 8 +++----- 4 files changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_cpupause.c b/arch/arm/src/armv7-a/arm_cpupause.c index 4abfac25b1..55ffbf9385 100644 --- a/arch/arm/src/armv7-a/arm_cpupause.c +++ b/arch/arm/src/armv7-a/arm_cpupause.c @@ -59,7 +59,7 @@ * up_cpu_pause(). The protocol for CPUn to pause CPUm is as follows * * 1. The up_cpu_pause() implementation on CPUn locks both g_cpu_wait[m] - * and g_cpu_paused[m]. CPUn then waits spinning on g_cpu_wait[m]. + * and g_cpu_paused[m]. CPUn then waits spinning on g_cpu_paused[m]. * 2. CPUm receives the interrupt it (1) unlocks g_cpu_paused[m] and * (2) locks g_cpu_wait[m]. The first unblocks CPUn and the second * blocks CPUm in the interrupt handler. diff --git a/arch/sim/src/up_internal.h b/arch/sim/src/up_internal.h index ac0a2269ab..9facb343af 100644 --- a/arch/sim/src/up_internal.h +++ b/arch/sim/src/up_internal.h @@ -204,7 +204,7 @@ extern volatile int g_uart_data_available; * up_cpu_pause(). The protocol for CPUn to pause CPUm is as follows * * 1. The up_cpu_pause() implementation on CPUn locks both g_cpu_wait[m] - * and g_cpu_paused[m]. CPUn then waits spinning on g_cpu_wait[m]. + * and g_cpu_paused[m]. CPUn then waits spinning on g_cpu_paused[m]. * 2. CPUm receives the interrupt it (1) unlocks g_cpu_paused[m] and * (2) locks g_cpu_wait[m]. The first unblocks CPUn and the second * blocks CPUm in the interrupt handler. diff --git a/arch/sim/src/up_simsmp.c b/arch/sim/src/up_simsmp.c index 5b24f6015c..8a1469976d 100644 --- a/arch/sim/src/up_simsmp.c +++ b/arch/sim/src/up_simsmp.c @@ -83,7 +83,7 @@ static pthread_t g_sim_cputhread[CONFIG_SMP_NCPUS]; * up_cpu_pause(). The protocol for CPUn to pause CPUm is as follows * * 1. The up_cpu_pause() implementation on CPUn locks both g_cpu_wait[m] - * and g_cpu_paused[m]. CPUn then waits spinning on g_cpu_wait[m]. + * and g_cpu_paused[m]. CPUn then waits spinning on g_cpu_paused[m]. * 2. CPUm receives the interrupt it (1) unlocks g_cpu_paused[m] and * (2) locks g_cpu_wait[m]. The first unblocks CPUn and the second * blocks CPUm in the interrupt handler. diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index cabe791587..96fb3abb1b 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -104,10 +104,8 @@ static uint8_t g_cpu_nestcount[CONFIG_SMP_NCPUS]; ****************************************************************************/ #ifdef CONFIG_SMP -static void irq_waitlock(void) +static inline void irq_waitlock(int cpu) { - int cpu = this_cpu(); - /* Duplicate the spin_lock() logic from spinlock.c, but adding the check * for the deadlock condition. */ @@ -262,10 +260,10 @@ irqstate_t enter_critical_section(void) if ((g_cpu_irqset & (1 << cpu)) == 0) { /* Wait until we can get the spinlock (meaning that we are - * no longer in the critical section). + * no longer blocked by the critical section). */ - irq_waitlock(); + irq_waitlock(cpu); } /* In any event, the nesting count is now one */ -- GitLab From b8754afb1460a4cede8ae93495222eb0d50c14a9 Mon Sep 17 00:00:00 2001 From: Ramtin Amin Date: Wed, 23 Nov 2016 07:00:57 -0600 Subject: [PATCH 493/734] Misoc LM32: Make system timer configurable via CONFIG_USEC_PER_TICK. --- arch/misoc/src/common/misoc.h | 10 ++++++++ arch/misoc/src/common/misoc_timerisr.c | 34 +++++++++++++++++--------- arch/misoc/src/lm32/lm32_initialize.c | 6 +++-- 3 files changed, 36 insertions(+), 14 deletions(-) diff --git a/arch/misoc/src/common/misoc.h b/arch/misoc/src/common/misoc.h index 4726759ea5..1531f3dc7f 100644 --- a/arch/misoc/src/common/misoc.h +++ b/arch/misoc/src/common/misoc.h @@ -63,6 +63,16 @@ #ifndef __ASSEMBLY__ +/**************************************************************************** + * Name: misoc_timer_initialize + * + * Description: + * Initialize and start the system timer. + * + ****************************************************************************/ + +void misoc_timer_initialize(void); + /**************************************************************************** * Name: up_serialinit * diff --git a/arch/misoc/src/common/misoc_timerisr.c b/arch/misoc/src/common/misoc_timerisr.c index d6d5bfabd6..3de69520be 100644 --- a/arch/misoc/src/common/misoc_timerisr.c +++ b/arch/misoc/src/common/misoc_timerisr.c @@ -47,10 +47,12 @@ #include #include #include + #include #include #include #include + #include "chip.h" #include "misoc.h" @@ -59,17 +61,26 @@ ****************************************************************************/ /* The desired timer interrupt frequency is provided by the definition - * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of - * system clock ticks per second. That value is a user configurable setting - * that defaults to 100 (100 ticks per second = 10 MS interval). + * CLOCKS_PER_SEC (see include/time.h). CLOCKS_PER_SEC defines the desired + * number of system clock ticks per second. That value is a user + * configurable setting based on CONFIG_USEC_PER_TICK. It defaults to 100 + * (100 ticks per second = 10 MS interval). * - * What clock feeds the timer? What rate does the timer increment by. The - * correct reload value is: + * Given the timer input frequency (Finput). The timer correct reload + * value is: * * reload = Finput / CLOCKS_PER_SEC */ -#warning Missing logic +#define SYSTICK_RELOAD ((SYSTEM_CLOCK_FREQUENCY / CLOCKS_PER_SEC) - 1) + +/* The size of the reload field is 30 bits. Verify that the reload value + * will fit in the reload register. + */ + +#if SYSTICK_RELOAD > 0x3fffffff +# error SYSTICK_RELOAD exceeds the range of the RELOAD register +#endif /**************************************************************************** * Public Functions @@ -107,8 +118,6 @@ int up_timerisr(int irq, void *context) void misoc_timer_initialize(void) { - uint32_t im; - /* Clear event pending */ timer0_ev_pending_write(timer0_ev_pending_read()); @@ -117,11 +126,12 @@ void misoc_timer_initialize(void) timer0_en_write(0); - /* FIX ME, PUT PROPER VALUE */ -#warning Missing logic + /* Setup the timer reload register to generate interrupts at the rate of + * CLOCKS_PER_SEC. + */ - timer0_reload_write(80000); - timer0_load_write(80000); + timer0_reload_write(SYSTICK_RELOAD); + timer0_load_write(SYSTICK_RELOAD); /* Enable timer */ diff --git a/arch/misoc/src/lm32/lm32_initialize.c b/arch/misoc/src/lm32/lm32_initialize.c index 23e6e8fc1f..dd93cce4b6 100644 --- a/arch/misoc/src/lm32/lm32_initialize.c +++ b/arch/misoc/src/lm32/lm32_initialize.c @@ -72,7 +72,9 @@ void up_initialize(void) /* Initialize the serial driver */ -#warning REVISIT: Here you should all misoc_serial_initialize(). That initializes the entire serial driver, a part of the operation is the uart initialization. - misoc_serial_initialize(); + + /* Initialize the system timer */ + + misoc_timer_initialize(); } -- GitLab From d4037a30aa1ebf08639fd47864e4cfd9ffbc8e05 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 23 Nov 2016 13:20:18 -0600 Subject: [PATCH 494/734] Update some comments --- configs/sabre-6quad/README.txt | 3 --- sched/sched/sched_removereadytorun.c | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/configs/sabre-6quad/README.txt b/configs/sabre-6quad/README.txt index 02e6acb6ec..ec41ee6271 100644 --- a/configs/sabre-6quad/README.txt +++ b/configs/sabre-6quad/README.txt @@ -482,9 +482,6 @@ The i.MX6 6Quad has 4 CPUs. Support is included for testing an SMP configuration. That configuration is still not yet ready for usage but can be enabled with the following configuration settings: - Build Setup: - CONFIG_EXPERIMENTAL=y - RTOS Features -> Tasks and Scheduling CONFIG_SPINLOCK=y CONFIG_SMP=y diff --git a/sched/sched/sched_removereadytorun.c b/sched/sched/sched_removereadytorun.c index 35543037ef..85c3d43fac 100644 --- a/sched/sched/sched_removereadytorun.c +++ b/sched/sched/sched_removereadytorun.c @@ -260,7 +260,7 @@ bool sched_removereadytorun(FAR struct tcb_s *rtcb) } else { - /* No.. we may need to perform release our hold on the irq state. */ + /* No.. we may need to release our hold on the irq state. */ spin_clrbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock, &g_cpu_irqlock); -- GitLab From bbc17abf6805a5c3dfb113b816bbcfbae5012311 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 23 Nov 2016 13:30:51 -0600 Subject: [PATCH 495/734] Update some comments --- TODO | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/TODO b/TODO index d50c610998..366533c534 100644 --- a/TODO +++ b/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated November 19, 2016) +NuttX TODO List (Last updated November 22, 2016) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with -- GitLab From 7dbc25b02ba12a4e005e72ab42f4e60e0da36634 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Wed, 23 Nov 2016 13:33:51 -0600 Subject: [PATCH 496/734] LPC43xx: Add timer driver; configs/bambino-200e: Add support for timer driver --- arch/arm/src/lpc43xx/Kconfig | 10 +- arch/arm/src/lpc43xx/Make.defs | 6 +- arch/arm/src/lpc43xx/chip/lpc43_timer.h | 4 + arch/arm/src/lpc43xx/lpc43_timer.c | 771 +++++++++++++++++++++++ arch/arm/src/lpc43xx/lpc43_timer.h | 100 +++ configs/bambino-200e/nsh/defconfig | 16 +- configs/bambino-200e/src/Makefile | 4 + configs/bambino-200e/src/bambino-200e.h | 14 + configs/bambino-200e/src/lpc43_appinit.c | 10 +- configs/bambino-200e/src/lpc43_timer.c | 125 ++++ 10 files changed, 1054 insertions(+), 6 deletions(-) create mode 100644 arch/arm/src/lpc43xx/lpc43_timer.c create mode 100644 arch/arm/src/lpc43xx/lpc43_timer.h create mode 100644 configs/bambino-200e/src/lpc43_timer.c diff --git a/arch/arm/src/lpc43xx/Kconfig b/arch/arm/src/lpc43xx/Kconfig index c063fd86c7..b597090dca 100644 --- a/arch/arm/src/lpc43xx/Kconfig +++ b/arch/arm/src/lpc43xx/Kconfig @@ -269,8 +269,9 @@ config LPC43_SSP1 default n config LPC43_TMR0 - bool "ADC1" + bool "Timer 0" default n + select LPC43_TIMER config LPC43_TMR1 bool "Timer 1" @@ -279,10 +280,17 @@ config LPC43_TMR1 config LPC43_TMR2 bool "Timer 2" default n + select LPC43_TIMER config LPC43_TMR3 bool "Timer 3" default n + select LPC43_TIMER + +config LPC43_TIMER + bool + default n + select ARCH_HAVE_EXTCLK config LPC43_USART0 bool "USART0" diff --git a/arch/arm/src/lpc43xx/Make.defs b/arch/arm/src/lpc43xx/Make.defs index 79ddaa4a02..c0d95a2799 100644 --- a/arch/arm/src/lpc43xx/Make.defs +++ b/arch/arm/src/lpc43xx/Make.defs @@ -154,6 +154,10 @@ CHIP_CSRCS += lpc43_ssp.c endif endif +ifeq ($(CONFIG_LPC43_TIMER),y) +CHIP_CSRCS += lpc43_timer.c +endif + ifeq ($(CONFIG_LPC43_RIT),y) CHIP_CSRCS += lpc43_rit.c endif @@ -196,4 +200,4 @@ CHIP_CSRCS += lpc43_usb0dev.c endif endif --include chip/spifi/src/Make.defs \ No newline at end of file +-include chip/spifi/src/Make.defs diff --git a/arch/arm/src/lpc43xx/chip/lpc43_timer.h b/arch/arm/src/lpc43xx/chip/lpc43_timer.h index 109b8c8b7f..b62f1352a3 100644 --- a/arch/arm/src/lpc43xx/chip/lpc43_timer.h +++ b/arch/arm/src/lpc43xx/chip/lpc43_timer.h @@ -42,10 +42,14 @@ #include +#include "chip.h" + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ +#define TMR_RVALUE_MASK (0xffffffff) + /* Register offsets *****************************************************************/ #define LPC43_TMR_IR_OFFSET 0x0000 /* Interrupt Register */ diff --git a/arch/arm/src/lpc43xx/lpc43_timer.c b/arch/arm/src/lpc43xx/lpc43_timer.c new file mode 100644 index 0000000000..0d8b35c911 --- /dev/null +++ b/arch/arm/src/lpc43xx/lpc43_timer.c @@ -0,0 +1,771 @@ +/**************************************************************************** + * arch/arm/src/lpc43/lpc43_timer.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include +#include +#include + +#include +#include +#include + +#include "up_arch.h" +#include "lpc43_timer.h" + +#if defined(CONFIG_TIMER) && (defined(CONFIG_LPC43_TMR0) || \ + defined(CONFIG_LPC43_TMR1) || defined(CONFIG_LPC43_TMR2) || \ + defined(CONFIG_LPC43_TMR3) ) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +#ifndef CONFIG_DEBUG_TIMER_INFO +# undef CONFIG_LPC43_TMR_REGDEBUG +#endif + +/* Clocking *****************************************************************/ + +/* TODO: Allow selection of any of the input clocks */ + +#define TMR_FCLK (BOARD_FCLKOUT_FREQUENCY) +#define TMR_MAXTIMEOUT ((1000000ULL * (1ULL + TMR_RVALUE_MASK)) / TMR_FCLK) + +/**************************************************************************** + * Private Types + ****************************************************************************/ +/* This structure provides the private representation of the "lower-half" + * driver state structure. This structure must be cast-compatible with the + * timer_lowerhalf_s structure. + */ + +struct lpc43_lowerhalf_s +{ + FAR const struct timer_ops_s *ops; /* Lower half operations */ + + /* Private data */ + + uint32_t base; /* Base address of the timer */ + tccb_t callback; /* Current user interrupt callback */ + FAR void *arg; /* Argument passed to the callback function */ + uint32_t timeout; /* The current timeout value (us) */ + uint32_t adjustment; /* time lost due to clock resolution truncation (us) */ + uint32_t clkticks; /* actual clock ticks for current interval */ + bool started; /* The timer has been started */ + uint16_t tmrid; /* Timer id */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ +/* Register operations ******************************************************/ + +#ifdef CONFIG_LPC43_TMR_REGDEBUG +static uint32_t lpc43_getreg(uint32_t addr); +static void lpc43_putreg(uint32_t val, uint32_t addr); +#else +# define lpc43_getreg(addr) getreg32(addr) +# define lpc43_putreg(val,addr) putreg32(val,addr) +#endif + +/* Interrupt handling *******************************************************/ + +static int lpc43_interrupt(int irq, FAR void *context); + +/* "Lower half" driver methods **********************************************/ + +static int lpc43_start(FAR struct timer_lowerhalf_s *lower); +static int lpc43_stop(FAR struct timer_lowerhalf_s *lower); +static int lpc43_getstatus(FAR struct timer_lowerhalf_s *lower, + FAR struct timer_status_s *status); +static int lpc43_settimeout(FAR struct timer_lowerhalf_s *lower, + uint32_t timeout); +static void lpc43_setcallback(FAR struct timer_lowerhalf_s *lower, + tccb_t callback, FAR void *arg); +static int lpc43_ioctl(FAR struct timer_lowerhalf_s *lower, int cmd, + unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* "Lower half" driver methods */ + +static const struct timer_ops_s g_tmrops = +{ + .start = lpc43_start, + .stop = lpc43_stop, + .getstatus = lpc43_getstatus, + .settimeout = lpc43_settimeout, + .setcallback = lpc43_setcallback, + .ioctl = lpc43_ioctl, +}; + +/* "Lower half" driver state */ + +/* TODO - allocating all 6 now, even though we might not need them. + * May want to allocate the right number to not be wasteful. + */ + +static struct lpc43_lowerhalf_s g_tmrdevs[4]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc43_getreg + * + * Description: + * Get the contents of a register + * + ****************************************************************************/ + +#ifdef CONFIG_LPC43_TMR_REGDEBUG +static uint32_t lpc43_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t count = 0; + static uint32_t preval = 0; + + /* Read the value from the register */ + + uint32_t val = getreg32(addr); + + /* Is this the same value that we read from the same registe last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + tmrinfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + tmrinfo("[repeats %d more times]\n", count-3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + tmrinfo("%08lx->%08lx\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: lpc43_putreg + * + * Description: + * Set the contents of an LPC43 register to a value + * + ****************************************************************************/ + +#ifdef CONFIG_LPC43_TMR_REGDEBUG +static void lpc43_putreg(uint32_t val, uint32_t addr) +{ + /* Show the register value being written */ + + tmrinfo("%08lx<-%08lx\n", addr, val); + + /* Write the value */ + + putreg32(val, addr); +} +#endif + +void tmr_clk_enable(uint16_t tmrid) +{ + uint32_t regval; + + /* Enable Timer 0 */ + + if (tmrid == 0) + { + regval = getreg32(LPC43_CCU1_M4_TIMER0_CFG); + regval |= CCU_CLK_CFG_RUN; + putreg32(regval, LPC43_CCU1_M4_TIMER0_CFG); + } + + /* Enable Timer 1 */ + + if (tmrid == 1) + { + regval = getreg32(LPC43_CCU1_M4_TIMER1_CFG); + regval |= CCU_CLK_CFG_RUN; + putreg32(regval, LPC43_CCU1_M4_TIMER1_CFG); + } + + /* Enable Timer 2 */ + + if (tmrid == 2) + { + regval = getreg32(LPC43_CCU1_M4_TIMER2_CFG); + regval |= CCU_CLK_CFG_RUN; + putreg32(regval, LPC43_CCU1_M4_TIMER2_CFG); + } + + /* Enable Timer 3 */ + + if (tmrid == 3) + { + regval = getreg32(LPC43_CCU1_M4_TIMER3_CFG); + regval |= CCU_CLK_CFG_RUN; + putreg32(regval, LPC43_CCU1_M4_TIMER3_CFG); + } +} + +void tmr_clk_disable(uint16_t tmrid) +{ + uint32_t regval; + + /* Enable Timer 0 */ + + if (tmrid == 0) + { + regval = getreg32(LPC43_CCU1_M4_TIMER0_CFG); + regval &= ~CCU_CLK_CFG_RUN; + putreg32(regval, LPC43_CCU1_M4_TIMER0_CFG); + } + + /* Enable Timer 1 */ + + if (tmrid == 1) + { + regval = getreg32(LPC43_CCU1_M4_TIMER1_CFG); + regval &= ~CCU_CLK_CFG_RUN; + putreg32(regval, LPC43_CCU1_M4_TIMER1_CFG); + } + + /* Enable Timer 2 */ + + if (tmrid == 2) + { + regval = getreg32(LPC43_CCU1_M4_TIMER2_CFG); + regval &= ~CCU_CLK_CFG_RUN; + putreg32(regval, LPC43_CCU1_M4_TIMER2_CFG); + } + + /* Enable Timer 3 */ + + if (tmrid == 3) + { + regval = getreg32(LPC43_CCU1_M4_TIMER3_CFG); + regval &= ~CCU_CLK_CFG_RUN; + putreg32(regval, LPC43_CCU1_M4_TIMER3_CFG); + } +} + +/**************************************************************************** + * Name: lpc43_interrupt + * + * Description: + * TC interrupt + * + * Input Parameters: + * Usual interrupt callback arguments. + * + * Returned Values: + * Always returns OK. + * + ****************************************************************************/ + +static int lpc43_interrupt(int irq, FAR void *context) +{ + uint8_t chan_int = 0x0f; + FAR struct lpc43_lowerhalf_s *priv = &g_tmrdevs[irq-LPC43M4_IRQ_TIMER0]; + + tmrinfo("Entry\n"); + DEBUGASSERT((irq >= LPC43M4_IRQ_TIMER0) && (irq <= LPC43M4_IRQ_TIMER3)); + + /* Check if the interrupt is really pending */ + + if ((lpc43_getreg(priv->base + LPC43_TMR_IR_OFFSET) & chan_int) != 0) + { + uint32_t timeout; + + /* Is there a registered callback? If the callback has been + * nullified, the timer will be stopped. + */ + + if (priv->callback && priv->callback(&priv->timeout, priv->arg)) + { + /* Calculate new ticks / dither adjustment */ + + priv->clkticks =((uint64_t)(priv->adjustment + priv->timeout)) * + TMR_FCLK / 1000000; + + /* Set next interval interval. TODO: make sure the interval is not + * so soon it will be missed! + */ + + lpc43_putreg(priv->clkticks, priv->base + LPC43_TMR_PR_OFFSET); + + /* Truncated timeout */ + + timeout = (1000000ULL * priv->clkticks) / TMR_FCLK; + + /* Truncated time to be added to next interval (dither) */ + + priv->adjustment = (priv->adjustment + priv->timeout) - timeout; + } + else + { + /* No callback or the callback returned false.. stop the timer */ + + lpc43_stop((FAR struct timer_lowerhalf_s *)priv); + tmrinfo("Stopped\n"); + } + + /* Clear the interrupts */ + + lpc43_putreg(chan_int, priv->base + LPC43_TMR_IR_OFFSET); + } + + return OK; +} + +/**************************************************************************** + * Name: lpc43_start + * + * Description: + * Start the timer, resetting the time to the current timeout, + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int lpc43_start(FAR struct timer_lowerhalf_s *lower) +{ + FAR struct lpc43_lowerhalf_s *priv = (FAR struct lpc43_lowerhalf_s *)lower; + uint32_t presc_val; + + tmrinfo("Entry\n"); + DEBUGASSERT(priv); + + if (priv->started) + { + return -EINVAL; + } + + /* Enable timer clock */ + + tmr_clk_enable(priv->tmrid); + + /* Set it to Timer Mode */ + + lpc43_putreg(0, priv->base + LPC43_TMR_CTCR_OFFSET); + + /* Disable the timer */ + + lpc43_putreg(0, priv->base + LPC43_TMR_TCR_OFFSET); + + /* Set prescaler to increase TC each 1 us */ + + presc_val = TMR_FCLK / 1000000; + lpc43_putreg(presc_val - 1, priv->base + LPC43_TMR_PR_OFFSET); + + /* Set MR0 with a large enough initial value */ + + lpc43_putreg(10000000, priv->base + LPC43_TMR_MR0_OFFSET); + + if (priv->callback) + { + /* Enable Match on MR0 generate interrupt and auto-restart */ + + lpc43_putreg(3, priv->base + LPC43_TMR_MCR_OFFSET); + } + + /* Enable the timer */ + + lpc43_putreg(TMR_TCR_EN, priv->base + LPC43_TMR_TCR_OFFSET); + + priv->started = true; + return OK; +} + +/**************************************************************************** + * Name: lpc43_stop + * + * Description: + * Stop the timer + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int lpc43_stop(FAR struct timer_lowerhalf_s *lower) +{ + FAR struct lpc43_lowerhalf_s *priv = (FAR struct lpc43_lowerhalf_s *)lower; + tmrinfo("Entry\n"); + DEBUGASSERT(priv); + + if (!priv->started) + { + return -EINVAL; + } + + /* Disable timer */ + + lpc43_putreg(0, priv->base + LPC43_TMR_TCR_OFFSET); + + /* Disable interrupt */ + + lpc43_putreg(0, priv->base + LPC43_TMR_MCR_OFFSET); + + /* Disable timer clock */ + + tmr_clk_disable(priv->tmrid); + + priv->started = false; + + return OK; +} + +/**************************************************************************** + * Name: lpc43_getstatus + * + * Description: + * Get the current timer status + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower- + * half" driver state structure. + * status - The location to return the status information. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int lpc43_getstatus(FAR struct timer_lowerhalf_s *lower, + FAR struct timer_status_s *status) +{ + FAR struct lpc43_lowerhalf_s *priv = (FAR struct lpc43_lowerhalf_s *)lower; + uint32_t elapsed; + + tmrinfo("Entry\n"); + DEBUGASSERT(priv); + + /* Return the status bit */ + + status->flags = 0; + if (priv->started) + { + status->flags |= TCFLAGS_ACTIVE; + } + + if (priv->callback) + { + status->flags |= TCFLAGS_HANDLER; + } + + /* Return the actual timeout is milliseconds */ + + status->timeout = priv->timeout; + + /* Get the time remaining until the timer expires (in microseconds) */ + /* TODO - check on the +1 in the time left calculation */ + + elapsed = lpc43_getreg(priv->base + LPC43_TMR_TC_OFFSET); + status->timeleft = ((uint64_t)priv->timeout * elapsed) / + (priv->clkticks + 1); + + tmrinfo(" flags : %08x\n", status->flags); + tmrinfo(" timeout : %d\n", status->timeout); + tmrinfo(" timeleft : %d\n", status->timeleft); + return OK; +} + +/**************************************************************************** + * Name: lpc43_settimeout + * + * Description: + * Set a new timeout value (and reset the timer) + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower + * half" driver state structure. + * timeout - The new timeout value in milliseconds. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int lpc43_settimeout(FAR struct timer_lowerhalf_s *lower, + uint32_t timeout) +{ + FAR struct lpc43_lowerhalf_s *priv = (FAR struct lpc43_lowerhalf_s *)lower; + + DEBUGASSERT(priv); + + if (priv->started) + { + return -EPERM; + } + + tmrinfo("Entry: timeout=%d\n", timeout); + + /* Can this timeout be represented? */ + + if (timeout < 1 || timeout > TMR_MAXTIMEOUT) + { + tmrerr("ERROR: Cannot represent timeout=%lu > %lu\n", + timeout, TMR_MAXTIMEOUT); + return -ERANGE; + } + + /* Intended timeout */ + + priv->timeout = timeout; + + /* Actual clock ticks */ + + priv->clkticks = (((uint64_t)timeout * TMR_FCLK) / 1000000); + + /* Truncated timeout */ + + timeout = (1000000ULL * priv->clkticks) / TMR_FCLK; + + /* Truncated time to be added to next interval (dither) */ + + priv->adjustment = priv->timeout - timeout; + + tmrinfo("fclk=%d clkticks=%d timout=%d, adjustment=%d\n", + TMR_FCLK, priv->clkticks, priv->timeout, priv->adjustment); + + return OK; +} + +/**************************************************************************** + * Name: lpc43_setcallback + * + * Description: + * Call this user provided timeout callback. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * newcallback - The new timer expiration function pointer. If this + * function pointer is NULL, then the reset-on-expiration + * behavior is restored, + * + * Returned Values: + * The previous timer expiration function pointer or NULL is there was + * no previous function pointer. + * + ****************************************************************************/ + +static void lpc43_setcallback(FAR struct timer_lowerhalf_s *lower, + tccb_t callback, FAR void *arg) +{ + FAR struct lpc43_lowerhalf_s *priv = (FAR struct lpc43_lowerhalf_s *)lower; + irqstate_t flags; + + flags = enter_critical_section(); + + DEBUGASSERT(priv); + tmrinfo("Entry: callback=%p\n", callback); + + /* Save the new callback and its argument */ + + priv->callback = callback; + priv->arg = arg; + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: lpc43_ioctl + * + * Description: + * Any ioctl commands that are not recognized by the "upper-half" driver + * are forwarded to the lower half driver through this method. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * cmd - The ioctl command value + * arg - The optional argument that accompanies the 'cmd'. The + * interpretation of this argument depends on the particular + * command. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int lpc43_ioctl(FAR struct timer_lowerhalf_s *lower, int cmd, + unsigned long arg) +{ + FAR struct lpc43_lowerhalf_s *priv = (FAR struct lpc43_lowerhalf_s *)lower; + int ret = -ENOTTY; + + DEBUGASSERT(priv); + tmrinfo("Entry: cmd=%d arg=%ld\n", cmd, arg); + UNUSED(priv); + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc43_tmrinitialize + * + * Description: + * Initialize the timer. The timer is initialized and + * registers as 'devpath'. + * + * Input Parameters: + * devpath - The full path to the timer. This should be of the form + * /dev/tmr0 + * + * Returned Values: + * None + * + ****************************************************************************/ + +void lpc43_tmrinitialize(FAR const char *devpath, int irq) +{ + FAR struct lpc43_lowerhalf_s *priv = &g_tmrdevs[irq-LPC43M4_IRQ_TIMER0]; + + tmrinfo("Entry: devpath=%s\n", devpath); + DEBUGASSERT((irq >= LPC43M4_IRQ_TIMER0) && (irq <= LPC43M4_IRQ_TIMER3)); + + /* Initialize the driver state structure. Here we assume: (1) the state + * structure lies in .bss and was zeroed at reset time. (2) This function + * is only called once so it is never necessary to re-zero the structure. + */ + + switch (irq) + { +#if defined(CONFIG_LPC43_TMR0) + case LPC43M4_IRQ_TIMER0: + priv->base = LPC43_TIMER0_BASE; + priv->tmrid = 0; + tmrinfo("Using: Timer 0"); + break; +#endif + +#if defined(CONFIG_LPC43_TMR1) + case LPC43M4_IRQ_TIMER1: + priv->base = LPC43_TIMER1_BASE; + priv->tmrid = 1; + tmrinfo("Using: Timer 1"); + break; +#endif + +#if defined(CONFIG_LPC43_TMR2) + case LPC43M4_IRQ_TIMER2: + priv->base = LPC43_TIMER2_BASE; + priv->tmrid = 2; + tmrinfo("Using: Timer 2"); + break; +#endif + +#if defined(CONFIG_LPC43_TMR3) + case LPC43M4_IRQ_TIMER3: + priv->base = LPC43_TIMER3_BASE; + priv->tmrid = 3; + tmrinfo("Using: Timer 3"); + break; +#endif + + default: + ASSERT(0); + } + + priv->ops = &g_tmrops; + + (void)irq_attach(irq, lpc43_interrupt); + + /* Enable NVIC interrupt. */ + + up_enable_irq(irq); + + /* Register the timer driver as /dev/timerX */ + + (void)timer_register(devpath, (FAR struct timer_lowerhalf_s *)priv); +} + +#endif /* CONFIG_TIMER && CONFIG_LPC43_TMRx */ diff --git a/arch/arm/src/lpc43xx/lpc43_timer.h b/arch/arm/src/lpc43xx/lpc43_timer.h new file mode 100644 index 0000000000..194d917c31 --- /dev/null +++ b/arch/arm/src/lpc43xx/lpc43_timer.h @@ -0,0 +1,100 @@ +/**************************************************************************** + * arch/arm/src/sam34/lpc43_tc.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43_TMR_H +#define __ARCH_ARM_SRC_LPC43_TMR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "chip/lpc43_timer.h" +#include "chip/lpc43_ccu.h" + +#ifdef CONFIG_TIMER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc43_tmrinitialize + * + * Description: + * Initialize the timer. The timer is initialized and + * registers as 'devpath. The initial state of the timer is + * disabled. + * + * Input Parameters: + * devpath - The full path to the timer. This should be of the form + * /dev/timer0 + * irq - irq associated with the timer + * Returned Values: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_LPC43_TMR0) || defined(CONFIG_LPC43_TMR1) || \ + defined(CONFIG_LPC43_TMR2) || defined(CONFIG_LPC43_TMR3) +void lpc43_tmrinitialize(FAR const char *devpath, int irq); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_TIMER */ +#endif /* __ARCH_ARM_SRC_LPC43_TMR_H */ diff --git a/configs/bambino-200e/nsh/defconfig b/configs/bambino-200e/nsh/defconfig index 1593440d4b..ab5b2edc94 100644 --- a/configs/bambino-200e/nsh/defconfig +++ b/configs/bambino-200e/nsh/defconfig @@ -209,10 +209,11 @@ CONFIG_LPC43_BOOT_SPIFI=y # CONFIG_LPC43_SPIFI is not set # CONFIG_LPC43_SSP0 is not set # CONFIG_LPC43_SSP1 is not set -# CONFIG_LPC43_TMR0 is not set +CONFIG_LPC43_TMR0=y # CONFIG_LPC43_TMR1 is not set # CONFIG_LPC43_TMR2 is not set # CONFIG_LPC43_TMR3 is not set +CONFIG_LPC43_TIMER=y # CONFIG_LPC43_USART0 is not set CONFIG_LPC43_UART1=y # CONFIG_LPC43_USART2 is not set @@ -262,7 +263,7 @@ CONFIG_ARCH_HAVE_VFORK=y # CONFIG_ARCH_HAVE_MMU is not set CONFIG_ARCH_HAVE_MPU=y # CONFIG_ARCH_NAND_HWECC is not set -# CONFIG_ARCH_HAVE_EXTCLK is not set +CONFIG_ARCH_HAVE_EXTCLK=y # CONFIG_ARCH_HAVE_POWEROFF is not set CONFIG_ARCH_HAVE_RESET=y # CONFIG_ARCH_USE_MPU is not set @@ -350,6 +351,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_ARCH_HAVE_TICKLESS=y # CONFIG_SCHED_TICKLESS is not set CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEMTICK_EXTCLK is not set # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set # CONFIG_ARCH_HAVE_TIMEKEEPING is not set @@ -466,7 +468,7 @@ CONFIG_DEV_NULL=y # # Timer Driver Support # -# CONFIG_TIMER is not set +CONFIG_TIMER=y # CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set @@ -809,6 +811,14 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_TCPECHO is not set # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_TIFF is not set +CONFIG_EXAMPLES_TIMER=y +CONFIG_EXAMPLE_TIMER_DEVNAME="/dev/timer0" +CONFIG_EXAMPLE_TIMER_INTERVAL=1000000 +CONFIG_EXAMPLE_TIMER_DELAY=100000 +CONFIG_EXAMPLE_TIMER_NSAMPLES=20 +CONFIG_EXAMPLES_TIMER_APPNAME="timer" +CONFIG_EXAMPLES_TIMER_STACKSIZE=2048 +CONFIG_EXAMPLES_TIMER_PRIORITY=100 # CONFIG_EXAMPLES_TOUCHSCREEN is not set # CONFIG_EXAMPLES_USBSERIAL is not set # CONFIG_EXAMPLES_USBTERM is not set diff --git a/configs/bambino-200e/src/Makefile b/configs/bambino-200e/src/Makefile index fa49acd104..bb34f2be40 100644 --- a/configs/bambino-200e/src/Makefile +++ b/configs/bambino-200e/src/Makefile @@ -57,6 +57,10 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += lpc43_buttons.c endif +ifeq ($(CONFIG_TIMER),y) +CSRCS += lpc43_timer.c +endif + ifeq ($(CONFIG_USBMSC),y) CSRCS += lpc43_usbmsc.c endif diff --git a/configs/bambino-200e/src/bambino-200e.h b/configs/bambino-200e/src/bambino-200e.h index 2ec6d17479..9a0b856801 100644 --- a/configs/bambino-200e/src/bambino-200e.h +++ b/configs/bambino-200e/src/bambino-200e.h @@ -123,5 +123,19 @@ void weak_function lpc43_sspdev_initialize(void); +/************************************************************************************ + * Name: lpc43xx_timerinitialize() + * + * Description: + * Perform architecture-specific initialization of the timer hardware. + * + ************************************************************************************/ + +#ifdef CONFIG_TIMER +int lpc43_timerinitialize(void); +#else +# define lpc43_timerinitialize() (0) +#endif + #endif /* __ASSEMBLY__ */ #endif /* _CONFIGS_BAMBINO_200E_SRC_BAMBINO_H */ diff --git a/configs/bambino-200e/src/lpc43_appinit.c b/configs/bambino-200e/src/lpc43_appinit.c index eae609cf2e..13c51dfd81 100644 --- a/configs/bambino-200e/src/lpc43_appinit.c +++ b/configs/bambino-200e/src/lpc43_appinit.c @@ -162,5 +162,13 @@ int board_app_initialize(uintptr_t arg) { /* Initialize the SPIFI block device */ - return nsh_spifi_initialize(); + nsh_spifi_initialize(); + +#ifdef CONFIG_TIMER + /* Registers the timers */ + + lpc43_timerinitialize(); +#endif + + return 0; } diff --git a/configs/bambino-200e/src/lpc43_timer.c b/configs/bambino-200e/src/lpc43_timer.c new file mode 100644 index 0000000000..2efe5b2366 --- /dev/null +++ b/configs/bambino-200e/src/lpc43_timer.c @@ -0,0 +1,125 @@ +/**************************************************************************** + * configs/bambino-200e/src/lpc43_timer.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Bob Doiron + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include "lpc43_timer.h" + +#ifdef CONFIG_TIMER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +#if !(defined(CONFIG_LPC43_TMR0) || defined(CONFIG_LPC43_TMR1) || defined(CONFIG_LPC43_TMR2) \ + || defined(CONFIG_LPC43_TMR3) ) +# warning "CONFIG_LPC43_TMRx must be defined" +#endif + +/* Select the path to the registered watchdog timer device */ + +#ifndef CONFIG_TIMER0_DEVPATH +# define CONFIG_TIMER0_DEVPATH "/dev/timer0" +#endif +#ifndef CONFIG_TIMER1_DEVPATH +# define CONFIG_TIMER1_DEVPATH "/dev/timer1" +#endif +#ifndef CONFIG_TIMER2_DEVPATH +# define CONFIG_TIMER2_DEVPATH "/dev/timer2" +#endif +#ifndef CONFIG_TIMER3_DEVPATH +# define CONFIG_TIMER3_DEVPATH "/dev/timer3" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc43_timerinitialize() + * + * Description: + * Perform architecture-specific initialization of the timer hardware. + * + ****************************************************************************/ + +int lpc43_timerinitialize(void) +{ + /* Initialize and register the timer devices */ + +#if defined(CONFIG_LPC43_TMR0) + tmrinfo("Initializing %s...\n", CONFIG_TIMER0_DEVPATH); + lpc43_tmrinitialize(CONFIG_TIMER0_DEVPATH, LPC43M4_IRQ_TIMER0); +#endif + +#if defined(CONFIG_LPC43_TMR1) + tmrinfo("Initializing %s...\n", CONFIG_TIMER1_DEVPATH); + lpc43_tmrinitialize(CONFIG_TIMER1_DEVPATH, LPC43M4_IRQ_TIMER1); +#endif + +#if defined(CONFIG_LPC43_TMR2) + tmrinfo("Initializing %s...\n", CONFIG_TIMER2_DEVPATH); + lpc43_tmrinitialize(CONFIG_TIMER2_DEVPATH, LPC43M4_IRQ_TIMER2); +#endif + +#if defined(CONFIG_LPC43_TMR3) + tmrinfo("Initializing %s...\n", CONFIG_TIMER3_DEVPATH); + lpc43_tmrinitialize(CONFIG_TIMER3_DEVPATH, LPC43M4_IRQ_TIMER3); +#endif + + return OK; +} + +#endif /* CONFIG_TIMER */ -- GitLab From 7bec4ffeec677de1bf7c3608d4e1e472460c55f8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 23 Nov 2016 17:40:01 -0600 Subject: [PATCH 497/734] Update some comments --- sched/irq/irq_csection.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 96fb3abb1b..9f89e2d285 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -112,31 +112,32 @@ static inline void irq_waitlock(int cpu) while (up_testset(&g_cpu_irqlock) == SP_LOCKED) { - /* The deadlock condition would occur if CPUn: + /* A deadlock condition would occur if CPUn: * - * 1. Holds the g_cpu_irqlock, and - * 2. Is trying to interrupt CPUm + * 1. Holds the g_cpu_irqlock, and + * 2. Is trying to interrupt CPUm, but + * 3. CPUm is spinning trying acquaire the g_cpu_irqlock. * * The protocol for CPUn to pause CPUm is as follows * - * 1. The up_cpu_pause() implementation on CPUn locks both - * g_cpu_wait[m] and g_cpu_paused[m]. CPUn then waits - * spinning on g_cpu_wait[m]. - * 2. When CPUm receives the interrupt it (1) unlocks - * g_cpu_paused[m] and (2) locks g_cpu_wait[m]. The - * first unblocks CPUn and the second blocks CPUm in the - * interrupt handler. + * 1. The up_cpu_pause() implementation on CPUn locks both + * g_cpu_wait[m] and g_cpu_paused[m]. CPUn then waits + * spinning on g_cpu_wait[m]. + * 2. When CPUm receives the interrupt it (1) unlocks + * g_cpu_paused[m] and (2) locks g_cpu_wait[m]. The + * first unblocks CPUn and the second blocks CPUm in the + * interrupt handler. * * The problem in the deadlock case is that CPUm cannot receive - * the interrupt because it is locked up spinning. He we break + * the interrupt because it is locked up spinning. Here we break * the deadlock here be handling the pause interrupt request * while waiting. */ if (up_cpu_pausereq(cpu)) { - /* Yes.. some CPU is requesting to pause us! Handle the - * pause interrupt now. + /* Yes.. some other CPU is requesting to pause this CPU! Handle + * the pause interrupt now. */ DEBUGVERIFY(up_cpu_paused(cpu)); -- GitLab From 4b0bbf41ca9e2c6dbe3e3332437551a784dcb476 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 23 Nov 2016 22:24:14 -0600 Subject: [PATCH 498/734] SMP: Fix backward condition in test. --- arch/arm/src/armv7-a/arm_cpupause.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_cpupause.c b/arch/arm/src/armv7-a/arm_cpupause.c index 55ffbf9385..3b5b2039d2 100644 --- a/arch/arm/src/armv7-a/arm_cpupause.c +++ b/arch/arm/src/armv7-a/arm_cpupause.c @@ -188,10 +188,11 @@ int arm_pause_handler(int irq, FAR void *context) /* Check for false alarms. Such false could occur as a consequence of * some deadlock breaking logic that might have already serviced the SG2 - * interrupt by calling up_cpu_paused. + * interrupt by calling up_cpu_paused(). If the pause event has already + * been processed with g_cpu_paused[cpu] will not be locked. */ - if (spin_islocked(&g_cpu_paused[cpu])) + if (!spin_islocked(&g_cpu_paused[cpu])) { return up_cpu_paused(cpu); } -- GitLab From 19e7f2210efbd15b4ae943b0194a7ce84ec7a6bf Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 24 Nov 2016 04:24:40 +0000 Subject: [PATCH 499/734] arm_cpupause.c edited online with Bitbucket. Fix a typo in a comment. --- arch/arm/src/armv7-a/arm_cpupause.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/armv7-a/arm_cpupause.c b/arch/arm/src/armv7-a/arm_cpupause.c index 3b5b2039d2..1e7fca94c1 100644 --- a/arch/arm/src/armv7-a/arm_cpupause.c +++ b/arch/arm/src/armv7-a/arm_cpupause.c @@ -189,7 +189,7 @@ int arm_pause_handler(int irq, FAR void *context) /* Check for false alarms. Such false could occur as a consequence of * some deadlock breaking logic that might have already serviced the SG2 * interrupt by calling up_cpu_paused(). If the pause event has already - * been processed with g_cpu_paused[cpu] will not be locked. + * been processed then g_cpu_paused[cpu] will not be locked. */ if (!spin_islocked(&g_cpu_paused[cpu])) -- GitLab From c03d126da6e43b4934d9f29a1e83314ea451b2d0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 24 Nov 2016 04:45:07 +0000 Subject: [PATCH 500/734] arm_cpupause.c edited online with Bitbucke. What was I thinking... Back out previous change. --- arch/arm/src/armv7-a/arm_cpupause.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/armv7-a/arm_cpupause.c b/arch/arm/src/armv7-a/arm_cpupause.c index 1e7fca94c1..1b5726aba9 100644 --- a/arch/arm/src/armv7-a/arm_cpupause.c +++ b/arch/arm/src/armv7-a/arm_cpupause.c @@ -192,7 +192,7 @@ int arm_pause_handler(int irq, FAR void *context) * been processed then g_cpu_paused[cpu] will not be locked. */ - if (!spin_islocked(&g_cpu_paused[cpu])) + if (spin_islocked(&g_cpu_paused[cpu])) { return up_cpu_paused(cpu); } -- GitLab From eb9f8074c0dd9b05be0501ef1d24d85c7740c2bb Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 24 Nov 2016 09:56:12 -0600 Subject: [PATCH 501/734] Update comments --- sched/sched/sched_mergepending.c | 4 ++-- sched/sched/sched_removereadytorun.c | 16 +++++++++++----- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/sched/sched/sched_mergepending.c b/sched/sched/sched_mergepending.c index 07a554ff06..863eb73c27 100644 --- a/sched/sched/sched_mergepending.c +++ b/sched/sched/sched_mergepending.c @@ -271,11 +271,11 @@ bool sched_mergepending(void) return ret; } - cpu = sched_cpu_select(ALL_CPUS /* ptcb->affinity */); + cpu = sched_cpu_select(ALL_CPUS /* ptcb->affinity */); rtcb = current_task(cpu); } - /* No more pending tasks can be made running. Move any reamaining + /* No more pending tasks can be made running. Move any remaining * tasks in the pending task list to the ready-to-run task list. */ diff --git a/sched/sched/sched_removereadytorun.c b/sched/sched/sched_removereadytorun.c index 85c3d43fac..5b6b663d97 100644 --- a/sched/sched/sched_removereadytorun.c +++ b/sched/sched/sched_removereadytorun.c @@ -145,7 +145,7 @@ bool sched_removereadytorun(FAR struct tcb_s *rtcb) cpu = rtcb->cpu; tasklist = TLIST_HEAD(rtcb->task_state, cpu); - /* Check if the TCB to be removed is at the head of a ready to run list. + /* Check if the TCB to be removed is at the head of a ready-to-run list. * For the case of SMP, there are two lists involved: (1) the * g_readytorun list that holds non-running tasks that have not been * assigned to a CPU, and (2) and the g_assignedtasks[] lists which hold @@ -154,9 +154,12 @@ bool sched_removereadytorun(FAR struct tcb_s *rtcb) * only only removing the head of that list can result in a context * switch. * - * The tasklist RUNNABLE attribute will inform us if the list holds the - * currently executing and task and, hence, if a context switch could - * occur. + * rtcb->blink == NULL will tell us if the TCB is at the head of the + * ready-to-run list and, hence, a candidate for the new running task. + * + * If so, then the tasklist RUNNABLE attribute will inform us if the list + * holds the currently executing task and, hence, if a context switch + * should occur. */ if (rtcb->blink == NULL && TLIST_ISRUNNABLE(rtcb->task_state)) @@ -205,7 +208,10 @@ bool sched_removereadytorun(FAR struct tcb_s *rtcb) rtrtcb = (FAR struct tcb_s *)rtrtcb->flink); /* Did we find a task in the g_readytorun list? Which task should - * we use? We decide strictly by the priority of the two tasks. + * we use? We decide strictly by the priority of the two tasks: + * Either (1) the task currently at the head of the g_assignedtasks[cpu] + * list (nexttcb) or (2) the highest priority task from the + * g_readytorun list with matching affinity (rtrtcb). */ if (rtrtcb != NULL && rtrtcb->sched_priority >= nxttcb->sched_priority) -- GitLab From f77dcdf323ce0b41a32028bf621fa2aae9ed1f44 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 24 Nov 2016 11:45:05 -0600 Subject: [PATCH 502/734] ARMv7-A SMP: Add a little logic to signal handling. --- arch/arm/src/armv7-a/arm_schedulesigaction.c | 25 ++++++++++++++++++++ arch/arm/src/armv7-a/arm_sigdeliver.c | 12 +++++++--- 2 files changed, 34 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_schedulesigaction.c b/arch/arm/src/armv7-a/arm_schedulesigaction.c index 89df348ba0..c448a9a8a4 100644 --- a/arch/arm/src/armv7-a/arm_schedulesigaction.c +++ b/arch/arm/src/armv7-a/arm_schedulesigaction.c @@ -153,6 +153,18 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver; CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT); +#ifdef CONFIG_SMP + /* In an SMP configuration, the interrupt disable logic also + * involves spinlocks that are configured per the TCB irqcount + * field. This is logically equivalent to enter_critical_section(). + * The matching call to leave_critical_section() will be + * performed in up_sigdeliver(). + */ + + DEBUGASSERT(tcb->irqcount < INT16_MAX); + tcb->irqcount++; +#endif + /* And make sure that the saved context in the TCB is the same * as the interrupt return context. */ @@ -183,6 +195,19 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver; tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT); + +#ifdef CONFIG_SMP + /* In an SMP configuration, the interrupt disable logic also + * involves spinlocks that are configured per the TCB irqcount + * field. This is logically equivalent to enter_critical_section(); + * The matching leave_critical_section will be performed in + * The matching call to leave_critical_section() will be performed + * in up_sigdeliver(). + */ + + DEBUGASSERT(tcb->irqcount < INT16_MAX); + tcb->irqcount++; +#endif } } diff --git a/arch/arm/src/armv7-a/arm_sigdeliver.c b/arch/arm/src/armv7-a/arm_sigdeliver.c index be720a464c..672648a63a 100644 --- a/arch/arm/src/armv7-a/arm_sigdeliver.c +++ b/arch/arm/src/armv7-a/arm_sigdeliver.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/armv7-a/arm_sigdeliver.c * - * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -103,18 +103,24 @@ void up_sigdeliver(void) /* Then restore the task interrupt state */ - up_irq_restore(regs[REG_CPSR]); + leave_critical_section(regs[REG_CPSR]); - /* Deliver the signals */ + /* Deliver the signal */ sigdeliver(rtcb); /* Output any debug messages BEFORE restoring errno (because they may * alter errno), then disable interrupts again and restore the original * errno that is needed by the user logic (it is probably EINTR). + * + * REVISIT: In SMP mode up_irq_save() probably only disables interrupts + * on the local CPU. We do not want to call enter_critical_section() + * here, however, because we don't want this state to stick after the + * call to up_fullcontextrestore(). */ sinfo("Resuming\n"); + (void)up_irq_save(); rtcb->pterrno = saved_errno; -- GitLab From 7568aaf21316ab4ab334295a7e54e0a64a4865d6 Mon Sep 17 00:00:00 2001 From: Ramtin Amin Date: Thu, 24 Nov 2016 12:58:23 -0600 Subject: [PATCH 503/734] Misoc LM32: Add signal handling logic --- arch/misoc/include/lm32/irq.h | 35 +++- arch/misoc/src/lm32/Make.defs | 2 +- arch/misoc/src/lm32/lm32.h | 11 +- arch/misoc/src/lm32/lm32_initialstate.c | 2 +- arch/misoc/src/lm32/lm32_schedulesigaction.c | 207 +++++++++++++++++++ arch/misoc/src/lm32/lm32_sigdeliver.c | 136 ++++++++++++ arch/misoc/src/lm32/lm32_vectors.S | 7 +- configs/misoc/hello/defconfig | 64 ++++-- 8 files changed, 438 insertions(+), 26 deletions(-) create mode 100644 arch/misoc/src/lm32/lm32_schedulesigaction.c create mode 100644 arch/misoc/src/lm32/lm32_sigdeliver.c diff --git a/arch/misoc/include/lm32/irq.h b/arch/misoc/include/lm32/irq.h index 2e5e51e83a..57512bba88 100644 --- a/arch/misoc/include/lm32/irq.h +++ b/arch/misoc/include/lm32/irq.h @@ -195,11 +195,44 @@ struct xcptcontext { +#ifndef CONFIG_DISABLE_SIGNALS + /* The following function pointer is non-NULL if there are pending signals + * to be processed. + */ + + void *sigdeliver; /* Actual type is sig_deliver_t */ + + /* These additional register save locations are used to implement the + * signal delivery trampoline. + */ + + uint32_t saved_epc; /* Trampoline PC */ + uint32_t saved_int_ctx; /* Interrupt context with interrupts disabled. */ + +# ifdef CONFIG_BUILD_KERNEL + /* This is the saved address to use when returning from a user-space + * signal handler. + */ + + uint32_t sigreturn; + +# endif +#endif + +#ifdef CONFIG_BUILD_KERNEL + /* The following array holds information needed to return from each nested + * system call. + */ + + uint8_t nsyscalls; + struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST]; + +#endif + /* Register save area */ uint32_t regs[XCPTCONTEXT_REGS]; }; #endif /* __ASSEMBLY__ */ - #endif /* __ARCH_MISOC_INCLUDE_LM32_IRQ_H */ diff --git a/arch/misoc/src/lm32/Make.defs b/arch/misoc/src/lm32/Make.defs index 01a6702dcb..addffc5984 100644 --- a/arch/misoc/src/lm32/Make.defs +++ b/arch/misoc/src/lm32/Make.defs @@ -49,4 +49,4 @@ CHIP_CSRCS += lm32_doirq.c lm32_dumpstate.c lm32_exit.c lm32_idle.c CHIP_CSRCS += lm32_initialize.c lm32_initialstate.c lm32_interruptcontext.c CHIP_CSRCS += lm32_irq.c lm32_releasepending.c lm32_releasestack.c CHIP_CSRCS += lm32_stackframe.c lm32_swint.c lm32_unblocktask.c -CHIP_CSRCS += lm32_reprioritizertr.c +CHIP_CSRCS += lm32_reprioritizertr.c lm32_schedulesigaction.c lm32_sigdeliver.c diff --git a/arch/misoc/src/lm32/lm32.h b/arch/misoc/src/lm32/lm32.h index eac1fe7651..b23e60e4f2 100644 --- a/arch/misoc/src/lm32/lm32.h +++ b/arch/misoc/src/lm32/lm32.h @@ -57,16 +57,17 @@ * logic. */ -#define STACK_COLOR 0xdeadbeef -#define INTSTACK_COLOR 0xdeadbeef -#define HEAP_COLOR 'h' +#define STACK_COLOR 0xdeadbeef +#define INTSTACK_COLOR 0xdeadbeef +#define HEAP_COLOR 'h' /* In the LM32 model, the state is copied from the stack to the TCB, but * only a referenced is passed to get the state from the TCB. */ -#define up_savestate(regs) lm32_copystate(regs, (uint32_t*)g_current_regs) -#define up_restorestate(regs) (g_current_regs = regs) +#define up_savestate(regs) lm32_copystate(regs, (uint32_t*)g_current_regs) +#define up_copystate(rega,regb) lm32_copystate(rega, regb) +#define up_restorestate(regs) (g_current_regs = regs) /* Determine which (if any) console driver to use. If a console is enabled * and no other console device is specified, then a serial console is diff --git a/arch/misoc/src/lm32/lm32_initialstate.c b/arch/misoc/src/lm32/lm32_initialstate.c index 6064e186c8..f46d2aaf07 100644 --- a/arch/misoc/src/lm32/lm32_initialstate.c +++ b/arch/misoc/src/lm32/lm32_initialstate.c @@ -101,7 +101,7 @@ void up_initial_state(struct tcb_s *tcb) /* Initial state of IE: Interrupts enabled */ - xcp->regs[REG_INT_CTX] = 1; + xcp->regs[REG_INT_CTX] = 2; /* If this task is running PIC, then set the PIC base register to the * address of the allocated D-Space region. diff --git a/arch/misoc/src/lm32/lm32_schedulesigaction.c b/arch/misoc/src/lm32/lm32_schedulesigaction.c new file mode 100644 index 0000000000..15f06e0e77 --- /dev/null +++ b/arch/misoc/src/lm32/lm32_schedulesigaction.c @@ -0,0 +1,207 @@ +/**************************************************************************** + * arch/misoc/src/lm32/lm32_schedulesigaction.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Modified for MISOC: + * + * Copyright (C) 2016 Ramtin Amin. All rights reserved. + * Author: Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "sched/sched.h" +#include "lm32.h" + +#ifndef CONFIG_DISABLE_SIGNALS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_schedule_sigaction + * + * Description: + * This function is called by the OS when one or more + * signal handling actions have been queued for execution. + * The architecture specific code must configure things so + * that the 'igdeliver' callback is executed on the thread + * specified by 'tcb' as soon as possible. + * + * This function may be called from interrupt handling logic. + * + * This operation should not cause the task to be unblocked + * nor should it cause any immediate execution of sigdeliver. + * Typically, a few cases need to be considered: + * + * (1) This function may be called from an interrupt handler + * During interrupt processing, all xcptcontext structures + * should be valid for all tasks. That structure should + * be modified to invoke sigdeliver() either on return + * from (this) interrupt or on some subsequent context + * switch to the recipient task. + * (2) If not in an interrupt handler and the tcb is NOT + * the currently executing task, then again just modify + * the saved xcptcontext structure for the recipient + * task so it will invoke sigdeliver when that task is + * later resumed. + * (3) If not in an interrupt handler and the tcb IS the + * currently executing task -- just call the signal + * handler now. + * + ****************************************************************************/ + +void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) +{ + irqstate_t flags; + uint32_t int_ctx; + + sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver); + + /* Make sure that interrupts are disabled */ + + flags = enter_critical_section(); + + /* Refuse to handle nested signal actions */ + + if (!tcb->xcp.sigdeliver) + { + /* First, handle some special cases when the signal is + * being delivered to the currently executing task. + */ + + sinfo("rtcb=0x%p g_current_regs=0x%p\n", + this_task(), g_current_regs); + + if (tcb == this_task()) + { + /* CASE 1: We are not in an interrupt handler and + * a task is signalling itself for some reason. + */ + + if (!g_current_regs) + { + /* In this case just deliver the signal now. */ + + sigdeliver(tcb); + } + + /* CASE 2: We are in an interrupt handler AND the + * interrupted task is the same as the one that + * must receive the signal, then we will have to modify + * the return state as well as the state in the TCB. + * + * Hmmm... there looks like a latent bug here: The following + * logic would fail in the strange case where we are in an + * interrupt handler, the thread is signalling itself, but + * a context switch to another task has occurred so that + * g_current_regs does not refer to the thread of this_task()! + */ + + else + { + /* Save the return EPC and STATUS registers. These will be + * restored by the signal trampoline after the signals have + * been delivered. + */ + + tcb->xcp.sigdeliver = sigdeliver; + tcb->xcp.saved_epc = g_current_regs[REG_EPC]; + + /* Then set up to vector to the trampoline with interrupts + * disabled + */ + + g_current_regs[REG_EPC] = (uint32_t)up_sigdeliver; + g_current_regs[REG_INT_CTX] = 0; + + + /* And make sure that the saved context in the TCB + * is the same as the interrupt return context. + */ + + up_savestate(tcb->xcp.regs); + + sinfo("PC/STATUS Saved: %08x/%08x New: %08x/%08x\n", + tcb->xcp.saved_epc, tcb->xcp.saved_status, + g_current_regs[REG_EPC], g_current_regs[REG_STATUS]); + } + } + + /* Otherwise, we are (1) signaling a task is not running + * from an interrupt handler or (2) we are not in an + * interrupt handler and the running task is signalling + * some non-running task. + */ + + else + { + /* Save the return EPC and STATUS registers. These will be + * restored by the signal trampoline after the signals have + * been delivered. + */ + + tcb->xcp.sigdeliver = sigdeliver; + tcb->xcp.saved_epc = tcb->xcp.regs[REG_EPC]; + tcb->xcp.saved_int_ctx = tcb->xcp.regs[REG_INT_CTX]; + + /* Then set up to vector to the trampoline with interrupts + * disabled + */ + + tcb->xcp.regs[REG_EPC] = (uint32_t)up_sigdeliver; + tcb->xcp.regs[REG_INT_CTX] = 0; + + sinfo("PC/STATUS Saved: %08x/%08x New: %08x/%08x\n", + tcb->xcp.saved_epc, tcb->xcp.saved_status, + tcb->xcp.regs[REG_EPC], tcb->xcp.regs[REG_STATUS]); + } + } + + leave_critical_section(flags); +} + +#endif /* !CONFIG_DISABLE_SIGNALS */ diff --git a/arch/misoc/src/lm32/lm32_sigdeliver.c b/arch/misoc/src/lm32/lm32_sigdeliver.c new file mode 100644 index 0000000000..ce3378e57d --- /dev/null +++ b/arch/misoc/src/lm32/lm32_sigdeliver.c @@ -0,0 +1,136 @@ +/**************************************************************************** + * arch/misoc/src/lm32/lm32_sigdeliver.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "sched/sched.h" +#include "lm32.h" + +#ifndef CONFIG_DISABLE_SIGNALS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_sigdeliver + * + * Description: + * This is the a signal handling trampoline. When a signal action was + * posted. The task context was mucked with and forced to branch to this + * location with interrupts disabled. + * + ****************************************************************************/ + +void up_sigdeliver(void) +{ + struct tcb_s *rtcb = this_task(); + uint32_t regs[XCPTCONTEXT_REGS]; + sig_deliver_t sigdeliver; + + /* Save the errno. This must be preserved throughout the signal handling + * so that the user code final gets the correct errno value (probably + * EINTR). + */ + + int saved_errno = rtcb->pterrno; + + board_autoled_on(LED_SIGNAL); + + sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", + rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); + ASSERT(rtcb->xcp.sigdeliver != NULL); + + /* Save the real return state on the stack. */ + + up_copystate(regs, rtcb->xcp.regs); + regs[REG_EPC] = rtcb->xcp.saved_epc; + regs[REG_INT_CTX] = rtcb->xcp.saved_int_ctx; + + /* Get a local copy of the sigdeliver function pointer. We do this so that + * we can nullify the sigdeliver function pointer in the TCB and accept + * more signal deliveries while processing the current pending signals. + */ + + sigdeliver = rtcb->xcp.sigdeliver; + rtcb->xcp.sigdeliver = NULL; + + /* Then restore the task interrupt state */ + + up_irq_restore((irqstate_t)regs[REG_INT_CTX]); + + /* Deliver the signals */ + + sigdeliver(rtcb); + + /* Output any debug messages BEFORE restoring errno (because they may + * alter errno), then disable interrupts again and restore the original + * errno that is needed by the user logic (it is probably EINTR). + */ + + sinfo("Resuming EPC: %08x INT_CTX: %08x\n", regs[REG_EPC], regs[REG_INT_CTX]); + + (void)up_irq_save(); + rtcb->pterrno = saved_errno; + + /* Then restore the correct state for this thread of + * execution. + */ + + board_autoled_off(LED_SIGNAL); + up_fullcontextrestore(regs); + + /* up_fullcontextrestore() should not return but could if the software + * interrupts are disabled. + */ + + PANIC(); +} + +#endif /* !CONFIG_DISABLE_SIGNALS */ diff --git a/arch/misoc/src/lm32/lm32_vectors.S b/arch/misoc/src/lm32/lm32_vectors.S index 4cc83a3919..45407f0db7 100644 --- a/arch/misoc/src/lm32/lm32_vectors.S +++ b/arch/misoc/src/lm32/lm32_vectors.S @@ -208,7 +208,6 @@ _do_reset: sw (sp+REG_X23), r23 sw (sp+REG_X24), r24 sw (sp+REG_X25), r25 - sw (sp+REG_GP), r26 sw (sp+REG_FP), r27 @@ -217,7 +216,7 @@ _do_reset: addi r1, sp, 136 sw (sp+REG_SP), r1 - /* reg RA done later */ + /* Reg RA done later */ sw (sp+REG_EA), r30 sw (sp+REG_BA), r31 @@ -235,6 +234,10 @@ _do_reset: /* The 2nd argument is the regs pointer */ addi r2, sp, 0 + + /* Move sp away from X0 */ + + addi sp, sp, -4 ret .restore_all_and_eret: diff --git a/configs/misoc/hello/defconfig b/configs/misoc/hello/defconfig index 71aea364a7..0fd2918d18 100644 --- a/configs/misoc/hello/defconfig +++ b/configs/misoc/hello/defconfig @@ -162,7 +162,7 @@ CONFIG_BOOT_RUNFROMFLASH=y # Boot Memory Configuration # CONFIG_RAM_START=0x40000000 -CONFIG_RAM_SIZE=524288 +CONFIG_RAM_SIZE=67108864 # CONFIG_ARCH_HAVE_SDRAM is not set # @@ -192,12 +192,7 @@ CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y # # RTOS Features # -CONFIG_DISABLE_OS_API=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_DISABLE_SIGNALS=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_ENVIRON=y +# CONFIG_DISABLE_OS_API is not set # # Clocks and Timers @@ -222,12 +217,18 @@ CONFIG_PREALLOC_TIMERS=0 CONFIG_INIT_ENTRYPOINT=y # CONFIG_INIT_FILEPATH is not set CONFIG_USER_ENTRYPOINT="nsh_main" -CONFIG_RR_INTERVAL=0 +CONFIG_RR_INTERVAL=200 # CONFIG_SCHED_SPORADIC is not set CONFIG_TASK_NAME_SIZE=0 -CONFIG_MAX_TASKS=4 +CONFIG_MAX_TASKS=16 # CONFIG_SCHED_HAVE_PARENT is not set -# CONFIG_SCHED_WAITPID is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 # # Performance Monitoring @@ -254,19 +255,36 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=32 +CONFIG_MQ_MAXMSGSIZE=32 # CONFIG_MODULE is not set # # Work queue support # +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_HPWORK is not set +# CONFIG_SCHED_LPWORK is not set # # Stack and heap information # -CONFIG_IDLETHREAD_STACKSIZE=1024 -CONFIG_USERMAIN_STACKSIZE=1024 -CONFIG_PTHREAD_STACK_MIN=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 # CONFIG_LIB_SYSCALL is not set # @@ -431,7 +449,9 @@ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y # CONFIG_FS_READABLE is not set # CONFIG_FS_WRITABLE is not set # CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" # CONFIG_FS_RAMMAP is not set +# CONFIG_FS_BINFS is not set # CONFIG_FS_PROCFS is not set # CONFIG_FS_UNIONFS is not set @@ -461,9 +481,10 @@ CONFIG_MM_REGIONS=1 # Binary Loader # # CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set # CONFIG_NXFLAT is not set # CONFIG_ELF is not set -# CONFIG_BUILTIN is not set +CONFIG_BUILTIN=y # CONFIG_PIC is not set # CONFIG_SYMTAB_ORDEREDBYNAME is not set @@ -477,6 +498,7 @@ CONFIG_MM_REGIONS=1 CONFIG_STDIO_BUFFER_SIZE=0 CONFIG_STDIO_LINEBUFFER=y CONFIG_NUNGET_CHARS=0 +CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBM is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set # CONFIG_LIBC_FLOATINGPOINT is not set @@ -495,6 +517,7 @@ CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 # CONFIG_LIBC_STRERROR is not set # CONFIG_LIBC_PERROR_STDOUT is not set CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set # CONFIG_TIME_EXTENDED is not set CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_ARCH_ROMGETC is not set @@ -520,6 +543,11 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # Application Configuration # +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + # # CAN Utilities # @@ -548,10 +576,10 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 # CONFIG_EXAMPLES_NRF24L01TERM is not set CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set @@ -561,6 +589,7 @@ CONFIG_EXAMPLES_OSTEST_STACKSIZE=8192 CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=8 CONFIG_EXAMPLES_OSTEST_RR_RANGE=10000 CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 +CONFIG_EXAMPLES_OSTEST_WAITRESULT=y # CONFIG_EXAMPLES_PCA9635 is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set @@ -573,6 +602,7 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_EXAMPLES_SERLOOP is not set # CONFIG_EXAMPLES_SLCD is not set # CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set # CONFIG_EXAMPLES_SMP is not set # CONFIG_EXAMPLES_TCPECHO is not set # CONFIG_EXAMPLES_TELNETD is not set @@ -637,6 +667,7 @@ CONFIG_NSH_MAXARGUMENTS=6 CONFIG_NSH_ARGCAT=y CONFIG_NSH_NESTDEPTH=3 # CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_BUILTIN_APPS=y # # Disable Individual commands @@ -741,6 +772,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set # CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set -- GitLab From 7f636f2280fe81d94df5b04de37da454c668f92a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 24 Nov 2016 13:33:43 -0600 Subject: [PATCH 504/734] SMP: Add spin_trylock(). Use this in conditions where other CPUs need to stopped but we cannot call enter_critical_section. --- arch/arm/src/armv7-a/arm_assert.c | 5 +++++ arch/arm/src/armv7-a/arm_sigdeliver.c | 3 +++ arch/arm/src/common/up_exit.c | 9 ++++++--- configs/sabre-6quad/README.txt | 5 ----- include/nuttx/spinlock.h | 21 +++++++++++++++++++++ 5 files changed, 35 insertions(+), 8 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_assert.c b/arch/arm/src/armv7-a/arm_assert.c index 3c798d33a0..c6742d2a6a 100644 --- a/arch/arm/src/armv7-a/arm_assert.c +++ b/arch/arm/src/armv7-a/arm_assert.c @@ -53,6 +53,7 @@ #include "up_arch.h" #include "sched/sched.h" +#include "irq/irq.h" #include "up_internal.h" /**************************************************************************** @@ -346,6 +347,10 @@ static void _up_assert(int errorcode) if (CURRENT_REGS || this_task()->pid == 0) { (void)up_irq_save(); +#ifdef SMP + (void)spin_trylock(&g_cpu_irqlock); +#endif + for (; ; ) { #ifdef CONFIG_ARCH_LEDS diff --git a/arch/arm/src/armv7-a/arm_sigdeliver.c b/arch/arm/src/armv7-a/arm_sigdeliver.c index 672648a63a..5d89583282 100644 --- a/arch/arm/src/armv7-a/arm_sigdeliver.c +++ b/arch/arm/src/armv7-a/arm_sigdeliver.c @@ -117,6 +117,9 @@ void up_sigdeliver(void) * on the local CPU. We do not want to call enter_critical_section() * here, however, because we don't want this state to stick after the * call to up_fullcontextrestore(). + * + * I would prefer that all interrupts are disabled when + * up_fullcontextrestore() is called, but that may not be necessary. */ sinfo("Resuming\n"); diff --git a/arch/arm/src/common/up_exit.c b/arch/arm/src/common/up_exit.c index 4d16f2a8a5..ec5a88498b 100644 --- a/arch/arm/src/common/up_exit.c +++ b/arch/arm/src/common/up_exit.c @@ -50,6 +50,7 @@ #include "task/task.h" #include "sched/sched.h" #include "group/group.h" +#include "irq/irq.h" #include "up_internal.h" /**************************************************************************** @@ -140,11 +141,14 @@ void _exit(int status) { struct tcb_s *tcb; - /* Disable interrupts. They will be restored when the next - * task is started. + /* Disable interrupts. They will be restored when the next task is + * started. */ (void)up_irq_save(); +#ifdef SMP + (void)spin_trylock(&g_cpu_irqlock); +#endif sinfo("TCB=%p exiting\n", this_task()); @@ -177,4 +181,3 @@ void _exit(int status) up_fullcontextrestore(tcb->xcp.regs); } - diff --git a/configs/sabre-6quad/README.txt b/configs/sabre-6quad/README.txt index ec41ee6271..c7d7fc57c7 100644 --- a/configs/sabre-6quad/README.txt +++ b/configs/sabre-6quad/README.txt @@ -555,11 +555,6 @@ Open Issues: Update: Cache inconsistencies seem to be the root cause of all current SMP issues. -5. Assertions. On a fatal assertions, other CPUs need to be stopped. The SCR, - however, only supports disabling CPUs 1 through 3. Perhaps if the assertion - occurs on CPUn, n > 0, then it should use and SGI to perform the assertion - on CPU0 always. From CPU0, CPU1-3 can be disabled. - Configurations ============== diff --git a/include/nuttx/spinlock.h b/include/nuttx/spinlock.h index 1ad7fef525..ee6bf65b64 100644 --- a/include/nuttx/spinlock.h +++ b/include/nuttx/spinlock.h @@ -179,6 +179,27 @@ void spin_initializer(FAR struct spinlock_s *lock); void spin_lock(FAR volatile spinlock_t *lock); +/**************************************************************************** + * Name: spin_trylock + * + * Description: + * Try once to lock the spinlock. Do not wait if the spinlock is already + * locked. + * + * Input Parameters: + * lock - A reference to the spinlock object to lock. + * + * Returned Value: + * SP_LOCKED - Failure, the spinlock was already locked + * SP_UNLOCKED - Success, the spinlock was successfully locked + * + * Assumptions: + * Not running at the interrupt level. + * + ****************************************************************************/ + +#define spin_trylock(l) up_testset(l) + /**************************************************************************** * Name: spin_lockr * -- GitLab From b08fb33c282d1b4470648ee1afe032ad754bf287 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 24 Nov 2016 17:59:45 -0600 Subject: [PATCH 505/734] SMP: Fix typos in some conditional compilation --- arch/arm/src/armv7-a/arm_assert.c | 13 ++++++++++--- arch/arm/src/common/up_exit.c | 2 +- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_assert.c b/arch/arm/src/armv7-a/arm_assert.c index c6742d2a6a..72952e0cfa 100644 --- a/arch/arm/src/armv7-a/arm_assert.c +++ b/arch/arm/src/armv7-a/arm_assert.c @@ -346,14 +346,21 @@ static void _up_assert(int errorcode) if (CURRENT_REGS || this_task()->pid == 0) { + /* Disable interrupts on this CPU */ + (void)up_irq_save(); -#ifdef SMP - (void)spin_trylock(&g_cpu_irqlock); -#endif for (; ; ) { +#ifdef CONFIG_SMP + /* Try (again) to stop activity on other CPUs */ + + (void)spin_trylock(&g_cpu_irqlock); +#endif + #ifdef CONFIG_ARCH_LEDS + /* FLASH LEDs a 2Hz */ + board_autoled_on(LED_PANIC); up_mdelay(250); board_autoled_off(LED_PANIC); diff --git a/arch/arm/src/common/up_exit.c b/arch/arm/src/common/up_exit.c index ec5a88498b..50ff85a743 100644 --- a/arch/arm/src/common/up_exit.c +++ b/arch/arm/src/common/up_exit.c @@ -146,7 +146,7 @@ void _exit(int status) */ (void)up_irq_save(); -#ifdef SMP +#ifdef CONFIG_SMP (void)spin_trylock(&g_cpu_irqlock); #endif -- GitLab From 0d0b1b64e2f4a3a48a47024b23160fa3b120651d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Maciej=20W=C3=B3jcik?= Date: Fri, 25 Nov 2016 06:17:18 +0100 Subject: [PATCH 506/734] Fix for F1 RTC Clock, tested on F103 --- arch/arm/src/stm32/stm32_rtcounter.c | 13 ++++++------- arch/arm/src/stm32/stm32f10xxx_rcc.c | 14 ++++++++------ 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/arch/arm/src/stm32/stm32_rtcounter.c b/arch/arm/src/stm32/stm32_rtcounter.c index 137e7344a0..1c90be9c14 100644 --- a/arch/arm/src/stm32/stm32_rtcounter.c +++ b/arch/arm/src/stm32/stm32_rtcounter.c @@ -378,13 +378,12 @@ int up_rtc_initialize(void) */ stm32_pwr_enablebkp(true); - - /* Set access to the peripheral, enable the backup domain (BKP) and the lower - * power external 32,768Hz (Low-Speed External, LSE) oscillator. Configure the - * LSE to drive the RTC. - */ - - stm32_rcc_enablelse(); + + /* Select the lower power external 32,768Hz (Low-Speed External, LSE) oscillator + * as RTC Clock Source and enable the Clock */ + + modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); + modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN); /* TODO: Get state from this function, if everything is * okay and whether it is already enabled (if it was disabled diff --git a/arch/arm/src/stm32/stm32f10xxx_rcc.c b/arch/arm/src/stm32/stm32f10xxx_rcc.c index 736b3ee7ef..218e534e22 100644 --- a/arch/arm/src/stm32/stm32f10xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f10xxx_rcc.c @@ -756,12 +756,6 @@ static void stm32_stdclockconfig(void) stm32_rcc_enablelsi(); #endif - -#if defined(CONFIG_RTC_LSECLOCK) - /* Low speed external clock source LSE */ - - stm32_rcc_enablelse(); -#endif } #endif @@ -774,6 +768,14 @@ static inline void rcc_enableperipherals(void) rcc_enableahb(); rcc_enableapb2(); rcc_enableapb1(); + +#if defined(CONFIG_RTC_LSECLOCK) + /* Low speed external clock source LSE + * For F1 it requires PWR and BKP from APB1 + */ + + stm32_rcc_enablelse(); +#endif } /**************************************************************************** -- GitLab From 5aeb4fb844f673499672db65964622fea1acb3f6 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 25 Nov 2016 10:55:48 -0600 Subject: [PATCH 507/734] Update all STM3210E-EVAL configurations --- configs/stm3210e-eval/composite/defconfig | 20 ++++++++++++++++++++ configs/stm3210e-eval/nsh/defconfig | 21 +++++++++++++++++++++ configs/stm3210e-eval/nsh2/defconfig | 23 +++++++++++++++++++++++ configs/stm3210e-eval/nxterm/defconfig | 21 +++++++++++++++++++++ configs/stm3210e-eval/pm/defconfig | 11 +++++++++++ configs/stm3210e-eval/usbmsc/defconfig | 19 +++++++++++++++++++ configs/stm3210e-eval/usbserial/defconfig | 19 +++++++++++++++++++ 7 files changed, 134 insertions(+) diff --git a/configs/stm3210e-eval/composite/defconfig b/configs/stm3210e-eval/composite/defconfig index 44e2d6e39d..a1a7799488 100644 --- a/configs/stm3210e-eval/composite/defconfig +++ b/configs/stm3210e-eval/composite/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -359,6 +362,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y # CONFIG_STM32_HAVE_CAN2 is not set CONFIG_STM32_HAVE_DAC1=y @@ -708,6 +717,8 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -715,6 +726,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -778,6 +790,7 @@ CONFIG_MTD=y # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -931,6 +944,7 @@ CONFIG_USBMSC_SCSI_STACKSIZE=2048 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1030,6 +1044,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1078,6 +1094,8 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1151,6 +1169,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1207,6 +1226,7 @@ CONFIG_SYSTEM_COMPOSITE_BUFSIZE=256 # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_USBMSC is not set # CONFIG_SYSTEM_VI is not set diff --git a/configs/stm3210e-eval/nsh/defconfig b/configs/stm3210e-eval/nsh/defconfig index 0621482063..b8896ddace 100644 --- a/configs/stm3210e-eval/nsh/defconfig +++ b/configs/stm3210e-eval/nsh/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -360,6 +363,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y # CONFIG_STM32_HAVE_CAN2 is not set CONFIG_STM32_HAVE_DAC1=y @@ -709,6 +718,8 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -716,6 +727,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -779,6 +791,7 @@ CONFIG_MTD=y # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -882,6 +895,7 @@ CONFIG_USBDEV_MAXPOWER=100 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -987,6 +1001,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1035,6 +1051,8 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1108,6 +1126,7 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1178,6 +1197,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1246,6 +1266,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3210e-eval/nsh2/defconfig b/configs/stm3210e-eval/nsh2/defconfig index b0e7ea89b8..741db60bb0 100644 --- a/configs/stm3210e-eval/nsh2/defconfig +++ b/configs/stm3210e-eval/nsh2/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -359,6 +362,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y # CONFIG_STM32_HAVE_CAN2 is not set CONFIG_STM32_HAVE_DAC1=y @@ -730,6 +739,8 @@ CONFIG_I2C_POLLED=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -737,6 +748,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_TIMERS_CS2100CP is not set @@ -772,6 +784,7 @@ CONFIG_LCD_MAXPOWER=1 # CONFIG_LCD_NOKIA6100 is not set # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -831,6 +844,7 @@ CONFIG_MTD=y # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -949,6 +963,7 @@ CONFIG_USBMSC_SCSI_STACKSIZE=2048 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1145,6 +1160,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1198,6 +1215,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1304,6 +1323,7 @@ CONFIG_EXAMPLES_NXHELLO_FONTID=6 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1375,6 +1395,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1451,6 +1472,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set CONFIG_SYSTEM_USBMSC=y CONFIG_SYSTEM_USBMSC_NLUNS=1 diff --git a/configs/stm3210e-eval/nxterm/defconfig b/configs/stm3210e-eval/nxterm/defconfig index fc61e8932b..2733e516ea 100644 --- a/configs/stm3210e-eval/nxterm/defconfig +++ b/configs/stm3210e-eval/nxterm/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -357,6 +360,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y # CONFIG_STM32_HAVE_CAN2 is not set CONFIG_STM32_HAVE_DAC1=y @@ -705,6 +714,8 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -712,6 +723,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -746,6 +758,7 @@ CONFIG_LCD_MAXPOWER=1 # CONFIG_LCD_NOKIA6100 is not set # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -846,6 +859,7 @@ CONFIG_USART2_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1056,6 +1070,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1106,6 +1122,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1177,6 +1195,7 @@ CONFIG_EXAMPLES_NXTERM=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1247,6 +1266,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1314,6 +1334,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3210e-eval/pm/defconfig b/configs/stm3210e-eval/pm/defconfig index 86003dfefc..94684ad13d 100644 --- a/configs/stm3210e-eval/pm/defconfig +++ b/configs/stm3210e-eval/pm/defconfig @@ -65,11 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -358,6 +360,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y # CONFIG_STM32_HAVE_CAN2 is not set CONFIG_STM32_HAVE_DAC1=y @@ -723,6 +731,8 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -1134,6 +1144,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # Examples # # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set diff --git a/configs/stm3210e-eval/usbmsc/defconfig b/configs/stm3210e-eval/usbmsc/defconfig index 9695318a73..9cea76f73f 100644 --- a/configs/stm3210e-eval/usbmsc/defconfig +++ b/configs/stm3210e-eval/usbmsc/defconfig @@ -61,10 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -352,6 +355,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y # CONFIG_STM32_HAVE_CAN2 is not set CONFIG_STM32_HAVE_DAC1=y @@ -701,6 +710,8 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -708,6 +719,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -859,6 +871,7 @@ CONFIG_USBMSC_SCSI_STACKSIZE=2048 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -958,6 +971,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1006,6 +1021,8 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1078,6 +1095,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1121,6 +1139,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set CONFIG_SYSTEM_USBMSC=y CONFIG_SYSTEM_USBMSC_NLUNS=1 diff --git a/configs/stm3210e-eval/usbserial/defconfig b/configs/stm3210e-eval/usbserial/defconfig index f90c876dd3..20c1fba098 100644 --- a/configs/stm3210e-eval/usbserial/defconfig +++ b/configs/stm3210e-eval/usbserial/defconfig @@ -61,10 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -350,6 +353,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y # CONFIG_STM32_HAVE_CAN2 is not set CONFIG_STM32_HAVE_DAC1=y @@ -688,6 +697,8 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -695,6 +706,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -833,6 +845,7 @@ CONFIG_PL2303_PRODUCTSTR="USBdev Serial" # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -926,6 +939,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -971,6 +986,8 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1041,6 +1058,7 @@ CONFIG_EXAMPLES_USBSERIAL_BUFSIZE=512 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1084,6 +1102,7 @@ CONFIG_EXAMPLES_USBSERIAL_BUFSIZE=512 # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set -- GitLab From c1082b283cd03a239757eb074a4ffb6d3244b2da Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Maciej=20W=C3=B3jcik?= Date: Sat, 26 Nov 2016 01:15:47 +0100 Subject: [PATCH 508/734] refresh config --- configs/hymini-stm32v/nsh2/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configs/hymini-stm32v/nsh2/defconfig b/configs/hymini-stm32v/nsh2/defconfig index 5777261820..c36a43d47f 100644 --- a/configs/hymini-stm32v/nsh2/defconfig +++ b/configs/hymini-stm32v/nsh2/defconfig @@ -1459,3 +1459,7 @@ CONFIG_SYSTEM_USBMSC_CMD_STACKSIZE=768 CONFIG_SYSTEM_USBMSC_CMD_PRIORITY=100 # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set + +# Application configuration + +CONFIG_APPS_DIR="../apps" -- GitLab From 91df4876228edd1665a0cb64116fd56199667500 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Maciej=20W=C3=B3jcik?= Date: Sat, 26 Nov 2016 01:17:22 +0100 Subject: [PATCH 509/734] add rtc back --- configs/hymini-stm32v/nsh2/defconfig | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/configs/hymini-stm32v/nsh2/defconfig b/configs/hymini-stm32v/nsh2/defconfig index c36a43d47f..887afa3ef9 100644 --- a/configs/hymini-stm32v/nsh2/defconfig +++ b/configs/hymini-stm32v/nsh2/defconfig @@ -16,7 +16,7 @@ CONFIG_HOST_LINUX=y # # Build Configuration # -# CONFIG_APPS_DIR="../apps" +CONFIG_APPS_DIR="../apps" CONFIG_BUILD_FLAT=y # CONFIG_BUILD_2PASS is not set @@ -475,6 +475,9 @@ CONFIG_STM32_USART1_SERIALDRIVER=y CONFIG_SDIO_DMAPRIO=0x00001000 CONFIG_STM32_HAVE_RTC_COUNTER=y # CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set +CONFIG_RTC_LSECLOCK=y +# CONFIG_RTC_LSICLOCK is not set +# CONFIG_RTC_HSECLOCK is not set # # USB FS Host Configuration @@ -603,9 +606,6 @@ CONFIG_USEC_PER_TICK=10000 # CONFIG_CLOCK_MONOTONIC is not set CONFIG_ARCH_HAVE_TIMEKEEPING=y # CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2016 -CONFIG_START_MONTH=7 -CONFIG_START_DAY=28 CONFIG_MAX_WDOGPARMS=2 CONFIG_PREALLOC_WDOGS=8 CONFIG_WDOG_INTRESERVE=1 @@ -734,7 +734,12 @@ CONFIG_SPI_EXCHANGE=y # # CONFIG_TIMER is not set # CONFIG_ONESHOT is not set -# CONFIG_RTC is not set +CONFIG_RTC=y +# CONFIG_RTC_DATETIME is not set +# CONFIG_RTC_HIRES is not set +# CONFIG_RTC_ALARM is not set +# CONFIG_RTC_DRIVER is not set +# CONFIG_RTC_EXTERNAL is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set # CONFIG_AUDIO_DEVICES is not set @@ -1166,6 +1171,10 @@ CONFIG_ARCH_HAVE_TLS=y # Application Configuration # +# +# NxWidgets/NxWM +# + # # Built-In Applications # @@ -1418,10 +1427,6 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_NSH_LOGIN is not set # CONFIG_NSH_CONSOLE_LOGIN is not set -# -# NxWidgets/NxWM -# - # # Platform-specific Support # @@ -1459,7 +1464,3 @@ CONFIG_SYSTEM_USBMSC_CMD_STACKSIZE=768 CONFIG_SYSTEM_USBMSC_CMD_PRIORITY=100 # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set - -# Application configuration - -CONFIG_APPS_DIR="../apps" -- GitLab From a0e1af26142cce09a5c6aa4976d9ab627b04089d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 25 Nov 2016 23:04:27 -0600 Subject: [PATCH 510/734] SMP: Fix yet another potential deadlock --- sched/irq/irq_csection.c | 75 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 70 insertions(+), 5 deletions(-) diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 9f89e2d285..1b8ba44d0b 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -110,13 +110,13 @@ static inline void irq_waitlock(int cpu) * for the deadlock condition. */ - while (up_testset(&g_cpu_irqlock) == SP_LOCKED) + while (spin_trylock(&g_cpu_irqlock) == SP_LOCKED) { /* A deadlock condition would occur if CPUn: * * 1. Holds the g_cpu_irqlock, and * 2. Is trying to interrupt CPUm, but - * 3. CPUm is spinning trying acquaire the g_cpu_irqlock. + * 3. CPUm is spinning trying acquire the g_cpu_irqlock. * * The protocol for CPUn to pause CPUm is as follows * @@ -152,6 +152,57 @@ static inline void irq_waitlock(int cpu) } #endif +/**************************************************************************** + * Name: task_waitlock + * + * Description: + * Spin to get g_irq_waitlock, handling a known deadlock condition: + * + * Suppose this situation: + * + * - CPUn enters a critical section and has the g_cpu_irqlock spinlock. + * - CPUn causes a task to become ready to run and scheduler selects + * CPUm. CPUm is requested to pause. + * - But CPUm is in a normal task and is also attempting to enter a + * critical section. So it is also spinning to get g_cpu_irqlock + * with interrupts disabled and cannot respond to the pause request, + * causing the deadlock. + * + * This function detects this deadlock condition while spinning with \ + * interrupts disabled. + * + ****************************************************************************/ + +#ifdef CONFIG_SMP +static inline bool task_waitlock(int cpu) +{ + /* Duplicate the spin_lock() logic from spinlock.c, but adding the check + * for the deadlock condition. + */ + + while (spin_trylock(&g_cpu_irqlock) == SP_LOCKED) + { + /* Is a pause request pending? */ + + if (up_cpu_pausereq(cpu)) + { + /* Yes.. some other CPU is requesting to pause this CPU! + * Abort the wait and return false. + */ + + return false; + } + + SP_DSB(); + } + + /* We have g_cpu_irqlock! */ + + SP_DMB(); + return true; +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -185,6 +236,8 @@ irqstate_t enter_critical_section(void) * the local CPU. */ +try_again: + ret = up_irq_save(); /* Verify that the system has sufficiently initialized so that the task @@ -218,14 +271,14 @@ irqstate_t enter_critical_section(void) * * g_cpu_irqlock = SP_LOCKED. * g_cpu_nestcount = 0 - * The bit in g_cpu_irqset for this CPU hould be zero + * The bit in g_cpu_irqset for this CPU should be zero * * 4. An extension of 3 is that we may be re-entered numerous * times from the same interrupt handler. In that case: * * g_cpu_irqlock = SP_LOCKED. * g_cpu_nestcount > 0 - * The bit in g_cpu_irqset for this CPU hould be zero + * The bit in g_cpu_irqset for this CPU should be zero * * NOTE: However, the interrupt entry conditions can change due * to previous processing by the interrupt handler that may @@ -305,7 +358,19 @@ irqstate_t enter_critical_section(void) cpu = this_cpu(); DEBUGASSERT((g_cpu_irqset & (1 << cpu)) == 0); - spin_lock(&g_cpu_irqlock); + + if (!task_waitlock(cpu)) + { + /* We are in a potential deadlock condition due to a + * pending pause request interrupt. Re-enable interrupts + * on this CPU and try again. Briefly re-enabling + * interrupts should be sufficient to permit processing + * the pending pause request. + */ + + up_irq_restore(ret); + goto try_again; + } /* The set the lock count to 1. * -- GitLab From 465e297b5b1fc28f85cac84bb0fb33ae05c99f33 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 25 Nov 2016 23:10:58 -0600 Subject: [PATCH 511/734] Uncomment CONFIG_APPS_DIR in a defconfig file --- configs/hymini-stm32v/nsh2/defconfig | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/configs/hymini-stm32v/nsh2/defconfig b/configs/hymini-stm32v/nsh2/defconfig index 887afa3ef9..5a47ce1424 100644 --- a/configs/hymini-stm32v/nsh2/defconfig +++ b/configs/hymini-stm32v/nsh2/defconfig @@ -16,7 +16,7 @@ CONFIG_HOST_LINUX=y # # Build Configuration # -CONFIG_APPS_DIR="../apps" +# CONFIG_APPS_DIR="../apps" CONFIG_BUILD_FLAT=y # CONFIG_BUILD_2PASS is not set @@ -1171,10 +1171,6 @@ CONFIG_ARCH_HAVE_TLS=y # Application Configuration # -# -# NxWidgets/NxWM -# - # # Built-In Applications # @@ -1427,6 +1423,10 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_NSH_LOGIN is not set # CONFIG_NSH_CONSOLE_LOGIN is not set +# +# NxWidgets/NxWM +# + # # Platform-specific Support # -- GitLab From 1d06e786e12cfd6c4675b25e7a5b5669b2dc8195 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Nov 2016 07:05:27 -0600 Subject: [PATCH 512/734] SMP: Clean-up and simplication of logic that I implemented late last night. --- sched/irq/irq_csection.c | 114 +++++++++++++-------------------------- 1 file changed, 37 insertions(+), 77 deletions(-) diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 1b8ba44d0b..8c91852c1a 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -88,7 +88,8 @@ static uint8_t g_cpu_nestcount[CONFIG_SMP_NCPUS]; * Description: * Spin to get g_irq_waitlock, handling a known deadlock condition: * - * Suppose this situation: + * A deadlock may occur if enter_critical_section is called from an + * interrupt handler. Suppose: * * - CPUn is in a critical section and has the g_cpu_irqlock spinlock. * - CPUm takes an interrupt and attempts to enter the critical section. @@ -98,83 +99,34 @@ static uint8_t g_cpu_nestcount[CONFIG_SMP_NCPUS]; * - But interrupts are disabled on CPUm so the up_cpu_pause() is never * handled, causing the deadlock. * - * This function detects this deadlock condition while spinning in an - * interrupt and calls up_cpu_pause() handler, breaking the deadlock. + * This same deadlock can occur in the normal tasking case: * - ****************************************************************************/ - -#ifdef CONFIG_SMP -static inline void irq_waitlock(int cpu) -{ - /* Duplicate the spin_lock() logic from spinlock.c, but adding the check - * for the deadlock condition. - */ - - while (spin_trylock(&g_cpu_irqlock) == SP_LOCKED) - { - /* A deadlock condition would occur if CPUn: - * - * 1. Holds the g_cpu_irqlock, and - * 2. Is trying to interrupt CPUm, but - * 3. CPUm is spinning trying acquire the g_cpu_irqlock. - * - * The protocol for CPUn to pause CPUm is as follows - * - * 1. The up_cpu_pause() implementation on CPUn locks both - * g_cpu_wait[m] and g_cpu_paused[m]. CPUn then waits - * spinning on g_cpu_wait[m]. - * 2. When CPUm receives the interrupt it (1) unlocks - * g_cpu_paused[m] and (2) locks g_cpu_wait[m]. The - * first unblocks CPUn and the second blocks CPUm in the - * interrupt handler. - * - * The problem in the deadlock case is that CPUm cannot receive - * the interrupt because it is locked up spinning. Here we break - * the deadlock here be handling the pause interrupt request - * while waiting. - */ - - if (up_cpu_pausereq(cpu)) - { - /* Yes.. some other CPU is requesting to pause this CPU! Handle - * the pause interrupt now. - */ - - DEBUGVERIFY(up_cpu_paused(cpu)); - } - - SP_DSB(); - } - - /* We have g_cpu_irqlock! */ - - SP_DMB(); -} -#endif - -/**************************************************************************** - * Name: task_waitlock - * - * Description: - * Spin to get g_irq_waitlock, handling a known deadlock condition: - * - * Suppose this situation: - * - * - CPUn enters a critical section and has the g_cpu_irqlock spinlock. - * - CPUn causes a task to become ready to run and scheduler selects - * CPUm. CPUm is requested to pause. - * - But CPUm is in a normal task and is also attempting to enter a - * critical section. So it is also spinning to get g_cpu_irqlock - * with interrupts disabled and cannot respond to the pause request, - * causing the deadlock. + * - A task on CPUn enters a critical section and has the g_cpu_irqlock + * spinlock. + * - Another task on CPUm attempts to enter the critical section but has + * to wait, spinning to get g_cpu_irqlock with interrupts disabled. + * - The task on CPUn causes a new task to become ready-torun and the + * scheduler selects CPUm. CPUm is requested to pause via a pause + * interrupt. + * - But the task on CPUm is also attempting to enter the critical + * section. Since it is spinning with interrupts disabled, CPUm cannot + * process the pending pause interrupt, causing the deadlock. * * This function detects this deadlock condition while spinning with \ * interrupts disabled. * + * Input Parameters: + * cpu - The index of CPU that is trying to enter the critical section. + * + * Returned Value: + * True: The g_cpu_irqlock spinlock has been taken. + * False: The g_cpu_irqlock spinlock has not been taken yet, but there is + * a pending pause interrupt request. + * ****************************************************************************/ #ifdef CONFIG_SMP -static inline bool task_waitlock(int cpu) +static inline bool irq_waitlock(int cpu) { /* Duplicate the spin_lock() logic from spinlock.c, but adding the check * for the deadlock condition. @@ -317,7 +269,15 @@ try_again: * no longer blocked by the critical section). */ - irq_waitlock(cpu); + if (!irq_waitlock(cpu)) + { + /* We are in a deadlock condition due to a pending + * pause request interrupt request. Break the + * deadlock by handling the pause interrupt now. + */ + + DEBUGVERIFY(up_cpu_paused(cpu)); + } } /* In any event, the nesting count is now one */ @@ -359,13 +319,13 @@ try_again: cpu = this_cpu(); DEBUGASSERT((g_cpu_irqset & (1 << cpu)) == 0); - if (!task_waitlock(cpu)) + if (!irq_waitlock(cpu)) { - /* We are in a potential deadlock condition due to a - * pending pause request interrupt. Re-enable interrupts - * on this CPU and try again. Briefly re-enabling - * interrupts should be sufficient to permit processing - * the pending pause request. + /* We are in a deadlock condition due to a pending pause + * request interrupt. Re-enable interrupts on this CPU + * and try again. Briefly re-enabling interrupts should + * be sufficient to permit processing the pending pause + * request. */ up_irq_restore(ret); -- GitLab From e3fe320e08f082779748522b98135669bc346ef2 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Nov 2016 08:47:03 -0600 Subject: [PATCH 513/734] SMP: Add support for linking spinlocks into a special, non-cached memory region. --- arch/arm/src/armv7-a/arm_cpupause.c | 4 +- arch/sim/src/up_idle.c | 2 +- arch/sim/src/up_internal.h | 4 +- arch/xtensa/src/common/xtensa_cpupause.c | 79 +++++++++++++++---- .../src/esp32/esp32_intercpu_interrupt.c | 4 +- include/nuttx/spinlock.h | 23 ++++-- sched/irq/irq.h | 6 +- sched/irq/irq_csection.c | 6 +- sched/sched/sched.h | 6 +- sched/sched/sched_lock.c | 6 +- sched/semaphore/spinlock.c | 7 +- 11 files changed, 108 insertions(+), 39 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_cpupause.c b/arch/arm/src/armv7-a/arm_cpupause.c index 1b5726aba9..8b8df44a73 100644 --- a/arch/arm/src/armv7-a/arm_cpupause.c +++ b/arch/arm/src/armv7-a/arm_cpupause.c @@ -69,8 +69,8 @@ * so that it will be ready for the next pause operation. */ -static volatile spinlock_t g_cpu_wait[CONFIG_SMP_NCPUS]; -static volatile spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS]; +static volatile spinlock_t g_cpu_wait[CONFIG_SMP_NCPUS] SP_SECTION; +static volatile spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS] SP_SECTION; /**************************************************************************** * Public Functions diff --git a/arch/sim/src/up_idle.c b/arch/sim/src/up_idle.c index 2e218b319d..1912bf755c 100644 --- a/arch/sim/src/up_idle.c +++ b/arch/sim/src/up_idle.c @@ -105,7 +105,7 @@ void up_idle(void) * should not matter which, however. */ - static volatile spinlock_t lock = SP_UNLOCKED; + static volatile spinlock_t lock SP_SECTION = SP_UNLOCKED; /* The one that gets the lock is the one that executes the IDLE operations */ diff --git a/arch/sim/src/up_internal.h b/arch/sim/src/up_internal.h index 9facb343af..53f4e2cd42 100644 --- a/arch/sim/src/up_internal.h +++ b/arch/sim/src/up_internal.h @@ -214,8 +214,8 @@ extern volatile int g_uart_data_available; * so that it will be ready for the next pause operation. */ -volatile spinlock_t g_cpu_wait[CONFIG_SMP_NCPUS]; -volatile spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS]; +volatile spinlock_t g_cpu_wait[CONFIG_SMP_NCPUS] SP_SECTION; +volatile spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS] SP_SECTION; #endif /**************************************************************************** diff --git a/arch/xtensa/src/common/xtensa_cpupause.c b/arch/xtensa/src/common/xtensa_cpupause.c index 46bac69bbd..e310ad44da 100644 --- a/arch/xtensa/src/common/xtensa_cpupause.c +++ b/arch/xtensa/src/common/xtensa_cpupause.c @@ -54,39 +54,64 @@ * Private Data ****************************************************************************/ -static spinlock_t g_cpu_wait[CONFIG_SMP_NCPUS]; -static spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS]; +static spinlock_t g_cpu_wait[CONFIG_SMP_NCPUS] SP_SECTION; +static spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS] SP_SECTION; /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: xtensa_pause_handler + * Name: up_cpu_pausereq * * Description: - * This is the handler for CPU_INTCODE_PAUSE CPU interrupt. This - * implements up_cpu_pause() by performing the following operations: + * Return true if a pause request is pending for this CPU. * - * 1. The current task state at the head of the current assigned task - * list was saved when the interrupt was entered. - * 2. This function simply waits on a spinlock, then returns. - * 3. Upon return, the interrupt exit logic will restore the state of - * the new task at the head of the ready to run list. + * Input Parameters: + * cpu - The index of the CPU to be queried + * + * Returned Value: + * true = a pause request is pending. + * false = no pasue request is pending. + * + ****************************************************************************/ + +bool up_cpu_pausereq(int cpu) +{ + return spin_islocked(&g_cpu_paused[cpu]); +} + +/**************************************************************************** + * Name: up_cpu_paused + * + * Description: + * Handle a pause request from another CPU. Normally, this logic is + * executed from interrupt handling logic within the architecture-specific + * However, it is sometimes necessary necessary to perform the pending + * pause operation in other contexts where the interrupt cannot be taken + * in order to avoid deadlocks. + * + * This function performs the following operations: + * + * 1. It saves the current task state at the head of the current assigned + * task list. + * 2. It waits on a spinlock, then + * 3. Returns from interrupt, restoring the state of the new task at the + * head of the ready to run list. * * Input Parameters: - * None + * cpu - The index of the CPU to be paused * * Returned Value: - * None + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. * ****************************************************************************/ -void xtensa_pause_handler(void) +int up_cpu_paused(int cpu) { FAR struct tcb_s *otcb = this_task(); FAR struct tcb_s *ntcb; - int cpu = up_cpu_index(); /* Update scheduler parameters */ @@ -128,6 +153,32 @@ void xtensa_pause_handler(void) spin_unlock(&g_cpu_wait[cpu]); } +/**************************************************************************** + * Name: xtensa_pause_handler + * + * Description: + * This is the handler for CPU_INTCODE_PAUSE CPU interrupt. This + * implements up_cpu_pause() by performing the following operations: + * + * 1. The current task state at the head of the current assigned task + * list was saved when the interrupt was entered. + * 2. This function simply waits on a spinlock, then returns. + * 3. Upon return, the interrupt exit logic will restore the state of + * the new task at the head of the ready to run list. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void xtensa_pause_handler(void) +{ + (void)up_cpu_paused(up_cpu_index()); +} + /**************************************************************************** * Name: up_cpu_pause * diff --git a/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c b/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c index 66ae7bac06..ccbe9de4e5 100644 --- a/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c +++ b/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c @@ -59,11 +59,11 @@ /* Single parameter passed with the inter-CPU interrupt */ -static volatile uint8_t g_intcode[CONFIG_SMP_NCPUS]; +static volatile uint8_t g_intcode[CONFIG_SMP_NCPUS] SP_SECTION; /* Spinlock protects parameter array */ -static volatile spinlock_t g_intercpu_spin[CONFIG_SMP_NCPUS] = +static volatile spinlock_t g_intercpu_spin[CONFIG_SMP_NCPUS] SP_SECTION = { SP_UNLOCKED, SP_UNLOCKED }; diff --git a/include/nuttx/spinlock.h b/include/nuttx/spinlock.h index ee6bf65b64..afcc4a1853 100644 --- a/include/nuttx/spinlock.h +++ b/include/nuttx/spinlock.h @@ -69,16 +69,29 @@ * DSB - Data syncrhonization barrier. */ -#define HAVE_DMB 1 -#ifndef SP_DMB +#undef __SP_UNLOCK_FUNCTION +#if !defined(SP_DMB) # define SP_DMB() -# undef HAVE_DMB +#else +# define __SP_UNLOCK_FUNCTION 1 #endif -#ifndef SP_DSB +#if !defined(SP_DSB) # define SP_DSB() #endif +/* If the target CPU supports a data cache then it may be necessary to + * manage spinlocks in a special way, perhaps linking them all into a + * special non-cacheable memory region. + * + * SP_SECTION - Special storage attributes may be required to force + * spinlocks into a special, non-cacheable section. + */ + +#if !defined(SP_SECTION) +# define SP_SECTION +#endif + /**************************************************************************** * Public Types ****************************************************************************/ @@ -244,7 +257,7 @@ void spin_lockr(FAR struct spinlock_s *lock); * ****************************************************************************/ -#ifdef HAVE_DMB +#ifdef __SP_UNLOCK_FUNCTION void spin_unlock(FAR volatile spinlock_t *lock); #else # define spin_unlock(l) do { *(l) = SP_UNLOCKED; } while (0) diff --git a/sched/irq/irq.h b/sched/irq/irq.h index 60d38443fb..69b3d344b3 100644 --- a/sched/irq/irq.h +++ b/sched/irq/irq.h @@ -65,12 +65,12 @@ extern FAR xcpt_t g_irqvector[NR_IRQS]; * disabled. */ -extern volatile spinlock_t g_cpu_irqlock; +extern volatile spinlock_t g_cpu_irqlock SP_SECTION; /* Used to keep track of which CPU(s) hold the IRQ lock. */ -extern volatile spinlock_t g_cpu_irqsetlock; -extern volatile cpu_set_t g_cpu_irqset; +extern volatile spinlock_t g_cpu_irqsetlock SP_SECTION; +extern volatile cpu_set_t g_cpu_irqset SP_SECTION; #endif /**************************************************************************** diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 8c91852c1a..20660dd728 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -60,12 +60,12 @@ * disabled. */ -volatile spinlock_t g_cpu_irqlock = SP_UNLOCKED; +volatile spinlock_t g_cpu_irqlock SP_SECTION = SP_UNLOCKED; /* Used to keep track of which CPU(s) hold the IRQ lock. */ -volatile spinlock_t g_cpu_irqsetlock; -volatile cpu_set_t g_cpu_irqset; +volatile spinlock_t g_cpu_irqsetlock SP_SECTION; +volatile cpu_set_t g_cpu_irqset SP_SECTION; #endif /**************************************************************************** diff --git a/sched/sched/sched.h b/sched/sched/sched.h index 9e4bd64ba3..c8534e1399 100644 --- a/sched/sched/sched.h +++ b/sched/sched/sched.h @@ -353,12 +353,12 @@ extern volatile uint32_t g_cpuload_total; * least one CPU has pre-emption disabled. */ -extern volatile spinlock_t g_cpu_schedlock; +extern volatile spinlock_t g_cpu_schedlock SP_SECTION; /* Used to keep track of which CPU(s) hold the IRQ lock. */ -extern volatile spinlock_t g_cpu_locksetlock; -extern volatile cpu_set_t g_cpu_lockset; +extern volatile spinlock_t g_cpu_locksetlock SP_SECTION; +extern volatile cpu_set_t g_cpu_lockset SP_SECTION; #endif /* CONFIG_SMP */ diff --git a/sched/sched/sched_lock.c b/sched/sched/sched_lock.c index 36b53775d2..5f389eed57 100644 --- a/sched/sched/sched_lock.c +++ b/sched/sched/sched_lock.c @@ -109,12 +109,12 @@ * least one CPU has pre-emption disabled. */ -volatile spinlock_t g_cpu_schedlock = SP_UNLOCKED; +volatile spinlock_t g_cpu_schedlock SP_SECTION = SP_UNLOCKED; /* Used to keep track of which CPU(s) hold the IRQ lock. */ -volatile spinlock_t g_cpu_locksetlock; -volatile cpu_set_t g_cpu_lockset; +volatile spinlock_t g_cpu_locksetlock SP_SECTION; +volatile cpu_set_t g_cpu_lockset SP_SECTION; #endif /* CONFIG_SMP */ diff --git a/sched/semaphore/spinlock.c b/sched/semaphore/spinlock.c index e03f14c72f..34a87126d2 100644 --- a/sched/semaphore/spinlock.c +++ b/sched/semaphore/spinlock.c @@ -144,7 +144,7 @@ void spin_lock(FAR volatile spinlock_t *lock) * ****************************************************************************/ -#ifdef HAVE_DMB +#ifdef __SP_UNLOCK_FUNCTION void spin_unlock(FAR volatile spinlock_t *lock) { *lock = SP_UNLOCKED; @@ -218,8 +218,11 @@ void spin_lockr(FAR struct spinlock_s *lock) up_irq_restore(flags); sched_yield(); flags = up_irq_save(); + SP_DSB(); } + SP_DMB(); + /* Take one count on the lock */ lock->sp_cpu = cpu; @@ -238,8 +241,10 @@ void spin_lockr(FAR struct spinlock_s *lock) while (up_testset(&lock->sp_lock) == SP_LOCKED) { sched_yield(); + SP_DSB() } + SP_DMB(); #endif /* CONFIG_SMP */ } -- GitLab From 61b45a854472f4f3d227d2630d89654993d150cc Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Nov 2016 09:27:29 -0600 Subject: [PATCH 514/734] i.MX6: Add some comments --- arch/arm/src/imx6/chip/imx_memorymap.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/src/imx6/chip/imx_memorymap.h b/arch/arm/src/imx6/chip/imx_memorymap.h index c91fb924e0..9875fe1e48 100644 --- a/arch/arm/src/imx6/chip/imx_memorymap.h +++ b/arch/arm/src/imx6/chip/imx_memorymap.h @@ -918,6 +918,14 @@ */ #ifndef CONFIG_ARCH_LOWVECTORS + /* Memory map + * VIRTUAL ADDRESS RANGE L1 PG TABLE L2 PG TABLE DESCRIPTION + * START END OFFSET SIZE + * ---------- ---------- ------------ ---------------------------- + * 0x80000000 0x803fffff 0x000002000 0x000000400 Vectors (1MiB) + * 0x80100000 0x806fffff 0x000002400 0x000001800 Paging (6MiB) + */ + /* Vector L2 page table offset/size */ # define VECTOR_L2_OFFSET 0x000002000 @@ -939,6 +947,13 @@ # define PGTABLE_L2_SIZE 0x000001800 #else + /* Memory map + * VIRTUAL ADDRESS RANGE L1 PG TABLE L2 PG TABLE DESCRIPTION + * START END OFFSET SIZE + * ---------- ---------- ------------ ---------------------------- + * 0x80000000 0x806fffff 0x000002000 0x000001c00 Paging (7MiB) + */ + /* Paging L2 page table offset/size */ # define PGTABLE_L2_OFFSET 0x000002000 -- GitLab From 2fba04f7521e84e5efefc25822c0574bb4efc2ce Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Nov 2016 10:37:06 -0600 Subject: [PATCH 515/734] i.MX6 SMP: Beginning of non-cacheable region (incomplete) --- arch/arm/src/imx6/chip/imx_memorymap.h | 87 +++++++++++++++++++++++--- arch/arm/src/imx6/imx_boot.c | 73 +++++++++++++++++---- 2 files changed, 139 insertions(+), 21 deletions(-) diff --git a/arch/arm/src/imx6/chip/imx_memorymap.h b/arch/arm/src/imx6/chip/imx_memorymap.h index c91fb924e0..87625af790 100644 --- a/arch/arm/src/imx6/chip/imx_memorymap.h +++ b/arch/arm/src/imx6/chip/imx_memorymap.h @@ -897,7 +897,7 @@ * 0x80000000-0xefffffff: Undefined (1.75 GB) * * That is the offset where the main L2 page tables will be positioned. This - * corresponds to page table offsets 0x000002000 up to 0x000003c00. That + * corresponds to page table offsets 0x00002000 up to 0x00003c00. That * is 1792 entries, each mapping 4KB of address for a total of 7MB of virtual * address space) * @@ -917,7 +917,21 @@ * the address space. */ +#define INTERCPU_L2_PAGES 1 /* Pages allowed for inter-processor communications */ + #ifndef CONFIG_ARCH_LOWVECTORS + /* Memory map + * VIRTUAL ADDRESS RANGE L1 PG TABLE L2 PG TABLE DESCRIPTION + * START END OFFSET SIZE + * ---------- ---------- ------------ ---------------------------- + * 0x80000000 0x803fffff 0x000002000 0x000000400 Vectors (1MiB) + * 0x80100000 0x806fffff 0x000002400 0x000001800 Paging (6MiB) + * + * If SMP is enabled, then INTERCPU_L2_PAGES pages are taken from the end + * of the Paging L2 page table to hold non-cacheable, inter-processor + * communication data. + */ + /* Vector L2 page table offset/size */ # define VECTOR_L2_OFFSET 0x000002000 @@ -933,16 +947,44 @@ # define VECTOR_L2_END_PADDR (VECTOR_L2_PBASE + VECTOR_L2_SIZE) # define VECTOR_L2_END_VADDR (VECTOR_L2_VBASE + VECTOR_L2_SIZE) - /* Paging L2 page table offset/size */ +# ifdef CONFIG_SMP + /* Paging L2 page table offset/size */ + +# define PGTABLE_L2_OFFSET 0x000002400 +# define PGTABLE_L2_SIZE (0x000001800 - 4*INTERCPU_L2_PAGES) -# define PGTABLE_L2_OFFSET 0x000002400 -# define PGTABLE_L2_SIZE 0x000001800 +# else + /* Paging L2 page table offset/size */ + +# define PGTABLE_L2_OFFSET 0x000002400 +# define PGTABLE_L2_SIZE 0x000001800 +# endif #else - /* Paging L2 page table offset/size */ + /* Memory map + * VIRTUAL ADDRESS RANGE L1 PG TABLE L2 PG TABLE DESCRIPTION + * START END OFFSET SIZE + * ---------- ---------- ------------ ---------------------------- + * 0x80000000 0x806fffff 0x000002000 0x000001c00 Paging (7MiB) + * + * If SMP is enabled, then INTERCPU_L2_PAGES pages are taken from the end + * of the Paging L2 page table to hold non-cacheable, inter-processor + * communication data. + */ + +# ifdef CONFIG_SMP + /* Paging L2 page table offset/size */ + +# define PGTABLE_L2_OFFSET 0x000002000 +# define PGTABLE_L2_SIZE (0x000001c00 - 4*INTERCPU_L2_PAGES) + +# else + /* Paging L2 page table offset/size */ + +# define PGTABLE_L2_OFFSET 0x000002000 +# define PGTABLE_L2_SIZE 0x000001c00 +# endif -# define PGTABLE_L2_OFFSET 0x000002000 -# define PGTABLE_L2_SIZE 0x000001c00 #endif /* Paging L2 page table base addresses @@ -959,6 +1001,17 @@ #define PGTABLE_L2_END_PADDR (PGTABLE_L2_PBASE + PGTABLE_L2_SIZE) #define PGTABLE_L2_END_VADDR (PGTABLE_L2_VBASE + PGTABLE_L2_SIZE) +#ifdef CONFIG_SMP +/* Non-cached inter-processor communication data */ + +# define INTERCPU_L2_OFFSET (PGTABLE_L2_OFFSET + PGTABLE_L2_SIZE) +# define INTERCPU_L2_SIZE (4*INTERCPU_L2_PAGES) + +/* Inter-processor communications L2 page table virtual base addresse */ + +# define INTERCPU_L2_VBASE (PGTABLE_BASE_VADDR + INTERCPU_L2_OFFSET) +#endif + /* Base address of the interrupt vector table. * * IMX_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM @@ -974,19 +1027,35 @@ */ #ifdef CONFIG_ARCH_LOWVECTORS /* Vectors located at 0x0000:0000 */ - - /* Vectors will always lie at the beginnin of OCRAM */ +/* Vectors will always lie at the beginning of OCRAM */ # define IMX_VECTOR_PADDR IMX_OCRAM_PBASE # define IMX_VECTOR_VSRAM IMX_OCRAM_VBASE # define IMX_VECTOR_VADDR 0x00000000 +#ifdef CONFIG_SMP +/* Inter-processor communications */ + +# define INTERCPU_PADDR (IMX_VECTOR_PADDR + VECTOR_TABLE_SIZE) +# define INTERCPU_VADDR (INTERCPU_L2_VBASE << 18) +# define INTERCPU_SIZE (INTERCPU_L2_PAGES << 12) +# define INTERCPU_VSRAM (IMX_VECTOR_VSRAM + VECTOR_TABLE_SIZE) +#endif + #else /* Vectors located at 0xffff:0000 -- this probably does not work */ # define IMX_VECTOR_PADDR (IMX_OCRAM_PBASE + IMX_OCRAM_SIZE - VECTOR_TABLE_SIZE) # define IMX_VECTOR_VSRAM (IMX_OCRAM_VBASE + IMX_OCRAM_SIZE - VECTOR_TABLE_SIZE) # define IMX_VECTOR_VADDR 0xffff0000 +#ifdef CONFIG_SMP +/* Inter-processor communications */ + +# define INTERCPU_PADDR (IMX_VECTOR_PADDR - INTERCPU_L2_SIZE) +# define INTERCPU_VADDR (INTERCPU_L2_VBASE << 18) +# define INTERCPU_SIZE (INTERCPU_L2_PAGES << 12) +# define INTERCPU_VSRAM (IMX_VECTOR_VSRAM - INTERCPU_L2_SIZE) +#endif #endif /************************************************************************************ diff --git a/arch/arm/src/imx6/imx_boot.c b/arch/arm/src/imx6/imx_boot.c index edfd5304a1..b4c36b9540 100644 --- a/arch/arm/src/imx6/imx_boot.c +++ b/arch/arm/src/imx6/imx_boot.c @@ -224,6 +224,46 @@ static void imx_vectormapping(void) # define imx_vectormapping() #endif +/**************************************************************************** + * Name: imx_intercpu_mapping + * + * Description: + * Setup a special mapping for the non-cached, inter-cpu communications + * area. + * + ****************************************************************************/ + +#ifndef CONFIG_SMP +static void imx_intercpu_mapping(void) +{ + uint32_t intercpu_paddr = INTERCPU_PADDR & PTE_SMALL_PADDR_MASK; + uint32_t intercpu_vaddr = INTERCPU_VADDR & PTE_SMALL_PADDR_MASK; + uint32_t end_paddr = INTERCPU_PADDR + INTERCPU_SIZE; + + /* We want to keep the inter-cpu region in on-chip RAM (OCRAM). The + * i.MX6 has 256Kb of OCRAM positioned at physical address 0x0090:0000. + */ + + while (intercpu_paddr < end_paddr) + { + mmu_l2_setentry(INTERCPU_L2_VBASE, intercpu_paddr, intercpu_vaddr, + MMU_L2_INTERCPUFLAGS); + intercpu_paddr += 4096; + intercpu_vaddr += 4096; + } + + /* Now set the level 1 descriptor to refer to the level 2 page table. */ + + mmu_l1_setentry(VECTOR_L2_PBASE & PMD_PTE_PADDR_MASK, + INTERCPU_VADDR & PMD_PTE_PADDR_MASK, + MMU_L1_PGTABFLAGS); +} +#else + /* No inter-cpu communications area */ + +# define imx_intercpu_mapping() +#endif + /**************************************************************************** * Name: imx_copyvectorblock * @@ -414,6 +454,15 @@ void arm_boot(void) imx_vectormapping(); imx_lowputc('B'); +#ifdef CONFIG_SMP + /* Provide a special mapping for the OCRAM interrupt vector positioned in + * high memory. + */ + + imx_intercpu_mapping(); + imx_lowputc('C'); +#endif + #ifdef CONFIG_ARCH_RAMFUNCS /* Copy any necessary code sections from FLASH to RAM. The correct * destination in OCRAM is given by _sramfuncs and _eramfuncs. The @@ -426,14 +475,14 @@ void arm_boot(void) *dest++ = *src++; } - imx_lowputc('C'); + imx_lowputc('D'); /* Flush the copied RAM functions into physical RAM so that will * be available when fetched into the I-Cache. */ arch_clean_dcache((uintptr_t)&_sramfuncs, (uintptr_t)&_eramfuncs) - imx_lowputc('D'); + imx_lowputc('E'); #endif /* Setup up vector block. _vector_start and _vector_end are exported from @@ -441,23 +490,23 @@ void arm_boot(void) */ imx_copyvectorblock(); - imx_lowputc('E'); + imx_lowputc('F'); /* Disable the watchdog timer */ imx_wdtdisable(); - imx_lowputc('F'); + imx_lowputc('G'); /* Initialize clocking to settings provided by board-specific logic */ imx_clockconfig(); - imx_lowputc('G'); + imx_lowputc('H'); #ifdef CONFIG_ARCH_FPU /* Initialize the FPU */ arm_fpuconfig(); - imx_lowputc('H'); + imx_lowputc('I'); #endif /* Perform board-specific initialization, This must include: @@ -471,7 +520,7 @@ void arm_boot(void) */ imx_board_initialize(); - imx_lowputc('I'); + imx_lowputc('J'); #ifdef NEED_SDRAM_REMAPPING /* SDRAM was configured in a temporary state to support low-level @@ -480,7 +529,7 @@ void arm_boot(void) */ imx_remap(); - imx_lowputc('J'); + imx_lowputc('K'); #endif #ifdef CONFIG_BOOT_SDRAM_DATA @@ -489,13 +538,13 @@ void arm_boot(void) */ arm_data_initialize(); - imx_lowputc('K'); + imx_lowputc('L'); #endif /* Perform common, low-level chip initialization (might do nothing) */ imx_lowsetup(); - imx_lowputc('L'); + imx_lowputc('M'); #ifdef USE_EARLYSERIALINIT /* Perform early serial initialization if we are going to use the serial @@ -503,7 +552,7 @@ void arm_boot(void) */ imx_earlyserialinit(); - imx_lowputc('M'); + imx_lowputc('N'); #endif /* Now we can enable all other CPUs. The enabled CPUs will start execution @@ -512,6 +561,6 @@ void arm_boot(void) */ imx_cpu_enable(); - imx_lowputc('N'); + imx_lowputc('O'); imx_lowputc('\n'); } -- GitLab From bdf570ea08b1fbdd4aa4bc39009111ed13630364 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Nov 2016 10:42:25 -0600 Subject: [PATCH 516/734] Fix typos in comments --- arch/arm/src/imx6/chip/imx_memorymap.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/imx6/chip/imx_memorymap.h b/arch/arm/src/imx6/chip/imx_memorymap.h index 9875fe1e48..8c1177af1b 100644 --- a/arch/arm/src/imx6/chip/imx_memorymap.h +++ b/arch/arm/src/imx6/chip/imx_memorymap.h @@ -897,7 +897,7 @@ * 0x80000000-0xefffffff: Undefined (1.75 GB) * * That is the offset where the main L2 page tables will be positioned. This - * corresponds to page table offsets 0x000002000 up to 0x000003c00. That + * corresponds to page table offsets 0x00002000 up to 0x00003c00. That * is 1792 entries, each mapping 4KB of address for a total of 7MB of virtual * address space) * @@ -989,8 +989,7 @@ */ #ifdef CONFIG_ARCH_LOWVECTORS /* Vectors located at 0x0000:0000 */ - - /* Vectors will always lie at the beginnin of OCRAM */ +/* Vectors will always lie at the beginning of OCRAM */ # define IMX_VECTOR_PADDR IMX_OCRAM_PBASE # define IMX_VECTOR_VSRAM IMX_OCRAM_VBASE -- GitLab From 8bacb1e4261c6f679903d0cf25bd7654b56809d1 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Nov 2016 11:02:21 -0600 Subject: [PATCH 517/734] Update comments --- arch/arm/src/imx6/chip/imx_memorymap.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/imx6/chip/imx_memorymap.h b/arch/arm/src/imx6/chip/imx_memorymap.h index 8c1177af1b..005fd1e4bb 100644 --- a/arch/arm/src/imx6/chip/imx_memorymap.h +++ b/arch/arm/src/imx6/chip/imx_memorymap.h @@ -989,13 +989,30 @@ */ #ifdef CONFIG_ARCH_LOWVECTORS /* Vectors located at 0x0000:0000 */ -/* Vectors will always lie at the beginning of OCRAM */ +/* Vectors will always lie at the beginning of OCRAM + * + * OCRAM Memory Map: + * ---------- ---------- --------------------------- + * OFFSET SIZE CONTENT + * ---------- ---------- --------------------------- + * 0x00000000 0x00010000 Vectors (VECTOR_TABLE_SIZE) + * 0x00010000 0x0003c000 Unused + * 0x0003c000 0x00004000 Page table (PGTABLE_SIZE) + */ # define IMX_VECTOR_PADDR IMX_OCRAM_PBASE # define IMX_VECTOR_VSRAM IMX_OCRAM_VBASE # define IMX_VECTOR_VADDR 0x00000000 #else /* Vectors located at 0xffff:0000 -- this probably does not work */ +/* OCRAM Memory Map: + * ---------- ---------- --------------------------- + * OFFSET SIZE CONTENT + * ---------- ---------- --------------------------- + * 0x00000000 0x00004000 Page table (PGTABLE_SIZE) + * 0x00004000 0x00030000 Unused + * 0x00030000 0x00010000 Vectors (VECTOR_TABLE_SIZE) + */ # define IMX_VECTOR_PADDR (IMX_OCRAM_PBASE + IMX_OCRAM_SIZE - VECTOR_TABLE_SIZE) # define IMX_VECTOR_VSRAM (IMX_OCRAM_VBASE + IMX_OCRAM_SIZE - VECTOR_TABLE_SIZE) -- GitLab From dda0ac8b21cb1404b57b0b583f6760610c6bddbc Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Nov 2016 11:06:24 -0600 Subject: [PATCH 518/734] Update comments --- arch/arm/src/imx6/chip/imx_memorymap.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/src/imx6/chip/imx_memorymap.h b/arch/arm/src/imx6/chip/imx_memorymap.h index de19b52743..6f185a0964 100644 --- a/arch/arm/src/imx6/chip/imx_memorymap.h +++ b/arch/arm/src/imx6/chip/imx_memorymap.h @@ -1031,10 +1031,11 @@ * * OCRAM Memory Map: * ---------- ---------- --------------------------- - * OFFSET SIZE CONTENT + * START END CONTENT * ---------- ---------- --------------------------- * 0x00000000 0x00010000 Vectors (VECTOR_TABLE_SIZE) - * 0x00010000 0x0003c000 Unused + * 0x00010000 0x00011000 Inter-CPU communications + * 0x00011000 0x0003c000 Unused * 0x0003c000 0x00004000 Page table (PGTABLE_SIZE) */ @@ -1054,10 +1055,11 @@ #else /* Vectors located at 0xffff:0000 -- this probably does not work */ /* OCRAM Memory Map: * ---------- ---------- --------------------------- - * OFFSET SIZE CONTENT + * START END CONTENT * ---------- ---------- --------------------------- * 0x00000000 0x00004000 Page table (PGTABLE_SIZE) - * 0x00004000 0x00030000 Unused + * 0x00004000 0x0002f000 Unused + * 0x0002f000 0x00030000 Inter-CPU communications * 0x00030000 0x00010000 Vectors (VECTOR_TABLE_SIZE) */ -- GitLab From 8e50541b10db889bf2ce1ae7d7656b19442b2f7b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Nov 2016 11:07:11 -0600 Subject: [PATCH 519/734] Update comments --- arch/arm/src/imx6/chip/imx_memorymap.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/imx6/chip/imx_memorymap.h b/arch/arm/src/imx6/chip/imx_memorymap.h index 005fd1e4bb..1a6fc0508d 100644 --- a/arch/arm/src/imx6/chip/imx_memorymap.h +++ b/arch/arm/src/imx6/chip/imx_memorymap.h @@ -993,7 +993,7 @@ * * OCRAM Memory Map: * ---------- ---------- --------------------------- - * OFFSET SIZE CONTENT + * START END CONTENT * ---------- ---------- --------------------------- * 0x00000000 0x00010000 Vectors (VECTOR_TABLE_SIZE) * 0x00010000 0x0003c000 Unused @@ -1007,7 +1007,7 @@ #else /* Vectors located at 0xffff:0000 -- this probably does not work */ /* OCRAM Memory Map: * ---------- ---------- --------------------------- - * OFFSET SIZE CONTENT + * START END CONTENT * ---------- ---------- --------------------------- * 0x00000000 0x00004000 Page table (PGTABLE_SIZE) * 0x00004000 0x00030000 Unused -- GitLab From aae306e9425b7ceb01e0328b8c2e6deb25e6d2a8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Nov 2016 12:04:02 -0600 Subject: [PATCH 520/734] i.MX6 SMP: Inter-CPU data no saved in a non-cacheable region. --- arch/arm/include/arm/spinlock.h | 57 +++++++++++++++++++++++++ arch/arm/include/armv6-m/spinlock.h | 39 +++++++++++++++++ arch/arm/include/armv7-a/spinlock.h | 39 +++++++++++++++++ arch/arm/include/armv7-m/spinlock.h | 39 +++++++++++++++++ arch/arm/include/armv7-r/spinlock.h | 39 +++++++++++++++++ arch/arm/include/spinlock.h | 20 +++++++++ arch/arm/src/armv7-a/mmu.h | 5 ++- arch/arm/src/common/up_internal.h | 10 +++++ arch/arm/src/imx6/chip/imx_memorymap.h | 18 ++++---- arch/arm/src/imx6/imx_boot.c | 25 ++++++++--- configs/sabre-6quad/scripts/dramboot.ld | 8 ++++ 11 files changed, 283 insertions(+), 16 deletions(-) create mode 100644 arch/arm/include/arm/spinlock.h create mode 100644 arch/arm/include/armv6-m/spinlock.h create mode 100644 arch/arm/include/armv7-a/spinlock.h create mode 100644 arch/arm/include/armv7-m/spinlock.h create mode 100644 arch/arm/include/armv7-r/spinlock.h diff --git a/arch/arm/include/arm/spinlock.h b/arch/arm/include/arm/spinlock.h new file mode 100644 index 0000000000..efe292acb7 --- /dev/null +++ b/arch/arm/include/arm/spinlock.h @@ -0,0 +1,57 @@ +/**************************************************************************** + * arch/arm/include/armv7-a/spinlock.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_ARM_SPINLOCK_H +#define __ARCH_ARM_INCLUDE_ARM_SPINLOCK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_SMP + /* In SMP configurations, save spinlocks and other inter-CPU communications + * data in a non-cached memory region. + */ + +# define SP_SECTION __attribute__((section(.nocache))) +#endif + +#endif /* __ARCH_ARM_INCLUDE_ARM_SPINLOCK_H */ diff --git a/arch/arm/include/armv6-m/spinlock.h b/arch/arm/include/armv6-m/spinlock.h new file mode 100644 index 0000000000..c1d154b370 --- /dev/null +++ b/arch/arm/include/armv6-m/spinlock.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/arm/include/armv7-a/spinlock.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_ARMV6_M_SPINLOCK_H +#define __ARCH_ARM_INCLUDE_ARMV6_M_SPINLOCK_H + +#endif /* __ARCH_ARM_INCLUDE_ARMV6_M_SPINLOCK_H */ diff --git a/arch/arm/include/armv7-a/spinlock.h b/arch/arm/include/armv7-a/spinlock.h new file mode 100644 index 0000000000..764a96ecef --- /dev/null +++ b/arch/arm/include/armv7-a/spinlock.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/arm/include/armv7-a/spinlock.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H +#define __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H + +#endif /* __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H */ diff --git a/arch/arm/include/armv7-m/spinlock.h b/arch/arm/include/armv7-m/spinlock.h new file mode 100644 index 0000000000..79a06b4173 --- /dev/null +++ b/arch/arm/include/armv7-m/spinlock.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/arm/include/armv7-a/spinlock.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_SPINLOCK_H +#define __ARCH_ARM_INCLUDE_ARMV7_M_SPINLOCK_H + +#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_SPINLOCK_H */ diff --git a/arch/arm/include/armv7-r/spinlock.h b/arch/arm/include/armv7-r/spinlock.h new file mode 100644 index 0000000000..ab7900fa73 --- /dev/null +++ b/arch/arm/include/armv7-r/spinlock.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/arm/include/armv7-r/spinlock.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_ARMV7_R_SPINLOCK_H +#define __ARCH_ARM_INCLUDE_ARMV7_R_SPINLOCK_H + +#endif /* __ARCH_ARM_INCLUDE_ARMV7_R_SPINLOCK_H */ diff --git a/arch/arm/include/spinlock.h b/arch/arm/include/spinlock.h index 45f26e0006..16079cc81a 100644 --- a/arch/arm/include/spinlock.h +++ b/arch/arm/include/spinlock.h @@ -44,6 +44,26 @@ # include #endif /* __ASSEMBLY__ */ +/* Include ARM architecture-specific IRQ definitions (including register + * save structure and up_irq_save()/up_irq_restore() functions) + */ + +#if defined(CONFIG_ARCH_CORTEXA5) || defined(CONFIG_ARCH_CORTEXA8) || \ + defined(CONFIG_ARCH_CORTEXA9) +# include +#elif defined(CONFIG_ARCH_CORTEXR4) || defined(CONFIG_ARCH_CORTEXR4F) || \ + defined(CONFIG_ARCH_CORTEXR5) || defined(CONFIG_ARCH_CORTEXR5F) || \ + defined(CONFIG_ARCH_CORTEXR7) || defined(CONFIG_ARCH_CORTEXR7F) +# include +#elif defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4) || \ + defined(CONFIG_ARCH_CORTEXM7) +# include +#elif defined(CONFIG_ARCH_CORTEXM0) +# include +#else +# include +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/arch/arm/src/armv7-a/mmu.h b/arch/arm/src/armv7-a/mmu.h index c84deda619..a10b357397 100644 --- a/arch/arm/src/armv7-a/mmu.h +++ b/arch/arm/src/armv7-a/mmu.h @@ -601,11 +601,14 @@ #define MMU_L2_PGTABFLAGS (PTE_TYPE_SMALL | PTE_WRITE_THROUGH | PTE_AP_RW1) #define MMU_L1_VECTORFLAGS (PMD_TYPE_PTE | PMD_PTE_PXN | PMD_PTE_DOM(0)) - #define MMU_L2_VECTRWFLAGS (PTE_TYPE_SMALL | PTE_WRITE_THROUGH | PTE_AP_RW1) #define MMU_L2_VECTROFLAGS (PTE_TYPE_SMALL | PTE_WRITE_THROUGH | PTE_AP_R1) #define MMU_L2_VECTORFLAGS MMU_L2_VECTRWFLAGS +#define MMU_L1_INTERCPUFLAGS (PMD_TYPE_PTE | PMD_PTE_PXN | PMD_DEVICE | \ + PMD_PTE_DOM(0)) +#define MMU_L2_INTERCPUFLAGS (PTE_TYPE_SMALL | PTE_DEVICE | PTE_AP_R1) + /* Mapped section size */ #define SECTION_SHIFT (20) diff --git a/arch/arm/src/common/up_internal.h b/arch/arm/src/common/up_internal.h index 36095a87a4..7318a70caa 100644 --- a/arch/arm/src/common/up_internal.h +++ b/arch/arm/src/common/up_internal.h @@ -191,6 +191,11 @@ # define _DATA_INIT &_eronly # define _START_DATA &_sdata # define _END_DATA &_edata + +#ifdef CONFIG_SMP +# define _START_NOCACHE &_snocache +# define _END_NOCACHE &_enocache +#endif #endif /* This is the value used to mark the stack for subsequent stack monitoring @@ -279,6 +284,11 @@ EXTERN uint32_t _edata; /* End+1 of .data */ EXTERN uint32_t _sbss; /* Start of .bss */ EXTERN uint32_t _ebss; /* End+1 of .bss */ +#ifdef CONFIG_SMP +EXTERN uint32_t _snocache; /* Start of .nocache */ +EXTERN uint32_t _enocache; /* End+1 of .nocache */ +#endif + /* Sometimes, functions must be executed from RAM. In this case, the following * macro may be used (with GCC!) to specify a function that will execute from * RAM. For example, diff --git a/arch/arm/src/imx6/chip/imx_memorymap.h b/arch/arm/src/imx6/chip/imx_memorymap.h index 6f185a0964..7b675e117b 100644 --- a/arch/arm/src/imx6/chip/imx_memorymap.h +++ b/arch/arm/src/imx6/chip/imx_memorymap.h @@ -927,9 +927,9 @@ * 0x80000000 0x803fffff 0x000002000 0x000000400 Vectors (1MiB) * 0x80100000 0x806fffff 0x000002400 0x000001800 Paging (6MiB) * - * If SMP is enabled, then INTERCPU_L2_PAGES pages are taken from the end - * of the Paging L2 page table to hold non-cacheable, inter-processor - * communication data. + * If SMP is enabled, then 1MiB of address spaces for the INTERCPU_L2_PAGES + * pages are taken from the end of the Paging L2 page table to hold non- + * cacheable, inter-processor communication data. */ /* Vector L2 page table offset/size */ @@ -951,7 +951,7 @@ /* Paging L2 page table offset/size */ # define PGTABLE_L2_OFFSET 0x000002400 -# define PGTABLE_L2_SIZE (0x000001800 - 4*INTERCPU_L2_PAGES) +# define PGTABLE_L2_SIZE 0x000001400 # else /* Paging L2 page table offset/size */ @@ -967,16 +967,16 @@ * ---------- ---------- ------------ ---------------------------- * 0x80000000 0x806fffff 0x000002000 0x000001c00 Paging (7MiB) * - * If SMP is enabled, then INTERCPU_L2_PAGES pages are taken from the end - * of the Paging L2 page table to hold non-cacheable, inter-processor - * communication data. + * If SMP is enabled, then 1MiB of address spaces for the INTERCPU_L2_PAGES + * pages are taken from the end of the Paging L2 page table to hold non- + * cacheable, inter-processor communication data. */ # ifdef CONFIG_SMP /* Paging L2 page table offset/size */ # define PGTABLE_L2_OFFSET 0x000002000 -# define PGTABLE_L2_SIZE (0x000001c00 - 4*INTERCPU_L2_PAGES) +# define PGTABLE_L2_SIZE 0x000001800 # else /* Paging L2 page table offset/size */ @@ -1005,7 +1005,7 @@ /* Non-cached inter-processor communication data */ # define INTERCPU_L2_OFFSET (PGTABLE_L2_OFFSET + PGTABLE_L2_SIZE) -# define INTERCPU_L2_SIZE (4*INTERCPU_L2_PAGES) +# define INTERCPU_L2_SIZE (0x00000400) /* Inter-processor communications L2 page table virtual base addresse */ diff --git a/arch/arm/src/imx6/imx_boot.c b/arch/arm/src/imx6/imx_boot.c index b4c36b9540..7e11fba87b 100644 --- a/arch/arm/src/imx6/imx_boot.c +++ b/arch/arm/src/imx6/imx_boot.c @@ -254,9 +254,9 @@ static void imx_intercpu_mapping(void) /* Now set the level 1 descriptor to refer to the level 2 page table. */ - mmu_l1_setentry(VECTOR_L2_PBASE & PMD_PTE_PADDR_MASK, + mmu_l1_setentry(INTERCPU_PBASE & PMD_PTE_PADDR_MASK, INTERCPU_VADDR & PMD_PTE_PADDR_MASK, - MMU_L1_PGTABFLAGS); + MMU_L1_INTERCPUFLAGS); } #else /* No inter-cpu communications area */ @@ -428,8 +428,10 @@ static inline void imx_wdtdisable(void) void arm_boot(void) { -#ifdef CONFIG_ARCH_RAMFUNCS +#if defined(CONFIG_ARCH_RAMFUNCS) const uint32_t *src; +#endif +#if defined(CONFIG_ARCH_RAMFUNCS) || defined(CONFIG_SMP) uint32_t *dest; #endif @@ -541,10 +543,21 @@ void arm_boot(void) imx_lowputc('L'); #endif +#ifdef CONFIG_SMP + /* Initialize the uncached, inter-CPU communications area */ + + for (dest = &_snocache; dest < &_enocache; ) + { + *dest++ = 0; + } + + imx_lowputc('M'); +#endif + /* Perform common, low-level chip initialization (might do nothing) */ imx_lowsetup(); - imx_lowputc('M'); + imx_lowputc('N'); #ifdef USE_EARLYSERIALINIT /* Perform early serial initialization if we are going to use the serial @@ -552,7 +565,7 @@ void arm_boot(void) */ imx_earlyserialinit(); - imx_lowputc('N'); + imx_lowputc('O'); #endif /* Now we can enable all other CPUs. The enabled CPUs will start execution @@ -561,6 +574,6 @@ void arm_boot(void) */ imx_cpu_enable(); - imx_lowputc('O'); + imx_lowputc('P'); imx_lowputc('\n'); } diff --git a/configs/sabre-6quad/scripts/dramboot.ld b/configs/sabre-6quad/scripts/dramboot.ld index f1134bcc92..de4b7a33dd 100644 --- a/configs/sabre-6quad/scripts/dramboot.ld +++ b/configs/sabre-6quad/scripts/dramboot.ld @@ -46,6 +46,7 @@ MEMORY { oscram (W!RX) : ORIGIN = 0x00900000, LENGTH = 256K - 16K ddr3 (W!RX) : ORIGIN = 0x10800000, LENGTH = 1024M - 8M + nocache (WR) : ORIGIN = 0x80600000, LENGTH = 4K } OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") @@ -122,6 +123,13 @@ SECTIONS _enoinit = ABSOLUTE(.); } > ddr3 + .nocache : + { + _snocache = ABSOLUTE(.); + *(.nocache) + _enocache = ABSOLUTE(.); + } > nocahce + /* Stabs debugging sections. */ .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } -- GitLab From 6ff6da083faf97ba1a6fdf8160fc50a4db5fe695 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Nov 2016 12:23:09 -0600 Subject: [PATCH 521/734] Fix a few compile related issues from the last commit --- arch/arm/include/arm/spinlock.h | 18 ------------------ arch/arm/include/armv7-a/spinlock.h | 18 ++++++++++++++++++ arch/arm/src/imx6/imx_boot.c | 2 ++ 3 files changed, 20 insertions(+), 18 deletions(-) diff --git a/arch/arm/include/arm/spinlock.h b/arch/arm/include/arm/spinlock.h index efe292acb7..ee3db052cf 100644 --- a/arch/arm/include/arm/spinlock.h +++ b/arch/arm/include/arm/spinlock.h @@ -36,22 +36,4 @@ #ifndef __ARCH_ARM_INCLUDE_ARM_SPINLOCK_H #define __ARCH_ARM_INCLUDE_ARM_SPINLOCK_H -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_SMP - /* In SMP configurations, save spinlocks and other inter-CPU communications - * data in a non-cached memory region. - */ - -# define SP_SECTION __attribute__((section(.nocache))) -#endif - #endif /* __ARCH_ARM_INCLUDE_ARM_SPINLOCK_H */ diff --git a/arch/arm/include/armv7-a/spinlock.h b/arch/arm/include/armv7-a/spinlock.h index 764a96ecef..5c5d1ae6ac 100644 --- a/arch/arm/include/armv7-a/spinlock.h +++ b/arch/arm/include/armv7-a/spinlock.h @@ -36,4 +36,22 @@ #ifndef __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H #define __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_SMP + /* In SMP configurations, save spinlocks and other inter-CPU communications + * data in a non-cached memory region. + */ + +# define SP_SECTION __attribute__((section(".nocache"))) +#endif + #endif /* __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H */ diff --git a/arch/arm/src/imx6/imx_boot.c b/arch/arm/src/imx6/imx_boot.c index 7e11fba87b..4455d3394a 100644 --- a/arch/arm/src/imx6/imx_boot.c +++ b/arch/arm/src/imx6/imx_boot.c @@ -240,6 +240,8 @@ static void imx_intercpu_mapping(void) uint32_t intercpu_vaddr = INTERCPU_VADDR & PTE_SMALL_PADDR_MASK; uint32_t end_paddr = INTERCPU_PADDR + INTERCPU_SIZE; + DEBUGASSERT(intercpu_vaddr == (uint32_t)&_snocache); + /* We want to keep the inter-cpu region in on-chip RAM (OCRAM). The * i.MX6 has 256Kb of OCRAM positioned at physical address 0x0090:0000. */ -- GitLab From 785ed5faf2918aa199690075a09e5f2fe2104db3 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Nov 2016 13:20:11 -0600 Subject: [PATCH 522/734] SMP: A few more compile/link issues. Still problems. --- arch/arm/src/armv7-a/mmu.h | 22 ++++++++++++++++++++++ arch/arm/src/imx6/chip/imx_memorymap.h | 11 +++++++++-- arch/arm/src/imx6/imx_boot.c | 4 ++-- configs/sabre-6quad/scripts/dramboot.ld | 4 ++-- 4 files changed, 35 insertions(+), 6 deletions(-) diff --git a/arch/arm/src/armv7-a/mmu.h b/arch/arm/src/armv7-a/mmu.h index a10b357397..3ea2074a7c 100644 --- a/arch/arm/src/armv7-a/mmu.h +++ b/arch/arm/src/armv7-a/mmu.h @@ -1426,6 +1426,28 @@ void mmu_l1_restore(uintptr_t vaddr, uint32_t l1entry); # define mmu_l1_clrentry(v) mmu_l1_restore(v,0) #endif +/**************************************************************************** + * Name: mmu_l2_setentry + * + * Description: + * Set one small (4096B) entry in a level2 translation table. + * + * Input Parameters: + * l2vaddr - the virtual address of the beginning of the L2 translation + * table. + * paddr - The physical address to be mapped. Must be aligned to a 4KB + * address boundary + * vaddr - The virtual address to be mapped. Must be aligned to a 4KB + * address boundary + * mmuflags - The MMU flags to use in the mapping. + * + ****************************************************************************/ + +#ifndef CONFIG_ARCH_ROMPGTABLE +void mmu_l2_setentry(uint32_t l2vaddr, uint32_t paddr, uint32_t vaddr, + uint32_t mmuflags); +#endif + /************************************************************************************ * Name: mmu_l1_map_region * diff --git a/arch/arm/src/imx6/chip/imx_memorymap.h b/arch/arm/src/imx6/chip/imx_memorymap.h index 7b675e117b..bd352ce7c7 100644 --- a/arch/arm/src/imx6/chip/imx_memorymap.h +++ b/arch/arm/src/imx6/chip/imx_memorymap.h @@ -917,7 +917,8 @@ * the address space. */ -#define INTERCPU_L2_PAGES 1 /* Pages allowed for inter-processor communications */ +#define INTERCPU_L2_PAGES 1 /* Pages allowed for inter-processor communications */ +#define L2_BASE 0x80000000 /* Beginning of L2 page table */ #ifndef CONFIG_ARCH_LOWVECTORS /* Memory map @@ -1007,9 +1008,15 @@ # define INTERCPU_L2_OFFSET (PGTABLE_L2_OFFSET + PGTABLE_L2_SIZE) # define INTERCPU_L2_SIZE (0x00000400) -/* Inter-processor communications L2 page table virtual base addresse */ + /* on-cached inter-processor communication page table base addresses */ +# define INTERCPU_L2_PBASE (PGTABLE_BASE_PADDR + INTERCPU_L2_OFFSET) # define INTERCPU_L2_VBASE (PGTABLE_BASE_VADDR + INTERCPU_L2_OFFSET) + + /* on-cached inter-processor communication end addresses */ + +# define INTERCPU_L2_END_PADDR (INTERCPU_L2_PBASE + INTERCPU_L2_SIZE) +# define INTERCPU_L2_END_VADDR (INTERCPU_L2_VBASE + INTERCPU_L2_SIZE) #endif /* Base address of the interrupt vector table. diff --git a/arch/arm/src/imx6/imx_boot.c b/arch/arm/src/imx6/imx_boot.c index 4455d3394a..b635a27aec 100644 --- a/arch/arm/src/imx6/imx_boot.c +++ b/arch/arm/src/imx6/imx_boot.c @@ -233,7 +233,7 @@ static void imx_vectormapping(void) * ****************************************************************************/ -#ifndef CONFIG_SMP +#ifdef CONFIG_SMP static void imx_intercpu_mapping(void) { uint32_t intercpu_paddr = INTERCPU_PADDR & PTE_SMALL_PADDR_MASK; @@ -256,7 +256,7 @@ static void imx_intercpu_mapping(void) /* Now set the level 1 descriptor to refer to the level 2 page table. */ - mmu_l1_setentry(INTERCPU_PBASE & PMD_PTE_PADDR_MASK, + mmu_l1_setentry(INTERCPU_PADDR & PMD_PTE_PADDR_MASK, INTERCPU_VADDR & PMD_PTE_PADDR_MASK, MMU_L1_INTERCPUFLAGS); } diff --git a/configs/sabre-6quad/scripts/dramboot.ld b/configs/sabre-6quad/scripts/dramboot.ld index de4b7a33dd..b496eb23c4 100644 --- a/configs/sabre-6quad/scripts/dramboot.ld +++ b/configs/sabre-6quad/scripts/dramboot.ld @@ -46,7 +46,7 @@ MEMORY { oscram (W!RX) : ORIGIN = 0x00900000, LENGTH = 256K - 16K ddr3 (W!RX) : ORIGIN = 0x10800000, LENGTH = 1024M - 8M - nocache (WR) : ORIGIN = 0x80600000, LENGTH = 4K + nocache (WR) : ORIGIN = 0xe0000000, LENGTH = 4K } OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") @@ -128,7 +128,7 @@ SECTIONS _snocache = ABSOLUTE(.); *(.nocache) _enocache = ABSOLUTE(.); - } > nocahce + } > nocache /* Stabs debugging sections. */ .stab 0 : { *(.stab) } -- GitLab From b2ba12e02a7aa4d9b179bb562016f8693b5f8d10 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Nov 2016 14:23:23 -0600 Subject: [PATCH 523/734] SMP: Basic function --- arch/arm/src/armv7-a/mmu.h | 5 ++--- arch/arm/src/imx6/chip/imx_memorymap.h | 19 +++++++++++++------ arch/arm/src/imx6/imx_boot.c | 2 +- configs/sabre-6quad/scripts/dramboot.ld | 2 +- 4 files changed, 17 insertions(+), 11 deletions(-) diff --git a/arch/arm/src/armv7-a/mmu.h b/arch/arm/src/armv7-a/mmu.h index 3ea2074a7c..6440657242 100644 --- a/arch/arm/src/armv7-a/mmu.h +++ b/arch/arm/src/armv7-a/mmu.h @@ -605,9 +605,8 @@ #define MMU_L2_VECTROFLAGS (PTE_TYPE_SMALL | PTE_WRITE_THROUGH | PTE_AP_R1) #define MMU_L2_VECTORFLAGS MMU_L2_VECTRWFLAGS -#define MMU_L1_INTERCPUFLAGS (PMD_TYPE_PTE | PMD_PTE_PXN | PMD_DEVICE | \ - PMD_PTE_DOM(0)) -#define MMU_L2_INTERCPUFLAGS (PTE_TYPE_SMALL | PTE_DEVICE | PTE_AP_R1) +#define MMU_L1_INTERCPUFLAGS (PMD_TYPE_PTE | PMD_PTE_PXN | PMD_PTE_DOM(0)) +#define MMU_L2_INTERCPUFLAGS (PTE_TYPE_SMALL | PTE_DEVICE | PTE_AP_RW1) /* Mapped section size */ diff --git a/arch/arm/src/imx6/chip/imx_memorymap.h b/arch/arm/src/imx6/chip/imx_memorymap.h index bd352ce7c7..f71eecb432 100644 --- a/arch/arm/src/imx6/chip/imx_memorymap.h +++ b/arch/arm/src/imx6/chip/imx_memorymap.h @@ -917,8 +917,7 @@ * the address space. */ -#define INTERCPU_L2_PAGES 1 /* Pages allowed for inter-processor communications */ -#define L2_BASE 0x80000000 /* Beginning of L2 page table */ +#define INTERCPU_L2_PAGES 1 /* Pages allowed for inter-processor communications */ #ifndef CONFIG_ARCH_LOWVECTORS /* Memory map @@ -1051,10 +1050,14 @@ # define IMX_VECTOR_VADDR 0x00000000 #ifdef CONFIG_SMP -/* Inter-processor communications */ +/* Inter-processor communications. + * + * NOTICE that we use the unused virtual address space at 0x00400000 for + * the inter-CPU virtual communication area. + */ # define INTERCPU_PADDR (IMX_VECTOR_PADDR + VECTOR_TABLE_SIZE) -# define INTERCPU_VADDR (INTERCPU_L2_VBASE << 18) +# define INTERCPU_VADDR (0x00400000) # define INTERCPU_SIZE (INTERCPU_L2_PAGES << 12) # define INTERCPU_VSRAM (IMX_VECTOR_VSRAM + VECTOR_TABLE_SIZE) #endif @@ -1075,10 +1078,14 @@ # define IMX_VECTOR_VADDR 0xffff0000 #ifdef CONFIG_SMP -/* Inter-processor communications */ +/* Inter-processor communications + * + * NOTICE that we use the unused virtual address space at 0x00400000 for + * the inter-CPU virtual communication area. + */ # define INTERCPU_PADDR (IMX_VECTOR_PADDR - INTERCPU_L2_SIZE) -# define INTERCPU_VADDR (INTERCPU_L2_VBASE << 18) +# define INTERCPU_VADDR (0x00400000) # define INTERCPU_SIZE (INTERCPU_L2_PAGES << 12) # define INTERCPU_VSRAM (IMX_VECTOR_VSRAM - INTERCPU_L2_SIZE) #endif diff --git a/arch/arm/src/imx6/imx_boot.c b/arch/arm/src/imx6/imx_boot.c index b635a27aec..59ccb8ac06 100644 --- a/arch/arm/src/imx6/imx_boot.c +++ b/arch/arm/src/imx6/imx_boot.c @@ -256,7 +256,7 @@ static void imx_intercpu_mapping(void) /* Now set the level 1 descriptor to refer to the level 2 page table. */ - mmu_l1_setentry(INTERCPU_PADDR & PMD_PTE_PADDR_MASK, + mmu_l1_setentry(INTERCPU_L2_PBASE & PMD_PTE_PADDR_MASK, INTERCPU_VADDR & PMD_PTE_PADDR_MASK, MMU_L1_INTERCPUFLAGS); } diff --git a/configs/sabre-6quad/scripts/dramboot.ld b/configs/sabre-6quad/scripts/dramboot.ld index b496eb23c4..da35b396aa 100644 --- a/configs/sabre-6quad/scripts/dramboot.ld +++ b/configs/sabre-6quad/scripts/dramboot.ld @@ -44,9 +44,9 @@ MEMORY { + nocache (WR) : ORIGIN = 0x00400000, LENGTH = 4K oscram (W!RX) : ORIGIN = 0x00900000, LENGTH = 256K - 16K ddr3 (W!RX) : ORIGIN = 0x10800000, LENGTH = 1024M - 8M - nocache (WR) : ORIGIN = 0xe0000000, LENGTH = 4K } OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -- GitLab From 8dc79bb7ef1512be41efa087c6cd797b590de8f5 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Nov 2016 16:02:37 -0600 Subject: [PATCH 524/734] Update comments and README file --- arch/arm/src/imx6/chip/imx_memorymap.h | 20 +++++++++++++---- configs/sabre-6quad/README.txt | 31 ++++++++++++++++++++------ 2 files changed, 40 insertions(+), 11 deletions(-) diff --git a/arch/arm/src/imx6/chip/imx_memorymap.h b/arch/arm/src/imx6/chip/imx_memorymap.h index f71eecb432..38632b9a22 100644 --- a/arch/arm/src/imx6/chip/imx_memorymap.h +++ b/arch/arm/src/imx6/chip/imx_memorymap.h @@ -122,6 +122,18 @@ #define IMX_MMDCDDR_PSECTION 0x10000000 /* 10000000-ffffffff 3840 MB MMDC-DDR Controller */ /* 10000000-7fffffff 1792 MB */ +/* By default, NuttX uses a 1-1 memory mapping. So the unused, reserved + * address in the top-level memory map are candidates for other mapping uses: + * + * 00018000-000fffff Reserved -- Not used + * 00400000-007fffff Reserved -- Used as the virtual address an inter-CPU, + * un-cached memory region in SMP + * configurations + * 00d00000-00ffffff Reserved -- Not used + * 0220c000-023fffff Reserved -- Not used + * 80000000-efffffff Reserved -- Level 2 page table (See below) + */ + /* i.MX6 DMA PSECTION Offsets */ #define IMX_CAAMRAM_OFFSET 0x00000000 /* 00000000-00003fff 16 KB CAAM (16K secure RAM) */ @@ -973,13 +985,13 @@ */ # ifdef CONFIG_SMP - /* Paging L2 page table offset/size */ + /* Paging L2 page table offset/size */ # define PGTABLE_L2_OFFSET 0x000002000 # define PGTABLE_L2_SIZE 0x000001800 # else - /* Paging L2 page table offset/size */ + /* Paging L2 page table offset/size */ # define PGTABLE_L2_OFFSET 0x000002000 # define PGTABLE_L2_SIZE 0x000001c00 @@ -1007,12 +1019,12 @@ # define INTERCPU_L2_OFFSET (PGTABLE_L2_OFFSET + PGTABLE_L2_SIZE) # define INTERCPU_L2_SIZE (0x00000400) - /* on-cached inter-processor communication page table base addresses */ +/* Non-cached inter-processor communication page table base addresses */ # define INTERCPU_L2_PBASE (PGTABLE_BASE_PADDR + INTERCPU_L2_OFFSET) # define INTERCPU_L2_VBASE (PGTABLE_BASE_VADDR + INTERCPU_L2_OFFSET) - /* on-cached inter-processor communication end addresses */ +/* Non-cached inter-processor communication end addresses */ # define INTERCPU_L2_END_PADDR (INTERCPU_L2_PBASE + INTERCPU_L2_SIZE) # define INTERCPU_L2_END_VADDR (INTERCPU_L2_VBASE + INTERCPU_L2_SIZE) diff --git a/configs/sabre-6quad/README.txt b/configs/sabre-6quad/README.txt index c7d7fc57c7..afd83b14a9 100644 --- a/configs/sabre-6quad/README.txt +++ b/configs/sabre-6quad/README.txt @@ -101,6 +101,14 @@ Status +if (up_cpu_index() == 0) return 17; // REMOVE ME +2016-11-26: With regard to SMP, the major issue is cache coherency. I added + some special build logic to move spinlock data into the separate, non- + cached section. That gives an improvement in performance but there are + still hangs. These, I have determined are to other kinds of cache + coherency problems. Semaphores, message queues, etc. basically all + shared data must be made coherent. I am not sure how to do that. See + the SMP sectin below for more information. + Platform Features ================= @@ -492,12 +500,13 @@ Open Issues: 1. Currently all device interrupts are handled on CPU0 only. Critical sections will attempt to disable interrupts but will now disable interrupts only on the current - CPU (which may not be CPU0). There is a spinlock to prohibit entrance into these critical sections in interrupt handlers of other CPUs. + CPU (which may not be CPU0). There is a spinlock to prohibit entrance into these + critical sections in interrupt handlers of other CPUs. When the critical section is used to lock a resource that is also used by interupt handling, the interrupt handling logic must also take the spinlock. This will cause the interrupt handlers on other CPUs to spin until - leave_critical_section() is called. More verification is needed, however. + leave_critical_section() is called. More verification is needed. 2. Cache Concurency. This is a complex problem. There is logic in place now to clean CPU0 D-cache before starting a new CPU and for invalidating the D-Cache @@ -536,7 +545,10 @@ Open Issues: Another alternative would be to place all spinlocks in a non-cachable memory region. That is problem what will have to be done. - This is a VERIFIED PROBLEM: I have seen cases where CPU0 sets a spinlock=1 then + This is a VERIFIED PROBLEM: Cache inconsistencies appear to be the root + cause of all current SMP issues. + + I have seen cases where CPU0 sets a spinlock=1 then tries to lock the spinlock. CPU0 will wait in this case until CPU1 unlocks the spinlock. Most of this happens correctly; I can see that CPU1 does set the spinlock=0, but CPU0 never sees the change and spins forever. That is surely @@ -546,14 +558,20 @@ Open Issues: spinlock "g_cpu_paused[cpu]". CPU1 correctly sets g_cpu_paused[cpu] to zero but CPU0 never sees the change. -3. Caching probabaly interferes with spinlocks as they are currently implemented. + Caching probably interferes with spinlocks as they are currently implemented. Waiting on a cached copy of the spinlock may result in a hang or a failure to wait. Should all spinlocks go into a special "strongly ordered" memory region? - Update: Cache inconsistencies seem to be the root cause of all current SMP - issues. + No... that is not sufficient: + + 2016-11-26: With regard to SMP, the major issue is cache coherency. I added + some special build logic to move spinlock data into the separate, non- + cached section. That gives an improvement in performance but there are + still hangs. These, I have determined are to other kinds of cache + coherency problems. Semaphores, message queues, etc. basically all + shared data must be made coherent. I am not sure how to do that. Configurations ============== @@ -644,7 +662,6 @@ Configuration sub-directories Device Drivers: CONFIG_RAMLOG - smp --- This is a configuration of testing the SMP configuration. It is -- GitLab From 3353d9280f50485f7731f4d6f1f549e25d446633 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Nov 2016 17:03:57 -0600 Subject: [PATCH 525/734] i.MX6: Disable non-cached region support. Add SCU register definitions. --- arch/arm/include/armv7-a/spinlock.h | 5 +- arch/arm/src/armv7-a/scu.h | 159 +++++++++++++++++++++++++ arch/arm/src/imx6/chip/imx_memorymap.h | 10 +- arch/arm/src/imx6/imx_boot.c | 8 +- 4 files changed, 172 insertions(+), 10 deletions(-) create mode 100644 arch/arm/src/armv7-a/scu.h diff --git a/arch/arm/include/armv7-a/spinlock.h b/arch/arm/include/armv7-a/spinlock.h index 5c5d1ae6ac..f43df337b8 100644 --- a/arch/arm/include/armv7-a/spinlock.h +++ b/arch/arm/include/armv7-a/spinlock.h @@ -45,8 +45,11 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +/* Not a useful feature */ -#ifdef CONFIG_SMP +#undef SMP_INTERCPU_NONCACHED + +#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) /* In SMP configurations, save spinlocks and other inter-CPU communications * data in a non-cached memory region. */ diff --git a/arch/arm/src/armv7-a/scu.h b/arch/arm/src/armv7-a/scu.h new file mode 100644 index 0000000000..cd44da392d --- /dev/null +++ b/arch/arm/src/armv7-a/scu.h @@ -0,0 +1,159 @@ +/**************************************************************************** + * arch/arm/src/armv7-a/scu.h + * Generic Interrupt Controller Definitions + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Reference: + * Cortexâ„¢-A9 MPCore, Revision: r4p1, Technical Reference Manual, ARM DDI + * 0407I (ID091612). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_ARMV7_A_SCU_H +#define __ARCH_ARM_SRC_ARMV7_A_SCU_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "mpcore.h" /* For MPCORE_SCU_VBASE */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define SCU_CTRL_OFFSET 0x0000 /* SCU Control Register (Implementation defined) */ +#define SCU_CONFIG_OFFSET 0x0004 /* SCU Configuration Register (Implementation defined) */ +#define SCU_PWRSTATUS_OFFSET 0x0008 /* SCU CPU Power Status Register */ +#define SCU_INVALIDATE_OFFSET 0x000c /* SCU Invalidate All Registers in Secure State */ +#define SCU_FILTERSTART_OFFSET 0x0040 /* Filtering Start Address Register Defined by FILTERSTART input */ +#define SCU_FILTEREND_OFFSET 0x0044 /* Filtering End Address Register Defined by FILTEREND input */ +#define SCU_SAC_OFFSET 0x0050 /* SCU Access Control (SAC) Register */ +#define SCU_SNSAC_OFFSET 0x0054 /* SCU Non-secure Access Control (SNSAC) Register */ + +/* Register addresses *******************************************************/ + +#define SCU_CTRL (MPCORE_SCU_VBASE+SCU_CTRL_OFFSET) +#define SCU_CONFIG (MPCORE_SCU_VBASE+SCU_CONFIG_OFFSET) +#define SCU_PWRSTATUS (MPCORE_SCU_VBASE+SCU_PWRSTATUS_OFFSET) +#define SCU_INVALIDATE (MPCORE_SCU_VBASE+SCU_INVALIDATE_OFFSET) +#define SCU_FILTERSTART (MPCORE_SCU_VBASE+SCU_FILTERSTART_OFFSET) +#define SCU_FILTEREND (MPCORE_SCU_VBASE+SCU_FILTEREND_OFFSET) +#define SCU_SAC (MPCORE_SCU_VBASE+SCU_SAC_OFFSET) +#define SCU_SNSAC (MPCORE_SCU_VBASE+SCU_SNSAC_OFFSET) + +/* Register bit-field definitions *******************************************/ + +/* SCU Control Register (Implementation defined) */ + +#define SCU_CTRL_ENABLE (1 << 0) /* SCU enable */ +#define SCU_CTRL_ADDRFILTER (1 << 1) /* Address filtering enable */ +#define SCU_CTRL_RAMPARITY (1 << 2) /* SCU RAMs parity enable */ +#define SCU_CTRL_LINFILL (1 << 3) /* SCU speculative linefill enable */ +#define SCU_CTRL_PORT0 (1 << 4) /* Force all device to port0 enable */ +#define SCU_CTRL_STANDBY (1 << 5) /* SCU standby enable */ +#define SCU_CTRL_ICSTANDBY (1 << 6) /* IC standby enable */ + +/* SCU Configuration Register (Implementation defined) */ + +#define SCU_CONFIG_NCPUS_SHIFT 0 /* CPU number Number of CPUs present */ +#define SCU_CONFIG_NCPUS_MASK (3 << SCU_CONFIG_NCPUS_SHIFT) +# define SCU_CONFIG_NCPUS(r) ((((uint32_t)(r) & SCU_CONFIG_NCPUS_MASK) >> SCU_CONFIG_NCPUS_SHIFT) + 1) +#define SCU_CONFIG_SMPCPUS_SHIFT 4 /* Processors that are in SMP or AMP mode */ +#define SCU_CONFIG_SMPCPUS_MASK (15 << SCU_CONFIG_SMPCPUS_SHIFT) +# define SCU_CONFIG_CPU0_SMP (1 << 4) +# define SCU_CONFIG_CPU1_SMP (1 << 5) +# define SCU_CONFIG_CPU2_SMP (1 << 6) +# define SCU_CONFIG_CPU3_SMP (1 << 7) + +#define SCU_CONFIG_TAGRAM_16KB 0 +#define SCU_CONFIG_TAGRAM_32KB 1 +#define SCU_CONFIG_TAGRAM_64KB 2 + +#define SCU_CONFIG_CPU0_TAGRAM_SHIFT 8 /* CPU 0 tag RAM size */ +#define SCU_CONFIG_CPU0_TAGRAM_MASK (3 << SCU_CONFIG_CPU0_TAGRAM_SHIFT) +#define SCU_CONFIG_CPU1_TAGRAM_SHIFT 10 /* CPU 1 tag RAM size */ +#define SCU_CONFIG_CPU1_TAGRAM_MASK (3 << SCU_CONFIG_CPU0_TAGRAM_SHIFT) +#define SCU_CONFIG_CPU2_TAGRAM_SHIFT 12 /* CPU 1 tag RAM size */ +#define SCU_CONFIG_CPU2_TAGRAM_MASK (3 << SCU_CONFIG_CPU0_TAGRAM_SHIFT) +#define SCU_CONFIG_CPU3_TAGRAM_SHIFT 14 /* CPU 1 tag RAM size */ +#define SCU_CONFIG_CPU3_TAGRAM_MASK (3 << SCU_CONFIG_CPU0_TAGRAM_SHIFT) + +/* SCU CPU Power Status Register */ + +#define SCU_PWRSTATUS_NORMAL 0 +#define SCU_PWRSTATUS_DORMANT 2 +#define SCU_PWRSTATUS_PWROFF 3 + +#define SCU_PWRSTATUS_CPU0_SHIFT 0 /* CPU0 status Power status */ +#define SCU_PWRSTATUS_CPU0_MASK (3 << SCU_PWRSTATUS_CPU0_SHIFT) +#define SCU_PWRSTATUS_CPU1_SHIFT 8 /* CPU1 status Power status */ +#define SCU_PWRSTATUS_CPU1_MASK (3 << SCU_PWRSTATUS_CPU1_SHIFT) +#define SCU_PWRSTATUS_CPU2_SHIFT 16 /* CPU2 status Power status */ +#define SCU_PWRSTATUS_CPU2_MASK (3 << SCU_PWRSTATUS_CPU2_SHIFT) +#define SCU_PWRSTATUS_CPU3_SHIFT 24 /* CPU3 status Power status */ +#define SCU_PWRSTATUS_CPU3_MASK (3 << SCU_PWRSTATUS_CPU3_SHIFT) + +/* SCU Invalidate All Registers in Secure State */ + +#define SCU_INVALIDATE_CPU0_SHIFT 0 /* Ways that must be invalidated for CPU0 */ +#define SCU_INVALIDATE_CPU0_MASK (15 << SCU_INVALIDATE_CPU0_SHIFT) +#define SCU_INVALIDATE_CPU1_SHIFT 4 /* Ways that must be invalidated for CPU1 */ +#define SCU_INVALIDATE_CPU1_MASK (15 << SCU_INVALIDATE_CPU1_SHIFT) +#define SCU_INVALIDATE_CPU2_SHIFT 8 /* Ways that must be invalidated for CPU2 */ +#define SCU_INVALIDATE_CPU2_MASK (15 << SCU_INVALIDATE_CPU2_SHIFT) +#define SCU_INVALIDATE_CPU3_SHIFT 12 /* Ways that must be invalidated for CPU3 */ +#define SCU_INVALIDATE_CPU3_MASK (15 << SCU_INVALIDATE_CPU3_SHIFT) + +/* Filtering Start Address Register Defined by FILTERSTART input */ + +#define SCU_FILTERSTART_SHIFT 10 /* Filtering start address */ +#define SCU_FILTERSTART_MASK (0xfff << SCU_FILTERSTART_SHIFT) + +/* Filtering End Address Register Defined by FILTEREND input */ + +#define SCU_FILTEREND_SHIFT 10 /* Filtering start address */ +#define SCU_FILTEREND_MASK (0xfff << SCU_FILTEREND_SHIFT) + +/* SCU Access Control (SAC) Register */ + +#define SCU_SAC_CPU(n) (1 << (n)) /* CPUn may access components */ + +/* SCU Non-secure Access Control (SNSAC) Register */ + +#define SCU_SNSAC_COMP_CPU(n) (1 << (n)) /* CPUn has non-secure access to components */ +#define SCU_SNSAC_PTIM_CPU(n) (1 << ((n)+4)) /* CPUn has non-secure access to private timers */ +#define SCU_SNSAC_GTIM_CPU(n) (1 << ((n)+8)) /* CPUn has non-secure access to global timer */ + +#endif /* __ARCH_ARM_SRC_ARMV7_A_SCU_H */ diff --git a/arch/arm/src/imx6/chip/imx_memorymap.h b/arch/arm/src/imx6/chip/imx_memorymap.h index 38632b9a22..17304c2474 100644 --- a/arch/arm/src/imx6/chip/imx_memorymap.h +++ b/arch/arm/src/imx6/chip/imx_memorymap.h @@ -959,7 +959,7 @@ # define VECTOR_L2_END_PADDR (VECTOR_L2_PBASE + VECTOR_L2_SIZE) # define VECTOR_L2_END_VADDR (VECTOR_L2_VBASE + VECTOR_L2_SIZE) -# ifdef CONFIG_SMP +# if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) /* Paging L2 page table offset/size */ # define PGTABLE_L2_OFFSET 0x000002400 @@ -984,7 +984,7 @@ * cacheable, inter-processor communication data. */ -# ifdef CONFIG_SMP +# if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) /* Paging L2 page table offset/size */ # define PGTABLE_L2_OFFSET 0x000002000 @@ -1013,7 +1013,7 @@ #define PGTABLE_L2_END_PADDR (PGTABLE_L2_PBASE + PGTABLE_L2_SIZE) #define PGTABLE_L2_END_VADDR (PGTABLE_L2_VBASE + PGTABLE_L2_SIZE) -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) /* Non-cached inter-processor communication data */ # define INTERCPU_L2_OFFSET (PGTABLE_L2_OFFSET + PGTABLE_L2_SIZE) @@ -1061,7 +1061,7 @@ # define IMX_VECTOR_VSRAM IMX_OCRAM_VBASE # define IMX_VECTOR_VADDR 0x00000000 -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) /* Inter-processor communications. * * NOTICE that we use the unused virtual address space at 0x00400000 for @@ -1089,7 +1089,7 @@ # define IMX_VECTOR_VSRAM (IMX_OCRAM_VBASE + IMX_OCRAM_SIZE - VECTOR_TABLE_SIZE) # define IMX_VECTOR_VADDR 0xffff0000 -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) /* Inter-processor communications * * NOTICE that we use the unused virtual address space at 0x00400000 for diff --git a/arch/arm/src/imx6/imx_boot.c b/arch/arm/src/imx6/imx_boot.c index 59ccb8ac06..eb731a3315 100644 --- a/arch/arm/src/imx6/imx_boot.c +++ b/arch/arm/src/imx6/imx_boot.c @@ -233,7 +233,7 @@ static void imx_vectormapping(void) * ****************************************************************************/ -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) static void imx_intercpu_mapping(void) { uint32_t intercpu_paddr = INTERCPU_PADDR & PTE_SMALL_PADDR_MASK; @@ -433,7 +433,7 @@ void arm_boot(void) #if defined(CONFIG_ARCH_RAMFUNCS) const uint32_t *src; #endif -#if defined(CONFIG_ARCH_RAMFUNCS) || defined(CONFIG_SMP) +#if defined(CONFIG_ARCH_RAMFUNCS) || defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) uint32_t *dest; #endif @@ -458,7 +458,7 @@ void arm_boot(void) imx_vectormapping(); imx_lowputc('B'); -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) /* Provide a special mapping for the OCRAM interrupt vector positioned in * high memory. */ @@ -545,7 +545,7 @@ void arm_boot(void) imx_lowputc('L'); #endif -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) /* Initialize the uncached, inter-CPU communications area */ for (dest = &_snocache; dest < &_enocache; ) -- GitLab From 546e352830348fa165992d0968b63a489bf2dfa3 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Nov 2016 17:46:20 -0600 Subject: [PATCH 526/734] i.MX6: Add some controls to enable SMP cache coherency in SMP mode --- arch/arm/src/armv7-a/arm_scu.c | 66 +++++++++++++++++++++++++++++++ arch/arm/src/armv7-a/scu.h | 16 ++++++++ arch/arm/src/imx6/Make.defs | 1 + arch/arm/src/imx6/imx_cpuboot.c | 7 ++++ arch/arm/src/imx6/imx_irq.c | 7 ++++ configs/sabre-6quad/README.txt | 70 ++++++--------------------------- 6 files changed, 109 insertions(+), 58 deletions(-) create mode 100644 arch/arm/src/armv7-a/arm_scu.c diff --git a/arch/arm/src/armv7-a/arm_scu.c b/arch/arm/src/armv7-a/arm_scu.c new file mode 100644 index 0000000000..24fa156e3c --- /dev/null +++ b/arch/arm/src/armv7-a/arm_scu.c @@ -0,0 +1,66 @@ +/**************************************************************************** + * arch/arm/src/armv7-a/arm_undefinedinsn.c + * + * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "up_arch.h" +#include "scu.h" + +#ifdef CONFIG_SMP + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_enable_smp + * + * Description: + * Enable the SCU and make certain that current CPU is participating in + * the SMP cache coherency. + * + ****************************************************************************/ + +void arm_enable_smp(int cpu) +{ + modifyreg32(SCU_CONFIG, 0, SCU_CONFIG_CPU_SMP(cpu)); + modifyreg32(SCU_CTRL, 0, SCU_CTRL_ENABLE); +} + +#endif diff --git a/arch/arm/src/armv7-a/scu.h b/arch/arm/src/armv7-a/scu.h index cd44da392d..a51f09cec4 100644 --- a/arch/arm/src/armv7-a/scu.h +++ b/arch/arm/src/armv7-a/scu.h @@ -92,6 +92,7 @@ # define SCU_CONFIG_NCPUS(r) ((((uint32_t)(r) & SCU_CONFIG_NCPUS_MASK) >> SCU_CONFIG_NCPUS_SHIFT) + 1) #define SCU_CONFIG_SMPCPUS_SHIFT 4 /* Processors that are in SMP or AMP mode */ #define SCU_CONFIG_SMPCPUS_MASK (15 << SCU_CONFIG_SMPCPUS_SHIFT) +# define SCU_CONFIG_CPU_SMP(n) (1 << ((n)+4)) # define SCU_CONFIG_CPU0_SMP (1 << 4) # define SCU_CONFIG_CPU1_SMP (1 << 5) # define SCU_CONFIG_CPU2_SMP (1 << 6) @@ -156,4 +157,19 @@ #define SCU_SNSAC_PTIM_CPU(n) (1 << ((n)+4)) /* CPUn has non-secure access to private timers */ #define SCU_SNSAC_GTIM_CPU(n) (1 << ((n)+8)) /* CPUn has non-secure access to global timer */ +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_enable_smp + * + * Description: + * Enable the SCU and make certain that current CPU is participating in + * the SMP cache coherency. + * + ****************************************************************************/ + +void arm_enable_smp(int cpu); + #endif /* __ARCH_ARM_SRC_ARMV7_A_SCU_H */ diff --git a/arch/arm/src/imx6/Make.defs b/arch/arm/src/imx6/Make.defs index 4870aa1d1d..9986ac23d9 100644 --- a/arch/arm/src/imx6/Make.defs +++ b/arch/arm/src/imx6/Make.defs @@ -81,6 +81,7 @@ CMN_CSRCS += arm_unblocktask.c arm_undefinedinsn.c ifeq ($(CONFIG_SMP),y) CMN_CSRCS += arm_cpuindex.c arm_cpustart.c arm_cpupause.c arm_cpuidlestack.c +CMN_CSRCS += arm_scu.c endif ifeq ($(CONFIG_DEBUG_IRQ_INFO),y) diff --git a/arch/arm/src/imx6/imx_cpuboot.c b/arch/arm/src/imx6/imx_cpuboot.c index 50b23b5c1d..db08757579 100644 --- a/arch/arm/src/imx6/imx_cpuboot.c +++ b/arch/arm/src/imx6/imx_cpuboot.c @@ -52,6 +52,7 @@ #include "sctlr.h" #include "smp.h" #include "fpu.h" +#include "scu.h" #include "gic.h" #include "cp15_cacheops.h" @@ -266,6 +267,12 @@ void arm_cpu_boot(int cpu) arm_fpuconfig(); #endif +#ifdef CONFIG_SMP + /* Enable SMP cache coherency for CPU0 */ + + arm_enable_smp(cpu); +#endif + /* Initialize the Generic Interrupt Controller (GIC) for CPUn (n != 0) */ arm_gic_initialize(); diff --git a/arch/arm/src/imx6/imx_irq.c b/arch/arm/src/imx6/imx_irq.c index e00a8e9527..ecf2f197ac 100644 --- a/arch/arm/src/imx6/imx_irq.c +++ b/arch/arm/src/imx6/imx_irq.c @@ -45,6 +45,7 @@ #include "up_internal.h" #include "sctlr.h" +#include "scu.h" #include "gic.h" /**************************************************************************** @@ -108,6 +109,12 @@ void up_irqinitialize(void) arm_gic0_initialize(); /* Initialization unique to CPU0 */ arm_gic_initialize(); /* Initialization common to all CPUs */ +#ifdef CONFIG_SMP + /* Enable SMP cache coherency for CPU0 */ + + arm_enable_smp(0); +#endif + #ifdef CONFIG_ARCH_LOWVECTORS /* If CONFIG_ARCH_LOWVECTORS is defined, then the vectors located at the * beginning of the .text region must appear at address at the address diff --git a/configs/sabre-6quad/README.txt b/configs/sabre-6quad/README.txt index afd83b14a9..3a7988d029 100644 --- a/configs/sabre-6quad/README.txt +++ b/configs/sabre-6quad/README.txt @@ -107,7 +107,10 @@ Status still hangs. These, I have determined are to other kinds of cache coherency problems. Semaphores, message queues, etc. basically all shared data must be made coherent. I am not sure how to do that. See - the SMP sectin below for more information. + the SMP section below for more information. + + I also added some SCU controls that should enable cache consistency for SMP + CPUs, but I don't think I have that working right yet. Platform Features ================= @@ -508,70 +511,21 @@ Open Issues: This will cause the interrupt handlers on other CPUs to spin until leave_critical_section() is called. More verification is needed. -2. Cache Concurency. This is a complex problem. There is logic in place now to - clean CPU0 D-cache before starting a new CPU and for invalidating the D-Cache - when the new CPU is started. REVISIT: Seems that this should not be necessary. - If the Shareable bit set in the MMU mappings and my understanding is that this - should keep cache coherency at least within a cluster. I need to study more - how the inner and outer shareable attribute works to control cacheing - - But there may are many, many more such cache coherency issues if I cannot find - a systematic way to manage cache coherency. - - http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dht0008a/CJABEHDA.html - http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/CEGDBEJE.html - - Try: - - --- mmu.h.orig 2016-05-20 13:09:34.773462000 -0600 - +++ mmu.h 2016-05-20 13:03:13.261978100 -0600 - @@ -572,8 +572,14 @@ - - #define MMU_ROMFLAGS (PMD_TYPE_SECT | PMD_SECT_AP_R1 | PMD_CACHEABLE | \ - PMD_SECT_DOM(0)) - -#define MMU_MEMFLAGS (PMD_TYPE_SECT | PMD_SECT_AP_RW1 | PMD_CACHEABLE | \ - +#ifdef CONFIG_SMP - + - +# define MMU_MEMFLAGS (PMD_TYPE_SECT | PMD_SECT_AP_RW1 | PMD_CACHEABLE | \ - + PMD_SECT_S | PMD_SECT_DOM(0)) - +#else - +# define MMU_MEMFLAGS (PMD_TYPE_SECT | PMD_SECT_AP_RW1 | PMD_CACHEABLE | \ - PMD_SECT_DOM(0)) - +#endif - #define MMU_IOFLAGS (PMD_TYPE_SECT | PMD_SECT_AP_RW1 | PMD_DEVICE | \ - PMD_SECT_DOM(0) | PMD_SECT_XN) - #define MMU_STRONGLY_ORDERED (PMD_TYPE_SECT | PMD_SECT_AP_RW1 | \ - - Another alternative would be to place all spinlocks in a non-cachable memory - region. That is problem what will have to be done. +2. Cache Concurency. Cache coherency in SMP configurations is managed by the the + CPU. I don't think I have the set up correctly yet. - This is a VERIFIED PROBLEM: Cache inconsistencies appear to be the root - cause of all current SMP issues. - - I have seen cases where CPU0 sets a spinlock=1 then - tries to lock the spinlock. CPU0 will wait in this case until CPU1 unlocks the - spinlock. Most of this happens correctly; I can see that CPU1 does set the - spinlock=0, but CPU0 never sees the change and spins forever. That is surely - a consequence of cache issues. - - This was observed between up_cpu_pause() and arm_pause_handler() with the - spinlock "g_cpu_paused[cpu]". CPU1 correctly sets g_cpu_paused[cpu] to zero - but CPU0 never sees the change. - - Caching probably interferes with spinlocks as they are currently implemented. - Waiting on a cached copy of the spinlock may result in a hang or a failure to - wait. - - Should all spinlocks go into a special "strongly ordered" memory region? - - No... that is not sufficient: + Currently cache inconsistencies appear to be the root cause of all current SMP + issues. 2016-11-26: With regard to SMP, the major issue is cache coherency. I added some special build logic to move spinlock data into the separate, non- cached section. That gives an improvement in performance but there are still hangs. These, I have determined are to other kinds of cache coherency problems. Semaphores, message queues, etc. basically all - shared data must be made coherent. I am not sure how to do that. + shared data must be made coherent. + + I also added some SCU controls that should enable cache consistency for SMP + CPUs, but I don't think I have that working right yet. Configurations ============== -- GitLab From 3f6eadc238eacb800c00782f112d11e42b9b4c04 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 26 Nov 2016 18:41:48 -0600 Subject: [PATCH 527/734] ARMv7-A: Fix some SCU SMP logic --- arch/arm/src/armv7-a/arm_scu.c | 95 +++++++++++++++++++++++++++++++++- arch/arm/src/armv7-a/scu.h | 1 + 2 files changed, 94 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_scu.c b/arch/arm/src/armv7-a/arm_scu.c index 24fa156e3c..ce857e1b2d 100644 --- a/arch/arm/src/armv7-a/arm_scu.c +++ b/arch/arm/src/armv7-a/arm_scu.c @@ -39,11 +39,78 @@ #include +#include + +#include + #include "up_arch.h" +#include "sctlr.h" #include "scu.h" #ifdef CONFIG_SMP +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_get_actlr + * + * Description: + * Get the contents of the ACTLR register + * + ****************************************************************************/ + +static inline uint32_t arm_get_actlr(void) +{ + uint32_t actlr; + + __asm__ __volatile__ + ( + "\tmrc p15, 0, %0, c1, c0, 1\n" /* Read ACTLR */ + : "=r"(actlr) + : + : + ); + + return actlr; +} + +/**************************************************************************** + * Name: arm_set_actlr + * + * Description: + * Set the contents of the ACTLR register + * + ****************************************************************************/ + +static inline void arm_set_actlr(uint32_t actlr) +{ + __asm__ __volatile__ + ( + "\tmcr p15, 0, %0, c1, c0, 1\n" /* Write ACTLR */ + : + : "r"(actlr) + : + ); +} + +/**************************************************************************** + * Name: arm_modify_actlr + * + * Description: + * Set the bits in the ACTLR register + * + ****************************************************************************/ + +static inline void arm_modify_actlr(uint32_t setbits) +{ + irqstate_t flags = enter_critical_section(); + uint32_t actlr = arm_get_actlr(); + arm_set_actlr(actlr | setbits); + leave_critical_section(flags); +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -59,8 +126,32 @@ void arm_enable_smp(int cpu) { - modifyreg32(SCU_CONFIG, 0, SCU_CONFIG_CPU_SMP(cpu)); - modifyreg32(SCU_CTRL, 0, SCU_CTRL_ENABLE); + /* Invalidate the data cache -- Missing logic. */ + + /* Handle actions unique to CPU0 */ + + if (cpu == 0) + { + /* Invalidate the SCU duplicate tags for all processors */ + + putreg32((SCU_INVALIDATE_ALL_WAYS << SCU_INVALIDATE_CPU0_SHIFT) | + (SCU_INVALIDATE_ALL_WAYS << SCU_INVALIDATE_CPU1_SHIFT) | + (SCU_INVALIDATE_ALL_WAYS << SCU_INVALIDATE_CPU2_SHIFT) | + (SCU_INVALIDATE_ALL_WAYS << SCU_INVALIDATE_CPU3_SHIFT), + SCU_INVALIDATE); + + /* Invalidate the L2C-310 -- Missing logic. */ + + /* Enable the SCU */ + + modifyreg32(SCU_CTRL, 0, SCU_CTRL_ENABLE); /* CPU0 only */ + } + + /* Enable the data cache -- Missing logic. */ + + /* This CPU now participates the SMP cache coherency */ + + arm_modify_actlr(ACTLR_SMP); } #endif diff --git a/arch/arm/src/armv7-a/scu.h b/arch/arm/src/armv7-a/scu.h index a51f09cec4..a84fb0cc4f 100644 --- a/arch/arm/src/armv7-a/scu.h +++ b/arch/arm/src/armv7-a/scu.h @@ -128,6 +128,7 @@ /* SCU Invalidate All Registers in Secure State */ +#define SCU_INVALIDATE_ALL_WAYS 15 #define SCU_INVALIDATE_CPU0_SHIFT 0 /* Ways that must be invalidated for CPU0 */ #define SCU_INVALIDATE_CPU0_MASK (15 << SCU_INVALIDATE_CPU0_SHIFT) #define SCU_INVALIDATE_CPU1_SHIFT 4 /* Ways that must be invalidated for CPU1 */ -- GitLab From 278d8330d6f48590088ac7ea498a97d72b45459b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 27 Nov 2016 02:59:42 +0000 Subject: [PATCH 528/734] arm_scu.c edited online with Bitbucket. Fux some typos. --- arch/arm/src/armv7-a/arm_scu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_scu.c b/arch/arm/src/armv7-a/arm_scu.c index ce857e1b2d..8779b04606 100644 --- a/arch/arm/src/armv7-a/arm_scu.c +++ b/arch/arm/src/armv7-a/arm_scu.c @@ -1,7 +1,7 @@ /**************************************************************************** - * arch/arm/src/armv7-a/arm_undefinedinsn.c + * arch/arm/src/armv7-a/arm_scu.c * - * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without -- GitLab From cd54c71dc1e421afdfce192d9b4173967065f815 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 27 Nov 2016 10:21:20 -0600 Subject: [PATCH 529/734] ARMv7-A/i.MX6: Modify handling of the SMP cache coherency configuration so that it is identical to the steps from the TRM. Makes no differenct, however. --- TODO | 50 +++++------ arch/arm/src/armv7-a/arm_cpuhead.S | 6 +- arch/arm/src/armv7-a/arm_cpustart.c | 10 ++- arch/arm/src/armv7-a/arm_head.S | 8 +- arch/arm/src/armv7-a/arm_pghead.S | 8 +- arch/arm/src/armv7-a/arm_scu.c | 106 ++++++++++++++++++------ arch/arm/src/imx6/imx_boot.c | 54 +++++++----- arch/arm/src/imx6/imx_boot.h | 29 ++++++- arch/arm/src/imx6/imx_cpuboot.c | 12 --- arch/arm/src/imx6/imx_irq.c | 7 -- configs/sabre-6quad/README.txt | 23 ++--- configs/sabre-6quad/src/imx_boardinit.c | 32 ++++++- 12 files changed, 227 insertions(+), 118 deletions(-) diff --git a/TODO b/TODO index 366533c534..6234b44e6d 100644 --- a/TODO +++ b/TODO @@ -308,33 +308,33 @@ o Task/Scheduler (sched/) o SMP ^^^ - Title: SPINLOCKS AND DATA CACHES - Description: If spinlocks are used in a system with a data cache, then there - may be a problem with cache coherency in some CPU architectures: - When one CPU modifies the spinlock, the changes may not be - visible to another CPU if it does not share the data cache. - That would cause failure in the spinlock logic. + Title: SMP AND DATA CACHES + Description: When spinlocks, semaphores, etc. are used in an SMP system with + a data cache, then there may be problems with cache coherency + in some CPU architectures: When one CPU modifies the shared + object, the changes may not be visible to another CPU if it + does not share the data cache. That would cause failure in + the IPC logic. Flushing the D-cache on writes and invalidating before a read is - not really an option. spinlocks are normally 8-bits in size and - cache lines are typically 32-bytes so that would have side effects - unless the spinlocks were made to be the same size as one cache - line. - - This might be doable if a write-through cache is used. Then you - could always safely invalidate the cache line before reading the - spinlock because there should never be any dirty cache lines in - this case. - - The better option is to add compiler independent "ornamentation" - to the spinlock so that the spinlocks are all linked together - into a separate, non-cacheable memory regions. Because of - region alignment and minimum region mapping sizes this could - still be wasteful of memory. This would work in systems that - have both data cache and either an MPU or an MMU. - Status: Open - Priority: High. spinlocks, and hence SMP, will not work on such systems - without this change. + not really an option. That would essentially effect every memory + access and there may be side-effects due to cache line sizes + and alignment. + + For the same reason a separate, non-cacheable memory region is + not an option. Essentially all data would have to go in the + non-cached region and you would have no benefit from the data + cache. + + On ARM Cortex-A, each CPU has a separate data cache. However, + the MPCore's Snoop Controller Unit supports coherency among + the different caches. The SCU is enabled by the SCU control + register and each CPU participates in the SMP coherency by + setting the ACTLR_SMP bit in the auxiliary control register + (ACTLR). + + Status: Closed + Priority: High on platforms that may have the issue. o Memory Management (mm/) ^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/arch/arm/src/armv7-a/arm_cpuhead.S b/arch/arm/src/armv7-a/arm_cpuhead.S index 487fee0a46..2f8387bdcd 100644 --- a/arch/arm/src/armv7-a/arm_cpuhead.S +++ b/arch/arm/src/armv7-a/arm_cpuhead.S @@ -308,7 +308,11 @@ __cpu3_start: orr r0, r0, #(SCTLR_RR) #endif -#ifndef CPU_DCACHE_DISABLE + /* In SMP configurations, the data cache will not be enabled until later + * after SMP cache coherency has been setup. + */ + +#if !defined(CPU_DCACHE_DISABLE) && !defined(CONFIG_SMP) /* Dcache enable * * SCTLR_C Bit 2: DCache enable diff --git a/arch/arm/src/armv7-a/arm_cpustart.c b/arch/arm/src/armv7-a/arm_cpustart.c index 88906a717d..38928e7aec 100644 --- a/arch/arm/src/armv7-a/arm_cpustart.c +++ b/arch/arm/src/armv7-a/arm_cpustart.c @@ -45,8 +45,9 @@ #include #include "up_internal.h" -#include "gic.h" #include "cp15_cacheops.h" +#include "gic.h" +#include "scu.h" #include "sched/sched.h" #ifdef CONFIG_SMP @@ -105,8 +106,13 @@ static inline void arm_registerdump(FAR struct tcb_s *tcb) int arm_start_handler(int irq, FAR void *context) { FAR struct tcb_s *tcb; + int cpu = up_cpu_index(); + + sinfo("CPU%d Started\n", cpu); + + /* Enable SMP cache coherency for the CPU */ - sinfo("CPU%d Started\n", up_cpu_index()); + arm_enable_smp(cpu); /* Reset scheduler parameters */ diff --git a/arch/arm/src/armv7-a/arm_head.S b/arch/arm/src/armv7-a/arm_head.S index c98ab30719..27c2a5b4dc 100644 --- a/arch/arm/src/armv7-a/arm_head.S +++ b/arch/arm/src/armv7-a/arm_head.S @@ -450,7 +450,11 @@ __start: orr r0, r0, #(SCTLR_RR) #endif -#ifndef CPU_DCACHE_DISABLE + /* In SMP configurations, the data cache will not be enabled until later + * after SMP cache coherency has been setup. + */ + +#if !defined(CPU_DCACHE_DISABLE) && !defined(CONFIG_SMP) /* Dcache enable * * SCTLR_C Bit 2: DCache enable @@ -638,7 +642,7 @@ __start: #endif /* Perform early C-level, platform-specific initialization. Logic - * within arm_boot() must configure SDRAM and call arm_ram_initailize. + * within arm_boot() must configure SDRAM and call arm_data_initialize(). */ bl arm_boot diff --git a/arch/arm/src/armv7-a/arm_pghead.S b/arch/arm/src/armv7-a/arm_pghead.S index 1a546c813d..1dda0acdd9 100644 --- a/arch/arm/src/armv7-a/arm_pghead.S +++ b/arch/arm/src/armv7-a/arm_pghead.S @@ -434,7 +434,11 @@ __start: orr r0, r0, #(SCTLR_RR) #endif -#ifndef CPU_DCACHE_DISABLE + /* In SMP configurations, the data cache will not be enabled until later + * after SMP cache coherency has been setup. + */ + +#if !defined(CPU_DCACHE_DISABLE) && !defined(CONFIG_SMP) /* Dcache enable * * SCTLR_C Bit 2: DCache enable @@ -670,7 +674,7 @@ __start: #endif /* Perform early C-level, platform-specific initialization. Logic - * within arm_boot() must configure SDRAM and call arm_ram_initailize. + * within arm_boot() must configure SDRAM and call arm_data_initialize(). */ bl arm_boot diff --git a/arch/arm/src/armv7-a/arm_scu.c b/arch/arm/src/armv7-a/arm_scu.c index 8779b04606..e1fdd52925 100644 --- a/arch/arm/src/armv7-a/arm_scu.c +++ b/arch/arm/src/armv7-a/arm_scu.c @@ -41,18 +41,59 @@ #include -#include - #include "up_arch.h" +#include "cp15_cacheops.h" #include "sctlr.h" #include "scu.h" #ifdef CONFIG_SMP /**************************************************************************** - * Public Functions + * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: arm_get_sctlr + * + * Description: + * Get the contents of the SCTLR register + * + ****************************************************************************/ + +static inline uint32_t arm_get_sctlr(void) +{ + uint32_t sctlr; + + __asm__ __volatile__ + ( + "\tmrc p15, 0, %0, c1, c0, 0\n" /* Read SCTLR */ + : "=r"(sctlr) + : + : + ); + + return sctlr; +} + +/**************************************************************************** + * Name: arm_set_sctlr + * + * Description: + * Set the contents of the SCTLR register + * + ****************************************************************************/ + +static inline void arm_set_sctlr(uint32_t sctlr) +{ + __asm__ __volatile__ + ( + "\tmcr p15, 0, %0, c1, c0, 0\n" /* Write SCTLR */ + : + : "r"(sctlr) + : + ); +} + /**************************************************************************** * Name: arm_get_actlr * @@ -95,22 +136,6 @@ static inline void arm_set_actlr(uint32_t actlr) ); } -/**************************************************************************** - * Name: arm_modify_actlr - * - * Description: - * Set the bits in the ACTLR register - * - ****************************************************************************/ - -static inline void arm_modify_actlr(uint32_t setbits) -{ - irqstate_t flags = enter_critical_section(); - uint32_t actlr = arm_get_actlr(); - arm_set_actlr(actlr | setbits); - leave_critical_section(flags); -} - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -122,13 +147,17 @@ static inline void arm_modify_actlr(uint32_t setbits) * Enable the SCU and make certain that current CPU is participating in * the SMP cache coherency. * + * Assumption: + * Called early in the CPU start-up. No special critical sections are + * needed if only CPU-private registers are modified. + * ****************************************************************************/ void arm_enable_smp(int cpu) { - /* Invalidate the data cache -- Missing logic. */ + uint32_t regval; - /* Handle actions unique to CPU0 */ + /* Handle actions unique to CPU0 which comes up first */ if (cpu == 0) { @@ -140,18 +169,45 @@ void arm_enable_smp(int cpu) (SCU_INVALIDATE_ALL_WAYS << SCU_INVALIDATE_CPU3_SHIFT), SCU_INVALIDATE); + /* Invalidate CPUn L1 data cache so that is will we be reloaded from + * coherent L2. + */ + + cp15_invalidate_dcache_all(); + /* Invalidate the L2C-310 -- Missing logic. */ /* Enable the SCU */ - modifyreg32(SCU_CTRL, 0, SCU_CTRL_ENABLE); /* CPU0 only */ + regval = getreg32(SCU_CTRL); + regval |= SCU_CTRL_ENABLE; + putreg32(regval, SCU_CTRL); + } + + /* Actions for other CPUs */ + + else + { + /* Invalidate CPUn L1 data cache so that is will we be reloaded from + * coherent L2. + */ + + cp15_invalidate_dcache_all(); + + /* Wait for the SCU to be enabled by the primary processor -- should + * not be necessary. + */ } - /* Enable the data cache -- Missing logic. */ + /* Enable the data cache, set the SMP mode with ACTLR.SMP=1. */ - /* This CPU now participates the SMP cache coherency */ + regval = arm_get_actlr(); + regval |= ACTLR_SMP; + arm_set_actlr(regval); - arm_modify_actlr(ACTLR_SMP); + regval = arm_get_sctlr(); + regval |= SCTLR_C; + arm_set_sctlr(regval); } #endif diff --git a/arch/arm/src/imx6/imx_boot.c b/arch/arm/src/imx6/imx_boot.c index eb731a3315..aaa249e5c0 100644 --- a/arch/arm/src/imx6/imx_boot.c +++ b/arch/arm/src/imx6/imx_boot.c @@ -52,6 +52,7 @@ #include "chip.h" #include "arm.h" #include "mmu.h" +#include "scu.h" #include "cache.h" #include "fpu.h" #include "up_internal.h" @@ -450,13 +451,21 @@ void arm_boot(void) */ imx_cpu_disable(); + imx_lowputc('B'); + +#ifdef CONFIG_SMP + /* Enable SMP cache coherency for CPU0 */ + + arm_enable_smp(0); + imx_lowputc('C'); +#endif /* Provide a special mapping for the OCRAM interrupt vector positioned in * high memory. */ imx_vectormapping(); - imx_lowputc('B'); + imx_lowputc('D'); #if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) /* Provide a special mapping for the OCRAM interrupt vector positioned in @@ -464,7 +473,7 @@ void arm_boot(void) */ imx_intercpu_mapping(); - imx_lowputc('C'); + imx_lowputc('E'); #endif #ifdef CONFIG_ARCH_RAMFUNCS @@ -479,14 +488,14 @@ void arm_boot(void) *dest++ = *src++; } - imx_lowputc('D'); + imx_lowputc('F'); /* Flush the copied RAM functions into physical RAM so that will * be available when fetched into the I-Cache. */ arch_clean_dcache((uintptr_t)&_sramfuncs, (uintptr_t)&_eramfuncs) - imx_lowputc('E'); + imx_lowputc('G'); #endif /* Setup up vector block. _vector_start and _vector_end are exported from @@ -494,37 +503,35 @@ void arm_boot(void) */ imx_copyvectorblock(); - imx_lowputc('F'); + imx_lowputc('H'); /* Disable the watchdog timer */ imx_wdtdisable(); - imx_lowputc('G'); + imx_lowputc('I'); /* Initialize clocking to settings provided by board-specific logic */ imx_clockconfig(); - imx_lowputc('H'); + imx_lowputc('J'); #ifdef CONFIG_ARCH_FPU /* Initialize the FPU */ arm_fpuconfig(); - imx_lowputc('I'); + imx_lowputc('K'); #endif - /* Perform board-specific initialization, This must include: - * - * - Initialization of board-specific memory resources (e.g., SDRAM) - * - Configuration of board specific resources (PIOs, LEDs, etc). + /* Perform board-specific memroy initialization, This must include + * initialization of board-specific memory resources (e.g., SDRAM) * * NOTE: We must use caution prior to this point to make sure that * the logic does not access any global variables that might lie * in SDRAM. */ - imx_board_initialize(); - imx_lowputc('J'); + imx_memory_initialize(); + imx_lowputc('L'); #ifdef NEED_SDRAM_REMAPPING /* SDRAM was configured in a temporary state to support low-level @@ -533,7 +540,7 @@ void arm_boot(void) */ imx_remap(); - imx_lowputc('K'); + imx_lowputc('M'); #endif #ifdef CONFIG_BOOT_SDRAM_DATA @@ -542,9 +549,16 @@ void arm_boot(void) */ arm_data_initialize(); - imx_lowputc('L'); + imx_lowputc('N'); #endif + /* Perform board-specific device initialization. This would include + * configuration of board specific resources such as GPIOs, LEDs, etc. + */ + + imx_board_initialize(); + imx_lowputc('O'); + #if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) /* Initialize the uncached, inter-CPU communications area */ @@ -553,13 +567,13 @@ void arm_boot(void) *dest++ = 0; } - imx_lowputc('M'); + imx_lowputc('P'); #endif /* Perform common, low-level chip initialization (might do nothing) */ imx_lowsetup(); - imx_lowputc('N'); + imx_lowputc('Q'); #ifdef USE_EARLYSERIALINIT /* Perform early serial initialization if we are going to use the serial @@ -567,7 +581,7 @@ void arm_boot(void) */ imx_earlyserialinit(); - imx_lowputc('O'); + imx_lowputc('R'); #endif /* Now we can enable all other CPUs. The enabled CPUs will start execution @@ -576,6 +590,6 @@ void arm_boot(void) */ imx_cpu_enable(); - imx_lowputc('P'); + imx_lowputc('S'); imx_lowputc('\n'); } diff --git a/arch/arm/src/imx6/imx_boot.h b/arch/arm/src/imx6/imx_boot.h index 11c1ef56fe..7f98d347ac 100644 --- a/arch/arm/src/imx6/imx_boot.h +++ b/arch/arm/src/imx6/imx_boot.h @@ -110,14 +110,37 @@ void imx_cpu_enable(void); # define imx_cpu_enable() #endif +/**************************************************************************** + * Name: imx_memory_initialize + * + * Description: + * All i.MX6 architectures must provide the following entry point. This + * entry point is called early in the initialization before memory has + * been configured. This board-specific function is responsible for + * configuring any on-board memories. + * + * Logic in imx_memory_initialize must be careful to avoid using any + * global variables because those will be uninitialized at the time this + * function is called. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imx_memory_initialize(void); + /**************************************************************************** * Name: imx_board_initialize * * Description: * All i.MX6 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. + * entry point is called in the initialization phase -- after + * imx_memory_initialize and after all memory has been configured and + * mapped but before any devices have been initialized. * * Input Parameters: * None diff --git a/arch/arm/src/imx6/imx_cpuboot.c b/arch/arm/src/imx6/imx_cpuboot.c index db08757579..4b288b17d1 100644 --- a/arch/arm/src/imx6/imx_cpuboot.c +++ b/arch/arm/src/imx6/imx_cpuboot.c @@ -52,9 +52,7 @@ #include "sctlr.h" #include "smp.h" #include "fpu.h" -#include "scu.h" #include "gic.h" -#include "cp15_cacheops.h" #ifdef CONFIG_SMP @@ -267,12 +265,6 @@ void arm_cpu_boot(int cpu) arm_fpuconfig(); #endif -#ifdef CONFIG_SMP - /* Enable SMP cache coherency for CPU0 */ - - arm_enable_smp(cpu); -#endif - /* Initialize the Generic Interrupt Controller (GIC) for CPUn (n != 0) */ arm_gic_initialize(); @@ -304,10 +296,6 @@ void arm_cpu_boot(int cpu) (void)up_irq_enable(); #endif - /* Invalidate CPUn L1 so that is will be reloaded from coherent L2. */ - - cp15_invalidate_dcache_all(); - /* The next thing that we expect to happen is for logic running on CPU0 * to call up_cpu_start() which generate an SGI and a context switch to * the configured NuttX IDLE task. diff --git a/arch/arm/src/imx6/imx_irq.c b/arch/arm/src/imx6/imx_irq.c index ecf2f197ac..e00a8e9527 100644 --- a/arch/arm/src/imx6/imx_irq.c +++ b/arch/arm/src/imx6/imx_irq.c @@ -45,7 +45,6 @@ #include "up_internal.h" #include "sctlr.h" -#include "scu.h" #include "gic.h" /**************************************************************************** @@ -109,12 +108,6 @@ void up_irqinitialize(void) arm_gic0_initialize(); /* Initialization unique to CPU0 */ arm_gic_initialize(); /* Initialization common to all CPUs */ -#ifdef CONFIG_SMP - /* Enable SMP cache coherency for CPU0 */ - - arm_enable_smp(0); -#endif - #ifdef CONFIG_ARCH_LOWVECTORS /* If CONFIG_ARCH_LOWVECTORS is defined, then the vectors located at the * beginning of the .text region must appear at address at the address diff --git a/configs/sabre-6quad/README.txt b/configs/sabre-6quad/README.txt index 3a7988d029..13584158a5 100644 --- a/configs/sabre-6quad/README.txt +++ b/configs/sabre-6quad/README.txt @@ -104,13 +104,13 @@ Status 2016-11-26: With regard to SMP, the major issue is cache coherency. I added some special build logic to move spinlock data into the separate, non- cached section. That gives an improvement in performance but there are - still hangs. These, I have determined are to other kinds of cache + still hangs. These, I have determined, are to other kinds of cache coherency problems. Semaphores, message queues, etc. basically all - shared data must be made coherent. I am not sure how to do that. See - the SMP section below for more information. + shared data must be made coherent. I also added some SCU controls that should enable cache consistency for SMP - CPUs, but I don't think I have that working right yet. + CPUs, but I don't think I have that working right yet. See the SMP section + below for more information. Platform Features ================= @@ -511,22 +511,13 @@ Open Issues: This will cause the interrupt handlers on other CPUs to spin until leave_critical_section() is called. More verification is needed. -2. Cache Concurency. Cache coherency in SMP configurations is managed by the the - CPU. I don't think I have the set up correctly yet. +2. Cache Concurency. Cache coherency in SMP configurations is managed by the + MPCore snoop control unit (SCU). But I don't think I have the set up + correctly yet. Currently cache inconsistencies appear to be the root cause of all current SMP issues. - 2016-11-26: With regard to SMP, the major issue is cache coherency. I added - some special build logic to move spinlock data into the separate, non- - cached section. That gives an improvement in performance but there are - still hangs. These, I have determined are to other kinds of cache - coherency problems. Semaphores, message queues, etc. basically all - shared data must be made coherent. - - I also added some SCU controls that should enable cache consistency for SMP - CPUs, but I don't think I have that working right yet. - Configurations ============== diff --git a/configs/sabre-6quad/src/imx_boardinit.c b/configs/sabre-6quad/src/imx_boardinit.c index f67592caf8..80dbc589a1 100644 --- a/configs/sabre-6quad/src/imx_boardinit.c +++ b/configs/sabre-6quad/src/imx_boardinit.c @@ -62,14 +62,40 @@ * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: imx_memory_initialize + * + * Description: + * All i.MX6 architectures must provide the following entry point. This + * entry point is called early in the initialization before memory has + * been configured. This board-specific function is responsible for + * configuring any on-board memories. + * + * Logic in imx_memory_initialize must be careful to avoid using any + * global variables because those will be uninitialized at the time this + * function is called. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imx_memory_initialize(void) +{ + /* SDRAM was initialized by a bootloader in the supported configurations. */ +} + /**************************************************************************** * Name: imx_board_initialize * * Description: * All i.MX6 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. + * entry point is called in the initialization phase -- after + * imx_memory_initialize and after all memory has been configured and + * mapped but before any devices have been initialized. * * Input Parameters: * None -- GitLab From b5bfe8af171b795f6e9cd91f89ba68293e12a398 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Sun, 27 Nov 2016 11:19:46 -0600 Subject: [PATCH 530/734] The Smoothie project needs to compile C++ inside config/boardname/src/ to use with High Priority Interruption, then I modified the board configs Makefile to support it, see attached patch. It works fine for the first time compilation, but if we execute: $ touch config/boardname/src/Pin.cxx And execute "make" it will not detect that Pin.cxx was modified. I think there is some other place I should modify, but I didn't find it. --- configs/Board.mk | 13 ++++++++++--- configs/Makefile | 16 +++++++++++++--- 2 files changed, 23 insertions(+), 6 deletions(-) diff --git a/configs/Board.mk b/configs/Board.mk index 11f0ed4dc2..680b37ebcb 100644 --- a/configs/Board.mk +++ b/configs/Board.mk @@ -43,6 +43,7 @@ else AOBJS = $(ASRCS:$(ASMEXT)=$(OBJEXT)) endif COBJS = $(CSRCS:.c=$(OBJEXT)) +CXXOBJS = $(CXXSRCS:.cxx=$(OBJEXT)) SRCS = $(ASRCS) $(CSRCS) OBJS = $(AOBJS) $(COBJS) @@ -108,17 +109,23 @@ $(AOBJS): %$(OBJEXT): %$(ASMEXT) $(COBJS) $(LINKOBJS): %$(OBJEXT): %.c $(call COMPILE, $<, $@) -libboard$(LIBEXT): $(OBJS) +$(CXXOBJS) $(LINKOBJS): %$(OBJEXT): %.cxx + $(call COMPILEXX, $<, $@) + +libboard$(LIBEXT): $(OBJS) $(CXXOBJS) $(Q) $(AR) $@ # Create an empty archive ifneq ($(OBJS),) - $(call ARCHIVE, $@, $(OBJS)) + $(call ARCHIVE, $@, $(OBJS) $(CXXOBJS)) endif -.depend: Makefile $(SRCS) +.depend: Makefile $(SRCS) $(CXXSRCS) ifneq ($(ZDSVERSION),) $(Q) $(MKDEP) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep else $(Q) $(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep +endif +ifneq ($(CXXSRCS),) + $(Q) $(MKDEP) "$(CXX)" -- $(CXXFLAGS) -- $(CXXSRCS) >>Make.dep endif $(Q) touch $@ diff --git a/configs/Makefile b/configs/Makefile index 68a5fad87f..f430e137e8 100644 --- a/configs/Makefile +++ b/configs/Makefile @@ -66,6 +66,7 @@ BOARD_INSTALLED = $(if $(wildcard $(BOARD_DIR)$(DELIM)Makefile),y,) CONFIG_ASRCS = CONFIG_CSRCS = +CONFIG_CXXSRCS = # boardctl support @@ -79,6 +80,9 @@ AOBJS = $(ASRCS:.S=$(OBJEXT)) CSRCS = $(CONFIG_CSRCS) COBJS = $(CSRCS:.c=$(OBJEXT)) +CXXSRCS = $(CONFIG_CXXSRCS) +CXXOBJS = $(CXXSRCS:.cxx=$(OBJEXT)) + SRCS = $(ASRCS) $(CSRCS) OBJS = $(AOBJS) $(COBJS) @@ -93,12 +97,18 @@ $(AOBJS): %$(OBJEXT): %.S $(COBJS): %$(OBJEXT): %.c $(call COMPILE, $<, $@) -$(BIN): $(OBJS) - $(call ARCHIVE, $@, $(OBJS)) +$(CXXOBJS): %$(OBJEXT): %.cxx + $(call COMPILEXX, $<, $@) + +$(BIN): $(OBJS) $(CXXOBJS) + $(call ARCHIVE, $@, $(OBJS) $(CXXOBJS)) -.depend: Makefile $(SRCS) +.depend: Makefile $(SRCS) $(CXXSRCS) ifneq ($(SRCS),) $(Q) $(MKDEP) --dep-path . "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep +endif +ifneq ($(CXXSRCS),) + $(Q) $(MKDEP) --dep-path . "$(CXX)" -- $(CXXFLAGS) -- $(CXXSRCS) >>Make.dep endif $(Q) touch $@ -- GitLab From 21e42d18c1fdfa7f856d7e93e689d0b67d800325 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 27 Nov 2016 11:28:24 -0600 Subject: [PATCH 531/734] ARMv7-A/i.MX6 SMP: Move SMP coherernt cache setup to earlier in initialization of CPUn, n>0 --- arch/arm/src/armv7-a/arm_cpustart.c | 5 ----- arch/arm/src/imx6/imx_cpuboot.c | 5 +++++ 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_cpustart.c b/arch/arm/src/armv7-a/arm_cpustart.c index 38928e7aec..c3eab68d4a 100644 --- a/arch/arm/src/armv7-a/arm_cpustart.c +++ b/arch/arm/src/armv7-a/arm_cpustart.c @@ -47,7 +47,6 @@ #include "up_internal.h" #include "cp15_cacheops.h" #include "gic.h" -#include "scu.h" #include "sched/sched.h" #ifdef CONFIG_SMP @@ -110,10 +109,6 @@ int arm_start_handler(int irq, FAR void *context) sinfo("CPU%d Started\n", cpu); - /* Enable SMP cache coherency for the CPU */ - - arm_enable_smp(cpu); - /* Reset scheduler parameters */ tcb = this_task(); diff --git a/arch/arm/src/imx6/imx_cpuboot.c b/arch/arm/src/imx6/imx_cpuboot.c index 4b288b17d1..818b327a4b 100644 --- a/arch/arm/src/imx6/imx_cpuboot.c +++ b/arch/arm/src/imx6/imx_cpuboot.c @@ -51,6 +51,7 @@ #include "chip/imx_src.h" #include "sctlr.h" #include "smp.h" +#include "scu.h" #include "fpu.h" #include "gic.h" @@ -259,6 +260,10 @@ void imx_cpu_enable(void) void arm_cpu_boot(int cpu) { + /* Enable SMP cache coherency for the CPU */ + + arm_enable_smp(cpu); + #ifdef CONFIG_ARCH_FPU /* Initialize the FPU */ -- GitLab From cbf98ae0a0d67dfbedf9410c99764dbbf206e9cb Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 27 Nov 2016 13:18:34 -0600 Subject: [PATCH 532/734] ARMv7 GIC: SGIs are non-maskable but go through the same path as other, maskable interrupts. Added logic to serialize SGI processing when necessary. --- arch/arm/src/armv7-a/arm_doirq.c | 162 +++++++++++++++++++++++++++++-- arch/arm/src/armv7-a/arm_gicv2.c | 2 +- arch/arm/src/imx6/imx_irq.c | 2 +- 3 files changed, 154 insertions(+), 12 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_doirq.c b/arch/arm/src/armv7-a/arm_doirq.c index b3d98151c0..fa3e104582 100644 --- a/arch/arm/src/armv7-a/arm_doirq.c +++ b/arch/arm/src/armv7-a/arm_doirq.c @@ -40,10 +40,10 @@ #include #include -#include -#include #include +#include +#include #include #include @@ -51,21 +51,40 @@ #include "up_internal.h" #include "group/group.h" +#include "gic.h" /**************************************************************************** - * Public Functions + * Private Data ****************************************************************************/ -uint32_t *arm_doirq(int irq, uint32_t *regs) -{ - board_autoled_on(LED_INIRQ); -#ifdef CONFIG_SUPPRESS_INTERRUPTS - PANIC(); +/* A bit set of pending, non-maskable SGI interrupts, on bit set for each + * supported CPU. + */ + +#ifdef CONFIG_ARMV7A_HAVE_GICv2 +#ifdef CONFIG_SMP +static uint16_t g_sgi_pending[CONFIG_SMP_NCPUS]; #else - /* Nested interrupts are not supported */ +static uint16_t g_sgi_pending[1]; +#endif +#endif - DEBUGASSERT(CURRENT_REGS == NULL); +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _arm_doirq + * + * Description: + * Receives the one decoded interrupt and dispatches control to the + * attached interrupt handler. + * + ****************************************************************************/ +#ifndef CONFIG_SUPPRESS_INTERRUPTS +static inline uint32_t *_arm_doirq(int irq, uint32_t *regs) +{ /* Current regs non-zero indicates that we are processing an interrupt; * CURRENT_REGS is also used to manage interrupt level context switches. */ @@ -110,8 +129,131 @@ uint32_t *arm_doirq(int irq, uint32_t *regs) regs = (uint32_t *)CURRENT_REGS; CURRENT_REGS = NULL; + + return regs; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_doirq + * + * Description: + * Receives the decoded GIC interrupt information and dispatches control + * to the attached interrupt handler. There are two versions: + * + * 1) For the simple case where all interrupts are maskable. In that + * simple case, arm_doirq() is simply a wrapper for the inlined + * _arm_do_irq() that does the real work. + * + * 2) With the GICv2, there are 16 non-maskable software generated + * interrupts (SGIs) that also come through arm_doirq(). In that case, + * we must avoid nesting interrupt handling and serial the processing. + * + ****************************************************************************/ + +#ifndef CONFIG_ARMV7A_HAVE_GICv2 +uint32_t *arm_doirq(int irq, uint32_t *regs) +{ + board_autoled_on(LED_INIRQ); +#ifdef CONFIG_SUPPRESS_INTERRUPTS + PANIC(); +#else + /* Nested interrupts are not supported */ + + DEBUGASSERT(CURRENT_REGS == NULL); + + /* Dispatch the interrupt to its attached handler */ + + regs = _arm_doirq(irq, regs); +#endif + + board_autoled_off(LED_INIRQ); + return regs; +} +#endif + +#ifdef CONFIG_ARMV7A_HAVE_GICv2 +uint32_t *arm_doirq(int irq, uint32_t *regs) +{ +#ifndef CONFIG_SUPPRESS_INTERRUPTS + uint32_t bit; + int cpu; + int i; +#endif + + board_autoled_on(LED_INIRQ); +#ifdef CONFIG_SUPPRESS_INTERRUPTS + PANIC(); + +#else + /* Get the CPU processing the interrupt */ + +#ifdef CONFIG_SMP + cpu = up_cpu_index(); +#else + cpu = 0; +#endif + + /* Non-zero CURRENT_REGS indicates that we are already processing an + * interrupt. This could be a normal event for the case of the GICv2; + * Software generated interrupts are non-maskable. + * + * REVISIT: There is no support for nested SGIs! That will cause an + * assertion below. There is also no protection for concurrent access + * to g_sgi_pending for that case. + */ + + if (CURRENT_REGS != NULL) + { + int ndx = irq - GIC_IRQ_SGI0; + bit = (1 << (ndx)); + + /* Only an SGI should cause this event. We also cannot support + * multiple pending SGI interrupts. + */ + + ASSERT((unsigned int)irq <= GIC_IRQ_SGI15 && + (g_sgi_pending[cpu] & bit) == 0); + + /* Mare the SGI as pending and return immediately */ + + sinfo("SGI%d pending\n", ndx); + g_sgi_pending[cpu] |= bit; + return regs; + } + + /* Dispatch the interrupt to its attached handler */ + + regs = _arm_doirq(irq, regs); + + /* Then loop dispatching any pending SGI interrupts that occcurred during + * processing of the interrupts. + */ + + for (i = 0; i < 16 && g_sgi_pending[cpu] != 0; i++) + { + /* Check if this SGI is pending */ + + bit = (1 << i); + if ((g_sgi_pending[cpu] & bit) != 0) + { + /* Clear the pending bit */ + + g_sgi_pending[cpu] &= ~bit; + + /* And dispatch the SGI */ + + sinfo("Dispatching pending SGI%d\n", i + GIC_IRQ_SGI0); + regs = _arm_doirq(i + GIC_IRQ_SGI0, regs); + } + } #endif board_autoled_off(LED_INIRQ); return regs; } +#endif diff --git a/arch/arm/src/armv7-a/arm_gicv2.c b/arch/arm/src/armv7-a/arm_gicv2.c index e99eb540fd..52ca465974 100644 --- a/arch/arm/src/armv7-a/arm_gicv2.c +++ b/arch/arm/src/armv7-a/arm_gicv2.c @@ -122,7 +122,7 @@ void arm_gic0_initialize(void) } #ifdef CONFIG_SMP - /* Attach SGI interrupt handlers */ + /* Attach SGI interrupt handlers. This attaches the handler for all CPUs. */ DEBUGVERIFY(irq_attach(GIC_IRQ_SGI1, arm_start_handler)); DEBUGVERIFY(irq_attach(GIC_IRQ_SGI2, arm_pause_handler)); diff --git a/arch/arm/src/imx6/imx_irq.c b/arch/arm/src/imx6/imx_irq.c index e00a8e9527..b15a9a4e6d 100644 --- a/arch/arm/src/imx6/imx_irq.c +++ b/arch/arm/src/imx6/imx_irq.c @@ -134,11 +134,11 @@ void up_irqinitialize(void) CURRENT_REGS = NULL; #ifndef CONFIG_SUPPRESS_INTERRUPTS +#ifdef CONFIG_IMX6_PIO_IRQ /* Initialize logic to support a second level of interrupt decoding for * PIO pins. */ -#ifdef CONFIG_IMX6_PIO_IRQ imx_gpioirq_initialize(); #endif -- GitLab From d65be718c2d365f2d8cb54af666d6fa7965e43fb Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 27 Nov 2016 17:14:57 -0600 Subject: [PATCH 533/734] sched_note: Extend OS instrumentation to include some SMP events. --- arch/arm/src/armv7-a/arm_cpupause.c | 25 ++++++++++ arch/arm/src/armv7-a/arm_cpustart.c | 3 +- arch/xtensa/src/common/xtensa_cpupause.c | 25 ++++++++++ drivers/syslog/Kconfig | 2 +- include/nuttx/sched_note.h | 59 ++++++++++++++++++++++++ sched/Kconfig | 8 ++++ sched/sched/sched_cpupause.c | 1 + sched/sched/sched_note.c | 56 ++++++++++++++++++++++ 8 files changed, 176 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_cpupause.c b/arch/arm/src/armv7-a/arm_cpupause.c index 8b8df44a73..c0751f8ee4 100644 --- a/arch/arm/src/armv7-a/arm_cpupause.c +++ b/arch/arm/src/armv7-a/arm_cpupause.c @@ -44,6 +44,7 @@ #include #include #include +#include #include "up_internal.h" #include "gic.h" @@ -131,6 +132,12 @@ int up_cpu_paused(int cpu) sched_suspend_scheduler(tcb); +#ifdef CONFIG_SCHED_INSTRUMENTATION + /* Notify that we are paused */ + + sched_note_cpu_paused(tcb); +#endif + /* Save the current context at CURRENT_REGS into the TCB at the head * of the assigned task list for this CPU. */ @@ -148,6 +155,12 @@ int up_cpu_paused(int cpu) tcb = this_task(); +#ifdef CONFIG_SCHED_INSTRUMENTATION + /* Notify that we have resumed */ + + sched_note_cpu_resumed(tcb); +#endif + /* Reset scheduler parameters */ sched_resume_scheduler(tcb); @@ -224,6 +237,12 @@ int up_cpu_pause(int cpu) { int ret; +#ifdef CONFIG_SCHED_INSTRUMENTATION + /* Notify of the pause event */ + + sched_note_cpu_pause(this_task(), cpu); +#endif + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu()); /* Take the both spinlocks. The g_cpu_wait spinlock will prevent the SGI2 @@ -287,6 +306,12 @@ int up_cpu_pause(int cpu) int up_cpu_resume(int cpu) { +#ifdef CONFIG_SCHED_INSTRUMENTATION + /* Notify of the resume event */ + + sched_note_cpu_resume(this_task(), cpu); +#endif + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu()); /* Release the spinlock. Releasing the spinlock will cause the SGI2 diff --git a/arch/arm/src/armv7-a/arm_cpustart.c b/arch/arm/src/armv7-a/arm_cpustart.c index c3eab68d4a..012d2e438e 100644 --- a/arch/arm/src/armv7-a/arm_cpustart.c +++ b/arch/arm/src/armv7-a/arm_cpustart.c @@ -105,9 +105,8 @@ static inline void arm_registerdump(FAR struct tcb_s *tcb) int arm_start_handler(int irq, FAR void *context) { FAR struct tcb_s *tcb; - int cpu = up_cpu_index(); - sinfo("CPU%d Started\n", cpu); + sinfo("CPU%d Started\n", this_cpu()); /* Reset scheduler parameters */ diff --git a/arch/xtensa/src/common/xtensa_cpupause.c b/arch/xtensa/src/common/xtensa_cpupause.c index e310ad44da..8d1fcd0371 100644 --- a/arch/xtensa/src/common/xtensa_cpupause.c +++ b/arch/xtensa/src/common/xtensa_cpupause.c @@ -44,6 +44,7 @@ #include #include #include +#include #include "xtensa.h" #include "sched/sched.h" @@ -117,6 +118,12 @@ int up_cpu_paused(int cpu) sched_suspend_scheduler(otcb); +#ifdef CONFIG_SCHED_INSTRUMENTATION + /* Notify that we are paused */ + + sched_note_cpu_paused(otcb); +#endif + /* Copy the CURRENT_REGS into the OLD TCB (otcb). The co-processor state * will be saved as part of the return from xtensa_irq_dispatch(). */ @@ -134,6 +141,12 @@ int up_cpu_paused(int cpu) ntcb = this_task(); +#ifdef CONFIG_SCHED_INSTRUMENTATION + /* Notify that we have resumed */ + + sched_note_cpu_resumed(ntcb); +#endif + /* Reset scheduler parameters */ sched_resume_scheduler(ntcb); @@ -203,6 +216,12 @@ int up_cpu_pause(int cpu) { int ret; +#ifdef CONFIG_SCHED_INSTRUMENTATION + /* Notify of the pause event */ + + sched_note_cpu_pause(this_task(), cpu); +#endif + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu()); /* Take the both spinlocks. The g_cpu_wait spinlock will prevent the SGI2 @@ -266,6 +285,12 @@ int up_cpu_pause(int cpu) int up_cpu_resume(int cpu) { +#ifdef CONFIG_SCHED_INSTRUMENTATION + /* Notify of the resume event */ + + sched_note_cpu_resume(this_task(), cpu); +#endif + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu()); /* Release the spinlock. Releasing the spinlock will cause the SGI2 diff --git a/drivers/syslog/Kconfig b/drivers/syslog/Kconfig index 3ac22d8b68..dd64edb1e8 100644 --- a/drivers/syslog/Kconfig +++ b/drivers/syslog/Kconfig @@ -73,7 +73,7 @@ config DRIVER_NOTE depends on SCHED_INSTRUMENTATION_BUFFER ---help--- Enable building a serial driver that can be used by an application - to read data from the in-memory, scheduler instrumentatin "note" + to read data from the in-memory, scheduler instrumentation "note" buffer. config SYSLOG_INTBUFFER diff --git a/include/nuttx/sched_note.h b/include/nuttx/sched_note.h index c21f040066..86afa0ea2c 100644 --- a/include/nuttx/sched_note.h +++ b/include/nuttx/sched_note.h @@ -64,6 +64,13 @@ enum note_type_e NOTE_STOP, NOTE_SUSPEND, NOTE_RESUME +#ifdef CONFIG_SMP + , + NOTE_CPU_PAUSE, + NOTE_CPU_PAUSED, + NOTE_CPU_RESUME, + NOTE_CPU_RESUMED +#endif #ifdef CONFIG_SCHED_INSTRUMENTATION_PREEMPTION , NOTE_PREEMPT_LOCK, @@ -122,6 +129,38 @@ struct note_resume_s struct note_common_s nre_cmn; /* Common note parameters */ }; +#ifdef CONFIG_SMP +/* This is the specific form of the NOTE_CPU_PAUSE note */ + +struct note_cpu_pause_s +{ + struct note_common_s ncp_cmn; /* Common note parameters */ + uint8_t ncp_target; /* CPU being paused */ +}; + +/* This is the specific form of the NOTE_CPU_PAUSED note */ + +struct note_cpu_paused_s +{ + struct note_common_s ncp_cmn; /* Common note parameters */ +}; + +/* This is the specific form of the NOTE_CPU_RESUME note */ + +struct note_cpu_resume_s +{ + struct note_common_s ncr_cmn; /* Common note parameters */ + uint8_t ncr_target; /* CPU being resumed */ +}; + +/* This is the specific form of the NOTE_CPU_RESUMED note */ + +struct note_cpu_resumed_s +{ + struct note_common_s ncr_cmn; /* Common note parameters */ +}; +#endif + #ifdef CONFIG_SCHED_INSTRUMENTATION_PREEMPTION /* This is the specific form of the NOTE_PREEMPT_LOCK/UNLOCK note */ @@ -174,12 +213,28 @@ void sched_note_stop(FAR struct tcb_s *tcb); void sched_note_suspend(FAR struct tcb_s *tcb); void sched_note_resume(FAR struct tcb_s *tcb); +#ifdef CONFIG_SMP +void sched_note_cpu_pause(FAR struct tcb_s *tcb, int cpu); +void sched_note_cpu_paused(FAR struct tcb_s *tcb); +void sched_note_cpu_resume(FAR struct tcb_s *tcb, int cpu); +void sched_note_cpu_resumed(FAR struct tcb_s *tcb); +#else +# define sched_note_cpu_pause(t,c) +# define sched_note_cpu_paused(t) +# define sched_note_cpu_resume(t,c) +# define sched_note_cpu_resumed(t) +#endif + #ifdef CONFIG_SCHED_INSTRUMENTATION_PREEMPTION void sched_note_premption(FAR struct tcb_s *tcb, bool locked); +#else +# define sched_note_premption(t,l) #endif #ifdef CONFIG_SCHED_INSTRUMENTATION_CSECTION void sched_note_csection(FAR struct tcb_s *tcb, bool enter); +#else +# define sched_note_csection(t,e) #endif /**************************************************************************** @@ -250,6 +305,10 @@ int note_register(void); # define sched_note_stop(t) # define sched_note_suspend(t) # define sched_note_resume(t) +# define sched_note_cpu_pause(t,c) +# define sched_note_cpu_paused(t) +# define sched_note_cpu_resume(t,c) +# define sched_note_cpu_resumed(t) # define sched_note_premption(t,l) # define sched_note_csection(t,e) diff --git a/sched/Kconfig b/sched/Kconfig index 60156e0368..9065261acb 100644 --- a/sched/Kconfig +++ b/sched/Kconfig @@ -661,6 +661,14 @@ config SCHED_INSTRUMENTATION void sched_note_suspend(FAR struct tcb_s *tcb); void sched_note_resume(FAR struct tcb_s *tcb); + If CONFIG_SMP is enabled, then these additional interfaces are + expected: + + void sched_note_cpu_pause(FAR struct tcb_s *tcb, int cpu); + void sched_note_cpu_paused(FAR struct tcb_s *tcb); + void sched_note_cpu_resume(FAR struct tcb_s *tcb, int cpu); + void sched_note_cpu_resumed(FAR struct tcb_s *tcb); + NOTE: These are internal OS interfaces and are called at at very critical locations in the OS. There is very little that can be done in these interfaces. For example, normal devices may not be diff --git a/sched/sched/sched_cpupause.c b/sched/sched/sched_cpupause.c index 513e8deb48..d2b14d187d 100644 --- a/sched/sched/sched_cpupause.c +++ b/sched/sched/sched_cpupause.c @@ -44,6 +44,7 @@ #include #include +#include #include "sched/sched.h" diff --git a/sched/sched/sched_note.c b/sched/sched/sched_note.c index 4dc1bd262e..6594efaf22 100644 --- a/sched/sched/sched_note.c +++ b/sched/sched/sched_note.c @@ -369,6 +369,62 @@ void sched_note_resume(FAR struct tcb_s *tcb) note_add((FAR const uint8_t *)¬e, sizeof(struct note_resume_s)); } +#ifdef CONFIG_SMP +void sched_note_cpu_pause(FAR struct tcb_s *tcb, int cpu) +{ + struct note_cpu_pause_s note; + + /* Format the note */ + + note_common(tcb, ¬e.ncp_cmn, sizeof(struct note_cpu_pause_s), NOTE_CPU_PAUSE); + note.ncp_target = (uint8_t)cpu; + + /* Add the note to circular buffer */ + + note_add((FAR const uint8_t *)¬e, sizeof(struct note_cpu_pause_s)); +} + +void sched_note_cpu_paused(FAR struct tcb_s *tcb) +{ + struct note_cpu_paused_s note; + + /* Format the note */ + + note_common(tcb, ¬e.ncp_cmn, sizeof(struct note_cpu_paused_s), NOTE_CPU_PAUSED); + + /* Add the note to circular buffer */ + + note_add((FAR const uint8_t *)¬e, sizeof(struct note_cpu_paused_s)); +} + +void sched_note_cpu_resume(FAR struct tcb_s *tcb, int cpu) +{ + struct note_cpu_resume_s note; + + /* Format the note */ + + note_common(tcb, ¬e.ncr_cmn, sizeof(struct note_cpu_resume_s), NOTE_CPU_RESUME); + note.ncr_target = (uint8_t)cpu; + + /* Add the note to circular buffer */ + + note_add((FAR const uint8_t *)¬e, sizeof(struct note_cpu_resume_s)); +} + +void sched_note_cpu_resumed(FAR struct tcb_s *tcb) +{ + struct note_cpu_resumed_s note; + + /* Format the note */ + + note_common(tcb, ¬e.ncr_cmn, sizeof(struct note_cpu_resumed_s), NOTE_CPU_RESUMED); + + /* Add the note to circular buffer */ + + note_add((FAR const uint8_t *)¬e, sizeof(struct note_cpu_resumed_s)); +} +#endif + #ifdef CONFIG_SCHED_INSTRUMENTATION_PREEMPTION void sched_note_premption(FAR struct tcb_s *tcb, bool locked) { -- GitLab From 00215fbc987d9a86d5095d24a33c749671a803ad Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 28 Nov 2016 10:33:46 -0600 Subject: [PATCH 534/734] sched_note: Add spinlock instrumentation; In SMP configurations, select to log only notes from certain CPUs --- include/nuttx/sched_note.h | 50 ++++++++++++++++++++++ include/nuttx/spinlock.h | 4 ++ sched/Kconfig | 35 ++++++++++++++- sched/irq/irq_csection.c | 20 +++++++++ sched/sched/sched_note.c | 74 +++++++++++++++++++++++++++++++- sched/semaphore/spinlock.c | 87 ++++++++++++++++++++++++++++++++++++++ 6 files changed, 267 insertions(+), 3 deletions(-) diff --git a/include/nuttx/sched_note.h b/include/nuttx/sched_note.h index 86afa0ea2c..0b19bd2a06 100644 --- a/include/nuttx/sched_note.h +++ b/include/nuttx/sched_note.h @@ -50,6 +50,22 @@ #ifdef CONFIG_SCHED_INSTRUMENTATION +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Provide defaults for some configuration settings (could be undefined with + * old configuration files) + */ + +#ifdef CONFIG_SCHED_INSTRUMENTATION_CPUSET +# define CONFIG_SCHED_INSTRUMENTATION_CPUSET 0xffff +#endif + +#ifdef CONFIG_SCHED_NOTE_BUFSIZE +# define CONFIG_SCHED_NOTE_BUFSIZE 2048 +#endif + /**************************************************************************** * Public Types ****************************************************************************/ @@ -81,6 +97,13 @@ enum note_type_e NOTE_CSECTION_ENTER, NOTE_CSECTION_LEAVE #endif +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS + , + NOTE_SPINLOCK_LOCK, + NOTE_SPINLOCK_LOCKED, + NOTE_SPINLOCK_UNLOCK, + NOTE_SPINLOCK_ABORT +#endif }; /* This structure provides the common header of each note */ @@ -182,6 +205,17 @@ struct note_csection_s #endif }; #endif /* CONFIG_SCHED_INSTRUMENTATION_CSECTION */ + +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS +/* This is the specific form of the NOTE_SPINLOCK_LOCK/LOCKED/UNLOCK/ABORT note */ + +struct note_spinlock_s +{ + struct note_common_s nsp_cmn; /* Common note parameters */ + FAR void *nsp_spinlock; /* Address of spinlock */ + uint8_t nsp_value; /* Value of spinlock */ +}; +#endif /* CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS */ #endif /* CONFIG_SCHED_INSTRUMENTATION_BUFFER */ /**************************************************************************** @@ -237,6 +271,18 @@ void sched_note_csection(FAR struct tcb_s *tcb, bool enter); # define sched_note_csection(t,e) #endif +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS +void sched_note_spinlock(FAR struct tcb_s *tcb, FAR volatile void *spinlock); +void sched_note_spinlocked(FAR struct tcb_s *tcb, FAR volatile void *spinlock); +void sched_note_spinunlock(FAR struct tcb_s *tcb, FAR volatile void *spinlock); +void sched_note_spinabort(FAR struct tcb_s *tcb, FAR volatile void *spinlock); +#else +# define sched_note_spinlock(t,s) +# define sched_note_spinlocked(t,s) +# define sched_note_spinunlock(t,s) +# define sched_note_spinabort(t,s) +#endif + /**************************************************************************** * Name: sched_note_get * @@ -311,6 +357,10 @@ int note_register(void); # define sched_note_cpu_resumed(t) # define sched_note_premption(t,l) # define sched_note_csection(t,e) +# define sched_note_spinlock(t,s) +# define sched_note_spinlocked(t,s) +# define sched_note_spinunlock(t,s) +# define sched_note_spinabort(t,s) #endif /* CONFIG_SCHED_INSTRUMENTATION */ #endif /* __INCLUDE_NUTTX_SCHED_NOTE_H */ diff --git a/include/nuttx/spinlock.h b/include/nuttx/spinlock.h index afcc4a1853..44b907bc61 100644 --- a/include/nuttx/spinlock.h +++ b/include/nuttx/spinlock.h @@ -80,6 +80,10 @@ # define SP_DSB() #endif +#if defined(CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS) && !defined(__SP_UNLOCK_FUNCTION) +# define __SP_UNLOCK_FUNCTION 1 +#endif + /* If the target CPU supports a data cache then it may be necessary to * manage spinlocks in a special way, perhaps linking them all into a * special non-cacheable memory region. diff --git a/sched/Kconfig b/sched/Kconfig index 9065261acb..b71e9874fe 100644 --- a/sched/Kconfig +++ b/sched/Kconfig @@ -678,6 +678,13 @@ config SCHED_INSTRUMENTATION if SCHED_INSTRUMENTATION +config SCHED_INSTRUMENTATION_CPUSET + hex "CPU bit set" + default 0xffff + depends on SMP + ---help--- + Monitor only CPUs in the bitset. Bit 0=CPU0, Bit1=CPU1, etc. + config SCHED_INSTRUMENTATION_PREEMPTION bool "Preemption monitor hooks" default n @@ -687,10 +694,15 @@ config SCHED_INSTRUMENTATION_PREEMPTION void sched_note_premption(FAR struct tcb_s *tcb, bool state); +config SCHED_INSTRUMENTATION_FAUXPAS + bool + default y if !EXPERIMENTAL && SCHED_INSTRUMENTATION_BUFFER + default n if EXPERIMENTAL || !SCHED_INSTRUMENTATION_BUFFER + config SCHED_INSTRUMENTATION_CSECTION bool "Critical section monitor hooks" default n - depends on EXPERIMENTAL || !SCHED_INSTRUMENTATION_BUFFER + depends on !SCHED_INSTRUMENTATION_FAUXPAS ---help--- Enables additional hooks for entry and exit from critical sections. Interrupts are disabled while within a critical section. Board- @@ -706,6 +718,27 @@ config SCHED_INSTRUMENTATION_CSECTION added from the note buffer in order to remove one entry. Not very useful in its current state! +config SCHED_INSTRUMENTATION_SPINLOCK + bool "Spinlock monitor hooks" + default n + depends on SPINLOCK && (!SMP || !SCHED_INSTRUMENTATION_FAUXPAS) + ---help--- + Enables additional hooks for spinlock state. Board-specific logic + must provide this additional logic. + + void sched_note_spinlock(FAR struct tcb_s *tcb, bool state); + void sched_note_spinlocked(FAR struct tcb_s *tcb, bool state); + void sched_note_spinunlock(FAR struct tcb_s *tcb, bool state); + void sched_note_spinabort(FAR struct tcb_s *tcb, bool state); + + NOTE: This option is marked EXPERIMENTAL because there is a logical + error in the design when this feature is used with + CONFIG_SCHED_INSTRUMENTATION_BUFFER. That error is that + sched_note_get() calls enter_ and leave_critical_section which use + spinlocks in SMP mode. That means that each call to sched_note_get() + causes several additional entries to be added from the note buffer in + order to remove one entry. Not very useful in its current state! + config SCHED_INSTRUMENTATION_BUFFER bool "Buffer instrumentation data in memory" default n diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 20660dd728..4f2178ab5f 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -128,6 +128,14 @@ static uint8_t g_cpu_nestcount[CONFIG_SMP_NCPUS]; #ifdef CONFIG_SMP static inline bool irq_waitlock(int cpu) { +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS + FAR struct tcb_s *tcb = this_task(); + + /* Notify that we are waiting for a spinlock */ + + sched_note_spinlock(tcb, &g_cpu_irqlock); +#endif + /* Duplicate the spin_lock() logic from spinlock.c, but adding the check * for the deadlock condition. */ @@ -142,6 +150,12 @@ static inline bool irq_waitlock(int cpu) * Abort the wait and return false. */ +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS + /* Notify that we are waiting for a spinlock */ + + sched_note_spinabort(tcb, &g_cpu_irqlock); +#endif + return false; } @@ -150,6 +164,12 @@ static inline bool irq_waitlock(int cpu) /* We have g_cpu_irqlock! */ +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS + /* Notify that we have the spinlock */ + + sched_note_spinlocked(tcb, &g_cpu_irqlock); +#endif + SP_DMB(); return true; } diff --git a/sched/sched/sched_note.c b/sched/sched/sched_note.c index 6594efaf22..2ad620f416 100644 --- a/sched/sched/sched_note.c +++ b/sched/sched/sched_note.c @@ -46,8 +46,11 @@ #include #include +#include #include +#include "sched/sched.h" + #ifdef CONFIG_SCHED_INSTRUMENTATION_BUFFER /**************************************************************************** @@ -122,8 +125,10 @@ static inline unsigned int note_next(unsigned int ndx, unsigned int offset) * Fill in some of the common fields in the note structure. * * Input Parameters: - * tcb - The TCB containing the information - * note - The common note structure to use + * tcb - The TCB containing the information + * note - The common note structure to use + * length - The total lengthof the note structure + * type - The type of the note * * Returned Value: * None @@ -154,6 +159,39 @@ static void note_common(FAR struct tcb_s *tcb, FAR struct note_common_s *note, note->nc_systime[3] = (uint8_t)((systime >> 24) & 0xff); } +/**************************************************************************** + * Name: note_spincommon + * + * Description: + * Common logic for NOTE_SPINLOCK, NOTE_SPINLOCKED, and NOTE_SPINUNLOCK + * + * Input Parameters: + * tcb - The TCB containing the information + * note - The common note structure to use + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS +void note_spincommon(FAR struct tcb_s *tcb, FAR volatile spinlock_t *spinlock, + int type) +{ + struct note_spinlock_s note; + + /* Format the note */ + + note_common(tcb, ¬e.nsp_cmn, sizeof(struct note_spinlock_s), type); + note.nsp_spinlock = (FAR void *)spinlock; + note.nsp_value = (uint8_t)*spinlock; + + /* Add the note to circular buffer */ + + note_add((FAR const uint8_t *)¬e, sizeof(struct note_spinlock_s)); +} +#endif + /**************************************************************************** * Name: note_length * @@ -244,6 +282,17 @@ static void note_add(FAR const uint8_t *note, uint8_t notelen) unsigned int head; unsigned int next; +#ifdef CONFIG_SMP + /* Ignore notes that are not in the set of monitored CPUs */ + + if ((CONFIG_SCHED_INSTRUMENTATION_CPUSET & (1 << this_cpu())) == 0) + { + /* Not in the set of monitored CPUs. Do not log the note. */ + + return; + } +#endif + /* Get the index to the head of the circular buffer */ DEBUGASSERT(note != NULL && notelen < CONFIG_SCHED_NOTE_BUFSIZE); @@ -463,6 +512,27 @@ void sched_note_csection(FAR struct tcb_s *tcb, bool enter) } #endif +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS +void sched_note_spinlock(FAR struct tcb_s *tcb, FAR volatile void *spinlock) +{ + note_spincommon(tcb, spinlock, NOTE_SPINLOCK_LOCK) +} + +void sched_note_spinlocked(FAR struct tcb_s *tcb, FAR volatile void *spinlock); +{ + note_spincommon(tcb, spinlock, NOTE_SPINLOCK_LOCKED) +} + +void sched_note_spinunlock(FAR struct tcb_s *tcb, FAR volatile void *spinlock); +{ + note_spincommon(tcb, spinlock, NOTE_SPINLOCK_UNLOCK) +} +void sched_note_spinabort(FAR struct tcb_s *tcb, FAR volatile void *spinlock); +{ + note_spincommon(tcb, spinlock, NOTE_SPINLOCK_ABORT) +} +#endif + /**************************************************************************** * Name: sched_note_get * diff --git a/sched/semaphore/spinlock.c b/sched/semaphore/spinlock.c index 34a87126d2..ec0e406d86 100644 --- a/sched/semaphore/spinlock.c +++ b/sched/semaphore/spinlock.c @@ -44,6 +44,7 @@ #include #include +#include #include #include "sched/sched.h" @@ -119,11 +120,22 @@ void spin_initializer(FAR struct spinlock_s *lock) void spin_lock(FAR volatile spinlock_t *lock) { +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS + /* Notify that we are waiting for a spinlock */ + + sched_note_spinlock(this_task(), lock); +#endif + while (up_testset(lock) == SP_LOCKED) { SP_DSB(); } +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS + /* Notify that we have the spinlock */ + + sched_note_spinlocked(this_task(), lock); +#endif SP_DMB(); } @@ -147,6 +159,12 @@ void spin_lock(FAR volatile spinlock_t *lock) #ifdef __SP_UNLOCK_FUNCTION void spin_unlock(FAR volatile spinlock_t *lock) { +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS + /* Notify that we are unlocking the spinlock */ + + sched_note_spinunlock(this_task(), lock); +#endif + *lock = SP_UNLOCKED; SP_DMB(); } @@ -208,6 +226,13 @@ void spin_lockr(FAR struct spinlock_s *lock) # warning Missing logic #endif + +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS + /* Notify that we are waiting for a spinlock */ + + sched_note_spinlock(this_task(), &lock->sp_lock); +#endif + /* Take the lock. REVISIT: We should set an indication in the TCB * that the thread is spinning. This might be useful in determining * some scheduling actions? @@ -221,6 +246,12 @@ void spin_lockr(FAR struct spinlock_s *lock) SP_DSB(); } +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS + /* Notify that we have thespinlock */ + + sched_note_spinlocked(this_task(), &lock->sp_lock); +#endif + SP_DMB(); /* Take one count on the lock */ @@ -233,6 +264,12 @@ void spin_lockr(FAR struct spinlock_s *lock) #else /* CONFIG_SMP */ +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS + /* Notify that we are waiting for a spinlock */ + + sched_note_spinlock(this_task(), &lock->sp_lock); +#endif + /* Take the lock. REVISIT: We should set an indication in the TCB that * the thread is spinning. This might be useful in determining some * scheduling actions? @@ -244,6 +281,12 @@ void spin_lockr(FAR struct spinlock_s *lock) SP_DSB() } +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS + /* Notify that we have thespinlock */ + + sched_note_spinlocked(this_task(), &lock->sp_lock); +#endif + SP_DMB(); #endif /* CONFIG_SMP */ } @@ -303,6 +346,11 @@ void spin_unlockr(FAR struct spinlock_s *lock) if (lock->sp_count <= 1) { +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS + /* Notify that we are unlocking the spinlock */ + + sched_note_spinunlock(this_task(), &lock->sp_lock); +#endif /* The count must decremented to zero */ lock->sp_count = 0; @@ -318,6 +366,13 @@ void spin_unlockr(FAR struct spinlock_s *lock) up_irq_restore(flags); #else /* CONFIG_SMP */ + +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS + /* Notify that we are unlocking the spinlock */ + + sched_note_spinunlock(this_task(), &lock->sp_lock); +#endif + /* Just mark the spinlock unlocked */ DEBUGASSERT(lock != NULL && lock->sp_lock == SP_LOCKED); @@ -347,15 +402,31 @@ void spin_setbit(FAR volatile cpu_set_t *set, unsigned int cpu, FAR volatile spinlock_t *setlock, FAR volatile spinlock_t *orlock) { +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS + cpu_set_t prev; +#endif + /* First, get the 'setlock' spinlock */ spin_lock(setlock); /* Then set the bit and mark the 'orlock' as locked */ +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS + prev = *set; +#endif *set |= (1 << cpu); *orlock = SP_LOCKED; +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS + if (prev == 0) + { + /* Notify that we have locked the spinlock */ + + sched_note_spinlocked(this_task(), orlock); + } +#endif + /* Release the 'setlock' */ spin_unlock(setlock); @@ -382,6 +453,10 @@ void spin_clrbit(FAR volatile cpu_set_t *set, unsigned int cpu, FAR volatile spinlock_t *setlock, FAR volatile spinlock_t *orlock) { +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS + cpu_set_t prev; +#endif + /* First, get the 'setlock' spinlock */ spin_lock(setlock); @@ -390,9 +465,21 @@ void spin_clrbit(FAR volatile cpu_set_t *set, unsigned int cpu, * upon the resulting state of the CPU set. */ +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS + prev = *set; +#endif *set &= ~(1 << cpu); *orlock = (*set != 0) ? SP_LOCKED : SP_UNLOCKED; +#ifdef CONFIG_SCHED_INSTRUMENTATION_SPINLOCKS + if (prev != 0 && *set == 0) + { + /* Notify that we have unlocked the spinlock */ + + sched_note_spinunlock(this_task(), orlock); + } +#endif + /* Release the 'setlock' */ spin_unlock(setlock); -- GitLab From b568bfa81318eb88d9b589846a47eeee47ed0ebf Mon Sep 17 00:00:00 2001 From: Ramtin Amin Date: Mon, 28 Nov 2016 11:08:29 -0600 Subject: [PATCH 535/734] Misoc LM3: Add Misoc Ethernet driver. Integrate network support into configs/misoc/hello. Remove configs/misoc/include/generated directory. I suppose the the intent now is that this is a symbolic link? DANGER! This means that you cannot compile this code with first generating these files a providing a symbolic link to this location! --- arch/misoc/Kconfig | 7 + arch/misoc/src/common/misoc.h | 10 + arch/misoc/src/common/misoc_net.c | 1364 +++++++++++++++++ arch/misoc/src/lm32/Make.defs | 2 +- arch/misoc/src/lm32/lm32_schedulesigaction.c | 1 - configs/misoc/hello/defconfig | 294 +++- configs/misoc/include/generated/common.h | 49 - configs/misoc/include/generated/csr.h | 250 --- configs/misoc/include/generated/mem.h | 13 - .../misoc/include/generated/output_format.ld | 1 - configs/misoc/include/generated/regions.ld | 5 - configs/misoc/include/generated/sdram_phy.h | 80 - configs/misoc/include/generated/variables.mak | 11 - 13 files changed, 1660 insertions(+), 427 deletions(-) create mode 100644 arch/misoc/src/common/misoc_net.c delete mode 100644 configs/misoc/include/generated/common.h delete mode 100644 configs/misoc/include/generated/csr.h delete mode 100644 configs/misoc/include/generated/mem.h delete mode 100644 configs/misoc/include/generated/output_format.ld delete mode 100644 configs/misoc/include/generated/regions.ld delete mode 100644 configs/misoc/include/generated/sdram_phy.h delete mode 100644 configs/misoc/include/generated/variables.mak diff --git a/arch/misoc/Kconfig b/arch/misoc/Kconfig index 615b741c52..eee7005c38 100644 --- a/arch/misoc/Kconfig +++ b/arch/misoc/Kconfig @@ -43,6 +43,13 @@ config MISOC_UART1 select ARCH_HAVE_UART1 select MISOC_UART +config MISOC_ETHERNET + bool "Ethernet" + default n + select NETDEVICES + select ARCH_HAVE_PHY + select ARCH_HAVE_NETDEV_STATISTICS + endmenu # MISOC Peripheral Support config MISOC_UART diff --git a/arch/misoc/src/common/misoc.h b/arch/misoc/src/common/misoc.h index 1531f3dc7f..d708e97b48 100644 --- a/arch/misoc/src/common/misoc.h +++ b/arch/misoc/src/common/misoc.h @@ -73,6 +73,16 @@ void misoc_timer_initialize(void); +/**************************************************************************** + * Name: flush_cpu_dcache + * + * Description: + * flush cpu cache Data cache + * + ****************************************************************************/ + +void flush_cpu_dcache(void); + /**************************************************************************** * Name: up_serialinit * diff --git a/arch/misoc/src/common/misoc_net.c b/arch/misoc/src/common/misoc_net.c new file mode 100644 index 0000000000..b758d2d47e --- /dev/null +++ b/arch/misoc/src/common/misoc_net.c @@ -0,0 +1,1364 @@ +/**************************************************************************** + * arch/misoc/src/commong/misoc_net_net.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#if defined(CONFIG_NET) && defined(CONFIG_MISOC_ETHERNET) + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include "chip.h" +#include "hw/flags.h" +#include "hw/ethmac_mem.h" +#include "misoc.h" + +#ifdef CONFIG_NET_NOINTS +# include +#endif + +#ifdef CONFIG_NET_PKT +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If processing is not done at the interrupt level, then high priority + * work queue support is required. + */ + +#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_HPWORK) +# error High priority work queue support is required +#endif + +/* CONFIG_MISOC_NET_NINTERFACES determines the number of physical interfaces + * that will be supported. + */ + +#ifndef CONFIG_MISOC_NET_NINTERFACES +# define CONFIG_MISOC_NET_NINTERFACES 1 +#endif + +/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per second */ + +#define MISOC_NET_WDDELAY (1*CLK_TCK) + +/* TX timeout = 1 minute */ + +#define MISOC_NET_TXTIMEOUT (60*CLK_TCK) + +/* This is a helper pointer for accessing the contents of the Ethernet header */ + +#define BUF ((struct eth_hdr_s *)priv->misoc_net_dev.d_buf) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* The misoc_net_driver_s encapsulates all state information for a single hardware + * interface + */ + +struct misoc_net_driver_s +{ + bool misoc_net_bifup; /* true:ifup false:ifdown */ + WDOG_ID misoc_net_txpoll; /* TX poll timer */ + WDOG_ID misoc_net_txtimeout; /* TX timeout timer */ +#ifdef CONFIG_NET_NOINTS + struct work_s misoc_net_work; /* For deferring work to the work queue */ +#endif + + uint8_t *rx0_buf; /* 2 RX and 2 TX buffer */ + uint8_t *rx1_buf; + uint8_t *tx0_buf; + uint8_t *tx1_buf; + + uint8_t *tx_buf; + + + uint8_t tx_slot; /* The slot from which we send packet (tx0/tx1) */ + + /* This holds the information visible to the NuttX network */ + + struct net_driver_s misoc_net_dev; /* Interface understood by the network */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct misoc_net_driver_s g_misoc_net[CONFIG_MISOC_NET_NINTERFACES]; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Common TX logic */ + +static int misoc_net_transmit(FAR struct misoc_net_driver_s *priv); +static int misoc_net_txpoll(FAR struct net_driver_s *dev); + +/* Interrupt handling */ + +static void misoc_net_receive(FAR struct misoc_net_driver_s *priv); +static void misoc_net_txdone(FAR struct misoc_net_driver_s *priv); +static inline void misoc_net_interrupt_process(FAR struct misoc_net_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void misoc_net_interrupt_work(FAR void *arg); +#endif +static int misoc_net_interrupt(int irq, FAR void *context); + +/* Watchdog timer expirations */ + +static inline void misoc_net_txtimeout_process(FAR struct misoc_net_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void misoc_net_txtimeout_work(FAR void *arg); +#endif +static void misoc_net_txtimeout_expiry(int argc, wdparm_t arg, ...); + +static inline void misoc_net_poll_process(FAR struct misoc_net_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void misoc_net_poll_work(FAR void *arg); +#endif +static void misoc_net_poll_expiry(int argc, wdparm_t arg, ...); + +/* NuttX callback functions */ + +static int misoc_net_ifup(FAR struct net_driver_s *dev); +static int misoc_net_ifdown(FAR struct net_driver_s *dev); +static inline void misoc_net_txavail_process(FAR struct misoc_net_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void misoc_net_txavail_work(FAR void *arg); +#endif +static int misoc_net_txavail(FAR struct net_driver_s *dev); +#if defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_ICMPv6) +static int misoc_net_addmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac); +#ifdef CONFIG_NET_IGMP +static int misoc_net_rmmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac); +#endif +#ifdef CONFIG_NET_ICMPv6 +static void misoc_net_ipv6multicast(FAR struct misoc_net_driver_s *priv); +#endif +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: misoc_net_transmit + * + * Description: + * Start hardware transmission. Called either from the txdone interrupt + * handling or from watchdog based polling. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * the network is locked. + * + ****************************************************************************/ + +static int misoc_net_transmit(FAR struct misoc_net_driver_s *priv) +{ + /* Verify that the hardware is ready to send another packet. If we get + * here, then we are committed to sending a packet; Higher level logic + * must have assured that there is no transmission in progress. + */ + + /* Increment statistics */ + + NETDEV_TXPACKETS(priv->misoc_net_dev); + + /* Send the packet: address=priv->misoc_net_dev.d_buf, + * length=priv->misoc_net_dev.d_len + */ + + memcpy(priv->tx_buf, priv->misoc_net_dev.d_buf, + priv->misoc_net_dev.d_len); + + /* Choose the slot on which we write */ + + ethmac_sram_reader_slot_write(priv->tx_slot); + + /* Write the len */ + + if (priv->misoc_net_dev.d_len < 60) + { + ethmac_sram_reader_length_write(60); + } + else + { + ethmac_sram_reader_length_write(priv->misoc_net_dev.d_len); + } + + /* Trigger the writing */ + + ethmac_sram_reader_start_write(1); + + /* switch tx slot */ + + priv->tx_slot = (priv->tx_slot+1)%2; + if (priv->tx_slot) + { + priv->tx_buf = priv->tx1_buf; + } + else + { + priv->tx_buf = priv->tx0_buf; + } + + /* Enable Tx interrupts */ + + ethmac_sram_reader_ev_enable_write(1); + + /* Setup the TX timeout watchdog (perhaps restarting the timer) */ + + (void)wd_start(priv->misoc_net_txtimeout, MISOC_NET_TXTIMEOUT, + misoc_net_txtimeout_expiry, 1, (wdparm_t)priv); + return OK; +} + +/**************************************************************************** + * Function: misoc_net_txpoll + * + * Description: + * The transmitter is available, check if the network has any outgoing + * packets ready to send. This is a callback from devif_poll(). + * devif_poll() may be called: + * + * 1. When the preceding TX packet send is complete, + * 2. When the preceding TX packet send timesout and the interface is reset + * 3. During normal TX polling + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * the network is locked. + * + ****************************************************************************/ + +static int misoc_net_txpoll(FAR struct net_driver_s *dev) +{ + FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)dev->d_private; + + /* If the polling resulted in data that should be sent out on the network, + * the field d_len is set to a value > 0. + */ + + if (priv->misoc_net_dev.d_len > 0) + { + /* Look up the destination MAC address and add it to the Ethernet + * header. + */ + +#ifdef CONFIG_NET_IPv4 +#ifdef CONFIG_NET_IPv6 + if (IFF_IS_IPv4(priv->misoc_net_dev.d_flags)) +#endif + { + arp_out(&priv->misoc_net_dev); + } +#endif /* CONFIG_NET_IPv4 */ + +#ifdef CONFIG_NET_IPv6 +#ifdef CONFIG_NET_IPv4 + else +#endif + { + neighbor_out(&priv->misoc_net_dev); + } +#endif /* CONFIG_NET_IPv6 */ + + /* Send the packet */ + + misoc_net_transmit(priv); + + /* Check if there is room in the device to hold another packet. If not, + * return a non-zero value to terminate the poll. + */ + } + + /* If zero is returned, the polling will continue until all connections have + * been examined. + */ + + return 0; +} + +/**************************************************************************** + * Function: misoc_net_receive + * + * Description: + * An interrupt was received indicating the availability of a new RX packet + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +static void misoc_net_receive(FAR struct misoc_net_driver_s *priv) +{ + uint8_t rxslot; + uint32_t rxlen; + + do + { + /* Check for errors and update statistics */ + + /* Check if the packet is a valid size for the network buffer + * configuration. + */ + + /* Find rx slot */ + + rxslot = ethmac_sram_writer_slot_read(); + + /* Get rx len */ + + rxlen = ethmac_sram_writer_length_read(); + + /* Copy the data data from the hardware to priv->misoc_net_dev.d_buf. Set + * amount of data in priv->misoc_net_dev.d_len + */ + + flush_cpu_dcache(); + + if (rxslot) + { + memcpy(priv->misoc_net_dev.d_buf, priv->rx1_buf, rxlen); + } + else + { + memcpy(priv->misoc_net_dev.d_buf, priv->rx0_buf, rxlen); + } + + /* Clear event pending */ + + ethmac_sram_writer_ev_pending_write(1); + + priv->misoc_net_dev.d_len = rxlen; + +#ifdef CONFIG_NET_PKT + /* When packet sockets are enabled, feed the frame into the packet tap */ + + pkt_input(&priv->misoc_net_dev); +#endif + + /* We only accept IP packets of the configured type and ARP packets */ + +#ifdef CONFIG_NET_IPv4 + if (BUF->type == HTONS(ETHTYPE_IP)) + { + ninfo("IPv4 frame\n"); + NETDEV_RXIPV4(&priv->misoc_net_dev); + + /* Handle ARP on input then give the IPv4 packet to the network + * layer + */ + + arp_ipin(&priv->misoc_net_dev); + ipv4_input(&priv->misoc_net_dev); + + /* If the above function invocation resulted in data that should be + * sent out on the network, the field d_len will set to a value > 0. + */ + + if (priv->misoc_net_dev.d_len > 0) + { + /* Update the Ethernet header with the correct MAC address */ + +#ifdef CONFIG_NET_IPv6 + if (IFF_IS_IPv4(priv->misoc_net_dev.d_flags)) +#endif + { + arp_out(&priv->misoc_net_dev); + } +#ifdef CONFIG_NET_IPv6 + else + { + neighbor_out(&kel->misoc_net_dev); + } +#endif + + /* And send the packet */ + + misoc_net_transmit(priv); + } + } + else +#endif +#ifdef CONFIG_NET_IPv6 + if (BUF->type == HTONS(ETHTYPE_IP6)) + { + ninfo("Iv6 frame\n"); + NETDEV_RXIPV6(&priv->misoc_net_dev); + + /* Give the IPv6 packet to the network layer */ + + ipv6_input(&priv->misoc_net_dev); + + /* If the above function invocation resulted in data that should be + * sent out on the network, the field d_len will set to a value > 0. + */ + + if (priv->misoc_net_dev.d_len > 0) + { + /* Update the Ethernet header with the correct MAC address */ + +#ifdef CONFIG_NET_IPv4 + if (IFF_IS_IPv4(priv->misoc_net_dev.d_flags)) + { + arp_out(&priv->misoc_net_dev); + } + else +#endif +#ifdef CONFIG_NET_IPv6 + { + neighbor_out(&priv->misoc_net_dev); + } +#endif + + /* And send the packet */ + + misoc_net_transmit(priv); + } + } + else +#endif +#ifdef CONFIG_NET_ARP + if (BUF->type == htons(ETHTYPE_ARP)) + { + arp_arpin(&priv->misoc_net_dev); + NETDEV_RXARP(&priv->misoc_net_dev); + + /* If the above function invocation resulted in data that should be + * sent out on the network, the field d_len will set to a value > 0. + */ + + if (priv->misoc_net_dev.d_len > 0) + { + misoc_net_transmit(priv); + } + } +#endif + else + { + NETDEV_RXDROPPED(&priv->misoc_net_dev); + } + } + while (ethmac_sram_writer_ev_pending_read() & ETHMAC_EV_SRAM_WRITER); +} + +/**************************************************************************** + * Function: misoc_net_txdone + * + * Description: + * An interrupt was received indicating that the last TX packet(s) is done + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +static void misoc_net_txdone(FAR struct misoc_net_driver_s *priv) +{ + /* Check for errors and update statistics */ + + NETDEV_TXDONE(priv->misoc_net_dev); + + /* Check if there are pending transmissions */ + + /* If no further transmissions are pending, then cancel the TX timeout and + * disable further Tx interrupts. + */ + + wd_cancel(priv->misoc_net_txtimeout); + + /* Then make sure that the TX poll timer is running (if it is already + * running, the following would restart it). This is necessary to + * avoid certain race conditions where the polling sequence can be + * interrupted. + */ + + (void)wd_start(priv->misoc_net_txpoll, MISOC_NET_WDDELAY, + misoc_net_poll_expiry, 1, (wdparm_t)priv); + + /* And disable further TX interrupts. */ + + ethmac_sram_reader_ev_enable_write(0); + + /* In any event, poll the network for new TX data */ + + (void)devif_poll(&priv->misoc_net_dev, misoc_net_txpoll); +} + +/**************************************************************************** + * Function: misoc_net_interrupt_process + * + * Description: + * Interrupt processing. This may be performed either within the interrupt + * handler or on the worker thread, depending upon the configuration + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +static inline void misoc_net_interrupt_process(FAR struct misoc_net_driver_s *priv) +{ + /* Get and clear interrupt status bits */ + + /* Handle interrupts according to status bit settings */ + + /* Check if we received an incoming packet, if so, call misoc_net_receive() */ + + if (ethmac_sram_writer_ev_pending_read() & ETHMAC_EV_SRAM_WRITER) + { + misoc_net_receive(priv); + } + + /* Check if a packet transmission just completed. If so, call misoc_net_txdone. + * This may disable further Tx interrupts if there are no pending + * transmissions. + */ + + if (ethmac_sram_reader_ev_pending_read() & ETHMAC_EV_SRAM_READER) + { + misoc_net_txdone(priv); + ethmac_sram_reader_ev_pending_write(1); + } +} + +/**************************************************************************** + * Function: misoc_net_interrupt_work + * + * Description: + * Perform interrupt related work from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() was called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void misoc_net_interrupt_work(FAR void *arg) +{ + FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)arg; + net_lock_t state; + + /* Process pending Ethernet interrupts */ + + state = net_lock(); + misoc_net_interrupt_process(priv); + net_unlock(state); + + /* Re-enable Ethernet interrupts */ + + up_enable_irq(ETHMAC_INTERRUPT); +} +#endif + +/**************************************************************************** + * Function: misoc_net_interrupt + * + * Description: + * Hardware interrupt handler + * + * Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * OK on success + * + * Assumptions: + * + ****************************************************************************/ + +static int misoc_net_interrupt(int irq, FAR void *context) +{ + FAR struct misoc_net_driver_s *priv = &g_misoc_net[0]; + +#ifdef CONFIG_NET_NOINTS + /* Disable further Ethernet interrupts. Because Ethernet interrupts are + * also disabled if the TX timeout event occurs, there can be no race + * condition here. + */ + + /* TODO: Determine if a TX transfer just completed */ + + if (ethmac_sram_reader_ev_pending_read() & ETHMAC_EV_SRAM_READER) + { + /* If a TX transfer just completed, then cancel the TX timeout so + * there will be do race condition between any subsequent timeout + * expiration and the deferred interrupt processing. + */ + + wd_cancel(priv->misoc_net_txtimeout); + } + + /* Cancel any pending poll work */ + + work_cancel(HPWORK, &priv->misoc_net_work); + + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(HPWORK, &priv->misoc_net_work, misoc_net_interrupt_work, priv, 0); + +#else + /* Process the interrupt now */ + + misoc_net_interrupt_process(priv); + +#endif + + return OK; +} + +/**************************************************************************** + * Function: misoc_net_txtimeout_process + * + * Description: + * Process a TX timeout. Called from the either the watchdog timer + * expiration logic or from the worker thread, depending upon the + * configuration. The timeout means that the last TX never completed. + * Reset the hardware and start again. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void misoc_net_txtimeout_process(FAR struct misoc_net_driver_s *priv) +{ + /* Increment statistics and dump debug info */ + + NETDEV_TXTIMEOUTS(priv->misoc_net_dev); + + /* Then reset the hardware */ + + /* Then poll the network for new XMIT data */ + + (void)devif_poll(&priv->misoc_net_dev, misoc_net_txpoll); +} + +/**************************************************************************** + * Function: misoc_net_txtimeout_work + * + * Description: + * Perform TX timeout related work from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void misoc_net_txtimeout_work(FAR void *arg) +{ + FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)arg; + net_lock_t state; + + /* Process pending Ethernet interrupts */ + + state = net_lock(); + misoc_net_txtimeout_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: misoc_net_txtimeout_expiry + * + * Description: + * Our TX watchdog timed out. Called from the timer interrupt handler. + * The last TX never completed. Reset the hardware and start again. + * + * Parameters: + * argc - The number of available arguments + * arg - The first argument + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * + ****************************************************************************/ + +static void misoc_net_txtimeout_expiry(int argc, wdparm_t arg, ...) +{ + FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)arg; + +#ifdef CONFIG_NET_NOINTS + /* Disable further Ethernet interrupts. This will prevent some race + * conditions with interrupt work. There is still a potential race + * condition with interrupt work that is already queued and in progress. + */ + + //up_disable_irq(ETHMAC_INTERRUPT); + + /* Cancel any pending poll or interrupt work. This will have no effect + * on work that has already been started. + */ + + work_cancel(HPWORK, &priv->misoc_net_work); + + /* Schedule to perform the TX timeout processing on the worker thread. */ + + work_queue(HPWORK, &priv->misoc_net_work, misoc_net_txtimeout_work, priv, 0); +#else + /* Process the timeout now */ + + misoc_net_txtimeout_process(priv); +#endif +} + +/**************************************************************************** + * Function: misoc_net_poll_process + * + * Description: + * Perform the periodic poll. This may be called either from watchdog + * timer logic or from the worker thread, depending upon the configuration. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static inline void misoc_net_poll_process(FAR struct misoc_net_driver_s *priv) +{ + /* Check if there is room in the send another TX packet. We cannot perform + * the TX poll if he are unable to accept another packet for transmission. + */ + + /* If so, update TCP timing states and poll the network for new XMIT data. + * Hmmm.. might be bug here. Does this mean if there is a transmit in + * progress, we will missing TCP time state updates? + */ + + (void)devif_timer(&priv->misoc_net_dev, misoc_net_txpoll); + + /* Setup the watchdog poll timer again */ + + (void)wd_start(priv->misoc_net_txpoll, MISOC_NET_WDDELAY, misoc_net_poll_expiry, 1, + (wdparm_t)priv); +} + +/**************************************************************************** + * Function: misoc_net_poll_work + * + * Description: + * Perform periodic polling from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void misoc_net_poll_work(FAR void *arg) +{ + FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)arg; + net_lock_t state; + + /* Perform the poll */ + + state = net_lock(); + misoc_net_poll_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: misoc_net_poll_expiry + * + * Description: + * Periodic timer handler. Called from the timer interrupt handler. + * + * Parameters: + * argc - The number of available arguments + * arg - The first argument + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * + ****************************************************************************/ + +static void misoc_net_poll_expiry(int argc, wdparm_t arg, ...) +{ + FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)arg; + +#ifdef CONFIG_NET_NOINTS + /* Is our single work structure available? It may not be if there are + * pending interrupt actions. + */ + + if (work_available(&priv->misoc_net_work)) + { + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(HPWORK, &priv->misoc_net_work, misoc_net_poll_work, priv, 0); + } + else + { + /* No.. Just re-start the watchdog poll timer, missing one polling + * cycle. + */ + + (void)wd_start(priv->misoc_net_txpoll, MISOC_NET_WDDELAY, misoc_net_poll_expiry, 1, arg); + } + +#else + /* Process the interrupt now */ + + misoc_net_poll_process(priv); +#endif +} + +/**************************************************************************** + * Function: misoc_net_ifup + * + * Description: + * NuttX Callback: Bring up the Ethernet interface when an IP address is + * provided + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int misoc_net_ifup(FAR struct net_driver_s *dev) +{ + FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)dev->d_private; + +#ifdef CONFIG_NET_IPv4 + ninfo("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); +#endif +#ifdef CONFIG_NET_IPv6 + ninfo("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", + dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2], + dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5], + dev->d_ipv6addr[6], dev->d_ipv6addr[7]); +#endif + + /* Initialize PHYs, the Ethernet interface, and setup up Ethernet interrupts */ + + /* Instantiate the MAC address from priv->misoc_net_dev.d_mac.ether_addr_octet */ + +#ifdef CONFIG_NET_ICMPv6 + /* Set up IPv6 multicast address filtering */ + + misoc_net_ipv6multicast(priv); +#endif + + /* Set and activate a timer process */ + + (void)wd_start(priv->misoc_net_txpoll, MISOC_NET_WDDELAY, misoc_net_poll_expiry, 1, + (wdparm_t)priv); + + priv->misoc_net_bifup = true; + up_enable_irq(ETHMAC_INTERRUPT); + + /* Enable the RX Event Handler */ + + ethmac_sram_writer_ev_enable_write(1); + return OK; +} + +/**************************************************************************** + * Function: misoc_net_ifdown + * + * Description: + * NuttX Callback: Stop the interface. + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int misoc_net_ifdown(FAR struct net_driver_s *dev) +{ + FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)dev->d_private; + irqstate_t flags; + + /* Disable the Ethernet interrupt */ + + flags = enter_critical_section(); + up_disable_irq(ETHMAC_INTERRUPT); + + /* Cancel the TX poll timer and TX timeout timers */ + + wd_cancel(priv->misoc_net_txpoll); + wd_cancel(priv->misoc_net_txtimeout); + + /* Put the EMAC in its reset, non-operational state. This should be + * a known configuration that will guarantee the misoc_net_ifup() always + * successfully brings the interface back up. + */ + + /* Mark the device "down" */ + + priv->misoc_net_bifup = false; + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Function: misoc_net_txavail_process + * + * Description: + * Perform an out-of-cycle poll. + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static inline void misoc_net_txavail_process(FAR struct misoc_net_driver_s *priv) +{ + /* Ignore the notification if the interface is not yet up */ + + if (priv->misoc_net_bifup) + { + /* Check if there is room in the hardware to hold another outgoing packet. */ + + if (!ethmac_sram_reader_ready_read()) + { + /* If so, then poll the network for new XMIT data */ + + (void)devif_poll(&priv->misoc_net_dev, misoc_net_txpoll); + } + } +} + +/**************************************************************************** + * Function: misoc_net_txavail_work + * + * Description: + * Perform an out-of-cycle poll on the worker thread. + * + * Parameters: + * arg - Reference to the NuttX driver state structure (cast to void*) + * + * Returned Value: + * None + * + * Assumptions: + * Called on the higher priority worker thread. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void misoc_net_txavail_work(FAR void *arg) +{ + FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)arg; + net_lock_t state; + + /* Perform the poll */ + + state = net_lock(); + misoc_net_txavail_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: misoc_net_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static int misoc_net_txavail(FAR struct net_driver_s *dev) +{ + FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)dev->d_private; + +#ifdef CONFIG_NET_NOINTS + /* Is our single work structure available? It may not be if there are + * pending interrupt actions and we will have to ignore the Tx + * availability action. + */ + + if (work_available(&priv->misoc_net_work)) + { + /* Schedule to serialize the poll on the worker thread. */ + + work_queue(HPWORK, &priv->misoc_net_work, misoc_net_txavail_work, priv, 0); + } + +#else + irqstate_t flags; + + /* Disable interrupts because this function may be called from interrupt + * level processing. + */ + + flags = enter_critical_section(); + + /* Perform the out-of-cycle poll now */ + + misoc_net_txavail_process(priv); + leave_critical_section(flags); +#endif + + return OK; +} + +/**************************************************************************** + * Function: misoc_net_addmac + * + * Description: + * NuttX Callback: Add the specified MAC address to the hardware multicast + * address filtering + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * mac - The MAC address to be added + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +#if defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_ICMPv6) +static int misoc_net_addmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac) +{ + FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)dev->d_private; + + /* Add the MAC address to the hardware multicast routing table */ + + return OK; +} +#endif + +/**************************************************************************** + * Function: misoc_net_rmmac + * + * Description: + * NuttX Callback: Remove the specified MAC address from the hardware multicast + * address filtering + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * mac - The MAC address to be removed + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NET_IGMP +static int misoc_net_rmmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac) +{ + FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)dev->d_private; + + /* Add the MAC address to the hardware multicast routing table */ + + return OK; +} +#endif + +/**************************************************************************** + * Function: misoc_net_ipv6multicast + * + * Description: + * Configure the IPv6 multicast MAC address. + * + * Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NET_ICMPv6 +static void misoc_net_ipv6multicast(FAR struct misoc_net_driver_s *priv) +{ + FAR struct net_driver_s *dev; + uint16_t tmp16; + uint8_t mac[6]; + + /* For ICMPv6, we need to add the IPv6 multicast address + * + * For IPv6 multicast addresses, the Ethernet MAC is derived by + * the four low-order octets OR'ed with the MAC 33:33:00:00:00:00, + * so for example the IPv6 address FF02:DEAD:BEEF::1:3 would map + * to the Ethernet MAC address 33:33:00:01:00:03. + * + * NOTES: This appears correct for the ICMPv6 Router Solicitation + * Message, but the ICMPv6 Neighbor Solicitation message seems to + * use 33:33:ff:01:00:03. + */ + + mac[0] = 0x33; + mac[1] = 0x33; + + dev = &priv->dev; + tmp16 = dev->d_ipv6addr[6]; + mac[2] = 0xff; + mac[3] = tmp16 >> 8; + + tmp16 = dev->d_ipv6addr[7]; + mac[4] = tmp16 & 0xff; + mac[5] = tmp16 >> 8; + + ninfo("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + + (void)misoc_net_addmac(dev, mac); + +#ifdef CONFIG_NET_ICMPv6_AUTOCONF + /* Add the IPv6 all link-local nodes Ethernet address. This is the + * address that we expect to receive ICMPv6 Router Advertisement + * packets. + */ + + (void)misoc_net_addmac(dev, g_ipv6_ethallnodes.ether_addr_octet); + +#endif /* CONFIG_NET_ICMPv6_AUTOCONF */ +#ifdef CONFIG_NET_ICMPv6_ROUTER + /* Add the IPv6 all link-local routers Ethernet address. This is the + * address that we expect to receive ICMPv6 Router Solicitation + * packets. + */ + + (void)misoc_net_addmac(dev, g_ipv6_ethallrouters.ether_addr_octet); + +#endif /* CONFIG_NET_ICMPv6_ROUTER */ +} +#endif /* CONFIG_NET_ICMPv6 */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: misoc_net_initialize + * + * Description: + * Initialize the Ethernet controller and driver + * + * Parameters: + * intf - In the case where there are multiple EMACs, this value + * identifies which EMAC is to be initialized. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +int misoc_net_initialize(int intf) +{ + FAR struct misoc_net_driver_s *priv; + + /* Get the interface structure associated with this interface number. */ + + DEBUGASSERT(intf < CONFIG_MISOC_NET_NINTERFACES); + priv = &g_misoc_net[intf]; + + /* Check if a Ethernet chip is recognized at its I/O base */ + + /* Attach the IRQ to the driver */ + + if (irq_attach(ETHMAC_INTERRUPT, misoc_net_interrupt)) + { + /* We could not attach the ISR to the interrupt */ + + return -EAGAIN; + } + + /* clear pending int */ + + ethmac_sram_writer_ev_pending_write(1); + ethmac_sram_reader_ev_pending_write(1); + + /* Initialize the driver structure */ + + memset(priv, 0, sizeof(struct misoc_net_driver_s)); + priv->rx0_buf = (uint8_t *)ETHMAC_RX0_BASE; + priv->rx1_buf = (uint8_t *)ETHMAC_RX1_BASE; + priv->tx0_buf = (uint8_t *)ETHMAC_TX0_BASE; + priv->tx1_buf = (uint8_t *)ETHMAC_TX1_BASE; + priv->tx_buf = priv->tx0_buf; + priv->tx_slot=0; + + priv->misoc_net_dev.d_ifup = misoc_net_ifup; /* I/F up (new IP address) callback */ + priv->misoc_net_dev.d_ifdown = misoc_net_ifdown; /* I/F down callback */ + priv->misoc_net_dev.d_txavail = misoc_net_txavail; /* New TX data callback */ +#ifdef CONFIG_NET_IGMP + priv->misoc_net_dev.d_addmac = misoc_net_addmac; /* Add multicast MAC address */ + priv->misoc_net_dev.d_rmmac = misoc_net_rmmac; /* Remove multicast MAC address */ +#endif + priv->misoc_net_dev.d_private = (FAR void *)g_misoc_net; /* Used to recover private state from dev */ + + /* Create a watchdog for timing polling for and timing of transmisstions */ + + priv->misoc_net_txpoll = wd_create(); /* Create periodic poll timer */ + priv->misoc_net_txtimeout = wd_create(); /* Create TX timeout timer */ + + /* Put the interface in the down state. This usually amounts to resetting + * the device and/or calling misoc_net_ifdown(). + */ + + /* Read the MAC address from the hardware into + * priv->misoc_net_dev.d_mac.ether_addr_octet + */ + + /* Register the device with the OS so that socket IOCTLs can be performed */ + + (void)netdev_register(&priv->misoc_net_dev, NET_LL_ETHERNET); + return OK; +} + +#endif /* CONFIG_NET && CONFIG_MISOC_NET_ETHERNET */ diff --git a/arch/misoc/src/lm32/Make.defs b/arch/misoc/src/lm32/Make.defs index addffc5984..7206117487 100644 --- a/arch/misoc/src/lm32/Make.defs +++ b/arch/misoc/src/lm32/Make.defs @@ -39,7 +39,7 @@ HEAD_ASRC = lm32_vectors.S CMN_ASRCS = CMN_CSRCS = misoc_lowputs.c misoc_serial.c misoc_mdelay.c CMN_CSRCS += misoc_modifyreg8.c misoc_modifyreg16.c misoc_modifyreg32.c -CMN_CSRCS += misoc_puts.c misoc_udelay.c misoc_timerisr.c +CMN_CSRCS += misoc_puts.c misoc_udelay.c misoc_timerisr.c misoc_net.c CHIP_ASRCS = lm32_syscall.S diff --git a/arch/misoc/src/lm32/lm32_schedulesigaction.c b/arch/misoc/src/lm32/lm32_schedulesigaction.c index 15f06e0e77..3b0b395c4a 100644 --- a/arch/misoc/src/lm32/lm32_schedulesigaction.c +++ b/arch/misoc/src/lm32/lm32_schedulesigaction.c @@ -97,7 +97,6 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) { irqstate_t flags; - uint32_t int_ctx; sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver); diff --git a/configs/misoc/hello/defconfig b/configs/misoc/hello/defconfig index 0fd2918d18..d18aef2c75 100644 --- a/configs/misoc/hello/defconfig +++ b/configs/misoc/hello/defconfig @@ -59,6 +59,7 @@ CONFIG_DEBUG_FEATURES=y # CONFIG_DEBUG_GRAPHICS is not set # CONFIG_DEBUG_LIB is not set # CONFIG_DEBUG_MM is not set +# CONFIG_DEBUG_NET is not set # CONFIG_DEBUG_SCHED is not set # @@ -105,6 +106,7 @@ CONFIG_ARCH_CHIP_LM32=y # CONFIG_MISOC_HAVE_UART1=y CONFIG_MISOC_UART1=y +CONFIG_MISOC_ETHERNET=y CONFIG_MISOC_UART=y CONFIG_MISOC_UART_RX_BUF_SIZE=64 CONFIG_MISOC_UART_TX_BUF_SIZE=64 @@ -131,7 +133,7 @@ CONFIG_LM32_TOOLCHAIN_GNUL=y # CONFIG_ARCH_HAVE_POWEROFF is not set # CONFIG_ARCH_HAVE_RESET is not set CONFIG_ARCH_STACKDUMP=y -# CONFIG_ENDIAN_BIG is not set +CONFIG_ENDIAN_BIG=y # CONFIG_ARCH_IDLE_CUSTOM is not set # CONFIG_ARCH_HAVE_RAMFUNCS is not set # CONFIG_ARCH_HAVE_RAMVECTORS is not set @@ -178,6 +180,7 @@ CONFIG_ARCH_BOARD_CUSTOM_DIR="/configs/misoc/" CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y # CONFIG_BOARD_CUSTOM_LEDS is not set # CONFIG_BOARD_CUSTOM_BUTTONS is not set +# CONFIG_BOARD_CUSTOM_INTERRUPT is not set # # Common Board Options @@ -192,7 +195,12 @@ CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y # # RTOS Features # -# CONFIG_DISABLE_OS_API is not set +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set # # Clocks and Timers @@ -206,9 +214,9 @@ CONFIG_START_YEAR=2011 CONFIG_START_MONTH=6 CONFIG_START_DAY=16 CONFIG_MAX_WDOGPARMS=2 -CONFIG_PREALLOC_WDOGS=4 -CONFIG_WDOG_INTRESERVE=0 -CONFIG_PREALLOC_TIMERS=0 +CONFIG_PREALLOC_WDOGS=8 +CONFIG_WDOG_INTRESERVE=1 +CONFIG_PREALLOC_TIMERS=4 # # Tasks and Scheduling @@ -290,7 +298,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 # # Device Drivers # -CONFIG_DISABLE_POLL=y +# CONFIG_DISABLE_POLL is not set CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set # CONFIG_DEV_URANDOM is not set @@ -349,6 +357,50 @@ CONFIG_DEV_NULL=y # CONFIG_MODEM is not set # CONFIG_MTD is not set # CONFIG_EEPROM is not set +CONFIG_NETDEVICES=y + +# +# General Ethernet MAC Driver Options +# +# CONFIG_NETDEV_LOOPBACK is not set +CONFIG_NETDEV_TELNET=y +CONFIG_TELNET_RXBUFFER_SIZE=256 +CONFIG_TELNET_TXBUFFER_SIZE=256 +# CONFIG_NETDEV_MULTINIC is not set +CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y +# CONFIG_NETDEV_LATEINIT is not set +# CONFIG_NET_DUMPPACKET is not set + +# +# External Ethernet MAC Device Support +# +# CONFIG_NET_DM90x0 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ENCX24J600 is not set +# CONFIG_NET_E1000 is not set +# CONFIG_NET_SLIP is not set +# CONFIG_NET_FTMAC100 is not set +# CONFIG_NET_VNET is not set + +# +# External Ethernet PHY Device Support +# +# CONFIG_ARCH_PHY_INTERRUPT is not set +CONFIG_ETH0_PHY_NONE=y +# CONFIG_ETH0_PHY_AM79C874 is not set +# CONFIG_ETH0_PHY_KS8721 is not set +# CONFIG_ETH0_PHY_KSZ8041 is not set +# CONFIG_ETH0_PHY_KSZ8051 is not set +# CONFIG_ETH0_PHY_KSZ8061 is not set +# CONFIG_ETH0_PHY_KSZ8081 is not set +# CONFIG_ETH0_PHY_KSZ90x1 is not set +# CONFIG_ETH0_PHY_DP83848C is not set +# CONFIG_ETH0_PHY_LAN8720 is not set +# CONFIG_ETH0_PHY_LAN8740 is not set +# CONFIG_ETH0_PHY_LAN8740A is not set +# CONFIG_ETH0_PHY_LAN8742A is not set +# CONFIG_ETH0_PHY_DM9161 is not set +# CONFIG_NETDEV_PHY_DEBUG is not set # CONFIG_PIPES is not set # CONFIG_PM is not set # CONFIG_POWER is not set @@ -428,9 +480,117 @@ CONFIG_SYSLOG_CONSOLE=y # # Networking Support # -# CONFIG_ARCH_HAVE_NET is not set -# CONFIG_ARCH_HAVE_PHY is not set -# CONFIG_NET is not set +CONFIG_ARCH_HAVE_NET=y +CONFIG_ARCH_HAVE_PHY=y +CONFIG_NET=y +# CONFIG_NET_NOINTS is not set +# CONFIG_NET_PROMISCUOUS is not set + +# +# Driver buffer configuration +# +# CONFIG_NET_MULTIBUFFER is not set +CONFIG_NET_ETH_MTU=1400 +CONFIG_NET_ETH_TCP_RECVWNDO=742 +CONFIG_NET_GUARDSIZE=648 + +# +# Data link support +# +# CONFIG_NET_MULTILINK is not set +CONFIG_NET_ETHERNET=y +# CONFIG_NET_LOOPBACK is not set +# CONFIG_NET_TUN is not set + +# +# Network Device Operations +# +# CONFIG_NETDEV_PHY_IOCTL is not set + +# +# Internet Protocol Selection +# +CONFIG_NET_IPv4=y +# CONFIG_NET_IPv6 is not set + +# +# Socket Support +# +CONFIG_NSOCKET_DESCRIPTORS=8 +CONFIG_NET_NACTIVESOCKETS=16 +CONFIG_NET_SOCKOPTS=y +# CONFIG_NET_SOLINGER is not set + +# +# Raw Socket Support +# +# CONFIG_NET_PKT is not set + +# +# TCP/IP Networking +# +CONFIG_NET_TCP=y +# CONFIG_NET_TCPURGDATA is not set +CONFIG_NET_TCP_CONNS=40 +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_TCP_READAHEAD=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_TCP_NWRBCHAINS=8 +# CONFIG_NET_TCP_WRBUFFER_DEBUG is not set +CONFIG_NET_TCP_RECVDELAY=0 +# CONFIG_NET_TCPBACKLOG is not set +# CONFIG_NET_SENDFILE is not set + +# +# UDP Networking +# +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NET_UDP_CONNS=8 +CONFIG_NET_BROADCAST=y +# CONFIG_NET_RXAVAIL is not set +CONFIG_NET_UDP_READAHEAD=y + +# +# ICMP Networking Support +# +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_PING=y + +# +# IGMPv2 Client Support +# +# CONFIG_NET_IGMP is not set + +# +# ARP Configuration +# +CONFIG_NET_ARP=y +CONFIG_NET_ARPTAB_SIZE=16 +CONFIG_NET_ARP_MAXAGE=120 +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_ARP_SEND=y +CONFIG_ARP_SEND_MAXTRIES=5 +CONFIG_ARP_SEND_DELAYMSEC=20 + +# +# Network I/O Buffer Support +# +CONFIG_NET_IOB=y +CONFIG_IOB_NBUFFERS=24 +CONFIG_IOB_BUFSIZE=196 +CONFIG_IOB_NCHAINS=8 +CONFIG_IOB_THROTTLE=8 +# CONFIG_IOB_DEBUG is not set +# CONFIG_NET_ARCH_INCR32 is not set +# CONFIG_NET_ARCH_CHKSUM is not set +# CONFIG_NET_STATISTICS is not set + +# +# Routing Table Configuration +# +# CONFIG_NET_ROUTE is not set +CONFIG_NET_HOSTNAME="nuttx" # # Crypto API @@ -495,14 +655,14 @@ CONFIG_BUILTIN=y # # Standard C Library Options # -CONFIG_STDIO_BUFFER_SIZE=0 +CONFIG_STDIO_BUFFER_SIZE=64 CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=0 +CONFIG_NUNGET_CHARS=2 CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBM is not set # CONFIG_NOPRINTF_FIELDWIDTH is not set # CONFIG_LIBC_FLOATINGPOINT is not set -# CONFIG_LIBC_LONG_LONG is not set +CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set # CONFIG_LIBC_WCHAR is not set # CONFIG_LIBC_LOCALE is not set @@ -523,7 +683,15 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_ARCH_ROMGETC is not set # CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set # CONFIG_ARCH_HAVE_TLS is not set -# CONFIG_LIBC_NETDB is not set +CONFIG_LIBC_NETDB=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSCLIENT_ENTRIES=8 +CONFIG_NETDB_DNSCLIENT_NAMESIZE=32 +CONFIG_NETDB_DNSCLIENT_LIFESEC=3600 +CONFIG_NETDB_DNSCLIENT_MAXRESPONSE=96 +# CONFIG_NETDB_DNSSERVER_NOADDR is not set +CONFIG_NETDB_DNSSERVER_IPv4=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x08080808 # # Non-standard Library Support @@ -537,7 +705,14 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # Basic CXX Support # # CONFIG_C99_BOOL8 is not set -# CONFIG_HAVE_CXX is not set +CONFIG_HAVE_CXX=y +# CONFIG_HAVE_CXXINITIALIZE is not set +# CONFIG_CXX_NEWLONG is not set + +# +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set # # Application Configuration @@ -558,13 +733,16 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set # CONFIG_EXAMPLES_FTPD is not set CONFIG_EXAMPLES_HELLO=y CONFIG_EXAMPLES_HELLO_PRIORITY=100 CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 +# CONFIG_EXAMPLES_HELLOXX is not set # CONFIG_EXAMPLES_HIDKBD is not set # CONFIG_EXAMPLES_IGMP is not set # CONFIG_EXAMPLES_JSON is not set @@ -573,6 +751,20 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 # CONFIG_EXAMPLES_MM is not set # CONFIG_EXAMPLES_MODBUS is not set # CONFIG_EXAMPLES_MOUNT is not set +CONFIG_EXAMPLES_NETTEST=y +# CONFIG_EXAMPLES_NETTEST_SERVER is not set +CONFIG_EXAMPLES_NETTEST_PERFORMANCE=y +CONFIG_EXAMPLES_NETTEST_IPv4=y +CONFIG_EXAMPLES_NETTEST_INIT=y +CONFIG_EXAMPLES_NETTEST_NOMAC=y + +# +# IPv4 addresses +# +CONFIG_EXAMPLES_NETTEST_IPADDR=0xc0a80132 +CONFIG_EXAMPLES_NETTEST_DRIPADDR=0xc0a80101 +CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00 +CONFIG_EXAMPLES_NETTEST_CLIENTIP=0xc0a8023b # CONFIG_EXAMPLES_NRF24L01TERM is not set CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NULL is not set @@ -604,13 +796,27 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y # CONFIG_EXAMPLES_SMART is not set # CONFIG_EXAMPLES_SMART_TEST is not set # CONFIG_EXAMPLES_SMP is not set -# CONFIG_EXAMPLES_TCPECHO is not set -# CONFIG_EXAMPLES_TELNETD is not set +CONFIG_EXAMPLES_TCPECHO=y +CONFIG_EXAMPLES_TCPECHO_PORT=80 +CONFIG_EXAMPLES_TCPECHO_BACKLOG=8 +CONFIG_EXAMPLES_TCPECHO_NCONN=8 +CONFIG_EXAMPLES_TELNETD=y +CONFIG_EXAMPLES_TELNETD_NOMAC=y +CONFIG_EXAMPLES_TELNETD_IPADDR=0xc0a80132 +CONFIG_EXAMPLES_TELNETD_DRIPADDR=0xc0a80101 +CONFIG_EXAMPLES_TELNETD_NETMASK=0xffffff00 +CONFIG_EXAMPLES_TELNETD_DAEMONPRIO=100 +CONFIG_EXAMPLES_TELNETD_DAEMONSTACKSIZE=2048 +CONFIG_EXAMPLES_TELNETD_CLIENTPRIO=100 +CONFIG_EXAMPLES_TELNETD_CLIENTSTACKSIZE=2048 # CONFIG_EXAMPLES_TIFF is not set # CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_UDPBLASTER is not set +# CONFIG_EXAMPLES_UDP is not set # CONFIG_EXAMPLES_USBTERM is not set # CONFIG_EXAMPLES_WATCHDOG is not set # CONFIG_EXAMPLES_WEBSERVER is not set +# CONFIG_EXAMPLES_XMLRPC is not set # # File System Utilities @@ -644,11 +850,32 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y # # Network Utilities # +# CONFIG_NETUTILS_CHAT is not set # CONFIG_NETUTILS_CODECS is not set +CONFIG_NETUTILS_DHCPC=y +# CONFIG_NETUTILS_DHCPD is not set +CONFIG_NETUTILS_DISCOVER=y +CONFIG_DISCOVER_STACK_SIZE=1024 +CONFIG_DISCOVER_PRIORITY=50 +CONFIG_DISCOVER_PORT=96 +CONFIG_DISCOVER_INTERFACE="eth0" +CONFIG_DISCOVER_DEVICE_CLASS=0xff +CONFIG_DISCOVER_DESCR="NuttX" # CONFIG_NETUTILS_ESP8266 is not set # CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_FTPD is not set # CONFIG_NETUTILS_JSON is not set +CONFIG_NETUTILS_NETLIB=y +# CONFIG_NETUTILS_NTPCLIENT is not set +# CONFIG_NETUTILS_PPPD is not set # CONFIG_NETUTILS_SMTP is not set +CONFIG_NETUTILS_TELNETD=y +# CONFIG_NETUTILS_TFTPC is not set +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NSH_WGET_USERAGENT="NuttX/6.xx.x (; http://www.nuttx.org/)" +CONFIG_WEBCLIENT_TIMEOUT=10 +# CONFIG_NETUTILS_WEBSERVER is not set +# CONFIG_NETUTILS_XMLRPC is not set # # NSH Library @@ -673,6 +900,7 @@ CONFIG_NSH_BUILTIN_APPS=y # Disable Individual commands # # CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_ARP is not set # CONFIG_NSH_DISABLE_BASENAME is not set # CONFIG_NSH_DISABLE_CAT is not set # CONFIG_NSH_DISABLE_CD is not set @@ -703,8 +931,10 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_NSLOOKUP is not set CONFIG_NSH_DISABLE_PRINTF=y CONFIG_NSH_DISABLE_PS=y +# CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set # CONFIG_NSH_DISABLE_RM is not set @@ -743,6 +973,37 @@ CONFIG_NSH_FILEIOSIZE=1024 CONFIG_NSH_CONSOLE=y # CONFIG_NSH_ALTCONDEV is not set # CONFIG_NSH_ARCHINIT is not set + +# +# Networking Configuration +# +CONFIG_NSH_NETINIT=y +CONFIG_NSH_NETINIT_THREAD=y +CONFIG_NSH_NETINIT_THREAD_STACKSIZE=1568 +CONFIG_NSH_NETINIT_THREAD_PRIORITY=80 +CONFIG_NSH_NETINIT_DEBUG=y + +# +# IP Address Configuration +# +# CONFIG_NSH_DHCPC is not set + +# +# IPv4 Addresses +# +CONFIG_NSH_IPADDR=0xc0a80132 +CONFIG_NSH_DRIPADDR=0xc0a80101 +CONFIG_NSH_NETMASK=0xffffff00 +# CONFIG_NSH_DNS is not set +CONFIG_NSH_NOMAC=y +CONFIG_NSH_SWMAC=y +CONFIG_NSH_MACADDR=0x00e0deadbeef +CONFIG_NSH_MAX_ROUNDTRIP=20 + +# +# Telnet Configuration +# +# CONFIG_NSH_TELNET is not set # CONFIG_NSH_LOGIN is not set # CONFIG_NSH_CONSOLE_LOGIN is not set @@ -765,6 +1026,7 @@ CONFIG_SYSTEM_CLE_DEBUGLEVEL=0 # CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_NETDB is not set # CONFIG_SYSTEM_RAMTEST is not set CONFIG_READLINE_HAVE_EXTMATCH=y CONFIG_SYSTEM_READLINE=y diff --git a/configs/misoc/include/generated/common.h b/configs/misoc/include/generated/common.h deleted file mode 100644 index 38859deefa..0000000000 --- a/configs/misoc/include/generated/common.h +++ /dev/null @@ -1,49 +0,0 @@ -/**************************************************************************** - * configs/misoc/include/generated/common.h - * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Ramtin Amin - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __CONFIGS_MISOC_INCLUDE_GENERATED_COMMON_H -#define __CONFIGS_MISOC_INCLUDE_GENERATED_COMMON_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef __ASSEMBLER__ -# define MMPTR(x) x -#else -# define MMPTR(x) (*((volatile unsigned int *)(x))) -#endif - -#endif /* __CONFIGS_MISOC_INCLUDE_GENERATED_COMMON_H */ diff --git a/configs/misoc/include/generated/csr.h b/configs/misoc/include/generated/csr.h deleted file mode 100644 index abfa8b39cd..0000000000 --- a/configs/misoc/include/generated/csr.h +++ /dev/null @@ -1,250 +0,0 @@ -#ifndef __GENERATED_CSR_H -#define __GENERATED_CSR_H -#include - -/* sdram */ -#define CSR_SDRAM_BASE 0xe0004000 -#define CSR_SDRAM_DFII_CONTROL_ADDR 0xe0004000 -#define CSR_SDRAM_DFII_CONTROL_SIZE 1 -static inline unsigned char sdram_dfii_control_read(void) { - unsigned char r = MMPTR(0xe0004000); - return r; -} -static inline void sdram_dfii_control_write(unsigned char value) { - MMPTR(0xe0004000) = value; -} -#define CSR_SDRAM_DFII_PI0_COMMAND_ADDR 0xe0004004 -#define CSR_SDRAM_DFII_PI0_COMMAND_SIZE 1 -static inline unsigned char sdram_dfii_pi0_command_read(void) { - unsigned char r = MMPTR(0xe0004004); - return r; -} -static inline void sdram_dfii_pi0_command_write(unsigned char value) { - MMPTR(0xe0004004) = value; -} -#define CSR_SDRAM_DFII_PI0_COMMAND_ISSUE_ADDR 0xe0004008 -#define CSR_SDRAM_DFII_PI0_COMMAND_ISSUE_SIZE 1 -static inline unsigned char sdram_dfii_pi0_command_issue_read(void) { - unsigned char r = MMPTR(0xe0004008); - return r; -} -static inline void sdram_dfii_pi0_command_issue_write(unsigned char value) { - MMPTR(0xe0004008) = value; -} -#define CSR_SDRAM_DFII_PI0_ADDRESS_ADDR 0xe000400c -#define CSR_SDRAM_DFII_PI0_ADDRESS_SIZE 2 -static inline unsigned short int sdram_dfii_pi0_address_read(void) { - unsigned short int r = MMPTR(0xe000400c); - r <<= 8; - r |= MMPTR(0xe0004010); - return r; -} -static inline void sdram_dfii_pi0_address_write(unsigned short int value) { - MMPTR(0xe000400c) = value >> 8; - MMPTR(0xe0004010) = value; -} -#define CSR_SDRAM_DFII_PI0_BADDRESS_ADDR 0xe0004014 -#define CSR_SDRAM_DFII_PI0_BADDRESS_SIZE 1 -static inline unsigned char sdram_dfii_pi0_baddress_read(void) { - unsigned char r = MMPTR(0xe0004014); - return r; -} -static inline void sdram_dfii_pi0_baddress_write(unsigned char value) { - MMPTR(0xe0004014) = value; -} -#define CSR_SDRAM_DFII_PI0_WRDATA_ADDR 0xe0004018 -#define CSR_SDRAM_DFII_PI0_WRDATA_SIZE 2 -static inline unsigned short int sdram_dfii_pi0_wrdata_read(void) { - unsigned short int r = MMPTR(0xe0004018); - r <<= 8; - r |= MMPTR(0xe000401c); - return r; -} -static inline void sdram_dfii_pi0_wrdata_write(unsigned short int value) { - MMPTR(0xe0004018) = value >> 8; - MMPTR(0xe000401c) = value; -} -#define CSR_SDRAM_DFII_PI0_RDDATA_ADDR 0xe0004020 -#define CSR_SDRAM_DFII_PI0_RDDATA_SIZE 2 -static inline unsigned short int sdram_dfii_pi0_rddata_read(void) { - unsigned short int r = MMPTR(0xe0004020); - r <<= 8; - r |= MMPTR(0xe0004024); - return r; -} - -/* timer0 */ -#define CSR_TIMER0_BASE 0xe0002000 -#define CSR_TIMER0_LOAD_ADDR 0xe0002000 -#define CSR_TIMER0_LOAD_SIZE 4 -static inline unsigned int timer0_load_read(void) { - unsigned int r = MMPTR(0xe0002000); - r <<= 8; - r |= MMPTR(0xe0002004); - r <<= 8; - r |= MMPTR(0xe0002008); - r <<= 8; - r |= MMPTR(0xe000200c); - return r; -} -static inline void timer0_load_write(unsigned int value) { - MMPTR(0xe0002000) = value >> 24; - MMPTR(0xe0002004) = value >> 16; - MMPTR(0xe0002008) = value >> 8; - MMPTR(0xe000200c) = value; -} -#define CSR_TIMER0_RELOAD_ADDR 0xe0002010 -#define CSR_TIMER0_RELOAD_SIZE 4 -static inline unsigned int timer0_reload_read(void) { - unsigned int r = MMPTR(0xe0002010); - r <<= 8; - r |= MMPTR(0xe0002014); - r <<= 8; - r |= MMPTR(0xe0002018); - r <<= 8; - r |= MMPTR(0xe000201c); - return r; -} -static inline void timer0_reload_write(unsigned int value) { - MMPTR(0xe0002010) = value >> 24; - MMPTR(0xe0002014) = value >> 16; - MMPTR(0xe0002018) = value >> 8; - MMPTR(0xe000201c) = value; -} -#define CSR_TIMER0_EN_ADDR 0xe0002020 -#define CSR_TIMER0_EN_SIZE 1 -static inline unsigned char timer0_en_read(void) { - unsigned char r = MMPTR(0xe0002020); - return r; -} -static inline void timer0_en_write(unsigned char value) { - MMPTR(0xe0002020) = value; -} -#define CSR_TIMER0_UPDATE_VALUE_ADDR 0xe0002024 -#define CSR_TIMER0_UPDATE_VALUE_SIZE 1 -static inline unsigned char timer0_update_value_read(void) { - unsigned char r = MMPTR(0xe0002024); - return r; -} -static inline void timer0_update_value_write(unsigned char value) { - MMPTR(0xe0002024) = value; -} -#define CSR_TIMER0_VALUE_ADDR 0xe0002028 -#define CSR_TIMER0_VALUE_SIZE 4 -static inline unsigned int timer0_value_read(void) { - unsigned int r = MMPTR(0xe0002028); - r <<= 8; - r |= MMPTR(0xe000202c); - r <<= 8; - r |= MMPTR(0xe0002030); - r <<= 8; - r |= MMPTR(0xe0002034); - return r; -} -#define CSR_TIMER0_EV_STATUS_ADDR 0xe0002038 -#define CSR_TIMER0_EV_STATUS_SIZE 1 -static inline unsigned char timer0_ev_status_read(void) { - unsigned char r = MMPTR(0xe0002038); - return r; -} -static inline void timer0_ev_status_write(unsigned char value) { - MMPTR(0xe0002038) = value; -} -#define CSR_TIMER0_EV_PENDING_ADDR 0xe000203c -#define CSR_TIMER0_EV_PENDING_SIZE 1 -static inline unsigned char timer0_ev_pending_read(void) { - unsigned char r = MMPTR(0xe000203c); - return r; -} -static inline void timer0_ev_pending_write(unsigned char value) { - MMPTR(0xe000203c) = value; -} -#define CSR_TIMER0_EV_ENABLE_ADDR 0xe0002040 -#define CSR_TIMER0_EV_ENABLE_SIZE 1 -static inline unsigned char timer0_ev_enable_read(void) { - unsigned char r = MMPTR(0xe0002040); - return r; -} -static inline void timer0_ev_enable_write(unsigned char value) { - MMPTR(0xe0002040) = value; -} - -/* uart */ -#define CSR_UART_BASE 0xe0001000 -#define CSR_UART_RXTX_ADDR 0xe0001000 -#define CSR_UART_RXTX_SIZE 1 -static inline unsigned char uart_rxtx_read(void) { - unsigned char r = MMPTR(0xe0001000); - return r; -} -static inline void uart_rxtx_write(unsigned char value) { - MMPTR(0xe0001000) = value; -} -#define CSR_UART_TXFULL_ADDR 0xe0001004 -#define CSR_UART_TXFULL_SIZE 1 -static inline unsigned char uart_txfull_read(void) { - unsigned char r = MMPTR(0xe0001004); - return r; -} -#define CSR_UART_RXEMPTY_ADDR 0xe0001008 -#define CSR_UART_RXEMPTY_SIZE 1 -static inline unsigned char uart_rxempty_read(void) { - unsigned char r = MMPTR(0xe0001008); - return r; -} -#define CSR_UART_EV_STATUS_ADDR 0xe000100c -#define CSR_UART_EV_STATUS_SIZE 1 -static inline unsigned char uart_ev_status_read(void) { - unsigned char r = MMPTR(0xe000100c); - return r; -} -static inline void uart_ev_status_write(unsigned char value) { - MMPTR(0xe000100c) = value; -} -#define CSR_UART_EV_PENDING_ADDR 0xe0001010 -#define CSR_UART_EV_PENDING_SIZE 1 -static inline unsigned char uart_ev_pending_read(void) { - unsigned char r = MMPTR(0xe0001010); - return r; -} -static inline void uart_ev_pending_write(unsigned char value) { - MMPTR(0xe0001010) = value; -} -#define CSR_UART_EV_ENABLE_ADDR 0xe0001014 -#define CSR_UART_EV_ENABLE_SIZE 1 -static inline unsigned char uart_ev_enable_read(void) { - unsigned char r = MMPTR(0xe0001014); - return r; -} -static inline void uart_ev_enable_write(unsigned char value) { - MMPTR(0xe0001014) = value; -} - -/* uart_phy */ -#define CSR_UART_PHY_BASE 0xe0000800 -#define CSR_UART_PHY_TUNING_WORD_ADDR 0xe0000800 -#define CSR_UART_PHY_TUNING_WORD_SIZE 4 -static inline unsigned int uart_phy_tuning_word_read(void) { - unsigned int r = MMPTR(0xe0000800); - r <<= 8; - r |= MMPTR(0xe0000804); - r <<= 8; - r |= MMPTR(0xe0000808); - r <<= 8; - r |= MMPTR(0xe000080c); - return r; -} -static inline void uart_phy_tuning_word_write(unsigned int value) { - MMPTR(0xe0000800) = value >> 24; - MMPTR(0xe0000804) = value >> 16; - MMPTR(0xe0000808) = value >> 8; - MMPTR(0xe000080c) = value; -} - -/* constants */ -#define UART_INTERRUPT 0 -#define TIMER0_INTERRUPT 1 -#define SYSTEM_CLOCK_FREQUENCY 80000000 -#define L2_SIZE 8192 - -#endif diff --git a/configs/misoc/include/generated/mem.h b/configs/misoc/include/generated/mem.h deleted file mode 100644 index 7b6839d2a9..0000000000 --- a/configs/misoc/include/generated/mem.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef __GENERATED_MEM_H -#define __GENERATED_MEM_H - -#define ROM_BASE 0x00000000 -#define ROM_SIZE 0x00008000 - -#define SRAM_BASE 0x10000000 -#define SRAM_SIZE 0x00001000 - -#define MAIN_RAM_BASE 0x40000000 -#define MAIN_RAM_SIZE 0x00800000 - -#endif diff --git a/configs/misoc/include/generated/output_format.ld b/configs/misoc/include/generated/output_format.ld deleted file mode 100644 index 72acc74d0f..0000000000 --- a/configs/misoc/include/generated/output_format.ld +++ /dev/null @@ -1 +0,0 @@ -OUTPUT_FORMAT("elf32-lm32") diff --git a/configs/misoc/include/generated/regions.ld b/configs/misoc/include/generated/regions.ld deleted file mode 100644 index eb3a45be98..0000000000 --- a/configs/misoc/include/generated/regions.ld +++ /dev/null @@ -1,5 +0,0 @@ -MEMORY { - rom : ORIGIN = 0x00000000, LENGTH = 0x00008000 - sram : ORIGIN = 0x10000000, LENGTH = 0x00001000 - main_ram : ORIGIN = 0x40000000, LENGTH = 0x00800000 -} diff --git a/configs/misoc/include/generated/sdram_phy.h b/configs/misoc/include/generated/sdram_phy.h deleted file mode 100644 index 9fa49eec22..0000000000 --- a/configs/misoc/include/generated/sdram_phy.h +++ /dev/null @@ -1,80 +0,0 @@ -#ifndef __GENERATED_SDRAM_PHY_H -#define __GENERATED_SDRAM_PHY_H -#include -#include -#include - -#define DFII_NPHASES 1 - -static void cdelay(int i); - -static void command_p0(int cmd) -{ - sdram_dfii_pi0_command_write(cmd); - sdram_dfii_pi0_command_issue_write(1); -} - - -#define sdram_dfii_pird_address_write(X) sdram_dfii_pi0_address_write(X) -#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi0_address_write(X) - -#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi0_baddress_write(X) -#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi0_baddress_write(X) - -#define command_prd(X) command_p0(X) -#define command_pwr(X) command_p0(X) - -#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE - -const unsigned int sdram_dfii_pix_wrdata_addr[1] = { - CSR_SDRAM_DFII_PI0_WRDATA_ADDR -}; - -const unsigned int sdram_dfii_pix_rddata_addr[1] = { - CSR_SDRAM_DFII_PI0_RDDATA_ADDR -}; - -static void init_sequence(void) -{ - /* Bring CKE high */ - sdram_dfii_pi0_address_write(0x0); - sdram_dfii_pi0_baddress_write(0); - sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N); - cdelay(20000); - - /* Precharge All */ - sdram_dfii_pi0_address_write(0x400); - sdram_dfii_pi0_baddress_write(0); - command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS); - - /* Load Mode Register / Reset DLL, CL=2, BL=1 */ - sdram_dfii_pi0_address_write(0x120); - sdram_dfii_pi0_baddress_write(0); - command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); - cdelay(200); - - /* Precharge All */ - sdram_dfii_pi0_address_write(0x400); - sdram_dfii_pi0_baddress_write(0); - command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS); - - /* Auto Refresh */ - sdram_dfii_pi0_address_write(0x0); - sdram_dfii_pi0_baddress_write(0); - command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS); - cdelay(4); - - /* Auto Refresh */ - sdram_dfii_pi0_address_write(0x0); - sdram_dfii_pi0_baddress_write(0); - command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS); - cdelay(4); - - /* Load Mode Register / CL=2, BL=1 */ - sdram_dfii_pi0_address_write(0x20); - sdram_dfii_pi0_baddress_write(0); - command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); - cdelay(200); - -} -#endif diff --git a/configs/misoc/include/generated/variables.mak b/configs/misoc/include/generated/variables.mak deleted file mode 100644 index a5e6478ad4..0000000000 --- a/configs/misoc/include/generated/variables.mak +++ /dev/null @@ -1,11 +0,0 @@ -TRIPLE=lm32-elf -CPU=lm32 -CPUFLAGS=-mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled -CPUENDIANNESS=big -CLANG=0 -SOC_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc -BUILDINC_DIRECTORY=/home/lenovo/fpga/litex/litex/boards/targets/soc_basesoc_papilio_pro/software/include -LIBBASE_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/libbase -LIBCOMPILER_RT_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/libcompiler_rt -LIBNET_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/libnet -BIOS_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/bios -- GitLab From 1f9e3ae5f1b4ca690333def3206bb49930969329 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 28 Nov 2016 11:18:07 -0600 Subject: [PATCH 536/734] Misoc LM32: Make naming consistent, lm32_sigdeliver vs. up_sigdeliver. --- arch/misoc/src/lm32/lm32_schedulesigaction.c | 4 ++-- arch/misoc/src/lm32/lm32_sigdeliver.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/misoc/src/lm32/lm32_schedulesigaction.c b/arch/misoc/src/lm32/lm32_schedulesigaction.c index 3b0b395c4a..d72e68cf64 100644 --- a/arch/misoc/src/lm32/lm32_schedulesigaction.c +++ b/arch/misoc/src/lm32/lm32_schedulesigaction.c @@ -154,7 +154,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) * disabled */ - g_current_regs[REG_EPC] = (uint32_t)up_sigdeliver; + g_current_regs[REG_EPC] = (uint32_t)lm32_sigdeliver; g_current_regs[REG_INT_CTX] = 0; @@ -191,7 +191,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) * disabled */ - tcb->xcp.regs[REG_EPC] = (uint32_t)up_sigdeliver; + tcb->xcp.regs[REG_EPC] = (uint32_t)lm32_sigdeliver; tcb->xcp.regs[REG_INT_CTX] = 0; sinfo("PC/STATUS Saved: %08x/%08x New: %08x/%08x\n", diff --git a/arch/misoc/src/lm32/lm32_sigdeliver.c b/arch/misoc/src/lm32/lm32_sigdeliver.c index ce3378e57d..f889691469 100644 --- a/arch/misoc/src/lm32/lm32_sigdeliver.c +++ b/arch/misoc/src/lm32/lm32_sigdeliver.c @@ -59,7 +59,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: up_sigdeliver + * Name: lm32_sigdeliver * * Description: * This is the a signal handling trampoline. When a signal action was @@ -68,7 +68,7 @@ * ****************************************************************************/ -void up_sigdeliver(void) +void lm32_sigdeliver(void) { struct tcb_s *rtcb = this_task(); uint32_t regs[XCPTCONTEXT_REGS]; -- GitLab From a8ea23c59c406e4870cc166965527299be41a025 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 28 Nov 2016 11:22:32 -0600 Subject: [PATCH 537/734] Update README --- configs/misoc/README.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configs/misoc/README.txt b/configs/misoc/README.txt index 2bb07dc699..094ec1acdb 100644 --- a/configs/misoc/README.txt +++ b/configs/misoc/README.txt @@ -63,3 +63,10 @@ Buildroot Toolchain CONFIG_LM3S_TOOLCHAIN_BUILDROOT=y +configs/misoc/include/generated +=============================== + + In order to build this configuration, you must provide this directory. + It contains the generated Misoc files. The base configurtion will NOT + build without this directory! + -- GitLab From d9a041349ec318814ef847727ba70c36c25c8ac0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 28 Nov 2016 12:00:10 -0600 Subject: [PATCH 538/734] Add tools/showsize.sh --- tools/README.txt | 12 +++++++++ tools/showsize.sh | 67 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 79 insertions(+) create mode 100644 tools/showsize.sh diff --git a/tools/README.txt b/tools/README.txt index 1fcac577c1..e8bb6135a3 100644 --- a/tools/README.txt +++ b/tools/README.txt @@ -688,6 +688,18 @@ refresh.sh refresh.sh will prompt you first to avoid overwriting the defconfig file with changes that you may not want. +showsize.sh +----------- + + Show the top 10 biggest memory hogs in code and data spaces. This + must be executed from the top-level NuttX directory like: + + $ tools/showsize.sh + TOP 10 BIG DATA + ... + TOP 10 BIG CODE + ... + testbuild.sh ------------ diff --git a/tools/showsize.sh b/tools/showsize.sh new file mode 100644 index 0000000000..8a8bec7f1e --- /dev/null +++ b/tools/showsize.sh @@ -0,0 +1,67 @@ +#!/bin/bash +############################################################################ +# tools/showsize.sh +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Lorenz Meier +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# set -x + +# Host nm should always work +#NM=arm-none-eabi-nm +NM=nm + +# This should be executed from the top-level NuttX directory + +if [ ! -x "tools/showsize.sh" ]; then + echo "This script must executed from the top-level NuttX directory" + exit 1 +fi + +# On the cywin simulation, the executable will be nuttx.exe + +if [ -f "nuttx" ]; then + NUTTX=nuttx +else + if [ -x "nuttx.exe" ]; then + NUTTX=nuttx.exe + else + echo "Cannot find the NuttX executable" + exit 1 + fi +fi + + +echo "TOP 10 BIG DATA" +$NM --print-size --size-sort --radix dec -C $NUTTX | grep ' [DdBb] ' | tail -20 +echo "TOP 10 BIG CODE" +$NM --print-size --size-sort --radix dec -C $NUTTX | grep ' [TtWw] ' | tail -20 -- GitLab From f9a7898bd4c32d0a7ed458ffd241f5f7674f09a8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 28 Nov 2016 13:24:19 -0600 Subject: [PATCH 539/734] Clean-up some miscellaneous kruft --- configs/misoc/include/.gitignore | 1 + configs/sam4s-xplained-pro/TODO.txt | 56 ----------------------------- tools/showsize.sh | 8 +++-- 3 files changed, 7 insertions(+), 58 deletions(-) create mode 100644 configs/misoc/include/.gitignore delete mode 100644 configs/sam4s-xplained-pro/TODO.txt diff --git a/configs/misoc/include/.gitignore b/configs/misoc/include/.gitignore new file mode 100644 index 0000000000..e324eac91f --- /dev/null +++ b/configs/misoc/include/.gitignore @@ -0,0 +1 @@ +/generated diff --git a/configs/sam4s-xplained-pro/TODO.txt b/configs/sam4s-xplained-pro/TODO.txt deleted file mode 100644 index 5c1a088abd..0000000000 --- a/configs/sam4s-xplained-pro/TODO.txt +++ /dev/null @@ -1,56 +0,0 @@ - - implement flash driver - - see arch/arm/src/stm32/stm32_flash.c and related - - both banks could be mapped with care taken not to erase the active code. - - perhaps the MPU could block code corruption? - - - once implemented, the free() cmd replacement can show flash information. - - - Seen crashes when running serial ports below 921600 - - - COM34 (UART1, ttyS1) runs the smoothest with 'serialblaster' test... - the other two (UART0, USART1) seem to stutter... - - - created a cpuhog test. Each instance takes a semaphore, burns cpu for 6ms and then releases - the sem to exercises semaphores passing and a busy cpu. The first two instances become a - producer/consumer pair using a pipe (FIFO) to exercise the fileio data passing. - -> no crashes with 8 instances running. (No MMU, No BASEPRI) - -> no crashes with 8 instances running. (MMU + BASEPRI) - -> not however that the serial ports are very finicky with BASEPRI enabled! - This setup sends single charactes for each produced or consumed block, - and doesn't seem to have any issues: - NuttShell (NSH) - nsh> cpuhog > /dev/ttyS1 & - cpuhog [5:50] - nsh> cpuhog > /dev/ttyS2 & - cpuhog [7:50] - nsh> cpuhog & - cpuhog [8:50] - nsh> cpuhog 2 - cpuhog & - cpuhog [9:50] - nsh> cpuhog 3 - cpuhog & - cpuhog [10:50] - nsh> cpuhog 4 - cpuhog & - cpuhog [11:50] - nsh> cpuhog 5 - - nsh> cpuhog & - cpuhog [12:50] - nsh> cpuhog 6 - - nsh> cpuhog & - cpuhog [13:50] - nsh> cpuhog 7 - - - USB serial not quite stable when pushing lots of data - - - UARTs don't use DMA. We may need this for high baudrates. - - Inbound hardware flow control requires dma. - -Current Test: - -40mA: 120Mhz (240 MHz PLL) with SDCard mounted, UART0+UART1+USART1 enabled, USB Device availible (but nothing plugged in) -37.8mA: 120Mhz (120 MHz PLL) with SDCard mounted, UART0+UART1+USART1 enabled -16.9mA: "" with WFI added to up_idle() diff --git a/tools/showsize.sh b/tools/showsize.sh index 8a8bec7f1e..ec66d63184 100644 --- a/tools/showsize.sh +++ b/tools/showsize.sh @@ -3,7 +3,8 @@ # tools/showsize.sh # # Copyright (C) 2016 Gregory Nutt. All rights reserved. -# Author: Lorenz Meier +# Author: Lorenz Meier (Original concept) +# Gregory Nutt (This instantiation) # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions @@ -37,7 +38,8 @@ # set -x # Host nm should always work -#NM=arm-none-eabi-nm +# vs. NM=arm-none-eabi-nm + NM=nm # This should be executed from the top-level NuttX directory @@ -60,8 +62,10 @@ else fi fi +# Show what we were asked for echo "TOP 10 BIG DATA" $NM --print-size --size-sort --radix dec -C $NUTTX | grep ' [DdBb] ' | tail -20 + echo "TOP 10 BIG CODE" $NM --print-size --size-sort --radix dec -C $NUTTX | grep ' [TtWw] ' | tail -20 -- GitLab From f3e6264654c110562a981ce5294a9df062104672 Mon Sep 17 00:00:00 2001 From: Ramtin Amin Date: Mon, 28 Nov 2016 13:30:46 -0600 Subject: [PATCH 540/734] configs/misoc: Add a sample directory containing generated sources. This is really only useful for performing test builds. You really must generate the Misoc architecture for a real-life build. --- configs/misoc/README.txt | 13 +- configs/misoc/include/generated-sample/csr.h | 653 ++++++++++++++++++ configs/misoc/include/generated-sample/mem.h | 16 + .../include/generated-sample/output_format.ld | 1 + .../misoc/include/generated-sample/regions.ld | 6 + .../include/generated-sample/sdram_phy.h | 102 +++ .../include/generated-sample/variables.mak | 11 + 7 files changed, 800 insertions(+), 2 deletions(-) create mode 100644 configs/misoc/include/generated-sample/csr.h create mode 100644 configs/misoc/include/generated-sample/mem.h create mode 100644 configs/misoc/include/generated-sample/output_format.ld create mode 100644 configs/misoc/include/generated-sample/regions.ld create mode 100644 configs/misoc/include/generated-sample/sdram_phy.h create mode 100644 configs/misoc/include/generated-sample/variables.mak diff --git a/configs/misoc/README.txt b/configs/misoc/README.txt index 094ec1acdb..a241aba6b6 100644 --- a/configs/misoc/README.txt +++ b/configs/misoc/README.txt @@ -66,7 +66,16 @@ Buildroot Toolchain configs/misoc/include/generated =============================== - In order to build this configuration, you must provide this directory. - It contains the generated Misoc files. The base configurtion will NOT + In order to build this configuration, you must provide the + configs/misoc/include/generated directory. It contains the generated + Misoc files and may be a symbolic link. The base configurtion will NOT build without this directory! + There is a sample generated directory at configs/misoc/include/generated-sample. + If you want to do a test build without generating the architecture, then + you can simply link this sample directory like: + + $ ln -s configs/misoc/include/generated-sample configs/misoc/include/generated + + That should permit a test build. + diff --git a/configs/misoc/include/generated-sample/csr.h b/configs/misoc/include/generated-sample/csr.h new file mode 100644 index 0000000000..e58b0e0bf4 --- /dev/null +++ b/configs/misoc/include/generated-sample/csr.h @@ -0,0 +1,653 @@ +#ifndef __GENERATED_CSR_H +#define __GENERATED_CSR_H +#include + +/* ddrphy */ +#define CSR_DDRPHY_BASE 0xe0008800 +#define CSR_DDRPHY_DLY_SEL_ADDR 0xe0008800 +#define CSR_DDRPHY_DLY_SEL_SIZE 1 +static inline unsigned char ddrphy_dly_sel_read(void) { + unsigned char r = MMPTR(0xe0008800); + return r; +} +static inline void ddrphy_dly_sel_write(unsigned char value) { + MMPTR(0xe0008800) = value; +} +#define CSR_DDRPHY_RDLY_DQ_RST_ADDR 0xe0008804 +#define CSR_DDRPHY_RDLY_DQ_RST_SIZE 1 +static inline unsigned char ddrphy_rdly_dq_rst_read(void) { + unsigned char r = MMPTR(0xe0008804); + return r; +} +static inline void ddrphy_rdly_dq_rst_write(unsigned char value) { + MMPTR(0xe0008804) = value; +} +#define CSR_DDRPHY_RDLY_DQ_INC_ADDR 0xe0008808 +#define CSR_DDRPHY_RDLY_DQ_INC_SIZE 1 +static inline unsigned char ddrphy_rdly_dq_inc_read(void) { + unsigned char r = MMPTR(0xe0008808); + return r; +} +static inline void ddrphy_rdly_dq_inc_write(unsigned char value) { + MMPTR(0xe0008808) = value; +} +#define CSR_DDRPHY_RDLY_DQ_BITSLIP_ADDR 0xe000880c +#define CSR_DDRPHY_RDLY_DQ_BITSLIP_SIZE 1 +static inline unsigned char ddrphy_rdly_dq_bitslip_read(void) { + unsigned char r = MMPTR(0xe000880c); + return r; +} +static inline void ddrphy_rdly_dq_bitslip_write(unsigned char value) { + MMPTR(0xe000880c) = value; +} + +/* ethmac */ +#define CSR_ETHMAC_BASE 0xe000f800 +#define CSR_ETHMAC_SRAM_WRITER_SLOT_ADDR 0xe000f800 +#define CSR_ETHMAC_SRAM_WRITER_SLOT_SIZE 1 +static inline unsigned char ethmac_sram_writer_slot_read(void) { + unsigned char r = MMPTR(0xe000f800); + return r; +} +#define CSR_ETHMAC_SRAM_WRITER_LENGTH_ADDR 0xe000f804 +#define CSR_ETHMAC_SRAM_WRITER_LENGTH_SIZE 4 +static inline unsigned int ethmac_sram_writer_length_read(void) { + unsigned int r = MMPTR(0xe000f804); + r <<= 8; + r |= MMPTR(0xe000f808); + r <<= 8; + r |= MMPTR(0xe000f80c); + r <<= 8; + r |= MMPTR(0xe000f810); + return r; +} +#define CSR_ETHMAC_SRAM_WRITER_EV_STATUS_ADDR 0xe000f814 +#define CSR_ETHMAC_SRAM_WRITER_EV_STATUS_SIZE 1 +static inline unsigned char ethmac_sram_writer_ev_status_read(void) { + unsigned char r = MMPTR(0xe000f814); + return r; +} +static inline void ethmac_sram_writer_ev_status_write(unsigned char value) { + MMPTR(0xe000f814) = value; +} +#define CSR_ETHMAC_SRAM_WRITER_EV_PENDING_ADDR 0xe000f818 +#define CSR_ETHMAC_SRAM_WRITER_EV_PENDING_SIZE 1 +static inline unsigned char ethmac_sram_writer_ev_pending_read(void) { + unsigned char r = MMPTR(0xe000f818); + return r; +} +static inline void ethmac_sram_writer_ev_pending_write(unsigned char value) { + MMPTR(0xe000f818) = value; +} +#define CSR_ETHMAC_SRAM_WRITER_EV_ENABLE_ADDR 0xe000f81c +#define CSR_ETHMAC_SRAM_WRITER_EV_ENABLE_SIZE 1 +static inline unsigned char ethmac_sram_writer_ev_enable_read(void) { + unsigned char r = MMPTR(0xe000f81c); + return r; +} +static inline void ethmac_sram_writer_ev_enable_write(unsigned char value) { + MMPTR(0xe000f81c) = value; +} +#define CSR_ETHMAC_SRAM_READER_START_ADDR 0xe000f820 +#define CSR_ETHMAC_SRAM_READER_START_SIZE 1 +static inline unsigned char ethmac_sram_reader_start_read(void) { + unsigned char r = MMPTR(0xe000f820); + return r; +} +static inline void ethmac_sram_reader_start_write(unsigned char value) { + MMPTR(0xe000f820) = value; +} +#define CSR_ETHMAC_SRAM_READER_READY_ADDR 0xe000f824 +#define CSR_ETHMAC_SRAM_READER_READY_SIZE 1 +static inline unsigned char ethmac_sram_reader_ready_read(void) { + unsigned char r = MMPTR(0xe000f824); + return r; +} +#define CSR_ETHMAC_SRAM_READER_SLOT_ADDR 0xe000f828 +#define CSR_ETHMAC_SRAM_READER_SLOT_SIZE 1 +static inline unsigned char ethmac_sram_reader_slot_read(void) { + unsigned char r = MMPTR(0xe000f828); + return r; +} +static inline void ethmac_sram_reader_slot_write(unsigned char value) { + MMPTR(0xe000f828) = value; +} +#define CSR_ETHMAC_SRAM_READER_LENGTH_ADDR 0xe000f82c +#define CSR_ETHMAC_SRAM_READER_LENGTH_SIZE 2 +static inline unsigned short int ethmac_sram_reader_length_read(void) { + unsigned short int r = MMPTR(0xe000f82c); + r <<= 8; + r |= MMPTR(0xe000f830); + return r; +} +static inline void ethmac_sram_reader_length_write(unsigned short int value) { + MMPTR(0xe000f82c) = value >> 8; + MMPTR(0xe000f830) = value; +} +#define CSR_ETHMAC_SRAM_READER_EV_STATUS_ADDR 0xe000f834 +#define CSR_ETHMAC_SRAM_READER_EV_STATUS_SIZE 1 +static inline unsigned char ethmac_sram_reader_ev_status_read(void) { + unsigned char r = MMPTR(0xe000f834); + return r; +} +static inline void ethmac_sram_reader_ev_status_write(unsigned char value) { + MMPTR(0xe000f834) = value; +} +#define CSR_ETHMAC_SRAM_READER_EV_PENDING_ADDR 0xe000f838 +#define CSR_ETHMAC_SRAM_READER_EV_PENDING_SIZE 1 +static inline unsigned char ethmac_sram_reader_ev_pending_read(void) { + unsigned char r = MMPTR(0xe000f838); + return r; +} +static inline void ethmac_sram_reader_ev_pending_write(unsigned char value) { + MMPTR(0xe000f838) = value; +} +#define CSR_ETHMAC_SRAM_READER_EV_ENABLE_ADDR 0xe000f83c +#define CSR_ETHMAC_SRAM_READER_EV_ENABLE_SIZE 1 +static inline unsigned char ethmac_sram_reader_ev_enable_read(void) { + unsigned char r = MMPTR(0xe000f83c); + return r; +} +static inline void ethmac_sram_reader_ev_enable_write(unsigned char value) { + MMPTR(0xe000f83c) = value; +} +#define CSR_ETHMAC_PREAMBLE_CRC_ADDR 0xe000f840 +#define CSR_ETHMAC_PREAMBLE_CRC_SIZE 1 +static inline unsigned char ethmac_preamble_crc_read(void) { + unsigned char r = MMPTR(0xe000f840); + return r; +} + +/* ethphy */ +#define CSR_ETHPHY_BASE 0xe000f000 +#define CSR_ETHPHY_CRG_RESET_ADDR 0xe000f000 +#define CSR_ETHPHY_CRG_RESET_SIZE 1 +static inline unsigned char ethphy_crg_reset_read(void) { + unsigned char r = MMPTR(0xe000f000); + return r; +} +static inline void ethphy_crg_reset_write(unsigned char value) { + MMPTR(0xe000f000) = value; +} +#define CSR_ETHPHY_MDIO_W_ADDR 0xe000f004 +#define CSR_ETHPHY_MDIO_W_SIZE 1 +static inline unsigned char ethphy_mdio_w_read(void) { + unsigned char r = MMPTR(0xe000f004); + return r; +} +static inline void ethphy_mdio_w_write(unsigned char value) { + MMPTR(0xe000f004) = value; +} +#define CSR_ETHPHY_MDIO_R_ADDR 0xe000f008 +#define CSR_ETHPHY_MDIO_R_SIZE 1 +static inline unsigned char ethphy_mdio_r_read(void) { + unsigned char r = MMPTR(0xe000f008); + return r; +} + +/* sdram */ +#define CSR_SDRAM_BASE 0xe0004000 +#define CSR_SDRAM_DFII_CONTROL_ADDR 0xe0004000 +#define CSR_SDRAM_DFII_CONTROL_SIZE 1 +static inline unsigned char sdram_dfii_control_read(void) { + unsigned char r = MMPTR(0xe0004000); + return r; +} +static inline void sdram_dfii_control_write(unsigned char value) { + MMPTR(0xe0004000) = value; +} +#define CSR_SDRAM_DFII_PI0_COMMAND_ADDR 0xe0004004 +#define CSR_SDRAM_DFII_PI0_COMMAND_SIZE 1 +static inline unsigned char sdram_dfii_pi0_command_read(void) { + unsigned char r = MMPTR(0xe0004004); + return r; +} +static inline void sdram_dfii_pi0_command_write(unsigned char value) { + MMPTR(0xe0004004) = value; +} +#define CSR_SDRAM_DFII_PI0_COMMAND_ISSUE_ADDR 0xe0004008 +#define CSR_SDRAM_DFII_PI0_COMMAND_ISSUE_SIZE 1 +static inline unsigned char sdram_dfii_pi0_command_issue_read(void) { + unsigned char r = MMPTR(0xe0004008); + return r; +} +static inline void sdram_dfii_pi0_command_issue_write(unsigned char value) { + MMPTR(0xe0004008) = value; +} +#define CSR_SDRAM_DFII_PI0_ADDRESS_ADDR 0xe000400c +#define CSR_SDRAM_DFII_PI0_ADDRESS_SIZE 2 +static inline unsigned short int sdram_dfii_pi0_address_read(void) { + unsigned short int r = MMPTR(0xe000400c); + r <<= 8; + r |= MMPTR(0xe0004010); + return r; +} +static inline void sdram_dfii_pi0_address_write(unsigned short int value) { + MMPTR(0xe000400c) = value >> 8; + MMPTR(0xe0004010) = value; +} +#define CSR_SDRAM_DFII_PI0_BADDRESS_ADDR 0xe0004014 +#define CSR_SDRAM_DFII_PI0_BADDRESS_SIZE 1 +static inline unsigned char sdram_dfii_pi0_baddress_read(void) { + unsigned char r = MMPTR(0xe0004014); + return r; +} +static inline void sdram_dfii_pi0_baddress_write(unsigned char value) { + MMPTR(0xe0004014) = value; +} +#define CSR_SDRAM_DFII_PI0_WRDATA_ADDR 0xe0004018 +#define CSR_SDRAM_DFII_PI0_WRDATA_SIZE 4 +static inline unsigned int sdram_dfii_pi0_wrdata_read(void) { + unsigned int r = MMPTR(0xe0004018); + r <<= 8; + r |= MMPTR(0xe000401c); + r <<= 8; + r |= MMPTR(0xe0004020); + r <<= 8; + r |= MMPTR(0xe0004024); + return r; +} +static inline void sdram_dfii_pi0_wrdata_write(unsigned int value) { + MMPTR(0xe0004018) = value >> 24; + MMPTR(0xe000401c) = value >> 16; + MMPTR(0xe0004020) = value >> 8; + MMPTR(0xe0004024) = value; +} +#define CSR_SDRAM_DFII_PI0_RDDATA_ADDR 0xe0004028 +#define CSR_SDRAM_DFII_PI0_RDDATA_SIZE 4 +static inline unsigned int sdram_dfii_pi0_rddata_read(void) { + unsigned int r = MMPTR(0xe0004028); + r <<= 8; + r |= MMPTR(0xe000402c); + r <<= 8; + r |= MMPTR(0xe0004030); + r <<= 8; + r |= MMPTR(0xe0004034); + return r; +} +#define CSR_SDRAM_DFII_PI1_COMMAND_ADDR 0xe0004038 +#define CSR_SDRAM_DFII_PI1_COMMAND_SIZE 1 +static inline unsigned char sdram_dfii_pi1_command_read(void) { + unsigned char r = MMPTR(0xe0004038); + return r; +} +static inline void sdram_dfii_pi1_command_write(unsigned char value) { + MMPTR(0xe0004038) = value; +} +#define CSR_SDRAM_DFII_PI1_COMMAND_ISSUE_ADDR 0xe000403c +#define CSR_SDRAM_DFII_PI1_COMMAND_ISSUE_SIZE 1 +static inline unsigned char sdram_dfii_pi1_command_issue_read(void) { + unsigned char r = MMPTR(0xe000403c); + return r; +} +static inline void sdram_dfii_pi1_command_issue_write(unsigned char value) { + MMPTR(0xe000403c) = value; +} +#define CSR_SDRAM_DFII_PI1_ADDRESS_ADDR 0xe0004040 +#define CSR_SDRAM_DFII_PI1_ADDRESS_SIZE 2 +static inline unsigned short int sdram_dfii_pi1_address_read(void) { + unsigned short int r = MMPTR(0xe0004040); + r <<= 8; + r |= MMPTR(0xe0004044); + return r; +} +static inline void sdram_dfii_pi1_address_write(unsigned short int value) { + MMPTR(0xe0004040) = value >> 8; + MMPTR(0xe0004044) = value; +} +#define CSR_SDRAM_DFII_PI1_BADDRESS_ADDR 0xe0004048 +#define CSR_SDRAM_DFII_PI1_BADDRESS_SIZE 1 +static inline unsigned char sdram_dfii_pi1_baddress_read(void) { + unsigned char r = MMPTR(0xe0004048); + return r; +} +static inline void sdram_dfii_pi1_baddress_write(unsigned char value) { + MMPTR(0xe0004048) = value; +} +#define CSR_SDRAM_DFII_PI1_WRDATA_ADDR 0xe000404c +#define CSR_SDRAM_DFII_PI1_WRDATA_SIZE 4 +static inline unsigned int sdram_dfii_pi1_wrdata_read(void) { + unsigned int r = MMPTR(0xe000404c); + r <<= 8; + r |= MMPTR(0xe0004050); + r <<= 8; + r |= MMPTR(0xe0004054); + r <<= 8; + r |= MMPTR(0xe0004058); + return r; +} +static inline void sdram_dfii_pi1_wrdata_write(unsigned int value) { + MMPTR(0xe000404c) = value >> 24; + MMPTR(0xe0004050) = value >> 16; + MMPTR(0xe0004054) = value >> 8; + MMPTR(0xe0004058) = value; +} +#define CSR_SDRAM_DFII_PI1_RDDATA_ADDR 0xe000405c +#define CSR_SDRAM_DFII_PI1_RDDATA_SIZE 4 +static inline unsigned int sdram_dfii_pi1_rddata_read(void) { + unsigned int r = MMPTR(0xe000405c); + r <<= 8; + r |= MMPTR(0xe0004060); + r <<= 8; + r |= MMPTR(0xe0004064); + r <<= 8; + r |= MMPTR(0xe0004068); + return r; +} +#define CSR_SDRAM_DFII_PI2_COMMAND_ADDR 0xe000406c +#define CSR_SDRAM_DFII_PI2_COMMAND_SIZE 1 +static inline unsigned char sdram_dfii_pi2_command_read(void) { + unsigned char r = MMPTR(0xe000406c); + return r; +} +static inline void sdram_dfii_pi2_command_write(unsigned char value) { + MMPTR(0xe000406c) = value; +} +#define CSR_SDRAM_DFII_PI2_COMMAND_ISSUE_ADDR 0xe0004070 +#define CSR_SDRAM_DFII_PI2_COMMAND_ISSUE_SIZE 1 +static inline unsigned char sdram_dfii_pi2_command_issue_read(void) { + unsigned char r = MMPTR(0xe0004070); + return r; +} +static inline void sdram_dfii_pi2_command_issue_write(unsigned char value) { + MMPTR(0xe0004070) = value; +} +#define CSR_SDRAM_DFII_PI2_ADDRESS_ADDR 0xe0004074 +#define CSR_SDRAM_DFII_PI2_ADDRESS_SIZE 2 +static inline unsigned short int sdram_dfii_pi2_address_read(void) { + unsigned short int r = MMPTR(0xe0004074); + r <<= 8; + r |= MMPTR(0xe0004078); + return r; +} +static inline void sdram_dfii_pi2_address_write(unsigned short int value) { + MMPTR(0xe0004074) = value >> 8; + MMPTR(0xe0004078) = value; +} +#define CSR_SDRAM_DFII_PI2_BADDRESS_ADDR 0xe000407c +#define CSR_SDRAM_DFII_PI2_BADDRESS_SIZE 1 +static inline unsigned char sdram_dfii_pi2_baddress_read(void) { + unsigned char r = MMPTR(0xe000407c); + return r; +} +static inline void sdram_dfii_pi2_baddress_write(unsigned char value) { + MMPTR(0xe000407c) = value; +} +#define CSR_SDRAM_DFII_PI2_WRDATA_ADDR 0xe0004080 +#define CSR_SDRAM_DFII_PI2_WRDATA_SIZE 4 +static inline unsigned int sdram_dfii_pi2_wrdata_read(void) { + unsigned int r = MMPTR(0xe0004080); + r <<= 8; + r |= MMPTR(0xe0004084); + r <<= 8; + r |= MMPTR(0xe0004088); + r <<= 8; + r |= MMPTR(0xe000408c); + return r; +} +static inline void sdram_dfii_pi2_wrdata_write(unsigned int value) { + MMPTR(0xe0004080) = value >> 24; + MMPTR(0xe0004084) = value >> 16; + MMPTR(0xe0004088) = value >> 8; + MMPTR(0xe000408c) = value; +} +#define CSR_SDRAM_DFII_PI2_RDDATA_ADDR 0xe0004090 +#define CSR_SDRAM_DFII_PI2_RDDATA_SIZE 4 +static inline unsigned int sdram_dfii_pi2_rddata_read(void) { + unsigned int r = MMPTR(0xe0004090); + r <<= 8; + r |= MMPTR(0xe0004094); + r <<= 8; + r |= MMPTR(0xe0004098); + r <<= 8; + r |= MMPTR(0xe000409c); + return r; +} +#define CSR_SDRAM_DFII_PI3_COMMAND_ADDR 0xe00040a0 +#define CSR_SDRAM_DFII_PI3_COMMAND_SIZE 1 +static inline unsigned char sdram_dfii_pi3_command_read(void) { + unsigned char r = MMPTR(0xe00040a0); + return r; +} +static inline void sdram_dfii_pi3_command_write(unsigned char value) { + MMPTR(0xe00040a0) = value; +} +#define CSR_SDRAM_DFII_PI3_COMMAND_ISSUE_ADDR 0xe00040a4 +#define CSR_SDRAM_DFII_PI3_COMMAND_ISSUE_SIZE 1 +static inline unsigned char sdram_dfii_pi3_command_issue_read(void) { + unsigned char r = MMPTR(0xe00040a4); + return r; +} +static inline void sdram_dfii_pi3_command_issue_write(unsigned char value) { + MMPTR(0xe00040a4) = value; +} +#define CSR_SDRAM_DFII_PI3_ADDRESS_ADDR 0xe00040a8 +#define CSR_SDRAM_DFII_PI3_ADDRESS_SIZE 2 +static inline unsigned short int sdram_dfii_pi3_address_read(void) { + unsigned short int r = MMPTR(0xe00040a8); + r <<= 8; + r |= MMPTR(0xe00040ac); + return r; +} +static inline void sdram_dfii_pi3_address_write(unsigned short int value) { + MMPTR(0xe00040a8) = value >> 8; + MMPTR(0xe00040ac) = value; +} +#define CSR_SDRAM_DFII_PI3_BADDRESS_ADDR 0xe00040b0 +#define CSR_SDRAM_DFII_PI3_BADDRESS_SIZE 1 +static inline unsigned char sdram_dfii_pi3_baddress_read(void) { + unsigned char r = MMPTR(0xe00040b0); + return r; +} +static inline void sdram_dfii_pi3_baddress_write(unsigned char value) { + MMPTR(0xe00040b0) = value; +} +#define CSR_SDRAM_DFII_PI3_WRDATA_ADDR 0xe00040b4 +#define CSR_SDRAM_DFII_PI3_WRDATA_SIZE 4 +static inline unsigned int sdram_dfii_pi3_wrdata_read(void) { + unsigned int r = MMPTR(0xe00040b4); + r <<= 8; + r |= MMPTR(0xe00040b8); + r <<= 8; + r |= MMPTR(0xe00040bc); + r <<= 8; + r |= MMPTR(0xe00040c0); + return r; +} +static inline void sdram_dfii_pi3_wrdata_write(unsigned int value) { + MMPTR(0xe00040b4) = value >> 24; + MMPTR(0xe00040b8) = value >> 16; + MMPTR(0xe00040bc) = value >> 8; + MMPTR(0xe00040c0) = value; +} +#define CSR_SDRAM_DFII_PI3_RDDATA_ADDR 0xe00040c4 +#define CSR_SDRAM_DFII_PI3_RDDATA_SIZE 4 +static inline unsigned int sdram_dfii_pi3_rddata_read(void) { + unsigned int r = MMPTR(0xe00040c4); + r <<= 8; + r |= MMPTR(0xe00040c8); + r <<= 8; + r |= MMPTR(0xe00040cc); + r <<= 8; + r |= MMPTR(0xe00040d0); + return r; +} + +/* timer0 */ +#define CSR_TIMER0_BASE 0xe0002000 +#define CSR_TIMER0_LOAD_ADDR 0xe0002000 +#define CSR_TIMER0_LOAD_SIZE 4 +static inline unsigned int timer0_load_read(void) { + unsigned int r = MMPTR(0xe0002000); + r <<= 8; + r |= MMPTR(0xe0002004); + r <<= 8; + r |= MMPTR(0xe0002008); + r <<= 8; + r |= MMPTR(0xe000200c); + return r; +} +static inline void timer0_load_write(unsigned int value) { + MMPTR(0xe0002000) = value >> 24; + MMPTR(0xe0002004) = value >> 16; + MMPTR(0xe0002008) = value >> 8; + MMPTR(0xe000200c) = value; +} +#define CSR_TIMER0_RELOAD_ADDR 0xe0002010 +#define CSR_TIMER0_RELOAD_SIZE 4 +static inline unsigned int timer0_reload_read(void) { + unsigned int r = MMPTR(0xe0002010); + r <<= 8; + r |= MMPTR(0xe0002014); + r <<= 8; + r |= MMPTR(0xe0002018); + r <<= 8; + r |= MMPTR(0xe000201c); + return r; +} +static inline void timer0_reload_write(unsigned int value) { + MMPTR(0xe0002010) = value >> 24; + MMPTR(0xe0002014) = value >> 16; + MMPTR(0xe0002018) = value >> 8; + MMPTR(0xe000201c) = value; +} +#define CSR_TIMER0_EN_ADDR 0xe0002020 +#define CSR_TIMER0_EN_SIZE 1 +static inline unsigned char timer0_en_read(void) { + unsigned char r = MMPTR(0xe0002020); + return r; +} +static inline void timer0_en_write(unsigned char value) { + MMPTR(0xe0002020) = value; +} +#define CSR_TIMER0_UPDATE_VALUE_ADDR 0xe0002024 +#define CSR_TIMER0_UPDATE_VALUE_SIZE 1 +static inline unsigned char timer0_update_value_read(void) { + unsigned char r = MMPTR(0xe0002024); + return r; +} +static inline void timer0_update_value_write(unsigned char value) { + MMPTR(0xe0002024) = value; +} +#define CSR_TIMER0_VALUE_ADDR 0xe0002028 +#define CSR_TIMER0_VALUE_SIZE 4 +static inline unsigned int timer0_value_read(void) { + unsigned int r = MMPTR(0xe0002028); + r <<= 8; + r |= MMPTR(0xe000202c); + r <<= 8; + r |= MMPTR(0xe0002030); + r <<= 8; + r |= MMPTR(0xe0002034); + return r; +} +#define CSR_TIMER0_EV_STATUS_ADDR 0xe0002038 +#define CSR_TIMER0_EV_STATUS_SIZE 1 +static inline unsigned char timer0_ev_status_read(void) { + unsigned char r = MMPTR(0xe0002038); + return r; +} +static inline void timer0_ev_status_write(unsigned char value) { + MMPTR(0xe0002038) = value; +} +#define CSR_TIMER0_EV_PENDING_ADDR 0xe000203c +#define CSR_TIMER0_EV_PENDING_SIZE 1 +static inline unsigned char timer0_ev_pending_read(void) { + unsigned char r = MMPTR(0xe000203c); + return r; +} +static inline void timer0_ev_pending_write(unsigned char value) { + MMPTR(0xe000203c) = value; +} +#define CSR_TIMER0_EV_ENABLE_ADDR 0xe0002040 +#define CSR_TIMER0_EV_ENABLE_SIZE 1 +static inline unsigned char timer0_ev_enable_read(void) { + unsigned char r = MMPTR(0xe0002040); + return r; +} +static inline void timer0_ev_enable_write(unsigned char value) { + MMPTR(0xe0002040) = value; +} + +/* uart */ +#define CSR_UART_BASE 0xe0001000 +#define CSR_UART_RXTX_ADDR 0xe0001000 +#define CSR_UART_RXTX_SIZE 1 +static inline unsigned char uart_rxtx_read(void) { + unsigned char r = MMPTR(0xe0001000); + return r; +} +static inline void uart_rxtx_write(unsigned char value) { + MMPTR(0xe0001000) = value; +} +#define CSR_UART_TXFULL_ADDR 0xe0001004 +#define CSR_UART_TXFULL_SIZE 1 +static inline unsigned char uart_txfull_read(void) { + unsigned char r = MMPTR(0xe0001004); + return r; +} +#define CSR_UART_RXEMPTY_ADDR 0xe0001008 +#define CSR_UART_RXEMPTY_SIZE 1 +static inline unsigned char uart_rxempty_read(void) { + unsigned char r = MMPTR(0xe0001008); + return r; +} +#define CSR_UART_EV_STATUS_ADDR 0xe000100c +#define CSR_UART_EV_STATUS_SIZE 1 +static inline unsigned char uart_ev_status_read(void) { + unsigned char r = MMPTR(0xe000100c); + return r; +} +static inline void uart_ev_status_write(unsigned char value) { + MMPTR(0xe000100c) = value; +} +#define CSR_UART_EV_PENDING_ADDR 0xe0001010 +#define CSR_UART_EV_PENDING_SIZE 1 +static inline unsigned char uart_ev_pending_read(void) { + unsigned char r = MMPTR(0xe0001010); + return r; +} +static inline void uart_ev_pending_write(unsigned char value) { + MMPTR(0xe0001010) = value; +} +#define CSR_UART_EV_ENABLE_ADDR 0xe0001014 +#define CSR_UART_EV_ENABLE_SIZE 1 +static inline unsigned char uart_ev_enable_read(void) { + unsigned char r = MMPTR(0xe0001014); + return r; +} +static inline void uart_ev_enable_write(unsigned char value) { + MMPTR(0xe0001014) = value; +} + +/* uart_phy */ +#define CSR_UART_PHY_BASE 0xe0000800 +#define CSR_UART_PHY_TUNING_WORD_ADDR 0xe0000800 +#define CSR_UART_PHY_TUNING_WORD_SIZE 4 +static inline unsigned int uart_phy_tuning_word_read(void) { + unsigned int r = MMPTR(0xe0000800); + r <<= 8; + r |= MMPTR(0xe0000804); + r <<= 8; + r |= MMPTR(0xe0000808); + r <<= 8; + r |= MMPTR(0xe000080c); + return r; +} +static inline void uart_phy_tuning_word_write(unsigned int value) { + MMPTR(0xe0000800) = value >> 24; + MMPTR(0xe0000804) = value >> 16; + MMPTR(0xe0000808) = value >> 8; + MMPTR(0xe000080c) = value; +} + +/* constants */ +#define UART_INTERRUPT 0 +#define TIMER0_INTERRUPT 1 +#define ETHMAC_INTERRUPT 2 +#define SYSTEM_CLOCK_FREQUENCY 100000000 +#define A7DDRPHY_BITSLIP 2 +#define A7DDRPHY_DELAY 6 +#define L2_SIZE 8192 + +#endif diff --git a/configs/misoc/include/generated-sample/mem.h b/configs/misoc/include/generated-sample/mem.h new file mode 100644 index 0000000000..f4a9c9c643 --- /dev/null +++ b/configs/misoc/include/generated-sample/mem.h @@ -0,0 +1,16 @@ +#ifndef __GENERATED_MEM_H +#define __GENERATED_MEM_H + +#define ROM_BASE 0x00000000 +#define ROM_SIZE 0x00008000 + +#define SRAM_BASE 0x10000000 +#define SRAM_SIZE 0x00008000 + +#define MAIN_RAM_BASE 0x40000000 +#define MAIN_RAM_SIZE 0x10000000 + +#define ETHMAC_BASE 0xb0000000 +#define ETHMAC_SIZE 0x00002000 + +#endif diff --git a/configs/misoc/include/generated-sample/output_format.ld b/configs/misoc/include/generated-sample/output_format.ld new file mode 100644 index 0000000000..72acc74d0f --- /dev/null +++ b/configs/misoc/include/generated-sample/output_format.ld @@ -0,0 +1 @@ +OUTPUT_FORMAT("elf32-lm32") diff --git a/configs/misoc/include/generated-sample/regions.ld b/configs/misoc/include/generated-sample/regions.ld new file mode 100644 index 0000000000..1708c3a309 --- /dev/null +++ b/configs/misoc/include/generated-sample/regions.ld @@ -0,0 +1,6 @@ +MEMORY { + rom : ORIGIN = 0x00000000, LENGTH = 0x00008000 + sram : ORIGIN = 0x10000000, LENGTH = 0x00008000 + main_ram : ORIGIN = 0x40000000, LENGTH = 0x10000000 + ethmac : ORIGIN = 0xb0000000, LENGTH = 0x00002000 +} diff --git a/configs/misoc/include/generated-sample/sdram_phy.h b/configs/misoc/include/generated-sample/sdram_phy.h new file mode 100644 index 0000000000..646cf7009a --- /dev/null +++ b/configs/misoc/include/generated-sample/sdram_phy.h @@ -0,0 +1,102 @@ +#ifndef __GENERATED_SDRAM_PHY_H +#define __GENERATED_SDRAM_PHY_H +#include +#include +#include + +#define DFII_NPHASES 4 + +static void cdelay(int i); + +static void command_p0(int cmd) +{ + sdram_dfii_pi0_command_write(cmd); + sdram_dfii_pi0_command_issue_write(1); +} +static void command_p1(int cmd) +{ + sdram_dfii_pi1_command_write(cmd); + sdram_dfii_pi1_command_issue_write(1); +} +static void command_p2(int cmd) +{ + sdram_dfii_pi2_command_write(cmd); + sdram_dfii_pi2_command_issue_write(1); +} +static void command_p3(int cmd) +{ + sdram_dfii_pi3_command_write(cmd); + sdram_dfii_pi3_command_issue_write(1); +} + + +#define sdram_dfii_pird_address_write(X) sdram_dfii_pi0_address_write(X) +#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi2_address_write(X) + +#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi0_baddress_write(X) +#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi2_baddress_write(X) + +#define command_prd(X) command_p0(X) +#define command_pwr(X) command_p2(X) + +#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE + +const unsigned int sdram_dfii_pix_wrdata_addr[4] = { + CSR_SDRAM_DFII_PI0_WRDATA_ADDR, + CSR_SDRAM_DFII_PI1_WRDATA_ADDR, + CSR_SDRAM_DFII_PI2_WRDATA_ADDR, + CSR_SDRAM_DFII_PI3_WRDATA_ADDR +}; + +const unsigned int sdram_dfii_pix_rddata_addr[4] = { + CSR_SDRAM_DFII_PI0_RDDATA_ADDR, + CSR_SDRAM_DFII_PI1_RDDATA_ADDR, + CSR_SDRAM_DFII_PI2_RDDATA_ADDR, + CSR_SDRAM_DFII_PI3_RDDATA_ADDR +}; + +#define DDR3_MR1 6 + +static void init_sequence(void) +{ + /* Release reset */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + sdram_dfii_control_write(DFII_CONTROL_ODT|DFII_CONTROL_RESET_N); + cdelay(50000); + + /* Bring CKE high */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(0); + sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N); + cdelay(10000); + + /* Load Mode Register 2 */ + sdram_dfii_pi0_address_write(0x408); + sdram_dfii_pi0_baddress_write(2); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 3 */ + sdram_dfii_pi0_address_write(0x0); + sdram_dfii_pi0_baddress_write(3); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 1 */ + sdram_dfii_pi0_address_write(0x6); + sdram_dfii_pi0_baddress_write(1); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + + /* Load Mode Register 0, CL=7, BL=8 */ + sdram_dfii_pi0_address_write(0x930); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); + cdelay(200); + + /* ZQ Calibration */ + sdram_dfii_pi0_address_write(0x400); + sdram_dfii_pi0_baddress_write(0); + command_p0(DFII_COMMAND_WE|DFII_COMMAND_CS); + cdelay(200); + +} +#endif diff --git a/configs/misoc/include/generated-sample/variables.mak b/configs/misoc/include/generated-sample/variables.mak new file mode 100644 index 0000000000..2bd0474215 --- /dev/null +++ b/configs/misoc/include/generated-sample/variables.mak @@ -0,0 +1,11 @@ +TRIPLE=lm32-elf +CPU=lm32 +CPUFLAGS=-mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled +CPUENDIANNESS=big +CLANG=0 +SOC_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc +BUILDINC_DIRECTORY=/home/lenovo/fpga/arty-soc/build/software/include +LIBBASE_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/libbase +LIBCOMPILER_RT_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/libcompiler_rt +LIBNET_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/libnet +BIOS_DIRECTORY=/usr/local/lib/python3.5/dist-packages/litex-0.1-py3.5.egg/litex/soc/software/bios -- GitLab From 9ee3f3b93309d355470c3ee8a23ac59c33228864 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 28 Nov 2016 18:36:26 -0600 Subject: [PATCH 541/734] sched_note: Permit spinlock and critical section notes in in-memory buffer iff sched_not_get() interfaces is disabled. --- drivers/syslog/Kconfig | 2 +- include/nuttx/sched_note.h | 10 +++++---- sched/Kconfig | 46 ++++++++++++++++++-------------------- sched/sched/sched_note.c | 4 ++++ 4 files changed, 33 insertions(+), 29 deletions(-) diff --git a/drivers/syslog/Kconfig b/drivers/syslog/Kconfig index dd64edb1e8..eb5b455af6 100644 --- a/drivers/syslog/Kconfig +++ b/drivers/syslog/Kconfig @@ -70,7 +70,7 @@ endif config DRIVER_NOTE bool "Scheduler instrumentation driver" default n - depends on SCHED_INSTRUMENTATION_BUFFER + depends on SCHED_INSTRUMENTATION_BUFFER && SCHED_NOTE_GET ---help--- Enable building a serial driver that can be used by an application to read data from the in-memory, scheduler instrumentation "note" diff --git a/include/nuttx/sched_note.h b/include/nuttx/sched_note.h index 0b19bd2a06..c27e931deb 100644 --- a/include/nuttx/sched_note.h +++ b/include/nuttx/sched_note.h @@ -58,11 +58,11 @@ * old configuration files) */ -#ifdef CONFIG_SCHED_INSTRUMENTATION_CPUSET +#ifndef CONFIG_SCHED_INSTRUMENTATION_CPUSET # define CONFIG_SCHED_INSTRUMENTATION_CPUSET 0xffff #endif -#ifdef CONFIG_SCHED_NOTE_BUFSIZE +#ifndef CONFIG_SCHED_NOTE_BUFSIZE # define CONFIG_SCHED_NOTE_BUFSIZE 2048 #endif @@ -301,7 +301,8 @@ void sched_note_spinabort(FAR struct tcb_s *tcb, FAR volatile void *spinlock); * ****************************************************************************/ -#ifdef CONFIG_SCHED_INSTRUMENTATION_BUFFER +#if defined(CONFIG_SCHED_INSTRUMENTATION_BUFFER) && \ + defined(CONFIG_SCHED_NOTE_GET) ssize_t sched_note_get(FAR uint8_t *buffer, size_t buflen); #endif @@ -320,7 +321,8 @@ ssize_t sched_note_get(FAR uint8_t *buffer, size_t buflen); * ****************************************************************************/ -#ifdef CONFIG_SCHED_INSTRUMENTATION_BUFFER +#if defined(CONFIG_SCHED_INSTRUMENTATION_BUFFER) && \ + defined(CONFIG_SCHED_NOTE_GET) ssize_t sched_note_size(void); #endif diff --git a/sched/Kconfig b/sched/Kconfig index b71e9874fe..4b0e068e6f 100644 --- a/sched/Kconfig +++ b/sched/Kconfig @@ -694,15 +694,9 @@ config SCHED_INSTRUMENTATION_PREEMPTION void sched_note_premption(FAR struct tcb_s *tcb, bool state); -config SCHED_INSTRUMENTATION_FAUXPAS - bool - default y if !EXPERIMENTAL && SCHED_INSTRUMENTATION_BUFFER - default n if EXPERIMENTAL || !SCHED_INSTRUMENTATION_BUFFER - config SCHED_INSTRUMENTATION_CSECTION bool "Critical section monitor hooks" default n - depends on !SCHED_INSTRUMENTATION_FAUXPAS ---help--- Enables additional hooks for entry and exit from critical sections. Interrupts are disabled while within a critical section. Board- @@ -710,18 +704,9 @@ config SCHED_INSTRUMENTATION_CSECTION void sched_note_csection(FAR struct tcb_s *tcb, bool state); - NOTE: This option is marked EXPERIMENTAL because there is a logical - error in the design when this feature is used with - CONFIG_SCHED_INSTRUMENTATION_BUFFER. That error is that - sched_note_get() calls enter_ and leave_critical_section. That - means that each call to sched_note_get() causes two entries to be - added from the note buffer in order to remove one entry. Not - very useful in its current state! - config SCHED_INSTRUMENTATION_SPINLOCK bool "Spinlock monitor hooks" default n - depends on SPINLOCK && (!SMP || !SCHED_INSTRUMENTATION_FAUXPAS) ---help--- Enables additional hooks for spinlock state. Board-specific logic must provide this additional logic. @@ -731,14 +716,6 @@ config SCHED_INSTRUMENTATION_SPINLOCK void sched_note_spinunlock(FAR struct tcb_s *tcb, bool state); void sched_note_spinabort(FAR struct tcb_s *tcb, bool state); - NOTE: This option is marked EXPERIMENTAL because there is a logical - error in the design when this feature is used with - CONFIG_SCHED_INSTRUMENTATION_BUFFER. That error is that - sched_note_get() calls enter_ and leave_critical_section which use - spinlocks in SMP mode. That means that each call to sched_note_get() - causes several additional entries to be added from the note buffer in - order to remove one entry. Not very useful in its current state! - config SCHED_INSTRUMENTATION_BUFFER bool "Buffer instrumentation data in memory" default n @@ -763,14 +740,35 @@ config SCHED_INSTRUMENTATION_BUFFER does not occur. See include/nuttx/sched_note.h for additional information. +if SCHED_INSTRUMENTATION_BUFFER + config SCHED_NOTE_BUFSIZE int "Instrumentation buffer size" default 2048 - depends on SCHED_INSTRUMENTATION_BUFFER ---help--- The size of the in-memory, circular instrumentation buffer (in bytes). +config SCHED_NOTE_GET + int "Callable interface to get instrumentatin data" + default 2048 + depends on !SCHED_INSTRUMENTATION_CSECTION && (!SCHED_INSTRUMENTATION_SPINLOCK || !SMP) + ---help--- + Add support for interfaces to get the size of the next note and also + to extract the next note from the instrumentation buffer: + + ssize_t sched_note_get(FAR uint8_t *buffer, size_t buflen); + ssize_t sched_note_size(void); + + NOTE: This option is not available if critical sections are being + monitor (nor if spinlocks are being monitored in SMP configuration) + because there would be a logical error in the design in those cases. + That error is that these interfaces call enter_ and leave_critical_section + (and which us spinlocks in SMP mode). That means that each call to + sched_note_get() causes several additional entries to be added from + the note buffer in order to remove one entry. + +endif # SCHED_INSTRUMENTATION_BUFFER endif # SCHED_INSTRUMENTATION endmenu # Performance Monitoring diff --git a/sched/sched/sched_note.c b/sched/sched/sched_note.c index 2ad620f416..32b27b4753 100644 --- a/sched/sched/sched_note.c +++ b/sched/sched/sched_note.c @@ -551,6 +551,7 @@ void sched_note_spinabort(FAR struct tcb_s *tcb, FAR volatile void *spinlock); * ****************************************************************************/ +#ifdef CONFIG_SCHED_NOTE_GET ssize_t sched_note_get(FAR uint8_t *buffer, size_t buflen) { FAR struct note_common_s *note; @@ -618,6 +619,7 @@ errout_with_csection: leave_critical_section(flags); return notelen; } +#endif /**************************************************************************** * Name: sched_note_size @@ -634,6 +636,7 @@ errout_with_csection: * ****************************************************************************/ +#ifdef CONFIG_SCHED_NOTE_GET ssize_t sched_note_size(void) { FAR struct note_common_s *note; @@ -668,5 +671,6 @@ errout_with_csection: leave_critical_section(flags); return notelen; } +#endif #endif /* CONFIG_SCHED_INSTRUMENTATION_BUFFER */ -- GitLab From 3f91bd60562bc3eccdbd8d6780b24a4e16bc735d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marc=20Recht=C3=A9?= Date: Tue, 29 Nov 2016 07:03:54 -0600 Subject: [PATCH 542/734] STM32 DAC: Fix shift value whenever there are is a DAC2 and, hence, up to three interfaces. --- arch/arm/src/armv7-a/arm_gicv2.c | 2 +- arch/arm/src/stm32/chip/stm32_dac.h | 76 ++++++++++++++--------------- arch/arm/src/stm32/stm32_dac.c | 15 ++++-- 3 files changed, 51 insertions(+), 42 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_gicv2.c b/arch/arm/src/armv7-a/arm_gicv2.c index 52ca465974..f726214593 100644 --- a/arch/arm/src/armv7-a/arm_gicv2.c +++ b/arch/arm/src/armv7-a/arm_gicv2.c @@ -107,6 +107,7 @@ void arm_gic0_initialize(void) /* Registers with 2-bits per interrupt */ + putreg32(0x5555ffff, GIC_ICDICFR(GIC_IRQ_SGI0)); /* SGIs are edge sensitive */ for (irq = GIC_IRQ_SPI; irq < nlines; irq += 16) { //putreg32(0xffffffff, GIC_ICDICFR(irq)); /* SPIs edge sensitive */ @@ -574,5 +575,4 @@ int arm_gic_irq_trigger(int irq, bool edge) return -EINVAL; } - #endif /* CONFIG_ARMV7A_HAVE_GICv2 */ diff --git a/arch/arm/src/stm32/chip/stm32_dac.h b/arch/arm/src/stm32/chip/stm32_dac.h index 81a69b71e6..61332080ea 100644 --- a/arch/arm/src/stm32/chip/stm32_dac.h +++ b/arch/arm/src/stm32/chip/stm32_dac.h @@ -51,17 +51,17 @@ #define STM32_DAC_CR_OFFSET 0x0000 /* DAC control register */ #define STM32_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */ -#define STM32_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel1 12-bit right-aligned data holding register */ -#define STM32_DAC_DHR12L1_OFFSET 0x000c /* DAC channel1 12-bit left aligned data holding register */ -#define STM32_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel1 8-bit right aligned data holding register */ -#define STM32_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel2 12-bit right aligned data holding register */ -#define STM32_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel2 12-bit left aligned data holding register */ -#define STM32_DAC_DHR8R2_OFFSET 0x001c /* DAC channel2 8-bit right-aligned data holding register */ +#define STM32_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */ +#define STM32_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */ +#define STM32_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */ +#define STM32_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */ #define STM32_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */ #define STM32_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */ #define STM32_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */ -#define STM32_DAC_DOR1_OFFSET 0x002c /* DAC channel1 data output register */ -#define STM32_DAC_DOR2_OFFSET 0x0030 /* DAC channel2 data output register */ +#define STM32_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */ +#define STM32_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */ #define STM32_DAC_SR_OFFSET 0x0034 /* DAC status register */ /* Register Addresses ***************************************************************/ @@ -164,10 +164,10 @@ /* These definitions may be used with the full, 32-bit register */ -#define DAC_CR_EN1 (1 << 0) /* Bit 0: DAC channel1 enable */ -#define DAC_CR_BOFF1 (1 << 1) /* Bit 1: DAC channel1 output buffer disable */ -#define DAC_CR_TEN1 (1 << 2) /* Bit 2: DAC channel1 trigger enable */ -#define DAC_CR_TSEL1_SHIFT (3) /* Bits 3-5: DAC channel1 trigger selection */ +#define DAC_CR_EN1 (1 << 0) /* Bit 0: DAC channel 1 enable */ +#define DAC_CR_BOFF1 (1 << 1) /* Bit 1: DAC channel 1 output buffer disable */ +#define DAC_CR_TEN1 (1 << 2) /* Bit 2: DAC channel 1 trigger enable */ +#define DAC_CR_TSEL1_SHIFT (3) /* Bits 3-5: DAC channel 1 trigger selection */ #define DAC_CR_TSEL1_MASK (7 << DAC_CR_TSEL1_SHIFT) # define DAC_CR_TSEL1_TIM6 (0 << DAC_CR_TSEL1_SHIFT) /* Timer 6 TRGO event */ # define DAC_CR_TSEL1_TIM8 (1 << DAC_CR_TSEL1_SHIFT) /* Timer 8 TRGO event */ @@ -177,12 +177,12 @@ # define DAC_CR_TSEL1_TIM4 (5 << DAC_CR_TSEL1_SHIFT) /* Timer 4 TRGO event */ # define DAC_CR_TSEL1_EXT9 (6 << DAC_CR_TSEL1_SHIFT) /* External line9 */ # define DAC_CR_TSEL1_SW (7 << DAC_CR_TSEL1_SHIFT) /* Software trigger */ -#define DAC_CR_WAVE1_SHIFT (6) /* Bits 6-7: DAC channel1 noise/triangle wave generation */enable +#define DAC_CR_WAVE1_SHIFT (6) /* Bits 6-7: DAC channel 1 noise/triangle wave generation */enable #define DAC_CR_WAVE1_MASK (3 << DAC_CR_WAVE1_SHIFT) # define DAC_CR_WAVE1_DISABLED (0 << DAC_CR_WAVE1_SHIFT) /* Wave generation disabled */ # define DAC_CR_WAVE1_NOISE (1 << DAC_CR_WAVE1_SHIFT) /* Noise wave generation enabled */ # define DAC_CR_WAVE1_TRIANGLE (2 << DAC_CR_WAVE1_SHIFT) /* Triangle wave generation enabled */ -#define DAC_CR_MAMP1_SHIFT (8) /* Bits 8-11: DAC channel1 mask/amplitude selector */ +#define DAC_CR_MAMP1_SHIFT (8) /* Bits 8-11: DAC channel 1 mask/amplitude selector */ #define DAC_CR_MAMP1_MASK (15 << DAC_CR_MAMP1_SHIFT) # define DAC_CR_MAMP1_AMP1 (0 << DAC_CR_MAMP1_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */ # define DAC_CR_MAMP1_AMP3 (1 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[1:0] of LFSR/triangle amplitude=3 */ @@ -196,13 +196,13 @@ # define DAC_CR_MAMP1_AMP1023 (9 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */ # define DAC_CR_MAMP1_AMP2047 (10 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */ # define DAC_CR_MAMP1_AMP4095 (11 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */ -#define DAC_CR_DMAEN1 (1 << 12) /* Bit 12: DAC channel1 DMA enable */ -#define DAC_CR_DMAUDRIE1 (1 << 13) /* Bit 13: DAC channel1 DMA Underrun Interrupt enable */ +#define DAC_CR_DMAEN1 (1 << 12) /* Bit 12: DAC channel 1 DMA enable */ +#define DAC_CR_DMAUDRIE1 (1 << 13) /* Bit 13: DAC channel 1 DMA Underrun Interrupt enable */ -#define DAC_CR_EN2 (1 << 16) /* Bit 16: DAC channel2 enable */ -#define DAC_CR_BOFF2 (1 << 17) /* Bit 17: DAC channel2 output buffer disable */ -#define DAC_CR_TEN2 (1 << 18) /* Bit 18: DAC channel2 trigger enable */ -#define DAC_CR_TSEL2_SHIFT (19) /* Bits 19-21: DAC channel2 trigger selection */ +#define DAC_CR_EN2 (1 << 16) /* Bit 16: DAC channel 2 enable */ +#define DAC_CR_BOFF2 (1 << 17) /* Bit 17: DAC channel 2 output buffer disable */ +#define DAC_CR_TEN2 (1 << 18) /* Bit 18: DAC channel 2 trigger enable */ +#define DAC_CR_TSEL2_SHIFT (19) /* Bits 19-21: DAC channel 2 trigger selection */ #define DAC_CR_TSEL2_MASK (7 << DAC_CR_TSEL2_SHIFT) # define DAC_CR_TSEL2_TIM6 (0 << DAC_CR_TSEL2_SHIFT) /* Timer 6 TRGO event */ # define DAC_CR_TSEL2_TIM8 (1 << DAC_CR_TSEL2_SHIFT) /* Timer 8 TRGO event */ @@ -212,12 +212,12 @@ # define DAC_CR_TSEL2_TIM4 (5 << DAC_CR_TSEL2_SHIFT) /* Timer 4 TRGO event */ # define DAC_CR_TSEL2_EXT9 (6 << DAC_CR_TSEL2_SHIFT) /* External line9 */ # define DAC_CR_TSEL2_SW (7 << DAC_CR_TSEL2_SHIFT) /* Software trigger */ -#define DAC_CR_WAVE2_SHIFT (22) /* Bit 22-23: DAC channel2 noise/triangle wave generation enable */ +#define DAC_CR_WAVE2_SHIFT (22) /* Bit 22-23: DAC channel 2 noise/triangle wave generation enable */ #define DAC_CR_WAVE2_MASK (3 << DAC_CR_WAVE2_SHIFT) # define DAC_CR_WAVE2_DISABLED (0 << DAC_CR_WAVE2_SHIFT) /* Wave generation disabled */ # define DAC_CR_WAVE2_NOISE (1 << DAC_CR_WAVE2_SHIFT) /* Noise wave generation enabled */ # define DAC_CR_WAVE2_TRIANGLE (2 << DAC_CR_WAVE2_SHIFT) /* Triangle wave generation enabled */ -#define DAC_CR_MAMP2_SHIFT (24) /* Bit 24-27: DAC channel2 mask/amplitude selector */ +#define DAC_CR_MAMP2_SHIFT (24) /* Bit 24-27: DAC channel 2 mask/amplitude selector */ #define DAC_CR_MAMP2_MASK (15 << DAC_CR_MAMP2_SHIFT) # define DAC_CR_MAMP2_AMP1 (0 << DAC_CR_MAMP2_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */ # define DAC_CR_MAMP2_AMP3 (1 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[1:0] of LFSR/triangle amplitude=3 */ @@ -231,24 +231,24 @@ # define DAC_CR_MAMP2_AMP1023 (9 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */ # define DAC_CR_MAMP2_AMP2047 (10 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */ # define DAC_CR_MAMP2_AMP4095 (11 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */ -#define DAC_CR_DMAEN2 (1 << 28) /* Bit 28: DAC channel2 DMA enable */ -#define DAC_CR_DMAUDRIE2 (1 << 29) /* Bits 29: DAC channel2 DMA underrun interrupt enable */ +#define DAC_CR_DMAEN2 (1 << 28) /* Bit 28: DAC channel 2 DMA enable */ +#define DAC_CR_DMAUDRIE2 (1 << 29) /* Bits 29: DAC channel 2 DMA underrun interrupt enable */ /* DAC software trigger register */ #define DAC_SWTRIGR_SWTRIG(n) (1 << ((n)-1)) -#define DAC_SWTRIGR_SWTRIG1 (1 << 0) /* Bit 0: DAC channel1 software trigger */ -#define DAC_SWTRIGR_SWTRIG2 (1 << 1) /* Bit 1: DAC channel2 software trigger */ +#define DAC_SWTRIGR_SWTRIG1 (1 << 0) /* Bit 0: DAC channel 1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 (1 << 1) /* Bit 1: DAC channel 2 software trigger */ -/* DAC channel1/2 12-bit right-aligned data holding register */ +/* DAC channel 1/2 12-bit right-aligned data holding register */ #define DAC_DHR12R_MASK (0x0fff) -/* DAC channel1/2 12-bit left aligned data holding register */ +/* DAC channel 1/2 12-bit left aligned data holding register */ #define DAC_DHR12L_MASK (0xfff0) -/* DAC channel1/2 8-bit right aligned data holding register */ +/* DAC channel 1/2 8-bit right aligned data holding register */ #define DAC_DHR8R_MASK (0x00ff) @@ -257,9 +257,9 @@ #define DAC_DHR12RD_DACC_SHIFT(n) (1 << (((n)-1) << 4)) #define DAC_DHR12RD_DACC_MASK(n) (0xfff << DAC_DHR12RD_DACC_SHIFT(n)) -#define DAC_DHR12RD_DACC1_SHIFT (0) /* Bits 0-11: DAC channel1 12-bit right-aligned data */ +#define DAC_DHR12RD_DACC1_SHIFT (0) /* Bits 0-11: DAC channel 1 12-bit right-aligned data */ #define DAC_DHR12RD_DACC1_MASK (0xfff << DAC_DHR12RD_DACC2_SHIFT) -#define DAC_DHR12RD_DACC2_SHIFT (16) /* Bits 16-27: DAC channel2 12-bit right-aligned data */ +#define DAC_DHR12RD_DACC2_SHIFT (16) /* Bits 16-27: DAC channel 2 12-bit right-aligned data */ #define DAC_DHR12RD_DACC2_MASK (0xfff << DAC_DHR12RD_DACC2_SHIFT) /* Dual DAC 12-bit left-aligned data holding register */ @@ -267,9 +267,9 @@ #define DAC_DHR12LD_DACC_SHIFT(n) ((1 << (((n)-1) << 4)) + 4) #define DAC_DHR12LD_DACC_MASK(n) (0xfff << DAC_DHR12LD_DACC_SHIFT(n)) -#define DAC_DHR12LD_DACC1_SHIFT (4) /* Bits 4-15: DAC channel1 12-bit left-aligned data */ +#define DAC_DHR12LD_DACC1_SHIFT (4) /* Bits 4-15: DAC channel 1 12-bit left-aligned data */ #define DAC_DHR12LD_DACC1_MASK (0xfff << DAC_DHR12LD_DACC1_SHIFT) -#define DAC_DHR12LD_DACC2_SHIFT (20) /* Bits 20-31: DAC channel2 12-bit left-aligned data */ +#define DAC_DHR12LD_DACC2_SHIFT (20) /* Bits 20-31: DAC channel 2 12-bit left-aligned data */ #define DAC_DHR12LD_DACC2_MASK (0xfff << DAC_DHR12LD_DACC2_SHIFT) /* DUAL DAC 8-bit right aligned data holding register */ @@ -277,19 +277,19 @@ #define DAC_DHR8RD_DACC_SHIFT(n) (1 << (((n)-1) << 3)) #define DAC_DHR8RD_DACC_MASK(n) (0xff << DAC_DHR8RD_DACC_SHIFT(n)) -#define DAC_DHR8RD_DACC1_SHIFT (0) /* Bits 0-7: DAC channel1 8-bit right-aligned data */ +#define DAC_DHR8RD_DACC1_SHIFT (0) /* Bits 0-7: DAC channel 1 8-bit right-aligned data */ #define DAC_DHR8RD_DACC1_MASK (0xff << DAC_DHR8RD_DACC1_SHIFT) -#define DAC_DHR8RD_DACC2_SHIFT (8) /* Bits 8-15: DAC channel2 8-bit right-aligned data */ +#define DAC_DHR8RD_DACC2_SHIFT (8) /* Bits 8-15: DAC channel 2 8-bit right-aligned data */ #define DAC_DHR8RD_DACC2_MASK (0xff << DAC_DHR8RD_DACC2_SHIFT) -/* DAC channel1/2 data output register */ +/* DAC channel 1/2 data output register */ #define DAC_DOR_MASK (0x0fff) /* DAC status register */ #define DAC_SR_DMAUDR(n) ((1 << (((n)-1) << 4)) + 13) -#define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel1 DMA underrun flag */ -#define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel2 DMA underrun flag */ +#define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */ +#define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */ #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_DAC_H */ diff --git a/arch/arm/src/stm32/stm32_dac.c b/arch/arm/src/stm32/stm32_dac.c index fdcbaf050a..796bb81d21 100644 --- a/arch/arm/src/stm32/stm32_dac.c +++ b/arch/arm/src/stm32/stm32_dac.c @@ -472,7 +472,7 @@ static struct dac_dev_s g_dac2dev = #endif #ifdef CONFIG_STM32_DAC2 -/* Channel 1 */ +/* Channel 3 */ static struct stm32_chan_s g_dac3priv = { @@ -514,9 +514,18 @@ static struct stm32_dac_s g_dacblock; static inline void stm32_dac_modify_cr(FAR struct stm32_chan_s *chan, uint32_t clearbits, uint32_t setbits) { - uint32_t shift; + unsigned int shift; + + /* DAC1 channels 1 and 2 share the STM32_DAC[1]_CR control register. DAC2 + * channel 1 (and perhaps channel 2) uses the STM32_DAC2_CR control + * register. In either case, bit 0 of the interface number provides the + * correct shift. + * + * Bit 0 = 0: Shift = 0 + * Bit 0 = 1: Shift = 16 + */ - shift = chan->intf * 16; + shift = (chan->intf & 1) << 4; modifyreg32(chan->cr, clearbits << shift, setbits << shift); } -- GitLab From a8b69c3efee39321d174dea2dd9c3705dd8cfec8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 29 Nov 2016 07:51:49 -0600 Subject: [PATCH 543/734] Back out a debug change that was included in commit --- arch/arm/src/armv7-a/arm_gicv2.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/src/armv7-a/arm_gicv2.c b/arch/arm/src/armv7-a/arm_gicv2.c index f726214593..dce0b621ed 100644 --- a/arch/arm/src/armv7-a/arm_gicv2.c +++ b/arch/arm/src/armv7-a/arm_gicv2.c @@ -107,7 +107,6 @@ void arm_gic0_initialize(void) /* Registers with 2-bits per interrupt */ - putreg32(0x5555ffff, GIC_ICDICFR(GIC_IRQ_SGI0)); /* SGIs are edge sensitive */ for (irq = GIC_IRQ_SPI; irq < nlines; irq += 16) { //putreg32(0xffffffff, GIC_ICDICFR(irq)); /* SPIs edge sensitive */ -- GitLab From 79bb895073e5351649facd07be1b86690b3e6e60 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 29 Nov 2016 08:34:22 -0600 Subject: [PATCH 544/734] i.MX6: Don't output the alphabet if CONFIG_DEBUG_FEATURES is not set. --- arch/arm/src/armv7-a/arm_cpuhead.S | 2 +- arch/arm/src/imx6/imx_boot.c | 50 ++++++++++++++++++------------ 2 files changed, 31 insertions(+), 21 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_cpuhead.S b/arch/arm/src/armv7-a/arm_cpuhead.S index 2f8387bdcd..02735e36d5 100644 --- a/arch/arm/src/armv7-a/arm_cpuhead.S +++ b/arch/arm/src/armv7-a/arm_cpuhead.S @@ -312,7 +312,7 @@ __cpu3_start: * after SMP cache coherency has been setup. */ -#if !defined(CPU_DCACHE_DISABLE) && !defined(CONFIG_SMP) +#if 0 /* !defined(CPU_DCACHE_DISABLE) && !defined(CONFIG_SMP) */ /* Dcache enable * * SCTLR_C Bit 2: DCache enable diff --git a/arch/arm/src/imx6/imx_boot.c b/arch/arm/src/imx6/imx_boot.c index aaa249e5c0..888baf53ae 100644 --- a/arch/arm/src/imx6/imx_boot.c +++ b/arch/arm/src/imx6/imx_boot.c @@ -65,6 +65,16 @@ #include "imx_serial.h" #include "imx_boot.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +# define PROGRESS(c) imx_lowputc(c) +#else +# define PROGRESS(c) +#endif + /**************************************************************************** * Public Data ****************************************************************************/ @@ -443,7 +453,7 @@ void arm_boot(void) */ imx_setupmappings(); - imx_lowputc('A'); + PROGRESS('A'); /* Make sure that all other CPUs are in the disabled state. This is a * formality because the other CPUs are actually running then we have @@ -451,13 +461,13 @@ void arm_boot(void) */ imx_cpu_disable(); - imx_lowputc('B'); + PROGRESS('B'); #ifdef CONFIG_SMP /* Enable SMP cache coherency for CPU0 */ arm_enable_smp(0); - imx_lowputc('C'); + PROGRESS('C'); #endif /* Provide a special mapping for the OCRAM interrupt vector positioned in @@ -465,7 +475,7 @@ void arm_boot(void) */ imx_vectormapping(); - imx_lowputc('D'); + PROGRESS('D'); #if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) /* Provide a special mapping for the OCRAM interrupt vector positioned in @@ -473,7 +483,7 @@ void arm_boot(void) */ imx_intercpu_mapping(); - imx_lowputc('E'); + PROGRESS('E'); #endif #ifdef CONFIG_ARCH_RAMFUNCS @@ -488,14 +498,14 @@ void arm_boot(void) *dest++ = *src++; } - imx_lowputc('F'); + PROGRESS('F'); /* Flush the copied RAM functions into physical RAM so that will * be available when fetched into the I-Cache. */ arch_clean_dcache((uintptr_t)&_sramfuncs, (uintptr_t)&_eramfuncs) - imx_lowputc('G'); + PROGRESS('G'); #endif /* Setup up vector block. _vector_start and _vector_end are exported from @@ -503,23 +513,23 @@ void arm_boot(void) */ imx_copyvectorblock(); - imx_lowputc('H'); + PROGRESS('H'); /* Disable the watchdog timer */ imx_wdtdisable(); - imx_lowputc('I'); + PROGRESS('I'); /* Initialize clocking to settings provided by board-specific logic */ imx_clockconfig(); - imx_lowputc('J'); + PROGRESS('J'); #ifdef CONFIG_ARCH_FPU /* Initialize the FPU */ arm_fpuconfig(); - imx_lowputc('K'); + PROGRESS('K'); #endif /* Perform board-specific memroy initialization, This must include @@ -531,7 +541,7 @@ void arm_boot(void) */ imx_memory_initialize(); - imx_lowputc('L'); + PROGRESS('L'); #ifdef NEED_SDRAM_REMAPPING /* SDRAM was configured in a temporary state to support low-level @@ -540,7 +550,7 @@ void arm_boot(void) */ imx_remap(); - imx_lowputc('M'); + PROGRESS('M'); #endif #ifdef CONFIG_BOOT_SDRAM_DATA @@ -549,7 +559,7 @@ void arm_boot(void) */ arm_data_initialize(); - imx_lowputc('N'); + PROGRESS('N'); #endif /* Perform board-specific device initialization. This would include @@ -557,7 +567,7 @@ void arm_boot(void) */ imx_board_initialize(); - imx_lowputc('O'); + PROGRESS('O'); #if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) /* Initialize the uncached, inter-CPU communications area */ @@ -567,13 +577,13 @@ void arm_boot(void) *dest++ = 0; } - imx_lowputc('P'); + PROGRESS('P'); #endif /* Perform common, low-level chip initialization (might do nothing) */ imx_lowsetup(); - imx_lowputc('Q'); + PROGRESS('Q'); #ifdef USE_EARLYSERIALINIT /* Perform early serial initialization if we are going to use the serial @@ -581,7 +591,7 @@ void arm_boot(void) */ imx_earlyserialinit(); - imx_lowputc('R'); + PROGRESS('R'); #endif /* Now we can enable all other CPUs. The enabled CPUs will start execution @@ -590,6 +600,6 @@ void arm_boot(void) */ imx_cpu_enable(); - imx_lowputc('S'); - imx_lowputc('\n'); + PROGRESS('S'); + PROGRESS('\n'); } -- GitLab From e400171feb3995aa72e2dcedaa37438acc155e92 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 29 Nov 2016 09:08:15 -0600 Subject: [PATCH 545/734] Update README --- configs/sabre-6quad/README.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/sabre-6quad/README.txt b/configs/sabre-6quad/README.txt index 13584158a5..0de45c795a 100644 --- a/configs/sabre-6quad/README.txt +++ b/configs/sabre-6quad/README.txt @@ -112,6 +112,9 @@ Status CPUs, but I don't think I have that working right yet. See the SMP section below for more information. +2016-11-28: SMP is unusable until the SCU cache coherency logic is fixed. + I do not know how to do that now. + Platform Features ================= -- GitLab From 137586f50a7f28a1a5fe15a2e193d81d8c3bf50b Mon Sep 17 00:00:00 2001 From: Ramtin Amin Date: Tue, 29 Nov 2016 09:09:28 -0600 Subject: [PATCH 546/734] Misoc LM32: Add logic to flush/invalidate caches --- arch/misoc/src/common/misoc.h | 30 +++++++++ arch/misoc/src/common/misoc_flushcache.c | 81 ++++++++++++++++++++++ arch/misoc/src/common/misoc_net.c | 2 +- arch/misoc/src/lm32/Make.defs | 2 + arch/misoc/src/lm32/lm32.h | 5 ++ arch/misoc/src/lm32/lm32_flushcache.c | 86 ++++++++++++++++++++++++ arch/misoc/src/lm32/lm32_initialize.c | 5 ++ 7 files changed, 210 insertions(+), 1 deletion(-) create mode 100644 arch/misoc/src/common/misoc_flushcache.c create mode 100644 arch/misoc/src/lm32/lm32_flushcache.c diff --git a/arch/misoc/src/common/misoc.h b/arch/misoc/src/common/misoc.h index d708e97b48..ab99f6aca2 100644 --- a/arch/misoc/src/common/misoc.h +++ b/arch/misoc/src/common/misoc.h @@ -94,6 +94,16 @@ void flush_cpu_dcache(void); void misoc_serial_initialize(void); +/**************************************************************************** + * Name: up_net_initialize + * + * Description: + * Register Network + * + ****************************************************************************/ + +int misoc_net_initialize(int intf); + /**************************************************************************** * Name: misoc_puts * @@ -136,5 +146,25 @@ void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits); void modifyreg16(unsigned int addr, uint16_t clearbits, uint16_t setbits); void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits); +/**************************************************************************** + * Name: misoc_flush_dcache + * + * Description: + * Flush the data cache of the cpu + * + ****************************************************************************/ + +void misoc_flush_dcache(void); + +/**************************************************************************** + * Name: misoc_flush_icache + * + * Description: + * Flush the instruction cache of the cpu + * + ****************************************************************************/ + +void misoc_flush_icache(void); + #endif /* __ASSEMBLY__ */ #endif /* __ARCH_MISOC_SRC_COMMON_MISOC_H */ diff --git a/arch/misoc/src/common/misoc_flushcache.c b/arch/misoc/src/common/misoc_flushcache.c new file mode 100644 index 0000000000..655ba8ab35 --- /dev/null +++ b/arch/misoc/src/common/misoc_flushcache.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * arch/misoc/src/common/misoc_flushcache.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Author: Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include "misoc.h" + +#ifdef CONFIG_ARCH_CHIP_LM32 +#include "lm32.h" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: misoc_flush_dcache + * + * Description: + * Flush the data cache of the cpu + * + ****************************************************************************/ + +void misoc_flush_dcache() +{ +#ifdef CONFIG_ARCH_CHIP_LM32 + lm32_flush_dcache(); +#endif +} + +/**************************************************************************** + * Name: misoc_flush_icache + * + * Description: + * Flush the instruction cache of the cpu + * + ****************************************************************************/ + +void misoc_flush_icache() +{ +#ifdef CONFIG_ARCH_CHIP_LM32 + lm32_flush_icache(); +#endif +} diff --git a/arch/misoc/src/common/misoc_net.c b/arch/misoc/src/common/misoc_net.c index b758d2d47e..7b4b84c2f0 100644 --- a/arch/misoc/src/common/misoc_net.c +++ b/arch/misoc/src/common/misoc_net.c @@ -391,7 +391,7 @@ static void misoc_net_receive(FAR struct misoc_net_driver_s *priv) * amount of data in priv->misoc_net_dev.d_len */ - flush_cpu_dcache(); + misoc_flush_dcache(); if (rxslot) { diff --git a/arch/misoc/src/lm32/Make.defs b/arch/misoc/src/lm32/Make.defs index 7206117487..a2ea84d61c 100644 --- a/arch/misoc/src/lm32/Make.defs +++ b/arch/misoc/src/lm32/Make.defs @@ -40,6 +40,7 @@ CMN_ASRCS = CMN_CSRCS = misoc_lowputs.c misoc_serial.c misoc_mdelay.c CMN_CSRCS += misoc_modifyreg8.c misoc_modifyreg16.c misoc_modifyreg32.c CMN_CSRCS += misoc_puts.c misoc_udelay.c misoc_timerisr.c misoc_net.c +CMN_CSRCS += misoc_flushcache.c CHIP_ASRCS = lm32_syscall.S @@ -50,3 +51,4 @@ CHIP_CSRCS += lm32_initialize.c lm32_initialstate.c lm32_interruptcontext.c CHIP_CSRCS += lm32_irq.c lm32_releasepending.c lm32_releasestack.c CHIP_CSRCS += lm32_stackframe.c lm32_swint.c lm32_unblocktask.c CHIP_CSRCS += lm32_reprioritizertr.c lm32_schedulesigaction.c lm32_sigdeliver.c +CHIP_CSRCS += lm32_flushcache.c \ No newline at end of file diff --git a/arch/misoc/src/lm32/lm32.h b/arch/misoc/src/lm32/lm32.h index b23e60e4f2..a09bcfec47 100644 --- a/arch/misoc/src/lm32/lm32.h +++ b/arch/misoc/src/lm32/lm32.h @@ -149,6 +149,11 @@ void lm32_timer_initialize(void); void lm32_sigdeliver(void); +/* Cache flushing ***********************************************************/ + +void lm32_flush_dcache(void); +void lm32_flush_icache(void); + /* Debug ********************************************************************/ void lm32_dumpstate(void); diff --git a/arch/misoc/src/lm32/lm32_flushcache.c b/arch/misoc/src/lm32/lm32_flushcache.c new file mode 100644 index 0000000000..8d1d653a6b --- /dev/null +++ b/arch/misoc/src/lm32/lm32_flushcache.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * arch/misoc/src/lm32/lm32_flushcache.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Ramtin Amin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "chip.h" +#include "lm32.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lm32_flush_dcache + * + * Description: + * Flush the data cache of the cpu + * + ****************************************************************************/ + +void lm32_flush_dcache(void) +{ + asm volatile( + "wcsr DCC, r0\n" + "nop\n" + "nop\n" + "nop\n" + "nop\n" + ); +} + +/**************************************************************************** + * Name: lm32_flush_icache + * + * Description: + * Flush the instruction cache of the cpu + * + ****************************************************************************/ + +void lm32_flush_icache(void) +{ + asm volatile( + "wcsr ICC, r0\n" + "nop\n" + "nop\n" + "nop\n" + "nop\n" + ); +} diff --git a/arch/misoc/src/lm32/lm32_initialize.c b/arch/misoc/src/lm32/lm32_initialize.c index dd93cce4b6..1c4323215a 100644 --- a/arch/misoc/src/lm32/lm32_initialize.c +++ b/arch/misoc/src/lm32/lm32_initialize.c @@ -77,4 +77,9 @@ void up_initialize(void) /* Initialize the system timer */ misoc_timer_initialize(); + + /* Initialize the network cores */ + + misoc_net_initialize(0); + } -- GitLab From f06d521c1046628057d8e4e54a0c4f50ab769fbe Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 29 Nov 2016 10:01:38 -0600 Subject: [PATCH 547/734] Minor extensions to some comments --- arch/arm/src/armv7-a/arm_cpupause.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_cpupause.c b/arch/arm/src/armv7-a/arm_cpupause.c index c0751f8ee4..ef324448e2 100644 --- a/arch/arm/src/armv7-a/arm_cpupause.c +++ b/arch/arm/src/armv7-a/arm_cpupause.c @@ -144,13 +144,20 @@ int up_cpu_paused(int cpu) up_savestate(tcb->xcp.regs); - /* Wait for the spinlock to be released */ + /* Release the g_cpu_puased spinlock to synchronize with the + * requesting CPU. + */ spin_unlock(&g_cpu_paused[cpu]); + + /* Wait for the spinlock to be released. The requesting CPU will release + * the spinlcok when the CPU is resumed. + */ + spin_lock(&g_cpu_wait[cpu]); - /* Restore the exception context of the tcb at the (new) head of the - * assigned task list. + /* This CPU has been resumed. Restore the exception context of the TCB at + * the (new) head of the assigned task list. */ tcb = this_task(); -- GitLab From 1793c1f8e17900741af38d25e3d2553c095f2603 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 29 Nov 2016 15:03:51 -0600 Subject: [PATCH 548/734] Trivial, cosmetic change --- drivers/mtd/mtd_partition.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/mtd_partition.c b/drivers/mtd/mtd_partition.c index 8b2f2586fd..655fe36826 100644 --- a/drivers/mtd/mtd_partition.c +++ b/drivers/mtd/mtd_partition.c @@ -900,8 +900,8 @@ FAR struct mtd_dev_s *mtd_partition(FAR struct mtd_dev_s *mtd, off_t firstblock, * Sets the name of the specified partition. * ****************************************************************************/ -#ifdef CONFIG_MTD_PARTITION_NAMES +#ifdef CONFIG_MTD_PARTITION_NAMES int mtd_setpartitionname(FAR struct mtd_dev_s *mtd, FAR const char *name) { FAR struct mtd_partition_s *priv = (FAR struct mtd_partition_s *)mtd; -- GitLab From 44e747ebf12e9d8c6cebd5d889cc9195be42683e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 29 Nov 2016 15:07:30 -0600 Subject: [PATCH 549/734] Remove all references to CONFIG_NET_MULTIBUFFER from configs/ --- configs/c5471evm/httpd/defconfig | 1 - configs/c5471evm/nettest/defconfig | 1 - configs/c5471evm/nsh/defconfig | 1 - configs/cloudctrl/nsh/defconfig | 1 - configs/dk-tm4c129x/README.txt | 1 - configs/dk-tm4c129x/ipv6/defconfig | 1 - configs/dk-tm4c129x/nsh/defconfig | 1 - configs/eagle100/httpd/defconfig | 1 - configs/eagle100/nettest/defconfig | 1 - configs/eagle100/nsh/defconfig | 1 - configs/eagle100/thttpd/defconfig | 1 - configs/ekk-lm3s9b96/nsh/defconfig | 1 - configs/ez80f910200zco/dhcpd/defconfig | 1 - configs/ez80f910200zco/httpd/defconfig | 1 - configs/ez80f910200zco/nettest/defconfig | 1 - configs/ez80f910200zco/nsh/defconfig | 1 - configs/ez80f910200zco/poll/defconfig | 1 - configs/fire-stm32v2/nsh/defconfig | 1 - configs/freedom-k64f/README.txt | 1 - configs/freedom-k64f/netnsh/defconfig | 1 - configs/lincoln60/netnsh/defconfig | 1 - configs/lincoln60/thttpd-binfs/defconfig | 1 - configs/lm3s6432-s2e/nsh/defconfig | 1 - configs/lm3s6965-ek/discover/defconfig | 1 - configs/lm3s6965-ek/nsh/defconfig | 1 - configs/lm3s6965-ek/tcpecho/defconfig | 1 - configs/lm3s8962-ek/nsh/defconfig | 1 - configs/lpcxpresso-lpc1768/dhcpd/defconfig | 1 - configs/lpcxpresso-lpc1768/nsh/defconfig | 1 - configs/lpcxpresso-lpc1768/thttpd/defconfig | 1 - configs/misoc/hello/defconfig | 1 - configs/moxa/nsh/defconfig | 1 - configs/ntosd-dm320/nettest/defconfig | 1 - configs/ntosd-dm320/nsh/defconfig | 1 - configs/ntosd-dm320/poll/defconfig | 1 - configs/ntosd-dm320/thttpd/defconfig | 1 - configs/ntosd-dm320/udp/defconfig | 1 - configs/ntosd-dm320/webserver/defconfig | 1 - configs/olimex-lpc1766stk/ftpc/defconfig | 1 - configs/olimex-lpc1766stk/hidmouse/defconfig | 1 - configs/olimex-lpc1766stk/nettest/defconfig | 1 - configs/olimex-lpc1766stk/nsh/defconfig | 1 - configs/olimex-lpc1766stk/slip-httpd/defconfig | 1 - configs/olimex-lpc1766stk/thttpd-binfs/defconfig | 1 - configs/olimex-lpc1766stk/thttpd-nxflat/defconfig | 1 - configs/olimex-lpc1766stk/zmodem/defconfig | 1 - configs/olimex-stm32-e407/discover/defconfig | 1 - configs/olimex-stm32-e407/netnsh/defconfig | 1 - configs/olimex-stm32-e407/telnetd/defconfig | 1 - configs/olimex-stm32-e407/webserver/defconfig | 1 - configs/olimex-stm32-p107/nsh/defconfig | 1 - configs/olimex-stm32-p207/nsh/defconfig | 1 - configs/olimex-strp711/nettest/defconfig | 1 - configs/pic32mx-starterkit/nsh2/defconfig | 1 - configs/pic32mx7mmb/nsh/defconfig | 1 - configs/rgmp/arm/default/defconfig | 1 - configs/rgmp/arm/nsh/defconfig | 1 - configs/rgmp/x86/cxxtest/defconfig | 1 - configs/rgmp/x86/default/defconfig | 1 - configs/rgmp/x86/helloxx/defconfig | 1 - configs/rgmp/x86/nsh/defconfig | 1 - configs/sam4e-ek/nsh/defconfig | 1 - configs/sam4e-ek/nxwm/defconfig | 1 - configs/sam4e-ek/usbnsh/defconfig | 1 - configs/sama5d3-xplained/bridge/defconfig | 1 - configs/sama5d4-ek/bridge/defconfig | 1 - configs/sama5d4-ek/ipv6/defconfig | 1 - configs/sama5d4-ek/nsh/defconfig | 1 - configs/sama5d4-ek/nxwm/defconfig | 1 - configs/same70-xplained/netnsh/defconfig | 1 - configs/samv71-xult/netnsh/defconfig | 1 - configs/samv71-xult/vnc/defconfig | 1 - configs/samv71-xult/vnxwm/defconfig | 1 - configs/shenzhou/nsh/defconfig | 1 - configs/shenzhou/nxwm/defconfig | 1 - configs/shenzhou/thttpd/defconfig | 1 - configs/sim/nettest/defconfig | 1 - configs/sim/udgram/defconfig | 1 - configs/sim/ustream/defconfig | 1 - configs/stm3220g-eval/dhcpd/defconfig | 1 - configs/stm3220g-eval/nettest/defconfig | 1 - configs/stm3220g-eval/nsh/defconfig | 1 - configs/stm3220g-eval/nsh2/defconfig | 1 - configs/stm3220g-eval/nxwm/defconfig | 1 - configs/stm3220g-eval/telnetd/defconfig | 1 - configs/stm3240g-eval/dhcpd/defconfig | 1 - configs/stm3240g-eval/discover/defconfig | 1 - configs/stm3240g-eval/nettest/defconfig | 1 - configs/stm3240g-eval/nsh/defconfig | 1 - configs/stm3240g-eval/nsh2/defconfig | 1 - configs/stm3240g-eval/nxterm/defconfig | 1 - configs/stm3240g-eval/nxwm/defconfig | 1 - configs/stm3240g-eval/telnetd/defconfig | 1 - configs/stm3240g-eval/webserver/defconfig | 1 - configs/stm3240g-eval/xmlrpc/defconfig | 1 - configs/stm32butterfly2/nshnet/defconfig | 1 - configs/stm32f4discovery/ipv6/defconfig | 1 - configs/stm32f4discovery/netnsh/defconfig | 1 - configs/tm4c1294-launchpad/ipv6/defconfig | 1 - configs/tm4c1294-launchpad/nsh/defconfig | 1 - configs/u-blox-c027/nsh/defconfig | 1 - configs/viewtool-stm32f107/README.txt | 1 - configs/viewtool-stm32f107/netnsh/defconfig | 1 - configs/zkit-arm-1769/hello/defconfig | 1 - configs/zkit-arm-1769/nsh/defconfig | 1 - configs/zkit-arm-1769/nxhello/defconfig | 1 - configs/zkit-arm-1769/thttpd/defconfig | 1 - 107 files changed, 107 deletions(-) diff --git a/configs/c5471evm/httpd/defconfig b/configs/c5471evm/httpd/defconfig index 4d735ee6e2..197f6d6bbb 100644 --- a/configs/c5471evm/httpd/defconfig +++ b/configs/c5471evm/httpd/defconfig @@ -478,7 +478,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/c5471evm/nettest/defconfig b/configs/c5471evm/nettest/defconfig index e16e805626..9aaf151900 100644 --- a/configs/c5471evm/nettest/defconfig +++ b/configs/c5471evm/nettest/defconfig @@ -471,7 +471,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/c5471evm/nsh/defconfig b/configs/c5471evm/nsh/defconfig index e61a16c8f1..9fbc29ae44 100644 --- a/configs/c5471evm/nsh/defconfig +++ b/configs/c5471evm/nsh/defconfig @@ -479,7 +479,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/cloudctrl/nsh/defconfig b/configs/cloudctrl/nsh/defconfig index 2b7a000923..63379c76a0 100644 --- a/configs/cloudctrl/nsh/defconfig +++ b/configs/cloudctrl/nsh/defconfig @@ -923,7 +923,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/dk-tm4c129x/README.txt b/configs/dk-tm4c129x/README.txt index 138e69cd3e..3ef95b3e26 100644 --- a/configs/dk-tm4c129x/README.txt +++ b/configs/dk-tm4c129x/README.txt @@ -228,7 +228,6 @@ Networking Support CONFIG_NET_ETHERNET=y : Support Ethernet data link CONFIG_NET_NOINTS=y : Should operative at non-interrupt level CONFIG_NET_SOCKOPTS=y : Enable socket operations - CONFIG_NET_MULTIBUFFER=y : Multi-packet buffer option required CONFIG_NET_ETH_MTU=590 : Maximum packet size (MTU) 1518 is more standard CONFIG_NET_ETH_TCP_RECVWNDO=536 : Should be the same as CONFIG_NET_ETH_MTU CONFIG_NET_ARP=y : Enable ARP diff --git a/configs/dk-tm4c129x/ipv6/defconfig b/configs/dk-tm4c129x/ipv6/defconfig index 040b6d517a..952adc9bee 100644 --- a/configs/dk-tm4c129x/ipv6/defconfig +++ b/configs/dk-tm4c129x/ipv6/defconfig @@ -684,7 +684,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/dk-tm4c129x/nsh/defconfig b/configs/dk-tm4c129x/nsh/defconfig index b871146318..cad9ba2649 100644 --- a/configs/dk-tm4c129x/nsh/defconfig +++ b/configs/dk-tm4c129x/nsh/defconfig @@ -686,7 +686,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/eagle100/httpd/defconfig b/configs/eagle100/httpd/defconfig index 9705928334..4197c688be 100644 --- a/configs/eagle100/httpd/defconfig +++ b/configs/eagle100/httpd/defconfig @@ -612,7 +612,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/eagle100/nettest/defconfig b/configs/eagle100/nettest/defconfig index 5d908c3893..82e1dbef79 100644 --- a/configs/eagle100/nettest/defconfig +++ b/configs/eagle100/nettest/defconfig @@ -604,7 +604,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/eagle100/nsh/defconfig b/configs/eagle100/nsh/defconfig index 3551825edb..7ba5c5680a 100644 --- a/configs/eagle100/nsh/defconfig +++ b/configs/eagle100/nsh/defconfig @@ -646,7 +646,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/eagle100/thttpd/defconfig b/configs/eagle100/thttpd/defconfig index 7b2287eaf1..d6f0e3c105 100644 --- a/configs/eagle100/thttpd/defconfig +++ b/configs/eagle100/thttpd/defconfig @@ -600,7 +600,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/ekk-lm3s9b96/nsh/defconfig b/configs/ekk-lm3s9b96/nsh/defconfig index d1f6d9bf57..51ecd48309 100644 --- a/configs/ekk-lm3s9b96/nsh/defconfig +++ b/configs/ekk-lm3s9b96/nsh/defconfig @@ -635,7 +635,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/ez80f910200zco/dhcpd/defconfig b/configs/ez80f910200zco/dhcpd/defconfig index 9a740baa64..8e770fe3e1 100644 --- a/configs/ez80f910200zco/dhcpd/defconfig +++ b/configs/ez80f910200zco/dhcpd/defconfig @@ -503,7 +503,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/ez80f910200zco/httpd/defconfig b/configs/ez80f910200zco/httpd/defconfig index 60fb2abeb9..be2280a06e 100644 --- a/configs/ez80f910200zco/httpd/defconfig +++ b/configs/ez80f910200zco/httpd/defconfig @@ -512,7 +512,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/ez80f910200zco/nettest/defconfig b/configs/ez80f910200zco/nettest/defconfig index 446c99cbb8..94d96ff873 100644 --- a/configs/ez80f910200zco/nettest/defconfig +++ b/configs/ez80f910200zco/nettest/defconfig @@ -504,7 +504,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/ez80f910200zco/nsh/defconfig b/configs/ez80f910200zco/nsh/defconfig index 20c5d5e5e4..c1f233c2e8 100644 --- a/configs/ez80f910200zco/nsh/defconfig +++ b/configs/ez80f910200zco/nsh/defconfig @@ -515,7 +515,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/ez80f910200zco/poll/defconfig b/configs/ez80f910200zco/poll/defconfig index 3a6fea2c6c..8c68f8d21f 100644 --- a/configs/ez80f910200zco/poll/defconfig +++ b/configs/ez80f910200zco/poll/defconfig @@ -514,7 +514,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/fire-stm32v2/nsh/defconfig b/configs/fire-stm32v2/nsh/defconfig index 56b6462675..9b1ccf2ba9 100644 --- a/configs/fire-stm32v2/nsh/defconfig +++ b/configs/fire-stm32v2/nsh/defconfig @@ -979,7 +979,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/freedom-k64f/README.txt b/configs/freedom-k64f/README.txt index 2c6666a7e6..4dd8932aad 100644 --- a/configs/freedom-k64f/README.txt +++ b/configs/freedom-k64f/README.txt @@ -195,7 +195,6 @@ Networking Support CONFIG_NET_ETHERNET=y : Support Ethernet data link CONFIG_NET_NOINTS=y : Should operative at non-interrupt level CONFIG_NET_SOCKOPTS=y : Enable socket operations - CONFIG_NET_MULTIBUFFER=y : Multi-packet buffer option required CONFIG_NET_ETH_MTU=590 : Maximum packet size (MTU) 1518 is more standard CONFIG_NET_ETH_TCP_RECVWNDO=536 : Should be the same as CONFIG_NET_ETH_MTU CONFIG_NET_ARP=y : Enable ARP diff --git a/configs/freedom-k64f/netnsh/defconfig b/configs/freedom-k64f/netnsh/defconfig index 7303dda872..f45f051dee 100644 --- a/configs/freedom-k64f/netnsh/defconfig +++ b/configs/freedom-k64f/netnsh/defconfig @@ -652,7 +652,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/lincoln60/netnsh/defconfig b/configs/lincoln60/netnsh/defconfig index 6875687ca8..e0d78b0c5a 100644 --- a/configs/lincoln60/netnsh/defconfig +++ b/configs/lincoln60/netnsh/defconfig @@ -631,7 +631,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/lincoln60/thttpd-binfs/defconfig b/configs/lincoln60/thttpd-binfs/defconfig index 4d54e20560..6c6c6e7cde 100644 --- a/configs/lincoln60/thttpd-binfs/defconfig +++ b/configs/lincoln60/thttpd-binfs/defconfig @@ -610,7 +610,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/lm3s6432-s2e/nsh/defconfig b/configs/lm3s6432-s2e/nsh/defconfig index 16f56238ee..59ae704707 100644 --- a/configs/lm3s6432-s2e/nsh/defconfig +++ b/configs/lm3s6432-s2e/nsh/defconfig @@ -626,7 +626,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/lm3s6965-ek/discover/defconfig b/configs/lm3s6965-ek/discover/defconfig index 6604cf2e5c..16a2eda7cf 100644 --- a/configs/lm3s6965-ek/discover/defconfig +++ b/configs/lm3s6965-ek/discover/defconfig @@ -640,7 +640,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/lm3s6965-ek/nsh/defconfig b/configs/lm3s6965-ek/nsh/defconfig index 6604cf2e5c..16a2eda7cf 100644 --- a/configs/lm3s6965-ek/nsh/defconfig +++ b/configs/lm3s6965-ek/nsh/defconfig @@ -640,7 +640,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/lm3s6965-ek/tcpecho/defconfig b/configs/lm3s6965-ek/tcpecho/defconfig index 69824a4a7c..7cffb832e4 100644 --- a/configs/lm3s6965-ek/tcpecho/defconfig +++ b/configs/lm3s6965-ek/tcpecho/defconfig @@ -610,7 +610,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=650 CONFIG_NET_ETH_TCP_RECVWNDO=624 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/lm3s8962-ek/nsh/defconfig b/configs/lm3s8962-ek/nsh/defconfig index d4c79ab20e..dc3cf532f4 100644 --- a/configs/lm3s8962-ek/nsh/defconfig +++ b/configs/lm3s8962-ek/nsh/defconfig @@ -650,7 +650,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/lpcxpresso-lpc1768/dhcpd/defconfig b/configs/lpcxpresso-lpc1768/dhcpd/defconfig index da0cb8af8c..62bd8b1a9c 100644 --- a/configs/lpcxpresso-lpc1768/dhcpd/defconfig +++ b/configs/lpcxpresso-lpc1768/dhcpd/defconfig @@ -599,7 +599,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/lpcxpresso-lpc1768/nsh/defconfig b/configs/lpcxpresso-lpc1768/nsh/defconfig index 1cf8e78fbb..ad8650d32d 100644 --- a/configs/lpcxpresso-lpc1768/nsh/defconfig +++ b/configs/lpcxpresso-lpc1768/nsh/defconfig @@ -671,7 +671,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/lpcxpresso-lpc1768/thttpd/defconfig b/configs/lpcxpresso-lpc1768/thttpd/defconfig index d227462fbf..8eb4af45ec 100644 --- a/configs/lpcxpresso-lpc1768/thttpd/defconfig +++ b/configs/lpcxpresso-lpc1768/thttpd/defconfig @@ -602,7 +602,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/misoc/hello/defconfig b/configs/misoc/hello/defconfig index d18aef2c75..cb7733b1bc 100644 --- a/configs/misoc/hello/defconfig +++ b/configs/misoc/hello/defconfig @@ -489,7 +489,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=1400 CONFIG_NET_ETH_TCP_RECVWNDO=742 CONFIG_NET_GUARDSIZE=648 diff --git a/configs/moxa/nsh/defconfig b/configs/moxa/nsh/defconfig index 3b7043c04e..a19e3b2c00 100644 --- a/configs/moxa/nsh/defconfig +++ b/configs/moxa/nsh/defconfig @@ -522,7 +522,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=1500 CONFIG_NET_ETH_TCP_RECVWNDO=1536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/ntosd-dm320/nettest/defconfig b/configs/ntosd-dm320/nettest/defconfig index a9ee527115..9aeb9e39de 100644 --- a/configs/ntosd-dm320/nettest/defconfig +++ b/configs/ntosd-dm320/nettest/defconfig @@ -512,7 +512,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/ntosd-dm320/nsh/defconfig b/configs/ntosd-dm320/nsh/defconfig index 845e806b36..2bac5f0e14 100644 --- a/configs/ntosd-dm320/nsh/defconfig +++ b/configs/ntosd-dm320/nsh/defconfig @@ -528,7 +528,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/ntosd-dm320/poll/defconfig b/configs/ntosd-dm320/poll/defconfig index 5b357b8182..989cc95a86 100644 --- a/configs/ntosd-dm320/poll/defconfig +++ b/configs/ntosd-dm320/poll/defconfig @@ -523,7 +523,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/ntosd-dm320/thttpd/defconfig b/configs/ntosd-dm320/thttpd/defconfig index 991f4c1875..19f0d460ed 100644 --- a/configs/ntosd-dm320/thttpd/defconfig +++ b/configs/ntosd-dm320/thttpd/defconfig @@ -516,7 +516,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/ntosd-dm320/udp/defconfig b/configs/ntosd-dm320/udp/defconfig index 6fe1d2e373..fece989f14 100644 --- a/configs/ntosd-dm320/udp/defconfig +++ b/configs/ntosd-dm320/udp/defconfig @@ -511,7 +511,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/ntosd-dm320/webserver/defconfig b/configs/ntosd-dm320/webserver/defconfig index 789fc76a73..5306d32dc3 100644 --- a/configs/ntosd-dm320/webserver/defconfig +++ b/configs/ntosd-dm320/webserver/defconfig @@ -519,7 +519,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/olimex-lpc1766stk/ftpc/defconfig b/configs/olimex-lpc1766stk/ftpc/defconfig index bae7aac56b..634f5d31df 100644 --- a/configs/olimex-lpc1766stk/ftpc/defconfig +++ b/configs/olimex-lpc1766stk/ftpc/defconfig @@ -638,7 +638,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=550 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/olimex-lpc1766stk/hidmouse/defconfig b/configs/olimex-lpc1766stk/hidmouse/defconfig index 31bc863951..f3a3822ef0 100644 --- a/configs/olimex-lpc1766stk/hidmouse/defconfig +++ b/configs/olimex-lpc1766stk/hidmouse/defconfig @@ -627,7 +627,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/olimex-lpc1766stk/nettest/defconfig b/configs/olimex-lpc1766stk/nettest/defconfig index 2b676ed872..819f8f8b13 100644 --- a/configs/olimex-lpc1766stk/nettest/defconfig +++ b/configs/olimex-lpc1766stk/nettest/defconfig @@ -600,7 +600,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/olimex-lpc1766stk/nsh/defconfig b/configs/olimex-lpc1766stk/nsh/defconfig index 1a67e4f8a6..55059b6518 100644 --- a/configs/olimex-lpc1766stk/nsh/defconfig +++ b/configs/olimex-lpc1766stk/nsh/defconfig @@ -640,7 +640,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/olimex-lpc1766stk/slip-httpd/defconfig b/configs/olimex-lpc1766stk/slip-httpd/defconfig index 006083964e..ef787d52d5 100644 --- a/configs/olimex-lpc1766stk/slip-httpd/defconfig +++ b/configs/olimex-lpc1766stk/slip-httpd/defconfig @@ -565,7 +565,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_SLIP_MTU=296 CONFIG_NET_SLIP_TCP_RECVWNDO=256 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/olimex-lpc1766stk/thttpd-binfs/defconfig b/configs/olimex-lpc1766stk/thttpd-binfs/defconfig index cb2b172f2b..ab5d46e64e 100644 --- a/configs/olimex-lpc1766stk/thttpd-binfs/defconfig +++ b/configs/olimex-lpc1766stk/thttpd-binfs/defconfig @@ -610,7 +610,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig b/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig index e82d0807e5..d68223b384 100644 --- a/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig +++ b/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig @@ -603,7 +603,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/olimex-lpc1766stk/zmodem/defconfig b/configs/olimex-lpc1766stk/zmodem/defconfig index 4540805469..52f165b294 100644 --- a/configs/olimex-lpc1766stk/zmodem/defconfig +++ b/configs/olimex-lpc1766stk/zmodem/defconfig @@ -655,7 +655,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/olimex-stm32-e407/discover/defconfig b/configs/olimex-stm32-e407/discover/defconfig index adb8afe01b..5e8aa59403 100644 --- a/configs/olimex-stm32-e407/discover/defconfig +++ b/configs/olimex-stm32-e407/discover/defconfig @@ -905,7 +905,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/olimex-stm32-e407/netnsh/defconfig b/configs/olimex-stm32-e407/netnsh/defconfig index c09c158e18..3bbf977266 100644 --- a/configs/olimex-stm32-e407/netnsh/defconfig +++ b/configs/olimex-stm32-e407/netnsh/defconfig @@ -907,7 +907,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/olimex-stm32-e407/telnetd/defconfig b/configs/olimex-stm32-e407/telnetd/defconfig index a20c3d7cd6..5b82f366ab 100644 --- a/configs/olimex-stm32-e407/telnetd/defconfig +++ b/configs/olimex-stm32-e407/telnetd/defconfig @@ -907,7 +907,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/olimex-stm32-e407/webserver/defconfig b/configs/olimex-stm32-e407/webserver/defconfig index 124c1c88f9..270c5dbb68 100644 --- a/configs/olimex-stm32-e407/webserver/defconfig +++ b/configs/olimex-stm32-e407/webserver/defconfig @@ -905,7 +905,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/olimex-stm32-p107/nsh/defconfig b/configs/olimex-stm32-p107/nsh/defconfig index 210607d988..e6cc90b04e 100644 --- a/configs/olimex-stm32-p107/nsh/defconfig +++ b/configs/olimex-stm32-p107/nsh/defconfig @@ -913,7 +913,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=650 CONFIG_NET_ETH_TCP_RECVWNDO=624 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/olimex-stm32-p207/nsh/defconfig b/configs/olimex-stm32-p207/nsh/defconfig index 2c60b36650..cc63f3004c 100644 --- a/configs/olimex-stm32-p207/nsh/defconfig +++ b/configs/olimex-stm32-p207/nsh/defconfig @@ -957,7 +957,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/olimex-strp711/nettest/defconfig b/configs/olimex-strp711/nettest/defconfig index 05e90b4d78..2a07f8e2d5 100644 --- a/configs/olimex-strp711/nettest/defconfig +++ b/configs/olimex-strp711/nettest/defconfig @@ -559,7 +559,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/pic32mx-starterkit/nsh2/defconfig b/configs/pic32mx-starterkit/nsh2/defconfig index ec259a462b..145509449d 100644 --- a/configs/pic32mx-starterkit/nsh2/defconfig +++ b/configs/pic32mx-starterkit/nsh2/defconfig @@ -676,7 +676,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/pic32mx7mmb/nsh/defconfig b/configs/pic32mx7mmb/nsh/defconfig index 716e0a9e8b..b535ae2d10 100644 --- a/configs/pic32mx7mmb/nsh/defconfig +++ b/configs/pic32mx7mmb/nsh/defconfig @@ -739,7 +739,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/rgmp/arm/default/defconfig b/configs/rgmp/arm/default/defconfig index d5234fe746..a05a9676fa 100644 --- a/configs/rgmp/arm/default/defconfig +++ b/configs/rgmp/arm/default/defconfig @@ -293,7 +293,6 @@ CONFIG_ARCH_HAVE_NET=y CONFIG_NET=y # CONFIG_NET_NOINTS is not set CONFIG_NET_IPv4=y -# CONFIG_NET_MULTIBUFFER is not set # CONFIG_NET_PROMISCUOUS is not set CONFIG_NSOCKET_DESCRIPTORS=5 CONFIG_NET_NACTIVESOCKETS=16 diff --git a/configs/rgmp/arm/nsh/defconfig b/configs/rgmp/arm/nsh/defconfig index 0d907f5dcc..32b04bda7e 100644 --- a/configs/rgmp/arm/nsh/defconfig +++ b/configs/rgmp/arm/nsh/defconfig @@ -315,7 +315,6 @@ CONFIG_ARCH_HAVE_NET=y CONFIG_NET=y # CONFIG_NET_NOINTS is not set CONFIG_NET_IPv4=y -# CONFIG_NET_MULTIBUFFER is not set # CONFIG_NET_PROMISCUOUS is not set CONFIG_NSOCKET_DESCRIPTORS=5 CONFIG_NET_NACTIVESOCKETS=16 diff --git a/configs/rgmp/x86/cxxtest/defconfig b/configs/rgmp/x86/cxxtest/defconfig index f103710ecf..acfbeeedef 100644 --- a/configs/rgmp/x86/cxxtest/defconfig +++ b/configs/rgmp/x86/cxxtest/defconfig @@ -322,7 +322,6 @@ CONFIG_ARCH_HAVE_NET=y CONFIG_NET=y # CONFIG_NET_NOINTS is not set CONFIG_NET_IPv4=y -# CONFIG_NET_MULTIBUFFER is not set # CONFIG_NET_PROMISCUOUS is not set CONFIG_NSOCKET_DESCRIPTORS=5 CONFIG_NET_NACTIVESOCKETS=16 diff --git a/configs/rgmp/x86/default/defconfig b/configs/rgmp/x86/default/defconfig index ac4dc3c632..7eef1813ab 100644 --- a/configs/rgmp/x86/default/defconfig +++ b/configs/rgmp/x86/default/defconfig @@ -301,7 +301,6 @@ CONFIG_ARCH_HAVE_NET=y CONFIG_NET=y # CONFIG_NET_NOINTS is not set CONFIG_NET_IPv4=y -# CONFIG_NET_MULTIBUFFER is not set # CONFIG_NET_PROMISCUOUS is not set CONFIG_NSOCKET_DESCRIPTORS=5 CONFIG_NET_NACTIVESOCKETS=16 diff --git a/configs/rgmp/x86/helloxx/defconfig b/configs/rgmp/x86/helloxx/defconfig index f911ae8c27..3ac271a21a 100644 --- a/configs/rgmp/x86/helloxx/defconfig +++ b/configs/rgmp/x86/helloxx/defconfig @@ -322,7 +322,6 @@ CONFIG_ARCH_HAVE_NET=y CONFIG_NET=y # CONFIG_NET_NOINTS is not set CONFIG_NET_IPv4=y -# CONFIG_NET_MULTIBUFFER is not set # CONFIG_NET_PROMISCUOUS is not set CONFIG_NSOCKET_DESCRIPTORS=5 CONFIG_NET_NACTIVESOCKETS=16 diff --git a/configs/rgmp/x86/nsh/defconfig b/configs/rgmp/x86/nsh/defconfig index 73534eae29..4eac635072 100644 --- a/configs/rgmp/x86/nsh/defconfig +++ b/configs/rgmp/x86/nsh/defconfig @@ -323,7 +323,6 @@ CONFIG_ARCH_HAVE_NET=y CONFIG_NET=y # CONFIG_NET_NOINTS is not set CONFIG_NET_IPv4=y -# CONFIG_NET_MULTIBUFFER is not set # CONFIG_NET_PROMISCUOUS is not set CONFIG_NSOCKET_DESCRIPTORS=5 CONFIG_NET_NACTIVESOCKETS=16 diff --git a/configs/sam4e-ek/nsh/defconfig b/configs/sam4e-ek/nsh/defconfig index 2ef13dd91f..b2241a1f87 100644 --- a/configs/sam4e-ek/nsh/defconfig +++ b/configs/sam4e-ek/nsh/defconfig @@ -744,7 +744,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/sam4e-ek/nxwm/defconfig b/configs/sam4e-ek/nxwm/defconfig index e0f08e426d..06934765a9 100644 --- a/configs/sam4e-ek/nxwm/defconfig +++ b/configs/sam4e-ek/nxwm/defconfig @@ -803,7 +803,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/sam4e-ek/usbnsh/defconfig b/configs/sam4e-ek/usbnsh/defconfig index 79c11c7385..8b9b010f16 100644 --- a/configs/sam4e-ek/usbnsh/defconfig +++ b/configs/sam4e-ek/usbnsh/defconfig @@ -784,7 +784,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/sama5d3-xplained/bridge/defconfig b/configs/sama5d3-xplained/bridge/defconfig index fe883173cf..4ece1c8211 100644 --- a/configs/sama5d3-xplained/bridge/defconfig +++ b/configs/sama5d3-xplained/bridge/defconfig @@ -700,7 +700,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/sama5d4-ek/bridge/defconfig b/configs/sama5d4-ek/bridge/defconfig index 2fe78fac24..c71740cad7 100644 --- a/configs/sama5d4-ek/bridge/defconfig +++ b/configs/sama5d4-ek/bridge/defconfig @@ -733,7 +733,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/sama5d4-ek/ipv6/defconfig b/configs/sama5d4-ek/ipv6/defconfig index dc12843886..d6f8a5d621 100644 --- a/configs/sama5d4-ek/ipv6/defconfig +++ b/configs/sama5d4-ek/ipv6/defconfig @@ -916,7 +916,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=562 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/sama5d4-ek/nsh/defconfig b/configs/sama5d4-ek/nsh/defconfig index 6e39bfc312..9df9e8592b 100644 --- a/configs/sama5d4-ek/nsh/defconfig +++ b/configs/sama5d4-ek/nsh/defconfig @@ -918,7 +918,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=562 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/sama5d4-ek/nxwm/defconfig b/configs/sama5d4-ek/nxwm/defconfig index 491f250f7b..c3f7f7e16a 100644 --- a/configs/sama5d4-ek/nxwm/defconfig +++ b/configs/sama5d4-ek/nxwm/defconfig @@ -887,7 +887,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=562 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/same70-xplained/netnsh/defconfig b/configs/same70-xplained/netnsh/defconfig index 1313e21cb9..535c3c9683 100644 --- a/configs/same70-xplained/netnsh/defconfig +++ b/configs/same70-xplained/netnsh/defconfig @@ -776,7 +776,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/samv71-xult/netnsh/defconfig b/configs/samv71-xult/netnsh/defconfig index 54877ac7e1..6ccda62f81 100644 --- a/configs/samv71-xult/netnsh/defconfig +++ b/configs/samv71-xult/netnsh/defconfig @@ -779,7 +779,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/samv71-xult/vnc/defconfig b/configs/samv71-xult/vnc/defconfig index 2e7a83721c..ff8aa31f6c 100644 --- a/configs/samv71-xult/vnc/defconfig +++ b/configs/samv71-xult/vnc/defconfig @@ -780,7 +780,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/samv71-xult/vnxwm/defconfig b/configs/samv71-xult/vnxwm/defconfig index af19392428..9ad4941d6e 100644 --- a/configs/samv71-xult/vnxwm/defconfig +++ b/configs/samv71-xult/vnxwm/defconfig @@ -783,7 +783,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/shenzhou/nsh/defconfig b/configs/shenzhou/nsh/defconfig index 1e440b536d..9d0efc7d8a 100644 --- a/configs/shenzhou/nsh/defconfig +++ b/configs/shenzhou/nsh/defconfig @@ -908,7 +908,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/shenzhou/nxwm/defconfig b/configs/shenzhou/nxwm/defconfig index c785575fd7..b486a69964 100644 --- a/configs/shenzhou/nxwm/defconfig +++ b/configs/shenzhou/nxwm/defconfig @@ -976,7 +976,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/shenzhou/thttpd/defconfig b/configs/shenzhou/thttpd/defconfig index d5f58ab0b0..8df46c0006 100644 --- a/configs/shenzhou/thttpd/defconfig +++ b/configs/shenzhou/thttpd/defconfig @@ -939,7 +939,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=768 CONFIG_NET_ETH_TCP_RECVWNDO=742 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/sim/nettest/defconfig b/configs/sim/nettest/defconfig index 2cd4f87f85..ccab175375 100644 --- a/configs/sim/nettest/defconfig +++ b/configs/sim/nettest/defconfig @@ -395,7 +395,6 @@ CONFIG_NET=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/sim/udgram/defconfig b/configs/sim/udgram/defconfig index fa768fa7c2..567b3165e2 100644 --- a/configs/sim/udgram/defconfig +++ b/configs/sim/udgram/defconfig @@ -409,7 +409,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_GUARDSIZE=2 # diff --git a/configs/sim/ustream/defconfig b/configs/sim/ustream/defconfig index 0e9b3b7e70..ed8cdd5ea2 100644 --- a/configs/sim/ustream/defconfig +++ b/configs/sim/ustream/defconfig @@ -409,7 +409,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_GUARDSIZE=2 # diff --git a/configs/stm3220g-eval/dhcpd/defconfig b/configs/stm3220g-eval/dhcpd/defconfig index b574b0fde2..50faf0a0c0 100644 --- a/configs/stm3220g-eval/dhcpd/defconfig +++ b/configs/stm3220g-eval/dhcpd/defconfig @@ -880,7 +880,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/stm3220g-eval/nettest/defconfig b/configs/stm3220g-eval/nettest/defconfig index ad9239d239..e97e8b01d3 100644 --- a/configs/stm3220g-eval/nettest/defconfig +++ b/configs/stm3220g-eval/nettest/defconfig @@ -880,7 +880,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/stm3220g-eval/nsh/defconfig b/configs/stm3220g-eval/nsh/defconfig index dcda247266..2b16a40723 100644 --- a/configs/stm3220g-eval/nsh/defconfig +++ b/configs/stm3220g-eval/nsh/defconfig @@ -947,7 +947,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/stm3220g-eval/nsh2/defconfig b/configs/stm3220g-eval/nsh2/defconfig index 923e1dbda1..ab552f7ae1 100644 --- a/configs/stm3220g-eval/nsh2/defconfig +++ b/configs/stm3220g-eval/nsh2/defconfig @@ -948,7 +948,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/stm3220g-eval/nxwm/defconfig b/configs/stm3220g-eval/nxwm/defconfig index 9ddc3d2f30..c1097ac55b 100644 --- a/configs/stm3220g-eval/nxwm/defconfig +++ b/configs/stm3220g-eval/nxwm/defconfig @@ -997,7 +997,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/stm3220g-eval/telnetd/defconfig b/configs/stm3220g-eval/telnetd/defconfig index 2bb72cf565..5875d4530b 100644 --- a/configs/stm3220g-eval/telnetd/defconfig +++ b/configs/stm3220g-eval/telnetd/defconfig @@ -882,7 +882,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/stm3240g-eval/dhcpd/defconfig b/configs/stm3240g-eval/dhcpd/defconfig index 091fc95372..754c19b28b 100644 --- a/configs/stm3240g-eval/dhcpd/defconfig +++ b/configs/stm3240g-eval/dhcpd/defconfig @@ -884,7 +884,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/stm3240g-eval/discover/defconfig b/configs/stm3240g-eval/discover/defconfig index 22b2acdc04..9690dcd899 100644 --- a/configs/stm3240g-eval/discover/defconfig +++ b/configs/stm3240g-eval/discover/defconfig @@ -907,7 +907,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=650 CONFIG_NET_ETH_TCP_RECVWNDO=624 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/stm3240g-eval/nettest/defconfig b/configs/stm3240g-eval/nettest/defconfig index 12c440b624..17b71623d7 100644 --- a/configs/stm3240g-eval/nettest/defconfig +++ b/configs/stm3240g-eval/nettest/defconfig @@ -884,7 +884,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/stm3240g-eval/nsh/defconfig b/configs/stm3240g-eval/nsh/defconfig index d4d84d24c2..3c3ea36359 100644 --- a/configs/stm3240g-eval/nsh/defconfig +++ b/configs/stm3240g-eval/nsh/defconfig @@ -925,7 +925,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/stm3240g-eval/nsh2/defconfig b/configs/stm3240g-eval/nsh2/defconfig index 64d4a78045..eee3754ec5 100644 --- a/configs/stm3240g-eval/nsh2/defconfig +++ b/configs/stm3240g-eval/nsh2/defconfig @@ -952,7 +952,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/stm3240g-eval/nxterm/defconfig b/configs/stm3240g-eval/nxterm/defconfig index 4226d88dc0..3acf60bb0b 100644 --- a/configs/stm3240g-eval/nxterm/defconfig +++ b/configs/stm3240g-eval/nxterm/defconfig @@ -959,7 +959,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/stm3240g-eval/nxwm/defconfig b/configs/stm3240g-eval/nxwm/defconfig index 5b3f4a223d..d84d697338 100644 --- a/configs/stm3240g-eval/nxwm/defconfig +++ b/configs/stm3240g-eval/nxwm/defconfig @@ -994,7 +994,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/stm3240g-eval/telnetd/defconfig b/configs/stm3240g-eval/telnetd/defconfig index abdbc56841..0fda97b4ad 100644 --- a/configs/stm3240g-eval/telnetd/defconfig +++ b/configs/stm3240g-eval/telnetd/defconfig @@ -886,7 +886,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/stm3240g-eval/webserver/defconfig b/configs/stm3240g-eval/webserver/defconfig index 31a294000e..4c8e72621a 100644 --- a/configs/stm3240g-eval/webserver/defconfig +++ b/configs/stm3240g-eval/webserver/defconfig @@ -946,7 +946,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/stm3240g-eval/xmlrpc/defconfig b/configs/stm3240g-eval/xmlrpc/defconfig index 84f733db93..43dfd2fbf0 100644 --- a/configs/stm3240g-eval/xmlrpc/defconfig +++ b/configs/stm3240g-eval/xmlrpc/defconfig @@ -903,7 +903,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=650 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/stm32butterfly2/nshnet/defconfig b/configs/stm32butterfly2/nshnet/defconfig index 41bdf15b31..950212cb7b 100644 --- a/configs/stm32butterfly2/nshnet/defconfig +++ b/configs/stm32butterfly2/nshnet/defconfig @@ -950,7 +950,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=1500 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/stm32f4discovery/ipv6/defconfig b/configs/stm32f4discovery/ipv6/defconfig index 9a828de914..fb6ce75801 100644 --- a/configs/stm32f4discovery/ipv6/defconfig +++ b/configs/stm32f4discovery/ipv6/defconfig @@ -954,7 +954,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/stm32f4discovery/netnsh/defconfig b/configs/stm32f4discovery/netnsh/defconfig index 61d4db2c5b..30eb7b69cf 100644 --- a/configs/stm32f4discovery/netnsh/defconfig +++ b/configs/stm32f4discovery/netnsh/defconfig @@ -956,7 +956,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/tm4c1294-launchpad/ipv6/defconfig b/configs/tm4c1294-launchpad/ipv6/defconfig index 25fc93d965..392efcf409 100644 --- a/configs/tm4c1294-launchpad/ipv6/defconfig +++ b/configs/tm4c1294-launchpad/ipv6/defconfig @@ -648,7 +648,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/tm4c1294-launchpad/nsh/defconfig b/configs/tm4c1294-launchpad/nsh/defconfig index 922fe3c678..1d098acb40 100644 --- a/configs/tm4c1294-launchpad/nsh/defconfig +++ b/configs/tm4c1294-launchpad/nsh/defconfig @@ -650,7 +650,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/u-blox-c027/nsh/defconfig b/configs/u-blox-c027/nsh/defconfig index 7f9acf9aff..74c243de7c 100644 --- a/configs/u-blox-c027/nsh/defconfig +++ b/configs/u-blox-c027/nsh/defconfig @@ -687,7 +687,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/viewtool-stm32f107/README.txt b/configs/viewtool-stm32f107/README.txt index e84f13aec0..04ff1afbb2 100644 --- a/configs/viewtool-stm32f107/README.txt +++ b/configs/viewtool-stm32f107/README.txt @@ -365,7 +365,6 @@ ViewTool DP83848 Ethernet Module Networking (required) CONFIG_NET=y : Enabled networking support - CONFIG_NET_MULTIBUFFER=y : Required by driver CONFIG_NSH_NOMAC=y Networking (recommended/typical) diff --git a/configs/viewtool-stm32f107/netnsh/defconfig b/configs/viewtool-stm32f107/netnsh/defconfig index 3da3e1b85b..f3d75c91ae 100644 --- a/configs/viewtool-stm32f107/netnsh/defconfig +++ b/configs/viewtool-stm32f107/netnsh/defconfig @@ -882,7 +882,6 @@ CONFIG_NET=y # # Driver buffer configuration # -CONFIG_NET_MULTIBUFFER=y CONFIG_NET_ETH_MTU=650 CONFIG_NET_ETH_TCP_RECVWNDO=624 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/zkit-arm-1769/hello/defconfig b/configs/zkit-arm-1769/hello/defconfig index d509b93944..2817bc0674 100644 --- a/configs/zkit-arm-1769/hello/defconfig +++ b/configs/zkit-arm-1769/hello/defconfig @@ -600,7 +600,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/zkit-arm-1769/nsh/defconfig b/configs/zkit-arm-1769/nsh/defconfig index 4e3b92cbb2..40b204fa69 100644 --- a/configs/zkit-arm-1769/nsh/defconfig +++ b/configs/zkit-arm-1769/nsh/defconfig @@ -640,7 +640,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/zkit-arm-1769/nxhello/defconfig b/configs/zkit-arm-1769/nxhello/defconfig index a969f3a503..ae2a05a5d3 100644 --- a/configs/zkit-arm-1769/nxhello/defconfig +++ b/configs/zkit-arm-1769/nxhello/defconfig @@ -678,7 +678,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 diff --git a/configs/zkit-arm-1769/thttpd/defconfig b/configs/zkit-arm-1769/thttpd/defconfig index d385519e2c..691a9323ef 100644 --- a/configs/zkit-arm-1769/thttpd/defconfig +++ b/configs/zkit-arm-1769/thttpd/defconfig @@ -603,7 +603,6 @@ CONFIG_NET_NOINTS=y # # Driver buffer configuration # -# CONFIG_NET_MULTIBUFFER is not set CONFIG_NET_ETH_MTU=590 CONFIG_NET_ETH_TCP_RECVWNDO=536 CONFIG_NET_GUARDSIZE=2 -- GitLab From 934aded293ff058e6cdf04a7f16772aa49af1631 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 29 Nov 2016 16:06:48 -0600 Subject: [PATCH 550/734] arch/: Adapt all Ethernet drivers to work as though CONFIG_NET_MULTIBUFFER were set. Remove all references to CONFIG_NET_MULTIBUFFER --- arch/arm/src/c5471/c5471_ethernet.c | 5 +++++ arch/arm/src/kinetis/Kconfig | 1 - arch/arm/src/kinetis/kinetis_enet.c | 4 ---- arch/arm/src/lpc17xx/lpc17_ethernet.c | 15 ++++++++++++++- arch/arm/src/lpc43xx/lpc43_ethernet.c | 6 ------ arch/arm/src/sam34/sam_emac.c | 4 ---- arch/arm/src/sama5/sam_emaca.c | 4 ---- arch/arm/src/sama5/sam_emacb.c | 14 -------------- arch/arm/src/sama5/sam_gmac.c | 4 ---- arch/arm/src/samv7/sam_emac.c | 14 -------------- arch/arm/src/stm32/stm32_eth.c | 6 ------ arch/arm/src/stm32f7/stm32_ethernet.c | 6 ------ arch/arm/src/tiva/lm3s_ethernet.c | 4 ---- arch/arm/src/tiva/tm4c_ethernet.c | 4 ---- arch/hc/src/m9s12/m9s12_ethernet.c | 13 ++++++++++--- arch/mips/src/pic32mx/pic32mx-ethernet.c | 6 ------ arch/mips/src/pic32mz/pic32mz-ethernet.c | 6 ------ arch/misoc/src/common/misoc_net.c | 7 +++++++ arch/sim/src/up_netdriver.c | 12 ++++++++---- arch/z80/src/ez80/ez80_emac.c | 7 ++++++- 20 files changed, 50 insertions(+), 92 deletions(-) diff --git a/arch/arm/src/c5471/c5471_ethernet.c b/arch/arm/src/c5471/c5471_ethernet.c index b7563aa054..62fe06eb0f 100644 --- a/arch/arm/src/c5471/c5471_ethernet.c +++ b/arch/arm/src/c5471/c5471_ethernet.c @@ -279,6 +279,10 @@ * Private Types ****************************************************************************/ +/* A single packet buffer is used */ + +static uint8_t g_pktbuf[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE]; + /* The c5471_driver_s encapsulates all state information for a single c5471 * hardware interface */ @@ -2248,6 +2252,7 @@ void up_netinitialize(void) /* Initialize the driver structure */ memset(g_c5471, 0, CONFIG_C5471_NET_NINTERFACES*sizeof(struct c5471_driver_s)); + g_c5471[0].c_dev.d_buf = g_pktbuf; /* Single packet buffer */ g_c5471[0].c_dev.d_ifup = c5471_ifup; /* I/F down callback */ g_c5471[0].c_dev.d_ifdown = c5471_ifdown; /* I/F up (new IP address) callback */ g_c5471[0].c_dev.d_txavail = c5471_txavail; /* New TX data callback */ diff --git a/arch/arm/src/kinetis/Kconfig b/arch/arm/src/kinetis/Kconfig index cf781ade5e..a585a57fe4 100644 --- a/arch/arm/src/kinetis/Kconfig +++ b/arch/arm/src/kinetis/Kconfig @@ -254,7 +254,6 @@ config KINETIS_ENET select ARCH_HAVE_NETDEV_STATISTICS select NET select NETDEVICES - select NET_MULTIBUFFER ---help--- Support Ethernet (K6x only) diff --git a/arch/arm/src/kinetis/kinetis_enet.c b/arch/arm/src/kinetis/kinetis_enet.c index a546103d36..e83c3fcc94 100644 --- a/arch/arm/src/kinetis/kinetis_enet.c +++ b/arch/arm/src/kinetis/kinetis_enet.c @@ -119,10 +119,6 @@ #define NENET_NBUFFERS \ (CONFIG_KINETIS_ENETNTXBUFFERS+CONFIG_KINETIS_ENETNRXBUFFERS) -#ifndef CONFIG_NET_MULTIBUFFER -# error "CONFIG_NET_MULTIBUFFER is required in the configuration" -#endif - /* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per * second. */ diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.c b/arch/arm/src/lpc17xx/lpc17_ethernet.c index d5ff009fd6..150602b1e5 100644 --- a/arch/arm/src/lpc17xx/lpc17_ethernet.c +++ b/arch/arm/src/lpc17xx/lpc17_ethernet.c @@ -138,6 +138,8 @@ # define CONFIG_NET_PRIORITY NVIC_SYSH_PRIORITY_DEFAULT #endif +#define PKTBUF_SIZE (MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE) + /* Debug Configuration *****************************************************/ /* Register debug -- can only happen of CONFIG_DEBUG_NET_INFO is selected */ @@ -290,6 +292,10 @@ struct lpc17_driver_s * Private Data ****************************************************************************/ +/* A single packet buffer per interface is used */ + +static uint8_t g_pktbuf[PKTBUF_SIZE * CONFIG_LPC17_NINTERFACES]; + /* Array of ethernet driver status structures */ static struct lpc17_driver_s g_ethdrvr[CONFIG_LPC17_NINTERFACES]; @@ -3206,6 +3212,7 @@ static inline int lpc17_ethinitialize(int intf) #endif { struct lpc17_driver_s *priv; + uint8_t *pktbuf; uint32_t regval; int ret; int i; @@ -3225,11 +3232,17 @@ static inline int lpc17_ethinitialize(int intf) { (void)lpc17_configgpio(g_enetpins[i]); } + lpc17_showpins(); + /* Select the packet buffer */ + + pktbuf = &g_pktbuf[PKTBUF_SIZE * intf]; + /* Initialize the driver structure */ memset(priv, 0, sizeof(struct lpc17_driver_s)); + priv->lp_dev.d_buf = pktbuf; /* Single packet buffer */ priv->lp_dev.d_ifup = lpc17_ifup; /* I/F down callback */ priv->lp_dev.d_ifdown = lpc17_ifdown; /* I/F up (new IP address) callback */ priv->lp_dev.d_txavail = lpc17_txavail; /* New TX data callback */ @@ -3237,7 +3250,7 @@ static inline int lpc17_ethinitialize(int intf) priv->lp_dev.d_addmac = lpc17_addmac; /* Add multicast MAC address */ priv->lp_dev.d_rmmac = lpc17_rmmac; /* Remove multicast MAC address */ #endif - priv->lp_dev.d_private = (void *)priv; /* Used to recover private state from dev */ + priv->lp_dev.d_private = (void *)priv; /* Used to recover private state from dev */ #if CONFIG_LPC17_NINTERFACES > 1 # error "A mechanism to associate base address an IRQ with an interface is needed" diff --git a/arch/arm/src/lpc43xx/lpc43_ethernet.c b/arch/arm/src/lpc43xx/lpc43_ethernet.c index c96f1a7551..35d9926b52 100644 --- a/arch/arm/src/lpc43xx/lpc43_ethernet.c +++ b/arch/arm/src/lpc43xx/lpc43_ethernet.c @@ -164,12 +164,6 @@ #undef CONFIG_LPC43_ETH_ENHANCEDDESC #undef CONFIG_LPC43_ETH_HWCHECKSUM -/* Ethernet buffer sizes, number of buffers, and number of descriptors */ - -#ifndef CONFIG_NET_MULTIBUFFER -# error "CONFIG_NET_MULTIBUFFER is required" -#endif - /* Add 4 to the configured buffer size to account for the 2 byte checksum * memory needed at the end of the maximum size packet. Buffer sizes must * be an even multiple of 4, 8, or 16 bytes (depending on buswidth). We diff --git a/arch/arm/src/sam34/sam_emac.c b/arch/arm/src/sam34/sam_emac.c index 15e7b1b4ba..6f234cebcb 100644 --- a/arch/arm/src/sam34/sam_emac.c +++ b/arch/arm/src/sam34/sam_emac.c @@ -313,7 +313,6 @@ struct sam_emac_s static struct sam_emac_s g_emac; -#ifdef CONFIG_NET_MULTIBUFFER /* A single packet buffer is used * * REVISIT: It might be possible to use this option to send and receive @@ -324,7 +323,6 @@ static struct sam_emac_s g_emac; */ static uint8_t g_pktbuf[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE]; -#endif #ifdef CONFIG_SAM34_EMAC_PREALLOCATE /* Preallocated data */ @@ -3820,9 +3818,7 @@ void up_netinitialize(void) /* Initialize the driver structure */ memset(priv, 0, sizeof(struct sam_emac_s)); -#ifdef CONFIG_NET_MULTIBUFFER priv->dev.d_buf = g_pktbuf; /* Single packet buffer */ -#endif priv->dev.d_ifup = sam_ifup; /* I/F up (new IP address) callback */ priv->dev.d_ifdown = sam_ifdown; /* I/F down callback */ priv->dev.d_txavail = sam_txavail; /* New TX data callback */ diff --git a/arch/arm/src/sama5/sam_emaca.c b/arch/arm/src/sama5/sam_emaca.c index 672a3efc7f..67715ee204 100644 --- a/arch/arm/src/sama5/sam_emaca.c +++ b/arch/arm/src/sama5/sam_emaca.c @@ -290,7 +290,6 @@ struct sam_emac_s static struct sam_emac_s g_emac; -#ifdef CONFIG_NET_MULTIBUFFER /* A single packet buffer is used * * REVISIT: It might be possible to use this option to send and receive @@ -301,7 +300,6 @@ static struct sam_emac_s g_emac; */ static uint8_t g_pktbuf[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE]; -#endif #ifdef CONFIG_SAMA5_EMACA_PREALLOCATE /* Preallocated data */ @@ -3486,9 +3484,7 @@ int sam_emac_initialize(void) /* Initialize the driver structure */ memset(priv, 0, sizeof(struct sam_emac_s)); -#ifdef CONFIG_NET_MULTIBUFFER priv->dev.d_buf = g_pktbuf; /* Single packet buffer */ -#endif priv->dev.d_ifup = sam_ifup; /* I/F up (new IP address) callback */ priv->dev.d_ifdown = sam_ifdown; /* I/F down callback */ priv->dev.d_txavail = sam_txavail; /* New TX data callback */ diff --git a/arch/arm/src/sama5/sam_emacb.c b/arch/arm/src/sama5/sam_emacb.c index 3d9f282ce9..6eb3dd2108 100644 --- a/arch/arm/src/sama5/sam_emacb.c +++ b/arch/arm/src/sama5/sam_emacb.c @@ -710,7 +710,6 @@ static const struct sam_emacattr_s g_emac0_attr = #endif }; -#ifdef CONFIG_NET_MULTIBUFFER /* A single packet buffer is used * * REVISIT: It might be possible to use this option to send and receive @@ -721,7 +720,6 @@ static const struct sam_emacattr_s g_emac0_attr = */ static uint8_t g_pktbuf0[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE]; -#endif /* EMAC0 peripheral state */ @@ -793,7 +791,6 @@ static const struct sam_emacattr_s g_emac1_attr = #endif }; -#ifdef CONFIG_NET_MULTIBUFFER /* A single packet buffer is used * * REVISIT: It might be possible to use this option to send and receive @@ -804,7 +801,6 @@ static const struct sam_emacattr_s g_emac1_attr = */ static uint8_t g_pktbuf1[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE]; -#endif /* EMAC1 peripheral state */ @@ -4546,9 +4542,7 @@ int sam_emac_initialize(int intf) { struct sam_emac_s *priv; const struct sam_emacattr_s *attr; -#ifdef CONFIG_NET_MULTIBUFFER uint8_t *pktbuf; -#endif #if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) uint8_t phytype; #endif @@ -4559,10 +4553,7 @@ int sam_emac_initialize(int intf) { priv = &g_emac0; attr = &g_emac0_attr; - -#ifdef CONFIG_NET_MULTIBUFFER pktbuf = g_pktbuf0; -#endif #if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) phytype = SAMA5_EMAC0_PHY_TYPE; @@ -4575,10 +4566,7 @@ int sam_emac_initialize(int intf) { priv = &g_emac1; attr = &g_emac1_attr; - -#ifdef CONFIG_NET_MULTIBUFFER pktbuf = g_pktbuf1; -#endif #if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) phytype = SAMA5_EMAC1_PHY_TYPE; @@ -4595,9 +4583,7 @@ int sam_emac_initialize(int intf) memset(priv, 0, sizeof(struct sam_emac_s)); priv->attr = attr; /* Save the constant attributes */ -#ifdef CONFIG_NET_MULTIBUFFER priv->dev.d_buf = pktbuf; /* Single packet buffer */ -#endif priv->dev.d_ifup = sam_ifup; /* I/F up (new IP address) callback */ priv->dev.d_ifdown = sam_ifdown; /* I/F down callback */ priv->dev.d_txavail = sam_txavail; /* New TX data callback */ diff --git a/arch/arm/src/sama5/sam_gmac.c b/arch/arm/src/sama5/sam_gmac.c index 5442920ee0..d264282117 100644 --- a/arch/arm/src/sama5/sam_gmac.c +++ b/arch/arm/src/sama5/sam_gmac.c @@ -216,7 +216,6 @@ struct sam_gmac_s static struct sam_gmac_s g_gmac; -#ifdef CONFIG_NET_MULTIBUFFER /* A single packet buffer is used * * REVISIT: It might be possible to use this option to send and receive @@ -227,7 +226,6 @@ static struct sam_gmac_s g_gmac; */ static uint8_t g_pktbuf[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE]; -#endif #ifdef CONFIG_SAMA5_GMAC_PREALLOCATE /* Preallocated data */ @@ -3558,9 +3556,7 @@ int sam_gmac_initialize(void) /* Initialize the driver structure */ memset(priv, 0, sizeof(struct sam_gmac_s)); -#ifdef CONFIG_NET_MULTIBUFFER priv->dev.d_buf = g_pktbuf; /* Single packet buffer */ -#endif priv->dev.d_ifup = sam_ifup; /* I/F up (new IP address) callback */ priv->dev.d_ifdown = sam_ifdown; /* I/F down callback */ priv->dev.d_txavail = sam_txavail; /* New TX data callback */ diff --git a/arch/arm/src/samv7/sam_emac.c b/arch/arm/src/samv7/sam_emac.c index 2eefdcefa7..8c9c9e0827 100644 --- a/arch/arm/src/samv7/sam_emac.c +++ b/arch/arm/src/samv7/sam_emac.c @@ -856,7 +856,6 @@ static const struct sam_emacattr_s g_emac0_attr = #endif }; -#ifdef CONFIG_NET_MULTIBUFFER /* A single packet buffer is used * * REVISIT: It might be possible to use this option to send and receive @@ -867,7 +866,6 @@ static const struct sam_emacattr_s g_emac0_attr = */ static uint8_t g_pktbuf0[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE]; -#endif /* EMAC0 peripheral state */ @@ -939,7 +937,6 @@ static const struct sam_emacattr_s g_emac1_attr = #endif }; -#ifdef CONFIG_NET_MULTIBUFFER /* A single packet buffer is used * * REVISIT: It might be possible to use this option to send and receive @@ -950,7 +947,6 @@ static const struct sam_emacattr_s g_emac1_attr = */ static uint8_t g_pktbuf1[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE]; -#endif /* EMAC1 peripheral state */ @@ -5112,9 +5108,7 @@ int sam_emac_initialize(int intf) { struct sam_emac_s *priv; const struct sam_emacattr_s *attr; -#ifdef CONFIG_NET_MULTIBUFFER uint8_t *pktbuf; -#endif #if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) uint8_t phytype; #endif @@ -5125,10 +5119,7 @@ int sam_emac_initialize(int intf) { priv = &g_emac0; attr = &g_emac0_attr; - -#ifdef CONFIG_NET_MULTIBUFFER pktbuf = g_pktbuf0; -#endif #if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) phytype = SAMV7_EMAC0_PHY_TYPE; @@ -5141,10 +5132,7 @@ int sam_emac_initialize(int intf) { priv = &g_emac1; attr = &g_emac1_attr; - -#ifdef CONFIG_NET_MULTIBUFFER pktbuf = g_pktbuf1; -#endif #if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) phytype = SAMV7_EMAC1_PHY_TYPE; @@ -5161,9 +5149,7 @@ int sam_emac_initialize(int intf) memset(priv, 0, sizeof(struct sam_emac_s)); priv->attr = attr; /* Save the constant attributes */ -#ifdef CONFIG_NET_MULTIBUFFER priv->dev.d_buf = pktbuf; /* Single packet buffer */ -#endif priv->dev.d_ifup = sam_ifup; /* I/F up (new IP address) callback */ priv->dev.d_ifdown = sam_ifdown; /* I/F down callback */ priv->dev.d_txavail = sam_txavail; /* New TX data callback */ diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/stm32/stm32_eth.c index 635940ac95..8bb121237a 100644 --- a/arch/arm/src/stm32/stm32_eth.c +++ b/arch/arm/src/stm32/stm32_eth.c @@ -207,12 +207,6 @@ #undef CONFIG_STM32_ETH_ENHANCEDDESC #undef CONFIG_STM32_ETH_HWCHECKSUM -/* Ethernet buffer sizes, number of buffers, and number of descriptors */ - -#ifndef CONFIG_NET_MULTIBUFFER -# error "CONFIG_NET_MULTIBUFFER is required" -#endif - /* Add 4 to the configured buffer size to account for the 2 byte checksum * memory needed at the end of the maximum size packet. Buffer sizes must * be an even multiple of 4, 8, or 16 bytes (depending on buswidth). We diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c index eccf15b348..8301f80e5b 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.c +++ b/arch/arm/src/stm32f7/stm32_ethernet.c @@ -194,12 +194,6 @@ #undef CONFIG_STM32F7_ETH_ENHANCEDDESC #undef CONFIG_STM32F7_ETH_HWCHECKSUM -/* Ethernet buffer sizes, number of buffers, and number of descriptors */ - -#ifndef CONFIG_NET_MULTIBUFFER -# error "CONFIG_NET_MULTIBUFFER is required" -#endif - /* Add 4 to the configured buffer size to account for the 2 byte checksum * memory needed at the end of the maximum size packet. Buffer sizes must * be an even multiple of 4, 8, or 16 bytes (depending on buswidth). We diff --git a/arch/arm/src/tiva/lm3s_ethernet.c b/arch/arm/src/tiva/lm3s_ethernet.c index cbdf0dac53..852c19a0d3 100644 --- a/arch/arm/src/tiva/lm3s_ethernet.c +++ b/arch/arm/src/tiva/lm3s_ethernet.c @@ -191,11 +191,9 @@ struct tiva_driver_s * Private Data ****************************************************************************/ -#ifdef CONFIG_NET_MULTIBUFFER /* A single packet buffer is used */ static uint8_t g_pktbuf[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE]; -#endif /* Ethernet peripheral state */ @@ -1472,9 +1470,7 @@ static inline int tiva_ethinitialize(int intf) /* Initialize the driver structure */ memset(priv, 0, sizeof(struct tiva_driver_s)); -#ifdef CONFIG_NET_MULTIBUFFER priv->ld_dev.d_buf = g_pktbuf; /* Single packet buffer */ -#endif priv->ld_dev.d_ifup = tiva_ifup; /* I/F down callback */ priv->ld_dev.d_ifdown = tiva_ifdown; /* I/F up (new IP address) callback */ priv->ld_dev.d_txavail = tiva_txavail; /* New TX data callback */ diff --git a/arch/arm/src/tiva/tm4c_ethernet.c b/arch/arm/src/tiva/tm4c_ethernet.c index 3882a95db3..e00bf6ef31 100644 --- a/arch/arm/src/tiva/tm4c_ethernet.c +++ b/arch/arm/src/tiva/tm4c_ethernet.c @@ -219,10 +219,6 @@ /* Ethernet buffer sizes, number of buffers, and number of descriptors */ -#ifndef CONFIG_NET_MULTIBUFFER -# error CONFIG_NET_MULTIBUFFER is required -#endif - #ifndef CONFIG_TIVA_EMAC_NRXDESC # define CONFIG_TIVA_EMAC_NRXDESC 8 #endif diff --git a/arch/hc/src/m9s12/m9s12_ethernet.c b/arch/hc/src/m9s12/m9s12_ethernet.c index fe2656e97a..3a85446e6d 100644 --- a/arch/hc/src/m9s12/m9s12_ethernet.c +++ b/arch/hc/src/m9s12/m9s12_ethernet.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/hc/src/m9s12/m9s12_ethernet.c * - * Copyright (C) 2011, 2014-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2014-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -106,6 +106,12 @@ struct emac_driver_s * Private Data ****************************************************************************/ +/* A single packet buffer is used */ + +static uint8_t g_pktbuf[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE]; + +/* Driver state structure */ + static struct emac_driver_s g_emac[CONFIG_HCS12_NINTERFACES]; /**************************************************************************** @@ -756,6 +762,7 @@ int emac_initialize(int intf) /* Initialize the driver structure */ memset(priv, 0, sizeof(struct emac_driver_s)); + priv->d_dev.d_buf = g_pktbuf; /* Single packet buffer */ priv->d_dev.d_ifup = emac_ifup; /* I/F down callback */ priv->d_dev.d_ifdown = emac_ifdown; /* I/F up (new IP address) callback */ priv->d_dev.d_txavail = emac_txavail; /* New TX data callback */ @@ -767,8 +774,8 @@ int emac_initialize(int intf) /* Create a watchdog for timing polling for and timing of transmisstions */ - priv->d_txpoll = wd_create(); /* Create periodic poll timer */ - priv->d_txtimeout = wd_create(); /* Create TX timeout timer */ + priv->d_txpoll = wd_create(); /* Create periodic poll timer */ + priv->d_txtimeout = wd_create(); /* Create TX timeout timer */ /* Put the interface in the down state. This usually amounts to resetting * the device and/or calling emac_ifdown(). diff --git a/arch/mips/src/pic32mx/pic32mx-ethernet.c b/arch/mips/src/pic32mx/pic32mx-ethernet.c index 8a1bc08482..1b1ebcb6fc 100644 --- a/arch/mips/src/pic32mx/pic32mx-ethernet.c +++ b/arch/mips/src/pic32mx/pic32mx-ethernet.c @@ -102,12 +102,6 @@ # define CONFIG_PIC32MX_NINTERFACES 1 #endif -/* CONFIG_NET_MULTIBUFFER is required */ - -#ifndef CONFIG_NET_MULTIBUFFER -# error "CONFIG_NET_MULTIBUFFER=y is required" -#endif - /* If IGMP is enabled, then accept multi-cast frames. */ #if defined(CONFIG_NET_IGMP) && !defined(CONFIG_PIC32MX_MULTICAST) diff --git a/arch/mips/src/pic32mz/pic32mz-ethernet.c b/arch/mips/src/pic32mz/pic32mz-ethernet.c index b2df365449..fe245e5a74 100644 --- a/arch/mips/src/pic32mz/pic32mz-ethernet.c +++ b/arch/mips/src/pic32mz/pic32mz-ethernet.c @@ -102,12 +102,6 @@ # define CONFIG_PIC32MZ_NINTERFACES 1 #endif -/* CONFIG_NET_MULTIBUFFER is required */ - -#ifndef CONFIG_NET_MULTIBUFFER -# error "CONFIG_NET_MULTIBUFFER=y is required" -#endif - /* If IGMP is enabled, then accept multi-cast frames. */ #if defined(CONFIG_NET_IGMP) && !defined(CONFIG_PIC32MZ_MULTICAST) diff --git a/arch/misoc/src/common/misoc_net.c b/arch/misoc/src/common/misoc_net.c index 7b4b84c2f0..8854616266 100644 --- a/arch/misoc/src/common/misoc_net.c +++ b/arch/misoc/src/common/misoc_net.c @@ -140,6 +140,12 @@ struct misoc_net_driver_s * Private Data ****************************************************************************/ +/* A single packet buffer is used */ + +static uint8_t g_pktbuf[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE]; + +/* Driver state structur */ + static struct misoc_net_driver_s g_misoc_net[CONFIG_MISOC_NET_NINTERFACES]; /**************************************************************************** @@ -1333,6 +1339,7 @@ int misoc_net_initialize(int intf) priv->tx_buf = priv->tx0_buf; priv->tx_slot=0; + priv->misoc_net_dev.d_buf = g_pktbuf; /* Single packet buffer */ priv->misoc_net_dev.d_ifup = misoc_net_ifup; /* I/F up (new IP address) callback */ priv->misoc_net_dev.d_ifdown = misoc_net_ifdown; /* I/F down callback */ priv->misoc_net_dev.d_txavail = misoc_net_txavail; /* New TX data callback */ diff --git a/arch/sim/src/up_netdriver.c b/arch/sim/src/up_netdriver.c index 1e7ef5345c..d9c12ae339 100644 --- a/arch/sim/src/up_netdriver.c +++ b/arch/sim/src/up_netdriver.c @@ -78,15 +78,18 @@ struct timer uint32_t start; }; -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - /**************************************************************************** * Private Data ****************************************************************************/ static struct timer g_periodic_timer; + +/* A single packet buffer is used */ + +static uint8_t g_pktbuf[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE]; + +/* Ethernet peripheral state */ + static struct net_driver_s g_sim_dev; /**************************************************************************** @@ -340,6 +343,7 @@ int netdriver_init(void) /* Set callbacks */ + g_sim_dev.d_buf = g_pktbuf; /* Single packet buffer */ g_sim_dev.d_ifup = netdriver_ifup; g_sim_dev.d_ifdown = netdriver_ifdown; diff --git a/arch/z80/src/ez80/ez80_emac.c b/arch/z80/src/ez80/ez80_emac.c index d4e56bf04f..0020991551 100644 --- a/arch/z80/src/ez80/ez80_emac.c +++ b/arch/z80/src/ez80/ez80_emac.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/z80/src/ez80/ez80_emac.c * - * Copyright (C) 2009-2010, 2012, 2014-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010, 2012, 2014-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: @@ -334,6 +334,10 @@ struct ez80emac_driver_s * Private Data ****************************************************************************/ +/* A single packet buffer is used */ + +static uint8_t g_pktbuf[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE]; + /* There is only a single instance of driver private data (because there is * only one EMAC interface. */ @@ -2224,6 +2228,7 @@ int up_netinitialize(void) /* Initialize the driver structure */ memset(&g_emac, 0, sizeof(struct ez80emac_driver_s)); + priv->dev.d_buf = g_pktbuf; /* Single packet buffer */ priv->dev.d_ifup = ez80emac_ifup; /* I/F down callback */ priv->dev.d_ifdown = ez80emac_ifdown; /* I/F up (new IP address) callback */ priv->dev.d_txavail = ez80emac_txavail; /* New TX data callback */ -- GitLab From c09ae58e3f38774ac158eb99a4a6fab7869b72f4 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 29 Nov 2016 16:08:36 -0600 Subject: [PATCH 551/734] include/: Remove all references to CONFIG_NET_MULTIBUFFER. d_buf in struct net_driver_s is now always a pointer vs. an array. --- include/nuttx/net/arp.h | 14 +++++++------- include/nuttx/net/netdev.h | 20 ++++++++------------ include/nuttx/net/slip.h | 1 - 3 files changed, 15 insertions(+), 20 deletions(-) diff --git a/include/nuttx/net/arp.h b/include/nuttx/net/arp.h index cf04895f76..a5365ea35e 100644 --- a/include/nuttx/net/arp.h +++ b/include/nuttx/net/arp.h @@ -137,7 +137,7 @@ extern "C" ****************************************************************************/ #ifdef CONFIG_NET_ARP_IPIN -void arp_ipin(struct net_driver_s *dev); +void arp_ipin(FAR struct net_driver_s **dev); #else # define arp_ipin(dev) #endif @@ -152,20 +152,20 @@ void arp_ipin(struct net_driver_s *dev); * that we previously sent out, the ARP cache will be filled in with * the values from the ARP reply. If the incoming ARP packet is an ARP * request for our IP address, an ARP reply packet is created and put - * into the d_buf[] buffer. + * into the d_buf buffer. * * On entry, this function expects that an ARP packet with a prepended - * Ethernet header is present in the d_buf[] buffer and that the length of + * Ethernet header is present in the d_buf buffer and that the length of * the packet is set in the d_len field. * * When the function returns, the value of the field d_len indicates whether * the device driver should send out the ARP reply packet or not. If d_len * is zero, no packet should be sent; If d_len is non-zero, it contains the - * length of the outbound packet that is present in the d_buf[] buffer. + * length of the outbound packet that is present in the d_buf buffer. * ****************************************************************************/ -void arp_arpin(struct net_driver_s *dev); +void arp_arpin(FAR struct net_driver_s **dev); /**************************************************************************** * Name: arp_out @@ -183,13 +183,13 @@ void arp_arpin(struct net_driver_s *dev); * beginning of the packet and the function returns. * * If no ARP cache entry is found for the destination IIPv4P address, the - * packet in the d_buf[] is replaced by an ARP request packet for the + * packet in the d_buf is replaced by an ARP request packet for the * IPv4 address. The IPv4 packet is dropped and it is assumed that the * higher level protocols (e.g., TCP) eventually will retransmit the * dropped packet. * * Upon return in either the case, a packet to be sent is present in the - * d_buf[] buffer and the d_len field holds the length of the Ethernet + * d_buf buffer and the d_len field holds the length of the Ethernet * frame that should be transmitted. * ****************************************************************************/ diff --git a/include/nuttx/net/netdev.h b/include/nuttx/net/netdev.h index 7ef7cc62d7..aceab4d083 100644 --- a/include/nuttx/net/netdev.h +++ b/include/nuttx/net/netdev.h @@ -227,23 +227,19 @@ struct net_driver_s net_ipv6addr_t d_ipv6netmask; /* Network IPv6 subnet mask */ #endif - /* The d_buf array is used to hold incoming and outgoing packets. The device - * driver should place incoming data into this buffer. When sending data, - * the device driver should read the link level headers and the TCP/IP - * headers from this buffer. The size of the link level headers is + /* The d_buf array is used to hold incoming and outgoing packets. The + * device driver should place incoming data into this buffer. When sending + * data, the device driver should read the link level headers and the + * TCP/IP headers from this buffer. The size of the link level headers is * configured by the NET_LL_HDRLEN(dev) define. * * The network will handle only a single buffer for both incoming and - * outgoing packets. However, the driver design may be concurrently send - * and filling separate, break-off buffers if CONFIG_NET_MULTIBUFFER is - * defined. That buffer management must be controlled by the driver. + * outgoing packets. However, the driver design may be concurrently + * sending and filling separate, break-off buffers. That buffer + * management must be controlled by the driver. */ -#ifdef CONFIG_NET_MULTIBUFFER - uint8_t *d_buf; -#else - uint8_t d_buf[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE]; -#endif + FAR uint8_t *d_buf; /* d_appdata points to the location where application data can be read from * or written to in the the packet buffer. diff --git a/include/nuttx/net/slip.h b/include/nuttx/net/slip.h index 1fb2e46514..3818b5083d 100644 --- a/include/nuttx/net/slip.h +++ b/include/nuttx/net/slip.h @@ -54,7 +54,6 @@ /* Dependencies: * * CONFIG_NET_NOINTS - Required. - * CONFIG_NET_MULTIBUFFER - Required. * * SLIP Configuration: * -- GitLab From 00beb665f59a5bdec2f027a30914b351ff6bc0e9 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 29 Nov 2016 16:12:39 -0600 Subject: [PATCH 552/734] net/: Remove references to CONFIG_NET_MULTIBUFFER --- net/Kconfig | 15 +-------------- net/arp/arp_arpin.c | 6 +++--- net/arp/arp_out.c | 4 ++-- net/neighbor/neighbor_out.c | 4 ++-- 4 files changed, 8 insertions(+), 21 deletions(-) diff --git a/net/Kconfig b/net/Kconfig index a216650c76..1655cb0abf 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -40,17 +40,6 @@ config NET_PROMISCUOUS menu "Driver buffer configuration" -config NET_MULTIBUFFER - bool "Use multiple device-side I/O buffers" - default n - ---help--- - Traditionally, the uIP-based stack has used a single buffer for all - incoming and outgoing traffic. If this configuration is selected, - then the driver can manage multiple I/O buffers and can, for - example, be filling one input buffer while sending another output - buffer. Or, as another example, the driver may support queuing of - concurrent input/ouput and output transfers for better performance. - config NET_ETH_MTU int "Ethernet packet buffer size (MTU)" default 1294 if NET_IPv6 @@ -171,8 +160,7 @@ config NET_SLIP select NET_MULTILINK if NET_ETHERNET || NET_LOOPBACK || NET_TUN ---help--- Enables building of the SLIP driver. SLIP requires - at least one IP protocol selected and the following additional - network settings: NET_NOINTS and NET_MULTIBUFFER. + at least one IP protocol selected and CONFIG_NET_NOINTS. SLIP supports point-to-point IP communications over a serial port. The default data link layer for network layer is Ethernet. If @@ -217,7 +205,6 @@ config NET_TUN default n select NETDEV_MULTINIC if NET_ETHERNET || NET_LOOPBACK || NET_SLIP select NET_MULTILINK if NET_ETHERNET || NET_LOOPBACK || NET_SLIP - select NET_MULTIBUFFER select ARCH_HAVE_NETDEV_STATISTICS if NET_TUN diff --git a/net/arp/arp_arpin.c b/net/arp/arp_arpin.c index 40c557c41d..fe8d47a63e 100644 --- a/net/arp/arp_arpin.c +++ b/net/arp/arp_arpin.c @@ -76,16 +76,16 @@ * that we previously sent out, the ARP cache will be filled in with * the values from the ARP reply. If the incoming ARP packet is an ARP * request for our IP address, an ARP reply packet is created and put - * into the d_buf[] buffer. + * into the d_buf buffer. * * On entry, this function expects that an ARP packet with a prepended - * Ethernet header is present in the d_buf[] buffer and that the length of + * Ethernet header is present in the d_buf buffer and that the length of * the packet is set in the d_len field. * * When the function returns, the value of the field d_len indicates whether * the device driver should send out the ARP reply packet or not. If d_len * is zero, no packet should be sent; If d_len is non-zero, it contains the - * length of the outbound packet that is present in the d_buf[] buffer. + * length of the outbound packet that is present in the d_buf buffer. * ****************************************************************************/ diff --git a/net/arp/arp_out.c b/net/arp/arp_out.c index 667851a200..b816197671 100644 --- a/net/arp/arp_out.c +++ b/net/arp/arp_out.c @@ -123,13 +123,13 @@ static const uint8_t g_multicast_ethaddr[3] = * beginning of the packet and the function returns. * * If no ARP cache entry is found for the destination IP address, the - * packet in the d_buf[] is replaced by an ARP request packet for the + * packet in the d_buf is replaced by an ARP request packet for the * IP address. The IP packet is dropped and it is assumed that the * higher level protocols (e.g., TCP) eventually will retransmit the * dropped packet. * * Upon return in either the case, a packet to be sent is present in the - * d_buf[] buffer and the d_len field holds the length of the Ethernet + * d_buf buffer and the d_len field holds the length of the Ethernet * frame that should be transmitted. * ****************************************************************************/ diff --git a/net/neighbor/neighbor_out.c b/net/neighbor/neighbor_out.c index c00253ffe3..4725a90ea2 100644 --- a/net/neighbor/neighbor_out.c +++ b/net/neighbor/neighbor_out.c @@ -120,13 +120,13 @@ static const uint8_t g_multicast_ethaddr[3] = * beginning of the packet and the function returns. * * If no Neighbor Table entry is found for the destination IPv6 address, - * the packet in the d_buf[] is replaced by an ICMPv6 Neighbor Solicit + * the packet in the d_buf is replaced by an ICMPv6 Neighbor Solicit * request packet for the IPv6 address. The IPv6 packet is dropped and * it is assumed that the higher level protocols (e.g., TCP) eventually * will retransmit the dropped packet. * * Upon return in either the case, a packet to be sent is present in the - * d_buf[] buffer and the d_len field holds the length of the Ethernet + * d_buf buffer and the d_len field holds the length of the Ethernet * frame that should be transmitted. * ****************************************************************************/ -- GitLab From 96be43b2707119398538d461b1235f28c52557ea Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 29 Nov 2016 16:44:23 -0600 Subject: [PATCH 553/734] drivers/net/: Adapt all Ethernet drivers to work as though CONFIG_NET_MULTIBUFFER were set. Remove all references to CONFIG_NET_MULTIBUFFER --- drivers/net/cs89x0.c | 18 +++++-- drivers/net/dm90x0.c | 7 ++- drivers/net/e1000.c | 55 ++++++++++++------- drivers/net/enc28j60.c | 7 +++ drivers/net/encx24j600.c | 7 +++ drivers/net/ftmac100.c | 7 +++ drivers/net/loopback.c | 7 +-- drivers/net/skeleton.c | 16 +++++- drivers/net/slip.c | 4 -- drivers/net/vnet.c | 111 ++++++++++++++++++++++----------------- 10 files changed, 154 insertions(+), 85 deletions(-) diff --git a/drivers/net/cs89x0.c b/drivers/net/cs89x0.c index dd2af6658b..f662f40f38 100644 --- a/drivers/net/cs89x0.c +++ b/drivers/net/cs89x0.c @@ -1,7 +1,7 @@ /**************************************************************************** * drivers/net/cs89x0.c * - * Copyright (C) 2009-2011, 2014-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2011, 2014-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -93,9 +93,7 @@ # define cs89x0_mapirq(irq) g_cs89x0[0] #endif -/**************************************************************************** - * Private Types - ****************************************************************************/ +#define PKTBUF_SIZE (MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE) /**************************************************************************** * Private Data @@ -1008,6 +1006,8 @@ static int cs89x0_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac) int cs89x0_initialize(FAR const cs89x0_driver_s *cs89x0, int devno) { + FAR uint8_t *pktbuf; + /* Sanity checks -- only performed with debug enabled */ #ifdef CONFIG_DEBUG_FEATURES @@ -1030,9 +1030,18 @@ int cs89x0_initialize(FAR const cs89x0_driver_s *cs89x0, int devno) return -EAGAIN; } + /* Allocate a packet buffer */ + + pktbuf = (FAR uint_t *)kmm_alloc(MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE); + if (pktbuf == NULL) + { + return -ENOMEM; + } + /* Initialize the driver structure */ g_cs89x[devno] = cs89x0; /* Used to map IRQ back to instance */ + cs89x0->cs_dev.d_buf = g_pktbuf; /* Single packet buffer */ cs89x0->cs_dev.d_ifup = cs89x0_ifup; /* I/F down callback */ cs89x0->cs_dev.d_ifdown = cs89x0_ifdown; /* I/F up (new IP address) callback */ cs89x0->cs_dev.d_txavail = cs89x0_txavail; /* New TX data callback */ @@ -1056,4 +1065,3 @@ int cs89x0_initialize(FAR const cs89x0_driver_s *cs89x0, int devno) } #endif /* CONFIG_NET && CONFIG_NET_CS89x0 */ - diff --git a/drivers/net/dm90x0.c b/drivers/net/dm90x0.c index ddc809f4c5..c99cf1846c 100644 --- a/drivers/net/dm90x0.c +++ b/drivers/net/dm90x0.c @@ -1,7 +1,7 @@ /**************************************************************************** * drivers/net/dm9x.c * - * Copyright (C) 2007-2010, 2014-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2010, 2014-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: Davicom data sheets (DM9000-DS-F03-041906.pdf, @@ -318,6 +318,10 @@ struct dm9x_driver_s * Private Data ****************************************************************************/ +/* A single packet buffer is used */ + +static uint8_t g_pktbuf[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE]; + /* At present, only a single DM90x0 device is supported. */ static struct dm9x_driver_s g_dm9x[CONFIG_DM9X_NINTERFACES]; @@ -1746,6 +1750,7 @@ int dm9x_initialize(void) /* Initialize the driver structure */ memset(g_dm9x, 0, CONFIG_DM9X_NINTERFACES*sizeof(struct dm9x_driver_s)); + g_dm9x[0].dm_dev.d_buf = g_pktbuf; /* Single packet buffer */ g_dm9x[0].dm_dev.d_ifup = dm9x_ifup; /* I/F down callback */ g_dm9x[0].dm_dev.d_ifdown = dm9x_ifdown; /* I/F up (new IP address) callback */ g_dm9x[0].dm_dev.d_txavail = dm9x_txavail; /* New TX data callback */ diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 6d5d5dc4f5..5bd17e2ae6 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -6,7 +6,7 @@ * * This file is a part of NuttX: * - * Copyright (C) 2011, 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2014, 2016 Gregory Nutt. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -83,6 +83,10 @@ #define E1000_TXTIMEOUT (60*CLK_TCK) +/* Size of one packet */ + +#define PKTBUF_SIZE (MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE) + /* This is a helper pointer for accessing the contents of the Ethernet header */ #define BUF ((struct eth_hdr_s *)e1000->netdev.d_buf) @@ -1087,18 +1091,26 @@ static pci_id_t e1000_id_table[] = static int e1000_probe(uint16_t addr, pci_id_t id) { - uint32_t mmio_base, mmio_size; + FAR struct e1000_dev *dev; + uint32_t mmio_base; + uint32_t mmio_size; uint32_t size; + FAR uint8_t *pktbuf + FAR void *kmem; + FAR void *omem; int errcode; - void *kmem; - void *omem; - struct e1000_dev *dev; - /* alloc e1000_dev memory */ + /* Allocate e1000_dev memory */ - if ((dev = kmm_zalloc(sizeof(struct e1000_dev))) == NULL) + if ((dev = (FAR struct e1000_dev *)kmm_zalloc(sizeof(struct e1000_dev))) == NULL) { - return -1; + return -ENOMEM; + } + + if ((pktbuf = (FAR uint8_t *)kmm_zalloc(PKTBUF_SIZE)) == NULL) + { + errcode = -ENOMEM; + goto errout_with_dev; } /* save pci addr */ @@ -1109,7 +1121,7 @@ static int e1000_probe(uint16_t addr, pci_id_t id) if ((errcode = pci_enable_device(addr, PCI_BUS_MASTER)) < 0) { - goto error; + goto errout_with_pktbuf; } /* get e1000 device type */ @@ -1123,12 +1135,12 @@ static int e1000_probe(uint16_t addr, pci_id_t id) errcode = rgmp_memmap_nocache(mmio_base, mmio_size, mmio_base); if (errcode) { - goto error; + goto errout_with_pktbuf; } dev->phy_mem_base = mmio_base; - dev->io_mem_base = mmio_base; - dev->mem_size = mmio_size; + dev->io_mem_base = mmio_base; + dev->mem_size = mmio_size; /* MAC address */ @@ -1141,7 +1153,7 @@ static int e1000_probe(uint16_t addr, pci_id_t id) dev->int_desc.dev_id = dev; if ((errcode = pci_request_irq(addr, &dev->int_desc, 0)) < 0) { - goto err0; + goto errout_with_memmap; } /* Here we alloc a big block of memory once and make it @@ -1161,11 +1173,12 @@ static int e1000_probe(uint16_t addr, pci_id_t id) CONFIG_E1000_N_RX_DESC * sizeof(struct rx_desc) + CONFIG_E1000_N_RX_DESC * CONFIG_E1000_BUFF_SIZE; size = ROUNDUP(size, PGSIZE); + omem = kmem = memalign(PGSIZE, size); if (kmem == NULL) { errcode = -ENOMEM; - goto err1; + goto errout_with_pci; } rgmp_memremap_nocache((uintptr_t)kmem, size); @@ -1185,6 +1198,7 @@ static int e1000_probe(uint16_t addr, pci_id_t id) /* Initialize the driver structure */ + dev->netdev.d_buf = pktbuf; /* Single packet buffer */ dev->netdev.d_ifup = e1000_ifup; /* I/F up (new IP address) callback */ dev->netdev.d_ifdown = e1000_ifdown; /* I/F down callback */ dev->netdev.d_txavail = e1000_txavail; /* New TX data callback */ @@ -1214,7 +1228,7 @@ static int e1000_probe(uint16_t addr, pci_id_t id) errcode = netdev_register(&dev->netdev, NET_LL_ETHERNET); if (errcode) { - goto err2; + goto errout_with_omem; } /* insert into e1000_list */ @@ -1225,14 +1239,16 @@ static int e1000_probe(uint16_t addr, pci_id_t id) return 0; -err2: +errout_with_omem: rgmp_memremap((uintptr_t)omem, size); free(omem); -err1: +errout_with_pci: pci_free_irq(addr); -err0: +errout_with_memmap: rgmp_memunmap(mmio_base, mmio_size); -error: +errout_with_pktbuf: + kmm_free(pktbuf); +errout_with_dev: kmm_free(dev); cprintf("e1000 device probe fail: %d\n", errcode); return errcode; @@ -1268,6 +1284,7 @@ void e1000_mod_exit(void) free(dev->tx_ring.desc); pci_free_irq(dev->pci_addr); rgmp_memunmap((uintptr_t)dev->io_mem_base, dev->mem_size); + kmm_free(dev->netdev.d_buf); kmm_free(dev); } diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c index a1c052f73d..99b9610685 100644 --- a/drivers/net/enc28j60.c +++ b/drivers/net/enc28j60.c @@ -269,6 +269,12 @@ struct enc_driver_s * Private Data ****************************************************************************/ +/* A single packet buffer is used */ + +static uint8_t g_pktbuf[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE]; + +/* Driver status structure */ + static struct enc_driver_s g_enc28j60[CONFIG_ENC28J60_NINTERFACES]; /**************************************************************************** @@ -2631,6 +2637,7 @@ int enc_initialize(FAR struct spi_dev_s *spi, /* Initialize the driver structure */ memset(g_enc28j60, 0, CONFIG_ENC28J60_NINTERFACES*sizeof(struct enc_driver_s)); + priv->dev.d_buf = g_pktbuf; /* Single packet buffer */ priv->dev.d_ifup = enc_ifup; /* I/F down callback */ priv->dev.d_ifdown = enc_ifdown; /* I/F up (new IP address) callback */ priv->dev.d_txavail = enc_txavail; /* New TX data callback */ diff --git a/drivers/net/encx24j600.c b/drivers/net/encx24j600.c index af415ac6d3..58aacaf603 100644 --- a/drivers/net/encx24j600.c +++ b/drivers/net/encx24j600.c @@ -282,6 +282,12 @@ struct enc_driver_s * Private Data ****************************************************************************/ +/* A single packet buffer is used */ + +static uint8_t g_pktbuf[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE]; + +/* Driver status structure */ + static struct enc_driver_s g_encx24j600[CONFIG_ENCX24J600_NINTERFACES]; /**************************************************************************** @@ -2866,6 +2872,7 @@ int enc_initialize(FAR struct spi_dev_s *spi, /* Initialize the driver structure */ memset(g_encx24j600, 0, CONFIG_ENCX24J600_NINTERFACES*sizeof(struct enc_driver_s)); + priv->dev.d_buf = g_pktbuf; /* Single packet buffer */ priv->dev.d_ifup = enc_ifup; /* I/F up (new IP address) callback */ priv->dev.d_ifdown = enc_ifdown; /* I/F down callback */ priv->dev.d_txavail = enc_txavail; /* New TX data callback */ diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c index c1fbec650a..c03e05ccb6 100644 --- a/drivers/net/ftmac100.c +++ b/drivers/net/ftmac100.c @@ -192,6 +192,12 @@ struct ftmac100_driver_s * Private Data ****************************************************************************/ +/* A single packet buffer is used */ + +static uint8_t g_pktbuf[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE]; + +/* Driver state structure. */ + static struct ftmac100_driver_s g_ftmac100[CONFIG_FTMAC100_NINTERFACES] __attribute__((aligned(16))); @@ -1738,6 +1744,7 @@ int ftmac100_initialize(int intf) /* Initialize the driver structure */ memset(priv, 0, sizeof(struct ftmac100_driver_s)); + priv->ft_dev.d_buf = g_pktbuf; /* Single packet buffer */ priv->ft_dev.d_ifup = ftmac100_ifup; /* I/F up (new IP address) callback */ priv->ft_dev.d_ifdown = ftmac100_ifdown; /* I/F down callback */ priv->ft_dev.d_txavail = ftmac100_txavail; /* New TX data callback */ diff --git a/drivers/net/loopback.c b/drivers/net/loopback.c index a9c1b6a819..8a703f6a60 100644 --- a/drivers/net/loopback.c +++ b/drivers/net/loopback.c @@ -1,7 +1,7 @@ /**************************************************************************** * drivers/net/loopback.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -121,10 +121,7 @@ struct lo_driver_s ****************************************************************************/ static struct lo_driver_s g_loopback; - -#ifdef CONFIG_NET_MULTIBUFFER static uint8_t g_iobuffer[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE]; -#endif /**************************************************************************** * Private Function Prototypes @@ -555,9 +552,7 @@ int localhost_initialize(void) priv->lo_dev.d_addmac = lo_addmac; /* Add multicast MAC address */ priv->lo_dev.d_rmmac = lo_rmmac; /* Remove multicast MAC address */ #endif -#ifdef CONFIG_NET_MULTIBUFFER priv->lo_dev.d_buf = g_iobuffer; /* Attach the IO buffer */ -#endif priv->lo_dev.d_private = (FAR void *)priv; /* Used to recover private state from dev */ /* Create a watchdog for timing polling for and timing of transmissions */ diff --git a/drivers/net/skeleton.c b/drivers/net/skeleton.c index ea24cf688c..49ad691a4c 100644 --- a/drivers/net/skeleton.c +++ b/drivers/net/skeleton.c @@ -1,7 +1,7 @@ /**************************************************************************** * drivers/net/skeleton.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -133,6 +133,19 @@ struct skel_driver_s * Private Data ****************************************************************************/ +/* These statically allocated structur would mean that only a single + * instance of the device could be supported. In order to support multiple + * devices instances, this data would have to be allocated dynamically. + */ + +/* A single packet buffer per device is used here. There might be multiple + * packet buffers in a more complex, pipelined design. + */ + +static uint8_t g_pktbuf[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE]; + +/* Driver state structure */ + static struct skel_driver_s g_skel[CONFIG_skeleton_NINTERFACES]; /**************************************************************************** @@ -1234,6 +1247,7 @@ int skel_initialize(int intf) /* Initialize the driver structure */ memset(priv, 0, sizeof(struct skel_driver_s)); + priv->sk_dev.d_buf = g_pktbuf; /* Single packet buffer */ priv->sk_dev.d_ifup = skel_ifup; /* I/F up (new IP address) callback */ priv->sk_dev.d_ifdown = skel_ifdown; /* I/F down callback */ priv->sk_dev.d_txavail = skel_txavail; /* New TX data callback */ diff --git a/drivers/net/slip.c b/drivers/net/slip.c index 744126971e..0470027d57 100644 --- a/drivers/net/slip.c +++ b/drivers/net/slip.c @@ -80,10 +80,6 @@ # warning "CONFIG_NET_NOINTS must be set" #endif -#ifndef CONFIG_NET_MULTIBUFFER -# warning "CONFIG_NET_MULTIBUFFER must be set" -#endif - #ifndef CONFIG_NET_SLIP_STACKSIZE # define CONFIG_NET_SLIP_STACKSIZE 2048 #endif diff --git a/drivers/net/vnet.c b/drivers/net/vnet.c index 8f6f14afb2..18dc4d5c36 100644 --- a/drivers/net/vnet.c +++ b/drivers/net/vnet.c @@ -88,7 +88,9 @@ /* This is a helper pointer for accessing the contents of the Ethernet header */ -#define BUF ((struct eth_hdr_s *)vnet->sk_dev.d_buf) +#define BUF ((struct eth_hdr_s *)vnet->vn_dev.d_buf) + +#define PKTBUF_SIZE (MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE) /**************************************************************************** * Private Types @@ -100,19 +102,25 @@ struct vnet_driver_s { - bool sk_bifup; /* true:ifup false:ifdown */ - WDOG_ID sk_txpoll; /* TX poll timer */ + bool vn_bifup; /* true:ifup false:ifdown */ + WDOG_ID vn_txpoll; /* TX poll timer */ struct rgmp_vnet *vnet; /* This holds the information visible to the NuttX */ - struct net_driver_s sk_dev; /* Interface understood by the network */ + struct net_driver_s vn_dev; /* Interface understood by the network */ }; /**************************************************************************** * Private Data ****************************************************************************/ +/* A single packet buffer per driver is used */ + +static uint8_t g_pktbuf[PKTBUF_SIZE * CONFIG_VNET_NINTERFACES]; + +/* Driver state structure instancs */ + static struct vnet_driver_s g_vnet[CONFIG_VNET_NINTERFACES]; /**************************************************************************** @@ -176,9 +184,9 @@ static int vnet_transmit(FAR struct vnet_driver_s *vnet) * must have assured that there is not transmission in progress. */ - /* Send the packet: address=vnet->sk_dev.d_buf, length=vnet->sk_dev.d_len */ + /* Send the packet: address=vnet->vn_dev.d_buf, length=vnet->vn_dev.d_len */ - errcode = vnet_xmit(vnet->vnet, (char *)vnet->sk_dev.d_buf, vnet->sk_dev.d_len); + errcode = vnet_xmit(vnet->vnet, (char *)vnet->vn_dev.d_buf, vnet->vn_dev.d_len); if (errcode) { /* When vnet_xmit fail, it means TX buffer is full. Watchdog @@ -234,7 +242,7 @@ static int vnet_txpoll(struct net_driver_s *dev) * the field d_len is set to a value > 0. */ - if (vnet->sk_dev.d_len > 0) + if (vnet->vn_dev.d_len > 0) { /* Look up the destination MAC address and add it to the Ethernet * header. @@ -242,10 +250,10 @@ static int vnet_txpoll(struct net_driver_s *dev) #ifdef CONFIG_NET_IPv4 #ifdef CONFIG_NET_IPv6 - if (IFF_IS_IPv4(vnet->sk_dev.d_flags)) + if (IFF_IS_IPv4(vnet->vn_dev.d_flags)) #endif { - arp_out(&vnet->sk_dev); + arp_out(&vnet->vn_dev); } #endif /* CONFIG_NET_IPv4 */ @@ -254,7 +262,7 @@ static int vnet_txpoll(struct net_driver_s *dev) else #endif { - neighbor_out(&vnet->sk_dev); + neighbor_out(&vnet->vn_dev); } #endif /* CONFIG_NET_IPv6 */ @@ -314,17 +322,17 @@ void rtos_vnet_recv(struct rgmp_vnet *rgmp_vnet, char *data, int len) return; } - /* Copy the data data from the hardware to vnet->sk_dev.d_buf. Set - * amount of data in vnet->sk_dev.d_len + /* Copy the data data from the hardware to vnet->vn_dev.d_buf. Set + * amount of data in vnet->vn_dev.d_len */ - memcpy(vnet->sk_dev.d_buf, data, len); - vnet->sk_dev.d_len = len; + memcpy(vnet->vn_dev.d_buf, data, len); + vnet->vn_dev.d_len = len; #ifdef CONFIG_NET_PKT /* When packet sockets are enabled, feed the frame into the packet tap */ - pkt_input(&vnet->sk_dev); + pkt_input(&vnet->vn_dev); #endif /* We only accept IP packets of the configured type and ARP packets */ @@ -338,27 +346,27 @@ void rtos_vnet_recv(struct rgmp_vnet *rgmp_vnet, char *data, int len) * layer */ - arp_ipin(&vnet->sk_dev); - ipv4_input(&vnet->sk_dev); + arp_ipin(&vnet->vn_dev); + ipv4_input(&vnet->vn_dev); /* If the above function invocation resulted in data that should be * sent out on the network, the field d_len will set to a value > 0. */ - if (vnet->sk_dev.d_len > 0) + if (vnet->vn_dev.d_len > 0) { /* Update the Ethernet header with the correct MAC address */ #ifdef CONFIG_NET_IPv6 - if (IFF_IS_IPv4(vnet->sk_dev.d_flags)) + if (IFF_IS_IPv4(vnet->vn_dev.d_flags)) #endif { - arp_out(&vnet->sk_dev); + arp_out(&vnet->vn_dev); } #ifdef CONFIG_NET_IPv6 else { - neighbor_out(&vnet->sk_dev); + neighbor_out(&vnet->vn_dev); } #endif @@ -376,26 +384,26 @@ void rtos_vnet_recv(struct rgmp_vnet *rgmp_vnet, char *data, int len) /* Give the IPv6 packet to the network layer */ - ipv6_input(&vnet->sk_dev); + ipv6_input(&vnet->vn_dev); /* If the above function invocation resulted in data that should be * sent out on the network, the field d_len will set to a value > 0. */ - if (vnet->sk_dev.d_len > 0) + if (vnet->vn_dev.d_len > 0) { /* Update the Ethernet header with the correct MAC address */ #ifdef CONFIG_NET_IPv4 - if (IFF_IS_IPv4(vnet->sk_dev.d_flags)) + if (IFF_IS_IPv4(vnet->vn_dev.d_flags)) { - arp_out(&vnet->sk_dev); + arp_out(&vnet->vn_dev); } else #endif #ifdef CONFIG_NET_IPv6 { - neighbor_out(&vnet->sk_dev); + neighbor_out(&vnet->vn_dev); } #endif @@ -409,14 +417,14 @@ void rtos_vnet_recv(struct rgmp_vnet *rgmp_vnet, char *data, int len) #ifdef CONFIG_NET_ARP if (BUF->type == htons(ETHTYPE_ARP)) { - arp_arpin(&vnet->sk_dev); + arp_arpin(&vnet->vn_dev); /* If the above function invocation resulted in data that should * be sent out on the network, the field d_len will set to a * value > 0. */ - if (vnet->sk_dev.d_len > 0) + if (vnet->vn_dev.d_len > 0) { vnet_transmit(vnet); } @@ -447,7 +455,7 @@ static void vnet_txdone(FAR struct vnet_driver_s *vnet) { /* Poll the network for new XMIT data */ - (void)devif_poll(&vnet->sk_dev, vnet_txpoll); + (void)devif_poll(&vnet->vn_dev, vnet_txpoll); } /**************************************************************************** @@ -475,7 +483,7 @@ static void vnet_txtimeout(int argc, uint32_t arg, ...) /* Poll the network for new XMIT data */ - (void)devif_poll(&vnet->sk_dev, vnet_txpoll); + (void)devif_poll(&vnet->vn_dev, vnet_txpoll); } /**************************************************************************** @@ -517,11 +525,11 @@ static void vnet_polltimer(int argc, uint32_t arg, ...) * progress, we will missing TCP time state updates? */ - (void)devif_timer(&vnet->sk_dev, vnet_txpoll); + (void)devif_timer(&vnet->vn_dev, vnet_txpoll); /* Setup the watchdog poll timer again */ - (void)wd_start(vnet->sk_txpoll, VNET_WDDELAY, vnet_polltimer, 1, + (void)wd_start(vnet->vn_txpoll, VNET_WDDELAY, vnet_polltimer, 1, (wdparm_t)arg); } @@ -554,10 +562,10 @@ static int vnet_ifup(struct net_driver_s *dev) /* Set and activate a timer process */ - (void)wd_start(vnet->sk_txpoll, VNET_WDDELAY, vnet_polltimer, 1, + (void)wd_start(vnet->vn_txpoll, VNET_WDDELAY, vnet_polltimer, 1, (wdparm_t)vnet); - vnet->sk_bifup = true; + vnet->vn_bifup = true; return OK; } @@ -588,7 +596,7 @@ static int vnet_ifdown(struct net_driver_s *dev) /* Cancel the TX poll timer and TX timeout timers */ - wd_cancel(vnet->sk_txpoll); + wd_cancel(vnet->vn_txpoll); /* Put the EMAC is its reset, non-operational state. This should be * a known configuration that will guarantee the vnet_ifup() always @@ -597,7 +605,7 @@ static int vnet_ifdown(struct net_driver_s *dev) /* Mark the device "down" */ - vnet->sk_bifup = false; + vnet->vn_bifup = false; leave_critical_section(flags); return OK; } @@ -634,7 +642,7 @@ static int vnet_txavail(struct net_driver_s *dev) /* Ignore the notification if the interface is not yet up */ - if (vnet->sk_bifup) + if (vnet->vn_bifup) { /* Check if there is room in the hardware to hold another outgoing packet. */ @@ -648,7 +656,7 @@ static int vnet_txavail(struct net_driver_s *dev) /* If so, then poll the network for new XMIT data */ - (void)devif_poll(&vnet->sk_dev, vnet_txpoll); + (void)devif_poll(&vnet->vn_dev, vnet_txpoll); } out: @@ -735,9 +743,10 @@ static int vnet_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac) * ****************************************************************************/ -int vnet_init(struct rgmp_vnet *vnet) +int vnet_init(FAR struct rgmp_vnet *vnet) { - struct vnet_driver_s *priv; + FAR struct vnet_driver_s *priv; + FAR uint8_t *pktbuf; static int i = 0; if (i >= CONFIG_VNET_NINTERFACES) @@ -745,30 +754,34 @@ int vnet_init(struct rgmp_vnet *vnet) return -1; } - priv = &g_vnet[i++]; + /* Get the packet buffer associated with this instance */ + + pktbuf = &g_pktbuf[PKTBUF_SIZE * i]; + priv = &g_vnet[i++]; /* Initialize the driver structure */ memset(priv, 0, sizeof(struct vnet_driver_s)); - priv->sk_dev.d_ifup = vnet_ifup; /* I/F down callback */ - priv->sk_dev.d_ifdown = vnet_ifdown; /* I/F up (new IP address) callback */ - priv->sk_dev.d_txavail = vnet_txavail; /* New TX data callback */ + priv->vn_dev.d_buf = pktbuf; /* Single packet buffer */ + priv->vn_dev.d_ifup = vnet_ifup; /* I/F down callback */ + priv->vn_dev.d_ifdown = vnet_ifdown; /* I/F up (new IP address) callback */ + priv->vn_dev.d_txavail = vnet_txavail; /* New TX data callback */ #ifdef CONFIG_NET_IGMP - priv->sk_dev.d_addmac = vnet_addmac; /* Add multicast MAC address */ - priv->sk_dev.d_rmmac = vnet_rmmac; /* Remove multicast MAC address */ + priv->vn_dev.d_addmac = vnet_addmac; /* Add multicast MAC address */ + priv->vn_dev.d_rmmac = vnet_rmmac; /* Remove multicast MAC address */ #endif - priv->sk_dev.d_private = (FAR void *)priv; /* Used to recover private state from dev */ + priv->vn_dev.d_private = (FAR void *)priv; /* Used to recover private state from dev */ /* Create a watchdog for timing polling for and timing of transmisstions */ - priv->sk_txpoll = wd_create(); /* Create periodic poll timer */ + priv->vn_txpoll = wd_create(); /* Create periodic poll timer */ priv->vnet = vnet; vnet->priv = priv; /* Register the device with the OS */ - (void)netdev_register(&priv->sk_dev), NET_LL_ETHERNET; + (void)netdev_register(&priv->vn_dev), NET_LL_ETHERNET; return 0; } -- GitLab From ca2d62f86c81ba1f8e5ab07f76ef0f7f44fa9a34 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 29 Nov 2016 16:57:19 -0600 Subject: [PATCH 554/734] arp.h: Fix some typos introduce in last big set of commits. --- include/nuttx/net/arp.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/nuttx/net/arp.h b/include/nuttx/net/arp.h index a5365ea35e..4a33994a1b 100644 --- a/include/nuttx/net/arp.h +++ b/include/nuttx/net/arp.h @@ -137,7 +137,7 @@ extern "C" ****************************************************************************/ #ifdef CONFIG_NET_ARP_IPIN -void arp_ipin(FAR struct net_driver_s **dev); +void arp_ipin(FAR struct net_driver_s *dev); #else # define arp_ipin(dev) #endif @@ -165,7 +165,7 @@ void arp_ipin(FAR struct net_driver_s **dev); * ****************************************************************************/ -void arp_arpin(FAR struct net_driver_s **dev); +void arp_arpin(FAR struct net_driver_s *dev); /**************************************************************************** * Name: arp_out -- GitLab From b29b77532f44111f4eed8fe186ab9f7a0b9dd33e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 29 Nov 2016 18:17:37 -0600 Subject: [PATCH 555/734] Update some comments --- arch/misoc/src/common/misoc_net.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/misoc/src/common/misoc_net.c b/arch/misoc/src/common/misoc_net.c index 8854616266..1174598318 100644 --- a/arch/misoc/src/common/misoc_net.c +++ b/arch/misoc/src/common/misoc_net.c @@ -236,6 +236,11 @@ static int misoc_net_transmit(FAR struct misoc_net_driver_s *priv) /* Send the packet: address=priv->misoc_net_dev.d_buf, * length=priv->misoc_net_dev.d_len + * + * NOTE: This memcpy could be avoided by setting tx_buf + * to the d_buf pointer and setting d_buf to an alternate + * buffer. Some additional buffer management logic would + * be required. */ memcpy(priv->tx_buf, priv->misoc_net_dev.d_buf, @@ -395,6 +400,10 @@ static void misoc_net_receive(FAR struct misoc_net_driver_s *priv) /* Copy the data data from the hardware to priv->misoc_net_dev.d_buf. Set * amount of data in priv->misoc_net_dev.d_len + * + * NOTE: These memcpy's could be avoided by simply setting the d_buf + * pointer to the rx*_buf containing the received data. Some additional + * buffer management logic would also be required. */ misoc_flush_dcache(); -- GitLab From 8453343426244a019b810c1d4cb7b6f79ea82e56 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 30 Nov 2016 07:24:15 -0600 Subject: [PATCH 556/734] scheduler instrumentation: Add a little more protection for the SMP case --- sched/sched/sched_note.c | 40 ++++++++++++++++++++++++++++++++++------ 1 file changed, 34 insertions(+), 6 deletions(-) diff --git a/sched/sched/sched_note.c b/sched/sched/sched_note.c index 32b27b4753..8e35565c79 100644 --- a/sched/sched/sched_note.c +++ b/sched/sched/sched_note.c @@ -63,8 +63,8 @@ struct note_info_s { - unsigned int ni_head; - unsigned int ni_tail; + volatile unsigned int ni_head; + volatile unsigned int ni_tail; uint8_t ni_buffer[CONFIG_SCHED_NOTE_BUFSIZE]; }; @@ -281,6 +281,7 @@ static void note_add(FAR const uint8_t *note, uint8_t notelen) { unsigned int head; unsigned int next; + unsigned int nxthd; #ifdef CONFIG_SMP /* Ignore notes that are not in the set of monitored CPUs */ @@ -293,10 +294,37 @@ static void note_add(FAR const uint8_t *note, uint8_t notelen) } #endif - /* Get the index to the head of the circular buffer */ - DEBUGASSERT(note != NULL && notelen < CONFIG_SCHED_NOTE_BUFSIZE); - head = g_note_info.ni_head; + + do + { + /* Get the index to the head of the circular buffer */ + + head = g_note_info.ni_head; + + /* Pre-calculate the next head index. We do this in advance to + * protect note as it is written. In the single CPU case, this is not + * a problem because this logic is always called within a critical + * section, but in the SMP case we have less protection. pre- + * calculating the next head indexed does not eliminate all + * possibility of conflict; it is possible that one note could be lost + * or corrupted. But the integrity of the overal buffer should be + * retained. + */ + + nxthd = note_next(head, notelen); + + /* Write the next head. There are two possible race conditions: (1) + * some other CPU wrote the head after we fetched it above. That + * note from the other CPU will be lost (and this one may be + * corrupted), or (2) some other CPU will write the head after we + * write it and the write the same value. Again, one note will be + * lost or corrupted. + */ + + g_note_info.ni_head = nxthd; + } + while (nxthd != g_note_info.ni_head); /* Loop until all bytes have been transferred to the circular buffer */ @@ -322,7 +350,7 @@ static void note_add(FAR const uint8_t *note, uint8_t notelen) notelen--; } - g_note_info.ni_head = head; + DEBUGASSERT(head == nxthd); } /**************************************************************************** -- GitLab From e6eb2e8bfae0d1eaf7a79ff54f1f1c289794fd7f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 30 Nov 2016 07:41:48 -0600 Subject: [PATCH 557/734] Back out the last change. I just noticed some complexities that need to be verified before this is released onto the world. --- sched/sched/sched_note.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/sched/sched/sched_note.c b/sched/sched/sched_note.c index 8e35565c79..0abd56ed6a 100644 --- a/sched/sched/sched_note.c +++ b/sched/sched/sched_note.c @@ -281,7 +281,9 @@ static void note_add(FAR const uint8_t *note, uint8_t notelen) { unsigned int head; unsigned int next; +#if 0 /* Backed out for now. */ unsigned int nxthd; +#endif #ifdef CONFIG_SMP /* Ignore notes that are not in the set of monitored CPUs */ @@ -294,6 +296,11 @@ static void note_add(FAR const uint8_t *note, uint8_t notelen) } #endif +#if 0 /* Backed out for now. This could advance the head index and wrap + * past the tail index. I am not sure how this would interact with + * note_remove(). Needs time to test and verify. + */ + DEBUGASSERT(note != NULL && notelen < CONFIG_SCHED_NOTE_BUFSIZE); do @@ -325,6 +332,12 @@ static void note_add(FAR const uint8_t *note, uint8_t notelen) g_note_info.ni_head = nxthd; } while (nxthd != g_note_info.ni_head); +#else + /* Get the index to the head of the circular buffer */ + + DEBUGASSERT(note != NULL && notelen < CONFIG_SCHED_NOTE_BUFSIZE); + head = g_note_info.ni_head; +#endif /* Loop until all bytes have been transferred to the circular buffer */ @@ -350,7 +363,11 @@ static void note_add(FAR const uint8_t *note, uint8_t notelen) notelen--; } +#if 0 /* Backed out for now. */ DEBUGASSERT(head == nxthd); +#else + g_note_info.ni_head = head; +#endif } /**************************************************************************** -- GitLab From b78c3fcc303708f144733b9f905d2e3ade6b1200 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 30 Nov 2016 08:13:43 -0600 Subject: [PATCH 558/734] Finish backing out previous change --- sched/sched/sched_note.c | 59 ++++++++++------------------------------ 1 file changed, 15 insertions(+), 44 deletions(-) diff --git a/sched/sched/sched_note.c b/sched/sched/sched_note.c index 0abd56ed6a..22d87b8264 100644 --- a/sched/sched/sched_note.c +++ b/sched/sched/sched_note.c @@ -281,9 +281,6 @@ static void note_add(FAR const uint8_t *note, uint8_t notelen) { unsigned int head; unsigned int next; -#if 0 /* Backed out for now. */ - unsigned int nxthd; -#endif #ifdef CONFIG_SMP /* Ignore notes that are not in the set of monitored CPUs */ @@ -296,48 +293,26 @@ static void note_add(FAR const uint8_t *note, uint8_t notelen) } #endif -#if 0 /* Backed out for now. This could advance the head index and wrap - * past the tail index. I am not sure how this would interact with - * note_remove(). Needs time to test and verify. - */ - - DEBUGASSERT(note != NULL && notelen < CONFIG_SCHED_NOTE_BUFSIZE); - - do - { - /* Get the index to the head of the circular buffer */ - - head = g_note_info.ni_head; - - /* Pre-calculate the next head index. We do this in advance to - * protect note as it is written. In the single CPU case, this is not - * a problem because this logic is always called within a critical - * section, but in the SMP case we have less protection. pre- - * calculating the next head indexed does not eliminate all - * possibility of conflict; it is possible that one note could be lost - * or corrupted. But the integrity of the overal buffer should be - * retained. - */ - - nxthd = note_next(head, notelen); - - /* Write the next head. There are two possible race conditions: (1) - * some other CPU wrote the head after we fetched it above. That - * note from the other CPU will be lost (and this one may be - * corrupted), or (2) some other CPU will write the head after we - * write it and the write the same value. Again, one note will be - * lost or corrupted. - */ + /* REVISIT: In the single CPU case, the following should be safe because + * the logic is always called within a critical section, but in the SMP + * case we have protection. One option would be to precalculate and + * advancing the new head entry before writing the data into the buffer. + * That will eliminate fatal race conditions (although could result in + * single notes being corrupted harmlessly). + * + * But there is a complexity: Advancing the head pointer where the note + * buffer is almost full could advance the head to wrap beyond the tail + * leaving the buffer in a bad state. A solution to this would be to pre- + * remove entries at the tail of the buffer as necessary to make certain + * that there will be space for the new note at the beginning of the + * buffer. I am less certain that this can be done safely in the SMP + * case. + */ - g_note_info.ni_head = nxthd; - } - while (nxthd != g_note_info.ni_head); -#else /* Get the index to the head of the circular buffer */ DEBUGASSERT(note != NULL && notelen < CONFIG_SCHED_NOTE_BUFSIZE); head = g_note_info.ni_head; -#endif /* Loop until all bytes have been transferred to the circular buffer */ @@ -363,11 +338,7 @@ static void note_add(FAR const uint8_t *note, uint8_t notelen) notelen--; } -#if 0 /* Backed out for now. */ - DEBUGASSERT(head == nxthd); -#else g_note_info.ni_head = head; -#endif } /**************************************************************************** -- GitLab From 44668c00a0283b68ecc2ae06971bbebbc2022e50 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 30 Nov 2016 12:16:21 -0600 Subject: [PATCH 559/734] LPC17 Ethernet: Tiny, trivial, cosmetic spacing change --- arch/arm/src/lpc17xx/lpc17_ethernet.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.c b/arch/arm/src/lpc17xx/lpc17_ethernet.c index 150602b1e5..545369e055 100644 --- a/arch/arm/src/lpc17xx/lpc17_ethernet.c +++ b/arch/arm/src/lpc17xx/lpc17_ethernet.c @@ -660,6 +660,7 @@ static int lpc17_transmit(struct lpc17_driver_s *priv) prodidx = 0; } + lpc17_putreg(prodidx, LPC17_ETH_TXPRODIDX); /* Enable Tx interrupts */ -- GitLab From a03d26e88d3a33f44abcc39e7024b1168a5263dd Mon Sep 17 00:00:00 2001 From: Janne Rosberg Date: Wed, 30 Nov 2016 12:17:12 -0600 Subject: [PATCH 560/734] stm32_otghshost: if STM32F446 increase number of channels to 16 --- arch/arm/src/stm32/stm32_otghshost.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32/stm32_otghshost.c b/arch/arm/src/stm32/stm32_otghshost.c index aec4fc37d5..9dee00ae45 100644 --- a/arch/arm/src/stm32/stm32_otghshost.c +++ b/arch/arm/src/stm32/stm32_otghshost.c @@ -139,11 +139,16 @@ /* HCD Setup *******************************************************************/ /* Hardware capabilities */ -#define STM32_NHOST_CHANNELS 12 /* Number of host channels */ +#if defined(CONFIG_STM32_STM32F446) +# define STM32_NHOST_CHANNELS 16 /* Number of host channels */ +# define STM32_MAX_TX_FIFOS 16 /* Max number of TX FIFOs */ +#else +# define STM32_NHOST_CHANNELS 12 /* Number of host channels */ +# define STM32_MAX_TX_FIFOS 12 /* Max number of TX FIFOs */ +#endif #define STM32_MAX_PACKET_SIZE 64 /* Full speed max packet size */ #define STM32_EP0_DEF_PACKET_SIZE 8 /* EP0 default packet size */ #define STM32_EP0_MAX_PACKET_SIZE 64 /* EP0 HS max packet size */ -#define STM32_MAX_TX_FIFOS 12 /* Max number of TX FIFOs */ #define STM32_MAX_PKTCOUNT 256 /* Max packet count */ #define STM32_RETRY_COUNT 3 /* Number of ctrl transfer retries */ -- GitLab From 4b282f219a28485e6c086dacaf480d5116c50f47 Mon Sep 17 00:00:00 2001 From: Janne Rosberg Date: Wed, 30 Nov 2016 12:18:23 -0600 Subject: [PATCH 561/734] usbhost_composite: fix end offset in usbhost_copyinterface() --- drivers/usbhost/usbhost_composite.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usbhost/usbhost_composite.c b/drivers/usbhost/usbhost_composite.c index 64ce014250..cc60adff94 100644 --- a/drivers/usbhost/usbhost_composite.c +++ b/drivers/usbhost/usbhost_composite.c @@ -337,7 +337,7 @@ static int usbhost_copyinterface(uint8_t ifno, FAR const uint8_t *configdesc, */ for (offset += len; - offset < desclen - sizeof(struct usb_ifdesc_s); + offset <= desclen - sizeof(struct usb_epdesc_s); offset += len) { epdesc = (FAR struct usb_epdesc_s *)&configdesc[offset]; -- GitLab From 8442bf66b94d18450396b502f47771a5a45d9028 Mon Sep 17 00:00:00 2001 From: Janne Rosberg Date: Wed, 30 Nov 2016 12:20:23 -0600 Subject: [PATCH 562/734] usbhost_cdcacm: add CDC_SUBCLASS_ACM and CDC_PROTO_ATM to supported class and proto --- drivers/usbhost/usbhost_cdcacm.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/usbhost/usbhost_cdcacm.c b/drivers/usbhost/usbhost_cdcacm.c index 35610e1308..260ed25c5f 100644 --- a/drivers/usbhost/usbhost_cdcacm.c +++ b/drivers/usbhost/usbhost_cdcacm.c @@ -392,13 +392,22 @@ static bool usbhost_txempty(FAR struct uart_dev_s *uartdev); * device. */ -static const const struct usbhost_id_s g_id = +static const const struct usbhost_id_s g_id[2] = { - USB_CLASS_CDC, /* base */ - CDC_SUBCLASS_NONE, /* subclass */ - CDC_PROTO_NONE, /* proto */ - 0, /* vid */ - 0 /* pid */ + { + USB_CLASS_CDC, /* base */ + CDC_SUBCLASS_NONE, /* subclass */ + CDC_PROTO_NONE, /* proto */ + 0, /* vid */ + 0 /* pid */ + }, + { + USB_CLASS_CDC, /* base */ + CDC_SUBCLASS_ACM, /* subclass */ + CDC_PROTO_ATM, /* proto */ + 0, /* vid */ + 0 /* pid */ + } }; /* This is the USB host CDC/ACM class's registry entry */ @@ -407,8 +416,8 @@ static struct usbhost_registry_s g_cdcacm = { NULL, /* flink */ usbhost_create, /* create */ - 1, /* nids */ - &g_id /* id[] */ + 2, /* nids */ + &g_id[0] /* id[] */ }; /* Serial driver lower half interface */ -- GitLab From 8b3a6d1eca35a63c29725deb45bb5bc24361b34e Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Wed, 30 Nov 2016 14:50:32 -0600 Subject: [PATCH 563/734] LPC43 SD/MMC: Correct some git definitions on SMMC control register in lpc43_sdmmc.h --- arch/arm/src/lpc43xx/chip/lpc43_sdmmc.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/lpc43xx/chip/lpc43_sdmmc.h b/arch/arm/src/lpc43xx/chip/lpc43_sdmmc.h index 1236d82f31..05a51178fb 100644 --- a/arch/arm/src/lpc43xx/chip/lpc43_sdmmc.h +++ b/arch/arm/src/lpc43xx/chip/lpc43_sdmmc.h @@ -143,10 +143,11 @@ #define SDMMC_CTRL_CEATAINT (1 << 11) /* Bit 11: CE-ATA device interrupts enabled */ /* Bits 12-15: Reserved */ #define SDMMC_CTRL_CDVA0 (1 << 16) /* Bit 16: Controls SD_VOLT0 pin */ -#define SDMMC_CTRL_CDVA0 (1 << 17) /* Bit 17: Controls SD_VOLT1 pin */ -#define SDMMC_CTRL_CDVA0 (1 << 18) /* Bit 18: Controls SD_VOLT2 pin */ +#define SDMMC_CTRL_CDVA1 (1 << 17) /* Bit 17: Controls SD_VOLT1 pin */ +#define SDMMC_CTRL_CDVA2 (1 << 18) /* Bit 18: Controls SD_VOLT2 pin */ /* Bits 19-23: Reserved */ -#define SDMMC_CTRL_INTDMA (1 << 25) /* Bit 24: SD/MMC DMA use */ + /* Bit 24: Reserved - always write it as 0 */ +#define SDMMC_CTRL_INTDMA (1 << 25) /* Bit 25: SD/MMC DMA use */ /* Bits 26-31: Reserved */ /* Power Enable Register (PWREN) */ -- GitLab From db24f237d773131e990efa19e73c6bf09ea106b8 Mon Sep 17 00:00:00 2001 From: Sebastien Lorquet Date: Thu, 1 Dec 2016 09:00:59 -0600 Subject: [PATCH 564/734] STM32L4: Correct USART1/2 definitions. Use default mbed UART4 settings --- arch/arm/include/stm32l4/chip.h | 2 +- arch/arm/src/stm32l4/Kconfig | 18 ++++++++++++++++-- arch/arm/src/stm32l4/stm32l4_serial.c | 6 +++--- arch/arm/src/stm32l4/stm32l4_uart.h | 10 +++++----- configs/nucleo-l476rg/include/board.h | 3 +++ 5 files changed, 28 insertions(+), 11 deletions(-) diff --git a/arch/arm/include/stm32l4/chip.h b/arch/arm/include/stm32l4/chip.h index 12d7187640..9d0712b276 100644 --- a/arch/arm/include/stm32l4/chip.h +++ b/arch/arm/include/stm32l4/chip.h @@ -77,7 +77,7 @@ # define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */ # define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ # define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 4 /* UART 4-5 */ +# define STM32L4_NUART 2 /* UART 4-5 */ # define STM32L4_NUSART 3 /* USART 1-3 */ # define STM32L4_NLPUART 1 /* LPUART 1 */ # define STM32L4_NSPI 3 /* SPI1-3 */ diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index 6995a51421..9f8d6cbda1 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -44,6 +44,8 @@ config STM32L4_STM32L476XX select ARCH_HAVE_DPFPU # REVISIT select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM + select STM32L4_HAVE_USART1 + select STM32L4_HAVE_USART2 select STM32L4_HAVE_USART3 select STM32L4_HAVE_UART4 select STM32L4_HAVE_UART5 @@ -55,6 +57,8 @@ config STM32L4_STM32L486XX select ARCH_HAVE_DPFPU # REVISIT select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM + select STM32L4_HAVE_USART1 + select STM32L4_HAVE_USART2 select STM32L4_HAVE_USART3 select STM32L4_HAVE_UART4 select STM32L4_HAVE_UART5 @@ -408,15 +412,17 @@ config STM32L4_SPI3 config STM32L4_USART1 bool "USART1" default n - select USART1_SERIALDRIVER + depends on STM32L4_HAVE_USART1 select ARCH_HAVE_SERIAL_TERMIOS + select USART1_SERIALDRIVER select STM32L4_USART config STM32L4_USART2 bool "USART2" default n - select USART2_SERIALDRIVER + depends on STM32L4_HAVE_USART2 select ARCH_HAVE_SERIAL_TERMIOS + select USART2_SERIALDRIVER select STM32L4_USART config STM32L4_USART3 @@ -2517,6 +2523,14 @@ config STM32L4_DAC_DMA_BUFFER_SIZE endmenu +config STM32L4_HAVE_USART1 + bool + default n + +config STM32L4_HAVE_USART2 + bool + default n + config STM32L4_HAVE_USART3 bool default n diff --git a/arch/arm/src/stm32l4/stm32l4_serial.c b/arch/arm/src/stm32l4/stm32l4_serial.c index 8e4b8d3bee..dfef76a9b1 100644 --- a/arch/arm/src/stm32l4/stm32l4_serial.c +++ b/arch/arm/src/stm32l4/stm32l4_serial.c @@ -731,7 +731,7 @@ static struct stm32l4_serial_s g_uart5priv = /* This table lets us iterate over the configured USARTs */ -FAR static struct stm32l4_serial_s * const uart_devs[STM32L4_NUSART] = +FAR static struct stm32l4_serial_s * const uart_devs[STM32L4_NUSART+STM32L4_NUART] = { #ifdef CONFIG_STM32L4_USART1 [0] = &g_usart1priv, @@ -2407,7 +2407,7 @@ void up_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32L4_NUSART; i++) + for (i = 0; i < STM32L4_NUSART+STM32L4_NUART; i++) { if (uart_devs[i]) { @@ -2476,7 +2476,7 @@ void up_serialinit(void) strcpy(devname, "/dev/ttySx"); - for (i = 0; i < STM32L4_NUSART; i++) + for (i = 0; i < STM32L4_NUSART+STM32L4_NUART; i++) { /* Don't create a device for non-configured ports. */ diff --git a/arch/arm/src/stm32l4/stm32l4_uart.h b/arch/arm/src/stm32l4/stm32l4_uart.h index 24fc9bd313..e66302d8e4 100644 --- a/arch/arm/src/stm32l4/stm32l4_uart.h +++ b/arch/arm/src/stm32l4/stm32l4_uart.h @@ -57,19 +57,19 @@ * device. */ -#if STM32L4_NUSART < 5 || !defined(CONFIG_STM32L4_HAVE_UART5) +#if !defined(CONFIG_STM32L4_HAVE_UART5) # undef CONFIG_STM32L4_UART5 #endif -#if STM32L4_NUSART < 4 || !defined(CONFIG_STM32L4_HAVE_UART4) +#if !defined(CONFIG_STM32L4_HAVE_UART4) # undef CONFIG_STM32L4_UART4 #endif -#if STM32L4_NUSART < 3 || !defined(CONFIG_STM32L4_HAVE_USART3) +#if !defined(CONFIG_STM32L4_HAVE_USART3) # undef CONFIG_STM32L4_USART3 #endif -#if STM32L4_NUSART < 2 +#if !defined(CONFIG_STM32L4_HAVE_USART2) # undef CONFIG_STM32L4_USART2 #endif -#if STM32L4_NUSART < 1 +#if !defined(CONFIG_STM32L4_HAVE_USART1) # undef CONFIG_STM32L4_USART1 #endif diff --git a/configs/nucleo-l476rg/include/board.h b/configs/nucleo-l476rg/include/board.h index 103f5a2e00..490e5af968 100644 --- a/configs/nucleo-l476rg/include/board.h +++ b/configs/nucleo-l476rg/include/board.h @@ -102,6 +102,9 @@ #define GPIO_USART2_RTS GPIO_USART2_RTS_2 #define GPIO_USART2_CTS GPIO_USART2_CTS_2 +#define GPIO_UART4_RX GPIO_UART4_RX_1 /* PA1 */ +#define GPIO_UART4_TX GPIO_UART4_TX_1 /* PA0 */ + /* I2C * * The optional _GPIO configurations allow the I2C driver to manually -- GitLab From 6dda185e8a905df58240e2ff8682e38854148030 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 1 Dec 2016 13:28:57 -0600 Subject: [PATCH 565/734] NX: Remove configuration CONFIG_NX_NXSTART. nx_start.c is now built unconditionally in multi-user mode. --- configs/mikroe-stm32f4/fulldemo/defconfig | 1 - configs/sam3u-ek/nxwm/defconfig | 1 - configs/sam4e-ek/nxwm/defconfig | 1 - configs/sama5d3x-ek/nxwm/defconfig | 1 - configs/sama5d4-ek/nxwm/defconfig | 1 - configs/samv71-xult/nxwm/defconfig | 1 - configs/samv71-xult/vnxwm/defconfig | 1 - configs/shenzhou/nxwm/defconfig | 1 - configs/sim/nxwm/defconfig | 1 - configs/stm3210e-eval/nxterm/defconfig | 1 - configs/stm3220g-eval/nxwm/defconfig | 1 - configs/stm3240g-eval/knxwm/defconfig | 1 - configs/stm3240g-eval/nxterm/defconfig | 1 - configs/stm3240g-eval/nxwm/defconfig | 1 - configs/stm3240g-eval/src/stm32_boot.c | 24 ++++++++--------------- configs/stm32f429i-disco/lcd/defconfig | 1 - graphics/Kconfig | 11 ----------- graphics/nxmu/Make.defs | 3 --- graphics/nxmu/nx_start.c | 7 +++---- include/nuttx/nx/nx.h | 5 ++++- 20 files changed, 15 insertions(+), 50 deletions(-) diff --git a/configs/mikroe-stm32f4/fulldemo/defconfig b/configs/mikroe-stm32f4/fulldemo/defconfig index d57290807f..83cce8b291 100644 --- a/configs/mikroe-stm32f4/fulldemo/defconfig +++ b/configs/mikroe-stm32f4/fulldemo/defconfig @@ -1162,7 +1162,6 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 -# CONFIG_NX_NXSTART is not set # # Memory Management diff --git a/configs/sam3u-ek/nxwm/defconfig b/configs/sam3u-ek/nxwm/defconfig index 1aa256be23..a838cbbef3 100644 --- a/configs/sam3u-ek/nxwm/defconfig +++ b/configs/sam3u-ek/nxwm/defconfig @@ -782,7 +782,6 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 -# CONFIG_NX_NXSTART is not set # # Memory Management diff --git a/configs/sam4e-ek/nxwm/defconfig b/configs/sam4e-ek/nxwm/defconfig index 06934765a9..c388946f72 100644 --- a/configs/sam4e-ek/nxwm/defconfig +++ b/configs/sam4e-ek/nxwm/defconfig @@ -1054,7 +1054,6 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 -# CONFIG_NX_NXSTART is not set # # Memory Management diff --git a/configs/sama5d3x-ek/nxwm/defconfig b/configs/sama5d3x-ek/nxwm/defconfig index d041a39707..cae9776438 100644 --- a/configs/sama5d3x-ek/nxwm/defconfig +++ b/configs/sama5d3x-ek/nxwm/defconfig @@ -853,7 +853,6 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 -# CONFIG_NX_NXSTART is not set # # Memory Management diff --git a/configs/sama5d4-ek/nxwm/defconfig b/configs/sama5d4-ek/nxwm/defconfig index c3f7f7e16a..16124e587c 100644 --- a/configs/sama5d4-ek/nxwm/defconfig +++ b/configs/sama5d4-ek/nxwm/defconfig @@ -1146,7 +1146,6 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 -# CONFIG_NX_NXSTART is not set # # Memory Management diff --git a/configs/samv71-xult/nxwm/defconfig b/configs/samv71-xult/nxwm/defconfig index 033561fc58..b3763ac745 100644 --- a/configs/samv71-xult/nxwm/defconfig +++ b/configs/samv71-xult/nxwm/defconfig @@ -898,7 +898,6 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 -# CONFIG_NX_NXSTART is not set # # Memory Management diff --git a/configs/samv71-xult/vnxwm/defconfig b/configs/samv71-xult/vnxwm/defconfig index 9ad4941d6e..6a5cce92ce 100644 --- a/configs/samv71-xult/vnxwm/defconfig +++ b/configs/samv71-xult/vnxwm/defconfig @@ -1040,7 +1040,6 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 -# CONFIG_NX_NXSTART is not set CONFIG_VNCSERVER=y # CONFIG_VNCSERVER_PROTO3p3 is not set CONFIG_VNCSERVER_PROTO3p8=y diff --git a/configs/shenzhou/nxwm/defconfig b/configs/shenzhou/nxwm/defconfig index b486a69964..fec63ca1bf 100644 --- a/configs/shenzhou/nxwm/defconfig +++ b/configs/shenzhou/nxwm/defconfig @@ -1220,7 +1220,6 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 -# CONFIG_NX_NXSTART is not set # # Memory Management diff --git a/configs/sim/nxwm/defconfig b/configs/sim/nxwm/defconfig index 68ad712147..bb03dfb47b 100644 --- a/configs/sim/nxwm/defconfig +++ b/configs/sim/nxwm/defconfig @@ -519,7 +519,6 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 -# CONFIG_NX_NXSTART is not set # # Memory Management diff --git a/configs/stm3210e-eval/nxterm/defconfig b/configs/stm3210e-eval/nxterm/defconfig index 2733e516ea..0bf17efa49 100644 --- a/configs/stm3210e-eval/nxterm/defconfig +++ b/configs/stm3210e-eval/nxterm/defconfig @@ -1024,7 +1024,6 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 -# CONFIG_NX_NXSTART is not set # # Memory Management diff --git a/configs/stm3220g-eval/nxwm/defconfig b/configs/stm3220g-eval/nxwm/defconfig index c1097ac55b..27fc76713d 100644 --- a/configs/stm3220g-eval/nxwm/defconfig +++ b/configs/stm3220g-eval/nxwm/defconfig @@ -1248,7 +1248,6 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 -# CONFIG_NX_NXSTART is not set # # Memory Management diff --git a/configs/stm3240g-eval/knxwm/defconfig b/configs/stm3240g-eval/knxwm/defconfig index a8f21ca593..364413a4fa 100644 --- a/configs/stm3240g-eval/knxwm/defconfig +++ b/configs/stm3240g-eval/knxwm/defconfig @@ -1056,7 +1056,6 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 -CONFIG_NX_NXSTART=y # CONFIG_NXSTART_EXTERNINIT is not set CONFIG_NXSTART_SERVERPRIO=110 CONFIG_NXSTART_SERVERSTACK=1596 diff --git a/configs/stm3240g-eval/nxterm/defconfig b/configs/stm3240g-eval/nxterm/defconfig index 3acf60bb0b..dad2e32b82 100644 --- a/configs/stm3240g-eval/nxterm/defconfig +++ b/configs/stm3240g-eval/nxterm/defconfig @@ -1204,7 +1204,6 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 -# CONFIG_NX_NXSTART is not set # # Memory Management diff --git a/configs/stm3240g-eval/nxwm/defconfig b/configs/stm3240g-eval/nxwm/defconfig index d84d697338..ca57da68e3 100644 --- a/configs/stm3240g-eval/nxwm/defconfig +++ b/configs/stm3240g-eval/nxwm/defconfig @@ -1245,7 +1245,6 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 -# CONFIG_NX_NXSTART is not set # # Memory Management diff --git a/configs/stm3240g-eval/src/stm32_boot.c b/configs/stm3240g-eval/src/stm32_boot.c index bfab437e4a..61daf3d2d7 100644 --- a/configs/stm3240g-eval/src/stm32_boot.c +++ b/configs/stm3240g-eval/src/stm32_boot.c @@ -49,11 +49,11 @@ * Pre-processor Definitions ************************************************************************************/ /* Configuration ********************************************************************/ -/* Should we initialize the NX server? This is done for NxWidgets (CONFIG_NXWIDGETS=y) - * if nx_start() is available (CONFIG_NX_NXSTART=y) and if the NxWidget::CNxServer - * class expects the RTOS to do the NX initialization (CONFIG_NXWIDGET_SERVERINIT=n). - * This combination of settings is normally only used in the kernel build mode - * (CONFIG_BUILD_PROTECTED) when NxWidgets is unable to initialize NX from user-space. +/* Should we initialize the NX server using nx_start? This is done for NxWidgets + * (CONFIG_NXWIDGETS=y) and if the NxWidget::CNxServer class expects the RTOS do the + * the NX initialization (CONFIG_NXWIDGET_SERVERINIT=n). This combination of + * settings is normally only used in the kernel build mode* (CONFIG_BUILD_PROTECTED) + * when NxWidgets is unable to initialize NX from user-space. */ #undef HAVE_NXSTART @@ -62,17 +62,9 @@ # undef CONFIG_NX_START #endif -#if defined(CONFIG_NXWIDGETS) -# if defined(CONFIG_NX_NXSTART) -# if !defined(CONFIG_NXWIDGET_SERVERINIT) -# define HAVE_NXSTART -# include -# endif -# else -# if !defined(CONFIG_NXWIDGET_SERVERINIT) && defined(CONFIG_BUILD_PROTECTED) -# error CONFIG_NX_NXSTART=y is needed -# endif -# endif +#if defined(CONFIG_NXWIDGETS) && !defined(CONFIG_NXWIDGET_SERVERINIT) +# define HAVE_NXSTART +# include #endif /* Should we initialize the touchscreen for the NxWM (CONFIG_NXWM=y)? This diff --git a/configs/stm32f429i-disco/lcd/defconfig b/configs/stm32f429i-disco/lcd/defconfig index b3d098ed09..16875b0a0a 100644 --- a/configs/stm32f429i-disco/lcd/defconfig +++ b/configs/stm32f429i-disco/lcd/defconfig @@ -989,7 +989,6 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 -# CONFIG_NX_NXSTART is not set # # Memory Management diff --git a/graphics/Kconfig b/graphics/Kconfig index 02e0205229..aa6ad25258 100644 --- a/graphics/Kconfig +++ b/graphics/Kconfig @@ -691,16 +691,6 @@ config NX_MXCLIENTMSGS flooding of the client or server with too many messages (PREALLOC_MQ_MSGS controls how many messages are pre-allocated). -config NX_NXSTART - bool "nx_start()" - default n - ---help--- - If this option is selected, then the nx_start() interface will be - built. The nx_start() interface provides a single call to initialize - and start the NX server. - -if NX_NXSTART - config NXSTART_EXTERNINIT bool "External display Initialization" default n @@ -743,7 +733,6 @@ config NXSTART_VPLANE ---help--- Only a single video plane is supported. Default: 0 -endif # NX_NXSTART endif # NX_MULTIUSER source "graphics/vnc/Kconfig" diff --git a/graphics/nxmu/Make.defs b/graphics/nxmu/Make.defs index 61016426c4..9c486dd87e 100644 --- a/graphics/nxmu/Make.defs +++ b/graphics/nxmu/Make.defs @@ -38,10 +38,7 @@ ifeq ($(CONFIG_NX_MULTIUSER),y) CSRCS += nxmu_kbdin.c nxmu_mouse.c nxmu_openwindow.c nxmu_redrawreq.c CSRCS += nxmu_releasebkgd.c nxmu_requestbkgd.c nxmu_reportposition.c CSRCS += nxmu_sendclient.c nxmu_sendclientwindow.c nxmu_server.c - -ifeq ($(CONFIG_NX_NXSTART),y) CSRCS += nx_start.c -endif DEPPATH += --dep-path nxmu CFLAGS += ${shell $(INCDIR) $(INCDIROPT) "$(CC)" $(TOPDIR)/graphics/nxmu} diff --git a/graphics/nxmu/nx_start.c b/graphics/nxmu/nx_start.c index 3c3e6446d9..f6dca53b18 100644 --- a/graphics/nxmu/nx_start.c +++ b/graphics/nxmu/nx_start.c @@ -51,8 +51,6 @@ #include "nxfe.h" -#ifdef CONFIG_NX_NXSTART - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -155,6 +153,9 @@ int nx_server(int argc, char *argv[]) * work in the NuttX kernel build because the resources required by the * NX server are private to the kernel mode logic. * + * nx_start() can be called (indirectly) from applications via the + * boardctl() interface with the BOARDIOC_NX_START command. + * * Input Parameters: * None * @@ -193,5 +194,3 @@ int nx_start(void) usleep(50*1000); return OK; } - -#endif /* CONFIG_NX_NXSTART */ diff --git a/include/nuttx/nx/nx.h b/include/nuttx/nx/nx.h index 5f6c02a481..ae4fc97379 100644 --- a/include/nuttx/nx/nx.h +++ b/include/nuttx/nx/nx.h @@ -287,6 +287,9 @@ int nx_runinstance(FAR const char *mqname, FAR NX_DRIVERTYPE *dev); * work in the NuttX kernel build because the resources required by the * NX server are private to the kernel mode logic. * + * nx_start() can be called (indirectly) from applications via the + * boardctl() interface with the BOARDIOC_NX_START command. + * * Input Parameters: * None * @@ -300,7 +303,7 @@ int nx_runinstance(FAR const char *mqname, FAR NX_DRIVERTYPE *dev); * ****************************************************************************/ -#if defined(CONFIG_NX_MULTIUSER) && defined(CONFIG_NX_NXSTART) +#ifdef CONFIG_NX_MULTIUSER int nx_start(void); #endif -- GitLab From 553f6d22fc6d1dc4d64d76e1446a4d852f62a455 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 1 Dec 2016 13:52:13 -0600 Subject: [PATCH 566/734] Boardctl: Add a boardctrl() command to start the NX server. Refresh all NX configurations. --- configs/boardctl.c | 16 +++++++ configs/lm3s6965-ek/nx/defconfig | 37 +++++++++++--- configs/lm3s8962-ek/nx/defconfig | 37 +++++++++++--- configs/lpcxpresso-lpc1768/nx/defconfig | 38 +++++++++++---- configs/maple/nx/defconfig | 25 ++++++++-- configs/mikroe-stm32f4/nx/defconfig | 21 ++++++++ configs/olimex-lpc1766stk/nx/defconfig | 35 ++++++++++++-- configs/sam3u-ek/nx/defconfig | 32 +++++++++++-- configs/sama5d3x-ek/nx/defconfig | 32 +++++++++++-- configs/sim/nsh/defconfig | 64 ++++++++++++++++++------- configs/stm3210e-eval/nx/defconfig | 20 ++++++++ include/sys/boardctl.h | 21 +++++--- 12 files changed, 316 insertions(+), 62 deletions(-) diff --git a/configs/boardctl.c b/configs/boardctl.c index 749056d82a..c346cb8d01 100644 --- a/configs/boardctl.c +++ b/configs/boardctl.c @@ -48,6 +48,7 @@ #include #include #include +#include #ifdef CONFIG_BOARDCTL_USBDEVCTRL # include @@ -381,6 +382,21 @@ int boardctl(unsigned int cmd, uintptr_t arg) break; #endif +#ifdef CONFIG_NX_MULTIUSER + /* CMD: BOARDIOC_NX_START + * DESCRIPTION: Start the NX servier + * ARG: None + * CONFIGURATION: CONFIG_NX_MULTIUSER + * DEPENDENCIES: Base graphics logic provides nx_start() + */ + + case BOARDIOC_NX_START: + { + ret = nx_start(ctrl); + } + break; +#endif + #ifdef CONFIG_BOARDCTL_TSCTEST /* CMD: BOARDIOC_TSCTEST_SETUP * DESCRIPTION: Touchscreen controller test configuration diff --git a/configs/lm3s6965-ek/nx/defconfig b/configs/lm3s6965-ek/nx/defconfig index a11d8d1492..93074343d9 100644 --- a/configs/lm3s6965-ek/nx/defconfig +++ b/configs/lm3s6965-ek/nx/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -318,6 +321,7 @@ CONFIG_ARCH_LEDS=y # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -343,6 +347,7 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2010 CONFIG_START_MONTH=5 @@ -435,6 +440,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -450,21 +456,24 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y CONFIG_SPI_CMDDATA=y # CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -472,7 +481,12 @@ CONFIG_SPI_CMDDATA=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -499,6 +513,7 @@ CONFIG_P14201_FRAMEBUFFER=y # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set # CONFIG_LCD_UG9664HSWAG01 is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -580,9 +595,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -596,6 +614,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -762,6 +781,8 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -787,6 +808,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -805,9 +827,9 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set @@ -847,10 +869,9 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -890,6 +911,7 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -926,13 +948,14 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/lm3s8962-ek/nx/defconfig b/configs/lm3s8962-ek/nx/defconfig index 1dc355b04f..49d50c94fb 100644 --- a/configs/lm3s8962-ek/nx/defconfig +++ b/configs/lm3s8962-ek/nx/defconfig @@ -64,10 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -328,6 +331,7 @@ CONFIG_ARCH_LEDS=y # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -353,6 +357,7 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2010 CONFIG_START_MONTH=5 @@ -445,6 +450,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -460,21 +466,24 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y CONFIG_SPI_CMDDATA=y # CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -482,7 +491,12 @@ CONFIG_SPI_CMDDATA=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -509,6 +523,7 @@ CONFIG_P14201_FRAMEBUFFER=y # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set # CONFIG_LCD_UG9664HSWAG01 is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -590,9 +605,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -606,6 +624,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -772,6 +791,8 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -797,6 +818,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -815,9 +837,9 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set @@ -857,10 +879,9 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -900,6 +921,7 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -936,13 +958,14 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/lpcxpresso-lpc1768/nx/defconfig b/configs/lpcxpresso-lpc1768/nx/defconfig index 5cf05e397d..9bef698f03 100644 --- a/configs/lpcxpresso-lpc1768/nx/defconfig +++ b/configs/lpcxpresso-lpc1768/nx/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -144,7 +147,6 @@ CONFIG_ARMV7M_TOOLCHAIN_CODEREDL=y # CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set # CONFIG_ARMV7M_HAVE_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_LPC17_GPIOIRQ is not set # CONFIG_SERIAL_TERMIOS is not set # @@ -219,6 +221,7 @@ CONFIG_LPC17_SSP1=y # # Serial driver options # +# CONFIG_LPC17_GPIOIRQ is not set # # Architecture Options @@ -297,6 +300,7 @@ CONFIG_ARCH_LEDS=y # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -322,6 +326,7 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2011 CONFIG_START_MONTH=4 @@ -414,6 +419,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -429,21 +435,23 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set # CONFIG_SPI_EXCHANGE is not set CONFIG_SPI_CMDDATA=y # CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -451,7 +459,12 @@ CONFIG_SPI_CMDDATA=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -478,6 +491,7 @@ CONFIG_UG9664HSWAG01_SPIMODE=0 CONFIG_UG9664HSWAG01_FREQUENCY=3500000 CONFIG_UG9664HSWAG01_NINTERFACES=1 CONFIG_UG9664HSWAG01_POWER=y +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -559,9 +573,12 @@ CONFIG_UART3_2STOP=0 # CONFIG_UART3_IFLOWCONTROL is not set # CONFIG_UART3_OFLOWCONTROL is not set # CONFIG_UART3_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -575,6 +592,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -741,6 +759,8 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -766,6 +786,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -784,9 +805,9 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set @@ -826,10 +847,9 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -869,6 +889,7 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -905,13 +926,14 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/maple/nx/defconfig b/configs/maple/nx/defconfig index ec0a3a53ad..069f58bf63 100644 --- a/configs/maple/nx/defconfig +++ b/configs/maple/nx/defconfig @@ -61,10 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -349,6 +352,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y # CONFIG_STM32_HAVE_CAN2 is not set # CONFIG_STM32_HAVE_DAC1 is not set @@ -702,14 +711,14 @@ CONFIG_I2C=y # CONFIG_I2C_TRACE is not set # CONFIG_I2C_DRIVER is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set CONFIG_SPI_HWFEATURES=y -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y CONFIG_SPI_BITORDER=y # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -720,6 +729,7 @@ CONFIG_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_TIMERS_CS2100CP is not set @@ -756,6 +766,7 @@ CONFIG_LCD_MAXPOWER=1 # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set # CONFIG_LCD_UG9664HSWAG01 is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -889,6 +900,7 @@ CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial" CONFIG_HAVE_USBTRACE=y # CONFIG_USBMONITOR is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1074,6 +1086,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set # CONFIG_LIBC_LONG_LONG is not set # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=2 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1124,6 +1138,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1217,6 +1233,7 @@ CONFIG_EXAMPLES_NXHELLO_DEFAULT_FONT=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1287,6 +1304,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1362,6 +1380,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/mikroe-stm32f4/nx/defconfig b/configs/mikroe-stm32f4/nx/defconfig index e766cd139b..0fdf1f925d 100644 --- a/configs/mikroe-stm32f4/nx/defconfig +++ b/configs/mikroe-stm32f4/nx/defconfig @@ -61,10 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -349,6 +352,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -678,6 +687,8 @@ CONFIG_DISABLE_POLL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -685,6 +696,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -719,6 +731,7 @@ CONFIG_LCD_MAXPOWER=1 # CONFIG_LCD_NOKIA6100 is not set CONFIG_LCD_MIO283QT2=y # CONFIG_LCD_MIO283QT9A is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -755,6 +768,7 @@ CONFIG_LCD_LANDSCAPE=y # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -945,6 +959,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1003,6 +1019,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1084,6 +1101,7 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1154,6 +1172,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1223,6 +1242,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/olimex-lpc1766stk/nx/defconfig b/configs/olimex-lpc1766stk/nx/defconfig index a05a645c5f..311c014840 100644 --- a/configs/olimex-lpc1766stk/nx/defconfig +++ b/configs/olimex-lpc1766stk/nx/defconfig @@ -64,10 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -153,7 +156,6 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y # CONFIG_ARMV7M_OABI_TOOLCHAIN is not set # CONFIG_ARMV7M_HAVE_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_LPC17_GPIOIRQ is not set # CONFIG_SERIAL_TERMIOS is not set # @@ -228,6 +230,7 @@ CONFIG_LPC17_SSP0=y # # Serial driver options # +# CONFIG_LPC17_GPIOIRQ is not set # # Architecture Options @@ -306,6 +309,7 @@ CONFIG_ARCH_HAVE_IRQBUTTONS=y # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -331,6 +335,7 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2010 CONFIG_START_MONTH=12 @@ -423,6 +428,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -438,12 +444,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -451,7 +461,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -486,6 +501,7 @@ CONFIG_NOKIA6100_ML=0 CONFIG_NOKIA6100_RGBORD=0 # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -567,9 +583,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -583,6 +602,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -749,6 +769,8 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -774,6 +796,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -792,9 +815,10 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set @@ -834,10 +858,9 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -877,6 +900,7 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -913,13 +937,14 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sam3u-ek/nx/defconfig b/configs/sam3u-ek/nx/defconfig index 14c3f405f4..138ef32e61 100644 --- a/configs/sam3u-ek/nx/defconfig +++ b/configs/sam3u-ek/nx/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -331,6 +334,7 @@ CONFIG_ARCH_HAVE_IRQBUTTONS=y # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set # @@ -349,6 +353,7 @@ CONFIG_DISABLE_ENVIRON=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2010 CONFIG_START_MONTH=4 @@ -441,6 +446,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -456,12 +462,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -469,7 +479,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -491,6 +506,7 @@ CONFIG_LCD_MAXPOWER=31 # CONFIG_LCD_NOKIA6100 is not set # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -572,9 +588,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -588,6 +607,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -751,6 +771,8 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -776,6 +798,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -795,9 +818,9 @@ CONFIG_ARCH_HAVE_TLS=y # Examples # # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set @@ -836,10 +859,9 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -878,6 +900,7 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -914,13 +937,14 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sama5d3x-ek/nx/defconfig b/configs/sama5d3x-ek/nx/defconfig index 54bf3ccefa..80e7c9c1d5 100644 --- a/configs/sama5d3x-ek/nx/defconfig +++ b/configs/sama5d3x-ek/nx/defconfig @@ -64,10 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -411,6 +414,7 @@ CONFIG_SAMA5D3xEK_MT47H128M16RT=y # CONFIG_SAMA5D3xEK_MT47H64M16HR is not set # CONFIG_SAMA5D3xEK_NOREDLED is not set # CONFIG_SAMA5D3xEK_SLOWCLOCK is not set +# CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set # @@ -431,6 +435,7 @@ CONFIG_ARCH_HAVE_TICKLESS=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2013 CONFIG_START_MONTH=8 @@ -523,6 +528,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -538,12 +544,16 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -551,7 +561,12 @@ CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -624,9 +639,12 @@ CONFIG_USART1_2STOP=0 # CONFIG_USART1_IFLOWCONTROL is not set # CONFIG_USART1_OFLOWCONTROL is not set # CONFIG_USART1_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -640,6 +658,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -811,6 +830,8 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -836,6 +857,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -866,9 +888,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set @@ -903,10 +926,9 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -945,6 +967,7 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -982,7 +1005,7 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set @@ -992,6 +1015,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sim/nsh/defconfig b/configs/sim/nsh/defconfig index 5cfed7a969..47c57eb4df 100644 --- a/configs/sim/nsh/defconfig +++ b/configs/sim/nsh/defconfig @@ -16,7 +16,7 @@ CONFIG_HOST_LINUX=y # # Build Configuration # -# CONFIG_APPS_DIR="../apps" +# CONFIG_APPS_DIR="y" CONFIG_BUILD_FLAT=y # CONFIG_BUILD_2PASS is not set @@ -42,9 +42,10 @@ CONFIG_BUILD_FLAT=y # # Debug Options # +# CONFIG_DEBUG_ALERT is not set # CONFIG_DEBUG_FEATURES is not set -# CONFIG_ARCH_HAVE_HEAPCHECK is not set # CONFIG_ARCH_HAVE_STACKCHECK is not set +# CONFIG_ARCH_HAVE_HEAPCHECK is not set CONFIG_DEBUG_SYMBOLS=y # CONFIG_ARCH_HAVE_CUSTOMOPT is not set CONFIG_DEBUG_NOOPT=y @@ -57,10 +58,13 @@ CONFIG_DEBUG_NOOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set CONFIG_ARCH_SIM=y # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="sim" @@ -78,6 +82,7 @@ CONFIG_SIM_NET_HOST_ROUTE=y # CONFIG_SIM_NET_BRIDGE is not set # CONFIG_SIM_FRAMEBUFFER is not set # CONFIG_SIM_SPIFLASH is not set +# CONFIG_SIM_QSPIFLASH is not set # # Architecture Options @@ -142,11 +147,11 @@ CONFIG_ARCH_BOARD="sim" # # Common Board Options # -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_POWEROFF=y # CONFIG_BOARDCTL_UNIQUEID is not set @@ -175,6 +180,7 @@ CONFIG_ARCH_HAVE_TICKLESS=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2008 CONFIG_START_MONTH=6 @@ -187,6 +193,7 @@ CONFIG_PREALLOC_TIMERS=8 # # Tasks and Scheduling # +# CONFIG_SMP is not set # CONFIG_INIT_NONE is not set CONFIG_INIT_ENTRYPOINT=y # CONFIG_INIT_FILEPATH is not set @@ -270,6 +277,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=8192 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y CONFIG_DEV_ZERO=y +# CONFIG_DEV_URANDOM is not set CONFIG_DEV_LOOP=y # @@ -285,12 +293,16 @@ CONFIG_DEV_LOOP=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -298,7 +310,12 @@ CONFIG_DEV_LOOP=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -311,6 +328,7 @@ CONFIG_DEV_LOOP=y # # CONFIG_RGBLED is not set # CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set # CONFIG_MMCSD is not set # CONFIG_MODEM is not set # CONFIG_MTD is not set @@ -322,6 +340,8 @@ CONFIG_DEV_LOOP=y # CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y # CONFIG_16550_UART is not set # CONFIG_UART_SERIALDRIVER is not set # CONFIG_UART0_SERIALDRIVER is not set @@ -351,19 +371,26 @@ CONFIG_SERIAL=y # CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_SERIAL_DMA is not set # CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set - -# -# System Logging Device Options -# +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging # +# CONFIG_ARCH_SYSLOG is not set # CONFIG_RAMLOG is not set -# CONFIG_CONSOLE_SYSLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -417,11 +444,6 @@ CONFIG_FS_PROCFS=y # CONFIG_FS_UNIONFS is not set # CONFIG_FS_HOSTFS is not set -# -# System Logging -# -# CONFIG_SYSLOG_TIMESTAMP is not set - # # Graphics Support # @@ -472,6 +494,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -501,8 +525,10 @@ CONFIG_ARCH_HAVE_TLS=y # # Non-standard Library Support # +# CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -526,9 +552,9 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FSTEST is not set @@ -557,9 +583,9 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set @@ -612,6 +638,7 @@ CONFIG_FSUTILS_PASSWD_KEY4=0x9abcdef0 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -681,13 +708,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_POWEROFF is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -705,6 +732,7 @@ CONFIG_NSH_DISABLE_SHUTDOWN=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -764,7 +792,7 @@ CONFIG_NSH_LOGIN_FAILCOUNT=3 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set @@ -777,6 +805,8 @@ CONFIG_READLINE_MAX_EXTCMDS=64 # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set # CONFIG_SYSTEM_SYMTAB is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3210e-eval/nx/defconfig b/configs/stm3210e-eval/nx/defconfig index 65752da1c0..f124e0132a 100644 --- a/configs/stm3210e-eval/nx/defconfig +++ b/configs/stm3210e-eval/nx/defconfig @@ -65,10 +65,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -357,6 +360,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y # CONFIG_STM32_HAVE_CAN2 is not set CONFIG_STM32_HAVE_DAC1=y @@ -710,6 +719,8 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -717,6 +728,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -751,6 +763,7 @@ CONFIG_LCD_MAXPOWER=1 # CONFIG_LCD_NOKIA6100 is not set # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -870,6 +883,7 @@ CONFIG_USBDEV_MAXPOWER=100 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1050,6 +1064,8 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1094,6 +1110,8 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1176,6 +1194,7 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1219,6 +1238,7 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/include/sys/boardctl.h b/include/sys/boardctl.h index b1ebe45e8f..ff7aeec6d7 100644 --- a/include/sys/boardctl.h +++ b/include/sys/boardctl.h @@ -1,7 +1,7 @@ /**************************************************************************** * include/sys/boardctl.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -109,6 +109,12 @@ * CONFIGURATION: CONFIG_LIB_BOARDCTL && CONFIG_BOARDCTL_USBDEVCTRL * DEPENDENCIES: Board logic must provide board__initialize() * + * CMD: BOARDIOC_NX_START + * DESCRIPTION: Start the NX servier + * ARG: None + * CONFIGURATION: CONFIG_NX_MULTIUSER + * DEPENDENCIES: Base graphics logic provides nx_start() + * * CMD: BOARDIOC_TSCTEST_SETUP * DESCRIPTION: Touchscreen controller test configuration * ARG: Touch controller device minor number @@ -154,12 +160,13 @@ #define BOARDIOC_APP_SYMTAB _BOARDIOC(0x0005) #define BOARDIOC_OS_SYMTAB _BOARDIOC(0x0006) #define BOARDIOC_USBDEV_CONTROL _BOARDIOC(0x0007) -#define BOARDIOC_TSCTEST_SETUP _BOARDIOC(0x0008) -#define BOARDIOC_TSCTEST_TEARDOWN _BOARDIOC(0x0009) -#define BOARDIOC_ADCTEST_SETUP _BOARDIOC(0x000a) -#define BOARDIOC_PWMTEST_SETUP _BOARDIOC(0x000b) -#define BOARDIOC_CAN_INITIALIZE _BOARDIOC(0x000c) -#define BOARDIOC_GRAPHICS_SETUP _BOARDIOC(0x000d) +#define BOARDIOC_NX_START _BOARDIOC(0x0008) +#define BOARDIOC_TSCTEST_SETUP _BOARDIOC(0x0009) +#define BOARDIOC_TSCTEST_TEARDOWN _BOARDIOC(0x000a) +#define BOARDIOC_ADCTEST_SETUP _BOARDIOC(0x000b) +#define BOARDIOC_PWMTEST_SETUP _BOARDIOC(0x000c) +#define BOARDIOC_CAN_INITIALIZE _BOARDIOC(0x000d) +#define BOARDIOC_GRAPHICS_SETUP _BOARDIOC(0x000e) /* If CONFIG_BOARDCTL_IOCTL=y, then boad-specific commands will be support. * In this case, all commands not recognized by boardctl() will be forwarded -- GitLab From 86b5f3b9ed99de3261af7fe861a6703db702471c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 1 Dec 2016 15:05:57 -0600 Subject: [PATCH 567/734] boardctl: Add new command to start the NX server as a kernel thread. Also refresh more configurations. --- configs/boardctl.c | 2 +- configs/mikroe-stm32f4/fulldemo/defconfig | 30 ++++- configs/sam3u-ek/nxwm/defconfig | 46 +++++-- configs/sam4e-ek/nxwm/defconfig | 4 + configs/sama5d3x-ek/nxwm/defconfig | 42 ++++++- configs/sama5d4-ek/nxwm/defconfig | 5 + configs/samv71-xult/nxwm/defconfig | 25 +++- configs/samv71-xult/vnxwm/defconfig | 5 + configs/shenzhou/nxwm/defconfig | 4 + configs/sim/nsh2/defconfig | 133 ++++++++++++++++----- configs/sim/nx/defconfig | 22 +++- configs/sim/nx11/defconfig | 22 +++- configs/sim/nxwm/defconfig | 139 +++++++++++++++++----- configs/stm3210e-eval/nxterm/defconfig | 4 + configs/stm3220g-eval/nxwm/defconfig | 4 + configs/stm3240g-eval/knxwm/defconfig | 20 ++++ configs/stm3240g-eval/nxterm/defconfig | 4 + configs/stm3240g-eval/nxwm/defconfig | 4 + configs/stm32f429i-disco/lcd/defconfig | 25 ++++ configs/stm32f429i-disco/ltdc/defconfig | 24 +++- graphics/Kconfig | 8 ++ graphics/nxmu/nx_start.c | 51 +++++--- 22 files changed, 510 insertions(+), 113 deletions(-) diff --git a/configs/boardctl.c b/configs/boardctl.c index c346cb8d01..6c5cb5224d 100644 --- a/configs/boardctl.c +++ b/configs/boardctl.c @@ -392,7 +392,7 @@ int boardctl(unsigned int cmd, uintptr_t arg) case BOARDIOC_NX_START: { - ret = nx_start(ctrl); + ret = nx_start(); } break; #endif diff --git a/configs/mikroe-stm32f4/fulldemo/defconfig b/configs/mikroe-stm32f4/fulldemo/defconfig index 83cce8b291..f2a4e507ab 100644 --- a/configs/mikroe-stm32f4/fulldemo/defconfig +++ b/configs/mikroe-stm32f4/fulldemo/defconfig @@ -61,10 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -350,6 +353,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -732,14 +741,14 @@ CONFIG_RAMDISK=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set CONFIG_SPI_CALLBACK=y # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -750,6 +759,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y CONFIG_RTC_DATETIME=y CONFIG_RTC_ALARM=y @@ -804,6 +814,7 @@ CONFIG_LCD_MAXPOWER=1 CONFIG_LCD_MIO283QT2=y # CONFIG_LCD_MIO283QT9A is not set # CONFIG_LCD_UG9664HSWAG01 is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -871,6 +882,7 @@ CONFIG_M25P_SPIFREQUENCY=20000000 CONFIG_M25P_MANUFACTURER=0x1C CONFIG_M25P_MEMORY_TYPE=0x31 CONFIG_M25P_SUBSECTOR_ERASE=y +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set CONFIG_MTD_SMART=y @@ -987,6 +999,7 @@ CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial" # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1162,6 +1175,10 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 +# CONFIG_NXSTART_EXTERNINIT is not set +CONFIG_NXSTART_SERVERPRIO=110 +CONFIG_NXSTART_SERVERSTACK=2048 +CONFIG_NXSTART_DEVNO=0 # # Memory Management @@ -1240,6 +1257,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1301,6 +1320,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1407,6 +1427,7 @@ CONFIG_FSUTILS_MKSMARTFS=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1479,6 +1500,7 @@ CONFIG_NSH_DISABLE_IFUPDOWN=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1780,6 +1802,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sam3u-ek/nxwm/defconfig b/configs/sam3u-ek/nxwm/defconfig index a838cbbef3..f100066b1f 100644 --- a/configs/sam3u-ek/nxwm/defconfig +++ b/configs/sam3u-ek/nxwm/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -334,11 +337,11 @@ CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_HAVE_IRQBUTTONS=y # CONFIG_ARCH_IRQBUTTONS is not set -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -364,6 +367,7 @@ CONFIG_DISABLE_OS_API=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2013 CONFIG_START_MONTH=6 @@ -462,6 +466,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=1024 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -477,21 +482,24 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -516,7 +524,12 @@ CONFIG_ADS7843E_THRESHY=39 # CONFIG_BUTTONS is not set # CONFIG_DJOYSTICK is not set # CONFIG_AJOYSTICK is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -539,6 +552,7 @@ CONFIG_LCD_MAXPOWER=31 # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set # CONFIG_LCD_UG9664HSWAG01 is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -620,9 +634,12 @@ CONFIG_UART0_2STOP=0 # CONFIG_UART0_IFLOWCONTROL is not set # CONFIG_UART0_OFLOWCONTROL is not set # CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -636,6 +653,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -782,6 +800,10 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 +# CONFIG_NXSTART_EXTERNINIT is not set +CONFIG_NXSTART_SERVERPRIO=110 +CONFIG_NXSTART_SERVERSTACK=2048 +CONFIG_NXSTART_DEVNO=0 # # Memory Management @@ -827,6 +849,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -853,6 +877,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -879,9 +904,9 @@ CONFIG_CXX_NEWLONG=y # Examples # # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set @@ -910,10 +935,9 @@ CONFIG_CXX_NEWLONG=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -953,6 +977,7 @@ CONFIG_CXX_NEWLONG=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1017,12 +1042,12 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_LS is not set # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1039,6 +1064,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -1252,7 +1278,7 @@ CONFIG_NXWM_HEXCALCULATOR_FONTID=5 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set @@ -1262,6 +1288,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sam4e-ek/nxwm/defconfig b/configs/sam4e-ek/nxwm/defconfig index c388946f72..75684644ed 100644 --- a/configs/sam4e-ek/nxwm/defconfig +++ b/configs/sam4e-ek/nxwm/defconfig @@ -1054,6 +1054,10 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 +# CONFIG_NXSTART_EXTERNINIT is not set +CONFIG_NXSTART_SERVERPRIO=110 +CONFIG_NXSTART_SERVERSTACK=2048 +CONFIG_NXSTART_DEVNO=0 # # Memory Management diff --git a/configs/sama5d3x-ek/nxwm/defconfig b/configs/sama5d3x-ek/nxwm/defconfig index cae9776438..e27f631772 100644 --- a/configs/sama5d3x-ek/nxwm/defconfig +++ b/configs/sama5d3x-ek/nxwm/defconfig @@ -64,10 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -429,7 +432,6 @@ CONFIG_ARCH_LEDS=y CONFIG_ARCH_HAVE_BUTTONS=y # CONFIG_ARCH_BUTTONS is not set CONFIG_ARCH_HAVE_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options @@ -442,6 +444,7 @@ CONFIG_SAMA5D3xEK_MT47H128M16RT=y # CONFIG_SAMA5D3xEK_NOREDLED is not set CONFIG_SAMA5D3xEK_TSD_DEVMINOR=0 # CONFIG_SAMA5D3xEK_SLOWCLOCK is not set +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y @@ -468,6 +471,7 @@ CONFIG_ARCH_HAVE_TICKLESS=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2013 CONFIG_START_MONTH=10 @@ -566,6 +570,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=1024 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -581,12 +586,16 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set CONFIG_ANALOG=y @@ -609,7 +618,12 @@ CONFIG_INPUT=y # CONFIG_BUTTONS is not set # CONFIG_DJOYSTICK is not set # CONFIG_AJOYSTICK is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -682,9 +696,12 @@ CONFIG_USART1_2STOP=0 # CONFIG_USART1_IFLOWCONTROL is not set # CONFIG_USART1_OFLOWCONTROL is not set # CONFIG_USART1_DMA is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -698,6 +715,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -853,6 +871,11 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 +# CONFIG_NXSTART_EXTERNINIT is not set +CONFIG_NXSTART_SERVERPRIO=110 +CONFIG_NXSTART_SERVERSTACK=2048 +CONFIG_NXSTART_DISPLAYNO=0 +CONFIG_NXSTART_VPLANE=0 # # Memory Management @@ -899,6 +922,8 @@ CONFIG_LIBM=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -926,6 +951,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -957,9 +983,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # Examples # # CONFIG_EXAMPLES_ADC is not set +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set @@ -987,10 +1014,9 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -1032,6 +1058,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1097,12 +1124,12 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_LS is not set # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1119,6 +1146,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -1340,7 +1368,7 @@ CONFIG_NXWM_HEXCALCULATOR_FONTID=6 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set @@ -1350,6 +1378,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sama5d4-ek/nxwm/defconfig b/configs/sama5d4-ek/nxwm/defconfig index 16124e587c..da5f0f08c9 100644 --- a/configs/sama5d4-ek/nxwm/defconfig +++ b/configs/sama5d4-ek/nxwm/defconfig @@ -1146,6 +1146,11 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 +# CONFIG_NXSTART_EXTERNINIT is not set +CONFIG_NXSTART_SERVERPRIO=110 +CONFIG_NXSTART_SERVERSTACK=2048 +CONFIG_NXSTART_DISPLAYNO=0 +CONFIG_NXSTART_VPLANE=0 # # Memory Management diff --git a/configs/samv71-xult/nxwm/defconfig b/configs/samv71-xult/nxwm/defconfig index b3763ac745..3ba0d0986e 100644 --- a/configs/samv71-xult/nxwm/defconfig +++ b/configs/samv71-xult/nxwm/defconfig @@ -64,10 +64,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -195,6 +198,7 @@ CONFIG_ARCH_CHIP_SAMV71Q=y # CONFIG_ARCH_CHIP_SAMV71J is not set # CONFIG_SAMV7_MCAN is not set CONFIG_SAMV7_HAVE_MCAN1=y +# CONFIG_SAMV7_DAC is not set CONFIG_SAMV7_HAVE_DAC1=y CONFIG_SAMV7_HAVE_EBI=y # CONFIG_SAMV7_EMAC is not set @@ -527,15 +531,15 @@ CONFIG_I2C=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y # CONFIG_SPI_CS_CONTROL is not set -# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set # CONFIG_SPI_BITBANG is not set @@ -545,6 +549,7 @@ CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_TIMERS_CS2100CP is not set @@ -592,6 +597,7 @@ CONFIG_LCD_MAXPOWER=1 # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set # CONFIG_LCD_UG9664HSWAG01 is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -661,6 +667,7 @@ CONFIG_AT25_SPIFREQUENCY=20000000 # CONFIG_MTD_AT45DB is not set # CONFIG_MTD_IS25XP is not set # CONFIG_MTD_M25P is not set +# CONFIG_MTD_MX25L is not set # CONFIG_MTD_S25FL1 is not set # CONFIG_MTD_N25QXXX is not set # CONFIG_MTD_SMART is not set @@ -730,6 +737,7 @@ CONFIG_USART0_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -898,6 +906,10 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 +# CONFIG_NXSTART_EXTERNINIT is not set +CONFIG_NXSTART_SERVERPRIO=110 +CONFIG_NXSTART_SERVERSTACK=2048 +CONFIG_NXSTART_DEVNO=0 # # Memory Management @@ -943,6 +955,8 @@ CONFIG_LIBM=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1004,6 +1018,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # Examples # # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1081,6 +1096,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1152,6 +1168,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1408,6 +1425,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/samv71-xult/vnxwm/defconfig b/configs/samv71-xult/vnxwm/defconfig index 6a5cce92ce..82e0de4d23 100644 --- a/configs/samv71-xult/vnxwm/defconfig +++ b/configs/samv71-xult/vnxwm/defconfig @@ -1040,6 +1040,11 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 +# CONFIG_NXSTART_EXTERNINIT is not set +CONFIG_NXSTART_SERVERPRIO=110 +CONFIG_NXSTART_SERVERSTACK=2048 +CONFIG_NXSTART_DISPLAYNO=0 +CONFIG_NXSTART_VPLANE=0 CONFIG_VNCSERVER=y # CONFIG_VNCSERVER_PROTO3p3 is not set CONFIG_VNCSERVER_PROTO3p8=y diff --git a/configs/shenzhou/nxwm/defconfig b/configs/shenzhou/nxwm/defconfig index fec63ca1bf..ccbcaa6fc0 100644 --- a/configs/shenzhou/nxwm/defconfig +++ b/configs/shenzhou/nxwm/defconfig @@ -1220,6 +1220,10 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 +# CONFIG_NXSTART_EXTERNINIT is not set +CONFIG_NXSTART_SERVERPRIO=110 +CONFIG_NXSTART_SERVERSTACK=2048 +CONFIG_NXSTART_DEVNO=0 # # Memory Management diff --git a/configs/sim/nsh2/defconfig b/configs/sim/nsh2/defconfig index c4f2dd0060..2c022f2917 100644 --- a/configs/sim/nsh2/defconfig +++ b/configs/sim/nsh2/defconfig @@ -37,13 +37,15 @@ CONFIG_BUILD_FLAT=y # CONFIG_ARCH_MATH_H is not set # CONFIG_ARCH_FLOAT_H is not set # CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set # # Debug Options # +# CONFIG_DEBUG_ALERT is not set # CONFIG_DEBUG_FEATURES is not set -# CONFIG_ARCH_HAVE_HEAPCHECK is not set # CONFIG_ARCH_HAVE_STACKCHECK is not set +# CONFIG_ARCH_HAVE_HEAPCHECK is not set CONFIG_DEBUG_SYMBOLS=y # CONFIG_ARCH_HAVE_CUSTOMOPT is not set CONFIG_DEBUG_NOOPT=y @@ -56,10 +58,13 @@ CONFIG_DEBUG_NOOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set CONFIG_ARCH_SIM=y # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="sim" @@ -73,6 +78,8 @@ CONFIG_HOST_X86_64=y CONFIG_SIM_X8664_SYSTEMV=y # CONFIG_SIM_X8664_MICROSOFT is not set # CONFIG_SIM_WALLTIME is not set +CONFIG_SIM_NET_HOST_ROUTE=y +# CONFIG_SIM_NET_BRIDGE is not set CONFIG_SIM_FRAMEBUFFER=y CONFIG_SIM_X11FB=y # CONFIG_SIM_X11NOSHM is not set @@ -84,6 +91,7 @@ CONFIG_SIM_TOUCHSCREEN=y # CONFIG_SIM_NOINPUT is not set # CONFIG_SIM_TCNWAITERS is not set # CONFIG_SIM_SPIFLASH is not set +# CONFIG_SIM_QSPIFLASH is not set # # Architecture Options @@ -96,6 +104,7 @@ CONFIG_SIM_TOUCHSCREEN=y # CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set # CONFIG_ARCH_HAVE_ADDRENV is not set # CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +CONFIG_ARCH_HAVE_MULTICPU=y # CONFIG_ARCH_HAVE_VFORK is not set # CONFIG_ARCH_HAVE_MMU is not set # CONFIG_ARCH_HAVE_MPU is not set @@ -147,12 +156,12 @@ CONFIG_ARCH_BOARD="sim" # # Common Board Options # -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # CONFIG_EXAMPLES_TOUCHSCREEN_BGCOLOR=0x007b68ee +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_POWEROFF is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -180,6 +189,7 @@ CONFIG_ARCH_HAVE_TICKLESS=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2011 CONFIG_START_MONTH=10 @@ -192,6 +202,7 @@ CONFIG_PREALLOC_TIMERS=8 # # Tasks and Scheduling # +# CONFIG_SMP is not set # CONFIG_INIT_NONE is not set CONFIG_INIT_ENTRYPOINT=y # CONFIG_INIT_FILEPATH is not set @@ -242,9 +253,10 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +# CONFIG_MODULE is not set # -# Work Queue Support +# Work queue support # # CONFIG_SCHED_WORKQUEUE is not set # CONFIG_SCHED_HPWORK is not set @@ -265,6 +277,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=8192 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -280,12 +293,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -302,8 +319,27 @@ CONFIG_INPUT=y # CONFIG_BUTTONS is not set # CONFIG_DJOYSTICK is not set # CONFIG_AJOYSTICK is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# # CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set # CONFIG_MMCSD is not set +# CONFIG_MODEM is not set # CONFIG_MTD is not set # CONFIG_EEPROM is not set # CONFIG_PIPES is not set @@ -313,6 +349,8 @@ CONFIG_INPUT=y # CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y # CONFIG_16550_UART is not set # CONFIG_UART_SERIALDRIVER is not set # CONFIG_UART0_SERIALDRIVER is not set @@ -336,29 +374,32 @@ CONFIG_SERIAL=y # CONFIG_USART7_SERIALDRIVER is not set # CONFIG_USART8_SERIALDRIVER is not set # CONFIG_OTHER_UART_SERIALDRIVER is not set - -# -# USART Configuration -# # CONFIG_MCU_SERIAL is not set # CONFIG_STANDARD_SERIAL is not set # CONFIG_SERIAL_IFLOWCONTROL is not set # CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_SERIAL_DMA is not set # CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set - -# -# System Logging Device Options -# +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging # +# CONFIG_ARCH_SYSLOG is not set # CONFIG_RAMLOG is not set -# CONFIG_CONSOLE_SYSLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -391,13 +432,16 @@ CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FAT_MAXFNAME=32 # CONFIG_FS_FATTIME is not set +# CONFIG_FAT_FORCE_INDIRECT is not set # CONFIG_FAT_DMAMEMORY is not set +# CONFIG_FAT_DIRECT_RETRY is not set # CONFIG_FS_NXFFS is not set CONFIG_FS_ROMFS=y # CONFIG_FS_TMPFS is not set # CONFIG_FS_SMARTFS is not set # CONFIG_FS_BINFS is not set CONFIG_FS_PROCFS=y +# CONFIG_FS_PROCFS_REGISTER is not set # # Exclude individual procfs entries @@ -408,11 +452,6 @@ CONFIG_FS_PROCFS=y # CONFIG_FS_UNIONFS is not set # CONFIG_FS_HOSTFS is not set -# -# System Logging -# -# CONFIG_SYSLOG_TIMESTAMP is not set - # # Graphics Support # @@ -421,6 +460,7 @@ CONFIG_NX_NPLANES=1 CONFIG_NX_BGCOLOR=0x0 # CONFIG_NX_ANTIALIASING is not set # CONFIG_NX_WRITEONLY is not set +# CONFIG_NX_UPDATE is not set # # Supported Pixel Depths @@ -516,6 +556,10 @@ CONFIG_MM_REGIONS=1 # # CONFIG_AUDIO is not set +# +# Wireless Support +# + # # Binary Loader # @@ -543,6 +587,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -561,14 +607,18 @@ CONFIG_ARCH_LOWPUTC=y CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_ARCH_ROMGETC is not set # CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set # CONFIG_LIBC_NETDB is not set # CONFIG_NETDB_HOSTFILE is not set # # Non-standard Library Support # +# CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -599,8 +649,9 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set +# CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set @@ -609,10 +660,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_FTPD is not set # CONFIG_EXAMPLES_HELLO is not set # CONFIG_EXAMPLES_HELLOXX is not set -# CONFIG_EXAMPLES_JSON is not set # CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set # CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set # CONFIG_EXAMPLES_MEDIA is not set # CONFIG_EXAMPLES_MM is not set # CONFIG_EXAMPLES_MODBUS is not set @@ -629,7 +680,6 @@ CONFIG_EXAMPLES_NX_BPP=32 # CONFIG_EXAMPLES_NX_RAWWINDOWS is not set CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_EXAMPLES_NX_EXTERNINIT is not set -# CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXFFS is not set CONFIG_EXAMPLES_NXHELLO=y CONFIG_EXAMPLES_NXHELLO_VPLANE=0 @@ -656,12 +706,14 @@ CONFIG_EXAMPLES_NXLINES_LINEWIDTH=16 CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=4 CONFIG_EXAMPLES_NXLINES_BPP=32 # CONFIG_EXAMPLES_NXLINES_EXTERNINIT is not set +# CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_PCA9635 is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -669,8 +721,9 @@ CONFIG_EXAMPLES_NXLINES_BPP=32 # CONFIG_EXAMPLES_SERIALRX is not set # CONFIG_EXAMPLES_SERLOOP is not set # CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART_TEST is not set # CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMP is not set # CONFIG_EXAMPLES_TCPECHO is not set # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_THTTPD is not set @@ -680,15 +733,22 @@ CONFIG_EXAMPLES_TOUCHSCREEN_MINOR=0 CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH="/dev/input0" # CONFIG_EXAMPLES_TOUCHSCREEN_MOUSE is not set CONFIG_EXAMPLES_TOUCHSCREEN_ARCHINIT=y -# CONFIG_EXAMPLES_WEBSERVER is not set # CONFIG_EXAMPLES_UNIONFS is not set # CONFIG_EXAMPLES_USBSERIAL is not set # CONFIG_EXAMPLES_USBTERM is not set # CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set # # File System Utilities # +# CONFIG_FSUTILS_INIFILE is not set +# CONFIG_FSUTILS_PASSWD is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set # # Graphics Support @@ -701,8 +761,9 @@ CONFIG_EXAMPLES_TOUCHSCREEN_ARCHINIT=y # # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_PCODE is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set # # FreeModBus @@ -713,6 +774,7 @@ CONFIG_EXAMPLES_TOUCHSCREEN_ARCHINIT=y # Network Utilities # # CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set # CONFIG_NETUTILS_FTPC is not set # CONFIG_NETUTILS_JSON is not set # CONFIG_NETUTILS_SMTP is not set @@ -721,6 +783,7 @@ CONFIG_EXAMPLES_TOUCHSCREEN_ARCHINIT=y # NSH Library # CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set # # Command Line Configuration @@ -766,12 +829,12 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -780,6 +843,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_SET is not set # CONFIG_NSH_DISABLE_SH is not set # CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set # CONFIG_NSH_DISABLE_TEST is not set # CONFIG_NSH_DISABLE_UMOUNT is not set # CONFIG_NSH_DISABLE_UNAME is not set @@ -787,6 +851,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -823,6 +888,8 @@ CONFIG_NSH_FATMOUNTPT="/tmp" CONFIG_NSH_CONSOLE=y # CONFIG_NSH_ALTCONDEV is not set CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set # # NxWidgets/NxWM @@ -837,13 +904,12 @@ CONFIG_NSH_ARCHINIT=y # # System Libraries and NSH Add-Ons # -# CONFIG_SYSTEM_FREE is not set # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set -# CONFIG_SYSTEM_INSTALL is not set -# CONFIG_LIB_HEX2BIN is not set -# CONFIG_FSUTILS_INIFILE is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set CONFIG_READLINE_HAVE_EXTMATCH=y CONFIG_SYSTEM_READLINE=y @@ -851,5 +917,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sim/nx/defconfig b/configs/sim/nx/defconfig index 24a778de8c..5474eade27 100644 --- a/configs/sim/nx/defconfig +++ b/configs/sim/nx/defconfig @@ -58,10 +58,13 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set CONFIG_ARCH_SIM=y # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="sim" @@ -83,6 +86,7 @@ CONFIG_SIM_FBHEIGHT=240 CONFIG_SIM_FBWIDTH=480 CONFIG_SIM_FBBPP=8 # CONFIG_SIM_SPIFLASH is not set +# CONFIG_SIM_QSPIFLASH is not set # # Architecture Options @@ -172,6 +176,7 @@ CONFIG_ARCH_HAVE_TICKLESS=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2008 CONFIG_START_MONTH=11 @@ -184,6 +189,7 @@ CONFIG_PREALLOC_TIMERS=8 # # Tasks and Scheduling # +# CONFIG_SMP is not set # CONFIG_INIT_NONE is not set CONFIG_INIT_ENTRYPOINT=y # CONFIG_INIT_FILEPATH is not set @@ -264,6 +270,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=8192 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -279,12 +286,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -353,10 +364,12 @@ CONFIG_SERIAL_CONSOLE=y # CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_SERIAL_DMA is not set # CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -533,6 +546,8 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -577,9 +592,9 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set @@ -612,10 +627,9 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -654,6 +668,7 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -697,6 +712,7 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sim/nx11/defconfig b/configs/sim/nx11/defconfig index 92ffa0a4ac..491fb3c438 100644 --- a/configs/sim/nx11/defconfig +++ b/configs/sim/nx11/defconfig @@ -58,10 +58,13 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set CONFIG_ARCH_SIM=y # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="sim" @@ -84,6 +87,7 @@ CONFIG_SIM_FBHEIGHT=240 CONFIG_SIM_FBWIDTH=480 CONFIG_SIM_FBBPP=32 # CONFIG_SIM_SPIFLASH is not set +# CONFIG_SIM_QSPIFLASH is not set # # Architecture Options @@ -173,6 +177,7 @@ CONFIG_ARCH_HAVE_TICKLESS=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2008 CONFIG_START_MONTH=11 @@ -185,6 +190,7 @@ CONFIG_PREALLOC_TIMERS=8 # # Tasks and Scheduling # +# CONFIG_SMP is not set # CONFIG_INIT_NONE is not set CONFIG_INIT_ENTRYPOINT=y # CONFIG_INIT_FILEPATH is not set @@ -265,6 +271,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=8192 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -280,12 +287,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -354,10 +365,12 @@ CONFIG_SERIAL_CONSOLE=y # CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_SERIAL_DMA is not set # CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -535,6 +548,8 @@ CONFIG_NUNGET_CHARS=2 # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -579,9 +594,9 @@ CONFIG_ARCH_HAVE_TLS=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set @@ -614,10 +629,9 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -656,6 +670,7 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -699,6 +714,7 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sim/nxwm/defconfig b/configs/sim/nxwm/defconfig index bb03dfb47b..e56488f3a6 100644 --- a/configs/sim/nxwm/defconfig +++ b/configs/sim/nxwm/defconfig @@ -37,13 +37,15 @@ CONFIG_BUILD_FLAT=y # CONFIG_ARCH_MATH_H is not set # CONFIG_ARCH_FLOAT_H is not set # CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set # # Debug Options # +# CONFIG_DEBUG_ALERT is not set # CONFIG_DEBUG_FEATURES is not set -# CONFIG_ARCH_HAVE_HEAPCHECK is not set # CONFIG_ARCH_HAVE_STACKCHECK is not set +# CONFIG_ARCH_HAVE_HEAPCHECK is not set CONFIG_DEBUG_SYMBOLS=y # CONFIG_ARCH_HAVE_CUSTOMOPT is not set CONFIG_DEBUG_NOOPT=y @@ -56,10 +58,13 @@ CONFIG_DEBUG_NOOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set CONFIG_ARCH_SIM=y # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="sim" @@ -73,6 +78,8 @@ CONFIG_HOST_X86_64=y CONFIG_SIM_X8664_SYSTEMV=y # CONFIG_SIM_X8664_MICROSOFT is not set # CONFIG_SIM_WALLTIME is not set +CONFIG_SIM_NET_HOST_ROUTE=y +# CONFIG_SIM_NET_BRIDGE is not set CONFIG_SIM_FRAMEBUFFER=y CONFIG_SIM_X11FB=y # CONFIG_SIM_X11NOSHM is not set @@ -80,6 +87,7 @@ CONFIG_SIM_FBHEIGHT=240 CONFIG_SIM_FBWIDTH=480 CONFIG_SIM_FBBPP=32 # CONFIG_SIM_SPIFLASH is not set +# CONFIG_SIM_QSPIFLASH is not set # # Architecture Options @@ -92,6 +100,7 @@ CONFIG_SIM_FBBPP=32 # CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set # CONFIG_ARCH_HAVE_ADDRENV is not set # CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +CONFIG_ARCH_HAVE_MULTICPU=y # CONFIG_ARCH_HAVE_VFORK is not set # CONFIG_ARCH_HAVE_MMU is not set # CONFIG_ARCH_HAVE_MPU is not set @@ -143,11 +152,11 @@ CONFIG_ARCH_BOARD="sim" # # Common Board Options # -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_POWEROFF is not set # CONFIG_BOARDCTL_UNIQUEID is not set @@ -175,6 +184,7 @@ CONFIG_ARCH_HAVE_TICKLESS=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2012 CONFIG_START_MONTH=5 @@ -187,6 +197,7 @@ CONFIG_PREALLOC_TIMERS=8 # # Tasks and Scheduling # +# CONFIG_SMP is not set # CONFIG_INIT_NONE is not set CONFIG_INIT_ENTRYPOINT=y # CONFIG_INIT_FILEPATH is not set @@ -230,6 +241,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_ATEXIT is not set CONFIG_SCHED_ONEXIT=y CONFIG_SCHED_ONEXIT_MAX=1 +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -245,9 +257,10 @@ CONFIG_SIG_SIGWORK=17 # CONFIG_PREALLOC_MQ_MSGS=32 CONFIG_MQ_MAXMSGSIZE=48 +# CONFIG_MODULE is not set # -# Work Queue Support +# Work queue support # CONFIG_SCHED_WORKQUEUE=y CONFIG_SCHED_HPWORK=y @@ -271,6 +284,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=8192 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -286,12 +300,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -299,8 +317,27 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# # CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set # CONFIG_MMCSD is not set +# CONFIG_MODEM is not set # CONFIG_MTD is not set # CONFIG_EEPROM is not set # CONFIG_PIPES is not set @@ -310,6 +347,8 @@ CONFIG_DEV_NULL=y # CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y # CONFIG_16550_UART is not set # CONFIG_UART_SERIALDRIVER is not set # CONFIG_UART0_SERIALDRIVER is not set @@ -333,29 +372,32 @@ CONFIG_SERIAL=y # CONFIG_USART7_SERIALDRIVER is not set # CONFIG_USART8_SERIALDRIVER is not set # CONFIG_OTHER_UART_SERIALDRIVER is not set - -# -# USART Configuration -# # CONFIG_MCU_SERIAL is not set # CONFIG_STANDARD_SERIAL is not set # CONFIG_SERIAL_IFLOWCONTROL is not set # CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_SERIAL_DMA is not set # CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set - -# -# System Logging Device Options -# +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging # +# CONFIG_ARCH_SYSLOG is not set # CONFIG_RAMLOG is not set -# CONFIG_CONSOLE_SYSLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -389,12 +431,15 @@ CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FAT_MAXFNAME=32 # CONFIG_FS_FATTIME is not set +# CONFIG_FAT_FORCE_INDIRECT is not set # CONFIG_FAT_DMAMEMORY is not set +# CONFIG_FAT_DIRECT_RETRY is not set # CONFIG_FS_NXFFS is not set CONFIG_FS_ROMFS=y # CONFIG_FS_TMPFS is not set # CONFIG_FS_SMARTFS is not set CONFIG_FS_PROCFS=y +# CONFIG_FS_PROCFS_REGISTER is not set # # Exclude individual procfs entries @@ -405,11 +450,6 @@ CONFIG_FS_PROCFS=y # CONFIG_FS_UNIONFS is not set # CONFIG_FS_HOSTFS is not set -# -# System Logging -# -# CONFIG_SYSLOG_TIMESTAMP is not set - # # Graphics Support # @@ -418,6 +458,7 @@ CONFIG_NX_NPLANES=1 CONFIG_NX_BGCOLOR=0x0 # CONFIG_NX_ANTIALIASING is not set # CONFIG_NX_WRITEONLY is not set +# CONFIG_NX_UPDATE is not set # # Supported Pixel Depths @@ -519,6 +560,11 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 +# CONFIG_NXSTART_EXTERNINIT is not set +CONFIG_NXSTART_SERVERPRIO=110 +CONFIG_NXSTART_SERVERSTACK=2048 +CONFIG_NXSTART_DISPLAYNO=0 +CONFIG_NXSTART_VPLANE=0 # # Memory Management @@ -533,6 +579,10 @@ CONFIG_MM_REGIONS=1 # # CONFIG_AUDIO is not set +# +# Wireless Support +# + # # Binary Loader # @@ -560,6 +610,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -578,14 +630,18 @@ CONFIG_ARCH_LOWPUTC=y CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_ARCH_ROMGETC is not set # CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set # CONFIG_LIBC_NETDB is not set # CONFIG_NETDB_HOSTFILE is not set # # Non-standard Library Support # +# CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -611,8 +667,9 @@ CONFIG_HAVE_CXX=y # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set +# CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set @@ -621,10 +678,10 @@ CONFIG_HAVE_CXX=y # CONFIG_EXAMPLES_FTPD is not set # CONFIG_EXAMPLES_HELLO is not set # CONFIG_EXAMPLES_HELLOXX is not set -# CONFIG_EXAMPLES_JSON is not set # CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set # CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set # CONFIG_EXAMPLES_MEDIA is not set # CONFIG_EXAMPLES_MM is not set # CONFIG_EXAMPLES_MODBUS is not set @@ -633,18 +690,18 @@ CONFIG_HAVE_CXX=y # CONFIG_EXAMPLES_NSH is not set # CONFIG_EXAMPLES_NULL is not set # CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set # CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set -# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_PCA9635 is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_QENCODER is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -653,20 +710,28 @@ CONFIG_HAVE_CXX=y # CONFIG_EXAMPLES_SERLOOP is not set # CONFIG_EXAMPLES_SLCD is not set # CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMP is not set # CONFIG_EXAMPLES_TCPECHO is not set # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_THTTPD is not set # CONFIG_EXAMPLES_TIFF is not set # CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_WEBSERVER is not set # CONFIG_EXAMPLES_UNIONFS is not set # CONFIG_EXAMPLES_USBSERIAL is not set # CONFIG_EXAMPLES_USBTERM is not set # CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set # # File System Utilities # +# CONFIG_FSUTILS_INIFILE is not set +# CONFIG_FSUTILS_PASSWD is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set # # Graphics Support @@ -679,8 +744,9 @@ CONFIG_HAVE_CXX=y # # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_PCODE is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set # # FreeModBus @@ -691,6 +757,7 @@ CONFIG_HAVE_CXX=y # Network Utilities # # CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set # CONFIG_NETUTILS_FTPC is not set # CONFIG_NETUTILS_JSON is not set # CONFIG_NETUTILS_SMTP is not set @@ -699,6 +766,7 @@ CONFIG_HAVE_CXX=y # NSH Library # CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set # # Command Line Configuration @@ -743,12 +811,12 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set # CONFIG_NSH_DISABLE_MKFATFS is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -757,6 +825,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_SET is not set # CONFIG_NSH_DISABLE_SH is not set # CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set # CONFIG_NSH_DISABLE_TEST is not set # CONFIG_NSH_DISABLE_UMOUNT is not set # CONFIG_NSH_DISABLE_UNAME is not set @@ -764,6 +833,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -800,6 +870,8 @@ CONFIG_NSH_FATMOUNTPT="/tmp" CONFIG_NSH_CONSOLE=y # CONFIG_NSH_ALTCONDEV is not set CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set # # NxWidgets/NxWM @@ -824,6 +896,7 @@ CONFIG_NXWIDGETS_LISTENERSTACK=8192 # NXWidget Configuration # CONFIG_NXWIDGETS_BPP=32 +# CONFIG_NXWIDGETS_GREYSCALE is not set CONFIG_NXWIDGETS_SIZEOFCHAR=1 # @@ -964,13 +1037,12 @@ CONFIG_NXWM_CALIBRATION_LISTENERSTACK=2048 # # System Libraries and NSH Add-Ons # -# CONFIG_SYSTEM_FREE is not set # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set -# CONFIG_SYSTEM_INSTALL is not set -# CONFIG_LIB_HEX2BIN is not set -# CONFIG_FSUTILS_INIFILE is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set CONFIG_READLINE_HAVE_EXTMATCH=y CONFIG_SYSTEM_READLINE=y @@ -978,5 +1050,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3210e-eval/nxterm/defconfig b/configs/stm3210e-eval/nxterm/defconfig index 0bf17efa49..41cd0202db 100644 --- a/configs/stm3210e-eval/nxterm/defconfig +++ b/configs/stm3210e-eval/nxterm/defconfig @@ -1024,6 +1024,10 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 +# CONFIG_NXSTART_EXTERNINIT is not set +CONFIG_NXSTART_SERVERPRIO=110 +CONFIG_NXSTART_SERVERSTACK=2048 +CONFIG_NXSTART_DEVNO=0 # # Memory Management diff --git a/configs/stm3220g-eval/nxwm/defconfig b/configs/stm3220g-eval/nxwm/defconfig index 27fc76713d..a85c3be95a 100644 --- a/configs/stm3220g-eval/nxwm/defconfig +++ b/configs/stm3220g-eval/nxwm/defconfig @@ -1248,6 +1248,10 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 +# CONFIG_NXSTART_EXTERNINIT is not set +CONFIG_NXSTART_SERVERPRIO=110 +CONFIG_NXSTART_SERVERSTACK=2048 +CONFIG_NXSTART_DEVNO=0 # # Memory Management diff --git a/configs/stm3240g-eval/knxwm/defconfig b/configs/stm3240g-eval/knxwm/defconfig index 364413a4fa..170f977e35 100644 --- a/configs/stm3240g-eval/knxwm/defconfig +++ b/configs/stm3240g-eval/knxwm/defconfig @@ -70,10 +70,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -365,6 +368,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -750,6 +759,8 @@ CONFIG_I2C_POLLED=y # CONFIG_I2C_TRACE is not set # CONFIG_I2C_DRIVER is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -757,6 +768,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set CONFIG_RTC=y CONFIG_RTC_DATETIME=y # CONFIG_RTC_ALARM is not set @@ -817,6 +829,7 @@ CONFIG_LCD_MAXPOWER=1 # CONFIG_LCD_NOKIA6100 is not set # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -903,6 +916,7 @@ CONFIG_USART3_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1106,6 +1120,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1165,6 +1181,8 @@ CONFIG_CXX_NEWLONG=y # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1239,6 +1257,7 @@ CONFIG_CXX_NEWLONG=y # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1454,6 +1473,7 @@ CONFIG_SYSTEM_READLINE=y CONFIG_READLINE_ECHO=y # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3240g-eval/nxterm/defconfig b/configs/stm3240g-eval/nxterm/defconfig index dad2e32b82..a4d3ba162c 100644 --- a/configs/stm3240g-eval/nxterm/defconfig +++ b/configs/stm3240g-eval/nxterm/defconfig @@ -1204,6 +1204,10 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 +# CONFIG_NXSTART_EXTERNINIT is not set +CONFIG_NXSTART_SERVERPRIO=110 +CONFIG_NXSTART_SERVERSTACK=2048 +CONFIG_NXSTART_DEVNO=0 # # Memory Management diff --git a/configs/stm3240g-eval/nxwm/defconfig b/configs/stm3240g-eval/nxwm/defconfig index ca57da68e3..1edbb208f3 100644 --- a/configs/stm3240g-eval/nxwm/defconfig +++ b/configs/stm3240g-eval/nxwm/defconfig @@ -1245,6 +1245,10 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 +# CONFIG_NXSTART_EXTERNINIT is not set +CONFIG_NXSTART_SERVERPRIO=110 +CONFIG_NXSTART_SERVERSTACK=2048 +CONFIG_NXSTART_DEVNO=0 # # Memory Management diff --git a/configs/stm32f429i-disco/lcd/defconfig b/configs/stm32f429i-disco/lcd/defconfig index 16875b0a0a..8e602529d8 100644 --- a/configs/stm32f429i-disco/lcd/defconfig +++ b/configs/stm32f429i-disco/lcd/defconfig @@ -62,10 +62,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -351,6 +354,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -711,6 +720,8 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -718,6 +729,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -752,6 +764,7 @@ CONFIG_LCD_MAXPOWER=1 # CONFIG_LCD_NOKIA6100 is not set # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -845,6 +858,7 @@ CONFIG_USART1_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -989,6 +1003,10 @@ CONFIG_NX_MULTIUSER=y CONFIG_NX_BLOCKING=y CONFIG_NX_MXSERVERMSGS=32 CONFIG_NX_MXCLIENTMSGS=16 +# CONFIG_NXSTART_EXTERNINIT is not set +CONFIG_NXSTART_SERVERPRIO=110 +CONFIG_NXSTART_SERVERSTACK=2048 +CONFIG_NXSTART_DEVNO=0 # # Memory Management @@ -1036,6 +1054,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1094,6 +1114,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # Examples # # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1186,6 +1207,7 @@ CONFIG_EXAMPLES_NX_NOTIFYSIGNO=4 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1256,6 +1278,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1324,6 +1347,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm32f429i-disco/ltdc/defconfig b/configs/stm32f429i-disco/ltdc/defconfig index 34a9442a1a..816844d39c 100644 --- a/configs/stm32f429i-disco/ltdc/defconfig +++ b/configs/stm32f429i-disco/ltdc/defconfig @@ -62,10 +62,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -351,6 +354,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -762,14 +771,14 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y CONFIG_SPI_CMDDATA=y # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -780,6 +789,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -870,6 +880,7 @@ CONFIG_USART1_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1066,6 +1077,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1125,6 +1138,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # Examples # # CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1207,6 +1221,7 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1277,6 +1292,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1346,6 +1362,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/graphics/Kconfig b/graphics/Kconfig index aa6ad25258..6264f3da29 100644 --- a/graphics/Kconfig +++ b/graphics/Kconfig @@ -726,6 +726,14 @@ config NXSTART_DEVNO LCD device number (in case there are more than one LCDs connected). Default: 0 +config NXSTART_DISPLAYNO + int "Display Number" + default 0 + depends on !NX_LCDDRIVER && !NXSTART_EXTERNINIT + ---help--- + Framebuffer display number (in case there are more than one framebuffers). + Default: 0 + config NXSTART_VPLANE int "Plane Number" default 0 diff --git a/graphics/nxmu/nx_start.c b/graphics/nxmu/nx_start.c index f6dca53b18..a262b28a91 100644 --- a/graphics/nxmu/nx_start.c +++ b/graphics/nxmu/nx_start.c @@ -39,6 +39,7 @@ #include +#include #include #include #include @@ -51,6 +52,12 @@ #include "nxfe.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static bool g_nxserver_started; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -114,14 +121,14 @@ int nx_server(int argc, char *argv[]) * REVISIT: display == 0 is assumed. */ - ret = up_fbinitialize(0); + ret = up_fbinitialize(CONFIG_NXSTART_DISPLAYNO); if (ret < 0) { gerr("ERROR: up_fbinitialize failed: %d\n", ret); return EXIT_FAILURE; } - dev = up_fbgetvplane(0, CONFIG_NXSTART_VPLANE); + dev = up_fbgetvplane(CONFIG_NXSTART_DISPLAYNO, CONFIG_NXSTART_VPLANE); if (!dev) { gerr("ERROR: up_fbgetvplane failed, vplane=%d\n", CONFIG_NXSTART_VPLANE); @@ -171,26 +178,34 @@ int nx_server(int argc, char *argv[]) int nx_start(void) { - pid_t server; - - /* Start the server kernel thread */ + /* Do nothing is the server has already been started */ - ginfo("Starting server task\n"); - server = kernel_thread("NX Server", CONFIG_NXSTART_SERVERPRIO, - CONFIG_NXSTART_SERVERSTACK, nx_server, NULL); - if (server < 0) + if (!g_nxserver_started) { - int errcode = errno; - DEBUGASSERT(errcode > 0); + pid_t server; - gerr("ERROR: Failed to create nx_server kernel thread: %d\n", errcode); - return -errcode; - } + /* Start the server kernel thread */ - /* Wait a bit to make sure that the server get started. NOTE that this - * operation cannot be done from the IDLE thread! - */ + ginfo("Starting server task\n"); + server = kernel_thread("NX Server", CONFIG_NXSTART_SERVERPRIO, + CONFIG_NXSTART_SERVERSTACK, nx_server, NULL); + if (server < 0) + { + int errcode = errno; + DEBUGASSERT(errcode > 0); + + gerr("ERROR: Failed to create nx_server kernel thread: %d\n", errcode); + return -errcode; + } + + g_nxserver_started = true; + + /* Wait a bit to make sure that the server get started. NOTE that + * this operation cannot be done from the IDLE thread! + */ + + usleep(50*1000); + } - usleep(50*1000); return OK; } -- GitLab From fa03fa5ea9e75a67f66a471d844f0d05321c9e1f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 1 Dec 2016 17:07:54 -0600 Subject: [PATCH 568/734] Refresh more defconfig files --- configs/compal_e99/nsh_highram/defconfig | 40 +++++++++++++++---- configs/mikroe-stm32f4/nxtext/defconfig | 21 ++++++++++ configs/sim/traveler/defconfig | 21 ++++++++-- configs/stm3240g-eval/nxterm/defconfig | 10 ++++- configs/stm32f103-minimum/jlx12864g/defconfig | 32 ++++++++++++--- configs/stm32f429i-disco/lcd/defconfig | 13 ++++-- 6 files changed, 117 insertions(+), 20 deletions(-) diff --git a/configs/compal_e99/nsh_highram/defconfig b/configs/compal_e99/nsh_highram/defconfig index 2829354372..0efcb31377 100644 --- a/configs/compal_e99/nsh_highram/defconfig +++ b/configs/compal_e99/nsh_highram/defconfig @@ -60,10 +60,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -232,12 +235,12 @@ CONFIG_ARCH_BOARD="compal_e99" # # Common Board Options # -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # CONFIG_COMPALE99_LCD_SSD1783=y +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_POWEROFF=y # CONFIG_BOARDCTL_UNIQUEID is not set @@ -263,6 +266,7 @@ CONFIG_DISABLE_MQUEUE=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2007 CONFIG_START_MONTH=2 @@ -349,6 +353,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=4096 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -364,21 +369,24 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y # CONFIG_SPI_CMDDATA is not set # CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI_DRIVER is not set +# CONFIG_SPI_BITBANG is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -386,7 +394,12 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -409,6 +422,7 @@ CONFIG_LCD_MAXPOWER=1 # CONFIG_LCD_MIO283QT2 is not set # CONFIG_LCD_MIO283QT9A is not set # CONFIG_LCD_UG9664HSWAG01 is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -475,9 +489,12 @@ CONFIG_MCU_SERIAL=y # CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set CONFIG_OTHER_SERIAL_CONSOLE=y # CONFIG_NO_SERIAL_CONSOLE is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -491,6 +508,7 @@ CONFIG_SYSLOG_SERIAL_CONSOLE=y CONFIG_SYSLOG_CONSOLE=y # CONFIG_SYSLOG_NONE is not set # CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set # # Networking Support @@ -664,6 +682,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -690,6 +710,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -713,9 +734,9 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set @@ -799,9 +820,9 @@ CONFIG_EXAMPLES_NXTEXT_PUFONTID=0 # CONFIG_EXAMPLES_NXTEXT_EXTERNINIT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set @@ -842,6 +863,7 @@ CONFIG_EXAMPLES_NXTEXT_PUFONTID=0 # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -907,13 +929,13 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_LS is not set # CONFIG_NSH_DISABLE_MB is not set # CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set # CONFIG_NSH_DISABLE_MKRD is not set # CONFIG_NSH_DISABLE_MH is not set # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_POWEROFF is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -931,6 +953,7 @@ CONFIG_NSH_DISABLE_SHUTDOWN=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -971,7 +994,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set @@ -981,6 +1004,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/mikroe-stm32f4/nxtext/defconfig b/configs/mikroe-stm32f4/nxtext/defconfig index e178ae9af5..b711838e80 100644 --- a/configs/mikroe-stm32f4/nxtext/defconfig +++ b/configs/mikroe-stm32f4/nxtext/defconfig @@ -61,10 +61,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -349,6 +352,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y CONFIG_STM32_HAVE_CAN2=y CONFIG_STM32_HAVE_DAC1=y @@ -678,6 +687,8 @@ CONFIG_DISABLE_POLL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_I2S is not set @@ -685,6 +696,7 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -719,6 +731,7 @@ CONFIG_LCD_MAXPOWER=1 # CONFIG_LCD_NOKIA6100 is not set CONFIG_LCD_MIO283QT2=y # CONFIG_LCD_MIO283QT9A is not set +# CONFIG_LCD_SH1106_OLED_132 is not set # CONFIG_LCD_UG2864HSWEG01 is not set # CONFIG_LCD_UG2832HSWEG04 is not set # CONFIG_LCD_SSD1351 is not set @@ -755,6 +768,7 @@ CONFIG_LCD_LANDSCAPE=y # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -945,6 +959,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1002,6 +1018,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CXXTEST is not set @@ -1095,6 +1112,7 @@ CONFIG_EXAMPLES_NXTEXT_DEFAULT_FONT=y # # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -1165,6 +1183,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set @@ -1233,6 +1252,8 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_TABCOMPLETION is not set # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sim/traveler/defconfig b/configs/sim/traveler/defconfig index 7ed85fbdbc..270cde215a 100644 --- a/configs/sim/traveler/defconfig +++ b/configs/sim/traveler/defconfig @@ -58,10 +58,13 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set CONFIG_ARCH_SIM=y # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="sim" @@ -87,6 +90,7 @@ CONFIG_SIM_FBBPP=32 CONFIG_SIM_AJOYSTICK=y # CONFIG_SIM_NOINPUT is not set # CONFIG_SIM_SPIFLASH is not set +# CONFIG_SIM_QSPIFLASH is not set # # Architecture Options @@ -176,6 +180,7 @@ CONFIG_ARCH_HAVE_TICKLESS=y CONFIG_USEC_PER_TICK=10000 # CONFIG_SYSTEM_TIME64 is not set # CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set # CONFIG_JULIAN_TIME is not set CONFIG_START_YEAR=2008 CONFIG_START_MONTH=11 @@ -271,6 +276,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=8192 CONFIG_DISABLE_POLL=y CONFIG_DEV_NULL=y # CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set # CONFIG_DEV_LOOP is not set # @@ -286,12 +292,16 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_I2CRESET is not set # CONFIG_I2C is not set # CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set # CONFIG_I2S is not set # # Timer Driver Support # # CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set # CONFIG_RTC is not set # CONFIG_WATCHDOG is not set # CONFIG_ANALOG is not set @@ -369,10 +379,12 @@ CONFIG_SERIAL_CONSOLE=y # CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_SERIAL_DMA is not set # CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set +# CONFIG_PSEUDOTERM is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -472,6 +484,8 @@ CONFIG_LIBM=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBC_LONG_LONG=y # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -518,9 +532,9 @@ CONFIG_ARCH_HAVE_TLS=y # Examples # # CONFIG_EXAMPLES_AJOYSTICK is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_DHCPD is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set @@ -546,10 +560,9 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_NXTEXT is not set # CONFIG_EXAMPLES_OSTEST is not set # CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set # CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set @@ -620,6 +633,7 @@ CONFIG_GRAPHICS_TRAVELER_DEBUG_LEVEL=0 # CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set # CONFIG_INTERPRETERS_PCODE is not set # @@ -663,6 +677,7 @@ CONFIG_GRAPHICS_TRAVELER_DEBUG_LEVEL=0 # CONFIG_READLINE_HAVE_EXTMATCH is not set # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_TEE is not set # CONFIG_SYSTEM_UBLOXMODEM is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3240g-eval/nxterm/defconfig b/configs/stm3240g-eval/nxterm/defconfig index a4d3ba162c..afec78eb97 100644 --- a/configs/stm3240g-eval/nxterm/defconfig +++ b/configs/stm3240g-eval/nxterm/defconfig @@ -622,7 +622,14 @@ CONFIG_STM3240G_LCD_RDSHIFT=5 # CONFIG_STM3240G_ILI9320_DISABLE is not set # CONFIG_STM3240G_ILI9325_DISABLE is not set # CONFIG_BOARD_CRASHDUMP is not set -# CONFIG_LIB_BOARDCTL is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_RESET is not set +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_ADCTEST is not set +# CONFIG_BOARDCTL_PWMTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set # # RTOS Features @@ -1374,6 +1381,7 @@ CONFIG_EXAMPLES_NXTERM=y # CONFIG_EXAMPLES_TOUCHSCREEN is not set # CONFIG_EXAMPLES_UDP is not set # CONFIG_EXAMPLES_UDPBLASTER is not set +# CONFIG_EXAMPLES_USBSERIAL is not set # CONFIG_EXAMPLES_USBTERM is not set # CONFIG_EXAMPLES_WATCHDOG is not set # CONFIG_EXAMPLES_WEBSERVER is not set diff --git a/configs/stm32f103-minimum/jlx12864g/defconfig b/configs/stm32f103-minimum/jlx12864g/defconfig index ac1ee07d2b..b74c761968 100644 --- a/configs/stm32f103-minimum/jlx12864g/defconfig +++ b/configs/stm32f103-minimum/jlx12864g/defconfig @@ -16,7 +16,7 @@ CONFIG_HOST_LINUX=y # # Build Configuration # -CONFIG_APPS_DIR="../apps" +# CONFIG_APPS_DIR="../apps" CONFIG_BUILD_FLAT=y # CONFIG_BUILD_2PASS is not set @@ -96,10 +96,13 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set # CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set # CONFIG_ARCH_Z16 is not set # CONFIG_ARCH_Z80 is not set CONFIG_ARCH="arm" @@ -385,6 +388,12 @@ CONFIG_STM32_HAVE_ADC3=y # CONFIG_STM32_HAVE_ADC2_DMA is not set # CONFIG_STM32_HAVE_ADC3_DMA is not set # CONFIG_STM32_HAVE_ADC4_DMA is not set +# CONFIG_STM32_HAVE_SDADC1 is not set +# CONFIG_STM32_HAVE_SDADC2 is not set +# CONFIG_STM32_HAVE_SDADC3 is not set +# CONFIG_STM32_HAVE_SDADC1_DMA is not set +# CONFIG_STM32_HAVE_SDADC2_DMA is not set +# CONFIG_STM32_HAVE_SDADC3_DMA is not set CONFIG_STM32_HAVE_CAN1=y # CONFIG_STM32_HAVE_CAN2 is not set # CONFIG_STM32_HAVE_DAC1 is not set @@ -574,6 +583,9 @@ CONFIG_ARCH_BOARD="stm32f103-minimum" # CONFIG_ARCH_HAVE_LEDS=y CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +# CONFIG_ARCH_BUTTONS is not set +CONFIG_ARCH_HAVE_IRQBUTTONS=y # # Board-Specific Options @@ -715,14 +727,14 @@ CONFIG_DEV_NULL=y CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set CONFIG_SPI=y +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_SLAVE is not set CONFIG_SPI_EXCHANGE=y CONFIG_SPI_CMDDATA=y # CONFIG_SPI_CALLBACK is not set # CONFIG_SPI_HWFEATURES is not set -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_SPI_BITORDER is not set # CONFIG_SPI_CS_DELAY_CONTROL is not set # CONFIG_SPI_DRIVER is not set @@ -864,6 +876,7 @@ CONFIG_USART1_2STOP=0 # CONFIG_USBHOST is not set # CONFIG_HAVE_USBTRACE is not set # CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set # # System Logging @@ -1050,6 +1063,8 @@ CONFIG_LIB_HOMEDIR="/" # CONFIG_LIBC_FLOATINGPOINT is not set # CONFIG_LIBC_LONG_LONG is not set # CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set CONFIG_LIB_RAND_ORDER=1 # CONFIG_EOL_IS_CR is not set # CONFIG_EOL_IS_LF is not set @@ -1100,6 +1115,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CCTYPE is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_DHCPD is not set @@ -1119,6 +1136,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_NRF24L01TERM is not set CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set CONFIG_EXAMPLES_NXHELLO=y CONFIG_EXAMPLES_NXHELLO_VPLANE=0 @@ -1136,13 +1154,16 @@ CONFIG_EXAMPLES_NXHELLO_DEFAULT_COLORS=y CONFIG_EXAMPLES_NXHELLO_DEFAULT_FONT=y # CONFIG_EXAMPLES_NXHELLO_EXTERNINIT is not set # CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NX is not set CONFIG_EXAMPLES_NXLINES=y CONFIG_EXAMPLES_NXLINES_VPLANE=0 CONFIG_EXAMPLES_NXLINES_DEVNO=0 # CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set +CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x00 CONFIG_EXAMPLES_NXLINES_LINEWIDTH=2 +CONFIG_EXAMPLES_NXLINES_LINECOLOR=0x00 CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=2 +CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0x00 +CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR=0x00 CONFIG_EXAMPLES_NXLINES_BPP=1 # CONFIG_EXAMPLES_NXLINES_EXTERNINIT is not set # CONFIG_EXAMPLES_NXTERM is not set @@ -1284,6 +1305,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MOUNT is not set # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set diff --git a/configs/stm32f429i-disco/lcd/defconfig b/configs/stm32f429i-disco/lcd/defconfig index 8e602529d8..d7443e529c 100644 --- a/configs/stm32f429i-disco/lcd/defconfig +++ b/configs/stm32f429i-disco/lcd/defconfig @@ -590,7 +590,14 @@ CONFIG_STM32F429I_DISCO_ILI9341_LCDDEVICE=0 CONFIG_STM32F429I_DISCO_ILI9341_SPIFREQUENCY=20000000 CONFIG_STM32F429I_DISCO_ILI9341_SPIBITS16=y # CONFIG_BOARD_CRASHDUMP is not set -# CONFIG_LIB_BOARDCTL is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_RESET is not set +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_ADCTEST is not set +# CONFIG_BOARDCTL_PWMTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set # # RTOS Features @@ -1141,13 +1148,12 @@ CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_NULL is not set CONFIG_EXAMPLES_NX=y -CONFIG_EXAMPLES_NX_VPLANE=0 -CONFIG_EXAMPLES_NX_DEVNO=0 CONFIG_EXAMPLES_NX_DEFAULT_COLORS=y CONFIG_EXAMPLES_NX_DEFAULT_FONT=y CONFIG_EXAMPLES_NX_BPP=16 # CONFIG_EXAMPLES_NX_RAWWINDOWS is not set CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 +# CONFIG_EXAMPLES_NX_EXTERNINIT is not set # # Multi-User Configuration Options @@ -1182,6 +1188,7 @@ CONFIG_EXAMPLES_NX_NOTIFYSIGNO=4 # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_TIFF is not set # CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBSERIAL is not set # CONFIG_EXAMPLES_USBTERM is not set # CONFIG_EXAMPLES_WATCHDOG is not set # CONFIG_EXAMPLES_WEBSERVER is not set -- GitLab From 241176abc33c8c1ae2844fd657f890c0c2031559 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 1 Dec 2016 17:09:08 -0600 Subject: [PATCH 569/734] Eliminate a warning --- configs/bambino-200e/src/lpc43_appinit.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/bambino-200e/src/lpc43_appinit.c b/configs/bambino-200e/src/lpc43_appinit.c index 13c51dfd81..f69023a4fe 100644 --- a/configs/bambino-200e/src/lpc43_appinit.c +++ b/configs/bambino-200e/src/lpc43_appinit.c @@ -58,6 +58,8 @@ # endif #endif +#include "bambino-200e.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -- GitLab From cd119ad54407d278de6f92b0069406c396b58e3f Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Thu, 1 Dec 2016 17:59:00 -0600 Subject: [PATCH 570/734] GPDMA driver for the LPC43xx. The GPDMA block is basically the same as the LPC17xx. Only the clock configuration is different and LPC43xx has four different DMA request sources, where LPC17xx has only two. --- arch/arm/src/lpc43xx/chip/lpc43_gpdma.h | 9 +- arch/arm/src/lpc43xx/lpc43_gpdma.c | 584 +++++++++++++++++++++++- 2 files changed, 584 insertions(+), 9 deletions(-) diff --git a/arch/arm/src/lpc43xx/chip/lpc43_gpdma.h b/arch/arm/src/lpc43xx/chip/lpc43_gpdma.h index 2139e09766..e9912534dd 100644 --- a/arch/arm/src/lpc43xx/chip/lpc43_gpdma.h +++ b/arch/arm/src/lpc43xx/chip/lpc43_gpdma.h @@ -70,12 +70,12 @@ #define LPC43_GPDMA_CONTROL_CHOFFSET 0x000c /* DMA Channel Control Register */ #define LPC43_GPDMA_CONFIG_CHOFFSET 0x0010 /* DMA Channel Configuration Register */ -#define LPC43_GPDMA_CHOFFSET(n) (0x0100 ((n) << 5)) +#define LPC43_GPDMA_CHOFFSET(n) (0x0100 + ((n) << 5)) #define LPC43_GPDMA_SRCADDR_OFFSET(n) (LPC43_GPDMA_CHOFFSET(n)+LPC43_GPDMA_SRCADDR_CHOFFSET) #define LPC43_GPDMA_DESTADDR_OFFSET(n) (LPC43_GPDMA_CHOFFSET(n)+LPC43_GPDMA_DESTADDR_CHOFFSET) #define LPC43_GPDMA_LLI_OFFSET(n) (LPC43_GPDMA_CHOFFSET(n)+LPC43_GPDMA_LLI_CHOFFSET) #define LPC43_GPDMA_CONTROL_OFFSET(n) (LPC43_GPDMA_CHOFFSET(n)+LPC43_GPDMA_CONTROL_CHOFFSET) -#define LPC43_GPDMA_CONFIG_OFFSET(n) (LPC43_GPDMA_CHOFFSET(n)+LPC43_GPDMA_CONFIG_CHOFFSET) +#define LPC43_GPDMA_CONFIG_OFFSET_(n) (LPC43_GPDMA_CHOFFSET(n)+LPC43_GPDMA_CONFIG_CHOFFSET) #define LPC43_GPDMA_SRCADDR0_OFFSET 0x0100 /* DMA Channel 0 Source Address Register */ #define LPC43_GPDMA_DESTADDR0_OFFSET 0x0104 /* DMA Channel 0 Destination Address Register */ @@ -149,7 +149,7 @@ #define LPC43_GPDMA_DESTADDR(n) (LPC43_DMA_BASE+LPC43_GPDMA_DESTADDR_OFFSET(n)) #define LPC43_GPDMA_LLI(n) (LPC43_DMA_BASE+LPC43_GPDMA_LLI_OFFSET(n)) #define LPC43_GPDMA_CONTROL(n) (LPC43_DMA_BASE+LPC43_GPDMA_CONTROL_OFFSET(n)) -#define LPC43_GPDMA_CONFIG(n) (LPC43_DMA_BASE+LPC43_GPDMA_CONFIG_OFFSET(n)) +#define LPC43_GPDMA_CONFIG_(n) (LPC43_DMA_BASE+LPC43_GPDMA_CONFIG_OFFSET_(n)) #define LPC43_GPDMA_SRCADDR0 (LPC43_DMA_BASE+LPC43_GPDMA_SRCADDR0_OFFSET) #define LPC43_GPDMA_DESTADDR0 (LPC43_DMA_BASE+LPC43_GPDMA_DESTADDR0_OFFSET) @@ -203,6 +203,9 @@ /* Common macros for DMA channel and source bit settings */ +#define DMACH_ALL (0xff) +#define LPC43_NDMACH 8 /* Eight DMA channels */ +#define LPC43_NDMAREQ (16) /* The number of DMA requests */ #define GPDMA_CHANNEL(n) (1 << (n)) /* Bits 0-7 correspond to DMA channel 0-7 */ #define GPDMA_SOURCE(n) (1 << (n)) /* Bits 0-15 correspond to DMA source 0-15 */ #define GPDMA_REQUEST(n) (1 << (n)) /* Bits 0-15 correspond to DMA request 0-15 */ diff --git a/arch/arm/src/lpc43xx/lpc43_gpdma.c b/arch/arm/src/lpc43xx/lpc43_gpdma.c index d104080a94..ab2942189c 100644 --- a/arch/arm/src/lpc43xx/lpc43_gpdma.c +++ b/arch/arm/src/lpc43xx/lpc43_gpdma.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/lpc43xx/lpc43_gpdma.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -52,11 +52,218 @@ #include "chip.h" -#include "lpc43_syscon.h" +#include "lpc43_ccu.h" +#include "lpc43_creg.h" #include "lpc43_gpdma.h" #ifdef CONFIG_LPC43_GPDMA +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure represents the state of one DMA channel */ + +struct lpc43_dmach_s +{ + uint8_t chn; /* The DMA channel number */ + bool inuse; /* True: The channel is in use */ + bool inprogress; /* True: DMA is in progress on this channel */ + uint16_t nxfrs; /* Number of bytes to transfers */ + dma_callback_t callback; /* DMA completion callback function */ + void *arg; /* Argument to pass to the callback function */ +}; + +/* This structure represents the state of the LPC43 DMA block */ + +struct lpc43_gpdma_s +{ + sem_t exclsem; /* For exclusive access to the DMA channel list */ + + /* This is the state of each DMA channel */ + + struct lpc43_dmach_s dmach[LPC43_NDMACH]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The state of the LPC43 DMA block */ + +static struct lpc43_gpdma_s g_gpdma; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* If the following value is zero, then there is no DMA in progress. This + * value is needed in the IDLE loop to determine if the IDLE loop should + * go into lower power power consumption modes. According to the LPC43xx + * User Manual: "The DMA controller can continue to work in Sleep mode, and + * has access to the peripheral SRAMs and all peripheral registers. The + * flash memory and the Main SRAM are not available in Sleep mode, they are + * disabled in order to save power." + */ + +volatile uint8_t g_dma_inprogress; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lpc43_dmainprogress + * + * Description: + * Another DMA has started. Increment the g_dma_inprogress counter. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc43_dmainprogress(struct lpc43_dmach_s *dmach) +{ + irqstate_t flags; + + /* Increment the DMA in progress counter */ + + flags = enter_critical_section(); + DEBUGASSERT(!dmach->inprogress && g_dma_inprogress < LPC43_NDMACH); + g_dma_inprogress++; + dmach->inprogress = true; + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: lpc43_dmadone + * + * Description: + * A DMA has completed. Decrement the g_dma_inprogress counter. + * + * This function is called only from lpc43_dmastop which, in turn, will be + * called either by the user directly, by the user indirectly via + * lpc43_dmafree(), or from gpdma_interrupt when the transfer completes. + * + * NOTE: In the first two cases, we must be able to handle the case where + * there is no DMA in progress and gracefully ignore the call. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void lpc43_dmadone(struct lpc43_dmach_s *dmach) +{ + irqstate_t flags; + + /* Increment the DMA in progress counter */ + + flags = enter_critical_section(); + if (dmach->inprogress) + { + DEBUGASSERT(g_dma_inprogress > 0); + dmach->inprogress = false; + g_dma_inprogress--; + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: gpdma_interrupt + * + * Description: + * The common GPDMA interrupt handler. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int gpdma_interrupt(int irq, FAR void *context) +{ + struct lpc43_dmach_s *dmach; + uint32_t regval; + uint32_t chbit; + int result; + int i; + + /* Check each DMA channel */ + + for (i = 0; i < LPC43_NDMACH; i++) + { + chbit = GPDMA_CHANNEL((uint32_t)i); + + /* Is there an interrupt pending for this channel? If the bit for + * this channel is set, that indicates that a specific DMA channel + * interrupt request is active. The request can be generated from + * either the error or terminal count interrupt requests. + */ + + regval = getreg32(LPC43_GPDMA_INTSTAT); + if ((regval & chbit) != 0) + { + /* Yes.. Is this channel assigned? Is there a callback function? */ + + dmach = &g_gpdma.dmach[i]; + if (dmach->inuse && dmach->callback) + { + /* Yes.. did an error occur? */ + + regval = getreg32(LPC43_GPDMA_INTERRSTAT); + if ((regval & chbit) != 0) + { + /* Yes.. report error status */ + + result = -EIO; + } + + /* Then this must be a terminal transfer event */ + + else + { + /* Let's make sure it is the terminal transfer event. */ + + regval = getreg32(LPC43_GPDMA_INTTCSTAT); + if ((regval & chbit) != 0) + { + result = OK; + } + + /* This should not happen */ + + else + { + result = -EINVAL; + } + } + + /* Perform the callback */ + + dmach->callback((DMA_HANDLE)dmach, dmach->arg, result); + } + + /* Disable this channel, mask any further interrupts for + * this channel, and clear any pending interrupts. + */ + + lpc43_dmastop((DMA_HANDLE)dmach); + } + } + + return OK; +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -68,12 +275,101 @@ * Initialize the GPDMA subsystem. * * Returned Value: + * Zero on success; A negated errno value on failure. + * + ****************************************************************************/ + +void weak_function up_dmainitialize(void) +{ + uint32_t regval; + int ret; + int i; + + /* Enable clocking to the GPDMA block */ + + regval = getreg32(LPC43_CCU1_M4_DMA_CFG); + regval |= CCU_CLK_CFG_RUN; + putreg32(regval, LPC43_CCU1_M4_DMA_CFG); + + /* Reset all channel configurations */ + + for (i = 0; i < LPC43_NDMACH; i++) + { + putreg32(0, LPC43_GPDMA_CONFIG_(i)); + } + + /* Clear all DMA interrupts */ + + putreg32(DMACH_ALL, LPC43_GPDMA_INTTCCLEAR); + putreg32(DMACH_ALL, LPC43_GPDMA_INTERRCLR); + + /* Initialize the DMA state structure */ + + sem_init(&g_gpdma.exclsem, 0, 1); + + for (i = 0; i < LPC43_NDMACH; i++) + { + g_gpdma.dmach[i].chn = i; /* Channel number */ + g_gpdma.dmach[i].inuse = false; /* Channel is not in-use */ + } + + /* Attach and enable the common interrupt handler */ + + ret = irq_attach(LPC43M4_IRQ_DMA, gpdma_interrupt); + if (ret == OK) + { + up_enable_irq(LPC43M4_IRQ_DMA); + } + + /* Enable the DMA controller (for little endian operation) */ + + putreg32(GPDMA_CONFIG_ENA, LPC43_GPDMA_CONFIG); +} + +/**************************************************************************** + * Name: lpc43_dmaconfigure + * + * Description: + * Configure a DMA request. Each DMA request may have four different DMA + * request sources. This associates one of the sources with a DMA request. + * + * Returned Value: * None * ****************************************************************************/ -void lpc43_dmainitilaize(void) +void lpc43_dmaconfigure(uint8_t dmarequest, uint8_t dmasrc) { + uint32_t regval; + + DEBUGASSERT(dmarequest < LPC43_NDMAREQ); + + /* Set or clear the DMASEL bit corresponding to the request number */ + + regval = getreg32(LPC43_CREG_DMAMUX); + + switch (dmasrc) + { + case 0: + regval &= ~(3 << dmarequest); + break; + + case 1: + regval &= ~(3 << dmarequest); + regval |= (1 << dmarequest); + break; + + case 2: + regval &= ~(3 << dmarequest); + regval |= (2 << dmarequest); + break; + + case 3: + regval |= (3 << dmarequest); + break; + } + + putreg32(regval, LPC43_CREG_DMAMUX); } /**************************************************************************** @@ -92,7 +388,37 @@ void lpc43_dmainitilaize(void) DMA_HANDLE lpc43_dmachannel(void) { - return NULL; + struct lpc43_dmach_s *dmach = NULL; + int ret; + int i; + + /* Get exclusive access to the GPDMA state structure */ + + do + { + ret = sem_wait(&g_gpdma.exclsem); + DEBUGASSERT(ret == 0 || errno == EINTR); + } + while (ret < 0); + + /* Find an available DMA channel */ + + for (i = 0; i < LPC43_NDMACH; i++) + { + if (!g_gpdma.dmach[i].inuse) + { + /* Found one! */ + + dmach = &g_gpdma.dmach[i]; + g_gpdma.dmach[i].inuse = true; + break; + } + } + + /* Return what we found (or not) */ + + sem_post(&g_gpdma.exclsem); + return (DMA_HANDLE)dmach; } /**************************************************************************** @@ -110,6 +436,19 @@ DMA_HANDLE lpc43_dmachannel(void) void lpc43_dmafree(DMA_HANDLE handle) { + struct lpc43_dmach_s *dmach = (DMA_HANDLE)handle; + + DEBUGASSERT(dmach && dmach->inuse); + + /* Make sure that the DMA channel was properly stopped */ + + lpc43_dmastop(handle); + + /* Mark the channel available. This is an atomic operation and needs no + * special protection. + */ + + dmach->inuse = false; } /**************************************************************************** @@ -123,7 +462,87 @@ void lpc43_dmafree(DMA_HANDLE handle) int lpc43_dmarxsetup(DMA_HANDLE handle, uint32_t control, uint32_t config, uint32_t srcaddr, uint32_t destaddr, size_t nbytes) { - return -ENOSYS; + struct lpc43_dmach_s *dmach = (DMA_HANDLE)handle; + uint32_t chbit; + uint32_t regval; + uint32_t base; + + DEBUGASSERT(dmach && dmach->inuse && nbytes < 4096); + + chbit = GPDMA_CHANNEL((uint32_t)dmach->chn); + base = LPC43_GPDMA_CHANNEL((uint32_t)dmach->chn); + + /* Put the channel in a known state. Zero disables everything */ + + putreg32(0, base + LPC43_GPDMA_CONTROL_CHOFFSET); + putreg32(0, base + LPC43_GPDMA_CONFIG_CHOFFSET); + + /* "Programming a DMA channel + * + * 1. "Choose a free DMA channel with the priority needed. DMA channel 0 + * has the highest priority and DMA channel 7 the lowest priority. + */ + + regval = getreg32(LPC43_GPDMA_ENBLDCHNS); + if ((regval & chbit) != 0) + { + /* There is an active DMA on this channel! */ + + return -EBUSY; + } + + /* 2. "Clear any pending interrupts on the channel to be used by writing + * to the DMACIntTCClear and DMACIntErrClear register. The previous + * channel operation might have left interrupt active. + */ + + putreg32(chbit, LPC43_GPDMA_INTTCCLEAR); + putreg32(chbit, LPC43_GPDMA_INTERRCLR); + + /* 3. "Write the source address into the DMACCxSrcAddr register. */ + + putreg32(srcaddr, base + LPC43_GPDMA_SRCADDR_CHOFFSET); + + /* 4. "Write the destination address into the DMACCxDestAddr register. */ + + putreg32(destaddr, base + LPC43_GPDMA_DESTADDR_CHOFFSET); + + /* 5. "Write the address of the next LLI into the DMACCxLLI register. If + * the transfer comprises of a single packet of data then 0 must be + * written into this register. + */ + + putreg32(0, base + LPC43_GPDMA_LLI_CHOFFSET); + + /* 6. "Write the control information into the DMACCxControl register." + * + * The caller provides all CONTROL register fields except for the transfer + * size which is passed as a separate parameter and for the terminal count + * interrupt enable bit which is controlled by the driver. + */ + + regval = control & ~(GPDMA_CONTROL_XFRSIZE_MASK | GPDMA_CONTROL_IE); + regval |= ((uint32_t)nbytes << GPDMA_CONTROL_XFRSIZE_SHIFT); + putreg32(regval, base + LPC43_GPDMA_CONTROL_CHOFFSET); + + /* Save the number of transfer to perform for lpc43_dmastart */ + + dmach->nxfrs = (uint16_t)nbytes; + + /* 7. "Write the channel configuration information into the DMACCxConfig + * register. If the enable bit is set then the DMA channel is + * automatically enabled." + * + * Only the SRCPER, DSTPER, and FCNTRL fields of the CONFIG register + * are provided by the caller. Little endian is assumed. + */ + + regval = config & (GPDMA_CONFIG_SRCPER_MASK | + GPDMA_CONFIG_DESTPER_MASK | + GPDMA_CONFIG_FCNTRL_MASK); + putreg32(regval, base + LPC43_GPDMA_CONFIG_CHOFFSET); + + return OK; } /**************************************************************************** @@ -136,7 +555,53 @@ int lpc43_dmarxsetup(DMA_HANDLE handle, uint32_t control, uint32_t config, int lpc43_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg) { - return -ENOSYS; + struct lpc43_dmach_s *dmach = (DMA_HANDLE)handle; + uint32_t regval; + uint32_t chbit; + uint32_t base; + + DEBUGASSERT(dmach && dmach->inuse && callback); + + /* Save the callback information */ + + dmach->callback = callback; + dmach->arg = arg; + + /* Increment the count of DMAs in-progress. This count will be + * decremented when lpc43_dmastop() is called, either by the user, + * indirectly via lpc43_dmafree(), or from gpdma_interrupt when the + * transfer completes. + */ + + lpc43_dmainprogress(dmach); + + /* Clear any pending DMA interrupts */ + + chbit = GPDMA_CHANNEL((uint32_t)dmach->chn); + putreg32(chbit, LPC43_GPDMA_INTTCCLEAR); + putreg32(chbit, LPC43_GPDMA_INTERRCLR); + + /* Enable terminal count interrupt. Note that we need to restore the + * number transfers. That is because the value has a different meaning + * when it is read. + */ + + base = LPC43_GPDMA_CHANNEL((uint32_t)dmach->chn); + regval = getreg32(base + LPC43_GPDMA_CONTROL_CHOFFSET); + regval &= ~GPDMA_CONTROL_XFRSIZE_MASK; + regval |= (GPDMA_CONTROL_IE | ((uint32_t)dmach->nxfrs << GPDMA_CONTROL_XFRSIZE_SHIFT)); + putreg32(regval, base + LPC43_GPDMA_CONTROL_CHOFFSET); + + /* Enable the channel and unmask terminal count and error interrupts. + * According to the user manual, zero masks and one unmasks (hence, + * these are really enables). + */ + + regval = getreg32(base + LPC43_GPDMA_CONFIG_CHOFFSET); + regval |= (GPDMA_CONFIG_ENA | GPDMA_CONFIG_IE | GPDMA_CONFIG_ITC); + putreg32(regval, base + LPC43_GPDMA_CONFIG_CHOFFSET); + + return OK; } /**************************************************************************** @@ -147,10 +612,40 @@ int lpc43_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg) * reset and lpc43_dmasetup() must be called before lpc43_dmastart() can be * called again * + * This function will be called either by the user directly, by the user + * indirectly via lpc43_dmafree(), or from gpdma_interrupt when the + * transfer completes. + * ****************************************************************************/ void lpc43_dmastop(DMA_HANDLE handle) { + struct lpc43_dmach_s *dmach = (DMA_HANDLE)handle; + uint32_t regaddr; + uint32_t regval; + uint32_t chbit; + + DEBUGASSERT(dmach && dmach->inuse); + + /* Disable this channel and mask any further interrupts from the channel. + * this channel. The channel is disabled by clearning the channel + * enable bit. Any outstanding data in the FIFOs is lost. + */ + + regaddr = LPC43_GPDMA_CONFIG_((uint32_t)dmach->chn); + regval = getreg32(regaddr); + regval &= ~(GPDMA_CONFIG_ENA | GPDMA_CONFIG_IE | GPDMA_CONFIG_ITC); + putreg32(regval, regaddr); + + /* Clear any pending interrupts for this channel */ + + chbit = GPDMA_CHANNEL((uint32_t)dmach->chn); + putreg32(chbit, LPC43_GPDMA_INTTCCLEAR); + putreg32(chbit, LPC43_GPDMA_INTERRCLR); + + /* Decrement the count of DMAs in progress */ + + lpc43_dmadone(dmach); } /**************************************************************************** @@ -164,6 +659,34 @@ void lpc43_dmastop(DMA_HANDLE handle) #ifdef CONFIG_DEBUG_DMA void lpc43_dmasample(DMA_HANDLE handle, struct lpc43_dmaregs_s *regs) { + struct lpc43_dmach_s *dmach = (DMA_HANDLE)handle; + uint32_t base; + + DEBUGASSERT(dmach); + + /* Sample the global DMA registers */ + + regs->gbl.intst = getreg32(LPC43_GPDMA_INTSTAT); + regs->gbl.inttcstat = getreg32(LPC43_GPDMA_INTTCSTAT); + regs->gbl.interrstat = getreg32(LPC43_GPDMA_INTERRSTAT); + regs->gbl.rawinttcstat = getreg32(LPC43_GPDMA_RAWINTTCSTAT); + regs->gbl.rawinterrstat = getreg32(LPC43_GPDMA_RAWINTERRSTAT); + regs->gbl.enbldchns = getreg32(LPC43_GPDMA_ENBLDCHNS); + regs->gbl.softbreq = getreg32(LPC43_GPDMA_SOFTBREQ); + regs->gbl.softsreq = getreg32(LPC43_GPDMA_SOFTSREQ); + regs->gbl.softlbreq = getreg32(LPC43_GPDMA_SOFTLBREQ); + regs->gbl.softlsreq = getreg32(LPC43_GPDMA_SOFTLSREQ); + regs->gbl.config = getreg32(LPC43_GPDMA_CONFIG); + regs->gbl.sync = getreg32(LPC43_GPDMA_SYNC); + + /* Sample the DMA channel registers */ + + base = LPC43_GPDMA_CHANNEL((uint32_t)dmach->chn); + regs->ch.srcaddr = getreg32(base + LPC43_GPDMA_SRCADDR_CHOFFSET); + regs->ch.destaddr = getreg32(base + LPC43_GPDMA_DESTADDR_CHOFFSET); + regs->ch.lli = getreg32(base + LPC43_GPDMA_LLI_CHOFFSET); + regs->ch.control = getreg32(base + LPC43_GPDMA_CONTROL_CHOFFSET); + regs->ch.config = getreg32(base + LPC43_GPDMA_CONFIG_CHOFFSET); } #endif /* CONFIG_DEBUG_DMA */ @@ -178,6 +701,55 @@ void lpc43_dmasample(DMA_HANDLE handle, struct lpc43_dmaregs_s *regs) #ifdef CONFIG_DEBUG_DMA void lpc43_dmadump(DMA_HANDLE handle, const struct lpc43_dmaregs_s *regs, const char *msg) { + struct lpc43_dmach_s *dmach = (DMA_HANDLE)handle; + uint32_t base; + + DEBUGASSERT(dmach); + + /* Dump the sampled global DMA registers */ + + dmainfo("Global GPDMA Registers: %s\n", msg); + dmainfo(" INTST[%08x]: %08x\n", + LPC43_GPDMA_INTSTAT, regs->gbl.intst); + dmainfo(" INTTCSTAT[%08x]: %08x\n", + LPC43_GPDMA_INTTCSTAT, regs->gbl.inttcstat); + dmainfo(" INTERRSTAT[%08x]: %08x\n", + LPC43_GPDMA_INTERRSTAT, regs->gbl.interrstat); + dmainfo(" RAWINTTCSTAT[%08x]: %08x\n", + LPC43_GPDMA_RAWINTTCSTAT, regs->gbl.rawinttcstat); + dmainfo(" RAWINTERRSTAT[%08x]: %08x\n", + LPC43_GPDMA_RAWINTERRSTAT, regs->gbl.rawinterrstat); + dmainfo(" ENBLDCHNS[%08x]: %08x\n", + LPC43_GPDMA_ENBLDCHNS, regs->gbl.enbldchns); + dmainfo(" SOFTBREQ[%08x]: %08x\n", + LPC43_GPDMA_SOFTBREQ, regs->gbl.softbreq); + dmainfo(" SOFTSREQ[%08x]: %08x\n", + LPC43_GPDMA_SOFTSREQ, regs->gbl.softsreq); + dmainfo(" SOFTLBREQ[%08x]: %08x\n", + LPC43_GPDMA_SOFTLBREQ, regs->gbl.softlbreq); + dmainfo(" SOFTLSREQ[%08x]: %08x\n", + LPC43_GPDMA_SOFTLSREQ, regs->gbl.softlsreq); + dmainfo(" CONFIG[%08x]: %08x\n", + LPC43_GPDMA_CONFIG, regs->gbl.config); + dmainfo(" SYNC[%08x]: %08x\n", + LPC43_GPDMA_SYNC, regs->gbl.sync); + + /* Dump the DMA channel registers */ + + base = LPC43_GPDMA_CHANNEL((uint32_t)dmach->chn); + + dmainfo("Channel GPDMA Registers: %d\n", dmach->chn); + + dmainfo(" SRCADDR[%08x]: %08x\n", + base + LPC43_GPDMA_SRCADDR_CHOFFSET, regs->ch.srcaddr); + dmainfo(" DESTADDR[%08x]: %08x\n", + base + LPC43_GPDMA_DESTADDR_CHOFFSET, regs->ch.destaddr); + dmainfo(" LLI[%08x]: %08x\n", + base + LPC43_GPDMA_LLI_CHOFFSET, regs->ch.lli); + dmainfo(" CONTROL[%08x]: %08x\n", + base + LPC43_GPDMA_CONTROL_CHOFFSET, regs->ch.control); + dmainfo(" CONFIG[%08x]: %08x\n", + base + LPC43_GPDMA_CONFIG_CHOFFSET, regs->ch.config); } #endif /* CONFIG_DEBUG_DMA */ -- GitLab From 99987a3d51322d0a6d510a06a145e3725bb9fae3 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 2 Dec 2016 08:38:42 -0600 Subject: [PATCH 571/734] Increase max message size in all NxWM configurations. --- configs/mikroe-stm32f4/fulldemo/defconfig | 4 ++-- configs/sam3u-ek/nxwm/defconfig | 2 +- configs/sam4e-ek/nxwm/defconfig | 2 +- configs/sama5d3x-ek/nxwm/defconfig | 2 +- configs/sama5d4-ek/nxwm/defconfig | 2 +- configs/shenzhou/nxwm/defconfig | 2 +- configs/sim/nxwm/defconfig | 2 +- configs/stm3220g-eval/nxwm/defconfig | 2 +- configs/stm3240g-eval/knxwm/defconfig | 2 +- configs/stm3240g-eval/nxwm/defconfig | 2 +- 10 files changed, 11 insertions(+), 11 deletions(-) diff --git a/configs/mikroe-stm32f4/fulldemo/defconfig b/configs/mikroe-stm32f4/fulldemo/defconfig index f2a4e507ab..d9e2a358b3 100644 --- a/configs/mikroe-stm32f4/fulldemo/defconfig +++ b/configs/mikroe-stm32f4/fulldemo/defconfig @@ -694,8 +694,8 @@ CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options # -CONFIG_PREALLOC_MQ_MSGS=4 -CONFIG_MQ_MAXMSGSIZE=32 +CONFIG_PREALLOC_MQ_MSGS=32 +CONFIG_MQ_MAXMSGSIZE=64 # CONFIG_MODULE is not set # diff --git a/configs/sam3u-ek/nxwm/defconfig b/configs/sam3u-ek/nxwm/defconfig index f100066b1f..4aab0d81a2 100644 --- a/configs/sam3u-ek/nxwm/defconfig +++ b/configs/sam3u-ek/nxwm/defconfig @@ -438,7 +438,7 @@ CONFIG_SIG_SIGWORK=17 # POSIX Message Queue Options # CONFIG_PREALLOC_MQ_MSGS=32 -CONFIG_MQ_MAXMSGSIZE=48 +CONFIG_MQ_MAXMSGSIZE=64 # CONFIG_MODULE is not set # diff --git a/configs/sam4e-ek/nxwm/defconfig b/configs/sam4e-ek/nxwm/defconfig index 75684644ed..64423d1b6d 100644 --- a/configs/sam4e-ek/nxwm/defconfig +++ b/configs/sam4e-ek/nxwm/defconfig @@ -485,7 +485,7 @@ CONFIG_SIG_SIGWORK=17 # POSIX Message Queue Options # CONFIG_PREALLOC_MQ_MSGS=32 -CONFIG_MQ_MAXMSGSIZE=48 +CONFIG_MQ_MAXMSGSIZE=64 # CONFIG_MODULE is not set # diff --git a/configs/sama5d3x-ek/nxwm/defconfig b/configs/sama5d3x-ek/nxwm/defconfig index e27f631772..2dfe96aeff 100644 --- a/configs/sama5d3x-ek/nxwm/defconfig +++ b/configs/sama5d3x-ek/nxwm/defconfig @@ -542,7 +542,7 @@ CONFIG_SIG_SIGWORK=17 # POSIX Message Queue Options # CONFIG_PREALLOC_MQ_MSGS=32 -CONFIG_MQ_MAXMSGSIZE=48 +CONFIG_MQ_MAXMSGSIZE=64 # CONFIG_MODULE is not set # diff --git a/configs/sama5d4-ek/nxwm/defconfig b/configs/sama5d4-ek/nxwm/defconfig index da5f0f08c9..5e27e7feee 100644 --- a/configs/sama5d4-ek/nxwm/defconfig +++ b/configs/sama5d4-ek/nxwm/defconfig @@ -590,7 +590,7 @@ CONFIG_SIG_SIGWORK=17 # POSIX Message Queue Options # CONFIG_PREALLOC_MQ_MSGS=32 -CONFIG_MQ_MAXMSGSIZE=48 +CONFIG_MQ_MAXMSGSIZE=64 # CONFIG_MODULE is not set # diff --git a/configs/shenzhou/nxwm/defconfig b/configs/shenzhou/nxwm/defconfig index ccbcaa6fc0..a9dc024a02 100644 --- a/configs/shenzhou/nxwm/defconfig +++ b/configs/shenzhou/nxwm/defconfig @@ -701,7 +701,7 @@ CONFIG_SIG_SIGWORK=17 # POSIX Message Queue Options # CONFIG_PREALLOC_MQ_MSGS=32 -CONFIG_MQ_MAXMSGSIZE=48 +CONFIG_MQ_MAXMSGSIZE=64 # CONFIG_MODULE is not set # diff --git a/configs/sim/nxwm/defconfig b/configs/sim/nxwm/defconfig index e56488f3a6..6fb3f9b5ea 100644 --- a/configs/sim/nxwm/defconfig +++ b/configs/sim/nxwm/defconfig @@ -256,7 +256,7 @@ CONFIG_SIG_SIGWORK=17 # POSIX Message Queue Options # CONFIG_PREALLOC_MQ_MSGS=32 -CONFIG_MQ_MAXMSGSIZE=48 +CONFIG_MQ_MAXMSGSIZE=64 # CONFIG_MODULE is not set # diff --git a/configs/stm3220g-eval/nxwm/defconfig b/configs/stm3220g-eval/nxwm/defconfig index a85c3be95a..f7cd83b4c5 100644 --- a/configs/stm3220g-eval/nxwm/defconfig +++ b/configs/stm3220g-eval/nxwm/defconfig @@ -714,7 +714,7 @@ CONFIG_SIG_SIGWORK=17 # POSIX Message Queue Options # CONFIG_PREALLOC_MQ_MSGS=32 -CONFIG_MQ_MAXMSGSIZE=48 +CONFIG_MQ_MAXMSGSIZE=64 # CONFIG_MODULE is not set # diff --git a/configs/stm3240g-eval/knxwm/defconfig b/configs/stm3240g-eval/knxwm/defconfig index 170f977e35..1f72f2fdaa 100644 --- a/configs/stm3240g-eval/knxwm/defconfig +++ b/configs/stm3240g-eval/knxwm/defconfig @@ -708,7 +708,7 @@ CONFIG_SIG_SIGWORK=17 # POSIX Message Queue Options # CONFIG_PREALLOC_MQ_MSGS=32 -CONFIG_MQ_MAXMSGSIZE=48 +CONFIG_MQ_MAXMSGSIZE=64 # CONFIG_MODULE is not set # diff --git a/configs/stm3240g-eval/nxwm/defconfig b/configs/stm3240g-eval/nxwm/defconfig index 1edbb208f3..42d4860e54 100644 --- a/configs/stm3240g-eval/nxwm/defconfig +++ b/configs/stm3240g-eval/nxwm/defconfig @@ -718,7 +718,7 @@ CONFIG_SIG_SIGWORK=17 # POSIX Message Queue Options # CONFIG_PREALLOC_MQ_MSGS=32 -CONFIG_MQ_MAXMSGSIZE=48 +CONFIG_MQ_MAXMSGSIZE=64 # CONFIG_MODULE is not set # -- GitLab From c0cbea2550982022e194b604485bb15be6447b16 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 2 Dec 2016 09:49:33 -0600 Subject: [PATCH 572/734] Remove RGMP and RGMP drivers. --- Documentation/NuttX.html | 28 - Documentation/README.html | 2 - README.txt | 2 - TODO | 1 - arch/Kconfig | 8 - arch/README.txt | 11 - arch/rgmp/Kconfig | 46 - arch/rgmp/include/.gitignore | 3 - arch/rgmp/include/arch.h | 63 - arch/rgmp/include/arm/arch/subarch/arch.h | 58 - arch/rgmp/include/inttypes.h | 245 ---- arch/rgmp/include/irq.h | 91 -- arch/rgmp/include/limits.h | 86 -- arch/rgmp/include/math.h | 260 ---- arch/rgmp/include/stdbool.h | 84 -- arch/rgmp/include/stdint.h | 277 ---- arch/rgmp/include/types.h | 96 -- arch/rgmp/include/x86/arch/com.h | 58 - arch/rgmp/include/x86/arch/subarch/arch.h | 68 - arch/rgmp/src/.gitignore | 4 - arch/rgmp/src/Makefile | 116 -- arch/rgmp/src/arm/Make.defs | 42 - arch/rgmp/src/arm/arch_nuttx.c | 89 -- arch/rgmp/src/arm/sigentry.S | 49 - arch/rgmp/src/bridge.c | 134 -- arch/rgmp/src/cxx.c | 19 - arch/rgmp/src/nuttx.c | 751 ---------- arch/rgmp/src/rgmp.c | 175 --- arch/rgmp/src/x86/Make.defs | 42 - arch/rgmp/src/x86/arch_nuttx.c | 101 -- arch/rgmp/src/x86/com.c | 667 --------- arch/rgmp/src/x86/sigentry.S | 55 - configs/Kconfig | 17 - configs/README.txt | 10 - configs/amber/hello/defconfig | 2 - configs/arduino-due/nsh/defconfig | 2 - configs/arduino-mega2560/hello/defconfig | 2 - configs/arduino-mega2560/nsh/defconfig | 2 - configs/avr32dev1/nsh/defconfig | 2 - configs/avr32dev1/ostest/defconfig | 2 - configs/bambino-200e/nsh/defconfig | 2 - configs/c5471evm/httpd/defconfig | 2 - configs/c5471evm/nettest/defconfig | 2 - configs/c5471evm/nsh/defconfig | 2 - configs/cc3200-launchpad/nsh/defconfig | 2 - configs/cloudctrl/nsh/defconfig | 5 +- configs/compal_e86/nsh_highram/defconfig | 2 - configs/compal_e88/nsh_highram/defconfig | 2 - configs/compal_e99/nsh_compalram/defconfig | 2 - configs/compal_e99/nsh_highram/defconfig | 2 - configs/demo9s12ne64/ostest/defconfig | 2 - configs/dk-tm4c129x/ipv6/defconfig | 5 +- configs/dk-tm4c129x/nsh/defconfig | 5 +- configs/ea3131/nsh/defconfig | 2 - configs/ea3131/pgnsh/defconfig | 2 - configs/ea3131/usbserial/defconfig | 2 - configs/ea3152/ostest/defconfig | 2 - configs/eagle100/httpd/defconfig | 5 +- configs/eagle100/nettest/defconfig | 5 +- configs/eagle100/nsh/defconfig | 5 +- configs/eagle100/nxflat/defconfig | 2 - configs/eagle100/thttpd/defconfig | 5 +- configs/efm32-g8xx-stk/nsh/defconfig | 2 - configs/efm32gg-stk3700/nsh/defconfig | 2 - configs/ekk-lm3s9b96/nsh/defconfig | 5 +- configs/esp32-core/nsh/defconfig | 2 - configs/esp32-core/smp/defconfig | 2 - configs/ez80f910200kitg/ostest/defconfig | 2 - configs/ez80f910200zco/dhcpd/defconfig | 5 +- configs/ez80f910200zco/httpd/defconfig | 5 +- configs/ez80f910200zco/nettest/defconfig | 5 +- configs/ez80f910200zco/nsh/defconfig | 5 +- configs/ez80f910200zco/poll/defconfig | 5 +- configs/fire-stm32v2/nsh/defconfig | 5 +- configs/freedom-k64f/netnsh/defconfig | 5 +- configs/freedom-k64f/nsh/defconfig | 2 - configs/freedom-kl25z/minnsh/defconfig | 2 - configs/freedom-kl25z/nsh/defconfig | 2 - configs/freedom-kl26z/minnsh/defconfig | 2 - configs/freedom-kl26z/nsh/defconfig | 2 - configs/hymini-stm32v/nsh/defconfig | 2 - configs/hymini-stm32v/nsh2/defconfig | 2 - configs/hymini-stm32v/usbmsc/defconfig | 2 - configs/hymini-stm32v/usbnsh/defconfig | 2 - configs/hymini-stm32v/usbserial/defconfig | 2 - configs/kwikstik-k40/ostest/defconfig | 2 - configs/launchxl-tms57004/nsh/defconfig | 2 - configs/lincoln60/netnsh/defconfig | 5 +- configs/lincoln60/nsh/defconfig | 2 - configs/lincoln60/thttpd-binfs/defconfig | 5 +- configs/lm3s6432-s2e/nsh/defconfig | 5 +- configs/lm3s6965-ek/discover/defconfig | 5 +- configs/lm3s6965-ek/nsh/defconfig | 5 +- configs/lm3s6965-ek/nx/defconfig | 2 - configs/lm3s6965-ek/tcpecho/defconfig | 5 +- configs/lm3s8962-ek/nsh/defconfig | 5 +- configs/lm3s8962-ek/nx/defconfig | 2 - configs/lm4f120-launchpad/nsh/defconfig | 2 - configs/lpc4330-xplorer/nsh/defconfig | 2 - configs/lpc4337-ws/nsh/defconfig | 2 - configs/lpc4357-evb/nsh/defconfig | 2 - configs/lpc4370-link2/nsh/defconfig | 2 - configs/lpcxpresso-lpc1115/minnsh/defconfig | 2 - configs/lpcxpresso-lpc1115/nsh/defconfig | 2 - configs/lpcxpresso-lpc1768/dhcpd/defconfig | 5 +- configs/lpcxpresso-lpc1768/nsh/defconfig | 5 +- configs/lpcxpresso-lpc1768/nx/defconfig | 2 - configs/lpcxpresso-lpc1768/thttpd/defconfig | 5 +- configs/lpcxpresso-lpc1768/usbmsc/defconfig | 2 - configs/maple/nsh/defconfig | 2 - configs/maple/nx/defconfig | 2 - configs/maple/usbnsh/defconfig | 2 - configs/mbed/hidkbd/defconfig | 2 - configs/mbed/nsh/defconfig | 2 - configs/mcu123-lpc214x/composite/defconfig | 2 - configs/mcu123-lpc214x/nsh/defconfig | 2 - configs/mcu123-lpc214x/usbmsc/defconfig | 2 - configs/mcu123-lpc214x/usbserial/defconfig | 2 - configs/micropendous3/hello/defconfig | 2 - configs/mikroe-stm32f4/fulldemo/defconfig | 2 - configs/mikroe-stm32f4/kostest/defconfig | 2 - configs/mikroe-stm32f4/nsh/defconfig | 2 - configs/mikroe-stm32f4/nx/defconfig | 2 - configs/mikroe-stm32f4/nxlines/defconfig | 2 - configs/mikroe-stm32f4/nxtext/defconfig | 2 - configs/mikroe-stm32f4/usbnsh/defconfig | 2 - configs/mirtoo/nsh/defconfig | 2 - configs/mirtoo/nxffs/defconfig | 2 - configs/misoc/hello/defconfig | 5 +- configs/misoc/nsh/defconfig | 2 - configs/moteino-mega/hello/defconfig | 2 - configs/moteino-mega/nsh/defconfig | 2 - configs/moxa/nsh/defconfig | 5 +- configs/mx1ads/ostest/defconfig | 2 - configs/ne64badge/ostest/defconfig | 2 - configs/nr5m100-nexys4/nsh/defconfig | 2 - configs/ntosd-dm320/nettest/defconfig | 5 +- configs/ntosd-dm320/nsh/defconfig | 5 +- configs/ntosd-dm320/poll/defconfig | 5 +- configs/ntosd-dm320/thttpd/defconfig | 5 +- configs/ntosd-dm320/udp/defconfig | 5 +- configs/ntosd-dm320/webserver/defconfig | 5 +- configs/nucleo-144/f746-evalos/defconfig | 2 - configs/nucleo-144/f746-nsh/defconfig | 2 - configs/nucleo-144/f767-evalos/defconfig | 2 - configs/nucleo-144/f767-nsh/defconfig | 2 - configs/nucleo-f303re/adc/defconfig | 2 - configs/nucleo-f303re/can/defconfig | 2 - configs/nucleo-f303re/hello/defconfig | 2 - configs/nucleo-f303re/nxlines/defconfig | 2 - configs/nucleo-f303re/pwm/defconfig | 2 - configs/nucleo-f303re/serialrx/defconfig | 2 - configs/nucleo-f303re/uavcan/defconfig | 2 - configs/nucleo-f4x1re/f401-nsh/defconfig | 2 - configs/nucleo-f4x1re/f411-nsh/defconfig | 2 - configs/nucleo-l476rg/nsh/defconfig | 2 - configs/nutiny-nuc120/nsh/defconfig | 2 - .../olimex-efm32g880f128-stk/nsh/defconfig | 2 - configs/olimex-lpc-h3131/nsh/defconfig | 2 - configs/olimex-lpc1766stk/ftpc/defconfig | 5 +- configs/olimex-lpc1766stk/hidkbd/defconfig | 2 - configs/olimex-lpc1766stk/hidmouse/defconfig | 2 - configs/olimex-lpc1766stk/nettest/defconfig | 5 +- configs/olimex-lpc1766stk/nsh/defconfig | 5 +- configs/olimex-lpc1766stk/nx/defconfig | 2 - .../olimex-lpc1766stk/slip-httpd/defconfig | 2 - .../olimex-lpc1766stk/thttpd-binfs/defconfig | 5 +- .../olimex-lpc1766stk/thttpd-nxflat/defconfig | 5 +- configs/olimex-lpc1766stk/usbmsc/defconfig | 2 - configs/olimex-lpc1766stk/usbserial/defconfig | 2 - configs/olimex-lpc1766stk/zmodem/defconfig | 5 +- configs/olimex-lpc2378/nsh/defconfig | 2 - configs/olimex-stm32-e407/discover/defconfig | 5 +- configs/olimex-stm32-e407/netnsh/defconfig | 5 +- configs/olimex-stm32-e407/nsh/defconfig | 2 - configs/olimex-stm32-e407/telnetd/defconfig | 5 +- configs/olimex-stm32-e407/usbnsh/defconfig | 2 - configs/olimex-stm32-e407/webserver/defconfig | 5 +- configs/olimex-stm32-h405/usbnsh/defconfig | 2 - configs/olimex-stm32-h407/nsh/defconfig | 2 - configs/olimex-stm32-p107/nsh/defconfig | 5 +- configs/olimex-stm32-p207/nsh/defconfig | 5 +- configs/olimex-strp711/nettest/defconfig | 5 +- configs/olimex-strp711/nsh/defconfig | 2 - configs/olimexino-stm32/can/defconfig | 2 - configs/olimexino-stm32/composite/defconfig | 2 - configs/olimexino-stm32/nsh/defconfig | 2 - configs/olimexino-stm32/smallnsh/defconfig | 2 - configs/olimexino-stm32/tiny/defconfig | 2 - configs/open1788/knsh/defconfig | 2 - configs/open1788/nsh/defconfig | 2 - configs/open1788/nxlines/defconfig | 2 - configs/p112/ostest/defconfig | 2 - configs/pcblogic-pic32mx/nsh/defconfig | 2 - configs/pcduino-a10/nsh/defconfig | 2 - configs/pic32mx-starterkit/nsh/defconfig | 2 - configs/pic32mx-starterkit/nsh2/defconfig | 5 +- configs/pic32mx7mmb/nsh/defconfig | 5 +- configs/pic32mz-starterkit/nsh/defconfig | 2 - configs/pirelli_dpl10/nsh_highram/defconfig | 2 - configs/qemu-i486/nsh/defconfig | 2 - configs/qemu-i486/ostest/defconfig | 2 - configs/rgmp/Kconfig | 8 - configs/rgmp/README.txt | 90 -- configs/rgmp/arm/default/Make.defs | 96 -- configs/rgmp/arm/default/defconfig | 659 --------- configs/rgmp/arm/default/setenv.sh | 47 - configs/rgmp/arm/nsh/Make.defs | 96 -- configs/rgmp/arm/nsh/defconfig | 768 ---------- configs/rgmp/arm/nsh/setenv.sh | 47 - configs/rgmp/include/stdarg.h | 8 - configs/rgmp/x86/cxxtest/Make.defs | 107 -- configs/rgmp/x86/cxxtest/defconfig | 700 --------- configs/rgmp/x86/cxxtest/setenv.sh | 47 - configs/rgmp/x86/default/Make.defs | 95 -- configs/rgmp/x86/default/defconfig | 667 --------- configs/rgmp/x86/default/setenv.sh | 47 - configs/rgmp/x86/helloxx/Make.defs | 105 -- configs/rgmp/x86/helloxx/defconfig | 697 --------- configs/rgmp/x86/helloxx/setenv.sh | 47 - configs/rgmp/x86/nsh/Make.defs | 95 -- configs/rgmp/x86/nsh/defconfig | 781 ---------- configs/rgmp/x86/nsh/setenv.sh | 47 - configs/sabre-6quad/nsh/defconfig | 2 - configs/sabre-6quad/smp/defconfig | 2 - configs/sam3u-ek/knsh/defconfig | 2 - configs/sam3u-ek/nsh/defconfig | 2 - configs/sam3u-ek/nx/defconfig | 2 - configs/sam3u-ek/nxwm/defconfig | 2 - configs/sam4e-ek/nsh/defconfig | 5 +- configs/sam4e-ek/nxwm/defconfig | 5 +- configs/sam4e-ek/usbnsh/defconfig | 5 +- configs/sam4l-xplained/nsh/defconfig | 2 - configs/sam4s-xplained-pro/nsh/defconfig | 2 - configs/sam4s-xplained/nsh/defconfig | 2 - configs/sama5d2-xult/nsh/defconfig | 2 - configs/sama5d3-xplained/bridge/defconfig | 5 +- configs/sama5d3-xplained/nsh/defconfig | 2 - configs/sama5d3x-ek/demo/defconfig | 2 - configs/sama5d3x-ek/hello/defconfig | 2 - configs/sama5d3x-ek/norboot/defconfig | 2 - configs/sama5d3x-ek/nsh/defconfig | 2 - configs/sama5d3x-ek/nx/defconfig | 2 - configs/sama5d3x-ek/nxplayer/defconfig | 2 - configs/sama5d3x-ek/nxwm/defconfig | 2 - configs/sama5d3x-ek/ov2640/defconfig | 2 - configs/sama5d4-ek/at25boot/defconfig | 2 - configs/sama5d4-ek/bridge/defconfig | 5 +- configs/sama5d4-ek/dramboot/defconfig | 2 - configs/sama5d4-ek/elf/defconfig | 2 - configs/sama5d4-ek/ipv6/defconfig | 5 +- configs/sama5d4-ek/knsh/defconfig | 2 - configs/sama5d4-ek/knsh/defconfig.ROMFS | 2 - configs/sama5d4-ek/nsh/defconfig | 5 +- configs/sama5d4-ek/nxwm/defconfig | 5 +- configs/sama5d4-ek/ramtest/defconfig | 2 - configs/samd20-xplained/nsh/defconfig | 2 - configs/samd21-xplained/nsh/defconfig | 2 - configs/same70-xplained/netnsh/defconfig | 5 +- configs/same70-xplained/nsh/defconfig | 2 - configs/saml21-xplained/nsh/defconfig | 2 - configs/samv71-xult/knsh/defconfig | 2 - configs/samv71-xult/module/defconfig | 2 - configs/samv71-xult/mxtxplnd/defconfig | 2 - configs/samv71-xult/netnsh/defconfig | 5 +- configs/samv71-xult/nsh/defconfig | 2 - configs/samv71-xult/nxwm/defconfig | 2 - configs/samv71-xult/vnc/defconfig | 5 +- configs/samv71-xult/vnxwm/defconfig | 5 +- configs/shenzhou/nsh/defconfig | 5 +- configs/shenzhou/nxwm/defconfig | 5 +- configs/shenzhou/thttpd/defconfig | 5 +- configs/sim/bas/defconfig | 2 - configs/sim/configdata/defconfig | 2 - configs/sim/cxxtest/defconfig | 2 - configs/sim/minibasic/defconfig | 2 - configs/sim/mount/defconfig | 2 - configs/sim/mtdpart/defconfig | 2 - configs/sim/mtdrwb/defconfig | 2 - configs/sim/nettest/defconfig | 2 - configs/sim/nsh/defconfig | 2 - configs/sim/nsh2/defconfig | 2 - configs/sim/nx/defconfig | 2 - configs/sim/nx11/defconfig | 2 - configs/sim/nxffs/defconfig | 2 - configs/sim/nxlines/defconfig | 2 - configs/sim/nxwm/defconfig | 2 - configs/sim/ostest/defconfig | 2 - configs/sim/pashello/defconfig | 2 - configs/sim/touchscreen/defconfig | 2 - configs/sim/traveler/defconfig | 2 - configs/sim/udgram/defconfig | 2 - configs/sim/unionfs/defconfig | 2 - configs/sim/ustream/defconfig | 2 - configs/skp16c26/ostest/defconfig | 2 - configs/spark/composite/defconfig | 2 - configs/spark/nsh/defconfig | 2 - configs/spark/usbmsc/defconfig | 2 - configs/spark/usbnsh/defconfig | 2 - configs/spark/usbserial/defconfig | 2 - configs/stm3210e-eval/composite/defconfig | 2 - configs/stm3210e-eval/nsh/defconfig | 2 - configs/stm3210e-eval/nsh2/defconfig | 2 - configs/stm3210e-eval/nx/defconfig | 2 - configs/stm3210e-eval/nxterm/defconfig | 2 - configs/stm3210e-eval/pm/defconfig | 2 - configs/stm3210e-eval/usbmsc/defconfig | 2 - configs/stm3210e-eval/usbserial/defconfig | 2 - configs/stm3220g-eval/dhcpd/defconfig | 5 +- configs/stm3220g-eval/nettest/defconfig | 5 +- configs/stm3220g-eval/nsh/defconfig | 5 +- configs/stm3220g-eval/nsh2/defconfig | 5 +- configs/stm3220g-eval/nxwm/defconfig | 5 +- configs/stm3220g-eval/telnetd/defconfig | 5 +- configs/stm3240g-eval/dhcpd/defconfig | 5 +- configs/stm3240g-eval/discover/defconfig | 5 +- configs/stm3240g-eval/knxwm/defconfig | 2 - configs/stm3240g-eval/nettest/defconfig | 5 +- configs/stm3240g-eval/nsh/defconfig | 5 +- configs/stm3240g-eval/nsh2/defconfig | 5 +- configs/stm3240g-eval/nxterm/defconfig | 5 +- configs/stm3240g-eval/nxwm/defconfig | 5 +- configs/stm3240g-eval/telnetd/defconfig | 5 +- configs/stm3240g-eval/webserver/defconfig | 5 +- configs/stm3240g-eval/xmlrpc/defconfig | 5 +- configs/stm32_tiny/nsh/defconfig | 2 - configs/stm32_tiny/usbnsh/defconfig | 2 - configs/stm32butterfly2/nsh/defconfig | 2 - configs/stm32butterfly2/nshnet/defconfig | 5 +- configs/stm32butterfly2/nshusbdev/defconfig | 2 - configs/stm32butterfly2/nshusbhost/defconfig | 2 - .../stm32f103-minimum/audio_tone/defconfig | 2 - configs/stm32f103-minimum/buttons/defconfig | 2 - configs/stm32f103-minimum/jlx12864g/defconfig | 2 - configs/stm32f103-minimum/minnsh/defconfig | 2 - configs/stm32f103-minimum/nsh/defconfig | 2 - configs/stm32f103-minimum/pwm/defconfig | 2 - .../stm32f103-minimum/rfid-rc522/defconfig | 2 - configs/stm32f103-minimum/rgbled/defconfig | 2 - configs/stm32f103-minimum/usbnsh/defconfig | 2 - configs/stm32f103-minimum/userled/defconfig | 2 - configs/stm32f103-minimum/veml6070/defconfig | 2 - configs/stm32f3discovery/nsh/defconfig | 2 - configs/stm32f3discovery/usbnsh/defconfig | 2 - configs/stm32f411e-disco/nsh/defconfig | 2 - configs/stm32f429i-disco/extflash/defconfig | 2 - configs/stm32f429i-disco/lcd/defconfig | 2 - configs/stm32f429i-disco/ltdc/defconfig | 2 - configs/stm32f429i-disco/nsh/defconfig | 2 - configs/stm32f429i-disco/usbmsc/defconfig | 2 - configs/stm32f429i-disco/usbnsh/defconfig | 2 - configs/stm32f4discovery/canard/defconfig | 2 - configs/stm32f4discovery/cxxtest/defconfig | 2 - configs/stm32f4discovery/elf/defconfig | 2 - configs/stm32f4discovery/ipv6/defconfig | 5 +- configs/stm32f4discovery/kostest/defconfig | 2 - configs/stm32f4discovery/netnsh/defconfig | 5 +- configs/stm32f4discovery/nsh/defconfig | 2 - configs/stm32f4discovery/nxlines/defconfig | 2 - configs/stm32f4discovery/pm/defconfig | 2 - .../stm32f4discovery/posix_spawn/defconfig | 2 - configs/stm32f4discovery/pseudoterm/defconfig | 2 - configs/stm32f4discovery/rgbled/defconfig | 2 - configs/stm32f4discovery/uavcan/defconfig | 2 - configs/stm32f4discovery/usbnsh/defconfig | 2 - configs/stm32f4discovery/winbuild/defconfig | 2 - configs/stm32f4discovery/xen1210/defconfig | 2 - configs/stm32f746-ws/nsh/defconfig | 2 - configs/stm32f746g-disco/nsh/defconfig | 2 - configs/stm32l476-mdk/nsh/defconfig | 2 - configs/stm32l476vg-disco/nsh/defconfig | 2 - configs/stm32ldiscovery/nsh/defconfig | 2 - configs/stm32vldiscovery/nsh/defconfig | 2 - configs/sure-pic32mx/nsh/defconfig | 2 - configs/sure-pic32mx/usbnsh/defconfig | 2 - configs/teensy-2.0/hello/defconfig | 2 - configs/teensy-2.0/nsh/defconfig | 2 - configs/teensy-2.0/usbmsc/defconfig | 2 - configs/teensy-3.x/nsh/defconfig | 2 - configs/teensy-3.x/usbnsh/defconfig | 2 - configs/teensy-lc/nsh/defconfig | 2 - configs/tm4c123g-launchpad/nsh/defconfig | 2 - configs/tm4c1294-launchpad/ipv6/defconfig | 5 +- configs/tm4c1294-launchpad/nsh/defconfig | 5 +- configs/twr-k60n512/nsh/defconfig | 2 - configs/u-blox-c027/nsh/defconfig | 5 +- configs/ubw32/nsh/defconfig | 2 - configs/us7032evb1/nsh/defconfig | 2 - configs/us7032evb1/ostest/defconfig | 2 - configs/viewtool-stm32f107/highpri/defconfig | 2 - configs/viewtool-stm32f107/netnsh/defconfig | 5 +- configs/viewtool-stm32f107/nsh/defconfig | 2 - configs/xtrs/nsh/defconfig | 2 - configs/xtrs/ostest/defconfig | 2 - configs/xtrs/pashello/defconfig | 2 - configs/z16f2800100zcog/nsh/defconfig | 2 - configs/z16f2800100zcog/ostest/defconfig | 2 - configs/z16f2800100zcog/pashello/defconfig | 2 - configs/z80sim/nsh/defconfig | 2 - configs/z80sim/ostest/defconfig | 2 - configs/z80sim/pashello/defconfig | 2 - configs/z8encore000zco/ostest/defconfig | 2 - configs/z8f64200100kit/ostest/defconfig | 2 - configs/zkit-arm-1769/hello/defconfig | 5 +- configs/zkit-arm-1769/nsh/defconfig | 5 +- configs/zkit-arm-1769/nxhello/defconfig | 5 +- configs/zkit-arm-1769/thttpd/defconfig | 5 +- configs/zp214xpa/nsh/defconfig | 2 - configs/zp214xpa/nxlines/defconfig | 2 - drivers/net/Kconfig | 32 - drivers/net/Make.defs | 8 - drivers/net/e1000.c | 1292 ----------------- drivers/net/e1000.h | 121 -- drivers/net/vnet.c | 789 ---------- tools/cfgdefine.c | 4 - 415 files changed, 90 insertions(+), 12146 deletions(-) delete mode 100644 arch/rgmp/Kconfig delete mode 100644 arch/rgmp/include/.gitignore delete mode 100644 arch/rgmp/include/arch.h delete mode 100644 arch/rgmp/include/arm/arch/subarch/arch.h delete mode 100644 arch/rgmp/include/inttypes.h delete mode 100644 arch/rgmp/include/irq.h delete mode 100644 arch/rgmp/include/limits.h delete mode 100644 arch/rgmp/include/math.h delete mode 100644 arch/rgmp/include/stdbool.h delete mode 100644 arch/rgmp/include/stdint.h delete mode 100644 arch/rgmp/include/types.h delete mode 100644 arch/rgmp/include/x86/arch/com.h delete mode 100644 arch/rgmp/include/x86/arch/subarch/arch.h delete mode 100644 arch/rgmp/src/.gitignore delete mode 100644 arch/rgmp/src/Makefile delete mode 100644 arch/rgmp/src/arm/Make.defs delete mode 100644 arch/rgmp/src/arm/arch_nuttx.c delete mode 100644 arch/rgmp/src/arm/sigentry.S delete mode 100644 arch/rgmp/src/bridge.c delete mode 100644 arch/rgmp/src/cxx.c delete mode 100644 arch/rgmp/src/nuttx.c delete mode 100644 arch/rgmp/src/rgmp.c delete mode 100644 arch/rgmp/src/x86/Make.defs delete mode 100644 arch/rgmp/src/x86/arch_nuttx.c delete mode 100644 arch/rgmp/src/x86/com.c delete mode 100644 arch/rgmp/src/x86/sigentry.S delete mode 100644 configs/rgmp/Kconfig delete mode 100644 configs/rgmp/README.txt delete mode 100644 configs/rgmp/arm/default/Make.defs delete mode 100644 configs/rgmp/arm/default/defconfig delete mode 100755 configs/rgmp/arm/default/setenv.sh delete mode 100644 configs/rgmp/arm/nsh/Make.defs delete mode 100644 configs/rgmp/arm/nsh/defconfig delete mode 100755 configs/rgmp/arm/nsh/setenv.sh delete mode 100644 configs/rgmp/include/stdarg.h delete mode 100644 configs/rgmp/x86/cxxtest/Make.defs delete mode 100644 configs/rgmp/x86/cxxtest/defconfig delete mode 100755 configs/rgmp/x86/cxxtest/setenv.sh delete mode 100644 configs/rgmp/x86/default/Make.defs delete mode 100644 configs/rgmp/x86/default/defconfig delete mode 100755 configs/rgmp/x86/default/setenv.sh delete mode 100644 configs/rgmp/x86/helloxx/Make.defs delete mode 100644 configs/rgmp/x86/helloxx/defconfig delete mode 100755 configs/rgmp/x86/helloxx/setenv.sh delete mode 100644 configs/rgmp/x86/nsh/Make.defs delete mode 100644 configs/rgmp/x86/nsh/defconfig delete mode 100755 configs/rgmp/x86/nsh/setenv.sh delete mode 100644 drivers/net/e1000.c delete mode 100644 drivers/net/e1000.h delete mode 100644 drivers/net/vnet.c diff --git a/Documentation/NuttX.html b/Documentation/NuttX.html index 18963bc574..7878f2fd25 100644 --- a/Documentation/NuttX.html +++ b/Documentation/NuttX.html @@ -4920,34 +4920,6 @@ Mem: 29232 5920 23312 23312 - -
    -
    - - -
    - -

    - RGMP. - RGMP stands for RTOS and GPOS on Multi-Processor. - RGMP is a project for running GPOS and RTOS simultaneously on multi-processor platforms - You can port your favorite RTOS to RGMP together with an unmodified Linux to form a hybrid operating system. - This makes your application able to use both RTOS and GPOS features. -

    -

    - See the RGMP Wiki for further information about RGMP. -

    -
      -

      - STATUS: - This initial port of NuttX to RGMP was provided in NuttX-6.3. - This initial RGP port provides only minimal driver support and does not use the native NuttX interrupt system. - This is a great, stable starting point for anyone interest in working with NuttX under RGMP! - Refer to the NuttX README file for further information. -

      -
    - - diff --git a/Documentation/README.html b/Documentation/README.html index a9577df8ce..4c7137a37b 100644 --- a/Documentation/README.html +++ b/Documentation/README.html @@ -203,8 +203,6 @@ nuttx/ | | `- README.txt | |- qemu-i486/ | | `- README.txt - | |- rgmp/ - | | `- README.txt | |- sabre-6quad/ | | `- README.txt | |- sama5d2-xult/ diff --git a/README.txt b/README.txt index 3a673b7e9a..89a41af473 100644 --- a/README.txt +++ b/README.txt @@ -1419,8 +1419,6 @@ nuttx/ | | `- README.txt | |- qemu-i486/ | | `- README.txt - | |- rgmp/ - | | `- README.txt | |- sabre-6quad/ | | `- README.txt | |- sama5d2-xult/ diff --git a/TODO b/TODO index 6234b44e6d..cdb5fc5a1c 100644 --- a/TODO +++ b/TODO @@ -1065,7 +1065,6 @@ o Network (net/, drivers/net) LPC43xx YES YES (not tested) DMxxx NIC NO NO PIC32 NO NO - RGMP ??? ??? SAM3/4 YES YES SAMA5D ----------------------- ------ EMACA NO YES (not tested) diff --git a/arch/Kconfig b/arch/Kconfig index 0125994830..1e26db617f 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -46,12 +46,6 @@ config ARCH_MISOC ---help--- MISOC -config ARCH_RGMP - bool "RGMP" - ---help--- - RTOS and GPOS on Multi-Processor (RGMP) architecture. See - http://rgmp.sourceforge.net/wiki/index.php/Main_Page. - config ARCH_RENESAS bool "Renesas" select ARCH_NOINTC @@ -107,7 +101,6 @@ config ARCH default "hc" if ARCH_HC default "mips" if ARCH_MIPS default "misoc" if ARCH_MISOC - default "rgmp" if ARCH_RGMP default "renesas" if ARCH_RENESAS default "risc-v" if ARCH_RISCV default "sim" if ARCH_SIM @@ -121,7 +114,6 @@ source arch/avr/Kconfig source arch/hc/Kconfig source arch/mips/Kconfig source arch/misoc/Kconfig -source arch/rgmp/Kconfig source arch/renesas/Kconfig source arch/risc-v/Kconfig source arch/sim/Kconfig diff --git a/arch/README.txt b/arch/README.txt index 4d4fe01ec1..2e52e95ff0 100644 --- a/arch/README.txt +++ b/arch/README.txt @@ -222,17 +222,6 @@ arch/renesas - Support for Renesas and legacy Hitachi microcontrollers. arch/renesas/include/m16c and arch/renesas/src/m16c arch/renesas/include/sh1 and arch/renesas/src/sh1 -arch/rgmp - - RGMP stands for RTOS and GPOS on Multi-Processor. RGMP is a project - for running GPOS and RTOS simultaneously on multi-processor platforms. - You can port your favorite RTOS to RGMP together with an unmodified - Linux to form a hybrid operating system. This makes your application - able to use both RTOS and GPOS features. - - See http://rgmp.sourceforge.net/wiki/index.php/Main_Page for further - information about RGMP. - arch/risc-v This directory is dedicated to ports to the RISC-V family. diff --git a/arch/rgmp/Kconfig b/arch/rgmp/Kconfig deleted file mode 100644 index 690f88e614..0000000000 --- a/arch/rgmp/Kconfig +++ /dev/null @@ -1,46 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -if ARCH_RGMP -comment "RGMP Configuration Options" - -choice - prompt "RGMP Architecture" - default RGMP_SUBARCH_X86 - -config RGMP_SUBARCH_ARM - bool "ARM" - ---help--- - RGMP ARM architecture" - -config RGMP_SUBARCH_X86 - bool "x86" - ---help--- - RGMP x86 architecture" - -endchoice # RGMP Architecture - -config RGMP_SUBARCH - string - default "arm" if RGMP_SUBARCH_ARM - default "x86" if RGMP_SUBARCH_X86 - -menu "x86 Peripheral Selections" - depends on RGMP_SUBARCH_X86 - -config COM1 - bool "COM1" - -config COM2 - bool "COM1" - -config COM3 - bool "COM1" - -config COM4 - bool "COM1" - -endmenu # x86 Peripheral Selections -endif # ARCH_RGMP diff --git a/arch/rgmp/include/.gitignore b/arch/rgmp/include/.gitignore deleted file mode 100644 index e6460c4a67..0000000000 --- a/arch/rgmp/include/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -/board -/chip - diff --git a/arch/rgmp/include/arch.h b/arch/rgmp/include/arch.h deleted file mode 100644 index af99356ea1..0000000000 --- a/arch/rgmp/include/arch.h +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * arch/rgmp/include/arch.h - * - * Copyright (C) 2011 Yu Qiang. All rights reserved. - * Author: Yu Qiang - * - * This file is a part of NuttX: - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __RGMP_ARCH_ARCH_H -#define __RGMP_ARCH_ARCH_H - -#include - -#ifndef __ASSEMBLY__ - -#include - -struct up_wait { - struct up_wait *next; - struct tcb_s *task; -}; - -extern struct tcb_s *current_task; - -void up_sigentry(void); - -int up_register_bridge(char *name, int size); -int up_unregister_bridge(char *name); - -#endif /* !__ASSEMBLY__ */ - -#endif diff --git a/arch/rgmp/include/arm/arch/subarch/arch.h b/arch/rgmp/include/arm/arch/subarch/arch.h deleted file mode 100644 index e5f3fff10f..0000000000 --- a/arch/rgmp/include/arm/arch/subarch/arch.h +++ /dev/null @@ -1,58 +0,0 @@ -/**************************************************************************** - * arch/rgmp/include/arm/arch/subarch/arch.h - * - * Copyright (C) 2011 Yu Qiang. All rights reserved. - * Author: Yu Qiang - * - * This file is a part of NuttX: - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __RGMP_ARCH_SUBARCH_ARCH_H -#define __RGMP_ARCH_SUBARCH_ARCH_H - -#ifndef __ASSEMBLY__ - - -static inline void up_mdelay(uint32_t msec) -{ - -} - -static inline void up_udelay(uint32_t usec) -{ - -} - -#endif /* !__ASSEMBLY__ */ - -#endif diff --git a/arch/rgmp/include/inttypes.h b/arch/rgmp/include/inttypes.h deleted file mode 100644 index 4d3d40aef2..0000000000 --- a/arch/rgmp/include/inttypes.h +++ /dev/null @@ -1,245 +0,0 @@ -/**************************************************************************** - * arch/rgmp/include/inttypes.h - * - * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. - * Author: Paul Alexander Patience - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_RGMP_INCLUDE_INTTYPES_H -#define __ARCH_RGMP_INCLUDE_INTTYPES_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define PRId8 "d" -#define PRId16 "d" -#define PRId32 "d" -#define PRId64 "lld" - -#define PRIdLEAST8 "d" -#define PRIdLEAST16 "d" -#define PRIdLEAST32 "d" -#define PRIdLEAST64 "lld" - -#define PRIdFAST8 "d" -#define PRIdFAST16 "d" -#define PRIdFAST32 "d" -#define PRIdFAST64 "lld" - -#define PRIdMAX "lld" -#define PRIdPTR "d" - -#define PRIi8 "i" -#define PRIi16 "i" -#define PRIi32 "i" -#define PRIi64 "lli" - -#define PRIiLEAST8 "i" -#define PRIiLEAST16 "i" -#define PRIiLEAST32 "i" -#define PRIiLEAST64 "lli" - -#define PRIiFAST8 "i" -#define PRIiFAST16 "i" -#define PRIiFAST32 "i" -#define PRIiFAST64 "lli" - -#define PRIiMAX "lli" -#define PRIiPTR "i" - -#define PRIo8 "o" -#define PRIo16 "o" -#define PRIo32 "o" -#define PRIo64 "llo" - -#define PRIoLEAST8 "o" -#define PRIoLEAST16 "o" -#define PRIoLEAST32 "o" -#define PRIoLEAST64 "llo" - -#define PRIoFAST8 "o" -#define PRIoFAST16 "o" -#define PRIoFAST32 "o" -#define PRIoFAST64 "llo" - -#define PRIoMAX "llo" -#define PRIoPTR "o" - -#define PRIu8 "u" -#define PRIu16 "u" -#define PRIu32 "u" -#define PRIu64 "llu" - -#define PRIuLEAST8 "u" -#define PRIuLEAST16 "u" -#define PRIuLEAST32 "u" -#define PRIuLEAST64 "llu" - -#define PRIuFAST8 "u" -#define PRIuFAST16 "u" -#define PRIuFAST32 "u" -#define PRIuFAST64 "llu" - -#define PRIuMAX "llu" -#define PRIuPTR "u" - -#define PRIx8 "x" -#define PRIx16 "x" -#define PRIx32 "x" -#define PRIx64 "llx" - -#define PRIxLEAST8 "x" -#define PRIxLEAST16 "x" -#define PRIxLEAST32 "x" -#define PRIxLEAST64 "llx" - -#define PRIxFAST8 "x" -#define PRIxFAST16 "x" -#define PRIxFAST32 "x" -#define PRIxFAST64 "llx" - -#define PRIxMAX "llx" -#define PRIxPTR "x" - -#define PRIX8 "X" -#define PRIX16 "X" -#define PRIX32 "X" -#define PRIX64 "llX" - -#define PRIXLEAST8 "X" -#define PRIXLEAST16 "X" -#define PRIXLEAST32 "X" -#define PRIXLEAST64 "llX" - -#define PRIXFAST8 "X" -#define PRIXFAST16 "X" -#define PRIXFAST32 "X" -#define PRIXFAST64 "llX" - -#define PRIXMAX "llX" -#define PRIXPTR "X" - -#define SCNd8 "hhd" -#define SCNd16 "hd" -#define SCNd32 "d" -#define SCNd64 "lld" - -#define SCNdLEAST8 "hhd" -#define SCNdLEAST16 "hd" -#define SCNdLEAST32 "d" -#define SCNdLEAST64 "lld" - -#define SCNdFAST8 "hhd" -#define SCNdFAST16 "hd" -#define SCNdFAST32 "d" -#define SCNdFAST64 "lld" - -#define SCNdMAX "lld" -#define SCNdPTR "d" - -#define SCNi8 "hhi" -#define SCNi16 "hi" -#define SCNi32 "i" -#define SCNi64 "lli" - -#define SCNiLEAST8 "hhi" -#define SCNiLEAST16 "hi" -#define SCNiLEAST32 "i" -#define SCNiLEAST64 "lli" - -#define SCNiFAST8 "hhi" -#define SCNiFAST16 "hi" -#define SCNiFAST32 "i" -#define SCNiFAST64 "lli" - -#define SCNiMAX "lli" -#define SCNiPTR "i" - -#define SCNo8 "hho" -#define SCNo16 "ho" -#define SCNo32 "o" -#define SCNo64 "llo" - -#define SCNoLEAST8 "hho" -#define SCNoLEAST16 "ho" -#define SCNoLEAST32 "o" -#define SCNoLEAST64 "llo" - -#define SCNoFAST8 "hho" -#define SCNoFAST16 "ho" -#define SCNoFAST32 "o" -#define SCNoFAST64 "llo" - -#define SCNoMAX "llo" -#define SCNoPTR "o" - -#define SCNu8 "hhu" -#define SCNu16 "hu" -#define SCNu32 "u" -#define SCNu64 "llu" - -#define SCNuLEAST8 "hhu" -#define SCNuLEAST16 "hu" -#define SCNuLEAST32 "u" -#define SCNuLEAST64 "llu" - -#define SCNuFAST8 "hhu" -#define SCNuFAST16 "hu" -#define SCNuFAST32 "u" -#define SCNuFAST64 "llu" - -#define SCNuMAX "llu" -#define SCNuPTR "u" - -#define SCNx8 "hhx" -#define SCNx16 "hx" -#define SCNx32 "x" -#define SCNx64 "llx" - -#define SCNxLEAST8 "hhx" -#define SCNxLEAST16 "hx" -#define SCNxLEAST32 "x" -#define SCNxLEAST64 "llx" - -#define SCNxFAST8 "hhx" -#define SCNxFAST16 "hx" -#define SCNxFAST32 "x" -#define SCNxFAST64 "llx" - -#define SCNxMAX "llx" -#define SCNxPTR "x" - -#endif /* __ARCH_RGMP_INCLUDE_INTTYPES_H */ diff --git a/arch/rgmp/include/irq.h b/arch/rgmp/include/irq.h deleted file mode 100644 index b4c4f37d2d..0000000000 --- a/arch/rgmp/include/irq.h +++ /dev/null @@ -1,91 +0,0 @@ -/**************************************************************************** - * arch/rgmp/include/irq.h - * - * Copyright (C) 2011 Yu Qiang. All rights reserved. - * Author: Yu Qiang - * - * This file is a part of NuttX: - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_RGMP_INCLUDE_IRQ_H -#define __ARCH_RGMP_INCLUDE_IRQ_H - -#define NR_IRQS 0 - -#ifndef __ASSEMBLY__ - -#include - -#include -#include - -struct xcptcontext -{ - struct rgmp_context ctx; - - /* For signal using */ - - unsigned int save_eip; - unsigned int save_eflags; - void *sigdeliver; -}; - -void push_xcptcontext(struct xcptcontext *xcp); -void pop_xcptcontext(struct xcptcontext *xcp); - -extern int nest_irq; - -/* Name: up_irq_save, up_irq_restore, and friends. - * - * NOTE: This function should never be called from application code and, - * as a general rule unless you really know what you are doing, this - * function should not be called directly from operation system code either: - * Typically, the wrapper functions, enter_critical_section() and - * leave_critical section(), are probably what you really want. - */ - -static inline irqstate_t up_irq_save(void) -{ - unsigned long flags; - local_irq_save(flags); - return flags; -} - -static inline void up_irq_restore(irqstate_t flags) -{ - local_irq_restore(flags); -} - -#endif /* !__ASSEMBLY__ */ - -#endif diff --git a/arch/rgmp/include/limits.h b/arch/rgmp/include/limits.h deleted file mode 100644 index a17af23d99..0000000000 --- a/arch/rgmp/include/limits.h +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************** - * arch/rgmp/include/limits.h - * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name Gregory Nutt nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_RGMP_INCLUDE_LIMITS_H -#define __ARCH_RGMP_INCLUDE_LIMITS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define CHAR_BIT 8 -#define SCHAR_MIN (-SCHAR_MAX - 1) -#define SCHAR_MAX 127 -#define UCHAR_MAX 255 - -/* These could be different on machines where char is unsigned */ - -#ifdef __CHAR_UNSIGNED__ -#define CHAR_MIN 0 -#define CHAR_MAX UCHAR_MAX -#else -#define CHAR_MIN SCHAR_MIN -#define CHAR_MAX SCHAR_MAX -#endif - -#define SHRT_MIN (-SHRT_MAX - 1) -#define SHRT_MAX 32767 -#define USHRT_MAX 65535U - -#define INT_MIN (-INT_MAX - 1) -#define INT_MAX 2147483647 -#define UINT_MAX 4294967295U - -/* These change on 32-bit and 64-bit platforms */ - -#define LONG_MIN (-LONG_MAX - 1) -#define LONG_MAX 2147483647L -#define ULONG_MAX 4294967295UL - -#define LLONG_MIN (-LLONG_MAX - 1) -#define LLONG_MAX 9223372036854775807LL -#define ULLONG_MAX 18446744073709551615ULL - -/* A pointer is 4 bytes */ - -#define PTR_MIN (-PTR_MAX - 1) -#define PTR_MAX 2147483647 -#define UPTR_MAX 4294967295U - -#endif /* __ARCH_RGMP_INCLUDE_LIMITS_H */ diff --git a/arch/rgmp/include/math.h b/arch/rgmp/include/math.h deleted file mode 100644 index e042ba4a3c..0000000000 --- a/arch/rgmp/include/math.h +++ /dev/null @@ -1,260 +0,0 @@ -/**************************************************************************** - * arch/rgmp/include/math.h - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_RGMP_INCLUDE_MATH_H -#define __ARCH_RGMP_INCLUDE_MATH_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Type Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -#include - -// following functions are not implemented by RGMP math library -// don't use them -// declared here for cmath - -/* General Functions ********************************************************/ - -float ceilf (float x); -#ifdef CONFIG_HAVE_DOUBLE -//double ceil (double x); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double ceill (long double x); -#endif - -float floorf(float x); -#ifdef CONFIG_HAVE_DOUBLE -//double floor (double x); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double floorl(long double x); -#endif - -float fabsf (float x); -#ifdef CONFIG_HAVE_DOUBLE -//double fabs (double x); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double fabsl (long double x); -#endif - -float modff (float x, float *iptr); -#ifdef CONFIG_HAVE_DOUBLE -//double modf (double x, double *iptr); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double modfl (long double x, long double *iptr); -#endif - -float fmodf (float x, float div); -#ifdef CONFIG_HAVE_DOUBLE -//double fmod (double x, double div); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double fmodl (long double x, long double div); -#endif - -/* Exponential and Logarithmic Functions ************************************/ - -float powf (float b, float e); -#ifdef CONFIG_HAVE_DOUBLE -//double pow (double b, double e); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double powl (long double b, long double e); -#endif - -float expf (float x); -#ifdef CONFIG_HAVE_DOUBLE -//double exp (double x); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double expl (long double x); -#endif - -float logf (float x); -#ifdef CONFIG_HAVE_DOUBLE -//double log (double x); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double logl (long double x); -#endif - -float log10f(float x); -#ifdef CONFIG_HAVE_DOUBLE -//double log10 (double x); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double log10l(long double x); -#endif - -float log2f (float x); -#ifdef CONFIG_HAVE_DOUBLE -//double log2 (double x); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double log2l (long double x); -#endif - -float sqrtf (float x); -#ifdef CONFIG_HAVE_DOUBLE -//double sqrt (double x); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double sqrtl (long double x); -#endif - -float ldexpf(float x, int n); -#ifdef CONFIG_HAVE_DOUBLE -double ldexp (double x, int n); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double ldexpl(long double x, int n); -#endif - -float frexpf(float x, int *exp); -#ifdef CONFIG_HAVE_DOUBLE -double frexp (double x, int *exp); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double frexpl(long double x, int *exp); -#endif - -/* Trigonometric Functions **************************************************/ - -float sinf (float x); -#ifdef CONFIG_HAVE_DOUBLE -//double sin (double x); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double sinl (long double x); -#endif - -float cosf (float x); -#ifdef CONFIG_HAVE_DOUBLE -//double cos (double x); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double cosl (long double x); -#endif - -float tanf (float x); -#ifdef CONFIG_HAVE_DOUBLE -//double tan (double x); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double tanl (long double x); -#endif - -float asinf (float x); -#ifdef CONFIG_HAVE_DOUBLE -//double asin (double x); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double asinl (long double x); -#endif - -float acosf (float x); -#ifdef CONFIG_HAVE_DOUBLE -//double acos (double x); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double acosl (long double x); -#endif - -float atanf (float x); -#ifdef CONFIG_HAVE_DOUBLE -//double atan (double x); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double atanl (long double x); -#endif - -float atan2f(float y, float x); -#ifdef CONFIG_HAVE_DOUBLE -//double atan2 (double y, double x); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double atan2l(long double y, long double x); -#endif - -float sinhf (float x); -#ifdef CONFIG_HAVE_DOUBLE -//double sinh (double x); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double sinhl (long double x); -#endif - -float coshf (float x); -#ifdef CONFIG_HAVE_DOUBLE -//double cosh (double x); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double coshl (long double x); -#endif - -float tanhf (float x); -#ifdef CONFIG_HAVE_DOUBLE -//double tanh (double x); -#endif -#ifdef CONFIG_HAVE_LONG_DOUBLE -long double tanhl (long double x); -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __ARCH_RGMP_INCLUDE_MATH_H */ diff --git a/arch/rgmp/include/stdbool.h b/arch/rgmp/include/stdbool.h deleted file mode 100644 index eb1bee1adb..0000000000 --- a/arch/rgmp/include/stdbool.h +++ /dev/null @@ -1,84 +0,0 @@ -/**************************************************************************** - * arch/rgmp/include/stdbool.h - * - * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_RGMP_INCLUDE_STDBOOL_H -#define __ARCH_RGMP_INCLUDE_STDBOOL_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* bool, true, and false must be provided as macros so that they can be - * redefined by the application if necessary. - * - * NOTE: Under C99 'bool' is required to be defined to be the intrinsic type - * _Bool. However, in this NuttX context, we need backward compatibility - * to pre-C99 standards where _Bool is not an intrinsic type. Hence, we - * use _Bool8 as the underlying type. - */ - -#define true 1 -#define false 0 - -#define __bool_true_false_are_defined 1 - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* A byte is the smallest address memory element (at least in architectures - * that do not support bit banding). The requirement is only that type _Bool - * be large enough to hold the values 0 and 1. We select uint8_t to minimize - * the RAM footprint of the executable. - * - * NOTE: We can't actually define the type _Bool here. Under C99 _Bool is - * an intrinsic type and cannot be the target of a typedef. However, in this - * NuttX context, we also need backward compatibility to pre-C99 standards - * where _Bool is not an intrinsic type. We work around this by using _Bool8 - * as the underlying type. - */ - -typedef uint8_t _Bool8; - -#endif /* __ARCH_RGMP_INCLUDE_STDBOOL_H */ diff --git a/arch/rgmp/include/stdint.h b/arch/rgmp/include/stdint.h deleted file mode 100644 index 07b9ffdeeb..0000000000 --- a/arch/rgmp/include/stdint.h +++ /dev/null @@ -1,277 +0,0 @@ -/**************************************************************************** - * arch/rgmp/include/stdint.h - * - * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_RGMP_INCLUDE_STDINTL_H -#define __ARCH_RGMP_INCLUDE_STDINTL_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Limits of exact-width integer types */ - -#define INT8_MIN 0x80 -#define INT8_MAX 0x7f -#define UINT8_MAX 0xff - -#define INT16_MIN 0x8000 -#define INT16_MAX 0x7fff -#define UINT16_MAX 0xffff - -#ifdef __INT64_DEFINED -# define INT24_MIN 0x800000 -# define INT24_MAX 0x7fffff -# define UINT24_MAX 0xffffff -#endif - -#define INT32_MIN 0x80000000 -#define INT32_MAX 0x7fffffff -#define UINT32_MAX 0xffffffff - -#ifdef __INT64_DEFINED -# define INT64_MIN 0x8000000000000000 -# define INT64_MAX 0x7fffffffffffffff -# define UINT64_MAX 0xffffffffffffffff -#endif - -/* Limits of minimum-width integer types */ - -#define INT8_LEASTN_MIN 0x80 -#define INT8_LEASTN_MAX 0x7f -#define UINT8_LEASTN_MAX 0xff - -#define INT16_LEASTN_MIN 0x8000 -#define INT16_LEASTN_MAX 0x7fff -#define UINT16_LEASTN_MAX 0xffff - -#ifdef __INT64_DEFINED -# define INT24_LEASTN_MIN 0x800000 -# define INT24_LEASTN_MAX 0x7fffff -# define UINT24_LEASTN_MAX 0xffffff -#endif - -#define INT32_LEASTN_MIN 0x80000000 -#define INT32_LEASTN_MAX 0x7fffffff -#define UINT32_LEASTN_MAX 0xffffffff - -#ifdef __INT64_DEFINED -# define INT64_LEASTN_MIN 0x8000000000000000 -# define INT64_LEASTN_MAX 0x7fffffffffffffff -# define UINT64_LEASTN_MAX 0xffffffffffffffff -#endif - -/* Limits of fastest minimum-width integer types */ - -#define INT8_FASTN_MIN 0x80 -#define INT8_FASTN_MAX 0x7f -#define UINT8_FASTN_MAX 0xff - -#define INT16_FASTN_MIN 0x8000 -#define INT16_FASTN_MAX 0x7fff -#define UINT16_FASTN_MAX 0xffff - -#ifdef __INT64_DEFINED -# define INT24_FASTN_MIN 0x800000 -# define INT24_FASTN_MAX 0x7fffff -# define UINT24_FASTN_MAX 0xffffff -#endif - -#define INT32_FASTN_MIN 0x80000000 -#define INT32_FASTN_MAX 0x7fffffff -#define UINT32_FASTN_MAX 0xffffffff - -#ifdef __INT64_DEFINED -# define INT64_FASTN_MIN 0x8000000000000000 -# define INT64_FASTN_MAX 0x7fffffffffffffff -# define UINT64_FASTN_MAX 0xffffffffffffffff -#endif - -/* Limits of integer types capable of holding object pointers */ - -#define INTPTR_MIN PTR_MIN -#define INTPTR_MAX PTR_MIN -#define UINTPTR_MAX UPTR_MAX - -/* Limits of greatest-width integer types */ - -#ifdef __INT64_DEFINED -# define INTMAX_MIN INT64_MIN -# define INTMAX_MAX INT64_MAX - -# define UINTMAX_MIN UINT64_MIN -# define UINTMAX_MAX UINT64_MAX -#else -# define INTMAX_MIN INT32_MIN -# define INTMAX_MAX INT32_MAX - -# define UINTMAX_MIN UINT32_MIN -# define UINTMAX_MAX UINT32_MAX -#endif - -/* Macros for minimum-width integer constant expressions */ - -#if 0 /* REVISIT: Depends on architecture specific implementation */ -#define INT8_C(x) x -#define INT16_C(x) x -#define INT32_C(x) x ## L -#define INT64_C(x) x ## LL - -#define UINT8_C(x) x -#define UINT16_C(x) x -#define UINT32_C(x) x ## UL -#define UINT64_C(x) x ## ULL -#endif - -/* Macros for greatest-width integer constant expressions - -#ifdef CONFIG_HAVE_LONG_LONG -# define INTMAX_C(x) x ## LL -# define UINTMAX_C(x) x ## ULL -#else -# define INTMAX_C(x) x ## L -# define UINTMAX_C(x) x ## UL -#endif - -/* Limits of Other Integer Types */ - -#if 0 -# define PTRDIFF_MIN -# define PTRDIFF_MAX -#endif - -#ifdef CONFIG_SMALL_MEMORY -# define SIZE_MAX 0xffff -#else -# define SIZE_MAX 0xffffffff -#endif - -#if 0 -# define WCHAR_MIN -# define WCHAR_MAX - -# define WINT_MIN -# define WINT_MAX -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* Exact-width integer types. NOTE that these types are defined in - * architecture-specific logic with leading underscore character. This file - * typedef's these to the final name without the underscore character. This - * roundabout way of doings things allows the stdint.h to be removed from the - * include/ directory in the event that the user prefers to use the definitions - * provided by their toolchain header files. - */ - -#include - -/* Minimum-width integer types */ - -typedef _int8_t int_least8_t; -typedef _uint8_t uint_least8_t; - -typedef _int16_t int_least16_t; -typedef _uint16_t uint_least16_t; - -#ifdef __INT24_DEFINED -typedef _int24_t int_least24_t; -typedef _uint24_t uint_least24_t; -#else -typedef _int32_t int_least24_t; -typedef _uint32_t uint_least24_t; -#endif - -typedef _int32_t int_least32_t; -typedef _uint32_t uint_least32_t; - -#ifdef __INT64_DEFINED -typedef _int64_t int_least64_t; -typedef _uint64_t uint_least64_t; -#endif - -/* Fastest minimum-width integer types */ - -typedef _int8_t int_fast8_t; -typedef _uint8_t uint_fast8_t; - -typedef int int_fast16_t; -typedef unsigned int uint_fast16_t; - -#ifdef __INT24_DEFINED -typedef _int24_t int_fast24_t; -typedef _uint24_t uint_fast24_t; -#else -typedef _int32_t int_fast24_t; -typedef _uint32_t uint_fast24_t; -#endif - -typedef _int32_t int_fast32_t; -typedef _uint32_t uint_fast32_t; - -#ifdef __INT64_DEFINED -typedef _int64_t int_fast64_t; -typedef _uint64_t uint_fast64_t; -#endif - -/* Integer types capable of holding object pointers */ - -#ifndef CONFIG_ARCH_RGMP -typedef _intptr_t intptr_t; -typedef _uintptr_t uintptr_t; -#endif - -/* Greatest-width integer types */ - -#ifdef __INT64_DEFINED -typedef _int64_t intmax_t; -typedef _uint64_t uintmax_t; -#else -typedef _int32_t intmax_t; -typedef _uint32_t uintmax_t; -#endif - -#endif /* __ARCH_RGMP_INCLUDE_STDINTL_H */ diff --git a/arch/rgmp/include/types.h b/arch/rgmp/include/types.h deleted file mode 100644 index 1f515cb70c..0000000000 --- a/arch/rgmp/include/types.h +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * arch/rgmp/include/types.h - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name Gregory Nutt nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/* This file should never be included directed but, rather, - * only indirectly through sys/types.h - */ - -#ifndef __ARCH_RGMP_INCLUDE_TYPES_H -#define __ARCH_RGMP_INCLUDE_TYPES_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Type Declarations - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/* These are the sizes of the standard integer types. NOTE that these type - * names have a leading underscore character. This file will be included - * (indirectly) by include/stdint.h and typedef'ed to the final name without - * the underscore character. This roundabout way of doings things allows - * the stdint.h to be removed from the include/ directory in the event that - * the user prefers to use the definitions provided by their toolchain header - * files - */ - -typedef char _int8_t; -typedef unsigned char _uint8_t; - -typedef short _int16_t; -typedef unsigned short _uint16_t; - -typedef int _int32_t; -typedef unsigned int _uint32_t; - -typedef long long _int64_t; -typedef unsigned long long _uint64_t; -#define __INT64_DEFINED - -/* A pointer is 4 bytes */ - -typedef unsigned int _intptr_t; -typedef unsigned int _uintptr_t; - -/* This is the size of the interrupt state save returned by - * up_irq_save() - */ - -typedef unsigned int irqstate_t; - -#endif /* __ASSEMBLY__ */ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_RGMP_INCLUDE_TYPES_H */ diff --git a/arch/rgmp/include/x86/arch/com.h b/arch/rgmp/include/x86/arch/com.h deleted file mode 100644 index 89df901bb3..0000000000 --- a/arch/rgmp/include/x86/arch/com.h +++ /dev/null @@ -1,58 +0,0 @@ -/**************************************************************************** - * arch/rgmp/include/com.h - * - * Copyright (C) 2011 Yu Qiang. All rights reserved. - * Author: Yu Qiang - * - * This file is a part of NuttX: - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_RGMP_INCLUDE_COM_H -#define __ARCH_RGMP_INCLUDE_COM_H - -#define COM_SET_BAUD 1 -#define COM_SET_PARITY 2 -#define COM_NO_PARITY 0 -#define COM_ODD_PARITY 1 -#define COM_EVEN_PARITY 3 -#define COM_SET_STOPBITS 3 -#define COM_ONE_STOPBITS 0 -#define COM_TWO_STOPBITS 1 -#define COM_SET_BITS 4 -#define COM_8_BITS 3 -#define COM_7_BITS 2 -#define COM_6_BITS 1 -#define COM_5_BITS 0 - - -#endif diff --git a/arch/rgmp/include/x86/arch/subarch/arch.h b/arch/rgmp/include/x86/arch/subarch/arch.h deleted file mode 100644 index b88cb34155..0000000000 --- a/arch/rgmp/include/x86/arch/subarch/arch.h +++ /dev/null @@ -1,68 +0,0 @@ -/**************************************************************************** - * arch/rgmp/include/x86/arch/subarch/arch.h - * - * Copyright (C) 2011 Yu Qiang. All rights reserved. - * Author: Yu Qiang - * - * This file is a part of NuttX: - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __RGMP_ARCH_SUBARCH_ARCH_H -#define __RGMP_ARCH_SUBARCH_ARCH_H - -#ifndef __ASSEMBLY__ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include - -static inline void up_mdelay(uint32_t msec) -{ - hpet_ndelay(msec*1000000); -} - -static inline void up_udelay(uint32_t usec) -{ - hpet_ndelay(usec*1000); -} - -#ifdef __cplusplus -} -#endif - -#endif /* !__ASSEMBLY__ */ - -#endif diff --git a/arch/rgmp/src/.gitignore b/arch/rgmp/src/.gitignore deleted file mode 100644 index 8d209f76a4..0000000000 --- a/arch/rgmp/src/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -/.depend -/Make.dep -/board -/chip diff --git a/arch/rgmp/src/Makefile b/arch/rgmp/src/Makefile deleted file mode 100644 index 4fe3bbfbfd..0000000000 --- a/arch/rgmp/src/Makefile +++ /dev/null @@ -1,116 +0,0 @@ -############################################################################ -# arch/rgmp/src/Makefile -# -# Copyright (C) 2011-2012, 2014, 2016 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - --include $(TOPDIR)/Make.defs -include $(CONFIG_RGMP_SUBARCH)/Make.defs - -RGMP_ARCH_ASRCS := $(addprefix $(CONFIG_RGMP_SUBARCH)/,$(RGMP_ARCH_ASRCS)) -RGMP_ARCH_CSRCS := $(addprefix $(CONFIG_RGMP_SUBARCH)/,$(RGMP_ARCH_CSRCS)) - -CPPFLAGS += -I$(TOPDIR)/sched -I$(TOPDIR)/fs $(EXTRADEFINES) -CFLAGS += -I$(TOPDIR)/sched -I$(TOPDIR)/fs $(EXTRADEFINES) -CXXFLAGS += -I$(TOPDIR)/sched -I$(TOPDIR)/fs $(EXTRADEFINES) - -ASRCS = $(RGMP_ARCH_ASRCS) -CSRCS = nuttx.c cxx.c $(RGMP_ARCH_CSRCS) -AOBJS = $(ASRCS:.S=$(OBJEXT)) -COBJS = $(CSRCS:.c=$(OBJEXT)) - -SRCS = $(ASRCS) $(CSRCS) -OBJS = $(AOBJS) $(COBJS) - -LINKSRCS = rgmp.c bridge.c -LINKOBJS = $(LINKSRCS:.c=$(OBJEXT)) - -# Override in Make.defs if linker is not 'ld' - -LDSTARTGROUP ?= --start-group -LDENDGROUP ?= --end-group - -LDFLAGS += -T$(RGMPLKSCPT) -LDLIBS = $(patsubst %.a,%,$(patsubst lib%,-l%,$(LINKLIBS))) -LIBPATHS += -L"$(TOPDIR)/lib" -L$(RGMPLIBDIR) -LDLIBS += -lrgmp $(shell "$(CC)" -print-libgcc-file-name) - -all: libarch$(LIBEXT) - -.PHONY: clean distclean depend - -$(AOBJS): %$(OBJEXT): %.S - $(call ASSEMBLE, $<, $@) - -$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c - $(call COMPILE, $<, $@) - -# The architecture-specific library - -libarch$(LIBEXT): $(OBJS) - $(call ARCHIVE, $@, $(OBJS)) - -# Generate the final NuttX binary by linking the host-specific objects with the NuttX -# specific objects (with munged names) - -nuttx$(EXEEXT): $(LINKOBJS) - @echo "LD: nuttx$(EXEEXT)" - @$(LD) $(LDFLAGS) $(LIBPATHS) $(LINKOBJS) $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LDENDGROUP) -o $(TOPDIR)/$@ - @$(OBJDUMP) -S $(TOPDIR)/$@ > $(TOPDIR)/nuttx.asm - @$(NM) -n $(TOPDIR)/$@ > $(TOPDIR)/nuttx.sym - @$(OBJCOPY) -S -O binary $(TOPDIR)/$@ nuttx.img - @cp nuttx.img $(TOPDIR)/kernel.img - -# This is part of the top-level export target - -expport_startup: - -# Dependencies - -.depend: Makefile $(SRCS) $(LINKSRCS) - @$(MKDEP) "$(CC)" -- $(CFLAGS) -- $(SRCS) $(LINKSRCS) >Make.dep - @touch $@ - -depend: .depend - -clean: - $(call DELFILE, "$(TOPDIR)/arch/rgmp/src/x86/*.o") - $(call DELFILE, "$(TOPDIR)/kernel.img") - $(call DELFILE, nuttx.img) - $(call DELFILE, libarch$(LIBEXT)) - $(call CLEAN) - -distclean: clean - $(call DELFILE, Make.dep) - $(call DELFILE, .depend) - --include Make.dep diff --git a/arch/rgmp/src/arm/Make.defs b/arch/rgmp/src/arm/Make.defs deleted file mode 100644 index e21b046e89..0000000000 --- a/arch/rgmp/src/arm/Make.defs +++ /dev/null @@ -1,42 +0,0 @@ -############################################################################ -# rgmp/arm/Make.defs -# -# Copyright (C) 2011 Yu Qiang. All rights reserved. -# Author: Yu Qiang -# -# This file is a part of NuttX: -# -# Copyright (C) 2011 Gregory Nutt. All rights reserved. -# -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name Gregory Nutt nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -RGMP_ARCH_ASRCS = sigentry.S -RGMP_ARCH_CSRCS = arch_nuttx.c diff --git a/arch/rgmp/src/arm/arch_nuttx.c b/arch/rgmp/src/arm/arch_nuttx.c deleted file mode 100644 index dd737946d9..0000000000 --- a/arch/rgmp/src/arm/arch_nuttx.c +++ /dev/null @@ -1,89 +0,0 @@ -/**************************************************************************** - * arch/rgmp/src/arm/arch_nuttx.c - * - * Copyright (C) 2011 Yu Qiang. All rights reserved. - * Author: Yu Qiang - * - * This file is a part of NuttX: - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#include -#include - -#include -#include - -void nuttx_arch_init(void) -{ -} - -void nuttx_arch_exit(void) -{ -} - -void up_initial_state(struct tcb_s *tcb) -{ - struct Trapframe *tf; - - if (tcb->pid != 0) - { - tf = (struct Trapframe *)tcb->adj_stack_ptr-1; - memset(tf, 0, sizeof(struct Trapframe)); - tf->tf_cpsr = SVC_MOD; - tf->tf_pc = (uint32_t)tcb->start; - tcb->xcp.tf = tf; - } -} - -void push_xcptcontext(struct xcptcontext *xcp) -{ - xcp->save_eip = xcp->tf->tf_pc; - xcp->save_eflags = xcp->tf->tf_cpsr; - - // set interrupts disabled - - xcp->tf->tf_pc = (uint32_t)up_sigentry; - xcp->tf->tf_cpsr |= CPSR_IF; -} - -void pop_xcptcontext(struct xcptcontext *xcp) -{ - xcp->tf->tf_pc = xcp->save_eip; - xcp->tf->tf_cpsr = xcp->save_eflags; -} - -void raise(void) -{ - -} - diff --git a/arch/rgmp/src/arm/sigentry.S b/arch/rgmp/src/arm/sigentry.S deleted file mode 100644 index 1e413450bf..0000000000 --- a/arch/rgmp/src/arm/sigentry.S +++ /dev/null @@ -1,49 +0,0 @@ -/**************************************************************************** - * arch/rgmp/src/arm/sigentry.S - * - * Copyright (C) 2011 Yu Qiang. All rights reserved. - * Author: Yu Qiang - * - * This file is a part of NuttX: - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - - .globl up_sigentry -up_sigentry: - sub sp, sp, #68 @ 68 is the size of Trapframe - mov r0, sp - bl up_sigdeliver - add sp, sp, #4 @ skip current_task - pop {r0-r12, lr} - rfefd sp! - - \ No newline at end of file diff --git a/arch/rgmp/src/bridge.c b/arch/rgmp/src/bridge.c deleted file mode 100644 index 320019ba9f..0000000000 --- a/arch/rgmp/src/bridge.c +++ /dev/null @@ -1,134 +0,0 @@ -/**************************************************************************** - * arch/rgmp/src/bridge.c - * - * Copyright (C) 2011 Yu Qiang. All rights reserved. - * Author: Yu Qiang - * - * This file is a part of NuttX: - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#include -#include -#include -#include -#include "inode/inode.h" -#include -#include -#include -#include -#include -#include - -struct bridge -{ - struct rgmp_bridge *b; - sem_t rd_lock; - sem_t wr_lock; -}; - -static ssize_t up_bridge_read(struct file *filep, char *buffer, size_t len) -{ - ssize_t ret; - struct bridge *b = filep->f_inode->i_private; - - sem_wait(&b->rd_lock); - ret = rgmp_bridge_read(b->b, buffer, len, 0); - sem_post(&b->rd_lock); - return ret; -} - -static ssize_t up_bridge_write(struct file *filep, const char *buffer, size_t len) -{ - ssize_t ret; - struct bridge *b = filep->f_inode->i_private; - - sem_wait(&b->wr_lock); - ret = rgmp_bridge_write(b->b, (char *)buffer, len, 0); - sem_post(&b->wr_lock); - return ret; -} - -static int up_bridge_open(struct file *filep) -{ - return 0; -} - -static int up_bridge_close(struct file *filep) -{ - return 0; -} - -static const struct file_operations up_bridge_fops = -{ - .read = up_bridge_read, - .write = up_bridge_write, - .open = up_bridge_open, - .close = up_bridge_close, -}; - -int rtos_bridge_init(struct rgmp_bridge *b) -{ - int errcode; - struct bridge *bridge; - char path[30] = {'/', 'd', 'e', 'v', '/'}; - - if ((bridge = kmm_malloc(sizeof(*bridge))) == NULL) - goto err0; - - bridge->b = b; - if ((errcode = sem_init(&bridge->rd_lock, 0, 1)) == ERROR) - goto err1; - - if ((errcode = sem_init(&bridge->wr_lock, 0, 1)) == ERROR) - goto err1; - - // make rgmp_bridge0 to be the console - - if (strcmp(b->vdev->name, "rgmp_bridge0") == 0) - strlcpy(path + 5, "console", 25); - else - strlcpy(path + 5, b->vdev->name, 25); - - if ((errcode = register_driver(path, &up_bridge_fops, 0666, bridge)) == ERROR) - { - cprintf("NuttX: register bridge %s fail\n", b->vdev->name); - goto err1; - } - - return 0; - -err1: - kmm_free(bridge); -err0: - return -1; -} diff --git a/arch/rgmp/src/cxx.c b/arch/rgmp/src/cxx.c deleted file mode 100644 index 8dfc6a697b..0000000000 --- a/arch/rgmp/src/cxx.c +++ /dev/null @@ -1,19 +0,0 @@ -#include -#include - -int stderr = 2; - -void __stack_chk_fail_local(void) -{ - panic("stack check fail\n"); -} - -int __sprintf_chk(char *str, int flag, size_t strlen, const char *format) -{ - return snprintf(str, strlen, format); -} - -int dl_iterate_phdr(void* arg1, void* arg2) -{ - return -1; -} diff --git a/arch/rgmp/src/nuttx.c b/arch/rgmp/src/nuttx.c deleted file mode 100644 index 07faf590fd..0000000000 --- a/arch/rgmp/src/nuttx.c +++ /dev/null @@ -1,751 +0,0 @@ -/**************************************************************************** - * arch/rgmp/src/nuttx.c - * - * Copyright (C) 2011 Yu Qiang. All rights reserved. - * Author: Yu Qiang - * - * This file is a part of NuttX: - * - * Copyright (C) 2011, 2014 Gregory Nutt. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "task/task.h" -#include "sched/sched.h" -#include "group/group.h" - -struct tcb_s *current_task = NULL; - -/* This function is called in non-interrupt context - * to switch tasks. - * Assumption: global interrupt is disabled. - */ - -static inline void up_switchcontext(struct tcb_s *ctcb, struct tcb_s *ntcb) -{ - // do nothing if two tasks are the same - - if (ctcb == ntcb) - return; - - // this function can not be called in interrupt - - if (up_interrupt_context()) { - panic("%s: try to switch context in interrupt\n", __func__); - } - - // start switch - - current_task = ntcb; - rgmp_context_switch(ctcb ? &ctcb->xcp.ctx : NULL, &ntcb->xcp.ctx); -} - -void up_initialize(void) -{ - extern pidhash_t g_pidhash[]; - extern void vdev_init(void); - extern void nuttx_arch_init(void); - - /* Initialize the current_task to g_idletcb */ - - current_task = g_pidhash[PIDHASH(0)].tcb; - - /* OS memory alloc system is ready */ - - use_os_kmalloc = 1; - - /* rgmp vdev init */ - - vdev_init(); - - nuttx_arch_init(); - -#ifdef CONFIG_PM - /* Initialize the power management subsystem. This MCU-specific function - * must be called *very* early in the initialization sequence *before* any - * other device drivers are initialized (since they may attempt to register - * with the power management subsystem). - */ - - up_pminitialize(); -#endif - -#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_PSEUDOTERM_SUSV1) - /* Register the master pseudo-terminal multiplexor device */ - - (void)ptmx_register(); -#endif - - /* Early initialization of the system logging device. Some SYSLOG channel - * can be initialized early in the initialization sequence because they - * depend on only minimal OS initialization. - */ - - syslog_initialize(SYSLOG_INIT_EARLY); - - /* Register devices */ - -#if CONFIG_NFILE_DESCRIPTORS > 0 - -#if defined(CONFIG_DEV_NULL) - devnull_register(); /* Standard /dev/null */ -#endif - -#if defined(CONFIG_DEV_RANDOM) - devrandom_register(); /* Standard /dev/random */ -#endif - -#if defined(CONFIG_DEV_URANDOM) - devurandom_register(); /* Standard /dev/urandom */ -#endif - -#if defined(CONFIG_DEV_ZERO) - devzero_register(); /* Standard /dev/zero */ -#endif - -#if defined(CONFIG_DEV_LOOP) - loop_register(); /* Standard /dev/loop */ -#endif -#endif /* CONFIG_NFILE_DESCRIPTORS */ - -#if defined(CONFIG_SCHED_INSTRUMENTATION_BUFFER) && \ - defined(CONFIG_DRIVER_NOTE) - note_register(); /* Non-standard /dev/note */ -#endif - -#if defined(CONFIG_CRYPTO) - /* Initialize the HW crypto and /dev/crypto */ - - up_cryptoinitialize(); -#endif - -#if CONFIG_NFILE_DESCRIPTORS > 0 && defined(CONFIG_CRYPTO_CRYPTODEV) - devcrypto_register(); -#endif - - /* Enable interrupt */ - - local_irq_enable(); -} - -void up_idle(void) -{ - arch_hlt(); -} - -void up_allocate_heap(void **heap_start, size_t *heap_size) -{ - void *boot_freemem = boot_alloc(0, sizeof(int)); - *heap_start = boot_freemem; - *heap_size = KERNBASE + kmem_size - (uint32_t)boot_freemem; -} - -int up_create_stack(struct tcb_s *tcb, size_t stack_size, uint8_t ttype) -{ - uint32_t *stack_alloc_ptr; - int ret = ERROR; - size_t *adj_stack_ptr; - - /* Move up to next even word boundary if necessary */ - - size_t adj_stack_size = (stack_size + 3) & ~3; - size_t adj_stack_words = adj_stack_size >> 2; - - /* Allocate the memory for the stack */ - -#if defined(CONFIG_BUILD_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP) - /* Use the kernel allocator if this is a kernel thread */ - - if (ttype == TCB_FLAG_TTYPE_KERNEL) { - stack_alloc_ptr = (uint32_t *)kmm_malloc(stack_size); - } else -#endif - { - stack_alloc_ptr = (uint32_t*)kumm_malloc(adj_stack_size); - } - if (stack_alloc_ptr) { - /* This is the address of the last word in the allocation */ - - adj_stack_ptr = &stack_alloc_ptr[adj_stack_words - 1]; - - /* Save the values in the TCB */ - - tcb->adj_stack_size = adj_stack_size; - tcb->stack_alloc_ptr = stack_alloc_ptr; - tcb->adj_stack_ptr = (void *)((unsigned int)adj_stack_ptr & ~7); - ret = OK; - } - return ret; -} - -int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size) -{ - /* Move up to next even word boundary if necessary */ - - size_t adj_stack_size = stack_size & ~3; - size_t adj_stack_words = adj_stack_size >> 2; - - /* This is the address of the last word in the allocation */ - - size_t *adj_stack_ptr = &((size_t*)stack)[adj_stack_words - 1]; - - /* Save the values in the TCB */ - - tcb->adj_stack_size = adj_stack_size; - tcb->stack_alloc_ptr = stack; - tcb->adj_stack_ptr = (void *)((unsigned int)adj_stack_ptr & ~7); - return OK; -} - -FAR void *up_stack_frame(FAR struct tcb_s *tcb, size_t frame_size) -{ - uintptr_t topaddr; - - /* Align the frame_size */ - - frame_size = (frame_size + 3) & ~3; - - /* Is there already a stack allocated? Is it big enough? */ - - if (!tcb->stack_alloc_ptr || tcb->adj_stack_size <= frame_size) { - return NULL; - } - - /* Save the adjusted stack values in the struct tcb_s */ - - topaddr = (uintptr_t)tcb->adj_stack_ptr - frame_size; - tcb->adj_stack_ptr = (FAR void *)topaddr; - tcb->adj_stack_size -= frame_size; - - /* Reset the initial state */ - - up_initial_state(tcb); - - /* And return a pointer to the allocated memory region */ - - return (FAR void *)(topaddr + sizeof(uint32_t)); -} - -void up_release_stack(struct tcb_s *dtcb, uint8_t ttype) -{ - /* Is there a stack allocated? */ - - if (dtcb->stack_alloc_ptr) { -#if defined(CONFIG_BUILD_KERNEL) && defined(CONFIG_MM_KERNEL_HEAP) - /* Use the kernel allocator if this is a kernel thread */ - - if (ttype == TCB_FLAG_TTYPE_KERNEL) { - kmm_free(dtcb->stack_alloc_ptr); - } else -#endif - { - /* Use the user-space allocator if this is a task or pthread */ - - kumm_free(dtcb->stack_alloc_ptr); - } - } - - /* Mark the stack freed */ - - dtcb->stack_alloc_ptr = NULL; - dtcb->adj_stack_size = 0; - dtcb->adj_stack_ptr = NULL; -} - -/**************************************************************************** - * Name: up_block_task - * - * Description: - * The currently executing task at the head of - * the ready to run list must be stopped. Save its context - * and move it to the inactive list specified by task_state. - * - * This function is called only from the NuttX scheduling - * logic. Interrupts will always be disabled when this - * function is called. - * - * Inputs: - * tcb: Refers to a task in the ready-to-run list (normally - * the task at the head of the list). It most be - * stopped, its context saved and moved into one of the - * waiting task lists. It it was the task at the head - * of the ready-to-run list, then a context to the new - * ready to run task must be performed. - * task_state: Specifies which waiting task list should be - * hold the blocked task TCB. - * - ****************************************************************************/ - -void up_block_task(struct tcb_s *tcb, tstate_t task_state) -{ - /* Verify that the context switch can be performed */ - - if ((tcb->task_state < FIRST_READY_TO_RUN_STATE) || - (tcb->task_state > LAST_READY_TO_RUN_STATE)) - { - _warn("%s: task sched error\n", __func__); - return; - } - else - { - struct tcb_s *rtcb = current_task; - bool switch_needed; - - /* Remove the tcb task from the ready-to-run list. If we - * are blocking the task at the head of the task list (the - * most likely case), then a context switch to the next - * ready-to-run task is needed. In this case, it should - * also be true that rtcb == tcb. - */ - - switch_needed = sched_removereadytorun(tcb); - - /* Add the task to the specified blocked task list */ - - sched_addblocked(tcb, (tstate_t)task_state); - - /* Now, perform the context switch if one is needed */ - - if (switch_needed) - { - struct tcb_s *nexttcb; - - /* Update scheduler parameters */ - - sched_suspend_scheduler(rtcb); - - /* this part should not be executed in interrupt context */ - - if (up_interrupt_context()) - { - panic("%s: %d\n", __func__, __LINE__); - } - - /* If there are any pending tasks, then add them to the ready-to-run - * task list now. It should be the up_realease_pending() called from - * sched_unlock() to do this for disable preemption. But it block - * itself, so it's OK. - */ - - if (g_pendingtasks.head) - { - _warn("Disable preemption failed for task block itself\n"); - sched_mergepending(); - } - - nexttcb = this_task(); - -#ifdef CONFIG_ARCH_ADDRENV - /* Make sure that the address environment for the previously - * running task is closed down gracefully (data caches dump, - * MMU flushed) and set up the address environment for the new - * thread at the head of the ready-to-run list. - */ - - (void)group_addrenv(nexttcb); -#endif - /* Reset scheduler parameters */ - - sched_resume_scheduler(nexttcb); - - /* context switch */ - - up_switchcontext(rtcb, nexttcb); - } - } -} - -/**************************************************************************** - * Name: up_unblock_task - * - * Description: - * A task is currently in an inactive task list - * but has been prepped to execute. Move the TCB to the - * ready-to-run list, restore its context, and start execution. - * - * Inputs: - * tcb: Refers to the tcb to be unblocked. This tcb is - * in one of the waiting tasks lists. It must be moved to - * the ready-to-run list and, if it is the highest priority - * ready to run taks, executed. - * - ****************************************************************************/ - -void up_unblock_task(struct tcb_s *tcb) -{ - /* Verify that the context switch can be performed */ - - if ((tcb->task_state < FIRST_BLOCKED_STATE) || - (tcb->task_state > LAST_BLOCKED_STATE)) - { - _warn("%s: task sched error\n", __func__); - return; - } - else - { - struct tcb_s *rtcb = current_task; - - /* Remove the task from the blocked task list */ - - sched_removeblocked(tcb); - - /* Add the task in the correct location in the prioritized - * ready-to-run task list. - */ - - if (sched_addreadytorun(tcb) && !up_interrupt_context()) - { - /* The currently active task has changed! */ - /* Update scheduler parameters */ - - sched_suspend_scheduler(rtcb); - - /* Are we in an interrupt handler? */ - - struct tcb_s *nexttcb = this_task(); - -#ifdef CONFIG_ARCH_ADDRENV - /* Make sure that the address environment for the previously - * running task is closed down gracefully (data caches dump, - * MMU flushed) and set up the address environment for the new - * thread at the head of the ready-to-run list. - - (void)group_addrenv(nexttcb); -#endif - /* Update scheduler parameters */ - - sched_resume_scheduler(nexttcb); - - /* context switch */ - - up_switchcontext(rtcb, nexttcb); - } - } -} - -/* This function is called from sched_unlock() which will check not - * in interrupt context and disable interrupt. - */ - -void up_release_pending(void) -{ - struct tcb_s *rtcb = current_task; - - /* Merge the g_pendingtasks list into the ready-to-run task list */ - - if (sched_mergepending()) - { - struct tcb_s *nexttcb = this_task(); - - /* The currently active task has changed! We will need to switch - * contexts. - * - * Update scheduler parameters. - */ - - sched_suspend_scheduler(rtcb); - -#ifdef CONFIG_ARCH_ADDRENV - /* Make sure that the address environment for the previously - * running task is closed down gracefully (data caches dump, - * MMU flushed) and set up the address environment for the new - * thread at the head of the ready-to-run list. - */ - - (void)group_addrenv(nexttcb); -#endif - /* Update scheduler parameters */ - - sched_resume_scheduler(nexttcb); - - /* context switch */ - - up_switchcontext(rtcb, nexttcb); - } -} - -void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) -{ - /* Verify that the caller is sane */ - - if (tcb->task_state < FIRST_READY_TO_RUN_STATE || - tcb->task_state > LAST_READY_TO_RUN_STATE -#if SCHED_PRIORITY_MIN > UINT8_MIN - || priority < SCHED_PRIORITY_MIN -#endif -#if SCHED_PRIORITY_MAX < UINT8_MAX - || priority > SCHED_PRIORITY_MAX -#endif - ) - { - _warn("%s: task sched error\n", __func__); - return; - } - else - { - struct tcb_s *rtcb = current_task; - bool switch_needed; - - /* Remove the tcb task from the ready-to-run list. - * sched_removereadytorun will return true if we just - * remove the head of the ready to run list. - */ - - switch_needed = sched_removereadytorun(tcb); - - /* Setup up the new task priority */ - - tcb->sched_priority = (uint8_t)priority; - - /* Return the task to the specified blocked task list. - * sched_addreadytorun will return true if the task was - * added to the new list. We will need to perform a context - * switch only if the EXCLUSIVE or of the two calls is non-zero - * (i.e., one and only one the calls changes the head of the - * ready-to-run list). - */ - - switch_needed ^= sched_addreadytorun(tcb); - - /* Now, perform the context switch if one is needed */ - - if (switch_needed && !up_interrupt_context()) - { - struct tcb_s *nexttcb; - - /* If there are any pending tasks, then add them to the ready-to-run - * task list now. It should be the up_realease_pending() called from - * sched_unlock() to do this for disable preemption. But it block - * itself, so it's OK. - */ - - if (g_pendingtasks.head) - { - _warn("Disable preemption failed for reprioritize task\n"); - sched_mergepending(); - } - - /* Update scheduler parameters */ - - sched_suspend_scheduler(rtcb); - - /* Get the TCB of the new task to run */ - - nexttcb = this_task(); - -#ifdef CONFIG_ARCH_ADDRENV - /* Make sure that the address environment for the previously - * running task is closed down gracefully (data caches dump, - * MMU flushed) and set up the address environment for the new - * thread at the head of the ready-to-run list. - */ - - (void)group_addrenv(nexttcb); -#endif - /* Update scheduler parameters */ - - sched_resume_scheduler(nexttcb); - - /* context switch */ - - up_switchcontext(rtcb, nexttcb); - } - } -} - -void _exit(int status) -{ - struct tcb_s* tcb; - - /* Destroy the task at the head of the ready to run list. */ - - (void)task_exit(); - - /* Now, perform the context switch to the new ready-to-run task at the - * head of the list. - */ - - tcb = this_task(); - -#ifdef CONFIG_ARCH_ADDRENV - /* Make sure that the address environment for the previously running - * task is closed down gracefully (data caches dump, MMU flushed) and - * set up the address environment for the new thread at the head of - * the ready-to-run list. - */ - - (void)group_addrenv(tcb); -#endif - - /* Then switch contexts */ - - up_switchcontext(NULL, tcb); -} - -void up_assert(const uint8_t *filename, int line) -{ - fprintf(stderr, "Assertion failed at file:%s line: %d\n", filename, line); - -#ifdef CONFIG_BOARD_CRASHDUMP - board_crashdump(up_getsp(), this_task(), filename, line); -#endif - - // in interrupt context or idle task means kernel error - // which will stop the OS - // if in user space just terminate the task - if (up_interrupt_context() || current_task->pid == 0) { - panic("%s: %d\n", __func__, __LINE__); - } - else { - exit(EXIT_FAILURE); - } -} - -#ifndef CONFIG_DISABLE_SIGNALS - -void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) -{ - /* Refuse to handle nested signal actions */ - if (!tcb->xcp.sigdeliver) { - int flags; - - /* Make sure that interrupts are disabled */ - local_irq_save(flags); - - // First, handle some special cases when the signal is - // being delivered to the currently executing task. - if (tcb == current_task) { - // CASE 1: We are not in an interrupt handler and - // a task is signalling itself for some reason. - if (!up_interrupt_context()) { - // In this case just deliver the signal now. - sigdeliver(tcb); - } - // CASE 2: We are in an interrupt handler AND the - // interrupted task is the same as the one that - // must receive the signal. - else { - tcb->xcp.sigdeliver = sigdeliver; - } - } - - // Otherwise, we are (1) signaling a task is not running - // from an interrupt handler or (2) we are not in an - // interrupt handler and the running task is signalling - // some non-running task. - else { - tcb->xcp.sigdeliver = sigdeliver; - push_xcptcontext(&tcb->xcp); - } - - local_irq_restore(flags); - } -} - -#endif /* !CONFIG_DISABLE_SIGNALS */ - - -bool up_interrupt_context(void) -{ - if (nest_irq) - return true; - return false; -} - -#ifndef CONFIG_ARCH_NOINTC -void up_disable_irq(int irq) -{ - -} - -void up_enable_irq(int irq) -{ - -} -#endif - -#ifdef CONFIG_ARCH_IRQPRIO -int up_prioritize_irq(int irq, int priority) -{ - -} -#endif - -void up_sigdeliver(struct Trapframe *tf) -{ - sig_deliver_t sigdeliver; - - pop_xcptcontext(¤t_task->xcp); - sigdeliver = current_task->xcp.sigdeliver; - current_task->xcp.sigdeliver = NULL; - local_irq_enable(); - sigdeliver(current_task); - local_irq_disable(); -} - -#if defined(CONFIG_HAVE_CXX) && defined(CONFIG_HAVE_CXXINITIALIZE) - -void up_cxxinitialize(void) -{ - rgmp_cxx_init(); -} - -#endif - - - - - - - - diff --git a/arch/rgmp/src/rgmp.c b/arch/rgmp/src/rgmp.c deleted file mode 100644 index 104591752d..0000000000 --- a/arch/rgmp/src/rgmp.c +++ /dev/null @@ -1,175 +0,0 @@ -/**************************************************************************** - * arch/rgmp/src/rgmp.c - * - * Copyright (C) 2011 Yu Qiang. All rights reserved. - * Author: Yu Qiang - * - * This file is a part of NuttX: - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -int nest_irq = 0; - -// The default time is 10ms -// REVISIT: tick time is given by CONFIG_USEC_PER_TICK. MSEC_PER_TICK may -// be zero. - -#ifdef MSEC_PER_TICK -const unsigned int rtos_tick_time = MSEC_PER_TICK; -#else -const unsigned int rtos_tick_time = 10; -#endif - -void rtos_entry(void) -{ - os_start(); -} - -void *rtos_get_page(void) -{ - return memalign(PTMEMSIZE, PTMEMSIZE); -} - -void rtos_free_page(void *page) -{ - free(page); -} - -void *rtos_kmalloc(int size) -{ - return kmm_malloc(size); -} - -void rtos_kfree(void *addr) -{ - kmm_free(addr); -} - -/* The interrupt can be nested. The pair of rtos_enter_interrupt() - * and rtos_exit_interrupt() make sure the context switch is - * performed only in the last IRQ exit. - */ - -void rtos_enter_interrupt(void) -{ - nest_irq++; -} - -void rtos_exit_interrupt(void) -{ - local_irq_disable(); - nest_irq--; - if (!nest_irq) - { - struct tcb_s *rtcb = current_task; - struct tcb_s *ntcb; - - if (rtcb->xcp.sigdeliver) - { - rtcb->xcp.ctx.tf = g_current_regs; - push_xcptcontext(&rtcb->xcp); - } - - ntcb = this_task(); - - /* Switch needed */ - - if (rtcb != ntcb) - { - rtcb->xcp.ctx.tf = g_current_regs; - current_task = ntcb; - rgmp_switch_to(&ntcb->xcp.ctx); - } - } -} - -void rtos_timer_isr(void *data) -{ - sched_process_timer(); -} - -/* RTOS semaphore operation */ - -int rtos_sem_init(struct semaphore *sem, int val) -{ - if ((sem->sem = kmm_malloc(sizeof(sem_t))) == NULL) - return -1; - return sem_init(sem->sem, 0, val); -} - -int rtos_sem_up(struct semaphore *sem) -{ - return sem_post(sem->sem); -} - -int rtos_sem_down(struct semaphore *sem) -{ - return sem_wait(sem->sem); -} - -void rtos_stop_running(void) -{ - extern void nuttx_arch_exit(void); - - local_irq_disable(); - - nuttx_arch_exit(); - - while (1) - { - arch_hlt(); - } -} - -int rtos_vnet_init(struct rgmp_vnet *vnet) -{ - extern int vnet_init(struct rgmp_vnet *vnet); - - return vnet_init(vnet); -} diff --git a/arch/rgmp/src/x86/Make.defs b/arch/rgmp/src/x86/Make.defs deleted file mode 100644 index fcf3180d82..0000000000 --- a/arch/rgmp/src/x86/Make.defs +++ /dev/null @@ -1,42 +0,0 @@ -############################################################################ -# rgmp/x86/Make.defs -# -# Copyright (C) 2011 Yu Qiang. All rights reserved. -# Author: Yu Qiang -# -# This file is a part of NuttX: -# -# Copyright (C) 2011 Gregory Nutt. All rights reserved. -# -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name Gregory Nutt nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -RGMP_ARCH_ASRCS = sigentry.S -RGMP_ARCH_CSRCS = com.c arch_nuttx.c diff --git a/arch/rgmp/src/x86/arch_nuttx.c b/arch/rgmp/src/x86/arch_nuttx.c deleted file mode 100644 index 32f919cd78..0000000000 --- a/arch/rgmp/src/x86/arch_nuttx.c +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * arch/rgmp/src/x86/arch_nuttx.c - * - * Copyright (C) 2011 Yu Qiang. All rights reserved. - * Author: Yu Qiang - * - * This file is a part of NuttX: - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#include -#include -#include - -#include -#include - -void nuttx_arch_init(void) -{ - extern void e1000_mod_init(void); - extern void up_serialinit(void); - - // setup COM device - up_serialinit(); - -#ifdef CONFIG_NET_E1000 - // setup e1000 - e1000_mod_init(); -#endif -} - -void nuttx_arch_exit(void) -{ - extern void e1000_mod_exit(void); - -#ifdef CONFIG_NET_E1000 - e1000_mod_exit(); -#endif -} - -void up_initial_state(struct tcb_s *tcb) -{ - struct Trapframe *tf; - - if (tcb->pid) - { - tf = (struct Trapframe *)tcb->adj_stack_ptr - 1; - rgmp_setup_context(&tcb->xcp.ctx, tf, tcb->start, 1); - } - else - { - rgmp_setup_context(&tcb->xcp.ctx, NULL, NULL, 0); - } -} - -void push_xcptcontext(struct xcptcontext *xcp) -{ - xcp->save_eip = xcp->ctx.tf->tf_eip; - xcp->save_eflags = xcp->ctx.tf->tf_eflags; - - // set up signal entry with interrupts disabled - - xcp->ctx.tf->tf_eip = (uint32_t)up_sigentry; - xcp->ctx.tf->tf_eflags = 0; -} - -void pop_xcptcontext(struct xcptcontext *xcp) -{ - xcp->ctx.tf->tf_eip = xcp->save_eip; - xcp->ctx.tf->tf_eflags = xcp->save_eflags; -} - diff --git a/arch/rgmp/src/x86/com.c b/arch/rgmp/src/x86/com.c deleted file mode 100644 index 8c8d076cc0..0000000000 --- a/arch/rgmp/src/x86/com.c +++ /dev/null @@ -1,667 +0,0 @@ -/**************************************************************************** - * arch/rgmp/src/x86/com.c - * - * Copyright (C) 2011 Yu Qiang. All rights reserved. - * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. - * Authors: Yu Qiang - * Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define COM1 0x3F8 -#define COM2 0x2f8 -#define COM3 0x3e8 -#define COM4 0x2e8 - -#define COM_RX 0 // In: Receive buffer (DLAB=0) -#define COM_DLL 0 // Out: Divisor Latch Low (DLAB=1) -#define COM_TX 0 // Out: Transmit buffer (DLAB=0) -#define COM_DLM 1 // Out: Divisor Latch High (DLAB=1) -#define COM_IER 1 // Out: Interrupt Enable Register -#define COM_IER_TEI 0x02 // Enable transmit buffer empty interrupt -#define COM_IER_RDI 0x01 // Enable receiver data interrupt -#define COM_IIR 2 // In: Interrupt ID Register -#define COM_FCR 2 // Out: FIFO Control Register -#define COM_LCR 3 // Out: Line Control Register -#define COM_LCR_DLAB 0x80 // Divisor latch access bit -#define COM_LCR_WLEN8 0x03 // Wordlength: 8 bits -#define COM_MCR 4 // Out: Modem Control Register -#define COM_MCR_RTS 0x02 // RTS complement -#define COM_MCR_DTR 0x01 // DTR complement -#define COM_MCR_OUT2 0x08 // Out2 complement -#define COM_LSR 5 // In: Line Status Register -#define COM_LSR_DATA 0x01 // Data available -#define COM_LSR_ETR 0x20 // buffer has space -#define COM_LSR_EDR 0x40 // buffer empty - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -#ifndef CONFIG_COM_RXBUFSIZE -#define CONFIG_COM_RXBUFSIZE 64 -#endif - -#ifndef CONFIG_COM_TXBUFSIZE -#define CONFIG_COM_TXBUFSIZE 64 -#endif - -struct up_dev_s -{ - unsigned int base; /* Base address of COM registers */ - unsigned int baud; /* Configured baud */ - int irq; /* IRQ associated with this COM */ - struct irq_action action; - union { - uint8_t val; - struct { - unsigned bits : 2; /* 3=8 bits, 2=7 bits, 1=6 bits, 0=5 bits */ - unsigned stopbits : 1; /* 0=1 stop bit, 1=2 stop bits */ - unsigned parity : 3; /* xx0=none, 001=odd, 011=even */ - unsigned ebreak : 1; - unsigned dlab : 1; - } sep; - } lcr; - char rxbuff[CONFIG_COM_RXBUFSIZE]; /* receive buffer */ - char txbuff[CONFIG_COM_TXBUFSIZE]; /* transmit buffer */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int up_setup(struct uart_dev_s *dev); -static void up_shutdown(struct uart_dev_s *dev); -static int up_attach(struct uart_dev_s *dev); -static void up_detach(struct uart_dev_s *dev); -static irqreturn_t up_com_int_handler(int irq, void *dev_id); -static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, unsigned int *status); -static void up_rxint(struct uart_dev_s *dev, bool enable); -static bool up_rxavailable(struct uart_dev_s *dev); -static void up_send(struct uart_dev_s *dev, int ch); -static void up_txint(struct uart_dev_s *dev, bool enable); -static bool up_txready(struct uart_dev_s *dev); -static bool up_txempty(struct uart_dev_s *dev); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct uart_ops_s g_com_ops = -{ - .setup = up_setup, - .shutdown = up_shutdown, - .attach = up_attach, - .detach = up_detach, - .ioctl = up_ioctl, - .receive = up_receive, - .rxint = up_rxint, - .rxavailable = up_rxavailable, -#ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = NULL, -#endif - .send = up_send, - .txint = up_txint, - .txready = up_txready, - .txempty = up_txempty, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_alloc_com - ****************************************************************************/ - -static uart_dev_t *up_alloc_com(unsigned int base, int irq) -{ - uart_dev_t *dev; - struct up_dev_s *priv; - - priv = kmm_zalloc(sizeof(struct up_dev_s)); - if (priv == NULL) - { - goto err0; - } - - dev = kmm_zalloc(sizeof(uart_dev_t)); - if (dev == NULL) - { - goto err1; - } - - priv->base = base; - priv->irq = irq; - priv->baud = 115200; - priv->lcr.val = 0; - priv->lcr.sep.parity = 0; - priv->lcr.sep.bits = 3; - priv->lcr.sep.stopbits = 0; - priv->action.handler = up_com_int_handler; - priv->action.dev_id = dev; - - dev->recv.size = CONFIG_COM_RXBUFSIZE; - dev->recv.buffer = priv->rxbuff; - dev->xmit.size = CONFIG_COM_TXBUFSIZE; - dev->xmit.buffer = priv->txbuff; - dev->ops = &g_com_ops; - dev->priv = priv; - - return dev; - -err1: - kmm_free(priv); -err0: - return NULL; -} - -/**************************************************************************** - * Name: up_alloc_com - ****************************************************************************/ - -static inline void up_free_com(uart_dev_t *com) -{ - kmm_free(com->priv); - kmm_free(com); -} - -/**************************************************************************** - * Name: up_setup - * - * Description: - * Configure the UART baud, bits, parity, fifos, etc. This - * method is called the first time that the serial port is - * opened. - * - ****************************************************************************/ - -static int up_setup(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = dev->priv; - uint16_t base = priv->base; - union { - uint16_t val; - struct { - uint8_t low; - uint8_t high; - } sep; - } data; - - // clear and disable FIFO - - outb(base+COM_FCR, 1); - outb(base+COM_FCR, 3); - outb(base+COM_FCR, 0); - - // Clear any preexisting overrun indications and interrupts - // Serial port doesn't exist if COM_LSR returns 0xFF - - inb(base+COM_LSR); - inb(base+COM_IIR); - inb(base+COM_RX); - if (inb(base+COM_LSR) == 0xff) - { - _err("ERROR: COM %d does not exist\n", base); - return -1; - } - - // Set speed; requires DLAB latch - - outb(base+COM_LCR, COM_LCR_DLAB); - data.val = 115200 / priv->baud; - outb(base+COM_DLL, data.sep.low); - outb(base+COM_DLM, data.sep.high); - - // set data bits, stop bit, parity; turn off DLAB latch - - outb(base+COM_LCR, priv->lcr.val); - - // OUT2 must be set to enable interrupt - - outb(base+COM_MCR, COM_MCR_OUT2); - - // setup FIFO - - outb(base+COM_FCR, 1); - - // disable COM interrupts - - outb(base+COM_IER, 0); - return OK; -} - -/**************************************************************************** - * Name: up_shutdown - * - * Description: - * Disable the UART. This method is called when the serial port is closed - * - ****************************************************************************/ - -static void up_shutdown(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = dev->priv; - uint16_t base = priv->base; - - // disable COM interrupts - outb(base+COM_IER, 0); -} - -/**************************************************************************** - * Name: up_attach - * - * Description: - * Configure the UART to operation in interrupt driven mode. This method is - * called when the serial port is opened. Normally, this is just after the - * the setup() method is called, however, the serial console may operate in - * a non-interrupt driven mode during the boot phase. - * - * RX and TX interrupts are not enabled when by the attach method (unless the - * hardware supports multiple levels of interrupt enabling). The RX and TX - * interrupts are not enabled until the txint() and rxint() methods are called. - * - ****************************************************************************/ - -static int up_attach(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = dev->priv; - int errcode; - - errcode = rgmp_request_irq(priv->irq, &priv->action, 0); - - return errcode; -} - -/**************************************************************************** - * Name: up_detach - * - * Description: - * Detach UART interrupts. This method is called when the serial port is - * closed normally just before the shutdown method is called. The exception is - * the serial console which is never shutdown. - * - ****************************************************************************/ - -static void up_detach(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = dev->priv; - - rgmp_free_irq(priv->irq, &priv->action); -} - -/**************************************************************************** - * Name: up_com_int_handler - * - * Description: - * This is the UART interrupt handler. It will be invoked - * when an interrupt received on the 'irq' It should call - * uart_transmitchars or uart_receivechar to perform the - * appropriate data transfers. The interrupt handling logic\ - * must be able to map the 'irq' number into the approprite - * uart_dev_s structure in order to call these functions. - * - ****************************************************************************/ - -static irqreturn_t up_com_int_handler(int irq, void *dev_id) -{ - struct uart_dev_s *dev = dev_id; - struct up_dev_s *priv = dev->priv; - uint16_t base = priv->base; - //uint8_t cause = inb(base+COM_IIR); - uint8_t state = inb(base+COM_LSR); - - if (state & COM_LSR_DATA) - uart_recvchars(dev); - - if (state & COM_LSR_ETR) - uart_xmitchars(dev); - - return IRQ_HANDLED; -} - -/**************************************************************************** - * Name: up_ioctl - * - * Description: - * All ioctl calls will be routed through this method - * - ****************************************************************************/ - -static int up_ioctl(struct file *filep, int cmd, unsigned long arg) -{ - struct inode *inode = filep->f_inode; - struct uart_dev_s *dev = inode->i_private; - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - - switch (cmd) { - case COM_SET_BAUD: - priv->baud = arg; - break; - case COM_SET_PARITY: - priv->lcr.sep.parity = arg; - break; - case COM_SET_STOPBITS: - priv->lcr.sep.stopbits = arg; - break; - case COM_SET_BITS: - priv->lcr.sep.bits = arg; - break; - default: - return ERROR; - } - - if (up_setup(dev) != OK) - return ERROR; - - up_rxint(dev, 1); - - return OK; -} - -/**************************************************************************** - * Name: up_receive - * - * Description: - * Called (usually) from the interrupt level to receive one character from - * the UART. Error bits associated with the receipt are provided in the - * the return 'status'. - * - ****************************************************************************/ - -static int up_receive(struct uart_dev_s *dev, unsigned int *status) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - uint16_t base = priv->base; - - return inb(base+COM_RX); -} - -/**************************************************************************** - * Name: up_rxint - * - * Description: - * Call to enable or disable RX interrupts - * - ****************************************************************************/ - -static void up_rxint(struct uart_dev_s *dev, bool enable) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - uint16_t base = priv->base; - uint8_t ier; - - ier = inb(base+COM_IER); - if (enable) - ier |= COM_IER_RDI; - else - ier &= ~COM_IER_RDI; - outb(base+COM_IER, ier); -} - -/**************************************************************************** - * Name: up_rxavailable - * - * Description: - * Return true if the receive fifo is not empty - * - ****************************************************************************/ - -static bool up_rxavailable(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - uint16_t base = priv->base; - - return inb(base+COM_LSR) & COM_LSR_DATA; -} - -/**************************************************************************** - * Name: up_send - * - * Description: - * This method will send one byte on the UART - * - ****************************************************************************/ - -static void up_send(struct uart_dev_s *dev, int ch) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - uint16_t base = priv->base; - - outb(base+COM_TX, ch); -} - -/**************************************************************************** - * Name: up_txint - * - * Description: - * Call to enable or disable TX interrupts - * - ****************************************************************************/ - -static void up_txint(struct uart_dev_s *dev, bool enable) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - uint16_t base = priv->base; - irqstate_t flags; - uint8_t ier; - - flags = enter_critical_section(); - ier = inb(base+COM_IER); - if (enable) { - ier |= COM_IER_TEI; - outb(base+COM_IER, ier); - - /* Fake a TX interrupt here by just calling uart_xmitchars() with - * interrupts disabled (note this may recurse). - */ - - uart_xmitchars(dev); - } - else { - ier &= ~COM_IER_TEI; - outb(base+COM_IER, ier); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: up_txready - * - * Description: - * Return true if the tranmsit fifo is not full - * - ****************************************************************************/ - -static bool up_txready(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - uint16_t base = priv->base; - - return inb(base+COM_LSR) & COM_LSR_ETR; -} - -/**************************************************************************** - * Name: up_txempty - * - * Description: - * Return true if the transmit fifo is empty - * - ****************************************************************************/ - -static bool up_txempty(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s*)dev->priv; - uint16_t base = priv->base; - - return inb(base+COM_LSR) & COM_LSR_EDR; -} - -/**************************************************************************** - * Public Funtions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_serialinit - * - * Description: - * Performs the low level UART initialization early in - * debug so that the serial console will be available - * during bootup. This must be called before up_serialinit. - * - ****************************************************************************/ - -void up_earlyserialinit(void) -{ - -} - -/**************************************************************************** - * Name: up_serialinit - * - * Description: - * Register serial console and serial ports. This assumes - * that up_earlyserialinit was called previously. - * - ****************************************************************************/ - -void up_serialinit(void) -{ - uart_dev_t *dev; - int errcode; - -#ifdef CONFIG_COM1 - dev = up_alloc_com(COM1, 4); - if (dev == NULL) - { - _err("ERROR: alloc com1 fail\n"); - } - else - { - errcode = uart_register("/dev/ttyS0", dev); - if (errcode) - { - _err("ERROR: register com1 fail\n"); - } - } -#endif -#ifdef CONFIG_COM2 - dev = up_alloc_com(COM2, 3); - if (dev == NULL) - { - _err("ERROR: alloc com2 fail\n"); - } - else - { - errcode = uart_register("/dev/ttyS1", dev); - if (errcode) - { - _err("ERROR: register com2 fail\n"); - } - } -#endif -#ifdef CONFIG_COM3 - dev = up_alloc_com(COM3, 4); - if (dev == NULL) - { - _err("ERROR: alloc com3 fail\n"); - } - else - { - errcode = uart_register("/dev/ttyS2", dev); - if (errcode) - { - _err("ERROR: register com3 fail\n"); - } - } -#endif -#ifdef CONFIG_COM4 - dev = up_alloc_com(COM4, 3); - if (dev == NULL) - { - _err("ERROR: alloc com4 fail\n"); - } - else - { - errcode = uart_register("/dev/ttyS3", dev); - if (errcode) - { - _err("ERROR: register com4 fail\n"); - } - } -#endif -} - -/**************************************************************************** - * Name: up_putc - * - * Description: - * Provide priority, low-level access to support OS debug - * writes - * - ****************************************************************************/ -extern void cons_putc(int c); - -int up_putc(int ch) -{ - cons_putc(ch); - return ch; -} - diff --git a/arch/rgmp/src/x86/sigentry.S b/arch/rgmp/src/x86/sigentry.S deleted file mode 100644 index 77214e8114..0000000000 --- a/arch/rgmp/src/x86/sigentry.S +++ /dev/null @@ -1,55 +0,0 @@ -/**************************************************************************** - * arch/rgmp/src/x86/sigentry.S - * - * Copyright (C) 2011 Yu Qiang. All rights reserved. - * Author: Yu Qiang - * - * This file is a part of NuttX: - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - - .globl up_sigentry -up_sigentry: - subl $172, %esp # 172 is the size of Trapframe without cross ring part - pushl %esp - movl %esp, %eax - call up_sigdeliver - addl $8, %esp # skip parameter and tf_curregs - frstor 0(%esp) - addl $108, %esp - popal - popl %es - popl %ds - addl $0x8, %esp # trapno and errcode - iret - - \ No newline at end of file diff --git a/configs/Kconfig b/configs/Kconfig index 21a4becacc..a0eeadad0f 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -761,19 +761,6 @@ config ARCH_BOARD_QEMU_I486 Port of NuttX to QEMU in i486 mode. This port will also run on real i486 hardwared (Google the Bifferboard). -config ARCH_BOARD_RGMP - bool "RGMP" - depends on ARCH_RGMP - ---help--- - RGMP stands for RTOS and GPOS on Multi-Processor. RGMP is a project for - running GPOS and RTOS simultaneously on multi-processor platforms. You can - port your favorite RTOS to RGMP together with an unmodified Linux to form a - hybrid operating system. This makes your application able to use both RTOS - and GPOS features. - - See http://rgmp.sourceforge.net/wiki/index.php/Main_Page for further information - about RGMP. - config ARCH_BOARD_SABRE_6QUAD bool "NXP/Freescale i.MX6 Sabre-6Quad board" depends on ARCH_CHIP_IMX6_6QUAD @@ -1460,7 +1447,6 @@ config ARCH_BOARD default "nucleo-f4x1re" if ARCH_BOARD_NUCLEO_F401RE || ARCH_BOARD_NUCLEO_F411RE default "nucleo-l476rg" if ARCH_BOARD_NUCLEO_L476RG default "qemu-i486" if ARCH_BOARD_QEMU_I486 - default "rgmp" if ARCH_BOARD_RGMP default "sabre-6quad" if ARCH_BOARD_SABRE_6QUAD default "sama5d2-xult" if ARCH_BOARD_SAMA5D2_XULT default "sama5d3x-ek" if ARCH_BOARD_SAMA5D3X_EK @@ -1772,9 +1758,6 @@ endif if ARCH_BOARD_QEMU_I486 source "configs/qemu-i486/Kconfig" endif -if ARCH_BOARD_RGMP -source "configs/rgmp/Kconfig" -endif if ARCH_BOARD_SABRE_6QUAD source "configs/sabre-6quad/Kconfig" endif diff --git a/configs/README.txt b/configs/README.txt index de1342ced2..fa59055c6a 100644 --- a/configs/README.txt +++ b/configs/README.txt @@ -552,16 +552,6 @@ configs/qemu-i486 Port of NuttX to QEMU in i486 mode. This port will also run on real i486 hardwared (Google the Bifferboard). -configs/rgmp - RGMP stands for RTOS and GPOS on Multi-Processor. RGMP is a project for - running GPOS and RTOS simultaneously on multi-processor platforms. You can - port your favorite RTOS to RGMP together with an unmodified Linux to form a - hybrid operating system. This makes your application able to use both RTOS - and GPOS features. - - See http://rgmp.sourceforge.net/wiki/index.php/Main_Page for further - information about RGMP. - configs/nr5m100-nexys4 Port of NuttX to RISC-V platform on IQ-Analog NR5M100 RISC-V FPGA platform. diff --git a/configs/amber/hello/defconfig b/configs/amber/hello/defconfig index cbad0a8ece..7292bfeb9d 100644 --- a/configs/amber/hello/defconfig +++ b/configs/amber/hello/defconfig @@ -58,7 +58,6 @@ CONFIG_DEBUG_FULLOPT=y CONFIG_ARCH_AVR=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -413,7 +412,6 @@ CONFIG_EXAMPLES_HELLO=y # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERLOOP is not set diff --git a/configs/arduino-due/nsh/defconfig b/configs/arduino-due/nsh/defconfig index 4aa125358a..268589a9ae 100644 --- a/configs/arduino-due/nsh/defconfig +++ b/configs/arduino-due/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -736,7 +735,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/arduino-mega2560/hello/defconfig b/configs/arduino-mega2560/hello/defconfig index 67cb895808..8907161516 100644 --- a/configs/arduino-mega2560/hello/defconfig +++ b/configs/arduino-mega2560/hello/defconfig @@ -62,7 +62,6 @@ CONFIG_DEBUG_FULLOPT=y CONFIG_ARCH_AVR=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -510,7 +509,6 @@ CONFIG_EXAMPLES_HELLO=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/arduino-mega2560/nsh/defconfig b/configs/arduino-mega2560/nsh/defconfig index 81605c97eb..6636c1d8ff 100644 --- a/configs/arduino-mega2560/nsh/defconfig +++ b/configs/arduino-mega2560/nsh/defconfig @@ -63,7 +63,6 @@ CONFIG_DEBUG_FULLOPT=y CONFIG_ARCH_AVR=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -519,7 +518,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/avr32dev1/nsh/defconfig b/configs/avr32dev1/nsh/defconfig index d0ff348be0..cbd3aa7c1a 100644 --- a/configs/avr32dev1/nsh/defconfig +++ b/configs/avr32dev1/nsh/defconfig @@ -58,7 +58,6 @@ CONFIG_DEBUG_FULLOPT=y CONFIG_ARCH_AVR=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -463,7 +462,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERLOOP is not set diff --git a/configs/avr32dev1/ostest/defconfig b/configs/avr32dev1/ostest/defconfig index dd8088c35a..ea66ee4723 100644 --- a/configs/avr32dev1/ostest/defconfig +++ b/configs/avr32dev1/ostest/defconfig @@ -58,7 +58,6 @@ CONFIG_DEBUG_FULLOPT=y CONFIG_ARCH_AVR=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -456,7 +455,6 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERLOOP is not set diff --git a/configs/bambino-200e/nsh/defconfig b/configs/bambino-200e/nsh/defconfig index ab5b2edc94..5926930456 100644 --- a/configs/bambino-200e/nsh/defconfig +++ b/configs/bambino-200e/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -799,7 +798,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/c5471evm/httpd/defconfig b/configs/c5471evm/httpd/defconfig index 197f6d6bbb..899863f4ae 100644 --- a/configs/c5471evm/httpd/defconfig +++ b/configs/c5471evm/httpd/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -722,7 +721,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/c5471evm/nettest/defconfig b/configs/c5471evm/nettest/defconfig index 9aaf151900..01c04e1c2d 100644 --- a/configs/c5471evm/nettest/defconfig +++ b/configs/c5471evm/nettest/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -728,7 +727,6 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/c5471evm/nsh/defconfig b/configs/c5471evm/nsh/defconfig index 9fbc29ae44..5bbf9895e7 100644 --- a/configs/c5471evm/nsh/defconfig +++ b/configs/c5471evm/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -736,7 +735,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/cc3200-launchpad/nsh/defconfig b/configs/cc3200-launchpad/nsh/defconfig index 377ac04c42..eba49bcd2c 100644 --- a/configs/cc3200-launchpad/nsh/defconfig +++ b/configs/cc3200-launchpad/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -707,7 +706,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/cloudctrl/nsh/defconfig b/configs/cloudctrl/nsh/defconfig index 63379c76a0..5a0edc77d7 100644 --- a/configs/cloudctrl/nsh/defconfig +++ b/configs/cloudctrl/nsh/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -812,10 +811,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1219,7 +1217,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/compal_e86/nsh_highram/defconfig b/configs/compal_e86/nsh_highram/defconfig index 0eb2bee40d..6d94dcf374 100644 --- a/configs/compal_e86/nsh_highram/defconfig +++ b/configs/compal_e86/nsh_highram/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -629,7 +628,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/compal_e88/nsh_highram/defconfig b/configs/compal_e88/nsh_highram/defconfig index 36fe799d21..dabec9c67a 100644 --- a/configs/compal_e88/nsh_highram/defconfig +++ b/configs/compal_e88/nsh_highram/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -629,7 +628,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/compal_e99/nsh_compalram/defconfig b/configs/compal_e99/nsh_compalram/defconfig index 919de8f67d..43706916ca 100644 --- a/configs/compal_e99/nsh_compalram/defconfig +++ b/configs/compal_e99/nsh_compalram/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -662,7 +661,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/compal_e99/nsh_highram/defconfig b/configs/compal_e99/nsh_highram/defconfig index 0efcb31377..b4fb3decf3 100644 --- a/configs/compal_e99/nsh_highram/defconfig +++ b/configs/compal_e99/nsh_highram/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -824,7 +823,6 @@ CONFIG_EXAMPLES_NXTEXT_PUFONTID=0 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/demo9s12ne64/ostest/defconfig b/configs/demo9s12ne64/ostest/defconfig index 42c0db51c7..b571cf62e8 100644 --- a/configs/demo9s12ne64/ostest/defconfig +++ b/configs/demo9s12ne64/ostest/defconfig @@ -53,7 +53,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set CONFIG_ARCH_HC=y # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -412,7 +411,6 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERLOOP is not set diff --git a/configs/dk-tm4c129x/ipv6/defconfig b/configs/dk-tm4c129x/ipv6/defconfig index 952adc9bee..8174d2adba 100644 --- a/configs/dk-tm4c129x/ipv6/defconfig +++ b/configs/dk-tm4c129x/ipv6/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -566,10 +565,9 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set CONFIG_ARCH_PHY_INTERRUPT=y # CONFIG_PIPES is not set # CONFIG_PM is not set @@ -954,7 +952,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/dk-tm4c129x/nsh/defconfig b/configs/dk-tm4c129x/nsh/defconfig index cad9ba2649..56660ab1f5 100644 --- a/configs/dk-tm4c129x/nsh/defconfig +++ b/configs/dk-tm4c129x/nsh/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -568,10 +567,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set CONFIG_ARCH_PHY_INTERRUPT=y # CONFIG_PIPES is not set # CONFIG_PM is not set @@ -964,7 +962,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/ea3131/nsh/defconfig b/configs/ea3131/nsh/defconfig index 3d086897d1..a1eb0e7d0b 100644 --- a/configs/ea3131/nsh/defconfig +++ b/configs/ea3131/nsh/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -661,7 +660,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/ea3131/pgnsh/defconfig b/configs/ea3131/pgnsh/defconfig index 923ad083f1..6b38e9a914 100644 --- a/configs/ea3131/pgnsh/defconfig +++ b/configs/ea3131/pgnsh/defconfig @@ -67,7 +67,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -737,7 +736,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/ea3131/usbserial/defconfig b/configs/ea3131/usbserial/defconfig index 069331dd50..81886fe97a 100644 --- a/configs/ea3131/usbserial/defconfig +++ b/configs/ea3131/usbserial/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -697,7 +696,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/ea3152/ostest/defconfig b/configs/ea3152/ostest/defconfig index ee7349d7cb..cc289d7602 100644 --- a/configs/ea3152/ostest/defconfig +++ b/configs/ea3152/ostest/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -639,7 +638,6 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/eagle100/httpd/defconfig b/configs/eagle100/httpd/defconfig index 4197c688be..b15438b5a7 100644 --- a/configs/eagle100/httpd/defconfig +++ b/configs/eagle100/httpd/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -522,10 +521,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # CONFIG_PIPES is not set # CONFIG_PM is not set # CONFIG_POWER is not set @@ -856,7 +854,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/eagle100/nettest/defconfig b/configs/eagle100/nettest/defconfig index 82e1dbef79..2dc669e057 100644 --- a/configs/eagle100/nettest/defconfig +++ b/configs/eagle100/nettest/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -514,10 +513,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # CONFIG_PIPES is not set # CONFIG_PM is not set # CONFIG_POWER is not set @@ -861,7 +859,6 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/eagle100/nsh/defconfig b/configs/eagle100/nsh/defconfig index 7ba5c5680a..18875dc628 100644 --- a/configs/eagle100/nsh/defconfig +++ b/configs/eagle100/nsh/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -555,10 +554,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # CONFIG_PIPES is not set # CONFIG_PM is not set # CONFIG_POWER is not set @@ -925,7 +923,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/eagle100/nxflat/defconfig b/configs/eagle100/nxflat/defconfig index 26d9a50f20..6db49bd186 100644 --- a/configs/eagle100/nxflat/defconfig +++ b/configs/eagle100/nxflat/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -711,7 +710,6 @@ CONFIG_EXAMPLES_NXFLAT=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/eagle100/thttpd/defconfig b/configs/eagle100/thttpd/defconfig index d6f0e3c105..842069c5fa 100644 --- a/configs/eagle100/thttpd/defconfig +++ b/configs/eagle100/thttpd/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -507,10 +506,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set CONFIG_PIPES=y CONFIG_DEV_PIPE_MAXSIZE=1024 CONFIG_DEV_PIPE_SIZE=1024 @@ -858,7 +856,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/efm32-g8xx-stk/nsh/defconfig b/configs/efm32-g8xx-stk/nsh/defconfig index 4a0b9d4bec..f0a8e668c2 100644 --- a/configs/efm32-g8xx-stk/nsh/defconfig +++ b/configs/efm32-g8xx-stk/nsh/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -666,7 +665,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/efm32gg-stk3700/nsh/defconfig b/configs/efm32gg-stk3700/nsh/defconfig index 1de3b218cd..3910296ef6 100644 --- a/configs/efm32gg-stk3700/nsh/defconfig +++ b/configs/efm32gg-stk3700/nsh/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -666,7 +665,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/ekk-lm3s9b96/nsh/defconfig b/configs/ekk-lm3s9b96/nsh/defconfig index 51ecd48309..bc00257530 100644 --- a/configs/ekk-lm3s9b96/nsh/defconfig +++ b/configs/ekk-lm3s9b96/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -544,10 +543,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # CONFIG_PIPES is not set # CONFIG_PM is not set # CONFIG_POWER is not set @@ -915,7 +913,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/esp32-core/nsh/defconfig b/configs/esp32-core/nsh/defconfig index 18cdefc0be..5c75b76887 100644 --- a/configs/esp32-core/nsh/defconfig +++ b/configs/esp32-core/nsh/defconfig @@ -63,7 +63,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -613,7 +612,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/esp32-core/smp/defconfig b/configs/esp32-core/smp/defconfig index d9641480ce..9db1561de7 100644 --- a/configs/esp32-core/smp/defconfig +++ b/configs/esp32-core/smp/defconfig @@ -63,7 +63,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -616,7 +615,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/ez80f910200kitg/ostest/defconfig b/configs/ez80f910200kitg/ostest/defconfig index 37192e23e0..fcfe07a33b 100644 --- a/configs/ez80f910200kitg/ostest/defconfig +++ b/configs/ez80f910200kitg/ostest/defconfig @@ -62,7 +62,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -597,7 +596,6 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/ez80f910200zco/dhcpd/defconfig b/configs/ez80f910200zco/dhcpd/defconfig index 8e770fe3e1..5439089c19 100644 --- a/configs/ez80f910200zco/dhcpd/defconfig +++ b/configs/ez80f910200zco/dhcpd/defconfig @@ -63,7 +63,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -394,10 +393,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -749,7 +747,6 @@ CONFIG_EXAMPLES_DHCPD_NETMASK=0xffffff00 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/ez80f910200zco/httpd/defconfig b/configs/ez80f910200zco/httpd/defconfig index be2280a06e..9e38b8322f 100644 --- a/configs/ez80f910200zco/httpd/defconfig +++ b/configs/ez80f910200zco/httpd/defconfig @@ -63,7 +63,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -403,10 +402,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -758,7 +756,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/ez80f910200zco/nettest/defconfig b/configs/ez80f910200zco/nettest/defconfig index 94d96ff873..1123421f92 100644 --- a/configs/ez80f910200zco/nettest/defconfig +++ b/configs/ez80f910200zco/nettest/defconfig @@ -63,7 +63,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -395,10 +394,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -763,7 +761,6 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/ez80f910200zco/nsh/defconfig b/configs/ez80f910200zco/nsh/defconfig index c1f233c2e8..6eacbefa3e 100644 --- a/configs/ez80f910200zco/nsh/defconfig +++ b/configs/ez80f910200zco/nsh/defconfig @@ -63,7 +63,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -405,10 +404,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -784,7 +782,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/ez80f910200zco/poll/defconfig b/configs/ez80f910200zco/poll/defconfig index 8c68f8d21f..e7919f583d 100644 --- a/configs/ez80f910200zco/poll/defconfig +++ b/configs/ez80f910200zco/poll/defconfig @@ -63,7 +63,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -402,10 +401,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -767,7 +765,6 @@ CONFIG_EXAMPLES_POLL_NETMASK=0xffffff00 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/fire-stm32v2/nsh/defconfig b/configs/fire-stm32v2/nsh/defconfig index 9b1ccf2ba9..8bc4620548 100644 --- a/configs/fire-stm32v2/nsh/defconfig +++ b/configs/fire-stm32v2/nsh/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -839,10 +838,9 @@ CONFIG_ENC28J60_HPWORK=y # CONFIG_ENC28J60_HALFDUPPLEX is not set # CONFIG_ENC28J60_DUMPPACKET is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # CONFIG_PIPES is not set # CONFIG_PM is not set # CONFIG_POWER is not set @@ -1266,7 +1264,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/freedom-k64f/netnsh/defconfig b/configs/freedom-k64f/netnsh/defconfig index f45f051dee..94d319b5b7 100644 --- a/configs/freedom-k64f/netnsh/defconfig +++ b/configs/freedom-k64f/netnsh/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -542,10 +541,9 @@ CONFIG_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -951,7 +949,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/freedom-k64f/nsh/defconfig b/configs/freedom-k64f/nsh/defconfig index 660add23d5..f88ffdc70b 100644 --- a/configs/freedom-k64f/nsh/defconfig +++ b/configs/freedom-k64f/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -771,7 +770,6 @@ CONFIG_EXAMPLES_PWM_FREQUENCY=100 CONFIG_EXAMPLES_PWM_DURATION=5 CONFIG_EXAMPLES_PWM_DUTYPCT=50 # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/freedom-kl25z/minnsh/defconfig b/configs/freedom-kl25z/minnsh/defconfig index 89935cad02..1e47ae567a 100644 --- a/configs/freedom-kl25z/minnsh/defconfig +++ b/configs/freedom-kl25z/minnsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -627,7 +626,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/freedom-kl25z/nsh/defconfig b/configs/freedom-kl25z/nsh/defconfig index c313a38f01..8f8060ba2d 100644 --- a/configs/freedom-kl25z/nsh/defconfig +++ b/configs/freedom-kl25z/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -662,7 +661,6 @@ CONFIG_EXAMPLES_PWM_FREQUENCY=100 CONFIG_EXAMPLES_PWM_DURATION=5 CONFIG_EXAMPLES_PWM_DUTYPCT=50 # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/freedom-kl26z/minnsh/defconfig b/configs/freedom-kl26z/minnsh/defconfig index 8852ec343b..480cd09801 100644 --- a/configs/freedom-kl26z/minnsh/defconfig +++ b/configs/freedom-kl26z/minnsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -627,7 +626,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/freedom-kl26z/nsh/defconfig b/configs/freedom-kl26z/nsh/defconfig index 73010ec824..2738c86079 100644 --- a/configs/freedom-kl26z/nsh/defconfig +++ b/configs/freedom-kl26z/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -654,7 +653,6 @@ CONFIG_EXAMPLES_PWM_FREQUENCY=100 CONFIG_EXAMPLES_PWM_DURATION=5 CONFIG_EXAMPLES_PWM_DUTYPCT=50 # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/hymini-stm32v/nsh/defconfig b/configs/hymini-stm32v/nsh/defconfig index 1278418787..8d9205db65 100644 --- a/configs/hymini-stm32v/nsh/defconfig +++ b/configs/hymini-stm32v/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -980,7 +979,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/hymini-stm32v/nsh2/defconfig b/configs/hymini-stm32v/nsh2/defconfig index 5a47ce1424..41cb4a97ff 100644 --- a/configs/hymini-stm32v/nsh2/defconfig +++ b/configs/hymini-stm32v/nsh2/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1252,7 +1251,6 @@ CONFIG_EXAMPLES_NXIMAGE_YSCALE1p0=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/hymini-stm32v/usbmsc/defconfig b/configs/hymini-stm32v/usbmsc/defconfig index a9bf81df95..49808a71fa 100644 --- a/configs/hymini-stm32v/usbmsc/defconfig +++ b/configs/hymini-stm32v/usbmsc/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1033,7 +1032,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/hymini-stm32v/usbnsh/defconfig b/configs/hymini-stm32v/usbnsh/defconfig index 37d610d61e..c5cd07b4e4 100644 --- a/configs/hymini-stm32v/usbnsh/defconfig +++ b/configs/hymini-stm32v/usbnsh/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1010,7 +1009,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/hymini-stm32v/usbserial/defconfig b/configs/hymini-stm32v/usbserial/defconfig index eb86d3a7e5..57d23bcb8c 100644 --- a/configs/hymini-stm32v/usbserial/defconfig +++ b/configs/hymini-stm32v/usbserial/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -996,7 +995,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/kwikstik-k40/ostest/defconfig b/configs/kwikstik-k40/ostest/defconfig index f80657b514..f0d1a49614 100644 --- a/configs/kwikstik-k40/ostest/defconfig +++ b/configs/kwikstik-k40/ostest/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -688,7 +687,6 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/launchxl-tms57004/nsh/defconfig b/configs/launchxl-tms57004/nsh/defconfig index c52311e79a..7bfdd01bd9 100644 --- a/configs/launchxl-tms57004/nsh/defconfig +++ b/configs/launchxl-tms57004/nsh/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -687,7 +686,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/lincoln60/netnsh/defconfig b/configs/lincoln60/netnsh/defconfig index e0d78b0c5a..137e5f3621 100644 --- a/configs/lincoln60/netnsh/defconfig +++ b/configs/lincoln60/netnsh/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -521,10 +520,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -914,7 +912,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/lincoln60/nsh/defconfig b/configs/lincoln60/nsh/defconfig index 524b76aec8..024db858a4 100644 --- a/configs/lincoln60/nsh/defconfig +++ b/configs/lincoln60/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -704,7 +703,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/lincoln60/thttpd-binfs/defconfig b/configs/lincoln60/thttpd-binfs/defconfig index 6c6c6e7cde..8a0a858cd2 100644 --- a/configs/lincoln60/thttpd-binfs/defconfig +++ b/configs/lincoln60/thttpd-binfs/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -498,10 +497,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -877,7 +875,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/lm3s6432-s2e/nsh/defconfig b/configs/lm3s6432-s2e/nsh/defconfig index 59ae704707..23169aeb52 100644 --- a/configs/lm3s6432-s2e/nsh/defconfig +++ b/configs/lm3s6432-s2e/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -521,10 +520,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # CONFIG_PIPES is not set # CONFIG_PM is not set # CONFIG_POWER is not set @@ -894,7 +892,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/lm3s6965-ek/discover/defconfig b/configs/lm3s6965-ek/discover/defconfig index 16a2eda7cf..0d7a0d7c80 100644 --- a/configs/lm3s6965-ek/discover/defconfig +++ b/configs/lm3s6965-ek/discover/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -549,10 +548,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # CONFIG_PIPES is not set # CONFIG_PM is not set # CONFIG_POWER is not set @@ -919,7 +917,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/lm3s6965-ek/nsh/defconfig b/configs/lm3s6965-ek/nsh/defconfig index 16a2eda7cf..0d7a0d7c80 100644 --- a/configs/lm3s6965-ek/nsh/defconfig +++ b/configs/lm3s6965-ek/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -549,10 +548,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # CONFIG_PIPES is not set # CONFIG_PM is not set # CONFIG_POWER is not set @@ -919,7 +917,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/lm3s6965-ek/nx/defconfig b/configs/lm3s6965-ek/nx/defconfig index 93074343d9..031025dc51 100644 --- a/configs/lm3s6965-ek/nx/defconfig +++ b/configs/lm3s6965-ek/nx/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -873,7 +872,6 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/lm3s6965-ek/tcpecho/defconfig b/configs/lm3s6965-ek/tcpecho/defconfig index 7cffb832e4..3a6346553b 100644 --- a/configs/lm3s6965-ek/tcpecho/defconfig +++ b/configs/lm3s6965-ek/tcpecho/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -518,10 +517,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # CONFIG_PIPES is not set # CONFIG_PM is not set # CONFIG_POWER is not set @@ -889,7 +887,6 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/lm3s8962-ek/nsh/defconfig b/configs/lm3s8962-ek/nsh/defconfig index dc3cf532f4..5ddde16265 100644 --- a/configs/lm3s8962-ek/nsh/defconfig +++ b/configs/lm3s8962-ek/nsh/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -559,10 +558,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # CONFIG_PIPES is not set # CONFIG_PM is not set # CONFIG_POWER is not set @@ -929,7 +927,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/lm3s8962-ek/nx/defconfig b/configs/lm3s8962-ek/nx/defconfig index 49d50c94fb..1029b9998d 100644 --- a/configs/lm3s8962-ek/nx/defconfig +++ b/configs/lm3s8962-ek/nx/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -883,7 +882,6 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/lm4f120-launchpad/nsh/defconfig b/configs/lm4f120-launchpad/nsh/defconfig index d94d618250..3f6d35f825 100644 --- a/configs/lm4f120-launchpad/nsh/defconfig +++ b/configs/lm4f120-launchpad/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -727,7 +726,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/lpc4330-xplorer/nsh/defconfig b/configs/lpc4330-xplorer/nsh/defconfig index 43d7da3c85..88cd838838 100644 --- a/configs/lpc4330-xplorer/nsh/defconfig +++ b/configs/lpc4330-xplorer/nsh/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -724,7 +723,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/lpc4337-ws/nsh/defconfig b/configs/lpc4337-ws/nsh/defconfig index e643242d3c..663c53f16d 100644 --- a/configs/lpc4337-ws/nsh/defconfig +++ b/configs/lpc4337-ws/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -789,7 +788,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/lpc4357-evb/nsh/defconfig b/configs/lpc4357-evb/nsh/defconfig index 475a16e1cd..b818e54be2 100644 --- a/configs/lpc4357-evb/nsh/defconfig +++ b/configs/lpc4357-evb/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -716,7 +715,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/lpc4370-link2/nsh/defconfig b/configs/lpc4370-link2/nsh/defconfig index f6a52ca1fe..6d6a2394f3 100644 --- a/configs/lpc4370-link2/nsh/defconfig +++ b/configs/lpc4370-link2/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -785,7 +784,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/lpcxpresso-lpc1115/minnsh/defconfig b/configs/lpcxpresso-lpc1115/minnsh/defconfig index dbae4a0abc..8480de14cb 100644 --- a/configs/lpcxpresso-lpc1115/minnsh/defconfig +++ b/configs/lpcxpresso-lpc1115/minnsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -595,7 +594,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/lpcxpresso-lpc1115/nsh/defconfig b/configs/lpcxpresso-lpc1115/nsh/defconfig index 4853dd1d67..5fbf61f2b8 100644 --- a/configs/lpcxpresso-lpc1115/nsh/defconfig +++ b/configs/lpcxpresso-lpc1115/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -619,7 +618,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/lpcxpresso-lpc1768/dhcpd/defconfig b/configs/lpcxpresso-lpc1768/dhcpd/defconfig index 62bd8b1a9c..7b0c989057 100644 --- a/configs/lpcxpresso-lpc1768/dhcpd/defconfig +++ b/configs/lpcxpresso-lpc1768/dhcpd/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -489,10 +488,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -843,7 +841,6 @@ CONFIG_EXAMPLES_DHCPD_NETMASK=0xffffff00 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/lpcxpresso-lpc1768/nsh/defconfig b/configs/lpcxpresso-lpc1768/nsh/defconfig index ad8650d32d..6cf2f99378 100644 --- a/configs/lpcxpresso-lpc1768/nsh/defconfig +++ b/configs/lpcxpresso-lpc1768/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -561,10 +560,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -950,7 +948,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/lpcxpresso-lpc1768/nx/defconfig b/configs/lpcxpresso-lpc1768/nx/defconfig index 9bef698f03..692a436fec 100644 --- a/configs/lpcxpresso-lpc1768/nx/defconfig +++ b/configs/lpcxpresso-lpc1768/nx/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -851,7 +850,6 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/lpcxpresso-lpc1768/thttpd/defconfig b/configs/lpcxpresso-lpc1768/thttpd/defconfig index 8eb4af45ec..23256edfa7 100644 --- a/configs/lpcxpresso-lpc1768/thttpd/defconfig +++ b/configs/lpcxpresso-lpc1768/thttpd/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -490,10 +489,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -860,7 +858,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/lpcxpresso-lpc1768/usbmsc/defconfig b/configs/lpcxpresso-lpc1768/usbmsc/defconfig index ec43ec9a66..87c84faf2d 100644 --- a/configs/lpcxpresso-lpc1768/usbmsc/defconfig +++ b/configs/lpcxpresso-lpc1768/usbmsc/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -763,7 +762,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/maple/nsh/defconfig b/configs/maple/nsh/defconfig index 68678b4a89..dcf2229582 100644 --- a/configs/maple/nsh/defconfig +++ b/configs/maple/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -965,7 +964,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/maple/nx/defconfig b/configs/maple/nx/defconfig index 069f58bf63..a334252dcb 100644 --- a/configs/maple/nx/defconfig +++ b/configs/maple/nx/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1194,7 +1193,6 @@ CONFIG_EXAMPLES_NXHELLO_DEFAULT_FONT=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/maple/usbnsh/defconfig b/configs/maple/usbnsh/defconfig index 8340e58722..b0b0a2bc4f 100644 --- a/configs/maple/usbnsh/defconfig +++ b/configs/maple/usbnsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -997,7 +996,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/mbed/hidkbd/defconfig b/configs/mbed/hidkbd/defconfig index 0b1188bcbd..5e58e588ae 100644 --- a/configs/mbed/hidkbd/defconfig +++ b/configs/mbed/hidkbd/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -726,7 +725,6 @@ CONFIG_EXAMPLES_HIDKBD_DEVNAME="/dev/kbda" # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/mbed/nsh/defconfig b/configs/mbed/nsh/defconfig index a1237556ce..89b418da90 100644 --- a/configs/mbed/nsh/defconfig +++ b/configs/mbed/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -756,7 +755,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/mcu123-lpc214x/composite/defconfig b/configs/mcu123-lpc214x/composite/defconfig index 2ec8c826cc..dde6e0a087 100644 --- a/configs/mcu123-lpc214x/composite/defconfig +++ b/configs/mcu123-lpc214x/composite/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -751,7 +750,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/mcu123-lpc214x/nsh/defconfig b/configs/mcu123-lpc214x/nsh/defconfig index 029eb95dc7..dbc7a65242 100644 --- a/configs/mcu123-lpc214x/nsh/defconfig +++ b/configs/mcu123-lpc214x/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -679,7 +678,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/mcu123-lpc214x/usbmsc/defconfig b/configs/mcu123-lpc214x/usbmsc/defconfig index 83450481f8..bc85948ea1 100644 --- a/configs/mcu123-lpc214x/usbmsc/defconfig +++ b/configs/mcu123-lpc214x/usbmsc/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -716,7 +715,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/mcu123-lpc214x/usbserial/defconfig b/configs/mcu123-lpc214x/usbserial/defconfig index 09fd06afce..9d0ad75115 100644 --- a/configs/mcu123-lpc214x/usbserial/defconfig +++ b/configs/mcu123-lpc214x/usbserial/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -683,7 +682,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/micropendous3/hello/defconfig b/configs/micropendous3/hello/defconfig index 4b37ae8ecf..46d64c660c 100644 --- a/configs/micropendous3/hello/defconfig +++ b/configs/micropendous3/hello/defconfig @@ -58,7 +58,6 @@ CONFIG_DEBUG_FULLOPT=y CONFIG_ARCH_AVR=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -421,7 +420,6 @@ CONFIG_EXAMPLES_HELLO=y # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERLOOP is not set diff --git a/configs/mikroe-stm32f4/fulldemo/defconfig b/configs/mikroe-stm32f4/fulldemo/defconfig index d9e2a358b3..ec9b61f877 100644 --- a/configs/mikroe-stm32f4/fulldemo/defconfig +++ b/configs/mikroe-stm32f4/fulldemo/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1377,7 +1376,6 @@ CONFIG_EXAMPLES_NX_NOTIFYSIGNO=4 # CONFIG_EXAMPLES_RANDOM is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/mikroe-stm32f4/kostest/defconfig b/configs/mikroe-stm32f4/kostest/defconfig index 639bfafc1a..a184e142c5 100644 --- a/configs/mikroe-stm32f4/kostest/defconfig +++ b/configs/mikroe-stm32f4/kostest/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1152,7 +1151,6 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y # CONFIG_EXAMPLES_RANDOM is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/mikroe-stm32f4/nsh/defconfig b/configs/mikroe-stm32f4/nsh/defconfig index fde82bf7eb..f83ae52238 100644 --- a/configs/mikroe-stm32f4/nsh/defconfig +++ b/configs/mikroe-stm32f4/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1080,7 +1079,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_RANDOM is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/mikroe-stm32f4/nx/defconfig b/configs/mikroe-stm32f4/nx/defconfig index 0fdf1f925d..a2d1c348fc 100644 --- a/configs/mikroe-stm32f4/nx/defconfig +++ b/configs/mikroe-stm32f4/nx/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1062,7 +1061,6 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/mikroe-stm32f4/nxlines/defconfig b/configs/mikroe-stm32f4/nxlines/defconfig index 762e07fd5a..87cc5aedfc 100644 --- a/configs/mikroe-stm32f4/nxlines/defconfig +++ b/configs/mikroe-stm32f4/nxlines/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1047,7 +1046,6 @@ CONFIG_EXAMPLES_NXLINES_BPP=16 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/mikroe-stm32f4/nxtext/defconfig b/configs/mikroe-stm32f4/nxtext/defconfig index b711838e80..a92b7cddc1 100644 --- a/configs/mikroe-stm32f4/nxtext/defconfig +++ b/configs/mikroe-stm32f4/nxtext/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1073,7 +1072,6 @@ CONFIG_EXAMPLES_NXTEXT_DEFAULT_FONT=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/mikroe-stm32f4/usbnsh/defconfig b/configs/mikroe-stm32f4/usbnsh/defconfig index d33f84fee3..d267fdde99 100644 --- a/configs/mikroe-stm32f4/usbnsh/defconfig +++ b/configs/mikroe-stm32f4/usbnsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1128,7 +1127,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_RANDOM is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/mirtoo/nsh/defconfig b/configs/mirtoo/nsh/defconfig index 125afec3bb..8c8743a9ce 100644 --- a/configs/mirtoo/nsh/defconfig +++ b/configs/mirtoo/nsh/defconfig @@ -63,7 +63,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set CONFIG_ARCH_MIPS=y -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -718,7 +717,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/mirtoo/nxffs/defconfig b/configs/mirtoo/nxffs/defconfig index 3ec96c7bca..06a76b0f07 100644 --- a/configs/mirtoo/nxffs/defconfig +++ b/configs/mirtoo/nxffs/defconfig @@ -63,7 +63,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set CONFIG_ARCH_MIPS=y -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -779,7 +778,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/misoc/hello/defconfig b/configs/misoc/hello/defconfig index cb7733b1bc..4bda51d016 100644 --- a/configs/misoc/hello/defconfig +++ b/configs/misoc/hello/defconfig @@ -88,7 +88,6 @@ CONFIG_DEBUG_NOOPT=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set CONFIG_ARCH_MISOC=y -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -377,10 +376,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -786,7 +784,6 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/misoc/nsh/defconfig b/configs/misoc/nsh/defconfig index 71aea364a7..438198545a 100644 --- a/configs/misoc/nsh/defconfig +++ b/configs/misoc/nsh/defconfig @@ -87,7 +87,6 @@ CONFIG_DEBUG_NOOPT=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set CONFIG_ARCH_MISOC=y -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -566,7 +565,6 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/moteino-mega/hello/defconfig b/configs/moteino-mega/hello/defconfig index 089bec4099..973aac4a8d 100644 --- a/configs/moteino-mega/hello/defconfig +++ b/configs/moteino-mega/hello/defconfig @@ -56,7 +56,6 @@ CONFIG_DEBUG_FULLOPT=y CONFIG_ARCH_AVR=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -478,7 +477,6 @@ CONFIG_EXAMPLES_HELLO=y # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/moteino-mega/nsh/defconfig b/configs/moteino-mega/nsh/defconfig index 83a2446ef4..97bf0cf3e0 100644 --- a/configs/moteino-mega/nsh/defconfig +++ b/configs/moteino-mega/nsh/defconfig @@ -56,7 +56,6 @@ CONFIG_DEBUG_FULLOPT=y CONFIG_ARCH_AVR=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -489,7 +488,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/moxa/nsh/defconfig b/configs/moxa/nsh/defconfig index a19e3b2c00..d57afb29b6 100644 --- a/configs/moxa/nsh/defconfig +++ b/configs/moxa/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -418,7 +417,7 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_CS89x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set CONFIG_NET_FTMAC100=y CONFIG_FTMAC100_BASE=0x90900000 @@ -427,7 +426,6 @@ CONFIG_FTMAC100_RX_DESC=64 CONFIG_FTMAC100_TX_DESC=32 CONFIG_FTMAC100_MAC0_ENV_ADDR=0x80000050 CONFIG_FTMAC100_HPWORK=y -# CONFIG_NET_VNET is not set # CONFIG_PIPES is not set # CONFIG_PM is not set # CONFIG_POWER is not set @@ -799,7 +797,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/mx1ads/ostest/defconfig b/configs/mx1ads/ostest/defconfig index a370cb0435..6b9443b925 100644 --- a/configs/mx1ads/ostest/defconfig +++ b/configs/mx1ads/ostest/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -619,7 +618,6 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/ne64badge/ostest/defconfig b/configs/ne64badge/ostest/defconfig index 6d75dbaf0b..94d4e981c3 100644 --- a/configs/ne64badge/ostest/defconfig +++ b/configs/ne64badge/ostest/defconfig @@ -53,7 +53,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set CONFIG_ARCH_HC=y # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -412,7 +411,6 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERLOOP is not set diff --git a/configs/nr5m100-nexys4/nsh/defconfig b/configs/nr5m100-nexys4/nsh/defconfig index bfd3fc4fc2..d282b47ccf 100644 --- a/configs/nr5m100-nexys4/nsh/defconfig +++ b/configs/nr5m100-nexys4/nsh/defconfig @@ -59,7 +59,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set CONFIG_ARCH_RISCV=y # CONFIG_ARCH_SIM is not set @@ -615,7 +614,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/ntosd-dm320/nettest/defconfig b/configs/ntosd-dm320/nettest/defconfig index 9aeb9e39de..27c48a7988 100644 --- a/configs/ntosd-dm320/nettest/defconfig +++ b/configs/ntosd-dm320/nettest/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -407,10 +406,9 @@ CONFIG_DM9X_MODE_AUTO=y # CONFIG_DM9X_MODE_100MFD is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # CONFIG_PIPES is not set # CONFIG_PM is not set # CONFIG_POWER is not set @@ -770,7 +768,6 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/ntosd-dm320/nsh/defconfig b/configs/ntosd-dm320/nsh/defconfig index 2bac5f0e14..f20494e37e 100644 --- a/configs/ntosd-dm320/nsh/defconfig +++ b/configs/ntosd-dm320/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -423,10 +422,9 @@ CONFIG_DM9X_MODE_AUTO=y # CONFIG_DM9X_MODE_100MFD is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # CONFIG_PIPES is not set # CONFIG_PM is not set # CONFIG_POWER is not set @@ -808,7 +806,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/ntosd-dm320/poll/defconfig b/configs/ntosd-dm320/poll/defconfig index 989cc95a86..47cf047ad0 100644 --- a/configs/ntosd-dm320/poll/defconfig +++ b/configs/ntosd-dm320/poll/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -414,10 +413,9 @@ CONFIG_DM9X_MODE_AUTO=y # CONFIG_DM9X_MODE_100MFD is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set CONFIG_PIPES=y CONFIG_DEV_PIPE_MAXSIZE=1024 CONFIG_DEV_PIPE_SIZE=1024 @@ -776,7 +774,6 @@ CONFIG_EXAMPLES_POLL_NETMASK=0xffffff00 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/ntosd-dm320/thttpd/defconfig b/configs/ntosd-dm320/thttpd/defconfig index 19f0d460ed..4961cfbd08 100644 --- a/configs/ntosd-dm320/thttpd/defconfig +++ b/configs/ntosd-dm320/thttpd/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -407,10 +406,9 @@ CONFIG_DM9X_MODE_AUTO=y # CONFIG_DM9X_MODE_100MFD is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set CONFIG_PIPES=y CONFIG_DEV_PIPE_MAXSIZE=1024 CONFIG_DEV_PIPE_SIZE=1024 @@ -776,7 +774,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/ntosd-dm320/udp/defconfig b/configs/ntosd-dm320/udp/defconfig index fece989f14..25043071da 100644 --- a/configs/ntosd-dm320/udp/defconfig +++ b/configs/ntosd-dm320/udp/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -406,10 +405,9 @@ CONFIG_DM9X_MODE_AUTO=y # CONFIG_DM9X_MODE_100MFD is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # CONFIG_PIPES is not set # CONFIG_PM is not set # CONFIG_POWER is not set @@ -753,7 +751,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/ntosd-dm320/webserver/defconfig b/configs/ntosd-dm320/webserver/defconfig index 5306d32dc3..71ec171e9e 100644 --- a/configs/ntosd-dm320/webserver/defconfig +++ b/configs/ntosd-dm320/webserver/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -414,10 +413,9 @@ CONFIG_DM9X_MODE_AUTO=y # CONFIG_DM9X_MODE_100MFD is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # CONFIG_PIPES is not set # CONFIG_PM is not set # CONFIG_POWER is not set @@ -765,7 +763,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/nucleo-144/f746-evalos/defconfig b/configs/nucleo-144/f746-evalos/defconfig index 6af63a32b8..ad4378e5d3 100644 --- a/configs/nucleo-144/f746-evalos/defconfig +++ b/configs/nucleo-144/f746-evalos/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -886,7 +885,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/nucleo-144/f746-nsh/defconfig b/configs/nucleo-144/f746-nsh/defconfig index 5bbd175b72..69bc73ac3d 100644 --- a/configs/nucleo-144/f746-nsh/defconfig +++ b/configs/nucleo-144/f746-nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -865,7 +864,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/nucleo-144/f767-evalos/defconfig b/configs/nucleo-144/f767-evalos/defconfig index 62ae169e46..45dc608217 100644 --- a/configs/nucleo-144/f767-evalos/defconfig +++ b/configs/nucleo-144/f767-evalos/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -890,7 +889,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/nucleo-144/f767-nsh/defconfig b/configs/nucleo-144/f767-nsh/defconfig index f69821ac7a..ee1f1ec661 100644 --- a/configs/nucleo-144/f767-nsh/defconfig +++ b/configs/nucleo-144/f767-nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -869,7 +868,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/nucleo-f303re/adc/defconfig b/configs/nucleo-f303re/adc/defconfig index 0e2f3b1adc..7701cf1093 100644 --- a/configs/nucleo-f303re/adc/defconfig +++ b/configs/nucleo-f303re/adc/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -917,7 +916,6 @@ CONFIG_EXAMPLES_ADC_SWTRIG=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/nucleo-f303re/can/defconfig b/configs/nucleo-f303re/can/defconfig index f6e0027a8a..eaf665382c 100644 --- a/configs/nucleo-f303re/can/defconfig +++ b/configs/nucleo-f303re/can/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -920,7 +919,6 @@ CONFIG_EXAMPLES_CAN_READWRITE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/nucleo-f303re/hello/defconfig b/configs/nucleo-f303re/hello/defconfig index bc432a230b..92ceeb5133 100644 --- a/configs/nucleo-f303re/hello/defconfig +++ b/configs/nucleo-f303re/hello/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -966,7 +965,6 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/nucleo-f303re/nxlines/defconfig b/configs/nucleo-f303re/nxlines/defconfig index ba05ea87b6..5c55292bf1 100644 --- a/configs/nucleo-f303re/nxlines/defconfig +++ b/configs/nucleo-f303re/nxlines/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1078,7 +1077,6 @@ CONFIG_EXAMPLES_NXLINES_EXTERNINIT=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/nucleo-f303re/pwm/defconfig b/configs/nucleo-f303re/pwm/defconfig index 4a202c87cd..554dc26f59 100644 --- a/configs/nucleo-f303re/pwm/defconfig +++ b/configs/nucleo-f303re/pwm/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -930,7 +929,6 @@ CONFIG_EXAMPLES_PWM_DUTYPCT2=50 CONFIG_EXAMPLES_PWM_CHANNEL2=2 # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/nucleo-f303re/serialrx/defconfig b/configs/nucleo-f303re/serialrx/defconfig index 19c06fd3fa..ae3d607a70 100644 --- a/configs/nucleo-f303re/serialrx/defconfig +++ b/configs/nucleo-f303re/serialrx/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -961,7 +960,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set CONFIG_EXAMPLES_SERIALRX=y diff --git a/configs/nucleo-f303re/uavcan/defconfig b/configs/nucleo-f303re/uavcan/defconfig index a55127ce49..8fa6320578 100644 --- a/configs/nucleo-f303re/uavcan/defconfig +++ b/configs/nucleo-f303re/uavcan/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -930,7 +929,6 @@ CONFIG_LIBUAVCAN_INIT_RETRIES=0 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/nucleo-f4x1re/f401-nsh/defconfig b/configs/nucleo-f4x1re/f401-nsh/defconfig index ab3b2df490..ce4f3cf3cc 100644 --- a/configs/nucleo-f4x1re/f401-nsh/defconfig +++ b/configs/nucleo-f4x1re/f401-nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -972,7 +971,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/nucleo-f4x1re/f411-nsh/defconfig b/configs/nucleo-f4x1re/f411-nsh/defconfig index b0a9f0e526..238cb1564c 100644 --- a/configs/nucleo-f4x1re/f411-nsh/defconfig +++ b/configs/nucleo-f4x1re/f411-nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -974,7 +973,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/nucleo-l476rg/nsh/defconfig b/configs/nucleo-l476rg/nsh/defconfig index 0fda36c2ed..3f05b78550 100644 --- a/configs/nucleo-l476rg/nsh/defconfig +++ b/configs/nucleo-l476rg/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -820,7 +819,6 @@ CONFIG_EXAMPLES_MAXSAMPLES=64 CONFIG_EXAMPLES_NSAMPLES=8 # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/nutiny-nuc120/nsh/defconfig b/configs/nutiny-nuc120/nsh/defconfig index c6bfab727d..d946b02f73 100644 --- a/configs/nutiny-nuc120/nsh/defconfig +++ b/configs/nutiny-nuc120/nsh/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -660,7 +659,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-efm32g880f128-stk/nsh/defconfig b/configs/olimex-efm32g880f128-stk/nsh/defconfig index bd9a59637f..1facde8362 100644 --- a/configs/olimex-efm32g880f128-stk/nsh/defconfig +++ b/configs/olimex-efm32g880f128-stk/nsh/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -659,7 +658,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-lpc-h3131/nsh/defconfig b/configs/olimex-lpc-h3131/nsh/defconfig index 273eab0bdf..4037c906c7 100644 --- a/configs/olimex-lpc-h3131/nsh/defconfig +++ b/configs/olimex-lpc-h3131/nsh/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -660,7 +659,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-lpc1766stk/ftpc/defconfig b/configs/olimex-lpc1766stk/ftpc/defconfig index 634f5d31df..306ef5d70e 100644 --- a/configs/olimex-lpc1766stk/ftpc/defconfig +++ b/configs/olimex-lpc1766stk/ftpc/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -527,10 +526,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -927,7 +925,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-lpc1766stk/hidkbd/defconfig b/configs/olimex-lpc1766stk/hidkbd/defconfig index 56f0f47356..438351bf1c 100644 --- a/configs/olimex-lpc1766stk/hidkbd/defconfig +++ b/configs/olimex-lpc1766stk/hidkbd/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -753,7 +752,6 @@ CONFIG_EXAMPLES_HIDKBD_ENCODED=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-lpc1766stk/hidmouse/defconfig b/configs/olimex-lpc1766stk/hidmouse/defconfig index f3a3822ef0..93c3572e91 100644 --- a/configs/olimex-lpc1766stk/hidmouse/defconfig +++ b/configs/olimex-lpc1766stk/hidmouse/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -916,7 +915,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-lpc1766stk/nettest/defconfig b/configs/olimex-lpc1766stk/nettest/defconfig index 819f8f8b13..cf81bb61a9 100644 --- a/configs/olimex-lpc1766stk/nettest/defconfig +++ b/configs/olimex-lpc1766stk/nettest/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -491,10 +490,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -858,7 +856,6 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-lpc1766stk/nsh/defconfig b/configs/olimex-lpc1766stk/nsh/defconfig index 55059b6518..e228e36701 100644 --- a/configs/olimex-lpc1766stk/nsh/defconfig +++ b/configs/olimex-lpc1766stk/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -530,10 +529,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -929,7 +927,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-lpc1766stk/nx/defconfig b/configs/olimex-lpc1766stk/nx/defconfig index 311c014840..e564252a62 100644 --- a/configs/olimex-lpc1766stk/nx/defconfig +++ b/configs/olimex-lpc1766stk/nx/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -862,7 +861,6 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-lpc1766stk/slip-httpd/defconfig b/configs/olimex-lpc1766stk/slip-httpd/defconfig index ef787d52d5..1c7e6b2ede 100644 --- a/configs/olimex-lpc1766stk/slip-httpd/defconfig +++ b/configs/olimex-lpc1766stk/slip-httpd/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -822,7 +821,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/olimex-lpc1766stk/thttpd-binfs/defconfig b/configs/olimex-lpc1766stk/thttpd-binfs/defconfig index ab5d46e64e..d3135f2794 100644 --- a/configs/olimex-lpc1766stk/thttpd-binfs/defconfig +++ b/configs/olimex-lpc1766stk/thttpd-binfs/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -498,10 +497,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -874,7 +872,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig b/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig index d68223b384..d65819e802 100644 --- a/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig +++ b/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -491,10 +490,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -862,7 +860,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/olimex-lpc1766stk/usbmsc/defconfig b/configs/olimex-lpc1766stk/usbmsc/defconfig index 6aaa47e165..e4931c1d56 100644 --- a/configs/olimex-lpc1766stk/usbmsc/defconfig +++ b/configs/olimex-lpc1766stk/usbmsc/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -764,7 +763,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-lpc1766stk/usbserial/defconfig b/configs/olimex-lpc1766stk/usbserial/defconfig index 9aaabe2fcb..39c6048cbb 100644 --- a/configs/olimex-lpc1766stk/usbserial/defconfig +++ b/configs/olimex-lpc1766stk/usbserial/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -734,7 +733,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-lpc1766stk/zmodem/defconfig b/configs/olimex-lpc1766stk/zmodem/defconfig index 52f165b294..4866dca396 100644 --- a/configs/olimex-lpc1766stk/zmodem/defconfig +++ b/configs/olimex-lpc1766stk/zmodem/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -531,10 +530,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -944,7 +942,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-lpc2378/nsh/defconfig b/configs/olimex-lpc2378/nsh/defconfig index b7496343ac..641e6078f0 100644 --- a/configs/olimex-lpc2378/nsh/defconfig +++ b/configs/olimex-lpc2378/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -632,7 +631,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-stm32-e407/discover/defconfig b/configs/olimex-stm32-e407/discover/defconfig index 5e8aa59403..dd23f1554d 100644 --- a/configs/olimex-stm32-e407/discover/defconfig +++ b/configs/olimex-stm32-e407/discover/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -794,10 +793,9 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1194,7 +1192,6 @@ CONFIG_EXAMPLES_DISCOVER_NETMASK=0xffffff00 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-stm32-e407/netnsh/defconfig b/configs/olimex-stm32-e407/netnsh/defconfig index 3bbf977266..6ae452f562 100644 --- a/configs/olimex-stm32-e407/netnsh/defconfig +++ b/configs/olimex-stm32-e407/netnsh/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -796,10 +795,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1193,7 +1191,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-stm32-e407/nsh/defconfig b/configs/olimex-stm32-e407/nsh/defconfig index 8b39910a0b..cc0120fbc7 100644 --- a/configs/olimex-stm32-e407/nsh/defconfig +++ b/configs/olimex-stm32-e407/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -998,7 +997,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-stm32-e407/telnetd/defconfig b/configs/olimex-stm32-e407/telnetd/defconfig index 5b82f366ab..6b17db7614 100644 --- a/configs/olimex-stm32-e407/telnetd/defconfig +++ b/configs/olimex-stm32-e407/telnetd/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -796,10 +795,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1192,7 +1190,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-stm32-e407/usbnsh/defconfig b/configs/olimex-stm32-e407/usbnsh/defconfig index d25ff45f35..8076c1a85a 100644 --- a/configs/olimex-stm32-e407/usbnsh/defconfig +++ b/configs/olimex-stm32-e407/usbnsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1057,7 +1056,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-stm32-e407/webserver/defconfig b/configs/olimex-stm32-e407/webserver/defconfig index 270c5dbb68..45d097fc16 100644 --- a/configs/olimex-stm32-e407/webserver/defconfig +++ b/configs/olimex-stm32-e407/webserver/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -794,10 +793,9 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1190,7 +1188,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-stm32-h405/usbnsh/defconfig b/configs/olimex-stm32-h405/usbnsh/defconfig index dd4cc0fb40..4823f38fd1 100644 --- a/configs/olimex-stm32-h405/usbnsh/defconfig +++ b/configs/olimex-stm32-h405/usbnsh/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1097,7 +1096,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-stm32-h407/nsh/defconfig b/configs/olimex-stm32-h407/nsh/defconfig index fd02c40d66..79915a1a72 100644 --- a/configs/olimex-stm32-h407/nsh/defconfig +++ b/configs/olimex-stm32-h407/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1005,7 +1004,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-stm32-p107/nsh/defconfig b/configs/olimex-stm32-p107/nsh/defconfig index e6cc90b04e..c5bc04f46d 100644 --- a/configs/olimex-stm32-p107/nsh/defconfig +++ b/configs/olimex-stm32-p107/nsh/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -802,10 +801,9 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1188,7 +1186,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-stm32-p207/nsh/defconfig b/configs/olimex-stm32-p207/nsh/defconfig index cc63f3004c..2b65965724 100644 --- a/configs/olimex-stm32-p207/nsh/defconfig +++ b/configs/olimex-stm32-p207/nsh/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -836,10 +835,9 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1249,7 +1247,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-strp711/nettest/defconfig b/configs/olimex-strp711/nettest/defconfig index 2a07f8e2d5..97e3515f2a 100644 --- a/configs/olimex-strp711/nettest/defconfig +++ b/configs/olimex-strp711/nettest/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -455,10 +454,9 @@ CONFIG_ENC28J60_HPWORK=y # CONFIG_ENC28J60_HALFDUPPLEX is not set # CONFIG_ENC28J60_DUMPPACKET is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # CONFIG_PIPES is not set # CONFIG_PM is not set # CONFIG_POWER is not set @@ -818,7 +816,6 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimex-strp711/nsh/defconfig b/configs/olimex-strp711/nsh/defconfig index 6f9794a23e..3e1009fe9b 100644 --- a/configs/olimex-strp711/nsh/defconfig +++ b/configs/olimex-strp711/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -689,7 +688,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimexino-stm32/can/defconfig b/configs/olimexino-stm32/can/defconfig index df3acfc4e9..42806be686 100644 --- a/configs/olimexino-stm32/can/defconfig +++ b/configs/olimexino-stm32/can/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1056,7 +1055,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimexino-stm32/composite/defconfig b/configs/olimexino-stm32/composite/defconfig index 6e75398ee7..be2146f2c9 100644 --- a/configs/olimexino-stm32/composite/defconfig +++ b/configs/olimexino-stm32/composite/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1147,7 +1146,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimexino-stm32/nsh/defconfig b/configs/olimexino-stm32/nsh/defconfig index 43c0283f2d..b9473b4cd9 100644 --- a/configs/olimexino-stm32/nsh/defconfig +++ b/configs/olimexino-stm32/nsh/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1076,7 +1075,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimexino-stm32/smallnsh/defconfig b/configs/olimexino-stm32/smallnsh/defconfig index 6bbd1478c6..496622da18 100644 --- a/configs/olimexino-stm32/smallnsh/defconfig +++ b/configs/olimexino-stm32/smallnsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1020,7 +1019,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/olimexino-stm32/tiny/defconfig b/configs/olimexino-stm32/tiny/defconfig index 9a5dc1b901..fda4a7b493 100644 --- a/configs/olimexino-stm32/tiny/defconfig +++ b/configs/olimexino-stm32/tiny/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1017,7 +1016,6 @@ CONFIG_EXAMPLES_CAN_READWRITE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/open1788/knsh/defconfig b/configs/open1788/knsh/defconfig index 3bb6dfcf45..4878abcb49 100644 --- a/configs/open1788/knsh/defconfig +++ b/configs/open1788/knsh/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -736,7 +735,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/open1788/nsh/defconfig b/configs/open1788/nsh/defconfig index e620dc3767..23c97563a9 100644 --- a/configs/open1788/nsh/defconfig +++ b/configs/open1788/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -739,7 +738,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/open1788/nxlines/defconfig b/configs/open1788/nxlines/defconfig index b44db1d026..7cb4a4b8bb 100644 --- a/configs/open1788/nxlines/defconfig +++ b/configs/open1788/nxlines/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -862,7 +861,6 @@ CONFIG_EXAMPLES_NXLINES_BPP=32 # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/p112/ostest/defconfig b/configs/p112/ostest/defconfig index c1da999fc3..7c5b119941 100644 --- a/configs/p112/ostest/defconfig +++ b/configs/p112/ostest/defconfig @@ -53,7 +53,6 @@ CONFIG_WINDOWS_NATIVE=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -411,7 +410,6 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERLOOP is not set diff --git a/configs/pcblogic-pic32mx/nsh/defconfig b/configs/pcblogic-pic32mx/nsh/defconfig index 2b4c87ba8c..32b0908358 100644 --- a/configs/pcblogic-pic32mx/nsh/defconfig +++ b/configs/pcblogic-pic32mx/nsh/defconfig @@ -63,7 +63,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set CONFIG_ARCH_MIPS=y -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -728,7 +727,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/pcduino-a10/nsh/defconfig b/configs/pcduino-a10/nsh/defconfig index 03bdbbcf0f..f16a34ab90 100644 --- a/configs/pcduino-a10/nsh/defconfig +++ b/configs/pcduino-a10/nsh/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -728,7 +727,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/pic32mx-starterkit/nsh/defconfig b/configs/pic32mx-starterkit/nsh/defconfig index 0bef836bff..70b83ca1b2 100644 --- a/configs/pic32mx-starterkit/nsh/defconfig +++ b/configs/pic32mx-starterkit/nsh/defconfig @@ -63,7 +63,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set CONFIG_ARCH_MIPS=y -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -785,7 +784,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/pic32mx-starterkit/nsh2/defconfig b/configs/pic32mx-starterkit/nsh2/defconfig index 145509449d..6f56164ea3 100644 --- a/configs/pic32mx-starterkit/nsh2/defconfig +++ b/configs/pic32mx-starterkit/nsh2/defconfig @@ -64,7 +64,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_HC is not set CONFIG_ARCH_MIPS=y # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -575,10 +574,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -961,7 +959,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/pic32mx7mmb/nsh/defconfig b/configs/pic32mx7mmb/nsh/defconfig index b535ae2d10..19214abc8a 100644 --- a/configs/pic32mx7mmb/nsh/defconfig +++ b/configs/pic32mx7mmb/nsh/defconfig @@ -64,7 +64,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_HC is not set CONFIG_ARCH_MIPS=y # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -594,10 +593,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1024,7 +1022,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/pic32mz-starterkit/nsh/defconfig b/configs/pic32mz-starterkit/nsh/defconfig index 9bfa572e16..58a9e43b6b 100644 --- a/configs/pic32mz-starterkit/nsh/defconfig +++ b/configs/pic32mz-starterkit/nsh/defconfig @@ -63,7 +63,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set CONFIG_ARCH_MIPS=y -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -712,7 +711,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/pirelli_dpl10/nsh_highram/defconfig b/configs/pirelli_dpl10/nsh_highram/defconfig index 37b1fb1ffd..549b8a3e0f 100644 --- a/configs/pirelli_dpl10/nsh_highram/defconfig +++ b/configs/pirelli_dpl10/nsh_highram/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -630,7 +629,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/qemu-i486/nsh/defconfig b/configs/qemu-i486/nsh/defconfig index 5389669288..36683c23fb 100644 --- a/configs/qemu-i486/nsh/defconfig +++ b/configs/qemu-i486/nsh/defconfig @@ -54,7 +54,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set CONFIG_ARCH_X86=y @@ -457,7 +456,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERLOOP is not set diff --git a/configs/qemu-i486/ostest/defconfig b/configs/qemu-i486/ostest/defconfig index a637ac9164..bddc708e7d 100644 --- a/configs/qemu-i486/ostest/defconfig +++ b/configs/qemu-i486/ostest/defconfig @@ -54,7 +54,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set CONFIG_ARCH_X86=y @@ -439,7 +438,6 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERLOOP is not set diff --git a/configs/rgmp/Kconfig b/configs/rgmp/Kconfig deleted file mode 100644 index ba62632ecb..0000000000 --- a/configs/rgmp/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -if ARCH_BOARD_RGMP - -endif # ARCH_BOARD_RGMP diff --git a/configs/rgmp/README.txt b/configs/rgmp/README.txt deleted file mode 100644 index ac92ef91a4..0000000000 --- a/configs/rgmp/README.txt +++ /dev/null @@ -1,90 +0,0 @@ -RGMP README File -================ - -RGMP stands for RTOS and GPOS on Multi-Processor. RGMP is a project for -running GPOS and RTOS simultaneously on multi-processor platforms. You can -port your favorite RTOS to RGMP together with an unmodified Linux to form a -hybrid operating system. This makes your application able to use both RTOS -and GPOS features. - -See http://rgmp.sourceforge.net/wiki/index.php/Main_Page for further -information about RGMP. - -The updated build instructions can be found at: -http://rgmp.sourceforge.net/wiki/index.php/Documentation - -Ubuntu Build Instructions --------------------------- -Build requirements: - * x86 PC: - Ubuntu 10.04, 10.10 or 11.04 - * OMAP4430 pandaboard: - Ubuntu 11.04 - -Run requirements: - * multi-processor x86 PC: - Ubuntu 10.04, 10.10 or 11.04 - * OMAP4430 pandaboard: - Ubuntu 11.04 - -1. Download RGMP from the following URL: - - http://rgmp.sourceforge.net/wiki/index.php/Download - - You should choose a right verion of RGMP compatible with this NuttX release. - Extract the tar file: - - $ tar -xjvf rgmp-.tar.bz2 - -2. Get Linux kernel header: - - $ sudo apt-get install linux-headers-$(uname -r) - -3. Build and install RGMP: - - $ cd - $ ./configure - $ make - $ sudo make install - $ sudo /usr/rgmp/setup - $ exit - -4. Configure NuttX. For example, for the RGMP x86 NSH configuration, do the - following: - - $ cd - $ cd tools - $ ./configure.sh rgmp/x86/nsh - $ cd .. - -5. Build NuttX. Get the binary image at /kernel.img. - - $ cd - $ make - -6. Run NuttX in RGMP: - - $ cd - $ su - $ rgmp_run - - -Other Linux OS Build Instruction --------------------------------------- -Requirements: - * multi-processor x86 PC - running Linux kernel 2.6.32, 2.6.35 or 2.6.38 - * OMAP4430 pandaboard - running Linux kernel 2.6.38 - -1. Get your running Linux kernel header under /usr/src/linux-headers-$(uname -r) - directory. - -2. Following the Ubuntu steps begin at 3. - -Note: You can configure the RGMP to find Linux kernel header in a different - place and install RGMP to a different place. See information printed - by the following instruction: - - $ cd - $ ./configure -h diff --git a/configs/rgmp/arm/default/Make.defs b/configs/rgmp/arm/default/Make.defs deleted file mode 100644 index ef6dcbbb3d..0000000000 --- a/configs/rgmp/arm/default/Make.defs +++ /dev/null @@ -1,96 +0,0 @@ -############################################################################ -# configs/rgmp/default/Make.defs -# -# Copyright (C) 2011 Yu Qiang. All rights reserved. -# Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Authors: Yu Qiang -# Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk - -RGMPLIBDIR := $(RGMP_INST_DIR)/lib -RGMPINCDIR := $(RGMP_INST_DIR)/include -RGMPLKSCPT := $(RGMP_INST_DIR)/etc/rgmp.ld - -HOSTOS = ${shell uname -o} - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION = -O2 -gstabs -else - ARCHOPTIMIZATION = -O2 -endif - -ARCHCPUFLAGS = -fno-builtin -nostdinc -fno-stack-protector -fno-omit-frame-pointer \ - -marm -march=armv7-a -ARCHPICFLAGS = -fpic -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -ARCHDEFINES = -ARCHINCLUDES = -I. -isystem $(TOPDIR)/include -I$(RGMPINCDIR) \ - -I$(TOPDIR)/configs/rgmp/include -I$(TOPDIR)/arch/rgmp/include/arm -ARCHSCRIPT = - -CROSSDEV = -CC = $(CROSSDEV)gcc -CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld -AR = $(CROSSDEV)ar rcs -NM = $(CROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -CFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ - $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) -pipe -CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) -AFLAGS = $(CFLAGS) -D__ASSEMBLY__ - -ASMEXT = .S -OBJEXT = .o -LIBEXT = .a - -ifeq ($(HOSTOS),Cygwin) - EXEEXT = .exe -else - EXEEXT = -endif - -LDFLAGS += -nostdlib -EXTRA_LIBS = - - -MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) - -HOSTCC = gcc -HOSTINCLUDES = -I. -HOSTCFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ - $(ARCHCPUFLAGS) $(HOSTINCLUDES) $(ARCHDEFINES) -pipe -HOSTLDFLAGS = diff --git a/configs/rgmp/arm/default/defconfig b/configs/rgmp/arm/default/defconfig deleted file mode 100644 index a05a9676fa..0000000000 --- a/configs/rgmp/arm/default/defconfig +++ /dev/null @@ -1,659 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Nuttx/ Configuration -# - -# -# Build Setup -# -# CONFIG_EXPERIMENTAL is not set -# CONFIG_DEFAULT_SMALL is not set -CONFIG_HOST_LINUX=y -# CONFIG_HOST_OSX is not set -# CONFIG_HOST_WINDOWS is not set -# CONFIG_HOST_OTHER is not set - -# -# Build Configuration -# -# CONFIG_APPS_DIR="../apps" -# CONFIG_BUILD_2PASS is not set - -# -# Binary Output Formats -# -# CONFIG_RRLOAD_BINARY is not set -# CONFIG_INTELHEX_BINARY is not set -# CONFIG_MOTOROLA_SREC is not set -# CONFIG_RAW_BINARY is not set - -# -# Customize Header Files -# -CONFIG_ARCH_STDINT_H=y -CONFIG_ARCH_STDBOOL_H=y -CONFIG_ARCH_MATH_H=y -# CONFIG_ARCH_FLOAT_H is not set -# CONFIG_ARCH_STDARG_H is not set - -# -# Debug Options -# -# CONFIG_DEBUG_FEATURES is not set -# CONFIG_ARCH_HAVE_STACKCHECK is not set -# CONFIG_ARCH_HAVE_HEAPCHECK is not set -# CONFIG_DEBUG_SYMBOLS is not set -# CONFIG_ARCH_HAVE_CUSTOMOPT is not set -# CONFIG_DEBUG_NOOPT is not set -CONFIG_DEBUG_FULLOPT=y - -# -# System Type -# -# CONFIG_ARCH_ARM is not set -# CONFIG_ARCH_AVR is not set -# CONFIG_ARCH_HC is not set -# CONFIG_ARCH_MIPS is not set -CONFIG_ARCH_RGMP=y -# CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_SIM is not set -# CONFIG_ARCH_X86 is not set -# CONFIG_ARCH_Z16 is not set -# CONFIG_ARCH_Z80 is not set -CONFIG_ARCH="rgmp" - -# -# RGMP Configuration Options -# -CONFIG_RGMP_SUBARCH_ARM=y -# CONFIG_RGMP_SUBARCH_X86 is not set -CONFIG_RGMP_SUBARCH="arm" - -# -# Architecture Options -# -# CONFIG_ARCH_NOINTC is not set -# CONFIG_ARCH_VECNOTIRQ is not set -# CONFIG_ARCH_DMA is not set -# CONFIG_ARCH_HAVE_IRQPRIO is not set -# CONFIG_ARCH_ADDRENV is not set -# CONFIG_ARCH_HAVE_VFORK is not set -# CONFIG_ARCH_HAVE_MMU is not set -# CONFIG_ARCH_NAND_HWECC is not set -# CONFIG_ARCH_STACKDUMP is not set -# CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_IDLE_CUSTOM is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set -# CONFIG_ARCH_HAVE_RAMVECTORS is not set - -# -# Board Settings -# -CONFIG_BOARD_LOOPSPERMSEC=5000 -# CONFIG_ARCH_CALIBRATION is not set - -# -# Interrupt options -# -# CONFIG_ARCH_HAVE_INTERRUPTSTACK is not set -# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set - -# -# Boot options -# -# CONFIG_BOOT_RUNFROMEXTSRAM is not set -CONFIG_BOOT_RUNFROMFLASH=y -# CONFIG_BOOT_RUNFROMISRAM is not set -# CONFIG_BOOT_RUNFROMSDRAM is not set -# CONFIG_BOOT_COPYTORAM is not set - -# -# Boot Memory Configuration -# -CONFIG_RAM_START=0x0 -CONFIG_RAM_SIZE=0 -# CONFIG_ARCH_HAVE_SDRAM is not set - -# -# Board Selection -# -CONFIG_ARCH_BOARD_RGMP=y -# CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD="rgmp" - -# -# Common Board Options -# - -# -# Board-Specific Options -# - -# -# RTOS Features -# -# CONFIG_BOARD_INITIALIZE is not set -CONFIG_USEC_PER_TICK=1000 -# CONFIG_SYSTEM_TIME64 is not set -CONFIG_RR_INTERVAL=0 -# CONFIG_SCHED_CPULOAD is not set -# CONFIG_SCHED_INSTRUMENTATION is not set -CONFIG_TASK_NAME_SIZE=31 -# CONFIG_SCHED_HAVE_PARENT is not set -# CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2007 -CONFIG_START_MONTH=2 -CONFIG_START_DAY=27 -CONFIG_DEV_CONSOLE=y -# CONFIG_MUTEX_TYPES is not set -# CONFIG_PRIORITY_INHERITANCE is not set -# CONFIG_FDCLONE_DISABLE is not set -# CONFIG_FDCLONE_STDIO is not set -CONFIG_SDCLONE_DISABLE=y -# CONFIG_SCHED_WAITPID is not set -# CONFIG_SCHED_STARTHOOK is not set -# CONFIG_SCHED_ATEXIT is not set -# CONFIG_SCHED_ONEXIT is not set -CONFIG_USER_ENTRYPOINT="rgmp_main" -CONFIG_DISABLE_OS_API=y -# CONFIG_DISABLE_POSIX_TIMERS is not set -# CONFIG_DISABLE_PTHREAD is not set -# CONFIG_DISABLE_SIGNALS is not set -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_ENVIRON is not set - -# -# Signal Numbers -# -CONFIG_SIG_SIGUSR1=1 -CONFIG_SIG_SIGUSR2=2 -CONFIG_SIG_SIGALARM=3 -CONFIG_SIG_SIGCONDTIMEDOUT=16 - -# -# Sizes of configurable things (0 disables) -# -CONFIG_MAX_TASKS=64 -CONFIG_NPTHREAD_KEYS=4 -CONFIG_NFILE_DESCRIPTORS=32 -CONFIG_NFILE_STREAMS=16 -CONFIG_NAME_MAX=32 -CONFIG_PREALLOC_MQ_MSGS=32 -CONFIG_MQ_MAXMSGSIZE=32 -CONFIG_MAX_WDOGPARMS=4 -CONFIG_PREALLOC_WDOGS=32 -CONFIG_WDOG_INTRESERVE=4 -CONFIG_PREALLOC_TIMERS=8 - -# -# Stack and heap information -# -CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_USERMAIN_STACKSIZE=4096 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=8192 - -# -# Device Drivers -# -CONFIG_DISABLE_POLL=y -CONFIG_DEV_NULL=y -# CONFIG_DEV_ZERO is not set -# CONFIG_DEV_LOOP is not set -# CONFIG_RAMDISK is not set -# CONFIG_CAN is not set -# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set -# CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set -# CONFIG_I2C is not set -# CONFIG_SPI is not set -# CONFIG_I2S is not set -# CONFIG_RTC is not set -# CONFIG_WATCHDOG is not set -# CONFIG_ANALOG is not set -# CONFIG_AUDIO_DEVICES is not set -# CONFIG_VIDEO_DEVICES is not set -# CONFIG_BCH is not set -# CONFIG_INPUT is not set -# CONFIG_LCD is not set -# CONFIG_MMCSD is not set -# CONFIG_MTD is not set -CONFIG_NETDEVICES=y - -# -# General Ethernet MAC Driver Options -# -# CONFIG_NETDEV_MULTINIC is not set - -# -# External Ethernet MAC Device Support -# -# CONFIG_NET_DM90x0 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set -# CONFIG_NET_SLIP is not set -CONFIG_NET_VNET=y -CONFIG_VNET_NINTERFACES=1 -# CONFIG_PIPES is not set -# CONFIG_PM is not set -# CONFIG_POWER is not set -# CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set -CONFIG_SERIAL=y -# CONFIG_DEV_LOWCONSOLE is not set -# CONFIG_16550_UART is not set -# CONFIG_UART_SERIALDRIVER is not set -# CONFIG_UART0_SERIALDRIVER is not set -# CONFIG_UART1_SERIALDRIVER is not set -# CONFIG_UART2_SERIALDRIVER is not set -# CONFIG_UART3_SERIALDRIVER is not set -# CONFIG_UART4_SERIALDRIVER is not set -# CONFIG_UART5_SERIALDRIVER is not set -# CONFIG_UART6_SERIALDRIVER is not set -# CONFIG_UART7_SERIALDRIVER is not set -# CONFIG_UART8_SERIALDRIVER is not set -# CONFIG_SCI0_SERIALDRIVER is not set -# CONFIG_SCI1_SERIALDRIVER is not set -# CONFIG_USART0_SERIALDRIVER is not set -# CONFIG_USART1_SERIALDRIVER is not set -# CONFIG_USART2_SERIALDRIVER is not set -# CONFIG_USART3_SERIALDRIVER is not set -# CONFIG_USART4_SERIALDRIVER is not set -# CONFIG_USART5_SERIALDRIVER is not set -# CONFIG_USART6_SERIALDRIVER is not set -# CONFIG_USART7_SERIALDRIVER is not set -# CONFIG_USART8_SERIALDRIVER is not set - -# -# USART Configuration -# -# CONFIG_MCU_SERIAL is not set -# CONFIG_STANDARD_SERIAL is not set -# CONFIG_SERIAL_IFLOWCONTROL is not set -# CONFIG_SERIAL_OFLOWCONTROL is not set -# CONFIG_USBDEV is not set -# CONFIG_USBHOST is not set -# CONFIG_DRIVERS_WIRELESS is not set - -# -# System Logging Device Options -# - -# -# System Logging -# -# CONFIG_RAMLOG is not set - -# -# Networking Support -# -CONFIG_ARCH_HAVE_NET=y -# CONFIG_ARCH_HAVE_PHY is not set -CONFIG_NET=y -# CONFIG_NET_NOINTS is not set -CONFIG_NET_IPv4=y -# CONFIG_NET_PROMISCUOUS is not set -CONFIG_NSOCKET_DESCRIPTORS=5 -CONFIG_NET_NACTIVESOCKETS=16 -CONFIG_NET_SOCKOPTS=y -# CONFIG_NET_SOLINGER is not set -CONFIG_NET_ETH_MTU=1514 -# CONFIG_NET_TCPURGDATA is not set - -# -# TCP/IP Networking -# -CONFIG_NET_TCP=y -CONFIG_NET_TCP_CONNS=40 -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_TCP_READAHEAD=y -# CONFIG_NET_TCP_WRITE_BUFFERS is not set -CONFIG_NET_TCP_RECVDELAY=0 -# CONFIG_NET_TCPBACKLOG is not set -# CONFIG_NET_TCP_SPLIT is not set -# CONFIG_NET_SENDFILE is not set - -# -# UDP Networking -# -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NET_UDP_CONNS=8 -# CONFIG_NET_BROADCAST is not set -# CONFIG_NET_RXAVAIL is not set -CONFIG_NET_ICMP=y -CONFIG_NET_ICMP_PING=y -# CONFIG_NET_IGMP is not set -CONFIG_NET_STATISTICS=y -CONFIG_NET_ETH_TCP_RECVWNDO=1460 -CONFIG_NET_ARPTAB_SIZE=16 -# CONFIG_NET_ARP_IPIN is not set -CONFIG_NET_IOB=y -CONFIG_IOB_NBUFFERS=24 -CONFIG_IOB_BUFSIZE=196 -CONFIG_IOB_NCHAINS=8 -CONFIG_IOB_THROTTLE=0 - -# -# Routing Table Configuration -# -# CONFIG_NET_ROUTE is not set -CONFIG_NET_ETHERNET=y - -# -# File Systems -# - -# -# File system configuration -# -# CONFIG_DISABLE_MOUNTPOINT is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_FS_READABLE is not set -# CONFIG_FS_WRITABLE is not set -# CONFIG_FS_RAMMAP is not set -# CONFIG_FS_FAT is not set -# CONFIG_NFS is not set -# CONFIG_FS_NXFFS is not set -# CONFIG_FS_ROMFS is not set -# CONFIG_FS_SMARTFS is not set -# CONFIG_FS_PROCFS is not set - -# -# System Logging -# - - -# -# Graphics Support -# -# CONFIG_NX is not set - -# -# Memory Management -# -# CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=1 -# CONFIG_ARCH_HAVE_HEAP2 is not set -# CONFIG_GRAN is not set - -# -# Audio Support -# -# CONFIG_AUDIO is not set - -# -# Binary Formats -# -# CONFIG_BINFMT_DISABLE is not set -# CONFIG_BINFMT_EXEPATH is not set -# CONFIG_NXFLAT is not set -# CONFIG_ELF is not set -# CONFIG_BUILTIN is not set -# CONFIG_PIC is not set -# CONFIG_SYMTAB_ORDEREDBYNAME is not set - -# -# Library Routines -# - -# -# Standard C Library Options -# -CONFIG_STDIO_BUFFER_SIZE=64 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=2 -CONFIG_LIB_HOMEDIR="/" -# CONFIG_NOPRINTF_FIELDWIDTH is not set -# CONFIG_LIBC_FLOATINGPOINT is not set -CONFIG_LIBC_LONG_LONG=y -CONFIG_LIB_RAND_ORDER=1 -# CONFIG_EOL_IS_CR is not set -# CONFIG_EOL_IS_LF is not set -# CONFIG_EOL_IS_BOTH_CRLF is not set -CONFIG_EOL_IS_EITHER_CRLF=y -# CONFIG_LIBC_EXECFUNCS is not set -CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 -# CONFIG_LIBC_STRERROR is not set -# CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_ARCH_LOWPUTC=y -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set -CONFIG_ARCH_OPTIMIZED_FUNCTIONS=y -CONFIG_ARCH_MEMCPY=y -CONFIG_ARCH_MEMCMP=y -CONFIG_ARCH_MEMMOVE=y -CONFIG_ARCH_MEMSET=y -# CONFIG_ARCH_STRCHR is not set -CONFIG_ARCH_STRCMP=y -CONFIG_ARCH_STRCPY=y -CONFIG_ARCH_STRNCPY=y -CONFIG_ARCH_STRLEN=y -CONFIG_ARCH_STRNLEN=y -# CONFIG_ARCH_BZERO is not set - -# -# Non-standard Library Support -# -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_LIB_KBDCODEC is not set -# CONFIG_LIB_SLCDCODEC is not set - -# -# Basic CXX Support -# -# CONFIG_C99_BOOL8 is not set -# CONFIG_HAVE_CXX is not set - -# -# Application Configuration -# - -# -# Built-In Applications -# - -# -# Examples -# -# CONFIG_EXAMPLES_BUTTONS is not set -# CONFIG_EXAMPLES_CAN is not set -# CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_DHCPD is not set -# CONFIG_EXAMPLES_ELF is not set -# CONFIG_EXAMPLES_FTPC is not set -# CONFIG_EXAMPLES_FTPD is not set -# CONFIG_EXAMPLES_HELLO is not set -# CONFIG_EXAMPLES_HELLOXX is not set -# CONFIG_EXAMPLES_JSON is not set -# CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set -# CONFIG_EXAMPLES_IGMP is not set -# CONFIG_EXAMPLES_LCDRW is not set -# CONFIG_EXAMPLES_MM is not set -# CONFIG_EXAMPLES_MODBUS is not set -# CONFIG_EXAMPLES_MOUNT is not set -# CONFIG_EXAMPLES_NETTEST is not set -# CONFIG_EXAMPLES_NRF24L01TERM is not set -# CONFIG_EXAMPLES_NSH is not set -# CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXTERM is not set -# CONFIG_EXAMPLES_NXFFS is not set -# CONFIG_EXAMPLES_NXFLAT is not set -# CONFIG_EXAMPLES_NXHELLO is not set -# CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NXLINES is not set -# CONFIG_EXAMPLES_NXTEXT is not set -# CONFIG_EXAMPLES_OSTEST is not set -# CONFIG_EXAMPLES_PASHELLO is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set -# CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_QENCODER is not set -CONFIG_EXAMPLES_RGMP=y -# CONFIG_EXAMPLES_ROMFS is not set -# CONFIG_EXAMPLES_SENDMAIL is not set -# CONFIG_EXAMPLES_SERLOOP is not set -# CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART is not set -# CONFIG_EXAMPLES_TCPECHO is not set -# CONFIG_EXAMPLES_TELNETD is not set -# CONFIG_EXAMPLES_THTTPD is not set -# CONFIG_EXAMPLES_TIFF is not set -# CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_UDP is not set -# CONFIG_EXAMPLES_DISCOVER is not set -# CONFIG_EXAMPLES_WEBSERVER is not set -# CONFIG_EXAMPLES_USBSERIAL is not set -# CONFIG_EXAMPLES_USBTERM is not set -# CONFIG_EXAMPLES_WATCHDOG is not set -# CONFIG_EXAMPLES_WGET is not set - -# -# Graphics Support -# -# CONFIG_TIFF is not set - -# -# Interpreters -# -# CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_PCODE is not set - -# -# Network Utilities -# - -# -# Networking Utilities -# -# CONFIG_NETUTILS_CODECS is not set -# CONFIG_NETUTILS_DHCPD is not set -# CONFIG_NETUTILS_FTPC is not set -# CONFIG_NETUTILS_FTPD is not set -# CONFIG_NETUTILS_JSON is not set -# CONFIG_NETUTILS_SMTP is not set -# CONFIG_NETUTILS_TELNETD is not set -# CONFIG_NETUTILS_TFTPC is not set -# CONFIG_NETUTILS_THTTPD is not set -# CONFIG_NETUTILS_NETLIB is not set -# CONFIG_NETUTILS_WEBCLIENT is not set -# CONFIG_NETUTILS_WEBSERVER is not set -# CONFIG_NETUTILS_DISCOVER is not set -# CONFIG_NETUTILS_XMLRPC is not set - -# -# FreeModBus -# -# CONFIG_MODBUS is not set - -# -# NSH Library -# -# CONFIG_NSH_LIBRARY is not set - -# -# NxWidgets/NxWM -# - -# -# Platform-specific Support -# -# CONFIG_PLATFORM_CONFIGDATA is not set - -# -# System Libraries and NSH Add-Ons -# - -# -# USB CDC/ACM Device Commands -# - -# -# USB Composite Device Commands -# - -# -# Custom Free Memory Command -# -# CONFIG_SYSTEM_FREE is not set - -# -# I2C tool -# - -# -# INI File Parser -# -# CONFIG_FSUTILS_INIFILE is not set - -# -# FLASH Program Installation -# -# CONFIG_SYSTEM_INSTALL is not set - -# -# FLASH Erase-all Command -# - -# -# NxPlayer media player library / command Line -# -# CONFIG_SYSTEM_NXPLAYER is not set - -# -# RAM test -# -# CONFIG_SYSTEM_RAMTEST is not set - -# -# readline() -# -# CONFIG_SYSTEM_READLINE is not set - -# -# Power Off -# -# CONFIG_SYSTEM_POWEROFF is not set - -# -# RAMTRON -# - -# -# SD Card -# - -# -# Sysinfo -# - -# -# USB Monitor -# - -# -# EMACS-like Command Line Editor -# -# CONFIG_SYSTEM_CLE is not set - -# -# VI Work-Alike Editor -# -# CONFIG_SYSTEM_VI is not set - -# -# Stack Monitor -# - -# -# USB Mass Storage Device Commands -# - -# -# Zmodem Commands -# -# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/rgmp/arm/default/setenv.sh b/configs/rgmp/arm/default/setenv.sh deleted file mode 100755 index bfb02549bd..0000000000 --- a/configs/rgmp/arm/default/setenv.sh +++ /dev/null @@ -1,47 +0,0 @@ -#!/bin/bash -# config/rgmp/default/setenv.sh -# -# Copyright (C) 2011 Yu Qiang. All rights reserved. -# Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Authors: Yu Qiang -# Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if [ "$(basename $0)" = "setenv.sh" ] ; then - echo "You must source this script, not run it!" 1>&2 - exit 1 -fi - -if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi - -#export NUTTX_BIN= -#export PATH=${NUTTX_BIN}:/sbin:/usr/sbin:${PATH_ORIG} - -echo "PATH : ${PATH}" diff --git a/configs/rgmp/arm/nsh/Make.defs b/configs/rgmp/arm/nsh/Make.defs deleted file mode 100644 index 3361618528..0000000000 --- a/configs/rgmp/arm/nsh/Make.defs +++ /dev/null @@ -1,96 +0,0 @@ -############################################################################ -# configs/rgmp/nsh/Make.defs -# -# Copyright (C) 2011 Yu Qiang. All rights reserved. -# Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Authors: Yu Qiang -# Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk - -RGMPLIBDIR := $(RGMP_INST_DIR)/lib -RGMPINCDIR := $(RGMP_INST_DIR)/include -RGMPLKSCPT := $(RGMP_INST_DIR)/etc/rgmp.ld - -HOSTOS = ${shell uname -o} - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION = -O2 -gstabs -else - ARCHOPTIMIZATION = -O2 -endif - -ARCHCPUFLAGS = -fno-builtin -nostdinc -fno-stack-protector -fno-omit-frame-pointer \ - -marm -march=armv7-a -ARCHPICFLAGS = -fpic -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -ARCHDEFINES = -ARCHINCLUDES = -I. -isystem $(TOPDIR)/include -I$(RGMPINCDIR) \ - -I$(TOPDIR)/configs/rgmp/include -I$(TOPDIR)/arch/rgmp/include/arm -ARCHSCRIPT = - -CROSSDEV = -CC = $(CROSSDEV)gcc -CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld -AR = $(CROSSDEV)ar rcs -NM = $(CROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -CFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ - $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) -pipe -CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) -AFLAGS = $(CFLAGS) -D__ASSEMBLY__ - -ASMEXT = .S -OBJEXT = .o -LIBEXT = .a - -ifeq ($(HOSTOS),Cygwin) - EXEEXT = .exe -else - EXEEXT = -endif - -LDFLAGS += -nostdlib -EXTRA_LIBS = - - -MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) - -HOSTCC = gcc -HOSTINCLUDES = -I. -HOSTCFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ - $(ARCHCPUFLAGS) $(HOSTINCLUDES) $(ARCHDEFINES) -pipe -HOSTLDFLAGS = diff --git a/configs/rgmp/arm/nsh/defconfig b/configs/rgmp/arm/nsh/defconfig deleted file mode 100644 index 32b04bda7e..0000000000 --- a/configs/rgmp/arm/nsh/defconfig +++ /dev/null @@ -1,768 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Nuttx/ Configuration -# - -# -# Build Setup -# -# CONFIG_EXPERIMENTAL is not set -# CONFIG_DEFAULT_SMALL is not set -CONFIG_HOST_LINUX=y -# CONFIG_HOST_OSX is not set -# CONFIG_HOST_WINDOWS is not set -# CONFIG_HOST_OTHER is not set - -# -# Build Configuration -# -# CONFIG_APPS_DIR="../apps" -# CONFIG_BUILD_2PASS is not set - -# -# Binary Output Formats -# -# CONFIG_RRLOAD_BINARY is not set -# CONFIG_INTELHEX_BINARY is not set -# CONFIG_MOTOROLA_SREC is not set -# CONFIG_RAW_BINARY is not set - -# -# Customize Header Files -# -CONFIG_ARCH_STDINT_H=y -CONFIG_ARCH_STDBOOL_H=y -CONFIG_ARCH_MATH_H=y -# CONFIG_ARCH_FLOAT_H is not set -# CONFIG_ARCH_STDARG_H is not set - -# -# Debug Options -# -# CONFIG_DEBUG_FEATURES is not set -# CONFIG_ARCH_HAVE_STACKCHECK is not set -# CONFIG_ARCH_HAVE_HEAPCHECK is not set -# CONFIG_DEBUG_INFO is not set - -# -# Subsystem Debug Options -# -# CONFIG_DEBUG_MM is not set -# CONFIG_DEBUG_SCHED is not set -# CONFIG_DEBUG_NET is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_DEBUG_LIB is not set -# CONFIG_DEBUG_BINFMT is not set -# CONFIG_DEBUG_GRAPHICS is not set -# CONFIG_DEBUG_IRQ is not set - -# -# Driver Debug Options -# -# CONFIG_DEBUG_ANALOG is not set -# CONFIG_DEBUG_GPIO is not set -# CONFIG_DEBUG_AUDIO is not set -CONFIG_DEBUG_SYMBOLS=y -# CONFIG_ARCH_HAVE_CUSTOMOPT is not set -CONFIG_DEBUG_NOOPT=y -# CONFIG_DEBUG_FULLOPT is not set - -# -# System Type -# -# CONFIG_ARCH_ARM is not set -# CONFIG_ARCH_AVR is not set -# CONFIG_ARCH_HC is not set -# CONFIG_ARCH_MIPS is not set -CONFIG_ARCH_RGMP=y -# CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_SIM is not set -# CONFIG_ARCH_X86 is not set -# CONFIG_ARCH_Z16 is not set -# CONFIG_ARCH_Z80 is not set -CONFIG_ARCH="rgmp" - -# -# RGMP Configuration Options -# -CONFIG_RGMP_SUBARCH_ARM=y -# CONFIG_RGMP_SUBARCH_X86 is not set -CONFIG_RGMP_SUBARCH="arm" - -# -# Architecture Options -# -# CONFIG_ARCH_NOINTC is not set -# CONFIG_ARCH_VECNOTIRQ is not set -# CONFIG_ARCH_DMA is not set -# CONFIG_ARCH_HAVE_IRQPRIO is not set -# CONFIG_ARCH_ADDRENV is not set -# CONFIG_ARCH_HAVE_VFORK is not set -# CONFIG_ARCH_HAVE_MMU is not set -# CONFIG_ARCH_NAND_HWECC is not set -# CONFIG_ARCH_STACKDUMP is not set -# CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_IDLE_CUSTOM is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set -# CONFIG_ARCH_HAVE_RAMVECTORS is not set - -# -# Board Settings -# -CONFIG_BOARD_LOOPSPERMSEC=5000 -# CONFIG_ARCH_CALIBRATION is not set - -# -# Interrupt options -# -# CONFIG_ARCH_HAVE_INTERRUPTSTACK is not set -# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set - -# -# Boot options -# -# CONFIG_BOOT_RUNFROMEXTSRAM is not set -CONFIG_BOOT_RUNFROMFLASH=y -# CONFIG_BOOT_RUNFROMISRAM is not set -# CONFIG_BOOT_RUNFROMSDRAM is not set -# CONFIG_BOOT_COPYTORAM is not set - -# -# Boot Memory Configuration -# -CONFIG_RAM_START=0x0 -CONFIG_RAM_SIZE=0 -# CONFIG_ARCH_HAVE_SDRAM is not set - -# -# Board Selection -# -CONFIG_ARCH_BOARD_RGMP=y -# CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD="rgmp" - -# -# Common Board Options -# -CONFIG_NSH_MMCSDMINOR=0 - -# -# Board-Specific Options -# - -# -# RTOS Features -# -# CONFIG_BOARD_INITIALIZE is not set -CONFIG_USEC_PER_TICK=1000 -# CONFIG_SYSTEM_TIME64 is not set -CONFIG_RR_INTERVAL=0 -# CONFIG_SCHED_CPULOAD is not set -# CONFIG_SCHED_INSTRUMENTATION is not set -CONFIG_TASK_NAME_SIZE=31 -# CONFIG_SCHED_HAVE_PARENT is not set -# CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2007 -CONFIG_START_MONTH=2 -CONFIG_START_DAY=27 -CONFIG_DEV_CONSOLE=y -# CONFIG_MUTEX_TYPES is not set -# CONFIG_PRIORITY_INHERITANCE is not set -# CONFIG_FDCLONE_DISABLE is not set -# CONFIG_FDCLONE_STDIO is not set -CONFIG_SDCLONE_DISABLE=y -# CONFIG_SCHED_WAITPID is not set -# CONFIG_SCHED_STARTHOOK is not set -# CONFIG_SCHED_ATEXIT is not set -# CONFIG_SCHED_ONEXIT is not set -CONFIG_USER_ENTRYPOINT="nsh_main" -CONFIG_DISABLE_OS_API=y -# CONFIG_DISABLE_POSIX_TIMERS is not set -# CONFIG_DISABLE_PTHREAD is not set -# CONFIG_DISABLE_SIGNALS is not set -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_ENVIRON is not set - -# -# Signal Numbers -# -CONFIG_SIG_SIGUSR1=1 -CONFIG_SIG_SIGUSR2=2 -CONFIG_SIG_SIGALARM=3 -CONFIG_SIG_SIGCONDTIMEDOUT=16 - -# -# Sizes of configurable things (0 disables) -# -CONFIG_MAX_TASKS=64 -CONFIG_NPTHREAD_KEYS=4 -CONFIG_NFILE_DESCRIPTORS=32 -CONFIG_NFILE_STREAMS=16 -CONFIG_NAME_MAX=32 -CONFIG_PREALLOC_MQ_MSGS=32 -CONFIG_MQ_MAXMSGSIZE=32 -CONFIG_MAX_WDOGPARMS=4 -CONFIG_PREALLOC_WDOGS=32 -CONFIG_WDOG_INTRESERVE=4 -CONFIG_PREALLOC_TIMERS=8 - -# -# Stack and heap information -# -CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_USERMAIN_STACKSIZE=4096 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=8192 - -# -# Device Drivers -# -CONFIG_DISABLE_POLL=y -CONFIG_DEV_NULL=y -# CONFIG_DEV_ZERO is not set -# CONFIG_DEV_LOOP is not set -# CONFIG_RAMDISK is not set -# CONFIG_CAN is not set -# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set -# CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set -# CONFIG_I2C is not set -# CONFIG_SPI is not set -# CONFIG_I2S is not set -# CONFIG_RTC is not set -# CONFIG_WATCHDOG is not set -# CONFIG_ANALOG is not set -# CONFIG_AUDIO_DEVICES is not set -# CONFIG_VIDEO_DEVICES is not set -# CONFIG_BCH is not set -# CONFIG_INPUT is not set -# CONFIG_LCD is not set -# CONFIG_MMCSD is not set -# CONFIG_MTD is not set -CONFIG_NETDEVICES=y - -# -# General Ethernet MAC Driver Options -# -# CONFIG_NETDEV_MULTINIC is not set -# CONFIG_NET_DUMPPACKET is not set - -# -# External Ethernet MAC Device Support -# -# CONFIG_NET_DM90x0 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set -# CONFIG_NET_SLIP is not set -CONFIG_NET_VNET=y -CONFIG_VNET_NINTERFACES=1 -# CONFIG_PIPES is not set -# CONFIG_PM is not set -# CONFIG_POWER is not set -# CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set -CONFIG_SERIAL=y -# CONFIG_DEV_LOWCONSOLE is not set -# CONFIG_16550_UART is not set -# CONFIG_UART_SERIALDRIVER is not set -# CONFIG_UART0_SERIALDRIVER is not set -# CONFIG_UART1_SERIALDRIVER is not set -# CONFIG_UART2_SERIALDRIVER is not set -# CONFIG_UART3_SERIALDRIVER is not set -# CONFIG_UART4_SERIALDRIVER is not set -# CONFIG_UART5_SERIALDRIVER is not set -# CONFIG_UART6_SERIALDRIVER is not set -# CONFIG_UART7_SERIALDRIVER is not set -# CONFIG_UART8_SERIALDRIVER is not set -# CONFIG_SCI0_SERIALDRIVER is not set -# CONFIG_SCI1_SERIALDRIVER is not set -# CONFIG_USART0_SERIALDRIVER is not set -# CONFIG_USART1_SERIALDRIVER is not set -# CONFIG_USART2_SERIALDRIVER is not set -# CONFIG_USART3_SERIALDRIVER is not set -# CONFIG_USART4_SERIALDRIVER is not set -# CONFIG_USART5_SERIALDRIVER is not set -# CONFIG_USART6_SERIALDRIVER is not set -# CONFIG_USART7_SERIALDRIVER is not set -# CONFIG_USART8_SERIALDRIVER is not set - -# -# USART Configuration -# -# CONFIG_MCU_SERIAL is not set -# CONFIG_STANDARD_SERIAL is not set -# CONFIG_SERIAL_IFLOWCONTROL is not set -# CONFIG_SERIAL_OFLOWCONTROL is not set -# CONFIG_USBDEV is not set -# CONFIG_USBHOST is not set -# CONFIG_DRIVERS_WIRELESS is not set - -# -# System Logging Device Options -# - -# -# System Logging -# -# CONFIG_RAMLOG is not set - -# -# Networking Support -# -CONFIG_ARCH_HAVE_NET=y -# CONFIG_ARCH_HAVE_PHY is not set -CONFIG_NET=y -# CONFIG_NET_NOINTS is not set -CONFIG_NET_IPv4=y -# CONFIG_NET_PROMISCUOUS is not set -CONFIG_NSOCKET_DESCRIPTORS=5 -CONFIG_NET_NACTIVESOCKETS=16 -CONFIG_NET_SOCKOPTS=y -# CONFIG_NET_SOLINGER is not set -CONFIG_NET_ETH_MTU=1514 -# CONFIG_NET_TCPURGDATA is not set - -# -# TCP/IP Networking -# -CONFIG_NET_TCP=y -CONFIG_NET_TCP_CONNS=40 -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_TCP_READAHEAD=y -# CONFIG_NET_TCP_WRITE_BUFFERS is not set -CONFIG_NET_TCP_RECVDELAY=0 -# CONFIG_NET_TCPBACKLOG is not set -# CONFIG_NET_TCP_SPLIT is not set -# CONFIG_NET_SENDFILE is not set - -# -# UDP Networking -# -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NET_UDP_CONNS=8 -CONFIG_NET_BROADCAST=y -# CONFIG_NET_RXAVAIL is not set -CONFIG_NET_ICMP=y -CONFIG_NET_ICMP_PING=y -# CONFIG_NET_IGMP is not set -CONFIG_NET_STATISTICS=y -CONFIG_NET_ETH_TCP_RECVWNDO=1460 -CONFIG_NET_ARPTAB_SIZE=8 -# CONFIG_NET_ARP_IPIN is not set -CONFIG_NET_IOB=y -CONFIG_IOB_NBUFFERS=24 -CONFIG_IOB_BUFSIZE=196 -CONFIG_IOB_NCHAINS=8 -CONFIG_IOB_THROTTLE=0 - -# -# Routing Table Configuration -# -# CONFIG_NET_ROUTE is not set -CONFIG_NET_ETHERNET=y - -# -# File Systems -# - -# -# File system configuration -# -# CONFIG_DISABLE_MOUNTPOINT is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_FS_READABLE is not set -# CONFIG_FS_WRITABLE is not set -# CONFIG_FS_RAMMAP is not set -# CONFIG_FS_FAT is not set -# CONFIG_NFS is not set -# CONFIG_FS_NXFFS is not set -# CONFIG_FS_ROMFS is not set -# CONFIG_FS_SMARTFS is not set -# CONFIG_FS_PROCFS is not set - -# -# System Logging -# - - -# -# Graphics Support -# -# CONFIG_NX is not set - -# -# Memory Management -# -# CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=1 -# CONFIG_ARCH_HAVE_HEAP2 is not set -# CONFIG_GRAN is not set - -# -# Audio Support -# -# CONFIG_AUDIO is not set - -# -# Binary Formats -# -# CONFIG_BINFMT_DISABLE is not set -# CONFIG_BINFMT_EXEPATH is not set -# CONFIG_NXFLAT is not set -# CONFIG_ELF is not set -# CONFIG_BUILTIN is not set -# CONFIG_PIC is not set -# CONFIG_SYMTAB_ORDEREDBYNAME is not set - -# -# Library Routines -# - -# -# Standard C Library Options -# -CONFIG_STDIO_BUFFER_SIZE=64 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=2 -CONFIG_LIB_HOMEDIR="/" -# CONFIG_NOPRINTF_FIELDWIDTH is not set -# CONFIG_LIBC_FLOATINGPOINT is not set -CONFIG_LIBC_LONG_LONG=y -CONFIG_LIB_RAND_ORDER=1 -# CONFIG_EOL_IS_CR is not set -# CONFIG_EOL_IS_LF is not set -# CONFIG_EOL_IS_BOTH_CRLF is not set -CONFIG_EOL_IS_EITHER_CRLF=y -# CONFIG_LIBC_EXECFUNCS is not set -CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 -# CONFIG_LIBC_STRERROR is not set -# CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_ARCH_LOWPUTC=y -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set -CONFIG_ARCH_OPTIMIZED_FUNCTIONS=y -CONFIG_ARCH_MEMCPY=y -CONFIG_ARCH_MEMCMP=y -CONFIG_ARCH_MEMMOVE=y -CONFIG_ARCH_MEMSET=y -# CONFIG_ARCH_STRCHR is not set -CONFIG_ARCH_STRCMP=y -CONFIG_ARCH_STRCPY=y -CONFIG_ARCH_STRNCPY=y -CONFIG_ARCH_STRLEN=y -CONFIG_ARCH_STRNLEN=y -# CONFIG_ARCH_BZERO is not set - -# -# Non-standard Library Support -# -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_LIB_KBDCODEC is not set -# CONFIG_LIB_SLCDCODEC is not set - -# -# Basic CXX Support -# -# CONFIG_C99_BOOL8 is not set -# CONFIG_HAVE_CXX is not set - -# -# Application Configuration -# - -# -# Built-In Applications -# - -# -# Examples -# -# CONFIG_EXAMPLES_BUTTONS is not set -# CONFIG_EXAMPLES_CAN is not set -# CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_DHCPD is not set -# CONFIG_EXAMPLES_ELF is not set -# CONFIG_EXAMPLES_FTPC is not set -# CONFIG_EXAMPLES_FTPD is not set -# CONFIG_EXAMPLES_HELLO is not set -# CONFIG_EXAMPLES_HELLOXX is not set -# CONFIG_EXAMPLES_JSON is not set -# CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set -# CONFIG_EXAMPLES_IGMP is not set -# CONFIG_EXAMPLES_LCDRW is not set -# CONFIG_EXAMPLES_MM is not set -# CONFIG_EXAMPLES_MODBUS is not set -# CONFIG_EXAMPLES_MOUNT is not set -# CONFIG_EXAMPLES_NETTEST is not set -# CONFIG_EXAMPLES_NRF24L01TERM is not set -CONFIG_EXAMPLES_NSH=y -# CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXTERM is not set -# CONFIG_EXAMPLES_NXFFS is not set -# CONFIG_EXAMPLES_NXFLAT is not set -# CONFIG_EXAMPLES_NXHELLO is not set -# CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NXLINES is not set -# CONFIG_EXAMPLES_NXTEXT is not set -# CONFIG_EXAMPLES_OSTEST is not set -# CONFIG_EXAMPLES_PASHELLO is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set -# CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set -# CONFIG_EXAMPLES_ROMFS is not set -# CONFIG_EXAMPLES_SENDMAIL is not set -# CONFIG_EXAMPLES_SERLOOP is not set -# CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART is not set -# CONFIG_EXAMPLES_TCPECHO is not set -# CONFIG_EXAMPLES_TELNETD is not set -# CONFIG_EXAMPLES_THTTPD is not set -# CONFIG_EXAMPLES_TIFF is not set -# CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_UDP is not set -# CONFIG_EXAMPLES_DISCOVER is not set -# CONFIG_EXAMPLES_WEBSERVER is not set -# CONFIG_EXAMPLES_USBSERIAL is not set -# CONFIG_EXAMPLES_USBTERM is not set -# CONFIG_EXAMPLES_WATCHDOG is not set -# CONFIG_EXAMPLES_WGET is not set - -# -# Graphics Support -# -# CONFIG_TIFF is not set - -# -# Interpreters -# -# CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_PCODE is not set - -# -# Network Utilities -# - -# -# Networking Utilities -# -# CONFIG_NETUTILS_CODECS is not set -CONFIG_NETUTILS_DHCPC=y -# CONFIG_NETUTILS_DHCPD is not set -# CONFIG_NETUTILS_FTPC is not set -# CONFIG_NETUTILS_FTPD is not set -# CONFIG_NETUTILS_JSON is not set -CONFIG_LIBC_NETDB=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSCLIENT_ENTRIES=4 -CONFIG_NETDB_DNSCLIENT_MAXRESPONSE=96 -# CONFIG_NETUTILS_SMTP is not set -# CONFIG_NETUTILS_TELNETD is not set -CONFIG_NETUTILS_TFTPC=y -# CONFIG_NETUTILS_THTTPD is not set -CONFIG_NETUTILS_NETLIB=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NSH_WGET_USERAGENT="NuttX/6.xx.x (; http://www.nuttx.org/)" -# CONFIG_NETUTILS_WEBSERVER is not set -# CONFIG_NETUTILS_DISCOVER is not set -# CONFIG_NETUTILS_XMLRPC is not set - -# -# FreeModBus -# -# CONFIG_MODBUS is not set - -# -# NSH Library -# -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -# CONFIG_NSH_CLE is not set - -# -# Disable Individual commands -# -# CONFIG_NSH_DISABLE_ADDROUTE is not set -# CONFIG_NSH_DISABLE_CAT is not set -# CONFIG_NSH_DISABLE_CD is not set -# CONFIG_NSH_DISABLE_CP is not set -# CONFIG_NSH_DISABLE_CMP is not set -# CONFIG_NSH_DISABLE_DD is not set -# CONFIG_NSH_DISABLE_DF is not set -# CONFIG_NSH_DISABLE_DELROUTE is not set -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HELP is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_KILL is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_MB is not set -# CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_MH is not set -# CONFIG_NSH_DISABLE_MOUNT is not set -# CONFIG_NSH_DISABLE_MW is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PING is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_PWD is not set -# CONFIG_NSH_DISABLE_RM is not set -# CONFIG_NSH_DISABLE_RMDIR is not set -# CONFIG_NSH_DISABLE_SET is not set -# CONFIG_NSH_DISABLE_SH is not set -# CONFIG_NSH_DISABLE_SLEEP is not set -# CONFIG_NSH_DISABLE_TEST is not set -# CONFIG_NSH_DISABLE_UMOUNT is not set -# CONFIG_NSH_DISABLE_UNSET is not set -# CONFIG_NSH_DISABLE_USLEEP is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set - -# -# Configure Command Options -# -CONFIG_NSH_CMDOPT_DF_H=y -CONFIG_NSH_CODECS_BUFSIZE=128 -CONFIG_NSH_CMDOPT_HEXDUMP=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_NSH_LINELEN=40 -# CONFIG_NSH_DISABLE_SEMICOLON is not set -CONFIG_NSH_CMDPARMS=y -CONFIG_NSH_TMPDIR="/tmp" -CONFIG_NSH_MAXARGUMENTS=6 -CONFIG_NSH_ARGCAT=y -CONFIG_NSH_NESTDEPTH=3 -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_ITEF is not set -# CONFIG_NSH_DISABLE_LOOPS is not set -# CONFIG_NSH_DISABLEBG is not set -CONFIG_NSH_CONSOLE=y - -# -# USB Trace Support -# -# CONFIG_NSH_ALTCONDEV is not set -# CONFIG_NSH_ARCHINIT is not set -# CONFIG_NSH_DHCPC is not set -CONFIG_NSH_IPADDR=0xc0a80a02 -CONFIG_NSH_DRIPADDR=0xc0a80a01 -CONFIG_NSH_NETMASK=0xffffff00 -# CONFIG_NSH_DNS is not set -# CONFIG_NSH_NOMAC is not set -CONFIG_NSH_MAX_ROUNDTRIP=20 - -# -# NxWidgets/NxWM -# - -# -# Platform-specific Support -# -# CONFIG_PLATFORM_CONFIGDATA is not set - -# -# System Libraries and NSH Add-Ons -# - -# -# USB CDC/ACM Device Commands -# - -# -# USB Composite Device Commands -# - -# -# Custom Free Memory Command -# -# CONFIG_SYSTEM_FREE is not set - -# -# I2C tool -# - -# -# INI File Parser -# -# CONFIG_FSUTILS_INIFILE is not set - -# -# FLASH Program Installation -# -# CONFIG_SYSTEM_INSTALL is not set - -# -# FLASH Erase-all Command -# - -# -# NxPlayer media player library / command Line -# -# CONFIG_SYSTEM_NXPLAYER is not set - -# -# RAM test -# -# CONFIG_SYSTEM_RAMTEST is not set - -# -# readline() -# -CONFIG_SYSTEM_READLINE=y -CONFIG_READLINE_ECHO=y - -# -# Power Off -# -# CONFIG_SYSTEM_POWEROFF is not set - -# -# RAMTRON -# - -# -# SD Card -# - -# -# Sysinfo -# - -# -# USB Monitor -# - -# -# EMACS-like Command Line Editor -# -# CONFIG_SYSTEM_CLE is not set - -# -# VI Work-Alike Editor -# -# CONFIG_SYSTEM_VI is not set - -# -# Stack Monitor -# - -# -# USB Mass Storage Device Commands -# - -# -# Zmodem Commands -# -# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/rgmp/arm/nsh/setenv.sh b/configs/rgmp/arm/nsh/setenv.sh deleted file mode 100755 index b2180473be..0000000000 --- a/configs/rgmp/arm/nsh/setenv.sh +++ /dev/null @@ -1,47 +0,0 @@ -#!/bin/bash -# config/rgmp/nsh/setenv.sh -# -# Copyright (C) 2011 Yu Qiang. All rights reserved. -# Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Authors: Yu Qiang -# Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if [ "$(basename $0)" = "setenv.sh" ] ; then - echo "You must source this script, not run it!" 1>&2 - exit 1 -fi - -if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi - -#export NUTTX_BIN= -#export PATH=${NUTTX_BIN}:/sbin:/usr/sbin:${PATH_ORIG} - -echo "PATH : ${PATH}" diff --git a/configs/rgmp/include/stdarg.h b/configs/rgmp/include/stdarg.h deleted file mode 100644 index b748243d15..0000000000 --- a/configs/rgmp/include/stdarg.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _CONFIG_RGMP_STDARG_H -#define _CONFIG_RGMP_STDARG_H - - -#include - - -#endif diff --git a/configs/rgmp/x86/cxxtest/Make.defs b/configs/rgmp/x86/cxxtest/Make.defs deleted file mode 100644 index b8ab2328ba..0000000000 --- a/configs/rgmp/x86/cxxtest/Make.defs +++ /dev/null @@ -1,107 +0,0 @@ -#################################################################################### -# configs/rgmp/default/Make.defs -# -# Copyright (C) 2011 Yu Qiang. All rights reserved. -# Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Authors: Yu Qiang -# Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk - -RGMPLIBDIR := $(RGMP_INST_DIR)/lib -RGMPINCDIR := $(RGMP_INST_DIR)/include -RGMPLKSCPT := $(RGMP_INST_DIR)/etc/rgmp.ld - -HOSTOS = ${shell uname -o} - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION = -O2 -gstabs -else - ARCHOPTIMIZATION = -O2 -endif - -#ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti -ARCHCXXFLAGS = -fno-builtin -ARCHCPUFLAGS = -fno-builtin -nostdinc -fno-stack-protector -ARCHPICFLAGS = -fpic -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -ARCHWARNINGSXX = -Wall -Wshadow -Wundef -ARCHDEFINES = -D__RGMP_KERNEL__ -D__RTOS_KERNEL__ -D__SHARE_KERNEL__ -ARCHINCLUDES = -I. -isystem $(TOPDIR)/include -I$(RGMPINCDIR) \ - -I$(TOPDIR)/configs/rgmp/include -I$(TOPDIR)/arch/rgmp/include/x86 - -ARCHXXDEFINES = -ARCHXXINCLUDES = -I$(TOPDIR)/include/cxx -isystem $(TOPDIR)/include -I$(RGMPINCDIR) \ - -I$(TOPDIR)/configs/rgmp/include -I$(TOPDIR)/arch/rgmp/include/x86 \ - -I$(TOPDIR)/include/uClibc++ - -CROSSDEV = -CC = $(CROSSDEV)gcc -CXX = $(CROSSDEV)g++ -CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld -AR = $(CROSSDEV)ar rcs -NM = $(CROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -CFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ - $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) -pipe -CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) -CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) \ - $(ARCHXXDEFINES) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) \ - -pipe -nodefaultlibs -nostdinc++ -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -AFLAGS = $(CFLAGS) -D__ASSEMBLY__ - -ASMEXT = .S -OBJEXT = .o -LIBEXT = .a - -ifeq ($(HOSTOS),Cygwin) - EXEEXT = .exe -else - EXEEXT = -endif - -LDFLAGS += -nostdlib -EXTRA_LIBS = $(shell $(CC) -print-file-name=libsupc++.a) \ - $(shell $(CC) -print-file-name=libgcc_eh.a) - -MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) - -HOSTCC = gcc -HOSTINCLUDES = -I. -HOSTCFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ - $(ARCHCPUFLAGS) $(HOSTINCLUDES) $(ARCHDEFINES) -pipe -HOSTLDFLAGS = diff --git a/configs/rgmp/x86/cxxtest/defconfig b/configs/rgmp/x86/cxxtest/defconfig deleted file mode 100644 index acfbeeedef..0000000000 --- a/configs/rgmp/x86/cxxtest/defconfig +++ /dev/null @@ -1,700 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Nuttx/ Configuration -# - -# -# Build Setup -# -# CONFIG_EXPERIMENTAL is not set -# CONFIG_DEFAULT_SMALL is not set -CONFIG_HOST_LINUX=y -# CONFIG_HOST_OSX is not set -# CONFIG_HOST_WINDOWS is not set -# CONFIG_HOST_OTHER is not set - -# -# Build Configuration -# -# CONFIG_APPS_DIR="../apps" -# CONFIG_BUILD_2PASS is not set - -# -# Binary Output Formats -# -# CONFIG_RRLOAD_BINARY is not set -# CONFIG_INTELHEX_BINARY is not set -# CONFIG_MOTOROLA_SREC is not set -# CONFIG_RAW_BINARY is not set - -# -# Customize Header Files -# -CONFIG_ARCH_STDINT_H=y -CONFIG_ARCH_STDBOOL_H=y -CONFIG_ARCH_MATH_H=y -# CONFIG_ARCH_FLOAT_H is not set -# CONFIG_ARCH_STDARG_H is not set - -# -# Debug Options -# -# CONFIG_DEBUG_FEATURES is not set -# CONFIG_ARCH_HAVE_STACKCHECK is not set -# CONFIG_ARCH_HAVE_HEAPCHECK is not set -CONFIG_DEBUG_INFO=y - -# -# Subsystem Debug Options -# -# CONFIG_DEBUG_MM is not set -# CONFIG_DEBUG_SCHED is not set -# CONFIG_DEBUG_NET is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_DEBUG_LIB is not set -# CONFIG_DEBUG_BINFMT is not set -# CONFIG_DEBUG_GRAPHICS is not set -# CONFIG_DEBUG_IRQ is not set - -# -# Driver Debug Options -# -# CONFIG_DEBUG_ANALOG is not set -# CONFIG_DEBUG_GPIO is not set -# CONFIG_DEBUG_AUDIO is not set -CONFIG_DEBUG_SYMBOLS=y -# CONFIG_ARCH_HAVE_CUSTOMOPT is not set -CONFIG_DEBUG_NOOPT=y -# CONFIG_DEBUG_FULLOPT is not set - -# -# System Type -# -# CONFIG_ARCH_ARM is not set -# CONFIG_ARCH_AVR is not set -# CONFIG_ARCH_HC is not set -# CONFIG_ARCH_MIPS is not set -CONFIG_ARCH_RGMP=y -# CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_SIM is not set -# CONFIG_ARCH_X86 is not set -# CONFIG_ARCH_Z16 is not set -# CONFIG_ARCH_Z80 is not set -CONFIG_ARCH="rgmp" - -# -# RGMP Configuration Options -# -# CONFIG_RGMP_SUBARCH_ARM is not set -CONFIG_RGMP_SUBARCH_X86=y -CONFIG_RGMP_SUBARCH="x86" - -# -# x86 Peripheral Selections -# -CONFIG_COM1=y -CONFIG_COM2=y -# CONFIG_COM3 is not set -# CONFIG_COM4 is not set - -# -# Architecture Options -# -# CONFIG_ARCH_NOINTC is not set -# CONFIG_ARCH_VECNOTIRQ is not set -# CONFIG_ARCH_DMA is not set -# CONFIG_ARCH_HAVE_IRQPRIO is not set -# CONFIG_ARCH_ADDRENV is not set -# CONFIG_ARCH_HAVE_VFORK is not set -# CONFIG_ARCH_HAVE_MMU is not set -# CONFIG_ARCH_NAND_HWECC is not set -# CONFIG_ARCH_STACKDUMP is not set -# CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_IDLE_CUSTOM is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set -# CONFIG_ARCH_HAVE_RAMVECTORS is not set - -# -# Board Settings -# -CONFIG_BOARD_LOOPSPERMSEC=5000 -# CONFIG_ARCH_CALIBRATION is not set - -# -# Interrupt options -# -# CONFIG_ARCH_HAVE_INTERRUPTSTACK is not set -# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set - -# -# Boot options -# -# CONFIG_BOOT_RUNFROMEXTSRAM is not set -CONFIG_BOOT_RUNFROMFLASH=y -# CONFIG_BOOT_RUNFROMISRAM is not set -# CONFIG_BOOT_RUNFROMSDRAM is not set -# CONFIG_BOOT_COPYTORAM is not set - -# -# Boot Memory Configuration -# -CONFIG_RAM_START=0x0 -CONFIG_RAM_SIZE=0 -# CONFIG_ARCH_HAVE_SDRAM is not set - -# -# Board Selection -# -CONFIG_ARCH_BOARD_RGMP=y -# CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD="rgmp" - -# -# Common Board Options -# - -# -# Board-Specific Options -# - -# -# RTOS Features -# -# CONFIG_BOARD_INITIALIZE is not set -CONFIG_USEC_PER_TICK=1000 -# CONFIG_SYSTEM_TIME64 is not set -CONFIG_RR_INTERVAL=0 -# CONFIG_SCHED_CPULOAD is not set -# CONFIG_SCHED_INSTRUMENTATION is not set -CONFIG_TASK_NAME_SIZE=31 -# CONFIG_SCHED_HAVE_PARENT is not set -# CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2007 -CONFIG_START_MONTH=2 -CONFIG_START_DAY=27 -CONFIG_DEV_CONSOLE=y -# CONFIG_MUTEX_TYPES is not set -# CONFIG_PRIORITY_INHERITANCE is not set -# CONFIG_FDCLONE_DISABLE is not set -# CONFIG_FDCLONE_STDIO is not set -CONFIG_SDCLONE_DISABLE=y -# CONFIG_SCHED_WAITPID is not set -# CONFIG_SCHED_STARTHOOK is not set -# CONFIG_SCHED_ATEXIT is not set -# CONFIG_SCHED_ONEXIT is not set -CONFIG_USER_ENTRYPOINT="cxxtest_main" -CONFIG_DISABLE_OS_API=y -# CONFIG_DISABLE_POSIX_TIMERS is not set -# CONFIG_DISABLE_PTHREAD is not set -# CONFIG_DISABLE_SIGNALS is not set -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_ENVIRON is not set - -# -# Signal Numbers -# -CONFIG_SIG_SIGUSR1=1 -CONFIG_SIG_SIGUSR2=2 -CONFIG_SIG_SIGALARM=3 -CONFIG_SIG_SIGCONDTIMEDOUT=16 - -# -# Sizes of configurable things (0 disables) -# -CONFIG_MAX_TASKS=64 -CONFIG_NPTHREAD_KEYS=4 -CONFIG_NFILE_DESCRIPTORS=32 -CONFIG_NFILE_STREAMS=16 -CONFIG_NAME_MAX=32 -CONFIG_PREALLOC_MQ_MSGS=32 -CONFIG_MQ_MAXMSGSIZE=32 -CONFIG_MAX_WDOGPARMS=4 -CONFIG_PREALLOC_WDOGS=32 -CONFIG_WDOG_INTRESERVE=4 -CONFIG_PREALLOC_TIMERS=8 - -# -# Stack and heap information -# -CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_USERMAIN_STACKSIZE=4096 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=8192 - -# -# Device Drivers -# -CONFIG_DISABLE_POLL=y -CONFIG_DEV_NULL=y -# CONFIG_DEV_ZERO is not set -# CONFIG_DEV_LOOP is not set -# CONFIG_RAMDISK is not set -# CONFIG_CAN is not set -# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set -# CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set -# CONFIG_I2C is not set -# CONFIG_SPI is not set -# CONFIG_I2S is not set -# CONFIG_RTC is not set -# CONFIG_WATCHDOG is not set -# CONFIG_ANALOG is not set -# CONFIG_AUDIO_DEVICES is not set -# CONFIG_VIDEO_DEVICES is not set -# CONFIG_BCH is not set -# CONFIG_INPUT is not set -# CONFIG_LCD is not set -# CONFIG_MMCSD is not set -# CONFIG_MTD is not set -CONFIG_NETDEVICES=y - -# -# General Ethernet MAC Driver Options -# -# CONFIG_NETDEV_MULTINIC is not set -# CONFIG_NET_DUMPPACKET is not set - -# -# External Ethernet MAC Device Support -# -# CONFIG_NET_DM90x0 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set -# CONFIG_NET_SLIP is not set -CONFIG_NET_VNET=y -CONFIG_VNET_NINTERFACES=1 -# CONFIG_PIPES is not set -# CONFIG_PM is not set -# CONFIG_POWER is not set -# CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set -CONFIG_SERIAL=y -# CONFIG_DEV_LOWCONSOLE is not set -# CONFIG_16550_UART is not set -# CONFIG_UART_SERIALDRIVER is not set -# CONFIG_UART0_SERIALDRIVER is not set -# CONFIG_UART1_SERIALDRIVER is not set -# CONFIG_UART2_SERIALDRIVER is not set -# CONFIG_UART3_SERIALDRIVER is not set -# CONFIG_UART4_SERIALDRIVER is not set -# CONFIG_UART5_SERIALDRIVER is not set -# CONFIG_UART6_SERIALDRIVER is not set -# CONFIG_UART7_SERIALDRIVER is not set -# CONFIG_UART8_SERIALDRIVER is not set -# CONFIG_SCI0_SERIALDRIVER is not set -# CONFIG_SCI1_SERIALDRIVER is not set -# CONFIG_USART0_SERIALDRIVER is not set -# CONFIG_USART1_SERIALDRIVER is not set -# CONFIG_USART2_SERIALDRIVER is not set -# CONFIG_USART3_SERIALDRIVER is not set -# CONFIG_USART4_SERIALDRIVER is not set -# CONFIG_USART5_SERIALDRIVER is not set -# CONFIG_USART6_SERIALDRIVER is not set -# CONFIG_USART7_SERIALDRIVER is not set -# CONFIG_USART8_SERIALDRIVER is not set - -# -# USART Configuration -# -# CONFIG_MCU_SERIAL is not set -# CONFIG_STANDARD_SERIAL is not set -# CONFIG_SERIAL_IFLOWCONTROL is not set -# CONFIG_SERIAL_OFLOWCONTROL is not set -# CONFIG_USBDEV is not set -# CONFIG_USBHOST is not set -# CONFIG_DRIVERS_WIRELESS is not set - -# -# System Logging Device Options -# - -# -# System Logging -# -# CONFIG_RAMLOG is not set - -# -# Networking Support -# -CONFIG_ARCH_HAVE_NET=y -# CONFIG_ARCH_HAVE_PHY is not set -CONFIG_NET=y -# CONFIG_NET_NOINTS is not set -CONFIG_NET_IPv4=y -# CONFIG_NET_PROMISCUOUS is not set -CONFIG_NSOCKET_DESCRIPTORS=5 -CONFIG_NET_NACTIVESOCKETS=16 -CONFIG_NET_SOCKOPTS=y -# CONFIG_NET_SOLINGER is not set -CONFIG_NET_ETH_MTU=1514 -# CONFIG_NET_TCPURGDATA is not set - -# -# TCP/IP Networking -# -CONFIG_NET_TCP=y -CONFIG_NET_TCP_CONNS=40 -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_TCP_READAHEAD=y -# CONFIG_NET_TCP_WRITE_BUFFERS is not set -CONFIG_NET_TCP_RECVDELAY=0 -# CONFIG_NET_TCPBACKLOG is not set -# CONFIG_NET_TCP_SPLIT is not set -# CONFIG_NET_SENDFILE is not set - -# -# UDP Networking -# -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NET_UDP_CONNS=8 -# CONFIG_NET_BROADCAST is not set -# CONFIG_NET_RXAVAIL is not set -CONFIG_NET_ICMP=y -CONFIG_NET_ICMP_PING=y -# CONFIG_NET_IGMP is not set -CONFIG_NET_STATISTICS=y -CONFIG_NET_ETH_TCP_RECVWNDO=1460 -CONFIG_NET_ARPTAB_SIZE=16 -# CONFIG_NET_ARP_IPIN is not set -CONFIG_NET_IOB=y -CONFIG_IOB_NBUFFERS=24 -CONFIG_IOB_BUFSIZE=196 -CONFIG_IOB_NCHAINS=8 -CONFIG_IOB_THROTTLE=0 - -# -# Routing Table Configuration -# -# CONFIG_NET_ROUTE is not set -CONFIG_NET_ETHERNET=y - -# -# File Systems -# - -# -# File system configuration -# -# CONFIG_DISABLE_MOUNTPOINT is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_FS_READABLE is not set -# CONFIG_FS_WRITABLE is not set -# CONFIG_FS_RAMMAP is not set -# CONFIG_FS_FAT is not set -# CONFIG_NFS is not set -# CONFIG_FS_NXFFS is not set -# CONFIG_FS_ROMFS is not set -# CONFIG_FS_SMARTFS is not set -# CONFIG_FS_PROCFS is not set - -# -# System Logging -# - - -# -# Graphics Support -# -# CONFIG_NX is not set - -# -# Memory Management -# -# CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=1 -# CONFIG_ARCH_HAVE_HEAP2 is not set -# CONFIG_GRAN is not set - -# -# Audio Support -# -# CONFIG_AUDIO is not set - -# -# Binary Formats -# -# CONFIG_BINFMT_DISABLE is not set -# CONFIG_BINFMT_EXEPATH is not set -# CONFIG_NXFLAT is not set -# CONFIG_ELF is not set -# CONFIG_BUILTIN is not set -# CONFIG_PIC is not set -# CONFIG_SYMTAB_ORDEREDBYNAME is not set - -# -# Library Routines -# - -# -# Standard C Library Options -# -CONFIG_STDIO_BUFFER_SIZE=64 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=2 -CONFIG_LIB_HOMEDIR="/" -# CONFIG_NOPRINTF_FIELDWIDTH is not set -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LIBC_LONG_LONG=y -CONFIG_LIB_RAND_ORDER=1 -# CONFIG_EOL_IS_CR is not set -# CONFIG_EOL_IS_LF is not set -# CONFIG_EOL_IS_BOTH_CRLF is not set -CONFIG_EOL_IS_EITHER_CRLF=y -# CONFIG_LIBC_EXECFUNCS is not set -CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 -# CONFIG_LIBC_STRERROR is not set -# CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_ARCH_LOWPUTC=y -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set -CONFIG_ARCH_OPTIMIZED_FUNCTIONS=y -CONFIG_ARCH_MEMCPY=y -CONFIG_ARCH_MEMCMP=y -CONFIG_ARCH_MEMMOVE=y -CONFIG_ARCH_MEMSET=y -CONFIG_ARCH_STRCHR=y -CONFIG_ARCH_STRCMP=y -CONFIG_ARCH_STRCPY=y -CONFIG_ARCH_STRNCPY=y -CONFIG_ARCH_STRLEN=y -CONFIG_ARCH_STRNLEN=y -# CONFIG_ARCH_BZERO is not set - -# -# Non-standard Library Support -# -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_LIB_KBDCODEC is not set -# CONFIG_LIB_SLCDCODEC is not set - -# -# Basic CXX Support -# -# CONFIG_C99_BOOL8 is not set -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -# CONFIG_CXX_NEWLONG is not set - -# -# uClibc++ Standard C++ Library -# -CONFIG_UCLIBCXX=y -CONFIG_UCLIBCXX_EXCEPTION=y -CONFIG_UCLIBCXX_IOSTREAM_BUFSIZE=32 -CONFIG_UCLIBCXX_HAVE_LIBSUPCXX=y - -# -# Application Configuration -# - -# -# Built-In Applications -# - -# -# Examples -# -# CONFIG_EXAMPLES_BUTTONS is not set -# CONFIG_EXAMPLES_CAN is not set -# CONFIG_EXAMPLES_CONFIGDATA is not set -CONFIG_EXAMPLES_CXXTEST=y -CONFIG_EXAMPLES_CXXTEST_CXXINITIALIZE=y -# CONFIG_EXAMPLES_DHCPD is not set -# CONFIG_EXAMPLES_ELF is not set -# CONFIG_EXAMPLES_FTPC is not set -# CONFIG_EXAMPLES_FTPD is not set -# CONFIG_EXAMPLES_HELLO is not set -# CONFIG_EXAMPLES_HELLOXX is not set -# CONFIG_EXAMPLES_JSON is not set -# CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set -# CONFIG_EXAMPLES_IGMP is not set -# CONFIG_EXAMPLES_LCDRW is not set -# CONFIG_EXAMPLES_MM is not set -# CONFIG_EXAMPLES_MODBUS is not set -# CONFIG_EXAMPLES_MOUNT is not set -# CONFIG_EXAMPLES_NETTEST is not set -# CONFIG_EXAMPLES_NRF24L01TERM is not set -# CONFIG_EXAMPLES_NSH is not set -# CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXTERM is not set -# CONFIG_EXAMPLES_NXFFS is not set -# CONFIG_EXAMPLES_NXFLAT is not set -# CONFIG_EXAMPLES_NXHELLO is not set -# CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NXLINES is not set -# CONFIG_EXAMPLES_NXTEXT is not set -# CONFIG_EXAMPLES_OSTEST is not set -# CONFIG_EXAMPLES_PASHELLO is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set -# CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set -# CONFIG_EXAMPLES_ROMFS is not set -# CONFIG_EXAMPLES_SENDMAIL is not set -# CONFIG_EXAMPLES_SERLOOP is not set -# CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART is not set -# CONFIG_EXAMPLES_TCPECHO is not set -# CONFIG_EXAMPLES_TELNETD is not set -# CONFIG_EXAMPLES_THTTPD is not set -# CONFIG_EXAMPLES_TIFF is not set -# CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_UDP is not set -# CONFIG_EXAMPLES_DISCOVER is not set -# CONFIG_EXAMPLES_WEBSERVER is not set -# CONFIG_EXAMPLES_USBSERIAL is not set -# CONFIG_EXAMPLES_USBTERM is not set -# CONFIG_EXAMPLES_WATCHDOG is not set -# CONFIG_EXAMPLES_WGET is not set - -# -# Graphics Support -# -# CONFIG_TIFF is not set - -# -# Interpreters -# -# CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_PCODE is not set - -# -# Network Utilities -# - -# -# Networking Utilities -# -# CONFIG_NETUTILS_CODECS is not set -# CONFIG_NETUTILS_DHCPD is not set -# CONFIG_NETUTILS_FTPC is not set -# CONFIG_NETUTILS_FTPD is not set -# CONFIG_NETUTILS_JSON is not set -# CONFIG_NETUTILS_SMTP is not set -# CONFIG_NETUTILS_TELNETD is not set -# CONFIG_NETUTILS_TFTPC is not set -# CONFIG_NETUTILS_THTTPD is not set -# CONFIG_NETUTILS_NETLIB is not set -# CONFIG_NETUTILS_WEBCLIENT is not set -# CONFIG_NETUTILS_WEBSERVER is not set -# CONFIG_NETUTILS_DISCOVER is not set -# CONFIG_NETUTILS_XMLRPC is not set - -# -# FreeModBus -# -# CONFIG_MODBUS is not set - -# -# NSH Library -# -# CONFIG_NSH_LIBRARY is not set - -# -# NxWidgets/NxWM -# - -# -# Platform-specific Support -# -# CONFIG_PLATFORM_CONFIGDATA is not set - -# -# System Libraries and NSH Add-Ons -# - -# -# USB CDC/ACM Device Commands -# - -# -# USB Composite Device Commands -# - -# -# Custom Free Memory Command -# -# CONFIG_SYSTEM_FREE is not set - -# -# I2C tool -# - -# -# INI File Parser -# -# CONFIG_FSUTILS_INIFILE is not set - -# -# FLASH Program Installation -# -# CONFIG_SYSTEM_INSTALL is not set - -# -# FLASH Erase-all Command -# - -# -# NxPlayer media player library / command Line -# -# CONFIG_SYSTEM_NXPLAYER is not set - -# -# RAM test -# -# CONFIG_SYSTEM_RAMTEST is not set - -# -# readline() -# -# CONFIG_SYSTEM_READLINE is not set - -# -# Power Off -# -# CONFIG_SYSTEM_POWEROFF is not set - -# -# RAMTRON -# - -# -# SD Card -# - -# -# Sysinfo -# - -# -# USB Monitor -# - -# -# EMACS-like Command Line Editor -# -# CONFIG_SYSTEM_CLE is not set - -# -# VI Work-Alike Editor -# -# CONFIG_SYSTEM_VI is not set - -# -# Stack Monitor -# - -# -# USB Mass Storage Device Commands -# - -# -# Zmodem Commands -# -# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/rgmp/x86/cxxtest/setenv.sh b/configs/rgmp/x86/cxxtest/setenv.sh deleted file mode 100755 index a6a533e477..0000000000 --- a/configs/rgmp/x86/cxxtest/setenv.sh +++ /dev/null @@ -1,47 +0,0 @@ -#!/bin/bash -# config/rgmp/default/setenv.sh -# -# Copyright (C) 2011 Yu Qiang. All rights reserved. -# Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Authors: Yu Qiang -# Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if [ "$(basename $0)" = "setenv.sh" ] ; then - echo "You must source this script, not run it!" 1>&2 - exit 1 -fi - -if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi - -#export NUTTX_BIN= -#export PATH=${NUTTX_BIN}:/sbin:/usr/sbin:${PATH_ORIG} - -echo "PATH : ${PATH}" diff --git a/configs/rgmp/x86/default/Make.defs b/configs/rgmp/x86/default/Make.defs deleted file mode 100644 index 2fed4fdcf8..0000000000 --- a/configs/rgmp/x86/default/Make.defs +++ /dev/null @@ -1,95 +0,0 @@ -############################################################################ -# configs/rgmp/default/Make.defs -# -# Copyright (C) 2011 Yu Qiang. All rights reserved. -# Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Authors: Yu Qiang -# Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk - -RGMPLIBDIR := $(RGMP_INST_DIR)/lib -RGMPINCDIR := $(RGMP_INST_DIR)/include -RGMPLKSCPT := $(RGMP_INST_DIR)/etc/rgmp.ld - -HOSTOS = ${shell uname -o} - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION = -O2 -gstabs -else - ARCHOPTIMIZATION = -O2 -endif - -ARCHCPUFLAGS = -fno-builtin -nostdinc -fno-stack-protector -ARCHPICFLAGS = -fpic -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -ARCHDEFINES = -D__RGMP_KERNEL__ -D__RTOS_KERNEL__ -D__SHARE_KERNEL__ -ARCHINCLUDES = -I. -isystem $(TOPDIR)/include -I$(RGMPINCDIR) \ - -I$(TOPDIR)/configs/rgmp/include -I$(TOPDIR)/arch/rgmp/include/x86 -ARCHSCRIPT = - -CROSSDEV = -CC = $(CROSSDEV)gcc -CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld -AR = $(CROSSDEV)ar rcs -NM = $(CROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -CFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ - $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) -pipe -CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) -AFLAGS = $(CFLAGS) -D__ASSEMBLY__ - -ASMEXT = .S -OBJEXT = .o -LIBEXT = .a - -ifeq ($(HOSTOS),Cygwin) - EXEEXT = .exe -else - EXEEXT = -endif - -LDFLAGS += -nostdlib -EXTRA_LIBS = - - -MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) - -HOSTCC = gcc -HOSTINCLUDES = -I. -HOSTCFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ - $(ARCHCPUFLAGS) $(HOSTINCLUDES) $(ARCHDEFINES) -pipe -HOSTLDFLAGS = diff --git a/configs/rgmp/x86/default/defconfig b/configs/rgmp/x86/default/defconfig deleted file mode 100644 index 7eef1813ab..0000000000 --- a/configs/rgmp/x86/default/defconfig +++ /dev/null @@ -1,667 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Nuttx/ Configuration -# - -# -# Build Setup -# -# CONFIG_EXPERIMENTAL is not set -# CONFIG_DEFAULT_SMALL is not set -CONFIG_HOST_LINUX=y -# CONFIG_HOST_OSX is not set -# CONFIG_HOST_WINDOWS is not set -# CONFIG_HOST_OTHER is not set - -# -# Build Configuration -# -# CONFIG_APPS_DIR="../apps" -# CONFIG_BUILD_2PASS is not set - -# -# Binary Output Formats -# -# CONFIG_RRLOAD_BINARY is not set -# CONFIG_INTELHEX_BINARY is not set -# CONFIG_MOTOROLA_SREC is not set -# CONFIG_RAW_BINARY is not set - -# -# Customize Header Files -# -CONFIG_ARCH_STDINT_H=y -CONFIG_ARCH_STDBOOL_H=y -CONFIG_ARCH_MATH_H=y -# CONFIG_ARCH_FLOAT_H is not set -# CONFIG_ARCH_STDARG_H is not set - -# -# Debug Options -# -# CONFIG_DEBUG_FEATURES is not set -# CONFIG_ARCH_HAVE_STACKCHECK is not set -# CONFIG_ARCH_HAVE_HEAPCHECK is not set -CONFIG_DEBUG_SYMBOLS=y -# CONFIG_ARCH_HAVE_CUSTOMOPT is not set -CONFIG_DEBUG_NOOPT=y -# CONFIG_DEBUG_FULLOPT is not set - -# -# System Type -# -# CONFIG_ARCH_ARM is not set -# CONFIG_ARCH_AVR is not set -# CONFIG_ARCH_HC is not set -# CONFIG_ARCH_MIPS is not set -CONFIG_ARCH_RGMP=y -# CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_SIM is not set -# CONFIG_ARCH_X86 is not set -# CONFIG_ARCH_Z16 is not set -# CONFIG_ARCH_Z80 is not set -CONFIG_ARCH="rgmp" - -# -# RGMP Configuration Options -# -# CONFIG_RGMP_SUBARCH_ARM is not set -CONFIG_RGMP_SUBARCH_X86=y -CONFIG_RGMP_SUBARCH="x86" - -# -# x86 Peripheral Selections -# -CONFIG_COM1=y -CONFIG_COM2=y -# CONFIG_COM3 is not set -# CONFIG_COM4 is not set - -# -# Architecture Options -# -# CONFIG_ARCH_NOINTC is not set -# CONFIG_ARCH_VECNOTIRQ is not set -# CONFIG_ARCH_DMA is not set -# CONFIG_ARCH_HAVE_IRQPRIO is not set -# CONFIG_ARCH_ADDRENV is not set -# CONFIG_ARCH_HAVE_VFORK is not set -# CONFIG_ARCH_HAVE_MMU is not set -# CONFIG_ARCH_NAND_HWECC is not set -# CONFIG_ARCH_STACKDUMP is not set -# CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_IDLE_CUSTOM is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set -# CONFIG_ARCH_HAVE_RAMVECTORS is not set - -# -# Board Settings -# -CONFIG_BOARD_LOOPSPERMSEC=5000 -# CONFIG_ARCH_CALIBRATION is not set - -# -# Interrupt options -# -# CONFIG_ARCH_HAVE_INTERRUPTSTACK is not set -# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set - -# -# Boot options -# -# CONFIG_BOOT_RUNFROMEXTSRAM is not set -CONFIG_BOOT_RUNFROMFLASH=y -# CONFIG_BOOT_RUNFROMISRAM is not set -# CONFIG_BOOT_RUNFROMSDRAM is not set -# CONFIG_BOOT_COPYTORAM is not set - -# -# Boot Memory Configuration -# -CONFIG_RAM_START=0x0 -CONFIG_RAM_SIZE=0 -# CONFIG_ARCH_HAVE_SDRAM is not set - -# -# Board Selection -# -CONFIG_ARCH_BOARD_RGMP=y -# CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD="rgmp" - -# -# Common Board Options -# - -# -# Board-Specific Options -# - -# -# RTOS Features -# -# CONFIG_BOARD_INITIALIZE is not set -CONFIG_USEC_PER_TICK=1000 -# CONFIG_SYSTEM_TIME64 is not set -CONFIG_RR_INTERVAL=0 -# CONFIG_SCHED_CPULOAD is not set -# CONFIG_SCHED_INSTRUMENTATION is not set -CONFIG_TASK_NAME_SIZE=31 -# CONFIG_SCHED_HAVE_PARENT is not set -# CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2007 -CONFIG_START_MONTH=2 -CONFIG_START_DAY=27 -CONFIG_DEV_CONSOLE=y -# CONFIG_MUTEX_TYPES is not set -# CONFIG_PRIORITY_INHERITANCE is not set -# CONFIG_FDCLONE_DISABLE is not set -# CONFIG_FDCLONE_STDIO is not set -CONFIG_SDCLONE_DISABLE=y -# CONFIG_SCHED_WAITPID is not set -# CONFIG_SCHED_STARTHOOK is not set -# CONFIG_SCHED_ATEXIT is not set -# CONFIG_SCHED_ONEXIT is not set -CONFIG_USER_ENTRYPOINT="rgmp_main" -CONFIG_DISABLE_OS_API=y -# CONFIG_DISABLE_POSIX_TIMERS is not set -# CONFIG_DISABLE_PTHREAD is not set -# CONFIG_DISABLE_SIGNALS is not set -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_ENVIRON is not set - -# -# Signal Numbers -# -CONFIG_SIG_SIGUSR1=1 -CONFIG_SIG_SIGUSR2=2 -CONFIG_SIG_SIGALARM=3 -CONFIG_SIG_SIGCONDTIMEDOUT=16 - -# -# Sizes of configurable things (0 disables) -# -CONFIG_MAX_TASKS=64 -CONFIG_NPTHREAD_KEYS=4 -CONFIG_NFILE_DESCRIPTORS=32 -CONFIG_NFILE_STREAMS=16 -CONFIG_NAME_MAX=32 -CONFIG_PREALLOC_MQ_MSGS=32 -CONFIG_MQ_MAXMSGSIZE=32 -CONFIG_MAX_WDOGPARMS=4 -CONFIG_PREALLOC_WDOGS=32 -CONFIG_WDOG_INTRESERVE=4 -CONFIG_PREALLOC_TIMERS=8 - -# -# Stack and heap information -# -CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_USERMAIN_STACKSIZE=4096 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=8192 - -# -# Device Drivers -# -CONFIG_DISABLE_POLL=y -CONFIG_DEV_NULL=y -# CONFIG_DEV_ZERO is not set -# CONFIG_DEV_LOOP is not set -# CONFIG_RAMDISK is not set -# CONFIG_CAN is not set -# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set -# CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set -# CONFIG_I2C is not set -# CONFIG_SPI is not set -# CONFIG_I2S is not set -# CONFIG_RTC is not set -# CONFIG_WATCHDOG is not set -# CONFIG_ANALOG is not set -# CONFIG_AUDIO_DEVICES is not set -# CONFIG_VIDEO_DEVICES is not set -# CONFIG_BCH is not set -# CONFIG_INPUT is not set -# CONFIG_LCD is not set -# CONFIG_MMCSD is not set -# CONFIG_MTD is not set -CONFIG_NETDEVICES=y - -# -# General Ethernet MAC Driver Options -# -# CONFIG_NETDEV_MULTINIC is not set - -# -# External Ethernet MAC Device Support -# -# CONFIG_NET_DM90x0 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set -# CONFIG_NET_SLIP is not set -CONFIG_NET_VNET=y -CONFIG_VNET_NINTERFACES=1 -# CONFIG_PIPES is not set -# CONFIG_PM is not set -# CONFIG_POWER is not set -# CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set -CONFIG_SERIAL=y -# CONFIG_DEV_LOWCONSOLE is not set -# CONFIG_16550_UART is not set -# CONFIG_UART_SERIALDRIVER is not set -# CONFIG_UART0_SERIALDRIVER is not set -# CONFIG_UART1_SERIALDRIVER is not set -# CONFIG_UART2_SERIALDRIVER is not set -# CONFIG_UART3_SERIALDRIVER is not set -# CONFIG_UART4_SERIALDRIVER is not set -# CONFIG_UART5_SERIALDRIVER is not set -# CONFIG_UART6_SERIALDRIVER is not set -# CONFIG_UART7_SERIALDRIVER is not set -# CONFIG_UART8_SERIALDRIVER is not set -# CONFIG_SCI0_SERIALDRIVER is not set -# CONFIG_SCI1_SERIALDRIVER is not set -# CONFIG_USART0_SERIALDRIVER is not set -# CONFIG_USART1_SERIALDRIVER is not set -# CONFIG_USART2_SERIALDRIVER is not set -# CONFIG_USART3_SERIALDRIVER is not set -# CONFIG_USART4_SERIALDRIVER is not set -# CONFIG_USART5_SERIALDRIVER is not set -# CONFIG_USART6_SERIALDRIVER is not set -# CONFIG_USART7_SERIALDRIVER is not set -# CONFIG_USART8_SERIALDRIVER is not set - -# -# USART Configuration -# -# CONFIG_MCU_SERIAL is not set -# CONFIG_STANDARD_SERIAL is not set -# CONFIG_SERIAL_IFLOWCONTROL is not set -# CONFIG_SERIAL_OFLOWCONTROL is not set -# CONFIG_USBDEV is not set -# CONFIG_USBHOST is not set -# CONFIG_DRIVERS_WIRELESS is not set - -# -# System Logging Device Options -# - -# -# System Logging -# -# CONFIG_RAMLOG is not set - -# -# Networking Support -# -CONFIG_ARCH_HAVE_NET=y -# CONFIG_ARCH_HAVE_PHY is not set -CONFIG_NET=y -# CONFIG_NET_NOINTS is not set -CONFIG_NET_IPv4=y -# CONFIG_NET_PROMISCUOUS is not set -CONFIG_NSOCKET_DESCRIPTORS=5 -CONFIG_NET_NACTIVESOCKETS=16 -CONFIG_NET_SOCKOPTS=y -# CONFIG_NET_SOLINGER is not set -CONFIG_NET_ETH_MTU=1514 -# CONFIG_NET_TCPURGDATA is not set - -# -# TCP/IP Networking -# -CONFIG_NET_TCP=y -CONFIG_NET_TCP_CONNS=40 -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_TCP_READAHEAD=y -# CONFIG_NET_TCP_WRITE_BUFFERS is not set -CONFIG_NET_TCP_RECVDELAY=0 -# CONFIG_NET_TCPBACKLOG is not set -# CONFIG_NET_TCP_SPLIT is not set -# CONFIG_NET_SENDFILE is not set - -# -# UDP Networking -# -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NET_UDP_CONNS=8 -# CONFIG_NET_BROADCAST is not set -# CONFIG_NET_RXAVAIL is not set -CONFIG_NET_ICMP=y -CONFIG_NET_ICMP_PING=y -# CONFIG_NET_IGMP is not set -CONFIG_NET_STATISTICS=y -CONFIG_NET_ETH_TCP_RECVWNDO=1460 -CONFIG_NET_ARPTAB_SIZE=16 -# CONFIG_NET_ARP_IPIN is not set -CONFIG_NET_IOB=y -CONFIG_IOB_NBUFFERS=24 -CONFIG_IOB_BUFSIZE=196 -CONFIG_IOB_NCHAINS=8 -CONFIG_IOB_THROTTLE=0 - -# -# Routing Table Configuration -# -# CONFIG_NET_ROUTE is not set -CONFIG_NET_ETHERNET=y - -# -# File Systems -# - -# -# File system configuration -# -# CONFIG_DISABLE_MOUNTPOINT is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_FS_READABLE is not set -# CONFIG_FS_WRITABLE is not set -# CONFIG_FS_RAMMAP is not set -# CONFIG_FS_FAT is not set -# CONFIG_NFS is not set -# CONFIG_FS_NXFFS is not set -# CONFIG_FS_ROMFS is not set -# CONFIG_FS_SMARTFS is not set -# CONFIG_FS_PROCFS is not set - -# -# System Logging -# - - -# -# Graphics Support -# -# CONFIG_NX is not set - -# -# Memory Management -# -# CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=1 -# CONFIG_ARCH_HAVE_HEAP2 is not set -# CONFIG_GRAN is not set - -# -# Audio Support -# -# CONFIG_AUDIO is not set - -# -# Binary Formats -# -# CONFIG_BINFMT_DISABLE is not set -# CONFIG_BINFMT_EXEPATH is not set -# CONFIG_NXFLAT is not set -# CONFIG_ELF is not set -# CONFIG_BUILTIN is not set -# CONFIG_PIC is not set -# CONFIG_SYMTAB_ORDEREDBYNAME is not set - -# -# Library Routines -# - -# -# Standard C Library Options -# -CONFIG_STDIO_BUFFER_SIZE=64 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=2 -CONFIG_LIB_HOMEDIR="/" -# CONFIG_NOPRINTF_FIELDWIDTH is not set -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LIBC_LONG_LONG=y -CONFIG_LIB_RAND_ORDER=1 -# CONFIG_EOL_IS_CR is not set -# CONFIG_EOL_IS_LF is not set -# CONFIG_EOL_IS_BOTH_CRLF is not set -CONFIG_EOL_IS_EITHER_CRLF=y -# CONFIG_LIBC_EXECFUNCS is not set -CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 -# CONFIG_LIBC_STRERROR is not set -# CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_ARCH_LOWPUTC=y -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set -CONFIG_ARCH_OPTIMIZED_FUNCTIONS=y -CONFIG_ARCH_MEMCPY=y -CONFIG_ARCH_MEMCMP=y -CONFIG_ARCH_MEMMOVE=y -CONFIG_ARCH_MEMSET=y -CONFIG_ARCH_STRCHR=y -CONFIG_ARCH_STRCMP=y -CONFIG_ARCH_STRCPY=y -CONFIG_ARCH_STRNCPY=y -CONFIG_ARCH_STRLEN=y -CONFIG_ARCH_STRNLEN=y -# CONFIG_ARCH_BZERO is not set - -# -# Non-standard Library Support -# -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_LIB_KBDCODEC is not set -# CONFIG_LIB_SLCDCODEC is not set - -# -# Basic CXX Support -# -# CONFIG_C99_BOOL8 is not set -# CONFIG_HAVE_CXX is not set - -# -# Application Configuration -# - -# -# Built-In Applications -# - -# -# Examples -# -# CONFIG_EXAMPLES_BUTTONS is not set -# CONFIG_EXAMPLES_CAN is not set -# CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_DHCPD is not set -# CONFIG_EXAMPLES_ELF is not set -# CONFIG_EXAMPLES_FTPC is not set -# CONFIG_EXAMPLES_FTPD is not set -# CONFIG_EXAMPLES_HELLO is not set -# CONFIG_EXAMPLES_HELLOXX is not set -# CONFIG_EXAMPLES_JSON is not set -# CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set -# CONFIG_EXAMPLES_IGMP is not set -# CONFIG_EXAMPLES_LCDRW is not set -# CONFIG_EXAMPLES_MM is not set -# CONFIG_EXAMPLES_MODBUS is not set -# CONFIG_EXAMPLES_MOUNT is not set -# CONFIG_EXAMPLES_NETTEST is not set -# CONFIG_EXAMPLES_NRF24L01TERM is not set -# CONFIG_EXAMPLES_NSH is not set -# CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXTERM is not set -# CONFIG_EXAMPLES_NXFFS is not set -# CONFIG_EXAMPLES_NXFLAT is not set -# CONFIG_EXAMPLES_NXHELLO is not set -# CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NXLINES is not set -# CONFIG_EXAMPLES_NXTEXT is not set -# CONFIG_EXAMPLES_OSTEST is not set -# CONFIG_EXAMPLES_PASHELLO is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set -# CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_QENCODER is not set -CONFIG_EXAMPLES_RGMP=y -# CONFIG_EXAMPLES_ROMFS is not set -# CONFIG_EXAMPLES_SENDMAIL is not set -# CONFIG_EXAMPLES_SERLOOP is not set -# CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART is not set -# CONFIG_EXAMPLES_TCPECHO is not set -# CONFIG_EXAMPLES_TELNETD is not set -# CONFIG_EXAMPLES_THTTPD is not set -# CONFIG_EXAMPLES_TIFF is not set -# CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_UDP is not set -# CONFIG_EXAMPLES_DISCOVER is not set -# CONFIG_EXAMPLES_WEBSERVER is not set -# CONFIG_EXAMPLES_USBSERIAL is not set -# CONFIG_EXAMPLES_USBTERM is not set -# CONFIG_EXAMPLES_WATCHDOG is not set -# CONFIG_EXAMPLES_WGET is not set - -# -# Graphics Support -# -# CONFIG_TIFF is not set - -# -# Interpreters -# -# CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_PCODE is not set - -# -# Network Utilities -# - -# -# Networking Utilities -# -# CONFIG_NETUTILS_CODECS is not set -# CONFIG_NETUTILS_DHCPD is not set -# CONFIG_NETUTILS_FTPC is not set -# CONFIG_NETUTILS_FTPD is not set -# CONFIG_NETUTILS_JSON is not set -# CONFIG_NETUTILS_SMTP is not set -# CONFIG_NETUTILS_TELNETD is not set -# CONFIG_NETUTILS_TFTPC is not set -# CONFIG_NETUTILS_THTTPD is not set -# CONFIG_NETUTILS_NETLIB is not set -# CONFIG_NETUTILS_WEBCLIENT is not set -# CONFIG_NETUTILS_WEBSERVER is not set -# CONFIG_NETUTILS_DISCOVER is not set -# CONFIG_NETUTILS_XMLRPC is not set - -# -# FreeModBus -# -# CONFIG_MODBUS is not set - -# -# NSH Library -# -# CONFIG_NSH_LIBRARY is not set - -# -# NxWidgets/NxWM -# - -# -# Platform-specific Support -# -# CONFIG_PLATFORM_CONFIGDATA is not set - -# -# System Libraries and NSH Add-Ons -# - -# -# USB CDC/ACM Device Commands -# - -# -# USB Composite Device Commands -# - -# -# Custom Free Memory Command -# -# CONFIG_SYSTEM_FREE is not set - -# -# I2C tool -# - -# -# INI File Parser -# -# CONFIG_FSUTILS_INIFILE is not set - -# -# FLASH Program Installation -# -# CONFIG_SYSTEM_INSTALL is not set - -# -# FLASH Erase-all Command -# - -# -# NxPlayer media player library / command Line -# -# CONFIG_SYSTEM_NXPLAYER is not set - -# -# RAM test -# -# CONFIG_SYSTEM_RAMTEST is not set - -# -# readline() -# -# CONFIG_SYSTEM_READLINE is not set - -# -# Power Off -# -# CONFIG_SYSTEM_POWEROFF is not set - -# -# RAMTRON -# - -# -# SD Card -# - -# -# Sysinfo -# - -# -# USB Monitor -# - -# -# EMACS-like Command Line Editor -# -# CONFIG_SYSTEM_CLE is not set - -# -# VI Work-Alike Editor -# -# CONFIG_SYSTEM_VI is not set - -# -# Stack Monitor -# - -# -# USB Mass Storage Device Commands -# - -# -# Zmodem Commands -# -# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/rgmp/x86/default/setenv.sh b/configs/rgmp/x86/default/setenv.sh deleted file mode 100755 index bfb02549bd..0000000000 --- a/configs/rgmp/x86/default/setenv.sh +++ /dev/null @@ -1,47 +0,0 @@ -#!/bin/bash -# config/rgmp/default/setenv.sh -# -# Copyright (C) 2011 Yu Qiang. All rights reserved. -# Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Authors: Yu Qiang -# Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if [ "$(basename $0)" = "setenv.sh" ] ; then - echo "You must source this script, not run it!" 1>&2 - exit 1 -fi - -if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi - -#export NUTTX_BIN= -#export PATH=${NUTTX_BIN}:/sbin:/usr/sbin:${PATH_ORIG} - -echo "PATH : ${PATH}" diff --git a/configs/rgmp/x86/helloxx/Make.defs b/configs/rgmp/x86/helloxx/Make.defs deleted file mode 100644 index 440c859135..0000000000 --- a/configs/rgmp/x86/helloxx/Make.defs +++ /dev/null @@ -1,105 +0,0 @@ -#################################################################################### -# configs/rgmp/default/Make.defs -# -# Copyright (C) 2011 Yu Qiang. All rights reserved. -# Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Authors: Yu Qiang -# Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk - -RGMPLIBDIR := $(RGMP_INST_DIR)/lib -RGMPINCDIR := $(RGMP_INST_DIR)/include -RGMPLKSCPT := $(RGMP_INST_DIR)/etc/rgmp.ld - -HOSTOS = ${shell uname -o} - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION = -O2 -gstabs -else - ARCHOPTIMIZATION = -O2 -endif - -ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti -ARCHCPUFLAGS = -fno-builtin -nostdinc -fno-stack-protector -ARCHPICFLAGS = -fpic -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -ARCHWARNINGSXX = -Wall -Wshadow -Wundef -ARCHDEFINES = -D__RGMP_KERNEL__ -D__RTOS_KERNEL__ -D__SHARE_KERNEL__ -ARCHINCLUDES = -I. -isystem $(TOPDIR)/include -I$(RGMPINCDIR) \ - -I$(TOPDIR)/configs/rgmp/include -I$(TOPDIR)/arch/rgmp/include/x86 - -ARCHXXINCLUDES = -I$(TOPDIR)/include/cxx -isystem $(TOPDIR)/include -I$(RGMPINCDIR) \ - -I$(TOPDIR)/configs/rgmp/include -I$(TOPDIR)/arch/rgmp/include/x86 \ - -I$(TOPDIR)/include/uClibc++ - -CROSSDEV = -CC = $(CROSSDEV)gcc -CXX = $(CROSSDEV)g++ -CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld -AR = $(CROSSDEV)ar rcs -NM = $(CROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -CFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ - $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) -pipe -CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) -CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) \ - $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -nodefaultlibs \ - -nostdinc++ -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -AFLAGS = $(CFLAGS) -D__ASSEMBLY__ - -ASMEXT = .S -OBJEXT = .o -LIBEXT = .a - -ifeq ($(HOSTOS),Cygwin) - EXEEXT = .exe -else - EXEEXT = -endif - -LDFLAGS += -nostdlib -EXTRA_LIBS = $(shell $(CC) -print-file-name=libsupc++.a) \ - $(shell $(CC) -print-file-name=libgcc_eh.a) - -MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) - -HOSTCC = gcc -HOSTINCLUDES = -I. -HOSTCFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ - $(ARCHCPUFLAGS) $(HOSTINCLUDES) $(ARCHDEFINES) -pipe -HOSTLDFLAGS = diff --git a/configs/rgmp/x86/helloxx/defconfig b/configs/rgmp/x86/helloxx/defconfig deleted file mode 100644 index 3ac271a21a..0000000000 --- a/configs/rgmp/x86/helloxx/defconfig +++ /dev/null @@ -1,697 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Nuttx/ Configuration -# - -# -# Build Setup -# -# CONFIG_EXPERIMENTAL is not set -# CONFIG_DEFAULT_SMALL is not set -CONFIG_HOST_LINUX=y -# CONFIG_HOST_OSX is not set -# CONFIG_HOST_WINDOWS is not set -# CONFIG_HOST_OTHER is not set - -# -# Build Configuration -# -# CONFIG_APPS_DIR="../apps" -# CONFIG_BUILD_2PASS is not set - -# -# Binary Output Formats -# -# CONFIG_RRLOAD_BINARY is not set -# CONFIG_INTELHEX_BINARY is not set -# CONFIG_MOTOROLA_SREC is not set -# CONFIG_RAW_BINARY is not set - -# -# Customize Header Files -# -CONFIG_ARCH_STDINT_H=y -CONFIG_ARCH_STDBOOL_H=y -CONFIG_ARCH_MATH_H=y -# CONFIG_ARCH_FLOAT_H is not set -# CONFIG_ARCH_STDARG_H is not set - -# -# Debug Options -# -# CONFIG_DEBUG_FEATURES is not set -# CONFIG_ARCH_HAVE_STACKCHECK is not set -# CONFIG_ARCH_HAVE_HEAPCHECK is not set -CONFIG_DEBUG_INFO=y - -# -# Subsystem Debug Options -# -# CONFIG_DEBUG_MM is not set -# CONFIG_DEBUG_SCHED is not set -# CONFIG_DEBUG_NET is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_DEBUG_LIB is not set -# CONFIG_DEBUG_BINFMT is not set -# CONFIG_DEBUG_GRAPHICS is not set -# CONFIG_DEBUG_IRQ is not set - -# -# Driver Debug Options -# -# CONFIG_DEBUG_ANALOG is not set -# CONFIG_DEBUG_GPIO is not set -# CONFIG_DEBUG_AUDIO is not set -CONFIG_DEBUG_SYMBOLS=y -# CONFIG_ARCH_HAVE_CUSTOMOPT is not set -CONFIG_DEBUG_NOOPT=y -# CONFIG_DEBUG_FULLOPT is not set - -# -# System Type -# -# CONFIG_ARCH_ARM is not set -# CONFIG_ARCH_AVR is not set -# CONFIG_ARCH_HC is not set -# CONFIG_ARCH_MIPS is not set -CONFIG_ARCH_RGMP=y -# CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_SIM is not set -# CONFIG_ARCH_X86 is not set -# CONFIG_ARCH_Z16 is not set -# CONFIG_ARCH_Z80 is not set -CONFIG_ARCH="rgmp" - -# -# RGMP Configuration Options -# -# CONFIG_RGMP_SUBARCH_ARM is not set -CONFIG_RGMP_SUBARCH_X86=y -CONFIG_RGMP_SUBARCH="x86" - -# -# x86 Peripheral Selections -# -CONFIG_COM1=y -CONFIG_COM2=y -# CONFIG_COM3 is not set -# CONFIG_COM4 is not set - -# -# Architecture Options -# -# CONFIG_ARCH_NOINTC is not set -# CONFIG_ARCH_VECNOTIRQ is not set -# CONFIG_ARCH_DMA is not set -# CONFIG_ARCH_HAVE_IRQPRIO is not set -# CONFIG_ARCH_ADDRENV is not set -# CONFIG_ARCH_HAVE_VFORK is not set -# CONFIG_ARCH_HAVE_MMU is not set -# CONFIG_ARCH_NAND_HWECC is not set -# CONFIG_ARCH_STACKDUMP is not set -# CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_IDLE_CUSTOM is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set -# CONFIG_ARCH_HAVE_RAMVECTORS is not set - -# -# Board Settings -# -CONFIG_BOARD_LOOPSPERMSEC=5000 -# CONFIG_ARCH_CALIBRATION is not set - -# -# Interrupt options -# -# CONFIG_ARCH_HAVE_INTERRUPTSTACK is not set -# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set - -# -# Boot options -# -# CONFIG_BOOT_RUNFROMEXTSRAM is not set -CONFIG_BOOT_RUNFROMFLASH=y -# CONFIG_BOOT_RUNFROMISRAM is not set -# CONFIG_BOOT_RUNFROMSDRAM is not set -# CONFIG_BOOT_COPYTORAM is not set - -# -# Boot Memory Configuration -# -CONFIG_RAM_START=0x0 -CONFIG_RAM_SIZE=0 -# CONFIG_ARCH_HAVE_SDRAM is not set - -# -# Board Selection -# -CONFIG_ARCH_BOARD_RGMP=y -# CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD="rgmp" - -# -# Common Board Options -# - -# -# Board-Specific Options -# - -# -# RTOS Features -# -# CONFIG_BOARD_INITIALIZE is not set -CONFIG_USEC_PER_TICK=1000 -# CONFIG_SYSTEM_TIME64 is not set -CONFIG_RR_INTERVAL=0 -# CONFIG_SCHED_CPULOAD is not set -# CONFIG_SCHED_INSTRUMENTATION is not set -CONFIG_TASK_NAME_SIZE=31 -# CONFIG_SCHED_HAVE_PARENT is not set -# CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2007 -CONFIG_START_MONTH=2 -CONFIG_START_DAY=27 -CONFIG_DEV_CONSOLE=y -# CONFIG_MUTEX_TYPES is not set -# CONFIG_PRIORITY_INHERITANCE is not set -# CONFIG_FDCLONE_DISABLE is not set -# CONFIG_FDCLONE_STDIO is not set -CONFIG_SDCLONE_DISABLE=y -# CONFIG_SCHED_WAITPID is not set -# CONFIG_SCHED_STARTHOOK is not set -# CONFIG_SCHED_ATEXIT is not set -# CONFIG_SCHED_ONEXIT is not set -CONFIG_USER_ENTRYPOINT="helloxx_main" -CONFIG_DISABLE_OS_API=y -# CONFIG_DISABLE_POSIX_TIMERS is not set -# CONFIG_DISABLE_PTHREAD is not set -# CONFIG_DISABLE_SIGNALS is not set -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_ENVIRON is not set - -# -# Signal Numbers -# -CONFIG_SIG_SIGUSR1=1 -CONFIG_SIG_SIGUSR2=2 -CONFIG_SIG_SIGALARM=3 -CONFIG_SIG_SIGCONDTIMEDOUT=16 - -# -# Sizes of configurable things (0 disables) -# -CONFIG_MAX_TASKS=64 -CONFIG_NPTHREAD_KEYS=4 -CONFIG_NFILE_DESCRIPTORS=32 -CONFIG_NFILE_STREAMS=16 -CONFIG_NAME_MAX=32 -CONFIG_PREALLOC_MQ_MSGS=32 -CONFIG_MQ_MAXMSGSIZE=32 -CONFIG_MAX_WDOGPARMS=4 -CONFIG_PREALLOC_WDOGS=32 -CONFIG_WDOG_INTRESERVE=4 -CONFIG_PREALLOC_TIMERS=8 - -# -# Stack and heap information -# -CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_USERMAIN_STACKSIZE=4096 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=8192 - -# -# Device Drivers -# -CONFIG_DISABLE_POLL=y -CONFIG_DEV_NULL=y -# CONFIG_DEV_ZERO is not set -# CONFIG_DEV_LOOP is not set -# CONFIG_RAMDISK is not set -# CONFIG_CAN is not set -# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set -# CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set -# CONFIG_I2C is not set -# CONFIG_SPI is not set -# CONFIG_I2S is not set -# CONFIG_RTC is not set -# CONFIG_WATCHDOG is not set -# CONFIG_ANALOG is not set -# CONFIG_AUDIO_DEVICES is not set -# CONFIG_VIDEO_DEVICES is not set -# CONFIG_BCH is not set -# CONFIG_INPUT is not set -# CONFIG_LCD is not set -# CONFIG_MMCSD is not set -# CONFIG_MTD is not set -CONFIG_NETDEVICES=y - -# -# General Ethernet MAC Driver Options -# -# CONFIG_NETDEV_MULTINIC is not set -# CONFIG_NET_DUMPPACKET is not set - -# -# External Ethernet MAC Device Support -# -# CONFIG_NET_DM90x0 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set -# CONFIG_NET_SLIP is not set -CONFIG_NET_VNET=y -CONFIG_VNET_NINTERFACES=1 -# CONFIG_PIPES is not set -# CONFIG_PM is not set -# CONFIG_POWER is not set -# CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set -CONFIG_SERIAL=y -# CONFIG_DEV_LOWCONSOLE is not set -# CONFIG_16550_UART is not set -# CONFIG_UART_SERIALDRIVER is not set -# CONFIG_UART0_SERIALDRIVER is not set -# CONFIG_UART1_SERIALDRIVER is not set -# CONFIG_UART2_SERIALDRIVER is not set -# CONFIG_UART3_SERIALDRIVER is not set -# CONFIG_UART4_SERIALDRIVER is not set -# CONFIG_UART5_SERIALDRIVER is not set -# CONFIG_UART6_SERIALDRIVER is not set -# CONFIG_UART7_SERIALDRIVER is not set -# CONFIG_UART8_SERIALDRIVER is not set -# CONFIG_SCI0_SERIALDRIVER is not set -# CONFIG_SCI1_SERIALDRIVER is not set -# CONFIG_USART0_SERIALDRIVER is not set -# CONFIG_USART1_SERIALDRIVER is not set -# CONFIG_USART2_SERIALDRIVER is not set -# CONFIG_USART3_SERIALDRIVER is not set -# CONFIG_USART4_SERIALDRIVER is not set -# CONFIG_USART5_SERIALDRIVER is not set -# CONFIG_USART6_SERIALDRIVER is not set -# CONFIG_USART7_SERIALDRIVER is not set -# CONFIG_USART8_SERIALDRIVER is not set - -# -# USART Configuration -# -# CONFIG_MCU_SERIAL is not set -# CONFIG_STANDARD_SERIAL is not set -# CONFIG_SERIAL_IFLOWCONTROL is not set -# CONFIG_SERIAL_OFLOWCONTROL is not set -# CONFIG_USBDEV is not set -# CONFIG_USBHOST is not set -# CONFIG_DRIVERS_WIRELESS is not set - -# -# System Logging Device Options -# - -# -# System Logging -# -# CONFIG_RAMLOG is not set - -# -# Networking Support -# -CONFIG_ARCH_HAVE_NET=y -# CONFIG_ARCH_HAVE_PHY is not set -CONFIG_NET=y -# CONFIG_NET_NOINTS is not set -CONFIG_NET_IPv4=y -# CONFIG_NET_PROMISCUOUS is not set -CONFIG_NSOCKET_DESCRIPTORS=5 -CONFIG_NET_NACTIVESOCKETS=16 -CONFIG_NET_SOCKOPTS=y -# CONFIG_NET_SOLINGER is not set -CONFIG_NET_ETH_MTU=1514 -# CONFIG_NET_TCPURGDATA is not set - -# -# TCP/IP Networking -# -CONFIG_NET_TCP=y -CONFIG_NET_TCP_CONNS=40 -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_TCP_READAHEAD=y -# CONFIG_NET_TCP_WRITE_BUFFERS is not set -CONFIG_NET_TCP_RECVDELAY=0 -# CONFIG_NET_TCPBACKLOG is not set -# CONFIG_NET_TCP_SPLIT is not set -# CONFIG_NET_SENDFILE is not set - -# -# UDP Networking -# -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NET_UDP_CONNS=8 -# CONFIG_NET_BROADCAST is not set -# CONFIG_NET_RXAVAIL is not set -CONFIG_NET_ICMP=y -CONFIG_NET_ICMP_PING=y -# CONFIG_NET_IGMP is not set -CONFIG_NET_STATISTICS=y -CONFIG_NET_ETH_TCP_RECVWNDO=1460 -CONFIG_NET_ARPTAB_SIZE=16 -# CONFIG_NET_ARP_IPIN is not set -CONFIG_NET_IOB=y -CONFIG_IOB_NBUFFERS=24 -CONFIG_IOB_BUFSIZE=196 -CONFIG_IOB_NCHAINS=8 -CONFIG_IOB_THROTTLE=0 - -# -# Routing Table Configuration -# -# CONFIG_NET_ROUTE is not set -CONFIG_NET_ETHERNET=y - -# -# File Systems -# - -# -# File system configuration -# -# CONFIG_DISABLE_MOUNTPOINT is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_FS_READABLE is not set -# CONFIG_FS_WRITABLE is not set -# CONFIG_FS_RAMMAP is not set -# CONFIG_FS_FAT is not set -# CONFIG_NFS is not set -# CONFIG_FS_NXFFS is not set -# CONFIG_FS_ROMFS is not set -# CONFIG_FS_SMARTFS is not set -# CONFIG_FS_PROCFS is not set - -# -# System Logging -# - - -# -# Graphics Support -# -# CONFIG_NX is not set - -# -# Memory Management -# -# CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=1 -# CONFIG_ARCH_HAVE_HEAP2 is not set -# CONFIG_GRAN is not set - -# -# Audio Support -# -# CONFIG_AUDIO is not set - -# -# Binary Formats -# -# CONFIG_BINFMT_DISABLE is not set -# CONFIG_BINFMT_EXEPATH is not set -# CONFIG_NXFLAT is not set -# CONFIG_ELF is not set -# CONFIG_BUILTIN is not set -# CONFIG_PIC is not set -# CONFIG_SYMTAB_ORDEREDBYNAME is not set - -# -# Library Routines -# - -# -# Standard C Library Options -# -CONFIG_STDIO_BUFFER_SIZE=64 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=2 -CONFIG_LIB_HOMEDIR="/" -# CONFIG_NOPRINTF_FIELDWIDTH is not set -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LIBC_LONG_LONG=y -CONFIG_LIB_RAND_ORDER=1 -# CONFIG_EOL_IS_CR is not set -# CONFIG_EOL_IS_LF is not set -# CONFIG_EOL_IS_BOTH_CRLF is not set -CONFIG_EOL_IS_EITHER_CRLF=y -# CONFIG_LIBC_EXECFUNCS is not set -CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 -# CONFIG_LIBC_STRERROR is not set -# CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_ARCH_LOWPUTC=y -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set -CONFIG_ARCH_OPTIMIZED_FUNCTIONS=y -CONFIG_ARCH_MEMCPY=y -CONFIG_ARCH_MEMCMP=y -CONFIG_ARCH_MEMMOVE=y -CONFIG_ARCH_MEMSET=y -CONFIG_ARCH_STRCHR=y -CONFIG_ARCH_STRCMP=y -CONFIG_ARCH_STRCPY=y -CONFIG_ARCH_STRNCPY=y -CONFIG_ARCH_STRLEN=y -CONFIG_ARCH_STRNLEN=y -# CONFIG_ARCH_BZERO is not set - -# -# Non-standard Library Support -# -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_LIB_KBDCODEC is not set -# CONFIG_LIB_SLCDCODEC is not set - -# -# Basic CXX Support -# -# CONFIG_C99_BOOL8 is not set -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -# CONFIG_CXX_NEWLONG is not set - -# -# uClibc++ Standard C++ Library -# -# CONFIG_UCLIBCXX is not set - -# -# Application Configuration -# - -# -# Built-In Applications -# - -# -# Examples -# -# CONFIG_EXAMPLES_BUTTONS is not set -# CONFIG_EXAMPLES_CAN is not set -# CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CXXTEST is not set -# CONFIG_EXAMPLES_DHCPD is not set -# CONFIG_EXAMPLES_ELF is not set -# CONFIG_EXAMPLES_FTPC is not set -# CONFIG_EXAMPLES_FTPD is not set -# CONFIG_EXAMPLES_HELLO is not set -CONFIG_EXAMPLES_HELLOXX=y -CONFIG_EXAMPLES_HELLOXX_CXXINITIALIZE=y -# CONFIG_EXAMPLES_JSON is not set -# CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set -# CONFIG_EXAMPLES_IGMP is not set -# CONFIG_EXAMPLES_LCDRW is not set -# CONFIG_EXAMPLES_MM is not set -# CONFIG_EXAMPLES_MODBUS is not set -# CONFIG_EXAMPLES_MOUNT is not set -# CONFIG_EXAMPLES_NETTEST is not set -# CONFIG_EXAMPLES_NRF24L01TERM is not set -# CONFIG_EXAMPLES_NSH is not set -# CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXTERM is not set -# CONFIG_EXAMPLES_NXFFS is not set -# CONFIG_EXAMPLES_NXFLAT is not set -# CONFIG_EXAMPLES_NXHELLO is not set -# CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NXLINES is not set -# CONFIG_EXAMPLES_NXTEXT is not set -# CONFIG_EXAMPLES_OSTEST is not set -# CONFIG_EXAMPLES_PASHELLO is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set -# CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set -# CONFIG_EXAMPLES_ROMFS is not set -# CONFIG_EXAMPLES_SENDMAIL is not set -# CONFIG_EXAMPLES_SERLOOP is not set -# CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART is not set -# CONFIG_EXAMPLES_TCPECHO is not set -# CONFIG_EXAMPLES_TELNETD is not set -# CONFIG_EXAMPLES_THTTPD is not set -# CONFIG_EXAMPLES_TIFF is not set -# CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_UDP is not set -# CONFIG_EXAMPLES_DISCOVER is not set -# CONFIG_EXAMPLES_WEBSERVER is not set -# CONFIG_EXAMPLES_USBSERIAL is not set -# CONFIG_EXAMPLES_USBTERM is not set -# CONFIG_EXAMPLES_WATCHDOG is not set -# CONFIG_EXAMPLES_WGET is not set - -# -# Graphics Support -# -# CONFIG_TIFF is not set - -# -# Interpreters -# -# CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_PCODE is not set - -# -# Network Utilities -# - -# -# Networking Utilities -# -# CONFIG_NETUTILS_CODECS is not set -# CONFIG_NETUTILS_DHCPD is not set -# CONFIG_NETUTILS_FTPC is not set -# CONFIG_NETUTILS_FTPD is not set -# CONFIG_NETUTILS_JSON is not set -# CONFIG_NETUTILS_SMTP is not set -# CONFIG_NETUTILS_TELNETD is not set -# CONFIG_NETUTILS_TFTPC is not set -# CONFIG_NETUTILS_THTTPD is not set -# CONFIG_NETUTILS_NETLIB is not set -# CONFIG_NETUTILS_WEBCLIENT is not set -# CONFIG_NETUTILS_WEBSERVER is not set -# CONFIG_NETUTILS_DISCOVER is not set -# CONFIG_NETUTILS_XMLRPC is not set - -# -# FreeModBus -# -# CONFIG_MODBUS is not set - -# -# NSH Library -# -# CONFIG_NSH_LIBRARY is not set - -# -# NxWidgets/NxWM -# - -# -# Platform-specific Support -# -# CONFIG_PLATFORM_CONFIGDATA is not set - -# -# System Libraries and NSH Add-Ons -# - -# -# USB CDC/ACM Device Commands -# - -# -# USB Composite Device Commands -# - -# -# Custom Free Memory Command -# -# CONFIG_SYSTEM_FREE is not set - -# -# I2C tool -# - -# -# INI File Parser -# -# CONFIG_FSUTILS_INIFILE is not set - -# -# FLASH Program Installation -# -# CONFIG_SYSTEM_INSTALL is not set - -# -# FLASH Erase-all Command -# - -# -# NxPlayer media player library / command Line -# -# CONFIG_SYSTEM_NXPLAYER is not set - -# -# RAM test -# -# CONFIG_SYSTEM_RAMTEST is not set - -# -# readline() -# -# CONFIG_SYSTEM_READLINE is not set - -# -# Power Off -# -# CONFIG_SYSTEM_POWEROFF is not set - -# -# RAMTRON -# - -# -# SD Card -# - -# -# Sysinfo -# - -# -# USB Monitor -# - -# -# EMACS-like Command Line Editor -# -# CONFIG_SYSTEM_CLE is not set - -# -# VI Work-Alike Editor -# -# CONFIG_SYSTEM_VI is not set - -# -# Stack Monitor -# - -# -# USB Mass Storage Device Commands -# - -# -# Zmodem Commands -# -# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/rgmp/x86/helloxx/setenv.sh b/configs/rgmp/x86/helloxx/setenv.sh deleted file mode 100755 index a6a533e477..0000000000 --- a/configs/rgmp/x86/helloxx/setenv.sh +++ /dev/null @@ -1,47 +0,0 @@ -#!/bin/bash -# config/rgmp/default/setenv.sh -# -# Copyright (C) 2011 Yu Qiang. All rights reserved. -# Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Authors: Yu Qiang -# Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if [ "$(basename $0)" = "setenv.sh" ] ; then - echo "You must source this script, not run it!" 1>&2 - exit 1 -fi - -if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi - -#export NUTTX_BIN= -#export PATH=${NUTTX_BIN}:/sbin:/usr/sbin:${PATH_ORIG} - -echo "PATH : ${PATH}" diff --git a/configs/rgmp/x86/nsh/Make.defs b/configs/rgmp/x86/nsh/Make.defs deleted file mode 100644 index fb81d4f577..0000000000 --- a/configs/rgmp/x86/nsh/Make.defs +++ /dev/null @@ -1,95 +0,0 @@ -############################################################################ -# configs/rgmp/nsh/Make.defs -# -# Copyright (C) 2011 Yu Qiang. All rights reserved. -# Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Authors: Yu Qiang -# Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk - -RGMPLIBDIR := $(RGMP_INST_DIR)/lib -RGMPINCDIR := $(RGMP_INST_DIR)/include -RGMPLKSCPT := $(RGMP_INST_DIR)/etc/rgmp.ld - -HOSTOS = ${shell uname -o} - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION = -O2 -gstabs -else - ARCHOPTIMIZATION = -O2 -endif - -ARCHCPUFLAGS = -fno-builtin -nostdinc -fno-stack-protector -ARCHPICFLAGS = -fpic -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -ARCHDEFINES = -D__RGMP_KERNEL__ -D__RTOS_KERNEL__ -D__SHARE_KERNEL__ -ARCHINCLUDES = -I. -isystem $(TOPDIR)/include -I$(RGMPINCDIR) \ - -I$(TOPDIR)/configs/rgmp/include -I$(TOPDIR)/arch/rgmp/include/x86 -ARCHSCRIPT = - -CROSSDEV = -CC = $(CROSSDEV)gcc -CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld -AR = $(CROSSDEV)ar rcs -NM = $(CROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -CFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ - $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) -pipe -CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) -AFLAGS = $(CFLAGS) -D__ASSEMBLY__ - -ASMEXT = .S -OBJEXT = .o -LIBEXT = .a - -ifeq ($(HOSTOS),Cygwin) - EXEEXT = .exe -else - EXEEXT = -endif - -LDFLAGS += -nostdlib -EXTRA_LIBS = - - -MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) - -HOSTCC = gcc -HOSTINCLUDES = -I. -HOSTCFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ - $(ARCHCPUFLAGS) $(HOSTINCLUDES) $(ARCHDEFINES) -pipe -HOSTLDFLAGS = diff --git a/configs/rgmp/x86/nsh/defconfig b/configs/rgmp/x86/nsh/defconfig deleted file mode 100644 index 4eac635072..0000000000 --- a/configs/rgmp/x86/nsh/defconfig +++ /dev/null @@ -1,781 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Nuttx/ Configuration -# - -# -# Build Setup -# -# CONFIG_EXPERIMENTAL is not set -# CONFIG_DEFAULT_SMALL is not set -CONFIG_HOST_LINUX=y -# CONFIG_HOST_OSX is not set -# CONFIG_HOST_WINDOWS is not set -# CONFIG_HOST_OTHER is not set - -# -# Build Configuration -# -# CONFIG_APPS_DIR="../apps" -# CONFIG_BUILD_2PASS is not set - -# -# Binary Output Formats -# -# CONFIG_RRLOAD_BINARY is not set -# CONFIG_INTELHEX_BINARY is not set -# CONFIG_MOTOROLA_SREC is not set -# CONFIG_RAW_BINARY is not set - -# -# Customize Header Files -# -CONFIG_ARCH_STDINT_H=y -CONFIG_ARCH_STDBOOL_H=y -CONFIG_ARCH_MATH_H=y -# CONFIG_ARCH_FLOAT_H is not set -# CONFIG_ARCH_STDARG_H is not set - -# -# Debug Options -# -# CONFIG_DEBUG_FEATURES is not set -# CONFIG_ARCH_HAVE_STACKCHECK is not set -# CONFIG_ARCH_HAVE_HEAPCHECK is not set -# CONFIG_DEBUG_INFO is not set - -# -# Subsystem Debug Options -# -# CONFIG_DEBUG_MM is not set -# CONFIG_DEBUG_SCHED is not set -# CONFIG_DEBUG_NET is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_DEBUG_LIB is not set -# CONFIG_DEBUG_BINFMT is not set -# CONFIG_DEBUG_GRAPHICS is not set -# CONFIG_DEBUG_IRQ is not set - -# -# Driver Debug Options -# -# CONFIG_DEBUG_ANALOG is not set -# CONFIG_DEBUG_GPIO is not set -# CONFIG_DEBUG_AUDIO is not set -CONFIG_DEBUG_SYMBOLS=y -# CONFIG_ARCH_HAVE_CUSTOMOPT is not set -CONFIG_DEBUG_NOOPT=y -# CONFIG_DEBUG_FULLOPT is not set - -# -# System Type -# -# CONFIG_ARCH_ARM is not set -# CONFIG_ARCH_AVR is not set -# CONFIG_ARCH_HC is not set -# CONFIG_ARCH_MIPS is not set -CONFIG_ARCH_RGMP=y -# CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_SIM is not set -# CONFIG_ARCH_X86 is not set -# CONFIG_ARCH_Z16 is not set -# CONFIG_ARCH_Z80 is not set -CONFIG_ARCH="rgmp" - -# -# RGMP Configuration Options -# -# CONFIG_RGMP_SUBARCH_ARM is not set -CONFIG_RGMP_SUBARCH_X86=y -CONFIG_RGMP_SUBARCH="x86" - -# -# x86 Peripheral Selections -# -CONFIG_COM1=y -CONFIG_COM2=y -# CONFIG_COM3 is not set -# CONFIG_COM4 is not set - -# -# Architecture Options -# -# CONFIG_ARCH_NOINTC is not set -# CONFIG_ARCH_VECNOTIRQ is not set -# CONFIG_ARCH_DMA is not set -# CONFIG_ARCH_HAVE_IRQPRIO is not set -# CONFIG_ARCH_ADDRENV is not set -# CONFIG_ARCH_HAVE_VFORK is not set -# CONFIG_ARCH_HAVE_MMU is not set -# CONFIG_ARCH_NAND_HWECC is not set -# CONFIG_ARCH_STACKDUMP is not set -# CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_IDLE_CUSTOM is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set -# CONFIG_ARCH_HAVE_RAMVECTORS is not set - -# -# Board Settings -# -CONFIG_BOARD_LOOPSPERMSEC=5000 -# CONFIG_ARCH_CALIBRATION is not set - -# -# Interrupt options -# -# CONFIG_ARCH_HAVE_INTERRUPTSTACK is not set -# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set - -# -# Boot options -# -# CONFIG_BOOT_RUNFROMEXTSRAM is not set -CONFIG_BOOT_RUNFROMFLASH=y -# CONFIG_BOOT_RUNFROMISRAM is not set -# CONFIG_BOOT_RUNFROMSDRAM is not set -# CONFIG_BOOT_COPYTORAM is not set - -# -# Boot Memory Configuration -# -CONFIG_RAM_START=0x0 -CONFIG_RAM_SIZE=0 -# CONFIG_ARCH_HAVE_SDRAM is not set - -# -# Board Selection -# -CONFIG_ARCH_BOARD_RGMP=y -# CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD="rgmp" - -# -# Common Board Options -# -CONFIG_NSH_MMCSDMINOR=0 - -# -# Board-Specific Options -# - -# -# RTOS Features -# -# CONFIG_BOARD_INITIALIZE is not set -CONFIG_USEC_PER_TICK=1000 -# CONFIG_SYSTEM_TIME64 is not set -CONFIG_RR_INTERVAL=0 -# CONFIG_SCHED_CPULOAD is not set -# CONFIG_SCHED_INSTRUMENTATION is not set -CONFIG_TASK_NAME_SIZE=31 -# CONFIG_SCHED_HAVE_PARENT is not set -# CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2007 -CONFIG_START_MONTH=2 -CONFIG_START_DAY=27 -CONFIG_DEV_CONSOLE=y -# CONFIG_MUTEX_TYPES is not set -# CONFIG_PRIORITY_INHERITANCE is not set -# CONFIG_FDCLONE_DISABLE is not set -# CONFIG_FDCLONE_STDIO is not set -CONFIG_SDCLONE_DISABLE=y -# CONFIG_SCHED_WAITPID is not set -# CONFIG_SCHED_STARTHOOK is not set -# CONFIG_SCHED_ATEXIT is not set -# CONFIG_SCHED_ONEXIT is not set -CONFIG_USER_ENTRYPOINT="nsh_main" -CONFIG_DISABLE_OS_API=y -# CONFIG_DISABLE_POSIX_TIMERS is not set -# CONFIG_DISABLE_PTHREAD is not set -# CONFIG_DISABLE_SIGNALS is not set -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_ENVIRON is not set - -# -# Signal Numbers -# -CONFIG_SIG_SIGUSR1=1 -CONFIG_SIG_SIGUSR2=2 -CONFIG_SIG_SIGALARM=3 -CONFIG_SIG_SIGCONDTIMEDOUT=16 - -# -# Sizes of configurable things (0 disables) -# -CONFIG_MAX_TASKS=64 -CONFIG_NPTHREAD_KEYS=4 -CONFIG_NFILE_DESCRIPTORS=32 -CONFIG_NFILE_STREAMS=16 -CONFIG_NAME_MAX=32 -CONFIG_PREALLOC_MQ_MSGS=32 -CONFIG_MQ_MAXMSGSIZE=32 -CONFIG_MAX_WDOGPARMS=4 -CONFIG_PREALLOC_WDOGS=32 -CONFIG_WDOG_INTRESERVE=4 -CONFIG_PREALLOC_TIMERS=8 - -# -# Stack and heap information -# -CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_USERMAIN_STACKSIZE=4096 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=8192 - -# -# Device Drivers -# -CONFIG_DISABLE_POLL=y -CONFIG_DEV_NULL=y -# CONFIG_DEV_ZERO is not set -# CONFIG_DEV_LOOP is not set -# CONFIG_RAMDISK is not set -# CONFIG_CAN is not set -# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set -# CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set -# CONFIG_I2C is not set -# CONFIG_SPI is not set -# CONFIG_I2S is not set -# CONFIG_RTC is not set -# CONFIG_WATCHDOG is not set -# CONFIG_ANALOG is not set -# CONFIG_AUDIO_DEVICES is not set -# CONFIG_VIDEO_DEVICES is not set -# CONFIG_BCH is not set -# CONFIG_INPUT is not set -# CONFIG_LCD is not set -# CONFIG_MMCSD is not set -# CONFIG_MTD is not set -CONFIG_NETDEVICES=y - -# -# General Ethernet MAC Driver Options -# -# CONFIG_NETDEV_MULTINIC is not set -# CONFIG_NET_DUMPPACKET is not set - -# -# External Ethernet MAC Device Support -# -# CONFIG_NET_DM90x0 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set -# CONFIG_NET_SLIP is not set -CONFIG_NET_VNET=y -CONFIG_VNET_NINTERFACES=1 -# CONFIG_PIPES is not set -# CONFIG_PM is not set -# CONFIG_POWER is not set -# CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set -CONFIG_SERIAL=y -# CONFIG_DEV_LOWCONSOLE is not set -# CONFIG_16550_UART is not set -# CONFIG_UART_SERIALDRIVER is not set -# CONFIG_UART0_SERIALDRIVER is not set -# CONFIG_UART1_SERIALDRIVER is not set -# CONFIG_UART2_SERIALDRIVER is not set -# CONFIG_UART3_SERIALDRIVER is not set -# CONFIG_UART4_SERIALDRIVER is not set -# CONFIG_UART5_SERIALDRIVER is not set -# CONFIG_UART6_SERIALDRIVER is not set -# CONFIG_UART7_SERIALDRIVER is not set -# CONFIG_UART8_SERIALDRIVER is not set -# CONFIG_SCI0_SERIALDRIVER is not set -# CONFIG_SCI1_SERIALDRIVER is not set -# CONFIG_USART0_SERIALDRIVER is not set -# CONFIG_USART1_SERIALDRIVER is not set -# CONFIG_USART2_SERIALDRIVER is not set -# CONFIG_USART3_SERIALDRIVER is not set -# CONFIG_USART4_SERIALDRIVER is not set -# CONFIG_USART5_SERIALDRIVER is not set -# CONFIG_USART6_SERIALDRIVER is not set -# CONFIG_USART7_SERIALDRIVER is not set -# CONFIG_USART8_SERIALDRIVER is not set - -# -# USART Configuration -# -# CONFIG_MCU_SERIAL is not set -# CONFIG_STANDARD_SERIAL is not set -# CONFIG_SERIAL_IFLOWCONTROL is not set -# CONFIG_SERIAL_OFLOWCONTROL is not set -# CONFIG_USBDEV is not set -# CONFIG_USBHOST is not set -# CONFIG_DRIVERS_WIRELESS is not set - -# -# System Logging Device Options -# - -# -# System Logging -# -# CONFIG_RAMLOG is not set - -# -# Networking Support -# -CONFIG_ARCH_HAVE_NET=y -# CONFIG_ARCH_HAVE_PHY is not set -CONFIG_NET=y -# CONFIG_NET_NOINTS is not set -CONFIG_NET_IPv4=y -# CONFIG_NET_PROMISCUOUS is not set -CONFIG_NSOCKET_DESCRIPTORS=5 -CONFIG_NET_NACTIVESOCKETS=16 -CONFIG_NET_SOCKOPTS=y -# CONFIG_NET_SOLINGER is not set -CONFIG_NET_ETH_MTU=1514 -# CONFIG_NET_TCPURGDATA is not set - -# -# TCP/IP Networking -# -CONFIG_NET_TCP=y -CONFIG_NET_TCP_CONNS=40 -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_TCP_READAHEAD=y -# CONFIG_NET_TCP_WRITE_BUFFERS is not set -CONFIG_NET_TCP_RECVDELAY=0 -# CONFIG_NET_TCPBACKLOG is not set -# CONFIG_NET_TCP_SPLIT is not set -# CONFIG_NET_SENDFILE is not set - -# -# UDP Networking -# -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NET_UDP_CONNS=8 -CONFIG_NET_BROADCAST=y -# CONFIG_NET_RXAVAIL is not set -CONFIG_NET_ICMP=y -CONFIG_NET_ICMP_PING=y -# CONFIG_NET_IGMP is not set -CONFIG_NET_STATISTICS=y -CONFIG_NET_ETH_TCP_RECVWNDO=1460 -CONFIG_NET_ARPTAB_SIZE=8 -# CONFIG_NET_ARP_IPIN is not set -CONFIG_NET_IOB=y -CONFIG_IOB_NBUFFERS=24 -CONFIG_IOB_BUFSIZE=196 -CONFIG_IOB_NCHAINS=8 -CONFIG_IOB_THROTTLE=0 - -# -# Routing Table Configuration -# -# CONFIG_NET_ROUTE is not set -CONFIG_NET_ETHERNET=y - -# -# File Systems -# - -# -# File system configuration -# -# CONFIG_DISABLE_MOUNTPOINT is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_FS_READABLE is not set -# CONFIG_FS_WRITABLE is not set -# CONFIG_FS_RAMMAP is not set -# CONFIG_FS_FAT is not set -# CONFIG_NFS is not set -# CONFIG_FS_NXFFS is not set -# CONFIG_FS_ROMFS is not set -# CONFIG_FS_SMARTFS is not set -# CONFIG_FS_PROCFS is not set - -# -# System Logging -# - - -# -# Graphics Support -# -# CONFIG_NX is not set - -# -# Memory Management -# -# CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=1 -# CONFIG_ARCH_HAVE_HEAP2 is not set -# CONFIG_GRAN is not set - -# -# Audio Support -# -# CONFIG_AUDIO is not set - -# -# Binary Formats -# -# CONFIG_BINFMT_DISABLE is not set -# CONFIG_BINFMT_EXEPATH is not set -# CONFIG_NXFLAT is not set -# CONFIG_ELF is not set -# CONFIG_BUILTIN is not set -# CONFIG_PIC is not set -# CONFIG_SYMTAB_ORDEREDBYNAME is not set - -# -# Library Routines -# - -# -# Standard C Library Options -# -CONFIG_STDIO_BUFFER_SIZE=64 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=2 -CONFIG_LIB_HOMEDIR="/" -# CONFIG_NOPRINTF_FIELDWIDTH is not set -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LIBC_LONG_LONG=y -CONFIG_LIB_RAND_ORDER=1 -# CONFIG_EOL_IS_CR is not set -# CONFIG_EOL_IS_LF is not set -# CONFIG_EOL_IS_BOTH_CRLF is not set -CONFIG_EOL_IS_EITHER_CRLF=y -# CONFIG_LIBC_EXECFUNCS is not set -CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 -# CONFIG_LIBC_STRERROR is not set -# CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_ARCH_LOWPUTC=y -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set -CONFIG_ARCH_OPTIMIZED_FUNCTIONS=y -CONFIG_ARCH_MEMCPY=y -CONFIG_ARCH_MEMCMP=y -CONFIG_ARCH_MEMMOVE=y -CONFIG_ARCH_MEMSET=y -CONFIG_ARCH_STRCHR=y -CONFIG_ARCH_STRCMP=y -CONFIG_ARCH_STRCPY=y -CONFIG_ARCH_STRNCPY=y -CONFIG_ARCH_STRLEN=y -CONFIG_ARCH_STRNLEN=y -# CONFIG_ARCH_BZERO is not set - -# -# Non-standard Library Support -# -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_LIB_KBDCODEC is not set -# CONFIG_LIB_SLCDCODEC is not set - -# -# Basic CXX Support -# -# CONFIG_C99_BOOL8 is not set -# CONFIG_HAVE_CXX is not set - -# -# Application Configuration -# - -# -# Built-In Applications -# - -# -# Examples -# -# CONFIG_EXAMPLES_BUTTONS is not set -# CONFIG_EXAMPLES_CAN is not set -# CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_DHCPD is not set -# CONFIG_EXAMPLES_ELF is not set -# CONFIG_EXAMPLES_FTPC is not set -# CONFIG_EXAMPLES_FTPD is not set -# CONFIG_EXAMPLES_HELLO is not set -# CONFIG_EXAMPLES_HELLOXX is not set -# CONFIG_EXAMPLES_JSON is not set -# CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set -# CONFIG_EXAMPLES_IGMP is not set -# CONFIG_EXAMPLES_LCDRW is not set -# CONFIG_EXAMPLES_MM is not set -# CONFIG_EXAMPLES_MODBUS is not set -# CONFIG_EXAMPLES_MOUNT is not set -# CONFIG_EXAMPLES_NETTEST is not set -# CONFIG_EXAMPLES_NRF24L01TERM is not set -CONFIG_EXAMPLES_NSH=y -# CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXTERM is not set -# CONFIG_EXAMPLES_NXFFS is not set -# CONFIG_EXAMPLES_NXFLAT is not set -# CONFIG_EXAMPLES_NXHELLO is not set -# CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NXLINES is not set -# CONFIG_EXAMPLES_NXTEXT is not set -# CONFIG_EXAMPLES_OSTEST is not set -# CONFIG_EXAMPLES_PASHELLO is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set -# CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set -# CONFIG_EXAMPLES_ROMFS is not set -# CONFIG_EXAMPLES_SENDMAIL is not set -# CONFIG_EXAMPLES_SERLOOP is not set -# CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART is not set -# CONFIG_EXAMPLES_TCPECHO is not set -# CONFIG_EXAMPLES_TELNETD is not set -# CONFIG_EXAMPLES_THTTPD is not set -# CONFIG_EXAMPLES_TIFF is not set -# CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_UDP is not set -# CONFIG_EXAMPLES_DISCOVER is not set -# CONFIG_EXAMPLES_WEBSERVER is not set -# CONFIG_EXAMPLES_USBSERIAL is not set -# CONFIG_EXAMPLES_USBTERM is not set -# CONFIG_EXAMPLES_WATCHDOG is not set -# CONFIG_EXAMPLES_WGET is not set - -# -# Graphics Support -# -# CONFIG_TIFF is not set - -# -# Interpreters -# -# CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_PCODE is not set - -# -# Network Utilities -# - -# -# Networking Utilities -# -CONFIG_NETUTILS_CODECS=y -# CONFIG_CODECS_BASE64 is not set -# CONFIG_CODECS_HASH_MD5 is not set -# CONFIG_CODECS_URLCODE is not set -# CONFIG_CODECS_URLCODE_NEWMEMORY is not set -# CONFIG_CODECS_AVR_URLCODE is not set -CONFIG_NETUTILS_DHCPC=y -# CONFIG_NETUTILS_DHCPD is not set -# CONFIG_NETUTILS_FTPC is not set -# CONFIG_NETUTILS_FTPD is not set -# CONFIG_NETUTILS_JSON is not set -CONFIG_LIBC_NETDB=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSCLIENT_ENTRIES=4 -CONFIG_NETDB_DNSCLIENT_MAXRESPONSE=96 -# CONFIG_NETUTILS_SMTP is not set -# CONFIG_NETUTILS_TELNETD is not set -CONFIG_NETUTILS_TFTPC=y -# CONFIG_NETUTILS_THTTPD is not set -CONFIG_NETUTILS_NETLIB=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NSH_WGET_USERAGENT="NuttX/6.xx.x (; http://www.nuttx.org/)" -# CONFIG_NETUTILS_WEBSERVER is not set -# CONFIG_NETUTILS_DISCOVER is not set -# CONFIG_NETUTILS_XMLRPC is not set - -# -# FreeModBus -# -# CONFIG_MODBUS is not set - -# -# NSH Library -# -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -# CONFIG_NSH_CLE is not set - -# -# Disable Individual commands -# -# CONFIG_NSH_DISABLE_ADDROUTE is not set -# CONFIG_NSH_DISABLE_CAT is not set -# CONFIG_NSH_DISABLE_CD is not set -# CONFIG_NSH_DISABLE_CP is not set -# CONFIG_NSH_DISABLE_CMP is not set -# CONFIG_NSH_DISABLE_DD is not set -# CONFIG_NSH_DISABLE_DF is not set -# CONFIG_NSH_DISABLE_DELROUTE is not set -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HELP is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_KILL is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_MB is not set -# CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_MH is not set -# CONFIG_NSH_DISABLE_MOUNT is not set -# CONFIG_NSH_DISABLE_MW is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PING is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_PWD is not set -# CONFIG_NSH_DISABLE_RM is not set -# CONFIG_NSH_DISABLE_RMDIR is not set -# CONFIG_NSH_DISABLE_SET is not set -# CONFIG_NSH_DISABLE_SH is not set -# CONFIG_NSH_DISABLE_SLEEP is not set -# CONFIG_NSH_DISABLE_TEST is not set -# CONFIG_NSH_DISABLE_UMOUNT is not set -# CONFIG_NSH_DISABLE_UNSET is not set -# CONFIG_NSH_DISABLE_USLEEP is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set - -# -# Configure Command Options -# -CONFIG_NSH_CMDOPT_DF_H=y -CONFIG_NSH_CODECS_BUFSIZE=128 -CONFIG_NSH_CMDOPT_HEXDUMP=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_NSH_LINELEN=40 -# CONFIG_NSH_DISABLE_SEMICOLON is not set -CONFIG_NSH_CMDPARMS=y -CONFIG_NSH_TMPDIR="/tmp" -CONFIG_NSH_MAXARGUMENTS=6 -CONFIG_NSH_ARGCAT=y -CONFIG_NSH_NESTDEPTH=3 -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_ITEF is not set -# CONFIG_NSH_DISABLE_LOOPS is not set -# CONFIG_NSH_DISABLEBG is not set -CONFIG_NSH_CONSOLE=y - -# -# USB Trace Support -# -# CONFIG_NSH_ALTCONDEV is not set -# CONFIG_NSH_ARCHINIT is not set -# CONFIG_NSH_DHCPC is not set -CONFIG_NSH_IPADDR=0xc0a80a02 -CONFIG_NSH_DRIPADDR=0xc0a80a01 -CONFIG_NSH_NETMASK=0xffffff00 -# CONFIG_NSH_DNS is not set -# CONFIG_NSH_NOMAC is not set -CONFIG_NSH_MAX_ROUNDTRIP=20 - -# -# NxWidgets/NxWM -# - -# -# Platform-specific Support -# -# CONFIG_PLATFORM_CONFIGDATA is not set - -# -# System Libraries and NSH Add-Ons -# - -# -# USB CDC/ACM Device Commands -# - -# -# USB Composite Device Commands -# - -# -# Custom Free Memory Command -# -# CONFIG_SYSTEM_FREE is not set - -# -# I2C tool -# - -# -# INI File Parser -# -# CONFIG_FSUTILS_INIFILE is not set - -# -# FLASH Program Installation -# -# CONFIG_SYSTEM_INSTALL is not set - -# -# FLASH Erase-all Command -# - -# -# NxPlayer media player library / command Line -# -# CONFIG_SYSTEM_NXPLAYER is not set - -# -# RAM test -# -# CONFIG_SYSTEM_RAMTEST is not set - -# -# readline() -# -CONFIG_SYSTEM_READLINE=y -CONFIG_READLINE_ECHO=y - -# -# Power Off -# -# CONFIG_SYSTEM_POWEROFF is not set - -# -# RAMTRON -# - -# -# SD Card -# - -# -# Sysinfo -# - -# -# USB Monitor -# - -# -# EMACS-like Command Line Editor -# -# CONFIG_SYSTEM_CLE is not set - -# -# VI Work-Alike Editor -# -# CONFIG_SYSTEM_VI is not set - -# -# Stack Monitor -# - -# -# USB Mass Storage Device Commands -# - -# -# Zmodem Commands -# -# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/rgmp/x86/nsh/setenv.sh b/configs/rgmp/x86/nsh/setenv.sh deleted file mode 100755 index b2180473be..0000000000 --- a/configs/rgmp/x86/nsh/setenv.sh +++ /dev/null @@ -1,47 +0,0 @@ -#!/bin/bash -# config/rgmp/nsh/setenv.sh -# -# Copyright (C) 2011 Yu Qiang. All rights reserved. -# Copyright (C) 2011 Gregory Nutt. All rights reserved. -# Authors: Yu Qiang -# Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if [ "$(basename $0)" = "setenv.sh" ] ; then - echo "You must source this script, not run it!" 1>&2 - exit 1 -fi - -if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi - -#export NUTTX_BIN= -#export PATH=${NUTTX_BIN}:/sbin:/usr/sbin:${PATH_ORIG} - -echo "PATH : ${PATH}" diff --git a/configs/sabre-6quad/nsh/defconfig b/configs/sabre-6quad/nsh/defconfig index e49adfad3a..4c1cee390c 100644 --- a/configs/sabre-6quad/nsh/defconfig +++ b/configs/sabre-6quad/nsh/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -721,7 +720,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sabre-6quad/smp/defconfig b/configs/sabre-6quad/smp/defconfig index 1e0d04e2f1..22ca988805 100644 --- a/configs/sabre-6quad/smp/defconfig +++ b/configs/sabre-6quad/smp/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -728,7 +727,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sam3u-ek/knsh/defconfig b/configs/sam3u-ek/knsh/defconfig index a28be4c76b..2fec468447 100644 --- a/configs/sam3u-ek/knsh/defconfig +++ b/configs/sam3u-ek/knsh/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -752,7 +751,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sam3u-ek/nsh/defconfig b/configs/sam3u-ek/nsh/defconfig index 293d0a2ad1..a4b7df6d05 100644 --- a/configs/sam3u-ek/nsh/defconfig +++ b/configs/sam3u-ek/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -744,7 +743,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sam3u-ek/nx/defconfig b/configs/sam3u-ek/nx/defconfig index 138ef32e61..2b1876e763 100644 --- a/configs/sam3u-ek/nx/defconfig +++ b/configs/sam3u-ek/nx/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -863,7 +862,6 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sam3u-ek/nxwm/defconfig b/configs/sam3u-ek/nxwm/defconfig index 4aab0d81a2..aa075785cc 100644 --- a/configs/sam3u-ek/nxwm/defconfig +++ b/configs/sam3u-ek/nxwm/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -939,7 +938,6 @@ CONFIG_CXX_NEWLONG=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sam4e-ek/nsh/defconfig b/configs/sam4e-ek/nsh/defconfig index b2241a1f87..a2a5a4e5f8 100644 --- a/configs/sam4e-ek/nsh/defconfig +++ b/configs/sam4e-ek/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -620,10 +619,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1034,7 +1032,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sam4e-ek/nxwm/defconfig b/configs/sam4e-ek/nxwm/defconfig index 64423d1b6d..734743e820 100644 --- a/configs/sam4e-ek/nxwm/defconfig +++ b/configs/sam4e-ek/nxwm/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -679,10 +678,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1212,7 +1210,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sam4e-ek/usbnsh/defconfig b/configs/sam4e-ek/usbnsh/defconfig index 8b9b010f16..572206bc8b 100644 --- a/configs/sam4e-ek/usbnsh/defconfig +++ b/configs/sam4e-ek/usbnsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -620,10 +619,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1071,7 +1069,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sam4l-xplained/nsh/defconfig b/configs/sam4l-xplained/nsh/defconfig index ad60bc8a5f..def321022b 100644 --- a/configs/sam4l-xplained/nsh/defconfig +++ b/configs/sam4l-xplained/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -757,7 +756,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sam4s-xplained-pro/nsh/defconfig b/configs/sam4s-xplained-pro/nsh/defconfig index dd20b99e65..a19c4101dd 100644 --- a/configs/sam4s-xplained-pro/nsh/defconfig +++ b/configs/sam4s-xplained-pro/nsh/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -924,7 +923,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set CONFIG_EXAMPLES_SERIALBLASTER=y CONFIG_EXAMPLES_SERIALBLASTER_STACKSIZE=2048 diff --git a/configs/sam4s-xplained/nsh/defconfig b/configs/sam4s-xplained/nsh/defconfig index d997c7c352..b7ccf03ad3 100644 --- a/configs/sam4s-xplained/nsh/defconfig +++ b/configs/sam4s-xplained/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -731,7 +730,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sama5d2-xult/nsh/defconfig b/configs/sama5d2-xult/nsh/defconfig index 43d37d1d97..4d386604bb 100644 --- a/configs/sama5d2-xult/nsh/defconfig +++ b/configs/sama5d2-xult/nsh/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -904,7 +903,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RANDOM is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sama5d3-xplained/bridge/defconfig b/configs/sama5d3-xplained/bridge/defconfig index 4ece1c8211..a1a3f37492 100644 --- a/configs/sama5d3-xplained/bridge/defconfig +++ b/configs/sama5d3-xplained/bridge/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -593,10 +592,9 @@ CONFIG_NETDEV_MULTINIC=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1013,7 +1011,6 @@ CONFIG_EXAMPLES_BRIDGE_NET2_PRIORITY=100 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sama5d3-xplained/nsh/defconfig b/configs/sama5d3-xplained/nsh/defconfig index 8e7517c7c9..f527aefe04 100644 --- a/configs/sama5d3-xplained/nsh/defconfig +++ b/configs/sama5d3-xplained/nsh/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -780,7 +779,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sama5d3x-ek/demo/defconfig b/configs/sama5d3x-ek/demo/defconfig index e31ab7c068..5771045f3e 100644 --- a/configs/sama5d3x-ek/demo/defconfig +++ b/configs/sama5d3x-ek/demo/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -976,7 +975,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RANDOM is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sama5d3x-ek/hello/defconfig b/configs/sama5d3x-ek/hello/defconfig index e6685267cf..80ad780990 100644 --- a/configs/sama5d3x-ek/hello/defconfig +++ b/configs/sama5d3x-ek/hello/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -736,7 +735,6 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sama5d3x-ek/norboot/defconfig b/configs/sama5d3x-ek/norboot/defconfig index f2549c6802..349fff0a1a 100644 --- a/configs/sama5d3x-ek/norboot/defconfig +++ b/configs/sama5d3x-ek/norboot/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -750,7 +749,6 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sama5d3x-ek/nsh/defconfig b/configs/sama5d3x-ek/nsh/defconfig index 9ed0736276..8c5a5954ae 100644 --- a/configs/sama5d3x-ek/nsh/defconfig +++ b/configs/sama5d3x-ek/nsh/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -793,7 +792,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sama5d3x-ek/nx/defconfig b/configs/sama5d3x-ek/nx/defconfig index 80e7c9c1d5..bad74c5af8 100644 --- a/configs/sama5d3x-ek/nx/defconfig +++ b/configs/sama5d3x-ek/nx/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -930,7 +929,6 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sama5d3x-ek/nxplayer/defconfig b/configs/sama5d3x-ek/nxplayer/defconfig index 02ceea85b9..9ed8ac0465 100644 --- a/configs/sama5d3x-ek/nxplayer/defconfig +++ b/configs/sama5d3x-ek/nxplayer/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -925,7 +924,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sama5d3x-ek/nxwm/defconfig b/configs/sama5d3x-ek/nxwm/defconfig index 2dfe96aeff..2db993f648 100644 --- a/configs/sama5d3x-ek/nxwm/defconfig +++ b/configs/sama5d3x-ek/nxwm/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1018,7 +1017,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sama5d3x-ek/ov2640/defconfig b/configs/sama5d3x-ek/ov2640/defconfig index b0fa780678..61d48821a6 100644 --- a/configs/sama5d3x-ek/ov2640/defconfig +++ b/configs/sama5d3x-ek/ov2640/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -819,7 +818,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sama5d4-ek/at25boot/defconfig b/configs/sama5d4-ek/at25boot/defconfig index c42d478750..2d4c89081f 100644 --- a/configs/sama5d4-ek/at25boot/defconfig +++ b/configs/sama5d4-ek/at25boot/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -851,7 +850,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sama5d4-ek/bridge/defconfig b/configs/sama5d4-ek/bridge/defconfig index c71740cad7..8e650abaad 100644 --- a/configs/sama5d4-ek/bridge/defconfig +++ b/configs/sama5d4-ek/bridge/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -612,10 +611,9 @@ CONFIG_NETDEV_MULTINIC=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1046,7 +1044,6 @@ CONFIG_EXAMPLES_BRIDGE_NET2_PRIORITY=100 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sama5d4-ek/dramboot/defconfig b/configs/sama5d4-ek/dramboot/defconfig index 4b0fa6cebb..f0f68c6855 100644 --- a/configs/sama5d4-ek/dramboot/defconfig +++ b/configs/sama5d4-ek/dramboot/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -803,7 +802,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sama5d4-ek/elf/defconfig b/configs/sama5d4-ek/elf/defconfig index 09ac89d5c7..b55fc14606 100644 --- a/configs/sama5d4-ek/elf/defconfig +++ b/configs/sama5d4-ek/elf/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -852,7 +851,6 @@ CONFIG_EXAMPLES_ELF_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RANDOM is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/sama5d4-ek/ipv6/defconfig b/configs/sama5d4-ek/ipv6/defconfig index d6f8a5d621..2d2a202cc5 100644 --- a/configs/sama5d4-ek/ipv6/defconfig +++ b/configs/sama5d4-ek/ipv6/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -765,10 +764,9 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1345,7 +1343,6 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_EXAMPLES_RANDOM is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/sama5d4-ek/knsh/defconfig b/configs/sama5d4-ek/knsh/defconfig index e1acee79ec..372200adb0 100644 --- a/configs/sama5d4-ek/knsh/defconfig +++ b/configs/sama5d4-ek/knsh/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -903,7 +902,6 @@ CONFIG_EXAMPLES_NSH_PROGNAME="init" # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RANDOM is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sama5d4-ek/knsh/defconfig.ROMFS b/configs/sama5d4-ek/knsh/defconfig.ROMFS index 47724cd6dc..1e11783700 100644 --- a/configs/sama5d4-ek/knsh/defconfig.ROMFS +++ b/configs/sama5d4-ek/knsh/defconfig.ROMFS @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -742,7 +741,6 @@ CONFIG_EXAMPLES_NSH_PROGNAME="init" # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set # CONFIG_EXAMPLES_RANDOM is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/sama5d4-ek/nsh/defconfig b/configs/sama5d4-ek/nsh/defconfig index 9df9e8592b..9857438af8 100644 --- a/configs/sama5d4-ek/nsh/defconfig +++ b/configs/sama5d4-ek/nsh/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -767,10 +766,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1356,7 +1354,6 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_EXAMPLES_RANDOM is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/sama5d4-ek/nxwm/defconfig b/configs/sama5d4-ek/nxwm/defconfig index 5e27e7feee..56265b311b 100644 --- a/configs/sama5d4-ek/nxwm/defconfig +++ b/configs/sama5d4-ek/nxwm/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -736,10 +735,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1339,7 +1337,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_RANDOM is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/sama5d4-ek/ramtest/defconfig b/configs/sama5d4-ek/ramtest/defconfig index dd96d28c1f..8b7eb08c69 100644 --- a/configs/sama5d4-ek/ramtest/defconfig +++ b/configs/sama5d4-ek/ramtest/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -811,7 +810,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/samd20-xplained/nsh/defconfig b/configs/samd20-xplained/nsh/defconfig index 66cdfec157..973d39e7ec 100644 --- a/configs/samd20-xplained/nsh/defconfig +++ b/configs/samd20-xplained/nsh/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -733,7 +732,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/samd21-xplained/nsh/defconfig b/configs/samd21-xplained/nsh/defconfig index aff0c4e559..0428f7b746 100644 --- a/configs/samd21-xplained/nsh/defconfig +++ b/configs/samd21-xplained/nsh/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -731,7 +730,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/same70-xplained/netnsh/defconfig b/configs/same70-xplained/netnsh/defconfig index 535c3c9683..57c0c01323 100644 --- a/configs/same70-xplained/netnsh/defconfig +++ b/configs/same70-xplained/netnsh/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -666,10 +665,9 @@ CONFIG_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1076,7 +1074,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/same70-xplained/nsh/defconfig b/configs/same70-xplained/nsh/defconfig index d43cf6698c..58d1ce23c5 100644 --- a/configs/same70-xplained/nsh/defconfig +++ b/configs/same70-xplained/nsh/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -896,7 +895,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/saml21-xplained/nsh/defconfig b/configs/saml21-xplained/nsh/defconfig index 6fab4a5a01..2306bef6b9 100644 --- a/configs/saml21-xplained/nsh/defconfig +++ b/configs/saml21-xplained/nsh/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -719,7 +718,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/samv71-xult/knsh/defconfig b/configs/samv71-xult/knsh/defconfig index 7d66836b5a..6a9b6a2474 100644 --- a/configs/samv71-xult/knsh/defconfig +++ b/configs/samv71-xult/knsh/defconfig @@ -69,7 +69,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -890,7 +889,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/samv71-xult/module/defconfig b/configs/samv71-xult/module/defconfig index 98dd0cf6bf..ac536918bb 100644 --- a/configs/samv71-xult/module/defconfig +++ b/configs/samv71-xult/module/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -809,7 +808,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/samv71-xult/mxtxplnd/defconfig b/configs/samv71-xult/mxtxplnd/defconfig index 940bcd430c..43bb2b8cc9 100644 --- a/configs/samv71-xult/mxtxplnd/defconfig +++ b/configs/samv71-xult/mxtxplnd/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1034,7 +1033,6 @@ CONFIG_EXAMPLES_NXLINES_BPP=16 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/samv71-xult/netnsh/defconfig b/configs/samv71-xult/netnsh/defconfig index 6ccda62f81..24f50e8e68 100644 --- a/configs/samv71-xult/netnsh/defconfig +++ b/configs/samv71-xult/netnsh/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -669,10 +668,9 @@ CONFIG_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1080,7 +1078,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/samv71-xult/nsh/defconfig b/configs/samv71-xult/nsh/defconfig index c376395c8b..1e1c76f76b 100644 --- a/configs/samv71-xult/nsh/defconfig +++ b/configs/samv71-xult/nsh/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -899,7 +898,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/samv71-xult/nxwm/defconfig b/configs/samv71-xult/nxwm/defconfig index 3ba0d0986e..81c2f922a2 100644 --- a/configs/samv71-xult/nxwm/defconfig +++ b/configs/samv71-xult/nxwm/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1054,7 +1053,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/samv71-xult/vnc/defconfig b/configs/samv71-xult/vnc/defconfig index ff8aa31f6c..a37393cef6 100644 --- a/configs/samv71-xult/vnc/defconfig +++ b/configs/samv71-xult/vnc/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -670,10 +669,9 @@ CONFIG_NETDEV_STATISTICS=y # CONFIG_NET_CS89x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1183,7 +1181,6 @@ CONFIG_EXAMPLES_NXIMAGE_YSCALE1p0=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/samv71-xult/vnxwm/defconfig b/configs/samv71-xult/vnxwm/defconfig index 82e0de4d23..b3fa15e306 100644 --- a/configs/samv71-xult/vnxwm/defconfig +++ b/configs/samv71-xult/vnxwm/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -673,10 +672,9 @@ CONFIG_NETDEV_STATISTICS=y # CONFIG_NET_CS89x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1208,7 +1206,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/shenzhou/nsh/defconfig b/configs/shenzhou/nsh/defconfig index 9d0efc7d8a..5247928fbd 100644 --- a/configs/shenzhou/nsh/defconfig +++ b/configs/shenzhou/nsh/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -798,10 +797,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1204,7 +1202,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/shenzhou/nxwm/defconfig b/configs/shenzhou/nxwm/defconfig index a9dc024a02..31a95d3293 100644 --- a/configs/shenzhou/nxwm/defconfig +++ b/configs/shenzhou/nxwm/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -866,10 +865,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1368,7 +1366,6 @@ CONFIG_HAVE_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/shenzhou/thttpd/defconfig b/configs/shenzhou/thttpd/defconfig index 8df46c0006..4c2456192b 100644 --- a/configs/shenzhou/thttpd/defconfig +++ b/configs/shenzhou/thttpd/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -825,10 +824,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1237,7 +1235,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/sim/bas/defconfig b/configs/sim/bas/defconfig index ef4da76d6b..0b4597a317 100644 --- a/configs/sim/bas/defconfig +++ b/configs/sim/bas/defconfig @@ -56,7 +56,6 @@ CONFIG_DEBUG_NOOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set CONFIG_ARCH_SIM=y # CONFIG_ARCH_X86 is not set @@ -535,7 +534,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/sim/configdata/defconfig b/configs/sim/configdata/defconfig index ac5eeef6fe..6a58a5c9e9 100644 --- a/configs/sim/configdata/defconfig +++ b/configs/sim/configdata/defconfig @@ -58,7 +58,6 @@ CONFIG_DEBUG_NOOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set CONFIG_ARCH_SIM=y # CONFIG_ARCH_X86 is not set @@ -573,7 +572,6 @@ CONFIG_EXAMPLES_NXFFS_NLOOPS=100 # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sim/cxxtest/defconfig b/configs/sim/cxxtest/defconfig index 06d8f83aa6..7ecdc39504 100644 --- a/configs/sim/cxxtest/defconfig +++ b/configs/sim/cxxtest/defconfig @@ -58,7 +58,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set CONFIG_ARCH_SIM=y # CONFIG_ARCH_X86 is not set @@ -544,7 +543,6 @@ CONFIG_EXAMPLES_CXXTEST=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sim/minibasic/defconfig b/configs/sim/minibasic/defconfig index 0e1519ffc0..ee1b5d9817 100644 --- a/configs/sim/minibasic/defconfig +++ b/configs/sim/minibasic/defconfig @@ -84,7 +84,6 @@ CONFIG_DEBUG_NOOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set CONFIG_ARCH_SIM=y # CONFIG_ARCH_X86 is not set @@ -601,7 +600,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/sim/mount/defconfig b/configs/sim/mount/defconfig index a205f783f5..14234058c0 100644 --- a/configs/sim/mount/defconfig +++ b/configs/sim/mount/defconfig @@ -58,7 +58,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set CONFIG_ARCH_SIM=y # CONFIG_ARCH_X86 is not set @@ -543,7 +542,6 @@ CONFIG_EXAMPLES_MOUNT_DEVNAME="/dev/ram0" # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sim/mtdpart/defconfig b/configs/sim/mtdpart/defconfig index 04568d5ca1..a9e8cb82f9 100644 --- a/configs/sim/mtdpart/defconfig +++ b/configs/sim/mtdpart/defconfig @@ -58,7 +58,6 @@ CONFIG_DEBUG_NOOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set CONFIG_ARCH_SIM=y # CONFIG_ARCH_X86 is not set @@ -555,7 +554,6 @@ CONFIG_EXAMPLES_MTDPART_NPARTITIONS=3 # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sim/mtdrwb/defconfig b/configs/sim/mtdrwb/defconfig index c14345962e..4a24af5075 100644 --- a/configs/sim/mtdrwb/defconfig +++ b/configs/sim/mtdrwb/defconfig @@ -58,7 +58,6 @@ CONFIG_DEBUG_NOOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set CONFIG_ARCH_SIM=y # CONFIG_ARCH_X86 is not set @@ -588,7 +587,6 @@ CONFIG_EXAMPLES_MTDRWB_NEBLOCKS=32 # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sim/nettest/defconfig b/configs/sim/nettest/defconfig index ccab175375..aebf077586 100644 --- a/configs/sim/nettest/defconfig +++ b/configs/sim/nettest/defconfig @@ -59,7 +59,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set CONFIG_ARCH_SIM=y @@ -673,7 +672,6 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0xc0a8006a # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sim/nsh/defconfig b/configs/sim/nsh/defconfig index 47c57eb4df..b44d379379 100644 --- a/configs/sim/nsh/defconfig +++ b/configs/sim/nsh/defconfig @@ -59,7 +59,6 @@ CONFIG_DEBUG_NOOPT=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set CONFIG_ARCH_SIM=y @@ -587,7 +586,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/sim/nsh2/defconfig b/configs/sim/nsh2/defconfig index 2c022f2917..918e40e594 100644 --- a/configs/sim/nsh2/defconfig +++ b/configs/sim/nsh2/defconfig @@ -59,7 +59,6 @@ CONFIG_DEBUG_NOOPT=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set CONFIG_ARCH_SIM=y @@ -714,7 +713,6 @@ CONFIG_EXAMPLES_NXLINES_BPP=32 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/sim/nx/defconfig b/configs/sim/nx/defconfig index 5474eade27..b205eadbdc 100644 --- a/configs/sim/nx/defconfig +++ b/configs/sim/nx/defconfig @@ -59,7 +59,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set CONFIG_ARCH_SIM=y @@ -631,7 +630,6 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sim/nx11/defconfig b/configs/sim/nx11/defconfig index 491fb3c438..d845ca9349 100644 --- a/configs/sim/nx11/defconfig +++ b/configs/sim/nx11/defconfig @@ -59,7 +59,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set CONFIG_ARCH_SIM=y @@ -633,7 +632,6 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sim/nxffs/defconfig b/configs/sim/nxffs/defconfig index 97f2b992ae..fb1252ac6e 100644 --- a/configs/sim/nxffs/defconfig +++ b/configs/sim/nxffs/defconfig @@ -56,7 +56,6 @@ CONFIG_DEBUG_NOOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set CONFIG_ARCH_SIM=y # CONFIG_ARCH_X86 is not set @@ -528,7 +527,6 @@ CONFIG_EXAMPLES_NXFFS_NLOOPS=100 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sim/nxlines/defconfig b/configs/sim/nxlines/defconfig index 70431cb06d..f1a973024d 100644 --- a/configs/sim/nxlines/defconfig +++ b/configs/sim/nxlines/defconfig @@ -60,7 +60,6 @@ CONFIG_DEBUG_NOOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set CONFIG_ARCH_SIM=y # CONFIG_ARCH_X86 is not set @@ -640,7 +639,6 @@ CONFIG_EXAMPLES_NXLINES_BPP=32 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/sim/nxwm/defconfig b/configs/sim/nxwm/defconfig index 6fb3f9b5ea..1b69d53d19 100644 --- a/configs/sim/nxwm/defconfig +++ b/configs/sim/nxwm/defconfig @@ -59,7 +59,6 @@ CONFIG_DEBUG_NOOPT=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set CONFIG_ARCH_SIM=y @@ -702,7 +701,6 @@ CONFIG_HAVE_CXX=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/sim/ostest/defconfig b/configs/sim/ostest/defconfig index 182af156ed..089a488da3 100644 --- a/configs/sim/ostest/defconfig +++ b/configs/sim/ostest/defconfig @@ -59,7 +59,6 @@ CONFIG_DEBUG_NOOPT=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set CONFIG_ARCH_SIM=y @@ -554,7 +553,6 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sim/pashello/defconfig b/configs/sim/pashello/defconfig index 8ffba0da35..ad3b274ceb 100644 --- a/configs/sim/pashello/defconfig +++ b/configs/sim/pashello/defconfig @@ -56,7 +56,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set CONFIG_ARCH_SIM=y # CONFIG_ARCH_X86 is not set @@ -508,7 +507,6 @@ CONFIG_EXAMPLES_PASHELLO_STRSTACKSIZE=128 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sim/touchscreen/defconfig b/configs/sim/touchscreen/defconfig index 5795b1c649..f290b2d544 100644 --- a/configs/sim/touchscreen/defconfig +++ b/configs/sim/touchscreen/defconfig @@ -58,7 +58,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set CONFIG_ARCH_SIM=y # CONFIG_ARCH_X86 is not set @@ -633,7 +632,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sim/traveler/defconfig b/configs/sim/traveler/defconfig index 270cde215a..14f3aa4719 100644 --- a/configs/sim/traveler/defconfig +++ b/configs/sim/traveler/defconfig @@ -59,7 +59,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set CONFIG_ARCH_SIM=y @@ -564,7 +563,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/sim/udgram/defconfig b/configs/sim/udgram/defconfig index 567b3165e2..ae87965d95 100644 --- a/configs/sim/udgram/defconfig +++ b/configs/sim/udgram/defconfig @@ -59,7 +59,6 @@ CONFIG_DEBUG_NOOPT=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set CONFIG_ARCH_SIM=y @@ -673,7 +672,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/sim/unionfs/defconfig b/configs/sim/unionfs/defconfig index 1ccf413c95..8babf143da 100644 --- a/configs/sim/unionfs/defconfig +++ b/configs/sim/unionfs/defconfig @@ -56,7 +56,6 @@ CONFIG_DEBUG_NOOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set CONFIG_ARCH_SIM=y # CONFIG_ARCH_X86 is not set @@ -534,7 +533,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/sim/ustream/defconfig b/configs/sim/ustream/defconfig index ed8cdd5ea2..fabbc20ff1 100644 --- a/configs/sim/ustream/defconfig +++ b/configs/sim/ustream/defconfig @@ -59,7 +59,6 @@ CONFIG_DEBUG_NOOPT=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set CONFIG_ARCH_SIM=y @@ -673,7 +672,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/skp16c26/ostest/defconfig b/configs/skp16c26/ostest/defconfig index 0efb93d2a2..b46a95b90d 100644 --- a/configs/skp16c26/ostest/defconfig +++ b/configs/skp16c26/ostest/defconfig @@ -53,7 +53,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set CONFIG_ARCH_RENESAS=y # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -424,7 +423,6 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERLOOP is not set diff --git a/configs/spark/composite/defconfig b/configs/spark/composite/defconfig index 490744f429..9c1a90f84f 100644 --- a/configs/spark/composite/defconfig +++ b/configs/spark/composite/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1121,7 +1120,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/spark/nsh/defconfig b/configs/spark/nsh/defconfig index a32b364ed2..09613a10f3 100644 --- a/configs/spark/nsh/defconfig +++ b/configs/spark/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1121,7 +1120,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/spark/usbmsc/defconfig b/configs/spark/usbmsc/defconfig index 9ac901f2a1..4c25d981cc 100644 --- a/configs/spark/usbmsc/defconfig +++ b/configs/spark/usbmsc/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1086,7 +1085,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/spark/usbnsh/defconfig b/configs/spark/usbnsh/defconfig index 328bf6670d..f92f017f03 100644 --- a/configs/spark/usbnsh/defconfig +++ b/configs/spark/usbnsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1065,7 +1064,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/spark/usbserial/defconfig b/configs/spark/usbserial/defconfig index da3d0c5e5d..a11551266f 100644 --- a/configs/spark/usbserial/defconfig +++ b/configs/spark/usbserial/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1096,7 +1095,6 @@ CONFIG_EXAMPLES_CC3000BASIC=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3210e-eval/composite/defconfig b/configs/stm3210e-eval/composite/defconfig index a1a7799488..16c1a20419 100644 --- a/configs/stm3210e-eval/composite/defconfig +++ b/configs/stm3210e-eval/composite/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1128,7 +1127,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3210e-eval/nsh/defconfig b/configs/stm3210e-eval/nsh/defconfig index b8896ddace..e8d1d71f2c 100644 --- a/configs/stm3210e-eval/nsh/defconfig +++ b/configs/stm3210e-eval/nsh/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1085,7 +1084,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3210e-eval/nsh2/defconfig b/configs/stm3210e-eval/nsh2/defconfig index 741db60bb0..0c67ce8603 100644 --- a/configs/stm3210e-eval/nsh2/defconfig +++ b/configs/stm3210e-eval/nsh2/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1281,7 +1280,6 @@ CONFIG_EXAMPLES_NXHELLO_FONTID=6 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3210e-eval/nx/defconfig b/configs/stm3210e-eval/nx/defconfig index f124e0132a..39ddbeda89 100644 --- a/configs/stm3210e-eval/nx/defconfig +++ b/configs/stm3210e-eval/nx/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1157,7 +1156,6 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3210e-eval/nxterm/defconfig b/configs/stm3210e-eval/nxterm/defconfig index 41cd0202db..7470e437ef 100644 --- a/configs/stm3210e-eval/nxterm/defconfig +++ b/configs/stm3210e-eval/nxterm/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1159,7 +1158,6 @@ CONFIG_EXAMPLES_NXTERM=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3210e-eval/pm/defconfig b/configs/stm3210e-eval/pm/defconfig index 94684ad13d..e1e7fae9f4 100644 --- a/configs/stm3210e-eval/pm/defconfig +++ b/configs/stm3210e-eval/pm/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1208,7 +1207,6 @@ CONFIG_EXAMPLES_NXHELLO_FONTID=6 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3210e-eval/usbmsc/defconfig b/configs/stm3210e-eval/usbmsc/defconfig index 9cea76f73f..e02a938d76 100644 --- a/configs/stm3210e-eval/usbmsc/defconfig +++ b/configs/stm3210e-eval/usbmsc/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1055,7 +1054,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3210e-eval/usbserial/defconfig b/configs/stm3210e-eval/usbserial/defconfig index 20c1fba098..195770cac3 100644 --- a/configs/stm3210e-eval/usbserial/defconfig +++ b/configs/stm3210e-eval/usbserial/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1019,7 +1018,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3220g-eval/dhcpd/defconfig b/configs/stm3220g-eval/dhcpd/defconfig index 50faf0a0c0..ec11cf50fd 100644 --- a/configs/stm3220g-eval/dhcpd/defconfig +++ b/configs/stm3220g-eval/dhcpd/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -770,10 +769,9 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1134,7 +1132,6 @@ CONFIG_EXAMPLES_DHCPD_NETMASK=0xffffff00 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3220g-eval/nettest/defconfig b/configs/stm3220g-eval/nettest/defconfig index e97e8b01d3..7867ba3f49 100644 --- a/configs/stm3220g-eval/nettest/defconfig +++ b/configs/stm3220g-eval/nettest/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -771,10 +770,9 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1147,7 +1145,6 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3220g-eval/nsh/defconfig b/configs/stm3220g-eval/nsh/defconfig index 2b16a40723..7075a4c735 100644 --- a/configs/stm3220g-eval/nsh/defconfig +++ b/configs/stm3220g-eval/nsh/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -837,10 +836,9 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1245,7 +1243,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3220g-eval/nsh2/defconfig b/configs/stm3220g-eval/nsh2/defconfig index ab552f7ae1..1ed45de59e 100644 --- a/configs/stm3220g-eval/nsh2/defconfig +++ b/configs/stm3220g-eval/nsh2/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -851,10 +850,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1245,7 +1243,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3220g-eval/nxwm/defconfig b/configs/stm3220g-eval/nxwm/defconfig index f7cd83b4c5..226185ff1a 100644 --- a/configs/stm3220g-eval/nxwm/defconfig +++ b/configs/stm3220g-eval/nxwm/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -887,10 +886,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1394,7 +1392,6 @@ CONFIG_HAVE_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3220g-eval/telnetd/defconfig b/configs/stm3220g-eval/telnetd/defconfig index 5875d4530b..3b2691aac1 100644 --- a/configs/stm3220g-eval/telnetd/defconfig +++ b/configs/stm3220g-eval/telnetd/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -773,10 +772,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1136,7 +1134,6 @@ CONFIG_HAVE_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3240g-eval/dhcpd/defconfig b/configs/stm3240g-eval/dhcpd/defconfig index 754c19b28b..eb100332f9 100644 --- a/configs/stm3240g-eval/dhcpd/defconfig +++ b/configs/stm3240g-eval/dhcpd/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -774,10 +773,9 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1138,7 +1136,6 @@ CONFIG_EXAMPLES_DHCPD_NETMASK=0xffffff00 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3240g-eval/discover/defconfig b/configs/stm3240g-eval/discover/defconfig index 9690dcd899..df9f2b18ee 100644 --- a/configs/stm3240g-eval/discover/defconfig +++ b/configs/stm3240g-eval/discover/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -797,10 +796,9 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1202,7 +1200,6 @@ CONFIG_EXAMPLES_DISCOVER_NETMASK=0xffffff00 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3240g-eval/knxwm/defconfig b/configs/stm3240g-eval/knxwm/defconfig index 1f72f2fdaa..550117b4bc 100644 --- a/configs/stm3240g-eval/knxwm/defconfig +++ b/configs/stm3240g-eval/knxwm/defconfig @@ -71,7 +71,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1217,7 +1216,6 @@ CONFIG_CXX_NEWLONG=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3240g-eval/nettest/defconfig b/configs/stm3240g-eval/nettest/defconfig index 17b71623d7..9f24daa36f 100644 --- a/configs/stm3240g-eval/nettest/defconfig +++ b/configs/stm3240g-eval/nettest/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -775,10 +774,9 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1151,7 +1149,6 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3240g-eval/nsh/defconfig b/configs/stm3240g-eval/nsh/defconfig index 3c3ea36359..1ced4eac01 100644 --- a/configs/stm3240g-eval/nsh/defconfig +++ b/configs/stm3240g-eval/nsh/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -815,10 +814,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1223,7 +1221,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_RANDOM is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3240g-eval/nsh2/defconfig b/configs/stm3240g-eval/nsh2/defconfig index eee3754ec5..446ecdaba8 100644 --- a/configs/stm3240g-eval/nsh2/defconfig +++ b/configs/stm3240g-eval/nsh2/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -855,10 +854,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1249,7 +1247,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3240g-eval/nxterm/defconfig b/configs/stm3240g-eval/nxterm/defconfig index afec78eb97..7d5aa49b05 100644 --- a/configs/stm3240g-eval/nxterm/defconfig +++ b/configs/stm3240g-eval/nxterm/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -856,10 +855,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1366,7 +1364,6 @@ CONFIG_EXAMPLES_NXTERM=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3240g-eval/nxwm/defconfig b/configs/stm3240g-eval/nxwm/defconfig index 42d4860e54..ab92f2b9c3 100644 --- a/configs/stm3240g-eval/nxwm/defconfig +++ b/configs/stm3240g-eval/nxwm/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -884,10 +883,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1398,7 +1396,6 @@ CONFIG_HAVE_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3240g-eval/telnetd/defconfig b/configs/stm3240g-eval/telnetd/defconfig index 0fda97b4ad..6882cd6d06 100644 --- a/configs/stm3240g-eval/telnetd/defconfig +++ b/configs/stm3240g-eval/telnetd/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -777,10 +776,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1140,7 +1138,6 @@ CONFIG_HAVE_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3240g-eval/webserver/defconfig b/configs/stm3240g-eval/webserver/defconfig index 4c8e72621a..076059622c 100644 --- a/configs/stm3240g-eval/webserver/defconfig +++ b/configs/stm3240g-eval/webserver/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -836,10 +835,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1242,7 +1240,6 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0x0a000001 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm3240g-eval/xmlrpc/defconfig b/configs/stm3240g-eval/xmlrpc/defconfig index 43dfd2fbf0..8a45ee1945 100644 --- a/configs/stm3240g-eval/xmlrpc/defconfig +++ b/configs/stm3240g-eval/xmlrpc/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -792,10 +791,9 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1194,7 +1192,6 @@ CONFIG_HAVE_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32_tiny/nsh/defconfig b/configs/stm32_tiny/nsh/defconfig index 8b9c4c1d86..98ebea74e1 100644 --- a/configs/stm32_tiny/nsh/defconfig +++ b/configs/stm32_tiny/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -978,7 +977,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32_tiny/usbnsh/defconfig b/configs/stm32_tiny/usbnsh/defconfig index 03de8a4dd1..d680f70dad 100644 --- a/configs/stm32_tiny/usbnsh/defconfig +++ b/configs/stm32_tiny/usbnsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -987,7 +986,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32butterfly2/nsh/defconfig b/configs/stm32butterfly2/nsh/defconfig index 08a3f805de..96c060fd14 100644 --- a/configs/stm32butterfly2/nsh/defconfig +++ b/configs/stm32butterfly2/nsh/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1073,7 +1072,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32butterfly2/nshnet/defconfig b/configs/stm32butterfly2/nshnet/defconfig index 950212cb7b..05b2ab9f0a 100644 --- a/configs/stm32butterfly2/nshnet/defconfig +++ b/configs/stm32butterfly2/nshnet/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -802,10 +801,9 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1253,7 +1251,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32butterfly2/nshusbdev/defconfig b/configs/stm32butterfly2/nshusbdev/defconfig index 63dc8d5a1d..83565df6ad 100644 --- a/configs/stm32butterfly2/nshusbdev/defconfig +++ b/configs/stm32butterfly2/nshusbdev/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1079,7 +1078,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32butterfly2/nshusbhost/defconfig b/configs/stm32butterfly2/nshusbhost/defconfig index 08a3f805de..96c060fd14 100644 --- a/configs/stm32butterfly2/nshusbhost/defconfig +++ b/configs/stm32butterfly2/nshusbhost/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1073,7 +1072,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f103-minimum/audio_tone/defconfig b/configs/stm32f103-minimum/audio_tone/defconfig index 4089a1842e..06ec48e05e 100644 --- a/configs/stm32f103-minimum/audio_tone/defconfig +++ b/configs/stm32f103-minimum/audio_tone/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1004,7 +1003,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PWM is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f103-minimum/buttons/defconfig b/configs/stm32f103-minimum/buttons/defconfig index 37ad971e05..a1ec7a28f0 100644 --- a/configs/stm32f103-minimum/buttons/defconfig +++ b/configs/stm32f103-minimum/buttons/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -974,7 +973,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f103-minimum/jlx12864g/defconfig b/configs/stm32f103-minimum/jlx12864g/defconfig index b74c761968..fb4a24692c 100644 --- a/configs/stm32f103-minimum/jlx12864g/defconfig +++ b/configs/stm32f103-minimum/jlx12864g/defconfig @@ -97,7 +97,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1194,7 +1193,6 @@ CONFIG_EXAMPLES_NXTEXT_DEFAULT_FONT=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f103-minimum/minnsh/defconfig b/configs/stm32f103-minimum/minnsh/defconfig index 06b686c04e..a150431a15 100644 --- a/configs/stm32f103-minimum/minnsh/defconfig +++ b/configs/stm32f103-minimum/minnsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -901,7 +900,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f103-minimum/nsh/defconfig b/configs/stm32f103-minimum/nsh/defconfig index db105a7a7b..91deca78db 100644 --- a/configs/stm32f103-minimum/nsh/defconfig +++ b/configs/stm32f103-minimum/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -950,7 +949,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f103-minimum/pwm/defconfig b/configs/stm32f103-minimum/pwm/defconfig index 27fa9d85b2..a597b31441 100644 --- a/configs/stm32f103-minimum/pwm/defconfig +++ b/configs/stm32f103-minimum/pwm/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -973,7 +972,6 @@ CONFIG_EXAMPLES_PWM_DURATION=5 CONFIG_EXAMPLES_PWM_DUTYPCT=50 # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f103-minimum/rfid-rc522/defconfig b/configs/stm32f103-minimum/rfid-rc522/defconfig index 0f41c12085..05a4cdb162 100644 --- a/configs/stm32f103-minimum/rfid-rc522/defconfig +++ b/configs/stm32f103-minimum/rfid-rc522/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -977,7 +976,6 @@ CONFIG_EXAMPLES_RFID_READUID=y CONFIG_EXAMPLES_RFID_READUID_PRIORITY=100 CONFIG_EXAMPLES_RFID_READUID_STACKSIZE=2048 # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f103-minimum/rgbled/defconfig b/configs/stm32f103-minimum/rgbled/defconfig index e058bd2e53..18f181819b 100644 --- a/configs/stm32f103-minimum/rgbled/defconfig +++ b/configs/stm32f103-minimum/rgbled/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -999,7 +998,6 @@ CONFIG_EXAMPLES_RGBLED=y CONFIG_EXAMPLES_RGBLED_DEVNAME="/dev/rgbled0" CONFIG_EXAMPLES_RGBLED_PRIORITY=100 CONFIG_EXAMPLES_RGBLED_STACKSIZE=2048 -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f103-minimum/usbnsh/defconfig b/configs/stm32f103-minimum/usbnsh/defconfig index e09d96e46e..411f621829 100644 --- a/configs/stm32f103-minimum/usbnsh/defconfig +++ b/configs/stm32f103-minimum/usbnsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -987,7 +986,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f103-minimum/userled/defconfig b/configs/stm32f103-minimum/userled/defconfig index 9cdfdc6380..5259eae061 100644 --- a/configs/stm32f103-minimum/userled/defconfig +++ b/configs/stm32f103-minimum/userled/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -959,7 +958,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f103-minimum/veml6070/defconfig b/configs/stm32f103-minimum/veml6070/defconfig index fa44438359..ff8f7eaafa 100644 --- a/configs/stm32f103-minimum/veml6070/defconfig +++ b/configs/stm32f103-minimum/veml6070/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1015,7 +1014,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f3discovery/nsh/defconfig b/configs/stm32f3discovery/nsh/defconfig index b1a68d9201..affc37c5ac 100644 --- a/configs/stm32f3discovery/nsh/defconfig +++ b/configs/stm32f3discovery/nsh/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1018,7 +1017,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f3discovery/usbnsh/defconfig b/configs/stm32f3discovery/usbnsh/defconfig index 69d103b1d7..3d3cdeb635 100644 --- a/configs/stm32f3discovery/usbnsh/defconfig +++ b/configs/stm32f3discovery/usbnsh/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1036,7 +1035,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f411e-disco/nsh/defconfig b/configs/stm32f411e-disco/nsh/defconfig index c48678fdab..fd0aea5e52 100644 --- a/configs/stm32f411e-disco/nsh/defconfig +++ b/configs/stm32f411e-disco/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -956,7 +955,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f429i-disco/extflash/defconfig b/configs/stm32f429i-disco/extflash/defconfig index de6d4ae581..f16f70e8f0 100644 --- a/configs/stm32f429i-disco/extflash/defconfig +++ b/configs/stm32f429i-disco/extflash/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1101,7 +1100,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_RANDOM is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f429i-disco/lcd/defconfig b/configs/stm32f429i-disco/lcd/defconfig index d7443e529c..3a44a86cf0 100644 --- a/configs/stm32f429i-disco/lcd/defconfig +++ b/configs/stm32f429i-disco/lcd/defconfig @@ -63,7 +63,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1175,7 +1174,6 @@ CONFIG_EXAMPLES_NX_NOTIFYSIGNO=4 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f429i-disco/ltdc/defconfig b/configs/stm32f429i-disco/ltdc/defconfig index 816844d39c..1c0ccce8c7 100644 --- a/configs/stm32f429i-disco/ltdc/defconfig +++ b/configs/stm32f429i-disco/ltdc/defconfig @@ -63,7 +63,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1181,7 +1180,6 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f429i-disco/nsh/defconfig b/configs/stm32f429i-disco/nsh/defconfig index e170337cae..b201f021ab 100644 --- a/configs/stm32f429i-disco/nsh/defconfig +++ b/configs/stm32f429i-disco/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1006,7 +1005,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f429i-disco/usbmsc/defconfig b/configs/stm32f429i-disco/usbmsc/defconfig index 00cdfd5236..f1b47adf0f 100644 --- a/configs/stm32f429i-disco/usbmsc/defconfig +++ b/configs/stm32f429i-disco/usbmsc/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1047,7 +1046,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f429i-disco/usbnsh/defconfig b/configs/stm32f429i-disco/usbnsh/defconfig index f350e42aaf..bcc99f3740 100644 --- a/configs/stm32f429i-disco/usbnsh/defconfig +++ b/configs/stm32f429i-disco/usbnsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1063,7 +1062,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f4discovery/canard/defconfig b/configs/stm32f4discovery/canard/defconfig index 327fc9c818..cede8f725a 100644 --- a/configs/stm32f4discovery/canard/defconfig +++ b/configs/stm32f4discovery/canard/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1051,7 +1050,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f4discovery/cxxtest/defconfig b/configs/stm32f4discovery/cxxtest/defconfig index 55b87040f9..17aee26004 100644 --- a/configs/stm32f4discovery/cxxtest/defconfig +++ b/configs/stm32f4discovery/cxxtest/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -982,7 +981,6 @@ CONFIG_EXAMPLES_CXXTEST_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f4discovery/elf/defconfig b/configs/stm32f4discovery/elf/defconfig index a072d09e95..267a0eb4c9 100644 --- a/configs/stm32f4discovery/elf/defconfig +++ b/configs/stm32f4discovery/elf/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -996,7 +995,6 @@ CONFIG_EXAMPLES_ELF_DEVPATH="/dev/ram0" # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/stm32f4discovery/ipv6/defconfig b/configs/stm32f4discovery/ipv6/defconfig index fb6ce75801..be3b59a928 100644 --- a/configs/stm32f4discovery/ipv6/defconfig +++ b/configs/stm32f4discovery/ipv6/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -844,10 +843,9 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1254,7 +1252,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f4discovery/kostest/defconfig b/configs/stm32f4discovery/kostest/defconfig index c5cdb7b619..f60c51af13 100644 --- a/configs/stm32f4discovery/kostest/defconfig +++ b/configs/stm32f4discovery/kostest/defconfig @@ -70,7 +70,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -983,7 +982,6 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f4discovery/netnsh/defconfig b/configs/stm32f4discovery/netnsh/defconfig index 30eb7b69cf..ff2ce11f27 100644 --- a/configs/stm32f4discovery/netnsh/defconfig +++ b/configs/stm32f4discovery/netnsh/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -846,10 +845,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1265,7 +1263,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f4discovery/nsh/defconfig b/configs/stm32f4discovery/nsh/defconfig index e5efd97735..8fde6da232 100644 --- a/configs/stm32f4discovery/nsh/defconfig +++ b/configs/stm32f4discovery/nsh/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1022,7 +1021,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f4discovery/nxlines/defconfig b/configs/stm32f4discovery/nxlines/defconfig index 91cc0a7bfe..4dc4b3990d 100644 --- a/configs/stm32f4discovery/nxlines/defconfig +++ b/configs/stm32f4discovery/nxlines/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1150,7 +1149,6 @@ CONFIG_EXAMPLES_NXLINES_BPP=16 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f4discovery/pm/defconfig b/configs/stm32f4discovery/pm/defconfig index f4e95b0c07..b3d5cf6b47 100644 --- a/configs/stm32f4discovery/pm/defconfig +++ b/configs/stm32f4discovery/pm/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1044,7 +1043,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f4discovery/posix_spawn/defconfig b/configs/stm32f4discovery/posix_spawn/defconfig index bde4e1647c..8ec76f3264 100644 --- a/configs/stm32f4discovery/posix_spawn/defconfig +++ b/configs/stm32f4discovery/posix_spawn/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -998,7 +997,6 @@ CONFIG_EXAMPLES_POSIXSPAWN_DEVPATH="/dev/ram0" # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/stm32f4discovery/pseudoterm/defconfig b/configs/stm32f4discovery/pseudoterm/defconfig index c129eb8c72..bfbce2da4b 100644 --- a/configs/stm32f4discovery/pseudoterm/defconfig +++ b/configs/stm32f4discovery/pseudoterm/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1050,7 +1049,6 @@ CONFIG_EXAMPLES_PTYTEST_STACKSIZE=2048 CONFIG_EXAMPLES_PTYTEST_DAEMONPRIO=100 # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f4discovery/rgbled/defconfig b/configs/stm32f4discovery/rgbled/defconfig index 166d2fd1d3..8aadf0ef48 100644 --- a/configs/stm32f4discovery/rgbled/defconfig +++ b/configs/stm32f4discovery/rgbled/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1032,7 +1031,6 @@ CONFIG_EXAMPLES_RGBLED=y CONFIG_EXAMPLES_RGBLED_DEVNAME="/dev/rgbled0" CONFIG_EXAMPLES_RGBLED_PRIORITY=100 CONFIG_EXAMPLES_RGBLED_STACKSIZE=2048 -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f4discovery/uavcan/defconfig b/configs/stm32f4discovery/uavcan/defconfig index d383024729..e1c6805af2 100644 --- a/configs/stm32f4discovery/uavcan/defconfig +++ b/configs/stm32f4discovery/uavcan/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -944,7 +943,6 @@ CONFIG_LIBUAVCAN_INIT_RETRIES=0 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f4discovery/usbnsh/defconfig b/configs/stm32f4discovery/usbnsh/defconfig index ee7402e4b7..ca4f90464b 100644 --- a/configs/stm32f4discovery/usbnsh/defconfig +++ b/configs/stm32f4discovery/usbnsh/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1070,7 +1069,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f4discovery/winbuild/defconfig b/configs/stm32f4discovery/winbuild/defconfig index 7de0aa1296..579f659c5f 100644 --- a/configs/stm32f4discovery/winbuild/defconfig +++ b/configs/stm32f4discovery/winbuild/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -871,7 +870,6 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f4discovery/xen1210/defconfig b/configs/stm32f4discovery/xen1210/defconfig index 2e99c29ed8..cd07105569 100644 --- a/configs/stm32f4discovery/xen1210/defconfig +++ b/configs/stm32f4discovery/xen1210/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -1060,7 +1059,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig index 4ba7dddad4..e245af1cc1 100644 --- a/configs/stm32f746-ws/nsh/defconfig +++ b/configs/stm32f746-ws/nsh/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -1004,7 +1003,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32f746g-disco/nsh/defconfig b/configs/stm32f746g-disco/nsh/defconfig index 330360fdc1..2fbb7948a8 100644 --- a/configs/stm32f746g-disco/nsh/defconfig +++ b/configs/stm32f746g-disco/nsh/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -867,7 +866,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32l476-mdk/nsh/defconfig b/configs/stm32l476-mdk/nsh/defconfig index 188e704f0b..fe3e8fc2a7 100644 --- a/configs/stm32l476-mdk/nsh/defconfig +++ b/configs/stm32l476-mdk/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -832,7 +831,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_RANDOM is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/stm32l476vg-disco/nsh/defconfig b/configs/stm32l476vg-disco/nsh/defconfig index 4bebf44d35..c621d79904 100644 --- a/configs/stm32l476vg-disco/nsh/defconfig +++ b/configs/stm32l476vg-disco/nsh/defconfig @@ -62,7 +62,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -897,7 +896,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_RANDOM is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/stm32ldiscovery/nsh/defconfig b/configs/stm32ldiscovery/nsh/defconfig index 04498a3779..5e6fd0b110 100644 --- a/configs/stm32ldiscovery/nsh/defconfig +++ b/configs/stm32ldiscovery/nsh/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -924,7 +923,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/stm32vldiscovery/nsh/defconfig b/configs/stm32vldiscovery/nsh/defconfig index 25ebdfe792..20b009d512 100644 --- a/configs/stm32vldiscovery/nsh/defconfig +++ b/configs/stm32vldiscovery/nsh/defconfig @@ -65,7 +65,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -973,7 +972,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sure-pic32mx/nsh/defconfig b/configs/sure-pic32mx/nsh/defconfig index bf079f0e17..5483e7d690 100644 --- a/configs/sure-pic32mx/nsh/defconfig +++ b/configs/sure-pic32mx/nsh/defconfig @@ -63,7 +63,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set CONFIG_ARCH_MIPS=y -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -741,7 +740,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/sure-pic32mx/usbnsh/defconfig b/configs/sure-pic32mx/usbnsh/defconfig index 42a85541b4..f176dd6ad6 100644 --- a/configs/sure-pic32mx/usbnsh/defconfig +++ b/configs/sure-pic32mx/usbnsh/defconfig @@ -63,7 +63,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set CONFIG_ARCH_MIPS=y -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -783,7 +782,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/teensy-2.0/hello/defconfig b/configs/teensy-2.0/hello/defconfig index b39e8d3db8..410aba1b5c 100644 --- a/configs/teensy-2.0/hello/defconfig +++ b/configs/teensy-2.0/hello/defconfig @@ -62,7 +62,6 @@ CONFIG_DEBUG_FULLOPT=y CONFIG_ARCH_AVR=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -516,7 +515,6 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/teensy-2.0/nsh/defconfig b/configs/teensy-2.0/nsh/defconfig index d46226fbf5..80afdf009b 100644 --- a/configs/teensy-2.0/nsh/defconfig +++ b/configs/teensy-2.0/nsh/defconfig @@ -62,7 +62,6 @@ CONFIG_DEBUG_FULLOPT=y CONFIG_ARCH_AVR=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -529,7 +528,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/teensy-2.0/usbmsc/defconfig b/configs/teensy-2.0/usbmsc/defconfig index c93c850b6c..821868dc61 100644 --- a/configs/teensy-2.0/usbmsc/defconfig +++ b/configs/teensy-2.0/usbmsc/defconfig @@ -62,7 +62,6 @@ CONFIG_DEBUG_FULLOPT=y CONFIG_ARCH_AVR=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -592,7 +591,6 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/teensy-3.x/nsh/defconfig b/configs/teensy-3.x/nsh/defconfig index 073e881a48..5d53034bd9 100644 --- a/configs/teensy-3.x/nsh/defconfig +++ b/configs/teensy-3.x/nsh/defconfig @@ -64,7 +64,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -713,7 +712,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/teensy-3.x/usbnsh/defconfig b/configs/teensy-3.x/usbnsh/defconfig index ad8e9f149d..d0f1374b8f 100644 --- a/configs/teensy-3.x/usbnsh/defconfig +++ b/configs/teensy-3.x/usbnsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -759,7 +758,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/teensy-lc/nsh/defconfig b/configs/teensy-lc/nsh/defconfig index 6b14248f1f..24f484c47d 100644 --- a/configs/teensy-lc/nsh/defconfig +++ b/configs/teensy-lc/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -682,7 +681,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_PWM is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/tm4c123g-launchpad/nsh/defconfig b/configs/tm4c123g-launchpad/nsh/defconfig index 2b1fff6606..eee27b3313 100644 --- a/configs/tm4c123g-launchpad/nsh/defconfig +++ b/configs/tm4c123g-launchpad/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -736,7 +735,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/tm4c1294-launchpad/ipv6/defconfig b/configs/tm4c1294-launchpad/ipv6/defconfig index 392efcf409..0ec47e4059 100644 --- a/configs/tm4c1294-launchpad/ipv6/defconfig +++ b/configs/tm4c1294-launchpad/ipv6/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -556,10 +555,9 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set CONFIG_ARCH_PHY_INTERRUPT=y # CONFIG_PIPES is not set # CONFIG_PM is not set @@ -916,7 +914,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/tm4c1294-launchpad/nsh/defconfig b/configs/tm4c1294-launchpad/nsh/defconfig index 1d098acb40..25a9cfe8b6 100644 --- a/configs/tm4c1294-launchpad/nsh/defconfig +++ b/configs/tm4c1294-launchpad/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -558,10 +557,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set CONFIG_ARCH_PHY_INTERRUPT=y # CONFIG_PIPES is not set # CONFIG_PM is not set @@ -928,7 +926,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/twr-k60n512/nsh/defconfig b/configs/twr-k60n512/nsh/defconfig index 49bc1c331c..5bea922930 100644 --- a/configs/twr-k60n512/nsh/defconfig +++ b/configs/twr-k60n512/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -705,7 +704,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/u-blox-c027/nsh/defconfig b/configs/u-blox-c027/nsh/defconfig index 74c243de7c..588447e164 100644 --- a/configs/u-blox-c027/nsh/defconfig +++ b/configs/u-blox-c027/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -523,10 +522,9 @@ CONFIG_NETDEV_LATEINIT=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -995,7 +993,6 @@ CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_PPPD=y # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/ubw32/nsh/defconfig b/configs/ubw32/nsh/defconfig index aec162d0a1..42258d1f63 100644 --- a/configs/ubw32/nsh/defconfig +++ b/configs/ubw32/nsh/defconfig @@ -63,7 +63,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set CONFIG_ARCH_MIPS=y -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -758,7 +757,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/us7032evb1/nsh/defconfig b/configs/us7032evb1/nsh/defconfig index 1744ab6fb3..d8e8df8334 100644 --- a/configs/us7032evb1/nsh/defconfig +++ b/configs/us7032evb1/nsh/defconfig @@ -53,7 +53,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set CONFIG_ARCH_RENESAS=y # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -439,7 +438,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERLOOP is not set diff --git a/configs/us7032evb1/ostest/defconfig b/configs/us7032evb1/ostest/defconfig index 4b2fe31023..1beac7ba05 100644 --- a/configs/us7032evb1/ostest/defconfig +++ b/configs/us7032evb1/ostest/defconfig @@ -53,7 +53,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set CONFIG_ARCH_RENESAS=y # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -440,7 +439,6 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERLOOP is not set diff --git a/configs/viewtool-stm32f107/highpri/defconfig b/configs/viewtool-stm32f107/highpri/defconfig index ece24f6b88..d05f74d688 100644 --- a/configs/viewtool-stm32f107/highpri/defconfig +++ b/configs/viewtool-stm32f107/highpri/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -975,7 +974,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/viewtool-stm32f107/netnsh/defconfig b/configs/viewtool-stm32f107/netnsh/defconfig index f3d75c91ae..9fece336b9 100644 --- a/configs/viewtool-stm32f107/netnsh/defconfig +++ b/configs/viewtool-stm32f107/netnsh/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -771,10 +770,9 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1160,7 +1158,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/viewtool-stm32f107/nsh/defconfig b/configs/viewtool-stm32f107/nsh/defconfig index 243f7bfee4..2e08d6e3cf 100644 --- a/configs/viewtool-stm32f107/nsh/defconfig +++ b/configs/viewtool-stm32f107/nsh/defconfig @@ -66,7 +66,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -978,7 +977,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/xtrs/nsh/defconfig b/configs/xtrs/nsh/defconfig index 8bf05716eb..aa63aa60f0 100644 --- a/configs/xtrs/nsh/defconfig +++ b/configs/xtrs/nsh/defconfig @@ -53,7 +53,6 @@ CONFIG_WINDOWS_NATIVE=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -339,7 +338,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERLOOP is not set diff --git a/configs/xtrs/ostest/defconfig b/configs/xtrs/ostest/defconfig index 178cf58462..39e06ae357 100644 --- a/configs/xtrs/ostest/defconfig +++ b/configs/xtrs/ostest/defconfig @@ -53,7 +53,6 @@ CONFIG_WINDOWS_NATIVE=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -343,7 +342,6 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERLOOP is not set diff --git a/configs/xtrs/pashello/defconfig b/configs/xtrs/pashello/defconfig index 218a91f1c9..324ef07f30 100644 --- a/configs/xtrs/pashello/defconfig +++ b/configs/xtrs/pashello/defconfig @@ -53,7 +53,6 @@ CONFIG_WINDOWS_NATIVE=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -339,7 +338,6 @@ CONFIG_EXAMPLES_PASHELLO=y # CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERLOOP is not set diff --git a/configs/z16f2800100zcog/nsh/defconfig b/configs/z16f2800100zcog/nsh/defconfig index 3c2af0733f..94b2c6ff7e 100644 --- a/configs/z16f2800100zcog/nsh/defconfig +++ b/configs/z16f2800100zcog/nsh/defconfig @@ -62,7 +62,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -583,7 +582,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/z16f2800100zcog/ostest/defconfig b/configs/z16f2800100zcog/ostest/defconfig index 10554e2b38..99ec6fd098 100644 --- a/configs/z16f2800100zcog/ostest/defconfig +++ b/configs/z16f2800100zcog/ostest/defconfig @@ -62,7 +62,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -582,7 +581,6 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/z16f2800100zcog/pashello/defconfig b/configs/z16f2800100zcog/pashello/defconfig index 984a060075..0594e40c9a 100644 --- a/configs/z16f2800100zcog/pashello/defconfig +++ b/configs/z16f2800100zcog/pashello/defconfig @@ -69,7 +69,6 @@ CONFIG_WINDOWS_CYGWIN=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -376,7 +375,6 @@ CONFIG_EXAMPLES_PASHELLO=y # CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERLOOP is not set diff --git a/configs/z80sim/nsh/defconfig b/configs/z80sim/nsh/defconfig index d7ee01a879..cdc9ce0d71 100644 --- a/configs/z80sim/nsh/defconfig +++ b/configs/z80sim/nsh/defconfig @@ -53,7 +53,6 @@ CONFIG_WINDOWS_NATIVE=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -339,7 +338,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERLOOP is not set diff --git a/configs/z80sim/ostest/defconfig b/configs/z80sim/ostest/defconfig index f0f1fa906d..6184bd8397 100644 --- a/configs/z80sim/ostest/defconfig +++ b/configs/z80sim/ostest/defconfig @@ -53,7 +53,6 @@ CONFIG_WINDOWS_NATIVE=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -343,7 +342,6 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERLOOP is not set diff --git a/configs/z80sim/pashello/defconfig b/configs/z80sim/pashello/defconfig index b4916a2269..a2b5d7fb12 100644 --- a/configs/z80sim/pashello/defconfig +++ b/configs/z80sim/pashello/defconfig @@ -53,7 +53,6 @@ CONFIG_WINDOWS_NATIVE=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -338,7 +337,6 @@ CONFIG_EXAMPLES_PASHELLO=y # CONFIG_EXAMPLES_PIPE is not set # CONFIG_EXAMPLES_POLL is not set # CONFIG_EXAMPLES_QENCODER is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERLOOP is not set diff --git a/configs/z8encore000zco/ostest/defconfig b/configs/z8encore000zco/ostest/defconfig index c1c3702554..79a76d1ba5 100644 --- a/configs/z8encore000zco/ostest/defconfig +++ b/configs/z8encore000zco/ostest/defconfig @@ -62,7 +62,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -587,7 +586,6 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/z8f64200100kit/ostest/defconfig b/configs/z8f64200100kit/ostest/defconfig index 896db3448d..ec1ca29aba 100644 --- a/configs/z8f64200100kit/ostest/defconfig +++ b/configs/z8f64200100kit/ostest/defconfig @@ -62,7 +62,6 @@ CONFIG_DEBUG_FULLOPT=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -588,7 +587,6 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/zkit-arm-1769/hello/defconfig b/configs/zkit-arm-1769/hello/defconfig index 2817bc0674..38855218b9 100644 --- a/configs/zkit-arm-1769/hello/defconfig +++ b/configs/zkit-arm-1769/hello/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -491,10 +490,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -857,7 +855,6 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/zkit-arm-1769/nsh/defconfig b/configs/zkit-arm-1769/nsh/defconfig index 40b204fa69..d7480266d0 100644 --- a/configs/zkit-arm-1769/nsh/defconfig +++ b/configs/zkit-arm-1769/nsh/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -530,10 +529,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -921,7 +919,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/zkit-arm-1769/nxhello/defconfig b/configs/zkit-arm-1769/nxhello/defconfig index ae2a05a5d3..8af1755ddb 100644 --- a/configs/zkit-arm-1769/nxhello/defconfig +++ b/configs/zkit-arm-1769/nxhello/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -568,10 +567,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -1053,7 +1051,6 @@ CONFIG_EXAMPLES_NXHELLO_DEFAULT_FONT=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/zkit-arm-1769/thttpd/defconfig b/configs/zkit-arm-1769/thttpd/defconfig index 691a9323ef..f251f0a05b 100644 --- a/configs/zkit-arm-1769/thttpd/defconfig +++ b/configs/zkit-arm-1769/thttpd/defconfig @@ -61,7 +61,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -491,10 +490,9 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set + # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set # # External Ethernet PHY Device Support @@ -861,7 +859,6 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_ROMFS is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set diff --git a/configs/zp214xpa/nsh/defconfig b/configs/zp214xpa/nsh/defconfig index 60c6a1e69f..14e69b3380 100644 --- a/configs/zp214xpa/nsh/defconfig +++ b/configs/zp214xpa/nsh/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -637,7 +636,6 @@ CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/configs/zp214xpa/nxlines/defconfig b/configs/zp214xpa/nxlines/defconfig index fc721d2aa3..12dbf6f2db 100644 --- a/configs/zp214xpa/nxlines/defconfig +++ b/configs/zp214xpa/nxlines/defconfig @@ -60,7 +60,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_AVR is not set # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_SIM is not set # CONFIG_ARCH_X86 is not set @@ -785,7 +784,6 @@ CONFIG_EXAMPLES_NXLINES_EXTERNINIT=y # CONFIG_EXAMPLES_POSIXSPAWN is not set # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 5bcb225dd0..2d62454562 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -367,26 +367,6 @@ config ENCX24J600_REGDEBUG endif # ENCX24J600 -menuconfig NET_E1000 - bool "E1000 support" - default n - -if NET_E1000 - -config E1000_N_TX_DESC - int "Number of TX descriptors" - default 128 - -config E1000_N_RX_DESC - int "Number of RX descriptors" - default 128 - -config E1000_BUFF_SIZE - int "Buffer size" - default 2048 - -endif # NET_E1000 - menuconfig NET_SLIP bool "SLIP (serial line) support" default n @@ -466,18 +446,6 @@ endchoice # Work queue endif # NET_FTMAC100 -menuconfig NET_VNET - bool "VNET support" - default n - -if NET_VNET - -config VNET_NINTERFACES - int "Number of VNET interfaces" - default 1 - -endif # NET_VNET - if ARCH_HAVE_PHY comment "External Ethernet PHY Device Support" diff --git a/drivers/net/Make.defs b/drivers/net/Make.defs index fe68efb267..144313623b 100644 --- a/drivers/net/Make.defs +++ b/drivers/net/Make.defs @@ -63,14 +63,6 @@ ifeq ($(CONFIG_ENCX24J600),y) CSRCS += encx24j600.c endif -ifeq ($(CONFIG_NET_VNET),y) - CSRCS += vnet.c -endif - -ifeq ($(CONFIG_NET_E1000),y) - CSRCS += e1000.c -endif - ifeq ($(CONFIG_NET_SLIP),y) CSRCS += slip.c endif diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c deleted file mode 100644 index 5bd17e2ae6..0000000000 --- a/drivers/net/e1000.c +++ /dev/null @@ -1,1292 +0,0 @@ -/**************************************************************************** - * drivers/net/e1000.c - * - * Copyright (C) 2011 Yu Qiang. All rights reserved. - * Author: Yu Qiang - * - * This file is a part of NuttX: - * - * Copyright (C) 2011, 2014, 2016 Gregory Nutt. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_NET_PKT -# include -#endif - -#include -#include -#include -#include -#include -#include - -#include "e1000.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */ - -#define E1000_WDDELAY (1*CLK_TCK) - -/* TX timeout = 1 minute */ - -#define E1000_TXTIMEOUT (60*CLK_TCK) - -/* Size of one packet */ - -#define PKTBUF_SIZE (MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE) - -/* This is a helper pointer for accessing the contents of the Ethernet header */ - -#define BUF ((struct eth_hdr_s *)e1000->netdev.d_buf) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct tx_ring -{ - struct tx_desc *desc; - char *buf; - int tail; /* where to write desc */ -}; - -struct rx_ring -{ - struct rx_desc *desc; - char *buf; - int head; /* where to read */ - int tail; /* where to release free desc */ - int free; /* number of freed desc */ -}; - -struct e1000_dev -{ - uint32_t phy_mem_base; - uint32_t io_mem_base; - uint32_t mem_size; - int pci_dev_id; - uint16_t pci_addr; - unsigned char src_mac[6]; - unsigned char dst_mac[6]; - struct irq_action int_desc; - struct tx_ring tx_ring; - struct rx_ring rx_ring; - struct e1000_dev *next; - - /* NuttX net data */ - - bool bifup; /* true:ifup false:ifdown */ - WDOG_ID txpoll; /* TX poll timer */ - WDOG_ID txtimeout; /* TX timeout timer */ - - /* This holds the information visible to the NuttX network */ - - struct net_driver_s netdev; /* Interface understood by networking layer */ -}; - -struct e1000_dev_head -{ - struct e1000_dev *next; -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct e1000_dev_head e1000_list = -{ - 0 -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Common TX logic */ - -static int e1000_transmit(struct e1000_dev *e1000); -static int e1000_txpoll(struct net_driver_s *dev); - -/* Interrupt handling */ - -static void e1000_receive(struct e1000_dev *e1000); - -/* Watchdog timer expirations */ - -static void e1000_polltimer(int argc, uint32_t arg, ...); -static void e1000_txtimeout(int argc, uint32_t arg, ...); - -/* NuttX callback functions */ - -static int e1000_ifup(struct net_driver_s *dev); -static int e1000_ifdown(struct net_driver_s *dev); -static int e1000_txavail(struct net_driver_s *dev); -#ifdef CONFIG_NET_IGMP -static int e1000_addmac(struct net_driver_s *dev, const uint8_t *mac); -static int e1000_rmmac(struct net_driver_s *dev, const uint8_t *mac); -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void e1000_outl(struct e1000_dev *dev, int reg, uint32_t val) -{ - writel(dev->io_mem_base+reg, val); -} - -static inline uint32_t e1000_inl(struct e1000_dev *dev, int reg) -{ - return readl(dev->io_mem_base+reg); -} - -/****************************** e1000 driver ********************************/ - -void e1000_reset(struct e1000_dev *dev) -{ - uint32_t dev_control; - - /* Reset the network controller hardware */ - - dev_control = 0; - dev_control |= (1 << 0); /* FD-bit (Full Duplex) */ - dev_control |= (0 << 2); /* GIOMD-bit (GIO Master Disable) */ - dev_control |= (1 << 3); /* LRST-bit (Link Reset) */ - dev_control |= (1 << 6); /* SLU-bit (Set Link Up) */ - dev_control |= (2 << 8); /* SPEED=2 (1000Mbps) */ - dev_control |= (0 << 11); /* FRCSPD-bit (Force Speed) */ - dev_control |= (0 << 12); /* FRCDPLX-bit (Force Duplex) */ - dev_control |= (0 << 20); /* ADVD3WUC-bit (Advertise D3 Wake Up Cap) */ - dev_control |= (1 << 26); /* RST-bit (Device Reset) */ - dev_control |= (1 << 27); /* RFCE-bit (Receive Flow Control Enable) */ - dev_control |= (1 << 28); /* TFCE-bit (Transmit Flow Control Enable) */ - dev_control |= (0 << 30); /* VME-bit (VLAN Mode Enable) */ - dev_control |= (0 << 31); /* PHY_RST-bit (PHY Reset) */ - - e1000_outl(dev, E1000_IMC, 0xFFFFFFFF); - e1000_outl(dev, E1000_STATUS, 0x00000000); - e1000_outl(dev, E1000_CTRL, dev_control); - dev_control &= ~(1 << 26); /* clear RST-bit (Device Reset) */ - e1000_outl(dev, E1000_CTRL, dev_control); - up_mdelay(10); - e1000_outl(dev, E1000_CTRL_EXT, 0x001401C0); - e1000_outl(dev, E1000_IMC, 0xFFFFFFFF); -} - -void e1000_turn_on(struct e1000_dev *dev) -{ - int tx_control; - int rx_control; - uint32_t ims = 0; - - /* turn on the controller's receive engine */ - - rx_control = e1000_inl(dev, E1000_RCTL); - rx_control |= (1 << 1); - e1000_outl(dev, E1000_RCTL, rx_control); - - /* turn on the controller's transmit engine */ - - tx_control = e1000_inl(dev, E1000_TCTL); - tx_control |= (1 << 1); - e1000_outl(dev, E1000_TCTL, tx_control); - - /* enable the controller's interrupts */ - - e1000_outl(dev, E1000_ICR, 0xFFFFFFFF); - e1000_outl(dev, E1000_IMC, 0xFFFFFFFF); - - ims |= 1 << 0; /* TXDW */ - ims |= 1 << 1; /* TXQE */ - ims |= 1 << 2; /* LSC */ - ims |= 1 << 4; /* RXDMT0 */ - ims |= 1 << 7; /* RXT0 */ - e1000_outl(dev, E1000_IMS, ims); -} - -void e1000_turn_off(struct e1000_dev *dev) -{ - int tx_control; - int rx_control; - - /* turn off the controller's receive engine */ - - rx_control = e1000_inl(dev, E1000_RCTL); - rx_control &= ~(1 << 1); - e1000_outl(dev, E1000_RCTL, rx_control); - - /* turn off the controller's transmit engine */ - - tx_control = e1000_inl(dev, E1000_TCTL); - tx_control &= ~(1 << 1); - e1000_outl(dev, E1000_TCTL, tx_control); - - /* turn off the controller's interrupts */ - - e1000_outl(dev, E1000_IMC, 0xFFFFFFFF); -} - -void e1000_init(struct e1000_dev *dev) -{ - uint32_t rxd_phys; - uint32_t txd_phys; - uint32_t kmem_phys; - uint32_t rx_control; - uint32_t tx_control; - uint32_t pba; - int i; - - e1000_reset(dev); - - /* configure the controller's 'receive' engine */ - - rx_control = 0; - rx_control |= (0 << 1); /* EN-bit (Enable) */ - rx_control |= (0 << 2); /* SPB-bit (Store Bad Packets) */ - rx_control |= (0 << 3); /* UPE-bit (Unicast Promiscuous Mode) */ - rx_control |= (1 << 4); /* MPE-bit (Multicast Promiscuous Mode) */ - rx_control |= (0 << 5); /* LPE-bit (Long Packet Enable) */ - rx_control |= (0 << 6); /* LBM=0 (Loop-Back Mode) */ - rx_control |= (0 << 8); /* RDMTS=0 (Rx Descriptor Min Threshold Size) */ - rx_control |= (0 << 10); /* DTYPE=0 (Descriptor Type) */ - rx_control |= (0 << 12); /* MO=0 (Multicast Offset) */ - rx_control |= (1 << 15); /* BAM-bit (Broadcast Address Mode) */ - rx_control |= (0 << 16); /* BSIZE=0 (Buffer Size = 2048) */ - rx_control |= (0 << 18); /* VLE-bit (VLAN filter Enable) */ - rx_control |= (0 << 19); /* CFIEN-bit (Canonical Form Indicator Enable) */ - rx_control |= (0 << 20); /* CFI-bit (Canonical Form Indicator) */ - rx_control |= (1 << 22); /* DPF-bit (Discard Pause Frames) */ - rx_control |= (0 << 23); /* PMCF-bit (Pass MAC Control Frames) */ - rx_control |= (0 << 25); /* BSEX=0 (Buffer Size EXtension) */ - rx_control |= (1 << 26); /* SECRC-bit (Strip Ethernet CRC) */ - rx_control |= (0 << 27); /* FLEXBUF=0 (Flexible Buffer size) */ - e1000_outl(dev, E1000_RCTL, rx_control); - - /* configure the controller's 'transmit' engine */ - - tx_control = 0; - tx_control |= (0 << 1); /* EN-bit (Enable) */ - tx_control |= (1 << 3); /* PSP-bit (Pad Short Packets) */ - tx_control |= (15 << 4); /* CT=15 (Collision Threshold) */ - tx_control |= (63 << 12); /* COLD=63 (Collision Distance) */ - tx_control |= (0 << 22); /* SWXOFF-bit (Software XOFF) */ - tx_control |= (1 << 24); /* RTLC-bit (Re-Transmit on Late Collision) */ - tx_control |= (0 << 25); /* UNORTX-bit (Underrun No Re-Transmit) */ - tx_control |= (0 << 26); /* TXCSCMT=0 (TxDesc Mininum Threshold) */ - tx_control |= (0 << 28); /* MULR-bit (Multiple Request Support) */ - e1000_outl(dev, E1000_TCTL, tx_control); - - /* hardware flow control */ - - pba = e1000_inl(dev, E1000_PBA); - - /* get receive FIFO size */ - - pba = (pba & 0x000000ff) << 10; - e1000_outl(dev, E1000_FCAL, 0x00C28001); - e1000_outl(dev, E1000_FCAH, 0x00000100); - e1000_outl(dev, E1000_FCT, 0x00008808); - e1000_outl(dev, E1000_FCTTV, 0x00000680); - e1000_outl(dev, E1000_FCRTL, (pba * 8 / 10) | 0x80000000); - e1000_outl(dev, E1000_FCRTH, pba * 9 / 10); - - /* setup tx rings */ - - txd_phys = PADDR((uintptr_t)dev->tx_ring.desc); - kmem_phys = PADDR((uintptr_t)dev->tx_ring.buf); - for (i = 0; i < CONFIG_E1000_N_TX_DESC; i++, kmem_phys += CONFIG_E1000_BUFF_SIZE) - { - dev->tx_ring.desc[i].base_address = kmem_phys; - dev->tx_ring.desc[i].packet_length = 0; - dev->tx_ring.desc[i].cksum_offset = 0; - dev->tx_ring.desc[i].cksum_origin = 0; - dev->tx_ring.desc[i].desc_status = 1; - dev->tx_ring.desc[i].desc_command = (1 << 0) | (1 << 1) | (1 << 3); - dev->tx_ring.desc[i].special_info = 0; - } - - dev->tx_ring.tail = 0; - e1000_outl(dev, E1000_TDT, 0); - e1000_outl(dev, E1000_TDH, 0); - - /* tell controller the location, size, and fetch-policy for Tx queue */ - - e1000_outl(dev, E1000_TDBAL, txd_phys); - e1000_outl(dev, E1000_TDBAH, 0x00000000); - e1000_outl(dev, E1000_TDLEN, CONFIG_E1000_N_TX_DESC * 16); - e1000_outl(dev, E1000_TXDCTL, 0x01010000); - - /* setup rx rings */ - - rxd_phys = PADDR((uintptr_t)dev->rx_ring.desc); - kmem_phys = PADDR((uintptr_t)dev->rx_ring.buf); - for (i = 0; i < CONFIG_E1000_N_RX_DESC; i++, kmem_phys += CONFIG_E1000_BUFF_SIZE) - { - dev->rx_ring.desc[i].base_address = kmem_phys; - dev->rx_ring.desc[i].packet_length = 0; - dev->rx_ring.desc[i].packet_cksum = 0; - dev->rx_ring.desc[i].desc_status = 0; - dev->rx_ring.desc[i].desc_errors = 0; - dev->rx_ring.desc[i].vlan_tag = 0; - } - - dev->rx_ring.head = 0; - dev->rx_ring.tail = CONFIG_E1000_N_RX_DESC-1; - dev->rx_ring.free = 0; - - /* give the controller ownership of all receive descriptors */ - - e1000_outl(dev, E1000_RDH, 0); - e1000_outl(dev, E1000_RDT, CONFIG_E1000_N_RX_DESC-1); - - /* tell controller the location, size, and fetch-policy for RX queue */ - - e1000_outl(dev, E1000_RDBAL, rxd_phys); - e1000_outl(dev, E1000_RDBAH, 0x00000000); - e1000_outl(dev, E1000_RDLEN, CONFIG_E1000_N_RX_DESC*16); - e1000_outl(dev, E1000_RXDCTL, 0x01010000); - - e1000_turn_on(dev); -} - -/**************************************************************************** - * Function: e1000_transmit - * - * Description: - * Start hardware transmission. Called either from the txdone interrupt - * handling or from watchdog based polling. - * - * Parameters: - * e1000 - Reference to the driver state structure - * - * Returned Value: - * OK on success; a negated errno on failure - * - * Assumptions: - * May or may not be called from an interrupt handler. In either case, - * global interrupts are disabled, either explicitly or indirectly through - * interrupt handling logic. - * - ****************************************************************************/ - -static int e1000_transmit(struct e1000_dev *e1000) -{ - int tail = e1000->tx_ring.tail; - unsigned char *cp = (unsigned char *) - (e1000->tx_ring.buf + tail * CONFIG_E1000_BUFF_SIZE); - int count = e1000->netdev.d_len; - - /* Verify that the hardware is ready to send another packet. If we get - * here, then we are committed to sending a packet; Higher level logic - * must have assured that there is not transmission in progress. - */ - - if (!e1000->tx_ring.desc[tail].desc_status) - { - return -1; - } - - /* Send the packet: address=skel->sk_dev.d_buf, length=skel->sk_dev.d_len */ - - memcpy(cp, e1000->netdev.d_buf, e1000->netdev.d_len); - - /* prepare the transmit-descriptor */ - - e1000->tx_ring.desc[tail].packet_length = count < 60 ? 60 : count; - e1000->tx_ring.desc[tail].desc_status = 0; - - /* give ownership of this descriptor to the network controller */ - - tail = (tail + 1) % CONFIG_E1000_N_TX_DESC; - e1000->tx_ring.tail = tail; - e1000_outl(e1000, E1000_TDT, tail); - - /* Enable Tx interrupts */ - - /* Setup the TX timeout watchdog (perhaps restarting the timer) */ - - wd_start(e1000->txtimeout, E1000_TXTIMEOUT, e1000_txtimeout, 1, - (wdparm_t)e1000); - return OK; -} - -/**************************************************************************** - * Function: e1000_txpoll - * - * Description: - * The transmitter is available, check if the network has any outgoing packets ready - * to send. This is a callback from devif_poll(). devif_poll() may be called: - * - * 1. When the preceding TX packet send is complete, - * 2. When the preceding TX packet send timesout and the interface is reset - * 3. During normal TX polling - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * OK on success; a negated errno on failure - * - * Assumptions: - * May or may not be called from an interrupt handler. In either case, - * global interrupts are disabled, either explicitly or indirectly through - * interrupt handling logic. - * - ****************************************************************************/ - -static int e1000_txpoll(struct net_driver_s *dev) -{ - struct e1000_dev *e1000 = (struct e1000_dev *)dev->d_private; - int tail = e1000->tx_ring.tail; - - /* If the polling resulted in data that should be sent out on the network, - * the field d_len is set to a value > 0. - */ - - if (e1000->netdev.d_len > 0) - { - /* Look up the destination MAC address and add it to the Ethernet - * header. - */ - -#ifdef CONFIG_NET_IPv4 -#ifdef CONFIG_NET_IPv6 - if (IFF_IS_IPv4(e1000->netdev.d_flags)) -#endif - { - arp_out(&e1000->netdev); - } -#endif /* CONFIG_NET_IPv4 */ - -#ifdef CONFIG_NET_IPv6 -#ifdef CONFIG_NET_IPv4 - else -#endif - { - neighbor_out(&e1000->netdev); - } -#endif /* CONFIG_NET_IPv6 */ - - /* Send the packet */ - - e1000_transmit(e1000); - - /* Check if there is room in the device to hold another packet. If not, - * return a non-zero value to terminate the poll. - */ - - if (!e1000->tx_ring.desc[tail].desc_status) - { - return -1; - } - } - - /* If zero is returned, the polling will continue until all connections have - * been examined. - */ - - return 0; -} - -/**************************************************************************** - * Function: e1000_receive - * - * Description: - * An interrupt was received indicating the availability of a new RX packet - * - * Parameters: - * e1000 - Reference to the driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * Global interrupts are disabled by interrupt handling logic. - * - ****************************************************************************/ - -static void e1000_receive(struct e1000_dev *e1000) -{ - int head = e1000->rx_ring.head; - unsigned char *cp = (unsigned char *) - (e1000->rx_ring.buf + head * CONFIG_E1000_BUFF_SIZE); - int cnt; - - while (e1000->rx_ring.desc[head].desc_status) - { - /* Here we do not handle packets that exceed packet-buffer size */ - - if ((e1000->rx_ring.desc[head].desc_status & 3) == 1) - { - cprintf("NIC READ: Oversized packet\n"); - goto next; - } - - /* Check if the packet is a valid size for the network buffer configuration */ - - /* get the number of actual data-bytes in this packet */ - - cnt = e1000->rx_ring.desc[head].packet_length; - - if (cnt > CONFIG_NET_ETH_MTU || cnt < 14) - { - cprintf("NIC READ: invalid package size\n"); - goto next; - } - - /* Copy the data data from the hardware to e1000->netdev.d_buf. Set - * amount of data in e1000->netdev.d_len - */ - - /* now we try to copy these data-bytes to the UIP buffer */ - - memcpy(e1000->netdev.d_buf, cp, cnt); - e1000->netdev.d_len = cnt; - -#ifdef CONFIG_NET_PKT - /* When packet sockets are enabled, feed the frame into the packet tap */ - - pkt_input(&e1000->netdev); -#endif - - /* We only accept IP packets of the configured type and ARP packets */ - -#ifdef CONFIG_NET_IPv4 - if (BUF->type == HTONS(ETHTYPE_IP)) - { - ninfo("IPv4 frame\n"); - - /* Handle ARP on input then give the IPv4 packet to the network - * layer - */ - - arp_ipin(&e1000->netdev); - ipv4_input(&e1000->netdev); - - /* If the above function invocation resulted in data that should be - * sent out on the network, the field d_len will set to a value > 0. - */ - - if (e1000->netdev.d_len > 0) - { - /* Update the Ethernet header with the correct MAC address */ - -#ifdef CONFIG_NET_IPv6 - if (IFF_IS_IPv4(e1000->netdev.d_flags)) -#endif - { - arp_out(&e1000->netdev); - } -#ifdef CONFIG_NET_IPv6 - else - { - neighbor_out(&e1000->netdev); - } -#endif - - /* And send the packet */ - - e1000_transmit(e1000); - } - } - else -#endif -#ifdef CONFIG_NET_IPv6 - if (BUF->type == HTONS(ETHTYPE_IP6)) - { - ninfo("Iv6 frame\n"); - - /* Give the IPv6 packet to the network layer */ - - ipv6_input(&e1000->netdev); - - /* If the above function invocation resulted in data that should be - * sent out on the network, the field d_len will set to a value > 0. - */ - - if (e1000->netdev.d_len > 0) - { - /* Update the Ethernet header with the correct MAC address */ - -#ifdef CONFIG_NET_IPv4 - if (IFF_IS_IPv4(e1000->netdev.d_flags)) - { - arp_out(&e1000->netdev); - } - else -#endif -#ifdef CONFIG_NET_IPv6 - { - neighbor_out(&e1000->netdev); - } -#endif - - /* And send the packet */ - - e1000_transmit(e1000); - } - } - else -#endif -#ifdef CONFIG_NET_ARP - if (BUF->type == htons(ETHTYPE_ARP)) - { - arp_arpin(&e1000->netdev); - - /* If the above function invocation resulted in data that should be - * sent out on the network, the field d_len will set to a value > 0. - */ - - if (e1000->netdev.d_len > 0) - { - e1000_transmit(e1000); - } -#endif - } - -next: - e1000->rx_ring.desc[head].desc_status = 0; - e1000->rx_ring.head = (head + 1) % CONFIG_E1000_N_RX_DESC; - e1000->rx_ring.free++; - head = e1000->rx_ring.head; - cp = (unsigned char *)(e1000->rx_ring.buf + head * CONFIG_E1000_BUFF_SIZE); - } -} - -/**************************************************************************** - * Function: e1000_txtimeout - * - * Description: - * Our TX watchdog timed out. Called from the timer interrupt handler. - * The last TX never completed. Reset the hardware and start again. - * - * Parameters: - * argc - The number of available arguments - * arg - The first argument - * - * Returned Value: - * None - * - * Assumptions: - * Global interrupts are disabled by the watchdog logic. - * - ****************************************************************************/ - -static void e1000_txtimeout(int argc, uint32_t arg, ...) -{ - struct e1000_dev *e1000 = (struct e1000_dev *)arg; - - /* Then reset the hardware */ - - e1000_init(e1000); - - /* Then poll the network for new XMIT data */ - - (void)devif_poll(&e1000->netdev, e1000_txpoll); -} - -/**************************************************************************** - * Function: e1000_polltimer - * - * Description: - * Periodic timer handler. Called from the timer interrupt handler. - * - * Parameters: - * argc - The number of available arguments - * arg - The first argument - * - * Returned Value: - * None - * - * Assumptions: - * Global interrupts are disabled by the watchdog logic. - * - ****************************************************************************/ - -static void e1000_polltimer(int argc, uint32_t arg, ...) -{ - struct e1000_dev *e1000 = (struct e1000_dev *)arg; - int tail = e1000->tx_ring.tail; - - /* Check if there is room in the send another TX packet. We cannot perform - * the TX poll if he are unable to accept another packet for transmission. - */ - - if (!e1000->tx_ring.desc[tail].desc_status) - { - return; - } - - /* If so, update TCP timing states and poll the network for new XMIT data. Hmmm.. - * might be bug here. Does this mean if there is a transmit in progress, - * we will missing TCP time state updates? - */ - - (void)devif_timer(&e1000->netdev, e1000_txpoll); - - /* Setup the watchdog poll timer again */ - - (void)wd_start(e1000->txpoll, E1000_WDDELAY, e1000_polltimer, 1, - (wdparm_t)arg); -} - -/**************************************************************************** - * Function: e1000_ifup - * - * Description: - * NuttX Callback: Bring up the Ethernet interface when an IP address is - * provided - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static int e1000_ifup(struct net_driver_s *dev) -{ - struct e1000_dev *e1000 = (struct e1000_dev *)dev->d_private; - - ninfo("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); - - /* Initialize PHYs, the Ethernet interface, and setup up Ethernet interrupts */ - - e1000_init(e1000); - - /* Set and activate a timer process */ - - (void)wd_start(e1000->txpoll, E1000_WDDELAY, e1000_polltimer, 1, - (wdparm_t)e1000); - - if (e1000_inl(e1000, E1000_STATUS) & 2) - { - e1000->bifup = true; - } - else - { - e1000->bifup = false; - } - - return OK; -} - -/**************************************************************************** - * Function: e1000_ifdown - * - * Description: - * NuttX Callback: Stop the interface. - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static int e1000_ifdown(struct net_driver_s *dev) -{ - struct e1000_dev *e1000 = (struct e1000_dev *)dev->d_private; - irqstate_t flags; - - /* Disable the Ethernet interrupt */ - - flags = enter_critical_section(); - - e1000_turn_off(e1000); - - /* Cancel the TX poll timer and TX timeout timers */ - - wd_cancel(e1000->txpoll); - wd_cancel(e1000->txtimeout); - - /* Put the EMAC is its reset, non-operational state. This should be - * a known configuration that will guarantee the skel_ifup() always - * successfully brings the interface back up. - */ - - //e1000_reset(e1000); - - /* Mark the device "down" */ - - e1000->bifup = false; - leave_critical_section(flags); - - return OK; -} - -/**************************************************************************** - * Function: e1000_txavail - * - * Description: - * Driver callback invoked when new TX data is available. This is a - * stimulus perform an out-of-cycle poll and, thereby, reduce the TX - * latency. - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * Called in normal user mode - * - ****************************************************************************/ - -static int e1000_txavail(struct net_driver_s *dev) -{ - struct e1000_dev *e1000 = (struct e1000_dev *)dev->d_private; - int tail = e1000->tx_ring.tail; - irqstate_t flags; - - /* Disable interrupts because this function may be called from interrupt - * level processing. - */ - - flags = enter_critical_section(); - - /* Ignore the notification if the interface is not yet up */ - - if (e1000->bifup) - { - /* Check if there is room in the hardware to hold another outgoing packet. */ - - if (e1000->tx_ring.desc[tail].desc_status) - { - (void)devif_poll(&e1000->netdev, e1000_txpoll); - } - } - - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Function: e1000_addmac - * - * Description: - * NuttX Callback: Add the specified MAC address to the hardware multicast - * address filtering - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * mac - The MAC address to be added - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -#ifdef CONFIG_NET_IGMP -static int e1000_addmac(struct net_driver_s *dev, const uint8_t *mac) -{ - /* Add the MAC address to the hardware multicast routing table */ - - return OK; -} -#endif - -/**************************************************************************** - * Function: e1000_rmmac - * - * Description: - * NuttX Callback: Remove the specified MAC address from the hardware multicast - * address filtering - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * mac - The MAC address to be removed - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -#ifdef CONFIG_NET_IGMP -static int e1000_rmmac(struct net_driver_s *dev, const uint8_t *mac) -{ - /* Add the MAC address to the hardware multicast routing table */ - - return OK; -} -#endif - -static irqreturn_t e1000_interrupt_handler(int irq, void *dev_id) -{ - struct e1000_dev *e1000 = (struct e1000_dev *)dev_id; - - /* Get and clear interrupt status bits */ - - int intr_cause = e1000_inl(e1000, E1000_ICR); - e1000_outl(e1000, E1000_ICR, intr_cause); - - /* not for me */ - - if (intr_cause == 0) - { - return IRQ_NONE; - } - - /* Handle interrupts according to status bit settings */ - - /* Link status change */ - - if (intr_cause & (1 << 2)) - { - if (e1000_inl(e1000, E1000_STATUS) & 2) - { - e1000->bifup = true; - } - else - { - e1000->bifup = false; - } - } - - /* Check if we received an incoming packet, if so, call skel_receive() */ - - /* Rx-descriptor Timer expired */ - - if (intr_cause & (1 << 7)) - { - e1000_receive(e1000); - } - - /* Tx queue empty */ - - if (intr_cause & (1 << 1)) - { - wd_cancel(e1000->txtimeout); - } - - /* Tx-descriptor Written back */ - - if (intr_cause & (1 << 0)) - { - devif_poll(&e1000->netdev, e1000_txpoll); - } - - /* Rx-Descriptors Low */ - - if (intr_cause & (1 << 4)) - { - int tail; - - tail = e1000->rx_ring.tail + e1000->rx_ring.free; - tail %= CONFIG_E1000_N_RX_DESC; - e1000->rx_ring.tail = tail; - e1000->rx_ring.free = 0; - e1000_outl(e1000, E1000_RDT, tail); - } - - return IRQ_HANDLED; -} - -/******************************* PCI driver *********************************/ - -static pci_id_t e1000_id_table[] = -{ - { - .sep = - { - INTEL_VENDERID, E1000_82573L - } - }, - { - .sep = - { - INTEL_VENDERID, E1000_82540EM - } - }, - { - .sep = - { - INTEL_VENDERID, E1000_82574L - } - }, - { - .sep = - { - INTEL_VENDERID, E1000_82567LM - } - }, - { - .sep = - { - INTEL_VENDERID, E1000_82541PI - } - }, - { - .sep = - { - 0, 0 - } - } -}; - -static int e1000_probe(uint16_t addr, pci_id_t id) -{ - FAR struct e1000_dev *dev; - uint32_t mmio_base; - uint32_t mmio_size; - uint32_t size; - FAR uint8_t *pktbuf - FAR void *kmem; - FAR void *omem; - int errcode; - - /* Allocate e1000_dev memory */ - - if ((dev = (FAR struct e1000_dev *)kmm_zalloc(sizeof(struct e1000_dev))) == NULL) - { - return -ENOMEM; - } - - if ((pktbuf = (FAR uint8_t *)kmm_zalloc(PKTBUF_SIZE)) == NULL) - { - errcode = -ENOMEM; - goto errout_with_dev; - } - - /* save pci addr */ - - dev->pci_addr = addr; - - /* enable device */ - - if ((errcode = pci_enable_device(addr, PCI_BUS_MASTER)) < 0) - { - goto errout_with_pktbuf; - } - - /* get e1000 device type */ - - dev->pci_dev_id = id.join; - - /* remap the controller's i/o-memory into kernel's address-space */ - - mmio_base = pci_resource_start(addr, 0); - mmio_size = pci_resource_len(addr, 0); - errcode = rgmp_memmap_nocache(mmio_base, mmio_size, mmio_base); - if (errcode) - { - goto errout_with_pktbuf; - } - - dev->phy_mem_base = mmio_base; - dev->io_mem_base = mmio_base; - dev->mem_size = mmio_size; - - /* MAC address */ - - memset(dev->dst_mac, 0xFF, 6); - memcpy(dev->src_mac, (void *)(dev->io_mem_base+E1000_RA), 6); - - /* IRQ setup */ - - dev->int_desc.handler = e1000_interrupt_handler; - dev->int_desc.dev_id = dev; - if ((errcode = pci_request_irq(addr, &dev->int_desc, 0)) < 0) - { - goto errout_with_memmap; - } - - /* Here we alloc a big block of memory once and make it - * aligned to page boundary and multiple of page size. This - * is because the memory can be modified by E1000 DMA and - * should be mapped no-cache which will hugely reduce memory - * access performance. The page size alloc will restrict - * this bad effect only within the memory we alloc here. - * - * NEED FIX: the memalign may alloc memory continuous in - * virtual address but dis-continuous in physical address - * due to RGMP memory setup. - */ - - size = CONFIG_E1000_N_TX_DESC * sizeof(struct tx_desc) + - CONFIG_E1000_N_TX_DESC * CONFIG_E1000_BUFF_SIZE + - CONFIG_E1000_N_RX_DESC * sizeof(struct rx_desc) + - CONFIG_E1000_N_RX_DESC * CONFIG_E1000_BUFF_SIZE; - size = ROUNDUP(size, PGSIZE); - - omem = kmem = memalign(PGSIZE, size); - if (kmem == NULL) - { - errcode = -ENOMEM; - goto errout_with_pci; - } - - rgmp_memremap_nocache((uintptr_t)kmem, size); - - /* alloc memory for tx ring */ - - dev->tx_ring.desc = (FAR struct tx_desc *)kmem; - kmem += CONFIG_E1000_N_TX_DESC * sizeof(struct tx_desc); - dev->tx_ring.buf = kmem; - kmem += CONFIG_E1000_N_TX_DESC * CONFIG_E1000_BUFF_SIZE; - - /* alloc memory for rx rings */ - - dev->rx_ring.desc = (FAR struct rx_desc *)kmem; - kmem += CONFIG_E1000_N_RX_DESC * sizeof(struct rx_desc); - dev->rx_ring.buf = kmem; - - /* Initialize the driver structure */ - - dev->netdev.d_buf = pktbuf; /* Single packet buffer */ - dev->netdev.d_ifup = e1000_ifup; /* I/F up (new IP address) callback */ - dev->netdev.d_ifdown = e1000_ifdown; /* I/F down callback */ - dev->netdev.d_txavail = e1000_txavail; /* New TX data callback */ -#ifdef CONFIG_NET_IGMP - dev->netdev.d_addmac = e1000_addmac; /* Add multicast MAC address */ - dev->netdev.d_rmmac = e1000_rmmac; /* Remove multicast MAC address */ -#endif - dev->netdev.d_private = dev; /* Used to recover private state from dev */ - - /* Create a watchdog for timing polling for and timing of transmisstions */ - - dev->txpoll = wd_create(); /* Create periodic poll timer */ - dev->txtimeout = wd_create(); /* Create TX timeout timer */ - - /* Put the interface in the down state. - * e1000 reset - */ - - e1000_reset(dev); - - /* Read the MAC address from the hardware */ - - memcpy(dev->netdev.d_mac.ether_addr_octet, (void *)(dev->io_mem_base+E1000_RA), 6); - - /* Register the device with the OS so that socket IOCTLs can be performed */ - - errcode = netdev_register(&dev->netdev, NET_LL_ETHERNET); - if (errcode) - { - goto errout_with_omem; - } - - /* insert into e1000_list */ - - dev->next = e1000_list.next; - e1000_list.next = dev; - cprintf("bring up e1000 device: %04x %08x\n", addr, id.join); - - return 0; - -errout_with_omem: - rgmp_memremap((uintptr_t)omem, size); - free(omem); -errout_with_pci: - pci_free_irq(addr); -errout_with_memmap: - rgmp_memunmap(mmio_base, mmio_size); -errout_with_pktbuf: - kmm_free(pktbuf); -errout_with_dev: - kmm_free(dev); - cprintf("e1000 device probe fail: %d\n", errcode); - return errcode; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void e1000_mod_init(void) -{ - pci_probe_device(e1000_id_table, e1000_probe); -} - -void e1000_mod_exit(void) -{ - uint32_t size; - struct e1000_dev *dev; - - size = CONFIG_E1000_N_TX_DESC * sizeof(struct tx_desc) + - CONFIG_E1000_N_TX_DESC * CONFIG_E1000_BUFF_SIZE + - CONFIG_E1000_N_RX_DESC * sizeof(struct rx_desc) + - CONFIG_E1000_N_RX_DESC * CONFIG_E1000_BUFF_SIZE; - size = ROUNDUP(size, PGSIZE); - - for (dev = e1000_list.next; dev != NULL; dev = dev->next) - { - netdev_unregister(&dev->netdev); - e1000_reset(dev); - wd_delete(dev->txpoll); - wd_delete(dev->txtimeout); - rgmp_memremap((uintptr_t)dev->tx_ring.desc, size); - free(dev->tx_ring.desc); - pci_free_irq(dev->pci_addr); - rgmp_memunmap((uintptr_t)dev->io_mem_base, dev->mem_size); - kmm_free(dev->netdev.d_buf); - kmm_free(dev); - } - - e1000_list.next = NULL; -} diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h deleted file mode 100644 index 63ff53e3c3..0000000000 --- a/drivers/net/e1000.h +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * drivers/net/e1000.h - * - * Copyright (C) 2011 Yu Qiang. All rights reserved. - * Author: Yu Qiang - * - * This file is a part of NuttX: - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __DRIVERS_NET_E1000_H -#define __DRIVERS_NET_E1000_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/************** PCI ID ***************/ - -#define INTEL_VENDERID 0x8086 -#define E1000_82573L 0x109a -#define E1000_82540EM 0x100e -#define E1000_82574L 0x10d3 -#define E1000_82567LM 0x10f5 -#define E1000_82541PI 0x107c - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -enum e1000_registers { - E1000_CTRL = 0x0000, // Device Control - E1000_STATUS = 0x0008, // Device Status - E1000_CTRL_EXT = 0x0018, // Device Control Extension - E1000_FCAL = 0x0028, // Flow Control Address Low - E1000_FCAH = 0x002C, // Flow Control Address High - E1000_FCT = 0x0030, // Flow Control Type - E1000_ICR = 0x00C0, // Interrupt Cause Read - E1000_ICS = 0x00C8, // Interrupt Cause Set - E1000_IMS = 0x00D0, // Interrupt Mask Set - E1000_IMC = 0x00D8, // Interrupt Mask Clear - E1000_RCTL = 0x0100, // Receive Control - E1000_FCTTV = 0x0170, // Flow Control Transmit Timer Value - E1000_TCTL = 0x0400, // Transmit Control - E1000_PBA = 0x1000, // Packet Buffer Allocation - E1000_FCRTL = 0x2160, // Flow Control Receive Threshold Low - E1000_FCRTH = 0x2168, // Flow Control Receive Threshold High - E1000_RDBAL = 0x2800, // Rx Descriptor Base Address Low - E1000_RDBAH = 0x2804, // Rx Descriptor Base Address High - E1000_RDLEN = 0x2808, // Rx Descriptor Length - E1000_RDH = 0x2810, // Rx Descriptor Head - E1000_RDT = 0x2818, // Rx Descriptor Tail - E1000_RXDCTL = 0x2828, // Rx Descriptor Control - E1000_TDBAL = 0x3800, // Tx Descriptor Base Address Low - E1000_TDBAH = 0x3804, // Tx Descriptor Base Address High - E1000_TDLEN = 0x3808, // Tx Descriptor Length - E1000_TDH = 0x3810, // Tx Descriptor Head - E1000_TDT = 0x3818, // Tx Descriptor Tail - E1000_TXDCTL = 0x3828, // Tx Descriptor Control - E1000_TPR = 0x40D0, // Total Packets Received - E1000_TPT = 0x40D4, // Total Packets Transmitted - E1000_RA = 0x5400, // Receive-filter Array -}; - -/***************** e1000 device structure *****************/ - -struct tx_desc { - uint64_t base_address; - uint16_t packet_length; - uint8_t cksum_offset; - uint8_t desc_command; - uint8_t desc_status; - uint8_t cksum_origin; - uint16_t special_info; -}; - -struct rx_desc { - uint64_t base_address; - uint16_t packet_length; - uint16_t packet_cksum; - uint8_t desc_status; - uint8_t desc_errors; - uint16_t vlan_tag; -}; - -#endif diff --git a/drivers/net/vnet.c b/drivers/net/vnet.c deleted file mode 100644 index 18dc4d5c36..0000000000 --- a/drivers/net/vnet.c +++ /dev/null @@ -1,789 +0,0 @@ -/**************************************************************************** - * drivers/net/vnet.c - * - * Copyright (C) 2011 Yu Qiang. All rights reserved. - * Author: Yu Qiang - * - * This file is a part of NuttX: - * - * Copyright (C) 2011, 2014 Gregory Nutt. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#if defined(CONFIG_NET) && defined(CONFIG_NET_VNET) - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include - -#ifdef CONFIG_NET_PKT -# include -#endif - -#include -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* CONFIG_VNET_NINTERFACES determines the number of physical interfaces - * that will be supported. - */ - -#ifndef CONFIG_VNET_NINTERFACES -# define CONFIG_VNET_NINTERFACES 1 -#endif - -/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */ - -#define VNET_WDDELAY (1*CLK_TCK) - -/* TX timeout = 1 minute */ - -#define VNET_TXTIMEOUT (60*CLK_TCK) - -/* This is a helper pointer for accessing the contents of the Ethernet header */ - -#define BUF ((struct eth_hdr_s *)vnet->vn_dev.d_buf) - -#define PKTBUF_SIZE (MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* The vnet_driver_s encapsulates all state information for a single hardware - * interface - */ - -struct vnet_driver_s -{ - bool vn_bifup; /* true:ifup false:ifdown */ - WDOG_ID vn_txpoll; /* TX poll timer */ - struct rgmp_vnet *vnet; - - /* This holds the information visible to the NuttX */ - - struct net_driver_s vn_dev; /* Interface understood by the network */ -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* A single packet buffer per driver is used */ - -static uint8_t g_pktbuf[PKTBUF_SIZE * CONFIG_VNET_NINTERFACES]; - -/* Driver state structure instancs */ - -static struct vnet_driver_s g_vnet[CONFIG_VNET_NINTERFACES]; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Common TX logic */ - -static int vnet_transmit(FAR struct vnet_driver_s *vnet); -static int vnet_txpoll(struct net_driver_s *dev); - -/* Interrupt handling */ - -static void vnet_txdone(FAR struct vnet_driver_s *vnet); - -/* Watchdog timer expirations */ - -static void vnet_polltimer(int argc, uint32_t arg, ...); -static void vnet_txtimeout(int argc, uint32_t arg, ...); - -/* NuttX callback functions */ - -static int vnet_ifup(struct net_driver_s *dev); -static int vnet_ifdown(struct net_driver_s *dev); -static int vnet_txavail(struct net_driver_s *dev); -#ifdef CONFIG_NET_IGMP -static int vnet_addmac(struct net_driver_s *dev, FAR const uint8_t *mac); -static int vnet_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac); -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: vnet_transmit - * - * Description: - * Start hardware transmission. Called either from the txdone interrupt - * handling or from watchdog based polling. - * - * Parameters: - * vnet - Reference to the driver state structure - * - * Returned Value: - * OK on success; a negated errno on failure - * - * Assumptions: - * May or may not be called from an interrupt handler. In either case, - * global interrupts are disabled, either explicitly or indirectly through - * interrupt handling logic. - * - ****************************************************************************/ - -static int vnet_transmit(FAR struct vnet_driver_s *vnet) -{ - int errcode; - - /* Verify that the hardware is ready to send another packet. If we get - * here, then we are committed to sending a packet; Higher level logic - * must have assured that there is not transmission in progress. - */ - - /* Send the packet: address=vnet->vn_dev.d_buf, length=vnet->vn_dev.d_len */ - - errcode = vnet_xmit(vnet->vnet, (char *)vnet->vn_dev.d_buf, vnet->vn_dev.d_len); - if (errcode) - { - /* When vnet_xmit fail, it means TX buffer is full. Watchdog - * is of no use here because no TX done INT will happen. So - * we reset the TX buffer directly. - */ - -#ifdef CONFIG_DEBUG_FEATURES - cprintf("VNET: TX buffer is full\n"); -#endif - return ERROR; - } - else - { - /* This step may be unnecessary here */ - - vnet_txdone(vnet); - } - - return OK; -} - -/**************************************************************************** - * Function: vnet_txpoll - * - * Description: - * The transmitter is available, check if the network has any outgoing - * packets ready to send. This is a callback from devif_poll(). - * devif_poll() may be called: - * - * 1. When the preceding TX packet send is complete, - * 2. When the preceding TX packet send timesout and the interface is reset - * 3. During normal TX polling - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * OK on success; a negated errno on failure - * - * Assumptions: - * May or may not be called from an interrupt handler. In either case, - * global interrupts are disabled, either explicitly or indirectly through - * interrupt handling logic. - * - ****************************************************************************/ - -static int vnet_txpoll(struct net_driver_s *dev) -{ - FAR struct vnet_driver_s *vnet = (FAR struct vnet_driver_s *)dev->d_private; - - /* If the polling resulted in data that should be sent out on the network, - * the field d_len is set to a value > 0. - */ - - if (vnet->vn_dev.d_len > 0) - { - /* Look up the destination MAC address and add it to the Ethernet - * header. - */ - -#ifdef CONFIG_NET_IPv4 -#ifdef CONFIG_NET_IPv6 - if (IFF_IS_IPv4(vnet->vn_dev.d_flags)) -#endif - { - arp_out(&vnet->vn_dev); - } -#endif /* CONFIG_NET_IPv4 */ - -#ifdef CONFIG_NET_IPv6 -#ifdef CONFIG_NET_IPv4 - else -#endif - { - neighbor_out(&vnet->vn_dev); - } -#endif /* CONFIG_NET_IPv6 */ - - /* Send the packet */ - - vnet_transmit(vnet); - - /* Check if there is room in the device to hold another packet. If not, - * return a non-zero value to terminate the poll. - */ - - if (vnet_is_txbuff_full(vnet->vnet)) - { - return 1; - } - } - - /* If zero is returned, the polling will continue until all connections have - * been examined. - */ - - return 0; -} - -/**************************************************************************** - * Function: rtos_vnet_recv - * - * Description: - * An interrupt was received indicating the availability of a new RX packet - * - * Parameters: - * vnet - Reference to the driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * Global interrupts are disabled by interrupt handling logic. - * - ****************************************************************************/ - -void rtos_vnet_recv(struct rgmp_vnet *rgmp_vnet, char *data, int len) -{ - struct vnet_driver_s *vnet = rgmp_vnet->priv; - - do - { - /* Check if the packet is a valid size for the network buffer - * configuration. - */ - - if (len > CONFIG_NET_ETH_MTU || len < 14) - { -#ifdef CONFIG_DEBUG_FEATURES - cprintf("VNET: receive invalid packet of size %d\n", len); -#endif - return; - } - - /* Copy the data data from the hardware to vnet->vn_dev.d_buf. Set - * amount of data in vnet->vn_dev.d_len - */ - - memcpy(vnet->vn_dev.d_buf, data, len); - vnet->vn_dev.d_len = len; - -#ifdef CONFIG_NET_PKT - /* When packet sockets are enabled, feed the frame into the packet tap */ - - pkt_input(&vnet->vn_dev); -#endif - - /* We only accept IP packets of the configured type and ARP packets */ - -#ifdef CONFIG_NET_IPv4 - if (BUF->type == HTONS(ETHTYPE_IP)) - { - ninfo("IPv4 frame\n"); - - /* Handle ARP on input then give the IPv4 packet to the network - * layer - */ - - arp_ipin(&vnet->vn_dev); - ipv4_input(&vnet->vn_dev); - - /* If the above function invocation resulted in data that should be - * sent out on the network, the field d_len will set to a value > 0. - */ - - if (vnet->vn_dev.d_len > 0) - { - /* Update the Ethernet header with the correct MAC address */ - -#ifdef CONFIG_NET_IPv6 - if (IFF_IS_IPv4(vnet->vn_dev.d_flags)) -#endif - { - arp_out(&vnet->vn_dev); - } -#ifdef CONFIG_NET_IPv6 - else - { - neighbor_out(&vnet->vn_dev); - } -#endif - - /* And send the packet */ - - vnet_transmit(vnet); - } - } - else -#endif -#ifdef CONFIG_NET_IPv6 - if (BUF->type == HTONS(ETHTYPE_IP6)) - { - ninfo("Iv6 frame\n"); - - /* Give the IPv6 packet to the network layer */ - - ipv6_input(&vnet->vn_dev); - - /* If the above function invocation resulted in data that should be - * sent out on the network, the field d_len will set to a value > 0. - */ - - if (vnet->vn_dev.d_len > 0) - { - /* Update the Ethernet header with the correct MAC address */ - -#ifdef CONFIG_NET_IPv4 - if (IFF_IS_IPv4(vnet->vn_dev.d_flags)) - { - arp_out(&vnet->vn_dev); - } - else -#endif -#ifdef CONFIG_NET_IPv6 - { - neighbor_out(&vnet->vn_dev); - } -#endif - - /* And send the packet */ - - vnet_transmit(vnet); - } - } - else -#endif -#ifdef CONFIG_NET_ARP - if (BUF->type == htons(ETHTYPE_ARP)) - { - arp_arpin(&vnet->vn_dev); - - /* If the above function invocation resulted in data that should - * be sent out on the network, the field d_len will set to a - * value > 0. - */ - - if (vnet->vn_dev.d_len > 0) - { - vnet_transmit(vnet); - } - } -#endif - } - while (0); /* While there are more packets to be processed */ -} - -/**************************************************************************** - * Function: vnet_txdone - * - * Description: - * An interrupt was received indicating that the last TX packet(s) is done - * - * Parameters: - * vnet - Reference to the driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * Global interrupts are disabled by the watchdog logic. - * - ****************************************************************************/ - -static void vnet_txdone(FAR struct vnet_driver_s *vnet) -{ - /* Poll the network for new XMIT data */ - - (void)devif_poll(&vnet->vn_dev, vnet_txpoll); -} - -/**************************************************************************** - * Function: vnet_txtimeout - * - * Description: - * Our TX watchdog timed out. Called from the timer interrupt handler. - * The last TX never completed. Reset the hardware and start again. - * - * Parameters: - * argc - The number of available arguments - * arg - The first argument - * - * Returned Value: - * None - * - * Assumptions: - * Global interrupts are disabled by the watchdog logic. - * - ****************************************************************************/ - -static void vnet_txtimeout(int argc, uint32_t arg, ...) -{ - FAR struct vnet_driver_s *vnet = (FAR struct vnet_driver_s *)arg; - - /* Poll the network for new XMIT data */ - - (void)devif_poll(&vnet->vn_dev, vnet_txpoll); -} - -/**************************************************************************** - * Function: vnet_polltimer - * - * Description: - * Periodic timer handler. Called from the timer interrupt handler. - * - * Parameters: - * argc - The number of available arguments - * arg - The first argument - * - * Returned Value: - * None - * - * Assumptions: - * Global interrupts are disabled by the watchdog logic. - * - ****************************************************************************/ - -static void vnet_polltimer(int argc, uint32_t arg, ...) -{ - FAR struct vnet_driver_s *vnet = (FAR struct vnet_driver_s *)arg; - - /* Check if there is room in the send another TX packet. We cannot perform - * the TX poll if he are unable to accept another packet for transmission. - */ - - if (vnet_is_txbuff_full(vnet->vnet)) - { -#ifdef CONFIG_DEBUG_FEATURES - cprintf("VNET: TX buffer is full\n"); -#endif - return; - } - - /* If so, update TCP timing states and poll the network for new XMIT data. - * Hmmm.. might be bug here. Does this mean if there is a transmit in - * progress, we will missing TCP time state updates? - */ - - (void)devif_timer(&vnet->vn_dev, vnet_txpoll); - - /* Setup the watchdog poll timer again */ - - (void)wd_start(vnet->vn_txpoll, VNET_WDDELAY, vnet_polltimer, 1, - (wdparm_t)arg); -} - -/**************************************************************************** - * Function: vnet_ifup - * - * Description: - * NuttX Callback: Bring up the Ethernet interface when an IP address is - * provided - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static int vnet_ifup(struct net_driver_s *dev) -{ - FAR struct vnet_driver_s *vnet = (FAR struct vnet_driver_s *)dev->d_private; - - ninfo("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); - - /* Initialize PHYs, the Ethernet interface, and setup up Ethernet interrupts */ - - /* Set and activate a timer process */ - - (void)wd_start(vnet->vn_txpoll, VNET_WDDELAY, vnet_polltimer, 1, - (wdparm_t)vnet); - - vnet->vn_bifup = true; - return OK; -} - -/**************************************************************************** - * Function: vnet_ifdown - * - * Description: - * NuttX Callback: Stop the interface. - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static int vnet_ifdown(struct net_driver_s *dev) -{ - FAR struct vnet_driver_s *vnet = (FAR struct vnet_driver_s *)dev->d_private; - irqstate_t flags; - - /* Disable the Ethernet interrupt */ - - flags = enter_critical_section(); - - /* Cancel the TX poll timer and TX timeout timers */ - - wd_cancel(vnet->vn_txpoll); - - /* Put the EMAC is its reset, non-operational state. This should be - * a known configuration that will guarantee the vnet_ifup() always - * successfully brings the interface back up. - */ - - /* Mark the device "down" */ - - vnet->vn_bifup = false; - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Function: vnet_txavail - * - * Description: - * Driver callback invoked when new TX data is available. This is a - * stimulus perform an out-of-cycle poll and, thereby, reduce the TX - * latency. - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * Called in normal user mode - * - ****************************************************************************/ - -static int vnet_txavail(struct net_driver_s *dev) -{ - FAR struct vnet_driver_s *vnet = (FAR struct vnet_driver_s *)dev->d_private; - irqstate_t flags; - - /* Disable interrupts because this function may be called from interrupt - * level processing. - */ - - flags = enter_critical_section(); - - /* Ignore the notification if the interface is not yet up */ - - if (vnet->vn_bifup) - { - /* Check if there is room in the hardware to hold another outgoing packet. */ - - if (vnet_is_txbuff_full(vnet->vnet)) - { -#ifdef CONFIG_DEBUG_FEATURES - cprintf("VNET: TX buffer is full\n"); -#endif - goto out; - } - - /* If so, then poll the network for new XMIT data */ - - (void)devif_poll(&vnet->vn_dev, vnet_txpoll); - } - -out: - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Function: vnet_addmac - * - * Description: - * NuttX Callback: Add the specified MAC address to the hardware multicast - * address filtering - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * mac - The MAC address to be added - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -#ifdef CONFIG_NET_IGMP -static int vnet_addmac(struct net_driver_s *dev, FAR const uint8_t *mac) -{ - FAR struct vnet_driver_s *vnet = (FAR struct vnet_driver_s *)dev->d_private; - - /* Add the MAC address to the hardware multicast routing table */ - - return OK; -} -#endif - -/**************************************************************************** - * Function: vnet_rmmac - * - * Description: - * NuttX Callback: Remove the specified MAC address from the hardware multicast - * address filtering - * - * Parameters: - * dev - Reference to the NuttX driver state structure - * mac - The MAC address to be removed - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -#ifdef CONFIG_NET_IGMP -static int vnet_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac) -{ - FAR struct vnet_driver_s *vnet = (FAR struct vnet_driver_s *)dev->d_private; - - /* Add the MAC address to the hardware multicast routing table */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: vnet_initialize - * - * Description: - * Initialize the Ethernet controller and driver - * - * Parameters: - * intf - In the case where there are multiple EMACs, this value - * identifies which EMAC is to be initialized. - * - * Returned Value: - * OK on success; Negated errno on failure. - * - * Assumptions: - * - ****************************************************************************/ - -int vnet_init(FAR struct rgmp_vnet *vnet) -{ - FAR struct vnet_driver_s *priv; - FAR uint8_t *pktbuf; - static int i = 0; - - if (i >= CONFIG_VNET_NINTERFACES) - { - return -1; - } - - /* Get the packet buffer associated with this instance */ - - pktbuf = &g_pktbuf[PKTBUF_SIZE * i]; - priv = &g_vnet[i++]; - - /* Initialize the driver structure */ - - memset(priv, 0, sizeof(struct vnet_driver_s)); - priv->vn_dev.d_buf = pktbuf; /* Single packet buffer */ - priv->vn_dev.d_ifup = vnet_ifup; /* I/F down callback */ - priv->vn_dev.d_ifdown = vnet_ifdown; /* I/F up (new IP address) callback */ - priv->vn_dev.d_txavail = vnet_txavail; /* New TX data callback */ -#ifdef CONFIG_NET_IGMP - priv->vn_dev.d_addmac = vnet_addmac; /* Add multicast MAC address */ - priv->vn_dev.d_rmmac = vnet_rmmac; /* Remove multicast MAC address */ -#endif - priv->vn_dev.d_private = (FAR void *)priv; /* Used to recover private state from dev */ - - /* Create a watchdog for timing polling for and timing of transmisstions */ - - priv->vn_txpoll = wd_create(); /* Create periodic poll timer */ - - priv->vnet = vnet; - vnet->priv = priv; - - /* Register the device with the OS */ - - (void)netdev_register(&priv->vn_dev), NET_LL_ETHERNET; - - return 0; -} - -#endif /* CONFIG_NET && CONFIG_NET_VNET */ diff --git a/tools/cfgdefine.c b/tools/cfgdefine.c index bb9a81eee2..cd8816734e 100644 --- a/tools/cfgdefine.c +++ b/tools/cfgdefine.c @@ -72,10 +72,6 @@ static const char *dequote_list[] = "CONFIG_INIT_SYMTAB", /* Global symbol table */ "CONFIG_INIT_NEXPORTS", /* Global symbol table size */ - /* RGMP */ - - "CONFIG_RGMP_SUBARCH", /* RGMP sub-architecture */ - /* NxWidgets/NxWM */ "CONFIG_NXWM_BACKGROUND_IMAGE", /* Name of bitmap image class */ -- GitLab From b95e1f656b150dbc8acf59d4ac75d919e26beba0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 2 Dec 2016 13:51:07 -0600 Subject: [PATCH 573/734] i.MX6: Add an untested SPI driver taken directly from the i.MX1 port. --- arch/arm/src/imx6/imx_ecspi.c | 1445 +++++++++++++++++++++++++++++++++ 1 file changed, 1445 insertions(+) create mode 100644 arch/arm/src/imx6/imx_ecspi.c diff --git a/arch/arm/src/imx6/imx_ecspi.c b/arch/arm/src/imx6/imx_ecspi.c new file mode 100644 index 0000000000..15c602a7c9 --- /dev/null +++ b/arch/arm/src/imx6/imx_ecspi.c @@ -0,0 +1,1445 @@ +/**************************************************************************** + * arch/arm/src/imx6/imx_ecspi.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from the i.MX1 CSPI driver: + * + * Copyright (C) 2009-2010, 2013, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" +#include "imx_gpio.h" +#include "imx_ecspi.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The i.MX6 supports 25SPI interfaces. Which have been enabled? */ + +#define __SPI1_NDX 0 + +#ifdef CONFIG_IMX6_ECSPI1 +# define SPI1_NDX __SPI1_NDX +# define __SPI1_PRESENT 1 +# define __SPI2_NDX (__SPI1_NDX + 1) +#else +# define __SPI1_PRESENT 0 +# define __SPI2_NDX __SPI1_NDX +#endif + +#ifdef CONFIG_IMX6_ECSPI2 +# define SPI2_NDX __SPI2_NDX +# define __SPI2_PRESENT 1 +# define __SPI3_NDX (__SPI2_NDX + 1) +#else +# define __SPI2_PRESENT 0 +# define __SPI3_NDX __SPI2_NDX +#endif + +#ifdef CONFIG_IMX6_ECSPI3 +# define SPI3_NDX __SPI3_NDX +# define __SPI3_PRESENT 1 +# define __SPI4_NDX (__SPI3_NDX + 1) +#else +# define __SPI3_PRESENT 0 +# define __SPI4_NDX __SPI3_NDX +#endif + +#ifdef CONFIG_IMX6_ECSPI4 +# define SPI4_NDX __SPI4_NDX +# define __SPI4_PRESENT 1 +# define __SPI5_NDX (__SPI4_NDX + 1) +#else +# define __SPI4_PRESENT 0 +# define __SPI5_NDX __SPI5_NDX +#endif + +#ifdef CONFIG_IMX6_ECSPI5 +# define SPI5_NDX __SPI5_NDX +# define __SPI5_PRESENT 1 +# define __SPI6_NDX (__SPI5_NDX + 1) +#else +# define __SPI5_PRESENT 0 +# define __SPI6_NDX __SPI5_NDX +#endif + +#define NSPIS (__SPI1_PRESENT + __SPI2_PRESENT + __SPI3_PRESENT + \ + __SPI4_PRESENT + __SPI5_PRESENT) + +/* Compile the rest of the file only if at least one SPI interface has been + * enabled. + */ + +#if NSPIS > 0 + +/* The number of words that will fit in the Tx FIFO */ + +#define IMX_TXFIFO_WORDS 8 + +/**************************************************************************** + * Private Type Definitions + ****************************************************************************/ + + /* Per SPI callouts to board-specific logic */ + +typedef CODE void (*imx_select_t)(FAR struct spi_dev_s *dev, + enum spi_dev_e devid, bool selected); +typedef CODE uint8_t (*imx_status_t)(FAR struct spi_dev_s *dev, + enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +typedef CODE int (*imx_cmddata_t)(FAR struct spi_dev_s *dev, + enum spi_dev_e devid, bool cmd); +#endif + +struct imx_spidev_s +{ + const struct spi_ops_s *ops; /* Common SPI operations */ +#ifndef CONFIG_SPI_POLLWAIT + sem_t waitsem; /* Wait for transfer to complete */ +#endif + sem_t exclsem; /* Supports mutually exclusive access */ + + /* These following are the source and destination buffers of the transfer. + * they are retained in this structure so that they will be accessible + * from an interrupt handler. The actual type of the buffer is uint8_t is + * nbits <=8 and uint16_t is nbits >8. + */ + + void *txbuffer; /* Source buffer */ + void *rxbuffer; /* Destination buffer */ + + /* These are functions pointers that are configured to perform the + * appropriate transfer for the particular kind of exchange that is + * occurring. Differnt functions may be selected depending on (1) + * if the tx or txbuffer is NULL and depending on the number of bits + * per word. + */ + + void (*txword)(struct imx_spidev_s *priv); + void (*rxword)(struct imx_spidev_s *priv); + + uint32_t base; /* SPI register base address */ + uint32_t frequency; /* Current desired SCLK frequency */ + uint32_t actual; /* Current actual SCLK frequency */ + + int ntxwords; /* Number of words left to transfer on the Tx FIFO */ + int nrxwords; /* Number of words received on the Rx FIFO */ + int nwords; /* Number of words to be exchanged */ + + uint8_t mode; /* Current mode */ + uint8_t nbits; /* Current number of bits per word */ + uint8_t spindx; /* SPI index */ +#ifndef CONFIG_SPI_POLLWAIT + uint8_t irq; /* SPI IRQ number */ + xcpt_t handler; /* ECSPI interrupt handler */ +#endif + + /* Per SPI callouts to board-specific logic */ + + imx_select_t select; /* Select callout */ + imx_status_t status; /* Status callout */ +#ifdef CONFIG_SPI_CMDDATA + imx_cmddata_t cmddata; /* Cmddata callout */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* SPI register access */ + +static inline uint32_t spi_getreg(struct imx_spidev_s *priv, unsigned int offset); +static inline void spi_putreg(struct imx_spidev_s *priv, unsigned int offset, uint32_t value); + +/* SPI data transfer */ + +static void spi_txnull(struct imx_spidev_s *priv); +static void spi_txuint16(struct imx_spidev_s *priv); +static void spi_txuint8(struct imx_spidev_s *priv); +static void spi_rxnull(struct imx_spidev_s *priv); +static void spi_rxuint16(struct imx_spidev_s *priv); +static void spi_rxuint8(struct imx_spidev_s *priv); +static int spi_performtx(struct imx_spidev_s *priv); +static inline void spi_performrx(struct imx_spidev_s *priv); +static int spi_transfer(struct imx_spidev_s *priv, const void *txbuffer, + void *rxbuffer, unsigned int nwords); + +/* Interrupt handling */ + +#ifndef CONFIG_SPI_POLLWAIT +static int spi_interrupt(struct imx_spidev_s *priv); +#ifdef CONFIG_IMX6_ECSPI1 +static int ecspi1_interrupt(int irq, void *context); +#endif +#ifdef CONFIG_IMX6_ECSPI2 +static int ecspi2_interrupt(int irq, void *context); +#endif +#ifdef CONFIG_IMX6_ECSPI3 +static int ecspi3_interrupt(int irq, void *context); +#endif +#ifdef CONFIG_IMX6_ECSPI4 +static int ecspi4_interrupt(int irq, void *context); +#endif +#ifdef CONFIG_IMX6_ECSPI5 +static int ecspi5_interrupt(int irq, void *context); +#endif +#endif + +/* SPI methods */ + +static int spi_lock(FAR struct spi_dev_s *dev, bool lock); +static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, + bool selected); +static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, + uint32_t frequency); +static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode); +static void spi_setbits(FAR struct spi_dev_s *dev, int nbits); +static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd); +static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#ifdef CONFIG_SPI_CMDDATA +static int spi_cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, + bool cmd); +#endif +#ifdef CONFIG_SPI_EXCHANGE +static void spi_exchange(FAR struct spi_dev_s *dev, + FAR const void *txbuffer, + FAR void *rxbuffer, size_t nwords); +#else +static void spi_sndblock(FAR struct spi_dev_s *dev, + FAR const void *buffer, size_t nwords); +static void spi_recvblock(FAR struct spi_dev_s *dev, + FAR void *buffer, size_t nwords); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Common SPI operations */ + +static const struct spi_ops_s g_spiops = +{ + .lock = spi_lock, + .select = spi_select, /* Provided externally by board logic */ + .setfrequency = spi_setfrequency, + .setmode = spi_setmode, + .setbits = spi_setbits, +#ifdef CONFIG_SPI_HWFEATURES + .hwfeatures = 0, /* Not supported */ +#endif + .status = spi_status, /* Provided externally by board logic */ +#ifdef CONFIG_SPI_CMDDATA + .cmddata = spi_cmddata, +#endif + .send = spi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = spi_exchange, +#else + .sndblock = spi_sndblock, + .recvblock = spi_recvblock, +#endif +}; + +/* This supports is up to five SPI busses/ports */ + +static struct imx_spidev_s g_spidev[] = +{ +#ifdef CONFIG_IMX6_ECSPI1 + { + .ops = &g_spiops, + .base = IMX_ECSPI1_VBASE, + .spindx = SPI1_NDX, +#ifndef CONFIG_SPI_POLLWAIT + .irq = IMX_IRQ_ECSPI1, + .handler = ecspi1_interrupt, +#endif + .select = imx_spi1select, + .status = imx_spi1status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = imx_spi1cmddata, +#endif + } +#endif + +#ifdef CONFIG_IMX6_ECSPI2 + , { + .ops = &g_spiops, + .base = IMX_ECSPI2_VBASE, + .spindx = SPI2_NDX, +#ifndef CONFIG_SPI_POLLWAIT + .irq = IMX_IRQ_ECSPI2, + .handler = ecspi2_interrupt, +#endif + .select = imx_spi2select, + .status = imx_spi2status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = imx_spi2cmddata, +#endif + } +#endif + +#ifdef CONFIG_IMX6_ECSPI3 + , { + .ops = &g_spiops, + .base = IMX_ECSPI3_VBASE, + .spindx = SPI3_NDX, +#ifndef CONFIG_SPI_POLLWAIT + .irq = IMX_IRQ_ECSPI3, + .handler = ecspi3_interrupt, +#endif + .select = imx_spi3select, + .status = imx_spi3status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = imx_spi3cmddata, +#endif + } +#endif + +#ifdef CONFIG_IMX6_ECSPI4 + , { + .ops = &g_spiops, + .base = IMX_ECSPI4_VBASE, + .spindx = SPI4_NDX, +#ifndef CONFIG_SPI_POLLWAIT + .irq = IMX_IRQ_ECSPI4, + .handler = ecspi4_interrupt, +#endif + .select = imx_spi4select, + .status = imx_spi4status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = imx_spi4cmddata, +#endif + } +#endif + +#ifdef CONFIG_IMX6_ECSPI5 + , { + .ops = &g_spiops, + .base = IMX_ECSPI5_VBASE, + .spindx = SPI5_NDX, +#ifndef CONFIG_SPI_POLLWAIT + .irq = IMX_IRQ_ECSPI5, + .handler = ecspi5_interrupt, +#endif + .select = imx_spi5select, + .status = imx_spi5status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = imx_spi5cmddata, +#endif + } +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: spi_getreg + * + * Description: + * Read the SPI register at this offeset + * + * Input Parameters: + * priv - Device-specific state data + * offset - Offset to the SPI register from the register base address + * + * Returned Value: + * Value of the register at this offset + * + ****************************************************************************/ + +static inline uint32_t spi_getreg(struct imx_spidev_s *priv, unsigned int offset) +{ + return getreg32(priv->base + offset); +} + +/**************************************************************************** + * Name: spi_putreg + * + * Description: + * Write the value to the SPI register at this offeset + * + * Input Parameters: + * priv - Device-specific state data + * offset - Offset to the SPI register from the register base address + * value - Value to write + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void spi_putreg(struct imx_spidev_s *priv, unsigned int offset, uint32_t value) +{ + putreg32(value, priv->base + offset); +} + +/**************************************************************************** + * Name: spi_txnull, spi_txuint16, and spi_txuint8 + * + * Description: + * Transfer all ones, a uint8_t, or uint16_t to Tx FIFO and update the txbuffer + * pointer appropriately. The selected function dependes on (1) if there + * is a source txbuffer provided, and (2) if the number of bits per + * word is <=8 or >8. + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void spi_txnull(struct imx_spidev_s *priv) +{ + spi_putreg(priv, ECSPI_TXDATA_OFFSET, 0xffff); +} + +static void spi_txuint16(struct imx_spidev_s *priv) +{ + uint16_t *ptr = (uint16_t *)priv->txbuffer; + spi_putreg(priv, ECSPI_TXDATA_OFFSET, *ptr++); + priv->txbuffer = (void *)ptr; +} + +static void spi_txuint8(struct imx_spidev_s *priv) +{ + uint8_t *ptr = (uint8_t *)priv->txbuffer; + spi_putreg(priv, ECSPI_TXDATA_OFFSET, *ptr++); + priv->txbuffer = (void *)ptr; +} + +/**************************************************************************** + * Name: spi_rxnull,spi_rxuint16, and spi_rxuint8 + * + * Description: + * Discard input, save a uint8_t, or or save a uint16_t from Tx FIFO in the + * user rxvbuffer and update the rxbuffer pointer appropriately. The + * selected function dependes on (1) if there is a desination rxbuffer + * provided, and (2) if the number of bits per word is <=8 or >8. + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void spi_rxnull(struct imx_spidev_s *priv) +{ + (void)spi_getreg(priv, ECSPI_RXDATA_OFFSET); +} + +static void spi_rxuint16(struct imx_spidev_s *priv) +{ + uint16_t *ptr = (uint16_t *)priv->rxbuffer; + *ptr++ = (uint16_t)spi_getreg(priv, ECSPI_TXDATA_OFFSET); + priv->rxbuffer = (void *)ptr; +} + +static void spi_rxuint8(struct imx_spidev_s *priv) +{ + uint8_t *ptr = (uint8_t *)priv->rxbuffer; + *ptr++ = (uint8_t)spi_getreg(priv, ECSPI_TXDATA_OFFSET); + priv->rxbuffer = (void *)ptr; +} + +/**************************************************************************** + * Name: spi_performtx + * + * Description: + * If the Tx FIFO is empty, then transfer as many words as we can to + * the FIFO. + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * The number of words written to the Tx FIFO (a value from 0 to 8, + * inclusive). + * + ****************************************************************************/ + +static int spi_performtx(struct imx_spidev_s *priv) +{ + uint32_t regval; + int ntxd = 0; /* Number of words written to Tx FIFO */ + + /* Check if the Tx FIFO is empty */ + + if ((spi_getreg(priv, ECSPI_STATREG_OFFSET) & ECSPI_INT_TE) != 0) + { + /* Check if all of the Tx words have been sent */ + + if (priv->ntxwords > 0) + { + /* No.. Transfer more words until either the TxFIFO is full or + * until all of the user provided data has been sent. + */ + + for (; ntxd < priv->ntxwords && ntxd < IMX_TXFIFO_WORDS; ntxd++) + { + priv->txword(priv); + } + + /* Update the count of words to to transferred */ + + priv->ntxwords -= ntxd; + } + else + { + /* Yes.. The transfer is complete, disable Tx FIFO empty interrupt */ + + regval = spi_getreg(priv, ECSPI_INTREG_OFFSET); + regval &= ~ECSPI_INT_TE; + spi_putreg(priv, ECSPI_INTREG_OFFSET, regval); + } + } + return ntxd; +} + +/**************************************************************************** + * Name: spi_performrx + * + * Description: + * Transfer as many bytes as possible from the Rx FIFO to the user Rx + * buffer (if one was provided). + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void spi_performrx(struct imx_spidev_s *priv) +{ + /* Loop while data is available in the Rx FIFO */ + + while ((spi_getreg(priv, ECSPI_STATREG_OFFSET) & ECSPI_INT_RR) != 0) + { + /* Have all of the requested words been transferred from the Rx FIFO? */ + + if (priv->nrxwords < priv->nwords) + { + /* No.. Read more data from Rx FIFO */ + + priv->rxword(priv); + priv->nrxwords++; + } + } +} + +/**************************************************************************** + * Name: spi_startxfr + * + * Description: + * If data was added to the Tx FIFO, then start the exchange + * + * Input Parameters: + * priv - Device-specific state data + * ntxd - The number of bytes added to the Tx FIFO by spi_performtx. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void spi_startxfr(struct imx_spidev_s *priv, int ntxd) +{ + uint32_t regval; + + /* The XCH bit initiates an exchange in master mode. It remains set + * remains set while the exchange is in progress but is automatically + * clear when all data in the Tx FIFO and shift register are shifted out. + * So if we have added data to the Tx FIFO on this interrupt, we must + * set the XCH bit to resume the exchange. + */ + + if (ntxd > 0) + { + regval = spi_getreg(priv, ECSPI_CONREG_OFFSET); + regval |= ECSPI_CONREG_XCH; + spi_putreg(priv, ECSPI_CONREG_OFFSET, regval); + } +} + +/**************************************************************************** + * Name: spi_transfer + * + * Description: + * Exchange a block data with the SPI device + * + * Input Parameters: + * priv - Device-specific state data + * txbuffer - The buffer of data to send to the device (may be NULL). + * rxbuffer - The buffer to receive data from the device (may be NULL). + * nwords - The total number of words to be exchanged. If the interface + * uses <= 8 bits per word, then this is the number of uint8_t's; + * if the interface uses >8 bits per word, then this is the + * number of uint16_t's + * + * Returned Value: + * 0: success, <0:Negated error number on failure + * + ****************************************************************************/ + +static int spi_transfer(struct imx_spidev_s *priv, const void *txbuffer, + void *rxbuffer, unsigned int nwords) +{ +#ifndef CONFIG_SPI_POLLWAIT + irqstate_t flags; + uint32_t regval; + int ret; +#endif + int ntxd; + + /* Set up to perform the transfer */ + + priv->txbuffer = (uint8_t *)txbuffer; /* Source buffer */ + priv->rxbuffer = (uint8_t *)rxbuffer; /* Destination buffer */ + priv->ntxwords = nwords; /* Number of words left to send */ + priv->nrxwords = 0; /* Number of words received */ + priv->nwords = nwords; /* Total number of exchanges */ + + /* Set up the low-level data transfer function pointers */ + + if (priv->nbits > 8) + { + priv->txword = spi_txuint16; + priv->rxword = spi_rxuint16; + } + else + { + priv->txword = spi_txuint8; + priv->rxword = spi_rxuint8; + } + + if (!txbuffer) + { + priv->txword = spi_txnull; + } + + if (!rxbuffer) + { + priv->rxword = spi_rxnull; + } + + /* Prime the Tx FIFO to start the sequence (saves one interrupt) */ + +#ifndef CONFIG_SPI_POLLWAIT + flags = enter_critical_section(); + ntxd = spi_performtx(priv); + spi_startxfr(priv, ntxd); + + /* Enable transmit empty interrupt */ + + regval = spi_getreg(priv, ECSPI_INTREG_OFFSET); + regval |= ECSPI_INT_TE; + spi_putreg(priv, ECSPI_INTREG_OFFSET, regval); + leave_critical_section(flags); + + /* Wait for the transfer to complete. Since there is no handshake + * with SPI, the following should complete even if there are problems + * with the transfer, so it should be safe with no timeout. + */ + + do + { + /* Wait to be signaled from the interrupt handler */ + + ret = sem_wait(&priv->waitsem); + } + while (ret < 0 && errno == EINTR); + +#else + /* Perform the transfer using polling logic. This will totally + * dominate the CPU until the transfer is complete. Only recommended + * if (1) your SPI is very fast, and (2) if you only use very short + * transfers. + */ + + do + { + /* Handle outgoing Tx FIFO transfers */ + + ntxd = spi_performtx(priv); + + /* Handle incoming Rx FIFO transfers */ + + spi_performrx(priv); + + /* Resume the transfer */ + + spi_startxfr(priv, ntxd); + + /* If there are other threads at this same priority level, + * the following may help: + */ + + sched_yield(); + } + while (priv->nrxwords < priv->nwords); +#endif + return OK; +} + +/**************************************************************************** + * Name: spi_interrupt + * + * Description: + * Common ECSPI interrupt handling logic + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * 0: success, <0:Negated error number on failure + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_POLLWAIT +static int spi_interrupt(struct imx_spidev_s *priv) +{ + int ntxd; + + DEBUGASSERT(priv != NULL); + + /* Handle outgoing Tx FIFO transfers */ + + ntxd = spi_performtx(priv); + + /* Handle incoming Rx FIFO transfers */ + + spi_performrx(priv); + + /* Resume the transfer */ + + spi_startxfr(priv, ntxd); + + /* Check if the transfer is complete */ + + if (priv->nrxwords >= priv->nwords) + { + /* Yes, wake up the waiting thread */ + + sem_post(&priv->waitsem); + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: ecspiN_interrupt, N=1..5 + * + * Description: + * Individual ECPSI interrupt handlers. + * + * Input Parameters: + * Standard interrupt handler inputs + * + * Returned Value: + * 0: success, <0:Negated error number on failure + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_POLLWAIT +#ifdef CONFIG_IMX6_ECSPI1 +static int ecspi1_interrupt(int irq, void *context) +{ + return spi_interrupt(&g_spidev[SPI1_NDX]); +} +#endif + +#ifdef CONFIG_IMX6_ECSPI2 +static int ecspi2_interrupt(int irq, void *context) +{ + return spi_interrupt(&g_spidev[SPI2_NDX]); +} +#endif + +#ifdef CONFIG_IMX6_ECSPI3 +static int ecspi3_interrupt(int irq, void *context) +{ + return spi_interrupt(&g_spidev[SPI3_NDX]); +} +#endif + +#ifdef CONFIG_IMX6_ECSPI4 +static int ecspi4_interrupt(int irq, void *context) +{ + return spi_interrupt(&g_spidev[SPI4_NDX]); +} +#endif + +#ifdef CONFIG_IMX6_ECSPI5 +static int ecspi5_interrupt(int irq, void *context) +{ + return spi_interrupt(&g_spidev[SPI5_NDX]); +} +#endif +#endif + +/**************************************************************************** + * Name: spi_lock + * + * Description: + * On SPI busses where there are multiple devices, it will be necessary to + * lock SPI to have exclusive access to the busses for a sequence of + * transfers. The bus should be locked before the chip is selected. After + * locking the SPI bus, the caller should then also call the setfrequency, + * setbits, and setmode methods to make sure that the SPI is properly + * configured for the device. If the SPI buss is being shared, then it + * may have been left in an incompatible state. + * + * Input Parameters: + * dev - Device-specific state data + * lock - true: Lock spi bus, false: unlock SPI bus + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int spi_lock(FAR struct spi_dev_s *dev, bool lock) +{ + struct imx_spidev_s *priv = (struct imx_spidev_s *)dev; + + if (lock) + { + /* Take the semaphore (perhaps waiting) */ + + while (sem_wait(&priv->exclsem) != 0) + { + /* The only case that an error should occur here is if the wait + * was awakened by a signal. + */ + + DEBUGASSERT(errno == EINTR); + } + } + else + { + (void)sem_post(&priv->exclsem); + } + + return OK; +} + +/**************************************************************************** + * Name: spi_select + * + * Description: + * Enable/disable the SPI chip select. The implementation of this method + * must include handshaking: If a device is selected, it must hold off + * all other attempts to select the device until the device is deselected. + * Required. + * + * Input Parameters: + * dev - Device-specific state data + * devid - Identifies the device to select + * selected - true: slave selected, false: slave de-selected + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, + bool selected) +{ + struct imx_spidev_s *priv = (struct imx_spidev_s *)dev; + + DEBUGASSERT(priv != NULL && priv->select != NULL); + priv->select(dev, devid, selected); +} + +/**************************************************************************** + * Name: spi_setfrequency + * + * Description: + * Set the SPI frequency. + * + * Input Parameters: + * dev - Device-specific state data + * frequency - The SPI frequency requested + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + +static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) +{ + struct imx_spidev_s *priv = (struct imx_spidev_s *)dev; + uint32_t actual; + + DEBUGASSERT(priv != NULL); + actual = priv->actual; + + if (frequency != priv->frequency) + { + uint32_t freqbits; + uint32_t regval; + + if (frequency >= IMX_PERCLK2_FREQ / 4) + { + freqbits = ECSPI_CONREG_DIV4; + actual = IMX_PERCLK2_FREQ / 4; + } + else if (frequency >= IMX_PERCLK2_FREQ / 8) + { + freqbits = ECSPI_CONREG_DIV8; + actual = IMX_PERCLK2_FREQ / 8; + } + else if (frequency >= IMX_PERCLK2_FREQ / 16) + { + freqbits = ECSPI_CONREG_DIV16; + actual = IMX_PERCLK2_FREQ / 16; + } + else if (frequency >= IMX_PERCLK2_FREQ / 32) + { + freqbits = ECSPI_CONREG_DIV32; + actual = IMX_PERCLK2_FREQ / 32; + } + else if (frequency >= IMX_PERCLK2_FREQ / 64) + { + freqbits = ECSPI_CONREG_DIV64; + actual = IMX_PERCLK2_FREQ / 64; + } + else if (frequency >= IMX_PERCLK2_FREQ / 128) + { + freqbits = ECSPI_CONREG_DIV128; + actual = IMX_PERCLK2_FREQ / 128; + } + else if (frequency >= IMX_PERCLK2_FREQ / 256) + { + freqbits = ECSPI_CONREG_DIV256; + actual = IMX_PERCLK2_FREQ / 256; + } + else /* if (frequency >= IMX_PERCLK2_FREQ / 512) */ + { + freqbits = ECSPI_CONREG_DIV512; + actual = IMX_PERCLK2_FREQ / 512; + } + + /* Then set the selected frequency */ + + regval = spi_getreg(priv, ECSPI_CONREG_OFFSET); + regval &= ~(ECSPI_CONREG_DATARATE_MASK); + regval |= freqbits; + spi_putreg(priv, ECSPI_CONREG_OFFSET, regval); + + priv->frequency = frequency; + priv->actual = actual; + } + + return actual; +} + +/**************************************************************************** + * Name: spi_setmode + * + * Description: + * Set the SPI mode. Optional. See enum spi_mode_e for mode definitions + * + * Input Parameters: + * dev - Device-specific state data + * mode - The SPI mode requested + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) +{ + struct imx_spidev_s *priv = (struct imx_spidev_s *)dev; + if (priv && mode != priv->mode) + { + uint32_t modebits; + uint32_t regval; + + /* Select the CTL register bits based on the selected mode */ + + switch (mode) + { + case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */ + modebits = 0; + break; + + case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */ + modebits = ECSPI_CONREG_PHA; + break; + + case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */ + modebits = ECSPI_CONREG_POL; + break; + + case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */ + modebits = ECSPI_CONREG_PHA | ECSPI_CONREG_POL; + break; + + default: + return; + } + + /* Then set the selected mode */ + + regval = spi_getreg(priv, ECSPI_CONREG_OFFSET); + regval &= ~(ECSPI_CONREG_PHA | ECSPI_CONREG_POL); + regval |= modebits; + spi_putreg(priv, ECSPI_CONREG_OFFSET, regval); + } +} + +/**************************************************************************** + * Name: spi_setbits + * + * Description: + * Set the number of bits per word. + * + * Input Parameters: + * dev - Device-specific state data + * nbits - The number of bits requests + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void spi_setbits(FAR struct spi_dev_s *dev, int nbits) +{ + struct imx_spidev_s *priv = (struct imx_spidev_s *)dev; + if (priv && nbits != priv->nbits && nbits > 0 && nbits <= 16) + { + uint32_t regval = spi_getreg(priv, ECSPI_CONREG_OFFSET); + regval &= ~ECSPI_CONREG_BITCOUNT_MASK; + regval |= ((nbits - 1) << ECSPI_CONREG_BITCOUNT_SHIFT); + spi_putreg(priv, ECSPI_CONREG_OFFSET, regval); + priv->nbits = nbits; + } +} + +/**************************************************************************** + * Name: spi_send + * + * Description: + * Exchange one word on SPI + * + * Input Parameters: + * dev - Device-specific state data + * wd - The word to send. the size of the data is determined by the + * number of bits selected for the SPI interface. + * + * Returned Value: + * response + * + ****************************************************************************/ + +static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd) +{ + struct imx_spidev_s *priv = (struct imx_spidev_s *)dev; + uint16_t response = 0; + + (void)spi_transfer(priv, &wd, &response, 1); + return response; +} + +/**************************************************************************** + * Name: spi_status + * + * Description: + * Get SPI/MMC status. Optional. + * + * Input Parameters: + * dev - Device-specific state data + * devid - Identifies the device to report status on + * + * Returned Value: + * Returns a bitset of status values (see SPI_STATUS_* defines) + * + ****************************************************************************/ + +static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +{ + struct imx_spidev_s *priv = (struct imx_spidev_s *)dev; + uint8_t ret = 0; + + DEBUGASSERT(priv != NULL); + + if (priv->status != NULL); + { + ret = priv->select(dev, devid); + } + + return ret; +} + +/**************************************************************************** + * Name: spi_cmddata + * + * Description: + * Some devices require and additional out-of-band bit to specify if the + * next word sent to the device is a command or data. This is typical, for + * example, in "9-bit" displays where the 9th bit is the CMD/DATA bit. + * This function provides selection of command or data. + * + * This "latches" the CMD/DATA state. It does not have to be called before + * every word is transferred; only when the CMD/DATA state changes. This + * method is required if CONFIG_SPI_CMDDATA is selected in the NuttX + * configuration + * + * Input Parameters: + * dev - Device-specific state data + * cmd - TRUE: The following word is a command; FALSE: the following words + * are data. + * + * Returned Value: + * OK unless an error occurs. Then a negated errno value is returned + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +static int spi_cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, + bool cmd) +{ + struct imx_spidev_s *priv = (struct imx_spidev_s *)dev; + int ret = -ENOSYS; + + DEBUGASSERT(priv != NULL); + + if (priv->cmddata != NULL); + { + ret = priv->cmddata(dev, devid, cmd); + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: SPI_EXCHANGE + * + * Description: + * Exahange a block of data from SPI. Required. + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to the buffer in which to recieve data + * nwords - the length of data that to be exchanged in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_EXCHANGE +static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, + FAR void *rxbuffer, size_t nwords) +{ + struct imx_spidev_s *priv = (struct imx_spidev_s *)dev; + (void)spi_transfer(priv, txbuffer, rxbuffer, nwords); +} +#endif + +/**************************************************************************** + * Name: spi_sndblock + * + * Description: + * Send a block of data on SPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer of data to be sent + * nwords - the length of data to send from the buffer in number of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords) +{ + struct imx_spidev_s *priv = (struct imx_spidev_s *)dev; + (void)spi_transfer(priv, buffer, NULL, nwords); +} +#endif + +/**************************************************************************** + * Name: spi_recvblock + * + * Description: + * Revice a block of data from SPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer in which to recieve data + * nwords - the length of data that can be received in the buffer in number + * of words. The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords) +{ + struct imx_spidev_s *priv = (struct imx_spidev_s *)dev; + (void)spi_transfer(priv, NULL, buffer, nwords); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx_spibus_initialize + * + * Description: + * Initialize common parts the selected SPI port. Initialization of + * chip select GPIOs must have been performed by board specific logic + * prior to calling this function. Specifically: GPIOs should have + * been configured for output, and all chip selects disabled. + * + * One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select. However, + * If multiple devices on on the bus, then multiple chip selects will be + * required. Theregore, all GPIO chip management is deferred to board- + * specific logic. + * + * Input Parameter: + * Port number (for hardware that has mutiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structre reference on succcess; a NULL on failure + * + ****************************************************************************/ + +FAR struct spi_dev_s *imx_spibus_initialize(int port) +{ + struct imx_spidev_s *priv; + uint8_t regval; + + /* Only the SPI1 interface is supported */ + + switch (port) + { +#ifdef CONFIG_IMX6_ECSPI1 + case 1: + /* Select SPI1 */ + + priv = &g_spidev[SPI1_NDX]; + + /* Configure SPI1 GPIOs (NOTE that SS is not initialized here, the + * logic in this file makes no assumptions about chip select) + */ + + imxgpio_configpfinput(GPIOC, 13); /* Port C, pin 13: RDY */ + imxgpio_configpfoutput(GPIOC, 14); /* Port C, pin 14: SCLK */ + imxgpio_configpfinput(GPIOC, 16); /* Port C, pin 16: MISO */ + imxgpio_configpfoutput(GPIOC, 17); /* Port C, pin 17: MOSI */ + break; +#endif /* CONFIG_IMX6_ECSPI1 */ + +#ifdef CONFIG_IMX6_ECSPI2 + case 2: + /* Select SPI2 */ + + priv = &g_spidev[SPI2_NDX]; + + /* Configure SPI2 GPIOs */ + /* SCLK: AIN of Port A, pin 0 -OR- AIN of Port D, pin 7 */ + +#if 1 + imxgpio_configoutput(GPIOA, 0); /* Set GIUS=1 OCR=0 DIR=OUT */ +#else + imxgpio_configoutput(GPIOD, 7); /* Set GIUS=1 OCR=0 DIR=OUT */ +#endif + + /* SS: AIN of Port A, pin 17 -OR- AIN of Port D, pin 8.(NOTE that SS + * is not initialized here, the logic in this file makes no assumptions + * about chip select) + */ + + /* RXD: AOUT of Port A, pin 1 -OR- AOUT of Port D, pin 9 */ + +#if 1 + imxgpio_configinput(GPIOA, 1); /* Set GIUS=1 OCR=0 DIR=IN */ + + /* Select input from SPI2_RXD_0 pin (AOUT Port A, pin 1) */ + + regval = getreg32(IMX_SC_FMCR); + regval &= ~FMCR_SPI2_RXDSEL; + putreg32(regval, IMX_SC_FMCR); +#else + imxgpio_configinput(GPIOD, 9); /* Set GIUS=1 OCR=0 DIR=IN */ + + /* Select input from SPI2_RXD_1 pin (AOUT Port D, pin 9) */ + + regval = getreg32(IMX_SC_FMCR); + regval |= FMCR_SPI2_RXDSEL; + putreg32(regval, IMX_SC_FMCR); +#endif + + /* TXD: BIN of Port D, pin 31 -OR- AIN of Port D, pin 10 */ + +#if 1 + imxgpio_configinput(GPIOD, 31); + imxgpio_ocrbin(GPIOD, 31); + imxgpio_dirout(GPIOD, 31); +#else + imxgpio_configoutput(GPIOD, 10); +#endif + break; +#endif /* CONFIG_IMX6_ECSPI2 */ + + default: + return NULL; + } + + /* Initialize the state structure */ + /* Initialize Semaphores */ + +#ifndef CONFIG_SPI_POLLWAIT + /* Initialize the semaphore that is used to wake up the waiting + * thread when the DMA transfer completes. This semaphore is used for + * signaling and, hence, should not have priority inheritance enabled. + */ + + sem_init(&priv->waitsem, 0, 0); + sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE); +#endif + sem_init(&priv->exclsem, 0, 1); + + /* Initialize control register: min frequency, ignore ready, master mode, mode=0, 8-bit */ + + spi_putreg(priv, ECSPI_CONREG_OFFSET, + ECSPI_CONREG_DIV512 | /* Lowest frequency */ + ECSPI_CONREG_DRCTL_IGNRDY | /* Ignore ready */ + ECSPI_CONREG_MODE | /* Master mode */ + (7 << ECSPI_CONREG_BITCOUNT_SHIFT)); /* 8-bit data */ + + /* Make sure state agrees with data */ + + priv->mode = SPIDEV_MODE0; + priv->nbits = 8; + + /* Set the initial clock frequency for identification mode < 400kHz */ + + spi_setfrequency((FAR struct spi_dev_s *)priv, 400000); + + /* Enable interrupts on data ready (and certain error conditions */ + +#ifndef CONFIG_SPI_POLLWAIT + spi_putreg(priv, ECSPI_INTREG_OFFSET, + ECSPI_INT_RR | /* RXFIFO Data Ready Interrupt Enable */ + ECSPI_INT_RO | /* RXFIFO Overflow Interrupt Enable */ + ECSPI_INT_BO); /* Bit Count Overflow Interrupt Enable */ +#else + spi_putreg(priv, ECSPI_INTREG_OFFSET, 0); /* No interrupts */ +#endif + + /* Set the clock source=bit clock and number of clocks inserted between + * transactions = 2. + */ + + spi_putreg(priv, ECSPI_PERIODREG_OFFSET, 2); + + /* No DMA */ + + spi_putreg(priv, ECSPI_DMAREG_OFFSET, 0); + + /* Attach the interrupt */ + +#ifndef CONFIG_SPI_POLLWAIT + DEBUGVERIFY(irq_attach(priv->irq, priv->handler)); +#endif + + /* Enable SPI */ + + regval = spi_getreg(priv, ECSPI_CONREG_OFFSET); + regval |= ECSPI_CONREG_SPIEN; + spi_putreg(priv, ECSPI_CONREG_OFFSET, regval); + + /* Enable SPI interrupts */ + +#ifndef CONFIG_SPI_POLLWAIT + up_enable_irq(priv->irq); +#endif + return (FAR struct spi_dev_s *)priv; +} + +#endif /* NSPIS > 0 */ -- GitLab From f7d8bbfa3bf2bf17a0b3cdd60ffb3a6c459bd447 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 2 Dec 2016 13:54:01 -0600 Subject: [PATCH 574/734] Update README. --- configs/sabre-6quad/README.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/sabre-6quad/README.txt b/configs/sabre-6quad/README.txt index 0de45c795a..ab4d4b5fa0 100644 --- a/configs/sabre-6quad/README.txt +++ b/configs/sabre-6quad/README.txt @@ -115,6 +115,9 @@ Status 2016-11-28: SMP is unusable until the SCU cache coherency logic is fixed. I do not know how to do that now. +2016-12-01: I committed a completely untest SPI driver. This was taken + directly from the i.MX1 and is most certainly not ready for use yet. + Platform Features ================= -- GitLab From 1851e9e837db6775288346f2ed646e08205f9bae Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 2 Dec 2016 16:36:27 -0600 Subject: [PATCH 575/734] SAMA5D3: Add support for CONFIG_NET_NOINTS to EMACA and GMAC driver. --- TODO | 6 +- arch/arm/src/sama5/Kconfig | 40 ++ arch/arm/src/sama5/sam_emaca.c | 461 ++++++++++++++++++++-- arch/arm/src/sama5/sam_gmac.c | 461 ++++++++++++++++++++-- configs/sama5d3-xplained/bridge/defconfig | 14 +- 5 files changed, 891 insertions(+), 91 deletions(-) diff --git a/TODO b/TODO index cdb5fc5a1c..2f930f21b1 100644 --- a/TODO +++ b/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated November 22, 2016) +NuttX TODO List (Last updated December 2, 2016) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with @@ -1067,9 +1067,9 @@ o Network (net/, drivers/net) PIC32 NO NO SAM3/4 YES YES SAMA5D ----------------------- ------ - EMACA NO YES (not tested) + EMACA YES YES (not tested) EMACB YES YES - GMAC NO YES (not tested) + GMAC YES YES (not tested) SAMV7 YES YES SIM N/A (No interrupts) NO diff --git a/arch/arm/src/sama5/Kconfig b/arch/arm/src/sama5/Kconfig index 1400aea5c9..d4ccc256be 100644 --- a/arch/arm/src/sama5/Kconfig +++ b/arch/arm/src/sama5/Kconfig @@ -1437,6 +1437,26 @@ config SAMA5_GMAC_NBC ---help--- Select to disable receipt of broadcast packets. +choice + prompt "Work queue" + default SAMA5_GMAC_LPWORK if SCHED_LPWORK + default SAMA5_GMAC_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + depends on SCHED_WORKQUEUE + ---help--- + Work queue support is required to use the Ethernet driver. If the + low priority work queue is available, then it should be used by the + driver. + +config SAMA5_GMAC_HPWORK + bool "High priority" + depends on SCHED_HPWORK + +config SAMA5_GMAC_LPWORK + bool "Low priority" + depends on SCHED_LPWORK + +endchoice # Work queue + config SAMA5_GMAC_PHYADDR int "PHY address" default 1 @@ -1675,6 +1695,26 @@ config SAMA5_EMACA_NBC ---help--- Select to disable receipt of broadcast packets. +choice + prompt "Work queue" + default SAMA5_EMACA_LPWORK if SCHED_LPWORK + default SAMA5_EMACA_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + depends on SCHED_WORKQUEUE + ---help--- + Work queue support is required to use the Ethernet driver. If the + low priority work queue is available, then it should be used by the + driver. + +config SAMA5_EMACA_HPWORK + bool "High priority" + depends on SCHED_HPWORK + +config SAMA5_EMACA_LPWORK + bool "Low priority" + depends on SCHED_LPWORK + +endchoice # Work queue + config SAMA5_EMACA_REGDEBUG bool "Register-Level Debug" default n diff --git a/arch/arm/src/sama5/sam_emaca.c b/arch/arm/src/sama5/sam_emaca.c index 67715ee204..c31ae128f8 100644 --- a/arch/arm/src/sama5/sam_emaca.c +++ b/arch/arm/src/sama5/sam_emaca.c @@ -4,7 +4,7 @@ * 10/100 Base-T Ethernet driver for the SAMA5D3. Denoted as 'A' to * distinguish it from the SAMA5D4 EMAC driver. * - * Copyright (C) 2013-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: @@ -65,6 +65,11 @@ #include #include #include + +#ifdef CONFIG_NET_NOINTS +# include +#endif + #include #include #include @@ -94,6 +99,26 @@ ****************************************************************************/ /* Configuration ************************************************************/ +/* If processing is not done at the interrupt level, then work queue support + * is required. + */ + +#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required +#endif + +/* Select work queue */ + +#if defined(CONFIG_SCHED_WORKQUEUE) +# if defined(CONFIG_SAMA5_EMACA_HPWORK) +# define ETHWORK HPWORK +# elif defined(CONFIG_SAMA5_EMACA_LPWORK) +# define ETHWORK LPWORK +# else +# error Neither CONFIG_SAMA5_EMACA_HPWORK nor CONFIG_SAMA5_EMACA_LPWORK defined +# endif +#endif + /* Number of buffers for RX */ #ifndef CONFIG_SAMA5_EMAC_NRXBUFFERS @@ -255,6 +280,9 @@ struct sam_emac_s uint8_t ifup : 1; /* true:ifup false:ifdown */ WDOG_ID txpoll; /* TX poll timer */ WDOG_ID txtimeout; /* TX timeout timer */ +#ifdef CONFIG_NET_NOINTS + struct work_s work; /* For deferring work to the work queue */ +#endif /* This holds the information visible to the NuttX network */ @@ -363,17 +391,35 @@ static void sam_dopoll(struct sam_emac_s *priv); static int sam_recvframe(struct sam_emac_s *priv); static void sam_receive(struct sam_emac_s *priv); static void sam_txdone(struct sam_emac_s *priv); +static inline void sam_interrupt_process(FAR struct sam_emac_s *priv); +#ifdef CONFIG_NET_NOINTS +static void sam_interrupt_work(FAR void *arg); +#endif static int sam_emac_interrupt(int irq, void *context); /* Watchdog timer expirations */ -static void sam_polltimer(int argc, uint32_t arg, ...); -static void sam_txtimeout(int argc, uint32_t arg, ...); +static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv); +#ifdef CONFIG_NET_NOINTS +static void sam_txtimeout_work(FAR void *arg); +#endif +static void sam_txtimeout_expiry(int argc, uint32_t arg, ...); + +static inline void sam_poll_process(FAR struct sam_emac_s *priv); +#ifdef CONFIG_NET_NOINTS +static void sam_poll_work(FAR void *arg); +#endif +static void sam_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ static int sam_ifup(struct net_driver_s *dev); static int sam_ifdown(struct net_driver_s *dev); + +static inline void sam_txavail_process(FAR struct sam_emac_s *priv); +#ifdef CONFIG_NET_NOINTS +static void sam_txavail_work(FAR void *arg); +#endif static int sam_txavail(struct net_driver_s *dev); #if defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_ICMPv6) @@ -788,7 +834,7 @@ static int sam_transmit(struct sam_emac_s *priv) /* Setup the TX timeout watchdog (perhaps restarting the timer) */ - (void)wd_start(priv->txtimeout, SAM_TXTIMEOUT, sam_txtimeout, 1, + (void)wd_start(priv->txtimeout, SAM_TXTIMEOUT, sam_txtimeout_expiry, 1, (uint32_t)priv); /* Set d_len to zero meaning that the d_buf[] packet buffer is again @@ -903,7 +949,7 @@ static int sam_txpoll(struct net_driver_s *dev) * * 1. After completion of a transmission (sam_txdone), * 2. When new TX data is available (sam_txavail), and - * 3. After a TX timeout to restart the sending process (sam_txtimeout). + * 3. After a TX timeout to restart the sending process (sam_txtimeout_expiry). * * Parameters: * priv - Reference to the driver state structure @@ -1416,25 +1462,25 @@ static void sam_txdone(struct sam_emac_s *priv) } /**************************************************************************** - * Function: sam_emac_interrupt + * Function: sam_interrupt_process * * Description: - * Hardware interrupt handler + * Interrupt processing. This may be performed either within the interrupt + * handler or on the worker thread, depending upon the configuration * * Parameters: - * irq - Number of the IRQ that generated the interrupt - * context - Interrupt register state save info (architecture-specific) + * priv - Reference to the driver state structure * * Returned Value: - * OK on success + * None * * Assumptions: + * Ethernet interrupts are disabled * ****************************************************************************/ -static int sam_emac_interrupt(int irq, void *context) +static inline void sam_interrupt_process(FAR struct sam_emac_s *priv) { - struct sam_emac_s *priv = &g_emac; uint32_t isr; uint32_t rsr; uint32_t tsr; @@ -1597,20 +1643,128 @@ static int sam_emac_interrupt(int irq, void *context) nwarn("WARNING: Pause TO!\n"); } #endif +} + +/**************************************************************************** + * Function: sam_interrupt_work + * + * Description: + * Perform interrupt related work from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() was called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * Ethernet interrupts are disabled + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void sam_interrupt_work(FAR void *arg) +{ + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; + net_lock_t state; + + /* Process pending Ethernet interrupts */ + + state = net_lock(); + sam_interrupt_process(priv); + net_unlock(state); + + /* Re-enable Ethernet interrupts */ + + up_enable_irq(SAM_IRQ_EMAC); +} +#endif + +/**************************************************************************** + * Function: sam_emac_interrupt + * + * Description: + * Hardware interrupt handler + * + * Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * OK on success + * + * Assumptions: + * + ****************************************************************************/ + +static int sam_emac_interrupt(int irq, void *context) +{ + struct sam_emac_s *priv = &g_emac; +#ifdef CONFIG_NET_NOINTS + uint32_t tsr; + + /* Disable further Ethernet interrupts. Because Ethernet interrupts are + * also disabled if the TX timeout event occurs, there can be no race + * condition here. + */ + + up_disable_irq(SAM_IRQ_EMAC); + + /* Check for the completion of a transmission. Careful: + * + * ISR:TCOMP is set when a frame has been transmitted. Cleared on read (so + * we cannot read it here). + * TSR:TXCOMP is set when a frame has been transmitted. Cleared by writing a + * one to this bit. + */ + + tsr = sam_getreg(priv, SAM_EMAC_TSR_OFFSET); + if ((tsr & EMAC_TSR_COMP) != 0) + { + /* If a TX transfer just completed, then cancel the TX timeout so + * there will be do race condition between any subsequent timeout + * expiration and the deferred interrupt processing. + */ + + wd_cancel(priv->txtimeout); + + /* Make sure that the TX poll timer is running (if it is already + * running, the following would restart it). This is necessary to + * avoid certain race conditions where the polling sequence can be + * interrupted. + */ + + (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, priv); + } + + /* Cancel any pending poll work */ + + work_cancel(ETHWORK, &priv->work); + + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->work, sam_interrupt_work, priv, 0); + +#else + /* Process the interrupt now */ + + sam_interrupt_process(priv); +#endif return OK; } /**************************************************************************** - * Function: sam_txtimeout + * Function: sam_txtimeout_process * * Description: - * Our TX watchdog timed out. Called from the timer interrupt handler. - * The last TX never completed. Reset the hardware and start again. + * Process a TX timeout. Called from the either the watchdog timer + * expiration logic or from the worker thread, depending upon the + * configuration. The timeout means that the last TX never completed. + * Reset the hardware and start again. * * Parameters: - * argc - The number of available arguments - * arg - The first argument + * priv - Reference to the driver state structure * * Returned Value: * None @@ -1620,15 +1774,11 @@ static int sam_emac_interrupt(int irq, void *context) * ****************************************************************************/ -static void sam_txtimeout(int argc, uint32_t arg, ...) +static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv) { - struct sam_emac_s *priv = (struct sam_emac_s *)arg; - nerr("ERROR: Timeout!\n"); - /* Then reset the hardware. Just take the interface down, then back - * up again. - */ + /* Reset the hardware. Just take the interface down, then back up again. */ sam_ifdown(&priv->dev); sam_ifup(&priv->dev); @@ -1639,10 +1789,42 @@ static void sam_txtimeout(int argc, uint32_t arg, ...) } /**************************************************************************** - * Function: sam_polltimer + * Function: sam_txtimeout_work * * Description: - * Periodic timer handler. Called from the timer interrupt handler. + * Perform TX timeout related work from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * Ethernet interrupts are disabled + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void sam_txtimeout_work(FAR void *arg) +{ + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; + net_lock_t state; + + /* Process pending Ethernet interrupts */ + + state = net_lock(); + sam_txtimeout_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: sam_txtimeout_expiry + * + * Description: + * Our TX watchdog timed out. Called from the timer interrupt handler. + * The last TX never completed. Reset the hardware and start again. * * Parameters: * argc - The number of available arguments @@ -1656,10 +1838,54 @@ static void sam_txtimeout(int argc, uint32_t arg, ...) * ****************************************************************************/ -static void sam_polltimer(int argc, uint32_t arg, ...) +static void sam_txtimeout_expiry(int argc, uint32_t arg, ...) { - struct sam_emac_s *priv = (struct sam_emac_s *)arg; - struct net_driver_s *dev = &priv->dev; + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; + +#ifdef CONFIG_NET_NOINTS + /* Disable further Ethernet interrupts. This will prevent some race + * conditions with interrupt work. There is still a potential race + * condition with interrupt work that is already queued and in progress. + */ + + up_disable_irq(SAM_IRQ_EMAC); + + /* Cancel any pending poll or interrupt work. This will have no effect + * on work that has already been started. + */ + + work_cancel(ETHWORK, &priv->work); + + /* Schedule to perform the TX timeout processing on the worker thread. */ + + work_queue(ETHWORK, &priv->work, sam_txtimeout_work, priv, 0); +#else + /* Process the timeout now */ + + sam_txtimeout_process(priv); +#endif +} + +/**************************************************************************** + * Function: sam_poll_process + * + * Description: + * Perform the periodic poll. This may be called either from watchdog + * timer logic or from the worker thread, depending upon the configuration. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static inline void sam_poll_process(FAR struct sam_emac_s *priv) +{ + struct net_driver_s *dev = &priv->dev; /* Check if the there are any free TX descriptors. We cannot perform the * TX poll if we do not have buffering for another packet. @@ -1674,7 +1900,87 @@ static void sam_polltimer(int argc, uint32_t arg, ...) /* Setup the watchdog poll timer again */ - (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_polltimer, 1, arg); + (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, priv); +} + +/**************************************************************************** + * Function: sam_poll_work + * + * Description: + * Perform periodic polling from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * Ethernet interrupts are disabled + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void sam_poll_work(FAR void *arg) +{ + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; + net_lock_t state; + + /* Perform the poll */ + + state = net_lock(); + sam_poll_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: sam_poll_expiry + * + * Description: + * Periodic timer handler. Called from the timer interrupt handler. + * + * Parameters: + * argc - The number of available arguments + * arg - The first argument + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * + ****************************************************************************/ + +static void sam_poll_expiry(int argc, uint32_t arg, ...) +{ + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; + +#ifdef CONFIG_NET_NOINTS + /* Is our single work structure available? It may not be if there are + * pending interrupt actions. + */ + + if (work_available(&priv->work)) + { + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->work, sam_poll_work, priv, 0); + } + else + { + /* No.. Just re-start the watchdog poll timer, missing one polling + * cycle. + */ + + (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, arg); + } + +#else + /* Process the interrupt now */ + + sam_poll_process(priv); +#endif } /**************************************************************************** @@ -1745,7 +2051,7 @@ static int sam_ifup(struct net_driver_s *dev) /* Set and activate a timer process */ - (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_polltimer, 1, (uint32_t)priv); + (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (uint32_t)priv); /* Enable the EMAC interrupt */ @@ -1801,6 +2107,68 @@ static int sam_ifdown(struct net_driver_s *dev) return OK; } +/**************************************************************************** + * Function: sam_txavail_process + * + * Description: + * Perform an out-of-cycle poll. + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static inline void sam_txavail_process(FAR struct sam_emac_s *priv) +{ + ninfo("ifup: %d\n", priv->ifup); + + /* Ignore the notification if the interface is not yet up */ + + if (priv->ifup) + { + /* Poll the network for new XMIT data */ + + sam_dopoll(priv); + } +} + +/**************************************************************************** + * Function: sam_txavail_work + * + * Description: + * Perform an out-of-cycle poll on the worker thread. + * + * Parameters: + * arg - Reference to the NuttX driver state structure (cast to void*) + * + * Returned Value: + * None + * + * Assumptions: + * Called on the higher priority worker thread. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void sam_txavail_work(FAR void *arg) +{ + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; + net_lock_t state; + + /* Perform the poll */ + + state = net_lock(); + sam_txavail_process(priv); + net_unlock(state); +} +#endif + /**************************************************************************** * Function: sam_txavail * @@ -1810,7 +2178,7 @@ static int sam_ifdown(struct net_driver_s *dev) * latency. * * Parameters: - * dev - Reference to the NuttX driver state structure + * dev - Reference to the NuttX driver state structure * * Returned Value: * None @@ -1822,10 +2190,23 @@ static int sam_ifdown(struct net_driver_s *dev) static int sam_txavail(struct net_driver_s *dev) { - struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private; - irqstate_t flags; + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)dev->d_private; - ninfo("ifup: %d\n", priv->ifup); +#ifdef CONFIG_NET_NOINTS + /* Is our single work structure available? It may not be if there are + * pending interrupt actions and we will have to ignore the Tx + * availability action. + */ + + if (work_available(&priv->work)) + { + /* Schedule to serialize the poll on the worker thread. */ + + work_queue(ETHWORK, &priv->work, sam_txavail_work, priv, 0); + } + +#else + irqstate_t flags; /* Disable interrupts because this function may be called from interrupt * level processing. @@ -1833,16 +2214,12 @@ static int sam_txavail(struct net_driver_s *dev) flags = enter_critical_section(); - /* Ignore the notification if the interface is not yet up */ - - if (priv->ifup) - { - /* Poll the network for new XMIT data */ - - sam_dopoll(priv); - } + /* Perform the out-of-cycle poll now */ + sam_txavail_process(priv); leave_critical_section(flags); +#endif + return OK; } diff --git a/arch/arm/src/sama5/sam_gmac.c b/arch/arm/src/sama5/sam_gmac.c index d264282117..d3450dc2be 100644 --- a/arch/arm/src/sama5/sam_gmac.c +++ b/arch/arm/src/sama5/sam_gmac.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/sama5/sam_gmac.c * - * Copyright (C) 2013-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * References: @@ -62,6 +62,11 @@ #include #include #include + +#ifdef CONFIG_NET_NOINTS +# include +#endif + #include #include #include @@ -91,6 +96,26 @@ ****************************************************************************/ /* Configuration ************************************************************/ +/* If processing is not done at the interrupt level, then work queue support + * is required. + */ + +#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required +#endif + +/* Select work queue */ + +#if defined(CONFIG_SCHED_WORKQUEUE) +# if defined(CONFIG_SAMA5_GMAC_HPWORK) +# define ETHWORK HPWORK +# elif defined(CONFIG_SAMA5_GMAC_LPWORK) +# define ETHWORK LPWORK +# else +# error Neither CONFIG_SAMA5_GMAC_HPWORK nor CONFIG_SAMA5_GMAC_LPWORK defined +# endif +#endif + /* Number of buffer for RX */ #ifndef CONFIG_SAMA5_GMAC_NRXBUFFERS @@ -181,6 +206,9 @@ struct sam_gmac_s uint8_t ifup : 1; /* true:ifup false:ifdown */ WDOG_ID txpoll; /* TX poll timer */ WDOG_ID txtimeout; /* TX timeout timer */ +#ifdef CONFIG_NET_NOINTS + struct work_s work; /* For deferring work to the work queue */ +#endif /* This holds the information visible to the NuttX network */ @@ -288,17 +316,35 @@ static void sam_dopoll(struct sam_gmac_s *priv); static int sam_recvframe(struct sam_gmac_s *priv); static void sam_receive(struct sam_gmac_s *priv); static void sam_txdone(struct sam_gmac_s *priv); +static inline void sam_interrupt_process(FAR struct sam_gmac_s *priv); +#ifdef CONFIG_NET_NOINTS +static void sam_interrupt_work(FAR void *arg); +#endif static int sam_gmac_interrupt(int irq, void *context); /* Watchdog timer expirations */ -static void sam_polltimer(int argc, uint32_t arg, ...); -static void sam_txtimeout(int argc, uint32_t arg, ...); +static inline void sam_txtimeout_process(FAR struct sam_gmac_s *priv); +#ifdef CONFIG_NET_NOINTS +static void sam_txtimeout_work(FAR void *arg); +#endif +static void sam_txtimeout_expiry(int argc, uint32_t arg, ...); + +static inline void sam_poll_process(FAR struct sam_gmac_s *priv); +#ifdef CONFIG_NET_NOINTS +static void sam_poll_work(FAR void *arg); +#endif +static void sam_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ static int sam_ifup(struct net_driver_s *dev); static int sam_ifdown(struct net_driver_s *dev); + +static inline void sam_txavail_process(FAR struct sam_gmac_s *priv); +#ifdef CONFIG_NET_NOINTS +static void sam_txavail_work(FAR void *arg); +#endif static int sam_txavail(struct net_driver_s *dev); #if defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_ICMPv6) @@ -720,7 +766,7 @@ static int sam_transmit(struct sam_gmac_s *priv) /* Setup the TX timeout watchdog (perhaps restarting the timer) */ - (void)wd_start(priv->txtimeout, SAM_TXTIMEOUT, sam_txtimeout, 1, + (void)wd_start(priv->txtimeout, SAM_TXTIMEOUT, sam_txtimeout_expiry, 1, (uint32_t)priv); /* Set d_len to zero meaning that the d_buf[] packet buffer is again @@ -835,7 +881,7 @@ static int sam_txpoll(struct net_driver_s *dev) * * 1. After completion of a transmission (sam_txdone), * 2. When new TX data is available (sam_txavail), and - * 3. After a TX timeout to restart the sending process (sam_txtimeout). + * 3. After a TX timeout to restart the sending process (sam_txtimeout_expiry). * * Parameters: * priv - Reference to the driver state structure @@ -1344,25 +1390,25 @@ static void sam_txdone(struct sam_gmac_s *priv) } /**************************************************************************** - * Function: sam_gmac_interrupt + * Function: sam_interrupt_process * * Description: - * Hardware interrupt handler + * Interrupt processing. This may be performed either within the interrupt + * handler or on the worker thread, depending upon the configuration * * Parameters: - * irq - Number of the IRQ that generated the interrupt - * context - Interrupt register state save info (architecture-specific) + * priv - Reference to the driver state structure * * Returned Value: - * OK on success + * None * * Assumptions: + * Ethernet interrupts are disabled * ****************************************************************************/ -static int sam_gmac_interrupt(int irq, void *context) +static inline void sam_interrupt_process(FAR struct sam_gmac_s *priv) { - struct sam_gmac_s *priv = &g_gmac; uint32_t isr; uint32_t rsr; uint32_t tsr; @@ -1549,20 +1595,128 @@ static int sam_gmac_interrupt(int irq, void *context) nwarn("WARNING: Pause TO!\n"); } #endif +} + +/**************************************************************************** + * Function: sam_interrupt_work + * + * Description: + * Perform interrupt related work from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() was called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * Ethernet interrupts are disabled + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void sam_interrupt_work(FAR void *arg) +{ + FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg; + net_lock_t state; + + /* Process pending Ethernet interrupts */ + + state = net_lock(); + sam_interrupt_process(priv); + net_unlock(state); + + /* Re-enable Ethernet interrupts */ + + up_enable_irq(SAM_IRQ_GMAC); +} +#endif + +/**************************************************************************** + * Function: sam_gmac_interrupt + * + * Description: + * Hardware interrupt handler + * + * Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * OK on success + * + * Assumptions: + * + ****************************************************************************/ + +static int sam_gmac_interrupt(int irq, void *context) +{ + struct sam_gmac_s *priv = &g_gmac; +#ifdef CONFIG_NET_NOINTS + uint32_t tsr; + + /* Disable further Ethernet interrupts. Because Ethernet interrupts are + * also disabled if the TX timeout event occurs, there can be no race + * condition here. + */ + + up_disable_irq(SAM_IRQ_GMAC); + + /* Check for the completion of a transmission. Careful: + * + * ISR:TCOMP is set when a frame has been transmitted. Cleared on read (so + * we cannot read it here). + * TSR:TXCOMP is set when a frame has been transmitted. Cleared by writing a + * one to this bit. + */ + + tsr = sam_getreg(priv, SAM_GMAC_TSR_OFFSET); + if ((tsr & GMAC_TSR_TXCOMP) != 0) + { + /* If a TX transfer just completed, then cancel the TX timeout so + * there will be do race condition between any subsequent timeout + * expiration and the deferred interrupt processing. + */ + + wd_cancel(priv->txtimeout); + + /* Make sure that the TX poll timer is running (if it is already + * running, the following would restart it). This is necessary to + * avoid certain race conditions where the polling sequence can be + * interrupted. + */ + + (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, priv); + } + + /* Cancel any pending poll work */ + + work_cancel(ETHWORK, &priv->work); + + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->work, sam_interrupt_work, priv, 0); + +#else + /* Process the interrupt now */ + + sam_interrupt_process(priv); +#endif return OK; } /**************************************************************************** - * Function: sam_txtimeout + * Function: sam_txtimeout_process * * Description: - * Our TX watchdog timed out. Called from the timer interrupt handler. - * The last TX never completed. Reset the hardware and start again. + * Process a TX timeout. Called from the either the watchdog timer + * expiration logic or from the worker thread, depending upon the + * configuration. The timeout means that the last TX never completed. + * Reset the hardware and start again. * * Parameters: - * argc - The number of available arguments - * arg - The first argument + * priv - Reference to the driver state structure * * Returned Value: * None @@ -1572,15 +1726,11 @@ static int sam_gmac_interrupt(int irq, void *context) * ****************************************************************************/ -static void sam_txtimeout(int argc, uint32_t arg, ...) +static inline void sam_txtimeout_process(FAR struct sam_gmac_s *priv) { - struct sam_gmac_s *priv = (struct sam_gmac_s *)arg; - nerr("ERROR: Timeout!\n"); - /* Then reset the hardware. Just take the interface down, then back - * up again. - */ + /* Reset the hardware. Just take the interface down, then back up again. */ sam_ifdown(&priv->dev); sam_ifup(&priv->dev); @@ -1591,10 +1741,42 @@ static void sam_txtimeout(int argc, uint32_t arg, ...) } /**************************************************************************** - * Function: sam_polltimer + * Function: sam_txtimeout_work * * Description: - * Periodic timer handler. Called from the timer interrupt handler. + * Perform TX timeout related work from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * Ethernet interrupts are disabled + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void sam_txtimeout_work(FAR void *arg) +{ + FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg; + net_lock_t state; + + /* Process pending Ethernet interrupts */ + + state = net_lock(); + sam_txtimeout_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: sam_txtimeout_expiry + * + * Description: + * Our TX watchdog timed out. Called from the timer interrupt handler. + * The last TX never completed. Reset the hardware and start again. * * Parameters: * argc - The number of available arguments @@ -1608,10 +1790,54 @@ static void sam_txtimeout(int argc, uint32_t arg, ...) * ****************************************************************************/ -static void sam_polltimer(int argc, uint32_t arg, ...) +static void sam_txtimeout_expiry(int argc, uint32_t arg, ...) { - struct sam_gmac_s *priv = (struct sam_gmac_s *)arg; - struct net_driver_s *dev = &priv->dev; + FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg; + +#ifdef CONFIG_NET_NOINTS + /* Disable further Ethernet interrupts. This will prevent some race + * conditions with interrupt work. There is still a potential race + * condition with interrupt work that is already queued and in progress. + */ + + up_disable_irq(SAM_IRQ_GMAC); + + /* Cancel any pending poll or interrupt work. This will have no effect + * on work that has already been started. + */ + + work_cancel(ETHWORK, &priv->work); + + /* Schedule to perform the TX timeout processing on the worker thread. */ + + work_queue(ETHWORK, &priv->work, sam_txtimeout_work, priv, 0); +#else + /* Process the timeout now */ + + sam_txtimeout_process(priv); +#endif +} + +/**************************************************************************** + * Function: sam_poll_process + * + * Description: + * Perform the periodic poll. This may be called either from watchdog + * timer logic or from the worker thread, depending upon the configuration. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static inline void sam_poll_process(FAR struct sam_gmac_s *priv) +{ + struct net_driver_s *dev = &priv->dev; /* Check if the there are any free TX descriptors. We cannot perform the * TX poll if we do not have buffering for another packet. @@ -1626,7 +1852,87 @@ static void sam_polltimer(int argc, uint32_t arg, ...) /* Setup the watchdog poll timer again */ - (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_polltimer, 1, arg); + (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, priv); +} + +/**************************************************************************** + * Function: sam_poll_work + * + * Description: + * Perform periodic polling from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * Ethernet interrupts are disabled + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void sam_poll_work(FAR void *arg) +{ + FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg; + net_lock_t state; + + /* Perform the poll */ + + state = net_lock(); + sam_poll_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: sam_poll_expiry + * + * Description: + * Periodic timer handler. Called from the timer interrupt handler. + * + * Parameters: + * argc - The number of available arguments + * arg - The first argument + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * + ****************************************************************************/ + +static void sam_poll_expiry(int argc, uint32_t arg, ...) +{ + FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg; + +#ifdef CONFIG_NET_NOINTS + /* Is our single work structure available? It may not be if there are + * pending interrupt actions. + */ + + if (work_available(&priv->work)) + { + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->work, sam_poll_work, priv, 0); + } + else + { + /* No.. Just re-start the watchdog poll timer, missing one polling + * cycle. + */ + + (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, arg); + } + +#else + /* Process the interrupt now */ + + sam_poll_process(priv); +#endif } /**************************************************************************** @@ -1700,7 +2006,7 @@ static int sam_ifup(struct net_driver_s *dev) /* Set and activate a timer process */ - (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_polltimer, 1, (uint32_t)priv); + (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, (uint32_t)priv); /* Enable the GMAC interrupt */ @@ -1756,6 +2062,68 @@ static int sam_ifdown(struct net_driver_s *dev) return OK; } +/**************************************************************************** + * Function: sam_txavail_process + * + * Description: + * Perform an out-of-cycle poll. + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static inline void sam_txavail_process(FAR struct sam_gmac_s *priv) +{ + ninfo("ifup: %d\n", priv->ifup); + + /* Ignore the notification if the interface is not yet up */ + + if (priv->ifup) + { + /* Poll the network for new XMIT data */ + + sam_dopoll(priv); + } +} + +/**************************************************************************** + * Function: sam_txavail_work + * + * Description: + * Perform an out-of-cycle poll on the worker thread. + * + * Parameters: + * arg - Reference to the NuttX driver state structure (cast to void*) + * + * Returned Value: + * None + * + * Assumptions: + * Called on the higher priority worker thread. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void sam_txavail_work(FAR void *arg) +{ + FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg; + net_lock_t state; + + /* Perform the poll */ + + state = net_lock(); + sam_txavail_process(priv); + net_unlock(state); +} +#endif + /**************************************************************************** * Function: sam_txavail * @@ -1765,7 +2133,7 @@ static int sam_ifdown(struct net_driver_s *dev) * latency. * * Parameters: - * dev - Reference to the NuttX driver state structure + * dev - Reference to the NuttX driver state structure * * Returned Value: * None @@ -1777,10 +2145,23 @@ static int sam_ifdown(struct net_driver_s *dev) static int sam_txavail(struct net_driver_s *dev) { - struct sam_gmac_s *priv = (struct sam_gmac_s *)dev->d_private; - irqstate_t flags; + FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)dev->d_private; - ninfo("ifup: %d\n", priv->ifup); +#ifdef CONFIG_NET_NOINTS + /* Is our single work structure available? It may not be if there are + * pending interrupt actions and we will have to ignore the Tx + * availability action. + */ + + if (work_available(&priv->work)) + { + /* Schedule to serialize the poll on the worker thread. */ + + work_queue(ETHWORK, &priv->work, sam_txavail_work, priv, 0); + } + +#else + irqstate_t flags; /* Disable interrupts because this function may be called from interrupt * level processing. @@ -1788,16 +2169,12 @@ static int sam_txavail(struct net_driver_s *dev) flags = enter_critical_section(); - /* Ignore the notification if the interface is not yet up */ - - if (priv->ifup) - { - /* Poll the network for new XMIT data */ - - sam_dopoll(priv); - } + /* Perform the out-of-cycle poll now */ + sam_txavail_process(priv); leave_critical_section(flags); +#endif + return OK; } diff --git a/configs/sama5d3-xplained/bridge/defconfig b/configs/sama5d3-xplained/bridge/defconfig index a1a3f37492..ea5c1c4fc6 100644 --- a/configs/sama5d3-xplained/bridge/defconfig +++ b/configs/sama5d3-xplained/bridge/defconfig @@ -279,6 +279,7 @@ CONFIG_SAMA5_GMAC_NRXBUFFERS=16 CONFIG_SAMA5_GMAC_NTXBUFFERS=8 # CONFIG_SAMA5_GMAC_PREALLOCATE is not set # CONFIG_SAMA5_GMAC_NBC is not set +CONFIG_SAMA5_GMAC_HPWORK=y CONFIG_SAMA5_GMAC_PHYADDR=1 # CONFIG_SAMA5_GMAC_PHYINIT is not set CONFIG_SAMA5_GMAC_AUTONEG=y @@ -302,6 +303,7 @@ CONFIG_SAMA5_EMAC_PHYSR_10FD=0x5 CONFIG_SAMA5_EMAC_PHYSR_100FD=0x6 # CONFIG_SAMA5_EMACA_PREALLOCATE is not set # CONFIG_SAMA5_EMACA_NBC is not set +CONFIG_SAMA5_EMACA_HPWORK=y # CONFIG_SAMA5_EMAC_ISETH0 is not set CONFIG_SAMA5_GMAC_ISETH0=y @@ -481,6 +483,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -489,6 +492,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -500,8 +504,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -592,7 +599,6 @@ CONFIG_NETDEV_MULTINIC=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set @@ -692,7 +698,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # -- GitLab From bfa1da14e2604fabc9440dc0387c0a8cd7a4bbd4 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 3 Dec 2016 08:32:49 -0600 Subject: [PATCH 576/734] LM3S Ethernet now supports CONFIG_NET_NOINTS --- TODO | 2 +- arch/arm/src/tiva/Kconfig | 20 + arch/arm/src/tiva/lm3s_ethernet.c | 493 ++++++++++++++++++++++--- configs/eagle100/httpd/defconfig | 13 +- configs/eagle100/nettest/defconfig | 13 +- configs/eagle100/nsh/defconfig | 13 +- configs/eagle100/thttpd/defconfig | 13 +- configs/ekk-lm3s9b96/nsh/defconfig | 13 +- configs/lm3s6432-s2e/nsh/defconfig | 13 +- configs/lm3s6965-ek/discover/defconfig | 13 +- configs/lm3s6965-ek/nsh/defconfig | 13 +- configs/lm3s6965-ek/tcpecho/defconfig | 13 +- configs/lm3s8962-ek/nsh/defconfig | 13 +- drivers/net/skeleton.c | 14 +- 14 files changed, 559 insertions(+), 100 deletions(-) diff --git a/TODO b/TODO index 2f930f21b1..a364e4e8ed 100644 --- a/TODO +++ b/TODO @@ -1057,7 +1057,7 @@ o Network (net/, drivers/net) STM32 YES YES STM32F7 YES YES TIVA ----------------------- ------ - LM3S NO NO + LM3S YES NO TM4C YES YES eZ80 NO NO Kinetis YES YES (not tested) diff --git a/arch/arm/src/tiva/Kconfig b/arch/arm/src/tiva/Kconfig index 78a7ae07f1..4f483170b4 100644 --- a/arch/arm/src/tiva/Kconfig +++ b/arch/arm/src/tiva/Kconfig @@ -911,6 +911,26 @@ config TIVA_BADCRC ---help--- Set to enable bad CRC rejection. +choice + prompt "Work queue" + default TIVA_ETHERNET_LPWORK if SCHED_LPWORK + default TIVA_ETHERNET_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + depends on SCHED_WORKQUEUE + ---help--- + Work queue support is required to use the Ethernet driver. If the + low priority work queue is available, then it should be used by the + driver. + +config TIVA_ETHERNET_HPWORK + bool "High priority" + depends on SCHED_HPWORK + +config TIVA_ETHERNET_LPWORK + bool "Low priority" + depends on SCHED_LPWORK + +endchoice # Work queue + config TIVA_DUMPPACKET bool "Dump Packets" default n diff --git a/arch/arm/src/tiva/lm3s_ethernet.c b/arch/arm/src/tiva/lm3s_ethernet.c index 852c19a0d3..4586747c20 100644 --- a/arch/arm/src/tiva/lm3s_ethernet.c +++ b/arch/arm/src/tiva/lm3s_ethernet.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/tiva/lm3s_ethernet.c * - * Copyright (C) 2009-2010, 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2009-2010, 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -52,6 +52,11 @@ #include #include #include + +#ifdef CONFIG_NET_NOINTS +# include +#endif + #include #include #include @@ -71,6 +76,26 @@ * Pre-processor Definitions ****************************************************************************/ +/* If processing is not done at the interrupt level, then work queue support + * is required. + */ + +#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required in this configuration (CONFIG_SCHED_WORKQUEUE) +#endif + +/* Use the low priority work queue if possible */ + +#if defined(CONFIG_SCHED_WORKQUEUE) +# if defined(CONFIG_TIVA_ETHERNET_HPWORK) +# define ETHWORK HPWORK +# elif defined(CONFIG_TIVA_ETHERNET_LPWORK) +# define ETHWORK LPWORK +# else +# error Neither CONFIG_TIVA_ETHERNET_HPWORK nor CONFIG_TIVA_ETHERNET_LPWORK defined +# endif +#endif + /* Half duplex can be forced if CONFIG_TIVA_ETHHDUPLEX is defined. */ #ifdef CONFIG_TIVA_ETHHDUPLEX @@ -181,6 +206,9 @@ struct tiva_driver_s bool ld_bifup; /* true:ifup false:ifdown */ WDOG_ID ld_txpoll; /* TX poll timer */ WDOG_ID ld_txtimeout; /* TX timeout timer */ +#ifdef CONFIG_NET_NOINTS + struct work_s ld_work; /* For deferring work to the work queue */ +#endif /* This holds the information visible to the NuttX network */ @@ -227,21 +255,42 @@ static int tiva_txpoll(struct net_driver_s *dev); static void tiva_receive(struct tiva_driver_s *priv); static void tiva_txdone(struct tiva_driver_s *priv); -static int tiva_interrupt(int irq, FAR void *context); + +static inline void tiva_interrupt_process(struct tiva_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void tiva_interrupt_work(void *arg); +#endif +static int tiva_interrupt(int irq, void *context); /* Watchdog timer expirations */ -static void tiva_polltimer(int argc, uint32_t arg, ...); -static void tiva_txtimeout(int argc, uint32_t arg, ...); +static inline void tiva_txtimeout_process(struct tiva_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void tiva_txtimeout_work(void *arg); +#endif +static void tiva_txtimeout_expiry(int argc, uint32_t arg, ...); + +static inline void tiva_poll_process(struct tiva_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void tiva_poll_work(void *arg); +#endif +static void tiva_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ static int tiva_ifup(struct net_driver_s *dev); static int tiva_ifdown(struct net_driver_s *dev); + + +static inline void tiva_txavail_process(struct tiva_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void tiva_txavail_work(void *arg); +#endif static int tiva_txavail(struct net_driver_s *dev); + #ifdef CONFIG_NET_IGMP -static int tiva_addmac(struct net_driver_s *dev, FAR const uint8_t *mac); -static int tiva_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac); +static int tiva_addmac(struct net_driver_s *dev, const uint8_t *mac); +static int tiva_rmmac(struct net_driver_s *dev, const uint8_t *mac); #endif /**************************************************************************** @@ -547,7 +596,8 @@ static int tiva_transmit(struct tiva_driver_s *priv) /* Setup the TX timeout watchdog (perhaps restarting the timer) */ - (void)wd_start(priv->ld_txtimeout, TIVA_TXTIMEOUT, tiva_txtimeout, 1, (uint32_t)priv); + (void)wd_start(priv->ld_txtimeout, TIVA_TXTIMEOUT, + tiva_txtimeout_expiry, 1, (uint32_t)priv); ret = OK; } @@ -913,33 +963,27 @@ static void tiva_txdone(struct tiva_driver_s *priv) } /**************************************************************************** - * Function: tiva_interrupt + * Function: tiva_interrupt_process * * Description: - * Hardware interrupt handler + * Interrupt processing. This may be performed either within the interrupt + * handler or on the worker thread, depending upon the configuration * * Parameters: - * irq - Number of the IRQ that generated the interrupt - * context - Interrupt register state save info (architecture-specific) + * priv - Reference to the driver state structure * * Returned Value: - * OK on success + * None * * Assumptions: + * The network is locked. * ****************************************************************************/ -static int tiva_interrupt(int irq, FAR void *context) +static inline void tiva_interrupt_process(struct tiva_driver_s *priv) { - register struct tiva_driver_s *priv; uint32_t ris; -#if TIVA_NETHCONTROLLERS > 1 -# error "A mechanism to associate and interface with an IRQ is needed" -#else - priv = &g_lm3sdev[0]; -#endif - /* Read the raw interrupt status register */ ris = tiva_ethin(priv, TIVA_MAC_RIS_OFFSET); @@ -994,36 +1038,142 @@ static int tiva_interrupt(int irq, FAR void *context) tiva_txdone(priv); } +} - /* Enable Ethernet interrupts (perhaps excluding the TX done interrupt if - * there are no pending transmissions). - */ +/**************************************************************************** + * Function: tiva_interrupt_work + * + * Description: + * Perform interrupt related work from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() was called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ - return OK; +#ifdef CONFIG_NET_NOINTS +static void tiva_interrupt_work(void *arg) +{ + struct tiva_driver_s *priv = (struct tiva_driver_s *)arg; + net_lock_t state; + + /* Process pending Ethernet interrupts */ + + state = net_lock(); + tiva_interrupt_process(priv); + net_unlock(state); + + /* Re-enable Ethernet interrupts */ + +#if TIVA_NETHCONTROLLERS > 1 + up_disable_irq(priv->irq); +#else + up_disable_irq(TIVA_IRQ_ETHCON); +#endif } +#endif /**************************************************************************** - * Function: tiva_txtimeout + * Function: tiva_interrupt * * Description: - * Our TX watchdog timed out. Called from the timer interrupt handler. - * The last TX never completed. Reset the hardware and start again. + * Hardware interrupt handler * * Parameters: - * argc - The number of available arguments - * arg - The first argument + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) * * Returned Value: - * None + * OK on success * * Assumptions: * ****************************************************************************/ -static void tiva_txtimeout(int argc, uint32_t arg, ...) +static int tiva_interrupt(int irq, void *context) { - struct tiva_driver_s *priv = (struct tiva_driver_s *)arg; + struct tiva_driver_s *priv; + uint32_t ris; + +#if TIVA_NETHCONTROLLERS > 1 +# error "A mechanism to associate and interface with an IRQ is needed" +#else + priv = &g_lm3sdev[0]; +#endif + +#ifdef CONFIG_NET_NOINTS + /* Disable further Ethernet interrupts. Because Ethernet interrupts are + * also disabled if the TX timeout event occurs, there can be no race + * condition here. + */ + +#if TIVA_NETHCONTROLLERS > 1 + up_disable_irq(priv->irq); +#else + up_disable_irq(TIVA_IRQ_ETHCON); +#endif + + /* Read the raw interrupt status register (masking out any disabled + * interrupts). + */ + + ris = tiva_ethin(priv, TIVA_MAC_RIS_OFFSET); + ris &= tiva_ethin(priv, TIVA_MAC_IM_OFFSET); + + /* Is this an Tx interrupt (meaning that the Tx FIFO is empty)? */ + + if ((ris & MAC_RIS_TXEMP) != 0) + { + /* If a TX transfer just completed, then cancel the TX timeout so + * there will be do race condition between any subsequent timeout + * expiration and the deferred interrupt processing. + */ + + wd_cancel(priv->ld_txtimeout); + } + + /* Cancel any pending poll work */ + + work_cancel(HPWORK, &priv->ld_work); + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->ld_work, tiva_interrupt_work, priv, 0); + +#else + /* Process the interrupt now */ + + tiva_interrupt_process(priv); +#endif + + return OK; +} + +/**************************************************************************** + * Function: tiva_txtimeout_process + * + * Description: + * Process a TX timeout. Called from the either the watchdog timer + * expiration logic or from the worker thread, depending upon the + * configuration. The timeout means that the last TX never completed. + * Reset the hardware and start again. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void tiva_txtimeout_process(struct tiva_driver_s *priv) +{ /* Increment statistics */ nerr("ERROR: Tx timeout\n"); @@ -1041,10 +1191,42 @@ static void tiva_txtimeout(int argc, uint32_t arg, ...) } /**************************************************************************** - * Function: tiva_polltimer + * Function: tiva_txtimeout_work * * Description: - * Periodic timer handler. Called from the timer interrupt handler. + * Perform TX timeout related work from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void tiva_txtimeout_work(void *arg) +{ + struct tiva_driver_s *priv = (struct tiva_driver_s *)arg; + net_lock_t state; + + /* Process pending Ethernet interrupts */ + + state = net_lock(); + tiva_txtimeout_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: tiva_txtimeout_expiry + * + * Description: + * Our TX watchdog timed out. Called from the timer interrupt handler. + * The last TX never completed. Reset the hardware and start again. * * Parameters: * argc - The number of available arguments @@ -1054,13 +1236,61 @@ static void tiva_txtimeout(int argc, uint32_t arg, ...) * None * * Assumptions: + * Global interrupts are disabled by the watchdog logic. * ****************************************************************************/ -static void tiva_polltimer(int argc, uint32_t arg, ...) +static void tiva_txtimeout_expiry(int argc, wdparm_t arg, ...) { struct tiva_driver_s *priv = (struct tiva_driver_s *)arg; +#ifdef CONFIG_NET_NOINTS + /* Disable further Ethernet interrupts. This will prevent some race + * conditions with interrupt work. There is still a potential race + * condition with interrupt work that is already queued and in progress. + */ + +#if TIVA_NETHCONTROLLERS > 1 + up_disable_irq(priv->irq); +#else + up_disable_irq(TIVA_IRQ_ETHCON); +#endif + + /* Cancel any pending poll or interrupt work. This will have no effect + * on work that has already been started. + */ + + work_cancel(ETHWORK, &priv->ld_work); + + /* Schedule to perform the TX timeout processing on the worker thread. */ + + work_queue(ETHWORK, &priv->ld_work, tiva_txtimeout_work, priv, 0); +#else + /* Process the timeout now */ + + tiva_txtimeout_process(priv); +#endif +} + +/**************************************************************************** + * Function: tiva_poll_process + * + * Description: + * Perform the periodic poll. This may be called either from watchdog + * timer logic or from the worker thread, depending upon the configuration. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static inline void tiva_poll_process(struct tiva_driver_s *priv) +{ /* Check if we can send another Tx packet now. The NEWTX bit initiates an * Ethernet transmission once the packet has been placed in the TX FIFO. * This bit is cleared once the transmission has been completed. @@ -1071,14 +1301,97 @@ static void tiva_polltimer(int argc, uint32_t arg, ...) if ((tiva_ethin(priv, TIVA_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) { - /* If so, update TCP timing states and poll the network for new XMIT data */ + /* If so, update TCP timing states and poll the network for new XMIT + * data. + */ (void)devif_timer(&priv->ld_dev, tiva_txpoll); /* Setup the watchdog poll timer again */ - (void)wd_start(priv->ld_txpoll, TIVA_WDDELAY, tiva_polltimer, 1, arg); + (void)wd_start(priv->ld_txpoll, TIVA_WDDELAY, tiva_poll_expiry, + 1, priv); + } +} + +/**************************************************************************** + * Function: tiva_poll_work + * + * Description: + * Perform periodic polling from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void tiva_poll_work(void *arg) +{ + struct tiva_driver_s *priv = (struct tiva_driver_s *)arg; + net_lock_t state; + + /* Perform the poll */ + + state = net_lock(); + tiva_poll_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: tiva_poll_expiry + * + * Description: + * Periodic timer handler. Called from the timer interrupt handler. + * + * Parameters: + * argc - The number of available arguments + * arg - The first argument + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * + ****************************************************************************/ + +static void tiva_poll_expiry(int argc, wdparm_t arg, ...) +{ + struct tiva_driver_s *priv = (struct tiva_driver_s *)arg; + +#ifdef CONFIG_NET_NOINTS + /* Is our single work structure available? It may not be if there are + * pending interrupt actions. + */ + + if (work_available(&priv->ld_work)) + { + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->ld_work, tiva_poll_work, priv, 0); + } + else + { + /* No.. Just re-start the watchdog poll timer, missing one polling + * cycle. + */ + + (void)wd_start(priv->ld_txpoll, TIVA_WDDELAY, tiva_poll_expiry, 1, arg); } + +#else + /* Process the interrupt now */ + + tiva_poll_process(priv); +#endif } /**************************************************************************** @@ -1230,7 +1543,7 @@ static int tiva_ifup(struct net_driver_s *dev) /* Set and activate a timer process */ - (void)wd_start(priv->ld_txpoll, TIVA_WDDELAY, tiva_polltimer, 1, (uint32_t)priv); + (void)wd_start(priv->ld_txpoll, TIVA_WDDELAY, tiva_poll_expiry, 1, (uint32_t)priv); priv->ld_bifup = true; leave_critical_section(flags); @@ -1321,15 +1634,13 @@ static int tiva_ifdown(struct net_driver_s *dev) } /**************************************************************************** - * Function: tiva_txavail + * Function: tiva_txavail_process * * Description: - * Driver callback invoked when new TX data is available. This is a - * stimulus perform an out-of-cycle poll and, thereby, reduce the TX - * latency. + * Perform an out-of-cycle poll. * * Parameters: - * dev - Reference to the NuttX driver state structure + * dev - Reference to the NuttX driver state structure * * Returned Value: * None @@ -1339,11 +1650,8 @@ static int tiva_ifdown(struct net_driver_s *dev) * ****************************************************************************/ -static int tiva_txavail(struct net_driver_s *dev) +static inline void tiva_txavail_process(struct tiva_driver_s *priv) { - struct tiva_driver_s *priv = (struct tiva_driver_s *)dev->d_private; - irqstate_t flags; - /* Ignore the notification if the interface is not yet up or if the Tx FIFO * hardware is not available at this time. The NEWTX bit initiates an * Ethernet transmission once the packet has been placed in the TX FIFO. @@ -1352,7 +1660,6 @@ static int tiva_txavail(struct net_driver_s *dev) * will occur at that time. */ - flags = enter_critical_section(); if (priv->ld_bifup && (tiva_ethin(priv, TIVA_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) { /* If the interface is up and we can use the Tx FIFO, then poll the network @@ -1361,8 +1668,90 @@ static int tiva_txavail(struct net_driver_s *dev) (void)devif_poll(&priv->ld_dev, tiva_txpoll); } +} + +/**************************************************************************** + * Function: tiva_txavail_work + * + * Description: + * Perform an out-of-cycle poll on the worker thread. + * + * Parameters: + * arg - Reference to the NuttX driver state structure (cast to void*) + * + * Returned Value: + * None + * + * Assumptions: + * Called on the higher priority worker thread. + * + ****************************************************************************/ +#ifdef CONFIG_NET_NOINTS +static void tiva_txavail_work(void *arg) +{ + struct tiva_driver_s *priv = (struct tiva_driver_s *)arg; + net_lock_t state; + + /* Perform the poll */ + + state = net_lock(); + tiva_txavail_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: tiva_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static int tiva_txavail(struct net_driver_s *dev) +{ + struct tiva_driver_s *priv = (struct tiva_driver_s *)dev->d_private; + +#ifdef CONFIG_NET_NOINTS + /* Is our single work structure available? It may not be if there are + * pending interrupt actions and we will have to ignore the Tx + * availability action. + */ + + if (work_available(&priv->ld_work)) + { + /* Schedule to serialize the poll on the worker thread. */ + + work_queue(ETHWORK, &priv->ld_work, tiva_txavail_work, priv, 0); + } + +#else + irqstate_t flags; + + /* Disable interrupts because this function may be called from interrupt + * level processing. + */ + + flags = enter_critical_section(); + + /* Perform the out-of-cycle poll now */ + + tiva_txavail_process(priv); leave_critical_section(flags); +#endif + return OK; } @@ -1385,9 +1774,9 @@ static int tiva_txavail(struct net_driver_s *dev) ****************************************************************************/ #ifdef CONFIG_NET_IGMP -static int tiva_addmac(struct net_driver_s *dev, FAR const uint8_t *mac) +static int tiva_addmac(struct net_driver_s *dev, const uint8_t *mac) { - FAR struct tiva_driver_s *priv = (FAR struct tiva_driver_s *)dev->d_private; + struct tiva_driver_s *priv = (struct tiva_driver_s *)dev->d_private; /* Add the MAC address to the hardware multicast routing table */ @@ -1415,9 +1804,9 @@ static int tiva_addmac(struct net_driver_s *dev, FAR const uint8_t *mac) ****************************************************************************/ #ifdef CONFIG_NET_IGMP -static int tiva_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac) +static int tiva_rmmac(struct net_driver_s *dev, const uint8_t *mac) { - FAR struct tiva_driver_s *priv = (FAR struct tiva_driver_s *)dev->d_private; + struct tiva_driver_s *priv = (struct tiva_driver_s *)dev->d_private; /* Add the MAC address to the hardware multicast routing table */ diff --git a/configs/eagle100/httpd/defconfig b/configs/eagle100/httpd/defconfig index b15438b5a7..6ff58e8c7d 100644 --- a/configs/eagle100/httpd/defconfig +++ b/configs/eagle100/httpd/defconfig @@ -257,6 +257,7 @@ CONFIG_TIVA_GPIOG_IRQS=y # CONFIG_TIVA_PROMISCUOUS is not set # CONFIG_TIVA_TIMESTAMP is not set # CONFIG_TIVA_BADCRC is not set +CONFIG_TIVA_ETHERNET_HPWORK=y # CONFIG_TIVA_DUMPPACKET is not set CONFIG_TIVA_BOARDMAC=y @@ -414,6 +415,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -422,13 +424,17 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -521,7 +527,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set # CONFIG_PIPES is not set @@ -604,7 +609,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/eagle100/nettest/defconfig b/configs/eagle100/nettest/defconfig index 2dc669e057..a0aa41a4d4 100644 --- a/configs/eagle100/nettest/defconfig +++ b/configs/eagle100/nettest/defconfig @@ -257,6 +257,7 @@ CONFIG_TIVA_GPIOG_IRQS=y # CONFIG_TIVA_PROMISCUOUS is not set # CONFIG_TIVA_TIMESTAMP is not set # CONFIG_TIVA_BADCRC is not set +CONFIG_TIVA_ETHERNET_HPWORK=y # CONFIG_TIVA_DUMPPACKET is not set CONFIG_TIVA_BOARDMAC=y @@ -408,6 +409,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -415,13 +417,17 @@ CONFIG_NAME_MAX=32 CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -513,7 +519,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set # CONFIG_PIPES is not set @@ -596,7 +601,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/eagle100/nsh/defconfig b/configs/eagle100/nsh/defconfig index 18875dc628..ca7b4701fe 100644 --- a/configs/eagle100/nsh/defconfig +++ b/configs/eagle100/nsh/defconfig @@ -257,6 +257,7 @@ CONFIG_TIVA_GPIOG_IRQS=y # CONFIG_TIVA_PROMISCUOUS is not set # CONFIG_TIVA_TIMESTAMP is not set # CONFIG_TIVA_BADCRC is not set +CONFIG_TIVA_ETHERNET_HPWORK=y # CONFIG_TIVA_DUMPPACKET is not set CONFIG_TIVA_BOARDMAC=y @@ -421,6 +422,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -429,6 +431,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -440,8 +443,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -554,7 +560,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set # CONFIG_PIPES is not set @@ -638,7 +643,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/eagle100/thttpd/defconfig b/configs/eagle100/thttpd/defconfig index 842069c5fa..9e597ffb4d 100644 --- a/configs/eagle100/thttpd/defconfig +++ b/configs/eagle100/thttpd/defconfig @@ -250,6 +250,7 @@ CONFIG_TIVA_GPIOG_IRQS=y # CONFIG_TIVA_PROMISCUOUS is not set # CONFIG_TIVA_TIMESTAMP is not set # CONFIG_TIVA_BADCRC is not set +CONFIG_TIVA_ETHERNET_HPWORK=y # CONFIG_TIVA_DUMPPACKET is not set CONFIG_TIVA_BOARDMAC=y @@ -401,6 +402,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -408,13 +410,17 @@ CONFIG_NAME_MAX=32 CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -506,7 +512,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set CONFIG_PIPES=y @@ -592,7 +597,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/ekk-lm3s9b96/nsh/defconfig b/configs/ekk-lm3s9b96/nsh/defconfig index bc00257530..080a0c5680 100644 --- a/configs/ekk-lm3s9b96/nsh/defconfig +++ b/configs/ekk-lm3s9b96/nsh/defconfig @@ -252,6 +252,7 @@ CONFIG_TIVA_GPIOG_IRQS=y # CONFIG_TIVA_PROMISCUOUS is not set # CONFIG_TIVA_TIMESTAMP is not set # CONFIG_TIVA_BADCRC is not set +CONFIG_TIVA_ETHERNET_HPWORK=y # CONFIG_TIVA_DUMPPACKET is not set # CONFIG_TIVA_BOARDMAC is not set @@ -410,6 +411,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -418,6 +420,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -429,8 +432,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -543,7 +549,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set # CONFIG_PIPES is not set @@ -627,7 +632,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/lm3s6432-s2e/nsh/defconfig b/configs/lm3s6432-s2e/nsh/defconfig index 23169aeb52..f69161c733 100644 --- a/configs/lm3s6432-s2e/nsh/defconfig +++ b/configs/lm3s6432-s2e/nsh/defconfig @@ -247,6 +247,7 @@ CONFIG_TIVA_GPIOB_IRQS=y # CONFIG_TIVA_PROMISCUOUS is not set # CONFIG_TIVA_TIMESTAMP is not set # CONFIG_TIVA_BADCRC is not set +CONFIG_TIVA_ETHERNET_HPWORK=y # CONFIG_TIVA_DUMPPACKET is not set CONFIG_TIVA_BOARDMAC=y @@ -405,6 +406,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -413,6 +415,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -424,8 +427,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -520,7 +526,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set # CONFIG_PIPES is not set @@ -618,7 +623,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/lm3s6965-ek/discover/defconfig b/configs/lm3s6965-ek/discover/defconfig index 0d7a0d7c80..f11ccb5d9d 100644 --- a/configs/lm3s6965-ek/discover/defconfig +++ b/configs/lm3s6965-ek/discover/defconfig @@ -251,6 +251,7 @@ CONFIG_TIVA_GPIOG_IRQS=y # CONFIG_TIVA_PROMISCUOUS is not set # CONFIG_TIVA_TIMESTAMP is not set # CONFIG_TIVA_BADCRC is not set +CONFIG_TIVA_ETHERNET_HPWORK=y # CONFIG_TIVA_DUMPPACKET is not set # CONFIG_TIVA_BOARDMAC is not set @@ -415,6 +416,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -423,6 +425,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -434,8 +437,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -548,7 +554,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set # CONFIG_PIPES is not set @@ -632,7 +637,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/lm3s6965-ek/nsh/defconfig b/configs/lm3s6965-ek/nsh/defconfig index 0d7a0d7c80..f11ccb5d9d 100644 --- a/configs/lm3s6965-ek/nsh/defconfig +++ b/configs/lm3s6965-ek/nsh/defconfig @@ -251,6 +251,7 @@ CONFIG_TIVA_GPIOG_IRQS=y # CONFIG_TIVA_PROMISCUOUS is not set # CONFIG_TIVA_TIMESTAMP is not set # CONFIG_TIVA_BADCRC is not set +CONFIG_TIVA_ETHERNET_HPWORK=y # CONFIG_TIVA_DUMPPACKET is not set # CONFIG_TIVA_BOARDMAC is not set @@ -415,6 +416,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -423,6 +425,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -434,8 +437,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -548,7 +554,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set # CONFIG_PIPES is not set @@ -632,7 +637,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/lm3s6965-ek/tcpecho/defconfig b/configs/lm3s6965-ek/tcpecho/defconfig index 3a6346553b..8a2f08ebc5 100644 --- a/configs/lm3s6965-ek/tcpecho/defconfig +++ b/configs/lm3s6965-ek/tcpecho/defconfig @@ -250,6 +250,7 @@ CONFIG_TIVA_GPIOG_IRQS=y # CONFIG_TIVA_PROMISCUOUS is not set # CONFIG_TIVA_TIMESTAMP is not set # CONFIG_TIVA_BADCRC is not set +CONFIG_TIVA_ETHERNET_HPWORK=y # CONFIG_TIVA_DUMPPACKET is not set # CONFIG_TIVA_BOARDMAC is not set @@ -402,6 +403,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -410,6 +412,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -421,8 +424,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -517,7 +523,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set # CONFIG_PIPES is not set @@ -602,7 +607,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/lm3s8962-ek/nsh/defconfig b/configs/lm3s8962-ek/nsh/defconfig index 5ddde16265..c631ca1bce 100644 --- a/configs/lm3s8962-ek/nsh/defconfig +++ b/configs/lm3s8962-ek/nsh/defconfig @@ -261,6 +261,7 @@ CONFIG_TIVA_GPIOG_IRQS=y # CONFIG_TIVA_PROMISCUOUS is not set # CONFIG_TIVA_TIMESTAMP is not set # CONFIG_TIVA_BADCRC is not set +CONFIG_TIVA_ETHERNET_HPWORK=y # CONFIG_TIVA_DUMPPACKET is not set # CONFIG_TIVA_BOARDMAC is not set @@ -425,6 +426,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -433,6 +435,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -444,8 +447,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -558,7 +564,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set # CONFIG_PIPES is not set @@ -642,7 +647,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/drivers/net/skeleton.c b/drivers/net/skeleton.c index 49ad691a4c..9ef4e40c0a 100644 --- a/drivers/net/skeleton.c +++ b/drivers/net/skeleton.c @@ -79,9 +79,9 @@ #if defined(CONFIG_SCHED_WORKQUEUE) # if defined(CONFIG_skeleton_HPWORK) -# define skelWORK HPWORK +# define ETHWORK HPWORK # elif defined(CONFIG_skeleton_LPWORK) -# define skelWORK LPWORK +# define ETHWORK LPWORK # else # error Neither CONFIG_skeleton_HPWORK nor CONFIG_skeleton_LPWORK defined # endif @@ -623,7 +623,7 @@ static int skel_interrupt(int irq, FAR void *context) /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(skelWORK, &priv->sk_work, skel_interrupt_work, priv, 0); + work_queue(ETHWORK, &priv->sk_work, skel_interrupt_work, priv, 0); #else /* Process the interrupt now */ @@ -730,11 +730,11 @@ static void skel_txtimeout_expiry(int argc, wdparm_t arg, ...) * on work that has already been started. */ - work_cancel(skelWORK, &priv->sk_work); + work_cancel(ETHWORK, &priv->sk_work); /* Schedule to perform the TX timeout processing on the worker thread. */ - work_queue(skelWORK, &priv->sk_work, skel_txtimeout_work, priv, 0); + work_queue(ETHWORK, &priv->sk_work, skel_txtimeout_work, priv, 0); #else /* Process the timeout now */ @@ -840,7 +840,7 @@ static void skel_poll_expiry(int argc, wdparm_t arg, ...) { /* Schedule to perform the interrupt processing on the worker thread. */ - work_queue(skelWORK, &priv->sk_work, skel_poll_work, priv, 0); + work_queue(ETHWORK, &priv->sk_work, skel_poll_work, priv, 0); } else { @@ -1051,7 +1051,7 @@ static int skel_txavail(FAR struct net_driver_s *dev) { /* Schedule to serialize the poll on the worker thread. */ - work_queue(skelWORK, &priv->sk_work, skel_txavail_work, priv, 0); + work_queue(ETHWORK, &priv->sk_work, skel_txavail_work, priv, 0); } #else -- GitLab From eba1e076ec2ce71eb26912f98682a46efac1c426 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 3 Dec 2016 09:50:14 -0600 Subject: [PATCH 577/734] PIC32MX/Z Ethernet: Now supports CONFIG_NET_NOINT --- arch/mips/src/pic32mx/Kconfig | 34 +- arch/mips/src/pic32mx/pic32mx-ethernet.c | 486 +++++++++++++++++++--- arch/mips/src/pic32mz/Kconfig | 36 +- arch/mips/src/pic32mz/pic32mz-ethernet.c | 486 +++++++++++++++++++--- configs/pic32mx-starterkit/nsh2/defconfig | 13 +- configs/pic32mx7mmb/nsh/defconfig | 13 +- drivers/net/skeleton.c | 9 +- 7 files changed, 945 insertions(+), 132 deletions(-) diff --git a/arch/mips/src/pic32mx/Kconfig b/arch/mips/src/pic32mx/Kconfig index 366c50fdf5..52dd774566 100644 --- a/arch/mips/src/pic32mx/Kconfig +++ b/arch/mips/src/pic32mx/Kconfig @@ -1094,13 +1094,6 @@ config NET_WOL ---help--- Enable Wake-up on LAN (not fully implemented). -config NET_REGDEBUG - bool "Register level debug" - default n - depends on PIC32MX_ETHERNET && DEBUG_NET_INFO - ---help--- - Enabled low level register debug. Also needs CONFIG_DEBUG_FEATURES. - config NET_HASH bool "Hash" default n @@ -1116,6 +1109,33 @@ config PIC32MX_MULTICAST Enable receipt of multicast (and unicast) frames. Automatically set if NET_IGMP is selected. +choice + prompt "Work queue" + default PIC32MX_ETHERNET_LPWORK if SCHED_LPWORK + default PIC32MX_ETHERNET_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + depends on SCHED_WORKQUEUE + ---help--- + Work queue support is required to use the Ethernet driver. If the + low priority work queue is available, then it should be used by the + driver. + +config PIC32MX_ETHERNET_HPWORK + bool "High priority" + depends on SCHED_HPWORK + +config PIC32MX_ETHERNET_LPWORK + bool "Low priority" + depends on SCHED_LPWORK + +endchoice # Work queue + +config NET_REGDEBUG + bool "Register level debug" + default n + depends on PIC32MX_ETHERNET && DEBUG_NET_INFO + ---help--- + Enabled low level register debug. Also needs CONFIG_DEBUG_FEATURES. + endmenu menu "Device Configuration 0 (DEVCFG0)" diff --git a/arch/mips/src/pic32mx/pic32mx-ethernet.c b/arch/mips/src/pic32mx/pic32mx-ethernet.c index 1b1ebcb6fc..2277e09039 100644 --- a/arch/mips/src/pic32mx/pic32mx-ethernet.c +++ b/arch/mips/src/pic32mx/pic32mx-ethernet.c @@ -55,6 +55,11 @@ #include #include #include + +#ifdef CONFIG_NET_NOINTS +# include +#endif + #include #include #include @@ -81,6 +86,26 @@ * Pre-processor Definitions ****************************************************************************/ /* Configuration ************************************************************/ +/* If processing is not done at the interrupt level, then work queue support + * is required. + */ + +#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required in this configuration (CONFIG_SCHED_WORKQUEUE) +#endif + +/* Use the low priority work queue if possible */ + +#if defined(CONFIG_SCHED_WORKQUEUE) +# if defined(CONFIG_PIC32MX_ETHERNET_HPWORK) +# define ETHWORK HPWORK +# elif defined(CONFIG_PIC32MX_ETHERNET_LPWORK) +# define ETHWORK LPWORK +# else +# error Neither CONFIG_PIC32MX_ETHERNET_HPWORK nor CONFIG_PIC32MX_ETHERNET_LPWORK defined +# endif +#endif + /* CONFIG_PIC32MX_NINTERFACES determines the number of physical interfaces * that will be supported -- unless it is more than actually supported by the * hardware! @@ -301,6 +326,9 @@ struct pic32mx_driver_s uint32_t pd_inten; /* Shadow copy of INTEN register */ WDOG_ID pd_txpoll; /* TX poll timer */ WDOG_ID pd_txtimeout; /* TX timeout timer */ +#ifdef CONFIG_NET_NOINTS + struct work_s pd_work; /* For deferring work to the work queue */ +#endif sq_queue_t pd_freebuffers; /* The free buffer list */ @@ -372,18 +400,38 @@ static void pic32mx_timerpoll(struct pic32mx_driver_s *priv); static void pic32mx_response(struct pic32mx_driver_s *priv); static void pic32mx_rxdone(struct pic32mx_driver_s *priv); static void pic32mx_txdone(struct pic32mx_driver_s *priv); + +static inline void pic32mx_interrupt_process(struct pic32mx_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void pic32mx_interrupt_work(void *arg); +#endif static int pic32mx_interrupt(int irq, void *context); /* Watchdog timer expirations */ -static void pic32mx_polltimer(int argc, uint32_t arg, ...); -static void pic32mx_txtimeout(int argc, uint32_t arg, ...); +static inline void pic32mx_txtimeout_process(struct pic32mx_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void pic32mx_txtimeout_work(void *arg); +#endif +static void pic32mx_txtimeout_expiry(int argc, uint32_t arg, ...); + +static inline void pic32mx_poll_process(struct pic32mx_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void pic32mx_poll_work(void *arg); +#endif +static void pic32mx_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ static int pic32mx_ifup(struct net_driver_s *dev); static int pic32mx_ifdown(struct net_driver_s *dev); + +static inline void pic32mx_txavail_process(struct pic32mx_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void pic32mx_txavail_work(void *arg); +#endif static int pic32mx_txavail(struct net_driver_s *dev); + #ifdef CONFIG_NET_IGMP static int pic32mx_addmac(struct net_driver_s *dev, const uint8_t *mac); static int pic32mx_rmmac(struct net_driver_s *dev, const uint8_t *mac); @@ -1055,8 +1103,8 @@ static int pic32mx_transmit(struct pic32mx_driver_s *priv) /* Setup the TX timeout watchdog (perhaps restarting the timer) */ - (void)wd_start(priv->pd_txtimeout, PIC32MX_TXTIMEOUT, pic32mx_txtimeout, - 1, (uint32_t)priv); + (void)wd_start(priv->pd_txtimeout, PIC32MX_TXTIMEOUT, + pic32mx_txtimeout_expiry, 1, (uint32_t)priv); return OK; } @@ -1634,33 +1682,27 @@ static void pic32mx_txdone(struct pic32mx_driver_s *priv) } /**************************************************************************** - * Function: pic32mx_interrupt + * Function: pic32mx_interrupt_process * * Description: - * Hardware interrupt handler + * Interrupt processing. This may be performed either within the interrupt + * handler or on the worker thread, depending upon the configuration * * Parameters: - * irq - Number of the IRQ that generated the interrupt - * context - Interrupt register state save info (architecture-specific) + * priv - Reference to the driver state structure * * Returned Value: - * OK on success + * None * * Assumptions: + * The network is locked. * ****************************************************************************/ -static int pic32mx_interrupt(int irq, void *context) +static inline void pic32mx_interrupt_process(struct pic32mx_driver_s *priv) { - register struct pic32mx_driver_s *priv; uint32_t status; -#if CONFIG_PIC32MX_NINTERFACES > 1 -# error "A mechanism to associate and interface with an IRQ is needed" -#else - priv = &g_ethdrvr[0]; -#endif - /* Get the interrupt status (zero means no interrupts pending). */ status = pic32mx_getreg(PIC32MX_ETH_IRQ); @@ -1789,43 +1831,148 @@ static int pic32mx_interrupt(int irq, void *context) * (ETHCON1:0) bit to decrement the BUFCNT counter. Writing a ‘0’ or a * ‘1’ has no effect. */ - } /* Clear the pending interrupt */ -# if CONFIG_PIC32MX_NINTERFACES > 1 +#if CONFIG_PIC32MX_NINTERFACES > 1 up_clrpend_irq(priv->pd_irqsrc); -# else +#else up_clrpend_irq(PIC32MX_IRQSRC_ETH); -# endif - - return OK; +#endif } /**************************************************************************** - * Function: pic32mx_txtimeout + * Function: pic32mx_interrupt_work * * Description: - * Our TX watchdog timed out. Called from the timer interrupt handler. - * The last TX never completed. Reset the hardware and start again. + * Perform interrupt related work from the worker thread * * Parameters: - * argc - The number of available arguments - * arg - The first argument + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: - * Global interrupts are disabled by the watchdog logic. + * The network is locked. * ****************************************************************************/ -static void pic32mx_txtimeout(int argc, uint32_t arg, ...) +#ifdef CONFIG_NET_NOINTS +static void pic32mx_interrupt_work(void *arg) { struct pic32mx_driver_s *priv = (struct pic32mx_driver_s *)arg; + net_lock_t state; + + /* Process pending Ethernet interrupts */ + + state = net_lock(); + pic32mx_interrupt_process(priv); + net_unlock(state); + + /* Re-enable Ethernet interrupts */ + +#if CONFIG_PIC32MX_NINTERFACES > 1 + up_enable_irq(priv->pd_irqsrc); +#else + up_enable_irq(PIC32MX_IRQSRC_ETH); +#endif +} +#endif + +/**************************************************************************** + * Function: pic32mx_interrupt + * + * Description: + * Hardware interrupt handler + * + * Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * OK on success + * + * Assumptions: + * + ****************************************************************************/ + +static int pic32mx_interrupt(int irq, void *context) +{ + struct pic32mx_driver_s *priv; + uint32_t status; + +#if CONFIG_PIC32MX_NINTERFACES > 1 +# error "A mechanism to associate an interface with an IRQ is needed" +#else + priv = &g_ethdrvr[0]; +#endif + +#ifdef CONFIG_NET_NOINTS + /* Disable further Ethernet interrupts. Because Ethernet interrupts are + * also disabled if the TX timeout event occurs, there can be no race + * condition here. + */ + +#if CONFIG_PIC32MX_NINTERFACES > 1 + up_disable_irq(priv->pd_irqsrc); +#else + up_disable_irq(PIC32MX_IRQSRC_ETH); +#endif + + /* Get the interrupt status (zero means no interrupts pending). */ + + status = pic32mx_getreg(PIC32MX_ETH_IRQ); + + /* Determine if a TX transfer just completed */ + + if ((status & ETH_INT_TXDONE) != 0) + { + /* If a TX transfer just completed, then cancel the TX timeout so + * there will be no race condition between any subsequent timeout + * expiration and the deferred interrupt processing. + */ + + wd_cancel(priv->pd_txtimeout); + } + + /* Cancel any pending poll work */ + + work_cancel(HPWORK, &priv->pd_work); + + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->pd_work, pic32mx_interrupt_work, priv, 0); + +#else + /* Process the interrupt now */ + pic32mx_interrupt_process(priv); +#endif + + return OK; +} + +/**************************************************************************** + * Function: pic32mx_txtimeout_process + * + * Description: + * Process a TX timeout. Called from the either the watchdog timer + * expiration logic or from the worker thread, depending upon the + * configuration. The timeout means that the last TX never completed. + * Reset the hardware and start again. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void pic32mx_txtimeout_process(struct pic32mx_driver_s *priv) +{ /* Increment statistics and dump debug info */ NETDEV_TXTIMEOUTS(&priv->pd_dev); @@ -1837,8 +1984,8 @@ static void pic32mx_txtimeout(int argc, uint32_t arg, ...) (void)pic32mx_ifup(&priv->pd_dev); - /* Then poll the network for new XMIT data (We are guaranteed to have a free - * buffer here). + /* Then poll the network for new XMIT data (We are guaranteed to have + * a free buffer here). */ pic32mx_poll(priv); @@ -1846,10 +1993,42 @@ static void pic32mx_txtimeout(int argc, uint32_t arg, ...) } /**************************************************************************** - * Function: pic32mx_polltimer + * Function: pic32mx_txtimeout_work * * Description: - * Periodic timer handler. Called from the timer interrupt handler. + * Perform TX timeout related work from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void pic32mx_txtimeout_work(void *arg) +{ + struct pic32mx_driver_s *priv = (struct pic32mx_driver_s *)arg; + net_lock_t state; + + /* Process pending Ethernet interrupts */ + + state = net_lock(); + pic32mx_txtimeout_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: pic32mx_txtimeout_expiry + * + * Description: + * Our TX watchdog timed out. Called from the timer interrupt handler. + * The last TX never completed. Reset the hardware and start again. * * Parameters: * argc - The number of available arguments @@ -1863,10 +2042,57 @@ static void pic32mx_txtimeout(int argc, uint32_t arg, ...) * ****************************************************************************/ -static void pic32mx_polltimer(int argc, uint32_t arg, ...) +static void pic32mx_txtimeout_expiry(int argc, wdparm_t arg, ...) { struct pic32mx_driver_s *priv = (struct pic32mx_driver_s *)arg; +#ifdef CONFIG_NET_NOINTS + /* Disable further Ethernet interrupts. This will prevent some race + * conditions with interrupt work. There is still a potential race + * condition with interrupt work that is already queued and in progress. + */ + +#if CONFIG_PIC32MX_NINTERFACES > 1 + up_disable_irq(priv->pd_irqsrc); +#else + up_disable_irq(PIC32MX_IRQSRC_ETH); +#endif + + /* Cancel any pending poll or interrupt work. This will have no effect + * on work that has already been started. + */ + + work_cancel(ETHWORK, &priv->pd_work); + + /* Schedule to perform the TX timeout processing on the worker thread. */ + + work_queue(ETHWORK, &priv->pd_work, pic32mx_txtimeout_work, priv, 0); +#else + /* Process the timeout now */ + + pic32mx_txtimeout_process(priv); +#endif +} + +/**************************************************************************** + * Function: pic32mx_poll_process + * + * Description: + * Perform the periodic poll. This may be called either from watchdog + * timer logic or from the worker thread, depending upon the configuration. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static inline void pic32mx_poll_process(struct pic32mx_driver_s *priv) +{ /* Check if the next Tx descriptor is available. We cannot perform the Tx * poll if we are unable to accept another packet for transmission. */ @@ -1883,7 +2109,89 @@ static void pic32mx_polltimer(int argc, uint32_t arg, ...) /* Setup the watchdog poll timer again */ - (void)wd_start(priv->pd_txpoll, PIC32MX_WDDELAY, pic32mx_polltimer, 1, arg); + (void)wd_start(priv->pd_txpoll, PIC32MX_WDDELAY, pic32mx_poll_expiry, + 1, priv); +} + +/**************************************************************************** + * Function: pic32mx_poll_work + * + * Description: + * Perform periodic polling from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void pic32mx_poll_work(void *arg) +{ + struct pic32mx_driver_s *priv = (struct pic32mx_driver_s *)arg; + net_lock_t state; + + /* Perform the poll */ + + state = net_lock(); + pic32mx_poll_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: pic32mx_poll_expiry + * + * Description: + * Periodic timer handler. Called from the timer interrupt handler. + * + * Parameters: + * argc - The number of available arguments + * arg - The first argument + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * + ****************************************************************************/ + +static void pic32mx_poll_expiry(int argc, wdparm_t arg, ...) +{ + struct pic32mx_driver_s *priv = (struct pic32mx_driver_s *)arg; + +#ifdef CONFIG_NET_NOINTS + /* Is our single work structure available? It may not be if there are + * pending interrupt actions. + */ + + if (work_available(&priv->pd_work)) + { + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->pd_work, pic32mx_poll_work, priv, 0); + } + else + { + /* No.. Just re-start the watchdog poll timer, missing one polling + * cycle. + */ + + (void)wd_start(priv->pd_txpoll, PIC32MX_WDDELAY, pic32mx_poll_expiry, + 1, arg); + } + +#else + /* Process the interrupt now */ + + pic32mx_poll_process(priv); +#endif } /**************************************************************************** @@ -2175,12 +2483,13 @@ static int pic32mx_ifup(struct net_driver_s *dev) /* Set and activate a timer process */ - (void)wd_start(priv->pd_txpoll, PIC32MX_WDDELAY, pic32mx_polltimer, 1, + (void)wd_start(priv->pd_txpoll, PIC32MX_WDDELAY, pic32mx_poll_expiry, 1, (uint32_t)priv); /* Finally, enable the Ethernet interrupt at the interrupt controller */ priv->pd_ifup = true; + #if CONFIG_PIC32MX_NINTERFACES > 1 up_enable_irq(priv->pd_irqsrc); #else @@ -2233,15 +2542,13 @@ static int pic32mx_ifdown(struct net_driver_s *dev) } /**************************************************************************** - * Function: pic32mx_txavail + * Function: pic32mx_txavail_process * * Description: - * Driver callback invoked when new TX data is available. This is a - * stimulus perform an out-of-cycle poll and, thereby, reduce the TX - * latency. + * Perform an out-of-cycle poll. * * Parameters: - * dev - Reference to the NuttX driver state structure + * dev - Reference to the NuttX driver state structure * * Returned Value: * None @@ -2251,17 +2558,8 @@ static int pic32mx_ifdown(struct net_driver_s *dev) * ****************************************************************************/ -static int pic32mx_txavail(struct net_driver_s *dev) +static inline void pic32mx_txavail_process(struct pic32mx_driver_s *priv) { - struct pic32mx_driver_s *priv = (struct pic32mx_driver_s *)dev->d_private; - irqstate_t flags; - - /* Disable interrupts because this function may be called from interrupt - * level processing. - */ - - flags = enter_critical_section(); - /* Ignore the notification if the interface is not yet up */ if (priv->pd_ifup) @@ -2277,8 +2575,90 @@ static int pic32mx_txavail(struct net_driver_s *dev) pic32mx_poll(priv); } } +} + +/**************************************************************************** + * Function: pic32mx_txavail_work + * + * Description: + * Perform an out-of-cycle poll on the worker thread. + * + * Parameters: + * arg - Reference to the NuttX driver state structure (cast to void*) + * + * Returned Value: + * None + * + * Assumptions: + * Called on the higher priority worker thread. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void pic32mx_txavail_work(void *arg) +{ + struct pic32mx_driver_s *priv = (struct pic32mx_driver_s *)arg; + net_lock_t state; + + /* Perform the poll */ + + state = net_lock(); + pic32mx_txavail_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: pic32mx_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static int pic32mx_txavail(struct net_driver_s *dev) +{ + struct pic32mx_driver_s *priv = (struct pic32mx_driver_s *)dev->d_private; + +#ifdef CONFIG_NET_NOINTS + /* Is our single work structure available? It may not be if there are + * pending interrupt actions and we will have to ignore the Tx + * availability action. + */ + + if (work_available(&priv->pd_work)) + { + /* Schedule to serialize the poll on the worker thread. */ + + work_queue(ETHWORK, &priv->pd_work, pic32mx_txavail_work, priv, 0); + } + +#else + irqstate_t flags; + /* Disable interrupts because this function may be called from interrupt + * level processing. + */ + + flags = enter_critical_section(); + + /* Perform the out-of-cycle poll now */ + + pic32mx_txavail_process(priv); leave_critical_section(flags); +#endif + return OK; } diff --git a/arch/mips/src/pic32mz/Kconfig b/arch/mips/src/pic32mz/Kconfig index 70dcf7d076..0ea6cfeae4 100644 --- a/arch/mips/src/pic32mz/Kconfig +++ b/arch/mips/src/pic32mz/Kconfig @@ -265,7 +265,7 @@ config PIC32MZ_CTMU bool "Charge Time Measurement Unit (CMTU)" default n -endmenu # PIC32MX Peripheral Support +endmenu # PIC32MZ Peripheral Support menuconfig PIC32MZ_GPIOIRQ bool "GPIO Interrupt Support" @@ -397,13 +397,6 @@ config NET_WOL ---help--- Enable Wake-up on LAN (not fully implemented). -config NET_REGDEBUG - bool "Register level debug" - default n - depends on PIC32MZ_ETHERNET && DEBUG_NET_INFO - ---help--- - Enabled low level register debug. Also needs CONFIG_DEBUG_FEATURES. - config NET_HASH bool "Hash" default n @@ -419,6 +412,33 @@ config PIC32MZ_MULTICAST Enable receipt of multicast (and unicast) frames. Automatically set if NET_IGMP is selected. +choice + prompt "Work queue" + default PIC32MZ_ETHERNET_LPWORK if SCHED_LPWORK + default PIC32MZ_ETHERNET_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + depends on SCHED_WORKQUEUE + ---help--- + Work queue support is required to use the Ethernet driver. If the + low priority work queue is available, then it should be used by the + driver. + +config PIC32MZ_ETHERNET_HPWORK + bool "High priority" + depends on SCHED_HPWORK + +config PIC32MZ_ETHERNET_LPWORK + bool "Low priority" + depends on SCHED_LPWORK + +endchoice # Work queue + +config NET_REGDEBUG + bool "Register level debug" + default n + depends on PIC32MZ_ETHERNET && DEBUG_NET_INFO + ---help--- + Enabled low level register debug. Also needs CONFIG_DEBUG_FEATURES. + endmenu # PIC32MZ PHY/Ethernet device driver settings menu "Device Configuration 0 (DEVCFG0)" diff --git a/arch/mips/src/pic32mz/pic32mz-ethernet.c b/arch/mips/src/pic32mz/pic32mz-ethernet.c index fe245e5a74..649a2314ca 100644 --- a/arch/mips/src/pic32mz/pic32mz-ethernet.c +++ b/arch/mips/src/pic32mz/pic32mz-ethernet.c @@ -55,6 +55,11 @@ #include #include #include + +#ifdef CONFIG_NET_NOINTS +# include +#endif + #include #include #include @@ -81,6 +86,26 @@ * Pre-processor Definitions ****************************************************************************/ /* Configuration ************************************************************/ +/* If processing is not done at the interrupt level, then work queue support + * is required. + */ + +#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required in this configuration (CONFIG_SCHED_WORKQUEUE) +#endif + +/* Use the low priority work queue if possible */ + +#if defined(CONFIG_SCHED_WORKQUEUE) +# if defined(CONFIG_PIC32MZ_ETHERNET_HPWORK) +# define ETHWORK HPWORK +# elif defined(CONFIG_PIC32MZ_ETHERNET_LPWORK) +# define ETHWORK LPWORK +# else +# error Neither CONFIG_PIC32MZ_ETHERNET_HPWORK nor CONFIG_PIC32MZ_ETHERNET_LPWORK defined +# endif +#endif + /* CONFIG_PIC32MZ_NINTERFACES determines the number of physical interfaces * that will be supported -- unless it is more than actually supported by the * hardware! @@ -328,6 +353,9 @@ struct pic32mz_driver_s uint32_t pd_inten; /* Shadow copy of INTEN register */ WDOG_ID pd_txpoll; /* TX poll timer */ WDOG_ID pd_txtimeout; /* TX timeout timer */ +#ifdef CONFIG_NET_NOINTS + struct work_s pd_work; /* For deferring work to the work queue */ +#endif sq_queue_t pd_freebuffers; /* The free buffer list */ @@ -399,18 +427,38 @@ static void pic32mz_timerpoll(struct pic32mz_driver_s *priv); static void pic32mz_response(struct pic32mz_driver_s *priv); static void pic32mz_rxdone(struct pic32mz_driver_s *priv); static void pic32mz_txdone(struct pic32mz_driver_s *priv); + +static inline void pic32mz_interrupt_process(struct pic32mz_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void pic32mz_interrupt_work(void *arg); +#endif static int pic32mz_interrupt(int irq, void *context); /* Watchdog timer expirations */ -static void pic32mz_polltimer(int argc, uint32_t arg, ...); -static void pic32mz_txtimeout(int argc, uint32_t arg, ...); +static inline void pic32mz_txtimeout_process(struct pic32mz_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void pic32mz_txtimeout_work(void *arg); +#endif +static void pic32mz_txtimeout_expiry(int argc, uint32_t arg, ...); + +static inline void pic32mz_poll_process(struct pic32mz_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void pic32mz_poll_work(void *arg); +#endif +static void pic32mz_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ static int pic32mz_ifup(struct net_driver_s *dev); static int pic32mz_ifdown(struct net_driver_s *dev); + +static inline void pic32mz_txavail_process(struct pic32mz_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void pic32mz_txavail_work(void *arg); +#endif static int pic32mz_txavail(struct net_driver_s *dev); + #ifdef CONFIG_NET_IGMP static int pic32mz_addmac(struct net_driver_s *dev, const uint8_t *mac); static int pic32mz_rmmac(struct net_driver_s *dev, const uint8_t *mac); @@ -1082,7 +1130,7 @@ static int pic32mz_transmit(struct pic32mz_driver_s *priv) /* Setup the TX timeout watchdog (perhaps restarting the timer) */ - (void)wd_start(priv->pd_txtimeout, PIC32MZ_TXTIMEOUT, pic32mz_txtimeout, + (void)wd_start(priv->pd_txtimeout, PIC32MZ_TXTIMEOUT, pic32mz_txtimeout_expiry, 1, (uint32_t)priv); return OK; @@ -1661,33 +1709,27 @@ static void pic32mz_txdone(struct pic32mz_driver_s *priv) } /**************************************************************************** - * Function: pic32mz_interrupt + * Function: pic32mz_interrupt_process * * Description: - * Hardware interrupt handler + * Interrupt processing. This may be performed either within the interrupt + * handler or on the worker thread, depending upon the configuration * * Parameters: - * irq - Number of the IRQ that generated the interrupt - * context - Interrupt register state save info (architecture-specific) + * priv - Reference to the driver state structure * * Returned Value: - * OK on success + * None * * Assumptions: + * The network is locked. * ****************************************************************************/ -static int pic32mz_interrupt(int irq, void *context) +static inline void pic32mz_interrupt_process(struct pic32mz_driver_s *priv) { - register struct pic32mz_driver_s *priv; uint32_t status; -#if CONFIG_PIC32MZ_NINTERFACES > 1 -# error "A mechanism to associate and interface with an IRQ is needed" -#else - priv = &g_ethdrvr[0]; -#endif - /* Get the interrupt status (zero means no interrupts pending). */ status = pic32mz_getreg(PIC32MZ_ETH_IRQ); @@ -1816,43 +1858,148 @@ static int pic32mz_interrupt(int irq, void *context) * (ETHCON1:0) bit to decrement the BUFCNT counter. Writing a ‘0’ or a * ‘1’ has no effect. */ - } /* Clear the pending interrupt */ -# if CONFIG_PIC32MZ_NINTERFACES > 1 +#if CONFIG_PIC32MZ_NINTERFACES > 1 up_clrpend_irq(priv->pd_irqsrc); -# else +#else up_clrpend_irq(PIC32MZ_IRQ_ETH); -# endif - - return OK; +#endif } /**************************************************************************** - * Function: pic32mz_txtimeout + * Function: pic32mz_interrupt_work * * Description: - * Our TX watchdog timed out. Called from the timer interrupt handler. - * The last TX never completed. Reset the hardware and start again. + * Perform interrupt related work from the worker thread * * Parameters: - * argc - The number of available arguments - * arg - The first argument + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: - * Global interrupts are disabled by the watchdog logic. + * The network is locked. * ****************************************************************************/ -static void pic32mz_txtimeout(int argc, uint32_t arg, ...) +#ifdef CONFIG_NET_NOINTS +static void pic32mz_interrupt_work(void *arg) { struct pic32mz_driver_s *priv = (struct pic32mz_driver_s *)arg; + net_lock_t state; + + /* Process pending Ethernet interrupts */ + + state = net_lock(); + pic32mz_interrupt_process(priv); + net_unlock(state); + + /* Re-enable Ethernet interrupts */ + +#if CONFIG_PIC32MZ_NINTERFACES > 1 + up_enable_irq(priv->pd_irqsrc); +#else + up_enable_irq(PIC32MZ_IRQ_ETH); +#endif +} +#endif + +/**************************************************************************** + * Function: pic32mz_interrupt + * + * Description: + * Hardware interrupt handler + * + * Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * OK on success + * + * Assumptions: + * + ****************************************************************************/ + +static int pic32mz_interrupt(int irq, void *context) +{ + struct pic32mz_driver_s *priv; + uint32_t status; + +#if CONFIG_PIC32MZ_NINTERFACES > 1 +# error "A mechanism to associate an interface with an IRQ is needed" +#else + priv = &g_ethdrvr[0]; +#endif + +#ifdef CONFIG_NET_NOINTS + /* Disable further Ethernet interrupts. Because Ethernet interrupts are + * also disabled if the TX timeout event occurs, there can be no race + * condition here. + */ + +#if CONFIG_PIC32MZ_NINTERFACES > 1 + up_disable_irq(priv->pd_irqsrc); +#else + up_disable_irq(PIC32MZ_IRQ_ETH); +#endif + + /* Get the interrupt status (zero means no interrupts pending). */ + + status = pic32mz_getreg(PIC32MZ_ETH_IRQ); + + /* Determine if a TX transfer just completed */ + + if ((status & ETH_INT_TXDONE) != 0) + { + /* If a TX transfer just completed, then cancel the TX timeout so + * there will be no race condition between any subsequent timeout + * expiration and the deferred interrupt processing. + */ + + wd_cancel(priv->pd_txtimeout); + } + + /* Cancel any pending poll work */ + + work_cancel(HPWORK, &priv->pd_work); + + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->pd_work, pic32mz_interrupt_work, priv, 0); + +#else + /* Process the interrupt now */ + pic32mz_interrupt_process(priv); +#endif + + return OK; +} + +/**************************************************************************** + * Function: pic32mz_txtimeout_process + * + * Description: + * Process a TX timeout. Called from the either the watchdog timer + * expiration logic or from the worker thread, depending upon the + * configuration. The timeout means that the last TX never completed. + * Reset the hardware and start again. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void pic32mz_txtimeout_process(struct pic32mz_driver_s *priv) +{ /* Increment statistics and dump debug info */ NETDEV_TXTIMEOUTS(&priv->pd_dev); @@ -1873,10 +2020,42 @@ static void pic32mz_txtimeout(int argc, uint32_t arg, ...) } /**************************************************************************** - * Function: pic32mz_polltimer + * Function: pic32mz_txtimeout_work * * Description: - * Periodic timer handler. Called from the timer interrupt handler. + * Perform TX timeout related work from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void pic32mz_txtimeout_work(void *arg) +{ + struct pic32mz_driver_s *priv = (struct pic32mz_driver_s *)arg; + net_lock_t state; + + /* Process pending Ethernet interrupts */ + + state = net_lock(); + pic32mz_txtimeout_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: pic32mz_txtimeout_expiry + * + * Description: + * Our TX watchdog timed out. Called from the timer interrupt handler. + * The last TX never completed. Reset the hardware and start again. * * Parameters: * argc - The number of available arguments @@ -1890,19 +2069,66 @@ static void pic32mz_txtimeout(int argc, uint32_t arg, ...) * ****************************************************************************/ -static void pic32mz_polltimer(int argc, uint32_t arg, ...) +static void pic32mz_txtimeout_expiry(int argc, wdparm_t arg, ...) { struct pic32mz_driver_s *priv = (struct pic32mz_driver_s *)arg; +#ifdef CONFIG_NET_NOINTS + /* Disable further Ethernet interrupts. This will prevent some race + * conditions with interrupt work. There is still a potential race + * condition with interrupt work that is already queued and in progress. + */ + +#if CONFIG_PIC32MZ_NINTERFACES > 1 + up_disable_irq(priv->pd_irqsrc); +#else + up_disable_irq(PIC32MZ_IRQ_ETH); +#endif + + /* Cancel any pending poll or interrupt work. This will have no effect + * on work that has already been started. + */ + + work_cancel(ETHWORK, &priv->pd_work); + + /* Schedule to perform the TX timeout processing on the worker thread. */ + + work_queue(ETHWORK, &priv->pd_work, pic32mz_txtimeout_work, priv, 0); +#else + /* Process the timeout now */ + + pic32mz_txtimeout_process(priv); +#endif +} + +/**************************************************************************** + * Function: pic32mz_poll_process + * + * Description: + * Perform the periodic poll. This may be called either from watchdog + * timer logic or from the worker thread, depending upon the configuration. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static inline void pic32mz_poll_process(struct pic32mz_driver_s *priv) +{ /* Check if the next Tx descriptor is available. We cannot perform the Tx * poll if we are unable to accept another packet for transmission. */ if (pic32mz_txdesc(priv) != NULL) { - /* If so, update TCP timing states and poll the network for new XMIT data. Hmmm.. - * might be bug here. Does this mean if there is a transmit in progress, - * we will missing TCP time state updates? + /* If so, update TCP timing states and poll the network for new XMIT + * data. Hmmm.. might be bug here. Does this mean if there is a + * transmit in progress, we will missing TCP time state updates? */ pic32mz_timerpoll(priv); @@ -1910,7 +2136,88 @@ static void pic32mz_polltimer(int argc, uint32_t arg, ...) /* Setup the watchdog poll timer again */ - (void)wd_start(priv->pd_txpoll, PIC32MZ_WDDELAY, pic32mz_polltimer, 1, arg); + (void)wd_start(priv->pd_txpoll, PIC32MZ_WDDELAY, pic32mz_poll_expiry, + 1, priv); +} + +/**************************************************************************** + * Function: pic32mz_poll_work + * + * Description: + * Perform periodic polling from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void pic32mz_poll_work(void *arg) +{ + struct pic32mz_driver_s *priv = (struct pic32mz_driver_s *)arg; + net_lock_t state; + + /* Perform the poll */ + + state = net_lock(); + pic32mz_poll_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: pic32mz_poll_expiry + * + * Description: + * Periodic timer handler. Called from the timer interrupt handler. + * + * Parameters: + * argc - The number of available arguments + * arg - The first argument + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * + ****************************************************************************/ + +static void pic32mz_poll_expiry(int argc, wdparm_t arg, ...) +{ + struct pic32mz_driver_s *priv = (struct pic32mz_driver_s *)arg; + +#ifdef CONFIG_NET_NOINTS + /* Is our single work structure available? It may not be if there are + * pending interrupt actions. + */ + + if (work_available(&priv->pd_work)) + { + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->pd_work, pic32mz_poll_work, priv, 0); + } + else + { + /* No.. Just re-start the watchdog poll timer, missing one polling + * cycle. + */ + + (void)wd_start(priv->pd_txpoll, PIC32MZ_WDDELAY, pic32mz_poll_expiry, 1, arg); + } + +#else + /* Process the interrupt now */ + + pic32mz_poll_process(priv); +#endif } /**************************************************************************** @@ -2207,17 +2514,19 @@ static int pic32mz_ifup(struct net_driver_s *dev) /* Set and activate a timer process */ - (void)wd_start(priv->pd_txpoll, PIC32MZ_WDDELAY, pic32mz_polltimer, 1, + (void)wd_start(priv->pd_txpoll, PIC32MZ_WDDELAY, pic32mz_poll_expiry, 1, (uint32_t)priv); /* Finally, enable the Ethernet interrupt at the interrupt controller */ priv->pd_ifup = true; + #if CONFIG_PIC32MZ_NINTERFACES > 1 up_enable_irq(priv->pd_irqsrc); #else up_enable_irq(PIC32MZ_IRQ_ETH); #endif + return OK; } @@ -2265,15 +2574,13 @@ static int pic32mz_ifdown(struct net_driver_s *dev) } /**************************************************************************** - * Function: pic32mz_txavail + * Function: pic32mz_txavail_process * * Description: - * Driver callback invoked when new TX data is available. This is a - * stimulus perform an out-of-cycle poll and, thereby, reduce the TX - * latency. + * Perform an out-of-cycle poll. * * Parameters: - * dev - Reference to the NuttX driver state structure + * dev - Reference to the NuttX driver state structure * * Returned Value: * None @@ -2283,17 +2590,8 @@ static int pic32mz_ifdown(struct net_driver_s *dev) * ****************************************************************************/ -static int pic32mz_txavail(struct net_driver_s *dev) +static inline void pic32mz_txavail_process(struct pic32mz_driver_s *priv) { - struct pic32mz_driver_s *priv = (struct pic32mz_driver_s *)dev->d_private; - irqstate_t flags; - - /* Disable interrupts because this function may be called from interrupt - * level processing. - */ - - flags = enter_critical_section(); - /* Ignore the notification if the interface is not yet up */ if (priv->pd_ifup) @@ -2309,8 +2607,90 @@ static int pic32mz_txavail(struct net_driver_s *dev) pic32mz_poll(priv); } } +} + +/**************************************************************************** + * Function: pic32mz_txavail_work + * + * Description: + * Perform an out-of-cycle poll on the worker thread. + * + * Parameters: + * arg - Reference to the NuttX driver state structure (cast to void*) + * + * Returned Value: + * None + * + * Assumptions: + * Called on the higher priority worker thread. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void pic32mz_txavail_work(void *arg) +{ + struct pic32mz_driver_s *priv = (struct pic32mz_driver_s *)arg; + net_lock_t state; + /* Perform the poll */ + + state = net_lock(); + pic32mz_txavail_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: pic32mz_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static int pic32mz_txavail(struct net_driver_s *dev) +{ + struct pic32mz_driver_s *priv = (struct pic32mz_driver_s *)dev->d_private; + +#ifdef CONFIG_NET_NOINTS + /* Is our single work structure available? It may not be if there are + * pending interrupt actions and we will have to ignore the Tx + * availability action. + */ + + if (work_available(&priv->pd_work)) + { + /* Schedule to serialize the poll on the worker thread. */ + + work_queue(ETHWORK, &priv->pd_work, pic32mz_txavail_work, priv, 0); + } + +#else + irqstate_t flags; + + /* Disable interrupts because this function may be called from interrupt + * level processing. + */ + + flags = enter_critical_section(); + + /* Perform the out-of-cycle poll now */ + + pic32mz_txavail_process(priv); leave_critical_section(flags); +#endif + return OK; } diff --git a/configs/pic32mx-starterkit/nsh2/defconfig b/configs/pic32mx-starterkit/nsh2/defconfig index 6f56164ea3..1805838d32 100644 --- a/configs/pic32mx-starterkit/nsh2/defconfig +++ b/configs/pic32mx-starterkit/nsh2/defconfig @@ -246,6 +246,7 @@ CONFIG_PIC32MX_T1PRIO=16 # PIC32MX PHY/Ethernet device driver settings # # CONFIG_PIC32MX_MULTICAST is not set +CONFIG_PIC32MX_ETHERNET_HPWORK=y # # Device Configuration 0 (DEVCFG0) @@ -422,6 +423,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -430,6 +432,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -441,8 +444,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -574,7 +580,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set @@ -668,7 +673,7 @@ CONFIG_RAMLOG_SYSLOG=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/pic32mx7mmb/nsh/defconfig b/configs/pic32mx7mmb/nsh/defconfig index 19214abc8a..5f406d3360 100644 --- a/configs/pic32mx7mmb/nsh/defconfig +++ b/configs/pic32mx7mmb/nsh/defconfig @@ -254,6 +254,7 @@ CONFIG_PIC32MX_USBPRIO=16 # PIC32MX PHY/Ethernet device driver settings # # CONFIG_PIC32MX_MULTICAST is not set +CONFIG_PIC32MX_ETHERNET_HPWORK=y # # Device Configuration 0 (DEVCFG0) @@ -431,6 +432,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -439,6 +441,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -450,8 +453,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -593,7 +599,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set @@ -731,7 +736,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/drivers/net/skeleton.c b/drivers/net/skeleton.c index 9ef4e40c0a..1b9e1c7866 100644 --- a/drivers/net/skeleton.c +++ b/drivers/net/skeleton.c @@ -53,13 +53,14 @@ #include #include #include -#include -#include #ifdef CONFIG_NET_NOINTS # include #endif +#include +#include + #ifdef CONFIG_NET_PKT # include #endif @@ -185,11 +186,13 @@ static void skel_poll_expiry(int argc, wdparm_t arg, ...); static int skel_ifup(FAR struct net_driver_s *dev); static int skel_ifdown(FAR struct net_driver_s *dev); + static inline void skel_txavail_process(FAR struct skel_driver_s *priv); #ifdef CONFIG_NET_NOINTS static void skel_txavail_work(FAR void *arg); #endif static int skel_txavail(FAR struct net_driver_s *dev); + #if defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_ICMPv6) static int skel_addmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac); #ifdef CONFIG_NET_IGMP @@ -610,7 +613,7 @@ static int skel_interrupt(int irq, FAR void *context) { /* If a TX transfer just completed, then cancel the TX timeout so - * there will be do race condition between any subsequent timeout + * there will be no race condition between any subsequent timeout * expiration and the deferred interrupt processing. */ -- GitLab From 41e35c88bfdee75535b04282fcb8845d0fce3cad Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 3 Dec 2016 10:43:35 -0600 Subject: [PATCH 578/734] eZ80 Ethernet now supports CONFIG_NET_NOINTS --- TODO | 4 +- arch/mips/src/pic32mz/pic32mz-ethernet.c | 2 + arch/z80/src/ez80/Kconfig | 20 + arch/z80/src/ez80/Make.defs | 2 +- arch/z80/src/ez80/ez80_emac.c | 652 +++++++++++++++++++++-- arch/z80/src/ez80/ez80_irqsave.asm | 2 +- configs/ez80f910200zco/dhcpd/defconfig | 13 +- configs/ez80f910200zco/httpd/defconfig | 13 +- configs/ez80f910200zco/nettest/defconfig | 13 +- configs/ez80f910200zco/nsh/defconfig | 13 +- configs/ez80f910200zco/poll/defconfig | 13 +- include/debug.h | 2 +- 12 files changed, 678 insertions(+), 71 deletions(-) diff --git a/TODO b/TODO index a364e4e8ed..36347d1036 100644 --- a/TODO +++ b/TODO @@ -1059,12 +1059,12 @@ o Network (net/, drivers/net) TIVA ----------------------- ------ LM3S YES NO TM4C YES YES - eZ80 NO NO + eZ80 YES NO Kinetis YES YES (not tested) LPC17xx YES YES (not tested) LPC43xx YES YES (not tested) DMxxx NIC NO NO - PIC32 NO NO + PIC32 YES NO SAM3/4 YES YES SAMA5D ----------------------- ------ EMACA YES YES (not tested) diff --git a/arch/mips/src/pic32mz/pic32mz-ethernet.c b/arch/mips/src/pic32mz/pic32mz-ethernet.c index 649a2314ca..356edab2d1 100644 --- a/arch/mips/src/pic32mz/pic32mz-ethernet.c +++ b/arch/mips/src/pic32mz/pic32mz-ethernet.c @@ -3174,6 +3174,7 @@ static inline int pic32mz_phyinit(struct pic32mz_driver_s *priv) nerr("ERROR: No PHY detected\n"); return -ENODEV; } + ninfo("phyaddr: %d\n", phyaddr); /* Save the discovered PHY device address */ @@ -3187,6 +3188,7 @@ static inline int pic32mz_phyinit(struct pic32mz_driver_s *priv) { return ret; } + pic32mz_showmii(phyaddr, "After reset"); /* Set the MII/RMII operation mode. This usually requires access to a diff --git a/arch/z80/src/ez80/Kconfig b/arch/z80/src/ez80/Kconfig index 7529e2c7ad..759160a512 100644 --- a/arch/z80/src/ez80/Kconfig +++ b/arch/z80/src/ez80/Kconfig @@ -117,6 +117,26 @@ config ARCH_MCFILTER ---help--- Enables multicast MAC address filtering (not fully implemented) +choice + prompt "Work queue" + default EZ80_EMAC_LPWORK if SCHED_LPWORK + default EZ80_EMAC_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + depends on SCHED_WORKQUEUE + ---help--- + Work queue support is required to use the Ethernet driver. If the + low priority work queue is available, then it should be used by the + driver. + +config EZ80_EMAC_HPWORK + bool "High priority" + depends on SCHED_HPWORK + +config EZ80_EMAC_LPWORK + bool "Low priority" + depends on SCHED_LPWORK + +endchoice # Work queue + endif # EZ80_EMAC config ARCH_TIMERHOOK diff --git a/arch/z80/src/ez80/Make.defs b/arch/z80/src/ez80/Make.defs index 7e79e19d65..5b4defd8e7 100644 --- a/arch/z80/src/ez80/Make.defs +++ b/arch/z80/src/ez80/Make.defs @@ -44,7 +44,7 @@ CMN_CSRCS += up_reprioritizertr.c up_idle.c up_assert.c up_doirq.c CMN_CSRCS += up_mdelay.c up_stackframe.c up_udelay.c up_usestack.c CMN_CSRCS += up_puts.c -CHIP_ASRCS = ez80_startup.asm ez80_io.asm ez80_up_irq_save.asm +CHIP_ASRCS = ez80_startup.asm ez80_io.asm ez80_irqsave.asm CHIP_ASRCS += ez80_saveusercontext.asm ez80_restorecontext.asm ifeq ($(CONFIG_ARCH_CHIP_EZ80F91),y) CHIP_ASRCS += ez80f91_init.asm diff --git a/arch/z80/src/ez80/ez80_emac.c b/arch/z80/src/ez80/ez80_emac.c index 0020991551..f5655fdc49 100644 --- a/arch/z80/src/ez80/ez80_emac.c +++ b/arch/z80/src/ez80/ez80_emac.c @@ -56,6 +56,11 @@ #include #include #include + +#ifdef CONFIG_NET_NOINTS +# include +#endif + #include #include #include @@ -75,6 +80,26 @@ /* Configuration ************************************************************/ +/* If processing is not done at the interrupt level, then work queue support + * is required. + */ + +#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required in this configuration (CONFIG_SCHED_WORKQUEUE) +#endif + +/* Use the low priority work queue if possible */ + +#if defined(CONFIG_SCHED_WORKQUEUE) +# if defined(CONFIG_EZ80_EMAC_HPWORK) +# define ETHWORK HPWORK +# elif defined(CONFIG_EZ80_EMAC_LPWORK) +# define ETHWORK LPWORK +# else +# error Neither CONFIG_EZ80_EMAC_HPWORK nor CONFIG_EZ80_EMAC_LPWORK defined +# endif +#endif + #ifndef CONFIG_EZ80_RAMADDR # define CONFIG_EZ80_RAMADDR EZ80_EMACSRAM #endif @@ -321,6 +346,12 @@ struct ez80emac_driver_s WDOG_ID txpoll; /* TX poll timer */ WDOG_ID txtimeout; /* TX timeout timer */ +#ifdef CONFIG_NET_NOINTS + struct work_s txwork; /* For deferring Tx-related work to the work queue */ + struct work_s rxwork; /* For deferring Rx-related work to the work queue */ + struct work_s syswork; /* For deferring system work to the work queue */ +#endif + #if defined(CONFIG_DEBUG_FEATURES) && defined(CONFIG_DEBUG_NET) struct ez80mac_statistics_s stat; #endif @@ -375,20 +406,49 @@ static int ez80emac_receive(struct ez80emac_driver_s *priv); /* Interrupt handling */ +static inline void ez80emac_txinterrupt_process(FAR struct ez80emac_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void ez80emac_txinterrupt_work(FAR void *arg); +#endif static int ez80emac_txinterrupt(int irq, FAR void *context); + +static inline void ez80emac_rxinterrupt_process(FAR struct ez80emac_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void ez80emac_rxinterrupt_work(FAR void *arg); +#endif static int ez80emac_rxinterrupt(int irq, FAR void *context); + +static inline void ez80emac_sysinterrupt_process(FAR struct ez80emac_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void ez80emac_sysinterrupt_work(FAR void *arg); +#endif static int ez80emac_sysinterrupt(int irq, FAR void *context); /* Watchdog timer expirations */ -static void ez80emac_polltimer(int argc, uint32_t arg, ...); -static void ez80emac_txtimeout(int argc, uint32_t arg, ...); +static inline void ez80emac_txtimeout_process(FAR struct ez80emac_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void ez80emac_txtimeout_work(FAR void *arg); +#endif +static void ez80emac_txtimeout_expiry(int argc, uint32_t arg, ...); + +static inline void ez80emac_poll_process(FAR struct ez80emac_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void ez80emac_poll_work(FAR void *arg); +#endif +static void ez80emac_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ static int ez80emac_ifup(struct net_driver_s *dev); static int ez80emac_ifdown(struct net_driver_s *dev); + +static inline void ez80emac_txavail_process(FAR struct ez80emac_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void ez80emac_txavail_work(FAR void *arg); +#endif static int ez80emac_txavail(struct net_driver_s *dev); + #ifdef CONFIG_NET_IGMP static int ez80emac_addmac(struct net_driver_s *dev, FAR const uint8_t *mac); static int ez80emac_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac); @@ -1051,7 +1111,8 @@ static int ez80emac_transmit(struct ez80emac_driver_s *priv) /* Setup the TX timeout watchdog (perhaps restarting the timer) */ - (void)wd_start(priv->txtimeout, EMAC_TXTIMEOUT, ez80emac_txtimeout, 1, (uint32_t)priv); + (void)wd_start(priv->txtimeout, EMAC_TXTIMEOUT, + ez80emac_txtimeout_expiry, 1, (uint32_t)priv); return OK; } @@ -1414,23 +1475,25 @@ static int ez80emac_receive(struct ez80emac_driver_s *priv) } /**************************************************************************** - * Function: ez80emac_txinterrupt + * Function: ez80emac_txinterrupt_process * * Description: - * Process Rx-related interrupt events + * Tx Interrupt processing. This may be performed either within the + * interrupt handler or on the worker thread, depending upon the configuration * * Parameters: - * priv - Driver data instance - * istat - Snapshot of ISTAT register containing Rx events to provess + * priv - Reference to the driver state structure * * Returned Value: - * None + * None + * + * Assumptions: + * The network is locked. * ****************************************************************************/ -static int ez80emac_txinterrupt(int irq, FAR void *context) +static inline void ez80emac_txinterrupt_process(FAR struct ez80emac_driver_s *priv) { - FAR struct ez80emac_driver_s *priv = &g_emac; FAR struct ez80emac_desc_s *txhead = priv->txhead; uint8_t regval; uint8_t istat; @@ -1514,28 +1577,117 @@ static int ez80emac_txinterrupt(int irq, FAR void *context) wd_cancel(priv->txtimeout); } +} + +/**************************************************************************** + * Function: ez80emac_txinterrupt_work + * + * Description: + * Perform Tx interrupt related work from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() was called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void ez80emac_txinterrupt_work(FAR void *arg) +{ + FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)arg; + net_lock_t state; + + /* Process pending Ethernet interrupts */ + + state = net_lock(); + ez80emac_txinterrupt_process(priv); + net_unlock(state); + + /* Re-enable Ethernet Tx interrupts */ + + up_enable_irq(EZ80_EMACRX_IRQ); +} +#endif + +/**************************************************************************** + * Function: ez80emac_txinterrupt + * + * Description: + * Process Tx-related interrupt events + * + * Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * OK on success + * + * Assumptions: + * + ****************************************************************************/ + +static int ez80emac_txinterrupt(int irq, FAR void *context) +{ + FAR struct ez80emac_driver_s *priv = &g_emac; + +#ifdef CONFIG_NET_NOINTS + /* Disable further Ethernet Tx interrupts. Because Ethernet interrupts are + * also disabled if the TX timeout event occurs, there can be no race + * condition here. + */ + + up_disable_irq(EZ80_EMACTX_IRQ); + + /* TODO: Determine if a TX transfer just completed */ + + { + /* If a TX transfer just completed, then cancel the TX timeout so + * there will be no race condition between any subsequent timeout + * expiration and the deferred interrupt processing. + */ + + wd_cancel(priv->txtimeout); + } + + /* Schedule to perform the Tx interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->txwork, ez80emac_txinterrupt_work, priv, 0); + +#else + /* Process the interrupt now */ + + ez80emac_txinterrupt_process(priv); +#endif return OK; } /**************************************************************************** - * Function: ez80emac_rxinterrupt + * Function: ez80emac_rxinterrupt_process * * Description: - * Process Rx-related interrupt events + * Rx Interrupt processing. This may be performed either within the + * interrupt handler or on the worker thread, depending upon the + * configuration * * Parameters: - * priv - Driver data instance - * istat - Snapshot of ISTAT register containing Rx events to provess + * priv - Reference to the driver state structure * * Returned Value: * None * + * Assumptions: + * The network is locked. + * ****************************************************************************/ -static int ez80emac_rxinterrupt(int irq, FAR void *context) +static inline void ez80emac_rxinterrupt_process(FAR struct ez80emac_driver_s *priv) { - FAR struct ez80emac_driver_s *priv = &g_emac; uint8_t istat; /* EMAC Rx interrupts: @@ -1558,14 +1710,48 @@ static int ez80emac_rxinterrupt(int irq, FAR void *context) /* Process any RX packets pending the RX buffer */ (void)ez80emac_receive(priv); - return OK; } /**************************************************************************** - * Function: ez80emac_sysinterrupt + * Function: ez80emac_rxinterrupt_work * * Description: - * Hardware interrupt handler + * Perform Rx interrupt related work from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() was called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void ez80emac_rxinterrupt_work(FAR void *arg) +{ + FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)arg; + net_lock_t state; + + /* Process pending Ethernet interrupts */ + + state = net_lock(); + ez80emac_rxinterrupt_process(priv); + net_unlock(state); + + /* Re-enable Ethernet Rx interrupts */ + + up_enable_irq(EZ80_EMACRX_IRQ); +} +#endif + +/**************************************************************************** + * Function: ez80emac_rxinterrupt + * + * Description: + * Process Rx-related interrupt events * * Parameters: * irq - Number of the IRQ that generated the interrupt @@ -1578,9 +1764,63 @@ static int ez80emac_rxinterrupt(int irq, FAR void *context) * ****************************************************************************/ -static int ez80emac_sysinterrupt(int irq, FAR void *context) +static int ez80emac_rxinterrupt(int irq, FAR void *context) { FAR struct ez80emac_driver_s *priv = &g_emac; + +#ifdef CONFIG_NET_NOINTS + /* Disable further Ethernet Rx interrupts. Because Ethernet interrupts are + * also disabled if the TX timeout event occurs, there can be no race + * condition here. + */ + + up_disable_irq(EZ80_EMACRX_IRQ); + + /* TODO: Determine if a TX transfer just completed */ + + { + /* If a TX transfer just completed, then cancel the TX timeout so + * there will be no race condition between any subsequent timeout + * expiration and the deferred interrupt processing. + */ + + wd_cancel(priv->txtimeout); + } + + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->rxwork, ez80emac_rxinterrupt_work, priv, 0); + +#else + /* Process the interrupt now */ + + ez80emac_rxinterrupt_process(priv); +#endif + + return OK; +} + +/**************************************************************************** + * Function: ez80emac_sysinterrupt_process + * + * Description: + * System interrupt processing. This may be performed either within the + * interrupt handler or on the worker thread, depending upon the + * configuration + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +static inline void ez80emac_sysinterrupt_process(FAR struct ez80emac_driver_s *priv) +{ uint8_t events; uint8_t istat; @@ -1636,30 +1876,119 @@ static int ez80emac_sysinterrupt(int irq, FAR void *context) EMAC_STAT(priv, rx_errors); EMAC_STAT(priv, rx_ovrerrors); } - return OK; } /**************************************************************************** - * Function: ez80emac_txtimeout + * Function: ez80emac_sysinterrupt_work * * Description: - * Our TX watchdog timed out. Called from the timer interrupt handler. - * The last TX never completed. Reset the hardware and start again. + * Perform system interrupt related work from the worker thread * * Parameters: - * argc - The number of available arguments - * arg - The first argument + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: + * The network is locked. * ****************************************************************************/ -static void ez80emac_txtimeout(int argc, uint32_t arg, ...) +#ifdef CONFIG_NET_NOINTS +static void ez80emac_sysinterrupt_work(FAR void *arg) { FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)arg; + net_lock_t state; + + /* Process pending Ethernet interrupts */ + + state = net_lock(); + ez80emac_sysinterrupt_process(priv); + net_unlock(state); + + /* Re-enable Ethernet system interrupts */ + + up_enable_irq(EZ80_EMACSYS_IRQ); +} +#endif + +/**************************************************************************** + * Function: ez80emac_sysinterrupt + * + * Description: + * System interrupt handler + * + * Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * OK on success + * + * Assumptions: + * + ****************************************************************************/ + +static int ez80emac_sysinterrupt(int irq, FAR void *context) +{ + FAR struct ez80emac_driver_s *priv = &g_emac; + +#ifdef CONFIG_NET_NOINTS + /* Disable further Ethernet interrupts. Because Ethernet interrupts are + * also disabled if the TX timeout event occurs, there can be no race + * condition here. + */ + + up_disable_irq(EZ80_EMACSYS_IRQ); + + /* TODO: Determine if a TX transfer just completed */ + + { + /* If a TX transfer just completed, then cancel the TX timeout so + * there will be no race condition between any subsequent timeout + * expiration and the deferred interrupt processing. + */ + + wd_cancel(priv->txtimeout); + } + + /* Cancel any pending poll work */ + + work_cancel(HPWORK, &priv->syswork); + + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->syswork, ez80emac_sysinterrupt_work, priv, 0); + +#else + /* Process the interrupt now */ + + ez80emac_sysinterrupt_process(priv); +#endif + + return OK; +} + +/**************************************************************************** + * Function: ez80emac_txtimeout_process + * + * Description: + * Process a TX timeout. Called from the either the watchdog timer + * expiration logic or from the worker thread, depending upon the + * configuration. The timeout means that the last TX never completed. + * Reset the hardware and start again. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void ez80emac_txtimeout_process(FAR struct ez80emac_driver_s *priv) +{ irqstate_t flags; /* Increment statistics and dump debug info */ @@ -1680,10 +2009,42 @@ static void ez80emac_txtimeout(int argc, uint32_t arg, ...) } /**************************************************************************** - * Function: ez80emac_polltimer + * Function: ez80emac_txtimeout_work * * Description: - * Periodic timer handler. Called from the timer interrupt handler. + * Perform TX timeout related work from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void ez80emac_txtimeout_work(FAR void *arg) +{ + FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)arg; + net_lock_t state; + + /* Process pending Ethernet interrupts */ + + state = net_lock(); + ez80emac_txtimeout_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: ez80emac_txtimeout_expiry + * + * Description: + * Our TX watchdog timed out. Called from the timer interrupt handler. + * The last TX never completed. Reset the hardware and start again. * * Parameters: * argc - The number of available arguments @@ -1693,20 +2054,144 @@ static void ez80emac_txtimeout(int argc, uint32_t arg, ...) * None * * Assumptions: + * Global interrupts are disabled by the watchdog logic. * ****************************************************************************/ -static void ez80emac_polltimer(int argc, uint32_t arg, ...) +static void ez80emac_txtimeout_expiry(int argc, wdparm_t arg, ...) { - struct ez80emac_driver_s *priv = (struct ez80emac_driver_s *)arg; + FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)arg; +#ifdef CONFIG_NET_NOINTS + /* Disable further Ethernet Tx interrupts. This will prevent some race + * conditions with interrupt work. There is still a potential race + * condition with interrupt work that is already queued and in progress. + */ + + up_disable_irq(EZ80_EMACTX_IRQ); + + /* Cancel any pending poll or Tx interrupt work. This will have no + * effect on work that has already been started. + */ + + work_cancel(ETHWORK, &priv->txwork); + + /* Schedule to perform the TX timeout processing on the worker thread. */ + + work_queue(ETHWORK, &priv->txwork, ez80emac_txtimeout_work, priv, 0); +#else + /* Process the timeout now */ + + ez80emac_txtimeout_process(priv); +#endif +} + +/**************************************************************************** + * Function: ez80emac_poll_process + * + * Description: + * Perform the periodic poll. This may be called either from watchdog + * timer logic or from the worker thread, depending upon the configuration. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static inline void ez80emac_poll_process(FAR struct ez80emac_driver_s *priv) +{ /* Poll the network for new XMIT data */ (void)devif_timer(&priv->dev, ez80emac_txpoll); /* Setup the watchdog poll timer again */ - (void)wd_start(priv->txpoll, EMAC_WDDELAY, ez80emac_polltimer, 1, arg); + (void)wd_start(priv->txpoll, EMAC_WDDELAY, ez80emac_poll_expiry, 1, priv); +} + +/**************************************************************************** + * Function: ez80emac_poll_work + * + * Description: + * Perform periodic polling from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void ez80emac_poll_work(FAR void *arg) +{ + FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)arg; + net_lock_t state; + + /* Perform the poll */ + + state = net_lock(); + ez80emac_poll_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: ez80emac_poll_expiry + * + * Description: + * Periodic timer handler. Called from the timer interrupt handler. + * + * Parameters: + * argc - The number of available arguments + * arg - The first argument + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * + ****************************************************************************/ + +static void ez80emac_poll_expiry(int argc, wdparm_t arg, ...) +{ + FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)arg; + +#ifdef CONFIG_NET_NOINTS + /* Is our single work structure available? It may not be if there are + * pending interrupt actions. + */ + + if (work_available(&priv->syswork)) + { + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->syswork, ez80emac_poll_work, priv, 0); + } + else + { + /* No.. Just re-start the watchdog poll timer, missing one polling + * cycle. + */ + + (void)wd_start(priv->txpoll, EMAC_WDDELAY, ez80emac_poll_expiry, 1, arg); + } + +#else + /* Process the interrupt now */ + + ez80emac_poll_process(priv); +#endif } /**************************************************************************** @@ -1792,7 +2277,8 @@ static int ez80emac_ifup(FAR struct net_driver_s *dev) /* Set and activate a timer process */ - (void)wd_start(priv->txpoll, EMAC_WDDELAY, ez80emac_polltimer, 1, (uint32_t)priv); + (void)wd_start(priv->txpoll, EMAC_WDDELAY, ez80emac_poll_expiry, + 1, (uint32_t)priv); /* Enable the Ethernet interrupts */ @@ -1855,15 +2341,13 @@ static int ez80emac_ifdown(struct net_driver_s *dev) } /**************************************************************************** - * Function: ez80emac_txavail + * Function: ez80emac_txavail_process * * Description: - * Driver callback invoked when new TX data is available. This is a - * stimulus perform an out-of-cycle poll and, thereby, reduce the TX - * latency. + * Perform an out-of-cycle poll. * * Parameters: - * dev - Reference to the NuttX driver state structure + * dev - Reference to the NuttX driver state structure * * Returned Value: * None @@ -1873,26 +2357,102 @@ static int ez80emac_ifdown(struct net_driver_s *dev) * ****************************************************************************/ -static int ez80emac_txavail(struct net_driver_s *dev) +static inline void ez80emac_txavail_process(FAR struct ez80emac_driver_s *priv) { - struct ez80emac_driver_s *priv = (struct ez80emac_driver_s *)dev->d_private; - irqstate_t flags; - - flags = enter_critical_section(); - /* Ignore the notification if the interface is not yet up */ if (priv->bifup) { - /* Check if there is room in the hardware to hold another outgoing packet. */ /* If so, then poll the network for new XMIT data */ (void)devif_poll(&priv->dev, ez80emac_txpoll); } +} + +/**************************************************************************** + * Function: ez80emac_txavail_work + * + * Description: + * Perform an out-of-cycle poll on the worker thread. + * + * Parameters: + * arg - Reference to the NuttX driver state structure (cast to void*) + * + * Returned Value: + * None + * + * Assumptions: + * Called on the higher priority worker thread. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void ez80emac_txavail_work(FAR void *arg) +{ + FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)arg; + net_lock_t state; + + /* Perform the poll */ + + state = net_lock(); + ez80emac_txavail_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: ez80emac_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static int ez80emac_txavail(FAR struct net_driver_s *dev) +{ + FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)dev->d_private; + +#ifdef CONFIG_NET_NOINTS + /* Is our single work structure available? It may not be if there are + * pending interrupt actions and we will have to ignore the Tx + * availability action. + */ + + if (work_available(&priv->syswork)) + { + /* Schedule to serialize the poll on the worker thread. */ + + work_queue(ETHWORK, &priv->syswork, ez80emac_txavail_work, priv, 0); + } + +#else + irqstate_t flags; + + /* Disable interrupts because this function may be called from interrupt + * level processing. + */ + + flags = enter_critical_section(); + /* Perform the out-of-cycle poll now */ + + ez80emac_txavail_process(priv); leave_critical_section(flags); +#endif + return OK; } diff --git a/arch/z80/src/ez80/ez80_irqsave.asm b/arch/z80/src/ez80/ez80_irqsave.asm index de3ad4a6e2..25edb630df 100644 --- a/arch/z80/src/ez80/ez80_irqsave.asm +++ b/arch/z80/src/ez80/ez80_irqsave.asm @@ -1,5 +1,5 @@ ;************************************************************************** -; arch/z80/src/ez80/ez80_up_irq_save.asm +; arch/z80/src/ez80/ez80_irqsave.asm ; ; Copyright (C) 2008 Gregory Nutt. All rights reserved. ; Author: Gregory Nutt diff --git a/configs/ez80f910200zco/dhcpd/defconfig b/configs/ez80f910200zco/dhcpd/defconfig index 5439089c19..126bf74026 100644 --- a/configs/ez80f910200zco/dhcpd/defconfig +++ b/configs/ez80f910200zco/dhcpd/defconfig @@ -148,6 +148,7 @@ CONFIG_EZ80_NRXPKTBUFS=64 CONFIG_EZ80_MDCDIV=0 CONFIG_EZ80_TXPOLLTIMERMS=10 # CONFIG_ARCH_MCFILTER is not set +CONFIG_EZ80_EMAC_HPWORK=y CONFIG_ARCH_TIMERHOOK=y # @@ -289,6 +290,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -296,13 +298,17 @@ CONFIG_NAME_MAX=32 CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -393,7 +399,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set @@ -495,7 +500,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/ez80f910200zco/httpd/defconfig b/configs/ez80f910200zco/httpd/defconfig index 9e38b8322f..4177c0bc9b 100644 --- a/configs/ez80f910200zco/httpd/defconfig +++ b/configs/ez80f910200zco/httpd/defconfig @@ -148,6 +148,7 @@ CONFIG_EZ80_NRXPKTBUFS=64 CONFIG_EZ80_MDCDIV=0 CONFIG_EZ80_TXPOLLTIMERMS=10 # CONFIG_ARCH_MCFILTER is not set +CONFIG_EZ80_EMAC_HPWORK=y CONFIG_ARCH_TIMERHOOK=y # @@ -295,6 +296,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -303,13 +305,17 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -402,7 +408,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set @@ -504,7 +509,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/ez80f910200zco/nettest/defconfig b/configs/ez80f910200zco/nettest/defconfig index 1123421f92..99250b29d5 100644 --- a/configs/ez80f910200zco/nettest/defconfig +++ b/configs/ez80f910200zco/nettest/defconfig @@ -148,6 +148,7 @@ CONFIG_EZ80_NRXPKTBUFS=64 CONFIG_EZ80_MDCDIV=0 CONFIG_EZ80_TXPOLLTIMERMS=10 # CONFIG_ARCH_MCFILTER is not set +CONFIG_EZ80_EMAC_HPWORK=y CONFIG_ARCH_TIMERHOOK=y # @@ -289,6 +290,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -296,13 +298,17 @@ CONFIG_NAME_MAX=32 CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -394,7 +400,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set @@ -496,7 +501,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/ez80f910200zco/nsh/defconfig b/configs/ez80f910200zco/nsh/defconfig index 6eacbefa3e..04dda2443e 100644 --- a/configs/ez80f910200zco/nsh/defconfig +++ b/configs/ez80f910200zco/nsh/defconfig @@ -148,6 +148,7 @@ CONFIG_EZ80_NRXPKTBUFS=64 CONFIG_EZ80_MDCDIV=0 CONFIG_EZ80_TXPOLLTIMERMS=10 # CONFIG_ARCH_MCFILTER is not set +CONFIG_EZ80_EMAC_HPWORK=y CONFIG_ARCH_TIMERHOOK=y # @@ -295,6 +296,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -303,13 +305,17 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -404,7 +410,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set @@ -507,7 +512,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/ez80f910200zco/poll/defconfig b/configs/ez80f910200zco/poll/defconfig index e7919f583d..770d89d9bb 100644 --- a/configs/ez80f910200zco/poll/defconfig +++ b/configs/ez80f910200zco/poll/defconfig @@ -148,6 +148,7 @@ CONFIG_EZ80_NRXPKTBUFS=64 CONFIG_EZ80_MDCDIV=0 CONFIG_EZ80_TXPOLLTIMERMS=10 # CONFIG_ARCH_MCFILTER is not set +CONFIG_EZ80_EMAC_HPWORK=y CONFIG_ARCH_TIMERHOOK=y # @@ -295,6 +296,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -303,13 +305,17 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -401,7 +407,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set @@ -506,7 +511,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/include/debug.h b/include/debug.h index c2fc93dd53..0bde25605b 100644 --- a/include/debug.h +++ b/include/debug.h @@ -810,7 +810,7 @@ #ifdef CONFIG_DEBUG_CRYPTO_INFO # define cryptinfo _info #else -# define cryptinfo(x...) +# define cryptinfo (void) #endif #ifdef CONFIG_DEBUG_INPUT_ERROR -- GitLab From 43459fe75e9157b8b7bc9f9a7adf75a2ca20fc7b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 3 Dec 2016 11:42:15 -0600 Subject: [PATCH 579/734] DM09x0 Ethernet now supports CONFIG_NET_NOINTS --- TODO | 2 +- arch/arm/src/tiva/lm3s_ethernet.c | 2 +- arch/misoc/src/common/misoc_net.c | 2 + arch/z80/src/ez80/ez80_emac.c | 7 +- configs/ntosd-dm320/nettest/defconfig | 13 +- configs/ntosd-dm320/nsh/defconfig | 13 +- configs/ntosd-dm320/poll/defconfig | 13 +- configs/ntosd-dm320/thttpd/defconfig | 13 +- configs/ntosd-dm320/udp/defconfig | 13 +- configs/ntosd-dm320/webserver/defconfig | 13 +- drivers/net/Kconfig | 20 + drivers/net/dm90x0.c | 716 ++++++++++++++++++------ drivers/net/skeleton.c | 2 +- 13 files changed, 628 insertions(+), 201 deletions(-) diff --git a/TODO b/TODO index 36347d1036..b943d40b4a 100644 --- a/TODO +++ b/TODO @@ -1063,7 +1063,7 @@ o Network (net/, drivers/net) Kinetis YES YES (not tested) LPC17xx YES YES (not tested) LPC43xx YES YES (not tested) - DMxxx NIC NO NO + DMxxx NIC YES NO PIC32 YES NO SAM3/4 YES YES SAMA5D ----------------------- ------ diff --git a/arch/arm/src/tiva/lm3s_ethernet.c b/arch/arm/src/tiva/lm3s_ethernet.c index 4586747c20..306276f17e 100644 --- a/arch/arm/src/tiva/lm3s_ethernet.c +++ b/arch/arm/src/tiva/lm3s_ethernet.c @@ -1140,7 +1140,7 @@ static int tiva_interrupt(int irq, void *context) /* Cancel any pending poll work */ - work_cancel(HPWORK, &priv->ld_work); + work_cancel(ETHWORK, &priv->ld_work); /* Schedule to perform the interrupt processing on the worker thread. */ diff --git a/arch/misoc/src/common/misoc_net.c b/arch/misoc/src/common/misoc_net.c index 1174598318..e23689f869 100644 --- a/arch/misoc/src/common/misoc_net.c +++ b/arch/misoc/src/common/misoc_net.c @@ -81,6 +81,8 @@ */ #if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_HPWORK) +/* REVISIT: The low priority work queue would be preferred if it is avaiable */ + # error High priority work queue support is required #endif diff --git a/arch/z80/src/ez80/ez80_emac.c b/arch/z80/src/ez80/ez80_emac.c index f5655fdc49..1a4e2129d7 100644 --- a/arch/z80/src/ez80/ez80_emac.c +++ b/arch/z80/src/ez80/ez80_emac.c @@ -1634,6 +1634,7 @@ static void ez80emac_txinterrupt_work(FAR void *arg) static int ez80emac_txinterrupt(int irq, FAR void *context) { FAR struct ez80emac_driver_s *priv = &g_emac; + uint8_t istat; #ifdef CONFIG_NET_NOINTS /* Disable further Ethernet Tx interrupts. Because Ethernet interrupts are @@ -1643,8 +1644,10 @@ static int ez80emac_txinterrupt(int irq, FAR void *context) up_disable_irq(EZ80_EMACTX_IRQ); - /* TODO: Determine if a TX transfer just completed */ + /* Determine if a TX transfer just completed */ + istat = inp(EZ80_EMAC_ISTAT); + if ((istat & EMAC_ISTAT_TXDONE) != 0) { /* If a TX transfer just completed, then cancel the TX timeout so * there will be no race condition between any subsequent timeout @@ -1955,7 +1958,7 @@ static int ez80emac_sysinterrupt(int irq, FAR void *context) /* Cancel any pending poll work */ - work_cancel(HPWORK, &priv->syswork); + work_cancel(ETHWORK, &priv->syswork); /* Schedule to perform the interrupt processing on the worker thread. */ diff --git a/configs/ntosd-dm320/nettest/defconfig b/configs/ntosd-dm320/nettest/defconfig index 27c48a7988..b1f9e6730d 100644 --- a/configs/ntosd-dm320/nettest/defconfig +++ b/configs/ntosd-dm320/nettest/defconfig @@ -289,6 +289,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -296,13 +297,17 @@ CONFIG_NAME_MAX=32 CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -404,9 +409,9 @@ CONFIG_DM9X_MODE_AUTO=y # CONFIG_DM9X_MODE_10MFD is not set # CONFIG_DM9X_MODE_100MHD is not set # CONFIG_DM9X_MODE_100MFD is not set +CONFIG_DM9X_HPWORK=y # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set # CONFIG_PIPES is not set @@ -504,7 +509,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/ntosd-dm320/nsh/defconfig b/configs/ntosd-dm320/nsh/defconfig index f20494e37e..9c16b857f5 100644 --- a/configs/ntosd-dm320/nsh/defconfig +++ b/configs/ntosd-dm320/nsh/defconfig @@ -295,6 +295,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -303,13 +304,17 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -420,9 +425,9 @@ CONFIG_DM9X_MODE_AUTO=y # CONFIG_DM9X_MODE_10MFD is not set # CONFIG_DM9X_MODE_100MHD is not set # CONFIG_DM9X_MODE_100MFD is not set +CONFIG_DM9X_HPWORK=y # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set # CONFIG_PIPES is not set @@ -520,7 +525,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/ntosd-dm320/poll/defconfig b/configs/ntosd-dm320/poll/defconfig index 47cf047ad0..5eac34cfe9 100644 --- a/configs/ntosd-dm320/poll/defconfig +++ b/configs/ntosd-dm320/poll/defconfig @@ -295,6 +295,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -303,13 +304,17 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -411,9 +416,9 @@ CONFIG_DM9X_MODE_AUTO=y # CONFIG_DM9X_MODE_10MFD is not set # CONFIG_DM9X_MODE_100MHD is not set # CONFIG_DM9X_MODE_100MFD is not set +CONFIG_DM9X_HPWORK=y # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set CONFIG_PIPES=y @@ -515,7 +520,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/ntosd-dm320/thttpd/defconfig b/configs/ntosd-dm320/thttpd/defconfig index 4961cfbd08..d6a53fa998 100644 --- a/configs/ntosd-dm320/thttpd/defconfig +++ b/configs/ntosd-dm320/thttpd/defconfig @@ -289,6 +289,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -296,13 +297,17 @@ CONFIG_NAME_MAX=32 CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -404,9 +409,9 @@ CONFIG_DM9X_MODE_AUTO=y # CONFIG_DM9X_MODE_10MFD is not set # CONFIG_DM9X_MODE_100MHD is not set # CONFIG_DM9X_MODE_100MFD is not set +CONFIG_DM9X_HPWORK=y # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set CONFIG_PIPES=y @@ -508,7 +513,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/ntosd-dm320/udp/defconfig b/configs/ntosd-dm320/udp/defconfig index 25043071da..01d6266cf2 100644 --- a/configs/ntosd-dm320/udp/defconfig +++ b/configs/ntosd-dm320/udp/defconfig @@ -289,6 +289,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -296,13 +297,17 @@ CONFIG_NAME_MAX=32 CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -403,9 +408,9 @@ CONFIG_DM9X_MODE_AUTO=y # CONFIG_DM9X_MODE_10MFD is not set # CONFIG_DM9X_MODE_100MHD is not set # CONFIG_DM9X_MODE_100MFD is not set +CONFIG_DM9X_HPWORK=y # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set # CONFIG_PIPES is not set @@ -503,7 +508,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/ntosd-dm320/webserver/defconfig b/configs/ntosd-dm320/webserver/defconfig index 71ec171e9e..d20b40829f 100644 --- a/configs/ntosd-dm320/webserver/defconfig +++ b/configs/ntosd-dm320/webserver/defconfig @@ -295,6 +295,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -303,13 +304,17 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -411,9 +416,9 @@ CONFIG_DM9X_MODE_AUTO=y # CONFIG_DM9X_MODE_10MFD is not set # CONFIG_DM9X_MODE_100MHD is not set # CONFIG_DM9X_MODE_100MFD is not set +CONFIG_DM9X_HPWORK=y # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set # CONFIG_PIPES is not set @@ -511,7 +516,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 2d62454562..96d012a04d 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -195,6 +195,26 @@ config DM9X_NINTERFACES default 1 depends on EXPERIMENTAL +choice + prompt "Work queue" + default DM9X_LPWORK if SCHED_LPWORK + default DM9X_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + depends on SCHED_WORKQUEUE + ---help--- + Work queue support is required to use the Ethernet driver. If the + low priority work queue is available, then it should be used by the + driver. + +config DM9X_HPWORK + bool "High priority" + depends on SCHED_HPWORK + +config DM9X_LPWORK + bool "Low priority" + depends on SCHED_LPWORK + +endchoice # Work queue + endif # NET_DM90x0 config NET_CS89x0 diff --git a/drivers/net/dm90x0.c b/drivers/net/dm90x0.c index c99cf1846c..6439d7494a 100644 --- a/drivers/net/dm90x0.c +++ b/drivers/net/dm90x0.c @@ -1,5 +1,5 @@ /**************************************************************************** - * drivers/net/dm9x.c + * drivers/net/dm90x0.c * * Copyright (C) 2007-2010, 2014-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -65,6 +65,11 @@ #include #include #include + +#ifdef CONFIG_NET_NOINTS +# include +#endif + #include #include @@ -75,6 +80,25 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +/* If processing is not done at the interrupt level, then work queue support + * is required. + */ + +#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required in this configuration (CONFIG_SCHED_WORKQUEUE) +#endif + +/* Use the low priority work queue if possible */ + +#if defined(CONFIG_SCHED_WORKQUEUE) +# if defined(CONFIG_DM9X_HPWORK) +# define ETHWORK HPWORK +# elif defined(CONFIG_DM9X_LPWORK) +# define ETHWORK LPWORK +# else +# error Neither CONFIG_DM9X_HPWORK nor CONFIG_DM9X_LPWORK defined +# endif +#endif /* DM90000 and DM9010 register offets */ @@ -265,7 +289,7 @@ /* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */ -#define DM6X_WDDELAY (1*CLK_TCK) +#define DM9X_WDDELAY (1*CLK_TCK) /* TX timeout = 1 minute */ @@ -273,7 +297,7 @@ /* This is a helper pointer for accessing the contents of the Ethernet header */ -#define BUF ((struct eth_hdr_s *)dm9x->dm_dev.d_buf) +#define BUF ((struct eth_hdr_s *)priv->dm_dev.d_buf) /**************************************************************************** * Private Types @@ -298,10 +322,13 @@ struct dm9x_driver_s { bool dm_bifup; /* true:ifup false:ifdown */ bool dm_b100M; /* true:speed == 100M; false:speed == 10M */ - WDOG_ID dm_txpoll; /* TX poll timer */ - WDOG_ID dm_txtimeout; /* TX timeout timer */ uint8_t dm_ntxpending; /* Count of packets pending transmission */ uint8_t ncrxpackets; /* Number of continuous rx packets */ + WDOG_ID dm_txpoll; /* TX poll timer */ + WDOG_ID dm_txtimeout; /* TX timeout timer */ +#ifdef CONFIG_NET_NOINTS + struct work_s dm_work; /* For deferring work to the work queue */ +#endif /* Mode-dependent function to move data in 8/16/32 I/O modes */ @@ -344,9 +371,9 @@ static void write8(const uint8_t *ptr, int len); static void write16(const uint8_t *ptr, int len); static void write32(const uint8_t *ptr, int len); -/* static uint16_t dm9x_readsrom(struct dm9x_driver_s *dm9x, int offset); */ -static uint16_t dm9x_phyread(struct dm9x_driver_s *dm9x, int reg); -static void dm9x_phywrite(struct dm9x_driver_s *dm9x, int reg, uint16_t value); +/* static uint16_t dm9x_readsrom(struct dm9x_driver_s *priv, int offset); */ +static uint16_t dm9x_phyread(struct dm9x_driver_s *priv, int reg); +static void dm9x_phywrite(struct dm9x_driver_s *priv, int reg, uint16_t value); #if defined(CONFIG_DM9X_CHECKSUM) static bool dm9x_rxchecksumready(uint8_t); @@ -356,25 +383,45 @@ static bool dm9x_rxchecksumready(uint8_t); /* Common TX logic */ -static int dm9x_transmit(struct dm9x_driver_s *dm9x); +static int dm9x_transmit(struct dm9x_driver_s *priv); static int dm9x_txpoll(struct net_driver_s *dev); /* Interrupt handling */ -static void dm9x_receive(struct dm9x_driver_s *dm9x); -static void dm9x_txdone(struct dm9x_driver_s *dm9x); +static void dm9x_receive(struct dm9x_driver_s *priv); +static void dm9x_txdone(struct dm9x_driver_s *priv); + +static inline void dm9x_interrupt_process(FAR struct dm9x_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void dm9x_interrupt_work(FAR void *arg); +#endif static int dm9x_interrupt(int irq, FAR void *context); /* Watchdog timer expirations */ -static void dm9x_polltimer(int argc, uint32_t arg, ...); -static void dm9x_txtimeout(int argc, uint32_t arg, ...); +static inline void dm9x_txtimeout_process(FAR struct dm9x_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void dm9x_txtimeout_work(FAR void *arg); +#endif +static void dm9x_txtimeout_expiry(int argc, uint32_t arg, ...); + +static inline void dm9x_poll_process(FAR struct dm9x_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void dm9x_poll_work(FAR void *arg); +#endif +static void dm9x_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ static int dm9x_ifup(struct net_driver_s *dev); static int dm9x_ifdown(struct net_driver_s *dev); + +static inline void dm9x_txavail_process(FAR struct dm9x_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void dm9x_txavail_work(FAR void *arg); +#endif static int dm9x_txavail(struct net_driver_s *dev); + #ifdef CONFIG_NET_IGMP static int dm9x_addmac(struct net_driver_s *dev, FAR const uint8_t *mac); static int dm9x_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac); @@ -382,8 +429,8 @@ static int dm9x_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac); /* Initialization functions */ -static void dm9x_bringup(struct dm9x_driver_s *dm9x); -static void dm9x_reset(struct dm9x_driver_s *dm9x); +static void dm9x_bringup(struct dm9x_driver_s *priv); +static void dm9x_reset(struct dm9x_driver_s *priv); /**************************************************************************** * Private Functions @@ -568,7 +615,7 @@ static void write32(FAR const uint8_t *ptr, int len) * Read a word from SROM * * Parameters: - * dm9x - Reference to the driver state structure + * priv - Reference to the driver state structure * offset - SROM offset to read from * * Returned Value: @@ -579,7 +626,7 @@ static void write32(FAR const uint8_t *ptr, int len) ****************************************************************************/ #if 0 /* Not used */ -static uint16_t dm9x_readsrom(struct dm9x_driver_s *dm9x, int offset) +static uint16_t dm9x_readsrom(struct dm9x_driver_s *priv, int offset) { putreg(DM9X_EEPHYA, offset); putreg(DM9X_EEPHYC, DM9X_EEPHYC_ERPRR); @@ -596,7 +643,7 @@ static uint16_t dm9x_readsrom(struct dm9x_driver_s *dm9x, int offset) * Read/write data from/to the PHY * * Parameters: - * dm9x - Reference to the driver state structure + * priv - Reference to the driver state structure * reg - PHY register offset * value - The value to write to the PHY register (dm9x_write only) * @@ -607,7 +654,7 @@ static uint16_t dm9x_readsrom(struct dm9x_driver_s *dm9x, int offset) * ****************************************************************************/ -static uint16_t dm9x_phyread(struct dm9x_driver_s *dm9x, int reg) +static uint16_t dm9x_phyread(struct dm9x_driver_s *priv, int reg) { /* Setup DM9X_EEPHYA, the EEPROM/PHY address register */ @@ -624,7 +671,7 @@ static uint16_t dm9x_phyread(struct dm9x_driver_s *dm9x, int reg) return (((uint16_t)getreg(DM9X_EEPHYDH)) << 8) | (uint16_t)getreg(DM9X_EEPHYDL); } -static void dm9x_phywrite(struct dm9x_driver_s *dm9x, int reg, uint16_t value) +static void dm9x_phywrite(struct dm9x_driver_s *priv, int reg, uint16_t value) { /* Setup DM9X_EEPHYA, the EEPROM/PHY address register */ @@ -678,7 +725,7 @@ static inline bool dm9x_rxchecksumready(uint8_t rxbyte) * handling or from watchdog based polling. * * Parameters: - * dm9x - Reference to the driver state structure + * priv - Reference to the driver state structure * * Returned Value: * OK on success; a negated errno on failure @@ -687,17 +734,17 @@ static inline bool dm9x_rxchecksumready(uint8_t rxbyte) * ****************************************************************************/ -static int dm9x_transmit(struct dm9x_driver_s *dm9x) +static int dm9x_transmit(struct dm9x_driver_s *priv) { /* Check if there is room in the DM90x0 to hold another packet. In 100M mode, * that can be 2 packets, otherwise it is a single packet. */ - if (dm9x->dm_ntxpending < 1 || (dm9x->dm_b100M && dm9x->dm_ntxpending < 2)) + if (priv->dm_ntxpending < 1 || (priv->dm_b100M && priv->dm_ntxpending < 2)) { /* Increment count of packets transmitted */ - dm9x->dm_ntxpending++; + priv->dm_ntxpending++; NETDEV_TXPACKETS(&dm9x0->dm_dev); /* Disable all DM90x0 interrupts */ @@ -706,13 +753,13 @@ static int dm9x_transmit(struct dm9x_driver_s *dm9x) /* Set the TX length */ - putreg(DM9X_TXPLL, (dm9x->dm_dev.d_len & 0xff)); - putreg(DM9X_TXPLH, (dm9x->dm_dev.d_len >> 8) & 0xff); + putreg(DM9X_TXPLL, (priv->dm_dev.d_len & 0xff)); + putreg(DM9X_TXPLH, (priv->dm_dev.d_len >> 8) & 0xff); /* Move the data to be sent into TX SRAM */ DM9X_INDEX = DM9X_MWCMD; - dm9x->dm_write(dm9x->dm_dev.d_buf, dm9x->dm_dev.d_len); + priv->dm_write(priv->dm_dev.d_buf, priv->dm_dev.d_len); #if !defined(CONFIG_DM9X_ETRANS) /* Issue TX polling command */ @@ -722,7 +769,7 @@ static int dm9x_transmit(struct dm9x_driver_s *dm9x) /* Clear count of back-to-back RX packet transfers */ - dm9x->ncrxpackets = 0; + priv->ncrxpackets = 0; /* Re-enable DM90x0 interrupts */ @@ -730,8 +777,8 @@ static int dm9x_transmit(struct dm9x_driver_s *dm9x) /* Setup the TX timeout watchdog (perhaps restarting the timer) */ - (void)wd_start(dm9x->dm_txtimeout, DM6X_TXTIMEOUT, dm9x_txtimeout, 1, - (wdparm_t)dm9x); + (void)wd_start(priv->dm_txtimeout, DM6X_TXTIMEOUT, dm9x_txtimeout_expiry, 1, + (wdparm_t)priv); return OK; } return -EBUSY; @@ -760,13 +807,13 @@ static int dm9x_transmit(struct dm9x_driver_s *dm9x) static int dm9x_txpoll(struct net_driver_s *dev) { - struct dm9x_driver_s *dm9x = (struct dm9x_driver_s *)dev->d_private; + struct dm9x_driver_s *priv = (struct dm9x_driver_s *)dev->d_private; /* If the polling resulted in data that should be sent out on the network, * the field d_len is set to a value > 0. */ - if (dm9x->dm_dev.d_len > 0) + if (priv->dm_dev.d_len > 0) { /* Look up the destination MAC address and add it to the Ethernet * header. @@ -774,10 +821,10 @@ static int dm9x_txpoll(struct net_driver_s *dev) #ifdef CONFIG_NET_IPv4 #ifdef CONFIG_NET_IPv6 - if (IFF_IS_IPv4(dm9x->dm_dev.d_flags)) + if (IFF_IS_IPv4(priv->dm_dev.d_flags)) #endif { - arp_out(&dm9x->dm_dev); + arp_out(&priv->dm_dev); } #endif /* CONFIG_NET_IPv4 */ @@ -786,19 +833,19 @@ static int dm9x_txpoll(struct net_driver_s *dev) else #endif { - neighbor_out(&dm9x->dm_dev); + neighbor_out(&priv->dm_dev); } #endif /* CONFIG_NET_IPv6 */ /* Send the packet */ - dm9x_transmit(dm9x); + dm9x_transmit(priv); /* Check if there is room in the DM90x0 to hold another packet. In 100M mode, * that can be 2 packets, otherwise it is a single packet. */ - if (dm9x->dm_ntxpending > 1 || !dm9x->dm_b100M) + if (priv->dm_ntxpending > 1 || !priv->dm_b100M) { /* Returning a non-zero value will terminate the poll operation */ @@ -820,7 +867,7 @@ static int dm9x_txpoll(struct net_driver_s *dev) * An interrupt was received indicating the availability of a new RX packet * * Parameters: - * dm9x - Reference to the driver state structure + * priv - Reference to the driver state structure * * Returned Value: * None @@ -829,7 +876,7 @@ static int dm9x_txpoll(struct net_driver_s *dev) * ****************************************************************************/ -static void dm9x_receive(FAR struct dm9x_driver_s *dm9x) +static void dm9x_receive(FAR struct dm9x_driver_s *priv) { union rx_desc_u rx; bool bchecksumready; @@ -861,7 +908,7 @@ static void dm9x_receive(FAR struct dm9x_driver_s *dm9x) /* Read packet status & length */ - dm9x->dm_read((FAR uint8_t *)&rx, 4); + priv->dm_read((FAR uint8_t *)&rx, 4); /* Check if any errors were reported by the hardware */ @@ -870,11 +917,11 @@ static void dm9x_receive(FAR struct dm9x_driver_s *dm9x) /* Bad RX packet... update statistics */ nerr("ERROR: Received packet with errors: %02x\n", rx.desc.rx_status); - NETDEV_RXERRORS(&dm9x->dm_dev); + NETDEV_RXERRORS(&priv->dm_dev); /* Drop this packet and continue to check the next packet */ - dm9x->dm_discard(rx.desc.rx_len); + priv->dm_discard(rx.desc.rx_len); } /* Also check if the packet is a valid size for the network configuration */ @@ -882,23 +929,23 @@ static void dm9x_receive(FAR struct dm9x_driver_s *dm9x) else if (rx.desc.rx_len < ETH_HDRLEN || rx.desc.rx_len > (CONFIG_NET_ETH_MTU + 2)) { nerr("ERROR: RX length error\n"); - NETDEV_RXERRORS(&dm9x->dm_dev); + NETDEV_RXERRORS(&priv->dm_dev); /* Drop this packet and continue to check the next packet */ - dm9x->dm_discard(rx.desc.rx_len); + priv->dm_discard(rx.desc.rx_len); } else { /* Good packet... Copy the packet data out of SRAM and pass it one to the network */ - dm9x->dm_dev.d_len = rx.desc.rx_len; - dm9x->dm_read(dm9x->dm_dev.d_buf, rx.desc.rx_len); + priv->dm_dev.d_len = rx.desc.rx_len; + priv->dm_read(priv->dm_dev.d_buf, rx.desc.rx_len); #ifdef CONFIG_NET_PKT /* When packet sockets are enabled, feed the frame into the packet tap */ - pkt_input(&dm9x->dm_dev); + pkt_input(&priv->dm_dev); #endif /* We only accept IP packets of the configured type and ARP packets */ @@ -913,33 +960,33 @@ static void dm9x_receive(FAR struct dm9x_driver_s *dm9x) * layer */ - arp_ipin(&dm9x->dm_dev); - ipv4_input(&dm9x->dm_dev); + arp_ipin(&priv->dm_dev); + ipv4_input(&priv->dm_dev); /* If the above function invocation resulted in data that should be * sent out on the network, the field d_len will set to a value > 0. */ - if (dm9x->dm_dev.d_len > 0) + if (priv->dm_dev.d_len > 0) { /* Update the Ethernet header with the correct MAC address */ #ifdef CONFIG_NET_IPv6 - if (IFF_IS_IPv4(dm9x->dm_dev.d_flags)) + if (IFF_IS_IPv4(priv->dm_dev.d_flags)) #endif { - arp_out(&dm9x->dm_dev); + arp_out(&priv->dm_dev); } #ifdef CONFIG_NET_IPv6 else { - neighbor_out(&dm9x->dm_dev); + neighbor_out(&priv->dm_dev); } #endif /* And send the packet */ - dm9x_transmit(dm9x); + dm9x_transmit(priv); } } else @@ -952,32 +999,32 @@ static void dm9x_receive(FAR struct dm9x_driver_s *dm9x) /* Give the IPv6 packet to the network layer */ - ipv6_input(&dm9x->dm_dev); + ipv6_input(&priv->dm_dev); /* If the above function invocation resulted in data that should be * sent out on the network, the field d_len will set to a value > 0. */ - if (dm9x->dm_dev.d_len > 0) + if (priv->dm_dev.d_len > 0) { /* Update the Ethernet header with the correct MAC address */ #ifdef CONFIG_NET_IPv4 - if (IFF_IS_IPv4(dm9x->dm_dev.d_flags)) + if (IFF_IS_IPv4(priv->dm_dev.d_flags)) { - arp_out(&dm9x->dm_dev); + arp_out(&priv->dm_dev); } else #endif #ifdef CONFIG_NET_IPv6 { - neighbor_out(&dm9x->dm_dev); + neighbor_out(&priv->dm_dev); } #endif /* And send the packet */ - dm9x_transmit(dm9x); + dm9x_transmit(priv); } } else @@ -985,16 +1032,16 @@ static void dm9x_receive(FAR struct dm9x_driver_s *dm9x) #ifdef CONFIG_NET_ARP if (BUF->type == htons(ETHTYPE_ARP)) { - arp_arpin(&dm9x->dm_dev); + arp_arpin(&priv->dm_dev); NETDEV_RXARP(&priv->dm_dev); /* If the above function invocation resulted in data that should be * sent out on the network, the field d_len will set to a value > 0. */ - if (dm9x->dm_dev.d_len > 0) + if (priv->dm_dev.d_len > 0) { - dm9x_transmit(dm9x); + dm9x_transmit(priv); } } #endif @@ -1004,10 +1051,10 @@ static void dm9x_receive(FAR struct dm9x_driver_s *dm9x) } } - NETDEV_RXPACKETS(&dm9x->dm_dev); - dm9x->ncrxpackets++; + NETDEV_RXPACKETS(&priv->dm_dev); + priv->ncrxpackets++; } - while ((rxbyte & 0x01) == DM9X_PKTRDY && dm9x->ncrxpackets < DM9X_CRXTHRES); + while ((rxbyte & 0x01) == DM9X_PKTRDY && priv->ncrxpackets < DM9X_CRXTHRES); ninfo("All RX packets processed\n"); } @@ -1018,7 +1065,7 @@ static void dm9x_receive(FAR struct dm9x_driver_s *dm9x) * An interrupt was received indicating that the last TX packet(s) is done * * Parameters: - * dm9x - Reference to the driver state structure + * priv - Reference to the driver state structure * * Returned Value: * None @@ -1027,7 +1074,7 @@ static void dm9x_receive(FAR struct dm9x_driver_s *dm9x) * ****************************************************************************/ -static void dm9x_txdone(struct dm9x_driver_s *dm9x) +static void dm9x_txdone(struct dm9x_driver_s *priv) { int nsr; @@ -1040,9 +1087,9 @@ static void dm9x_txdone(struct dm9x_driver_s *dm9x) nsr = getreg(DM9X_NETS); if (nsr & DM9X_NETS_TX1END) { - if (dm9x->dm_ntxpending) + if (priv->dm_ntxpending) { - dm9x->dm_ntxpending--; + priv->dm_ntxpending--; } else { @@ -1052,9 +1099,9 @@ static void dm9x_txdone(struct dm9x_driver_s *dm9x) if (nsr & DM9X_NETS_TX2END) { - if (dm9x->dm_ntxpending) + if (priv->dm_ntxpending) { - dm9x->dm_ntxpending--; + priv->dm_ntxpending--; } else { @@ -1064,40 +1111,36 @@ static void dm9x_txdone(struct dm9x_driver_s *dm9x) /* Cancel the TX timeout */ - if (dm9x->dm_ntxpending == 0) + if (priv->dm_ntxpending == 0) { - wd_cancel(dm9x->dm_txtimeout); + wd_cancel(priv->dm_txtimeout); } /* Then poll the network for new XMIT data */ - (void)devif_poll(&dm9x->dm_dev, dm9x_txpoll); + (void)devif_poll(&priv->dm_dev, dm9x_txpoll); } /**************************************************************************** - * Function: dm9x_interrupt + * Function: dm9x_interrupt_process * * Description: - * DM90x0 interrupt handler + * Interrupt processing. This may be performed either within the interrupt + * handler or on the worker thread, depending upon the configuration * * Parameters: - * irq - Number of the IRQ that generated the interrupt - * context - Interrupt register state save info (architecture-specific) + * priv - Reference to the driver state structure * * Returned Value: - * OK on success + * None * * Assumptions: + * The network is locked. * ****************************************************************************/ -static int dm9x_interrupt(int irq, FAR void *context) +static inline void dm9x_interrupt_process(FAR struct dm9x_driver_s *priv) { -#if CONFIG_DM9X_NINTERFACES == 1 - register struct dm9x_driver_s *dm9x = &g_dm9x[0]; -#else -# error "Additional logic needed to support multiple interfaces" -#endif uint8_t isr; uint8_t save; int i; @@ -1124,8 +1167,8 @@ static int dm9x_interrupt(int irq, FAR void *context) for (i = 0; i < 500; i++) { - dm9x_phyread(dm9x, 0x1); - if (dm9x_phyread(dm9x, 0x1) & 0x4) /* Link OK */ + dm9x_phyread(priv, 0x1); + if (dm9x_phyread(priv, 0x1) & 0x4) /* Link OK */ { /* Wait to get detected speed */ @@ -1136,41 +1179,41 @@ static int dm9x_interrupt(int irq, FAR void *context) /* Set the new network speed */ - if (dm9x_phyread(dm9x, 0) & 0x2000) + if (dm9x_phyread(priv, 0) & 0x2000) { - dm9x->dm_b100M = true; + priv->dm_b100M = true; } else { - dm9x->dm_b100M = false; + priv->dm_b100M = false; } break; } up_mdelay(1); } - nerr("ERROR: delay: %dmS speed: %s\n", i, dm9x->dm_b100M ? "100M" : "10M"); + nerr("ERROR: delay: %dmS speed: %s\n", i, priv->dm_b100M ? "100M" : "10M"); } /* Check if we received an incoming packet */ if (isr & DM9X_INT_PR) { - dm9x_receive(dm9x); + dm9x_receive(priv); } /* Check if we are able to transmit a packet */ if (isr & DM9X_INT_PT) { - dm9x_txdone(dm9x); + dm9x_txdone(priv); } /* If the number of consecutive receive packets exceeds a threshold, * then disable the RX interrupt. */ - if (dm9x->ncrxpackets >= DM9X_CRXTHRES) + if (priv->ncrxpackets >= DM9X_CRXTHRES) { /* Eanble all DM90x0 interrupts EXCEPT for RX */ @@ -1186,38 +1229,134 @@ static int dm9x_interrupt(int irq, FAR void *context) /* Restore previous register address */ DM9X_INDEX = save; - return OK; } /**************************************************************************** - * Function: dm9x_txtimeout + * Function: dm9x_interrupt_work * * Description: - * Our TX watchdog timed out. Called from the timer interrupt handler. - * The last TX never completed. Reset the DM90x0 and start again. + * Perform interrupt related work from the worker thread * * Parameters: - * argc - The number of available arguments - * arg - The first argument + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void dm9x_interrupt_work(FAR void *arg) +{ + FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)arg; + net_lock_t state; + + /* Process pending Ethernet interrupts */ + + state = net_lock(); + dm9x_interrupt_process(priv); + net_unlock(state); + + /* Re-enable Ethernet interrupts */ + + up_enable_irq(CONFIG_DM9X_IRQ); +} +#endif + +/**************************************************************************** + * Function: dm9x_interrupt + * + * Description: + * Hardware interrupt handler + * + * Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * OK on success * * Assumptions: * ****************************************************************************/ -static void dm9x_txtimeout(int argc, uint32_t arg, ...) +static int dm9x_interrupt(int irq, FAR void *context) { - struct dm9x_driver_s *dm9x = (struct dm9x_driver_s *)arg; +#if CONFIG_DM9X_NINTERFACES == 1 + FAR struct dm9x_driver_s *priv = &g_dm9x[0]; +#else +# error "Additional logic needed to support multiple interfaces" +#endif +#ifdef CONFIG_NET_NOINTS + uint8_t isr; + + /* Disable further Ethernet interrupts. Because Ethernet interrupts are + * also disabled if the TX timeout event occurs, there can be no race + * condition here. + */ + + up_disable_irq(CONFIG_DM9X_IRQ); + + /* Determine if a TX transfer just completed */ + + isr = getreg(DM9X_ISR); + if ((isr & DM9X_INT_PT) != 0) + { + /* If a TX transfer just completed, then cancel the TX timeout so + * there will be no race condition between any subsequent timeout + * expiration and the deferred interrupt processing. + */ + + wd_cancel(priv->dm_txtimeout); + } + + /* Cancel any pending poll work */ + + work_cancel(ETHWORK, &priv->dm_work); + + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->dm_work, dm9x_interrupt_work, priv, 0); + +#else + /* Process the interrupt now */ + + dm9x_interrupt_process(priv); +#endif + + return OK; +} + +/**************************************************************************** + * Function: dm9x_txtimeout_process + * + * Description: + * Process a TX timeout. Called from the either the watchdog timer + * expiration logic or from the worker thread, depending upon the + * configuration. The timeout means that the last TX never completed. + * Reset the hardware and start again. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void dm9x_txtimeout_process(FAR struct dm9x_driver_s *priv) +{ nerr("ERROR: TX timeout\n"); /* Increment statistics and dump debug info */ - NETDEV_TXTIMEOUTS(dm9x->dm_dev); + NETDEV_TXTIMEOUTS(priv->dm_dev); - ninfo(" TX packet count: %d\n", dm9x->dm_ntxpending); + ninfo(" TX packet count: %d\n", priv->dm_ntxpending); ninfo(" TX read pointer address: 0x%02x:%02x\n", getreg(DM9X_TRPAH), getreg(DM9X_TRPAL)); ninfo(" Memory data write address: 0x%02x:%02x (DM9010)\n", @@ -1225,18 +1364,50 @@ static void dm9x_txtimeout(int argc, uint32_t arg, ...) /* Then reset the DM90x0 */ - dm9x_reset(dm9x); + dm9x_reset(priv); /* Then poll the network for new XMIT data */ - (void)devif_poll(&dm9x->dm_dev, dm9x_txpoll); + (void)devif_poll(&priv->dm_dev, dm9x_txpoll); } /**************************************************************************** - * Function: dm9x_polltimer + * Function: dm9x_txtimeout_work * * Description: - * Periodic timer handler. Called from the timer interrupt handler. + * Perform TX timeout related work from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void dm9x_txtimeout_work(FAR void *arg) +{ + FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)arg; + net_lock_t state; + + /* Process pending Ethernet interrupts */ + + state = net_lock(); + dm9x_txtimeout_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: dm9x_txtimeout_expiry + * + * Description: + * Our TX watchdog timed out. Called from the timer interrupt handler. + * The last TX never completed. Reset the hardware and start again. * * Parameters: * argc - The number of available arguments @@ -1246,20 +1417,64 @@ static void dm9x_txtimeout(int argc, uint32_t arg, ...) * None * * Assumptions: + * Global interrupts are disabled by the watchdog logic. * ****************************************************************************/ -static void dm9x_polltimer(int argc, uint32_t arg, ...) +static void dm9x_txtimeout_expiry(int argc, wdparm_t arg, ...) { - struct dm9x_driver_s *dm9x = (struct dm9x_driver_s *)arg; + FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)arg; + +#ifdef CONFIG_NET_NOINTS + /* Disable further Ethernet interrupts. This will prevent some race + * conditions with interrupt work. There is still a potential race + * condition with interrupt work that is already queued and in progress. + */ + up_disable_irq(CONFIG_DM9X_IRQ); + + /* Cancel any pending poll or interrupt work. This will have no effect + * on work that has already been started. + */ + + work_cancel(ETHWORK, &priv->dm_work); + + /* Schedule to perform the TX timeout processing on the worker thread. */ + + work_queue(ETHWORK, &priv->dm_work, dm9x_txtimeout_work, priv, 0); +#else + /* Process the timeout now */ + + dm9x_txtimeout_process(priv); +#endif +} + +/**************************************************************************** + * Function: dm9x_poll_process + * + * Description: + * Perform the periodic poll. This may be called either from watchdog + * timer logic or from the worker thread, depending upon the configuration. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static inline void dm9x_poll_process(FAR struct dm9x_driver_s *priv) +{ /* If the number of contiguous RX packets exceeds a threshold, reset the counter and * re-enable RX interrupts */ - if (dm9x->ncrxpackets >= DM9X_CRXTHRES) + if (priv->ncrxpackets >= DM9X_CRXTHRES) { - dm9x->ncrxpackets = 0; + priv->ncrxpackets = 0; putreg(DM9X_IMR, DM9X_IMRENABLE); } @@ -1267,17 +1482,97 @@ static void dm9x_polltimer(int argc, uint32_t arg, ...) * that can be 2 packets, otherwise it is a single packet. */ - if (dm9x->dm_ntxpending < 1 || (dm9x->dm_b100M && dm9x->dm_ntxpending < 2)) + if (priv->dm_ntxpending < 1 || (priv->dm_b100M && priv->dm_ntxpending < 2)) { /* If so, update TCP timing states and poll the network for new XMIT data */ - (void)devif_timer(&dm9x->dm_dev, dm9x_txpoll); + (void)devif_timer(&priv->dm_dev, dm9x_txpoll); } /* Setup the watchdog poll timer again */ - (void)wd_start(dm9x->dm_txpoll, DM6X_WDDELAY, dm9x_polltimer, 1, - (wdparm_t)arg); + (void)wd_start(priv->dm_txpoll, DM9X_WDDELAY, dm9x_poll_expiry, 1, + (wdparm_t)priv); +} + +/**************************************************************************** + * Function: dm9x_poll_work + * + * Description: + * Perform periodic polling from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void dm9x_poll_work(FAR void *arg) +{ + FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)arg; + net_lock_t state; + + /* Perform the poll */ + + state = net_lock(); + dm9x_poll_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: dm9x_poll_expiry + * + * Description: + * Periodic timer handler. Called from the timer interrupt handler. + * + * Parameters: + * argc - The number of available arguments + * arg - The first argument + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * + ****************************************************************************/ + +static void dm9x_poll_expiry(int argc, wdparm_t arg, ...) +{ + FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)arg; + +#ifdef CONFIG_NET_NOINTS + /* Is our single work structure available? It may not be if there are + * pending interrupt actions. + */ + + if (work_available(&priv->dm_work)) + { + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->dm_work, dm9x_poll_work, priv, 0); + } + else + { + /* No.. Just re-start the watchdog poll timer, missing one polling + * cycle. + */ + + (void)wd_start(priv->dm_txpoll, DM9X_WDDELAY, dm9x_poll_expiry, 1, arg); + } + +#else + /* Process the interrupt now */ + + dm9x_poll_process(priv); +#endif } /**************************************************************************** @@ -1287,7 +1582,7 @@ static void dm9x_polltimer(int argc, uint32_t arg, ...) * Configure the PHY operating mode * * Parameters: - * dm9x - Reference to the driver state structure + * priv - Reference to the driver state structure * * Returned Value: * None @@ -1296,7 +1591,7 @@ static void dm9x_polltimer(int argc, uint32_t arg, ...) * ****************************************************************************/ -static inline void dm9x_phymode(struct dm9x_driver_s *dm9x) +static inline void dm9x_phymode(struct dm9x_driver_s *priv) { uint16_t phyreg0; uint16_t phyreg4; @@ -1320,8 +1615,8 @@ static inline void dm9x_phymode(struct dm9x_driver_s *dm9x) # error "Recognized PHY mode" #endif - dm9x_phywrite(dm9x, 0, phyreg0); - dm9x_phywrite(dm9x, 4, phyreg4); + dm9x_phywrite(priv, 0, phyreg0); + dm9x_phywrite(priv, 4, phyreg4); } /**************************************************************************** @@ -1343,7 +1638,7 @@ static inline void dm9x_phymode(struct dm9x_driver_s *dm9x) static int dm9x_ifup(struct net_driver_s *dev) { - struct dm9x_driver_s *dm9x = (struct dm9x_driver_s *)dev->d_private; + struct dm9x_driver_s *priv = (struct dm9x_driver_s *)dev->d_private; uint8_t netstatus; int i; @@ -1353,11 +1648,11 @@ static int dm9x_ifup(struct net_driver_s *dev) /* Initilize DM90x0 chip */ - dm9x_bringup(dm9x); + dm9x_bringup(priv); /* Check link state and media speed (waiting up to 3s for link OK) */ - dm9x->dm_b100M = false; + priv->dm_b100M = false; for (i = 0; i < 3000; i++) { netstatus = getreg(DM9X_NETS); @@ -1369,7 +1664,7 @@ static int dm9x_ifup(struct net_driver_s *dev) netstatus = getreg(DM9X_NETS); if ((netstatus & DM9X_NETS_SPEED) == 0) { - dm9x->dm_b100M = true; + priv->dm_b100M = true; } break; } @@ -1377,16 +1672,16 @@ static int dm9x_ifup(struct net_driver_s *dev) up_mdelay(1); } - ninfo("delay: %dmS speed: %s\n", i, dm9x->dm_b100M ? "100M" : "10M"); + ninfo("delay: %dmS speed: %s\n", i, priv->dm_b100M ? "100M" : "10M"); /* Set and activate a timer process */ - (void)wd_start(dm9x->dm_txpoll, DM6X_WDDELAY, dm9x_polltimer, 1, - (wdparm_t)dm9x); + (void)wd_start(priv->dm_txpoll, DM9X_WDDELAY, dm9x_poll_expiry, 1, + (wdparm_t)priv); /* Enable the DM9X interrupt */ - dm9x->dm_bifup = true; + priv->dm_bifup = true; up_enable_irq(CONFIG_DM9X_IRQ); return OK; } @@ -1409,7 +1704,7 @@ static int dm9x_ifup(struct net_driver_s *dev) static int dm9x_ifdown(struct net_driver_s *dev) { - struct dm9x_driver_s *dm9x = (struct dm9x_driver_s *)dev->d_private; + struct dm9x_driver_s *priv = (struct dm9x_driver_s *)dev->d_private; irqstate_t flags; ninfo("Stopping\n"); @@ -1421,32 +1716,30 @@ static int dm9x_ifdown(struct net_driver_s *dev) /* Cancel the TX poll timer and TX timeout timers */ - wd_cancel(dm9x->dm_txpoll); - wd_cancel(dm9x->dm_txtimeout); + wd_cancel(priv->dm_txpoll); + wd_cancel(priv->dm_txtimeout); /* Reset the device */ - dm9x_phywrite(dm9x, 0x00, 0x8000); /* PHY reset */ + dm9x_phywrite(priv, 0x00, 0x8000); /* PHY reset */ putreg(DM9X_GPD, 0x01); /* Power-down PHY (GEPIO0=1) */ putreg(DM9X_IMR, DM9X_IMRDISABLE); /* Disable all interrupts */ putreg(DM9X_RXC, 0x00); /* Disable RX */ putreg(DM9X_ISR, DM9X_INT_ALL); /* Clear interrupt status */ - dm9x->dm_bifup = false; + priv->dm_bifup = false; leave_critical_section(flags); return OK; } /**************************************************************************** - * Function: dm9x_txavail + * Function: dm9x_txavail_process * * Description: - * Driver callback invoked when new TX data is available. This is a - * stimulus perform an out-of-cycle poll and, thereby, reduce the TX - * latency. + * Perform an out-of-cycle poll. * * Parameters: - * dev - Reference to the NuttX driver state structure + * dev - Reference to the NuttX driver state structure * * Returned Value: * None @@ -1456,31 +1749,110 @@ static int dm9x_ifdown(struct net_driver_s *dev) * ****************************************************************************/ -static int dm9x_txavail(struct net_driver_s *dev) +static inline void dm9x_txavail_process(FAR struct dm9x_driver_s *priv) { - struct dm9x_driver_s *dm9x = (struct dm9x_driver_s *)dev->d_private; - irqstate_t flags; - ninfo("Polling\n"); - flags = enter_critical_section(); /* Ignore the notification if the interface is not yet up */ - if (dm9x->dm_bifup) + if (priv->dm_bifup) { /* Check if there is room in the DM90x0 to hold another packet. In 100M * mode, that can be 2 packets, otherwise it is a single packet. */ - if (dm9x->dm_ntxpending < 1 || (dm9x->dm_b100M && dm9x->dm_ntxpending < 2)) + if (priv->dm_ntxpending < 1 || (priv->dm_b100M && priv->dm_ntxpending < 2)) { /* If so, then poll the network for new XMIT data */ - (void)devif_poll(&dm9x->dm_dev, dm9x_txpoll); + (void)devif_poll(&priv->dm_dev, dm9x_txpoll); } } +} + +/**************************************************************************** + * Function: dm9x_txavail_work + * + * Description: + * Perform an out-of-cycle poll on the worker thread. + * + * Parameters: + * arg - Reference to the NuttX driver state structure (cast to void*) + * + * Returned Value: + * None + * + * Assumptions: + * Called on the higher priority worker thread. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void dm9x_txavail_work(FAR void *arg) +{ + FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)arg; + net_lock_t state; + + /* Perform the poll */ + + state = net_lock(); + dm9x_txavail_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: dm9x_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static int dm9x_txavail(FAR struct net_driver_s *dev) +{ + FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)dev->d_private; + +#ifdef CONFIG_NET_NOINTS + /* Is our single work structure available? It may not be if there are + * pending interrupt actions and we will have to ignore the Tx + * availability action. + */ + + if (work_available(&priv->dm_work)) + { + /* Schedule to serialize the poll on the worker thread. */ + + work_queue(ETHWORK, &priv->dm_work, dm9x_txavail_work, priv, 0); + } + +#else + irqstate_t flags; + + /* Disable interrupts because this function may be called from interrupt + * level processing. + */ + + flags = enter_critical_section(); + + /* Perform the out-of-cycle poll now */ + + dm9x_txavail_process(priv); leave_critical_section(flags); +#endif + return OK; } @@ -1551,7 +1923,7 @@ static int dm9x_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac) * Initialize the dm90x0 chip * * Parameters: - * dm9x - Reference to the driver state structure + * priv - Reference to the driver state structure * * Returned Value: * None @@ -1560,7 +1932,7 @@ static int dm9x_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac) * ****************************************************************************/ -static void dm9x_bringup(struct dm9x_driver_s *dm9x) +static void dm9x_bringup(struct dm9x_driver_s *priv) { ninfo("Initializing\n"); @@ -1585,21 +1957,21 @@ static void dm9x_bringup(struct dm9x_driver_s *dm9x) switch (getreg(DM9X_ISR) & DM9X_ISR_IOMODEM) { case DM9X_ISR_IOMODE8: - dm9x->dm_read = read8; - dm9x->dm_write = write8; - dm9x->dm_discard = discard8; + priv->dm_read = read8; + priv->dm_write = write8; + priv->dm_discard = discard8; break; case DM9X_ISR_IOMODE16: - dm9x->dm_read = read16; - dm9x->dm_write = write16; - dm9x->dm_discard = discard16; + priv->dm_read = read16; + priv->dm_write = write16; + priv->dm_discard = discard16; break; case DM9X_ISR_IOMODE32: - dm9x->dm_read = read32; - dm9x->dm_write = write32; - dm9x->dm_discard = discard32; + priv->dm_read = read32; + priv->dm_write = write32; + priv->dm_discard = discard32; break; default: @@ -1608,7 +1980,7 @@ static void dm9x_bringup(struct dm9x_driver_s *dm9x) /* Program PHY operating mode */ - dm9x_phymode(dm9x); + dm9x_phymode(priv); /* Program operating mode */ @@ -1630,9 +2002,9 @@ static void dm9x_bringup(struct dm9x_driver_s *dm9x) /* Initialize statistics */ - dm9x->ncrxpackets = 0; /* Number of continuous RX packets */ - dm9x->dm_ntxpending = 0; /* Number of pending TX packets */ - NETDEV_RESET_STATISTICS(&dm9x->dm_dev); + priv->ncrxpackets = 0; /* Number of continuous RX packets */ + priv->dm_ntxpending = 0; /* Number of pending TX packets */ + NETDEV_RESET_STATISTICS(&priv->dm_dev); /* Activate DM9000A/DM9010 */ @@ -1648,7 +2020,7 @@ static void dm9x_bringup(struct dm9x_driver_s *dm9x) * present, the chip is only reset after a TX timeout. * * Parameters: - * dm9x - Reference to the driver state structure + * priv - Reference to the driver state structure * * Returned Value: * None @@ -1657,31 +2029,31 @@ static void dm9x_bringup(struct dm9x_driver_s *dm9x) * ****************************************************************************/ -static void dm9x_reset(struct dm9x_driver_s *dm9x) +static void dm9x_reset(struct dm9x_driver_s *priv) { uint8_t save; int i; /* Cancel the TX poll timer and TX timeout timers */ - wd_cancel(dm9x->dm_txpoll); - wd_cancel(dm9x->dm_txtimeout); + wd_cancel(priv->dm_txpoll); + wd_cancel(priv->dm_txtimeout); /* Save previous register address */ save = (uint8_t)DM9X_INDEX; - dm9x_bringup(dm9x); + dm9x_bringup(priv); /* Wait up to 1 second for the link to be OK */ - dm9x->dm_b100M = false; + priv->dm_b100M = false; for (i = 0; i < 1000; i++) { - if (dm9x_phyread(dm9x, 0x1) & 0x4) + if (dm9x_phyread(priv, 0x1) & 0x4) { - if (dm9x_phyread(dm9x, 0) &0x2000) + if (dm9x_phyread(priv, 0) &0x2000) { - dm9x->dm_b100M = true; + priv->dm_b100M = true; } break; } diff --git a/drivers/net/skeleton.c b/drivers/net/skeleton.c index 1b9e1c7866..1cfb8277d6 100644 --- a/drivers/net/skeleton.c +++ b/drivers/net/skeleton.c @@ -622,7 +622,7 @@ static int skel_interrupt(int irq, FAR void *context) /* Cancel any pending poll work */ - work_cancel(HPWORK, &priv->sk_work); + work_cancel(ETHWORK, &priv->sk_work); /* Schedule to perform the interrupt processing on the worker thread. */ -- GitLab From ad3897531f12ec3676d38c2484318b56e2cc4a06 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 3 Dec 2016 12:17:55 -0600 Subject: [PATCH 580/734] C5471 Ethernet now supports CONFIG_NET_NOINTS --- arch/arm/src/c5471/Kconfig | 20 + arch/arm/src/c5471/c5471_ethernet.c | 755 +++++++++++++++++++++------- configs/c5471evm/httpd/defconfig | 12 +- configs/c5471evm/nettest/defconfig | 12 +- configs/c5471evm/nsh/defconfig | 12 +- drivers/net/skeleton.c | 1 + 6 files changed, 610 insertions(+), 202 deletions(-) diff --git a/arch/arm/src/c5471/Kconfig b/arch/arm/src/c5471/Kconfig index 17b615a097..5f46d7684a 100644 --- a/arch/arm/src/c5471/Kconfig +++ b/arch/arm/src/c5471/Kconfig @@ -110,3 +110,23 @@ config C5471_BASET10 bool "10BaseT FullDuplex" endchoice + +choice + prompt "Ethernet work queue" + default C5471_LPWORK if SCHED_LPWORK + default C5471_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + depends on SCHED_WORKQUEUE + ---help--- + Work queue support is required to use the Ethernet driver. If the + low priority work queue is available, then it should be used by the + driver. + +config C5471_HPWORK + bool "High priority" + depends on SCHED_HPWORK + +config C5471_LPWORK + bool "Low priority" + depends on SCHED_LPWORK + +endchoice # Work queue diff --git a/arch/arm/src/c5471/c5471_ethernet.c b/arch/arm/src/c5471/c5471_ethernet.c index 62fe06eb0f..b041574ea5 100644 --- a/arch/arm/src/c5471/c5471_ethernet.c +++ b/arch/arm/src/c5471/c5471_ethernet.c @@ -59,6 +59,11 @@ #include #include #include + +#ifdef CONFIG_NET_NOINTS +# include +#endif + #include #include @@ -75,6 +80,26 @@ ****************************************************************************/ /* Configuration ************************************************************/ +/* If processing is not done at the interrupt level, then work queue support + * is required. + */ + +#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required in this configuration (CONFIG_SCHED_WORKQUEUE) +#endif + +/* Use the low priority work queue if possible */ + +#if defined(CONFIG_SCHED_WORKQUEUE) +# if defined(CONFIG_C5471_HPWORK) +# define ETHWORK HPWORK +# elif defined(CONFIG_C5471_LPWORK) +# define ETHWORK LPWORK +# else +# error Neither CONFIG_C5471_HPWORK nor CONFIG_C5471_LPWORK defined +# endif +#endif + /* CONFIG_C5471_NET_NINTERFACES determines the number of physical interfaces * that will be supported. */ @@ -273,7 +298,7 @@ /* This is a helper pointer for accessing the contents of the Ethernet header */ -#define BUF ((struct eth_hdr_s *)c5471->c_dev.d_buf) +#define BUF ((struct eth_hdr_s *)priv->c_dev.d_buf) /**************************************************************************** * Private Types @@ -292,6 +317,9 @@ struct c5471_driver_s bool c_bifup; /* true:ifup false:ifdown */ WDOG_ID c_txpoll; /* TX poll timer */ WDOG_ID c_txtimeout; /* TX timeout timer */ +#ifdef CONFIG_NET_NOINTS + struct work_s c_work; /* For deferring work to the work queue */ +#endif /* Note: According to the C547x documentation: "The software has to maintain * two pointers to the current RX-CPU and TX-CPU descriptors. At init time, @@ -360,36 +388,57 @@ static int c5471_phyinit (void); /* Support logic */ -static inline void c5471_inctxcpu(struct c5471_driver_s *c5471); -static inline void c5471_incrxcpu(struct c5471_driver_s *c5471); +static inline void c5471_inctxcpu(struct c5471_driver_s *priv); +static inline void c5471_incrxcpu(struct c5471_driver_s *priv); /* Common TX logic */ -static int c5471_transmit(struct c5471_driver_s *c5471); +static int c5471_transmit(struct c5471_driver_s *priv); static int c5471_txpoll(struct net_driver_s *dev); /* Interrupt handling */ #ifdef CONFIG_C5471_NET_STATS -static void c5471_rxstatus(struct c5471_driver_s *c5471); +static void c5471_rxstatus(struct c5471_driver_s *priv); #endif -static void c5471_receive(struct c5471_driver_s *c5471); +static void c5471_receive(struct c5471_driver_s *priv); #ifdef CONFIG_C5471_NET_STATS -static void c5471_txstatus(struct c5471_driver_s *c5471); +static void c5471_txstatus(struct c5471_driver_s *priv); +#endif +static void c5471_txdone(struct c5471_driver_s *priv); + +static inline void c5471_interrupt_process(FAR struct c5471_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void c5471_interrupt_work(FAR void *arg); #endif -static void c5471_txdone(struct c5471_driver_s *c5471); + static int c5471_interrupt(int irq, FAR void *context); /* Watchdog timer expirations */ -static void c5471_polltimer(int argc, uint32_t arg, ...); -static void c5471_txtimeout(int argc, uint32_t arg, ...); +static inline void c5471_txtimeout_process(FAR struct c5471_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void c5471_txtimeout_work(FAR void *arg); +#endif +static void c5471_txtimeout_expiry(int argc, uint32_t arg, ...); + +static inline void c5471_poll_process(FAR struct c5471_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void c5471_poll_work(FAR void *arg); +#endif +static void c5471_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ static int c5471_ifup(struct net_driver_s *dev); static int c5471_ifdown(struct net_driver_s *dev); + +static inline void c5471_txavail_process(FAR struct c5471_driver_s *priv); +#ifdef CONFIG_NET_NOINTS +static void c5471_txavail_work(FAR void *arg); +#endif static int c5471_txavail(struct net_driver_s *dev); + #ifdef CONFIG_NET_IGMP static int c5471_addmac(struct net_driver_s *dev, FAR const uint8_t *mac); static int c5471_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac); @@ -397,10 +446,10 @@ static int c5471_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac); /* Initialization functions */ -static void c5471_eimreset (struct c5471_driver_s *c5471); -static void c5471_eimconfig(struct c5471_driver_s *c5471); -static void c5471_reset(struct c5471_driver_s *c5471); -static void c5471_macassign(struct c5471_driver_s *c5471); +static void c5471_eimreset (struct c5471_driver_s *priv); +static void c5471_eimconfig(struct c5471_driver_s *priv); +static void c5471_reset(struct c5471_driver_s *priv); +static void c5471_macassign(struct c5471_driver_s *priv); /**************************************************************************** * Private Functions @@ -415,7 +464,8 @@ static void c5471_macassign(struct c5471_driver_s *c5471); ****************************************************************************/ #ifdef CONFIG_C5471_NET_DUMPBUFFER -static inline void c5471_dumpbuffer(const char *msg, const uint8_t *buffer, unsigned int nbytes) +static inline void c5471_dumpbuffer(const char *msg, const uint8_t *buffer, + unsigned int nbytes) { /* CONFIG_DEBUG_FEATURES, CONFIG_DEBUG_INFO, and CONFIG_DEBUG_NET have to be * defined or the following does nothing. @@ -793,20 +843,20 @@ static int c5471_phyinit (void) * ****************************************************************************/ -static inline void c5471_inctxcpu(struct c5471_driver_s *c5471) +static inline void c5471_inctxcpu(struct c5471_driver_s *priv) { - if (EIM_TXDESC_WRAP_NEXT & getreg32(c5471->c_txcpudesc)) + if (EIM_TXDESC_WRAP_NEXT & getreg32(priv->c_txcpudesc)) { /* Loop back around to base of descriptor queue */ - c5471->c_txcpudesc = getreg32(EIM_CPU_TXBA) + EIM_RAM_START; + priv->c_txcpudesc = getreg32(EIM_CPU_TXBA) + EIM_RAM_START; } else { - c5471->c_txcpudesc += 2*sizeof(uint32_t); + priv->c_txcpudesc += 2*sizeof(uint32_t); } - ninfo("TX CPU desc: %08x\n", c5471->c_txcpudesc); + ninfo("TX CPU desc: %08x\n", priv->c_txcpudesc); } /**************************************************************************** @@ -816,20 +866,20 @@ static inline void c5471_inctxcpu(struct c5471_driver_s *c5471) * ****************************************************************************/ -static inline void c5471_incrxcpu(struct c5471_driver_s *c5471) +static inline void c5471_incrxcpu(struct c5471_driver_s *priv) { - if (EIM_RXDESC_WRAP_NEXT & getreg32(c5471->c_rxcpudesc)) + if (EIM_RXDESC_WRAP_NEXT & getreg32(priv->c_rxcpudesc)) { /* Loop back around to base of descriptor queue */ - c5471->c_rxcpudesc = getreg32(EIM_CPU_RXBA) + EIM_RAM_START; + priv->c_rxcpudesc = getreg32(EIM_CPU_RXBA) + EIM_RAM_START; } else { - c5471->c_rxcpudesc += 2*sizeof(uint32_t); + priv->c_rxcpudesc += 2*sizeof(uint32_t); } - ninfo("RX CPU desc: %08x\n", c5471->c_rxcpudesc); + ninfo("RX CPU desc: %08x\n", priv->c_rxcpudesc); } /**************************************************************************** @@ -840,7 +890,7 @@ static inline void c5471_incrxcpu(struct c5471_driver_s *c5471) * handling or from watchdog based polling. * * Parameters: - * c5471 - Reference to the driver state structure + * priv - Reference to the driver state structure * * Returned Value: * OK on success; a negated errno on failure @@ -849,9 +899,9 @@ static inline void c5471_incrxcpu(struct c5471_driver_s *c5471) * ****************************************************************************/ -static int c5471_transmit(struct c5471_driver_s *c5471) +static int c5471_transmit(struct c5471_driver_s *priv) { - struct net_driver_s *dev = &c5471->c_dev; + struct net_driver_s *dev = &priv->c_dev; volatile uint16_t *packetmem; uint16_t framelen; bool bfirstframe; @@ -860,12 +910,12 @@ static int c5471_transmit(struct c5471_driver_s *c5471) unsigned int i; unsigned int j; - nbytes = (dev->d_len + 1) & ~1; - j = 0; - bfirstframe = true; - c5471->c_lastdescstart = c5471->c_rxcpudesc; + nbytes = (dev->d_len + 1) & ~1; + j = 0; + bfirstframe = true; + priv->c_lastdescstart = priv->c_rxcpudesc; - ninfo("Packet size: %d RX CPU desc: %08x\n", nbytes, c5471->c_rxcpudesc); + ninfo("Packet size: %d RX CPU desc: %08x\n", nbytes, priv->c_rxcpudesc); c5471_dumpbuffer("Transmit packet", dev->d_buf, dev->d_len); while (nbytes) @@ -873,7 +923,7 @@ static int c5471_transmit(struct c5471_driver_s *c5471) /* Verify that the hardware is ready to send another packet */ /* Words #0 and #1 of descriptor */ - while (EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc)) + while (EIM_TXDESC_OWN_HOST & getreg32(priv->c_rxcpudesc)) { /* Loop until the SWITCH lets go of the descriptor giving us access * rights to submit our new ether frame to it. @@ -882,18 +932,18 @@ static int c5471_transmit(struct c5471_driver_s *c5471) if (bfirstframe) { - putreg32((getreg32(c5471->c_rxcpudesc) | EIM_RXDESC_FIF), c5471->c_rxcpudesc); + putreg32((getreg32(priv->c_rxcpudesc) | EIM_RXDESC_FIF), priv->c_rxcpudesc); } else { - putreg32((getreg32(c5471->c_rxcpudesc) & ~EIM_RXDESC_FIF), c5471->c_rxcpudesc); + putreg32((getreg32(priv->c_rxcpudesc) & ~EIM_RXDESC_FIF), priv->c_rxcpudesc); } - putreg32((getreg32(c5471->c_rxcpudesc) & ~EIM_RXDESC_PADCRC), c5471->c_rxcpudesc); + putreg32((getreg32(priv->c_rxcpudesc) & ~EIM_RXDESC_PADCRC), priv->c_rxcpudesc); if (bfirstframe) { - putreg32((getreg32(c5471->c_rxcpudesc) | EIM_RXDESC_PADCRC), c5471->c_rxcpudesc); + putreg32((getreg32(priv->c_rxcpudesc) | EIM_RXDESC_PADCRC), priv->c_rxcpudesc); } if (nbytes >= EIM_PACKET_BYTES) @@ -912,7 +962,7 @@ static int c5471_transmit(struct c5471_driver_s *c5471) /* Words #2 and #3 of descriptor */ - packetmem = (uint16_t *)getreg32(c5471->c_rxcpudesc + sizeof(uint32_t)); + packetmem = (uint16_t *)getreg32(priv->c_rxcpudesc + sizeof(uint32_t)); for (i = 0; i < nshorts; i++, j++) { /* 16-bits at a time. */ @@ -920,43 +970,45 @@ static int c5471_transmit(struct c5471_driver_s *c5471) packetmem[i] = htons(((uint16_t *)dev->d_buf)[j]); } - putreg32(((getreg32(c5471->c_rxcpudesc) & ~EIM_RXDESC_BYTEMASK) | framelen), c5471->c_rxcpudesc); + putreg32(((getreg32(priv->c_rxcpudesc) & ~EIM_RXDESC_BYTEMASK) | framelen), + priv->c_rxcpudesc); nbytes -= framelen; ninfo("Wrote framelen: %d nbytes: %d nshorts: %d\n", framelen, nbytes, nshorts); if (0 == nbytes) { - putreg32((getreg32(c5471->c_rxcpudesc) | EIM_RXDESC_LIF), c5471->c_rxcpudesc); + putreg32((getreg32(priv->c_rxcpudesc) | EIM_RXDESC_LIF), priv->c_rxcpudesc); } else { - putreg32((getreg32(c5471->c_rxcpudesc) & ~EIM_RXDESC_LIF), c5471->c_rxcpudesc); + putreg32((getreg32(priv->c_rxcpudesc) & ~EIM_RXDESC_LIF), priv->c_rxcpudesc); } /* We're done with that descriptor; give access rights back to h/w */ - putreg32((getreg32(c5471->c_rxcpudesc) | EIM_RXDESC_OWN_HOST), c5471->c_rxcpudesc); + putreg32((getreg32(priv->c_rxcpudesc) | EIM_RXDESC_OWN_HOST), priv->c_rxcpudesc); /* Next, tell Ether Module that those submitted bytes are ready for the wire */ putreg32(0x00000001, EIM_CPU_RXREADY); - c5471->c_lastdescend = c5471->c_rxcpudesc; + priv->c_lastdescend = priv->c_rxcpudesc; /* Advance to the next free descriptor */ - c5471_incrxcpu(c5471); + c5471_incrxcpu(priv); bfirstframe = false; } /* Packet transferred .. Update statistics */ #ifdef CONFIG_C5471_NET_STATS - c5471->c_txpackets++; + priv->c_txpackets++; #endif /* Setup the TX timeout watchdog (perhaps restarting the timer) */ - (void)wd_start(c5471->c_txtimeout, C5471_TXTIMEOUT, c5471_txtimeout, 1, (uint32_t)c5471); + (void)wd_start(priv->c_txtimeout, C5471_TXTIMEOUT, + c5471_txtimeout_expiry, 1, (wdparm_t)priv); return OK; } @@ -983,13 +1035,13 @@ static int c5471_transmit(struct c5471_driver_s *c5471) static int c5471_txpoll(struct net_driver_s *dev) { - struct c5471_driver_s *c5471 = (struct c5471_driver_s *)dev->d_private; + struct c5471_driver_s *priv = (struct c5471_driver_s *)dev->d_private; /* If the polling resulted in data that should be sent out on the network, * the field d_len is set to a value > 0. */ - if (c5471->c_dev.d_len > 0) + if (priv->c_dev.d_len > 0) { /* Look up the destination MAC address and add it to the Ethernet * header. @@ -997,10 +1049,10 @@ static int c5471_txpoll(struct net_driver_s *dev) #ifdef CONFIG_NET_IPv4 #ifdef CONFIG_NET_IPv6 - if (IFF_IS_IPv4(c5471->c_dev.d_flags)) + if (IFF_IS_IPv4(priv->c_dev.d_flags)) #endif { - arp_out(&c5471->c_dev); + arp_out(&priv->c_dev); } #endif /* CONFIG_NET_IPv4 */ @@ -1009,19 +1061,19 @@ static int c5471_txpoll(struct net_driver_s *dev) else #endif { - neighbor_out(&c5471->c_dev); + neighbor_out(&priv->c_dev); } #endif /* CONFIG_NET_IPv6 */ /* Send the packet */ - c5471_transmit(c5471); + c5471_transmit(priv); /* Check if the ESM has let go of the RX descriptor giving us access * rights to submit another Ethernet frame. */ - if ((EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc)) != 0) + if ((EIM_TXDESC_OWN_HOST & getreg32(priv->c_rxcpudesc)) != 0) { /* No, then return non-zero to terminate the poll */ @@ -1043,7 +1095,7 @@ static int c5471_txpoll(struct net_driver_s *dev) * An interrupt was received indicating that the last RX packet(s) is done * * Parameters: - * c5471 - Reference to the driver state structure + * priv - Reference to the driver state structure * * Returned Value: * None @@ -1053,9 +1105,9 @@ static int c5471_txpoll(struct net_driver_s *dev) ****************************************************************************/ #ifdef CONFIG_C5471_NET_STATS -static void c5471_rxstatus(struct c5471_driver_s *c5471) +static void c5471_rxstatus(struct c5471_driver_s *priv) { - uint32_t desc = c5471->c_txcpudesc; + uint32_t desc = priv->c_txcpudesc; uint32_t rxstatus; /* Walk that last packet we just received to collect xmit status bits. */ @@ -1095,44 +1147,44 @@ static void c5471_rxstatus(struct c5471_driver_s *c5471) { if ((rxstatus & EIM_TXDESC_RETRYERROR) != 0) { - c5471->c_rxretries++; - ninfo("c_rxretries: %d\n", c5471->c_rxretries); + priv->c_rxretries++; + ninfo("c_rxretries: %d\n", priv->c_rxretries); } if ((rxstatus & EIM_TXDESC_HEARTBEAT) != 0) { - c5471->c_rxheartbeat++; - ninfo("c_rxheartbeat: %d\n", c5471->c_rxheartbeat); + priv->c_rxheartbeat++; + ninfo("c_rxheartbeat: %d\n", priv->c_rxheartbeat); } if ((rxstatus & EIM_TXDESC_LCOLLISON) != 0) { - c5471->c_rxlcollision++; - ninfo("c_rxlcollision: %d\n", c5471->c_rxlcollision); + priv->c_rxlcollision++; + ninfo("c_rxlcollision: %d\n", priv->c_rxlcollision); } if ((rxstatus & EIM_TXDESC_COLLISION) != 0) { - c5471->c_rxcollision++; - ninfo("c_rxcollision: %d\n", c5471->c_rxcollision); + priv->c_rxcollision++; + ninfo("c_rxcollision: %d\n", priv->c_rxcollision); } if ((rxstatus & EIM_TXDESC_CRCERROR) != 0) { - c5471->c_rxcrc++; - ninfo("c_rxcrc: %d\n", c5471->c_rxcrc); + priv->c_rxcrc++; + ninfo("c_rxcrc: %d\n", priv->c_rxcrc); } if ((rxstatus & EIM_TXDESC_UNDERRUN) != 0) { - c5471->c_rxunderrun++; - ninfo("c_rxunderrun: %d\n", c5471->c_rxunderrun); + priv->c_rxunderrun++; + ninfo("c_rxunderrun: %d\n", priv->c_rxunderrun); } if ((rxstatus & EIM_TXDESC_LOC) != 0) { - c5471->c_rxloc++; - ninfo("c_rxloc: %d\n", c5471->c_rxloc); + priv->c_rxloc++; + ninfo("c_rxloc: %d\n", priv->c_rxloc); } } } @@ -1145,7 +1197,7 @@ static void c5471_rxstatus(struct c5471_driver_s *c5471) * An interrupt was received indicating the availability of a new RX packet * * Parameters: - * c5471 - Reference to the driver state structure + * priv - Reference to the driver state structure * * Returned Value: * None @@ -1154,9 +1206,9 @@ static void c5471_rxstatus(struct c5471_driver_s *c5471) * ****************************************************************************/ -static void c5471_receive(struct c5471_driver_s *c5471) +static void c5471_receive(struct c5471_driver_s *priv) { - struct net_driver_s *dev = &c5471->c_dev; + struct net_driver_s *dev = &priv->c_dev; uint16_t *packetmem; bool bmore = true; int packetlen = 0; @@ -1170,12 +1222,12 @@ static void c5471_receive(struct c5471_driver_s *c5471) * the EIM for additional packets that might be received later from the network. */ - ninfo("Reading TX CPU desc: %08x\n", c5471->c_txcpudesc); + ninfo("Reading TX CPU desc: %08x\n", priv->c_txcpudesc); while (bmore) { /* Words #0 and #1 of descriptor */ - if (EIM_TXDESC_OWN_HOST & getreg32(c5471->c_txcpudesc)) + if (EIM_TXDESC_OWN_HOST & getreg32(priv->c_txcpudesc)) { /* No further packets to receive. */ @@ -1186,7 +1238,7 @@ static void c5471_receive(struct c5471_driver_s *c5471) * and update the accumulated packet size */ - framelen = (getreg32(c5471->c_txcpudesc) & EIM_TXDESC_BYTEMASK); + framelen = (getreg32(priv->c_txcpudesc) & EIM_TXDESC_BYTEMASK); packetlen += framelen; /* Check if the received packet will fit within the network packet buffer */ @@ -1195,7 +1247,7 @@ static void c5471_receive(struct c5471_driver_s *c5471) { /* Get the packet memory from words #2 and #3 of descriptor */ - packetmem = (uint16_t *)getreg32(c5471->c_txcpudesc + sizeof(uint32_t)); + packetmem = (uint16_t *)getreg32(priv->c_txcpudesc + sizeof(uint32_t)); /* Divide by 2 with round up to get the number of 16-bit words. */ @@ -1205,7 +1257,7 @@ static void c5471_receive(struct c5471_driver_s *c5471) for (i = 0 ; i < nshorts; i++, j++) { - /* Copy the data data from the hardware to c5471->c_dev.d_buf 16-bits at + /* Copy the data data from the hardware to priv->c_dev.d_buf 16-bits at * a time. */ @@ -1217,7 +1269,7 @@ static void c5471_receive(struct c5471_driver_s *c5471) ninfo("Discarding framelen: %d packetlen\n", framelen, packetlen); } - if (getreg32(c5471->c_txcpudesc) & EIM_TXDESC_LIF) + if (getreg32(priv->c_txcpudesc) & EIM_TXDESC_LIF) { bmore = false; } @@ -1226,16 +1278,16 @@ static void c5471_receive(struct c5471_driver_s *c5471) * the settings of a select few. Can leave descriptor words 2/3 alone. */ - putreg32((getreg32(c5471->c_txcpudesc) & (EIM_TXDESC_WRAP_NEXT | EIM_TXDESC_INTRE)), - c5471->c_txcpudesc); + putreg32((getreg32(priv->c_txcpudesc) & (EIM_TXDESC_WRAP_NEXT | EIM_TXDESC_INTRE)), + priv->c_txcpudesc); /* Next, Give ownership of now emptied descriptor back to the Ether Module's SWITCH */ - putreg32((getreg32(c5471->c_txcpudesc) | EIM_TXDESC_OWN_HOST), c5471->c_txcpudesc); + putreg32((getreg32(priv->c_txcpudesc) | EIM_TXDESC_OWN_HOST), priv->c_txcpudesc); /* Advance to the next data buffer */ - c5471_inctxcpu(c5471); + c5471_inctxcpu(priv); } /* Adjust the packet length to remove the CRC bytes that the network doesn't care about. */ @@ -1245,7 +1297,7 @@ static void c5471_receive(struct c5471_driver_s *c5471) #ifdef CONFIG_C5471_NET_STATS /* Increment the count of received packets */ - c5471->c_rxpackets++; + priv->c_rxpackets++; #endif /* If we successfully transferred the data into the network buffer, then pass it on @@ -1254,7 +1306,7 @@ static void c5471_receive(struct c5471_driver_s *c5471) if (packetlen > 0 && packetlen < CONFIG_NET_ETH_MTU) { - /* Set amount of data in c5471->c_dev.d_len. */ + /* Set amount of data in priv->c_dev.d_len. */ dev->d_len = packetlen; ninfo("Received packet, packetlen: %d type: %02x\n", packetlen, ntohs(BUF->type)); @@ -1287,7 +1339,7 @@ static void c5471_receive(struct c5471_driver_s *c5471) */ if (dev->d_len > 0 && - (EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc)) == 0) + (EIM_TXDESC_OWN_HOST & getreg32(priv->c_rxcpudesc)) == 0) { /* Update the Ethernet header with the correct MAC address */ @@ -1306,7 +1358,7 @@ static void c5471_receive(struct c5471_driver_s *c5471) /* And send the packet */ - c5471_transmit(c5471); + c5471_transmit(priv); } } else @@ -1327,7 +1379,7 @@ static void c5471_receive(struct c5471_driver_s *c5471) */ if (dev->d_len > 0 && - (EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc)) == 0) + (EIM_TXDESC_OWN_HOST & getreg32(priv->c_rxcpudesc)) == 0) { /* Update the Ethernet header with the correct MAC address */ @@ -1346,7 +1398,7 @@ static void c5471_receive(struct c5471_driver_s *c5471) /* And send the packet */ - c5471_transmit(c5471); + c5471_transmit(priv); } } else @@ -1363,9 +1415,9 @@ static void c5471_receive(struct c5471_driver_s *c5471) */ if (dev->d_len > 0 && - (EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc)) == 0) + (EIM_TXDESC_OWN_HOST & getreg32(priv->c_rxcpudesc)) == 0) { - c5471_transmit(c5471); + c5471_transmit(priv); } } #endif @@ -1376,7 +1428,7 @@ static void c5471_receive(struct c5471_driver_s *c5471) /* Increment the count of dropped packets */ nwarn("WARNING: Too big! packetlen: %d\n", packetlen); - c5471->c_rxdropped++; + priv->c_rxdropped++; } #endif } @@ -1388,7 +1440,7 @@ static void c5471_receive(struct c5471_driver_s *c5471) * An interrupt was received indicating that the last TX packet(s) is done * * Parameters: - * c5471 - Reference to the driver state structure + * priv - Reference to the driver state structure * * Returned Value: * None @@ -1398,27 +1450,27 @@ static void c5471_receive(struct c5471_driver_s *c5471) ****************************************************************************/ #ifdef CONFIG_C5471_NET_STATS -static void c5471_txstatus(struct c5471_driver_s *c5471) +static void c5471_txstatus(struct c5471_driver_s *priv) { - uint32_t desc = c5471->c_lastdescstart; + uint32_t desc = priv->c_lastdescstart; uint32_t txstatus; /* Walk that last packet we just sent to collect xmit status bits. */ txstatus = 0; - if (c5471->c_lastdescstart && c5471->c_lastdescend) + if (priv->c_lastdescstart && priv->c_lastdescend) { for (; ; ) { txstatus |= (getreg32(desc) & EIM_RXDESC_STATUSMASK); - if (desc == c5471->c_lastdescend) + if (desc == priv->c_lastdescend) { break; } /* This packet is made up of several descriptors, find next one in chain. */ - if (EIM_RXDESC_WRAP_NEXT & getreg32(c5471->c_rxcpudesc)) + if (EIM_RXDESC_WRAP_NEXT & getreg32(priv->c_rxcpudesc)) { /* Loop back around to base of descriptor queue. */ @@ -1435,44 +1487,44 @@ static void c5471_txstatus(struct c5471_driver_s *c5471) { if ((txstatus & EIM_RXDESC_MISS) != 0) { - c5471->c_txmiss++; - ninfo("c_txmiss: %d\n", c5471->c_txmiss); + priv->c_txmiss++; + ninfo("c_txmiss: %d\n", priv->c_txmiss); } if ((txstatus & EIM_RXDESC_VLAN) != 0) { - c5471->c_txvlan++; - ninfo("c_txvlan: %d\n", c5471->c_txvlan); + priv->c_txvlan++; + ninfo("c_txvlan: %d\n", priv->c_txvlan); } if ((txstatus & EIM_RXDESC_LFRAME) != 0) { - c5471->c_txlframe++; - ninfo("c_txlframe: %d\n", c5471->c_txlframe); + priv->c_txlframe++; + ninfo("c_txlframe: %d\n", priv->c_txlframe); } if ((txstatus & EIM_RXDESC_SFRAME) != 0) { - c5471->c_txsframe++; - ninfo("c_txsframe: %d\n", c5471->c_txsframe); + priv->c_txsframe++; + ninfo("c_txsframe: %d\n", priv->c_txsframe); } if ((txstatus & EIM_RXDESC_CRCERROR) != 0) { - c5471->c_txcrc++; - ninfo("c_txcrc: %d\n", c5471->c_txcrc); + priv->c_txcrc++; + ninfo("c_txcrc: %d\n", priv->c_txcrc); } if ((txstatus & EIM_RXDESC_OVERRUN) != 0) { - c5471->c_txoverrun++; - ninfo("c_txoverrun: %d\n", c5471->c_txoverrun); + priv->c_txoverrun++; + ninfo("c_txoverrun: %d\n", priv->c_txoverrun); } if ((txstatus & EIM_RXDESC_OVERRUN) != 0) { - c5471->c_txalign++; - ninfo("c_txalign: %d\n", c5471->c_txalign); + priv->c_txalign++; + ninfo("c_txalign: %d\n", priv->c_txalign); } } } @@ -1485,7 +1537,7 @@ static void c5471_txstatus(struct c5471_driver_s *c5471) * An interrupt was received indicating that the last TX packet(s) is done * * Parameters: - * c5471 - Reference to the driver state structure + * priv - Reference to the driver state structure * * Returned Value: * None @@ -1494,50 +1546,45 @@ static void c5471_txstatus(struct c5471_driver_s *c5471) * ****************************************************************************/ -static void c5471_txdone(struct c5471_driver_s *c5471) +static void c5471_txdone(struct c5471_driver_s *priv) { /* If no further xmits are pending, then cancel the TX timeout */ - wd_cancel(c5471->c_txtimeout); + wd_cancel(priv->c_txtimeout); /* Then poll the network for new XMIT data */ - (void)devif_poll(&c5471->c_dev, c5471_txpoll); + (void)devif_poll(&priv->c_dev, c5471_txpoll); } /**************************************************************************** - * Function: c5471_interrupt + * Function: c5471_interrupt_process * * Description: - * Hardware interrupt handler + * Interrupt processing. This may be performed either within the interrupt + * handler or on the worker thread, depending upon the configuration * * Parameters: - * irq - Number of the IRQ that generated the interrupt - * context - Interrupt register state save info (architecture-specific) + * priv - Reference to the driver state structure * * Returned Value: - * OK on success + * None * * Assumptions: + * The network is locked. * ****************************************************************************/ -static int c5471_interrupt(int irq, FAR void *context) +static inline void c5471_interrupt_process(FAR struct c5471_driver_s *priv) { -#if CONFIG_C5471_NET_NINTERFACES == 1 - register struct c5471_driver_s *c5471 = &g_c5471[0]; -#else -# error "Additional logic needed to support multiple interfaces" -#endif - /* Get and clear interrupt status bits */ - c5471->c_eimstatus = getreg32(EIM_STATUS); + priv->c_eimstatus = getreg32(EIM_STATUS); /* Handle interrupts according to status bit settings */ /* Check if we received an incoming packet, if so, call c5471_receive() */ - if ((EIM_STATUS_CPU_TX & c5471->c_eimstatus) != 0) + if ((EIM_STATUS_CPU_TX & priv->c_eimstatus) != 0) { /* An incoming packet has been received by the EIM from the network and * the interrupt associated with EIM's CPU TX queue has been asserted. It @@ -1549,17 +1596,17 @@ static int c5471_interrupt(int irq, FAR void *context) #ifdef CONFIG_C5471_NET_STATS /* Check for RX errors */ - c5471_rxstatus(c5471); + c5471_rxstatus(priv); #endif /* Process the received packet */ - c5471_receive(c5471); + c5471_receive(priv); } /* Check is a packet transmission just completed. If so, call c5471_txdone */ - if ((EIM_STATUS_CPU_RX & c5471->c_eimstatus) != 0) + if ((EIM_STATUS_CPU_RX & priv->c_eimstatus) != 0) { /* An outgoing packet has been processed by the EIM and the interrupt * associated with EIM's CPU RX que has been asserted. It is the EIM's @@ -1570,65 +1617,184 @@ static int c5471_interrupt(int irq, FAR void *context) #ifdef CONFIG_C5471_NET_STATS /* Check for TX errors */ - c5471_txstatus(c5471); + c5471_txstatus(priv); #endif /* Handle the transmission done event */ - c5471_txdone(c5471); + c5471_txdone(priv); } +} - /* Enable Ethernet interrupts (perhaps excluding the TX done interrupt if - * there are no pending transmissions. - */ +/**************************************************************************** + * Function: c5471_interrupt_work + * + * Description: + * Perform interrupt related work from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() was called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ - return OK; +#ifdef CONFIG_NET_NOINTS +static void c5471_interrupt_work(FAR void *arg) +{ + FAR struct c5471_driver_s *priv = (FAR struct c5471_driver_s *)arg; + net_lock_t state; + + /* Process pending Ethernet interrupts */ + + state = net_lock(); + c5471_interrupt_process(priv); + net_unlock(state); + + /* Re-enable Ethernet interrupts */ + + up_enable_irq(C5471_IRQ_ETHER); } +#endif /**************************************************************************** - * Function: c5471_txtimeout + * Function: c5471_interrupt * * Description: - * Our TX watchdog timed out. Called from the timer interrupt handler. - * The last TX never completed. Reset the hardware and start again. + * Hardware interrupt handler * * Parameters: - * argc - The number of available arguments - * arg - The first argument + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) * * Returned Value: - * None + * OK on success * * Assumptions: * ****************************************************************************/ -static void c5471_txtimeout(int argc, uint32_t arg, ...) +static int c5471_interrupt(int irq, FAR void *context) { - struct c5471_driver_s *c5471 = (struct c5471_driver_s *)arg; +#if CONFIG_C5471_NET_NINTERFACES == 1 + register struct c5471_driver_s *priv = &g_c5471[0]; +#else +# error "Additional logic needed to support multiple interfaces" +#endif + +#ifdef CONFIG_NET_NOINTS + /* Disable further Ethernet interrupts. Because Ethernet interrupts are + * also disabled if the TX timeout event occurs, there can be no race + * condition here. + */ + + up_disable_irq(C5471_IRQ_ETHER); + + /* TODO: Determine if a TX transfer just completed */ + + { + /* If a TX transfer just completed, then cancel the TX timeout so + * there will be no race condition between any subsequent timeout + * expiration and the deferred interrupt processing. + */ + + wd_cancel(priv->c_txtimeout); + } + + /* Cancel any pending poll work */ + + work_cancel(ETHWORK, &priv->c_work); + + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->c_work, c5471_interrupt_work, priv, 0); + +#else + /* Process the interrupt now */ + + c5471_interrupt_process(priv); +#endif + + return OK; +} + +/**************************************************************************** + * Function: c5471_txtimeout_process + * + * Description: + * Process a TX timeout. Called from the either the watchdog timer + * expiration logic or from the worker thread, depending upon the + * configuration. The timeout means that the last TX never completed. + * Reset the hardware and start again. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ +static inline void c5471_txtimeout_process(FAR struct c5471_driver_s *priv) +{ /* Increment statistics */ #ifdef CONFIG_C5471_NET_STATS - c5471->c_txtimeouts++; - ninfo("c_txtimeouts: %d\n", c5471->c_txtimeouts); + priv->c_txtimeouts++; + ninfo("c_txtimeouts: %d\n", priv->c_txtimeouts); #endif /* Then try to restart the hardware */ - c5471_ifdown(&c5471->c_dev); - c5471_ifup(&c5471->c_dev); + c5471_ifdown(&priv->c_dev); + c5471_ifup(&priv->c_dev); /* Then poll the network for new XMIT data */ - (void)devif_poll(&c5471->c_dev, c5471_txpoll); + (void)devif_poll(&priv->c_dev, c5471_txpoll); } /**************************************************************************** - * Function: c5471_polltimer + * Function: c5471_txtimeout_work * * Description: - * Periodic timer handler. Called from the timer interrupt handler. + * Perform TX timeout related work from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void c5471_txtimeout_work(FAR void *arg) +{ + FAR struct c5471_driver_s *priv = (FAR struct c5471_driver_s *)arg; + net_lock_t state; + + /* Process pending Ethernet interrupts */ + + state = net_lock(); + c5471_txtimeout_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: c5471_txtimeout_expiry + * + * Description: + * Our TX watchdog timed out. Called from the timer interrupt handler. + * The last TX never completed. Reset the hardware and start again. * * Parameters: * argc - The number of available arguments @@ -1638,27 +1804,153 @@ static void c5471_txtimeout(int argc, uint32_t arg, ...) * None * * Assumptions: + * Global interrupts are disabled by the watchdog logic. * ****************************************************************************/ -static void c5471_polltimer(int argc, uint32_t arg, ...) +static void c5471_txtimeout_expiry(int argc, wdparm_t arg, ...) { - struct c5471_driver_s *c5471 = (struct c5471_driver_s *)arg; + struct c5471_driver_s *priv = (struct c5471_driver_s *)arg; + +#ifdef CONFIG_NET_NOINTS + /* Disable further Ethernet interrupts. This will prevent some race + * conditions with interrupt work. There is still a potential race + * condition with interrupt work that is already queued and in progress. + */ + + up_disable_irq(C5471_IRQ_ETHER); + + /* Cancel any pending poll or interrupt work. This will have no effect + * on work that has already been started. + */ + + work_cancel(ETHWORK, &priv->c_work); + + /* Schedule to perform the TX timeout processing on the worker thread. */ + + work_queue(ETHWORK, &priv->c_work, c5471_txtimeout_work, priv, 0); +#else + /* Process the timeout now */ + c5471_txtimeout_process(priv); +#endif +} + +/**************************************************************************** + * Function: c5471_poll_process + * + * Description: + * Perform the periodic poll. This may be called either from watchdog + * timer logic or from the worker thread, depending upon the configuration. + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static inline void c5471_poll_process(FAR struct c5471_driver_s *priv) +{ /* Check if the ESM has let go of the RX descriptor giving us access rights * to submit another Ethernet frame. */ - if ((EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc)) == 0) + if ((EIM_TXDESC_OWN_HOST & getreg32(priv->c_rxcpudesc)) == 0) { /* If so, update TCP timing states and poll the network for new XMIT data */ - (void)devif_timer(&c5471->c_dev, c5471_txpoll); + (void)devif_timer(&priv->c_dev, c5471_txpoll); } /* Setup the watchdog poll timer again */ - (void)wd_start(c5471->c_txpoll, C5471_WDDELAY, c5471_polltimer, 1, arg); + (void)wd_start(priv->c_txpoll, C5471_WDDELAY, c5471_poll_expiry, 1, + (wdparm_t)priv); +} + +/**************************************************************************** + * Function: c5471_poll_work + * + * Description: + * Perform periodic polling from the worker thread + * + * Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NOINTS +static void c5471_poll_work(FAR void *arg) +{ + FAR struct c5471_driver_s *priv = (FAR struct c5471_driver_s *)arg; + net_lock_t state; + + /* Perform the poll */ + + state = net_lock(); + c5471_poll_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: c5471_poll_expiry + * + * Description: + * Periodic timer handler. Called from the timer interrupt handler. + * + * Parameters: + * argc - The number of available arguments + * arg - The first argument + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * + ****************************************************************************/ + +static void c5471_poll_expiry(int argc, wdparm_t arg, ...) +{ + struct c5471_driver_s *priv = (struct c5471_driver_s *)arg; + +#ifdef CONFIG_NET_NOINTS + /* Is our single work structure available? It may not be if there are + * pending interrupt actions. + */ + + if (work_available(&priv->c_work)) + { + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->c_work, c5471_poll_work, priv, 0); + } + else + { + /* No.. Just re-start the watchdog poll timer, missing one polling + * cycle. + */ + + (void)wd_start(priv->c_txpoll, C5471_WDDELAY, c5471_poll_expiry, + 1, arg); + } + +#else + /* Process the interrupt now */ + + c5471_poll_process(priv); +#endif } /**************************************************************************** @@ -1681,7 +1973,7 @@ static void c5471_polltimer(int argc, uint32_t arg, ...) static int c5471_ifup(struct net_driver_s *dev) { - struct c5471_driver_s *c5471 = (struct c5471_driver_s *)dev->d_private; + struct c5471_driver_s *priv = (struct c5471_driver_s *)dev->d_private; volatile uint32_t clearbits; ninfo("Bringing up: %d.%d.%d.%d\n", @@ -1690,11 +1982,11 @@ static int c5471_ifup(struct net_driver_s *dev) /* Initilize Ethernet interface */ - c5471_reset(c5471); + c5471_reset(priv); /* Assign the MAC to the device */ - c5471_macassign(c5471); + c5471_macassign(priv); /* Clear pending interrupts by reading the EIM status register */ @@ -1716,11 +2008,12 @@ static int c5471_ifup(struct net_driver_s *dev) /* Set and activate a timer process */ - (void)wd_start(c5471->c_txpoll, C5471_WDDELAY, c5471_polltimer, 1, (uint32_t)c5471); + (void)wd_start(priv->c_txpoll, C5471_WDDELAY, c5471_poll_expiry, + 1, (wdparm_t)priv); /* Enable the Ethernet interrupt */ - c5471->c_bifup = true; + priv->c_bifup = true; up_enable_irq(C5471_IRQ_ETHER); return OK; } @@ -1743,7 +2036,7 @@ static int c5471_ifup(struct net_driver_s *dev) static int c5471_ifdown(struct net_driver_s *dev) { - struct c5471_driver_s *c5471 = (struct c5471_driver_s *)dev->d_private; + struct c5471_driver_s *priv = (struct c5471_driver_s *)dev->d_private; irqstate_t flags; ninfo("Stopping\n"); @@ -1768,26 +2061,24 @@ static int c5471_ifdown(struct net_driver_s *dev) /* Cancel the TX poll timer and TX timeout timers */ - wd_cancel(c5471->c_txpoll); - wd_cancel(c5471->c_txtimeout); + wd_cancel(priv->c_txpoll); + wd_cancel(priv->c_txtimeout); /* Reset the device */ - c5471->c_bifup = false; + priv->c_bifup = false; leave_critical_section(flags); return OK; } /**************************************************************************** - * Function: c5471_txavail + * Function: c5471_txavail_process * * Description: - * Driver callback invoked when new TX data is available. This is a - * stimulus perform an out-of-cycle poll and, thereby, reduce the TX - * latency. + * Perform an out-of-cycle poll. * * Parameters: - * dev - Reference to the NuttX driver state structure + * dev - Reference to the NuttX driver state structure * * Returned Value: * None @@ -1797,31 +2088,109 @@ static int c5471_ifdown(struct net_driver_s *dev) * ****************************************************************************/ -static int c5471_txavail(struct net_driver_s *dev) +static inline void c5471_txavail_process(FAR struct c5471_driver_s *priv) { - struct c5471_driver_s *c5471 = (struct c5471_driver_s *)dev->d_private; - irqstate_t flags; - ninfo("Polling\n"); - flags = enter_critical_section(); /* Ignore the notification if the interface is not yet up */ - if (c5471->c_bifup) + if (priv->c_bifup) { /* Check if the ESM has let go of the RX descriptor giving us access * rights to submit another Ethernet frame. */ - if ((EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc)) == 0) + if ((EIM_TXDESC_OWN_HOST & getreg32(priv->c_rxcpudesc)) == 0) { /* If so, then poll the network for new XMIT data */ - (void)devif_poll(&c5471->c_dev, c5471_txpoll); + (void)devif_poll(&priv->c_dev, c5471_txpoll); } } +} + +/**************************************************************************** + * Function: c5471_txavail_work + * + * Description: + * Perform an out-of-cycle poll on the worker thread. + * + * Parameters: + * arg - Reference to the NuttX driver state structure (cast to void*) + * + * Returned Value: + * None + * + * Assumptions: + * Called on the higher priority worker thread. + * + ****************************************************************************/ +#ifdef CONFIG_NET_NOINTS +static void c5471_txavail_work(FAR void *arg) +{ + FAR struct c5471_driver_s *priv = (FAR struct c5471_driver_s *)arg; + net_lock_t state; + + /* Perform the poll */ + + state = net_lock(); + c5471_txavail_process(priv); + net_unlock(state); +} +#endif + +/**************************************************************************** + * Function: c5471_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static int c5471_txavail(FAR struct net_driver_s *dev) +{ + struct c5471_driver_s *priv = (struct c5471_driver_s *)dev->d_private; + +#ifdef CONFIG_NET_NOINTS + /* Is our single work structure available? It may not be if there are + * pending interrupt actions and we will have to ignore the Tx + * availability action. + */ + + if (work_available(&priv->c_work)) + { + /* Schedule to serialize the poll on the worker thread. */ + + work_queue(ETHWORK, &priv->c_work, c5471_txavail_work, priv, 0); + } + +#else + irqstate_t flags; + + /* Disable interrupts because this function may be called from interrupt + * level processing. + */ + + flags = enter_critical_section(); + + /* Perform the out-of-cycle poll now */ + + c5471_txavail_process(priv); leave_critical_section(flags); +#endif + return OK; } @@ -1899,7 +2268,7 @@ static int c5471_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac) * ****************************************************************************/ -static void c5471_eimreset (struct c5471_driver_s *c5471) +static void c5471_eimreset (struct c5471_driver_s *priv) { /* Stop the EIM module clock */ @@ -1929,8 +2298,8 @@ static void c5471_eimreset (struct c5471_driver_s *c5471) /* All EIM register should now be in there power-up default states */ - c5471->c_lastdescstart = 0; - c5471->c_lastdescend = 0; + priv->c_lastdescstart = 0; + priv->c_lastdescend = 0; } /**************************************************************************** @@ -1943,7 +2312,7 @@ static void c5471_eimreset (struct c5471_driver_s *c5471) * ****************************************************************************/ -static void c5471_eimconfig(struct c5471_driver_s *c5471) +static void c5471_eimconfig(struct c5471_driver_s *priv) { volatile uint32_t pbuf; volatile uint32_t desc; @@ -2010,7 +2379,7 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471) /* TX CPU */ ninfo("TX CPU desc: %08x pbuf: %08x\n", desc, pbuf); - c5471->c_txcpudesc = desc; + priv->c_txcpudesc = desc; putreg32((desc & 0x0000ffff), EIM_CPU_TXBA); /* 16-bit offset address */ for (i = NUM_DESC_TX-1; i >= 0; i--) { @@ -2040,7 +2409,7 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471) /* RX CPU */ ninfo("RX CPU desc: %08x pbuf: %08x\n", desc, pbuf); - c5471->c_rxcpudesc = desc; + priv->c_rxcpudesc = desc; putreg32((desc & 0x0000ffff), EIM_CPU_RXBA); /* 16-bit offset address */ for (i = NUM_DESC_RX-1; i >= 0; i--) { @@ -2151,17 +2520,17 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471) * ****************************************************************************/ -static void c5471_reset(struct c5471_driver_s *c5471) +static void c5471_reset(struct c5471_driver_s *priv) { #if defined(CONFIG_C5471_PHY_LU3X31T_T64) ninfo("EIM reset\n"); - c5471_eimreset(c5471); + c5471_eimreset(priv); #endif ninfo("PHY init\n"); c5471_phyinit(); ninfo("EIM config\n"); - c5471_eimconfig(c5471); + c5471_eimconfig(priv); } /**************************************************************************** @@ -2176,9 +2545,9 @@ static void c5471_reset(struct c5471_driver_s *c5471) * ****************************************************************************/ -static void c5471_macassign(struct c5471_driver_s *c5471) +static void c5471_macassign(struct c5471_driver_s *priv) { - struct net_driver_s *dev = &c5471->c_dev; + struct net_driver_s *dev = &priv->c_dev; uint8_t *mptr = dev->d_mac.ether_addr_octet; register uint32_t tmp; diff --git a/configs/c5471evm/httpd/defconfig b/configs/c5471evm/httpd/defconfig index 899863f4ae..a9b069c742 100644 --- a/configs/c5471evm/httpd/defconfig +++ b/configs/c5471evm/httpd/defconfig @@ -167,6 +167,7 @@ CONFIG_C5471_PHY_LU3X31T_T64=y CONFIG_C5471_AUTONEGOTIATION=y # CONFIG_C5471_BASET100 is not set # CONFIG_C5471_BASET10 is not set +CONFIG_C5471_HPWORK=y # # Architecture Options @@ -312,6 +313,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -320,13 +322,17 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -471,7 +477,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/c5471evm/nettest/defconfig b/configs/c5471evm/nettest/defconfig index 01c04e1c2d..2e7f35e1fb 100644 --- a/configs/c5471evm/nettest/defconfig +++ b/configs/c5471evm/nettest/defconfig @@ -167,6 +167,7 @@ CONFIG_C5471_PHY_LU3X31T_T64=y CONFIG_C5471_AUTONEGOTIATION=y # CONFIG_C5471_BASET100 is not set # CONFIG_C5471_BASET10 is not set +CONFIG_C5471_HPWORK=y # # Architecture Options @@ -306,6 +307,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -313,13 +315,17 @@ CONFIG_NAME_MAX=32 CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -464,7 +470,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/c5471evm/nsh/defconfig b/configs/c5471evm/nsh/defconfig index 5bbf9895e7..96874ffa0f 100644 --- a/configs/c5471evm/nsh/defconfig +++ b/configs/c5471evm/nsh/defconfig @@ -167,6 +167,7 @@ CONFIG_C5471_PHY_LU3X31T_T64=y CONFIG_C5471_AUTONEGOTIATION=y # CONFIG_C5471_BASET100 is not set # CONFIG_C5471_BASET10 is not set +CONFIG_C5471_HPWORK=y # # Architecture Options @@ -312,6 +313,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -320,13 +322,17 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -472,7 +478,7 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -# CONFIG_NET_NOINTS is not set +CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/drivers/net/skeleton.c b/drivers/net/skeleton.c index 1cfb8277d6..0a6de71539 100644 --- a/drivers/net/skeleton.c +++ b/drivers/net/skeleton.c @@ -162,6 +162,7 @@ static int skel_txpoll(FAR struct net_driver_s *dev); static void skel_receive(FAR struct skel_driver_s *priv); static void skel_txdone(FAR struct skel_driver_s *priv); + static inline void skel_interrupt_process(FAR struct skel_driver_s *priv); #ifdef CONFIG_NET_NOINTS static void skel_interrupt_work(FAR void *arg); -- GitLab From bdb8275824b571d7aeec0678eedf3eb9259bcc15 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 3 Dec 2016 12:21:18 -0600 Subject: [PATCH 581/734] Update TODO list --- TODO | 48 +++++++++++++----------------------------------- 1 file changed, 13 insertions(+), 35 deletions(-) diff --git a/TODO b/TODO index b943d40b4a..9282df6df6 100644 --- a/TODO +++ b/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated December 2, 2016) +NuttX TODO List (Last updated December 3, 2016) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with @@ -1043,40 +1043,18 @@ o Network (net/, drivers/net) Priority: Medium. Important on slow applications that will not accept connections promptly. - Title: INTERRUPT LEVEL PROCESSING IN ETHERNET DRIVERS - Description: Too many Ethernet drivers do interrupt-level processing with - the network stack. The network stack supports either interrupt - level processing or normal task level processing (depending on - CONFIG_NET_NOINTS). This is really a very bad use of CPU - resources; All of the network stack processing should be - modified to use a work queue (and, all use of CONFIG_NET_NOINTS=n - should be eliminated). This applies to many Ethernet drivers: - - ARCHITECTURE CONFIG_NET_NOINTS? ADDRESS FILTER SUPPORT? - C5471 NO NO - STM32 YES YES - STM32F7 YES YES - TIVA ----------------------- ------ - LM3S YES NO - TM4C YES YES - eZ80 YES NO - Kinetis YES YES (not tested) - LPC17xx YES YES (not tested) - LPC43xx YES YES (not tested) - DMxxx NIC YES NO - PIC32 YES NO - SAM3/4 YES YES - SAMA5D ----------------------- ------ - EMACA YES YES (not tested) - EMACB YES YES - GMAC YES YES (not tested) - SAMV7 YES YES - SIM N/A (No interrupts) NO - - The general outline of how this might be done is included in - drivers/net/skeleton.c - Status: Open - Priority: Pretty high if you want a well behaved system. + Title: IPv6 REQUIRES ADDRESS FILTER SUPPORT + Description: IPv6 requires that the Ethernet driver support NuttX address + filter interfaces. Several Ethernet drivers do support there, + however. Others support the address filtering interfaces but + have never been verifed: + + C5471, LM3X, ez80, DM0x90 NIC, PIC: Do not support address + filteringing. + Kinetis, LPC17xx, LPC43xx: Untested address filter support + + Status: Open + Priority: Pretty high if you want a to use IPv6 on these platforms. Title: UDP MULTICAST RECEPTION Description: The logic in udp_input() expects either a single receive socket or -- GitLab From 7467329a986debe08d03f2226f09222746bc93ae Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 3 Dec 2016 16:28:19 -0600 Subject: [PATCH 582/734] Eliminate CONFIG_NO_NOINTS. Lots of files changed -> lots of testing needed. --- arch/arm/src/c5471/c5471_ethernet.c | 255 +++--------- arch/arm/src/kinetis/kinetis_enet.c | 243 ++--------- arch/arm/src/lpc17xx/lpc17_ethernet.c | 335 ++++----------- arch/arm/src/lpc43xx/lpc43_ethernet.c | 258 ++---------- arch/arm/src/sam34/sam_emac.c | 252 ++--------- arch/arm/src/sama5/sam_emaca.c | 251 ++--------- arch/arm/src/sama5/sam_emacb.c | 251 ++--------- arch/arm/src/sama5/sam_gmac.c | 251 ++--------- arch/arm/src/samv7/sam_emac.c | 255 ++---------- arch/arm/src/stm32/stm32_eth.c | 261 +++--------- arch/arm/src/stm32f7/stm32_ethernet.c | 263 +++--------- arch/arm/src/tiva/lm3s_ethernet.c | 252 ++--------- arch/arm/src/tiva/tm4c_ethernet.c | 257 +++--------- arch/mips/src/pic32mx/pic32mx-ethernet.c | 253 ++--------- arch/mips/src/pic32mz/pic32mz-ethernet.c | 253 ++--------- arch/misoc/src/common/misoc_net.c | 256 +++--------- arch/z80/src/ez80/ez80_emac.c | 393 +++--------------- configs/c5471evm/httpd/defconfig | 1 - configs/c5471evm/nettest/defconfig | 1 - configs/c5471evm/nsh/defconfig | 1 - configs/cloudctrl/nsh/defconfig | 1 - configs/dk-tm4c129x/README.txt | 1 - configs/dk-tm4c129x/ipv6/defconfig | 1 - configs/dk-tm4c129x/nsh/defconfig | 1 - configs/eagle100/httpd/defconfig | 1 - configs/eagle100/nettest/defconfig | 1 - configs/eagle100/nsh/defconfig | 1 - configs/eagle100/thttpd/defconfig | 1 - configs/ekk-lm3s9b96/nsh/defconfig | 1 - configs/ez80f910200zco/dhcpd/defconfig | 1 - configs/ez80f910200zco/httpd/defconfig | 1 - configs/ez80f910200zco/nettest/defconfig | 1 - configs/ez80f910200zco/nsh/defconfig | 1 - configs/ez80f910200zco/poll/defconfig | 1 - configs/fire-stm32v2/nsh/defconfig | 1 - configs/freedom-k64f/README.txt | 1 - configs/freedom-k64f/netnsh/defconfig | 1 - configs/lincoln60/netnsh/defconfig | 1 - configs/lincoln60/thttpd-binfs/defconfig | 1 - configs/lm3s6432-s2e/nsh/defconfig | 1 - configs/lm3s6965-ek/discover/defconfig | 1 - configs/lm3s6965-ek/nsh/defconfig | 1 - configs/lm3s6965-ek/tcpecho/defconfig | 1 - configs/lm3s8962-ek/nsh/defconfig | 1 - configs/lpcxpresso-lpc1768/dhcpd/defconfig | 1 - configs/lpcxpresso-lpc1768/nsh/defconfig | 1 - configs/lpcxpresso-lpc1768/thttpd/defconfig | 1 - configs/misoc/hello/defconfig | 1 - configs/moxa/nsh/defconfig | 1 - configs/ntosd-dm320/nettest/defconfig | 1 - configs/ntosd-dm320/nsh/defconfig | 1 - configs/ntosd-dm320/poll/defconfig | 1 - configs/ntosd-dm320/thttpd/defconfig | 1 - configs/ntosd-dm320/udp/defconfig | 1 - configs/ntosd-dm320/webserver/defconfig | 1 - configs/olimex-lpc1766stk/ftpc/defconfig | 1 - configs/olimex-lpc1766stk/hidmouse/defconfig | 1 - configs/olimex-lpc1766stk/nettest/defconfig | 1 - configs/olimex-lpc1766stk/nsh/defconfig | 1 - .../olimex-lpc1766stk/slip-httpd/defconfig | 1 - .../olimex-lpc1766stk/thttpd-binfs/defconfig | 1 - .../olimex-lpc1766stk/thttpd-nxflat/defconfig | 1 - configs/olimex-lpc1766stk/zmodem/defconfig | 1 - configs/olimex-stm32-e407/discover/defconfig | 1 - configs/olimex-stm32-e407/netnsh/defconfig | 1 - configs/olimex-stm32-e407/telnetd/defconfig | 1 - configs/olimex-stm32-e407/webserver/defconfig | 1 - configs/olimex-stm32-p107/nsh/defconfig | 1 - configs/olimex-stm32-p207/nsh/defconfig | 1 - configs/olimex-strp711/nettest/defconfig | 1 - configs/pic32mx-starterkit/nsh2/defconfig | 1 - configs/pic32mx7mmb/nsh/defconfig | 1 - configs/sam4e-ek/nsh/defconfig | 1 - configs/sam4e-ek/nxwm/defconfig | 1 - configs/sam4e-ek/usbnsh/defconfig | 1 - configs/sama5d3-xplained/bridge/defconfig | 1 - configs/sama5d4-ek/bridge/defconfig | 1 - configs/sama5d4-ek/ipv6/defconfig | 1 - configs/sama5d4-ek/nsh/defconfig | 1 - configs/sama5d4-ek/nxwm/defconfig | 1 - configs/same70-xplained/README.txt | 1 - configs/same70-xplained/netnsh/defconfig | 1 - configs/samv71-xult/README.txt | 1 - configs/samv71-xult/netnsh/defconfig | 1 - configs/samv71-xult/vnc/defconfig | 1 - configs/samv71-xult/vnxwm/defconfig | 1 - configs/shenzhou/nsh/defconfig | 1 - configs/shenzhou/nxwm/defconfig | 1 - configs/shenzhou/thttpd/defconfig | 1 - configs/sim/nettest/defconfig | 1 - configs/sim/udgram/defconfig | 1 - configs/sim/ustream/defconfig | 1 - configs/stm3220g-eval/dhcpd/defconfig | 1 - configs/stm3220g-eval/nettest/defconfig | 1 - configs/stm3220g-eval/nsh/defconfig | 1 - configs/stm3220g-eval/nsh2/defconfig | 1 - configs/stm3220g-eval/nxwm/defconfig | 1 - configs/stm3220g-eval/telnetd/defconfig | 1 - configs/stm3240g-eval/dhcpd/defconfig | 1 - configs/stm3240g-eval/discover/defconfig | 1 - configs/stm3240g-eval/nettest/defconfig | 1 - configs/stm3240g-eval/nsh/defconfig | 1 - configs/stm3240g-eval/nsh2/defconfig | 1 - configs/stm3240g-eval/nxterm/defconfig | 1 - configs/stm3240g-eval/nxwm/defconfig | 1 - configs/stm3240g-eval/telnetd/defconfig | 1 - configs/stm3240g-eval/webserver/defconfig | 1 - configs/stm3240g-eval/xmlrpc/defconfig | 1 - configs/stm32butterfly2/nshnet/defconfig | 1 - configs/stm32f4discovery/ipv6/defconfig | 1 - configs/stm32f4discovery/netnsh/defconfig | 1 - configs/tm4c1294-launchpad/ipv6/defconfig | 1 - configs/tm4c1294-launchpad/nsh/defconfig | 1 - configs/u-blox-c027/nsh/defconfig | 1 - configs/viewtool-stm32f107/netnsh/defconfig | 1 - configs/zkit-arm-1769/hello/defconfig | 1 - configs/zkit-arm-1769/nsh/defconfig | 1 - configs/zkit-arm-1769/nxhello/defconfig | 1 - configs/zkit-arm-1769/thttpd/defconfig | 1 - drivers/net/Kconfig | 5 +- drivers/net/dm90x0.c | 258 +++--------- drivers/net/enc28j60.c | 21 +- drivers/net/encx24j600.c | 21 +- drivers/net/ftmac100.c | 270 +++--------- drivers/net/loopback.c | 16 +- drivers/net/skeleton.c | 241 +++-------- drivers/net/slip.c | 15 +- drivers/net/tun.c | 96 ++--- include/nuttx/net/net.h | 58 +-- include/nuttx/net/slip.h | 6 +- net/Kconfig | 17 +- net/arp/arp_send.c | 5 +- net/devif/devif_callback.c | 22 +- net/icmp/icmp_ping.c | 5 +- net/icmpv6/icmpv6_autoconfig.c | 25 +- net/icmpv6/icmpv6_neighbor.c | 5 +- net/icmpv6/icmpv6_ping.c | 5 +- net/igmp/igmp_group.c | 18 +- net/igmp/igmp_leave.c | 5 +- net/igmp/igmp_msg.c | 12 +- net/igmp/igmp_timer.c | 7 +- net/local/local_connect.c | 21 +- net/local/local_listen.c | 5 +- net/local/local_netpoll.c | 5 +- net/local/local_release.c | 5 +- net/netdev/netdev_count.c | 5 +- net/netdev/netdev_default.c | 7 +- net/netdev/netdev_findbyaddr.c | 14 +- net/netdev/netdev_findbyindex.c | 7 +- net/netdev/netdev_findbyname.c | 7 +- net/netdev/netdev_foreach.c | 5 +- net/netdev/netdev_register.c | 5 +- net/netdev/netdev_unregister.c | 5 +- net/netdev/netdev_verify.c | 5 +- net/pkt/pkt_send.c | 5 +- net/route/net_addroute.c | 10 +- net/route/net_allocroute.c | 24 +- net/route/net_foreachroute.c | 10 +- net/socket/accept.c | 10 +- net/socket/connect.c | 5 +- net/socket/getsockname.c | 14 +- net/socket/net_clone.c | 5 +- net/socket/net_close.c | 5 +- net/socket/net_monitor.c | 19 +- net/socket/net_sendfile.c | 5 +- net/socket/net_vfcntl.c | 5 +- net/socket/recvfrom.c | 19 +- net/socket/setsockopt.c | 9 +- net/tcp/tcp_backlog.c | 5 +- net/tcp/tcp_conn.c | 25 +- net/tcp/tcp_listen.c | 10 +- net/tcp/tcp_netpoll.c | 12 +- net/tcp/tcp_send_buffered.c | 7 +- net/tcp/tcp_send_unbuffered.c | 5 +- net/udp/udp_conn.c | 9 +- net/udp/udp_netpoll.c | 12 +- net/udp/udp_psock_sendto.c | 5 +- net/utils/Make.defs | 8 +- net/utils/net_lock.c | 9 +- net/utils/utils.h | 4 - 180 files changed, 1225 insertions(+), 4901 deletions(-) diff --git a/arch/arm/src/c5471/c5471_ethernet.c b/arch/arm/src/c5471/c5471_ethernet.c index b041574ea5..a163cecaab 100644 --- a/arch/arm/src/c5471/c5471_ethernet.c +++ b/arch/arm/src/c5471/c5471_ethernet.c @@ -59,11 +59,7 @@ #include #include #include - -#ifdef CONFIG_NET_NOINTS -# include -#endif - +#include #include #include @@ -84,13 +80,12 @@ * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +#if !defined(CONFIG_SCHED_WORKQUEUE) # error Work queue support is required in this configuration (CONFIG_SCHED_WORKQUEUE) -#endif +#else -/* Use the low priority work queue if possible */ + /* Use the low priority work queue if possible */ -#if defined(CONFIG_SCHED_WORKQUEUE) # if defined(CONFIG_C5471_HPWORK) # define ETHWORK HPWORK # elif defined(CONFIG_C5471_LPWORK) @@ -317,9 +312,7 @@ struct c5471_driver_s bool c_bifup; /* true:ifup false:ifdown */ WDOG_ID c_txpoll; /* TX poll timer */ WDOG_ID c_txtimeout; /* TX timeout timer */ -#ifdef CONFIG_NET_NOINTS struct work_s c_work; /* For deferring work to the work queue */ -#endif /* Note: According to the C547x documentation: "The software has to maintain * two pointers to the current RX-CPU and TX-CPU descriptors. At init time, @@ -407,25 +400,15 @@ static void c5471_txstatus(struct c5471_driver_s *priv); #endif static void c5471_txdone(struct c5471_driver_s *priv); -static inline void c5471_interrupt_process(FAR struct c5471_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void c5471_interrupt_work(FAR void *arg); -#endif - static int c5471_interrupt(int irq, FAR void *context); /* Watchdog timer expirations */ -static inline void c5471_txtimeout_process(FAR struct c5471_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void c5471_txtimeout_work(FAR void *arg); -#endif static void c5471_txtimeout_expiry(int argc, uint32_t arg, ...); -static inline void c5471_poll_process(FAR struct c5471_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void c5471_poll_work(FAR void *arg); -#endif static void c5471_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ @@ -433,10 +416,7 @@ static void c5471_poll_expiry(int argc, uint32_t arg, ...); static int c5471_ifup(struct net_driver_s *dev); static int c5471_ifdown(struct net_driver_s *dev); -static inline void c5471_txavail_process(FAR struct c5471_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void c5471_txavail_work(FAR void *arg); -#endif static int c5471_txavail(struct net_driver_s *dev); #ifdef CONFIG_NET_IGMP @@ -1558,25 +1538,30 @@ static void c5471_txdone(struct c5471_driver_s *priv) } /**************************************************************************** - * Function: c5471_interrupt_process + * Function: c5471_interrupt_work * * Description: - * Interrupt processing. This may be performed either within the interrupt - * handler or on the worker thread, depending upon the configuration + * Perform interrupt related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: * The network is locked. * ****************************************************************************/ -static inline void c5471_interrupt_process(FAR struct c5471_driver_s *priv) +static void c5471_interrupt_work(FAR void *arg) { + FAR struct c5471_driver_s *priv = (FAR struct c5471_driver_s *)arg; + + /* Process pending Ethernet interrupts */ + + net_lock(); + /* Get and clear interrupt status bits */ priv->c_eimstatus = getreg32(EIM_STATUS); @@ -1624,42 +1609,13 @@ static inline void c5471_interrupt_process(FAR struct c5471_driver_s *priv) c5471_txdone(priv); } -} - -/**************************************************************************** - * Function: c5471_interrupt_work - * - * Description: - * Perform interrupt related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() was called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS -static void c5471_interrupt_work(FAR void *arg) -{ - FAR struct c5471_driver_s *priv = (FAR struct c5471_driver_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - c5471_interrupt_process(priv); - net_unlock(state); + net_unlock(); /* Re-enable Ethernet interrupts */ up_enable_irq(C5471_IRQ_ETHER); } -#endif /**************************************************************************** * Function: c5471_interrupt @@ -1686,7 +1642,6 @@ static int c5471_interrupt(int irq, FAR void *context) # error "Additional logic needed to support multiple interfaces" #endif -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. Because Ethernet interrupts are * also disabled if the TX timeout event occurs, there can be no race * condition here. @@ -1712,37 +1667,33 @@ static int c5471_interrupt(int irq, FAR void *context) /* Schedule to perform the interrupt processing on the worker thread. */ work_queue(ETHWORK, &priv->c_work, c5471_interrupt_work, priv, 0); - -#else - /* Process the interrupt now */ - - c5471_interrupt_process(priv); -#endif - return OK; } /**************************************************************************** - * Function: c5471_txtimeout_process + * Function: c5471_txtimeout_work * * Description: - * Process a TX timeout. Called from the either the watchdog timer - * expiration logic or from the worker thread, depending upon the - * configuration. The timeout means that the last TX never completed. - * Reset the hardware and start again. + * Perform TX timeout related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success + * + * Assumptions: + * The network is locked. * ****************************************************************************/ -static inline void c5471_txtimeout_process(FAR struct c5471_driver_s *priv) +static void c5471_txtimeout_work(FAR void *arg) { + FAR struct c5471_driver_s *priv = (FAR struct c5471_driver_s *)arg; + /* Increment statistics */ + net_lock(); #ifdef CONFIG_C5471_NET_STATS priv->c_txtimeouts++; ninfo("c_txtimeouts: %d\n", priv->c_txtimeouts); @@ -1756,39 +1707,9 @@ static inline void c5471_txtimeout_process(FAR struct c5471_driver_s *priv) /* Then poll the network for new XMIT data */ (void)devif_poll(&priv->c_dev, c5471_txpoll); + net_unlock(); } -/**************************************************************************** - * Function: c5471_txtimeout_work - * - * Description: - * Perform TX timeout related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void c5471_txtimeout_work(FAR void *arg) -{ - FAR struct c5471_driver_s *priv = (FAR struct c5471_driver_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - c5471_txtimeout_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: c5471_txtimeout_expiry * @@ -1812,7 +1733,6 @@ static void c5471_txtimeout_expiry(int argc, wdparm_t arg, ...) { struct c5471_driver_s *priv = (struct c5471_driver_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race * conditions with interrupt work. There is still a potential race * condition with interrupt work that is already queued and in progress. @@ -1829,36 +1749,34 @@ static void c5471_txtimeout_expiry(int argc, wdparm_t arg, ...) /* Schedule to perform the TX timeout processing on the worker thread. */ work_queue(ETHWORK, &priv->c_work, c5471_txtimeout_work, priv, 0); -#else - /* Process the timeout now */ - - c5471_txtimeout_process(priv); -#endif } /**************************************************************************** - * Function: c5471_poll_process + * Function: c5471_poll_work * * Description: - * Perform the periodic poll. This may be called either from watchdog - * timer logic or from the worker thread, depending upon the configuration. + * Perform periodic polling from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: + * The network is locked. * ****************************************************************************/ -static inline void c5471_poll_process(FAR struct c5471_driver_s *priv) +static void c5471_poll_work(FAR void *arg) { + FAR struct c5471_driver_s *priv = (FAR struct c5471_driver_s *)arg; + /* Check if the ESM has let go of the RX descriptor giving us access rights * to submit another Ethernet frame. */ + net_lock(); if ((EIM_TXDESC_OWN_HOST & getreg32(priv->c_rxcpudesc)) == 0) { /* If so, update TCP timing states and poll the network for new XMIT data */ @@ -1870,39 +1788,9 @@ static inline void c5471_poll_process(FAR struct c5471_driver_s *priv) (void)wd_start(priv->c_txpoll, C5471_WDDELAY, c5471_poll_expiry, 1, (wdparm_t)priv); + net_unlock(); } -/**************************************************************************** - * Function: c5471_poll_work - * - * Description: - * Perform periodic polling from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void c5471_poll_work(FAR void *arg) -{ - FAR struct c5471_driver_s *priv = (FAR struct c5471_driver_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - c5471_poll_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: c5471_poll_expiry * @@ -1925,7 +1813,6 @@ static void c5471_poll_expiry(int argc, wdparm_t arg, ...) { struct c5471_driver_s *priv = (struct c5471_driver_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions. */ @@ -1945,12 +1832,6 @@ static void c5471_poll_expiry(int argc, wdparm_t arg, ...) (void)wd_start(priv->c_txpoll, C5471_WDDELAY, c5471_poll_expiry, 1, arg); } - -#else - /* Process the interrupt now */ - - c5471_poll_process(priv); -#endif } /**************************************************************************** @@ -2072,28 +1953,31 @@ static int c5471_ifdown(struct net_driver_s *dev) } /**************************************************************************** - * Function: c5471_txavail_process + * Function: c5471_txavail_work * * Description: - * Perform an out-of-cycle poll. + * Perform an out-of-cycle poll on the worker thread. * * Parameters: - * dev - Reference to the NuttX driver state structure + * arg - Reference to the NuttX driver state structure (cast to void*) * * Returned Value: * None * * Assumptions: - * Called in normal user mode + * Called on the higher priority worker thread. * ****************************************************************************/ -static inline void c5471_txavail_process(FAR struct c5471_driver_s *priv) +static void c5471_txavail_work(FAR void *arg) { + FAR struct c5471_driver_s *priv = (FAR struct c5471_driver_s *)arg; + ninfo("Polling\n"); /* Ignore the notification if the interface is not yet up */ + net_lock(); if (priv->c_bifup) { /* Check if the ESM has let go of the RX descriptor giving us access @@ -2107,38 +1991,9 @@ static inline void c5471_txavail_process(FAR struct c5471_driver_s *priv) (void)devif_poll(&priv->c_dev, c5471_txpoll); } } -} -/**************************************************************************** - * Function: c5471_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void c5471_txavail_work(FAR void *arg) -{ - FAR struct c5471_driver_s *priv = (FAR struct c5471_driver_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - c5471_txavail_process(priv); - net_unlock(state); + net_unlock(); } -#endif /**************************************************************************** * Function: c5471_txavail @@ -2163,7 +2018,6 @@ static int c5471_txavail(FAR struct net_driver_s *dev) { struct c5471_driver_s *priv = (struct c5471_driver_s *)dev->d_private; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions and we will have to ignore the Tx * availability action. @@ -2176,21 +2030,6 @@ static int c5471_txavail(FAR struct net_driver_s *dev) work_queue(ETHWORK, &priv->c_work, c5471_txavail_work, priv, 0); } -#else - irqstate_t flags; - - /* Disable interrupts because this function may be called from interrupt - * level processing. - */ - - flags = enter_critical_section(); - - /* Perform the out-of-cycle poll now */ - - c5471_txavail_process(priv); - leave_critical_section(flags); -#endif - return OK; } diff --git a/arch/arm/src/kinetis/kinetis_enet.c b/arch/arm/src/kinetis/kinetis_enet.c index e83c3fcc94..30707e47ac 100644 --- a/arch/arm/src/kinetis/kinetis_enet.c +++ b/arch/arm/src/kinetis/kinetis_enet.c @@ -53,14 +53,11 @@ #include #include #include +#include #include #include #include -#ifdef CONFIG_NET_NOINTS -# include -#endif - #ifdef CONFIG_NET_PKT # include #endif @@ -84,13 +81,12 @@ * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +#if !defined(CONFIG_SCHED_WORKQUEUE) # error Work queue support is required -#endif +#else -/* Select work queue */ + /* Select work queue */ -#if defined(CONFIG_SCHED_WORKQUEUE) # if defined(CONFIG_KINETIS_EMAC_HPWORK) # define ETHWORK HPWORK # elif defined(CONFIG_KINETIS_EMAC_LPWORK) @@ -219,9 +215,7 @@ struct kinetis_driver_s uint8_t phyaddr; /* Selected PHY address */ WDOG_ID txpoll; /* TX poll timer */ WDOG_ID txtimeout; /* TX timeout timer */ -#ifdef CONFIG_NET_NOINTS struct work_s work; /* For deferring work to the work queue */ -#endif struct enet_desc_s *txdesc; /* A pointer to the list of TX descriptor */ struct enet_desc_s *rxdesc; /* A pointer to the list of RX descriptors */ @@ -279,24 +273,15 @@ static int kinetis_txpoll(struct net_driver_s *dev); static void kinetis_receive(FAR struct kinetis_driver_s *priv); static void kinetis_txdone(FAR struct kinetis_driver_s *priv); -static inline void kinetis_interrupt_process(FAR struct kinetis_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void kinetis_interrupt_work(FAR void *arg); -#endif static int kinetis_interrupt(int irq, FAR void *context); /* Watchdog timer expirations */ -static inline void kinetis_txtimeout_process(FAR struct kinetis_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void kinetis_txtimeout_work(FAR void *arg); -#endif static void kinetis_txtimeout_expiry(int argc, uint32_t arg, ...); -static inline void kinetis_poll_process(FAR struct kinetis_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void kinetis_poll_work(FAR void *arg); -#endif static void kinetis_polltimer_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ @@ -304,10 +289,7 @@ static void kinetis_polltimer_expiry(int argc, uint32_t arg, ...); static int kinetis_ifup(struct net_driver_s *dev); static int kinetis_ifdown(struct net_driver_s *dev); -static inline void kinetis_txavail_process(FAR struct kinetis_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void kinetis_txavail_work(FAR void *arg); -#endif static int kinetis_txavail(struct net_driver_s *dev); #ifdef CONFIG_NET_IGMP @@ -824,27 +806,31 @@ static void kinetis_txdone(FAR struct kinetis_driver_s *priv) } /**************************************************************************** - * Function: kinetis_interrupt_process + * Function: kinetis_interrupt_work * * Description: - * Interrupt processing. This may be performed either within the interrupt - * handler or on the worker thread, depending upon the configuration + * Perform interrupt related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: * The network is locked. * ****************************************************************************/ -static inline void kinetis_interrupt_process(FAR struct kinetis_driver_s *priv) +static void kinetis_interrupt_work(FAR void *arg) { + FAR struct kinetis_driver_s *priv = (FAR struct kinetis_driver_s *)arg; uint32_t pending; + /* Process pending Ethernet interrupts */ + + net_lock(); + /* Get the set of unmasked, pending interrupt. */ pending = getreg32(KINETIS_ENET_EIR) & getreg32(KINETIS_ENET_EIMR); @@ -892,36 +878,8 @@ static inline void kinetis_interrupt_process(FAR struct kinetis_driver_s *priv) putreg32(ENET_RDAR, KINETIS_ENET_RDAR); } -} - -/**************************************************************************** - * Function: kinetis_interrupt_work - * - * Description: - * Perform interrupt related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() was called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void kinetis_interrupt_work(FAR void *arg) -{ - FAR struct kinetis_driver_s *priv = (FAR struct kinetis_driver_s *)arg; - net_lock_t state; - /* Process pending Ethernet interrupts */ - - state = net_lock(); - kinetis_interrupt_process(priv); - net_unlock(state); + net_unlock(); /* Re-enable Ethernet interrupts */ @@ -932,7 +890,6 @@ static void kinetis_interrupt_work(FAR void *arg) up_enable_irq(KINETIS_IRQ_EMACRX); up_enable_irq(KINETIS_IRQ_EMACMISC); } -#endif /**************************************************************************** * Function: kinetis_interrupt @@ -958,7 +915,6 @@ static int kinetis_interrupt(int irq, FAR void *context) { register FAR struct kinetis_driver_s *priv = &g_enet[0]; -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. Because Ethernet interrupts are * also disabled if the TX timeout event occurs, there can be no race * condition here. @@ -987,37 +943,33 @@ static int kinetis_interrupt(int irq, FAR void *context) /* Schedule to perform the interrupt processing on the worker thread. */ work_queue(ETHWORK, &priv->work, kinetis_interrupt_work, priv, 0); - -#else - /* Process the interrupt now */ - - kinetis_interrupt_process(priv); -#endif - return OK; } /**************************************************************************** - * Function: kinetis_txtimeout_process + * Function: kinetis_txtimeout_work * * Description: - * Process a TX timeout. Called from the either the watchdog timer - * expiration logic or from the worker thread, depending upon the - * configuration. The timeout means that the last TX never completed. - * Reset the hardware and start again. + * Perform TX timeout related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success + * + * Assumptions: + * The network is locked. * ****************************************************************************/ -static inline void kinetis_txtimeout_process(FAR struct kinetis_driver_s *priv) +static void kinetis_txtimeout_work(FAR void *arg) { + FAR struct kinetis_driver_s *priv = (FAR struct kinetis_driver_s *)arg; + /* Increment statistics and dump debug info */ + net_lock(); NETDEV_TXTIMEOUTS(&priv->dev); /* Take the interface down and bring it back up. The is the most agressive @@ -1030,39 +982,9 @@ static inline void kinetis_txtimeout_process(FAR struct kinetis_driver_s *priv) /* Then poll the network for new XMIT data */ (void)devif_poll(&priv->dev, kinetis_txpoll); + net_unlock(); } -/**************************************************************************** - * Function: kinetis_txtimeout_work - * - * Description: - * Perform TX timeout related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void kinetis_txtimeout_work(FAR void *arg) -{ - FAR struct kinetis_driver_s *priv = (FAR struct kinetis_driver_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - kinetis_txtimeout_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: kinetis_txtimeout_expiry * @@ -1086,7 +1008,6 @@ static void kinetis_txtimeout_expiry(int argc, uint32_t arg, ...) { FAR struct kinetis_driver_s *priv = (FAR struct kinetis_driver_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race * conditions with interrupt work. There is still a potential race * condition with interrupt work that is already queued and in progress. @@ -1106,36 +1027,34 @@ static void kinetis_txtimeout_expiry(int argc, uint32_t arg, ...) /* Schedule to perform the TX timeout processing on the worker thread. */ work_queue(ETHWORK, &priv->work, kinetis_txtimeout_work, priv, 0); -#else - /* Process the timeout now */ - - kinetis_txtimeout_process(priv); -#endif } /**************************************************************************** - * Function: kinetis_poll_process + * Function: kinetis_poll_work * * Description: - * Perform the periodic poll. This may be called either from watchdog - * timer logic or from the worker thread, depending upon the configuration. + * Perform periodic polling from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: + * The network is locked. * ****************************************************************************/ -static inline void kinetis_poll_process(FAR struct kinetis_driver_s *priv) +static void kinetis_poll_work(FAR void *arg) { + FAR struct kinetis_driver_s *priv = (FAR struct kinetis_driver_s *)arg; + /* Check if there is there is a transmission in progress. We cannot perform * the TX poll if he are unable to accept another packet for transmission. */ + net_lock(); if (!kinetics_txringfull(priv)) { /* If so, update TCP timing states and poll the network for new XMIT data. Hmmm.. @@ -1150,39 +1069,9 @@ static inline void kinetis_poll_process(FAR struct kinetis_driver_s *priv) (void)wd_start(priv->txpoll, KINETIS_WDDELAY, kinetis_polltimer_expiry, 1, (wdparm_t)priv); + net_unlock(); } -/**************************************************************************** - * Function: kinetis_poll_work - * - * Description: - * Perform periodic polling from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void kinetis_poll_work(FAR void *arg) -{ - FAR struct kinetis_driver_s *priv = (FAR struct kinetis_driver_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - kinetis_poll_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: kinetis_polltimer_expiry * @@ -1205,7 +1094,6 @@ static void kinetis_polltimer_expiry(int argc, uint32_t arg, ...) { FAR struct kinetis_driver_s *priv = (FAR struct kinetis_driver_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions. */ @@ -1225,12 +1113,6 @@ static void kinetis_polltimer_expiry(int argc, uint32_t arg, ...) (void)wd_start(priv->txpoll, KINETIS_WDDELAY, kinetis_polltimer_expiry, 1, (wdparm_t)arg); } - -#else - /* Process the interrupt now */ - - kinetis_poll_process(priv); -#endif } /**************************************************************************** @@ -1417,29 +1299,29 @@ static int kinetis_ifdown(struct net_driver_s *dev) } /**************************************************************************** - * Function: kinetis_txavail_process + * Function: kinetis_txavail_work * * Description: - * Perform an out-of-cycle poll. + * Perform an out-of-cycle poll on the worker thread. * * Parameters: - * dev - Reference to the NuttX driver state structure + * arg - Reference to the NuttX driver state structure (cast to void*) * * Returned Value: * None * * Assumptions: - * Called in normal user mode + * Called on the higher priority worker thread. * ****************************************************************************/ -static inline void kinetis_txavail_process(FAR struct kinetis_driver_s *priv) +static void kinetis_txavail_work(FAR void *arg) { - net_lock_t state; + FAR struct kinetis_driver_s *priv = (FAR struct kinetis_driver_s *)arg; /* Ignore the notification if the interface is not yet up */ - state = net_lock(); + net_lock(); if (priv->bifup) { /* Check if there is room in the hardware to hold another outgoing @@ -1456,36 +1338,8 @@ static inline void kinetis_txavail_process(FAR struct kinetis_driver_s *priv) } } - net_unlock(state); -} - -/**************************************************************************** - * Function: kinetis_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void kinetis_txavail_work(FAR void *arg) -{ - FAR struct kinetis_driver_s *priv = (FAR struct kinetis_driver_s *)arg; - - /* Perform the poll */ - - kinetis_txavail_process(priv); + net_unlock(); } -#endif /**************************************************************************** * Function: kinetis_txavail @@ -1511,7 +1365,6 @@ static int kinetis_txavail(struct net_driver_s *dev) FAR struct kinetis_driver_s *priv = (FAR struct kinetis_driver_s *)dev->d_private; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions and we will have to ignore the Tx * availability action. @@ -1524,12 +1377,6 @@ static int kinetis_txavail(struct net_driver_s *dev) work_queue(ETHWORK, &priv->work, kinetis_txavail_work, priv, 0); } -#else - /* Perform the out-of-cycle poll now */ - - kinetis_txavail_process(priv); -#endif - return OK; } diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.c b/arch/arm/src/lpc17xx/lpc17_ethernet.c index 545369e055..1ec3d332e2 100644 --- a/arch/arm/src/lpc17xx/lpc17_ethernet.c +++ b/arch/arm/src/lpc17xx/lpc17_ethernet.c @@ -52,15 +52,12 @@ #include #include #include +#include #include #include #include #include -#ifdef CONFIG_NET_NOINTS -# include -#endif - #ifdef CONFIG_NET_PKT # include #endif @@ -87,13 +84,12 @@ * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +#if !defined(CONFIG_SCHED_WORKQUEUE) # error Work queue support is required -#endif +#else -/* Select work queue */ + /* Select work queue */ -#if defined(CONFIG_SCHED_WORKQUEUE) # if defined(CONFIG_LPC17_ETHERNET_HPWORK) # define ETHWORK HPWORK # elif defined(CONFIG_LPC17_ETHERNET_LPWORK) @@ -276,12 +272,10 @@ struct lpc17_driver_s WDOG_ID lp_txpoll; /* TX poll timer */ WDOG_ID lp_txtimeout; /* TX timeout timer */ -#ifdef CONFIG_NET_NOINTS struct work_s lp_txwork; /* TX work continuation */ struct work_s lp_rxwork; /* RX work continuation */ struct work_s lp_pollwork; /* Poll work continuation */ uint32_t status; -#endif /* CONFIG_NET_NOINTS */ /* This holds the information visible to the NuttX networking layer */ @@ -338,26 +332,17 @@ static int lpc17_txpoll(struct net_driver_s *dev); /* Interrupt handling */ static void lpc17_response(struct lpc17_driver_s *priv); -static void lpc17_rxdone_process(struct lpc17_driver_s *priv); -static void lpc17_txdone_process(struct lpc17_driver_s *priv); -#ifdef CONFIG_NET_NOINTS + static void lpc17_txdone_work(FAR void *arg); static void lpc17_rxdone_work(FAR void *arg); -#endif /* CONFIG_NET_NOINTS */ static int lpc17_interrupt(int irq, void *context); /* Watchdog timer expirations */ -static void lpc17_txtimeout_process(FAR struct lpc17_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void lpc17_txtimeout_work(FAR void *arg); -#endif /* CONFIG_NET_NOINTS */ static void lpc17_txtimeout_expiry(int argc, uint32_t arg, ...); -static void lpc17_poll_process(FAR struct lpc17_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void lpc17_poll_work(FAR void *arg); -#endif /* CONFIG_NET_NOINTS */ static void lpc17_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ @@ -368,11 +353,9 @@ static void lpc17_ipv6multicast(FAR struct lpc17_driver_s *priv); static int lpc17_ifup(struct net_driver_s *dev); static int lpc17_ifdown(struct net_driver_s *dev); -static void lpc17_txavail_process(FAR struct lpc17_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void lpc17_txavail_work(FAR void *arg); -#endif static int lpc17_txavail(struct net_driver_s *dev); + #if defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_ICMPv6) static uint32_t lpc17_calcethcrc(const uint8_t *data, size_t length); static int lpc17_addmac(struct net_driver_s *dev, const uint8_t *mac); @@ -805,30 +788,40 @@ static void lpc17_response(struct lpc17_driver_s *priv) } /**************************************************************************** - * Function: lpc17_rxdone_process + * Function: lpc17_rxdone_work * * Description: - * An interrupt was received indicating the availability of a new RX packet + * Perform Rx interrupt handling logic outside of the interrupt handler (on + * the work queue thread). * * Parameters: - * priv - Reference to the driver state structure + * arg - The reference to the driver structure (case to void*) * * Returned Value: * None * * Assumptions: - * Global interrupts are disabled by interrupt handling logic. * ****************************************************************************/ -static void lpc17_rxdone_process(struct lpc17_driver_s *priv) +static void lpc17_rxdone_work(FAR void *arg) { - uint32_t *rxstat; - bool fragment; + FAR struct lpc17_driver_s *priv = (FAR struct lpc17_driver_s *)arg; + irqstate_t flags; + uint32_t *rxstat; + bool fragment; unsigned int prodidx; unsigned int considx; unsigned int pktlen; + DEBUGASSERT(priv); + + /* Perform pending RX work. RX interrupts were disabled prior to + * scheduling this work to prevent work queue overruns. + */ + + net_lock(); + /* Get the current producer and consumer indices */ considx = lpc17_getreg(LPC17_ETH_RXCONSIDX) & ETH_RXCONSIDX_MASK; @@ -1042,37 +1035,55 @@ static void lpc17_rxdone_process(struct lpc17_driver_s *priv) lpc17_putreg(considx, LPC17_ETH_RXCONSIDX); prodidx = lpc17_getreg(LPC17_ETH_RXPRODIDX) & ETH_RXPRODIDX_MASK; } + + net_unlock(); + + /* Re-enable RX interrupts (this must be atomic). Skip this step if the + * lp-txpending TX underrun state is in effect. + */ + + flags = enter_critical_section(); + if (!priv->lp_txpending) + { + priv->lp_inten |= ETH_RXINTS; + lpc17_putreg(priv->lp_inten, LPC17_ETH_INTEN); + } + + leave_critical_section(flags); } + /**************************************************************************** - * Function: lpc17_txdone_process + * Function: lpc17_txdone_work * * Description: - * An interrupt was received indicating that the last TX packet(s) is done + * Perform Tx interrupt handling logic outside of the interrupt handler (on + * the work queue thread). * * Parameters: - * priv - Reference to the driver state structure + * arg - The reference to the driver structure (case to void*) * * Returned Value: * None * - * Assumptions: - * Global interrupts are disabled by interrupt handling logic. - * ****************************************************************************/ -static void lpc17_txdone_process(struct lpc17_driver_s *priv) +static void lpc17_txdone_work(FAR void *arg) { + FAR struct lpc17_driver_s *priv = (FAR struct lpc17_driver_s *)arg; + /* Verify that the hardware is ready to send another packet. Since a Tx * just completed, this must be the case. */ + DEBUGASSERT(priv); DEBUGASSERT(lpc17_txdesc(priv) == OK); /* Check if there is a pending Tx transfer that was scheduled by Rx handling * while the Tx logic was busy. If so, processing that pending Tx now. */ + net_lock(); if (priv->lp_txpending) { /* Clear the pending condition, send the packet, and restore Rx interrupts */ @@ -1091,73 +1102,9 @@ static void lpc17_txdone_process(struct lpc17_driver_s *priv) { (void)devif_poll(&priv->lp_dev, lpc17_txpoll); } -} - -/**************************************************************************** - * Function: lpc17_txdone_work and lpc17_rxdone_work - * - * Description: - * Perform interrupt handling logic outside of the interrupt handler (on - * the work queue thread). - * - * Parameters: - * arg - The reference to the driver structure (case to void*) - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void lpc17_txdone_work(FAR void *arg) -{ - FAR struct lpc17_driver_s *priv = (FAR struct lpc17_driver_s *)arg; - net_lock_t state; - - DEBUGASSERT(priv); - - /* Perform pending TX work. At this point TX interrupts are disable but - * may be re-enabled again depending on the actions of - * lpc17_txdone_process(). - */ - - state = net_lock(); - lpc17_txdone_process(priv); - net_unlock(state); -} - -static void lpc17_rxdone_work(FAR void *arg) -{ - FAR struct lpc17_driver_s *priv = (FAR struct lpc17_driver_s *)arg; - irqstate_t flags; - net_lock_t state; - - DEBUGASSERT(priv); - - /* Perform pending RX work. RX interrupts were disabled prior to - * scheduling this work to prevent work queue overruns. - */ - - state = net_lock(); - lpc17_rxdone_process(priv); - net_unlock(state); - - /* Re-enable RX interrupts (this must be atomic). Skip this step if the - * lp-txpending TX underrun state is in effect. - */ - - flags = enter_critical_section(); - if (!priv->lp_txpending) - { - priv->lp_inten |= ETH_RXINTS; - lpc17_putreg(priv->lp_inten, LPC17_ETH_INTEN); - } - leave_critical_section(flags); + net_unlock(); } -#endif /* CONFIG_NET_NOINTS */ /**************************************************************************** * Function: lpc17_interrupt @@ -1267,8 +1214,6 @@ static int lpc17_interrupt(int irq, void *context) if ((status & ETH_INT_RXFIN) != 0 || (status & ETH_INT_RXDONE) != 0) { /* We have received at least one new incoming packet. */ - -#ifdef CONFIG_NET_NOINTS /* Disable further TX interrupts for now. TX interrupts will * be re-enabled after the work has been processed. */ @@ -1284,11 +1229,6 @@ static int lpc17_interrupt(int irq, void *context) work_queue(ETHWORK, &priv->lp_rxwork, (worker_t)lpc17_rxdone_work, priv, 0); - -#else /* CONFIG_NET_NOINTS */ - lpc17_rxdone_process(priv); - -#endif /* CONFIG_NET_NOINTS */ } /* Check for Tx events ********************************************/ @@ -1337,7 +1277,6 @@ static int lpc17_interrupt(int irq, void *context) priv->lp_inten &= ~ETH_TXINTS; lpc17_putreg(priv->lp_inten, LPC17_ETH_INTEN); -#ifdef CONFIG_NET_NOINTS /* Cancel any pending TX done work (to prevent overruns and also * to avoid race conditions with the TX timeout work) */ @@ -1357,13 +1296,6 @@ static int lpc17_interrupt(int irq, void *context) work_queue(ETHWORK, &priv->lp_txwork, (worker_t)lpc17_txdone_work, priv, 0); - -#else /* CONFIG_NET_NOINTS */ - /* Perform the TX work at the interrupt level */ - - lpc17_txdone_process(priv); - -#endif /* CONFIG_NET_NOINTS */ } } } @@ -1382,26 +1314,29 @@ static int lpc17_interrupt(int irq, void *context) } /**************************************************************************** - * Function: lpc17_txtimeout_process + * Function: lpc17_txtimeout_work * * Description: - * Process a TX timeout. Called from the either the watchdog timer - * expiration logic or from the worker thread, depending upon the - * configuration. The timeout means that the last TX never completed. - * Reset the hardware and start again. + * Perform TX timeout related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success + * + * Assumptions: + * Ethernet interrupts are disabled * ****************************************************************************/ -static void lpc17_txtimeout_process(FAR struct lpc17_driver_s *priv) +static void lpc17_txtimeout_work(FAR void *arg) { + FAR struct lpc17_driver_s *priv = (FAR struct lpc17_driver_s *)arg; + /* Increment statistics and dump debug info */ + net_lock(); NETDEV_TXTIMEOUTS(&priv->lp_dev); if (priv->lp_ifup) { @@ -1415,38 +1350,9 @@ static void lpc17_txtimeout_process(FAR struct lpc17_driver_s *priv) (void)devif_poll(&priv->lp_dev, lpc17_txpoll); } -} - -/**************************************************************************** - * Function: lpc17_txtimeout_work - * - * Description: - * Perform TX timeout related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS -static void lpc17_txtimeout_work(FAR void *arg) -{ - FAR struct lpc17_driver_s *priv = (FAR struct lpc17_driver_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - lpc17_txtimeout_process(priv); - net_unlock(state); + net_unlock(); } -#endif /**************************************************************************** * Function: lpc17_txtimeout_expiry @@ -1478,7 +1384,6 @@ static void lpc17_txtimeout_expiry(int argc, uint32_t arg, ...) priv->lp_inten &= ~ETH_TXINTS; lpc17_putreg(priv->lp_inten, LPC17_ETH_INTEN); -#ifdef CONFIG_NET_NOINTS /* Is the single TX work structure available? If not, then there is * pending TX work to be done this must be a false alarm TX timeout. */ @@ -1489,33 +1394,28 @@ static void lpc17_txtimeout_expiry(int argc, uint32_t arg, ...) work_queue(ETHWORK, &priv->lp_txwork, lpc17_txtimeout_work, priv, 0); } - -#else - /* Process the timeout now */ - - lpc17_txtimeout_process(priv); -#endif } /**************************************************************************** - * Function: lpc17_poll_process + * Function: lpc17_poll_work * * Description: - * Perform the periodic poll. This may be called either from watchdog - * timer logic or from the worker thread, depending upon the configuration. + * Perform periodic polling from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: + * Ethernet interrupts are disabled * ****************************************************************************/ -static void lpc17_poll_process(FAR struct lpc17_driver_s *priv) +static void lpc17_poll_work(FAR void *arg) { + FAR struct lpc17_driver_s *priv = (FAR struct lpc17_driver_s *)arg; unsigned int prodidx; unsigned int considx; @@ -1523,6 +1423,7 @@ static void lpc17_poll_process(FAR struct lpc17_driver_s *priv) * the TX poll if he are unable to accept another packet for transmission. */ + net_lock(); if (lpc17_txdesc(priv) == OK) { /* If so, update TCP timing states and poll the network layer for new @@ -1544,54 +1445,17 @@ static void lpc17_poll_process(FAR struct lpc17_driver_s *priv) if (considx != prodidx) { -#ifdef CONFIG_NET_NOINTS work_queue(ETHWORK, &priv->lp_rxwork, (worker_t)lpc17_rxdone_work, priv, 0); - -#else /* CONFIG_NET_NOINTS */ - lpc17_rxdone_process(priv); - -#endif /* CONFIG_NET_NOINTS */ } /* Setup the watchdog poll timer again */ (void)wd_start(priv->lp_txpoll, LPC17_WDDELAY, lpc17_poll_expiry, 1, priv); + net_unlock(); } -/**************************************************************************** - * Function: lpc17_poll_work - * - * Description: - * Perform periodic polling from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void lpc17_poll_work(FAR void *arg) -{ - FAR struct lpc17_driver_s *priv = (FAR struct lpc17_driver_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - lpc17_poll_process(priv); - net_unlock(state); -} -#endif - - /**************************************************************************** * Function: lpc17_poll_expiry * @@ -1616,7 +1480,6 @@ static void lpc17_poll_expiry(int argc, uint32_t arg, ...) DEBUGASSERT(arg); -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions. */ @@ -1635,12 +1498,6 @@ static void lpc17_poll_expiry(int argc, uint32_t arg, ...) (void)wd_start(priv->lp_txpoll, LPC17_WDDELAY, lpc17_poll_expiry, 1, arg); } - -#else - /* Process the interrupt now */ - - lpc17_poll_process(priv); -#endif } /**************************************************************************** @@ -1932,29 +1789,29 @@ static int lpc17_ifdown(struct net_driver_s *dev) } /**************************************************************************** - * Function: lpc17_txavail_process + * Function: lpc17_txavail_work * * Description: - * Perform an out-of-cycle poll. + * Perform an out-of-cycle poll on the worker thread. * * Parameters: - * dev - Reference to the NuttX driver state structure + * arg - Reference to the NuttX driver state structure (cast to void*) * * Returned Value: * None * * Assumptions: - * Called in normal user mode + * Called on the higher priority worker thread. * ****************************************************************************/ -static inline void lpc17_txavail_process(FAR struct lpc17_driver_s *priv) +static void lpc17_txavail_work(FAR void *arg) { - net_lock_t state; + FAR struct lpc17_driver_s *priv = (FAR struct lpc17_driver_s *)arg; /* Ignore the notification if the interface is not yet up */ - state = net_lock(); + net_lock(); if (priv->lp_ifup) { /* Check if there is room in the hardware to hold another outgoing packet. */ @@ -1967,36 +1824,8 @@ static inline void lpc17_txavail_process(FAR struct lpc17_driver_s *priv) } } - net_unlock(state); -} - -/**************************************************************************** - * Function: lpc17_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void lpc17_txavail_work(FAR void *arg) -{ - FAR struct lpc17_driver_s *priv = (FAR struct lpc17_driver_s *)arg; - - /* Perform the poll */ - - lpc17_txavail_process(priv); + net_unlock(); } -#endif /**************************************************************************** * Function: lpc17_txavail @@ -2021,7 +1850,6 @@ static int lpc17_txavail(struct net_driver_s *dev) { FAR struct lpc17_driver_s *priv = (FAR struct lpc17_driver_s *)dev->d_private; -#ifdef CONFIG_NET_NOINTS /* Is our single poll work structure available? It may not be if there * are pending polling actions and we will have to ignore the Tx * availability action (which is okay because all poll actions have, @@ -2035,13 +1863,6 @@ static int lpc17_txavail(struct net_driver_s *dev) work_queue(ETHWORK, &priv->lp_pollwork, lpc17_txavail_work, priv, 0); } -#else - - /* Perform the out-of-cycle poll now */ - - lpc17_txavail_process(priv); -#endif - return OK; } diff --git a/arch/arm/src/lpc43xx/lpc43_ethernet.c b/arch/arm/src/lpc43xx/lpc43_ethernet.c index 35d9926b52..6060c9cb2a 100644 --- a/arch/arm/src/lpc43xx/lpc43_ethernet.c +++ b/arch/arm/src/lpc43xx/lpc43_ethernet.c @@ -53,11 +53,7 @@ #include #include #include - -#ifdef CONFIG_NET_NOINTS -# include -#endif - +#include #include #include #include @@ -87,13 +83,12 @@ * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +#if !defined(CONFIG_SCHED_WORKQUEUE) # error Work queue support is required -#endif +#else -/* Select work queue */ + /* Select work queue */ -#if defined(CONFIG_SCHED_WORKQUEUE) # if defined(CONFIG_LPC43_ETHERNET_HPWORK) # define ETHWORK HPWORK # elif defined(CONFIG_LPC43_ETHERNET_LPWORK) @@ -524,9 +519,7 @@ struct lpc43_ethmac_s uint8_t fduplex : 1; /* Full (vs. half) duplex */ WDOG_ID txpoll; /* TX poll timer */ WDOG_ID txtimeout; /* TX timeout timer */ -#ifdef CONFIG_NET_NOINTS struct work_s work; /* For deferring work to the work queue */ -#endif /* This holds the information visible to the NuttX network */ @@ -599,34 +592,26 @@ static int lpc43_recvframe(FAR struct lpc43_ethmac_s *priv); static void lpc43_receive(FAR struct lpc43_ethmac_s *priv); static void lpc43_freeframe(FAR struct lpc43_ethmac_s *priv); static void lpc43_txdone(FAR struct lpc43_ethmac_s *priv); -#ifdef CONFIG_NET_NOINTS + static void lpc43_interrupt_work(FAR void *arg); -#endif static int lpc43_interrupt(int irq, FAR void *context); /* Watchdog timer expirations */ -static inline void lpc43_txtimeout_process(FAR struct lpc43_ethmac_s *priv); -#ifdef CONFIG_NET_NOINTS static void lpc43_txtimeout_work(FAR void *arg); -#endif static void lpc43_txtimeout_expiry(int argc, uint32_t arg, ...); -static inline void lpc43_poll_process(FAR struct lpc43_ethmac_s *priv); -#ifdef CONFIG_NET_NOINTS static void lpc43_poll_work(FAR void *arg); -#endif static void lpc43_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ static int lpc43_ifup(struct net_driver_s *dev); static int lpc43_ifdown(struct net_driver_s *dev); -static inline void lpc43_txavail_process(FAR struct lpc43_ethmac_s *priv); -#ifdef CONFIG_NET_NOINTS + static void lpc43_txavail_work(FAR void *arg); -#endif static int lpc43_txavail(struct net_driver_s *dev); + #if defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_ICMPv6) static int lpc43_addmac(struct net_driver_s *dev, FAR const uint8_t *mac); #endif @@ -1900,29 +1885,32 @@ static void lpc43_txdone(FAR struct lpc43_ethmac_s *priv) } /**************************************************************************** - * Function: lpc43_interrupt_process + * Function: lpc43_interrupt_work * * Description: - * Interrupt processing. This may be performed either within the interrupt - * handler or on the worker thread, depending upon the configuration + * Perform interrupt related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void lpc43_interrupt_process(FAR struct lpc43_ethmac_s *priv) +static void lpc43_interrupt_work(FAR void *arg) { + FAR struct lpc43_ethmac_s *priv = (FAR struct lpc43_ethmac_s *)arg; uint32_t dmasr; + DEBUGASSERT(priv); + /* Get the DMA interrupt status bits (no MAC interrupts are expected) */ + net_lock(); dmasr = lpc43_getreg(LPC43_ETH_DMASTAT); /* Mask only enabled interrupts. This depends on the fact that the interrupt @@ -1974,7 +1962,6 @@ static inline void lpc43_interrupt_process(FAR struct lpc43_ethmac_s *priv) /* Handle error interrupt only if CONFIG_DEBUG_NET is eanbled */ #ifdef CONFIG_DEBUG_NET - /* Check if there are pending "abnormal" interrupts */ if ((dmasr & ETH_DMAINT_AIS) != 0) @@ -1991,45 +1978,13 @@ static inline void lpc43_interrupt_process(FAR struct lpc43_ethmac_s *priv) lpc43_putreg(ETH_DMAINT_AIS, LPC43_ETH_DMASTAT); } -#endif -} -/**************************************************************************** - * Function: lpc43_interrupt_work - * - * Description: - * Perform interrupt related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() was called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void lpc43_interrupt_work(FAR void *arg) -{ - FAR struct lpc43_ethmac_s *priv = (FAR struct lpc43_ethmac_s *)arg; - net_lock_t state; - - DEBUGASSERT(priv); - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - lpc43_interrupt_process(priv); - net_unlock(state); + net_unlock(); /* Re-enable Ethernet interrupts at the NVIC */ up_enable_irq(LPC43M4_IRQ_ETHERNET); } -#endif /**************************************************************************** * Function: lpc43_interrupt @@ -2051,8 +2006,6 @@ static void lpc43_interrupt_work(FAR void *arg) static int lpc43_interrupt(int irq, FAR void *context) { FAR struct lpc43_ethmac_s *priv = &g_lpc43ethmac; - -#ifdef CONFIG_NET_NOINTS uint32_t dmasr; /* Get the DMA interrupt status bits (no MAC interrupts are expected) */ @@ -2088,80 +2041,44 @@ static int lpc43_interrupt(int irq, FAR void *context) work_queue(ETHWORK, &priv->work, lpc43_interrupt_work, priv, 0); } -#else - /* Process the interrupt now */ - - lpc43_interrupt_process(priv); -#endif - return OK; } /**************************************************************************** - * Function: lpc43_txtimeout_process + * Function: lpc43_txtimeout_work * * Description: - * Process a TX timeout. Called from the either the watchdog timer - * expiration logic or from the worker thread, depending upon the - * configuration. The timeout means that the last TX never completed. - * Reset the hardware and start again. + * Perform TX timeout related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: - * Global interrupts are disabled by the watchdog logic. + * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void lpc43_txtimeout_process(FAR struct lpc43_ethmac_s *priv) +static void lpc43_txtimeout_work(FAR void *arg) { + FAR struct lpc43_ethmac_s *priv = (FAR struct lpc43_ethmac_s *)arg; + /* Then reset the hardware. Just take the interface down, then back * up again. */ + net_lock(); lpc43_ifdown(&priv->dev); lpc43_ifup(&priv->dev); /* Then poll the network for new XMIT data */ lpc43_dopoll(priv); + net_unlock(); } -/**************************************************************************** - * Function: lpc43_txtimeout_work - * - * Description: - * Perform TX timeout related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void lpc43_txtimeout_work(FAR void *arg) -{ - FAR struct lpc43_ethmac_s *priv = (FAR struct lpc43_ethmac_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - lpc43_txtimeout_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: lpc43_txtimeout_expiry * @@ -2187,7 +2104,6 @@ static void lpc43_txtimeout_expiry(int argc, uint32_t arg, ...) ninfo("Timeout!\n"); -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race * conditions with interrupt work. There is still a potential race * condition with interrupt work that is already queued and in progress. @@ -2206,33 +2122,28 @@ static void lpc43_txtimeout_expiry(int argc, uint32_t arg, ...) /* Schedule to perform the TX timeout processing on the worker thread. */ work_queue(ETHWORK, &priv->work, lpc43_txtimeout_work, priv, 0); - -#else - /* Process the timeout now */ - - lpc43_txtimeout_process(priv); -#endif } /**************************************************************************** - * Function: lpc43_poll_process + * Function: lpc43_poll_work * * Description: - * Perform the periodic poll. This may be called either from watchdog - * timer logic or from the worker thread, depending upon the configuration. + * Perform periodic polling from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: + * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void lpc43_poll_process(FAR struct lpc43_ethmac_s *priv) +static void lpc43_poll_work(FAR void *arg) { + FAR struct lpc43_ethmac_s *priv = (FAR struct lpc43_ethmac_s *)arg; FAR struct net_driver_s *dev = &priv->dev; /* Check if the next TX descriptor is owned by the Ethernet DMA or CPU. We @@ -2246,6 +2157,7 @@ static inline void lpc43_poll_process(FAR struct lpc43_ethmac_s *priv) * CONFIG_LPC43_ETH_NTXDESC). */ + net_lock(); if ((priv->txhead->tdes0 & ETH_TDES0_OWN) == 0 && priv->txhead->tdes2 == 0) { @@ -2281,39 +2193,9 @@ static inline void lpc43_poll_process(FAR struct lpc43_ethmac_s *priv) /* Setup the watchdog poll timer again */ (void)wd_start(priv->txpoll, LPC43_WDDELAY, lpc43_poll_expiry, 1, priv); + net_unlock(); } -/**************************************************************************** - * Function: lpc43_poll_work - * - * Description: - * Perform periodic polling from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void lpc43_poll_work(FAR void *arg) -{ - FAR struct lpc43_ethmac_s *priv = (FAR struct lpc43_ethmac_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - lpc43_poll_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: lpc43_poll_expiry * @@ -2336,7 +2218,6 @@ static void lpc43_poll_expiry(int argc, uint32_t arg, ...) { FAR struct lpc43_ethmac_s *priv = (FAR struct lpc43_ethmac_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions. */ @@ -2356,12 +2237,6 @@ static void lpc43_poll_expiry(int argc, uint32_t arg, ...) (void)wd_start(priv->txpoll, LPC43_WDDELAY, lpc43_poll_expiry, 1, (uint32_t)priv); } - -#else - /* Process the interrupt now */ - - lpc43_poll_process(priv); -#endif } /**************************************************************************** @@ -2468,66 +2343,39 @@ static int lpc43_ifdown(struct net_driver_s *dev) } /**************************************************************************** - * Function: lpc43_txavail_process + * Function: lpc43_txavail_work * * Description: - * Perform an out-of-cycle poll. + * Perform an out-of-cycle poll on the worker thread. * * Parameters: - * priv - Reference to the NuttX driver state structure + * arg - Reference to the NuttX driver state structure (cast to void*) * * Returned Value: * None * * Assumptions: - * Called in normal user mode + * Called on the higher priority worker thread. * ****************************************************************************/ -static inline void lpc43_txavail_process(FAR struct lpc43_ethmac_s *priv) +static void lpc43_txavail_work(FAR void *arg) { - ninfo("ifup: %d\n", priv->ifup); + FAR struct lpc43_ethmac_s *priv = (FAR struct lpc43_ethmac_s *)arg; /* Ignore the notification if the interface is not yet up */ + net_lock(); + ninfo("ifup: %d\n", priv->ifup); if (priv->ifup) { /* Poll for new XMIT data */ lpc43_dopoll(priv); } -} - -/**************************************************************************** - * Function: lpc43_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS -static void lpc43_txavail_work(FAR void *arg) -{ - FAR struct lpc43_ethmac_s *priv = (FAR struct lpc43_ethmac_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - lpc43_txavail_process(priv); - net_unlock(state); + net_unlock(); } -#endif /**************************************************************************** * Function: lpc43_txavail @@ -2552,7 +2400,6 @@ static int lpc43_txavail(struct net_driver_s *dev) { FAR struct lpc43_ethmac_s *priv = (FAR struct lpc43_ethmac_s *)dev->d_private; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions and we will have to ignore the Tx * availability action. @@ -2565,21 +2412,6 @@ static int lpc43_txavail(struct net_driver_s *dev) work_queue(ETHWORK, &priv->work, lpc43_txavail_work, priv, 0); } -#else - irqstate_t flags; - - /* Disable interrupts because this function may be called from interrupt - * level processing. - */ - - flags = enter_critical_section(); - - /* Perform the out-of-cycle poll now */ - - lpc43_txavail_process(priv); - leave_critical_section(flags); -#endif - return OK; } diff --git a/arch/arm/src/sam34/sam_emac.c b/arch/arm/src/sam34/sam_emac.c index 6f234cebcb..7ce3b0c316 100644 --- a/arch/arm/src/sam34/sam_emac.c +++ b/arch/arm/src/sam34/sam_emac.c @@ -64,11 +64,7 @@ #include #include #include - -#ifdef CONFIG_NET_NOINTS -# include -#endif - +#include #include #include #include @@ -101,13 +97,12 @@ * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +#if !defined(CONFIG_SCHED_WORKQUEUE) # error Work queue support is required -#endif +#else -/* Select work queue */ + /* Select work queue */ -#if defined(CONFIG_SCHED_WORKQUEUE) # if defined(CONFIG_SAM34_EMAC_HPWORK) # define ETHWORK HPWORK # elif defined(CONFIG_SAM34_EMAC_LPWORK) @@ -275,9 +270,7 @@ struct sam_emac_s uint8_t ifup : 1; /* true:ifup false:ifdown */ WDOG_ID txpoll; /* TX poll timer */ WDOG_ID txtimeout; /* TX timeout timer */ -#ifdef CONFIG_NET_NOINTS struct work_s work; /* For deferring work to the work queue */ -#endif /* This holds the information visible to the NuttX network */ @@ -386,24 +379,16 @@ static void sam_dopoll(struct sam_emac_s *priv); static int sam_recvframe(struct sam_emac_s *priv); static void sam_receive(struct sam_emac_s *priv); static void sam_txdone(struct sam_emac_s *priv); -static inline void sam_interrupt_process(FAR struct sam_emac_s *priv); -#ifdef CONFIG_NET_NOINTS + static void sam_interrupt_work(FAR void *arg); -#endif static int sam_emac_interrupt(int irq, void *context); /* Watchdog timer expirations */ -static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv); -#ifdef CONFIG_NET_NOINTS static void sam_txtimeout_work(FAR void *arg); -#endif static void sam_txtimeout_expiry(int argc, uint32_t arg, ...); -static inline void sam_poll_process(FAR struct sam_emac_s *priv); -#ifdef CONFIG_NET_NOINTS static void sam_poll_work(FAR void *arg); -#endif static void sam_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ @@ -411,10 +396,7 @@ static void sam_poll_expiry(int argc, uint32_t arg, ...); static int sam_ifup(struct net_driver_s *dev); static int sam_ifdown(struct net_driver_s *dev); -static inline void sam_txavail_process(FAR struct sam_emac_s *priv); -#ifdef CONFIG_NET_NOINTS static void sam_txavail_work(FAR void *arg); -#endif static int sam_txavail(struct net_driver_s *dev); #if defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_ICMPv6) @@ -465,6 +447,7 @@ static int sam_emac_configure(struct sam_emac_s *priv); /**************************************************************************** * Private Functions ****************************************************************************/ + /**************************************************************************** * Name: sam_checkreg * @@ -1421,25 +1404,25 @@ static void sam_txdone(struct sam_emac_s *priv) } /**************************************************************************** - * Function: sam_interrupt_process + * Function: sam_interrupt_work * * Description: - * Interrupt processing. This may be performed either within the interrupt - * handler or on the worker thread, depending upon the configuration + * Perform interrupt related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void sam_interrupt_process(FAR struct sam_emac_s *priv) +static void sam_interrupt_work(FAR void *arg) { + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; uint32_t isr; uint32_t rsr; uint32_t tsr; @@ -1448,6 +1431,9 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv) uint32_t pending; uint32_t clrbits; + /* Process pending Ethernet interrupts */ + + net_lock(); isr = sam_getreg(priv, SAM_EMAC_ISR); rsr = sam_getreg(priv, SAM_EMAC_RSR); tsr = sam_getreg(priv, SAM_EMAC_TSR); @@ -1603,42 +1589,13 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv) nwarn("WARNING: Pause TO!\n"); } #endif -} - -/**************************************************************************** - * Function: sam_interrupt_work - * - * Description: - * Perform interrupt related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() was called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS -static void sam_interrupt_work(FAR void *arg) -{ - FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - sam_interrupt_process(priv); - net_unlock(state); + net_unlock(); /* Re-enable Ethernet interrupts */ up_enable_irq(SAM_IRQ_EMAC); } -#endif /**************************************************************************** * Function: sam_emac_interrupt @@ -1661,7 +1618,6 @@ static int sam_emac_interrupt(int irq, void *context) { struct sam_emac_s *priv = &g_emac; -#ifdef CONFIG_NET_NOINTS uint32_t tsr; /* Disable further Ethernet interrupts. Because Ethernet interrupts are @@ -1705,83 +1661,46 @@ static int sam_emac_interrupt(int irq, void *context) /* Schedule to perform the interrupt processing on the worker thread. */ work_queue(ETHWORK, &priv->work, sam_interrupt_work, priv, 0); - -#else - /* Process the interrupt now */ - - sam_interrupt_process(priv); -#endif - return OK; } /**************************************************************************** - * Function: sam_txtimeout_process + * Function: sam_txtimeout_work * * Description: - * Process a TX timeout. Called from the either the watchdog timer - * expiration logic or from the worker thread, depending upon the - * configuration. The timeout means that the last TX never completed. - * Reset the hardware and start again. + * Perform TX timeout related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: - * Global interrupts are disabled by the watchdog logic. + * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv) +static void sam_txtimeout_work(FAR void *arg) { + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; + nerr("ERROR: Timeout!\n"); /* Then reset the hardware. Just take the interface down, then back * up again. */ + net_lock(); sam_ifdown(&priv->dev); sam_ifup(&priv->dev); /* Then poll the network for new XMIT data */ sam_dopoll(priv); + net_unlock(); } -/**************************************************************************** - * Function: sam_txtimeout_work - * - * Description: - * Perform TX timeout related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void sam_txtimeout_work(FAR void *arg) -{ - FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - sam_txtimeout_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: sam_txtimeout_expiry * @@ -1805,7 +1724,6 @@ static void sam_txtimeout_expiry(int argc, uint32_t arg, ...) { FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race * conditions with interrupt work. There is still a potential race * condition with interrupt work that is already queued and in progress. @@ -1822,38 +1740,35 @@ static void sam_txtimeout_expiry(int argc, uint32_t arg, ...) /* Schedule to perform the TX timeout processing on the worker thread. */ work_queue(ETHWORK, &priv->work, sam_txtimeout_work, priv, 0); -#else - /* Process the timeout now */ - - sam_txtimeout_process(priv); -#endif } /**************************************************************************** - * Function: sam_poll_process + * Function: sam_poll_work * * Description: - * Perform the periodic poll. This may be called either from watchdog - * timer logic or from the worker thread, depending upon the configuration. + * Perform periodic polling from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: + * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void sam_poll_process(FAR struct sam_emac_s *priv) +static void sam_poll_work(FAR void *arg) { + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; struct net_driver_s *dev = &priv->dev; /* Check if the there are any free TX descriptors. We cannot perform the * TX poll if we do not have buffering for another packet. */ + net_lock(); if (sam_txfree(priv) > 0) { /* Update TCP timing states and poll the network for new XMIT data. */ @@ -1864,39 +1779,9 @@ static inline void sam_poll_process(FAR struct sam_emac_s *priv) /* Setup the watchdog poll timer again */ (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, priv); + net_unlock(); } -/**************************************************************************** - * Function: sam_poll_work - * - * Description: - * Perform periodic polling from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void sam_poll_work(FAR void *arg) -{ - FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - sam_poll_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: sam_poll_expiry * @@ -1919,7 +1804,6 @@ static void sam_poll_expiry(int argc, uint32_t arg, ...) { FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions. */ @@ -1938,12 +1822,6 @@ static void sam_poll_expiry(int argc, uint32_t arg, ...) (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, arg); } - -#else - /* Process the interrupt now */ - - sam_poll_process(priv); -#endif } /**************************************************************************** @@ -2071,66 +1949,40 @@ static int sam_ifdown(struct net_driver_s *dev) } /**************************************************************************** - * Function: sam_txavail_process + * Function: sam_txavail_work * * Description: - * Perform an out-of-cycle poll. + * Perform an out-of-cycle poll on the worker thread. * * Parameters: - * dev - Reference to the NuttX driver state structure + * arg - Reference to the NuttX driver state structure (cast to void*) * * Returned Value: * None * * Assumptions: - * Called in normal user mode + * Called on the higher priority worker thread. * ****************************************************************************/ -static inline void sam_txavail_process(FAR struct sam_emac_s *priv) +static void sam_txavail_work(FAR void *arg) { + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; + ninfo("ifup: %d\n", priv->ifup); /* Ignore the notification if the interface is not yet up */ + net_lock(); if (priv->ifup) { /* Poll the network for new XMIT data */ sam_dopoll(priv); } -} -/**************************************************************************** - * Function: sam_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void sam_txavail_work(FAR void *arg) -{ - FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - sam_txavail_process(priv); - net_unlock(state); + net_unlock(); } -#endif /**************************************************************************** * Function: sam_txavail @@ -2155,7 +2007,6 @@ static int sam_txavail(struct net_driver_s *dev) { FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)dev->d_private; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions and we will have to ignore the Tx * availability action. @@ -2168,21 +2019,6 @@ static int sam_txavail(struct net_driver_s *dev) work_queue(ETHWORK, &priv->work, sam_txavail_work, priv, 0); } -#else - irqstate_t flags; - - /* Disable interrupts because this function may be called from interrupt - * level processing. - */ - - flags = enter_critical_section(); - - /* Perform the out-of-cycle poll now */ - - sam_txavail_process(priv); - leave_critical_section(flags); -#endif - return OK; } diff --git a/arch/arm/src/sama5/sam_emaca.c b/arch/arm/src/sama5/sam_emaca.c index c31ae128f8..29bd28c5a7 100644 --- a/arch/arm/src/sama5/sam_emaca.c +++ b/arch/arm/src/sama5/sam_emaca.c @@ -65,11 +65,7 @@ #include #include #include - -#ifdef CONFIG_NET_NOINTS -# include -#endif - +#include #include #include #include @@ -103,13 +99,12 @@ * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +#if !defined(CONFIG_SCHED_WORKQUEUE) # error Work queue support is required -#endif +#else -/* Select work queue */ + /* Select work queue */ -#if defined(CONFIG_SCHED_WORKQUEUE) # if defined(CONFIG_SAMA5_EMACA_HPWORK) # define ETHWORK HPWORK # elif defined(CONFIG_SAMA5_EMACA_LPWORK) @@ -280,9 +275,7 @@ struct sam_emac_s uint8_t ifup : 1; /* true:ifup false:ifdown */ WDOG_ID txpoll; /* TX poll timer */ WDOG_ID txtimeout; /* TX timeout timer */ -#ifdef CONFIG_NET_NOINTS struct work_s work; /* For deferring work to the work queue */ -#endif /* This holds the information visible to the NuttX network */ @@ -391,24 +384,16 @@ static void sam_dopoll(struct sam_emac_s *priv); static int sam_recvframe(struct sam_emac_s *priv); static void sam_receive(struct sam_emac_s *priv); static void sam_txdone(struct sam_emac_s *priv); -static inline void sam_interrupt_process(FAR struct sam_emac_s *priv); -#ifdef CONFIG_NET_NOINTS + static void sam_interrupt_work(FAR void *arg); -#endif static int sam_emac_interrupt(int irq, void *context); /* Watchdog timer expirations */ -static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv); -#ifdef CONFIG_NET_NOINTS static void sam_txtimeout_work(FAR void *arg); -#endif static void sam_txtimeout_expiry(int argc, uint32_t arg, ...); -static inline void sam_poll_process(FAR struct sam_emac_s *priv); -#ifdef CONFIG_NET_NOINTS static void sam_poll_work(FAR void *arg); -#endif static void sam_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ @@ -416,10 +401,7 @@ static void sam_poll_expiry(int argc, uint32_t arg, ...); static int sam_ifup(struct net_driver_s *dev); static int sam_ifdown(struct net_driver_s *dev); -static inline void sam_txavail_process(FAR struct sam_emac_s *priv); -#ifdef CONFIG_NET_NOINTS static void sam_txavail_work(FAR void *arg); -#endif static int sam_txavail(struct net_driver_s *dev); #if defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_ICMPv6) @@ -1462,25 +1444,25 @@ static void sam_txdone(struct sam_emac_s *priv) } /**************************************************************************** - * Function: sam_interrupt_process + * Function: sam_interrupt_work * * Description: - * Interrupt processing. This may be performed either within the interrupt - * handler or on the worker thread, depending upon the configuration + * Perform interrupt related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void sam_interrupt_process(FAR struct sam_emac_s *priv) +static void sam_interrupt_work(FAR void *arg) { + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; uint32_t isr; uint32_t rsr; uint32_t tsr; @@ -1489,6 +1471,9 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv) uint32_t pending; uint32_t clrbits; + /* Process pending Ethernet interrupts */ + + net_lock(); isr = sam_getreg(priv, SAM_EMAC_ISR); rsr = sam_getreg(priv, SAM_EMAC_RSR); tsr = sam_getreg(priv, SAM_EMAC_TSR); @@ -1643,42 +1628,13 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv) nwarn("WARNING: Pause TO!\n"); } #endif -} -/**************************************************************************** - * Function: sam_interrupt_work - * - * Description: - * Perform interrupt related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() was called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void sam_interrupt_work(FAR void *arg) -{ - FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - sam_interrupt_process(priv); - net_unlock(state); + net_unlock(); /* Re-enable Ethernet interrupts */ up_enable_irq(SAM_IRQ_EMAC); } -#endif /**************************************************************************** * Function: sam_emac_interrupt @@ -1700,7 +1656,6 @@ static void sam_interrupt_work(FAR void *arg) static int sam_emac_interrupt(int irq, void *context) { struct sam_emac_s *priv = &g_emac; -#ifdef CONFIG_NET_NOINTS uint32_t tsr; /* Disable further Ethernet interrupts. Because Ethernet interrupts are @@ -1744,81 +1699,44 @@ static int sam_emac_interrupt(int irq, void *context) /* Schedule to perform the interrupt processing on the worker thread. */ work_queue(ETHWORK, &priv->work, sam_interrupt_work, priv, 0); - -#else - /* Process the interrupt now */ - - sam_interrupt_process(priv); -#endif - return OK; } /**************************************************************************** - * Function: sam_txtimeout_process + * Function: sam_txtimeout_work * * Description: - * Process a TX timeout. Called from the either the watchdog timer - * expiration logic or from the worker thread, depending upon the - * configuration. The timeout means that the last TX never completed. - * Reset the hardware and start again. + * Perform TX timeout related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: - * Global interrupts are disabled by the watchdog logic. + * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv) +static void sam_txtimeout_work(FAR void *arg) { + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; + nerr("ERROR: Timeout!\n"); /* Reset the hardware. Just take the interface down, then back up again. */ + net_lock(); sam_ifdown(&priv->dev); sam_ifup(&priv->dev); /* Then poll the network for new XMIT data */ sam_dopoll(priv); + net_unlock(); } -/**************************************************************************** - * Function: sam_txtimeout_work - * - * Description: - * Perform TX timeout related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void sam_txtimeout_work(FAR void *arg) -{ - FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - sam_txtimeout_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: sam_txtimeout_expiry * @@ -1842,7 +1760,6 @@ static void sam_txtimeout_expiry(int argc, uint32_t arg, ...) { FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race * conditions with interrupt work. There is still a potential race * condition with interrupt work that is already queued and in progress. @@ -1859,38 +1776,35 @@ static void sam_txtimeout_expiry(int argc, uint32_t arg, ...) /* Schedule to perform the TX timeout processing on the worker thread. */ work_queue(ETHWORK, &priv->work, sam_txtimeout_work, priv, 0); -#else - /* Process the timeout now */ - - sam_txtimeout_process(priv); -#endif } /**************************************************************************** - * Function: sam_poll_process + * Function: sam_poll_work * * Description: - * Perform the periodic poll. This may be called either from watchdog - * timer logic or from the worker thread, depending upon the configuration. + * Perform periodic polling from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: + * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void sam_poll_process(FAR struct sam_emac_s *priv) +static void sam_poll_work(FAR void *arg) { + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; struct net_driver_s *dev = &priv->dev; /* Check if the there are any free TX descriptors. We cannot perform the * TX poll if we do not have buffering for another packet. */ + net_lock(); if (sam_txfree(priv) > 0) { /* Update TCP timing states and poll the network for new XMIT data. */ @@ -1901,39 +1815,9 @@ static inline void sam_poll_process(FAR struct sam_emac_s *priv) /* Setup the watchdog poll timer again */ (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, priv); + net_unlock(); } -/**************************************************************************** - * Function: sam_poll_work - * - * Description: - * Perform periodic polling from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void sam_poll_work(FAR void *arg) -{ - FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - sam_poll_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: sam_poll_expiry * @@ -1956,7 +1840,6 @@ static void sam_poll_expiry(int argc, uint32_t arg, ...) { FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions. */ @@ -1975,12 +1858,6 @@ static void sam_poll_expiry(int argc, uint32_t arg, ...) (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, arg); } - -#else - /* Process the interrupt now */ - - sam_poll_process(priv); -#endif } /**************************************************************************** @@ -2108,66 +1985,40 @@ static int sam_ifdown(struct net_driver_s *dev) } /**************************************************************************** - * Function: sam_txavail_process + * Function: sam_txavail_work * * Description: - * Perform an out-of-cycle poll. + * Perform an out-of-cycle poll on the worker thread. * * Parameters: - * dev - Reference to the NuttX driver state structure + * arg - Reference to the NuttX driver state structure (cast to void*) * * Returned Value: * None * * Assumptions: - * Called in normal user mode + * Called on the higher priority worker thread. * ****************************************************************************/ -static inline void sam_txavail_process(FAR struct sam_emac_s *priv) +static void sam_txavail_work(FAR void *arg) { + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; + ninfo("ifup: %d\n", priv->ifup); /* Ignore the notification if the interface is not yet up */ + net_lock(); if (priv->ifup) { /* Poll the network for new XMIT data */ sam_dopoll(priv); } -} -/**************************************************************************** - * Function: sam_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void sam_txavail_work(FAR void *arg) -{ - FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - sam_txavail_process(priv); - net_unlock(state); + net_unlock(); } -#endif /**************************************************************************** * Function: sam_txavail @@ -2192,7 +2043,6 @@ static int sam_txavail(struct net_driver_s *dev) { FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)dev->d_private; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions and we will have to ignore the Tx * availability action. @@ -2205,21 +2055,6 @@ static int sam_txavail(struct net_driver_s *dev) work_queue(ETHWORK, &priv->work, sam_txavail_work, priv, 0); } -#else - irqstate_t flags; - - /* Disable interrupts because this function may be called from interrupt - * level processing. - */ - - flags = enter_critical_section(); - - /* Perform the out-of-cycle poll now */ - - sam_txavail_process(priv); - leave_critical_section(flags); -#endif - return OK; } diff --git a/arch/arm/src/sama5/sam_emacb.c b/arch/arm/src/sama5/sam_emacb.c index 6eb3dd2108..44b477cb7b 100644 --- a/arch/arm/src/sama5/sam_emacb.c +++ b/arch/arm/src/sama5/sam_emacb.c @@ -79,11 +79,7 @@ #include #include #include - -#ifdef CONFIG_NET_NOINTS -# include -#endif - +#include #include #include #include @@ -117,13 +113,12 @@ * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +#if !defined(CONFIG_SCHED_WORKQUEUE) # error Work queue support is required -#endif +#else -/* Select work queue */ + /* Select work queue */ -#if defined(CONFIG_SCHED_WORKQUEUE) # if defined(CONFIG_SAMA5_EMACB_HPWORK) # define ETHWORK HPWORK # elif defined(CONFIG_SAMA5_EMACB_LPWORK) @@ -418,9 +413,7 @@ struct sam_emac_s uint8_t ifup : 1; /* true:ifup false:ifdown */ WDOG_ID txpoll; /* TX poll timer */ WDOG_ID txtimeout; /* TX timeout timer */ -#ifdef CONFIG_NET_NOINTS struct work_s work; /* For deferring work to the work queue */ -#endif /* This holds the information visible to the NuttX network */ @@ -486,10 +479,8 @@ static void sam_dopoll(struct sam_emac_s *priv); static int sam_recvframe(struct sam_emac_s *priv); static void sam_receive(struct sam_emac_s *priv); static void sam_txdone(struct sam_emac_s *priv); -static inline void sam_interrupt_process(FAR struct sam_emac_s *priv); -#ifdef CONFIG_NET_NOINTS + static void sam_interrupt_work(FAR void *arg); -#endif static int sam_emac_interrupt(struct sam_emac_s *priv); #ifdef CONFIG_SAMA5_EMAC0 static int sam_emac0_interrupt(int irq, void *context); @@ -500,16 +491,10 @@ static int sam_emac1_interrupt(int irq, void *context); /* Watchdog timer expirations */ -static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv); -#ifdef CONFIG_NET_NOINTS static void sam_txtimeout_work(FAR void *arg); -#endif static void sam_txtimeout_expiry(int argc, uint32_t arg, ...); -static inline void sam_poll_process(FAR struct sam_emac_s *priv); -#ifdef CONFIG_NET_NOINTS static void sam_poll_work(FAR void *arg); -#endif static void sam_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ @@ -517,10 +502,7 @@ static void sam_poll_expiry(int argc, uint32_t arg, ...); static int sam_ifup(struct net_driver_s *dev); static int sam_ifdown(struct net_driver_s *dev); -static inline void sam_txavail_process(FAR struct sam_emac_s *priv); -#ifdef CONFIG_NET_NOINTS static void sam_txavail_work(FAR void *arg); -#endif static int sam_txavail(struct net_driver_s *dev); #if defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_ICMPv6) @@ -1830,25 +1812,25 @@ static void sam_txdone(struct sam_emac_s *priv) } /**************************************************************************** - * Function: sam_interrupt_process + * Function: sam_interrupt_work * * Description: - * Interrupt processing. This may be performed either within the interrupt - * handler or on the worker thread, depending upon the configuration + * Perform interrupt related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void sam_interrupt_process(FAR struct sam_emac_s *priv) +static void sam_interrupt_work(FAR void *arg) { + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; uint32_t isr; uint32_t rsr; uint32_t tsr; @@ -1857,6 +1839,9 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv) uint32_t pending; uint32_t clrbits; + /* Process pending Ethernet interrupts */ + + net_lock(); isr = sam_getreg(priv, SAM_EMAC_ISR_OFFSET); rsr = sam_getreg(priv, SAM_EMAC_RSR_OFFSET); tsr = sam_getreg(priv, SAM_EMAC_TSR_OFFSET); @@ -2012,42 +1997,13 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv) nwarn("WARNING: Pause TO!\n"); } #endif -} -/**************************************************************************** - * Function: sam_interrupt_work - * - * Description: - * Perform interrupt related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() was called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void sam_interrupt_work(FAR void *arg) -{ - FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - sam_interrupt_process(priv); - net_unlock(state); + net_unlock(); /* Re-enable Ethernet interrupts */ up_enable_irq(priv->attr->irq); } -#endif /**************************************************************************** * Function: sam_emac_interrupt @@ -2067,7 +2023,6 @@ static void sam_interrupt_work(FAR void *arg) static int sam_emac_interrupt(struct sam_emac_s *priv) { -#ifdef CONFIG_NET_NOINTS uint32_t tsr; /* Disable further Ethernet interrupts. Because Ethernet interrupts are @@ -2111,13 +2066,6 @@ static int sam_emac_interrupt(struct sam_emac_s *priv) /* Schedule to perform the interrupt processing on the worker thread. */ work_queue(ETHWORK, &priv->work, sam_interrupt_work, priv, 0); - -#else - /* Process the interrupt now */ - - sam_interrupt_process(priv); -#endif - return OK; } @@ -2153,70 +2101,40 @@ static int sam_emac1_interrupt(int irq, void *context) #endif /**************************************************************************** - * Function: sam_txtimeout_process + * Function: sam_txtimeout_work * * Description: - * Process a TX timeout. Called from the either the watchdog timer - * expiration logic or from the worker thread, depending upon the - * configuration. The timeout means that the last TX never completed. - * Reset the hardware and start again. + * Perform TX timeout related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: - * Global interrupts are disabled by the watchdog logic. + * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv) +static void sam_txtimeout_work(FAR void *arg) { + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; + nerr("ERROR: Timeout!\n"); /* Reset the hardware. Just take the interface down, then back up again. */ + net_lock(); sam_ifdown(&priv->dev); sam_ifup(&priv->dev); /* Then poll the network for new XMIT data */ sam_dopoll(priv); + net_unlock(); } -/**************************************************************************** - * Function: sam_txtimeout_work - * - * Description: - * Perform TX timeout related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void sam_txtimeout_work(FAR void *arg) -{ - FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - sam_txtimeout_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: sam_txtimeout_expiry * @@ -2240,7 +2158,6 @@ static void sam_txtimeout_expiry(int argc, uint32_t arg, ...) { FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race * conditions with interrupt work. There is still a potential race * condition with interrupt work that is already queued and in progress. @@ -2257,38 +2174,35 @@ static void sam_txtimeout_expiry(int argc, uint32_t arg, ...) /* Schedule to perform the TX timeout processing on the worker thread. */ work_queue(ETHWORK, &priv->work, sam_txtimeout_work, priv, 0); -#else - /* Process the timeout now */ - - sam_txtimeout_process(priv); -#endif } /**************************************************************************** - * Function: sam_poll_process + * Function: sam_poll_work * * Description: - * Perform the periodic poll. This may be called either from watchdog - * timer logic or from the worker thread, depending upon the configuration. + * Perform periodic polling from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: + * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void sam_poll_process(FAR struct sam_emac_s *priv) +static void sam_poll_work(FAR void *arg) { + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; struct net_driver_s *dev = &priv->dev; /* Check if the there are any free TX descriptors. We cannot perform the * TX poll if we do not have buffering for another packet. */ + net_lock(); if (sam_txfree(priv) > 0) { /* Update TCP timing states and poll the network for new XMIT data. */ @@ -2299,39 +2213,9 @@ static inline void sam_poll_process(FAR struct sam_emac_s *priv) /* Setup the watchdog poll timer again */ (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, priv); + net_unlock(); } -/**************************************************************************** - * Function: sam_poll_work - * - * Description: - * Perform periodic polling from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void sam_poll_work(FAR void *arg) -{ - FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - sam_poll_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: sam_poll_expiry * @@ -2354,7 +2238,6 @@ static void sam_poll_expiry(int argc, uint32_t arg, ...) { FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions. */ @@ -2373,12 +2256,6 @@ static void sam_poll_expiry(int argc, uint32_t arg, ...) (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, arg); } - -#else - /* Process the interrupt now */ - - sam_poll_process(priv); -#endif } /**************************************************************************** @@ -2514,66 +2391,40 @@ static int sam_ifdown(struct net_driver_s *dev) } /**************************************************************************** - * Function: sam_txavail_process + * Function: sam_txavail_work * * Description: - * Perform an out-of-cycle poll. + * Perform an out-of-cycle poll on the worker thread. * * Parameters: - * dev - Reference to the NuttX driver state structure + * arg - Reference to the NuttX driver state structure (cast to void*) * * Returned Value: * None * * Assumptions: - * Called in normal user mode + * Called on the higher priority worker thread. * ****************************************************************************/ -static inline void sam_txavail_process(FAR struct sam_emac_s *priv) +static void sam_txavail_work(FAR void *arg) { + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; + ninfo("ifup: %d\n", priv->ifup); /* Ignore the notification if the interface is not yet up */ + net_lock(); if (priv->ifup) { /* Poll the network for new XMIT data */ sam_dopoll(priv); } -} -/**************************************************************************** - * Function: sam_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void sam_txavail_work(FAR void *arg) -{ - FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - sam_txavail_process(priv); - net_unlock(state); + net_unlock(); } -#endif /**************************************************************************** * Function: sam_txavail @@ -2598,7 +2449,6 @@ static int sam_txavail(struct net_driver_s *dev) { FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)dev->d_private; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions and we will have to ignore the Tx * availability action. @@ -2611,21 +2461,6 @@ static int sam_txavail(struct net_driver_s *dev) work_queue(ETHWORK, &priv->work, sam_txavail_work, priv, 0); } -#else - irqstate_t flags; - - /* Disable interrupts because this function may be called from interrupt - * level processing. - */ - - flags = enter_critical_section(); - - /* Perform the out-of-cycle poll now */ - - sam_txavail_process(priv); - leave_critical_section(flags); -#endif - return OK; } diff --git a/arch/arm/src/sama5/sam_gmac.c b/arch/arm/src/sama5/sam_gmac.c index d3450dc2be..da6b320d52 100644 --- a/arch/arm/src/sama5/sam_gmac.c +++ b/arch/arm/src/sama5/sam_gmac.c @@ -62,11 +62,7 @@ #include #include #include - -#ifdef CONFIG_NET_NOINTS -# include -#endif - +#include #include #include #include @@ -100,13 +96,12 @@ * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +#if !defined(CONFIG_SCHED_WORKQUEUE) # error Work queue support is required -#endif +#else -/* Select work queue */ + /* Select work queue */ -#if defined(CONFIG_SCHED_WORKQUEUE) # if defined(CONFIG_SAMA5_GMAC_HPWORK) # define ETHWORK HPWORK # elif defined(CONFIG_SAMA5_GMAC_LPWORK) @@ -206,9 +201,7 @@ struct sam_gmac_s uint8_t ifup : 1; /* true:ifup false:ifdown */ WDOG_ID txpoll; /* TX poll timer */ WDOG_ID txtimeout; /* TX timeout timer */ -#ifdef CONFIG_NET_NOINTS struct work_s work; /* For deferring work to the work queue */ -#endif /* This holds the information visible to the NuttX network */ @@ -316,24 +309,16 @@ static void sam_dopoll(struct sam_gmac_s *priv); static int sam_recvframe(struct sam_gmac_s *priv); static void sam_receive(struct sam_gmac_s *priv); static void sam_txdone(struct sam_gmac_s *priv); -static inline void sam_interrupt_process(FAR struct sam_gmac_s *priv); -#ifdef CONFIG_NET_NOINTS + static void sam_interrupt_work(FAR void *arg); -#endif static int sam_gmac_interrupt(int irq, void *context); /* Watchdog timer expirations */ -static inline void sam_txtimeout_process(FAR struct sam_gmac_s *priv); -#ifdef CONFIG_NET_NOINTS static void sam_txtimeout_work(FAR void *arg); -#endif static void sam_txtimeout_expiry(int argc, uint32_t arg, ...); -static inline void sam_poll_process(FAR struct sam_gmac_s *priv); -#ifdef CONFIG_NET_NOINTS static void sam_poll_work(FAR void *arg); -#endif static void sam_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ @@ -341,10 +326,7 @@ static void sam_poll_expiry(int argc, uint32_t arg, ...); static int sam_ifup(struct net_driver_s *dev); static int sam_ifdown(struct net_driver_s *dev); -static inline void sam_txavail_process(FAR struct sam_gmac_s *priv); -#ifdef CONFIG_NET_NOINTS static void sam_txavail_work(FAR void *arg); -#endif static int sam_txavail(struct net_driver_s *dev); #if defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_ICMPv6) @@ -1390,25 +1372,25 @@ static void sam_txdone(struct sam_gmac_s *priv) } /**************************************************************************** - * Function: sam_interrupt_process + * Function: sam_interrupt_work * * Description: - * Interrupt processing. This may be performed either within the interrupt - * handler or on the worker thread, depending upon the configuration + * Perform interrupt related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void sam_interrupt_process(FAR struct sam_gmac_s *priv) +static void sam_interrupt_work(FAR void *arg) { + FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg; uint32_t isr; uint32_t rsr; uint32_t tsr; @@ -1417,6 +1399,9 @@ static inline void sam_interrupt_process(FAR struct sam_gmac_s *priv) uint32_t pending; uint32_t clrbits; + /* Process pending Ethernet interrupts */ + + net_lock(); isr = sam_getreg(priv, SAM_GMAC_ISR); rsr = sam_getreg(priv, SAM_GMAC_RSR); tsr = sam_getreg(priv, SAM_GMAC_TSR); @@ -1595,42 +1580,13 @@ static inline void sam_interrupt_process(FAR struct sam_gmac_s *priv) nwarn("WARNING: Pause TO!\n"); } #endif -} -/**************************************************************************** - * Function: sam_interrupt_work - * - * Description: - * Perform interrupt related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() was called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void sam_interrupt_work(FAR void *arg) -{ - FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - sam_interrupt_process(priv); - net_unlock(state); + net_unlock(); /* Re-enable Ethernet interrupts */ up_enable_irq(SAM_IRQ_GMAC); } -#endif /**************************************************************************** * Function: sam_gmac_interrupt @@ -1652,7 +1608,6 @@ static void sam_interrupt_work(FAR void *arg) static int sam_gmac_interrupt(int irq, void *context) { struct sam_gmac_s *priv = &g_gmac; -#ifdef CONFIG_NET_NOINTS uint32_t tsr; /* Disable further Ethernet interrupts. Because Ethernet interrupts are @@ -1696,81 +1651,44 @@ static int sam_gmac_interrupt(int irq, void *context) /* Schedule to perform the interrupt processing on the worker thread. */ work_queue(ETHWORK, &priv->work, sam_interrupt_work, priv, 0); - -#else - /* Process the interrupt now */ - - sam_interrupt_process(priv); -#endif - return OK; } /**************************************************************************** - * Function: sam_txtimeout_process + * Function: sam_txtimeout_work * * Description: - * Process a TX timeout. Called from the either the watchdog timer - * expiration logic or from the worker thread, depending upon the - * configuration. The timeout means that the last TX never completed. - * Reset the hardware and start again. + * Perform TX timeout related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: - * Global interrupts are disabled by the watchdog logic. + * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void sam_txtimeout_process(FAR struct sam_gmac_s *priv) +static void sam_txtimeout_work(FAR void *arg) { + FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg; + nerr("ERROR: Timeout!\n"); /* Reset the hardware. Just take the interface down, then back up again. */ + net_lock(); sam_ifdown(&priv->dev); sam_ifup(&priv->dev); /* Then poll the network for new XMIT data */ sam_dopoll(priv); + net_unlock(); } -/**************************************************************************** - * Function: sam_txtimeout_work - * - * Description: - * Perform TX timeout related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void sam_txtimeout_work(FAR void *arg) -{ - FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - sam_txtimeout_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: sam_txtimeout_expiry * @@ -1794,7 +1712,6 @@ static void sam_txtimeout_expiry(int argc, uint32_t arg, ...) { FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race * conditions with interrupt work. There is still a potential race * condition with interrupt work that is already queued and in progress. @@ -1811,38 +1728,35 @@ static void sam_txtimeout_expiry(int argc, uint32_t arg, ...) /* Schedule to perform the TX timeout processing on the worker thread. */ work_queue(ETHWORK, &priv->work, sam_txtimeout_work, priv, 0); -#else - /* Process the timeout now */ - - sam_txtimeout_process(priv); -#endif } /**************************************************************************** - * Function: sam_poll_process + * Function: sam_poll_work * * Description: - * Perform the periodic poll. This may be called either from watchdog - * timer logic or from the worker thread, depending upon the configuration. + * Perform periodic polling from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: + * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void sam_poll_process(FAR struct sam_gmac_s *priv) +static void sam_poll_work(FAR void *arg) { + FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg; struct net_driver_s *dev = &priv->dev; /* Check if the there are any free TX descriptors. We cannot perform the * TX poll if we do not have buffering for another packet. */ + net_lock(); if (sam_txfree(priv) > 0) { /* Update TCP timing states and poll the network for new XMIT data. */ @@ -1853,39 +1767,9 @@ static inline void sam_poll_process(FAR struct sam_gmac_s *priv) /* Setup the watchdog poll timer again */ (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, priv); + net_unlock(); } -/**************************************************************************** - * Function: sam_poll_work - * - * Description: - * Perform periodic polling from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void sam_poll_work(FAR void *arg) -{ - FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - sam_poll_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: sam_poll_expiry * @@ -1908,7 +1792,6 @@ static void sam_poll_expiry(int argc, uint32_t arg, ...) { FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions. */ @@ -1927,12 +1810,6 @@ static void sam_poll_expiry(int argc, uint32_t arg, ...) (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, arg); } - -#else - /* Process the interrupt now */ - - sam_poll_process(priv); -#endif } /**************************************************************************** @@ -2063,66 +1940,40 @@ static int sam_ifdown(struct net_driver_s *dev) } /**************************************************************************** - * Function: sam_txavail_process + * Function: sam_txavail_work * * Description: - * Perform an out-of-cycle poll. + * Perform an out-of-cycle poll on the worker thread. * * Parameters: - * dev - Reference to the NuttX driver state structure + * arg - Reference to the NuttX driver state structure (cast to void*) * * Returned Value: * None * * Assumptions: - * Called in normal user mode + * Called on the higher priority worker thread. * ****************************************************************************/ -static inline void sam_txavail_process(FAR struct sam_gmac_s *priv) +static void sam_txavail_work(FAR void *arg) { + FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg; + ninfo("ifup: %d\n", priv->ifup); /* Ignore the notification if the interface is not yet up */ + net_lock(); if (priv->ifup) { /* Poll the network for new XMIT data */ sam_dopoll(priv); } -} -/**************************************************************************** - * Function: sam_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void sam_txavail_work(FAR void *arg) -{ - FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - sam_txavail_process(priv); - net_unlock(state); + net_unlock(); } -#endif /**************************************************************************** * Function: sam_txavail @@ -2147,7 +1998,6 @@ static int sam_txavail(struct net_driver_s *dev) { FAR struct sam_gmac_s *priv = (FAR struct sam_gmac_s *)dev->d_private; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions and we will have to ignore the Tx * availability action. @@ -2160,21 +2010,6 @@ static int sam_txavail(struct net_driver_s *dev) work_queue(ETHWORK, &priv->work, sam_txavail_work, priv, 0); } -#else - irqstate_t flags; - - /* Disable interrupts because this function may be called from interrupt - * level processing. - */ - - flags = enter_critical_section(); - - /* Perform the out-of-cycle poll now */ - - sam_txavail_process(priv); - leave_critical_section(flags); -#endif - return OK; } diff --git a/arch/arm/src/samv7/sam_emac.c b/arch/arm/src/samv7/sam_emac.c index 8c9c9e0827..271ab994be 100644 --- a/arch/arm/src/samv7/sam_emac.c +++ b/arch/arm/src/samv7/sam_emac.c @@ -69,11 +69,7 @@ #include #include #include - -#ifdef CONFIG_NET_NOINTS -# include -#endif - +#include #include #include #include @@ -107,13 +103,12 @@ * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +#if !defined(CONFIG_SCHED_WORKQUEUE) # error Work queue support is required -#endif +#else -/* Select work queue */ + /* Select work queue */ -#if defined(CONFIG_SCHED_WORKQUEUE) # if defined(CONFIG_SAMV7_EMAC_HPWORK) # define ETHWORK HPWORK # elif defined(CONFIG_SAMV7_EMAC_LPWORK) @@ -523,9 +518,7 @@ struct sam_emac_s uint8_t ifup : 1; /* true:ifup false:ifdown */ WDOG_ID txpoll; /* TX poll timer */ WDOG_ID txtimeout; /* TX timeout timer */ -#ifdef CONFIG_NET_NOINTS struct work_s work; /* For deferring work to the work queue */ -#endif /* This holds the information visible to the NuttX network */ @@ -588,11 +581,8 @@ static int sam_recvframe(struct sam_emac_s *priv, int qid); static void sam_receive(struct sam_emac_s *priv, int qid); static void sam_txdone(struct sam_emac_s *priv, int qid); static void sam_txerr_interrupt(FAR struct sam_emac_s *priv, int qid); -static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, - int qid); -#ifdef CONFIG_NET_NOINTS + static void sam_interrupt_work(FAR void *arg); -#endif static int sam_emac_interrupt(struct sam_emac_s *priv); #ifdef CONFIG_SAMV7_EMAC0 static int sam_emac0_interrupt(int irq, void *context); @@ -603,16 +593,10 @@ static int sam_emac1_interrupt(int irq, void *context); /* Watchdog timer expirations */ -static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv); -#ifdef CONFIG_NET_NOINTS static void sam_txtimeout_work(FAR void *arg); -#endif static void sam_txtimeout_expiry(int argc, uint32_t arg, ...); -static inline void sam_poll_process(FAR struct sam_emac_s *priv); -#ifdef CONFIG_NET_NOINTS static void sam_poll_work(FAR void *arg); -#endif static void sam_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ @@ -620,10 +604,7 @@ static void sam_poll_expiry(int argc, uint32_t arg, ...); static int sam_ifup(struct net_driver_s *dev); static int sam_ifdown(struct net_driver_s *dev); -static inline void sam_txavail_process(FAR struct sam_emac_s *priv); -#ifdef CONFIG_NET_NOINTS static void sam_txavail_work(FAR void *arg); -#endif static int sam_txavail(struct net_driver_s *dev); #if defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_ICMPv6) @@ -2272,26 +2253,25 @@ static void sam_txerr_interrupt(FAR struct sam_emac_s *priv, int qid) } /**************************************************************************** - * Function: sam_interrupt_process + * Function: sam_interrupt_work * * Description: - * Interrupt processing. This may be performed either within the interrupt - * handler or on the worker thread, depending upon the configuration + * Perform interrupt related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure - * quid - Index of the transfer queue that generated the interrupt + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid) +static void sam_interrupt_work(FAR void *arg) { + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; uint32_t isr; uint32_t rsr; uint32_t tsr; @@ -2300,6 +2280,10 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid) uint32_t pending; uint32_t clrbits; + /* Process pending Ethernet interrupts */ + + net_lock(); + /* Read the interrupt status, RX status, and TX status registers. * NOTE that the interrupt status register is cleared by this read. */ @@ -2458,42 +2442,13 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid) ninfo("Pause TO!\n"); } #endif -} - -/**************************************************************************** - * Function: sam_interrupt_work - * - * Description: - * Perform interrupt related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() was called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void sam_interrupt_work(FAR void *arg) -{ - FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - state = net_lock(); - sam_interrupt_process(priv, EMAC_QUEUE_0); - net_unlock(state); + net_unlock(); /* Re-enable Ethernet interrupts */ up_enable_irq(priv->attr->irq); } -#endif /**************************************************************************** * Function: sam_emac_interrupt @@ -2513,7 +2468,6 @@ static void sam_interrupt_work(FAR void *arg) static int sam_emac_interrupt(struct sam_emac_s *priv) { -#ifdef CONFIG_NET_NOINTS uint32_t tsr; /* Disable further Ethernet interrupts. Because Ethernet interrupts are @@ -2557,13 +2511,6 @@ static int sam_emac_interrupt(struct sam_emac_s *priv) /* Schedule to perform the interrupt processing on the worker thread. */ work_queue(ETHWORK, &priv->work, sam_interrupt_work, priv, 0); - -#else - /* Process the interrupt now */ - - sam_interrupt_process(priv, EMAC_QUEUE_0); -#endif - return OK; } @@ -2599,28 +2546,29 @@ static int sam_emac1_interrupt(int irq, void *context) #endif /**************************************************************************** - * Function: sam_txtimeout_process + * Function: sam_txtimeout_work * * Description: - * Process a TX timeout. Called from the either the watchdog timer - * expiration logic or from the worker thread, depending upon the - * configuration. The timeout means that the last TX never completed. - * Reset the hardware and start again. + * Perform TX timeout related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: - * Global interrupts are disabled by the watchdog logic. + * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv) +static void sam_txtimeout_work(FAR void *arg) { + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; + nerr("ERROR: Timeout!\n"); + + net_lock(); NETDEV_TXTIMEOUTS(&priv->dev); /* Reset the hardware. Just take the interface down, then back up again. */ @@ -2631,39 +2579,9 @@ static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv) /* Then poll the network for new XMIT data */ sam_dopoll(priv, EMAC_QUEUE_0); + net_unlock(); } -/**************************************************************************** - * Function: sam_txtimeout_work - * - * Description: - * Perform TX timeout related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void sam_txtimeout_work(FAR void *arg) -{ - FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - sam_txtimeout_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: sam_txtimeout_expiry * @@ -2687,7 +2605,6 @@ static void sam_txtimeout_expiry(int argc, uint32_t arg, ...) { FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race * conditions with interrupt work. There is still a potential race * condition with interrupt work that is already queued and in progress. @@ -2704,38 +2621,35 @@ static void sam_txtimeout_expiry(int argc, uint32_t arg, ...) /* Schedule to perform the TX timeout processing on the worker thread. */ work_queue(ETHWORK, &priv->work, sam_txtimeout_work, priv, 0); -#else - /* Process the timeout now */ - - sam_txtimeout_process(priv); -#endif } /**************************************************************************** - * Function: sam_poll_process + * Function: sam_poll_work * * Description: - * Perform the periodic poll. This may be called either from watchdog - * timer logic or from the worker thread, depending upon the configuration. + * Perform periodic polling from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: + * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void sam_poll_process(FAR struct sam_emac_s *priv) +static void sam_poll_work(FAR void *arg) { + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; struct net_driver_s *dev = &priv->dev; /* Check if the there are any free TX descriptors. We cannot perform the * TX poll if we do not have buffering for another packet. */ + net_lock(); if (sam_txfree(priv, EMAC_QUEUE_0) > 0) { /* Update TCP timing states and poll the network for new XMIT data. */ @@ -2746,39 +2660,9 @@ static inline void sam_poll_process(FAR struct sam_emac_s *priv) /* Setup the watchdog poll timer again */ (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, priv); + net_unlock(); } -/**************************************************************************** - * Function: sam_poll_work - * - * Description: - * Perform periodic polling from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void sam_poll_work(FAR void *arg) -{ - FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - sam_poll_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: sam_poll_expiry * @@ -2801,7 +2685,6 @@ static void sam_poll_expiry(int argc, uint32_t arg, ...) { FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions. */ @@ -2820,12 +2703,6 @@ static void sam_poll_expiry(int argc, uint32_t arg, ...) (void)wd_start(priv->txpoll, SAM_WDDELAY, sam_poll_expiry, 1, arg); } - -#else - /* Process the interrupt now */ - - sam_poll_process(priv); -#endif } /**************************************************************************** @@ -2964,66 +2841,40 @@ static int sam_ifdown(struct net_driver_s *dev) } /**************************************************************************** - * Function: sam_txavail_process + * Function: sam_txavail_work * * Description: - * Perform an out-of-cycle poll. + * Perform an out-of-cycle poll on the worker thread. * * Parameters: - * dev - Reference to the NuttX driver state structure + * arg - Reference to the NuttX driver state structure (cast to void*) * * Returned Value: * None * * Assumptions: - * Called in normal user mode + * Called on the higher priority worker thread. * ****************************************************************************/ -static inline void sam_txavail_process(FAR struct sam_emac_s *priv) +static void sam_txavail_work(FAR void *arg) { + FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; + ninfo("ifup: %d\n", priv->ifup); /* Ignore the notification if the interface is not yet up */ + net_lock(); if (priv->ifup) { /* Poll the network for new XMIT data */ sam_dopoll(priv, EMAC_QUEUE_0); } -} - -/**************************************************************************** - * Function: sam_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS -static void sam_txavail_work(FAR void *arg) -{ - FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - sam_txavail_process(priv); - net_unlock(state); + net_unlock(); } -#endif /**************************************************************************** * Function: sam_txavail @@ -3048,7 +2899,6 @@ static int sam_txavail(struct net_driver_s *dev) { FAR struct sam_emac_s *priv = (FAR struct sam_emac_s *)dev->d_private; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions and we will have to ignore the Tx * availability action. @@ -3061,21 +2911,6 @@ static int sam_txavail(struct net_driver_s *dev) work_queue(ETHWORK, &priv->work, sam_txavail_work, priv, 0); } -#else - irqstate_t flags; - - /* Disable interrupts because this function may be called from interrupt - * level processing. - */ - - flags = enter_critical_section(); - - /* Perform the out-of-cycle poll now */ - - sam_txavail_process(priv); - leave_critical_section(flags); -#endif - return OK; } diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/stm32/stm32_eth.c index 8bb121237a..52dcaacd72 100644 --- a/arch/arm/src/stm32/stm32_eth.c +++ b/arch/arm/src/stm32/stm32_eth.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/stm32/stm32_eth.c * - * Copyright (C) 2011-2012, 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2012, 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -53,14 +53,11 @@ #include #include #include - -#ifdef CONFIG_NET_NOINTS -# include -#endif - +#include #include #include #include + #if defined(CONFIG_NET_PKT) # include #endif @@ -97,13 +94,12 @@ * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +#if !defined(CONFIG_SCHED_WORKQUEUE) # error Work queue support is required -#endif +#else -/* Select work queue */ + /* Select work queue */ -#if defined(CONFIG_SCHED_WORKQUEUE) # if defined(CONFIG_STM32_ETHMAC_HPWORK) # define ETHWORK HPWORK # elif defined(CONFIG_STM32_ETHMAC_LPWORK) @@ -587,9 +583,7 @@ struct stm32_ethmac_s uint8_t fduplex : 1; /* Full (vs. half) duplex */ WDOG_ID txpoll; /* TX poll timer */ WDOG_ID txtimeout; /* TX timeout timer */ -#ifdef CONFIG_NET_NOINTS struct work_s work; /* For deferring work to the work queue */ -#endif /* This holds the information visible to the NuttX network */ @@ -662,34 +656,26 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv); static void stm32_receive(FAR struct stm32_ethmac_s *priv); static void stm32_freeframe(FAR struct stm32_ethmac_s *priv); static void stm32_txdone(FAR struct stm32_ethmac_s *priv); -#ifdef CONFIG_NET_NOINTS + static void stm32_interrupt_work(FAR void *arg); -#endif static int stm32_interrupt(int irq, FAR void *context); /* Watchdog timer expirations */ -static inline void stm32_txtimeout_process(FAR struct stm32_ethmac_s *priv); -#ifdef CONFIG_NET_NOINTS static void stm32_txtimeout_work(FAR void *arg); -#endif static void stm32_txtimeout_expiry(int argc, uint32_t arg, ...); -static inline void stm32_poll_process(FAR struct stm32_ethmac_s *priv); -#ifdef CONFIG_NET_NOINTS static void stm32_poll_work(FAR void *arg); -#endif static void stm32_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ static int stm32_ifup(struct net_driver_s *dev); static int stm32_ifdown(struct net_driver_s *dev); -static inline void stm32_txavail_process(FAR struct stm32_ethmac_s *priv); -#ifdef CONFIG_NET_NOINTS + static void stm32_txavail_work(FAR void *arg); -#endif static int stm32_txavail(struct net_driver_s *dev); + #if defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_ICMPv6) static int stm32_addmac(struct net_driver_s *dev, FAR const uint8_t *mac); #endif @@ -1964,27 +1950,33 @@ static void stm32_txdone(FAR struct stm32_ethmac_s *priv) } /**************************************************************************** - * Function: stm32_interrupt_process + * Function: stm32_interrupt_work * * Description: - * Interrupt processing. This may be performed either within the interrupt - * handler or on the worker thread, depending upon the configuration + * Perform interrupt related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void stm32_interrupt_process(FAR struct stm32_ethmac_s *priv) +static void stm32_interrupt_work(FAR void *arg) { + FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)arg; uint32_t dmasr; + DEBUGASSERT(priv); + + /* Process pending Ethernet interrupts */ + + net_lock(); + /* Get the DMA interrupt status bits (no MAC interrupts are expected) */ dmasr = stm32_getreg(STM32_ETH_DMASR); @@ -2056,44 +2048,13 @@ static inline void stm32_interrupt_process(FAR struct stm32_ethmac_s *priv) stm32_putreg(ETH_DMAINT_AIS, STM32_ETH_DMASR); } #endif -} -/**************************************************************************** - * Function: stm32_interrupt_work - * - * Description: - * Perform interrupt related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() was called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void stm32_interrupt_work(FAR void *arg) -{ - FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)arg; - net_lock_t state; - - DEBUGASSERT(priv); - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - stm32_interrupt_process(priv); - net_unlock(state); + net_unlock(); /* Re-enable Ethernet interrupts at the NVIC */ up_enable_irq(STM32_IRQ_ETH); } -#endif /**************************************************************************** * Function: stm32_interrupt @@ -2115,8 +2076,6 @@ static void stm32_interrupt_work(FAR void *arg) static int stm32_interrupt(int irq, FAR void *context) { FAR struct stm32_ethmac_s *priv = &g_stm32ethmac[0]; - -#ifdef CONFIG_NET_NOINTS uint32_t dmasr; /* Get the DMA interrupt status bits (no MAC interrupts are expected) */ @@ -2152,49 +2111,9 @@ static int stm32_interrupt(int irq, FAR void *context) work_queue(ETHWORK, &priv->work, stm32_interrupt_work, priv, 0); } -#else - /* Process the interrupt now */ - - stm32_interrupt_process(priv); -#endif - return OK; } -/**************************************************************************** - * Function: stm32_txtimeout_process - * - * Description: - * Process a TX timeout. Called from the either the watchdog timer - * expiration logic or from the worker thread, depending upon the - * configuration. The timeout means that the last TX never completed. - * Reset the hardware and start again. - * - * Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * Global interrupts are disabled by the watchdog logic. - * - ****************************************************************************/ - -static inline void stm32_txtimeout_process(FAR struct stm32_ethmac_s *priv) -{ - /* Then reset the hardware. Just take the interface down, then back - * up again. - */ - - stm32_ifdown(&priv->dev); - stm32_ifup(&priv->dev); - - /* Then poll for new XMIT data */ - - stm32_dopoll(priv); -} - /**************************************************************************** * Function: stm32_txtimeout_work * @@ -2212,19 +2131,21 @@ static inline void stm32_txtimeout_process(FAR struct stm32_ethmac_s *priv) * ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS static void stm32_txtimeout_work(FAR void *arg) { FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)arg; - net_lock_t state; - /* Process pending Ethernet interrupts */ + /* Reset the hardware. Just take the interface down, then back up again. */ + + net_lock(); + stm32_ifdown(&priv->dev); + stm32_ifup(&priv->dev); - state = net_lock(); - stm32_txtimeout_process(priv); - net_unlock(state); + /* Then poll for new XMIT data */ + + stm32_dopoll(priv); + net_unlock(); } -#endif /**************************************************************************** * Function: stm32_txtimeout_expiry @@ -2251,7 +2172,6 @@ static void stm32_txtimeout_expiry(int argc, uint32_t arg, ...) nerr("ERROR: Timeout!\n"); -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race * conditions with interrupt work. There is still a potential race * condition with interrupt work that is already queued and in progress. @@ -2270,33 +2190,28 @@ static void stm32_txtimeout_expiry(int argc, uint32_t arg, ...) /* Schedule to perform the TX timeout processing on the worker thread. */ work_queue(ETHWORK, &priv->work, stm32_txtimeout_work, priv, 0); - -#else - /* Process the timeout now */ - - stm32_txtimeout_process(priv); -#endif } /**************************************************************************** - * Function: stm32_poll_process + * Function: stm32_poll_work * * Description: - * Perform the periodic poll. This may be called either from watchdog - * timer logic or from the worker thread, depending upon the configuration. + * Perform periodic polling from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: + * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void stm32_poll_process(FAR struct stm32_ethmac_s *priv) +static void stm32_poll_work(FAR void *arg) { + FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)arg; FAR struct net_driver_s *dev = &priv->dev; /* Check if the next TX descriptor is owned by the Ethernet DMA or CPU. We @@ -2310,6 +2225,7 @@ static inline void stm32_poll_process(FAR struct stm32_ethmac_s *priv) * CONFIG_STM32_ETH_NTXDESC). */ + net_lock(); if ((priv->txhead->tdes0 & ETH_TDES0_OWN) == 0 && priv->txhead->tdes2 == 0) { @@ -2345,39 +2261,9 @@ static inline void stm32_poll_process(FAR struct stm32_ethmac_s *priv) /* Setup the watchdog poll timer again */ (void)wd_start(priv->txpoll, STM32_WDDELAY, stm32_poll_expiry, 1, priv); + net_unlock(); } -/**************************************************************************** - * Function: stm32_poll_work - * - * Description: - * Perform periodic polling from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void stm32_poll_work(FAR void *arg) -{ - FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - stm32_poll_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: stm32_poll_expiry * @@ -2400,7 +2286,6 @@ static void stm32_poll_expiry(int argc, uint32_t arg, ...) { FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions. */ @@ -2419,12 +2304,6 @@ static void stm32_poll_expiry(int argc, uint32_t arg, ...) (void)wd_start(priv->txpoll, STM32_WDDELAY, stm32_poll_expiry, 1, (uint32_t)priv); } - -#else - /* Process the interrupt now */ - - stm32_poll_process(priv); -#endif } /**************************************************************************** @@ -2530,66 +2409,40 @@ static int stm32_ifdown(struct net_driver_s *dev) } /**************************************************************************** - * Function: stm32_txavail_process + * Function: stm32_txavail_work * * Description: - * Perform an out-of-cycle poll. + * Perform an out-of-cycle poll on the worker thread. * * Parameters: - * priv - Reference to the NuttX driver state structure + * arg - Reference to the NuttX driver state structure (cast to void*) * * Returned Value: * None * * Assumptions: - * Called in normal user mode + * Called on the higher priority worker thread. * ****************************************************************************/ -static inline void stm32_txavail_process(FAR struct stm32_ethmac_s *priv) +static void stm32_txavail_work(FAR void *arg) { + FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)arg; + ninfo("ifup: %d\n", priv->ifup); /* Ignore the notification if the interface is not yet up */ + net_lock(); if (priv->ifup) { /* Poll the network for new XMIT data */ stm32_dopoll(priv); } -} - -/**************************************************************************** - * Function: stm32_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS -static void stm32_txavail_work(FAR void *arg) -{ - FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - stm32_txavail_process(priv); - net_unlock(state); + net_unlock(); } -#endif /**************************************************************************** * Function: stm32_txavail @@ -2614,7 +2467,6 @@ static int stm32_txavail(struct net_driver_s *dev) { FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)dev->d_private; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions and we will have to ignore the Tx * availability action. @@ -2627,21 +2479,6 @@ static int stm32_txavail(struct net_driver_s *dev) work_queue(ETHWORK, &priv->work, stm32_txavail_work, priv, 0); } -#else - irqstate_t flags; - - /* Disable interrupts because this function may be called from interrupt - * level processing. - */ - - flags = enter_critical_section(); - - /* Perform the out-of-cycle poll now */ - - stm32_txavail_process(priv); - leave_critical_section(flags); -#endif - return OK; } diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c index 8301f80e5b..b84e8511ac 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.c +++ b/arch/arm/src/stm32f7/stm32_ethernet.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/stm32f7/stm32_ethernet.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -52,14 +52,11 @@ #include #include #include - -#ifdef CONFIG_NET_NOINTS -# include -#endif - +#include #include #include #include + #if defined(CONFIG_NET_PKT) # include #endif @@ -98,13 +95,12 @@ * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +#if !defined(CONFIG_SCHED_WORKQUEUE) # error Work queue support is required -#endif +#else -/* Select work queue */ + /* Select work queue */ -#if defined(CONFIG_SCHED_WORKQUEUE) # if defined(CONFIG_STM32F7_ETHMAC_HPWORK) # define ETHWORK HPWORK # elif defined(CONFIG_STM32F7_ETHMAC_LPWORK) @@ -611,9 +607,7 @@ struct stm32_ethmac_s uint8_t intf; /* Ethernet interface number */ WDOG_ID txpoll; /* TX poll timer */ WDOG_ID txtimeout; /* TX timeout timer */ -#ifdef CONFIG_NET_NOINTS struct work_s work; /* For deferring work to the work queue */ -#endif /* This holds the information visible to the NuttX network */ @@ -705,35 +699,26 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv); static void stm32_receive(struct stm32_ethmac_s *priv); static void stm32_freeframe(struct stm32_ethmac_s *priv); static void stm32_txdone(struct stm32_ethmac_s *priv); -#ifdef CONFIG_NET_NOINTS + static void stm32_interrupt_work(void *arg); -#endif static int stm32_interrupt(int irq, void *context); /* Watchdog timer expirations */ -static inline void stm32_txtimeout_process(struct stm32_ethmac_s *priv); -#ifdef CONFIG_NET_NOINTS static void stm32_txtimeout_work(void *arg); -#endif static void stm32_txtimeout_expiry(int argc, uint32_t arg, ...); -static inline void stm32_poll_process(struct stm32_ethmac_s *priv); -#ifdef CONFIG_NET_NOINTS static void stm32_poll_work(void *arg); -#endif static void stm32_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ static int stm32_ifup(struct net_driver_s *dev); static int stm32_ifdown(struct net_driver_s *dev); -static int stm32_ifdown(struct net_driver_s *dev); -static inline void stm32_txavail_process(struct stm32_ethmac_s *priv); -#ifdef CONFIG_NET_NOINTS + static void stm32_txavail_work(void *arg); -#endif static int stm32_txavail(struct net_driver_s *dev); + #if defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_ICMPv6) static int stm32_addmac(struct net_driver_s *dev, const uint8_t *mac); #endif @@ -2078,27 +2063,33 @@ static void stm32_txdone(struct stm32_ethmac_s *priv) } /**************************************************************************** - * Function: stm32_interrupt_process + * Function: stm32_interrupt_work * * Description: - * Interrupt processing. This may be performed either within the interrupt - * handler or on the worker thread, depending upon the configuration + * Perform interrupt related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void stm32_interrupt_process(struct stm32_ethmac_s *priv) +static void stm32_interrupt_work(void *arg) { + struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg; uint32_t dmasr; + DEBUGASSERT(priv); + + /* Process pending Ethernet interrupts */ + + net_lock(); + /* Get the DMA interrupt status bits (no MAC interrupts are expected) */ dmasr = stm32_getreg(STM32_ETH_DMASR); @@ -2169,44 +2160,13 @@ static inline void stm32_interrupt_process(struct stm32_ethmac_s *priv) stm32_putreg(ETH_DMAINT_AIS, STM32_ETH_DMASR); } #endif -} - -/**************************************************************************** - * Function: stm32_interrupt_work - * - * Description: - * Perform interrupt related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() was called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void stm32_interrupt_work(void *arg) -{ - struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg; - net_lock_t state; - - DEBUGASSERT(priv); - - /* Process pending Ethernet interrupts */ - state = net_lock(); - stm32_interrupt_process(priv); - net_unlock(state); + net_unlock(); /* Re-enable Ethernet interrupts at the NVIC */ up_enable_irq(STM32_IRQ_ETH); } -#endif /**************************************************************************** * Function: stm32_interrupt @@ -2228,8 +2188,6 @@ static void stm32_interrupt_work(void *arg) static int stm32_interrupt(int irq, void *context) { struct stm32_ethmac_s *priv = &g_stm32ethmac[0]; - -#ifdef CONFIG_NET_NOINTS uint32_t dmasr; /* Get the DMA interrupt status bits (no MAC interrupts are expected) */ @@ -2265,49 +2223,9 @@ static int stm32_interrupt(int irq, void *context) work_queue(ETHWORK, &priv->work, stm32_interrupt_work, priv, 0); } -#else - /* Process the interrupt now */ - - stm32_interrupt_process(priv); -#endif - return OK; } -/**************************************************************************** - * Function: stm32_txtimeout_process - * - * Description: - * Process a TX timeout. Called from the either the watchdog timer - * expiration logic or from the worker thread, depending upon the - * configuration. The timeout means that the last TX never completed. - * Reset the hardware and start again. - * - * Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * Global interrupts are disabled by the watchdog logic. - * - ****************************************************************************/ - -static inline void stm32_txtimeout_process(struct stm32_ethmac_s *priv) -{ - /* Then reset the hardware. Just take the interface down, then back - * up again. - */ - - stm32_ifdown(&priv->dev); - stm32_ifup(&priv->dev); - - /* Then poll for new XMIT data */ - - stm32_dopoll(priv); -} - /**************************************************************************** * Function: stm32_txtimeout_work * @@ -2325,19 +2243,21 @@ static inline void stm32_txtimeout_process(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS static void stm32_txtimeout_work(void *arg) { struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg; - net_lock_t state; - /* Process pending Ethernet interrupts */ + /* Reset the hardware. Just take the interface down, then back up again. */ + + net_lock(); + stm32_ifdown(&priv->dev); + stm32_ifup(&priv->dev); - state = net_lock(); - stm32_txtimeout_process(priv); - net_unlock(state); + /* Then poll for new XMIT data */ + + stm32_dopoll(priv); + net_unlock(); } -#endif /**************************************************************************** * Function: stm32_txtimeout_expiry @@ -2364,7 +2284,6 @@ static void stm32_txtimeout_expiry(int argc, uint32_t arg, ...) nerr("ERROR: Timeout!\n"); -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race * conditions with interrupt work. There is still a potential race * condition with interrupt work that is already queued and in progress. @@ -2383,33 +2302,28 @@ static void stm32_txtimeout_expiry(int argc, uint32_t arg, ...) /* Schedule to perform the TX timeout processing on the worker thread. */ work_queue(ETHWORK, &priv->work, stm32_txtimeout_work, priv, 0); - -#else - /* Process the timeout now */ - - stm32_txtimeout_process(priv); -#endif } /**************************************************************************** - * Function: stm32_poll_process + * Function: stm32_poll_work * * Description: - * Perform the periodic poll. This may be called either from watchdog - * timer logic or from the worker thread, depending upon the configuration. + * Perform periodic polling from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: + * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void stm32_poll_process(struct stm32_ethmac_s *priv) +static void stm32_poll_work(void *arg) { + struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg; struct net_driver_s *dev = &priv->dev; /* Check if the next TX descriptor is owned by the Ethernet DMA or CPU. We @@ -2423,6 +2337,7 @@ static inline void stm32_poll_process(struct stm32_ethmac_s *priv) * CONFIG_STM32F7_ETH_NTXDESC). */ + net_lock(); if ((priv->txhead->tdes0 & ETH_TDES0_OWN) == 0 && priv->txhead->tdes2 == 0) { @@ -2458,39 +2373,9 @@ static inline void stm32_poll_process(struct stm32_ethmac_s *priv) /* Setup the watchdog poll timer again */ (void)wd_start(priv->txpoll, STM32_WDDELAY, stm32_poll_expiry, 1, priv); + net_unlock(); } -/**************************************************************************** - * Function: stm32_poll_work - * - * Description: - * Perform periodic polling from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void stm32_poll_work(void *arg) -{ - struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - stm32_poll_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: stm32_poll_expiry * @@ -2513,7 +2398,6 @@ static void stm32_poll_expiry(int argc, uint32_t arg, ...) { struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions. */ @@ -2532,12 +2416,6 @@ static void stm32_poll_expiry(int argc, uint32_t arg, ...) (void)wd_start(priv->txpoll, STM32_WDDELAY, stm32_poll_expiry, 1, (uint32_t)priv); } - -#else - /* Process the interrupt now */ - - stm32_poll_process(priv); -#endif } /**************************************************************************** @@ -2643,28 +2521,31 @@ static int stm32_ifdown(struct net_driver_s *dev) } /**************************************************************************** - * Function: stm32_txavail_process + * Function: stm32_txavail_work * * Description: - * Perform an out-of-cycle poll. + * Perform an out-of-cycle poll on the worker thread. * * Parameters: - * priv - Reference to the NuttX driver state structure + * arg - Reference to the NuttX driver state structure (cast to void*) * * Returned Value: * None * * Assumptions: - * Called in normal user mode + * Called on the higher priority worker thread. * ****************************************************************************/ -static inline void stm32_txavail_process(struct stm32_ethmac_s *priv) +static void stm32_txavail_work(void *arg) { + struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg; + ninfo("ifup: %d\n", priv->ifup); /* Ignore the notification if the interface is not yet up */ + net_lock(); if (priv->ifup) { /* Poll the network for new XMIT data */ @@ -2672,39 +2553,9 @@ static inline void stm32_txavail_process(struct stm32_ethmac_s *priv) stm32_dopoll(priv); } + net_unlock(); } -/**************************************************************************** - * Function: stm32_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void stm32_txavail_work(void *arg) -{ - struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - stm32_txavail_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: stm32_txavail * @@ -2728,7 +2579,6 @@ static int stm32_txavail(struct net_driver_s *dev) { struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)dev->d_private; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions and we will have to ignore the Tx * availability action. @@ -2741,21 +2591,6 @@ static int stm32_txavail(struct net_driver_s *dev) work_queue(ETHWORK, &priv->work, stm32_txavail_work, priv, 0); } -#else - irqstate_t flags; - - /* Disable interrupts because this function may be called from interrupt - * level processing. - */ - - flags = enter_critical_section(); - - /* Perform the out-of-cycle poll now */ - - stm32_txavail_process(priv); - leave_critical_section(flags); -#endif - return OK; } diff --git a/arch/arm/src/tiva/lm3s_ethernet.c b/arch/arm/src/tiva/lm3s_ethernet.c index 306276f17e..b7fd2189c5 100644 --- a/arch/arm/src/tiva/lm3s_ethernet.c +++ b/arch/arm/src/tiva/lm3s_ethernet.c @@ -52,10 +52,7 @@ #include #include #include - -#ifdef CONFIG_NET_NOINTS -# include -#endif +#include #include #include @@ -80,13 +77,12 @@ * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +#if !defined(CONFIG_SCHED_WORKQUEUE) # error Work queue support is required in this configuration (CONFIG_SCHED_WORKQUEUE) -#endif +#else -/* Use the low priority work queue if possible */ + /* Use the low priority work queue if possible */ -#if defined(CONFIG_SCHED_WORKQUEUE) # if defined(CONFIG_TIVA_ETHERNET_HPWORK) # define ETHWORK HPWORK # elif defined(CONFIG_TIVA_ETHERNET_LPWORK) @@ -206,9 +202,7 @@ struct tiva_driver_s bool ld_bifup; /* true:ifup false:ifdown */ WDOG_ID ld_txpoll; /* TX poll timer */ WDOG_ID ld_txtimeout; /* TX timeout timer */ -#ifdef CONFIG_NET_NOINTS struct work_s ld_work; /* For deferring work to the work queue */ -#endif /* This holds the information visible to the NuttX network */ @@ -256,24 +250,15 @@ static int tiva_txpoll(struct net_driver_s *dev); static void tiva_receive(struct tiva_driver_s *priv); static void tiva_txdone(struct tiva_driver_s *priv); -static inline void tiva_interrupt_process(struct tiva_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void tiva_interrupt_work(void *arg); -#endif static int tiva_interrupt(int irq, void *context); /* Watchdog timer expirations */ -static inline void tiva_txtimeout_process(struct tiva_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void tiva_txtimeout_work(void *arg); -#endif static void tiva_txtimeout_expiry(int argc, uint32_t arg, ...); -static inline void tiva_poll_process(struct tiva_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void tiva_poll_work(void *arg); -#endif static void tiva_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ @@ -281,11 +266,7 @@ static void tiva_poll_expiry(int argc, uint32_t arg, ...); static int tiva_ifup(struct net_driver_s *dev); static int tiva_ifdown(struct net_driver_s *dev); - -static inline void tiva_txavail_process(struct tiva_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void tiva_txavail_work(void *arg); -#endif static int tiva_txavail(struct net_driver_s *dev); #ifdef CONFIG_NET_IGMP @@ -963,27 +944,31 @@ static void tiva_txdone(struct tiva_driver_s *priv) } /**************************************************************************** - * Function: tiva_interrupt_process + * Function: tiva_interrupt_work * * Description: - * Interrupt processing. This may be performed either within the interrupt - * handler or on the worker thread, depending upon the configuration + * Perform interrupt related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: * The network is locked. * ****************************************************************************/ -static inline void tiva_interrupt_process(struct tiva_driver_s *priv) +static void tiva_interrupt_work(void *arg) { + struct tiva_driver_s *priv = (struct tiva_driver_s *)arg; uint32_t ris; + /* Process pending Ethernet interrupts */ + + net_lock(); + /* Read the raw interrupt status register */ ris = tiva_ethin(priv, TIVA_MAC_RIS_OFFSET); @@ -1038,36 +1023,8 @@ static inline void tiva_interrupt_process(struct tiva_driver_s *priv) tiva_txdone(priv); } -} - -/**************************************************************************** - * Function: tiva_interrupt_work - * - * Description: - * Perform interrupt related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() was called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void tiva_interrupt_work(void *arg) -{ - struct tiva_driver_s *priv = (struct tiva_driver_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - state = net_lock(); - tiva_interrupt_process(priv); - net_unlock(state); + net_unlock(); /* Re-enable Ethernet interrupts */ @@ -1077,7 +1034,6 @@ static void tiva_interrupt_work(void *arg) up_disable_irq(TIVA_IRQ_ETHCON); #endif } -#endif /**************************************************************************** * Function: tiva_interrupt @@ -1107,7 +1063,6 @@ static int tiva_interrupt(int irq, void *context) priv = &g_lm3sdev[0]; #endif -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. Because Ethernet interrupts are * also disabled if the TX timeout event occurs, there can be no race * condition here. @@ -1145,37 +1100,33 @@ static int tiva_interrupt(int irq, void *context) /* Schedule to perform the interrupt processing on the worker thread. */ work_queue(ETHWORK, &priv->ld_work, tiva_interrupt_work, priv, 0); - -#else - /* Process the interrupt now */ - - tiva_interrupt_process(priv); -#endif - return OK; } /**************************************************************************** - * Function: tiva_txtimeout_process + * Function: tiva_txtimeout_work * * Description: - * Process a TX timeout. Called from the either the watchdog timer - * expiration logic or from the worker thread, depending upon the - * configuration. The timeout means that the last TX never completed. - * Reset the hardware and start again. + * Perform TX timeout related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success + * + * Assumptions: + * The network is locked. * ****************************************************************************/ -static inline void tiva_txtimeout_process(struct tiva_driver_s *priv) +static void tiva_txtimeout_work(void *arg) { + struct tiva_driver_s *priv = (struct tiva_driver_s *)arg; + /* Increment statistics */ + net_lock(); nerr("ERROR: Tx timeout\n"); NETDEV_TXTIMEOUTS(&priv->ld_dev); @@ -1188,39 +1139,9 @@ static inline void tiva_txtimeout_process(struct tiva_driver_s *priv) /* Then poll the network for new XMIT data */ (void)devif_poll(&priv->ld_dev, tiva_txpoll); + net_unlock(); } -/**************************************************************************** - * Function: tiva_txtimeout_work - * - * Description: - * Perform TX timeout related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void tiva_txtimeout_work(void *arg) -{ - struct tiva_driver_s *priv = (struct tiva_driver_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - tiva_txtimeout_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: tiva_txtimeout_expiry * @@ -1244,7 +1165,6 @@ static void tiva_txtimeout_expiry(int argc, wdparm_t arg, ...) { struct tiva_driver_s *priv = (struct tiva_driver_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race * conditions with interrupt work. There is still a potential race * condition with interrupt work that is already queued and in progress. @@ -1265,32 +1185,29 @@ static void tiva_txtimeout_expiry(int argc, wdparm_t arg, ...) /* Schedule to perform the TX timeout processing on the worker thread. */ work_queue(ETHWORK, &priv->ld_work, tiva_txtimeout_work, priv, 0); -#else - /* Process the timeout now */ - - tiva_txtimeout_process(priv); -#endif } /**************************************************************************** - * Function: tiva_poll_process + * Function: tiva_poll_work * * Description: - * Perform the periodic poll. This may be called either from watchdog - * timer logic or from the worker thread, depending upon the configuration. + * Perform periodic polling from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: + * The network is locked. * ****************************************************************************/ -static inline void tiva_poll_process(struct tiva_driver_s *priv) +static void tiva_poll_work(void *arg) { + struct tiva_driver_s *priv = (struct tiva_driver_s *)arg; + /* Check if we can send another Tx packet now. The NEWTX bit initiates an * Ethernet transmission once the packet has been placed in the TX FIFO. * This bit is cleared once the transmission has been completed. @@ -1299,6 +1216,7 @@ static inline void tiva_poll_process(struct tiva_driver_s *priv) * inaccuracies. */ + net_lock(); if ((tiva_ethin(priv, TIVA_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) { /* If so, update TCP timing states and poll the network for new XMIT @@ -1312,38 +1230,9 @@ static inline void tiva_poll_process(struct tiva_driver_s *priv) (void)wd_start(priv->ld_txpoll, TIVA_WDDELAY, tiva_poll_expiry, 1, priv); } -} -/**************************************************************************** - * Function: tiva_poll_work - * - * Description: - * Perform periodic polling from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void tiva_poll_work(void *arg) -{ - struct tiva_driver_s *priv = (struct tiva_driver_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - tiva_poll_process(priv); - net_unlock(state); + net_unlock(); } -#endif /**************************************************************************** * Function: tiva_poll_expiry @@ -1367,7 +1256,6 @@ static void tiva_poll_expiry(int argc, wdparm_t arg, ...) { struct tiva_driver_s *priv = (struct tiva_driver_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions. */ @@ -1386,12 +1274,6 @@ static void tiva_poll_expiry(int argc, wdparm_t arg, ...) (void)wd_start(priv->ld_txpoll, TIVA_WDDELAY, tiva_poll_expiry, 1, arg); } - -#else - /* Process the interrupt now */ - - tiva_poll_process(priv); -#endif } /**************************************************************************** @@ -1634,24 +1516,26 @@ static int tiva_ifdown(struct net_driver_s *dev) } /**************************************************************************** - * Function: tiva_txavail_process + * Function: tiva_txavail_work * * Description: - * Perform an out-of-cycle poll. + * Perform an out-of-cycle poll on the worker thread. * * Parameters: - * dev - Reference to the NuttX driver state structure + * arg - Reference to the NuttX driver state structure (cast to void*) * * Returned Value: * None * * Assumptions: - * Called in normal user mode + * Called on the higher priority worker thread. * ****************************************************************************/ -static inline void tiva_txavail_process(struct tiva_driver_s *priv) +static void tiva_txavail_work(void *arg) { + struct tiva_driver_s *priv = (struct tiva_driver_s *)arg; + /* Ignore the notification if the interface is not yet up or if the Tx FIFO * hardware is not available at this time. The NEWTX bit initiates an * Ethernet transmission once the packet has been placed in the TX FIFO. @@ -1660,6 +1544,7 @@ static inline void tiva_txavail_process(struct tiva_driver_s *priv) * will occur at that time. */ + net_lock(); if (priv->ld_bifup && (tiva_ethin(priv, TIVA_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0) { /* If the interface is up and we can use the Tx FIFO, then poll the network @@ -1668,38 +1553,9 @@ static inline void tiva_txavail_process(struct tiva_driver_s *priv) (void)devif_poll(&priv->ld_dev, tiva_txpoll); } -} - -/**************************************************************************** - * Function: tiva_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS -static void tiva_txavail_work(void *arg) -{ - struct tiva_driver_s *priv = (struct tiva_driver_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - tiva_txavail_process(priv); - net_unlock(state); + net_unlock(); } -#endif /**************************************************************************** * Function: tiva_txavail @@ -1724,7 +1580,6 @@ static int tiva_txavail(struct net_driver_s *dev) { struct tiva_driver_s *priv = (struct tiva_driver_s *)dev->d_private; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions and we will have to ignore the Tx * availability action. @@ -1737,21 +1592,6 @@ static int tiva_txavail(struct net_driver_s *dev) work_queue(ETHWORK, &priv->ld_work, tiva_txavail_work, priv, 0); } -#else - irqstate_t flags; - - /* Disable interrupts because this function may be called from interrupt - * level processing. - */ - - flags = enter_critical_section(); - - /* Perform the out-of-cycle poll now */ - - tiva_txavail_process(priv); - leave_critical_section(flags); -#endif - return OK; } diff --git a/arch/arm/src/tiva/tm4c_ethernet.c b/arch/arm/src/tiva/tm4c_ethernet.c index e00bf6ef31..a04854879d 100644 --- a/arch/arm/src/tiva/tm4c_ethernet.c +++ b/arch/arm/src/tiva/tm4c_ethernet.c @@ -53,11 +53,7 @@ #include #include #include - -#ifdef CONFIG_NET_NOINTS -# include -#endif - +#include #include #include #include @@ -102,13 +98,12 @@ * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +#if !defined(CONFIG_SCHED_WORKQUEUE) # error Work queue support is required -#endif +#else -/* Select work queue */ + /* Select work queue */ -#if defined(CONFIG_SCHED_WORKQUEUE) # if defined(CONFIG_TIVA_ETHERNET_HPWORK) # define ETHWORK HPWORK # elif defined(CONFIG_TIVA_ETHERNET_LPWORK) @@ -631,9 +626,7 @@ struct tiva_ethmac_s uint8_t fduplex : 1; /* Full (vs. half) duplex */ WDOG_ID txpoll; /* TX poll timer */ WDOG_ID txtimeout; /* TX timeout timer */ -#ifdef CONFIG_NET_NOINTS struct work_s work; /* For deferring work to the work queue */ -#endif #ifdef CONFIG_TIVA_PHY_INTERRUPTS xcpt_t handler; /* Attached PHY interrupt handler */ #endif @@ -709,35 +702,26 @@ static int tiva_recvframe(FAR struct tiva_ethmac_s *priv); static void tiva_receive(FAR struct tiva_ethmac_s *priv); static void tiva_freeframe(FAR struct tiva_ethmac_s *priv); static void tiva_txdone(FAR struct tiva_ethmac_s *priv); -static inline void tiva_interrupt_process(FAR struct tiva_ethmac_s *priv); -#ifdef CONFIG_NET_NOINTS + static void tiva_interrupt_work(FAR void *arg); -#endif static int tiva_interrupt(int irq, FAR void *context); /* Watchdog timer expirations */ -static inline void tiva_txtimeout_process(FAR struct tiva_ethmac_s *priv); -#ifdef CONFIG_NET_NOINTS static void tiva_txtimeout_work(FAR void *arg); -#endif static void tiva_txtimeout_expiry(int argc, uint32_t arg, ...); -static inline void tiva_poll_process(FAR struct tiva_ethmac_s *priv); -#ifdef CONFIG_NET_NOINTS static void tiva_poll_work(FAR void *arg); -#endif static void tiva_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ static int tiva_ifup(struct net_driver_s *dev); static int tiva_ifdown(struct net_driver_s *dev); -static inline void tiva_txavail_process(FAR struct tiva_ethmac_s *priv); -#ifdef CONFIG_NET_NOINTS + static void tiva_txavail_work(FAR void *arg); -#endif static int tiva_txavail(struct net_driver_s *dev); + #if defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_ICMPv6) static int tiva_addmac(struct net_driver_s *dev, FAR const uint8_t *mac); #endif @@ -1994,27 +1978,33 @@ static void tiva_txdone(FAR struct tiva_ethmac_s *priv) } /**************************************************************************** - * Function: tiva_interrupt_process + * Function: tiva_interrupt_work * * Description: - * Interrupt processing. This may be performed either within the interrupt - * handler or on the worker thread, depending upon the configuration + * Perform interrupt related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void tiva_interrupt_process(FAR struct tiva_ethmac_s *priv) +static void tiva_interrupt_work(FAR void *arg) { + FAR struct tiva_ethmac_s *priv = (FAR struct tiva_ethmac_s *)arg; uint32_t dmaris; + DEBUGASSERT(priv); + + /* Process pending Ethernet interrupts */ + + net_lock(); + /* Get the DMA interrupt status bits (no MAC interrupts are expected) */ dmaris = tiva_getreg(TIVA_EMAC_DMARIS); @@ -2086,44 +2076,13 @@ static inline void tiva_interrupt_process(FAR struct tiva_ethmac_s *priv) tiva_putreg(EMAC_DMAINT_AIS, TIVA_EMAC_DMARIS); } #endif -} -/**************************************************************************** - * Function: tiva_interrupt_work - * - * Description: - * Perform interrupt related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() was called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void tiva_interrupt_work(FAR void *arg) -{ - FAR struct tiva_ethmac_s *priv = (FAR struct tiva_ethmac_s *)arg; - net_lock_t state; - - DEBUGASSERT(priv); - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - tiva_interrupt_process(priv); - net_unlock(state); + net_unlock(); /* Re-enable Ethernet interrupts at the NVIC */ up_enable_irq(TIVA_IRQ_ETHCON); } -#endif /**************************************************************************** * Function: tiva_interrupt @@ -2145,8 +2104,6 @@ static void tiva_interrupt_work(FAR void *arg) static int tiva_interrupt(int irq, FAR void *context) { FAR struct tiva_ethmac_s *priv = &g_tiva_ethmac[0]; - -#ifdef CONFIG_NET_NOINTS uint32_t dmaris; /* Get the raw interrupt status. */ @@ -2182,12 +2139,6 @@ static int tiva_interrupt(int irq, FAR void *context) work_queue(ETHWORK, &priv->work, tiva_interrupt_work, priv, 0); } -#else - /* Process the interrupt now */ - - tiva_interrupt_process(priv); -#endif - #ifdef CONFIG_TIVA_PHY_INTERRUPTS /* Check for pending PHY interrupts */ @@ -2209,38 +2160,6 @@ static int tiva_interrupt(int irq, FAR void *context) return OK; } -/**************************************************************************** - * Function: tiva_txtimeout_process - * - * Description: - * Process a TX timeout. Called from the either the watchdog timer - * expiration logic or from the worker thread, depending upon the - * configuration. The timeout means that the last TX never completed. - * Reset the hardware and start again. - * - * Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * Global interrupts are disabled by the watchdog logic. - * - ****************************************************************************/ - -static inline void tiva_txtimeout_process(FAR struct tiva_ethmac_s *priv) -{ - /* Reset the hardware. Just take the interface down, then back up again. */ - - tiva_ifdown(&priv->dev); - tiva_ifup(&priv->dev); - - /* Then poll the network for new XMIT data */ - - tiva_dopoll(priv); -} - /**************************************************************************** * Function: tiva_txtimeout_work * @@ -2258,19 +2177,21 @@ static inline void tiva_txtimeout_process(FAR struct tiva_ethmac_s *priv) * ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS static void tiva_txtimeout_work(FAR void *arg) { FAR struct tiva_ethmac_s *priv = (FAR struct tiva_ethmac_s *)arg; - net_lock_t state; - /* Process pending Ethernet interrupts */ + /* Reset the hardware. Just take the interface down, then back up again. */ + + net_lock(); + tiva_ifdown(&priv->dev); + tiva_ifup(&priv->dev); - state = net_lock(); - tiva_txtimeout_process(priv); - net_unlock(state); + /* Then poll the network for new XMIT data */ + + tiva_dopoll(priv); + net_unlock(); } -#endif /**************************************************************************** * Function: tiva_txtimeout_expiry @@ -2297,7 +2218,6 @@ static void tiva_txtimeout_expiry(int argc, uint32_t arg, ...) nerr("ERROR: Timeout!\n"); -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race * conditions with interrupt work. There is still a potential race * condition with interrupt work that is already queued and in progress. @@ -2316,33 +2236,28 @@ static void tiva_txtimeout_expiry(int argc, uint32_t arg, ...) /* Schedule to perform the TX timeout processing on the worker thread. */ work_queue(ETHWORK, &priv->work, tiva_txtimeout_work, priv, 0); - -#else - /* Process the timeout now */ - - tiva_txtimeout_process(priv); -#endif } /**************************************************************************** - * Function: tiva_poll_process + * Function: tiva_poll_work * * Description: - * Perform the periodic poll. This may be called either from watchdog - * timer logic or from the worker thread, depending upon the configuration. + * Perform periodic polling from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: + * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void tiva_poll_process(FAR struct tiva_ethmac_s *priv) +static void tiva_poll_work(FAR void *arg) { + FAR struct tiva_ethmac_s *priv = (FAR struct tiva_ethmac_s *)arg; FAR struct net_driver_s *dev = &priv->dev; /* Check if the next TX descriptor is owned by the Ethernet DMA or CPU. We @@ -2356,6 +2271,7 @@ static inline void tiva_poll_process(FAR struct tiva_ethmac_s *priv) * CONFIG_TIVA_EMAC_NTXDESC). */ + net_lock(); if ((priv->txhead->tdes0 & EMAC_TDES0_OWN) == 0 && priv->txhead->tdes2 == 0) { @@ -2391,39 +2307,9 @@ static inline void tiva_poll_process(FAR struct tiva_ethmac_s *priv) /* Setup the watchdog poll timer again */ (void)wd_start(priv->txpoll, TIVA_WDDELAY, tiva_poll_expiry, 1, (uint32_t)priv); + net_unlock(); } -/**************************************************************************** - * Function: tiva_poll_work - * - * Description: - * Perform periodic polling from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void tiva_poll_work(FAR void *arg) -{ - FAR struct tiva_ethmac_s *priv = (FAR struct tiva_ethmac_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - tiva_poll_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: tiva_poll_expiry * @@ -2446,7 +2332,6 @@ static void tiva_poll_expiry(int argc, uint32_t arg, ...) { FAR struct tiva_ethmac_s *priv = (FAR struct tiva_ethmac_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions. */ @@ -2465,12 +2350,6 @@ static void tiva_poll_expiry(int argc, uint32_t arg, ...) (void)wd_start(priv->txpoll, TIVA_WDDELAY, tiva_poll_expiry, 1, (uint32_t)priv); } - -#else - /* Process the interrupt now */ - - tiva_poll_process(priv); -#endif } /**************************************************************************** @@ -2576,66 +2455,40 @@ static int tiva_ifdown(struct net_driver_s *dev) } /**************************************************************************** - * Function: tiva_txavail_process + * Function: tiva_txavail_work * * Description: - * Perform an out-of-cycle poll. + * Perform an out-of-cycle poll on the worker thread. * * Parameters: - * priv - Reference to the NuttX driver state structure + * arg - Reference to the NuttX driver state structure (cast to void*) * * Returned Value: * None * * Assumptions: - * Called in normal user mode + * Called on the higher priority worker thread. * ****************************************************************************/ -static inline void tiva_txavail_process(FAR struct tiva_ethmac_s *priv) +static void tiva_txavail_work(FAR void *arg) { + FAR struct tiva_ethmac_s *priv = (FAR struct tiva_ethmac_s *)arg; + ninfo("ifup: %d\n", priv->ifup); /* Ignore the notification if the interface is not yet up */ + net_lock(); if (priv->ifup) { /* Poll the network for new XMIT data */ tiva_dopoll(priv); } -} - -/**************************************************************************** - * Function: tiva_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS -static void tiva_txavail_work(FAR void *arg) -{ - FAR struct tiva_ethmac_s *priv = (FAR struct tiva_ethmac_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - tiva_txavail_process(priv); - net_unlock(state); + net_unlock(); } -#endif /**************************************************************************** * Function: tiva_txavail @@ -2660,7 +2513,6 @@ static int tiva_txavail(struct net_driver_s *dev) { FAR struct tiva_ethmac_s *priv = (FAR struct tiva_ethmac_s *)dev->d_private; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions and we will have to ignore the Tx * availability action. @@ -2673,21 +2525,6 @@ static int tiva_txavail(struct net_driver_s *dev) work_queue(ETHWORK, &priv->work, tiva_txavail_work, priv, 0); } -#else - irqstate_t flags; - - /* Disable interrupts because this function may be called from interrupt - * level processing. - */ - - flags = enter_critical_section(); - - /* Perform the out-of-cycle poll now */ - - tiva_txavail_process(priv); - leave_critical_section(flags); -#endif - return OK; } diff --git a/arch/mips/src/pic32mx/pic32mx-ethernet.c b/arch/mips/src/pic32mx/pic32mx-ethernet.c index 2277e09039..3515635f22 100644 --- a/arch/mips/src/pic32mx/pic32mx-ethernet.c +++ b/arch/mips/src/pic32mx/pic32mx-ethernet.c @@ -55,11 +55,7 @@ #include #include #include - -#ifdef CONFIG_NET_NOINTS -# include -#endif - +#include #include #include #include @@ -90,13 +86,12 @@ * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +#if !defined(CONFIG_SCHED_WORKQUEUE) # error Work queue support is required in this configuration (CONFIG_SCHED_WORKQUEUE) -#endif +#else -/* Use the low priority work queue if possible */ + /* Use the low priority work queue if possible */ -#if defined(CONFIG_SCHED_WORKQUEUE) # if defined(CONFIG_PIC32MX_ETHERNET_HPWORK) # define ETHWORK HPWORK # elif defined(CONFIG_PIC32MX_ETHERNET_LPWORK) @@ -326,9 +321,7 @@ struct pic32mx_driver_s uint32_t pd_inten; /* Shadow copy of INTEN register */ WDOG_ID pd_txpoll; /* TX poll timer */ WDOG_ID pd_txtimeout; /* TX timeout timer */ -#ifdef CONFIG_NET_NOINTS struct work_s pd_work; /* For deferring work to the work queue */ -#endif sq_queue_t pd_freebuffers; /* The free buffer list */ @@ -401,24 +394,15 @@ static void pic32mx_response(struct pic32mx_driver_s *priv); static void pic32mx_rxdone(struct pic32mx_driver_s *priv); static void pic32mx_txdone(struct pic32mx_driver_s *priv); -static inline void pic32mx_interrupt_process(struct pic32mx_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void pic32mx_interrupt_work(void *arg); -#endif static int pic32mx_interrupt(int irq, void *context); /* Watchdog timer expirations */ -static inline void pic32mx_txtimeout_process(struct pic32mx_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void pic32mx_txtimeout_work(void *arg); -#endif static void pic32mx_txtimeout_expiry(int argc, uint32_t arg, ...); -static inline void pic32mx_poll_process(struct pic32mx_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void pic32mx_poll_work(void *arg); -#endif static void pic32mx_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ @@ -426,10 +410,7 @@ static void pic32mx_poll_expiry(int argc, uint32_t arg, ...); static int pic32mx_ifup(struct net_driver_s *dev); static int pic32mx_ifdown(struct net_driver_s *dev); -static inline void pic32mx_txavail_process(struct pic32mx_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void pic32mx_txavail_work(void *arg); -#endif static int pic32mx_txavail(struct net_driver_s *dev); #ifdef CONFIG_NET_IGMP @@ -1682,27 +1663,31 @@ static void pic32mx_txdone(struct pic32mx_driver_s *priv) } /**************************************************************************** - * Function: pic32mx_interrupt_process + * Function: pic32mx_interrupt_work * * Description: - * Interrupt processing. This may be performed either within the interrupt - * handler or on the worker thread, depending upon the configuration + * Perform interrupt related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: * The network is locked. * ****************************************************************************/ -static inline void pic32mx_interrupt_process(struct pic32mx_driver_s *priv) +static void pic32mx_interrupt_work(void *arg) { + struct pic32mx_driver_s *priv = (struct pic32mx_driver_s *)arg; uint32_t status; + /* Process pending Ethernet interrupts */ + + net_lock(); + /* Get the interrupt status (zero means no interrupts pending). */ status = pic32mx_getreg(PIC32MX_ETH_IRQ); @@ -1840,36 +1825,7 @@ static inline void pic32mx_interrupt_process(struct pic32mx_driver_s *priv) #else up_clrpend_irq(PIC32MX_IRQSRC_ETH); #endif -} - -/**************************************************************************** - * Function: pic32mx_interrupt_work - * - * Description: - * Perform interrupt related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() was called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void pic32mx_interrupt_work(void *arg) -{ - struct pic32mx_driver_s *priv = (struct pic32mx_driver_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - pic32mx_interrupt_process(priv); - net_unlock(state); + net_unlock(); /* Re-enable Ethernet interrupts */ @@ -1879,7 +1835,6 @@ static void pic32mx_interrupt_work(void *arg) up_enable_irq(PIC32MX_IRQSRC_ETH); #endif } -#endif /**************************************************************************** * Function: pic32mx_interrupt @@ -1909,7 +1864,6 @@ static int pic32mx_interrupt(int irq, void *context) priv = &g_ethdrvr[0]; #endif -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. Because Ethernet interrupts are * also disabled if the TX timeout event occurs, there can be no race * condition here. @@ -1944,37 +1898,33 @@ static int pic32mx_interrupt(int irq, void *context) /* Schedule to perform the interrupt processing on the worker thread. */ work_queue(ETHWORK, &priv->pd_work, pic32mx_interrupt_work, priv, 0); - -#else - /* Process the interrupt now */ - - pic32mx_interrupt_process(priv); -#endif - return OK; } /**************************************************************************** - * Function: pic32mx_txtimeout_process + * Function: pic32mx_txtimeout_work * * Description: - * Process a TX timeout. Called from the either the watchdog timer - * expiration logic or from the worker thread, depending upon the - * configuration. The timeout means that the last TX never completed. - * Reset the hardware and start again. + * Perform TX timeout related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success + * + * Assumptions: + * The network is locked. * ****************************************************************************/ -static inline void pic32mx_txtimeout_process(struct pic32mx_driver_s *priv) +static void pic32mx_txtimeout_work(void *arg) { + struct pic32mx_driver_s *priv = (struct pic32mx_driver_s *)arg; + /* Increment statistics and dump debug info */ + net_lock(); NETDEV_TXTIMEOUTS(&priv->pd_dev); if (priv->pd_ifup) { @@ -1990,38 +1940,9 @@ static inline void pic32mx_txtimeout_process(struct pic32mx_driver_s *priv) pic32mx_poll(priv); } -} - -/**************************************************************************** - * Function: pic32mx_txtimeout_work - * - * Description: - * Perform TX timeout related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void pic32mx_txtimeout_work(void *arg) -{ - struct pic32mx_driver_s *priv = (struct pic32mx_driver_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - state = net_lock(); - pic32mx_txtimeout_process(priv); - net_unlock(state); + net_unlock(); } -#endif /**************************************************************************** * Function: pic32mx_txtimeout_expiry @@ -2046,7 +1967,6 @@ static void pic32mx_txtimeout_expiry(int argc, wdparm_t arg, ...) { struct pic32mx_driver_s *priv = (struct pic32mx_driver_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race * conditions with interrupt work. There is still a potential race * condition with interrupt work that is already queued and in progress. @@ -2067,36 +1987,34 @@ static void pic32mx_txtimeout_expiry(int argc, wdparm_t arg, ...) /* Schedule to perform the TX timeout processing on the worker thread. */ work_queue(ETHWORK, &priv->pd_work, pic32mx_txtimeout_work, priv, 0); -#else - /* Process the timeout now */ - - pic32mx_txtimeout_process(priv); -#endif } /**************************************************************************** - * Function: pic32mx_poll_process + * Function: pic32mx_poll_work * * Description: - * Perform the periodic poll. This may be called either from watchdog - * timer logic or from the worker thread, depending upon the configuration. + * Perform periodic polling from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: + * The network is locked. * ****************************************************************************/ -static inline void pic32mx_poll_process(struct pic32mx_driver_s *priv) +static void pic32mx_poll_work(void *arg) { + struct pic32mx_driver_s *priv = (struct pic32mx_driver_s *)arg; + /* Check if the next Tx descriptor is available. We cannot perform the Tx * poll if we are unable to accept another packet for transmission. */ + net_lock(); if (pic32mx_txdesc(priv) != NULL) { /* If so, update TCP timing states and poll the network for new XMIT data. Hmmm.. @@ -2111,39 +2029,9 @@ static inline void pic32mx_poll_process(struct pic32mx_driver_s *priv) (void)wd_start(priv->pd_txpoll, PIC32MX_WDDELAY, pic32mx_poll_expiry, 1, priv); + net_unlock(); } -/**************************************************************************** - * Function: pic32mx_poll_work - * - * Description: - * Perform periodic polling from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void pic32mx_poll_work(void *arg) -{ - struct pic32mx_driver_s *priv = (struct pic32mx_driver_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - pic32mx_poll_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: pic32mx_poll_expiry * @@ -2166,7 +2054,6 @@ static void pic32mx_poll_expiry(int argc, wdparm_t arg, ...) { struct pic32mx_driver_s *priv = (struct pic32mx_driver_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions. */ @@ -2186,12 +2073,6 @@ static void pic32mx_poll_expiry(int argc, wdparm_t arg, ...) (void)wd_start(priv->pd_txpoll, PIC32MX_WDDELAY, pic32mx_poll_expiry, 1, arg); } - -#else - /* Process the interrupt now */ - - pic32mx_poll_process(priv); -#endif } /**************************************************************************** @@ -2542,26 +2423,29 @@ static int pic32mx_ifdown(struct net_driver_s *dev) } /**************************************************************************** - * Function: pic32mx_txavail_process + * Function: pic32mx_txavail_work * * Description: - * Perform an out-of-cycle poll. + * Perform an out-of-cycle poll on the worker thread. * * Parameters: - * dev - Reference to the NuttX driver state structure + * arg - Reference to the NuttX driver state structure (cast to void*) * * Returned Value: * None * * Assumptions: - * Called in normal user mode + * Called on the higher priority worker thread. * ****************************************************************************/ -static inline void pic32mx_txavail_process(struct pic32mx_driver_s *priv) +static void pic32mx_txavail_work(void *arg) { + struct pic32mx_driver_s *priv = (struct pic32mx_driver_s *)arg; + /* Ignore the notification if the interface is not yet up */ + net_lock(); if (priv->pd_ifup) { /* Check if the next Tx descriptor is available. */ @@ -2575,38 +2459,9 @@ static inline void pic32mx_txavail_process(struct pic32mx_driver_s *priv) pic32mx_poll(priv); } } -} -/**************************************************************************** - * Function: pic32mx_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void pic32mx_txavail_work(void *arg) -{ - struct pic32mx_driver_s *priv = (struct pic32mx_driver_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - pic32mx_txavail_process(priv); - net_unlock(state); + net_unlock(); } -#endif /**************************************************************************** * Function: pic32mx_txavail @@ -2631,7 +2486,6 @@ static int pic32mx_txavail(struct net_driver_s *dev) { struct pic32mx_driver_s *priv = (struct pic32mx_driver_s *)dev->d_private; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions and we will have to ignore the Tx * availability action. @@ -2644,21 +2498,6 @@ static int pic32mx_txavail(struct net_driver_s *dev) work_queue(ETHWORK, &priv->pd_work, pic32mx_txavail_work, priv, 0); } -#else - irqstate_t flags; - - /* Disable interrupts because this function may be called from interrupt - * level processing. - */ - - flags = enter_critical_section(); - - /* Perform the out-of-cycle poll now */ - - pic32mx_txavail_process(priv); - leave_critical_section(flags); -#endif - return OK; } diff --git a/arch/mips/src/pic32mz/pic32mz-ethernet.c b/arch/mips/src/pic32mz/pic32mz-ethernet.c index 356edab2d1..7eb5c4d54c 100644 --- a/arch/mips/src/pic32mz/pic32mz-ethernet.c +++ b/arch/mips/src/pic32mz/pic32mz-ethernet.c @@ -55,11 +55,7 @@ #include #include #include - -#ifdef CONFIG_NET_NOINTS -# include -#endif - +#include #include #include #include @@ -90,13 +86,12 @@ * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +#if !defined(CONFIG_SCHED_WORKQUEUE) # error Work queue support is required in this configuration (CONFIG_SCHED_WORKQUEUE) -#endif +#else -/* Use the low priority work queue if possible */ + /* Use the low priority work queue if possible */ -#if defined(CONFIG_SCHED_WORKQUEUE) # if defined(CONFIG_PIC32MZ_ETHERNET_HPWORK) # define ETHWORK HPWORK # elif defined(CONFIG_PIC32MZ_ETHERNET_LPWORK) @@ -353,9 +348,7 @@ struct pic32mz_driver_s uint32_t pd_inten; /* Shadow copy of INTEN register */ WDOG_ID pd_txpoll; /* TX poll timer */ WDOG_ID pd_txtimeout; /* TX timeout timer */ -#ifdef CONFIG_NET_NOINTS struct work_s pd_work; /* For deferring work to the work queue */ -#endif sq_queue_t pd_freebuffers; /* The free buffer list */ @@ -428,24 +421,15 @@ static void pic32mz_response(struct pic32mz_driver_s *priv); static void pic32mz_rxdone(struct pic32mz_driver_s *priv); static void pic32mz_txdone(struct pic32mz_driver_s *priv); -static inline void pic32mz_interrupt_process(struct pic32mz_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void pic32mz_interrupt_work(void *arg); -#endif static int pic32mz_interrupt(int irq, void *context); /* Watchdog timer expirations */ -static inline void pic32mz_txtimeout_process(struct pic32mz_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void pic32mz_txtimeout_work(void *arg); -#endif static void pic32mz_txtimeout_expiry(int argc, uint32_t arg, ...); -static inline void pic32mz_poll_process(struct pic32mz_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void pic32mz_poll_work(void *arg); -#endif static void pic32mz_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ @@ -453,10 +437,7 @@ static void pic32mz_poll_expiry(int argc, uint32_t arg, ...); static int pic32mz_ifup(struct net_driver_s *dev); static int pic32mz_ifdown(struct net_driver_s *dev); -static inline void pic32mz_txavail_process(struct pic32mz_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void pic32mz_txavail_work(void *arg); -#endif static int pic32mz_txavail(struct net_driver_s *dev); #ifdef CONFIG_NET_IGMP @@ -1709,27 +1690,31 @@ static void pic32mz_txdone(struct pic32mz_driver_s *priv) } /**************************************************************************** - * Function: pic32mz_interrupt_process + * Function: pic32mz_interrupt_work * * Description: - * Interrupt processing. This may be performed either within the interrupt - * handler or on the worker thread, depending upon the configuration + * Perform interrupt related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: * The network is locked. * ****************************************************************************/ -static inline void pic32mz_interrupt_process(struct pic32mz_driver_s *priv) +static void pic32mz_interrupt_work(void *arg) { + struct pic32mz_driver_s *priv = (struct pic32mz_driver_s *)arg; uint32_t status; + /* Process pending Ethernet interrupts */ + + net_lock(); + /* Get the interrupt status (zero means no interrupts pending). */ status = pic32mz_getreg(PIC32MZ_ETH_IRQ); @@ -1867,36 +1852,7 @@ static inline void pic32mz_interrupt_process(struct pic32mz_driver_s *priv) #else up_clrpend_irq(PIC32MZ_IRQ_ETH); #endif -} - -/**************************************************************************** - * Function: pic32mz_interrupt_work - * - * Description: - * Perform interrupt related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() was called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void pic32mz_interrupt_work(void *arg) -{ - struct pic32mz_driver_s *priv = (struct pic32mz_driver_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - pic32mz_interrupt_process(priv); - net_unlock(state); + net_unlock(); /* Re-enable Ethernet interrupts */ @@ -1906,7 +1862,6 @@ static void pic32mz_interrupt_work(void *arg) up_enable_irq(PIC32MZ_IRQ_ETH); #endif } -#endif /**************************************************************************** * Function: pic32mz_interrupt @@ -1936,7 +1891,6 @@ static int pic32mz_interrupt(int irq, void *context) priv = &g_ethdrvr[0]; #endif -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. Because Ethernet interrupts are * also disabled if the TX timeout event occurs, there can be no race * condition here. @@ -1971,37 +1925,33 @@ static int pic32mz_interrupt(int irq, void *context) /* Schedule to perform the interrupt processing on the worker thread. */ work_queue(ETHWORK, &priv->pd_work, pic32mz_interrupt_work, priv, 0); - -#else - /* Process the interrupt now */ - - pic32mz_interrupt_process(priv); -#endif - return OK; } /**************************************************************************** - * Function: pic32mz_txtimeout_process + * Function: pic32mz_txtimeout_work * * Description: - * Process a TX timeout. Called from the either the watchdog timer - * expiration logic or from the worker thread, depending upon the - * configuration. The timeout means that the last TX never completed. - * Reset the hardware and start again. + * Perform TX timeout related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success + * + * Assumptions: + * The network is locked. * ****************************************************************************/ -static inline void pic32mz_txtimeout_process(struct pic32mz_driver_s *priv) +static void pic32mz_txtimeout_work(void *arg) { + struct pic32mz_driver_s *priv = (struct pic32mz_driver_s *)arg; + /* Increment statistics and dump debug info */ + net_lock(); NETDEV_TXTIMEOUTS(&priv->pd_dev); if (priv->pd_ifup) { @@ -2017,38 +1967,9 @@ static inline void pic32mz_txtimeout_process(struct pic32mz_driver_s *priv) pic32mz_poll(priv); } -} - -/**************************************************************************** - * Function: pic32mz_txtimeout_work - * - * Description: - * Perform TX timeout related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void pic32mz_txtimeout_work(void *arg) -{ - struct pic32mz_driver_s *priv = (struct pic32mz_driver_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - state = net_lock(); - pic32mz_txtimeout_process(priv); - net_unlock(state); + net_unlock(); } -#endif /**************************************************************************** * Function: pic32mz_txtimeout_expiry @@ -2073,7 +1994,6 @@ static void pic32mz_txtimeout_expiry(int argc, wdparm_t arg, ...) { struct pic32mz_driver_s *priv = (struct pic32mz_driver_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race * conditions with interrupt work. There is still a potential race * condition with interrupt work that is already queued and in progress. @@ -2094,36 +2014,34 @@ static void pic32mz_txtimeout_expiry(int argc, wdparm_t arg, ...) /* Schedule to perform the TX timeout processing on the worker thread. */ work_queue(ETHWORK, &priv->pd_work, pic32mz_txtimeout_work, priv, 0); -#else - /* Process the timeout now */ - - pic32mz_txtimeout_process(priv); -#endif } /**************************************************************************** - * Function: pic32mz_poll_process + * Function: pic32mz_poll_work * * Description: - * Perform the periodic poll. This may be called either from watchdog - * timer logic or from the worker thread, depending upon the configuration. + * Perform periodic polling from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: + * The network is locked. * ****************************************************************************/ -static inline void pic32mz_poll_process(struct pic32mz_driver_s *priv) +static void pic32mz_poll_work(void *arg) { + struct pic32mz_driver_s *priv = (struct pic32mz_driver_s *)arg; + /* Check if the next Tx descriptor is available. We cannot perform the Tx * poll if we are unable to accept another packet for transmission. */ + net_lock(); if (pic32mz_txdesc(priv) != NULL) { /* If so, update TCP timing states and poll the network for new XMIT @@ -2138,39 +2056,9 @@ static inline void pic32mz_poll_process(struct pic32mz_driver_s *priv) (void)wd_start(priv->pd_txpoll, PIC32MZ_WDDELAY, pic32mz_poll_expiry, 1, priv); + net_unlock(); } -/**************************************************************************** - * Function: pic32mz_poll_work - * - * Description: - * Perform periodic polling from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void pic32mz_poll_work(void *arg) -{ - struct pic32mz_driver_s *priv = (struct pic32mz_driver_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - pic32mz_poll_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: pic32mz_poll_expiry * @@ -2193,7 +2081,6 @@ static void pic32mz_poll_expiry(int argc, wdparm_t arg, ...) { struct pic32mz_driver_s *priv = (struct pic32mz_driver_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions. */ @@ -2212,12 +2099,6 @@ static void pic32mz_poll_expiry(int argc, wdparm_t arg, ...) (void)wd_start(priv->pd_txpoll, PIC32MZ_WDDELAY, pic32mz_poll_expiry, 1, arg); } - -#else - /* Process the interrupt now */ - - pic32mz_poll_process(priv); -#endif } /**************************************************************************** @@ -2574,26 +2455,29 @@ static int pic32mz_ifdown(struct net_driver_s *dev) } /**************************************************************************** - * Function: pic32mz_txavail_process + * Function: pic32mz_txavail_work * * Description: - * Perform an out-of-cycle poll. + * Perform an out-of-cycle poll on the worker thread. * * Parameters: - * dev - Reference to the NuttX driver state structure + * arg - Reference to the NuttX driver state structure (cast to void*) * * Returned Value: * None * * Assumptions: - * Called in normal user mode + * Called on the higher priority worker thread. * ****************************************************************************/ -static inline void pic32mz_txavail_process(struct pic32mz_driver_s *priv) +static void pic32mz_txavail_work(void *arg) { + struct pic32mz_driver_s *priv = (struct pic32mz_driver_s *)arg; + /* Ignore the notification if the interface is not yet up */ + net_lock(); if (priv->pd_ifup) { /* Check if the next Tx descriptor is available. */ @@ -2607,38 +2491,9 @@ static inline void pic32mz_txavail_process(struct pic32mz_driver_s *priv) pic32mz_poll(priv); } } -} -/**************************************************************************** - * Function: pic32mz_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void pic32mz_txavail_work(void *arg) -{ - struct pic32mz_driver_s *priv = (struct pic32mz_driver_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - pic32mz_txavail_process(priv); - net_unlock(state); + net_unlock(); } -#endif /**************************************************************************** * Function: pic32mz_txavail @@ -2663,7 +2518,6 @@ static int pic32mz_txavail(struct net_driver_s *dev) { struct pic32mz_driver_s *priv = (struct pic32mz_driver_s *)dev->d_private; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions and we will have to ignore the Tx * availability action. @@ -2676,21 +2530,6 @@ static int pic32mz_txavail(struct net_driver_s *dev) work_queue(ETHWORK, &priv->pd_work, pic32mz_txavail_work, priv, 0); } -#else - irqstate_t flags; - - /* Disable interrupts because this function may be called from interrupt - * level processing. - */ - - flags = enter_critical_section(); - - /* Perform the out-of-cycle poll now */ - - pic32mz_txavail_process(priv); - leave_critical_section(flags); -#endif - return OK; } diff --git a/arch/misoc/src/common/misoc_net.c b/arch/misoc/src/common/misoc_net.c index e23689f869..85d6e60bbf 100644 --- a/arch/misoc/src/common/misoc_net.c +++ b/arch/misoc/src/common/misoc_net.c @@ -54,20 +54,18 @@ #include #include #include +#include #include #include #include #include + #include "chip.h" #include "hw/flags.h" #include "hw/ethmac_mem.h" #include "misoc.h" -#ifdef CONFIG_NET_NOINTS -# include -#endif - #ifdef CONFIG_NET_PKT # include #endif @@ -80,8 +78,8 @@ * work queue support is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_HPWORK) -/* REVISIT: The low priority work queue would be preferred if it is avaiable */ +#if !defined(CONFIG_SCHED_HPWORK) + /* REVISIT: The low priority work queue would be preferred if it is avaiable */ # error High priority work queue support is required #endif @@ -119,9 +117,7 @@ struct misoc_net_driver_s bool misoc_net_bifup; /* true:ifup false:ifdown */ WDOG_ID misoc_net_txpoll; /* TX poll timer */ WDOG_ID misoc_net_txtimeout; /* TX timeout timer */ -#ifdef CONFIG_NET_NOINTS struct work_s misoc_net_work; /* For deferring work to the work queue */ -#endif uint8_t *rx0_buf; /* 2 RX and 2 TX buffer */ uint8_t *rx1_buf; @@ -163,35 +159,26 @@ static int misoc_net_txpoll(FAR struct net_driver_s *dev); static void misoc_net_receive(FAR struct misoc_net_driver_s *priv); static void misoc_net_txdone(FAR struct misoc_net_driver_s *priv); -static inline void misoc_net_interrupt_process(FAR struct misoc_net_driver_s *priv); -#ifdef CONFIG_NET_NOINTS + static void misoc_net_interrupt_work(FAR void *arg); -#endif static int misoc_net_interrupt(int irq, FAR void *context); /* Watchdog timer expirations */ -static inline void misoc_net_txtimeout_process(FAR struct misoc_net_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void misoc_net_txtimeout_work(FAR void *arg); -#endif static void misoc_net_txtimeout_expiry(int argc, wdparm_t arg, ...); -static inline void misoc_net_poll_process(FAR struct misoc_net_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void misoc_net_poll_work(FAR void *arg); -#endif static void misoc_net_poll_expiry(int argc, wdparm_t arg, ...); /* NuttX callback functions */ static int misoc_net_ifup(FAR struct net_driver_s *dev); static int misoc_net_ifdown(FAR struct net_driver_s *dev); -static inline void misoc_net_txavail_process(FAR struct misoc_net_driver_s *priv); -#ifdef CONFIG_NET_NOINTS + static void misoc_net_txavail_work(FAR void *arg); -#endif static int misoc_net_txavail(FAR struct net_driver_s *dev); + #if defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_ICMPv6) static int misoc_net_addmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac); #ifdef CONFIG_NET_IGMP @@ -586,28 +573,29 @@ static void misoc_net_txdone(FAR struct misoc_net_driver_s *priv) } /**************************************************************************** - * Function: misoc_net_interrupt_process + * Function: misoc_net_interrupt_work * * Description: - * Interrupt processing. This may be performed either within the interrupt - * handler or on the worker thread, depending upon the configuration + * Perform interrupt related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: * The network is locked. * ****************************************************************************/ -static inline void misoc_net_interrupt_process(FAR struct misoc_net_driver_s *priv) +static void misoc_net_interrupt_work(FAR void *arg) { - /* Get and clear interrupt status bits */ + FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)arg; - /* Handle interrupts according to status bit settings */ + /* Process pending Ethernet interrupts */ + + net_lock(); /* Check if we received an incoming packet, if so, call misoc_net_receive() */ @@ -626,42 +614,13 @@ static inline void misoc_net_interrupt_process(FAR struct misoc_net_driver_s *pr misoc_net_txdone(priv); ethmac_sram_reader_ev_pending_write(1); } -} - -/**************************************************************************** - * Function: misoc_net_interrupt_work - * - * Description: - * Perform interrupt related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() was called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void misoc_net_interrupt_work(FAR void *arg) -{ - FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)arg; - net_lock_t state; - /* Process pending Ethernet interrupts */ - - state = net_lock(); - misoc_net_interrupt_process(priv); - net_unlock(state); + net_unlock(); /* Re-enable Ethernet interrupts */ up_enable_irq(ETHMAC_INTERRUPT); } -#endif /**************************************************************************** * Function: misoc_net_interrupt @@ -684,7 +643,6 @@ static int misoc_net_interrupt(int irq, FAR void *context) { FAR struct misoc_net_driver_s *priv = &g_misoc_net[0]; -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. Because Ethernet interrupts are * also disabled if the TX timeout event occurs, there can be no race * condition here. @@ -709,47 +667,9 @@ static int misoc_net_interrupt(int irq, FAR void *context) /* Schedule to perform the interrupt processing on the worker thread. */ work_queue(HPWORK, &priv->misoc_net_work, misoc_net_interrupt_work, priv, 0); - -#else - /* Process the interrupt now */ - - misoc_net_interrupt_process(priv); - -#endif - return OK; } -/**************************************************************************** - * Function: misoc_net_txtimeout_process - * - * Description: - * Process a TX timeout. Called from the either the watchdog timer - * expiration logic or from the worker thread, depending upon the - * configuration. The timeout means that the last TX never completed. - * Reset the hardware and start again. - * - * Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void misoc_net_txtimeout_process(FAR struct misoc_net_driver_s *priv) -{ - /* Increment statistics and dump debug info */ - - NETDEV_TXTIMEOUTS(priv->misoc_net_dev); - - /* Then reset the hardware */ - - /* Then poll the network for new XMIT data */ - - (void)devif_poll(&priv->misoc_net_dev, misoc_net_txpoll); -} - /**************************************************************************** * Function: misoc_net_txtimeout_work * @@ -767,19 +687,22 @@ static inline void misoc_net_txtimeout_process(FAR struct misoc_net_driver_s *pr * ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS static void misoc_net_txtimeout_work(FAR void *arg) { FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)arg; - net_lock_t state; - /* Process pending Ethernet interrupts */ + /* Increment statistics and dump debug info */ + + net_lock(); + NETDEV_TXTIMEOUTS(priv->misoc_net_dev); + + /* Then reset the hardware */ - state = net_lock(); - misoc_net_txtimeout_process(priv); - net_unlock(state); + /* Then poll the network for new XMIT data */ + + (void)devif_poll(&priv->misoc_net_dev, misoc_net_txpoll); + net_unlock(); } -#endif /**************************************************************************** * Function: misoc_net_txtimeout_expiry @@ -804,7 +727,6 @@ static void misoc_net_txtimeout_expiry(int argc, wdparm_t arg, ...) { FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race * conditions with interrupt work. There is still a potential race * condition with interrupt work that is already queued and in progress. @@ -821,32 +743,33 @@ static void misoc_net_txtimeout_expiry(int argc, wdparm_t arg, ...) /* Schedule to perform the TX timeout processing on the worker thread. */ work_queue(HPWORK, &priv->misoc_net_work, misoc_net_txtimeout_work, priv, 0); -#else - /* Process the timeout now */ - - misoc_net_txtimeout_process(priv); -#endif } /**************************************************************************** - * Function: misoc_net_poll_process + * Function: misoc_net_poll_work * * Description: - * Perform the periodic poll. This may be called either from watchdog - * timer logic or from the worker thread, depending upon the configuration. + * Perform periodic polling from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: + * The network is locked. * ****************************************************************************/ -static inline void misoc_net_poll_process(FAR struct misoc_net_driver_s *priv) +static void misoc_net_poll_work(FAR void *arg) { + FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)arg; + + /* Perform the poll */ + + net_lock(); + /* Check if there is room in the send another TX packet. We cannot perform * the TX poll if he are unable to accept another packet for transmission. */ @@ -862,38 +785,9 @@ static inline void misoc_net_poll_process(FAR struct misoc_net_driver_s *priv) (void)wd_start(priv->misoc_net_txpoll, MISOC_NET_WDDELAY, misoc_net_poll_expiry, 1, (wdparm_t)priv); -} -/**************************************************************************** - * Function: misoc_net_poll_work - * - * Description: - * Perform periodic polling from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void misoc_net_poll_work(FAR void *arg) -{ - FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - misoc_net_poll_process(priv); - net_unlock(state); + net_unlock(); } -#endif /**************************************************************************** * Function: misoc_net_poll_expiry @@ -917,7 +811,6 @@ static void misoc_net_poll_expiry(int argc, wdparm_t arg, ...) { FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions. */ @@ -934,14 +827,9 @@ static void misoc_net_poll_expiry(int argc, wdparm_t arg, ...) * cycle. */ - (void)wd_start(priv->misoc_net_txpoll, MISOC_NET_WDDELAY, misoc_net_poll_expiry, 1, arg); + (void)wd_start(priv->misoc_net_txpoll, MISOC_NET_WDDELAY, + misoc_net_poll_expiry, 1, arg); } - -#else - /* Process the interrupt now */ - - misoc_net_poll_process(priv); -#endif } /**************************************************************************** @@ -1045,26 +933,29 @@ static int misoc_net_ifdown(FAR struct net_driver_s *dev) } /**************************************************************************** - * Function: misoc_net_txavail_process + * Function: misoc_net_txavail_work * * Description: - * Perform an out-of-cycle poll. + * Perform an out-of-cycle poll on the worker thread. * * Parameters: - * dev - Reference to the NuttX driver state structure + * arg - Reference to the NuttX driver state structure (cast to void*) * * Returned Value: * None * * Assumptions: - * Called in normal user mode + * Called on the higher priority worker thread. * ****************************************************************************/ -static inline void misoc_net_txavail_process(FAR struct misoc_net_driver_s *priv) +static void misoc_net_txavail_work(FAR void *arg) { + FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)arg; + /* Ignore the notification if the interface is not yet up */ + net_lock(); if (priv->misoc_net_bifup) { /* Check if there is room in the hardware to hold another outgoing packet. */ @@ -1076,38 +967,9 @@ static inline void misoc_net_txavail_process(FAR struct misoc_net_driver_s *priv (void)devif_poll(&priv->misoc_net_dev, misoc_net_txpoll); } } -} -/**************************************************************************** - * Function: misoc_net_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void misoc_net_txavail_work(FAR void *arg) -{ - FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - misoc_net_txavail_process(priv); - net_unlock(state); + net_unlock(); } -#endif /**************************************************************************** * Function: misoc_net_txavail @@ -1132,7 +994,6 @@ static int misoc_net_txavail(FAR struct net_driver_s *dev) { FAR struct misoc_net_driver_s *priv = (FAR struct misoc_net_driver_s *)dev->d_private; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions and we will have to ignore the Tx * availability action. @@ -1145,21 +1006,6 @@ static int misoc_net_txavail(FAR struct net_driver_s *dev) work_queue(HPWORK, &priv->misoc_net_work, misoc_net_txavail_work, priv, 0); } -#else - irqstate_t flags; - - /* Disable interrupts because this function may be called from interrupt - * level processing. - */ - - flags = enter_critical_section(); - - /* Perform the out-of-cycle poll now */ - - misoc_net_txavail_process(priv); - leave_critical_section(flags); -#endif - return OK; } diff --git a/arch/z80/src/ez80/ez80_emac.c b/arch/z80/src/ez80/ez80_emac.c index 1a4e2129d7..71f1c4ee9c 100644 --- a/arch/z80/src/ez80/ez80_emac.c +++ b/arch/z80/src/ez80/ez80_emac.c @@ -56,11 +56,7 @@ #include #include #include - -#ifdef CONFIG_NET_NOINTS -# include -#endif - +#include #include #include #include @@ -84,13 +80,12 @@ * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +#if !defined(CONFIG_SCHED_WORKQUEUE) # error Work queue support is required in this configuration (CONFIG_SCHED_WORKQUEUE) -#endif +#else -/* Use the low priority work queue if possible */ + /* Use the low priority work queue if possible */ -#if defined(CONFIG_SCHED_WORKQUEUE) # if defined(CONFIG_EZ80_EMAC_HPWORK) # define ETHWORK HPWORK # elif defined(CONFIG_EZ80_EMAC_LPWORK) @@ -346,11 +341,9 @@ struct ez80emac_driver_s WDOG_ID txpoll; /* TX poll timer */ WDOG_ID txtimeout; /* TX timeout timer */ -#ifdef CONFIG_NET_NOINTS struct work_s txwork; /* For deferring Tx-related work to the work queue */ struct work_s rxwork; /* For deferring Rx-related work to the work queue */ struct work_s syswork; /* For deferring system work to the work queue */ -#endif #if defined(CONFIG_DEBUG_FEATURES) && defined(CONFIG_DEBUG_NET) struct ez80mac_statistics_s stat; @@ -406,36 +399,21 @@ static int ez80emac_receive(struct ez80emac_driver_s *priv); /* Interrupt handling */ -static inline void ez80emac_txinterrupt_process(FAR struct ez80emac_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void ez80emac_txinterrupt_work(FAR void *arg); -#endif static int ez80emac_txinterrupt(int irq, FAR void *context); -static inline void ez80emac_rxinterrupt_process(FAR struct ez80emac_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void ez80emac_rxinterrupt_work(FAR void *arg); -#endif static int ez80emac_rxinterrupt(int irq, FAR void *context); -static inline void ez80emac_sysinterrupt_process(FAR struct ez80emac_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void ez80emac_sysinterrupt_work(FAR void *arg); -#endif static int ez80emac_sysinterrupt(int irq, FAR void *context); /* Watchdog timer expirations */ -static inline void ez80emac_txtimeout_process(FAR struct ez80emac_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void ez80emac_txtimeout_work(FAR void *arg); -#endif static void ez80emac_txtimeout_expiry(int argc, uint32_t arg, ...); -static inline void ez80emac_poll_process(FAR struct ez80emac_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void ez80emac_poll_work(FAR void *arg); -#endif static void ez80emac_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ @@ -443,10 +421,7 @@ static void ez80emac_poll_expiry(int argc, uint32_t arg, ...); static int ez80emac_ifup(struct net_driver_s *dev); static int ez80emac_ifdown(struct net_driver_s *dev); -static inline void ez80emac_txavail_process(FAR struct ez80emac_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void ez80emac_txavail_work(FAR void *arg); -#endif static int ez80emac_txavail(struct net_driver_s *dev); #ifdef CONFIG_NET_IGMP @@ -1475,29 +1450,33 @@ static int ez80emac_receive(struct ez80emac_driver_s *priv) } /**************************************************************************** - * Function: ez80emac_txinterrupt_process + * Function: ez80emac_txinterrupt_work * * Description: - * Tx Interrupt processing. This may be performed either within the - * interrupt handler or on the worker thread, depending upon the configuration + * Perform Tx interrupt related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: * The network is locked. * ****************************************************************************/ -static inline void ez80emac_txinterrupt_process(FAR struct ez80emac_driver_s *priv) +static void ez80emac_txinterrupt_work(FAR void *arg) { + FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)arg; FAR struct ez80emac_desc_s *txhead = priv->txhead; uint8_t regval; uint8_t istat; + /* Process pending Ethernet Tx interrupts */ + + net_lock(); + /* EMAC Tx interrupts: * * EMAC_ISTAT_TXDONE - Bit 0: 1=Transmit done interrupt @@ -1577,42 +1556,13 @@ static inline void ez80emac_txinterrupt_process(FAR struct ez80emac_driver_s *pr wd_cancel(priv->txtimeout); } -} - -/**************************************************************************** - * Function: ez80emac_txinterrupt_work - * - * Description: - * Perform Tx interrupt related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() was called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS -static void ez80emac_txinterrupt_work(FAR void *arg) -{ - FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - ez80emac_txinterrupt_process(priv); - net_unlock(state); + net_unlock(); /* Re-enable Ethernet Tx interrupts */ up_enable_irq(EZ80_EMACRX_IRQ); } -#endif /**************************************************************************** * Function: ez80emac_txinterrupt @@ -1636,7 +1586,6 @@ static int ez80emac_txinterrupt(int irq, FAR void *context) FAR struct ez80emac_driver_s *priv = &g_emac; uint8_t istat; -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet Tx interrupts. Because Ethernet interrupts are * also disabled if the TX timeout event occurs, there can be no race * condition here. @@ -1661,38 +1610,35 @@ static int ez80emac_txinterrupt(int irq, FAR void *context) work_queue(ETHWORK, &priv->txwork, ez80emac_txinterrupt_work, priv, 0); -#else - /* Process the interrupt now */ - - ez80emac_txinterrupt_process(priv); -#endif - return OK; } /**************************************************************************** - * Function: ez80emac_rxinterrupt_process + * Function: ez80emac_rxinterrupt_work * * Description: - * Rx Interrupt processing. This may be performed either within the - * interrupt handler or on the worker thread, depending upon the - * configuration + * Perform Rx interrupt related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: * The network is locked. * ****************************************************************************/ -static inline void ez80emac_rxinterrupt_process(FAR struct ez80emac_driver_s *priv) +static void ez80emac_rxinterrupt_work(FAR void *arg) { + FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)arg; uint8_t istat; + /* Process pending Ethernet Rx interrupts */ + + net_lock(); + /* EMAC Rx interrupts: * * EMAC_ISTAT_RXDONE - Bit 3: 1=Receive done interrupt @@ -1713,42 +1659,12 @@ static inline void ez80emac_rxinterrupt_process(FAR struct ez80emac_driver_s *pr /* Process any RX packets pending the RX buffer */ (void)ez80emac_receive(priv); -} - -/**************************************************************************** - * Function: ez80emac_rxinterrupt_work - * - * Description: - * Perform Rx interrupt related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() was called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void ez80emac_rxinterrupt_work(FAR void *arg) -{ - FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - ez80emac_rxinterrupt_process(priv); - net_unlock(state); + net_unlock(); /* Re-enable Ethernet Rx interrupts */ up_enable_irq(EZ80_EMACRX_IRQ); } -#endif /**************************************************************************** * Function: ez80emac_rxinterrupt @@ -1771,7 +1687,6 @@ static int ez80emac_rxinterrupt(int irq, FAR void *context) { FAR struct ez80emac_driver_s *priv = &g_emac; -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet Rx interrupts. Because Ethernet interrupts are * also disabled if the TX timeout event occurs, there can be no race * condition here. @@ -1779,54 +1694,39 @@ static int ez80emac_rxinterrupt(int irq, FAR void *context) up_disable_irq(EZ80_EMACRX_IRQ); - /* TODO: Determine if a TX transfer just completed */ - - { - /* If a TX transfer just completed, then cancel the TX timeout so - * there will be no race condition between any subsequent timeout - * expiration and the deferred interrupt processing. - */ - - wd_cancel(priv->txtimeout); - } - - /* Schedule to perform the interrupt processing on the worker thread. */ + /* Schedule to perform the Rx interrupt processing on the worker thread. */ work_queue(ETHWORK, &priv->rxwork, ez80emac_rxinterrupt_work, priv, 0); - -#else - /* Process the interrupt now */ - - ez80emac_rxinterrupt_process(priv); -#endif - return OK; } /**************************************************************************** - * Function: ez80emac_sysinterrupt_process + * Function: ez80emac_sysinterrupt_work * * Description: - * System interrupt processing. This may be performed either within the - * interrupt handler or on the worker thread, depending upon the - * configuration + * Perform system interrupt related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: * The network is locked. * ****************************************************************************/ -static inline void ez80emac_sysinterrupt_process(FAR struct ez80emac_driver_s *priv) +static void ez80emac_sysinterrupt_work(FAR void *arg) { + FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)arg; uint8_t events; uint8_t istat; + /* Process pending system interrupts */ + + net_lock(); + /* EMAC system interrupts : * * EMAC_ISTAT_TXFSMERR - Bit 7: 1=Transmit state machine error interrupt @@ -1879,42 +1779,13 @@ static inline void ez80emac_sysinterrupt_process(FAR struct ez80emac_driver_s *p EMAC_STAT(priv, rx_errors); EMAC_STAT(priv, rx_ovrerrors); } -} -/**************************************************************************** - * Function: ez80emac_sysinterrupt_work - * - * Description: - * Perform system interrupt related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() was called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void ez80emac_sysinterrupt_work(FAR void *arg) -{ - FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - ez80emac_sysinterrupt_process(priv); - net_unlock(state); + net_unlock(); /* Re-enable Ethernet system interrupts */ up_enable_irq(EZ80_EMACSYS_IRQ); } -#endif /**************************************************************************** * Function: ez80emac_sysinterrupt @@ -1937,7 +1808,6 @@ static int ez80emac_sysinterrupt(int irq, FAR void *context) { FAR struct ez80emac_driver_s *priv = &g_emac; -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. Because Ethernet interrupts are * also disabled if the TX timeout event occurs, there can be no race * condition here. @@ -1945,17 +1815,6 @@ static int ez80emac_sysinterrupt(int irq, FAR void *context) up_disable_irq(EZ80_EMACSYS_IRQ); - /* TODO: Determine if a TX transfer just completed */ - - { - /* If a TX transfer just completed, then cancel the TX timeout so - * there will be no race condition between any subsequent timeout - * expiration and the deferred interrupt processing. - */ - - wd_cancel(priv->txtimeout); - } - /* Cancel any pending poll work */ work_cancel(ETHWORK, &priv->syswork); @@ -1963,37 +1822,35 @@ static int ez80emac_sysinterrupt(int irq, FAR void *context) /* Schedule to perform the interrupt processing on the worker thread. */ work_queue(ETHWORK, &priv->syswork, ez80emac_sysinterrupt_work, priv, 0); - -#else - /* Process the interrupt now */ - - ez80emac_sysinterrupt_process(priv); -#endif - return OK; } /**************************************************************************** - * Function: ez80emac_txtimeout_process + * Function: ez80emac_txtimeout_work * * Description: - * Process a TX timeout. Called from the either the watchdog timer - * expiration logic or from the worker thread, depending upon the - * configuration. The timeout means that the last TX never completed. - * Reset the hardware and start again. + * Perform TX timeout related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success + * + * Assumptions: + * The network is locked. * ****************************************************************************/ -static inline void ez80emac_txtimeout_process(FAR struct ez80emac_driver_s *priv) +static void ez80emac_txtimeout_work(FAR void *arg) { + FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)arg; irqstate_t flags; + /* Process pending Ethernet interrupts */ + + net_lock(); + /* Increment statistics and dump debug info */ EMAC_STAT(priv, tx_errors); @@ -2009,39 +1866,9 @@ static inline void ez80emac_txtimeout_process(FAR struct ez80emac_driver_s *priv /* Then poll the network for new XMIT data */ (void)devif_poll(&priv->dev, ez80emac_txpoll); + net_unlock(); } -/**************************************************************************** - * Function: ez80emac_txtimeout_work - * - * Description: - * Perform TX timeout related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void ez80emac_txtimeout_work(FAR void *arg) -{ - FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - ez80emac_txtimeout_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: ez80emac_txtimeout_expiry * @@ -2065,7 +1892,6 @@ static void ez80emac_txtimeout_expiry(int argc, wdparm_t arg, ...) { FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet Tx interrupts. This will prevent some race * conditions with interrupt work. There is still a potential race * condition with interrupt work that is already queued and in progress. @@ -2082,39 +1908,6 @@ static void ez80emac_txtimeout_expiry(int argc, wdparm_t arg, ...) /* Schedule to perform the TX timeout processing on the worker thread. */ work_queue(ETHWORK, &priv->txwork, ez80emac_txtimeout_work, priv, 0); -#else - /* Process the timeout now */ - - ez80emac_txtimeout_process(priv); -#endif -} - -/**************************************************************************** - * Function: ez80emac_poll_process - * - * Description: - * Perform the periodic poll. This may be called either from watchdog - * timer logic or from the worker thread, depending upon the configuration. - * - * Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * None - * - * Assumptions: - * - ****************************************************************************/ - -static inline void ez80emac_poll_process(FAR struct ez80emac_driver_s *priv) -{ - /* Poll the network for new XMIT data */ - - (void)devif_timer(&priv->dev, ez80emac_txpoll); - - /* Setup the watchdog poll timer again */ - - (void)wd_start(priv->txpoll, EMAC_WDDELAY, ez80emac_poll_expiry, 1, priv); } /**************************************************************************** @@ -2134,19 +1927,20 @@ static inline void ez80emac_poll_process(FAR struct ez80emac_driver_s *priv) * ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS static void ez80emac_poll_work(FAR void *arg) { FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)arg; - net_lock_t state; - /* Perform the poll */ + /* Poll the network for new XMIT data */ + + net_lock(); + (void)devif_timer(&priv->dev, ez80emac_txpoll); + + /* Setup the watchdog poll timer again */ - state = net_lock(); - ez80emac_poll_process(priv); - net_unlock(state); + (void)wd_start(priv->txpoll, EMAC_WDDELAY, ez80emac_poll_expiry, 1, priv); + net_unlock(); } -#endif /**************************************************************************** * Function: ez80emac_poll_expiry @@ -2170,7 +1964,6 @@ static void ez80emac_poll_expiry(int argc, wdparm_t arg, ...) { FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions. */ @@ -2189,12 +1982,6 @@ static void ez80emac_poll_expiry(int argc, wdparm_t arg, ...) (void)wd_start(priv->txpoll, EMAC_WDDELAY, ez80emac_poll_expiry, 1, arg); } - -#else - /* Process the interrupt now */ - - ez80emac_poll_process(priv); -#endif } /**************************************************************************** @@ -2344,26 +2131,29 @@ static int ez80emac_ifdown(struct net_driver_s *dev) } /**************************************************************************** - * Function: ez80emac_txavail_process + * Function: ez80emac_txavail_work * * Description: - * Perform an out-of-cycle poll. + * Perform an out-of-cycle poll on the worker thread. * * Parameters: - * dev - Reference to the NuttX driver state structure + * arg - Reference to the NuttX driver state structure (cast to void*) * * Returned Value: * None * * Assumptions: - * Called in normal user mode + * Called on the higher priority worker thread. * ****************************************************************************/ -static inline void ez80emac_txavail_process(FAR struct ez80emac_driver_s *priv) +static void ez80emac_txavail_work(FAR void *arg) { + FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)arg; + /* Ignore the notification if the interface is not yet up */ + net_lock(); if (priv->bifup) { /* Check if there is room in the hardware to hold another outgoing packet. */ @@ -2372,38 +2162,9 @@ static inline void ez80emac_txavail_process(FAR struct ez80emac_driver_s *priv) (void)devif_poll(&priv->dev, ez80emac_txpoll); } -} -/**************************************************************************** - * Function: ez80emac_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void ez80emac_txavail_work(FAR void *arg) -{ - FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - ez80emac_txavail_process(priv); - net_unlock(state); + net_unlock(); } -#endif /**************************************************************************** * Function: ez80emac_txavail @@ -2428,7 +2189,6 @@ static int ez80emac_txavail(FAR struct net_driver_s *dev) { FAR struct ez80emac_driver_s *priv = (FAR struct ez80emac_driver_s *)dev->d_private; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions and we will have to ignore the Tx * availability action. @@ -2441,21 +2201,6 @@ static int ez80emac_txavail(FAR struct net_driver_s *dev) work_queue(ETHWORK, &priv->syswork, ez80emac_txavail_work, priv, 0); } -#else - irqstate_t flags; - - /* Disable interrupts because this function may be called from interrupt - * level processing. - */ - - flags = enter_critical_section(); - - /* Perform the out-of-cycle poll now */ - - ez80emac_txavail_process(priv); - leave_critical_section(flags); -#endif - return OK; } diff --git a/configs/c5471evm/httpd/defconfig b/configs/c5471evm/httpd/defconfig index a9b069c742..86eb3afb03 100644 --- a/configs/c5471evm/httpd/defconfig +++ b/configs/c5471evm/httpd/defconfig @@ -477,7 +477,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/c5471evm/nettest/defconfig b/configs/c5471evm/nettest/defconfig index 2e7f35e1fb..ec8f1de744 100644 --- a/configs/c5471evm/nettest/defconfig +++ b/configs/c5471evm/nettest/defconfig @@ -470,7 +470,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/c5471evm/nsh/defconfig b/configs/c5471evm/nsh/defconfig index 96874ffa0f..8608b84420 100644 --- a/configs/c5471evm/nsh/defconfig +++ b/configs/c5471evm/nsh/defconfig @@ -478,7 +478,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/cloudctrl/nsh/defconfig b/configs/cloudctrl/nsh/defconfig index 5a0edc77d7..41f4db58a8 100644 --- a/configs/cloudctrl/nsh/defconfig +++ b/configs/cloudctrl/nsh/defconfig @@ -915,7 +915,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/dk-tm4c129x/README.txt b/configs/dk-tm4c129x/README.txt index 3ef95b3e26..bf81eb4f73 100644 --- a/configs/dk-tm4c129x/README.txt +++ b/configs/dk-tm4c129x/README.txt @@ -226,7 +226,6 @@ Networking Support Networking Support CONFIG_NET=y : Enable Neworking CONFIG_NET_ETHERNET=y : Support Ethernet data link - CONFIG_NET_NOINTS=y : Should operative at non-interrupt level CONFIG_NET_SOCKOPTS=y : Enable socket operations CONFIG_NET_ETH_MTU=590 : Maximum packet size (MTU) 1518 is more standard CONFIG_NET_ETH_TCP_RECVWNDO=536 : Should be the same as CONFIG_NET_ETH_MTU diff --git a/configs/dk-tm4c129x/ipv6/defconfig b/configs/dk-tm4c129x/ipv6/defconfig index 8174d2adba..7e6a993b1d 100644 --- a/configs/dk-tm4c129x/ipv6/defconfig +++ b/configs/dk-tm4c129x/ipv6/defconfig @@ -676,7 +676,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/dk-tm4c129x/nsh/defconfig b/configs/dk-tm4c129x/nsh/defconfig index 56660ab1f5..741b7af168 100644 --- a/configs/dk-tm4c129x/nsh/defconfig +++ b/configs/dk-tm4c129x/nsh/defconfig @@ -678,7 +678,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/eagle100/httpd/defconfig b/configs/eagle100/httpd/defconfig index 6ff58e8c7d..2d955bbcab 100644 --- a/configs/eagle100/httpd/defconfig +++ b/configs/eagle100/httpd/defconfig @@ -609,7 +609,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/eagle100/nettest/defconfig b/configs/eagle100/nettest/defconfig index a0aa41a4d4..7cf58f403b 100644 --- a/configs/eagle100/nettest/defconfig +++ b/configs/eagle100/nettest/defconfig @@ -601,7 +601,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/eagle100/nsh/defconfig b/configs/eagle100/nsh/defconfig index ca7b4701fe..af982ff487 100644 --- a/configs/eagle100/nsh/defconfig +++ b/configs/eagle100/nsh/defconfig @@ -643,7 +643,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/eagle100/thttpd/defconfig b/configs/eagle100/thttpd/defconfig index 9e597ffb4d..05d4be5f54 100644 --- a/configs/eagle100/thttpd/defconfig +++ b/configs/eagle100/thttpd/defconfig @@ -597,7 +597,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/ekk-lm3s9b96/nsh/defconfig b/configs/ekk-lm3s9b96/nsh/defconfig index 080a0c5680..fb38935f6e 100644 --- a/configs/ekk-lm3s9b96/nsh/defconfig +++ b/configs/ekk-lm3s9b96/nsh/defconfig @@ -632,7 +632,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/ez80f910200zco/dhcpd/defconfig b/configs/ez80f910200zco/dhcpd/defconfig index 126bf74026..72dcc5ecfa 100644 --- a/configs/ez80f910200zco/dhcpd/defconfig +++ b/configs/ez80f910200zco/dhcpd/defconfig @@ -500,7 +500,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/ez80f910200zco/httpd/defconfig b/configs/ez80f910200zco/httpd/defconfig index 4177c0bc9b..b74d62ba78 100644 --- a/configs/ez80f910200zco/httpd/defconfig +++ b/configs/ez80f910200zco/httpd/defconfig @@ -509,7 +509,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/ez80f910200zco/nettest/defconfig b/configs/ez80f910200zco/nettest/defconfig index 99250b29d5..e4fe5af40f 100644 --- a/configs/ez80f910200zco/nettest/defconfig +++ b/configs/ez80f910200zco/nettest/defconfig @@ -501,7 +501,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/ez80f910200zco/nsh/defconfig b/configs/ez80f910200zco/nsh/defconfig index 04dda2443e..2b23512921 100644 --- a/configs/ez80f910200zco/nsh/defconfig +++ b/configs/ez80f910200zco/nsh/defconfig @@ -512,7 +512,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/ez80f910200zco/poll/defconfig b/configs/ez80f910200zco/poll/defconfig index 770d89d9bb..a7b22914de 100644 --- a/configs/ez80f910200zco/poll/defconfig +++ b/configs/ez80f910200zco/poll/defconfig @@ -511,7 +511,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/fire-stm32v2/nsh/defconfig b/configs/fire-stm32v2/nsh/defconfig index 8bc4620548..f2c01e8a69 100644 --- a/configs/fire-stm32v2/nsh/defconfig +++ b/configs/fire-stm32v2/nsh/defconfig @@ -971,7 +971,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/freedom-k64f/README.txt b/configs/freedom-k64f/README.txt index 4dd8932aad..3ea647ad58 100644 --- a/configs/freedom-k64f/README.txt +++ b/configs/freedom-k64f/README.txt @@ -193,7 +193,6 @@ Networking Support Networking Support CONFIG_NET=y : Enable Neworking CONFIG_NET_ETHERNET=y : Support Ethernet data link - CONFIG_NET_NOINTS=y : Should operative at non-interrupt level CONFIG_NET_SOCKOPTS=y : Enable socket operations CONFIG_NET_ETH_MTU=590 : Maximum packet size (MTU) 1518 is more standard CONFIG_NET_ETH_TCP_RECVWNDO=536 : Should be the same as CONFIG_NET_ETH_MTU diff --git a/configs/freedom-k64f/netnsh/defconfig b/configs/freedom-k64f/netnsh/defconfig index 94d319b5b7..d04232162c 100644 --- a/configs/freedom-k64f/netnsh/defconfig +++ b/configs/freedom-k64f/netnsh/defconfig @@ -644,7 +644,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/lincoln60/netnsh/defconfig b/configs/lincoln60/netnsh/defconfig index 137e5f3621..0d956981f6 100644 --- a/configs/lincoln60/netnsh/defconfig +++ b/configs/lincoln60/netnsh/defconfig @@ -623,7 +623,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/lincoln60/thttpd-binfs/defconfig b/configs/lincoln60/thttpd-binfs/defconfig index 8a0a858cd2..abfe74e562 100644 --- a/configs/lincoln60/thttpd-binfs/defconfig +++ b/configs/lincoln60/thttpd-binfs/defconfig @@ -602,7 +602,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/lm3s6432-s2e/nsh/defconfig b/configs/lm3s6432-s2e/nsh/defconfig index f69161c733..92f2f68964 100644 --- a/configs/lm3s6432-s2e/nsh/defconfig +++ b/configs/lm3s6432-s2e/nsh/defconfig @@ -623,7 +623,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/lm3s6965-ek/discover/defconfig b/configs/lm3s6965-ek/discover/defconfig index f11ccb5d9d..91a26e61e7 100644 --- a/configs/lm3s6965-ek/discover/defconfig +++ b/configs/lm3s6965-ek/discover/defconfig @@ -637,7 +637,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/lm3s6965-ek/nsh/defconfig b/configs/lm3s6965-ek/nsh/defconfig index f11ccb5d9d..91a26e61e7 100644 --- a/configs/lm3s6965-ek/nsh/defconfig +++ b/configs/lm3s6965-ek/nsh/defconfig @@ -637,7 +637,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/lm3s6965-ek/tcpecho/defconfig b/configs/lm3s6965-ek/tcpecho/defconfig index 8a2f08ebc5..6945c7a71f 100644 --- a/configs/lm3s6965-ek/tcpecho/defconfig +++ b/configs/lm3s6965-ek/tcpecho/defconfig @@ -607,7 +607,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/lm3s8962-ek/nsh/defconfig b/configs/lm3s8962-ek/nsh/defconfig index c631ca1bce..45be5effd8 100644 --- a/configs/lm3s8962-ek/nsh/defconfig +++ b/configs/lm3s8962-ek/nsh/defconfig @@ -647,7 +647,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/lpcxpresso-lpc1768/dhcpd/defconfig b/configs/lpcxpresso-lpc1768/dhcpd/defconfig index 7b0c989057..8df48ef27e 100644 --- a/configs/lpcxpresso-lpc1768/dhcpd/defconfig +++ b/configs/lpcxpresso-lpc1768/dhcpd/defconfig @@ -591,7 +591,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/lpcxpresso-lpc1768/nsh/defconfig b/configs/lpcxpresso-lpc1768/nsh/defconfig index 6cf2f99378..1ebf3b8ae9 100644 --- a/configs/lpcxpresso-lpc1768/nsh/defconfig +++ b/configs/lpcxpresso-lpc1768/nsh/defconfig @@ -663,7 +663,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/lpcxpresso-lpc1768/thttpd/defconfig b/configs/lpcxpresso-lpc1768/thttpd/defconfig index 23256edfa7..4d16ce1734 100644 --- a/configs/lpcxpresso-lpc1768/thttpd/defconfig +++ b/configs/lpcxpresso-lpc1768/thttpd/defconfig @@ -594,7 +594,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/misoc/hello/defconfig b/configs/misoc/hello/defconfig index 4bda51d016..b785983a23 100644 --- a/configs/misoc/hello/defconfig +++ b/configs/misoc/hello/defconfig @@ -481,7 +481,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/moxa/nsh/defconfig b/configs/moxa/nsh/defconfig index d57afb29b6..ca520d5eb9 100644 --- a/configs/moxa/nsh/defconfig +++ b/configs/moxa/nsh/defconfig @@ -514,7 +514,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/ntosd-dm320/nettest/defconfig b/configs/ntosd-dm320/nettest/defconfig index b1f9e6730d..bd68dc951a 100644 --- a/configs/ntosd-dm320/nettest/defconfig +++ b/configs/ntosd-dm320/nettest/defconfig @@ -509,7 +509,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/ntosd-dm320/nsh/defconfig b/configs/ntosd-dm320/nsh/defconfig index 9c16b857f5..a2c9d13163 100644 --- a/configs/ntosd-dm320/nsh/defconfig +++ b/configs/ntosd-dm320/nsh/defconfig @@ -525,7 +525,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/ntosd-dm320/poll/defconfig b/configs/ntosd-dm320/poll/defconfig index 5eac34cfe9..99ac30997c 100644 --- a/configs/ntosd-dm320/poll/defconfig +++ b/configs/ntosd-dm320/poll/defconfig @@ -520,7 +520,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/ntosd-dm320/thttpd/defconfig b/configs/ntosd-dm320/thttpd/defconfig index d6a53fa998..b9cc758765 100644 --- a/configs/ntosd-dm320/thttpd/defconfig +++ b/configs/ntosd-dm320/thttpd/defconfig @@ -513,7 +513,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/ntosd-dm320/udp/defconfig b/configs/ntosd-dm320/udp/defconfig index 01d6266cf2..b34efac745 100644 --- a/configs/ntosd-dm320/udp/defconfig +++ b/configs/ntosd-dm320/udp/defconfig @@ -508,7 +508,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/ntosd-dm320/webserver/defconfig b/configs/ntosd-dm320/webserver/defconfig index d20b40829f..40ff3fe1bf 100644 --- a/configs/ntosd-dm320/webserver/defconfig +++ b/configs/ntosd-dm320/webserver/defconfig @@ -516,7 +516,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/olimex-lpc1766stk/ftpc/defconfig b/configs/olimex-lpc1766stk/ftpc/defconfig index 306ef5d70e..cdb8d28d0a 100644 --- a/configs/olimex-lpc1766stk/ftpc/defconfig +++ b/configs/olimex-lpc1766stk/ftpc/defconfig @@ -630,7 +630,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/olimex-lpc1766stk/hidmouse/defconfig b/configs/olimex-lpc1766stk/hidmouse/defconfig index 93c3572e91..82273f0771 100644 --- a/configs/olimex-lpc1766stk/hidmouse/defconfig +++ b/configs/olimex-lpc1766stk/hidmouse/defconfig @@ -620,7 +620,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/olimex-lpc1766stk/nettest/defconfig b/configs/olimex-lpc1766stk/nettest/defconfig index cf81bb61a9..0e78b00259 100644 --- a/configs/olimex-lpc1766stk/nettest/defconfig +++ b/configs/olimex-lpc1766stk/nettest/defconfig @@ -592,7 +592,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/olimex-lpc1766stk/nsh/defconfig b/configs/olimex-lpc1766stk/nsh/defconfig index e228e36701..f0989e352b 100644 --- a/configs/olimex-lpc1766stk/nsh/defconfig +++ b/configs/olimex-lpc1766stk/nsh/defconfig @@ -632,7 +632,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/olimex-lpc1766stk/slip-httpd/defconfig b/configs/olimex-lpc1766stk/slip-httpd/defconfig index 1c7e6b2ede..ad62a7308b 100644 --- a/configs/olimex-lpc1766stk/slip-httpd/defconfig +++ b/configs/olimex-lpc1766stk/slip-httpd/defconfig @@ -558,7 +558,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/olimex-lpc1766stk/thttpd-binfs/defconfig b/configs/olimex-lpc1766stk/thttpd-binfs/defconfig index d3135f2794..61584a923f 100644 --- a/configs/olimex-lpc1766stk/thttpd-binfs/defconfig +++ b/configs/olimex-lpc1766stk/thttpd-binfs/defconfig @@ -602,7 +602,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig b/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig index d65819e802..a3f8045c97 100644 --- a/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig +++ b/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig @@ -595,7 +595,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/olimex-lpc1766stk/zmodem/defconfig b/configs/olimex-lpc1766stk/zmodem/defconfig index 4866dca396..9ce6ae44c0 100644 --- a/configs/olimex-lpc1766stk/zmodem/defconfig +++ b/configs/olimex-lpc1766stk/zmodem/defconfig @@ -647,7 +647,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/olimex-stm32-e407/discover/defconfig b/configs/olimex-stm32-e407/discover/defconfig index dd23f1554d..60f0cc16e5 100644 --- a/configs/olimex-stm32-e407/discover/defconfig +++ b/configs/olimex-stm32-e407/discover/defconfig @@ -897,7 +897,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/olimex-stm32-e407/netnsh/defconfig b/configs/olimex-stm32-e407/netnsh/defconfig index 6ae452f562..72c2701589 100644 --- a/configs/olimex-stm32-e407/netnsh/defconfig +++ b/configs/olimex-stm32-e407/netnsh/defconfig @@ -899,7 +899,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/olimex-stm32-e407/telnetd/defconfig b/configs/olimex-stm32-e407/telnetd/defconfig index 6b17db7614..10a34c4e92 100644 --- a/configs/olimex-stm32-e407/telnetd/defconfig +++ b/configs/olimex-stm32-e407/telnetd/defconfig @@ -899,7 +899,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/olimex-stm32-e407/webserver/defconfig b/configs/olimex-stm32-e407/webserver/defconfig index 45d097fc16..2e78b26022 100644 --- a/configs/olimex-stm32-e407/webserver/defconfig +++ b/configs/olimex-stm32-e407/webserver/defconfig @@ -897,7 +897,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/olimex-stm32-p107/nsh/defconfig b/configs/olimex-stm32-p107/nsh/defconfig index c5bc04f46d..962d6ca2d9 100644 --- a/configs/olimex-stm32-p107/nsh/defconfig +++ b/configs/olimex-stm32-p107/nsh/defconfig @@ -905,7 +905,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/olimex-stm32-p207/nsh/defconfig b/configs/olimex-stm32-p207/nsh/defconfig index 2b65965724..86e6c4216d 100644 --- a/configs/olimex-stm32-p207/nsh/defconfig +++ b/configs/olimex-stm32-p207/nsh/defconfig @@ -949,7 +949,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/olimex-strp711/nettest/defconfig b/configs/olimex-strp711/nettest/defconfig index 97e3515f2a..d89e0bf5d3 100644 --- a/configs/olimex-strp711/nettest/defconfig +++ b/configs/olimex-strp711/nettest/defconfig @@ -551,7 +551,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/pic32mx-starterkit/nsh2/defconfig b/configs/pic32mx-starterkit/nsh2/defconfig index 1805838d32..7768166473 100644 --- a/configs/pic32mx-starterkit/nsh2/defconfig +++ b/configs/pic32mx-starterkit/nsh2/defconfig @@ -673,7 +673,6 @@ CONFIG_RAMLOG_SYSLOG=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/pic32mx7mmb/nsh/defconfig b/configs/pic32mx7mmb/nsh/defconfig index 5f406d3360..aadcf0e895 100644 --- a/configs/pic32mx7mmb/nsh/defconfig +++ b/configs/pic32mx7mmb/nsh/defconfig @@ -736,7 +736,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/sam4e-ek/nsh/defconfig b/configs/sam4e-ek/nsh/defconfig index a2a5a4e5f8..fc74521d7b 100644 --- a/configs/sam4e-ek/nsh/defconfig +++ b/configs/sam4e-ek/nsh/defconfig @@ -736,7 +736,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/sam4e-ek/nxwm/defconfig b/configs/sam4e-ek/nxwm/defconfig index 734743e820..e886128820 100644 --- a/configs/sam4e-ek/nxwm/defconfig +++ b/configs/sam4e-ek/nxwm/defconfig @@ -795,7 +795,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/sam4e-ek/usbnsh/defconfig b/configs/sam4e-ek/usbnsh/defconfig index 572206bc8b..af76f90700 100644 --- a/configs/sam4e-ek/usbnsh/defconfig +++ b/configs/sam4e-ek/usbnsh/defconfig @@ -776,7 +776,6 @@ CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/sama5d3-xplained/bridge/defconfig b/configs/sama5d3-xplained/bridge/defconfig index ea5c1c4fc6..51c672c066 100644 --- a/configs/sama5d3-xplained/bridge/defconfig +++ b/configs/sama5d3-xplained/bridge/defconfig @@ -698,7 +698,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/sama5d4-ek/bridge/defconfig b/configs/sama5d4-ek/bridge/defconfig index 8e650abaad..134be3f686 100644 --- a/configs/sama5d4-ek/bridge/defconfig +++ b/configs/sama5d4-ek/bridge/defconfig @@ -725,7 +725,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/sama5d4-ek/ipv6/defconfig b/configs/sama5d4-ek/ipv6/defconfig index 2d2a202cc5..9f9c9506be 100644 --- a/configs/sama5d4-ek/ipv6/defconfig +++ b/configs/sama5d4-ek/ipv6/defconfig @@ -908,7 +908,6 @@ CONFIG_RAMLOG_SYSLOG=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/sama5d4-ek/nsh/defconfig b/configs/sama5d4-ek/nsh/defconfig index 9857438af8..ef3a9884b4 100644 --- a/configs/sama5d4-ek/nsh/defconfig +++ b/configs/sama5d4-ek/nsh/defconfig @@ -910,7 +910,6 @@ CONFIG_RAMLOG_SYSLOG=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/sama5d4-ek/nxwm/defconfig b/configs/sama5d4-ek/nxwm/defconfig index 56265b311b..c13d4c27b0 100644 --- a/configs/sama5d4-ek/nxwm/defconfig +++ b/configs/sama5d4-ek/nxwm/defconfig @@ -879,7 +879,6 @@ CONFIG_RAMLOG_SYSLOG=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/same70-xplained/README.txt b/configs/same70-xplained/README.txt index 7d31d20e9d..ddd198f68e 100644 --- a/configs/same70-xplained/README.txt +++ b/configs/same70-xplained/README.txt @@ -388,7 +388,6 @@ Selecting the GMAC peripheral Networking Support CONFIG_NET=y : Enable Neworking - CONFIG_NET_NOINTS=y : Use the work queue, not interrupts for processing CONFIG_NET_SOCKOPTS=y : Enable socket operations CONFIG_NET_ETH_MTU=562 : Maximum packet size (MTU) 1518 is more standard CONFIG_NET_ETH_TCP_RECVWNDO=562 : Should be the same as CONFIG_NET_ETH_MTU diff --git a/configs/same70-xplained/netnsh/defconfig b/configs/same70-xplained/netnsh/defconfig index 57c0c01323..1b1b7be836 100644 --- a/configs/same70-xplained/netnsh/defconfig +++ b/configs/same70-xplained/netnsh/defconfig @@ -768,7 +768,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/samv71-xult/README.txt b/configs/samv71-xult/README.txt index f84223d5b8..e370dabc72 100644 --- a/configs/samv71-xult/README.txt +++ b/configs/samv71-xult/README.txt @@ -704,7 +704,6 @@ Selecting the GMAC peripheral Networking Support CONFIG_NET=y : Enable Neworking - CONFIG_NET_NOINTS=y : Use the work queue, not interrupts for processing CONFIG_NET_SOCKOPTS=y : Enable socket operations CONFIG_NET_ETH_MTU=562 : Maximum packet size (MTU) 1518 is more standard CONFIG_NET_ETH_TCP_RECVWNDO=562 : Should be the same as CONFIG_NET_ETH_MTU diff --git a/configs/samv71-xult/netnsh/defconfig b/configs/samv71-xult/netnsh/defconfig index 24f50e8e68..6a005c6e5d 100644 --- a/configs/samv71-xult/netnsh/defconfig +++ b/configs/samv71-xult/netnsh/defconfig @@ -771,7 +771,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/samv71-xult/vnc/defconfig b/configs/samv71-xult/vnc/defconfig index a37393cef6..90d26f1600 100644 --- a/configs/samv71-xult/vnc/defconfig +++ b/configs/samv71-xult/vnc/defconfig @@ -772,7 +772,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/samv71-xult/vnxwm/defconfig b/configs/samv71-xult/vnxwm/defconfig index b3fa15e306..64ebea05db 100644 --- a/configs/samv71-xult/vnxwm/defconfig +++ b/configs/samv71-xult/vnxwm/defconfig @@ -775,7 +775,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/shenzhou/nsh/defconfig b/configs/shenzhou/nsh/defconfig index 5247928fbd..1fc93461f1 100644 --- a/configs/shenzhou/nsh/defconfig +++ b/configs/shenzhou/nsh/defconfig @@ -900,7 +900,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/shenzhou/nxwm/defconfig b/configs/shenzhou/nxwm/defconfig index 31a95d3293..093f2bd80c 100644 --- a/configs/shenzhou/nxwm/defconfig +++ b/configs/shenzhou/nxwm/defconfig @@ -968,7 +968,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/shenzhou/thttpd/defconfig b/configs/shenzhou/thttpd/defconfig index 4c2456192b..defbcf3cf8 100644 --- a/configs/shenzhou/thttpd/defconfig +++ b/configs/shenzhou/thttpd/defconfig @@ -931,7 +931,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/sim/nettest/defconfig b/configs/sim/nettest/defconfig index aebf077586..7bce3f6cb1 100644 --- a/configs/sim/nettest/defconfig +++ b/configs/sim/nettest/defconfig @@ -388,7 +388,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/sim/udgram/defconfig b/configs/sim/udgram/defconfig index ae87965d95..e85867d7cb 100644 --- a/configs/sim/udgram/defconfig +++ b/configs/sim/udgram/defconfig @@ -402,7 +402,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/sim/ustream/defconfig b/configs/sim/ustream/defconfig index fabbc20ff1..f495bcea50 100644 --- a/configs/sim/ustream/defconfig +++ b/configs/sim/ustream/defconfig @@ -402,7 +402,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/stm3220g-eval/dhcpd/defconfig b/configs/stm3220g-eval/dhcpd/defconfig index ec11cf50fd..92d9dac8c8 100644 --- a/configs/stm3220g-eval/dhcpd/defconfig +++ b/configs/stm3220g-eval/dhcpd/defconfig @@ -872,7 +872,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/stm3220g-eval/nettest/defconfig b/configs/stm3220g-eval/nettest/defconfig index 7867ba3f49..e66a156f92 100644 --- a/configs/stm3220g-eval/nettest/defconfig +++ b/configs/stm3220g-eval/nettest/defconfig @@ -872,7 +872,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/stm3220g-eval/nsh/defconfig b/configs/stm3220g-eval/nsh/defconfig index 7075a4c735..ce18adbe6d 100644 --- a/configs/stm3220g-eval/nsh/defconfig +++ b/configs/stm3220g-eval/nsh/defconfig @@ -939,7 +939,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/stm3220g-eval/nsh2/defconfig b/configs/stm3220g-eval/nsh2/defconfig index 1ed45de59e..69fb3cd888 100644 --- a/configs/stm3220g-eval/nsh2/defconfig +++ b/configs/stm3220g-eval/nsh2/defconfig @@ -940,7 +940,6 @@ CONFIG_RAMLOG_SYSLOG=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/stm3220g-eval/nxwm/defconfig b/configs/stm3220g-eval/nxwm/defconfig index 226185ff1a..fa8ab410a4 100644 --- a/configs/stm3220g-eval/nxwm/defconfig +++ b/configs/stm3220g-eval/nxwm/defconfig @@ -989,7 +989,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/stm3220g-eval/telnetd/defconfig b/configs/stm3220g-eval/telnetd/defconfig index 3b2691aac1..4af8ce18ac 100644 --- a/configs/stm3220g-eval/telnetd/defconfig +++ b/configs/stm3220g-eval/telnetd/defconfig @@ -874,7 +874,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/stm3240g-eval/dhcpd/defconfig b/configs/stm3240g-eval/dhcpd/defconfig index eb100332f9..0f0b7fb1da 100644 --- a/configs/stm3240g-eval/dhcpd/defconfig +++ b/configs/stm3240g-eval/dhcpd/defconfig @@ -876,7 +876,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/stm3240g-eval/discover/defconfig b/configs/stm3240g-eval/discover/defconfig index df9f2b18ee..18210f6a9d 100644 --- a/configs/stm3240g-eval/discover/defconfig +++ b/configs/stm3240g-eval/discover/defconfig @@ -899,7 +899,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/stm3240g-eval/nettest/defconfig b/configs/stm3240g-eval/nettest/defconfig index 9f24daa36f..e64f241e19 100644 --- a/configs/stm3240g-eval/nettest/defconfig +++ b/configs/stm3240g-eval/nettest/defconfig @@ -876,7 +876,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/stm3240g-eval/nsh/defconfig b/configs/stm3240g-eval/nsh/defconfig index 1ced4eac01..0bb15260d3 100644 --- a/configs/stm3240g-eval/nsh/defconfig +++ b/configs/stm3240g-eval/nsh/defconfig @@ -917,7 +917,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/stm3240g-eval/nsh2/defconfig b/configs/stm3240g-eval/nsh2/defconfig index 446ecdaba8..6656348e26 100644 --- a/configs/stm3240g-eval/nsh2/defconfig +++ b/configs/stm3240g-eval/nsh2/defconfig @@ -944,7 +944,6 @@ CONFIG_RAMLOG_SYSLOG=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/stm3240g-eval/nxterm/defconfig b/configs/stm3240g-eval/nxterm/defconfig index 7d5aa49b05..da3ffd42ab 100644 --- a/configs/stm3240g-eval/nxterm/defconfig +++ b/configs/stm3240g-eval/nxterm/defconfig @@ -958,7 +958,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/stm3240g-eval/nxwm/defconfig b/configs/stm3240g-eval/nxwm/defconfig index ab92f2b9c3..eab7420dcf 100644 --- a/configs/stm3240g-eval/nxwm/defconfig +++ b/configs/stm3240g-eval/nxwm/defconfig @@ -986,7 +986,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/stm3240g-eval/telnetd/defconfig b/configs/stm3240g-eval/telnetd/defconfig index 6882cd6d06..07ad188e92 100644 --- a/configs/stm3240g-eval/telnetd/defconfig +++ b/configs/stm3240g-eval/telnetd/defconfig @@ -878,7 +878,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/stm3240g-eval/webserver/defconfig b/configs/stm3240g-eval/webserver/defconfig index 076059622c..856364d415 100644 --- a/configs/stm3240g-eval/webserver/defconfig +++ b/configs/stm3240g-eval/webserver/defconfig @@ -938,7 +938,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/stm3240g-eval/xmlrpc/defconfig b/configs/stm3240g-eval/xmlrpc/defconfig index 8a45ee1945..4cee1e1d72 100644 --- a/configs/stm3240g-eval/xmlrpc/defconfig +++ b/configs/stm3240g-eval/xmlrpc/defconfig @@ -895,7 +895,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/stm32butterfly2/nshnet/defconfig b/configs/stm32butterfly2/nshnet/defconfig index 05b2ab9f0a..b1321f4ee7 100644 --- a/configs/stm32butterfly2/nshnet/defconfig +++ b/configs/stm32butterfly2/nshnet/defconfig @@ -942,7 +942,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/stm32f4discovery/ipv6/defconfig b/configs/stm32f4discovery/ipv6/defconfig index be3b59a928..b2fd121eeb 100644 --- a/configs/stm32f4discovery/ipv6/defconfig +++ b/configs/stm32f4discovery/ipv6/defconfig @@ -946,7 +946,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/stm32f4discovery/netnsh/defconfig b/configs/stm32f4discovery/netnsh/defconfig index ff2ce11f27..61d20ad657 100644 --- a/configs/stm32f4discovery/netnsh/defconfig +++ b/configs/stm32f4discovery/netnsh/defconfig @@ -948,7 +948,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/tm4c1294-launchpad/ipv6/defconfig b/configs/tm4c1294-launchpad/ipv6/defconfig index 0ec47e4059..936957248b 100644 --- a/configs/tm4c1294-launchpad/ipv6/defconfig +++ b/configs/tm4c1294-launchpad/ipv6/defconfig @@ -640,7 +640,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/tm4c1294-launchpad/nsh/defconfig b/configs/tm4c1294-launchpad/nsh/defconfig index 25a9cfe8b6..f2a84e52b8 100644 --- a/configs/tm4c1294-launchpad/nsh/defconfig +++ b/configs/tm4c1294-launchpad/nsh/defconfig @@ -642,7 +642,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y # CONFIG_ARCH_HAVE_PHY is not set CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/u-blox-c027/nsh/defconfig b/configs/u-blox-c027/nsh/defconfig index 588447e164..c98cfdac70 100644 --- a/configs/u-blox-c027/nsh/defconfig +++ b/configs/u-blox-c027/nsh/defconfig @@ -679,7 +679,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/viewtool-stm32f107/netnsh/defconfig b/configs/viewtool-stm32f107/netnsh/defconfig index 9fece336b9..466b2d7009 100644 --- a/configs/viewtool-stm32f107/netnsh/defconfig +++ b/configs/viewtool-stm32f107/netnsh/defconfig @@ -874,7 +874,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -# CONFIG_NET_NOINTS is not set # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/zkit-arm-1769/hello/defconfig b/configs/zkit-arm-1769/hello/defconfig index 38855218b9..b6b968fe33 100644 --- a/configs/zkit-arm-1769/hello/defconfig +++ b/configs/zkit-arm-1769/hello/defconfig @@ -592,7 +592,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/zkit-arm-1769/nsh/defconfig b/configs/zkit-arm-1769/nsh/defconfig index d7480266d0..481f472b21 100644 --- a/configs/zkit-arm-1769/nsh/defconfig +++ b/configs/zkit-arm-1769/nsh/defconfig @@ -632,7 +632,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/zkit-arm-1769/nxhello/defconfig b/configs/zkit-arm-1769/nxhello/defconfig index 8af1755ddb..be2211450a 100644 --- a/configs/zkit-arm-1769/nxhello/defconfig +++ b/configs/zkit-arm-1769/nxhello/defconfig @@ -670,7 +670,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/configs/zkit-arm-1769/thttpd/defconfig b/configs/zkit-arm-1769/thttpd/defconfig index f251f0a05b..026d759b45 100644 --- a/configs/zkit-arm-1769/thttpd/defconfig +++ b/configs/zkit-arm-1769/thttpd/defconfig @@ -595,7 +595,6 @@ CONFIG_SYSLOG_CONSOLE=y CONFIG_ARCH_HAVE_NET=y CONFIG_ARCH_HAVE_PHY=y CONFIG_NET=y -CONFIG_NET_NOINTS=y # CONFIG_NET_PROMISCUOUS is not set # diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 96d012a04d..83213465e4 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -9,12 +9,9 @@ config NETDEV_LOOPBACK bool default n if !NET_LOOPBACK default y if NET_LOOPBACK - select NET_NOINTS select ARCH_HAVE_NETDEV_STATISTICS ---help--- - Add support for the local network loopback device, lo. Any additional - networking devices that are enabled must be compatible with - CONFIG_NET_NOINTS. + Add support for the local network loopback device, lo. if NETDEV_LOOPBACK diff --git a/drivers/net/dm90x0.c b/drivers/net/dm90x0.c index 6439d7494a..61c22a929b 100644 --- a/drivers/net/dm90x0.c +++ b/drivers/net/dm90x0.c @@ -65,11 +65,7 @@ #include #include #include - -#ifdef CONFIG_NET_NOINTS -# include -#endif - +#include #include #include @@ -84,13 +80,12 @@ * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +#if !defined(CONFIG_SCHED_WORKQUEUE) # error Work queue support is required in this configuration (CONFIG_SCHED_WORKQUEUE) -#endif +#else -/* Use the low priority work queue if possible */ + /* Use the low priority work queue if possible */ -#if defined(CONFIG_SCHED_WORKQUEUE) # if defined(CONFIG_DM9X_HPWORK) # define ETHWORK HPWORK # elif defined(CONFIG_DM9X_LPWORK) @@ -326,9 +321,7 @@ struct dm9x_driver_s uint8_t ncrxpackets; /* Number of continuous rx packets */ WDOG_ID dm_txpoll; /* TX poll timer */ WDOG_ID dm_txtimeout; /* TX timeout timer */ -#ifdef CONFIG_NET_NOINTS struct work_s dm_work; /* For deferring work to the work queue */ -#endif /* Mode-dependent function to move data in 8/16/32 I/O modes */ @@ -391,24 +384,15 @@ static int dm9x_txpoll(struct net_driver_s *dev); static void dm9x_receive(struct dm9x_driver_s *priv); static void dm9x_txdone(struct dm9x_driver_s *priv); -static inline void dm9x_interrupt_process(FAR struct dm9x_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void dm9x_interrupt_work(FAR void *arg); -#endif static int dm9x_interrupt(int irq, FAR void *context); /* Watchdog timer expirations */ -static inline void dm9x_txtimeout_process(FAR struct dm9x_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void dm9x_txtimeout_work(FAR void *arg); -#endif static void dm9x_txtimeout_expiry(int argc, uint32_t arg, ...); -static inline void dm9x_poll_process(FAR struct dm9x_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void dm9x_poll_work(FAR void *arg); -#endif static void dm9x_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ @@ -416,10 +400,7 @@ static void dm9x_poll_expiry(int argc, uint32_t arg, ...); static int dm9x_ifup(struct net_driver_s *dev); static int dm9x_ifdown(struct net_driver_s *dev); -static inline void dm9x_txavail_process(FAR struct dm9x_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void dm9x_txavail_work(FAR void *arg); -#endif static int dm9x_txavail(struct net_driver_s *dev); #ifdef CONFIG_NET_IGMP @@ -1122,29 +1103,33 @@ static void dm9x_txdone(struct dm9x_driver_s *priv) } /**************************************************************************** - * Function: dm9x_interrupt_process + * Function: dm9x_interrupt_work * * Description: - * Interrupt processing. This may be performed either within the interrupt - * handler or on the worker thread, depending upon the configuration + * Perform interrupt related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: * The network is locked. * ****************************************************************************/ -static inline void dm9x_interrupt_process(FAR struct dm9x_driver_s *priv) +static void dm9x_interrupt_work(FAR void *arg) { + FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)arg; uint8_t isr; uint8_t save; int i; + /* Process pending Ethernet interrupts */ + + net_lock(); + /* Save previous register address */ save = (uint8_t)DM9X_INDEX; @@ -1229,42 +1214,12 @@ static inline void dm9x_interrupt_process(FAR struct dm9x_driver_s *priv) /* Restore previous register address */ DM9X_INDEX = save; -} - -/**************************************************************************** - * Function: dm9x_interrupt_work - * - * Description: - * Perform interrupt related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() was called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void dm9x_interrupt_work(FAR void *arg) -{ - FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - dm9x_interrupt_process(priv); - net_unlock(state); + net_unlock(); /* Re-enable Ethernet interrupts */ up_enable_irq(CONFIG_DM9X_IRQ); } -#endif /**************************************************************************** * Function: dm9x_interrupt @@ -1290,8 +1245,6 @@ static int dm9x_interrupt(int irq, FAR void *context) #else # error "Additional logic needed to support multiple interfaces" #endif - -#ifdef CONFIG_NET_NOINTS uint8_t isr; /* Disable further Ethernet interrupts. Because Ethernet interrupts are @@ -1321,39 +1274,35 @@ static int dm9x_interrupt(int irq, FAR void *context) /* Schedule to perform the interrupt processing on the worker thread. */ work_queue(ETHWORK, &priv->dm_work, dm9x_interrupt_work, priv, 0); - -#else - /* Process the interrupt now */ - - dm9x_interrupt_process(priv); -#endif - return OK; } /**************************************************************************** - * Function: dm9x_txtimeout_process + * Function: dm9x_txtimeout_work * * Description: - * Process a TX timeout. Called from the either the watchdog timer - * expiration logic or from the worker thread, depending upon the - * configuration. The timeout means that the last TX never completed. - * Reset the hardware and start again. + * Perform TX timeout related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success + * + * Assumptions: + * The network is locked. * ****************************************************************************/ -static inline void dm9x_txtimeout_process(FAR struct dm9x_driver_s *priv) +static void dm9x_txtimeout_work(FAR void *arg) { + FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)arg; + nerr("ERROR: TX timeout\n"); /* Increment statistics and dump debug info */ + net_lock(); NETDEV_TXTIMEOUTS(priv->dm_dev); ninfo(" TX packet count: %d\n", priv->dm_ntxpending); @@ -1369,39 +1318,9 @@ static inline void dm9x_txtimeout_process(FAR struct dm9x_driver_s *priv) /* Then poll the network for new XMIT data */ (void)devif_poll(&priv->dm_dev, dm9x_txpoll); + net_unlock(); } -/**************************************************************************** - * Function: dm9x_txtimeout_work - * - * Description: - * Perform TX timeout related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void dm9x_txtimeout_work(FAR void *arg) -{ - FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - dm9x_txtimeout_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: dm9x_txtimeout_expiry * @@ -1425,7 +1344,6 @@ static void dm9x_txtimeout_expiry(int argc, wdparm_t arg, ...) { FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race * conditions with interrupt work. There is still a potential race * condition with interrupt work that is already queued and in progress. @@ -1442,32 +1360,33 @@ static void dm9x_txtimeout_expiry(int argc, wdparm_t arg, ...) /* Schedule to perform the TX timeout processing on the worker thread. */ work_queue(ETHWORK, &priv->dm_work, dm9x_txtimeout_work, priv, 0); -#else - /* Process the timeout now */ - - dm9x_txtimeout_process(priv); -#endif } /**************************************************************************** - * Function: dm9x_poll_process + * Function: dm9x_poll_work * * Description: - * Perform the periodic poll. This may be called either from watchdog - * timer logic or from the worker thread, depending upon the configuration. + * Perform periodic polling from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: + * The network is locked. * ****************************************************************************/ -static inline void dm9x_poll_process(FAR struct dm9x_driver_s *priv) +static void dm9x_poll_work(FAR void *arg) { + FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)arg; + + /* Perform the poll */ + + net_lock(); + /* If the number of contiguous RX packets exceeds a threshold, reset the counter and * re-enable RX interrupts */ @@ -1493,39 +1412,9 @@ static inline void dm9x_poll_process(FAR struct dm9x_driver_s *priv) (void)wd_start(priv->dm_txpoll, DM9X_WDDELAY, dm9x_poll_expiry, 1, (wdparm_t)priv); + net_unlock(); } -/**************************************************************************** - * Function: dm9x_poll_work - * - * Description: - * Perform periodic polling from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void dm9x_poll_work(FAR void *arg) -{ - FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - dm9x_poll_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: dm9x_poll_expiry * @@ -1548,7 +1437,6 @@ static void dm9x_poll_expiry(int argc, wdparm_t arg, ...) { FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions. */ @@ -1567,12 +1455,6 @@ static void dm9x_poll_expiry(int argc, wdparm_t arg, ...) (void)wd_start(priv->dm_txpoll, DM9X_WDDELAY, dm9x_poll_expiry, 1, arg); } - -#else - /* Process the interrupt now */ - - dm9x_poll_process(priv); -#endif } /**************************************************************************** @@ -1733,28 +1615,31 @@ static int dm9x_ifdown(struct net_driver_s *dev) } /**************************************************************************** - * Function: dm9x_txavail_process + * Function: dm9x_txavail_work * * Description: - * Perform an out-of-cycle poll. + * Perform an out-of-cycle poll on the worker thread. * * Parameters: - * dev - Reference to the NuttX driver state structure + * arg - Reference to the NuttX driver state structure (cast to void*) * * Returned Value: * None * * Assumptions: - * Called in normal user mode + * Called on the higher priority worker thread. * ****************************************************************************/ -static inline void dm9x_txavail_process(FAR struct dm9x_driver_s *priv) +static void dm9x_txavail_work(FAR void *arg) { + FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)arg; + ninfo("Polling\n"); /* Ignore the notification if the interface is not yet up */ + net_lock(); if (priv->dm_bifup) { @@ -1769,38 +1654,9 @@ static inline void dm9x_txavail_process(FAR struct dm9x_driver_s *priv) (void)devif_poll(&priv->dm_dev, dm9x_txpoll); } } -} -/**************************************************************************** - * Function: dm9x_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void dm9x_txavail_work(FAR void *arg) -{ - FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - dm9x_txavail_process(priv); - net_unlock(state); + net_unlock(); } -#endif /**************************************************************************** * Function: dm9x_txavail @@ -1825,7 +1681,6 @@ static int dm9x_txavail(FAR struct net_driver_s *dev) { FAR struct dm9x_driver_s *priv = (FAR struct dm9x_driver_s *)dev->d_private; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions and we will have to ignore the Tx * availability action. @@ -1838,21 +1693,6 @@ static int dm9x_txavail(FAR struct net_driver_s *dev) work_queue(ETHWORK, &priv->dm_work, dm9x_txavail_work, priv, 0); } -#else - irqstate_t flags; - - /* Disable interrupts because this function may be called from interrupt - * level processing. - */ - - flags = enter_critical_section(); - - /* Perform the out-of-cycle poll now */ - - dm9x_txavail_process(priv); - leave_critical_section(flags); -#endif - return OK; } diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c index 99b9610685..e91a5652ce 100644 --- a/drivers/net/enc28j60.c +++ b/drivers/net/enc28j60.c @@ -135,12 +135,6 @@ # define enc_dumppacket(m,a,n) #endif -/* The ENC28J60 will not do interrupt level processing */ - -#ifndef CONFIG_NET_NOINTS -# warning "CONFIG_NET_NOINTS should be set" -#endif - /* Low-level register debug */ #if !defined(CONFIG_DEBUG_FEATURES) || !defined(CONFIG_DEBUG_NET) @@ -1629,14 +1623,13 @@ static void enc_pktif(FAR struct enc_driver_s *priv) static void enc_irqworker(FAR void *arg) { FAR struct enc_driver_s *priv = (FAR struct enc_driver_s *)arg; - net_lock_t lock; uint8_t eir; DEBUGASSERT(priv); /* Get exclusive access to both the network and the SPI bus. */ - lock = net_lock(); + net_lock(); enc_lock(priv); /* Disable further interrupts by clearing the global interrupt enable bit. @@ -1827,7 +1820,7 @@ static void enc_irqworker(FAR void *arg) /* Release lock on the SPI bus and the network */ enc_unlock(priv); - net_unlock(lock); + net_unlock(); } /**************************************************************************** @@ -1889,7 +1882,6 @@ static int enc_interrupt(int irq, FAR void *context) static void enc_toworker(FAR void *arg) { FAR struct enc_driver_s *priv = (FAR struct enc_driver_s *)arg; - net_lock_t lock; int ret; nerr("ERROR: Tx timeout\n"); @@ -1897,7 +1889,7 @@ static void enc_toworker(FAR void *arg) /* Get exclusive access to the network */ - lock = net_lock(); + net_lock(); /* Increment statistics and dump debug info */ @@ -1919,7 +1911,7 @@ static void enc_toworker(FAR void *arg) /* Release lock on the network */ - net_unlock(lock); + net_unlock(); } /**************************************************************************** @@ -1983,13 +1975,12 @@ static void enc_txtimeout(int argc, uint32_t arg, ...) static void enc_pollworker(FAR void *arg) { FAR struct enc_driver_s *priv = (FAR struct enc_driver_s *)arg; - net_lock_t lock; DEBUGASSERT(priv); /* Get exclusive access to both the network and the SPI bus. */ - lock = net_lock(); + net_lock(); enc_lock(priv); /* Verify that the hardware is ready to send another packet. The driver @@ -2011,7 +2002,7 @@ static void enc_pollworker(FAR void *arg) /* Release lock on the SPI bus and the network */ enc_unlock(priv); - net_unlock(lock); + net_unlock(); /* Setup the watchdog poll timer again */ diff --git a/drivers/net/encx24j600.c b/drivers/net/encx24j600.c index 58aacaf603..e169068047 100644 --- a/drivers/net/encx24j600.c +++ b/drivers/net/encx24j600.c @@ -140,12 +140,6 @@ # define enc_dumppacket(m,a,n) #endif -/* The ENCX24J600 will not do interrupt level processing */ - -#ifndef CONFIG_NET_NOINTS -# warning "CONFIG_NET_NOINTS should be set" -#endif - /* Low-level register debug */ #if !defined(CONFIG_DEBUG_FEATURES) || !defined(CONFIG_DEBUG_NET) @@ -1841,14 +1835,13 @@ static void enc_rxabtif(FAR struct enc_driver_s *priv) static void enc_irqworker(FAR void *arg) { FAR struct enc_driver_s *priv = (FAR struct enc_driver_s *)arg; - net_lock_t lock; uint16_t eir; DEBUGASSERT(priv); /* Get exclusive access to both the network and the SPI bus. */ - lock = net_lock(); + net_lock(); enc_lock(priv); /* A good practice is for the host controller to clear the Global Interrupt @@ -1992,7 +1985,7 @@ static void enc_irqworker(FAR void *arg) /* Release lock on the SPI bus and the network */ enc_unlock(priv); - net_unlock(lock); + net_unlock(); } /**************************************************************************** @@ -2054,7 +2047,6 @@ static int enc_interrupt(int irq, FAR void *context) static void enc_toworker(FAR void *arg) { FAR struct enc_driver_s *priv = (FAR struct enc_driver_s *)arg; - net_lock_t lock; int ret; nerr("ERROR: Tx timeout\n"); @@ -2062,7 +2054,7 @@ static void enc_toworker(FAR void *arg) /* Get exclusive access to the network. */ - lock = net_lock(); + net_lock(); /* Increment statistics and dump debug info */ @@ -2084,7 +2076,7 @@ static void enc_toworker(FAR void *arg) /* Release the network */ - net_unlock(lock); + net_unlock(); } /**************************************************************************** @@ -2148,13 +2140,12 @@ static void enc_txtimeout(int argc, uint32_t arg, ...) static void enc_pollworker(FAR void *arg) { FAR struct enc_driver_s *priv = (FAR struct enc_driver_s *)arg; - net_lock_t lock; DEBUGASSERT(priv); /* Get exclusive access to both the network and the SPI bus. */ - lock = net_lock(); + net_lock(); enc_lock(priv); /* Verify that the hardware is ready to send another packet. The driver @@ -2176,7 +2167,7 @@ static void enc_pollworker(FAR void *arg) /* Release lock on the SPI bus and the network */ enc_unlock(priv); - net_unlock(lock); + net_unlock(); /* Setup the watchdog poll timer again */ diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c index c03e05ccb6..1550d9ad7c 100644 --- a/drivers/net/ftmac100.c +++ b/drivers/net/ftmac100.c @@ -56,11 +56,7 @@ #include #include #include - -#ifdef CONFIG_NET_NOINTS -# include -#endif - +#include #include #include #include @@ -76,13 +72,12 @@ * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +#if !defined(CONFIG_SCHED_WORKQUEUE) # error Work queue support is required in this configuration (CONFIG_SCHED_WORKQUEUE) -#endif +#else -/* Use the low priority work queue if possible */ + /* Use the low priority work queue if possible */ -#if defined(CONFIG_SCHED_WORKQUEUE) # if defined(CONFIG_FTMAC100_HPWORK) # define FTMAWORK HPWORK # elif defined(CONFIG_FTMAC100_LPWORK) @@ -178,10 +173,8 @@ struct ftmac100_driver_s bool ft_bifup; /* true:ifup false:ifdown */ WDOG_ID ft_txpoll; /* TX poll timer */ WDOG_ID ft_txtimeout; /* TX timeout timer */ -#ifdef CONFIG_NET_NOINTS unsigned int status; /* Last ISR status */ struct work_s ft_work; /* For deferring work to the work queue */ -#endif /* This holds the information visible to the NuttX network */ @@ -215,35 +208,26 @@ static int ftmac100_txpoll(struct net_driver_s *dev); static void ftmac100_reset(FAR struct ftmac100_driver_s *priv); static void ftmac100_receive(FAR struct ftmac100_driver_s *priv); static void ftmac100_txdone(FAR struct ftmac100_driver_s *priv); -static inline void ftmac100_interrupt_process(FAR struct ftmac100_driver_s *priv); -#ifdef CONFIG_NET_NOINTS + static void ftmac100_interrupt_work(FAR void *arg); -#endif static int ftmac100_interrupt(int irq, FAR void *context); /* Watchdog timer expirations */ -static inline void ftmac100_txtimeout_process(FAR struct ftmac100_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void ftmac100_txtimeout_work(FAR void *arg); -#endif static void ftmac100_txtimeout_expiry(int argc, uint32_t arg, ...); -static inline void ftmac100_poll_process(FAR struct ftmac100_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void ftmac100_poll_work(FAR void *arg); -#endif static void ftmac100_poll_expiry(int argc, uint32_t arg, ...); /* NuttX callback functions */ static int ftmac100_ifup(FAR struct net_driver_s *dev); static int ftmac100_ifdown(FAR struct net_driver_s *dev); -static inline void ftmac100_txavail_process(FAR struct ftmac100_driver_s *priv); -#ifdef CONFIG_NET_NOINTS + static void ftmac100_txavail_work(FAR void *arg); -#endif static int ftmac100_txavail(FAR struct net_driver_s *dev); + #if defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_ICMPv6) static int ftmac100_addmac(FAR struct net_driver_s *dev, FAR const uint8_t *mac); #ifdef CONFIG_NET_IGMP @@ -873,34 +857,33 @@ static void ftmac100_txdone(FAR struct ftmac100_driver_s *priv) } /**************************************************************************** - * Function: ftmac100_interrupt_process + * Function: ftmac100_interrupt_work * * Description: - * Interrupt processing. This may be performed either within the interrupt - * handler or on the worker thread, depending upon the configuration + * Perform interrupt related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void ftmac100_interrupt_process(FAR struct ftmac100_driver_s *priv) +static void ftmac100_interrupt_work(FAR void *arg) { + FAR struct ftmac100_driver_s *priv = (FAR struct ftmac100_driver_s *)arg; FAR struct ftmac100_register_s *iobase = (FAR struct ftmac100_register_s *)priv->iobase; unsigned int status; unsigned int phycr; -#ifdef CONFIG_NET_NOINTS + /* Process pending Ethernet interrupts */ + + net_lock(); status = priv->status; -#else - status = getreg32 (&iobase->isr); -#endif ninfo("status=%08x(%08x) BASE=%p ISR=%p PHYCR=%p\n", status, getreg32(&iobase->isr), iobase, &iobase->isr, &iobase->phycr); @@ -970,47 +953,12 @@ out: putreg32 (INT_MASK_ALL_ENABLED, &iobase->imr); ninfo("ISR-done\n"); -} - -/**************************************************************************** - * Function: ftmac100_interrupt_work - * - * Description: - * Perform interrupt related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() was called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void ftmac100_interrupt_work(FAR void *arg) -{ - FAR struct ftmac100_driver_s *priv = (FAR struct ftmac100_driver_s *)arg; - net_lock_t state; -//irqstate_t flags; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); -//flags = enter_critical_section(); - - ftmac100_interrupt_process(priv); - -//leave_critical_section(flags); - net_unlock(state); + net_unlock(); /* Re-enable Ethernet interrupts */ up_enable_irq(CONFIG_FTMAC100_IRQ); } -#endif /**************************************************************************** * Function: ftmac100_interrupt @@ -1034,17 +982,12 @@ static int ftmac100_interrupt(int irq, FAR void *context) FAR struct ftmac100_driver_s *priv = &g_ftmac100[0]; FAR struct ftmac100_register_s *iobase = (FAR struct ftmac100_register_s *)priv->iobase; -#ifdef CONFIG_NET_NOINTS - irqstate_t flags; - /* Disable further Ethernet interrupts. Because Ethernet interrupts are * also disabled if the TX timeout event occurs, there can be no race * condition here. */ - flags = enter_critical_section(); - - priv->status = getreg32 (&iobase->isr); + priv->status = getreg32(&iobase->isr); up_disable_irq(CONFIG_FTMAC100_IRQ); @@ -1073,45 +1016,9 @@ static int ftmac100_interrupt(int irq, FAR void *context) work_queue(FTMAWORK, &priv->ft_work, ftmac100_interrupt_work, priv, 0); - leave_critical_section(flags); -#else - /* Process the interrupt now */ - putreg32 (INT_MASK_ALL_DISABLED, &iobase->imr); - - ftmac100_interrupt_process(priv); -#endif - return OK; } -/**************************************************************************** - * Function: ftmac100_txtimeout_process - * - * Description: - * Process a TX timeout. Called from the either the watchdog timer - * expiration logic or from the worker thread, depending upon the - * configuration. The timeout means that the last TX never completed. - * Reset the hardware and start again. - * - * Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void ftmac100_txtimeout_process(FAR struct ftmac100_driver_s *priv) -{ - /* Then reset the hardware */ - - ninfo("TXTIMEOUT\n"); - - /* Then poll the network for new XMIT data */ - - (void)devif_poll(&priv->ft_dev, ftmac100_txpoll); -} - /**************************************************************************** * Function: ftmac100_txtimeout_work * @@ -1129,19 +1036,21 @@ static inline void ftmac100_txtimeout_process(FAR struct ftmac100_driver_s *priv * ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS static void ftmac100_txtimeout_work(FAR void *arg) { FAR struct ftmac100_driver_s *priv = (FAR struct ftmac100_driver_s *)arg; - net_lock_t state; + + ninfo("TXTIMEOUT\n"); /* Process pending Ethernet interrupts */ - state = net_lock(); - ftmac100_txtimeout_process(priv); - net_unlock(state); + net_lock(); + + /* Then poll the network for new XMIT data */ + + (void)devif_poll(&priv->ft_dev, ftmac100_txpoll); + net_unlock(); } -#endif /**************************************************************************** * Function: ftmac100_txtimeout_expiry @@ -1166,7 +1075,6 @@ static void ftmac100_txtimeout_expiry(int argc, uint32_t arg, ...) { FAR struct ftmac100_driver_s *priv = (FAR struct ftmac100_driver_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race * conditions with interrupt work. There is still a potential race * condition with interrupt work that is already queued and in progress. @@ -1183,32 +1091,32 @@ static void ftmac100_txtimeout_expiry(int argc, uint32_t arg, ...) /* Schedule to perform the TX timeout processing on the worker thread. */ work_queue(FTMAWORK, &priv->ft_work, ftmac100_txtimeout_work, priv, 0); -#else - /* Process the timeout now */ - - ftmac100_txtimeout_process(priv); -#endif } - /**************************************************************************** - * Function: ftmac100_poll_process + * Function: ftmac100_poll_work * * Description: - * Perform the periodic poll. This may be called either from watchdog - * timer logic or from the worker thread, depending upon the configuration. + * Perform periodic polling from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: + * Ethernet interrupts are disabled * ****************************************************************************/ -static inline void ftmac100_poll_process(FAR struct ftmac100_driver_s *priv) +static void ftmac100_poll_work(FAR void *arg) { + FAR struct ftmac100_driver_s *priv = (FAR struct ftmac100_driver_s *)arg; + + /* Perform the poll */ + + net_lock(); + /* Check if there is room in the send another TX packet. We cannot perform * the TX poll if he are unable to accept another packet for transmission. */ @@ -1224,39 +1132,9 @@ static inline void ftmac100_poll_process(FAR struct ftmac100_driver_s *priv) (void)wd_start(priv->ft_txpoll, FTMAC100_WDDELAY, ftmac100_poll_expiry, 1, (wdparm_t)priv); + net_unlock(); } -/**************************************************************************** - * Function: ftmac100_poll_work - * - * Description: - * Perform periodic polling from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void ftmac100_poll_work(FAR void *arg) -{ - FAR struct ftmac100_driver_s *priv = (FAR struct ftmac100_driver_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - ftmac100_poll_process(priv); - net_unlock(state); -} -#endif - /**************************************************************************** * Function: ftmac100_poll_expiry * @@ -1279,7 +1157,6 @@ static void ftmac100_poll_expiry(int argc, uint32_t arg, ...) { FAR struct ftmac100_driver_s *priv = (FAR struct ftmac100_driver_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions. */ @@ -1299,12 +1176,6 @@ static void ftmac100_poll_expiry(int argc, uint32_t arg, ...) (void)wd_start(priv->ft_txpoll, FTMAC100_WDDELAY, ftmac100_poll_expiry, 1, (wdparm_t)arg); } - -#else - /* Process the interrupt now */ - - ftmac100_poll_process(priv); -#endif } /**************************************************************************** @@ -1415,24 +1286,30 @@ static int ftmac100_ifdown(struct net_driver_s *dev) } /**************************************************************************** - * Function: ftmac100_txavail_process + * Function: ftmac100_txavail_work * * Description: - * Perform an out-of-cycle poll. + * Perform an out-of-cycle poll on the worker thread. * * Parameters: - * dev - Reference to the NuttX driver state structure + * arg - Reference to the NuttX driver state structure (cast to void*) * * Returned Value: * None * * Assumptions: - * Called in normal user mode + * Called on the higher priority worker thread. * ****************************************************************************/ -static inline void ftmac100_txavail_process(FAR struct ftmac100_driver_s *priv) +static void ftmac100_txavail_work(FAR void *arg) { + FAR struct ftmac100_driver_s *priv = (FAR struct ftmac100_driver_s *)arg; + + /* Perform the poll */ + + net_lock(); + /* Ignore the notification if the interface is not yet up */ if (priv->ft_bifup) @@ -1443,38 +1320,9 @@ static inline void ftmac100_txavail_process(FAR struct ftmac100_driver_s *priv) (void)devif_poll(&priv->ft_dev, ftmac100_txpoll); } -} -/**************************************************************************** - * Function: ftmac100_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void ftmac100_txavail_work(FAR void *arg) -{ - FAR struct ftmac100_driver_s *priv = (FAR struct ftmac100_driver_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - ftmac100_txavail_process(priv); - net_unlock(state); + net_unlock(); } -#endif /**************************************************************************** * Function: ftmac100_txavail @@ -1499,7 +1347,6 @@ static int ftmac100_txavail(struct net_driver_s *dev) { FAR struct ftmac100_driver_s *priv = (FAR struct ftmac100_driver_s *)dev->d_private; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions and we will have to ignore the Tx * availability action. @@ -1512,21 +1359,6 @@ static int ftmac100_txavail(struct net_driver_s *dev) work_queue(FTMAWORK, &priv->ft_work, ftmac100_txavail_work, priv, 0); } -#else - irqstate_t flags; - - /* Disable interrupts because this function may be called from interrupt - * level processing. - */ - - flags = enter_critical_section(); - - /* Perform the out-of-cycle poll now */ - - ftmac100_txavail_process(priv); - leave_critical_section(flags); -#endif - return OK; } diff --git a/drivers/net/loopback.c b/drivers/net/loopback.c index 8a703f6a60..06459d5449 100644 --- a/drivers/net/loopback.c +++ b/drivers/net/loopback.c @@ -67,12 +67,6 @@ * Pre-processor Definitions ****************************************************************************/ -/* Non-network-driven configuration is required */ - -#ifndef CONFIG_NET_NOINTS -# error CONFIG_NET_NOINTS must be selected -#endif - /* We need to have the work queue to handle SPI interrupts */ #if !defined(CONFIG_SCHED_WORKQUEUE) @@ -244,11 +238,10 @@ static int lo_txpoll(FAR struct net_driver_s *dev) static void lo_poll_work(FAR void *arg) { FAR struct lo_driver_s *priv = (FAR struct lo_driver_s *)arg; - net_lock_t state; /* Perform the poll */ - state = net_lock(); + net_lock(); priv->lo_txdone = false; (void)devif_timer(&priv->lo_dev, lo_txpoll); @@ -265,7 +258,7 @@ static void lo_poll_work(FAR void *arg) /* Setup the watchdog poll timer again */ (void)wd_start(priv->lo_polldog, LO_WDDELAY, lo_poll_expiry, 1, priv); - net_unlock(state); + net_unlock(); } /**************************************************************************** @@ -401,11 +394,10 @@ static int lo_ifdown(FAR struct net_driver_s *dev) static void lo_txavail_work(FAR void *arg) { FAR struct lo_driver_s *priv = (FAR struct lo_driver_s *)arg; - net_lock_t state; /* Ignore the notification if the interface is not yet up */ - state = net_lock(); + net_lock(); if (priv->lo_bifup) { do @@ -418,7 +410,7 @@ static void lo_txavail_work(FAR void *arg) while (priv->lo_txdone); } - net_unlock(state); + net_unlock(); } /**************************************************************************** diff --git a/drivers/net/skeleton.c b/drivers/net/skeleton.c index 0a6de71539..59c5a8fac5 100644 --- a/drivers/net/skeleton.c +++ b/drivers/net/skeleton.c @@ -53,11 +53,7 @@ #include #include #include - -#ifdef CONFIG_NET_NOINTS -# include -#endif - +#include #include #include @@ -72,13 +68,12 @@ * is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +#if !defined(CONFIG_SCHED_WORKQUEUE) # error Work queue support is required in this configuration (CONFIG_SCHED_WORKQUEUE) -#endif +#else -/* Use the low priority work queue if possible */ + /* Use the low priority work queue if possible */ -#if defined(CONFIG_SCHED_WORKQUEUE) # if defined(CONFIG_skeleton_HPWORK) # define ETHWORK HPWORK # elif defined(CONFIG_skeleton_LPWORK) @@ -121,9 +116,7 @@ struct skel_driver_s bool sk_bifup; /* true:ifup false:ifdown */ WDOG_ID sk_txpoll; /* TX poll timer */ WDOG_ID sk_txtimeout; /* TX timeout timer */ -#ifdef CONFIG_NET_NOINTS struct work_s sk_work; /* For deferring work to the work queue */ -#endif /* This holds the information visible to the NuttX network */ @@ -163,24 +156,15 @@ static int skel_txpoll(FAR struct net_driver_s *dev); static void skel_receive(FAR struct skel_driver_s *priv); static void skel_txdone(FAR struct skel_driver_s *priv); -static inline void skel_interrupt_process(FAR struct skel_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void skel_interrupt_work(FAR void *arg); -#endif static int skel_interrupt(int irq, FAR void *context); /* Watchdog timer expirations */ -static inline void skel_txtimeout_process(FAR struct skel_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void skel_txtimeout_work(FAR void *arg); -#endif static void skel_txtimeout_expiry(int argc, wdparm_t arg, ...); -static inline void skel_poll_process(FAR struct skel_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void skel_poll_work(FAR void *arg); -#endif static void skel_poll_expiry(int argc, wdparm_t arg, ...); /* NuttX callback functions */ @@ -188,10 +172,7 @@ static void skel_poll_expiry(int argc, wdparm_t arg, ...); static int skel_ifup(FAR struct net_driver_s *dev); static int skel_ifdown(FAR struct net_driver_s *dev); -static inline void skel_txavail_process(FAR struct skel_driver_s *priv); -#ifdef CONFIG_NET_NOINTS static void skel_txavail_work(FAR void *arg); -#endif static int skel_txavail(FAR struct net_driver_s *dev); #if defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_ICMPv6) @@ -511,31 +492,35 @@ static void skel_txdone(FAR struct skel_driver_s *priv) } /**************************************************************************** - * Function: skel_interrupt_process + * Function: skel_interrupt_work * * Description: - * Interrupt processing. This may be performed either within the interrupt - * handler or on the worker thread, depending upon the configuration + * Perform interrupt related work from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() was called. * * Returned Value: - * None + * OK on success * * Assumptions: * The network is locked. * ****************************************************************************/ -static inline void skel_interrupt_process(FAR struct skel_driver_s *priv) +static void skel_interrupt_work(FAR void *arg) { + FAR struct skel_driver_s *priv = (FAR struct skel_driver_s *)arg; + + /* Process pending Ethernet interrupts */ + /* Get and clear interrupt status bits */ /* Handle interrupts according to status bit settings */ /* Check if we received an incoming packet, if so, call skel_receive() */ + net_lock(); skel_receive(priv); /* Check if a packet transmission just completed. If so, call skel_txdone. @@ -544,42 +529,12 @@ static inline void skel_interrupt_process(FAR struct skel_driver_s *priv) */ skel_txdone(priv); -} - -/**************************************************************************** - * Function: skel_interrupt_work - * - * Description: - * Perform interrupt related work from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() was called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * The network is locked. - * - ****************************************************************************/ - -#ifdef CONFIG_NET_NOINTS -static void skel_interrupt_work(FAR void *arg) -{ - FAR struct skel_driver_s *priv = (FAR struct skel_driver_s *)arg; - net_lock_t state; - - /* Process pending Ethernet interrupts */ - - state = net_lock(); - skel_interrupt_process(priv); - net_unlock(state); + net_unlock(); /* Re-enable Ethernet interrupts */ up_enable_irq(CONFIG_skeleton_IRQ); } -#endif /**************************************************************************** * Function: skel_interrupt @@ -602,7 +557,6 @@ static int skel_interrupt(int irq, FAR void *context) { FAR struct skel_driver_s *priv = &g_skel[0]; -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. Because Ethernet interrupts are * also disabled if the TX timeout event occurs, there can be no race * condition here. @@ -628,46 +582,9 @@ static int skel_interrupt(int irq, FAR void *context) /* Schedule to perform the interrupt processing on the worker thread. */ work_queue(ETHWORK, &priv->sk_work, skel_interrupt_work, priv, 0); - -#else - /* Process the interrupt now */ - - skel_interrupt_process(priv); -#endif - return OK; } -/**************************************************************************** - * Function: skel_txtimeout_process - * - * Description: - * Process a TX timeout. Called from the either the watchdog timer - * expiration logic or from the worker thread, depending upon the - * configuration. The timeout means that the last TX never completed. - * Reset the hardware and start again. - * - * Parameters: - * priv - Reference to the driver state structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void skel_txtimeout_process(FAR struct skel_driver_s *priv) -{ - /* Increment statistics and dump debug info */ - - NETDEV_TXTIMEOUTS(priv->sk_dev); - - /* Then reset the hardware */ - - /* Then poll the network for new XMIT data */ - - (void)devif_poll(&priv->sk_dev, skel_txpoll); -} - /**************************************************************************** * Function: skel_txtimeout_work * @@ -685,19 +602,22 @@ static inline void skel_txtimeout_process(FAR struct skel_driver_s *priv) * ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS static void skel_txtimeout_work(FAR void *arg) { FAR struct skel_driver_s *priv = (FAR struct skel_driver_s *)arg; - net_lock_t state; - /* Process pending Ethernet interrupts */ + /* Increment statistics and dump debug info */ + + NETDEV_TXTIMEOUTS(priv->sk_dev); - state = net_lock(); - skel_txtimeout_process(priv); - net_unlock(state); + /* Then reset the hardware */ + + /* Then poll the network for new XMIT data */ + + net_lock(); + (void)devif_poll(&priv->sk_dev, skel_txpoll); + net_unlock(); } -#endif /**************************************************************************** * Function: skel_txtimeout_expiry @@ -722,7 +642,6 @@ static void skel_txtimeout_expiry(int argc, wdparm_t arg, ...) { FAR struct skel_driver_s *priv = (FAR struct skel_driver_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Disable further Ethernet interrupts. This will prevent some race * conditions with interrupt work. There is still a potential race * condition with interrupt work that is already queued and in progress. @@ -739,11 +658,6 @@ static void skel_txtimeout_expiry(int argc, wdparm_t arg, ...) /* Schedule to perform the TX timeout processing on the worker thread. */ work_queue(ETHWORK, &priv->sk_work, skel_txtimeout_work, priv, 0); -#else - /* Process the timeout now */ - - skel_txtimeout_process(priv); -#endif } /**************************************************************************** @@ -765,21 +679,6 @@ static void skel_txtimeout_expiry(int argc, wdparm_t arg, ...) static inline void skel_poll_process(FAR struct skel_driver_s *priv) { - /* Check if there is room in the send another TX packet. We cannot perform - * the TX poll if he are unable to accept another packet for transmission. - */ - - /* If so, update TCP timing states and poll the network for new XMIT data. - * Hmmm.. might be bug here. Does this mean if there is a transmit in - * progress, we will missing TCP time state updates? - */ - - (void)devif_timer(&priv->sk_dev, skel_txpoll); - - /* Setup the watchdog poll timer again */ - - (void)wd_start(priv->sk_txpoll, skeleton_WDDELAY, skel_poll_expiry, 1, - (wdparm_t)priv); } /**************************************************************************** @@ -799,19 +698,30 @@ static inline void skel_poll_process(FAR struct skel_driver_s *priv) * ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS static void skel_poll_work(FAR void *arg) { FAR struct skel_driver_s *priv = (FAR struct skel_driver_s *)arg; - net_lock_t state; /* Perform the poll */ - state = net_lock(); - skel_poll_process(priv); - net_unlock(state); + /* Check if there is room in the send another TX packet. We cannot perform + * the TX poll if he are unable to accept another packet for transmission. + */ + + /* If so, update TCP timing states and poll the network for new XMIT data. + * Hmmm.. might be bug here. Does this mean if there is a transmit in + * progress, we will missing TCP time state updates? + */ + + net_lock(); + (void)devif_timer(&priv->sk_dev, skel_txpoll); + + /* Setup the watchdog poll timer again */ + + (void)wd_start(priv->sk_txpoll, skeleton_WDDELAY, skel_poll_expiry, 1, + (wdparm_t)priv); + net_unlock(); } -#endif /**************************************************************************** * Function: skel_poll_expiry @@ -835,7 +745,6 @@ static void skel_poll_expiry(int argc, wdparm_t arg, ...) { FAR struct skel_driver_s *priv = (FAR struct skel_driver_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions. */ @@ -854,12 +763,6 @@ static void skel_poll_expiry(int argc, wdparm_t arg, ...) (void)wd_start(priv->sk_txpoll, skeleton_WDDELAY, skel_poll_expiry, 1, arg); } - -#else - /* Process the interrupt now */ - - skel_poll_process(priv); -#endif } /**************************************************************************** @@ -961,26 +864,29 @@ static int skel_ifdown(FAR struct net_driver_s *dev) } /**************************************************************************** - * Function: skel_txavail_process + * Function: skel_txavail_work * * Description: - * Perform an out-of-cycle poll. + * Perform an out-of-cycle poll on the worker thread. * * Parameters: - * dev - Reference to the NuttX driver state structure + * arg - Reference to the NuttX driver state structure (cast to void*) * * Returned Value: * None * * Assumptions: - * Called in normal user mode + * Called on the higher priority worker thread. * ****************************************************************************/ -static inline void skel_txavail_process(FAR struct skel_driver_s *priv) +static void skel_txavail_work(FAR void *arg) { + FAR struct skel_driver_s *priv = (FAR struct skel_driver_s *)arg; + /* Ignore the notification if the interface is not yet up */ + net_lock(); if (priv->sk_bifup) { /* Check if there is room in the hardware to hold another outgoing packet. */ @@ -989,38 +895,9 @@ static inline void skel_txavail_process(FAR struct skel_driver_s *priv) (void)devif_poll(&priv->sk_dev, skel_txpoll); } -} - -/**************************************************************************** - * Function: skel_txavail_work - * - * Description: - * Perform an out-of-cycle poll on the worker thread. - * - * Parameters: - * arg - Reference to the NuttX driver state structure (cast to void*) - * - * Returned Value: - * None - * - * Assumptions: - * Called on the higher priority worker thread. - * - ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS -static void skel_txavail_work(FAR void *arg) -{ - FAR struct skel_driver_s *priv = (FAR struct skel_driver_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - state = net_lock(); - skel_txavail_process(priv); - net_unlock(state); + net_unlock(); } -#endif /**************************************************************************** * Function: skel_txavail @@ -1045,7 +922,6 @@ static int skel_txavail(FAR struct net_driver_s *dev) { FAR struct skel_driver_s *priv = (FAR struct skel_driver_s *)dev->d_private; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions and we will have to ignore the Tx * availability action. @@ -1058,21 +934,6 @@ static int skel_txavail(FAR struct net_driver_s *dev) work_queue(ETHWORK, &priv->sk_work, skel_txavail_work, priv, 0); } -#else - irqstate_t flags; - - /* Disable interrupts because this function may be called from interrupt - * level processing. - */ - - flags = enter_critical_section(); - - /* Perform the out-of-cycle poll now */ - - skel_txavail_process(priv); - leave_critical_section(flags); -#endif - return OK; } diff --git a/drivers/net/slip.c b/drivers/net/slip.c index 0470027d57..afd3ca91ae 100644 --- a/drivers/net/slip.c +++ b/drivers/net/slip.c @@ -76,10 +76,6 @@ /* Configuration ************************************************************/ -#ifndef CONFIG_NET_NOINTS -# warning "CONFIG_NET_NOINTS must be set" -#endif - #ifndef CONFIG_NET_SLIP_STACKSIZE # define CONFIG_NET_SLIP_STACKSIZE 2048 #endif @@ -430,7 +426,6 @@ static void slip_txtask(int argc, FAR char *argv[]) { FAR struct slip_driver_s *priv; unsigned int index = *(argv[1]) - '0'; - net_lock_t flags; systime_t start_ticks; systime_t now_ticks; unsigned int hsec; @@ -476,7 +471,7 @@ static void slip_txtask(int argc, FAR char *argv[]) /* Poll the networking layer for new XMIT data. */ - flags = net_lock(); + net_lock(); priv->dev.d_buf = priv->txbuf; /* Has a half second elapsed since the last timer poll? */ @@ -497,7 +492,7 @@ static void slip_txtask(int argc, FAR char *argv[]) (void)devif_poll(&priv->dev, slip_txpoll); } - net_unlock(flags); + net_unlock(); slip_semgive(priv); } } @@ -655,7 +650,6 @@ static int slip_rxtask(int argc, FAR char *argv[]) { FAR struct slip_driver_s *priv; unsigned int index = *(argv[1]) - '0'; - net_lock_t flags; int ch; nerr("index: %d\n", index); @@ -728,7 +722,7 @@ static int slip_rxtask(int argc, FAR char *argv[]) priv->dev.d_buf = priv->rxbuf; priv->dev.d_len = priv->rxlen; - flags = net_lock(); + net_lock(); ipv4_input(&priv->dev); /* If the above function invocation resulted in data that should @@ -741,7 +735,8 @@ static int slip_rxtask(int argc, FAR char *argv[]) slip_transmit(priv); kill(priv->txpid, SIGALRM); } - net_unlock(flags); + + net_unlock(); slip_semgive(priv); } else diff --git a/drivers/net/tun.c b/drivers/net/tun.c index aaa411a613..ebb59587b6 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -58,15 +58,12 @@ #include #include #include +#include #include #include - -#include #include -#ifdef CONFIG_NET_NOINTS -# include -#endif +#include #ifdef CONFIG_NET_PKT # include @@ -79,11 +76,10 @@ * work queue support is required. */ -#if defined(CONFIG_NET_NOINTS) && !defined(CONFIG_SCHED_WORKQUEUE) +#if !defined(CONFIG_SCHED_WORKQUEUE) # error Work queue support is required in this configuration (CONFIG_SCHED_WORKQUEUE) -#endif +#else -#if defined(CONFIG_SCHED_WORKQUEUE) # if defined(CONFIG_TUN_HPWORK) # define TUNWORK HPWORK # elif defined(CONFIG_TUN_LPWORK) @@ -119,9 +115,7 @@ struct tun_device_s { bool bifup; /* true:ifup false:ifdown */ WDOG_ID txpoll; /* TX poll timer */ -#ifdef CONFIG_NET_NOINTS struct work_s work; /* For deferring work to the work queue */ -#endif FAR struct file *filep; @@ -169,10 +163,7 @@ static void tun_txdone(FAR struct tun_device_s *priv); /* Watchdog timer expirations */ -static inline void tun_poll_process(FAR struct tun_device_s *priv); -#ifdef CONFIG_NET_NOINTS static void tun_poll_work(FAR void *arg); -#endif static void tun_poll_expiry(int argc, wdparm_t arg, ...); /* NuttX callback functions */ @@ -533,24 +524,31 @@ static void tun_txdone(FAR struct tun_device_s *priv) } /**************************************************************************** - * Function: tun_poll_process + * Function: tun_poll_work * * Description: - * Perform the periodic poll. This may be called either from watchdog - * timer logic or from the worker thread, depending upon the configuration. + * Perform periodic polling from the worker thread * * Parameters: - * priv - Reference to the driver state structure + * arg - The argument passed when work_queue() as called. * * Returned Value: - * None + * OK on success * * Assumptions: + * Ethernet interrupts are disabled * ****************************************************************************/ -static void tun_poll_process(FAR struct tun_device_s *priv) +static void tun_poll_work(FAR void *arg) { + FAR struct tun_device_s *priv = (FAR struct tun_device_s *)arg; + + /* Perform the poll */ + + tun_lock(priv); + net_lock(); + /* Check if there is room in the send another TX packet. We cannot perform * the TX poll if he are unable to accept another packet for transmission. */ @@ -566,42 +564,10 @@ static void tun_poll_process(FAR struct tun_device_s *priv) /* Setup the watchdog poll timer again */ (void)wd_start(priv->txpoll, TUN_WDDELAY, tun_poll_expiry, 1, priv); -} - -/**************************************************************************** - * Function: tun_poll_work - * - * Description: - * Perform periodic polling from the worker thread - * - * Parameters: - * arg - The argument passed when work_queue() as called. - * - * Returned Value: - * OK on success - * - * Assumptions: - * Ethernet interrupts are disabled - * - ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS -static void tun_poll_work(FAR void *arg) -{ - FAR struct tun_device_s *priv = (FAR struct tun_device_s *)arg; - net_lock_t state; - - /* Perform the poll */ - - tun_lock(priv); - state = net_lock(); - - tun_poll_process(priv); - - net_unlock(state); + net_unlock(); tun_unlock(priv); } -#endif /**************************************************************************** * Function: tun_poll_expiry @@ -625,7 +591,6 @@ static void tun_poll_expiry(int argc, wdparm_t arg, ...) { FAR struct tun_device_s *priv = (FAR struct tun_device_s *)arg; -#ifdef CONFIG_NET_NOINTS /* Is our single work structure available? It may not be if there are * pending interrupt actions. */ @@ -644,12 +609,6 @@ static void tun_poll_expiry(int argc, wdparm_t arg, ...) (void)wd_start(priv->txpoll, TUN_WDDELAY, tun_poll_expiry, 1, arg); } - -#else - /* Process the interrupt now */ - - tun_poll_process(priv); -#endif } /**************************************************************************** @@ -758,7 +717,6 @@ static int tun_ifdown(struct net_driver_s *dev) static int tun_txavail(struct net_driver_s *dev) { FAR struct tun_device_s *priv = (FAR struct tun_device_s *)dev->d_private; - net_lock_t state; tun_lock(priv); @@ -770,7 +728,7 @@ static int tun_txavail(struct net_driver_s *dev) return OK; } - state = net_lock(); + net_lock(); if (priv->bifup) { @@ -780,7 +738,7 @@ static int tun_txavail(struct net_driver_s *dev) (void)devif_poll(&priv->dev, tun_txpoll); } - net_unlock(state); + net_unlock(); tun_unlock(priv); return OK; @@ -1005,7 +963,6 @@ static ssize_t tun_write(FAR struct file *filep, FAR const char *buffer, size_t buflen) { FAR struct tun_device_s *priv = filep->f_priv; - net_lock_t state; ssize_t ret; if (!priv) @@ -1021,7 +978,7 @@ static ssize_t tun_write(FAR struct file *filep, FAR const char *buffer, return -EBUSY; } - state = net_lock(); + net_lock(); if (buflen > CONFIG_NET_TUN_MTU) { @@ -1039,7 +996,7 @@ static ssize_t tun_write(FAR struct file *filep, FAR const char *buffer, ret = (ssize_t)buflen; } - net_unlock(state); + net_unlock(); tun_unlock(priv); return ret; @@ -1053,7 +1010,6 @@ static ssize_t tun_read(FAR struct file *filep, FAR char *buffer, size_t buflen) { FAR struct tun_device_s *priv = filep->f_priv; - net_lock_t state; ssize_t ret; size_t write_d_len; size_t read_d_len; @@ -1084,9 +1040,9 @@ static ssize_t tun_read(FAR struct file *filep, FAR char *buffer, if (priv->read_d_len == 0) { - state = net_lock(); + net_lock(); tun_txdone(priv); - net_unlock(state); + net_unlock(); } goto out; @@ -1106,7 +1062,7 @@ static ssize_t tun_read(FAR struct file *filep, FAR char *buffer, tun_lock(priv); } - state = net_lock(); + net_lock(); read_d_len = priv->read_d_len; if (buflen < read_d_len) @@ -1122,7 +1078,7 @@ static ssize_t tun_read(FAR struct file *filep, FAR char *buffer, priv->read_d_len = 0; tun_txdone(priv); - net_unlock(state); + net_unlock(); out: tun_unlock(priv); diff --git a/include/nuttx/net/net.h b/include/nuttx/net/net.h index 74abc0d701..54f5c83273 100644 --- a/include/nuttx/net/net.h +++ b/include/nuttx/net/net.h @@ -49,10 +49,6 @@ #include #include -#ifndef CONFIG_NET_NOINTS -# include -#endif - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -142,24 +138,6 @@ struct socketlist struct net_driver_s; /* Forward reference. Defined in nuttx/net/netdev.h */ typedef int (*netdev_callback_t)(FAR struct net_driver_s *dev, FAR void *arg); -#ifdef CONFIG_NET_NOINTS -/* Semaphore based locking for non-interrupt based logic. - * - * net_lock_t -- Not used. Only for compatibility - */ - -typedef uint8_t net_lock_t; /* Not really used */ - -#else - -/* Enable/disable locking for interrupt based logic: - * - * net_lock_t -- The processor specific representation of interrupt state. - */ - -# define net_lock_t irqstate_t -#endif - /**************************************************************************** * Public Data ****************************************************************************/ @@ -221,27 +199,15 @@ void net_setup(void); void net_initialize(void); /**************************************************************************** - * Critical section management. The NuttX configuration setting - * CONFIG_NET_NOINTS indicates that the network stack not called from the - * interrupt level. If CONFIG_NET_NOINTS is defined, then these will map - * to semaphore controls. Otherwise, it assumed that the stack will be - * called from interrupt level handling and these will map to interrupt - * enable/disable controls. - * + * Critical section management. * - * If CONFIG_NET_NOINTS is defined, then semaphore based locking is used: + * Semaphore based locking is used: * * net_lock() - Takes the semaphore(). Implements a re-entrant mutex. * net_unlock() - Gives the semaphore(). * net_lockedwait() - Like pthread_cond_wait(); releases the semaphore * momentarily to wait on another semaphore() * - * Otherwise, interrupt based locking is used: - * - * net_lock() - Disables interrupts. - * net_unlock() - Conditionally restores interrupts. - * net_lockedwait() - Just wait for the semaphore. - * ****************************************************************************/ /**************************************************************************** @@ -252,11 +218,7 @@ void net_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS -net_lock_t net_lock(void); -#else -# define net_lock() enter_critical_section() -#endif +void net_lock(void); /**************************************************************************** * Function: net_unlock @@ -266,11 +228,7 @@ net_lock_t net_lock(void); * ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS -void net_unlock(net_lock_t flags); -#else -# define net_unlock(f) leave_critical_section(f) -#endif +void net_unlock(void); /**************************************************************************** * Function: net_timedwait @@ -290,12 +248,8 @@ void net_unlock(net_lock_t flags); * ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS struct timespec; int net_timedwait(sem_t *sem, FAR const struct timespec *abstime); -#else -# define net_timedwait(s,t) sem_timedwait(s,t) -#endif /**************************************************************************** * Function: net_lockedwait @@ -313,11 +267,7 @@ int net_timedwait(sem_t *sem, FAR const struct timespec *abstime); * ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS int net_lockedwait(sem_t *sem); -#else -# define net_lockedwait(s) sem_wait(s) -#endif /**************************************************************************** * Function: net_setipid diff --git a/include/nuttx/net/slip.h b/include/nuttx/net/slip.h index 3818b5083d..546781f85f 100644 --- a/include/nuttx/net/slip.h +++ b/include/nuttx/net/slip.h @@ -51,11 +51,7 @@ * Pre-processor Definitions ****************************************************************************/ /* Configuration ***********************************************************/ -/* Dependencies: - * - * CONFIG_NET_NOINTS - Required. - * - * SLIP Configuration: +/* SLIP Configuration: * * CONFIG_NET_SLIP - Enables building of the SLIP driver * CONFIG_NET_SLIP_STACKSIZE - Provides the stack size for SLIP RX and TX diff --git a/net/Kconfig b/net/Kconfig index 1655cb0abf..2fea54f86f 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -20,17 +20,6 @@ config NET if NET -config NET_NOINTS - bool "Not interrupt driven" - default n - ---help--- - NET_NOINT indicates that network layer is not called from the - interrupt level. If NET_NOINTS is defined, critical sections - will be managed with semaphores; Otherwise, it assumed that - network layer will be called from interrupt level handling - and critical sections will be managed by enabling and disabling - interrupts. - config NET_PROMISCUOUS bool "Promiscuous mode" default n @@ -149,9 +138,7 @@ config NET_LOOPBACK select NETDEV_MULTINIC if NET_ETHERNET || NET_SLIP || NET_TUN select NET_MULTILINK if NET_ETHERNET || NET_SLIP || NET_TUN ---help--- - Add support for the local network loopback device, lo. Any additional - networking devices that are enabled must be compatible with - CONFIG_NET_NOINTS. + Add support for the local network loopback device, lo. config NET_SLIP bool "SLIP support" @@ -160,7 +147,7 @@ config NET_SLIP select NET_MULTILINK if NET_ETHERNET || NET_LOOPBACK || NET_TUN ---help--- Enables building of the SLIP driver. SLIP requires - at least one IP protocol selected and CONFIG_NET_NOINTS. + at least one IP protocol selected. SLIP supports point-to-point IP communications over a serial port. The default data link layer for network layer is Ethernet. If diff --git a/net/arp/arp_send.c b/net/arp/arp_send.c index 0a525c7d68..e5a1e48221 100644 --- a/net/arp/arp_send.c +++ b/net/arp/arp_send.c @@ -192,7 +192,6 @@ int arp_send(in_addr_t ipaddr) struct arp_notify_s notify; struct timespec delay; struct arp_send_s state; - net_lock_t save; int ret; /* First check if destination is a local broadcast. */ @@ -282,7 +281,7 @@ int arp_send(in_addr_t ipaddr) * want anything to happen until we are ready. */ - save = net_lock(); + net_lock(); state.snd_cb = arp_callback_alloc(dev); if (!state.snd_cb) { @@ -409,7 +408,7 @@ int arp_send(in_addr_t ipaddr) sem_destroy(&state.snd_sem); arp_callback_free(dev, state.snd_cb); errout_with_lock: - net_unlock(save); + net_unlock(); errout: return ret; } diff --git a/net/devif/devif_callback.c b/net/devif/devif_callback.c index 01986a3a9e..067b7663d9 100644 --- a/net/devif/devif_callback.c +++ b/net/devif/devif_callback.c @@ -80,11 +80,10 @@ static void devif_callback_free(FAR struct net_driver_s *dev, { FAR struct devif_callback_s *prev; FAR struct devif_callback_s *curr; - net_lock_t save; if (cb) { - save = net_lock(); + net_lock(); #ifdef CONFIG_DEBUG_FEATURES /* Check for double freed callbacks */ @@ -159,7 +158,7 @@ static void devif_callback_free(FAR struct net_driver_s *dev, cb->nxtconn = g_cbfreelist; cb->nxtdev = NULL; g_cbfreelist = cb; - net_unlock(save); + net_unlock(); } } @@ -210,11 +209,10 @@ FAR struct devif_callback_s * FAR struct devif_callback_s **list) { FAR struct devif_callback_s *ret; - net_lock_t save; /* Check the head of the free list */ - save = net_lock(); + net_lock(); ret = g_cbfreelist; if (ret) { @@ -241,7 +239,7 @@ FAR struct devif_callback_s * /* No.. release the callback structure and fail */ devif_callback_free(NULL, NULL, list); - net_unlock(save); + net_unlock(); return NULL; } @@ -264,7 +262,7 @@ FAR struct devif_callback_s * } #endif - net_unlock(save); + net_unlock(); return ret; } @@ -385,13 +383,12 @@ uint16_t devif_conn_event(FAR struct net_driver_s *dev, void *pvconn, uint16_t flags, FAR struct devif_callback_s *list) { FAR struct devif_callback_s *next; - net_lock_t save; /* Loop for each callback in the list and while there are still events * set in the flags set. */ - save = net_lock(); + net_lock(); while (list && flags) { /* Save the pointer to the next callback in the lists. This is done @@ -419,7 +416,7 @@ uint16_t devif_conn_event(FAR struct net_driver_s *dev, void *pvconn, list = next; } - net_unlock(save); + net_unlock(); return flags; } @@ -450,13 +447,12 @@ uint16_t devif_dev_event(FAR struct net_driver_s *dev, void *pvconn, { FAR struct devif_callback_s *cb; FAR struct devif_callback_s *next; - net_lock_t save; /* Loop for each callback in the list and while there are still events * set in the flags set. */ - save = net_lock(); + net_lock(); for (cb = dev->d_devcb; cb != NULL && flags != 0; cb = next) { /* Save the pointer to the next callback in the lists. This is done @@ -484,7 +480,7 @@ uint16_t devif_dev_event(FAR struct net_driver_s *dev, void *pvconn, cb = next; } - net_unlock(save); + net_unlock(); return flags; } diff --git a/net/icmp/icmp_ping.c b/net/icmp/icmp_ping.c index 96dd811cce..e6f8961b48 100644 --- a/net/icmp/icmp_ping.c +++ b/net/icmp/icmp_ping.c @@ -334,7 +334,6 @@ int icmp_ping(in_addr_t addr, uint16_t id, uint16_t seqno, uint16_t datalen, { FAR struct net_driver_s *dev; struct icmp_ping_s state; - net_lock_t save; #ifdef CONFIG_NET_ARP_SEND int ret; #endif @@ -380,7 +379,7 @@ int icmp_ping(in_addr_t addr, uint16_t id, uint16_t seqno, uint16_t datalen, state.png_datlen = datalen; /* The length of data to send in the ECHO request */ state.png_sent = false; /* ECHO request not yet sent */ - save = net_lock(); + net_lock(); state.png_time = clock_systimer(); /* Set up the callback */ @@ -410,7 +409,7 @@ int icmp_ping(in_addr_t addr, uint16_t id, uint16_t seqno, uint16_t datalen, icmp_callback_free(dev, state.png_cb); } - net_unlock(save); + net_unlock(); /* Return the negated error number in the event of a failure, or the * sequence number of the ECHO reply on success. diff --git a/net/icmpv6/icmpv6_autoconfig.c b/net/icmpv6/icmpv6_autoconfig.c index 0e8fc688cd..05a9c44926 100644 --- a/net/icmpv6/icmpv6_autoconfig.c +++ b/net/icmpv6/icmpv6_autoconfig.c @@ -279,7 +279,6 @@ errout_with_semaphore: * Parameters: * dev - The device to use to send the solicitation * notify - The pre-initialized notification structure - * save - We will need this to temporarily release the net lock * * Returned Value: * Zero (OK) is returned on success; On error a negated errno value is @@ -291,8 +290,7 @@ errout_with_semaphore: ****************************************************************************/ static int icmpv6_wait_radvertise(FAR struct net_driver_s *dev, - FAR struct icmpv6_rnotify_s *notify, - net_lock_t *save) + FAR struct icmpv6_rnotify_s *notify) { struct timespec delay; int ret; @@ -353,7 +351,6 @@ int icmpv6_autoconfig(FAR struct net_driver_s *dev) #else /* CONFIG_NET_ETHERNET */ struct icmpv6_rnotify_s notify; net_ipv6addr_t lladdr; - net_lock_t save; int retries; int ret; @@ -374,9 +371,9 @@ int icmpv6_autoconfig(FAR struct net_driver_s *dev) /* The interface should be in the down state */ - save = net_lock(); + net_lock(); netdev_ifdown(dev); - net_unlock(save); + net_unlock(); /* IPv6 Stateless Autoconfiguration * Reference: http://www.tcpipguide.com/free/t_IPv6AutoconfigurationandRenumbering.htm @@ -415,9 +412,9 @@ int icmpv6_autoconfig(FAR struct net_driver_s *dev) #ifdef CONFIG_NET_ICMPv6_NEIGHBOR /* Bring the interface up with no IP address */ - save = net_lock(); + net_lock(); netdev_ifup(dev); - net_unlock(save); + net_unlock(); /* 2. Link-Local Address Uniqueness Test: The node tests to ensure that * the address it generated isn't for some reason already in use on the @@ -435,9 +432,9 @@ int icmpv6_autoconfig(FAR struct net_driver_s *dev) /* Take the interface back down */ - save = net_lock(); + net_lock(); netdev_ifdown(dev); - net_unlock(save); + net_unlock(); if (ret == OK) { @@ -456,7 +453,7 @@ int icmpv6_autoconfig(FAR struct net_driver_s *dev) * on the wider Internet (since link-local addresses are not routed). */ - save = net_lock(); + net_lock(); net_ipv6addr_copy(dev->d_ipv6addr, lladdr); /* Bring the interface up with the new, temporary IP address */ @@ -489,7 +486,7 @@ int icmpv6_autoconfig(FAR struct net_driver_s *dev) /* Wait to receive the Router Advertisement message */ - ret = icmpv6_wait_radvertise(dev, ¬ify, &save); + ret = icmpv6_wait_radvertise(dev, ¬ify); if (ret != -ETIMEDOUT) { /* ETIMEDOUT is the only expected failure. We will retry on that @@ -534,7 +531,7 @@ int icmpv6_autoconfig(FAR struct net_driver_s *dev) * work out quite the way we wanted). */ - net_unlock(save); + net_unlock(); return ret; } @@ -557,7 +554,7 @@ int icmpv6_autoconfig(FAR struct net_driver_s *dev) */ netdev_ifup(dev); - net_unlock(save); + net_unlock(); return OK; #endif /* CONFIG_NET_ETHERNET */ } diff --git a/net/icmpv6/icmpv6_neighbor.c b/net/icmpv6/icmpv6_neighbor.c index 60f63660bd..de7ba28046 100644 --- a/net/icmpv6/icmpv6_neighbor.c +++ b/net/icmpv6/icmpv6_neighbor.c @@ -207,7 +207,6 @@ int icmpv6_neighbor(const net_ipv6addr_t ipaddr) struct timespec delay; struct icmpv6_neighbor_s state; FAR const uint16_t *lookup; - net_lock_t save; int ret; /* First check if destination is a local broadcast or a multicast address. @@ -295,7 +294,7 @@ int icmpv6_neighbor(const net_ipv6addr_t ipaddr) * want anything to happen until we are ready. */ - save = net_lock(); + net_lock(); state.snd_cb = icmpv6_callback_alloc(dev); if (!state.snd_cb) { @@ -404,7 +403,7 @@ int icmpv6_neighbor(const net_ipv6addr_t ipaddr) sem_destroy(&state.snd_sem); icmpv6_callback_free(dev, state.snd_cb); errout_with_lock: - net_unlock(save); + net_unlock(); errout: return ret; } diff --git a/net/icmpv6/icmpv6_ping.c b/net/icmpv6/icmpv6_ping.c index 839ac06e07..2d37890464 100644 --- a/net/icmpv6/icmpv6_ping.c +++ b/net/icmpv6/icmpv6_ping.c @@ -408,7 +408,6 @@ int icmpv6_ping(net_ipv6addr_t addr, uint16_t id, uint16_t seqno, { FAR struct net_driver_s *dev; struct icmpv6_ping_s state; - net_lock_t save; #ifdef CONFIG_NET_ICMPv6_NEIGHBOR int ret; @@ -454,7 +453,7 @@ int icmpv6_ping(net_ipv6addr_t addr, uint16_t id, uint16_t seqno, net_ipv6addr_copy(state.png_addr, addr); /* Address of the peer to be ping'ed */ - save = net_lock(); + net_lock(); state.png_time = clock_systimer(); /* Set up the callback */ @@ -484,7 +483,7 @@ int icmpv6_ping(net_ipv6addr_t addr, uint16_t id, uint16_t seqno, icmpv6_callback_free(dev, state.png_cb); } - net_unlock(save); + net_unlock(); /* Return the negated error number in the event of a failure, or the * sequence number of the ECHO reply on success. diff --git a/net/igmp/igmp_group.c b/net/igmp/igmp_group.c index e93a502052..a1fe865eb5 100644 --- a/net/igmp/igmp_group.c +++ b/net/igmp/igmp_group.c @@ -213,7 +213,6 @@ FAR struct igmp_group_s *igmp_grpalloc(FAR struct net_driver_s *dev, FAR const in_addr_t *addr) { FAR struct igmp_group_s *group; - net_lock_t flags; ninfo("addr: %08x dev: %p\n", *addr, dev); if (up_interrupt_context()) @@ -256,12 +255,12 @@ FAR struct igmp_group_s *igmp_grpalloc(FAR struct net_driver_s *dev, /* Interrupts must be disabled in order to modify the group list */ - flags = net_lock(); + net_lock(); /* Add the group structure to the list in the device structure */ sq_addfirst((FAR sq_entry_t *)group, &dev->grplist); - net_unlock(flags); + net_unlock(); } return group; @@ -282,7 +281,6 @@ FAR struct igmp_group_s *igmp_grpfind(FAR struct net_driver_s *dev, FAR const in_addr_t *addr) { FAR struct igmp_group_s *group; - net_lock_t flags; grpinfo("Searching for addr %08x\n", (int)*addr); @@ -290,7 +288,7 @@ FAR struct igmp_group_s *igmp_grpfind(FAR struct net_driver_s *dev, * called from. */ - flags = net_lock(); + net_lock(); for (group = (FAR struct igmp_group_s *)dev->grplist.head; group; group = group->next) @@ -303,7 +301,7 @@ FAR struct igmp_group_s *igmp_grpfind(FAR struct net_driver_s *dev, } } - net_unlock(flags); + net_unlock(); return group; } @@ -347,13 +345,11 @@ FAR struct igmp_group_s *igmp_grpallocfind(FAR struct net_driver_s *dev, void igmp_grpfree(FAR struct net_driver_s *dev, FAR struct igmp_group_s *group) { - net_lock_t flags; - grpinfo("Free: %p flags: %02x\n", group, group->flags); /* Cancel the wdog */ - flags = net_lock(); + net_lock(); wd_cancel(group->wdog); /* Remove the group structure from the group list in the device structure */ @@ -377,7 +373,7 @@ void igmp_grpfree(FAR struct net_driver_s *dev, FAR struct igmp_group_s *group) { grpinfo("Put back on free list\n"); sq_addlast((FAR sq_entry_t *)group, &g_freelist); - net_unlock(flags); + net_unlock(); } else #endif @@ -386,7 +382,7 @@ void igmp_grpfree(FAR struct net_driver_s *dev, FAR struct igmp_group_s *group) * this function is executing within an interrupt handler. */ - net_unlock(flags); + net_unlock(); grpinfo("Call sched_kfree()\n"); sched_kfree(group); } diff --git a/net/igmp/igmp_leave.c b/net/igmp/igmp_leave.c index 8e40451101..2b7ee654b3 100644 --- a/net/igmp/igmp_leave.c +++ b/net/igmp/igmp_leave.c @@ -127,7 +127,6 @@ int igmp_leavegroup(struct net_driver_s *dev, FAR const struct in_addr *grpaddr) { struct igmp_group_s *group; - net_lock_t flags; DEBUGASSERT(dev && grpaddr); @@ -143,11 +142,11 @@ int igmp_leavegroup(struct net_driver_s *dev, FAR const struct in_addr *grpaddr) * could interfere with the Leave Group. */ - flags = net_lock(); + net_lock(); wd_cancel(group->wdog); CLR_SCHEDMSG(group->flags); CLR_WAITMSG(group->flags); - net_unlock(flags); + net_unlock(); IGMP_STATINCR(g_netstats.igmp.leaves); diff --git a/net/igmp/igmp_msg.c b/net/igmp/igmp_msg.c index 3fd56fc381..0b5065f3ec 100644 --- a/net/igmp/igmp_msg.c +++ b/net/igmp/igmp_msg.c @@ -72,15 +72,13 @@ void igmp_schedmsg(FAR struct igmp_group_s *group, uint8_t msgid) { - net_lock_t flags; - /* The following should be atomic */ - flags = net_lock(); + net_lock(); DEBUGASSERT(!IS_SCHEDMSG(group->flags)); group->msgid = msgid; SET_SCHEDMSG(group->flags); - net_unlock(flags); + net_unlock(); } /**************************************************************************** @@ -98,11 +96,9 @@ void igmp_schedmsg(FAR struct igmp_group_s *group, uint8_t msgid) void igmp_waitmsg(FAR struct igmp_group_s *group, uint8_t msgid) { - net_lock_t flags; - /* Schedule to send the message */ - flags = net_lock(); + net_lock(); DEBUGASSERT(!IS_WAITMSG(group->flags)); SET_WAITMSG(group->flags); igmp_schedmsg(group, msgid); @@ -126,7 +122,7 @@ void igmp_waitmsg(FAR struct igmp_group_s *group, uint8_t msgid) /* The message has been sent and we are no longer waiting */ CLR_WAITMSG(group->flags); - net_unlock(flags); + net_unlock(); } #endif /* CONFIG_NET_IGMP */ diff --git a/net/igmp/igmp_timer.c b/net/igmp/igmp_timer.c index e413eb75fb..9019376a4e 100644 --- a/net/igmp/igmp_timer.c +++ b/net/igmp/igmp_timer.c @@ -196,14 +196,13 @@ void igmp_starttimer(FAR struct igmp_group_s *group, uint8_t decisecs) bool igmp_cmptimer(FAR struct igmp_group_s *group, int maxticks) { - net_lock_t flags; int remaining; /* Disable interrupts so that there is no race condition with the actual * timer expiration. */ - flags = net_lock(); + net_lock(); /* Get the timer remaining on the watchdog. A time of <= zero means that * the watchdog was never started. @@ -222,11 +221,11 @@ bool igmp_cmptimer(FAR struct igmp_group_s *group, int maxticks) /* Cancel the watchdog timer and return true */ wd_cancel(group->wdog); - net_unlock(flags); + net_unlock(); return true; } - net_unlock(flags); + net_unlock(); return false; } diff --git a/net/local/local_connect.c b/net/local/local_connect.c index b336b370b3..a1ae96337c 100644 --- a/net/local/local_connect.c +++ b/net/local/local_connect.c @@ -123,7 +123,7 @@ static inline void _local_semtake(sem_t *sem) int inline local_stream_connect(FAR struct local_conn_s *client, FAR struct local_conn_s *server, - bool nonblock, net_lock_t state) + bool nonblock) { int ret; @@ -135,7 +135,7 @@ int inline local_stream_connect(FAR struct local_conn_s *client, if (server->lc_state != LOCAL_STATE_LISTENING || server->u.server.lc_pending >= server->u.server.lc_backlog) { - net_unlock(state); + net_unlock(); nerr("ERROR: Server is not listening: lc_state=%d\n", server->lc_state); nerr(" OR: The backlog limit was reached: %d or %d\n", @@ -156,7 +156,7 @@ int inline local_stream_connect(FAR struct local_conn_s *client, nerr("ERROR: Failed to create FIFOs for %s: %d\n", client->lc_path, ret); - net_unlock(state); + net_unlock(); return ret; } @@ -170,7 +170,7 @@ int inline local_stream_connect(FAR struct local_conn_s *client, nerr("ERROR: Failed to open write-only FIFOs for %s: %d\n", client->lc_path, ret); - net_unlock(state); + net_unlock(); goto errout_with_fifos; } @@ -182,7 +182,7 @@ int inline local_stream_connect(FAR struct local_conn_s *client, client->lc_state = LOCAL_STATE_ACCEPT; local_accept_pollnotify(server, POLLIN); _local_semgive(&server->lc_waitsem); - net_unlock(state); + net_unlock(); /* Wait for the server to accept the connections */ @@ -257,7 +257,6 @@ int psock_local_connect(FAR struct socket *psock, FAR struct local_conn_s *client; FAR struct sockaddr_un *unaddr = (FAR struct sockaddr_un *)addr; FAR struct local_conn_s *conn; - net_lock_t state; DEBUGASSERT(psock && psock->s_conn); client = (FAR struct local_conn_s *)psock->s_conn; @@ -270,7 +269,7 @@ int psock_local_connect(FAR struct socket *psock, /* Find the matching server connection */ - state = net_lock(); + net_lock(); for (conn = (FAR struct local_conn_s *)g_local_listeners.head; conn; conn = (FAR struct local_conn_s *)dq_next(&conn->lc_node)) @@ -290,7 +289,7 @@ int psock_local_connect(FAR struct socket *psock, case LOCAL_TYPE_ABSTRACT: /* lc_path is length zero */ { #warning Missing logic - net_unlock(state); + net_unlock(); return OK; } break; @@ -322,7 +321,7 @@ int psock_local_connect(FAR struct socket *psock, } else { - net_unlock(state); + net_unlock(); } return ret; @@ -335,13 +334,13 @@ int psock_local_connect(FAR struct socket *psock, case LOCAL_TYPE_UNTYPED: /* Type is not determined until the socket is bound */ { - net_unlock(state); + net_unlock(); return -EINVAL; } } } - net_unlock(state); + net_unlock(); return -EADDRNOTAVAIL; } diff --git a/net/local/local_listen.c b/net/local/local_listen.c index 712055c9ce..a1020570e7 100644 --- a/net/local/local_listen.c +++ b/net/local/local_listen.c @@ -84,7 +84,6 @@ dq_queue_t g_local_listeners; int local_listen(FAR struct local_conn_s *server, int backlog) { - net_lock_t state; /* Some sanity checks */ @@ -118,9 +117,9 @@ int local_listen(FAR struct local_conn_s *server, int backlog) /* Add the connection structure to the list of listeners */ - state = net_lock(); + net_lock(); dq_addlast(&server->lc_node, &g_local_listeners); - net_unlock(state); + net_unlock(); /* And change the server state to listing */ diff --git a/net/local/local_netpoll.c b/net/local/local_netpoll.c index 9800af3172..f9e087b36d 100644 --- a/net/local/local_netpoll.c +++ b/net/local/local_netpoll.c @@ -62,12 +62,11 @@ static int local_accept_pollsetup(FAR struct local_conn_s *conn, FAR struct pollfd *fds, bool setup) { - net_lock_t state; pollevent_t eventset; int ret = OK; int i; - state = net_lock(); + net_lock(); if (setup) { /* This is a request to set up the poll. Find an available @@ -125,7 +124,7 @@ static int local_accept_pollsetup(FAR struct local_conn_s *conn, } errout: - net_unlock(state); + net_unlock(); return ret; } #endif diff --git a/net/local/local_release.c b/net/local/local_release.c index 29ea65f2f3..0d2bf42f80 100644 --- a/net/local/local_release.c +++ b/net/local/local_release.c @@ -69,12 +69,11 @@ int local_release(FAR struct local_conn_s *conn) { - net_lock_t state; /* There should be no references on this structure */ DEBUGASSERT(conn->lc_crefs == 0); - state = net_lock(); + net_lock(); #ifdef CONFIG_NET_LOCAL_STREAM /* We should not bet here with state LOCAL_STATE_ACCEPT. That is an @@ -126,7 +125,7 @@ int local_release(FAR struct local_conn_s *conn) /* Free the connection structure */ local_free(conn); - net_unlock(state); + net_unlock(); return OK; } diff --git a/net/netdev/netdev_count.c b/net/netdev/netdev_count.c index 73ff960f3d..171039caf6 100644 --- a/net/netdev/netdev_count.c +++ b/net/netdev/netdev_count.c @@ -72,12 +72,11 @@ int netdev_count(void) { struct net_driver_s *dev; - net_lock_t save; int ndev; - save = net_lock(); + net_lock(); for (dev = g_netdevices, ndev = 0; dev; dev = dev->flink, ndev++); - net_unlock(save); + net_unlock(); return ndev; } diff --git a/net/netdev/netdev_default.c b/net/netdev/netdev_default.c index 24884259a7..331f50343d 100644 --- a/net/netdev/netdev_default.c +++ b/net/netdev/netdev_default.c @@ -76,11 +76,10 @@ FAR struct net_driver_s *netdev_default(void) { FAR struct net_driver_s *dev; - net_lock_t save; /* Examine each registered network device */ - save = net_lock(); + net_lock(); for (dev = g_netdevices; dev; dev = dev->flink) { /* Is the interface in the "up" state? */ @@ -91,12 +90,12 @@ FAR struct net_driver_s *netdev_default(void) * state. */ - net_unlock(save); + net_unlock(); return dev; } } - net_unlock(save); + net_unlock(); return NULL; } diff --git a/net/netdev/netdev_findbyaddr.c b/net/netdev/netdev_findbyaddr.c index 54cf1cee35..25fbc02b8d 100644 --- a/net/netdev/netdev_findbyaddr.c +++ b/net/netdev/netdev_findbyaddr.c @@ -82,11 +82,10 @@ static FAR struct net_driver_s *netdev_finddevice_ipv4addr(in_addr_t ripaddr) { FAR struct net_driver_s *dev; - net_lock_t save; /* Examine each registered network device */ - save = net_lock(); + net_lock(); for (dev = g_netdevices; dev; dev = dev->flink) { /* Is the interface in the "up" state? */ @@ -100,7 +99,7 @@ static FAR struct net_driver_s *netdev_finddevice_ipv4addr(in_addr_t ripaddr) { /* Its a match */ - net_unlock(save); + net_unlock(); return dev; } } @@ -108,7 +107,7 @@ static FAR struct net_driver_s *netdev_finddevice_ipv4addr(in_addr_t ripaddr) /* No device with the matching address found */ - net_unlock(save); + net_unlock(); return NULL; } #endif /* CONFIG_NET_IPv4 */ @@ -137,11 +136,10 @@ static FAR struct net_driver_s * netdev_finddevice_ipv6addr(const net_ipv6addr_t ripaddr) { FAR struct net_driver_s *dev; - net_lock_t save; /* Examine each registered network device */ - save = net_lock(); + net_lock(); for (dev = g_netdevices; dev; dev = dev->flink) { /* Is the interface in the "up" state? */ @@ -155,7 +153,7 @@ netdev_finddevice_ipv6addr(const net_ipv6addr_t ripaddr) { /* Its a match */ - net_unlock(save); + net_unlock(); return dev; } } @@ -163,7 +161,7 @@ netdev_finddevice_ipv6addr(const net_ipv6addr_t ripaddr) /* No device with the matching address found */ - net_unlock(save); + net_unlock(); return NULL; } #endif /* CONFIG_NET_IPv6 */ diff --git a/net/netdev/netdev_findbyindex.c b/net/netdev/netdev_findbyindex.c index 74ccba04c8..f17bba0b7c 100644 --- a/net/netdev/netdev_findbyindex.c +++ b/net/netdev/netdev_findbyindex.c @@ -78,20 +78,19 @@ FAR struct net_driver_s *netdev_findbyindex(int index) { #ifdef CONFIG_NETDEV_MULTINIC FAR struct net_driver_s *dev; - net_lock_t save; int i; - save = net_lock(); + net_lock(); for (i = 0, dev = g_netdevices; dev; i++, dev = dev->flink) { if (i == index) { - net_unlock(save); + net_unlock(); return dev; } } - net_unlock(save); + net_unlock(); return NULL; #else return (index == 0) ? g_netdevices : NULL; diff --git a/net/netdev/netdev_findbyname.c b/net/netdev/netdev_findbyname.c index 04c20b27c8..944489a2d0 100644 --- a/net/netdev/netdev_findbyname.c +++ b/net/netdev/netdev_findbyname.c @@ -73,21 +73,20 @@ FAR struct net_driver_s *netdev_findbyname(FAR const char *ifname) { FAR struct net_driver_s *dev; - net_lock_t save; if (ifname) { - save = net_lock(); + net_lock(); for (dev = g_netdevices; dev; dev = dev->flink) { if (strcmp(ifname, dev->d_ifname) == 0) { - net_unlock(save); + net_unlock(); return dev; } } - net_unlock(save); + net_unlock(); } return NULL; diff --git a/net/netdev/netdev_foreach.c b/net/netdev/netdev_foreach.c index 99d6a8c061..11df953902 100644 --- a/net/netdev/netdev_foreach.c +++ b/net/netdev/netdev_foreach.c @@ -73,12 +73,11 @@ int netdev_foreach(netdev_callback_t callback, FAR void *arg) { FAR struct net_driver_s *dev; - net_lock_t save; int ret = 0; if (callback) { - save = net_lock(); + net_lock(); for (dev = g_netdevices; dev; dev = dev->flink) { if (callback(dev, arg) != 0) @@ -88,7 +87,7 @@ int netdev_foreach(netdev_callback_t callback, FAR void *arg) } } - net_unlock(save); + net_unlock(); } return ret; diff --git a/net/netdev/netdev_register.c b/net/netdev/netdev_register.c index 81bfe8232b..a2144d2288 100644 --- a/net/netdev/netdev_register.c +++ b/net/netdev/netdev_register.c @@ -178,7 +178,6 @@ int netdev_register(FAR struct net_driver_s *dev, enum net_lltype_e lltype) #ifdef CONFIG_NET_USER_DEVFMT FAR const char devfmt_str[IFNAMSIZ]; #endif - net_lock_t save; int devnum; if (dev) @@ -271,7 +270,7 @@ int netdev_register(FAR struct net_driver_s *dev, enum net_lltype_e lltype) * the interface */ - save = net_lock(); + net_lock(); #ifdef CONFIG_NET_MULTILINK # ifdef CONFIG_NET_LOOPBACK @@ -316,7 +315,7 @@ int netdev_register(FAR struct net_driver_s *dev, enum net_lltype_e lltype) #ifdef CONFIG_NET_IGMP igmp_devinit(dev); #endif - net_unlock(save); + net_unlock(); #ifdef CONFIG_NET_ETHERNET ninfo("Registered MAC: %02x:%02x:%02x:%02x:%02x:%02x as dev: %s\n", diff --git a/net/netdev/netdev_unregister.c b/net/netdev/netdev_unregister.c index 405118e308..6d56ad70f4 100644 --- a/net/netdev/netdev_unregister.c +++ b/net/netdev/netdev_unregister.c @@ -91,11 +91,10 @@ int netdev_unregister(FAR struct net_driver_s *dev) { struct net_driver_s *prev; struct net_driver_s *curr; - net_lock_t save; if (dev) { - save = net_lock(); + net_lock(); /* Find the device in the list of known network devices */ @@ -125,7 +124,7 @@ int netdev_unregister(FAR struct net_driver_s *dev) curr->flink = NULL; } - net_unlock(save); + net_unlock(); #ifdef CONFIG_NET_ETHERNET ninfo("Unregistered MAC: %02x:%02x:%02x:%02x:%02x:%02x as dev: %s\n", diff --git a/net/netdev/netdev_verify.c b/net/netdev/netdev_verify.c index 8fdd42b53a..ee3031ea78 100644 --- a/net/netdev/netdev_verify.c +++ b/net/netdev/netdev_verify.c @@ -64,12 +64,11 @@ bool netdev_verify(FAR struct net_driver_s *dev) { FAR struct net_driver_s *chkdev; - net_lock_t save; bool valid = false; /* Search the list of registered devices */ - save = net_lock(); + net_lock(); for (chkdev = g_netdevices; chkdev != NULL; chkdev = chkdev->flink) { /* Is the the network device that we are looking for? */ @@ -83,6 +82,6 @@ bool netdev_verify(FAR struct net_driver_s *dev) } } - net_unlock(save); + net_unlock(); return valid; } diff --git a/net/pkt/pkt_send.c b/net/pkt/pkt_send.c index b4dc0d6d45..fa5bda318b 100644 --- a/net/pkt/pkt_send.c +++ b/net/pkt/pkt_send.c @@ -213,7 +213,6 @@ ssize_t psock_pkt_send(FAR struct socket *psock, FAR const void *buf, { FAR struct net_driver_s *dev; struct send_s state; - net_lock_t save; int errcode; int ret = OK; @@ -245,7 +244,7 @@ ssize_t psock_pkt_send(FAR struct socket *psock, FAR const void *buf, * are ready. */ - save = net_lock(); + net_lock(); memset(&state, 0, sizeof(struct send_s)); /* This semaphore is used for signaling and, hence, should not have @@ -293,7 +292,7 @@ ssize_t psock_pkt_send(FAR struct socket *psock, FAR const void *buf, } sem_destroy(&state.snd_sem); - net_unlock(save); + net_unlock(); /* Set the socket state to idle */ diff --git a/net/route/net_addroute.c b/net/route/net_addroute.c index 3451a1691e..1f75944ec5 100644 --- a/net/route/net_addroute.c +++ b/net/route/net_addroute.c @@ -74,7 +74,6 @@ int net_addroute(in_addr_t target, in_addr_t netmask, in_addr_t router) { FAR struct net_route_s *route; - net_lock_t save; /* Allocate a route entry */ @@ -93,12 +92,12 @@ int net_addroute(in_addr_t target, in_addr_t netmask, in_addr_t router) /* Get exclusive address to the networking data structures */ - save = net_lock(); + net_lock(); /* Then add the new entry to the table */ sq_addlast((FAR sq_entry_t *)route, (FAR sq_queue_t *)&g_routes); - net_unlock(save); + net_unlock(); return OK; } #endif @@ -107,7 +106,6 @@ int net_addroute(in_addr_t target, in_addr_t netmask, in_addr_t router) int net_addroute_ipv6(net_ipv6addr_t target, net_ipv6addr_t netmask, net_ipv6addr_t router) { FAR struct net_route_ipv6_s *route; - net_lock_t save; /* Allocate a route entry */ @@ -126,12 +124,12 @@ int net_addroute_ipv6(net_ipv6addr_t target, net_ipv6addr_t netmask, net_ipv6add /* Get exclusive address to the networking data structures */ - save = net_lock(); + net_lock(); /* Then add the new entry to the table */ sq_addlast((FAR sq_entry_t *)route, (FAR sq_queue_t *)&g_routes_ipv6); - net_unlock(save); + net_unlock(); return OK; } #endif diff --git a/net/route/net_allocroute.c b/net/route/net_allocroute.c index 5c278a9a03..8c0cfdd02f 100644 --- a/net/route/net_allocroute.c +++ b/net/route/net_allocroute.c @@ -161,18 +161,17 @@ void net_initroute(void) FAR struct net_route_s *net_allocroute(void) { FAR struct net_route_s *route; - net_lock_t save; /* Get exclusive address to the networking data structures */ - save = net_lock(); + net_lock(); /* Then add the new entry to the table */ route = (FAR struct net_route_s *) sq_remfirst((FAR sq_queue_t *)&g_freeroutes); - net_unlock(save); + net_unlock(); return route; } #endif @@ -181,24 +180,23 @@ FAR struct net_route_s *net_allocroute(void) FAR struct net_route_ipv6_s *net_allocroute_ipv6(void) { FAR struct net_route_ipv6_s *route; - net_lock_t save; /* Get exclusive address to the networking data structures */ - save = net_lock(); + net_lock(); /* Then add the new entry to the table */ route = (FAR struct net_route_ipv6_s *) sq_remfirst((FAR sq_queue_t *)&g_freeroutes_ipv6); - net_unlock(save); + net_unlock(); return route; } #endif /**************************************************************************** - * Function: net_allocroute + * Function: net_freeroute * * Description: * Free one route by adding it from the free list @@ -214,36 +212,32 @@ FAR struct net_route_ipv6_s *net_allocroute_ipv6(void) #ifdef CONFIG_NET_IPv4 void net_freeroute(FAR struct net_route_s *route) { - net_lock_t save; - DEBUGASSERT(route); /* Get exclusive address to the networking data structures */ - save = net_lock(); + net_lock(); /* Then add the new entry to the table */ sq_addlast((FAR sq_entry_t *)route, (FAR sq_queue_t *)&g_freeroutes); - net_unlock(save); + net_unlock(); } #endif #ifdef CONFIG_NET_IPv6 void net_freeroute_ipv6(FAR struct net_route_ipv6_s *route) { - net_lock_t save; - DEBUGASSERT(route); /* Get exclusive address to the networking data structures */ - save = net_lock(); + net_lock(); /* Then add the new entry to the table */ sq_addlast((FAR sq_entry_t *)route, (FAR sq_queue_t *)&g_freeroutes_ipv6); - net_unlock(save); + net_unlock(); } #endif diff --git a/net/route/net_foreachroute.c b/net/route/net_foreachroute.c index 1c5789dd64..b9e52051af 100644 --- a/net/route/net_foreachroute.c +++ b/net/route/net_foreachroute.c @@ -72,12 +72,11 @@ int net_foreachroute(route_handler_t handler, FAR void *arg) { FAR struct net_route_s *route; FAR struct net_route_s *next; - net_lock_t save; int ret = 0; /* Prevent concurrent access to the routing table */ - save = net_lock(); + net_lock(); /* Visit each entry in the routing table */ @@ -93,7 +92,7 @@ int net_foreachroute(route_handler_t handler, FAR void *arg) /* Unlock the network */ - net_unlock(save); + net_unlock(); return ret; } #endif @@ -103,12 +102,11 @@ int net_foreachroute_ipv6(route_handler_ipv6_t handler, FAR void *arg) { FAR struct net_route_ipv6_s *route; FAR struct net_route_ipv6_s *next; - net_lock_t save; int ret = 0; /* Prevent concurrent access to the routing table */ - save = net_lock(); + net_lock(); /* Visit each entry in the routing table */ @@ -124,7 +122,7 @@ int net_foreachroute_ipv6(route_handler_ipv6_t handler, FAR void *arg) /* Unlock the network */ - net_unlock(save); + net_unlock(); return ret; } #endif diff --git a/net/socket/accept.c b/net/socket/accept.c index 59fa329bd8..a01f69f6c6 100644 --- a/net/socket/accept.c +++ b/net/socket/accept.c @@ -233,15 +233,13 @@ int psock_accept(FAR struct socket *psock, FAR struct sockaddr *addr, else #endif { - net_lock_t state; - /* Perform the local accept operation (with the network locked) */ - state = net_lock(); + net_lock(); ret = psock_tcp_accept(psock, addr, addrlen, &newsock->s_conn); if (ret < 0) { - net_unlock(state); + net_unlock(); errcode = -ret; goto errout; } @@ -258,12 +256,12 @@ int psock_accept(FAR struct socket *psock, FAR struct sockaddr *addr, * called. Undo everything we have done and return a failure. */ - net_unlock(state); + net_unlock(); errcode = -ret; goto errout_after_accept; } - net_unlock(state); + net_unlock(); } #endif /* CONFIG_NET_TCP */ diff --git a/net/socket/connect.c b/net/socket/connect.c index 3e174ae0b3..6b83184fd9 100644 --- a/net/socket/connect.c +++ b/net/socket/connect.c @@ -346,7 +346,6 @@ static inline int psock_tcp_connect(FAR struct socket *psock, FAR const struct sockaddr *addr) { struct tcp_connect_s state; - net_lock_t flags; int ret = OK; /* Interrupts must be disabled through all of the following because @@ -354,7 +353,7 @@ static inline int psock_tcp_connect(FAR struct socket *psock, * setup. */ - flags = net_lock(); + net_lock(); /* Get the connection reference from the socket */ @@ -431,7 +430,7 @@ static inline int psock_tcp_connect(FAR struct socket *psock, } } - net_unlock(flags); + net_unlock(); return ret; } #endif /* CONFIG_NET_TCP */ diff --git a/net/socket/getsockname.c b/net/socket/getsockname.c index 3b895525ef..7bf87c29d1 100644 --- a/net/socket/getsockname.c +++ b/net/socket/getsockname.c @@ -99,7 +99,6 @@ int ipv4_getsockname(FAR struct socket *psock, FAR struct sockaddr *addr, in_addr_t lipaddr; in_addr_t ripaddr; #endif - net_lock_t save; /* Check if enough space has been provided for the full address */ @@ -152,7 +151,7 @@ int ipv4_getsockname(FAR struct socket *psock, FAR struct sockaddr *addr, * a single network device and only the network device knows the IP address. */ - save = net_lock(); + net_lock(); #ifdef CONFIG_NETDEV_MULTINIC /* Find the device matching the IPv4 address in the connection structure */ @@ -166,7 +165,7 @@ int ipv4_getsockname(FAR struct socket *psock, FAR struct sockaddr *addr, if (!dev) { - net_unlock(save); + net_unlock(); return -EINVAL; } @@ -177,7 +176,7 @@ int ipv4_getsockname(FAR struct socket *psock, FAR struct sockaddr *addr, outaddr->sin_addr.s_addr = dev->d_ipaddr; *addrlen = sizeof(struct sockaddr_in); #endif - net_unlock(save); + net_unlock(); /* Return success */ @@ -223,7 +222,6 @@ int ipv6_getsockname(FAR struct socket *psock, FAR struct sockaddr *addr, net_ipv6addr_t *lipaddr; net_ipv6addr_t *ripaddr; #endif - net_lock_t save; /* Check if enough space has been provided for the full address */ @@ -276,7 +274,7 @@ int ipv6_getsockname(FAR struct socket *psock, FAR struct sockaddr *addr, * a single network device and only the network device knows the IP address. */ - save = net_lock(); + net_lock(); #ifdef CONFIG_NETDEV_MULTINIC /* Find the device matching the IPv6 address in the connection structure */ @@ -290,7 +288,7 @@ int ipv6_getsockname(FAR struct socket *psock, FAR struct sockaddr *addr, if (!dev) { - net_unlock(save); + net_unlock(); return -EINVAL; } @@ -301,7 +299,7 @@ int ipv6_getsockname(FAR struct socket *psock, FAR struct sockaddr *addr, memcpy(outaddr->sin6_addr.in6_u.u6_addr8, dev->d_ipv6addr, 16); *addrlen = sizeof(struct sockaddr_in6); #endif - net_unlock(save); + net_unlock(); /* Return success */ diff --git a/net/socket/net_clone.c b/net/socket/net_clone.c index e76f4ed2ce..5398c614fd 100644 --- a/net/socket/net_clone.c +++ b/net/socket/net_clone.c @@ -66,12 +66,11 @@ int net_clone(FAR struct socket *psock1, FAR struct socket *psock2) { - net_lock_t flags; int ret = OK; /* Parts of this operation need to be atomic */ - flags = net_lock(); + net_lock(); /* Duplicate the socket state */ @@ -120,7 +119,7 @@ int net_clone(FAR struct socket *psock1, FAR struct socket *psock2) ret = -EBADF; } - net_unlock(flags); + net_unlock(); return ret; } diff --git a/net/socket/net_close.c b/net/socket/net_close.c index 3ca53d30de..ba0fb85dc1 100644 --- a/net/socket/net_close.c +++ b/net/socket/net_close.c @@ -337,7 +337,6 @@ static inline int netclose_disconnect(FAR struct socket *psock) { struct tcp_close_s state; FAR struct tcp_conn_s *conn; - net_lock_t flags; #ifdef CONFIG_NET_SOLINGER bool linger; #endif @@ -345,7 +344,7 @@ static inline int netclose_disconnect(FAR struct socket *psock) /* Interrupts are disabled here to avoid race conditions */ - flags = net_lock(); + net_lock(); conn = (FAR struct tcp_conn_s *)psock->s_conn; /* If we have a semi-permanent write buffer callback in place, then @@ -449,7 +448,7 @@ static inline int netclose_disconnect(FAR struct socket *psock) tcp_free(conn); } - net_unlock(flags); + net_unlock(); return ret; } #endif /* CONFIG_NET_TCP */ diff --git a/net/socket/net_monitor.c b/net/socket/net_monitor.c index d7d566725b..cee6a13cd9 100644 --- a/net/socket/net_monitor.c +++ b/net/socket/net_monitor.c @@ -216,7 +216,6 @@ int net_startmonitor(FAR struct socket *psock) { FAR struct tcp_conn_s *conn; FAR struct devif_callback_s *cb; - net_lock_t save; DEBUGASSERT(psock != NULL && psock->s_conn != NULL); conn = (FAR struct tcp_conn_s *)psock->s_conn; @@ -226,7 +225,7 @@ int net_startmonitor(FAR struct socket *psock) * registered the monitoring callback.) */ - save = net_lock(); + net_lock(); if (!(conn->tcpstateflags == TCP_ESTABLISHED || conn->tcpstateflags == TCP_SYN_RCVD)) { @@ -244,7 +243,7 @@ int net_startmonitor(FAR struct socket *psock) * because the socket was already disconnected. */ - net_unlock(save); + net_unlock(); return -ENOTCONN; } @@ -270,7 +269,7 @@ int net_startmonitor(FAR struct socket *psock) conn->connection_private = (FAR void *)psock; conn->connection_event = connection_event; - net_unlock(save); + net_unlock(); return OK; } @@ -294,13 +293,11 @@ int net_startmonitor(FAR struct socket *psock) void net_stopmonitor(FAR struct tcp_conn_s *conn) { - net_lock_t save; - DEBUGASSERT(conn); /* Free any allocated device event callback structure */ - save = net_lock(); + net_lock(); if (conn->connection_devcb) { tcp_monitor_callback_free(conn, conn->connection_devcb); @@ -311,7 +308,7 @@ void net_stopmonitor(FAR struct tcp_conn_s *conn) conn->connection_private = NULL; conn->connection_devcb = NULL; conn->connection_event = NULL; - net_unlock(save); + net_unlock(); } /**************************************************************************** @@ -335,19 +332,17 @@ void net_stopmonitor(FAR struct tcp_conn_s *conn) void net_lostconnection(FAR struct socket *psock, uint16_t flags) { - net_lock_t save; - DEBUGASSERT(psock != NULL && psock->s_conn != NULL); /* Close the connection */ - save = net_lock(); + net_lock(); connection_closed(psock, flags); /* Stop the network monitor */ net_stopmonitor((FAR struct tcp_conn_s *)psock->s_conn); - net_unlock(save); + net_unlock(); } #endif /* CONFIG_NET && CONFIG_NET_TCP */ diff --git a/net/socket/net_sendfile.c b/net/socket/net_sendfile.c index 1efb22d1c8..617bce5397 100644 --- a/net/socket/net_sendfile.c +++ b/net/socket/net_sendfile.c @@ -604,7 +604,6 @@ ssize_t net_sendfile(int outfd, struct file *infile, off_t *offset, FAR struct socket *psock = sockfd_socket(outfd); FAR struct tcp_conn_s *conn; struct sendfile_s state; - net_lock_t save; int errcode; /* Verify that the sockfd corresponds to valid, allocated socket */ @@ -673,7 +672,7 @@ ssize_t net_sendfile(int outfd, struct file *infile, off_t *offset, * are ready. */ - save = net_lock(); + net_lock(); memset(&state, 0, sizeof(struct sendfile_s)); /* This semaphore is used for signaling and, hence, should not have @@ -757,7 +756,7 @@ errout_datacb: errout_locked: sem_destroy(&state. snd_sem); - net_unlock(save); + net_unlock(); errout: diff --git a/net/socket/net_vfcntl.c b/net/socket/net_vfcntl.c index 977db7833a..b260edb5b0 100644 --- a/net/socket/net_vfcntl.c +++ b/net/socket/net_vfcntl.c @@ -76,7 +76,6 @@ int net_vfcntl(int sockfd, int cmd, va_list ap) { FAR struct socket *psock = sockfd_socket(sockfd); - net_lock_t flags; int errcode = 0; int ret = 0; @@ -92,7 +91,7 @@ int net_vfcntl(int sockfd, int cmd, va_list ap) /* Interrupts must be disabled in order to perform operations on socket structures */ - flags = net_lock(); + net_lock(); switch (cmd) { case F_DUPFD: @@ -271,7 +270,7 @@ int net_vfcntl(int sockfd, int cmd, va_list ap) break; } - net_unlock(flags); + net_unlock(); errout: if (errcode != 0) diff --git a/net/socket/recvfrom.c b/net/socket/recvfrom.c index 046860b75f..e8a029b099 100644 --- a/net/socket/recvfrom.c +++ b/net/socket/recvfrom.c @@ -1395,7 +1395,6 @@ static ssize_t pkt_recvfrom(FAR struct socket *psock, FAR void *buf, size_t len, FAR struct pkt_conn_s *conn = (FAR struct pkt_conn_s *)psock->s_conn; FAR struct net_driver_s *dev; struct recvfrom_s state; - net_lock_t save; int ret; /* Perform the packet recvfrom() operation */ @@ -1405,7 +1404,7 @@ static ssize_t pkt_recvfrom(FAR struct socket *psock, FAR void *buf, size_t len, * are ready. */ - save = net_lock(); + net_lock(); recvfrom_init(psock, buf, len, from, fromlen, &state); /* Get the device driver that will service this transfer */ @@ -1463,7 +1462,7 @@ static ssize_t pkt_recvfrom(FAR struct socket *psock, FAR void *buf, size_t len, } errout_with_state: - net_unlock(save); + net_unlock(); recvfrom_uninit(&state); return ret; } @@ -1496,7 +1495,6 @@ static ssize_t udp_recvfrom(FAR struct socket *psock, FAR void *buf, size_t len, FAR struct udp_conn_s *conn = (FAR struct udp_conn_s *)psock->s_conn; FAR struct net_driver_s *dev; struct recvfrom_s state; - net_lock_t save; int ret; /* Perform the UDP recvfrom() operation */ @@ -1506,7 +1504,7 @@ static ssize_t udp_recvfrom(FAR struct socket *psock, FAR void *buf, size_t len, * are ready. */ - save = net_lock(); + net_lock(); recvfrom_init(psock, buf, len, from, fromlen, &state); /* Setup the UDP remote connection */ @@ -1604,7 +1602,7 @@ static ssize_t udp_recvfrom(FAR struct socket *psock, FAR void *buf, size_t len, } errout_with_state: - net_unlock(save); + net_unlock(); recvfrom_uninit(&state); return ret; } @@ -1634,16 +1632,15 @@ errout_with_state: static ssize_t tcp_recvfrom(FAR struct socket *psock, FAR void *buf, size_t len, FAR struct sockaddr *from, FAR socklen_t *fromlen) { - struct recvfrom_s state; - net_lock_t save; - int ret; + struct recvfrom_s state; + int ret; /* Initialize the state structure. This is done with interrupts * disabled because we don't want anything to happen until we * are ready. */ - save = net_lock(); + net_lock(); recvfrom_init(psock, buf, len, from, fromlen, &state); /* Handle any any TCP data already buffered in a read-ahead buffer. NOTE @@ -1783,7 +1780,7 @@ static ssize_t tcp_recvfrom(FAR struct socket *psock, FAR void *buf, size_t len, } } - net_unlock(save); + net_unlock(); recvfrom_uninit(&state); return (ssize_t)ret; } diff --git a/net/socket/setsockopt.c b/net/socket/setsockopt.c index 2086771b37..cdcd8d2e85 100644 --- a/net/socket/setsockopt.c +++ b/net/socket/setsockopt.c @@ -105,7 +105,6 @@ int psock_setsockopt(FAR struct socket *psock, int level, int option, FAR const void *value, socklen_t value_len) { - net_lock_t flags; int errcode; /* Verify that the socket option if valid (but might not be supported ) */ @@ -153,7 +152,7 @@ int psock_setsockopt(FAR struct socket *psock, int level, int option, * level access to options. */ - flags = net_lock(); + net_lock(); /* Set or clear the option bit */ @@ -166,7 +165,7 @@ int psock_setsockopt(FAR struct socket *psock, int level, int option, _SO_CLROPT(psock->s_options, option); } - net_unlock(flags); + net_unlock(); } break; @@ -235,7 +234,7 @@ int psock_setsockopt(FAR struct socket *psock, int level, int option, * level access to options. */ - flags = net_lock(); + net_lock(); /* Set or clear the linger option bit and linger time (in deciseconds) */ @@ -250,7 +249,7 @@ int psock_setsockopt(FAR struct socket *psock, int level, int option, psock->s_linger = 0; } - net_unlock(flags); + net_unlock(); } break; #endif diff --git a/net/tcp/tcp_backlog.c b/net/tcp/tcp_backlog.c index 6d7122fd3d..252f04a0f8 100644 --- a/net/tcp/tcp_backlog.c +++ b/net/tcp/tcp_backlog.c @@ -72,7 +72,6 @@ int tcp_backlogcreate(FAR struct tcp_conn_s *conn, int nblg) { FAR struct tcp_backlog_s *bls = NULL; FAR struct tcp_blcontainer_s *blc; - net_lock_t flags; int size; int offset; int i; @@ -125,7 +124,7 @@ int tcp_backlogcreate(FAR struct tcp_conn_s *conn, int nblg) /* Destroy any existing backlog (shouldn't be any) */ - flags = net_lock(); + net_lock(); tcp_backlogdestroy(conn); /* Now install the backlog tear-off in the connection. NOTE that bls may @@ -135,7 +134,7 @@ int tcp_backlogcreate(FAR struct tcp_conn_s *conn, int nblg) */ conn->backlog = bls; - net_unlock(flags); + net_unlock(); return OK; } diff --git a/net/tcp/tcp_conn.c b/net/tcp/tcp_conn.c index 12f7b332ea..8ca70aed79 100644 --- a/net/tcp/tcp_conn.c +++ b/net/tcp/tcp_conn.c @@ -514,13 +514,12 @@ static inline FAR struct tcp_conn_s * static inline int tcp_ipv4_bind(FAR struct tcp_conn_s *conn, FAR const struct sockaddr_in *addr) { - net_lock_t flags; int port; int ret; /* Verify or select a local port and address */ - flags = net_lock(); + net_lock(); /* Verify or select a local port (host byte order) */ @@ -565,7 +564,7 @@ static inline int tcp_ipv4_bind(FAR struct tcp_conn_s *conn, return ret; } - net_unlock(flags); + net_unlock(); return OK; } #endif /* CONFIG_NET_IPv4 */ @@ -589,13 +588,12 @@ static inline int tcp_ipv4_bind(FAR struct tcp_conn_s *conn, static inline int tcp_ipv6_bind(FAR struct tcp_conn_s *conn, FAR const struct sockaddr_in6 *addr) { - net_lock_t flags; int port; int ret; /* Verify or select a local port and address */ - flags = net_lock(); + net_lock(); /* Verify or select a local port (host byte order) */ @@ -646,7 +644,7 @@ static inline int tcp_ipv6_bind(FAR struct tcp_conn_s *conn, return ret; } - net_unlock(flags); + net_unlock(); return OK; } #endif /* CONFIG_NET_IPv6 */ @@ -700,14 +698,13 @@ void tcp_initialize(void) FAR struct tcp_conn_s *tcp_alloc(uint8_t domain) { FAR struct tcp_conn_s *conn; - net_lock_t flags; /* Because this routine is called from both interrupt level and * and from user level, we have not option but to disable interrupts * while accessing g_free_tcp_connections[]; */ - flags = net_lock(); + net_lock(); /* Return the entry from the head of the free list */ @@ -786,7 +783,7 @@ FAR struct tcp_conn_s *tcp_alloc(uint8_t domain) } #endif - net_unlock(flags); + net_unlock(); /* Mark the connection allocated */ @@ -818,7 +815,6 @@ void tcp_free(FAR struct tcp_conn_s *conn) #ifdef CONFIG_NET_TCP_WRITE_BUFFERS FAR struct tcp_wrbuffer_s *wrbuffer; #endif - net_lock_t flags; /* Because g_free_tcp_connections is accessed from user level and interrupt * level, code, it is necessary to keep interrupts disabled during this @@ -826,7 +822,7 @@ void tcp_free(FAR struct tcp_conn_s *conn) */ DEBUGASSERT(conn->crefs == 0); - flags = net_lock(); + net_lock(); /* Free remaining callbacks, actually there should be only the close callback * left. @@ -891,7 +887,7 @@ void tcp_free(FAR struct tcp_conn_s *conn) conn->tcpstateflags = TCP_CLOSED; dq_addlast(&conn->node, &g_free_tcp_connections); - net_unlock(flags); + net_unlock(); } /**************************************************************************** @@ -1184,7 +1180,6 @@ int tcp_bind(FAR struct tcp_conn_s *conn, FAR const struct sockaddr *addr) int tcp_connect(FAR struct tcp_conn_s *conn, FAR const struct sockaddr *addr) { - net_lock_t flags; int port; int ret; @@ -1203,7 +1198,7 @@ int tcp_connect(FAR struct tcp_conn_s *conn, FAR const struct sockaddr *addr) * but the port may still be INPORT_ANY. */ - flags = net_lock(); + net_lock(); #ifdef CONFIG_NETDEV_MULTINIC /* If there are multiple network devices, then we need to pass the local, @@ -1373,7 +1368,7 @@ int tcp_connect(FAR struct tcp_conn_s *conn, FAR const struct sockaddr *addr) ret = OK; errout_with_lock: - net_unlock(flags); + net_unlock(); return ret; } diff --git a/net/tcp/tcp_listen.c b/net/tcp/tcp_listen.c index b4990ba166..8a10fd9b57 100644 --- a/net/tcp/tcp_listen.c +++ b/net/tcp/tcp_listen.c @@ -141,11 +141,10 @@ void tcp_listen_initialize(void) int tcp_unlisten(FAR struct tcp_conn_s *conn) { - net_lock_t flags; int ndx; int ret = -EINVAL; - flags = net_lock(); + net_lock(); for (ndx = 0; ndx < CONFIG_NET_MAX_LISTENPORTS; ndx++) { if (tcp_listenports[ndx] == conn) @@ -156,7 +155,7 @@ int tcp_unlisten(FAR struct tcp_conn_s *conn) } } - net_unlock(flags); + net_unlock(); return ret; } @@ -173,7 +172,6 @@ int tcp_unlisten(FAR struct tcp_conn_s *conn) int tcp_listen(FAR struct tcp_conn_s *conn) { - net_lock_t flags; int ndx; int ret; @@ -181,7 +179,7 @@ int tcp_listen(FAR struct tcp_conn_s *conn) * is accessed from interrupt level as well. */ - flags = net_lock(); + net_lock(); /* First, check if there is already a socket listening on this port */ @@ -216,7 +214,7 @@ int tcp_listen(FAR struct tcp_conn_s *conn) } } - net_unlock(flags); + net_unlock(); return ret; } diff --git a/net/tcp/tcp_netpoll.c b/net/tcp/tcp_netpoll.c index 41382144c2..733c8c89e8 100644 --- a/net/tcp/tcp_netpoll.c +++ b/net/tcp/tcp_netpoll.c @@ -164,7 +164,6 @@ int tcp_pollsetup(FAR struct socket *psock, FAR struct pollfd *fds) FAR struct tcp_conn_s *conn = psock->s_conn; FAR struct tcp_poll_s *info; FAR struct devif_callback_s *cb; - net_lock_t flags; int ret; /* Sanity check */ @@ -186,7 +185,7 @@ int tcp_pollsetup(FAR struct socket *psock, FAR struct pollfd *fds) /* Some of the following must be atomic */ - flags = net_lock(); + net_lock(); /* Allocate a TCP/IP callback structure */ @@ -296,12 +295,12 @@ int tcp_pollsetup(FAR struct socket *psock, FAR struct pollfd *fds) sem_post(fds->sem); } - net_unlock(flags); + net_unlock(); return OK; errout_with_lock: kmm_free(info); - net_unlock(flags); + net_unlock(); return ret; } @@ -325,7 +324,6 @@ int tcp_pollteardown(FAR struct socket *psock, FAR struct pollfd *fds) { FAR struct tcp_conn_s *conn = psock->s_conn; FAR struct tcp_poll_s *info; - net_lock_t flags; /* Sanity check */ @@ -344,9 +342,9 @@ int tcp_pollteardown(FAR struct socket *psock, FAR struct pollfd *fds) { /* Release the callback */ - flags = net_lock(); + net_lock(); tcp_callback_free(conn, info->cb); - net_unlock(flags); + net_unlock(); /* Release the poll/select data slot */ diff --git a/net/tcp/tcp_send_buffered.c b/net/tcp/tcp_send_buffered.c index 468f90b9da..dbb2f28087 100644 --- a/net/tcp/tcp_send_buffered.c +++ b/net/tcp/tcp_send_buffered.c @@ -948,7 +948,6 @@ ssize_t psock_tcp_send(FAR struct socket *psock, FAR const void *buf, { FAR struct tcp_conn_s *conn; FAR struct tcp_wrbuffer_s *wrb; - net_lock_t save; ssize_t result = 0; int errcode; int ret = OK; @@ -1019,7 +1018,7 @@ ssize_t psock_tcp_send(FAR struct socket *psock, FAR const void *buf, * unlocked here. */ - save = net_lock(); + net_lock(); wrb = tcp_wrbuffer_alloc(); if (!wrb) { @@ -1077,7 +1076,7 @@ ssize_t psock_tcp_send(FAR struct socket *psock, FAR const void *buf, /* Notify the device driver of the availability of TX data */ send_txnotify(psock, conn); - net_unlock(save); + net_unlock(); } /* Set the socket state to idle */ @@ -1112,7 +1111,7 @@ errout_with_wrb: tcp_wrbuffer_release(wrb); errout_with_lock: - net_unlock(save); + net_unlock(); errout: set_errno(errcode); diff --git a/net/tcp/tcp_send_unbuffered.c b/net/tcp/tcp_send_unbuffered.c index 4710c41fe7..385c385a29 100644 --- a/net/tcp/tcp_send_unbuffered.c +++ b/net/tcp/tcp_send_unbuffered.c @@ -720,7 +720,6 @@ ssize_t psock_tcp_send(FAR struct socket *psock, { FAR struct tcp_conn_s *conn = (FAR struct tcp_conn_s *)psock->s_conn; struct send_s state; - net_lock_t save; int errcode; int ret = OK; @@ -792,7 +791,7 @@ ssize_t psock_tcp_send(FAR struct socket *psock, * are ready. */ - save = net_lock(); + net_lock(); memset(&state, 0, sizeof(struct send_s)); /* This semaphore is used for signaling and, hence, should not have @@ -854,7 +853,7 @@ ssize_t psock_tcp_send(FAR struct socket *psock, } sem_destroy(&state.snd_sem); - net_unlock(save); + net_unlock(); /* Set the socket state to idle */ diff --git a/net/udp/udp_conn.c b/net/udp/udp_conn.c index 1f5ecd095c..964846e91d 100644 --- a/net/udp/udp_conn.c +++ b/net/udp/udp_conn.c @@ -229,7 +229,7 @@ static uint16_t udp_select_port(void) * listen port number that is not being used by any other connection. */ - net_lock_t flags = net_lock(); + net_lock(); do { /* Guess that the next available port number will be the one after @@ -256,7 +256,7 @@ static uint16_t udp_select_port(void) */ portno = g_last_udp_port; - net_unlock(flags); + net_unlock(); return portno; } @@ -576,7 +576,6 @@ FAR struct udp_conn_s *udp_nextconn(FAR struct udp_conn_s *conn) int udp_bind(FAR struct udp_conn_s *conn, FAR const struct sockaddr *addr) { - net_lock_t flags; uint16_t portno; int ret; @@ -643,7 +642,7 @@ int udp_bind(FAR struct udp_conn_s *conn, FAR const struct sockaddr *addr) { /* Interrupts must be disabled while access the UDP connection list */ - flags = net_lock(); + net_lock(); /* Is any other UDP connection already bound to this address and port? */ @@ -659,7 +658,7 @@ int udp_bind(FAR struct udp_conn_s *conn, FAR const struct sockaddr *addr) ret = OK; } - net_unlock(flags); + net_unlock(); } return ret; diff --git a/net/udp/udp_netpoll.c b/net/udp/udp_netpoll.c index eade182fa1..6dd873aaec 100644 --- a/net/udp/udp_netpoll.c +++ b/net/udp/udp_netpoll.c @@ -161,7 +161,6 @@ int udp_pollsetup(FAR struct socket *psock, FAR struct pollfd *fds) FAR struct udp_conn_s *conn = psock->s_conn; FAR struct udp_poll_s *info; FAR struct devif_callback_s *cb; - net_lock_t flags; int ret; /* Sanity check */ @@ -183,7 +182,7 @@ int udp_pollsetup(FAR struct socket *psock, FAR struct pollfd *fds) /* Some of the following must be atomic */ - flags = net_lock(); + net_lock(); /* Get the device that will provide the provide the NETDEV_DOWN event. * NOTE: in the event that the local socket is bound to INADDR_ANY, the @@ -262,12 +261,12 @@ int udp_pollsetup(FAR struct socket *psock, FAR struct pollfd *fds) sem_post(fds->sem); } - net_unlock(flags); + net_unlock(); return OK; errout_with_lock: kmm_free(info); - net_unlock(flags); + net_unlock(); return ret; } @@ -291,7 +290,6 @@ int udp_pollteardown(FAR struct socket *psock, FAR struct pollfd *fds) { FAR struct udp_conn_s *conn = psock->s_conn; FAR struct udp_poll_s *info; - net_lock_t flags; /* Sanity check */ @@ -310,9 +308,9 @@ int udp_pollteardown(FAR struct socket *psock, FAR struct pollfd *fds) { /* Release the callback */ - flags = net_lock(); + net_lock(); udp_callback_free(info->dev, conn, info->cb); - net_unlock(flags); + net_unlock(); /* Release the poll/select data slot */ diff --git a/net/udp/udp_psock_sendto.c b/net/udp/udp_psock_sendto.c index 7ae830c5b7..84564f8a7e 100644 --- a/net/udp/udp_psock_sendto.c +++ b/net/udp/udp_psock_sendto.c @@ -340,7 +340,6 @@ ssize_t psock_udp_sendto(FAR struct socket *psock, FAR const void *buf, FAR struct udp_conn_s *conn; FAR struct net_driver_s *dev; struct sendto_s state; - net_lock_t save; int ret; #if defined(CONFIG_NET_ARP_SEND) || defined(CONFIG_NET_ICMPv6_NEIGHBOR) @@ -390,7 +389,7 @@ ssize_t psock_udp_sendto(FAR struct socket *psock, FAR const void *buf, * are ready. */ - save = net_lock(); + net_lock(); memset(&state, 0, sizeof(struct sendto_s)); /* This semaphore is used for signaling and, hence, should not have @@ -484,7 +483,7 @@ errout_with_lock: /* Unlock the network and return the result of the sendto() operation */ - net_unlock(save); + net_unlock(); return ret; } diff --git a/net/utils/Make.defs b/net/utils/Make.defs index 5abcb9226c..270b80bbbe 100644 --- a/net/utils/Make.defs +++ b/net/utils/Make.defs @@ -36,7 +36,7 @@ # Common utilities NET_CSRCS += net_dsec2tick.c net_dsec2timeval.c net_timeval2dsec.c -NET_CSRCS += net_chksum.c +NET_CSRCS += net_chksum.c net_lock.c # IPv6 utilities @@ -44,12 +44,6 @@ ifeq ($(CONFIG_NET_IPv6),y) NET_CSRCS += net_ipv6_maskcmp.c net_ipv6_mask2pref.c net_ipv6_pref2mask.c endif -# Non-interrupt level support required? - -ifeq ($(CONFIG_NET_NOINTS),y) -NET_CSRCS += net_lock.c -endif - # Include utility build support DEPPATH += --dep-path utils diff --git a/net/utils/net_lock.c b/net/utils/net_lock.c index 49ce834070..fbd42342ae 100644 --- a/net/utils/net_lock.c +++ b/net/utils/net_lock.c @@ -51,8 +51,6 @@ #include "utils/utils.h" -#if defined(CONFIG_NET) && defined(CONFIG_NET_NOINTS) - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -116,7 +114,7 @@ void net_lockinitialize(void) * ****************************************************************************/ -net_lock_t net_lock(void) +void net_lock(void) { pid_t me = getpid(); @@ -139,8 +137,6 @@ net_lock_t net_lock(void) g_holder = me; g_count = 1; } - - return 0; } /**************************************************************************** @@ -151,7 +147,7 @@ net_lock_t net_lock(void) * ****************************************************************************/ -void net_unlock(net_lock_t flags) +void net_unlock(void) { DEBUGASSERT(g_holder == getpid() && g_count > 0); @@ -261,4 +257,3 @@ int net_lockedwait(sem_t *sem) return net_timedwait(sem, NULL); } -#endif /* CONFIG_NET */ diff --git a/net/utils/utils.h b/net/utils/utils.h index 355e75e51e..6e33b72a83 100644 --- a/net/utils/utils.h +++ b/net/utils/utils.h @@ -84,11 +84,7 @@ struct timeval; /* Forward reference */ * ****************************************************************************/ -#ifdef CONFIG_NET_NOINTS void net_lockinitialize(void); -#else -# define net_lockinitialize() -#endif /**************************************************************************** * Function: net_dsec2timeval -- GitLab From a431fc77cb487e2714ea92842b7386a735ba3b76 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 3 Dec 2016 16:35:37 -0600 Subject: [PATCH 583/734] Add a forward refeence to elininate a warning. --- include/nuttx/sensors/xen1210.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/nuttx/sensors/xen1210.h b/include/nuttx/sensors/xen1210.h index de92cd5225..d76b504833 100644 --- a/include/nuttx/sensors/xen1210.h +++ b/include/nuttx/sensors/xen1210.h @@ -114,6 +114,7 @@ * handler but rather from the context of the worker thread with interrupts enabled. */ +struct xen1210_config_s; typedef void (*xen1210_handler_t)(FAR struct xen1210_config_s *config, FAR void *arg); /* A reference to a structure of this type must be passed to the XEN1210 driver when the -- GitLab From 83477c55f8c0ab2b9ea6d66906681ee81e7e9344 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 3 Dec 2016 17:06:14 -0600 Subject: [PATCH 584/734] STM32 Ethernet configurations must have work queue enabled. --- configs/olimex-stm32-e407/discover/defconfig | 11 ++++++++--- configs/olimex-stm32-e407/netnsh/defconfig | 11 ++++++++--- configs/olimex-stm32-e407/telnetd/defconfig | 11 ++++++++--- configs/olimex-stm32-e407/webserver/defconfig | 11 ++++++++--- configs/shenzhou/nsh/defconfig | 11 ++++++++--- configs/shenzhou/thttpd/defconfig | 11 ++++++++--- configs/stm3220g-eval/dhcpd/defconfig | 11 ++++++++--- configs/stm3220g-eval/nettest/defconfig | 11 ++++++++--- configs/stm3220g-eval/nsh/defconfig | 11 ++++++++--- configs/stm3220g-eval/telnetd/defconfig | 11 ++++++++--- configs/stm3240g-eval/dhcpd/defconfig | 11 ++++++++--- configs/stm3240g-eval/discover/defconfig | 11 ++++++++--- configs/stm3240g-eval/nettest/defconfig | 11 ++++++++--- configs/stm3240g-eval/nsh/defconfig | 11 ++++++++--- configs/stm3240g-eval/nxterm/defconfig | 11 ++++++++--- configs/stm3240g-eval/telnetd/defconfig | 11 ++++++++--- configs/stm3240g-eval/webserver/defconfig | 11 ++++++++--- configs/stm3240g-eval/xmlrpc/defconfig | 11 ++++++++--- 18 files changed, 144 insertions(+), 54 deletions(-) diff --git a/configs/olimex-stm32-e407/discover/defconfig b/configs/olimex-stm32-e407/discover/defconfig index 60f0cc16e5..069ce1dcb7 100644 --- a/configs/olimex-stm32-e407/discover/defconfig +++ b/configs/olimex-stm32-e407/discover/defconfig @@ -500,6 +500,7 @@ CONFIG_STM32_RMII=y # CONFIG_STM32_RMII_MCO1 is not set # CONFIG_STM32_RMII_MCO2 is not set CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -672,6 +673,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -680,6 +682,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -691,8 +694,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -793,7 +799,6 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set diff --git a/configs/olimex-stm32-e407/netnsh/defconfig b/configs/olimex-stm32-e407/netnsh/defconfig index 72c2701589..1ba24512b9 100644 --- a/configs/olimex-stm32-e407/netnsh/defconfig +++ b/configs/olimex-stm32-e407/netnsh/defconfig @@ -500,6 +500,7 @@ CONFIG_STM32_RMII=y # CONFIG_STM32_RMII_MCO1 is not set # CONFIG_STM32_RMII_MCO2 is not set CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -672,6 +673,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -680,6 +682,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -691,8 +694,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -795,7 +801,6 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set diff --git a/configs/olimex-stm32-e407/telnetd/defconfig b/configs/olimex-stm32-e407/telnetd/defconfig index 10a34c4e92..7eaea867bf 100644 --- a/configs/olimex-stm32-e407/telnetd/defconfig +++ b/configs/olimex-stm32-e407/telnetd/defconfig @@ -500,6 +500,7 @@ CONFIG_STM32_RMII=y # CONFIG_STM32_RMII_MCO1 is not set # CONFIG_STM32_RMII_MCO2 is not set CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -672,6 +673,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -680,6 +682,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -691,8 +694,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -795,7 +801,6 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set diff --git a/configs/olimex-stm32-e407/webserver/defconfig b/configs/olimex-stm32-e407/webserver/defconfig index 2e78b26022..7fd7e60e35 100644 --- a/configs/olimex-stm32-e407/webserver/defconfig +++ b/configs/olimex-stm32-e407/webserver/defconfig @@ -500,6 +500,7 @@ CONFIG_STM32_RMII=y # CONFIG_STM32_RMII_MCO1 is not set # CONFIG_STM32_RMII_MCO2 is not set CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -672,6 +673,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -680,6 +682,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -691,8 +694,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -793,7 +799,6 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set diff --git a/configs/shenzhou/nsh/defconfig b/configs/shenzhou/nsh/defconfig index 1fc93461f1..beafbeecec 100644 --- a/configs/shenzhou/nsh/defconfig +++ b/configs/shenzhou/nsh/defconfig @@ -481,6 +481,7 @@ CONFIG_STM32_PHYSR_100FD=0x8000 CONFIG_STM32_RMII=y CONFIG_STM32_RMII_MCO=y # CONFIG_STM32_RMII_EXTCLK is not set +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -659,6 +660,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -667,6 +669,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -678,8 +681,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -797,7 +803,6 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set diff --git a/configs/shenzhou/thttpd/defconfig b/configs/shenzhou/thttpd/defconfig index defbcf3cf8..810b7d515f 100644 --- a/configs/shenzhou/thttpd/defconfig +++ b/configs/shenzhou/thttpd/defconfig @@ -482,6 +482,7 @@ CONFIG_STM32_PHYSR_100FD=0x8000 CONFIG_STM32_RMII=y CONFIG_STM32_RMII_MCO=y # CONFIG_STM32_RMII_EXTCLK is not set +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -660,6 +661,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -668,6 +670,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -679,8 +682,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -824,7 +830,6 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set diff --git a/configs/stm3220g-eval/dhcpd/defconfig b/configs/stm3220g-eval/dhcpd/defconfig index 92d9dac8c8..af4f6af931 100644 --- a/configs/stm3220g-eval/dhcpd/defconfig +++ b/configs/stm3220g-eval/dhcpd/defconfig @@ -501,6 +501,7 @@ CONFIG_STM32_PHYSR_100MBPS=0x0000 CONFIG_STM32_PHYSR_MODE=0x0004 CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 # CONFIG_STM32_ETH_PTP is not set +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -665,6 +666,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -672,13 +674,17 @@ CONFIG_NAME_MAX=32 CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -769,7 +775,6 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set diff --git a/configs/stm3220g-eval/nettest/defconfig b/configs/stm3220g-eval/nettest/defconfig index e66a156f92..6a21166a9a 100644 --- a/configs/stm3220g-eval/nettest/defconfig +++ b/configs/stm3220g-eval/nettest/defconfig @@ -501,6 +501,7 @@ CONFIG_STM32_PHYSR_100MBPS=0x0000 CONFIG_STM32_PHYSR_MODE=0x0004 CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 # CONFIG_STM32_ETH_PTP is not set +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -665,6 +666,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -672,13 +674,17 @@ CONFIG_NAME_MAX=32 CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -770,7 +776,6 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set diff --git a/configs/stm3220g-eval/nsh/defconfig b/configs/stm3220g-eval/nsh/defconfig index ce18adbe6d..c3e02f4f66 100644 --- a/configs/stm3220g-eval/nsh/defconfig +++ b/configs/stm3220g-eval/nsh/defconfig @@ -509,6 +509,7 @@ CONFIG_STM32_PHYSR_100MBPS=0x0000 CONFIG_STM32_PHYSR_MODE=0x0004 CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 # CONFIG_STM32_ETH_PTP is not set +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -676,6 +677,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -684,6 +686,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -695,8 +698,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -836,7 +842,6 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set diff --git a/configs/stm3220g-eval/telnetd/defconfig b/configs/stm3220g-eval/telnetd/defconfig index 4af8ce18ac..5e7c56f25f 100644 --- a/configs/stm3220g-eval/telnetd/defconfig +++ b/configs/stm3220g-eval/telnetd/defconfig @@ -501,6 +501,7 @@ CONFIG_STM32_PHYSR_100MBPS=0x0000 CONFIG_STM32_PHYSR_MODE=0x0004 CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 # CONFIG_STM32_ETH_PTP is not set +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -665,6 +666,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -672,13 +674,17 @@ CONFIG_NAME_MAX=32 CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -772,7 +778,6 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set diff --git a/configs/stm3240g-eval/dhcpd/defconfig b/configs/stm3240g-eval/dhcpd/defconfig index 0f0b7fb1da..89f99ddd5b 100644 --- a/configs/stm3240g-eval/dhcpd/defconfig +++ b/configs/stm3240g-eval/dhcpd/defconfig @@ -505,6 +505,7 @@ CONFIG_STM32_PHYSR_100MBPS=0x0000 CONFIG_STM32_PHYSR_MODE=0x0004 CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 # CONFIG_STM32_ETH_PTP is not set +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -669,6 +670,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -676,13 +678,17 @@ CONFIG_NAME_MAX=32 CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -773,7 +779,6 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set diff --git a/configs/stm3240g-eval/discover/defconfig b/configs/stm3240g-eval/discover/defconfig index 18210f6a9d..f40268a76f 100644 --- a/configs/stm3240g-eval/discover/defconfig +++ b/configs/stm3240g-eval/discover/defconfig @@ -508,6 +508,7 @@ CONFIG_STM32_PHYSR_100MBPS=0x0000 CONFIG_STM32_PHYSR_MODE=0x0004 CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 # CONFIG_STM32_ETH_PTP is not set +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -678,6 +679,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -686,6 +688,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -697,8 +700,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -796,7 +802,6 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set diff --git a/configs/stm3240g-eval/nettest/defconfig b/configs/stm3240g-eval/nettest/defconfig index e64f241e19..ae30475a20 100644 --- a/configs/stm3240g-eval/nettest/defconfig +++ b/configs/stm3240g-eval/nettest/defconfig @@ -505,6 +505,7 @@ CONFIG_STM32_PHYSR_100MBPS=0x0000 CONFIG_STM32_PHYSR_MODE=0x0004 CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 # CONFIG_STM32_ETH_PTP is not set +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -669,6 +670,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -676,13 +678,17 @@ CONFIG_NAME_MAX=32 CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -774,7 +780,6 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set diff --git a/configs/stm3240g-eval/nsh/defconfig b/configs/stm3240g-eval/nsh/defconfig index 0bb15260d3..afc9d74ff1 100644 --- a/configs/stm3240g-eval/nsh/defconfig +++ b/configs/stm3240g-eval/nsh/defconfig @@ -521,6 +521,7 @@ CONFIG_STM32_PHYSR_100MBPS=0x0000 CONFIG_STM32_PHYSR_MODE=0x0004 CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 # CONFIG_STM32_ETH_PTP is not set +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -688,6 +689,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -696,6 +698,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -707,8 +710,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -814,7 +820,6 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set diff --git a/configs/stm3240g-eval/nxterm/defconfig b/configs/stm3240g-eval/nxterm/defconfig index da3ffd42ab..0042bbd78c 100644 --- a/configs/stm3240g-eval/nxterm/defconfig +++ b/configs/stm3240g-eval/nxterm/defconfig @@ -522,6 +522,7 @@ CONFIG_STM32_PHYSR_100MBPS=0x0000 CONFIG_STM32_PHYSR_MODE=0x0004 CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 # CONFIG_STM32_ETH_PTP is not set +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -700,6 +701,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -708,6 +710,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -719,8 +722,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -855,7 +861,6 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set diff --git a/configs/stm3240g-eval/telnetd/defconfig b/configs/stm3240g-eval/telnetd/defconfig index 07ad188e92..cb4e4b091a 100644 --- a/configs/stm3240g-eval/telnetd/defconfig +++ b/configs/stm3240g-eval/telnetd/defconfig @@ -505,6 +505,7 @@ CONFIG_STM32_PHYSR_100MBPS=0x0000 CONFIG_STM32_PHYSR_MODE=0x0004 CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 # CONFIG_STM32_ETH_PTP is not set +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -669,6 +670,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -676,13 +678,17 @@ CONFIG_NAME_MAX=32 CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGWORK=17 # CONFIG_MODULE is not set # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -776,7 +782,6 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set diff --git a/configs/stm3240g-eval/webserver/defconfig b/configs/stm3240g-eval/webserver/defconfig index 856364d415..17e05f9e57 100644 --- a/configs/stm3240g-eval/webserver/defconfig +++ b/configs/stm3240g-eval/webserver/defconfig @@ -513,6 +513,7 @@ CONFIG_STM32_PHYSR_100MBPS=0x0000 CONFIG_STM32_PHYSR_MODE=0x0004 CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 # CONFIG_STM32_ETH_PTP is not set +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -680,6 +681,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -688,6 +690,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -699,8 +702,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -835,7 +841,6 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set diff --git a/configs/stm3240g-eval/xmlrpc/defconfig b/configs/stm3240g-eval/xmlrpc/defconfig index 4cee1e1d72..b3db31d930 100644 --- a/configs/stm3240g-eval/xmlrpc/defconfig +++ b/configs/stm3240g-eval/xmlrpc/defconfig @@ -508,6 +508,7 @@ CONFIG_STM32_PHYSR_100MBPS=0x0000 CONFIG_STM32_PHYSR_MODE=0x0004 CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 # CONFIG_STM32_ETH_PTP is not set +CONFIG_STM32_ETHMAC_HPWORK=y # # USB FS Host Configuration @@ -673,6 +674,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -681,6 +683,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -692,8 +695,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -791,7 +797,6 @@ CONFIG_NETDEVICES=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -- GitLab From f45727dffc6231e1b8591fab87c2427cda4e8722 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 3 Dec 2016 16:53:22 -0600 Subject: [PATCH 585/734] Fix some kruft left behind in last big commit. --- net/local/local_connect.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/net/local/local_connect.c b/net/local/local_connect.c index a1ae96337c..53dd321905 100644 --- a/net/local/local_connect.c +++ b/net/local/local_connect.c @@ -316,8 +316,7 @@ int psock_local_connect(FAR struct socket *psock, if (conn->lc_proto == SOCK_STREAM) { ret = local_stream_connect(client, conn, - _SS_ISNONBLOCK(psock->s_flags), - state); + _SS_ISNONBLOCK(psock->s_flags)); } else { -- GitLab From 62114755c93f8d4ed8c6b26b129a4ded93837e42 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 3 Dec 2016 17:37:07 -0600 Subject: [PATCH 586/734] Misoc hello configuration needs HP work queue enabled. --- configs/misoc/hello/defconfig | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/configs/misoc/hello/defconfig b/configs/misoc/hello/defconfig index b785983a23..3aef6631d1 100644 --- a/configs/misoc/hello/defconfig +++ b/configs/misoc/hello/defconfig @@ -262,6 +262,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -270,6 +271,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -281,8 +283,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -376,7 +381,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set @@ -764,10 +768,10 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0xc0a8023b # CONFIG_EXAMPLES_NRF24L01TERM is not set CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set @@ -806,8 +810,8 @@ CONFIG_EXAMPLES_TELNETD_CLIENTPRIO=100 CONFIG_EXAMPLES_TELNETD_CLIENTSTACKSIZE=2048 # CONFIG_EXAMPLES_TIFF is not set # CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_UDPBLASTER is not set # CONFIG_EXAMPLES_UDP is not set +# CONFIG_EXAMPLES_UDPBLASTER is not set # CONFIG_EXAMPLES_USBTERM is not set # CONFIG_EXAMPLES_WATCHDOG is not set # CONFIG_EXAMPLES_WEBSERVER is not set -- GitLab From 4f1b96b29b7d5d28440d05a2520a1980d404302d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 3 Dec 2016 17:52:13 -0600 Subject: [PATCH 587/734] More networking configurations taht need the work queue enabled. --- configs/sam4e-ek/usbnsh/defconfig | 11 ++++++++--- configs/sama5d4-ek/bridge/defconfig | 11 ++++++++--- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/configs/sam4e-ek/usbnsh/defconfig b/configs/sam4e-ek/usbnsh/defconfig index af76f90700..ed8824bf3c 100644 --- a/configs/sam4e-ek/usbnsh/defconfig +++ b/configs/sam4e-ek/usbnsh/defconfig @@ -293,6 +293,7 @@ CONFIG_SAM34_EMAC_PHYSR_100HD=0x2 CONFIG_SAM34_EMAC_PHYSR_10FD=0x5 CONFIG_SAM34_EMAC_PHYSR_100FD=0x6 CONFIG_SAM34_EMAC_ISETH0=y +CONFIG_SAM34_EMAC_HPWORK=y # # AT91SAM3/4 USB Full Speed Device Controller driver (DCD) options @@ -464,6 +465,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -472,6 +474,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -483,8 +486,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -619,7 +625,6 @@ CONFIG_TELNET_TXBUFFER_SIZE=256 # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set diff --git a/configs/sama5d4-ek/bridge/defconfig b/configs/sama5d4-ek/bridge/defconfig index 134be3f686..a02e653903 100644 --- a/configs/sama5d4-ek/bridge/defconfig +++ b/configs/sama5d4-ek/bridge/defconfig @@ -318,6 +318,7 @@ CONFIG_SAMA5_EMAC1_PHYSR_10FD=0x5 CONFIG_SAMA5_EMAC1_PHYSR_100FD=0x6 # CONFIG_SAMA5_EMACB_PREALLOCATE is not set # CONFIG_SAMA5_EMACB_NBC is not set +CONFIG_SAMA5_EMACB_HPWORK=y CONFIG_SAMA5_EMAC0_ISETH0=y # CONFIG_SAMA5_EMAC1_ISETH0 is not set @@ -500,6 +501,7 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -508,6 +510,7 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -519,8 +522,11 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=224 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 # CONFIG_SCHED_LPWORK is not set # @@ -611,7 +617,6 @@ CONFIG_NETDEV_MULTINIC=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set -- GitLab From 920a9592d1887d541c5d44e396568f4efe5b5fd6 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 3 Dec 2016 18:19:08 -0600 Subject: [PATCH 588/734] Fix a naming collision introduced in last big commit --- arch/arm/src/tiva/Kconfig | 9 +++++---- arch/arm/src/tiva/lm3s_ethernet.c | 6 +++--- configs/eagle100/httpd/defconfig | 2 +- configs/eagle100/nettest/defconfig | 2 +- configs/eagle100/nsh/defconfig | 2 +- configs/eagle100/thttpd/defconfig | 2 +- configs/ekk-lm3s9b96/nsh/defconfig | 2 +- configs/lm3s6432-s2e/nsh/defconfig | 2 +- configs/lm3s6965-ek/discover/defconfig | 2 +- configs/lm3s6965-ek/nsh/defconfig | 2 +- configs/lm3s6965-ek/tcpecho/defconfig | 2 +- configs/lm3s8962-ek/nsh/defconfig | 2 +- 12 files changed, 18 insertions(+), 17 deletions(-) diff --git a/arch/arm/src/tiva/Kconfig b/arch/arm/src/tiva/Kconfig index 4f483170b4..fb82d1fb5a 100644 --- a/arch/arm/src/tiva/Kconfig +++ b/arch/arm/src/tiva/Kconfig @@ -913,19 +913,19 @@ config TIVA_BADCRC choice prompt "Work queue" - default TIVA_ETHERNET_LPWORK if SCHED_LPWORK - default TIVA_ETHERNET_HPWORK if !SCHED_LPWORK && SCHED_HPWORK + default LM3S_ETHERNET_LPWORK if SCHED_LPWORK + default LM3S_ETHERNET_HPWORK if !SCHED_LPWORK && SCHED_HPWORK depends on SCHED_WORKQUEUE ---help--- Work queue support is required to use the Ethernet driver. If the low priority work queue is available, then it should be used by the driver. -config TIVA_ETHERNET_HPWORK +config LM3S_ETHERNET_HPWORK bool "High priority" depends on SCHED_HPWORK -config TIVA_ETHERNET_LPWORK +config LM3S_ETHERNET_LPWORK bool "Low priority" depends on SCHED_LPWORK @@ -1139,6 +1139,7 @@ config TIVA_ETHERNET_LPWORK depends on SCHED_LPWORK endchoice # Work queue + config TIVA_ETHERNET_REGDEBUG bool "Register-Level Debug" default n diff --git a/arch/arm/src/tiva/lm3s_ethernet.c b/arch/arm/src/tiva/lm3s_ethernet.c index b7fd2189c5..bfe8f2669d 100644 --- a/arch/arm/src/tiva/lm3s_ethernet.c +++ b/arch/arm/src/tiva/lm3s_ethernet.c @@ -83,12 +83,12 @@ /* Use the low priority work queue if possible */ -# if defined(CONFIG_TIVA_ETHERNET_HPWORK) +# if defined(CONFIG_LM3S_ETHERNET_HPWORK) # define ETHWORK HPWORK -# elif defined(CONFIG_TIVA_ETHERNET_LPWORK) +# elif defined(CONFIG_LM3S_ETHERNET_LPWORK) # define ETHWORK LPWORK # else -# error Neither CONFIG_TIVA_ETHERNET_HPWORK nor CONFIG_TIVA_ETHERNET_LPWORK defined +# error Neither CONFIG_LM3S_ETHERNET_HPWORK nor CONFIG_LM3S_ETHERNET_LPWORK defined # endif #endif diff --git a/configs/eagle100/httpd/defconfig b/configs/eagle100/httpd/defconfig index 2d955bbcab..3cae28f259 100644 --- a/configs/eagle100/httpd/defconfig +++ b/configs/eagle100/httpd/defconfig @@ -257,7 +257,7 @@ CONFIG_TIVA_GPIOG_IRQS=y # CONFIG_TIVA_PROMISCUOUS is not set # CONFIG_TIVA_TIMESTAMP is not set # CONFIG_TIVA_BADCRC is not set -CONFIG_TIVA_ETHERNET_HPWORK=y +CONFIG_LM3S_ETHERNET_HPWORK=y # CONFIG_TIVA_DUMPPACKET is not set CONFIG_TIVA_BOARDMAC=y diff --git a/configs/eagle100/nettest/defconfig b/configs/eagle100/nettest/defconfig index 7cf58f403b..09a90f2759 100644 --- a/configs/eagle100/nettest/defconfig +++ b/configs/eagle100/nettest/defconfig @@ -257,7 +257,7 @@ CONFIG_TIVA_GPIOG_IRQS=y # CONFIG_TIVA_PROMISCUOUS is not set # CONFIG_TIVA_TIMESTAMP is not set # CONFIG_TIVA_BADCRC is not set -CONFIG_TIVA_ETHERNET_HPWORK=y +CONFIG_LM3S_ETHERNET_HPWORK=y # CONFIG_TIVA_DUMPPACKET is not set CONFIG_TIVA_BOARDMAC=y diff --git a/configs/eagle100/nsh/defconfig b/configs/eagle100/nsh/defconfig index af982ff487..f32a3000a7 100644 --- a/configs/eagle100/nsh/defconfig +++ b/configs/eagle100/nsh/defconfig @@ -257,7 +257,7 @@ CONFIG_TIVA_GPIOG_IRQS=y # CONFIG_TIVA_PROMISCUOUS is not set # CONFIG_TIVA_TIMESTAMP is not set # CONFIG_TIVA_BADCRC is not set -CONFIG_TIVA_ETHERNET_HPWORK=y +CONFIG_LM3S_ETHERNET_HPWORK=y # CONFIG_TIVA_DUMPPACKET is not set CONFIG_TIVA_BOARDMAC=y diff --git a/configs/eagle100/thttpd/defconfig b/configs/eagle100/thttpd/defconfig index 05d4be5f54..60d1f3ade7 100644 --- a/configs/eagle100/thttpd/defconfig +++ b/configs/eagle100/thttpd/defconfig @@ -250,7 +250,7 @@ CONFIG_TIVA_GPIOG_IRQS=y # CONFIG_TIVA_PROMISCUOUS is not set # CONFIG_TIVA_TIMESTAMP is not set # CONFIG_TIVA_BADCRC is not set -CONFIG_TIVA_ETHERNET_HPWORK=y +CONFIG_LM3S_ETHERNET_HPWORK=y # CONFIG_TIVA_DUMPPACKET is not set CONFIG_TIVA_BOARDMAC=y diff --git a/configs/ekk-lm3s9b96/nsh/defconfig b/configs/ekk-lm3s9b96/nsh/defconfig index fb38935f6e..c733dade36 100644 --- a/configs/ekk-lm3s9b96/nsh/defconfig +++ b/configs/ekk-lm3s9b96/nsh/defconfig @@ -252,7 +252,7 @@ CONFIG_TIVA_GPIOG_IRQS=y # CONFIG_TIVA_PROMISCUOUS is not set # CONFIG_TIVA_TIMESTAMP is not set # CONFIG_TIVA_BADCRC is not set -CONFIG_TIVA_ETHERNET_HPWORK=y +CONFIG_LM3S_ETHERNET_HPWORK=y # CONFIG_TIVA_DUMPPACKET is not set # CONFIG_TIVA_BOARDMAC is not set diff --git a/configs/lm3s6432-s2e/nsh/defconfig b/configs/lm3s6432-s2e/nsh/defconfig index 92f2f68964..ee2493f4f3 100644 --- a/configs/lm3s6432-s2e/nsh/defconfig +++ b/configs/lm3s6432-s2e/nsh/defconfig @@ -247,7 +247,7 @@ CONFIG_TIVA_GPIOB_IRQS=y # CONFIG_TIVA_PROMISCUOUS is not set # CONFIG_TIVA_TIMESTAMP is not set # CONFIG_TIVA_BADCRC is not set -CONFIG_TIVA_ETHERNET_HPWORK=y +CONFIG_LM3S_ETHERNET_HPWORK=y # CONFIG_TIVA_DUMPPACKET is not set CONFIG_TIVA_BOARDMAC=y diff --git a/configs/lm3s6965-ek/discover/defconfig b/configs/lm3s6965-ek/discover/defconfig index 91a26e61e7..ed9c7291f9 100644 --- a/configs/lm3s6965-ek/discover/defconfig +++ b/configs/lm3s6965-ek/discover/defconfig @@ -251,7 +251,7 @@ CONFIG_TIVA_GPIOG_IRQS=y # CONFIG_TIVA_PROMISCUOUS is not set # CONFIG_TIVA_TIMESTAMP is not set # CONFIG_TIVA_BADCRC is not set -CONFIG_TIVA_ETHERNET_HPWORK=y +CONFIG_LM3S_ETHERNET_HPWORK=y # CONFIG_TIVA_DUMPPACKET is not set # CONFIG_TIVA_BOARDMAC is not set diff --git a/configs/lm3s6965-ek/nsh/defconfig b/configs/lm3s6965-ek/nsh/defconfig index 91a26e61e7..ed9c7291f9 100644 --- a/configs/lm3s6965-ek/nsh/defconfig +++ b/configs/lm3s6965-ek/nsh/defconfig @@ -251,7 +251,7 @@ CONFIG_TIVA_GPIOG_IRQS=y # CONFIG_TIVA_PROMISCUOUS is not set # CONFIG_TIVA_TIMESTAMP is not set # CONFIG_TIVA_BADCRC is not set -CONFIG_TIVA_ETHERNET_HPWORK=y +CONFIG_LM3S_ETHERNET_HPWORK=y # CONFIG_TIVA_DUMPPACKET is not set # CONFIG_TIVA_BOARDMAC is not set diff --git a/configs/lm3s6965-ek/tcpecho/defconfig b/configs/lm3s6965-ek/tcpecho/defconfig index 6945c7a71f..2142ed9137 100644 --- a/configs/lm3s6965-ek/tcpecho/defconfig +++ b/configs/lm3s6965-ek/tcpecho/defconfig @@ -250,7 +250,7 @@ CONFIG_TIVA_GPIOG_IRQS=y # CONFIG_TIVA_PROMISCUOUS is not set # CONFIG_TIVA_TIMESTAMP is not set # CONFIG_TIVA_BADCRC is not set -CONFIG_TIVA_ETHERNET_HPWORK=y +CONFIG_LM3S_ETHERNET_HPWORK=y # CONFIG_TIVA_DUMPPACKET is not set # CONFIG_TIVA_BOARDMAC is not set diff --git a/configs/lm3s8962-ek/nsh/defconfig b/configs/lm3s8962-ek/nsh/defconfig index 45be5effd8..a13cba6072 100644 --- a/configs/lm3s8962-ek/nsh/defconfig +++ b/configs/lm3s8962-ek/nsh/defconfig @@ -261,7 +261,7 @@ CONFIG_TIVA_GPIOG_IRQS=y # CONFIG_TIVA_PROMISCUOUS is not set # CONFIG_TIVA_TIMESTAMP is not set # CONFIG_TIVA_BADCRC is not set -CONFIG_TIVA_ETHERNET_HPWORK=y +CONFIG_LM3S_ETHERNET_HPWORK=y # CONFIG_TIVA_DUMPPACKET is not set # CONFIG_TIVA_BOARDMAC is not set -- GitLab From 9c65b0321d79cf5853a83a73da55b90ab0a79f04 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 4 Dec 2016 06:24:24 -0600 Subject: [PATCH 589/734] Eliminate some warnings --- arch/arm/src/lpc17xx/lpc17_allocateheap.c | 2 +- configs/lincoln60/netnsh/defconfig | 2 +- configs/lincoln60/nsh/defconfig | 2 +- configs/lincoln60/thttpd-binfs/defconfig | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/src/lpc17xx/lpc17_allocateheap.c b/arch/arm/src/lpc17xx/lpc17_allocateheap.c index 20568f0457..dd1652bf18 100644 --- a/arch/arm/src/lpc17xx/lpc17_allocateheap.c +++ b/arch/arm/src/lpc17xx/lpc17_allocateheap.c @@ -136,7 +136,7 @@ # endif /* LPC17_HAVE_BANK1 && LPC17_BANK1_HEAPSIZE */ # else /* !LPC17_BANK0_HEAPSIZE */ - /* We have Bnak 0, but no memory is available for the heap there. + /* We have Bank 0, but no memory is available for the heap there. * Do we have Bank 1? Is any heap memory available in Bank 1? */ diff --git a/configs/lincoln60/netnsh/defconfig b/configs/lincoln60/netnsh/defconfig index 0d956981f6..1f6f544322 100644 --- a/configs/lincoln60/netnsh/defconfig +++ b/configs/lincoln60/netnsh/defconfig @@ -297,7 +297,7 @@ CONFIG_BOOT_RUNFROMFLASH=y # Boot Memory Configuration # CONFIG_RAM_START=0x10000000 -CONFIG_RAM_SIZE=65536 +CONFIG_RAM_SIZE=32768 # CONFIG_ARCH_HAVE_SDRAM is not set # diff --git a/configs/lincoln60/nsh/defconfig b/configs/lincoln60/nsh/defconfig index 024db858a4..0568982c09 100644 --- a/configs/lincoln60/nsh/defconfig +++ b/configs/lincoln60/nsh/defconfig @@ -274,7 +274,7 @@ CONFIG_BOOT_RUNFROMFLASH=y # Boot Memory Configuration # CONFIG_RAM_START=0x10000000 -CONFIG_RAM_SIZE=65536 +CONFIG_RAM_SIZE=32768 # CONFIG_ARCH_HAVE_SDRAM is not set # diff --git a/configs/lincoln60/thttpd-binfs/defconfig b/configs/lincoln60/thttpd-binfs/defconfig index abfe74e562..90f3ac8b54 100644 --- a/configs/lincoln60/thttpd-binfs/defconfig +++ b/configs/lincoln60/thttpd-binfs/defconfig @@ -297,7 +297,7 @@ CONFIG_BOOT_RUNFROMFLASH=y # Boot Memory Configuration # CONFIG_RAM_START=0x10000000 -CONFIG_RAM_SIZE=65536 +CONFIG_RAM_SIZE=32768 # CONFIG_ARCH_HAVE_SDRAM is not set # -- GitLab From 84900298b70608e686e38c57e7fbb9173df55158 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Sun, 4 Dec 2016 06:49:49 -0600 Subject: [PATCH 590/734] ARMv7-M SMP: Applied the latest changes for ARMv7A-SMP --- arch/arm/src/armv7-m/up_assert.c | 13 +++++++++++ arch/arm/src/armv7-m/up_schedulesigaction.c | 26 +++++++++++++++++++++ arch/arm/src/armv7-m/up_sigdeliver.c | 13 +++++++++-- 3 files changed, 50 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/armv7-m/up_assert.c b/arch/arm/src/armv7-m/up_assert.c index b34cfc7395..11f29cd653 100644 --- a/arch/arm/src/armv7-m/up_assert.c +++ b/arch/arm/src/armv7-m/up_assert.c @@ -53,6 +53,7 @@ #include "up_arch.h" #include "sched/sched.h" +#include "irq/irq.h" #include "up_internal.h" /**************************************************************************** @@ -319,6 +320,12 @@ static void up_dumpstate(void) #endif +#ifdef CONFIG_SMP + /* Show the CPU number */ + + _alert("CPU%d:\n", up_cpu_index()); +#endif + /* Then dump the registers (if available) */ up_registerdump(); @@ -351,6 +358,12 @@ static void _up_assert(int errorcode) (void)up_irq_save(); for (; ; ) { +#ifdef CONFIG_SMP + /* Try (again) to stop activity on other CPUs */ + + (void)spin_trylock(&g_cpu_irqlock); +#endif + #ifdef CONFIG_ARCH_LEDS board_autoled_on(LED_PANIC); up_mdelay(250); diff --git a/arch/arm/src/armv7-m/up_schedulesigaction.c b/arch/arm/src/armv7-m/up_schedulesigaction.c index cf70662510..fb6a4c167c 100644 --- a/arch/arm/src/armv7-m/up_schedulesigaction.c +++ b/arch/arm/src/armv7-m/up_schedulesigaction.c @@ -165,6 +165,19 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) #ifdef CONFIG_BUILD_PROTECTED CURRENT_REGS[REG_LR] = EXC_RETURN_PRIVTHR; #endif + +#ifdef CONFIG_SMP + /* In an SMP configuration, the interrupt disable logic also + * involves spinlocks that are configured per the TCB irqcount + * field. This is logically equivalent to enter_critical_section(). + * The matching call to leave_critical_section() will be + * performed in up_sigdeliver(). + */ + + DEBUGASSERT(tcb->irqcount < INT16_MAX); + tcb->irqcount++; +#endif + /* And make sure that the saved context in the TCB is the same * as the interrupt return context. */ @@ -211,6 +224,19 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) #ifdef CONFIG_BUILD_PROTECTED tcb->xcp.regs[REG_LR] = EXC_RETURN_PRIVTHR; #endif + +#ifdef CONFIG_SMP + /* In an SMP configuration, the interrupt disable logic also + * involves spinlocks that are configured per the TCB irqcount + * field. This is logically equivalent to enter_critical_section(); + * The matching leave_critical_section will be performed in + * The matching call to leave_critical_section() will be performed + * in up_sigdeliver(). + */ + + DEBUGASSERT(tcb->irqcount < INT16_MAX); + tcb->irqcount++; +#endif } } diff --git a/arch/arm/src/armv7-m/up_sigdeliver.c b/arch/arm/src/armv7-m/up_sigdeliver.c index 6169b51279..086ed882fc 100644 --- a/arch/arm/src/armv7-m/up_sigdeliver.c +++ b/arch/arm/src/armv7-m/up_sigdeliver.c @@ -124,9 +124,9 @@ void up_sigdeliver(void) /* Then restore the task interrupt state */ #ifdef CONFIG_ARMV7M_USEBASEPRI - up_irq_restore((uint8_t)regs[REG_BASEPRI]); + leave_critical_section((uint8_t)regs[REG_BASEPRI]); #else - up_irq_restore((uint16_t)regs[REG_PRIMASK]); + leave_critical_section((uint16_t)regs[REG_PRIMASK]); #endif /* Deliver the signal */ @@ -136,9 +136,18 @@ void up_sigdeliver(void) /* Output any debug messages BEFORE restoring errno (because they may * alter errno), then disable interrupts again and restore the original * errno that is needed by the user logic (it is probably EINTR). + * + * REVISIT: In SMP mode up_irq_save() probably only disables interrupts + * on the local CPU. We do not want to call enter_critical_section() + * here, however, because we don't want this state to stick after the + * call to up_fullcontextrestore(). + * + * I would prefer that all interrupts are disabled when + * up_fullcontextrestore() is called, but that may not be necessary. */ sinfo("Resuming\n"); + (void)up_irq_save(); rtcb->pterrno = saved_errno; -- GitLab From 13c9031a8dfeb2a5f98a6808b43122dcb5a740ae Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Sun, 4 Dec 2016 06:52:08 -0600 Subject: [PATCH 591/734] Fix DEBUGASSERT() in group_signal.c --- sched/group/group_signal.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/sched/group/group_signal.c b/sched/group/group_signal.c index ac8afca3e5..363cccf92a 100644 --- a/sched/group/group_signal.c +++ b/sched/group/group_signal.c @@ -93,12 +93,11 @@ static int group_signal_handler(pid_t pid, FAR void *arg) FAR sigactq_t *sigact; int ret; - DEBUGASSERT(tcb != NULL && tcb->group != NULL && info != NULL); - /* Get the TCB associated with the group member */ tcb = sched_gettcb(pid); - DEBUGASSERT(tcb ! = NULL); + DEBUGASSERT(tcb != NULL && tcb->group != NULL && info != NULL); + if (tcb) { /* Set this one as the default if we have not already set the default. */ -- GitLab From b3d182b5d503428cc70dae8c3f82b7055f62c77c Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Sun, 4 Dec 2016 07:06:17 -0600 Subject: [PATCH 592/734] Add support for the SAM5CMP-DB board --- configs/Kconfig | 10 + configs/README.txt | 3 + configs/sam4cmp-db/Kconfig | 7 + configs/sam4cmp-db/README.txt | 28 + configs/sam4cmp-db/include/board.h | 178 +++++ configs/sam4cmp-db/nsh/Make.defs | 111 +++ configs/sam4cmp-db/nsh/defconfig | 964 +++++++++++++++++++++++++++ configs/sam4cmp-db/nsh/setenv.sh | 73 ++ configs/sam4cmp-db/scripts/ld.script | 121 ++++ configs/sam4cmp-db/src/Makefile | 41 ++ configs/sam4cmp-db/src/sam4cmp-db.h | 68 ++ configs/sam4cmp-db/src/sam_boot.c | 91 +++ 12 files changed, 1695 insertions(+) create mode 100644 configs/sam4cmp-db/Kconfig create mode 100644 configs/sam4cmp-db/README.txt create mode 100644 configs/sam4cmp-db/include/board.h create mode 100644 configs/sam4cmp-db/nsh/Make.defs create mode 100644 configs/sam4cmp-db/nsh/defconfig create mode 100644 configs/sam4cmp-db/nsh/setenv.sh create mode 100644 configs/sam4cmp-db/scripts/ld.script create mode 100644 configs/sam4cmp-db/src/Makefile create mode 100644 configs/sam4cmp-db/src/sam4cmp-db.h create mode 100644 configs/sam4cmp-db/src/sam_boot.c diff --git a/configs/Kconfig b/configs/Kconfig index a0eeadad0f..6ef90c00ef 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -852,6 +852,12 @@ config ARCH_BOARD_SAM3UEK ---help--- The port of NuttX to the Atmel SAM3U-EK development board. +config ARCH_BOARD_SAM4CMP_DB + bool "Atmel SAM4CMP-DB development board" + depends on ARCH_CHIP_ATSAM4CMP16B + ---help--- + The port of NuttX to the Atmel SAM4CMP-DB development board. + config ARCH_BOARD_SAM4EEK bool "Atmel SAM4E-EK development board" depends on ARCH_CHIP_ATSAM4E16E @@ -1456,6 +1462,7 @@ config ARCH_BOARD default "samd21-xplained" if ARCH_BOARD_SAMD21_XPLAINED default "saml21-xplained" if ARCH_BOARD_SAML21_XPLAINED default "sam3u-ek" if ARCH_BOARD_SAM3UEK + default "sam4cmp-db" if ARCH_BOARD_SAM4CMP_DB default "sam4e-ek" if ARCH_BOARD_SAM4EEK default "sam4l-xplained" if ARCH_BOARD_SAM4L_XPLAINED default "sam4s-xplained" if ARCH_BOARD_SAM4S_XPLAINED @@ -1785,6 +1792,9 @@ endif if ARCH_BOARD_SAM3UEK source "configs/sam3u-ek/Kconfig" endif +if ARCH_BOARD_SAM4CMP_DB +source "configs/sam4cmp-db/Kconfig" +endif if ARCH_BOARD_SAM4EEK source "configs/sam4e-ek/Kconfig" endif diff --git a/configs/README.txt b/configs/README.txt index fa59055c6a..c7fe008e1d 100644 --- a/configs/README.txt +++ b/configs/README.txt @@ -600,6 +600,9 @@ configs/samd21-xplained configs/sam3u-ek The port of NuttX to the Atmel SAM3U-EK development board. +configs/sam4cmp-db + The port of NuttX to the Atmel SAM4CMP-DB development board. + configs/sam4e-ek The port of NuttX to the Atmel SAM4E-EK development board. This board features the SAM4E16 MCU running at up to 120MHz. diff --git a/configs/sam4cmp-db/Kconfig b/configs/sam4cmp-db/Kconfig new file mode 100644 index 0000000000..9080dfce40 --- /dev/null +++ b/configs/sam4cmp-db/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_SAM4CMP_DB +endif diff --git a/configs/sam4cmp-db/README.txt b/configs/sam4cmp-db/README.txt new file mode 100644 index 0000000000..efe90a6690 --- /dev/null +++ b/configs/sam4cmp-db/README.txt @@ -0,0 +1,28 @@ +README +^^^^^^ + +README for NuttX port to the SAM4CMP-DB board. + + http://www.atmel.com/tools/SAM4CMP-DB.aspx + +The board is intended to test NuttX SMP features for dual Cortex-M4. + + +Settings +^^^^^^^^ +1. Both CPUs are running at 92.160MHz with PLLB. +2. Serial console can be used via on-board USB-UART (115200/8/N/1) +3. Interrupt handlers such as timer and UART are handled on CPU0 +4. Both CPUs share internal SRAM0 (128KB) +5. SRAM1 is used to boot CPU1. +6. Cache controllers are disabled because of no snooping features. + +Status +^^^^^^ +Currently SMP freature works on the board but is not stable. + +1. "nsh> sleep 1 &" works without crash. +2. "nsh> smp " sometimes works but some assertions might happen. +3. "nsh> ostest " causes deadlocks during the test. + + diff --git a/configs/sam4cmp-db/include/board.h b/configs/sam4cmp-db/include/board.h new file mode 100644 index 0000000000..1339e6ec67 --- /dev/null +++ b/configs/sam4cmp-db/include/board.h @@ -0,0 +1,178 @@ +/************************************************************************************ + * configs/sam4cmp-db/include/board.h + * + * Copyright (C) 2016 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_SAM4CMP_DB_INCLUDE_BOARD_H +#define __CONFIGS_SAM4CMP_DB_INCLUDE_BOARD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ +/* After power-on reset, the sam3u device is running on a 4MHz internal RC. These + * definitions will configure clocking with MCK = 48MHz, PLLA = 96, and CPU=120MHz. + */ + +/* Main oscillator register settings */ + +#define BOARD_CKGR_MOR_MOSCXTST (63 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */ + +/* PLLA configuration: + * + * Source: 12MHz crystall at 12MHz + * PLLdiv: 10 + * PLLmul: 1 (bypassed) + * Fpll: (12MHz * 10) / 1 = 120MHz + */ + +#define BOARD_MAINOSC_FREQUENCY (8192000) +#define BOARD_CKGR_PLLAR_MUL (9 << PMC_CKGR_PLLAR_MUL_SHIFT) +#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS +#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) +#define BOARD_PLLA_FREQUENCY (10*BOARD_MAINOSC_FREQUENCY) + +/* PLLB configuration + * + * Source: MAIN clock (i.e. 8.192MHz) + * PLLdiv: 4 + * PLLmul: 45 + * Fpll: (8.192MHz * (44+1) / 4 = 92.120 MHz + */ + +#define BOARD_CKGR_PLLBR_SRCB (0 << PMC_CKGR_PLLBR_SRCB_SHIFT) +#define BOARD_CKGR_PLLBR_DIV (4 << PMC_CKGR_PLLBR_DIV_SHIFT) +#define BOARD_CKGR_PLLBR_MUL (44 << PMC_CKGR_PLLBR_MUL_SHIFT) +#define BOARD_CKGR_PLLBR_COUNT (63 << PMC_CKGR_PLLBR_COUNT_SHIFT) +#define BOARD_PLLB_FREQUENCY (92160000) + + +/* PMC master clock register settings */ + +#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLB +#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV1 +#define BOARD_MCK_FREQUENCY (BOARD_PLLB_FREQUENCY/1) +#define BOARD_CPU_FREQUENCY (BOARD_PLLB_FREQUENCY/1) + +/* USB UTMI PLL start-up time */ + +#define BOARD_CKGR_UCKR_UPLLCOUNT (3 << PMC_CKGR_UCKR_UPLLCOUNT_SHIFT) + +/* FLASH wait states: + * + * DC Characteristics + * + * Parameter Min Typ Max + * ---------------------- ----- ----- ---- + * Vddcore DC Supply Core 1.08V 1.2V 1.32V + * Vvddio DC Supply I/Os 1.62V 3.3V 3.6V + * + * Wait Maximum + * Vddcore Vvddio States Frequency (MHz) + * ------- ---------- ------ --------------- + * 1.08V 1.62-3.6V 0 16 + * " " " "-" " 1 33 + * " " " "-" " 2 50 + * " " " "-" " 3 67 + * " " " "-" " 4 84 + * " " " "-" " 5 100 + * 1.08V 2.7-3.6V 0 20 + * " " " "-" " 1 40 + * " " " "-" " 2 60 + * " " " "-" " 3 80 + * " " " "-" " 4 100 + * 1.2V 1.62-3.6V 0 17 + * " " " "-" " 1 34 + * " " " "-" " 2 52 + * " " " "-" " 3 69 + * " " " "-" " 4 87 + * " " " "-" " 5 104 + * " " " "-" " 6 121 + * 1.2V 2.7-3.6V 0 21 + * " " " "-" " 1 42 + * " " " "-" " 2 63 + * " " " "-" " 3 84 + * " " " "-" " 4 105 + * " " " "-" " 5 123 << SELECTION + */ + +#define BOARD_FWS 5 + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ +/************************************************************************************ + * Name: sam_boardinitialize + * + * Description: + * All SAM3U architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void sam_boardinitialize(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_SAM4CMP_DB_INCLUDE_BOARD_H */ diff --git a/configs/sam4cmp-db/nsh/Make.defs b/configs/sam4cmp-db/nsh/Make.defs new file mode 100644 index 0000000000..60acde6e28 --- /dev/null +++ b/configs/sam4cmp-db/nsh/Make.defs @@ -0,0 +1,111 @@ +############################################################################ +# configs/sam4cmp-db/nsh/Make.defs +# +# Copyright (C) 2016 Masayuki Ishikawa. All rights reserved. +# Author: Masayuki Ishikawa +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/ld.script +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/sam4cmp-db/nsh/defconfig b/configs/sam4cmp-db/nsh/defconfig new file mode 100644 index 0000000000..8dc7937a07 --- /dev/null +++ b/configs/sam4cmp-db/nsh/defconfig @@ -0,0 +1,964 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +CONFIG_EXPERIMENTAL=y +# CONFIG_DEFAULT_SMALL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +CONFIG_DEBUG_FEATURES=y + +# +# Debug SYSLOG Output Controls +# +CONFIG_DEBUG_ERROR=y +CONFIG_DEBUG_WARN=y +# CONFIG_DEBUG_INFO is not set +CONFIG_DEBUG_ASSERTIONS=y + +# +# Subsystem Debug Options +# +# CONFIG_DEBUG_BINFMT is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_DEBUG_GRAPHICS is not set +# CONFIG_DEBUG_LIB is not set +# CONFIG_DEBUG_MM is not set +# CONFIG_DEBUG_SCHED is not set + +# +# OS Function Debug Options +# +# CONFIG_DEBUG_IRQ is not set + +# +# Driver Debug Options +# +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_TIMER is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +# CONFIG_ARCH_HAVE_HEAPCHECK is not set +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ARCH_HAVE_CUSTOMOPT=y +CONFIG_DEBUG_NOOPT=y +# CONFIG_DEBUG_CUSTOMOPT is not set +# CONFIG_DEBUG_FULLOPT is not set + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_MISOC is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_XTENSA is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LC823450 is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +CONFIG_ARCH_CHIP_SAM34=y +# CONFIG_ARCH_CHIP_SAMV7 is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM3 is not set +CONFIG_ARCH_CORTEXM4=y +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="sam34" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARMV7M_LAZYFPU is not set +# CONFIG_ARCH_HAVE_FPU is not set +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set +# CONFIG_DEBUG_HARDFAULT is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y +CONFIG_ARMV7M_HAVE_STACKCHECK=y +# CONFIG_ARMV7M_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set +# CONFIG_SERIAL_TERMIOS is not set + +# +# AT91SAM3/4 Configuration Options +# +# CONFIG_ARCH_CHIP_ATSAM3U4E is not set +# CONFIG_ARCH_CHIP_ATSAM3U4C is not set +# CONFIG_ARCH_CHIP_ATSAM3U2E is not set +# CONFIG_ARCH_CHIP_ATSAM3U2C is not set +# CONFIG_ARCH_CHIP_ATSAM3U1E is not set +# CONFIG_ARCH_CHIP_ATSAM3U1C is not set +# CONFIG_ARCH_CHIP_ATSAM3X8E is not set +# CONFIG_ARCH_CHIP_ATSAM3X8C is not set +# CONFIG_ARCH_CHIP_ATSAM3X4E is not set +# CONFIG_ARCH_CHIP_ATSAM3X4C is not set +# CONFIG_ARCH_CHIP_ATSAM3A8C is not set +# CONFIG_ARCH_CHIP_ATSAM3A4C is not set +CONFIG_ARCH_CHIP_ATSAM4CMP16B=y +# CONFIG_ARCH_CHIP_ATSAM4LC2C is not set +# CONFIG_ARCH_CHIP_ATSAM4LC2B is not set +# CONFIG_ARCH_CHIP_ATSAM4LC2A is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4C is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4B is not set +# CONFIG_ARCH_CHIP_ATSAM4LC4A is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2C is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2B is not set +# CONFIG_ARCH_CHIP_ATSAM4LS2A is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4C is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4B is not set +# CONFIG_ARCH_CHIP_ATSAM4LS4A is not set +# CONFIG_ARCH_CHIP_ATSAM4SD32C is not set +# CONFIG_ARCH_CHIP_ATSAM4SD32B is not set +# CONFIG_ARCH_CHIP_ATSAM4SD16C is not set +# CONFIG_ARCH_CHIP_ATSAM4SD16B is not set +# CONFIG_ARCH_CHIP_ATSAM4SA16C is not set +# CONFIG_ARCH_CHIP_ATSAM4SA16B is not set +# CONFIG_ARCH_CHIP_ATSAM4S16C is not set +# CONFIG_ARCH_CHIP_ATSAM4S16B is not set +# CONFIG_ARCH_CHIP_ATSAM4S8C is not set +# CONFIG_ARCH_CHIP_ATSAM4S8B is not set +# CONFIG_ARCH_CHIP_ATSAM4E16E is not set +# CONFIG_ARCH_CHIP_ATSAM4E16C is not set +# CONFIG_ARCH_CHIP_ATSAM4E8E is not set +# CONFIG_ARCH_CHIP_ATSAM4E8C is not set +# CONFIG_ARCH_CHIP_SAM3U is not set +# CONFIG_ARCH_CHIP_SAM3X is not set +# CONFIG_ARCH_CHIP_SAM3A is not set +CONFIG_ARCH_CHIP_SAM4CM=y +# CONFIG_ARCH_CHIP_SAM4L is not set +# CONFIG_ARCH_CHIP_SAM4E is not set +# CONFIG_ARCH_CHIP_SAM4S is not set + +# +# AT91SAM3/4 Peripheral Support +# +# CONFIG_SAM34_ADC12B is not set +# CONFIG_SAM34_AES is not set +# CONFIG_SAM34_DMAC1 is not set +# CONFIG_SAM34_SLCDC is not set +# CONFIG_SAM34_SPI0 is not set +# CONFIG_SAM34_TC0 is not set +# CONFIG_SAM34_TC1 is not set +# CONFIG_SAM34_TWI is not set +# CONFIG_SAM34_TWIM is not set +# CONFIG_SAM34_TWIS is not set +# CONFIG_SAM34_TWIM0 is not set +# CONFIG_SAM34_TWIS0 is not set +# CONFIG_SAM34_TWIM1 is not set +# CONFIG_SAM34_TWIS1 is not set +CONFIG_SAM34_UART0=y +# CONFIG_SAM34_UART1 is not set +# CONFIG_SAM34_USART0 is not set +# CONFIG_SAM34_USART1 is not set +# CONFIG_SAM34_USART2 is not set +# CONFIG_SAM34_USART3 is not set +# CONFIG_SAM34_WDT is not set + +# +# AT91SAM3/4 External Memory Configuration +# + +# +# AT91SAM3/4 GPIO Interrupt Configuration +# +# CONFIG_SAM34_HAVE_GPIOD_IRQ is not set +# CONFIG_SAM34_HAVE_GPIOE_IRQ is not set +# CONFIG_SAM34_HAVE_GPIOF_IRQ is not set +# CONFIG_SAM34_GPIO_IRQ is not set +# CONFIG_SAM34_TC is not set + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +CONFIG_ARCH_HAVE_MULTICPU=y +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +CONFIG_ARCH_HAVE_RAMFUNCS=y +CONFIG_ARCH_RAMFUNCS=y +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=6124 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_SIZE=131072 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_SAM4CMP_DB=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="sam4cmp-db" + +# +# Common Board Options +# + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +# CONFIG_LIB_BOARDCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +CONFIG_DISABLE_ENVIRON=y + +# +# Clocks and Timers +# +CONFIG_ARCH_HAVE_TICKLESS=y +# CONFIG_SCHED_TICKLESS is not set +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_ARCH_HAVE_TIMEKEEPING is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2013 +CONFIG_START_MONTH=6 +CONFIG_START_DAY=12 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +CONFIG_SPINLOCK=y +CONFIG_SMP=y +CONFIG_SMP_NCPUS=2 +CONFIG_SMP_IDLETHREAD_STACKSIZE=2048 +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=0 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=24 +CONFIG_MAX_TASKS=32 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_HPWORK is not set +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +# CONFIG_ARCH_HAVE_I2CRESET is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set +# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set +# CONFIG_ARCH_HAVE_SPI_BITORDER is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_ONESHOT is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +CONFIG_UART0_SERIALDRIVER=y +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +# CONFIG_SERIAL_TIOCSERGSTRUCT is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +CONFIG_UART0_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART0 Configuration +# +CONFIG_UART0_RXBUFSIZE=256 +CONFIG_UART0_TXBUFSIZE=256 +CONFIG_UART0_BAUD=115200 +CONFIG_UART0_BITS=8 +CONFIG_UART0_PARITY=0 +CONFIG_UART0_2STOP=0 +# CONFIG_UART0_IFLOWCONTROL is not set +# CONFIG_UART0_OFLOWCONTROL is not set +# CONFIG_UART0_DMA is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set +# CONFIG_DRIVERS_CONTACTLESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +CONFIG_FS_READABLE=y +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +CONFIG_FS_PROCFS=y +# CONFIG_FS_PROCFS_REGISTER is not set + +# +# Exclude individual procfs entries +# +# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set +# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# +# CONFIG_WIRELESS is not set + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_IOCTL_VARIADIC is not set +# CONFIG_LIBC_WCHAR is not set +# CONFIG_LIBC_LOCALE is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set +# CONFIG_LIBC_NETDB is not set +# CONFIG_NETDB_HOSTFILE is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_CCTYPE is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +CONFIG_EXAMPLES_OSTEST=y +CONFIG_EXAMPLES_OSTEST_LOOPS=1 +CONFIG_EXAMPLES_OSTEST_STACKSIZE=8192 +CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=8 +CONFIG_EXAMPLES_OSTEST_RR_RANGE=10000 +CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 +CONFIG_EXAMPLES_OSTEST_WAITRESULT=y +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RFID_READUID is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +CONFIG_EXAMPLES_SMP=y +CONFIG_EXAMPLES_SMP_NBARRIER_THREADS=8 +CONFIG_EXAMPLES_SMP_PRIORITY=100 +CONFIG_EXAMPLES_SMP_STACKSIZE=2048 +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set +# CONFIG_FSUTILS_PASSWD is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_BAS is not set +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_MINIBASIC is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=80 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +CONFIG_NSH_CMDPARMS=y +CONFIG_NSH_MAXARGUMENTS=6 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_NSH_DISABLE_PRINTF=y +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Configure Command Options +# +# CONFIG_NSH_CMDOPT_DF_H is not set +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_CMDOPT_HEXDUMP=y +CONFIG_NSH_PROC_MOUNTPOINT="/proc" +CONFIG_NSH_FILEIOSIZE=512 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +# CONFIG_NSH_ARCHINIT is not set +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_SYSTEM is not set +# CONFIG_SYSTEM_TEE is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/sam4cmp-db/nsh/setenv.sh b/configs/sam4cmp-db/nsh/setenv.sh new file mode 100644 index 0000000000..651b20b308 --- /dev/null +++ b/configs/sam4cmp-db/nsh/setenv.sh @@ -0,0 +1,73 @@ +#!/bin/bash +# configs/sam4cmp-db/nsh/setenv.sh +# +# Copyright (C) 2016 Masayuki Ishikawa. All rights reserved. +# Author: Masayuki Ishikawa +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the Atmel GCC +# toolchain under Windows. You will also have to edit this if you install +# this toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Atmel/Atmel Toolchain/ARM GCC/Native/4.7.3.99/arm-gnu-toolchain/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" + +# These are the Cygwin paths to the locations where I installed the Atollic +# toolchain under windows. You will also have to edit this if you install +# the Atollic toolchain in any other location. /usr/bin is added before +# the Atollic bin path because there is are binaries named gcc.exe and g++.exe +# at those locations as well. +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/configs/sam4cmp-db/scripts/ld.script b/configs/sam4cmp-db/scripts/ld.script new file mode 100644 index 0000000000..d82568f84f --- /dev/null +++ b/configs/sam4cmp-db/scripts/ld.script @@ -0,0 +1,121 @@ +/**************************************************************************** + * configs/sam4cmp-db/scripts/ld.script + * + * Copyright (C) 2016 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The ATSAM4CM has 1MB of FLASH beginning at address 0x0100:0000 and + * 128KB of SRAM beginning at address 0x2000:0000 + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x01000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } >flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } >flash + __exidx_end = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + _eronly = LOADADDR(.data); + + .ramfunc ALIGN(4): { + _sramfuncs = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfuncs = ABSOLUTE(.); + } > sram AT > flash + + _framfuncs = LOADADDR(.ramfunc); + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/sam4cmp-db/src/Makefile b/configs/sam4cmp-db/src/Makefile new file mode 100644 index 0000000000..2463d7e867 --- /dev/null +++ b/configs/sam4cmp-db/src/Makefile @@ -0,0 +1,41 @@ +############################################################################ +# configs/sam4cmp-db/src/Makefile +# +# Copyright (C) 2016 Masayuki Ishikawa. All rights reserved. +# Author: Masayuki Ishikawa +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = sam_boot.c + +include $(TOPDIR)/configs/Board.mk diff --git a/configs/sam4cmp-db/src/sam4cmp-db.h b/configs/sam4cmp-db/src/sam4cmp-db.h new file mode 100644 index 0000000000..e665614571 --- /dev/null +++ b/configs/sam4cmp-db/src/sam4cmp-db.h @@ -0,0 +1,68 @@ +/************************************************************************************ + * configs/sam4cmp-db/src/sam4cmp-db.h + * + * Copyright (C) 2016 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_SAM4CMP_DB_SRC_SAM4CMP_DB_H +#define __CONFIGS_SAM4CMP_DB_SRC_SAM4CMP_DB_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include + +#include +#include + +#include "chip/sam_pinmap.h" + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_SAM4CMP_DB_SRC_SAM4CMP_DB_H */ diff --git a/configs/sam4cmp-db/src/sam_boot.c b/configs/sam4cmp-db/src/sam_boot.c new file mode 100644 index 0000000000..ee34da638d --- /dev/null +++ b/configs/sam4cmp-db/src/sam_boot.c @@ -0,0 +1,91 @@ +/************************************************************************************ + * configs/sam4cmp-db/src/sam_boot.c + * + * Copyright (C) 2016 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include + +#include "sam4cmp-db.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: sam_boardinitialize + * + * Description: + * All SAM3/4 architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void sam_boardinitialize(void) +{ +} + +/**************************************************************************** + * Name: board_initialize + * + * Description: + * If CONFIG_BOARD_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_initialize(). board_initialize() will be + * called immediately after up_intitialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_INITIALIZE +void board_initialize(void) +{ +} +#endif /* CONFIG_BOARD_INITIALIZE */ -- GitLab From 9f323692f4329abd777306e015725f04546b8413 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 4 Dec 2016 07:07:39 -0600 Subject: [PATCH 593/734] Update README files --- Documentation/README.html | 4 +++- README.txt | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/README.html b/Documentation/README.html index 4c7137a37b..3ded166a0a 100644 --- a/Documentation/README.html +++ b/Documentation/README.html @@ -8,7 +8,7 @@

    NuttX README Files

    -

    Last Updated: November 14, 2016

    +

    Last Updated: December 4, 2016

    @@ -221,6 +221,8 @@ nuttx/ | | `- README.txt | |- sam3u-ek/ | | `- README.txt + | |- sam4cmp-db + | | `- README.txt | |- sam4e-ek/ | | `- README.txt | |- sam4l-xplained/ diff --git a/README.txt b/README.txt index 89a41af473..ee43ef25cc 100644 --- a/README.txt +++ b/README.txt @@ -1437,6 +1437,8 @@ nuttx/ | | `- README.txt | |- sam3u-ek/ | | `- README.txt + | |- sam4cmp-db + | | `- README.txt | |- sam4e-ek/ | | `- README.txt | |- sam4l-xplained/ -- GitLab From d92a7886a4ae707f0de4e5e2bbd8e64d95696340 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Sun, 4 Dec 2016 07:23:31 -0600 Subject: [PATCH 594/734] SAM3/4: Add SMP support for the dual-core SAM4CM --- arch/arm/src/sam34/Kconfig | 1 + arch/arm/src/sam34/Make.defs | 24 +- arch/arm/src/sam34/chip/sam4cm_memorymap.h | 1 + arch/arm/src/sam34/chip/sam_pmc.h | 13 +- arch/arm/src/sam34/sam4cm_cpuidlestack.c | 136 +++++++++ arch/arm/src/sam34/sam4cm_cpuindex.c | 77 +++++ arch/arm/src/sam34/sam4cm_cpupause.c | 328 +++++++++++++++++++++ arch/arm/src/sam34/sam4cm_cpustart.c | 228 ++++++++++++++ arch/arm/src/sam34/sam4cm_idle.c | 77 +++++ arch/arm/src/sam34/sam_irq.c | 4 + arch/arm/src/sam34/sam_start.c | 7 + 11 files changed, 884 insertions(+), 12 deletions(-) create mode 100644 arch/arm/src/sam34/sam4cm_cpuidlestack.c create mode 100644 arch/arm/src/sam34/sam4cm_cpuindex.c create mode 100644 arch/arm/src/sam34/sam4cm_cpupause.c create mode 100644 arch/arm/src/sam34/sam4cm_cpustart.c create mode 100644 arch/arm/src/sam34/sam4cm_idle.c diff --git a/arch/arm/src/sam34/Kconfig b/arch/arm/src/sam34/Kconfig index df13714792..01194134c2 100644 --- a/arch/arm/src/sam34/Kconfig +++ b/arch/arm/src/sam34/Kconfig @@ -240,6 +240,7 @@ config ARCH_CHIP_SAM3A config ARCH_CHIP_SAM4CM bool default n + select ARCH_HAVE_MULTICPU select ARCH_HAVE_TICKLESS config ARCH_CHIP_SAM4L diff --git a/arch/arm/src/sam34/Make.defs b/arch/arm/src/sam34/Make.defs index dab10fb45e..9b4e75079a 100644 --- a/arch/arm/src/sam34/Make.defs +++ b/arch/arm/src/sam34/Make.defs @@ -50,13 +50,17 @@ CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S CMN_ASRCS += up_testset.S vfork.S CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c -CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_idle.c up_initialize.c +CMN_CSRCS += up_mdelay.c up_udelay.c up_exit.c up_initialize.c CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_memfault.c up_modifyreg8.c CMN_CSRCS += up_modifyreg16.c up_modifyreg32.c up_releasepending.c CMN_CSRCS += up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_unblocktask.c up_usestack.c CMN_CSRCS += up_doirq.c up_hardfault.c up_svcall.c up_vfork.c +ifneq ($(CONFIG_SMP),y) +CMN_CSRCS += up_idle.c +endif + # Configuration-dependent common files ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y) @@ -198,14 +202,22 @@ endif ifeq ($(CONFIG_ARCH_CHIP_SAM4CM),y) ifeq ($(CONFIG_SAM34_TC),y) CHIP_CSRCS += sam4cm_tc.c + ifeq ($(CONFIG_SAM34_ONESHOT),y) CHIP_CSRCS += sam4cm_oneshot.c sam4cm_oneshot_lowerhalf.c -endif +endif # CONFIG_SAM34_ONESHOT + ifeq ($(CONFIG_SAM34_FREERUN),y) CHIP_CSRCS += sam4cm_freerun.c -endif +endif # CONFIG_SAM34_FREERUN + ifeq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += sam4cm_tickless.c -endif -endif -endif +endif # CONFIG_SCHED_TICKLESS +endif # CONFIG_SAM34_TC + +ifeq ($(CONFIG_SMP),y) +CHIP_CSRCS += sam4cm_cpuindex.c sam4cm_cpuidlestack.c +CHIP_CSRCS += sam4cm_cpupause.c sam4cm_cpustart.c sam4cm_idle.c +endif # CONFIG_SMP +endif # CONFIG_ARCH_CHIP_SAM4CM diff --git a/arch/arm/src/sam34/chip/sam4cm_memorymap.h b/arch/arm/src/sam34/chip/sam4cm_memorymap.h index c0b2de041b..d719e268c0 100644 --- a/arch/arm/src/sam34/chip/sam4cm_memorymap.h +++ b/arch/arm/src/sam34/chip/sam4cm_memorymap.h @@ -65,6 +65,7 @@ /* Internal SRAM memory region */ #define SAM_INTSRAM0_BASE 0x20000000 /* For SAM3U compatibility */ +#define SAM_INTSRAM1_BASE 0x20080000 /* 0x20080000-0x200fffff: Internal SRAM 1 */ #define SAM_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32MB bit-band region */ /* 0x24000000-0x3fffffff: Undefined */ /* Peripherals address region */ diff --git a/arch/arm/src/sam34/chip/sam_pmc.h b/arch/arm/src/sam34/chip/sam_pmc.h index 6514d1f42e..d7a75f6b03 100644 --- a/arch/arm/src/sam34/chip/sam_pmc.h +++ b/arch/arm/src/sam34/chip/sam_pmc.h @@ -402,10 +402,10 @@ # define PMC_MCKR_CPCSS_SHIFT (16) # define PMC_MCKR_CPCSS_MASK (0x7 << PMC_MCKR_CPCSS_SHIFT) # define PMC_MCKR_CPCSS_SLOW (0 << PMC_MCKR_CPCSS_SHIFT) /* Slow Clock */ -# define PMC_MCKR_CCPSS_MAIN (1 << PMC_MCKR_CPCSS_SHIFT) /* Main Clock */ -# define PMC_MCKR_CCPSS_PLLA (2 << PMC_MCKR_CPCSS_SHIFT) /* PLLA Clock */ -# define PMC_MCKR_CCPSS_PLLB (3 << PMC_MCKR_CPCSS_SHIFT) /* PLLB Clock */ -# define PMC_MCKR_CCPSS_MCK (4 << PMC_MCKR_CPCSS_SHIFT) /* Master Clock */ +# define PMC_MCKR_CPCSS_MAIN (1 << PMC_MCKR_CPCSS_SHIFT) /* Main Clock */ +# define PMC_MCKR_CPCSS_PLLA (2 << PMC_MCKR_CPCSS_SHIFT) /* PLLA Clock */ +# define PMC_MCKR_CPCSS_PLLB (3 << PMC_MCKR_CPCSS_SHIFT) /* PLLB Clock */ +# define PMC_MCKR_CPCSS_MCK (4 << PMC_MCKR_CPCSS_SHIFT) /* Master Clock */ # define PMC_MCKR_CPPRES_SHIFT (20) # define PMC_MCKR_CPPRES_MASK (0xF << PMC_MCKR_CPPRES_SHIFT) # define PMC_MCKR_CPPRES(D) (((D) - 1) << PMC_MCKR_CPPRES_SHIFT) @@ -547,13 +547,14 @@ /* Peripheral Clock Status Register 1 */ #if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3X) || \ - defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) + defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E) || \ + defined(CONFIG_ARCH_CHIP_SAM4CM) # define PMC_PIDH(n) (1 << ((n) - 32)) # define PMC_PID32 (1 << 0) /* Bit 0: PID32 */ # define PMC_PID33 (1 << 1) /* Bit 1: PID33 */ # define PMC_PID34 (1 << 2) /* Bit 2: PID34 */ # if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3X) || \ - defined(CONFIG_ARCH_CHIP_SAM4E) + defined(CONFIG_ARCH_CHIP_SAM4E) || defined(CONFIG_ARCH_CHIP_SAM4CM) # define PMC_PID35 (1 << 3) /* Bit 3: PID35 */ # define PMC_PID36 (1 << 4) /* Bit 4: PID36 */ # define PMC_PID37 (1 << 5) /* Bit 5: PID37 */ diff --git a/arch/arm/src/sam34/sam4cm_cpuidlestack.c b/arch/arm/src/sam34/sam4cm_cpuidlestack.c new file mode 100644 index 0000000000..411ebfaad7 --- /dev/null +++ b/arch/arm/src/sam34/sam4cm_cpuidlestack.c @@ -0,0 +1,136 @@ +/**************************************************************************** + * arch/arm/src/sam34/sam4cm_cpuidlestack.c + * + * Copyright (C) 2016 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "up_internal.h" + +#ifdef CONFIG_SMP + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + sched_process_timer(); +#else + + /* Sleep until an interrupt occurs to save power */ + + asm("WFI"); + +#endif +} + +/**************************************************************************** + * Name: up_cpu_idlestack + * + * Description: + * Allocate a stack for the CPU[n] IDLE task (n > 0) if appropriate and + * setup up stack-related information in the IDLE task's TCB. This + * function is always called before up_cpu_start(). This function is + * only called for the CPU's initial IDLE task; up_create_task is used for + * all normal tasks, pthreads, and kernel threads for all CPUs. + * + * The initial IDLE task is a special case because the CPUs can be started + * in different wans in different environments: + * + * 1. The CPU may already have been started and waiting in a low power + * state for up_cpu_start(). In this case, the IDLE thread's stack + * has already been allocated and is already in use. Here + * up_cpu_idlestack() only has to provide information about the + * already allocated stack. + * + * 2. The CPU may be disabled but started when up_cpu_start() is called. + * In this case, a new stack will need to be created for the IDLE + * thread and this function is then equivalent to: + * + * return up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL); + * + * The following TCB fields must be initialized by this function: + * + * - adj_stack_size: Stack size after adjustment for hardware, processor, + * etc. This value is retained only for debug purposes. + * - stack_alloc_ptr: Pointer to allocated stack + * - adj_stack_ptr: Adjusted stack_alloc_ptr for HW. The initial value of + * the stack pointer. + * + * Inputs: + * - cpu: CPU index that indicates which CPU the IDLE task is + * being created for. + * - tcb: The TCB of new CPU IDLE task + * - stack_size: The requested stack size for the IDLE task. At least + * this much must be allocated. This should be + * CONFIG_SMP_STACK_SIZE. + * + ****************************************************************************/ + +int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size) +{ +#if CONFIG_SMP_NCPUS > 1 + (void)up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL); +#endif + return OK; +} + +#endif /* CONFIG_SMP */ diff --git a/arch/arm/src/sam34/sam4cm_cpuindex.c b/arch/arm/src/sam34/sam4cm_cpuindex.c new file mode 100644 index 0000000000..867d36e5c1 --- /dev/null +++ b/arch/arm/src/sam34/sam4cm_cpuindex.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * arch/arm/src/sam34/sam4cm_cpuindex.c + * + * Copyright (C) 2016 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "mpu.h" + +#ifdef CONFIG_SMP + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_cpu_index + * + * Description: + * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + * Input Parameters: + * None + * + * Returned Value: + * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + ****************************************************************************/ + +int up_cpu_index(void) +{ + /* MPU is not supported on CM4P1 */ + + return (getreg32(MPU_TYPE) == 0) ? 1 : 0; +} + +#endif /* CONFIG_SMP */ + + diff --git a/arch/arm/src/sam34/sam4cm_cpupause.c b/arch/arm/src/sam34/sam4cm_cpupause.c new file mode 100644 index 0000000000..9b9d126f25 --- /dev/null +++ b/arch/arm/src/sam34/sam4cm_cpupause.c @@ -0,0 +1,328 @@ +/**************************************************************************** + * arch/arm/src/sam34/sam4cm_cpupause.c + * + * Copyright (C) 2016 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "sched/sched.h" +#include "up_internal.h" +#include "chip/sam4cm_ipc.h" + +#ifdef CONFIG_SMP + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if 0 +# define DPRINTF(fmt, args...) _err(fmt, ##args) +#else +# define DPRINTF(fmt, args...) do {} while (0) +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* These spinlocks are used in the SMP configuration in order to implement + * up_cpu_pause(). The protocol for CPUn to pause CPUm is as follows + * + * 1. The up_cpu_pause() implementation on CPUn locks both g_cpu_wait[m] + * and g_cpu_paused[m]. CPUn then waits spinning on g_cpu_paused[m]. + * 2. CPUm receives the interrupt it (1) unlocks g_cpu_paused[m] and + * (2) locks g_cpu_wait[m]. The first unblocks CPUn and the second + * blocks CPUm in the interrupt handler. + * + * When CPUm resumes, CPUn unlocks g_cpu_wait[m] and the interrupt handler + * on CPUm continues. CPUm must, of course, also then unlock g_cpu_wait[m] + * so that it will be ready for the next pause operation. + */ + +static volatile spinlock_t g_cpu_wait[CONFIG_SMP_NCPUS]; +static volatile spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_cpu_pausereq + * + * Description: + * Return true if a pause request is pending for this CPU. + * + * Input Parameters: + * cpu - The index of the CPU to be queried + * + * Returned Value: + * true = a pause request is pending. + * false = no pasue request is pending. + * + ****************************************************************************/ + +bool up_cpu_pausereq(int cpu) +{ + return spin_islocked(&g_cpu_paused[cpu]); +} + +/**************************************************************************** + * Name: up_cpu_paused + * + * Description: + * Handle a pause request from another CPU. Normally, this logic is + * executed from interrupt handling logic within the architecture-specific + * However, it is sometimes necessary necessary to perform the pending + * pause operation in other contexts where the interrupt cannot be taken + * in order to avoid deadlocks. + * + * This function performs the following operations: + * + * 1. It saves the current task state at the head of the current assigned + * task list. + * 2. It waits on a spinlock, then + * 3. Returns from interrupt, restoring the state of the new task at the + * head of the ready to run list. + * + * Input Parameters: + * cpu - The index of the CPU to be paused + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused(int cpu) +{ + FAR struct tcb_s *tcb = this_task(); + + /* Update scheduler parameters */ + + sched_suspend_scheduler(tcb); + + /* Save the current context at CURRENT_REGS into the TCB at the head + * of the assigned task list for this CPU. + */ + + up_savestate(tcb->xcp.regs); + + /* Wait for the spinlock to be released */ + + spin_unlock(&g_cpu_paused[cpu]); + spin_lock(&g_cpu_wait[cpu]); + + /* Restore the exception context of the tcb at the (new) head of the + * assigned task list. + */ + + tcb = this_task(); + + /* Reset scheduler parameters */ + + sched_resume_scheduler(tcb); + + /* Then switch contexts. Any necessary address environment changes + * will be made when the interrupt returns. + */ + + up_restorestate(tcb->xcp.regs); + spin_unlock(&g_cpu_wait[cpu]); + + return OK; +} + +/**************************************************************************** + * Name: arm_pause_handler + * + * Description: + * Inter-CPU interrupt handler + * + * Input Parameters: + * Standard interrupt handler inputs + * + * Returned Value: + * Should always return OK + * + ****************************************************************************/ + +int arm_pause_handler(int irq, void *c) +{ + int cpu = up_cpu_index(); + + /* Clear : Pause IRQ */ + /* IPC Interrupt Clear Command Register (write-only) */ + + if (1 == cpu) + { + DPRINTF("CPU0 -> CPU1\n"); + putreg32(0x1, SAM_IPC1_ICCR); + } + else + { + DPRINTF("CPU1 -> CPU0\n"); + putreg32(0x1, SAM_IPC0_ICCR); + } + + /* Check for false alarms. Such false could occur as a consequence of + * some deadlock breaking logic that might have already serviced the SG2 + * interrupt by calling up_cpu_paused. + */ + + if (spin_islocked(&g_cpu_paused[cpu])) + { + return up_cpu_paused(cpu); + } + + return OK; +} + +/**************************************************************************** + * Name: up_cpu_pause + * + * Description: + * Save the state of the current task at the head of the + * g_assignedtasks[cpu] task list and then pause task execution on the + * CPU. + * + * This function is called by the OS when the logic executing on one CPU + * needs to modify the state of the g_assignedtasks[cpu] list for another + * CPU. + * + * Input Parameters: + * cpu - The index of the CPU to be stopped/ + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +int up_cpu_pause(int cpu) +{ + DPRINTF("cpu=%d\n",cpu); + + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu()); + + /* Take the both spinlocks. The g_cpu_wait spinlock will prevent the SGI2 + * handler from returning until up_cpu_resume() is called; g_cpu_paused + * is a handshake that will prefent this function from returning until + * the CPU is actually paused. + */ + + spin_lock(&g_cpu_wait[cpu]); + spin_lock(&g_cpu_paused[cpu]); + + DEBUGASSERT(spin_islocked(&g_cpu_wait[cpu]) && + spin_islocked(&g_cpu_paused[cpu])); + + /* Execute Pause IRQ to CPU(cpu) */ + /* Set IPC Interrupt (IRQ0) (write-only) */ + + if (cpu == 1) + { + putreg32(0x1, SAM_IPC1_ISCR); + } + else + { + putreg32(0x1, SAM_IPC0_ISCR); + } + + /* Wait for the other CPU to unlock g_cpu_paused meaning that + * it is fully paused and ready for up_cpu_resume(); + */ + + spin_lock(&g_cpu_paused[cpu]); + + spin_unlock(&g_cpu_paused[cpu]); + + /* On successful return g_cpu_wait will be locked, the other CPU will be + * spinninf on g_cpu_wait and will not continue until g_cpu_resume() is + * called. g_cpu_paused will be unlocked in any case. + */ + + return 0; +} + +/**************************************************************************** + * Name: up_cpu_resume + * + * Description: + * Restart the cpu after it was paused via up_cpu_pause(), restoring the + * state of the task at the head of the g_assignedtasks[cpu] list, and + * resume normal tasking. + * + * This function is called after up_cpu_pause in order resume operation of + * the CPU after modifying its g_assignedtasks[cpu] list. + * + * Input Parameters: + * cpu - The index of the CPU being re-started. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +int up_cpu_resume(int cpu) +{ + DPRINTF("cpu=%d\n",cpu); + + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu()); + + /* Release the spinlock. Releasing the spinlock will cause the SGI2 + * handler on 'cpu' to continue and return from interrupt to the newly + * established thread. + */ + + DEBUGASSERT(spin_islocked(&g_cpu_wait[cpu]) && + !spin_islocked(&g_cpu_paused[cpu])); + + spin_unlock(&g_cpu_wait[cpu]); + + return 0; +} + +#endif /* CONFIG_SMP */ diff --git a/arch/arm/src/sam34/sam4cm_cpustart.c b/arch/arm/src/sam34/sam4cm_cpustart.c new file mode 100644 index 0000000000..44c8d9508c --- /dev/null +++ b/arch/arm/src/sam34/sam4cm_cpustart.c @@ -0,0 +1,228 @@ +/**************************************************************************** + * arch/arm/src/sam34/sam4cm_cpustart.c + * + * Copyright (C) 2016 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "nvic.h" +#include "up_arch.h" +#include "sched/sched.h" +#include "init/init.h" +#include "up_internal.h" +#include "chip/sam_pmc.h" +#include "chip/sam_rstc.h" +#include "chip/sam4cm_ipc.h" +#include "sam4cm_periphclks.h" + +#ifdef CONFIG_SMP + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if 0 +# define DPRINTF(fmt, args...) _err(fmt, ##args) +#else +# define DPRINTF(fmt, args...) do {} while (0) +#endif + +#define CPU1_VECTOR_RESETV (SAM_INTSRAM1_BASE) +#define CPU1_VECTOR_ISTACK (SAM_INTSRAM1_BASE + 4) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile static spinlock_t g_cpu1_boot; +extern int arm_pause_handler(int irq, void *c); + +/**************************************************************************** + * Name: cpu1_boot + * + * Description: + * This is the boot vector for CM4P1 + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static void cpu1_boot(void) +{ + int cpu; + + /* Disable CMCC1 */ + + putreg32(0, 0x48018008); + while ((getreg32(0x4801800c) & 0x01) != 0); + + cpu = up_cpu_index(); + DPRINTF("cpu = %d\n", cpu); + + if (cpu == 1) + { + /* Use CPU0 vectors */ + + putreg32((uint32_t)&_stext, NVIC_VECTAB); + sam_ipc1_enableclk(); + + /* Clear : write-only */ + + putreg32(0x1, SAM_IPC1_ICCR); + + /* Enable : write-only */ + + putreg32(0x1, SAM_IPC1_IECR); + irq_attach(SAM_IRQ_IPC1, arm_pause_handler); + up_enable_irq(SAM_IRQ_IPC1); + } + + spin_unlock(&g_cpu1_boot); + + /* Then transfer control to the IDLE task */ + + (void)os_idle_task(0, NULL); +} + +/**************************************************************************** + * Name: up_cpu_start + * + * Description: + * In an SMP configution, only one CPU is initially active (CPU 0). System + * initialization occurs on that single thread. At the completion of the + * initialization of the OS, just before beginning normal multitasking, + * the additional CPUs would be started by calling this function. + * + * Each CPU is provided the entry point to is IDLE task when started. A + * TCB for each CPU's IDLE task has been initialized and placed in the + * CPU's g_assignedtasks[cpu] list. Not stack has been alloced or + * initialized. + * + * The OS initialization logic calls this function repeatedly until each + * CPU has been started, 1 through (CONFIG_SMP_NCPUS-1). + * + * Input Parameters: + * cpu - The index of the CPU being started. This will be a numeric + * value in the range of from one to (CONFIG_SMP_NCPUS-1). (CPU + * 0 is already active) + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +int up_cpu_start(int cpu) +{ + struct tcb_s *tcb = current_task(cpu); + + DPRINTF("cpu=%d\n",cpu); + + if (cpu != 1) + return -1; + + /* Reset coprocessor */ + + putreg32(0x5a000000, SAM_RSTC_CPMR); + + /* Enable Coprocessor Bus Master Clock (write-only) */ + + putreg32(PMC_CPKEY | PMC_CPBMCK, SAM_PMC_SCER); + + /* Enable Coprocessor Clock (write-only) */ + + putreg32(PMC_CPKEY | PMC_CPCK, SAM_PMC_SCER); + + /* Set Coprocessor Clock Prescalar */ + + modifyreg32(SAM_PMC_MCKR, PMC_MCKR_CPPRES_MASK, 0); + + /* Set Coprocessor Clock Source */ + + modifyreg32(SAM_PMC_MCKR, PMC_MCKR_CPCSS_MASK, PMC_MCKR_CPCSS_PLLB); + + /* Unreset coprocessor pheripheral */ + + putreg32(0x5a000010, SAM_RSTC_CPMR); + + /* Enable clock for SRAM1 where CPU1 starts (write-only) */ + + putreg32(PMC_PID42, SAM_PMC_PCER1); + + /* Clear SRAM1 */ + + memset((void *)SAM_INTSRAM1_BASE, 0, 16 * 1024); + + /* Copy initial vectors for CPU1 */ + + putreg32((uint32_t)tcb->adj_stack_ptr, CPU1_VECTOR_RESETV); + putreg32((uint32_t)cpu1_boot, CPU1_VECTOR_ISTACK); + + spin_lock(&g_cpu1_boot); + + /* Unreset coprocessor */ + + putreg32(0x5a000011, SAM_RSTC_CPMR); + + /* IRQ setup CPU1->CPU0 */ + + sam_ipc0_enableclk(); + putreg32(0x1, SAM_IPC0_ICCR); /* clear : write-only */ + putreg32(0x1, SAM_IPC0_IECR); /* enable : write-only */ + irq_attach(SAM_IRQ_IPC0, arm_pause_handler); + up_enable_irq(SAM_IRQ_IPC0); + + spin_lock(&g_cpu1_boot); + + /* CPU1 boot done */ + + spin_unlock(&g_cpu1_boot); + + return 0; +} + +#endif /* CONFIG_SMP */ diff --git a/arch/arm/src/sam34/sam4cm_idle.c b/arch/arm/src/sam34/sam4cm_idle.c new file mode 100644 index 0000000000..9c3810136c --- /dev/null +++ b/arch/arm/src/sam34/sam4cm_idle.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * arch/arm/src/sam34/sam4cm_idle.c + * + * Copyright (C) 2016 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include "up_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + sched_process_timer(); +#else + + /* Sleep until an interrupt occurs to save power */ + + asm("WFI"); + +#endif +} diff --git a/arch/arm/src/sam34/sam_irq.c b/arch/arm/src/sam34/sam_irq.c index 68f1777434..0b3286d0ca 100644 --- a/arch/arm/src/sam34/sam_irq.c +++ b/arch/arm/src/sam34/sam_irq.c @@ -84,7 +84,11 @@ * CURRENT_REGS for portability. */ +#ifdef CONFIG_SMP +volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; +#else volatile uint32_t *g_current_regs[1]; +#endif /* This is the address of the exception vector table (determined by the * linker script). diff --git a/arch/arm/src/sam34/sam_start.c b/arch/arm/src/sam34/sam_start.c index abae1da761..71537f1c38 100644 --- a/arch/arm/src/sam34/sam_start.c +++ b/arch/arm/src/sam34/sam_start.c @@ -241,6 +241,13 @@ void __start(void) const uint32_t *src; uint32_t *dest; +#ifdef CONFIG_SMP + /* Disable CMCC0 */ + + putreg32(0, 0x4007c008); + while ((getreg32(0x4007c00c) & 0x01) != 0); +#endif + #ifdef CONFIG_ARMV7M_STACKCHECK /* Set the stack limit before we attempt to call any functions */ -- GitLab From 7c4e3e21b8c6a37fe6edb8e4d2e5aa4ba1915fa8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 4 Dec 2016 09:06:08 -0600 Subject: [PATCH 595/734] Allow option to enable IP address conversions even when the IP address family is not supported. --- libc/Kconfig | 10 ++++++++++ libc/net/lib_inetntoa.c | 4 ++-- libc/net/lib_inetntop.c | 16 ++++++++-------- libc/net/lib_inetpton.c | 16 ++++++++-------- 4 files changed, 28 insertions(+), 18 deletions(-) diff --git a/libc/Kconfig b/libc/Kconfig index dead1df0b3..757b115d81 100644 --- a/libc/Kconfig +++ b/libc/Kconfig @@ -575,6 +575,16 @@ config TLS_NELEM endif # TLS +config LIBC_IPv4_ADDRCONV + bool "IPv4 address conversions" + default n + depends on !NET_IPv4 + +config LIBC_IPv6_ADDRCONV + bool "IPv6 address conversions" + default n + depends on !NET_IPv6 + config LIBC_NETDB bool default n diff --git a/libc/net/lib_inetntoa.c b/libc/net/lib_inetntoa.c index a25364ce2d..7914accdc2 100644 --- a/libc/net/lib_inetntoa.c +++ b/libc/net/lib_inetntoa.c @@ -44,7 +44,7 @@ #include #include -#ifdef CONFIG_NET_IPv4 +#if defined(CONFIG_NET_IPv4) || defined(CONFIG_LIBC_IPv4_ADDRCONV) /**************************************************************************** * Public Functions @@ -78,4 +78,4 @@ FAR char *_inet_ntoa(in_addr_t in) return buffer; } #endif -#endif /* CONFIG_NET_IPv4 */ +#endif /* CONFIG_NET_IPv4 || CONFIG_LIBC_IPv4_ADDRCONV */ diff --git a/libc/net/lib_inetntop.c b/libc/net/lib_inetntop.c index 2a6037f97c..196dfa62e3 100644 --- a/libc/net/lib_inetntop.c +++ b/libc/net/lib_inetntop.c @@ -62,10 +62,10 @@ */ #ifdef CONFIG_NETDB_HOSTFILE -# undef CONFIG_NET_IPv4 -# undef CONFIG_NET_IPv6 -# define CONFIG_NET_IPv4 1 -# define CONFIG_NET_IPv6 1 +# undef CONFIG_LIBC_IPv4_ADDRCONV +# undef CONFIG_LIBC_IPv6_ADDRCONV +# define CONFIG_LIBC_IPv4_ADDRCONV 1 +# define CONFIG_LIBC_IPv6_ADDRCONV 1 #endif /**************************************************************************** @@ -97,7 +97,7 @@ * ****************************************************************************/ -#ifdef CONFIG_NET_IPv4 +#if defined(CONFIG_NET_IPv4) || defined(CONFIG_LIBC_IPv4_ADDRCONV) static int inet_ipv4_ntop(FAR const void *src, FAR char *dest, socklen_t size) { FAR char *ptr; @@ -141,7 +141,7 @@ static int inet_ipv4_ntop(FAR const void *src, FAR char *dest, socklen_t size) * ****************************************************************************/ -#ifdef CONFIG_NET_IPv6 +#if defined(CONFIG_NET_IPv6) || defined(CONFIG_LIBC_IPv6_ADDRCONV) static int inet_ipv6_ntop(FAR const void *src, FAR char *dest, socklen_t size) { FAR const struct in6_addr *in6_addr; @@ -265,13 +265,13 @@ FAR const char *inet_ntop(int af, FAR const void *src, FAR char *dest, switch (af) { -#ifdef CONFIG_NET_IPv4 +#if defined(CONFIG_NET_IPv4) || defined(CONFIG_LIBC_IPv4_ADDRCONV) case AF_INET: ret = inet_ipv4_ntop(src, dest, size); break; #endif -#ifdef CONFIG_NET_IPv6 +#if defined(CONFIG_NET_IPv6) || defined(CONFIG_LIBC_IPv6_ADDRCONV) case AF_INET6: ret = inet_ipv6_ntop(src, dest, size); break; diff --git a/libc/net/lib_inetpton.c b/libc/net/lib_inetpton.c index 8b5eb77dd1..93a8804b72 100644 --- a/libc/net/lib_inetpton.c +++ b/libc/net/lib_inetpton.c @@ -64,10 +64,10 @@ */ #ifdef CONFIG_NETDB_HOSTFILE -# undef CONFIG_NET_IPv4 -# undef CONFIG_NET_IPv6 -# define CONFIG_NET_IPv4 1 -# define CONFIG_NET_IPv6 1 +# undef CONFIG_LIBC_IPv4_ADDRCONV +# undef CONFIG_LIBC_IPv6_ADDRCONV +# define CONFIG_LIBC_IPv4_ADDRCONV 1 +# define CONFIG_LIBC_IPv6_ADDRCONV 1 #endif /**************************************************************************** @@ -93,7 +93,7 @@ * ****************************************************************************/ -#ifdef CONFIG_NET_IPv4 +#if defined(CONFIG_NET_IPv4) || defined(CONFIG_LIBC_IPv4_ADDRCONV) static int inet_ipv4_pton(FAR const char *src, FAR void *dest) { size_t srcoffset; @@ -203,7 +203,7 @@ static int inet_ipv4_pton(FAR const char *src, FAR void *dest) * ****************************************************************************/ -#ifdef CONFIG_NET_IPv6 +#if defined(CONFIG_NET_IPv6) || defined(CONFIG_LIBC_IPv6_ADDRCONV) static int inet_ipv6_pton(FAR const char *src, FAR void *dest) { size_t srcoffset; @@ -393,12 +393,12 @@ int inet_pton(int af, FAR const char *src, FAR void *dest) switch (af) { -#ifdef CONFIG_NET_IPv4 +#if defined(CONFIG_NET_IPv4) || defined(CONFIG_LIBC_IPv4_ADDRCONV) case AF_INET: return inet_ipv4_pton(src, dest); #endif -#ifdef CONFIG_NET_IPv6 +#if defined(CONFIG_NET_IPv6) || defined(CONFIG_LIBC_IPv6_ADDRCONV) case AF_INET6: return inet_ipv6_pton(src, dest); #endif -- GitLab From 44b7975a5ea261068d15d9f421c68f8ecfa6112b Mon Sep 17 00:00:00 2001 From: Gong Darcy Date: Sun, 4 Dec 2016 10:07:46 -0600 Subject: [PATCH 596/734] SSD1306: Fix errors in SPI mode configuration --- drivers/lcd/ssd1306.h | 2 +- drivers/lcd/ssd1306_spi.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/lcd/ssd1306.h b/drivers/lcd/ssd1306.h index b04f2bc400..9fd38cc020 100644 --- a/drivers/lcd/ssd1306.h +++ b/drivers/lcd/ssd1306.h @@ -276,7 +276,7 @@ void ssd1306_sendblk(FAR struct ssd1306_dev_s *priv, uint8_t *data, uint8_t len) #ifdef CONFIG_LCD_SSD1306_SPI void ssd1306_select(FAR struct ssd1306_dev_s *priv, bool cs); void ssd1306_cmddata(FAR struct ssd1306_dev_s *priv, bool cmd); -static inline void ssd1306_configspi(FAR struct spi_dev_s *spi) +static inline void ssd1306_configspi(FAR struct spi_dev_s *spi); #else # define ssd1306_select(priv, cs) diff --git a/drivers/lcd/ssd1306_spi.c b/drivers/lcd/ssd1306_spi.c index 9f3817a7b6..33d6d61961 100644 --- a/drivers/lcd/ssd1306_spi.c +++ b/drivers/lcd/ssd1306_spi.c @@ -45,7 +45,7 @@ #include #include - +#include #include "ssd1306.h" #if defined(CONFIG_LCD_SSD1306) && defined(CONFIG_LCD_SSD1306_SPI) @@ -109,7 +109,7 @@ void ssd1306_sendblk(FAR struct ssd1306_dev_s *priv, uint8_t *data, uint8_t len) { /* Send byte value to display */ - (void)SPI_SNDBLOCK(priv, data, len); + (void)SPI_SNDBLOCK(priv->spi, data, len); } /**************************************************************************** -- GitLab From ff76ebfd31328c7df71341d5fab3b62a64a2be10 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 4 Dec 2016 15:25:43 -0600 Subject: [PATCH 597/734] SAMA5 does not build when executing from SDRAM before board frequencies are not constant. Rather, the bootloader configures the clocking and we must derive the clocking from the MCK left by the bootloader. This means lots more computations. This is untested on initial commit because I don't have a good PWM test setup right now. --- arch/arm/src/sama5/chip/sam_pwm.h | 3 + arch/arm/src/sama5/sam_pwm.c | 382 +++++++++++++++++------------- 2 files changed, 218 insertions(+), 167 deletions(-) diff --git a/arch/arm/src/sama5/chip/sam_pwm.h b/arch/arm/src/sama5/chip/sam_pwm.h index aa5ca2ed0f..8aef808f29 100644 --- a/arch/arm/src/sama5/chip/sam_pwm.h +++ b/arch/arm/src/sama5/chip/sam_pwm.h @@ -286,6 +286,7 @@ # define PWM_CLK_DIVA(n) ((uint32_t)(n) << PWM_CLK_DIVA_SHIFT) /* CLKA clock = clock selected by PREA / DIVA */ #define PWM_CLK_PREA_SHIFT (8) /* Bits 8-11: CLKA Source Clock Selection */ #define PWM_CLK_PREA_MASK (15 << PWM_CLK_PREA_SHIFT) +# define PWM_CLK_PREA_DIV(n) ((uint32_t)(n) << PWM_CLK_PREA_SHIFT) # define PWM_CLK_PREA_DIV1 (0 << PWM_CLK_PREA_SHIFT) /* MCK */ # define PWM_CLK_PREA_DIV2 (1 << PWM_CLK_PREA_SHIFT) /* MCK/2 */ # define PWM_CLK_PREA_DIV4 (2 << PWM_CLK_PREA_SHIFT) /* MCK/4 */ @@ -298,11 +299,13 @@ # define PWM_CLK_PREA_DIV512 (9 << PWM_CLK_PREA_SHIFT) /* MCK/512 */ # define PWM_CLK_PREA_DIV1024 (10 << PWM_CLK_PREA_SHIFT) /* MCK/1024 */ #define PWM_CLK_DIVB_SHIFT (16) /* Bits 16-23: CLKB Divide Factor */ +#define PWM_CLK_DIVB_MASK (0xff << PWM_CLK_DIVB_SHIFT) # define PWM_CLK_DIVB_OFF (0 << PWM_CLK_DIVB_SHIFT) /* CLKB clock = off */ # define PWM_CLK_DIVB_PREB (1 << PWM_CLK_DIVB_SHIFT) /* CLKB clock = clock selected by PREB */ # define PWM_CLK_DIVB(n) ((uint32_t)(n) << PWM_CLK_DIVB_SHIFT) /* CLKB clock = clock selected by PREB / DIVB */ #define PWM_CLK_PREB_SHIFT (24) /* Bits 24-27: CLKB Source Clock Selection */ #define PWM_CLK_PREB_MASK (15 << PWM_CLK_PREB_SHIFT) +# define PWM_CLK_PREB_DIV(n) ((uint32_t)(n) << PWM_CLK_PREB_SHIFT) # define PWM_CLK_PREB_DIV1 (0 << PWM_CLK_PREB_SHIFT) /* MCK */ # define PWM_CLK_PREB_DIV2 (1 << PWM_CLK_PREB_SHIFT) /* MCK/2 */ # define PWM_CLK_PREB_DIV4 (2 << PWM_CLK_PREB_SHIFT) /* MCK/4 */ diff --git a/arch/arm/src/sama5/sam_pwm.c b/arch/arm/src/sama5/sam_pwm.c index d523da24a1..898a6e04e8 100644 --- a/arch/arm/src/sama5/sam_pwm.c +++ b/arch/arm/src/sama5/sam_pwm.c @@ -82,154 +82,14 @@ # warning CONFIG_PWM_PULSECOUNT no supported by this driver. #endif -/* Are we using CLKA? CLKB? If so, what frequency? Select the prescaler - * value that allows the largest, valid divider value. This may not be - * optimal in all cases, but in general should provide a reasonable frequency - * value. - * - * frequency = MCK / prescaler / div - * - * Pick smallest prescaler such that: - * - * prescaler = MCK / frequency / div < 256 - * - * Then: - * - * div = MCK / prescaler / frequency - * - * Calulcated Values - * - * CLKn_PRE = CLKn prescaler value - * PWM_CLK_PREn = CLKn prescaler register setting - * CLKn_DIV = CLKn divider value - * PWM_CLK_DIVn = CLKn divider register setting - * CLKn_FREQUENCY = Actual resulting CLKn frequency - */ - -#ifdef CONFIG_SAMA5_PWM_CLKA +/* Are we using CLKA? CLKB? If so, at what frequency? */ -# if !defined(CONFIG_SAMA5_PWM_CLKA_FREQUENCY) +#if defined(CONFIG_SAMA5_PWM_CLKA) && !defined(CONFIG_SAMA5_PWM_CLKA_FREQUENCY) # error CONFIG_SAMA5_PWM_CLKA_FREQUENCY is not defined - -# elif (BOARD_MCK_FREQUENCY / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) < 256 -# define CLKA_PRE_BITS PWM_CLK_PREA_DIV1 -# define CLKA_PRE 1 - -# elif (BOARD_MCK_FREQUENCY / 2 / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) < 256 -# define CLKA_PRE_BITS PWM_CLK_PREA_DIV2 -# define CLKA_PRE 2 - -# elif (BOARD_MCK_FREQUENCY / 4 / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) < 256 -# define CLKA_PRE_BITS PWM_CLK_PREA_DIV4 -# define CLKA_PRE 4 - -# elif (BOARD_MCK_FREQUENCY / 8 / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) < 256 -# define CLKA_PRE_BITS PWM_CLK_PREA_DIV8 -# define CLKA_PRE 8 - -# elif (BOARD_MCK_FREQUENCY / 16 / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) < 256 -# define CLKA_PRE_BITS PWM_CLK_PREA_DIV16 -# define CLKA_PRE 16 - -# elif (BOARD_MCK_FREQUENCY / 32 / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) < 256 -# define CLKA_PRE_BITS PWM_CLK_PREA_DIV32 -# define CLKA_PRE 32 - -# elif (BOARD_MCK_FREQUENCY / 64 / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) < 256 -# define CLKA_PRE_BITS PWM_CLK_PREA_DIV64 -# define CLKA_PRE 64 - -# elif (BOARD_MCK_FREQUENCY / 128 / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) < 256 -# define CLKA_PRE_BITS PWM_CLK_PREA_DIV128 -# define CLKA_PRE 128 - -# elif (BOARD_MCK_FREQUENCY / 256 / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) < 256 -# define CLKA_PRE_BITS PWM_CLK_PREA_DIV256 -# define CLKA_PRE 256 - -# elif (BOARD_MCK_FREQUENCY / 512 / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) < 256 -# define CLKA_PRE_BITS PWM_CLK_PREA_DIV512 -# define CLKA_PRE 512 - -# elif (BOARD_MCK_FREQUENCY / 1024 / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) < 256 -# define CLKA_PRE_BITS PWM_CLK_PREA_DIV1024 -# define CLKA_PRE 1024 - -# else -# error Cannot realize CONFIG_SAMA5_PWM_CLKA_FREQUENCY -# endif - -# define CLKA_DIV (BOARD_MCK_FREQUENCY / CLKA_PRE / CONFIG_SAMA5_PWM_CLKA_FREQUENCY) -# define CLKA_FREQUENCY (BOARD_MCK_FREQUENCY / CLKA_PRE / CLKA_DIV) -# define CLKA_DIV_BITS PWM_CLK_DIVA(CLKA_DIV) - -#else -# undef CONFIG_SAMA5_PWM_CLKA_FREQUENCY -# define CLKA_PRE_BITS PWM_CLK_PREA_DIV1 -# define CLKA_DIV_BITS PWM_CLK_DIVA_OFF #endif -#ifdef CONFIG_SAMA5_PWM_CLKB - -# if !defined(CONFIG_SAMA5_PWM_CLKB_FREQUENCY) +#if defined(CONFIG_SAMA5_PWM_CLKB) && !defined(CONFIG_SAMA5_PWM_CLKB_FREQUENCY) # error CONFIG_SAMA5_PWM_CLKB_FREQUENCY is not defined - -# elif (BOARD_MCK_FREQUENCY / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) < 256 -# define CLKB_PRE_BITS PWM_CLK_PREB_DIV1 -# define CLKB_PRE 1 - -# elif (BOARD_MCK_FREQUENCY / 2 / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) < 256 -# define CLKB_PRE_BITS PWM_CLK_PREB_DIV2 -# define CLKB_PRE 2 - -# elif (BOARD_MCK_FREQUENCY / 4 / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) < 256 -# define CLKB_PRE_BITS PWM_CLK_PREB_DIV4 -# define CLKB_PRE 4 - -# elif (BOARD_MCK_FREQUENCY / 8 / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) < 256 -# define CLKB_PRE_BITS PWM_CLK_PREB_DIV8 -# define CLKB_PRE 8 - -# elif (BOARD_MCK_FREQUENCY / 16 / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) < 256 -# define CLKB_PRE_BITS PWM_CLK_PREB_DIV16 -# define CLKB_PRE 16 - -# elif (BOARD_MCK_FREQUENCY / 32 / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) < 256 -# define CLKB_PRE_BITS PWM_CLK_PREB_DIV32 -# define CLKB_PRE 32 - -# elif (BOARD_MCK_FREQUENCY / 64 / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) < 256 -# define CLKB_PRE_BITS PWM_CLK_PREB_DIV64 -# define CLKB_PRE 64 - -# elif (BOARD_MCK_FREQUENCY / 128 / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) < 256 -# define CLKB_PRE_BITS PWM_CLK_PREB_DIV128 -# define CLKB_PRE 128 - -# elif (BOARD_MCK_FREQUENCY / 256 / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) < 256 -# define CLKB_PRE_BITS PWM_CLK_PREB_DIV256 -# define CLKB_PRE 256 - -# elif (BOARD_MCK_FREQUENCY / 512 / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) < 256 -# define CLKB_PRE_BITS PWM_CLK_PREB_DIV512 -# define CLKB_PRE 512 - -# elif (BOARD_MCK_FREQUENCY / 1024 / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) < 256 -# define CLKB_PRE_BITS PWM_CLK_PREB_DIV1024 -# define CLKB_PRE 1024 - -# else -# error Cannot realize CONFIG_SAMA5_PWM_CLKB_FREQUENCY -# endif - -# define CLKB_DIV (BOARD_MCK_FREQUENCY / CLKB_PRE / CONFIG_SAMA5_PWM_CLKB_FREQUENCY) -# define CLKB_FREQUENCY (BOARD_MCK_FREQUENCY / CLKB_PRE / CLKB_DIV) -# define CLKB_DIV_BITS PWM_CLK_DIVB(CLKB_DIV) - -#else -# undef CONFIG_SAMA5_PWM_CLKB_FREQUENCY -# define CLKB_PRE_BITS PWM_CLK_PREB_DIV1 -# define CLKB_DIV_BITS PWM_CLK_DIVB_OFF #endif #ifdef CONFIG_SAMA5_PWM_CHAN0 @@ -237,27 +97,27 @@ # undef CONFIG_SAMA5_PWM_CHAN0_CLKA # undef CONFIG_SAMA5_PWM_CHAN0_CLKB # if CONFIG_SAMA5_PWM_CHAN0_MCKDIV == 1 -# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 0 +# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 0 # elif CONFIG_SAMA5_PWM_CHAN0_MCKDIV == 2 -# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 1 +# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 1 # elif CONFIG_SAMA5_PWM_CHAN0_MCKDIV == 4 -# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 2 +# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 2 # elif CONFIG_SAMA5_PWM_CHAN0_MCKDIV == 8 -# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 3 +# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 3 # elif CONFIG_SAMA5_PWM_CHAN0_MCKDIV == 16 -# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 4 +# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 4 # elif CONFIG_SAMA5_PWM_CHAN0_MCKDIV == 32 -# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 5 +# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 5 # elif CONFIG_SAMA5_PWM_CHAN0_MCKDIV == 64 -# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 6 +# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 6 # elif CONFIG_SAMA5_PWM_CHAN0_MCKDIV == 128 -# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 7 +# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 7 # elif CONFIG_SAMA5_PWM_CHAN0_MCKDIV == 256 -# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 8 +# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 8 # elif CONFIG_SAMA5_PWM_CHAN0_MCKDIV == 512 -# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 9 +# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 9 # elif CONFIG_SAMA5_PWM_CHAN0_MCKDIV == 1024 -# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 = 10 +# define SAMA5_PWM_CHAN0_MCKDIV_LOG2 10 # else # error Unsupported MCK divider value # endif @@ -485,6 +345,11 @@ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, /* Initialization */ +static unsigned int pwm_clk_prescaler_log2(uint32_t mck, uint32_t fclk); +static unsigned int pwm_clk_divider(uint32_t mck, uint32_t fclk, + unsigned int prelog2); +static uint32_t pwm_clk_frequency(uint32_t mck, unsigned int prelog2, + unsigned int div); static void pwm_resetpins(FAR struct sam_pwm_chan_s *chan); /**************************************************************************** @@ -779,6 +644,7 @@ static uint32_t pwm_getreg(struct sam_pwm_chan_s *chan, int offset) * ****************************************************************************/ +#ifdef CONFIG_DEBUG_PWM_INFO /* Currently only used for debug output */ static uint32_t pwm_chan_getreg(struct sam_pwm_chan_s *chan, int offset) { uintptr_t regaddr; @@ -800,6 +666,7 @@ static uint32_t pwm_chan_getreg(struct sam_pwm_chan_s *chan, int offset) return regval; } +#endif /**************************************************************************** * Name: pwm_putreg @@ -1073,6 +940,11 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev, FAR const struct pwm_info_s *info) { FAR struct sam_pwm_chan_s *chan = (FAR struct sam_pwm_chan_s *)dev; +#if defined(CONFIG_SAMA5_PWM_CLKA) || defined(CONFIG_SAMA5_PWM_CLKB) + unsigned int prelog2; + unsigned int div; + uint32_t mck; +#endif uint32_t regval; uint32_t cprd; uint32_t fsrc; @@ -1086,21 +958,35 @@ static int pwm_start(FAR struct pwm_lowerhalf_s *dev, switch (chan->clksrc) { case PWM_CLKSRC_MCK: - regval = PWM_CMR_CPRE_MCKDIV(chan->divlog2); - fsrc = BOARD_MCK_FREQUENCY >> chan->divlog2; + { + regval = PWM_CMR_CPRE_MCKDIV(chan->divlog2); + fsrc = BOARD_MCK_FREQUENCY >> chan->divlog2; + } break; #ifdef CONFIG_SAMA5_PWM_CLKA case PWM_CLKSRC_CLKA: - regval = PWM_CMR_CPRE_CLKA; - fsrc = CLKA_FREQUENCY; + { + regval = pwm_getreg(chan, SAM_PWM_CLK_OFFSET); + prelog2 = (unsigned int)((regval & PWM_CLK_PREA_MASK) >> PWM_CLK_PREA_SHIFT); + div = (unsigned int)((regval & PWM_CLK_DIVA_MASK) >> PWM_CLK_DIVA_SHIFT); + mck = BOARD_MCK_FREQUENCY; + fsrc = pwm_clk_frequency(mck, prelog2, div); + regval = PWM_CMR_CPRE_CLKA; + } break; #endif #ifdef CONFIG_SAMA5_PWM_CLKB case PWM_CLKSRC_CLKB: - regval = PWM_CMR_CPRE_CLKB; - fsrc = CLKB_FREQUENCY; + { + regval = pwm_getreg(chan, SAM_PWM_CLK_OFFSET); + prelog2 = (unsigned int)((regval & PWM_CLK_PREB_MASK) >> PWM_CLK_PREB_SHIFT); + div = (unsigned int)((regval & PWM_CLK_DIVB_MASK) >> PWM_CLK_DIVB_SHIFT); + mck = BOARD_MCK_FREQUENCY; + fsrc = pwm_clk_frequency(mck, prelog2, div); + regval = PWM_CMR_CPRE_CLKB; + } break; #endif @@ -1223,18 +1109,156 @@ static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg } /**************************************************************************** - * Name: pwm_ioctl + * Name: pwm_clk_prescaler_log2 + * + * Description: + * Return log2 of the clock prescaler value. The PWM clock divisor + * register fields use this kind of value. The return value of this + * function can be converted into a PWM clock register value or an absolute + * prescaler value by applying the following operations (macros defined in + * chip/sam_pwm.h): + * + * This function selects the prescaler value that allows the largest, valid + * divider value. This may not be optimal in all cases, but in general + * should provide a reasonable frequency value. The frequency is given by: + * + * frequency = MCK / prescaler / div + * + * The divider has a range of 1-255. Pick smallest prescaler such that: + * + * prescaler = MCK / frequency / div < 256 + * + * Example usage given: + * unsigned int prelog2; + * unsigned int prescaler; + * uint32_t regbits; + * + * For clock A: + * prelog2 = pwm_clk_prescaler_log2(BOARD_MCK_FREQUENCY, + * CONFIG_SAMA5_PWM_CLKA_FREQUENCY ) + * regbits = PWM_CLK_PREA_DIV(prelog2); + * prescaler = (1 << prelog2) + * + * For clock B: + * prelog2 = pwm_clk_prescaler_log2(BOARD_MCK_FREQUENCY, + * CONFIG_SAMA5_PWM_CLKB_FREQUENCY ) + * regbits = PWM_CLK_PREB_DIV(prelog2); + * prescaler = (1 << prelog2) + * + * Input parameters: + * mck - The main clock frequency + * fclk - The desired clock A or B frequency + * + * Returned Value: + * The select value of log2(prescaler) in the range 0-10 corresponding to + * the actual prescaler value in the range 1-1024. + * + ****************************************************************************/ + +static unsigned int pwm_clk_prescaler_log2(uint32_t mck, uint32_t fclk) +{ + uint32_t unscaled; + unsigned int prelog2; + + unscaled = mck / fclk; + prelog2 = 0; + + while (unscaled >= 256) + { + unscaled >>= 1; + prelog2++; + } + + DEBUGASSERT(prelog2 <= 10); + if (prelog2 > 10) + { + prelog2 = 10; + } + + return prelog2; +} + +/**************************************************************************** + * Name: pwm_clk_divider + * + * Description: + * Given that we have already selected the prescaler value, select the + * divider in the range of 1 through 255. The CLKA/B frequency is + * determined by both the prescaler and divider valuess: + * + * frequency = MCK / prescaler / div + * + * Then: + * + * div = MCK / prescaler / frequency + * + * Input parameters: + * mck - The main clock frequency + * fclk - The desired clock A or B frequency + * prelog2 - The log2(prescaler) value previously selected by + * pwm_prescale_log2(). + * + * Returned Value: + * The select value of log2(prescaler) in the range 0-10 corresponding to + * the actual prescaler value in the range 1-1024. + * + ****************************************************************************/ + +static unsigned int pwm_clk_divider(uint32_t mck, uint32_t fclk, + unsigned int prelog2) +{ + uint32_t div = (mck >> prelog2) / fclk; + + if (div < 1) + { + div = 1; + } + else if (div > 255) + { + div = 255; + } + + return div; +} + +/**************************************************************************** + * Name: pwm_clk_frequency + * + * Description: + * Given that we have already selected the prescaler value and cacluated + * the corresponding divider, the result clock frequency is give by: + * + * frequency = MCK / prescaler / div + * + * Input parameters: + * mck - The main clock frequency + * prelog2 - The log2(prescaler) value previously selected by + * pwm_prescale_log2(). + * div - The divider previously calculated from pwm_clk_divider(). + * + * Returned Value: + * The select value of log2(prescaler) in the range 0-10 corresponding to + * the actual prescaler value in the range 1-1024. + * + ****************************************************************************/ + +static uint32_t pwm_clk_frequency(uint32_t mck, unsigned int prelog2, + unsigned int div) +{ + return (mck >> prelog2) / div; +} + +/**************************************************************************** + * Name: pwm_resetpins * * Description: * Lower-half logic may support platform-specific ioctl commands * * Input parameters: - * dev - A reference to the lower half PWM driver state structure - * cmd - The ioctl command - * arg - The argument accompanying the ioctl command + * chan - A reference to the PWM channel instance * * Returned Value: - * Zero on success; a negated errno value on failure + * None * ****************************************************************************/ @@ -1327,13 +1351,37 @@ FAR struct pwm_lowerhalf_s *sam_pwminitialize(int channel) if (!g_pwm.initialized) { +#if defined(CONFIG_SAMA5_PWM_CLKA) || defined(CONFIG_SAMA5_PWM_CLKB) + uint32_t mck; + unsigned int prelog2; + unsigned int div; +#endif + /* Enable the PWM peripheral clock */ sam_pwm_enableclk(); - /* Set clock A and clock B */ +#if defined(CONFIG_SAMA5_PWM_CLKA) || defined(CONFIG_SAMA5_PWM_CLKB) + mck = BOARD_MCK_FREQUENCY; +#endif +#ifdef CONFIG_SAMA5_PWM_CLKA + /* Set clock A configuration */ + + prelog2 = pwm_clk_prescaler_log2(mck, CONFIG_SAMA5_PWM_CLKA_FREQUENCY); + div = pwm_clk_divider(mck, CONFIG_SAMA5_PWM_CLKA_FREQUENCY, prelog2); + regval = (PWM_CLK_DIVA(div) | PWM_CLK_PREA_DIV(prelog2)); +#else + regval = 0; +#endif + +#ifdef CONFIG_SAMA5_PWM_CLKB + /* Set clock B configuration */ + + prelog2 = pwm_clk_prescaler_log2(mck, CONFIG_SAMA5_PWM_CLKB_FREQUENCY); + div = pwm_clk_divider(mck, CONFIG_SAMA5_PWM_CLKA_FREQUENCY, prelog2); + regval |= (PWM_CLK_DIVB(div) | PWM_CLK_PREB_DIV(prelog2)); +#endif - regval = (CLKA_PRE_BITS | CLKA_DIV_BITS | CLKB_PRE_BITS | CLKB_DIV_BITS); pwm_putreg(chan, SAM_PWM_CLK_OFFSET, regval); /* Disable all PWM interrupts at the PWM peripheral */ -- GitLab From 39c4ecbcd074505c0fa48c5e24f50fb8aa765237 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 4 Dec 2016 15:39:53 -0600 Subject: [PATCH 598/734] SAMA5 PWM: Costmetic --- arch/arm/src/sama5/sam_pwm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/sama5/sam_pwm.c b/arch/arm/src/sama5/sam_pwm.c index 898a6e04e8..f5984f9337 100644 --- a/arch/arm/src/sama5/sam_pwm.c +++ b/arch/arm/src/sama5/sam_pwm.c @@ -1161,9 +1161,9 @@ static unsigned int pwm_clk_prescaler_log2(uint32_t mck, uint32_t fclk) unsigned int prelog2; unscaled = mck / fclk; - prelog2 = 0; + prelog2 = 0; - while (unscaled >= 256) + while (unscaled >= 256 && prelog2 < 11) { unscaled >>= 1; prelog2++; -- GitLab From 6cff0a7012095c709f2f770e0256075b2aa92291 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 4 Dec 2016 15:48:13 -0600 Subject: [PATCH 599/734] SAMA5 PWM: Minor improvement to a loop --- arch/arm/src/sama5/sam_pwm.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/arm/src/sama5/sam_pwm.c b/arch/arm/src/sama5/sam_pwm.c index f5984f9337..622d4569b0 100644 --- a/arch/arm/src/sama5/sam_pwm.c +++ b/arch/arm/src/sama5/sam_pwm.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/sama5/sam_pwm.c * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -1163,18 +1163,19 @@ static unsigned int pwm_clk_prescaler_log2(uint32_t mck, uint32_t fclk) unscaled = mck / fclk; prelog2 = 0; - while (unscaled >= 256 && prelog2 < 11) + /* Loop, incrementing the log2(prescaler) value. Exit with either: + * + * 1) unscaled < 256 and prelog2 <= 10, or with + * 2) unscaled >= 256 and prelog2 == 10 + */ + + while (unscaled >= 256 && prelog2 < 10) { unscaled >>= 1; prelog2++; } - DEBUGASSERT(prelog2 <= 10); - if (prelog2 > 10) - { - prelog2 = 10; - } - + DEBUGASSERT(unscaled < 256); return prelog2; } -- GitLab From 9ed038737914434eac0d97af9dde2d00c37e43a9 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 5 Dec 2016 08:52:40 -0600 Subject: [PATCH 600/734] Olimex-LPC1766-STK: Enable procfs in NSH configuration. Automount /proc on startup. --- arch/arm/src/lpc17xx/lpc17_ethernet.c | 4 ++-- configs/olimex-lpc1766stk/nsh/defconfig | 16 ++++++++++--- configs/olimex-lpc1766stk/src/lpc17_appinit.c | 23 ++++++++++++++++--- sched/irq/irq_csection.c | 4 ++++ 4 files changed, 39 insertions(+), 8 deletions(-) diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.c b/arch/arm/src/lpc17xx/lpc17_ethernet.c index 1ec3d332e2..fa9b65a95f 100644 --- a/arch/arm/src/lpc17xx/lpc17_ethernet.c +++ b/arch/arm/src/lpc17xx/lpc17_ethernet.c @@ -844,7 +844,7 @@ static void lpc17_rxdone_work(FAR void *arg) pktlen = (*rxstat & RXSTAT_INFO_RXSIZE_MASK) - 3; /* Check for errors. NOTE: The DMA engine reports bogus length errors, - * making this a pretty useless check. + * making this a pretty useless (as well as annoying) check. */ if ((*rxstat & RXSTAT_INFO_ERROR) != 0) @@ -1190,7 +1190,7 @@ static int lpc17_interrupt(int irq, void *context) * or Overrun. NOTE: (1) We will still need to call lpc17_rxdone_process * on RX errors to bump the considx over the bad packet. (2) The * DMA engine reports bogus length errors, making this a pretty - * useless check anyway. + * useless (as well as annoying) check anyway. */ if ((status & ETH_INT_RXERR) != 0) diff --git a/configs/olimex-lpc1766stk/nsh/defconfig b/configs/olimex-lpc1766stk/nsh/defconfig index f0989e352b..dcacc2d2f6 100644 --- a/configs/olimex-lpc1766stk/nsh/defconfig +++ b/configs/olimex-lpc1766stk/nsh/defconfig @@ -529,7 +529,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_NET_DM90x0 is not set # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set - # CONFIG_NET_SLIP is not set # CONFIG_NET_FTMAC100 is not set @@ -774,7 +773,16 @@ CONFIG_FAT_MAXFNAME=32 # CONFIG_FS_TMPFS is not set # CONFIG_FS_SMARTFS is not set # CONFIG_FS_BINFS is not set -# CONFIG_FS_PROCFS is not set +CONFIG_FS_PROCFS=y +# CONFIG_FS_PROCFS_REGISTER is not set + +# +# Exclude individual procfs entries +# +# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set +# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set +# CONFIG_FS_PROCFS_EXCLUDE_NET is not set # CONFIG_FS_UNIONFS is not set # @@ -848,6 +856,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set CONFIG_ARCH_HAVE_TLS=y # CONFIG_TLS is not set +# CONFIG_LIBC_IPv6_ADDRCONV is not set CONFIG_LIBC_NETDB=y # CONFIG_NETDB_HOSTFILE is not set CONFIG_NETDB_DNSCLIENT=y @@ -1041,7 +1050,7 @@ CONFIG_NSH_DISABLE_DATE=y # CONFIG_NSH_DISABLE_HELP is not set # CONFIG_NSH_DISABLE_HEXDUMP is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set -CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_IFUPDOWN is not set # CONFIG_NSH_DISABLE_KILL is not set # CONFIG_NSH_DISABLE_LOSETUP is not set CONFIG_NSH_DISABLE_LOSMART=y @@ -1083,6 +1092,7 @@ CONFIG_NSH_MMCSDSPIPORTNO=1 # CONFIG_NSH_CMDOPT_DF_H is not set CONFIG_NSH_CODECS_BUFSIZE=128 # CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_NSH_PROC_MOUNTPOINT="/proc" CONFIG_NSH_FILEIOSIZE=512 # diff --git a/configs/olimex-lpc1766stk/src/lpc17_appinit.c b/configs/olimex-lpc1766stk/src/lpc17_appinit.c index a8176afa25..fbbef27b6b 100644 --- a/configs/olimex-lpc1766stk/src/lpc17_appinit.c +++ b/configs/olimex-lpc1766stk/src/lpc17_appinit.c @@ -39,6 +39,7 @@ #include +#include #include #include #include @@ -348,12 +349,28 @@ int board_app_initialize(uintptr_t arg) /* Initialize SPI-based microSD */ ret = nsh_sdinitialize(); - if (ret == OK) + if (ret < 0) { - /* Initialize USB host */ + syslog(LOG_ERR, "ERROR: Failed to initialize SPI-based SD card: %d\n", ret); + } + + /* Initialize USB host */ - ret = nsh_usbhostinitialize(); + ret = nsh_usbhostinitialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); } +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + return ret; } diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 4f2178ab5f..935cbfd3af 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -346,6 +346,10 @@ try_again: * and try again. Briefly re-enabling interrupts should * be sufficient to permit processing the pending pause * request. + * + * NOTE: This should never happen on architectures like + * the Cortex-A; the inter-CPU interrupt (SGI) is not + * maskable. */ up_irq_restore(ret); -- GitLab From da69f6df556fec034a858e03d2c397a18b9fd4a3 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 5 Dec 2016 11:58:58 -0600 Subject: [PATCH 601/734] SAM4CMP-DB: Add hooks to auto-mount the procfs file system on startup in board bring-up logic. --- configs/sam4cmp-db/nsh/defconfig | 21 ++++--- configs/sam4cmp-db/src/Makefile | 6 ++ configs/sam4cmp-db/src/sam4cmp-db.h | 12 ++++ configs/sam4cmp-db/src/sam_appinit.c | 88 ++++++++++++++++++++++++++++ configs/sam4cmp-db/src/sam_boot.c | 11 +--- configs/sam4cmp-db/src/sam_bringup.c | 81 +++++++++++++++++++++++++ 6 files changed, 204 insertions(+), 15 deletions(-) create mode 100644 configs/sam4cmp-db/src/sam_appinit.c create mode 100644 configs/sam4cmp-db/src/sam_bringup.c diff --git a/configs/sam4cmp-db/nsh/defconfig b/configs/sam4cmp-db/nsh/defconfig index 8dc7937a07..8541fc330e 100644 --- a/configs/sam4cmp-db/nsh/defconfig +++ b/configs/sam4cmp-db/nsh/defconfig @@ -16,7 +16,7 @@ CONFIG_HOST_LINUX=y # # Build Configuration # -CONFIG_APPS_DIR="../apps" +# CONFIG_APPS_DIR="../apps" CONFIG_BUILD_FLAT=y # CONFIG_BUILD_2PASS is not set @@ -90,7 +90,6 @@ CONFIG_ARCH_ARM=y # CONFIG_ARCH_HC is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RGMP is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_SIM is not set @@ -112,7 +111,6 @@ CONFIG_ARCH="arm" # CONFIG_ARCH_CHIP_IMX6 is not set # CONFIG_ARCH_CHIP_KINETIS is not set # CONFIG_ARCH_CHIP_KL is not set -# CONFIG_ARCH_CHIP_LC823450 is not set # CONFIG_ARCH_CHIP_LM is not set # CONFIG_ARCH_CHIP_TIVA is not set # CONFIG_ARCH_CHIP_LPC11XX is not set @@ -343,7 +341,14 @@ CONFIG_ARCH_BOARD="sam4cmp-db" # Board-Specific Options # # CONFIG_BOARD_CRASHDUMP is not set -# CONFIG_LIB_BOARDCTL is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_RESET is not set +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_ADCTEST is not set +# CONFIG_BOARDCTL_PWMTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set # # RTOS Features @@ -703,6 +708,8 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set CONFIG_ARCH_HAVE_TLS=y # CONFIG_TLS is not set +# CONFIG_LIBC_IPv4_ADDRCONV is not set +# CONFIG_LIBC_IPv6_ADDRCONV is not set # CONFIG_LIBC_NETDB is not set # CONFIG_NETDB_HOSTFILE is not set @@ -755,10 +762,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_NRF24L01TERM is not set CONFIG_EXAMPLES_NSH=y # CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set @@ -774,7 +781,6 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y # CONFIG_EXAMPLES_PPPD is not set # CONFIG_EXAMPLES_RFID_READUID is not set # CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_RGMP is not set # CONFIG_EXAMPLES_SENDMAIL is not set # CONFIG_EXAMPLES_SERIALBLASTER is not set # CONFIG_EXAMPLES_SERIALRX is not set @@ -790,6 +796,7 @@ CONFIG_EXAMPLES_SMP_STACKSIZE=2048 # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_TIFF is not set # CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBSERIAL is not set # CONFIG_EXAMPLES_USBTERM is not set # CONFIG_EXAMPLES_WATCHDOG is not set # CONFIG_EXAMPLES_WEBSERVER is not set @@ -928,7 +935,7 @@ CONFIG_NSH_FILEIOSIZE=512 # CONFIG_NSH_CONSOLE=y # CONFIG_NSH_ALTCONDEV is not set -# CONFIG_NSH_ARCHINIT is not set +CONFIG_NSH_ARCHINIT=y # CONFIG_NSH_LOGIN is not set # CONFIG_NSH_CONSOLE_LOGIN is not set diff --git a/configs/sam4cmp-db/src/Makefile b/configs/sam4cmp-db/src/Makefile index 2463d7e867..1dd2e0485c 100644 --- a/configs/sam4cmp-db/src/Makefile +++ b/configs/sam4cmp-db/src/Makefile @@ -38,4 +38,10 @@ ASRCS = CSRCS = sam_boot.c +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += sam_appinit.c sam_bringup.c +else ifeq ($(CONFIG_BOARD_INITIALIZE),y) +CSRCS += sam_bringup.c +endif + include $(TOPDIR)/configs/Board.mk diff --git a/configs/sam4cmp-db/src/sam4cmp-db.h b/configs/sam4cmp-db/src/sam4cmp-db.h index e665614571..9fab435d5a 100644 --- a/configs/sam4cmp-db/src/sam4cmp-db.h +++ b/configs/sam4cmp-db/src/sam4cmp-db.h @@ -64,5 +64,17 @@ * Public Functions ************************************************************************************/ +/************************************************************************************ + * Name: sam_bringup + * + * Description: + * Bring up board features + * + ************************************************************************************/ + +#if defined(CONFIG_LIB_BOARDCTL) || defined(CONFIG_BOARD_INITIALIZE) +int sam_bringup(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_SAM4CMP_DB_SRC_SAM4CMP_DB_H */ diff --git a/configs/sam4cmp-db/src/sam_appinit.c b/configs/sam4cmp-db/src/sam_appinit.c new file mode 100644 index 0000000000..6bab1d5751 --- /dev/null +++ b/configs/sam4cmp-db/src/sam_appinit.c @@ -0,0 +1,88 @@ +/**************************************************************************** + * config/sam4cmp-db/src/sam_appinit.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "sam4cmp-db.h" + +#ifdef CONFIG_LIB_BOARDCTL + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifndef CONFIG_BOARD_INITIALIZE + /* Perform board initialization */ + + return sam_bringup(); +#else + return OK; +#endif +} + +#endif /* CONFIG_LIB_BOARDCTL */ diff --git a/configs/sam4cmp-db/src/sam_boot.c b/configs/sam4cmp-db/src/sam_boot.c index ee34da638d..f883f0add6 100644 --- a/configs/sam4cmp-db/src/sam_boot.c +++ b/configs/sam4cmp-db/src/sam_boot.c @@ -45,14 +45,6 @@ #include "sam4cmp-db.h" -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ @@ -87,5 +79,8 @@ void sam_boardinitialize(void) #ifdef CONFIG_BOARD_INITIALIZE void board_initialize(void) { + /* Perform board initialization */ + + (void)sam_bringup(); } #endif /* CONFIG_BOARD_INITIALIZE */ diff --git a/configs/sam4cmp-db/src/sam_bringup.c b/configs/sam4cmp-db/src/sam_bringup.c new file mode 100644 index 0000000000..fbfe1a4106 --- /dev/null +++ b/configs/sam4cmp-db/src/sam_bringup.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * config/sam4cmp-db/src/sam_bringup.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +int sam_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + + /* If we got here then perhaps not all initialization was successful, but + * at least enough succeeded to bring-up NSH with perhaps reduced + * capabilities. + */ + + UNUSED(ret); + return OK; +} -- GitLab From b999e63c82e0d914cac3ab9b28cc70820ad316f3 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 5 Dec 2016 13:54:12 -0600 Subject: [PATCH 602/734] Remove some references to BOARDIOC_PWMTEST and board_pwm_setup(). Still lots more. --- configs/Kconfig | 8 ------- configs/bambino-200e/nsh/defconfig | 1 - configs/boardctl.c | 15 ------------- configs/cloudctrl/nsh/defconfig | 1 - configs/compal_e86/nsh_highram/defconfig | 1 - configs/compal_e88/nsh_highram/defconfig | 1 - configs/compal_e99/nsh_compalram/defconfig | 1 - configs/compal_e99/nsh_highram/defconfig | 1 - configs/dk-tm4c129x/ipv6/defconfig | 1 - configs/dk-tm4c129x/nsh/defconfig | 1 - configs/ea3131/nsh/defconfig | 1 - configs/ea3131/pgnsh/defconfig | 1 - configs/ea3131/usbserial/defconfig | 1 - configs/eagle100/nsh/defconfig | 1 - configs/ekk-lm3s9b96/nsh/defconfig | 1 - configs/fire-stm32v2/nsh/defconfig | 1 - configs/freedom-k64f/netnsh/defconfig | 1 - configs/freedom-k64f/nsh/defconfig | 1 - configs/freedom-k64f/src/freedom-k64f.h | 12 ++++++++++ configs/freedom-k64f/src/k64_bringup.c | 16 +++++++++++--- configs/freedom-k64f/src/k64_pwm.c | 7 +++--- configs/freedom-kl25z/nsh/defconfig | 1 - configs/freedom-kl25z/src/freedom-kl25z.h | 14 ++++++++++-- configs/freedom-kl25z/src/kl_appinit.c | 22 ++++++++++++++----- configs/freedom-kl25z/src/kl_pwm.c | 7 +++--- configs/freedom-kl26z/nsh/defconfig | 1 - configs/freedom-kl26z/src/freedom-kl26z.h | 12 ++++++++++ configs/freedom-kl26z/src/kl_appinit.c | 20 +++++++++++++---- .../freedom-kl26z/src/kl_boardinitialize.c | 8 ------- configs/freedom-kl26z/src/kl_pwm.c | 11 +++------- configs/hymini-stm32v/nsh/defconfig | 1 - configs/hymini-stm32v/nsh2/defconfig | 1 - configs/hymini-stm32v/usbmsc/defconfig | 1 - configs/hymini-stm32v/usbnsh/defconfig | 1 - configs/hymini-stm32v/usbserial/defconfig | 1 - configs/launchxl-tms57004/nsh/defconfig | 1 - configs/lincoln60/netnsh/defconfig | 1 - configs/lincoln60/nsh/defconfig | 1 - configs/lm3s6432-s2e/nsh/defconfig | 1 - configs/lm3s6965-ek/discover/defconfig | 1 - configs/lm3s6965-ek/nsh/defconfig | 1 - configs/lm3s6965-ek/nx/defconfig | 1 - configs/lm3s8962-ek/nsh/defconfig | 1 - configs/lm3s8962-ek/nx/defconfig | 1 - configs/lpc4330-xplorer/nsh/defconfig | 1 - configs/lpc4337-ws/nsh/defconfig | 1 - configs/lpc4357-evb/nsh/defconfig | 1 - configs/lpc4370-link2/nsh/defconfig | 1 - configs/lpcxpresso-lpc1768/nsh/defconfig | 1 - configs/lpcxpresso-lpc1768/nx/defconfig | 1 - configs/lpcxpresso-lpc1768/usbmsc/defconfig | 1 - configs/maple/nx/defconfig | 1 - configs/maple/usbnsh/defconfig | 1 - configs/mbed/nsh/defconfig | 1 - configs/mcu123-lpc214x/composite/defconfig | 1 - configs/mcu123-lpc214x/nsh/defconfig | 1 - configs/mcu123-lpc214x/usbmsc/defconfig | 1 - configs/mcu123-lpc214x/usbserial/defconfig | 1 - configs/mikroe-stm32f4/fulldemo/defconfig | 1 - configs/mikroe-stm32f4/kostest/defconfig | 1 - configs/mikroe-stm32f4/nsh/defconfig | 1 - configs/mikroe-stm32f4/nx/defconfig | 1 - configs/mikroe-stm32f4/nxlines/defconfig | 1 - configs/mikroe-stm32f4/nxtext/defconfig | 1 - configs/mikroe-stm32f4/usbnsh/defconfig | 1 - configs/mirtoo/nxffs/defconfig | 1 - configs/moxa/nsh/defconfig | 1 - configs/nr5m100-nexys4/nsh/defconfig | 1 - configs/nucleo-144/f746-evalos/defconfig | 1 - configs/nucleo-144/f767-evalos/defconfig | 1 - configs/nucleo-f303re/adc/defconfig | 1 - configs/nucleo-f303re/can/defconfig | 1 - configs/nucleo-f303re/nxlines/defconfig | 1 - configs/nucleo-f303re/pwm/defconfig | 1 - configs/nucleo-f303re/serialrx/defconfig | 1 - configs/nucleo-f303re/src/nucleo-f303re.h | 12 ++++++++++ .../nucleo-f303re/src/stm32_appinitialize.c | 10 +++++++++ configs/nucleo-f303re/src/stm32_pwm.c | 11 +++++----- configs/nucleo-l476rg/nsh/defconfig | 1 - configs/olimex-lpc-h3131/nsh/defconfig | 1 - configs/olimex-lpc1766stk/ftpc/defconfig | 1 - configs/olimex-lpc1766stk/hidmouse/defconfig | 1 - configs/olimex-lpc1766stk/nsh/defconfig | 1 - configs/olimex-lpc1766stk/nx/defconfig | 1 - configs/olimex-lpc1766stk/usbmsc/defconfig | 1 - configs/olimex-lpc1766stk/usbserial/defconfig | 1 - configs/olimex-lpc1766stk/zmodem/defconfig | 1 - configs/olimex-stm32-e407/usbnsh/defconfig | 1 - configs/olimex-stm32-h405/usbnsh/defconfig | 1 - configs/olimex-stm32-p207/nsh/defconfig | 1 - configs/olimex-strp711/nsh/defconfig | 1 - configs/olimexino-stm32/can/defconfig | 1 - configs/olimexino-stm32/composite/defconfig | 1 - configs/olimexino-stm32/nsh/defconfig | 1 - configs/olimexino-stm32/smallnsh/defconfig | 1 - configs/olimexino-stm32/tiny/defconfig | 1 - configs/open1788/nsh/defconfig | 1 - configs/pic32mx-starterkit/nsh/defconfig | 1 - configs/pic32mx-starterkit/nsh2/defconfig | 1 - configs/pic32mx7mmb/nsh/defconfig | 1 - configs/pic32mz-starterkit/nsh/defconfig | 1 - configs/pirelli_dpl10/nsh_highram/defconfig | 1 - configs/sabre-6quad/nsh/defconfig | 1 - configs/sabre-6quad/smp/defconfig | 1 - configs/sam3u-ek/nsh/defconfig | 1 - configs/sam3u-ek/nxwm/defconfig | 1 - configs/sam4cmp-db/nsh/defconfig | 1 - configs/sam4e-ek/nsh/defconfig | 1 - configs/sam4e-ek/nxwm/defconfig | 1 - configs/sam4e-ek/usbnsh/defconfig | 1 - configs/sam4s-xplained-pro/nsh/defconfig | 1 - configs/sama5d2-xult/nsh/defconfig | 1 - configs/sama5d3x-ek/demo/defconfig | 1 - configs/sama5d3x-ek/nxplayer/defconfig | 1 - configs/sama5d3x-ek/nxwm/defconfig | 1 - configs/sama5d4-ek/ipv6/defconfig | 1 - configs/sama5d4-ek/nsh/defconfig | 1 - configs/sama5d4-ek/nxwm/defconfig | 1 - configs/same70-xplained/netnsh/defconfig | 1 - configs/same70-xplained/nsh/defconfig | 1 - configs/samv71-xult/knsh/defconfig | 1 - configs/samv71-xult/module/defconfig | 1 - configs/samv71-xult/mxtxplnd/defconfig | 1 - configs/samv71-xult/netnsh/defconfig | 1 - configs/samv71-xult/nsh/defconfig | 1 - configs/samv71-xult/nxwm/defconfig | 1 - configs/samv71-xult/vnc/defconfig | 1 - configs/samv71-xult/vnxwm/defconfig | 1 - configs/shenzhou/nsh/defconfig | 1 - configs/shenzhou/nxwm/defconfig | 1 - configs/shenzhou/thttpd/defconfig | 1 - configs/sim/bas/defconfig | 1 - configs/sim/minibasic/defconfig | 1 - configs/sim/nsh/defconfig | 1 - configs/sim/nsh2/defconfig | 1 - configs/sim/nxlines/defconfig | 1 - configs/sim/nxwm/defconfig | 1 - configs/sim/touchscreen/defconfig | 1 - configs/sim/udgram/defconfig | 1 - configs/sim/unionfs/defconfig | 1 - configs/sim/ustream/defconfig | 1 - configs/spark/composite/defconfig | 1 - configs/spark/nsh/defconfig | 1 - configs/spark/usbmsc/defconfig | 1 - configs/spark/usbnsh/defconfig | 1 - configs/spark/usbserial/defconfig | 1 - configs/stm3210e-eval/composite/defconfig | 1 - configs/stm3210e-eval/nsh/defconfig | 1 - configs/stm3210e-eval/nsh2/defconfig | 1 - configs/stm3210e-eval/nxterm/defconfig | 1 - configs/stm3210e-eval/pm/defconfig | 1 - configs/stm3210e-eval/usbmsc/defconfig | 1 - configs/stm3210e-eval/usbserial/defconfig | 1 - configs/stm3220g-eval/nsh2/defconfig | 1 - configs/stm3220g-eval/nxwm/defconfig | 1 - configs/stm3240g-eval/knxwm/defconfig | 1 - configs/stm3240g-eval/nsh2/defconfig | 1 - configs/stm3240g-eval/nxterm/defconfig | 1 - configs/stm3240g-eval/nxwm/defconfig | 1 - configs/stm32_tiny/nsh/defconfig | 1 - configs/stm32_tiny/usbnsh/defconfig | 1 - configs/stm32butterfly2/nsh/defconfig | 1 - configs/stm32butterfly2/nshnet/defconfig | 1 - configs/stm32butterfly2/nshusbdev/defconfig | 1 - configs/stm32butterfly2/nshusbhost/defconfig | 1 - .../stm32f103-minimum/audio_tone/defconfig | 1 - configs/stm32f103-minimum/buttons/defconfig | 1 - configs/stm32f103-minimum/jlx12864g/defconfig | 1 - configs/stm32f103-minimum/nsh/defconfig | 1 - configs/stm32f103-minimum/pwm/defconfig | 1 - .../stm32f103-minimum/rfid-rc522/defconfig | 1 - configs/stm32f103-minimum/rgbled/defconfig | 1 - configs/stm32f103-minimum/src/stm32_bringup.c | 10 +++++++++ configs/stm32f103-minimum/src/stm32_pwm.c | 11 +++------- .../stm32f103-minimum/src/stm32f103_minimum.h | 12 ++++++++++ configs/stm32f103-minimum/usbnsh/defconfig | 1 - configs/stm32f103-minimum/userled/defconfig | 1 - configs/stm32f103-minimum/veml6070/defconfig | 1 - configs/stm32f3discovery/nsh/defconfig | 1 - configs/stm32f3discovery/usbnsh/defconfig | 1 - configs/stm32f429i-disco/extflash/defconfig | 1 - configs/stm32f429i-disco/lcd/defconfig | 1 - configs/stm32f429i-disco/usbmsc/defconfig | 1 - configs/stm32f429i-disco/usbnsh/defconfig | 1 - configs/stm32f4discovery/canard/defconfig | 1 - configs/stm32f4discovery/ipv6/defconfig | 1 - configs/stm32f4discovery/netnsh/defconfig | 1 - configs/stm32f4discovery/usbnsh/defconfig | 1 - configs/stm32f746-ws/nsh/defconfig | 1 - configs/stm32l476-mdk/nsh/defconfig | 1 - configs/stm32l476vg-disco/nsh/defconfig | 1 - configs/sure-pic32mx/nsh/defconfig | 1 - configs/sure-pic32mx/usbnsh/defconfig | 1 - configs/teensy-3.x/usbnsh/defconfig | 1 - configs/teensy-lc/nsh/defconfig | 1 - configs/tm4c123g-launchpad/nsh/defconfig | 1 - configs/tm4c1294-launchpad/ipv6/defconfig | 1 - configs/tm4c1294-launchpad/nsh/defconfig | 1 - configs/tm4c1294-launchpad/src/tm4c_appinit.c | 22 ------------------- configs/u-blox-c027/nsh/defconfig | 1 - configs/ubw32/nsh/defconfig | 1 - configs/zkit-arm-1769/nsh/defconfig | 1 - configs/zkit-arm-1769/nxhello/defconfig | 1 - configs/zp214xpa/nxlines/defconfig | 1 - include/nuttx/board.h | 17 -------------- include/sys/boardctl.h | 11 ++-------- 206 files changed, 144 insertions(+), 309 deletions(-) diff --git a/configs/Kconfig b/configs/Kconfig index 6ef90c00ef..ba68a4e541 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -2037,14 +2037,6 @@ config BOARDCTL_ADCTEST Architecture specific logic must provide board_adc_setup() interface. -config BOARDCTL_PWMTEST - bool "Enable PWM test interfaces" - default n - ---help--- - Enables support for the BOARDIOC_PWMTEST_SETUP boardctl() command. - Architecture specific logic must provide board_pwm_setup() - interface. - config BOARDCTL_CANINIT bool "Enable CAN initialize interface" default n diff --git a/configs/bambino-200e/nsh/defconfig b/configs/bambino-200e/nsh/defconfig index 5926930456..6ca4351125 100644 --- a/configs/bambino-200e/nsh/defconfig +++ b/configs/bambino-200e/nsh/defconfig @@ -330,7 +330,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/boardctl.c b/configs/boardctl.c index 6c5cb5224d..4807769731 100644 --- a/configs/boardctl.c +++ b/configs/boardctl.c @@ -441,21 +441,6 @@ int boardctl(unsigned int cmd, uintptr_t arg) break; #endif -#ifdef CONFIG_BOARDCTL_PWMTEST - /* CMD: BOARDIOC_PWMTEST_SETUP - * DESCRIPTION: PWM controller test configuration - * ARG: None - * CONFIGURATION: CONFIG_LIB_BOARDCTL && CONFIG_BOARDCTL_PWMTEST - * DEPENDENCIES: Board logic must provide board_pwm_setup() - */ - - case BOARDIOC_PWMTEST_SETUP: - { - ret = board_pwm_setup(); - } - break; -#endif - #ifdef CONFIG_BOARDCTL_CANINIT /* CMD: BOARDIOC_CAN_INITIALIZE * DESCRIPTION: CAN device initialization diff --git a/configs/cloudctrl/nsh/defconfig b/configs/cloudctrl/nsh/defconfig index 41f4db58a8..053a106531 100644 --- a/configs/cloudctrl/nsh/defconfig +++ b/configs/cloudctrl/nsh/defconfig @@ -594,7 +594,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/compal_e86/nsh_highram/defconfig b/configs/compal_e86/nsh_highram/defconfig index 6d94dcf374..0b88e0cb10 100644 --- a/configs/compal_e86/nsh_highram/defconfig +++ b/configs/compal_e86/nsh_highram/defconfig @@ -241,7 +241,6 @@ CONFIG_BOARDCTL_POWEROFF=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/compal_e88/nsh_highram/defconfig b/configs/compal_e88/nsh_highram/defconfig index dabec9c67a..a05d578955 100644 --- a/configs/compal_e88/nsh_highram/defconfig +++ b/configs/compal_e88/nsh_highram/defconfig @@ -241,7 +241,6 @@ CONFIG_BOARDCTL_POWEROFF=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/compal_e99/nsh_compalram/defconfig b/configs/compal_e99/nsh_compalram/defconfig index 43706916ca..746b5c0f42 100644 --- a/configs/compal_e99/nsh_compalram/defconfig +++ b/configs/compal_e99/nsh_compalram/defconfig @@ -243,7 +243,6 @@ CONFIG_BOARDCTL_POWEROFF=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/compal_e99/nsh_highram/defconfig b/configs/compal_e99/nsh_highram/defconfig index b4fb3decf3..86d90fbd39 100644 --- a/configs/compal_e99/nsh_highram/defconfig +++ b/configs/compal_e99/nsh_highram/defconfig @@ -245,7 +245,6 @@ CONFIG_BOARDCTL_POWEROFF=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/dk-tm4c129x/ipv6/defconfig b/configs/dk-tm4c129x/ipv6/defconfig index 7e6a993b1d..84a22592c7 100644 --- a/configs/dk-tm4c129x/ipv6/defconfig +++ b/configs/dk-tm4c129x/ipv6/defconfig @@ -368,7 +368,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/dk-tm4c129x/nsh/defconfig b/configs/dk-tm4c129x/nsh/defconfig index 741b7af168..674bd5f241 100644 --- a/configs/dk-tm4c129x/nsh/defconfig +++ b/configs/dk-tm4c129x/nsh/defconfig @@ -368,7 +368,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/ea3131/nsh/defconfig b/configs/ea3131/nsh/defconfig index a1eb0e7d0b..6008b42558 100644 --- a/configs/ea3131/nsh/defconfig +++ b/configs/ea3131/nsh/defconfig @@ -258,7 +258,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/ea3131/pgnsh/defconfig b/configs/ea3131/pgnsh/defconfig index 6b38e9a914..21bd28018e 100644 --- a/configs/ea3131/pgnsh/defconfig +++ b/configs/ea3131/pgnsh/defconfig @@ -280,7 +280,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/ea3131/usbserial/defconfig b/configs/ea3131/usbserial/defconfig index 81886fe97a..ec611ad315 100644 --- a/configs/ea3131/usbserial/defconfig +++ b/configs/ea3131/usbserial/defconfig @@ -266,7 +266,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/eagle100/nsh/defconfig b/configs/eagle100/nsh/defconfig index f32a3000a7..5e84f8454d 100644 --- a/configs/eagle100/nsh/defconfig +++ b/configs/eagle100/nsh/defconfig @@ -347,7 +347,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/ekk-lm3s9b96/nsh/defconfig b/configs/ekk-lm3s9b96/nsh/defconfig index c733dade36..d86a37e544 100644 --- a/configs/ekk-lm3s9b96/nsh/defconfig +++ b/configs/ekk-lm3s9b96/nsh/defconfig @@ -336,7 +336,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/fire-stm32v2/nsh/defconfig b/configs/fire-stm32v2/nsh/defconfig index f2c01e8a69..24645154e4 100644 --- a/configs/fire-stm32v2/nsh/defconfig +++ b/configs/fire-stm32v2/nsh/defconfig @@ -603,7 +603,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/freedom-k64f/netnsh/defconfig b/configs/freedom-k64f/netnsh/defconfig index d04232162c..395bdd882f 100644 --- a/configs/freedom-k64f/netnsh/defconfig +++ b/configs/freedom-k64f/netnsh/defconfig @@ -346,7 +346,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/freedom-k64f/nsh/defconfig b/configs/freedom-k64f/nsh/defconfig index f88ffdc70b..b2d1ba0fef 100644 --- a/configs/freedom-k64f/nsh/defconfig +++ b/configs/freedom-k64f/nsh/defconfig @@ -336,7 +336,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -CONFIG_BOARDCTL_PWMTEST=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/freedom-k64f/src/freedom-k64f.h b/configs/freedom-k64f/src/freedom-k64f.h index 0e0af54f96..d63492a071 100644 --- a/configs/freedom-k64f/src/freedom-k64f.h +++ b/configs/freedom-k64f/src/freedom-k64f.h @@ -340,5 +340,17 @@ void k64_automount_initialize(void); void k64_automount_event(bool inserted); #endif +/************************************************************************************ + * Name: k64_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int k64_pwm_setup(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_FREEDOM_K64F_SRC_FREEDOM_K64F_H */ diff --git a/configs/freedom-k64f/src/k64_bringup.c b/configs/freedom-k64f/src/k64_bringup.c index b307c7038e..40590f8962 100644 --- a/configs/freedom-k64f/src/k64_bringup.c +++ b/configs/freedom-k64f/src/k64_bringup.c @@ -86,7 +86,7 @@ int k64_bringup(void) ret = k64_sdhc_initialize(); if (ret < 0) { - mcerr("ERROR: k64_sdhc_initialize() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: k64_sdhc_initialize() failed: %d\n", ret); } #ifdef CONFIG_FRDMK64F_SDHC_MOUNT @@ -102,14 +102,24 @@ int k64_bringup(void) if (ret < 0) { - mcerr("ERROR: Failed to mount %s: %d\n", - CONFIG_FRDMK64F_SDHC_MOUNT_MOUNTPOINT, errno); + syslog(LOG_ERR,"ERROR: Failed to mount %s: %d\n", + CONFIG_FRDMK64F_SDHC_MOUNT_MOUNTPOINT, errno); } } #endif /* CONFIG_FRDMK64F_SDHC_MOUNT */ #endif /* HAVE_MMCSD */ +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = k64_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: k64_pwm_setup() failed: %d\n", ret); + } +#endif + #ifdef HAVE_AUTOMOUNTER /* Initialize the auto-mounter */ diff --git a/configs/freedom-k64f/src/k64_pwm.c b/configs/freedom-k64f/src/k64_pwm.c index 2434974122..547c19fb17 100644 --- a/configs/freedom-k64f/src/k64_pwm.c +++ b/configs/freedom-k64f/src/k64_pwm.c @@ -60,15 +60,14 @@ ************************************************************************************/ /************************************************************************************ - * Name: board_pwm_setup + * Name: k64_pwm_setup * * Description: - * All Kinetis K architectures must provide the following interface to work with - * examples/pwm. + * Initialize PWM and register the PWM device. * ************************************************************************************/ -int board_pwm_setup(void) +int k64_pwm_setup(void) { FAR struct pwm_lowerhalf_s *pwm; static bool initialized = false; diff --git a/configs/freedom-kl25z/nsh/defconfig b/configs/freedom-kl25z/nsh/defconfig index 8f8060ba2d..d87eabd5f8 100644 --- a/configs/freedom-kl25z/nsh/defconfig +++ b/configs/freedom-kl25z/nsh/defconfig @@ -268,7 +268,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -CONFIG_BOARDCTL_PWMTEST=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/freedom-kl25z/src/freedom-kl25z.h b/configs/freedom-kl25z/src/freedom-kl25z.h index ca5ce242d8..8c7c9f0092 100644 --- a/configs/freedom-kl25z/src/freedom-kl25z.h +++ b/configs/freedom-kl25z/src/freedom-kl25z.h @@ -1,8 +1,7 @@ /**************************************************************************************************** * configs/freedom-kl25z/src/freedom-kl25z.h - * arch/arm/src/board/freedom-kl25z.c * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -137,6 +136,17 @@ void weak_function kl_usbinitialize(void); void kl_led_initialize(void); #endif +/************************************************************************************ + * Name: kl_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int kl_pwm_setup(void); +#endif #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_FREEDOM_KL25Z_SRC_FREEDOM_KL25Z_H */ diff --git a/configs/freedom-kl25z/src/kl_appinit.c b/configs/freedom-kl25z/src/kl_appinit.c index 1f0d218ece..ef425471dd 100644 --- a/configs/freedom-kl25z/src/kl_appinit.c +++ b/configs/freedom-kl25z/src/kl_appinit.c @@ -45,11 +45,9 @@ #include -#ifdef CONFIG_LIB_BOARDCTL +#include "freedom-kl25z.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ +#ifdef CONFIG_LIB_BOARDCTL /**************************************************************************** * Public Functions @@ -80,15 +78,27 @@ int board_app_initialize(uintptr_t arg) { -#if defined(CONFIG_SENSORS_ADXL345) int ret; + #if defined(CONFIG_SENSORS_ADXL345) ret = adxl345_archinitialize(0); if (ret < 0) { - _err("ERROR: adxl345_archinitialize failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: adxl345_archinitialize failed: %d\n", ret); } #endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = kl_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: k64_pwm_setup() failed: %d\n", ret); + } +#endif + + UNUSED(ret); return OK; } diff --git a/configs/freedom-kl25z/src/kl_pwm.c b/configs/freedom-kl25z/src/kl_pwm.c index 1db53f5a26..6f43a06daa 100644 --- a/configs/freedom-kl25z/src/kl_pwm.c +++ b/configs/freedom-kl25z/src/kl_pwm.c @@ -75,15 +75,14 @@ extern struct pwm_lowerhalf_s *kl_pwminitialize(int timer); ************************************************************************************/ /************************************************************************************ - * Name: board_pwm_setup + * Name: kl_pwm_setup * * Description: - * All Kinetis KL architectures must provide the following interface to work with - * examples/pwm. + * Initialize PWM and register the PWM device. * ************************************************************************************/ -int board_pwm_setup(void) +int kl_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; diff --git a/configs/freedom-kl26z/nsh/defconfig b/configs/freedom-kl26z/nsh/defconfig index 2738c86079..16db1d5744 100644 --- a/configs/freedom-kl26z/nsh/defconfig +++ b/configs/freedom-kl26z/nsh/defconfig @@ -268,7 +268,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -CONFIG_BOARDCTL_PWMTEST=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/freedom-kl26z/src/freedom-kl26z.h b/configs/freedom-kl26z/src/freedom-kl26z.h index 053101db5b..e120714979 100644 --- a/configs/freedom-kl26z/src/freedom-kl26z.h +++ b/configs/freedom-kl26z/src/freedom-kl26z.h @@ -136,5 +136,17 @@ void weak_function kl_usbinitialize(void); void kl_led_initialize(void); #endif +/************************************************************************************ + * Name: kl_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int kl_pwm_setup(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_FREEDOM_KL26Z_SRC_FREEDOM_KL26Z_H */ diff --git a/configs/freedom-kl26z/src/kl_appinit.c b/configs/freedom-kl26z/src/kl_appinit.c index 96ac70a061..6b6550c915 100644 --- a/configs/freedom-kl26z/src/kl_appinit.c +++ b/configs/freedom-kl26z/src/kl_appinit.c @@ -40,14 +40,13 @@ #include #include +#include #include -#ifdef CONFIG_LIB_BOARDCTL +#include "freedom-kl26z.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ +#ifdef CONFIG_LIB_BOARDCTL /**************************************************************************** * Public Functions @@ -78,6 +77,19 @@ int board_app_initialize(uintptr_t arg) { + int ret; + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = kl_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: kl_pwm_setup() failed: %d\n", ret); + } +#endif + + UNUSED(ret); return OK; } diff --git a/configs/freedom-kl26z/src/kl_boardinitialize.c b/configs/freedom-kl26z/src/kl_boardinitialize.c index 3a3be5190a..f976a86727 100644 --- a/configs/freedom-kl26z/src/kl_boardinitialize.c +++ b/configs/freedom-kl26z/src/kl_boardinitialize.c @@ -47,14 +47,6 @@ #include "up_arch.h" #include "freedom-kl26z.h" -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ diff --git a/configs/freedom-kl26z/src/kl_pwm.c b/configs/freedom-kl26z/src/kl_pwm.c index cb5b6af3f8..d256e2281e 100644 --- a/configs/freedom-kl26z/src/kl_pwm.c +++ b/configs/freedom-kl26z/src/kl_pwm.c @@ -66,24 +66,19 @@ extern struct pwm_lowerhalf_s *kl_pwminitialize(int timer); -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_pwm_setup + * Name: kl_pwm_setup * * Description: - * All Kinetis KL architectures must provide the following interface to work with - * examples/pwm. + * Initialize PWM and register the PWM device. * ************************************************************************************/ -int board_pwm_setup(void) +int kl_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; diff --git a/configs/hymini-stm32v/nsh/defconfig b/configs/hymini-stm32v/nsh/defconfig index 8d9205db65..385782572c 100644 --- a/configs/hymini-stm32v/nsh/defconfig +++ b/configs/hymini-stm32v/nsh/defconfig @@ -554,7 +554,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/hymini-stm32v/nsh2/defconfig b/configs/hymini-stm32v/nsh2/defconfig index 41cb4a97ff..eaf473107d 100644 --- a/configs/hymini-stm32v/nsh2/defconfig +++ b/configs/hymini-stm32v/nsh2/defconfig @@ -581,7 +581,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARDCTL_TSCTEST=y # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/hymini-stm32v/usbmsc/defconfig b/configs/hymini-stm32v/usbmsc/defconfig index 49808a71fa..dc189f23c5 100644 --- a/configs/hymini-stm32v/usbmsc/defconfig +++ b/configs/hymini-stm32v/usbmsc/defconfig @@ -559,7 +559,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/hymini-stm32v/usbnsh/defconfig b/configs/hymini-stm32v/usbnsh/defconfig index c5cd07b4e4..1dab64fb6d 100644 --- a/configs/hymini-stm32v/usbnsh/defconfig +++ b/configs/hymini-stm32v/usbnsh/defconfig @@ -556,7 +556,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/hymini-stm32v/usbserial/defconfig b/configs/hymini-stm32v/usbserial/defconfig index 57d23bcb8c..0d62c0ed93 100644 --- a/configs/hymini-stm32v/usbserial/defconfig +++ b/configs/hymini-stm32v/usbserial/defconfig @@ -550,7 +550,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/launchxl-tms57004/nsh/defconfig b/configs/launchxl-tms57004/nsh/defconfig index 7bfdd01bd9..7329956077 100644 --- a/configs/launchxl-tms57004/nsh/defconfig +++ b/configs/launchxl-tms57004/nsh/defconfig @@ -254,7 +254,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lincoln60/netnsh/defconfig b/configs/lincoln60/netnsh/defconfig index 1f6f544322..0a43f6d84d 100644 --- a/configs/lincoln60/netnsh/defconfig +++ b/configs/lincoln60/netnsh/defconfig @@ -325,7 +325,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lincoln60/nsh/defconfig b/configs/lincoln60/nsh/defconfig index 0568982c09..4a1ab48f51 100644 --- a/configs/lincoln60/nsh/defconfig +++ b/configs/lincoln60/nsh/defconfig @@ -302,7 +302,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lm3s6432-s2e/nsh/defconfig b/configs/lm3s6432-s2e/nsh/defconfig index ee2493f4f3..becaa42d18 100644 --- a/configs/lm3s6432-s2e/nsh/defconfig +++ b/configs/lm3s6432-s2e/nsh/defconfig @@ -331,7 +331,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lm3s6965-ek/discover/defconfig b/configs/lm3s6965-ek/discover/defconfig index ed9c7291f9..f087bbee8e 100644 --- a/configs/lm3s6965-ek/discover/defconfig +++ b/configs/lm3s6965-ek/discover/defconfig @@ -341,7 +341,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lm3s6965-ek/nsh/defconfig b/configs/lm3s6965-ek/nsh/defconfig index ed9c7291f9..f087bbee8e 100644 --- a/configs/lm3s6965-ek/nsh/defconfig +++ b/configs/lm3s6965-ek/nsh/defconfig @@ -341,7 +341,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lm3s6965-ek/nx/defconfig b/configs/lm3s6965-ek/nx/defconfig index 031025dc51..ee5110cf2d 100644 --- a/configs/lm3s6965-ek/nx/defconfig +++ b/configs/lm3s6965-ek/nx/defconfig @@ -326,7 +326,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set CONFIG_BOARDCTL_GRAPHICS=y # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lm3s8962-ek/nsh/defconfig b/configs/lm3s8962-ek/nsh/defconfig index a13cba6072..823b410d3e 100644 --- a/configs/lm3s8962-ek/nsh/defconfig +++ b/configs/lm3s8962-ek/nsh/defconfig @@ -351,7 +351,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lm3s8962-ek/nx/defconfig b/configs/lm3s8962-ek/nx/defconfig index 1029b9998d..afef4c8ca8 100644 --- a/configs/lm3s8962-ek/nx/defconfig +++ b/configs/lm3s8962-ek/nx/defconfig @@ -336,7 +336,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set CONFIG_BOARDCTL_GRAPHICS=y # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lpc4330-xplorer/nsh/defconfig b/configs/lpc4330-xplorer/nsh/defconfig index 88cd838838..390ab0fa33 100644 --- a/configs/lpc4330-xplorer/nsh/defconfig +++ b/configs/lpc4330-xplorer/nsh/defconfig @@ -318,7 +318,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lpc4337-ws/nsh/defconfig b/configs/lpc4337-ws/nsh/defconfig index 663c53f16d..b73f0527bc 100644 --- a/configs/lpc4337-ws/nsh/defconfig +++ b/configs/lpc4337-ws/nsh/defconfig @@ -316,7 +316,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set CONFIG_BOARDCTL_ADCTEST=y -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lpc4357-evb/nsh/defconfig b/configs/lpc4357-evb/nsh/defconfig index b818e54be2..c01d703bea 100644 --- a/configs/lpc4357-evb/nsh/defconfig +++ b/configs/lpc4357-evb/nsh/defconfig @@ -310,7 +310,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lpc4370-link2/nsh/defconfig b/configs/lpc4370-link2/nsh/defconfig index 6d6a2394f3..b4a36288a1 100644 --- a/configs/lpc4370-link2/nsh/defconfig +++ b/configs/lpc4370-link2/nsh/defconfig @@ -318,7 +318,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lpcxpresso-lpc1768/nsh/defconfig b/configs/lpcxpresso-lpc1768/nsh/defconfig index 1ebf3b8ae9..11d4e02757 100644 --- a/configs/lpcxpresso-lpc1768/nsh/defconfig +++ b/configs/lpcxpresso-lpc1768/nsh/defconfig @@ -317,7 +317,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lpcxpresso-lpc1768/nx/defconfig b/configs/lpcxpresso-lpc1768/nx/defconfig index 692a436fec..4ac3ebe809 100644 --- a/configs/lpcxpresso-lpc1768/nx/defconfig +++ b/configs/lpcxpresso-lpc1768/nx/defconfig @@ -305,7 +305,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set CONFIG_BOARDCTL_GRAPHICS=y # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lpcxpresso-lpc1768/usbmsc/defconfig b/configs/lpcxpresso-lpc1768/usbmsc/defconfig index 87c84faf2d..21eac4b620 100644 --- a/configs/lpcxpresso-lpc1768/usbmsc/defconfig +++ b/configs/lpcxpresso-lpc1768/usbmsc/defconfig @@ -313,7 +313,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/maple/nx/defconfig b/configs/maple/nx/defconfig index a334252dcb..dcf5d4aded 100644 --- a/configs/maple/nx/defconfig +++ b/configs/maple/nx/defconfig @@ -579,7 +579,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/maple/usbnsh/defconfig b/configs/maple/usbnsh/defconfig index b0b0a2bc4f..8a6bca9ea7 100644 --- a/configs/maple/usbnsh/defconfig +++ b/configs/maple/usbnsh/defconfig @@ -545,7 +545,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mbed/nsh/defconfig b/configs/mbed/nsh/defconfig index 89b418da90..6c0cd29980 100644 --- a/configs/mbed/nsh/defconfig +++ b/configs/mbed/nsh/defconfig @@ -305,7 +305,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mcu123-lpc214x/composite/defconfig b/configs/mcu123-lpc214x/composite/defconfig index dde6e0a087..0073cceaf9 100644 --- a/configs/mcu123-lpc214x/composite/defconfig +++ b/configs/mcu123-lpc214x/composite/defconfig @@ -250,7 +250,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mcu123-lpc214x/nsh/defconfig b/configs/mcu123-lpc214x/nsh/defconfig index dbc7a65242..51e5c8b2fc 100644 --- a/configs/mcu123-lpc214x/nsh/defconfig +++ b/configs/mcu123-lpc214x/nsh/defconfig @@ -243,7 +243,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mcu123-lpc214x/usbmsc/defconfig b/configs/mcu123-lpc214x/usbmsc/defconfig index bc85948ea1..78b27e5c5a 100644 --- a/configs/mcu123-lpc214x/usbmsc/defconfig +++ b/configs/mcu123-lpc214x/usbmsc/defconfig @@ -250,7 +250,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mcu123-lpc214x/usbserial/defconfig b/configs/mcu123-lpc214x/usbserial/defconfig index 9d0ad75115..a8174a6940 100644 --- a/configs/mcu123-lpc214x/usbserial/defconfig +++ b/configs/mcu123-lpc214x/usbserial/defconfig @@ -249,7 +249,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mikroe-stm32f4/fulldemo/defconfig b/configs/mikroe-stm32f4/fulldemo/defconfig index ec9b61f877..9056cf58cd 100644 --- a/configs/mikroe-stm32f4/fulldemo/defconfig +++ b/configs/mikroe-stm32f4/fulldemo/defconfig @@ -604,7 +604,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARDCTL_TSCTEST=y # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mikroe-stm32f4/kostest/defconfig b/configs/mikroe-stm32f4/kostest/defconfig index a184e142c5..1eba3c8fc0 100644 --- a/configs/mikroe-stm32f4/kostest/defconfig +++ b/configs/mikroe-stm32f4/kostest/defconfig @@ -597,7 +597,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mikroe-stm32f4/nsh/defconfig b/configs/mikroe-stm32f4/nsh/defconfig index f83ae52238..84b304c3bc 100644 --- a/configs/mikroe-stm32f4/nsh/defconfig +++ b/configs/mikroe-stm32f4/nsh/defconfig @@ -578,7 +578,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mikroe-stm32f4/nx/defconfig b/configs/mikroe-stm32f4/nx/defconfig index a2d1c348fc..65e350b4b2 100644 --- a/configs/mikroe-stm32f4/nx/defconfig +++ b/configs/mikroe-stm32f4/nx/defconfig @@ -555,7 +555,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mikroe-stm32f4/nxlines/defconfig b/configs/mikroe-stm32f4/nxlines/defconfig index 87cc5aedfc..c997db7e16 100644 --- a/configs/mikroe-stm32f4/nxlines/defconfig +++ b/configs/mikroe-stm32f4/nxlines/defconfig @@ -546,7 +546,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mikroe-stm32f4/nxtext/defconfig b/configs/mikroe-stm32f4/nxtext/defconfig index a92b7cddc1..f81464664c 100644 --- a/configs/mikroe-stm32f4/nxtext/defconfig +++ b/configs/mikroe-stm32f4/nxtext/defconfig @@ -555,7 +555,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mikroe-stm32f4/usbnsh/defconfig b/configs/mikroe-stm32f4/usbnsh/defconfig index d267fdde99..c462790ac5 100644 --- a/configs/mikroe-stm32f4/usbnsh/defconfig +++ b/configs/mikroe-stm32f4/usbnsh/defconfig @@ -581,7 +581,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mirtoo/nxffs/defconfig b/configs/mirtoo/nxffs/defconfig index 06a76b0f07..ee4e547d14 100644 --- a/configs/mirtoo/nxffs/defconfig +++ b/configs/mirtoo/nxffs/defconfig @@ -342,7 +342,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/moxa/nsh/defconfig b/configs/moxa/nsh/defconfig index ca520d5eb9..b7dbca0b39 100644 --- a/configs/moxa/nsh/defconfig +++ b/configs/moxa/nsh/defconfig @@ -218,7 +218,6 @@ CONFIG_BOARDCTL_RESET=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/nr5m100-nexys4/nsh/defconfig b/configs/nr5m100-nexys4/nsh/defconfig index d282b47ccf..37ab198610 100644 --- a/configs/nr5m100-nexys4/nsh/defconfig +++ b/configs/nr5m100-nexys4/nsh/defconfig @@ -180,7 +180,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/nucleo-144/f746-evalos/defconfig b/configs/nucleo-144/f746-evalos/defconfig index ad4378e5d3..bc6229886d 100644 --- a/configs/nucleo-144/f746-evalos/defconfig +++ b/configs/nucleo-144/f746-evalos/defconfig @@ -441,7 +441,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/nucleo-144/f767-evalos/defconfig b/configs/nucleo-144/f767-evalos/defconfig index 45dc608217..ef3426fdd8 100644 --- a/configs/nucleo-144/f767-evalos/defconfig +++ b/configs/nucleo-144/f767-evalos/defconfig @@ -445,7 +445,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/nucleo-f303re/adc/defconfig b/configs/nucleo-f303re/adc/defconfig index 7701cf1093..d742cb5190 100644 --- a/configs/nucleo-f303re/adc/defconfig +++ b/configs/nucleo-f303re/adc/defconfig @@ -543,7 +543,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set CONFIG_BOARDCTL_ADCTEST=y -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/nucleo-f303re/can/defconfig b/configs/nucleo-f303re/can/defconfig index eaf665382c..ce3f030450 100644 --- a/configs/nucleo-f303re/can/defconfig +++ b/configs/nucleo-f303re/can/defconfig @@ -546,7 +546,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set CONFIG_BOARDCTL_CANINIT=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/nucleo-f303re/nxlines/defconfig b/configs/nucleo-f303re/nxlines/defconfig index 5c55292bf1..20a48e3d14 100644 --- a/configs/nucleo-f303re/nxlines/defconfig +++ b/configs/nucleo-f303re/nxlines/defconfig @@ -545,7 +545,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_CANINIT is not set CONFIG_BOARDCTL_GRAPHICS=y # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/nucleo-f303re/pwm/defconfig b/configs/nucleo-f303re/pwm/defconfig index 554dc26f59..5d5ea72956 100644 --- a/configs/nucleo-f303re/pwm/defconfig +++ b/configs/nucleo-f303re/pwm/defconfig @@ -547,7 +547,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -CONFIG_BOARDCTL_PWMTEST=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/nucleo-f303re/serialrx/defconfig b/configs/nucleo-f303re/serialrx/defconfig index ae3d607a70..afdb02265c 100644 --- a/configs/nucleo-f303re/serialrx/defconfig +++ b/configs/nucleo-f303re/serialrx/defconfig @@ -550,7 +550,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set CONFIG_BOARDCTL_ADCTEST=y -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/nucleo-f303re/src/nucleo-f303re.h b/configs/nucleo-f303re/src/nucleo-f303re.h index 8d9d21d227..d77bff2908 100644 --- a/configs/nucleo-f303re/src/nucleo-f303re.h +++ b/configs/nucleo-f303re/src/nucleo-f303re.h @@ -167,4 +167,16 @@ int stm32_timer_driver_setup(FAR const char *devpath, int timer); int stm32_dac_setup(void); #endif +/************************************************************************************ + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int stm32_pwm_setup(void); +#endif + #endif /* __CONFIGS_NUCLEO_F303RE_SRC_NUCLEO_F303RE_H */ diff --git a/configs/nucleo-f303re/src/stm32_appinitialize.c b/configs/nucleo-f303re/src/stm32_appinitialize.c index 7157606edb..1f6acb405a 100644 --- a/configs/nucleo-f303re/src/stm32_appinitialize.c +++ b/configs/nucleo-f303re/src/stm32_appinitialize.c @@ -110,6 +110,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + /* Contrairement à l'ADC, il n'y a pas de BOARDIOC_DAC_SETUP spécifique. Il * faut le faire ici */ diff --git a/configs/nucleo-f303re/src/stm32_pwm.c b/configs/nucleo-f303re/src/stm32_pwm.c index 7ab25eac4d..ae46bc7057 100644 --- a/configs/nucleo-f303re/src/stm32_pwm.c +++ b/configs/nucleo-f303re/src/stm32_pwm.c @@ -57,16 +57,15 @@ * Public Functions ****************************************************************************/ -/**************************************************************************** - * Name: board_pwm_setup +/************************************************************************************ + * Name: stm32_pwm_setup * * Description: - * All STM32 architectures must provide the following interface to work - * with examples/pwm. + * Initialize PWM and register the PWM device. * - ****************************************************************************/ + ************************************************************************************/ -int board_pwm_setup(void) +int stm32_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; diff --git a/configs/nucleo-l476rg/nsh/defconfig b/configs/nucleo-l476rg/nsh/defconfig index 3f05b78550..5e478f2e2a 100644 --- a/configs/nucleo-l476rg/nsh/defconfig +++ b/configs/nucleo-l476rg/nsh/defconfig @@ -370,7 +370,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-lpc-h3131/nsh/defconfig b/configs/olimex-lpc-h3131/nsh/defconfig index 4037c906c7..1ac70acd6c 100644 --- a/configs/olimex-lpc-h3131/nsh/defconfig +++ b/configs/olimex-lpc-h3131/nsh/defconfig @@ -256,7 +256,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-lpc1766stk/ftpc/defconfig b/configs/olimex-lpc1766stk/ftpc/defconfig index cdb8d28d0a..e812a9f414 100644 --- a/configs/olimex-lpc1766stk/ftpc/defconfig +++ b/configs/olimex-lpc1766stk/ftpc/defconfig @@ -317,7 +317,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-lpc1766stk/hidmouse/defconfig b/configs/olimex-lpc1766stk/hidmouse/defconfig index 82273f0771..99c9c14799 100644 --- a/configs/olimex-lpc1766stk/hidmouse/defconfig +++ b/configs/olimex-lpc1766stk/hidmouse/defconfig @@ -329,7 +329,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-lpc1766stk/nsh/defconfig b/configs/olimex-lpc1766stk/nsh/defconfig index dcacc2d2f6..c71430bf84 100644 --- a/configs/olimex-lpc1766stk/nsh/defconfig +++ b/configs/olimex-lpc1766stk/nsh/defconfig @@ -318,7 +318,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-lpc1766stk/nx/defconfig b/configs/olimex-lpc1766stk/nx/defconfig index e564252a62..3a547904fc 100644 --- a/configs/olimex-lpc1766stk/nx/defconfig +++ b/configs/olimex-lpc1766stk/nx/defconfig @@ -314,7 +314,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set CONFIG_BOARDCTL_GRAPHICS=y # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-lpc1766stk/usbmsc/defconfig b/configs/olimex-lpc1766stk/usbmsc/defconfig index e4931c1d56..ffaf78d6c7 100644 --- a/configs/olimex-lpc1766stk/usbmsc/defconfig +++ b/configs/olimex-lpc1766stk/usbmsc/defconfig @@ -314,7 +314,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-lpc1766stk/usbserial/defconfig b/configs/olimex-lpc1766stk/usbserial/defconfig index 39c6048cbb..6e06b1be4c 100644 --- a/configs/olimex-lpc1766stk/usbserial/defconfig +++ b/configs/olimex-lpc1766stk/usbserial/defconfig @@ -314,7 +314,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-lpc1766stk/zmodem/defconfig b/configs/olimex-lpc1766stk/zmodem/defconfig index 9ce6ae44c0..e7a6ae7dd8 100644 --- a/configs/olimex-lpc1766stk/zmodem/defconfig +++ b/configs/olimex-lpc1766stk/zmodem/defconfig @@ -319,7 +319,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-stm32-e407/usbnsh/defconfig b/configs/olimex-stm32-e407/usbnsh/defconfig index 8076c1a85a..7b8d7235a6 100644 --- a/configs/olimex-stm32-e407/usbnsh/defconfig +++ b/configs/olimex-stm32-e407/usbnsh/defconfig @@ -573,7 +573,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-stm32-h405/usbnsh/defconfig b/configs/olimex-stm32-h405/usbnsh/defconfig index 4823f38fd1..228c5da542 100644 --- a/configs/olimex-stm32-h405/usbnsh/defconfig +++ b/configs/olimex-stm32-h405/usbnsh/defconfig @@ -601,7 +601,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set CONFIG_BOARDCTL_ADCTEST=y -# CONFIG_BOARDCTL_PWMTEST is not set CONFIG_BOARDCTL_CANINIT=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-stm32-p207/nsh/defconfig b/configs/olimex-stm32-p207/nsh/defconfig index 86e6c4216d..12540090d2 100644 --- a/configs/olimex-stm32-p207/nsh/defconfig +++ b/configs/olimex-stm32-p207/nsh/defconfig @@ -627,7 +627,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set CONFIG_BOARDCTL_ADCTEST=y -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_CANINIT is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-strp711/nsh/defconfig b/configs/olimex-strp711/nsh/defconfig index 3e1009fe9b..85142cbcd5 100644 --- a/configs/olimex-strp711/nsh/defconfig +++ b/configs/olimex-strp711/nsh/defconfig @@ -253,7 +253,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimexino-stm32/can/defconfig b/configs/olimexino-stm32/can/defconfig index 42806be686..5217a05048 100644 --- a/configs/olimexino-stm32/can/defconfig +++ b/configs/olimexino-stm32/can/defconfig @@ -589,7 +589,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set CONFIG_BOARDCTL_CANINIT=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimexino-stm32/composite/defconfig b/configs/olimexino-stm32/composite/defconfig index be2146f2c9..fea02cc27e 100644 --- a/configs/olimexino-stm32/composite/defconfig +++ b/configs/olimexino-stm32/composite/defconfig @@ -598,7 +598,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimexino-stm32/nsh/defconfig b/configs/olimexino-stm32/nsh/defconfig index b9473b4cd9..1d5511ef13 100644 --- a/configs/olimexino-stm32/nsh/defconfig +++ b/configs/olimexino-stm32/nsh/defconfig @@ -597,7 +597,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimexino-stm32/smallnsh/defconfig b/configs/olimexino-stm32/smallnsh/defconfig index 496622da18..4eb59f7f21 100644 --- a/configs/olimexino-stm32/smallnsh/defconfig +++ b/configs/olimexino-stm32/smallnsh/defconfig @@ -570,7 +570,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set CONFIG_BOARDCTL_CANINIT=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimexino-stm32/tiny/defconfig b/configs/olimexino-stm32/tiny/defconfig index fda4a7b493..e84c5f9ce1 100644 --- a/configs/olimexino-stm32/tiny/defconfig +++ b/configs/olimexino-stm32/tiny/defconfig @@ -570,7 +570,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set CONFIG_BOARDCTL_CANINIT=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/open1788/nsh/defconfig b/configs/open1788/nsh/defconfig index 23c97563a9..b65783f70e 100644 --- a/configs/open1788/nsh/defconfig +++ b/configs/open1788/nsh/defconfig @@ -314,7 +314,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/pic32mx-starterkit/nsh/defconfig b/configs/pic32mx-starterkit/nsh/defconfig index 70b83ca1b2..9376fb2143 100644 --- a/configs/pic32mx-starterkit/nsh/defconfig +++ b/configs/pic32mx-starterkit/nsh/defconfig @@ -336,7 +336,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/pic32mx-starterkit/nsh2/defconfig b/configs/pic32mx-starterkit/nsh2/defconfig index 7768166473..2af0e68d5a 100644 --- a/configs/pic32mx-starterkit/nsh2/defconfig +++ b/configs/pic32mx-starterkit/nsh2/defconfig @@ -348,7 +348,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/pic32mx7mmb/nsh/defconfig b/configs/pic32mx7mmb/nsh/defconfig index aadcf0e895..b13b33cf70 100644 --- a/configs/pic32mx7mmb/nsh/defconfig +++ b/configs/pic32mx7mmb/nsh/defconfig @@ -357,7 +357,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/pic32mz-starterkit/nsh/defconfig b/configs/pic32mz-starterkit/nsh/defconfig index 58a9e43b6b..45e55691e9 100644 --- a/configs/pic32mz-starterkit/nsh/defconfig +++ b/configs/pic32mz-starterkit/nsh/defconfig @@ -263,7 +263,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/pirelli_dpl10/nsh_highram/defconfig b/configs/pirelli_dpl10/nsh_highram/defconfig index 549b8a3e0f..8c214d338b 100644 --- a/configs/pirelli_dpl10/nsh_highram/defconfig +++ b/configs/pirelli_dpl10/nsh_highram/defconfig @@ -242,7 +242,6 @@ CONFIG_BOARDCTL_POWEROFF=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sabre-6quad/nsh/defconfig b/configs/sabre-6quad/nsh/defconfig index 4c1cee390c..180a7f37eb 100644 --- a/configs/sabre-6quad/nsh/defconfig +++ b/configs/sabre-6quad/nsh/defconfig @@ -271,7 +271,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sabre-6quad/smp/defconfig b/configs/sabre-6quad/smp/defconfig index 22ca988805..ae16b4ce48 100644 --- a/configs/sabre-6quad/smp/defconfig +++ b/configs/sabre-6quad/smp/defconfig @@ -274,7 +274,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sam3u-ek/nsh/defconfig b/configs/sam3u-ek/nsh/defconfig index a4b7df6d05..0e6ca642f1 100644 --- a/configs/sam3u-ek/nsh/defconfig +++ b/configs/sam3u-ek/nsh/defconfig @@ -336,7 +336,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sam3u-ek/nxwm/defconfig b/configs/sam3u-ek/nxwm/defconfig index aa075785cc..29a8b18aa7 100644 --- a/configs/sam3u-ek/nxwm/defconfig +++ b/configs/sam3u-ek/nxwm/defconfig @@ -346,7 +346,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sam4cmp-db/nsh/defconfig b/configs/sam4cmp-db/nsh/defconfig index 8541fc330e..80453ba350 100644 --- a/configs/sam4cmp-db/nsh/defconfig +++ b/configs/sam4cmp-db/nsh/defconfig @@ -346,7 +346,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sam4e-ek/nsh/defconfig b/configs/sam4e-ek/nsh/defconfig index fc74521d7b..13422342f2 100644 --- a/configs/sam4e-ek/nsh/defconfig +++ b/configs/sam4e-ek/nsh/defconfig @@ -384,7 +384,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sam4e-ek/nxwm/defconfig b/configs/sam4e-ek/nxwm/defconfig index e886128820..126da5cc7e 100644 --- a/configs/sam4e-ek/nxwm/defconfig +++ b/configs/sam4e-ek/nxwm/defconfig @@ -396,7 +396,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sam4e-ek/usbnsh/defconfig b/configs/sam4e-ek/usbnsh/defconfig index ed8824bf3c..1ebbd2b786 100644 --- a/configs/sam4e-ek/usbnsh/defconfig +++ b/configs/sam4e-ek/usbnsh/defconfig @@ -390,7 +390,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sam4s-xplained-pro/nsh/defconfig b/configs/sam4s-xplained-pro/nsh/defconfig index a19c4101dd..231a7fcc1d 100644 --- a/configs/sam4s-xplained-pro/nsh/defconfig +++ b/configs/sam4s-xplained-pro/nsh/defconfig @@ -378,7 +378,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sama5d2-xult/nsh/defconfig b/configs/sama5d2-xult/nsh/defconfig index 4d386604bb..dc1ba8e882 100644 --- a/configs/sama5d2-xult/nsh/defconfig +++ b/configs/sama5d2-xult/nsh/defconfig @@ -407,7 +407,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sama5d3x-ek/demo/defconfig b/configs/sama5d3x-ek/demo/defconfig index 5771045f3e..48c33331d2 100644 --- a/configs/sama5d3x-ek/demo/defconfig +++ b/configs/sama5d3x-ek/demo/defconfig @@ -435,7 +435,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sama5d3x-ek/nxplayer/defconfig b/configs/sama5d3x-ek/nxplayer/defconfig index 9ed8ac0465..8059a6a420 100644 --- a/configs/sama5d3x-ek/nxplayer/defconfig +++ b/configs/sama5d3x-ek/nxplayer/defconfig @@ -432,7 +432,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sama5d3x-ek/nxwm/defconfig b/configs/sama5d3x-ek/nxwm/defconfig index 2db993f648..d6264e5b5b 100644 --- a/configs/sama5d3x-ek/nxwm/defconfig +++ b/configs/sama5d3x-ek/nxwm/defconfig @@ -448,7 +448,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sama5d4-ek/ipv6/defconfig b/configs/sama5d4-ek/ipv6/defconfig index 9f9c9506be..9c62baddfe 100644 --- a/configs/sama5d4-ek/ipv6/defconfig +++ b/configs/sama5d4-ek/ipv6/defconfig @@ -526,7 +526,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sama5d4-ek/nsh/defconfig b/configs/sama5d4-ek/nsh/defconfig index ef3a9884b4..01a6e3e281 100644 --- a/configs/sama5d4-ek/nsh/defconfig +++ b/configs/sama5d4-ek/nsh/defconfig @@ -526,7 +526,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sama5d4-ek/nxwm/defconfig b/configs/sama5d4-ek/nxwm/defconfig index c13d4c27b0..d5394ad53c 100644 --- a/configs/sama5d4-ek/nxwm/defconfig +++ b/configs/sama5d4-ek/nxwm/defconfig @@ -497,7 +497,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/same70-xplained/netnsh/defconfig b/configs/same70-xplained/netnsh/defconfig index 1b1b7be836..4eb2335b58 100644 --- a/configs/same70-xplained/netnsh/defconfig +++ b/configs/same70-xplained/netnsh/defconfig @@ -400,7 +400,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/same70-xplained/nsh/defconfig b/configs/same70-xplained/nsh/defconfig index 58d1ce23c5..c78142a8ba 100644 --- a/configs/same70-xplained/nsh/defconfig +++ b/configs/same70-xplained/nsh/defconfig @@ -385,7 +385,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/samv71-xult/knsh/defconfig b/configs/samv71-xult/knsh/defconfig index 6a9b6a2474..20879e5a1b 100644 --- a/configs/samv71-xult/knsh/defconfig +++ b/configs/samv71-xult/knsh/defconfig @@ -389,7 +389,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/samv71-xult/module/defconfig b/configs/samv71-xult/module/defconfig index ac536918bb..ddb8fd288c 100644 --- a/configs/samv71-xult/module/defconfig +++ b/configs/samv71-xult/module/defconfig @@ -363,7 +363,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_OS_SYMTAB=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/samv71-xult/mxtxplnd/defconfig b/configs/samv71-xult/mxtxplnd/defconfig index 43bb2b8cc9..70f1b6f86d 100644 --- a/configs/samv71-xult/mxtxplnd/defconfig +++ b/configs/samv71-xult/mxtxplnd/defconfig @@ -386,7 +386,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/samv71-xult/netnsh/defconfig b/configs/samv71-xult/netnsh/defconfig index 6a005c6e5d..8a9a66faa1 100644 --- a/configs/samv71-xult/netnsh/defconfig +++ b/configs/samv71-xult/netnsh/defconfig @@ -403,7 +403,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/samv71-xult/nsh/defconfig b/configs/samv71-xult/nsh/defconfig index 1e1c76f76b..89602972f2 100644 --- a/configs/samv71-xult/nsh/defconfig +++ b/configs/samv71-xult/nsh/defconfig @@ -388,7 +388,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/samv71-xult/nxwm/defconfig b/configs/samv71-xult/nxwm/defconfig index 81c2f922a2..7dc80e5ec5 100644 --- a/configs/samv71-xult/nxwm/defconfig +++ b/configs/samv71-xult/nxwm/defconfig @@ -386,7 +386,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/samv71-xult/vnc/defconfig b/configs/samv71-xult/vnc/defconfig index 90d26f1600..7e13d37a37 100644 --- a/configs/samv71-xult/vnc/defconfig +++ b/configs/samv71-xult/vnc/defconfig @@ -402,7 +402,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/samv71-xult/vnxwm/defconfig b/configs/samv71-xult/vnxwm/defconfig index 64ebea05db..1e51ed10e8 100644 --- a/configs/samv71-xult/vnxwm/defconfig +++ b/configs/samv71-xult/vnxwm/defconfig @@ -402,7 +402,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/shenzhou/nsh/defconfig b/configs/shenzhou/nsh/defconfig index beafbeecec..ad941f6951 100644 --- a/configs/shenzhou/nsh/defconfig +++ b/configs/shenzhou/nsh/defconfig @@ -586,7 +586,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/shenzhou/nxwm/defconfig b/configs/shenzhou/nxwm/defconfig index 093f2bd80c..4d41e08c5a 100644 --- a/configs/shenzhou/nxwm/defconfig +++ b/configs/shenzhou/nxwm/defconfig @@ -607,7 +607,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/shenzhou/thttpd/defconfig b/configs/shenzhou/thttpd/defconfig index 810b7d515f..a21ff7816d 100644 --- a/configs/shenzhou/thttpd/defconfig +++ b/configs/shenzhou/thttpd/defconfig @@ -587,7 +587,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sim/bas/defconfig b/configs/sim/bas/defconfig index 0b4597a317..70a460b8f6 100644 --- a/configs/sim/bas/defconfig +++ b/configs/sim/bas/defconfig @@ -148,7 +148,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_APP_SYMTAB is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sim/minibasic/defconfig b/configs/sim/minibasic/defconfig index ee1b5d9817..196c22194a 100644 --- a/configs/sim/minibasic/defconfig +++ b/configs/sim/minibasic/defconfig @@ -180,7 +180,6 @@ CONFIG_BOARDCTL_POWEROFF=y # CONFIG_BOARDCTL_APP_SYMTAB is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sim/nsh/defconfig b/configs/sim/nsh/defconfig index b44d379379..7c82a8b10d 100644 --- a/configs/sim/nsh/defconfig +++ b/configs/sim/nsh/defconfig @@ -157,7 +157,6 @@ CONFIG_BOARDCTL_POWEROFF=y # CONFIG_BOARDCTL_APP_SYMTAB is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sim/nsh2/defconfig b/configs/sim/nsh2/defconfig index 918e40e594..048787bdfd 100644 --- a/configs/sim/nsh2/defconfig +++ b/configs/sim/nsh2/defconfig @@ -166,7 +166,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sim/nxlines/defconfig b/configs/sim/nxlines/defconfig index f1a973024d..42d05ee1bc 100644 --- a/configs/sim/nxlines/defconfig +++ b/configs/sim/nxlines/defconfig @@ -157,7 +157,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sim/nxwm/defconfig b/configs/sim/nxwm/defconfig index 1b69d53d19..cf5b55d2d9 100644 --- a/configs/sim/nxwm/defconfig +++ b/configs/sim/nxwm/defconfig @@ -161,7 +161,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sim/touchscreen/defconfig b/configs/sim/touchscreen/defconfig index f290b2d544..3bbf0c93a0 100644 --- a/configs/sim/touchscreen/defconfig +++ b/configs/sim/touchscreen/defconfig @@ -162,7 +162,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sim/udgram/defconfig b/configs/sim/udgram/defconfig index e85867d7cb..215e1354f4 100644 --- a/configs/sim/udgram/defconfig +++ b/configs/sim/udgram/defconfig @@ -157,7 +157,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_APP_SYMTAB is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sim/unionfs/defconfig b/configs/sim/unionfs/defconfig index 8babf143da..9d522a9931 100644 --- a/configs/sim/unionfs/defconfig +++ b/configs/sim/unionfs/defconfig @@ -148,7 +148,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_APP_SYMTAB is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sim/ustream/defconfig b/configs/sim/ustream/defconfig index f495bcea50..87262350af 100644 --- a/configs/sim/ustream/defconfig +++ b/configs/sim/ustream/defconfig @@ -157,7 +157,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_APP_SYMTAB is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/spark/composite/defconfig b/configs/spark/composite/defconfig index 9c1a90f84f..55af6e92a4 100644 --- a/configs/spark/composite/defconfig +++ b/configs/spark/composite/defconfig @@ -558,7 +558,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/spark/nsh/defconfig b/configs/spark/nsh/defconfig index 09613a10f3..2a12c9e1bd 100644 --- a/configs/spark/nsh/defconfig +++ b/configs/spark/nsh/defconfig @@ -558,7 +558,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_USBDEVCTRL is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/spark/usbmsc/defconfig b/configs/spark/usbmsc/defconfig index 4c25d981cc..5627cee07c 100644 --- a/configs/spark/usbmsc/defconfig +++ b/configs/spark/usbmsc/defconfig @@ -558,7 +558,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/spark/usbnsh/defconfig b/configs/spark/usbnsh/defconfig index f92f017f03..9c91f06d90 100644 --- a/configs/spark/usbnsh/defconfig +++ b/configs/spark/usbnsh/defconfig @@ -557,7 +557,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/spark/usbserial/defconfig b/configs/spark/usbserial/defconfig index a11551266f..984b82f7d2 100644 --- a/configs/spark/usbserial/defconfig +++ b/configs/spark/usbserial/defconfig @@ -558,7 +558,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3210e-eval/composite/defconfig b/configs/stm3210e-eval/composite/defconfig index 16c1a20419..a7c0e15a10 100644 --- a/configs/stm3210e-eval/composite/defconfig +++ b/configs/stm3210e-eval/composite/defconfig @@ -580,7 +580,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3210e-eval/nsh/defconfig b/configs/stm3210e-eval/nsh/defconfig index e8d1d71f2c..31903c4a4d 100644 --- a/configs/stm3210e-eval/nsh/defconfig +++ b/configs/stm3210e-eval/nsh/defconfig @@ -581,7 +581,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_USBDEVCTRL is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3210e-eval/nsh2/defconfig b/configs/stm3210e-eval/nsh2/defconfig index 0c67ce8603..95774fa875 100644 --- a/configs/stm3210e-eval/nsh2/defconfig +++ b/configs/stm3210e-eval/nsh2/defconfig @@ -597,7 +597,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3210e-eval/nxterm/defconfig b/configs/stm3210e-eval/nxterm/defconfig index 7470e437ef..c10aeef17b 100644 --- a/configs/stm3210e-eval/nxterm/defconfig +++ b/configs/stm3210e-eval/nxterm/defconfig @@ -577,7 +577,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3210e-eval/pm/defconfig b/configs/stm3210e-eval/pm/defconfig index e1e7fae9f4..12758dc6c7 100644 --- a/configs/stm3210e-eval/pm/defconfig +++ b/configs/stm3210e-eval/pm/defconfig @@ -597,7 +597,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3210e-eval/usbmsc/defconfig b/configs/stm3210e-eval/usbmsc/defconfig index e02a938d76..a85a51a2aa 100644 --- a/configs/stm3210e-eval/usbmsc/defconfig +++ b/configs/stm3210e-eval/usbmsc/defconfig @@ -573,7 +573,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3210e-eval/usbserial/defconfig b/configs/stm3210e-eval/usbserial/defconfig index 195770cac3..5dcbcb817e 100644 --- a/configs/stm3210e-eval/usbserial/defconfig +++ b/configs/stm3210e-eval/usbserial/defconfig @@ -565,7 +565,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3220g-eval/nsh2/defconfig b/configs/stm3220g-eval/nsh2/defconfig index 69fb3cd888..e2c14711b9 100644 --- a/configs/stm3220g-eval/nsh2/defconfig +++ b/configs/stm3220g-eval/nsh2/defconfig @@ -604,7 +604,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3220g-eval/nxwm/defconfig b/configs/stm3220g-eval/nxwm/defconfig index fa8ab410a4..71096f14d2 100644 --- a/configs/stm3220g-eval/nxwm/defconfig +++ b/configs/stm3220g-eval/nxwm/defconfig @@ -623,7 +623,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3240g-eval/knxwm/defconfig b/configs/stm3240g-eval/knxwm/defconfig index 550117b4bc..55e71a0d6d 100644 --- a/configs/stm3240g-eval/knxwm/defconfig +++ b/configs/stm3240g-eval/knxwm/defconfig @@ -617,7 +617,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3240g-eval/nsh2/defconfig b/configs/stm3240g-eval/nsh2/defconfig index 6656348e26..14d341e3b2 100644 --- a/configs/stm3240g-eval/nsh2/defconfig +++ b/configs/stm3240g-eval/nsh2/defconfig @@ -608,7 +608,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3240g-eval/nxterm/defconfig b/configs/stm3240g-eval/nxterm/defconfig index 0042bbd78c..be5de3bcdc 100644 --- a/configs/stm3240g-eval/nxterm/defconfig +++ b/configs/stm3240g-eval/nxterm/defconfig @@ -627,7 +627,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3240g-eval/nxwm/defconfig b/configs/stm3240g-eval/nxwm/defconfig index eab7420dcf..fc3e55862e 100644 --- a/configs/stm3240g-eval/nxwm/defconfig +++ b/configs/stm3240g-eval/nxwm/defconfig @@ -627,7 +627,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32_tiny/nsh/defconfig b/configs/stm32_tiny/nsh/defconfig index 98ebea74e1..8997783b56 100644 --- a/configs/stm32_tiny/nsh/defconfig +++ b/configs/stm32_tiny/nsh/defconfig @@ -547,7 +547,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32_tiny/usbnsh/defconfig b/configs/stm32_tiny/usbnsh/defconfig index d680f70dad..a00da5fcaa 100644 --- a/configs/stm32_tiny/usbnsh/defconfig +++ b/configs/stm32_tiny/usbnsh/defconfig @@ -541,7 +541,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32butterfly2/nsh/defconfig b/configs/stm32butterfly2/nsh/defconfig index 96c060fd14..e036cc7e31 100644 --- a/configs/stm32butterfly2/nsh/defconfig +++ b/configs/stm32butterfly2/nsh/defconfig @@ -576,7 +576,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set CONFIG_BOARDCTL_ADCTEST=y -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32butterfly2/nshnet/defconfig b/configs/stm32butterfly2/nshnet/defconfig index b1321f4ee7..b234a4297d 100644 --- a/configs/stm32butterfly2/nshnet/defconfig +++ b/configs/stm32butterfly2/nshnet/defconfig @@ -584,7 +584,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set CONFIG_BOARDCTL_ADCTEST=y -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32butterfly2/nshusbdev/defconfig b/configs/stm32butterfly2/nshusbdev/defconfig index 83565df6ad..b30c5c9fd2 100644 --- a/configs/stm32butterfly2/nshusbdev/defconfig +++ b/configs/stm32butterfly2/nshusbdev/defconfig @@ -569,7 +569,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set CONFIG_BOARDCTL_ADCTEST=y -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32butterfly2/nshusbhost/defconfig b/configs/stm32butterfly2/nshusbhost/defconfig index 96c060fd14..e036cc7e31 100644 --- a/configs/stm32butterfly2/nshusbhost/defconfig +++ b/configs/stm32butterfly2/nshusbhost/defconfig @@ -576,7 +576,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set CONFIG_BOARDCTL_ADCTEST=y -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f103-minimum/audio_tone/defconfig b/configs/stm32f103-minimum/audio_tone/defconfig index 06ec48e05e..423deaad57 100644 --- a/configs/stm32f103-minimum/audio_tone/defconfig +++ b/configs/stm32f103-minimum/audio_tone/defconfig @@ -553,7 +553,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f103-minimum/buttons/defconfig b/configs/stm32f103-minimum/buttons/defconfig index a1ec7a28f0..3408e75ec4 100644 --- a/configs/stm32f103-minimum/buttons/defconfig +++ b/configs/stm32f103-minimum/buttons/defconfig @@ -543,7 +543,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f103-minimum/jlx12864g/defconfig b/configs/stm32f103-minimum/jlx12864g/defconfig index fb4a24692c..c7794055bb 100644 --- a/configs/stm32f103-minimum/jlx12864g/defconfig +++ b/configs/stm32f103-minimum/jlx12864g/defconfig @@ -595,7 +595,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f103-minimum/nsh/defconfig b/configs/stm32f103-minimum/nsh/defconfig index 91deca78db..da00dedca0 100644 --- a/configs/stm32f103-minimum/nsh/defconfig +++ b/configs/stm32f103-minimum/nsh/defconfig @@ -539,7 +539,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f103-minimum/pwm/defconfig b/configs/stm32f103-minimum/pwm/defconfig index a597b31441..152a1f55f1 100644 --- a/configs/stm32f103-minimum/pwm/defconfig +++ b/configs/stm32f103-minimum/pwm/defconfig @@ -551,7 +551,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -CONFIG_BOARDCTL_PWMTEST=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f103-minimum/rfid-rc522/defconfig b/configs/stm32f103-minimum/rfid-rc522/defconfig index 05a4cdb162..6fed7b2f8a 100644 --- a/configs/stm32f103-minimum/rfid-rc522/defconfig +++ b/configs/stm32f103-minimum/rfid-rc522/defconfig @@ -547,7 +547,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f103-minimum/rgbled/defconfig b/configs/stm32f103-minimum/rgbled/defconfig index 18f181819b..79a80423a6 100644 --- a/configs/stm32f103-minimum/rgbled/defconfig +++ b/configs/stm32f103-minimum/rgbled/defconfig @@ -578,7 +578,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f103-minimum/src/stm32_bringup.c b/configs/stm32f103-minimum/src/stm32_bringup.c index ed1cd3d415..a5b02ad4bc 100644 --- a/configs/stm32f103-minimum/src/stm32_bringup.c +++ b/configs/stm32f103-minimum/src/stm32_bringup.c @@ -106,6 +106,16 @@ int stm32_bringup(void) #endif int ret = OK; +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + #ifdef CONFIG_AUDIO_TONE /* Configure and initialize the tone generator. */ diff --git a/configs/stm32f103-minimum/src/stm32_pwm.c b/configs/stm32f103-minimum/src/stm32_pwm.c index 3238a9077b..c3e64baf7b 100644 --- a/configs/stm32f103-minimum/src/stm32_pwm.c +++ b/configs/stm32f103-minimum/src/stm32_pwm.c @@ -87,24 +87,19 @@ #ifdef HAVE_PWM -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_pwm_setup + * Name: stm32_pwm_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/pwm. + * Initialize PWM and register the PWM device. * ************************************************************************************/ -int board_pwm_setup(void) +int stm32_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; diff --git a/configs/stm32f103-minimum/src/stm32f103_minimum.h b/configs/stm32f103-minimum/src/stm32f103_minimum.h index 7b0f69ddf3..cb6185c107 100644 --- a/configs/stm32f103-minimum/src/stm32f103_minimum.h +++ b/configs/stm32f103-minimum/src/stm32f103_minimum.h @@ -168,6 +168,18 @@ int stm32_rgbled_setup(void); void stm32_usbinitialize(void); +/************************************************************************************ + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int stm32_pwm_setup(void); +#endif + /************************************************************************************ * Name: stm32_mfrc522initialize * diff --git a/configs/stm32f103-minimum/usbnsh/defconfig b/configs/stm32f103-minimum/usbnsh/defconfig index 411f621829..d93e7de8c9 100644 --- a/configs/stm32f103-minimum/usbnsh/defconfig +++ b/configs/stm32f103-minimum/usbnsh/defconfig @@ -541,7 +541,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f103-minimum/userled/defconfig b/configs/stm32f103-minimum/userled/defconfig index 5259eae061..f8c736137b 100644 --- a/configs/stm32f103-minimum/userled/defconfig +++ b/configs/stm32f103-minimum/userled/defconfig @@ -539,7 +539,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f103-minimum/veml6070/defconfig b/configs/stm32f103-minimum/veml6070/defconfig index ff8f7eaafa..28b6371670 100644 --- a/configs/stm32f103-minimum/veml6070/defconfig +++ b/configs/stm32f103-minimum/veml6070/defconfig @@ -564,7 +564,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f3discovery/nsh/defconfig b/configs/stm32f3discovery/nsh/defconfig index affc37c5ac..46b24777c9 100644 --- a/configs/stm32f3discovery/nsh/defconfig +++ b/configs/stm32f3discovery/nsh/defconfig @@ -557,7 +557,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f3discovery/usbnsh/defconfig b/configs/stm32f3discovery/usbnsh/defconfig index 3d3cdeb635..69eac04b68 100644 --- a/configs/stm32f3discovery/usbnsh/defconfig +++ b/configs/stm32f3discovery/usbnsh/defconfig @@ -564,7 +564,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f429i-disco/extflash/defconfig b/configs/stm32f429i-disco/extflash/defconfig index f16f70e8f0..3e89f5d9cd 100644 --- a/configs/stm32f429i-disco/extflash/defconfig +++ b/configs/stm32f429i-disco/extflash/defconfig @@ -594,7 +594,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f429i-disco/lcd/defconfig b/configs/stm32f429i-disco/lcd/defconfig index 3a44a86cf0..7742784b56 100644 --- a/configs/stm32f429i-disco/lcd/defconfig +++ b/configs/stm32f429i-disco/lcd/defconfig @@ -594,7 +594,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f429i-disco/usbmsc/defconfig b/configs/stm32f429i-disco/usbmsc/defconfig index f1b47adf0f..7eb67d1081 100644 --- a/configs/stm32f429i-disco/usbmsc/defconfig +++ b/configs/stm32f429i-disco/usbmsc/defconfig @@ -589,7 +589,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f429i-disco/usbnsh/defconfig b/configs/stm32f429i-disco/usbnsh/defconfig index bcc99f3740..b48cb3c714 100644 --- a/configs/stm32f429i-disco/usbnsh/defconfig +++ b/configs/stm32f429i-disco/usbnsh/defconfig @@ -580,7 +580,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f4discovery/canard/defconfig b/configs/stm32f4discovery/canard/defconfig index cede8f725a..3214be0633 100644 --- a/configs/stm32f4discovery/canard/defconfig +++ b/configs/stm32f4discovery/canard/defconfig @@ -590,7 +590,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set CONFIG_BOARDCTL_CANINIT=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f4discovery/ipv6/defconfig b/configs/stm32f4discovery/ipv6/defconfig index b2fd121eeb..001398e732 100644 --- a/configs/stm32f4discovery/ipv6/defconfig +++ b/configs/stm32f4discovery/ipv6/defconfig @@ -627,7 +627,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f4discovery/netnsh/defconfig b/configs/stm32f4discovery/netnsh/defconfig index 61d20ad657..cb5c0302a3 100644 --- a/configs/stm32f4discovery/netnsh/defconfig +++ b/configs/stm32f4discovery/netnsh/defconfig @@ -627,7 +627,6 @@ CONFIG_BOARDCTL_RESET=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f4discovery/usbnsh/defconfig b/configs/stm32f4discovery/usbnsh/defconfig index ca4f90464b..f2e1cdf6e0 100644 --- a/configs/stm32f4discovery/usbnsh/defconfig +++ b/configs/stm32f4discovery/usbnsh/defconfig @@ -589,7 +589,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig index e245af1cc1..75e20adb4b 100644 --- a/configs/stm32f746-ws/nsh/defconfig +++ b/configs/stm32f746-ws/nsh/defconfig @@ -470,7 +470,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32l476-mdk/nsh/defconfig b/configs/stm32l476-mdk/nsh/defconfig index fe3e8fc2a7..b92a9cf5bd 100644 --- a/configs/stm32l476-mdk/nsh/defconfig +++ b/configs/stm32l476-mdk/nsh/defconfig @@ -374,7 +374,6 @@ CONFIG_BOARDCTL_UNIQUEID=y CONFIG_BOARDCTL_UNIQUEID_SIZE=12 # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32l476vg-disco/nsh/defconfig b/configs/stm32l476vg-disco/nsh/defconfig index c621d79904..a6026d5a3c 100644 --- a/configs/stm32l476vg-disco/nsh/defconfig +++ b/configs/stm32l476vg-disco/nsh/defconfig @@ -392,7 +392,6 @@ CONFIG_BOARDCTL_UNIQUEID=y CONFIG_BOARDCTL_UNIQUEID_SIZE=12 # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set CONFIG_BOARDCTL_IOCTL=y diff --git a/configs/sure-pic32mx/nsh/defconfig b/configs/sure-pic32mx/nsh/defconfig index 5483e7d690..501cdf7639 100644 --- a/configs/sure-pic32mx/nsh/defconfig +++ b/configs/sure-pic32mx/nsh/defconfig @@ -340,7 +340,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sure-pic32mx/usbnsh/defconfig b/configs/sure-pic32mx/usbnsh/defconfig index f176dd6ad6..1d6f01fce4 100644 --- a/configs/sure-pic32mx/usbnsh/defconfig +++ b/configs/sure-pic32mx/usbnsh/defconfig @@ -342,7 +342,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/teensy-3.x/usbnsh/defconfig b/configs/teensy-3.x/usbnsh/defconfig index d0f1374b8f..31f717f133 100644 --- a/configs/teensy-3.x/usbnsh/defconfig +++ b/configs/teensy-3.x/usbnsh/defconfig @@ -308,7 +308,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/teensy-lc/nsh/defconfig b/configs/teensy-lc/nsh/defconfig index 24f484c47d..b9de76765e 100644 --- a/configs/teensy-lc/nsh/defconfig +++ b/configs/teensy-lc/nsh/defconfig @@ -273,7 +273,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/tm4c123g-launchpad/nsh/defconfig b/configs/tm4c123g-launchpad/nsh/defconfig index eee27b3313..ba93f9714a 100644 --- a/configs/tm4c123g-launchpad/nsh/defconfig +++ b/configs/tm4c123g-launchpad/nsh/defconfig @@ -339,7 +339,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/tm4c1294-launchpad/ipv6/defconfig b/configs/tm4c1294-launchpad/ipv6/defconfig index 936957248b..ea44f86d5f 100644 --- a/configs/tm4c1294-launchpad/ipv6/defconfig +++ b/configs/tm4c1294-launchpad/ipv6/defconfig @@ -358,7 +358,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/tm4c1294-launchpad/nsh/defconfig b/configs/tm4c1294-launchpad/nsh/defconfig index f2a84e52b8..f8cbc9e5a9 100644 --- a/configs/tm4c1294-launchpad/nsh/defconfig +++ b/configs/tm4c1294-launchpad/nsh/defconfig @@ -358,7 +358,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/tm4c1294-launchpad/src/tm4c_appinit.c b/configs/tm4c1294-launchpad/src/tm4c_appinit.c index 747c1f20df..35b1f1ce1b 100644 --- a/configs/tm4c1294-launchpad/src/tm4c_appinit.c +++ b/configs/tm4c1294-launchpad/src/tm4c_appinit.c @@ -87,26 +87,4 @@ int board_app_initialize(uintptr_t arg) #endif } -/**************************************************************************** - * Name: board_pwm_setup - * - * Description: - * No implementation for now, it's called by PWM tool via boardctl(). - * See include/nuttx/board.h - * - * Input Parameters: - * None. - * - * Returned Value: - * Zero on Success. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARDCTL_PWMTEST -int board_pwm_setup(void) -{ - return OK; -} -#endif /* CONFIG_BOARDCTL_PWMTEST */ - #endif /* CONFIG_LIB_BOARDCTL */ diff --git a/configs/u-blox-c027/nsh/defconfig b/configs/u-blox-c027/nsh/defconfig index c98cfdac70..a0845f5bad 100644 --- a/configs/u-blox-c027/nsh/defconfig +++ b/configs/u-blox-c027/nsh/defconfig @@ -324,7 +324,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/ubw32/nsh/defconfig b/configs/ubw32/nsh/defconfig index 42258d1f63..3c23567159 100644 --- a/configs/ubw32/nsh/defconfig +++ b/configs/ubw32/nsh/defconfig @@ -339,7 +339,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/zkit-arm-1769/nsh/defconfig b/configs/zkit-arm-1769/nsh/defconfig index 481f472b21..5762266bb1 100644 --- a/configs/zkit-arm-1769/nsh/defconfig +++ b/configs/zkit-arm-1769/nsh/defconfig @@ -318,7 +318,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/zkit-arm-1769/nxhello/defconfig b/configs/zkit-arm-1769/nxhello/defconfig index be2211450a..7a485050a8 100644 --- a/configs/zkit-arm-1769/nxhello/defconfig +++ b/configs/zkit-arm-1769/nxhello/defconfig @@ -318,7 +318,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/zp214xpa/nxlines/defconfig b/configs/zp214xpa/nxlines/defconfig index 12dbf6f2db..ebb8928ac1 100644 --- a/configs/zp214xpa/nxlines/defconfig +++ b/configs/zp214xpa/nxlines/defconfig @@ -237,7 +237,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set # CONFIG_BOARDCTL_ADCTEST is not set -# CONFIG_BOARDCTL_PWMTEST is not set CONFIG_BOARDCTL_GRAPHICS=y # CONFIG_BOARDCTL_IOCTL is not set diff --git a/include/nuttx/board.h b/include/nuttx/board.h index e143c4862b..72e39de945 100644 --- a/include/nuttx/board.h +++ b/include/nuttx/board.h @@ -332,23 +332,6 @@ void board_tsc_teardown(void); int board_adc_setup(void); -/**************************************************************************** - * Name: board_pwm_setup - * - * Description: - * All architectures must provide the following interface in order to - * work with examples/pwm. - * - * This is an internal OS interface but may be invoked indirectly from - * application-level graphics logic. If CONFIG_LIB_BOARDCTL=y and - * CONFIG_BOARDCTL_PWMTEST=y, then this functions will be invoked via the - * (non-standard) boardctl() interface using the commands - * BOARDIOC_PWMTEST_SETUP command. - * - ****************************************************************************/ - -int board_pwm_setup(void); - /**************************************************************************** * Name: board_graphics_setup * diff --git a/include/sys/boardctl.h b/include/sys/boardctl.h index ff7aeec6d7..6f0bd8253e 100644 --- a/include/sys/boardctl.h +++ b/include/sys/boardctl.h @@ -133,12 +133,6 @@ * CONFIGURATION: CONFIG_LIB_BOARDCTL && CONFIG_BOARDCTL_ADCTEST * DEPENDENCIES: Board logic must provide board_adc_setup() * - * CMD: BOARDIOC_PWMTEST_SETUP - * DESCRIPTION: PWM controller test configuration - * ARG: None - * CONFIGURATION: CONFIG_LIB_BOARDCTL && CONFIG_BOARDCTL_PWMTEST - * DEPENDENCIES: Board logic must provide board_pwm_setup() - * * CMD: BOARDIOC_CAN_INITIALIZE * DESCRIPTION: CAN device initialization * ARG: None @@ -164,9 +158,8 @@ #define BOARDIOC_TSCTEST_SETUP _BOARDIOC(0x0009) #define BOARDIOC_TSCTEST_TEARDOWN _BOARDIOC(0x000a) #define BOARDIOC_ADCTEST_SETUP _BOARDIOC(0x000b) -#define BOARDIOC_PWMTEST_SETUP _BOARDIOC(0x000c) -#define BOARDIOC_CAN_INITIALIZE _BOARDIOC(0x000d) -#define BOARDIOC_GRAPHICS_SETUP _BOARDIOC(0x000e) +#define BOARDIOC_CAN_INITIALIZE _BOARDIOC(0x000c) +#define BOARDIOC_GRAPHICS_SETUP _BOARDIOC(0x000d) /* If CONFIG_BOARDCTL_IOCTL=y, then boad-specific commands will be support. * In this case, all commands not recognized by boardctl() will be forwarded -- GitLab From 4b216ff8dde2377bcb1891334028f1257c2c02f5 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 5 Dec 2016 14:56:21 -0600 Subject: [PATCH 603/734] Finish removing traces of BOARDIOC_PWMSETUP --- configs/lpcxpresso-lpc1768/src/Makefile | 6 ++++- .../lpcxpresso-lpc1768/src/lpc17_appinit.c | 15 ++++++++++- configs/lpcxpresso-lpc1768/src/lpc17_pwm.c | 11 +++----- .../src/lpcxpresso-lpc1768.h | 14 ++++++++++- configs/mbed/src/Makefile | 6 ++++- configs/mbed/src/lpc17_appinit.c | 15 +++++++++++ configs/mbed/src/lpc17_pwm.c | 13 +++------- configs/mbed/src/mbed.h | 14 ++++++++++- configs/mikroe-stm32f4/src/mikroe-stm32f4.h | 12 +++++++++ configs/mikroe-stm32f4/src/stm32_appinit.c | 10 ++++++++ configs/mikroe-stm32f4/src/stm32_pwm.c | 17 +++++-------- configs/nucleo-l476rg/src/nucleo-l476rg.h | 12 +++++++++ configs/nucleo-l476rg/src/stm32_appinit.c | 10 ++++++++ configs/nucleo-l476rg/src/stm32_pwm.c | 13 +++------- configs/sama5d3-xplained/src/sam_appinit.c | 17 ++++++++++--- configs/sama5d3-xplained/src/sam_pwm.c | 13 +++------- .../sama5d3-xplained/src/sama5d3-xplained.h | 21 +++++++++++++--- configs/sama5d3x-ek/src/Makefile | 2 +- configs/sama5d3x-ek/src/sam_appinit.c | 15 ++++++++--- configs/sama5d3x-ek/src/sam_pwm.c | 13 +++------- configs/sama5d3x-ek/src/sama5d3x-ek.h | 12 +++++++++ configs/sama5d4-ek/src/sam_bringup.c | 18 ++++++++----- configs/sama5d4-ek/src/sam_pwm.c | 13 +++------- configs/sama5d4-ek/src/sama5d4-ek.h | 12 +++++++++ configs/stm3220g-eval/src/stm3220g-eval.h | 14 ++++++++++- configs/stm3220g-eval/src/stm32_appinit.c | 10 ++++++++ configs/stm3220g-eval/src/stm32_pwm.c | 13 +++------- configs/stm3240g-eval/src/stm3240g-eval.h | 14 ++++++++++- configs/stm3240g-eval/src/stm32_appinit.c | 10 ++++++++ configs/stm3240g-eval/src/stm32_pwm.c | 13 +++------- configs/stm32_tiny/src/stm32_appinit.c | 12 +++++++++ configs/stm32_tiny/src/stm32_pwm.c | 13 +++------- configs/stm32_tiny/src/stm32_tiny.h | 18 ++++++++++--- configs/stm32f3discovery/src/stm32_appinit.c | 10 ++++++++ configs/stm32f3discovery/src/stm32_pwm.c | 19 ++++++-------- .../stm32f3discovery/src/stm32f3discovery.h | 13 +++++++++- configs/stm32f4discovery/src/stm32_bringup.c | 10 ++++++++ configs/stm32f4discovery/src/stm32_pwm.c | 19 ++++++-------- configs/stm32f4discovery/src/stm32_rgbled.c | 5 ++-- .../stm32f4discovery/src/stm32f4discovery.h | 12 +++++++++ configs/stm32ldiscovery/src/stm32_appinit.c | 10 ++++++++ configs/stm32ldiscovery/src/stm32_pwm.c | 20 ++++++--------- configs/stm32ldiscovery/src/stm32ldiscovery.h | 12 +++++++++ configs/teensy-2.0/src/Makefile | 3 +++ configs/teensy-3.x/src/k20_appinit.c | 16 ++++++++++++ configs/teensy-3.x/src/k20_pwm.c | 11 +++----- configs/teensy-3.x/src/teensy-3x.h | 12 +++++++++ configs/teensy-lc/src/kl_appinit.c | 13 ++++++++++ configs/teensy-lc/src/kl_pwm.c | 13 +++------- configs/teensy-lc/src/teensy-lc.h | 12 +++++++++ configs/u-blox-c027/src/Makefile | 6 ++++- configs/u-blox-c027/src/lpc17_appinit.c | 13 ++++++++++ configs/u-blox-c027/src/lpc17_pwm.c | 7 +++--- configs/u-blox-c027/src/u-blox-c027.h | 25 +++++++++++++++---- 54 files changed, 494 insertions(+), 188 deletions(-) diff --git a/configs/lpcxpresso-lpc1768/src/Makefile b/configs/lpcxpresso-lpc1768/src/Makefile index c7a44a8284..971d589eb3 100644 --- a/configs/lpcxpresso-lpc1768/src/Makefile +++ b/configs/lpcxpresso-lpc1768/src/Makefile @@ -36,7 +36,11 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = lpc17_boot.c lpc17_leds.c lpc17_ssp.c lpc17_adc.c lpc17_dac.c lpc17_pwm.c +CSRCS = lpc17_boot.c lpc17_leds.c lpc17_ssp.c lpc17_adc.c lpc17_dac.c + +ifeq ($(CONFIG_PWM),y) +CSRCS += lpc17_pwm.c +endif ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += lpc17_appinit.c diff --git a/configs/lpcxpresso-lpc1768/src/lpc17_appinit.c b/configs/lpcxpresso-lpc1768/src/lpc17_appinit.c index 0aefdd37d4..fb55c2128c 100644 --- a/configs/lpcxpresso-lpc1768/src/lpc17_appinit.c +++ b/configs/lpcxpresso-lpc1768/src/lpc17_appinit.c @@ -139,9 +139,10 @@ int board_app_initialize(uintptr_t arg) { + int ret; + #ifdef NSH_HAVEMMCSD FAR struct spi_dev_s *ssp; - int ret; /* Get the SSP port */ @@ -169,5 +170,17 @@ int board_app_initialize(uintptr_t arg) syslog(LOG_INFO, "Successfuly bound SSP port %d to MMC/SD slot %d\n", CONFIG_NSH_MMCSDSPIPORTNO, CONFIG_NSH_MMCSDSLOTNO); #endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = lpcexpresso_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: lpcexpresso_pwm_setup() failed: %d\n", ret); + } +#endif + + UNUSED(ret); return OK; } diff --git a/configs/lpcxpresso-lpc1768/src/lpc17_pwm.c b/configs/lpcxpresso-lpc1768/src/lpc17_pwm.c index 5aec1613c1..27f122c27b 100644 --- a/configs/lpcxpresso-lpc1768/src/lpc17_pwm.c +++ b/configs/lpcxpresso-lpc1768/src/lpc17_pwm.c @@ -64,24 +64,19 @@ FAR struct pwm_lowerhalf_s *lpc17_pwminitialize(int timer); FAR struct pwm_lowerhalf_s *lpc17_mcpwminitialize(int timer); FAR struct pwm_lowerhalf_s *lpc17_timerinitialize(int timer); -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_pwm_setup + * Name: lpcexpresso_pwm_setup * * Description: - * All LPC17 architectures must provide the following interface to work with - * examples/pwm. + * Initialize PWM and register the PWM device. * ************************************************************************************/ -int board_pwm_setup(void) +int lpcexpresso_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; diff --git a/configs/lpcxpresso-lpc1768/src/lpcxpresso-lpc1768.h b/configs/lpcxpresso-lpc1768/src/lpcxpresso-lpc1768.h index 8b853a5df3..b88821559e 100644 --- a/configs/lpcxpresso-lpc1768/src/lpcxpresso-lpc1768.h +++ b/configs/lpcxpresso-lpc1768/src/lpcxpresso-lpc1768.h @@ -1,7 +1,7 @@ /************************************************************************************ * configs/lpcxpresso-lpc1768/src/lpcxpresso-lpc1768.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -230,6 +230,18 @@ void weak_function lpcxpresso_sspdev_initialize(void); +/************************************************************************************ + * Name: lpcexpresso_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int lpcexpresso_pwm_setup(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* _CONFIGS_LPCXPRESSO_LPC1768_SRC_LPCXPRESSO_H */ diff --git a/configs/mbed/src/Makefile b/configs/mbed/src/Makefile index 1bd5a3e33c..e2d360dac7 100644 --- a/configs/mbed/src/Makefile +++ b/configs/mbed/src/Makefile @@ -36,7 +36,7 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = lpc17_boot.c lpc17_leds.c lpc17_adc.c lpc17_dac.c lpc17_pwm.c +CSRCS = lpc17_boot.c lpc17_leds.c lpc17_adc.c lpc17_dac.c ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += lpc17_appinit.c @@ -45,6 +45,10 @@ ifeq ($(CONFIG_USBMSC),y) CSRCS += lpc17_usbmsc.c endif +ifeq ($(CONFIG_PWM),y) +CSRCS += lpc17_pwm.c +endif + ifeq ($(CONFIG_EXAMPLES_HIDKBD),y) CSRCS += lpc17_hidkbd.c endif diff --git a/configs/mbed/src/lpc17_appinit.c b/configs/mbed/src/lpc17_appinit.c index f70e811f3b..15c2a19556 100644 --- a/configs/mbed/src/lpc17_appinit.c +++ b/configs/mbed/src/lpc17_appinit.c @@ -47,6 +47,8 @@ #include #include +#include "mbed.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -97,5 +99,18 @@ int board_app_initialize(uintptr_t arg) { + int ret; + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = mbed_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: mbed_pwm_setup() failed: %d\n", ret); + } +#endif + + UNUSED(ret); return OK; } diff --git a/configs/mbed/src/lpc17_pwm.c b/configs/mbed/src/lpc17_pwm.c index 5b312bd71b..6ed91a0c20 100644 --- a/configs/mbed/src/lpc17_pwm.c +++ b/configs/mbed/src/lpc17_pwm.c @@ -3,7 +3,7 @@ * * Based on onfigs/lpcexpresso-lpc1768/lpc17_pwm.c * - * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2014-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -66,24 +66,19 @@ FAR struct pwm_lowerhalf_s *lpc17_pwminitialize(int timer); FAR struct pwm_lowerhalf_s *lpc17_mcpwminitialize(int timer); FAR struct pwm_lowerhalf_s *lpc17_timerinitialize(int timer); -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_pwm_setup + * Name: mbed_pwm_setup * * Description: - * All LPC17 architectures must provide the following interface to work with - * examples/pwm. + * Initialize PWM and register the PWM device. * ************************************************************************************/ -int board_pwm_setup(void) +int mbed_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; diff --git a/configs/mbed/src/mbed.h b/configs/mbed/src/mbed.h index 938372b780..2b8bac944c 100644 --- a/configs/mbed/src/mbed.h +++ b/configs/mbed/src/mbed.h @@ -1,7 +1,7 @@ /************************************************************************************ * configs/mbed/src/mbed.h * - * Copyright (C) 2010 Gregory Nutt. All rights reserved. + * Copyright (C) 2010, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -88,6 +88,18 @@ void weak_function mbed_sspdev_initialize(void); +/************************************************************************************ + * Name: mbed_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int mbed_pwm_setup(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* _CONFIGS_MBED_SRC_MBED_H */ diff --git a/configs/mikroe-stm32f4/src/mikroe-stm32f4.h b/configs/mikroe-stm32f4/src/mikroe-stm32f4.h index 20158043ed..be7b4edc17 100644 --- a/configs/mikroe-stm32f4/src/mikroe-stm32f4.h +++ b/configs/mikroe-stm32f4/src/mikroe-stm32f4.h @@ -227,6 +227,18 @@ void weak_function stm32_spidev_initialize(void); void weak_function stm32_usbinitialize(void); #endif +/************************************************************************************ + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int stm32_pwm_setup(void); +#endif + /**************************************************************************************************** * Name: stm32_usbhost_initialize * diff --git a/configs/mikroe-stm32f4/src/stm32_appinit.c b/configs/mikroe-stm32f4/src/stm32_appinit.c index 89828b2872..f42b6bc917 100644 --- a/configs/mikroe-stm32f4/src/stm32_appinit.c +++ b/configs/mikroe-stm32f4/src/stm32_appinit.c @@ -350,6 +350,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + #if defined(CONFIG_LCD_MIO283QT2) || defined(CONFIG_LCD_MIO283QT9A) /* Configure the TFT LCD module */ diff --git a/configs/mikroe-stm32f4/src/stm32_pwm.c b/configs/mikroe-stm32f4/src/stm32_pwm.c index 39ac1f2b6c..a4bb122a45 100644 --- a/configs/mikroe-stm32f4/src/stm32_pwm.c +++ b/configs/mikroe-stm32f4/src/stm32_pwm.c @@ -58,9 +58,9 @@ /* Configuration *******************************************************************/ /* PWM * - * The mikroe_stm32f4 has no real on-board PWM devices, but the board can be configured to output - * a pulse train using TIM4 CH2. This pin is used by FSMC is connect to CN5 just for this - * purpose: + * The mikroe_stm32f4 has no real on-board PWM devices, but the board can be + * configured to output a pulse train using TIM4 CH2. This pin is used by FSMC is + * connected to CN5 just for this purpose: * * PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB) * @@ -87,24 +87,19 @@ #ifdef HAVE_PWM -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_pwm_setup + * Name: stm32_pwm_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/pwm. + * Initialize PWM and register the PWM device. * ************************************************************************************/ -int board_pwm_setup(void) +int stm32_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; diff --git a/configs/nucleo-l476rg/src/nucleo-l476rg.h b/configs/nucleo-l476rg/src/nucleo-l476rg.h index 53915d0393..60bf27c713 100644 --- a/configs/nucleo-l476rg/src/nucleo-l476rg.h +++ b/configs/nucleo-l476rg/src/nucleo-l476rg.h @@ -327,6 +327,18 @@ void stm32_spiinitialize(void); void stm32_usbinitialize(void); +/************************************************************************************ + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int stm32_pwm_setup(void); +#endif + /************************************************************************************ * Name: board_adc_initialize * diff --git a/configs/nucleo-l476rg/src/stm32_appinit.c b/configs/nucleo-l476rg/src/stm32_appinit.c index ab2665bc73..3505a2faaa 100644 --- a/configs/nucleo-l476rg/src/stm32_appinit.c +++ b/configs/nucleo-l476rg/src/stm32_appinit.c @@ -196,6 +196,16 @@ int board_app_initialize(uintptr_t arg) syslog(LOG_INFO, "[boot] Initialized SDIO\n"); #endif +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + #ifdef CONFIG_AJOYSTICK /* Initialize and register the joystick driver */ diff --git a/configs/nucleo-l476rg/src/stm32_pwm.c b/configs/nucleo-l476rg/src/stm32_pwm.c index f5c00a1a64..3db43caacf 100644 --- a/configs/nucleo-l476rg/src/stm32_pwm.c +++ b/configs/nucleo-l476rg/src/stm32_pwm.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/nucleo-l476rg/src/stm32_pwm.c * - * Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Copyright (C) 2016 Sebastien Lorquet. All rights reserved. @@ -68,24 +68,19 @@ #ifdef CONFIG_PWM -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_pwm_setup + * Name: stm32_pwm_setup * * Description: - * All STM32L4 architectures must provide the following interface to work with - * examples/pwm. + * Initialize PWM and register the PWM device. * ************************************************************************************/ -int board_pwm_setup(void) +int stm32_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; diff --git a/configs/sama5d3-xplained/src/sam_appinit.c b/configs/sama5d3-xplained/src/sam_appinit.c index 34073c9f17..3001cf4774 100644 --- a/configs/sama5d3-xplained/src/sam_appinit.c +++ b/configs/sama5d3-xplained/src/sam_appinit.c @@ -85,11 +85,7 @@ int board_app_initialize(uintptr_t arg) { -#if defined(HAVE_NAND) || defined(HAVE_AT25) || defined(HAVE_HSMCI) || \ - defined(HAVE_USBHOST) || defined(HAVE_USBMONITOR) || \\ - defined(CONFIG_AJOYSTICK) || defined(CONFIG_FS_PROCFS) int ret; -#endif #ifdef HAVE_NAND /* Initialize the NAND driver */ @@ -175,6 +171,17 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = sam_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: sam_pwm_setup() failed: %d\n", ret); + return ret; + } +#endif + #ifdef CONFIG_FS_PROCFS /* Mount the procfs file system */ @@ -184,8 +191,10 @@ int board_app_initialize(uintptr_t arg) syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", SAMA5_PROCFS_MOUNTPOINT, ret); + return ret; } #endif + UNUSED(ret); return OK; } diff --git a/configs/sama5d3-xplained/src/sam_pwm.c b/configs/sama5d3-xplained/src/sam_pwm.c index a6acea54d8..bbb6b05417 100644 --- a/configs/sama5d3-xplained/src/sam_pwm.c +++ b/configs/sama5d3-xplained/src/sam_pwm.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/sama5d3-xplained/src/sam_pwm.c * - * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2014-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -107,24 +107,19 @@ #if defined(CONFIG_PWM) && defined(CONFIG_SAMA5_PWM) -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_pwm_setup + * Name: sam_pwm_setup * * Description: - * All SAMA5 architectures must provide the following interface to work with - * examples/pwm. + * Initialize PWM and register the PWM device. * ************************************************************************************/ -int board_pwm_setup(void) +int sam_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; diff --git a/configs/sama5d3-xplained/src/sama5d3-xplained.h b/configs/sama5d3-xplained/src/sama5d3-xplained.h index 66e1231a4c..18b8956907 100644 --- a/configs/sama5d3-xplained/src/sama5d3-xplained.h +++ b/configs/sama5d3-xplained/src/sama5d3-xplained.h @@ -725,19 +725,32 @@ bool sam_writeprotected(int slotno); void weak_function sam_usbinitialize(void); #endif -/**************************************************************************************************** +/************************************************************************************ * Name: stm32_usbhost_initialize * * Description: - * Called at application startup time to initialize the USB host functionality. This function will - * start a thread that will monitor for device connection/disconnection events. + * Called at application startup time to initialize the USB host functionality. + * This function will start a thread that will monitor for device connection/ + * disconnection events. * - ****************************************************************************************************/ + ************************************************************************************/ #ifdef HAVE_USBHOST int sam_usbhost_initialize(void); #endif +/************************************************************************************ + * Name: sam_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int sam_pwm_setup(void); +#endif + /************************************************************************************ * Name: sam_netinitialize * diff --git a/configs/sama5d3x-ek/src/Makefile b/configs/sama5d3x-ek/src/Makefile index 86fd69cd02..45cbfd26b4 100644 --- a/configs/sama5d3x-ek/src/Makefile +++ b/configs/sama5d3x-ek/src/Makefile @@ -1,7 +1,7 @@ ############################################################################ # configs/sama5d3x-ek/src/Makefile # -# Copyright (C) 2013-2014 Gregory Nutt. All rights reserved. +# Copyright (C) 2013-2014, 2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without diff --git a/configs/sama5d3x-ek/src/sam_appinit.c b/configs/sama5d3x-ek/src/sam_appinit.c index b3fb39f676..aee55a41a4 100644 --- a/configs/sama5d3x-ek/src/sam_appinit.c +++ b/configs/sama5d3x-ek/src/sam_appinit.c @@ -89,11 +89,7 @@ int board_app_initialize(uintptr_t arg) { -#if defined(HAVE_NAND) || defined(HAVE_AT25) || defined(HAVE_AT24) || \ - defined(HAVE_HSMCI) || defined(HAVE_USBHOST) || defined(HAVE_USBMONITOR) ||\ - defined(HAVE_WM8904) || defined(CONFIG_FS_PROCFS) int ret; -#endif #ifdef HAVE_NAND /* Initialize the NAND driver */ @@ -188,6 +184,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = sam_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: sam_pwm_setup() failed: %d\n", ret); + } +#endif + #ifdef CONFIG_FS_PROCFS /* Mount the procfs file system */ @@ -199,5 +205,6 @@ int board_app_initialize(uintptr_t arg) } #endif + UNUSED(ret); return OK; } diff --git a/configs/sama5d3x-ek/src/sam_pwm.c b/configs/sama5d3x-ek/src/sam_pwm.c index 8cc1642e71..0d422586bf 100644 --- a/configs/sama5d3x-ek/src/sam_pwm.c +++ b/configs/sama5d3x-ek/src/sam_pwm.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/sama5d3x-ek/src/sam_pwm.c * - * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -107,24 +107,19 @@ #if defined(CONFIG_PWM) && defined(CONFIG_SAMA5_PWM) -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_pwm_setup + * Name: sam_pwm_setup * * Description: - * All SAMA5 architectures must provide the following interface to work with - * examples/pwm. + * Initialize PWM and register the PWM device. * ************************************************************************************/ -int board_pwm_setup(void) +int sam_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; diff --git a/configs/sama5d3x-ek/src/sama5d3x-ek.h b/configs/sama5d3x-ek/src/sama5d3x-ek.h index 6521211395..5b1575fc3e 100644 --- a/configs/sama5d3x-ek/src/sama5d3x-ek.h +++ b/configs/sama5d3x-ek/src/sama5d3x-ek.h @@ -832,6 +832,18 @@ int sam_usbhost_initialize(void); void weak_function sam_netinitialize(void); #endif +/************************************************************************************ + * Name: sam_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int sam_pwm_setup(void); +#endif + /**************************************************************************** * Name: sam_wm8904_initialize * diff --git a/configs/sama5d4-ek/src/sam_bringup.c b/configs/sama5d4-ek/src/sam_bringup.c index 3aaccd3244..272e9251de 100644 --- a/configs/sama5d4-ek/src/sam_bringup.c +++ b/configs/sama5d4-ek/src/sam_bringup.c @@ -1,7 +1,7 @@ /**************************************************************************** * config/sama5d4-ek/src/sam_bringup.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -146,12 +146,7 @@ static void sam_i2ctool(void) int sam_bringup(void) { -#if defined(HAVE_NAND) || defined(HAVE_AT25) || defined(HAVE_HSMCI) || \ - defined(HAVE_USBHOST) || defined(HAVE_USBMONITOR) || defined(HAVE_WM8904) || \ - defined(HAVE_AUTOMOUNTER) || defined(HAVE_ELF) || defined(HAVE_ROMFS) || \ - defined(CONFIG_FS_PROCFS) int ret; -#endif /* Register I2C drivers on behalf of the I2C tool */ @@ -293,6 +288,16 @@ int sam_bringup(void) } #endif +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = sam_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: sam_pwm_setup() failed: %d\n", ret); + } +#endif + #ifdef HAVE_WM8904 /* Configure WM8904 audio */ @@ -340,5 +345,6 @@ int sam_bringup(void) * capabilities. */ + UNUSED(ret); return OK; } diff --git a/configs/sama5d4-ek/src/sam_pwm.c b/configs/sama5d4-ek/src/sam_pwm.c index ebae4ce11b..a3ad6760a7 100644 --- a/configs/sama5d4-ek/src/sam_pwm.c +++ b/configs/sama5d4-ek/src/sam_pwm.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/sama5d4-ek/src/sam_pwm.c * - * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2014-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -107,24 +107,19 @@ #if defined(CONFIG_PWM) && defined(CONFIG_SAMA5_PWM) -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_pwm_setup + * Name: sam_pwm_setup * * Description: - * All SAMA5 architectures must provide the following interface to work with - * examples/pwm. + * Initialize PWM and register the PWM device. * ************************************************************************************/ -int board_pwm_setup(void) +int sam_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; diff --git a/configs/sama5d4-ek/src/sama5d4-ek.h b/configs/sama5d4-ek/src/sama5d4-ek.h index ed7ff6bd2b..c4ebca971b 100644 --- a/configs/sama5d4-ek/src/sama5d4-ek.h +++ b/configs/sama5d4-ek/src/sama5d4-ek.h @@ -1073,6 +1073,18 @@ void weak_function sam_usbinitialize(void); int sam_usbhost_initialize(void); #endif +/************************************************************************************ + * Name: sam_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int sam_pwm_setup(void); +#endif + /************************************************************************************ * Name: sam_netinitialize * diff --git a/configs/stm3220g-eval/src/stm3220g-eval.h b/configs/stm3220g-eval/src/stm3220g-eval.h index d00b0e8eae..b15be6fd8f 100644 --- a/configs/stm3220g-eval/src/stm3220g-eval.h +++ b/configs/stm3220g-eval/src/stm3220g-eval.h @@ -1,7 +1,7 @@ /**************************************************************************************************** * configs/stm3220g_eval/src/stm3220g.h * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -249,6 +249,18 @@ void weak_function stm32_usbinitialize(void); int stm32_usbhost_initialize(void); #endif +/************************************************************************************ + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int stm32_pwm_setup(void); +#endif + /**************************************************************************************************** * Name: stm32_extmemgpios * diff --git a/configs/stm3220g-eval/src/stm32_appinit.c b/configs/stm3220g-eval/src/stm32_appinit.c index 93ed87e3c4..bcc176f4a1 100644 --- a/configs/stm3220g-eval/src/stm32_appinit.c +++ b/configs/stm3220g-eval/src/stm32_appinit.c @@ -294,5 +294,15 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + return OK; } diff --git a/configs/stm3220g-eval/src/stm32_pwm.c b/configs/stm3220g-eval/src/stm32_pwm.c index e689794d57..3063d1621e 100644 --- a/configs/stm3220g-eval/src/stm32_pwm.c +++ b/configs/stm3220g-eval/src/stm32_pwm.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/stm3220g-eval/src/stm32_pwm.c * - * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -65,24 +65,19 @@ #ifdef CONFIG_PWM -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_pwm_setup + * Name: stm32_pwm_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/pwm. + * Initialize PWM and register the PWM device. * ************************************************************************************/ -int board_pwm_setup(void) +int stm32_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; diff --git a/configs/stm3240g-eval/src/stm3240g-eval.h b/configs/stm3240g-eval/src/stm3240g-eval.h index 696d29e6a5..acef27fc53 100644 --- a/configs/stm3240g-eval/src/stm3240g-eval.h +++ b/configs/stm3240g-eval/src/stm3240g-eval.h @@ -1,7 +1,7 @@ /**************************************************************************************************** * configs/stm3240g_eval/src/stm3240g_eval.h * - * Copyright (C) 2011-2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -262,6 +262,18 @@ int stm32_usbhost_initialize(void); void stm32_led_initialize(void); #endif +/************************************************************************************ + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int stm32_pwm_setup(void); +#endif + /**************************************************************************************************** * Name: stm32_extmemgpios * diff --git a/configs/stm3240g-eval/src/stm32_appinit.c b/configs/stm3240g-eval/src/stm32_appinit.c index 7523030be2..6e8b94dffa 100644 --- a/configs/stm3240g-eval/src/stm32_appinit.c +++ b/configs/stm3240g-eval/src/stm32_appinit.c @@ -345,5 +345,15 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + return OK; } diff --git a/configs/stm3240g-eval/src/stm32_pwm.c b/configs/stm3240g-eval/src/stm32_pwm.c index a565995d42..e4085ee117 100644 --- a/configs/stm3240g-eval/src/stm32_pwm.c +++ b/configs/stm3240g-eval/src/stm32_pwm.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/stm3240g-eval/src/stm32_pwm.c * - * Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -65,24 +65,19 @@ #ifdef CONFIG_PWM -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_pwm_setup + * Name: stm32_pwm_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/pwm. + * Initialize PWM and register the PWM device. * ************************************************************************************/ -int board_pwm_setup(void) +int stm32_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; diff --git a/configs/stm32_tiny/src/stm32_appinit.c b/configs/stm32_tiny/src/stm32_appinit.c index 4b590de5d5..d9152f5ddf 100644 --- a/configs/stm32_tiny/src/stm32_appinit.c +++ b/configs/stm32_tiny/src/stm32_appinit.c @@ -80,6 +80,18 @@ int board_app_initialize(uintptr_t arg) { +#ifdef CONFIG_PWM + int ret; + + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + #if defined(CONFIG_WL_NRF24L01) syslog(LOG_INFO, "Register the nRF24L01 module"); stm32_wlinitialize(); diff --git a/configs/stm32_tiny/src/stm32_pwm.c b/configs/stm32_tiny/src/stm32_pwm.c index 675e9d0c15..86fb75cdfd 100644 --- a/configs/stm32_tiny/src/stm32_pwm.c +++ b/configs/stm32_tiny/src/stm32_pwm.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/stm32_tiny/src/stm32_pwm.c * - * Copyright (C) 2012-2013, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2012-2013, 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -63,24 +63,19 @@ #ifdef CONFIG_PWM -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_pwm_setup + * Name: stm32_pwm_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/pwm. + * Initialize PWM and register the PWM device. * ************************************************************************************/ -int board_pwm_setup(void) +int stm32_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; diff --git a/configs/stm32_tiny/src/stm32_tiny.h b/configs/stm32_tiny/src/stm32_tiny.h index daadcf2605..5a75d25d9f 100644 --- a/configs/stm32_tiny/src/stm32_tiny.h +++ b/configs/stm32_tiny/src/stm32_tiny.h @@ -121,7 +121,7 @@ * ************************************************************************************/ -extern void stm32_spidev_initialize(void); +void stm32_spidev_initialize(void); /************************************************************************************ * Name: stm32_usbinitialize @@ -131,7 +131,19 @@ extern void stm32_spidev_initialize(void); * ************************************************************************************/ -extern void stm32_usbinitialize(void); +void stm32_usbinitialize(void); + +/************************************************************************************ + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int stm32_pwm_setup(void); +#endif /************************************************************************************ * Name: stm32_wlinitialize @@ -141,7 +153,7 @@ extern void stm32_usbinitialize(void); * ************************************************************************************/ -extern void stm32_wlinitialize(void); +void stm32_wlinitialize(void); #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_HYMINI_STM32V_H */ diff --git a/configs/stm32f3discovery/src/stm32_appinit.c b/configs/stm32f3discovery/src/stm32_appinit.c index 68cb782539..6007b0a4f6 100644 --- a/configs/stm32f3discovery/src/stm32_appinit.c +++ b/configs/stm32f3discovery/src/stm32_appinit.c @@ -127,6 +127,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + #ifdef CONFIG_QENCODER /* Initialize and register the qencoder driver */ diff --git a/configs/stm32f3discovery/src/stm32_pwm.c b/configs/stm32f3discovery/src/stm32_pwm.c index a11d2a464a..e31a2e62fc 100644 --- a/configs/stm32f3discovery/src/stm32_pwm.c +++ b/configs/stm32f3discovery/src/stm32_pwm.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/stm32f3discovery/src/stm32_pwm.c * - * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -58,9 +58,9 @@ /* Configuration *******************************************************************/ /* PWM * - * The stm32f3discovery has no real on-board PWM devices, but the board can be configured to output - * a pulse train using TIM4 CH2. This pin is used by FSMC is connect to CN5 just for this - * purpose: + * The stm32f3discovery has no real on-board PWM devices, but the board can be + * configured to output a pulse train using TIM4 CH2. This pin is used by FSMC is + * connected to CN5 just for this purpose: * * PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB) * @@ -87,24 +87,19 @@ #ifdef HAVE_PWM -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_pwm_setup + * Name: stm32_pwm_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/pwm. + * Initialize PWM and register the PWM device. * ************************************************************************************/ -int board_pwm_setup(void) +int stm32_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; diff --git a/configs/stm32f3discovery/src/stm32f3discovery.h b/configs/stm32f3discovery/src/stm32f3discovery.h index 5b2e2626a0..0926778d8a 100644 --- a/configs/stm32f3discovery/src/stm32f3discovery.h +++ b/configs/stm32f3discovery/src/stm32f3discovery.h @@ -1,6 +1,5 @@ /**************************************************************************************************** * configs/stm32f3discovery/src/stm32f3discovery.h - * arch/arm/src/board/stm32f3discovery.n * * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -162,6 +161,18 @@ void weak_function stm32_spidev_initialize(void); void weak_function stm32_usbinitialize(void); #endif +/************************************************************************************ + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int stm32_pwm_setup(void); +#endif + /**************************************************************************** * Name: stm32_qencoder_initialize * diff --git a/configs/stm32f4discovery/src/stm32_bringup.c b/configs/stm32f4discovery/src/stm32_bringup.c index 8a800d59f3..496b17c2cc 100644 --- a/configs/stm32f4discovery/src/stm32_bringup.c +++ b/configs/stm32f4discovery/src/stm32_bringup.c @@ -159,6 +159,16 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + #ifdef CONFIG_QENCODER /* Initialize and register the qencoder driver */ diff --git a/configs/stm32f4discovery/src/stm32_pwm.c b/configs/stm32f4discovery/src/stm32_pwm.c index 5d7d8ee7fd..e8565b8fd0 100644 --- a/configs/stm32f4discovery/src/stm32_pwm.c +++ b/configs/stm32f4discovery/src/stm32_pwm.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/stm32f4discovery/src/stm32_pwm.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -56,9 +56,9 @@ /* Configuration *******************************************************************/ /* PWM * - * The stm32f4discovery has no real on-board PWM devices, but the board can be configured to output - * a pulse train using TIM4 CH2. This pin is used by FSMC is connect to CN5 just for this - * purpose: + * The stm32f4discovery has no real on-board PWM devices, but the board can be + * configured to output a pulse train using TIM4 CH2. This pin is used by FSMC is + * connected to CN5 just for this purpose: * * PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB) * @@ -85,24 +85,19 @@ #ifdef HAVE_PWM -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_pwm_setup + * Name: stm32_pwm_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/pwm. + * Initialize PWM and register the PWM device. * ************************************************************************************/ -int board_pwm_setup(void) +int stm32_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; diff --git a/configs/stm32f4discovery/src/stm32_rgbled.c b/configs/stm32f4discovery/src/stm32_rgbled.c index c1d320a05a..8f6fd9c8e7 100644 --- a/configs/stm32f4discovery/src/stm32_rgbled.c +++ b/configs/stm32f4discovery/src/stm32_rgbled.c @@ -93,11 +93,10 @@ ************************************************************************************/ /************************************************************************************ - * Name: board_pwm_setup + * Name: stm32_rgbled_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/pwm. + * Configure the RGB LED. * ************************************************************************************/ diff --git a/configs/stm32f4discovery/src/stm32f4discovery.h b/configs/stm32f4discovery/src/stm32f4discovery.h index 2d4f7a617a..b6754197ee 100644 --- a/configs/stm32f4discovery/src/stm32f4discovery.h +++ b/configs/stm32f4discovery/src/stm32f4discovery.h @@ -438,6 +438,18 @@ void weak_function stm32_usbinitialize(void); int stm32_usbhost_initialize(void); #endif +/************************************************************************************ + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int stm32_pwm_setup(void); +#endif + /**************************************************************************** * Name: stm32_extmemgpios * diff --git a/configs/stm32ldiscovery/src/stm32_appinit.c b/configs/stm32ldiscovery/src/stm32_appinit.c index b0f4909a2e..30db4f50f2 100644 --- a/configs/stm32ldiscovery/src/stm32_appinit.c +++ b/configs/stm32ldiscovery/src/stm32_appinit.c @@ -91,6 +91,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + #ifdef CONFIG_QENCODER /* Initialize and register the qencoder driver */ diff --git a/configs/stm32ldiscovery/src/stm32_pwm.c b/configs/stm32ldiscovery/src/stm32_pwm.c index 1aeca320fc..6e2753cf9d 100644 --- a/configs/stm32ldiscovery/src/stm32_pwm.c +++ b/configs/stm32ldiscovery/src/stm32_pwm.c @@ -1,8 +1,7 @@ /************************************************************************************ * configs/stm32ldiscovery/src/up_pwm.c - * arch/arm/src/board/up_pwm.c * - * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -59,9 +58,9 @@ /* Configuration *******************************************************************/ /* PWM * - * The stm32ldiscovery has no real on-board PWM devices, but the board can be configured to output - * a pulse train using TIM4 CH2. This pin is used by FSMC is connect to CN5 just for this - * purpose: + * The stm32ldiscovery has no real on-board PWM devices, but the board can be + * configured to output a pulse train using TIM4 CH2. This pin is used by FSMC is + * connected to CN5 just for this purpose: * * PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB) * @@ -88,24 +87,19 @@ #ifdef HAVE_PWM -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_pwm_setup + * Name: stm32_pwm_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/pwm. + * Initialize PWM and register the PWM device. * ************************************************************************************/ -int board_pwm_setup(void) +int stm32_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; diff --git a/configs/stm32ldiscovery/src/stm32ldiscovery.h b/configs/stm32ldiscovery/src/stm32ldiscovery.h index bf2f34e16e..c8d05a2c44 100644 --- a/configs/stm32ldiscovery/src/stm32ldiscovery.h +++ b/configs/stm32ldiscovery/src/stm32ldiscovery.h @@ -243,6 +243,18 @@ void weak_function stm32_spidev_initialize(void); +/************************************************************************************ + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int stm32_pwm_setup(void); +#endif + /**************************************************************************** * Name: stm32_qencoder_initialize * diff --git a/configs/teensy-2.0/src/Makefile b/configs/teensy-2.0/src/Makefile index ebf8c9b876..b56c428442 100644 --- a/configs/teensy-2.0/src/Makefile +++ b/configs/teensy-2.0/src/Makefile @@ -41,12 +41,15 @@ CSRCS = at90usb_boot.c ifeq ($(CONFIG_ARCH_LEDS),y) CSRCS += at90usb_leds.c endif + ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += at90usb_appinit.c endif + ifeq ($(CONFIG_USBMSC),y) CSRCS += at90usb_usbmsc.c endif + ifeq ($(CONFIG_AVR_SPI),y) CSRCS += at90usb_spi.c endif diff --git a/configs/teensy-3.x/src/k20_appinit.c b/configs/teensy-3.x/src/k20_appinit.c index f027eb7167..ae26f993f6 100644 --- a/configs/teensy-3.x/src/k20_appinit.c +++ b/configs/teensy-3.x/src/k20_appinit.c @@ -38,7 +38,10 @@ ****************************************************************************/ #include + #include +#include + #include #include "kinetis_usbotg.h" @@ -75,6 +78,8 @@ int board_app_initialize(uintptr_t arg) { + int ret; + #ifdef CONFIG_USBDEV /* Teensy is powered from usb and (bug?) only boots from being programmed, * so if usb is compiled in signal the controller driver that we're attached now. @@ -83,5 +88,16 @@ int board_app_initialize(uintptr_t arg) khci_usbattach(); #endif +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = kinetis_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: kinetis_pwm_setup() failed: %d\n", ret); + } +#endif + + UNUSED(ret); return OK; } diff --git a/configs/teensy-3.x/src/k20_pwm.c b/configs/teensy-3.x/src/k20_pwm.c index 5fc7652f16..6e0d384c18 100644 --- a/configs/teensy-3.x/src/k20_pwm.c +++ b/configs/teensy-3.x/src/k20_pwm.c @@ -66,24 +66,19 @@ extern struct pwm_lowerhalf_s *kinetis_pwminitialize(int timer); -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_pwm_setup + * Name: kinetis_pwm_setup * * Description: - * All Kinetis K20 architectures must provide the following interface to work with - * examples/pwm. + * Initialize PWM and register the PWM device. * ************************************************************************************/ -int board_pwm_setup(void) +int kinetis_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; diff --git a/configs/teensy-3.x/src/teensy-3x.h b/configs/teensy-3.x/src/teensy-3x.h index 030ac3d2cd..890845adbd 100644 --- a/configs/teensy-3.x/src/teensy-3x.h +++ b/configs/teensy-3.x/src/teensy-3x.h @@ -115,6 +115,18 @@ void kinetis_i2cdev_initialize(void); extern void weak_function kinetis_usbinitialize(void); +/************************************************************************************ + * Name: kinetis_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int kinetis_pwm_setup(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_TEENSY_3X_SRC_TEENSY_3X_H */ diff --git a/configs/teensy-lc/src/kl_appinit.c b/configs/teensy-lc/src/kl_appinit.c index fdd1e3bd30..654d1dfae2 100644 --- a/configs/teensy-lc/src/kl_appinit.c +++ b/configs/teensy-lc/src/kl_appinit.c @@ -78,6 +78,19 @@ int board_app_initialize(uintptr_t arg) { + int ret; + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = kl_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: kl_pwm_setup() failed: %d\n", ret); + } +#endif + + UNUSED(ret); return OK; } diff --git a/configs/teensy-lc/src/kl_pwm.c b/configs/teensy-lc/src/kl_pwm.c index 13d58804db..82d80b5432 100644 --- a/configs/teensy-lc/src/kl_pwm.c +++ b/configs/teensy-lc/src/kl_pwm.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/teensy-lc/src/kl_pwm.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * Alan Carvalho de Assis * @@ -66,24 +66,19 @@ extern struct pwm_lowerhalf_s *kl_pwminitialize(int timer); -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_pwm_setup + * Name: kl_pwm_setup * * Description: - * All Kinetis KL architectures must provide the following interface to work with - * examples/pwm. + * Initialize PWM and register the PWM device. * ************************************************************************************/ -int board_pwm_setup(void) +int kl_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; diff --git a/configs/teensy-lc/src/teensy-lc.h b/configs/teensy-lc/src/teensy-lc.h index 048fcaeab4..996c8677c4 100644 --- a/configs/teensy-lc/src/teensy-lc.h +++ b/configs/teensy-lc/src/teensy-lc.h @@ -79,6 +79,18 @@ void weak_function kl_spidev_initialize(void); +/************************************************************************************ + * Name: kl_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int kl_pwm_setup(void); +#endif + /**************************************************************************** * Name: kl_led_initialize * diff --git a/configs/u-blox-c027/src/Makefile b/configs/u-blox-c027/src/Makefile index 844046486e..e7a301c813 100644 --- a/configs/u-blox-c027/src/Makefile +++ b/configs/u-blox-c027/src/Makefile @@ -36,12 +36,16 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = lpc17_boot.c lpc17_leds.c lpc17_ssp.c lpc17_adc.c lpc17_dac.c lpc17_pwm.c +CSRCS = lpc17_boot.c lpc17_leds.c lpc17_ssp.c lpc17_adc.c lpc17_dac.c ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += lpc17_appinit.c endif +ifeq ($(CONFIG_PWM),y) +CSRCS += lpc17_pwm.c +endif + ifeq ($(CONFIG_MODEM_U_BLOX),y) CSRCS += lpc17_ubxmdm.c endif diff --git a/configs/u-blox-c027/src/lpc17_appinit.c b/configs/u-blox-c027/src/lpc17_appinit.c index f315953dfb..78b92d7004 100644 --- a/configs/u-blox-c027/src/lpc17_appinit.c +++ b/configs/u-blox-c027/src/lpc17_appinit.c @@ -195,5 +195,18 @@ int board_app_initialize(uintptr_t arg) syslog(LOG_INFO, "Successfuly bound SSP port %d to MMC/SD slot %d\n", CONFIG_NSH_MMCSDSPIPORTNO, CONFIG_NSH_MMCSDSLOTNO); #endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = lpc17_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: lpc17_pwm_setup() failed: %d\n", ret); + return ret; + } +#endif + + UNUSED(ret); return OK; } diff --git a/configs/u-blox-c027/src/lpc17_pwm.c b/configs/u-blox-c027/src/lpc17_pwm.c index 03569cc11d..3c4630d0f2 100644 --- a/configs/u-blox-c027/src/lpc17_pwm.c +++ b/configs/u-blox-c027/src/lpc17_pwm.c @@ -69,15 +69,14 @@ FAR struct pwm_lowerhalf_s *lpc17_timerinitialize(int timer); ************************************************************************************/ /************************************************************************************ - * Name: board_pwm_setup + * Name: lpc17_pwm_setup * * Description: - * All LPC17 architectures must provide the following interface to work with - * examples/pwm. + * Initialize PWM and register the PWM device. * ************************************************************************************/ -int board_pwm_setup(void) +int lpc17_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; diff --git a/configs/u-blox-c027/src/u-blox-c027.h b/configs/u-blox-c027/src/u-blox-c027.h index 6f2b8da990..c277eeeb50 100644 --- a/configs/u-blox-c027/src/u-blox-c027.h +++ b/configs/u-blox-c027/src/u-blox-c027.h @@ -90,14 +90,29 @@ void weak_function c027_sspdev_initialize(void); -#if defined(CONFIG_MODEM_U_BLOX) +/************************************************************************************ + * Name: lpc17_ubxmdm_init + * + * Description: + * Initialisation function for the u-blox modem. + * + ************************************************************************************/ -/* - * Initialisation function for the u-blox modem. - */ +#if defined(CONFIG_MODEM_U_BLOX) void lpc17_ubxmdm_init(bool usb_used); - #endif /* CONFIG_MODEM_U_BLOX */ +/************************************************************************************ + * Name: lpc17_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int lpc17_pwm_setup(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_U_BLOX_C027_SRC_U_BLOX_C027_H */ -- GitLab From 55dd1c87b39e3c2de843766b048c91c42cde3434 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 5 Dec 2016 15:31:40 -0600 Subject: [PATCH 604/734] Remove all references to BOARDIOC_ADCSETUP --- configs/Kconfig | 8 -------- configs/bambino-200e/nsh/defconfig | 1 - configs/boardctl.c | 17 +---------------- configs/cloudctrl/nsh/defconfig | 1 - configs/compal_e86/nsh_highram/defconfig | 1 - configs/compal_e88/nsh_highram/defconfig | 1 - configs/compal_e99/nsh_compalram/defconfig | 1 - configs/compal_e99/nsh_highram/defconfig | 1 - configs/dk-tm4c129x/ipv6/defconfig | 1 - configs/dk-tm4c129x/nsh/defconfig | 1 - configs/ea3131/nsh/defconfig | 1 - configs/ea3131/pgnsh/defconfig | 1 - configs/ea3131/usbserial/defconfig | 1 - configs/eagle100/nsh/defconfig | 1 - configs/ekk-lm3s9b96/nsh/defconfig | 1 - configs/fire-stm32v2/nsh/defconfig | 1 - configs/freedom-k64f/netnsh/defconfig | 1 - configs/freedom-k64f/nsh/defconfig | 1 - configs/freedom-kl25z/nsh/defconfig | 1 - configs/freedom-kl26z/nsh/defconfig | 1 - configs/hymini-stm32v/nsh/defconfig | 1 - configs/hymini-stm32v/nsh2/defconfig | 1 - configs/hymini-stm32v/usbmsc/defconfig | 1 - configs/hymini-stm32v/usbnsh/defconfig | 1 - configs/hymini-stm32v/usbserial/defconfig | 1 - configs/launchxl-tms57004/nsh/defconfig | 1 - configs/lincoln60/netnsh/defconfig | 1 - configs/lincoln60/nsh/defconfig | 1 - configs/lm3s6432-s2e/nsh/defconfig | 1 - configs/lm3s6965-ek/discover/defconfig | 1 - configs/lm3s6965-ek/nsh/defconfig | 1 - configs/lm3s6965-ek/nx/defconfig | 1 - configs/lm3s8962-ek/nsh/defconfig | 1 - configs/lm3s8962-ek/nx/defconfig | 1 - configs/lpc4330-xplorer/nsh/defconfig | 1 - configs/lpc4337-ws/nsh/defconfig | 1 - configs/lpc4357-evb/nsh/defconfig | 1 - configs/lpc4370-link2/nsh/defconfig | 1 - configs/lpcxpresso-lpc1768/nsh/defconfig | 1 - configs/lpcxpresso-lpc1768/nx/defconfig | 1 - configs/lpcxpresso-lpc1768/usbmsc/defconfig | 1 - configs/maple/nx/defconfig | 1 - configs/maple/usbnsh/defconfig | 1 - configs/mbed/nsh/defconfig | 1 - configs/mcu123-lpc214x/composite/defconfig | 1 - configs/mcu123-lpc214x/nsh/defconfig | 1 - configs/mcu123-lpc214x/usbmsc/defconfig | 1 - configs/mcu123-lpc214x/usbserial/defconfig | 1 - configs/mikroe-stm32f4/fulldemo/defconfig | 1 - configs/mikroe-stm32f4/kostest/defconfig | 1 - configs/mikroe-stm32f4/nsh/defconfig | 1 - configs/mikroe-stm32f4/nx/defconfig | 1 - configs/mikroe-stm32f4/nxlines/defconfig | 1 - configs/mikroe-stm32f4/nxtext/defconfig | 1 - configs/mikroe-stm32f4/usbnsh/defconfig | 1 - configs/mirtoo/nxffs/defconfig | 1 - configs/moxa/nsh/defconfig | 1 - configs/nr5m100-nexys4/nsh/defconfig | 1 - configs/nucleo-144/f746-evalos/defconfig | 1 - configs/nucleo-144/f767-evalos/defconfig | 1 - configs/nucleo-f303re/adc/defconfig | 1 - configs/nucleo-f303re/can/defconfig | 1 - configs/nucleo-f303re/nxlines/defconfig | 1 - configs/nucleo-f303re/pwm/defconfig | 1 - configs/nucleo-f303re/serialrx/defconfig | 1 - configs/nucleo-l476rg/nsh/defconfig | 1 - configs/olimex-lpc-h3131/nsh/defconfig | 1 - configs/olimex-lpc1766stk/ftpc/defconfig | 1 - configs/olimex-lpc1766stk/hidmouse/defconfig | 1 - configs/olimex-lpc1766stk/nsh/defconfig | 1 - configs/olimex-lpc1766stk/nx/defconfig | 1 - configs/olimex-lpc1766stk/usbmsc/defconfig | 1 - configs/olimex-lpc1766stk/usbserial/defconfig | 1 - configs/olimex-lpc1766stk/zmodem/defconfig | 1 - configs/olimex-stm32-e407/usbnsh/defconfig | 1 - configs/olimex-stm32-h405/usbnsh/defconfig | 1 - configs/olimex-stm32-p207/nsh/defconfig | 1 - configs/olimex-strp711/nsh/defconfig | 1 - configs/olimexino-stm32/can/defconfig | 1 - configs/olimexino-stm32/composite/defconfig | 1 - configs/olimexino-stm32/nsh/defconfig | 1 - configs/olimexino-stm32/smallnsh/defconfig | 1 - configs/olimexino-stm32/tiny/defconfig | 1 - configs/open1788/nsh/defconfig | 1 - configs/pic32mx-starterkit/nsh/defconfig | 1 - configs/pic32mx-starterkit/nsh2/defconfig | 1 - configs/pic32mx7mmb/nsh/defconfig | 1 - configs/pic32mz-starterkit/nsh/defconfig | 1 - configs/pirelli_dpl10/nsh_highram/defconfig | 1 - configs/sabre-6quad/nsh/defconfig | 1 - configs/sabre-6quad/smp/defconfig | 1 - configs/sam3u-ek/nsh/defconfig | 1 - configs/sam3u-ek/nxwm/defconfig | 1 - configs/sam4cmp-db/nsh/defconfig | 1 - configs/sam4e-ek/nsh/defconfig | 1 - configs/sam4e-ek/nxwm/defconfig | 1 - configs/sam4e-ek/usbnsh/defconfig | 1 - configs/sam4s-xplained-pro/nsh/defconfig | 1 - configs/sama5d2-xult/nsh/defconfig | 1 - configs/sama5d3x-ek/demo/defconfig | 1 - configs/sama5d3x-ek/nxplayer/defconfig | 1 - configs/sama5d3x-ek/nxwm/defconfig | 1 - configs/sama5d4-ek/ipv6/defconfig | 1 - configs/sama5d4-ek/nsh/defconfig | 1 - configs/sama5d4-ek/nxwm/defconfig | 1 - configs/same70-xplained/netnsh/defconfig | 1 - configs/same70-xplained/nsh/defconfig | 1 - configs/samv71-xult/knsh/defconfig | 1 - configs/samv71-xult/module/defconfig | 1 - configs/samv71-xult/mxtxplnd/defconfig | 1 - configs/samv71-xult/netnsh/defconfig | 1 - configs/samv71-xult/nsh/defconfig | 1 - configs/samv71-xult/nxwm/defconfig | 1 - configs/samv71-xult/vnc/defconfig | 1 - configs/samv71-xult/vnxwm/defconfig | 1 - configs/shenzhou/nsh/defconfig | 1 - configs/shenzhou/nxwm/defconfig | 1 - configs/shenzhou/thttpd/defconfig | 1 - configs/sim/bas/defconfig | 1 - configs/sim/minibasic/defconfig | 1 - configs/sim/nsh/defconfig | 1 - configs/sim/nsh2/defconfig | 1 - configs/sim/nxlines/defconfig | 1 - configs/sim/nxwm/defconfig | 1 - configs/sim/touchscreen/defconfig | 1 - configs/sim/udgram/defconfig | 1 - configs/sim/unionfs/defconfig | 1 - configs/sim/ustream/defconfig | 1 - configs/spark/composite/defconfig | 1 - configs/spark/nsh/defconfig | 1 - configs/spark/usbmsc/defconfig | 1 - configs/spark/usbnsh/defconfig | 1 - configs/spark/usbserial/defconfig | 1 - configs/stm3210e-eval/composite/defconfig | 1 - configs/stm3210e-eval/nsh/defconfig | 1 - configs/stm3210e-eval/nsh2/defconfig | 1 - configs/stm3210e-eval/nxterm/defconfig | 1 - configs/stm3210e-eval/pm/defconfig | 1 - configs/stm3210e-eval/usbmsc/defconfig | 1 - configs/stm3210e-eval/usbserial/defconfig | 1 - configs/stm3220g-eval/nsh2/defconfig | 1 - configs/stm3220g-eval/nxwm/defconfig | 1 - configs/stm3240g-eval/knxwm/defconfig | 1 - configs/stm3240g-eval/nsh2/defconfig | 1 - configs/stm3240g-eval/nxterm/defconfig | 1 - configs/stm3240g-eval/nxwm/defconfig | 1 - configs/stm32_tiny/nsh/defconfig | 1 - configs/stm32_tiny/usbnsh/defconfig | 1 - configs/stm32butterfly2/nsh/defconfig | 1 - configs/stm32butterfly2/nshnet/defconfig | 1 - configs/stm32butterfly2/nshusbdev/defconfig | 1 - configs/stm32butterfly2/nshusbhost/defconfig | 1 - configs/stm32f103-minimum/audio_tone/defconfig | 1 - configs/stm32f103-minimum/buttons/defconfig | 1 - configs/stm32f103-minimum/jlx12864g/defconfig | 1 - configs/stm32f103-minimum/nsh/defconfig | 1 - configs/stm32f103-minimum/pwm/defconfig | 1 - configs/stm32f103-minimum/rfid-rc522/defconfig | 1 - configs/stm32f103-minimum/rgbled/defconfig | 1 - configs/stm32f103-minimum/usbnsh/defconfig | 1 - configs/stm32f103-minimum/userled/defconfig | 1 - configs/stm32f103-minimum/veml6070/defconfig | 1 - configs/stm32f3discovery/nsh/defconfig | 1 - configs/stm32f3discovery/usbnsh/defconfig | 1 - configs/stm32f429i-disco/extflash/defconfig | 1 - configs/stm32f429i-disco/lcd/defconfig | 1 - configs/stm32f429i-disco/usbmsc/defconfig | 1 - configs/stm32f429i-disco/usbnsh/defconfig | 1 - configs/stm32f4discovery/canard/defconfig | 1 - configs/stm32f4discovery/ipv6/defconfig | 1 - configs/stm32f4discovery/netnsh/defconfig | 1 - configs/stm32f4discovery/usbnsh/defconfig | 1 - configs/stm32f746-ws/nsh/defconfig | 1 - configs/stm32l476-mdk/nsh/defconfig | 1 - configs/stm32l476vg-disco/nsh/defconfig | 1 - configs/sure-pic32mx/nsh/defconfig | 1 - configs/sure-pic32mx/usbnsh/defconfig | 1 - configs/teensy-3.x/usbnsh/defconfig | 1 - configs/teensy-lc/nsh/defconfig | 1 - configs/tm4c123g-launchpad/nsh/defconfig | 1 - configs/tm4c1294-launchpad/ipv6/defconfig | 1 - configs/tm4c1294-launchpad/nsh/defconfig | 1 - configs/u-blox-c027/nsh/defconfig | 1 - configs/ubw32/nsh/defconfig | 1 - configs/zkit-arm-1769/nsh/defconfig | 1 - configs/zkit-arm-1769/nxhello/defconfig | 1 - configs/zp214xpa/nxlines/defconfig | 1 - include/nuttx/board.h | 17 ----------------- include/sys/boardctl.h | 11 ++--------- 189 files changed, 3 insertions(+), 235 deletions(-) diff --git a/configs/Kconfig b/configs/Kconfig index ba68a4e541..ea7efa2104 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -2029,14 +2029,6 @@ config BOARDCTL_TSCTEST specific logic must provide board_tsc_setup() and board_tsc_teardown() interfaces. -config BOARDCTL_ADCTEST - bool "Enable ADC test interfaces" - default n - ---help--- - Enables support for the BOARDIOC_ADCTEST_SETUP boardctl() command. - Architecture specific logic must provide board_adc_setup() - interface. - config BOARDCTL_CANINIT bool "Enable CAN initialize interface" default n diff --git a/configs/bambino-200e/nsh/defconfig b/configs/bambino-200e/nsh/defconfig index 6ca4351125..56947667f4 100644 --- a/configs/bambino-200e/nsh/defconfig +++ b/configs/bambino-200e/nsh/defconfig @@ -329,7 +329,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/boardctl.c b/configs/boardctl.c index 4807769731..d073420d79 100644 --- a/configs/boardctl.c +++ b/configs/boardctl.c @@ -426,21 +426,6 @@ int boardctl(unsigned int cmd, uintptr_t arg) break; #endif -#ifdef CONFIG_BOARDCTL_ADCTEST - /* CMD: BOARDIOC_ADCTEST_SETUP - * DESCRIPTION: ADC controller test configuration - * ARG: None - * CONFIGURATION: CONFIG_LIB_BOARDCTL && CONFIG_BOARDCTL_ADCTEST - * DEPENDENCIES: Board logic must provide board_adc_setup() - */ - - case BOARDIOC_ADCTEST_SETUP: - { - ret = board_adc_setup(); - } - break; -#endif - #ifdef CONFIG_BOARDCTL_CANINIT /* CMD: BOARDIOC_CAN_INITIALIZE * DESCRIPTION: CAN device initialization @@ -462,7 +447,7 @@ int boardctl(unsigned int cmd, uintptr_t arg) * procedures * ARG: A pointer to an instance of struct boardioc_graphics_s * CONFIGURATION: CONFIG_LIB_BOARDCTL && CONFIG_BOARDCTL_GRAPHICS - * DEPENDENCIES: Board logic must provide board_adc_setup() + * DEPENDENCIES: Board logic must provide board_graphics_setup() */ case BOARDIOC_GRAPHICS_SETUP: diff --git a/configs/cloudctrl/nsh/defconfig b/configs/cloudctrl/nsh/defconfig index 053a106531..3fa1500ea5 100644 --- a/configs/cloudctrl/nsh/defconfig +++ b/configs/cloudctrl/nsh/defconfig @@ -593,7 +593,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/compal_e86/nsh_highram/defconfig b/configs/compal_e86/nsh_highram/defconfig index 0b88e0cb10..7ea34d54da 100644 --- a/configs/compal_e86/nsh_highram/defconfig +++ b/configs/compal_e86/nsh_highram/defconfig @@ -240,7 +240,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_POWEROFF=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/compal_e88/nsh_highram/defconfig b/configs/compal_e88/nsh_highram/defconfig index a05d578955..3672faf14d 100644 --- a/configs/compal_e88/nsh_highram/defconfig +++ b/configs/compal_e88/nsh_highram/defconfig @@ -240,7 +240,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_POWEROFF=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/compal_e99/nsh_compalram/defconfig b/configs/compal_e99/nsh_compalram/defconfig index 746b5c0f42..f5dc463da4 100644 --- a/configs/compal_e99/nsh_compalram/defconfig +++ b/configs/compal_e99/nsh_compalram/defconfig @@ -242,7 +242,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_POWEROFF=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/compal_e99/nsh_highram/defconfig b/configs/compal_e99/nsh_highram/defconfig index 86d90fbd39..6129f41748 100644 --- a/configs/compal_e99/nsh_highram/defconfig +++ b/configs/compal_e99/nsh_highram/defconfig @@ -244,7 +244,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_POWEROFF=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/dk-tm4c129x/ipv6/defconfig b/configs/dk-tm4c129x/ipv6/defconfig index 84a22592c7..cdbfd30b3d 100644 --- a/configs/dk-tm4c129x/ipv6/defconfig +++ b/configs/dk-tm4c129x/ipv6/defconfig @@ -367,7 +367,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/dk-tm4c129x/nsh/defconfig b/configs/dk-tm4c129x/nsh/defconfig index 674bd5f241..48231e3d5e 100644 --- a/configs/dk-tm4c129x/nsh/defconfig +++ b/configs/dk-tm4c129x/nsh/defconfig @@ -367,7 +367,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/ea3131/nsh/defconfig b/configs/ea3131/nsh/defconfig index 6008b42558..c47bb4d67c 100644 --- a/configs/ea3131/nsh/defconfig +++ b/configs/ea3131/nsh/defconfig @@ -257,7 +257,6 @@ CONFIG_NSH_MMCSDMINOR=0 CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/ea3131/pgnsh/defconfig b/configs/ea3131/pgnsh/defconfig index 21bd28018e..39c05cad92 100644 --- a/configs/ea3131/pgnsh/defconfig +++ b/configs/ea3131/pgnsh/defconfig @@ -279,7 +279,6 @@ CONFIG_EA3131_PAGING_SPIPORT=0 CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/ea3131/usbserial/defconfig b/configs/ea3131/usbserial/defconfig index ec611ad315..69f48400c0 100644 --- a/configs/ea3131/usbserial/defconfig +++ b/configs/ea3131/usbserial/defconfig @@ -265,7 +265,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/eagle100/nsh/defconfig b/configs/eagle100/nsh/defconfig index 5e84f8454d..fd7f6e6e4d 100644 --- a/configs/eagle100/nsh/defconfig +++ b/configs/eagle100/nsh/defconfig @@ -346,7 +346,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/ekk-lm3s9b96/nsh/defconfig b/configs/ekk-lm3s9b96/nsh/defconfig index d86a37e544..9ab7bb5842 100644 --- a/configs/ekk-lm3s9b96/nsh/defconfig +++ b/configs/ekk-lm3s9b96/nsh/defconfig @@ -335,7 +335,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/fire-stm32v2/nsh/defconfig b/configs/fire-stm32v2/nsh/defconfig index 24645154e4..12ea15117c 100644 --- a/configs/fire-stm32v2/nsh/defconfig +++ b/configs/fire-stm32v2/nsh/defconfig @@ -602,7 +602,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/freedom-k64f/netnsh/defconfig b/configs/freedom-k64f/netnsh/defconfig index 395bdd882f..7a174609d4 100644 --- a/configs/freedom-k64f/netnsh/defconfig +++ b/configs/freedom-k64f/netnsh/defconfig @@ -345,7 +345,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/freedom-k64f/nsh/defconfig b/configs/freedom-k64f/nsh/defconfig index b2d1ba0fef..1a570c533f 100644 --- a/configs/freedom-k64f/nsh/defconfig +++ b/configs/freedom-k64f/nsh/defconfig @@ -335,7 +335,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/freedom-kl25z/nsh/defconfig b/configs/freedom-kl25z/nsh/defconfig index d87eabd5f8..25a5f7e7e9 100644 --- a/configs/freedom-kl25z/nsh/defconfig +++ b/configs/freedom-kl25z/nsh/defconfig @@ -267,7 +267,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/freedom-kl26z/nsh/defconfig b/configs/freedom-kl26z/nsh/defconfig index 16db1d5744..cfd523f6c2 100644 --- a/configs/freedom-kl26z/nsh/defconfig +++ b/configs/freedom-kl26z/nsh/defconfig @@ -267,7 +267,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/hymini-stm32v/nsh/defconfig b/configs/hymini-stm32v/nsh/defconfig index 385782572c..6b5e138135 100644 --- a/configs/hymini-stm32v/nsh/defconfig +++ b/configs/hymini-stm32v/nsh/defconfig @@ -553,7 +553,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/hymini-stm32v/nsh2/defconfig b/configs/hymini-stm32v/nsh2/defconfig index eaf473107d..32def3b8bf 100644 --- a/configs/hymini-stm32v/nsh2/defconfig +++ b/configs/hymini-stm32v/nsh2/defconfig @@ -580,7 +580,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARDCTL_TSCTEST=y -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/hymini-stm32v/usbmsc/defconfig b/configs/hymini-stm32v/usbmsc/defconfig index dc189f23c5..b85dca84bc 100644 --- a/configs/hymini-stm32v/usbmsc/defconfig +++ b/configs/hymini-stm32v/usbmsc/defconfig @@ -558,7 +558,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/hymini-stm32v/usbnsh/defconfig b/configs/hymini-stm32v/usbnsh/defconfig index 1dab64fb6d..a806aa165c 100644 --- a/configs/hymini-stm32v/usbnsh/defconfig +++ b/configs/hymini-stm32v/usbnsh/defconfig @@ -555,7 +555,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/hymini-stm32v/usbserial/defconfig b/configs/hymini-stm32v/usbserial/defconfig index 0d62c0ed93..e8e85f2933 100644 --- a/configs/hymini-stm32v/usbserial/defconfig +++ b/configs/hymini-stm32v/usbserial/defconfig @@ -549,7 +549,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/launchxl-tms57004/nsh/defconfig b/configs/launchxl-tms57004/nsh/defconfig index 7329956077..c10cf4fdf6 100644 --- a/configs/launchxl-tms57004/nsh/defconfig +++ b/configs/launchxl-tms57004/nsh/defconfig @@ -253,7 +253,6 @@ CONFIG_NSH_MMCSDMINOR=0 CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lincoln60/netnsh/defconfig b/configs/lincoln60/netnsh/defconfig index 0a43f6d84d..4a351f8fba 100644 --- a/configs/lincoln60/netnsh/defconfig +++ b/configs/lincoln60/netnsh/defconfig @@ -324,7 +324,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lincoln60/nsh/defconfig b/configs/lincoln60/nsh/defconfig index 4a1ab48f51..9dbec58c1d 100644 --- a/configs/lincoln60/nsh/defconfig +++ b/configs/lincoln60/nsh/defconfig @@ -301,7 +301,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lm3s6432-s2e/nsh/defconfig b/configs/lm3s6432-s2e/nsh/defconfig index becaa42d18..afd5629832 100644 --- a/configs/lm3s6432-s2e/nsh/defconfig +++ b/configs/lm3s6432-s2e/nsh/defconfig @@ -330,7 +330,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lm3s6965-ek/discover/defconfig b/configs/lm3s6965-ek/discover/defconfig index f087bbee8e..defeaed79c 100644 --- a/configs/lm3s6965-ek/discover/defconfig +++ b/configs/lm3s6965-ek/discover/defconfig @@ -340,7 +340,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lm3s6965-ek/nsh/defconfig b/configs/lm3s6965-ek/nsh/defconfig index f087bbee8e..defeaed79c 100644 --- a/configs/lm3s6965-ek/nsh/defconfig +++ b/configs/lm3s6965-ek/nsh/defconfig @@ -340,7 +340,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lm3s6965-ek/nx/defconfig b/configs/lm3s6965-ek/nx/defconfig index ee5110cf2d..0350c0ac98 100644 --- a/configs/lm3s6965-ek/nx/defconfig +++ b/configs/lm3s6965-ek/nx/defconfig @@ -325,7 +325,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set CONFIG_BOARDCTL_GRAPHICS=y # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lm3s8962-ek/nsh/defconfig b/configs/lm3s8962-ek/nsh/defconfig index 823b410d3e..49acf3dc8c 100644 --- a/configs/lm3s8962-ek/nsh/defconfig +++ b/configs/lm3s8962-ek/nsh/defconfig @@ -350,7 +350,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lm3s8962-ek/nx/defconfig b/configs/lm3s8962-ek/nx/defconfig index afef4c8ca8..4506f553cb 100644 --- a/configs/lm3s8962-ek/nx/defconfig +++ b/configs/lm3s8962-ek/nx/defconfig @@ -335,7 +335,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set CONFIG_BOARDCTL_GRAPHICS=y # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lpc4330-xplorer/nsh/defconfig b/configs/lpc4330-xplorer/nsh/defconfig index 390ab0fa33..dd91ed8a78 100644 --- a/configs/lpc4330-xplorer/nsh/defconfig +++ b/configs/lpc4330-xplorer/nsh/defconfig @@ -317,7 +317,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lpc4337-ws/nsh/defconfig b/configs/lpc4337-ws/nsh/defconfig index b73f0527bc..31c1ac48fe 100644 --- a/configs/lpc4337-ws/nsh/defconfig +++ b/configs/lpc4337-ws/nsh/defconfig @@ -315,7 +315,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -CONFIG_BOARDCTL_ADCTEST=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lpc4357-evb/nsh/defconfig b/configs/lpc4357-evb/nsh/defconfig index c01d703bea..7b59831c7b 100644 --- a/configs/lpc4357-evb/nsh/defconfig +++ b/configs/lpc4357-evb/nsh/defconfig @@ -309,7 +309,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lpc4370-link2/nsh/defconfig b/configs/lpc4370-link2/nsh/defconfig index b4a36288a1..a740815531 100644 --- a/configs/lpc4370-link2/nsh/defconfig +++ b/configs/lpc4370-link2/nsh/defconfig @@ -317,7 +317,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lpcxpresso-lpc1768/nsh/defconfig b/configs/lpcxpresso-lpc1768/nsh/defconfig index 11d4e02757..6a6c05e5de 100644 --- a/configs/lpcxpresso-lpc1768/nsh/defconfig +++ b/configs/lpcxpresso-lpc1768/nsh/defconfig @@ -316,7 +316,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lpcxpresso-lpc1768/nx/defconfig b/configs/lpcxpresso-lpc1768/nx/defconfig index 4ac3ebe809..7085ccd02b 100644 --- a/configs/lpcxpresso-lpc1768/nx/defconfig +++ b/configs/lpcxpresso-lpc1768/nx/defconfig @@ -304,7 +304,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set CONFIG_BOARDCTL_GRAPHICS=y # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/lpcxpresso-lpc1768/usbmsc/defconfig b/configs/lpcxpresso-lpc1768/usbmsc/defconfig index 21eac4b620..d02c4d951a 100644 --- a/configs/lpcxpresso-lpc1768/usbmsc/defconfig +++ b/configs/lpcxpresso-lpc1768/usbmsc/defconfig @@ -312,7 +312,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/maple/nx/defconfig b/configs/maple/nx/defconfig index dcf5d4aded..3e75539627 100644 --- a/configs/maple/nx/defconfig +++ b/configs/maple/nx/defconfig @@ -578,7 +578,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/maple/usbnsh/defconfig b/configs/maple/usbnsh/defconfig index 8a6bca9ea7..6976bf0eaa 100644 --- a/configs/maple/usbnsh/defconfig +++ b/configs/maple/usbnsh/defconfig @@ -544,7 +544,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mbed/nsh/defconfig b/configs/mbed/nsh/defconfig index 6c0cd29980..257ca1a75c 100644 --- a/configs/mbed/nsh/defconfig +++ b/configs/mbed/nsh/defconfig @@ -304,7 +304,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mcu123-lpc214x/composite/defconfig b/configs/mcu123-lpc214x/composite/defconfig index 0073cceaf9..defee1ad92 100644 --- a/configs/mcu123-lpc214x/composite/defconfig +++ b/configs/mcu123-lpc214x/composite/defconfig @@ -249,7 +249,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mcu123-lpc214x/nsh/defconfig b/configs/mcu123-lpc214x/nsh/defconfig index 51e5c8b2fc..ed35e28cf9 100644 --- a/configs/mcu123-lpc214x/nsh/defconfig +++ b/configs/mcu123-lpc214x/nsh/defconfig @@ -242,7 +242,6 @@ CONFIG_NSH_MMCSDSPIPORTNO=1 CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mcu123-lpc214x/usbmsc/defconfig b/configs/mcu123-lpc214x/usbmsc/defconfig index 78b27e5c5a..df52fa03bd 100644 --- a/configs/mcu123-lpc214x/usbmsc/defconfig +++ b/configs/mcu123-lpc214x/usbmsc/defconfig @@ -249,7 +249,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mcu123-lpc214x/usbserial/defconfig b/configs/mcu123-lpc214x/usbserial/defconfig index a8174a6940..100d87fe95 100644 --- a/configs/mcu123-lpc214x/usbserial/defconfig +++ b/configs/mcu123-lpc214x/usbserial/defconfig @@ -248,7 +248,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mikroe-stm32f4/fulldemo/defconfig b/configs/mikroe-stm32f4/fulldemo/defconfig index 9056cf58cd..13ff114588 100644 --- a/configs/mikroe-stm32f4/fulldemo/defconfig +++ b/configs/mikroe-stm32f4/fulldemo/defconfig @@ -603,7 +603,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARDCTL_TSCTEST=y -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mikroe-stm32f4/kostest/defconfig b/configs/mikroe-stm32f4/kostest/defconfig index 1eba3c8fc0..629d012add 100644 --- a/configs/mikroe-stm32f4/kostest/defconfig +++ b/configs/mikroe-stm32f4/kostest/defconfig @@ -596,7 +596,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mikroe-stm32f4/nsh/defconfig b/configs/mikroe-stm32f4/nsh/defconfig index 84b304c3bc..9291880ddf 100644 --- a/configs/mikroe-stm32f4/nsh/defconfig +++ b/configs/mikroe-stm32f4/nsh/defconfig @@ -577,7 +577,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mikroe-stm32f4/nx/defconfig b/configs/mikroe-stm32f4/nx/defconfig index 65e350b4b2..478c440e14 100644 --- a/configs/mikroe-stm32f4/nx/defconfig +++ b/configs/mikroe-stm32f4/nx/defconfig @@ -554,7 +554,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mikroe-stm32f4/nxlines/defconfig b/configs/mikroe-stm32f4/nxlines/defconfig index c997db7e16..67088d6ac0 100644 --- a/configs/mikroe-stm32f4/nxlines/defconfig +++ b/configs/mikroe-stm32f4/nxlines/defconfig @@ -545,7 +545,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mikroe-stm32f4/nxtext/defconfig b/configs/mikroe-stm32f4/nxtext/defconfig index f81464664c..f6f131b972 100644 --- a/configs/mikroe-stm32f4/nxtext/defconfig +++ b/configs/mikroe-stm32f4/nxtext/defconfig @@ -554,7 +554,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mikroe-stm32f4/usbnsh/defconfig b/configs/mikroe-stm32f4/usbnsh/defconfig index c462790ac5..45102afa4a 100644 --- a/configs/mikroe-stm32f4/usbnsh/defconfig +++ b/configs/mikroe-stm32f4/usbnsh/defconfig @@ -580,7 +580,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/mirtoo/nxffs/defconfig b/configs/mirtoo/nxffs/defconfig index ee4e547d14..6dbc62ca2b 100644 --- a/configs/mirtoo/nxffs/defconfig +++ b/configs/mirtoo/nxffs/defconfig @@ -341,7 +341,6 @@ CONFIG_MIRTOO_RELEASE=2 CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/moxa/nsh/defconfig b/configs/moxa/nsh/defconfig index b7dbca0b39..d1cdfc6b40 100644 --- a/configs/moxa/nsh/defconfig +++ b/configs/moxa/nsh/defconfig @@ -217,7 +217,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_RESET=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/nr5m100-nexys4/nsh/defconfig b/configs/nr5m100-nexys4/nsh/defconfig index 37ab198610..eacb815a02 100644 --- a/configs/nr5m100-nexys4/nsh/defconfig +++ b/configs/nr5m100-nexys4/nsh/defconfig @@ -179,7 +179,6 @@ CONFIG_ARCH_BOARD="nr5m100-nexys4" CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/nucleo-144/f746-evalos/defconfig b/configs/nucleo-144/f746-evalos/defconfig index bc6229886d..e3ab70c260 100644 --- a/configs/nucleo-144/f746-evalos/defconfig +++ b/configs/nucleo-144/f746-evalos/defconfig @@ -440,7 +440,6 @@ CONFIG_NUCLEO_CONSOLE_VIRTUAL=y CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/nucleo-144/f767-evalos/defconfig b/configs/nucleo-144/f767-evalos/defconfig index ef3426fdd8..1a9d88032e 100644 --- a/configs/nucleo-144/f767-evalos/defconfig +++ b/configs/nucleo-144/f767-evalos/defconfig @@ -444,7 +444,6 @@ CONFIG_NUCLEO_CONSOLE_VIRTUAL=y CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/nucleo-f303re/adc/defconfig b/configs/nucleo-f303re/adc/defconfig index d742cb5190..c78821676c 100644 --- a/configs/nucleo-f303re/adc/defconfig +++ b/configs/nucleo-f303re/adc/defconfig @@ -542,7 +542,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -CONFIG_BOARDCTL_ADCTEST=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/nucleo-f303re/can/defconfig b/configs/nucleo-f303re/can/defconfig index ce3f030450..baaf7ac37a 100644 --- a/configs/nucleo-f303re/can/defconfig +++ b/configs/nucleo-f303re/can/defconfig @@ -545,7 +545,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set CONFIG_BOARDCTL_CANINIT=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/nucleo-f303re/nxlines/defconfig b/configs/nucleo-f303re/nxlines/defconfig index 20a48e3d14..ff310f5237 100644 --- a/configs/nucleo-f303re/nxlines/defconfig +++ b/configs/nucleo-f303re/nxlines/defconfig @@ -544,7 +544,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_CANINIT is not set CONFIG_BOARDCTL_GRAPHICS=y # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/nucleo-f303re/pwm/defconfig b/configs/nucleo-f303re/pwm/defconfig index 5d5ea72956..df69cdde82 100644 --- a/configs/nucleo-f303re/pwm/defconfig +++ b/configs/nucleo-f303re/pwm/defconfig @@ -546,7 +546,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/nucleo-f303re/serialrx/defconfig b/configs/nucleo-f303re/serialrx/defconfig index afdb02265c..894a6bcc59 100644 --- a/configs/nucleo-f303re/serialrx/defconfig +++ b/configs/nucleo-f303re/serialrx/defconfig @@ -549,7 +549,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -CONFIG_BOARDCTL_ADCTEST=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/nucleo-l476rg/nsh/defconfig b/configs/nucleo-l476rg/nsh/defconfig index 5e478f2e2a..730c7bb3a1 100644 --- a/configs/nucleo-l476rg/nsh/defconfig +++ b/configs/nucleo-l476rg/nsh/defconfig @@ -369,7 +369,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-lpc-h3131/nsh/defconfig b/configs/olimex-lpc-h3131/nsh/defconfig index 1ac70acd6c..816136a679 100644 --- a/configs/olimex-lpc-h3131/nsh/defconfig +++ b/configs/olimex-lpc-h3131/nsh/defconfig @@ -255,7 +255,6 @@ CONFIG_NSH_MMCSDMINOR=0 CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-lpc1766stk/ftpc/defconfig b/configs/olimex-lpc1766stk/ftpc/defconfig index e812a9f414..37340b18dd 100644 --- a/configs/olimex-lpc1766stk/ftpc/defconfig +++ b/configs/olimex-lpc1766stk/ftpc/defconfig @@ -316,7 +316,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-lpc1766stk/hidmouse/defconfig b/configs/olimex-lpc1766stk/hidmouse/defconfig index 99c9c14799..7deaf52065 100644 --- a/configs/olimex-lpc1766stk/hidmouse/defconfig +++ b/configs/olimex-lpc1766stk/hidmouse/defconfig @@ -328,7 +328,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-lpc1766stk/nsh/defconfig b/configs/olimex-lpc1766stk/nsh/defconfig index c71430bf84..a391c8b8b6 100644 --- a/configs/olimex-lpc1766stk/nsh/defconfig +++ b/configs/olimex-lpc1766stk/nsh/defconfig @@ -317,7 +317,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-lpc1766stk/nx/defconfig b/configs/olimex-lpc1766stk/nx/defconfig index 3a547904fc..5bfc733710 100644 --- a/configs/olimex-lpc1766stk/nx/defconfig +++ b/configs/olimex-lpc1766stk/nx/defconfig @@ -313,7 +313,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set CONFIG_BOARDCTL_GRAPHICS=y # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-lpc1766stk/usbmsc/defconfig b/configs/olimex-lpc1766stk/usbmsc/defconfig index ffaf78d6c7..ac9781cd82 100644 --- a/configs/olimex-lpc1766stk/usbmsc/defconfig +++ b/configs/olimex-lpc1766stk/usbmsc/defconfig @@ -313,7 +313,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-lpc1766stk/usbserial/defconfig b/configs/olimex-lpc1766stk/usbserial/defconfig index 6e06b1be4c..6ae2279fee 100644 --- a/configs/olimex-lpc1766stk/usbserial/defconfig +++ b/configs/olimex-lpc1766stk/usbserial/defconfig @@ -313,7 +313,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-lpc1766stk/zmodem/defconfig b/configs/olimex-lpc1766stk/zmodem/defconfig index e7a6ae7dd8..88aa69be37 100644 --- a/configs/olimex-lpc1766stk/zmodem/defconfig +++ b/configs/olimex-lpc1766stk/zmodem/defconfig @@ -318,7 +318,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-stm32-e407/usbnsh/defconfig b/configs/olimex-stm32-e407/usbnsh/defconfig index 7b8d7235a6..a0a4084076 100644 --- a/configs/olimex-stm32-e407/usbnsh/defconfig +++ b/configs/olimex-stm32-e407/usbnsh/defconfig @@ -572,7 +572,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-stm32-h405/usbnsh/defconfig b/configs/olimex-stm32-h405/usbnsh/defconfig index 228c5da542..5c90c54a77 100644 --- a/configs/olimex-stm32-h405/usbnsh/defconfig +++ b/configs/olimex-stm32-h405/usbnsh/defconfig @@ -600,7 +600,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -CONFIG_BOARDCTL_ADCTEST=y CONFIG_BOARDCTL_CANINIT=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-stm32-p207/nsh/defconfig b/configs/olimex-stm32-p207/nsh/defconfig index 12540090d2..702a3fa491 100644 --- a/configs/olimex-stm32-p207/nsh/defconfig +++ b/configs/olimex-stm32-p207/nsh/defconfig @@ -626,7 +626,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -CONFIG_BOARDCTL_ADCTEST=y # CONFIG_BOARDCTL_CANINIT is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-strp711/nsh/defconfig b/configs/olimex-strp711/nsh/defconfig index 85142cbcd5..aed99049aa 100644 --- a/configs/olimex-strp711/nsh/defconfig +++ b/configs/olimex-strp711/nsh/defconfig @@ -252,7 +252,6 @@ CONFIG_NSH_MMCSDSPIPORTNO=1 CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimexino-stm32/can/defconfig b/configs/olimexino-stm32/can/defconfig index 5217a05048..a0c85f35fa 100644 --- a/configs/olimexino-stm32/can/defconfig +++ b/configs/olimexino-stm32/can/defconfig @@ -588,7 +588,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set CONFIG_BOARDCTL_CANINIT=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimexino-stm32/composite/defconfig b/configs/olimexino-stm32/composite/defconfig index fea02cc27e..7dc2e5a48b 100644 --- a/configs/olimexino-stm32/composite/defconfig +++ b/configs/olimexino-stm32/composite/defconfig @@ -597,7 +597,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimexino-stm32/nsh/defconfig b/configs/olimexino-stm32/nsh/defconfig index 1d5511ef13..fe7b38e685 100644 --- a/configs/olimexino-stm32/nsh/defconfig +++ b/configs/olimexino-stm32/nsh/defconfig @@ -596,7 +596,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimexino-stm32/smallnsh/defconfig b/configs/olimexino-stm32/smallnsh/defconfig index 4eb59f7f21..2358425336 100644 --- a/configs/olimexino-stm32/smallnsh/defconfig +++ b/configs/olimexino-stm32/smallnsh/defconfig @@ -569,7 +569,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set CONFIG_BOARDCTL_CANINIT=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimexino-stm32/tiny/defconfig b/configs/olimexino-stm32/tiny/defconfig index e84c5f9ce1..0f20a157a3 100644 --- a/configs/olimexino-stm32/tiny/defconfig +++ b/configs/olimexino-stm32/tiny/defconfig @@ -569,7 +569,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set CONFIG_BOARDCTL_CANINIT=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/open1788/nsh/defconfig b/configs/open1788/nsh/defconfig index b65783f70e..8ed16d5c5e 100644 --- a/configs/open1788/nsh/defconfig +++ b/configs/open1788/nsh/defconfig @@ -313,7 +313,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/pic32mx-starterkit/nsh/defconfig b/configs/pic32mx-starterkit/nsh/defconfig index 9376fb2143..7281f362e7 100644 --- a/configs/pic32mx-starterkit/nsh/defconfig +++ b/configs/pic32mx-starterkit/nsh/defconfig @@ -335,7 +335,6 @@ CONFIG_ARCH_LEDS=y CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/pic32mx-starterkit/nsh2/defconfig b/configs/pic32mx-starterkit/nsh2/defconfig index 2af0e68d5a..c28f915d1c 100644 --- a/configs/pic32mx-starterkit/nsh2/defconfig +++ b/configs/pic32mx-starterkit/nsh2/defconfig @@ -347,7 +347,6 @@ CONFIG_ARCH_LEDS=y CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/pic32mx7mmb/nsh/defconfig b/configs/pic32mx7mmb/nsh/defconfig index b13b33cf70..75ff18d6d0 100644 --- a/configs/pic32mx7mmb/nsh/defconfig +++ b/configs/pic32mx7mmb/nsh/defconfig @@ -356,7 +356,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/pic32mz-starterkit/nsh/defconfig b/configs/pic32mz-starterkit/nsh/defconfig index 45e55691e9..9368fa716d 100644 --- a/configs/pic32mz-starterkit/nsh/defconfig +++ b/configs/pic32mz-starterkit/nsh/defconfig @@ -262,7 +262,6 @@ CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/pirelli_dpl10/nsh_highram/defconfig b/configs/pirelli_dpl10/nsh_highram/defconfig index 8c214d338b..e03349f8ee 100644 --- a/configs/pirelli_dpl10/nsh_highram/defconfig +++ b/configs/pirelli_dpl10/nsh_highram/defconfig @@ -241,7 +241,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_POWEROFF=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sabre-6quad/nsh/defconfig b/configs/sabre-6quad/nsh/defconfig index 180a7f37eb..51c987752a 100644 --- a/configs/sabre-6quad/nsh/defconfig +++ b/configs/sabre-6quad/nsh/defconfig @@ -270,7 +270,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sabre-6quad/smp/defconfig b/configs/sabre-6quad/smp/defconfig index ae16b4ce48..7bd54f8c70 100644 --- a/configs/sabre-6quad/smp/defconfig +++ b/configs/sabre-6quad/smp/defconfig @@ -273,7 +273,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sam3u-ek/nsh/defconfig b/configs/sam3u-ek/nsh/defconfig index 0e6ca642f1..4607e053cc 100644 --- a/configs/sam3u-ek/nsh/defconfig +++ b/configs/sam3u-ek/nsh/defconfig @@ -335,7 +335,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sam3u-ek/nxwm/defconfig b/configs/sam3u-ek/nxwm/defconfig index 29a8b18aa7..5358c385b2 100644 --- a/configs/sam3u-ek/nxwm/defconfig +++ b/configs/sam3u-ek/nxwm/defconfig @@ -345,7 +345,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sam4cmp-db/nsh/defconfig b/configs/sam4cmp-db/nsh/defconfig index 80453ba350..6eb1691432 100644 --- a/configs/sam4cmp-db/nsh/defconfig +++ b/configs/sam4cmp-db/nsh/defconfig @@ -345,7 +345,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sam4e-ek/nsh/defconfig b/configs/sam4e-ek/nsh/defconfig index 13422342f2..ea0145d431 100644 --- a/configs/sam4e-ek/nsh/defconfig +++ b/configs/sam4e-ek/nsh/defconfig @@ -383,7 +383,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sam4e-ek/nxwm/defconfig b/configs/sam4e-ek/nxwm/defconfig index 126da5cc7e..7f1d48a118 100644 --- a/configs/sam4e-ek/nxwm/defconfig +++ b/configs/sam4e-ek/nxwm/defconfig @@ -395,7 +395,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sam4e-ek/usbnsh/defconfig b/configs/sam4e-ek/usbnsh/defconfig index 1ebbd2b786..095a827bda 100644 --- a/configs/sam4e-ek/usbnsh/defconfig +++ b/configs/sam4e-ek/usbnsh/defconfig @@ -389,7 +389,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sam4s-xplained-pro/nsh/defconfig b/configs/sam4s-xplained-pro/nsh/defconfig index 231a7fcc1d..a77d893167 100644 --- a/configs/sam4s-xplained-pro/nsh/defconfig +++ b/configs/sam4s-xplained-pro/nsh/defconfig @@ -377,7 +377,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sama5d2-xult/nsh/defconfig b/configs/sama5d2-xult/nsh/defconfig index dc1ba8e882..c524993839 100644 --- a/configs/sama5d2-xult/nsh/defconfig +++ b/configs/sama5d2-xult/nsh/defconfig @@ -406,7 +406,6 @@ CONFIG_SAMA5D2XULT_528MHZ=y CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sama5d3x-ek/demo/defconfig b/configs/sama5d3x-ek/demo/defconfig index 48c33331d2..521ace3b80 100644 --- a/configs/sama5d3x-ek/demo/defconfig +++ b/configs/sama5d3x-ek/demo/defconfig @@ -434,7 +434,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sama5d3x-ek/nxplayer/defconfig b/configs/sama5d3x-ek/nxplayer/defconfig index 8059a6a420..6d6dfc0d15 100644 --- a/configs/sama5d3x-ek/nxplayer/defconfig +++ b/configs/sama5d3x-ek/nxplayer/defconfig @@ -431,7 +431,6 @@ CONFIG_SAMA5D3xEK_WM8904_SRCMAIN=y CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sama5d3x-ek/nxwm/defconfig b/configs/sama5d3x-ek/nxwm/defconfig index d6264e5b5b..016756b5c6 100644 --- a/configs/sama5d3x-ek/nxwm/defconfig +++ b/configs/sama5d3x-ek/nxwm/defconfig @@ -447,7 +447,6 @@ CONFIG_SAMA5D3xEK_TSD_DEVMINOR=0 CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sama5d4-ek/ipv6/defconfig b/configs/sama5d4-ek/ipv6/defconfig index 9c62baddfe..a4488a7647 100644 --- a/configs/sama5d4-ek/ipv6/defconfig +++ b/configs/sama5d4-ek/ipv6/defconfig @@ -525,7 +525,6 @@ CONFIG_SAMA5D4EK_WM8904_SRCMAIN=y CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sama5d4-ek/nsh/defconfig b/configs/sama5d4-ek/nsh/defconfig index 01a6e3e281..dff96a156d 100644 --- a/configs/sama5d4-ek/nsh/defconfig +++ b/configs/sama5d4-ek/nsh/defconfig @@ -525,7 +525,6 @@ CONFIG_SAMA5D4EK_WM8904_SRCMAIN=y CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sama5d4-ek/nxwm/defconfig b/configs/sama5d4-ek/nxwm/defconfig index d5394ad53c..e890dab1a6 100644 --- a/configs/sama5d4-ek/nxwm/defconfig +++ b/configs/sama5d4-ek/nxwm/defconfig @@ -496,7 +496,6 @@ CONFIG_SAMA5D4EK_MXT_DEVMINOR=0 CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/same70-xplained/netnsh/defconfig b/configs/same70-xplained/netnsh/defconfig index 4eb2335b58..d46655853d 100644 --- a/configs/same70-xplained/netnsh/defconfig +++ b/configs/same70-xplained/netnsh/defconfig @@ -399,7 +399,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/same70-xplained/nsh/defconfig b/configs/same70-xplained/nsh/defconfig index c78142a8ba..8f45a3dba3 100644 --- a/configs/same70-xplained/nsh/defconfig +++ b/configs/same70-xplained/nsh/defconfig @@ -384,7 +384,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/samv71-xult/knsh/defconfig b/configs/samv71-xult/knsh/defconfig index 20879e5a1b..400e510fb0 100644 --- a/configs/samv71-xult/knsh/defconfig +++ b/configs/samv71-xult/knsh/defconfig @@ -388,7 +388,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/samv71-xult/module/defconfig b/configs/samv71-xult/module/defconfig index ddb8fd288c..f7457269df 100644 --- a/configs/samv71-xult/module/defconfig +++ b/configs/samv71-xult/module/defconfig @@ -362,7 +362,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_OS_SYMTAB=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/samv71-xult/mxtxplnd/defconfig b/configs/samv71-xult/mxtxplnd/defconfig index 70f1b6f86d..4bdce00af1 100644 --- a/configs/samv71-xult/mxtxplnd/defconfig +++ b/configs/samv71-xult/mxtxplnd/defconfig @@ -385,7 +385,6 @@ CONFIG_SAMV71XULT_LCD_BGCOLOR=0x00 CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/samv71-xult/netnsh/defconfig b/configs/samv71-xult/netnsh/defconfig index 8a9a66faa1..e200f8f883 100644 --- a/configs/samv71-xult/netnsh/defconfig +++ b/configs/samv71-xult/netnsh/defconfig @@ -402,7 +402,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/samv71-xult/nsh/defconfig b/configs/samv71-xult/nsh/defconfig index 89602972f2..43cb4ab172 100644 --- a/configs/samv71-xult/nsh/defconfig +++ b/configs/samv71-xult/nsh/defconfig @@ -387,7 +387,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/samv71-xult/nxwm/defconfig b/configs/samv71-xult/nxwm/defconfig index 7dc80e5ec5..7af475dfee 100644 --- a/configs/samv71-xult/nxwm/defconfig +++ b/configs/samv71-xult/nxwm/defconfig @@ -385,7 +385,6 @@ CONFIG_SAMV71XULT_LCD_BGCOLOR=0x95fa CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/samv71-xult/vnc/defconfig b/configs/samv71-xult/vnc/defconfig index 7e13d37a37..762455ee66 100644 --- a/configs/samv71-xult/vnc/defconfig +++ b/configs/samv71-xult/vnc/defconfig @@ -401,7 +401,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/samv71-xult/vnxwm/defconfig b/configs/samv71-xult/vnxwm/defconfig index 1e51ed10e8..3efe65fb47 100644 --- a/configs/samv71-xult/vnxwm/defconfig +++ b/configs/samv71-xult/vnxwm/defconfig @@ -401,7 +401,6 @@ CONFIG_ARCH_IRQBUTTONS=y CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/shenzhou/nsh/defconfig b/configs/shenzhou/nsh/defconfig index ad941f6951..d41b177dfd 100644 --- a/configs/shenzhou/nsh/defconfig +++ b/configs/shenzhou/nsh/defconfig @@ -585,7 +585,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/shenzhou/nxwm/defconfig b/configs/shenzhou/nxwm/defconfig index 4d41e08c5a..be72bc7d18 100644 --- a/configs/shenzhou/nxwm/defconfig +++ b/configs/shenzhou/nxwm/defconfig @@ -606,7 +606,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/shenzhou/thttpd/defconfig b/configs/shenzhou/thttpd/defconfig index a21ff7816d..f35fe1526a 100644 --- a/configs/shenzhou/thttpd/defconfig +++ b/configs/shenzhou/thttpd/defconfig @@ -586,7 +586,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sim/bas/defconfig b/configs/sim/bas/defconfig index 70a460b8f6..9b11ad5947 100644 --- a/configs/sim/bas/defconfig +++ b/configs/sim/bas/defconfig @@ -147,7 +147,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_APP_SYMTAB is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sim/minibasic/defconfig b/configs/sim/minibasic/defconfig index 196c22194a..b7a6e11eae 100644 --- a/configs/sim/minibasic/defconfig +++ b/configs/sim/minibasic/defconfig @@ -179,7 +179,6 @@ CONFIG_BOARDCTL_POWEROFF=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_APP_SYMTAB is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sim/nsh/defconfig b/configs/sim/nsh/defconfig index 7c82a8b10d..b7b881c136 100644 --- a/configs/sim/nsh/defconfig +++ b/configs/sim/nsh/defconfig @@ -156,7 +156,6 @@ CONFIG_BOARDCTL_POWEROFF=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_APP_SYMTAB is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sim/nsh2/defconfig b/configs/sim/nsh2/defconfig index 048787bdfd..320355597b 100644 --- a/configs/sim/nsh2/defconfig +++ b/configs/sim/nsh2/defconfig @@ -165,7 +165,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_POWEROFF is not set # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sim/nxlines/defconfig b/configs/sim/nxlines/defconfig index 42d05ee1bc..9b82cf3586 100644 --- a/configs/sim/nxlines/defconfig +++ b/configs/sim/nxlines/defconfig @@ -156,7 +156,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_POWEROFF is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sim/nxwm/defconfig b/configs/sim/nxwm/defconfig index cf5b55d2d9..ab478684c3 100644 --- a/configs/sim/nxwm/defconfig +++ b/configs/sim/nxwm/defconfig @@ -160,7 +160,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_POWEROFF is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sim/touchscreen/defconfig b/configs/sim/touchscreen/defconfig index 3bbf0c93a0..e5427ff736 100644 --- a/configs/sim/touchscreen/defconfig +++ b/configs/sim/touchscreen/defconfig @@ -161,7 +161,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_POWEROFF is not set # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sim/udgram/defconfig b/configs/sim/udgram/defconfig index 215e1354f4..6a41938192 100644 --- a/configs/sim/udgram/defconfig +++ b/configs/sim/udgram/defconfig @@ -156,7 +156,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_APP_SYMTAB is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sim/unionfs/defconfig b/configs/sim/unionfs/defconfig index 9d522a9931..77da0ebc32 100644 --- a/configs/sim/unionfs/defconfig +++ b/configs/sim/unionfs/defconfig @@ -147,7 +147,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_APP_SYMTAB is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sim/ustream/defconfig b/configs/sim/ustream/defconfig index 87262350af..b61d8b04a7 100644 --- a/configs/sim/ustream/defconfig +++ b/configs/sim/ustream/defconfig @@ -156,7 +156,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_APP_SYMTAB is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/spark/composite/defconfig b/configs/spark/composite/defconfig index 55af6e92a4..80fc026185 100644 --- a/configs/spark/composite/defconfig +++ b/configs/spark/composite/defconfig @@ -557,7 +557,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/spark/nsh/defconfig b/configs/spark/nsh/defconfig index 2a12c9e1bd..8c480ed1de 100644 --- a/configs/spark/nsh/defconfig +++ b/configs/spark/nsh/defconfig @@ -557,7 +557,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_USBDEVCTRL is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/spark/usbmsc/defconfig b/configs/spark/usbmsc/defconfig index 5627cee07c..524811c2b9 100644 --- a/configs/spark/usbmsc/defconfig +++ b/configs/spark/usbmsc/defconfig @@ -557,7 +557,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/spark/usbnsh/defconfig b/configs/spark/usbnsh/defconfig index 9c91f06d90..4f0f81059b 100644 --- a/configs/spark/usbnsh/defconfig +++ b/configs/spark/usbnsh/defconfig @@ -556,7 +556,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/spark/usbserial/defconfig b/configs/spark/usbserial/defconfig index 984b82f7d2..dcd7afa1d2 100644 --- a/configs/spark/usbserial/defconfig +++ b/configs/spark/usbserial/defconfig @@ -557,7 +557,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3210e-eval/composite/defconfig b/configs/stm3210e-eval/composite/defconfig index a7c0e15a10..f15376d1b6 100644 --- a/configs/stm3210e-eval/composite/defconfig +++ b/configs/stm3210e-eval/composite/defconfig @@ -579,7 +579,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3210e-eval/nsh/defconfig b/configs/stm3210e-eval/nsh/defconfig index 31903c4a4d..64a89edb98 100644 --- a/configs/stm3210e-eval/nsh/defconfig +++ b/configs/stm3210e-eval/nsh/defconfig @@ -580,7 +580,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_USBDEVCTRL is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3210e-eval/nsh2/defconfig b/configs/stm3210e-eval/nsh2/defconfig index 95774fa875..ebe9ca441f 100644 --- a/configs/stm3210e-eval/nsh2/defconfig +++ b/configs/stm3210e-eval/nsh2/defconfig @@ -596,7 +596,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3210e-eval/nxterm/defconfig b/configs/stm3210e-eval/nxterm/defconfig index c10aeef17b..f1c58151c7 100644 --- a/configs/stm3210e-eval/nxterm/defconfig +++ b/configs/stm3210e-eval/nxterm/defconfig @@ -576,7 +576,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3210e-eval/pm/defconfig b/configs/stm3210e-eval/pm/defconfig index 12758dc6c7..57fc099163 100644 --- a/configs/stm3210e-eval/pm/defconfig +++ b/configs/stm3210e-eval/pm/defconfig @@ -596,7 +596,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3210e-eval/usbmsc/defconfig b/configs/stm3210e-eval/usbmsc/defconfig index a85a51a2aa..78e0771998 100644 --- a/configs/stm3210e-eval/usbmsc/defconfig +++ b/configs/stm3210e-eval/usbmsc/defconfig @@ -572,7 +572,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3210e-eval/usbserial/defconfig b/configs/stm3210e-eval/usbserial/defconfig index 5dcbcb817e..b7ca54b7c7 100644 --- a/configs/stm3210e-eval/usbserial/defconfig +++ b/configs/stm3210e-eval/usbserial/defconfig @@ -564,7 +564,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3220g-eval/nsh2/defconfig b/configs/stm3220g-eval/nsh2/defconfig index e2c14711b9..b7bbf116fc 100644 --- a/configs/stm3220g-eval/nsh2/defconfig +++ b/configs/stm3220g-eval/nsh2/defconfig @@ -603,7 +603,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3220g-eval/nxwm/defconfig b/configs/stm3220g-eval/nxwm/defconfig index 71096f14d2..bdd33e67b6 100644 --- a/configs/stm3220g-eval/nxwm/defconfig +++ b/configs/stm3220g-eval/nxwm/defconfig @@ -622,7 +622,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3240g-eval/knxwm/defconfig b/configs/stm3240g-eval/knxwm/defconfig index 55e71a0d6d..e5c07319dc 100644 --- a/configs/stm3240g-eval/knxwm/defconfig +++ b/configs/stm3240g-eval/knxwm/defconfig @@ -616,7 +616,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3240g-eval/nsh2/defconfig b/configs/stm3240g-eval/nsh2/defconfig index 14d341e3b2..9cb4875f38 100644 --- a/configs/stm3240g-eval/nsh2/defconfig +++ b/configs/stm3240g-eval/nsh2/defconfig @@ -607,7 +607,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3240g-eval/nxterm/defconfig b/configs/stm3240g-eval/nxterm/defconfig index be5de3bcdc..9aed6dd720 100644 --- a/configs/stm3240g-eval/nxterm/defconfig +++ b/configs/stm3240g-eval/nxterm/defconfig @@ -626,7 +626,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm3240g-eval/nxwm/defconfig b/configs/stm3240g-eval/nxwm/defconfig index fc3e55862e..63a4cf23a8 100644 --- a/configs/stm3240g-eval/nxwm/defconfig +++ b/configs/stm3240g-eval/nxwm/defconfig @@ -626,7 +626,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32_tiny/nsh/defconfig b/configs/stm32_tiny/nsh/defconfig index 8997783b56..d1c78f0cbd 100644 --- a/configs/stm32_tiny/nsh/defconfig +++ b/configs/stm32_tiny/nsh/defconfig @@ -546,7 +546,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32_tiny/usbnsh/defconfig b/configs/stm32_tiny/usbnsh/defconfig index a00da5fcaa..6f9342afa8 100644 --- a/configs/stm32_tiny/usbnsh/defconfig +++ b/configs/stm32_tiny/usbnsh/defconfig @@ -540,7 +540,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32butterfly2/nsh/defconfig b/configs/stm32butterfly2/nsh/defconfig index e036cc7e31..56edadf664 100644 --- a/configs/stm32butterfly2/nsh/defconfig +++ b/configs/stm32butterfly2/nsh/defconfig @@ -575,7 +575,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -CONFIG_BOARDCTL_ADCTEST=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32butterfly2/nshnet/defconfig b/configs/stm32butterfly2/nshnet/defconfig index b234a4297d..b8249473b6 100644 --- a/configs/stm32butterfly2/nshnet/defconfig +++ b/configs/stm32butterfly2/nshnet/defconfig @@ -583,7 +583,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -CONFIG_BOARDCTL_ADCTEST=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32butterfly2/nshusbdev/defconfig b/configs/stm32butterfly2/nshusbdev/defconfig index b30c5c9fd2..01071e210d 100644 --- a/configs/stm32butterfly2/nshusbdev/defconfig +++ b/configs/stm32butterfly2/nshusbdev/defconfig @@ -568,7 +568,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -CONFIG_BOARDCTL_ADCTEST=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32butterfly2/nshusbhost/defconfig b/configs/stm32butterfly2/nshusbhost/defconfig index e036cc7e31..56edadf664 100644 --- a/configs/stm32butterfly2/nshusbhost/defconfig +++ b/configs/stm32butterfly2/nshusbhost/defconfig @@ -575,7 +575,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -CONFIG_BOARDCTL_ADCTEST=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f103-minimum/audio_tone/defconfig b/configs/stm32f103-minimum/audio_tone/defconfig index 423deaad57..42f05f35f1 100644 --- a/configs/stm32f103-minimum/audio_tone/defconfig +++ b/configs/stm32f103-minimum/audio_tone/defconfig @@ -552,7 +552,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f103-minimum/buttons/defconfig b/configs/stm32f103-minimum/buttons/defconfig index 3408e75ec4..d18846b909 100644 --- a/configs/stm32f103-minimum/buttons/defconfig +++ b/configs/stm32f103-minimum/buttons/defconfig @@ -542,7 +542,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f103-minimum/jlx12864g/defconfig b/configs/stm32f103-minimum/jlx12864g/defconfig index c7794055bb..7714aa1c45 100644 --- a/configs/stm32f103-minimum/jlx12864g/defconfig +++ b/configs/stm32f103-minimum/jlx12864g/defconfig @@ -594,7 +594,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f103-minimum/nsh/defconfig b/configs/stm32f103-minimum/nsh/defconfig index da00dedca0..f66dd17b41 100644 --- a/configs/stm32f103-minimum/nsh/defconfig +++ b/configs/stm32f103-minimum/nsh/defconfig @@ -538,7 +538,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f103-minimum/pwm/defconfig b/configs/stm32f103-minimum/pwm/defconfig index 152a1f55f1..971e72ba34 100644 --- a/configs/stm32f103-minimum/pwm/defconfig +++ b/configs/stm32f103-minimum/pwm/defconfig @@ -550,7 +550,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f103-minimum/rfid-rc522/defconfig b/configs/stm32f103-minimum/rfid-rc522/defconfig index 6fed7b2f8a..d32c6b3008 100644 --- a/configs/stm32f103-minimum/rfid-rc522/defconfig +++ b/configs/stm32f103-minimum/rfid-rc522/defconfig @@ -546,7 +546,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f103-minimum/rgbled/defconfig b/configs/stm32f103-minimum/rgbled/defconfig index 79a80423a6..2fd2f2707a 100644 --- a/configs/stm32f103-minimum/rgbled/defconfig +++ b/configs/stm32f103-minimum/rgbled/defconfig @@ -577,7 +577,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f103-minimum/usbnsh/defconfig b/configs/stm32f103-minimum/usbnsh/defconfig index d93e7de8c9..83ca39bb6c 100644 --- a/configs/stm32f103-minimum/usbnsh/defconfig +++ b/configs/stm32f103-minimum/usbnsh/defconfig @@ -540,7 +540,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f103-minimum/userled/defconfig b/configs/stm32f103-minimum/userled/defconfig index f8c736137b..02996a0ab5 100644 --- a/configs/stm32f103-minimum/userled/defconfig +++ b/configs/stm32f103-minimum/userled/defconfig @@ -538,7 +538,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f103-minimum/veml6070/defconfig b/configs/stm32f103-minimum/veml6070/defconfig index 28b6371670..3fd720b90f 100644 --- a/configs/stm32f103-minimum/veml6070/defconfig +++ b/configs/stm32f103-minimum/veml6070/defconfig @@ -563,7 +563,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f3discovery/nsh/defconfig b/configs/stm32f3discovery/nsh/defconfig index 46b24777c9..e3495e5ddb 100644 --- a/configs/stm32f3discovery/nsh/defconfig +++ b/configs/stm32f3discovery/nsh/defconfig @@ -556,7 +556,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f3discovery/usbnsh/defconfig b/configs/stm32f3discovery/usbnsh/defconfig index 69eac04b68..b7be381bdd 100644 --- a/configs/stm32f3discovery/usbnsh/defconfig +++ b/configs/stm32f3discovery/usbnsh/defconfig @@ -563,7 +563,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f429i-disco/extflash/defconfig b/configs/stm32f429i-disco/extflash/defconfig index 3e89f5d9cd..916011dfe8 100644 --- a/configs/stm32f429i-disco/extflash/defconfig +++ b/configs/stm32f429i-disco/extflash/defconfig @@ -593,7 +593,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f429i-disco/lcd/defconfig b/configs/stm32f429i-disco/lcd/defconfig index 7742784b56..7f8194d36a 100644 --- a/configs/stm32f429i-disco/lcd/defconfig +++ b/configs/stm32f429i-disco/lcd/defconfig @@ -593,7 +593,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f429i-disco/usbmsc/defconfig b/configs/stm32f429i-disco/usbmsc/defconfig index 7eb67d1081..e67c0af126 100644 --- a/configs/stm32f429i-disco/usbmsc/defconfig +++ b/configs/stm32f429i-disco/usbmsc/defconfig @@ -588,7 +588,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f429i-disco/usbnsh/defconfig b/configs/stm32f429i-disco/usbnsh/defconfig index b48cb3c714..e7e805b97f 100644 --- a/configs/stm32f429i-disco/usbnsh/defconfig +++ b/configs/stm32f429i-disco/usbnsh/defconfig @@ -579,7 +579,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f4discovery/canard/defconfig b/configs/stm32f4discovery/canard/defconfig index 3214be0633..c1d19f3ed8 100644 --- a/configs/stm32f4discovery/canard/defconfig +++ b/configs/stm32f4discovery/canard/defconfig @@ -589,7 +589,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set CONFIG_BOARDCTL_CANINIT=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f4discovery/ipv6/defconfig b/configs/stm32f4discovery/ipv6/defconfig index 001398e732..a0ba73ae9c 100644 --- a/configs/stm32f4discovery/ipv6/defconfig +++ b/configs/stm32f4discovery/ipv6/defconfig @@ -626,7 +626,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f4discovery/netnsh/defconfig b/configs/stm32f4discovery/netnsh/defconfig index cb5c0302a3..24acf42035 100644 --- a/configs/stm32f4discovery/netnsh/defconfig +++ b/configs/stm32f4discovery/netnsh/defconfig @@ -626,7 +626,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_RESET=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f4discovery/usbnsh/defconfig b/configs/stm32f4discovery/usbnsh/defconfig index f2e1cdf6e0..732aff799c 100644 --- a/configs/stm32f4discovery/usbnsh/defconfig +++ b/configs/stm32f4discovery/usbnsh/defconfig @@ -588,7 +588,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig index 75e20adb4b..f49876c5c7 100644 --- a/configs/stm32f746-ws/nsh/defconfig +++ b/configs/stm32f746-ws/nsh/defconfig @@ -469,7 +469,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32l476-mdk/nsh/defconfig b/configs/stm32l476-mdk/nsh/defconfig index b92a9cf5bd..2d6b19fd7e 100644 --- a/configs/stm32l476-mdk/nsh/defconfig +++ b/configs/stm32l476-mdk/nsh/defconfig @@ -373,7 +373,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_UNIQUEID=y CONFIG_BOARDCTL_UNIQUEID_SIZE=12 # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32l476vg-disco/nsh/defconfig b/configs/stm32l476vg-disco/nsh/defconfig index a6026d5a3c..6a25d6e89b 100644 --- a/configs/stm32l476vg-disco/nsh/defconfig +++ b/configs/stm32l476vg-disco/nsh/defconfig @@ -391,7 +391,6 @@ CONFIG_LIB_BOARDCTL=y CONFIG_BOARDCTL_UNIQUEID=y CONFIG_BOARDCTL_UNIQUEID_SIZE=12 # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set CONFIG_BOARDCTL_IOCTL=y diff --git a/configs/sure-pic32mx/nsh/defconfig b/configs/sure-pic32mx/nsh/defconfig index 501cdf7639..6934ae6970 100644 --- a/configs/sure-pic32mx/nsh/defconfig +++ b/configs/sure-pic32mx/nsh/defconfig @@ -339,7 +339,6 @@ CONFIG_ARCH_DBDP11215=y CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sure-pic32mx/usbnsh/defconfig b/configs/sure-pic32mx/usbnsh/defconfig index 1d6f01fce4..b5dd27d3ed 100644 --- a/configs/sure-pic32mx/usbnsh/defconfig +++ b/configs/sure-pic32mx/usbnsh/defconfig @@ -341,7 +341,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/teensy-3.x/usbnsh/defconfig b/configs/teensy-3.x/usbnsh/defconfig index 31f717f133..25bb2c87e6 100644 --- a/configs/teensy-3.x/usbnsh/defconfig +++ b/configs/teensy-3.x/usbnsh/defconfig @@ -307,7 +307,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/teensy-lc/nsh/defconfig b/configs/teensy-lc/nsh/defconfig index b9de76765e..e00646624c 100644 --- a/configs/teensy-lc/nsh/defconfig +++ b/configs/teensy-lc/nsh/defconfig @@ -272,7 +272,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/tm4c123g-launchpad/nsh/defconfig b/configs/tm4c123g-launchpad/nsh/defconfig index ba93f9714a..0f871ed23f 100644 --- a/configs/tm4c123g-launchpad/nsh/defconfig +++ b/configs/tm4c123g-launchpad/nsh/defconfig @@ -338,7 +338,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/tm4c1294-launchpad/ipv6/defconfig b/configs/tm4c1294-launchpad/ipv6/defconfig index ea44f86d5f..0d05d6b4cb 100644 --- a/configs/tm4c1294-launchpad/ipv6/defconfig +++ b/configs/tm4c1294-launchpad/ipv6/defconfig @@ -357,7 +357,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/tm4c1294-launchpad/nsh/defconfig b/configs/tm4c1294-launchpad/nsh/defconfig index f8cbc9e5a9..a4131c7391 100644 --- a/configs/tm4c1294-launchpad/nsh/defconfig +++ b/configs/tm4c1294-launchpad/nsh/defconfig @@ -357,7 +357,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/u-blox-c027/nsh/defconfig b/configs/u-blox-c027/nsh/defconfig index a0845f5bad..7e4713c0c9 100644 --- a/configs/u-blox-c027/nsh/defconfig +++ b/configs/u-blox-c027/nsh/defconfig @@ -323,7 +323,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/ubw32/nsh/defconfig b/configs/ubw32/nsh/defconfig index 3c23567159..59dee9b713 100644 --- a/configs/ubw32/nsh/defconfig +++ b/configs/ubw32/nsh/defconfig @@ -338,7 +338,6 @@ CONFIG_ARCH_HAVE_IRQBUTTONS=y CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/zkit-arm-1769/nsh/defconfig b/configs/zkit-arm-1769/nsh/defconfig index 5762266bb1..19e8ebc26f 100644 --- a/configs/zkit-arm-1769/nsh/defconfig +++ b/configs/zkit-arm-1769/nsh/defconfig @@ -317,7 +317,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/zkit-arm-1769/nxhello/defconfig b/configs/zkit-arm-1769/nxhello/defconfig index 7a485050a8..370e8d037c 100644 --- a/configs/zkit-arm-1769/nxhello/defconfig +++ b/configs/zkit-arm-1769/nxhello/defconfig @@ -317,7 +317,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/zp214xpa/nxlines/defconfig b/configs/zp214xpa/nxlines/defconfig index ebb8928ac1..cfc2584b66 100644 --- a/configs/zp214xpa/nxlines/defconfig +++ b/configs/zp214xpa/nxlines/defconfig @@ -236,7 +236,6 @@ CONFIG_ARCH_BOARD="zp214xpa" CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_ADCTEST is not set CONFIG_BOARDCTL_GRAPHICS=y # CONFIG_BOARDCTL_IOCTL is not set diff --git a/include/nuttx/board.h b/include/nuttx/board.h index 72e39de945..0c436de8a3 100644 --- a/include/nuttx/board.h +++ b/include/nuttx/board.h @@ -315,23 +315,6 @@ int board_tsc_setup(int minor); void board_tsc_teardown(void); -/**************************************************************************** - * Name: board_adc_setup - * - * Description: - * All architectures must provide the following interface in order to - * work with examples/adc. - * - * This is an internal OS interface but may be invoked indirectly from - * application-level graphics logic. If CONFIG_LIB_BOARDCTL=y and - * CONFIG_BOARDCTL_ADCTEST=y, then this functions will be invoked via the - * (non-standard) boardctl() interface using the BOARDIOC_ADCTEST_SETUP - * command. - * - ****************************************************************************/ - -int board_adc_setup(void); - /**************************************************************************** * Name: board_graphics_setup * diff --git a/include/sys/boardctl.h b/include/sys/boardctl.h index 6f0bd8253e..9a0e984358 100644 --- a/include/sys/boardctl.h +++ b/include/sys/boardctl.h @@ -127,12 +127,6 @@ * CONFIGURATION: CONFIG_LIB_BOARDCTL && CONFIG_BOARDCTL_TSCTEST * DEPENDENCIES: Board logic must provide board_tsc_teardown() * - * CMD: BOARDIOC_ADCTEST_SETUP - * DESCRIPTION: ADC controller test configuration - * ARG: None - * CONFIGURATION: CONFIG_LIB_BOARDCTL && CONFIG_BOARDCTL_ADCTEST - * DEPENDENCIES: Board logic must provide board_adc_setup() - * * CMD: BOARDIOC_CAN_INITIALIZE * DESCRIPTION: CAN device initialization * ARG: None @@ -144,7 +138,7 @@ * procedures * ARG: A pointer to an instance of struct boardioc_graphics_s * CONFIGURATION: CONFIG_LIB_BOARDCTL && CONFIG_BOARDCTL_GRAPHICS - * DEPENDENCIES: Board logic must provide board_adc_setup() + * DEPENDENCIES: Board logic must provide board_graphics_setup() */ #define BOARDIOC_INIT _BOARDIOC(0x0001) @@ -157,9 +151,8 @@ #define BOARDIOC_NX_START _BOARDIOC(0x0008) #define BOARDIOC_TSCTEST_SETUP _BOARDIOC(0x0009) #define BOARDIOC_TSCTEST_TEARDOWN _BOARDIOC(0x000a) -#define BOARDIOC_ADCTEST_SETUP _BOARDIOC(0x000b) #define BOARDIOC_CAN_INITIALIZE _BOARDIOC(0x000c) -#define BOARDIOC_GRAPHICS_SETUP _BOARDIOC(0x000d) +#define BOARDIOC_GRAPHICS_SETUP _BOARDIOC(0x000c) /* If CONFIG_BOARDCTL_IOCTL=y, then boad-specific commands will be support. * In this case, all commands not recognized by boardctl() will be forwarded -- GitLab From ee2852f5ffba46bfad2bb908c9fd3a44956e0845 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 5 Dec 2016 17:06:08 -0600 Subject: [PATCH 605/734] Remove all references to board_adc_setup() --- configs/cloudctrl/src/cloudctrl.h | 15 ++- configs/cloudctrl/src/stm32_adc.c | 13 +-- configs/cloudctrl/src/stm32_appinit.c | 14 ++- configs/lpc4337-ws/src/lpc4337-ws.h | 13 ++- configs/lpc4337-ws/src/lpc43_adc.c | 7 +- configs/lpc4337-ws/src/lpc43_appinit.c | 14 +++ configs/lpc4370-link2/src/lpc4370-link2.h | 22 +++- configs/lpc4370-link2/src/lpc43_adc.c | 9 +- configs/lpc4370-link2/src/lpc43_appinit.c | 14 +++ configs/lpcxpresso-lpc1768/src/Makefile | 6 +- configs/lpcxpresso-lpc1768/src/lpc17_adc.c | 21 +--- .../lpcxpresso-lpc1768/src/lpc17_appinit.c | 10 ++ .../src/lpcxpresso-lpc1768.h | 18 +++- configs/mbed/src/Makefile | 7 +- configs/mbed/src/lpc17_adc.c | 21 +--- configs/mbed/src/lpc17_appinit.c | 10 ++ configs/mbed/src/mbed.h | 12 +++ configs/nucleo-144/src/Makefile | 1 + configs/nucleo-144/src/nucleo-144.h | 24 ++--- configs/nucleo-144/src/stm32_adc.c | 20 +--- configs/nucleo-144/src/stm32_appinitialize.c | 10 ++ configs/nucleo-f303re/src/nucleo-f303re.h | 12 +++ configs/nucleo-f303re/src/stm32_adc.c | 101 ++++++++---------- .../nucleo-f303re/src/stm32_appinitialize.c | 13 ++- configs/nucleo-f4x1re/src/nucleo-f4x1re.h | 6 +- configs/nucleo-f4x1re/src/stm32_adc.c | 83 ++++---------- configs/nucleo-f4x1re/src/stm32_ajoystick.c | 10 +- configs/nucleo-f4x1re/src/stm32_appinit.c | 10 ++ configs/nucleo-l476rg/src/nucleo-l476rg.h | 8 +- configs/nucleo-l476rg/src/stm32_adc.c | 79 ++++---------- configs/nucleo-l476rg/src/stm32_ajoystick.c | 10 +- configs/nucleo-l476rg/src/stm32_appinit.c | 14 ++- .../olimex-stm32-e407/src/olimex-stm32-e407.h | 20 ++-- configs/olimex-stm32-e407/src/stm32_adc.c | 20 +--- configs/olimex-stm32-e407/src/stm32_appinit.c | 9 +- .../olimex-stm32-h405/src/olimex-stm32-h405.h | 6 +- configs/olimex-stm32-h405/src/stm32_adc.c | 26 +---- configs/olimex-stm32-h405/src/stm32_appinit.c | 21 ++-- .../olimex-stm32-h407/src/olimex-stm32-h407.h | 10 +- configs/olimex-stm32-h407/src/stm32_adc.c | 24 +---- configs/olimex-stm32-h407/src/stm32_bringup.c | 14 +-- .../olimex-stm32-p207/src/olimex-stm32-p207.h | 6 +- configs/olimex-stm32-p207/src/stm32_adc.c | 26 +---- configs/olimex-stm32-p207/src/stm32_appinit.c | 11 +- configs/sama5d3-xplained/src/sam_adc.c | 40 +------ configs/sama5d3-xplained/src/sam_ajoystick.c | 10 +- configs/sama5d3-xplained/src/sam_appinit.c | 10 ++ .../sama5d3-xplained/src/sama5d3-xplained.h | 16 +-- configs/sama5d3x-ek/src/sam_adc.c | 22 +--- configs/sama5d3x-ek/src/sam_appinit.c | 10 ++ configs/sama5d3x-ek/src/sama5d3x-ek.h | 12 +++ configs/sama5d4-ek/src/sam_adc.c | 21 +--- configs/sama5d4-ek/src/sam_bringup.c | 10 ++ configs/sama5d4-ek/src/sama5d4-ek.h | 12 +++ configs/shenzhou/src/shenzhou.h | 12 +++ configs/shenzhou/src/stm32_adc.c | 13 +-- configs/shenzhou/src/stm32_appinit.c | 13 ++- configs/stm3210e-eval/src/stm3210e-eval.h | 12 +++ configs/stm3210e-eval/src/stm32_adc.c | 13 +-- configs/stm3210e-eval/src/stm32_appinit.c | 13 ++- configs/stm3220g-eval/src/stm3220g-eval.h | 12 +++ configs/stm3220g-eval/src/stm32_adc.c | 13 +-- configs/stm3220g-eval/src/stm32_appinit.c | 13 ++- configs/stm3240g-eval/src/stm3240g-eval.h | 12 +++ configs/stm3240g-eval/src/stm32_adc.c | 13 +-- configs/stm3240g-eval/src/stm32_appinit.c | 13 ++- configs/stm32butterfly2/src/stm32_adc.c | 11 +- configs/stm32butterfly2/src/stm32_boot.c | 29 +++-- .../stm32butterfly2/src/stm32_butterfly2.h | 14 +++ .../stm32l476vg-disco/src/stm32l476vg-disco.h | 12 --- .../src/tm4c123g-launchpad.h | 26 ++--- configs/tm4c123g-launchpad/src/tm4c_adc.c | 68 ++++-------- configs/tm4c123g-launchpad/src/tm4c_bringup.c | 13 ++- configs/u-blox-c027/src/Makefile | 6 +- configs/u-blox-c027/src/lpc17_adc.c | 9 +- configs/u-blox-c027/src/lpc17_appinit.c | 10 ++ configs/u-blox-c027/src/u-blox-c027.h | 12 +++ configs/zkit-arm-1769/src/Makefile | 2 +- configs/zkit-arm-1769/src/lpc17_adc.c | 9 +- configs/zkit-arm-1769/src/lpc17_appinit.c | 17 ++- configs/zkit-arm-1769/src/zkit-arm-1769.h | 14 ++- 81 files changed, 726 insertions(+), 661 deletions(-) diff --git a/configs/cloudctrl/src/cloudctrl.h b/configs/cloudctrl/src/cloudctrl.h index 44042435af..57f1847d85 100644 --- a/configs/cloudctrl/src/cloudctrl.h +++ b/configs/cloudctrl/src/cloudctrl.h @@ -1,8 +1,7 @@ /**************************************************************************************************** * configs/cloudctrl/src/cloudctrl.h - * arch/arm/src/board/cloudctrl.n * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * Darcy Gong * @@ -255,6 +254,18 @@ void weak_function stm32_usbinitialize(void); int stm32_usbhost_initialize(void); #endif +/************************************************************************************ + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_ADC +int stm32_adc_setup(void); +#endif + /**************************************************************************** * Name: stm32_sdinitialize * diff --git a/configs/cloudctrl/src/stm32_adc.c b/configs/cloudctrl/src/stm32_adc.c index 346100b782..ba798386d0 100644 --- a/configs/cloudctrl/src/stm32_adc.c +++ b/configs/cloudctrl/src/stm32_adc.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/cloudctrl/src/stm32_adc.c * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * Darcy Gong * @@ -105,24 +105,19 @@ static const uint8_t g_chanlist[ADC1_NCHANNELS] = {10}; //{10, 8, 9}; static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC12_IN10}; //{GPIO_ADC12_IN10, GPIO_ADC12_IN8, GPIO_ADC12_IN9}; #endif -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_adc_setup + * Name: stm32_adc_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/adc. + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -int board_adc_setup(void) +int stm32_adc_setup(void) { #ifdef CONFIG_STM32_ADC1 static bool initialized = false; diff --git a/configs/cloudctrl/src/stm32_appinit.c b/configs/cloudctrl/src/stm32_appinit.c index cc772b5add..c628bd142a 100644 --- a/configs/cloudctrl/src/stm32_appinit.c +++ b/configs/cloudctrl/src/stm32_appinit.c @@ -127,9 +127,7 @@ int board_app_initialize(uintptr_t arg) { -#if defined(HAVE_USBHOST) || defined(HAVE_W25) int ret; -#endif /* Initialize and register the W25 FLASH file system. */ @@ -156,5 +154,17 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + return ret; + } +#endif + + UNUSED(ret); return OK; } diff --git a/configs/lpc4337-ws/src/lpc4337-ws.h b/configs/lpc4337-ws/src/lpc4337-ws.h index 7c31fe745b..d5c11a35b9 100644 --- a/configs/lpc4337-ws/src/lpc4337-ws.h +++ b/configs/lpc4337-ws/src/lpc4337-ws.h @@ -67,6 +67,17 @@ * Public Functions ****************************************************************************/ -#endif /* __ASSEMBLY__ */ +/************************************************************************************ + * Name: lpc43_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_LPC43_ADC0 +int lpc43_adc_setup(void); #endif +#endif /* __ASSEMBLY__ */ +#endif diff --git a/configs/lpc4337-ws/src/lpc43_adc.c b/configs/lpc4337-ws/src/lpc43_adc.c index c1cb491f61..e54ca29ea5 100644 --- a/configs/lpc4337-ws/src/lpc43_adc.c +++ b/configs/lpc4337-ws/src/lpc43_adc.c @@ -63,15 +63,14 @@ ************************************************************************************/ /************************************************************************************ - * Name: board_adc_setup + * Name: lpc43_adc_setup * * Description: - * All LPC43 architectures must provide the following interface to work with - * examples/adc. + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -int board_adc_setup(void) +int lpc43_adc_setup(void) { static bool initialized = false; struct adc_dev_s *adc; diff --git a/configs/lpc4337-ws/src/lpc43_appinit.c b/configs/lpc4337-ws/src/lpc43_appinit.c index 3ae071fe12..047b544caa 100644 --- a/configs/lpc4337-ws/src/lpc43_appinit.c +++ b/configs/lpc4337-ws/src/lpc43_appinit.c @@ -135,8 +135,22 @@ static void lpc43_i2ctool(void) int board_app_initialize(uintptr_t arg) { + int ret; + /* Register I2C drivers on behalf of the I2C tool */ lpc43_i2ctool(); + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = lpc43_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: lpc43_adc_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); return OK; } diff --git a/configs/lpc4370-link2/src/lpc4370-link2.h b/configs/lpc4370-link2/src/lpc4370-link2.h index 887d5b94f4..52c3083d13 100644 --- a/configs/lpc4370-link2/src/lpc4370-link2.h +++ b/configs/lpc4370-link2/src/lpc4370-link2.h @@ -1,7 +1,7 @@ /**************************************************************************** * configs/lpc4370-link2/src/lpc4370-link2.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -99,8 +99,28 @@ * Public Functions ****************************************************************************/ +/************************************************************************************ + * Name: board_spifi_initialize + * + * Description: + * Initialize SPIFI. + * + ************************************************************************************/ + void board_spifi_initialize(void); +/************************************************************************************ + * Name: lpc43_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_ADC +int lpc43_adc_setup(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* _CONFIGS_LPC4370_LINK2_SRC_LPC3257_LINK2_H */ diff --git a/configs/lpc4370-link2/src/lpc43_adc.c b/configs/lpc4370-link2/src/lpc43_adc.c index def52a5748..0a350e5713 100644 --- a/configs/lpc4370-link2/src/lpc43_adc.c +++ b/configs/lpc4370-link2/src/lpc43_adc.c @@ -6,7 +6,7 @@ * * Based on configs/stm3220g-eval/src/lpc43_adc.c * - * Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -63,15 +63,14 @@ ************************************************************************************/ /************************************************************************************ - * Name: board_adc_setup + * Name: lpc43_adc_setup * * Description: - * All LPC43 architectures must provide the following interface to work with - * examples/adc. + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -int board_adc_setup(void) +int lpc43_adc_setup(void) { static bool initialized = false; struct adc_dev_s *adc; diff --git a/configs/lpc4370-link2/src/lpc43_appinit.c b/configs/lpc4370-link2/src/lpc43_appinit.c index 8493fb391d..ceda373a43 100644 --- a/configs/lpc4370-link2/src/lpc43_appinit.c +++ b/configs/lpc4370-link2/src/lpc43_appinit.c @@ -135,8 +135,22 @@ static void lpc43_i2ctool(void) int board_app_initialize(uintptr_t arg) { + int ret; + /* Register I2C drivers on behalf of the I2C tool */ lpc43_i2ctool(); + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = lpc43_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: lpc43_adc_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); return OK; } diff --git a/configs/lpcxpresso-lpc1768/src/Makefile b/configs/lpcxpresso-lpc1768/src/Makefile index 971d589eb3..24441d8eb3 100644 --- a/configs/lpcxpresso-lpc1768/src/Makefile +++ b/configs/lpcxpresso-lpc1768/src/Makefile @@ -36,12 +36,16 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = lpc17_boot.c lpc17_leds.c lpc17_ssp.c lpc17_adc.c lpc17_dac.c +CSRCS = lpc17_boot.c lpc17_leds.c lpc17_ssp.c lpc17_dac.c ifeq ($(CONFIG_PWM),y) CSRCS += lpc17_pwm.c endif +ifeq ($(CONFIG_ADC),y) +CSRCS += lpc17_adc.c +endif + ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += lpc17_appinit.c endif diff --git a/configs/lpcxpresso-lpc1768/src/lpc17_adc.c b/configs/lpcxpresso-lpc1768/src/lpc17_adc.c index b7d1b6ddb9..e76f67ff20 100644 --- a/configs/lpcxpresso-lpc1768/src/lpc17_adc.c +++ b/configs/lpcxpresso-lpc1768/src/lpc17_adc.c @@ -6,7 +6,7 @@ * * Based on configs/stm3220g-eval/src/lpc17_adc.c * - * Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -59,32 +59,19 @@ #ifdef CONFIG_ADC -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Data - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_adc_setup + * Name: lpcxpresso_adc_setup * * Description: - * All LPC17 architectures must provide the following interface to work with - * examples/adc. + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -int board_adc_setup(void) +int lpcxpresso_adc_setup(void) { static bool initialized = false; struct adc_dev_s *adc; diff --git a/configs/lpcxpresso-lpc1768/src/lpc17_appinit.c b/configs/lpcxpresso-lpc1768/src/lpc17_appinit.c index fb55c2128c..d922e61963 100644 --- a/configs/lpcxpresso-lpc1768/src/lpc17_appinit.c +++ b/configs/lpcxpresso-lpc1768/src/lpc17_appinit.c @@ -181,6 +181,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = lpcxpresso_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: lpcxpresso_adc_setup failed: %d\n", ret); + } +#endif + UNUSED(ret); return OK; } diff --git a/configs/lpcxpresso-lpc1768/src/lpcxpresso-lpc1768.h b/configs/lpcxpresso-lpc1768/src/lpcxpresso-lpc1768.h index b88821559e..ecde0db121 100644 --- a/configs/lpcxpresso-lpc1768/src/lpcxpresso-lpc1768.h +++ b/configs/lpcxpresso-lpc1768/src/lpcxpresso-lpc1768.h @@ -1,5 +1,5 @@ /************************************************************************************ - * configs/lpcxpresso-lpc1768/src/lpcxpresso-lpc1768.h + * configs/lpcxpresso-lpcxpresso68/src/lpcxpresso-lpcxpresso68.h * * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -140,8 +140,8 @@ * SD Signal Pin Pin * --- ----------- ----- -------- * CS PIO1_11* 55 P2.2 (See LPCXPRESSO_SD_CS) - * DIN PIO0_9-MOSI 5 P0.9 MOSI1 (See GPIO_SSP1_MOSI in chip/lpc17_ssp.h) - * DOUT PIO0_8-MISO 6 P0.8 MISO1 (See GPIO_SSP1_MISO in chip/lpc17_ssp.h) + * DIN PIO0_9-MOSI 5 P0.9 MOSI1 (See GPIO_SSP1_MOSI in chip/lpcxpresso_ssp.h) + * DOUT PIO0_8-MISO 6 P0.8 MISO1 (See GPIO_SSP1_MISO in chip/lpcxpresso_ssp.h) * CLK PIO2_11-SCK 7 P0.9 SCK1 (See GPIO_SSP1_SCK in board.h) * CD PIO2_10 52 P2.11 (See LPCXPRESSO_SD_CD) */ @@ -242,6 +242,18 @@ void weak_function lpcxpresso_sspdev_initialize(void); int lpcexpresso_pwm_setup(void); #endif +/************************************************************************************ + * Name: lpcxpresso_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_ADC +int lpcxpresso_adc_setup(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* _CONFIGS_LPCXPRESSO_LPC1768_SRC_LPCXPRESSO_H */ diff --git a/configs/mbed/src/Makefile b/configs/mbed/src/Makefile index e2d360dac7..6a93bdb091 100644 --- a/configs/mbed/src/Makefile +++ b/configs/mbed/src/Makefile @@ -36,11 +36,12 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = lpc17_boot.c lpc17_leds.c lpc17_adc.c lpc17_dac.c +CSRCS = lpc17_boot.c lpc17_leds.c lpc17_dac.c ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += lpc17_appinit.c endif + ifeq ($(CONFIG_USBMSC),y) CSRCS += lpc17_usbmsc.c endif @@ -49,6 +50,10 @@ ifeq ($(CONFIG_PWM),y) CSRCS += lpc17_pwm.c endif +ifeq ($(CONFIG_ADC),y) +CSRCS += lpc17_adc.c +endif + ifeq ($(CONFIG_EXAMPLES_HIDKBD),y) CSRCS += lpc17_hidkbd.c endif diff --git a/configs/mbed/src/lpc17_adc.c b/configs/mbed/src/lpc17_adc.c index 4cc9b6ad8d..059e63de00 100644 --- a/configs/mbed/src/lpc17_adc.c +++ b/configs/mbed/src/lpc17_adc.c @@ -8,7 +8,7 @@ * * Based on configs/lpc1720g-eval/src/lpc17_adc.c * - * Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -61,32 +61,19 @@ #ifdef CONFIG_ADC -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Data - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_adc_setup + * Name: mbed_adc_setup * * Description: - * All LPC17 architectures must provide the following interface to work with - * examples/adc. + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -int board_adc_setup(void) +int mbed_adc_setup(void) { static bool initialized = false; struct adc_dev_s *adc; diff --git a/configs/mbed/src/lpc17_appinit.c b/configs/mbed/src/lpc17_appinit.c index 15c2a19556..f371ab764b 100644 --- a/configs/mbed/src/lpc17_appinit.c +++ b/configs/mbed/src/lpc17_appinit.c @@ -111,6 +111,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = mbed_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: mbed_adc_setup failed: %d\n", ret); + } +#endif + UNUSED(ret); return OK; } diff --git a/configs/mbed/src/mbed.h b/configs/mbed/src/mbed.h index 2b8bac944c..5978e5d17c 100644 --- a/configs/mbed/src/mbed.h +++ b/configs/mbed/src/mbed.h @@ -100,6 +100,18 @@ void weak_function mbed_sspdev_initialize(void); int mbed_pwm_setup(void); #endif +/************************************************************************************ + * Name: mbed_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_ADC +int mbed_adc_setup(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* _CONFIGS_MBED_SRC_MBED_H */ diff --git a/configs/nucleo-144/src/Makefile b/configs/nucleo-144/src/Makefile index 846122801b..52068fbe35 100644 --- a/configs/nucleo-144/src/Makefile +++ b/configs/nucleo-144/src/Makefile @@ -56,6 +56,7 @@ endif ifeq ($(CONFIG_SPI),y) CSRCS += stm32_spi.c endif + ifeq ($(CONFIG_ADC),y) CSRCS += stm32_adc.c endif diff --git a/configs/nucleo-144/src/nucleo-144.h b/configs/nucleo-144/src/nucleo-144.h index 9b0e25cb4c..b12dbead8b 100644 --- a/configs/nucleo-144/src/nucleo-144.h +++ b/configs/nucleo-144/src/nucleo-144.h @@ -244,18 +244,6 @@ void stm32_dma_alloc_init(void); int stm32_dma_alloc_init(void); #endif -/**************************************************************************** - * Name: stm32_adc_initialize - * - * Description: - * Called at application startup time to initialize the ADC functionality. - * - ****************************************************************************/ - -#ifdef CONFIG_ADC -int board_adc_initialize(void); -#endif - /**************************************************************************** * Name: stm32_sdio_initialize * @@ -281,6 +269,18 @@ int stm32_sdio_initialize(void); void stm32_usbinitialize(void); #endif +/************************************************************************************ + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_ADC +int stm32_adc_setup(void); +#endif + /************************************************************************************ * Name: stm32_bbsram_int ************************************************************************************/ diff --git a/configs/nucleo-144/src/stm32_adc.c b/configs/nucleo-144/src/stm32_adc.c index f185335a7a..5a26723f5e 100644 --- a/configs/nucleo-144/src/stm32_adc.c +++ b/configs/nucleo-144/src/stm32_adc.c @@ -112,28 +112,14 @@ static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN3}; ************************************************************************************/ /************************************************************************************ - * Name: board_adc_setup + * Name: stm32_adc_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/adc. + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -int board_adc_setup(void) -{ - return board_adc_initialize(); -} - -/************************************************************************************ - * Name: stm32_adc_initialize - * - * Description: - * Called at application startup time to initialize the ADC functionality. - * - ************************************************************************************/ - -int board_adc_initialize(void) +int stm32_adc_setup(void) { #ifdef CONFIG_STM32F7_ADC1 static bool initialized = false; diff --git a/configs/nucleo-144/src/stm32_appinitialize.c b/configs/nucleo-144/src/stm32_appinitialize.c index 837048b5a1..86febc3e85 100644 --- a/configs/nucleo-144/src/stm32_appinitialize.c +++ b/configs/nucleo-144/src/stm32_appinitialize.c @@ -102,6 +102,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + #ifdef CONFIG_STM32F7_BBSRAM /* Initialize battery-backed RAM */ diff --git a/configs/nucleo-f303re/src/nucleo-f303re.h b/configs/nucleo-f303re/src/nucleo-f303re.h index d77bff2908..11d3c9c22a 100644 --- a/configs/nucleo-f303re/src/nucleo-f303re.h +++ b/configs/nucleo-f303re/src/nucleo-f303re.h @@ -179,4 +179,16 @@ int stm32_dac_setup(void); int stm32_pwm_setup(void); #endif +/************************************************************************************ + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_ADC +int stm32_adc_setup(void); +#endif + #endif /* __CONFIGS_NUCLEO_F303RE_SRC_NUCLEO_F303RE_H */ diff --git a/configs/nucleo-f303re/src/stm32_adc.c b/configs/nucleo-f303re/src/stm32_adc.c index 10183458ec..04014c4fe8 100644 --- a/configs/nucleo-f303re/src/stm32_adc.c +++ b/configs/nucleo-f303re/src/stm32_adc.c @@ -320,85 +320,74 @@ static const uint32_t g_pinlist2[1] = * Public Functions ****************************************************************************/ -/**************************************************************************** - * Name: board_adc_setup +/************************************************************************************ + * Name: stm32_adc_setup * * Description: - * All STM32 architectures must provide the following interface to work - * with examples/adc. + * Initialize ADC and register the ADC driver. * - ****************************************************************************/ + ************************************************************************************/ -int board_adc_setup(void) +int stm32_adc_setup(void) { - static bool initialized = false; FAR struct adc_dev_s *adc; int ret; int i; - /* Check if we have already initialized */ - - if (!initialized) { - - /* DEV1 */ - /* Configure the pins as analog inputs for the selected channels */ + /* DEV1 */ + /* Configure the pins as analog inputs for the selected channels */ - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - return -ENODEV; - } + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } - /* Register the ADC driver at "/dev/adc0" */ + /* Register the ADC driver at "/dev/adc0" */ - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); - return ret; - } + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } #ifdef DEV2_PORT - /* DEV2 */ - /* Configure the pins as analog inputs for the selected channels */ + /* DEV2 */ + /* Configure the pins as analog inputs for the selected channels */ - for (i = 0; i < DEV2_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist2[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 2\n"); - return -ENODEV; - } + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } - /* Register the ADC driver at "/dev/adc1" */ + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - ret = adc_register("/dev/adc1", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); - return ret; - } -#endif + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 2\n"); + return -ENODEV; + } - /* Now we are initialized */ + /* Register the ADC driver at "/dev/adc1" */ - initialized = true; + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); + return ret; } +#endif return OK; } diff --git a/configs/nucleo-f303re/src/stm32_appinitialize.c b/configs/nucleo-f303re/src/stm32_appinitialize.c index 1f6acb405a..56f43b328d 100644 --- a/configs/nucleo-f303re/src/stm32_appinitialize.c +++ b/configs/nucleo-f303re/src/stm32_appinitialize.c @@ -95,9 +95,7 @@ int board_app_initialize(uintptr_t arg) { -#if defined(HAVE_LEDS) || defined(HAVE_DAC) int ret; -#endif #ifdef HAVE_LEDS /* Register the LED driver */ @@ -133,5 +131,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); return OK; } diff --git a/configs/nucleo-f4x1re/src/nucleo-f4x1re.h b/configs/nucleo-f4x1re/src/nucleo-f4x1re.h index 14d1c042c6..c3d1a62ea0 100644 --- a/configs/nucleo-f4x1re/src/nucleo-f4x1re.h +++ b/configs/nucleo-f4x1re/src/nucleo-f4x1re.h @@ -309,15 +309,15 @@ void stm32_spidev_initialize(void); void stm32_usbinitialize(void); /************************************************************************************ - * Name: board_adc_initialize + * Name: stm32_adc_setup * * Description: - * Initialize and register the ADC driver(s) + * Initialize ADC and register the ADC driver. * ************************************************************************************/ #ifdef CONFIG_ADC -int board_adc_initialize(void); +int stm32_adc_setup(void); #endif /**************************************************************************** diff --git a/configs/nucleo-f4x1re/src/stm32_adc.c b/configs/nucleo-f4x1re/src/stm32_adc.c index 3b55e7ef7d..e4fb1c7f6e 100644 --- a/configs/nucleo-f4x1re/src/stm32_adc.c +++ b/configs/nucleo-f4x1re/src/stm32_adc.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/nucleo-f4x1re/src/stm32_adc.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -71,7 +71,6 @@ ************************************************************************************/ /* Identifying number of each ADC channel. */ -#ifdef CONFIG_STM32_ADC1 #ifdef CONFIG_AJOYSTICK #ifdef CONFIG_ADC_DMA /* The Itead analog joystick gets inputs on ADC_IN0 and ADC_IN1 */ @@ -95,87 +94,51 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN0}; #endif /* CONFIG_ADC_DMA */ #endif /* CONFIG_AJOYSTICK */ -#endif /* CONFIG_STM32_ADC1*/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_adc_initialize + * Name: stm32_adc_setup * * Description: - * Initialize and register the ADC driver + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -int board_adc_initialize(void) +int stm32_adc_setup(void) { - static bool initialized = false; struct adc_dev_s *adc; int ret; int i; - /* Check if we have already initialized */ + /* Configure the pins as analog inputs for the selected channels */ - if (!initialized) + for (i = 0; i < ADC1_NCHANNELS; i++) { -#ifdef CONFIG_STM32_ADC1 - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_adc1_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } -#endif - /* Now we are initialized */ + stm32_configgpio(g_adc1_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - initialized = true; + adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; } - return OK; -} + /* Register the ADC driver at "/dev/adc0" */ -/************************************************************************************ - * Name: board_adc_setup - * - * Description: - * All STM32 architectures must provide the following interface to work with - * examples/adc. - * - ************************************************************************************/ + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } -#ifdef CONFIG_EXAMPLES_ADC -int board_adc_setup(void) -{ -#ifdef CONFIG_SAMA5_ADC - return board_adc_initialize(); -#else - return -ENOSYS; -#endif + return OK; } -#endif /* CONFIG_EXAMPLES_ADC */ #endif /* CONFIG_STM32_ADC1 */ diff --git a/configs/nucleo-f4x1re/src/stm32_ajoystick.c b/configs/nucleo-f4x1re/src/stm32_ajoystick.c index a40f08f4b0..7bc30b1d67 100644 --- a/configs/nucleo-f4x1re/src/stm32_ajoystick.c +++ b/configs/nucleo-f4x1re/src/stm32_ajoystick.c @@ -456,15 +456,7 @@ int board_ajoy_initialize(void) iinfo("Initialize ADC driver: /dev/adc0\n"); - /* Initialize ADC. We will need this to read the ADC inputs */ - - ret = board_adc_initialize(); - if (ret < 0) - { - ierr("ERROR: board_adc_initialize() failed: %d\n", ret); - return ret; - } - + /* NOTE: The ADC driver was initialized earlier in the bring-up sequence. */ /* Open the ADC driver for reading. */ fd = open("/dev/adc0", O_RDONLY); diff --git a/configs/nucleo-f4x1re/src/stm32_appinit.c b/configs/nucleo-f4x1re/src/stm32_appinit.c index a55f6a3c51..5845ad169f 100644 --- a/configs/nucleo-f4x1re/src/stm32_appinit.c +++ b/configs/nucleo-f4x1re/src/stm32_appinit.c @@ -139,6 +139,16 @@ int board_app_initialize(uintptr_t arg) syslog(LOG_INFO, "[boot] Initialized SDIO\n"); #endif +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + #ifdef CONFIG_QENCODER /* Initialize and register the qencoder driver */ diff --git a/configs/nucleo-l476rg/src/nucleo-l476rg.h b/configs/nucleo-l476rg/src/nucleo-l476rg.h index 60bf27c713..e82283b177 100644 --- a/configs/nucleo-l476rg/src/nucleo-l476rg.h +++ b/configs/nucleo-l476rg/src/nucleo-l476rg.h @@ -1,7 +1,7 @@ /************************************************************************************ * configs/nucleo-l476rg/src/nucleo-l476rg.h * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. * Authors: Frank Bennett * Gregory Nutt * Sebastien Lorquet @@ -340,15 +340,15 @@ int stm32_pwm_setup(void); #endif /************************************************************************************ - * Name: board_adc_initialize + * Name: stm32_adc_setup * * Description: - * Initialize and register the ADC driver(s) + * Initialize ADC and register the ADC driver. * ************************************************************************************/ #ifdef CONFIG_ADC -int board_adc_initialize(void); +int stm32_adc_setup(void); #endif /**************************************************************************** diff --git a/configs/nucleo-l476rg/src/stm32_adc.c b/configs/nucleo-l476rg/src/stm32_adc.c index 77ed219a31..7ca4b18ab0 100644 --- a/configs/nucleo-l476rg/src/stm32_adc.c +++ b/configs/nucleo-l476rg/src/stm32_adc.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/nucleo-l476rg/src/stm32_adc.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -71,7 +71,6 @@ ************************************************************************************/ /* Identifying number of each ADC channel. */ -#ifdef CONFIG_STM32_ADC1 #ifdef CONFIG_AJOYSTICK #ifdef CONFIG_ADC_DMA /* The Itead analog joystick gets inputs on ADC_IN0 and ADC_IN1 */ @@ -95,7 +94,6 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN0}; #endif /* CONFIG_ADC_DMA */ #endif /* CONFIG_AJOYSTICK */ -#endif /* CONFIG_STM32_ADC1*/ /************************************************************************************ * Private Functions @@ -106,76 +104,45 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN0}; ************************************************************************************/ /************************************************************************************ - * Name: board_adc_initialize + * Name: stm32_adc_setup * * Description: - * Initialize and register the ADC driver + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -int board_adc_initialize(void) +int stm32_adc_setup(void) { - static bool initialized = false; struct adc_dev_s *adc; int ret; int i; - /* Check if we have already initialized */ + /* Configure the pins as analog inputs for the selected channels */ - if (!initialized) + for (i = 0; i < ADC1_NCHANNELS; i++) { -#ifdef CONFIG_STM32_ADC1 - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_adc1_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } -#endif - /* Now we are initialized */ + stm32_configgpio(g_adc1_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - initialized = true; + adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; } - return OK; -} + /* Register the ADC driver at "/dev/adc0" */ -/************************************************************************************ - * Name: board_adc_setup - * - * Description: - * All STM32 architectures must provide the following interface to work with - * examples/adc. - * - ************************************************************************************/ + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } -#ifdef CONFIG_EXAMPLES_ADC -int board_adc_setup(void) -{ -#ifdef CONFIG_SAMA5_ADC - return board_adc_initialize(); -#else - return -ENOSYS; -#endif + return OK; } -#endif /* CONFIG_EXAMPLES_ADC */ #endif /* CONFIG_STM32_ADC1 */ diff --git a/configs/nucleo-l476rg/src/stm32_ajoystick.c b/configs/nucleo-l476rg/src/stm32_ajoystick.c index 71a61ef417..1fc72b5629 100644 --- a/configs/nucleo-l476rg/src/stm32_ajoystick.c +++ b/configs/nucleo-l476rg/src/stm32_ajoystick.c @@ -455,15 +455,7 @@ int board_ajoy_initialize(void) iinfo("Initialize ADC driver: /dev/adc0\n"); - /* Initialize ADC. We will need this to read the ADC inputs */ - - ret = board_adc_initialize(); - if (ret < 0) - { - ierr("ERROR: board_adc_initialize() failed: %d\n", ret); - return ret; - } - + /* NOTE: The ADC driver was initialized earlier in the bring-up sequence. */ /* Open the ADC driver for reading. */ fd = open("/dev/adc0", O_RDONLY); diff --git a/configs/nucleo-l476rg/src/stm32_appinit.c b/configs/nucleo-l476rg/src/stm32_appinit.c index 3505a2faaa..41b54976ae 100644 --- a/configs/nucleo-l476rg/src/stm32_appinit.c +++ b/configs/nucleo-l476rg/src/stm32_appinit.c @@ -120,9 +120,9 @@ int board_app_initialize(uintptr_t arg) (void)ret; +#ifdef CONFIG_SCHED_INSTRUMENTATION /* Configure CPU load estimation */ -#ifdef CONFIG_SCHED_INSTRUMENTATION cpuload_initialize_once(); #endif @@ -206,6 +206,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + #ifdef CONFIG_AJOYSTICK /* Initialize and register the joystick driver */ @@ -311,6 +321,8 @@ int board_app_initialize(uintptr_t arg) #endif #endif + + UNUSED(ret); return OK; } diff --git a/configs/olimex-stm32-e407/src/olimex-stm32-e407.h b/configs/olimex-stm32-e407/src/olimex-stm32-e407.h index cc3eff460d..72055c1d36 100644 --- a/configs/olimex-stm32-e407/src/olimex-stm32-e407.h +++ b/configs/olimex-stm32-e407/src/olimex-stm32-e407.h @@ -221,28 +221,28 @@ void weak_function stm32_usbinitialize(void); #endif -/**************************************************************************** - * Name: stm32_sdio_initialize +/************************************************************************************ + * Name: stm32_adc_setup * * Description: - * Initialize SDIO-based MMC/SD card support + * Initialize ADC and register the ADC driver. * - ****************************************************************************/ + ************************************************************************************/ -#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32_SDIO) -int stm32_sdio_initialize(void); +#ifdef CONFIG_ADC +int stm32_adc_setup(void); #endif /**************************************************************************** - * Name: stm32_adc_initialize + * Name: stm32_sdio_initialize * * Description: - * Called at application startup time to initialize the ADC functionality. + * Initialize SDIO-based MMC/SD card support * ****************************************************************************/ -#ifdef CONFIG_ADC -int stm32_adc_initialize(void); +#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32_SDIO) +int stm32_sdio_initialize(void); #endif /**************************************************************************** diff --git a/configs/olimex-stm32-e407/src/stm32_adc.c b/configs/olimex-stm32-e407/src/stm32_adc.c index 98ff8b85f3..c8b9682a12 100644 --- a/configs/olimex-stm32-e407/src/stm32_adc.c +++ b/configs/olimex-stm32-e407/src/stm32_adc.c @@ -114,28 +114,14 @@ static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN1}; ************************************************************************************/ /************************************************************************************ - * Name: board_adc_setup + * Name: stm32_adc_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/adc. + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -int board_adc_setup(void) -{ - return stm32_adc_initialize(); -} - -/************************************************************************************ - * Name: stm32_adc_initialize - * - * Description: - * Called at application startup time to initialize the ADC functionality. - * - ************************************************************************************/ - -int stm32_adc_initialize(void) +int stm32_adc_setup(void) { #ifdef CONFIG_STM32_ADC1 static bool initialized = false; diff --git a/configs/olimex-stm32-e407/src/stm32_appinit.c b/configs/olimex-stm32-e407/src/stm32_appinit.c index c7715a95b2..77023b153a 100644 --- a/configs/olimex-stm32-e407/src/stm32_appinit.c +++ b/configs/olimex-stm32-e407/src/stm32_appinit.c @@ -188,7 +188,6 @@ int board_app_initialize(uintptr_t arg) stm32_i2ctool(); - #ifdef CONFIG_CAN /* Configure on-board CAN if CAN support has been selected. */ @@ -200,12 +199,12 @@ int board_app_initialize(uintptr_t arg) #endif #ifdef CONFIG_ADC - /* Configure on-board ADCs if ADC support has been selected. */ + /* Initialize ADC and register the ADC driver. */ - ret = stm32_adc_initialize(); - if (ret != OK) + ret = stm32_adc_setup(); + if (ret < 0) { - syslog(LOG_ERR, "ERROR: Failed to initialize ADC: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); } #endif diff --git a/configs/olimex-stm32-h405/src/olimex-stm32-h405.h b/configs/olimex-stm32-h405/src/olimex-stm32-h405.h index 0ae22a4e2a..9ded4cfa69 100644 --- a/configs/olimex-stm32-h405/src/olimex-stm32-h405.h +++ b/configs/olimex-stm32-h405/src/olimex-stm32-h405.h @@ -89,15 +89,15 @@ void weak_function stm32_usbinitialize(void); #endif /************************************************************************************ - * Name: stm32_adc_initialize + * Name: stm32_adc_setup * * Description: - * Called at application startup time to initialize the ADC functionality. + * Initialize ADC and register the ADC driver. * ************************************************************************************/ #ifdef CONFIG_ADC -int stm32_adc_initialize(void); +int stm32_adc_setup(void); #endif /************************************************************************************ diff --git a/configs/olimex-stm32-h405/src/stm32_adc.c b/configs/olimex-stm32-h405/src/stm32_adc.c index f7cee47b8b..137ebf9561 100644 --- a/configs/olimex-stm32-h405/src/stm32_adc.c +++ b/configs/olimex-stm32-h405/src/stm32_adc.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/olimex-stm32-h405/src/stm32_adc.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -105,37 +105,19 @@ static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN1};/*, GPIO_ADC GPIO_ADC1_IN13, GPIO_ADC1_IN15};*/ #endif -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_adc_setup - * - * Description: - * All STM32 architectures must provide the following interface to work with - * examples/adc. - * - ************************************************************************************/ - -int board_adc_setup(void) -{ - return stm32_adc_initialize(); -} - -/************************************************************************************ - * Name: stm32_adc_initialize + * Name: stm32_adc_setup * * Description: - * Called at application startup time to initialize the ADC functionality. + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -int stm32_adc_initialize(void) +int stm32_adc_setup(void) { #ifdef CONFIG_STM32_ADC1 static bool initialized = false; diff --git a/configs/olimex-stm32-h405/src/stm32_appinit.c b/configs/olimex-stm32-h405/src/stm32_appinit.c index ed8b8fe846..4206d7c373 100644 --- a/configs/olimex-stm32-h405/src/stm32_appinit.c +++ b/configs/olimex-stm32-h405/src/stm32_appinit.c @@ -103,29 +103,28 @@ int board_app_initialize(uintptr_t arg) { -#if defined(CONFIG_CAN) || defined(CONFIG_ADC) int ret; -#endif -#ifdef CONFIG_CAN - /* Configure on-board CAN if CAN support has been selected. */ +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ - ret = stm32_can_initialize(); - if (ret != OK) + ret = stm32_adc_setup(); + if (ret < 0) { - syslog(LOG_ERR, "ERROR: Failed to initialize CAN: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); } #endif -#ifdef CONFIG_ADC - /* Configure on-board ADCs if ADC support has been selected. */ +#ifdef CONFIG_CAN + /* Configure on-board CAN if CAN support has been selected. */ - ret = stm32_adc_initialize(); + ret = stm32_can_initialize(); if (ret != OK) { - syslog(LOG_ERR, "ERROR: Failed to initialize ADC: %d\n", ret); + syslog(LOG_ERR, "ERROR: Failed to initialize CAN: %d\n", ret); } #endif + UNUSED(ret); return OK; } diff --git a/configs/olimex-stm32-h407/src/olimex-stm32-h407.h b/configs/olimex-stm32-h407/src/olimex-stm32-h407.h index 6687ef897a..51b051c6de 100644 --- a/configs/olimex-stm32-h407/src/olimex-stm32-h407.h +++ b/configs/olimex-stm32-h407/src/olimex-stm32-h407.h @@ -254,16 +254,16 @@ int stm32_sdio_initialize(void); void weak_function stm32_usbinitialize(void); #endif -/**************************************************************************** - * Name: stm32_adc_initialize +/************************************************************************************ + * Name: stm32_adc_setup * * Description: - * Called at application startup time to initialize the ADC functionality. + * Initialize ADC and register the ADC driver. * - ****************************************************************************/ + ************************************************************************************/ #ifdef CONFIG_ADC -int stm32_adc_initialize(void); +int stm32_adc_setup(void); #endif /**************************************************************************** diff --git a/configs/olimex-stm32-h407/src/stm32_adc.c b/configs/olimex-stm32-h407/src/stm32_adc.c index 9fa020954c..9282080a6b 100644 --- a/configs/olimex-stm32-h407/src/stm32_adc.c +++ b/configs/olimex-stm32-h407/src/stm32_adc.c @@ -105,37 +105,19 @@ static const uint8_t g_chanlist[ADC1_NCHANNELS] = {1}; static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN1}; #endif -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_adc_setup - * - * Description: - * All STM32 architectures must provide the following interface to work with - * examples/adc. - * - ************************************************************************************/ - -int board_adc_setup(void) -{ - return stm32_adc_initialize(); -} - -/************************************************************************************ - * Name: stm32_adc_initialize + * Name: stm32_adc_setup * * Description: - * Called at application startup time to initialize the ADC functionality. + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -int stm32_adc_initialize(void) +int stm32_adc_setup(void) { #ifdef CONFIG_STM32_ADC1 static bool initialized = false; diff --git a/configs/olimex-stm32-h407/src/stm32_bringup.c b/configs/olimex-stm32-h407/src/stm32_bringup.c index 73e29d5037..ba931c8a18 100644 --- a/configs/olimex-stm32-h407/src/stm32_bringup.c +++ b/configs/olimex-stm32-h407/src/stm32_bringup.c @@ -94,10 +94,7 @@ int stm32_bringup(void) #ifdef HAVE_RTC_DRIVER FAR struct rtc_lowerhalf_s *lower; #endif -#if defined(CONFIG_CAN) || defined(CONFIG_ADC) || defined(HAVE_SDIO) || \ - defined(HAVE_RTC_DRIVER) int ret; -#endif #ifdef CONFIG_CAN /* Configure on-board CAN if CAN support has been selected. */ @@ -112,14 +109,12 @@ int stm32_bringup(void) #endif #ifdef CONFIG_ADC - /* Configure on-board ADCs if ADC support has been selected. */ + /* Initialize ADC and register the ADC driver. */ - ret = stm32_adc_initialize(); - if (ret != OK) + ret = stm32_adc_setup(); + if (ret < 0) { - syslog(LOG_ERR, - "ERROR: Failed to initialize ADC: %d\n", - ret); + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); } #endif @@ -186,5 +181,6 @@ int stm32_bringup(void) } #endif + UNUSED(ret); return OK; } diff --git a/configs/olimex-stm32-p207/src/olimex-stm32-p207.h b/configs/olimex-stm32-p207/src/olimex-stm32-p207.h index 21f0d8ecfd..885d69e7ad 100644 --- a/configs/olimex-stm32-p207/src/olimex-stm32-p207.h +++ b/configs/olimex-stm32-p207/src/olimex-stm32-p207.h @@ -125,15 +125,15 @@ int stm32_usbhost_initialize(void); #endif /************************************************************************************ - * Name: stm32_adc_initialize + * Name: stm32_adc_setup * * Description: - * Called at application startup time to initialize the ADC functionality. + * Initialize ADC and register the ADC driver. * ************************************************************************************/ #ifdef CONFIG_ADC -int stm32_adc_initialize(void); +int stm32_adc_setup(void); #endif /************************************************************************************ diff --git a/configs/olimex-stm32-p207/src/stm32_adc.c b/configs/olimex-stm32-p207/src/stm32_adc.c index 75a451176a..ef7858ccbb 100644 --- a/configs/olimex-stm32-p207/src/stm32_adc.c +++ b/configs/olimex-stm32-p207/src/stm32_adc.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/olimex-stm32-p207/src/stm32_adc.c * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -97,37 +97,19 @@ static const uint8_t g_chanlist[ADC1_NCHANNELS] = {10}; static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN10}; #endif -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_adc_setup - * - * Description: - * All STM32 architectures must provide the following interface to work with - * examples/adc. - * - ************************************************************************************/ - -int board_adc_setup(void) -{ - return stm32_adc_initialize(); -} - -/************************************************************************************ - * Name: stm32_adc_initialize + * Name: stm32_adc_setup * * Description: - * Called at application startup time to initialize the ADC functionality. + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -int stm32_adc_initialize(void) +int stm32_adc_setup(void) { #ifdef CONFIG_STM32_ADC1 static bool initialized = false; diff --git a/configs/olimex-stm32-p207/src/stm32_appinit.c b/configs/olimex-stm32-p207/src/stm32_appinit.c index fa3fce23f2..8941d109aa 100644 --- a/configs/olimex-stm32-p207/src/stm32_appinit.c +++ b/configs/olimex-stm32-p207/src/stm32_appinit.c @@ -132,9 +132,7 @@ int board_app_initialize(uintptr_t arg) { -#if defined(HAVE_USBHOST) || defined(HAVE_USBMONITOR) || defined(CONFIG_ADC) int ret; -#endif #if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) /* Configure on-board CAN if CAN support has been selected. */ @@ -147,12 +145,12 @@ int board_app_initialize(uintptr_t arg) #endif #ifdef CONFIG_ADC - /* Configure on-board ADCs if ADC support has been selected. */ + /* Initialize ADC and register the ADC driver. */ - ret = stm32_adc_initialize(); - if (ret != OK) + ret = stm32_adc_setup(); + if (ret < 0) { - syslog(LOG_ERR, "ERROR: Failed to initialize ADC: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); } #endif @@ -179,5 +177,6 @@ int board_app_initialize(uintptr_t arg) } #endif + UNUSED(ret); return OK; } diff --git a/configs/sama5d3-xplained/src/sam_adc.c b/configs/sama5d3-xplained/src/sam_adc.c index 797dbe182e..9ef01d875e 100644 --- a/configs/sama5d3-xplained/src/sam_adc.c +++ b/configs/sama5d3-xplained/src/sam_adc.c @@ -48,32 +48,21 @@ #include "sam_adc.h" #include "sama5d3-xplained.h" -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Data - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ +#ifdef CONFIG_SAMA5_ADC /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_adc_initialize + * Name: sam_adc_setup * * Description: - * Initialize and register the ADC driver + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -#ifdef CONFIG_SAMA5_ADC -int board_adc_initialize(void) +int sam_adc_setup(void) { static bool initialized = false; struct adc_dev_s *adc; @@ -108,24 +97,5 @@ int board_adc_initialize(void) return OK; } -#endif /* CONFIG_ADC */ -/************************************************************************************ - * Name: board_adc_setup - * - * Description: - * All SAMA5 architectures must provide the following interface to work with - * examples/adc. - * - ************************************************************************************/ - -#ifdef CONFIG_EXAMPLES_ADC -int board_adc_setup(void) -{ -#ifdef CONFIG_SAMA5_ADC - return board_adc_initialize(); -#else - return -ENOSYS; -#endif -} -#endif /* CONFIG_EXAMPLES_ADC */ +#endif /* CONFIG_ADC */ diff --git a/configs/sama5d3-xplained/src/sam_ajoystick.c b/configs/sama5d3-xplained/src/sam_ajoystick.c index 7ff2f02195..a4712eabf8 100644 --- a/configs/sama5d3-xplained/src/sam_ajoystick.c +++ b/configs/sama5d3-xplained/src/sam_ajoystick.c @@ -406,15 +406,7 @@ int sam_ajoy_initialization(void) int fd; int i; - /* Initialize ADC. We will need this to read the ADC inputs */ - - ret = board_adc_initialize(); - if (ret < 0) - { - ierr("ERROR: board_adc_initialize() failed: %d\n", ret); - return ret; - } - + /* NOTE: The ADC driver was initialized earlier in the bring-up sequence. */ /* Open the ADC driver for reading. */ fd = open("/dev/adc0", O_RDONLY); diff --git a/configs/sama5d3-xplained/src/sam_appinit.c b/configs/sama5d3-xplained/src/sam_appinit.c index 3001cf4774..8b80cb994c 100644 --- a/configs/sama5d3-xplained/src/sam_appinit.c +++ b/configs/sama5d3-xplained/src/sam_appinit.c @@ -158,6 +158,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = sam_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: sam_adc_setup failed: %d\n", ret); + } +#endif + #ifdef CONFIG_AJOYSTICK /* Initialize and register the joystick driver */ diff --git a/configs/sama5d3-xplained/src/sama5d3-xplained.h b/configs/sama5d3-xplained/src/sama5d3-xplained.h index 18b8956907..f0509ce5fc 100644 --- a/configs/sama5d3-xplained/src/sama5d3-xplained.h +++ b/configs/sama5d3-xplained/src/sama5d3-xplained.h @@ -752,27 +752,27 @@ int sam_pwm_setup(void); #endif /************************************************************************************ - * Name: sam_netinitialize + * Name: sam_adc_setup * * Description: - * Configure board resources to support networking. + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -#ifdef HAVE_NETWORK -void weak_function sam_netinitialize(void); +#ifdef CONFIG_ADC +int sam_adc_setup(void); #endif /************************************************************************************ - * Name: board_adc_initialize + * Name: sam_netinitialize * * Description: - * Initialize and register the ADC driver + * Configure board resources to support networking. * ************************************************************************************/ -#ifdef CONFIG_SAMA5_ADC -int board_adc_initialize(void); +#ifdef HAVE_NETWORK +void weak_function sam_netinitialize(void); #endif #endif /* __ASSEMBLY__ */ diff --git a/configs/sama5d3x-ek/src/sam_adc.c b/configs/sama5d3x-ek/src/sam_adc.c index 2600ffd098..50982fb41c 100644 --- a/configs/sama5d3x-ek/src/sam_adc.c +++ b/configs/sama5d3x-ek/src/sam_adc.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/sama5d3x-ek/src/sam_adc.c * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -50,33 +50,19 @@ #ifdef CONFIG_ADC -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ - -/************************************************************************************ - * Private Data - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_adc_setup + * Name: sam_adc_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/adc. + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -int board_adc_setup(void) +int sam_adc_setup(void) { #ifdef CONFIG_SAMA5_ADC static bool initialized = false; diff --git a/configs/sama5d3x-ek/src/sam_appinit.c b/configs/sama5d3x-ek/src/sam_appinit.c index aee55a41a4..0b56f3cea3 100644 --- a/configs/sama5d3x-ek/src/sam_appinit.c +++ b/configs/sama5d3x-ek/src/sam_appinit.c @@ -194,6 +194,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = sam_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: sam_adc_setup failed: %d\n", ret); + } +#endif + #ifdef CONFIG_FS_PROCFS /* Mount the procfs file system */ diff --git a/configs/sama5d3x-ek/src/sama5d3x-ek.h b/configs/sama5d3x-ek/src/sama5d3x-ek.h index 5b1575fc3e..fd80daf7e8 100644 --- a/configs/sama5d3x-ek/src/sama5d3x-ek.h +++ b/configs/sama5d3x-ek/src/sama5d3x-ek.h @@ -844,6 +844,18 @@ void weak_function sam_netinitialize(void); int sam_pwm_setup(void); #endif +/************************************************************************************ + * Name: sam_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_ADC +int sam_adc_setup(void); +#endif + /**************************************************************************** * Name: sam_wm8904_initialize * diff --git a/configs/sama5d4-ek/src/sam_adc.c b/configs/sama5d4-ek/src/sam_adc.c index 762caccd20..031eb6673d 100644 --- a/configs/sama5d4-ek/src/sam_adc.c +++ b/configs/sama5d4-ek/src/sam_adc.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/sama5d4-ek/src/sam_adc.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -50,32 +50,19 @@ #ifdef CONFIG_ADC -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Data - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_adc_setup + * Name: sam_adc_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/adc. + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -int board_adc_setup(void) +int sam_adc_setup(void) { #ifdef CONFIG_SAMA5_ADC static bool initialized = false; diff --git a/configs/sama5d4-ek/src/sam_bringup.c b/configs/sama5d4-ek/src/sam_bringup.c index 272e9251de..5669b17fc7 100644 --- a/configs/sama5d4-ek/src/sam_bringup.c +++ b/configs/sama5d4-ek/src/sam_bringup.c @@ -298,6 +298,16 @@ int sam_bringup(void) } #endif +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = sam_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: sam_adc_setup failed: %d\n", ret); + } +#endif + #ifdef HAVE_WM8904 /* Configure WM8904 audio */ diff --git a/configs/sama5d4-ek/src/sama5d4-ek.h b/configs/sama5d4-ek/src/sama5d4-ek.h index c4ebca971b..4bf4031976 100644 --- a/configs/sama5d4-ek/src/sama5d4-ek.h +++ b/configs/sama5d4-ek/src/sama5d4-ek.h @@ -1085,6 +1085,18 @@ int sam_usbhost_initialize(void); int sam_pwm_setup(void); #endif +/************************************************************************************ + * Name: sam_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_ADC +int sam_adc_setup(void); +#endif + /************************************************************************************ * Name: sam_netinitialize * diff --git a/configs/shenzhou/src/shenzhou.h b/configs/shenzhou/src/shenzhou.h index c66f333361..220a91ff4a 100644 --- a/configs/shenzhou/src/shenzhou.h +++ b/configs/shenzhou/src/shenzhou.h @@ -448,6 +448,18 @@ void weak_function stm32_usbinitialize(void); int stm32_usbhost_initialize(void); #endif +/************************************************************************************ + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_ADC +int stm32_adc_setup(void); +#endif + /**************************************************************************** * Name: stm32_sdinitialize * diff --git a/configs/shenzhou/src/stm32_adc.c b/configs/shenzhou/src/stm32_adc.c index 0b61b68f8e..3e185bcdf5 100644 --- a/configs/shenzhou/src/stm32_adc.c +++ b/configs/shenzhou/src/stm32_adc.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/shenzhou/src/stm32_adc.c * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -104,24 +104,19 @@ static const uint8_t g_chanlist[ADC1_NCHANNELS] = {10}; //{10, 8, 9}; static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC12_IN10}; //{GPIO_ADC12_IN10, GPIO_ADC12_IN8, GPIO_ADC12_IN9}; #endif -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_adc_setup + * Name: stm32_adc_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/adc. + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -int board_adc_setup(void) +int stm32_adc_setup(void) { #ifdef CONFIG_STM32_ADC1 static bool initialized = false; diff --git a/configs/shenzhou/src/stm32_appinit.c b/configs/shenzhou/src/stm32_appinit.c index 9b18c80d5d..0ef1e05bcd 100644 --- a/configs/shenzhou/src/stm32_appinit.c +++ b/configs/shenzhou/src/stm32_appinit.c @@ -165,9 +165,7 @@ int board_app_initialize(uintptr_t arg) { -#if defined(HAVE_MMCSD) || defined(HAVE_USBHOST) || defined(HAVE_W25) int ret; -#endif /* Initialize and register the W25 FLASH file system. */ @@ -206,5 +204,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); return OK; } diff --git a/configs/stm3210e-eval/src/stm3210e-eval.h b/configs/stm3210e-eval/src/stm3210e-eval.h index aa129bf9ce..368e12c0d0 100644 --- a/configs/stm3210e-eval/src/stm3210e-eval.h +++ b/configs/stm3210e-eval/src/stm3210e-eval.h @@ -192,6 +192,18 @@ void weak_function stm32_spidev_initialize(void); void weak_function stm32_usbinitialize(void); +/************************************************************************************ + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_ADC +int stm32_adc_setup(void); +#endif + /************************************************************************************ * Name: stm32_extcontextsave * diff --git a/configs/stm3210e-eval/src/stm32_adc.c b/configs/stm3210e-eval/src/stm32_adc.c index a0c5b87fa3..bb92bf9e93 100644 --- a/configs/stm3210e-eval/src/stm32_adc.c +++ b/configs/stm3210e-eval/src/stm32_adc.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/stm3210e-eval/src/stm32_adc.c * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -95,24 +95,19 @@ static const uint8_t g_chanlist[ADC1_NCHANNELS] = {14}; static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN14}; #endif -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_adc_setup + * Name: stm32_adc_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/adc. + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -int board_adc_setup(void) +int stm32_adc_setup(void) { #ifdef CONFIG_STM32_ADC1 static bool initialized = false; diff --git a/configs/stm3210e-eval/src/stm32_appinit.c b/configs/stm3210e-eval/src/stm32_appinit.c index 10d617c0da..338b108aaf 100644 --- a/configs/stm3210e-eval/src/stm32_appinit.c +++ b/configs/stm3210e-eval/src/stm32_appinit.c @@ -206,9 +206,7 @@ int board_app_initialize(uintptr_t arg) #ifdef NSH_HAVEMMCSD FAR struct sdio_dev_s *sdio; #endif -#if defined(NSH_HAVEMMCSD) || defined(CONFIG_DJOYSTICK) int ret; -#endif /* Register I2C drivers on behalf of the I2C tool */ @@ -286,6 +284,16 @@ int board_app_initialize(uintptr_t arg) sdio_mediachange(sdio, true); #endif +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + #ifdef CONFIG_DJOYSTICK /* Initialize and register the joystick driver */ @@ -299,5 +307,6 @@ int board_app_initialize(uintptr_t arg) syslog(LOG_INFO, "Successfully registered the joystick driver\n"); #endif + UNUSED(ret); return OK; } diff --git a/configs/stm3220g-eval/src/stm3220g-eval.h b/configs/stm3220g-eval/src/stm3220g-eval.h index b15be6fd8f..4cea9d2d4d 100644 --- a/configs/stm3220g-eval/src/stm3220g-eval.h +++ b/configs/stm3220g-eval/src/stm3220g-eval.h @@ -261,6 +261,18 @@ int stm32_usbhost_initialize(void); int stm32_pwm_setup(void); #endif +/************************************************************************************ + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_ADC +int stm32_adc_setup(void); +#endif + /**************************************************************************************************** * Name: stm32_extmemgpios * diff --git a/configs/stm3220g-eval/src/stm32_adc.c b/configs/stm3220g-eval/src/stm32_adc.c index 9db71d0bd0..e020101a01 100644 --- a/configs/stm3220g-eval/src/stm32_adc.c +++ b/configs/stm3220g-eval/src/stm32_adc.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/stm3220g-eval/src/stm32_adc.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -99,24 +99,19 @@ static const uint8_t g_chanlist[ADC3_NCHANNELS] = {7}; static const uint32_t g_pinlist[ADC3_NCHANNELS] = {GPIO_ADC3_IN7}; #endif -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_adc_setup + * Name: stm32_adc_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/adc. + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -int board_adc_setup(void) +int stm32_adc_setup(void) { #ifdef CONFIG_STM32_ADC3 static bool initialized = false; diff --git a/configs/stm3220g-eval/src/stm32_appinit.c b/configs/stm3220g-eval/src/stm32_appinit.c index bcc176f4a1..8644f579d4 100644 --- a/configs/stm3220g-eval/src/stm32_appinit.c +++ b/configs/stm3220g-eval/src/stm32_appinit.c @@ -219,9 +219,7 @@ int board_app_initialize(uintptr_t arg) #ifdef HAVE_MMCSD FAR struct sdio_dev_s *sdio; #endif -#if defined(HAVE_MMCSD) || defined (HAVE_USBHOST) int ret; -#endif /* Register I2C drivers on behalf of the I2C tool */ @@ -304,5 +302,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); return OK; } diff --git a/configs/stm3240g-eval/src/stm3240g-eval.h b/configs/stm3240g-eval/src/stm3240g-eval.h index acef27fc53..5da50bcfc9 100644 --- a/configs/stm3240g-eval/src/stm3240g-eval.h +++ b/configs/stm3240g-eval/src/stm3240g-eval.h @@ -274,6 +274,18 @@ void stm32_led_initialize(void); int stm32_pwm_setup(void); #endif +/************************************************************************************ + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_ADC +int stm32_adc_setup(void); +#endif + /**************************************************************************************************** * Name: stm32_extmemgpios * diff --git a/configs/stm3240g-eval/src/stm32_adc.c b/configs/stm3240g-eval/src/stm32_adc.c index 1d78797043..82a5531edb 100644 --- a/configs/stm3240g-eval/src/stm32_adc.c +++ b/configs/stm3240g-eval/src/stm32_adc.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/stm3240g-eval/src/stm32_adc.c * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -99,24 +99,19 @@ static const uint8_t g_chanlist[ADC3_NCHANNELS] = {7}; static const uint32_t g_pinlist[ADC3_NCHANNELS] = {GPIO_ADC3_IN7}; #endif -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_adc_setup + * Name: stm32_adc_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/adc. + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -int board_adc_setup(void) +int stm32_adc_setup(void) { #ifdef CONFIG_STM32_ADC3 static bool initialized = false; diff --git a/configs/stm3240g-eval/src/stm32_appinit.c b/configs/stm3240g-eval/src/stm32_appinit.c index 6e8b94dffa..c926262e0a 100644 --- a/configs/stm3240g-eval/src/stm32_appinit.c +++ b/configs/stm3240g-eval/src/stm32_appinit.c @@ -240,9 +240,7 @@ int board_app_initialize(uintptr_t arg) #ifdef HAVE_MMCSD FAR struct sdio_dev_s *sdio; #endif -#if defined(HAVE_MMCSD) || defined(HAVE_USBHOST) || defined(HAVE_RTC_DRIVER) int ret; -#endif /* Register I2C drivers on behalf of the I2C tool */ @@ -355,5 +353,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); return OK; } diff --git a/configs/stm32butterfly2/src/stm32_adc.c b/configs/stm32butterfly2/src/stm32_adc.c index b75a4f01f2..eaac1722e7 100644 --- a/configs/stm32butterfly2/src/stm32_adc.c +++ b/configs/stm32butterfly2/src/stm32_adc.c @@ -46,14 +46,15 @@ * Public Functions ****************************************************************************/ -/***************************************************************************** - * Name: board_adc_setup +/************************************************************************************ + * Name: stm32_adc_setup * * Description: - * Function initializes channel 1 of adc1 and registers device as /dev/adc0 - ****************************************************************************/ + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ -int board_adc_setup(void) +int stm32_adc_setup(void) { static bool initialized = false; uint8_t channel[1] = {10}; diff --git a/configs/stm32butterfly2/src/stm32_boot.c b/configs/stm32butterfly2/src/stm32_boot.c index e77a6edffc..f42e7a7fd7 100644 --- a/configs/stm32butterfly2/src/stm32_boot.c +++ b/configs/stm32butterfly2/src/stm32_boot.c @@ -72,23 +72,36 @@ void stm32_boardinitialize(void) int board_app_initialize(uintptr_t arg) { - int rv = 0; + int ret = 0; #ifdef CONFIG_MMCSD - if ((rv = stm32_mmcsd_initialize(CONFIG_NSH_MMCSDMINOR)) < 0) + ret = stm32_mmcsd_initialize(CONFIG_NSH_MMCSDMINOR); + if (ret < 0) { - syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n"); - return rv; + syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", ret); + return ret; } #endif #ifdef CONFIG_USBHOST - if ((rv = stm32_usbhost_initialize()) < 0) + ret = stm32_usbhost_initialize(); + if (ret < 0) { - syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", rv); - return rv; + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + return ret; } #endif - return rv; +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return ret; } diff --git a/configs/stm32butterfly2/src/stm32_butterfly2.h b/configs/stm32butterfly2/src/stm32_butterfly2.h index d291a426a3..b309939d0d 100644 --- a/configs/stm32butterfly2/src/stm32_butterfly2.h +++ b/configs/stm32butterfly2/src/stm32_butterfly2.h @@ -127,5 +127,19 @@ int stm32_usbhost_initialize(void); static inline int stm32_usbhost_initialize(void) { return 0; } #endif +/************************************************************************************ + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_STM32_ADC +int stm32_adc_setup(void); +#else +static inline int stm32_adc_setup(void) { return 0; } +#endif + #endif /* __CONFIGS_STM32_BUTTERFLY2_SRC_STM32_BUTTERFLY2_H */ diff --git a/configs/stm32l476vg-disco/src/stm32l476vg-disco.h b/configs/stm32l476vg-disco/src/stm32l476vg-disco.h index 471a19d561..dfa9b4ebfa 100644 --- a/configs/stm32l476vg-disco/src/stm32l476vg-disco.h +++ b/configs/stm32l476vg-disco/src/stm32l476vg-disco.h @@ -272,16 +272,4 @@ void stm32_spiinitialize(void); void stm32l4_usbinitialize(void); -/************************************************************************************ - * Name: board_adc_initialize - * - * Description: - * Initialize and register the ADC driver(s) - * - ************************************************************************************/ - -#ifdef CONFIG_ADC -int board_adc_initialize(void); -#endif - #endif /* __CONFIGS_STM32L476VG_DISCO_SRC_STM32L476VG_DISCO_H */ diff --git a/configs/tm4c123g-launchpad/src/tm4c123g-launchpad.h b/configs/tm4c123g-launchpad/src/tm4c123g-launchpad.h index b9ca7ce480..4b8df2c9e1 100644 --- a/configs/tm4c123g-launchpad/src/tm4c123g-launchpad.h +++ b/configs/tm4c123g-launchpad/src/tm4c123g-launchpad.h @@ -1,7 +1,7 @@ /************************************************************************************ * configs/tm4c123g-launchpad/src/tm4c123g-launchpad.h * - * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2014-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -213,6 +213,18 @@ void tm4c_led_initialize(void); int tm4c_bringup(void); +/************************************************************************************ + * Name: tm4c_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_TIVA_ADC +int tm4c_adc_setup(void); +#endif + /**************************************************************************** * Name: tm4c_at24_automount * @@ -237,17 +249,5 @@ int tm4c_at24_automount(int minor); int tiva_timer_configure(void); #endif -/************************************************************************************ - * Name: board_adc_initialize - * - * Description: - * Initialize and register the ADC driver - * - ************************************************************************************/ - -#ifdef CONFIG_TIVA_ADC -int board_adc_initialize(void); -#endif - #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_TM4C123G_LAUNCHPAD_TM4C123G_LAUNCHPAD_H */ diff --git a/configs/tm4c123g-launchpad/src/tm4c_adc.c b/configs/tm4c123g-launchpad/src/tm4c_adc.c index c4494b5579..a43f5ee961 100644 --- a/configs/tm4c123g-launchpad/src/tm4c_adc.c +++ b/configs/tm4c123g-launchpad/src/tm4c_adc.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/tm4c123g-launchpad/tm4c_adc.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -50,34 +50,23 @@ #include "tm4c123g-launchpad.h" #include "chip/tiva_pinmap.h" -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Data - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ +#ifdef CONFIG_TIVA_ADC /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_adc_initialize + * Name: tm4c_adc_setup * * Description: - * Initialize and register the ADC driver. + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -#ifdef CONFIG_TIVA_ADC -int board_adc_initialize(void) +int tm4c_adc_setup(void) { -# if defined (CONFIG_TIVA_ADC) && defined (CONFIG_ADC) +#ifdef CONFIG_ADC static bool initialized = false; int ret; uint8_t srate = 0; @@ -90,11 +79,11 @@ int board_adc_initialize(void) }; sse_cfg0.priority = 0; -# ifdef CONFIG_EXAMPLES_ADC_SWTRIG +#ifdef CONFIG_EXAMPLES_ADC_SWTRIG sse_cfg0.trigger = TIVA_ADC_TRIG_SW; -# else +#else sse_cfg0.trigger = TIVA_ADC_TRIG_ALWAYS; -# endif +#endif adc_cfg.adc = 0; adc_cfg.sse[0] = true; @@ -105,11 +94,11 @@ int board_adc_initialize(void) adc_cfg.steps = 1; adc_cfg.stepcfg = step_cfg; -# ifdef CONFIG_EXAMPLES_ADC_SWTRIG +#ifdef CONFIG_EXAMPLES_ADC_SWTRIG srate = TIVA_ADC_SAMPLE_RATE_FASTEST; -# else +#else srate = TIVA_ADC_SAMPLE_RATE_SLOWEST; -# endif +#endif /* Check if we have already initialized */ @@ -132,35 +121,11 @@ int board_adc_initialize(void) initialized = true; } - return OK; -} #endif /* CONFIG_ADC */ -/************************************************************************************ - * Name: board_adc_setup - * - * Description: - * All Tiva architectures must provide the following interface to work with - * examples/adc. - * - ************************************************************************************/ - -#ifdef CONFIG_EXAMPLES_ADC -int board_adc_setup(void) -{ -#ifdef CONFIG_TIVA_ADC - return board_adc_initialize(); -#else - return -ENOSYS; -#endif + return OK; } -#endif /* CONFIG_EXAMPLES_ADC */ - -#if defined (CONFIG_TIVA_ADC) && defined (CONFIG_TIVA_TIMER) - -/* Tiva timer interface does not currently support user configuration */ -#if 0 /************************************************************************************ * Name: adc_timer_init * @@ -169,6 +134,9 @@ int board_adc_setup(void) * ************************************************************************************/ +/* Tiva timer interface does not currently support user configuration */ + +#if 0 /* defined(CONFIG_TIVA_TIMER) */ TIMER_HANDLE adc_timer_init(void) { struct tiva_gptm32config_s adctimer = @@ -189,6 +157,6 @@ TIMER_HANDLE adc_timer_init(void) return tiva_gptm_configure((const struct tiva_gptmconfig_s *)&adctimer); } +#endif /* CONFIG_TIVA_TIMER */ -#endif -#endif /* defined (CONFIG_TIVA_ADC) && defined (CONFIG_TIVA_TIMER) */ +#endif /* CONFIG_TIVA_ADC */ diff --git a/configs/tm4c123g-launchpad/src/tm4c_bringup.c b/configs/tm4c123g-launchpad/src/tm4c_bringup.c index 48a8d649fe..d70b9156ba 100644 --- a/configs/tm4c123g-launchpad/src/tm4c_bringup.c +++ b/configs/tm4c123g-launchpad/src/tm4c_bringup.c @@ -1,7 +1,7 @@ /**************************************************************************** * config/tm4c123g-launchpad/src/tm4c_bringup.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -63,6 +63,16 @@ int tm4c_bringup(void) { int ret = OK; +#ifdef CONFIG_TIVA_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = tm4c_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: tm4c_adc_setup failed: %d\n", ret); + } +#endif + #ifdef HAVE_AT24 /* Initialize the AT24 driver */ @@ -85,5 +95,6 @@ int tm4c_bringup(void) } #endif /* CONFIG_TIVA_TIMER */ + UNUSED(ret); return ret; } diff --git a/configs/u-blox-c027/src/Makefile b/configs/u-blox-c027/src/Makefile index e7a301c813..e76c00febd 100644 --- a/configs/u-blox-c027/src/Makefile +++ b/configs/u-blox-c027/src/Makefile @@ -36,7 +36,7 @@ -include $(TOPDIR)/Make.defs ASRCS = -CSRCS = lpc17_boot.c lpc17_leds.c lpc17_ssp.c lpc17_adc.c lpc17_dac.c +CSRCS = lpc17_boot.c lpc17_leds.c lpc17_ssp.c lpc17_dac.c ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += lpc17_appinit.c @@ -46,6 +46,10 @@ ifeq ($(CONFIG_PWM),y) CSRCS += lpc17_pwm.c endif +ifeq ($(CONFIG_ADC),y) +CSRCS += lpc17_adc.c +endif + ifeq ($(CONFIG_MODEM_U_BLOX),y) CSRCS += lpc17_ubxmdm.c endif diff --git a/configs/u-blox-c027/src/lpc17_adc.c b/configs/u-blox-c027/src/lpc17_adc.c index bc876a8d53..0321cda7e7 100644 --- a/configs/u-blox-c027/src/lpc17_adc.c +++ b/configs/u-blox-c027/src/lpc17_adc.c @@ -8,7 +8,7 @@ * * which, in turn, was based on configs/stm3220g-eval/src/lpc17_adc.c * - * Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -66,15 +66,14 @@ ************************************************************************************/ /************************************************************************************ - * Name: board_adc_setup + * Name: lpc17_adc_setup * * Description: - * All LPC17 architectures must provide the following interface to work with - * examples/adc. + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -int board_adc_setup(void) +int lpc17_adc_setup(void) { static bool initialized = false; struct adc_dev_s *adc; diff --git a/configs/u-blox-c027/src/lpc17_appinit.c b/configs/u-blox-c027/src/lpc17_appinit.c index 78b92d7004..30c6d27161 100644 --- a/configs/u-blox-c027/src/lpc17_appinit.c +++ b/configs/u-blox-c027/src/lpc17_appinit.c @@ -207,6 +207,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = lpc17_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: lpc17_adc_setup failed: %d\n", ret); + } +#endif + UNUSED(ret); return OK; } diff --git a/configs/u-blox-c027/src/u-blox-c027.h b/configs/u-blox-c027/src/u-blox-c027.h index c277eeeb50..edeb43dbe1 100644 --- a/configs/u-blox-c027/src/u-blox-c027.h +++ b/configs/u-blox-c027/src/u-blox-c027.h @@ -114,5 +114,17 @@ void lpc17_ubxmdm_init(bool usb_used); int lpc17_pwm_setup(void); #endif +/************************************************************************************ + * Name: lpc17_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_ADC +int lpc17_adc_setup(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_U_BLOX_C027_SRC_U_BLOX_C027_H */ diff --git a/configs/zkit-arm-1769/src/Makefile b/configs/zkit-arm-1769/src/Makefile index 80905b8853..9e1a628a18 100644 --- a/configs/zkit-arm-1769/src/Makefile +++ b/configs/zkit-arm-1769/src/Makefile @@ -6,7 +6,7 @@ # # Based on configs/lpcxpresso-lpc1768/src/Makefile # -# Copyright (C) 2011 Gregory Nutt. All rights reserved. +# Copyright (C) 201, 2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without diff --git a/configs/zkit-arm-1769/src/lpc17_adc.c b/configs/zkit-arm-1769/src/lpc17_adc.c index 3d3628ea9c..207aa83f82 100644 --- a/configs/zkit-arm-1769/src/lpc17_adc.c +++ b/configs/zkit-arm-1769/src/lpc17_adc.c @@ -6,7 +6,7 @@ * * Based on configs/stm3220g-eval/src/lpc17_adc.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -76,15 +76,14 @@ ************************************************************************************/ /************************************************************************************ - * Name: board_adc_setup + * Name: zkit_adc_setup * * Description: - * All LPC17 architectures must provide the following interface to work with - * examples/adc. + * Initialize ADC and register the ADC driver. * ************************************************************************************/ -int board_adc_setup(void) +int zkit_adc_setup(void) { static bool initialized = false; struct adc_dev_s *adc; diff --git a/configs/zkit-arm-1769/src/lpc17_appinit.c b/configs/zkit-arm-1769/src/lpc17_appinit.c index 3854e0d1c4..673c3b6ca0 100644 --- a/configs/zkit-arm-1769/src/lpc17_appinit.c +++ b/configs/zkit-arm-1769/src/lpc17_appinit.c @@ -6,7 +6,7 @@ * * Based on config/lpcxpresso-lpc1768/src/lpc17_appinit.c * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -160,9 +160,10 @@ int board_app_initialize(uintptr_t arg) { + int ret; + #ifdef CONFIG_NSH_HAVEMMCSD FAR struct spi_dev_s *spi; - int ret; /* Get the SPI port */ @@ -190,5 +191,17 @@ int board_app_initialize(uintptr_t arg) message("Successfuly bound SPI port %d to MMC/SD slot %d\n", CONFIG_NSH_MMCSDSPIPORTNO, CONFIG_NSH_MMCSDSLOTNO); #endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = zkit_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: zkit_adc_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); return OK; } diff --git a/configs/zkit-arm-1769/src/zkit-arm-1769.h b/configs/zkit-arm-1769/src/zkit-arm-1769.h index 84de2d3cb2..2ebaf011c8 100644 --- a/configs/zkit-arm-1769/src/zkit-arm-1769.h +++ b/configs/zkit-arm-1769/src/zkit-arm-1769.h @@ -6,7 +6,7 @@ * * Based on configs/lpcxpresso-lpc1768/src/lpcxpresso.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -249,5 +249,17 @@ void weak_function zkit_sspdev_initialize(void); void weak_function zkit_spidev_initialize(void); +/************************************************************************************ + * Name: zkit_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_ADC +int zkit_adc_setup(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* _CONFIGS_ZKITARM_LPC1768_SRC_ZKITARM_H */ -- GitLab From d829c03656fb67b5235e7e0c08ec84b8938832f2 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 5 Dec 2016 17:24:25 -0600 Subject: [PATCH 606/734] Corrects some warnings and link problems introduced in the last big commits. --- configs/bambino-200e/src/lpc43_appinit.c | 2 +- configs/mikroe-stm32f4/src/stm32_pwm.c | 7 ++++--- configs/stm32f103-minimum/src/stm32_pwm.c | 7 ++++--- configs/stm32f3discovery/src/stm32_pwm.c | 7 ++++--- configs/stm32f4discovery/src/stm32_pwm.c | 8 ++++---- configs/stm32ldiscovery/src/stm32_pwm.c | 7 ++++--- 6 files changed, 21 insertions(+), 17 deletions(-) diff --git a/configs/bambino-200e/src/lpc43_appinit.c b/configs/bambino-200e/src/lpc43_appinit.c index f69023a4fe..785c28758b 100644 --- a/configs/bambino-200e/src/lpc43_appinit.c +++ b/configs/bambino-200e/src/lpc43_appinit.c @@ -164,7 +164,7 @@ int board_app_initialize(uintptr_t arg) { /* Initialize the SPIFI block device */ - nsh_spifi_initialize(); + (void)nsh_spifi_initialize(); #ifdef CONFIG_TIMER /* Registers the timers */ diff --git a/configs/mikroe-stm32f4/src/stm32_pwm.c b/configs/mikroe-stm32f4/src/stm32_pwm.c index a4bb122a45..bad3819dd0 100644 --- a/configs/mikroe-stm32f4/src/stm32_pwm.c +++ b/configs/mikroe-stm32f4/src/stm32_pwm.c @@ -85,8 +85,6 @@ # undef HAVE_PWM #endif -#ifdef HAVE_PWM - /************************************************************************************ * Public Functions ************************************************************************************/ @@ -101,6 +99,7 @@ int stm32_pwm_setup(void) { +#ifdef HAVE_PWM static bool initialized = false; struct pwm_lowerhalf_s *pwm; int ret; @@ -133,6 +132,8 @@ int stm32_pwm_setup(void) } return OK; +#else + return -ENOSYS; +#endif } -#endif /* HAVE_PWM */ diff --git a/configs/stm32f103-minimum/src/stm32_pwm.c b/configs/stm32f103-minimum/src/stm32_pwm.c index c3e64baf7b..8f7e99f839 100644 --- a/configs/stm32f103-minimum/src/stm32_pwm.c +++ b/configs/stm32f103-minimum/src/stm32_pwm.c @@ -85,8 +85,6 @@ # undef HAVE_PWM #endif -#ifdef HAVE_PWM - /************************************************************************************ * Public Functions ************************************************************************************/ @@ -101,6 +99,7 @@ int stm32_pwm_setup(void) { +#ifdef HAVE_PWM static bool initialized = false; struct pwm_lowerhalf_s *pwm; int ret; @@ -133,6 +132,8 @@ int stm32_pwm_setup(void) } return OK; +#else + return -ENOSYS; +#endif } -#endif /* HAVE_PWM */ diff --git a/configs/stm32f3discovery/src/stm32_pwm.c b/configs/stm32f3discovery/src/stm32_pwm.c index e31a2e62fc..5eb075c51d 100644 --- a/configs/stm32f3discovery/src/stm32_pwm.c +++ b/configs/stm32f3discovery/src/stm32_pwm.c @@ -85,8 +85,6 @@ # undef HAVE_PWM #endif -#ifdef HAVE_PWM - /************************************************************************************ * Public Functions ************************************************************************************/ @@ -101,6 +99,7 @@ int stm32_pwm_setup(void) { +#ifdef HAVE_PWM static bool initialized = false; struct pwm_lowerhalf_s *pwm; int ret; @@ -133,6 +132,8 @@ int stm32_pwm_setup(void) } return OK; +#else + return -ENOSYS; +#endif } -#endif /* HAVE_PWM */ diff --git a/configs/stm32f4discovery/src/stm32_pwm.c b/configs/stm32f4discovery/src/stm32_pwm.c index e8565b8fd0..0eaefc9371 100644 --- a/configs/stm32f4discovery/src/stm32_pwm.c +++ b/configs/stm32f4discovery/src/stm32_pwm.c @@ -83,8 +83,6 @@ # undef HAVE_PWM #endif -#ifdef HAVE_PWM - /************************************************************************************ * Public Functions ************************************************************************************/ @@ -99,6 +97,7 @@ int stm32_pwm_setup(void) { +#ifdef HAVE_PWM static bool initialized = false; struct pwm_lowerhalf_s *pwm; int ret; @@ -131,6 +130,7 @@ int stm32_pwm_setup(void) } return OK; +#else + return -ENOSYS; +#endif } - -#endif /* HAVE_PWM */ diff --git a/configs/stm32ldiscovery/src/stm32_pwm.c b/configs/stm32ldiscovery/src/stm32_pwm.c index 6e2753cf9d..3409fccc8e 100644 --- a/configs/stm32ldiscovery/src/stm32_pwm.c +++ b/configs/stm32ldiscovery/src/stm32_pwm.c @@ -85,8 +85,6 @@ # undef HAVE_PWM #endif -#ifdef HAVE_PWM - /************************************************************************************ * Public Functions ************************************************************************************/ @@ -101,6 +99,7 @@ int stm32_pwm_setup(void) { +#ifdef HAVE_PWM static bool initialized = false; struct pwm_lowerhalf_s *pwm; int ret; @@ -133,6 +132,8 @@ int stm32_pwm_setup(void) } return OK; +#else + return -ENOSYS; +#endif } -#endif /* HAVE_PWM */ -- GitLab From e5e54670973bbebe270abab046842dd651fe3443 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 5 Dec 2016 17:37:19 -0600 Subject: [PATCH 607/734] In last commit, ENODEV is a better error to report than ENOSYS. --- configs/mikroe-stm32f4/src/stm32_pwm.c | 2 +- configs/stm32f103-minimum/src/stm32_pwm.c | 2 +- configs/stm32f3discovery/src/stm32_pwm.c | 2 +- configs/stm32f4discovery/src/stm32_pwm.c | 2 +- configs/stm32ldiscovery/src/stm32_pwm.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/configs/mikroe-stm32f4/src/stm32_pwm.c b/configs/mikroe-stm32f4/src/stm32_pwm.c index bad3819dd0..2ef8d6c9e6 100644 --- a/configs/mikroe-stm32f4/src/stm32_pwm.c +++ b/configs/mikroe-stm32f4/src/stm32_pwm.c @@ -133,7 +133,7 @@ int stm32_pwm_setup(void) return OK; #else - return -ENOSYS; + return -ENODEV; #endif } diff --git a/configs/stm32f103-minimum/src/stm32_pwm.c b/configs/stm32f103-minimum/src/stm32_pwm.c index 8f7e99f839..5248e48921 100644 --- a/configs/stm32f103-minimum/src/stm32_pwm.c +++ b/configs/stm32f103-minimum/src/stm32_pwm.c @@ -133,7 +133,7 @@ int stm32_pwm_setup(void) return OK; #else - return -ENOSYS; + return -ENODEV; #endif } diff --git a/configs/stm32f3discovery/src/stm32_pwm.c b/configs/stm32f3discovery/src/stm32_pwm.c index 5eb075c51d..262c1bc851 100644 --- a/configs/stm32f3discovery/src/stm32_pwm.c +++ b/configs/stm32f3discovery/src/stm32_pwm.c @@ -133,7 +133,7 @@ int stm32_pwm_setup(void) return OK; #else - return -ENOSYS; + return -ENODEV; #endif } diff --git a/configs/stm32f4discovery/src/stm32_pwm.c b/configs/stm32f4discovery/src/stm32_pwm.c index 0eaefc9371..1b8468d2bb 100644 --- a/configs/stm32f4discovery/src/stm32_pwm.c +++ b/configs/stm32f4discovery/src/stm32_pwm.c @@ -131,6 +131,6 @@ int stm32_pwm_setup(void) return OK; #else - return -ENOSYS; + return -ENODEV; #endif } diff --git a/configs/stm32ldiscovery/src/stm32_pwm.c b/configs/stm32ldiscovery/src/stm32_pwm.c index 3409fccc8e..908307565c 100644 --- a/configs/stm32ldiscovery/src/stm32_pwm.c +++ b/configs/stm32ldiscovery/src/stm32_pwm.c @@ -133,7 +133,7 @@ int stm32_pwm_setup(void) return OK; #else - return -ENOSYS; + return -ENODEV; #endif } -- GitLab From 8558bf6bd5e1ac25262db62957e2dd6ba323bce4 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 5 Dec 2016 18:07:15 -0600 Subject: [PATCH 608/734] Eliminate some warnings --- configs/lpc4337-ws/src/lpc43_appinit.c | 2 +- configs/stm32f103-minimum/src/stm32_pwm.c | 2 +- configs/stm32f4discovery/src/stm32_pwm.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/configs/lpc4337-ws/src/lpc43_appinit.c b/configs/lpc4337-ws/src/lpc43_appinit.c index 047b544caa..3c5acc8584 100644 --- a/configs/lpc4337-ws/src/lpc43_appinit.c +++ b/configs/lpc4337-ws/src/lpc43_appinit.c @@ -141,7 +141,7 @@ int board_app_initialize(uintptr_t arg) lpc43_i2ctool(); -#ifdef CONFIG_ADC +#ifdef CONFIG_LPC43_ADC0 /* Initialize ADC and register the ADC driver. */ ret = lpc43_adc_setup(); diff --git a/configs/stm32f103-minimum/src/stm32_pwm.c b/configs/stm32f103-minimum/src/stm32_pwm.c index 5248e48921..dec2597991 100644 --- a/configs/stm32f103-minimum/src/stm32_pwm.c +++ b/configs/stm32f103-minimum/src/stm32_pwm.c @@ -81,7 +81,7 @@ # undef HAVE_PWM #endif -#if CONFIG_STM32_TIM3_CHANNEL != STM32F103MINIMUM_PWMCHANNEL +#if !defined(CONFIG_STM32_TIM3_CHANNEL) || CONFIG_STM32_TIM3_CHANNEL != STM32F103MINIMUM_PWMCHANNEL # undef HAVE_PWM #endif diff --git a/configs/stm32f4discovery/src/stm32_pwm.c b/configs/stm32f4discovery/src/stm32_pwm.c index 1b8468d2bb..48b7ff3a5f 100644 --- a/configs/stm32f4discovery/src/stm32_pwm.c +++ b/configs/stm32f4discovery/src/stm32_pwm.c @@ -79,7 +79,7 @@ # undef HAVE_PWM #endif -#if CONFIG_STM32_TIM4_CHANNEL != STM32F4DISCOVERY_PWMCHANNEL +#if !defined(CONFIG_STM32_TIM4_CHANNEL) || CONFIG_STM32_TIM4_CHANNEL != STM32F4DISCOVERY_PWMCHANNEL # undef HAVE_PWM #endif -- GitLab From 8b31eda4d8574e49b09ce39cdd1eaf7f7eee17d7 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Mon, 5 Dec 2016 14:19:56 -1000 Subject: [PATCH 609/734] Added Timers 2-5 and control of SAI and I2S PLLs --- arch/arm/src/stm32/Kconfig | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index f914f760e1..2cebd8ea41 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -1571,6 +1571,10 @@ config STM32_STM32F446 select STM32_HAVE_UART5 select STM32_HAVE_USART6 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 @@ -1604,6 +1608,10 @@ config STM32_STM32F469 select STM32_HAVE_UART7 select STM32_HAVE_UART8 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 @@ -1623,6 +1631,9 @@ config STM32_STM32F469 select STM32_HAVE_SPI4 select STM32_HAVE_SPI5 select STM32_HAVE_SPI6 + select STM32_HAVE_SAIPLL + select STM32_HAVE_I2SPLL + config STM32_DFU bool "DFU bootloader" -- GitLab From 50f36f896761c4dfc4bae801e0bbc8928c2730dd Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Mon, 5 Dec 2016 14:21:46 -1000 Subject: [PATCH 610/734] Added support for stmf469 SAI and I2S PLL configuration and STM446 fixes --- arch/arm/src/stm32/stm32f40xxx_rcc.c | 132 ++++++++++++++++++--------- 1 file changed, 91 insertions(+), 41 deletions(-) diff --git a/arch/arm/src/stm32/stm32f40xxx_rcc.c b/arch/arm/src/stm32/stm32f40xxx_rcc.c index 347d8a3d62..abb44313c8 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f40xxx_rcc.c @@ -725,7 +725,7 @@ static void stm32_stdclockconfig(void) #else /* if STM32_BOARD_USEHSE */ | RCC_PLLCFG_PLLSRC_HSE #endif -#if defined(CONFIG_STM32_STM32F446) +#if defined(STM32_PLLCFG_PLLR) | STM32_PLLCFG_PLLR #endif ); @@ -743,7 +743,8 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F446) +#if defined(PWR_CSR_ODRDY) + /* Enable the Over-drive to extend the clock frequency to 180 Mhz */ regval = getreg32(STM32_PWR_CR); @@ -783,12 +784,12 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32_LTDC) || \ - (defined(CONFIG_STM32_STM32F446) && defined(CONFIG_STM32_SAIPLL)) +#if defined(CONFIG_STM32_LTDC) || defined(CONFIG_STM32_SAIPLL) + /* Configure PLLSAI */ regval = getreg32(STM32_RCC_PLLSAICFGR); -#if defined(CONFIG_STM32_STM32F446) +# if defined(CONFIG_STM32_STM32F446) regval &= ~(RCC_PLLSAICFGR_PLLSAIM_MASK | RCC_PLLSAICFGR_PLLSAIN_MASK | RCC_PLLSAICFGR_PLLSAIP_MASK @@ -797,35 +798,64 @@ static void stm32_stdclockconfig(void) | STM32_RCC_PLLSAICFGR_PLLSAIN | STM32_RCC_PLLSAICFGR_PLLSAIP | STM32_RCC_PLLSAICFGR_PLLSAIQ); -#else +# elif defined(CONFIG_STM32_STM32F469) regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK - | RCC_PLLSAICFGR_PLLSAIR_MASK - | RCC_PLLSAICFGR_PLLSAIQ_MASK); + | RCC_PLLSAICFGR_PLLSAIP_MASK + | RCC_PLLSAICFGR_PLLSAIQ_MASK + | RCC_PLLSAICFGR_PLLSAIR_MASK); regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN - | STM32_RCC_PLLSAICFGR_PLLSAIR - | STM32_RCC_PLLSAICFGR_PLLSAIQ); -#endif + | STM32_RCC_PLLSAICFGR_PLLSAIP + | STM32_RCC_PLLSAICFGR_PLLSAIQ + | STM32_RCC_PLLSAICFGR_PLLSAIR); +# else + regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK + | RCC_PLLSAICFGR_PLLSAIQ_MASK + | RCC_PLLSAICFGR_PLLSAIR_MASK); + regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN + | STM32_RCC_PLLSAICFGR_PLLSAIQ + | STM32_RCC_PLLSAICFGR_PLLSAIR); +# endif putreg32(regval, STM32_RCC_PLLSAICFGR); regval = getreg32(STM32_RCC_DCKCFGR); -#if defined(CONFIG_STM32_STM32F446) +# if defined(CONFIG_STM32_STM32F446) regval &= ~(RCC_DCKCFGR_PLLI2SDIVQ_MASK - | RCC_DCKCFGR_PLLSAIDIVQ_MASK - | RCC_DCKCFGR_SAI1SRC_MASK - | RCC_DCKCFGR_SAI2SRC_MASK - | RCC_DCKCFGR_I2S1SRC_MASK - | RCC_DCKCFGR_I2S2SRC_MASK); + | RCC_DCKCFGR_PLLSAIDIVQ_MASK + | RCC_DCKCFGR_SAI1SRC_MASK + | RCC_DCKCFGR_SAI2SRC_MASK + | RCC_DCKCFGR_TIMPRE + | RCC_DCKCFGR_I2S1SRC_MASK + | RCC_DCKCFGR_I2S2SRC_MASK); regval |= (STM32_RCC_DCKCFGR_PLLI2SDIVQ - | STM32_RCC_DCKCFGR_PLLSAIDIVQ - | STM32_RCC_DCKCFGR_SAI1SRC - | STM32_RCC_DCKCFGR_SAI2SRC - | STM32_RCC_DCKCFGR_TIMPRE - | STM32_RCC_DCKCFGR_I2S1SRC - | STM32_RCC_DCKCFGR_I2S2SRC); -#else + | STM32_RCC_DCKCFGR_PLLSAIDIVQ + | STM32_RCC_DCKCFGR_SAI1SRC + | STM32_RCC_DCKCFGR_SAI2SRC + | STM32_RCC_DCKCFGR_TIMPRE + | STM32_RCC_DCKCFGR_I2S1SRC + | STM32_RCC_DCKCFGR_I2S2SRC); +# elif defined(CONFIG_STM32_STM32F469) + regval &= ~(RCC_DCKCFGR_PLLI2SDIVQ_MASK + | RCC_DCKCFGR_PLLSAIDIVQ_MASK + | RCC_DCKCFGR_PLLSAIDIVR_MASK + | RCC_DCKCFGR_SAI1ASRC_MASK + | RCC_DCKCFGR_SAI1BSRC_MASK + | RCC_DCKCFGR_TIMPRE + | RCC_DCKCFGR_48MSEL_MASK + | RCC_DCKCFGR_SDMMCSEL_MASK + | RCC_DCKCFGR_DSISEL_MASK); + regval |= (STM32_RCC_DCKCFGR_PLLI2SDIVQ + | STM32_RCC_DCKCFGR_PLLSAIDIVQ + | STM32_RCC_DCKCFGR_PLLSAIDIVR + | STM32_RCC_DCKCFGR_SAI1ASRC + | STM32_RCC_DCKCFGR_SAI1BSRC + | STM32_RCC_DCKCFGR_TIMPRE + | STM32_RCC_DCKCFGR_48MSEL + | STM32_RCC_DCKCFGR_SDMMCSEL + | STM32_RCC_DCKCFGR_DSISEL); +# else regval &= ~RCC_DCKCFGR_PLLSAIDIVR_MASK; regval |= STM32_RCC_DCKCFGR_PLLSAIDIVR; -#endif +# endif putreg32(regval, STM32_RCC_DCKCFGR); /* Enable PLLSAI */ @@ -841,34 +871,54 @@ static void stm32_stdclockconfig(void) } #endif -#if defined(CONFIG_STM32_STM32F446) && defined(CONFIG_STM32_I2SPLL) +#if defined(CONFIG_STM32_I2SPLL) + /* Configure PLLI2S */ regval = getreg32(STM32_RCC_PLLI2SCFGR); + +# if defined(CONFIG_STM32_STM32F446) + regval &= ~(RCC_PLLI2SCFGR_PLLI2SM_MASK - | RCC_PLLI2SCFGR_PLLI2SN_MASK - | RCC_PLLI2SCFGR_PLLI2SP_MASK - | RCC_PLLI2SCFGR_PLLI2SQ_MASK); + | RCC_PLLI2SCFGR_PLLI2SN_MASK + | RCC_PLLI2SCFGR_PLLI2SP_MASK + | RCC_PLLI2SCFGR_PLLI2SQ_MASK + | RCC_PLLI2SCFGR_PLLI2SR_MASK); regval |= (STM32_RCC_PLLI2SCFGR_PLLI2SM - | STM32_RCC_PLLI2SCFGR_PLLI2SN - | STM32_RCC_PLLI2SCFGR_PLLI2SP - | STM32_RCC_PLLI2SCFGR_PLLI2SQ - | STM32_RCC_PLLI2SCFGR_PLLI2SR); + | STM32_RCC_PLLI2SCFGR_PLLI2SN + | STM32_RCC_PLLI2SCFGR_PLLI2SP + | STM32_RCC_PLLI2SCFGR_PLLI2SQ + | STM32_RCC_PLLI2SCFGR_PLLI2SR); + +# elif defined(CONFIG_STM32_STM32F469) + + regval &= ~(RCC_PLLI2SCFGR_PLLI2SN_MASK + | RCC_PLLI2SCFGR_PLLI2SQ_MASK + | RCC_PLLI2SCFGR_PLLI2SR_MASK); + regval |= (STM32_RCC_PLLI2SCFGR_PLLI2SN + | STM32_RCC_PLLI2SCFGR_PLLI2SQ + | STM32_RCC_PLLI2SCFGR_PLLI2SR); +# endif + putreg32(regval, STM32_RCC_PLLI2SCFGR); +# if defined(STM32_RCC_DCKCFGR2) + regval = getreg32(STM32_RCC_DCKCFGR2); + regval &= ~(RCC_DCKCFGR2_FMPI2C1SEL_MASK - | RCC_DCKCFGR2_CECSEL_MASK - | RCC_DCKCFGR2_CK48MSEL_MASK - | RCC_DCKCFGR2_SDIOSEL_MASK - | RCC_DCKCFGR2_SPDIFRXSEL_MASK); + | RCC_DCKCFGR2_CECSEL_MASK + | RCC_DCKCFGR2_CK48MSEL_MASK + | RCC_DCKCFGR2_SDIOSEL_MASK + | RCC_DCKCFGR2_SPDIFRXSEL_MASK); regval |= (STM32_RCC_DCKCFGR2_FMPI2C1SEL - | STM32_RCC_DCKCFGR2_CECSEL - | STM32_RCC_DCKCFGR2_CK48MSEL - | STM32_RCC_DCKCFGR2_SDIOSEL - | STM32_RCC_DCKCFGR2_SPDIFRXSEL); + | STM32_RCC_DCKCFGR2_CECSEL + | STM32_RCC_DCKCFGR2_CK48MSEL + | STM32_RCC_DCKCFGR2_SDIOSEL + | STM32_RCC_DCKCFGR2_SPDIFRXSEL); putreg32(regval, STM32_RCC_DCKCFGR2); +# endif /* Enable PLLI2S */ -- GitLab From 885b718552dfbc69e60e73120c21cc4c87794dbe Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Mon, 5 Dec 2016 14:24:48 -1000 Subject: [PATCH 611/734] Expanded otgfs support to stm32F469 and stm32f446 Added missing bits definitions Used stm32F469 and stm32f446 bit definitions Removed unsed header file --- arch/arm/src/stm32/chip/stm32_otgfs.h | 1018 ------------------- arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h | 11 +- arch/arm/src/stm32/stm32_otgfsdev.c | 77 +- 3 files changed, 61 insertions(+), 1045 deletions(-) delete mode 100644 arch/arm/src/stm32/chip/stm32_otgfs.h diff --git a/arch/arm/src/stm32/chip/stm32_otgfs.h b/arch/arm/src/stm32/chip/stm32_otgfs.h deleted file mode 100644 index 575214e648..0000000000 --- a/arch/arm/src/stm32/chip/stm32_otgfs.h +++ /dev/null @@ -1,1018 +0,0 @@ -/**************************************************************************************************** - * arch/arm/src/stm32/chip/stm32_otgfs.h - * - * Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_OTGFS_H -#define __ARCH_ARM_SRC_STM32_CHIP_STM32_OTGFS_H - -/**************************************************************************************************** - * Included Files - ****************************************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************************/ -/* General definitions */ - -#define OTGFS_EPTYPE_CTRL (0) /* Control */ -#define OTGFS_EPTYPE_ISOC (1) /* Isochronous */ -#define OTGFS_EPTYPE_BULK (2) /* Bulk */ -#define OTGFS_EPTYPE_INTR (3) /* Interrupt */ - -#define OTGFS_PID_DATA0 (0) -#define OTGFS_PID_DATA2 (1) -#define OTGFS_PID_DATA1 (2) -#define OTGFS_PID_MDATA (3) /* Non-control */ -#define OTGFS_PID_SETUP (3) /* Control */ - -/* Register Offsets *********************************************************************************/ -/* Core global control and status registers */ - -#define STM32_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ -#define STM32_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ -#define STM32_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ -#define STM32_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ -#define STM32_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */ -#define STM32_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ -#define STM32_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ -#define STM32_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ -#define STM32_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ -#define STM32_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ -#define STM32_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ -#define STM32_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ -#define STM32_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ -#define STM32_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */ -#define STM32_OTGFS_CID_OFFSET 0x003c /* Core ID register */ -#define STM32_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ - -#define STM32_OTGFS_DIEPTXF_OFFSET(n) (104+(((n)-1) << 2)) -#define STM32_OTGFS_DIEPTXF1_OFFSET 0x0104 /* Device IN endpoint transmit FIFO1 size register */ -#define STM32_OTGFS_DIEPTXF2_OFFSET 0x0108 /* Device IN endpoint transmit FIFO2 size register */ -#define STM32_OTGFS_DIEPTXF3_OFFSET 0x010c /* Device IN endpoint transmit FIFO3 size register */ - -/* Host-mode control and status registers */ - -#define STM32_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */ -#define STM32_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */ -#define STM32_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ -#define STM32_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ -#define STM32_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ -#define STM32_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ -#define STM32_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */ - -#define STM32_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5) -#define STM32_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ -#define STM32_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ -#define STM32_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ -#define STM32_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ - -#define STM32_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) -#define STM32_OTGFS_HCCHAR0_OFFSET 0x0500 /* Host channel-0 characteristics register */ -#define STM32_OTGFS_HCCHAR1_OFFSET 0x0520 /* Host channel-1 characteristics register */ -#define STM32_OTGFS_HCCHAR2_OFFSET 0x0540 /* Host channel-2 characteristics register */ -#define STM32_OTGFS_HCCHAR3_OFFSET 0x0560 /* Host channel-3 characteristics register */ -#define STM32_OTGFS_HCCHAR4_OFFSET 0x0580 /* Host channel-4 characteristics register */ -#define STM32_OTGFS_HCCHAR5_OFFSET 0x05a0 /* Host channel-5 characteristics register */ -#define STM32_OTGFS_HCCHAR6_OFFSET 0x05c0 /* Host channel-6 characteristics register */ -#define STM32_OTGFS_HCCHAR7_OFFSET 0x05e0 /* Host channel-7 characteristics register */ - -#define STM32_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) -#define STM32_OTGFS_HCINT0_OFFSET 0x0508 /* Host channel-0 interrupt register */ -#define STM32_OTGFS_HCINT1_OFFSET 0x0528 /* Host channel-1 interrupt register */ -#define STM32_OTGFS_HCINT2_OFFSET 0x0548 /* Host channel-2 interrupt register */ -#define STM32_OTGFS_HCINT3_OFFSET 0x0568 /* Host channel-3 interrupt register */ -#define STM32_OTGFS_HCINT4_OFFSET 0x0588 /* Host channel-4 interrupt register */ -#define STM32_OTGFS_HCINT5_OFFSET 0x05a8 /* Host channel-5 interrupt register */ -#define STM32_OTGFS_HCINT6_OFFSET 0x05c8 /* Host channel-6 interrupt register */ -#define STM32_OTGFS_HCINT7_OFFSET 0x05e8 /* Host channel-7 interrupt register */ - -#define STM32_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) -#define STM32_OTGFS_HCINTMSK0_OFFSET 0x050c /* Host channel-0 interrupt mask register */ -#define STM32_OTGFS_HCINTMSK1_OFFSET 0x052c /* Host channel-1 interrupt mask register */ -#define STM32_OTGFS_HCINTMSK2_OFFSET 0x054c /* Host channel-2 interrupt mask register */ -#define STM32_OTGFS_HCINTMSK3_OFFSET 0x056c /* Host channel-3 interrupt mask register */ -#define STM32_OTGFS_HCINTMSK4_OFFSET 0x058c /* Host channel-4 interrupt mask register */ -#define STM32_OTGFS_HCINTMSK5_OFFSET 0x05ac /* Host channel-5 interrupt mask register */ -#define STM32_OTGFS_HCINTMSK6_OFFSET 0x05cc /* Host channel-6 interrupt mask register */ -#define STM32_OTGFS_HCINTMSK7_OFFSET 0x05ec /* Host channel-7 interrupt mask register */ - -#define STM32_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) -#define STM32_OTGFS_HCTSIZ0_OFFSET 0x0510 /* Host channel-0 interrupt register */ -#define STM32_OTGFS_HCTSIZ1_OFFSET 0x0530 /* Host channel-1 interrupt register */ -#define STM32_OTGFS_HCTSIZ2_OFFSET 0x0550 /* Host channel-2 interrupt register */ -#define STM32_OTGFS_HCTSIZ3_OFFSET 0x0570 /* Host channel-3 interrupt register */ -#define STM32_OTGFS_HCTSIZ4_OFFSET 0x0590 /* Host channel-4 interrupt register */ -#define STM32_OTGFS_HCTSIZ5_OFFSET 0x05b0 /* Host channel-5 interrupt register */ -#define STM32_OTGFS_HCTSIZ6_OFFSET 0x05d0 /* Host channel-6 interrupt register */ -#define STM32_OTGFS_HCTSIZ7_OFFSET 0x05f0 /* Host channel-7 interrupt register */ - -/* Device-mode control and status registers */ - -#define STM32_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */ -#define STM32_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */ -#define STM32_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */ -#define STM32_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ -#define STM32_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ -#define STM32_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ -#define STM32_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ -#define STM32_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ -#define STM32_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ -#define STM32_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ - -#define STM32_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ -#define STM32_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ -#define STM32_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ -#define STM32_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ - -#define STM32_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32_OTGFS_DIEPCTL0_OFFSET 0x0900 /* Device control IN endpoint 0 control register */ -#define STM32_OTGFS_DIEPCTL1_OFFSET 0x0920 /* Device control IN endpoint 2 control register */ -#define STM32_OTGFS_DIEPCTL2_OFFSET 0x0940 /* Device control IN endpoint 3 control register */ -#define STM32_OTGFS_DIEPCTL3_OFFSET 0x0960 /* Device control IN endpoint 4 control register */ - -#define STM32_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) -#define STM32_OTGFS_DIEPINT0_OFFSET 0x0908 /* Device endpoint-0 interrupt register */ -#define STM32_OTGFS_DIEPINT1_OFFSET 0x0928 /* Device endpoint-1 interrupt register */ -#define STM32_OTGFS_DIEPINT2_OFFSET 0x0948 /* Device endpoint-2 interrupt register */ -#define STM32_OTGFS_DIEPINT3_OFFSET 0x0968 /* Device endpoint-3 interrupt register */ - -#define STM32_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) -#define STM32_OTGFS_DIEPTSIZ0_OFFSET 0x0910 /* Device IN endpoint 0 transfer size register */ -#define STM32_OTGFS_DIEPTSIZ1_OFFSET 0x0930 /* Device IN endpoint 1 transfer size register */ -#define STM32_OTGFS_DIEPTSIZ2_OFFSET 0x0950 /* Device IN endpoint 2 transfer size register */ -#define STM32_OTGFS_DIEPTSIZ3_OFFSET 0x0970 /* Device IN endpoint 3 transfer size register */ - -#define STM32_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) -#define STM32_OTGFS_DTXFSTS0_OFFSET 0x0918 /* Device OUT endpoint-0 TxFIFO status register */ -#define STM32_OTGFS_DTXFSTS1_OFFSET 0x0938 /* Device OUT endpoint-1 TxFIFO status register */ -#define STM32_OTGFS_DTXFSTS2_OFFSET 0x0958 /* Device OUT endpoint-2 TxFIFO status register */ -#define STM32_OTGFS_DTXFSTS3_OFFSET 0x0978 /* Device OUT endpoint-3 TxFIFO status register */ - -#define STM32_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ -#define STM32_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ - -#define STM32_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32_OTGFS_DOEPCTL0_OFFSET 0x00b00 /* Device OUT endpoint 0 control register */ -#define STM32_OTGFS_DOEPCTL1_OFFSET 0x00b20 /* Device OUT endpoint 1 control register */ -#define STM32_OTGFS_DOEPCTL2_OFFSET 0x00b40 /* Device OUT endpoint 2 control register */ -#define STM32_OTGFS_DOEPCTL3_OFFSET 0x00b60 /* Device OUT endpoint 3 control register */ - -#define STM32_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) -#define STM32_OTGFS_DOEPINT0_OFFSET 0x00b08 /* Device endpoint-0 interrupt register */ -#define STM32_OTGFS_DOEPINT1_OFFSET 0x00b28 /* Device endpoint-1 interrupt register */ -#define STM32_OTGFS_DOEPINT2_OFFSET 0x00b48 /* Device endpoint-2 interrupt register */ -#define STM32_OTGFS_DOEPINT3_OFFSET 0x00b68 /* Device endpoint-3 interrupt register */ - -#define STM32_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) -#define STM32_OTGFS_DOEPTSIZ0_OFFSET 0x00b10 /* Device OUT endpoint-0 transfer size register */ -#define STM32_OTGFS_DOEPTSIZ1_OFFSET 0x00b30 /* Device OUT endpoint-1 transfer size register */ -#define STM32_OTGFS_DOEPTSIZ2_OFFSET 0x00b50 /* Device OUT endpoint-2 transfer size register */ -#define STM32_OTGFS_DOEPTSIZ3_OFFSET 0x00b70 /* Device OUT endpoint-3 transfer size register */ - -/* Power and clock gating registers */ - -#define STM32_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ - -/* Data FIFO (DFIFO) access registers */ - -#define STM32_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) -#define STM32_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) - -#define STM32_OTGFS_DFIFO_DEP0_OFFSET 0x1000 /* 0x1000-0x1ffc Device IN/OUT Endpoint 0 DFIFO Write/Read Access */ -#define STM32_OTGFS_DFIFO_HCH0_OFFSET 0x1000 /* 0x1000-0x1ffc Host OUT/IN Channel 0 DFIFO Read/Write Access */ - -#define STM32_OTGFS_DFIFO_DEP1_OFFSET 0x2000 /* 0x2000-0x2ffc Device IN/OUT Endpoint 1 DFIFO Write/Read Access */ -#define STM32_OTGFS_DFIFO_HCH1_OFFSET 0x2000 /* 0x2000-0x2ffc Host OUT/IN Channel 1 DFIFO Read/Write Access */ - -#define STM32_OTGFS_DFIFO_DEP2_OFFSET 0x3000 /* 0x3000-0x3ffc Device IN/OUT Endpoint 2 DFIFO Write/Read Access */ -#define STM32_OTGFS_DFIFO_HCH2_OFFSET 0x3000 /* 0x3000-0x3ffc Host OUT/IN Channel 2 DFIFO Read/Write Access */ - -#define STM32_OTGFS_DFIFO_DEP3_OFFSET 0x4000 /* 0x4000-0x4ffc Device IN/OUT Endpoint 3 DFIFO Write/Read Access */ -#define STM32_OTGFS_DFIFO_HCH3_OFFSET 0x4000 /* 0x4000-0x4ffc Host OUT/IN Channel 3 DFIFO Read/Write Access */ - -/* Register Addresses *******************************************************************************/ - -#define STM32_OTGFS_GOTGCTL (STM32_OTGFS_BASE+STM32_OTGFS_GOTGCTL_OFFSET) -#define STM32_OTGFS_GOTGINT (STM32_OTGFS_BASE+STM32_OTGFS_GOTGINT_OFFSET) -#define STM32_OTGFS_GAHBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GAHBCFG_OFFSET) -#define STM32_OTGFS_GUSBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GUSBCFG_OFFSET) -#define STM32_OTGFS_GRSTCTL (STM32_OTGFS_BASE+STM32_OTGFS_GRSTCTL_OFFSET) -#define STM32_OTGFS_GINTSTS (STM32_OTGFS_BASE+STM32_OTGFS_GINTSTS_OFFSET) -#define STM32_OTGFS_GINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_GINTMSK_OFFSET) -#define STM32_OTGFS_GRXSTSR (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSR_OFFSET) -#define STM32_OTGFS_GRXSTSP (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSP_OFFSET) -#define STM32_OTGFS_GRXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_GRXFSIZ_OFFSET) -#define STM32_OTGFS_HNPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXFSIZ_OFFSET) -#define STM32_OTGFS_DIEPTXF0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF0_OFFSET) -#define STM32_OTGFS_HNPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXSTS_OFFSET) -#define STM32_OTGFS_GCCFG (STM32_OTGFS_BASE+STM32_OTGFS_GCCFG_OFFSET) -#define STM32_OTGFS_CID (STM32_OTGFS_BASE+STM32_OTGFS_CID_OFFSET) -#define STM32_OTGFS_HPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HPTXFSIZ_OFFSET) - -#define STM32_OTGFS_DIEPTXF(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF_OFFSET(n)) -#define STM32_OTGFS_DIEPTXF1 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF1_OFFSET) -#define STM32_OTGFS_DIEPTXF2 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF2_OFFSET) -#define STM32_OTGFS_DIEPTXF3 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF3_OFFSET) - -/* Host-mode control and status registers */ - -#define STM32_OTGFS_HCFG (STM32_OTGFS_BASE+STM32_OTGFS_HCFG_OFFSET) -#define STM32_OTGFS_HFIR (STM32_OTGFS_BASE+STM32_OTGFS_HFIR_OFFSET) -#define STM32_OTGFS_HFNUM (STM32_OTGFS_BASE+STM32_OTGFS_HFNUM_OFFSET) -#define STM32_OTGFS_HPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HPTXSTS_OFFSET) -#define STM32_OTGFS_HAINT (STM32_OTGFS_BASE+STM32_OTGFS_HAINT_OFFSET) -#define STM32_OTGFS_HAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_HAINTMSK_OFFSET) -#define STM32_OTGFS_HPRT (STM32_OTGFS_BASE+STM32_OTGFS_HPRT_OFFSET) - -#define STM32_OTGFS_CHAN(n) (STM32_OTGFS_BASE+STM32_OTGFS_CHAN_OFFSET(n)) - -#define STM32_OTGFS_HCCHAR(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR_OFFSET(n)) -#define STM32_OTGFS_HCCHAR0 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR0_OFFSET) -#define STM32_OTGFS_HCCHAR1 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR1_OFFSET) -#define STM32_OTGFS_HCCHAR2 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR2_OFFSET) -#define STM32_OTGFS_HCCHAR3 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR3_OFFSET) -#define STM32_OTGFS_HCCHAR4 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR4_OFFSET) -#define STM32_OTGFS_HCCHAR5 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR5_OFFSET) -#define STM32_OTGFS_HCCHAR6 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR6_OFFSET) -#define STM32_OTGFS_HCCHAR7 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR7_OFFSET) - -#define STM32_OTGFS_HCINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINT_OFFSET(n)) -#define STM32_OTGFS_HCINT0 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT0_OFFSET) -#define STM32_OTGFS_HCINT1 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT1_OFFSET) -#define STM32_OTGFS_HCINT2 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT2_OFFSET) -#define STM32_OTGFS_HCINT3 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT3_OFFSET) -#define STM32_OTGFS_HCINT4 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT4_OFFSET) -#define STM32_OTGFS_HCINT5 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT5_OFFSET) -#define STM32_OTGFS_HCINT6 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT6_OFFSET) -#define STM32_OTGFS_HCINT7 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT7_OFFSET) - -#define STM32_OTGFS_HCINTMSK(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK_OFFSET(n)) -#define STM32_OTGFS_HCINTMSK0 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK0_OFFSET) -#define STM32_OTGFS_HCINTMSK1 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK1_OFFSET) -#define STM32_OTGFS_HCINTMSK2 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK2_OFFSET) -#define STM32_OTGFS_HCINTMSK3 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK3_OFFSET) -#define STM32_OTGFS_HCINTMSK4 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK4_OFFSET) -#define STM32_OTGFS_HCINTMSK5 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK5_OFFSET) -#define STM32_OTGFS_HCINTMSK6 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK6_OFFSET) -#define STM32_OTGFS_HCINTMSK7 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK7_OFFSET)_ - -#define STM32_OTGFS_HCTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ_OFFSET(n)) -#define STM32_OTGFS_HCTSIZ0 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ0_OFFSET) -#define STM32_OTGFS_HCTSIZ1 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ1_OFFSET) -#define STM32_OTGFS_HCTSIZ2 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ2_OFFSET) -#define STM32_OTGFS_HCTSIZ3 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ3_OFFSET) -#define STM32_OTGFS_HCTSIZ4 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ4_OFFSET) -#define STM32_OTGFS_HCTSIZ5 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ5_OFFSET) -#define STM32_OTGFS_HCTSIZ6 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ6_OFFSET) -#define STM32_OTGFS_HCTSIZ7 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ7_OFFSET) - -/* Device-mode control and status registers */ - -#define STM32_OTGFS_DCFG (STM32_OTGFS_BASE+STM32_OTGFS_DCFG_OFFSET) -#define STM32_OTGFS_DCTL (STM32_OTGFS_BASE+STM32_OTGFS_DCTL_OFFSET) -#define STM32_OTGFS_DSTS (STM32_OTGFS_BASE+STM32_OTGFS_DSTS_OFFSET) -#define STM32_OTGFS_DIEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPMSK_OFFSET) -#define STM32_OTGFS_DOEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DOEPMSK_OFFSET) -#define STM32_OTGFS_DAINT (STM32_OTGFS_BASE+STM32_OTGFS_DAINT_OFFSET) -#define STM32_OTGFS_DAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_DAINTMSK_OFFSET) -#define STM32_OTGFS_DVBUSDIS (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSDIS_OFFSET) -#define STM32_OTGFS_DVBUSPULSE (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSPULSE_OFFSET) -#define STM32_OTGFS_DIEPEMPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPEMPMSK_OFFSET) - -#define STM32_OTGFS_DIEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEP_OFFSET(n)) - -#define STM32_OTGFS_DIEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL_OFFSET(n)) -#define STM32_OTGFS_DIEPCTL0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL0_OFFSET) -#define STM32_OTGFS_DIEPCTL1 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL1_OFFSET) -#define STM32_OTGFS_DIEPCTL2 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL2_OFFSET) -#define STM32_OTGFS_DIEPCTL3 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL3_OFFSET) - -#define STM32_OTGFS_DIEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT_OFFSET(n)) -#define STM32_OTGFS_DIEPINT0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT0_OFFSET) -#define STM32_OTGFS_DIEPINT1 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT1_OFFSET) -#define STM32_OTGFS_DIEPINT2 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT2_OFFSET) -#define STM32_OTGFS_DIEPINT3 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT3_OFFSET) - -#define STM32_OTGFS_DIEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ_OFFSET(n)) -#define STM32_OTGFS_DIEPTSIZ0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ0_OFFSET) -#define STM32_OTGFS_DIEPTSIZ1 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ1_OFFSET) -#define STM32_OTGFS_DIEPTSIZ2 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ2_OFFSET) -#define STM32_OTGFS_DIEPTSIZ3 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ3_OFFSET) - -#define STM32_OTGFS_DTXFSTS(n) (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS_OFFSET(n)) -#define STM32_OTGFS_DTXFSTS0 (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS0_OFFSET) -#define STM32_OTGFS_DTXFSTS1 (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS1_OFFSET) -#define STM32_OTGFS_DTXFSTS2 (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS2_OFFSET) -#define STM32_OTGFS_DTXFSTS3 (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS3_OFFSET) - -#define STM32_OTGFS_DOEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEP_OFFSET(n)) - -#define STM32_OTGFS_DOEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL_OFFSET(n)) -#define STM32_OTGFS_DOEPCTL0 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL0_OFFSET) -#define STM32_OTGFS_DOEPCTL1 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL1_OFFSET) -#define STM32_OTGFS_DOEPCTL2 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL2_OFFSET) -#define STM32_OTGFS_DOEPCTL3 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL3_OFFSET) - -#define STM32_OTGFS_DOEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT_OFFSET(n)) -#define STM32_OTGFS_DOEPINT0 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT0_OFFSET) -#define STM32_OTGFS_DOEPINT1 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT1_OFFSET) -#define STM32_OTGFS_DOEPINT2 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT2_OFFSET) -#define STM32_OTGFS_DOEPINT3 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT3_OFFSET) - -#define STM32_OTGFS_DOEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ_OFFSET(n)) -#define STM32_OTGFS_DOEPTSIZ0 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ0_OFFSET) -#define STM32_OTGFS_DOEPTSIZ1 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ1_OFFSET) -#define STM32_OTGFS_DOEPTSIZ2 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ2_OFFSET) -#define STM32_OTGFS_DOEPTSIZ3 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ3_OFFSET) - -/* Power and clock gating registers */ - -#define STM32_OTGFS_PCGCCTL (STM32_OTGFS_BASE+STM32_OTGFS_PCGCCTL_OFFSET) - -/* Data FIFO (DFIFO) access registers */ - -#define STM32_OTGFS_DFIFO_DEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP_OFFSET(n)) -#define STM32_OTGFS_DFIFO_HCH(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH_OFFSET(n)) - -#define STM32_OTGFS_DFIFO_DEP0 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP0_OFFSET) -#define STM32_OTGFS_DFIFO_HCH0 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH0_OFFSET) - -#define STM32_OTGFS_DFIFO_DEP1 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP1_OFFSET) -#define STM32_OTGFS_DFIFO_HCH1 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH1_OFFSET) - -#define STM32_OTGFS_DFIFO_DEP2 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP2_OFFSET) -#define STM32_OTGFS_DFIFO_HCH2 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH2_OFFSET) - -#define STM32_OTGFS_DFIFO_DEP3 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP3_OFFSET) -#define STM32_OTGFS_DFIFO_HCH3 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH3_OFFSET) - -/* Register Bitfield Definitions ********************************************************************/ -/* Core global control and status registers */ - -/* Control and status register */ - -#define OTGFS_GOTGCTL_SRQSCS (1 << 0) /* Bit 0: Session request success */ -#define OTGFS_GOTGCTL_SRQ (1 << 1) /* Bit 1: Session request */ - /* Bits 2-72 Reserved, must be kept at reset value */ -#define OTGFS_GOTGCTL_HNGSCS (1 << 8) /* Bit 8: Host negotiation success */ -#define OTGFS_GOTGCTL_HNPRQ (1 << 9) /* Bit 9: HNP request */ -#define OTGFS_GOTGCTL_HSHNPEN (1 << 10) /* Bit 10: host set HNP enable */ -#define OTGFS_GOTGCTL_DHNPEN (1 << 11) /* Bit 11: Device HNP enabled */ - /* Bits 12-15: Reserved, must be kept at reset value */ -#define OTGFS_GOTGCTL_CIDSTS (1 << 16) /* Bit 16: Connector ID status */ -#define OTGFS_GOTGCTL_DBCT (1 << 17) /* Bit 17: Long/short debounce time */ -#define OTGFS_GOTGCTL_ASVLD (1 << 18) /* Bit 18: A-session valid */ -#define OTGFS_GOTGCTL_BSVLD (1 << 19) /* Bit 19: B-session valid */ - /* Bits 20-31: Reserved, must be kept at reset value */ -/* Interrupt register */ - /* Bits 1:0 Reserved, must be kept at reset value */ -#define OTGFS_GOTGINT_SEDET (1 << 2) /* Bit 2: Session end detected */ - /* Bits 3-7: Reserved, must be kept at reset value */ -#define OTGFS_GOTGINT_SRSSCHG (1 << 8) /* Bit 8: Session request success status change */ -#define OTGFS_GOTGINT_HNSSCHG (1 << 9) /* Bit 9: Host negotiation success status change */ - /* Bits 16:10 Reserved, must be kept at reset value */ -#define OTGFS_GOTGINT_HNGDET (1 << 17) /* Bit 17: Host negotiation detected */ -#define OTGFS_GOTGINT_ADTOCHG (1 << 18) /* Bit 18: A-device timeout change */ -#define OTGFS_GOTGINT_DBCDNE (1 << 19) /* Bit 19: Debounce done */ - /* Bits 2-31: Reserved, must be kept at reset value */ - -/* AHB configuration register */ - -#define OTGFS_GAHBCFG_GINTMSK (1 << 0) /* Bit 0: Global interrupt mask */ - /* Bits 1-6: Reserved, must be kept at reset value */ -#define OTGFS_GAHBCFG_TXFELVL (1 << 7) /* Bit 7: TxFIFO empty level */ -#define OTGFS_GAHBCFG_PTXFELVL (1 << 8) /* Bit 8: Periodic TxFIFO empty level */ - /* Bits 20-31: Reserved, must be kept at reset value */ -/* USB configuration register */ - -#define OTGFS_GUSBCFG_TOCAL_SHIFT (0) /* Bits 0-2: FS timeout calibration */ -#define OTGFS_GUSBCFG_TOCAL_MASK (7 << OTGFS_GUSBCFG_TOCAL_SHIFT) - /* Bits 3-5: Reserved, must be kept at reset value */ -#define OTGFS_GUSBCFG_PHYSEL (1 << 6) /* Bit 6: Full Speed serial transceiver select */ - /* Bit 7: Reserved, must be kept at reset value */ -#define OTGFS_GUSBCFG_SRPCAP (1 << 8) /* Bit 8: SRP-capable */ -#define OTGFS_GUSBCFG_HNPCAP (1 << 9) /* Bit 9: HNP-capable */ -#define OTGFS_GUSBCFG_TRDT_SHIFT (10) /* Bits 10-13: USB turnaround time */ -#define OTGFS_GUSBCFG_TRDT_MASK (15 << OTGFS_GUSBCFG_TRDT_SHIFT) -# define OTGFS_GUSBCFG_TRDT(n) ((n) << OTGFS_GUSBCFG_TRDT_SHIFT) - /* Bits 14-28: Reserved, must be kept at reset value */ -#define OTGFS_GUSBCFG_FHMOD (1 << 29) /* Bit 29: Force host mode */ -#define OTGFS_GUSBCFG_FDMOD (1 << 30) /* Bit 30: Force device mode */ -#define OTGFS_GUSBCFG_CTXPKT (1 << 31) /* Bit 31: Corrupt Tx packet */ - /* Bits 20-31: Reserved, must be kept at reset value */ -/* Reset register */ - -#define OTGFS_GRSTCTL_CSRST (1 << 0) /* Bit 0: Core soft reset */ -#define OTGFS_GRSTCTL_HSRST (1 << 1) /* Bit 1: HCLK soft reset */ -#define OTGFS_GRSTCTL_FCRST (1 << 2) /* Bit 2: Host frame counter reset */ - /* Bit 3 Reserved, must be kept at reset value */ -#define OTGFS_GRSTCTL_RXFFLSH (1 << 4) /* Bit 4: RxFIFO flush */ -#define OTGFS_GRSTCTL_TXFFLSH (1 << 5) /* Bit 5: TxFIFO flush */ -#define OTGFS_GRSTCTL_TXFNUM_SHIFT (6) /* Bits 6-10: TxFIFO number */ -#define OTGFS_GRSTCTL_TXFNUM_MASK (31 << OTGFS_GRSTCTL_TXFNUM_SHIFT) -# define OTGFS_GRSTCTL_TXFNUM_HNONPER (0 << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Non-periodic TxFIFO flush in host mode */ -# define OTGFS_GRSTCTL_TXFNUM_HPER (1 << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Periodic TxFIFO flush in host mode */ -# define OTGFS_GRSTCTL_TXFNUM_HALL (16 << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in host mode.*/ -# define OTGFS_GRSTCTL_TXFNUM_D(n) ((n) << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* TXFIFO n flush in device mode, n=0-15 */ -# define OTGFS_GRSTCTL_TXFNUM_DALL (16 << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in device mode.*/ - /* Bits 11-31: Reserved, must be kept at reset value */ -#define OTGFS_GRSTCTL_AHBIDL (1 << 31) /* Bit 31: AHB master idle */ - -/* Core interrupt and Interrupt mask registers */ - -#define OTGFS_GINTSTS_CMOD (1 << 0) /* Bit 0: Current mode of operation */ -# define OTGFS_GINTSTS_DEVMODE (0) -# define OTGFS_GINTSTS_HOSTMODE (OTGFS_GINTSTS_CMOD) -#define OTGFS_GINT_MMIS (1 << 1) /* Bit 1: Mode mismatch interrupt */ -#define OTGFS_GINT_OTG (1 << 2) /* Bit 2: OTG interrupt */ -#define OTGFS_GINT_SOF (1 << 3) /* Bit 3: Start of frame */ -#define OTGFS_GINT_RXFLVL (1 << 4) /* Bit 4: RxFIFO non-empty */ -#define OTGFS_GINT_NPTXFE (1 << 5) /* Bit 5: Non-periodic TxFIFO empty */ -#define OTGFS_GINT_GINAKEFF (1 << 6) /* Bit 6: Global IN non-periodic NAK effective */ -#define OTGFS_GINT_GONAKEFF (1 << 7) /* Bit 7: Global OUT NAK effective */ - /* Bits 8-9: Reserved, must be kept at reset value */ -#define OTGFS_GINT_ESUSP (1 << 10) /* Bit 10: Early suspend */ -#define OTGFS_GINT_USBSUSP (1 << 11) /* Bit 11: USB suspend */ -#define OTGFS_GINT_USBRST (1 << 12) /* Bit 12: USB reset */ -#define OTGFS_GINT_ENUMDNE (1 << 13) /* Bit 13: Enumeration done */ -#define OTGFS_GINT_ISOODRP (1 << 14) /* Bit 14: Isochronous OUT packet dropped interrupt */ -#define OTGFS_GINT_EOPF (1 << 15) /* Bit 15: End of periodic frame interrupt */ - /* Bits 16 Reserved, must be kept at reset value */ -#define OTGFS_GINTMSK_EPMISM (1 << 17) /* Bit 17: Endpoint mismatch interrupt mask */ -#define OTGFS_GINT_IEP (1 << 18) /* Bit 18: IN endpoint interrupt */ -#define OTGFS_GINT_OEP (1 << 19) /* Bit 19: OUT endpoint interrupt */ -#define OTGFS_GINT_IISOIXFR (1 << 20) /* Bit 20: Incomplete isochronous IN transfer */ -#define OTGFS_GINT_IISOOXFR (1 << 21) /* Bit 21: Incomplete isochronous OUT transfer (device) */ -#define OTGFS_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */ - /* Bits 22-23: Reserved, must be kept at reset value */ -#define OTGFS_GINT_HPRT (1 << 24) /* Bit 24: Host port interrupt */ -#define OTGFS_GINT_HC (1 << 25) /* Bit 25: Host channels interrupt */ -#define OTGFS_GINT_PTXFE (1 << 26) /* Bit 26: Periodic TxFIFO empty */ - /* Bit 27 Reserved, must be kept at reset value */ -#define OTGFS_GINT_CIDSCHG (1 << 28) /* Bit 28: Connector ID status change */ -#define OTGFS_GINT_DISC (1 << 29) /* Bit 29: Disconnect detected interrupt */ -#define OTGFS_GINT_SRQ (1 << 30) /* Bit 30: Session request/new session detected interrupt */ -#define OTGFS_GINT_WKUP (1 << 31) /* Bit 31: Resume/remote wakeup detected interrupt */ - -/* Receive status debug read/OTG status read and pop registers (host mode) */ - -#define OTGFS_GRXSTSH_CHNUM_SHIFT (0) /* Bits 0-3: Channel number */ -#define OTGFS_GRXSTSH_CHNUM_MASK (15 << OTGFS_GRXSTSH_CHNUM_SHIFT) -#define OTGFS_GRXSTSH_BCNT_SHIFT (4) /* Bits 4-14: Byte count */ -#define OTGFS_GRXSTSH_BCNT_MASK (0x7ff << OTGFS_GRXSTSH_BCNT_SHIFT) -#define OTGFS_GRXSTSH_DPID_SHIFT (15) /* Bits 15-16: Data PID */ -#define OTGFS_GRXSTSH_DPID_MASK (3 << OTGFS_GRXSTSH_DPID_SHIFT) -# define OTGFS_GRXSTSH_DPID_DATA0 (0 << OTGFS_GRXSTSH_DPID_SHIFT) -# define OTGFS_GRXSTSH_DPID_DATA2 (1 << OTGFS_GRXSTSH_DPID_SHIFT) -# define OTGFS_GRXSTSH_DPID_DATA1 (2 << OTGFS_GRXSTSH_DPID_SHIFT) -# define OTGFS_GRXSTSH_DPID_MDATA (3 << OTGFS_GRXSTSH_DPID_SHIFT) -#define OTGFS_GRXSTSH_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */ -#define OTGFS_GRXSTSH_PKTSTS_MASK (15 << OTGFS_GRXSTSH_PKTSTS_SHIFT) -# define OTGFS_GRXSTSH_PKTSTS_INRECVD (2 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* IN data packet received */ -# define OTGFS_GRXSTSH_PKTSTS_INDONE (3 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* IN transfer completed */ -# define OTGFS_GRXSTSH_PKTSTS_DTOGERR (5 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* Data toggle error */ -# define OTGFS_GRXSTSH_PKTSTS_HALTED (7 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* Channel halted */ - /* Bits 21-31: Reserved, must be kept at reset value */ -/* Receive status debug read/OTG status read and pop registers (device mode) */ - -#define OTGFS_GRXSTSD_EPNUM_SHIFT (0) /* Bits 0-3: Endpoint number */ -#define OTGFS_GRXSTSD_EPNUM_MASK (15 << OTGFS_GRXSTSD_EPNUM_SHIFT) -#define OTGFS_GRXSTSD_BCNT_SHIFT (4) /* Bits 4-14: Byte count */ -#define OTGFS_GRXSTSD_BCNT_MASK (0x7ff << OTGFS_GRXSTSD_BCNT_SHIFT) -#define OTGFS_GRXSTSD_DPID_SHIFT (15) /* Bits 15-16: Data PID */ -#define OTGFS_GRXSTSD_DPID_MASK (3 << OTGFS_GRXSTSD_DPID_SHIFT) -# define OTGFS_GRXSTSD_DPID_DATA0 (0 << OTGFS_GRXSTSD_DPID_SHIFT) -# define OTGFS_GRXSTSD_DPID_DATA2 (1 << OTGFS_GRXSTSD_DPID_SHIFT) -# define OTGFS_GRXSTSD_DPID_DATA1 (2 << OTGFS_GRXSTSD_DPID_SHIFT) -# define OTGFS_GRXSTSD_DPID_MDATA (3 << OTGFS_GRXSTSD_DPID_SHIFT) -#define OTGFS_GRXSTSD_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */ -#define OTGFS_GRXSTSD_PKTSTS_MASK (15 << OTGFS_GRXSTSD_PKTSTS_SHIFT) -# define OTGFS_GRXSTSD_PKTSTS_OUTNAK (1 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* Global OUT NAK */ -# define OTGFS_GRXSTSD_PKTSTS_OUTRECVD (2 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* OUT data packet received */ -# define OTGFS_GRXSTSD_PKTSTS_OUTDONE (3 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* OUT transfer completed */ -# define OTGFS_GRXSTSD_PKTSTS_SETUPDONE (4 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* SETUP transaction completed */ -# define OTGFS_GRXSTSD_PKTSTS_SETUPRECVD (6 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* SETUP data packet received */ -#define OTGFS_GRXSTSD_FRMNUM_SHIFT (21) /* Bits 21-24: Frame number */ -#define OTGFS_GRXSTSD_FRMNUM_MASK (15 << OTGFS_GRXSTSD_FRMNUM_SHIFT) - /* Bits 25-31: Reserved, must be kept at reset value */ -/* Receive FIFO size register */ - -#define OTGFS_GRXFSIZ_MASK (0xffff) - -/* Host non-periodic transmit FIFO size register */ - -#define OTGFS_HNPTXFSIZ_NPTXFSA_SHIFT (0) /* Bits 0-15: Non-periodic transmit RAM start address */ -#define OTGFS_HNPTXFSIZ_NPTXFSA_MASK (0xffff << OTGFS_HNPTXFSIZ_NPTXFSA_SHIFT) -#define OTGFS_HNPTXFSIZ_NPTXFD_SHIFT (16) /* Bits 16-31: Non-periodic TxFIFO depth */ -#define OTGFS_HNPTXFSIZ_NPTXFD_MASK (0xffff << OTGFS_HNPTXFSIZ_NPTXFD_SHIFT) -# define OTGFS_HNPTXFSIZ_NPTXFD_MIN (16 << OTGFS_HNPTXFSIZ_NPTXFD_SHIFT) -# define OTGFS_HNPTXFSIZ_NPTXFD_MAX (256 << OTGFS_HNPTXFSIZ_NPTXFD_SHIFT) - -/* Endpoint 0 Transmit FIFO size */ - -#define OTGFS_DIEPTXF0_TX0FD_SHIFT (0) /* Bits 0-15: Endpoint 0 transmit RAM start address */ -#define OTGFS_DIEPTXF0_TX0FD_MASK (0xffff << OTGFS_DIEPTXF0_TX0FD_SHIFT) -#define OTGFS_DIEPTXF0_TX0FSA_SHIFT (16) /* Bits 16-31: Endpoint 0 TxFIFO depth */ -#define OTGFS_DIEPTXF0_TX0FSA_MASK (0xffff << OTGFS_DIEPTXF0_TX0FSA_SHIFT) -# define OTGFS_DIEPTXF0_TX0FSA_MIN (16 << OTGFS_DIEPTXF0_TX0FSA_SHIFT) -# define OTGFS_DIEPTXF0_TX0FSA_MAX (256 << OTGFS_DIEPTXF0_TX0FSA_SHIFT) - -/* Non-periodic transmit FIFO/queue status register */ - -#define OTGFS_HNPTXSTS_NPTXFSAV_SHIFT (0) /* Bits 0-15: Non-periodic TxFIFO space available */ -#define OTGFS_HNPTXSTS_NPTXFSAV_MASK (0xffff << OTGFS_HNPTXSTS_NPTXFSAV_SHIFT) -# define OTGFS_HNPTXSTS_NPTXFSAV_FULL (0 << OTGFS_HNPTXSTS_NPTXFSAV_SHIFT) -#define OTGFS_HNPTXSTS_NPTQXSAV_SHIFT (16) /* Bits 16-23: Non-periodic transmit request queue space available */ -#define OTGFS_HNPTXSTS_NPTQXSAV_MASK (0xff << OTGFS_HNPTXSTS_NPTQXSAV_SHIFT) -# define OTGFS_HNPTXSTS_NPTQXSAV_FULL (0 << OTGFS_HNPTXSTS_NPTQXSAV_SHIFT) -#define OTGFS_HNPTXSTS_NPTXQTOP_SHIFT (24) /* Bits 24-30: Top of the non-periodic transmit request queue */ -#define OTGFS_HNPTXSTS_NPTXQTOP_MASK (0x7f << OTGFS_HNPTXSTS_NPTXQTOP_SHIFT) -# define OTGFS_HNPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */ -# define OTGFS_HNPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Status */ -# define OTGFS_HNPTXSTS_TYPE_MASK (3 << OTGFS_HNPTXSTS_TYPE_SHIFT) -# define OTGFS_HNPTXSTS_TYPE_INOUT (0 << OTGFS_HNPTXSTS_TYPE_SHIFT) /* IN/OUT token */ -# define OTGFS_HNPTXSTS_TYPE_ZLP (1 << OTGFS_HNPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet (device IN/host OUT) */ -# define OTGFS_HNPTXSTS_TYPE_HALT (3 << OTGFS_HNPTXSTS_TYPE_SHIFT) /* Channel halt command */ -# define OTGFS_HNPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */ -# define OTGFS_HNPTXSTS_CHNUM_MASK (15 << OTGFS_HNPTXSTS_CHNUM_SHIFT) -# define OTGFS_HNPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */ -# define OTGFS_HNPTXSTS_EPNUM_MASK (15 << OTGFS_HNPTXSTS_EPNUM_SHIFT) - /* Bit 31 Reserved, must be kept at reset value */ -/* General core configuration register */ - /* Bits 15:0 Reserved, must be kept at reset value */ -#define OTGFS_GCCFG_PWRDWN (1 << 16) /* Bit 16: Power down */ - /* Bit 17 Reserved, must be kept at reset value */ -#define OTGFS_GCCFG_VBUSASEN (1 << 18) /* Bit 18: Enable the VBUS sensing “A” device */ -#define OTGFS_GCCFG_VBUSBSEN (1 << 19) /* Bit 19: Enable the VBUS sensing “B” device */ -#define OTGFS_GCCFG_SOFOUTEN (1 << 20) /* Bit 20: SOF output enable */ -#define OTGFS_GCCFG_NOVBUSSENS (1 << 21) /* Bit 21: VBUS sensing disable option */ - /* Bits 31:22 Reserved, must be kept at reset value */ -/* Core ID register (32-bit product ID) */ - -/* Host periodic transmit FIFO size register */ - -#define OTGFS_HPTXFSIZ_PTXSA_SHIFT (0) /* Bits 0-15: Host periodic TxFIFO start address */ -#define OTGFS_HPTXFSIZ_PTXSA_MASK (0xffff << OTGFS_HPTXFSIZ_PTXSA_SHIFT) -#define OTGFS_HPTXFSIZ_PTXFD_SHIFT (16) /* Bits 16-31: Host periodic TxFIFO depth */ -#define OTGFS_HPTXFSIZ_PTXFD_MASK (0xffff << OTGFS_HPTXFSIZ_PTXFD_SHIFT) - -/* Device IN endpoint transmit FIFOn size register */ - -#define OTGFS_DIEPTXF_INEPTXSA_SHIFT (0) /* Bits 0-15: IN endpoint FIFOx transmit RAM start address */ -#define OTGFS_DIEPTXF_INEPTXSA_MASK (0xffff << OTGFS_DIEPTXF_INEPTXSA_SHIFT) -#define OTGFS_DIEPTXF_INEPTXFD_SHIFT (16) /* Bits 16-31: IN endpoint TxFIFO depth */ -#define OTGFS_DIEPTXF_INEPTXFD_MASK (0xffff << OTGFS_DIEPTXF_INEPTXFD_SHIFT) -# define OTGFS_DIEPTXF_INEPTXFD_MIN (16 << OTGFS_DIEPTXF_INEPTXFD_MASK) - -/* Host-mode control and status registers */ - -/* Host configuration register */ - -#define OTGFS_HCFG_FSLSPCS_SHIFT (0) /* Bits 0-1: FS/LS PHY clock select */ -#define OTGFS_HCFG_FSLSPCS_MASK (3 << OTGFS_HCFG_FSLSPCS_SHIFT) -# define OTGFS_HCFG_FSLSPCS_FS48MHz (1 << OTGFS_HCFG_FSLSPCS_SHIFT) /* FS host mode, PHY clock is running at 48 MHz */ -# define OTGFS_HCFG_FSLSPCS_LS48MHz (1 << OTGFS_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 48 MHz PHY clock frequency */ -# define OTGFS_HCFG_FSLSPCS_LS6MHz (2 << OTGFS_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 6 MHz PHY clock frequency */ -#define OTGFS_HCFG_FSLSS (1 << 2) /* Bit 2: FS- and LS-only support */ - /* Bits 31:3 Reserved, must be kept at reset value */ -/* Host frame interval register */ - -#define OTGFS_HFIR_MASK (0xffff) - -/* Host frame number/frame time remaining register */ - -#define OTGFS_HFNUM_FRNUM_SHIFT (0) /* Bits 0-15: Frame number */ -#define OTGFS_HFNUM_FRNUM_MASK (0xffff << OTGFS_HFNUM_FRNUM_SHIFT) -#define OTGFS_HFNUM_FTREM_SHIFT (16) /* Bits 16-31: Frame time remaining */ -#define OTGFS_HFNUM_FTREM_MASK (0xffff << OTGFS_HFNUM_FTREM_SHIFT) - -/* Host periodic transmit FIFO/queue status register */ - -#define OTGFS_HPTXSTS_PTXFSAVL_SHIFT (0) /* Bits 0-15: Periodic transmit data FIFO space available */ -#define OTGFS_HPTXSTS_PTXFSAVL_MASK (0xffff << OTGFS_HPTXSTS_PTXFSAVL_SHIFT) -# define OTGFS_HPTXSTS_PTXFSAVL_FULL (0 << OTGFS_HPTXSTS_PTXFSAVL_SHIFT) -#define OTGFS_HPTXSTS_PTXQSAV_SHIFT (16) /* Bits 16-23: Periodic transmit request queue space available */ -#define OTGFS_HPTXSTS_PTXQSAV_MASK (0xff << OTGFS_HPTXSTS_PTXQSAV_SHIFT) -# define OTGFS_HPTXSTS_PTXQSAV_FULL (0 << OTGFS_HPTXSTS_PTXQSAV_SHIFT) -#define OTGFS_HPTXSTS_PTXQTOP_SHIFT (24) /* Bits 24-31: Top of the periodic transmit request queue */ -#define OTGFS_HPTXSTS_PTXQTOP_MASK (0x7f << OTGFS_HPTXSTS_PTXQTOP_SHIFT) -# define OTGFS_HPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */ -# define OTGFS_HPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Type */ -# define OTGFS_HPTXSTS_TYPE_MASK (3 << OTGFS_HPTXSTS_TYPE_SHIFT) -# define OTGFS_HPTXSTS_TYPE_INOUT (0 << OTGFS_HPTXSTS_TYPE_SHIFT) /* IN/OUT token */ -# define OTGFS_HPTXSTS_TYPE_ZLP (1 << OTGFS_HPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet */ -# define OTGFS_HPTXSTS_TYPE_HALT (3 << OTGFS_HPTXSTS_TYPE_SHIFT) /* Disable channel command */ -# define OTGFS_HPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */ -# define OTGFS_HPTXSTS_EPNUM_MASK (15 << OTGFS_HPTXSTS_EPNUM_SHIFT) -# define OTGFS_HPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */ -# define OTGFS_HPTXSTS_CHNUM_MASK (15 << OTGFS_HPTXSTS_CHNUM_SHIFT) -# define OTGFS_HPTXSTS_ODD (1 << 24) /* Bit 31: Send in odd (vs even) frame */ - -/* Host all channels interrupt and all channels interrupt mask registers */ - -#define OTGFS_HAINT(n) (1 << (n)) /* Bits 15:0 HAINTM: Channel interrupt */ - -/* Host port control and status register */ - -#define OTGFS_HPRT_PCSTS (1 << 0) /* Bit 0: Port connect status */ -#define OTGFS_HPRT_PCDET (1 << 1) /* Bit 1: Port connect detected */ -#define OTGFS_HPRT_PENA (1 << 2) /* Bit 2: Port enable */ -#define OTGFS_HPRT_PENCHNG (1 << 3) /* Bit 3: Port enable/disable change */ -#define OTGFS_HPRT_POCA (1 << 4) /* Bit 4: Port overcurrent active */ -#define OTGFS_HPRT_POCCHNG (1 << 5) /* Bit 5: Port overcurrent change */ -#define OTGFS_HPRT_PRES (1 << 6) /* Bit 6: Port resume */ -#define OTGFS_HPRT_PSUSP (1 << 7) /* Bit 7: Port suspend */ -#define OTGFS_HPRT_PRST (1 << 8) /* Bit 8: Port reset */ - /* Bit 9: Reserved, must be kept at reset value */ -#define OTGFS_HPRT_PLSTS_SHIFT (10) /* Bits 10-11: Port line status */ -#define OTGFS_HPRT_PLSTS_MASK (3 << OTGFS_HPRT_PLSTS_SHIFT) -# define OTGFS_HPRT_PLSTS_DP (1 << 10) /* Bit 10: Logic level of OTG_FS_FS_DP */ -# define OTGFS_HPRT_PLSTS_DM (1 << 11) /* Bit 11: Logic level of OTG_FS_FS_DM */ -#define OTGFS_HPRT_PPWR (1 << 12) /* Bit 12: Port power */ -#define OTGFS_HPRT_PTCTL_SHIFT (13) /* Bits 13-16: Port test control */ -#define OTGFS_HPRT_PTCTL_MASK (15 << OTGFS_HPRT_PTCTL_SHIFT) -# define OTGFS_HPRT_PTCTL_DISABLED (0 << OTGFS_HPRT_PTCTL_SHIFT) /* Test mode disabled */ -# define OTGFS_HPRT_PTCTL_J (1 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_J mode */ -# define OTGFS_HPRT_PTCTL_L (2 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_K mode */ -# define OTGFS_HPRT_PTCTL_SE0_NAK (3 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_SE0_NAK mode */ -# define OTGFS_HPRT_PTCTL_PACKET (4 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_Packet mode */ -# define OTGFS_HPRT_PTCTL_FORCE (5 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_Force_Enable */ -#define OTGFS_HPRT_PSPD_SHIFT (17) /* Bits 17-18: Port speed */ -#define OTGFS_HPRT_PSPD_MASK (3 << OTGFS_HPRT_PSPD_SHIFT) -# define OTGFS_HPRT_PSPD_FS (1 << OTGFS_HPRT_PSPD_SHIFT) /* Full speed */ -# define OTGFS_HPRT_PSPD_LS (2 << OTGFS_HPRT_PSPD_SHIFT) /* Low speed */ - /* Bits 19-31: Reserved, must be kept at reset value */ - -/* Host channel-n characteristics register */ - -#define OTGFS_HCCHAR_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ -#define OTGFS_HCCHAR_MPSIZ_MASK (0x7ff << OTGFS_HCCHAR_MPSIZ_SHIFT) -#define OTGFS_HCCHAR_EPNUM_SHIFT (11) /* Bits 11-14: Endpoint number */ -#define OTGFS_HCCHAR_EPNUM_MASK (15 << OTGFS_HCCHAR_EPNUM_SHIFT) -#define OTGFS_HCCHAR_EPDIR (1 << 15) /* Bit 15: Endpoint direction */ -# define OTGFS_HCCHAR_EPDIR_OUT (0) -# define OTGFS_HCCHAR_EPDIR_IN OTGFS_HCCHAR_EPDIR - /* Bit 16 Reserved, must be kept at reset value */ -#define OTGFS_HCCHAR_LSDEV (1 << 17) /* Bit 17: Low-speed device */ -#define OTGFS_HCCHAR_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ -#define OTGFS_HCCHAR_EPTYP_MASK (3 << OTGFS_HCCHAR_EPTYP_SHIFT) -# define OTGFS_HCCHAR_EPTYP_CTRL (0 << OTGFS_HCCHAR_EPTYP_SHIFT) /* Control */ -# define OTGFS_HCCHAR_EPTYP_ISOC (1 << OTGFS_HCCHAR_EPTYP_SHIFT) /* Isochronous */ -# define OTGFS_HCCHAR_EPTYP_BULK (2 << OTGFS_HCCHAR_EPTYP_SHIFT) /* Bulk */ -# define OTGFS_HCCHAR_EPTYP_INTR (3 << OTGFS_HCCHAR_EPTYP_SHIFT) /* Interrupt */ -#define OTGFS_HCCHAR_MCNT_SHIFT (20) /* Bits 20-21: Multicount */ -#define OTGFS_HCCHAR_MCNT_MASK (3 << OTGFS_HCCHAR_MCNT_SHIFT) -#define OTGFS_HCCHAR_DAD_SHIFT (22) /* Bits 22-28: Device address */ -#define OTGFS_HCCHAR_DAD_MASK (0x7f << OTGFS_HCCHAR_DAD_SHIFT) -#define OTGFS_HCCHAR_ODDFRM (1 << 29) /* Bit 29: Odd frame */ -#define OTGFS_HCCHAR_CHDIS (1 << 30) /* Bit 30: Channel disable */ -#define OTGFS_HCCHAR_CHENA (1 << 31) /* Bit 31: Channel enable */ - -/* Host channel-n interrupt and Host channel-0 interrupt mask registers */ - -#define OTGFS_HCINT_XFRC (1 << 0) /* Bit 0: Transfer completed */ -#define OTGFS_HCINT_CHH (1 << 1) /* Bit 1: Channel halted */ - /* Bit 2: Reserved, must be kept at reset value */ -#define OTGFS_HCINT_STALL (1 << 3) /* Bit 3: STALL response received interrupt */ -#define OTGFS_HCINT_NAK (1 << 4) /* Bit 4: NAK response received interrupt */ -#define OTGFS_HCINT_ACK (1 << 5) /* Bit 5: ACK response received/transmitted interrupt */ -#define OTGFS_HCINT_NYET (1 << 6) /* Bit 6: Response received interrupt */ -#define OTGFS_HCINT_TXERR (1 << 7) /* Bit 7: Transaction error */ -#define OTGFS_HCINT_BBERR (1 << 8) /* Bit 8: Babble error */ -#define OTGFS_HCINT_FRMOR (1 << 9) /* Bit 9: Frame overrun */ -#define OTGFS_HCINT_DTERR (1 << 10) /* Bit 10: Data toggle error */ - /* Bits 11-31 Reserved, must be kept at reset value */ -/* Host channel-n interrupt register */ - -#define OTGFS_HCTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ -#define OTGFS_HCTSIZ_XFRSIZ_MASK (0x7ffff << OTGFS_HCTSIZ_XFRSIZ_SHIFT) -#define OTGFS_HCTSIZ_PKTCNT_SHIFT (19) /* Bits 19-28: Packet count */ -#define OTGFS_HCTSIZ_PKTCNT_MASK (0x3ff << OTGFS_HCTSIZ_PKTCNT_SHIFT) -#define OTGFS_HCTSIZ_DPID_SHIFT (29) /* Bits 29-30: Data PID */ -#define OTGFS_HCTSIZ_DPID_MASK (3 << OTGFS_HCTSIZ_DPID_SHIFT) -# define OTGFS_HCTSIZ_DPID_DATA0 (0 << OTGFS_HCTSIZ_DPID_SHIFT) -# define OTGFS_HCTSIZ_DPID_DATA2 (1 << OTGFS_HCTSIZ_DPID_SHIFT) -# define OTGFS_HCTSIZ_DPID_DATA1 (2 << OTGFS_HCTSIZ_DPID_SHIFT) -# define OTGFS_HCTSIZ_DPID_MDATA (3 << OTGFS_HCTSIZ_DPID_SHIFT) /* Non-control */ -# define OTGFS_HCTSIZ_PID_SETUP (3 << OTGFS_HCTSIZ_DPID_SHIFT) /* Control */ - /* Bit 31 Reserved, must be kept at reset value */ -/* Device-mode control and status registers */ - -/* Device configuration register */ - -#define OTGFS_DCFG_DSPD_SHIFT (0) /* Bits 0-1: Device speed */ -#define OTGFS_DCFG_DSPD_MASK (3 << OTGFS_DCFG_DSPD_SHIFT) -# define OTGFS_DCFG_DSPD_FS (3 << OTGFS_DCFG_DSPD_SHIFT) /* Full speed */ -#define OTGFS_DCFG_NZLSOHSK (1 << 2) /* Bit 2: Non-zero-length status OUT handshake */ - /* Bit 3: Reserved, must be kept at reset value */ -#define OTGFS_DCFG_DAD_SHIFT (4) /* Bits 4-10: Device address */ -#define OTGFS_DCFG_DAD_MASK (0x7f << OTGFS_DCFG_DAD_SHIFT) -#define OTGFS_DCFG_PFIVL_SHIFT (11) /* Bits 11-12: Periodic frame interval */ -#define OTGFS_DCFG_PFIVL_MASK (3 << OTGFS_DCFG_PFIVL_SHIFT) -# define OTGFS_DCFG_PFIVL_80PCT (0 << OTGFS_DCFG_PFIVL_SHIFT) /* 80% of the frame interval */ -# define OTGFS_DCFG_PFIVL_85PCT (1 << OTGFS_DCFG_PFIVL_SHIFT) /* 85% of the frame interval */ -# define OTGFS_DCFG_PFIVL_90PCT (2 << OTGFS_DCFG_PFIVL_SHIFT) /* 90% of the frame interval */ -# define OTGFS_DCFG_PFIVL_95PCT (3 << OTGFS_DCFG_PFIVL_SHIFT) /* 95% of the frame interval */ - /* Bits 13-31 Reserved, must be kept at reset value */ -/* Device control register */ - -#define OTGFS_TESTMODE_DISABLED (0) /* Test mode disabled */ -#define OTGFS_TESTMODE_J (1) /* Test_J mode */ -#define OTGFS_TESTMODE_K (2) /* Test_K mode */ -#define OTGFS_TESTMODE_SE0_NAK (3) /* Test_SE0_NAK mode */ -#define OTGFS_TESTMODE_PACKET (4) /* Test_Packet mode */ -#define OTGFS_TESTMODE_FORCE (5) /* Test_Force_Enable */ - -#define OTGFS_DCTL_RWUSIG (1 << 0) /* Bit 0: Remote wakeup signaling */ -#define OTGFS_DCTL_SDIS (1 << 1) /* Bit 1: Soft disconnect */ -#define OTGFS_DCTL_GINSTS (1 << 2) /* Bit 2: Global IN NAK status */ -#define OTGFS_DCTL_GONSTS (1 << 3) /* Bit 3: Global OUT NAK status */ -#define OTGFS_DCTL_TCTL_SHIFT (4) /* Bits 4-6: Test control */ -#define OTGFS_DCTL_TCTL_MASK (7 << OTGFS_DCTL_TCTL_SHIFT) -# define OTGFS_DCTL_TCTL_DISABLED (0 << OTGFS_DCTL_TCTL_SHIFT) /* Test mode disabled */ -# define OTGFS_DCTL_TCTL_J (1 << OTGFS_DCTL_TCTL_SHIFT) /* Test_J mode */ -# define OTGFS_DCTL_TCTL_K (2 << OTGFS_DCTL_TCTL_SHIFT) /* Test_K mode */ -# define OTGFS_DCTL_TCTL_SE0_NAK (3 << OTGFS_DCTL_TCTL_SHIFT) /* Test_SE0_NAK mode */ -# define OTGFS_DCTL_TCTL_PACKET (4 << OTGFS_DCTL_TCTL_SHIFT) /* Test_Packet mode */ -# define OTGFS_DCTL_TCTL_FORCE (5 << OTGFS_DCTL_TCTL_SHIFT) /* Test_Force_Enable */ -#define OTGFS_DCTL_SGINAK (1 << 7) /* Bit 7: Set global IN NAK */ -#define OTGFS_DCTL_CGINAK (1 << 8) /* Bit 8: Clear global IN NAK */ -#define OTGFS_DCTL_SGONAK (1 << 9) /* Bit 9: Set global OUT NAK */ -#define OTGFS_DCTL_CGONAK (1 << 10) /* Bit 10: Clear global OUT NAK */ -#define OTGFS_DCTL_POPRGDNE (1 << 11) /* Bit 11: Power-on programming done */ - /* Bits 12-31: Reserved, must be kept at reset value */ -/* Device status register */ - -#define OTGFS_DSTS_SUSPSTS (1 << 0) /* Bit 0: Suspend status */ -#define OTGFS_DSTS_ENUMSPD_SHIFT (1) /* Bits 1-2: Enumerated speed */ -#define OTGFS_DSTS_ENUMSPD_MASK (3 << OTGFS_DSTS_ENUMSPD_SHIFT) -# define OTGFS_DSTS_ENUMSPD_FS (3 << OTGFS_DSTS_ENUMSPD_MASK) /* Full speed */ - /* Bits 4-7: Reserved, must be kept at reset value */ -#define OTGFS_DSTS_EERR (1 << 3) /* Bit 3: Erratic error */ -#define OTGFS_DSTS_SOFFN_SHIFT (8) /* Bits 8-21: Frame number of the received SOF */ -#define OTGFS_DSTS_SOFFN_MASK (0x3fff << OTGFS_DSTS_SOFFN_SHIFT) -#define OTGFS_DSTS_SOFFN0 (1 << 8) /* Bits 8: Frame number even/odd bit */ -#define OTGFS_DSTS_SOFFN_EVEN 0 -#define OTGFS_DSTS_SOFFN_ODD OTGFS_DSTS_SOFFN0 - /* Bits 22-31: Reserved, must be kept at reset value */ -/* Device IN endpoint common interrupt mask register */ - -#define OTGFS_DIEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */ -#define OTGFS_DIEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */ - /* Bit 2: Reserved, must be kept at reset value */ -#define OTGFS_DIEPMSK_TOM (1 << 3) /* Bit 3: Timeout condition mask (Non-isochronous endpoints) */ -#define OTGFS_DIEPMSK_ITTXFEMSK (1 << 4) /* Bit 4: IN token received when TxFIFO empty mask */ -#define OTGFS_DIEPMSK_INEPNMM (1 << 5) /* Bit 5: IN token received with EP mismatch mask */ -#define OTGFS_DIEPMSK_INEPNEM (1 << 6) /* Bit 6: IN endpoint NAK effective mask */ - /* Bits 7-31: Reserved, must be kept at reset value */ -/* Device OUT endpoint common interrupt mask register */ - -#define OTGFS_DOEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */ -#define OTGFS_DOEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */ - /* Bit 2: Reserved, must be kept at reset value */ -#define OTGFS_DOEPMSK_STUPM (1 << 3) /* Bit 3: SETUP phase done mask */ -#define OTGFS_DOEPMSK_OTEPDM (1 << 4) /* Bit 4: OUT token received when endpoint disabled mask */ - /* Bits 5-31: Reserved, must be kept at reset value */ -/* Device all endpoints interrupt and All endpoints interrupt mask registers */ - -#define OTGFS_DAINT_IEP_SHIFT (0) /* Bits 0-15: IN endpoint interrupt bits */ -#define OTGFS_DAINT_IEP_MASK (0xffff << OTGFS_DAINT_IEP_SHIFT) -# define OTGFS_DAINT_IEP(n) (1 << (n)) -#define OTGFS_DAINT_OEP_SHIFT (16) /* Bits 16-31: OUT endpoint interrupt bits */ -#define OTGFS_DAINT_OEP_MASK (0xffff << OTGFS_DAINT_OEP_SHIFT) -# define OTGFS_DAINT_OEP(n) (1 << ((n)+16)) - -/* Device VBUS discharge time register */ - -#define OTGFS_DVBUSDIS_MASK (0xffff) - -/* Device VBUS pulsing time register */ - -#define OTGFS_DVBUSPULSE_MASK (0xfff) - -/* Device IN endpoint FIFO empty interrupt mask register */ - -#define OTGFS_DIEPEMPMSK(n) (1 << (n)) - -/* Device control IN endpoint 0 control register */ - -#define OTGFS_DIEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */ -#define OTGFS_DIEPCTL0_MPSIZ_MASK (3 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) -# define OTGFS_DIEPCTL0_MPSIZ_64 (0 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) /* 64 bytes */ -# define OTGFS_DIEPCTL0_MPSIZ_32 (1 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) /* 32 bytes */ -# define OTGFS_DIEPCTL0_MPSIZ_16 (2 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) /* 16 bytes */ -# define OTGFS_DIEPCTL0_MPSIZ_8 (3 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) /* 8 bytes */ - /* Bits 2-14: Reserved, must be kept at reset value */ -#define OTGFS_DIEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ - /* Bit 16: Reserved, must be kept at reset value */ -#define OTGFS_DIEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */ -#define OTGFS_DIEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ -#define OTGFS_DIEPCTL0_EPTYP_MASK (3 << OTGFS_DIEPCTL0_EPTYP_SHIFT) -# define OTGFS_DIEPCTL0_EPTYP_CTRL (0 << OTGFS_DIEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */ - /* Bit 20: Reserved, must be kept at reset value */ -#define OTGFS_DIEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */ -#define OTGFS_DIEPCTL0_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */ -#define OTGFS_DIEPCTL0_TXFNUM_MASK (15 << OTGFS_DIEPCTL0_TXFNUM_SHIFT) -#define OTGFS_DIEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */ -#define OTGFS_DIEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */ - /* Bits 28-29: Reserved, must be kept at reset value */ -#define OTGFS_DIEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ -#define OTGFS_DIEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */ - -/* Device control IN endpoint n control register */ - -#define OTGFS_DIEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ -#define OTGFS_DIEPCTL_MPSIZ_MASK (0x7ff << OTGFS_DIEPCTL_MPSIZ_SHIFT) - /* Bits 11-14: Reserved, must be kept at reset value */ -#define OTGFS_DIEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ -#define OTGFS_DIEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame */ -# define OTGFS_DIEPCTL_EVEN (0) -# define OTGFS_DIEPCTL_ODD OTGFS_DIEPCTL_EONUM -# define OTGFS_DIEPCTL_DATA0 (0) -# define OTGFS_DIEPCTL_DATA1 OTGFS_DIEPCTL_EONUM -#define OTGFS_DIEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */ -#define OTGFS_DIEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ -#define OTGFS_DIEPCTL_EPTYP_MASK (3 << OTGFS_DIEPCTL_EPTYP_SHIFT) -# define OTGFS_DIEPCTL_EPTYP_CTRL (0 << OTGFS_DIEPCTL_EPTYP_SHIFT) /* Control */ -# define OTGFS_DIEPCTL_EPTYP_ISOC (1 << OTGFS_DIEPCTL_EPTYP_SHIFT) /* Isochronous */ -# define OTGFS_DIEPCTL_EPTYP_BULK (2 << OTGFS_DIEPCTL_EPTYP_SHIFT) /* Bulk */ -# define OTGFS_DIEPCTL_EPTYP_INTR (3 << OTGFS_DIEPCTL_EPTYP_SHIFT) /* Interrupt */ - /* Bit 20: Reserved, must be kept at reset value */ -#define OTGFS_DIEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */ -#define OTGFS_DIEPCTL_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */ -#define OTGFS_DIEPCTL_TXFNUM_MASK (15 << OTGFS_DIEPCTL_TXFNUM_SHIFT) -#define OTGFS_DIEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */ -#define OTGFS_DIEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */ -#define OTGFS_DIEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */ -#define OTGFS_DIEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous)) */ -#define OTGFS_DIEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous) */ -#define OTGFS_DIEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ -#define OTGFS_DIEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */ - -/* Device endpoint-n interrupt register */ - -#define OTGFS_DIEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */ -#define OTGFS_DIEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */ - /* Bit 2: Reserved, must be kept at reset value */ -#define OTGFS_DIEPINT_TOC (1 << 3) /* Bit 3: Timeout condition */ -#define OTGFS_DIEPINT_ITTXFE (1 << 4) /* Bit 4: IN token received when TxFIFO is empty */ - /* Bit 5: Reserved, must be kept at reset value */ -#define OTGFS_DIEPINT_INEPNE (1 << 6) /* Bit 6: IN endpoint NAK effective */ -#define OTGFS_DIEPINT_TXFE (1 << 7) /* Bit 7: Transmit FIFO empty */ - /* Bits 8-31: Reserved, must be kept at reset value */ -/* Device IN endpoint 0 transfer size register */ - -#define OTGFS_DIEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */ -#define OTGFS_DIEPTSIZ0_XFRSIZ_MASK (0x7f << OTGFS_DIEPTSIZ0_XFRSIZ_SHIFT) - /* Bits 7-18: Reserved, must be kept at reset value */ -#define OTGFS_DIEPTSIZ0_PKTCNT_SHIFT (19) /* Bits 19-20: Packet count */ -#define OTGFS_DIEPTSIZ0_PKTCNT_MASK (3 << OTGFS_DIEPTSIZ0_PKTCNT_SHIFT) - /* Bits 21-31: Reserved, must be kept at reset value */ -/* Device IN endpoint n transfer size register */ - -#define OTGFS_DIEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ -#define OTGFS_DIEPTSIZ_XFRSIZ_MASK (0x7ffff << OTGFS_DIEPTSIZ_XFRSIZ_SHIFT) -#define OTGFS_DIEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */ -#define OTGFS_DIEPTSIZ_PKTCNT_MASK (0x3ff << OTGFS_DIEPTSIZ_PKTCNT_SHIFT) -#define OTGFS_DIEPTSIZ_MCNT_SHIFT (29) /* Bits 29-30: Multi count */ -#define OTGFS_DIEPTSIZ_MCNT_MASK (3 << OTGFS_DIEPTSIZ_MCNT_SHIFT) - /* Bit 31: Reserved, must be kept at reset value */ -/* Device OUT endpoint TxFIFO status register */ - -#define OTGFS_DTXFSTS_MASK (0xffff) - -/* Device OUT endpoint 0 control register */ - -#define OTGFS_DOEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */ -#define OTGFS_DOEPCTL0_MPSIZ_MASK (3 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) -# define OTGFS_DOEPCTL0_MPSIZ_64 (0 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) /* 64 bytes */ -# define OTGFS_DOEPCTL0_MPSIZ_32 (1 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) /* 32 bytes */ -# define OTGFS_DOEPCTL0_MPSIZ_16 (2 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) /* 16 bytes */ -# define OTGFS_DOEPCTL0_MPSIZ_8 (3 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) /* 8 bytes */ - /* Bits 2-14: Reserved, must be kept at reset value */ -#define OTGFS_DOEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ - /* Bit 16: Reserved, must be kept at reset value */ -#define OTGFS_DOEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */ -#define OTGFS_DOEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ -#define OTGFS_DOEPCTL0_EPTYP_MASK (3 << OTGFS_DOEPCTL0_EPTYP_SHIFT) -# define OTGFS_DOEPCTL0_EPTYP_CTRL (0 << OTGFS_DOEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */ -#define OTGFS_DOEPCTL0_SNPM (1 << 20) /* Bit 20: Snoop mode */ -#define OTGFS_DOEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */ - /* Bits 22-25: Reserved, must be kept at reset value */ -#define OTGFS_DOEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */ -#define OTGFS_DOEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */ - /* Bits 28-29: Reserved, must be kept at reset value */ -#define OTGFS_DOEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ -#define OTGFS_DOEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */ - -/* Device OUT endpoint n control register */ - -#define OTGFS_DOEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ -#define OTGFS_DOEPCTL_MPSIZ_MASK (0x7ff << OTGFS_DOEPCTL_MPSIZ_SHIFT) - /* Bits 11-14: Reserved, must be kept at reset value */ -#define OTGFS_DOEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ -#define OTGFS_DOEPCTL_DPID (1 << 16) /* Bit 16: Endpoint data PID (interrupt/buld) */ -# define OTGFS_DOEPCTL_DATA0 (0) -# define OTGFS_DOEPCTL_DATA1 OTGFS_DOEPCTL_DPID -#define OTGFS_DOEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame (isochronous) */ -# define OTGFS_DOEPCTL_EVEN (0) -# define OTGFS_DOEPCTL_ODD OTGFS_DOEPCTL_EONUM -#define OTGFS_DOEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */ -#define OTGFS_DOEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ -#define OTGFS_DOEPCTL_EPTYP_MASK (3 << OTGFS_DOEPCTL_EPTYP_SHIFT) -# define OTGFS_DOEPCTL_EPTYP_CTRL (0 << OTGFS_DOEPCTL_EPTYP_SHIFT) /* Control */ -# define OTGFS_DOEPCTL_EPTYP_ISOC (1 << OTGFS_DOEPCTL_EPTYP_SHIFT) /* Isochronous */ -# define OTGFS_DOEPCTL_EPTYP_BULK (2 << OTGFS_DOEPCTL_EPTYP_SHIFT) /* Bulk */ -# define OTGFS_DOEPCTL_EPTYP_INTR (3 << OTGFS_DOEPCTL_EPTYP_SHIFT) /* Interrupt */ -#define OTGFS_DOEPCTL_SNPM (1 << 20) /* Bit 20: Snoop mode */ -#define OTGFS_DOEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */ - /* Bits 22-25: Reserved, must be kept at reset value */ -#define OTGFS_DOEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */ -#define OTGFS_DOEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */ -#define OTGFS_DOEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */ -#define OTGFS_DOEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous) */ -#define OTGFS_DOEPCTL_SD1PID (1 << 29) /* Bit 29: Set DATA1 PID (interrupt/bulk) */ -#define OTGFS_DOEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous */ -#define OTGFS_DOEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ -#define OTGFS_DOEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */ - -/* Device endpoint-n interrupt register */ - -#define OTGFS_DOEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */ -#define OTGFS_DOEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */ - /* Bit 2: Reserved, must be kept at reset value */ -#define OTGFS_DOEPINT_SETUP (1 << 3) /* Bit 3: SETUP phase done */ -#define OTGFS_DOEPINT_OTEPDIS (1 << 4) /* Bit 4: OUT token received when endpoint disabled */ - /* Bit 5: Reserved, must be kept at reset value */ -#define OTGFS_DOEPINT_B2BSTUP (1 << 6) /* Bit 6: Back-to-back SETUP packets received */ - /* Bits 7-31: Reserved, must be kept at reset value */ -/* Device OUT endpoint-0 transfer size register */ - -#define OTGFS_DOEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */ -#define OTGFS_DOEPTSIZ0_XFRSIZ_MASK (0x7f << OTGFS_DOEPTSIZ0_XFRSIZ_SHIFT) - /* Bits 7-18: Reserved, must be kept at reset value */ -#define OTGFS_DOEPTSIZ0_PKTCNT (1 << 19) /* Bit 19 PKTCNT: Packet count */ - /* Bits 20-28: Reserved, must be kept at reset value */ -#define OTGFS_DOEPTSIZ0_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */ -#define OTGFS_DOEPTSIZ0_STUPCNT_MASK (3 << OTGFS_DOEPTSIZ0_STUPCNT_SHIFT) - /* Bit 31: Reserved, must be kept at reset value */ -/* Device OUT endpoint-n transfer size register */ - -#define OTGFS_DOEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ -#define OTGFS_DOEPTSIZ_XFRSIZ_MASK (0x7ffff << OTGFS_DOEPTSIZ_XFRSIZ_SHIFT) -#define OTGFS_DOEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */ -#define OTGFS_DOEPTSIZ_PKTCNT_MASK (0x3ff << OTGFS_DOEPTSIZ_PKTCNT_SHIFT) -#define OTGFS_DOEPTSIZ_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */ -#define OTGFS_DOEPTSIZ_STUPCNT_MASK (3 << OTGFS_DOEPTSIZ_STUPCNT_SHIFT) -#define OTGFS_DOEPTSIZ_RXDPID_SHIFT (29) /* Bits 29-30: Received data PID */ -#define OTGFS_DOEPTSIZ_RXDPID_MASK (3 << OTGFS_DOEPTSIZ_RXDPID_SHIFT) -# define OTGFS_DOEPTSIZ_RXDPID_DATA0 (0 << OTGFS_DOEPTSIZ_RXDPID_SHIFT) -# define OTGFS_DOEPTSIZ_RXDPID_DATA2 (1 << OTGFS_DOEPTSIZ_RXDPID_SHIFT) -# define OTGFS_DOEPTSIZ_RXDPID_DATA1 (2 << OTGFS_DOEPTSIZ_RXDPID_SHIFT) -# define OTGFS_DOEPTSIZ_RXDPID_MDATA (3 << OTGFS_DOEPTSIZ_RXDPID_SHIFT) - /* Bit 31: Reserved, must be kept at reset value */ -/* Power and clock gating control register */ - -#define OTGFS_PCGCCTL_STPPCLK (1 << 0) /* Bit 0: Stop PHY clock */ -#define OTGFS_PCGCCTL_GATEHCLK (1 << 1) /* Bit 1: Gate HCLK */ - /* Bits 2-3: Reserved, must be kept at reset value */ -#define OTGFS_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */ - /* Bits 5-31: Reserved, must be kept at reset value */ - -#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_OTGFS_H */ diff --git a/arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h b/arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h index 8658aec0a8..bccc9c1708 100644 --- a/arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h +++ b/arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h @@ -494,11 +494,20 @@ #define OTGFS_GINT_OEP (1 << 19) /* Bit 19: ro OUT endpoint interrupt */ #define OTGFS_GINT_IISOIXFR (1 << 20) /* Bit 20: rc_w1Incomplete isochronous IN transfer */ #define OTGFS_GINT_IISOOXFR (1 << 21) /* Bit 21: rc_w1 Incomplete isochronous OUT transfer */ -#define OTGFS_GINT_RES2223 (3 << 22) /* Bits 22-23: Reserved, must be kept at reset value */ +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +# define OTGFS_GINT_RES22 (1 << 22) /* Bits 22: Reserved, must be kept at reset value */ +# define OTGFS_GINT_RSTDET (1 << 23) /* Bits 23: asserted when a reset is detected on the USB in partial */ +#else +# define OTGFS_GINT_RES2223 (3 << 22) /* Bits 22-23: Reserved, must be kept at reset value */ +#endif #define OTGFS_GINT_HPRT (1 << 24) /* Bit 24: ro Host port interrupt */ #define OTGFS_GINT_HC (1 << 25) /* Bit 25: ro Host channels interrupt */ #define OTGFS_GINT_PTXFE (1 << 26) /* Bit 26: ro Periodic TxFIFO empty */ +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +#define OTGFS_GINT_LPMINT (1 << 27) /* Bit 27 LPM interrupt */ +#else #define OTGFS_GINT_RES27 (1 << 27) /* Bit 27 Reserved, must be kept at reset value */ +#endif #define OTGFS_GINT_CIDSCHG (1 << 28) /* Bit 28: rc_w1 Connector ID status change */ #define OTGFS_GINT_DISC (1 << 29) /* Bit 29: rc_w1 Disconnect detected interrupt */ #define OTGFS_GINT_SRQ (1 << 30) /* Bit 30: rc_w1 Session request/new session detected interrupt */ diff --git a/arch/arm/src/stm32/stm32_otgfsdev.c b/arch/arm/src/stm32/stm32_otgfsdev.c index c570e6d084..2fcbf599f0 100644 --- a/arch/arm/src/stm32/stm32_otgfsdev.c +++ b/arch/arm/src/stm32/stm32_otgfsdev.c @@ -153,25 +153,50 @@ # error "CONFIG_USBDEV_EP3_TXFIFO_SIZE is out of range" #endif -#define OTGFS_GINT_RESERVED (OTGFS_GINT_RES89 | \ - (OTGFS_GINT_RES16 | OTGFS_GINTMSK_EPMISM) \ - |OTGFS_GINT_RES2223 | \ - OTGFS_GINT_RES27) - -#define OTGFS_GINT_RC_W1 (OTGFS_GINT_MMIS | \ - OTGFS_GINT_SOF | \ - OTGFS_GINT_ESUSP | \ - OTGFS_GINT_USBSUSP | \ - OTGFS_GINT_USBRST | \ - OTGFS_GINT_ENUMDNE | \ - OTGFS_GINT_ISOODRP | \ - OTGFS_GINT_EOPF | \ - OTGFS_GINT_IISOIXFR | \ - OTGFS_GINT_IISOOXFR | \ - OTGFS_GINT_CIDSCHG | \ - OTGFS_GINT_DISC | \ - OTGFS_GINT_SRQ | \ - OTGFS_GINT_WKUP) +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +# define OTGFS_GINT_RESETS (OTGFS_GINT_USBRST | OTGFS_GINT_RSTDET) +# define OTGFS_GINT_RESERVED (OTGFS_GINT_RES89 | \ + (OTGFS_GINT_RES16 | OTGFS_GINTMSK_EPMISM) \ + |OTGFS_GINT_RES22) + +# define OTGFS_GINT_RC_W1 (OTGFS_GINT_MMIS | \ + OTGFS_GINT_SOF | \ + OTGFS_GINT_ESUSP | \ + OTGFS_GINT_USBSUSP | \ + OTGFS_GINT_USBRST | \ + OTGFS_GINT_ENUMDNE | \ + OTGFS_GINT_ISOODRP | \ + OTGFS_GINT_EOPF | \ + OTGFS_GINT_IISOIXFR | \ + OTGFS_GINT_IISOOXFR | \ + OTGFS_GINT_RSTDET | \ + OTGFS_GINT_LPMINT | \ + OTGFS_GINT_CIDSCHG | \ + OTGFS_GINT_DISC | \ + OTGFS_GINT_SRQ | \ + OTGFS_GINT_WKUP) +#else +# define OTGFS_GINT_RESETS OTGFS_GINT_USBRST +# define OTGFS_GINT_RESERVED (OTGFS_GINT_RES89 | \ + (OTGFS_GINT_RES16 | OTGFS_GINTMSK_EPMISM) \ + |OTGFS_GINT_RES2223 | \ + OTGFS_GINT_RES27) + +# define OTGFS_GINT_RC_W1 (OTGFS_GINT_MMIS | \ + OTGFS_GINT_SOF | \ + OTGFS_GINT_ESUSP | \ + OTGFS_GINT_USBSUSP | \ + OTGFS_GINT_USBRST | \ + OTGFS_GINT_ENUMDNE | \ + OTGFS_GINT_ISOODRP | \ + OTGFS_GINT_EOPF | \ + OTGFS_GINT_IISOIXFR | \ + OTGFS_GINT_IISOOXFR | \ + OTGFS_GINT_CIDSCHG | \ + OTGFS_GINT_DISC | \ + OTGFS_GINT_SRQ | \ + OTGFS_GINT_WKUP) +#endif /* Debug ***********************************************************************/ /* Trace error codes */ @@ -3517,7 +3542,7 @@ static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv) /* Clear OTG interrupt */ - stm32_putreg(retval, STM32_OTGFS_GOTGINT); + stm32_putreg(regval, STM32_OTGFS_GOTGINT); } #endif @@ -3642,7 +3667,7 @@ static int stm32_usbinterrupt(int irq, FAR void *context) /* USB reset interrupt */ - if ((regval & OTGFS_GINT_USBRST) != 0) + if ((regval & OTGFS_GINT_RESETS) != 0) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVRESET), (uint16_t)regval); @@ -5201,9 +5226,9 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) /* Deactivate the power down */ -#if defined(CONFIG_STM32_STM32F446) - /* In the case of the STM32F446 the meaning of the bit has changed to VBUS - * Detection Enable when set +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) + /* In the case of the STM32F446 or STM32F469 the meaning of the bit + * has changed to VBUS Detection Enable when set */ regval = OTGFS_GCCFG_PWRDWN; @@ -5228,11 +5253,11 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) stm32_putreg(regval, STM32_OTGFS_GCCFG); up_mdelay(20); - /* For the new OTG controller in the F446 when VBUS sensing is not used we + /* For the new OTG controller in the F446, F469 when VBUS sensing is not used we * need to force the B session valid */ -#if defined(CONFIG_STM32_STM32F446) +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) # ifndef CONFIG_USBDEV_VBUSSENSING regval = stm32_getreg(STM32_OTGFS_GOTGCTL); regval |= (OTGFS_GOTGCTL_BVALOEN | OTGFS_GOTGCTL_BVALOVAL); -- GitLab From 35dfe254300ded5865013962532f18558ec7515b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 6 Dec 2016 08:51:37 -0600 Subject: [PATCH 612/734] Remove BOARDIOC_CAN_INITIALIZE. CAN initialization is now done in the board initialization logic just like every other device driver. --- configs/Kconfig | 9 -- configs/boardctl.c | 15 --- configs/nucleo-f303re/can/defconfig | 1 - configs/nucleo-f303re/nxlines/defconfig | 1 - configs/nucleo-f303re/src/nucleo-f303re.h | 12 ++ .../nucleo-f303re/src/stm32_appinitialize.c | 10 ++ configs/nucleo-f303re/src/stm32_can.c | 50 ++++----- configs/olimex-lpc1766stk/src/lpc1766stk.h | 14 ++- configs/olimex-lpc1766stk/src/lpc17_appinit.c | 10 ++ configs/olimex-lpc1766stk/src/lpc17_can.c | 51 ++++----- .../olimex-stm32-e407/src/olimex-stm32-e407.h | 8 +- configs/olimex-stm32-e407/src/stm32_appinit.c | 11 +- configs/olimex-stm32-e407/src/stm32_can.c | 68 +++++------- .../olimex-stm32-h405/src/olimex-stm32-h405.h | 12 +- configs/olimex-stm32-h405/src/stm32_appinit.c | 8 +- configs/olimex-stm32-h405/src/stm32_boot.c | 8 -- configs/olimex-stm32-h405/src/stm32_can.c | 65 ++++------- configs/olimex-stm32-h405/usbnsh/defconfig | 1 - .../olimex-stm32-h407/src/olimex-stm32-h407.h | 8 +- configs/olimex-stm32-h407/src/stm32_appinit.c | 4 - configs/olimex-stm32-h407/src/stm32_bringup.c | 10 +- configs/olimex-stm32-h407/src/stm32_can.c | 64 ++++------- configs/olimex-stm32-p107/src/Makefile | 4 + .../olimex-stm32-p107/src/olimex-stm32-p107.h | 13 +++ configs/olimex-stm32-p107/src/stm32_appinit.c | 105 ++++++++++++++++++ configs/olimex-stm32-p107/src/stm32_boot.c | 9 -- configs/olimex-stm32-p107/src/stm32_can.c | 64 +++++------ configs/olimex-stm32-p207/nsh/defconfig | 1 - .../olimex-stm32-p207/src/olimex-stm32-p207.h | 12 +- configs/olimex-stm32-p207/src/stm32_appinit.c | 10 +- configs/olimex-stm32-p207/src/stm32_can.c | 66 ++++------- configs/olimexino-stm32/can/defconfig | 1 - configs/olimexino-stm32/smallnsh/defconfig | 1 - configs/olimexino-stm32/src/olimexino-stm32.h | 24 ++-- configs/olimexino-stm32/src/stm32_appinit.c | 11 ++ configs/olimexino-stm32/src/stm32_can.c | 67 +++++------ configs/olimexino-stm32/tiny/defconfig | 1 - configs/sama5d3-xplained/src/sam_appinit.c | 10 ++ configs/sama5d3-xplained/src/sam_can.c | 53 ++++----- .../sama5d3-xplained/src/sama5d3-xplained.h | 12 ++ configs/sama5d3x-ek/src/sam_appinit.c | 10 ++ configs/sama5d3x-ek/src/sam_can.c | 51 ++++----- configs/sama5d3x-ek/src/sama5d3x-ek.h | 25 ++++- configs/same70-xplained/README.txt | 4 - configs/same70-xplained/src/sam_bringup.c | 55 +++++---- configs/same70-xplained/src/sam_mcan.c | 51 ++++----- configs/same70-xplained/src/same70-xplained.h | 12 ++ configs/samv71-xult/README.txt | 4 - configs/samv71-xult/src/sam_bringup.c | 10 ++ configs/samv71-xult/src/sam_mcan.c | 51 ++++----- configs/samv71-xult/src/samv71-xult.h | 14 ++- configs/shenzhou/src/shenzhou.h | 14 ++- configs/shenzhou/src/stm32_appinit.c | 10 ++ configs/shenzhou/src/stm32_can.c | 62 ++++++----- configs/stm3210e-eval/src/stm3210e-eval.h | 14 ++- configs/stm3210e-eval/src/stm32_appinit.c | 10 ++ configs/stm3210e-eval/src/stm32_can.c | 49 ++++---- configs/stm3220g-eval/src/stm3220g-eval.h | 20 +++- configs/stm3220g-eval/src/stm32_appinit.c | 10 ++ configs/stm3220g-eval/src/stm32_can.c | 51 ++++----- configs/stm3240g-eval/src/stm3240g-eval.h | 20 +++- configs/stm3240g-eval/src/stm32_appinit.c | 10 ++ configs/stm3240g-eval/src/stm32_can.c | 51 ++++----- configs/stm32f4discovery/canard/defconfig | 1 - configs/stm32f4discovery/src/stm32_bringup.c | 10 ++ configs/stm32f4discovery/src/stm32_can.c | 49 ++++---- .../stm32f4discovery/src/stm32f4discovery.h | 32 +++--- .../viewtool-stm32f107/src/stm32_appinit.c | 37 +++++- configs/viewtool-stm32f107/src/stm32_can.c | 62 ++++++----- .../src/viewtool_stm32f107.h | 12 ++ configs/zkit-arm-1769/src/lpc17_appinit.c | 11 ++ configs/zkit-arm-1769/src/lpc17_can.c | 89 +++++++-------- configs/zkit-arm-1769/src/zkit-arm-1769.h | 12 ++ include/nuttx/board.h | 19 ---- include/sys/boardctl.h | 9 +- 75 files changed, 1022 insertions(+), 833 deletions(-) create mode 100644 configs/olimex-stm32-p107/src/stm32_appinit.c diff --git a/configs/Kconfig b/configs/Kconfig index ea7efa2104..cf6826157b 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -2029,15 +2029,6 @@ config BOARDCTL_TSCTEST specific logic must provide board_tsc_setup() and board_tsc_teardown() interfaces. -config BOARDCTL_CANINIT - bool "Enable CAN initialize interface" - default n - depends on CAN - ---help--- - Enables support for the BOARDIOC_CAN_INITIALIZE boardctl() command. - Architecture specific logic must provide board_can_initialize() - interface. - config BOARDCTL_GRAPHICS bool "Enable custom graphics initialization interfaces" default n diff --git a/configs/boardctl.c b/configs/boardctl.c index d073420d79..d5810699cc 100644 --- a/configs/boardctl.c +++ b/configs/boardctl.c @@ -426,21 +426,6 @@ int boardctl(unsigned int cmd, uintptr_t arg) break; #endif -#ifdef CONFIG_BOARDCTL_CANINIT - /* CMD: BOARDIOC_CAN_INITIALIZE - * DESCRIPTION: CAN device initialization - * ARG: None - * CONFIGURATION: CONFIG_LIB_BOARDCTL && CONFIG_BOARDCTL_CANINIT - * DEPENDENCIES: Board logic must provide board_can_initialize() - */ - - case BOARDIOC_CAN_INITIALIZE: - { - ret = board_can_initialize(); - } - break; -#endif - #ifdef CONFIG_BOARDCTL_GRAPHICS /* CMD: BOARDIOC_GRAPHICS_SETUP * DESCRIPTION: Configure graphics that require special initialization diff --git a/configs/nucleo-f303re/can/defconfig b/configs/nucleo-f303re/can/defconfig index baaf7ac37a..868ad9be6a 100644 --- a/configs/nucleo-f303re/can/defconfig +++ b/configs/nucleo-f303re/can/defconfig @@ -545,7 +545,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -CONFIG_BOARDCTL_CANINIT=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/nucleo-f303re/nxlines/defconfig b/configs/nucleo-f303re/nxlines/defconfig index ff310f5237..0cf525b59c 100644 --- a/configs/nucleo-f303re/nxlines/defconfig +++ b/configs/nucleo-f303re/nxlines/defconfig @@ -544,7 +544,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_CANINIT is not set CONFIG_BOARDCTL_GRAPHICS=y # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/nucleo-f303re/src/nucleo-f303re.h b/configs/nucleo-f303re/src/nucleo-f303re.h index 11d3c9c22a..e11495f5f1 100644 --- a/configs/nucleo-f303re/src/nucleo-f303re.h +++ b/configs/nucleo-f303re/src/nucleo-f303re.h @@ -191,4 +191,16 @@ int stm32_pwm_setup(void); int stm32_adc_setup(void); #endif +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +#ifdef CONFIG_CAN +int stm32_can_setup(void); +#endif + #endif /* __CONFIGS_NUCLEO_F303RE_SRC_NUCLEO_F303RE_H */ diff --git a/configs/nucleo-f303re/src/stm32_appinitialize.c b/configs/nucleo-f303re/src/stm32_appinitialize.c index 56f43b328d..621488c57f 100644 --- a/configs/nucleo-f303re/src/stm32_appinitialize.c +++ b/configs/nucleo-f303re/src/stm32_appinitialize.c @@ -141,6 +141,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_CAN + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + UNUSED(ret); return OK; } diff --git a/configs/nucleo-f303re/src/stm32_can.c b/configs/nucleo-f303re/src/stm32_can.c index ec689b3e91..e1f1a2d713 100644 --- a/configs/nucleo-f303re/src/stm32_can.c +++ b/configs/nucleo-f303re/src/stm32_can.c @@ -45,60 +45,52 @@ #include #include -#include #include #include "stm32.h" -#if defined(CONFIG_CAN) && defined(CONFIG_STM32_CAN1) +#ifdef CONFIG_CAN /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: board_can_initialize + * Name: stm32_can_setup * * Description: - * All STM32 architectures must provide the following interface to work - * with examples/can. + * Initialize CAN and register the CAN device * ****************************************************************************/ -int board_can_initialize(void) +int stm32_can_setup(void) { - static bool initialized = false; +#ifdef CONFIG_STM32_CAN1 struct can_dev_s *can; int ret; - /* Check if we have already initialized */ + /* Call stm32_caninitialize() to get an instance of the CAN interface */ - if (!initialized) + can = stm32_caninitialize(1); + if (can == NULL) { - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(1); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } - /* Now we are initialized */ + /* Register the CAN driver at "/dev/can0" */ - initialized = true; + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; } return OK; +#else + return -ENODEV; +#endif } -#endif /* CONFIG_CAN && CONFIG_STM32_CAN1 */ +#endif /* CONFIG_CAN */ diff --git a/configs/olimex-lpc1766stk/src/lpc1766stk.h b/configs/olimex-lpc1766stk/src/lpc1766stk.h index da5a6da689..e591862819 100644 --- a/configs/olimex-lpc1766stk/src/lpc1766stk.h +++ b/configs/olimex-lpc1766stk/src/lpc1766stk.h @@ -1,7 +1,7 @@ /************************************************************************************ * configs/olimex-lpc1766stk/src/lpc1766stk.h * - * Copyright (C) 2010-2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2010-2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -260,6 +260,18 @@ void weak_function lpc1766stk_sspdev_initialize(void); +/************************************************************************************ + * Name: lpc1766stk_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ************************************************************************************/ + +#ifdef CONFIG_CAN +int lpc1766stk_can_setup(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* _CONFIGS_OLIMEX_LPC1766STK_SRC_LPC1766STK_H */ diff --git a/configs/olimex-lpc1766stk/src/lpc17_appinit.c b/configs/olimex-lpc1766stk/src/lpc17_appinit.c index fbbef27b6b..e3aa02bd45 100644 --- a/configs/olimex-lpc1766stk/src/lpc17_appinit.c +++ b/configs/olimex-lpc1766stk/src/lpc17_appinit.c @@ -362,6 +362,16 @@ int board_app_initialize(uintptr_t arg) syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); } +#ifdef CONFIG_CAN + /* Initialize CAN and register the CAN driver. */ + + ret = lpc1766stk_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: lpc1766stk_can_setup failed: %d\n", ret); + } +#endif + #ifdef CONFIG_FS_PROCFS /* Mount the procfs file system */ diff --git a/configs/olimex-lpc1766stk/src/lpc17_can.c b/configs/olimex-lpc1766stk/src/lpc17_can.c index afb1ff47a0..a9e1b68c88 100644 --- a/configs/olimex-lpc1766stk/src/lpc17_can.c +++ b/configs/olimex-lpc1766stk/src/lpc17_can.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/solimex-lpc1766stk/src/lpc17_can.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -51,7 +51,7 @@ #include "lpc17_can.h" #include "lpc1766stk.h" -#if defined(CONFIG_CAN) && (defined(CONFIG_LPC17_CAN1) || defined(CONFIG_LPC17_CAN2)) +#ifdef CONFIG_CAN /************************************************************************************ * Pre-processor Definitions @@ -78,48 +78,41 @@ ************************************************************************************/ /************************************************************************************ - * Name: board_can_initialize + * Name: lpc1766stk_can_setup * * Description: - * All LPC17 architectures must provide the following interface to work with - * examples/can. + * Initialize CAN and register the CAN device * ************************************************************************************/ -int board_can_initialize(void) +int lpc1766stk_can_setup(void) { - static bool initialized = false; +#if defined(CONFIG_LPC17_CAN1) || defined(CONFIG_LPC17_CAN2) struct can_dev_s *can; int ret; - /* Check if we have already initialized */ + /* Call lpc17_caninitialize() to get an instance of the CAN interface */ - if (!initialized) + can = lpc17_caninitialize(CAN_PORT); + if (can == NULL) { - /* Call lpc17_caninitialize() to get an instance of the CAN interface */ - - can = lpc17_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } - /* Now we are initialized */ + /* Register the CAN driver at "/dev/can0" */ - initialized = true; + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; } return OK; +#else + return -ENODEV; +#endif } -#endif /* CONFIG_CAN && (CONFIG_LPC17_CAN1 || CONFIG_LPC17_CAN2) */ +#endif /* CONFIG_CAN */ diff --git a/configs/olimex-stm32-e407/src/olimex-stm32-e407.h b/configs/olimex-stm32-e407/src/olimex-stm32-e407.h index 72055c1d36..e941de636b 100644 --- a/configs/olimex-stm32-e407/src/olimex-stm32-e407.h +++ b/configs/olimex-stm32-e407/src/olimex-stm32-e407.h @@ -246,15 +246,15 @@ int stm32_sdio_initialize(void); #endif /**************************************************************************** - * Name: stm32_can_initialize + * Name: stm32_can_setup * * Description: - * Called at application startup time to initialize the CAN functionality. + * Initialize CAN and register the CAN device * ****************************************************************************/ -#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) -int stm32_can_initialize(void); +#ifdef CONFIG_CAN +int stm32_can_setup(void); #endif #endif /* __ASSEMBLY__ */ diff --git a/configs/olimex-stm32-e407/src/stm32_appinit.c b/configs/olimex-stm32-e407/src/stm32_appinit.c index 77023b153a..672d6a7561 100644 --- a/configs/olimex-stm32-e407/src/stm32_appinit.c +++ b/configs/olimex-stm32-e407/src/stm32_appinit.c @@ -180,21 +180,19 @@ static void stm32_i2ctool(void) int board_app_initialize(uintptr_t arg) { -#if defined(CONFIG_CAN) || defined(CONFIG_ADC) int ret; -#endif /* Register I2C drivers on behalf of the I2C tool */ stm32_i2ctool(); #ifdef CONFIG_CAN - /* Configure on-board CAN if CAN support has been selected. */ + /* Initialize CAN and register the CAN driver. */ - ret = stm32_can_initialize(); - if (ret != OK) + ret = stm32_can_setup(); + if (ret < 0) { - syslog(LOG_ERR, "ERROR: Failed to initialize CAN: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); } #endif @@ -231,5 +229,6 @@ int board_app_initialize(uintptr_t arg) } #endif + UNUSED(ret); return OK; } diff --git a/configs/olimex-stm32-e407/src/stm32_can.c b/configs/olimex-stm32-e407/src/stm32_can.c index 42def42a81..b5c7bce8bc 100644 --- a/configs/olimex-stm32-e407/src/stm32_can.c +++ b/configs/olimex-stm32-e407/src/stm32_can.c @@ -41,13 +41,15 @@ #include #include + #include #include + #include "stm32.h" #include "stm32_can.h" #include "olimex-stm32-e407.h" -#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) +#ifdef CONFIG_CAN /************************************************************************************ * Pre-processor Definitions @@ -69,62 +71,42 @@ * Public Functions ************************************************************************************/ -/************************************************************************************ - * Name: board_can_initialize - * - * Description: - * All STM32 architectures must provide the following interface to work with - * examples/can. - * - ************************************************************************************/ - -int board_can_initialize(void) -{ - return stm32_can_initialize(); -} - -/************************************************************************************ - * Name: stm32_can_initialize +/**************************************************************************** + * Name: stm32_can_setup * * Description: - * Called at application startup time to initialize the CAN functionality. + * Initialize CAN and register the CAN device * - ************************************************************************************/ + ****************************************************************************/ -int stm32_can_initialize(void) +int stm32_can_setup(void) { - static bool initialized = false; +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) struct can_dev_s *can; int ret; - /* Check if we have already initialized */ + /* Call stm32_caninitialize() to get an instance of the CAN interface */ - if (!initialized) + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) { - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - candbg("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - candbg("ERROR: can_register failed: %d\n", ret); - return ret; - } + candbg("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } - /* Now we are initialized */ + /* Register the CAN driver at "/dev/can0" */ - initialized = true; + ret = can_register("/dev/can0", can); + if (ret < 0) + { + candbg("ERROR: can_register failed: %d\n", ret); + return ret; } return OK; +#else + return -ENODEV; +#endif } -#endif /* CONFIG_CAN && (CONFIG_STM32_CAN1 || CONFIG_STM32_CAN2) */ +#endif /* CONFIG_CAN */ diff --git a/configs/olimex-stm32-h405/src/olimex-stm32-h405.h b/configs/olimex-stm32-h405/src/olimex-stm32-h405.h index 9ded4cfa69..d0e40d135d 100644 --- a/configs/olimex-stm32-h405/src/olimex-stm32-h405.h +++ b/configs/olimex-stm32-h405/src/olimex-stm32-h405.h @@ -100,16 +100,16 @@ void weak_function stm32_usbinitialize(void); int stm32_adc_setup(void); #endif -/************************************************************************************ - * Name: stm32_can_initialize +/**************************************************************************** + * Name: stm32_can_setup * * Description: - * Called at application startup time to initialize the CAN functionality. + * Initialize CAN and register the CAN device * - ************************************************************************************/ + ****************************************************************************/ -#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) -int stm32_can_initialize(void); +#ifdef CONFIG_CAN +int stm32_can_setup(void); #endif #endif /* __ASSEMBLY__ */ diff --git a/configs/olimex-stm32-h405/src/stm32_appinit.c b/configs/olimex-stm32-h405/src/stm32_appinit.c index 4206d7c373..d94f29d31b 100644 --- a/configs/olimex-stm32-h405/src/stm32_appinit.c +++ b/configs/olimex-stm32-h405/src/stm32_appinit.c @@ -116,12 +116,12 @@ int board_app_initialize(uintptr_t arg) #endif #ifdef CONFIG_CAN - /* Configure on-board CAN if CAN support has been selected. */ + /* Initialize CAN and register the CAN driver. */ - ret = stm32_can_initialize(); - if (ret != OK) + ret = stm32_can_setup(); + if (ret < 0) { - syslog(LOG_ERR, "ERROR: Failed to initialize CAN: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); } #endif diff --git a/configs/olimex-stm32-h405/src/stm32_boot.c b/configs/olimex-stm32-h405/src/stm32_boot.c index 7332b8a4ef..bc4792fc09 100644 --- a/configs/olimex-stm32-h405/src/stm32_boot.c +++ b/configs/olimex-stm32-h405/src/stm32_boot.c @@ -47,14 +47,6 @@ #include "olimex-stm32-h405.h" -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ diff --git a/configs/olimex-stm32-h405/src/stm32_can.c b/configs/olimex-stm32-h405/src/stm32_can.c index 62c94a0b19..6f361af940 100644 --- a/configs/olimex-stm32-h405/src/stm32_can.c +++ b/configs/olimex-stm32-h405/src/stm32_can.c @@ -41,13 +41,16 @@ #include #include + #include + #include + #include "stm32.h" #include "stm32_can.h" #include "olimex-stm32-h405.h" -#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) +#ifdef CONFIG_CAN /************************************************************************************ * Pre-processor Definitions @@ -70,61 +73,41 @@ ************************************************************************************/ /************************************************************************************ - * Name: board_can_initialize + * Name: stm32_can_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/can. + * Initialize CAN and register the CAN device * ************************************************************************************/ -int board_can_initialize(void) +int stm32_can_setup(void) { - return stm32_can_initialize(); -} - -/**************************************************************************************************** - * Name: stm32_can_initialize - * - * Description: - * Called at application startup time to initialize the CAN functionality. - * - ****************************************************************************************************/ - -int stm32_can_initialize(void) -{ - static bool initialized = false; +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) struct can_dev_s *can; int ret; - /* Check if we have already initialized */ + /* Call stm32_caninitialize() to get an instance of the CAN interface */ - if (!initialized) + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) { - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } - /* Now we are initialized */ + /* Register the CAN driver at "/dev/can0" */ - initialized = true; + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; } return OK; +#else + return -ENODEV; +#endif } -#endif /* CONFIG_CAN && (CONFIG_STM32_CAN1 || CONFIG_STM32_CAN2) */ +#endif /* CONFIG_CAN */ diff --git a/configs/olimex-stm32-h405/usbnsh/defconfig b/configs/olimex-stm32-h405/usbnsh/defconfig index 5c90c54a77..37de3e0885 100644 --- a/configs/olimex-stm32-h405/usbnsh/defconfig +++ b/configs/olimex-stm32-h405/usbnsh/defconfig @@ -600,7 +600,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y # CONFIG_BOARDCTL_TSCTEST is not set -CONFIG_BOARDCTL_CANINIT=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-stm32-h407/src/olimex-stm32-h407.h b/configs/olimex-stm32-h407/src/olimex-stm32-h407.h index 51b051c6de..c2df0a8678 100644 --- a/configs/olimex-stm32-h407/src/olimex-stm32-h407.h +++ b/configs/olimex-stm32-h407/src/olimex-stm32-h407.h @@ -267,15 +267,15 @@ int stm32_adc_setup(void); #endif /**************************************************************************** - * Name: stm32_can_initialize + * Name: stm32_can_setup * * Description: - * Called at application startup time to initialize the CAN functionality. + * Initialize CAN and register the CAN device * ****************************************************************************/ -#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) -int stm32_can_initialize(void); +#ifdef CONFIG_CAN +int stm32_can_setup(void); #endif #endif /* __ASSEMBLY__ */ diff --git a/configs/olimex-stm32-h407/src/stm32_appinit.c b/configs/olimex-stm32-h407/src/stm32_appinit.c index d87ae0670a..f461c2f193 100644 --- a/configs/olimex-stm32-h407/src/stm32_appinit.c +++ b/configs/olimex-stm32-h407/src/stm32_appinit.c @@ -59,10 +59,6 @@ #ifdef CONFIG_LIB_BOARDCTL -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/configs/olimex-stm32-h407/src/stm32_bringup.c b/configs/olimex-stm32-h407/src/stm32_bringup.c index ba931c8a18..621e6c1cca 100644 --- a/configs/olimex-stm32-h407/src/stm32_bringup.c +++ b/configs/olimex-stm32-h407/src/stm32_bringup.c @@ -97,14 +97,12 @@ int stm32_bringup(void) int ret; #ifdef CONFIG_CAN - /* Configure on-board CAN if CAN support has been selected. */ + /* Initialize CAN and register the CAN driver. */ - ret = stm32_can_initialize(); - if (ret != OK) + ret = stm32_can_setup(); + if (ret < 0) { - syslog(LOG_ERR, - "ERROR: Failed to initialize CAN: %d\n", - ret); + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); } #endif diff --git a/configs/olimex-stm32-h407/src/stm32_can.c b/configs/olimex-stm32-h407/src/stm32_can.c index ec7f2d39ab..b482342e61 100644 --- a/configs/olimex-stm32-h407/src/stm32_can.c +++ b/configs/olimex-stm32-h407/src/stm32_can.c @@ -41,13 +41,15 @@ #include #include + #include #include + #include "stm32.h" #include "stm32_can.h" #include "olimex-stm32-h407.h" -#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) +#ifdef CONFIG_CAN /************************************************************************************ * Pre-processor Definitions @@ -70,61 +72,41 @@ ************************************************************************************/ /************************************************************************************ - * Name: board_can_initialize - * - * Description: - * All STM32 architectures must provide the following interface to work with - * examples/can. - * - ************************************************************************************/ - -int board_can_initialize(void) -{ - return stm32_can_initialize(); -} - -/************************************************************************************ - * Name: stm32_can_initialize + * Name: stm32_can_setup * * Description: - * Called at application startup time to initialize the CAN functionality. + * Initialize CAN and register the CAN device * ************************************************************************************/ -int stm32_can_initialize(void) +int stm32_can_setup(void) { - static bool initialized = false; +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) struct can_dev_s *can; int ret; - /* Check if we have already initialized */ + /* Call stm32_caninitialize() to get an instance of the CAN interface */ - if (!initialized) + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) { - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } - /* Now we are initialized */ + /* Register the CAN driver at "/dev/can0" */ - initialized = true; + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; } return OK; +#else + return -ENODEV; +#endif } -#endif /* CONFIG_CAN && (CONFIG_STM32_CAN1 || CONFIG_STM32_CAN2) */ +#endif /* CONFIG_CAN */ diff --git a/configs/olimex-stm32-p107/src/Makefile b/configs/olimex-stm32-p107/src/Makefile index 9d4acd1697..a68b6db8ba 100644 --- a/configs/olimex-stm32-p107/src/Makefile +++ b/configs/olimex-stm32-p107/src/Makefile @@ -38,6 +38,10 @@ ASRCS = CSRCS = stm32_boot.c stm32_spi.c +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += stm32_appinit.c +endif + ifeq ($(CONFIG_CAN),y) CSRCS += stm32_can.c endif diff --git a/configs/olimex-stm32-p107/src/olimex-stm32-p107.h b/configs/olimex-stm32-p107/src/olimex-stm32-p107.h index 4b4b2240e9..813cc251d8 100644 --- a/configs/olimex-stm32-p107/src/olimex-stm32-p107.h +++ b/configs/olimex-stm32-p107/src/olimex-stm32-p107.h @@ -32,6 +32,7 @@ * POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************/ + #ifndef __CONFIGS_OLIMEX_STM32_P107_SRC_H #define __CONFIGS_OLIMEX_STM32_P107_SRC_H @@ -84,5 +85,17 @@ void weak_function stm32_spidev_initialize(void); +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +#ifdef CONFIG_CAN +int stm32_can_setup(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_OLIMEX_STM32_P107_SRC_H */ diff --git a/configs/olimex-stm32-p107/src/stm32_appinit.c b/configs/olimex-stm32-p107/src/stm32_appinit.c new file mode 100644 index 0000000000..af7736d2ca --- /dev/null +++ b/configs/olimex-stm32-p107/src/stm32_appinit.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * configs/olimex-stm32-p107/src/stm32_appinit.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "olimex-stm32-p107.h" + +#ifdef CONFIG_LIB_BOARDCTL + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * CONFIG_LIB_BOARDCTL=y: + * If CONFIG_NSH_ARCHINITIALIZE=y: + * Called from the NSH library (or other application) + * Otherse, assumed to be called from some other application. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ + int ret; + +#ifdef CONFIG_CAN + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} + +#endif /* CONFIG_LIB_BOARDCTL */ diff --git a/configs/olimex-stm32-p107/src/stm32_boot.c b/configs/olimex-stm32-p107/src/stm32_boot.c index c1ae4152a8..090a45f1c5 100644 --- a/configs/olimex-stm32-p107/src/stm32_boot.c +++ b/configs/olimex-stm32-p107/src/stm32_boot.c @@ -44,14 +44,6 @@ #include "up_arch.h" #include "olimex-stm32-p107.h" -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Private Functions - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ @@ -78,5 +70,4 @@ void stm32_boardinitialize(void) stm32_spidev_initialize(); } #endif - } diff --git a/configs/olimex-stm32-p107/src/stm32_can.c b/configs/olimex-stm32-p107/src/stm32_can.c index 2687c08f9c..5402f7d44a 100644 --- a/configs/olimex-stm32-p107/src/stm32_can.c +++ b/configs/olimex-stm32-p107/src/stm32_can.c @@ -51,7 +51,7 @@ #include "stm32.h" #include "stm32_can.h" -#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) +#ifdef CONFIG_CAN /************************************************************************************ * Pre-processor Definitions @@ -59,55 +59,57 @@ /* Configuration ********************************************************************/ /* The STM32F107VC supports CAN1 and CAN2 */ -#define CAN_PORT 1 +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is used." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif /************************************************************************************ * Public Functions ************************************************************************************/ -/************************************************************************************ - * Name: board_can_initialize +/**************************************************************************** + * Name: stm32_can_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/can. + * Initialize CAN and register the CAN device * - ************************************************************************************/ + ****************************************************************************/ -int board_can_initialize(void) +int stm32_can_setup(void) { - static bool initialized = false; +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) struct can_dev_s *can; int ret; - /* Check if we have already initialized */ + /* Call stm32_caninitialize() to get an instance of the CAN interface */ - if (!initialized) + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) { - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } - /* Now we are initialized */ + /* Register the CAN driver at "/dev/can0" */ - initialized = true; + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; } return OK; +#else + return -ENODEV; +#endif } -#endif /* CONFIG_CAN && CONFIG_STM32_CAN1 */ +#endif /* CONFIG_CAN */ diff --git a/configs/olimex-stm32-p207/nsh/defconfig b/configs/olimex-stm32-p207/nsh/defconfig index 702a3fa491..a4d0aa56e1 100644 --- a/configs/olimex-stm32-p207/nsh/defconfig +++ b/configs/olimex-stm32-p207/nsh/defconfig @@ -626,7 +626,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_CANINIT is not set # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimex-stm32-p207/src/olimex-stm32-p207.h b/configs/olimex-stm32-p207/src/olimex-stm32-p207.h index 885d69e7ad..04d7c558a3 100644 --- a/configs/olimex-stm32-p207/src/olimex-stm32-p207.h +++ b/configs/olimex-stm32-p207/src/olimex-stm32-p207.h @@ -136,16 +136,16 @@ int stm32_usbhost_initialize(void); int stm32_adc_setup(void); #endif -/************************************************************************************ - * Name: stm32_can_initialize +/**************************************************************************** + * Name: stm32_can_setup * * Description: - * Called at application startup time to initialize the CAN functionality. + * Initialize CAN and register the CAN device * - ************************************************************************************/ + ****************************************************************************/ -#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) -int stm32_can_initialize(void); +#ifdef CONFIG_CAN +int stm32_can_setup(void); #endif #endif /* __ASSEMBLY__ */ diff --git a/configs/olimex-stm32-p207/src/stm32_appinit.c b/configs/olimex-stm32-p207/src/stm32_appinit.c index 8941d109aa..fc22cc5aff 100644 --- a/configs/olimex-stm32-p207/src/stm32_appinit.c +++ b/configs/olimex-stm32-p207/src/stm32_appinit.c @@ -134,13 +134,13 @@ int board_app_initialize(uintptr_t arg) { int ret; -#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) - /* Configure on-board CAN if CAN support has been selected. */ +#ifdef CONFIG_CAN + /* Initialize CAN and register the CAN driver. */ - ret = stm32_can_initialize(); - if (ret != OK) + ret = stm32_can_setup(); + if (ret < 0) { - syslog(LOG_ERR, "ERROR: Failed to initialize CAN: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); } #endif diff --git a/configs/olimex-stm32-p207/src/stm32_can.c b/configs/olimex-stm32-p207/src/stm32_can.c index b05dcb2446..ab20e9fcb9 100644 --- a/configs/olimex-stm32-p207/src/stm32_can.c +++ b/configs/olimex-stm32-p207/src/stm32_can.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/olimex-stm32-p207/src/stm32_can.c * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -41,13 +41,15 @@ #include #include + #include #include + #include "stm32.h" #include "stm32_can.h" #include "olimex-stm32-p207.h" -#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) +#ifdef CONFIG_CAN /************************************************************************************ * Pre-processor Definitions @@ -70,61 +72,41 @@ ************************************************************************************/ /************************************************************************************ - * Name: board_can_initialize + * Name: stm32_can_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/can. + * Initialize CAN and register the CAN device * ************************************************************************************/ -int board_can_initialize(void) -{ - return stm32_can_initialize(); -} - -/**************************************************************************************************** - * Name: stm32_can_initialize - * - * Description: - * Called at application startup time to initialize the CAN functionality. - * - ****************************************************************************************************/ - -int stm32_can_initialize(void) +int stm32_can_setup(void) { - static bool initialized = false; +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) struct can_dev_s *can; int ret; - /* Check if we have already initialized */ + /* Call stm32_caninitialize() to get an instance of the CAN interface */ - if (!initialized) + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) { - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } - /* Now we are initialized */ + /* Register the CAN driver at "/dev/can0" */ - initialized = true; + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; } return OK; +#else + return -ENODEV; +#endif } -#endif /* CONFIG_CAN && (CONFIG_STM32_CAN1 || CONFIG_STM32_CAN2) */ +#endif /* CONFIG_CAN */ diff --git a/configs/olimexino-stm32/can/defconfig b/configs/olimexino-stm32/can/defconfig index a0c85f35fa..d83e2a9a93 100644 --- a/configs/olimexino-stm32/can/defconfig +++ b/configs/olimexino-stm32/can/defconfig @@ -588,7 +588,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -CONFIG_BOARDCTL_CANINIT=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimexino-stm32/smallnsh/defconfig b/configs/olimexino-stm32/smallnsh/defconfig index 2358425336..0eca97c944 100644 --- a/configs/olimexino-stm32/smallnsh/defconfig +++ b/configs/olimexino-stm32/smallnsh/defconfig @@ -569,7 +569,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -CONFIG_BOARDCTL_CANINIT=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/olimexino-stm32/src/olimexino-stm32.h b/configs/olimexino-stm32/src/olimexino-stm32.h index df496c9894..987c55c00f 100644 --- a/configs/olimexino-stm32/src/olimexino-stm32.h +++ b/configs/olimexino-stm32/src/olimexino-stm32.h @@ -200,18 +200,6 @@ void stm32_usb_set_pwr_callback(xcpt_t pwr_changed_handler); void stm32_led_initialize(void); #endif -/************************************************************************************ - * Name: stm32_can_initialize - * - * Description: - * Called at application startup time to initialize the CAN functionality. - * - ************************************************************************************/ - -#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) -int stm32_can_initialize(void); -#endif - /**************************************************************************** * Name: board_usbmsc_initialize * @@ -228,5 +216,17 @@ int stm32_can_initialize(void); int board_usbmsc_initialize(int port); #endif +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +#ifdef CONFIG_CAN +int stm32_can_setup(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_OLIMEXINO_STM32_SRC_OLIMEXINO_STM32_H */ diff --git a/configs/olimexino-stm32/src/stm32_appinit.c b/configs/olimexino-stm32/src/stm32_appinit.c index c0e50597f7..4fdc6a1c68 100644 --- a/configs/olimexino-stm32/src/stm32_appinit.c +++ b/configs/olimexino-stm32/src/stm32_appinit.c @@ -105,5 +105,16 @@ int board_app_initialize(uintptr_t arg) #endif #endif +#ifdef CONFIG_CAN + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); return ret; } diff --git a/configs/olimexino-stm32/src/stm32_can.c b/configs/olimexino-stm32/src/stm32_can.c index c03a1c8d26..862def8094 100644 --- a/configs/olimexino-stm32/src/stm32_can.c +++ b/configs/olimexino-stm32/src/stm32_can.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/olimexino-stm32/src/stm32_can.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * David Sidrane * @@ -48,13 +48,12 @@ #include "chip.h" #include "up_arch.h" - -#include "olimexino-stm32.h" - #include "stm32.h" #include "stm32_can.h" -#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) +#include "olimexino-stm32.h" + +#ifdef CONFIG_CAN /************************************************************************************ * Pre-processor Definitions @@ -62,55 +61,57 @@ /* Configuration ********************************************************************/ /* The STM32F107VC supports CAN1 and CAN2 */ -#define CAN_PORT 1 +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_can_initialize + * Name: stm32_can_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/can. + * Initialize CAN and register the CAN device * ************************************************************************************/ -int board_can_initialize(void) +int stm32_can_setup(void) { - static bool initialized = false; +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) struct can_dev_s *can; int ret; - /* Check if we have already initialized */ + /* Call stm32_caninitialize() to get an instance of the CAN interface */ - if (!initialized) + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) { - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } - /* Now we are initialized */ + /* Register the CAN driver at "/dev/can0" */ - initialized = true; + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; } return OK; +#else + return -ENODEV; +#endif } -#endif /* CONFIG_CAN && CONFIG_STM32_CAN1 */ +#endif /* CONFIG_CAN */ diff --git a/configs/olimexino-stm32/tiny/defconfig b/configs/olimexino-stm32/tiny/defconfig index 0f20a157a3..b56ff2028e 100644 --- a/configs/olimexino-stm32/tiny/defconfig +++ b/configs/olimexino-stm32/tiny/defconfig @@ -569,7 +569,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -CONFIG_BOARDCTL_CANINIT=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/sama5d3-xplained/src/sam_appinit.c b/configs/sama5d3-xplained/src/sam_appinit.c index 8b80cb994c..ad5d8146f8 100644 --- a/configs/sama5d3-xplained/src/sam_appinit.c +++ b/configs/sama5d3-xplained/src/sam_appinit.c @@ -192,6 +192,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_CAN + /* Initialize CAN and register the CAN driver. */ + + ret = sam_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: sam_can_setup failed: %d\n", ret); + } +#endif + #ifdef CONFIG_FS_PROCFS /* Mount the procfs file system */ diff --git a/configs/sama5d3-xplained/src/sam_can.c b/configs/sama5d3-xplained/src/sam_can.c index 76b12f3b14..cbd76837d8 100644 --- a/configs/sama5d3-xplained/src/sam_can.c +++ b/configs/sama5d3-xplained/src/sam_can.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/sama5d3-xplained/src/sam_can.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -51,7 +51,7 @@ #include "sam_can.h" #include "sama5d3-xplained.h" -#if defined(CONFIG_CAN) && (defined(CONFIG_SAMA5_CAN0) || defined(CONFIG_SAMA5_CAN1)) +#ifdef CONFIG_CAN /************************************************************************************ * Pre-processor Definitions @@ -74,48 +74,41 @@ ************************************************************************************/ /************************************************************************************ - * Name: board_can_initialize + * Name: sam_can_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/can. + * Initialize CAN and register the CAN device * ************************************************************************************/ -int board_can_initialize(void) +int sam_can_setup(void) { - static bool initialized = false; +#if defined(CONFIG_SAMA5_CAN0) || defined(CONFIG_SAMA5_CAN1) struct can_dev_s *can; int ret; - /* Check if we have already initialized */ + /* Call stm32_caninitialize() to get an instance of the CAN interface */ - if (!initialized) + can = sam_caninitialize(CAN_PORT); + if (can == NULL) { - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = sam_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } - /* Now we are initialized */ + /* Register the CAN driver at "/dev/can0" */ - initialized = true; - } + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } return OK; +#else + return -ENODEV; +#endif } -#endif /* CONFIG_CAN && (CONFIG_SAMA5_CAN0 || CONFIG_SAMA5_CAN1) */ +#endif /* CONFIG_CAN */ diff --git a/configs/sama5d3-xplained/src/sama5d3-xplained.h b/configs/sama5d3-xplained/src/sama5d3-xplained.h index f0509ce5fc..40de794377 100644 --- a/configs/sama5d3-xplained/src/sama5d3-xplained.h +++ b/configs/sama5d3-xplained/src/sama5d3-xplained.h @@ -763,6 +763,18 @@ int sam_pwm_setup(void); int sam_adc_setup(void); #endif +/************************************************************************************ + * Name: sam_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ************************************************************************************/ + +#ifdef CONFIG_CAN +int sam_can_setup(void); +#endif + /************************************************************************************ * Name: sam_netinitialize * diff --git a/configs/sama5d3x-ek/src/sam_appinit.c b/configs/sama5d3x-ek/src/sam_appinit.c index 0b56f3cea3..f352bcdf97 100644 --- a/configs/sama5d3x-ek/src/sam_appinit.c +++ b/configs/sama5d3x-ek/src/sam_appinit.c @@ -204,6 +204,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_CAN + /* Initialize CAN and register the CAN driver. */ + + ret = sam_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: sam_can_setup failed: %d\n", ret); + } +#endif + #ifdef CONFIG_FS_PROCFS /* Mount the procfs file system */ diff --git a/configs/sama5d3x-ek/src/sam_can.c b/configs/sama5d3x-ek/src/sam_can.c index f483e30dd0..4fc441f110 100644 --- a/configs/sama5d3x-ek/src/sam_can.c +++ b/configs/sama5d3x-ek/src/sam_can.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/sama5d3x-ek/src/sam_can.c * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -51,7 +51,7 @@ #include "sam_can.h" #include "sama5d3x-ek.h" -#if defined(CONFIG_CAN) && (defined(CONFIG_SAMA5_CAN0) || defined(CONFIG_SAMA5_CAN1)) +#ifdef CONFIG_CAN /************************************************************************************ * Pre-processor Definitions @@ -74,48 +74,41 @@ ************************************************************************************/ /************************************************************************************ - * Name: board_can_initialize + * Name: sam_can_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/can. + * Initialize CAN and register the CAN device * ************************************************************************************/ -int board_can_initialize(void) +int sam_can_setup(void) { - static bool initialized = false; +#if defined(CONFIG_SAMA5_CAN0) || defined(CONFIG_SAMA5_CAN1) struct can_dev_s *can; int ret; - /* Check if we have already initialized */ + /* Call stm32_caninitialize() to get an instance of the CAN interface */ - if (!initialized) + can = sam_caninitialize(CAN_PORT); + if (can == NULL) { - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = sam_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } - /* Now we are initialized */ + /* Register the CAN driver at "/dev/can0" */ - initialized = true; + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; } return OK; +#else + return -ENODEV; +#endif } -#endif /* CONFIG_CAN && (CONFIG_SAMA5_CAN0 || CONFIG_SAMA5_CAN1) */ +#endif /* CONFIG_CAN */ diff --git a/configs/sama5d3x-ek/src/sama5d3x-ek.h b/configs/sama5d3x-ek/src/sama5d3x-ek.h index fd80daf7e8..51647349a2 100644 --- a/configs/sama5d3x-ek/src/sama5d3x-ek.h +++ b/configs/sama5d3x-ek/src/sama5d3x-ek.h @@ -807,14 +807,15 @@ bool sam_writeprotected(int slotno); void weak_function sam_usbinitialize(void); #endif -/**************************************************************************************************** +/************************************************************************************ * Name: stm32_usbhost_initialize * * Description: - * Called at application startup time to initialize the USB host functionality. This function will - * start a thread that will monitor for device connection/disconnection events. + * Called at application startup time to initialize the USB host functionality. + * This function will start a thread that will monitor for device connection/ + * disconnection events. * - ****************************************************************************************************/ + ************************************************************************************/ #ifdef HAVE_USBHOST int sam_usbhost_initialize(void); @@ -856,7 +857,19 @@ int sam_pwm_setup(void); int sam_adc_setup(void); #endif -/**************************************************************************** +/************************************************************************************ + * Name: sam_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ************************************************************************************/ + +#ifdef CONFIG_CAN +int sam_can_setup(void); +#endif + +/************************************************************************************ * Name: sam_wm8904_initialize * * Description: @@ -871,7 +884,7 @@ int sam_adc_setup(void); * Zero is returned on success. Otherwise, a negated errno value is * returned to indicate the nature of the failure. * - ****************************************************************************/ + ************************************************************************************/ #ifdef HAVE_WM8904 int sam_wm8904_initialize(int minor); diff --git a/configs/same70-xplained/README.txt b/configs/same70-xplained/README.txt index ddd198f68e..c95eef6e1b 100644 --- a/configs/same70-xplained/README.txt +++ b/configs/same70-xplained/README.txt @@ -732,10 +732,6 @@ MCAN1 Loopback Test CONFIG_SAMV7_MCAN1_TXFIFOQ_SIZE=8 # There are 8 queue elements CONFIG_SAMV7_MCAN1_TXEVENTFIFO_SIZE=0 # The event FIFO is not used - Board Selection - CONFIG_LIB_BOARDCTL=y # Needed for CAN initialization - CONFIG_BOARDCTL_CANINIT=y # Enabled CAN initialization - Enabling the CAN Loopback Test ------------------------------ Application Configuration -> Examples -> CAN Example diff --git a/configs/same70-xplained/src/sam_bringup.c b/configs/same70-xplained/src/sam_bringup.c index 9a84f3228e..4b41c93674 100644 --- a/configs/same70-xplained/src/sam_bringup.c +++ b/configs/same70-xplained/src/sam_bringup.c @@ -43,6 +43,7 @@ #include #include +#include #include #include @@ -97,14 +98,14 @@ static void sam_i2c_register(int bus) i2c = sam_i2cbus_initialize(bus); if (i2c == NULL) { - _err("ERROR: Failed to get I2C%d interface\n", bus); + syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); } else { ret = i2c_register(i2c, bus); if (ret < 0) { - _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", bus, ret); sam_i2cbus_uninitialize(i2c); } } @@ -169,7 +170,7 @@ int sam_bringup(void) ret = sam_emac0_setmac(); if (ret < 0) { - _err("ERROR: sam_emac0_setmac() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: sam_emac0_setmac() failed: %d\n", ret); } #endif @@ -179,8 +180,8 @@ int sam_bringup(void) ret = mount(NULL, SAME70_PROCFS_MOUNTPOINT, "procfs", 0, NULL); if (ret < 0) { - _err("ERROR: Failed to mount procfs at %s: %d\n", - SAME70_PROCFS_MOUNTPOINT, ret); + syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", + SAME70_PROCFS_MOUNTPOINT, ret); } #endif @@ -192,7 +193,7 @@ int sam_bringup(void) ret = sam_at24config(); if (ret < 0) { - _err("ERROR: sam_at24config() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: sam_at24config() failed: %d\n", ret); } #endif @@ -202,8 +203,8 @@ int sam_bringup(void) ret = sam_hsmci_initialize(HSMCI0_SLOTNO, HSMCI0_MINOR); if (ret < 0) { - _err("ERROR: sam_hsmci_initialize(%d,%d) failed: %d\n", - HSMCI0_SLOTNO, HSMCI0_MINOR, ret); + syslog(LOG_ERR, "ERROR: sam_hsmci_initialize(%d,%d) failed: %d\n", + HSMCI0_SLOTNO, HSMCI0_MINOR, ret); } #ifdef CONFIG_SAME70XPLAINED_HSMCI0_MOUNT @@ -219,8 +220,8 @@ int sam_bringup(void) if (ret < 0) { - _err("ERROR: Failed to mount %s: %d\n", - CONFIG_SAME70XPLAINED_HSMCI0_MOUNT_MOUNTPOINT, errno); + syslog(LOG_ERR, "ERROR: Failed to mount %s: %d\n", + CONFIG_SAME70XPLAINED_HSMCI0_MOUNT_MOUNTPOINT, errno); } } @@ -241,7 +242,7 @@ int sam_bringup(void) CONFIG_SAME70XPLAINED_ROMFS_ROMDISK_SECTSIZE); if (ret < 0) { - _err("ERROR: romdisk_register failed: %d\n", -ret); + syslog(LOG_ERR, "ERROR: romdisk_register failed: %d\n", -ret); } else { @@ -252,9 +253,9 @@ int sam_bringup(void) "romfs", MS_RDONLY, NULL); if (ret < 0) { - _err("ERROR: mount(%s,%s,romfs) failed: %d\n", - CONFIG_SAME70XPLAINED_ROMFS_ROMDISK_DEVNAME, - CONFIG_SAME70XPLAINED_ROMFS_MOUNT_MOUNTPOINT, errno); + syslog(LOG_ERR, "ERROR: mount(%s,%s,romfs) failed: %d\n", + CONFIG_SAME70XPLAINED_ROMFS_ROMDISK_DEVNAME, + CONFIG_SAME70XPLAINED_ROMFS_MOUNT_MOUNTPOINT, errno); } } #endif @@ -269,7 +270,7 @@ int sam_bringup(void) mtd = progmem_initialize(); if (!mtd) { - _err("ERROR: progmem_initialize failed\n"); + syslog(LOG_ERR, "ERROR: progmem_initialize failed\n"); } /* Use the FTL layer to wrap the MTD driver as a block driver */ @@ -277,7 +278,7 @@ int sam_bringup(void) ret = ftl_initialize(PROGMEM_MTD_MINOR, mtd); if (ret < 0) { - _err("ERROR: Failed to initialize the FTL layer: %d\n", ret); + syslog(LOG_ERR, "ERROR: Failed to initialize the FTL layer: %d\n", ret); return ret; } @@ -291,7 +292,7 @@ int sam_bringup(void) ret = bchdev_register(blockdev, chardev, false); if (ret < 0) { - _err("ERROR: bchdev_register %s failed: %d\n", chardev, ret); + syslog(LOG_ERR, "ERROR: bchdev_register %s failed: %d\n", chardev, ret); return ret; } #endif @@ -304,7 +305,7 @@ int sam_bringup(void) ret = sam_usbhost_initialize(); if (ret != OK) { - _err("ERROR: Failed to initialize USB host: %d\n", ret); + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); } #endif @@ -314,18 +315,28 @@ int sam_bringup(void) ret = usbmonitor_start(); if (ret != OK) { - _err("ERROR: Failed to start the USB monitor: %d\n", ret); + syslog(LOG_ERR, "ERROR: Failed to start the USB monitor: %d\n", ret); + } +#endif + +#ifdef CONFIG_SAMV7_MCAN + /* Initialize CAN and register the CAN driver. */ + + ret = sam_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: sam_can_setup failed: %d\n", ret); } #endif #ifdef HAVE_ELF /* Initialize the ELF binary loader */ - _err("Initializing the ELF binary loader\n"); + syslog(LOG_ERR, "Initializing the ELF binary loader\n"); ret = elf_initialize(); if (ret < 0) { - _err("ERROR: Initialization of the ELF loader failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: Initialization of the ELF loader failed: %d\n", ret); } #endif @@ -333,7 +344,7 @@ int sam_bringup(void) ret = sam_dacdev_initialize(); if (ret < 0) { - _err("ERROR: Initialization of the DAC module failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: Initialization of the DAC module failed: %d\n", ret); } #endif diff --git a/configs/same70-xplained/src/sam_mcan.c b/configs/same70-xplained/src/sam_mcan.c index 2c5301c3a1..5a96930a63 100644 --- a/configs/same70-xplained/src/sam_mcan.c +++ b/configs/same70-xplained/src/sam_mcan.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/same70-xplainedk/src/sam_mcan.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -49,7 +49,7 @@ #include "sam_mcan.h" #include "same70-xplained.h" -#if defined(CONFIG_CAN) && (defined(CONFIG_SAMV7_MCAN0) || defined(CONFIG_SAMV7_MCAN1)) +#ifdef CONFIG_SAMV7_MCAN /************************************************************************************ * Pre-processor Definitions @@ -72,48 +72,41 @@ ************************************************************************************/ /************************************************************************************ - * Name: board_can_initialize + * Name: sam_can_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/can. + * Initialize CAN and register the CAN device * ************************************************************************************/ -int board_can_initialize(void) +int sam_can_setup(void) { - static bool initialized = false; +#if defined(CONFIG_SAMV7_MCAN0) || defined(CONFIG_SAMV7_MCAN1) struct can_dev_s *can; int ret; - /* Check if we have already initialized */ + /* Call stm32_caninitialize() to get an instance of the CAN interface */ - if (!initialized) + can = sam_mcan_initialize(CAN_PORT); + if (can == NULL) { - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = sam_mcan_initialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } - /* Now we are initialized */ + /* Register the CAN driver at "/dev/can0" */ - initialized = true; + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; } return OK; +#else + return -ENODEV; +#endif } -#endif /* CONFIG_CAN && (CONFIG_SAMV7_MCAN0 || CONFIG_SAMV7_MCAN1) */ +#endif /* CONFIG_SAMV7_MCAN */ diff --git a/configs/same70-xplained/src/same70-xplained.h b/configs/same70-xplained/src/same70-xplained.h index 117c6a6893..ed0e98e156 100644 --- a/configs/same70-xplained/src/same70-xplained.h +++ b/configs/same70-xplained/src/same70-xplained.h @@ -400,6 +400,18 @@ int sam_hsmci_initialize(int slot, int minor); void sam_usbinitialize(void); #endif +/**************************************************************************** + * Name: sam_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_MCAN +int sam_can_setup(void); +#endif + /************************************************************************************ * Name: sam_netinitialize * diff --git a/configs/samv71-xult/README.txt b/configs/samv71-xult/README.txt index e370dabc72..2452746a0e 100644 --- a/configs/samv71-xult/README.txt +++ b/configs/samv71-xult/README.txt @@ -1322,10 +1322,6 @@ MCAN1 Loopback Test CONFIG_SAMV7_MCAN1_TXFIFOQ_SIZE=8 # There are 8 queue elements CONFIG_SAMV7_MCAN1_TXEVENTFIFO_SIZE=0 # The event FIFO is not used - Board Selection - CONFIG_LIB_BOARDCTL=y # Needed for CAN initialization - CONFIG_BOARDCTL_CANINIT=y # Enabled CAN initialization - Enabling the CAN Loopback Test ------------------------------ Application Configuration -> Examples -> CAN Example diff --git a/configs/samv71-xult/src/sam_bringup.c b/configs/samv71-xult/src/sam_bringup.c index 3999c0ab24..cc2487719e 100644 --- a/configs/samv71-xult/src/sam_bringup.c +++ b/configs/samv71-xult/src/sam_bringup.c @@ -253,6 +253,16 @@ int sam_bringup(void) } #endif +#ifdef CONFIG_SAMV7_MCAN + /* Initialize CAN and register the CAN driver. */ + + ret = sam_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: sam_can_setup failed: %d\n", ret); + } +#endif + #ifdef HAVE_MACADDR /* Read the Ethernet MAC address from the AT24 FLASH and configure the * Ethernet driver with that address. diff --git a/configs/samv71-xult/src/sam_mcan.c b/configs/samv71-xult/src/sam_mcan.c index bb28cbb9b0..f17d9ccb20 100644 --- a/configs/samv71-xult/src/sam_mcan.c +++ b/configs/samv71-xult/src/sam_mcan.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/samv71-xultk/src/sam_mcan.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -49,7 +49,7 @@ #include "sam_mcan.h" #include "samv71-xult.h" -#if defined(CONFIG_CAN) && (defined(CONFIG_SAMV7_MCAN0) || defined(CONFIG_SAMV7_MCAN1)) +#ifdef CONFIG_SAMV7_MCAN /************************************************************************************ * Pre-processor Definitions @@ -72,48 +72,41 @@ ************************************************************************************/ /************************************************************************************ - * Name: board_can_initialize + * Name: sam_can_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/can. + * Initialize CAN and register the CAN device * ************************************************************************************/ -int board_can_initialize(void) +int sam_can_setup(void) { - static bool initialized = false; +#if defined(CONFIG_SAMV7_MCAN0) || defined(CONFIG_SAMV7_MCAN1) struct can_dev_s *can; int ret; - /* Check if we have already initialized */ + /* Call stm32_caninitialize() to get an instance of the CAN interface */ - if (!initialized) + can = sam_mcan_initialize(CAN_PORT); + if (can == NULL) { - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = sam_mcan_initialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } - /* Now we are initialized */ + /* Register the CAN driver at "/dev/can0" */ - initialized = true; + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; } return OK; +#else + return -ENODEV; +#endif } -#endif /* CONFIG_CAN && (CONFIG_SAMV7_MCAN0 || CONFIG_SAMV7_MCAN1) */ +#endif /* CONFIG_SAMV7_MCAN */ diff --git a/configs/samv71-xult/src/samv71-xult.h b/configs/samv71-xult/src/samv71-xult.h index 21884b7191..f635ff361c 100644 --- a/configs/samv71-xult/src/samv71-xult.h +++ b/configs/samv71-xult/src/samv71-xult.h @@ -1,7 +1,7 @@ /************************************************************************************ * configs/samv71-xult/src/samv71-xult.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -597,6 +597,18 @@ int sam_bringup(void); void sam_spidev_initialize(void); #endif +/************************************************************************************ + * Name: sam_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ************************************************************************************/ + +#ifdef CONFIG_SAMV7_MCAN +int sam_can_setup(void); +#endif + /************************************************************************************ * Name: sam_hsmci_initialize * diff --git a/configs/shenzhou/src/shenzhou.h b/configs/shenzhou/src/shenzhou.h index 220a91ff4a..68fb63d102 100644 --- a/configs/shenzhou/src/shenzhou.h +++ b/configs/shenzhou/src/shenzhou.h @@ -1,7 +1,7 @@ /**************************************************************************************************** * configs/shenzhou/src/shenzhou.h * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -460,6 +460,18 @@ int stm32_usbhost_initialize(void); int stm32_adc_setup(void); #endif +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +#ifdef CONFIG_CAN +int stm32_can_setup(void); +#endif + /**************************************************************************** * Name: stm32_sdinitialize * diff --git a/configs/shenzhou/src/stm32_appinit.c b/configs/shenzhou/src/stm32_appinit.c index 0ef1e05bcd..2bfb40a59f 100644 --- a/configs/shenzhou/src/stm32_appinit.c +++ b/configs/shenzhou/src/stm32_appinit.c @@ -214,6 +214,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_CAN + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + UNUSED(ret); return OK; } diff --git a/configs/shenzhou/src/stm32_can.c b/configs/shenzhou/src/stm32_can.c index bc6472bef7..6a08cc1fc0 100644 --- a/configs/shenzhou/src/stm32_can.c +++ b/configs/shenzhou/src/stm32_can.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/shenzhou/src/stm32_can.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -52,7 +52,7 @@ #include "stm32_can.h" #include "shenzhou.h" -#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) +#ifdef CONFIG_CAN /************************************************************************************ * Pre-processor Definitions @@ -60,55 +60,57 @@ /* Configuration ********************************************************************/ /* The STM32F107VC supports CAN1 and CAN2 */ -#define CAN_PORT 1 +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_can_initialize + * Name: stm32_can_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/can. + * Initialize CAN and register the CAN device * ************************************************************************************/ -int board_can_initialize(void) +int stm32_can_setup(void) { - static bool initialized = false; +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) struct can_dev_s *can; int ret; - /* Check if we have already initialized */ + /* Call stm32_caninitialize() to get an instance of the CAN interface */ - if (!initialized) + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) { - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } - /* Now we are initialized */ + /* Register the CAN driver at "/dev/can0" */ - initialized = true; + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; } return OK; +#else + return -ENODEV; +#endif } -#endif /* CONFIG_CAN && CONFIG_STM32_CAN1 */ +#endif /* CONFIG_CAN */ diff --git a/configs/stm3210e-eval/src/stm3210e-eval.h b/configs/stm3210e-eval/src/stm3210e-eval.h index 368e12c0d0..1426785854 100644 --- a/configs/stm3210e-eval/src/stm3210e-eval.h +++ b/configs/stm3210e-eval/src/stm3210e-eval.h @@ -1,7 +1,7 @@ /************************************************************************************ * configs/stm3210e_eval/src/stm3210e-eval.h * - * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -204,6 +204,18 @@ void weak_function stm32_usbinitialize(void); int stm32_adc_setup(void); #endif +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +#ifdef CONFIG_CAN +int stm32_can_setup(void); +#endif + /************************************************************************************ * Name: stm32_extcontextsave * diff --git a/configs/stm3210e-eval/src/stm32_appinit.c b/configs/stm3210e-eval/src/stm32_appinit.c index 338b108aaf..0b4a1c52c2 100644 --- a/configs/stm3210e-eval/src/stm32_appinit.c +++ b/configs/stm3210e-eval/src/stm32_appinit.c @@ -294,6 +294,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_CAN + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + #ifdef CONFIG_DJOYSTICK /* Initialize and register the joystick driver */ diff --git a/configs/stm3210e-eval/src/stm32_can.c b/configs/stm3210e-eval/src/stm32_can.c index 284e6098c0..06e24930ea 100644 --- a/configs/stm3210e-eval/src/stm32_can.c +++ b/configs/stm3210e-eval/src/stm32_can.c @@ -52,7 +52,7 @@ #include "stm32_can.h" #include "stm3210e-eval.h" -#if defined(CONFIG_CAN) && defined(CONFIG_STM32_CAN1) +#ifdef CONFIG_CAN /************************************************************************************ * Pre-processor Definitions @@ -67,48 +67,41 @@ ************************************************************************************/ /************************************************************************************ - * Name: board_can_initialize + * Name: stm32_can_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/can. + * Initialize CAN and register the CAN device * ************************************************************************************/ -int board_can_initialize(void) +int stm32_can_setup(void) { - static bool initialized = false; +#ifdef CONFIG_STM32_CAN1 struct can_dev_s *can; int ret; - /* Check if we have already initialized */ + /* Call stm32_caninitialize() to get an instance of the CAN interface */ - if (!initialized) + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) { - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } - /* Now we are initialized */ + /* Register the CAN driver at "/dev/can0" */ - initialized = true; + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; } return OK; +#else + return -ENODEV; +#endif } -#endif /* CONFIG_CAN && CONFIG_STM32_CAN1 */ +#endif /* CONFIG_CAN */ diff --git a/configs/stm3220g-eval/src/stm3220g-eval.h b/configs/stm3220g-eval/src/stm3220g-eval.h index 4cea9d2d4d..1e3087109f 100644 --- a/configs/stm3220g-eval/src/stm3220g-eval.h +++ b/configs/stm3220g-eval/src/stm3220g-eval.h @@ -249,30 +249,42 @@ void weak_function stm32_usbinitialize(void); int stm32_usbhost_initialize(void); #endif -/************************************************************************************ +/**************************************************************************************************** * Name: stm32_pwm_setup * * Description: * Initialize PWM and register the PWM device. * - ************************************************************************************/ + ****************************************************************************************************/ #ifdef CONFIG_PWM int stm32_pwm_setup(void); #endif -/************************************************************************************ +/**************************************************************************************************** * Name: stm32_adc_setup * * Description: * Initialize ADC and register the ADC driver. * - ************************************************************************************/ + ****************************************************************************************************/ #ifdef CONFIG_ADC int stm32_adc_setup(void); #endif +/**************************************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************************************/ + +#ifdef CONFIG_CAN +int stm32_can_setup(void); +#endif + /**************************************************************************************************** * Name: stm32_extmemgpios * diff --git a/configs/stm3220g-eval/src/stm32_appinit.c b/configs/stm3220g-eval/src/stm32_appinit.c index 8644f579d4..0fd45e4a6e 100644 --- a/configs/stm3220g-eval/src/stm32_appinit.c +++ b/configs/stm3220g-eval/src/stm32_appinit.c @@ -312,6 +312,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_CAN + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + UNUSED(ret); return OK; } diff --git a/configs/stm3220g-eval/src/stm32_can.c b/configs/stm3220g-eval/src/stm32_can.c index 5115a7b7d9..e362ad95c5 100644 --- a/configs/stm3220g-eval/src/stm32_can.c +++ b/configs/stm3220g-eval/src/stm32_can.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/stm3220g-eval/src/stm32_can.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -52,7 +52,7 @@ #include "stm32_can.h" #include "stm3220g-eval.h" -#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) +#ifdef CONFIG_CAN /************************************************************************************ * Pre-processor Definitions @@ -75,48 +75,41 @@ ************************************************************************************/ /************************************************************************************ - * Name: board_can_initialize + * Name: stm32_can_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/can. + * Initialize CAN and register the CAN device * ************************************************************************************/ -int board_can_initialize(void) +int stm32_can_setup(void) { - static bool initialized = false; +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) struct can_dev_s *can; int ret; - /* Check if we have already initialized */ + /* Call stm32_caninitialize() to get an instance of the CAN interface */ - if (!initialized) + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) { - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } - /* Now we are initialized */ + /* Register the CAN driver at "/dev/can0" */ - initialized = true; + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; } return OK; +#else + return -ENODEV; +#endif } -#endif /* CONFIG_CAN && (CONFIG_STM32_CAN1 || CONFIG_STM32_CAN2) */ +#endif /* CONFIG_CAN */ diff --git a/configs/stm3240g-eval/src/stm3240g-eval.h b/configs/stm3240g-eval/src/stm3240g-eval.h index 5da50bcfc9..f645db52f2 100644 --- a/configs/stm3240g-eval/src/stm3240g-eval.h +++ b/configs/stm3240g-eval/src/stm3240g-eval.h @@ -262,30 +262,42 @@ int stm32_usbhost_initialize(void); void stm32_led_initialize(void); #endif -/************************************************************************************ +/**************************************************************************************************** * Name: stm32_pwm_setup * * Description: * Initialize PWM and register the PWM device. * - ************************************************************************************/ + ****************************************************************************************************/ #ifdef CONFIG_PWM int stm32_pwm_setup(void); #endif -/************************************************************************************ +/**************************************************************************************************** * Name: stm32_adc_setup * * Description: * Initialize ADC and register the ADC driver. * - ************************************************************************************/ + ****************************************************************************************************/ #ifdef CONFIG_ADC int stm32_adc_setup(void); #endif +/**************************************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************************************/ + +#ifdef CONFIG_CAN +int stm32_can_setup(void); +#endif + /**************************************************************************************************** * Name: stm32_extmemgpios * diff --git a/configs/stm3240g-eval/src/stm32_appinit.c b/configs/stm3240g-eval/src/stm32_appinit.c index c926262e0a..e2e18f961c 100644 --- a/configs/stm3240g-eval/src/stm32_appinit.c +++ b/configs/stm3240g-eval/src/stm32_appinit.c @@ -363,6 +363,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_CAN + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + UNUSED(ret); return OK; } diff --git a/configs/stm3240g-eval/src/stm32_can.c b/configs/stm3240g-eval/src/stm32_can.c index 75e138fd20..3ebae0dfa3 100644 --- a/configs/stm3240g-eval/src/stm32_can.c +++ b/configs/stm3240g-eval/src/stm32_can.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/stm3240g-eval/src/stm32_can.c * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -52,7 +52,7 @@ #include "stm32_can.h" #include "stm3240g-eval.h" -#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) +#ifdef CONFIG_CAN /************************************************************************************ * Pre-processor Definitions @@ -75,48 +75,41 @@ ************************************************************************************/ /************************************************************************************ - * Name: board_can_initialize + * Name: stm32_can_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/can. + * Initialize CAN and register the CAN device * ************************************************************************************/ -int board_can_initialize(void) +int stm32_can_setup(void) { - static bool initialized = false; +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) struct can_dev_s *can; int ret; - /* Check if we have already initialized */ + /* Call stm32_caninitialize() to get an instance of the CAN interface */ - if (!initialized) + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) { - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } - /* Now we are initialized */ + /* Register the CAN driver at "/dev/can0" */ - initialized = true; + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; } return OK; +#else + return -ENODEV; +#endif } -#endif /* CONFIG_CAN && (CONFIG_STM32_CAN1 || CONFIG_STM32_CAN2) */ +#endif /* CONFIG_CAN */ diff --git a/configs/stm32f4discovery/canard/defconfig b/configs/stm32f4discovery/canard/defconfig index c1d19f3ed8..092eb83b75 100644 --- a/configs/stm32f4discovery/canard/defconfig +++ b/configs/stm32f4discovery/canard/defconfig @@ -589,7 +589,6 @@ CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_RESET is not set # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set -CONFIG_BOARDCTL_CANINIT=y # CONFIG_BOARDCTL_GRAPHICS is not set # CONFIG_BOARDCTL_IOCTL is not set diff --git a/configs/stm32f4discovery/src/stm32_bringup.c b/configs/stm32f4discovery/src/stm32_bringup.c index 496b17c2cc..e360c8cc0c 100644 --- a/configs/stm32f4discovery/src/stm32_bringup.c +++ b/configs/stm32f4discovery/src/stm32_bringup.c @@ -169,6 +169,16 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_CAN + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + #ifdef CONFIG_QENCODER /* Initialize and register the qencoder driver */ diff --git a/configs/stm32f4discovery/src/stm32_can.c b/configs/stm32f4discovery/src/stm32_can.c index beafd449d9..702dff902f 100644 --- a/configs/stm32f4discovery/src/stm32_can.c +++ b/configs/stm32f4discovery/src/stm32_can.c @@ -52,7 +52,7 @@ #include "stm32_can.h" #include "stm32f4discovery.h" -#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) +#ifdef CONFIG_CAN /************************************************************************************ * Pre-processor Definitions @@ -76,48 +76,41 @@ ************************************************************************************/ /************************************************************************************ - * Name: board_can_initialize + * Name: stm32_can_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/can. + * Initialize CAN and register the CAN device * ************************************************************************************/ -int board_can_initialize(void) +int stm32_can_setup(void) { - static bool initialized = false; +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) struct can_dev_s *can; int ret; - /* Check if we have already initialized */ + /* Call stm32_caninitialize() to get an instance of the CAN interface */ - if (!initialized) + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) { - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } - /* Now we are initialized */ + /* Register the CAN driver at "/dev/can0" */ - initialized = true; + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; } return OK; +#else + return -ENODEV; +#endif } -#endif /* CONFIG_CAN && (CONFIG_STM32_CAN1 || CONFIG_STM32_CAN2) */ +#endif /* CONFIG_CAN */ diff --git a/configs/stm32f4discovery/src/stm32f4discovery.h b/configs/stm32f4discovery/src/stm32f4discovery.h index b6754197ee..75892830ad 100644 --- a/configs/stm32f4discovery/src/stm32f4discovery.h +++ b/configs/stm32f4discovery/src/stm32f4discovery.h @@ -438,18 +438,30 @@ void weak_function stm32_usbinitialize(void); int stm32_usbhost_initialize(void); #endif -/************************************************************************************ +/**************************************************************************** * Name: stm32_pwm_setup * * Description: * Initialize PWM and register the PWM device. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_PWM int stm32_pwm_setup(void); #endif +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +#ifdef CONFIG_CAN +int stm32_can_setup(void); +#endif + /**************************************************************************** * Name: stm32_extmemgpios * @@ -536,22 +548,6 @@ void stm32_led_pminitialize(void); void stm32_pm_buttons(void); #endif -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_INITIALIZE=y : - * Called from board_initialize(). - * - * CONFIG_BOARD_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : - * Called from the NSH library - * - ****************************************************************************/ - -int stm32_bringup(void); - /**************************************************************************** * Name: stm32_sdio_initialize * diff --git a/configs/viewtool-stm32f107/src/stm32_appinit.c b/configs/viewtool-stm32f107/src/stm32_appinit.c index e43fcef6bf..82e4ff85af 100644 --- a/configs/viewtool-stm32f107/src/stm32_appinit.c +++ b/configs/viewtool-stm32f107/src/stm32_appinit.c @@ -146,17 +146,42 @@ static int rtc_driver_initialize(void) int board_app_initialize(uintptr_t arg) { + int ret; + #ifdef HAVE_RTC_DRIVER - (void)rtc_driver_initialize(); + ret = rtc_driver_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: rtc_driver_initialize failed: %d\n", ret); + } +#endif + +#ifdef HAVE_MMCSD + ret = stm32_sdinitialize(CONFIG_NSH_MMCSDSLOTNO); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_sdinitialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_CAN + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } #endif #ifdef CONFIG_MPL115A - stm32_mpl115ainitialize("/dev/press"); + ret = stm32_mpl115ainitialize("/dev/press"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mpl115ainitialize failed: %d\n", ret); + } #endif -#ifdef HAVE_MMCSD - return stm32_sdinitialize(CONFIG_NSH_MMCSDSLOTNO); -#else + UNUSED(ret); return OK; -#endif } diff --git a/configs/viewtool-stm32f107/src/stm32_can.c b/configs/viewtool-stm32f107/src/stm32_can.c index ce2b5912f5..462e5a72ba 100644 --- a/configs/viewtool-stm32f107/src/stm32_can.c +++ b/configs/viewtool-stm32f107/src/stm32_can.c @@ -1,7 +1,7 @@ /************************************************************************************ * configs/viewtool-stm32f107/src/stm32_can.c * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -51,7 +51,7 @@ #include "stm32.h" #include "stm32_can.h" -#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) +#ifdef CONFIG_CAN /************************************************************************************ * Pre-processor Definitions @@ -59,55 +59,57 @@ /* Configuration ********************************************************************/ /* The STM32F107VC supports CAN1 and CAN2 */ -#define CAN_PORT 1 +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif /************************************************************************************ * Public Functions ************************************************************************************/ /************************************************************************************ - * Name: board_can_initialize + * Name: stm32_can_setup * * Description: - * All STM32 architectures must provide the following interface to work with - * examples/can. + * Initialize CAN and register the CAN device * ************************************************************************************/ -int board_can_initialize(void) +int stm32_can_setup(void) { - static bool initialized = false; +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) struct can_dev_s *can; int ret; - /* Check if we have already initialized */ + /* Call stm32_caninitialize() to get an instance of the CAN interface */ - if (!initialized) + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) { - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } - /* Now we are initialized */ + /* Register the CAN driver at "/dev/can0" */ - initialized = true; + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; } return OK; +#else + return -ENODEV; +#endif } -#endif /* CONFIG_CAN && CONFIG_STM32_CAN1 */ +#endif /* CONFIG_CAN */ diff --git a/configs/viewtool-stm32f107/src/viewtool_stm32f107.h b/configs/viewtool-stm32f107/src/viewtool_stm32f107.h index bf4c2692ad..508f10c8a2 100644 --- a/configs/viewtool-stm32f107/src/viewtool_stm32f107.h +++ b/configs/viewtool-stm32f107/src/viewtool_stm32f107.h @@ -342,6 +342,18 @@ void weak_function stm32_usbdev_initialize(void); int stm32_sdinitialize(int minor); +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +#ifdef CONFIG_CAN +int stm32_can_setup(void); +#endif + /**************************************************************************** * Name: stm32_mpl115ainitialize * diff --git a/configs/zkit-arm-1769/src/lpc17_appinit.c b/configs/zkit-arm-1769/src/lpc17_appinit.c index 673c3b6ca0..b98cb2bab9 100644 --- a/configs/zkit-arm-1769/src/lpc17_appinit.c +++ b/configs/zkit-arm-1769/src/lpc17_appinit.c @@ -53,6 +53,7 @@ #include #include "lpc17_spi.h" +#include "zkit-arm-1769.h" /**************************************************************************** * Pre-processor Definitions @@ -202,6 +203,16 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_CAN + /* Initialize CAN and register the CAN driver. */ + + ret = zkit_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: zkit_can_setup failed: %d\n", ret); + } +#endif + UNUSED(ret); return OK; } diff --git a/configs/zkit-arm-1769/src/lpc17_can.c b/configs/zkit-arm-1769/src/lpc17_can.c index 03176894a9..6b4a1021f8 100644 --- a/configs/zkit-arm-1769/src/lpc17_can.c +++ b/configs/zkit-arm-1769/src/lpc17_can.c @@ -6,7 +6,7 @@ * * Based on configs/olimex-lpc1766stk/src/lpc17_can.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -56,7 +56,7 @@ #include "lpc17_can.h" #include "zkit-arm-1769.h" -#if defined(CONFIG_CAN) && (defined(CONFIG_LPC17_CAN1) || defined(CONFIG_LPC17_CAN2)) +#ifdef CONFIG_CAN /************************************************************************************ * Pre-processor Definitions @@ -71,70 +71,63 @@ ************************************************************************************/ /************************************************************************************ - * Name: board_can_initialize + * Name: zkit_can_setup * * Description: - * All LPC17 architectures must provide the following interface to work with - * examples/can. + * Initialize CAN and register the CAN device * ************************************************************************************/ -int board_can_initialize(void) +int zkit_can_setup(void) { - static bool initialized = false; +#if defined(CONFIG_LPC17_CAN1) || defined(CONFIG_LPC17_CAN2) struct can_dev_s *can; int ret; - /* Check if we have already initialized */ +#ifdef CONFIG_LPC17_CAN1 + /* Call lpc17_caninitialize() to get an instance of the CAN1 interface */ - if (!initialized) + can = lpc17_caninitialize(CAN_PORT1); + if (can == NULL) { -#ifdef CONFIG_LPC17_CAN1 - /* Call lpc17_caninitialize() to get an instance of the CAN1 interface */ - - can = lpc17_caninitialize(CAN_PORT1); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN1 interface\n"); - return -ENODEV; - } - - /* Register the CAN1 driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: CAN1 register failed: %d\n", ret); - return ret; - } + canerr("ERROR: Failed to get CAN1 interface\n"); + return -ENODEV; + } + + /* Register the CAN1 driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: CAN1 register failed: %d\n", ret); + return ret; + } #endif #ifdef CONFIG_LPC17_CAN2 - /* Call lpc17_caninitialize() to get an instance of the CAN2 interface */ - - can = lpc17_caninitialize(CAN_PORT2); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN2 interface\n"); - return -ENODEV; - } - - /* Register the CAN2 driver at "/dev/can1" */ - - ret = can_register("/dev/can1", can); - if (ret < 0) - { - canerr("ERROR: CAN2 register failed: %d\n", ret); - return ret; - } -#endif + /* Call lpc17_caninitialize() to get an instance of the CAN2 interface */ + + can = lpc17_caninitialize(CAN_PORT2); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN2 interface\n"); + return -ENODEV; + } - /* Now we are initialized */ + /* Register the CAN2 driver at "/dev/can1" */ - initialized = true; + ret = can_register("/dev/can1", can); + if (ret < 0) + { + canerr("ERROR: CAN2 register failed: %d\n", ret); + return ret; } +#endif return OK; +#else + return -ENODEV; +#endif } -#endif /* CONFIG_CAN && (CONFIG_LPC17_CAN1 || CONFIG_LPC17_CAN2) */ +#endif /* CONFIG_CAN */ diff --git a/configs/zkit-arm-1769/src/zkit-arm-1769.h b/configs/zkit-arm-1769/src/zkit-arm-1769.h index 2ebaf011c8..1928c0bbb8 100644 --- a/configs/zkit-arm-1769/src/zkit-arm-1769.h +++ b/configs/zkit-arm-1769/src/zkit-arm-1769.h @@ -261,5 +261,17 @@ void weak_function zkit_spidev_initialize(void); int zkit_adc_setup(void); #endif +/************************************************************************************ + * Name: zkit_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ************************************************************************************/ + +#ifdef CONFIG_CAN +int zkit_can_setup(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* _CONFIGS_ZKITARM_LPC1768_SRC_ZKITARM_H */ diff --git a/include/nuttx/board.h b/include/nuttx/board.h index 0c436de8a3..f31398548d 100644 --- a/include/nuttx/board.h +++ b/include/nuttx/board.h @@ -338,25 +338,6 @@ struct fb_vtable_s; FAR struct fb_vtable_s *board_graphics_setup(unsigned int devno); #endif -/**************************************************************************** - * Name: board_can_initialize - * - * Description: - * Perform one-time CAN initialization. This is currently only needed for - * apps/examples/can. - * - * This is an internal OS interface but may be invoked indirectly from - * application-level graphics logic. If CONFIG_LIB_BOARDCTL=y and - * CONFIG_BOARDCTL_CANINIT=y, then this functions will be invoked via the - * (non-standard) boardctl() interface using the BOARDIOC_CAN_INITIALIZE - * command. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARDCTL_CANINIT -int board_can_initialize(void); -#endif - /**************************************************************************** * Name: board_ioctl * diff --git a/include/sys/boardctl.h b/include/sys/boardctl.h index 9a0e984358..c96215ec93 100644 --- a/include/sys/boardctl.h +++ b/include/sys/boardctl.h @@ -127,12 +127,6 @@ * CONFIGURATION: CONFIG_LIB_BOARDCTL && CONFIG_BOARDCTL_TSCTEST * DEPENDENCIES: Board logic must provide board_tsc_teardown() * - * CMD: BOARDIOC_CAN_INITIALIZE - * DESCRIPTION: CAN device initialization - * ARG: None - * CONFIGURATION: CONFIG_LIB_BOARDCTL && CONFIG_BOARDCTL_CANINIT - * DEPENDENCIES: Board logic must provide board_can_initialize() - * * CMD: BOARDIOC_GRAPHICS_SETUP * DESCRIPTION: Configure graphics that require special initialization * procedures @@ -151,8 +145,7 @@ #define BOARDIOC_NX_START _BOARDIOC(0x0008) #define BOARDIOC_TSCTEST_SETUP _BOARDIOC(0x0009) #define BOARDIOC_TSCTEST_TEARDOWN _BOARDIOC(0x000a) -#define BOARDIOC_CAN_INITIALIZE _BOARDIOC(0x000c) -#define BOARDIOC_GRAPHICS_SETUP _BOARDIOC(0x000c) +#define BOARDIOC_GRAPHICS_SETUP _BOARDIOC(0x000b) /* If CONFIG_BOARDCTL_IOCTL=y, then boad-specific commands will be support. * In this case, all commands not recognized by boardctl() will be forwarded -- GitLab From a441601281ef76d180c88312b09dd9e079c0265c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 6 Dec 2016 07:16:11 -0600 Subject: [PATCH 613/734] Eliminate a warning --- configs/teensy-lc/src/kl_appinit.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/teensy-lc/src/kl_appinit.c b/configs/teensy-lc/src/kl_appinit.c index 654d1dfae2..cfe2684ebd 100644 --- a/configs/teensy-lc/src/kl_appinit.c +++ b/configs/teensy-lc/src/kl_appinit.c @@ -45,6 +45,8 @@ #include +#include "teensy-lc.h" + #ifdef CONFIG_LIB_BOARDCTL /**************************************************************************** -- GitLab From d6437407b12682e0ac3436954c0bb2b538502c76 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 6 Dec 2016 09:03:00 -0600 Subject: [PATCH 614/734] Fix broken build. Previous commit removed a file that was being used. --- arch/arm/src/stm32/stm32_usbhost.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/stm32/stm32_usbhost.h b/arch/arm/src/stm32/stm32_usbhost.h index 7c036a8fa6..04a64190be 100644 --- a/arch/arm/src/stm32/stm32_usbhost.h +++ b/arch/arm/src/stm32/stm32_usbhost.h @@ -46,7 +46,7 @@ #include #include "chip.h" -#include "chip/stm32_otgfs.h" +#include "chip/stm32fxxxxx_otgfs.h" #include "chip/stm32_otghs.h" #if (defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS)) && defined(CONFIG_USBHOST) -- GitLab From 8e447453e1f0b41ae7b48175b63db4889c40dbf4 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 6 Dec 2016 09:22:03 -0600 Subject: [PATCH 615/734] Add a missing bit field definitions that was lost when stm32_otgfs.h was deleted. --- arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h | 27 +++++++++++---------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h b/arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h index bccc9c1708..9d6bd7bc47 100644 --- a/arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h +++ b/arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h @@ -475,34 +475,35 @@ # define OTGFS_GINTSTS_DEVMODE (0) # define OTGFS_GINTSTS_HOSTMODE (OTGFS_GINTSTS_CMOD) #define OTGFS_GINT_MMIS (1 << 1) /* Bit 1: rc_w1 Mode mismatch interrupt */ -#define OTGFS_GINT_OTG (1 << 2) /* Bit 2: ro OTG interrupt */ +#define OTGFS_GINT_OTG (1 << 2) /* Bit 2: ro OTG interrupt */ #define OTGFS_GINT_SOF (1 << 3) /* Bit 3: rc_w1 Start of frame */ -#define OTGFS_GINT_RXFLVL (1 << 4) /* Bit 4: ro RxFIFO non-empty */ -#define OTGFS_GINT_NPTXFE (1 << 5) /* Bit 5: ro Non-periodic TxFIFO empty */ -#define OTGFS_GINT_GINAKEFF (1 << 6) /* Bit 6: ro Global IN non-periodic NAK effective */ +#define OTGFS_GINT_RXFLVL (1 << 4) /* Bit 4: ro RxFIFO non-empty */ +#define OTGFS_GINT_NPTXFE (1 << 5) /* Bit 5: ro Non-periodic TxFIFO empty */ +#define OTGFS_GINT_GINAKEFF (1 << 6) /* Bit 6: ro Global IN non-periodic NAK effective */ #define OTGFS_GINT_GONAKEFF (1 << 7) /* Bit 7: Global OUT NAK effective */ -#define OTGFS_GINT_RES89 (3 << 8) /* Bits 8-9: Reserved, must be kept at reset value */ +#define OTGFS_GINT_RES89 (3 << 8) /* Bits 8-9: Reserved, must be kept at reset value */ #define OTGFS_GINT_ESUSP (1 << 10) /* Bit 10: rc_w1 Early suspend */ #define OTGFS_GINT_USBSUSP (1 << 11) /* Bit 11: rc_w1 USB suspend */ #define OTGFS_GINT_USBRST (1 << 12) /* Bit 12: rc_w1 USB reset */ #define OTGFS_GINT_ENUMDNE (1 << 13) /* Bit 13: rc_w1 Enumeration done */ #define OTGFS_GINT_ISOODRP (1 << 14) /* Bit 14: rc_w1 Isochronous OUT packet dropped interrupt */ #define OTGFS_GINT_EOPF (1 << 15) /* Bit 15: rc_w1 End of periodic frame interrupt */ -#define OTGFS_GINT_RES16 (1 << 16) /* Bits 16 Reserved, must be kept at reset value */ -#define OTGFS_GINTMSK_EPMISM (1 << 17) /* Bit 17: Reserved in GINT rw Endpoint mismatch interrupt mask */ -#define OTGFS_GINT_IEP (1 << 18) /* Bit 18: ro IN endpoint interrupt */ -#define OTGFS_GINT_OEP (1 << 19) /* Bit 19: ro OUT endpoint interrupt */ -#define OTGFS_GINT_IISOIXFR (1 << 20) /* Bit 20: rc_w1Incomplete isochronous IN transfer */ +#define OTGFS_GINT_RES16 (1 << 16) /* Bit 16 Reserved, must be kept at reset value */ +#define OTGFS_GINTMSK_EPMISM (1 << 17) /* Bit 17: Reserved in GINT rw Endpoint mismatch interrupt mask */ +#define OTGFS_GINT_IEP (1 << 18) /* Bit 18: ro IN endpoint interrupt */ +#define OTGFS_GINT_OEP (1 << 19) /* Bit 19: ro OUT endpoint interrupt */ +#define OTGFS_GINT_IISOIXFR (1 << 20) /* Bit 20: rc_w1 Incomplete isochronous IN transfer */ #define OTGFS_GINT_IISOOXFR (1 << 21) /* Bit 21: rc_w1 Incomplete isochronous OUT transfer */ +#define OTGFS_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */ #if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) # define OTGFS_GINT_RES22 (1 << 22) /* Bits 22: Reserved, must be kept at reset value */ # define OTGFS_GINT_RSTDET (1 << 23) /* Bits 23: asserted when a reset is detected on the USB in partial */ #else # define OTGFS_GINT_RES2223 (3 << 22) /* Bits 22-23: Reserved, must be kept at reset value */ #endif -#define OTGFS_GINT_HPRT (1 << 24) /* Bit 24: ro Host port interrupt */ -#define OTGFS_GINT_HC (1 << 25) /* Bit 25: ro Host channels interrupt */ -#define OTGFS_GINT_PTXFE (1 << 26) /* Bit 26: ro Periodic TxFIFO empty */ +#define OTGFS_GINT_HPRT (1 << 24) /* Bit 24: ro Host port interrupt */ +#define OTGFS_GINT_HC (1 << 25) /* Bit 25: ro Host channels interrupt */ +#define OTGFS_GINT_PTXFE (1 << 26) /* Bit 26: ro Periodic TxFIFO empty */ #if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) #define OTGFS_GINT_LPMINT (1 << 27) /* Bit 27 LPM interrupt */ #else -- GitLab From e190e1ee5b2d5b051371efa23839799c8fc70f4b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 6 Dec 2016 15:58:05 +0000 Subject: [PATCH 616/734] stm32fxxxxx_otgfs.h edited online with Bitbucket --- arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h b/arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h index 9d6bd7bc47..3660638267 100644 --- a/arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h +++ b/arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h @@ -493,7 +493,7 @@ #define OTGFS_GINT_IEP (1 << 18) /* Bit 18: ro IN endpoint interrupt */ #define OTGFS_GINT_OEP (1 << 19) /* Bit 19: ro OUT endpoint interrupt */ #define OTGFS_GINT_IISOIXFR (1 << 20) /* Bit 20: rc_w1 Incomplete isochronous IN transfer */ -#define OTGFS_GINT_IISOOXFR (1 << 21) /* Bit 21: rc_w1 Incomplete isochronous OUT transfer */ +#define OTGFS_GINT_IISOOXFR (1 << 21) /* Bit 21: rc_w1 Incomplete isochronous OUT transfer (device) */ #define OTGFS_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */ #if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) # define OTGFS_GINT_RES22 (1 << 22) /* Bits 22: Reserved, must be kept at reset value */ -- GitLab From b1a5364dd61a1d64fa320b28471e17491542835f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 6 Dec 2016 13:16:30 -0600 Subject: [PATCH 617/734] Eliminate a warning by adding missing include. --- configs/lpc4337-ws/src/lpc43_appinit.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/lpc4337-ws/src/lpc43_appinit.c b/configs/lpc4337-ws/src/lpc43_appinit.c index 3c5acc8584..8f9a074992 100644 --- a/configs/lpc4337-ws/src/lpc43_appinit.c +++ b/configs/lpc4337-ws/src/lpc43_appinit.c @@ -46,8 +46,9 @@ #include #include -#include "lpc43_i2c.h" #include "chip.h" +#include "lpc43_i2c.h" +#include "lpc4337-ws.h" /**************************************************************************** * Private Functions -- GitLab From 7cc0a06f448e8796d4c729595df0340f8190f279 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Tue, 6 Dec 2016 13:30:07 -1000 Subject: [PATCH 618/734] STM32: Allow the config to override the clock edge setting --- arch/arm/src/stm32/stm32_sdio.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm/src/stm32/stm32_sdio.c b/arch/arm/src/stm32/stm32_sdio.c index 6cd372b7fd..92437840b5 100644 --- a/arch/arm/src/stm32/stm32_sdio.c +++ b/arch/arm/src/stm32/stm32_sdio.c @@ -148,18 +148,26 @@ #define SDIO_CLKCR_RISINGEDGE (0) #define SDIO_CLKCR_FALLINGEDGE SDIO_CLKCR_NEGEDGE +/* Use the default of the rising edge but allow a configuration, + * that does not have the errata, to override the edge the SDIO + * command and data is changed on. + */ +#if !defined(SDIO_CLKCR_EDGE) +# define SDIO_CLKCR_EDGE SDIO_CLKCR_RISINGEDGE +#endif + /* Mode dependent settings. These depend on clock devisor settings that must * be defined in the board-specific board.h header file: SDIO_INIT_CLKDIV, * SDIO_MMCXFR_CLKDIV, and SDIO_SDXFR_CLKDIV. */ -#define STM32_CLCKCR_INIT (SDIO_INIT_CLKDIV | SDIO_CLKCR_RISINGEDGE | \ +#define STM32_CLCKCR_INIT (SDIO_INIT_CLKDIV | SDIO_CLKCR_EDGE | \ SDIO_CLKCR_WIDBUS_D1) -#define SDIO_CLKCR_MMCXFR (SDIO_MMCXFR_CLKDIV | SDIO_CLKCR_RISINGEDGE | \ +#define SDIO_CLKCR_MMCXFR (SDIO_MMCXFR_CLKDIV | SDIO_CLKCR_EDGE | \ SDIO_CLKCR_WIDBUS_D1) -#define SDIO_CLCKR_SDXFR (SDIO_SDXFR_CLKDIV | SDIO_CLKCR_RISINGEDGE | \ +#define SDIO_CLCKR_SDXFR (SDIO_SDXFR_CLKDIV | SDIO_CLKCR_EDGE | \ SDIO_CLKCR_WIDBUS_D1) -#define SDIO_CLCKR_SDWIDEXFR (SDIO_SDXFR_CLKDIV | SDIO_CLKCR_RISINGEDGE | \ +#define SDIO_CLCKR_SDWIDEXFR (SDIO_SDXFR_CLKDIV | SDIO_CLKCR_EDGE | \ SDIO_CLKCR_WIDBUS_D4) /* Timing */ -- GitLab From 9df1b28e6c716d002f7e17d3baac5c59fa59000c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 6 Dec 2016 17:40:52 -0600 Subject: [PATCH 619/734] SAMV71-XULT: Use syslog(LOG_ERR, ..) not the supposedly hidden _err() macro. --- configs/samv71-xult/src/sam_bringup.c | 87 ++++++++++++++++----------- 1 file changed, 52 insertions(+), 35 deletions(-) diff --git a/configs/samv71-xult/src/sam_bringup.c b/configs/samv71-xult/src/sam_bringup.c index cc2487719e..b24cfc9643 100644 --- a/configs/samv71-xult/src/sam_bringup.c +++ b/configs/samv71-xult/src/sam_bringup.c @@ -43,6 +43,7 @@ #include #include +#include #include #include @@ -120,14 +121,15 @@ static void sam_i2c_register(int bus) i2c = sam_i2cbus_initialize(bus); if (i2c == NULL) { - _err("ERROR: Failed to get I2C%d interface\n", bus); + syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); } else { ret = i2c_register(i2c, bus); if (ret < 0) { - _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", + bus, ret); sam_i2cbus_uninitialize(i2c); } } @@ -198,7 +200,8 @@ int sam_bringup(void) ret = userled_lower_initialize(LED_DRIVER_PATH); if (ret < 0) { - _err("ERROR: userled_lower_initialize() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", + ret); } #endif @@ -208,7 +211,8 @@ int sam_bringup(void) i2c = sam_i2cbus_initialize(PCF85263_TWI_BUS); if (i2c == NULL) { - _err("ERROR: sam_i2cbus_initialize(%d) failed\n", PCF85263_TWI_BUS); + syslog(LOG_ERR, "ERROR: sam_i2cbus_initialize(%d) failed\n", + PCF85263_TWI_BUS); } else { @@ -217,7 +221,8 @@ int sam_bringup(void) ret = pcf85263_rtc_initialize(i2c); if (ret < 0) { - _err("ERROR: pcf85263_rtc_initialize() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: pcf85263_rtc_initialize() failed: %d\n", + ret); } else { @@ -233,7 +238,8 @@ int sam_bringup(void) i2c = sam_i2cbus_initialize(DSXXXX_TWI_BUS); if (i2c == NULL) { - _err("ERROR: sam_i2cbus_initialize(%d) failed\n", DSXXXX_TWI_BUS); + syslog(LOG_ERR, "ERROR: sam_i2cbus_initialize(%d) failed\n", + DSXXXX_TWI_BUS); } else { @@ -242,7 +248,8 @@ int sam_bringup(void) ret = dsxxxx_rtc_initialize(i2c); if (ret < 0) { - _err("ERROR: dsxxxx_rtc_initialize() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: dsxxxx_rtc_initialize() failed: %d\n", + ret); } else { @@ -271,7 +278,7 @@ int sam_bringup(void) ret = sam_emac0_setmac(); if (ret < 0) { - _err("ERROR: sam_emac0_setmac() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: sam_emac0_setmac() failed: %d\n", ret); } #endif @@ -281,8 +288,8 @@ int sam_bringup(void) ret = mount(NULL, SAMV71_PROCFS_MOUNTPOINT, "procfs", 0, NULL); if (ret < 0) { - _err("ERROR: Failed to mount procfs at %s: %d\n", - SAMV71_PROCFS_MOUNTPOINT, ret); + syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", + SAMV71_PROCFS_MOUNTPOINT, ret); } #endif @@ -294,7 +301,7 @@ int sam_bringup(void) ret = sam_at24config(); if (ret < 0) { - _err("ERROR: sam_at24config() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: sam_at24config() failed: %d\n", ret); } #endif @@ -304,8 +311,8 @@ int sam_bringup(void) ret = sam_hsmci_initialize(HSMCI0_SLOTNO, HSMCI0_MINOR); if (ret < 0) { - _err("ERROR: sam_hsmci_initialize(%d,%d) failed: %d\n", - HSMCI0_SLOTNO, HSMCI0_MINOR, ret); + syslog(LOG_ERR, "ERROR: sam_hsmci_initialize(%d,%d) failed: %d\n", + HSMCI0_SLOTNO, HSMCI0_MINOR, ret); } #ifdef CONFIG_SAMV71XULT_HSMCI0_MOUNT @@ -321,8 +328,8 @@ int sam_bringup(void) if (ret < 0) { - _err("ERROR: Failed to mount %s: %d\n", - CONFIG_SAMV71XULT_HSMCI0_MOUNT_MOUNTPOINT, errno); + syslog(LOG_ERR, "ERROR: Failed to mount %s: %d\n", + CONFIG_SAMV71XULT_HSMCI0_MOUNT_MOUNTPOINT, errno); } } @@ -343,7 +350,7 @@ int sam_bringup(void) CONFIG_SAMV71XULT_ROMFS_ROMDISK_SECTSIZE); if (ret < 0) { - _err("ERROR: romdisk_register failed: %d\n", -ret); + syslog(LOG_ERR, "ERROR: romdisk_register failed: %d\n", -ret); } else { @@ -354,9 +361,9 @@ int sam_bringup(void) "romfs", MS_RDONLY, NULL); if (ret < 0) { - _err("ERROR: mount(%s,%s,romfs) failed: %d\n", - CONFIG_SAMV71XULT_ROMFS_ROMDISK_DEVNAME, - CONFIG_SAMV71XULT_ROMFS_MOUNT_MOUNTPOINT, errno); + syslog(LOG_ERR, "ERROR: mount(%s,%s,romfs) failed: %d\n", + CONFIG_SAMV71XULT_ROMFS_ROMDISK_DEVNAME, + CONFIG_SAMV71XULT_ROMFS_MOUNT_MOUNTPOINT, errno); } } #endif @@ -367,7 +374,7 @@ int sam_bringup(void) qspi = sam_qspi_initialize(0); if (!qspi) { - _err("ERROR: sam_qspi_initialize failed\n"); + syslog(LOG_ERR, "ERROR: sam_qspi_initialize failed\n"); } else { @@ -378,7 +385,7 @@ int sam_bringup(void) mtd = s25fl1_initialize(qspi, true); if (!mtd) { - _err("ERROR: s25fl1_initialize failed\n"); + syslog(LOG_ERR, "ERROR: s25fl1_initialize failed\n"); } #ifdef HAVE_S25FL1_SMARTFS @@ -387,7 +394,7 @@ int sam_bringup(void) ret = smart_initialize(S25FL1_SMART_MINOR, mtd, NULL); if (ret != OK) { - _err("ERROR: Failed to initialize SmartFS: %d\n", ret); + syslog(LOG_ERR, "ERROR: Failed to initialize SmartFS: %d\n", ret); } #elif defined(HAVE_S25FL1_NXFFS) @@ -396,7 +403,7 @@ int sam_bringup(void) ret = nxffs_initialize(mtd); if (ret < 0) { - _err("ERROR: NXFFS initialization failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: NXFFS initialization failed: %d\n", ret); } /* Mount the file system at /mnt/s25fl1 */ @@ -404,7 +411,8 @@ int sam_bringup(void) ret = mount(NULL, "/mnt/s25fl1", "nxffs", 0, NULL); if (ret < 0) { - _err("ERROR: Failed to mount the NXFFS volume: %d\n", errno); + syslog(LOG_ERR, "ERROR: Failed to mount the NXFFS volume: %d\n", + errno); return ret; } @@ -414,7 +422,8 @@ int sam_bringup(void) ret = ftl_initialize(S25FL1_MTD_MINOR, mtd); if (ret < 0) { - _err("ERROR: Failed to initialize the FTL layer: %d\n", ret); + syslog(LOG_ERR, "ERROR: Failed to initialize the FTL layer: %d\n", + ret); return ret; } @@ -428,7 +437,8 @@ int sam_bringup(void) ret = bchdev_register(blockdev, chardev, false); if (ret < 0) { - _err("ERROR: bchdev_register %s failed: %d\n", chardev, ret); + syslog(LOG_ERR, "ERROR: bchdev_register %s failed: %d\n", + chardev, ret); return ret; } #endif @@ -445,7 +455,7 @@ int sam_bringup(void) mtd = progmem_initialize(); if (!mtd) { - _err("ERROR: progmem_initialize failed\n"); + syslog(LOG_ERR, "ERROR: progmem_initialize failed\n"); } /* Use the FTL layer to wrap the MTD driver as a block driver */ @@ -453,7 +463,8 @@ int sam_bringup(void) ret = ftl_initialize(PROGMEM_MTD_MINOR, mtd); if (ret < 0) { - _err("ERROR: Failed to initialize the FTL layer: %d\n", ret); + syslog(LOG_ERR, "ERROR: Failed to initialize the FTL layer: %d\n", + ret); return ret; } @@ -467,7 +478,8 @@ int sam_bringup(void) ret = bchdev_register(blockdev, chardev, false); if (ret < 0) { - _err("ERROR: bchdev_register %s failed: %d\n", chardev, ret); + syslog(LOG_ERR, "ERROR: bchdev_register %s failed: %d\n", + chardev, ret); return ret; } #endif @@ -480,7 +492,7 @@ int sam_bringup(void) ret = sam_usbhost_initialize(); if (ret != OK) { - _err("ERROR: Failed to initialize USB host: %d\n", ret); + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); } #endif @@ -490,7 +502,7 @@ int sam_bringup(void) ret = usbmonitor_start(); if (ret != OK) { - _err("ERROR: Failed to start the USB monitor: %d\n", ret); + syslog(LOG_ERR, "ERROR: Failed to start the USB monitor: %d\n", ret); } #endif @@ -500,7 +512,8 @@ int sam_bringup(void) ret = sam_wm8904_initialize(0); if (ret != OK) { - _err("ERROR: Failed to initialize WM8904 audio: %d\n", ret); + syslog(LOG_ERR, "ERROR: Failed to initialize WM8904 audio: %d\n", + ret); } #endif @@ -510,18 +523,22 @@ int sam_bringup(void) ret = sam_audio_null_initialize(0); if (ret != OK) { - _err("ERROR: Failed to initialize the NULL audio device: %d\n", ret); + syslog(LOG_ERR, + "ERROR: Failed to initialize the NULL audio device: %d\n", + ret); } #endif #ifdef HAVE_ELF /* Initialize the ELF binary loader */ - _err("Initializing the ELF binary loader\n"); + syslog(LOG_ERR, "Initializing the ELF binary loader\n"); ret = elf_initialize(); if (ret < 0) { - _err("ERROR: Initialization of the ELF loader failed: %d\n", ret); + syslog(LOG_ERR, + "ERROR: Initialization of the ELF loader failed: %d\n", + ret); } #endif -- GitLab From cbf863b1cadc5c651e368f5d305866eb14246aa9 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Tue, 6 Dec 2016 13:43:57 -1000 Subject: [PATCH 620/734] STM32F7: Allow the config to override the clock edge setting --- arch/arm/src/stm32f7/stm32_sdmmc.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index 3e6aff9620..5984b2741d 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -153,7 +153,15 @@ /* Friendly CLKCR bit re-definitions ****************************************/ #define STM32_CLKCR_RISINGEDGE (0) -#define STM32_CLKCR_FALLINGEDGE STM32_CLKCR_NEGEDGE +#define STM32_CLKCR_FALLINGEDGE STM32_SDMMC_CLKCR_NEGEDGE + +/* Use the default of the rising edge but allow a configuration, + * that does not have the errata, to override the edge the SDIO + * command and data is changed on. + */ +#if !defined(STM32_SDMMC_CLKCR_EDGE) +# define STM32_SDMMC_CLKCR_EDGE STM32_CLKCR_RISINGEDGE +#endif /* Mode dependent settings. These depend on clock divisor settings that must * be defined in the board-specific board.h header file: STM32_SDMMC_INIT_CLKDIV, @@ -161,16 +169,16 @@ */ #define STM32_CLCKCR_INIT (STM32_SDMMC_INIT_CLKDIV | \ - STM32_CLKCR_RISINGEDGE | \ + STM32_SDMMC_CLKCR_EDGE | \ STM32_SDMMC_CLKCR_WIDBUS_D1) #define STM32_SDMMC_CLKCR_MMCXFR (STM32_SDMMC_MMCXFR_CLKDIV | \ - STM32_CLKCR_RISINGEDGE | \ + STM32_SDMMC_CLKCR_EDGE | \ STM32_SDMMC_CLKCR_WIDBUS_D1) #define STM32_SDMMC_CLCKR_SDXFR (STM32_SDMMC_SDXFR_CLKDIV | \ - STM32_CLKCR_RISINGEDGE | \ + STM32_SDMMC_CLKCR_EDGE | \ STM32_SDMMC_CLKCR_WIDBUS_D1) #define STM32_SDMMC_CLCKR_SDWIDEXFR (STM32_SDMMC_SDXFR_CLKDIV | \ - STM32_CLKCR_RISINGEDGE | \ + STM32_SDMMC_CLKCR_EDGE | \ STM32_SDMMC_CLKCR_WIDBUS_D4) /* Timing */ -- GitLab From b9be0279b1730e380ac6ffe772064b80c0101a78 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 7 Dec 2016 06:52:15 -0600 Subject: [PATCH 621/734] Coding standard requires a blank line after every comment. --- arch/arm/src/stm32/stm32_sdio.c | 1 + arch/arm/src/stm32f7/stm32_sdmmc.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/src/stm32/stm32_sdio.c b/arch/arm/src/stm32/stm32_sdio.c index 4758fb0bb1..9d93a432c0 100644 --- a/arch/arm/src/stm32/stm32_sdio.c +++ b/arch/arm/src/stm32/stm32_sdio.c @@ -153,6 +153,7 @@ * that does not have the errata, to override the edge the SDIO * command and data is changed on. */ + #if !defined(SDIO_CLKCR_EDGE) # define SDIO_CLKCR_EDGE SDIO_CLKCR_RISINGEDGE #endif diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index 5abde30705..2df98c10a9 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -160,6 +160,7 @@ * that does not have the errata, to override the edge the SDIO * command and data is changed on. */ + #if !defined(STM32_SDMMC_CLKCR_EDGE) # define STM32_SDMMC_CLKCR_EDGE STM32_CLKCR_RISINGEDGE #endif -- GitLab From dc79e35d65dbace7763317ad95a2995340e3dac1 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 7 Dec 2016 09:06:41 -0600 Subject: [PATCH 622/734] For Cortex-A9, should also set ACTLR.FW in SMP mode to enble TLB and cache broadcasts. Does not fix SMP cache problem. --- arch/arm/src/armv7-a/arm_scu.c | 16 +++++++++++++++- arch/arm/src/armv7-a/cache.h | 10 ++++++++++ arch/arm/src/armv7-r/cache.h | 4 ++-- 3 files changed, 27 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_scu.c b/arch/arm/src/armv7-a/arm_scu.c index e1fdd52925..eedf179e73 100644 --- a/arch/arm/src/armv7-a/arm_scu.c +++ b/arch/arm/src/armv7-a/arm_scu.c @@ -44,6 +44,7 @@ #include "up_arch.h" #include "cp15_cacheops.h" #include "sctlr.h" +#include "cache.h" #include "scu.h" #ifdef CONFIG_SMP @@ -174,6 +175,7 @@ void arm_enable_smp(int cpu) */ cp15_invalidate_dcache_all(); + ARM_DSB(); /* Invalidate the L2C-310 -- Missing logic. */ @@ -193,16 +195,28 @@ void arm_enable_smp(int cpu) */ cp15_invalidate_dcache_all(); + ARM_DSB(); /* Wait for the SCU to be enabled by the primary processor -- should * not be necessary. */ } - /* Enable the data cache, set the SMP mode with ACTLR.SMP=1. */ + /* Enable the data cache, set the SMP mode with ACTLR.SMP=1. + * + * SMP - Sgnals if the Cortex-A9 processor is taking part in coherency + * or not. + * + * Cortex-A9 also needs ACTLR.FW=1 + * + * FW - Cache and TLB maintenance broadcast. + */ regval = arm_get_actlr(); regval |= ACTLR_SMP; +#ifdef CONFIG_ARCH_CORTEXA9 + regval |= ACTLR_FW; +#endif arm_set_actlr(regval); regval = arm_get_sctlr(); diff --git a/arch/arm/src/armv7-a/cache.h b/arch/arm/src/armv7-a/cache.h index dda36271e2..c9af0611f7 100644 --- a/arch/arm/src/armv7-a/cache.h +++ b/arch/arm/src/armv7-a/cache.h @@ -50,6 +50,16 @@ * Pre-processor Definitions ************************************************************************************/ +/* Intrinsics are used in these inline functions */ + +#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory") +#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory") +#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory") + +#define ARM_DSB() arm_dsb(15) +#define ARM_ISB() arm_isb(15) +#define ARM_DMB() arm_dmb(15) + /************************************************************************************ * Inline Functions ************************************************************************************/ diff --git a/arch/arm/src/armv7-r/cache.h b/arch/arm/src/armv7-r/cache.h index a0d25c8941..721f40313f 100644 --- a/arch/arm/src/armv7-r/cache.h +++ b/arch/arm/src/armv7-r/cache.h @@ -51,7 +51,7 @@ * Pre-processor Definitions ************************************************************************************/ -/* intrinsics are used in these inline functions */ +/* Intrinsics are used in these inline functions */ #define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory") #define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory") @@ -61,7 +61,7 @@ #define ARM_ISB() arm_isb(15) #define ARM_DMB() arm_dmb(15) - /************************************************************************************ +/************************************************************************************ * Inline Functions ************************************************************************************/ -- GitLab From a7b688e87b87d6e85e2928ef2b112920ebbb14d3 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 7 Dec 2016 09:08:20 -0600 Subject: [PATCH 623/734] sched notes: Add additional note to see if/when CPU is started in SMP mode. --- arch/arm/src/armv7-a/arm_cpustart.c | 16 +++++++++++++-- arch/arm/src/sam34/sam4cm_cpustart.c | 17 +++++++++++++++- arch/xtensa/src/esp32/esp32_cpustart.c | 16 +++++++++++++-- configs/sabre-6quad/README.txt | 3 +++ configs/sabre-6quad/src/imx_bringup.c | 16 ++++++++++++++- include/nuttx/sched_note.h | 24 +++++++++++++++++++++++ sched/sched/sched_note.c | 27 ++++++++++++++++++++++++++ 7 files changed, 113 insertions(+), 6 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_cpustart.c b/arch/arm/src/armv7-a/arm_cpustart.c index 012d2e438e..d63c035db6 100644 --- a/arch/arm/src/armv7-a/arm_cpustart.c +++ b/arch/arm/src/armv7-a/arm_cpustart.c @@ -43,6 +43,7 @@ #include #include +#include #include "up_internal.h" #include "cp15_cacheops.h" @@ -104,13 +105,18 @@ static inline void arm_registerdump(FAR struct tcb_s *tcb) int arm_start_handler(int irq, FAR void *context) { - FAR struct tcb_s *tcb; + FAR struct tcb_s *tcb = this_task(); sinfo("CPU%d Started\n", this_cpu()); +#ifdef CONFIG_SCHED_INSTRUMENTATION + /* Notify that this CPU has started */ + + sched_note_cpu_started(tcb); +#endif + /* Reset scheduler parameters */ - tcb = this_task(); sched_resume_scheduler(tcb); /* Dump registers so that we can see what is going to happen on return */ @@ -159,6 +165,12 @@ int up_cpu_start(int cpu) DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu()); +#ifdef CONFIG_SCHED_INSTRUMENTATION + /* Notify of the start event */ + + sched_note_cpu_start(this_task(), cpu); +#endif + /* Make the content of CPU0 L1 cache has been written to coherent L2 */ cp15_clean_dcache(CONFIG_RAM_START, CONFIG_RAM_END - 1); diff --git a/arch/arm/src/sam34/sam4cm_cpustart.c b/arch/arm/src/sam34/sam4cm_cpustart.c index 44c8d9508c..7a5c62f0fc 100644 --- a/arch/arm/src/sam34/sam4cm_cpustart.c +++ b/arch/arm/src/sam34/sam4cm_cpustart.c @@ -47,6 +47,7 @@ #include #include +#include #include "nvic.h" #include "up_arch.h" @@ -124,6 +125,12 @@ static void cpu1_boot(void) spin_unlock(&g_cpu1_boot); +#ifdef CONFIG_SCHED_INSTRUMENTATION + /* Notify that this CPU has started */ + + sched_note_cpu_started(this_task()); +#endif + /* Then transfer control to the IDLE task */ (void)os_idle_task(0, NULL); @@ -163,7 +170,15 @@ int up_cpu_start(int cpu) DPRINTF("cpu=%d\n",cpu); if (cpu != 1) - return -1; + { + return -EINVAL; + } + +#ifdef CONFIG_SCHED_INSTRUMENTATION + /* Notify of the start event */ + + sched_note_cpu_start(this_task(), cpu); +#endif /* Reset coprocessor */ diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c index 3a603579b6..90998f107c 100644 --- a/arch/xtensa/src/esp32/esp32_cpustart.c +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -47,6 +47,7 @@ #include #include #include +#include #include "sched/sched.h" #include "xtensa.h" @@ -152,11 +153,17 @@ static inline void xtensa_attach_fromcpu0_interrupt(void) int xtensa_start_handler(int irq, FAR void *context) { - FAR struct tcb_s *tcb; + FAR struct tcb_s *tcb = this_task(); int i; sinfo("CPU%d Started\n", up_cpu_index()); +#ifdef CONFIG_SCHED_INSTRUMENTATION + /* Notify that this CPU has started */ + + sched_note_cpu_started(tcb); +#endif + /* Handle interlock*/ g_appcpu_started = true; @@ -164,7 +171,6 @@ int xtensa_start_handler(int irq, FAR void *context) /* Reset scheduler parameters */ - tcb = this_task(); sched_resume_scheduler(tcb); /* Move CPU0 exception vectors to IRAM */ @@ -261,6 +267,12 @@ int up_cpu_start(int cpu) sinfo("Starting CPU%d\n", cpu); +#ifdef CONFIG_SCHED_INSTRUMENTATION + /* Notify of the start event */ + + sched_note_cpu_start(this_task(), cpu); +#endif + /* The waitsem semaphore is used for signaling and, hence, should not * have priority inheritance enabled. */ diff --git a/configs/sabre-6quad/README.txt b/configs/sabre-6quad/README.txt index ab4d4b5fa0..dda5ef7620 100644 --- a/configs/sabre-6quad/README.txt +++ b/configs/sabre-6quad/README.txt @@ -118,6 +118,9 @@ Status 2016-12-01: I committed a completely untest SPI driver. This was taken directly from the i.MX1 and is most certainly not ready for use yet. +2016-12-07: Just a note to remind myself. The PL310 L2 cache has *not* + yet been enbled. + Platform Features ================= diff --git a/configs/sabre-6quad/src/imx_bringup.c b/configs/sabre-6quad/src/imx_bringup.c index 13f1742c15..6c3f4949ba 100644 --- a/configs/sabre-6quad/src/imx_bringup.c +++ b/configs/sabre-6quad/src/imx_bringup.c @@ -40,7 +40,8 @@ #include #include -#include +#include +#include #include "sabre-6quad.h" @@ -58,5 +59,18 @@ int imx_bringup(void) { + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + + UNUSED(ret); return OK; } diff --git a/include/nuttx/sched_note.h b/include/nuttx/sched_note.h index c27e931deb..47c028b617 100644 --- a/include/nuttx/sched_note.h +++ b/include/nuttx/sched_note.h @@ -82,6 +82,8 @@ enum note_type_e NOTE_RESUME #ifdef CONFIG_SMP , + NOTE_CPU_START, + NOTE_CPU_STARTED, NOTE_CPU_PAUSE, NOTE_CPU_PAUSED, NOTE_CPU_RESUME, @@ -153,6 +155,22 @@ struct note_resume_s }; #ifdef CONFIG_SMP + +/* This is the specific form of the NOTE_CPU_START note */ + +struct note_cpu_start_s +{ + struct note_common_s ncs_cmn; /* Common note parameters */ + uint8_t ncs_target; /* CPU being started */ +}; + +/* This is the specific form of the NOTE_CPU_STARTED note */ + +struct note_cpu_started_s +{ + struct note_common_s ncs_cmn; /* Common note parameters */ +}; + /* This is the specific form of the NOTE_CPU_PAUSE note */ struct note_cpu_pause_s @@ -248,11 +266,15 @@ void sched_note_suspend(FAR struct tcb_s *tcb); void sched_note_resume(FAR struct tcb_s *tcb); #ifdef CONFIG_SMP +void sched_note_cpu_start(FAR struct tcb_s *tcb, int cpu); +void sched_note_cpu_started(FAR struct tcb_s *tcb); void sched_note_cpu_pause(FAR struct tcb_s *tcb, int cpu); void sched_note_cpu_paused(FAR struct tcb_s *tcb); void sched_note_cpu_resume(FAR struct tcb_s *tcb, int cpu); void sched_note_cpu_resumed(FAR struct tcb_s *tcb); #else +# define sched_note_cpu_start(t,c) +# define sched_note_cpu_started(t) # define sched_note_cpu_pause(t,c) # define sched_note_cpu_paused(t) # define sched_note_cpu_resume(t,c) @@ -353,6 +375,8 @@ int note_register(void); # define sched_note_stop(t) # define sched_note_suspend(t) # define sched_note_resume(t) +# define sched_note_cpu_start(t,c) +# define sched_note_cpu_started(t) # define sched_note_cpu_pause(t,c) # define sched_note_cpu_paused(t) # define sched_note_cpu_resume(t,c) diff --git a/sched/sched/sched_note.c b/sched/sched/sched_note.c index 22d87b8264..cf7b475c61 100644 --- a/sched/sched/sched_note.c +++ b/sched/sched/sched_note.c @@ -435,6 +435,33 @@ void sched_note_resume(FAR struct tcb_s *tcb) } #ifdef CONFIG_SMP +void sched_note_cpu_start(FAR struct tcb_s *tcb, int cpu) +{ + struct note_cpu_start_s note; + + /* Format the note */ + + note_common(tcb, ¬e.ncs_cmn, sizeof(struct note_cpu_start_s), NOTE_CPU_START); + note.ncs_target = (uint8_t)cpu; + + /* Add the note to circular buffer */ + + note_add((FAR const uint8_t *)¬e, sizeof(struct note_cpu_start_s)); +} + +void sched_note_cpu_started(FAR struct tcb_s *tcb) +{ + struct note_cpu_started_s note; + + /* Format the note */ + + note_common(tcb, ¬e.ncs_cmn, sizeof(struct note_cpu_started_s), NOTE_CPU_STARTED); + + /* Add the note to circular buffer */ + + note_add((FAR const uint8_t *)¬e, sizeof(struct note_cpu_started_s)); +} + void sched_note_cpu_pause(FAR struct tcb_s *tcb, int cpu) { struct note_cpu_pause_s note; -- GitLab From 017773eda37d6ac60e4a74b92544b4df67902b5f Mon Sep 17 00:00:00 2001 From: Pierre-noel Bouteville Date: Wed, 7 Dec 2016 09:13:13 -0600 Subject: [PATCH 624/734] EFM32: Fix a compilation error --- arch/arm/src/efm32/efm32_lowputc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/efm32/efm32_lowputc.c b/arch/arm/src/efm32/efm32_lowputc.c index b3fa2ee386..26ec02884a 100644 --- a/arch/arm/src/efm32/efm32_lowputc.c +++ b/arch/arm/src/efm32/efm32_lowputc.c @@ -281,7 +281,8 @@ static void efm32_leuart_setbaud(uintptr_t base, uint32_t baud) void efm32_lowsetup(void) { -#if defined(HAVE_UART_DEVICE) || defined(HAVE_LEUART_DEVICE) +#if defined(HAVE_UART_DEVICE) || defined(HAVE_LEUART_DEVICE) || \ + defined(HAVE_SPI_DEVICE) uint32_t regval; #endif -- GitLab From 7632dfd6c76b88eb7b1c9daf72194f6efedb31d3 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 8 Dec 2016 07:52:02 -0600 Subject: [PATCH 625/734] Update some comments. --- sched/task/task_exithook.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/sched/task/task_exithook.c b/sched/task/task_exithook.c index cffae18e7d..3f75ec7ca1 100644 --- a/sched/task/task_exithook.c +++ b/sched/task/task_exithook.c @@ -73,6 +73,9 @@ static inline void task_atexit(FAR struct tcb_s *tcb) /* Make sure that we have not already left the group. Only the final * exiting thread in the task group should trigger the atexit() * callbacks. + * + * REVISIT: This is a security problem In the PROTECTED and KERNEL builds: + * We must not call the registered function in supervisor mode! */ if (group && group->tg_nmembers == 1) @@ -133,6 +136,9 @@ static inline void task_onexit(FAR struct tcb_s *tcb, int status) /* Make sure that we have not already left the group. Only the final * exiting thread in the task group should trigger the atexit() * callbacks. + * + * REVISIT: This is a security problem In the PROTECTED and KERNEL builds: + * We must not call the registered function in supervisor mode! */ if (group && group->tg_nmembers == 1) -- GitLab From a1fbc2ad0d1f3ac2fcf761866d29fdd5a99e40be Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 8 Dec 2016 09:27:13 -0600 Subject: [PATCH 626/734] pthreads: Add pthread_cleanup_push() and pthread_cleanup_pop() --- TODO | 4 +- include/nuttx/sched.h | 23 ++++ include/pthread.h | 15 +++ include/sys/syscall.h | 14 ++- sched/Kconfig | 18 +++ sched/pthread/Make.defs | 4 + sched/pthread/pthread.h | 5 + sched/pthread/pthread_cancel.c | 20 ++- sched/pthread/pthread_cleanup.c | 212 ++++++++++++++++++++++++++++++++ sched/pthread/pthread_exit.c | 9 ++ sched/task/task_exithook.c | 6 +- syscall/syscall.csv | 2 + syscall/syscall_lookup.h | 4 + syscall/syscall_stublookup.c | 4 + 14 files changed, 327 insertions(+), 13 deletions(-) create mode 100644 sched/pthread/pthread_cleanup.c diff --git a/TODO b/TODO index 9282df6df6..9b8776acd0 100644 --- a/TODO +++ b/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated December 3, 2016) +NuttX TODO List (Last updated December 17, 2016) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with @@ -101,7 +101,7 @@ o Task/Scheduler (sched/) Status: Open Priority: Medium Low for now - Title: ISSUES WITH atexit() AND on_exit() + Title: ISSUES WITH atexit(), on_exit(), AND pthread_cleanup_pop() Description: These functions execute with the following bad properties: 1. They run with interrupts disabled, diff --git a/include/nuttx/sched.h b/include/nuttx/sched.h index ec438727f8..81d72c6e60 100644 --- a/include/nuttx/sched.h +++ b/include/nuttx/sched.h @@ -322,6 +322,18 @@ struct child_status_s }; #endif +/* struct pthread_cleanup_s ******************************************************/ + +#ifdef CONFIG_PTHREAD_CLEANUP +/* This structure describes one element of the pthread cleanup stack */ + +struct pthread_cleanup_s +{ + pthread_cleanup_t pc_cleaner; /* Cleanup callback address */ + FAR void *pc_arg; /* Argument that accompanies the callback */ +}; +#endif + /* struct dspace_s ***************************************************************/ /* This structure describes a reference counted D-Space region. This must be a * separately allocated "break-away" structure that can be owned by a task and @@ -682,6 +694,17 @@ struct pthread_tcb_s pthread_addr_t arg; /* Startup argument */ FAR void *joininfo; /* Detach-able info to support join */ + /* Clean-up stack *************************************************************/ + +#ifdef CONFIG_PTHREAD_CLEANUP + /* tos - The index to the next avaiable entry at the top of the stack. + * stack - The pre-allocated clean-up stack memory. + */ + + uint8_t tos; + struct pthread_cleanup_s stack[CONFIG_PTHREAD_CLEANUP_STACKSIZE]; +#endif + /* POSIX Thread Specific Data *************************************************/ #if CONFIG_NPTHREAD_KEYS > 0 diff --git a/include/pthread.h b/include/pthread.h index ac495e44c2..28bb0add97 100644 --- a/include/pthread.h +++ b/include/pthread.h @@ -265,6 +265,12 @@ typedef struct pthread_barrier_s pthread_barrier_t; typedef bool pthread_once_t; #define __PTHREAD_ONCE_T_DEFINED 1 +#ifdef CONFIG_PTHREAD_CLEANUP +/* This type describes the pthread cleanup callback (non-standard) */ + +typedef CODE void (*pthread_cleanup_t)(FAR void *arg); +#endif + /* Forward references */ struct sched_param; /* Defined in sched.h */ @@ -336,6 +342,15 @@ int pthread_cancel(pthread_t thread); int pthread_setcancelstate(int state, FAR int *oldstate); void pthread_testcancel(void); +/* A thread may set up cleanup functions to execut when the thread exits or + * is canceled. + */ + +#ifdef CONFIG_PTHREAD_CLEANUP +void pthread_cleanup_pop(int execute); +void pthread_cleanup_push(pthread_cleanup_t routine, FAR void *arg); +#endif + /* A thread can await termination of another thread and retrieve the return * value of the thread. */ diff --git a/include/sys/syscall.h b/include/sys/syscall.h index d0bfcd9597..5c13ec70e3 100644 --- a/include/sys/syscall.h +++ b/include/sys/syscall.h @@ -406,7 +406,7 @@ # define SYS_pthread_setspecific (__SYS_pthread+26) # define SYS_pthread_yield (__SYS_pthread+27) -# ifndef CONFIG_SMP +# ifdef CONFIG_SMP # define SYS_pthread_setaffinity_np (__SYS_pthread+28) # define SYS_pthread_getaffinity_np (__SYS_pthread+29) # define __SYS_pthread_signals (__SYS_pthread+30) @@ -418,9 +418,17 @@ # define SYS_pthread_cond_timedwait (__SYS_pthread_signals+0) # define SYS_pthread_kill (__SYS_pthread_signals+1) # define SYS_pthread_sigmask (__SYS_pthread_signals+2) -# define __SYS_mqueue (__SYS_pthread_signals+3) +# define __SYS_pthread_cleanup (__SYS_pthread_signals+3) # else -# define __SYS_mqueue __SYS_pthread_signals +# define __SYS_pthread_cleanup __SYS_pthread_signals +# endif + +# ifdef CONFIG_PTHREAD_CLEANUP +# define __SYS_pthread_cleanup_push (__SYS_pthread_cleanup+0) +# define __SYS_pthread_cleanup_pop (__SYS_pthread_cleanup+1) +# define __SYS_mqueue (__SYS_pthread_cleanup+2) +# else +# define __SYS_mqueue __SYS_pthread_cleanup # endif #else diff --git a/sched/Kconfig b/sched/Kconfig index 4b0e068e6f..6f938bf45b 100644 --- a/sched/Kconfig +++ b/sched/Kconfig @@ -537,6 +537,24 @@ config NPTHREAD_KEYS The number of items of thread- specific data that can be retained +config PTHREAD_CLEANUP + bool "pthread cleanup stack" + default n + ---help--- + Select to enable support for pthread exit cleanup stacks. This + enables the interfaces pthread_cleanup_push() and + pthread_cleanup_pop(). + +config PTHREAD_CLEANUP_STACKSIZE + int "pthread cleanup stack size" + default 1 + range 1 32 + depends on PTHREAD_CLEANUP + ---help--- + The maximum number of cleanup actions that may be pushed by + pthread_clean_push(). This setting will increase the size of EVERY + pthread task control block by about 8 * CONFIG_PTHREAD_CLEANUP_STACKSIZE. + endmenu # Pthread Options menu "Performance Monitoring" diff --git a/sched/pthread/Make.defs b/sched/pthread/Make.defs index d27938aa37..a08315c732 100644 --- a/sched/pthread/Make.defs +++ b/sched/pthread/Make.defs @@ -55,6 +55,10 @@ ifeq ($(CONFIG_SMP),y) CSRCS += pthread_setaffinity.c pthread_getaffinity.c endif +ifeq ($(CONFIG_PTHREAD_CLEANUP),y) +CSRCS += pthread_cleanup.c +endif + # Include pthread build support DEPPATH += --dep-path pthread diff --git a/sched/pthread/pthread.h b/sched/pthread/pthread.h index 6371e9df33..be7a20de2e 100644 --- a/sched/pthread/pthread.h +++ b/sched/pthread/pthread.h @@ -96,6 +96,11 @@ struct task_group_s; /* Forward reference */ void weak_function pthread_initialize(void); int pthread_schedsetup(FAR struct pthread_tcb_s *tcb, int priority, start_t start, pthread_startroutine_t entry); + +#ifdef CONFIG_PTHREAD_CLEANUP +void pthread_cleanup_popall(FAR struct pthread_tcb_s *tcb); +#endif + int pthread_completejoin(pid_t pid, FAR void *exit_value); void pthread_destroyjoin(FAR struct task_group_s *group, FAR struct join_s *pjoin); diff --git a/sched/pthread/pthread_cancel.c b/sched/pthread/pthread_cancel.c index a8ba2ee4c9..e651259bc0 100644 --- a/sched/pthread/pthread_cancel.c +++ b/sched/pthread/pthread_cancel.c @@ -53,7 +53,7 @@ int pthread_cancel(pthread_t thread) { - FAR struct tcb_s *tcb; + FAR struct pthread_tcb_s *tcb; /* First, make sure that the handle references a valid thread */ @@ -66,8 +66,8 @@ int pthread_cancel(pthread_t thread) return ESRCH; } - tcb = sched_gettcb((pid_t)thread); - if (!tcb) + tcb = (FAR struct pthread_tcb_s *)sched_gettcb((pid_t)thread); + if (tcb == NULL) { /* The pid does not correspond to any known thread. The thread * has probably already exited. @@ -76,13 +76,15 @@ int pthread_cancel(pthread_t thread) return ESRCH; } + DEBUGASSERT((tcb-cmn.flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD); + /* Check to see if this thread has the non-cancelable bit set in its * flags. Suppress context changes for a bit so that the flags are stable. * (the flags should not change in interrupt handling. */ sched_lock(); - if ((tcb->flags & TCB_FLAG_NONCANCELABLE) != 0) + if ((tcb->cmn.flags & TCB_FLAG_NONCANCELABLE) != 0) { /* Then we cannot cancel the thread now. Here is how this is * supposed to work: @@ -97,7 +99,7 @@ int pthread_cancel(pthread_t thread) * processing." */ - tcb->flags |= TCB_FLAG_CANCEL_PENDING; + tcb->cmn.flags |= TCB_FLAG_CANCEL_PENDING; sched_unlock(); return OK; } @@ -108,11 +110,17 @@ int pthread_cancel(pthread_t thread) * same as pthread_exit(PTHREAD_CANCELED). */ - if (tcb == this_task()) + if (tcb == (FAR struct pthread_tcb_s *)this_task()) { pthread_exit(PTHREAD_CANCELED); } +#ifdef CONFIG_PTHREAD_CLEANUP + /* Perform any stack pthread clean-up callbacks */ + + pthread_cleanup_popall(tcb); +#endif + /* Complete pending join operations */ (void)pthread_completejoin((pid_t)thread, PTHREAD_CANCELED); diff --git a/sched/pthread/pthread_cleanup.c b/sched/pthread/pthread_cleanup.c new file mode 100644 index 0000000000..304d572f21 --- /dev/null +++ b/sched/pthread/pthread_cleanup.c @@ -0,0 +1,212 @@ +/**************************************************************************** + * sched/pthread/pthread_cleanup.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "sched/sched.h" +#include "pthread/pthread.h" + +#ifdef CONFIG_PTHREAD_CLEANUP + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pthread_cleanup_pop_tcb + * + * Description: + * The pthread_cleanup_pop_tcb() function will remove the routine at the top + * of the calling thread's cancellation cleanup stack and optionally + * invoke it (if 'execute' is non-zero). + * + * Input Parameters: + * tcb - The TCB of the pthread that is exiting or being canceled. + * + * Return Value: + * None + * + ****************************************************************************/ + +static void pthread_cleanup_pop_tcb(FAR struct pthread_tcb_s *tcb, int execute) +{ + if (tcb->tos > 0) + { + unsigned int ndx; + + /* Get the index to the last cleaner function pushed onto the stack */ + + ndx = tcb->tos - 1; + DEBUGASSERT(ndx < CONFIG_PTHREAD_CLEANUP_STACKSIZE); + + /* Should we execute the cleanup routine at the top of the stack? */ + + if (execute != 0) + { + FAR struct pthread_cleanup_s *cb; + + /* Yes.. Execute the clean-up routine. + * + * REVISIT: This is a security problem In the PROTECTED and KERNEL + * builds: We must not call the registered function in supervisor + * mode! See also on_exit() and atexit() callbacks. + */ + + cb = &tcb->stack[ndx]; + cb->pc_cleaner(cb->pc_arg); + } + + tcb->tos = ndx; + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pthread_cleanup_push + * pthread_cleanup_pop + * + * Description: + * The pthread_cleanup_pop() function will remove the routine at the top + * of the calling thread's cancellation cleanup stack and optionally + * invoke it (if 'execute' is non-zero). + * + * The pthread_cleanup_push() function will push the specified cancellation + * cleanup handler routine onto the calling thread's cancellation cleanup + * stack. The cancellation cleanup handler will be popped from the + * cancellation cleanup stack and invoked with the argument arg when: + * + * - The thread exits (that is, calls pthread_exit()). + * - The thread acts upon a cancellation request. + * - The thread calls pthread_cleanup_pop() with a non-zero execute argument. + * + * Input Parameters: + * routine - The cleanup routine to be pushed on the the cleanup stack. + * arg - An argument that will accompany the callback. + * execute - Execute the popped cleanup function immediately. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void pthread_cleanup_pop(int execute) +{ + FAR struct pthread_tcb_s *tcb = (FAR struct pthread_tcb_s *)this_task(); + irqstate_t flags; + + /* We don't assert if called from a non-pthread; we just don't do anything */ + + DEBUGASSERT(tcb != NULL); + + flags = enter_critical_section(); + if ((tcb->cmn.flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD) + { + pthread_cleanup_pop_tcb(tcb, execute); + } + + leave_critical_section(flags); +} + +void pthread_cleanup_push(pthread_cleanup_t routine, FAR void *arg) +{ + FAR struct pthread_tcb_s *tcb = (FAR struct pthread_tcb_s *)this_task(); + irqstate_t flags; + + /* We don't assert if called from a non-pthread; we just don't do anything */ + + DEBUGASSERT(tcb != NULL); + DEBUGASSERT(tcb->tos < CONFIG_PTHREAD_CLEANUP_STACKSIZE); + + flags = enter_critical_section(); + if ((tcb->cmn.flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD && + tcb->tos < CONFIG_PTHREAD_CLEANUP_STACKSIZE) + { + unsigned int ndx = tcb->tos; + + tcb->tos++; + tcb->stack[ndx].pc_cleaner = routine; + tcb->stack[ndx].pc_arg = arg; + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: pthread_cleanup_popall + * + * Description: + * The pthread_cleanup_popall() is an internal function that will pop and + * execute all clean-up functions. This function is only called from within + * the pthread_exit() and pthread_cancellation() logic + * + * Input Parameters: + * tcb - The TCB of the pthread that is exiting or being canceled. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void pthread_cleanup_popall(FAR struct pthread_tcb_s *tcb) +{ + irqstate_t flags; + + DEBUGASSERT(tcb != NULL); + DEBUGASSERT((tcb->cmn.flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD); + + /* Pop and execute each cleanup routine */ + + flags = enter_critical_section(); + while (tcb->tos > 0) + { + pthread_cleanup_pop_tcb(tcb, 1); + } + + leave_critical_section(flags); +} + +#endif /* CONFIG_PTHREAD_CLEANUP */ diff --git a/sched/pthread/pthread_exit.c b/sched/pthread/pthread_exit.c index 15b6240ee7..545148a4eb 100644 --- a/sched/pthread/pthread_exit.c +++ b/sched/pthread/pthread_exit.c @@ -80,6 +80,9 @@ void pthread_exit(FAR void *exit_value) sinfo("exit_value=%p\n", exit_value); + DEBUGASSERT(tcb != NULL); + DEBUGASSERT((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD); + /* Block any signal actions that would awaken us while were * are performing the JOIN handshake. */ @@ -91,6 +94,12 @@ void pthread_exit(FAR void *exit_value) } #endif +#ifdef CONFIG_PTHREAD_CLEANUP + /* Perform any stack pthread clean-up callbacks */ + + pthread_cleanup_popall((FAR struct pthread_tcb_s *)tcb); +#endif + /* Complete pending join operations */ status = pthread_completejoin(getpid(), exit_value); diff --git a/sched/task/task_exithook.c b/sched/task/task_exithook.c index 3f75ec7ca1..94ed2786a2 100644 --- a/sched/task/task_exithook.c +++ b/sched/task/task_exithook.c @@ -75,7 +75,8 @@ static inline void task_atexit(FAR struct tcb_s *tcb) * callbacks. * * REVISIT: This is a security problem In the PROTECTED and KERNEL builds: - * We must not call the registered function in supervisor mode! + * We must not call the registered function in supervisor mode! See also + * on_exit() and pthread_cleanup_pop() callbacks. */ if (group && group->tg_nmembers == 1) @@ -138,7 +139,8 @@ static inline void task_onexit(FAR struct tcb_s *tcb, int status) * callbacks. * * REVISIT: This is a security problem In the PROTECTED and KERNEL builds: - * We must not call the registered function in supervisor mode! + * We must not call the registered function in supervisor mode! See also + * atexit() and pthread_cleanup_pop() callbacks. */ if (group && group->tg_nmembers == 1) diff --git a/syscall/syscall.csv b/syscall/syscall.csv index 8ecf52854f..a28d0d01a6 100644 --- a/syscall/syscall.csv +++ b/syscall/syscall.csv @@ -64,6 +64,8 @@ "pthread_barrier_init","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_barrier_t*","FAR const pthread_barrierattr_t*","unsigned int" "pthread_barrier_wait","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_barrier_t*" "pthread_cancel","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_t" +"pthread_cleanup_pop","pthread.h","defined(CONFIG_PTHREAD_CLEANUP)","void","int" +"pthread_cleanup_push","pthread.h","defined(CONFIG_PTHREAD_CLEANUP)","void","pthread_cleanup_t","FAR void*" "pthread_cond_broadcast","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_cond_t*" "pthread_cond_destroy","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_cond_t*" "pthread_cond_init","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_cond_t*","FAR const pthread_condattr_t*" diff --git a/syscall/syscall_lookup.h b/syscall/syscall_lookup.h index 0c16b8ce1e..60f194fc20 100644 --- a/syscall/syscall_lookup.h +++ b/syscall/syscall_lookup.h @@ -304,6 +304,10 @@ SYSCALL_LOOKUP(up_assert, 2, STUB_up_assert) SYSCALL_LOOKUP(pthread_kill, 2, STUB_pthread_kill) SYSCALL_LOOKUP(pthread_sigmask, 3, STUB_pthread_sigmask) # endif +# ifdef CONFIG_PTHREAD_CLEANUP + SYSCALL_LOOKUP(pthread_cleanup_push, 2, STUB_pthread_cleanup_push) + SYSCALL_LOOKUP(pthread_cleanup_pop, 1, STUB_pthread_cleanup_pop) +# endif #endif /* The following are defined only if message queues are enabled */ diff --git a/syscall/syscall_stublookup.c b/syscall/syscall_stublookup.c index f655e0800d..2b7b1eafca 100644 --- a/syscall/syscall_stublookup.c +++ b/syscall/syscall_stublookup.c @@ -311,6 +311,10 @@ uintptr_t STUB_pthread_kill(int nbr, uintptr_t parm1, uintptr_t parm2); uintptr_t STUB_pthread_sigmask(int nbr, uintptr_t parm1, uintptr_t parm2, uintptr_t parm3); +uintptr_t STUB_pthread_cleanup_pop(int nbr, uintptr_t parm1); +uintptr_t STUB_pthread_cleanup_push(int nbr, uintptr_t parm1, + uintptr_t parm2); + /* The following are defined only if message queues are enabled */ uintptr_t STUB_mq_close(int nbr, uintptr_t parm1); -- GitLab From ab43681f15717d0add34a9e0d6766be36c94dfa5 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 8 Dec 2016 10:24:40 -0600 Subject: [PATCH 627/734] Update TODO and some comments. --- TODO | 41 ++++++++++++++++++++--- arch/arm/src/armv7-m/up_signal_dispatch.c | 12 ------- include/nuttx/sched.h | 3 +- sched/pthread/pthread_cancel.c | 11 ++++-- sched/task/task_exithook.c | 8 +++++ 5 files changed, 54 insertions(+), 21 deletions(-) diff --git a/TODO b/TODO index 9b8776acd0..b6658bb388 100644 --- a/TODO +++ b/TODO @@ -108,9 +108,30 @@ o Task/Scheduler (sched/) 2. They run in supervisor mode (if applicable), and 3. They do not obey any setup of PIC or address environments. Do they need to? + 4. In the case of task_delete() and pthread_cancel, these + callbacks will run on the thread of execution and address + context of the caller of task. That is very bad! The fix for all of these issues it to have the callbacks - run on the caller's thread (as with signal handlers). + run on the caller's thread as is currently done with + signal handlers. Signals are delivered differently in + PROTECTED and KERNEL modes: The deliver is involes a + signal handling trampoline function in the user address + space and two signal handlers: One to call the signal + handler trampoline in user mode (SYS_signal_handler) and + on in with the signal handler trampoline to return to + supervisor mode (SYS_signal_handler_return) + + The primary difference is in the location of the signal + handling trampoline: + + - In PROTECTED mode, there is on a single user space blob + with a header at the beginning of the block (at a well- + known location. There is a pointer to the signal handler + trampoline function in that header. + - In the KERNEL mode, a special process signal handler + trampoline is used at a well-known location in every + process address space (ARCH_DATA_RESERVE->ar_sigtramp). Status: Open Priority: Medium Low. This is an important change to some less important interfaces. For the average user, these @@ -145,16 +166,26 @@ o Task/Scheduler (sched/) Priority: Low Title: REMOVE TASK_DELETE - Description: Need to remove or fix task delete. This interface is non- + Description: Need to remove or fix task delete(). This interface is non- standard and not safe. Arbitrary deleting tasks can cause - serious problems such as memory leaks. Better to remove it - than to retain it as a latent bug. + serious problems such as memory leaks and resources like + semaphores left in bad states. + + Task/process exit callbacks registered via atexit() or + on_exit() will not work correctly with task_delete(): In + that case the callback would execute in the context the + caller of task_delete() cancel, not in the context of the + exiting task (or process). + + Better to remove task_delete() than to retain it as a latent + bug. Currently used within the OS and also part of the implementation of pthread_cancel() and task_restart() (which should also go for the same reasons). It is used in NxWM::CNxConsole to terminate console tasks and also in - apps/netutils/thttpd to kill CGI tasks that timeout. + apps/netutils/thttpd to kill CGI tasks that timeout. So not + so simple to remove. Status: Open Priority: Low and not easily removable. diff --git a/arch/arm/src/armv7-m/up_signal_dispatch.c b/arch/arm/src/armv7-m/up_signal_dispatch.c index 4a03a26b21..9ec7d15152 100644 --- a/arch/arm/src/armv7-m/up_signal_dispatch.c +++ b/arch/arm/src/armv7-m/up_signal_dispatch.c @@ -46,18 +46,6 @@ #if ((defined(CONFIG_BUILD_PROTECTED) && defined(__KERNEL__)) || \ defined(CONFIG_BUILD_KERNEL)) && !defined(CONFIG_DISABLE_SIGNALS) -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/include/nuttx/sched.h b/include/nuttx/sched.h index 81d72c6e60..1db8b70a24 100644 --- a/include/nuttx/sched.h +++ b/include/nuttx/sched.h @@ -323,10 +323,9 @@ struct child_status_s #endif /* struct pthread_cleanup_s ******************************************************/ - -#ifdef CONFIG_PTHREAD_CLEANUP /* This structure describes one element of the pthread cleanup stack */ +#ifdef CONFIG_PTHREAD_CLEANUP struct pthread_cleanup_s { pthread_cleanup_t pc_cleaner; /* Cleanup callback address */ diff --git a/sched/pthread/pthread_cancel.c b/sched/pthread/pthread_cancel.c index e651259bc0..fcaba69079 100644 --- a/sched/pthread/pthread_cancel.c +++ b/sched/pthread/pthread_cancel.c @@ -116,9 +116,16 @@ int pthread_cancel(pthread_t thread) } #ifdef CONFIG_PTHREAD_CLEANUP - /* Perform any stack pthread clean-up callbacks */ + /* Perform any stack pthread clean-up callbacks. + * + * REVISIT: In this case, the clean-up callback will execute on the + * thread of the caller of pthread cancel, not on the thread of + * the thread-to-be-canceled. Is that an issue? Presumably they + * are both within the same group and within the same process address + * space. + */ - pthread_cleanup_popall(tcb); + pthread_cleanup_popall(tcb); #endif /* Complete pending join operations */ diff --git a/sched/task/task_exithook.c b/sched/task/task_exithook.c index 94ed2786a2..96856d8792 100644 --- a/sched/task/task_exithook.c +++ b/sched/task/task_exithook.c @@ -77,6 +77,10 @@ static inline void task_atexit(FAR struct tcb_s *tcb) * REVISIT: This is a security problem In the PROTECTED and KERNEL builds: * We must not call the registered function in supervisor mode! See also * on_exit() and pthread_cleanup_pop() callbacks. + * + * REVISIT: In the case of task_delete(), the callback would execute in + * the context the caller of task_delete() cancel, not in the context of + * the exiting task (or process). */ if (group && group->tg_nmembers == 1) @@ -141,6 +145,10 @@ static inline void task_onexit(FAR struct tcb_s *tcb, int status) * REVISIT: This is a security problem In the PROTECTED and KERNEL builds: * We must not call the registered function in supervisor mode! See also * atexit() and pthread_cleanup_pop() callbacks. + * + * REVISIT: In the case of task_delete(), the callback would execute in + * he context the caller of task_delete() cancel, not in the context of + * the exiting task (or process). */ if (group && group->tg_nmembers == 1) -- GitLab From 2a2926473cfaac5d19c7e2a4746f4eeb0584ce03 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 8 Dec 2016 12:30:10 -0600 Subject: [PATCH 628/734] Update TODO list --- TODO | 33 ++++++++++++++++++++++++++++++--- 1 file changed, 30 insertions(+), 3 deletions(-) diff --git a/TODO b/TODO index b6658bb388..5441ac9bae 100644 --- a/TODO +++ b/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated December 17, 2016) +NuttX TODO List (Last updated December 8, 2016) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with @@ -113,7 +113,7 @@ o Task/Scheduler (sched/) context of the caller of task. That is very bad! The fix for all of these issues it to have the callbacks - run on the caller's thread as is currently done with + run on the caller's thread as is currently done with signal handlers. Signals are delivered differently in PROTECTED and KERNEL modes: The deliver is involes a signal handling trampoline function in the user address @@ -186,6 +186,12 @@ o Task/Scheduler (sched/) NxWM::CNxConsole to terminate console tasks and also in apps/netutils/thttpd to kill CGI tasks that timeout. So not so simple to remove. + + Option: Perhaps task_delete() should not do asynchronous + deletion but should rather do the same kind of + synchronization such as the pthread_cancellation points? + (see pthread_cancel() issues). + Status: Open Priority: Low and not easily removable. @@ -524,7 +530,28 @@ o pthreads (sched/pthreads) Title: CANCELLATION POINTS Description: pthread_cancel(): Should implement cancellation points and - pthread_testcancel() + pthread_testcancel(). + + Internal implementation perhaps as follows. See list of + functions that are cancellation points on OpenGroup.org. In + general: + + - Remove asynchronous cancellation. All cancellations must + pend. + - Check if the thread is within cancellation region, then + treat like a signal to wake up with -ECANCELED vs -EINTER + + For each function/cancellation point + + - Call enter_cancellation region() on entry. Checks for + pending cancellation and marks "within cancellation region" + in TCB flags. + - Will wake-up with -ECANCELED if cancellation occurs. + - Call leave_cancellation region() on exit. Checks for + pending cancellation and marks NOT "within cancellation region" + + Perhaps task_delete() should do the same kind of synchronization? + Status: Open. No changes are planned. Priority: Low, probably not that useful -- GitLab From 7d750e418718c193acd46cfce7ed1bd83894dde8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 8 Dec 2016 12:55:54 -0600 Subject: [PATCH 629/734] Fix some comments --- configs/bambino-200e/include/board.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/configs/bambino-200e/include/board.h b/configs/bambino-200e/include/board.h index d84320a8d3..9f33f9aea7 100644 --- a/configs/bambino-200e/include/board.h +++ b/configs/bambino-200e/include/board.h @@ -57,12 +57,11 @@ * here because the including C file may not have that file in its include * path. * - * The Xplorer board has four crystals on board: + * The Bambino-200e board has three crystals on board: * * Y1 - RTC 32.768 MHz oscillator input, - * Y2 - 24.576 MHz input to the UDA 1380 audio codec, - * Y3 - 12.000 MHz LPC43xx crystal oscillator input - * Y4 - 50 MHz input for Ethernet + * Y2 - 12.000 MHz LPC43xx crystal oscillator input + * Y3 - 25 MHz input for Ethernet KSZ8031 PHY */ #define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency (Y3) */ -- GitLab From a692a4cc46a194e0f7c39fc01586dba332d6c089 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 8 Dec 2016 13:34:18 -0600 Subject: [PATCH 630/734] Update TODO again --- TODO | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/TODO b/TODO index 5441ac9bae..72472dfb23 100644 --- a/TODO +++ b/TODO @@ -536,9 +536,18 @@ o pthreads (sched/pthreads) functions that are cancellation points on OpenGroup.org. In general: - - Remove asynchronous cancellation. All cancellations must - pend. - - Check if the thread is within cancellation region, then + - Two types of cancellation. DEFFERRED and ASYCNCHOOUS: + PTHREAD_CANCEL_DEFERRED: A cancellation request is deferred + until the thread next calls a function that is a cancellation + point. This is the default cancelability type for all + threads. + PTHREAD_CANCEL_ASYNCHRONOUS: The thread can be canceled at + any time + DEFERRED should be the default but currently only + asyncrhononous is supported by NuttX + - To implement DEFERRED mode: + All cancellations must pend. + Check if the thread is within cancellation region, then treat like a signal to wake up with -ECANCELED vs -EINTER For each function/cancellation point -- GitLab From c77bda47d717f81c25ee6f0639728ae7099e52c1 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Thu, 8 Dec 2016 20:31:56 +0000 Subject: [PATCH 631/734] BUGFIX:STM32F427 was rebooting. Over reached family. --- arch/arm/src/stm32/stm32f40xxx_rcc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/stm32/stm32f40xxx_rcc.c b/arch/arm/src/stm32/stm32f40xxx_rcc.c index abb44313c8..5e2ba73b1f 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f40xxx_rcc.c @@ -743,7 +743,8 @@ static void stm32_stdclockconfig(void) { } -#if defined(PWR_CSR_ODRDY) +#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F446) || \ + defined(CONFIG_STM32_STM32F469) /* Enable the Over-drive to extend the clock frequency to 180 Mhz */ -- GitLab From 6224e4753391e09ffeca9a58c7a8126b4fd63833 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 8 Dec 2016 14:33:02 -0600 Subject: [PATCH 632/734] pthread cleanup stack: Replace critical section with sched_lock/unlock(). The cleanup stack modification only needs to have the TCB stationary. The stack is never modified from interrupt level logic --- sched/Kconfig | 5 ++++- sched/pthread/pthread_cleanup.c | 37 +++++++++++++++++++++------------ 2 files changed, 28 insertions(+), 14 deletions(-) diff --git a/sched/Kconfig b/sched/Kconfig index 6f938bf45b..58078d10fa 100644 --- a/sched/Kconfig +++ b/sched/Kconfig @@ -553,7 +553,10 @@ config PTHREAD_CLEANUP_STACKSIZE ---help--- The maximum number of cleanup actions that may be pushed by pthread_clean_push(). This setting will increase the size of EVERY - pthread task control block by about 8 * CONFIG_PTHREAD_CLEANUP_STACKSIZE. + pthread task control block by about n * CONFIG_PTHREAD_CLEANUP_STACKSIZE + where n is the size of a pointer, 2* sizeof(uintptr_t), this would be + 8 for a CPU with 32-bit addressing and 4 for a CPU with 16-bit + addressing. endmenu # Pthread Options diff --git a/sched/pthread/pthread_cleanup.c b/sched/pthread/pthread_cleanup.c index 304d572f21..7310c08cb6 100644 --- a/sched/pthread/pthread_cleanup.c +++ b/sched/pthread/pthread_cleanup.c @@ -40,8 +40,8 @@ #include #include +#include -#include #include #include "sched/sched.h" @@ -78,7 +78,7 @@ static void pthread_cleanup_pop_tcb(FAR struct pthread_tcb_s *tcb, int execute) /* Get the index to the last cleaner function pushed onto the stack */ ndx = tcb->tos - 1; - DEBUGASSERT(ndx < CONFIG_PTHREAD_CLEANUP_STACKSIZE); + DEBUGASSERT(ndx >= 0 && ndx < CONFIG_PTHREAD_CLEANUP_STACKSIZE); /* Should we execute the cleanup routine at the top of the stack? */ @@ -136,32 +136,40 @@ static void pthread_cleanup_pop_tcb(FAR struct pthread_tcb_s *tcb, int execute) void pthread_cleanup_pop(int execute) { FAR struct pthread_tcb_s *tcb = (FAR struct pthread_tcb_s *)this_task(); - irqstate_t flags; /* We don't assert if called from a non-pthread; we just don't do anything */ DEBUGASSERT(tcb != NULL); - flags = enter_critical_section(); + /* sched_lock() should provide sufficient protection. We only need to + * have this TCB stationary; the pthread cleanup stack should never be + * modified by interrupt level logic. + */ + + sched_lock(); if ((tcb->cmn.flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD) { pthread_cleanup_pop_tcb(tcb, execute); } - leave_critical_section(flags); + sched_unlock(); } void pthread_cleanup_push(pthread_cleanup_t routine, FAR void *arg) { FAR struct pthread_tcb_s *tcb = (FAR struct pthread_tcb_s *)this_task(); - irqstate_t flags; /* We don't assert if called from a non-pthread; we just don't do anything */ DEBUGASSERT(tcb != NULL); DEBUGASSERT(tcb->tos < CONFIG_PTHREAD_CLEANUP_STACKSIZE); - flags = enter_critical_section(); + /* sched_lock() should provide sufficient protection. We only need to + * have this TCB stationary; the pthread cleanup stack should never be + * modified by interrupt level logic. + */ + + sched_lock(); if ((tcb->cmn.flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD && tcb->tos < CONFIG_PTHREAD_CLEANUP_STACKSIZE) { @@ -172,7 +180,7 @@ void pthread_cleanup_push(pthread_cleanup_t routine, FAR void *arg) tcb->stack[ndx].pc_arg = arg; } - leave_critical_section(flags); + sched_unlock(); } /**************************************************************************** @@ -193,20 +201,23 @@ void pthread_cleanup_push(pthread_cleanup_t routine, FAR void *arg) void pthread_cleanup_popall(FAR struct pthread_tcb_s *tcb) { - irqstate_t flags; - DEBUGASSERT(tcb != NULL); DEBUGASSERT((tcb->cmn.flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD); - /* Pop and execute each cleanup routine */ + /* Pop and execute each cleanup routine/ + * + * sched_lock() should provide sufficient protection. We only need to + * have this TCB stationary; the pthread cleanup stack should never be + * modified by interrupt level logic. + */ - flags = enter_critical_section(); + sched_lock(); while (tcb->tos > 0) { pthread_cleanup_pop_tcb(tcb, 1); } - leave_critical_section(flags); + sched_unlock(); } #endif /* CONFIG_PTHREAD_CLEANUP */ -- GitLab From dd309ad9e8a82f30ef94a65b00dac614ddeedc29 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Thu, 8 Dec 2016 21:14:31 +0000 Subject: [PATCH 633/734] I was wrong - the original commit was correct. Assume a write op on the last word: address of 0xxxxxfe and count of 2. It is a valid operation and address+count is == STM32_FLASH_SIZE - so that is OK --- arch/arm/src/stm32/stm32_flash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/stm32/stm32_flash.c b/arch/arm/src/stm32/stm32_flash.c index 56aa1f75ed..73f1419506 100644 --- a/arch/arm/src/stm32/stm32_flash.c +++ b/arch/arm/src/stm32/stm32_flash.c @@ -313,7 +313,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count) addr -= STM32_FLASH_BASE; } - if ((addr+count) >= STM32_FLASH_SIZE) + if ((addr+count) > STM32_FLASH_SIZE) { return -EFAULT; } -- GitLab From acaae12e8b8d8f0ab00735ac50e23221312aeb78 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 9 Dec 2016 07:23:00 -0600 Subject: [PATCH 634/734] Add pthread_testcancel(), pthread_testcancel(), and definitiions for cancellation types. --- include/nuttx/sched.h | 12 ++- include/pthread.h | 8 +- sched/Kconfig | 9 ++ sched/pthread/Make.defs | 3 +- sched/pthread/pthread_cleanup.c | 3 + sched/pthread/pthread_create.c | 6 ++ sched/pthread/pthread_setcancelstate.c | 47 +++++++-- sched/pthread/pthread_setcanceltype.c | 128 +++++++++++++++++++++++++ sched/pthread/pthread_testcancel.c | 66 +++++++++++++ sched/task/task_setup.c | 6 ++ 10 files changed, 274 insertions(+), 14 deletions(-) create mode 100644 sched/pthread/pthread_setcanceltype.c create mode 100644 sched/pthread/pthread_testcancel.c diff --git a/include/nuttx/sched.h b/include/nuttx/sched.h index 1db8b70a24..0eb9432973 100644 --- a/include/nuttx/sched.h +++ b/include/nuttx/sched.h @@ -141,16 +141,18 @@ # define TCB_FLAG_TTYPE_PTHREAD (1 << TCB_FLAG_TTYPE_SHIFT) /* User pthread */ # define TCB_FLAG_TTYPE_KERNEL (2 << TCB_FLAG_TTYPE_SHIFT) /* Kernel thread */ #define TCB_FLAG_NONCANCELABLE (1 << 2) /* Bit 2: Pthread is non-cancelable */ -#define TCB_FLAG_CANCEL_PENDING (1 << 3) /* Bit 3: Pthread cancel is pending */ -#define TCB_FLAG_POLICY_SHIFT (4) /* Bit 4-5: Scheduling policy */ +#define TCB_FLAG_CANCEL_DEFERRED (1 << 3) /* Bit 3: Deferred (vs asynch) cancellation type */ +#define TCB_FLAG_CANCEL_POINT (1 << 4) /* Bit 4: At a cancellation point */ +#define TCB_FLAG_CANCEL_PENDING (1 << 5) /* Bit 5: Pthread cancel is pending */ +#define TCB_FLAG_POLICY_SHIFT (6) /* Bit 6-7: Scheduling policy */ #define TCB_FLAG_POLICY_MASK (3 << TCB_FLAG_POLICY_SHIFT) # define TCB_FLAG_SCHED_FIFO (0 << TCB_FLAG_POLICY_SHIFT) /* FIFO scheding policy */ # define TCB_FLAG_SCHED_RR (1 << TCB_FLAG_POLICY_SHIFT) /* Round robin scheding policy */ # define TCB_FLAG_SCHED_SPORADIC (2 << TCB_FLAG_POLICY_SHIFT) /* Sporadic scheding policy */ # define TCB_FLAG_SCHED_OTHER (3 << TCB_FLAG_POLICY_SHIFT) /* Other scheding policy */ -#define TCB_FLAG_CPU_LOCKED (1 << 6) /* Bit 6: Locked to this CPU */ -#define TCB_FLAG_EXIT_PROCESSING (1 << 7) /* Bit 7: Exitting */ - /* Bits 8-15: Available */ +#define TCB_FLAG_CPU_LOCKED (1 << 8) /* Bit 8: Locked to this CPU */ +#define TCB_FLAG_EXIT_PROCESSING (1 << 9) /* Bit 9: Exitting */ + /* Bits 10-15: Available */ /* Values for struct task_group tg_flags */ diff --git a/include/pthread.h b/include/pthread.h index 28bb0add97..d943a843e2 100644 --- a/include/pthread.h +++ b/include/pthread.h @@ -115,11 +115,16 @@ #define PTHREAD_DEFAULT_PRIORITY 100 -/* Cancellation states returned by pthread_cancelstate() */ +/* Cancellation states used by pthread_setcancelstate() */ #define PTHREAD_CANCEL_ENABLE (0) #define PTHREAD_CANCEL_DISABLE (1) +/* Cancellation types used by pthread_setcanceltype() */ + +#define PTHREAD_CANCEL_DEFERRED (0) +#define PTHREAD_CANCEL_ASYNCHRONOUS (1) + /* Thread return value when a pthread is canceled */ #define PTHREAD_CANCELED ((FAR void*)ERROR) @@ -340,6 +345,7 @@ int pthread_detach(pthread_t thread); void pthread_exit(pthread_addr_t value) noreturn_function; int pthread_cancel(pthread_t thread); int pthread_setcancelstate(int state, FAR int *oldstate); +int pthread_setcanceltype(int type, FAR int *oldtype); void pthread_testcancel(void); /* A thread may set up cleanup functions to execut when the thread exits or diff --git a/sched/Kconfig b/sched/Kconfig index 58078d10fa..d3d9230d6e 100644 --- a/sched/Kconfig +++ b/sched/Kconfig @@ -560,6 +560,15 @@ config PTHREAD_CLEANUP_STACKSIZE endmenu # Pthread Options +config CANCELLATION_POINTS + bool "Cancellation points" + default n + depends on EXPERIMENTAL + ---help--- + Enable POSIX cancellation points for pthread_cancel(). If selected, + cancellation points will also used with the () task_delete() API even if + pthreads are not enabled. + menu "Performance Monitoring" config SCHED_CPULOAD diff --git a/sched/pthread/Make.defs b/sched/pthread/Make.defs index a08315c732..f589f3dfef 100644 --- a/sched/pthread/Make.defs +++ b/sched/pthread/Make.defs @@ -42,7 +42,8 @@ CSRCS += pthread_mutexlock.c pthread_mutextrylock.c pthread_mutexunlock.c CSRCS += pthread_condinit.c pthread_conddestroy.c CSRCS += pthread_condwait.c pthread_condsignal.c pthread_condbroadcast.c CSRCS += pthread_barrierinit.c pthread_barrierdestroy.c pthread_barrierwait.c -CSRCS += pthread_cancel.c pthread_setcancelstate.c +CSRCS += pthread_cancel.c pthread_setcancelstate.c pthread_setcanceltype.c +CSRCS += pthread_testcancel.c CSRCS += pthread_keycreate.c pthread_setspecific.c pthread_getspecific.c pthread_keydelete.c CSRCS += pthread_initialize.c pthread_completejoin.c pthread_findjoininfo.c CSRCS += pthread_once.c pthread_release.c pthread_setschedprio.c diff --git a/sched/pthread/pthread_cleanup.c b/sched/pthread/pthread_cleanup.c index 7310c08cb6..6c71cd8c13 100644 --- a/sched/pthread/pthread_cleanup.c +++ b/sched/pthread/pthread_cleanup.c @@ -67,6 +67,9 @@ * Return Value: * None * + * Assumptions: + * The scheduler is locked. + * ****************************************************************************/ static void pthread_cleanup_pop_tcb(FAR struct pthread_tcb_s *tcb, int execute) diff --git a/sched/pthread/pthread_create.c b/sched/pthread/pthread_create.c index 6efc9aa21a..7a4e628e00 100644 --- a/sched/pthread/pthread_create.c +++ b/sched/pthread/pthread_create.c @@ -483,6 +483,12 @@ int pthread_create(FAR pthread_t *thread, FAR const pthread_attr_t *attr, #endif } +#ifdef CONFIG_CANCELLATION_POINTS + /* Set the deferred cancellation type */ + + ptcb->cmn.flags |= TCB_FLAG_CANCEL_DEFERRED; +#endif + /* Get the assigned pid before we start the task (who knows what * could happen to ptcb after this!). Copy this ID into the join structure * as well. diff --git a/sched/pthread/pthread_setcancelstate.c b/sched/pthread/pthread_setcancelstate.c index b9aab9a7d1..4c457766fa 100644 --- a/sched/pthread/pthread_setcancelstate.c +++ b/sched/pthread/pthread_setcancelstate.c @@ -47,6 +47,18 @@ /**************************************************************************** * Name: pthread_setcancelstate + * + * Description: + * The pthread_setcancelstate() function atomically both sets the calling + * thread's cancelability state to the indicated state and returns the + * previous cancelability state at the location referenced by oldstate. + * Legal values for state are PTHREAD_CANCEL_ENABLE and + * PTHREAD_CANCEL_DISABLE. + * + * The cancelability state and type of any newly created threads, + * including the thread in which main() was first invoked, are + * PTHREAD_CANCEL_ENABLE and PTHREAD_CANCEL_DEFERRED respectively. + * ****************************************************************************/ int pthread_setcancelstate(int state, FAR int *oldstate) @@ -78,17 +90,38 @@ int pthread_setcancelstate(int state, FAR int *oldstate) if (state == PTHREAD_CANCEL_ENABLE) { - unsigned flags = tcb->flags; - - /* Clear the non-cancelable and cancel pending flags */ + /* Clear the non-cancelable flag */ - tcb->flags &= ~(TCB_FLAG_NONCANCELABLE | TCB_FLAG_CANCEL_PENDING); + tcb->flags &= ~TCB_FLAG_NONCANCELABLE; - /* If the cancel was pending, then just exit as requested */ + /* Check if a cancellation was pending */ - if (flags & TCB_FLAG_CANCEL_PENDING) + if ((tcb->flags & TCB_FLAG_CANCEL_PENDING) != 0) { - pthread_exit(PTHREAD_CANCELED); +#ifdef CONFIG_CANCELLATION_POINTS + /* If we are using deferred cancellation? */ + + if ((tcb->flags & TCB_FLAG_CANCEL_DEFERRED) != 0) + { + /* Yes.. If we are within a cancellation point, then + * notify of the cancellation. + */ + + if (tcb->flags & TCB_FLAG_CANCEL_POINT) != 0) + { +# warning Missing logic + } + } + else +#endif + { + /* No.. We are using asynchronous cancellation. If the + * cancellation was pending in this case, then just exit. + */ + + tcb->flags &= ~TCB_FLAG_CANCEL_PENDING; + pthread_exit(PTHREAD_CANCELED); + } } } else if (state == PTHREAD_CANCEL_DISABLE) diff --git a/sched/pthread/pthread_setcanceltype.c b/sched/pthread/pthread_setcanceltype.c new file mode 100644 index 0000000000..ca88ea3ddb --- /dev/null +++ b/sched/pthread/pthread_setcanceltype.c @@ -0,0 +1,128 @@ +/**************************************************************************** + * sched/pthread/pthread_setcanceltype.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "sched/sched.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pthread_setcancelstate + * + * Description: + * The pthread_setcanceltype() function atomically both sets the calling + * thread's cancelability type to the indicated type and returns the + * previous cancelability type at the location referenced by oldtype + * Legal values for type are PTHREAD_CANCEL_DEFERRED and + * PTHREAD_CANCEL_ASYNCHRONOUS. + * + * The cancelability state and type of any newly created threads, + * including the thread in which main() was first invoked, are + * PTHREAD_CANCEL_ASYNCHRONOUS and PTHREAD_CANCEL_DEFERRED respectively. + * + ****************************************************************************/ + +int pthread_setcanceltype(int type, FAR int *oldtype) +{ + FAR struct tcb_s *tcb = this_task(); + int ret = OK; + + /* Suppress context changes for a bit so that the flags are stable. (the + * flags should not change in interrupt handling). + */ + + sched_lock(); + + /* Return the current type if so requrested */ + + if (oldtype) + { + if ((tcb->flags & TCB_FLAG_CANCEL_DEFERRED) != 0) + { + *oldtype = PTHREAD_CANCEL_DEFERRED; + } + else + { + *oldtype = PTHREAD_CANCEL_ASYNCHRONOUS; + } + } + + /* Set the new cancellation type */ + + if (type == PTHREAD_CANCEL_ASYNCHRONOUS) + { + /* Clear the deferred cancellation bit */ + + tcb->flags &= ~TCB_FLAG_CANCEL_DEFERRED; + +#ifdef CONFIG_CANCELLATION_POINTS + /* If we just switched from deferred to asynchronous type and if a + * cancellation is pending, then exit now. + */ + + if ((tcb->flags & TCB_FLAG_CANCEL_PENDING) != 0 && + (tcb->flags & TCB_FLAG_NONCANCELABLE) == 0) + { + tcb->flags &= ~TCB_FLAG_CANCEL_PENDING; + pthread_exit(PTHREAD_CANCELED); + } +#endif + } +#ifdef CONFIG_CANCELLATION_POINTS + else if (type == PTHREAD_CANCEL_DEFERRED) + { + /* Set the deferred cancellation type */ + + tcb->flags |= TCB_FLAG_CANCEL_DEFERRED; + } +#endif + else + { + ret = EINVAL; + } + + sched_unlock(); + return ret; +} diff --git a/sched/pthread/pthread_testcancel.c b/sched/pthread/pthread_testcancel.c new file mode 100644 index 0000000000..0e6186dec2 --- /dev/null +++ b/sched/pthread/pthread_testcancel.c @@ -0,0 +1,66 @@ +/**************************************************************************** + * sched/pthread/pthread_testcancel.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "sched/sched.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pthread_testcancel + * + * Description: + * The pthread_testcancel() function creates a cancellation point in the + * calling thread. The pthread_testcancel() function has no effect if + * cancelability is disabled + * + ****************************************************************************/ + +void pthread_testcancel(void) +{ +#ifdef CONFIG_CANCELLATION_POINTS +# warning Missing Logic +#endif +} diff --git a/sched/task/task_setup.c b/sched/task/task_setup.c index 7b8b086434..19736f86ab 100644 --- a/sched/task/task_setup.c +++ b/sched/task/task_setup.c @@ -378,6 +378,12 @@ static int thread_schedsetup(FAR struct tcb_s *tcb, int priority, tcb->flags &= ~TCB_FLAG_TTYPE_MASK; tcb->flags |= ttype; +#ifdef CONFIG_CANCELLATION_POINTS + /* Set the deferred cancellation type */ + + tcb->flags |= TCB_FLAG_CANCEL_DEFERRED; +#endif + /* Save the task ID of the parent task in the TCB and allocate * a child status structure. */ -- GitLab From 82a79b9c1b56a54a2b4b5175f1c4eb46650a3476 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 9 Dec 2016 08:13:28 -0600 Subject: [PATCH 635/734] Add framework for cancellation point support. --- include/nuttx/pthread.h | 68 +++++++++++- sched/pthread/Make.defs | 3 +- sched/pthread/pthread_setcancelstate.c | 8 +- sched/task/Make.defs | 4 + sched/task/task.h | 6 ++ sched/task/task_cancelpt.c | 144 +++++++++++++++++++++++++ 6 files changed, 229 insertions(+), 4 deletions(-) create mode 100644 sched/task/task_cancelpt.c diff --git a/include/nuttx/pthread.h b/include/nuttx/pthread.h index 54d5dc659b..2625e40d53 100644 --- a/include/nuttx/pthread.h +++ b/include/nuttx/pthread.h @@ -2,7 +2,7 @@ * include/nuttx/pthread.h * Non-standard, NuttX-specific pthread-related declarations. * - * Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -127,6 +127,72 @@ EXTERN const pthread_attr_t g_default_pthread_attr; * Public Function Prototypes ****************************************************************************/ +/**************************************************************************** + * Cancellation Points. + * + * Cancellation points shall occur when a thread is executing the following + * functions: + * + * accept() mq_timedsend() putpmsg() sigtimedwait() + * aio_suspend() msgrcv() pwrite() sigwait() + * clock_nanosleep() msgsnd() read() sigwaitinfo() + * close() msync() readv() sleep() + * connect() nanosleep() recv() system() + * creat() open() recvfrom() tcdrain() + * fcntl() pause() recvmsg() usleep() + * fdatasync() poll() select() wait() + * fsync() pread() sem_timedwait() waitid() + * getmsg() pselect() sem_wait() waitpid() + * getpmsg() pthread_cond_timedwait() send() write() + * lockf() pthread_cond_wait() sendmsg() writev() + * mq_receive() pthread_join() sendto() + * mq_send() pthread_testcancel() sigpause() + * mq_timedreceive() putmsg() sigsuspend() + * + * Each of the above function must call enter_cancellation_point() on entry + * in order to establish the cancellation point and leave_cancellation_point() + * on exit. These functions are described below. + * + ****************************************************************************/ + +/**************************************************************************** + * Name: enter_cancellation_point + * + * Description: + * Called at the beginning of the cancellation point to establish the + * cancellation point. This function does the following: + * + * 1. If deferred cancellation does not apply to this thread, nothing is + * done, otherwise, it + * 2. Sets state information in the caller's TCB and increments a nesting + * count. + * 3. If this is the outermost nesting level, it checks if there is a + * pending cancellation and, if so, calls either exit() or + * pthread_exit(), depending upon the type of the + * + ****************************************************************************/ + +void leave_cancellation_point(void); + +/**************************************************************************** + * Name: enter_cancellation_point + * + * Description: + * Called at the end of the cancellation point. This function does the + * following: + * + * 1. If deferred cancellation does not apply to this thread, nothing is + * done, otherwise, it + * 2. Clears state information in the caller's TCB and decrements a + * nesting count. + * 3. If this is the outermost nesting level, it checks if there is a + * pending cancellation and, if so, calls either exit() or + * pthread_exit(), depending upon the type of the + * + ****************************************************************************/ + +void enter_cancellation_point(void); + #undef EXTERN #ifdef __cplusplus } diff --git a/sched/pthread/Make.defs b/sched/pthread/Make.defs index f589f3dfef..0ed862edf0 100644 --- a/sched/pthread/Make.defs +++ b/sched/pthread/Make.defs @@ -44,7 +44,8 @@ CSRCS += pthread_condwait.c pthread_condsignal.c pthread_condbroadcast.c CSRCS += pthread_barrierinit.c pthread_barrierdestroy.c pthread_barrierwait.c CSRCS += pthread_cancel.c pthread_setcancelstate.c pthread_setcanceltype.c CSRCS += pthread_testcancel.c -CSRCS += pthread_keycreate.c pthread_setspecific.c pthread_getspecific.c pthread_keydelete.c +CSRCS += pthread_keycreate.c pthread_setspecific.c pthread_getspecific.c +CSRCS += pthread_keydelete.c CSRCS += pthread_initialize.c pthread_completejoin.c pthread_findjoininfo.c CSRCS += pthread_once.c pthread_release.c pthread_setschedprio.c diff --git a/sched/pthread/pthread_setcancelstate.c b/sched/pthread/pthread_setcancelstate.c index 4c457766fa..d536842157 100644 --- a/sched/pthread/pthread_setcancelstate.c +++ b/sched/pthread/pthread_setcancelstate.c @@ -37,8 +37,12 @@ * Included Files ****************************************************************************/ +#include + #include #include + +#include "task/task.h" #include "sched/sched.h" /**************************************************************************** @@ -107,9 +111,9 @@ int pthread_setcancelstate(int state, FAR int *oldstate) * notify of the cancellation. */ - if (tcb->flags & TCB_FLAG_CANCEL_POINT) != 0) + if ((tcb->flags & TCB_FLAG_CANCEL_POINT) != 0) { -# warning Missing logic + notify_cancellation(); } } else diff --git a/sched/task/Make.defs b/sched/task/Make.defs index ddf3e972b7..e173a8b246 100644 --- a/sched/task/Make.defs +++ b/sched/task/Make.defs @@ -66,6 +66,10 @@ ifeq ($(CONFIG_SCHED_ONEXIT),y) CSRCS += task_onexit.c endif +ifeq ($(CONFIG_CANCELLATION_POINTS),y) +CSRCS += task_cancelpt.c +endif + # Include task build support DEPPATH += --dep-path task diff --git a/sched/task/task.h b/sched/task/task.h index e81f0eaefc..2abcf4a74d 100644 --- a/sched/task/task.h +++ b/sched/task/task.h @@ -80,4 +80,10 @@ int task_terminate(pid_t pid, bool nonblocking); void task_exithook(FAR struct tcb_s *tcb, int status, bool nonblocking); void task_recover(FAR struct tcb_s *tcb); +/* Cancellation points */ + +#ifdef CONFIG_CANCELLATION_POINTS +void notify_cancellation(void); +#endif + #endif /* __SCHED_TASK_TASK_H */ diff --git a/sched/task/task_cancelpt.c b/sched/task/task_cancelpt.c new file mode 100644 index 0000000000..2e294000d6 --- /dev/null +++ b/sched/task/task_cancelpt.c @@ -0,0 +1,144 @@ +/**************************************************************************** + * sched/task/task_cancelpt.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Cancellation Points. + * + * Cancellation points shall occur when a thread is executing the following + * functions: + * + * accept() mq_timedsend() putpmsg() sigtimedwait() + * aio_suspend() msgrcv() pwrite() sigwait() + * clock_nanosleep() msgsnd() read() sigwaitinfo() + * close() msync() readv() sleep() + * connect() nanosleep() recv() system() + * creat() open() recvfrom() tcdrain() + * fcntl() pause() recvmsg() usleep() + * fdatasync() poll() select() wait() + * fsync() pread() sem_timedwait() waitid() + * getmsg() pselect() sem_wait() waitpid() + * getpmsg() pthread_cond_timedwait() send() write() + * lockf() pthread_cond_wait() sendmsg() writev() + * mq_receive() pthread_join() sendto() + * mq_send() pthread_testcancel() sigpause() + * mq_timedreceive() putmsg() sigsuspend() + * + * Each of the above function must call enter_cancellation_point() on entry + * in order to establish the cancellation point and leave_cancellation_point() + * on exit. These functions are described below. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "task/task.h" + +#ifdef CONFIG_CANCELLATION_POINTS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: enter_cancellation_point + * + * Description: + * Called at the beginning of the cancellation point to establish the + * cancellation point. This function does the following: + * + * 1. If deferred cancellation does not apply to this thread, nothing is + * done, otherwise, it + * 2. Sets state information in the caller's TCB and increments a nesting + * count. + * 3. If this is the outermost nesting level, it checks if there is a + * pending cancellation and, if so, calls either exit() or + * pthread_exit(), depending upon the type of the + * + ****************************************************************************/ + +void leave_cancellation_point(void) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: enter_cancellation_point + * + * Description: + * Called at the end of the cancellation point. This function does the + * following: + * + * 1. If deferred cancellation does not apply to this thread, nothing is + * done, otherwise, it + * 2. Clears state information in the caller's TCB and decrements a + * nesting count. + * 3. If this is the outermost nesting level, it checks if there is a + * pending cancellation and, if so, calls either exit() or + * pthread_exit(), depending upon the type of the + * + ****************************************************************************/ + +void enter_cancellation_point(void) +{ +#warning Missing logic +} + +/**************************************************************************** + * Name: notify_cancellation + * + * Description: + * Called by task_delete() or pthread_cancel() if the cancellation occurs + * while we the thread is within the cancellation point. This logic + * behaves much like sending a signal: It will cause waiting threads + * to wake up and terminated with ECANCELED. A call to + * leave_cancellation_point() whould then follow, causing the thread to + * exit. + * + ****************************************************************************/ + +void notify_cancellation(void) +{ +#warning Missing logic +} + +#endif /* CONFIG_CANCELLATION_POINTS */ -- GitLab From df9c5b33a01cac9da1786ede3903c575861cc769 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Fri, 9 Dec 2016 05:02:31 -1000 Subject: [PATCH 636/734] Added STM32F469 RAM size and deliberated STM32F446 size --- arch/arm/src/stm32/stm32_allocateheap.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/stm32/stm32_allocateheap.c b/arch/arm/src/stm32/stm32_allocateheap.c index a222253af5..c77f81b4a3 100644 --- a/arch/arm/src/stm32/stm32_allocateheap.c +++ b/arch/arm/src/stm32/stm32_allocateheap.c @@ -295,10 +295,13 @@ # define SRAM1_END 0x20018000 # elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) # define SRAM1_END 0x20030000 +# elif defined(CONFIG_STM32_STM32F446) +# define SRAM1_END 0x20020000 +# elif defined(CONFIG_STM32_STM32F469) +# define SRAM1_END 0x20050000 # else # define SRAM1_END 0x20020000 # endif - /* Set the range of CCM SRAM as well (although we may not use it) */ # define SRAM2_START 0x10000000 -- GitLab From d35e589d567677098a85503c12cb99154f38a266 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 9 Dec 2016 09:44:23 -0600 Subject: [PATCH 637/734] Flesh basic cancellation point support --- include/nuttx/pthread.h | 18 ++- include/nuttx/sched.h | 14 +- sched/pthread/pthread_setcancelstate.c | 4 +- sched/task/task.h | 2 +- sched/task/task_cancelpt.c | 171 +++++++++++++++++++++++-- 5 files changed, 186 insertions(+), 23 deletions(-) diff --git a/include/nuttx/pthread.h b/include/nuttx/pthread.h index 2625e40d53..e4698ae741 100644 --- a/include/nuttx/pthread.h +++ b/include/nuttx/pthread.h @@ -168,14 +168,18 @@ EXTERN const pthread_attr_t g_default_pthread_attr; * count. * 3. If this is the outermost nesting level, it checks if there is a * pending cancellation and, if so, calls either exit() or - * pthread_exit(), depending upon the type of the + * pthread_exit(), depending upon the type of the thread. * ****************************************************************************/ -void leave_cancellation_point(void); +#ifdef CONFIG_CANCELLATION_POINTS +void enter_cancellation_point(void); +#else +# define enter_cancellation_point() +#endif /**************************************************************************** - * Name: enter_cancellation_point + * Name: leave_cancellation_point * * Description: * Called at the end of the cancellation point. This function does the @@ -187,11 +191,15 @@ void leave_cancellation_point(void); * nesting count. * 3. If this is the outermost nesting level, it checks if there is a * pending cancellation and, if so, calls either exit() or - * pthread_exit(), depending upon the type of the + * pthread_exit(), depending upon the type of the thread. * ****************************************************************************/ -void enter_cancellation_point(void); +#ifdef CONFIG_CANCELLATION_POINTS +void leave_cancellation_point(void); +#else +# define leave_cancellation_point() +#endif #undef EXTERN #ifdef __cplusplus diff --git a/include/nuttx/sched.h b/include/nuttx/sched.h index 0eb9432973..687d19dcf9 100644 --- a/include/nuttx/sched.h +++ b/include/nuttx/sched.h @@ -142,17 +142,16 @@ # define TCB_FLAG_TTYPE_KERNEL (2 << TCB_FLAG_TTYPE_SHIFT) /* Kernel thread */ #define TCB_FLAG_NONCANCELABLE (1 << 2) /* Bit 2: Pthread is non-cancelable */ #define TCB_FLAG_CANCEL_DEFERRED (1 << 3) /* Bit 3: Deferred (vs asynch) cancellation type */ -#define TCB_FLAG_CANCEL_POINT (1 << 4) /* Bit 4: At a cancellation point */ -#define TCB_FLAG_CANCEL_PENDING (1 << 5) /* Bit 5: Pthread cancel is pending */ -#define TCB_FLAG_POLICY_SHIFT (6) /* Bit 6-7: Scheduling policy */ +#define TCB_FLAG_CANCEL_PENDING (1 << 4) /* Bit 4: Pthread cancel is pending */ +#define TCB_FLAG_POLICY_SHIFT (5) /* Bit 5-6: Scheduling policy */ #define TCB_FLAG_POLICY_MASK (3 << TCB_FLAG_POLICY_SHIFT) # define TCB_FLAG_SCHED_FIFO (0 << TCB_FLAG_POLICY_SHIFT) /* FIFO scheding policy */ # define TCB_FLAG_SCHED_RR (1 << TCB_FLAG_POLICY_SHIFT) /* Round robin scheding policy */ # define TCB_FLAG_SCHED_SPORADIC (2 << TCB_FLAG_POLICY_SHIFT) /* Sporadic scheding policy */ # define TCB_FLAG_SCHED_OTHER (3 << TCB_FLAG_POLICY_SHIFT) /* Other scheding policy */ -#define TCB_FLAG_CPU_LOCKED (1 << 8) /* Bit 8: Locked to this CPU */ -#define TCB_FLAG_EXIT_PROCESSING (1 << 9) /* Bit 9: Exitting */ - /* Bits 10-15: Available */ +#define TCB_FLAG_CPU_LOCKED (1 << 7) /* Bit 7: Locked to this CPU */ +#define TCB_FLAG_EXIT_PROCESSING (1 << 8) /* Bit 8: Exitting */ + /* Bits 9-15: Available */ /* Values for struct task_group tg_flags */ @@ -584,6 +583,9 @@ struct tcb_s #ifdef CONFIG_SMP int16_t irqcount; /* 0=interrupts enabled */ #endif +#ifdef CONFIG_CANCELLATION_POINTS + int16_t cpcount; /* Nested cancellation point count */ +#endif #if CONFIG_RR_INTERVAL > 0 || defined(CONFIG_SCHED_SPORADIC) int32_t timeslice; /* RR timeslice OR Sporadic budget */ diff --git a/sched/pthread/pthread_setcancelstate.c b/sched/pthread/pthread_setcancelstate.c index d536842157..44c05fba9a 100644 --- a/sched/pthread/pthread_setcancelstate.c +++ b/sched/pthread/pthread_setcancelstate.c @@ -111,9 +111,9 @@ int pthread_setcancelstate(int state, FAR int *oldstate) * notify of the cancellation. */ - if ((tcb->flags & TCB_FLAG_CANCEL_POINT) != 0) + if (tcb->cpcount > 0) { - notify_cancellation(); + notify_cancellation(tcb); } } else diff --git a/sched/task/task.h b/sched/task/task.h index 2abcf4a74d..83ce71d3f5 100644 --- a/sched/task/task.h +++ b/sched/task/task.h @@ -83,7 +83,7 @@ void task_recover(FAR struct tcb_s *tcb); /* Cancellation points */ #ifdef CONFIG_CANCELLATION_POINTS -void notify_cancellation(void); +void notify_cancellation(FAR struct tcb_s *tcb); #endif #endif /* __SCHED_TASK_TASK_H */ diff --git a/sched/task/task_cancelpt.c b/sched/task/task_cancelpt.c index 2e294000d6..162bbc139c 100644 --- a/sched/task/task_cancelpt.c +++ b/sched/task/task_cancelpt.c @@ -68,9 +68,14 @@ #include #include +#include +#include #include +#include "sched/sched.h" +#include "semaphore/semaphore.h" +#include "mqueue/mqueue.h" #include "task/task.h" #ifdef CONFIG_CANCELLATION_POINTS @@ -92,17 +97,67 @@ * count. * 3. If this is the outermost nesting level, it checks if there is a * pending cancellation and, if so, calls either exit() or - * pthread_exit(), depending upon the type of the + * pthread_exit(), depending upon the type of the thread. * ****************************************************************************/ -void leave_cancellation_point(void) +void enter_cancellation_point(void) { -#warning Missing logic + FAR struct tcb_s *tcb = this_task(); + + /* Disabling pre-emption should provide sufficient protection. We only + * need the TCB to be stationary (no interrupt level modification is + * anticipated). + */ + + sched_lock(); + + /* If cancellation is disabled on this thread or if this thread is using + * asynchronous cancellation, then do nothing. + * + * Special case: if the cpcount count is greater than zero, then we are + * nested and the above condition was certainly true at the outermost + * nesting level. + */ + + if (((tcb->flags & TCB_FLAG_NONCANCELABLE) == 0 && + (tcb->flags & TCB_FLAG_CANCEL_DEFERRED) != 0) || + tcb->cpcount > 0) + { + /* If there is a pending cancellation and we are at the outermost + * nesting level of cancellation function calls, then just exit + * according to the type of the thread. + */ + + if ((tcb->flags & TCB_FLAG_CANCEL_PENDING) != 0 && + tcb->cpcount == 0) + { +#ifndef CONFIG_DISABLE_PTHREAD + if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD) + { + pthread_exit(NULL); + } + else +#endif + { + exit(EXIT_FAILURE); + } + } + + /* Otherwise, indicate that we are at a cancellation point by + * incrementing the nesting level of the cancellation point + * functions. + */ + + DEBUGASSERT(tcb->cpcount < INT16_MAX); + tcb->cpcount++; + } + + sched_unlock(); } /**************************************************************************** - * Name: enter_cancellation_point + * Name: leave_cancellation_point * * Description: * Called at the end of the cancellation point. This function does the @@ -114,13 +169,68 @@ void leave_cancellation_point(void) * nesting count. * 3. If this is the outermost nesting level, it checks if there is a * pending cancellation and, if so, calls either exit() or - * pthread_exit(), depending upon the type of the + * pthread_exit(), depending upon the type of the thread. * ****************************************************************************/ -void enter_cancellation_point(void) +void leave_cancellation_point(void) { -#warning Missing logic + FAR struct tcb_s *tcb = this_task(); + + /* Disabling pre-emption should provide sufficient protection. We only + * need the TCB to be stationary (no interrupt level modification is + * anticipated). + */ + + sched_lock(); + + /* If cancellation is disabled on this thread or if this thread is using + * asynchronous cancellation, then do nothing. Here we check only the + * nesting level: if the cpcount count is greater than zero, then the + * required condition was certainly true at the outermost nesting level. + */ + + if (tcb->cpcount > 0) + { + /* Decrement the nesting level. If if would decrement to zero, then + * we are at the outermost nesting level and may need to do more. + */ + + if (tcb->cpcount == 1) + { + /* We are no longer at the cancellation point */ + + tcb->cpcount = 0; + + /* If there is a pending cancellation then just exit according to + * the type of the thread. + */ + + if ((tcb->flags & TCB_FLAG_CANCEL_PENDING) != 0) + { +#ifndef CONFIG_DISABLE_PTHREAD + if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD) + { + pthread_exit(NULL); + } + else +#endif + { + exit(EXIT_FAILURE); + } + } + } + else + { + /* We are not at the outermost nesting level. Just decrment the + * nesting level count. + */ + + tcb->cpcount--; + } + } + + sched_unlock(); } /**************************************************************************** @@ -136,9 +246,52 @@ void enter_cancellation_point(void) * ****************************************************************************/ -void notify_cancellation(void) +void notify_cancellation(FAR struct tcb_s *tcb) { -#warning Missing logic + irqstate_t flags; + + /* We need perform the following operations from within a critical section + * because it can compete with interrupt level activity. + */ + + flags = enter_critical_section(); + + /* Make sure that the cancellation pending indication is set. */ + + tcb->flags |= TCB_FLAG_CANCEL_PENDING; + + /* We only notify the cancellation if (1) the thread has not disabled + * cancellation, (2) the thread uses the deffered cancellation mode, + * (3) the thread is waiting within a cancellation point. + */ + + if (((tcb->flags & TCB_FLAG_NONCANCELABLE) == 0 && + (tcb->flags & TCB_FLAG_CANCEL_DEFERRED) != 0) || + tcb->cpcount > 0) + { + /* If the thread is blocked waiting for a semaphore, then the thread + * must be unblocked to handle the cancellation. + */ + + if (tcb->task_state == TSTATE_WAIT_SEM) + { + sem_waitirq(tcb, ECANCELED); + } + + /* If the thread is blocked waiting on a message queue, then the + * thread must be unblocked to handle the cancellation. + */ + +#ifndef CONFIG_DISABLE_MQUEUE + if (tcb->task_state == TSTATE_WAIT_MQNOTEMPTY || + tcb->task_state == TSTATE_WAIT_MQNOTFULL) + { + mq_waitirq(tcb, ECANCELED); + } +#endif + } + + leave_critical_section(flags); } #endif /* CONFIG_CANCELLATION_POINTS */ -- GitLab From e7597d1754ae1c06f7e7241145076b227a0e320a Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Fri, 9 Dec 2016 15:53:58 +0000 Subject: [PATCH 638/734] Typo in stm32f76xx77xx_pinmap.h edited online with Bitbucket --- arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h index 6054d70242..c5d1b50a16 100644 --- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h @@ -997,7 +997,7 @@ #define GPIO_SPI2_SCK_3 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN13) #define GPIO_SPI2_SCK_4 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN3) #define GPIO_SPI2_SCK_5 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN1) -#define GPIO_SPI2_SCK_6 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTIA|GPIO_PIN12) +#define GPIO_SPI2_SCK_6 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN12) #define GPIO_SPI3_MISO_1 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4) #define GPIO_SPI3_MISO_2 (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN11) -- GitLab From 018db8456734f23ce3563e475176bee90a419b83 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 9 Dec 2016 10:31:40 -0600 Subject: [PATCH 639/734] Flesh out more cancellation point logic. --- arch/sim/src/nuttx-names.dat | 3 +++ sched/init/os_smpstart.c | 7 +++++++ sched/init/os_start.c | 5 +++-- sched/pthread/pthread_testcancel.c | 7 ++++--- sched/sched/sched_wait.c | 2 +- sched/sched/sched_waitid.c | 6 ++++++ sched/sched/sched_waitpid.c | 15 +++++++++++++++ sched/semaphore/sem_wait.c | 5 +++++ 8 files changed, 44 insertions(+), 6 deletions(-) diff --git a/arch/sim/src/nuttx-names.dat b/arch/sim/src/nuttx-names.dat index 759743be53..f1373f1d9c 100644 --- a/arch/sim/src/nuttx-names.dat +++ b/arch/sim/src/nuttx-names.dat @@ -62,7 +62,10 @@ pthread_mutex_init NXpthread_mutex_init pthread_mutex_lock NXpthread_mutex_lock pthread_mutex_unlock NXpthread_mutex_unlock pthread_setspecific NXpthread_setspecific +pthread_setcancelstate NXpthread_setcancelstate +pthread_setcanceltype NXpthread_setcanceltype pthread_sigmask NXpthread_sigmask +pthread_testcancel NXpthread_testcancel pthread_yield NXpthread_yield ptsname NXptsname ptsname_r NXptsname_r diff --git a/sched/init/os_smpstart.c b/sched/init/os_smpstart.c index ba8afac2de..17316e5b61 100644 --- a/sched/init/os_smpstart.c +++ b/sched/init/os_smpstart.c @@ -218,6 +218,13 @@ int os_smp_start(void) */ up_initial_state(tcb); + + /* Set the task flags to indicate that this is a kernel thread and that + * this task is locked to this CPU. + */ + + tcb->flags = (TCB_FLAG_TTYPE_KERNEL | TCB_FLAG_NONCANCELABLE | TCB_FLAG_CPU_LOCKED); + tcb->cpu = cpu; } /* Then start all of the other CPUs after we have completed the memory diff --git a/sched/init/os_start.c b/sched/init/os_start.c index 17e1f40cde..5b8236b56a 100644 --- a/sched/init/os_start.c +++ b/sched/init/os_start.c @@ -470,10 +470,11 @@ void os_start(void) */ #ifdef CONFIG_SMP - g_idletcb[cpu].cmn.flags = (TCB_FLAG_TTYPE_KERNEL | TCB_FLAG_CPU_LOCKED); + g_idletcb[cpu].cmn.flags = (TCB_FLAG_TTYPE_KERNEL TCB_FLAG_NONCANCELABLE | + TCB_FLAG_CPU_LOCKED); g_idletcb[cpu].cmn.cpu = cpu; #else - g_idletcb[cpu].cmn.flags = TCB_FLAG_TTYPE_KERNEL; + g_idletcb[cpu].cmn.flags = (TCB_FLAG_TTYPE_KERNEL | TCB_FLAG_NONCANCELABLE); #endif #ifdef CONFIG_SMP diff --git a/sched/pthread/pthread_testcancel.c b/sched/pthread/pthread_testcancel.c index 0e6186dec2..c58d9344e1 100644 --- a/sched/pthread/pthread_testcancel.c +++ b/sched/pthread/pthread_testcancel.c @@ -42,6 +42,8 @@ #include #include +#include + #include "sched/sched.h" /**************************************************************************** @@ -60,7 +62,6 @@ void pthread_testcancel(void) { -#ifdef CONFIG_CANCELLATION_POINTS -# warning Missing Logic -#endif + enter_cancellation_point(); + leave_cancellation_point(); } diff --git a/sched/sched/sched_wait.c b/sched/sched/sched_wait.c index d1547e07cf..6a50403d54 100644 --- a/sched/sched/sched_wait.c +++ b/sched/sched/sched_wait.c @@ -44,6 +44,7 @@ #include #include +#include #include "sched/sched.h" @@ -84,4 +85,3 @@ pid_t wait(FAR int *stat_loc) } #endif /* CONFIG_SCHED_WAITPID && CONFIG_SCHED_HAVE_PARENT */ - diff --git a/sched/sched/sched_waitid.c b/sched/sched/sched_waitid.c index f4e48d5f64..3fb3a329a2 100644 --- a/sched/sched/sched_waitid.c +++ b/sched/sched/sched_waitid.c @@ -164,6 +164,10 @@ int waitid(idtype_t idtype, id_t id, FAR siginfo_t *info, int options) int errcode; int ret; + /* waitid() is a cancellation point */ + + enter_cancellation_point(); + /* MISSING LOGIC: If WNOHANG is provided in the options, then this function * should returned immediately. However, there is no mechanism available now * know if the thread has child: The children remember their parents (if @@ -404,12 +408,14 @@ int waitid(idtype_t idtype, id_t id, FAR siginfo_t *info, int options) } } + leave_cancellation_point(); sched_unlock(); return OK; errout_with_errno: set_errno(errcode); errout: + leave_cancellation_point(); sched_unlock(); return ERROR; } diff --git a/sched/sched/sched_waitpid.c b/sched/sched/sched_waitpid.c index a3ef50674f..d386d15308 100644 --- a/sched/sched/sched_waitpid.c +++ b/sched/sched/sched_waitpid.c @@ -45,6 +45,7 @@ #include #include +#include #include "sched/sched.h" #include "group/group.h" @@ -185,12 +186,17 @@ pid_t waitpid(pid_t pid, int *stat_loc, int options) DEBUGASSERT(stat_loc); + /* waitpid() is a cancellation point */ + + enter_cancellation_point(); + /* None of the options are supported */ #ifdef CONFIG_DEBUG_FEATURES if (options != 0) { set_errno(ENOSYS); + leave_cancellation_point(); return ERROR; } #endif @@ -268,12 +274,14 @@ pid_t waitpid(pid_t pid, int *stat_loc, int options) /* On success, return the PID */ + leave_cancellation_point(); sched_unlock(); return pid; errout_with_errno: set_errno(errcode); errout: + leave_cancellation_point(); sched_unlock(); return ERROR; } @@ -307,12 +315,17 @@ pid_t waitpid(pid_t pid, int *stat_loc, int options) DEBUGASSERT(stat_loc); + /* waitpid() is a cancellation point */ + + enter_cancellation_point(); + /* None of the options are supported */ #ifdef CONFIG_DEBUG_FEATURES if (options != 0) { set_errno(ENOSYS); + leave_cancellation_point(); return ERROR; } #endif @@ -528,6 +541,7 @@ pid_t waitpid(pid_t pid, int *stat_loc, int options) } } + leave_cancellation_point(); sched_unlock(); return (int)pid; @@ -535,6 +549,7 @@ errout_with_errno: set_errno(errcode); errout_with_lock: + leave_cancellation_point(); sched_unlock(); return ERROR; } diff --git a/sched/semaphore/sem_wait.c b/sched/semaphore/sem_wait.c index da855bc70c..d0b6c8661a 100644 --- a/sched/semaphore/sem_wait.c +++ b/sched/semaphore/sem_wait.c @@ -86,6 +86,10 @@ int sem_wait(FAR sem_t *sem) DEBUGASSERT(sem != NULL && up_interrupt_context() == false); + /* sem_wait is a cancellation point */ + + enter_cancellation_point(); + /* Make sure we were supplied with a valid semaphore. */ if (sem != NULL) @@ -196,5 +200,6 @@ int sem_wait(FAR sem_t *sem) set_errno(EINVAL); } + leave_cancellation_point(); return ret; } -- GitLab From 64ae731c99e819bb464e0e220ff502f9ff8d910f Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Fri, 9 Dec 2016 16:35:35 +0000 Subject: [PATCH 640/734] stm32_allocateheap.c edited online with Bitbucket --- arch/arm/src/stm32/stm32_allocateheap.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/src/stm32/stm32_allocateheap.c b/arch/arm/src/stm32/stm32_allocateheap.c index c77f81b4a3..92a3fcdd81 100644 --- a/arch/arm/src/stm32/stm32_allocateheap.c +++ b/arch/arm/src/stm32/stm32_allocateheap.c @@ -302,6 +302,7 @@ # else # define SRAM1_END 0x20020000 # endif + /* Set the range of CCM SRAM as well (although we may not use it) */ # define SRAM2_START 0x10000000 -- GitLab From 35023e4c6ddd78592d0d93e1a65d60bc389426bb Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Fri, 9 Dec 2016 10:50:48 -0600 Subject: [PATCH 641/734] LPC43xx SD card: Correct pin configuration options needed for SD card pins. --- .../lpc43xx/chip/lpc4310203050_pinconfig.h | 34 +++++++++---------- .../lpc43xx/chip/lpc4337jet100_pinconfig.h | 34 +++++++++---------- .../lpc43xx/chip/lpc4357fet256_pinconfig.h | 34 +++++++++---------- 3 files changed, 51 insertions(+), 51 deletions(-) diff --git a/arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h b/arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h index 708ecfa862..23380f60e3 100644 --- a/arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h +++ b/arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h @@ -603,23 +603,23 @@ #define PINCONF_QEI_PHA (PINCONF_FUNC1|PINCONF_PINSA|PINCONF_PIN_3) #define PINCONF_QEI_PHB (PINCONF_FUNC1|PINCONF_PINSA|PINCONF_PIN_2) -#define PINCONF_SD_CD_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_13) -#define PINCONF_SD_CD_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_8) -#define PINCONF_SD_CLK (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_0) -#define PINCONF_SD_CMD_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_6) -#define PINCONF_SD_CMD_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_10) -#define PINCONF_SD_DAT0_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_9) -#define PINCONF_SD_DAT0_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_4) -#define PINCONF_SD_DAT1_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_10) -#define PINCONF_SD_DAT1_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_5) -#define PINCONF_SD_DAT2_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_11) -#define PINCONF_SD_DAT2_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_6) -#define PINCONF_SD_DAT3_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_12) -#define PINCONF_SD_DAT3_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_7) -#define PINCONF_SD_DAT4 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_11) -#define PINCONF_SD_DAT5 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_12) -#define PINCONF_SD_DAT6 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_13) -#define PINCONF_SD_DAT7 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_14) +#define PINCONF_SD_CD_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_13) +#define PINCONF_SD_CD_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_8) +#define PINCONF_SD_CLK (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_0) +#define PINCONF_SD_CMD_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_6) +#define PINCONF_SD_CMD_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_10) +#define PINCONF_SD_DAT0_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_9) +#define PINCONF_SD_DAT0_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_4) +#define PINCONF_SD_DAT1_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_10) +#define PINCONF_SD_DAT1_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_5) +#define PINCONF_SD_DAT2_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_11) +#define PINCONF_SD_DAT2_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_6) +#define PINCONF_SD_DAT3_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_12) +#define PINCONF_SD_DAT3_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_7) +#define PINCONF_SD_DAT4 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_11) +#define PINCONF_SD_DAT5 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_12) +#define PINCONF_SD_DAT6 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_13) +#define PINCONF_SD_DAT7 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_14) #define PINCONF_SD_POW_1 (PINCONF_FUNC5|PINCONF_PINSD|PINCONF_PIN_1) #define PINCONF_SD_POW_2 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_5) #define PINCONF_SD_POW_3 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_9) diff --git a/arch/arm/src/lpc43xx/chip/lpc4337jet100_pinconfig.h b/arch/arm/src/lpc43xx/chip/lpc4337jet100_pinconfig.h index cf3fcd2213..fb63978ec3 100644 --- a/arch/arm/src/lpc43xx/chip/lpc4337jet100_pinconfig.h +++ b/arch/arm/src/lpc43xx/chip/lpc4337jet100_pinconfig.h @@ -603,23 +603,23 @@ #define PINCONF_QEI_PHA (PINCONF_FUNC1|PINCONF_PINSA|PINCONF_PIN_3) #define PINCONF_QEI_PHB (PINCONF_FUNC1|PINCONF_PINSA|PINCONF_PIN_2) -#define PINCONF_SD_CD_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_13) -#define PINCONF_SD_CD_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_8) -#define PINCONF_SD_CLK (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_0) -#define PINCONF_SD_CMD_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_6) -#define PINCONF_SD_CMD_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_10) -#define PINCONF_SD_DAT0_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_9) -#define PINCONF_SD_DAT0_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_4) -#define PINCONF_SD_DAT1_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_10) -#define PINCONF_SD_DAT1_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_5) -#define PINCONF_SD_DAT2_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_11) -#define PINCONF_SD_DAT2_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_6) -#define PINCONF_SD_DAT3_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_12) -#define PINCONF_SD_DAT3_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_7) -#define PINCONF_SD_DAT4 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_11) -#define PINCONF_SD_DAT5 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_12) -#define PINCONF_SD_DAT6 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_13) -#define PINCONF_SD_DAT7 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_14) +#define PINCONF_SD_CD_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_13) +#define PINCONF_SD_CD_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_8) +#define PINCONF_SD_CLK (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_0) +#define PINCONF_SD_CMD_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_6) +#define PINCONF_SD_CMD_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_10) +#define PINCONF_SD_DAT0_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_9) +#define PINCONF_SD_DAT0_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_4) +#define PINCONF_SD_DAT1_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_10) +#define PINCONF_SD_DAT1_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_5) +#define PINCONF_SD_DAT2_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_11) +#define PINCONF_SD_DAT2_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_6) +#define PINCONF_SD_DAT3_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_12) +#define PINCONF_SD_DAT3_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_7) +#define PINCONF_SD_DAT4 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_11) +#define PINCONF_SD_DAT5 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_12) +#define PINCONF_SD_DAT6 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_13) +#define PINCONF_SD_DAT7 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_14) #define PINCONF_SD_POW_1 (PINCONF_FUNC5|PINCONF_PINSD|PINCONF_PIN_1) #define PINCONF_SD_POW_2 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_5) #define PINCONF_SD_POW_3 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_9) diff --git a/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h b/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h index 41a5d93954..0c9a37a0ff 100644 --- a/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h +++ b/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h @@ -603,23 +603,23 @@ #define PINCONF_QEI_PHA (PINCONF_FUNC1|PINCONF_PINSA|PINCONF_PIN_3) #define PINCONF_QEI_PHB (PINCONF_FUNC1|PINCONF_PINSA|PINCONF_PIN_2) -#define PINCONF_SD_CD_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_13) -#define PINCONF_SD_CD_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_8) -#define PINCONF_SD_CLK (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_0) -#define PINCONF_SD_CMD_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_6) -#define PINCONF_SD_CMD_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_10) -#define PINCONF_SD_DAT0_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_9) -#define PINCONF_SD_DAT0_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_4) -#define PINCONF_SD_DAT1_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_10) -#define PINCONF_SD_DAT1_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_5) -#define PINCONF_SD_DAT2_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_11) -#define PINCONF_SD_DAT2_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_6) -#define PINCONF_SD_DAT3_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_12) -#define PINCONF_SD_DAT3_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_7) -#define PINCONF_SD_DAT4 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_11) -#define PINCONF_SD_DAT5 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_12) -#define PINCONF_SD_DAT6 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_13) -#define PINCONF_SD_DAT7 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_14) +#define PINCONF_SD_CD_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_13) +#define PINCONF_SD_CD_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_8) +#define PINCONF_SD_CLK (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_0) +#define PINCONF_SD_CMD_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_6) +#define PINCONF_SD_CMD_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_10) +#define PINCONF_SD_DAT0_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_9) +#define PINCONF_SD_DAT0_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_4) +#define PINCONF_SD_DAT1_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_10) +#define PINCONF_SD_DAT1_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_5) +#define PINCONF_SD_DAT2_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_11) +#define PINCONF_SD_DAT2_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_6) +#define PINCONF_SD_DAT3_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_12) +#define PINCONF_SD_DAT3_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_7) +#define PINCONF_SD_DAT4 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_11) +#define PINCONF_SD_DAT5 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_12) +#define PINCONF_SD_DAT6 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_13) +#define PINCONF_SD_DAT7 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_14) #define PINCONF_SD_POW_1 (PINCONF_FUNC5|PINCONF_PINSD|PINCONF_PIN_1) #define PINCONF_SD_POW_2 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_5) #define PINCONF_SD_POW_3 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_9) -- GitLab From c9ca97b4b531dbd9adf1e4ad6a9c09acb5763ded Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 9 Dec 2016 12:01:18 -0600 Subject: [PATCH 642/734] cancellation points are basically function. More tested is needed and additional cancellation points must be implemented before this can be merged back to master. --- fs/vfs/fs_poll.c | 6 ++++++ fs/vfs/fs_select.c | 6 ++++++ sched/pthread/pthread_cancel.c | 30 ++++++++++++++++++++++++++++++ sched/pthread/pthread_exit.c | 11 +++++++++++ sched/sched/sched_waitid.c | 1 + sched/semaphore/sem_wait.c | 1 + sched/task/task_cancelpt.c | 8 ++++++-- sched/task/task_delete.c | 32 +++++++++++++++++++++++++++++++- sched/task/task_exithook.c | 11 +++++++++++ 9 files changed, 103 insertions(+), 3 deletions(-) diff --git a/fs/vfs/fs_poll.c b/fs/vfs/fs_poll.c index e2c66abf7b..bccd7d4f14 100644 --- a/fs/vfs/fs_poll.c +++ b/fs/vfs/fs_poll.c @@ -48,6 +48,7 @@ #include #include +#include #include #include @@ -365,6 +366,10 @@ int poll(FAR struct pollfd *fds, nfds_t nfds, int timeout) int errcode; int ret; + /* poll() is a cancellation point */ + + enter_cancellation_point(); + /* This semaphore is used for signaling and, hence, should not have * priority inheritance enabled. */ @@ -425,6 +430,7 @@ int poll(FAR struct pollfd *fds, nfds_t nfds, int timeout) } sem_destroy(&sem); + leave_cancellation_point(); /* Check for errors */ diff --git a/fs/vfs/fs_select.c b/fs/vfs/fs_select.c index d71d8e28a1..8a9cd9ae60 100644 --- a/fs/vfs/fs_select.c +++ b/fs/vfs/fs_select.c @@ -110,6 +110,10 @@ int select(int nfds, FAR fd_set *readfds, FAR fd_set *writefds, int ndx; int ret; + /* select() is cancellation point */ + + enter_cancellation_point(); + /* How many pollfd structures do we need to allocate? */ /* Initialize the descriptor list for poll() */ @@ -134,6 +138,7 @@ int select(int nfds, FAR fd_set *readfds, FAR fd_set *writefds, if (!pollset) { set_errno(ENOMEM); + leave_cancellation_point(); return ERROR; } @@ -280,6 +285,7 @@ int select(int nfds, FAR fd_set *readfds, FAR fd_set *writefds, set_errno(errcode); } + leave_cancellation_point(); return ret; } diff --git a/sched/pthread/pthread_cancel.c b/sched/pthread/pthread_cancel.c index fcaba69079..5b6fa04db8 100644 --- a/sched/pthread/pthread_cancel.c +++ b/sched/pthread/pthread_cancel.c @@ -45,6 +45,7 @@ #include #include "sched/sched.h" +#include "task/task.h" #include "pthread/pthread.h" /**************************************************************************** @@ -104,6 +105,35 @@ int pthread_cancel(pthread_t thread) return OK; } +#ifdef CONFIG_CANCELLATION_POINTS + /* Check if this thread supports deferred cancellation */ + + if ((tcb->cmn.flags & TCB_FLAG_CANCEL_DEFERRED) != 0) + { + /* Then we cannot cancel the thread asynchronoulsy. Mark the cancellation + * as pending. + */ + + tcb->cmn.flags |= TCB_FLAG_CANCEL_PENDING; + + /* If the thread is waiting at a cancellation point, then notify of the + * cancellation thereby waking the task up with an ECANCELED error. + * + * REVISIT: is locking the scheduler sufficent in SMP mode? + */ + + if (tcb->cmn.cpcount > 0) + { + notify_cancellation(&tcb->cmn); + } + + sched_unlock(); + return OK; + } +#endif + + /* Otherwise, perform the asyncrhonous cancellation */ + sched_unlock(); /* Check to see if the ID refers to ourselves.. this would be the diff --git a/sched/pthread/pthread_exit.c b/sched/pthread/pthread_exit.c index 545148a4eb..40a5b7fb0d 100644 --- a/sched/pthread/pthread_exit.c +++ b/sched/pthread/pthread_exit.c @@ -94,6 +94,17 @@ void pthread_exit(FAR void *exit_value) } #endif +#ifdef CONFIG_CANCELLATION_POINTS + /* Mark the pthread as non-cancelable to avoid additional calls to + * pthread_exit() due to any cancellation point logic that might get + * kicked off by actions taken during pthread_exit processing. + */ + + tcb->flags |= TCB_FLAG_NONCANCELABLE; + tcb->flags &= ~TCB_FLAG_CANCEL_PENDING; + tcb->cpcount = 0; +#endif + #ifdef CONFIG_PTHREAD_CLEANUP /* Perform any stack pthread clean-up callbacks */ diff --git a/sched/sched/sched_waitid.c b/sched/sched/sched_waitid.c index 3fb3a329a2..439fe0b8ac 100644 --- a/sched/sched/sched_waitid.c +++ b/sched/sched/sched_waitid.c @@ -44,6 +44,7 @@ #include #include +#include #include "sched/sched.h" #include "group/group.h" diff --git a/sched/semaphore/sem_wait.c b/sched/semaphore/sem_wait.c index d0b6c8661a..8bfe95254b 100644 --- a/sched/semaphore/sem_wait.c +++ b/sched/semaphore/sem_wait.c @@ -46,6 +46,7 @@ #include #include +#include #include "sched/sched.h" #include "semaphore/semaphore.h" diff --git a/sched/task/task_cancelpt.c b/sched/task/task_cancelpt.c index 162bbc139c..fcf6745c65 100644 --- a/sched/task/task_cancelpt.c +++ b/sched/task/task_cancelpt.c @@ -108,6 +108,8 @@ void enter_cancellation_point(void) /* Disabling pre-emption should provide sufficient protection. We only * need the TCB to be stationary (no interrupt level modification is * anticipated). + * + * REVISIT: is locking the scheduler sufficent in SMP mode? */ sched_lock(); @@ -135,7 +137,7 @@ void enter_cancellation_point(void) #ifndef CONFIG_DISABLE_PTHREAD if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD) { - pthread_exit(NULL); + pthread_exit(PTHREAD_CANCELED); } else #endif @@ -180,6 +182,8 @@ void leave_cancellation_point(void) /* Disabling pre-emption should provide sufficient protection. We only * need the TCB to be stationary (no interrupt level modification is * anticipated). + * + * REVISIT: is locking the scheduler sufficent in SMP mode? */ sched_lock(); @@ -211,7 +215,7 @@ void leave_cancellation_point(void) #ifndef CONFIG_DISABLE_PTHREAD if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD) { - pthread_exit(NULL); + pthread_exit(PTHREAD_CANCELED); } else #endif diff --git a/sched/task/task_delete.c b/sched/task/task_delete.c index 5b4c0f747d..50746f2387 100644 --- a/sched/task/task_delete.c +++ b/sched/task/task_delete.c @@ -103,7 +103,37 @@ int task_delete(pid_t pid) exit(EXIT_SUCCESS); } - /* Then let task_terminate do the heavy lifting */ +#ifdef CONFIG_CANCELLATION_POINTS + /* Check if this task supports deferred cancellation */ + + sched_lock(); + if ((rtcb->flags & TCB_FLAG_CANCEL_DEFERRED) != 0) + { + /* Then we cannot cancel the task asynchronoulsy. Mark the cancellation + * as pending. + */ + + rtcb->flags |= TCB_FLAG_CANCEL_PENDING; + + /* If the task is waiting at a cancellation point, then notify of the + * cancellation thereby waking the task up with an ECANCELED error. + * + * REVISIT: is locking the scheduler sufficent in SMP mode? + */ + + if (rtcb->cpcount > 0) + { + notify_cancellation(rtcb); + } + + sched_unlock(); + return OK; + } +#endif + + /* Otherwise, perform the asynchronous cancellation, letting + * task_terminate() do all of the heavy lifting. + */ return task_terminate(pid, false); } diff --git a/sched/task/task_exithook.c b/sched/task/task_exithook.c index 96856d8792..e384238365 100644 --- a/sched/task/task_exithook.c +++ b/sched/task/task_exithook.c @@ -612,6 +612,17 @@ void task_exithook(FAR struct tcb_s *tcb, int status, bool nonblocking) return; } +#ifdef CONFIG_CANCELLATION_POINTS + /* Mark the task as non-cancelable to avoid additional calls to exit() + * due to any cancellation point logic that might get kicked off by + * actions taken during exit processing. + */ + + tcb->flags |= TCB_FLAG_NONCANCELABLE; + tcb->flags &= ~TCB_FLAG_CANCEL_PENDING; + tcb->cpcount = 0; +#endif + #if defined(CONFIG_SCHED_ATEXIT) || defined(CONFIG_SCHED_ONEXIT) /* If exit function(s) were registered, call them now before we do any un- * initialization. -- GitLab From d20265164e122475f6a2e4473719e5b381e8b14f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 9 Dec 2016 12:13:52 -0600 Subject: [PATCH 643/734] Update TODO list --- TODO | 54 ++++++++++-------------------------------------------- 1 file changed, 10 insertions(+), 44 deletions(-) diff --git a/TODO b/TODO index 72472dfb23..62839abb7b 100644 --- a/TODO +++ b/TODO @@ -14,7 +14,7 @@ nuttx/: (1) Memory Management (mm/) (1) Power Management (drivers/pm) (3) Signals (sched/signal, arch/) - (2) pthreads (sched/pthread) + (1) pthreads (sched/pthread) (0) Message Queues (sched/mqueue) (8) Kernel/Protected Build (3) C++ Support @@ -166,9 +166,9 @@ o Task/Scheduler (sched/) Priority: Low Title: REMOVE TASK_DELETE - Description: Need to remove or fix task delete(). This interface is non- - standard and not safe. Arbitrary deleting tasks can cause - serious problems such as memory leaks and resources like + Description: Need to remove asychronous fix task_delete(). This interface + is non-standard and not safe. Arbitrary deleting tasks can + cause serious problems such as memory leaks and resources like semaphores left in bad states. Task/process exit callbacks registered via atexit() or @@ -187,10 +187,12 @@ o Task/Scheduler (sched/) apps/netutils/thttpd to kill CGI tasks that timeout. So not so simple to remove. - Option: Perhaps task_delete() should not do asynchronous - deletion but should rather do the same kind of - synchronization such as the pthread_cancellation points? - (see pthread_cancel() issues). + Option: With CONFIG_CANCELLATION_POINTS=y task_delete() + does not do asynchronous deletion but should rather do the + same kind of synchronization such as the pthread cancellation + points. In this configuration, none of the issues above + apply. It is only the asyncrhonous task deletion that cannot + be supported. Status: Open Priority: Low and not easily removable. @@ -528,42 +530,6 @@ o Signals (sched/signal, arch/) o pthreads (sched/pthreads) ^^^^^^^^^^^^^^^^^ - Title: CANCELLATION POINTS - Description: pthread_cancel(): Should implement cancellation points and - pthread_testcancel(). - - Internal implementation perhaps as follows. See list of - functions that are cancellation points on OpenGroup.org. In - general: - - - Two types of cancellation. DEFFERRED and ASYCNCHOOUS: - PTHREAD_CANCEL_DEFERRED: A cancellation request is deferred - until the thread next calls a function that is a cancellation - point. This is the default cancelability type for all - threads. - PTHREAD_CANCEL_ASYNCHRONOUS: The thread can be canceled at - any time - DEFERRED should be the default but currently only - asyncrhononous is supported by NuttX - - To implement DEFERRED mode: - All cancellations must pend. - Check if the thread is within cancellation region, then - treat like a signal to wake up with -ECANCELED vs -EINTER - - For each function/cancellation point - - - Call enter_cancellation region() on entry. Checks for - pending cancellation and marks "within cancellation region" - in TCB flags. - - Will wake-up with -ECANCELED if cancellation occurs. - - Call leave_cancellation region() on exit. Checks for - pending cancellation and marks NOT "within cancellation region" - - Perhaps task_delete() should do the same kind of synchronization? - - Status: Open. No changes are planned. - Priority: Low, probably not that useful - Title: PTHREAD_PRIO_PROTECT Description: Extend pthread_mutexattr_setprotocol() support PTHREAD_PRIO_PROTECT: -- GitLab From 3eba0acb1c091bc83d4e35a9ceb9ad33d05126e8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 9 Dec 2016 13:49:36 -0600 Subject: [PATCH 644/734] More cancellation points. --- fs/vfs/fs_close.c | 16 ++++++++-- fs/vfs/fs_fcntl.c | 20 ++++++------ fs/vfs/fs_fsync.c | 15 +++++++-- fs/vfs/fs_open.c | 15 ++++++--- fs/vfs/fs_pread.c | 23 +++++++++----- fs/vfs/fs_pwrite.c | 23 +++++++++----- fs/vfs/fs_read.c | 45 +++++++++++++++++---------- fs/vfs/fs_write.c | 63 ++++++++++++++++++++++++-------------- sched/sched/sched_wait.c | 4 +++ sched/task/task_exithook.c | 2 +- 10 files changed, 150 insertions(+), 76 deletions(-) diff --git a/fs/vfs/fs_close.c b/fs/vfs/fs_close.c index a2b02b1d87..573b73ee70 100644 --- a/fs/vfs/fs_close.c +++ b/fs/vfs/fs_close.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/vfs/fs_close.c * - * Copyright (C) 2007-2009, 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -42,6 +42,8 @@ #include #include #include + +#include #include #if defined(CONFIG_NET) && CONFIG_NSOCKET_DESCRIPTORS > 0 @@ -82,7 +84,13 @@ int close(int fd) int errcode; #if CONFIG_NFILE_DESCRIPTORS > 0 int ret; +#endif + + /* close() is a cancellation point */ + enter_cancellation_point(); + +#if CONFIG_NFILE_DESCRIPTORS > 0 /* Did we get a valid file descriptor? */ if ((unsigned int)fd >= CONFIG_NFILE_DESCRIPTORS) @@ -93,7 +101,9 @@ int close(int fd) #if defined(CONFIG_NET) && CONFIG_NSOCKET_DESCRIPTORS > 0 if ((unsigned int)fd < (CONFIG_NFILE_DESCRIPTORS+CONFIG_NSOCKET_DESCRIPTORS)) { - return net_close(fd); + ret = net_close(fd); + leave_cancellation_point(); + return ret; } else #endif @@ -123,11 +133,13 @@ int close(int fd) goto errout; } + leave_cancellation_point(); return OK; #endif errout: set_errno(errcode); + leave_cancellation_point(); return ERROR; } diff --git a/fs/vfs/fs_fcntl.c b/fs/vfs/fs_fcntl.c index 01ca8761fe..f2f1ae5c4c 100644 --- a/fs/vfs/fs_fcntl.c +++ b/fs/vfs/fs_fcntl.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/vfs/fs_fcntl.c * - * Copyright (C) 2009, 2012-2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2009, 2012-2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -44,20 +44,13 @@ #include #include +#include +#include #include #include -#include #include "inode/inode.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -228,6 +221,10 @@ int fcntl(int fd, int cmd, ...) va_list ap; int ret; + /* fcntl() is a cancellation point */ + + enter_cancellation_point(); + /* Setup to access the variable argument list */ va_start(ap, cmd); @@ -244,6 +241,8 @@ int fcntl(int fd, int cmd, ...) { /* The errno value has already been set */ + va_end(ap); + leave_cancellation_point(); return ERROR; } @@ -273,5 +272,6 @@ int fcntl(int fd, int cmd, ...) } va_end(ap); + leave_cancellation_point(); return ret; } diff --git a/fs/vfs/fs_fsync.c b/fs/vfs/fs_fsync.c index a2d58825eb..fb132275a0 100644 --- a/fs/vfs/fs_fsync.c +++ b/fs/vfs/fs_fsync.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/vfs/fs_fsync.c * - * Copyright (C) 2007-2009, 2013-2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2013-2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -44,8 +44,9 @@ #include #include -#include #include +#include +#include #include "inode/inode.h" @@ -117,6 +118,11 @@ errout: int fsync(int fd) { FAR struct file *filep; + int ret; + + /* fsync() is a cancellation point */ + + enter_cancellation_point(); /* Get the file structure corresponding to the file descriptor. */ @@ -125,12 +131,15 @@ int fsync(int fd) { /* The errno value has already been set */ + leave_cancellation_point(); return ERROR; } /* Perform the fsync operation */ - return file_fsync(filep); + ret = file_fsync(filep); + leave_cancellation_point(); + return ret; } #endif /* !CONFIG_DISABLE_MOUNTPOINT */ diff --git a/fs/vfs/fs_open.c b/fs/vfs/fs_open.c index a66f62e869..5930ccf7ef 100644 --- a/fs/vfs/fs_open.c +++ b/fs/vfs/fs_open.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/vfs/fs_open.c * - * Copyright (C) 2007-2009, 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2011-2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -48,15 +48,12 @@ #include #endif +#include #include #include "inode/inode.h" #include "driver/driver.h" -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -106,6 +103,10 @@ int open(const char *path, int oflags, ...) # warning "File creation not implemented" # endif + /* open() is a cancellation point */ + + enter_cancellation_point(); + /* If the file is opened for creation, then get the mode bits */ if ((oflags & (O_WRONLY | O_CREAT)) != 0) @@ -159,6 +160,7 @@ int open(const char *path, int oflags, ...) /* Return the file descriptor */ + leave_cancellation_point(); return fd; } else @@ -204,6 +206,7 @@ int open(const char *path, int oflags, ...) { /* The errno value has already been set */ + leave_cancellation_point(); return ERROR; } @@ -264,6 +267,7 @@ int open(const char *path, int oflags, ...) } #endif + leave_cancellation_point(); return fd; errout_with_fd: @@ -272,5 +276,6 @@ errout_with_inode: inode_release(inode); errout: set_errno(ret); + leave_cancellation_point(); return ERROR; } diff --git a/fs/vfs/fs_pread.c b/fs/vfs/fs_pread.c index e80efe66a0..520d35684e 100644 --- a/fs/vfs/fs_pread.c +++ b/fs/vfs/fs_pread.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/vfs/fs_pread.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -43,12 +43,9 @@ #include #include +#include #include -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -144,6 +141,11 @@ ssize_t file_pread(FAR struct file *filep, FAR void *buf, size_t nbytes, ssize_t pread(int fd, FAR void *buf, size_t nbytes, off_t offset) { FAR struct file *filep; + ssize_t ret; + + /* pread() is a cancellation point */ + + enter_cancellation_point(); /* Get the file structure corresponding to the file descriptor. */ @@ -152,10 +154,15 @@ ssize_t pread(int fd, FAR void *buf, size_t nbytes, off_t offset) { /* The errno value has already been set */ - return (ssize_t)ERROR; + ret = (ssize_t)ERROR; } + else + { + /* Let file_pread do the real work */ - /* Let file_pread do the real work */ + ret = file_pread(filep, buf, nbytes, offset); + } - return file_pread(filep, buf, nbytes, offset); + leave_cancellation_point(); + return ret; } diff --git a/fs/vfs/fs_pwrite.c b/fs/vfs/fs_pwrite.c index 43630c455a..6b29ee406a 100644 --- a/fs/vfs/fs_pwrite.c +++ b/fs/vfs/fs_pwrite.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/vfs/fs_pwrite.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -43,12 +43,9 @@ #include #include +#include #include -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -142,6 +139,11 @@ ssize_t file_pwrite(FAR struct file *filep, FAR const void *buf, ssize_t pwrite(int fd, FAR const void *buf, size_t nbytes, off_t offset) { FAR struct file *filep; + ssize_t ret; + + /* pread() is a cancellation point */ + + enter_cancellation_point(); /* Get the file structure corresponding to the file descriptor. */ @@ -150,10 +152,15 @@ ssize_t pwrite(int fd, FAR const void *buf, size_t nbytes, off_t offset) { /* The errno value has already been set */ - return (ssize_t)ERROR; + ret = (ssize_t)ERROR; } + else + { + /* Let file_pread do the real work */ - /* Let file_pread do the real work */ + ret = file_pwrite(filep, buf, nbytes, offset); + } - return file_pwrite(filep, buf, nbytes, offset); + enter_cancellation_point(); + return ret; } diff --git a/fs/vfs/fs_read.c b/fs/vfs/fs_read.c index f1d6097236..b55ada24ef 100644 --- a/fs/vfs/fs_read.c +++ b/fs/vfs/fs_read.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/vfs/fs_read.c * - * Copyright (C) 2007-2009, 2012-2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2012-2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -38,19 +38,17 @@ ****************************************************************************/ #include + #include #include - #include #include #include #include -#include "inode/inode.h" +#include -/**************************************************************************** - * Private Functions - ****************************************************************************/ +#include "inode/inode.h" /**************************************************************************** * Public Functions @@ -136,23 +134,30 @@ ssize_t file_read(FAR struct file *filep, FAR void *buf, size_t nbytes) ssize_t read(int fd, FAR void *buf, size_t nbytes) { + ssize_t ret; + + /* read() is a cancellation point */ + + enter_cancellation_point(); + /* Did we get a valid file descriptor? */ #if CONFIG_NFILE_DESCRIPTORS > 0 if ((unsigned int)fd >= CONFIG_NFILE_DESCRIPTORS) #endif { +#if defined(CONFIG_NET) && CONFIG_NSOCKET_DESCRIPTORS > 0 /* No.. If networking is enabled, read() is the same as recv() with - * the flags parameter set to zero. + * the flags parameter set to zero. Note that recv() sets + * the errno variable. */ -#if defined(CONFIG_NET) && CONFIG_NSOCKET_DESCRIPTORS > 0 - return recv(fd, buf, nbytes, 0); + ret = recv(fd, buf, nbytes, 0); #else /* No networking... it is a bad descriptor in any event */ set_errno(EBADF); - return ERROR; + ret = ERROR; #endif } @@ -162,20 +167,28 @@ ssize_t read(int fd, FAR void *buf, size_t nbytes) FAR struct file *filep; /* The descriptor is in a valid range to file descriptor... do the - * read. First, get the file structure. + * read. First, get the file structure. Note that on failure, + * fs_getfilep() will set the errno variable. */ filep = fs_getfilep(fd); - if (!filep) + if (filep == NULL) { /* The errno value has already been set */ - return ERROR; + ret = ERROR; } + else + { + /* Then let file_read do all of the work. Note that file_read() + * sets the errno variable. + */ - /* Then let file_read do all of the work */ - - return file_read(filep, buf, nbytes); + ret = file_read(filep, buf, nbytes); + } } #endif + + leave_cancellation_point(); + return ret; } diff --git a/fs/vfs/fs_write.c b/fs/vfs/fs_write.c index 34b77e5a47..80f828731d 100644 --- a/fs/vfs/fs_write.c +++ b/fs/vfs/fs_write.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/vfs/fs_write.c * - * Copyright (C) 2007-2009, 2012-2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2012-2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -38,6 +38,7 @@ ****************************************************************************/ #include + #include #include #include @@ -49,11 +50,9 @@ # include #endif -#include "inode/inode.h" +#include -/**************************************************************************** - * Private Functions - ****************************************************************************/ +#include "inode/inode.h" /**************************************************************************** * Public Functions @@ -72,7 +71,7 @@ ssize_t file_write(FAR struct file *filep, FAR const void *buf, size_t nbytes) { FAR struct inode *inode; - int ret; + ssize_t ret; int errcode; /* Was this file opened for write access? */ @@ -163,6 +162,11 @@ ssize_t write(int fd, FAR const void *buf, size_t nbytes) #if CONFIG_NFILE_DESCRIPTORS > 0 FAR struct file *filep; #endif + ssize_t ret; + + /* write() is a cancellation point */ + + enter_cancellation_point(); /* Did we get a valid file descriptor? */ @@ -170,31 +174,44 @@ ssize_t write(int fd, FAR const void *buf, size_t nbytes) if ((unsigned int)fd >= CONFIG_NFILE_DESCRIPTORS) #endif { - /* Write to a socket descriptor is equivalent to send with flags == 0 */ - #if defined(CONFIG_NET_TCP) && CONFIG_NSOCKET_DESCRIPTORS > 0 - return send(fd, buf, nbytes, 0); + /* Write to a socket descriptor is equivalent to send with flags == 0. + * Note that send() will set the errno on failure. + */ + + ret = send(fd, buf, nbytes, 0); #else set_errno(EBADF); - return ERROR; + ret = ERROR ERROR; #endif } #if CONFIG_NFILE_DESCRIPTORS > 0 - /* The descriptor is in the right range to be a file descriptor... write - * to the file. - */ - - filep = fs_getfilep(fd); - if (!filep) + else { - /* The errno value has already been set */ - - return ERROR; + /* The descriptor is in the right range to be a file descriptor.. + * write to the file. Note that fs_getfilep() will set the errno on + * failure. + */ + + filep = fs_getfilep(fd); + if (filep == NULL) + { + /* The errno value has already been set */ + + ret = ERROR; + } + else + { + /* Perform the write operation using the file descriptor as an + * index. Note that file_write() will set the errno on failure. + */ + + ret = file_write(filep, buf, nbytes); + } +#endif } - /* Perform the write operation using the file descriptor as an index */ - - return file_write(filep, buf, nbytes); -#endif + leave_cancellation_point(); + return ret; } diff --git a/sched/sched/sched_wait.c b/sched/sched/sched_wait.c index 6a50403d54..8987098528 100644 --- a/sched/sched/sched_wait.c +++ b/sched/sched/sched_wait.c @@ -81,6 +81,10 @@ pid_t wait(FAR int *stat_loc) { + /* wait() is a cancellation point, but nothings needs to be done for this + * trivial case. + */ + return waitpid((pid_t)-1, stat_loc, 0); } diff --git a/sched/task/task_exithook.c b/sched/task/task_exithook.c index e384238365..3c44135330 100644 --- a/sched/task/task_exithook.c +++ b/sched/task/task_exithook.c @@ -146,7 +146,7 @@ static inline void task_onexit(FAR struct tcb_s *tcb, int status) * We must not call the registered function in supervisor mode! See also * atexit() and pthread_cleanup_pop() callbacks. * - * REVISIT: In the case of task_delete(), the callback would execute in + * REVISIT: In the case of task_delete(), the callback would execute in * he context the caller of task_delete() cancel, not in the context of * the exiting task (or process). */ -- GitLab From d8783a7345e07e54ce6a1bdcbe1fd84f4c4063ed Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 9 Dec 2016 14:41:54 -0600 Subject: [PATCH 645/734] Update Documentation --- Documentation/NuttxUserGuide.html | 342 +++++++++++++++++--------- sched/pthread/pthread_setcanceltype.c | 2 +- 2 files changed, 225 insertions(+), 119 deletions(-) diff --git a/Documentation/NuttxUserGuide.html b/Documentation/NuttxUserGuide.html index 3766eba646..59e1b76f4f 100644 --- a/Documentation/NuttxUserGuide.html +++ b/Documentation/NuttxUserGuide.html @@ -13,7 +13,7 @@

    NuttX Operating System

    User's Manual

    by

    Gregory Nutt

    -

    Last Updated: July 24, 2015

    +

    Last Updated: December 9, 2016

    @@ -5424,12 +5424,15 @@ be sent.
  • 2.8.13 pthread_exit
  • 2.8.14 pthread_cancel
  • 2.8.15 pthread_setcancelstate
    • -
  • 2.8.16 pthread_testcancelstate
    • -
  • 2.8.17 pthread_join
    • -
  • 2.8.18 pthread_yield
    • -
  • 2.8.19 pthread_self
    • -
  • 2.8.20 pthread_getschedparam
    • -
  • 2.8.21 pthread_setschedparam
    • +
  • 2.8.16 pthread_setcanceltype
    • +
  • 2.8.17 pthread_testcancel
    • +
  • 2.8.18 pthread_cleanup_pop
    • +
  • 2.8.19 pthread_cleanup_push
    • +
  • 2.8.20 pthread_join
    • +
  • 2.8.21 pthread_yield
    • +
  • 2.8.22 pthread_self
    • +
  • 2.8.23 pthread_getschedparam
    • +
  • 2.8.24 pthread_setschedparam

    • Thread Specific Data. @@ -5439,64 +5442,64 @@ be sent. (2) The main task thread does not had thread-specific data.

    pthread Mutexes.

    Condition Variables.

    Barriers.

    Initialization.

    Signals.

    @@ -5515,8 +5518,6 @@ be sent.

  • pthread_attr_setscope. get and set the contentionscope attribute.
  • pthread_attr_setstack. get and set stack attributes.
  • pthread_attr_setstackaddr. get and set the stackaddr attribute.
    • -
  • pthread_cleanup_pop. establish cancellation handlers.
    • -
  • pthread_cleanup_push. establish cancellation handlers.
  • pthread_condattr_getclock. set the clock selection condition variable attribute.
  • pthread_condattr_getpshared. get the process-shared condition variable attribute.
  • pthread_condattr_setclock. set the clock selection condition variable attribute.
    • @@ -5543,14 +5544,12 @@ be sent.
  • pthread_rwlockattr_getpshared. get and set the process-shared attribute of the read-write lock attributes object.
  • pthread_rwlockattr_init. destroy and initialize the read-write lock attributes object.
  • pthread_rwlockattr_setpshared. get and set the process-shared attribute of the read-write lock attributes object.
    • -
  • pthread_setcanceltype. set cancelability state.
  • pthread_setconcurrency. get and set the level of concurrency.
  • pthread_spin_destroy. destroy or initialize a spin lock object.
  • pthread_spin_init. destroy or initialize a spin lock object.
  • pthread_spin_lock. lock a spin lock object.
  • pthread_spin_trylock. lock a spin lock object.
  • pthread_spin_unlock. unlock a spin lock object.
    • -
  • pthread_testcancel. set cancelability state.

    • 2.8.1 pthread_attr_init

    @@ -5985,19 +5984,15 @@ interface of the same name.

    Description: -

    The pthread_cancel() function will request that thread -be canceled. The target thread's cancelability state determines -when the cancellation takes effect. When the -cancellation is acted on, thread will be terminated.

    +

    The pthread_cancel() function will request that thread be canceled. +The target thread's cancelability state, enabled, or disabled, determines when the cancellation takes effect: When the cancellation is acted on, thread will be terminated. +When cancelability is disabled, all cancellations are held pending in the target thread until the thread re-enables cancelability.

    -

    When cancelability is disabled, all cancels are held pending -in the target thread until the thread changes the cancelability. -When cancelability is deferred, all cancels are held pending in -the target thread until the thread changes the cancelability or -calls pthread_testcancel().

    +

    The target thread's cancelability state determines how the cancellation is acted on: +Either asychronrously or deferred. +Asynchronous cancellations we be acted upon immediately (when enabled), interrupting the thread with its processing in an abritray state.

    -

    Cancelability is asynchronous; all cancels are acted upon -immediately (when enable), interrupting the thread with its processing.

    +

    When cancelability is deferred, all cancels are held pending in the target thread until the thread changes the cancelability type or a cancellation point function such as pthread_cancel().

    Input Parameters: @@ -6018,16 +6013,10 @@ No thread could be found corresponding to that specified by the given thread ID. Assumptions/Limitations:

    -POSIX Compatibility: Comparable to the POSIX -interface of the same name. Except:

    +POSIX Compatibility: Comparable to the POSIX interface of the same name. Except:

      -
    • The thread-specific data destructor functions will be called for thread. -However, these destructors are not currently supported.
      • -
    • Cancellation types are not supported. The thread will be canceled -at the time that pthread_cancel() is called or, if cancellation is disabled, at -the time when cancellation is re-enabled.
      • -
    • pthread_testcancel() is not supported.
      • -
    • Thread cancellation at cancellation points is not supported.
      • +
    • The thread-specific data destructor functions will be not called for thread +These destructors are not currently supported.

    2.8.15 pthread_setcancelstate

    @@ -6040,23 +6029,29 @@ the time when cancellation is re-enabled.

    Description: -

    The pthread_setcancelstate() function atomically +

    +

    +The pthread_setcancelstate() function atomically sets both the calling thread's cancelability state to the indicated state and returns the previous cancelability state at the location referenced by oldstate. -Legal values for state are PTHREAD_CANCEL_ENABLE and PTHREAD_CANCEL_DISABLE.<.li> - -

    Any pending thread cancellation may occur at the time that the -cancellation state is set to PTHREAD_CANCEL_ENABLE.

    - +Legal values for state are PTHREAD_CANCEL_ENABLE and PTHREAD_CANCEL_DISABLE. +

    +

    +Any pending thread cancellation may occur at the time that the +cancellation state is set to PTHREAD_CANCEL_ENABLE. +

    +

    Input Parameters: +

    • state -New cancellation state. One of PTHREAD_CANCEL_ENABLE or PTHREAD_CANCEL_DISABLE.<.li> +New cancellation state. One of PTHREAD_CANCEL_ENABLE or PTHREAD_CANCEL_DISABLE.
    • oldstate. Location to return the previous cancellation state.
    +

    Returned Value:

    @@ -6072,38 +6067,148 @@ No thread could be found corresponding to that specified by the given thread ID. POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.16 pthread_testcancelstate

    +

    2.8.16 pthread_setcanceltype

    Function Prototype: 

         #include <pthread.h>
-    int pthread_setcancelstate(void);
+    int pthread_setcanceltype(int type, FAR int *oldtype);

    Description: -

    NOT SUPPORTED +The pthread_setcanceltype() function atomically both sets the calling thread's cancelability type to the indicated type and returns the previous cancelability type at the location referenced by oldtype. +Legal values for type are PTHREAD_CANCEL_DEFERRED and PTHREAD_CANCEL_ASYNCHRONOUS. +

    +

    +The cancelability state and type of any newly created threads are PTHREAD_CANCEL_ENABLE and PTHREAD_CANCEL_DEFERRED respectively. +

    +

    Input Parameters: +

      -
    • To be provided.
      • +
    • type +New cancellation state. One of PTHREAD_CANCEL_DEFERRED or PTHREAD_CANCEL_ASYNCHRONOUS.
      • +
    • oldtype. +Location to return the previous cancellation type. +
    +

    +

    +Returned Value: +

    +If successful, the pthread_setcancelstate() function will return +zero (OK). Otherwise, an error number will be +returned to indicate the error. +

    +

    +POSIX Compatibility: Comparable to the POSIX interface of the same name. +

    + +

    2.8.17 pthread_testcancel

    +

    +Function Prototype: +

    +

    +

    +    #include <pthread.h>
+    void pthread_testcancel(void);
+
    +

    +

    +Description: +

    +

    +The pthread_testcancel() function creates a cancellation point in the calling thread. +The pthread_testcancel() function has no effect if cancelability is disabled. +

    +

    +Input Parameters: None +

    +

    +Returned Value: None +

    +

    +POSIX Compatibility: Comparable to the POSIX interface of the same name. +

    + +

    2.8.18 pthread_cleanup_pop

    +

    +Function Prototype: +

    +

    +    #include <pthread.h>
+    void pthread_cleanup_pop(int execute);
+
    +

    +Description: +

    +

    +The pthread_cleanup_pop() function will remove the routine at the top of the calling thread's cancellation cleanup stack and optionally invoke it (if execute is non-zero). +

    +

    +Input Parameters: +

    +

    +

      +
    • execute. Execute the popped cleanup function immediately.
    +

    Returned Value: +

    If successful, the pthread_setcancelstate() function will return zero (OK). Otherwise, an error number will be returned to indicate the error:

    +

    +

    +POSIX Compatibility: Comparable to the POSIX interface of the same name. +

    + +

    2.8.19 pthread_cleanup_push

    +

    +Function Prototype: +

    +

    +    #include <pthread.h>
+    void pthread_cleanup_push(CODE void (*routine)(FAR void *), FAR void *arg);
+
    +

    +Description: +

    +

    +The pthread_cleanup_push() function will push the specified cancellation cleanup handler routine onto the calling thread's cancellation cleanup stack. + +The cancellation cleanup handler will be popped from the cancellation cleanup stack and invoked with the argument arg when: +

    +

      -
    • To be provided.
      • +
    • The thread exits (that is, calls pthread_exit()).
      • +
    • The thread acts upon a cancellation request.
      • +
    • The thread calls pthread_cleanup_pop() with a non-zero execute argument.
    -Assumptions/Limitations: +

    -POSIX Compatibility: Comparable to the POSIX -interface of the same name. +Input Parameters: +

    +

      +
    • routine. The cleanup routine to be pushed on the the cleanup stack.
      • +
    • arg. An argument that will accompany the callback.
      • +
    +

    +Returned Value: +

    +If successful, the pthread_setcancelstate() function will return +zero (OK). Otherwise, an error number will be +returned to indicate the error. +

    +

    +POSIX Compatibility: Comparable to the POSIX interface of the same name. +

    -

    2.8.17 pthread_join

    +

    2.8.20 pthread_join

    Function Prototype:

    @@ -6136,7 +6241,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.18 pthread_yield

    +

    2.8.21 pthread_yield

    Function Prototype:

    @@ -6169,7 +6274,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.19 pthread_self

    +

    2.8.22 pthread_self

    Function Prototype:

    @@ -6201,7 +6306,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.20 pthread_getschedparam

    +

    2.8.23 pthread_getschedparam

    Function Prototype:

    @@ -6291,7 +6396,7 @@ interface of the same name. Comparable to the POSIX interface of the same name.

    -

    2.8.21 pthread_setschedparam

    +

    2.8.24 pthread_setschedparam

    Function Prototype:

    @@ -6383,7 +6488,7 @@ interface of the same name. Comparable to the POSIX interface of the same name.

    -

    2.8.22 pthread_key_create

    +

    2.8.25 pthread_key_create

    Function Prototype:

    @@ -6438,7 +6543,7 @@ interface of the same name.

  • The present implementation ignores the destructor argument. -

    2.8.23 pthread_setspecific

    +

    2.8.26 pthread_setspecific

    Function Prototype:

    @@ -6488,7 +6593,7 @@ interface of the same name. destructor function. -

    2.8.24 pthread_getspecific

    +

    2.8.27 pthread_getspecific

    Function Prototype:

    @@ -6529,7 +6634,7 @@ interface of the same name. destructor function. -

    2.8.25 pthread_key_delete

    +

    2.8.28 pthread_key_delete

    Function Prototype:

    @@ -6561,7 +6666,7 @@ this function does nothing in the present implementation. POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.26 pthread_mutexattr_init

    +

    2.8.29 pthread_mutexattr_init

    Function Prototype:

    @@ -6592,7 +6697,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.27 pthread_mutexattr_destroy

    +

    2.8.30 pthread_mutexattr_destroy

    Function Prototype:

    @@ -6623,7 +6728,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.28 pthread_mutexattr_getpshared

    +

    2.8.31 pthread_mutexattr_getpshared

    Function Prototype:

    @@ -6655,7 +6760,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.29 pthread_mutexattr_setpshared

    +

    2.8.32 pthread_mutexattr_setpshared

    Function Prototype:

    @@ -6687,7 +6792,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.30 pthread_mutexattr_gettype

    +

    2.8.33 pthread_mutexattr_gettype

    Function Prototype:

    @@ -6722,7 +6827,7 @@ returned to indicate the error:

    POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.31 pthread_mutexattr_settype

    +

    2.8.34 pthread_mutexattr_settype

    Function Prototype:

    @@ -6776,7 +6881,7 @@ returned to indicate the error:

    POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.32 pthread_mutex_init

    +

    2.8.35 pthread_mutex_init

    Function Prototype:

    @@ -6808,7 +6913,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.33 pthread_mutex_destroy

    +

    2.8.36 pthread_mutex_destroy

    Function Prototype:

    @@ -6839,7 +6944,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.34 pthread_mutex_lock

    +

    2.8.37 pthread_mutex_lock

    Function Prototype:

    @@ -6905,7 +7010,7 @@ Otherwise, an error number will be returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.35 pthread_mutex_trylock

    +

    2.8.38 pthread_mutex_trylock

    Function Prototype:

    @@ -6945,7 +7050,7 @@ Otherwise, an error number will be returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.36 pthread_mutex_unlock

    +

    2.8.39 pthread_mutex_unlock

    Function Prototype:

    @@ -6991,7 +7096,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.37 pthread_condattr_init

    +

    2.8.40 pthread_condattr_init

    Function Prototype:

    @@ -7022,7 +7127,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.38 pthread_condattr_destroy

    +

    2.8.41 pthread_condattr_destroy

    Function Prototype:

    @@ -7053,7 +7158,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.39 pthread_cond_init

    +

    2.8.42 pthread_cond_init

    Function Prototype:

    @@ -7084,7 +7189,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.40 pthread_cond_destroy

    +

    2.8.43 pthread_cond_destroy

    Function Prototype:

    @@ -7115,7 +7220,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.41 pthread_cond_broadcast

    +

    2.8.44 pthread_cond_broadcast

    Function Prototype:

    @@ -7146,7 +7251,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.42 pthread_cond_signal

    +

    2.8.45 pthread_cond_signal

    Function Prototype:

    @@ -7177,7 +7282,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.43 pthread_cond_wait

    +

    2.8.46 pthread_cond_wait

    Function Prototype:

    @@ -7208,7 +7313,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.44 pthread_cond_timedwait

    +

    2.8.47 pthread_cond_timedwait

    Function Prototype:

    @@ -7245,7 +7350,7 @@ interface of the same name. POSIX Compatibility: Comparable to the POSIX interface of the same name.

    -

    2.8.45 pthread_barrierattr_init

    +

    2.8.48 pthread_barrierattr_init

    Function Prototype:

    @@ -7278,7 +7383,7 @@ interface of the same name. POSIX Compatibility: Comparable to the POSIX interface of the same name.

    -

    2.8.46 pthread_barrierattr_destroy

    +

    2.8.49 pthread_barrierattr_destroy

    Function Prototype:

    @@ -7310,7 +7415,7 @@ interface of the same name. POSIX Compatibility: Comparable to the POSIX interface of the same name.

    -

    2.8.47 pthread_barrierattr_setpshared

    +

    2.8.50 pthread_barrierattr_setpshared

    Function Prototype:

    @@ -7348,7 +7453,7 @@ interface of the same name. POSIX Compatibility: Comparable to the POSIX interface of the same name.

    -

    2.8.48 pthread_barrierattr_getpshared

    +

    2.8.51 pthread_barrierattr_getpshared

    Function Prototype:

    @@ -7380,7 +7485,7 @@ interface of the same name. POSIX Compatibility: Comparable to the POSIX interface of the same name.

    -

    2.8.49 pthread_barrier_init

    +

    2.8.52 pthread_barrier_init

    Function Prototype:

    @@ -7450,7 +7555,7 @@ interface of the same name. POSIX Compatibility: Comparable to the POSIX interface of the same name.

    -

    2.8.50 pthread_barrier_destroy

    +

    2.8.53 pthread_barrier_destroy

    Function Prototype:

    @@ -7494,7 +7599,7 @@ interface of the same name. POSIX Compatibility: Comparable to the POSIX interface of the same name.

    -

    2.8.51 pthread_barrier_wait

    +

    2.8.54 pthread_barrier_wait

    Function Prototype:

    @@ -7554,7 +7659,7 @@ interface of the same name.

    -

    2.8.52 pthread_once

    +

    2.8.55 pthread_once

    Function Prototype:

    @@ -7598,7 +7703,7 @@ interface of the same name. POSIX Compatibility: Comparable to the POSIX interface of the same name.

    -

    2.8.53 pthread_kill

    +

    2.8.56 pthread_kill

    Function Prototype:

    @@ -7660,7 +7765,7 @@ interface of the same name. POSIX Compatibility: Comparable to the POSIX interface of the same name.

    -

    2.8.54 pthread_sigmask

    +

    2.8.57 pthread_sigmask

    Function Prototype:

    @@ -10077,7 +10182,8 @@ notify a task when a message is available on a queue.
  • pthread_setschedparam
  • pthread_setspecific
  • pthread_sigmask
    • -
  • pthread_testcancelstate
    • +
  • pthread_setcanceltype
    • +
  • pthread_testcancel
  • pthread_yield
  • puts
  • RAM disk driver
    • diff --git a/sched/pthread/pthread_setcanceltype.c b/sched/pthread/pthread_setcanceltype.c index ca88ea3ddb..0de093cb09 100644 --- a/sched/pthread/pthread_setcanceltype.c +++ b/sched/pthread/pthread_setcanceltype.c @@ -60,7 +60,7 @@ * * The cancelability state and type of any newly created threads, * including the thread in which main() was first invoked, are - * PTHREAD_CANCEL_ASYNCHRONOUS and PTHREAD_CANCEL_DEFERRED respectively. + * PTHREAD_CANCEL_ENABLE and PTHREAD_CANCEL_DEFERRED respectively. * ****************************************************************************/ -- GitLab From 16be9b332ef1db7588fec602023d13d35fb4b7cf Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 9 Dec 2016 15:17:58 -0600 Subject: [PATCH 646/734] More cancellation points --- Documentation/NuttxUserGuide.html | 3 ++- libc/unistd/lib_usleep.c | 20 -------------------- net/socket/accept.c | 17 ++++++++++++++++- net/socket/connect.c | 17 ++++++++++++++++- net/socket/recv.c | 2 ++ net/socket/recvfrom.c | 16 +++++++++++++++- net/socket/send.c | 26 ++++++++++++++++++++++++-- net/socket/sendto.c | 9 ++++++++- 8 files changed, 83 insertions(+), 27 deletions(-) diff --git a/Documentation/NuttxUserGuide.html b/Documentation/NuttxUserGuide.html index 59e1b76f4f..ada2c6d9e1 100644 --- a/Documentation/NuttxUserGuide.html +++ b/Documentation/NuttxUserGuide.html @@ -6180,7 +6180,8 @@ returned to indicate the error:

    The pthread_cleanup_push() function will push the specified cancellation cleanup handler routine onto the calling thread's cancellation cleanup stack. - +

    +

    The cancellation cleanup handler will be popped from the cancellation cleanup stack and invoked with the argument arg when:

    diff --git a/libc/unistd/lib_usleep.c b/libc/unistd/lib_usleep.c index 5b72bbdcdf..4e3d4cdb0c 100644 --- a/libc/unistd/lib_usleep.c +++ b/libc/unistd/lib_usleep.c @@ -43,26 +43,6 @@ #include #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Type Declarations - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/net/socket/accept.c b/net/socket/accept.c index a01f69f6c6..ed6d35fa09 100644 --- a/net/socket/accept.c +++ b/net/socket/accept.c @@ -1,7 +1,7 @@ /**************************************************************************** * net/socket/accept.c * - * Copyright (C) 2007-2012, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2012, 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -48,6 +48,7 @@ #include #include +#include #include #include "tcp/tcp.h" @@ -132,6 +133,10 @@ int psock_accept(FAR struct socket *psock, FAR struct sockaddr *addr, DEBUGASSERT(psock != NULL); + /* Treat as a cancellation point */ + + enter_cancellation_point(); + /* Is the socket a stream? */ if (psock->s_type != SOCK_STREAM) @@ -269,6 +274,8 @@ int psock_accept(FAR struct socket *psock, FAR struct sockaddr *addr, newsock->s_flags |= _SF_CONNECTED; newsock->s_flags &= ~_SF_CLOSED; + + leave_cancellation_point(); return OK; errout_after_accept: @@ -276,6 +283,7 @@ errout_after_accept: errout: set_errno(errcode); + leave_cancellation_point(); return ERROR; } @@ -355,6 +363,10 @@ int accept(int sockfd, FAR struct sockaddr *addr, FAR socklen_t *addrlen) int errcode; int ret; + /* accept() is a cancellation point */ + + enter_cancellation_point(); + /* Verify that the sockfd corresponds to valid, allocated socket */ if (psock == NULL || psock->s_crefs <= 0) @@ -402,9 +414,11 @@ int accept(int sockfd, FAR struct sockaddr *addr, FAR socklen_t *addrlen) /* The errno value has already been set */ sockfd_release(newfd); + leave_cancellation_point(); return ERROR; } + leave_cancellation_point(); return newfd; errout_with_socket: @@ -412,6 +426,7 @@ errout_with_socket: errout: set_errno(errcode); + leave_cancellation_point(); return ERROR; } diff --git a/net/socket/connect.c b/net/socket/connect.c index 6b83184fd9..3bb98d9899 100644 --- a/net/socket/connect.c +++ b/net/socket/connect.c @@ -51,6 +51,7 @@ #include #include +#include #include #include #include @@ -516,6 +517,10 @@ int psock_connect(FAR struct socket *psock, FAR const struct sockaddr *addr, #endif int errcode; + /* Treat as a cancellation point */ + + enter_cancellation_point(); + /* Verify that the psock corresponds to valid, allocated socket */ if (!psock || psock->s_crefs <= 0) @@ -663,10 +668,12 @@ int psock_connect(FAR struct socket *psock, FAR const struct sockaddr *addr, goto errout; } + leave_cancellation_point(); return OK; errout: set_errno(errcode); + leave_cancellation_point(); return ERROR; } @@ -741,13 +748,21 @@ errout: int connect(int sockfd, FAR const struct sockaddr *addr, socklen_t addrlen) { + int ret; + + /* accept() is a cancellation point */ + + enter_cancellation_point(); + /* Get the underlying socket structure */ FAR struct socket *psock = sockfd_socket(sockfd); /* Then let psock_connect() do all of the work */ - return psock_connect(psock, addr, addrlen); + ret = psock_connect(psock, addr, addrlen); + leave_cancellation_point(); + return ret; } #endif /* CONFIG_NET */ diff --git a/net/socket/recv.c b/net/socket/recv.c index 412ed6e0d0..2e590c0b71 100644 --- a/net/socket/recv.c +++ b/net/socket/recv.c @@ -71,6 +71,8 @@ ssize_t recv(int sockfd, FAR void *buf, size_t len, int flags) { + /* recv is a cancellation point, but that can all be handled by recvfrom */ + return recvfrom(sockfd, buf, len, flags, NULL, 0); } diff --git a/net/socket/recvfrom.c b/net/socket/recvfrom.c index e8a029b099..e45bacd032 100644 --- a/net/socket/recvfrom.c +++ b/net/socket/recvfrom.c @@ -57,6 +57,7 @@ #include #include +#include #include #include #include @@ -1851,6 +1852,10 @@ ssize_t psock_recvfrom(FAR struct socket *psock, FAR void *buf, size_t len, ssize_t ret; int errcode; + /* Treat as a cancellation point */ + + enter_cancellation_point(); + /* Verify that non-NULL pointers were passed */ #ifdef CONFIG_DEBUG_FEATURES @@ -2013,10 +2018,12 @@ ssize_t psock_recvfrom(FAR struct socket *psock, FAR void *buf, size_t len, /* Success return */ + leave_cancellation_point(); return ret; errout: set_errno(errcode); + leave_cancellation_point(); return ERROR; } @@ -2076,6 +2083,11 @@ ssize_t recvfrom(int sockfd, FAR void *buf, size_t len, int flags, FAR struct sockaddr *from, FAR socklen_t *fromlen) { FAR struct socket *psock; + ssize_t ret; + + /* recvfrom() is a cancellation point */ + + enter_cancellation_point(); /* Get the underlying socket structure */ @@ -2083,7 +2095,9 @@ ssize_t recvfrom(int sockfd, FAR void *buf, size_t len, int flags, /* Then let psock_recvfrom() do all of the work */ - return psock_recvfrom(psock, buf, len, flags, from, fromlen); + ret = psock_recvfrom(psock, buf, len, flags, from, fromlen); + leave_cancellation_point(); + return ret; } #endif /* CONFIG_NET */ diff --git a/net/socket/send.c b/net/socket/send.c index 60b19ab296..269de0882b 100644 --- a/net/socket/send.c +++ b/net/socket/send.c @@ -1,7 +1,7 @@ /**************************************************************************** * net/socket/send.c * - * Copyright (C) 2007-2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -43,6 +43,8 @@ #include #include +#include + #include "tcp/tcp.h" #include "udp/udp.h" #include "pkt/pkt.h" @@ -122,6 +124,10 @@ ssize_t psock_send(FAR struct socket *psock, FAR const void *buf, size_t len, { int ret; + /* Treat as a cancellation point */ + + enter_cancellation_point(); + switch (psock->s_type) { #if defined(CONFIG_NET_PKT) @@ -192,6 +198,7 @@ ssize_t psock_send(FAR struct socket *psock, FAR const void *buf, size_t len, break; } + leave_cancellation_point(); return ret; } @@ -261,5 +268,20 @@ ssize_t psock_send(FAR struct socket *psock, FAR const void *buf, size_t len, ssize_t send(int sockfd, FAR const void *buf, size_t len, int flags) { - return psock_send(sockfd_socket(sockfd), buf, len, flags); + FAR struct socket *psock; + ssize_t ret; + + /* send() is a cancellation point */ + + enter_cancellation_point(); + + /* Get the underlying socket structure */ + + psock = sockfd_socket(sockfd); + + /* And let psock_send do all of the work */ + + ret = psock_send(psock, buf, len, flags, to, tolen); + leave_cancellation_point(); + return ret; } diff --git a/net/socket/sendto.c b/net/socket/sendto.c index 79eb93e68f..26f88f6bdb 100644 --- a/net/socket/sendto.c +++ b/net/socket/sendto.c @@ -309,6 +309,11 @@ ssize_t sendto(int sockfd, FAR const void *buf, size_t len, int flags, FAR const struct sockaddr *to, socklen_t tolen) { FAR struct socket *psock; + ssize_t ret; + + /* sendto() is a cancellation point */ + + enter_cancellation_point(); /* Get the underlying socket structure */ @@ -316,5 +321,7 @@ ssize_t sendto(int sockfd, FAR const void *buf, size_t len, int flags, /* And let psock_sendto do all of the work */ - return psock_sendto(psock, buf, len, flags, to, tolen); + ret = psock_sendto(psock, buf, len, flags, to, tolen); + leave_cancellation_point(); + return ret; } -- GitLab From 7fce8022c6c84cfddd556f2387910a2d8677652b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 9 Dec 2016 16:50:34 -0600 Subject: [PATCH 647/734] Finishes all cancellation point logic --- TODO | 40 ++++++++++++++++++++++++++- libc/aio/aio_suspend.c | 21 -------------- sched/mqueue/mq_receive.c | 7 +++++ sched/mqueue/mq_send.c | 7 +++++ sched/mqueue/mq_timedreceive.c | 10 +++++++ sched/mqueue/mq_timedsend.c | 10 +++++++ sched/pthread/pthread_condtimedwait.c | 6 ++++ sched/pthread/pthread_condwait.c | 9 +++++- sched/pthread/pthread_join.c | 12 +++++++- sched/semaphore/sem_timedwait.c | 7 +++++ sched/signal/sig_nanosleep.c | 7 +++++ sched/signal/sig_pause.c | 15 ++++++++-- sched/signal/sig_suspend.c | 8 +++++- sched/signal/sig_timedwait.c | 5 ++++ sched/signal/sig_waitinfo.c | 15 +++++++++- 15 files changed, 150 insertions(+), 29 deletions(-) diff --git a/TODO b/TODO index 62839abb7b..802c68b2e8 100644 --- a/TODO +++ b/TODO @@ -14,7 +14,7 @@ nuttx/: (1) Memory Management (mm/) (1) Power Management (drivers/pm) (3) Signals (sched/signal, arch/) - (1) pthreads (sched/pthread) + (2) pthreads (sched/pthread) (0) Message Queues (sched/mqueue) (8) Kernel/Protected Build (3) C++ Support @@ -590,6 +590,44 @@ o pthreads (sched/pthreads) solution. So I discarded a few hours of programming. Not a big loss from the experience I gained." + Title: ISSUES WITH CANCELLATION POINTS + Description: According to POIX cancellation points must occur when a thread is executing + the following functions. There are some execptions as noted: + + accept() mq_timedsend() NA putpmsg() sigtimedwait() + -4 aio_suspend() NA msgrcv() pwrite() NA sigwait() + NA clock_nanosleep() NA msgsnd() read() sigwaitinfo() + close() NA msync() NA readv() -1 sleep() + connect() nanosleep() recv() -2 system() + OK creat() open() recvfrom() NA tcdrain() + fcntl() pause() NA recvmsg() -1 usleep() + NA fdatasync() poll() select() OK wait() + fsync() pread() sem_timedwait() waitid() + NA getmsg() NA pselect() sem_wait() waitpid() + NA getpmsg() pthread_cond_timedwait() send() write() + NA lockf() pthread_cond_wait() NA sendmsg() NA writev() + mq_receive() pthread_join() sendto() + mq_send() pthread_testcancel() -3 sigpause() + mq_timedreceive() NA putmsg() sigsuspend() + + NA Not supported + OK Doesn't need instrumentation. Handled by lower level calls. + -n See note n + + NOTE 1: sleep() and usleep() are user-space functions in the C library and cannot + serve as cancellation points. They are, however, simple wrappers around nanosleep + which is a true cancellation point. + NOTE 2: system() is actually implemented in apps/ as part of NSH. It cannot be + a cancellation point either. + NOTE 3: sigpause() is a user-space function in the C library and cannot serve as + cancellation points. It is, however, a simple wrapper around sigsuspend() + which is a true cancellation point. + NOTE 4: aio_suspend() is a user-space function in the C library and cannot serve as + cancellation points. It does call around sigtimedwait() which is a true cancellation + point. + Status: Not really open. This is just the way it is. + Priority: Nothing additional is planned. + o Message Queues (sched/mqueue) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/libc/aio/aio_suspend.c b/libc/aio/aio_suspend.c index 948462cd90..34b7e4a72b 100644 --- a/libc/aio/aio_suspend.c +++ b/libc/aio/aio_suspend.c @@ -47,27 +47,6 @@ #ifdef CONFIG_FS_AIO -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ -/* Configuration ************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/sched/mqueue/mq_receive.c b/sched/mqueue/mq_receive.c index 4fed3b5afd..a7fa225541 100644 --- a/sched/mqueue/mq_receive.c +++ b/sched/mqueue/mq_receive.c @@ -47,6 +47,7 @@ #include #include +#include #include "mqueue/mqueue.h" @@ -103,12 +104,17 @@ ssize_t mq_receive(mqd_t mqdes, FAR char *msg, size_t msglen, DEBUGASSERT(up_interrupt_context() == false); + /* mq_receive() is a cancellation point */ + + enter_cancellation_point(); + /* Verify the input parameters and, in case of an error, set * errno appropriately. */ if (mq_verifyreceive(mqdes, msg, msglen) != OK) { + leave_cancellation_point(); return ERROR; } @@ -145,5 +151,6 @@ ssize_t mq_receive(mqd_t mqdes, FAR char *msg, size_t msglen, } sched_unlock(); + leave_cancellation_point(); return ret; } diff --git a/sched/mqueue/mq_send.c b/sched/mqueue/mq_send.c index 12ce2b85c1..045a57eca1 100644 --- a/sched/mqueue/mq_send.c +++ b/sched/mqueue/mq_send.c @@ -46,6 +46,7 @@ #include #include +#include #include "mqueue/mqueue.h" @@ -103,12 +104,17 @@ int mq_send(mqd_t mqdes, FAR const char *msg, size_t msglen, int prio) irqstate_t flags; int ret = ERROR; + /* mq_send() is a cancellation point */ + + enter_cancellation_point(); + /* Verify the input parameters -- setting errno appropriately * on any failures to verify. */ if (mq_verifysend(mqdes, msg, msglen, prio) != OK) { + leave_cancellation_point(); return ERROR; } @@ -177,5 +183,6 @@ int mq_send(mqd_t mqdes, FAR const char *msg, size_t msglen, int prio) } sched_unlock(); + leave_cancellation_point(); return ret; } diff --git a/sched/mqueue/mq_timedreceive.c b/sched/mqueue/mq_timedreceive.c index b5bb100b89..7b97d65294 100644 --- a/sched/mqueue/mq_timedreceive.c +++ b/sched/mqueue/mq_timedreceive.c @@ -50,6 +50,7 @@ #include #include #include +#include #include "sched/sched.h" #include "clock/clock.h" @@ -174,18 +175,24 @@ ssize_t mq_timedreceive(mqd_t mqdes, FAR char *msg, size_t msglen, DEBUGASSERT(up_interrupt_context() == false && rtcb->waitdog == NULL); + /* mq_timedreceive() is a cancellation point */ + + enter_cancellation_point(); + /* Verify the input parameters and, in case of an error, set * errno appropriately. */ if (mq_verifyreceive(mqdes, msg, msglen) != OK) { + leave_cancellation_point(); return ERROR; } if (!abstime || abstime->tv_nsec < 0 || abstime->tv_nsec >= 1000000000) { set_errno(EINVAL); + leave_cancellation_point(); return ERROR; } @@ -198,6 +205,7 @@ ssize_t mq_timedreceive(mqd_t mqdes, FAR char *msg, size_t msglen, if (!rtcb->waitdog) { set_errno(EINVAL); + leave_cancellation_point(); return ERROR; } @@ -250,6 +258,7 @@ ssize_t mq_timedreceive(mqd_t mqdes, FAR char *msg, size_t msglen, rtcb->waitdog = NULL; set_errno(result); + leave_cancellation_point(); return ERROR; } @@ -288,5 +297,6 @@ ssize_t mq_timedreceive(mqd_t mqdes, FAR char *msg, size_t msglen, sched_unlock(); wd_delete(rtcb->waitdog); rtcb->waitdog = NULL; + leave_cancellation_point(); return ret; } diff --git a/sched/mqueue/mq_timedsend.c b/sched/mqueue/mq_timedsend.c index 0b82fb8edb..ccd18c69a1 100644 --- a/sched/mqueue/mq_timedsend.c +++ b/sched/mqueue/mq_timedsend.c @@ -50,6 +50,7 @@ #include #include #include +#include #include "clock/clock.h" #include "sched/sched.h" @@ -178,6 +179,10 @@ int mq_timedsend(mqd_t mqdes, FAR const char *msg, size_t msglen, int prio, DEBUGASSERT(up_interrupt_context() == false && rtcb->waitdog == NULL); + /* mq_timedsend() is a cancellation point */ + + enter_cancellation_point(); + /* Verify the input parameters -- setting errno appropriately * on any failures to verify. */ @@ -186,6 +191,7 @@ int mq_timedsend(mqd_t mqdes, FAR const char *msg, size_t msglen, int prio, { /* mq_verifysend() will set the errno appropriately */ + leave_cancellation_point(); return ERROR; } @@ -199,6 +205,7 @@ int mq_timedsend(mqd_t mqdes, FAR const char *msg, size_t msglen, int prio, */ set_errno(ENOMEM); + leave_cancellation_point(); return ERROR; } @@ -229,6 +236,7 @@ int mq_timedsend(mqd_t mqdes, FAR const char *msg, size_t msglen, int prio, ret = mq_dosend(mqdes, mqmsg, msg, msglen, prio); sched_unlock(); + leave_cancellation_point(); return ret; } @@ -320,6 +328,7 @@ int mq_timedsend(mqd_t mqdes, FAR const char *msg, size_t msglen, int prio, sched_unlock(); wd_delete(rtcb->waitdog); rtcb->waitdog = NULL; + leave_cancellation_point(); return ret; /* Exit here with (1) the scheduler locked, (2) a message allocated, (3) a @@ -341,5 +350,6 @@ errout_with_mqmsg: sched_unlock(); set_errno(result); + leave_cancellation_point(); return ERROR; } diff --git a/sched/pthread/pthread_condtimedwait.c b/sched/pthread/pthread_condtimedwait.c index 7950c5b5fc..d9756a6217 100644 --- a/sched/pthread/pthread_condtimedwait.c +++ b/sched/pthread/pthread_condtimedwait.c @@ -51,6 +51,7 @@ #include #include +#include #include "sched/sched.h" #include "pthread/pthread.h" @@ -178,6 +179,10 @@ int pthread_cond_timedwait(FAR pthread_cond_t *cond, FAR pthread_mutex_t *mutex, DEBUGASSERT(rtcb->waitdog == NULL); + /* pthread_cond_timedwait() is a cancellation point */ + + enter_cancellation_point(); + /* Make sure that non-NULL references were provided. */ if (!cond || !mutex) @@ -338,6 +343,7 @@ int pthread_cond_timedwait(FAR pthread_cond_t *cond, FAR pthread_mutex_t *mutex, } } + leave_cancellation_point(); sinfo("Returning %d\n", ret); return ret; } diff --git a/sched/pthread/pthread_condwait.c b/sched/pthread/pthread_condwait.c index a9ad2ba91c..65eadfc131 100644 --- a/sched/pthread/pthread_condwait.c +++ b/sched/pthread/pthread_condwait.c @@ -1,7 +1,7 @@ /**************************************************************************** * sched/pthread/pthread_condwait.c * - * Copyright (C) 2007-2009, 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -45,6 +45,8 @@ #include #include +#include + #include "pthread/pthread.h" /**************************************************************************** @@ -73,6 +75,10 @@ int pthread_cond_wait(FAR pthread_cond_t *cond, FAR pthread_mutex_t *mutex) sinfo("cond=0x%p mutex=0x%p\n", cond, mutex); + /* pthread_cond_wait() is a cancellation point */ + + enter_cancellation_point(); + /* Make sure that non-NULL references were provided. */ if (!cond || !mutex) @@ -111,6 +117,7 @@ int pthread_cond_wait(FAR pthread_cond_t *cond, FAR pthread_mutex_t *mutex) } } + leave_cancellation_point(); sinfo("Returning %d\n", ret); return ret; } diff --git a/sched/pthread/pthread_join.c b/sched/pthread/pthread_join.c index 9b73fd4268..2ea88ee8f8 100644 --- a/sched/pthread/pthread_join.c +++ b/sched/pthread/pthread_join.c @@ -1,7 +1,7 @@ /**************************************************************************** * sched/pthread/pthread_join.c * - * Copyright (C) 2007, 2008, 2011, 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2007, 2008, 2011, 2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -37,12 +37,16 @@ * Included Files ****************************************************************************/ +#include + #include #include #include #include #include +#include + #include "sched/sched.h" #include "group/group.h" #include "pthread/pthread.h" @@ -90,12 +94,17 @@ int pthread_join(pthread_t thread, FAR pthread_addr_t *pexit_value) sinfo("thread=%d group=%p\n", thread, group); DEBUGASSERT(group); + /* pthread_join() is a cancellation point */ + + enter_cancellation_point(); + /* First make sure that this is not an attempt to join to * ourself. */ if ((pid_t)thread == getpid()) { + leave_cancellation_point(); return EDEADLK; } @@ -230,6 +239,7 @@ int pthread_join(pthread_t thread, FAR pthread_addr_t *pexit_value) ret = OK; } + leave_cancellation_point(); sinfo("Returning %d\n", ret); return ret; } diff --git a/sched/semaphore/sem_timedwait.c b/sched/semaphore/sem_timedwait.c index 81e7a79d50..26cfa4db99 100644 --- a/sched/semaphore/sem_timedwait.c +++ b/sched/semaphore/sem_timedwait.c @@ -49,6 +49,7 @@ #include #include #include +#include #include "sched/sched.h" #include "clock/clock.h" @@ -103,6 +104,10 @@ int sem_timedwait(FAR sem_t *sem, FAR const struct timespec *abstime) DEBUGASSERT(up_interrupt_context() == false && rtcb->waitdog == NULL); + /* sem_timedwait() is a cancellation point */ + + enter_cancellation_point(); + /* Verify the input parameters and, in case of an error, set * errno appropriately. */ @@ -209,6 +214,7 @@ success_with_irqdisabled: leave_critical_section(flags); wd_delete(rtcb->waitdog); rtcb->waitdog = NULL; + leave_cancellation_point(); return OK; /* Error exits */ @@ -220,5 +226,6 @@ errout_with_irqdisabled: errout: set_errno(errcode); + leave_cancellation_point(); return ERROR; } diff --git a/sched/signal/sig_nanosleep.c b/sched/signal/sig_nanosleep.c index 4a492f0c85..e37d9142b0 100644 --- a/sched/signal/sig_nanosleep.c +++ b/sched/signal/sig_nanosleep.c @@ -46,6 +46,7 @@ #include #include +#include #include "clock/clock.h" @@ -112,6 +113,10 @@ int nanosleep(FAR const struct timespec *rqtp, FAR struct timespec *rmtp) int ret; #endif + /* nanosleep() is a cancellation point */ + + enter_cancellation_point(); + if (!rqtp || rqtp->tv_nsec < 0 || rqtp->tv_nsec >= 1000000000) { errval = EINVAL; @@ -154,6 +159,7 @@ int nanosleep(FAR const struct timespec *rqtp, FAR struct timespec *rmtp) /* The timeout "error" is the normal, successful result */ leave_critical_section(flags); + leave_cancellation_point(); return OK; } @@ -203,5 +209,6 @@ int nanosleep(FAR const struct timespec *rqtp, FAR struct timespec *rmtp) errout: set_errno(errval); + leave_cancellation_point(); return ERROR; } diff --git a/sched/signal/sig_pause.c b/sched/signal/sig_pause.c index 80fc712cb7..1aa48b6004 100644 --- a/sched/signal/sig_pause.c +++ b/sched/signal/sig_pause.c @@ -1,7 +1,7 @@ /**************************************************************************** * sched/signal/sig_pause.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -42,6 +42,8 @@ #include #include +#include + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -72,8 +74,13 @@ int pause(void) { - sigset_t set; struct siginfo value; + sigset_t set; + int ret; + + /* pause() is a cancellation point */ + + enter_cancellation_point(); /* Set up for the sleep. Using the empty set means that we are not * waiting for any particular signal. However, any unmasked signal @@ -86,5 +93,7 @@ int pause(void) * meaning that some unblocked signal was caught. */ - return sigwaitinfo(&set, &value); + ret = sigwaitinfo(&set, &value); + leave_cancellation_point(); + return ret; } diff --git a/sched/signal/sig_suspend.c b/sched/signal/sig_suspend.c index d3a4a9ba71..a717d76ce2 100644 --- a/sched/signal/sig_suspend.c +++ b/sched/signal/sig_suspend.c @@ -46,6 +46,7 @@ #include #include +#include #include "sched/sched.h" #include "signal/signal.h" @@ -98,6 +99,10 @@ int sigsuspend(FAR const sigset_t *set) irqstate_t flags; int unblocksigno; + /* sigsuspend() is a cancellation point */ + + enter_cancellation_point(); + /* Several operations must be performed below: We must determine if any * signal is pending and, if not, wait for the signal. Since signals can * be posted from the interrupt level, there is a race condition that @@ -154,5 +159,6 @@ int sigsuspend(FAR const sigset_t *set) } sched_unlock(); - return ERROR; + leave_cancellation_point(); + return ERROR; /* ??REVISIT: Always returns ERROR?? */ } diff --git a/sched/signal/sig_timedwait.c b/sched/signal/sig_timedwait.c index 687884dcf9..9ac4062beb 100644 --- a/sched/signal/sig_timedwait.c +++ b/sched/signal/sig_timedwait.c @@ -52,6 +52,7 @@ #include #include #include +#include #include "sched/sched.h" #include "signal/signal.h" @@ -173,6 +174,9 @@ int sigtimedwait(FAR const sigset_t *set, FAR struct siginfo *info, DEBUGASSERT(rtcb->waitdog == NULL); + /* sigtimedwait() is a cancellation point */ + + enter_cancellation_point(); sched_lock(); /* Not necessary */ /* Several operations must be performed below: We must determine if any @@ -343,5 +347,6 @@ int sigtimedwait(FAR const sigset_t *set, FAR struct siginfo *info, } sched_unlock(); + leave_cancellation_point(); return ret; } diff --git a/sched/signal/sig_waitinfo.c b/sched/signal/sig_waitinfo.c index d271dc9884..470624c338 100644 --- a/sched/signal/sig_waitinfo.c +++ b/sched/signal/sig_waitinfo.c @@ -38,8 +38,11 @@ ****************************************************************************/ #include + #include +#include + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -65,5 +68,15 @@ int sigwaitinfo(FAR const sigset_t *set, FAR struct siginfo *info) { - return sigtimedwait(set, info, NULL); + int ret; + + /* sigwaitinfo() is a cancellation point */ + + enter_cancellation_point(); + + /* Just a wrapper around sigtimedwait() */ + + ret = sigtimedwait(set, info, NULL); + leave_cancellation_point(); + return ret; } -- GitLab From b07964461e478d2f4970ac05479c47aa5855ce10 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 9 Dec 2016 16:53:29 -0600 Subject: [PATCH 648/734] pthread_mutex_destroy(): Fix an error in destorynig a mutex which can occur after a pthread has been canceled while holding the mutex. --- sched/pthread/pthread_mutexdestroy.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/sched/pthread/pthread_mutexdestroy.c b/sched/pthread/pthread_mutexdestroy.c index a6b945f670..bea9ba7c38 100644 --- a/sched/pthread/pthread_mutexdestroy.c +++ b/sched/pthread/pthread_mutexdestroy.c @@ -41,6 +41,7 @@ #include #include +#include #include #include #include @@ -90,7 +91,29 @@ int pthread_mutex_destroy(FAR pthread_mutex_t *mutex) if (mutex->pid != -1) { - ret = EBUSY; +#ifndef CONFIG_DISABLE_SIGNALS + /* Verify that the PID still exists. We may be destroying the + * mutex after cancelling a pthread and the mutex may have been + * in a bad state owned by the dead pthread. + */ + + ret = kill(mutex->pid, 0); + if (ret < 0) + { + /* That thread associated with the PID no longer exists */ + + mutex->pid = -1; + + /* Destroy the semaphore */ + + status = sem_destroy((FAR sem_t *)&mutex->sem); + ret = (status != OK) ? get_errno() : OK; + } + else +#endif + { + ret = EBUSY; + } } else { @@ -99,7 +122,7 @@ int pthread_mutex_destroy(FAR pthread_mutex_t *mutex) status = sem_destroy((FAR sem_t *)&mutex->sem); if (status != OK) { - ret = EINVAL; + ret = get_errno(); } } -- GitLab From 0832b11df01681f8c8fc33e49337905e8cb1b161 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 6 Dec 2016 13:41:35 -0600 Subject: [PATCH 649/734] Ooops... one too many righ parentheses. --- configs/olimex-stm32-p107/src/stm32_can.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/olimex-stm32-p107/src/stm32_can.c b/configs/olimex-stm32-p107/src/stm32_can.c index 5402f7d44a..9889f836b2 100644 --- a/configs/olimex-stm32-p107/src/stm32_can.c +++ b/configs/olimex-stm32-p107/src/stm32_can.c @@ -84,7 +84,7 @@ int stm32_can_setup(void) { -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) struct can_dev_s *can; int ret; -- GitLab From 78cdc9f113a189711becacd2c53b98b5de67a032 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 9 Dec 2016 16:59:10 -0600 Subject: [PATCH 650/734] Fix a typo in a debug assertion. --- sched/pthread/pthread_cancel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sched/pthread/pthread_cancel.c b/sched/pthread/pthread_cancel.c index 5b6fa04db8..b8f89ead30 100644 --- a/sched/pthread/pthread_cancel.c +++ b/sched/pthread/pthread_cancel.c @@ -77,7 +77,7 @@ int pthread_cancel(pthread_t thread) return ESRCH; } - DEBUGASSERT((tcb-cmn.flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD); + DEBUGASSERT((tcb->cmn.flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD); /* Check to see if this thread has the non-cancelable bit set in its * flags. Suppress context changes for a bit so that the flags are stable. -- GitLab From 05f61def6a3cec79a994afa62a138d2eca413626 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 9 Dec 2016 17:02:27 -0600 Subject: [PATCH 651/734] Fix warning and link error due to missing header file. --- fs/vfs/fs_select.c | 1 + 1 file changed, 1 insertion(+) diff --git a/fs/vfs/fs_select.c b/fs/vfs/fs_select.c index 8a9cd9ae60..660607439d 100644 --- a/fs/vfs/fs_select.c +++ b/fs/vfs/fs_select.c @@ -49,6 +49,7 @@ #include #include +#include #include #include "inode/inode.h" -- GitLab From 113d8bdccade6ba762f0ff71978b96040d585e92 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 9 Dec 2016 17:10:59 -0600 Subject: [PATCH 652/734] Fix some SMP-related compilation errors --- arch/arm/src/sam34/sam4cm_cpustart.c | 1 + sched/init/os_start.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/sam34/sam4cm_cpustart.c b/arch/arm/src/sam34/sam4cm_cpustart.c index 7a5c62f0fc..f8544abf7f 100644 --- a/arch/arm/src/sam34/sam4cm_cpustart.c +++ b/arch/arm/src/sam34/sam4cm_cpustart.c @@ -44,6 +44,7 @@ #include #include #include +#include #include #include diff --git a/sched/init/os_start.c b/sched/init/os_start.c index 5b8236b56a..2d8eb2e6e1 100644 --- a/sched/init/os_start.c +++ b/sched/init/os_start.c @@ -470,7 +470,7 @@ void os_start(void) */ #ifdef CONFIG_SMP - g_idletcb[cpu].cmn.flags = (TCB_FLAG_TTYPE_KERNEL TCB_FLAG_NONCANCELABLE | + g_idletcb[cpu].cmn.flags = (TCB_FLAG_TTYPE_KERNEL | TCB_FLAG_NONCANCELABLE | TCB_FLAG_CPU_LOCKED); g_idletcb[cpu].cmn.cpu = cpu; #else -- GitLab From a76e729b0d7e50579b2e9ea8cdf226059cf98301 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 9 Dec 2016 17:20:57 -0600 Subject: [PATCH 653/734] Trivial, cosmetic --- sched/pthread/pthread_condwait.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sched/pthread/pthread_condwait.c b/sched/pthread/pthread_condwait.c index 65eadfc131..631e6c2679 100644 --- a/sched/pthread/pthread_condwait.c +++ b/sched/pthread/pthread_condwait.c @@ -81,7 +81,7 @@ int pthread_cond_wait(FAR pthread_cond_t *cond, FAR pthread_mutex_t *mutex) /* Make sure that non-NULL references were provided. */ - if (!cond || !mutex) + if (cond == NULL || mutex == NULL) { ret = EINVAL; } @@ -111,7 +111,7 @@ int pthread_cond_wait(FAR pthread_cond_t *cond, FAR pthread_mutex_t *mutex) sinfo("Reacquire mutex...\n"); ret |= pthread_takesemaphore((FAR sem_t *)&mutex->sem); - if (!ret) + if (ret == OK) { mutex->pid = getpid(); } -- GitLab From 64ffd89ee1c05c7a0033373b3237c0b2de636a4b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 9 Dec 2016 17:25:00 -0600 Subject: [PATCH 654/734] Another missing header file inclusion. --- net/socket/sendto.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/socket/sendto.c b/net/socket/sendto.c index 26f88f6bdb..d1236efb0e 100644 --- a/net/socket/sendto.c +++ b/net/socket/sendto.c @@ -45,6 +45,7 @@ #include #include +#include #include #include "udp/udp.h" -- GitLab From 559a027229df0f120f157da05128e739e0092dc0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 9 Dec 2016 17:38:18 -0600 Subject: [PATCH 655/734] Update TODO list --- TODO | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/TODO b/TODO index 802c68b2e8..3dcfc0365f 100644 --- a/TODO +++ b/TODO @@ -22,7 +22,7 @@ nuttx/: (12) Network (net/, drivers/net) (4) USB (drivers/usbdev, drivers/usbhost) (0) Other drivers (drivers/) - (11) Libraries (libc/, libm/) + (12) Libraries (libc/, libm/) (11) File system/Generic drivers (fs/, drivers/) (9) Graphics Subsystem (graphics/) (2) Build system / Toolchains @@ -1522,10 +1522,17 @@ o Libraries (libc/, libm/) 2016-07-30: Numerous fixes and performance improvements from David Alessio. -Status: Open -Priority: Low for casual users but clearly high if you need care about + Status: Open + Priority: Low for casual users but clearly high if you need care about these incorrect corner case behaviors in the math libraries. + Title: Repartition libc functionality. + Description: There are many things implemented within the kernel (for example + under sched/pthread) that probably should be migrated in the + C library where it belongs. + Status: Open + Priority: Low + o File system / Generic drivers (fs/, drivers/) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -- GitLab From 38b9ab09d92e27ee860e125471da7ba43d48ff2b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 9 Dec 2016 17:27:24 -0600 Subject: [PATCH 656/734] Fix copy-and-paste gone wrong. --- net/socket/send.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/socket/send.c b/net/socket/send.c index 269de0882b..7f97eac7cc 100644 --- a/net/socket/send.c +++ b/net/socket/send.c @@ -281,7 +281,7 @@ ssize_t send(int sockfd, FAR const void *buf, size_t len, int flags) /* And let psock_send do all of the work */ - ret = psock_send(psock, buf, len, flags, to, tolen); + ret = psock_send(psock, buf, len, flags); leave_cancellation_point(); return ret; } -- GitLab From 018eb7c1d27dee0691b655976022cbdb7475c892 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 9 Dec 2016 17:44:37 -0600 Subject: [PATCH 657/734] Cancellation points no longer depend on EXPERIMENTAL --- sched/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/sched/Kconfig b/sched/Kconfig index d3d9230d6e..ecfe78addd 100644 --- a/sched/Kconfig +++ b/sched/Kconfig @@ -249,7 +249,6 @@ menu "Tasks and Scheduling" config SPINLOCK bool "Support Spinlocks" default n - depends on EXPERIMENTAL ---help--- Enables suppport for spinlocks. Spinlocks are current used only for SMP suppport. @@ -563,7 +562,6 @@ endmenu # Pthread Options config CANCELLATION_POINTS bool "Cancellation points" default n - depends on EXPERIMENTAL ---help--- Enable POSIX cancellation points for pthread_cancel(). If selected, cancellation points will also used with the () task_delete() API even if -- GitLab From 03a58b2ebcc51de60cfdd1865f2cab2a7bd17fea Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 9 Dec 2016 18:12:23 -0600 Subject: [PATCH 658/734] write(): Fix a misplaced #endif --- fs/vfs/fs_write.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/vfs/fs_write.c b/fs/vfs/fs_write.c index 80f828731d..4d0311fcfe 100644 --- a/fs/vfs/fs_write.c +++ b/fs/vfs/fs_write.c @@ -209,8 +209,8 @@ ssize_t write(int fd, FAR const void *buf, size_t nbytes) ret = file_write(filep, buf, nbytes); } -#endif } +#endif leave_cancellation_point(); return ret; -- GitLab From a0f567f4a30375b809224cdea87ed9b6b95786e5 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 9 Dec 2016 18:39:40 -0600 Subject: [PATCH 659/734] Update TODO, cosmetic changes, spelling -- US English spells it canceled and canceling vs cancelled and cancelling. No idea why. --- TODO | 30 ++++++++++++++-------------- fs/aio/aio_cancel.c | 22 ++++++++++---------- fs/aio/aio_read.c | 4 ++-- fs/aio/aio_write.c | 4 ++-- fs/mount/fs_automount.c | 2 +- sched/pthread/pthread_condwait.c | 6 +++++- sched/pthread/pthread_mutexdestroy.c | 4 ++-- 7 files changed, 38 insertions(+), 34 deletions(-) diff --git a/TODO b/TODO index 3dcfc0365f..e330d46a95 100644 --- a/TODO +++ b/TODO @@ -595,34 +595,34 @@ o pthreads (sched/pthreads) the following functions. There are some execptions as noted: accept() mq_timedsend() NA putpmsg() sigtimedwait() - -4 aio_suspend() NA msgrcv() pwrite() NA sigwait() + 04 aio_suspend() NA msgrcv() pwrite() NA sigwait() NA clock_nanosleep() NA msgsnd() read() sigwaitinfo() - close() NA msync() NA readv() -1 sleep() - connect() nanosleep() recv() -2 system() - OK creat() open() recvfrom() NA tcdrain() - fcntl() pause() NA recvmsg() -1 usleep() - NA fdatasync() poll() select() OK wait() + close() NA msync() NA readv() 01 sleep() + connect() nanosleep() recv() 02 system() + -- creat() open() recvfrom() NA tcdrain() + fcntl() pause() NA recvmsg() 01 usleep() + NA fdatasync() poll() select() -- wait() fsync() pread() sem_timedwait() waitid() NA getmsg() NA pselect() sem_wait() waitpid() NA getpmsg() pthread_cond_timedwait() send() write() NA lockf() pthread_cond_wait() NA sendmsg() NA writev() mq_receive() pthread_join() sendto() - mq_send() pthread_testcancel() -3 sigpause() + mq_send() pthread_testcancel() 03 sigpause() mq_timedreceive() NA putmsg() sigsuspend() - NA Not supported - OK Doesn't need instrumentation. Handled by lower level calls. - -n See note n + NA Not supported + -- Doesn't need instrumentation. Handled by lower level calls. + nn See note nn - NOTE 1: sleep() and usleep() are user-space functions in the C library and cannot + NOTE 01: sleep() and usleep() are user-space functions in the C library and cannot serve as cancellation points. They are, however, simple wrappers around nanosleep which is a true cancellation point. - NOTE 2: system() is actually implemented in apps/ as part of NSH. It cannot be + NOTE 02: system() is actually implemented in apps/ as part of NSH. It cannot be a cancellation point either. - NOTE 3: sigpause() is a user-space function in the C library and cannot serve as + NOTE 03: sigpause() is a user-space function in the C library and cannot serve as cancellation points. It is, however, a simple wrapper around sigsuspend() which is a true cancellation point. - NOTE 4: aio_suspend() is a user-space function in the C library and cannot serve as + NOTE 04: aio_suspend() is a user-space function in the C library and cannot serve as cancellation points. It does call around sigtimedwait() which is a true cancellation point. Status: Not really open. This is just the way it is. @@ -1530,7 +1530,7 @@ o Libraries (libc/, libm/) Description: There are many things implemented within the kernel (for example under sched/pthread) that probably should be migrated in the C library where it belongs. - Status: Open + Status: Ope Priority: Low o File system / Generic drivers (fs/, drivers/) diff --git a/fs/aio/aio_cancel.c b/fs/aio/aio_cancel.c index bdd4ba463a..aa575fdb8b 100644 --- a/fs/aio/aio_cancel.c +++ b/fs/aio/aio_cancel.c @@ -61,30 +61,30 @@ * The aio_cancel() function attempts to cancel one or more asynchronous * I/O requests currently outstanding against file descriptor 'fildes'. * The aiocbp argument points to the asynchronous I/O control block for - * a particular request to be cancelled. If aiocbp is NULL, then all + * a particular request to be canceled. If aiocbp is NULL, then all * outstanding cancelable asynchronous I/O requests against fildes will - * be cancelled. + * be canceled. * * Normal asynchronous notification will occur for asynchronous I/O - * operations that are successfully cancelled. If there are requests that - * cannot be cancelled, then the normal asynchronous completion process + * operations that are successfully canceled. If there are requests that + * cannot be canceled, then the normal asynchronous completion process * will take place for those requests when they are completed. * - * For requested operations that are successfully cancelled, the associated + * For requested operations that are successfully canceled, the associated * error status will be set to ECANCELED and the return status will be -1. - * For requested operations that are not successfully cancelled, the aiocbp + * For requested operations that are not successfully canceled, the aiocbp * will not be modified by aio_cancel(). * * Input Parameters: * fildes - Not used in this implementation * aiocbp - Points to the asynchronous I/O control block for a particular - * request to be cancelled. + * request to be canceled. * * Returned Value: * The aio_cancel() function will return the value AIO_CANCELED if the - * requested operation(s) were cancelled. The value AIO_NOTCANCELED will + * requested operation(s) were canceled. The value AIO_NOTCANCELED will * be returned if at least one of the requested operation(s) cannot be - * cancelled because it is in progress. In this case, the state of the + * canceled because it is in progress. In this case, the state of the * other operations, if any, referenced in the call to aio_cancel() is * not indicated by the return value of aio_cancel(). The application * may determine the state of affairs for these operations by using @@ -133,7 +133,7 @@ int aio_cancel(int fildes, FAR struct aiocb *aiocbp) * possibilities:* (1) the work has already been started and * is no longer queued, or (2) the work has not been started * and is still in the work queue. Only the second case can - * be cancelled. work_cancel() will return -ENOENT in the + * be canceled. work_cancel() will return -ENOENT in the * first case. */ @@ -177,7 +177,7 @@ int aio_cancel(int fildes, FAR struct aiocb *aiocbp) * possibilities:* (1) the work has already been started and * is no longer queued, or (2) the work has not been started * and is still in the work queue. Only the second case can - * be cancelled. work_cancel() will return -ENOENT in the + * be canceled. work_cancel() will return -ENOENT in the * first case. */ diff --git a/fs/aio/aio_read.c b/fs/aio/aio_read.c index 6d261ec7d8..462c5ddd26 100644 --- a/fs/aio/aio_read.c +++ b/fs/aio/aio_read.c @@ -226,7 +226,7 @@ static void aio_read_worker(FAR void *arg) * aiocbp->aio_nbytes is an invalid value. * * In the case that the aio_read() successfully queues the I/O operation - * but the operation is subsequently cancelled or encounters an error, the + * but the operation is subsequently canceled or encounters an error, the * return status of the asynchronous operation is one of the values * normally returned by the read() function call. In addition, the error * status of the asynchronous operation is set to one of the error @@ -235,7 +235,7 @@ static void aio_read_worker(FAR void *arg) * * EBADF - The aiocbp->aio_fildes argument is not a valid file descriptor * open for reading. - * ECANCELED - The requested I/O was cancelled before the I/O completed + * ECANCELED - The requested I/O was canceled before the I/O completed * due to an explicit aio_cancel() request. * EINVAL - The file offset value implied by aiocbp->aio_offset would be * invalid. diff --git a/fs/aio/aio_write.c b/fs/aio/aio_write.c index 3d20b2dd93..0aab19e7cb 100644 --- a/fs/aio/aio_write.c +++ b/fs/aio/aio_write.c @@ -279,7 +279,7 @@ errout: * aiocbp->aio_nbytes is an invalid value. * * In the case that the aio_write() successfully queues the I/O operation - * but the operation is subsequently cancelled or encounters an error, the + * but the operation is subsequently canceled or encounters an error, the * return status of the asynchronous operation is one of the values * normally returned by the write() function call. In addition, the error * status of the asynchronous operation is set to one of the error @@ -290,7 +290,7 @@ errout: * open for writing. * EINVAL - The file offset value implied by aiocbp->aio_offset would be * invalid. - * ECANCELED - The requested I/O was cancelled before the I/O completed + * ECANCELED - The requested I/O was canceled before the I/O completed * due to an explicit aio_cancel() request. * * The following condition may be detected synchronously or asynchronously: diff --git a/fs/mount/fs_automount.c b/fs/mount/fs_automount.c index 1bee61d7f5..47bc9c0118 100644 --- a/fs/mount/fs_automount.c +++ b/fs/mount/fs_automount.c @@ -485,7 +485,7 @@ static int automount_interrupt(FAR const struct automount_lower_s *lower, /* Queue work to occur after a delay. The delays performs debouncing: * If the insertion/removal detection logic has "chatter", then we may * receive this interrupt numerous times. Each time, the previous work - * will be cancelled (above) and the new work will scheduled with the + * will be canceled (above) and the new work will scheduled with the * delay. So the final mount operation will not be performed until the * insertion state is stable for that delay. */ diff --git a/sched/pthread/pthread_condwait.c b/sched/pthread/pthread_condwait.c index 631e6c2679..647313dc66 100644 --- a/sched/pthread/pthread_condwait.c +++ b/sched/pthread/pthread_condwait.c @@ -107,7 +107,11 @@ int pthread_cond_wait(FAR pthread_cond_t *cond, FAR pthread_mutex_t *mutex) ret |= pthread_takesemaphore((FAR sem_t *)&cond->sem); sched_unlock(); - /* Reacquire the mutex */ + /* Reacquire the mutex. + * + * REVISIT: When cancellation points are enabled, we will almost + * certainly hold the mutex when the pthread is canceled. + */ sinfo("Reacquire mutex...\n"); ret |= pthread_takesemaphore((FAR sem_t *)&mutex->sem); diff --git a/sched/pthread/pthread_mutexdestroy.c b/sched/pthread/pthread_mutexdestroy.c index bea9ba7c38..8bab62c474 100644 --- a/sched/pthread/pthread_mutexdestroy.c +++ b/sched/pthread/pthread_mutexdestroy.c @@ -75,7 +75,7 @@ int pthread_mutex_destroy(FAR pthread_mutex_t *mutex) sinfo("mutex=0x%p\n", mutex); - if (!mutex) + if (mutex == NULL) { ret = EINVAL; } @@ -100,7 +100,7 @@ int pthread_mutex_destroy(FAR pthread_mutex_t *mutex) ret = kill(mutex->pid, 0); if (ret < 0) { - /* That thread associated with the PID no longer exists */ + /* The thread associated with the PID no longer exists */ mutex->pid = -1; -- GitLab From 1b2135a90a6d1d082d67910d507abb9fd492b672 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 10 Dec 2016 07:12:11 -0600 Subject: [PATCH 660/734] Add pthread_setcanceltype() and pthread_testcancel() as system calls. --- TODO | 13 ++++++++++++- include/sys/syscall.h | 18 ++++++++++-------- syscall/syscall.csv | 2 ++ syscall/syscall_lookup.h | 2 ++ syscall/syscall_stublookup.c | 3 +++ 5 files changed, 29 insertions(+), 9 deletions(-) diff --git a/TODO b/TODO index e330d46a95..263dce27e7 100644 --- a/TODO +++ b/TODO @@ -1530,7 +1530,18 @@ o Libraries (libc/, libm/) Description: There are many things implemented within the kernel (for example under sched/pthread) that probably should be migrated in the C library where it belongs. - Status: Ope + + I would really like to see a little flavor of a micro-kernel + at the OS interface: I would like to see more primitive OS + system calls with more higher level logic in the C library. + + One awkard thing is the incompatibility of KERNEL vs FLAT + builds: In the kernel build, it would be nice to move many + of the thread-specific data items out of the TCB and into + the process address environment where they belong. It is + difficult to make this compatible with the FLAT build, + however. + Status: Open Priority: Low o File system / Generic drivers (fs/, drivers/) diff --git a/include/sys/syscall.h b/include/sys/syscall.h index 5c13ec70e3..0890ff66e3 100644 --- a/include/sys/syscall.h +++ b/include/sys/syscall.h @@ -401,17 +401,19 @@ # define SYS_pthread_mutex_unlock (__SYS_pthread+21) # define SYS_pthread_once (__SYS_pthread+22) # define SYS_pthread_setcancelstate (__SYS_pthread+23) -# define SYS_pthread_setschedparam (__SYS_pthread+24) -# define SYS_pthread_setschedprio (__SYS_pthread+25) -# define SYS_pthread_setspecific (__SYS_pthread+26) -# define SYS_pthread_yield (__SYS_pthread+27) +# define SYS_Pthread_setcanceltype (__SYS_pthread+24) +# define SYS_pthread_setschedparam (__SYS_pthread+25) +# define SYS_pthread_setschedprio (__SYS_pthread+26) +# define SYS_pthread_setspecific (__SYS_pthread+27) +# define SYS_pthread_testcancel (__SYS_pthread+28) +# define SYS_pthread_yield (__SYS_pthread+29) # ifdef CONFIG_SMP -# define SYS_pthread_setaffinity_np (__SYS_pthread+28) -# define SYS_pthread_getaffinity_np (__SYS_pthread+29) -# define __SYS_pthread_signals (__SYS_pthread+30) +# define SYS_pthread_setaffinity_np (__SYS_pthread+30) +# define SYS_pthread_getaffinity_np (__SYS_pthread+31) +# define __SYS_pthread_signals (__SYS_pthread+32) # else -# define __SYS_pthread_signals (__SYS_pthread+28) +# define __SYS_pthread_signals (__SYS_pthread+30) # endif # ifndef CONFIG_DISABLE_SIGNALS diff --git a/syscall/syscall.csv b/syscall/syscall.csv index a28d0d01a6..e52159ab1d 100644 --- a/syscall/syscall.csv +++ b/syscall/syscall.csv @@ -90,10 +90,12 @@ "pthread_once","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_once_t*","CODE void (*)(void)" "pthread_setaffinity_np","pthread.h","!defined(CONFIG_DISABLE_PTHREAD) && defined(CONFIG_SMP)","int","pthread_t","size_t","FAR const cpu_set_t*" "pthread_setcancelstate","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","int","FAR int*" +"pthread_setcanceltype","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","int","FAR int*" "pthread_setschedparam","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_t","int","FAR const struct sched_param*" "pthread_setschedprio","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_t","int" "pthread_setspecific","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_key_t","FAR const void*" "pthread_sigmask","pthread.h","!defined(CONFIG_DISABLE_SIGNALS) && !defined(CONFIG_DISABLE_PTHREAD)","int","int","FAR const sigset_t*","FAR sigset_t*" +"pthread_testcancel","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","void" "pthread_yield","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","void" "putenv","stdlib.h","!defined(CONFIG_DISABLE_ENVIRON)","int","FAR const char*" "read","unistd.h","CONFIG_NSOCKET_DESCRIPTORS > 0 || CONFIG_NFILE_DESCRIPTORS > 0","ssize_t","int","FAR void*","size_t" diff --git a/syscall/syscall_lookup.h b/syscall/syscall_lookup.h index 60f194fc20..a261bef9a7 100644 --- a/syscall/syscall_lookup.h +++ b/syscall/syscall_lookup.h @@ -291,9 +291,11 @@ SYSCALL_LOOKUP(up_assert, 2, STUB_up_assert) SYSCALL_LOOKUP(pthread_mutex_unlock, 1, STUB_pthread_mutex_unlock) SYSCALL_LOOKUP(pthread_once, 2, STUB_pthread_once) SYSCALL_LOOKUP(pthread_setcancelstate, 2, STUB_pthread_setcancelstate) + SYSCALL_LOOKUP(pthread_setcanceltype, 2, STUB_pthread_setcanceltype) SYSCALL_LOOKUP(pthread_setschedparam, 3, STUB_pthread_setschedparam) SYSCALL_LOOKUP(pthread_setschedprio, 2, STUB_pthread_setschedprio) SYSCALL_LOOKUP(pthread_setspecific, 2, STUB_pthread_setspecific) + SYSCALL_LOOKUP(pthread_testcancel, 0, STUB_pthread_testcancel) SYSCALL_LOOKUP(pthread_yield, 0, STUB_pthread_yield) # ifdef CONFIG_SMP SYSCALL_LOOKUP(pthread_setaffinity, 3, STUB_pthread_setaffinity) diff --git a/syscall/syscall_stublookup.c b/syscall/syscall_stublookup.c index 2b7b1eafca..43e4ebfecb 100644 --- a/syscall/syscall_stublookup.c +++ b/syscall/syscall_stublookup.c @@ -292,12 +292,15 @@ uintptr_t STUB_pthread_mutex_unlock(int nbr, uintptr_t parm1); uintptr_t STUB_pthread_once(int nbr, uintptr_t parm1, uintptr_t parm2); uintptr_t STUB_pthread_setcancelstate(int nbr, uintptr_t parm1, uintptr_t parm2); +uintptr_t STUB_pthread_setcanceltype(int nbr, uintptr_t parm1, + uintptr_t parm2); uintptr_t STUB_pthread_setschedparam(int nbr, uintptr_t parm1, uintptr_t parm2, uintptr_t parm3); uintptr_t STUB_pthread_setschedprio(int nbr, uintptr_t parm1, uintptr_t parm2); uintptr_t STUB_pthread_setspecific(int nbr, uintptr_t parm1, uintptr_t parm2); +uintptr_t STUB_pthread_testcancel(int nbr); uintptr_t STUB_pthread_yield(int nbr); uintptr_t STUB_pthread_setaffinity(int nbr, uintptr_t parm1, -- GitLab From 18ce5496e4bdce4264af29ad527d74eba8dc9a1c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 10 Dec 2016 07:15:33 -0600 Subject: [PATCH 661/734] Fix upper- vs. lower-case typo. --- include/sys/syscall.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/sys/syscall.h b/include/sys/syscall.h index 0890ff66e3..b041abda91 100644 --- a/include/sys/syscall.h +++ b/include/sys/syscall.h @@ -401,7 +401,7 @@ # define SYS_pthread_mutex_unlock (__SYS_pthread+21) # define SYS_pthread_once (__SYS_pthread+22) # define SYS_pthread_setcancelstate (__SYS_pthread+23) -# define SYS_Pthread_setcanceltype (__SYS_pthread+24) +# define SYS_pthread_setcanceltype (__SYS_pthread+24) # define SYS_pthread_setschedparam (__SYS_pthread+25) # define SYS_pthread_setschedprio (__SYS_pthread+26) # define SYS_pthread_setspecific (__SYS_pthread+27) -- GitLab From e62b3bccd3ca2b0e2a6c250b5889a5ce730364d8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 10 Dec 2016 07:40:48 -0600 Subject: [PATCH 662/734] pthread_setcanceltype() and pthread_testcancel() do not have to be system calls if cancellation points are not enabled. --- include/sys/syscall.h | 26 ++++++++++++++++---------- libc/pthread/Make.defs | 4 ++++ sched/pthread/Make.defs | 7 +++++-- sched/pthread/pthread_setcancelstate.c | 2 +- sched/pthread/pthread_setcanceltype.c | 2 +- syscall/syscall.csv | 4 ++-- syscall/syscall_lookup.h | 6 ++++-- syscall/syscall_stublookup.c | 7 ++++--- 8 files changed, 37 insertions(+), 21 deletions(-) diff --git a/include/sys/syscall.h b/include/sys/syscall.h index b041abda91..99fd22b454 100644 --- a/include/sys/syscall.h +++ b/include/sys/syscall.h @@ -401,19 +401,25 @@ # define SYS_pthread_mutex_unlock (__SYS_pthread+21) # define SYS_pthread_once (__SYS_pthread+22) # define SYS_pthread_setcancelstate (__SYS_pthread+23) -# define SYS_pthread_setcanceltype (__SYS_pthread+24) -# define SYS_pthread_setschedparam (__SYS_pthread+25) -# define SYS_pthread_setschedprio (__SYS_pthread+26) -# define SYS_pthread_setspecific (__SYS_pthread+27) -# define SYS_pthread_testcancel (__SYS_pthread+28) -# define SYS_pthread_yield (__SYS_pthread+29) +# define SYS_pthread_setschedparam (__SYS_pthread+24) +# define SYS_pthread_setschedprio (__SYS_pthread+25) +# define SYS_pthread_setspecific (__SYS_pthread+26) +# define SYS_pthread_yield (__SYS_pthread+27) + +# ifdef CONFIG_CANCELLATION_POINTS +# define SYS_pthread_setcanceltype (__SYS_pthread+28) +# define SYS_pthread_testcancel (__SYS_pthread+29) +# define __SYS_pthread_smp (__SYS_pthread+30) +# else +# define __SYS_pthread_smp (__SYS_pthread+28) +# endif # ifdef CONFIG_SMP -# define SYS_pthread_setaffinity_np (__SYS_pthread+30) -# define SYS_pthread_getaffinity_np (__SYS_pthread+31) -# define __SYS_pthread_signals (__SYS_pthread+32) +# define SYS_pthread_setaffinity_np (__SYS_pthread_smp+0) +# define SYS_pthread_getaffinity_np (__SYS_pthread_smp+1) +# define __SYS_pthread_signals (__SYS_pthread_smp+2) # else -# define __SYS_pthread_signals (__SYS_pthread+30) +# define __SYS_pthread_signals __SYS_pthread_smp # endif # ifndef CONFIG_DISABLE_SIGNALS diff --git a/libc/pthread/Make.defs b/libc/pthread/Make.defs index bbb3280959..60ae02b59a 100644 --- a/libc/pthread/Make.defs +++ b/libc/pthread/Make.defs @@ -48,6 +48,10 @@ CSRCS += pthread_mutexattr_getpshared.c pthread_mutexattr_setpshared.c CSRCS += pthread_mutexattr_setprotocol.c pthread_mutexattr_getprotocol.c CSRCS += pthread_mutexattr_settype.c pthread_mutexattr_gettype.c +ifneq ($(CONFIG_CANCELLATION_POINTS),y) +CSRCS += pthread_setcanceltype.c pthread_testcancel.c +endif + ifeq ($(CONFIG_SMP),y) CSRCS += pthread_attr_getaffinity.c pthread_attr_setaffinity.c endif diff --git a/sched/pthread/Make.defs b/sched/pthread/Make.defs index 0ed862edf0..c8ef588422 100644 --- a/sched/pthread/Make.defs +++ b/sched/pthread/Make.defs @@ -42,8 +42,7 @@ CSRCS += pthread_mutexlock.c pthread_mutextrylock.c pthread_mutexunlock.c CSRCS += pthread_condinit.c pthread_conddestroy.c CSRCS += pthread_condwait.c pthread_condsignal.c pthread_condbroadcast.c CSRCS += pthread_barrierinit.c pthread_barrierdestroy.c pthread_barrierwait.c -CSRCS += pthread_cancel.c pthread_setcancelstate.c pthread_setcanceltype.c -CSRCS += pthread_testcancel.c +CSRCS += pthread_cancel.c pthread_setcancelstate.c CSRCS += pthread_keycreate.c pthread_setspecific.c pthread_getspecific.c CSRCS += pthread_keydelete.c CSRCS += pthread_initialize.c pthread_completejoin.c pthread_findjoininfo.c @@ -53,6 +52,10 @@ ifneq ($(CONFIG_DISABLE_SIGNALS),y) CSRCS += pthread_condtimedwait.c pthread_kill.c pthread_sigmask.c endif +ifeq ($(CONFIG_CANCELLATION_POINTS),y) +CSRCS += pthread_setcanceltype.c pthread_testcancel.c +endif + ifeq ($(CONFIG_SMP),y) CSRCS += pthread_setaffinity.c pthread_getaffinity.c endif diff --git a/sched/pthread/pthread_setcancelstate.c b/sched/pthread/pthread_setcancelstate.c index 44c05fba9a..bcc5d24f6b 100644 --- a/sched/pthread/pthread_setcancelstate.c +++ b/sched/pthread/pthread_setcancelstate.c @@ -78,7 +78,7 @@ int pthread_setcancelstate(int state, FAR int *oldstate) /* Return the current state if so requrested */ - if (oldstate) + if (oldstate != NULL) { if ((tcb->flags & TCB_FLAG_NONCANCELABLE) != 0) { diff --git a/sched/pthread/pthread_setcanceltype.c b/sched/pthread/pthread_setcanceltype.c index 0de093cb09..ba3704cd2a 100644 --- a/sched/pthread/pthread_setcanceltype.c +++ b/sched/pthread/pthread_setcanceltype.c @@ -77,7 +77,7 @@ int pthread_setcanceltype(int type, FAR int *oldtype) /* Return the current type if so requrested */ - if (oldtype) + if (oldtype != NULL) { if ((tcb->flags & TCB_FLAG_CANCEL_DEFERRED) != 0) { diff --git a/syscall/syscall.csv b/syscall/syscall.csv index e52159ab1d..19ff12aed6 100644 --- a/syscall/syscall.csv +++ b/syscall/syscall.csv @@ -90,12 +90,12 @@ "pthread_once","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_once_t*","CODE void (*)(void)" "pthread_setaffinity_np","pthread.h","!defined(CONFIG_DISABLE_PTHREAD) && defined(CONFIG_SMP)","int","pthread_t","size_t","FAR const cpu_set_t*" "pthread_setcancelstate","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","int","FAR int*" -"pthread_setcanceltype","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","int","FAR int*" +"pthread_setcanceltype","pthread.h","!defined(CONFIG_DISABLE_PTHREAD) && defined(CONFIG_CANCELLATION_POINTS)","int","int","FAR int*" "pthread_setschedparam","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_t","int","FAR const struct sched_param*" "pthread_setschedprio","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_t","int" "pthread_setspecific","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_key_t","FAR const void*" "pthread_sigmask","pthread.h","!defined(CONFIG_DISABLE_SIGNALS) && !defined(CONFIG_DISABLE_PTHREAD)","int","int","FAR const sigset_t*","FAR sigset_t*" -"pthread_testcancel","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","void" +"pthread_testcancel","pthread.h","!defined(CONFIG_DISABLE_PTHREAD) && defined(CONFIG_CANCELLATION_POINTS)","void" "pthread_yield","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","void" "putenv","stdlib.h","!defined(CONFIG_DISABLE_ENVIRON)","int","FAR const char*" "read","unistd.h","CONFIG_NSOCKET_DESCRIPTORS > 0 || CONFIG_NFILE_DESCRIPTORS > 0","ssize_t","int","FAR void*","size_t" diff --git a/syscall/syscall_lookup.h b/syscall/syscall_lookup.h index a261bef9a7..9381c36b0c 100644 --- a/syscall/syscall_lookup.h +++ b/syscall/syscall_lookup.h @@ -291,12 +291,14 @@ SYSCALL_LOOKUP(up_assert, 2, STUB_up_assert) SYSCALL_LOOKUP(pthread_mutex_unlock, 1, STUB_pthread_mutex_unlock) SYSCALL_LOOKUP(pthread_once, 2, STUB_pthread_once) SYSCALL_LOOKUP(pthread_setcancelstate, 2, STUB_pthread_setcancelstate) - SYSCALL_LOOKUP(pthread_setcanceltype, 2, STUB_pthread_setcanceltype) SYSCALL_LOOKUP(pthread_setschedparam, 3, STUB_pthread_setschedparam) SYSCALL_LOOKUP(pthread_setschedprio, 2, STUB_pthread_setschedprio) SYSCALL_LOOKUP(pthread_setspecific, 2, STUB_pthread_setspecific) - SYSCALL_LOOKUP(pthread_testcancel, 0, STUB_pthread_testcancel) SYSCALL_LOOKUP(pthread_yield, 0, STUB_pthread_yield) +# ifdef CONFIG_CANCELLATION_POINTS + SYSCALL_LOOKUP(pthread_setcanceltype, 2, STUB_pthread_setcanceltype) + SYSCALL_LOOKUP(pthread_testcancel, 0, STUB_pthread_testcancel) +# endif # ifdef CONFIG_SMP SYSCALL_LOOKUP(pthread_setaffinity, 3, STUB_pthread_setaffinity) SYSCALL_LOOKUP(pthread_getaffinity, 3, STUB_pthread_getaffinity) diff --git a/syscall/syscall_stublookup.c b/syscall/syscall_stublookup.c index 43e4ebfecb..3004dedcce 100644 --- a/syscall/syscall_stublookup.c +++ b/syscall/syscall_stublookup.c @@ -292,17 +292,18 @@ uintptr_t STUB_pthread_mutex_unlock(int nbr, uintptr_t parm1); uintptr_t STUB_pthread_once(int nbr, uintptr_t parm1, uintptr_t parm2); uintptr_t STUB_pthread_setcancelstate(int nbr, uintptr_t parm1, uintptr_t parm2); -uintptr_t STUB_pthread_setcanceltype(int nbr, uintptr_t parm1, - uintptr_t parm2); uintptr_t STUB_pthread_setschedparam(int nbr, uintptr_t parm1, uintptr_t parm2, uintptr_t parm3); uintptr_t STUB_pthread_setschedprio(int nbr, uintptr_t parm1, uintptr_t parm2); uintptr_t STUB_pthread_setspecific(int nbr, uintptr_t parm1, uintptr_t parm2); -uintptr_t STUB_pthread_testcancel(int nbr); uintptr_t STUB_pthread_yield(int nbr); +uintptr_t STUB_pthread_setcanceltype(int nbr, uintptr_t parm1, + uintptr_t parm2); +uintptr_t STUB_pthread_testcancel(int nbr); + uintptr_t STUB_pthread_setaffinity(int nbr, uintptr_t parm1, uintptr_t parm2, uintptr_t parm3); uintptr_t STUB_pthread_getaffinity(int nbr, uintptr_t parm1, -- GitLab From 4c68c93f4712fd4a702b96ae32bab21b31cf376b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 10 Dec 2016 07:41:56 -0600 Subject: [PATCH 663/734] Forgot to add some files in the last commit. --- libc/pthread/pthread_setcanceltype.c | 75 ++++++++++++++++++++++++++++ libc/pthread/pthread_testcancel.c | 58 +++++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 libc/pthread/pthread_setcanceltype.c create mode 100644 libc/pthread/pthread_testcancel.c diff --git a/libc/pthread/pthread_setcanceltype.c b/libc/pthread/pthread_setcanceltype.c new file mode 100644 index 0000000000..0565367b1b --- /dev/null +++ b/libc/pthread/pthread_setcanceltype.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * libc/pthread/pthread_setcanceltype.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pthread_setcancelstate + * + * Description: + * The pthread_setcanceltype() function atomically both sets the calling + * thread's cancelability type to the indicated type and returns the + * previous cancelability type at the location referenced by oldtype + * Legal values for type are PTHREAD_CANCEL_DEFERRED and + * PTHREAD_CANCEL_ASYNCHRONOUS. + * + * The cancelability state and type of any newly created threads, + * including the thread in which main() was first invoked, are + * PTHREAD_CANCEL_ENABLE and PTHREAD_CANCEL_DEFERRED respectively. + * + ****************************************************************************/ + +int pthread_setcanceltype(int type, FAR int *oldtype) +{ + /* Return the current type if so requrested */ + + if (oldtype != NULL) + { + *oldtype = PTHREAD_CANCEL_ASYNCHRONOUS; + } + + /* Check the requested cancellation type */ + + return (type == PTHREAD_CANCEL_ASYNCHRONOUS) ? OK : ENOSYS; +} diff --git a/libc/pthread/pthread_testcancel.c b/libc/pthread/pthread_testcancel.c new file mode 100644 index 0000000000..99bc76a56e --- /dev/null +++ b/libc/pthread/pthread_testcancel.c @@ -0,0 +1,58 @@ +/**************************************************************************** + * libc/pthread/pthread_testcancel.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pthread_testcancel + * + * Description: + * The pthread_testcancel() function creates a cancellation point in the + * calling thread. The pthread_testcancel() function has no effect if + * cancelability is disabled + * + ****************************************************************************/ + +void pthread_testcancel(void) +{ +} -- GitLab From e9d3c3362a08558252b3242e5e9c47ffa638439c Mon Sep 17 00:00:00 2001 From: Pierre-Noel Bouteville Date: Sat, 10 Dec 2016 07:46:54 -0600 Subject: [PATCH 664/734] Correct some default font IDs --- include/nuttx/nx/nxfonts.h | 44 +++++++++++++++++++------------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/include/nuttx/nx/nxfonts.h b/include/nuttx/nx/nxfonts.h index 5a5d81e04b..5d5dcf0d36 100644 --- a/include/nuttx/nx/nxfonts.h +++ b/include/nuttx/nx/nxfonts.h @@ -124,70 +124,70 @@ /* X11 misc fixed fonts */ #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_4X6) -# define NXFONT_DEFAULT CONFIG_NXFONT_X11_MISC_FIXED_4X6 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_4X6 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_5X7) -# define NXFONT_DEFAULT CONFIG_NXFONT_X11_MISC_FIXED_5X7 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_5X7 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_5X8) -# define NXFONT_DEFAULT CONFIG_NXFONT_X11_MISC_FIXED_5X8 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_5X8 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_6X9) -# define NXFONT_DEFAULT CONFIG_NXFONT_X11_MISC_FIXED_6X9 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_6X9 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_6X10) -# define NXFONT_DEFAULT CONFIG_NXFONT_X11_MISC_FIXED_6X10 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_6X10 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_6X12) -# define NXFONT_DEFAULT CONFIG_NXFONT_X11_MISC_FIXED_6X12 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_6X12 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_6X13) -# define NXFONT_DEFAULT CONFIG_NXFONT_X11_MISC_FIXED_6X13 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_6X13 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_6X13B) -# define NXFONT_DEFAULT CONFIG_NXFONT_X11_MISC_FIXED_6X13B +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_6X13B #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_6X13O) -# define NXFONT_DEFAULT CONFIG_NXFONT_X11_MISC_FIXED_6X13O +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_6X13O #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_7X13) -# define NXFONT_DEFAULT CONFIG_NXFONT_X11_MISC_FIXED_7X13 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_7X13 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_7X13B) -# define NXFONT_DEFAULT CONFIG_NXFONT_X11_MISC_FIXED_7X13B +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_7X13B #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_7X13O) -# define NXFONT_DEFAULT CONFIG_NXFONT_X11_MISC_FIXED_7X13O +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_7X13O #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_7X14) -# define NXFONT_DEFAULT CONFIG_NXFONT_X11_MISC_FIXED_7X14 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_7X14 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_7X14B) -# define NXFONT_DEFAULT CONFIG_NXFONT_X11_MISC_FIXED_7X14B +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_7X14B #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_8X13) -# define NXFONT_DEFAULT CONFIG_NXFONT_X11_MISC_FIXED_8X13 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_8X13 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_8X13B) -# define NXFONT_DEFAULT CONFIG_NXFONT_X11_MISC_FIXED_8X13B +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_8X13B #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_8X13O) -# define NXFONT_DEFAULT CONFIG_NXFONT_X11_MISC_FIXED_8X13O +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_8X13O #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_9X15) -# define NXFONT_DEFAULT CONFIG_NXFONT_X11_MISC_FIXED_9X15 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_9X15 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_9X15B) -# define NXFONT_DEFAULT CONFIG_NXFONT_X11_MISC_FIXED_9X15B +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_9X15B #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_9X18) -# define NXFONT_DEFAULT CONFIG_NXFONT_X11_MISC_FIXED_9X18 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_9X18 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_9X18B) -# define NXFONT_DEFAULT CONFIG_NXFONT_X11_MISC_FIXED_9X18B +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_9X18B #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_10X20) -# define NXFONT_DEFAULT CONFIG_NXFONT_X11_MISC_FIXED_10X20 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_10X20 /* Mono-space fonts */ -- GitLab From bc3ca25cc7db85a0788d4b89283a9f884192759e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 10 Dec 2016 08:36:58 -0600 Subject: [PATCH 665/734] Cancellation points: Close up some logic to eliminte some race conditions. --- fs/vfs/fs_close.c | 2 +- fs/vfs/fs_fcntl.c | 2 +- fs/vfs/fs_fsync.c | 2 +- fs/vfs/fs_open.c | 2 +- fs/vfs/fs_poll.c | 2 +- fs/vfs/fs_pread.c | 2 +- fs/vfs/fs_pwrite.c | 4 +- fs/vfs/fs_read.c | 2 +- fs/vfs/fs_select.c | 2 +- fs/vfs/fs_write.c | 2 +- include/nuttx/pthread.h | 19 +++++++++- net/socket/accept.c | 4 +- net/socket/connect.c | 4 +- net/socket/recvfrom.c | 4 +- net/socket/send.c | 4 +- net/socket/sendto.c | 2 +- sched/mqueue/mq_rcvinternal.c | 17 +++++++++ sched/mqueue/mq_receive.c | 2 +- sched/mqueue/mq_send.c | 2 +- sched/mqueue/mq_sndinternal.c | 21 ++++++++++- sched/mqueue/mq_timedreceive.c | 2 +- sched/mqueue/mq_timedsend.c | 2 +- sched/pthread/pthread_condtimedwait.c | 2 +- sched/pthread/pthread_condwait.c | 2 +- sched/pthread/pthread_join.c | 2 +- sched/pthread/pthread_testcancel.c | 2 +- sched/sched/sched_waitid.c | 2 +- sched/sched/sched_waitpid.c | 4 +- sched/semaphore/sem_timedwait.c | 2 +- sched/semaphore/sem_wait.c | 31 ++++++++++------ sched/signal/sig_nanosleep.c | 2 +- sched/signal/sig_pause.c | 2 +- sched/signal/sig_suspend.c | 2 +- sched/signal/sig_timedwait.c | 2 +- sched/signal/sig_waitinfo.c | 2 +- sched/task/task_cancelpt.c | 53 +++++++++++++++++++-------- 36 files changed, 148 insertions(+), 67 deletions(-) diff --git a/fs/vfs/fs_close.c b/fs/vfs/fs_close.c index 573b73ee70..2fcf2cb9b8 100644 --- a/fs/vfs/fs_close.c +++ b/fs/vfs/fs_close.c @@ -88,7 +88,7 @@ int close(int fd) /* close() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); #if CONFIG_NFILE_DESCRIPTORS > 0 /* Did we get a valid file descriptor? */ diff --git a/fs/vfs/fs_fcntl.c b/fs/vfs/fs_fcntl.c index f2f1ae5c4c..0fb10e9aa1 100644 --- a/fs/vfs/fs_fcntl.c +++ b/fs/vfs/fs_fcntl.c @@ -223,7 +223,7 @@ int fcntl(int fd, int cmd, ...) /* fcntl() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Setup to access the variable argument list */ diff --git a/fs/vfs/fs_fsync.c b/fs/vfs/fs_fsync.c index fb132275a0..b8ad29ccf3 100644 --- a/fs/vfs/fs_fsync.c +++ b/fs/vfs/fs_fsync.c @@ -122,7 +122,7 @@ int fsync(int fd) /* fsync() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Get the file structure corresponding to the file descriptor. */ diff --git a/fs/vfs/fs_open.c b/fs/vfs/fs_open.c index 5930ccf7ef..0c3bb5ffa5 100644 --- a/fs/vfs/fs_open.c +++ b/fs/vfs/fs_open.c @@ -105,7 +105,7 @@ int open(const char *path, int oflags, ...) /* open() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* If the file is opened for creation, then get the mode bits */ diff --git a/fs/vfs/fs_poll.c b/fs/vfs/fs_poll.c index bccd7d4f14..9389c3e6d1 100644 --- a/fs/vfs/fs_poll.c +++ b/fs/vfs/fs_poll.c @@ -368,7 +368,7 @@ int poll(FAR struct pollfd *fds, nfds_t nfds, int timeout) /* poll() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* This semaphore is used for signaling and, hence, should not have * priority inheritance enabled. diff --git a/fs/vfs/fs_pread.c b/fs/vfs/fs_pread.c index 520d35684e..0d63307c36 100644 --- a/fs/vfs/fs_pread.c +++ b/fs/vfs/fs_pread.c @@ -145,7 +145,7 @@ ssize_t pread(int fd, FAR void *buf, size_t nbytes, off_t offset) /* pread() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Get the file structure corresponding to the file descriptor. */ diff --git a/fs/vfs/fs_pwrite.c b/fs/vfs/fs_pwrite.c index 6b29ee406a..3e90e971b9 100644 --- a/fs/vfs/fs_pwrite.c +++ b/fs/vfs/fs_pwrite.c @@ -143,7 +143,7 @@ ssize_t pwrite(int fd, FAR const void *buf, size_t nbytes, off_t offset) /* pread() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Get the file structure corresponding to the file descriptor. */ @@ -161,6 +161,6 @@ ssize_t pwrite(int fd, FAR const void *buf, size_t nbytes, off_t offset) ret = file_pwrite(filep, buf, nbytes, offset); } - enter_cancellation_point(); + (void)enter_cancellation_point(); return ret; } diff --git a/fs/vfs/fs_read.c b/fs/vfs/fs_read.c index b55ada24ef..aa792d648e 100644 --- a/fs/vfs/fs_read.c +++ b/fs/vfs/fs_read.c @@ -138,7 +138,7 @@ ssize_t read(int fd, FAR void *buf, size_t nbytes) /* read() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Did we get a valid file descriptor? */ diff --git a/fs/vfs/fs_select.c b/fs/vfs/fs_select.c index 660607439d..ca074bb2c7 100644 --- a/fs/vfs/fs_select.c +++ b/fs/vfs/fs_select.c @@ -113,7 +113,7 @@ int select(int nfds, FAR fd_set *readfds, FAR fd_set *writefds, /* select() is cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* How many pollfd structures do we need to allocate? */ diff --git a/fs/vfs/fs_write.c b/fs/vfs/fs_write.c index 4d0311fcfe..c6f2292968 100644 --- a/fs/vfs/fs_write.c +++ b/fs/vfs/fs_write.c @@ -166,7 +166,7 @@ ssize_t write(int fd, FAR const void *buf, size_t nbytes) /* write() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Did we get a valid file descriptor? */ diff --git a/include/nuttx/pthread.h b/include/nuttx/pthread.h index e4698ae741..3250da7894 100644 --- a/include/nuttx/pthread.h +++ b/include/nuttx/pthread.h @@ -42,6 +42,8 @@ ****************************************************************************/ #include + +#include #include #include @@ -170,12 +172,19 @@ EXTERN const pthread_attr_t g_default_pthread_attr; * pending cancellation and, if so, calls either exit() or * pthread_exit(), depending upon the type of the thread. * + * Input Parameters: + * None + * + * Returned Value + * true is returned if a cancellation is pending but cannot be performed + * now due to the nesting level. + * ****************************************************************************/ #ifdef CONFIG_CANCELLATION_POINTS -void enter_cancellation_point(void); +bool enter_cancellation_point(void); #else -# define enter_cancellation_point() +# define enter_cancellation_point() false #endif /**************************************************************************** @@ -193,6 +202,12 @@ void enter_cancellation_point(void); * pending cancellation and, if so, calls either exit() or * pthread_exit(), depending upon the type of the thread. * + * Input Parameters: + * None + * + * Returned Value + * None + * ****************************************************************************/ #ifdef CONFIG_CANCELLATION_POINTS diff --git a/net/socket/accept.c b/net/socket/accept.c index ed6d35fa09..9179a8bd6f 100644 --- a/net/socket/accept.c +++ b/net/socket/accept.c @@ -135,7 +135,7 @@ int psock_accept(FAR struct socket *psock, FAR struct sockaddr *addr, /* Treat as a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Is the socket a stream? */ @@ -365,7 +365,7 @@ int accept(int sockfd, FAR struct sockaddr *addr, FAR socklen_t *addrlen) /* accept() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Verify that the sockfd corresponds to valid, allocated socket */ diff --git a/net/socket/connect.c b/net/socket/connect.c index 3bb98d9899..da5d9fb14e 100644 --- a/net/socket/connect.c +++ b/net/socket/connect.c @@ -519,7 +519,7 @@ int psock_connect(FAR struct socket *psock, FAR const struct sockaddr *addr, /* Treat as a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Verify that the psock corresponds to valid, allocated socket */ @@ -752,7 +752,7 @@ int connect(int sockfd, FAR const struct sockaddr *addr, socklen_t addrlen) /* accept() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Get the underlying socket structure */ diff --git a/net/socket/recvfrom.c b/net/socket/recvfrom.c index e45bacd032..88185aaeab 100644 --- a/net/socket/recvfrom.c +++ b/net/socket/recvfrom.c @@ -1854,7 +1854,7 @@ ssize_t psock_recvfrom(FAR struct socket *psock, FAR void *buf, size_t len, /* Treat as a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Verify that non-NULL pointers were passed */ @@ -2087,7 +2087,7 @@ ssize_t recvfrom(int sockfd, FAR void *buf, size_t len, int flags, /* recvfrom() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Get the underlying socket structure */ diff --git a/net/socket/send.c b/net/socket/send.c index 7f97eac7cc..c0c4dc75db 100644 --- a/net/socket/send.c +++ b/net/socket/send.c @@ -126,7 +126,7 @@ ssize_t psock_send(FAR struct socket *psock, FAR const void *buf, size_t len, /* Treat as a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); switch (psock->s_type) { @@ -273,7 +273,7 @@ ssize_t send(int sockfd, FAR const void *buf, size_t len, int flags) /* send() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Get the underlying socket structure */ diff --git a/net/socket/sendto.c b/net/socket/sendto.c index d1236efb0e..1de63028df 100644 --- a/net/socket/sendto.c +++ b/net/socket/sendto.c @@ -314,7 +314,7 @@ ssize_t sendto(int sockfd, FAR const void *buf, size_t len, int flags, /* sendto() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Get the underlying socket structure */ diff --git a/sched/mqueue/mq_rcvinternal.c b/sched/mqueue/mq_rcvinternal.c index c260c1183d..55a72378cc 100644 --- a/sched/mqueue/mq_rcvinternal.c +++ b/sched/mqueue/mq_rcvinternal.c @@ -50,6 +50,7 @@ #include #include +#include #include "sched/sched.h" #include "mqueue/mqueue.h" @@ -141,6 +142,21 @@ FAR struct mqueue_msg_s *mq_waitreceive(mqd_t mqdes) FAR struct mqueue_inode_s *msgq; FAR struct mqueue_msg_s *rcvmsg; + /* mq_waitreceive() is not a cancellation point, but it is always called + * from a cancellation point. + */ + + if (enter_cancellation_point()) + { + /* If there is a pending cancellation, then do not perform + * the wait. Exit now with ECANCELED. + */ + + set_errno(ECANCELED); + leave_cancellation_point(); + return NULL; + } + /* Get a pointer to the message queue */ msgq = mqdes->msgq; @@ -195,6 +211,7 @@ FAR struct mqueue_msg_s *mq_waitreceive(mqd_t mqdes) msgq->nmsgs--; } + leave_cancellation_point(); return rcvmsg; } diff --git a/sched/mqueue/mq_receive.c b/sched/mqueue/mq_receive.c index a7fa225541..9a46b0d36d 100644 --- a/sched/mqueue/mq_receive.c +++ b/sched/mqueue/mq_receive.c @@ -106,7 +106,7 @@ ssize_t mq_receive(mqd_t mqdes, FAR char *msg, size_t msglen, /* mq_receive() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Verify the input parameters and, in case of an error, set * errno appropriately. diff --git a/sched/mqueue/mq_send.c b/sched/mqueue/mq_send.c index 045a57eca1..354d76e5c7 100644 --- a/sched/mqueue/mq_send.c +++ b/sched/mqueue/mq_send.c @@ -106,7 +106,7 @@ int mq_send(mqd_t mqdes, FAR const char *msg, size_t msglen, int prio) /* mq_send() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Verify the input parameters -- setting errno appropriately * on any failures to verify. diff --git a/sched/mqueue/mq_sndinternal.c b/sched/mqueue/mq_sndinternal.c index 087e1f15dc..0d7682dee2 100644 --- a/sched/mqueue/mq_sndinternal.c +++ b/sched/mqueue/mq_sndinternal.c @@ -1,5 +1,5 @@ /**************************************************************************** - * sched/mqueue/mq_send.c + * sched/mqueue/mq_sndinternal.c * * Copyright (C) 2007, 2009, 2013-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -53,6 +53,7 @@ #include #include #include +#include #include "sched/sched.h" #ifndef CONFIG_DISABLE_SIGNALS @@ -232,6 +233,21 @@ int mq_waitsend(mqd_t mqdes) FAR struct tcb_s *rtcb; FAR struct mqueue_inode_s *msgq; + /* mq_waitsend() is not a cancellation point, but it is always called from + * a cancellation point. + */ + + if (enter_cancellation_point()) + { + /* If there is a pending cancellation, then do not perform + * the wait. Exit now with ECANCELED. + */ + + set_errno(ECANCELED); + leave_cancellation_point(); + return ERROR; + } + /* Get a pointer to the message queue */ msgq = mqdes->msgq; @@ -249,6 +265,7 @@ int mq_waitsend(mqd_t mqdes) /* No... We will return an error to the caller. */ set_errno(EAGAIN); + leave_cancellation_point(); return ERROR; } @@ -283,12 +300,14 @@ int mq_waitsend(mqd_t mqdes) if (get_errno() != OK) { + leave_cancellation_point(); return ERROR; } } } } + leave_cancellation_point(); return OK; } diff --git a/sched/mqueue/mq_timedreceive.c b/sched/mqueue/mq_timedreceive.c index 7b97d65294..d764fbf396 100644 --- a/sched/mqueue/mq_timedreceive.c +++ b/sched/mqueue/mq_timedreceive.c @@ -177,7 +177,7 @@ ssize_t mq_timedreceive(mqd_t mqdes, FAR char *msg, size_t msglen, /* mq_timedreceive() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Verify the input parameters and, in case of an error, set * errno appropriately. diff --git a/sched/mqueue/mq_timedsend.c b/sched/mqueue/mq_timedsend.c index ccd18c69a1..588ae041fc 100644 --- a/sched/mqueue/mq_timedsend.c +++ b/sched/mqueue/mq_timedsend.c @@ -181,7 +181,7 @@ int mq_timedsend(mqd_t mqdes, FAR const char *msg, size_t msglen, int prio, /* mq_timedsend() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Verify the input parameters -- setting errno appropriately * on any failures to verify. diff --git a/sched/pthread/pthread_condtimedwait.c b/sched/pthread/pthread_condtimedwait.c index d9756a6217..0c1001a630 100644 --- a/sched/pthread/pthread_condtimedwait.c +++ b/sched/pthread/pthread_condtimedwait.c @@ -181,7 +181,7 @@ int pthread_cond_timedwait(FAR pthread_cond_t *cond, FAR pthread_mutex_t *mutex, /* pthread_cond_timedwait() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Make sure that non-NULL references were provided. */ diff --git a/sched/pthread/pthread_condwait.c b/sched/pthread/pthread_condwait.c index 647313dc66..06d691dfcd 100644 --- a/sched/pthread/pthread_condwait.c +++ b/sched/pthread/pthread_condwait.c @@ -77,7 +77,7 @@ int pthread_cond_wait(FAR pthread_cond_t *cond, FAR pthread_mutex_t *mutex) /* pthread_cond_wait() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Make sure that non-NULL references were provided. */ diff --git a/sched/pthread/pthread_join.c b/sched/pthread/pthread_join.c index 2ea88ee8f8..6eb795a199 100644 --- a/sched/pthread/pthread_join.c +++ b/sched/pthread/pthread_join.c @@ -96,7 +96,7 @@ int pthread_join(pthread_t thread, FAR pthread_addr_t *pexit_value) /* pthread_join() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* First make sure that this is not an attempt to join to * ourself. diff --git a/sched/pthread/pthread_testcancel.c b/sched/pthread/pthread_testcancel.c index c58d9344e1..5f34ea86b7 100644 --- a/sched/pthread/pthread_testcancel.c +++ b/sched/pthread/pthread_testcancel.c @@ -62,6 +62,6 @@ void pthread_testcancel(void) { - enter_cancellation_point(); + (void)enter_cancellation_point(); leave_cancellation_point(); } diff --git a/sched/sched/sched_waitid.c b/sched/sched/sched_waitid.c index 439fe0b8ac..7f99a92e44 100644 --- a/sched/sched/sched_waitid.c +++ b/sched/sched/sched_waitid.c @@ -167,7 +167,7 @@ int waitid(idtype_t idtype, id_t id, FAR siginfo_t *info, int options) /* waitid() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* MISSING LOGIC: If WNOHANG is provided in the options, then this function * should returned immediately. However, there is no mechanism available now diff --git a/sched/sched/sched_waitpid.c b/sched/sched/sched_waitpid.c index d386d15308..9aa0bada89 100644 --- a/sched/sched/sched_waitpid.c +++ b/sched/sched/sched_waitpid.c @@ -188,7 +188,7 @@ pid_t waitpid(pid_t pid, int *stat_loc, int options) /* waitpid() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* None of the options are supported */ @@ -317,7 +317,7 @@ pid_t waitpid(pid_t pid, int *stat_loc, int options) /* waitpid() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* None of the options are supported */ diff --git a/sched/semaphore/sem_timedwait.c b/sched/semaphore/sem_timedwait.c index 26cfa4db99..ec795c80e4 100644 --- a/sched/semaphore/sem_timedwait.c +++ b/sched/semaphore/sem_timedwait.c @@ -106,7 +106,7 @@ int sem_timedwait(FAR sem_t *sem, FAR const struct timespec *abstime) /* sem_timedwait() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Verify the input parameters and, in case of an error, set * errno appropriately. diff --git a/sched/semaphore/sem_wait.c b/sched/semaphore/sem_wait.c index 8bfe95254b..8baa20ea92 100644 --- a/sched/semaphore/sem_wait.c +++ b/sched/semaphore/sem_wait.c @@ -87,21 +87,31 @@ int sem_wait(FAR sem_t *sem) DEBUGASSERT(sem != NULL && up_interrupt_context() == false); - /* sem_wait is a cancellation point */ + /* The following operations must be performed with interrupts + * disabled because sem_post() may be called from an interrupt + * handler. + */ - enter_cancellation_point(); + flags = enter_critical_section(); - /* Make sure we were supplied with a valid semaphore. */ + /* sem_wait() is a cancellation point */ - if (sem != NULL) + if (enter_cancellation_point()) { - /* The following operations must be performed with interrupts - * disabled because sem_post() may be called from an interrupt - * handler. + /* If there is a pending cancellation, then do not perform + * the wait. Exit now with ECANCELED. */ - flags = enter_critical_section(); + set_errno(ECANCELED); + leave_cancellation_point(); + leave_critical_section(flags); + return ERROR; + } + + /* Make sure we were supplied with a valid semaphore. */ + if (sem != NULL) + { /* Check if the lock is available */ if (sem->semcount > 0) @@ -191,10 +201,6 @@ int sem_wait(FAR sem_t *sem) sched_unlock(); #endif } - - /* Interrupts may now be enabled. */ - - leave_critical_section(flags); } else { @@ -202,5 +208,6 @@ int sem_wait(FAR sem_t *sem) } leave_cancellation_point(); + leave_critical_section(flags); return ret; } diff --git a/sched/signal/sig_nanosleep.c b/sched/signal/sig_nanosleep.c index e37d9142b0..6f61dc45b9 100644 --- a/sched/signal/sig_nanosleep.c +++ b/sched/signal/sig_nanosleep.c @@ -115,7 +115,7 @@ int nanosleep(FAR const struct timespec *rqtp, FAR struct timespec *rmtp) /* nanosleep() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); if (!rqtp || rqtp->tv_nsec < 0 || rqtp->tv_nsec >= 1000000000) { diff --git a/sched/signal/sig_pause.c b/sched/signal/sig_pause.c index 1aa48b6004..3c3ffa1497 100644 --- a/sched/signal/sig_pause.c +++ b/sched/signal/sig_pause.c @@ -80,7 +80,7 @@ int pause(void) /* pause() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Set up for the sleep. Using the empty set means that we are not * waiting for any particular signal. However, any unmasked signal diff --git a/sched/signal/sig_suspend.c b/sched/signal/sig_suspend.c index a717d76ce2..626683ca45 100644 --- a/sched/signal/sig_suspend.c +++ b/sched/signal/sig_suspend.c @@ -101,7 +101,7 @@ int sigsuspend(FAR const sigset_t *set) /* sigsuspend() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Several operations must be performed below: We must determine if any * signal is pending and, if not, wait for the signal. Since signals can diff --git a/sched/signal/sig_timedwait.c b/sched/signal/sig_timedwait.c index 9ac4062beb..f0451b3b43 100644 --- a/sched/signal/sig_timedwait.c +++ b/sched/signal/sig_timedwait.c @@ -176,7 +176,7 @@ int sigtimedwait(FAR const sigset_t *set, FAR struct siginfo *info, /* sigtimedwait() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); sched_lock(); /* Not necessary */ /* Several operations must be performed below: We must determine if any diff --git a/sched/signal/sig_waitinfo.c b/sched/signal/sig_waitinfo.c index 470624c338..e332614583 100644 --- a/sched/signal/sig_waitinfo.c +++ b/sched/signal/sig_waitinfo.c @@ -72,7 +72,7 @@ int sigwaitinfo(FAR const sigset_t *set, FAR struct siginfo *info) /* sigwaitinfo() is a cancellation point */ - enter_cancellation_point(); + (void)enter_cancellation_point(); /* Just a wrapper around sigtimedwait() */ diff --git a/sched/task/task_cancelpt.c b/sched/task/task_cancelpt.c index fcf6745c65..b94ee7c336 100644 --- a/sched/task/task_cancelpt.c +++ b/sched/task/task_cancelpt.c @@ -99,11 +99,19 @@ * pending cancellation and, if so, calls either exit() or * pthread_exit(), depending upon the type of the thread. * + * Input Parameters: + * None + * + * Returned Value + * true is returned if a cancellation is pending but cannot be performed + * now due to the nesting level. + * ****************************************************************************/ -void enter_cancellation_point(void) +bool enter_cancellation_point(void) { FAR struct tcb_s *tcb = this_task(); + bool ret = false; /* Disabling pre-emption should provide sufficient protection. We only * need the TCB to be stationary (no interrupt level modification is @@ -126,24 +134,32 @@ void enter_cancellation_point(void) (tcb->flags & TCB_FLAG_CANCEL_DEFERRED) != 0) || tcb->cpcount > 0) { - /* If there is a pending cancellation and we are at the outermost - * nesting level of cancellation function calls, then just exit - * according to the type of the thread. - */ + /* Check if there is a pending cancellation */ - if ((tcb->flags & TCB_FLAG_CANCEL_PENDING) != 0 && - tcb->cpcount == 0) + if ((tcb->flags & TCB_FLAG_CANCEL_PENDING) != 0) { + /* Yes... return true (if we don't exit here) */ + + ret = true; + + /* If there is a pending cancellation and we are at the outermost + * nesting level of cancellation function calls, then exit + * according to the type of the thread. + */ + + if (tcb->cpcount == 0) + { #ifndef CONFIG_DISABLE_PTHREAD - if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD) - { - pthread_exit(PTHREAD_CANCELED); - } - else + if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD) + { + pthread_exit(PTHREAD_CANCELED); + } + else #endif - { - exit(EXIT_FAILURE); - } + { + exit(EXIT_FAILURE); + } + } } /* Otherwise, indicate that we are at a cancellation point by @@ -156,6 +172,7 @@ void enter_cancellation_point(void) } sched_unlock(); + return ret; } /**************************************************************************** @@ -173,6 +190,12 @@ void enter_cancellation_point(void) * pending cancellation and, if so, calls either exit() or * pthread_exit(), depending upon the type of the thread. * + * Input Parameters: + * None + * + * Returned Value + * None + * ****************************************************************************/ void leave_cancellation_point(void) -- GitLab From b52e4e5ecd924f1da7e8346c435ae5a795c203fe Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 10 Dec 2016 09:08:26 -0600 Subject: [PATCH 666/734] Move cancellation point definitions to their own header file. --- fs/vfs/fs_close.c | 2 +- fs/vfs/fs_fcntl.c | 2 +- fs/vfs/fs_fsync.c | 2 +- fs/vfs/fs_open.c | 2 +- fs/vfs/fs_poll.c | 2 +- fs/vfs/fs_pread.c | 2 +- fs/vfs/fs_pwrite.c | 2 +- fs/vfs/fs_read.c | 2 +- fs/vfs/fs_select.c | 2 +- fs/vfs/fs_write.c | 2 +- include/nuttx/cancelpt.h | 152 ++++++++++++++++++++++++++ include/nuttx/pthread.h | 88 --------------- net/socket/accept.c | 2 +- net/socket/connect.c | 2 +- net/socket/recvfrom.c | 2 +- net/socket/send.c | 2 +- net/socket/sendto.c | 2 +- sched/mqueue/mq_rcvinternal.c | 2 +- sched/mqueue/mq_receive.c | 2 +- sched/mqueue/mq_send.c | 2 +- sched/mqueue/mq_sndinternal.c | 2 +- sched/mqueue/mq_timedreceive.c | 2 +- sched/mqueue/mq_timedsend.c | 2 +- sched/pthread/pthread_condtimedwait.c | 2 +- sched/pthread/pthread_condwait.c | 2 +- sched/pthread/pthread_join.c | 2 +- sched/pthread/pthread_testcancel.c | 2 +- sched/sched/sched_wait.c | 1 - sched/sched/sched_waitid.c | 2 +- sched/sched/sched_waitpid.c | 2 +- sched/semaphore/sem_timedwait.c | 2 +- sched/semaphore/sem_wait.c | 2 +- sched/signal/sig_nanosleep.c | 2 +- sched/signal/sig_pause.c | 2 +- sched/signal/sig_suspend.c | 2 +- sched/signal/sig_timedwait.c | 2 +- sched/signal/sig_waitinfo.c | 2 +- sched/task/task_cancelpt.c | 2 +- 38 files changed, 187 insertions(+), 124 deletions(-) create mode 100644 include/nuttx/cancelpt.h diff --git a/fs/vfs/fs_close.c b/fs/vfs/fs_close.c index 2fcf2cb9b8..6020af5731 100644 --- a/fs/vfs/fs_close.c +++ b/fs/vfs/fs_close.c @@ -43,7 +43,7 @@ #include #include -#include +#include #include #if defined(CONFIG_NET) && CONFIG_NSOCKET_DESCRIPTORS > 0 diff --git a/fs/vfs/fs_fcntl.c b/fs/vfs/fs_fcntl.c index 0fb10e9aa1..4d8e74b497 100644 --- a/fs/vfs/fs_fcntl.c +++ b/fs/vfs/fs_fcntl.c @@ -45,7 +45,7 @@ #include #include -#include +#include #include #include diff --git a/fs/vfs/fs_fsync.c b/fs/vfs/fs_fsync.c index b8ad29ccf3..60c5563497 100644 --- a/fs/vfs/fs_fsync.c +++ b/fs/vfs/fs_fsync.c @@ -45,7 +45,7 @@ #include #include -#include +#include #include #include "inode/inode.h" diff --git a/fs/vfs/fs_open.c b/fs/vfs/fs_open.c index 0c3bb5ffa5..a2a662f722 100644 --- a/fs/vfs/fs_open.c +++ b/fs/vfs/fs_open.c @@ -48,7 +48,7 @@ #include #endif -#include +#include #include #include "inode/inode.h" diff --git a/fs/vfs/fs_poll.c b/fs/vfs/fs_poll.c index 9389c3e6d1..f0cc6ce2a9 100644 --- a/fs/vfs/fs_poll.c +++ b/fs/vfs/fs_poll.c @@ -48,7 +48,7 @@ #include #include -#include +#include #include #include diff --git a/fs/vfs/fs_pread.c b/fs/vfs/fs_pread.c index 0d63307c36..2385ea00a0 100644 --- a/fs/vfs/fs_pread.c +++ b/fs/vfs/fs_pread.c @@ -43,7 +43,7 @@ #include #include -#include +#include #include /**************************************************************************** diff --git a/fs/vfs/fs_pwrite.c b/fs/vfs/fs_pwrite.c index 3e90e971b9..8e841247ca 100644 --- a/fs/vfs/fs_pwrite.c +++ b/fs/vfs/fs_pwrite.c @@ -43,7 +43,7 @@ #include #include -#include +#include #include /**************************************************************************** diff --git a/fs/vfs/fs_read.c b/fs/vfs/fs_read.c index aa792d648e..6da412c379 100644 --- a/fs/vfs/fs_read.c +++ b/fs/vfs/fs_read.c @@ -46,7 +46,7 @@ #include #include -#include +#include #include "inode/inode.h" diff --git a/fs/vfs/fs_select.c b/fs/vfs/fs_select.c index ca074bb2c7..acb42b35ae 100644 --- a/fs/vfs/fs_select.c +++ b/fs/vfs/fs_select.c @@ -49,7 +49,7 @@ #include #include -#include +#include #include #include "inode/inode.h" diff --git a/fs/vfs/fs_write.c b/fs/vfs/fs_write.c index c6f2292968..4731f26bb1 100644 --- a/fs/vfs/fs_write.c +++ b/fs/vfs/fs_write.c @@ -50,7 +50,7 @@ # include #endif -#include +#include #include "inode/inode.h" diff --git a/include/nuttx/cancelpt.h b/include/nuttx/cancelpt.h new file mode 100644 index 0000000000..8adfc8c217 --- /dev/null +++ b/include/nuttx/cancelpt.h @@ -0,0 +1,152 @@ +/**************************************************************************** + * include/nuttx/cancelpt.h + * Definitions related to cancellation points + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_CANCELPT_H +#define __INCLUDE_NUTTX_CANCELPT_H + +/**************************************************************************** + * Cancellation Points. + * + * Cancellation points shall occur when a thread is executing the following + * functions: + * + * accept() mq_timedsend() putpmsg() sigtimedwait() + * aio_suspend() msgrcv() pwrite() sigwait() + * clock_nanosleep() msgsnd() read() sigwaitinfo() + * close() msync() readv() sleep() + * connect() nanosleep() recv() system() + * creat() open() recvfrom() tcdrain() + * fcntl() pause() recvmsg() usleep() + * fdatasync() poll() select() wait() + * fsync() pread() sem_timedwait() waitid() + * getmsg() pselect() sem_wait() waitpid() + * getpmsg() pthread_cond_timedwait() send() write() + * lockf() pthread_cond_wait() sendmsg() writev() + * mq_receive() pthread_join() sendto() + * mq_send() pthread_testcancel() sigpause() + * mq_timedreceive() putmsg() sigsuspend() + * + * Each of the above function must call enter_cancellation_point() on entry + * in order to establish the cancellation point and leave_cancellation_point() + * on exit. These functions are described below. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: enter_cancellation_point + * + * Description: + * Called at the beginning of the cancellation point to establish the + * cancellation point. This function does the following: + * + * 1. If deferred cancellation does not apply to this thread, nothing is + * done, otherwise, it + * 2. Sets state information in the caller's TCB and increments a nesting + * count. + * 3. If this is the outermost nesting level, it checks if there is a + * pending cancellation and, if so, calls either exit() or + * pthread_exit(), depending upon the type of the thread. + * + * Input Parameters: + * None + * + * Returned Value + * true is returned if a cancellation is pending but cannot be performed + * now due to the nesting level. + * + ****************************************************************************/ + +#ifdef CONFIG_CANCELLATION_POINTS +bool enter_cancellation_point(void); +#else +# define enter_cancellation_point() false +#endif + +/**************************************************************************** + * Name: leave_cancellation_point + * + * Description: + * Called at the end of the cancellation point. This function does the + * following: + * + * 1. If deferred cancellation does not apply to this thread, nothing is + * done, otherwise, it + * 2. Clears state information in the caller's TCB and decrements a + * nesting count. + * 3. If this is the outermost nesting level, it checks if there is a + * pending cancellation and, if so, calls either exit() or + * pthread_exit(), depending upon the type of the thread. + * + * Input Parameters: + * None + * + * Returned Value + * None + * + ****************************************************************************/ + +#ifdef CONFIG_CANCELLATION_POINTS +void leave_cancellation_point(void); +#else +# define leave_cancellation_point() +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __INCLUDE_NUTTX_CANCELPT_H */ diff --git a/include/nuttx/pthread.h b/include/nuttx/pthread.h index 3250da7894..27fb5dd99c 100644 --- a/include/nuttx/pthread.h +++ b/include/nuttx/pthread.h @@ -43,7 +43,6 @@ #include -#include #include #include @@ -129,93 +128,6 @@ EXTERN const pthread_attr_t g_default_pthread_attr; * Public Function Prototypes ****************************************************************************/ -/**************************************************************************** - * Cancellation Points. - * - * Cancellation points shall occur when a thread is executing the following - * functions: - * - * accept() mq_timedsend() putpmsg() sigtimedwait() - * aio_suspend() msgrcv() pwrite() sigwait() - * clock_nanosleep() msgsnd() read() sigwaitinfo() - * close() msync() readv() sleep() - * connect() nanosleep() recv() system() - * creat() open() recvfrom() tcdrain() - * fcntl() pause() recvmsg() usleep() - * fdatasync() poll() select() wait() - * fsync() pread() sem_timedwait() waitid() - * getmsg() pselect() sem_wait() waitpid() - * getpmsg() pthread_cond_timedwait() send() write() - * lockf() pthread_cond_wait() sendmsg() writev() - * mq_receive() pthread_join() sendto() - * mq_send() pthread_testcancel() sigpause() - * mq_timedreceive() putmsg() sigsuspend() - * - * Each of the above function must call enter_cancellation_point() on entry - * in order to establish the cancellation point and leave_cancellation_point() - * on exit. These functions are described below. - * - ****************************************************************************/ - -/**************************************************************************** - * Name: enter_cancellation_point - * - * Description: - * Called at the beginning of the cancellation point to establish the - * cancellation point. This function does the following: - * - * 1. If deferred cancellation does not apply to this thread, nothing is - * done, otherwise, it - * 2. Sets state information in the caller's TCB and increments a nesting - * count. - * 3. If this is the outermost nesting level, it checks if there is a - * pending cancellation and, if so, calls either exit() or - * pthread_exit(), depending upon the type of the thread. - * - * Input Parameters: - * None - * - * Returned Value - * true is returned if a cancellation is pending but cannot be performed - * now due to the nesting level. - * - ****************************************************************************/ - -#ifdef CONFIG_CANCELLATION_POINTS -bool enter_cancellation_point(void); -#else -# define enter_cancellation_point() false -#endif - -/**************************************************************************** - * Name: leave_cancellation_point - * - * Description: - * Called at the end of the cancellation point. This function does the - * following: - * - * 1. If deferred cancellation does not apply to this thread, nothing is - * done, otherwise, it - * 2. Clears state information in the caller's TCB and decrements a - * nesting count. - * 3. If this is the outermost nesting level, it checks if there is a - * pending cancellation and, if so, calls either exit() or - * pthread_exit(), depending upon the type of the thread. - * - * Input Parameters: - * None - * - * Returned Value - * None - * - ****************************************************************************/ - -#ifdef CONFIG_CANCELLATION_POINTS -void leave_cancellation_point(void); -#else -# define leave_cancellation_point() -#endif - #undef EXTERN #ifdef __cplusplus } diff --git a/net/socket/accept.c b/net/socket/accept.c index 9179a8bd6f..4bf35dc7f2 100644 --- a/net/socket/accept.c +++ b/net/socket/accept.c @@ -48,7 +48,7 @@ #include #include -#include +#include #include #include "tcp/tcp.h" diff --git a/net/socket/connect.c b/net/socket/connect.c index da5d9fb14e..6a0140ea55 100644 --- a/net/socket/connect.c +++ b/net/socket/connect.c @@ -51,7 +51,7 @@ #include #include -#include +#include #include #include #include diff --git a/net/socket/recvfrom.c b/net/socket/recvfrom.c index 88185aaeab..9a692fea8a 100644 --- a/net/socket/recvfrom.c +++ b/net/socket/recvfrom.c @@ -57,7 +57,7 @@ #include #include -#include +#include #include #include #include diff --git a/net/socket/send.c b/net/socket/send.c index c0c4dc75db..e90b27b116 100644 --- a/net/socket/send.c +++ b/net/socket/send.c @@ -43,7 +43,7 @@ #include #include -#include +#include #include "tcp/tcp.h" #include "udp/udp.h" diff --git a/net/socket/sendto.c b/net/socket/sendto.c index 1de63028df..db51b73c79 100644 --- a/net/socket/sendto.c +++ b/net/socket/sendto.c @@ -45,7 +45,7 @@ #include #include -#include +#include #include #include "udp/udp.h" diff --git a/sched/mqueue/mq_rcvinternal.c b/sched/mqueue/mq_rcvinternal.c index 55a72378cc..1b9c249e75 100644 --- a/sched/mqueue/mq_rcvinternal.c +++ b/sched/mqueue/mq_rcvinternal.c @@ -50,7 +50,7 @@ #include #include -#include +#include #include "sched/sched.h" #include "mqueue/mqueue.h" diff --git a/sched/mqueue/mq_receive.c b/sched/mqueue/mq_receive.c index 9a46b0d36d..31878a29a5 100644 --- a/sched/mqueue/mq_receive.c +++ b/sched/mqueue/mq_receive.c @@ -47,7 +47,7 @@ #include #include -#include +#include #include "mqueue/mqueue.h" diff --git a/sched/mqueue/mq_send.c b/sched/mqueue/mq_send.c index 354d76e5c7..59e6eecebe 100644 --- a/sched/mqueue/mq_send.c +++ b/sched/mqueue/mq_send.c @@ -46,7 +46,7 @@ #include #include -#include +#include #include "mqueue/mqueue.h" diff --git a/sched/mqueue/mq_sndinternal.c b/sched/mqueue/mq_sndinternal.c index 0d7682dee2..10721add0a 100644 --- a/sched/mqueue/mq_sndinternal.c +++ b/sched/mqueue/mq_sndinternal.c @@ -53,7 +53,7 @@ #include #include #include -#include +#include #include "sched/sched.h" #ifndef CONFIG_DISABLE_SIGNALS diff --git a/sched/mqueue/mq_timedreceive.c b/sched/mqueue/mq_timedreceive.c index d764fbf396..9df2a6ab61 100644 --- a/sched/mqueue/mq_timedreceive.c +++ b/sched/mqueue/mq_timedreceive.c @@ -50,7 +50,7 @@ #include #include #include -#include +#include #include "sched/sched.h" #include "clock/clock.h" diff --git a/sched/mqueue/mq_timedsend.c b/sched/mqueue/mq_timedsend.c index 588ae041fc..83e25515eb 100644 --- a/sched/mqueue/mq_timedsend.c +++ b/sched/mqueue/mq_timedsend.c @@ -50,7 +50,7 @@ #include #include #include -#include +#include #include "clock/clock.h" #include "sched/sched.h" diff --git a/sched/pthread/pthread_condtimedwait.c b/sched/pthread/pthread_condtimedwait.c index 0c1001a630..9027c305ef 100644 --- a/sched/pthread/pthread_condtimedwait.c +++ b/sched/pthread/pthread_condtimedwait.c @@ -51,7 +51,7 @@ #include #include -#include +#include #include "sched/sched.h" #include "pthread/pthread.h" diff --git a/sched/pthread/pthread_condwait.c b/sched/pthread/pthread_condwait.c index 06d691dfcd..e7c6a9af25 100644 --- a/sched/pthread/pthread_condwait.c +++ b/sched/pthread/pthread_condwait.c @@ -45,7 +45,7 @@ #include #include -#include +#include #include "pthread/pthread.h" diff --git a/sched/pthread/pthread_join.c b/sched/pthread/pthread_join.c index 6eb795a199..01c1c713ea 100644 --- a/sched/pthread/pthread_join.c +++ b/sched/pthread/pthread_join.c @@ -45,7 +45,7 @@ #include #include -#include +#include #include "sched/sched.h" #include "group/group.h" diff --git a/sched/pthread/pthread_testcancel.c b/sched/pthread/pthread_testcancel.c index 5f34ea86b7..d93af13807 100644 --- a/sched/pthread/pthread_testcancel.c +++ b/sched/pthread/pthread_testcancel.c @@ -42,7 +42,7 @@ #include #include -#include +#include #include "sched/sched.h" diff --git a/sched/sched/sched_wait.c b/sched/sched/sched_wait.c index 8987098528..c558de50bf 100644 --- a/sched/sched/sched_wait.c +++ b/sched/sched/sched_wait.c @@ -44,7 +44,6 @@ #include #include -#include #include "sched/sched.h" diff --git a/sched/sched/sched_waitid.c b/sched/sched/sched_waitid.c index 7f99a92e44..dd3dd86211 100644 --- a/sched/sched/sched_waitid.c +++ b/sched/sched/sched_waitid.c @@ -44,7 +44,7 @@ #include #include -#include +#include #include "sched/sched.h" #include "group/group.h" diff --git a/sched/sched/sched_waitpid.c b/sched/sched/sched_waitpid.c index 9aa0bada89..aca86d093f 100644 --- a/sched/sched/sched_waitpid.c +++ b/sched/sched/sched_waitpid.c @@ -45,7 +45,7 @@ #include #include -#include +#include #include "sched/sched.h" #include "group/group.h" diff --git a/sched/semaphore/sem_timedwait.c b/sched/semaphore/sem_timedwait.c index ec795c80e4..23c16cc2d5 100644 --- a/sched/semaphore/sem_timedwait.c +++ b/sched/semaphore/sem_timedwait.c @@ -49,7 +49,7 @@ #include #include #include -#include +#include #include "sched/sched.h" #include "clock/clock.h" diff --git a/sched/semaphore/sem_wait.c b/sched/semaphore/sem_wait.c index 8baa20ea92..80827b62db 100644 --- a/sched/semaphore/sem_wait.c +++ b/sched/semaphore/sem_wait.c @@ -46,7 +46,7 @@ #include #include -#include +#include #include "sched/sched.h" #include "semaphore/semaphore.h" diff --git a/sched/signal/sig_nanosleep.c b/sched/signal/sig_nanosleep.c index 6f61dc45b9..05f2c88af7 100644 --- a/sched/signal/sig_nanosleep.c +++ b/sched/signal/sig_nanosleep.c @@ -46,7 +46,7 @@ #include #include -#include +#include #include "clock/clock.h" diff --git a/sched/signal/sig_pause.c b/sched/signal/sig_pause.c index 3c3ffa1497..5a83f1a735 100644 --- a/sched/signal/sig_pause.c +++ b/sched/signal/sig_pause.c @@ -42,7 +42,7 @@ #include #include -#include +#include /**************************************************************************** * Public Functions diff --git a/sched/signal/sig_suspend.c b/sched/signal/sig_suspend.c index 626683ca45..ab5cfd25fe 100644 --- a/sched/signal/sig_suspend.c +++ b/sched/signal/sig_suspend.c @@ -46,7 +46,7 @@ #include #include -#include +#include #include "sched/sched.h" #include "signal/signal.h" diff --git a/sched/signal/sig_timedwait.c b/sched/signal/sig_timedwait.c index f0451b3b43..bdb5376d8b 100644 --- a/sched/signal/sig_timedwait.c +++ b/sched/signal/sig_timedwait.c @@ -52,7 +52,7 @@ #include #include #include -#include +#include #include "sched/sched.h" #include "signal/signal.h" diff --git a/sched/signal/sig_waitinfo.c b/sched/signal/sig_waitinfo.c index e332614583..73afb186de 100644 --- a/sched/signal/sig_waitinfo.c +++ b/sched/signal/sig_waitinfo.c @@ -41,7 +41,7 @@ #include -#include +#include /**************************************************************************** * Public Functions diff --git a/sched/task/task_cancelpt.c b/sched/task/task_cancelpt.c index b94ee7c336..07b4a664c8 100644 --- a/sched/task/task_cancelpt.c +++ b/sched/task/task_cancelpt.c @@ -71,7 +71,7 @@ #include #include -#include +#include #include "sched/sched.h" #include "semaphore/semaphore.h" -- GitLab From 842ec7e612b2ddc1a7732162d74581246e02227f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 10 Dec 2016 09:43:04 -0600 Subject: [PATCH 667/734] ifdef out some non-reachable code --- sched/mqueue/mq_rcvinternal.c | 2 ++ sched/mqueue/mq_sndinternal.c | 2 ++ sched/semaphore/sem_wait.c | 2 ++ 3 files changed, 6 insertions(+) diff --git a/sched/mqueue/mq_rcvinternal.c b/sched/mqueue/mq_rcvinternal.c index 1b9c249e75..8bd9545c86 100644 --- a/sched/mqueue/mq_rcvinternal.c +++ b/sched/mqueue/mq_rcvinternal.c @@ -148,6 +148,7 @@ FAR struct mqueue_msg_s *mq_waitreceive(mqd_t mqdes) if (enter_cancellation_point()) { +#ifndef CONFIG_CANCELLATION_POINTS /* Not reachable in this case *. /* If there is a pending cancellation, then do not perform * the wait. Exit now with ECANCELED. */ @@ -155,6 +156,7 @@ FAR struct mqueue_msg_s *mq_waitreceive(mqd_t mqdes) set_errno(ECANCELED); leave_cancellation_point(); return NULL; +#endif } /* Get a pointer to the message queue */ diff --git a/sched/mqueue/mq_sndinternal.c b/sched/mqueue/mq_sndinternal.c index 10721add0a..a8b74ade72 100644 --- a/sched/mqueue/mq_sndinternal.c +++ b/sched/mqueue/mq_sndinternal.c @@ -239,6 +239,7 @@ int mq_waitsend(mqd_t mqdes) if (enter_cancellation_point()) { +#ifndef CONFIG_CANCELLATION_POINTS /* Not reachable in this case *. /* If there is a pending cancellation, then do not perform * the wait. Exit now with ECANCELED. */ @@ -246,6 +247,7 @@ int mq_waitsend(mqd_t mqdes) set_errno(ECANCELED); leave_cancellation_point(); return ERROR; +#endif } /* Get a pointer to the message queue */ diff --git a/sched/semaphore/sem_wait.c b/sched/semaphore/sem_wait.c index 80827b62db..4a01ffcafa 100644 --- a/sched/semaphore/sem_wait.c +++ b/sched/semaphore/sem_wait.c @@ -98,6 +98,7 @@ int sem_wait(FAR sem_t *sem) if (enter_cancellation_point()) { +#ifndef CONFIG_CANCELLATION_POINTS /* Not reachable in this case *. /* If there is a pending cancellation, then do not perform * the wait. Exit now with ECANCELED. */ @@ -106,6 +107,7 @@ int sem_wait(FAR sem_t *sem) leave_cancellation_point(); leave_critical_section(flags); return ERROR; +#endif } /* Make sure we were supplied with a valid semaphore. */ -- GitLab From 6997cda1b5ef6030713a170969bad8bc3edcaf00 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 10 Dec 2016 09:45:55 -0600 Subject: [PATCH 668/734] Grrr... cloned typos! --- sched/mqueue/mq_rcvinternal.c | 2 +- sched/mqueue/mq_sndinternal.c | 2 +- sched/semaphore/sem_wait.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/sched/mqueue/mq_rcvinternal.c b/sched/mqueue/mq_rcvinternal.c index 8bd9545c86..91701e5e07 100644 --- a/sched/mqueue/mq_rcvinternal.c +++ b/sched/mqueue/mq_rcvinternal.c @@ -148,7 +148,7 @@ FAR struct mqueue_msg_s *mq_waitreceive(mqd_t mqdes) if (enter_cancellation_point()) { -#ifndef CONFIG_CANCELLATION_POINTS /* Not reachable in this case *. +#ifndef CONFIG_CANCELLATION_POINTS /* Not reachable in this case */ /* If there is a pending cancellation, then do not perform * the wait. Exit now with ECANCELED. */ diff --git a/sched/mqueue/mq_sndinternal.c b/sched/mqueue/mq_sndinternal.c index a8b74ade72..c59250683f 100644 --- a/sched/mqueue/mq_sndinternal.c +++ b/sched/mqueue/mq_sndinternal.c @@ -239,7 +239,7 @@ int mq_waitsend(mqd_t mqdes) if (enter_cancellation_point()) { -#ifndef CONFIG_CANCELLATION_POINTS /* Not reachable in this case *. +#ifndef CONFIG_CANCELLATION_POINTS /* Not reachable in this case */ /* If there is a pending cancellation, then do not perform * the wait. Exit now with ECANCELED. */ diff --git a/sched/semaphore/sem_wait.c b/sched/semaphore/sem_wait.c index 4a01ffcafa..1aec3679d8 100644 --- a/sched/semaphore/sem_wait.c +++ b/sched/semaphore/sem_wait.c @@ -98,7 +98,7 @@ int sem_wait(FAR sem_t *sem) if (enter_cancellation_point()) { -#ifndef CONFIG_CANCELLATION_POINTS /* Not reachable in this case *. +#ifndef CONFIG_CANCELLATION_POINTS /* Not reachable in this case */ /* If there is a pending cancellation, then do not perform * the wait. Exit now with ECANCELED. */ -- GitLab From 698597a838fe89cb4c2e2a73f71be3c5bdce0802 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 10 Dec 2016 14:39:19 -0600 Subject: [PATCH 669/734] task_delete() now obeys all cancellation point semantics. --- Documentation/NuttxUserGuide.html | 22 ++++-- sched/pthread/pthread_cancel.c | 14 ++-- sched/task/task_delete.c | 108 ++++++++++++++++++++++-------- sched/task/task_restart.c | 2 +- 4 files changed, 107 insertions(+), 39 deletions(-) diff --git a/Documentation/NuttxUserGuide.html b/Documentation/NuttxUserGuide.html index ada2c6d9e1..c4bc4c839d 100644 --- a/Documentation/NuttxUserGuide.html +++ b/Documentation/NuttxUserGuide.html @@ -13,7 +13,7 @@

    NuttX Operating System

    User's Manual

    by

    Gregory Nutt

    -

    Last Updated: December 9, 2016

    +

    Last Updated: December 10, 2016

    @@ -469,8 +469,21 @@ int task_delete(pid_t pid);

    Description: - This function causes a specified task to cease to exist -- its stack and TCB will be deallocated. - This function is the companion to task_create(). + This function causes a specified task to cease to exist. + Its stack and TCB will be deallocated. + This function is the companion to task_create(). + This is the version of the function exposed to the user; + it is simply a wrapper around the internal, task_terminate() function. +

    +

    + The logic in this function only deletes non-running tasks. + If the pid parameter refers to to the currently runing task, then processing is redirected to exit(). + This can only happen if a task calls task_delete() in order to delete itself. +

    +

    + This function obeys the semantics of pthread cancellation: + task deletion is deferred if cancellation is disabled or if deferred cancellation is supported (with cancellation points enabled). +

    Input Parameters:

      @@ -485,7 +498,8 @@ int task_delete(pid_t pid);
      • OK, or ERROR if the task cannot be deleted. - This function can fail if the provided pid does not correspond to a task (errno is not set). + The errno is set to indicate the nature of the failure. + This function can fail, for example, if the provided pid does not correspond to a currently executing task.

      diff --git a/sched/pthread/pthread_cancel.c b/sched/pthread/pthread_cancel.c index b8f89ead30..6b974629a0 100644 --- a/sched/pthread/pthread_cancel.c +++ b/sched/pthread/pthread_cancel.c @@ -58,7 +58,7 @@ int pthread_cancel(pthread_t thread) /* First, make sure that the handle references a valid thread */ - if (!thread) + if (thread == 0) { /* pid == 0 is the IDLE task. Callers cannot cancel the * IDLE task. @@ -77,11 +77,13 @@ int pthread_cancel(pthread_t thread) return ESRCH; } + /* Only pthreads should use this interface */ + DEBUGASSERT((tcb->cmn.flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD); /* Check to see if this thread has the non-cancelable bit set in its * flags. Suppress context changes for a bit so that the flags are stable. - * (the flags should not change in interrupt handling. + * (the flags should not change in interrupt handling). */ sched_lock(); @@ -110,7 +112,7 @@ int pthread_cancel(pthread_t thread) if ((tcb->cmn.flags & TCB_FLAG_CANCEL_DEFERRED) != 0) { - /* Then we cannot cancel the thread asynchronoulsy. Mark the cancellation + /* Then we cannot cancel the thread asynchronously. Mark the cancellation * as pending. */ @@ -162,9 +164,7 @@ int pthread_cancel(pthread_t thread) (void)pthread_completejoin((pid_t)thread, PTHREAD_CANCELED); - /* Then let pthread_delete do the real work */ + /* Then let task_terminate do the real work */ - task_delete((pid_t)thread); - return OK; + return task_terminate((pid_t)thread, false); } - diff --git a/sched/task/task_delete.c b/sched/task/task_delete.c index 50746f2387..755584fd0c 100644 --- a/sched/task/task_delete.c +++ b/sched/task/task_delete.c @@ -1,7 +1,7 @@ /**************************************************************************** * sched/task/task_delete.c * - * Copyright (C) 2007-2009, 2011-2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2009, 2011-2013, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -40,6 +40,7 @@ #include #include +#include #include @@ -64,56 +65,90 @@ * redirected to exit(). This can only happen if a task calls task_delete() * in order to delete itself. * - * In fact, this function (and task_terminate) are the final functions - * called all task termination sequences. task_delete may be called - * from: - * - * - task_restart(), - * - pthread_cancel(), - * - and directly from user code. - * - * Other exit paths (exit(), _eixt(), and pthread_exit()) will go through - * task_terminate() + * This function obeys the semantics of pthread cancellation: task + * deletion is deferred if cancellation is disabled or if deferred + * cancellation is supported (with cancellation points enabled). * * Inputs: * pid - The task ID of the task to delete. A pid of zero * signifies the calling task. * * Return Value: - * OK on success; or ERROR on failure - * - * This function can fail if the provided pid does not correspond to a - * task (errno is not set) + * OK on success; or ERROR on failure with the errno variable set + * appropriately. * ****************************************************************************/ int task_delete(pid_t pid) { + FAR struct tcb_s *dtcb; FAR struct tcb_s *rtcb; + int ret; - /* Check if the task to delete is the calling task */ + /* Check if the task to delete is the calling task: PID=0 means to delete + * the calling task. In this case, task_delete() is much like exit() + * except that it obeys the cancellation semantics. + */ rtcb = this_task(); - if (pid == 0 || pid == rtcb->pid) + if (pid == 0) { - /* If it is, then what we really wanted to do was exit. Note that we - * don't bother to unlock the TCB since it will be going away. + pid = rtcb->pid; + } + + /* Get the TCB of the task to be deleted */ + + dtcb = (FAR struct tcb_s *)sched_gettcb(pid); + if (dtcb == NULL) + { + /* The pid does not correspond to any known thread. The task + * has probably already exited. */ - exit(EXIT_SUCCESS); + set_errno(ESRCH); + return ERROR; + } + + /* Only tasks and kernel threads should use this interface */ + + DEBUGASSERT((dtcb->flags & TCB_FLAG_TTYPE_MASK) != TCB_FLAG_TTYPE_PTHREAD); + + /* Check to see if this task has the non-cancelable bit set in its + * flags. Suppress context changes for a bit so that the flags are stable. + * (the flags should not change in interrupt handling). + */ + + sched_lock(); + if ((dtcb->flags & TCB_FLAG_NONCANCELABLE) != 0) + { + /* Then we cannot cancel the thread now. Here is how this is + * supposed to work: + * + * "When cancelability is disabled, all cancels are held pending + * in the target thread until the thread changes the cancelability. + * When cancelability is deferred, all cancels are held pending in + * the target thread until the thread changes the cancelability, calls + * a function which is a cancellation point or calls pthread_testcancel(), + * thus creating a cancellation point. When cancelability is asynchronous, + * all cancels are acted upon immediately, interrupting the thread with its + * processing." + */ + + dtcb->flags |= TCB_FLAG_CANCEL_PENDING; + sched_unlock(); + return OK; } #ifdef CONFIG_CANCELLATION_POINTS /* Check if this task supports deferred cancellation */ - sched_lock(); - if ((rtcb->flags & TCB_FLAG_CANCEL_DEFERRED) != 0) + if ((dtcb->flags & TCB_FLAG_CANCEL_DEFERRED) != 0) { - /* Then we cannot cancel the task asynchronoulsy. Mark the cancellation + /* Then we cannot cancel the task asynchronously. Mark the cancellation * as pending. */ - rtcb->flags |= TCB_FLAG_CANCEL_PENDING; + dtcb->flags |= TCB_FLAG_CANCEL_PENDING; /* If the task is waiting at a cancellation point, then notify of the * cancellation thereby waking the task up with an ECANCELED error. @@ -121,9 +156,9 @@ int task_delete(pid_t pid) * REVISIT: is locking the scheduler sufficent in SMP mode? */ - if (rtcb->cpcount > 0) + if (dtcb->cpcount > 0) { - notify_cancellation(rtcb); + notify_cancellation(dtcb); } sched_unlock(); @@ -131,9 +166,28 @@ int task_delete(pid_t pid) } #endif + /* Check if the task to delete is the calling task */ + + sched_unlock(); + if (pid == rtcb->pid) + { + /* If it is, then what we really wanted to do was exit. Note that we + * don't bother to unlock the TCB since it will be going away. + */ + + exit(EXIT_SUCCESS); + } + /* Otherwise, perform the asynchronous cancellation, letting * task_terminate() do all of the heavy lifting. */ - return task_terminate(pid, false); + ret = task_terminate(pid, false); + if (ret < 0) + { + set_errno(-ret); + return ERROR; + } + + return OK; } diff --git a/sched/task/task_restart.c b/sched/task/task_restart.c index 21aec95b47..e499a6c598 100644 --- a/sched/task/task_restart.c +++ b/sched/task/task_restart.c @@ -214,7 +214,7 @@ int task_restart(pid_t pid) ret = task_activate((FAR struct tcb_s *)tcb); if (ret != OK) { - (void)task_delete(pid); + (void)task_terminate(pid, true); errcode = -ret; goto errout_with_lock; } -- GitLab From 5fb207eb363bb768524f4c2512edc531aeec8d20 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 10 Dec 2016 15:16:46 -0600 Subject: [PATCH 670/734] Add task_setcancelstate() --- Documentation/NuttxUserGuide.html | 151 ++++++++++++------ include/sched.h | 2 + include/sys/syscall.h | 22 +-- sched/pthread/Make.defs | 2 +- sched/task/Make.defs | 5 +- .../task_setcancelstate.c} | 47 ++++-- syscall/syscall.csv | 2 +- syscall/syscall_lookup.h | 2 +- syscall/syscall_stublookup.c | 4 +- 9 files changed, 156 insertions(+), 81 deletions(-) rename sched/{pthread/pthread_setcancelstate.c => task/task_setcancelstate.c} (77%) diff --git a/Documentation/NuttxUserGuide.html b/Documentation/NuttxUserGuide.html index c4bc4c839d..9efb520f46 100644 --- a/Documentation/NuttxUserGuide.html +++ b/Documentation/NuttxUserGuide.html @@ -203,49 +203,51 @@ paragraphs.

    • 2.1.3 task_activate
    • 2.1.4 task_delete
    • 2.1.5 task_restart
      • +
    • 2.1.6 task_setcancelstate

    Standard interfaces

    Standard vfork and exec[v|l] interfaces:

    Standard posix_spawn interfaces:

    Non-standard task control interfaces inspired by posix_spawn:

    2.1.1 task_create

    @@ -597,7 +599,59 @@ VxWorks provides the following similar interface: -

    2.1.6 exit

    +

    2.1.6 task_setcancelstate

    +

    +Function Prototype: +

    +

    +    #include <sched.h>
+    int task_setcancelstate(int state, int *oldstate);
+
    +

    +Description: +

    +

    +The task_setcancelstate() function atomically +sets both the calling task's cancelability state to the indicated +state and returns the previous cancelability state at the location +referenced by oldstate. +Legal values for state are TASK_CANCEL_ENABLE and TASK_CANCEL_DISABLE. +

    +

    +Any pending thread cancellation may occur at the time that the +cancellation state is set to TASK_CANCEL_ENABLE. +

    +

    +The cancelability state and type of any newly created tasks are TASK_CANCEL_ENABLE and TASK_CANCEL_DEFERRED respectively. +

    +Input Parameters: +

    +

    +

      +
    • state +New cancellation state. One of PTHREAD_CANCEL_ENABLE or PTHREAD_CANCEL_DISABLE.
      • +
    • oldstate. +Location to return the previous cancellation state. +
    +

    +

    +Returned Value: +

    +

    +Zero (OK) on success; ERROR is returned on any failure with the errno value set appropriately: +

    +

    +

      +
    • ESRCH. +No thread could be found corresponding to that specified by the given thread ID.
      • +
    +

    +Assumptions/Limitations: +

    +POSIX Compatibility: This is a non-standard interface. It extends the functionality of pthread_setcancelstate() to tasks and supports use of task_delete. +

    + +

    2.1.7 exit

    Function Prototype: @@ -643,7 +697,7 @@ And the UNIX interface:

  • The code parameter is ignored. -

    2.1.7 getpid

    +

    2.1.8 getpid

    Function Prototype: @@ -671,7 +725,7 @@ level. Compatible with the POSIX interface of the same name.

    -

    2.1.8 vfork

    +

    2.1.9 vfork

    Function Prototype:

    @@ -705,7 +759,7 @@ pid_t vfork(void); Compatible with the Unix interface of the same name.

    -

    2.1.9 execv

    +

    2.1.10 execv

    Function Prototype:

    @@ -791,7 +845,7 @@ int execv(FAR const char *path, FAR char *const argv[]); There are, however, several compatibility issues as detailed in the description above.

    -

    2.1.10 execl

    +

    2.1.11 execl

    Function Prototype:

    @@ -835,7 +889,7 @@ int execl(FAR const char *path, ...); There are, however, several compatibility issues as detailed in the description of execv().

    -

    2.1.11 posix_spawn and posix_spawnp

    +

    2.1.12 posix_spawn and posix_spawnp

    Function Prototype:

    @@ -978,7 +1032,7 @@ int posix_spawnp(FAR pid_t *pid, FAR const char *file, For the caller of posix_spawn(), the provided argv[0] will correspond to argv[1] received by the new task.

    -

    2.1.12 posix_spawn_file_actions_init

    +

    2.1.13 posix_spawn_file_actions_init

    Function Prototype:

    @@ -1004,7 +1058,7 @@ int posix_spawn_file_actions_init(FAR posix_spawn_file_actions_t *file_actions); On success, this function returns 0; on failure it will return an error number from <errno.h>.

    -

    2.1.13 posix_spawn_file_actions_destroy

    +

    2.1.14 posix_spawn_file_actions_destroy

    Function Prototype:

    @@ -1031,7 +1085,7 @@ int posix_spawn_file_actions_destroy(FAR posix_spawn_file_actions_t *file_action On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.14 posix_spawn_file_actions_addclose

    +

    2.1.15 posix_spawn_file_actions_addclose

    Function Prototype:

    @@ -1062,7 +1116,7 @@ int posix_spawn_file_actions_addclose(FAR posix_spawn_file_actions_t *file_actio On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.15 posix_spawn_file_actions_adddup2

    +

    2.1.16 posix_spawn_file_actions_adddup2

    Function Prototype:

    @@ -1099,7 +1153,7 @@ int posix_spawn_file_actions_adddup2(FAR posix_spawn_file_actions_t *file_action On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.16 posix_spawn_file_actions_addopen

    +

    2.1.17 posix_spawn_file_actions_addopen

    Function Prototype:

    @@ -1144,7 +1198,7 @@ int posix_spawn_file_actions_addopen(FAR posix_spawn_file_actions_t *file_action On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.17 posix_spawnattr_init

    +

    2.1.18 posix_spawnattr_init

    Function Prototype:

    @@ -1180,7 +1234,7 @@ int posix_spawnattr_init(FAR posix_spawnattr_t *attr); On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.18 posix_spawnattr_getflags

    +

    2.1.19 posix_spawnattr_getflags

    Function Prototype:

    @@ -1210,7 +1264,7 @@ int posix_spawnattr_getflags(FAR const posix_spawnattr_t *attr, FAR short *flags On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.19 posix_spawnattr_getschedparam

    +

    2.1.20 posix_spawnattr_getschedparam

    Function Prototype:

    @@ -1240,7 +1294,7 @@ int posix_spawnattr_getschedparam(FAR const posix_spawnattr_t *attr, FAR struct On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.20 posix_spawnattr_getschedpolicy

    +

    2.1.21 posix_spawnattr_getschedpolicy

    Function Prototype:

    @@ -1270,7 +1324,7 @@ int posix_spawnattr_getschedpolicy(FAR const posix_spawnattr_t *attr, FAR int *p On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.21 posix_spawnattr_getsigmask

    +

    2.1.22 posix_spawnattr_getsigmask

    Function Prototype:

    @@ -1302,7 +1356,7 @@ int posix_spawnattr_getsigmask(FAR const posix_spawnattr_t *attr, FAR sigset_t * On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.22 posix_spawnattr_setflags

    +

    2.1.23 posix_spawnattr_setflags

    Function Prototype:

    @@ -1332,7 +1386,7 @@ int posix_spawnattr_setflags(FAR posix_spawnattr_t *attr, short flags); On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.23 posix_spawnattr_setschedparam

    +

    2.1.24 posix_spawnattr_setschedparam

    Function Prototype:

    @@ -1362,7 +1416,7 @@ int posix_spawnattr_setschedparam(FAR posix_spawnattr_t *attr, FAR const struct On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.24 posix_spawnattr_setschedpolicy

    +

    2.1.25 posix_spawnattr_setschedpolicy

    Function Prototype:

    @@ -1392,7 +1446,7 @@ int posix_spawnattr_setschedpolicy(FAR posix_spawnattr_t *attr, int policy); On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.25 posix_spawnattr_setsigmask

    +

    2.1.26 posix_spawnattr_setsigmask

    Function Prototype:

    @@ -1424,7 +1478,7 @@ int posix_spawnattr_setsigmask(FAR posix_spawnattr_t *attr, FAR const sigset_t * On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.26 task_spawn

    +

    2.1.27 task_spawn

    Function Prototype:

    @@ -1538,7 +1592,7 @@ int task_spawn(FAR pid_t *pid, FAR const char *name, main_t entry, This is a non-standard interface inspired by posix_spawn().

    -

    2.1.26 task_spawnattr_getstacksize

    +

    2.1.28 task_spawnattr_getstacksize

    Function Prototype:

    @@ -1568,7 +1622,7 @@ int task_spawnattr_getstacksize(FAR const posix_spawnattr_t *attr, FAR size_t *s On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.26 task_spawnattr_setstacksize

    +

    2.1.29 task_spawnattr_setstacksize

    Function Prototype:

    @@ -1598,7 +1652,7 @@ int task_spawnattr_setstacksize(FAR posix_spawnattr_t *attr, size_t stacksize); On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.12 posix_spawn_file_actions_init

    +

    2.1.30 posix_spawn_file_actions_init

    Function Prototype:

    @@ -10194,10 +10248,10 @@ notify a task when a message is available on a queue.
  • pthread_once
  • pthread_self
  • pthread_setcancelstate
    • +
  • pthread_setcanceltype
  • pthread_setschedparam
  • pthread_setspecific
  • pthread_sigmask
    • -
  • pthread_setcanceltype
  • pthread_testcancel
  • pthread_yield
  • puts
    • @@ -10268,6 +10322,7 @@ notify a task when a message is available on a queue.
  • task_init
  • task_restart
  • Task Scheduling Interfaces +
  • task_setcancelstate
  • task_spawn
  • task_spawnattr_getstacksize
  • task_spawnattr_setstacksize
    • diff --git a/include/sched.h b/include/sched.h index 31526f923e..44877c2341 100644 --- a/include/sched.h +++ b/include/sched.h @@ -229,6 +229,8 @@ int task_create(FAR const char *name, int priority, int stack_size, int task_delete(pid_t pid); int task_restart(pid_t pid); +int task_setcancelstate(int state, FAR int *oldstate); + /* Task Scheduling Interfaces (based on POSIX APIs) */ int sched_setparam(pid_t pid, const struct sched_param *param); diff --git a/include/sys/syscall.h b/include/sys/syscall.h index 99fd22b454..06aa183658 100644 --- a/include/sys/syscall.h +++ b/include/sys/syscall.h @@ -128,8 +128,9 @@ # define SYS_task_delete __SYS_task_delete # define SYS_task_restart (__SYS_task_delete+1) -# define SYS_up_assert (__SYS_task_delete+2) -# define __SYS_vfork (__SYS_task_delete+3) +# define SYS_task_setcancelstate (__SYS_task_delete+2) +# define SYS_up_assert (__SYS_task_delete+3) +# define __SYS_vfork (__SYS_task_delete+4) /* The following can be individually enabled */ @@ -400,18 +401,17 @@ # define SYS_pthread_mutex_trylock (__SYS_pthread+20) # define SYS_pthread_mutex_unlock (__SYS_pthread+21) # define SYS_pthread_once (__SYS_pthread+22) -# define SYS_pthread_setcancelstate (__SYS_pthread+23) -# define SYS_pthread_setschedparam (__SYS_pthread+24) -# define SYS_pthread_setschedprio (__SYS_pthread+25) -# define SYS_pthread_setspecific (__SYS_pthread+26) -# define SYS_pthread_yield (__SYS_pthread+27) +# define SYS_pthread_setschedparam (__SYS_pthread+23) +# define SYS_pthread_setschedprio (__SYS_pthread+24) +# define SYS_pthread_setspecific (__SYS_pthread+25) +# define SYS_pthread_yield (__SYS_pthread+26) # ifdef CONFIG_CANCELLATION_POINTS -# define SYS_pthread_setcanceltype (__SYS_pthread+28) -# define SYS_pthread_testcancel (__SYS_pthread+29) -# define __SYS_pthread_smp (__SYS_pthread+30) +# define SYS_pthread_setcanceltype (__SYS_pthread+27) +# define SYS_pthread_testcancel (__SYS_pthread+28) +# define __SYS_pthread_smp (__SYS_pthread+29) # else -# define __SYS_pthread_smp (__SYS_pthread+28) +# define __SYS_pthread_smp (__SYS_pthread+27) # endif # ifdef CONFIG_SMP diff --git a/sched/pthread/Make.defs b/sched/pthread/Make.defs index c8ef588422..362a6d63bf 100644 --- a/sched/pthread/Make.defs +++ b/sched/pthread/Make.defs @@ -42,7 +42,7 @@ CSRCS += pthread_mutexlock.c pthread_mutextrylock.c pthread_mutexunlock.c CSRCS += pthread_condinit.c pthread_conddestroy.c CSRCS += pthread_condwait.c pthread_condsignal.c pthread_condbroadcast.c CSRCS += pthread_barrierinit.c pthread_barrierdestroy.c pthread_barrierwait.c -CSRCS += pthread_cancel.c pthread_setcancelstate.c +CSRCS += pthread_cancel.c CSRCS += pthread_keycreate.c pthread_setspecific.c pthread_getspecific.c CSRCS += pthread_keydelete.c CSRCS += pthread_initialize.c pthread_completejoin.c pthread_findjoininfo.c diff --git a/sched/task/Make.defs b/sched/task/Make.defs index e173a8b246..9819db2879 100644 --- a/sched/task/Make.defs +++ b/sched/task/Make.defs @@ -35,8 +35,9 @@ CSRCS += task_create.c task_init.c task_setup.c task_activate.c CSRCS += task_start.c task_delete.c task_exit.c task_exithook.c -CSRCS += task_recover.c task_restart.c task_spawnparms.c task_terminate.c -CSRCS += task_getgroup.c task_prctl.c task_getpid.c exit.c +CSRCS += task_getgroup.c task_getpid.c task_prctl.c task_recover.c +CSRCS += task_restart.c task_spawnparms.c task_setcancelstate.c +CSRCS += task_terminate.c exit.c ifeq ($(CONFIG_ARCH_HAVE_VFORK),y) ifeq ($(CONFIG_SCHED_WAITPID),y) diff --git a/sched/pthread/pthread_setcancelstate.c b/sched/task/task_setcancelstate.c similarity index 77% rename from sched/pthread/pthread_setcancelstate.c rename to sched/task/task_setcancelstate.c index bcc5d24f6b..c8fc0460c4 100644 --- a/sched/pthread/pthread_setcancelstate.c +++ b/sched/task/task_setcancelstate.c @@ -1,7 +1,7 @@ /**************************************************************************** - * sched/pthread/pthread_setcancelstate.c + * sched/task/task_setcancelstate.c * - * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. + * Copyright (C) 2007, 2008, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -39,33 +39,39 @@ #include -#include #include -#include "task/task.h" #include "sched/sched.h" +#include "task/task.h" /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: pthread_setcancelstate + * Name: task_setcancelstate * * Description: - * The pthread_setcancelstate() function atomically both sets the calling - * thread's cancelability state to the indicated state and returns the + * The task_setcancelstate() function atomically both sets the calling + * task's cancelability state to the indicated state and returns the * previous cancelability state at the location referenced by oldstate. - * Legal values for state are PTHREAD_CANCEL_ENABLE and - * PTHREAD_CANCEL_DISABLE. + * Legal values for state are TASK_CANCEL_ENABLE and TASK_CANCEL_DISABLE. + * + * The cancelability state and type of any newly created tasks are + * TASK_CANCEL_ENABLE and TASK_CANCEL_DEFERRED respectively. * - * The cancelability state and type of any newly created threads, - * including the thread in which main() was first invoked, are - * PTHREAD_CANCEL_ENABLE and PTHREAD_CANCEL_DEFERRED respectively. + * Input Parameters: + * state - the new cancellability state, either TASK_CANCEL_ENABLE or + * TASK_CANCEL_DISABLE + * oldstate - The location to return the old cancellability state. + * + * Returned Value: + * Zero (OK) on success; ERROR is returned on any failure with the + * errno value set appropriately. * ****************************************************************************/ -int pthread_setcancelstate(int state, FAR int *oldstate) +int task_setcancelstate(int state, FAR int *oldstate) { FAR struct tcb_s *tcb = this_task(); int ret = OK; @@ -124,7 +130,17 @@ int pthread_setcancelstate(int state, FAR int *oldstate) */ tcb->flags &= ~TCB_FLAG_CANCEL_PENDING; - pthread_exit(PTHREAD_CANCELED); + +#ifndef CONFIG_DISABLE_PTHREAD + if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD) + { + pthread_exit(PTHREAD_CANCELED); + } + else +#endif + { + exit(EXIT_FAILURE); + } } } } @@ -136,7 +152,8 @@ int pthread_setcancelstate(int state, FAR int *oldstate) } else { - ret = EINVAL; + set_errno(EINVAL); + ret = ERROR; } sched_unlock(); diff --git a/syscall/syscall.csv b/syscall/syscall.csv index 19ff12aed6..0687ee4d4d 100644 --- a/syscall/syscall.csv +++ b/syscall/syscall.csv @@ -89,7 +89,6 @@ "pthread_mutex_unlock","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_mutex_t*" "pthread_once","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_once_t*","CODE void (*)(void)" "pthread_setaffinity_np","pthread.h","!defined(CONFIG_DISABLE_PTHREAD) && defined(CONFIG_SMP)","int","pthread_t","size_t","FAR const cpu_set_t*" -"pthread_setcancelstate","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","int","FAR int*" "pthread_setcanceltype","pthread.h","!defined(CONFIG_DISABLE_PTHREAD) && defined(CONFIG_CANCELLATION_POINTS)","int","int","FAR int*" "pthread_setschedparam","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_t","int","FAR const struct sched_param*" "pthread_setschedprio","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_t","int" @@ -152,6 +151,7 @@ #"task_create","sched.h","","int","const char*","int","main_t","FAR char * const []|FAR char * const *" "task_delete","sched.h","","int","pid_t" "task_restart","sched.h","","int","pid_t" +"task_setcancelstate","sched.h","","int","int","FAR int*" "telldir","dirent.h","CONFIG_NFILE_DESCRIPTORS > 0","off_t","FAR DIR*" "timer_create","time.h","!defined(CONFIG_DISABLE_POSIX_TIMERS)","int","clockid_t","FAR struct sigevent*","FAR timer_t*" "timer_delete","time.h","!defined(CONFIG_DISABLE_POSIX_TIMERS)","int","timer_t" diff --git a/syscall/syscall_lookup.h b/syscall/syscall_lookup.h index 9381c36b0c..f7e2165351 100644 --- a/syscall/syscall_lookup.h +++ b/syscall/syscall_lookup.h @@ -86,6 +86,7 @@ SYSCALL_LOOKUP(pgalloc, 2, STUB_pgalloc) #endif SYSCALL_LOOKUP(task_delete, 1, STUB_task_delete) SYSCALL_LOOKUP(task_restart, 1, STUB_task_restart) +SYSCALL_LOOKUP(task_setcancelstate, 2, STUB_task_setcancelstate) SYSCALL_LOOKUP(up_assert, 2, STUB_up_assert) /* The following can be individually enabled */ @@ -290,7 +291,6 @@ SYSCALL_LOOKUP(up_assert, 2, STUB_up_assert) SYSCALL_LOOKUP(pthread_mutex_trylock, 1, STUB_pthread_mutex_trylock) SYSCALL_LOOKUP(pthread_mutex_unlock, 1, STUB_pthread_mutex_unlock) SYSCALL_LOOKUP(pthread_once, 2, STUB_pthread_once) - SYSCALL_LOOKUP(pthread_setcancelstate, 2, STUB_pthread_setcancelstate) SYSCALL_LOOKUP(pthread_setschedparam, 3, STUB_pthread_setschedparam) SYSCALL_LOOKUP(pthread_setschedprio, 2, STUB_pthread_setschedprio) SYSCALL_LOOKUP(pthread_setspecific, 2, STUB_pthread_setspecific) diff --git a/syscall/syscall_stublookup.c b/syscall/syscall_stublookup.c index 3004dedcce..34e60fd1fa 100644 --- a/syscall/syscall_stublookup.c +++ b/syscall/syscall_stublookup.c @@ -96,6 +96,8 @@ uintptr_t STUB_task_create(int nbr, uintptr_t parm1, uintptr_t parm2, uintptr_t parm3, uintptr_t parm4, uintptr_t parm5); uintptr_t STUB_task_delete(int nbr, uintptr_t parm1); uintptr_t STUB_task_restart(int nbr, uintptr_t parm1); +uintptr_t STUB_task_setcancelstate(int nbr, uintptr_t parm1, + uintptr_t parm2); uintptr_t STUB_up_assert(int nbr, uintptr_t parm1, uintptr_t parm2); /* The following can be individually enabled */ @@ -290,8 +292,6 @@ uintptr_t STUB_pthread_mutex_lock(int nbr, uintptr_t parm1); uintptr_t STUB_pthread_mutex_trylock(int nbr, uintptr_t parm1); uintptr_t STUB_pthread_mutex_unlock(int nbr, uintptr_t parm1); uintptr_t STUB_pthread_once(int nbr, uintptr_t parm1, uintptr_t parm2); -uintptr_t STUB_pthread_setcancelstate(int nbr, uintptr_t parm1, - uintptr_t parm2); uintptr_t STUB_pthread_setschedparam(int nbr, uintptr_t parm1, uintptr_t parm2, uintptr_t parm3); uintptr_t STUB_pthread_setschedprio(int nbr, uintptr_t parm1, -- GitLab From f132960789ea8a1cf58ce05d5e009cf3e43046fb Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 10 Dec 2016 16:06:14 -0600 Subject: [PATCH 671/734] Add task_setcanceltype() --- Documentation/NuttxUserGuide.html | 143 ++++++++++++------ include/sched.h | 25 ++- include/sys/syscall.h | 13 +- libc/pthread/Make.defs | 3 +- libc/pthread/pthread_setcanceltype.c | 29 +++- libc/sched/Make.defs | 4 + sched/pthread/Make.defs | 2 +- sched/task/Make.defs | 4 + sched/task/task_setcancelstate.c | 39 ++--- .../task_setcanceltype.c} | 39 +++-- syscall/syscall.csv | 2 +- syscall/syscall_lookup.h | 5 +- syscall/syscall_stublookup.c | 5 +- 13 files changed, 211 insertions(+), 102 deletions(-) rename sched/{pthread/pthread_setcanceltype.c => task/task_setcanceltype.c} (80%) diff --git a/Documentation/NuttxUserGuide.html b/Documentation/NuttxUserGuide.html index 9efb520f46..a3a911b919 100644 --- a/Documentation/NuttxUserGuide.html +++ b/Documentation/NuttxUserGuide.html @@ -204,50 +204,51 @@ paragraphs.
  • 2.1.4 task_delete
  • 2.1.5 task_restart
  • 2.1.6 task_setcancelstate
    • +
  • 2.1.7 task_setcanceltype

    • Standard interfaces

    Standard vfork and exec[v|l] interfaces:

    Standard posix_spawn interfaces:

    Non-standard task control interfaces inspired by posix_spawn:

    2.1.1 task_create

    @@ -609,8 +610,6 @@ VxWorks provides the following similar interface:

    Description: -

    -

    The task_setcancelstate() function atomically sets both the calling task's cancelability state to the indicated state and returns the previous cancelability state at the location @@ -651,7 +650,50 @@ No thread could be found corresponding to that specified by the given thread ID. POSIX Compatibility: This is a non-standard interface. It extends the functionality of pthread_setcancelstate() to tasks and supports use of task_delete.

    -

    2.1.7 exit

    +

    2.1.7 task_setcanceltype

    +

    +Function Prototype: +

    +

    +    #include <sched.h>
+    int task_setcanceltype(int type, FAR int *oldtype);
+
    +

    +Description: +The task_setcanceltype() function atomically both sets the calling task's cancelability type to the indicated type and returns the previous cancelability type at the location referenced by oldtype. +Legal values for type are TASK_CANCEL_DEFERRED and TASK_CANCEL_ASYNCHRONOUS. +

    +

    +The cancelability state and type of any newly created tasks are TASK_CANCEL_ENABLE and TASK_CANCEL_DEFERRED respectively. +

    +

    +Input Parameters: +

    +

    +

      +
    • type +New cancellation state. One of PTHREAD_CANCEL_DEFERRED or PTHREAD_CANCEL_ASYNCHRONOUS.
      • +
    • oldtype. +Location to return the previous cancellation type. +
    +

    +

    +Returned Value: +

    +

    +Zero (OK) on success; ERROR is returned on any failure with the errno value set appropriately: +

    +

    +

      +
    • ESRCH. +No thread could be found corresponding to that specified by the given thread ID.
      • +
    +

    +

    +POSIX Compatibility: This is a non-standard interface. It extends the functionality of pthread_setcanceltype() to tasks and supports use of task_delete. +

    + +

    2.1.8 exit

    Function Prototype: @@ -697,7 +739,7 @@ And the UNIX interface:

  • The code parameter is ignored. -

    2.1.8 getpid

    +

    2.1.9 getpid

    Function Prototype: @@ -725,7 +767,7 @@ level. Compatible with the POSIX interface of the same name.

    -

    2.1.9 vfork

    +

    2.1.10 vfork

    Function Prototype:

    @@ -759,7 +801,7 @@ pid_t vfork(void); Compatible with the Unix interface of the same name.

    -

    2.1.10 execv

    +

    2.1.11 execv

    Function Prototype:

    @@ -845,7 +887,7 @@ int execv(FAR const char *path, FAR char *const argv[]); There are, however, several compatibility issues as detailed in the description above.

    -

    2.1.11 execl

    +

    2.1.12 execl

    Function Prototype:

    @@ -889,7 +931,7 @@ int execl(FAR const char *path, ...); There are, however, several compatibility issues as detailed in the description of execv().

    -

    2.1.12 posix_spawn and posix_spawnp

    +

    2.1.13 posix_spawn and posix_spawnp

    Function Prototype:

    @@ -1032,7 +1074,7 @@ int posix_spawnp(FAR pid_t *pid, FAR const char *file, For the caller of posix_spawn(), the provided argv[0] will correspond to argv[1] received by the new task.

    -

    2.1.13 posix_spawn_file_actions_init

    +

    2.1.14 posix_spawn_file_actions_init

    Function Prototype:

    @@ -1058,7 +1100,7 @@ int posix_spawn_file_actions_init(FAR posix_spawn_file_actions_t *file_actions); On success, this function returns 0; on failure it will return an error number from <errno.h>.

    -

    2.1.14 posix_spawn_file_actions_destroy

    +

    2.1.15 posix_spawn_file_actions_destroy

    Function Prototype:

    @@ -1085,7 +1127,7 @@ int posix_spawn_file_actions_destroy(FAR posix_spawn_file_actions_t *file_action On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.15 posix_spawn_file_actions_addclose

    +

    2.1.16 posix_spawn_file_actions_addclose

    Function Prototype:

    @@ -1116,7 +1158,7 @@ int posix_spawn_file_actions_addclose(FAR posix_spawn_file_actions_t *file_actio On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.16 posix_spawn_file_actions_adddup2

    +

    2.1.17 posix_spawn_file_actions_adddup2

    Function Prototype:

    @@ -1153,7 +1195,7 @@ int posix_spawn_file_actions_adddup2(FAR posix_spawn_file_actions_t *file_action On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.17 posix_spawn_file_actions_addopen

    +

    2.1.18 posix_spawn_file_actions_addopen

    Function Prototype:

    @@ -1198,7 +1240,7 @@ int posix_spawn_file_actions_addopen(FAR posix_spawn_file_actions_t *file_action On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.18 posix_spawnattr_init

    +

    2.1.19 posix_spawnattr_init

    Function Prototype:

    @@ -1234,7 +1276,7 @@ int posix_spawnattr_init(FAR posix_spawnattr_t *attr); On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.19 posix_spawnattr_getflags

    +

    2.1.20 posix_spawnattr_getflags

    Function Prototype:

    @@ -1264,7 +1306,7 @@ int posix_spawnattr_getflags(FAR const posix_spawnattr_t *attr, FAR short *flags On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.20 posix_spawnattr_getschedparam

    +

    2.1.21 posix_spawnattr_getschedparam

    Function Prototype:

    @@ -1294,7 +1336,7 @@ int posix_spawnattr_getschedparam(FAR const posix_spawnattr_t *attr, FAR struct On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.21 posix_spawnattr_getschedpolicy

    +

    2.1.22 posix_spawnattr_getschedpolicy

    Function Prototype:

    @@ -1324,7 +1366,7 @@ int posix_spawnattr_getschedpolicy(FAR const posix_spawnattr_t *attr, FAR int *p On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.22 posix_spawnattr_getsigmask

    +

    2.1.23 posix_spawnattr_getsigmask

    Function Prototype:

    @@ -1356,7 +1398,7 @@ int posix_spawnattr_getsigmask(FAR const posix_spawnattr_t *attr, FAR sigset_t * On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.23 posix_spawnattr_setflags

    +

    2.1.24 posix_spawnattr_setflags

    Function Prototype:

    @@ -1386,7 +1428,7 @@ int posix_spawnattr_setflags(FAR posix_spawnattr_t *attr, short flags); On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.24 posix_spawnattr_setschedparam

    +

    2.1.25 posix_spawnattr_setschedparam

    Function Prototype:

    @@ -1416,7 +1458,7 @@ int posix_spawnattr_setschedparam(FAR posix_spawnattr_t *attr, FAR const struct On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.25 posix_spawnattr_setschedpolicy

    +

    2.1.26 posix_spawnattr_setschedpolicy

    Function Prototype:

    @@ -1446,7 +1488,7 @@ int posix_spawnattr_setschedpolicy(FAR posix_spawnattr_t *attr, int policy); On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.26 posix_spawnattr_setsigmask

    +

    2.1.27 posix_spawnattr_setsigmask

    Function Prototype:

    @@ -1478,7 +1520,7 @@ int posix_spawnattr_setsigmask(FAR posix_spawnattr_t *attr, FAR const sigset_t * On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.27 task_spawn

    +

    2.1.28 task_spawn

    Function Prototype:

    @@ -1592,7 +1634,7 @@ int task_spawn(FAR pid_t *pid, FAR const char *name, main_t entry, This is a non-standard interface inspired by posix_spawn().

    -

    2.1.28 task_spawnattr_getstacksize

    +

    2.1.29 task_spawnattr_getstacksize

    Function Prototype:

    @@ -1622,7 +1664,7 @@ int task_spawnattr_getstacksize(FAR const posix_spawnattr_t *attr, FAR size_t *s On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.29 task_spawnattr_setstacksize

    +

    2.1.30 task_spawnattr_setstacksize

    Function Prototype:

    @@ -1652,7 +1694,7 @@ int task_spawnattr_setstacksize(FAR posix_spawnattr_t *attr, size_t stacksize); On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.30 posix_spawn_file_actions_init

    +

    2.1.31 posix_spawn_file_actions_init

    Function Prototype:

    @@ -10323,6 +10365,7 @@ notify a task when a message is available on a queue.
  • task_restart
  • Task Scheduling Interfaces
  • task_setcancelstate
    • +
  • task_spawn
  • task_spawnattr_getstacksize
  • task_spawnattr_setstacksize
    • diff --git a/include/sched.h b/include/sched.h index 44877c2341..f0e1195911 100644 --- a/include/sched.h +++ b/include/sched.h @@ -54,18 +54,30 @@ /* POSIX-like scheduling policies */ -#define SCHED_FIFO 1 /* FIFO priority scheduling policy */ -#define SCHED_RR 2 /* Round robin scheduling policy */ -#define SCHED_SPORADIC 3 /* Sporadic scheduling policy */ -#define SCHED_OTHER 4 /* Not supported */ +#define SCHED_FIFO 1 /* FIFO priority scheduling policy */ +#define SCHED_RR 2 /* Round robin scheduling policy */ +#define SCHED_SPORADIC 3 /* Sporadic scheduling policy */ +#define SCHED_OTHER 4 /* Not supported */ /* Maximum number of SCHED_SPORADIC replenishments */ -#define SS_REPL_MAX CONFIG_SCHED_SPORADIC_MAXREPL +#define SS_REPL_MAX CONFIG_SCHED_SPORADIC_MAXREPL + +/* Cancellation definitions *****************************************************/ + +/* Cancellation states used by task_setcancelstate() */ + +#define TASK_CANCEL_ENABLE (0) +#define TASK_CANCEL_DISABLE (1) + +/* Cancellation types used by task_setcanceltype() */ + +#define TASK_CANCEL_DEFERRED (0) +#define TASK_CANCEL_ASYNCHRONOUS (1) /* Pthread definitions **********************************************************/ -#define PTHREAD_KEYS_MAX CONFIG_NPTHREAD_KEYS +#define PTHREAD_KEYS_MAX CONFIG_NPTHREAD_KEYS /* CPU affinity mask helpers ***************************************************/ /* These are not standard but are defined for Linux compatibility */ @@ -230,6 +242,7 @@ int task_delete(pid_t pid); int task_restart(pid_t pid); int task_setcancelstate(int state, FAR int *oldstate); +int task_setcanceltype(int type, FAR int *oldtype); /* Task Scheduling Interfaces (based on POSIX APIs) */ diff --git a/include/sys/syscall.h b/include/sys/syscall.h index 06aa183658..f0533b6289 100644 --- a/include/sys/syscall.h +++ b/include/sys/syscall.h @@ -130,7 +130,13 @@ # define SYS_task_restart (__SYS_task_delete+1) # define SYS_task_setcancelstate (__SYS_task_delete+2) # define SYS_up_assert (__SYS_task_delete+3) -# define __SYS_vfork (__SYS_task_delete+4) + +# ifdef CONFIG_CANCELLATION_POINTS +# define SYS_pthread_setcanceltype (__SYS_task_delete+4) +# define __SYS_vfork (__SYS_task_delete+5) +# else +# define __SYS_vfork (__SYS_task_delete+4) +# endif /* The following can be individually enabled */ @@ -407,9 +413,8 @@ # define SYS_pthread_yield (__SYS_pthread+26) # ifdef CONFIG_CANCELLATION_POINTS -# define SYS_pthread_setcanceltype (__SYS_pthread+27) -# define SYS_pthread_testcancel (__SYS_pthread+28) -# define __SYS_pthread_smp (__SYS_pthread+29) +# define SYS_pthread_testcancel (__SYS_pthread+27) +# define __SYS_pthread_smp (__SYS_pthread+28) # else # define __SYS_pthread_smp (__SYS_pthread+27) # endif diff --git a/libc/pthread/Make.defs b/libc/pthread/Make.defs index 60ae02b59a..c530947fbc 100644 --- a/libc/pthread/Make.defs +++ b/libc/pthread/Make.defs @@ -47,9 +47,10 @@ CSRCS += pthread_mutexattr_init.c pthread_mutexattr_destroy.c CSRCS += pthread_mutexattr_getpshared.c pthread_mutexattr_setpshared.c CSRCS += pthread_mutexattr_setprotocol.c pthread_mutexattr_getprotocol.c CSRCS += pthread_mutexattr_settype.c pthread_mutexattr_gettype.c +CSRCS += pthread_setcancelstate.c pthread_setcanceltype.c ifneq ($(CONFIG_CANCELLATION_POINTS),y) -CSRCS += pthread_setcanceltype.c pthread_testcancel.c +CSRCS += pthread_testcancel.c endif ifeq ($(CONFIG_SMP),y) diff --git a/libc/pthread/pthread_setcanceltype.c b/libc/pthread/pthread_setcanceltype.c index 0565367b1b..583376dfcc 100644 --- a/libc/pthread/pthread_setcanceltype.c +++ b/libc/pthread/pthread_setcanceltype.c @@ -38,8 +38,24 @@ ****************************************************************************/ #include +#include #include +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* The following are defined in different header files but must have the + * same values. + */ + +#if PTHREAD_CANCEL_DEFERRED != TASK_CANCEL_DEFERRED +# error We must have PTHREAD_CANCEL_DEFERRED == TASK_CANCEL_DEFERRED +#endif + +#if PTHREAD_CANCEL_ASYNCHRONOUS != TASK_CANCEL_ASYNCHRONOUS +# error We must have PTHREAD_CANCEL_ASYNCHRONOUS == TASK_CANCEL_ASYNCHRONOUS +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -62,14 +78,15 @@ int pthread_setcanceltype(int type, FAR int *oldtype) { - /* Return the current type if so requrested */ + int ret; + + /* task_setcanceltype() can do this */ - if (oldtype != NULL) + ret = task_setcanceltype(type, oldtype); + if (ret < 0) { - *oldtype = PTHREAD_CANCEL_ASYNCHRONOUS; + ret = errno; } - /* Check the requested cancellation type */ - - return (type == PTHREAD_CANCEL_ASYNCHRONOUS) ? OK : ENOSYS; + return ret; } diff --git a/libc/sched/Make.defs b/libc/sched/Make.defs index eeb4be1c1b..b7402aea05 100644 --- a/libc/sched/Make.defs +++ b/libc/sched/Make.defs @@ -37,6 +37,10 @@ CSRCS += sched_getprioritymax.c sched_getprioritymin.c +ifneq ($(CONFIG_CANCELLATION_POINTS),y) +CSRCS += task_setcanceltype.c +endif + ifeq ($(CONFIG_SMP),y) CSRCS += sched_cpucount.c endif diff --git a/sched/pthread/Make.defs b/sched/pthread/Make.defs index 362a6d63bf..1970de7804 100644 --- a/sched/pthread/Make.defs +++ b/sched/pthread/Make.defs @@ -53,7 +53,7 @@ CSRCS += pthread_condtimedwait.c pthread_kill.c pthread_sigmask.c endif ifeq ($(CONFIG_CANCELLATION_POINTS),y) -CSRCS += pthread_setcanceltype.c pthread_testcancel.c +CSRCS += pthread_testcancel.c endif ifeq ($(CONFIG_SMP),y) diff --git a/sched/task/Make.defs b/sched/task/Make.defs index 9819db2879..b2543fccdd 100644 --- a/sched/task/Make.defs +++ b/sched/task/Make.defs @@ -49,6 +49,10 @@ ifneq ($(CONFIG_BUILD_KERNEL),y) CSRCS += task_spawn.c endif +ifeq ($(CONFIG_CANCELLATION_POINTS),y) +CSRCS += task_setcanceltype.c +endif + ifneq ($(CONFIG_BINFMT_DISABLE),y) ifeq ($(CONFIG_LIBC_EXECFUNCS),y) CSRCS += task_execv.c task_posixspawn.c diff --git a/sched/task/task_setcancelstate.c b/sched/task/task_setcancelstate.c index c8fc0460c4..d7003f3af7 100644 --- a/sched/task/task_setcancelstate.c +++ b/sched/task/task_setcancelstate.c @@ -39,6 +39,9 @@ #include +#include +#include +#include #include #include "sched/sched.h" @@ -88,17 +91,17 @@ int task_setcancelstate(int state, FAR int *oldstate) { if ((tcb->flags & TCB_FLAG_NONCANCELABLE) != 0) { - *oldstate = PTHREAD_CANCEL_DISABLE; + *oldstate = TASK_CANCEL_DISABLE; } else { - *oldstate = PTHREAD_CANCEL_ENABLE; + *oldstate = TASK_CANCEL_ENABLE; } } /* Set the new cancellation state */ - if (state == PTHREAD_CANCEL_ENABLE) + if (state == TASK_CANCEL_ENABLE) { /* Clear the non-cancelable flag */ @@ -124,27 +127,27 @@ int task_setcancelstate(int state, FAR int *oldstate) } else #endif - { - /* No.. We are using asynchronous cancellation. If the - * cancellation was pending in this case, then just exit. - */ + { + /* No.. We are using asynchronous cancellation. If the + * cancellation was pending in this case, then just exit. + */ - tcb->flags &= ~TCB_FLAG_CANCEL_PENDING; + tcb->flags &= ~TCB_FLAG_CANCEL_PENDING; #ifndef CONFIG_DISABLE_PTHREAD - if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD) - { - pthread_exit(PTHREAD_CANCELED); - } - else + if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD) + { + pthread_exit(PTHREAD_CANCELED); + } + else #endif - { - exit(EXIT_FAILURE); - } - } + { + exit(EXIT_FAILURE); + } + } } } - else if (state == PTHREAD_CANCEL_DISABLE) + else if (state == TASK_CANCEL_DISABLE) { /* Set the non-cancelable state */ diff --git a/sched/pthread/pthread_setcanceltype.c b/sched/task/task_setcanceltype.c similarity index 80% rename from sched/pthread/pthread_setcanceltype.c rename to sched/task/task_setcanceltype.c index ba3704cd2a..b7536f4625 100644 --- a/sched/pthread/pthread_setcanceltype.c +++ b/sched/task/task_setcanceltype.c @@ -1,5 +1,5 @@ /**************************************************************************** - * sched/pthread/pthread_setcanceltype.c + * sched/task/task_setcanceltype.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -39,32 +39,35 @@ #include +#include #include +#include #include #include "sched/sched.h" +#include "task/task.h" /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: pthread_setcancelstate + * Name: task_setcancelstate * * Description: - * The pthread_setcanceltype() function atomically both sets the calling + * The task_setcanceltype() function atomically both sets the calling * thread's cancelability type to the indicated type and returns the * previous cancelability type at the location referenced by oldtype - * Legal values for type are PTHREAD_CANCEL_DEFERRED and - * PTHREAD_CANCEL_ASYNCHRONOUS. + * Legal values for type are TASK_CANCEL_DEFERRED and + * TASK_CANCEL_ASYNCHRONOUS. * * The cancelability state and type of any newly created threads, * including the thread in which main() was first invoked, are - * PTHREAD_CANCEL_ENABLE and PTHREAD_CANCEL_DEFERRED respectively. + * TASK_CANCEL_ENABLE and TASK_CANCEL_DEFERRED respectively. * ****************************************************************************/ -int pthread_setcanceltype(int type, FAR int *oldtype) +int task_setcanceltype(int type, FAR int *oldtype) { FAR struct tcb_s *tcb = this_task(); int ret = OK; @@ -81,17 +84,17 @@ int pthread_setcanceltype(int type, FAR int *oldtype) { if ((tcb->flags & TCB_FLAG_CANCEL_DEFERRED) != 0) { - *oldtype = PTHREAD_CANCEL_DEFERRED; + *oldtype = TASK_CANCEL_DEFERRED; } else { - *oldtype = PTHREAD_CANCEL_ASYNCHRONOUS; + *oldtype = TASK_CANCEL_ASYNCHRONOUS; } } /* Set the new cancellation type */ - if (type == PTHREAD_CANCEL_ASYNCHRONOUS) + if (type == TASK_CANCEL_ASYNCHRONOUS) { /* Clear the deferred cancellation bit */ @@ -106,12 +109,24 @@ int pthread_setcanceltype(int type, FAR int *oldtype) (tcb->flags & TCB_FLAG_NONCANCELABLE) == 0) { tcb->flags &= ~TCB_FLAG_CANCEL_PENDING; - pthread_exit(PTHREAD_CANCELED); + + /* Exit according to the type of the thread */ + +#ifndef CONFIG_DISABLE_PTHREAD + if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_PTHREAD) + { + pthread_exit(PTHREAD_CANCELED); + } + else +#endif + { + exit(EXIT_FAILURE); + } } #endif } #ifdef CONFIG_CANCELLATION_POINTS - else if (type == PTHREAD_CANCEL_DEFERRED) + else if (type == TASK_CANCEL_DEFERRED) { /* Set the deferred cancellation type */ diff --git a/syscall/syscall.csv b/syscall/syscall.csv index 0687ee4d4d..42706b701f 100644 --- a/syscall/syscall.csv +++ b/syscall/syscall.csv @@ -89,7 +89,6 @@ "pthread_mutex_unlock","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_mutex_t*" "pthread_once","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_once_t*","CODE void (*)(void)" "pthread_setaffinity_np","pthread.h","!defined(CONFIG_DISABLE_PTHREAD) && defined(CONFIG_SMP)","int","pthread_t","size_t","FAR const cpu_set_t*" -"pthread_setcanceltype","pthread.h","!defined(CONFIG_DISABLE_PTHREAD) && defined(CONFIG_CANCELLATION_POINTS)","int","int","FAR int*" "pthread_setschedparam","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_t","int","FAR const struct sched_param*" "pthread_setschedprio","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_t","int" "pthread_setspecific","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_key_t","FAR const void*" @@ -152,6 +151,7 @@ "task_delete","sched.h","","int","pid_t" "task_restart","sched.h","","int","pid_t" "task_setcancelstate","sched.h","","int","int","FAR int*" +"task_setcanceltype","sched.h","defined(CONFIG_CANCELLATION_POINTS)","int","int","FAR int*" "telldir","dirent.h","CONFIG_NFILE_DESCRIPTORS > 0","off_t","FAR DIR*" "timer_create","time.h","!defined(CONFIG_DISABLE_POSIX_TIMERS)","int","clockid_t","FAR struct sigevent*","FAR timer_t*" "timer_delete","time.h","!defined(CONFIG_DISABLE_POSIX_TIMERS)","int","timer_t" diff --git a/syscall/syscall_lookup.h b/syscall/syscall_lookup.h index f7e2165351..abd056fe37 100644 --- a/syscall/syscall_lookup.h +++ b/syscall/syscall_lookup.h @@ -89,6 +89,10 @@ SYSCALL_LOOKUP(task_restart, 1, STUB_task_restart) SYSCALL_LOOKUP(task_setcancelstate, 2, STUB_task_setcancelstate) SYSCALL_LOOKUP(up_assert, 2, STUB_up_assert) +# ifdef CONFIG_CANCELLATION_POINTS + SYSCALL_LOOKUP(task_setcanceltype, 2, STUB_task_setcanceltype) +# endif + /* The following can be individually enabled */ #ifdef CONFIG_ARCH_HAVE_VFORK @@ -296,7 +300,6 @@ SYSCALL_LOOKUP(up_assert, 2, STUB_up_assert) SYSCALL_LOOKUP(pthread_setspecific, 2, STUB_pthread_setspecific) SYSCALL_LOOKUP(pthread_yield, 0, STUB_pthread_yield) # ifdef CONFIG_CANCELLATION_POINTS - SYSCALL_LOOKUP(pthread_setcanceltype, 2, STUB_pthread_setcanceltype) SYSCALL_LOOKUP(pthread_testcancel, 0, STUB_pthread_testcancel) # endif # ifdef CONFIG_SMP diff --git a/syscall/syscall_stublookup.c b/syscall/syscall_stublookup.c index 34e60fd1fa..61ccb8ecd6 100644 --- a/syscall/syscall_stublookup.c +++ b/syscall/syscall_stublookup.c @@ -100,6 +100,9 @@ uintptr_t STUB_task_setcancelstate(int nbr, uintptr_t parm1, uintptr_t parm2); uintptr_t STUB_up_assert(int nbr, uintptr_t parm1, uintptr_t parm2); +uintptr_t STUB_task_setcanceltype(int nbr, uintptr_t parm1, + uintptr_t parm2); + /* The following can be individually enabled */ uintptr_t STUB_vfork(int nbr); @@ -300,8 +303,6 @@ uintptr_t STUB_pthread_setspecific(int nbr, uintptr_t parm1, uintptr_t parm2); uintptr_t STUB_pthread_yield(int nbr); -uintptr_t STUB_pthread_setcanceltype(int nbr, uintptr_t parm1, - uintptr_t parm2); uintptr_t STUB_pthread_testcancel(int nbr); uintptr_t STUB_pthread_setaffinity(int nbr, uintptr_t parm1, -- GitLab From 50a25c3fde42630378d26493bd20da9ca3f4f7c0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 10 Dec 2016 16:12:35 -0600 Subject: [PATCH 672/734] Forget to add files before last commits --- libc/pthread/pthread_setcancelstate.c | 92 +++++++++++++++++++++++++++ libc/sched/task_setcanceltype.c | 74 +++++++++++++++++++++ 2 files changed, 166 insertions(+) create mode 100644 libc/pthread/pthread_setcancelstate.c create mode 100644 libc/sched/task_setcanceltype.c diff --git a/libc/pthread/pthread_setcancelstate.c b/libc/pthread/pthread_setcancelstate.c new file mode 100644 index 0000000000..e81a4440f7 --- /dev/null +++ b/libc/pthread/pthread_setcancelstate.c @@ -0,0 +1,92 @@ +/**************************************************************************** + * libc/pthread/pthread_setcancelstate.c + * + * Copyright (C) 2007, 2008, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ +/* These are defined in different header files but must have the same values. */ + +#if PTHREAD_CANCEL_ENABLE != TASK_CANCEL_ENABLE +# error We must have PTHREAD_CANCEL_ENABLE == TASK_CANCEL_ENABLE +#endif + +#if PTHREAD_CANCEL_DISABLE != TASK_CANCEL_DISABLE +# error We must have PTHREAD_CANCEL_DISABLE == TASK_CANCEL_DISABLE +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pthread_setcancelstate + * + * Description: + * The pthread_setcancelstate() function atomically both sets the calling + * thread's cancelability state to the indicated state and returns the + * previous cancelability state at the location referenced by oldstate. + * Legal values for state are PTHREAD_CANCEL_ENABLE and + * PTHREAD_CANCEL_DISABLE. + * + * The cancelability state and type of any newly created threads, + * including the thread in which main() was first invoked, are + * PTHREAD_CANCEL_ENABLE and PTHREAD_CANCEL_DEFERRED respectively. + * + ****************************************************************************/ + +int pthread_setcancelstate(int state, FAR int *oldstate) +{ + int ret; + + /* task_setcancelstate() can do this */ + + ret = task_setcancelstate(state, oldstate); + if (ret < 0) + { + ret = errno; + } + + return ret; +} diff --git a/libc/sched/task_setcanceltype.c b/libc/sched/task_setcanceltype.c new file mode 100644 index 0000000000..d43f5d9d30 --- /dev/null +++ b/libc/sched/task_setcanceltype.c @@ -0,0 +1,74 @@ +/**************************************************************************** + * libc/sched/task_setcanceltype.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: task_setcancelstate + * + * Description: + * The task_setcanceltype() function atomically both sets the calling + * task's cancelability type to the indicated type and returns the + * previous cancelability type at the location referenced by oldtype + * Legal values for type are TASK_CANCEL_DEFERRED and + * TASK_CANCEL_ASYNCHRONOUS. + * + * The cancelability state and type of any newly created tasks are + * TASK_CANCEL_ENABLE and TASK_CANCEL_DEFERRED respectively. + * + ****************************************************************************/ + +int task_setcanceltype(int type, FAR int *oldtype) +{ + /* Return the current type if so requrested */ + + if (oldtype != NULL) + { + *oldtype = TASK_CANCEL_ASYNCHRONOUS; + } + + /* Check the requested cancellation type */ + + return (type == TASK_CANCEL_ASYNCHRONOUS) ? OK : ENOSYS; +} -- GitLab From d648f9c8b488cc80e3994d080106545a98a24aa9 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 10 Dec 2016 16:34:14 -0600 Subject: [PATCH 673/734] Add task_testcancel() --- Documentation/NuttxUserGuide.html | 130 +++++++++++------- TODO | 11 +- include/sched.h | 1 + include/sys/syscall.h | 13 +- libc/pthread/Make.defs | 3 - libc/pthread/pthread_testcancel.c | 4 + libc/sched/Make.defs | 2 +- libc/sched/task_testcancel.c | 58 ++++++++ sched/pthread/Make.defs | 4 - sched/task/Make.defs | 2 +- .../task_testcancel.c} | 14 +- syscall/syscall.csv | 2 +- syscall/syscall_lookup.h | 4 +- syscall/syscall_stublookup.c | 3 +- 14 files changed, 168 insertions(+), 83 deletions(-) create mode 100644 libc/sched/task_testcancel.c rename sched/{pthread/pthread_testcancel.c => task/task_testcancel.c} (89%) diff --git a/Documentation/NuttxUserGuide.html b/Documentation/NuttxUserGuide.html index a3a911b919..4a98bf50e4 100644 --- a/Documentation/NuttxUserGuide.html +++ b/Documentation/NuttxUserGuide.html @@ -205,50 +205,51 @@ paragraphs.
  • 2.1.5 task_restart
  • 2.1.6 task_setcancelstate
  • 2.1.7 task_setcanceltype
    • +
  • 2.1.8 task_testcancel

    • Standard interfaces

    Standard vfork and exec[v|l] interfaces:

    Standard posix_spawn interfaces:

    Non-standard task control interfaces inspired by posix_spawn:

    2.1.1 task_create

    @@ -647,7 +648,7 @@ No thread could be found corresponding to that specified by the given thread ID.

    Assumptions/Limitations:

    -POSIX Compatibility: This is a non-standard interface. It extends the functionality of pthread_setcancelstate() to tasks and supports use of task_delete. +POSIX Compatibility: This is a non-standard interface. It extends the functionality of pthread_setcancelstate() to tasks and supports use of task_delete().

    2.1.7 task_setcanceltype

    @@ -690,10 +691,38 @@ No thread could be found corresponding to that specified by the given thread ID.

    -POSIX Compatibility: This is a non-standard interface. It extends the functionality of pthread_setcanceltype() to tasks and supports use of task_delete. +POSIX Compatibility: This is a non-standard interface. It extends the functionality of pthread_setcanceltype() to tasks and supports use of task_delete().

    -

    2.1.8 exit

    +

    2.1.8 task_testcancel

    +

    +Function Prototype: +

    +

    +

    +    #include <sched.h>
+    void task_testcancel(void);
+
    +

    +

    +Description: +

    +

    +The task_testcancel() function creates a cancellation point in the calling task. +The task_testcancel() function has no effect if cancelability is disabled. +

    +

    +Input Parameters: None +

    +

    +Returned Value: None +

    +

    +POSIX Compatibility: This is a non-standard interface. It extends the functionality of pthread_testcancel() to tasks and supports use of task_delete(). +

    + + +

    2.1.9 exit

    Function Prototype: @@ -739,7 +768,7 @@ And the UNIX interface:

  • The code parameter is ignored. -

    2.1.9 getpid

    +

    2.1.10 getpid

    Function Prototype: @@ -767,7 +796,7 @@ level. Compatible with the POSIX interface of the same name.

    -

    2.1.10 vfork

    +

    2.1.11 vfork

    Function Prototype:

    @@ -801,7 +830,7 @@ pid_t vfork(void); Compatible with the Unix interface of the same name.

    -

    2.1.11 execv

    +

    2.1.12 execv

    Function Prototype:

    @@ -887,7 +916,7 @@ int execv(FAR const char *path, FAR char *const argv[]); There are, however, several compatibility issues as detailed in the description above.

    -

    2.1.12 execl

    +

    2.1.13 execl

    Function Prototype:

    @@ -931,7 +960,7 @@ int execl(FAR const char *path, ...); There are, however, several compatibility issues as detailed in the description of execv().

    -

    2.1.13 posix_spawn and posix_spawnp

    +

    2.1.14 posix_spawn and posix_spawnp

    Function Prototype:

    @@ -1074,7 +1103,7 @@ int posix_spawnp(FAR pid_t *pid, FAR const char *file, For the caller of posix_spawn(), the provided argv[0] will correspond to argv[1] received by the new task.

    -

    2.1.14 posix_spawn_file_actions_init

    +

    2.1.15 posix_spawn_file_actions_init

    Function Prototype:

    @@ -1100,7 +1129,7 @@ int posix_spawn_file_actions_init(FAR posix_spawn_file_actions_t *file_actions); On success, this function returns 0; on failure it will return an error number from <errno.h>.

    -

    2.1.15 posix_spawn_file_actions_destroy

    +

    2.1.16 posix_spawn_file_actions_destroy

    Function Prototype:

    @@ -1127,7 +1156,7 @@ int posix_spawn_file_actions_destroy(FAR posix_spawn_file_actions_t *file_action On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.16 posix_spawn_file_actions_addclose

    +

    2.1.17 posix_spawn_file_actions_addclose

    Function Prototype:

    @@ -1158,7 +1187,7 @@ int posix_spawn_file_actions_addclose(FAR posix_spawn_file_actions_t *file_actio On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.17 posix_spawn_file_actions_adddup2

    +

    2.1.18 posix_spawn_file_actions_adddup2

    Function Prototype:

    @@ -1195,7 +1224,7 @@ int posix_spawn_file_actions_adddup2(FAR posix_spawn_file_actions_t *file_action On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.18 posix_spawn_file_actions_addopen

    +

    2.1.19 posix_spawn_file_actions_addopen

    Function Prototype:

    @@ -1240,7 +1269,7 @@ int posix_spawn_file_actions_addopen(FAR posix_spawn_file_actions_t *file_action On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.19 posix_spawnattr_init

    +

    2.1.20 posix_spawnattr_init

    Function Prototype:

    @@ -1276,7 +1305,7 @@ int posix_spawnattr_init(FAR posix_spawnattr_t *attr); On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.20 posix_spawnattr_getflags

    +

    2.1.21 posix_spawnattr_getflags

    Function Prototype:

    @@ -1306,7 +1335,7 @@ int posix_spawnattr_getflags(FAR const posix_spawnattr_t *attr, FAR short *flags On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.21 posix_spawnattr_getschedparam

    +

    2.1.22 posix_spawnattr_getschedparam

    Function Prototype:

    @@ -1336,7 +1365,7 @@ int posix_spawnattr_getschedparam(FAR const posix_spawnattr_t *attr, FAR struct On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.22 posix_spawnattr_getschedpolicy

    +

    2.1.23 posix_spawnattr_getschedpolicy

    Function Prototype:

    @@ -1366,7 +1395,7 @@ int posix_spawnattr_getschedpolicy(FAR const posix_spawnattr_t *attr, FAR int *p On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.23 posix_spawnattr_getsigmask

    +

    2.1.24 posix_spawnattr_getsigmask

    Function Prototype:

    @@ -1398,7 +1427,7 @@ int posix_spawnattr_getsigmask(FAR const posix_spawnattr_t *attr, FAR sigset_t * On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.24 posix_spawnattr_setflags

    +

    2.1.25 posix_spawnattr_setflags

    Function Prototype:

    @@ -1428,7 +1457,7 @@ int posix_spawnattr_setflags(FAR posix_spawnattr_t *attr, short flags); On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.25 posix_spawnattr_setschedparam

    +

    2.1.26 posix_spawnattr_setschedparam

    Function Prototype:

    @@ -1458,7 +1487,7 @@ int posix_spawnattr_setschedparam(FAR posix_spawnattr_t *attr, FAR const struct On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.26 posix_spawnattr_setschedpolicy

    +

    2.1.27 posix_spawnattr_setschedpolicy

    Function Prototype:

    @@ -1488,7 +1517,7 @@ int posix_spawnattr_setschedpolicy(FAR posix_spawnattr_t *attr, int policy); On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.27 posix_spawnattr_setsigmask

    +

    2.1.28 posix_spawnattr_setsigmask

    Function Prototype:

    @@ -1520,7 +1549,7 @@ int posix_spawnattr_setsigmask(FAR posix_spawnattr_t *attr, FAR const sigset_t * On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.28 task_spawn

    +

    2.1.29 task_spawn

    Function Prototype:

    @@ -1634,7 +1663,7 @@ int task_spawn(FAR pid_t *pid, FAR const char *name, main_t entry, This is a non-standard interface inspired by posix_spawn().

    -

    2.1.29 task_spawnattr_getstacksize

    +

    2.1.30 task_spawnattr_getstacksize

    Function Prototype:

    @@ -1664,7 +1693,7 @@ int task_spawnattr_getstacksize(FAR const posix_spawnattr_t *attr, FAR size_t *s On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.30 task_spawnattr_setstacksize

    +

    2.1.31 task_spawnattr_setstacksize

    Function Prototype:

    @@ -1694,7 +1723,7 @@ int task_spawnattr_setstacksize(FAR posix_spawnattr_t *attr, size_t stacksize); On success, this function returns 0; on failure it will return an error number from <errno.h>

    -

    2.1.31 posix_spawn_file_actions_init

    +

    2.1.32 posix_spawn_file_actions_init

    Function Prototype:

    @@ -10370,6 +10399,7 @@ notify a task when a message is available on a queue.
  • task_spawnattr_getstacksize
  • task_spawnattr_setstacksize
  • Task Switching Interfaces +
  • task_testcancel
  • telldir
  • timer_create
  • timer_delete
    • diff --git a/TODO b/TODO index 263dce27e7..c208e56124 100644 --- a/TODO +++ b/TODO @@ -191,8 +191,15 @@ o Task/Scheduler (sched/) does not do asynchronous deletion but should rather do the same kind of synchronization such as the pthread cancellation points. In this configuration, none of the issues above - apply. It is only the asyncrhonous task deletion that cannot - be supported. + apply. It is only the asynchronous task deletion that cannot + be supported. These helper functions are also available to + help manage task deletion: + + int task_setcancelstate(int state, FAR int *oldstate); + int task_setcanceltype(int type, FAR int *oldtype); + void task_testcancel(void); + + Which are analogous to the similarly named pthread_ interfaces. Status: Open Priority: Low and not easily removable. diff --git a/include/sched.h b/include/sched.h index f0e1195911..f63c42201a 100644 --- a/include/sched.h +++ b/include/sched.h @@ -243,6 +243,7 @@ int task_restart(pid_t pid); int task_setcancelstate(int state, FAR int *oldstate); int task_setcanceltype(int type, FAR int *oldtype); +void task_testcancel(void); /* Task Scheduling Interfaces (based on POSIX APIs) */ diff --git a/include/sys/syscall.h b/include/sys/syscall.h index f0533b6289..8da2d8f968 100644 --- a/include/sys/syscall.h +++ b/include/sys/syscall.h @@ -132,8 +132,9 @@ # define SYS_up_assert (__SYS_task_delete+3) # ifdef CONFIG_CANCELLATION_POINTS -# define SYS_pthread_setcanceltype (__SYS_task_delete+4) -# define __SYS_vfork (__SYS_task_delete+5) +# define SYS_task_setcanceltype (__SYS_task_delete+4) +# define SYS_task_testcancel (__SYS_task_delete+5) +# define __SYS_vfork (__SYS_task_delete+6) # else # define __SYS_vfork (__SYS_task_delete+4) # endif @@ -411,13 +412,7 @@ # define SYS_pthread_setschedprio (__SYS_pthread+24) # define SYS_pthread_setspecific (__SYS_pthread+25) # define SYS_pthread_yield (__SYS_pthread+26) - -# ifdef CONFIG_CANCELLATION_POINTS -# define SYS_pthread_testcancel (__SYS_pthread+27) -# define __SYS_pthread_smp (__SYS_pthread+28) -# else -# define __SYS_pthread_smp (__SYS_pthread+27) -# endif +# define __SYS_pthread_smp (__SYS_pthread+27) # ifdef CONFIG_SMP # define SYS_pthread_setaffinity_np (__SYS_pthread_smp+0) diff --git a/libc/pthread/Make.defs b/libc/pthread/Make.defs index c530947fbc..f5eab2b943 100644 --- a/libc/pthread/Make.defs +++ b/libc/pthread/Make.defs @@ -48,10 +48,7 @@ CSRCS += pthread_mutexattr_getpshared.c pthread_mutexattr_setpshared.c CSRCS += pthread_mutexattr_setprotocol.c pthread_mutexattr_getprotocol.c CSRCS += pthread_mutexattr_settype.c pthread_mutexattr_gettype.c CSRCS += pthread_setcancelstate.c pthread_setcanceltype.c - -ifneq ($(CONFIG_CANCELLATION_POINTS),y) CSRCS += pthread_testcancel.c -endif ifeq ($(CONFIG_SMP),y) CSRCS += pthread_attr_getaffinity.c pthread_attr_setaffinity.c diff --git a/libc/pthread/pthread_testcancel.c b/libc/pthread/pthread_testcancel.c index 99bc76a56e..c5bf14aec4 100644 --- a/libc/pthread/pthread_testcancel.c +++ b/libc/pthread/pthread_testcancel.c @@ -38,6 +38,7 @@ ****************************************************************************/ #include +#include /**************************************************************************** * Public Functions @@ -55,4 +56,7 @@ void pthread_testcancel(void) { + /* task_testcancel() does the real work */ + + task_testcancel(); } diff --git a/libc/sched/Make.defs b/libc/sched/Make.defs index b7402aea05..5d875d3eac 100644 --- a/libc/sched/Make.defs +++ b/libc/sched/Make.defs @@ -38,7 +38,7 @@ CSRCS += sched_getprioritymax.c sched_getprioritymin.c ifneq ($(CONFIG_CANCELLATION_POINTS),y) -CSRCS += task_setcanceltype.c +CSRCS += task_setcanceltype.c task_testcancel.c endif ifeq ($(CONFIG_SMP),y) diff --git a/libc/sched/task_testcancel.c b/libc/sched/task_testcancel.c new file mode 100644 index 0000000000..0d99dbebbc --- /dev/null +++ b/libc/sched/task_testcancel.c @@ -0,0 +1,58 @@ +/**************************************************************************** + * libc/sched/task_testcancel.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: task_testcancel + * + * Description: + * The task_testcancel() function creates a cancellation point in the + * calling thread. The task_testcancel() function has no effect if + * cancelability is disabled + * + ****************************************************************************/ + +void task_testcancel(void) +{ +} diff --git a/sched/pthread/Make.defs b/sched/pthread/Make.defs index 1970de7804..6156dd5411 100644 --- a/sched/pthread/Make.defs +++ b/sched/pthread/Make.defs @@ -52,10 +52,6 @@ ifneq ($(CONFIG_DISABLE_SIGNALS),y) CSRCS += pthread_condtimedwait.c pthread_kill.c pthread_sigmask.c endif -ifeq ($(CONFIG_CANCELLATION_POINTS),y) -CSRCS += pthread_testcancel.c -endif - ifeq ($(CONFIG_SMP),y) CSRCS += pthread_setaffinity.c pthread_getaffinity.c endif diff --git a/sched/task/Make.defs b/sched/task/Make.defs index b2543fccdd..a5c2295692 100644 --- a/sched/task/Make.defs +++ b/sched/task/Make.defs @@ -50,7 +50,7 @@ CSRCS += task_spawn.c endif ifeq ($(CONFIG_CANCELLATION_POINTS),y) -CSRCS += task_setcanceltype.c +CSRCS += task_setcanceltype.c task_testcancel.c endif ifneq ($(CONFIG_BINFMT_DISABLE),y) diff --git a/sched/pthread/pthread_testcancel.c b/sched/task/task_testcancel.c similarity index 89% rename from sched/pthread/pthread_testcancel.c rename to sched/task/task_testcancel.c index d93af13807..b0407173e3 100644 --- a/sched/pthread/pthread_testcancel.c +++ b/sched/task/task_testcancel.c @@ -1,5 +1,5 @@ /**************************************************************************** - * sched/pthread/pthread_testcancel.c + * sched/task/task_testcancel.c * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -39,28 +39,28 @@ #include -#include +#include #include #include -#include "sched/sched.h" +#include "task/task.h" /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: pthread_testcancel + * Name: task_testcancel * * Description: - * The pthread_testcancel() function creates a cancellation point in the - * calling thread. The pthread_testcancel() function has no effect if + * The task_testcancel() function creates a cancellation point in the + * calling thread. The task_testcancel() function has no effect if * cancelability is disabled * ****************************************************************************/ -void pthread_testcancel(void) +void task_testcancel(void) { (void)enter_cancellation_point(); leave_cancellation_point(); diff --git a/syscall/syscall.csv b/syscall/syscall.csv index 42706b701f..4dbcc98227 100644 --- a/syscall/syscall.csv +++ b/syscall/syscall.csv @@ -93,7 +93,6 @@ "pthread_setschedprio","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_t","int" "pthread_setspecific","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_key_t","FAR const void*" "pthread_sigmask","pthread.h","!defined(CONFIG_DISABLE_SIGNALS) && !defined(CONFIG_DISABLE_PTHREAD)","int","int","FAR const sigset_t*","FAR sigset_t*" -"pthread_testcancel","pthread.h","!defined(CONFIG_DISABLE_PTHREAD) && defined(CONFIG_CANCELLATION_POINTS)","void" "pthread_yield","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","void" "putenv","stdlib.h","!defined(CONFIG_DISABLE_ENVIRON)","int","FAR const char*" "read","unistd.h","CONFIG_NSOCKET_DESCRIPTORS > 0 || CONFIG_NFILE_DESCRIPTORS > 0","ssize_t","int","FAR void*","size_t" @@ -152,6 +151,7 @@ "task_restart","sched.h","","int","pid_t" "task_setcancelstate","sched.h","","int","int","FAR int*" "task_setcanceltype","sched.h","defined(CONFIG_CANCELLATION_POINTS)","int","int","FAR int*" +"task_testcancel","pthread.h","defined(CONFIG_CANCELLATION_POINTS)","void" "telldir","dirent.h","CONFIG_NFILE_DESCRIPTORS > 0","off_t","FAR DIR*" "timer_create","time.h","!defined(CONFIG_DISABLE_POSIX_TIMERS)","int","clockid_t","FAR struct sigevent*","FAR timer_t*" "timer_delete","time.h","!defined(CONFIG_DISABLE_POSIX_TIMERS)","int","timer_t" diff --git a/syscall/syscall_lookup.h b/syscall/syscall_lookup.h index abd056fe37..25807590d8 100644 --- a/syscall/syscall_lookup.h +++ b/syscall/syscall_lookup.h @@ -91,6 +91,7 @@ SYSCALL_LOOKUP(up_assert, 2, STUB_up_assert) # ifdef CONFIG_CANCELLATION_POINTS SYSCALL_LOOKUP(task_setcanceltype, 2, STUB_task_setcanceltype) + SYSCALL_LOOKUP(task_testcancel, 0, STUB_task_testcancel) # endif /* The following can be individually enabled */ @@ -299,9 +300,6 @@ SYSCALL_LOOKUP(up_assert, 2, STUB_up_assert) SYSCALL_LOOKUP(pthread_setschedprio, 2, STUB_pthread_setschedprio) SYSCALL_LOOKUP(pthread_setspecific, 2, STUB_pthread_setspecific) SYSCALL_LOOKUP(pthread_yield, 0, STUB_pthread_yield) -# ifdef CONFIG_CANCELLATION_POINTS - SYSCALL_LOOKUP(pthread_testcancel, 0, STUB_pthread_testcancel) -# endif # ifdef CONFIG_SMP SYSCALL_LOOKUP(pthread_setaffinity, 3, STUB_pthread_setaffinity) SYSCALL_LOOKUP(pthread_getaffinity, 3, STUB_pthread_getaffinity) diff --git a/syscall/syscall_stublookup.c b/syscall/syscall_stublookup.c index 61ccb8ecd6..fda336d5aa 100644 --- a/syscall/syscall_stublookup.c +++ b/syscall/syscall_stublookup.c @@ -102,6 +102,7 @@ uintptr_t STUB_up_assert(int nbr, uintptr_t parm1, uintptr_t parm2); uintptr_t STUB_task_setcanceltype(int nbr, uintptr_t parm1, uintptr_t parm2); +uintptr_t STUB_task_testcancel(int nbr); /* The following can be individually enabled */ @@ -303,8 +304,6 @@ uintptr_t STUB_pthread_setspecific(int nbr, uintptr_t parm1, uintptr_t parm2); uintptr_t STUB_pthread_yield(int nbr); -uintptr_t STUB_pthread_testcancel(int nbr); - uintptr_t STUB_pthread_setaffinity(int nbr, uintptr_t parm1, uintptr_t parm2, uintptr_t parm3); uintptr_t STUB_pthread_getaffinity(int nbr, uintptr_t parm1, -- GitLab From baaa5f7cb8e32d902d95856ad85dfebd578a8729 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 11 Dec 2016 07:50:05 -0600 Subject: [PATCH 674/734] Update TODO list --- TODO | 43 ++----------------------------------------- 1 file changed, 2 insertions(+), 41 deletions(-) diff --git a/TODO b/TODO index c208e56124..752e3b4d54 100644 --- a/TODO +++ b/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated December 8, 2016) +NuttX TODO List (Last updated December 11, 2016) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with @@ -9,7 +9,7 @@ issues related to each board port. nuttx/: - (13) Task/Scheduler (sched/) + (12) Task/Scheduler (sched/) (1) SMP (1) Memory Management (mm/) (1) Power Management (drivers/pm) @@ -165,45 +165,6 @@ o Task/Scheduler (sched/) incompatibilities could show up in porting some code). Priority: Low - Title: REMOVE TASK_DELETE - Description: Need to remove asychronous fix task_delete(). This interface - is non-standard and not safe. Arbitrary deleting tasks can - cause serious problems such as memory leaks and resources like - semaphores left in bad states. - - Task/process exit callbacks registered via atexit() or - on_exit() will not work correctly with task_delete(): In - that case the callback would execute in the context the - caller of task_delete() cancel, not in the context of the - exiting task (or process). - - Better to remove task_delete() than to retain it as a latent - bug. - - Currently used within the OS and also part of the - implementation of pthread_cancel() and task_restart() (which - should also go for the same reasons). It is used in - NxWM::CNxConsole to terminate console tasks and also in - apps/netutils/thttpd to kill CGI tasks that timeout. So not - so simple to remove. - - Option: With CONFIG_CANCELLATION_POINTS=y task_delete() - does not do asynchronous deletion but should rather do the - same kind of synchronization such as the pthread cancellation - points. In this configuration, none of the issues above - apply. It is only the asynchronous task deletion that cannot - be supported. These helper functions are also available to - help manage task deletion: - - int task_setcancelstate(int state, FAR int *oldstate); - int task_setcanceltype(int type, FAR int *oldtype); - void task_testcancel(void); - - Which are analogous to the similarly named pthread_ interfaces. - - Status: Open - Priority: Low and not easily removable. - Title: RELEASE SEMAPHORES HELD BY CANCELED THREADS: Description: Commit: fecb9040d0e54baf14b729e556a832febfe8229e: "In case a thread is doing a blocking operation (e.g. read()) -- GitLab From e3d3fa704e62483dba0959da4f7b6330322a6496 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 11 Dec 2016 10:37:03 -0600 Subject: [PATCH 675/734] Update ChangeLog --- ChangeLog | 226 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 226 insertions(+) diff --git a/ChangeLog b/ChangeLog index b5567cf8f3..4c5c42b134 100755 --- a/ChangeLog +++ b/ChangeLog @@ -13130,5 +13130,231 @@ So this change adds locking (via enter_critical section) to wdog expiration logic for the the case if the SMP configuration (2016-11-18). + * SAM3/4: Add delay between setting and clearing the endpoint RESET bit + in sam_ep_resume(). We need to add a delay between setting and + clearing the endpoint reset bit in SAM_UDP_RSTEP. Without the delay the + USB controller will (may?) not reset the endpoint. If the endpoint is + not being reset, the Data Toggle (DTGLE) bit will not to be cleared + which will cause the next transaction to fail if DTGLE is 1. If that + happens the host will time-out and reset the bus. Adding this delay + may also fix the USBMSC_STALL_RACEWAR in usbmsc_scsi.c, however this + has not been verified yet. From Wolfgang Reißnegger (2016-11-18). + * SAM3/4: Remove unused 'halted' flag in UDP driver. From Wolfgang + Reißnegger (2016-11-18). + * SAM3/4: Remove 'stalled' flag in UDP driver. The flag is not necessary. + The state of the endpoint can be determined using 'epstate' instead. + From Wolfgang Reißnegger (2016-11-18). + * USBMSC: Fix length of mode6 sense reply packet. From Wolfgang + Reißnegger (2016-11-18). + * configs/dk-tm4c129x: Typo fix. From Wolfgang Reißnegger (2016-11-18). + * Typo fix in sam_udp.c. From Wolfgang Reißnegger (2016-11-18). + * STM32: STM32F303xB and STM32F303xC chips have 4 ADCs. From Paul A. + Patience (2016-11-19). + * vfork(): Fix a race condition in the SMP case. Existing logic + depended on the fact that the child would not run until waitpid was + called because the child had the same priority as the parent. BUT + in the SMP case that is not true... the child may run immediately on + a different CPU (2016-11-19). + * arch/: Add option to use low-priority work queue to all Ethernet + drivers in arch that support CONFIG_NET_NOINTS (2016-11-19). + * sched/clock: Correct calculation for the case of Tickless mode with + a 32-bit timer. In that case, the calculation was returning + millisecond accuracy. That is not good when the timer accuracy is < 1 + msec. From Rajan Gill (2016-11-19). + * sched/task: task_restart() test not supported on SMP systems. This is + not fully implemented (2016-11-19). + * This commit adds a new internal interfaces and fixes a problem with + three APIs in the SMP configuration. The new internal interface is + sched_cpu_pause(tcb). This function will pause a CPU if the task + associated with 'tcb' is running on that CPU. This allows a different + CPU to modify that OS data stuctures associated with the CPU. When the + other CPU is resumed, those modifications can safely take place. The + three fixes are to handle cases in the SMP configuration where one CPU + does need to make modifications to TCB and data structures on a task + that could be running running on another CPU. Those three cases are + task_delete(), task_restart(), and execution of signal handles. In + all three cases the solutions is basically the same: (1) Call + sched_cpu_pause(tcb) to pause the CPU on which the task is running, + (2) perform the necessary operations, then (3) call up_cpu_resume() to + restart the paused CPU (2016-11-20). + * task_restart: Make sure new task starts with pre-emption disabled and + not in a critical section (2016-11-21). + * Fix a typo in a spinlock macro (2016-11-21). + * Spinlocks: Added capability to provide architecture-specific memory + barriers. This was for i.MX6 but does not help with the SMP problems. + It is still a good feature (2016-11-21). + * Remove a assertion condition that appears to rarely cause false-alarm + assertions. Teported by Petteri Aimonen (2016-11-21). + * The examples/qencoder app was trying to init the encoder by a direct + call into the board, cheating in a local header to declare the normally + unavailable function prototype. From Sebastien Lorquet (2016-11-22). + * configs: All QE encoder files. Last change made timer hard-coded to 3. + Make configurable (2016-11-22). + * configs: Remove all traces of the no-longer existent ARCHBUTTONS + example. Remove all button configurations that depended on the + obsoleted ARCHBUTTON example (2016-11-22). + * nucleo-l476rg: Add better selection of timer (2016-11-22). + * implementation of dumpgpio for stm32l4, was required for pwm debug. + From Sebastien Lorquet (2016-11-22). + * SMP: Add logic to avoid a deadlock condition when CPU1 is hung waiting + for g_cpu_irqlock and CPU0 is waitin for g_cpu_paused (2016-11-22). + * Misoc: Add timer driver. From Ramtin Amin (2016-11-22). + * Misoc: Add commits and warnings about missing caculation of the timer + reload value (2016-11-22). + * SAM3/4: Name of method is now setcallback, not sethandler (2016-11-22). + * sam4s-xplained-pro/nsh: Configuration uses old, improper timer interface. + CONFIG_TIMER disabled in configuration. (2016-11-22). + * sam4s-xplained-pro: Remove obsolete timer initialization logic + (2016-11-22). + * Misoc LM32: Make system timer configurable via CONFIG_USEC_PER_TICK. + From Ramtin Amin (2016-11-23). + * LPC43xx: Add timer driver; configs/bambino-200e: Add support for timer + driver. From Alan Carvalho de Assis (2016-11-23). + * SMP: Fix backward condition in test (2016-11-23). + * ARMv7-A SMP: Add a little logic to signal handling (2016-11-24). + * Misoc LM32: Add signal handling logic. From Ramtin Amin (2016-11-24). + * SMP: Add spin_trylock(). Use this in conditions where other CPUs need + to stopped but we cannot call enter_critical_section (2016-11-24). + * Fix for F1 RTC Clock, tested on F103. From Maciej Wójcik (2016-11-25). + * SMP: Fix yet another potential deadlock (2016-11-25). + * Enable CONFIG_RTC in the hymini-stm32v/nsh2 (kitchensink) config. + From Maciej Wójcik (2016-11-26). + * This adds support for keeping i.MX6 inter-processor communication data + in a non-cached address region (2016-11-26). + * i.MX6: Disable non-cached region support. Add SCU register definitions + (2016-11-26). + * i.MX6: Add some controls to enable SMP cache coherency in SMP mode + (2016-11-26). + * ARMv7-A: Fix some SCU SMP logic (2016-11-26). + * ARMv7-A/i.MX6: Modify handling of the SMP cache coherency + configuration so that it is identical to the steps from the TRM. + Makes no differenct, however (2016-11-27). + * The Smoothie project needs to compile C++ inside config/boardname/src/ + to use with High Priority Interruption, then I modified the board + configs Makefile to support it. It works fine for the first time + compilation, but if we execute "touch config/boardname/src/Pin.cxx" + and execute "make" it will not detect that Pin.cxx was modified. I + think there is some other place I should modify, but I didn't find + it. From Alan Carvalho de Assis (2016-11-27). + * ARMv7-A/i.MX6 SMP: Move SMP coherernt cache setup to earlier in + initialization of CPUn, n>0 (2016-11-27). + * ARMv7 GIC: SGIs are non-maskable but go through the same path as other, + maskable interrupts. Added logic to serialize SGI processing when + necessary (2016-11-27). + * sched_note: Extend OS instrumentation to include some SMP events + (2016-11-27). + * sched_note: Add spinlock instrumentation; In SMP configurations, + select to log only notes from certain CPUs (2016-11-28). + * Misoc LM3: Add Misoc Ethernet driver. Integrate network support into + configs/misoc/hello. Remove configs/misoc/include/generated directory. + I suppose the the intent now is that this is a symbolic link? DANGER! + This means that you cannot compile this code with first generating + these files a providing a symbolic link to this location! From Ramtin + Amin (2016-11-28). + * Add tools/showsize.sh (2016-11-28). + * configs/misoc: Add a sample directory containing generated sources. + This is really only useful for performing test builds. You really + must generate the Misoc architecture for a real-life build. From + Ramtin Amin (2016-11-28). + * sched_note: Permit spinlock and critical section notes in in-memory + buffer iff sched_not_get() interfaces is disabled (2016-11-28). + * STM32 DAC: Fix shift value whenever there are is a DAC2 and, hence, + up to three interfaces. From Marc Rechté (2016-11-29). + * Back out a debug change that was included in commit (2016-11-29). + * i.MX6: Don't output the alphabet if CONFIG_DEBUG_FEATURES is not set + (2016-11-29). + * Misoc LM32: Add logic to flush/invalidate caches. From Ramtin Amin + (2016-11-29). + * drivers/net/: Adapt all Ethernet drivers to work as though + CONFIG_NET_MULTIBUFFER were set. Remove all references to + CONFIG_NET_MULTIBUFFER (2016-11-29). + * stm32_otghshost: if STM32F446 increase number of channels to 16. From + Janne Rosberg (2016-11-30). + * usbhost_composite: fix end offset in usbhost_copyinterface(). From + Janne Rosberg (2016-11-30). + * usbhost_cdcacm: add CDC_SUBCLASS_ACM and CDC_PROTO_ATM to supported + class and proto. From Janne Rosberg (2016-11-30). + * LPC43 SD/MMC: Correct some git definitions on SMMC control register + in lpc43_sdmmc.h. From Alan Carvalho de Assis (2016-11-30). + * STM32L4: Correct USART1/2 definitions. Use default mbed UART4 + settings. From Sebastien Lorquet (2016-12-01). + * boardctl: Add new boardctl() command ,BOARDIOC_NX_START, to start the + NX server as a kernel thread (2016-12-01). + * GPDMA driver for the LPC43xx. The GPDMA block is basically the same + as the LPC17xx. Only the clock configuration is different and LPC43xx + has four different DMA request sources, where LPC17xx has only two. + From Alan Carvalho de Assis (2016-12-01). + * Remove RGMP and RGMP drivers (2016-12-02). + * i.MX6: Add an untested SPI driver taken directly from the i.MX1 port + (2016-12-02). + * Eliminate CONFIG_NO_NOINTS. There is no longer any support for + interrupt level processing of the network stack. Lots of files changed + -> lots of testing needed (2016-12-03). + * Fix DEBUGASSERT() in group_signal.c. From Masayuki Ishikawa + (2016-12-04). + * Add support for the SAM5CMP-DB board. From Masayuki Ishikawa + (2016-12-04). + * SAM3/4: Add SMP support for the dual-core SAM4CM. From Masayuki + Ishikawa (2016-12-04). + * C Library: Allow option to enable IP address conversions even when the + IP address family is not supported (2016-12-04). + * SSD1306: Fix errors in SPI mode configuration. From Gong Darcy + (2016-12-04). + * SAMA5 does not build when executing from SDRAM before board + frequencies are not constant. Rather, the bootloader configures the + clocking and we must derive the clocking from the MCK left by the + bootloader. This means lots more computations. This is untested on + initial commit because I don't have a good PWM test setup right now + (2016-12-04). + * Olimex-LPC1766-STK: Enable procfs in NSH configuration. Automount + /proc on startup (2016-12-05). + * SAM4CMP-DB: Add hooks to auto-mount the procfs file system on startup + in board bring-up logic (2016-12-05). + * Remove all references to BOARDIOC_PWMSETUP and board_pwm_setup() + (2016-12-05). + * Remove all references to BOARDIOC_ADCSETUP and board_adc_setup() + (2016-12-05). + * Added Timers 2-5 and control of SAI and I2S PLLs. From David Sidrane + (2016-12-05). + * Added support for stmf469 SAI and I2S PLL configuration and STM446 + fixes. From David Sidrane (2016-12-05). + * Expanded otgfs support to stm32F469 and stm32f446. Added missing bits + definitions, Used stm32F469 and stm32f446 bit definitions, Removed + unsed header file. From David Sidrane (2016-12-05). + * Remove BOARDIOC_CAN_INITIALIZE. CAN initialization is now done in the + board initialization logic just like every other device driver + (2016-12-06). + * STM32F7: Allow the config to override the clock edge setting. From + David Sidrane (2016-12-06). + * For Cortex-A9, should also set ACTLR.FW in SMP mode to enble TLB and + cache broadcasts. Does not fix SMP cache problem (2016-12-07). + * sched notes: Add additional note to see if/when CPU is started in SMP + mode (2016-12-07). + * EFM32: Fix a compilation error. From Pierre-noel Bouteville + (2016-12-07). + * pthreads: Add pthread_cleanup_push() and pthread_cleanup_pop() + (2016-12-08). + * BUGFIX:STM32F427 was rebooting. Over reached family. From David + Sidrane (2016-12-08). + * Add pthread_setcanceltype() and pthread_testcancel() (2016-12-09). + * Added STM32F469 RAM size and deliberated STM32F446 size. From David + Sidrane (2016-12-09). + * Typo in stm32f76xx77xx_pinmap.h edited online with Bitbucket. From + David Sidrane (2016-12-09). + * stm32_allocateheap.c edited online with Bitbucket. From David Sidrane + (2016-12-09). + * LPC43xx SD card: Correct pin configuration options needed for SD card + pins. From Alan Carvalho de Assis (2016-12-09). + * pthread_mutex_destroy(): Fix an error in destroying a mutex which can + occur after a pthread has been canceled while holding the mutex + (2016-12-09). + * Add support for cancellation points (2016-12-09). + * Forgot to add some files in the last commit (2016-12-10). + * Correct some default font IDs. From Pierre-Noel Bouteville + (2016-12-10). + * task_delete() now obeys all cancellation point semantics (2016-12-10). + * Add task_setcancelstate(), task_setcanceltype(), and task_testcancel(). + These are non-standard interfaces analogous to the correponding pthread_ + interfaces that provide cancellation controls for tasks (2016-12-10). 7.19 2016-xx-xx Gregory Nutt -- GitLab From 5d99a37ab72040429c1ba5c6bcd759658028775c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 11 Dec 2016 13:40:26 -0600 Subject: [PATCH 676/734] Update user manual --- Documentation/NuttxUserGuide.html | 249 +++++++++++++++---- libc/pthread/pthread_mutexattr_setprotocol.c | 1 - 2 files changed, 197 insertions(+), 53 deletions(-) diff --git a/Documentation/NuttxUserGuide.html b/Documentation/NuttxUserGuide.html index 4a98bf50e4..df71ef5c54 100644 --- a/Documentation/NuttxUserGuide.html +++ b/Documentation/NuttxUserGuide.html @@ -13,7 +13,7 @@

    NuttX Operating System

    User's Manual

    by

    Gregory Nutt

    -

    Last Updated: December 10, 2016

    +

    Last Updated: December 11, 2016

    @@ -3533,6 +3533,8 @@ interface of the same name.
  • 2.5.8 sem_trywait
  • 2.5.9 sem_post
  • 2.5.10 sem_getvalue
    • +
  • 2.5.11 sem_getprotocol
    • +
  • 2.5.12 sem_setprotocol

    • 2.5.1 sem_init

    @@ -4007,6 +4009,74 @@ number of tasks waiting for the semaphore. interface of the same name.

    +

    2.5.11 sem_getprotocol

    +

    +Function Prototype: +

    +

    +    #include <nuttx/semaphore.h>
+    int sem_getprotocol(FAR const pthread_mutexattr_t *attr, FAR int *protocol);
+
    +

    +Description: Return the value of the semaphore protocol attribute. +

    +

    +Input Parameters: +

    +

    +

      +
    • attr. A pointer to the semaphore to be queried
      • +
    • protocol. The user provided location in which to store the protocol value. May be one of SEM_PRIO_NONE, or SEM_PRIO_INHERIT, SEM_PRIO_PROTECT.
      • +
    +

    +

    +Returned Value: +

    +

    +If successful, the sem_getprotocol() function will return zero (OK). +Otherwise, an -1 (ERROR) will be returned and the errno value will be set to indicate the nature of the error. +

    +

    +Assumptions/Limitations: +

    +

    +POSIX Compatibility: Non-standard NuttX interface. Should not be used in portable code. Analogous to pthread_muxtexattr_getprotocol(). +

    + +

    2.5.12 sem_setprotocol

    +

    +Function Prototype: +

    +

    +    #include <nuttx/semaphore.h>
+    int sem_setprotocol(FAR pthread_mutexattr_t *attr, int protocol);
+
    +

    +Description: Set semaphore protocol attribute. +

    +

    +Input Parameters: +

    +

    +

      +
    • attr. A pointer to the semaphore to be modified
      • +
    • protocol. The new protocol to use. One of SEM_PRIO_NONE, or SEM_PRIO_INHERIT, SEM_PRIO_PROTECT. SEM_PRIO_INHERIT is supported only if CONFIG_PRIORITY_INHERITANCE is defined; SEM_PRIO_PROTECT is not currently supported in any configuration.
      • +
    +

    +

    +Returned Value: +

    +

    +If successful, the sem_getprotocol() function will return zero (OK). +Otherwise, an -1 (ERROR) will be returned and the errno value will be set to indicate the nature of the error. +

    +

    +Assumptions/Limitations: +

    +

    +POSIX Compatibility: Non-standard NuttX interface. Should not be used in portable code. Analogous to pthread_muxtexattr_setprotocol(). +

    + - + - - - - - - - -
    @@ -5596,49 +5666,51 @@ be sent.
  • 2.8.32 pthread_mutexattr_setpshared
  • 2.8.33 pthread_mutexattr_gettype
  • 2.8.34 pthread_mutexattr_settype
    • -
  • 2.8.35 pthread_mutex_init
    • -
  • 2.8.36 pthread_mutex_destroy
    • -
  • 2.8.37 pthread_mutex_lock
    • -
  • 2.8.38 pthread_mutex_trylock
    • -
  • 2.8.39 pthread_mutex_unlock
    • +
  • 2.8.35 pthread_mutexattr_getprotocol
    • +
  • 2.8.36 pthread_mutexattr_setprotocol
    • +
  • 2.8.37 pthread_mutex_init
    • +
  • 2.8.38 pthread_mutex_destroy
    • +
  • 2.8.39 pthread_mutex_lock
    • +
  • 2.8.40 pthread_mutex_trylock
    • +
  • 2.8.41 pthread_mutex_unlock

    • Condition Variables.

    Barriers.

    Initialization.

    Signals.

    @@ -7021,7 +7093,77 @@ returned to indicate the error:

    POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.35 pthread_mutex_init

    +

    2.8.35 pthread_mutexattr_getprotocol

    +

    +Function Prototype: +

    +

    +    #include <pthread.h>
+    int pthread_mutexattr_getprotocol(FAR const pthread_mutexattr_t *attr,
+                                      FAR int *protocol);
+
    +

    +Description: Return the value of the mutex protocol attribute.. +

    +

    +Input Parameters: +

    +

    +

      +
    • attr. A pointer to the mutex attributes to be queried
      • +
    • protocol. The user provided location in which to store the protocol value. May be one of PTHREAD_PRIO_NONE, or PTHREAD_PRIO_INHERIT, PTHREAD_PRIO_PROTECT.
      • +
    +

    +

    +Returned Value: +

    +

    +If successful, the pthread_mutexattr_setprotocol() function will return zero (OK). +Otherwise, an error number will be returned to indicate the error. +

    +

    +Assumptions/Limitations: +

    +

    +POSIX Compatibility: Comparable to the POSIX interface of the same name. +

    + +

    2.8.36 pthread_mutexattr_setprotocol

    +

    +Function Prototype: +

    +

    +    #include <pthread.h>
+    int pthread_mutexattr_setprotocol(FAR pthread_mutexattr_t *attr,
+                                      int protocol);
+
    +

    +Description: Set mutex protocol attribute. +

    +

    +Input Parameters: +

    +

    +

      +
    • attr. A pointer to the mutex attributes to be modified
      • +
    • protocol. The new protocol to use. One of PTHREAD_PRIO_NONE, or PTHREAD_PRIO_INHERIT, PTHREAD_PRIO_PROTECT. PTHREAD_PRIO_INHERIT is supported only if CONFIG_PRIORITY_INHERITANCE is defined; PTHREAD_PRIO_PROTECT is not currently supported in any configuration.
      • +
    +

    +

    +Returned Value: +

    +

    +If successful, the pthread_mutexattr_setprotocol() function will return zero (OK). +Otherwise, an error number will be returned to indicate the error. +

    +

    +Assumptions/Limitations: +

    +

    +POSIX Compatibility: Comparable to the POSIX interface of the same name. +

    + +

    2.8.37 pthread_mutex_init

    Function Prototype:

    @@ -7050,10 +7192,9 @@ returned to indicate the error: Assumptions/Limitations:

    -POSIX Compatibility: Comparable to the POSIX -interface of the same name. +POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.36 pthread_mutex_destroy

    +

    2.8.38 pthread_mutex_destroy

    Function Prototype:

    @@ -7084,7 +7225,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.37 pthread_mutex_lock

    +

    2.8.39 pthread_mutex_lock

    Function Prototype:

    @@ -7150,7 +7291,7 @@ Otherwise, an error number will be returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.38 pthread_mutex_trylock

    +

    2.8.40 pthread_mutex_trylock

    Function Prototype:

    @@ -7190,7 +7331,7 @@ Otherwise, an error number will be returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.39 pthread_mutex_unlock

    +

    2.8.41 pthread_mutex_unlock

    Function Prototype:

    @@ -7236,7 +7377,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.40 pthread_condattr_init

    +

    2.8.42 pthread_condattr_init

    Function Prototype:

    @@ -7267,7 +7408,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.41 pthread_condattr_destroy

    +

    2.8.43 pthread_condattr_destroy

    Function Prototype:

    @@ -7298,7 +7439,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.42 pthread_cond_init

    +

    2.8.44 pthread_cond_init

    Function Prototype:

    @@ -7329,7 +7470,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.43 pthread_cond_destroy

    +

    2.8.45 pthread_cond_destroy

    Function Prototype:

    @@ -7360,7 +7501,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.44 pthread_cond_broadcast

    +

    2.8.46 pthread_cond_broadcast

    Function Prototype:

    @@ -7391,7 +7532,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.45 pthread_cond_signal

    +

    2.8.47 pthread_cond_signal

    Function Prototype:

    @@ -7422,7 +7563,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.46 pthread_cond_wait

    +

    2.8.48 pthread_cond_wait

    Function Prototype:

    @@ -7453,7 +7594,7 @@ returned to indicate the error: POSIX Compatibility: Comparable to the POSIX interface of the same name. -

    2.8.47 pthread_cond_timedwait

    +

    2.8.49 pthread_cond_timedwait

    Function Prototype:

    @@ -7490,7 +7631,7 @@ interface of the same name. POSIX Compatibility: Comparable to the POSIX interface of the same name.

    -

    2.8.48 pthread_barrierattr_init

    +

    2.8.50 pthread_barrierattr_init

    Function Prototype:

    @@ -7523,7 +7664,7 @@ interface of the same name. POSIX Compatibility: Comparable to the POSIX interface of the same name.

    -

    2.8.49 pthread_barrierattr_destroy

    +

    2.8.51 pthread_barrierattr_destroy

    Function Prototype:

    @@ -7555,7 +7696,7 @@ interface of the same name. POSIX Compatibility: Comparable to the POSIX interface of the same name.

    -

    2.8.50 pthread_barrierattr_setpshared

    +

    2.8.52 pthread_barrierattr_setpshared

    Function Prototype:

    @@ -7593,7 +7734,7 @@ interface of the same name. POSIX Compatibility: Comparable to the POSIX interface of the same name.

    -

    2.8.51 pthread_barrierattr_getpshared

    +

    2.8.53 pthread_barrierattr_getpshared

    Function Prototype:

    @@ -7625,7 +7766,7 @@ interface of the same name. POSIX Compatibility: Comparable to the POSIX interface of the same name.

    -

    2.8.52 pthread_barrier_init

    +

    2.8.54 pthread_barrier_init

    Function Prototype:

    @@ -7695,7 +7836,7 @@ interface of the same name. POSIX Compatibility: Comparable to the POSIX interface of the same name.

    -

    2.8.53 pthread_barrier_destroy

    +

    2.8.55 pthread_barrier_destroy

    Function Prototype:

    @@ -7739,7 +7880,7 @@ interface of the same name. POSIX Compatibility: Comparable to the POSIX interface of the same name.

    -

    2.8.54 pthread_barrier_wait

    +

    2.8.56 pthread_barrier_wait

    Function Prototype:

    @@ -7799,7 +7940,7 @@ interface of the same name.

    -

    2.8.55 pthread_once

    +

    2.8.57 pthread_once

    Function Prototype:

    @@ -7843,7 +7984,7 @@ interface of the same name. POSIX Compatibility: Comparable to the POSIX interface of the same name.

    -

    2.8.56 pthread_kill

    +

    2.8.58 pthread_kill

    Function Prototype:

    @@ -7905,7 +8046,7 @@ interface of the same name. POSIX Compatibility: Comparable to the POSIX interface of the same name.

    -

    2.8.57 pthread_sigmask

    +

    2.8.59 pthread_sigmask

    Function Prototype:

    @@ -10237,10 +10378,10 @@ notify a task when a message is available on a queue.
  • mq_timedsend
  • mq_unlink
  • mmap
    • -
  • Network Interfaces
  • on_exit +
    		•
  • open
  • opendir
  • OS Interfaces
    • @@ -10305,9 +10446,11 @@ notify a task when a message is available on a queue.
  • pthread_key_delete
  • pthread_kill
  • pthread_mutexattr_destroy
    • +
  • pthread_mutexattr_getprotocol
  • pthread_mutexattr_getpshared
  • pthread_mutexattr_gettype
  • pthread_mutexattr_init
    • +
  • pthread_mutexattr_setprotocol
  • pthread_mutexattr_setpshared
  • pthread_mutexattr_settype
  • pthread_mutex_destroy
    • @@ -10328,9 +10471,9 @@ notify a task when a message is available on a queue.
  • puts
  • RAM disk driver
  • read
    • +
  • readdir
    		•  -
  • readdir
  • readdir_r
  • recv
  • recvfrom
    • @@ -10353,10 +10496,12 @@ notify a task when a message is available on a queue.
  • Counting Semaphore Interfaces
  • sem_close
  • sem_destroy
    • +
  • sem_getprotocol
  • sem_getvalue
  • sem_init
  • sem_open
  • sem_post
    • +
  • sem_setprotocol
  • sem_trywait
  • sem_unlink
  • sem_wait
    • diff --git a/libc/pthread/pthread_mutexattr_setprotocol.c b/libc/pthread/pthread_mutexattr_setprotocol.c index 0d128e0480..44d8be7849 100644 --- a/libc/pthread/pthread_mutexattr_setprotocol.c +++ b/libc/pthread/pthread_mutexattr_setprotocol.c @@ -86,5 +86,4 @@ int pthread_mutexattr_setprotocol(FAR pthread_mutexattr_t *attr, return ENOSYS; #endif - } -- GitLab From e6fac360c6bbb3683719a50376d9d228f99b7c9c Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 11 Dec 2016 14:34:11 -0600 Subject: [PATCH 677/734] Update user manual --- Documentation/NuttxUserGuide.html | 35 ++++++++++++++++++++++++++----- 1 file changed, 30 insertions(+), 5 deletions(-) diff --git a/Documentation/NuttxUserGuide.html b/Documentation/NuttxUserGuide.html index df71ef5c54..cb0cacfc59 100644 --- a/Documentation/NuttxUserGuide.html +++ b/Documentation/NuttxUserGuide.html @@ -3519,6 +3519,29 @@ interface of the same name. inheritance logic. +

    + Locking versus Signaling Semaphores. + Semaphores (and mutexes) may be used for many different purposes. + One typical use of for mutual exclusion and locking of resources: + In this usage, the thread that needs exclusive access to a resources takes the semaphore to get access to the resource. + The same thread subsequently releases the seamphore count when it no longer needs exclusive access. + Priority inheritance is intended just for this usage case. +

    +

    + In a different usage case, a semaphore may to be used to signal an event: + One thread A waits on a semaphore for an event to occur. + When the event occurs, another thread B will post the semaphore waking the waiting thread A. + This is a completely different usage model; notice that in the mutual exclusion case, the same thread takes and posts the semaphore. In the signaling case, one thread takes the seamphore and a different thread posts the samphore. Priority inheritance should never be used in this signaling case. + Subtle, strange behaviors may result. +

    +

    + When priority inheritance is enabled with CONFIG_PRIORITY_INHERITANCE, the default protocol for the semaphore will be to use priority inheritance. + For signaling semaphores, priority inheritance must be explicitly disabled by calling sem_setprotocol with SEM_PRIO_NONE. + For the case of pthread mutexes, pthread_mutexattr_setprotocol with PTHREAD_PRIO_NONE. +

    +

    + This is discussed in much more detail on this Wiki page. +

    POSIX semaphore interfaces:

    @@ -4052,7 +4075,8 @@ Otherwise, an -1 (ERROR) will be returned and the errno

    -Description: Set semaphore protocol attribute. +Description: Set semaphore protocol attribute. See the paragraph Locking versus Signaling Semaphores for some important information about the use of this interface. +

    Input Parameters: @@ -4796,9 +4820,9 @@ interface of the same name. See the NuttX Threading Wiki page and the Tasks vs. Threads FAQ for additional information on tasks and threads in NuttX.

    - Signalling Multi-threaded Task Groups. + Signaling Multi-threaded Task Groups. The behavior of signals in the multi-thread task group is complex. - NuttX emulates a process model with task groups and follows the POSIX rules for signalling behavior. + NuttX emulates a process model with task groups and follows the POSIX rules for signaling behavior. Normally when you signal the task group you would signal using the task ID of the main task that created the group (in practice, a different task should not know the IDs of the internal threads created within the task group); that ID is remembered by the task group (even if the main task thread exits).

    @@ -7118,7 +7142,7 @@ returned to indicate the error: Returned Value:

    -If successful, the pthread_mutexattr_setprotocol() function will return zero (OK). +If successful, the pthread_mutexattr_getprotocol() function will return zero (OK). Otherwise, an error number will be returned to indicate the error.

    @@ -7138,7 +7162,7 @@ Otherwise, an error number will be returned to indicate the error. int protocol);

    -Description: Set mutex protocol attribute. +Description: Set mutex protocol attribute. See the paragraph Locking versus Signaling Semaphores for some important information about the use of this interface.

    Input Parameters: @@ -10361,6 +10385,7 @@ notify a task when a message is available on a queue.

  • lio_listio
  • listen
  • localtime_r
    • +
  • Locking versus Signaling Semaphores
  • lseek
  • Named Message Queue Interfaces
  • mkdir
    • -- GitLab From 9617ac8b507b5264a268bd1d8410b95facbadbb6 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 12 Dec 2016 06:54:38 -0600 Subject: [PATCH 678/734] Trivial fix to document --- Documentation/NuttxUserGuide.html | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/Documentation/NuttxUserGuide.html b/Documentation/NuttxUserGuide.html index cb0cacfc59..3ad289614c 100644 --- a/Documentation/NuttxUserGuide.html +++ b/Documentation/NuttxUserGuide.html @@ -5763,9 +5763,7 @@ be sent.
  • pthread_mutex_setprioceiling. get and set the priority ceiling of a mutex.
  • pthread_mutex_timedlock. lock a mutex.
  • pthread_mutexattr_getprioceiling. get and set the prioceiling attribute of the mutex attributes object.
    • -
  • pthread_mutexattr_getprotocol. get and set the protocol attribute of the mutex attributes object.
  • pthread_mutexattr_setprioceiling. get and set the prioceiling attribute of the mutex attributes object.
    • -
  • pthread_mutexattr_setprotocol. get and set the protocol attribute of the mutex attributes object.
  • pthread_rwlock_destroy. destroy and initialize a read-write lock object.
  • pthread_rwlock_init. destroy and initialize a read-write lock object.
  • pthread_rwlock_rdlock. lock a read-write lock object for reading.
    • @@ -10404,9 +10402,9 @@ notify a task when a message is available on a queue.
  • mq_unlink
  • mmap
  • Network Interfaces
    • -
  • on_exit
    		• +
  • on_exit
  • open
  • opendir
  • OS Interfaces
    • @@ -10496,9 +10494,9 @@ notify a task when a message is available on a queue.
  • puts
  • RAM disk driver
  • read
    • -
  • readdir
    		•  +
  • readdir
  • readdir_r
  • recv
  • recvfrom
    • -- GitLab From 8f76bacc552f73ec5404d93aa9f9364ccec0583f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 12 Dec 2016 08:18:38 -0600 Subject: [PATCH 679/734] Add hyprlinks to a document --- Documentation/NuttxUserGuide.html | 13 +++++++++---- TODO | 2 +- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/Documentation/NuttxUserGuide.html b/Documentation/NuttxUserGuide.html index 3ad289614c..fa78eac460 100644 --- a/Documentation/NuttxUserGuide.html +++ b/Documentation/NuttxUserGuide.html @@ -203,6 +203,11 @@ paragraphs.
  • 2.1.3 task_activate
  • 2.1.4 task_delete
  • 2.1.5 task_restart
    • + +

    + Non-standard extensions to VxWorks-like interfaces to support POSIX Cancellation Points. +

    +
    • 2.1.6 task_setcancelstate
    • 2.1.7 task_setcanceltype
    • 2.1.8 task_testcancel
      • @@ -486,7 +491,7 @@ int task_delete(pid_t pid);

      This function obeys the semantics of pthread cancellation: - task deletion is deferred if cancellation is disabled or if deferred cancellation is supported (with cancellation points enabled). + task deletion is deferred if cancellation is disabled or if deferred cancellation is supported (with Cancellation Points enabled).

      Input Parameters: @@ -708,7 +713,7 @@ No thread could be found corresponding to that specified by the given thread ID. Description:

      -The task_testcancel() function creates a cancellation point in the calling task. +The task_testcancel() function creates a Cancellation Point in the calling task. The task_testcancel() function has no effect if cancelability is disabled.

      @@ -6225,7 +6230,7 @@ When cancelability is disabled, all cancellations are held pending in the target Either asychronrously or deferred. Asynchronous cancellations we be acted upon immediately (when enabled), interrupting the thread with its processing in an abritray state.

      -

      When cancelability is deferred, all cancels are held pending in the target thread until the thread changes the cancelability type or a cancellation point function such as pthread_cancel().

      +

      When cancelability is deferred, all cancels are held pending in the target thread until the thread changes the cancelability type or a Cancellation Point function such as pthread_cancel().

      Input Parameters: @@ -6352,7 +6357,7 @@ returned to indicate the error. Description:

      -The pthread_testcancel() function creates a cancellation point in the calling thread. +The pthread_testcancel() function creates a Cancellation Point in the calling thread. The pthread_testcancel() function has no effect if cancelability is disabled.

      diff --git a/TODO b/TODO index 752e3b4d54..38557d8124 100644 --- a/TODO +++ b/TODO @@ -108,7 +108,7 @@ o Task/Scheduler (sched/) 2. They run in supervisor mode (if applicable), and 3. They do not obey any setup of PIC or address environments. Do they need to? - 4. In the case of task_delete() and pthread_cancel, these + 4. In the case of task_delete() and pthread_cancel(), these callbacks will run on the thread of execution and address context of the caller of task. That is very bad! -- GitLab From dcb15e6ae420f96bf207780bfa48d6528910b746 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 12 Dec 2016 08:23:35 -0600 Subject: [PATCH 680/734] More trivial documentation updates. --- Documentation/NuttxUserGuide.html | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/NuttxUserGuide.html b/Documentation/NuttxUserGuide.html index fa78eac460..5f1b35ca94 100644 --- a/Documentation/NuttxUserGuide.html +++ b/Documentation/NuttxUserGuide.html @@ -6230,7 +6230,7 @@ When cancelability is disabled, all cancellations are held pending in the target Either asychronrously or deferred. Asynchronous cancellations we be acted upon immediately (when enabled), interrupting the thread with its processing in an abritray state.

      -

      When cancelability is deferred, all cancels are held pending in the target thread until the thread changes the cancelability type or a Cancellation Point function such as pthread_cancel().

      +

      When cancelability is deferred, all cancellations are held pending in the target thread until the thread changes the cancelability type or a Cancellation Point function such as pthread_testcancel() is entered.

      Input Parameters: -- GitLab From edeee90c667a6f1c273082c2a73f764c92e85552 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 13 Dec 2016 10:04:38 -0600 Subject: [PATCH 681/734] i.MX6 interrupt handling: Additional logic needed to handle nested interrupts when an interrupt stack is used --- arch/arm/src/armv7-a/arm_vectors.S | 66 +++++++++++++++++++++++++++++- 1 file changed, 65 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/armv7-a/arm_vectors.S b/arch/arm/src/armv7-a/arm_vectors.S index 33d1f8fc55..8a76e000b5 100644 --- a/arch/arm/src/armv7-a/arm_vectors.S +++ b/arch/arm/src/armv7-a/arm_vectors.S @@ -64,6 +64,10 @@ g_fiqtmp: .word 0 /* Saved lr */ .word 0 /* Saved spsr */ #endif +#if CONFIG_ARCH_INTERRUPTSTACK > 3 && defined(CONFIG_ARMV7A_HAVE_GICv2) +g_nestlevel: + .word 0 /* Interrupt nesting level */ +#endif /************************************************************************************ * Private Functions @@ -172,13 +176,53 @@ arm_vectorirq: mov r0, sp /* Get r0=xcp */ #if CONFIG_ARCH_INTERRUPTSTACK > 3 +#ifdef CONFIG_ARMV7A_HAVE_GICv2 + /* We will switch to the interrupt stack, UNLESS we are processing a + * nested interrupt in which case we are already using the interrupt + * stack. SGI interrupts may be nested because they are non-maskable. + */ + + ldr r5, .Lirqnestlevel /* r1=Points to interrupt nesting level */ + ldr r1, [r5] /* Get r1= nesting level */ + add r1, r1, #1 /* Increment nesting level */ + str r1, [r5] /* Save r1= nesting level */ + + cmp r1, #1 /* r1>1 if nested */ + bgt .Lintnested /* Use current SP if nested */ +#endif + + /* Call arm_decodeirq() on the interrupt stack */ + ldr sp, .Lirqstackbase /* SP = interrupt stack base */ str r0, [sp] /* Save the user stack pointer */ mov r4, sp /* Save the SP in a preserved register */ bic sp, sp, #7 /* Force 8-byte alignment */ bl arm_decodeirq /* Call the handler */ ldr sp, [r4] /* Restore the user stack pointer */ + +#ifdef CONFIG_ARMV7A_HAVE_GICv2 + b .Lintreturn + + /* Call arm_decodeirq() on whatever stack is in place */ + +.Lintnested: + mov r4, sp /* Save the SP in a preserved register */ + bic sp, sp, #7 /* Force 8-byte alignment */ + bl arm_decodeirq /* Call the handler */ + mov sp, r4 /* Restore the possibly unaligned stack pointer */ + + /* Decrement the nesting level (r5 should be preserved) */ + +.Lintreturn: + ldr r1, [r5] /* Get r1= nesting level */ + cmp r1, #0 /* A sanity check*/ + subgt r1, r1, #1 /* Decrement nesting level */ + strgt r1, [r5] /* Save r1= nesting level */ +#endif + #else + /* Call arm_decodeirq() on the user stack */ + mov r4, sp /* Save the SP in a preserved register */ bic sp, sp, #7 /* Force 8-byte alignment */ bl arm_decodeirq /* Call the handler */ @@ -227,6 +271,10 @@ arm_vectorirq: #if CONFIG_ARCH_INTERRUPTSTACK > 3 .Lirqstackbase: .word g_intstackbase +#ifdef CONFIG_ARMV7A_HAVE_GICv2 +.Lirqnestlevel: + .word g_nestlevel +#endif #endif .size arm_vectorirq, . - arm_vectorirq .align 5 @@ -937,7 +985,7 @@ arm_vectorfiq: .word g_fiqtmp #if CONFIG_ARCH_INTERRUPTSTACK > 3 .Lfiqstackbase: - .word g_intstackbase + .word g_fiqstackbase #endif #else @@ -965,5 +1013,21 @@ g_intstackbase: .size g_intstackbase, 4 .size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~3) + .globl g_fiqstackalloc + .type g_fiqstackalloc, object + .globl g_fiqstackbase + .type g_fiqstackbase, object + +/************************************************************************************ + * Name: g_fiqstackalloc/g_fiqstackbase + ************************************************************************************/ + +g_fiqstackalloc: + .skip ((CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4) +g_fiqstackbase: + .skip 4 + .size g_fiqstackbase, 4 + .size g_fiqstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~3) + #endif /* CONFIG_ARCH_INTERRUPTSTACK > 3 */ .end -- GitLab From dae7e77d9173a7879b767f0562b63e301ade6ec8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 13 Dec 2016 11:20:14 -0600 Subject: [PATCH 682/734] Update README.txt --- configs/sabre-6quad/README.txt | 46 +++++++++++++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/configs/sabre-6quad/README.txt b/configs/sabre-6quad/README.txt index dda5ef7620..a9703e5a28 100644 --- a/configs/sabre-6quad/README.txt +++ b/configs/sabre-6quad/README.txt @@ -525,7 +525,51 @@ Open Issues: correctly yet. Currently cache inconsistencies appear to be the root cause of all current SMP - issues. + issues. SMP works as expected if the caches are disabled, but otherwise there + are problems (usually hangs): + + This will disable the caches: + +diff --git a/arch/arm/src/armv7-a/arm_head.S b/arch/arm/src/armv7-a/arm_head.S +index 27c2a5b..2a6274c 100644 +--- a/arch/arm/src/armv7-a/arm_head.S ++++ b/arch/arm/src/armv7-a/arm_head.S +@@ -454,6 +454,7 @@ __start: + * after SMP cache coherency has been setup. + */ + ++#if 0 // REMOVE ME + #if !defined(CPU_DCACHE_DISABLE) && !defined(CONFIG_SMP) + /* Dcache enable + * +@@ -471,6 +472,7 @@ __start: + + orr r0, r0, #(SCTLR_I) + #endif ++#endif // REMOVE ME + + #ifdef CPU_ALIGNMENT_TRAP + /* Alignment abort enable +diff --git a/arch/arm/src/armv7-a/arm_scu.c b/arch/arm/src/armv7-a/arm_scu.c +index eedf179..1db2092 100644 +--- a/arch/arm/src/armv7-a/arm_scu.c ++++ b/arch/arm/src/armv7-a/arm_scu.c +@@ -156,6 +156,7 @@ static inline void arm_set_actlr(uint32_t actlr) + + void arm_enable_smp(int cpu) + { ++#if 0 // REMOVE ME + uint32_t regval; + + /* Handle actions unique to CPU0 which comes up first */ +@@ -222,6 +223,7 @@ void arm_enable_smp(int cpu) + regval = arm_get_sctlr(); + regval |= SCTLR_C; + arm_set_sctlr(regval); ++#endif // REMOVE ME + } + + #endif Configurations ============== -- GitLab From a36ed28790aef1ee46248e1b51a987e139e42dbb Mon Sep 17 00:00:00 2001 From: Frank Benkert Date: Tue, 13 Dec 2016 11:22:54 -0600 Subject: [PATCH 683/734] SAMV7: MCAN: Prevent Interrupt-Flooding of ACKE when not connected to CAN-BUS. An Acknowledge-Error will occur every time no other CAN Node acknowledges the message sent. This will also occur if the device is not connected to the can-bus. The CAN-Standard declares, that the Chip has to retry a given message as long as it is not sent successfully (or it is not cancelled by the application). Every time the chip tries to resend the message an Acknowledge-Error-Interrupt is generated. At high baud rates this can lead in extremely high CPU load just for handling the interrupts (and possibly the error handling in the application). To prevent this Interrupt-Flooding we disable the ACKE once it is seen as long we didn't transfer at least one message successfully. --- arch/arm/src/samv7/sam_mcan.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c index 49e05f306b..f6c53306bb 100644 --- a/arch/arm/src/samv7/sam_mcan.c +++ b/arch/arm/src/samv7/sam_mcan.c @@ -3388,6 +3388,19 @@ static void mcan_interrupt(FAR struct can_dev_s *dev) { canerr("ERROR: TX %08x\n", pending & MCAN_TXERR_INTS); + /* An Acknowledge-Error will occur if for example the device + * is not connected to the bus. + * + * The CAN-Standard states that the Chip has to retry the + * message forever, which will produce an ACKE every time. + * To prevent this Interrupt-Flooding and the high CPU-Load + * we disable the ACKE here as long we didn't transfer at + * least one message successfully (see MCAN_INT_TC below). + */ + + ie &= ~MCAN_INT_ACKE; + mcan_putreg(priv, SAM_MCAN_IE_OFFSET, ie); + /* Clear the error indications */ mcan_putreg(priv, SAM_MCAN_IR_OFFSET, MCAN_TXERR_INTS); @@ -3441,6 +3454,17 @@ static void mcan_interrupt(FAR struct can_dev_s *dev) if ((pending & MCAN_INT_TC) != 0) { + /* Check if we have disabled the ACKE in the error-handling above + * (see MCAN_TXERR_INTS) to prevent Interrupt-Flooding and + * re-enable the error interrupt here again. + */ + + if ((ie & MCAN_INT_ACKE) == 0) + { + ie |= MCAN_INT_ACKE; + mcan_putreg(priv, SAM_MCAN_IE_OFFSET, ie); + } + /* Clear the pending TX completion interrupt (and all * other TX-related interrupts) */ -- GitLab From 26560cb9e1916252b3d35aad6f9aa4e02ba670ae Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 13 Dec 2016 16:59:50 -0600 Subject: [PATCH 684/734] i.MX6: Remove non-cached, inter-cpu memory region. Not a useful concept. --- arch/arm/include/armv7-a/spinlock.h | 21 ------ arch/arm/src/armv7-a/mmu.h | 3 - arch/arm/src/common/up_internal.h | 10 --- arch/arm/src/imx6/chip/imx_memorymap.h | 88 +++---------------------- arch/arm/src/imx6/imx_boot.c | 88 ++++--------------------- configs/sabre-6quad/scripts/dramboot.ld | 9 +-- 6 files changed, 22 insertions(+), 197 deletions(-) diff --git a/arch/arm/include/armv7-a/spinlock.h b/arch/arm/include/armv7-a/spinlock.h index f43df337b8..764a96ecef 100644 --- a/arch/arm/include/armv7-a/spinlock.h +++ b/arch/arm/include/armv7-a/spinlock.h @@ -36,25 +36,4 @@ #ifndef __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H #define __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ -/* Not a useful feature */ - -#undef SMP_INTERCPU_NONCACHED - -#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) - /* In SMP configurations, save spinlocks and other inter-CPU communications - * data in a non-cached memory region. - */ - -# define SP_SECTION __attribute__((section(".nocache"))) -#endif - #endif /* __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H */ diff --git a/arch/arm/src/armv7-a/mmu.h b/arch/arm/src/armv7-a/mmu.h index 6440657242..c6338d3337 100644 --- a/arch/arm/src/armv7-a/mmu.h +++ b/arch/arm/src/armv7-a/mmu.h @@ -605,9 +605,6 @@ #define MMU_L2_VECTROFLAGS (PTE_TYPE_SMALL | PTE_WRITE_THROUGH | PTE_AP_R1) #define MMU_L2_VECTORFLAGS MMU_L2_VECTRWFLAGS -#define MMU_L1_INTERCPUFLAGS (PMD_TYPE_PTE | PMD_PTE_PXN | PMD_PTE_DOM(0)) -#define MMU_L2_INTERCPUFLAGS (PTE_TYPE_SMALL | PTE_DEVICE | PTE_AP_RW1) - /* Mapped section size */ #define SECTION_SHIFT (20) diff --git a/arch/arm/src/common/up_internal.h b/arch/arm/src/common/up_internal.h index 7318a70caa..36095a87a4 100644 --- a/arch/arm/src/common/up_internal.h +++ b/arch/arm/src/common/up_internal.h @@ -191,11 +191,6 @@ # define _DATA_INIT &_eronly # define _START_DATA &_sdata # define _END_DATA &_edata - -#ifdef CONFIG_SMP -# define _START_NOCACHE &_snocache -# define _END_NOCACHE &_enocache -#endif #endif /* This is the value used to mark the stack for subsequent stack monitoring @@ -284,11 +279,6 @@ EXTERN uint32_t _edata; /* End+1 of .data */ EXTERN uint32_t _sbss; /* Start of .bss */ EXTERN uint32_t _ebss; /* End+1 of .bss */ -#ifdef CONFIG_SMP -EXTERN uint32_t _snocache; /* Start of .nocache */ -EXTERN uint32_t _enocache; /* End+1 of .nocache */ -#endif - /* Sometimes, functions must be executed from RAM. In this case, the following * macro may be used (with GCC!) to specify a function that will execute from * RAM. For example, diff --git a/arch/arm/src/imx6/chip/imx_memorymap.h b/arch/arm/src/imx6/chip/imx_memorymap.h index 17304c2474..c9ad19dfdf 100644 --- a/arch/arm/src/imx6/chip/imx_memorymap.h +++ b/arch/arm/src/imx6/chip/imx_memorymap.h @@ -126,9 +126,7 @@ * address in the top-level memory map are candidates for other mapping uses: * * 00018000-000fffff Reserved -- Not used - * 00400000-007fffff Reserved -- Used as the virtual address an inter-CPU, - * un-cached memory region in SMP - * configurations + * 00400000-007fffff Reserved -- Not used * 00d00000-00ffffff Reserved -- Not used * 0220c000-023fffff Reserved -- Not used * 80000000-efffffff Reserved -- Level 2 page table (See below) @@ -929,8 +927,6 @@ * the address space. */ -#define INTERCPU_L2_PAGES 1 /* Pages allowed for inter-processor communications */ - #ifndef CONFIG_ARCH_LOWVECTORS /* Memory map * VIRTUAL ADDRESS RANGE L1 PG TABLE L2 PG TABLE DESCRIPTION @@ -938,10 +934,6 @@ * ---------- ---------- ------------ ---------------------------- * 0x80000000 0x803fffff 0x000002000 0x000000400 Vectors (1MiB) * 0x80100000 0x806fffff 0x000002400 0x000001800 Paging (6MiB) - * - * If SMP is enabled, then 1MiB of address spaces for the INTERCPU_L2_PAGES - * pages are taken from the end of the Paging L2 page table to hold non- - * cacheable, inter-processor communication data. */ /* Vector L2 page table offset/size */ @@ -959,18 +951,10 @@ # define VECTOR_L2_END_PADDR (VECTOR_L2_PBASE + VECTOR_L2_SIZE) # define VECTOR_L2_END_VADDR (VECTOR_L2_VBASE + VECTOR_L2_SIZE) -# if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) - /* Paging L2 page table offset/size */ - -# define PGTABLE_L2_OFFSET 0x000002400 -# define PGTABLE_L2_SIZE 0x000001400 - -# else - /* Paging L2 page table offset/size */ + /* Paging L2 page table offset/size */ -# define PGTABLE_L2_OFFSET 0x000002400 -# define PGTABLE_L2_SIZE 0x000001800 -# endif +# define PGTABLE_L2_OFFSET 0x000002400 +# define PGTABLE_L2_SIZE 0x000001800 #else /* Memory map @@ -978,24 +962,12 @@ * START END OFFSET SIZE * ---------- ---------- ------------ ---------------------------- * 0x80000000 0x806fffff 0x000002000 0x000001c00 Paging (7MiB) - * - * If SMP is enabled, then 1MiB of address spaces for the INTERCPU_L2_PAGES - * pages are taken from the end of the Paging L2 page table to hold non- - * cacheable, inter-processor communication data. */ -# if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) - /* Paging L2 page table offset/size */ - -# define PGTABLE_L2_OFFSET 0x000002000 -# define PGTABLE_L2_SIZE 0x000001800 - -# else /* Paging L2 page table offset/size */ -# define PGTABLE_L2_OFFSET 0x000002000 -# define PGTABLE_L2_SIZE 0x000001c00 -# endif +# define PGTABLE_L2_OFFSET 0x000002000 +# define PGTABLE_L2_SIZE 0x000001c00 #endif @@ -1013,23 +985,6 @@ #define PGTABLE_L2_END_PADDR (PGTABLE_L2_PBASE + PGTABLE_L2_SIZE) #define PGTABLE_L2_END_VADDR (PGTABLE_L2_VBASE + PGTABLE_L2_SIZE) -#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) -/* Non-cached inter-processor communication data */ - -# define INTERCPU_L2_OFFSET (PGTABLE_L2_OFFSET + PGTABLE_L2_SIZE) -# define INTERCPU_L2_SIZE (0x00000400) - -/* Non-cached inter-processor communication page table base addresses */ - -# define INTERCPU_L2_PBASE (PGTABLE_BASE_PADDR + INTERCPU_L2_OFFSET) -# define INTERCPU_L2_VBASE (PGTABLE_BASE_VADDR + INTERCPU_L2_OFFSET) - -/* Non-cached inter-processor communication end addresses */ - -# define INTERCPU_L2_END_PADDR (INTERCPU_L2_PBASE + INTERCPU_L2_SIZE) -# define INTERCPU_L2_END_VADDR (INTERCPU_L2_VBASE + INTERCPU_L2_SIZE) -#endif - /* Base address of the interrupt vector table. * * IMX_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM @@ -1052,8 +1007,7 @@ * START END CONTENT * ---------- ---------- --------------------------- * 0x00000000 0x00010000 Vectors (VECTOR_TABLE_SIZE) - * 0x00010000 0x00011000 Inter-CPU communications - * 0x00011000 0x0003c000 Unused + * 0x00010000 0x0003c000 Unused * 0x0003c000 0x00004000 Page table (PGTABLE_SIZE) */ @@ -1061,27 +1015,13 @@ # define IMX_VECTOR_VSRAM IMX_OCRAM_VBASE # define IMX_VECTOR_VADDR 0x00000000 -#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) -/* Inter-processor communications. - * - * NOTICE that we use the unused virtual address space at 0x00400000 for - * the inter-CPU virtual communication area. - */ - -# define INTERCPU_PADDR (IMX_VECTOR_PADDR + VECTOR_TABLE_SIZE) -# define INTERCPU_VADDR (0x00400000) -# define INTERCPU_SIZE (INTERCPU_L2_PAGES << 12) -# define INTERCPU_VSRAM (IMX_VECTOR_VSRAM + VECTOR_TABLE_SIZE) -#endif - #else /* Vectors located at 0xffff:0000 -- this probably does not work */ /* OCRAM Memory Map: * ---------- ---------- --------------------------- * START END CONTENT * ---------- ---------- --------------------------- * 0x00000000 0x00004000 Page table (PGTABLE_SIZE) - * 0x00004000 0x0002f000 Unused - * 0x0002f000 0x00030000 Inter-CPU communications + * 0x00004000 0x00030000 Unused * 0x00030000 0x00010000 Vectors (VECTOR_TABLE_SIZE) */ @@ -1089,18 +1029,6 @@ # define IMX_VECTOR_VSRAM (IMX_OCRAM_VBASE + IMX_OCRAM_SIZE - VECTOR_TABLE_SIZE) # define IMX_VECTOR_VADDR 0xffff0000 -#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) -/* Inter-processor communications - * - * NOTICE that we use the unused virtual address space at 0x00400000 for - * the inter-CPU virtual communication area. - */ - -# define INTERCPU_PADDR (IMX_VECTOR_PADDR - INTERCPU_L2_SIZE) -# define INTERCPU_VADDR (0x00400000) -# define INTERCPU_SIZE (INTERCPU_L2_PAGES << 12) -# define INTERCPU_VSRAM (IMX_VECTOR_VSRAM - INTERCPU_L2_SIZE) -#endif #endif /************************************************************************************ diff --git a/arch/arm/src/imx6/imx_boot.c b/arch/arm/src/imx6/imx_boot.c index 888baf53ae..6abc6f8b15 100644 --- a/arch/arm/src/imx6/imx_boot.c +++ b/arch/arm/src/imx6/imx_boot.c @@ -235,48 +235,6 @@ static void imx_vectormapping(void) # define imx_vectormapping() #endif -/**************************************************************************** - * Name: imx_intercpu_mapping - * - * Description: - * Setup a special mapping for the non-cached, inter-cpu communications - * area. - * - ****************************************************************************/ - -#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) -static void imx_intercpu_mapping(void) -{ - uint32_t intercpu_paddr = INTERCPU_PADDR & PTE_SMALL_PADDR_MASK; - uint32_t intercpu_vaddr = INTERCPU_VADDR & PTE_SMALL_PADDR_MASK; - uint32_t end_paddr = INTERCPU_PADDR + INTERCPU_SIZE; - - DEBUGASSERT(intercpu_vaddr == (uint32_t)&_snocache); - - /* We want to keep the inter-cpu region in on-chip RAM (OCRAM). The - * i.MX6 has 256Kb of OCRAM positioned at physical address 0x0090:0000. - */ - - while (intercpu_paddr < end_paddr) - { - mmu_l2_setentry(INTERCPU_L2_VBASE, intercpu_paddr, intercpu_vaddr, - MMU_L2_INTERCPUFLAGS); - intercpu_paddr += 4096; - intercpu_vaddr += 4096; - } - - /* Now set the level 1 descriptor to refer to the level 2 page table. */ - - mmu_l1_setentry(INTERCPU_L2_PBASE & PMD_PTE_PADDR_MASK, - INTERCPU_VADDR & PMD_PTE_PADDR_MASK, - MMU_L1_INTERCPUFLAGS); -} -#else - /* No inter-cpu communications area */ - -# define imx_intercpu_mapping() -#endif - /**************************************************************************** * Name: imx_copyvectorblock * @@ -477,15 +435,6 @@ void arm_boot(void) imx_vectormapping(); PROGRESS('D'); -#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) - /* Provide a special mapping for the OCRAM interrupt vector positioned in - * high memory. - */ - - imx_intercpu_mapping(); - PROGRESS('E'); -#endif - #ifdef CONFIG_ARCH_RAMFUNCS /* Copy any necessary code sections from FLASH to RAM. The correct * destination in OCRAM is given by _sramfuncs and _eramfuncs. The @@ -498,14 +447,14 @@ void arm_boot(void) *dest++ = *src++; } - PROGRESS('F'); + PROGRESS('E'); /* Flush the copied RAM functions into physical RAM so that will * be available when fetched into the I-Cache. */ arch_clean_dcache((uintptr_t)&_sramfuncs, (uintptr_t)&_eramfuncs) - PROGRESS('G'); + PROGRESS('F'); #endif /* Setup up vector block. _vector_start and _vector_end are exported from @@ -513,23 +462,23 @@ void arm_boot(void) */ imx_copyvectorblock(); - PROGRESS('H'); + PROGRESS('G'); /* Disable the watchdog timer */ imx_wdtdisable(); - PROGRESS('I'); + PROGRESS('H'); /* Initialize clocking to settings provided by board-specific logic */ imx_clockconfig(); - PROGRESS('J'); + PROGRESS('I'); #ifdef CONFIG_ARCH_FPU /* Initialize the FPU */ arm_fpuconfig(); - PROGRESS('K'); + PROGRESS('J'); #endif /* Perform board-specific memroy initialization, This must include @@ -541,7 +490,7 @@ void arm_boot(void) */ imx_memory_initialize(); - PROGRESS('L'); + PROGRESS('K'); #ifdef NEED_SDRAM_REMAPPING /* SDRAM was configured in a temporary state to support low-level @@ -550,7 +499,7 @@ void arm_boot(void) */ imx_remap(); - PROGRESS('M'); + PROGRESS('L'); #endif #ifdef CONFIG_BOOT_SDRAM_DATA @@ -559,7 +508,7 @@ void arm_boot(void) */ arm_data_initialize(); - PROGRESS('N'); + PROGRESS('M'); #endif /* Perform board-specific device initialization. This would include @@ -567,23 +516,12 @@ void arm_boot(void) */ imx_board_initialize(); - PROGRESS('O'); - -#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) - /* Initialize the uncached, inter-CPU communications area */ - - for (dest = &_snocache; dest < &_enocache; ) - { - *dest++ = 0; - } - - PROGRESS('P'); -#endif + PROGRESS('N'); /* Perform common, low-level chip initialization (might do nothing) */ imx_lowsetup(); - PROGRESS('Q'); + PROGRESS('O'); #ifdef USE_EARLYSERIALINIT /* Perform early serial initialization if we are going to use the serial @@ -591,7 +529,7 @@ void arm_boot(void) */ imx_earlyserialinit(); - PROGRESS('R'); + PROGRESS('P'); #endif /* Now we can enable all other CPUs. The enabled CPUs will start execution @@ -600,6 +538,6 @@ void arm_boot(void) */ imx_cpu_enable(); - PROGRESS('S'); + PROGRESS('Q'); PROGRESS('\n'); } diff --git a/configs/sabre-6quad/scripts/dramboot.ld b/configs/sabre-6quad/scripts/dramboot.ld index da35b396aa..a5d696c5ce 100644 --- a/configs/sabre-6quad/scripts/dramboot.ld +++ b/configs/sabre-6quad/scripts/dramboot.ld @@ -44,7 +44,6 @@ MEMORY { - nocache (WR) : ORIGIN = 0x00400000, LENGTH = 4K oscram (W!RX) : ORIGIN = 0x00900000, LENGTH = 256K - 16K ddr3 (W!RX) : ORIGIN = 0x10800000, LENGTH = 1024M - 8M } @@ -123,14 +122,8 @@ SECTIONS _enoinit = ABSOLUTE(.); } > ddr3 - .nocache : - { - _snocache = ABSOLUTE(.); - *(.nocache) - _enocache = ABSOLUTE(.); - } > nocache - /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } .stab.excl 0 : { *(.stab.excl) } -- GitLab From c83da3c48fab8c4892c2d314b7ad07b8304fe574 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 13 Dec 2016 18:01:23 -0600 Subject: [PATCH 685/734] Remove minnsh configurations and support logic: up_getc() and lowinstream. This was an interesting exercise to see just how small you could get NuttX, but otherwise it was not useful: (1) the NSH code violated the OS interface layer by callup up_getc and up_putc directly, and (2) while waiting for character input, NSH would call up_getc() which would hog all of the CPU. NOt a reasonably solution other than as a proof of concept. --- arch/arm/src/kl/Make.defs | 2 +- arch/arm/src/kl/kl_getc.c | 96 -- arch/arm/src/kl/kl_getc.h | 48 - arch/arm/src/lpc11xx/Make.defs | 2 +- arch/arm/src/lpc11xx/lpc11_getc.c | 95 -- arch/arm/src/lpc11xx/lpc11_getc.h | 47 - arch/arm/src/stm32/Make.defs | 2 +- arch/arm/src/stm32/stm32.h | 1 - arch/arm/src/stm32/stm32_getc.c | 121 -- arch/arm/src/stm32/stm32_getc.h | 47 - configs/freedom-kl25z/README.txt | 92 -- configs/freedom-kl25z/minnsh/Make.defs | 124 -- configs/freedom-kl25z/minnsh/defconfig | 799 ------------ configs/freedom-kl25z/minnsh/setenv.sh | 75 -- configs/freedom-kl26z/README.txt | 87 -- configs/freedom-kl26z/minnsh/Make.defs | 124 -- configs/freedom-kl26z/minnsh/defconfig | 799 ------------ configs/freedom-kl26z/minnsh/setenv.sh | 71 -- configs/lpcxpresso-lpc1115/README.txt | 138 --- configs/lpcxpresso-lpc1115/minnsh/Make.defs | 123 -- configs/lpcxpresso-lpc1115/minnsh/defconfig | 767 ------------ configs/lpcxpresso-lpc1115/minnsh/setenv.sh | 72 -- configs/stm3220g-eval/ide/nsh/iar/libc.ewp | 3 - .../stm3220g-eval/ide/nsh/uvision/libc.uvproj | 5 - configs/stm32f103-minimum/README.txt | 134 -- configs/stm32f103-minimum/minnsh/Make.defs | 113 -- configs/stm32f103-minimum/minnsh/defconfig | 1073 ----------------- configs/stm32f103-minimum/minnsh/setenv.sh | 100 -- .../ide/ltcd/uvision/libc.uvproj | 5 - include/nuttx/arch.h | 10 - include/nuttx/streams.h | 11 +- libc/stdio/Make.defs | 2 +- libc/stdio/lib_lowinstream.c | 102 -- 33 files changed, 7 insertions(+), 5283 deletions(-) delete mode 100644 arch/arm/src/kl/kl_getc.c delete mode 100644 arch/arm/src/kl/kl_getc.h delete mode 100644 arch/arm/src/lpc11xx/lpc11_getc.c delete mode 100644 arch/arm/src/lpc11xx/lpc11_getc.h delete mode 100644 arch/arm/src/stm32/stm32_getc.c delete mode 100644 arch/arm/src/stm32/stm32_getc.h delete mode 100644 configs/freedom-kl25z/minnsh/Make.defs delete mode 100644 configs/freedom-kl25z/minnsh/defconfig delete mode 100755 configs/freedom-kl25z/minnsh/setenv.sh delete mode 100644 configs/freedom-kl26z/minnsh/Make.defs delete mode 100644 configs/freedom-kl26z/minnsh/defconfig delete mode 100755 configs/freedom-kl26z/minnsh/setenv.sh delete mode 100644 configs/lpcxpresso-lpc1115/minnsh/Make.defs delete mode 100644 configs/lpcxpresso-lpc1115/minnsh/defconfig delete mode 100755 configs/lpcxpresso-lpc1115/minnsh/setenv.sh delete mode 100644 configs/stm32f103-minimum/minnsh/Make.defs delete mode 100644 configs/stm32f103-minimum/minnsh/defconfig delete mode 100644 configs/stm32f103-minimum/minnsh/setenv.sh delete mode 100644 libc/stdio/lib_lowinstream.c diff --git a/arch/arm/src/kl/Make.defs b/arch/arm/src/kl/Make.defs index d7712f0983..6af672fd46 100644 --- a/arch/arm/src/kl/Make.defs +++ b/arch/arm/src/kl/Make.defs @@ -70,7 +70,7 @@ CMN_CSRCS += up_dumpnvic.c endif CHIP_ASRCS = -CHIP_CSRCS = kl_clockconfig.c kl_gpio.c kl_idle.c kl_irq.c kl_getc.c +CHIP_CSRCS = kl_clockconfig.c kl_gpio.c kl_idle.c kl_irq.c CHIP_CSRCS += kl_lowputc.c kl_serial.c kl_start.c kl_cfmconfig.c ifneq ($(CONFIG_SCHED_TICKLESS),y) diff --git a/arch/arm/src/kl/kl_getc.c b/arch/arm/src/kl/kl_getc.c deleted file mode 100644 index 8b63ec217d..0000000000 --- a/arch/arm/src/kl/kl_getc.c +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * arch/arm/src/kl/kl_getc.c - * - * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "up_arch.h" - -#include "kl_config.h" -#include "kl_getc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Select UART parameters for the selected console */ - -#if defined(CONFIG_UART0_SERIAL_CONSOLE) -# define CONSOLE_BASE KL_UART0_BASE -#elif defined(CONFIG_UART1_SERIAL_CONSOLE) -# define CONSOLE_BASE KL_UART1_BASE -#elif defined(CONFIG_UART2_SERIAL_CONSOLE) -# define CONSOLE_BASE KL_UART2_BASE -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_getc - * - * Description: - * Input one byte from the serial console - * - * REVIST: If used with the serial driver enabled, then this could - * interfere with the serial driver operations. Serial interrupts should - * be disabled when this function executes in that case. - * - ****************************************************************************/ - -int up_getc(void) -{ - uint8_t ch = 0; - -#if defined HAVE_UART_DEVICE && defined HAVE_SERIAL_CONSOLE - /* Wait while the receiver data buffer is "empty" (RDRF) to assure that - * we have data in the buffer to read. - */ - - while ((getreg8(CONSOLE_BASE + KL_UART_S1_OFFSET) & UART_S1_RDRF) == 0); - - /* Then read a character from the UART data register */ - - ch = getreg8(CONSOLE_BASE + KL_UART_D_OFFSET); -#endif - - return (int)ch; -} diff --git a/arch/arm/src/kl/kl_getc.h b/arch/arm/src/kl/kl_getc.h deleted file mode 100644 index aff6b2a0b3..0000000000 --- a/arch/arm/src/kl/kl_getc.h +++ /dev/null @@ -1,48 +0,0 @@ -/************************************************************************************ - * arch/arm/src/kl/kl_getc.h - * - * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_KL_KINETIS_GETC_H -#define __ARCH_ARM_SRC_KL_KINETIS_GETC_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "kl_config.h" -#include "chip/kl_uart.h" - -#endif /* __ARCH_ARM_SRC_KL_KINETIS_GETC_H */ diff --git a/arch/arm/src/lpc11xx/Make.defs b/arch/arm/src/lpc11xx/Make.defs index a347d99946..d9fcb5e152 100644 --- a/arch/arm/src/lpc11xx/Make.defs +++ b/arch/arm/src/lpc11xx/Make.defs @@ -71,7 +71,7 @@ endif CHIP_ASRCS = CHIP_CSRCS = lpc11_clockconfig.c lpc11_gpio.c lpc11_i2c.c lpc11_idle.c -CHIP_CSRCS += lpc11_irq.c lpc11_lowputc.c lpc11_getc.c lpc11_serial.c +CHIP_CSRCS += lpc11_irq.c lpc11_lowputc.c lpc11_serial.c CHIP_CSRCS += lpc11_spi.c lpc11_ssp.c lpc11_start.c # Configuration-dependent LPC11xx files diff --git a/arch/arm/src/lpc11xx/lpc11_getc.c b/arch/arm/src/lpc11xx/lpc11_getc.c deleted file mode 100644 index f809e9d343..0000000000 --- a/arch/arm/src/lpc11xx/lpc11_getc.c +++ /dev/null @@ -1,95 +0,0 @@ -/**************************************************************************** - * arch/arm/src/lpc11/lpc11_getc.c - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "up_arch.h" - -#include "lpc11_getc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Select UART parameters for the selected console */ - -#if defined(CONFIG_UART0_SERIAL_CONSOLE) -# define CONSOLE_BASE LPC11_UART0_BASE -#elif defined(CONFIG_UART1_SERIAL_CONSOLE) -# define CONSOLE_BASE LPC11_UART1_BASE -#elif defined(CONFIG_UART2_SERIAL_CONSOLE) -# define CONSOLE_BASE LPC11_UART2_BASE -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_getc - * - * Description: - * Input one byte from the serial console. - * - * REVIST: If used with the serial driver enabled, then this could - * interfere with the serial driver operations. Serial interrupts should - * be disabled when this function executes in that case. - * - ****************************************************************************/ - -int up_getc(void) -{ - uint8_t ch = 0; - -#if defined HAVE_UART && defined HAVE_SERIAL_CONSOLE - /* Wait while the Receiver Data Ready (RDR) is indicating a "empty" FIFO to - * assure that we have data in the buffer to read. - */ - - while ((getreg32(CONSOLE_BASE+LPC11_UART_LSR_OFFSET) & UART_LSR_RDR) == 0); - - /* Then read a character from the UART data register */ - - ch = getreg8(CONSOLE_BASE+LPC11_UART_RBR_OFFSET); -#endif - - return (int)ch; -} diff --git a/arch/arm/src/lpc11xx/lpc11_getc.h b/arch/arm/src/lpc11xx/lpc11_getc.h deleted file mode 100644 index e00864bfc4..0000000000 --- a/arch/arm/src/lpc11xx/lpc11_getc.h +++ /dev/null @@ -1,47 +0,0 @@ -/************************************************************************************ - * arch/arm/src/lpc11/lpc11_getc.h - * - * Copyright (C) 2015, 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_GETC_H -#define __ARCH_ARM_SRC_LPC11XX_LPC11_GETC_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include "lpc11_serial.h" -#include "chip/lpc11_uart.h" - -#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_GETC_H */ diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs index 5cd3564893..8b10228a3a 100644 --- a/arch/arm/src/stm32/Make.defs +++ b/arch/arm/src/stm32/Make.defs @@ -110,7 +110,7 @@ CHIP_ASRCS = CHIP_CSRCS = stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c CHIP_CSRCS += stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c -CHIP_CSRCS += stm32_irq.c stm32_dma.c stm32_lowputc.c stm32_getc.c +CHIP_CSRCS += stm32_irq.c stm32_dma.c stm32_lowputc.c CHIP_CSRCS += stm32_serial.c stm32_spi.c stm32_sdio.c stm32_tim.c CHIP_CSRCS += stm32_waste.c stm32_ccm.c stm32_uid.c stm32_capture.c diff --git a/arch/arm/src/stm32/stm32.h b/arch/arm/src/stm32/stm32.h index f2304e2735..6680e81293 100644 --- a/arch/arm/src/stm32/stm32.h +++ b/arch/arm/src/stm32/stm32.h @@ -78,7 +78,6 @@ #include "stm32_usbdev.h" #include "stm32_wdg.h" #include "stm32_lowputc.h" -#include "stm32_getc.h" #include "stm32_eth.h" #endif /* __ARCH_ARM_SRC_STM32_STM32_H */ diff --git a/arch/arm/src/stm32/stm32_getc.c b/arch/arm/src/stm32/stm32_getc.c deleted file mode 100644 index de9020bab4..0000000000 --- a/arch/arm/src/stm32/stm32_getc.c +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_getc.c - * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "up_internal.h" -#include "up_arch.h" - -#include "chip.h" - -#include "stm32.h" -#include "stm32_rcc.h" -#include "stm32_gpio.h" -#include "stm32_uart.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Select U[S]ART console base address */ - -#ifdef HAVE_CONSOLE -# if defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_USART1_BASE -# elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_USART2_BASE -# elif defined(CONFIG_USART3_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_USART3_BASE -# elif defined(CONFIG_UART4_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_UART4_BASE -# elif defined(CONFIG_UART5_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_UART5_BASE -# elif defined(CONFIG_USART6_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_USART6_BASE -# elif defined(CONFIG_UART7_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_UART7_BASE -# elif defined(CONFIG_UART8_SERIAL_CONSOLE) -# define STM32_CONSOLE_BASE STM32_UART8_BASE -# endif -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_getc - * - * Description: - * Read one byte from the serial console - * - * REVIST: If used with the serial driver enabled, then this could - * interfere with the serial driver operations. Serial interrupts should - * be disabled when this function executes in that case. - * - ****************************************************************************/ - -int up_getc(void) -{ - uint32_t ch = 0; - -#ifdef HAVE_CONSOLE - /* While there is any error, read and discard bytes to clear the errors */ - - while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) & - (USART_SR_ORE | USART_SR_NE | USART_SR_FE | USART_SR_PE)) != 0) - { - (void)getreg32(STM32_CONSOLE_BASE + STM32_USART_RDR_OFFSET); - } - - /* Wait until the RX data register has a character to be read */ - - while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) & USART_SR_RXNE) == 0); - - /* Then read the character */ - - ch = getreg32(STM32_CONSOLE_BASE + STM32_USART_RDR_OFFSET); -#endif /* HAVE_CONSOLE */ - - return (int)ch; -} diff --git a/arch/arm/src/stm32/stm32_getc.h b/arch/arm/src/stm32/stm32_getc.h deleted file mode 100644 index 651165fba5..0000000000 --- a/arch/arm/src/stm32/stm32_getc.h +++ /dev/null @@ -1,47 +0,0 @@ -/************************************************************************************ - * arch/arm/src/stm32/stm32_getc.h - * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_GETC_H -#define __ARCH_ARM_SRC_STM32_STM32_GETC_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" - -#endif /* __ARCH_ARM_SRC_STM32_STM32_GETC_H */ diff --git a/configs/freedom-kl25z/README.txt b/configs/freedom-kl25z/README.txt index a4a806dd48..b5114b4d43 100644 --- a/configs/freedom-kl25z/README.txt +++ b/configs/freedom-kl25z/README.txt @@ -294,98 +294,6 @@ instead of configure.sh: Where is one of the following: - minnsh: - ------ - - This is a experiment to see just how small we can get a usable NSH - configuration. This configuration has far fewer features than the nsh - configuration but is also a fraction of the size. - - 2016-06-21: - $ arm-none-eabi-size nuttx - text data bss dec hex filename - 12282 196 736 13214 339e nuttx - - This minnsh configuration is a "proof-of-concept" and not very usable in - its current state. This configuration was created by disabling - everything possible INCLUDING file system support. Without file system - support, NuttX is pretty much crippled. Here are some of the - consequences of disabling the file system: - - - All features that depend on the file system are lost: device drivers, - mountpoints, message queues, named semaphores. - - - Without device drivers, you cannot interact with the RTOS using POSIX - interfaces. You would have to work with NuttX as with those other - tiny RTOSs: As a scheduler and a callable hardare abstraction layer - (HAL). - - - You cannot use any of the NuttX upper half device drivers since they - depend on the pseudo-file system and device nodes. You can, of - course, continue to use the lower half drivers either directly. Or, - perhaps, you could write some custom minnsh upper half drivers that - do not depend on a file system and expose a HAL interface. - - There is a special version of readline() the NSH uses when there is no - file system. It uses a special up_putc() to write data to the console - and a special function up_getc() to read data from the console. - - - The current up_getc() implementationsa are a kludge. They are - analogous to the up_putc() implementations: They directly poll the - hardware for serial availability, locking up all lower priority tasks - in the entire system while they poll. So a version of NSH that uses - up_getc() essentially blocks the system until a character is received. - - This, of course, could be fixed by creating a special, upper half - implementation of the interrupt-driven serial lower half (like - stm32_serial) that just supports single character console I/O - (perhaps called up_putc and up_getc?). The NSH could wait for serial - input without blocking the system. But then that would increase the - footprint too. - - So although the minnsh configurations are a good starting point for - making things small, they not are really very practical. Why might - you want a NuttX minnsh solution? Perhaps you have software that runs - on a family of chips including some very tiny MCUs. Then perhaps having - the RTOS compatibility would justify the loss of functionality? - - You can re-enable the file system and (true) serial console with - these settings: - - Enable the file system: - CONFIG_NFILE_DESCRIPTORS=5 - CONFIG_NFILE_STREAMS=5 - - Enable the console device: - CONFIG_DEV_CONSOLE=y - - Disable most new NSH commands. Some like 'ls' are really mandatory - with a file system: - CONFIG_NSH_DISABLE_xxx=y - - Enable the upper half serial driver: - CONFIG_SERIAL=y - CONFIG_STANDARD_SERIAL=y - - Enable the USART1 serial driver: - CONFIG_STM32_USART1=y - CONFIG_STM32_USART1_SERIALDRIVER=y - CONFIG_USART1_SERIAL_CONSOLE=y - - CONFIG_USART1_2STOP=0 - CONFIG_USART1_BAUD=115200 - CONFIG_USART1_BITS=8 - CONFIG_USART1_PARITY=0 - CONFIG_USART1_RXBUFSIZE=16 - CONFIG_USART1_TXBUFSIZE=16 - - With these changes, NSH should behave better and we preserve the device - driver interface. But this result in a total size increase of about - 7KB: That is about 5KB of additional OS support for the file system and - serial console PLUS about 2KB for the 'ls' command logic (including OS - support for opendir(), readdir(), closedir(), stat(), and probably other - things). - nsh: --- Configures the NuttShell (nsh) located at apps/examples/nsh. The diff --git a/configs/freedom-kl25z/minnsh/Make.defs b/configs/freedom-kl25z/minnsh/Make.defs deleted file mode 100644 index 453b86e4cf..0000000000 --- a/configs/freedom-kl25z/minnsh/Make.defs +++ /dev/null @@ -1,124 +0,0 @@ -############################################################################ -# configs/freedom-kl25z/minnsh/Make.defs -# -# Copyright (C) 2013 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk -include ${TOPDIR}/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = ld.script - -ifeq ($(WINTOOL),y) - # Windows-native toolchains - ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" - ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" - ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" -else - # Linux/Cygwin-native toolchain - ARCHINCLUDES = -I. -isystem $(TOPDIR)/include - ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx - ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) -endif - -CC = $(CROSSDEV)gcc -CXX = $(CROSSDEV)g++ -CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld -AR = $(ARCROSSDEV)ar rcs -NM = $(ARCROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} -ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION = -g -endif - -ifneq ($(CONFIG_DEBUG_NOOPT),y) - ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer -endif - -ARCHCFLAGS = -fno-builtin -ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -ARCHWARNINGSXX = -Wall -Wshadow -Wundef -ARCHDEFINES = -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -AFLAGS = $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -ASMEXT = .S -OBJEXT = .o -LIBEXT = .a -EXEEXT = - -ifneq ($(CROSSDEV),arm-nuttx-elf-) - LDFLAGS += -nostartfiles -nodefaultlibs -endif -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - LDFLAGS += -g -endif - - -HOSTCC = gcc -HOSTINCLUDES = -I. -HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe -HOSTLDFLAGS = -ifeq ($(CONFIG_HOST_WINDOWS),y) - HOSTEXEEXT = .exe -else - HOSTEXEEXT = -endif - -ifeq ($(WINTOOL),y) - # Windows-native host tools - DIRLINK = $(TOPDIR)/tools/copydir.sh - DIRUNLINK = $(TOPDIR)/tools/unlink.sh - MKDEP = $(TOPDIR)/tools/mkwindeps.sh -else - # Linux/Cygwin-native host tools - MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) -endif - diff --git a/configs/freedom-kl25z/minnsh/defconfig b/configs/freedom-kl25z/minnsh/defconfig deleted file mode 100644 index 1e47ae567a..0000000000 --- a/configs/freedom-kl25z/minnsh/defconfig +++ /dev/null @@ -1,799 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Nuttx/ Configuration -# - -# -# Build Setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_DEFAULT_SMALL=y -CONFIG_HOST_LINUX=y -# CONFIG_HOST_OSX is not set -# CONFIG_HOST_WINDOWS is not set -# CONFIG_HOST_OTHER is not set - -# -# Build Configuration -# -# CONFIG_APPS_DIR="../apps" -CONFIG_BUILD_FLAT=y -# CONFIG_BUILD_2PASS is not set - -# -# Binary Output Formats -# -# CONFIG_RRLOAD_BINARY is not set -# CONFIG_INTELHEX_BINARY is not set -CONFIG_MOTOROLA_SREC=y -CONFIG_RAW_BINARY=y -# CONFIG_UBOOT_UIMAGE is not set - -# -# Customize Header Files -# -# CONFIG_ARCH_STDINT_H is not set -# CONFIG_ARCH_STDBOOL_H is not set -# CONFIG_ARCH_MATH_H is not set -# CONFIG_ARCH_FLOAT_H is not set -# CONFIG_ARCH_STDARG_H is not set -# CONFIG_ARCH_DEBUG_H is not set - -# -# Debug Options -# -# CONFIG_DEBUG_ALERT is not set -# CONFIG_DEBUG_FEATURES is not set -CONFIG_ARCH_HAVE_STACKCHECK=y -# CONFIG_STACK_COLORATION is not set -# CONFIG_ARCH_HAVE_HEAPCHECK is not set -# CONFIG_DEBUG_SYMBOLS is not set -CONFIG_ARCH_HAVE_CUSTOMOPT=y -# CONFIG_DEBUG_NOOPT is not set -# CONFIG_DEBUG_CUSTOMOPT is not set -CONFIG_DEBUG_FULLOPT=y - -# -# System Type -# -CONFIG_ARCH_ARM=y -# CONFIG_ARCH_AVR is not set -# CONFIG_ARCH_HC is not set -# CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_SIM is not set -# CONFIG_ARCH_X86 is not set -# CONFIG_ARCH_Z16 is not set -# CONFIG_ARCH_Z80 is not set -CONFIG_ARCH="arm" - -# -# ARM Options -# -# CONFIG_ARCH_CHIP_A1X is not set -# CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set -# CONFIG_ARCH_CHIP_DM320 is not set -# CONFIG_ARCH_CHIP_EFM32 is not set -# CONFIG_ARCH_CHIP_IMX1 is not set -# CONFIG_ARCH_CHIP_IMX6 is not set -# CONFIG_ARCH_CHIP_KINETIS is not set -CONFIG_ARCH_CHIP_KL=y -# CONFIG_ARCH_CHIP_LM is not set -# CONFIG_ARCH_CHIP_TIVA is not set -# CONFIG_ARCH_CHIP_LPC11XX is not set -# CONFIG_ARCH_CHIP_LPC17XX is not set -# CONFIG_ARCH_CHIP_LPC214X is not set -# CONFIG_ARCH_CHIP_LPC2378 is not set -# CONFIG_ARCH_CHIP_LPC31XX is not set -# CONFIG_ARCH_CHIP_LPC43XX is not set -# CONFIG_ARCH_CHIP_NUC1XX is not set -# CONFIG_ARCH_CHIP_SAMA5 is not set -# CONFIG_ARCH_CHIP_SAMD is not set -# CONFIG_ARCH_CHIP_SAML is not set -# CONFIG_ARCH_CHIP_SAM34 is not set -# CONFIG_ARCH_CHIP_SAMV7 is not set -# CONFIG_ARCH_CHIP_STM32 is not set -# CONFIG_ARCH_CHIP_STM32F7 is not set -# CONFIG_ARCH_CHIP_STM32L4 is not set -# CONFIG_ARCH_CHIP_STR71X is not set -# CONFIG_ARCH_CHIP_TMS570 is not set -# CONFIG_ARCH_CHIP_MOXART is not set -# CONFIG_ARCH_ARM7TDMI is not set -# CONFIG_ARCH_ARM926EJS is not set -# CONFIG_ARCH_ARM920T is not set -CONFIG_ARCH_CORTEXM0=y -# CONFIG_ARCH_CORTEXM3 is not set -# CONFIG_ARCH_CORTEXM4 is not set -# CONFIG_ARCH_CORTEXM7 is not set -# CONFIG_ARCH_CORTEXA5 is not set -# CONFIG_ARCH_CORTEXA8 is not set -# CONFIG_ARCH_CORTEXA9 is not set -# CONFIG_ARCH_CORTEXR4 is not set -# CONFIG_ARCH_CORTEXR4F is not set -# CONFIG_ARCH_CORTEXR5 is not set -# CONFIG_ARCH_CORTEX5F is not set -# CONFIG_ARCH_CORTEXR7 is not set -# CONFIG_ARCH_CORTEXR7F is not set -CONFIG_ARCH_FAMILY="armv6-m" -CONFIG_ARCH_CHIP="kl" -# CONFIG_ARM_TOOLCHAIN_IAR is not set -# CONFIG_ARM_TOOLCHAIN_GNU is not set -CONFIG_ARCH_HAVE_CMNVECTOR=y -# CONFIG_ARMV7M_CMNVECTOR is not set -# CONFIG_ARMV7M_LAZYFPU is not set -# CONFIG_ARCH_HAVE_FPU is not set -# CONFIG_ARCH_HAVE_DPFPU is not set -# CONFIG_ARCH_HAVE_TRUSTZONE is not set -# CONFIG_ARM_HAVE_MPU_UNIFIED is not set - -# -# ARMV6M Configuration Options -# -# CONFIG_ARMV6M_TOOLCHAIN_BUILDROOT is not set -# CONFIG_ARMV6M_TOOLCHAIN_CODEREDL is not set -# CONFIG_ARMV6M_TOOLCHAIN_CODESOURCERYL is not set -CONFIG_ARMV6M_TOOLCHAIN_GNU_EABIL=y -# CONFIG_KL_GPIOIRQ is not set - -# -# Kinetis Configuration Options -# -# CONFIG_ARCH_CHIP_MKL25Z64 is not set -CONFIG_ARCH_CHIP_MKL25Z128=y -# CONFIG_ARCH_CHIP_MKL26Z128 is not set -CONFIG_ARCH_FAMILY_KL2X=y - -# -# Kinetis Peripheral Support -# -# CONFIG_KL_TRACE is not set -# CONFIG_KL_FLEXBUS is not set -CONFIG_KL_UART0=y -# CONFIG_KL_UART1 is not set -# CONFIG_KL_UART2 is not set -# CONFIG_KL_FLEXCAN0 is not set -# CONFIG_KL_FLEXCAN1 is not set -CONFIG_KL_SPI0=y -CONFIG_KL_SPI1=y -# CONFIG_KL_SPI2 is not set -# CONFIG_KL_I2C0 is not set -# CONFIG_KL_I2C1 is not set -# CONFIG_KL_I2S is not set -# CONFIG_KL_DAC0 is not set -# CONFIG_KL_DAC1 is not set -# CONFIG_KL_ADC0 is not set -# CONFIG_KL_ADC1 is not set -# CONFIG_KL_CMP is not set -# CONFIG_KL_VREF is not set -# CONFIG_KL_TPM0 is not set -# CONFIG_KL_TPM1 is not set -# CONFIG_KL_TPM2 is not set -# CONFIG_KL_LPTIMER is not set -# CONFIG_KL_RTC is not set -# CONFIG_KL_EWM is not set -# CONFIG_KL_CMT is not set -# CONFIG_KL_USBOTG is not set -# CONFIG_KL_USBDCD is not set -# CONFIG_KL_LLWU is not set -# CONFIG_KL_TSI is not set -# CONFIG_KL_FTFL is not set -# CONFIG_KL_DMA is not set -# CONFIG_KL_CRC is not set -# CONFIG_KL_PDB is not set -# CONFIG_KL_PIT is not set -CONFIG_KL_SYSTICK_CORECLK=y -# CONFIG_KL_SYSTICK_CORECLK_DIV16 is not set - -# -# Kinetis GPIO Interrupt Configuration -# - -# -# Architecture Options -# -# CONFIG_ARCH_NOINTC is not set -# CONFIG_ARCH_VECNOTIRQ is not set -# CONFIG_ARCH_DMA is not set -CONFIG_ARCH_HAVE_IRQPRIO=y -# CONFIG_ARCH_L2CACHE is not set -# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set -# CONFIG_ARCH_HAVE_ADDRENV is not set -# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set -# CONFIG_ARCH_HAVE_MULTICPU is not set -CONFIG_ARCH_HAVE_VFORK=y -# CONFIG_ARCH_HAVE_MMU is not set -# CONFIG_ARCH_HAVE_MPU is not set -# CONFIG_ARCH_NAND_HWECC is not set -# CONFIG_ARCH_HAVE_EXTCLK is not set -# CONFIG_ARCH_HAVE_POWEROFF is not set -CONFIG_ARCH_HAVE_RESET=y -# CONFIG_ARCH_IRQPRIO is not set -# CONFIG_ARCH_STACKDUMP is not set -# CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_IDLE_CUSTOM is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set -# CONFIG_ARCH_HAVE_RAMVECTORS is not set - -# -# Board Settings -# -CONFIG_BOARD_LOOPSPERMSEC=2988 -# CONFIG_ARCH_CALIBRATION is not set - -# -# Interrupt options -# -CONFIG_ARCH_HAVE_INTERRUPTSTACK=y -CONFIG_ARCH_INTERRUPTSTACK=0 -# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set - -# -# Boot options -# -# CONFIG_BOOT_RUNFROMEXTSRAM is not set -CONFIG_BOOT_RUNFROMFLASH=y -# CONFIG_BOOT_RUNFROMISRAM is not set -# CONFIG_BOOT_RUNFROMSDRAM is not set -# CONFIG_BOOT_COPYTORAM is not set - -# -# Boot Memory Configuration -# -CONFIG_RAM_START=0x1FFFF000 -CONFIG_RAM_SIZE=16384 -# CONFIG_ARCH_HAVE_SDRAM is not set - -# -# Board Selection -# -CONFIG_ARCH_BOARD_FREEDOM_KL25Z=y -# CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD="freedom-kl25z" - -# -# Common Board Options -# -CONFIG_ARCH_HAVE_LEDS=y -CONFIG_ARCH_LEDS=y -CONFIG_NSH_MMCSDMINOR=0 - -# -# Board-Specific Options -# -# CONFIG_LIB_BOARDCTL is not set - -# -# RTOS Features -# -CONFIG_DISABLE_OS_API=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_DISABLE_SIGNALS=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_ENVIRON=y - -# -# Clocks and Timers -# -CONFIG_USEC_PER_TICK=10000 -# CONFIG_SYSTEM_TIME64 is not set -# CONFIG_CLOCK_MONOTONIC is not set -# CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2013 -CONFIG_START_MONTH=2 -CONFIG_START_DAY=26 -CONFIG_MAX_WDOGPARMS=2 -CONFIG_PREALLOC_WDOGS=4 -CONFIG_WDOG_INTRESERVE=0 -CONFIG_PREALLOC_TIMERS=0 - -# -# Tasks and Scheduling -# -# CONFIG_SPINLOCK is not set -# CONFIG_INIT_NONE is not set -CONFIG_INIT_ENTRYPOINT=y -# CONFIG_INIT_FILEPATH is not set -CONFIG_USER_ENTRYPOINT="nsh_main" -CONFIG_RR_INTERVAL=0 -# CONFIG_SCHED_SPORADIC is not set -CONFIG_TASK_NAME_SIZE=0 -CONFIG_MAX_TASKS=8 -# CONFIG_SCHED_HAVE_PARENT is not set -# CONFIG_SCHED_WAITPID is not set - -# -# Performance Monitoring -# -# CONFIG_SCHED_CPULOAD is not set -# CONFIG_SCHED_INSTRUMENTATION is not set - -# -# Files and I/O -# -# CONFIG_DEV_CONSOLE is not set -CONFIG_FDCLONE_DISABLE=y -# CONFIG_FDCLONE_STDIO is not set -CONFIG_SDCLONE_DISABLE=y -CONFIG_NFILE_DESCRIPTORS=0 -CONFIG_NFILE_STREAMS=0 -CONFIG_NAME_MAX=32 -# CONFIG_PRIORITY_INHERITANCE is not set - -# -# RTOS hooks -# -# CONFIG_BOARD_INITIALIZE is not set -# CONFIG_SCHED_STARTHOOK is not set -# CONFIG_SCHED_ATEXIT is not set -# CONFIG_SCHED_ONEXIT is not set -# CONFIG_MODULE is not set - -# -# Work queue support -# - -# -# Stack and heap information -# -CONFIG_IDLETHREAD_STACKSIZE=1024 -CONFIG_USERMAIN_STACKSIZE=1536 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=1536 -# CONFIG_LIB_SYSCALL is not set - -# -# Device Drivers -# -CONFIG_DISABLE_POLL=y -# CONFIG_DEV_NULL is not set -# CONFIG_DEV_ZERO is not set -# CONFIG_DEV_LOOP is not set - -# -# Buffering -# -# CONFIG_DRVR_WRITEBUFFER is not set -# CONFIG_DRVR_READAHEAD is not set -# CONFIG_RAMDISK is not set -# CONFIG_CAN is not set -# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set -# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set -# CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set -# CONFIG_I2C is not set -CONFIG_SPI=y -# CONFIG_SPI_SLAVE is not set -CONFIG_SPI_EXCHANGE=y -# CONFIG_SPI_CMDDATA is not set -# CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set -# CONFIG_SPI_CS_DELAY_CONTROL is not set -# CONFIG_I2S is not set - -# -# Timer Driver Support -# -# CONFIG_TIMER is not set -# CONFIG_RTC is not set -# CONFIG_WATCHDOG is not set -# CONFIG_ANALOG is not set -# CONFIG_AUDIO_DEVICES is not set -# CONFIG_VIDEO_DEVICES is not set -# CONFIG_BCH is not set -# CONFIG_INPUT is not set -# CONFIG_IOEXPANDER is not set - -# -# LCD Driver Support -# -# CONFIG_LCD is not set -# CONFIG_SLCD is not set - -# -# LED Support -# -# CONFIG_USERLED is not set -# CONFIG_RGBLED is not set -# CONFIG_PCA9635PW is not set -# CONFIG_NCP5623C is not set -# CONFIG_MMCSD is not set -# CONFIG_MODEM is not set -# CONFIG_MTD is not set -# CONFIG_EEPROM is not set -# CONFIG_PIPES is not set -# CONFIG_PM is not set -# CONFIG_POWER is not set -# CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set -CONFIG_SERIAL=y -# CONFIG_SERIAL_REMOVABLE is not set -CONFIG_SERIAL_CONSOLE=y -# CONFIG_16550_UART is not set -# CONFIG_UART_SERIALDRIVER is not set -CONFIG_UART0_SERIALDRIVER=y -# CONFIG_UART1_SERIALDRIVER is not set -# CONFIG_UART2_SERIALDRIVER is not set -# CONFIG_UART3_SERIALDRIVER is not set -# CONFIG_UART4_SERIALDRIVER is not set -# CONFIG_UART5_SERIALDRIVER is not set -# CONFIG_UART6_SERIALDRIVER is not set -# CONFIG_UART7_SERIALDRIVER is not set -# CONFIG_UART8_SERIALDRIVER is not set -# CONFIG_SCI0_SERIALDRIVER is not set -# CONFIG_SCI1_SERIALDRIVER is not set -# CONFIG_USART0_SERIALDRIVER is not set -# CONFIG_USART1_SERIALDRIVER is not set -# CONFIG_USART2_SERIALDRIVER is not set -# CONFIG_USART3_SERIALDRIVER is not set -# CONFIG_USART4_SERIALDRIVER is not set -# CONFIG_USART5_SERIALDRIVER is not set -# CONFIG_USART6_SERIALDRIVER is not set -# CONFIG_USART7_SERIALDRIVER is not set -# CONFIG_USART8_SERIALDRIVER is not set -# CONFIG_OTHER_UART_SERIALDRIVER is not set -CONFIG_MCU_SERIAL=y -# CONFIG_STANDARD_SERIAL is not set -# CONFIG_SERIAL_IFLOWCONTROL is not set -# CONFIG_SERIAL_OFLOWCONTROL is not set -# CONFIG_SERIAL_DMA is not set -# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set -CONFIG_UART0_SERIAL_CONSOLE=y -# CONFIG_OTHER_SERIAL_CONSOLE is not set -# CONFIG_NO_SERIAL_CONSOLE is not set - -# -# UART0 Configuration -# -CONFIG_UART0_RXBUFSIZE=256 -CONFIG_UART0_TXBUFSIZE=256 -CONFIG_UART0_BAUD=115200 -CONFIG_UART0_BITS=8 -CONFIG_UART0_PARITY=0 -CONFIG_UART0_2STOP=0 -# CONFIG_UART0_IFLOWCONTROL is not set -# CONFIG_UART0_OFLOWCONTROL is not set -# CONFIG_UART0_DMA is not set -# CONFIG_USBDEV is not set -# CONFIG_USBHOST is not set -# CONFIG_DRIVERS_WIRELESS is not set - -# -# System Logging -# -# CONFIG_ARCH_SYSLOG is not set -# CONFIG_RAMLOG is not set -# CONFIG_SYSLOG_INTBUFFER is not set -# CONFIG_SYSLOG_TIMESTAMP is not set -# CONFIG_SYSLOG_SERIAL_CONSOLE is not set -# CONFIG_SYSLOG_CHAR is not set -CONFIG_SYSLOG_NONE=y -# CONFIG_SYSLOG_FILE is not set - -# -# Networking Support -# -# CONFIG_ARCH_HAVE_NET is not set -# CONFIG_ARCH_HAVE_PHY is not set -# CONFIG_NET is not set - -# -# Crypto API -# -# CONFIG_CRYPTO is not set - -# -# File Systems -# - -# -# File system configuration -# -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y -# CONFIG_FS_READABLE is not set -# CONFIG_FS_WRITABLE is not set -# CONFIG_FS_NAMED_SEMAPHORES is not set -# CONFIG_FS_RAMMAP is not set -# CONFIG_FS_PROCFS is not set -# CONFIG_FS_UNIONFS is not set - -# -# Graphics Support -# -# CONFIG_NX is not set - -# -# Memory Management -# -CONFIG_MM_SMALL=y -CONFIG_MM_REGIONS=1 -# CONFIG_ARCH_HAVE_HEAP2 is not set -# CONFIG_GRAN is not set - -# -# Audio Support -# -# CONFIG_AUDIO is not set - -# -# Wireless Support -# -# CONFIG_WIRELESS is not set - -# -# Binary Loader -# -# CONFIG_BINFMT_DISABLE is not set -# CONFIG_NXFLAT is not set -# CONFIG_ELF is not set -# CONFIG_BUILTIN is not set -# CONFIG_PIC is not set -# CONFIG_SYMTAB_ORDEREDBYNAME is not set - -# -# Library Routines -# - -# -# Standard C Library Options -# -CONFIG_STDIO_BUFFER_SIZE=0 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=0 -# CONFIG_LIBM is not set -CONFIG_NOPRINTF_FIELDWIDTH=y -# CONFIG_LIBC_FLOATINGPOINT is not set -# CONFIG_LIBC_LONG_LONG is not set -# CONFIG_LIBC_IOCTL_VARIADIC is not set -CONFIG_LIB_RAND_ORDER=1 -# CONFIG_EOL_IS_CR is not set -# CONFIG_EOL_IS_LF is not set -# CONFIG_EOL_IS_BOTH_CRLF is not set -CONFIG_EOL_IS_EITHER_CRLF=y -# CONFIG_LIBC_EXECFUNCS is not set -CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 -# CONFIG_LIBC_STRERROR is not set -# CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_ARCH_LOWPUTC=y -# CONFIG_TIME_EXTENDED is not set -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set -# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set -CONFIG_ARCH_HAVE_TLS=y -# CONFIG_TLS is not set -# CONFIG_LIBC_NETDB is not set - -# -# Non-standard Library Support -# -# CONFIG_LIB_CRC64_FAST is not set -# CONFIG_LIB_KBDCODEC is not set -# CONFIG_LIB_SLCDCODEC is not set - -# -# Basic CXX Support -# -# CONFIG_C99_BOOL8 is not set -# CONFIG_HAVE_CXX is not set - -# -# Application Configuration -# - -# -# CAN Utilities -# - -# -# Examples -# -# CONFIG_EXAMPLES_CHAT is not set -# CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set -# CONFIG_EXAMPLES_DHCPD is not set -# CONFIG_EXAMPLES_ELF is not set -# CONFIG_EXAMPLES_FTPC is not set -# CONFIG_EXAMPLES_FTPD is not set -# CONFIG_EXAMPLES_HELLO is not set -# CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_IGMP is not set -# CONFIG_EXAMPLES_JSON is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set -# CONFIG_EXAMPLES_MEDIA is not set -# CONFIG_EXAMPLES_MM is not set -# CONFIG_EXAMPLES_MODBUS is not set -# CONFIG_EXAMPLES_MOUNT is not set -# CONFIG_EXAMPLES_NRF24L01TERM is not set -CONFIG_EXAMPLES_NSH=y -# CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXFFS is not set -# CONFIG_EXAMPLES_NXHELLO is not set -# CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NXLINES is not set -# CONFIG_EXAMPLES_NXTERM is not set -# CONFIG_EXAMPLES_NXTEXT is not set -# CONFIG_EXAMPLES_OSTEST is not set -# CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set -# CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_PPPD is not set -# CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_SENDMAIL is not set -# CONFIG_EXAMPLES_SERIALBLASTER is not set -# CONFIG_EXAMPLES_SERIALRX is not set -# CONFIG_EXAMPLES_SERLOOP is not set -# CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART is not set -# CONFIG_EXAMPLES_SMP is not set -# CONFIG_EXAMPLES_TCPECHO is not set -# CONFIG_EXAMPLES_TELNETD is not set -# CONFIG_EXAMPLES_TIFF is not set -# CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_USBTERM is not set -# CONFIG_EXAMPLES_WATCHDOG is not set -# CONFIG_EXAMPLES_WEBSERVER is not set - -# -# File System Utilities -# -# CONFIG_FSUTILS_INIFILE is not set - -# -# GPS Utilities -# -# CONFIG_GPSUTILS_MINMEA_LIB is not set - -# -# Graphics Support -# -# CONFIG_TIFF is not set -# CONFIG_GRAPHICS_TRAVELER is not set - -# -# Interpreters -# -# CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_MICROPYTHON is not set -# CONFIG_INTERPRETERS_PCODE is not set - -# -# FreeModBus -# -# CONFIG_MODBUS is not set - -# -# Network Utilities -# -# CONFIG_NETUTILS_CODECS is not set -# CONFIG_NETUTILS_ESP8266 is not set -# CONFIG_NETUTILS_FTPC is not set -# CONFIG_NETUTILS_JSON is not set -# CONFIG_NETUTILS_SMTP is not set - -# -# NSH Library -# -CONFIG_NSH_LIBRARY=y -# CONFIG_NSH_MOTD is not set - -# -# Command Line Configuration -# -CONFIG_NSH_READLINE=y -# CONFIG_NSH_CLE is not set -CONFIG_NSH_LINELEN=80 -CONFIG_NSH_DISABLE_SEMICOLON=y -CONFIG_NSH_MAXARGUMENTS=6 -# CONFIG_NSH_ARGCAT is not set -CONFIG_NSH_NESTDEPTH=3 -# CONFIG_NSH_DISABLEBG is not set - -# -# Disable Individual commands -# -CONFIG_NSH_DISABLE_ADDROUTE=y -CONFIG_NSH_DISABLE_BASENAME=y -# CONFIG_NSH_DISABLE_CAT is not set -CONFIG_NSH_DISABLE_CD=y -CONFIG_NSH_DISABLE_CP=y -# CONFIG_NSH_DISABLE_CMP is not set -CONFIG_NSH_DISABLE_DATE=y -CONFIG_NSH_DISABLE_DD=y -CONFIG_NSH_DISABLE_DF=y -CONFIG_NSH_DISABLE_DELROUTE=y -CONFIG_NSH_DISABLE_DIRNAME=y -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_FREE is not set -CONFIG_NSH_DISABLE_GET=y -# CONFIG_NSH_DISABLE_HELP is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -CONFIG_NSH_DISABLE_IFCONFIG=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -# CONFIG_NSH_DISABLE_KILL is not set -CONFIG_NSH_DISABLE_LOSETUP=y -CONFIG_NSH_DISABLE_LOSMART=y -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_MB is not set -CONFIG_NSH_DISABLE_MKDIR=y -# CONFIG_NSH_DISABLE_MKFIFO is not set -CONFIG_NSH_DISABLE_MKRD=y -# CONFIG_NSH_DISABLE_MH is not set -CONFIG_NSH_DISABLE_MOUNT=y -# CONFIG_NSH_DISABLE_MV is not set -# CONFIG_NSH_DISABLE_MW is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_NSH_DISABLE_PUT=y -# CONFIG_NSH_DISABLE_PWD is not set -CONFIG_NSH_DISABLE_RM=y -CONFIG_NSH_DISABLE_RMDIR=y -# CONFIG_NSH_DISABLE_SET is not set -# CONFIG_NSH_DISABLE_SH is not set -# CONFIG_NSH_DISABLE_SLEEP is not set -CONFIG_NSH_DISABLE_TIME=y -# CONFIG_NSH_DISABLE_TEST is not set -CONFIG_NSH_DISABLE_UMOUNT=y -CONFIG_NSH_DISABLE_UNAME=y -# CONFIG_NSH_DISABLE_UNSET is not set -# CONFIG_NSH_DISABLE_USLEEP is not set -CONFIG_NSH_DISABLE_WGET=y -# CONFIG_NSH_DISABLE_XD is not set - -# -# Configure Command Options -# -CONFIG_NSH_CODECS_BUFSIZE=128 -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_NSH_FILEIOSIZE=64 - -# -# Scripting Support -# -CONFIG_NSH_DISABLESCRIPT=y - -# -# Console Configuration -# -CONFIG_NSH_CONSOLE=y -# CONFIG_NSH_ALTCONDEV is not set -# CONFIG_NSH_ARCHINIT is not set -# CONFIG_NSH_LOGIN is not set -# CONFIG_NSH_CONSOLE_LOGIN is not set - -# -# NxWidgets/NxWM -# - -# -# Platform-specific Support -# -# CONFIG_PLATFORM_CONFIGDATA is not set - -# -# System Libraries and NSH Add-Ons -# -# CONFIG_SYSTEM_CLE is not set -# CONFIG_SYSTEM_CUTERM is not set -# CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set -# CONFIG_SYSTEM_HEXED is not set -# CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_RAMTEST is not set -CONFIG_READLINE_HAVE_EXTMATCH=y -CONFIG_SYSTEM_READLINE=y -CONFIG_READLINE_ECHO=y -# CONFIG_READLINE_TABCOMPLETION is not set -# CONFIG_READLINE_CMD_HISTORY is not set -# CONFIG_SYSTEM_SUDOKU is not set -# CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_VI is not set -# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/freedom-kl25z/minnsh/setenv.sh b/configs/freedom-kl25z/minnsh/setenv.sh deleted file mode 100755 index 2541df62fd..0000000000 --- a/configs/freedom-kl25z/minnsh/setenv.sh +++ /dev/null @@ -1,75 +0,0 @@ -#!/bin/bash -# configs/freedom-kl25z/minnsh/setenv.sh -# -# Copyright (C) 2013 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if [ "$_" = "$0" ] ; then - echo "You must source this script, not run it!" 1>&2 - exit 1 -fi - -WD=`pwd` -if [ ! -x "setenv.sh" ]; then - echo "This script must be executed from the top-level NuttX build directory" - exit 1 -fi - -if [ -z "${PATH_ORIG}" ]; then - export PATH_ORIG="${PATH}" -fi - -# This is the Cygwin path to the location where I installed the RIDE -# toolchain under windows. You will also have to edit this if you install -# the RIDE toolchain in any other location -#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Raisonance/Ride/arm-gcc/bin" - -# This is the Cygwin path to the location where I installed the CodeSourcery -# toolchain under windows. You will also have to edit this if you install -# the CodeSourcery toolchain in any other location -#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" - -# These are the Cygwin paths to the locations where I installed the Atollic -# toolchain under windows. You will also have to edit this if you install -# the Atollic toolchain in any other location. /usr/bin is added before -# the Atollic bin path because there is are binaries named gcc.exe and g++.exe -# at those locations as well. -#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" -#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" - -# This is the Cygwin path to the location where I build the buildroot -# toolchain. -export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" - -# Add the path to the toolchain to the PATH varialble -export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" - -echo "PATH : ${PATH}" diff --git a/configs/freedom-kl26z/README.txt b/configs/freedom-kl26z/README.txt index 55f593c7d0..6237f71ad9 100644 --- a/configs/freedom-kl26z/README.txt +++ b/configs/freedom-kl26z/README.txt @@ -272,93 +272,6 @@ instead of configure.sh: Where is one of the following: - minnsh: - ------ - - This is a experiment to see just how small we can get a usable NSH - configuration. This configuration has far fewer features than the nsh - configuration but is also a fraction of the size. - - This minnsh configuration is a "proof-of-concept" and not very usable in - its current state. This configuration was created by disabling - everything possible INCLUDING file system support. Without file system - support, NuttX is pretty much crippled. Here are some of the - consequences of disabling the file system: - - - All features that depend on the file system are lost: device drivers, - mountpoints, message queues, named semaphores. - - - Without device drivers, you cannot interact with the RTOS using POSIX - interfaces. You would have to work with NuttX as with those other - tiny RTOSs: As a scheduler and a callable hardare abstraction layer - (HAL). - - - You cannot use any of the NuttX upper half device drivers since they - depend on the pseudo-file system and device nodes. You can, of - course, continue to use the lower half drivers either directly. Or, - perhaps, you could write some custom minnsh upper half drivers that - do not depend on a file system and expose a HAL interface. - - There is a special version of readline() the NSH uses when there is no - file system. It uses a special up_putc() to write data to the console - and a special function up_getc() to read data from the console. - - - The current up_getc() implementationsa are a kludge. They are - analogous to the up_putc() implementations: They directly poll the - hardware for serial availability, locking up all lower priority tasks - in the entire system while they poll. So a version of NSH that uses - up_getc() essentially blocks the system until a character is received. - - This, of course, could be fixed by creating a special, upper half - implementation of the interrupt-driven serial lower half (like - stm32_serial) that just supports single character console I/O - (perhaps called up_putc and up_getc?). The NSH could wait for serial - input without blocking the system. But then that would increase the - footprint too. - - So although the minnsh configurations are a good starting point for - making things small, they not are really very practical. Why might - you want a NuttX minnsh solution? Perhaps you have software that runs - on a family of chips including some very tiny MCUs. Then perhaps having - the RTOS compatibility would justify the loss of functionality? - - You can re-enable the file system and (true) serial console with - these settings: - - Enable the file system: - CONFIG_NFILE_DESCRIPTORS=5 - CONFIG_NFILE_STREAMS=5 - - Enable the console device: - CONFIG_DEV_CONSOLE=y - - Disable most new NSH commands. Some like 'ls' are really mandatory - with a file system: - CONFIG_NSH_DISABLE_xxx=y - - Enable the upper half serial driver: - CONFIG_SERIAL=y - CONFIG_STANDARD_SERIAL=y - - Enable the USART1 serial driver: - CONFIG_STM32_USART1=y - CONFIG_STM32_USART1_SERIALDRIVER=y - CONFIG_USART1_SERIAL_CONSOLE=y - - CONFIG_USART1_2STOP=0 - CONFIG_USART1_BAUD=115200 - CONFIG_USART1_BITS=8 - CONFIG_USART1_PARITY=0 - CONFIG_USART1_RXBUFSIZE=16 - CONFIG_USART1_TXBUFSIZE=16 - - With these changes, NSH should behave better and we preserve the device - driver interface. But this result in a total size increase of about - 7KB: That is about 5KB of additional OS support for the file system and - serial console PLUS about 2KB for the 'ls' command logic (including OS - support for opendir(), readdir(), closedir(), stat(), and probably other - things). - nsh: --- Configures the NuttShell (nsh) located at apps/examples/nsh. The diff --git a/configs/freedom-kl26z/minnsh/Make.defs b/configs/freedom-kl26z/minnsh/Make.defs deleted file mode 100644 index 380541961d..0000000000 --- a/configs/freedom-kl26z/minnsh/Make.defs +++ /dev/null @@ -1,124 +0,0 @@ -############################################################################ -# configs/freedom-kl26z/minnsh/Make.defs -# -# Copyright (C) 2015 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk -include ${TOPDIR}/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = ld.script - -ifeq ($(WINTOOL),y) - # Windows-native toolchains - ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" - ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" - ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" -else - # Linux/Cygwin-native toolchain - ARCHINCLUDES = -I. -isystem $(TOPDIR)/include - ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx - ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) -endif - -CC = $(CROSSDEV)gcc -CXX = $(CROSSDEV)g++ -CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld -AR = $(ARCROSSDEV)ar rcs -NM = $(ARCROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} -ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION = -g -endif - -ifneq ($(CONFIG_DEBUG_NOOPT),y) - ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer -endif - -ARCHCFLAGS = -fno-builtin -ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -ARCHWARNINGSXX = -Wall -Wshadow -Wundef -ARCHDEFINES = -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -AFLAGS = $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -ASMEXT = .S -OBJEXT = .o -LIBEXT = .a -EXEEXT = - -ifneq ($(CROSSDEV),arm-nuttx-elf-) - LDFLAGS += -nostartfiles -nodefaultlibs -endif -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - LDFLAGS += -g -endif - - -HOSTCC = gcc -HOSTINCLUDES = -I. -HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe -HOSTLDFLAGS = -ifeq ($(CONFIG_HOST_WINDOWS),y) - HOSTEXEEXT = .exe -else - HOSTEXEEXT = -endif - -ifeq ($(WINTOOL),y) - # Windows-native host tools - DIRLINK = $(TOPDIR)/tools/copydir.sh - DIRUNLINK = $(TOPDIR)/tools/unlink.sh - MKDEP = $(TOPDIR)/tools/mkwindeps.sh -else - # Linux/Cygwin-native host tools - MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) -endif - diff --git a/configs/freedom-kl26z/minnsh/defconfig b/configs/freedom-kl26z/minnsh/defconfig deleted file mode 100644 index 480cd09801..0000000000 --- a/configs/freedom-kl26z/minnsh/defconfig +++ /dev/null @@ -1,799 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Nuttx/ Configuration -# - -# -# Build Setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_DEFAULT_SMALL=y -CONFIG_HOST_LINUX=y -# CONFIG_HOST_OSX is not set -# CONFIG_HOST_WINDOWS is not set -# CONFIG_HOST_OTHER is not set - -# -# Build Configuration -# -# CONFIG_APPS_DIR="../apps" -CONFIG_BUILD_FLAT=y -# CONFIG_BUILD_2PASS is not set - -# -# Binary Output Formats -# -# CONFIG_RRLOAD_BINARY is not set -# CONFIG_INTELHEX_BINARY is not set -CONFIG_MOTOROLA_SREC=y -CONFIG_RAW_BINARY=y -# CONFIG_UBOOT_UIMAGE is not set - -# -# Customize Header Files -# -# CONFIG_ARCH_STDINT_H is not set -# CONFIG_ARCH_STDBOOL_H is not set -# CONFIG_ARCH_MATH_H is not set -# CONFIG_ARCH_FLOAT_H is not set -# CONFIG_ARCH_STDARG_H is not set -# CONFIG_ARCH_DEBUG_H is not set - -# -# Debug Options -# -# CONFIG_DEBUG_ALERT is not set -# CONFIG_DEBUG_FEATURES is not set -CONFIG_ARCH_HAVE_STACKCHECK=y -# CONFIG_STACK_COLORATION is not set -# CONFIG_ARCH_HAVE_HEAPCHECK is not set -# CONFIG_DEBUG_SYMBOLS is not set -CONFIG_ARCH_HAVE_CUSTOMOPT=y -# CONFIG_DEBUG_NOOPT is not set -# CONFIG_DEBUG_CUSTOMOPT is not set -CONFIG_DEBUG_FULLOPT=y - -# -# System Type -# -CONFIG_ARCH_ARM=y -# CONFIG_ARCH_AVR is not set -# CONFIG_ARCH_HC is not set -# CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_SIM is not set -# CONFIG_ARCH_X86 is not set -# CONFIG_ARCH_Z16 is not set -# CONFIG_ARCH_Z80 is not set -CONFIG_ARCH="arm" - -# -# ARM Options -# -# CONFIG_ARCH_CHIP_A1X is not set -# CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set -# CONFIG_ARCH_CHIP_DM320 is not set -# CONFIG_ARCH_CHIP_EFM32 is not set -# CONFIG_ARCH_CHIP_IMX1 is not set -# CONFIG_ARCH_CHIP_IMX6 is not set -# CONFIG_ARCH_CHIP_KINETIS is not set -CONFIG_ARCH_CHIP_KL=y -# CONFIG_ARCH_CHIP_LM is not set -# CONFIG_ARCH_CHIP_TIVA is not set -# CONFIG_ARCH_CHIP_LPC11XX is not set -# CONFIG_ARCH_CHIP_LPC17XX is not set -# CONFIG_ARCH_CHIP_LPC214X is not set -# CONFIG_ARCH_CHIP_LPC2378 is not set -# CONFIG_ARCH_CHIP_LPC31XX is not set -# CONFIG_ARCH_CHIP_LPC43XX is not set -# CONFIG_ARCH_CHIP_NUC1XX is not set -# CONFIG_ARCH_CHIP_SAMA5 is not set -# CONFIG_ARCH_CHIP_SAMD is not set -# CONFIG_ARCH_CHIP_SAML is not set -# CONFIG_ARCH_CHIP_SAM34 is not set -# CONFIG_ARCH_CHIP_SAMV7 is not set -# CONFIG_ARCH_CHIP_STM32 is not set -# CONFIG_ARCH_CHIP_STM32F7 is not set -# CONFIG_ARCH_CHIP_STM32L4 is not set -# CONFIG_ARCH_CHIP_STR71X is not set -# CONFIG_ARCH_CHIP_TMS570 is not set -# CONFIG_ARCH_CHIP_MOXART is not set -# CONFIG_ARCH_ARM7TDMI is not set -# CONFIG_ARCH_ARM926EJS is not set -# CONFIG_ARCH_ARM920T is not set -CONFIG_ARCH_CORTEXM0=y -# CONFIG_ARCH_CORTEXM3 is not set -# CONFIG_ARCH_CORTEXM4 is not set -# CONFIG_ARCH_CORTEXM7 is not set -# CONFIG_ARCH_CORTEXA5 is not set -# CONFIG_ARCH_CORTEXA8 is not set -# CONFIG_ARCH_CORTEXA9 is not set -# CONFIG_ARCH_CORTEXR4 is not set -# CONFIG_ARCH_CORTEXR4F is not set -# CONFIG_ARCH_CORTEXR5 is not set -# CONFIG_ARCH_CORTEX5F is not set -# CONFIG_ARCH_CORTEXR7 is not set -# CONFIG_ARCH_CORTEXR7F is not set -CONFIG_ARCH_FAMILY="armv6-m" -CONFIG_ARCH_CHIP="kl" -# CONFIG_ARM_TOOLCHAIN_IAR is not set -# CONFIG_ARM_TOOLCHAIN_GNU is not set -CONFIG_ARCH_HAVE_CMNVECTOR=y -# CONFIG_ARMV7M_CMNVECTOR is not set -# CONFIG_ARMV7M_LAZYFPU is not set -# CONFIG_ARCH_HAVE_FPU is not set -# CONFIG_ARCH_HAVE_DPFPU is not set -# CONFIG_ARCH_HAVE_TRUSTZONE is not set -# CONFIG_ARM_HAVE_MPU_UNIFIED is not set - -# -# ARMV6M Configuration Options -# -# CONFIG_ARMV6M_TOOLCHAIN_BUILDROOT is not set -# CONFIG_ARMV6M_TOOLCHAIN_CODEREDL is not set -# CONFIG_ARMV6M_TOOLCHAIN_CODESOURCERYL is not set -CONFIG_ARMV6M_TOOLCHAIN_GNU_EABIL=y -# CONFIG_KL_GPIOIRQ is not set - -# -# Kinetis Configuration Options -# -# CONFIG_ARCH_CHIP_MKL25Z64 is not set -# CONFIG_ARCH_CHIP_MKL25Z128 is not set -CONFIG_ARCH_CHIP_MKL26Z128=y -CONFIG_ARCH_FAMILY_KL2X=y - -# -# Kinetis Peripheral Support -# -# CONFIG_KL_TRACE is not set -# CONFIG_KL_FLEXBUS is not set -CONFIG_KL_UART0=y -# CONFIG_KL_UART1 is not set -# CONFIG_KL_UART2 is not set -# CONFIG_KL_FLEXCAN0 is not set -# CONFIG_KL_FLEXCAN1 is not set -CONFIG_KL_SPI0=y -CONFIG_KL_SPI1=y -# CONFIG_KL_SPI2 is not set -# CONFIG_KL_I2C0 is not set -# CONFIG_KL_I2C1 is not set -# CONFIG_KL_I2S is not set -# CONFIG_KL_DAC0 is not set -# CONFIG_KL_DAC1 is not set -# CONFIG_KL_ADC0 is not set -# CONFIG_KL_ADC1 is not set -# CONFIG_KL_CMP is not set -# CONFIG_KL_VREF is not set -# CONFIG_KL_TPM0 is not set -# CONFIG_KL_TPM1 is not set -# CONFIG_KL_TPM2 is not set -# CONFIG_KL_LPTIMER is not set -# CONFIG_KL_RTC is not set -# CONFIG_KL_EWM is not set -# CONFIG_KL_CMT is not set -# CONFIG_KL_USBOTG is not set -# CONFIG_KL_USBDCD is not set -# CONFIG_KL_LLWU is not set -# CONFIG_KL_TSI is not set -# CONFIG_KL_FTFL is not set -# CONFIG_KL_DMA is not set -# CONFIG_KL_CRC is not set -# CONFIG_KL_PDB is not set -# CONFIG_KL_PIT is not set -CONFIG_KL_SYSTICK_CORECLK=y -# CONFIG_KL_SYSTICK_CORECLK_DIV16 is not set - -# -# Kinetis GPIO Interrupt Configuration -# - -# -# Architecture Options -# -# CONFIG_ARCH_NOINTC is not set -# CONFIG_ARCH_VECNOTIRQ is not set -# CONFIG_ARCH_DMA is not set -CONFIG_ARCH_HAVE_IRQPRIO=y -# CONFIG_ARCH_L2CACHE is not set -# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set -# CONFIG_ARCH_HAVE_ADDRENV is not set -# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set -# CONFIG_ARCH_HAVE_MULTICPU is not set -CONFIG_ARCH_HAVE_VFORK=y -# CONFIG_ARCH_HAVE_MMU is not set -# CONFIG_ARCH_HAVE_MPU is not set -# CONFIG_ARCH_NAND_HWECC is not set -# CONFIG_ARCH_HAVE_EXTCLK is not set -# CONFIG_ARCH_HAVE_POWEROFF is not set -CONFIG_ARCH_HAVE_RESET=y -# CONFIG_ARCH_IRQPRIO is not set -# CONFIG_ARCH_STACKDUMP is not set -# CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_IDLE_CUSTOM is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set -# CONFIG_ARCH_HAVE_RAMVECTORS is not set - -# -# Board Settings -# -CONFIG_BOARD_LOOPSPERMSEC=2988 -# CONFIG_ARCH_CALIBRATION is not set - -# -# Interrupt options -# -CONFIG_ARCH_HAVE_INTERRUPTSTACK=y -CONFIG_ARCH_INTERRUPTSTACK=0 -# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set - -# -# Boot options -# -# CONFIG_BOOT_RUNFROMEXTSRAM is not set -CONFIG_BOOT_RUNFROMFLASH=y -# CONFIG_BOOT_RUNFROMISRAM is not set -# CONFIG_BOOT_RUNFROMSDRAM is not set -# CONFIG_BOOT_COPYTORAM is not set - -# -# Boot Memory Configuration -# -CONFIG_RAM_START=0x1FFFF000 -CONFIG_RAM_SIZE=16384 -# CONFIG_ARCH_HAVE_SDRAM is not set - -# -# Board Selection -# -CONFIG_ARCH_BOARD_FREEDOM_KL26Z=y -# CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD="freedom-kl26z" - -# -# Common Board Options -# -CONFIG_ARCH_HAVE_LEDS=y -CONFIG_ARCH_LEDS=y -CONFIG_NSH_MMCSDMINOR=0 - -# -# Board-Specific Options -# -# CONFIG_LIB_BOARDCTL is not set - -# -# RTOS Features -# -CONFIG_DISABLE_OS_API=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_DISABLE_SIGNALS=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_ENVIRON=y - -# -# Clocks and Timers -# -CONFIG_USEC_PER_TICK=10000 -# CONFIG_SYSTEM_TIME64 is not set -# CONFIG_CLOCK_MONOTONIC is not set -# CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2013 -CONFIG_START_MONTH=2 -CONFIG_START_DAY=26 -CONFIG_MAX_WDOGPARMS=2 -CONFIG_PREALLOC_WDOGS=4 -CONFIG_WDOG_INTRESERVE=0 -CONFIG_PREALLOC_TIMERS=0 - -# -# Tasks and Scheduling -# -# CONFIG_SPINLOCK is not set -# CONFIG_INIT_NONE is not set -CONFIG_INIT_ENTRYPOINT=y -# CONFIG_INIT_FILEPATH is not set -CONFIG_USER_ENTRYPOINT="nsh_main" -CONFIG_RR_INTERVAL=0 -# CONFIG_SCHED_SPORADIC is not set -CONFIG_TASK_NAME_SIZE=0 -CONFIG_MAX_TASKS=8 -# CONFIG_SCHED_HAVE_PARENT is not set -# CONFIG_SCHED_WAITPID is not set - -# -# Performance Monitoring -# -# CONFIG_SCHED_CPULOAD is not set -# CONFIG_SCHED_INSTRUMENTATION is not set - -# -# Files and I/O -# -# CONFIG_DEV_CONSOLE is not set -CONFIG_FDCLONE_DISABLE=y -# CONFIG_FDCLONE_STDIO is not set -CONFIG_SDCLONE_DISABLE=y -CONFIG_NFILE_DESCRIPTORS=0 -CONFIG_NFILE_STREAMS=0 -CONFIG_NAME_MAX=32 -# CONFIG_PRIORITY_INHERITANCE is not set - -# -# RTOS hooks -# -# CONFIG_BOARD_INITIALIZE is not set -# CONFIG_SCHED_STARTHOOK is not set -# CONFIG_SCHED_ATEXIT is not set -# CONFIG_SCHED_ONEXIT is not set -# CONFIG_MODULE is not set - -# -# Work queue support -# - -# -# Stack and heap information -# -CONFIG_IDLETHREAD_STACKSIZE=1024 -CONFIG_USERMAIN_STACKSIZE=1536 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=1536 -# CONFIG_LIB_SYSCALL is not set - -# -# Device Drivers -# -CONFIG_DISABLE_POLL=y -# CONFIG_DEV_NULL is not set -# CONFIG_DEV_ZERO is not set -# CONFIG_DEV_LOOP is not set - -# -# Buffering -# -# CONFIG_DRVR_WRITEBUFFER is not set -# CONFIG_DRVR_READAHEAD is not set -# CONFIG_RAMDISK is not set -# CONFIG_CAN is not set -# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set -# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set -# CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set -# CONFIG_I2C is not set -CONFIG_SPI=y -# CONFIG_SPI_SLAVE is not set -CONFIG_SPI_EXCHANGE=y -# CONFIG_SPI_CMDDATA is not set -# CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set -# CONFIG_SPI_CS_DELAY_CONTROL is not set -# CONFIG_I2S is not set - -# -# Timer Driver Support -# -# CONFIG_TIMER is not set -# CONFIG_RTC is not set -# CONFIG_WATCHDOG is not set -# CONFIG_ANALOG is not set -# CONFIG_AUDIO_DEVICES is not set -# CONFIG_VIDEO_DEVICES is not set -# CONFIG_BCH is not set -# CONFIG_INPUT is not set -# CONFIG_IOEXPANDER is not set - -# -# LCD Driver Support -# -# CONFIG_LCD is not set -# CONFIG_SLCD is not set - -# -# LED Support -# -# CONFIG_USERLED is not set -# CONFIG_RGBLED is not set -# CONFIG_PCA9635PW is not set -# CONFIG_NCP5623C is not set -# CONFIG_MMCSD is not set -# CONFIG_MODEM is not set -# CONFIG_MTD is not set -# CONFIG_EEPROM is not set -# CONFIG_PIPES is not set -# CONFIG_PM is not set -# CONFIG_POWER is not set -# CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set -CONFIG_SERIAL=y -# CONFIG_SERIAL_REMOVABLE is not set -CONFIG_SERIAL_CONSOLE=y -# CONFIG_16550_UART is not set -# CONFIG_UART_SERIALDRIVER is not set -CONFIG_UART0_SERIALDRIVER=y -# CONFIG_UART1_SERIALDRIVER is not set -# CONFIG_UART2_SERIALDRIVER is not set -# CONFIG_UART3_SERIALDRIVER is not set -# CONFIG_UART4_SERIALDRIVER is not set -# CONFIG_UART5_SERIALDRIVER is not set -# CONFIG_UART6_SERIALDRIVER is not set -# CONFIG_UART7_SERIALDRIVER is not set -# CONFIG_UART8_SERIALDRIVER is not set -# CONFIG_SCI0_SERIALDRIVER is not set -# CONFIG_SCI1_SERIALDRIVER is not set -# CONFIG_USART0_SERIALDRIVER is not set -# CONFIG_USART1_SERIALDRIVER is not set -# CONFIG_USART2_SERIALDRIVER is not set -# CONFIG_USART3_SERIALDRIVER is not set -# CONFIG_USART4_SERIALDRIVER is not set -# CONFIG_USART5_SERIALDRIVER is not set -# CONFIG_USART6_SERIALDRIVER is not set -# CONFIG_USART7_SERIALDRIVER is not set -# CONFIG_USART8_SERIALDRIVER is not set -# CONFIG_OTHER_UART_SERIALDRIVER is not set -CONFIG_MCU_SERIAL=y -# CONFIG_STANDARD_SERIAL is not set -# CONFIG_SERIAL_IFLOWCONTROL is not set -# CONFIG_SERIAL_OFLOWCONTROL is not set -# CONFIG_SERIAL_DMA is not set -# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set -CONFIG_UART0_SERIAL_CONSOLE=y -# CONFIG_OTHER_SERIAL_CONSOLE is not set -# CONFIG_NO_SERIAL_CONSOLE is not set - -# -# UART0 Configuration -# -CONFIG_UART0_RXBUFSIZE=256 -CONFIG_UART0_TXBUFSIZE=256 -CONFIG_UART0_BAUD=115200 -CONFIG_UART0_BITS=8 -CONFIG_UART0_PARITY=0 -CONFIG_UART0_2STOP=0 -# CONFIG_UART0_IFLOWCONTROL is not set -# CONFIG_UART0_OFLOWCONTROL is not set -# CONFIG_UART0_DMA is not set -# CONFIG_USBDEV is not set -# CONFIG_USBHOST is not set -# CONFIG_DRIVERS_WIRELESS is not set - -# -# System Logging -# -# CONFIG_ARCH_SYSLOG is not set -# CONFIG_RAMLOG is not set -# CONFIG_SYSLOG_INTBUFFER is not set -# CONFIG_SYSLOG_TIMESTAMP is not set -# CONFIG_SYSLOG_SERIAL_CONSOLE is not set -# CONFIG_SYSLOG_CHAR is not set -CONFIG_SYSLOG_NONE=y -# CONFIG_SYSLOG_FILE is not set - -# -# Networking Support -# -# CONFIG_ARCH_HAVE_NET is not set -# CONFIG_ARCH_HAVE_PHY is not set -# CONFIG_NET is not set - -# -# Crypto API -# -# CONFIG_CRYPTO is not set - -# -# File Systems -# - -# -# File system configuration -# -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y -# CONFIG_FS_READABLE is not set -# CONFIG_FS_WRITABLE is not set -# CONFIG_FS_NAMED_SEMAPHORES is not set -# CONFIG_FS_RAMMAP is not set -# CONFIG_FS_PROCFS is not set -# CONFIG_FS_UNIONFS is not set - -# -# Graphics Support -# -# CONFIG_NX is not set - -# -# Memory Management -# -CONFIG_MM_SMALL=y -CONFIG_MM_REGIONS=1 -# CONFIG_ARCH_HAVE_HEAP2 is not set -# CONFIG_GRAN is not set - -# -# Audio Support -# -# CONFIG_AUDIO is not set - -# -# Wireless Support -# -# CONFIG_WIRELESS is not set - -# -# Binary Loader -# -# CONFIG_BINFMT_DISABLE is not set -# CONFIG_NXFLAT is not set -# CONFIG_ELF is not set -# CONFIG_BUILTIN is not set -# CONFIG_PIC is not set -# CONFIG_SYMTAB_ORDEREDBYNAME is not set - -# -# Library Routines -# - -# -# Standard C Library Options -# -CONFIG_STDIO_BUFFER_SIZE=0 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=0 -# CONFIG_LIBM is not set -CONFIG_NOPRINTF_FIELDWIDTH=y -# CONFIG_LIBC_FLOATINGPOINT is not set -# CONFIG_LIBC_LONG_LONG is not set -# CONFIG_LIBC_IOCTL_VARIADIC is not set -CONFIG_LIB_RAND_ORDER=1 -# CONFIG_EOL_IS_CR is not set -# CONFIG_EOL_IS_LF is not set -# CONFIG_EOL_IS_BOTH_CRLF is not set -CONFIG_EOL_IS_EITHER_CRLF=y -# CONFIG_LIBC_EXECFUNCS is not set -CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 -# CONFIG_LIBC_STRERROR is not set -# CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_ARCH_LOWPUTC=y -# CONFIG_TIME_EXTENDED is not set -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set -# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set -CONFIG_ARCH_HAVE_TLS=y -# CONFIG_TLS is not set -# CONFIG_LIBC_NETDB is not set - -# -# Non-standard Library Support -# -# CONFIG_LIB_CRC64_FAST is not set -# CONFIG_LIB_KBDCODEC is not set -# CONFIG_LIB_SLCDCODEC is not set - -# -# Basic CXX Support -# -# CONFIG_C99_BOOL8 is not set -# CONFIG_HAVE_CXX is not set - -# -# Application Configuration -# - -# -# CAN Utilities -# - -# -# Examples -# -# CONFIG_EXAMPLES_CHAT is not set -# CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set -# CONFIG_EXAMPLES_DHCPD is not set -# CONFIG_EXAMPLES_ELF is not set -# CONFIG_EXAMPLES_FTPC is not set -# CONFIG_EXAMPLES_FTPD is not set -# CONFIG_EXAMPLES_HELLO is not set -# CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_IGMP is not set -# CONFIG_EXAMPLES_JSON is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set -# CONFIG_EXAMPLES_MEDIA is not set -# CONFIG_EXAMPLES_MM is not set -# CONFIG_EXAMPLES_MODBUS is not set -# CONFIG_EXAMPLES_MOUNT is not set -# CONFIG_EXAMPLES_NRF24L01TERM is not set -CONFIG_EXAMPLES_NSH=y -# CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXFFS is not set -# CONFIG_EXAMPLES_NXHELLO is not set -# CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NXLINES is not set -# CONFIG_EXAMPLES_NXTERM is not set -# CONFIG_EXAMPLES_NXTEXT is not set -# CONFIG_EXAMPLES_OSTEST is not set -# CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set -# CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_PPPD is not set -# CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_SENDMAIL is not set -# CONFIG_EXAMPLES_SERIALBLASTER is not set -# CONFIG_EXAMPLES_SERIALRX is not set -# CONFIG_EXAMPLES_SERLOOP is not set -# CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART is not set -# CONFIG_EXAMPLES_SMP is not set -# CONFIG_EXAMPLES_TCPECHO is not set -# CONFIG_EXAMPLES_TELNETD is not set -# CONFIG_EXAMPLES_TIFF is not set -# CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_USBTERM is not set -# CONFIG_EXAMPLES_WATCHDOG is not set -# CONFIG_EXAMPLES_WEBSERVER is not set - -# -# File System Utilities -# -# CONFIG_FSUTILS_INIFILE is not set - -# -# GPS Utilities -# -# CONFIG_GPSUTILS_MINMEA_LIB is not set - -# -# Graphics Support -# -# CONFIG_TIFF is not set -# CONFIG_GRAPHICS_TRAVELER is not set - -# -# Interpreters -# -# CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_MICROPYTHON is not set -# CONFIG_INTERPRETERS_PCODE is not set - -# -# FreeModBus -# -# CONFIG_MODBUS is not set - -# -# Network Utilities -# -# CONFIG_NETUTILS_CODECS is not set -# CONFIG_NETUTILS_ESP8266 is not set -# CONFIG_NETUTILS_FTPC is not set -# CONFIG_NETUTILS_JSON is not set -# CONFIG_NETUTILS_SMTP is not set - -# -# NSH Library -# -CONFIG_NSH_LIBRARY=y -# CONFIG_NSH_MOTD is not set - -# -# Command Line Configuration -# -CONFIG_NSH_READLINE=y -# CONFIG_NSH_CLE is not set -CONFIG_NSH_LINELEN=80 -CONFIG_NSH_DISABLE_SEMICOLON=y -CONFIG_NSH_MAXARGUMENTS=6 -# CONFIG_NSH_ARGCAT is not set -CONFIG_NSH_NESTDEPTH=3 -# CONFIG_NSH_DISABLEBG is not set - -# -# Disable Individual commands -# -CONFIG_NSH_DISABLE_ADDROUTE=y -CONFIG_NSH_DISABLE_BASENAME=y -# CONFIG_NSH_DISABLE_CAT is not set -CONFIG_NSH_DISABLE_CD=y -CONFIG_NSH_DISABLE_CP=y -# CONFIG_NSH_DISABLE_CMP is not set -CONFIG_NSH_DISABLE_DATE=y -CONFIG_NSH_DISABLE_DD=y -CONFIG_NSH_DISABLE_DF=y -CONFIG_NSH_DISABLE_DELROUTE=y -CONFIG_NSH_DISABLE_DIRNAME=y -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_FREE is not set -CONFIG_NSH_DISABLE_GET=y -# CONFIG_NSH_DISABLE_HELP is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -CONFIG_NSH_DISABLE_IFCONFIG=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -# CONFIG_NSH_DISABLE_KILL is not set -CONFIG_NSH_DISABLE_LOSETUP=y -CONFIG_NSH_DISABLE_LOSMART=y -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_MB is not set -CONFIG_NSH_DISABLE_MKDIR=y -# CONFIG_NSH_DISABLE_MKFIFO is not set -CONFIG_NSH_DISABLE_MKRD=y -# CONFIG_NSH_DISABLE_MH is not set -CONFIG_NSH_DISABLE_MOUNT=y -# CONFIG_NSH_DISABLE_MV is not set -# CONFIG_NSH_DISABLE_MW is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_NSH_DISABLE_PUT=y -# CONFIG_NSH_DISABLE_PWD is not set -CONFIG_NSH_DISABLE_RM=y -CONFIG_NSH_DISABLE_RMDIR=y -# CONFIG_NSH_DISABLE_SET is not set -# CONFIG_NSH_DISABLE_SH is not set -# CONFIG_NSH_DISABLE_SLEEP is not set -CONFIG_NSH_DISABLE_TIME=y -# CONFIG_NSH_DISABLE_TEST is not set -CONFIG_NSH_DISABLE_UMOUNT=y -CONFIG_NSH_DISABLE_UNAME=y -# CONFIG_NSH_DISABLE_UNSET is not set -# CONFIG_NSH_DISABLE_USLEEP is not set -CONFIG_NSH_DISABLE_WGET=y -# CONFIG_NSH_DISABLE_XD is not set - -# -# Configure Command Options -# -CONFIG_NSH_CODECS_BUFSIZE=128 -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_NSH_FILEIOSIZE=64 - -# -# Scripting Support -# -CONFIG_NSH_DISABLESCRIPT=y - -# -# Console Configuration -# -CONFIG_NSH_CONSOLE=y -# CONFIG_NSH_ALTCONDEV is not set -# CONFIG_NSH_ARCHINIT is not set -# CONFIG_NSH_LOGIN is not set -# CONFIG_NSH_CONSOLE_LOGIN is not set - -# -# NxWidgets/NxWM -# - -# -# Platform-specific Support -# -# CONFIG_PLATFORM_CONFIGDATA is not set - -# -# System Libraries and NSH Add-Ons -# -# CONFIG_SYSTEM_CLE is not set -# CONFIG_SYSTEM_CUTERM is not set -# CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set -# CONFIG_SYSTEM_HEXED is not set -# CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_RAMTEST is not set -CONFIG_READLINE_HAVE_EXTMATCH=y -CONFIG_SYSTEM_READLINE=y -CONFIG_READLINE_ECHO=y -# CONFIG_READLINE_TABCOMPLETION is not set -# CONFIG_READLINE_CMD_HISTORY is not set -# CONFIG_SYSTEM_SUDOKU is not set -# CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_VI is not set -# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/freedom-kl26z/minnsh/setenv.sh b/configs/freedom-kl26z/minnsh/setenv.sh deleted file mode 100755 index 755c02b4b6..0000000000 --- a/configs/freedom-kl26z/minnsh/setenv.sh +++ /dev/null @@ -1,71 +0,0 @@ -#!/bin/bash -# configs/freedom-kl26z/minnsh/setenv.sh -# -# Copyright (C) 2015 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if [ "$_" = "$0" ] ; then - echo "You must source this script, not run it!" 1>&2 - exit 1 -fi - -WD=`pwd` -if [ ! -x "setenv.sh" ]; then - echo "This script must be executed from the top-level NuttX build directory" - exit 1 -fi - -if [ -z "${PATH_ORIG}" ]; then - export PATH_ORIG="${PATH}" -fi - -# This is the Cygwin path to the location where I installed the CodeSourcery -# toolchain under windows. You will also have to edit this if you install -# the CodeSourcery toolchain in any other location -#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" -#export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" - -# These are the Cygwin paths to the locations where I installed the Atollic -# toolchain under windows. You will also have to edit this if you install -# the Atollic toolchain in any other location. /usr/bin is added before -# the Atollic bin path because there is are binaries named gcc.exe and g++.exe -# at those locations as well. -#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" -#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" - -# This is the Cygwin path to the location where I build the buildroot -# toolchain. -export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" - -# Add the path to the toolchain to the PATH varialble -export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" - -echo "PATH : ${PATH}" diff --git a/configs/lpcxpresso-lpc1115/README.txt b/configs/lpcxpresso-lpc1115/README.txt index bfe29dc6d5..168bed5198 100644 --- a/configs/lpcxpresso-lpc1115/README.txt +++ b/configs/lpcxpresso-lpc1115/README.txt @@ -680,144 +680,6 @@ selected as follow: Where is one of the following: - minnsh: - ------ - - This is a experiment to see just how small we can get a usable NSH - configuration. This configuration has far fewer features than the nsh - configuration but is also a fraction of the size. - - This minnsh configuration is a "proof-of-concept" and not very usable in - its current state. This configuration was created by disabling - everything possible INCLUDING file system support. Without file system - support, NuttX is pretty much crippled. Here are some of the - consequences of disabling the file system: - - - All features that depend on the file system are lost: device drivers, - mountpoints, message queues, named semaphores. - - - Without device drivers, you cannot interact with the RTOS using POSIX - interfaces. You would have to work with NuttX as with those other - tiny RTOSs: As a scheduler and a callable hardare abstraction layer - (HAL). - - - You cannot use any of the NuttX upper half device drivers since they - depend on the pseudo-file system and device nodes. You can, of - course, continue to use the lower half drivers either directly. Or, - perhaps, you could write some custom minnsh upper half drivers that - do not depend on a file system and expose a HAL interface. - - There is a special version of readline() the NSH uses when there is no - file system. It uses a special up_putc() to write data to the console - and a special function up_getc() to read data from the console. - - - The current up_getc() implementationsa are a kludge. They are - analogous to the up_putc() implementations: They directly poll the - hardware for serial availability, locking up all lower priority tasks - in the entire system while they poll. So a version of NSH that uses - up_getc() essentially blocks the system until a character is received. - - This, of course, could be fixed by creating a special, upper half - implementation of the interrupt-driven serial lower half (like - stm32_serial) that just supports single character console I/O - (perhaps called up_putc and up_getc?). The NSH could wait for serial - input without blocking the system. But then that would increase the - footprint too. - - So although the minnsh configurations are a good starting point for - making things small, they not are really very practical. Why might - you want a NuttX minnsh solution? Perhaps you have software that runs - on a family of chips including some very tiny MCUs. Then perhaps having - the RTOS compatibility would justify the loss of functionality? - - You can re-enable the file system and (true) serial console with - these settings: - - Enable the file system: - CONFIG_NFILE_DESCRIPTORS=5 - CONFIG_NFILE_STREAMS=5 - - Enable the console device: - CONFIG_DEV_CONSOLE=y - - Disable most new NSH commands. Some like 'ls' are really mandatory - with a file system: - CONFIG_NSH_DISABLE_xxx=y - - Enable the upper half serial driver: - CONFIG_SERIAL=y - CONFIG_STANDARD_SERIAL=y - - Enable the USART1 serial driver: - CONFIG_STM32_USART1=y - CONFIG_STM32_USART1_SERIALDRIVER=y - CONFIG_USART1_SERIAL_CONSOLE=y - - CONFIG_USART1_2STOP=0 - CONFIG_USART1_BAUD=115200 - CONFIG_USART1_BITS=8 - CONFIG_USART1_PARITY=0 - CONFIG_USART1_RXBUFSIZE=16 - CONFIG_USART1_TXBUFSIZE=16 - - With these changes, NSH should behave better and we preserve the device - driver interface. But this result in a total size increase of about - 7KB: That is about 5KB of additional OS support for the file system and - serial console PLUS about 2KB for the 'ls' command logic (including OS - support for opendir(), readdir(), closedir(), stat(), and probably other - things). - - STATUS: - 2015-6-10 - The nuttx.bin minnsh firmware file size: - - $ ls -l nuttx.bin - -rwxr-xr-x 1 alan alan 13859 Jun 10 08:54 nuttx.bin - - $ arm-none-eabi-size nuttx - text data bss dec hex filename - 12818 193 704 13715 3593 nuttx - - This is serial console output (and input) : - - NuttShell (NSH) - nsh> ls /dev - nsh: ls: command not found - - No filesystem, no "ls" command :-) - - nsh> ? - help usage: help [-v] [] - - ? exec free mb mw xd - echo exit help mh ps - nsh> free - total used free largest - Mem: 6464 1816 4648 4648 - - nsh> echo "NuttX is magic!" - NuttX is magic! - nsh> - - Replace NSH with apps/examples/hello: - - $ ls -l nuttx.bin - -rwxr-xr-x 1 alan alan 9318 Jun 10 09:02 nuttx.bin - - $ arm-none-eabi-size nuttx - text data bss dec hex filename - 8277 193 704 9174 23d6 nuttx - - Some additional commits from Alan reduce this FLASH size by - about another kilobyte. That changes: (1) disable stack - dumping on assertions,and (2) make some FLASH data structures - smaller. - - Almost 2Kb of the remaining size was due to some arithmetic - "long long" (64 bits) operations drawn from libgcc.a. - Alan changed vsprintf to make "long long" support optional. - This change reduced the NuttX kernel to less than 8KiB! - nsh: --- diff --git a/configs/lpcxpresso-lpc1115/minnsh/Make.defs b/configs/lpcxpresso-lpc1115/minnsh/Make.defs deleted file mode 100644 index 5024dbe9ca..0000000000 --- a/configs/lpcxpresso-lpc1115/minnsh/Make.defs +++ /dev/null @@ -1,123 +0,0 @@ -############################################################################ -# configs/lpcxpresso-lpc1115/minnsh/Make.defs -# -# Copyright (C) 2015 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk -include ${TOPDIR}/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = ld.script - -ifeq ($(WINTOOL),y) - # Windows-native toolchains - ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" - ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" - ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" -else - # Linux/Cygwin-native toolchain - ARCHINCLUDES = -I. -isystem $(TOPDIR)/include - ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx - ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) -endif - -CC = $(CROSSDEV)gcc -CXX = $(CROSSDEV)g++ -CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld -AR = $(ARCROSSDEV)ar rcs -NM = $(ARCROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} -ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION = -g -endif - -ifneq ($(CONFIG_DEBUG_NOOPT),y) - ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer -endif - -ARCHCFLAGS = -fno-builtin -ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -ARCHWARNINGSXX = -Wall -Wshadow -Wundef -ARCHDEFINES = -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -AFLAGS = $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -ASMEXT = .S -OBJEXT = .o -LIBEXT = .a -EXEEXT = - -ifneq ($(CROSSDEV),arm-nuttx-elf-) - LDFLAGS += -nostartfiles -nodefaultlibs -endif -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - LDFLAGS += -g -endif - - -HOSTCC = gcc -HOSTINCLUDES = -I. -HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe -HOSTLDFLAGS = -ifeq ($(CONFIG_HOST_WINDOWS),y) - HOSTEXEEXT = .exe -else - HOSTEXEEXT = -endif - -ifeq ($(WINTOOL),y) - # Windows-native host tools - DIRLINK = $(TOPDIR)/tools/copydir.sh - DIRUNLINK = $(TOPDIR)/tools/unlink.sh - MKDEP = $(TOPDIR)/tools/mkwindeps.sh -else - # Linux/Cygwin-native host tools - MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) -endif diff --git a/configs/lpcxpresso-lpc1115/minnsh/defconfig b/configs/lpcxpresso-lpc1115/minnsh/defconfig deleted file mode 100644 index 8480de14cb..0000000000 --- a/configs/lpcxpresso-lpc1115/minnsh/defconfig +++ /dev/null @@ -1,767 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Nuttx/ Configuration -# - -# -# Build Setup -# -# CONFIG_EXPERIMENTAL is not set -CONFIG_DEFAULT_SMALL=y -CONFIG_HOST_LINUX=y -# CONFIG_HOST_OSX is not set -# CONFIG_HOST_WINDOWS is not set -# CONFIG_HOST_OTHER is not set - -# -# Build Configuration -# -# CONFIG_APPS_DIR="../apps" -CONFIG_BUILD_FLAT=y -# CONFIG_BUILD_2PASS is not set - -# -# Binary Output Formats -# -# CONFIG_RRLOAD_BINARY is not set -# CONFIG_INTELHEX_BINARY is not set -# CONFIG_MOTOROLA_SREC is not set -CONFIG_RAW_BINARY=y -# CONFIG_UBOOT_UIMAGE is not set - -# -# Customize Header Files -# -# CONFIG_ARCH_STDINT_H is not set -# CONFIG_ARCH_STDBOOL_H is not set -# CONFIG_ARCH_MATH_H is not set -# CONFIG_ARCH_FLOAT_H is not set -# CONFIG_ARCH_STDARG_H is not set -# CONFIG_ARCH_DEBUG_H is not set - -# -# Debug Options -# -# CONFIG_DEBUG_ALERT is not set -# CONFIG_DEBUG_FEATURES is not set -CONFIG_ARCH_HAVE_STACKCHECK=y -# CONFIG_STACK_COLORATION is not set -# CONFIG_ARCH_HAVE_HEAPCHECK is not set -# CONFIG_DEBUG_SYMBOLS is not set -CONFIG_ARCH_HAVE_CUSTOMOPT=y -# CONFIG_DEBUG_NOOPT is not set -# CONFIG_DEBUG_CUSTOMOPT is not set -CONFIG_DEBUG_FULLOPT=y - -# -# System Type -# -CONFIG_ARCH_ARM=y -# CONFIG_ARCH_AVR is not set -# CONFIG_ARCH_HC is not set -# CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_SIM is not set -# CONFIG_ARCH_X86 is not set -# CONFIG_ARCH_Z16 is not set -# CONFIG_ARCH_Z80 is not set -CONFIG_ARCH="arm" - -# -# ARM Options -# -# CONFIG_ARCH_CHIP_A1X is not set -# CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set -# CONFIG_ARCH_CHIP_DM320 is not set -# CONFIG_ARCH_CHIP_EFM32 is not set -# CONFIG_ARCH_CHIP_IMX1 is not set -# CONFIG_ARCH_CHIP_IMX6 is not set -# CONFIG_ARCH_CHIP_KINETIS is not set -# CONFIG_ARCH_CHIP_KL is not set -# CONFIG_ARCH_CHIP_LM is not set -# CONFIG_ARCH_CHIP_TIVA is not set -CONFIG_ARCH_CHIP_LPC11XX=y -# CONFIG_ARCH_CHIP_LPC17XX is not set -# CONFIG_ARCH_CHIP_LPC214X is not set -# CONFIG_ARCH_CHIP_LPC2378 is not set -# CONFIG_ARCH_CHIP_LPC31XX is not set -# CONFIG_ARCH_CHIP_LPC43XX is not set -# CONFIG_ARCH_CHIP_NUC1XX is not set -# CONFIG_ARCH_CHIP_SAMA5 is not set -# CONFIG_ARCH_CHIP_SAMD is not set -# CONFIG_ARCH_CHIP_SAML is not set -# CONFIG_ARCH_CHIP_SAM34 is not set -# CONFIG_ARCH_CHIP_SAMV7 is not set -# CONFIG_ARCH_CHIP_STM32 is not set -# CONFIG_ARCH_CHIP_STM32F7 is not set -# CONFIG_ARCH_CHIP_STM32L4 is not set -# CONFIG_ARCH_CHIP_STR71X is not set -# CONFIG_ARCH_CHIP_TMS570 is not set -# CONFIG_ARCH_CHIP_MOXART is not set -# CONFIG_ARCH_ARM7TDMI is not set -# CONFIG_ARCH_ARM926EJS is not set -# CONFIG_ARCH_ARM920T is not set -CONFIG_ARCH_CORTEXM0=y -# CONFIG_ARCH_CORTEXM3 is not set -# CONFIG_ARCH_CORTEXM4 is not set -# CONFIG_ARCH_CORTEXM7 is not set -# CONFIG_ARCH_CORTEXA5 is not set -# CONFIG_ARCH_CORTEXA8 is not set -# CONFIG_ARCH_CORTEXA9 is not set -# CONFIG_ARCH_CORTEXR4 is not set -# CONFIG_ARCH_CORTEXR4F is not set -# CONFIG_ARCH_CORTEXR5 is not set -# CONFIG_ARCH_CORTEX5F is not set -# CONFIG_ARCH_CORTEXR7 is not set -# CONFIG_ARCH_CORTEXR7F is not set -CONFIG_ARCH_FAMILY="armv6-m" -CONFIG_ARCH_CHIP="lpc11xx" -# CONFIG_ARM_TOOLCHAIN_IAR is not set -# CONFIG_ARM_TOOLCHAIN_GNU is not set -CONFIG_ARCH_HAVE_CMNVECTOR=y -# CONFIG_ARMV7M_CMNVECTOR is not set -# CONFIG_ARMV7M_LAZYFPU is not set -# CONFIG_ARCH_HAVE_FPU is not set -# CONFIG_ARCH_HAVE_DPFPU is not set -# CONFIG_ARCH_HAVE_TRUSTZONE is not set -# CONFIG_ARM_HAVE_MPU_UNIFIED is not set - -# -# ARMV6M Configuration Options -# -# CONFIG_ARMV6M_TOOLCHAIN_BUILDROOT is not set -# CONFIG_ARMV6M_TOOLCHAIN_CODEREDL is not set -# CONFIG_ARMV6M_TOOLCHAIN_CODESOURCERYL is not set -CONFIG_ARMV6M_TOOLCHAIN_GNU_EABIL=y -# CONFIG_LPC11_GPIOIRQ is not set - -# -# LPC11xx Configuration Options -# -# CONFIG_ARCH_CHIP_LPC1114 is not set -CONFIG_ARCH_CHIP_LPC1115=y -CONFIG_ARCH_FAMILY_LPC111X=y - -# -# LPC11xx Peripheral Support -# -CONFIG_LPC11_INTRCOSC=y -# CONFIG_LPC11_MAINOSC is not set -CONFIG_LPC11_SYSTICK_CORECLK=y -# CONFIG_LPC11_SYSTICK_CORECLK_DIV16 is not set -CONFIG_LPC11_PLL=y -CONFIG_LPC11_UART0=y -# CONFIG_LPC11_CAN0 is not set -# CONFIG_LPC11_SPI is not set -# CONFIG_LPC11_SSP0 is not set -# CONFIG_LPC11_SSP1 is not set -# CONFIG_LPC11_I2C0 is not set -# CONFIG_LPC11_TMR0 is not set -# CONFIG_LPC11_TMR1 is not set -# CONFIG_LPC11_WDT is not set -# CONFIG_LPC11_ADC is not set -# CONFIG_LPC11_FLASH is not set - -# -# Serial driver options -# -# CONFIG_SERIAL_TERMIOS is not set - -# -# Architecture Options -# -# CONFIG_ARCH_NOINTC is not set -# CONFIG_ARCH_VECNOTIRQ is not set -# CONFIG_ARCH_DMA is not set -CONFIG_ARCH_HAVE_IRQPRIO=y -# CONFIG_ARCH_L2CACHE is not set -# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set -# CONFIG_ARCH_HAVE_ADDRENV is not set -# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set -# CONFIG_ARCH_HAVE_MULTICPU is not set -CONFIG_ARCH_HAVE_VFORK=y -# CONFIG_ARCH_HAVE_MMU is not set -# CONFIG_ARCH_HAVE_MPU is not set -# CONFIG_ARCH_NAND_HWECC is not set -# CONFIG_ARCH_HAVE_EXTCLK is not set -# CONFIG_ARCH_HAVE_POWEROFF is not set -CONFIG_ARCH_HAVE_RESET=y -# CONFIG_ARCH_IRQPRIO is not set -# CONFIG_ARCH_STACKDUMP is not set -# CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_IDLE_CUSTOM is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set -# CONFIG_ARCH_HAVE_RAMVECTORS is not set - -# -# Board Settings -# -CONFIG_BOARD_LOOPSPERMSEC=2988 -# CONFIG_ARCH_CALIBRATION is not set - -# -# Interrupt options -# -CONFIG_ARCH_HAVE_INTERRUPTSTACK=y -CONFIG_ARCH_INTERRUPTSTACK=0 -# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set - -# -# Boot options -# -# CONFIG_BOOT_RUNFROMEXTSRAM is not set -CONFIG_BOOT_RUNFROMFLASH=y -# CONFIG_BOOT_RUNFROMISRAM is not set -# CONFIG_BOOT_RUNFROMSDRAM is not set -# CONFIG_BOOT_COPYTORAM is not set - -# -# Boot Memory Configuration -# -CONFIG_RAM_START=0x10000000 -CONFIG_RAM_SIZE=8192 -# CONFIG_ARCH_HAVE_SDRAM is not set - -# -# Board Selection -# -CONFIG_ARCH_BOARD_LPCXPRESSO_LPC1115=y -# CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD="lpcxpresso-lpc1115" - -# -# Common Board Options -# -CONFIG_ARCH_HAVE_LEDS=y -CONFIG_ARCH_LEDS=y -CONFIG_NSH_MMCSDMINOR=0 - -# -# Board-Specific Options -# -# CONFIG_LIB_BOARDCTL is not set - -# -# RTOS Features -# -CONFIG_DISABLE_OS_API=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_DISABLE_SIGNALS=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_ENVIRON=y - -# -# Clocks and Timers -# -CONFIG_USEC_PER_TICK=10000 -# CONFIG_SYSTEM_TIME64 is not set -# CONFIG_CLOCK_MONOTONIC is not set -# CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2013 -CONFIG_START_MONTH=2 -CONFIG_START_DAY=26 -CONFIG_MAX_WDOGPARMS=2 -CONFIG_PREALLOC_WDOGS=4 -CONFIG_WDOG_INTRESERVE=0 -CONFIG_PREALLOC_TIMERS=0 - -# -# Tasks and Scheduling -# -# CONFIG_INIT_NONE is not set -CONFIG_INIT_ENTRYPOINT=y -# CONFIG_INIT_FILEPATH is not set -CONFIG_USER_ENTRYPOINT="nsh_main" -CONFIG_RR_INTERVAL=0 -# CONFIG_SCHED_SPORADIC is not set -CONFIG_TASK_NAME_SIZE=0 -CONFIG_MAX_TASKS=4 -# CONFIG_SCHED_HAVE_PARENT is not set -# CONFIG_SCHED_WAITPID is not set - -# -# Performance Monitoring -# -# CONFIG_SCHED_CPULOAD is not set -# CONFIG_SCHED_INSTRUMENTATION is not set - -# -# Files and I/O -# -# CONFIG_DEV_CONSOLE is not set -CONFIG_FDCLONE_DISABLE=y -# CONFIG_FDCLONE_STDIO is not set -CONFIG_SDCLONE_DISABLE=y -CONFIG_NFILE_DESCRIPTORS=0 -CONFIG_NFILE_STREAMS=0 -CONFIG_NAME_MAX=32 -# CONFIG_PRIORITY_INHERITANCE is not set - -# -# RTOS hooks -# -# CONFIG_BOARD_INITIALIZE is not set -# CONFIG_SCHED_STARTHOOK is not set -# CONFIG_SCHED_ATEXIT is not set -# CONFIG_SCHED_ONEXIT is not set -# CONFIG_MODULE is not set - -# -# Work queue support -# - -# -# Stack and heap information -# -CONFIG_IDLETHREAD_STACKSIZE=1024 -CONFIG_USERMAIN_STACKSIZE=1536 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=1536 -# CONFIG_LIB_SYSCALL is not set - -# -# Device Drivers -# -CONFIG_DISABLE_POLL=y -# CONFIG_DEV_NULL is not set -# CONFIG_DEV_ZERO is not set -# CONFIG_DEV_LOOP is not set - -# -# Buffering -# -# CONFIG_DRVR_WRITEBUFFER is not set -# CONFIG_DRVR_READAHEAD is not set -# CONFIG_RAMDISK is not set -# CONFIG_CAN is not set -# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set -# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set -# CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set -# CONFIG_I2C is not set -# CONFIG_SPI is not set -# CONFIG_I2S is not set - -# -# Timer Driver Support -# -# CONFIG_TIMER is not set -# CONFIG_RTC is not set -# CONFIG_WATCHDOG is not set -# CONFIG_ANALOG is not set -# CONFIG_AUDIO_DEVICES is not set -# CONFIG_VIDEO_DEVICES is not set -# CONFIG_BCH is not set -# CONFIG_INPUT is not set -# CONFIG_IOEXPANDER is not set - -# -# LCD Driver Support -# -# CONFIG_LCD is not set -# CONFIG_SLCD is not set - -# -# LED Support -# -# CONFIG_USERLED is not set -# CONFIG_RGBLED is not set -# CONFIG_PCA9635PW is not set -# CONFIG_NCP5623C is not set -# CONFIG_MMCSD is not set -# CONFIG_MODEM is not set -# CONFIG_MTD is not set -# CONFIG_EEPROM is not set -# CONFIG_PIPES is not set -# CONFIG_PM is not set -# CONFIG_POWER is not set -# CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set -CONFIG_SERIAL=y -# CONFIG_SERIAL_REMOVABLE is not set -CONFIG_SERIAL_CONSOLE=y -# CONFIG_16550_UART is not set -# CONFIG_UART_SERIALDRIVER is not set -CONFIG_UART0_SERIALDRIVER=y -# CONFIG_UART1_SERIALDRIVER is not set -# CONFIG_UART2_SERIALDRIVER is not set -# CONFIG_UART3_SERIALDRIVER is not set -# CONFIG_UART4_SERIALDRIVER is not set -# CONFIG_UART5_SERIALDRIVER is not set -# CONFIG_UART6_SERIALDRIVER is not set -# CONFIG_UART7_SERIALDRIVER is not set -# CONFIG_UART8_SERIALDRIVER is not set -# CONFIG_SCI0_SERIALDRIVER is not set -# CONFIG_SCI1_SERIALDRIVER is not set -# CONFIG_USART0_SERIALDRIVER is not set -# CONFIG_USART1_SERIALDRIVER is not set -# CONFIG_USART2_SERIALDRIVER is not set -# CONFIG_USART3_SERIALDRIVER is not set -# CONFIG_USART4_SERIALDRIVER is not set -# CONFIG_USART5_SERIALDRIVER is not set -# CONFIG_USART6_SERIALDRIVER is not set -# CONFIG_USART7_SERIALDRIVER is not set -# CONFIG_USART8_SERIALDRIVER is not set -# CONFIG_OTHER_UART_SERIALDRIVER is not set -CONFIG_MCU_SERIAL=y -# CONFIG_STANDARD_SERIAL is not set -# CONFIG_SERIAL_IFLOWCONTROL is not set -# CONFIG_SERIAL_OFLOWCONTROL is not set -# CONFIG_SERIAL_DMA is not set -# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set -CONFIG_UART0_SERIAL_CONSOLE=y -# CONFIG_OTHER_SERIAL_CONSOLE is not set -# CONFIG_NO_SERIAL_CONSOLE is not set - -# -# UART0 Configuration -# -CONFIG_UART0_RXBUFSIZE=64 -CONFIG_UART0_TXBUFSIZE=64 -CONFIG_UART0_BAUD=115200 -CONFIG_UART0_BITS=8 -CONFIG_UART0_PARITY=0 -CONFIG_UART0_2STOP=0 -# CONFIG_UART0_IFLOWCONTROL is not set -# CONFIG_UART0_OFLOWCONTROL is not set -# CONFIG_UART0_DMA is not set -# CONFIG_USBDEV is not set -# CONFIG_USBHOST is not set -# CONFIG_DRIVERS_WIRELESS is not set - -# -# System Logging -# -# CONFIG_ARCH_SYSLOG is not set -# CONFIG_RAMLOG is not set -# CONFIG_SYSLOG_INTBUFFER is not set -# CONFIG_SYSLOG_TIMESTAMP is not set -# CONFIG_SYSLOG_SERIAL_CONSOLE is not set -# CONFIG_SYSLOG_CHAR is not set -CONFIG_SYSLOG_NONE=y -# CONFIG_SYSLOG_FILE is not set - -# -# Networking Support -# -# CONFIG_ARCH_HAVE_NET is not set -# CONFIG_ARCH_HAVE_PHY is not set -# CONFIG_NET is not set - -# -# Crypto API -# -# CONFIG_CRYPTO is not set - -# -# File Systems -# - -# -# File system configuration -# -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y -# CONFIG_FS_READABLE is not set -# CONFIG_FS_WRITABLE is not set -# CONFIG_FS_NAMED_SEMAPHORES is not set -# CONFIG_FS_RAMMAP is not set -# CONFIG_FS_PROCFS is not set -# CONFIG_FS_UNIONFS is not set - -# -# Graphics Support -# -# CONFIG_NX is not set - -# -# Memory Management -# -CONFIG_MM_SMALL=y -CONFIG_MM_REGIONS=1 -# CONFIG_ARCH_HAVE_HEAP2 is not set -# CONFIG_GRAN is not set - -# -# Audio Support -# -# CONFIG_AUDIO is not set - -# -# Wireless Support -# - -# -# Binary Loader -# -# CONFIG_BINFMT_DISABLE is not set -# CONFIG_NXFLAT is not set -# CONFIG_ELF is not set -# CONFIG_BUILTIN is not set -# CONFIG_PIC is not set -# CONFIG_SYMTAB_ORDEREDBYNAME is not set - -# -# Library Routines -# - -# -# Standard C Library Options -# -CONFIG_STDIO_BUFFER_SIZE=0 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=0 -# CONFIG_LIBM is not set -CONFIG_NOPRINTF_FIELDWIDTH=y -# CONFIG_LIBC_FLOATINGPOINT is not set -# CONFIG_LIBC_LONG_LONG is not set -# CONFIG_LIBC_IOCTL_VARIADIC is not set -CONFIG_LIB_RAND_ORDER=1 -# CONFIG_EOL_IS_CR is not set -# CONFIG_EOL_IS_LF is not set -# CONFIG_EOL_IS_BOTH_CRLF is not set -CONFIG_EOL_IS_EITHER_CRLF=y -# CONFIG_LIBC_EXECFUNCS is not set -CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 -# CONFIG_LIBC_STRERROR is not set -# CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_ARCH_LOWPUTC=y -# CONFIG_TIME_EXTENDED is not set -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set -# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set -CONFIG_ARCH_HAVE_TLS=y -# CONFIG_TLS is not set -# CONFIG_LIBC_NETDB is not set - -# -# Non-standard Library Support -# -# CONFIG_LIB_CRC64_FAST is not set -# CONFIG_LIB_KBDCODEC is not set -# CONFIG_LIB_SLCDCODEC is not set - -# -# Basic CXX Support -# -# CONFIG_C99_BOOL8 is not set -# CONFIG_HAVE_CXX is not set - -# -# Application Configuration -# - -# -# CAN Utilities -# - -# -# Examples -# -# CONFIG_EXAMPLES_CHAT is not set -# CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set -# CONFIG_EXAMPLES_DHCPD is not set -# CONFIG_EXAMPLES_ELF is not set -# CONFIG_EXAMPLES_FTPC is not set -# CONFIG_EXAMPLES_FTPD is not set -# CONFIG_EXAMPLES_HELLO is not set -# CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_IGMP is not set -# CONFIG_EXAMPLES_JSON is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set -# CONFIG_EXAMPLES_MEDIA is not set -# CONFIG_EXAMPLES_MM is not set -# CONFIG_EXAMPLES_MODBUS is not set -# CONFIG_EXAMPLES_MOUNT is not set -# CONFIG_EXAMPLES_NRF24L01TERM is not set -CONFIG_EXAMPLES_NSH=y -# CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXFFS is not set -# CONFIG_EXAMPLES_NXHELLO is not set -# CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NXLINES is not set -# CONFIG_EXAMPLES_NXTERM is not set -# CONFIG_EXAMPLES_NXTEXT is not set -# CONFIG_EXAMPLES_OSTEST is not set -# CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POLL is not set -# CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_PPPD is not set -# CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_SENDMAIL is not set -# CONFIG_EXAMPLES_SERIALBLASTER is not set -# CONFIG_EXAMPLES_SERIALRX is not set -# CONFIG_EXAMPLES_SERLOOP is not set -# CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART is not set -# CONFIG_EXAMPLES_SMP is not set -# CONFIG_EXAMPLES_TCPECHO is not set -# CONFIG_EXAMPLES_TELNETD is not set -# CONFIG_EXAMPLES_TIFF is not set -# CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_USBTERM is not set -# CONFIG_EXAMPLES_WATCHDOG is not set -# CONFIG_EXAMPLES_WEBSERVER is not set - -# -# File System Utilities -# -# CONFIG_FSUTILS_INIFILE is not set - -# -# GPS Utilities -# -# CONFIG_GPSUTILS_MINMEA_LIB is not set - -# -# Graphics Support -# -# CONFIG_TIFF is not set -# CONFIG_GRAPHICS_TRAVELER is not set - -# -# Interpreters -# -# CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_MICROPYTHON is not set -# CONFIG_INTERPRETERS_PCODE is not set - -# -# FreeModBus -# -# CONFIG_MODBUS is not set - -# -# Network Utilities -# -# CONFIG_NETUTILS_CODECS is not set -# CONFIG_NETUTILS_ESP8266 is not set -# CONFIG_NETUTILS_FTPC is not set -# CONFIG_NETUTILS_JSON is not set -# CONFIG_NETUTILS_SMTP is not set - -# -# NSH Library -# -CONFIG_NSH_LIBRARY=y -# CONFIG_NSH_MOTD is not set - -# -# Command Line Configuration -# -CONFIG_NSH_READLINE=y -# CONFIG_NSH_CLE is not set -CONFIG_NSH_LINELEN=80 -CONFIG_NSH_DISABLE_SEMICOLON=y -CONFIG_NSH_MAXARGUMENTS=6 -# CONFIG_NSH_ARGCAT is not set -CONFIG_NSH_NESTDEPTH=3 -# CONFIG_NSH_DISABLEBG is not set - -# -# Disable Individual commands -# -CONFIG_NSH_DISABLE_ADDROUTE=y -CONFIG_NSH_DISABLE_BASENAME=y -# CONFIG_NSH_DISABLE_CAT is not set -CONFIG_NSH_DISABLE_CD=y -CONFIG_NSH_DISABLE_CP=y -# CONFIG_NSH_DISABLE_CMP is not set -CONFIG_NSH_DISABLE_DATE=y -CONFIG_NSH_DISABLE_DD=y -CONFIG_NSH_DISABLE_DF=y -CONFIG_NSH_DISABLE_DELROUTE=y -CONFIG_NSH_DISABLE_DIRNAME=y -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_FREE is not set -CONFIG_NSH_DISABLE_GET=y -# CONFIG_NSH_DISABLE_HELP is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -CONFIG_NSH_DISABLE_IFCONFIG=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -# CONFIG_NSH_DISABLE_KILL is not set -CONFIG_NSH_DISABLE_LOSETUP=y -CONFIG_NSH_DISABLE_LOSMART=y -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_MB is not set -CONFIG_NSH_DISABLE_MKDIR=y -# CONFIG_NSH_DISABLE_MKFIFO is not set -CONFIG_NSH_DISABLE_MKRD=y -# CONFIG_NSH_DISABLE_MH is not set -CONFIG_NSH_DISABLE_MOUNT=y -CONFIG_NSH_DISABLE_MV=y -# CONFIG_NSH_DISABLE_MW is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_NSH_DISABLE_PUT=y -# CONFIG_NSH_DISABLE_PWD is not set -CONFIG_NSH_DISABLE_RM=y -CONFIG_NSH_DISABLE_RMDIR=y -# CONFIG_NSH_DISABLE_SET is not set -# CONFIG_NSH_DISABLE_SH is not set -# CONFIG_NSH_DISABLE_SLEEP is not set -CONFIG_NSH_DISABLE_TIME=y -# CONFIG_NSH_DISABLE_TEST is not set -CONFIG_NSH_DISABLE_UMOUNT=y -CONFIG_NSH_DISABLE_UNAME=y -# CONFIG_NSH_DISABLE_UNSET is not set -# CONFIG_NSH_DISABLE_USLEEP is not set -CONFIG_NSH_DISABLE_WGET=y -# CONFIG_NSH_DISABLE_XD is not set - -# -# Configure Command Options -# -CONFIG_NSH_CODECS_BUFSIZE=128 -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_NSH_FILEIOSIZE=64 - -# -# Scripting Support -# -CONFIG_NSH_DISABLESCRIPT=y - -# -# Console Configuration -# -CONFIG_NSH_CONSOLE=y -# CONFIG_NSH_ALTCONDEV is not set -# CONFIG_NSH_ARCHINIT is not set -# CONFIG_NSH_LOGIN is not set -# CONFIG_NSH_CONSOLE_LOGIN is not set - -# -# NxWidgets/NxWM -# - -# -# Platform-specific Support -# -# CONFIG_PLATFORM_CONFIGDATA is not set - -# -# System Libraries and NSH Add-Ons -# -# CONFIG_SYSTEM_CLE is not set -# CONFIG_SYSTEM_CUTERM is not set -# CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set -# CONFIG_SYSTEM_HEXED is not set -# CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_RAMTEST is not set -CONFIG_READLINE_HAVE_EXTMATCH=y -CONFIG_SYSTEM_READLINE=y -CONFIG_READLINE_ECHO=y -# CONFIG_READLINE_TABCOMPLETION is not set -# CONFIG_READLINE_CMD_HISTORY is not set -# CONFIG_SYSTEM_SUDOKU is not set -# CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_VI is not set -# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/lpcxpresso-lpc1115/minnsh/setenv.sh b/configs/lpcxpresso-lpc1115/minnsh/setenv.sh deleted file mode 100755 index f47c395c1c..0000000000 --- a/configs/lpcxpresso-lpc1115/minnsh/setenv.sh +++ /dev/null @@ -1,72 +0,0 @@ -#!/bin/bash -# configs/lpcxpresso-lpc1115/minnsh/setenv.sh -# -# Copyright (C) 2015 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if [ "$(basename $0)" = "setenv.sh" ] ; then - echo "You must source this script, not run it!" 1>&2 - exit 1 -fi - -if [ -z "${PATH_ORIG}" ]; then export PATH_ORIG="${PATH}"; fi - -WD=`pwd` - -# This is the Cygwin path to the location where I installed the CodeSourcery -# toolchain under windows. You will also have to edit this if you install -# the CodeSourcery toolchain in any other location -#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" -#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" -# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" - -# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" -# You can this free toolchain here https://launchpad.net/gcc-arm-embedded -export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" - -# This is the path to the location where I installed the devkitARM toolchain -# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/ -#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin" - -# This is the default install location for Code Red on Linux -# export TOOLCHAIN_BIN="/usr/local/LPCXpresso/tools/bin" - -# This is the Cygwin path to the LPCXpresso 3.6 install location under Windows -#export TOOLCHAIN_BIN="/cygdrive/c/nxp/lpcxpresso_3.6/Tools/bin" - -# This is the Cygwin path to the location where I build the buildroot -# toolchain. -# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" - -# Add the path to the toolchain to the PATH varialble -export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" - -echo "PATH : ${PATH}" diff --git a/configs/stm3220g-eval/ide/nsh/iar/libc.ewp b/configs/stm3220g-eval/ide/nsh/iar/libc.ewp index db57f8d8b9..15e9c88df4 100644 --- a/configs/stm3220g-eval/ide/nsh/iar/libc.ewp +++ b/configs/stm3220g-eval/ide/nsh/iar/libc.ewp @@ -2313,9 +2313,6 @@ $PROJ_DIR$/../../../../../libc/stdio/lib_memsostream.c - - $PROJ_DIR$/../../../../../libc/stdio/lib_lowinstream.c - $PROJ_DIR$/../../../../../libc/stdio/lib_lowoutstream.c diff --git a/configs/stm3220g-eval/ide/nsh/uvision/libc.uvproj b/configs/stm3220g-eval/ide/nsh/uvision/libc.uvproj index 31ee6e86a5..90ecb7c9c1 100644 --- a/configs/stm3220g-eval/ide/nsh/uvision/libc.uvproj +++ b/configs/stm3220g-eval/ide/nsh/uvision/libc.uvproj @@ -953,11 +953,6 @@ 1 ../../../../../libc/stdio/lib_memsostream.c - - lib_lowinstream.c - 1 - ../../../../../libc/stdio/lib_lowinstream.c - lib_lowoutstream.c 1 diff --git a/configs/stm32f103-minimum/README.txt b/configs/stm32f103-minimum/README.txt index 112182b032..fd4c30987f 100644 --- a/configs/stm32f103-minimum/README.txt +++ b/configs/stm32f103-minimum/README.txt @@ -421,140 +421,6 @@ instead of configure.sh: Where is one of the following: - minnsh: - ------ - - This is a experiment to see just how small we can get a usable NSH - configuration. This configuration has far fewer features than the nsh - configuration but is also a fraction of the size. - - This minnsh configuration is a "proof-of-concept" and not very usable in - its current state. This configuration was created by disabling - everything possible INCLUDING file system support. Without file system - support, NuttX is pretty much crippled. Here are some of the - consequences of disabling the file system: - - - All features that depend on the file system are lost: device drivers, - mountpoints, message queues, named semaphores. - - - Without device drivers, you cannot interact with the RTOS using POSIX - interfaces. You would have to work with NuttX as with those other - tiny RTOSs: As a scheduler and a callable hardare abstraction layer - (HAL). - - - You cannot use any of the NuttX upper half device drivers since they - depend on the pseudo-file system and device nodes. You can, of - course, continue to use the lower half drivers either directly. Or, - perhaps, you could write some custom minnsh upper half drivers that - do not depend on a file system and expose a HAL interface. - - There is a special version of readline() the NSH uses when there is no - file system. It uses a special up_putc() to write data to the console - and a special function up_getc() to read data from the console. - - - The current up_getc() implementationsa are a kludge. They are - analogous to the up_putc() implementations: They directly poll the - hardware for serial availability, locking up all lower priority tasks - in the entire system while they poll. So a version of NSH that uses - up_getc() essentially blocks the system until a character is received. - - This, of course, could be fixed by creating a special, upper half - implementation of the interrupt-driven serial lower half (like - stm32_serial) that just supports single character console I/O - (perhaps called up_putc and up_getc?). The NSH could wait for serial - input without blocking the system. But then that would increase the - footprint too. - - So although the minnsh configurations are a good starting point for - making things small, they not are really very practical. Why might - you want a NuttX minnsh solution? Perhaps you have software that runs - on a family of chips including some very tiny MCUs. Then perhaps having - the RTOS compatibility would justify the loss of functionality? - - STATUS: - 2016-06-03: Using that config I got this: - - $ ls -l nuttx.bin - -rwxr-xr-x 1 alan alan 12543 Jun 3 17:58 nuttx.bin - - $ arm-none-eabi-size nuttx - text data bss dec hex filename - 12542 1 816 13359 342f nuttx - - And this is free command from NuttX shell: - - NuttShell (NSH) - nsh> free - total used free largest - Mem: 18624 2328 16296 16296 - nsh> - - 2016-06-07: As another experiment, I tried enabling just (1) the file - system, (2) the console device, and (3) the upper half serial driver in - the minnsh configuration. With these changes, NSH should behave better - and we preserve the device driver interface. I made the following - configuration changes: - - Enable the file system: - CONFIG_NFILE_DESCRIPTORS=5 - CONFIG_NFILE_STREAMS=5 - - Enable the console device: - CONFIG_DEV_CONSOLE=y - - Disable most new NSH commands. Some like 'ls' are really mandatory - with a file system: - CONFIG_NSH_DISABLE_xxx=y - - Enable the upper half serial driver: - CONFIG_SERIAL=y - CONFIG_STANDARD_SERIAL=y - - Enable the USART1 serial driver: - CONFIG_STM32_USART1=y - CONFIG_STM32_USART1_SERIALDRIVER=y - CONFIG_USART1_SERIAL_CONSOLE=y - - CONFIG_USART1_2STOP=0 - CONFIG_USART1_BAUD=115200 - CONFIG_USART1_BITS=8 - CONFIG_USART1_PARITY=0 - CONFIG_USART1_RXBUFSIZE=16 - CONFIG_USART1_TXBUFSIZE=16 - - The resulting code was bigger as expected: - - $ arm-none-eabi-size nuttx - text data bss dec hex filename - 19853 88 876 20817 5151 nuttx - - I am sure that other things that could be disabled were also drawn into - the build, so perhaps this could be reduced. This amounts to a size - increase of around 7KB. - - One major part of this size increase is due to the addition of the NSH - 'ls' command. Now, if I disable the 'ls' command, I get: - - $ arm-none-eabi-size nuttx - text data bss dec hex filename - 17804 80 864 18748 493c nuttx - - Or an increase of only 5.1 KB. This, of course, not only excludes the - 'ls' command logic, but also the things that were drawn into the link - when 'ls' was enabled: opendir(), readdir(), closedir(), stat(), and - probably other things. - - So I think we can say that the cost of the file system and true serial - console device was about 5 KB (primarily OS support) and the cost of - the NSH 'ls' command (including OS support) is about 2KB. - - 2016-06-21: Just checking the size after some big system changes: The - size of the base configuration has actually dropped by a few bytes: - - $ arm-none-eabi-size nuttx - text data bss dec hex filename - 12526 4 816 13346 3422 nuttx - nsh: --- Configures the NuttShell (nsh) located at apps/examples/nsh. This diff --git a/configs/stm32f103-minimum/minnsh/Make.defs b/configs/stm32f103-minimum/minnsh/Make.defs deleted file mode 100644 index 8d3d478305..0000000000 --- a/configs/stm32f103-minimum/minnsh/Make.defs +++ /dev/null @@ -1,113 +0,0 @@ -############################################################################ -# configs/stm32f103-minimum/nsh/Make.defs -# -# Copyright (C) 2016 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk -include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script - -ifeq ($(WINTOOL),y) - # Windows-native toolchains - DIRLINK = $(TOPDIR)/tools/copydir.sh - DIRUNLINK = $(TOPDIR)/tools/unlink.sh - MKDEP = $(TOPDIR)/tools/mkwindeps.sh - ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" - ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" - ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" -else - # Linux/Cygwin-native toolchain - MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) - ARCHINCLUDES = -I. -isystem $(TOPDIR)/include - ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx - ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) -endif - -CC = $(CROSSDEV)gcc -CXX = $(CROSSDEV)g++ -CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld -AR = $(CROSSDEV)ar rcs -NM = $(CROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} -ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION = -g -endif - -ifneq ($(CONFIG_DEBUG_NOOPT),y) - ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer -endif - -ARCHCFLAGS = -fno-builtin -ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -ARCHWARNINGSXX = -Wall -Wshadow -Wundef -ARCHDEFINES = -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -AFLAGS = $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -ASMEXT = .S -OBJEXT = .o -LIBEXT = .a -EXEEXT = - -ifneq ($(CROSSDEV),arm-nuttx-elf-) - LDFLAGS += -nostartfiles -nodefaultlibs -endif -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - LDFLAGS += -g -endif - - -HOSTCC = gcc -HOSTINCLUDES = -I. -HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe -HOSTLDFLAGS = - diff --git a/configs/stm32f103-minimum/minnsh/defconfig b/configs/stm32f103-minimum/minnsh/defconfig deleted file mode 100644 index a150431a15..0000000000 --- a/configs/stm32f103-minimum/minnsh/defconfig +++ /dev/null @@ -1,1073 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Nuttx/ Configuration -# - -# -# Build Setup -# -# CONFIG_EXPERIMENTAL is not set -CONFIG_DEFAULT_SMALL=y -CONFIG_HOST_LINUX=y -# CONFIG_HOST_OSX is not set -# CONFIG_HOST_WINDOWS is not set -# CONFIG_HOST_OTHER is not set - -# -# Build Configuration -# -# CONFIG_APPS_DIR="../apps" -CONFIG_BUILD_FLAT=y -# CONFIG_BUILD_2PASS is not set - -# -# Binary Output Formats -# -# CONFIG_RRLOAD_BINARY is not set -# CONFIG_INTELHEX_BINARY is not set -# CONFIG_MOTOROLA_SREC is not set -CONFIG_RAW_BINARY=y -# CONFIG_UBOOT_UIMAGE is not set - -# -# Customize Header Files -# -# CONFIG_ARCH_STDINT_H is not set -# CONFIG_ARCH_STDBOOL_H is not set -# CONFIG_ARCH_MATH_H is not set -# CONFIG_ARCH_FLOAT_H is not set -# CONFIG_ARCH_STDARG_H is not set -# CONFIG_ARCH_DEBUG_H is not set - -# -# Debug Options -# -# CONFIG_DEBUG_ALERT is not set -# CONFIG_DEBUG_FEATURES is not set -CONFIG_ARCH_HAVE_STACKCHECK=y -# CONFIG_STACK_COLORATION is not set -CONFIG_ARCH_HAVE_HEAPCHECK=y -# CONFIG_HEAP_COLORATION is not set -# CONFIG_DEBUG_SYMBOLS is not set -CONFIG_ARCH_HAVE_CUSTOMOPT=y -# CONFIG_DEBUG_NOOPT is not set -# CONFIG_DEBUG_CUSTOMOPT is not set -CONFIG_DEBUG_FULLOPT=y - -# -# System Type -# -CONFIG_ARCH_ARM=y -# CONFIG_ARCH_AVR is not set -# CONFIG_ARCH_HC is not set -# CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_SIM is not set -# CONFIG_ARCH_X86 is not set -# CONFIG_ARCH_Z16 is not set -# CONFIG_ARCH_Z80 is not set -CONFIG_ARCH="arm" - -# -# ARM Options -# -# CONFIG_ARCH_CHIP_A1X is not set -# CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set -# CONFIG_ARCH_CHIP_DM320 is not set -# CONFIG_ARCH_CHIP_EFM32 is not set -# CONFIG_ARCH_CHIP_IMX1 is not set -# CONFIG_ARCH_CHIP_IMX6 is not set -# CONFIG_ARCH_CHIP_KINETIS is not set -# CONFIG_ARCH_CHIP_KL is not set -# CONFIG_ARCH_CHIP_LM is not set -# CONFIG_ARCH_CHIP_TIVA is not set -# CONFIG_ARCH_CHIP_LPC11XX is not set -# CONFIG_ARCH_CHIP_LPC17XX is not set -# CONFIG_ARCH_CHIP_LPC214X is not set -# CONFIG_ARCH_CHIP_LPC2378 is not set -# CONFIG_ARCH_CHIP_LPC31XX is not set -# CONFIG_ARCH_CHIP_LPC43XX is not set -# CONFIG_ARCH_CHIP_NUC1XX is not set -# CONFIG_ARCH_CHIP_SAMA5 is not set -# CONFIG_ARCH_CHIP_SAMD is not set -# CONFIG_ARCH_CHIP_SAML is not set -# CONFIG_ARCH_CHIP_SAM34 is not set -# CONFIG_ARCH_CHIP_SAMV7 is not set -CONFIG_ARCH_CHIP_STM32=y -# CONFIG_ARCH_CHIP_STM32F7 is not set -# CONFIG_ARCH_CHIP_STM32L4 is not set -# CONFIG_ARCH_CHIP_STR71X is not set -# CONFIG_ARCH_CHIP_TMS570 is not set -# CONFIG_ARCH_CHIP_MOXART is not set -# CONFIG_ARCH_ARM7TDMI is not set -# CONFIG_ARCH_ARM926EJS is not set -# CONFIG_ARCH_ARM920T is not set -# CONFIG_ARCH_CORTEXM0 is not set -CONFIG_ARCH_CORTEXM3=y -# CONFIG_ARCH_CORTEXM4 is not set -# CONFIG_ARCH_CORTEXM7 is not set -# CONFIG_ARCH_CORTEXA5 is not set -# CONFIG_ARCH_CORTEXA8 is not set -# CONFIG_ARCH_CORTEXA9 is not set -# CONFIG_ARCH_CORTEXR4 is not set -# CONFIG_ARCH_CORTEXR4F is not set -# CONFIG_ARCH_CORTEXR5 is not set -# CONFIG_ARCH_CORTEX5F is not set -# CONFIG_ARCH_CORTEXR7 is not set -# CONFIG_ARCH_CORTEXR7F is not set -CONFIG_ARCH_FAMILY="armv7-m" -CONFIG_ARCH_CHIP="stm32" -# CONFIG_ARM_TOOLCHAIN_IAR is not set -CONFIG_ARM_TOOLCHAIN_GNU=y -# CONFIG_ARMV7M_USEBASEPRI is not set -CONFIG_ARCH_HAVE_CMNVECTOR=y -# CONFIG_ARMV7M_CMNVECTOR is not set -# CONFIG_ARMV7M_LAZYFPU is not set -# CONFIG_ARCH_HAVE_FPU is not set -# CONFIG_ARCH_HAVE_DPFPU is not set -# CONFIG_ARCH_HAVE_TRUSTZONE is not set -CONFIG_ARM_HAVE_MPU_UNIFIED=y -# CONFIG_ARM_MPU is not set - -# -# ARMV7M Configuration Options -# -# CONFIG_ARMV7M_HAVE_ICACHE is not set -# CONFIG_ARMV7M_HAVE_DCACHE is not set -# CONFIG_ARMV7M_HAVE_ITCM is not set -# CONFIG_ARMV7M_HAVE_DTCM is not set -# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set -# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set -# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set -# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set -CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y -CONFIG_ARMV7M_HAVE_STACKCHECK=y -# CONFIG_ARMV7M_STACKCHECK is not set -# CONFIG_ARMV7M_ITMSYSLOG is not set -# CONFIG_SERIAL_TERMIOS is not set - -# -# STM32 Configuration Options -# -# CONFIG_ARCH_CHIP_STM32L151C6 is not set -# CONFIG_ARCH_CHIP_STM32L151C8 is not set -# CONFIG_ARCH_CHIP_STM32L151CB is not set -# CONFIG_ARCH_CHIP_STM32L151R6 is not set -# CONFIG_ARCH_CHIP_STM32L151R8 is not set -# CONFIG_ARCH_CHIP_STM32L151RB is not set -# CONFIG_ARCH_CHIP_STM32L151V6 is not set -# CONFIG_ARCH_CHIP_STM32L151V8 is not set -# CONFIG_ARCH_CHIP_STM32L151VB is not set -# CONFIG_ARCH_CHIP_STM32L152C6 is not set -# CONFIG_ARCH_CHIP_STM32L152C8 is not set -# CONFIG_ARCH_CHIP_STM32L152CB is not set -# CONFIG_ARCH_CHIP_STM32L152R6 is not set -# CONFIG_ARCH_CHIP_STM32L152R8 is not set -# CONFIG_ARCH_CHIP_STM32L152RB is not set -# CONFIG_ARCH_CHIP_STM32L152V6 is not set -# CONFIG_ARCH_CHIP_STM32L152V8 is not set -# CONFIG_ARCH_CHIP_STM32L152VB is not set -# CONFIG_ARCH_CHIP_STM32L162ZD is not set -# CONFIG_ARCH_CHIP_STM32L162VE is not set -# CONFIG_ARCH_CHIP_STM32F100C8 is not set -# CONFIG_ARCH_CHIP_STM32F100CB is not set -# CONFIG_ARCH_CHIP_STM32F100R8 is not set -# CONFIG_ARCH_CHIP_STM32F100RB is not set -# CONFIG_ARCH_CHIP_STM32F100RC is not set -# CONFIG_ARCH_CHIP_STM32F100RD is not set -# CONFIG_ARCH_CHIP_STM32F100RE is not set -# CONFIG_ARCH_CHIP_STM32F100V8 is not set -# CONFIG_ARCH_CHIP_STM32F100VB is not set -# CONFIG_ARCH_CHIP_STM32F100VC is not set -# CONFIG_ARCH_CHIP_STM32F100VD is not set -# CONFIG_ARCH_CHIP_STM32F100VE is not set -# CONFIG_ARCH_CHIP_STM32F102CB is not set -# CONFIG_ARCH_CHIP_STM32F103T8 is not set -# CONFIG_ARCH_CHIP_STM32F103TB is not set -# CONFIG_ARCH_CHIP_STM32F103C4 is not set -CONFIG_ARCH_CHIP_STM32F103C8=y -# CONFIG_ARCH_CHIP_STM32F103CB is not set -# CONFIG_ARCH_CHIP_STM32F103R8 is not set -# CONFIG_ARCH_CHIP_STM32F103RB is not set -# CONFIG_ARCH_CHIP_STM32F103RC is not set -# CONFIG_ARCH_CHIP_STM32F103RD is not set -# CONFIG_ARCH_CHIP_STM32F103RE is not set -# CONFIG_ARCH_CHIP_STM32F103RG is not set -# CONFIG_ARCH_CHIP_STM32F103V8 is not set -# CONFIG_ARCH_CHIP_STM32F103VB is not set -# CONFIG_ARCH_CHIP_STM32F103VC is not set -# CONFIG_ARCH_CHIP_STM32F103VE is not set -# CONFIG_ARCH_CHIP_STM32F103ZE is not set -# CONFIG_ARCH_CHIP_STM32F105VB is not set -# CONFIG_ARCH_CHIP_STM32F105RB is not set -# CONFIG_ARCH_CHIP_STM32F107VC is not set -# CONFIG_ARCH_CHIP_STM32F205RG is not set -# CONFIG_ARCH_CHIP_STM32F207IG is not set -# CONFIG_ARCH_CHIP_STM32F207ZE is not set -# CONFIG_ARCH_CHIP_STM32F302K6 is not set -# CONFIG_ARCH_CHIP_STM32F302K8 is not set -# CONFIG_ARCH_CHIP_STM32F302CB is not set -# CONFIG_ARCH_CHIP_STM32F302CC is not set -# CONFIG_ARCH_CHIP_STM32F302RB is not set -# CONFIG_ARCH_CHIP_STM32F302RC is not set -# CONFIG_ARCH_CHIP_STM32F302VB is not set -# CONFIG_ARCH_CHIP_STM32F302VC is not set -# CONFIG_ARCH_CHIP_STM32F303K6 is not set -# CONFIG_ARCH_CHIP_STM32F303K8 is not set -# CONFIG_ARCH_CHIP_STM32F303C6 is not set -# CONFIG_ARCH_CHIP_STM32F303C8 is not set -# CONFIG_ARCH_CHIP_STM32F303CB is not set -# CONFIG_ARCH_CHIP_STM32F303CC is not set -# CONFIG_ARCH_CHIP_STM32F303RB is not set -# CONFIG_ARCH_CHIP_STM32F303RC is not set -# CONFIG_ARCH_CHIP_STM32F303RD is not set -# CONFIG_ARCH_CHIP_STM32F303RE is not set -# CONFIG_ARCH_CHIP_STM32F303VB is not set -# CONFIG_ARCH_CHIP_STM32F303VC is not set -# CONFIG_ARCH_CHIP_STM32F372C8 is not set -# CONFIG_ARCH_CHIP_STM32F372R8 is not set -# CONFIG_ARCH_CHIP_STM32F372V8 is not set -# CONFIG_ARCH_CHIP_STM32F372CB is not set -# CONFIG_ARCH_CHIP_STM32F372RB is not set -# CONFIG_ARCH_CHIP_STM32F372VB is not set -# CONFIG_ARCH_CHIP_STM32F372CC is not set -# CONFIG_ARCH_CHIP_STM32F372RC is not set -# CONFIG_ARCH_CHIP_STM32F372VC is not set -# CONFIG_ARCH_CHIP_STM32F373C8 is not set -# CONFIG_ARCH_CHIP_STM32F373R8 is not set -# CONFIG_ARCH_CHIP_STM32F373V8 is not set -# CONFIG_ARCH_CHIP_STM32F373CB is not set -# CONFIG_ARCH_CHIP_STM32F373RB is not set -# CONFIG_ARCH_CHIP_STM32F373VB is not set -# CONFIG_ARCH_CHIP_STM32F373CC is not set -# CONFIG_ARCH_CHIP_STM32F373RC is not set -# CONFIG_ARCH_CHIP_STM32F373VC is not set -# CONFIG_ARCH_CHIP_STM32F401RE is not set -# CONFIG_ARCH_CHIP_STM32F411RE is not set -# CONFIG_ARCH_CHIP_STM32F411VE is not set -# CONFIG_ARCH_CHIP_STM32F405RG is not set -# CONFIG_ARCH_CHIP_STM32F405VG is not set -# CONFIG_ARCH_CHIP_STM32F405ZG is not set -# CONFIG_ARCH_CHIP_STM32F407VE is not set -# CONFIG_ARCH_CHIP_STM32F407VG is not set -# CONFIG_ARCH_CHIP_STM32F407ZE is not set -# CONFIG_ARCH_CHIP_STM32F407ZG is not set -# CONFIG_ARCH_CHIP_STM32F407IE is not set -# CONFIG_ARCH_CHIP_STM32F407IG is not set -# CONFIG_ARCH_CHIP_STM32F427V is not set -# CONFIG_ARCH_CHIP_STM32F427Z is not set -# CONFIG_ARCH_CHIP_STM32F427I is not set -# CONFIG_ARCH_CHIP_STM32F429V is not set -# CONFIG_ARCH_CHIP_STM32F429Z is not set -# CONFIG_ARCH_CHIP_STM32F429I is not set -# CONFIG_ARCH_CHIP_STM32F429B is not set -# CONFIG_ARCH_CHIP_STM32F429N is not set -# CONFIG_ARCH_CHIP_STM32F446M is not set -# CONFIG_ARCH_CHIP_STM32F446R is not set -# CONFIG_ARCH_CHIP_STM32F446V is not set -# CONFIG_ARCH_CHIP_STM32F446Z is not set -# CONFIG_ARCH_CHIP_STM32F469A is not set -# CONFIG_ARCH_CHIP_STM32F469I is not set -# CONFIG_ARCH_CHIP_STM32F469B is not set -# CONFIG_ARCH_CHIP_STM32F469N is not set -CONFIG_STM32_FLASH_CONFIG_DEFAULT=y -# CONFIG_STM32_FLASH_CONFIG_4 is not set -# CONFIG_STM32_FLASH_CONFIG_6 is not set -# CONFIG_STM32_FLASH_CONFIG_8 is not set -# CONFIG_STM32_FLASH_CONFIG_B is not set -# CONFIG_STM32_FLASH_CONFIG_C is not set -# CONFIG_STM32_FLASH_CONFIG_D is not set -# CONFIG_STM32_FLASH_CONFIG_E is not set -# CONFIG_STM32_FLASH_CONFIG_F is not set -# CONFIG_STM32_FLASH_CONFIG_G is not set -# CONFIG_STM32_FLASH_CONFIG_I is not set -# CONFIG_STM32_STM32L15XX is not set -# CONFIG_STM32_ENERGYLITE is not set -CONFIG_STM32_STM32F10XX=y -# CONFIG_STM32_VALUELINE is not set -# CONFIG_STM32_CONNECTIVITYLINE is not set -CONFIG_STM32_PERFORMANCELINE=y -# CONFIG_STM32_USBACCESSLINE is not set -# CONFIG_STM32_HIGHDENSITY is not set -CONFIG_STM32_MEDIUMDENSITY=y -# CONFIG_STM32_LOWDENSITY is not set -# CONFIG_STM32_STM32F20XX is not set -# CONFIG_STM32_STM32F205 is not set -# CONFIG_STM32_STM32F207 is not set -# CONFIG_STM32_STM32F30XX is not set -# CONFIG_STM32_STM32F302 is not set -# CONFIG_STM32_STM32F303 is not set -# CONFIG_STM32_STM32F37XX is not set -# CONFIG_STM32_STM32F40XX is not set -# CONFIG_STM32_STM32F401 is not set -# CONFIG_STM32_STM32F411 is not set -# CONFIG_STM32_STM32F405 is not set -# CONFIG_STM32_STM32F407 is not set -# CONFIG_STM32_STM32F427 is not set -# CONFIG_STM32_STM32F429 is not set -# CONFIG_STM32_STM32F446 is not set -# CONFIG_STM32_STM32F469 is not set -# CONFIG_STM32_DFU is not set - -# -# STM32 Peripheral Support -# -# CONFIG_STM32_HAVE_CCM is not set -CONFIG_STM32_HAVE_USBDEV=y -# CONFIG_STM32_HAVE_OTGFS is not set -# CONFIG_STM32_HAVE_FSMC is not set -# CONFIG_STM32_HAVE_LTDC is not set -CONFIG_STM32_HAVE_USART3=y -CONFIG_STM32_HAVE_UART4=y -CONFIG_STM32_HAVE_UART5=y -# CONFIG_STM32_HAVE_USART6 is not set -# CONFIG_STM32_HAVE_UART7 is not set -# CONFIG_STM32_HAVE_UART8 is not set -CONFIG_STM32_HAVE_TIM1=y -# CONFIG_STM32_HAVE_TIM2 is not set -CONFIG_STM32_HAVE_TIM3=y -CONFIG_STM32_HAVE_TIM4=y -CONFIG_STM32_HAVE_TIM5=y -CONFIG_STM32_HAVE_TIM6=y -CONFIG_STM32_HAVE_TIM7=y -CONFIG_STM32_HAVE_TIM8=y -# CONFIG_STM32_HAVE_TIM9 is not set -# CONFIG_STM32_HAVE_TIM10 is not set -# CONFIG_STM32_HAVE_TIM11 is not set -# CONFIG_STM32_HAVE_TIM12 is not set -# CONFIG_STM32_HAVE_TIM13 is not set -# CONFIG_STM32_HAVE_TIM14 is not set -# CONFIG_STM32_HAVE_TIM15 is not set -# CONFIG_STM32_HAVE_TIM16 is not set -# CONFIG_STM32_HAVE_TIM17 is not set -CONFIG_STM32_HAVE_ADC2=y -CONFIG_STM32_HAVE_ADC3=y -# CONFIG_STM32_HAVE_ADC4 is not set -# CONFIG_STM32_HAVE_ADC1_DMA is not set -# CONFIG_STM32_HAVE_ADC2_DMA is not set -# CONFIG_STM32_HAVE_ADC3_DMA is not set -# CONFIG_STM32_HAVE_ADC4_DMA is not set -CONFIG_STM32_HAVE_CAN1=y -# CONFIG_STM32_HAVE_CAN2 is not set -# CONFIG_STM32_HAVE_DAC1 is not set -# CONFIG_STM32_HAVE_DAC2 is not set -# CONFIG_STM32_HAVE_RNG is not set -# CONFIG_STM32_HAVE_ETHMAC is not set -CONFIG_STM32_HAVE_I2C2=y -# CONFIG_STM32_HAVE_I2C3 is not set -CONFIG_STM32_HAVE_SPI2=y -CONFIG_STM32_HAVE_SPI3=y -# CONFIG_STM32_HAVE_SPI4 is not set -# CONFIG_STM32_HAVE_SPI5 is not set -# CONFIG_STM32_HAVE_SPI6 is not set -# CONFIG_STM32_HAVE_SAIPLL is not set -# CONFIG_STM32_HAVE_I2SPLL is not set -# CONFIG_STM32_ADC1 is not set -# CONFIG_STM32_ADC2 is not set -# CONFIG_STM32_ADC3 is not set -# CONFIG_STM32_BKP is not set -# CONFIG_STM32_CAN1 is not set -# CONFIG_STM32_CRC is not set -# CONFIG_STM32_DMA1 is not set -# CONFIG_STM32_DMA2 is not set -# CONFIG_STM32_I2C1 is not set -# CONFIG_STM32_I2C2 is not set -# CONFIG_STM32_PWR is not set -# CONFIG_STM32_SDIO is not set -# CONFIG_STM32_SPI1 is not set -# CONFIG_STM32_SPI2 is not set -# CONFIG_STM32_SPI3 is not set -# CONFIG_STM32_TIM1 is not set -# CONFIG_STM32_TIM2 is not set -# CONFIG_STM32_TIM3 is not set -# CONFIG_STM32_TIM4 is not set -# CONFIG_STM32_TIM5 is not set -# CONFIG_STM32_TIM6 is not set -# CONFIG_STM32_TIM7 is not set -# CONFIG_STM32_TIM8 is not set -CONFIG_STM32_USART1=y -# CONFIG_STM32_USART2 is not set -# CONFIG_STM32_USART3 is not set -# CONFIG_STM32_UART4 is not set -# CONFIG_STM32_UART5 is not set -# CONFIG_STM32_USB is not set -# CONFIG_STM32_IWDG is not set -# CONFIG_STM32_WWDG is not set -# CONFIG_STM32_NOEXT_VECTORS is not set - -# -# Alternate Pin Mapping -# -# CONFIG_STM32_USART1_REMAP is not set -# CONFIG_STM32_JTAG_DISABLE is not set -CONFIG_STM32_JTAG_FULL_ENABLE=y -# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set -# CONFIG_STM32_JTAG_SW_ENABLE is not set -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -# CONFIG_STM32_FORCEPOWER is not set -# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set - -# -# Timer Configuration -# -# CONFIG_STM32_ONESHOT is not set -# CONFIG_STM32_FREERUN is not set -# CONFIG_STM32_TIM1_CAP is not set -# CONFIG_STM32_TIM3_CAP is not set -# CONFIG_STM32_TIM4_CAP is not set -# CONFIG_STM32_TIM5_CAP is not set -# CONFIG_STM32_TIM8_CAP is not set -CONFIG_STM32_USART=y -CONFIG_STM32_SERIALDRIVER=y - -# -# U[S]ART Configuration -# - -# -# U[S]ART Device Configuration -# -CONFIG_STM32_USART1_SERIALDRIVER=y -# CONFIG_STM32_USART1_1WIREDRIVER is not set -# CONFIG_USART1_RS485 is not set - -# -# Serial Driver Configuration -# -# CONFIG_SERIAL_DISABLE_REORDERING is not set -# CONFIG_STM32_FLOWCONTROL_BROKEN is not set -# CONFIG_STM32_USART_BREAKS is not set -# CONFIG_STM32_USART_SINGLEWIRE is not set -CONFIG_STM32_HAVE_RTC_COUNTER=y -# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set - -# -# USB FS Host Configuration -# - -# -# USB HS Host Configuration -# - -# -# USB Host Debug Configuration -# - -# -# USB Device Configuration -# - -# -# Architecture Options -# -# CONFIG_ARCH_NOINTC is not set -# CONFIG_ARCH_VECNOTIRQ is not set -# CONFIG_ARCH_DMA is not set -CONFIG_ARCH_HAVE_IRQPRIO=y -# CONFIG_ARCH_L2CACHE is not set -# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set -# CONFIG_ARCH_HAVE_ADDRENV is not set -# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set -# CONFIG_ARCH_HAVE_MULTICPU is not set -CONFIG_ARCH_HAVE_VFORK=y -# CONFIG_ARCH_HAVE_MMU is not set -CONFIG_ARCH_HAVE_MPU=y -# CONFIG_ARCH_NAND_HWECC is not set -# CONFIG_ARCH_HAVE_EXTCLK is not set -# CONFIG_ARCH_HAVE_POWEROFF is not set -CONFIG_ARCH_HAVE_RESET=y -# CONFIG_ARCH_USE_MPU is not set -# CONFIG_ARCH_IRQPRIO is not set -# CONFIG_ARCH_STACKDUMP is not set -# CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_IDLE_CUSTOM is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set -CONFIG_ARCH_HAVE_RAMVECTORS=y -# CONFIG_ARCH_RAMVECTORS is not set - -# -# Board Settings -# -CONFIG_BOARD_LOOPSPERMSEC=5483 -# CONFIG_ARCH_CALIBRATION is not set - -# -# Interrupt options -# -CONFIG_ARCH_HAVE_INTERRUPTSTACK=y -CONFIG_ARCH_INTERRUPTSTACK=0 -CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y -# CONFIG_ARCH_HIPRI_INTERRUPT is not set - -# -# Boot options -# -# CONFIG_BOOT_RUNFROMEXTSRAM is not set -CONFIG_BOOT_RUNFROMFLASH=y -# CONFIG_BOOT_RUNFROMISRAM is not set -# CONFIG_BOOT_RUNFROMSDRAM is not set -# CONFIG_BOOT_COPYTORAM is not set - -# -# Boot Memory Configuration -# -CONFIG_RAM_START=0x20000000 -CONFIG_RAM_SIZE=20480 -# CONFIG_ARCH_HAVE_SDRAM is not set - -# -# Board Selection -# -# CONFIG_ARCH_BOARD_STM32_TINY is not set -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -# CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD="stm32f103-minimum" - -# -# Common Board Options -# -CONFIG_ARCH_HAVE_LEDS=y -CONFIG_ARCH_LEDS=y - -# -# Board-Specific Options -# -# CONFIG_BOARD_CRASHDUMP is not set -# CONFIG_LIB_BOARDCTL is not set - -# -# RTOS Features -# -CONFIG_DISABLE_OS_API=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_DISABLE_SIGNALS=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_ENVIRON=y - -# -# Clocks and Timers -# -CONFIG_ARCH_HAVE_TICKLESS=y -# CONFIG_SCHED_TICKLESS is not set -CONFIG_USEC_PER_TICK=10000 -# CONFIG_SYSTEM_TIME64 is not set -# CONFIG_CLOCK_MONOTONIC is not set -CONFIG_ARCH_HAVE_TIMEKEEPING=y -# CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2013 -CONFIG_START_MONTH=2 -CONFIG_START_DAY=26 -CONFIG_MAX_WDOGPARMS=2 -CONFIG_PREALLOC_WDOGS=4 -CONFIG_WDOG_INTRESERVE=0 -CONFIG_PREALLOC_TIMERS=0 - -# -# Tasks and Scheduling -# -# CONFIG_INIT_NONE is not set -CONFIG_INIT_ENTRYPOINT=y -# CONFIG_INIT_FILEPATH is not set -CONFIG_USER_ENTRYPOINT="nsh_main" -CONFIG_RR_INTERVAL=0 -# CONFIG_SCHED_SPORADIC is not set -CONFIG_TASK_NAME_SIZE=0 -CONFIG_MAX_TASKS=4 -# CONFIG_SCHED_HAVE_PARENT is not set -# CONFIG_SCHED_WAITPID is not set - -# -# Performance Monitoring -# -# CONFIG_SCHED_CPULOAD is not set -# CONFIG_SCHED_INSTRUMENTATION is not set - -# -# Files and I/O -# -# CONFIG_DEV_CONSOLE is not set -CONFIG_FDCLONE_DISABLE=y -# CONFIG_FDCLONE_STDIO is not set -CONFIG_SDCLONE_DISABLE=y -CONFIG_NFILE_DESCRIPTORS=0 -CONFIG_NFILE_STREAMS=0 -CONFIG_NAME_MAX=32 -# CONFIG_PRIORITY_INHERITANCE is not set - -# -# RTOS hooks -# -# CONFIG_BOARD_INITIALIZE is not set -# CONFIG_SCHED_STARTHOOK is not set -# CONFIG_SCHED_ATEXIT is not set -# CONFIG_SCHED_ONEXIT is not set -# CONFIG_MODULE is not set - -# -# Work queue support -# - -# -# Stack and heap information -# -CONFIG_IDLETHREAD_STACKSIZE=1024 -CONFIG_USERMAIN_STACKSIZE=2048 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=2048 -# CONFIG_LIB_SYSCALL is not set - -# -# Device Drivers -# -CONFIG_DISABLE_POLL=y -# CONFIG_DEV_NULL is not set -# CONFIG_DEV_ZERO is not set -# CONFIG_DEV_URANDOM is not set -# CONFIG_DEV_LOOP is not set - -# -# Buffering -# -# CONFIG_DRVR_WRITEBUFFER is not set -# CONFIG_DRVR_READAHEAD is not set -# CONFIG_RAMDISK is not set -# CONFIG_CAN is not set -# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set -# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set -# CONFIG_PWM is not set -CONFIG_ARCH_HAVE_I2CRESET=y -# CONFIG_I2C is not set -# CONFIG_SPI is not set -CONFIG_ARCH_HAVE_SPI_BITORDER=y -# CONFIG_I2S is not set - -# -# Timer Driver Support -# -# CONFIG_TIMER is not set -# CONFIG_RTC is not set -# CONFIG_WATCHDOG is not set -# CONFIG_ANALOG is not set -# CONFIG_AUDIO_DEVICES is not set -# CONFIG_VIDEO_DEVICES is not set -# CONFIG_BCH is not set -# CONFIG_INPUT is not set - -# -# IO Expander/GPIO Support -# -# CONFIG_IOEXPANDER is not set -# CONFIG_DEV_GPIO is not set - -# -# LCD Driver Support -# -# CONFIG_LCD is not set -# CONFIG_SLCD is not set - -# -# LED Support -# -# CONFIG_USERLED is not set -# CONFIG_RGBLED is not set -# CONFIG_PCA9635PW is not set -# CONFIG_NCP5623C is not set -# CONFIG_MMCSD is not set -# CONFIG_MODEM is not set -# CONFIG_MTD is not set -# CONFIG_EEPROM is not set -# CONFIG_PIPES is not set -# CONFIG_PM is not set -# CONFIG_POWER is not set -# CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set -CONFIG_SERIAL=y -# CONFIG_SERIAL_REMOVABLE is not set -CONFIG_SERIAL_CONSOLE=y -# CONFIG_16550_UART is not set -# CONFIG_UART_SERIALDRIVER is not set -# CONFIG_UART0_SERIALDRIVER is not set -# CONFIG_UART1_SERIALDRIVER is not set -# CONFIG_UART2_SERIALDRIVER is not set -# CONFIG_UART3_SERIALDRIVER is not set -# CONFIG_UART4_SERIALDRIVER is not set -# CONFIG_UART5_SERIALDRIVER is not set -# CONFIG_UART6_SERIALDRIVER is not set -# CONFIG_UART7_SERIALDRIVER is not set -# CONFIG_UART8_SERIALDRIVER is not set -# CONFIG_SCI0_SERIALDRIVER is not set -# CONFIG_SCI1_SERIALDRIVER is not set -# CONFIG_USART0_SERIALDRIVER is not set -CONFIG_USART1_SERIALDRIVER=y -# CONFIG_USART2_SERIALDRIVER is not set -# CONFIG_USART3_SERIALDRIVER is not set -# CONFIG_USART4_SERIALDRIVER is not set -# CONFIG_USART5_SERIALDRIVER is not set -# CONFIG_USART6_SERIALDRIVER is not set -# CONFIG_USART7_SERIALDRIVER is not set -# CONFIG_USART8_SERIALDRIVER is not set -# CONFIG_OTHER_UART_SERIALDRIVER is not set -CONFIG_MCU_SERIAL=y -# CONFIG_STANDARD_SERIAL is not set -# CONFIG_SERIAL_IFLOWCONTROL is not set -# CONFIG_SERIAL_OFLOWCONTROL is not set -# CONFIG_SERIAL_DMA is not set -CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y -CONFIG_USART1_SERIAL_CONSOLE=y -# CONFIG_OTHER_SERIAL_CONSOLE is not set -# CONFIG_NO_SERIAL_CONSOLE is not set - -# -# USART1 Configuration -# -CONFIG_USART1_RXBUFSIZE=64 -CONFIG_USART1_TXBUFSIZE=64 -CONFIG_USART1_BAUD=115200 -CONFIG_USART1_BITS=8 -CONFIG_USART1_PARITY=0 -CONFIG_USART1_2STOP=0 -# CONFIG_USART1_IFLOWCONTROL is not set -# CONFIG_USART1_OFLOWCONTROL is not set -# CONFIG_USART1_DMA is not set -# CONFIG_PSEUDOTERM is not set -# CONFIG_USBDEV is not set -# CONFIG_USBHOST is not set -# CONFIG_HAVE_USBTRACE is not set -# CONFIG_DRIVERS_WIRELESS is not set - -# -# System Logging -# -# CONFIG_ARCH_SYSLOG is not set -# CONFIG_RAMLOG is not set -# CONFIG_SYSLOG_INTBUFFER is not set -# CONFIG_SYSLOG_TIMESTAMP is not set -# CONFIG_SYSLOG_SERIAL_CONSOLE is not set -# CONFIG_SYSLOG_CHAR is not set -CONFIG_SYSLOG_NONE=y -# CONFIG_SYSLOG_FILE is not set -# CONFIG_SYSLOG_CHARDEV is not set - -# -# Networking Support -# -# CONFIG_ARCH_HAVE_NET is not set -# CONFIG_ARCH_HAVE_PHY is not set -# CONFIG_NET is not set - -# -# Crypto API -# -# CONFIG_CRYPTO is not set - -# -# File Systems -# - -# -# File system configuration -# -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y -# CONFIG_FS_READABLE is not set -# CONFIG_FS_WRITABLE is not set -# CONFIG_FS_NAMED_SEMAPHORES is not set -# CONFIG_FS_RAMMAP is not set -# CONFIG_FS_PROCFS is not set -# CONFIG_FS_UNIONFS is not set - -# -# Graphics Support -# -# CONFIG_NX is not set - -# -# Memory Management -# -CONFIG_MM_SMALL=y -CONFIG_MM_REGIONS=1 -# CONFIG_ARCH_HAVE_HEAP2 is not set -# CONFIG_GRAN is not set - -# -# Audio Support -# -# CONFIG_AUDIO is not set - -# -# Wireless Support -# - -# -# Binary Loader -# -# CONFIG_BINFMT_DISABLE is not set -# CONFIG_NXFLAT is not set -# CONFIG_ELF is not set -# CONFIG_BUILTIN is not set -# CONFIG_PIC is not set -# CONFIG_SYMTAB_ORDEREDBYNAME is not set - -# -# Library Routines -# - -# -# Standard C Library Options -# -CONFIG_STDIO_BUFFER_SIZE=0 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=0 -# CONFIG_LIBM is not set -CONFIG_NOPRINTF_FIELDWIDTH=y -# CONFIG_LIBC_FLOATINGPOINT is not set -# CONFIG_LIBC_LONG_LONG is not set -# CONFIG_LIBC_IOCTL_VARIADIC is not set -CONFIG_LIB_RAND_ORDER=1 -# CONFIG_EOL_IS_CR is not set -# CONFIG_EOL_IS_LF is not set -# CONFIG_EOL_IS_BOTH_CRLF is not set -CONFIG_EOL_IS_EITHER_CRLF=y -# CONFIG_LIBC_EXECFUNCS is not set -CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 -# CONFIG_LIBC_STRERROR is not set -# CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_ARCH_LOWPUTC=y -# CONFIG_TIME_EXTENDED is not set -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set -# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set -CONFIG_ARCH_HAVE_TLS=y -# CONFIG_TLS is not set -# CONFIG_LIBC_NETDB is not set - -# -# Non-standard Library Support -# -# CONFIG_LIB_CRC64_FAST is not set -# CONFIG_LIB_KBDCODEC is not set -# CONFIG_LIB_SLCDCODEC is not set -# CONFIG_LIB_HEX2BIN is not set - -# -# Basic CXX Support -# -# CONFIG_C99_BOOL8 is not set -# CONFIG_HAVE_CXX is not set - -# -# Application Configuration -# - -# -# CAN Utilities -# - -# -# Examples -# -# CONFIG_EXAMPLES_CHAT is not set -# CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_DHCPD is not set -# CONFIG_EXAMPLES_ELF is not set -# CONFIG_EXAMPLES_FTPC is not set -# CONFIG_EXAMPLES_FTPD is not set -# CONFIG_EXAMPLES_HELLO is not set -# CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_IGMP is not set -# CONFIG_EXAMPLES_JSON is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set -# CONFIG_EXAMPLES_MEDIA is not set -# CONFIG_EXAMPLES_MM is not set -# CONFIG_EXAMPLES_MODBUS is not set -# CONFIG_EXAMPLES_MOUNT is not set -# CONFIG_EXAMPLES_NRF24L01TERM is not set -CONFIG_EXAMPLES_NSH=y -# CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXFFS is not set -# CONFIG_EXAMPLES_NXHELLO is not set -# CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NXLINES is not set -# CONFIG_EXAMPLES_NXTERM is not set -# CONFIG_EXAMPLES_NXTEXT is not set -# CONFIG_EXAMPLES_OSTEST is not set -# CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_PPPD is not set -# CONFIG_EXAMPLES_RFID_READUID is not set -# CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_SENDMAIL is not set -# CONFIG_EXAMPLES_SERIALBLASTER is not set -# CONFIG_EXAMPLES_SERIALRX is not set -# CONFIG_EXAMPLES_SERLOOP is not set -# CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART is not set -# CONFIG_EXAMPLES_SMP is not set -# CONFIG_EXAMPLES_TCPECHO is not set -# CONFIG_EXAMPLES_TELNETD is not set -# CONFIG_EXAMPLES_TIFF is not set -# CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_USBTERM is not set -# CONFIG_EXAMPLES_WATCHDOG is not set -# CONFIG_EXAMPLES_WEBSERVER is not set - -# -# File System Utilities -# -# CONFIG_FSUTILS_INIFILE is not set - -# -# GPS Utilities -# -# CONFIG_GPSUTILS_MINMEA_LIB is not set - -# -# Graphics Support -# -# CONFIG_TIFF is not set -# CONFIG_GRAPHICS_TRAVELER is not set - -# -# Interpreters -# -# CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_MICROPYTHON is not set -# CONFIG_INTERPRETERS_PCODE is not set - -# -# FreeModBus -# -# CONFIG_MODBUS is not set - -# -# Network Utilities -# -# CONFIG_NETUTILS_CODECS is not set -# CONFIG_NETUTILS_ESP8266 is not set -# CONFIG_NETUTILS_FTPC is not set -# CONFIG_NETUTILS_JSON is not set -# CONFIG_NETUTILS_SMTP is not set - -# -# NSH Library -# -CONFIG_NSH_LIBRARY=y -# CONFIG_NSH_MOTD is not set - -# -# Command Line Configuration -# -CONFIG_NSH_READLINE=y -# CONFIG_NSH_CLE is not set -CONFIG_NSH_LINELEN=80 -CONFIG_NSH_DISABLE_SEMICOLON=y -CONFIG_NSH_MAXARGUMENTS=6 -# CONFIG_NSH_ARGCAT is not set -CONFIG_NSH_NESTDEPTH=3 -# CONFIG_NSH_DISABLEBG is not set - -# -# Disable Individual commands -# -CONFIG_NSH_DISABLE_ADDROUTE=y -CONFIG_NSH_DISABLE_BASENAME=y -# CONFIG_NSH_DISABLE_CAT is not set -CONFIG_NSH_DISABLE_CD=y -CONFIG_NSH_DISABLE_CP=y -# CONFIG_NSH_DISABLE_CMP is not set -CONFIG_NSH_DISABLE_DATE=y -CONFIG_NSH_DISABLE_DD=y -CONFIG_NSH_DISABLE_DF=y -CONFIG_NSH_DISABLE_DELROUTE=y -CONFIG_NSH_DISABLE_DIRNAME=y -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_FREE is not set -CONFIG_NSH_DISABLE_GET=y -# CONFIG_NSH_DISABLE_HELP is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -CONFIG_NSH_DISABLE_IFCONFIG=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -# CONFIG_NSH_DISABLE_KILL is not set -CONFIG_NSH_DISABLE_LOSETUP=y -CONFIG_NSH_DISABLE_LOSMART=y -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_MB is not set -CONFIG_NSH_DISABLE_MKDIR=y -CONFIG_NSH_DISABLE_MKRD=y -# CONFIG_NSH_DISABLE_MH is not set -CONFIG_NSH_DISABLE_MOUNT=y -CONFIG_NSH_DISABLE_MV=y -# CONFIG_NSH_DISABLE_MW is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_NSH_DISABLE_PUT=y -# CONFIG_NSH_DISABLE_PWD is not set -CONFIG_NSH_DISABLE_RM=y -CONFIG_NSH_DISABLE_RMDIR=y -# CONFIG_NSH_DISABLE_SET is not set -# CONFIG_NSH_DISABLE_SH is not set -# CONFIG_NSH_DISABLE_SLEEP is not set -CONFIG_NSH_DISABLE_TIME=y -# CONFIG_NSH_DISABLE_TEST is not set -CONFIG_NSH_DISABLE_UMOUNT=y -CONFIG_NSH_DISABLE_UNAME=y -# CONFIG_NSH_DISABLE_UNSET is not set -# CONFIG_NSH_DISABLE_USLEEP is not set -CONFIG_NSH_DISABLE_WGET=y -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_NSH_MMCSDMINOR=0 - -# -# Configure Command Options -# -CONFIG_NSH_CODECS_BUFSIZE=128 -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_NSH_FILEIOSIZE=64 - -# -# Scripting Support -# -CONFIG_NSH_DISABLESCRIPT=y - -# -# Console Configuration -# -CONFIG_NSH_CONSOLE=y -# CONFIG_NSH_ALTCONDEV is not set -# CONFIG_NSH_ARCHINIT is not set -# CONFIG_NSH_LOGIN is not set -# CONFIG_NSH_CONSOLE_LOGIN is not set - -# -# NxWidgets/NxWM -# - -# -# Platform-specific Support -# -# CONFIG_PLATFORM_CONFIGDATA is not set - -# -# System Libraries and NSH Add-Ons -# -# CONFIG_SYSTEM_CLE is not set -# CONFIG_SYSTEM_CUTERM is not set -# CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set -# CONFIG_SYSTEM_HEXED is not set -# CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_RAMTEST is not set -CONFIG_READLINE_HAVE_EXTMATCH=y -CONFIG_SYSTEM_READLINE=y -CONFIG_READLINE_ECHO=y -# CONFIG_READLINE_TABCOMPLETION is not set -# CONFIG_READLINE_CMD_HISTORY is not set -# CONFIG_SYSTEM_SUDOKU is not set -# CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_VI is not set -# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm32f103-minimum/minnsh/setenv.sh b/configs/stm32f103-minimum/minnsh/setenv.sh deleted file mode 100644 index 73dfab5a4d..0000000000 --- a/configs/stm32f103-minimum/minnsh/setenv.sh +++ /dev/null @@ -1,100 +0,0 @@ -#!/bin/bash -# configs//stm32f103-minimum/nsh/setenv.sh -# -# Copyright (C) 2016 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if [ "$_" = "$0" ] ; then - echo "You must source this script, not run it!" 1>&2 - exit 1 -fi - -WD=`pwd` -if [ ! -x "setenv.sh" ]; then - echo "This script must be executed from the top-level NuttX build directory" - exit 1 -fi - -if [ -z "${PATH_ORIG}" ]; then - export PATH_ORIG="${PATH}" -fi - -# This is the Cygwin path to the location where I installed the CodeSourcery -# toolchain under windows. You will also have to edit this if you install -# the CodeSourcery toolchain in any other location -#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" -#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" -# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" - -# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" -# You can this free toolchain here https://launchpad.net/gcc-arm-embedded -export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" - -# This is the path to the location where I installed the devkitARM toolchain -# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/ -#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin" - -# This is the Cygwin path to the location where I build the buildroot -# toolchain. -# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" - -# Add the path to the toolchain to the PATH varialble -export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" - -echo "PATH : ${PATH}" diff --git a/configs/stm32f429i-disco/ide/ltcd/uvision/libc.uvproj b/configs/stm32f429i-disco/ide/ltcd/uvision/libc.uvproj index f7340f2ce7..97ded00865 100644 --- a/configs/stm32f429i-disco/ide/ltcd/uvision/libc.uvproj +++ b/configs/stm32f429i-disco/ide/ltcd/uvision/libc.uvproj @@ -915,11 +915,6 @@ 1 ../../../../../libc/stdio/lib_memsostream.c - - lib_lowinstream.c - 1 - ../../../../../libc/stdio/lib_lowinstream.c - lib_lowoutstream.c 1 diff --git a/include/nuttx/arch.h b/include/nuttx/arch.h index 4affda90da..22b5ebb337 100644 --- a/include/nuttx/arch.h +++ b/include/nuttx/arch.h @@ -2300,16 +2300,6 @@ xcpt_t arch_phy_irq(FAR const char *intf, xcpt_t handler, phy_enable_t *enable); int up_putc(int ch); -/**************************************************************************** - * Name: up_getc - * - * Description: - * Get one character on the console - * - ****************************************************************************/ - -int up_getc(void); - /**************************************************************************** * Name: up_puts * diff --git a/include/nuttx/streams.h b/include/nuttx/streams.h index ffbcffc9ec..eb7ad67844 100644 --- a/include/nuttx/streams.h +++ b/include/nuttx/streams.h @@ -299,15 +299,13 @@ void lib_rawsistream(FAR struct lib_rawsistream_s *instream, int fd); void lib_rawsostream(FAR struct lib_rawsostream_s *outstream, int fd); /**************************************************************************** - * Name: lib_lowinstream, lib_lowoutstream + * Name: lib_lowoutstream * * Description: - * Initializes a stream for use with low-level, architecture-specific I/O. - * Defined in lib/stdio/lib_lowinstream.c and lib/stdio/lib_lowoutstream.c + * Initializes a stream for use with low-level, architecture-specific output. + * Defined in ib/stdio/lib_lowoutstream.c * * Input parameters: - * lowinstream - User allocated, uninitialized instance of struct - * lib_lowinstream_s to be initialized. * lowoutstream - User allocated, uninitialized instance of struct * lib_lowoutstream_s to be initialized. * @@ -316,9 +314,6 @@ void lib_rawsostream(FAR struct lib_rawsostream_s *outstream, int fd); * ****************************************************************************/ -#ifdef CONFIG_ARCH_LOWGETC -void lib_lowinstream(FAR struct lib_instream_s *lowinstream); -#endif #ifdef CONFIG_ARCH_LOWPUTC void lib_lowoutstream(FAR struct lib_outstream_s *lowoutstream); #endif diff --git a/libc/stdio/Make.defs b/libc/stdio/Make.defs index f308266d65..f6220671c9 100644 --- a/libc/stdio/Make.defs +++ b/libc/stdio/Make.defs @@ -41,7 +41,7 @@ CSRCS += lib_fileno.c lib_printf.c lib_sprintf.c lib_asprintf.c CSRCS += lib_snprintf.c lib_libsprintf.c lib_vsprintf.c lib_vasprintf.c CSRCS += lib_vsnprintf.c lib_libvsprintf.c lib_dprintf.c lib_vdprintf.c CSRCS += lib_meminstream.c lib_memoutstream.c lib_memsistream.c -CSRCS += lib_memsostream.c lib_lowinstream.c lib_lowoutstream.c +CSRCS += lib_memsostream.c lib_lowoutstream.c CSRCS += lib_zeroinstream.c lib_nullinstream.c lib_nulloutstream.c CSRCS += lib_sscanf.c diff --git a/libc/stdio/lib_lowinstream.c b/libc/stdio/lib_lowinstream.c deleted file mode 100644 index ad3231784d..0000000000 --- a/libc/stdio/lib_lowinstream.c +++ /dev/null @@ -1,102 +0,0 @@ -/**************************************************************************** - * libc/stdio/lib_lowinstream.c - * - * Copyright (C) 2007-2009, 2011-2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "libc.h" - -#ifdef CONFIG_ARCH_LOWGETC - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lowinstream_getc - ****************************************************************************/ - -static int lowinstream_getc(FAR struct lib_instream_s *this) -{ - int ret; - - DEBUGASSERT(this); - - /* Get the next character from the incoming stream */ - - ret = up_getc(ch); - if (ret != EOF) - { - this->nget++; - } - - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: lib_lowinstream - * - * Description: - * Initializes a stream for use with low-level, architecture-specific I/O. - * - * Input parameters: - * stream - User allocated, uninitialized instance of struct - * lib_lowinstream_s to be initialized. - * - * Returned Value: - * None (User allocated instance initialized). - * - ****************************************************************************/ - -void lib_lowinstream(FAR struct lib_instream_s *stream) -{ - stream->get = lowinstream_getc; - stream->nget = 0; -} - -#endif /* CONFIG_ARCH_LOWGETC */ -- GitLab From d9e040d76b2e6d03e06a98ff75278409f66f6fcb Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 13 Dec 2016 18:24:49 -0600 Subject: [PATCH 686/734] Remove all Calypso board configurations --- Documentation/NuttX.html | 28 +- Documentation/README.html | 8 - README.txt | 8 - configs/Kconfig | 49 - configs/README.txt | 12 - configs/arduino-due/nsh/defconfig | 1 - configs/bambino-200e/nsh/defconfig | 1 - configs/c5471evm/httpd/defconfig | 1 - configs/c5471evm/nettest/defconfig | 1 - configs/c5471evm/nsh/defconfig | 1 - configs/cc3200-launchpad/nsh/defconfig | 1 - configs/cloudctrl/nsh/defconfig | 1 - configs/compal_e86/Kconfig | 4 - configs/compal_e86/README.txt | 70 -- configs/compal_e86/include/board.h | 6 - configs/compal_e86/nsh_highram/Make.defs | 140 --- configs/compal_e86/nsh_highram/defconfig | 808 ------------- configs/compal_e86/nsh_highram/setenv.sh | 74 -- configs/compal_e86/scripts/flash.ld | 142 --- configs/compal_e86/scripts/highram.ld | 142 --- configs/compal_e86/src/Makefile | 44 - configs/compal_e86/src/boot.c | 75 -- configs/compal_e88/Kconfig | 4 - configs/compal_e88/README.txt | 52 - configs/compal_e88/include/board.h | 6 - configs/compal_e88/nsh_highram/Make.defs | 124 -- configs/compal_e88/nsh_highram/defconfig | 808 ------------- configs/compal_e88/nsh_highram/setenv.sh | 46 - configs/compal_e88/scripts/ld.script | 128 --- configs/compal_e88/src/.gitignore | 2 - configs/compal_e88/src/Makefile | 44 - configs/compal_e88/src/boot.c | 75 -- configs/compal_e99/Kconfig | 13 - configs/compal_e99/README.txt | 81 -- configs/compal_e99/include/board.h | 6 - configs/compal_e99/nsh_compalram/Make.defs | 125 -- configs/compal_e99/nsh_compalram/defconfig | 841 -------------- configs/compal_e99/nsh_compalram/setenv.sh | 63 -- configs/compal_e99/nsh_highram/Make.defs | 125 -- configs/compal_e99/nsh_highram/defconfig | 1006 ----------------- configs/compal_e99/nsh_highram/setenv.sh | 63 -- configs/compal_e99/scripts/compalram.ld | 126 --- configs/compal_e99/scripts/highram.ld | 128 --- configs/compal_e99/src/.gitignore | 2 - configs/compal_e99/src/Makefile | 44 - configs/compal_e99/src/boot.c | 75 -- configs/compal_e99/src/ssd1783.c | 542 --------- configs/compal_e99/src/ssd1783.h | 110 -- configs/dk-tm4c129x/ipv6/defconfig | 1 - configs/dk-tm4c129x/nsh/defconfig | 1 - configs/ea3131/nsh/defconfig | 1 - configs/ea3131/pgnsh/defconfig | 1 - configs/ea3131/usbserial/defconfig | 1 - configs/ea3152/ostest/defconfig | 1 - configs/eagle100/httpd/defconfig | 1 - configs/eagle100/nettest/defconfig | 1 - configs/eagle100/nsh/defconfig | 1 - configs/eagle100/nxflat/defconfig | 1 - configs/eagle100/thttpd/defconfig | 1 - configs/efm32-g8xx-stk/nsh/defconfig | 1 - configs/efm32gg-stk3700/nsh/defconfig | 1 - configs/ekk-lm3s9b96/nsh/defconfig | 1 - configs/fire-stm32v2/nsh/defconfig | 1 - configs/freedom-k64f/netnsh/defconfig | 1 - configs/freedom-k64f/nsh/defconfig | 1 - configs/freedom-kl25z/nsh/defconfig | 1 - configs/freedom-kl26z/nsh/defconfig | 1 - configs/hymini-stm32v/nsh/defconfig | 1 - configs/hymini-stm32v/nsh2/defconfig | 1 - configs/hymini-stm32v/usbmsc/defconfig | 1 - configs/hymini-stm32v/usbnsh/defconfig | 1 - configs/hymini-stm32v/usbserial/defconfig | 1 - configs/kwikstik-k40/ostest/defconfig | 1 - configs/launchxl-tms57004/nsh/defconfig | 1 - configs/lincoln60/netnsh/defconfig | 1 - configs/lincoln60/nsh/defconfig | 1 - configs/lincoln60/thttpd-binfs/defconfig | 1 - configs/lm3s6432-s2e/nsh/defconfig | 1 - configs/lm3s6965-ek/discover/defconfig | 1 - configs/lm3s6965-ek/nsh/defconfig | 1 - configs/lm3s6965-ek/nx/defconfig | 1 - configs/lm3s6965-ek/tcpecho/defconfig | 1 - configs/lm3s8962-ek/nsh/defconfig | 1 - configs/lm3s8962-ek/nx/defconfig | 1 - configs/lm4f120-launchpad/nsh/defconfig | 1 - configs/lpc4330-xplorer/nsh/defconfig | 1 - configs/lpc4337-ws/nsh/defconfig | 1 - configs/lpc4357-evb/nsh/defconfig | 1 - configs/lpc4370-link2/nsh/defconfig | 1 - configs/lpcxpresso-lpc1115/nsh/defconfig | 1 - configs/lpcxpresso-lpc1768/dhcpd/defconfig | 1 - configs/lpcxpresso-lpc1768/nsh/defconfig | 1 - configs/lpcxpresso-lpc1768/nx/defconfig | 1 - configs/lpcxpresso-lpc1768/thttpd/defconfig | 1 - configs/lpcxpresso-lpc1768/usbmsc/defconfig | 1 - configs/maple/nsh/defconfig | 1 - configs/maple/nx/defconfig | 1 - configs/maple/usbnsh/defconfig | 1 - configs/mbed/hidkbd/defconfig | 1 - configs/mbed/nsh/defconfig | 1 - configs/mcu123-lpc214x/composite/defconfig | 1 - configs/mcu123-lpc214x/nsh/defconfig | 1 - configs/mcu123-lpc214x/usbmsc/defconfig | 1 - configs/mcu123-lpc214x/usbserial/defconfig | 1 - configs/mikroe-stm32f4/fulldemo/defconfig | 1 - configs/mikroe-stm32f4/kostest/defconfig | 1 - configs/mikroe-stm32f4/nsh/defconfig | 1 - configs/mikroe-stm32f4/nx/defconfig | 1 - configs/mikroe-stm32f4/nxlines/defconfig | 1 - configs/mikroe-stm32f4/nxtext/defconfig | 1 - configs/mikroe-stm32f4/usbnsh/defconfig | 1 - configs/moxa/nsh/defconfig | 1 - configs/mx1ads/ostest/defconfig | 1 - configs/ntosd-dm320/nettest/defconfig | 1 - configs/ntosd-dm320/nsh/defconfig | 1 - configs/ntosd-dm320/poll/defconfig | 1 - configs/ntosd-dm320/thttpd/defconfig | 1 - configs/ntosd-dm320/udp/defconfig | 1 - configs/ntosd-dm320/webserver/defconfig | 1 - configs/nucleo-144/f746-evalos/defconfig | 1 - configs/nucleo-144/f746-nsh/defconfig | 1 - configs/nucleo-144/f767-evalos/defconfig | 1 - configs/nucleo-144/f767-nsh/defconfig | 1 - configs/nucleo-f303re/adc/defconfig | 1 - configs/nucleo-f303re/can/defconfig | 1 - configs/nucleo-f303re/hello/defconfig | 1 - configs/nucleo-f303re/nxlines/defconfig | 1 - configs/nucleo-f303re/pwm/defconfig | 1 - configs/nucleo-f303re/serialrx/defconfig | 1 - configs/nucleo-f303re/uavcan/defconfig | 1 - configs/nucleo-f4x1re/f401-nsh/defconfig | 1 - configs/nucleo-f4x1re/f411-nsh/defconfig | 1 - configs/nucleo-l476rg/nsh/defconfig | 1 - configs/nutiny-nuc120/nsh/defconfig | 1 - .../olimex-efm32g880f128-stk/nsh/defconfig | 1 - configs/olimex-lpc-h3131/nsh/defconfig | 1 - configs/olimex-lpc1766stk/ftpc/defconfig | 1 - configs/olimex-lpc1766stk/hidkbd/defconfig | 1 - configs/olimex-lpc1766stk/hidmouse/defconfig | 1 - configs/olimex-lpc1766stk/nettest/defconfig | 1 - configs/olimex-lpc1766stk/nsh/defconfig | 1 - configs/olimex-lpc1766stk/nx/defconfig | 1 - .../olimex-lpc1766stk/slip-httpd/defconfig | 1 - .../olimex-lpc1766stk/thttpd-binfs/defconfig | 1 - .../olimex-lpc1766stk/thttpd-nxflat/defconfig | 1 - configs/olimex-lpc1766stk/usbmsc/defconfig | 1 - configs/olimex-lpc1766stk/usbserial/defconfig | 1 - configs/olimex-lpc1766stk/zmodem/defconfig | 1 - configs/olimex-lpc2378/nsh/defconfig | 1 - configs/olimex-stm32-e407/discover/defconfig | 1 - configs/olimex-stm32-e407/netnsh/defconfig | 1 - configs/olimex-stm32-e407/nsh/defconfig | 1 - configs/olimex-stm32-e407/telnetd/defconfig | 1 - configs/olimex-stm32-e407/usbnsh/defconfig | 1 - configs/olimex-stm32-e407/webserver/defconfig | 1 - configs/olimex-stm32-h405/usbnsh/defconfig | 1 - configs/olimex-stm32-h407/nsh/defconfig | 1 - configs/olimex-stm32-p107/nsh/defconfig | 1 - configs/olimex-stm32-p207/nsh/defconfig | 1 - configs/olimex-strp711/nettest/defconfig | 1 - configs/olimex-strp711/nsh/defconfig | 1 - configs/olimexino-stm32/can/defconfig | 1 - configs/olimexino-stm32/composite/defconfig | 1 - configs/olimexino-stm32/nsh/defconfig | 1 - configs/olimexino-stm32/smallnsh/defconfig | 1 - configs/olimexino-stm32/tiny/defconfig | 1 - configs/open1788/knsh/defconfig | 1 - configs/open1788/nsh/defconfig | 1 - configs/open1788/nxlines/defconfig | 1 - configs/pcduino-a10/nsh/defconfig | 1 - configs/pirelli_dpl10/Kconfig | 4 - configs/pirelli_dpl10/README.txt | 363 ------ configs/pirelli_dpl10/include/board.h | 6 - configs/pirelli_dpl10/nsh_highram/Make.defs | 131 --- configs/pirelli_dpl10/nsh_highram/defconfig | 809 ------------- configs/pirelli_dpl10/nsh_highram/setenv.sh | 62 - configs/pirelli_dpl10/scripts/highram.ld | 132 --- configs/pirelli_dpl10/src/.gitignore | 2 - configs/pirelli_dpl10/src/Makefile | 44 - configs/pirelli_dpl10/src/boot.c | 77 -- configs/sabre-6quad/nsh/defconfig | 1 - configs/sabre-6quad/smp/defconfig | 1 - configs/sam3u-ek/knsh/defconfig | 1 - configs/sam3u-ek/nsh/defconfig | 1 - configs/sam3u-ek/nx/defconfig | 1 - configs/sam3u-ek/nxwm/defconfig | 1 - configs/sam4cmp-db/nsh/defconfig | 1 - configs/sam4e-ek/nsh/defconfig | 1 - configs/sam4e-ek/nxwm/defconfig | 1 - configs/sam4e-ek/usbnsh/defconfig | 1 - configs/sam4l-xplained/nsh/defconfig | 1 - configs/sam4s-xplained-pro/nsh/defconfig | 1 - configs/sam4s-xplained/nsh/defconfig | 1 - configs/sama5d2-xult/nsh/defconfig | 1 - configs/sama5d3-xplained/bridge/defconfig | 1 - configs/sama5d3-xplained/nsh/defconfig | 1 - configs/sama5d3x-ek/demo/defconfig | 1 - configs/sama5d3x-ek/hello/defconfig | 1 - configs/sama5d3x-ek/norboot/defconfig | 1 - configs/sama5d3x-ek/nsh/defconfig | 1 - configs/sama5d3x-ek/nx/defconfig | 1 - configs/sama5d3x-ek/nxplayer/defconfig | 1 - configs/sama5d3x-ek/nxwm/defconfig | 1 - configs/sama5d3x-ek/ov2640/defconfig | 1 - configs/sama5d4-ek/at25boot/defconfig | 1 - configs/sama5d4-ek/bridge/defconfig | 1 - configs/sama5d4-ek/dramboot/defconfig | 1 - configs/sama5d4-ek/elf/defconfig | 1 - configs/sama5d4-ek/ipv6/defconfig | 1 - configs/sama5d4-ek/knsh/defconfig | 1 - configs/sama5d4-ek/knsh/defconfig.ROMFS | 1 - configs/sama5d4-ek/nsh/defconfig | 1 - configs/sama5d4-ek/nxwm/defconfig | 1 - configs/sama5d4-ek/ramtest/defconfig | 1 - configs/samd20-xplained/nsh/defconfig | 1 - configs/samd21-xplained/nsh/defconfig | 1 - configs/same70-xplained/netnsh/defconfig | 1 - configs/same70-xplained/nsh/defconfig | 1 - configs/saml21-xplained/nsh/defconfig | 1 - configs/samv71-xult/knsh/defconfig | 1 - configs/samv71-xult/module/defconfig | 1 - configs/samv71-xult/mxtxplnd/defconfig | 1 - configs/samv71-xult/netnsh/defconfig | 1 - configs/samv71-xult/nsh/defconfig | 1 - configs/samv71-xult/nxwm/defconfig | 1 - configs/samv71-xult/vnc/defconfig | 1 - configs/samv71-xult/vnxwm/defconfig | 1 - configs/shenzhou/nsh/defconfig | 1 - configs/shenzhou/nxwm/defconfig | 1 - configs/shenzhou/thttpd/defconfig | 1 - configs/spark/composite/defconfig | 1 - configs/spark/nsh/defconfig | 1 - configs/spark/usbmsc/defconfig | 1 - configs/spark/usbnsh/defconfig | 1 - configs/spark/usbserial/defconfig | 1 - configs/stm3210e-eval/composite/defconfig | 1 - configs/stm3210e-eval/nsh/defconfig | 1 - configs/stm3210e-eval/nsh2/defconfig | 1 - configs/stm3210e-eval/nx/defconfig | 1 - configs/stm3210e-eval/nxterm/defconfig | 1 - configs/stm3210e-eval/pm/defconfig | 1 - configs/stm3210e-eval/usbmsc/defconfig | 1 - configs/stm3210e-eval/usbserial/defconfig | 1 - configs/stm3220g-eval/dhcpd/defconfig | 1 - configs/stm3220g-eval/nettest/defconfig | 1 - configs/stm3220g-eval/nsh/defconfig | 1 - configs/stm3220g-eval/nsh2/defconfig | 1 - configs/stm3220g-eval/nxwm/defconfig | 1 - configs/stm3220g-eval/telnetd/defconfig | 1 - configs/stm3240g-eval/dhcpd/defconfig | 1 - configs/stm3240g-eval/discover/defconfig | 1 - configs/stm3240g-eval/knxwm/defconfig | 1 - configs/stm3240g-eval/nettest/defconfig | 1 - configs/stm3240g-eval/nsh/defconfig | 1 - configs/stm3240g-eval/nsh2/defconfig | 1 - configs/stm3240g-eval/nxterm/defconfig | 1 - configs/stm3240g-eval/nxwm/defconfig | 1 - configs/stm3240g-eval/telnetd/defconfig | 1 - configs/stm3240g-eval/webserver/defconfig | 1 - configs/stm3240g-eval/xmlrpc/defconfig | 1 - configs/stm32_tiny/nsh/defconfig | 1 - configs/stm32_tiny/usbnsh/defconfig | 1 - configs/stm32butterfly2/nsh/defconfig | 1 - configs/stm32butterfly2/nshnet/defconfig | 1 - configs/stm32butterfly2/nshusbdev/defconfig | 1 - configs/stm32butterfly2/nshusbhost/defconfig | 1 - .../stm32f103-minimum/audio_tone/defconfig | 1 - configs/stm32f103-minimum/buttons/defconfig | 1 - configs/stm32f103-minimum/jlx12864g/defconfig | 1 - configs/stm32f103-minimum/nsh/defconfig | 1 - configs/stm32f103-minimum/pwm/defconfig | 1 - .../stm32f103-minimum/rfid-rc522/defconfig | 1 - configs/stm32f103-minimum/rgbled/defconfig | 1 - configs/stm32f103-minimum/usbnsh/defconfig | 1 - configs/stm32f103-minimum/userled/defconfig | 1 - configs/stm32f103-minimum/veml6070/defconfig | 1 - configs/stm32f3discovery/nsh/defconfig | 1 - configs/stm32f3discovery/usbnsh/defconfig | 1 - configs/stm32f411e-disco/nsh/defconfig | 1 - configs/stm32f429i-disco/extflash/defconfig | 1 - configs/stm32f429i-disco/lcd/defconfig | 1 - configs/stm32f429i-disco/ltdc/defconfig | 1 - configs/stm32f429i-disco/nsh/defconfig | 1 - configs/stm32f429i-disco/usbmsc/defconfig | 1 - configs/stm32f429i-disco/usbnsh/defconfig | 1 - configs/stm32f4discovery/canard/defconfig | 1 - configs/stm32f4discovery/cxxtest/defconfig | 1 - configs/stm32f4discovery/elf/defconfig | 1 - configs/stm32f4discovery/ipv6/defconfig | 1 - configs/stm32f4discovery/kostest/defconfig | 1 - configs/stm32f4discovery/netnsh/defconfig | 1 - configs/stm32f4discovery/nsh/defconfig | 1 - configs/stm32f4discovery/nxlines/defconfig | 1 - configs/stm32f4discovery/pm/defconfig | 1 - .../stm32f4discovery/posix_spawn/defconfig | 1 - configs/stm32f4discovery/pseudoterm/defconfig | 1 - configs/stm32f4discovery/rgbled/defconfig | 1 - configs/stm32f4discovery/uavcan/defconfig | 1 - configs/stm32f4discovery/usbnsh/defconfig | 1 - configs/stm32f4discovery/winbuild/defconfig | 1 - configs/stm32f4discovery/xen1210/defconfig | 1 - configs/stm32f746-ws/nsh/defconfig | 1 - configs/stm32f746g-disco/nsh/defconfig | 1 - configs/stm32l476-mdk/nsh/defconfig | 1 - configs/stm32l476vg-disco/nsh/defconfig | 1 - configs/stm32ldiscovery/nsh/defconfig | 1 - configs/stm32vldiscovery/nsh/defconfig | 1 - configs/teensy-3.x/nsh/defconfig | 1 - configs/teensy-3.x/usbnsh/defconfig | 1 - configs/teensy-lc/nsh/defconfig | 1 - configs/tm4c123g-launchpad/nsh/defconfig | 1 - configs/tm4c1294-launchpad/ipv6/defconfig | 1 - configs/tm4c1294-launchpad/nsh/defconfig | 1 - configs/twr-k60n512/nsh/defconfig | 1 - configs/u-blox-c027/nsh/defconfig | 1 - configs/viewtool-stm32f107/highpri/defconfig | 1 - configs/viewtool-stm32f107/netnsh/defconfig | 1 - configs/viewtool-stm32f107/nsh/defconfig | 1 - configs/zkit-arm-1769/hello/defconfig | 1 - configs/zkit-arm-1769/nsh/defconfig | 1 - configs/zkit-arm-1769/nxhello/defconfig | 1 - configs/zkit-arm-1769/thttpd/defconfig | 1 - configs/zp214xpa/nsh/defconfig | 1 - configs/zp214xpa/nxlines/defconfig | 1 - drivers/lcd/README.txt | 4 - 325 files changed, 1 insertion(+), 8155 deletions(-) delete mode 100644 configs/compal_e86/Kconfig delete mode 100644 configs/compal_e86/README.txt delete mode 100644 configs/compal_e86/include/board.h delete mode 100644 configs/compal_e86/nsh_highram/Make.defs delete mode 100644 configs/compal_e86/nsh_highram/defconfig delete mode 100755 configs/compal_e86/nsh_highram/setenv.sh delete mode 100644 configs/compal_e86/scripts/flash.ld delete mode 100644 configs/compal_e86/scripts/highram.ld delete mode 100644 configs/compal_e86/src/Makefile delete mode 100644 configs/compal_e86/src/boot.c delete mode 100644 configs/compal_e88/Kconfig delete mode 100644 configs/compal_e88/README.txt delete mode 100644 configs/compal_e88/include/board.h delete mode 100644 configs/compal_e88/nsh_highram/Make.defs delete mode 100644 configs/compal_e88/nsh_highram/defconfig delete mode 100755 configs/compal_e88/nsh_highram/setenv.sh delete mode 100644 configs/compal_e88/scripts/ld.script delete mode 100644 configs/compal_e88/src/.gitignore delete mode 100644 configs/compal_e88/src/Makefile delete mode 100644 configs/compal_e88/src/boot.c delete mode 100644 configs/compal_e99/Kconfig delete mode 100644 configs/compal_e99/README.txt delete mode 100644 configs/compal_e99/include/board.h delete mode 100644 configs/compal_e99/nsh_compalram/Make.defs delete mode 100644 configs/compal_e99/nsh_compalram/defconfig delete mode 100755 configs/compal_e99/nsh_compalram/setenv.sh delete mode 100644 configs/compal_e99/nsh_highram/Make.defs delete mode 100644 configs/compal_e99/nsh_highram/defconfig delete mode 100755 configs/compal_e99/nsh_highram/setenv.sh delete mode 100644 configs/compal_e99/scripts/compalram.ld delete mode 100644 configs/compal_e99/scripts/highram.ld delete mode 100644 configs/compal_e99/src/.gitignore delete mode 100644 configs/compal_e99/src/Makefile delete mode 100644 configs/compal_e99/src/boot.c delete mode 100644 configs/compal_e99/src/ssd1783.c delete mode 100644 configs/compal_e99/src/ssd1783.h delete mode 100644 configs/pirelli_dpl10/Kconfig delete mode 100644 configs/pirelli_dpl10/README.txt delete mode 100644 configs/pirelli_dpl10/include/board.h delete mode 100644 configs/pirelli_dpl10/nsh_highram/Make.defs delete mode 100644 configs/pirelli_dpl10/nsh_highram/defconfig delete mode 100755 configs/pirelli_dpl10/nsh_highram/setenv.sh delete mode 100644 configs/pirelli_dpl10/scripts/highram.ld delete mode 100644 configs/pirelli_dpl10/src/.gitignore delete mode 100644 configs/pirelli_dpl10/src/Makefile delete mode 100644 configs/pirelli_dpl10/src/boot.c diff --git a/Documentation/NuttX.html b/Documentation/NuttX.html index 7878f2fd25..ca35c859ed 100644 --- a/Documentation/NuttX.html +++ b/Documentation/NuttX.html @@ -1408,7 +1408,7 @@

    • Linux/Cygwin user mode simulation (1)
    • ARM


    		-

    - TI Calypso. - This port supports the TI "Calypso" MCU used in various cell phones (and, in particular, - by the Osmocom-bb project). - Like the c5471, NuttX operates on the ARM7 of this dual core processor. - Board support is available for the Motorola C139, C155 and W220 phones and for the Pirelli DP-L10 phone. -

    -
      -

      - STATUS: - This port was contributed by Denis Carilki and includes the work of Denis Carikli, Alan Carvalho de Assis, and Stefan Richter. - Calypso support first appeared in NuttX-6.17 with LCD drivers. - Support for the Calypso keyboard was added in NuttX-6.24 by Denis Carilki. - Refer to the NuttX board README files for the Compal E88, Compal E99 and Pirelli DP-L10 phones for further information. -

      -
    -


    		diff --git a/Documentation/README.html b/Documentation/README.html index 3ded166a0a..6e0d32528e 100644 --- a/Documentation/README.html +++ b/Documentation/README.html @@ -70,12 +70,6 @@ nuttx/ | | `- README.txt | |- cloudctrl/ | | `- README.txt - | |- compal_e86/ - | | `- README.txt - | |- compal_e88/ - | | `- README.txt - | |- compal_e99/ - | | `- README.txt | |- demo9s12ne64/ | | `- README.txt | |- dk-tm4c129x/ @@ -199,8 +193,6 @@ nuttx/ | | `- README.txt | |- pic32mz-starterkit/ | | `- README.txt - | |- pirelli_dpl10/ - | | `- README.txt | |- qemu-i486/ | | `- README.txt | |- sabre-6quad/ diff --git a/README.txt b/README.txt index ee43ef25cc..f09c6dff96 100644 --- a/README.txt +++ b/README.txt @@ -1287,12 +1287,6 @@ nuttx/ | | `- README.txt | |- cloudctrl | | `- README.txt - | |- compal_e86 - | | `- README.txt - | |- compal_e88 - | | `- README.txt - | |- compal_e99 - | | `- README.txt | |- demo0s12ne64/ | | `- README.txt | |- dk-tm4c129x/ @@ -1415,8 +1409,6 @@ nuttx/ | | `- README.txt | |- pic32mz-starterkit/ | | `- README.txt - | |- pirelli_dpl10/ - | | `- README.txt | |- qemu-i486/ | | `- README.txt | |- sabre-6quad/ diff --git a/configs/Kconfig b/configs/Kconfig index cf6826157b..ab35c06762 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -70,32 +70,6 @@ config ARCH_BOARD_CLOUDCTRL Small network relay development board. Based on the Shenzhou IV development board design. -config ARCH_BOARD_COMPALE86 - bool "Compal e86 phone" - depends on ARCH_CHIP_CALYPSO - ---help--- - This configuration enables board support for Compal e86 phone. - This port derives from the Compal E88 port and was provided by Craig - Comstock. - -config ARCH_BOARD_COMPALE88 - bool "Compal e88 phone" - depends on ARCH_CHIP_CALYPSO - ---help--- - This configuration enables board support for compal e88 phone. - This ports is based on patches contributed by Denis Carikli for both the - compal e99 and e88. The patches were made by Alan Carvalho de Assis and - Denis Carikli using the Stefan Richter's Osmocom-bb patches. - -config ARCH_BOARD_COMPALE99 - bool "Compal e99 phone" - depends on ARCH_CHIP_CALYPSO - ---help--- - This configuration enables board support for compal e88 and e99 phones. - This port is based on patches contributed by Denis Carikli for both the - compal e99 and e88. The patches were made by Alan Carvalho de Assis and - Denis Carikli using the Stefan Richter's Osmocom-bb patches. - config ARCH_BOARD_DEMOS92S12NEC64 bool "Freescale DMO9S12NE64 board" depends on ARCH_CHIP_MCS92S12NEC64 @@ -677,13 +651,6 @@ config ARCH_BOARD_PIC32MZ_STARTERKIT See www.microchip.com for further information. -config ARCH_BOARD_PIRELLI_DPL10 - bool "Pirelli DPL10 phone" - depends on ARCH_CHIP_CALYPSO - ---help--- - This directory contains the board support for Pirelli dpl10 phones. The - additions were made by Craig Comstock (with help form Alan Carvalho de Assis). - config ARCH_BOARD_NR5M100_NEXYS4 bool "NEXT RISC-V NR5M100 on Nexys-4 board" depends on ARCH_CHIP_NR5M100 @@ -1386,9 +1353,6 @@ config ARCH_BOARD default "bambino-200e" if ARCH_BOARD_BAMBINO_200E default "c5471evm" if ARCH_BOARD_C5471EVM default "cloudctrl" if ARCH_BOARD_CLOUDCTRL - default "compal_e86" if ARCH_BOARD_COMPALE86 - default "compal_e88" if ARCH_BOARD_COMPALE88 - default "compal_e99" if ARCH_BOARD_COMPALE99 default "demo9s12ne64" if ARCH_BOARD_DEMOS92S12NEC64 default "dk-tm4c129x" if ARCH_BOARD_DK_TM4C129X default "ea3131" if ARCH_BOARD_EA3131 @@ -1447,7 +1411,6 @@ config ARCH_BOARD default "pic32mx-starterkit" if ARCH_BOARD_PIC32MX_STARTERKIT default "pic32mx7mmb" if ARCH_BOARD_PIC32MX7MMB default "pic32mz-starterkit" if ARCH_BOARD_PIC32MZ_STARTERKIT - default "pirelli_dpl10" if ARCH_BOARD_PIRELLI_DPL10 default "nucleo-144" if ARCH_BOARD_NUCLEO_144 default "nucleo-f303re" if ARCH_BOARD_NUCLEO_F303RE default "nucleo-f4x1re" if ARCH_BOARD_NUCLEO_F401RE || ARCH_BOARD_NUCLEO_F411RE @@ -1567,15 +1530,6 @@ endif if ARCH_BOARD_CLOUDCTRL source "configs/cloudctrl/Kconfig" endif -if ARCH_BOARD_COMPALE86 -source "configs/compal_e86/Kconfig" -endif -if ARCH_BOARD_COMPALE88 -source "configs/compal_e88/Kconfig" -endif -if ARCH_BOARD_COMPALE99 -source "configs/compal_e99/Kconfig" -endif if ARCH_BOARD_DEMOS92S12NEC64 source "configs/demo9s12ne64/Kconfig" endif @@ -1747,9 +1701,6 @@ endif if ARCH_BOARD_PIC32MZ_STARTERKIT source "configs/pic32mz-starterkit/Kconfig" endif -if ARCH_BOARD_PIRELLI_DPL10 -source "configs/pirelli_dpl10/Kconfig" -endif if ARCH_BOARD_NUCLEO_144 source "configs/nucleo-144/Kconfig" endif diff --git a/configs/README.txt b/configs/README.txt index c7fe008e1d..6406ef2617 100644 --- a/configs/README.txt +++ b/configs/README.txt @@ -206,13 +206,6 @@ configs/cloudctrl board. Based on the Shenzhou IV development board design. It is based on the STM32F107VC MCU. -configs/compal_e86, compal_e88 and compal_e99 - These directories contain the board support for compal e86, e88 and e99 phones. - These ports are based on patches contributed by Denis Carikli for both the - compal e99 and e88. The patches were made by Alan Carvalho de Assis and - Denis Carikli using the Stefan Richter's Osmocom-bb patches. The variant - for the e86 was submitted by Craig Comstock. - configs/demo9s12ne64 Freescale DMO9S12NE64 board based on the MC9S12NE64 hcs12 cpu. This port uses the m9s12x GCC toolchain. STATUS: (Still) under development; it @@ -531,7 +524,6 @@ configs/pic32mx7mmb Mikroelektronika PIC32MX7 Multimedia Board (MMB). See http://www.mikroe.com/ for further information. -configs/pirelli_dpl10 configs/pic32mz-starterkit This directory contains the port of NuttX to the Microchip PIC32MZ Embedded Connectivity (EC) Starter Kit. There are two configurations of @@ -544,10 +536,6 @@ configs/pic32mz-starterkit See www.microchip.com for further information. - This directory contains the board support for Pirelli "Discus" DP-L10 phones. - It is a variant of the compal_e88 config with the small changes for the - differences in the board. - configs/qemu-i486 Port of NuttX to QEMU in i486 mode. This port will also run on real i486 hardwared (Google the Bifferboard). diff --git a/configs/arduino-due/nsh/defconfig b/configs/arduino-due/nsh/defconfig index 268589a9ae..1d50abd7e9 100644 --- a/configs/arduino-due/nsh/defconfig +++ b/configs/arduino-due/nsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/bambino-200e/nsh/defconfig b/configs/bambino-200e/nsh/defconfig index 56947667f4..405b666585 100644 --- a/configs/bambino-200e/nsh/defconfig +++ b/configs/bambino-200e/nsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/c5471evm/httpd/defconfig b/configs/c5471evm/httpd/defconfig index 86eb3afb03..2816583ae1 100644 --- a/configs/c5471evm/httpd/defconfig +++ b/configs/c5471evm/httpd/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set CONFIG_ARCH_CHIP_C5471=y -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/c5471evm/nettest/defconfig b/configs/c5471evm/nettest/defconfig index ec8f1de744..989d3be0e8 100644 --- a/configs/c5471evm/nettest/defconfig +++ b/configs/c5471evm/nettest/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set CONFIG_ARCH_CHIP_C5471=y -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/c5471evm/nsh/defconfig b/configs/c5471evm/nsh/defconfig index 8608b84420..eae7f1f095 100644 --- a/configs/c5471evm/nsh/defconfig +++ b/configs/c5471evm/nsh/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set CONFIG_ARCH_CHIP_C5471=y -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/cc3200-launchpad/nsh/defconfig b/configs/cc3200-launchpad/nsh/defconfig index eba49bcd2c..c0b7945bc2 100644 --- a/configs/cc3200-launchpad/nsh/defconfig +++ b/configs/cc3200-launchpad/nsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/cloudctrl/nsh/defconfig b/configs/cloudctrl/nsh/defconfig index 3fa1500ea5..a558bd84c1 100644 --- a/configs/cloudctrl/nsh/defconfig +++ b/configs/cloudctrl/nsh/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/compal_e86/Kconfig b/configs/compal_e86/Kconfig deleted file mode 100644 index f72f3c094c..0000000000 --- a/configs/compal_e86/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# diff --git a/configs/compal_e86/README.txt b/configs/compal_e86/README.txt deleted file mode 100644 index 704f2b6b70..0000000000 --- a/configs/compal_e86/README.txt +++ /dev/null @@ -1,70 +0,0 @@ -compal_e86 -========== - -This directory contains the board support for compal e86 phones. This port -is tested on the following phone: - -* motorola c139 (compal e86) with flash configuration - -This port is based on patches contributed by Denis Carikli for both the -compal e99 and e88. At the time of initial check-in, the following phones -were tested: - -* motorolla c155 (compal e99) with the compalram and highram configuration -* motorolla W220 (compal e88) -* The openmoko freerunner baseband(compal e88) - -The patches were made by Alan Carvalho de Assis and Denis Carikli using -the Stefan Richter's patches that can be found here: - -http://cgit.osmocom.org/cgit/nuttx-bb/log/?h=lputt%2Ftesting - -Osmocom-BB Dependencies and Sercomm -=================================== - -The build environment assumes that you have the osmocom-bb project -directory at same level as the nuttx project: - - |- nuttx - |- apps - `- osmocom-bb - -If you attempt to build this configuration without osmocom-bb, and that -you added support for sercomm in your configuration(CONFIG_SERCOMM_CONSOLE=y) -you will get compilation errors in drivers/sercomm due to header files that -are needed from the osmocom-bb directory. - -By default, NuttX will not use sercomm (HDLC protocol) to communicate with -the host system. Sercomm is the transport used by osmocom-bb that runs on top -of serial. See http://bb.osmocom.org/trac/wiki/nuttx-bb/run for detailed -the usage of nuttx with sercomm. - -Running NuttX From Flash -======================== - -Flash layout: - -0x00000 - 0x02000 - original compal loader -0x02000 - 0x10000 - simple binary to jump to 0x10000 (jumper.e86loader.bin) -0x10000 - ??? - NuttX binary (nuttx.bin) - -Using osmocon/osmoload, retrieve the compal loader, flash it and the -jumper.e86loader.bin as well as nuttx.bin. - -The jumper app is a modified version of the menu app in osmocom-bb, branch -jolly/menu. The app disabled irqs (setup by compal loader?) and jumps to -0x10000. This app is submitted as a patch to osmocom-bb mailing list. - -Loading NuttX (highram) -======================= - -The osmocom-bb wiki describes how to load NuttX. See -http://bb.osmocom.org/trac/wiki/nuttx-bb for detailed information. -The way that nuttx is loaded depends on the configuration (highram/compalram) -and phone: - -o compalram is for the ramloader(for phone having a bootloader on flash) -o highram is for phones having the romloader(if the phone has a bootrom) - or for loading in the ram trough a special loader(loaded first on ram - by talking to the ramloader) when having a ramloader(which can only - load 64k). diff --git a/configs/compal_e86/include/board.h b/configs/compal_e86/include/board.h deleted file mode 100644 index 00c96bf6f5..0000000000 --- a/configs/compal_e86/include/board.h +++ /dev/null @@ -1,6 +0,0 @@ -/**************************************************************************** - * configs/nsh_highram/include/board.h - * - * Supposed to be empty - * - ****************************************************************************/ diff --git a/configs/compal_e86/nsh_highram/Make.defs b/configs/compal_e86/nsh_highram/Make.defs deleted file mode 100644 index c06a6821b1..0000000000 --- a/configs/compal_e86/nsh_highram/Make.defs +++ /dev/null @@ -1,140 +0,0 @@ -############################################################################ -# configs/compal_e86/nsh_highram/Make.defs -# -# Copyright (C) 2007, 2008, 2011, 2013 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk -include ${TOPDIR}/arch/arm/src/arm/Toolchain.defs - -ifeq ($(CONFIG_BOOT_RUNFROMFLASH),y) - LDSCRIPT = flash.ld -else - LDSCRIPT = highram.ld -endif - -ifeq ($(WINTOOL),y) - # Windows-native toolchains - DIRLINK = $(TOPDIR)/tools/copydir.sh - DIRUNLINK = $(TOPDIR)/tools/unlink.sh - MKDEP = $(TOPDIR)/tools/mkwindeps.sh - ARCHINCLUDES = -I. -I "${shell cygpath -w $(OSMODIR)/src/shared/libosmocore/include}" -isystem "${shell cygpath -w $(TOPDIR)/include}" - ARCHXXINCLUDES = -I. -I "${shell cygpath -w $(OSMODIR)/src/shared/libosmocore/include}" -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" - ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" - -ifeq ("${CONFIG_SERCOMM_CONSOLE}","y") - OSMODIR = "${shell cygpath -w $(TOPDIR)/../../osmocom-bb}" - EXTRA_LIBS = "${shell cygpath -w $(OSMODIR)/src/target/firmware/comm/libcomm.a}" \ - "${shell cygpath -w $(OSMODIR)/src/shared/libosmocore/build-target/src/.libs/libosmocore.a}" \ - "${shell cygpath -w $(OSMODIR)/src/target/firmware/calypso/libcalypso.a}" \ - "${shell cygpath -w $(OSMODIR)/src/target/firmware/comm/libcomm.a}" -endif -else - # Linux/Cygwin-native toolchain - MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) - ARCHINCLUDES = -I. -isystem $(TOPDIR)/include - ARCHINCLUDES = -I. -I$(OSMODIR)/src/shared/libosmocore/include -isystem $(TOPDIR)/include - ARCHXXINCLUDES = -I. -I$(OSMODIR)/src/shared/libosmocore/include -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx - ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) - -ifeq ("${CONFIG_SERCOMM_CONSOLE}","y") - OSMODIR = $(TOPDIR)/../../osmocom-bb - EXTRA_LIBS = $(OSMODIR)/src/target/firmware/comm/libcomm.a \ - $(OSMODIR)/src/shared/libosmocore/build-target/src/.libs/libosmocore.a \ - $(OSMODIR)/src/target/firmware/calypso/libcalypso.a \ - $(OSMODIR)/src/target/firmware/comm/libcomm.a - # ^^^ Stupid hack! Why do I have to put it twice??? -endif -endif - -CC = $(CROSSDEV)gcc -CXX = $(CROSSDEV)g++ -CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld -AR = $(CROSSDEV)ar rcs -NM = $(CROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} -ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION = -g -endif - -ifneq ($(CONFIG_DEBUG_NOOPT),y) - ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer -endif - -ifeq ($(ARCHCCMAJOR),4) - ARCHCPUFLAGS = -mcpu=arm7tdmi -mfloat-abi=soft -fno-builtin -else - ARCHCPUFLAGS = -mapcs-32 -mcpu=arm7tdmi -msoft-float -fno-builtin -endif - -ARCHCFLAGS = -fno-builtin -ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -ARCHWARNINGSXX = -Wall -Wshadow -Wundef -ARCHDEFINES = -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -AFLAGS = $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -ASMEXT = .S -OBJEXT = .o -LIBEXT = .a -EXEEXT = - -ifneq ($(CROSSDEV),arm-nuttx-elf-) - LDFLAGS += -nostartfiles -nodefaultlibs -endif - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - LDFLAGS += -g -endif - -HOSTCC = gcc -HOSTINCLUDES = -I. -HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe -HOSTLDFLAGS = diff --git a/configs/compal_e86/nsh_highram/defconfig b/configs/compal_e86/nsh_highram/defconfig deleted file mode 100644 index 7ea34d54da..0000000000 --- a/configs/compal_e86/nsh_highram/defconfig +++ /dev/null @@ -1,808 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Nuttx/ Configuration -# - -# -# Build Setup -# -# CONFIG_EXPERIMENTAL is not set -# CONFIG_DEFAULT_SMALL is not set -CONFIG_HOST_LINUX=y -# CONFIG_HOST_OSX is not set -# CONFIG_HOST_WINDOWS is not set -# CONFIG_HOST_OTHER is not set - -# -# Build Configuration -# -# CONFIG_APPS_DIR="../apps" -CONFIG_BUILD_FLAT=y -# CONFIG_BUILD_2PASS is not set - -# -# Binary Output Formats -# -# CONFIG_RRLOAD_BINARY is not set -# CONFIG_INTELHEX_BINARY is not set -# CONFIG_MOTOROLA_SREC is not set -CONFIG_RAW_BINARY=y -# CONFIG_UBOOT_UIMAGE is not set - -# -# Customize Header Files -# -# CONFIG_ARCH_STDINT_H is not set -# CONFIG_ARCH_STDBOOL_H is not set -# CONFIG_ARCH_MATH_H is not set -# CONFIG_ARCH_FLOAT_H is not set -# CONFIG_ARCH_STDARG_H is not set -# CONFIG_ARCH_DEBUG_H is not set - -# -# Debug Options -# -CONFIG_DEBUG_ALERT=y -# CONFIG_DEBUG_FEATURES is not set -CONFIG_ARCH_HAVE_STACKCHECK=y -# CONFIG_STACK_COLORATION is not set -# CONFIG_ARCH_HAVE_HEAPCHECK is not set -# CONFIG_DEBUG_SYMBOLS is not set -CONFIG_ARCH_HAVE_CUSTOMOPT=y -# CONFIG_DEBUG_NOOPT is not set -# CONFIG_DEBUG_CUSTOMOPT is not set -CONFIG_DEBUG_FULLOPT=y - -# -# System Type -# -CONFIG_ARCH_ARM=y -# CONFIG_ARCH_AVR is not set -# CONFIG_ARCH_HC is not set -# CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_SIM is not set -# CONFIG_ARCH_X86 is not set -# CONFIG_ARCH_Z16 is not set -# CONFIG_ARCH_Z80 is not set -CONFIG_ARCH="arm" - -# -# ARM Options -# -# CONFIG_ARCH_CHIP_A1X is not set -# CONFIG_ARCH_CHIP_C5471 is not set -CONFIG_ARCH_CHIP_CALYPSO=y -# CONFIG_ARCH_CHIP_DM320 is not set -# CONFIG_ARCH_CHIP_EFM32 is not set -# CONFIG_ARCH_CHIP_IMX1 is not set -# CONFIG_ARCH_CHIP_IMX6 is not set -# CONFIG_ARCH_CHIP_KINETIS is not set -# CONFIG_ARCH_CHIP_KL is not set -# CONFIG_ARCH_CHIP_LM is not set -# CONFIG_ARCH_CHIP_TIVA is not set -# CONFIG_ARCH_CHIP_LPC11XX is not set -# CONFIG_ARCH_CHIP_LPC17XX is not set -# CONFIG_ARCH_CHIP_LPC214X is not set -# CONFIG_ARCH_CHIP_LPC2378 is not set -# CONFIG_ARCH_CHIP_LPC31XX is not set -# CONFIG_ARCH_CHIP_LPC43XX is not set -# CONFIG_ARCH_CHIP_NUC1XX is not set -# CONFIG_ARCH_CHIP_SAMA5 is not set -# CONFIG_ARCH_CHIP_SAMD is not set -# CONFIG_ARCH_CHIP_SAML is not set -# CONFIG_ARCH_CHIP_SAM34 is not set -# CONFIG_ARCH_CHIP_SAMV7 is not set -# CONFIG_ARCH_CHIP_STM32 is not set -# CONFIG_ARCH_CHIP_STM32F7 is not set -# CONFIG_ARCH_CHIP_STM32L4 is not set -# CONFIG_ARCH_CHIP_STR71X is not set -# CONFIG_ARCH_CHIP_TMS570 is not set -# CONFIG_ARCH_CHIP_MOXART is not set -CONFIG_ARCH_ARM7TDMI=y -# CONFIG_ARCH_ARM926EJS is not set -# CONFIG_ARCH_ARM920T is not set -# CONFIG_ARCH_CORTEXM0 is not set -# CONFIG_ARCH_CORTEXM3 is not set -# CONFIG_ARCH_CORTEXM4 is not set -# CONFIG_ARCH_CORTEXM7 is not set -# CONFIG_ARCH_CORTEXA5 is not set -# CONFIG_ARCH_CORTEXA8 is not set -# CONFIG_ARCH_CORTEXA9 is not set -# CONFIG_ARCH_CORTEXR4 is not set -# CONFIG_ARCH_CORTEXR4F is not set -# CONFIG_ARCH_CORTEXR5 is not set -# CONFIG_ARCH_CORTEX5F is not set -# CONFIG_ARCH_CORTEXR7 is not set -# CONFIG_ARCH_CORTEXR7F is not set -CONFIG_ARCH_FAMILY="arm" -CONFIG_ARCH_CHIP="calypso" -# CONFIG_ARM_TOOLCHAIN_IAR is not set -# CONFIG_ARM_TOOLCHAIN_GNU is not set -# CONFIG_ARCH_HAVE_FPU is not set -# CONFIG_ARCH_HAVE_DPFPU is not set -# CONFIG_ARCH_HAVE_TRUSTZONE is not set -# CONFIG_ARM_HAVE_MPU_UNIFIED is not set -CONFIG_ARCH_HAVE_LOWVECTORS=y -# CONFIG_ARCH_LOWVECTORS is not set - -# -# ARM Configuration Options -# -# CONFIG_ARM_TOOLCHAIN_BUILDROOT is not set -# CONFIG_ARM_TOOLCHAIN_CODESOURCERYL is not set -CONFIG_ARM_TOOLCHAIN_GNU_EABIL=y -# CONFIG_ARM_TOOLCHAIN_GNU_OABI is not set -CONFIG_UART_IRDA_BAUD=115200 -CONFIG_UART_IRDA_PARITY=0 -CONFIG_UART_IRDA_BITS=8 -CONFIG_UART_IRDA_2STOP=0 -CONFIG_UART_IRDA_RXBUFSIZE=256 -CONFIG_UART_IRDA_TXBUFSIZE=256 -CONFIG_UART_MODEM_BAUD=115200 -CONFIG_UART_MODEM_PARITY=0 -CONFIG_UART_MODEM_BITS=8 -CONFIG_UART_MODEM_2STOP=0 -CONFIG_UART_MODEM_RXBUFSIZE=256 -CONFIG_UART_MODEM_TXBUFSIZE=256 - -# -# Calypso Configuration Options -# - -# -# Modem UART Configuration -# -# CONFIG_UART_MODEM_HWFLOWCONTROL is not set - -# -# IrDA UART Configuration -# -# CONFIG_UART_IRDA_HWFLOWCONTROL is not set -# CONFIG_USE_SERCOMM_CONSOLE is not set -# CONFIG_SERIAL_MODEM_CONSOLE is not set -# CONFIG_SERIAL_IRDA_CONSOLE is not set -CONFIG_SERIAL_CONSOLE_NONE=y - -# -# Architecture Options -# -# CONFIG_ARCH_NOINTC is not set -# CONFIG_ARCH_VECNOTIRQ is not set -# CONFIG_ARCH_DMA is not set -# CONFIG_ARCH_HAVE_IRQPRIO is not set -# CONFIG_ARCH_L2CACHE is not set -# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set -# CONFIG_ARCH_HAVE_ADDRENV is not set -# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set -# CONFIG_ARCH_HAVE_MULTICPU is not set -CONFIG_ARCH_HAVE_VFORK=y -# CONFIG_ARCH_HAVE_MMU is not set -# CONFIG_ARCH_HAVE_MPU is not set -# CONFIG_ARCH_NAND_HWECC is not set -# CONFIG_ARCH_HAVE_EXTCLK is not set -CONFIG_ARCH_HAVE_POWEROFF=y -# CONFIG_ARCH_HAVE_RESET is not set -CONFIG_ARCH_STACKDUMP=y -# CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_IDLE_CUSTOM is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set -# CONFIG_ARCH_HAVE_RAMVECTORS is not set - -# -# Board Settings -# -CONFIG_BOARD_LOOPSPERMSEC=1250 -# CONFIG_ARCH_CALIBRATION is not set - -# -# Interrupt options -# -CONFIG_ARCH_HAVE_INTERRUPTSTACK=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set - -# -# Boot options -# -# CONFIG_BOOT_RUNFROMEXTSRAM is not set -CONFIG_BOOT_RUNFROMFLASH=y -# CONFIG_BOOT_RUNFROMISRAM is not set -# CONFIG_BOOT_RUNFROMSDRAM is not set -# CONFIG_BOOT_COPYTORAM is not set - -# -# Boot Memory Configuration -# -CONFIG_RAM_START=0 -CONFIG_RAM_SIZE=8650752 -# CONFIG_ARCH_HAVE_SDRAM is not set - -# -# Board Selection -# -CONFIG_ARCH_BOARD_COMPALE86=y -# CONFIG_ARCH_BOARD_COMPALE88 is not set -# CONFIG_ARCH_BOARD_COMPALE99 is not set -# CONFIG_ARCH_BOARD_PIRELLI_DPL10 is not set -# CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD="compal_e86" - -# -# Common Board Options -# -CONFIG_NSH_MMCSDMINOR=0 - -# -# Board-Specific Options -# -CONFIG_LIB_BOARDCTL=y -CONFIG_BOARDCTL_POWEROFF=y -# CONFIG_BOARDCTL_UNIQUEID is not set -# CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_GRAPHICS is not set -# CONFIG_BOARDCTL_IOCTL is not set - -# -# RTOS Features -# -CONFIG_DISABLE_OS_API=y -# CONFIG_DISABLE_POSIX_TIMERS is not set -# CONFIG_DISABLE_PTHREAD is not set -# CONFIG_DISABLE_SIGNALS is not set -CONFIG_DISABLE_MQUEUE=y -# CONFIG_DISABLE_ENVIRON is not set - -# -# Clocks and Timers -# -CONFIG_USEC_PER_TICK=10000 -# CONFIG_SYSTEM_TIME64 is not set -# CONFIG_CLOCK_MONOTONIC is not set -# CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2007 -CONFIG_START_MONTH=2 -CONFIG_START_DAY=13 -CONFIG_MAX_WDOGPARMS=4 -CONFIG_PREALLOC_WDOGS=8 -CONFIG_WDOG_INTRESERVE=1 -CONFIG_PREALLOC_TIMERS=8 - -# -# Tasks and Scheduling -# -# CONFIG_INIT_NONE is not set -CONFIG_INIT_ENTRYPOINT=y -# CONFIG_INIT_FILEPATH is not set -CONFIG_USER_ENTRYPOINT="nsh_main" -CONFIG_RR_INTERVAL=200 -# CONFIG_SCHED_SPORADIC is not set -CONFIG_TASK_NAME_SIZE=0 -CONFIG_MAX_TASKS=16 -# CONFIG_SCHED_HAVE_PARENT is not set -# CONFIG_SCHED_WAITPID is not set - -# -# Pthread Options -# -# CONFIG_MUTEX_TYPES is not set -CONFIG_NPTHREAD_KEYS=4 - -# -# Performance Monitoring -# -# CONFIG_SCHED_CPULOAD is not set -# CONFIG_SCHED_INSTRUMENTATION is not set - -# -# Files and I/O -# -CONFIG_DEV_CONSOLE=y -# CONFIG_FDCLONE_DISABLE is not set -# CONFIG_FDCLONE_STDIO is not set -CONFIG_SDCLONE_DISABLE=y -CONFIG_NFILE_DESCRIPTORS=8 -CONFIG_NFILE_STREAMS=8 -CONFIG_NAME_MAX=32 -# CONFIG_PRIORITY_INHERITANCE is not set - -# -# RTOS hooks -# -# CONFIG_BOARD_INITIALIZE is not set -# CONFIG_SCHED_STARTHOOK is not set -# CONFIG_SCHED_ATEXIT is not set -# CONFIG_SCHED_ONEXIT is not set - -# -# Signal Numbers -# -CONFIG_SIG_SIGUSR1=1 -CONFIG_SIG_SIGUSR2=2 -CONFIG_SIG_SIGALARM=3 -CONFIG_SIG_SIGCONDTIMEDOUT=16 -# CONFIG_MODULE is not set - -# -# Work queue support -# -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set -# CONFIG_SCHED_LPWORK is not set - -# -# Stack and heap information -# -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_USERMAIN_STACKSIZE=2048 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=2048 -# CONFIG_LIB_SYSCALL is not set - -# -# Device Drivers -# -CONFIG_DISABLE_POLL=y -CONFIG_DEV_NULL=y -# CONFIG_DEV_ZERO is not set -# CONFIG_DEV_LOOP is not set - -# -# Buffering -# -# CONFIG_DRVR_WRITEBUFFER is not set -# CONFIG_DRVR_READAHEAD is not set -# CONFIG_RAMDISK is not set -# CONFIG_CAN is not set -# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set -# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set -# CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set -# CONFIG_I2C is not set -CONFIG_SPI=y -# CONFIG_SPI_SLAVE is not set -CONFIG_SPI_EXCHANGE=y -# CONFIG_SPI_CMDDATA is not set -# CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set -# CONFIG_SPI_CS_DELAY_CONTROL is not set -# CONFIG_I2S is not set - -# -# Timer Driver Support -# -# CONFIG_TIMER is not set -# CONFIG_RTC is not set -# CONFIG_WATCHDOG is not set -# CONFIG_ANALOG is not set -# CONFIG_AUDIO_DEVICES is not set -# CONFIG_VIDEO_DEVICES is not set -# CONFIG_BCH is not set -# CONFIG_INPUT is not set -# CONFIG_IOEXPANDER is not set - -# -# LCD Driver Support -# -# CONFIG_LCD is not set -# CONFIG_SLCD is not set - -# -# LED Support -# -# CONFIG_RGBLED is not set -# CONFIG_PCA9635PW is not set -# CONFIG_NCP5623C is not set -# CONFIG_MMCSD is not set -# CONFIG_MODEM is not set -# CONFIG_MTD is not set -# CONFIG_EEPROM is not set -# CONFIG_PIPES is not set -# CONFIG_PM is not set -# CONFIG_POWER is not set -# CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set -CONFIG_SERIAL=y -# CONFIG_DEV_LOWCONSOLE is not set -# CONFIG_SERIAL_REMOVABLE is not set -CONFIG_SERIAL_CONSOLE=y -# CONFIG_16550_UART is not set -# CONFIG_UART_SERIALDRIVER is not set -# CONFIG_UART0_SERIALDRIVER is not set -# CONFIG_UART1_SERIALDRIVER is not set -# CONFIG_UART2_SERIALDRIVER is not set -# CONFIG_UART3_SERIALDRIVER is not set -# CONFIG_UART4_SERIALDRIVER is not set -# CONFIG_UART5_SERIALDRIVER is not set -# CONFIG_UART6_SERIALDRIVER is not set -# CONFIG_UART7_SERIALDRIVER is not set -# CONFIG_UART8_SERIALDRIVER is not set -# CONFIG_SCI0_SERIALDRIVER is not set -# CONFIG_SCI1_SERIALDRIVER is not set -# CONFIG_USART0_SERIALDRIVER is not set -# CONFIG_USART1_SERIALDRIVER is not set -# CONFIG_USART2_SERIALDRIVER is not set -# CONFIG_USART3_SERIALDRIVER is not set -# CONFIG_USART4_SERIALDRIVER is not set -# CONFIG_USART5_SERIALDRIVER is not set -# CONFIG_USART6_SERIALDRIVER is not set -# CONFIG_USART7_SERIALDRIVER is not set -# CONFIG_USART8_SERIALDRIVER is not set -CONFIG_OTHER_UART_SERIALDRIVER=y -CONFIG_MCU_SERIAL=y -# CONFIG_STANDARD_SERIAL is not set -# CONFIG_SERIAL_IFLOWCONTROL is not set -# CONFIG_SERIAL_OFLOWCONTROL is not set -# CONFIG_SERIAL_DMA is not set -# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set -CONFIG_OTHER_SERIAL_CONSOLE=y -# CONFIG_NO_SERIAL_CONSOLE is not set -# CONFIG_USBDEV is not set -# CONFIG_USBHOST is not set -# CONFIG_DRIVERS_WIRELESS is not set - -# -# System Logging -# -# CONFIG_ARCH_SYSLOG is not set -# CONFIG_RAMLOG is not set -# CONFIG_SYSLOG_INTBUFFER is not set -# CONFIG_SYSLOG_TIMESTAMP is not set -CONFIG_SYSLOG_SERIAL_CONSOLE=y -# CONFIG_SYSLOG_CHAR is not set -CONFIG_SYSLOG_CONSOLE=y -# CONFIG_SYSLOG_NONE is not set -# CONFIG_SYSLOG_FILE is not set - -# -# Networking Support -# -# CONFIG_ARCH_HAVE_NET is not set -# CONFIG_ARCH_HAVE_PHY is not set -# CONFIG_NET is not set - -# -# Crypto API -# -# CONFIG_CRYPTO is not set - -# -# File Systems -# - -# -# File system configuration -# -# CONFIG_DISABLE_MOUNTPOINT is not set -# CONFIG_FS_AUTOMOUNTER is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_FS_READABLE is not set -# CONFIG_FS_WRITABLE is not set -# CONFIG_FS_NAMED_SEMAPHORES is not set -# CONFIG_FS_RAMMAP is not set -# CONFIG_FS_FAT is not set -# CONFIG_FS_NXFFS is not set -# CONFIG_FS_ROMFS is not set -# CONFIG_FS_TMPFS is not set -# CONFIG_FS_SMARTFS is not set -# CONFIG_FS_BINFS is not set -# CONFIG_FS_PROCFS is not set -# CONFIG_FS_UNIONFS is not set - -# -# Graphics Support -# -# CONFIG_NX is not set - -# -# Memory Management -# -# CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=1 -CONFIG_ARCH_HAVE_HEAP2=y -CONFIG_HEAP2_BASE=0x00000000 -CONFIG_HEAP2_SIZE=0 -# CONFIG_GRAN is not set - -# -# Audio Support -# -# CONFIG_AUDIO is not set - -# -# Wireless Support -# - -# -# Binary Loader -# -# CONFIG_BINFMT_DISABLE is not set -# CONFIG_BINFMT_EXEPATH is not set -# CONFIG_NXFLAT is not set -# CONFIG_ELF is not set -CONFIG_BUILTIN=y -# CONFIG_PIC is not set -# CONFIG_SYMTAB_ORDEREDBYNAME is not set - -# -# Library Routines -# - -# -# Standard C Library Options -# -CONFIG_STDIO_BUFFER_SIZE=1024 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=2 -CONFIG_LIB_HOMEDIR="/" -# CONFIG_LIBM is not set -# CONFIG_NOPRINTF_FIELDWIDTH is not set -# CONFIG_LIBC_FLOATINGPOINT is not set -CONFIG_LIBC_LONG_LONG=y -# CONFIG_LIBC_IOCTL_VARIADIC is not set -CONFIG_LIB_RAND_ORDER=1 -# CONFIG_EOL_IS_CR is not set -# CONFIG_EOL_IS_LF is not set -# CONFIG_EOL_IS_BOTH_CRLF is not set -CONFIG_EOL_IS_EITHER_CRLF=y -# CONFIG_LIBC_EXECFUNCS is not set -CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 -# CONFIG_LIBC_STRERROR is not set -# CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_ARCH_LOWPUTC=y -# CONFIG_LIBC_LOCALTIME is not set -# CONFIG_TIME_EXTENDED is not set -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set -# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set -CONFIG_ARCH_HAVE_TLS=y -# CONFIG_TLS is not set -# CONFIG_LIBC_NETDB is not set - -# -# Non-standard Library Support -# -# CONFIG_LIB_CRC64_FAST is not set -# CONFIG_LIB_KBDCODEC is not set -# CONFIG_LIB_SLCDCODEC is not set - -# -# Basic CXX Support -# -# CONFIG_C99_BOOL8 is not set -# CONFIG_HAVE_CXX is not set - -# -# Application Configuration -# - -# -# Built-In Applications -# -CONFIG_BUILTIN_PROXY_STACKSIZE=1024 - -# -# CAN Utilities -# - -# -# Examples -# -# CONFIG_EXAMPLES_CHAT is not set -# CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set -# CONFIG_EXAMPLES_DHCPD is not set -# CONFIG_EXAMPLES_ELF is not set -# CONFIG_EXAMPLES_FTPC is not set -# CONFIG_EXAMPLES_FTPD is not set -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_HELLO_PRIORITY=100 -CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 -# CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_IGMP is not set -# CONFIG_EXAMPLES_JSON is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set -# CONFIG_EXAMPLES_MEDIA is not set -# CONFIG_EXAMPLES_MM is not set -# CONFIG_EXAMPLES_MODBUS is not set -# CONFIG_EXAMPLES_MOUNT is not set -# CONFIG_EXAMPLES_NRF24L01TERM is not set -CONFIG_EXAMPLES_NSH=y -# CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXFFS is not set -# CONFIG_EXAMPLES_NXHELLO is not set -# CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NXLINES is not set -# CONFIG_EXAMPLES_NXTERM is not set -# CONFIG_EXAMPLES_NXTEXT is not set -# CONFIG_EXAMPLES_OSTEST is not set -# CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_PPPD is not set -# CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_SENDMAIL is not set -# CONFIG_EXAMPLES_SERIALBLASTER is not set -# CONFIG_EXAMPLES_SERIALRX is not set -# CONFIG_EXAMPLES_SERLOOP is not set -# CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART is not set -# CONFIG_EXAMPLES_SMART_TEST is not set -# CONFIG_EXAMPLES_SMP is not set -# CONFIG_EXAMPLES_TCPECHO is not set -# CONFIG_EXAMPLES_TELNETD is not set -# CONFIG_EXAMPLES_TIFF is not set -# CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_USBSERIAL is not set -# CONFIG_EXAMPLES_USBTERM is not set -# CONFIG_EXAMPLES_WATCHDOG is not set -# CONFIG_EXAMPLES_WEBSERVER is not set - -# -# File System Utilities -# -# CONFIG_FSUTILS_INIFILE is not set - -# -# GPS Utilities -# -# CONFIG_GPSUTILS_MINMEA_LIB is not set - -# -# Graphics Support -# -# CONFIG_TIFF is not set -# CONFIG_GRAPHICS_TRAVELER is not set - -# -# Interpreters -# -# CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_MICROPYTHON is not set -# CONFIG_INTERPRETERS_PCODE is not set - -# -# FreeModBus -# -# CONFIG_MODBUS is not set - -# -# Network Utilities -# -# CONFIG_NETUTILS_CODECS is not set -# CONFIG_NETUTILS_ESP8266 is not set -# CONFIG_NETUTILS_FTPC is not set -# CONFIG_NETUTILS_JSON is not set -# CONFIG_NETUTILS_SMTP is not set - -# -# NSH Library -# -CONFIG_NSH_LIBRARY=y -# CONFIG_NSH_MOTD is not set - -# -# Command Line Configuration -# -CONFIG_NSH_READLINE=y -# CONFIG_NSH_CLE is not set -CONFIG_NSH_LINELEN=80 -# CONFIG_NSH_DISABLE_SEMICOLON is not set -CONFIG_NSH_CMDPARMS=y -CONFIG_NSH_MAXARGUMENTS=6 -CONFIG_NSH_ARGCAT=y -CONFIG_NSH_NESTDEPTH=3 -# CONFIG_NSH_DISABLEBG is not set -CONFIG_NSH_BUILTIN_APPS=y - -# -# Disable Individual commands -# -# CONFIG_NSH_DISABLE_ADDROUTE is not set -# CONFIG_NSH_DISABLE_BASENAME is not set -# CONFIG_NSH_DISABLE_CAT is not set -# CONFIG_NSH_DISABLE_CD is not set -# CONFIG_NSH_DISABLE_CP is not set -# CONFIG_NSH_DISABLE_CMP is not set -CONFIG_NSH_DISABLE_DATE=y -# CONFIG_NSH_DISABLE_DD is not set -# CONFIG_NSH_DISABLE_DF is not set -# CONFIG_NSH_DISABLE_DELROUTE is not set -# CONFIG_NSH_DISABLE_DIRNAME is not set -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HELP is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -CONFIG_NSH_DISABLE_IFUPDOWN=y -# CONFIG_NSH_DISABLE_KILL is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -CONFIG_NSH_DISABLE_LOSMART=y -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_MB is not set -# CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_MH is not set -# CONFIG_NSH_DISABLE_MOUNT is not set -# CONFIG_NSH_DISABLE_MV is not set -# CONFIG_NSH_DISABLE_MW is not set -# CONFIG_NSH_DISABLE_POWEROFF is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_PWD is not set -# CONFIG_NSH_DISABLE_RM is not set -# CONFIG_NSH_DISABLE_RMDIR is not set -# CONFIG_NSH_DISABLE_SET is not set -# CONFIG_NSH_DISABLE_SH is not set -CONFIG_NSH_DISABLE_SHUTDOWN=y -# CONFIG_NSH_DISABLE_SLEEP is not set -# CONFIG_NSH_DISABLE_TIME is not set -# CONFIG_NSH_DISABLE_TEST is not set -# CONFIG_NSH_DISABLE_UMOUNT is not set -# CONFIG_NSH_DISABLE_UNAME is not set -# CONFIG_NSH_DISABLE_UNSET is not set -# CONFIG_NSH_DISABLE_USLEEP is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set - -# -# Configure Command Options -# -# CONFIG_NSH_CMDOPT_DF_H is not set -CONFIG_NSH_CODECS_BUFSIZE=128 -CONFIG_NSH_CMDOPT_HEXDUMP=y -CONFIG_NSH_FILEIOSIZE=1024 - -# -# Scripting Support -# -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_ITEF is not set -# CONFIG_NSH_DISABLE_LOOPS is not set - -# -# Console Configuration -# -CONFIG_NSH_CONSOLE=y -# CONFIG_NSH_ALTCONDEV is not set -# CONFIG_NSH_ARCHINIT is not set -# CONFIG_NSH_LOGIN is not set -# CONFIG_NSH_CONSOLE_LOGIN is not set - -# -# NxWidgets/NxWM -# - -# -# Platform-specific Support -# -# CONFIG_PLATFORM_CONFIGDATA is not set - -# -# System Libraries and NSH Add-Ons -# -# CONFIG_SYSTEM_CLE is not set -# CONFIG_SYSTEM_CUTERM is not set -# CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set -# CONFIG_SYSTEM_HEXED is not set -# CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_RAMTEST is not set -CONFIG_READLINE_HAVE_EXTMATCH=y -CONFIG_SYSTEM_READLINE=y -CONFIG_READLINE_ECHO=y -# CONFIG_READLINE_TABCOMPLETION is not set -# CONFIG_READLINE_CMD_HISTORY is not set -# CONFIG_SYSTEM_SUDOKU is not set -# CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_VI is not set -# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/compal_e86/nsh_highram/setenv.sh b/configs/compal_e86/nsh_highram/setenv.sh deleted file mode 100755 index 3828a56504..0000000000 --- a/configs/compal_e86/nsh_highram/setenv.sh +++ /dev/null @@ -1,74 +0,0 @@ -#!/bin/bash -# compal_e86/nsh_highram/setenv.sh -# -# Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if [ "$_" = "$0" ] ; then - echo "You must source this script, not run it!" 1>&2 - exit 1 -fi - -WD=`pwd` -if [ ! -x "setenv.sh" ]; then - echo "This script must be executed from the top-level NuttX build directory" - exit 1 -fi - -if [ -z "${PATH_ORIG}" ]; then - export PATH_ORIG="${PATH}" -fi - -# This is the Cygwin path to the location where I installed the Atmel GCC -# toolchain under Windows. You will also have to edit this if you install -# this toolchain in any other location -#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Atmel/Atmel Toolchain/ARM GCC/Native/4.7.3.99/arm-gnu-toolchain/bin" - -# This is the Cygwin path to the location where I installed the CodeSourcery -# toolchain under windows. You will also have to edit this if you install -# the CodeSourcery toolchain in any other location -#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" - -# These are the Cygwin paths to the locations where I installed the Atollic -# toolchain under windows. You will also have to edit this if you install -# the Atollic toolchain in any other location. /usr/bin is added before -# the Atollic bin path because there is are binaries named gcc.exe and g++.exe -# at those locations as well. -#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" - -# This is the Cygwin path to the location where I build the buildroot -# toolchain. -export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" - -# Add the path to the toolchain to the PATH varialble -export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" - -echo "PATH : ${PATH}" diff --git a/configs/compal_e86/scripts/flash.ld b/configs/compal_e86/scripts/flash.ld deleted file mode 100644 index 73c72f00ce..0000000000 --- a/configs/compal_e86/scripts/flash.ld +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Linker script for flashed applications on the Compal E86 - * - * This script creates a binary that can be linked at 0xFFFF, starting - * with the second flash page. This is what a phone application or - * pure layer1 device uses. - * - * XXX: interrupts? - * - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -MEMORY -{ - LOADR (rx) : ORIGIN = 0x00000000, LENGTH = 0x10000 - /* 4 MBytes of external flash memory (minus loader) */ - FLASH (rx) : ORIGIN = 0x00010000, LENGTH = 0x3F0000 - /* 256 kBytes of internal zero-waitstate sram */ - IRAM (rw) : ORIGIN = 0x00800000, LENGTH = 0x040000 - /* 256 kBytes of external slow sram */ - ERAM (rw) : ORIGIN = 0x01000000, LENGTH = 0x040000 -} -SECTIONS -{ - /* entrypoint */ - .text.start : { - PROVIDE(_start = .); - KEEP(*(.text.start)) - *(.text.start) - } > FLASH - - /* exception vectors from 0x80001c to 0x800034 */ - .text.exceptions 0x80001c : { - KEEP(*(.text.exceptions)) - * (.text.exceptions) - . = ALIGN(4); - } > IRAM AT> FLASH - PROVIDE(_exceptions = LOADADDR(.text.exceptions)); - - /* code */ - .text : { - _stext = ABSOLUTE(.) ; - /* regular code */ - *(.text*) - /* gcc voodoo */ - *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx) - _etext = ABSOLUTE(.) ; - } > FLASH - PROVIDE(_text_start = ADDR(.text)); - PROVIDE(_text_end = ADDR(.text) + SIZEOF(.text)); - - /* constructor pointers */ - .ctors : { - /* ctor count */ - LONG(SIZEOF(.ctors) / 4 - 2) - /* ctor pointers */ - KEEP(*(SORT(.ctors))) - /* end of list */ - LONG(0) - } > FLASH - PROVIDE(_ctor_start = LOADADDR(.ctors)); - PROVIDE(_ctor_end = LOADADDR(.ctors) + SIZEOF(.ctors)); - - /* destructor pointers */ - .dtors : { - /* dtor count */ - LONG(SIZEOF(.dtors) / 4 - 2) - /* dtor pointers */ - KEEP(*(SORT(.dtors))) - /* end of list */ - LONG(0) - } > FLASH - PROVIDE(_dtor_start = LOADADDR(.dtors)); - PROVIDE(_dtor_end = LOADADDR(.dtors) + SIZEOF(.dtors)); - - /* read-only data */ - .rodata : { - *(.rodata*) - _eronly = ABSOLUTE(.) ; - } > FLASH - PROVIDE(_rodata_start = ADDR(.rodata)); - PROVIDE(_rodata_end = ADDR(.rodata) + SIZEOF(.rodata)); - - /* pic offset tables */ - .got : { - . = ALIGN(4); - *(.got) - *(.got.plt) *(.igot.plt) *(.got) *(.igot) - . = ALIGN(4); - } > FLASH - PROVIDE(_got_start = ADDR(.got)); - PROVIDE(_got_end = ADDR(.got) + SIZEOF(.got)); - - /* reserved ram */ - .compal.reservedram 0x800000 (NOLOAD) : { - . = 0xff; - } > IRAM - - /* initialized data */ - .data : AT (LOADADDR(.got) + SIZEOF(.got)) { - . = ALIGN(4); - _sdata = ABSOLUTE(.); - *(.data) - _edata = ABSOLUTE(.); - . = ALIGN(4); - } > IRAM - PROVIDE(__data_start = LOADADDR(.data)); - PROVIDE(__data_end = LOADADDR(.data) + SIZEOF(.data)); - PROVIDE(_data_start = ADDR(.data)); - PROVIDE(_data_end = ADDR(.data) + SIZEOF(.data)); - - /* ram code */ - .ramtext : AT (LOADADDR(.data) + SIZEOF(.data)) { - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - } > IRAM - PROVIDE(__ramtext_start = LOADADDR(.ramtext)); - PROVIDE(__ramtext_end = LOADADDR(.ramtext) + SIZEOF(.ramtext)); - PROVIDE(_ramtext_start = ADDR(.ramtext)); - PROVIDE(_ramtext_end = ADDR(.ramtext) + SIZEOF(.ramtext)); - - /* uninitialized data */ - .bss (NOLOAD) : { - . = ALIGN(4); - _sbss = ABSOLUTE(.); - *(.bss) - _ebss = ABSOLUTE(.); - . = ALIGN(4); - } > IRAM - PROVIDE(__bss_start = ADDR(.bss)); - PROVIDE(__bss_end = ADDR(.bss) + SIZEOF(.bss)); - PROVIDE(_bss_start = __bss_start); - PROVIDE(_bss_end = __bss_end); - - /* end of image */ - . = ALIGN(4); - _end = .; - PROVIDE(end = .); -} diff --git a/configs/compal_e86/scripts/highram.ld b/configs/compal_e86/scripts/highram.ld deleted file mode 100644 index 429ef2b502..0000000000 --- a/configs/compal_e86/scripts/highram.ld +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Linker script for running from internal SRAM on Compal phones - * - * This script is tailored specifically to the requirements imposed - * on us by the Compal bootloader. - * - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(__start) -MEMORY -{ - -/* E86 stacked flash 32mbit flash, 4mbit sram, DBB internal 256kb SRAM */ - /* 0x800000-0x87ffff */ /* bump up because we have 32mbit instead of 16mbit */ - /* compal-loaded binary: our text, initialized data */ - LRAM (rw) : ORIGIN = 0x00800000, LENGTH = 0x00020000 - TRAM (rw) : ORIGIN = 0x00820000, LENGTH = 0x00040000 - /* compal-loaded binary: our unitialized data, stacks, heap */ - IRAM (rw) : ORIGIN = 0x00860000, LENGTH = 0x00020000 - -/* E88 NOR flash 16mbits, SRAM 256 kb, DBB has 256kb internal SRAM */ - /* 0x800000-0x83ffff */ - /* compal-loaded binary: our text, initialized data */ -/* - LRAM (rw) : ORIGIN = 0x00800000, LENGTH = 0x00020000 - TRAM (rw) : ORIGIN = 0x00820000, LENGTH = 0x00010000 -*/ - /* compal-loaded binary: our unitialized data, stacks, heap */ -/* - IRAM (rw) : ORIGIN = 0x00830000, LENGTH = 0x00010000 -*/ -} -SECTIONS -{ - . = 0x800000; - - /* romloader data section, contains passthru interrupt vectors */ - .compal.loader (NOLOAD) : { . = 0x100; } > LRAM - - /* image signature (prepended by osmocon according to phone type) */ - .compal.header (NOLOAD) : { . = 4; } > LRAM - - /* initialization code */ - . = ALIGN(4); - .text.start : { - PROVIDE(__start = .); - KEEP(*(.text.start)) - *(.text.start) - } > TRAM - - /* exception vectors from 0x80001c to 0x800034 */ - .text.exceptions 0x80001c : AT (LOADADDR(.text.start) + SIZEOF(.text.start)) { - KEEP(*(.text.exceptions)) - * (.text.exceptions) - . = ALIGN(4); - } > LRAM - PROVIDE(_exceptions = LOADADDR(.text.exceptions)); - - /* code */ - . = ALIGN(4); - .text (LOADADDR(.text.exceptions) + SIZEOF(.text.exceptions)) : - AT (LOADADDR(.text.exceptions) + SIZEOF(.text.exceptions)) { - /* regular code */ - *(.text*) - /* always-in-ram code */ - *(.ramtext*) - /* gcc voodoo */ - *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx) - . = ALIGN(4); - } > TRAM - PROVIDE(_text_start = LOADADDR(.text)); - PROVIDE(_text_end = LOADADDR(.text) + SIZEOF(.text)); - - /* constructor pointers */ - .ctors : { - /* ctor count */ - LONG(SIZEOF(.ctors) / 4 - 2) - /* ctor pointers */ - KEEP(*(SORT(.ctors))) - /* end of list */ - LONG(0) - } > TRAM - PROVIDE(_ctor_start = LOADADDR(.ctors)); - PROVIDE(_ctor_end = LOADADDR(.ctors) + SIZEOF(.ctors)); - - /* destructor pointers */ - .dtors : { - /* dtor count */ - LONG(SIZEOF(.dtors) / 4 - 2) - /* dtor pointers */ - KEEP(*(SORT(.dtors))) - /* end of list */ - LONG(0) - } > TRAM - PROVIDE(_dtor_start = LOADADDR(.dtors)); - PROVIDE(_dtor_end = LOADADDR(.dtors) + SIZEOF(.dtors)); - - /* read-only data */ - . = ALIGN(4); - .rodata : { - *(.rodata*) - } > TRAM - PROVIDE(_rodata_start = LOADADDR(.rodata)); - PROVIDE(_rodata_end = LOADADDR(.rodata) + SIZEOF(.rodata)); - - /* initialized data */ - . = ALIGN(4); - .data : { - *(.data) - } > TRAM - PROVIDE(_data_start = LOADADDR(.data)); - PROVIDE(_data_end = LOADADDR(.data) + SIZEOF(.data)); - - /* pic offset tables */ - . = ALIGN(4); - .got : { - *(.got) - *(.got.plt) *(.igot.plt) *(.got) *(.igot) - } > TRAM - PROVIDE(_got_start = LOADADDR(.got)); - PROVIDE(_got_end = LOADADDR(.got) + SIZEOF(.got)); - - /* uninitialized data */ - .bss (NOLOAD) : { - . = ALIGN(4); - __bss_start = .; - _sbss = ABSOLUTE(.); - *(.bss) - _ebss = ABSOLUTE(.); - } > IRAM - . = ALIGN(4); - __bss_end = .; - PROVIDE(_bss_start = __bss_start); - PROVIDE(_bss_end = __bss_end); - - /* end of image */ - . = ALIGN(4); - _end = .; - PROVIDE(end = .); -} diff --git a/configs/compal_e86/src/Makefile b/configs/compal_e86/src/Makefile deleted file mode 100644 index b8f7e5dc8a..0000000000 --- a/configs/compal_e86/src/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -############################################################################ -# configs/compal_e86/src/Makefile -# -# Copyright (C) 2007, 2008, 2013, 2015 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Copyright (C) 2011 Stefan Richter. All rights reserved. -# Author: Stefan Richter -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - --include $(TOPDIR)/Make.defs - -ASRCS = -CSRCS = boot.c - -include $(TOPDIR)/configs/Board.mk diff --git a/configs/compal_e86/src/boot.c b/configs/compal_e86/src/boot.c deleted file mode 100644 index 8c214a004c..0000000000 --- a/configs/compal_e86/src/boot.c +++ /dev/null @@ -1,75 +0,0 @@ -/**************************************************************************** - * configs/compal_e86/boot.c - * - * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_app_initialize - * - * Description: - * Perform architecture specific initialization - * - * Input Parameters: - * arg - The boardctl() argument is passed to the board_app_initialize() - * implementation without modification. The argument has no - * meaning to NuttX; the meaning of the argument is a contract - * between the board-specific initalization logic and the the - * matching application logic. The value cold be such things as a - * mode enumeration value, a set of DIP switch switch settings, a - * pointer to configuration data read from a file or serial FLASH, - * or whatever you would like to do with it. Every implementation - * should accept zero/NULL as a default configuration. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_LIB_BOARDCTL -int board_app_initialize(uintptr_t arg) -{ - return 0; -} -#endif /* CONFIG_LIB_BOARDCTL */ diff --git a/configs/compal_e88/Kconfig b/configs/compal_e88/Kconfig deleted file mode 100644 index f72f3c094c..0000000000 --- a/configs/compal_e88/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# diff --git a/configs/compal_e88/README.txt b/configs/compal_e88/README.txt deleted file mode 100644 index 1dfefc7466..0000000000 --- a/configs/compal_e88/README.txt +++ /dev/null @@ -1,52 +0,0 @@ -compal_e88 -========== - -This directory contains the board support for compal e88 phones. - -This port is based on patches contributed by Denis Carikli for both the -compal e99 and e88. At the time of initial check-in, the following phones -were tested: - -* Motorola c155 (compal e99) with the compalram and highram configuration -* Motorola W220 (compal e88) -* The openmoko freerunner baseband(compal e88) - -The patches were made by Alan Carvalho de Assis and Denis Carikli using -the Stefan Richter's patches that can be found here: - -http://cgit.osmocom.org/cgit/nuttx-bb/log/?h=lputt%2Ftesting - -Osmocom-BB Dependencies and Sercomm -=================================== - -The build environment assumes that you have the osmocom-bb project -directory at same level as the nuttx project: - - |- nuttx - |- apps - `- osmocom-bb - -If you attempt to build this configuration without osmocom-bb, and that -you added support for sercomm in your configuration(CONFIG_SERCOMM_CONSOLE=y) -you will get compilation errors in drivers/sercomm due to header files that -are needed from the osmocom-bb directory. - -By default, NuttX will not use sercomm (HDLC protocol) to communicate with -the host system. Sercomm is the transport used by osmocom-bb that runs on top -of serial. See http://bb.osmocom.org/trac/wiki/nuttx-bb/run for detailed -the usage of nuttx with sercomm. - -Loading NuttX -============= - -The osmocom-bb wiki describes how to load NuttX. See -http://bb.osmocom.org/trac/wiki/nuttx-bb for detailed information. -The way that nuttx is loaded depends on the configuration (highram/compalram) -and phone: - -o compalram is for the ramloader(for phone having a bootloader on flash) -o highram is for phones having the romloader(if the phone has a bootrom) - or for loading in the ram trough a special loader(loaded first on ram - by talking to the ramloader) when having a ramloader(which can only - load 64k). - diff --git a/configs/compal_e88/include/board.h b/configs/compal_e88/include/board.h deleted file mode 100644 index 5855614184..0000000000 --- a/configs/compal_e88/include/board.h +++ /dev/null @@ -1,6 +0,0 @@ -/**************************************************************************** - * arch/board.h - * - * Supposed to be empty - * - ****************************************************************************/ diff --git a/configs/compal_e88/nsh_highram/Make.defs b/configs/compal_e88/nsh_highram/Make.defs deleted file mode 100644 index e9c3e23943..0000000000 --- a/configs/compal_e88/nsh_highram/Make.defs +++ /dev/null @@ -1,124 +0,0 @@ -############################################################################ -# configs/compal_e88/nsh_highram/Make.defs -# -# Copyright (C) 2013 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk -include ${TOPDIR}/arch/arm/src/arm/Toolchain.defs - -LDSCRIPT = ld.script - -ifeq ($(WINTOOL),y) - # Windows-native toolchains - ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" - ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" - ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" -else - # Linux/Cygwin-native toolchain - ARCHINCLUDES = -I. -isystem $(TOPDIR)/include - ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx - ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) -endif - -CC = $(CROSSDEV)gcc -CXX = $(CROSSDEV)g++ -CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld -AR = $(ARCROSSDEV)ar rcs -NM = $(ARCROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} -ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION = -g -endif - -ifneq ($(CONFIG_DEBUG_NOOPT),y) - ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer -endif - -ARCHCFLAGS = -fno-builtin -ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -ARCHWARNINGSXX = -Wall -Wshadow -Wundef -ARCHDEFINES = -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -AFLAGS = $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -ASMEXT = .S -OBJEXT = .o -LIBEXT = .a -EXEEXT = - -ifneq ($(CROSSDEV),arm-nuttx-elf-) - LDFLAGS += -nostartfiles -nodefaultlibs -endif -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - LDFLAGS += -g -endif - - -HOSTCC = gcc -HOSTINCLUDES = -I. -HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe -HOSTLDFLAGS = -ifeq ($(CONFIG_HOST_WINDOWS),y) - HOSTEXEEXT = .exe -else - HOSTEXEEXT = -endif - -ifeq ($(WINTOOL),y) - # Windows-native host tools - DIRLINK = $(TOPDIR)/tools/copydir.sh - DIRUNLINK = $(TOPDIR)/tools/unlink.sh - MKDEP = $(TOPDIR)/tools/mkwindeps.sh -else - # Linux/Cygwin-native host tools - MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) -endif - diff --git a/configs/compal_e88/nsh_highram/defconfig b/configs/compal_e88/nsh_highram/defconfig deleted file mode 100644 index 3672faf14d..0000000000 --- a/configs/compal_e88/nsh_highram/defconfig +++ /dev/null @@ -1,808 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Nuttx/ Configuration -# - -# -# Build Setup -# -# CONFIG_EXPERIMENTAL is not set -# CONFIG_DEFAULT_SMALL is not set -CONFIG_HOST_LINUX=y -# CONFIG_HOST_OSX is not set -# CONFIG_HOST_WINDOWS is not set -# CONFIG_HOST_OTHER is not set - -# -# Build Configuration -# -# CONFIG_APPS_DIR="../apps" -CONFIG_BUILD_FLAT=y -# CONFIG_BUILD_2PASS is not set - -# -# Binary Output Formats -# -# CONFIG_RRLOAD_BINARY is not set -# CONFIG_INTELHEX_BINARY is not set -# CONFIG_MOTOROLA_SREC is not set -CONFIG_RAW_BINARY=y -# CONFIG_UBOOT_UIMAGE is not set - -# -# Customize Header Files -# -# CONFIG_ARCH_STDINT_H is not set -# CONFIG_ARCH_STDBOOL_H is not set -# CONFIG_ARCH_MATH_H is not set -# CONFIG_ARCH_FLOAT_H is not set -# CONFIG_ARCH_STDARG_H is not set -# CONFIG_ARCH_DEBUG_H is not set - -# -# Debug Options -# -CONFIG_DEBUG_ALERT=y -# CONFIG_DEBUG_FEATURES is not set -CONFIG_ARCH_HAVE_STACKCHECK=y -# CONFIG_STACK_COLORATION is not set -# CONFIG_ARCH_HAVE_HEAPCHECK is not set -# CONFIG_DEBUG_SYMBOLS is not set -CONFIG_ARCH_HAVE_CUSTOMOPT=y -# CONFIG_DEBUG_NOOPT is not set -# CONFIG_DEBUG_CUSTOMOPT is not set -CONFIG_DEBUG_FULLOPT=y - -# -# System Type -# -CONFIG_ARCH_ARM=y -# CONFIG_ARCH_AVR is not set -# CONFIG_ARCH_HC is not set -# CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_SIM is not set -# CONFIG_ARCH_X86 is not set -# CONFIG_ARCH_Z16 is not set -# CONFIG_ARCH_Z80 is not set -CONFIG_ARCH="arm" - -# -# ARM Options -# -# CONFIG_ARCH_CHIP_A1X is not set -# CONFIG_ARCH_CHIP_C5471 is not set -CONFIG_ARCH_CHIP_CALYPSO=y -# CONFIG_ARCH_CHIP_DM320 is not set -# CONFIG_ARCH_CHIP_EFM32 is not set -# CONFIG_ARCH_CHIP_IMX1 is not set -# CONFIG_ARCH_CHIP_IMX6 is not set -# CONFIG_ARCH_CHIP_KINETIS is not set -# CONFIG_ARCH_CHIP_KL is not set -# CONFIG_ARCH_CHIP_LM is not set -# CONFIG_ARCH_CHIP_TIVA is not set -# CONFIG_ARCH_CHIP_LPC11XX is not set -# CONFIG_ARCH_CHIP_LPC17XX is not set -# CONFIG_ARCH_CHIP_LPC214X is not set -# CONFIG_ARCH_CHIP_LPC2378 is not set -# CONFIG_ARCH_CHIP_LPC31XX is not set -# CONFIG_ARCH_CHIP_LPC43XX is not set -# CONFIG_ARCH_CHIP_NUC1XX is not set -# CONFIG_ARCH_CHIP_SAMA5 is not set -# CONFIG_ARCH_CHIP_SAMD is not set -# CONFIG_ARCH_CHIP_SAML is not set -# CONFIG_ARCH_CHIP_SAM34 is not set -# CONFIG_ARCH_CHIP_SAMV7 is not set -# CONFIG_ARCH_CHIP_STM32 is not set -# CONFIG_ARCH_CHIP_STM32F7 is not set -# CONFIG_ARCH_CHIP_STM32L4 is not set -# CONFIG_ARCH_CHIP_STR71X is not set -# CONFIG_ARCH_CHIP_TMS570 is not set -# CONFIG_ARCH_CHIP_MOXART is not set -CONFIG_ARCH_ARM7TDMI=y -# CONFIG_ARCH_ARM926EJS is not set -# CONFIG_ARCH_ARM920T is not set -# CONFIG_ARCH_CORTEXM0 is not set -# CONFIG_ARCH_CORTEXM3 is not set -# CONFIG_ARCH_CORTEXM4 is not set -# CONFIG_ARCH_CORTEXM7 is not set -# CONFIG_ARCH_CORTEXA5 is not set -# CONFIG_ARCH_CORTEXA8 is not set -# CONFIG_ARCH_CORTEXA9 is not set -# CONFIG_ARCH_CORTEXR4 is not set -# CONFIG_ARCH_CORTEXR4F is not set -# CONFIG_ARCH_CORTEXR5 is not set -# CONFIG_ARCH_CORTEX5F is not set -# CONFIG_ARCH_CORTEXR7 is not set -# CONFIG_ARCH_CORTEXR7F is not set -CONFIG_ARCH_FAMILY="arm" -CONFIG_ARCH_CHIP="calypso" -# CONFIG_ARM_TOOLCHAIN_IAR is not set -# CONFIG_ARM_TOOLCHAIN_GNU is not set -# CONFIG_ARCH_HAVE_FPU is not set -# CONFIG_ARCH_HAVE_DPFPU is not set -# CONFIG_ARCH_HAVE_TRUSTZONE is not set -# CONFIG_ARM_HAVE_MPU_UNIFIED is not set -CONFIG_ARCH_HAVE_LOWVECTORS=y -# CONFIG_ARCH_LOWVECTORS is not set - -# -# ARM Configuration Options -# -# CONFIG_ARM_TOOLCHAIN_BUILDROOT is not set -# CONFIG_ARM_TOOLCHAIN_CODESOURCERYL is not set -CONFIG_ARM_TOOLCHAIN_GNU_EABIL=y -# CONFIG_ARM_TOOLCHAIN_GNU_OABI is not set -CONFIG_UART_IRDA_BAUD=115200 -CONFIG_UART_IRDA_PARITY=0 -CONFIG_UART_IRDA_BITS=8 -CONFIG_UART_IRDA_2STOP=0 -CONFIG_UART_IRDA_RXBUFSIZE=256 -CONFIG_UART_IRDA_TXBUFSIZE=256 -CONFIG_UART_MODEM_BAUD=115200 -CONFIG_UART_MODEM_PARITY=0 -CONFIG_UART_MODEM_BITS=8 -CONFIG_UART_MODEM_2STOP=0 -CONFIG_UART_MODEM_RXBUFSIZE=256 -CONFIG_UART_MODEM_TXBUFSIZE=256 - -# -# Calypso Configuration Options -# - -# -# Modem UART Configuration -# -# CONFIG_UART_MODEM_HWFLOWCONTROL is not set - -# -# IrDA UART Configuration -# -# CONFIG_UART_IRDA_HWFLOWCONTROL is not set -# CONFIG_USE_SERCOMM_CONSOLE is not set -# CONFIG_SERIAL_MODEM_CONSOLE is not set -# CONFIG_SERIAL_IRDA_CONSOLE is not set -CONFIG_SERIAL_CONSOLE_NONE=y - -# -# Architecture Options -# -# CONFIG_ARCH_NOINTC is not set -# CONFIG_ARCH_VECNOTIRQ is not set -# CONFIG_ARCH_DMA is not set -# CONFIG_ARCH_HAVE_IRQPRIO is not set -# CONFIG_ARCH_L2CACHE is not set -# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set -# CONFIG_ARCH_HAVE_ADDRENV is not set -# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set -# CONFIG_ARCH_HAVE_MULTICPU is not set -CONFIG_ARCH_HAVE_VFORK=y -# CONFIG_ARCH_HAVE_MMU is not set -# CONFIG_ARCH_HAVE_MPU is not set -# CONFIG_ARCH_NAND_HWECC is not set -# CONFIG_ARCH_HAVE_EXTCLK is not set -CONFIG_ARCH_HAVE_POWEROFF=y -# CONFIG_ARCH_HAVE_RESET is not set -CONFIG_ARCH_STACKDUMP=y -# CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_IDLE_CUSTOM is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set -# CONFIG_ARCH_HAVE_RAMVECTORS is not set - -# -# Board Settings -# -CONFIG_BOARD_LOOPSPERMSEC=1250 -# CONFIG_ARCH_CALIBRATION is not set - -# -# Interrupt options -# -CONFIG_ARCH_HAVE_INTERRUPTSTACK=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set - -# -# Boot options -# -# CONFIG_BOOT_RUNFROMEXTSRAM is not set -# CONFIG_BOOT_RUNFROMFLASH is not set -CONFIG_BOOT_RUNFROMISRAM=y -# CONFIG_BOOT_RUNFROMSDRAM is not set -# CONFIG_BOOT_COPYTORAM is not set - -# -# Boot Memory Configuration -# -CONFIG_RAM_START=0 -CONFIG_RAM_SIZE=8650752 -# CONFIG_ARCH_HAVE_SDRAM is not set - -# -# Board Selection -# -# CONFIG_ARCH_BOARD_COMPALE86 is not set -CONFIG_ARCH_BOARD_COMPALE88=y -# CONFIG_ARCH_BOARD_COMPALE99 is not set -# CONFIG_ARCH_BOARD_PIRELLI_DPL10 is not set -# CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD="compal_e88" - -# -# Common Board Options -# -CONFIG_NSH_MMCSDMINOR=0 - -# -# Board-Specific Options -# -CONFIG_LIB_BOARDCTL=y -CONFIG_BOARDCTL_POWEROFF=y -# CONFIG_BOARDCTL_UNIQUEID is not set -# CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_GRAPHICS is not set -# CONFIG_BOARDCTL_IOCTL is not set - -# -# RTOS Features -# -CONFIG_DISABLE_OS_API=y -# CONFIG_DISABLE_POSIX_TIMERS is not set -# CONFIG_DISABLE_PTHREAD is not set -# CONFIG_DISABLE_SIGNALS is not set -CONFIG_DISABLE_MQUEUE=y -# CONFIG_DISABLE_ENVIRON is not set - -# -# Clocks and Timers -# -CONFIG_USEC_PER_TICK=10000 -# CONFIG_SYSTEM_TIME64 is not set -# CONFIG_CLOCK_MONOTONIC is not set -# CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2007 -CONFIG_START_MONTH=2 -CONFIG_START_DAY=13 -CONFIG_MAX_WDOGPARMS=4 -CONFIG_PREALLOC_WDOGS=8 -CONFIG_WDOG_INTRESERVE=1 -CONFIG_PREALLOC_TIMERS=8 - -# -# Tasks and Scheduling -# -# CONFIG_INIT_NONE is not set -CONFIG_INIT_ENTRYPOINT=y -# CONFIG_INIT_FILEPATH is not set -CONFIG_USER_ENTRYPOINT="nsh_main" -CONFIG_RR_INTERVAL=200 -# CONFIG_SCHED_SPORADIC is not set -CONFIG_TASK_NAME_SIZE=0 -CONFIG_MAX_TASKS=16 -# CONFIG_SCHED_HAVE_PARENT is not set -# CONFIG_SCHED_WAITPID is not set - -# -# Pthread Options -# -# CONFIG_MUTEX_TYPES is not set -CONFIG_NPTHREAD_KEYS=4 - -# -# Performance Monitoring -# -# CONFIG_SCHED_CPULOAD is not set -# CONFIG_SCHED_INSTRUMENTATION is not set - -# -# Files and I/O -# -CONFIG_DEV_CONSOLE=y -# CONFIG_FDCLONE_DISABLE is not set -# CONFIG_FDCLONE_STDIO is not set -CONFIG_SDCLONE_DISABLE=y -CONFIG_NFILE_DESCRIPTORS=8 -CONFIG_NFILE_STREAMS=8 -CONFIG_NAME_MAX=32 -# CONFIG_PRIORITY_INHERITANCE is not set - -# -# RTOS hooks -# -# CONFIG_BOARD_INITIALIZE is not set -# CONFIG_SCHED_STARTHOOK is not set -# CONFIG_SCHED_ATEXIT is not set -# CONFIG_SCHED_ONEXIT is not set - -# -# Signal Numbers -# -CONFIG_SIG_SIGUSR1=1 -CONFIG_SIG_SIGUSR2=2 -CONFIG_SIG_SIGALARM=3 -CONFIG_SIG_SIGCONDTIMEDOUT=16 -# CONFIG_MODULE is not set - -# -# Work queue support -# -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set -# CONFIG_SCHED_LPWORK is not set - -# -# Stack and heap information -# -CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_USERMAIN_STACKSIZE=4096 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=4096 -# CONFIG_LIB_SYSCALL is not set - -# -# Device Drivers -# -CONFIG_DISABLE_POLL=y -CONFIG_DEV_NULL=y -# CONFIG_DEV_ZERO is not set -# CONFIG_DEV_LOOP is not set - -# -# Buffering -# -# CONFIG_DRVR_WRITEBUFFER is not set -# CONFIG_DRVR_READAHEAD is not set -# CONFIG_RAMDISK is not set -# CONFIG_CAN is not set -# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set -# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set -# CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set -# CONFIG_I2C is not set -CONFIG_SPI=y -# CONFIG_SPI_SLAVE is not set -CONFIG_SPI_EXCHANGE=y -# CONFIG_SPI_CMDDATA is not set -# CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set -# CONFIG_SPI_CS_DELAY_CONTROL is not set -# CONFIG_I2S is not set - -# -# Timer Driver Support -# -# CONFIG_TIMER is not set -# CONFIG_RTC is not set -# CONFIG_WATCHDOG is not set -# CONFIG_ANALOG is not set -# CONFIG_AUDIO_DEVICES is not set -# CONFIG_VIDEO_DEVICES is not set -# CONFIG_BCH is not set -# CONFIG_INPUT is not set -# CONFIG_IOEXPANDER is not set - -# -# LCD Driver Support -# -# CONFIG_LCD is not set -# CONFIG_SLCD is not set - -# -# LED Support -# -# CONFIG_RGBLED is not set -# CONFIG_PCA9635PW is not set -# CONFIG_NCP5623C is not set -# CONFIG_MMCSD is not set -# CONFIG_MODEM is not set -# CONFIG_MTD is not set -# CONFIG_EEPROM is not set -# CONFIG_PIPES is not set -# CONFIG_PM is not set -# CONFIG_POWER is not set -# CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set -CONFIG_SERIAL=y -# CONFIG_DEV_LOWCONSOLE is not set -# CONFIG_SERIAL_REMOVABLE is not set -CONFIG_SERIAL_CONSOLE=y -# CONFIG_16550_UART is not set -# CONFIG_UART_SERIALDRIVER is not set -# CONFIG_UART0_SERIALDRIVER is not set -# CONFIG_UART1_SERIALDRIVER is not set -# CONFIG_UART2_SERIALDRIVER is not set -# CONFIG_UART3_SERIALDRIVER is not set -# CONFIG_UART4_SERIALDRIVER is not set -# CONFIG_UART5_SERIALDRIVER is not set -# CONFIG_UART6_SERIALDRIVER is not set -# CONFIG_UART7_SERIALDRIVER is not set -# CONFIG_UART8_SERIALDRIVER is not set -# CONFIG_SCI0_SERIALDRIVER is not set -# CONFIG_SCI1_SERIALDRIVER is not set -# CONFIG_USART0_SERIALDRIVER is not set -# CONFIG_USART1_SERIALDRIVER is not set -# CONFIG_USART2_SERIALDRIVER is not set -# CONFIG_USART3_SERIALDRIVER is not set -# CONFIG_USART4_SERIALDRIVER is not set -# CONFIG_USART5_SERIALDRIVER is not set -# CONFIG_USART6_SERIALDRIVER is not set -# CONFIG_USART7_SERIALDRIVER is not set -# CONFIG_USART8_SERIALDRIVER is not set -CONFIG_OTHER_UART_SERIALDRIVER=y -CONFIG_MCU_SERIAL=y -# CONFIG_STANDARD_SERIAL is not set -# CONFIG_SERIAL_IFLOWCONTROL is not set -# CONFIG_SERIAL_OFLOWCONTROL is not set -# CONFIG_SERIAL_DMA is not set -# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set -CONFIG_OTHER_SERIAL_CONSOLE=y -# CONFIG_NO_SERIAL_CONSOLE is not set -# CONFIG_USBDEV is not set -# CONFIG_USBHOST is not set -# CONFIG_DRIVERS_WIRELESS is not set - -# -# System Logging -# -# CONFIG_ARCH_SYSLOG is not set -# CONFIG_RAMLOG is not set -# CONFIG_SYSLOG_INTBUFFER is not set -# CONFIG_SYSLOG_TIMESTAMP is not set -CONFIG_SYSLOG_SERIAL_CONSOLE=y -# CONFIG_SYSLOG_CHAR is not set -CONFIG_SYSLOG_CONSOLE=y -# CONFIG_SYSLOG_NONE is not set -# CONFIG_SYSLOG_FILE is not set - -# -# Networking Support -# -# CONFIG_ARCH_HAVE_NET is not set -# CONFIG_ARCH_HAVE_PHY is not set -# CONFIG_NET is not set - -# -# Crypto API -# -# CONFIG_CRYPTO is not set - -# -# File Systems -# - -# -# File system configuration -# -# CONFIG_DISABLE_MOUNTPOINT is not set -# CONFIG_FS_AUTOMOUNTER is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_FS_READABLE is not set -# CONFIG_FS_WRITABLE is not set -# CONFIG_FS_NAMED_SEMAPHORES is not set -# CONFIG_FS_RAMMAP is not set -# CONFIG_FS_FAT is not set -# CONFIG_FS_NXFFS is not set -# CONFIG_FS_ROMFS is not set -# CONFIG_FS_TMPFS is not set -# CONFIG_FS_SMARTFS is not set -# CONFIG_FS_BINFS is not set -# CONFIG_FS_PROCFS is not set -# CONFIG_FS_UNIONFS is not set - -# -# Graphics Support -# -# CONFIG_NX is not set - -# -# Memory Management -# -# CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=1 -CONFIG_ARCH_HAVE_HEAP2=y -CONFIG_HEAP2_BASE=0x00000000 -CONFIG_HEAP2_SIZE=0 -# CONFIG_GRAN is not set - -# -# Audio Support -# -# CONFIG_AUDIO is not set - -# -# Wireless Support -# - -# -# Binary Loader -# -# CONFIG_BINFMT_DISABLE is not set -# CONFIG_BINFMT_EXEPATH is not set -# CONFIG_NXFLAT is not set -# CONFIG_ELF is not set -CONFIG_BUILTIN=y -# CONFIG_PIC is not set -# CONFIG_SYMTAB_ORDEREDBYNAME is not set - -# -# Library Routines -# - -# -# Standard C Library Options -# -CONFIG_STDIO_BUFFER_SIZE=64 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=2 -CONFIG_LIB_HOMEDIR="/" -# CONFIG_LIBM is not set -# CONFIG_NOPRINTF_FIELDWIDTH is not set -# CONFIG_LIBC_FLOATINGPOINT is not set -CONFIG_LIBC_LONG_LONG=y -# CONFIG_LIBC_IOCTL_VARIADIC is not set -CONFIG_LIB_RAND_ORDER=1 -# CONFIG_EOL_IS_CR is not set -# CONFIG_EOL_IS_LF is not set -# CONFIG_EOL_IS_BOTH_CRLF is not set -CONFIG_EOL_IS_EITHER_CRLF=y -# CONFIG_LIBC_EXECFUNCS is not set -CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 -# CONFIG_LIBC_STRERROR is not set -# CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_ARCH_LOWPUTC=y -# CONFIG_LIBC_LOCALTIME is not set -# CONFIG_TIME_EXTENDED is not set -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set -# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set -CONFIG_ARCH_HAVE_TLS=y -# CONFIG_TLS is not set -# CONFIG_LIBC_NETDB is not set - -# -# Non-standard Library Support -# -# CONFIG_LIB_CRC64_FAST is not set -# CONFIG_LIB_KBDCODEC is not set -# CONFIG_LIB_SLCDCODEC is not set - -# -# Basic CXX Support -# -# CONFIG_C99_BOOL8 is not set -# CONFIG_HAVE_CXX is not set - -# -# Application Configuration -# - -# -# Built-In Applications -# -CONFIG_BUILTIN_PROXY_STACKSIZE=1024 - -# -# CAN Utilities -# - -# -# Examples -# -# CONFIG_EXAMPLES_CHAT is not set -# CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set -# CONFIG_EXAMPLES_DHCPD is not set -# CONFIG_EXAMPLES_ELF is not set -# CONFIG_EXAMPLES_FTPC is not set -# CONFIG_EXAMPLES_FTPD is not set -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_HELLO_PRIORITY=100 -CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 -# CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_IGMP is not set -# CONFIG_EXAMPLES_JSON is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set -# CONFIG_EXAMPLES_MEDIA is not set -# CONFIG_EXAMPLES_MM is not set -# CONFIG_EXAMPLES_MODBUS is not set -# CONFIG_EXAMPLES_MOUNT is not set -# CONFIG_EXAMPLES_NRF24L01TERM is not set -CONFIG_EXAMPLES_NSH=y -# CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXFFS is not set -# CONFIG_EXAMPLES_NXHELLO is not set -# CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NXLINES is not set -# CONFIG_EXAMPLES_NXTERM is not set -# CONFIG_EXAMPLES_NXTEXT is not set -# CONFIG_EXAMPLES_OSTEST is not set -# CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_PPPD is not set -# CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_SENDMAIL is not set -# CONFIG_EXAMPLES_SERIALBLASTER is not set -# CONFIG_EXAMPLES_SERIALRX is not set -# CONFIG_EXAMPLES_SERLOOP is not set -# CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART is not set -# CONFIG_EXAMPLES_SMART_TEST is not set -# CONFIG_EXAMPLES_SMP is not set -# CONFIG_EXAMPLES_TCPECHO is not set -# CONFIG_EXAMPLES_TELNETD is not set -# CONFIG_EXAMPLES_TIFF is not set -# CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_USBSERIAL is not set -# CONFIG_EXAMPLES_USBTERM is not set -# CONFIG_EXAMPLES_WATCHDOG is not set -# CONFIG_EXAMPLES_WEBSERVER is not set - -# -# File System Utilities -# -# CONFIG_FSUTILS_INIFILE is not set - -# -# GPS Utilities -# -# CONFIG_GPSUTILS_MINMEA_LIB is not set - -# -# Graphics Support -# -# CONFIG_TIFF is not set -# CONFIG_GRAPHICS_TRAVELER is not set - -# -# Interpreters -# -# CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_MICROPYTHON is not set -# CONFIG_INTERPRETERS_PCODE is not set - -# -# FreeModBus -# -# CONFIG_MODBUS is not set - -# -# Network Utilities -# -# CONFIG_NETUTILS_CODECS is not set -# CONFIG_NETUTILS_ESP8266 is not set -# CONFIG_NETUTILS_FTPC is not set -# CONFIG_NETUTILS_JSON is not set -# CONFIG_NETUTILS_SMTP is not set - -# -# NSH Library -# -CONFIG_NSH_LIBRARY=y -# CONFIG_NSH_MOTD is not set - -# -# Command Line Configuration -# -CONFIG_NSH_READLINE=y -# CONFIG_NSH_CLE is not set -CONFIG_NSH_LINELEN=64 -# CONFIG_NSH_DISABLE_SEMICOLON is not set -# CONFIG_NSH_CMDPARMS is not set -CONFIG_NSH_MAXARGUMENTS=6 -# CONFIG_NSH_ARGCAT is not set -CONFIG_NSH_NESTDEPTH=3 -# CONFIG_NSH_DISABLEBG is not set -CONFIG_NSH_BUILTIN_APPS=y - -# -# Disable Individual commands -# -# CONFIG_NSH_DISABLE_ADDROUTE is not set -# CONFIG_NSH_DISABLE_BASENAME is not set -# CONFIG_NSH_DISABLE_CAT is not set -# CONFIG_NSH_DISABLE_CD is not set -# CONFIG_NSH_DISABLE_CP is not set -# CONFIG_NSH_DISABLE_CMP is not set -CONFIG_NSH_DISABLE_DATE=y -# CONFIG_NSH_DISABLE_DD is not set -# CONFIG_NSH_DISABLE_DF is not set -# CONFIG_NSH_DISABLE_DELROUTE is not set -# CONFIG_NSH_DISABLE_DIRNAME is not set -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HELP is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -CONFIG_NSH_DISABLE_IFUPDOWN=y -# CONFIG_NSH_DISABLE_KILL is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -CONFIG_NSH_DISABLE_LOSMART=y -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_MB is not set -# CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_MH is not set -# CONFIG_NSH_DISABLE_MOUNT is not set -# CONFIG_NSH_DISABLE_MV is not set -# CONFIG_NSH_DISABLE_MW is not set -# CONFIG_NSH_DISABLE_POWEROFF is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_PWD is not set -# CONFIG_NSH_DISABLE_RM is not set -# CONFIG_NSH_DISABLE_RMDIR is not set -# CONFIG_NSH_DISABLE_SET is not set -# CONFIG_NSH_DISABLE_SH is not set -CONFIG_NSH_DISABLE_SHUTDOWN=y -# CONFIG_NSH_DISABLE_SLEEP is not set -# CONFIG_NSH_DISABLE_TIME is not set -# CONFIG_NSH_DISABLE_TEST is not set -# CONFIG_NSH_DISABLE_UMOUNT is not set -# CONFIG_NSH_DISABLE_UNAME is not set -# CONFIG_NSH_DISABLE_UNSET is not set -# CONFIG_NSH_DISABLE_USLEEP is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set - -# -# Configure Command Options -# -CONFIG_NSH_CMDOPT_DF_H=y -CONFIG_NSH_CODECS_BUFSIZE=128 -CONFIG_NSH_CMDOPT_HEXDUMP=y -CONFIG_NSH_FILEIOSIZE=512 - -# -# Scripting Support -# -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_ITEF is not set -# CONFIG_NSH_DISABLE_LOOPS is not set - -# -# Console Configuration -# -CONFIG_NSH_CONSOLE=y -# CONFIG_NSH_ALTCONDEV is not set -# CONFIG_NSH_ARCHINIT is not set -# CONFIG_NSH_LOGIN is not set -# CONFIG_NSH_CONSOLE_LOGIN is not set - -# -# NxWidgets/NxWM -# - -# -# Platform-specific Support -# -# CONFIG_PLATFORM_CONFIGDATA is not set - -# -# System Libraries and NSH Add-Ons -# -# CONFIG_SYSTEM_CLE is not set -# CONFIG_SYSTEM_CUTERM is not set -# CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set -# CONFIG_SYSTEM_HEXED is not set -# CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_RAMTEST is not set -CONFIG_READLINE_HAVE_EXTMATCH=y -CONFIG_SYSTEM_READLINE=y -CONFIG_READLINE_ECHO=y -# CONFIG_READLINE_TABCOMPLETION is not set -# CONFIG_READLINE_CMD_HISTORY is not set -# CONFIG_SYSTEM_SUDOKU is not set -# CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_VI is not set -# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/compal_e88/nsh_highram/setenv.sh b/configs/compal_e88/nsh_highram/setenv.sh deleted file mode 100755 index 0693ede0ac..0000000000 --- a/configs/compal_e88/nsh_highram/setenv.sh +++ /dev/null @@ -1,46 +0,0 @@ -#!/bin/bash -# c5471evm/nsh/setenv.sh -# -# Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if [ "$(basename $0)" = "setenv.sh" ] ; then - echo "You must source this script, not run it!" 1>&2 - exit 1 -fi - -if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi - -WD=`pwd` -export BUILDROOT_BIN=${WD}/../buildroot/build_arm_nofpu/staging_dir/bin -export PATH=${BUILDROOT_BIN}:/sbin:/usr/sbin:${PATH_ORIG} - -echo "PATH : ${PATH}" diff --git a/configs/compal_e88/scripts/ld.script b/configs/compal_e88/scripts/ld.script deleted file mode 100644 index 35fa847284..0000000000 --- a/configs/compal_e88/scripts/ld.script +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Linker script for running from internal SRAM on Compal phones - * - * This script is tailored specifically to the requirements imposed - * on us by the Compal bootloader. - * - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(__start) -MEMORY -{ - /* 0x800000-0x83ffff */ - /* compal-loaded binary: our text, initialized data */ - LRAM (rw) : ORIGIN = 0x00800000, LENGTH = 0x00020000 - TRAM (rw) : ORIGIN = 0x00820000, LENGTH = 0x00010000 - /* compal-loaded binary: our unitialized data, stacks, heap */ - IRAM (rw) : ORIGIN = 0x00830000, LENGTH = 0x00010000 -} -SECTIONS -{ - . = 0x800000; - - /* romloader data section, contains passthru interrupt vectors */ - .compal.loader (NOLOAD) : { . = 0x100; } > LRAM - - /* image signature (prepended by osmocon according to phone type) */ - .compal.header (NOLOAD) : { . = 4; } > LRAM - - /* initialization code */ - . = ALIGN(4); - .text.start : { - PROVIDE(__start = .); - KEEP(*(.text.start)) - *(.text.start) - } > TRAM - - /* exception vectors from 0x80001c to 0x800034 */ - .text.exceptions 0x80001c : AT (LOADADDR(.text.start) + SIZEOF(.text.start)) { - KEEP(*(.text.exceptions)) - * (.text.exceptions) - . = ALIGN(4); - } > LRAM - PROVIDE(_exceptions = LOADADDR(.text.exceptions)); - - /* code */ - . = ALIGN(4); - .text (LOADADDR(.text.exceptions) + SIZEOF(.text.exceptions)) : - AT (LOADADDR(.text.exceptions) + SIZEOF(.text.exceptions)) { - /* regular code */ - *(.text*) - /* always-in-ram code */ - *(.ramtext*) - /* gcc voodoo */ - *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx) - . = ALIGN(4); - } > TRAM - PROVIDE(_text_start = LOADADDR(.text)); - PROVIDE(_text_end = LOADADDR(.text) + SIZEOF(.text)); - - /* constructor pointers */ - .ctors : { - /* ctor count */ - LONG(SIZEOF(.ctors) / 4 - 2) - /* ctor pointers */ - KEEP(*(SORT(.ctors))) - /* end of list */ - LONG(0) - } > TRAM - PROVIDE(_ctor_start = LOADADDR(.ctors)); - PROVIDE(_ctor_end = LOADADDR(.ctors) + SIZEOF(.ctors)); - - /* destructor pointers */ - .dtors : { - /* dtor count */ - LONG(SIZEOF(.dtors) / 4 - 2) - /* dtor pointers */ - KEEP(*(SORT(.dtors))) - /* end of list */ - LONG(0) - } > TRAM - PROVIDE(_dtor_start = LOADADDR(.dtors)); - PROVIDE(_dtor_end = LOADADDR(.dtors) + SIZEOF(.dtors)); - - /* read-only data */ - . = ALIGN(4); - .rodata : { - *(.rodata*) - } > TRAM - PROVIDE(_rodata_start = LOADADDR(.rodata)); - PROVIDE(_rodata_end = LOADADDR(.rodata) + SIZEOF(.rodata)); - - /* initialized data */ - . = ALIGN(4); - .data : { - *(.data) - } > TRAM - PROVIDE(_data_start = LOADADDR(.data)); - PROVIDE(_data_end = LOADADDR(.data) + SIZEOF(.data)); - - /* pic offset tables */ - . = ALIGN(4); - .got : { - *(.got) - *(.got.plt) *(.igot.plt) *(.got) *(.igot) - } > TRAM - PROVIDE(_got_start = LOADADDR(.got)); - PROVIDE(_got_end = LOADADDR(.got) + SIZEOF(.got)); - - /* uninitialized data */ - .bss (NOLOAD) : { - . = ALIGN(4); - __bss_start = .; - _sbss = ABSOLUTE(.); - *(.bss) - _ebss = ABSOLUTE(.); - } > IRAM - . = ALIGN(4); - __bss_end = .; - PROVIDE(_bss_start = __bss_start); - PROVIDE(_bss_end = __bss_end); - - /* end of image */ - . = ALIGN(4); - _end = .; - PROVIDE(end = .); -} diff --git a/configs/compal_e88/src/.gitignore b/configs/compal_e88/src/.gitignore deleted file mode 100644 index 726d936e1e..0000000000 --- a/configs/compal_e88/src/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/.depend -/Make.dep diff --git a/configs/compal_e88/src/Makefile b/configs/compal_e88/src/Makefile deleted file mode 100644 index e4703f9a0a..0000000000 --- a/configs/compal_e88/src/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -############################################################################ -# configs/compal_e88/src/Makefile -# -# Copyright (C) 2007, 2008, 2015 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Copyright (C) 2011 Stefan Richter. All rights reserved. -# Author: Stefan Richter -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - --include $(TOPDIR)/Make.defs - -ASRCS = -CSRCS = boot.c - -include $(TOPDIR)/configs/Board.mk diff --git a/configs/compal_e88/src/boot.c b/configs/compal_e88/src/boot.c deleted file mode 100644 index a3c6829227..0000000000 --- a/configs/compal_e88/src/boot.c +++ /dev/null @@ -1,75 +0,0 @@ -/**************************************************************************** - * configs/compal_e88/boot.c - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_app_initialize - * - * Description: - * Perform architecture specific initialization - * - * Input Parameters: - * arg - The boardctl() argument is passed to the board_app_initialize() - * implementation without modification. The argument has no - * meaning to NuttX; the meaning of the argument is a contract - * between the board-specific initalization logic and the the - * matching application logic. The value cold be such things as a - * mode enumeration value, a set of DIP switch switch settings, a - * pointer to configuration data read from a file or serial FLASH, - * or whatever you would like to do with it. Every implementation - * should accept zero/NULL as a default configuration. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_LIB_BOARDCTL -int board_app_initialize(uintptr_t arg) -{ - return 0; -} -#endif /* CONFIG_LIB_BOARDCTL */ diff --git a/configs/compal_e99/Kconfig b/configs/compal_e99/Kconfig deleted file mode 100644 index e7d03fb148..0000000000 --- a/configs/compal_e99/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -if ARCH_BOARD_COMPALE99 - -config COMPALE99_LCD_SSD1783 - bool "SSD1783 LCD support" - default y - select LCD - -endif diff --git a/configs/compal_e99/README.txt b/configs/compal_e99/README.txt deleted file mode 100644 index 646cdcf59c..0000000000 --- a/configs/compal_e99/README.txt +++ /dev/null @@ -1,81 +0,0 @@ -compal_e99 -========== - -This directory contains the board support for compal e99 phones. - -This port is based on patches contributed by Denis Carikli for both the -compal e99 and e88. At the time of initial check-in, the following phones -were tested: - -* Motorola c155 (compal e99) with the compalram and highram configuration -* Motorola W220 (compal e88) -* The openmoko freerunner baseband(compal e88) - -The patches were made by Alan Carvalho de Assis and Denis Carikli using -the Stefan Richter's patches that can be found here: - -http://cgit.osmocom.org/cgit/nuttx-bb/log/?h=lputt%2Ftesting - -Osmocom-BB Dependencies and Sercomm -=================================== - -The build environment assumes that you have the osmocom-bb project -directory at same level as the nuttx project: - - |- nuttx - |- apps - `- osmocom-bb - -If you attempt to build this configuration without osmocom-bb, and that -you added support for sercomm in your configuration(CONFIG_SERCOMM_CONSOLE=y) -you will get compilation errors in drivers/sercomm due to header files that -are needed from the osmocom-bb directory. - -By default, NuttX will not use sercomm (HDLC protocol) to communicate with -the host system. Sercomm is the transport used by osmocom-bb that runs on top -of serial. See http://bb.osmocom.org/trac/wiki/nuttx-bb/run for detailed -the usage of nuttx with sercomm. - -Loading NuttX -============= - -The osmocom-bb wiki describes how to load NuttX. See -http://bb.osmocom.org/trac/wiki/nuttx-bb for detailed information. -The way that nuttx is loaded depends on the configuration (highram/compalram) -and phone: - -o compalram is for the ramloader(for phone having a bootloader on flash) -o highram is for phones having the romloader(if the phone has a bootrom) - or for loading in the ram trough a special loader(loaded first on ram - by talking to the ramloader) when having a ramloader(which can only - load 64k). - -Configurations -============== - - 1. Each Compal E99 configuration is maintained in a sub-directory and - can be selected as follow: - - cd tools - ./configure.sh compal_e99/ - cd - - . ./setenv.sh - - Where is one of the configuration sub-directories under - nuttx/configs/compal_e99. - - 2. These configurations use the mconf-based configuration tool. To - change a configurations using that tool, you should: - - a. Build and install the kconfig-mconf tool. See nuttx/README.txt - see additional README.txt files in the NuttX tools repository. - - b. Execute 'make menuconfig' in nuttx/ in order to start the - reconfiguration process. - - 3. By default, all configurations assume the NuttX Buildroot toolchain - under Linux (should work under Windows with Cygwin as well). This - is easily reconfigured: - - CONFIG_HOST_LINUX=y - CONFIG_ARM_TOOLCHAIN_BUILDROOT=y diff --git a/configs/compal_e99/include/board.h b/configs/compal_e99/include/board.h deleted file mode 100644 index 5855614184..0000000000 --- a/configs/compal_e99/include/board.h +++ /dev/null @@ -1,6 +0,0 @@ -/**************************************************************************** - * arch/board.h - * - * Supposed to be empty - * - ****************************************************************************/ diff --git a/configs/compal_e99/nsh_compalram/Make.defs b/configs/compal_e99/nsh_compalram/Make.defs deleted file mode 100644 index ce04422ec8..0000000000 --- a/configs/compal_e99/nsh_compalram/Make.defs +++ /dev/null @@ -1,125 +0,0 @@ -############################################################################ -# configs/c5471evm/nsh/Make.defs -# -# Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk -include ${TOPDIR}/arch/arm/src/arm/Toolchain.defs - -ifeq ($(WINTOOL),y) - # Windows-native toolchains - DIRLINK = $(TOPDIR)/tools/copydir.sh - DIRUNLINK = $(TOPDIR)/tools/unlink.sh - MKDEP = $(TOPDIR)/tools/mkwindeps.sh - ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" - ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" - ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/compalram.ld}" -else - # Linux/Cygwin-native toolchain - MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) - ARCHINCLUDES = -I. -isystem $(TOPDIR)/include - ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx - ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/compalram.ld -endif - -CC = $(CROSSDEV)gcc -CXX = $(CROSSDEV)g++ -CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld -AR = $(CROSSDEV)ar rcs -NM = $(CROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} -ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} - -ifeq ($(ARCHCCMAJOR),4) -ifneq ($(HOSTOS),Cygwin) - OBJCOPYARGS = -R .note -R .note.gnu.build-id -R .comment -endif -endif - -ifeq ("${CONFIG_DEBUG_FEATURES}","y") - ARCHOPTIMIZATION = -g -endif - -ifneq ($(CONFIG_DEBUG_NOOPT),y) - ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer -endif - -ifeq ($(ARCHCCMAJOR),4) - ARCHCPUFLAGS = -mcpu=arm7tdmi -mfloat-abi=soft -else - ARCHCPUFLAGS = -mapcs-32 -mcpu=arm7tdmi -msoft-float -endif - -ARCHCFLAGS = -fno-builtin -ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -ARCHWARNINGSXX = -Wall -Wshadow -Wundef -ARCHDEFINES = - -CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ - $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) \ - $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -AFLAGS = $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) \ - -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld \ - -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -ASMEXT = .S -OBJEXT = .o -LIBEXT = .a -EXEEXT = - -ifneq ($(CROSSDEV),arm-nuttx-elf-) - LDFLAGS += -nostartfiles -nodefaultlibs -endif -ifeq ($(CONFIG_DEBUG_FEATURES),y) - LDFLAGS += -g -endif - -HOSTCC = gcc -HOSTINCLUDES = -I. -HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe -HOSTLDFLAGS = diff --git a/configs/compal_e99/nsh_compalram/defconfig b/configs/compal_e99/nsh_compalram/defconfig deleted file mode 100644 index f5dc463da4..0000000000 --- a/configs/compal_e99/nsh_compalram/defconfig +++ /dev/null @@ -1,841 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Nuttx/ Configuration -# - -# -# Build Setup -# -# CONFIG_EXPERIMENTAL is not set -# CONFIG_DEFAULT_SMALL is not set -CONFIG_HOST_LINUX=y -# CONFIG_HOST_OSX is not set -# CONFIG_HOST_WINDOWS is not set -# CONFIG_HOST_OTHER is not set - -# -# Build Configuration -# -# CONFIG_APPS_DIR="../apps" -CONFIG_BUILD_FLAT=y -# CONFIG_BUILD_2PASS is not set - -# -# Binary Output Formats -# -# CONFIG_RRLOAD_BINARY is not set -# CONFIG_INTELHEX_BINARY is not set -# CONFIG_MOTOROLA_SREC is not set -CONFIG_RAW_BINARY=y -# CONFIG_UBOOT_UIMAGE is not set - -# -# Customize Header Files -# -# CONFIG_ARCH_STDINT_H is not set -# CONFIG_ARCH_STDBOOL_H is not set -# CONFIG_ARCH_MATH_H is not set -# CONFIG_ARCH_FLOAT_H is not set -# CONFIG_ARCH_STDARG_H is not set -# CONFIG_ARCH_DEBUG_H is not set - -# -# Debug Options -# -CONFIG_DEBUG_ALERT=y -# CONFIG_DEBUG_FEATURES is not set -CONFIG_ARCH_HAVE_STACKCHECK=y -# CONFIG_STACK_COLORATION is not set -# CONFIG_ARCH_HAVE_HEAPCHECK is not set -# CONFIG_DEBUG_SYMBOLS is not set -CONFIG_ARCH_HAVE_CUSTOMOPT=y -# CONFIG_DEBUG_NOOPT is not set -# CONFIG_DEBUG_CUSTOMOPT is not set -CONFIG_DEBUG_FULLOPT=y - -# -# System Type -# -CONFIG_ARCH_ARM=y -# CONFIG_ARCH_AVR is not set -# CONFIG_ARCH_HC is not set -# CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_SIM is not set -# CONFIG_ARCH_X86 is not set -# CONFIG_ARCH_Z16 is not set -# CONFIG_ARCH_Z80 is not set -CONFIG_ARCH="arm" - -# -# ARM Options -# -# CONFIG_ARCH_CHIP_A1X is not set -# CONFIG_ARCH_CHIP_C5471 is not set -CONFIG_ARCH_CHIP_CALYPSO=y -# CONFIG_ARCH_CHIP_DM320 is not set -# CONFIG_ARCH_CHIP_EFM32 is not set -# CONFIG_ARCH_CHIP_IMX1 is not set -# CONFIG_ARCH_CHIP_IMX6 is not set -# CONFIG_ARCH_CHIP_KINETIS is not set -# CONFIG_ARCH_CHIP_KL is not set -# CONFIG_ARCH_CHIP_LM is not set -# CONFIG_ARCH_CHIP_TIVA is not set -# CONFIG_ARCH_CHIP_LPC11XX is not set -# CONFIG_ARCH_CHIP_LPC17XX is not set -# CONFIG_ARCH_CHIP_LPC214X is not set -# CONFIG_ARCH_CHIP_LPC2378 is not set -# CONFIG_ARCH_CHIP_LPC31XX is not set -# CONFIG_ARCH_CHIP_LPC43XX is not set -# CONFIG_ARCH_CHIP_NUC1XX is not set -# CONFIG_ARCH_CHIP_SAMA5 is not set -# CONFIG_ARCH_CHIP_SAMD is not set -# CONFIG_ARCH_CHIP_SAML is not set -# CONFIG_ARCH_CHIP_SAM34 is not set -# CONFIG_ARCH_CHIP_SAMV7 is not set -# CONFIG_ARCH_CHIP_STM32 is not set -# CONFIG_ARCH_CHIP_STM32F7 is not set -# CONFIG_ARCH_CHIP_STM32L4 is not set -# CONFIG_ARCH_CHIP_STR71X is not set -# CONFIG_ARCH_CHIP_TMS570 is not set -# CONFIG_ARCH_CHIP_MOXART is not set -CONFIG_ARCH_ARM7TDMI=y -# CONFIG_ARCH_ARM926EJS is not set -# CONFIG_ARCH_ARM920T is not set -# CONFIG_ARCH_CORTEXM0 is not set -# CONFIG_ARCH_CORTEXM3 is not set -# CONFIG_ARCH_CORTEXM4 is not set -# CONFIG_ARCH_CORTEXM7 is not set -# CONFIG_ARCH_CORTEXA5 is not set -# CONFIG_ARCH_CORTEXA8 is not set -# CONFIG_ARCH_CORTEXA9 is not set -# CONFIG_ARCH_CORTEXR4 is not set -# CONFIG_ARCH_CORTEXR4F is not set -# CONFIG_ARCH_CORTEXR5 is not set -# CONFIG_ARCH_CORTEX5F is not set -# CONFIG_ARCH_CORTEXR7 is not set -# CONFIG_ARCH_CORTEXR7F is not set -CONFIG_ARCH_FAMILY="arm" -CONFIG_ARCH_CHIP="calypso" -# CONFIG_ARM_TOOLCHAIN_IAR is not set -# CONFIG_ARM_TOOLCHAIN_GNU is not set -# CONFIG_ARCH_HAVE_FPU is not set -# CONFIG_ARCH_HAVE_DPFPU is not set -# CONFIG_ARCH_HAVE_TRUSTZONE is not set -# CONFIG_ARM_HAVE_MPU_UNIFIED is not set -CONFIG_ARCH_HAVE_LOWVECTORS=y -# CONFIG_ARCH_LOWVECTORS is not set - -# -# ARM Configuration Options -# -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -# CONFIG_ARM_TOOLCHAIN_CODESOURCERYL is not set -# CONFIG_ARM_TOOLCHAIN_GNU_EABIL is not set -# CONFIG_ARM_TOOLCHAIN_GNU_OABI is not set -# CONFIG_ARM_OABI_TOOLCHAIN is not set -CONFIG_UART_IRDA_BAUD=115200 -CONFIG_UART_IRDA_PARITY=0 -CONFIG_UART_IRDA_BITS=8 -CONFIG_UART_IRDA_2STOP=0 -CONFIG_UART_IRDA_RXBUFSIZE=256 -CONFIG_UART_IRDA_TXBUFSIZE=256 -CONFIG_UART_MODEM_BAUD=115200 -CONFIG_UART_MODEM_PARITY=0 -CONFIG_UART_MODEM_BITS=8 -CONFIG_UART_MODEM_2STOP=0 -CONFIG_UART_MODEM_RXBUFSIZE=256 -CONFIG_UART_MODEM_TXBUFSIZE=256 - -# -# Calypso Configuration Options -# - -# -# Modem UART Configuration -# -# CONFIG_UART_MODEM_HWFLOWCONTROL is not set - -# -# IrDA UART Configuration -# -# CONFIG_UART_IRDA_HWFLOWCONTROL is not set -# CONFIG_USE_SERCOMM_CONSOLE is not set -# CONFIG_SERIAL_MODEM_CONSOLE is not set -# CONFIG_SERIAL_IRDA_CONSOLE is not set -CONFIG_SERIAL_CONSOLE_NONE=y - -# -# Architecture Options -# -# CONFIG_ARCH_NOINTC is not set -# CONFIG_ARCH_VECNOTIRQ is not set -# CONFIG_ARCH_DMA is not set -# CONFIG_ARCH_HAVE_IRQPRIO is not set -# CONFIG_ARCH_L2CACHE is not set -# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set -# CONFIG_ARCH_HAVE_ADDRENV is not set -# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set -# CONFIG_ARCH_HAVE_MULTICPU is not set -CONFIG_ARCH_HAVE_VFORK=y -# CONFIG_ARCH_HAVE_MMU is not set -# CONFIG_ARCH_HAVE_MPU is not set -# CONFIG_ARCH_NAND_HWECC is not set -# CONFIG_ARCH_HAVE_EXTCLK is not set -CONFIG_ARCH_HAVE_POWEROFF=y -# CONFIG_ARCH_HAVE_RESET is not set -CONFIG_ARCH_STACKDUMP=y -# CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_IDLE_CUSTOM is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set -# CONFIG_ARCH_HAVE_RAMVECTORS is not set - -# -# Board Settings -# -CONFIG_BOARD_LOOPSPERMSEC=1250 -# CONFIG_ARCH_CALIBRATION is not set - -# -# Interrupt options -# -CONFIG_ARCH_HAVE_INTERRUPTSTACK=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set - -# -# Boot options -# -# CONFIG_BOOT_RUNFROMEXTSRAM is not set -# CONFIG_BOOT_RUNFROMFLASH is not set -CONFIG_BOOT_RUNFROMISRAM=y -# CONFIG_BOOT_RUNFROMSDRAM is not set -# CONFIG_BOOT_COPYTORAM is not set - -# -# Boot Memory Configuration -# -CONFIG_RAM_START=0 -CONFIG_RAM_SIZE=8650752 -# CONFIG_ARCH_HAVE_SDRAM is not set - -# -# Board Selection -# -# CONFIG_ARCH_BOARD_COMPALE86 is not set -# CONFIG_ARCH_BOARD_COMPALE88 is not set -CONFIG_ARCH_BOARD_COMPALE99=y -# CONFIG_ARCH_BOARD_PIRELLI_DPL10 is not set -# CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD="compal_e99" - -# -# Common Board Options -# -CONFIG_NSH_MMCSDMINOR=0 - -# -# Board-Specific Options -# -CONFIG_COMPALE99_LCD_SSD1783=y -CONFIG_LIB_BOARDCTL=y -CONFIG_BOARDCTL_POWEROFF=y -# CONFIG_BOARDCTL_UNIQUEID is not set -# CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_GRAPHICS is not set -# CONFIG_BOARDCTL_IOCTL is not set - -# -# RTOS Features -# -CONFIG_DISABLE_OS_API=y -# CONFIG_DISABLE_POSIX_TIMERS is not set -# CONFIG_DISABLE_PTHREAD is not set -# CONFIG_DISABLE_SIGNALS is not set -CONFIG_DISABLE_MQUEUE=y -# CONFIG_DISABLE_ENVIRON is not set - -# -# Clocks and Timers -# -CONFIG_USEC_PER_TICK=10000 -# CONFIG_SYSTEM_TIME64 is not set -# CONFIG_CLOCK_MONOTONIC is not set -# CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2007 -CONFIG_START_MONTH=2 -CONFIG_START_DAY=13 -CONFIG_MAX_WDOGPARMS=4 -CONFIG_PREALLOC_WDOGS=8 -CONFIG_WDOG_INTRESERVE=1 -CONFIG_PREALLOC_TIMERS=8 - -# -# Tasks and Scheduling -# -# CONFIG_INIT_NONE is not set -CONFIG_INIT_ENTRYPOINT=y -# CONFIG_INIT_FILEPATH is not set -CONFIG_USER_ENTRYPOINT="nsh_main" -CONFIG_RR_INTERVAL=200 -# CONFIG_SCHED_SPORADIC is not set -CONFIG_TASK_NAME_SIZE=0 -CONFIG_MAX_TASKS=16 -# CONFIG_SCHED_HAVE_PARENT is not set -# CONFIG_SCHED_WAITPID is not set - -# -# Pthread Options -# -# CONFIG_MUTEX_TYPES is not set -CONFIG_NPTHREAD_KEYS=4 - -# -# Performance Monitoring -# -# CONFIG_SCHED_CPULOAD is not set -# CONFIG_SCHED_INSTRUMENTATION is not set - -# -# Files and I/O -# -CONFIG_DEV_CONSOLE=y -# CONFIG_FDCLONE_DISABLE is not set -# CONFIG_FDCLONE_STDIO is not set -CONFIG_SDCLONE_DISABLE=y -CONFIG_NFILE_DESCRIPTORS=8 -CONFIG_NFILE_STREAMS=8 -CONFIG_NAME_MAX=32 -# CONFIG_PRIORITY_INHERITANCE is not set - -# -# RTOS hooks -# -# CONFIG_BOARD_INITIALIZE is not set -# CONFIG_SCHED_STARTHOOK is not set -# CONFIG_SCHED_ATEXIT is not set -# CONFIG_SCHED_ONEXIT is not set - -# -# Signal Numbers -# -CONFIG_SIG_SIGUSR1=1 -CONFIG_SIG_SIGUSR2=2 -CONFIG_SIG_SIGALARM=3 -CONFIG_SIG_SIGCONDTIMEDOUT=16 -# CONFIG_MODULE is not set - -# -# Work queue support -# -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set -# CONFIG_SCHED_LPWORK is not set - -# -# Stack and heap information -# -CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_USERMAIN_STACKSIZE=4096 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=4096 -# CONFIG_LIB_SYSCALL is not set - -# -# Device Drivers -# -CONFIG_DISABLE_POLL=y -CONFIG_DEV_NULL=y -# CONFIG_DEV_ZERO is not set -# CONFIG_DEV_LOOP is not set - -# -# Buffering -# -# CONFIG_DRVR_WRITEBUFFER is not set -# CONFIG_DRVR_READAHEAD is not set -# CONFIG_RAMDISK is not set -# CONFIG_CAN is not set -# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set -# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set -# CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set -# CONFIG_I2C is not set -CONFIG_SPI=y -# CONFIG_SPI_SLAVE is not set -CONFIG_SPI_EXCHANGE=y -# CONFIG_SPI_CMDDATA is not set -# CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set -# CONFIG_SPI_CS_DELAY_CONTROL is not set -# CONFIG_I2S is not set - -# -# Timer Driver Support -# -# CONFIG_TIMER is not set -# CONFIG_RTC is not set -# CONFIG_WATCHDOG is not set -# CONFIG_ANALOG is not set -# CONFIG_AUDIO_DEVICES is not set -# CONFIG_VIDEO_DEVICES is not set -# CONFIG_BCH is not set -# CONFIG_INPUT is not set -# CONFIG_IOEXPANDER is not set - -# -# LCD Driver Support -# -CONFIG_LCD=y - -# -# Common Graphic LCD Settings -# -# CONFIG_LCD_CONSOLE is not set -# CONFIG_LCD_NOGETRUN is not set -CONFIG_LCD_MAXCONTRAST=63 -CONFIG_LCD_MAXPOWER=1 - -# -# Graphic LCD Devices -# -# CONFIG_LCD_P14201 is not set -# CONFIG_LCD_NOKIA6100 is not set -# CONFIG_LCD_MIO283QT2 is not set -# CONFIG_LCD_MIO283QT9A is not set -# CONFIG_LCD_UG9664HSWAG01 is not set -# CONFIG_LCD_UG2864HSWEG01 is not set -# CONFIG_LCD_UG2832HSWEG04 is not set -# CONFIG_LCD_SSD1351 is not set -# CONFIG_LCD_ST7565 is not set -# CONFIG_LCD_ST7567 is not set -# CONFIG_LCD_UG2864AMBAG01 is not set -# CONFIG_LCD_SSD1289 is not set -# CONFIG_LCD_SHARP_MEMLCD is not set -CONFIG_LCD_LANDSCAPE=y -# CONFIG_LCD_PORTRAIT is not set -# CONFIG_LCD_RPORTRAIT is not set -# CONFIG_LCD_RLANDSCAPE is not set -# CONFIG_LCD_ILI9341 is not set -# CONFIG_LCD_RA8875 is not set -# CONFIG_SLCD is not set - -# -# LED Support -# -# CONFIG_RGBLED is not set -# CONFIG_PCA9635PW is not set -# CONFIG_NCP5623C is not set -# CONFIG_MMCSD is not set -# CONFIG_MODEM is not set -# CONFIG_MTD is not set -# CONFIG_EEPROM is not set -# CONFIG_PIPES is not set -# CONFIG_PM is not set -# CONFIG_POWER is not set -# CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set -CONFIG_SERIAL=y -# CONFIG_DEV_LOWCONSOLE is not set -# CONFIG_SERIAL_REMOVABLE is not set -CONFIG_SERIAL_CONSOLE=y -# CONFIG_16550_UART is not set -# CONFIG_UART_SERIALDRIVER is not set -# CONFIG_UART0_SERIALDRIVER is not set -# CONFIG_UART1_SERIALDRIVER is not set -# CONFIG_UART2_SERIALDRIVER is not set -# CONFIG_UART3_SERIALDRIVER is not set -# CONFIG_UART4_SERIALDRIVER is not set -# CONFIG_UART5_SERIALDRIVER is not set -# CONFIG_UART6_SERIALDRIVER is not set -# CONFIG_UART7_SERIALDRIVER is not set -# CONFIG_UART8_SERIALDRIVER is not set -# CONFIG_SCI0_SERIALDRIVER is not set -# CONFIG_SCI1_SERIALDRIVER is not set -# CONFIG_USART0_SERIALDRIVER is not set -# CONFIG_USART1_SERIALDRIVER is not set -# CONFIG_USART2_SERIALDRIVER is not set -# CONFIG_USART3_SERIALDRIVER is not set -# CONFIG_USART4_SERIALDRIVER is not set -# CONFIG_USART5_SERIALDRIVER is not set -# CONFIG_USART6_SERIALDRIVER is not set -# CONFIG_USART7_SERIALDRIVER is not set -# CONFIG_USART8_SERIALDRIVER is not set -CONFIG_OTHER_UART_SERIALDRIVER=y -CONFIG_MCU_SERIAL=y -# CONFIG_STANDARD_SERIAL is not set -# CONFIG_SERIAL_IFLOWCONTROL is not set -# CONFIG_SERIAL_OFLOWCONTROL is not set -# CONFIG_SERIAL_DMA is not set -# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set -CONFIG_OTHER_SERIAL_CONSOLE=y -# CONFIG_NO_SERIAL_CONSOLE is not set -# CONFIG_USBDEV is not set -# CONFIG_USBHOST is not set -# CONFIG_DRIVERS_WIRELESS is not set - -# -# System Logging -# -# CONFIG_ARCH_SYSLOG is not set -# CONFIG_RAMLOG is not set -# CONFIG_SYSLOG_INTBUFFER is not set -# CONFIG_SYSLOG_TIMESTAMP is not set -CONFIG_SYSLOG_SERIAL_CONSOLE=y -# CONFIG_SYSLOG_CHAR is not set -CONFIG_SYSLOG_CONSOLE=y -# CONFIG_SYSLOG_NONE is not set -# CONFIG_SYSLOG_FILE is not set - -# -# Networking Support -# -# CONFIG_ARCH_HAVE_NET is not set -# CONFIG_ARCH_HAVE_PHY is not set -# CONFIG_NET is not set - -# -# Crypto API -# -# CONFIG_CRYPTO is not set - -# -# File Systems -# - -# -# File system configuration -# -# CONFIG_DISABLE_MOUNTPOINT is not set -# CONFIG_FS_AUTOMOUNTER is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_FS_READABLE is not set -# CONFIG_FS_WRITABLE is not set -# CONFIG_FS_NAMED_SEMAPHORES is not set -# CONFIG_FS_RAMMAP is not set -# CONFIG_FS_FAT is not set -# CONFIG_FS_NXFFS is not set -# CONFIG_FS_ROMFS is not set -# CONFIG_FS_TMPFS is not set -# CONFIG_FS_SMARTFS is not set -# CONFIG_FS_BINFS is not set -# CONFIG_FS_PROCFS is not set -# CONFIG_FS_UNIONFS is not set - -# -# Graphics Support -# -# CONFIG_NX is not set - -# -# Memory Management -# -# CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=2 -CONFIG_ARCH_HAVE_HEAP2=y -CONFIG_HEAP2_BASE=0x01000000 -CONFIG_HEAP2_SIZE=2097152 -# CONFIG_GRAN is not set - -# -# Audio Support -# -# CONFIG_AUDIO is not set - -# -# Wireless Support -# - -# -# Binary Loader -# -# CONFIG_BINFMT_DISABLE is not set -# CONFIG_BINFMT_EXEPATH is not set -# CONFIG_NXFLAT is not set -# CONFIG_ELF is not set -CONFIG_BUILTIN=y -# CONFIG_PIC is not set -# CONFIG_SYMTAB_ORDEREDBYNAME is not set - -# -# Library Routines -# - -# -# Standard C Library Options -# -CONFIG_STDIO_BUFFER_SIZE=64 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=2 -CONFIG_LIB_HOMEDIR="/" -# CONFIG_LIBM is not set -# CONFIG_NOPRINTF_FIELDWIDTH is not set -# CONFIG_LIBC_FLOATINGPOINT is not set -CONFIG_LIBC_LONG_LONG=y -# CONFIG_LIBC_IOCTL_VARIADIC is not set -CONFIG_LIB_RAND_ORDER=1 -# CONFIG_EOL_IS_CR is not set -# CONFIG_EOL_IS_LF is not set -# CONFIG_EOL_IS_BOTH_CRLF is not set -CONFIG_EOL_IS_EITHER_CRLF=y -# CONFIG_LIBC_EXECFUNCS is not set -CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 -# CONFIG_LIBC_STRERROR is not set -# CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_ARCH_LOWPUTC=y -# CONFIG_LIBC_LOCALTIME is not set -# CONFIG_TIME_EXTENDED is not set -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set -# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set -CONFIG_ARCH_HAVE_TLS=y -# CONFIG_TLS is not set -# CONFIG_LIBC_NETDB is not set - -# -# Non-standard Library Support -# -# CONFIG_LIB_CRC64_FAST is not set -# CONFIG_LIB_KBDCODEC is not set -# CONFIG_LIB_SLCDCODEC is not set - -# -# Basic CXX Support -# -# CONFIG_C99_BOOL8 is not set -# CONFIG_HAVE_CXX is not set - -# -# Application Configuration -# - -# -# Built-In Applications -# -CONFIG_BUILTIN_PROXY_STACKSIZE=1024 - -# -# CAN Utilities -# - -# -# Examples -# -# CONFIG_EXAMPLES_CHAT is not set -# CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set -# CONFIG_EXAMPLES_DHCPD is not set -# CONFIG_EXAMPLES_ELF is not set -# CONFIG_EXAMPLES_FTPC is not set -# CONFIG_EXAMPLES_FTPD is not set -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_HELLO_PRIORITY=100 -CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 -# CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_IGMP is not set -# CONFIG_EXAMPLES_JSON is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set -# CONFIG_EXAMPLES_MEDIA is not set -# CONFIG_EXAMPLES_MM is not set -# CONFIG_EXAMPLES_MODBUS is not set -# CONFIG_EXAMPLES_MOUNT is not set -# CONFIG_EXAMPLES_NRF24L01TERM is not set -CONFIG_EXAMPLES_NSH=y -# CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXFFS is not set -# CONFIG_EXAMPLES_NXHELLO is not set -# CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NXLINES is not set -# CONFIG_EXAMPLES_NXTERM is not set -# CONFIG_EXAMPLES_NXTEXT is not set -# CONFIG_EXAMPLES_OSTEST is not set -# CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_PPPD is not set -# CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_SENDMAIL is not set -# CONFIG_EXAMPLES_SERIALBLASTER is not set -# CONFIG_EXAMPLES_SERIALRX is not set -# CONFIG_EXAMPLES_SERLOOP is not set -# CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART is not set -# CONFIG_EXAMPLES_SMART_TEST is not set -# CONFIG_EXAMPLES_SMP is not set -# CONFIG_EXAMPLES_TCPECHO is not set -# CONFIG_EXAMPLES_TELNETD is not set -# CONFIG_EXAMPLES_TIFF is not set -# CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_USBSERIAL is not set -# CONFIG_EXAMPLES_USBTERM is not set -# CONFIG_EXAMPLES_WATCHDOG is not set -# CONFIG_EXAMPLES_WEBSERVER is not set - -# -# File System Utilities -# -# CONFIG_FSUTILS_INIFILE is not set - -# -# GPS Utilities -# -# CONFIG_GPSUTILS_MINMEA_LIB is not set - -# -# Graphics Support -# -# CONFIG_TIFF is not set -# CONFIG_GRAPHICS_TRAVELER is not set - -# -# Interpreters -# -# CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_MICROPYTHON is not set -# CONFIG_INTERPRETERS_PCODE is not set - -# -# FreeModBus -# -# CONFIG_MODBUS is not set - -# -# Network Utilities -# -# CONFIG_NETUTILS_CODECS is not set -# CONFIG_NETUTILS_ESP8266 is not set -# CONFIG_NETUTILS_FTPC is not set -# CONFIG_NETUTILS_JSON is not set -# CONFIG_NETUTILS_SMTP is not set - -# -# NSH Library -# -CONFIG_NSH_LIBRARY=y -# CONFIG_NSH_MOTD is not set - -# -# Command Line Configuration -# -CONFIG_NSH_READLINE=y -# CONFIG_NSH_CLE is not set -CONFIG_NSH_LINELEN=64 -# CONFIG_NSH_DISABLE_SEMICOLON is not set -CONFIG_NSH_CMDPARMS=y -CONFIG_NSH_MAXARGUMENTS=6 -CONFIG_NSH_ARGCAT=y -CONFIG_NSH_NESTDEPTH=3 -# CONFIG_NSH_DISABLEBG is not set -CONFIG_NSH_BUILTIN_APPS=y - -# -# Disable Individual commands -# -# CONFIG_NSH_DISABLE_ADDROUTE is not set -# CONFIG_NSH_DISABLE_BASENAME is not set -# CONFIG_NSH_DISABLE_CAT is not set -# CONFIG_NSH_DISABLE_CD is not set -# CONFIG_NSH_DISABLE_CP is not set -# CONFIG_NSH_DISABLE_CMP is not set -CONFIG_NSH_DISABLE_DATE=y -# CONFIG_NSH_DISABLE_DD is not set -# CONFIG_NSH_DISABLE_DF is not set -# CONFIG_NSH_DISABLE_DELROUTE is not set -# CONFIG_NSH_DISABLE_DIRNAME is not set -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HELP is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -CONFIG_NSH_DISABLE_IFUPDOWN=y -# CONFIG_NSH_DISABLE_KILL is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -CONFIG_NSH_DISABLE_LOSMART=y -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_MB is not set -# CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_MH is not set -# CONFIG_NSH_DISABLE_MOUNT is not set -# CONFIG_NSH_DISABLE_MV is not set -# CONFIG_NSH_DISABLE_MW is not set -# CONFIG_NSH_DISABLE_POWEROFF is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_PWD is not set -# CONFIG_NSH_DISABLE_RM is not set -# CONFIG_NSH_DISABLE_RMDIR is not set -# CONFIG_NSH_DISABLE_SET is not set -# CONFIG_NSH_DISABLE_SH is not set -CONFIG_NSH_DISABLE_SHUTDOWN=y -# CONFIG_NSH_DISABLE_SLEEP is not set -# CONFIG_NSH_DISABLE_TIME is not set -# CONFIG_NSH_DISABLE_TEST is not set -# CONFIG_NSH_DISABLE_UMOUNT is not set -# CONFIG_NSH_DISABLE_UNAME is not set -# CONFIG_NSH_DISABLE_UNSET is not set -# CONFIG_NSH_DISABLE_USLEEP is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set - -# -# Configure Command Options -# -CONFIG_NSH_CMDOPT_DF_H=y -CONFIG_NSH_CODECS_BUFSIZE=128 -CONFIG_NSH_CMDOPT_HEXDUMP=y -CONFIG_NSH_FILEIOSIZE=1024 - -# -# Scripting Support -# -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_ITEF is not set -# CONFIG_NSH_DISABLE_LOOPS is not set - -# -# Console Configuration -# -CONFIG_NSH_CONSOLE=y -# CONFIG_NSH_ALTCONDEV is not set -# CONFIG_NSH_ARCHINIT is not set -# CONFIG_NSH_LOGIN is not set -# CONFIG_NSH_CONSOLE_LOGIN is not set - -# -# NxWidgets/NxWM -# - -# -# Platform-specific Support -# -# CONFIG_PLATFORM_CONFIGDATA is not set - -# -# System Libraries and NSH Add-Ons -# -# CONFIG_SYSTEM_CLE is not set -# CONFIG_SYSTEM_CUTERM is not set -# CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set -# CONFIG_SYSTEM_HEXED is not set -# CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_RAMTEST is not set -CONFIG_READLINE_HAVE_EXTMATCH=y -CONFIG_SYSTEM_READLINE=y -CONFIG_READLINE_ECHO=y -# CONFIG_READLINE_TABCOMPLETION is not set -# CONFIG_READLINE_CMD_HISTORY is not set -# CONFIG_SYSTEM_SUDOKU is not set -# CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_VI is not set -# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/compal_e99/nsh_compalram/setenv.sh b/configs/compal_e99/nsh_compalram/setenv.sh deleted file mode 100755 index 16a2fe30fa..0000000000 --- a/configs/compal_e99/nsh_compalram/setenv.sh +++ /dev/null @@ -1,63 +0,0 @@ -#!/bin/bash -# c5471evm/nsh/setenv.sh -# -# Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if [ "$_" = "$0" ] ; then - echo "You must source this script, not run it!" 1>&2 - exit 1 -fi - -WD=`pwd` -if [ ! -x "setenv.sh" ]; then - echo "This script must be executed from the top-level NuttX build directory" - exit 1 -fi - -if [ -z "${PATH_ORIG}" ]; then - export PATH_ORIG="${PATH}" -fi - -# This is the Cygwin path to the location where I installed the CodeSourcery -# toolchain under windows. You will also have to edit this if you install -# the CodeSourcery toolchain in any other location -# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" -# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" - -# This is the Cygwin path to the location where I build the buildroot -# toolchain. -export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" - -# Add the path to the toolchain to the PATH varialble -export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" - -echo "PATH : ${PATH}" diff --git a/configs/compal_e99/nsh_highram/Make.defs b/configs/compal_e99/nsh_highram/Make.defs deleted file mode 100644 index 7eaac99e8b..0000000000 --- a/configs/compal_e99/nsh_highram/Make.defs +++ /dev/null @@ -1,125 +0,0 @@ -############################################################################ -# configs/c5471evm/nsh/Make.defs -# -# Copyright (C) 2007, 2008, 2011, 2014 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk -include ${TOPDIR}/arch/arm/src/arm/Toolchain.defs - -ifeq ($(WINTOOL),y) - # Windows-native toolchains - DIRLINK = $(TOPDIR)/tools/copydir.sh - DIRUNLINK = $(TOPDIR)/tools/unlink.sh - MKDEP = $(TOPDIR)/tools/mkwindeps.sh - ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" - ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" - ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/highram.ld}" -else - # Linux/Cygwin-native toolchain - MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) - ARCHINCLUDES = -I. -isystem $(TOPDIR)/include - ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx - ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/highram.ld -endif - -CC = $(CROSSDEV)gcc -CXX = $(CROSSDEV)g++ -CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld -AR = $(CROSSDEV)ar rcs -NM = $(CROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} -ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} - -ifeq ($(ARCHCCMAJOR),4) -ifneq ($(HOSTOS),Cygwin) - OBJCOPYARGS = -R .note -R .note.gnu.build-id -R .comment -endif -endif - -ifeq ("${CONFIG_DEBUG_FEATURES}","y") - ARCHOPTIMIZATION = -g -endif - -ifneq ($(CONFIG_DEBUG_NOOPT),y) - ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer -endif - -ifeq ($(ARCHCCMAJOR),4) - ARCHCPUFLAGS = -mcpu=arm7tdmi -mfloat-abi=soft -else - ARCHCPUFLAGS = -mapcs-32 -mcpu=arm7tdmi -msoft-float -endif - -ARCHCFLAGS = -fno-builtin -ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -ARCHWARNINGSXX = -Wall -Wshadow -Wundef -ARCHDEFINES = - -CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ - $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) \ - $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -AFLAGS = $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) \ - -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld \ - -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -ASMEXT = .S -OBJEXT = .o -LIBEXT = .a -EXEEXT = - -ifneq ($(CROSSDEV),arm-nuttx-elf-) - LDFLAGS += -nostartfiles -nodefaultlibs -endif -ifeq ($(CONFIG_DEBUG_FEATURES),y) - LDFLAGS += -g -endif - -HOSTCC = gcc -HOSTINCLUDES = -I. -HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe -HOSTLDFLAGS = diff --git a/configs/compal_e99/nsh_highram/defconfig b/configs/compal_e99/nsh_highram/defconfig deleted file mode 100644 index 6129f41748..0000000000 --- a/configs/compal_e99/nsh_highram/defconfig +++ /dev/null @@ -1,1006 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Nuttx/ Configuration -# - -# -# Build Setup -# -# CONFIG_EXPERIMENTAL is not set -# CONFIG_DEFAULT_SMALL is not set -CONFIG_HOST_LINUX=y -# CONFIG_HOST_OSX is not set -# CONFIG_HOST_WINDOWS is not set -# CONFIG_HOST_OTHER is not set - -# -# Build Configuration -# -# CONFIG_APPS_DIR="../apps" -CONFIG_BUILD_FLAT=y -# CONFIG_BUILD_2PASS is not set - -# -# Binary Output Formats -# -# CONFIG_RRLOAD_BINARY is not set -# CONFIG_INTELHEX_BINARY is not set -# CONFIG_MOTOROLA_SREC is not set -CONFIG_RAW_BINARY=y -# CONFIG_UBOOT_UIMAGE is not set - -# -# Customize Header Files -# -# CONFIG_ARCH_STDINT_H is not set -# CONFIG_ARCH_STDBOOL_H is not set -# CONFIG_ARCH_MATH_H is not set -# CONFIG_ARCH_FLOAT_H is not set -# CONFIG_ARCH_STDARG_H is not set -# CONFIG_ARCH_DEBUG_H is not set - -# -# Debug Options -# -CONFIG_DEBUG_ALERT=y -# CONFIG_DEBUG_FEATURES is not set -CONFIG_ARCH_HAVE_STACKCHECK=y -# CONFIG_STACK_COLORATION is not set -# CONFIG_ARCH_HAVE_HEAPCHECK is not set -# CONFIG_DEBUG_SYMBOLS is not set -CONFIG_ARCH_HAVE_CUSTOMOPT=y -# CONFIG_DEBUG_NOOPT is not set -# CONFIG_DEBUG_CUSTOMOPT is not set -CONFIG_DEBUG_FULLOPT=y - -# -# System Type -# -CONFIG_ARCH_ARM=y -# CONFIG_ARCH_AVR is not set -# CONFIG_ARCH_HC is not set -# CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_MISOC is not set -# CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_RISCV is not set -# CONFIG_ARCH_SIM is not set -# CONFIG_ARCH_X86 is not set -# CONFIG_ARCH_XTENSA is not set -# CONFIG_ARCH_Z16 is not set -# CONFIG_ARCH_Z80 is not set -CONFIG_ARCH="arm" - -# -# ARM Options -# -# CONFIG_ARCH_CHIP_A1X is not set -# CONFIG_ARCH_CHIP_C5471 is not set -CONFIG_ARCH_CHIP_CALYPSO=y -# CONFIG_ARCH_CHIP_DM320 is not set -# CONFIG_ARCH_CHIP_EFM32 is not set -# CONFIG_ARCH_CHIP_IMX1 is not set -# CONFIG_ARCH_CHIP_IMX6 is not set -# CONFIG_ARCH_CHIP_KINETIS is not set -# CONFIG_ARCH_CHIP_KL is not set -# CONFIG_ARCH_CHIP_LM is not set -# CONFIG_ARCH_CHIP_TIVA is not set -# CONFIG_ARCH_CHIP_LPC11XX is not set -# CONFIG_ARCH_CHIP_LPC17XX is not set -# CONFIG_ARCH_CHIP_LPC214X is not set -# CONFIG_ARCH_CHIP_LPC2378 is not set -# CONFIG_ARCH_CHIP_LPC31XX is not set -# CONFIG_ARCH_CHIP_LPC43XX is not set -# CONFIG_ARCH_CHIP_NUC1XX is not set -# CONFIG_ARCH_CHIP_SAMA5 is not set -# CONFIG_ARCH_CHIP_SAMD is not set -# CONFIG_ARCH_CHIP_SAML is not set -# CONFIG_ARCH_CHIP_SAM34 is not set -# CONFIG_ARCH_CHIP_SAMV7 is not set -# CONFIG_ARCH_CHIP_STM32 is not set -# CONFIG_ARCH_CHIP_STM32F7 is not set -# CONFIG_ARCH_CHIP_STM32L4 is not set -# CONFIG_ARCH_CHIP_STR71X is not set -# CONFIG_ARCH_CHIP_TMS570 is not set -# CONFIG_ARCH_CHIP_MOXART is not set -CONFIG_ARCH_ARM7TDMI=y -# CONFIG_ARCH_ARM926EJS is not set -# CONFIG_ARCH_ARM920T is not set -# CONFIG_ARCH_CORTEXM0 is not set -# CONFIG_ARCH_CORTEXM3 is not set -# CONFIG_ARCH_CORTEXM4 is not set -# CONFIG_ARCH_CORTEXM7 is not set -# CONFIG_ARCH_CORTEXA5 is not set -# CONFIG_ARCH_CORTEXA8 is not set -# CONFIG_ARCH_CORTEXA9 is not set -# CONFIG_ARCH_CORTEXR4 is not set -# CONFIG_ARCH_CORTEXR4F is not set -# CONFIG_ARCH_CORTEXR5 is not set -# CONFIG_ARCH_CORTEX5F is not set -# CONFIG_ARCH_CORTEXR7 is not set -# CONFIG_ARCH_CORTEXR7F is not set -CONFIG_ARCH_FAMILY="arm" -CONFIG_ARCH_CHIP="calypso" -# CONFIG_ARM_TOOLCHAIN_IAR is not set -# CONFIG_ARM_TOOLCHAIN_GNU is not set -# CONFIG_ARCH_HAVE_FPU is not set -# CONFIG_ARCH_HAVE_DPFPU is not set -# CONFIG_ARCH_HAVE_TRUSTZONE is not set -# CONFIG_ARM_HAVE_MPU_UNIFIED is not set -CONFIG_ARCH_HAVE_LOWVECTORS=y -# CONFIG_ARCH_LOWVECTORS is not set - -# -# ARM Configuration Options -# -# CONFIG_ARM_TOOLCHAIN_BUILDROOT is not set -# CONFIG_ARM_TOOLCHAIN_CODESOURCERYL is not set -CONFIG_ARM_TOOLCHAIN_GNU_EABIL=y -# CONFIG_ARM_TOOLCHAIN_GNU_OABI is not set -CONFIG_UART_IRDA_BAUD=115200 -CONFIG_UART_IRDA_PARITY=0 -CONFIG_UART_IRDA_BITS=8 -CONFIG_UART_IRDA_2STOP=0 -CONFIG_UART_IRDA_RXBUFSIZE=256 -CONFIG_UART_IRDA_TXBUFSIZE=256 -CONFIG_UART_MODEM_BAUD=115200 -CONFIG_UART_MODEM_PARITY=0 -CONFIG_UART_MODEM_BITS=8 -CONFIG_UART_MODEM_2STOP=0 -CONFIG_UART_MODEM_RXBUFSIZE=256 -CONFIG_UART_MODEM_TXBUFSIZE=256 - -# -# Calypso Configuration Options -# - -# -# Modem UART Configuration -# -# CONFIG_UART_MODEM_HWFLOWCONTROL is not set - -# -# IrDA UART Configuration -# -# CONFIG_UART_IRDA_HWFLOWCONTROL is not set -# CONFIG_USE_SERCOMM_CONSOLE is not set -# CONFIG_SERIAL_MODEM_CONSOLE is not set -# CONFIG_SERIAL_IRDA_CONSOLE is not set -CONFIG_SERIAL_CONSOLE_NONE=y - -# -# Architecture Options -# -# CONFIG_ARCH_NOINTC is not set -# CONFIG_ARCH_VECNOTIRQ is not set -# CONFIG_ARCH_DMA is not set -# CONFIG_ARCH_HAVE_IRQPRIO is not set -# CONFIG_ARCH_L2CACHE is not set -# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set -# CONFIG_ARCH_HAVE_ADDRENV is not set -# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set -# CONFIG_ARCH_HAVE_MULTICPU is not set -CONFIG_ARCH_HAVE_VFORK=y -# CONFIG_ARCH_HAVE_MMU is not set -# CONFIG_ARCH_HAVE_MPU is not set -# CONFIG_ARCH_NAND_HWECC is not set -# CONFIG_ARCH_HAVE_EXTCLK is not set -CONFIG_ARCH_HAVE_POWEROFF=y -# CONFIG_ARCH_HAVE_RESET is not set -CONFIG_ARCH_STACKDUMP=y -# CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_IDLE_CUSTOM is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set -# CONFIG_ARCH_HAVE_RAMVECTORS is not set - -# -# Board Settings -# -CONFIG_BOARD_LOOPSPERMSEC=1250 -# CONFIG_ARCH_CALIBRATION is not set - -# -# Interrupt options -# -CONFIG_ARCH_HAVE_INTERRUPTSTACK=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set - -# -# Boot options -# -# CONFIG_BOOT_RUNFROMEXTSRAM is not set -# CONFIG_BOOT_RUNFROMFLASH is not set -CONFIG_BOOT_RUNFROMISRAM=y -# CONFIG_BOOT_RUNFROMSDRAM is not set -# CONFIG_BOOT_COPYTORAM is not set - -# -# Boot Memory Configuration -# -CONFIG_RAM_START=0 -CONFIG_RAM_SIZE=8650752 -# CONFIG_ARCH_HAVE_SDRAM is not set - -# -# Board Selection -# -# CONFIG_ARCH_BOARD_COMPALE86 is not set -# CONFIG_ARCH_BOARD_COMPALE88 is not set -CONFIG_ARCH_BOARD_COMPALE99=y -# CONFIG_ARCH_BOARD_PIRELLI_DPL10 is not set -# CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD="compal_e99" - -# -# Common Board Options -# - -# -# Board-Specific Options -# -CONFIG_COMPALE99_LCD_SSD1783=y -# CONFIG_BOARD_CRASHDUMP is not set -CONFIG_LIB_BOARDCTL=y -CONFIG_BOARDCTL_POWEROFF=y -# CONFIG_BOARDCTL_UNIQUEID is not set -# CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_GRAPHICS is not set -# CONFIG_BOARDCTL_IOCTL is not set - -# -# RTOS Features -# -CONFIG_DISABLE_OS_API=y -# CONFIG_DISABLE_POSIX_TIMERS is not set -# CONFIG_DISABLE_PTHREAD is not set -# CONFIG_DISABLE_SIGNALS is not set -CONFIG_DISABLE_MQUEUE=y -# CONFIG_DISABLE_ENVIRON is not set - -# -# Clocks and Timers -# -CONFIG_USEC_PER_TICK=10000 -# CONFIG_SYSTEM_TIME64 is not set -# CONFIG_CLOCK_MONOTONIC is not set -# CONFIG_ARCH_HAVE_TIMEKEEPING is not set -# CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2007 -CONFIG_START_MONTH=2 -CONFIG_START_DAY=13 -CONFIG_MAX_WDOGPARMS=4 -CONFIG_PREALLOC_WDOGS=8 -CONFIG_WDOG_INTRESERVE=1 -CONFIG_PREALLOC_TIMERS=8 - -# -# Tasks and Scheduling -# -# CONFIG_INIT_NONE is not set -CONFIG_INIT_ENTRYPOINT=y -# CONFIG_INIT_FILEPATH is not set -CONFIG_USER_ENTRYPOINT="nsh_main" -CONFIG_RR_INTERVAL=200 -# CONFIG_SCHED_SPORADIC is not set -CONFIG_TASK_NAME_SIZE=0 -CONFIG_MAX_TASKS=16 -# CONFIG_SCHED_HAVE_PARENT is not set -# CONFIG_SCHED_WAITPID is not set - -# -# Pthread Options -# -# CONFIG_MUTEX_TYPES is not set -CONFIG_NPTHREAD_KEYS=4 - -# -# Performance Monitoring -# -# CONFIG_SCHED_CPULOAD is not set -# CONFIG_SCHED_INSTRUMENTATION is not set - -# -# Files and I/O -# -CONFIG_DEV_CONSOLE=y -# CONFIG_FDCLONE_DISABLE is not set -# CONFIG_FDCLONE_STDIO is not set -CONFIG_SDCLONE_DISABLE=y -CONFIG_NFILE_DESCRIPTORS=8 -CONFIG_NFILE_STREAMS=8 -CONFIG_NAME_MAX=32 -# CONFIG_PRIORITY_INHERITANCE is not set - -# -# RTOS hooks -# -# CONFIG_BOARD_INITIALIZE is not set -# CONFIG_SCHED_STARTHOOK is not set -# CONFIG_SCHED_ATEXIT is not set -# CONFIG_SCHED_ONEXIT is not set - -# -# Signal Numbers -# -CONFIG_SIG_SIGUSR1=1 -CONFIG_SIG_SIGUSR2=2 -CONFIG_SIG_SIGALARM=3 -CONFIG_SIG_SIGCONDTIMEDOUT=16 -# CONFIG_MODULE is not set - -# -# Work queue support -# -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set -# CONFIG_SCHED_LPWORK is not set - -# -# Stack and heap information -# -CONFIG_IDLETHREAD_STACKSIZE=4096 -CONFIG_USERMAIN_STACKSIZE=4096 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=4096 -# CONFIG_LIB_SYSCALL is not set - -# -# Device Drivers -# -CONFIG_DISABLE_POLL=y -CONFIG_DEV_NULL=y -# CONFIG_DEV_ZERO is not set -# CONFIG_DEV_URANDOM is not set -# CONFIG_DEV_LOOP is not set - -# -# Buffering -# -# CONFIG_DRVR_WRITEBUFFER is not set -# CONFIG_DRVR_READAHEAD is not set -# CONFIG_RAMDISK is not set -# CONFIG_CAN is not set -# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set -# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set -# CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set -# CONFIG_I2C is not set -CONFIG_SPI=y -# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set -# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set -# CONFIG_ARCH_HAVE_SPI_BITORDER is not set -# CONFIG_SPI_SLAVE is not set -CONFIG_SPI_EXCHANGE=y -# CONFIG_SPI_CMDDATA is not set -# CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CS_DELAY_CONTROL is not set -# CONFIG_SPI_DRIVER is not set -# CONFIG_SPI_BITBANG is not set -# CONFIG_I2S is not set - -# -# Timer Driver Support -# -# CONFIG_TIMER is not set -# CONFIG_ONESHOT is not set -# CONFIG_RTC is not set -# CONFIG_WATCHDOG is not set -# CONFIG_ANALOG is not set -# CONFIG_AUDIO_DEVICES is not set -# CONFIG_VIDEO_DEVICES is not set -# CONFIG_BCH is not set -# CONFIG_INPUT is not set - -# -# IO Expander/GPIO Support -# -# CONFIG_IOEXPANDER is not set -# CONFIG_DEV_GPIO is not set - -# -# LCD Driver Support -# -CONFIG_LCD=y - -# -# Common Graphic LCD Settings -# -# CONFIG_LCD_CONSOLE is not set -CONFIG_LCD_NOGETRUN=y -CONFIG_LCD_MAXCONTRAST=63 -CONFIG_LCD_MAXPOWER=1 - -# -# Graphic LCD Devices -# -# CONFIG_LCD_P14201 is not set -# CONFIG_LCD_NOKIA6100 is not set -# CONFIG_LCD_MIO283QT2 is not set -# CONFIG_LCD_MIO283QT9A is not set -# CONFIG_LCD_UG9664HSWAG01 is not set -# CONFIG_LCD_SH1106_OLED_132 is not set -# CONFIG_LCD_UG2864HSWEG01 is not set -# CONFIG_LCD_UG2832HSWEG04 is not set -# CONFIG_LCD_SSD1351 is not set -# CONFIG_LCD_ST7565 is not set -# CONFIG_LCD_ST7567 is not set -# CONFIG_LCD_UG2864AMBAG01 is not set -# CONFIG_LCD_SSD1289 is not set -# CONFIG_LCD_SHARP_MEMLCD is not set -CONFIG_LCD_LANDSCAPE=y -# CONFIG_LCD_PORTRAIT is not set -# CONFIG_LCD_RPORTRAIT is not set -# CONFIG_LCD_RLANDSCAPE is not set -# CONFIG_LCD_ILI9341 is not set -# CONFIG_LCD_RA8875 is not set -# CONFIG_SLCD is not set - -# -# LED Support -# -# CONFIG_RGBLED is not set -# CONFIG_PCA9635PW is not set -# CONFIG_NCP5623C is not set -# CONFIG_MMCSD is not set -# CONFIG_MODEM is not set -# CONFIG_MTD is not set -# CONFIG_EEPROM is not set -# CONFIG_PIPES is not set -# CONFIG_PM is not set -# CONFIG_POWER is not set -# CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set -CONFIG_SERIAL=y -# CONFIG_DEV_LOWCONSOLE is not set -# CONFIG_SERIAL_REMOVABLE is not set -CONFIG_SERIAL_CONSOLE=y -# CONFIG_16550_UART is not set -# CONFIG_UART_SERIALDRIVER is not set -# CONFIG_UART0_SERIALDRIVER is not set -# CONFIG_UART1_SERIALDRIVER is not set -# CONFIG_UART2_SERIALDRIVER is not set -# CONFIG_UART3_SERIALDRIVER is not set -# CONFIG_UART4_SERIALDRIVER is not set -# CONFIG_UART5_SERIALDRIVER is not set -# CONFIG_UART6_SERIALDRIVER is not set -# CONFIG_UART7_SERIALDRIVER is not set -# CONFIG_UART8_SERIALDRIVER is not set -# CONFIG_SCI0_SERIALDRIVER is not set -# CONFIG_SCI1_SERIALDRIVER is not set -# CONFIG_USART0_SERIALDRIVER is not set -# CONFIG_USART1_SERIALDRIVER is not set -# CONFIG_USART2_SERIALDRIVER is not set -# CONFIG_USART3_SERIALDRIVER is not set -# CONFIG_USART4_SERIALDRIVER is not set -# CONFIG_USART5_SERIALDRIVER is not set -# CONFIG_USART6_SERIALDRIVER is not set -# CONFIG_USART7_SERIALDRIVER is not set -# CONFIG_USART8_SERIALDRIVER is not set -CONFIG_OTHER_UART_SERIALDRIVER=y -CONFIG_MCU_SERIAL=y -# CONFIG_STANDARD_SERIAL is not set -# CONFIG_SERIAL_IFLOWCONTROL is not set -# CONFIG_SERIAL_OFLOWCONTROL is not set -# CONFIG_SERIAL_DMA is not set -# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set -CONFIG_OTHER_SERIAL_CONSOLE=y -# CONFIG_NO_SERIAL_CONSOLE is not set -# CONFIG_PSEUDOTERM is not set -# CONFIG_USBDEV is not set -# CONFIG_USBHOST is not set -# CONFIG_HAVE_USBTRACE is not set -# CONFIG_DRIVERS_WIRELESS is not set -# CONFIG_DRIVERS_CONTACTLESS is not set - -# -# System Logging -# -# CONFIG_ARCH_SYSLOG is not set -# CONFIG_RAMLOG is not set -# CONFIG_SYSLOG_INTBUFFER is not set -# CONFIG_SYSLOG_TIMESTAMP is not set -CONFIG_SYSLOG_SERIAL_CONSOLE=y -# CONFIG_SYSLOG_CHAR is not set -CONFIG_SYSLOG_CONSOLE=y -# CONFIG_SYSLOG_NONE is not set -# CONFIG_SYSLOG_FILE is not set -# CONFIG_SYSLOG_CHARDEV is not set - -# -# Networking Support -# -# CONFIG_ARCH_HAVE_NET is not set -# CONFIG_ARCH_HAVE_PHY is not set -# CONFIG_NET is not set - -# -# Crypto API -# -# CONFIG_CRYPTO is not set - -# -# File Systems -# - -# -# File system configuration -# -# CONFIG_DISABLE_MOUNTPOINT is not set -# CONFIG_FS_AUTOMOUNTER is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_FS_READABLE is not set -# CONFIG_FS_WRITABLE is not set -# CONFIG_FS_NAMED_SEMAPHORES is not set -# CONFIG_FS_RAMMAP is not set -# CONFIG_FS_FAT is not set -# CONFIG_FS_NXFFS is not set -# CONFIG_FS_ROMFS is not set -# CONFIG_FS_TMPFS is not set -# CONFIG_FS_SMARTFS is not set -# CONFIG_FS_BINFS is not set -# CONFIG_FS_PROCFS is not set -# CONFIG_FS_UNIONFS is not set - -# -# Graphics Support -# -CONFIG_NX=y -CONFIG_NX_LCDDRIVER=y -CONFIG_NX_NPLANES=1 -CONFIG_NX_BGCOLOR=0x0 -CONFIG_NX_WRITEONLY=y -# CONFIG_NX_UPDATE is not set - -# -# Supported Pixel Depths -# -CONFIG_NX_DISABLE_1BPP=y -CONFIG_NX_DISABLE_2BPP=y -CONFIG_NX_DISABLE_4BPP=y -CONFIG_NX_DISABLE_8BPP=y -# CONFIG_NX_DISABLE_16BPP is not set -CONFIG_NX_DISABLE_24BPP=y -CONFIG_NX_DISABLE_32BPP=y -CONFIG_NX_PACKEDMSFIRST=y - -# -# Input Devices -# -# CONFIG_NX_XYINPUT is not set -CONFIG_NX_XYINPUT_NONE=y -# CONFIG_NX_XYINPUT_MOUSE is not set -# CONFIG_NX_XYINPUT_TOUCHSCREEN is not set -CONFIG_NX_KBD=y - -# -# Framed Window Borders -# -CONFIG_NXTK_BORDERWIDTH=4 -CONFIG_NXTK_DEFAULT_BORDERCOLORS=y -# CONFIG_NXTK_AUTORAISE is not set - -# -# Font Selections -# -CONFIG_NXFONTS_CHARBITS=7 -# CONFIG_NXFONT_MONO5X8 is not set -CONFIG_NXFONT_SANS17X22=y -# CONFIG_NXFONT_SANS20X26 is not set -# CONFIG_NXFONT_SANS23X27 is not set -# CONFIG_NXFONT_SANS22X29 is not set -# CONFIG_NXFONT_SANS28X37 is not set -# CONFIG_NXFONT_SANS39X48 is not set -# CONFIG_NXFONT_SANS17X23B is not set -# CONFIG_NXFONT_SANS20X27B is not set -# CONFIG_NXFONT_SANS22X29B is not set -# CONFIG_NXFONT_SANS28X37B is not set -# CONFIG_NXFONT_SANS40X49B is not set -# CONFIG_NXFONT_SERIF22X29 is not set -# CONFIG_NXFONT_SERIF29X37 is not set -# CONFIG_NXFONT_SERIF38X48 is not set -# CONFIG_NXFONT_SERIF22X28B is not set -# CONFIG_NXFONT_SERIF27X38B is not set -# CONFIG_NXFONT_SERIF38X49B is not set -# CONFIG_NXFONT_PIXEL_UNICODE is not set -# CONFIG_NXFONT_PIXEL_LCD_MACHINE is not set -# CONFIG_NXFONT_X11_MISC_FIXED_4X6 is not set -# CONFIG_NXFONT_X11_MISC_FIXED_5X7 is not set -# CONFIG_NXFONT_X11_MISC_FIXED_5X8 is not set -# CONFIG_NXFONT_X11_MISC_FIXED_6X9 is not set -# CONFIG_NXFONT_X11_MISC_FIXED_6X10 is not set -# CONFIG_NXFONT_X11_MISC_FIXED_6X12 is not set -# CONFIG_NXFONT_X11_MISC_FIXED_6X13 is not set -# CONFIG_NXFONT_X11_MISC_FIXED_6X13B is not set -# CONFIG_NXFONT_X11_MISC_FIXED_6X13O is not set -# CONFIG_NXFONT_X11_MISC_FIXED_7X13 is not set -# CONFIG_NXFONT_X11_MISC_FIXED_7X13B is not set -# CONFIG_NXFONT_X11_MISC_FIXED_7X13O is not set -# CONFIG_NXFONT_X11_MISC_FIXED_7X14 is not set -# CONFIG_NXFONT_X11_MISC_FIXED_7X14B is not set -# CONFIG_NXFONT_X11_MISC_FIXED_8X13 is not set -# CONFIG_NXFONT_X11_MISC_FIXED_8X13B is not set -# CONFIG_NXFONT_X11_MISC_FIXED_8X13O is not set -# CONFIG_NXFONT_X11_MISC_FIXED_9X15 is not set -# CONFIG_NXFONT_X11_MISC_FIXED_9X15B is not set -# CONFIG_NXFONT_X11_MISC_FIXED_9X18 is not set -# CONFIG_NXFONT_X11_MISC_FIXED_9X18B is not set -# CONFIG_NXFONT_X11_MISC_FIXED_10X20 is not set -# CONFIG_NXTERM is not set - -# -# NX Multi-user only options -# -# CONFIG_NX_MULTIUSER is not set - -# -# Memory Management -# -# CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=2 -CONFIG_ARCH_HAVE_HEAP2=y -CONFIG_HEAP2_BASE=0x01000000 -CONFIG_HEAP2_SIZE=2097152 -# CONFIG_GRAN is not set - -# -# Audio Support -# -# CONFIG_AUDIO is not set - -# -# Wireless Support -# - -# -# Binary Loader -# -# CONFIG_BINFMT_DISABLE is not set -# CONFIG_BINFMT_EXEPATH is not set -# CONFIG_NXFLAT is not set -# CONFIG_ELF is not set -CONFIG_BUILTIN=y -# CONFIG_PIC is not set -# CONFIG_SYMTAB_ORDEREDBYNAME is not set - -# -# Library Routines -# - -# -# Standard C Library Options -# -CONFIG_STDIO_BUFFER_SIZE=64 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=2 -CONFIG_LIB_HOMEDIR="/" -# CONFIG_LIBM is not set -# CONFIG_NOPRINTF_FIELDWIDTH is not set -# CONFIG_LIBC_FLOATINGPOINT is not set -CONFIG_LIBC_LONG_LONG=y -# CONFIG_LIBC_IOCTL_VARIADIC is not set -# CONFIG_LIBC_WCHAR is not set -# CONFIG_LIBC_LOCALE is not set -CONFIG_LIB_RAND_ORDER=1 -# CONFIG_EOL_IS_CR is not set -# CONFIG_EOL_IS_LF is not set -# CONFIG_EOL_IS_BOTH_CRLF is not set -CONFIG_EOL_IS_EITHER_CRLF=y -# CONFIG_LIBC_EXECFUNCS is not set -CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 -# CONFIG_LIBC_STRERROR is not set -# CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_ARCH_LOWPUTC=y -# CONFIG_LIBC_LOCALTIME is not set -# CONFIG_TIME_EXTENDED is not set -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set -# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set -CONFIG_ARCH_HAVE_TLS=y -# CONFIG_TLS is not set -# CONFIG_LIBC_NETDB is not set - -# -# Non-standard Library Support -# -# CONFIG_LIB_CRC64_FAST is not set -# CONFIG_LIB_KBDCODEC is not set -# CONFIG_LIB_SLCDCODEC is not set -# CONFIG_LIB_HEX2BIN is not set - -# -# Basic CXX Support -# -# CONFIG_C99_BOOL8 is not set -# CONFIG_HAVE_CXX is not set - -# -# Application Configuration -# - -# -# Built-In Applications -# -CONFIG_BUILTIN_PROXY_STACKSIZE=1024 - -# -# CAN Utilities -# - -# -# Examples -# -# CONFIG_EXAMPLES_CCTYPE is not set -# CONFIG_EXAMPLES_CHAT is not set -# CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_DHCPD is not set -# CONFIG_EXAMPLES_ELF is not set -# CONFIG_EXAMPLES_FTPC is not set -# CONFIG_EXAMPLES_FTPD is not set -# CONFIG_EXAMPLES_HELLO is not set -# CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_IGMP is not set -# CONFIG_EXAMPLES_JSON is not set -CONFIG_EXAMPLES_KEYPADTEST=y -CONFIG_EXAMPLES_KEYPAD_DEVNAME="/dev/keypad" -# CONFIG_EXAMPLES_KEYPADTEST_ENCODED is not set -# CONFIG_EXAMPLES_LCDRW is not set -# CONFIG_EXAMPLES_MEDIA is not set -# CONFIG_EXAMPLES_MM is not set -# CONFIG_EXAMPLES_MODBUS is not set -# CONFIG_EXAMPLES_MOUNT is not set -# CONFIG_EXAMPLES_NRF24L01TERM is not set -CONFIG_EXAMPLES_NSH=y -# CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXFFS is not set -CONFIG_EXAMPLES_NXHELLO=y -CONFIG_EXAMPLES_NXHELLO_VPLANE=0 -CONFIG_EXAMPLES_NXHELLO_DEVNO=0 -CONFIG_EXAMPLES_NXHELLO_BPP=16 - -# -# Example Color Configuration -# -CONFIG_EXAMPLES_NXHELLO_DEFAULT_COLORS=y - -# -# Example Font Configuration -# -CONFIG_EXAMPLES_NXHELLO_DEFAULT_FONT=y -# CONFIG_EXAMPLES_NXHELLO_EXTERNINIT is not set -CONFIG_EXAMPLES_NXIMAGE=y -CONFIG_EXAMPLES_NXIMAGE_VPLANE=0 -CONFIG_EXAMPLES_NXIMAGE_DEVNO=0 -CONFIG_EXAMPLES_NXIMAGE_BPP=16 -# CONFIG_EXAMPLES_NXIMAGE_GREYSCALE is not set -CONFIG_EXAMPLES_NXIMAGE_XSCALEp5=y -CONFIG_EXAMPLES_NXIMAGE_XSCALE1p0=y -# CONFIG_EXAMPLES_NXIMAGE_XSCALE1p5 is not set -# CONFIG_EXAMPLES_NXIMAGE_XSCALE2p0 is not set -CONFIG_EXAMPLES_NXIMAGE_YSCALEp5=y -CONFIG_EXAMPLES_NXIMAGE_YSCALE1p0=y -# CONFIG_EXAMPLES_NXIMAGE_YSCALE1p5 is not set -# CONFIG_EXAMPLES_NXIMAGE_YSCALE2p0 is not set -CONFIG_EXAMPLES_NXLINES=y -CONFIG_EXAMPLES_NXLINES_VPLANE=0 -CONFIG_EXAMPLES_NXLINES_DEVNO=0 -CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS=y -CONFIG_EXAMPLES_NXLINES_LINEWIDTH=4 -CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=2 -CONFIG_EXAMPLES_NXLINES_BPP=16 -# CONFIG_EXAMPLES_NXLINES_EXTERNINIT is not set -# CONFIG_EXAMPLES_NXTERM is not set -CONFIG_EXAMPLES_NXTEXT=y - -# -# Basic Configuration of the example -# -CONFIG_EXAMPLES_NXTEXT_VPLANE=0 -CONFIG_EXAMPLES_NXTEXT_DEVNO=0 -CONFIG_EXAMPLES_NXTEXT_BPP=16 -CONFIG_EXAMPLES_NXTEXT_BMCACHE=128 -CONFIG_EXAMPLES_NXTEXT_GLCACHE=16 - -# -# Example Color Configuration -# -CONFIG_EXAMPLES_NXTEXT_DEFAULT_COLORS=y - -# -# Example Font Configuration -# -# CONFIG_EXAMPLES_NXTEXT_DEFAULT_FONT is not set -CONFIG_EXAMPLES_NXTEXT_BGFONTID=14 -CONFIG_EXAMPLES_NXTEXT_PUFONTID=0 -# CONFIG_EXAMPLES_NXTEXT_EXTERNINIT is not set -# CONFIG_EXAMPLES_OSTEST is not set -# CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_PPPD is not set -# CONFIG_EXAMPLES_RFID_READUID is not set -# CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_SENDMAIL is not set -# CONFIG_EXAMPLES_SERIALBLASTER is not set -# CONFIG_EXAMPLES_SERIALRX is not set -# CONFIG_EXAMPLES_SERLOOP is not set -# CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART is not set -# CONFIG_EXAMPLES_SMART_TEST is not set -# CONFIG_EXAMPLES_SMP is not set -# CONFIG_EXAMPLES_TCPECHO is not set -# CONFIG_EXAMPLES_TELNETD is not set -# CONFIG_EXAMPLES_TIFF is not set -# CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_USBSERIAL is not set -# CONFIG_EXAMPLES_USBTERM is not set -# CONFIG_EXAMPLES_WATCHDOG is not set -# CONFIG_EXAMPLES_WEBSERVER is not set - -# -# File System Utilities -# -# CONFIG_FSUTILS_INIFILE is not set - -# -# GPS Utilities -# -# CONFIG_GPSUTILS_MINMEA_LIB is not set - -# -# Graphics Support -# -# CONFIG_TIFF is not set -# CONFIG_GRAPHICS_TRAVELER is not set - -# -# Interpreters -# -# CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_MICROPYTHON is not set -# CONFIG_INTERPRETERS_MINIBASIC is not set -# CONFIG_INTERPRETERS_PCODE is not set - -# -# FreeModBus -# -# CONFIG_MODBUS is not set - -# -# Network Utilities -# -# CONFIG_NETUTILS_CODECS is not set -# CONFIG_NETUTILS_ESP8266 is not set -# CONFIG_NETUTILS_FTPC is not set -# CONFIG_NETUTILS_JSON is not set -# CONFIG_NETUTILS_SMTP is not set - -# -# NSH Library -# -CONFIG_NSH_LIBRARY=y -# CONFIG_NSH_MOTD is not set - -# -# Command Line Configuration -# -CONFIG_NSH_READLINE=y -# CONFIG_NSH_CLE is not set -CONFIG_NSH_LINELEN=64 -# CONFIG_NSH_DISABLE_SEMICOLON is not set -CONFIG_NSH_CMDPARMS=y -CONFIG_NSH_MAXARGUMENTS=6 -CONFIG_NSH_ARGCAT=y -CONFIG_NSH_NESTDEPTH=3 -# CONFIG_NSH_DISABLEBG is not set -CONFIG_NSH_BUILTIN_APPS=y - -# -# Disable Individual commands -# -# CONFIG_NSH_DISABLE_ADDROUTE is not set -# CONFIG_NSH_DISABLE_BASENAME is not set -# CONFIG_NSH_DISABLE_CAT is not set -# CONFIG_NSH_DISABLE_CD is not set -# CONFIG_NSH_DISABLE_CP is not set -# CONFIG_NSH_DISABLE_CMP is not set -CONFIG_NSH_DISABLE_DATE=y -# CONFIG_NSH_DISABLE_DD is not set -# CONFIG_NSH_DISABLE_DF is not set -# CONFIG_NSH_DISABLE_DELROUTE is not set -# CONFIG_NSH_DISABLE_DIRNAME is not set -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HELP is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -CONFIG_NSH_DISABLE_IFUPDOWN=y -# CONFIG_NSH_DISABLE_KILL is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -CONFIG_NSH_DISABLE_LOSMART=y -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_MB is not set -# CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_MH is not set -# CONFIG_NSH_DISABLE_MOUNT is not set -# CONFIG_NSH_DISABLE_MV is not set -# CONFIG_NSH_DISABLE_MW is not set -# CONFIG_NSH_DISABLE_POWEROFF is not set -CONFIG_NSH_DISABLE_PRINTF=y -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_PWD is not set -# CONFIG_NSH_DISABLE_RM is not set -# CONFIG_NSH_DISABLE_RMDIR is not set -# CONFIG_NSH_DISABLE_SET is not set -# CONFIG_NSH_DISABLE_SH is not set -CONFIG_NSH_DISABLE_SHUTDOWN=y -# CONFIG_NSH_DISABLE_SLEEP is not set -# CONFIG_NSH_DISABLE_TIME is not set -# CONFIG_NSH_DISABLE_TEST is not set -# CONFIG_NSH_DISABLE_UMOUNT is not set -# CONFIG_NSH_DISABLE_UNAME is not set -# CONFIG_NSH_DISABLE_UNSET is not set -# CONFIG_NSH_DISABLE_USLEEP is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_NSH_MMCSDMINOR=0 - -# -# Configure Command Options -# -CONFIG_NSH_CMDOPT_DF_H=y -CONFIG_NSH_CODECS_BUFSIZE=128 -CONFIG_NSH_CMDOPT_HEXDUMP=y -CONFIG_NSH_FILEIOSIZE=1024 - -# -# Scripting Support -# -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_ITEF is not set -# CONFIG_NSH_DISABLE_LOOPS is not set - -# -# Console Configuration -# -CONFIG_NSH_CONSOLE=y -# CONFIG_NSH_ALTCONDEV is not set -# CONFIG_NSH_ARCHINIT is not set -# CONFIG_NSH_LOGIN is not set -# CONFIG_NSH_CONSOLE_LOGIN is not set - -# -# NxWidgets/NxWM -# - -# -# Platform-specific Support -# -# CONFIG_PLATFORM_CONFIGDATA is not set - -# -# System Libraries and NSH Add-Ons -# -# CONFIG_SYSTEM_CLE is not set -# CONFIG_SYSTEM_CUTERM is not set -# CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set -# CONFIG_SYSTEM_HEXED is not set -# CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_RAMTEST is not set -CONFIG_READLINE_HAVE_EXTMATCH=y -CONFIG_SYSTEM_READLINE=y -CONFIG_READLINE_ECHO=y -# CONFIG_READLINE_TABCOMPLETION is not set -# CONFIG_READLINE_CMD_HISTORY is not set -# CONFIG_SYSTEM_SUDOKU is not set -# CONFIG_SYSTEM_TEE is not set -# CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_VI is not set -# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/compal_e99/nsh_highram/setenv.sh b/configs/compal_e99/nsh_highram/setenv.sh deleted file mode 100755 index 16a2fe30fa..0000000000 --- a/configs/compal_e99/nsh_highram/setenv.sh +++ /dev/null @@ -1,63 +0,0 @@ -#!/bin/bash -# c5471evm/nsh/setenv.sh -# -# Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if [ "$_" = "$0" ] ; then - echo "You must source this script, not run it!" 1>&2 - exit 1 -fi - -WD=`pwd` -if [ ! -x "setenv.sh" ]; then - echo "This script must be executed from the top-level NuttX build directory" - exit 1 -fi - -if [ -z "${PATH_ORIG}" ]; then - export PATH_ORIG="${PATH}" -fi - -# This is the Cygwin path to the location where I installed the CodeSourcery -# toolchain under windows. You will also have to edit this if you install -# the CodeSourcery toolchain in any other location -# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" -# export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" - -# This is the Cygwin path to the location where I build the buildroot -# toolchain. -export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" - -# Add the path to the toolchain to the PATH varialble -export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" - -echo "PATH : ${PATH}" diff --git a/configs/compal_e99/scripts/compalram.ld b/configs/compal_e99/scripts/compalram.ld deleted file mode 100644 index 52554ddacb..0000000000 --- a/configs/compal_e99/scripts/compalram.ld +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Linker script for running from internal SRAM on Compal phones - * - * This script is tailored specifically to the requirements imposed - * on us by the Compal bootloader. - * - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(__start) -MEMORY -{ - /* compal-loaded binary: our text, initialized data */ - LRAM (rw) : ORIGIN = 0x00800000, LENGTH = 0x00020000 - /* compal-loaded binary: our unitialized data, stacks, heap */ - IRAM (rw) : ORIGIN = 0x00820000, LENGTH = 0x00020000 -} -SECTIONS -{ - . = 0x800000; - - /* romloader data section, contains passthru interrupt vectors */ - .compal.loader (NOLOAD) : { . = 0x100; } > LRAM - - /* image signature (prepended by osmocon according to phone type) */ - .compal.header (NOLOAD) : { . = 4; } > LRAM - - /* initialization code */ - . = ALIGN(4); - .text.start : { - PROVIDE(__start = .); - KEEP(*(.text.start)) - *(.text.start) - } > LRAM - - /* exception vectors from 0x80001c to 0x800034 */ - .text.exceptions 0x80001c : AT (LOADADDR(.text.start) + SIZEOF(.text.start)) { - KEEP(*(.text.exceptions)) - * (.text.exceptions) - . = ALIGN(4); - } > LRAM - PROVIDE(_exceptions = LOADADDR(.text.exceptions)); - - /* code */ - . = ALIGN(4); - .text (LOADADDR(.text.exceptions) + SIZEOF(.text.exceptions)) : - AT (LOADADDR(.text.exceptions) + SIZEOF(.text.exceptions)) { - /* regular code */ - *(.text*) - /* always-in-ram code */ - *(.ramtext*) - /* gcc voodoo */ - *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx) - . = ALIGN(4); - } > LRAM - PROVIDE(_text_start = LOADADDR(.text)); - PROVIDE(_text_end = LOADADDR(.text) + SIZEOF(.text)); - - /* constructor pointers */ - .ctors : { - /* ctor count */ - LONG(SIZEOF(.ctors) / 4 - 2) - /* ctor pointers */ - KEEP(*(SORT(.ctors))) - /* end of list */ - LONG(0) - } > LRAM - PROVIDE(_ctor_start = LOADADDR(.ctors)); - PROVIDE(_ctor_end = LOADADDR(.ctors) + SIZEOF(.ctors)); - - /* destructor pointers */ - .dtors : { - /* dtor count */ - LONG(SIZEOF(.dtors) / 4 - 2) - /* dtor pointers */ - KEEP(*(SORT(.dtors))) - /* end of list */ - LONG(0) - } > LRAM - PROVIDE(_dtor_start = LOADADDR(.dtors)); - PROVIDE(_dtor_end = LOADADDR(.dtors) + SIZEOF(.dtors)); - - /* read-only data */ - . = ALIGN(4); - .rodata : { - *(.rodata*) - } > LRAM - PROVIDE(_rodata_start = LOADADDR(.rodata)); - PROVIDE(_rodata_end = LOADADDR(.rodata) + SIZEOF(.rodata)); - - /* initialized data */ - . = ALIGN(4); - .data : { - *(.data) - } > LRAM - PROVIDE(_data_start = LOADADDR(.data)); - PROVIDE(_data_end = LOADADDR(.data) + SIZEOF(.data)); - - /* pic offset tables */ - . = ALIGN(4); - .got : { - *(.got) - *(.got.plt) *(.igot.plt) *(.got) *(.igot) - } > LRAM - PROVIDE(_got_start = LOADADDR(.got)); - PROVIDE(_got_end = LOADADDR(.got) + SIZEOF(.got)); - - /* uninitialized data */ - .bss (NOLOAD) : { - . = ALIGN(4); - __bss_start = .; - _sbss = ABSOLUTE(.); - *(.bss) - _ebss = ABSOLUTE(.); - } > IRAM - . = ALIGN(4); - __bss_end = .; - PROVIDE(_bss_start = __bss_start); - PROVIDE(_bss_end = __bss_end); - - /* end of image */ - . = ALIGN(4); - _end = .; - PROVIDE(end = .); -} diff --git a/configs/compal_e99/scripts/highram.ld b/configs/compal_e99/scripts/highram.ld deleted file mode 100644 index db72f251aa..0000000000 --- a/configs/compal_e99/scripts/highram.ld +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Linker script for running from internal SRAM on Compal phones - * - * This script is tailored specifically to the requirements imposed - * on us by the Compal bootloader. - * - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(__start) -MEMORY -{ - /* 0x800000-0xa00000 */ - /* compal-loaded binary: our text, initialized data */ - LRAM (rw) : ORIGIN = 0x00800000, LENGTH = 0x00020000 - TRAM (rw) : ORIGIN = 0x00820000, LENGTH = 0x0001d000 - /* compal-loaded binary: our unitialized data, stacks, heap */ - IRAM (rw) : ORIGIN = 0x0083d000, LENGTH = 0x00002000 -} -SECTIONS -{ - . = 0x800000; - - /* romloader data section, contains passthru interrupt vectors */ - .compal.loader (NOLOAD) : { . = 0x100; } > LRAM - - /* image signature (prepended by osmocon according to phone type) */ - .compal.header (NOLOAD) : { . = 4; } > LRAM - - /* initialization code */ - . = ALIGN(4); - .text.start : { - PROVIDE(__start = .); - KEEP(*(.text.start)) - *(.text.start) - } > TRAM - - /* exception vectors from 0x80001c to 0x800034 */ - .text.exceptions 0x80001c : AT (LOADADDR(.text.start) + SIZEOF(.text.start)) { - KEEP(*(.text.exceptions)) - * (.text.exceptions) - . = ALIGN(4); - } > LRAM - PROVIDE(_exceptions = LOADADDR(.text.exceptions)); - - /* code */ - . = ALIGN(4); - .text (LOADADDR(.text.exceptions) + SIZEOF(.text.exceptions)) : - AT (LOADADDR(.text.exceptions) + SIZEOF(.text.exceptions)) { - /* regular code */ - *(.text*) - /* always-in-ram code */ - *(.ramtext*) - /* gcc voodoo */ - *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx) - . = ALIGN(4); - } > TRAM - PROVIDE(_text_start = LOADADDR(.text)); - PROVIDE(_text_end = LOADADDR(.text) + SIZEOF(.text)); - - /* constructor pointers */ - .ctors : { - /* ctor count */ - LONG(SIZEOF(.ctors) / 4 - 2) - /* ctor pointers */ - KEEP(*(SORT(.ctors))) - /* end of list */ - LONG(0) - } > TRAM - PROVIDE(_ctor_start = LOADADDR(.ctors)); - PROVIDE(_ctor_end = LOADADDR(.ctors) + SIZEOF(.ctors)); - - /* destructor pointers */ - .dtors : { - /* dtor count */ - LONG(SIZEOF(.dtors) / 4 - 2) - /* dtor pointers */ - KEEP(*(SORT(.dtors))) - /* end of list */ - LONG(0) - } > TRAM - PROVIDE(_dtor_start = LOADADDR(.dtors)); - PROVIDE(_dtor_end = LOADADDR(.dtors) + SIZEOF(.dtors)); - - /* read-only data */ - . = ALIGN(4); - .rodata : { - *(.rodata*) - } > TRAM - PROVIDE(_rodata_start = LOADADDR(.rodata)); - PROVIDE(_rodata_end = LOADADDR(.rodata) + SIZEOF(.rodata)); - - /* initialized data */ - . = ALIGN(4); - .data : { - *(.data) - } > TRAM - PROVIDE(_data_start = LOADADDR(.data)); - PROVIDE(_data_end = LOADADDR(.data) + SIZEOF(.data)); - - /* pic offset tables */ - . = ALIGN(4); - .got : { - *(.got) - *(.got.plt) *(.igot.plt) *(.got) *(.igot) - } > TRAM - PROVIDE(_got_start = LOADADDR(.got)); - PROVIDE(_got_end = LOADADDR(.got) + SIZEOF(.got)); - - /* uninitialized data */ - .bss (NOLOAD) : { - . = ALIGN(4); - __bss_start = .; - _sbss = ABSOLUTE(.); - *(.bss) - _ebss = ABSOLUTE(.); - } > IRAM - . = ALIGN(4); - __bss_end = .; - PROVIDE(_bss_start = __bss_start); - PROVIDE(_bss_end = __bss_end); - - /* end of image */ - . = ALIGN(4); - _end = .; - PROVIDE(end = .); -} diff --git a/configs/compal_e99/src/.gitignore b/configs/compal_e99/src/.gitignore deleted file mode 100644 index 726d936e1e..0000000000 --- a/configs/compal_e99/src/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/.depend -/Make.dep diff --git a/configs/compal_e99/src/Makefile b/configs/compal_e99/src/Makefile deleted file mode 100644 index c2ad1cc776..0000000000 --- a/configs/compal_e99/src/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -############################################################################ -# configs/compal_e99/src/Makefile -# -# Copyright (C) 2007, 2008, 2015 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Copyright (C) 2011 Stefan Richter. All rights reserved. -# Author: Stefan Richter -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - --include $(TOPDIR)/Make.defs - -ASRCS = -CSRCS = boot.c ssd1783.c - -include $(TOPDIR)/configs/Board.mk diff --git a/configs/compal_e99/src/boot.c b/configs/compal_e99/src/boot.c deleted file mode 100644 index 8bc7061daf..0000000000 --- a/configs/compal_e99/src/boot.c +++ /dev/null @@ -1,75 +0,0 @@ -/**************************************************************************** - * configs/compal_e99/boot.c - * - * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_app_initialize - * - * Description: - * Perform architecture specific initialization - * - * Input Parameters: - * arg - The boardctl() argument is passed to the board_app_initialize() - * implementation without modification. The argument has no - * meaning to NuttX; the meaning of the argument is a contract - * between the board-specific initalization logic and the the - * matching application logic. The value cold be such things as a - * mode enumeration value, a set of DIP switch switch settings, a - * pointer to configuration data read from a file or serial FLASH, - * or whatever you would like to do with it. Every implementation - * should accept zero/NULL as a default configuration. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_LIB_BOARDCTL -int board_app_initialize(uintptr_t arg) -{ - return 0; -} -#endif /* CONFIG_LIB_BOARDCTL */ diff --git a/configs/compal_e99/src/ssd1783.c b/configs/compal_e99/src/ssd1783.c deleted file mode 100644 index 75725fc920..0000000000 --- a/configs/compal_e99/src/ssd1783.c +++ /dev/null @@ -1,542 +0,0 @@ -/************************************************************************************ - * nuttx/configs/compal_e99/src/ssd1783.c - * - * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Laurent Latil - * Denis 'GNUtoo' Carikli - * Alan Carvalho de Assis - * - * This driver for SSD1783 used part of SSD1783 driver developed by - * Christian Vogel for Osmocom-BB and relicensed - * to BSD with permission from author. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "up_arch.h" -#include "ssd1783.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Color depth and format */ - -#define LCD_BPP 16 -#define LCD_COLORFMT FB_FMT_RGB16_555 - -/* Display Resolution */ - -#define LCD_XRES 98 -#define LCD_YRES 67 - -/* This should be put elsewhere */ - -#ifdef __CC_ARM /* ARM Compiler */ -#define lcd_inline static __inline -#elif defined (__ICCARM__) /* for IAR Compiler */ -#define lcd_inline inline -#elif defined (__GNUC__) /* GNU GCC Compiler */ -#define lcd_inline static __inline -#else -#define lcd_inline static -#endif - -static void lcd_clear(void); -static void fb_ssd1783_send_cmdlist(const struct ssd1783_cmdlist *p); - -/* LCD Data Transfer Methods */ -int lcd_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buffer, - size_t npixels); -int lcd_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, - size_t npixels); - -/* LCD Configuration */ -static int lcd_getvideoinfo(FAR struct lcd_dev_s *dev, - FAR struct fb_videoinfo_s *vinfo); -static int lcd_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno, - FAR struct lcd_planeinfo_s *pinfo); - -/* LCD RGB Mapping */ -#ifdef CONFIG_FB_CMAP -# error "RGB color mapping not supported by this driver" -#endif - -/* Cursor Controls */ -#ifdef CONFIG_FB_HWCURSOR -# error "Cursor control not supported by this driver" -#endif - -/* LCD Specific Controls */ -static int lcd_getpower(struct lcd_dev_s *dev); -static int lcd_setpower(struct lcd_dev_s *dev, int power); -static int lcd_getcontrast(struct lcd_dev_s *dev); -static int lcd_setcontrast(struct lcd_dev_s *dev, unsigned int contrast); - -/* Initialization (LCD ctrl / backlight) */ -static inline void lcd_initialize(void); - -/************************************************************************************** - * Private Data - **************************************************************************************/ - -/* This is working memory allocated by the LCD driver for each LCD device - * and for each color plane. This memory will hold one raster line of data. - * The size of the allocated run buffer must therefore be at least - * (bpp * xres / 8). Actual alignment of the buffer must conform to the - * bitwidth of the underlying pixel type. - * - * If there are multiple planes, they may share the same working buffer - * because different planes will not be operate on concurrently. However, - * if there are multiple LCD devices, they must each have unique run buffers. - */ - -static uint16_t g_runbuffer[LCD_XRES]; - -/* This structure describes the overall LCD video controller */ - -static const struct fb_videoinfo_s g_videoinfo = -{ - .fmt = LCD_COLORFMT, /* Color format: RGB16-565: RRRR RGGG GGGB BBBB */ - .xres = LCD_XRES, /* Horizontal resolution in pixel columns */ - .yres = LCD_YRES, /* Vertical resolutiSend a command list to the LCD panelon in pixel rows */ - .nplanes = 1, /* Number of color planes supported */ -}; - -/* This is the standard, NuttX Plane information object */ - -static const struct lcd_planeinfo_s g_planeinfo = -{ - .putrun = lcd_putrun, /* Put a run into LCD memory */ -// .getrun = lcd_getrun, /* Get a run from LCD memory */ - .buffer = (uint8_t*) g_runbuffer, /* Run scratch buffer */ - .bpp = LCD_BPP, /* Bits-per-pixel */ -}; - -/* This is the standard, NuttX LCD driver object */ - -static struct ssd1783_dev_s g_lcddev = -{ - .dev = - { - /* LCD Configuration */ - - .getvideoinfo = lcd_getvideoinfo, - .getplaneinfo = lcd_getplaneinfo, - -/* LCD RGB Mapping -- Not supported */ -/* Cursor Controls -- Not supported */ - -/* LCD Specific Controls */ - .getpower = lcd_getpower, - .setpower = lcd_setpower, -// .getcontrast = lcd_getcontrast, -// .setcontrast = lcd_setcontrast, - }, - .power=0 -}; - -/* we trust gcc to move this expensive bitshifting out of - * the loops in the drawing funtcions - */ - -static uint8_t rgb_to_pixel(uint16_t color) -{ - uint8_t ret; - - ret = (FB_COLOR_TO_R(color) & 0xe0); /* 765 = RRR */ - ret |= (FB_COLOR_TO_G(color) & 0xe0) >> 3; /* 432 = GGG */ - ret |= (FB_COLOR_TO_B(color) & 0xc0) >> 6; /* 10 = BB */ - - return ret; -} - -/* somehow the palette is messed up, RRR seems to have the - * bits reversed! R0 R1 R2 G G G B B ---> R2 R1 R0 G G G B B - */ - -uint8_t fix_rrr(uint8_t v) -{ - return (v & 0x5f) | (v & 0x80) >> 2 | (v & 0x20) << 2; -} - - -lcd_inline void write_data(uint16_t datain) -{ - uint16_t dataout = 0x0100 | fix_rrr(rgb_to_pixel(datain)); - uwire_xfer(SSD1783_DEV_ID,SSD1783_UWIRE_BITLEN,&dataout, NULL); -} - -static void fb_ssd1783_send_cmdlist(const struct ssd1783_cmdlist *p) -{ - int i=0; - - while (p->is_cmd != END) - { - uint16_t sendcmd = p->data; - if (p->is_cmd == DATA) - { - sendcmd |= 0x0100; /* 9th bit is cmd/data flag */ - } - - uwire_xfer(SSD1783_DEV_ID, SSD1783_UWIRE_BITLEN, &sendcmd, NULL); - p++; - i++; - } -} - -static void lcd_write_prepare(unsigned int x1, unsigned int x2, unsigned int y1, unsigned int y2) -{; - DEBUGASSERT( (x1 < x2 )&& (y1 < y2)); - struct ssd1783_cmdlist prepare_disp_write_cmds[] = { - { CMD, 0x15 }, /* set column address */ - { DATA, x1 }, - { DATA, x2 }, - { CMD, 0x75 }, /* set page address (Y) */ - { DATA, y1 }, - { DATA, y2 }, - { CMD, 0x5c }, /* enter write display ram mode */ - { END, 0x00 } - }; - - _info("x1:%d, x2:%d, y1:%d, y2:%d\n",x1, x2,y1, y2); - fb_ssd1783_send_cmdlist(prepare_disp_write_cmds); -} - -/************************************************************************************** - * Name: lcd_putrun - * - * Description: - * This method can be used to write a partial raster line to the LCD: - * - * row - Starting row to write to (range: 0 <= row < yres) - * col - Starting column to write to (range: 0 <= col <= xres-npixels) - * buffer - The buffer containing the run to be written to the LCD - * npixels - The number of pixels to write to the LCD - * (range: 0 < npixels <= xres-col) - * - **************************************************************************************/ - -int lcd_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buffer, - size_t npixels) -{ - int i; - FAR const uint16_t *src = (FAR const uint16_t*) buffer; - - /* Buffer must be provided and aligned to a 16-bit address boundary */ - DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); - - - /* Write the run to GRAM. */ - lcd_write_prepare(col,col+npixels, row,row+1); - - for (i = 0; i < npixels; i++) - { - write_data(*src++); - } - fb_ssd1783_send_cmdlist(nop); - - return OK; -} - -/************************************************************************************** - * Name: lcd_getrun - * - * Description: - * This method can be used to read a partial raster line from the LCD: - * - * row - Starting row to read from (range: 0 <= row < yres) - * col - Starting column to read read (range: 0 <= col <= xres-npixels) - * buffer - The buffer in which to return the run read from the LCD - * npixels - The number of pixels to read from the LCD - * (range: 0 < npixels <= xres-col) - * - **************************************************************************************/ - -int lcd_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, - size_t npixels) -{ - ginfo("Not implemented\n"); - return -ENOSYS; -} - -/************************************************************************************** - * Name: lcd_getvideoinfo - * - * Description: - * Get information about the LCD video controller configuration. - * - **************************************************************************************/ - -static int lcd_getvideoinfo(FAR struct lcd_dev_s *dev, - FAR struct fb_videoinfo_s *vinfo) -{ - DEBUGASSERT(dev && vinfo);ginfo("fmt: %d xres: %d yres: %d nplanes: %d\n", - g_videoinfo.fmt, g_videoinfo.xres, g_videoinfo.yres, g_videoinfo.nplanes); - memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); - return OK; -} - -/************************************************************************************** - * Name: lcd_getplaneinfo - * - * Description: - * Get information about the configuration of each LCD color plane. - * - **************************************************************************************/ - -static int lcd_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno, - FAR struct lcd_planeinfo_s *pinfo) -{ - DEBUGASSERT(dev && pinfo && planeno == 0);ginfo("planeno: %d bpp: %d\n", planeno, g_planeinfo.bpp); - memcpy(pinfo, &g_planeinfo, sizeof(struct lcd_planeinfo_s)); - return OK; -} - -/************************************************************************************** - * Name: lcd_getpower - * - * Description: - * Get the LCD panel power status (0: full off - CONFIG_LCD_MAXPOWER: full on). On - * backlit LCDs, this setting may correspond to the backlight setting. - * - **************************************************************************************/ - -static int lcd_getpower(struct lcd_dev_s *dev) -{ - ginfo("power: %d\n", 0); - return g_lcddev.power; -} - -/************************************************************************************** - * Name: lcd_setpower - * - * Description: - * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: full on). - * Used here to set pwm duty on timer used for backlight. - * - **************************************************************************************/ - -static int lcd_setpower(struct lcd_dev_s *dev, int power) -{ - uint16_t reg; - - if (g_lcddev.power == power) { - return OK; - } - - ginfo("power: %d\n", power); - DEBUGASSERT(power <= CONFIG_LCD_MAXPOWER); - - /* Set new power level */ - reg = getreg16(ASIC_CONF_REG); - if (power) - { - reg = getreg16(ASIC_CONF_REG); - /* LCD Set I/O(3) / SA0 to I/O(3) mode */ - reg &= ~( (1 << 12) | (1 << 10) | (1 << 7) | (1 << 1)) ; - /* don't set function pins to I2C Mode, C155 uses UWire */ - /* TWL3025: Set SPI+RIF RX clock to rising edge */ - reg |= (1 << 13) | (1 << 14); - putreg16(reg, ASIC_CONF_REG); - - /* LCD Set I/O(3) to output mode and enable C155 backlight (IO1) */ - /* FIXME: Put the display backlight control to backlight.c */ - reg = getreg16(IO_CNTL_REG); - reg &= ~( (1 << 3) | (1 << 1)); - putreg16(reg, IO_CNTL_REG); - - /* LCD Set I/O(3) output low */ - reg = getreg16(ARMIO_LATCH_OUT); - reg &= ~(1 << 3); - reg |= (1 << 1); - putreg16(reg, ARMIO_LATCH_OUT); - } - else - { - ginfo("powering LCD off...\n"); - /* Switch pin from PWL to LT */ - reg &= ~ASCONF_PWL_ENA; - putreg8(reg, ASIC_CONF_REG); - /* Disable pwl */ - putreg8(0x00, PWL_REG(PWL_CTRL)); - } - return OK; -} - - -/************************************************************************************** - * Name: lcd_getcontrast - * - * Description: - * Get the current contrast setting (0-CONFIG_LCD_MAXCONTRAST). - * - **************************************************************************************/ - -static int lcd_getcontrast(struct lcd_dev_s *dev) -{ - ginfo("Not implemented\n"); - return -ENOSYS; -} - -/************************************************************************************** - * Name: lcd_setcontrast - * - * Description: - * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). - * - **************************************************************************************/ - -static int lcd_setcontrast(struct lcd_dev_s *dev, unsigned int contrast) -{ - ginfo("Not implemented\n"); - return -ENOSYS; -} - -/************************************************************************************** - * Name: lcd_lcdinitialize - * - * Description: - * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). - * - **************************************************************************************/ -static inline void lcd_initialize(void) -{ - ginfo("%s: initializing LCD.\n",__FUNCTION__); - calypso_reset_set(RESET_EXT, 0); - usleep(5000); - uwire_init(); - usleep(5000); - fb_ssd1783_send_cmdlist(ssd1783_initdata); -} - -/************************************************************************************** - * Public Functions - **************************************************************************************/ - - -/************************************************************************************** - * Name: board_lcd_initialize - * - * Description: - * Initialize the LCD video hardware. The initial state of the LCD is fully - * initialized, display memory cleared, and the LCD ready to use, but with the power - * setting at 0 (full off). - * - **************************************************************************************/ - -int board_lcd_initialize(void) -{ - ginfo("Initializing\n"); - - lcd_initialize(); - - /* Clear the display */ - lcd_clear(); - - return OK; -} - -/************************************************************************************** - * Name: board_lcd_getdev - * - * Description: - * Return a a reference to the LCD object for the specified LCD. This allows support - * for multiple LCD devices. - * - **************************************************************************************/ - -FAR struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - DEBUGASSERT(lcddev == 0); - return &g_lcddev.dev; -} - - -/************************************************************************************** - * Name: board_lcd_uninitialize - * - * Description: - * Un-initialize the LCD support - * - **************************************************************************************/ - -void board_lcd_uninitialize(void) -{ - lcd_setpower(&g_lcddev.dev, 0); -} - -/************************************************************************************** - * Name: lcd_clear - * - * Description: - * Fill the LCD ctrl memory with given color - * - **************************************************************************************/ - -void lcd_clear() -{ - struct ssd1783_cmdlist prepare_disp_write_cmds[] = - { - { CMD, 0x8E }, - { DATA, 0x00 }, - { DATA, 0x00 }, - { DATA, LCD_XRES }, - { DATA, LCD_YRES }, - { END, 0x00 } - }; - - struct ssd1783_cmdlist nop_command[] = - { - { CMD, 0x25 }, // NOP command - { END, 0x00 } - }; - - fb_ssd1783_send_cmdlist(prepare_disp_write_cmds); - fb_ssd1783_send_cmdlist(nop_command); -} diff --git a/configs/compal_e99/src/ssd1783.h b/configs/compal_e99/src/ssd1783.h deleted file mode 100644 index 50ec449259..0000000000 --- a/configs/compal_e99/src/ssd1783.h +++ /dev/null @@ -1,110 +0,0 @@ -#ifndef SSD1783_H_ -#define SSD1783_H_ - -#include - -#define FB_COLOR_TO_R(v) (((v)>>16) & 0xff) -#define FB_COLOR_TO_G(v) (((v)>> 8) & 0xff) -#define FB_COLOR_TO_B(v) ( (v) & 0xff) - -#define SSD1783_UWIRE_BITLEN 9 -#define SSD1783_DEV_ID 0 - -#define ARMIO_LATCH_OUT 0xfffe4802 -#define IO_CNTL_REG 0xfffe4804 -#define ASIC_CONF_REG 0xfffef008 - -#define ASCONF_PWL_ENA (1 << 4) - -/* begin backlight.c */ -#define BASE_ADDR_PWL 0xfffe8000 -#define PWL_REG(m) (BASE_ADDR_PWL + (m)) - -enum pwl_reg { - PWL_LEVEL = 0, - PWL_CTRL = 1, -}; - -enum ssd1783_cmdflag { CMD, DATA, END }; - -struct ssd1783_cmdlist { - enum ssd1783_cmdflag is_cmd:8; /* 1: is a command, 0: is data, 2: end marker! */ - uint8_t data; /* 8 bit to send to LC display */ -} __attribute__((packed)); - -static const struct ssd1783_cmdlist nop[] = { - { CMD, 0x25 }, // NOP command - { END, 0x00 } -}; - -static const struct ssd1783_cmdlist -ssd1783_initdata[] = { - { CMD, 0xD1 }, /* CMD set internal oscillator on */ - { CMD, 0x94 }, /* CMD leave sleep mode */ - { CMD, 0xbb }, /* CMD Set COM Output Scan Direction: */ - { DATA, 0x01 }, /* DATA: 01: COM0-79, then COM159-80 */ -/* -------- DIFFERENT FROM ORIGINAL CODE: -------------- */ -/* we use 8bit per pixel packed RGB 332 */ - { CMD, 0xbc }, /* CMD Set Data Output Scan Direction */ - { DATA, 0x00 }, /* DATA: column scan, normal rotation, normal display */ - { DATA, 0x00 }, /* DATA: RGB color arrangement R G B R G B ... */ -/*-->*/ { DATA, 0x01 }, /* DATA: 8 bit per pixel mode MSB LSB */ -/* --------- /DIFFERENT ---------- */ - { CMD, 0xce }, /* CMD Set 256 Color Look Up Table LUT */ - { DATA, 0x00 }, /* DATA red 000 */ - { DATA, 0x03 }, /* DATA red 001 */ - { DATA, 0x05 }, /* DATA red 010 */ - { DATA, 0x07 }, /* DATA red 011 */ - { DATA, 0x09 }, /* DATA red 100 */ - { DATA, 0x0b }, /* DATA red 101 */ - { DATA, 0x0d }, /* DATA red 110 */ - { DATA, 0x0f }, /* DATA red 111 */ - { DATA, 0x00 }, /* DATA green 000 */ - { DATA, 0x03 }, /* DATA green 001 */ - { DATA, 0x05 }, /* DATA green 010 */ - { DATA, 0x07 }, /* DATA green 011 */ - { DATA, 0x09 }, /* DATA green 100 */ - { DATA, 0x0b }, /* DATA green 101 */ - { DATA, 0x0d }, /* DATA green 110 */ - { DATA, 0x0f }, /* DATA green 111 */ - { DATA, 0x00 }, /* DATA blue 00 */ - { DATA, 0x05 }, /* DATA blue 01 */ - { DATA, 0x0a }, /* DATA blue 10 */ - { DATA, 0x0f }, /* DATA blue 11 */ - { CMD, 0xca }, /* CMD Set Display Control - Driver Duty Selection */ - { DATA, 0xff }, // can't find description of the values in the original - { DATA, 0x10 }, // display/ssd1783.c in my datasheet :-( - { DATA, 0x01 }, // - { CMD, 0xab }, /* CMD Set Scroll Start */ - { DATA, 0x00 }, /* DATA: Starting address at block 0 */ - { CMD, 0x20 }, /* CMD Set power control register */ - { DATA, 0x0b }, /* DATA: booster 6x, reference gen. & int regulator */ - { CMD, 0x81 }, /* CMD Contrast Lvl & Int. Regul. Resistor Ratio */ - { DATA, 0x29 }, /* DATA: contrast = 0x29 */ - { DATA, 0x05 }, /* DATA: 0x05 = 0b101 -> 1+R2/R1 = 11.37 */ - { CMD, 0xa7 }, /* CMD Invert Display */ - { CMD, 0x82 }, /* CMD Set Temperature Compensation Coefficient */ - { DATA, 0x00 }, /* DATA: Gradient is -0.10 % / degC */ - { CMD, 0xfb }, /* CMD Set Biasing Ratio */ - { DATA, 0x03 }, /* DATA: 1/10 bias */ - { CMD, 0xf2 }, /* CMD Set Frame Frequency and N-line inversion */ - { DATA, 0x08 }, /* DATA: 75 Hz (POR) */ - { DATA, 0x06 }, /* DATA: n-line inversion: 6 lines */ - { CMD, 0xf7 }, /* CMD Select PWM/FRC Select Full Col./8col mode */ - { DATA, 0x28 }, /* DATA: always 0x28 */ - { DATA, 0x8c }, /* DATA: 4bit PWM + 2 bit FRC */ - { DATA, 0x05 }, /* DATA: full color mode */ - { CMD, 0xaf }, /* CMD Display On */ - { END, 0x00 }, /* MARKER: end of list */ -}; - -struct ssd1783_dev_s -{ - /* Publicly visible device structure */ - struct lcd_dev_s dev; - - /* Private LCD-specific information follows */ - uint8_t power; /* Current power setting */ -}; - -#endif /* SSD1783_H_ */ diff --git a/configs/dk-tm4c129x/ipv6/defconfig b/configs/dk-tm4c129x/ipv6/defconfig index cdbfd30b3d..2cdd072895 100644 --- a/configs/dk-tm4c129x/ipv6/defconfig +++ b/configs/dk-tm4c129x/ipv6/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/dk-tm4c129x/nsh/defconfig b/configs/dk-tm4c129x/nsh/defconfig index 48231e3d5e..085a598e1f 100644 --- a/configs/dk-tm4c129x/nsh/defconfig +++ b/configs/dk-tm4c129x/nsh/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/ea3131/nsh/defconfig b/configs/ea3131/nsh/defconfig index c47bb4d67c..3250e05da7 100644 --- a/configs/ea3131/nsh/defconfig +++ b/configs/ea3131/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/ea3131/pgnsh/defconfig b/configs/ea3131/pgnsh/defconfig index 39c05cad92..8d53362269 100644 --- a/configs/ea3131/pgnsh/defconfig +++ b/configs/ea3131/pgnsh/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/ea3131/usbserial/defconfig b/configs/ea3131/usbserial/defconfig index 69f48400c0..6c2c68e5db 100644 --- a/configs/ea3131/usbserial/defconfig +++ b/configs/ea3131/usbserial/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/ea3152/ostest/defconfig b/configs/ea3152/ostest/defconfig index cc289d7602..96961e4204 100644 --- a/configs/ea3152/ostest/defconfig +++ b/configs/ea3152/ostest/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/eagle100/httpd/defconfig b/configs/eagle100/httpd/defconfig index 3cae28f259..b2fbabd77c 100644 --- a/configs/eagle100/httpd/defconfig +++ b/configs/eagle100/httpd/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/eagle100/nettest/defconfig b/configs/eagle100/nettest/defconfig index 09a90f2759..a0c3b49b98 100644 --- a/configs/eagle100/nettest/defconfig +++ b/configs/eagle100/nettest/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/eagle100/nsh/defconfig b/configs/eagle100/nsh/defconfig index fd7f6e6e4d..2a90032891 100644 --- a/configs/eagle100/nsh/defconfig +++ b/configs/eagle100/nsh/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/eagle100/nxflat/defconfig b/configs/eagle100/nxflat/defconfig index 6db49bd186..d28067ad94 100644 --- a/configs/eagle100/nxflat/defconfig +++ b/configs/eagle100/nxflat/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/eagle100/thttpd/defconfig b/configs/eagle100/thttpd/defconfig index 60d1f3ade7..579c652513 100644 --- a/configs/eagle100/thttpd/defconfig +++ b/configs/eagle100/thttpd/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/efm32-g8xx-stk/nsh/defconfig b/configs/efm32-g8xx-stk/nsh/defconfig index f0a8e668c2..d97369ecf9 100644 --- a/configs/efm32-g8xx-stk/nsh/defconfig +++ b/configs/efm32-g8xx-stk/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set CONFIG_ARCH_CHIP_EFM32=y # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/efm32gg-stk3700/nsh/defconfig b/configs/efm32gg-stk3700/nsh/defconfig index 3910296ef6..aef89ed858 100644 --- a/configs/efm32gg-stk3700/nsh/defconfig +++ b/configs/efm32gg-stk3700/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set CONFIG_ARCH_CHIP_EFM32=y # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/ekk-lm3s9b96/nsh/defconfig b/configs/ekk-lm3s9b96/nsh/defconfig index 9ab7bb5842..9870858ce1 100644 --- a/configs/ekk-lm3s9b96/nsh/defconfig +++ b/configs/ekk-lm3s9b96/nsh/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/fire-stm32v2/nsh/defconfig b/configs/fire-stm32v2/nsh/defconfig index 12ea15117c..50cae46c40 100644 --- a/configs/fire-stm32v2/nsh/defconfig +++ b/configs/fire-stm32v2/nsh/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/freedom-k64f/netnsh/defconfig b/configs/freedom-k64f/netnsh/defconfig index 7a174609d4..02ec9f3d77 100644 --- a/configs/freedom-k64f/netnsh/defconfig +++ b/configs/freedom-k64f/netnsh/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/freedom-k64f/nsh/defconfig b/configs/freedom-k64f/nsh/defconfig index 1a570c533f..32c412eff7 100644 --- a/configs/freedom-k64f/nsh/defconfig +++ b/configs/freedom-k64f/nsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/freedom-kl25z/nsh/defconfig b/configs/freedom-kl25z/nsh/defconfig index 25a5f7e7e9..7e8e1e499c 100644 --- a/configs/freedom-kl25z/nsh/defconfig +++ b/configs/freedom-kl25z/nsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/freedom-kl26z/nsh/defconfig b/configs/freedom-kl26z/nsh/defconfig index cfd523f6c2..47dd2b666c 100644 --- a/configs/freedom-kl26z/nsh/defconfig +++ b/configs/freedom-kl26z/nsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/hymini-stm32v/nsh/defconfig b/configs/hymini-stm32v/nsh/defconfig index 6b5e138135..47f1611dde 100644 --- a/configs/hymini-stm32v/nsh/defconfig +++ b/configs/hymini-stm32v/nsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/hymini-stm32v/nsh2/defconfig b/configs/hymini-stm32v/nsh2/defconfig index 32def3b8bf..7bc35a4917 100644 --- a/configs/hymini-stm32v/nsh2/defconfig +++ b/configs/hymini-stm32v/nsh2/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/hymini-stm32v/usbmsc/defconfig b/configs/hymini-stm32v/usbmsc/defconfig index b85dca84bc..504e368db2 100644 --- a/configs/hymini-stm32v/usbmsc/defconfig +++ b/configs/hymini-stm32v/usbmsc/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/hymini-stm32v/usbnsh/defconfig b/configs/hymini-stm32v/usbnsh/defconfig index a806aa165c..32e61c43d6 100644 --- a/configs/hymini-stm32v/usbnsh/defconfig +++ b/configs/hymini-stm32v/usbnsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/hymini-stm32v/usbserial/defconfig b/configs/hymini-stm32v/usbserial/defconfig index e8e85f2933..e60be704c7 100644 --- a/configs/hymini-stm32v/usbserial/defconfig +++ b/configs/hymini-stm32v/usbserial/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/kwikstik-k40/ostest/defconfig b/configs/kwikstik-k40/ostest/defconfig index f0d1a49614..3aa09462c5 100644 --- a/configs/kwikstik-k40/ostest/defconfig +++ b/configs/kwikstik-k40/ostest/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/launchxl-tms57004/nsh/defconfig b/configs/launchxl-tms57004/nsh/defconfig index c10cf4fdf6..d80732cc89 100644 --- a/configs/launchxl-tms57004/nsh/defconfig +++ b/configs/launchxl-tms57004/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/lincoln60/netnsh/defconfig b/configs/lincoln60/netnsh/defconfig index 4a351f8fba..d441e274ba 100644 --- a/configs/lincoln60/netnsh/defconfig +++ b/configs/lincoln60/netnsh/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/lincoln60/nsh/defconfig b/configs/lincoln60/nsh/defconfig index 9dbec58c1d..3fcf92ddc8 100644 --- a/configs/lincoln60/nsh/defconfig +++ b/configs/lincoln60/nsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/lincoln60/thttpd-binfs/defconfig b/configs/lincoln60/thttpd-binfs/defconfig index 90f3ac8b54..2ca94f7fa3 100644 --- a/configs/lincoln60/thttpd-binfs/defconfig +++ b/configs/lincoln60/thttpd-binfs/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/lm3s6432-s2e/nsh/defconfig b/configs/lm3s6432-s2e/nsh/defconfig index afd5629832..a18a57d4c2 100644 --- a/configs/lm3s6432-s2e/nsh/defconfig +++ b/configs/lm3s6432-s2e/nsh/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/lm3s6965-ek/discover/defconfig b/configs/lm3s6965-ek/discover/defconfig index defeaed79c..8d96db5491 100644 --- a/configs/lm3s6965-ek/discover/defconfig +++ b/configs/lm3s6965-ek/discover/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/lm3s6965-ek/nsh/defconfig b/configs/lm3s6965-ek/nsh/defconfig index defeaed79c..8d96db5491 100644 --- a/configs/lm3s6965-ek/nsh/defconfig +++ b/configs/lm3s6965-ek/nsh/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/lm3s6965-ek/nx/defconfig b/configs/lm3s6965-ek/nx/defconfig index 0350c0ac98..496b2737ea 100644 --- a/configs/lm3s6965-ek/nx/defconfig +++ b/configs/lm3s6965-ek/nx/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/lm3s6965-ek/tcpecho/defconfig b/configs/lm3s6965-ek/tcpecho/defconfig index 2142ed9137..d080e57f55 100644 --- a/configs/lm3s6965-ek/tcpecho/defconfig +++ b/configs/lm3s6965-ek/tcpecho/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/lm3s8962-ek/nsh/defconfig b/configs/lm3s8962-ek/nsh/defconfig index 49acf3dc8c..d707ebe974 100644 --- a/configs/lm3s8962-ek/nsh/defconfig +++ b/configs/lm3s8962-ek/nsh/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/lm3s8962-ek/nx/defconfig b/configs/lm3s8962-ek/nx/defconfig index 4506f553cb..7cfe420286 100644 --- a/configs/lm3s8962-ek/nx/defconfig +++ b/configs/lm3s8962-ek/nx/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/lm4f120-launchpad/nsh/defconfig b/configs/lm4f120-launchpad/nsh/defconfig index 3f6d35f825..2dd6e821ae 100644 --- a/configs/lm4f120-launchpad/nsh/defconfig +++ b/configs/lm4f120-launchpad/nsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/lpc4330-xplorer/nsh/defconfig b/configs/lpc4330-xplorer/nsh/defconfig index dd91ed8a78..ded2899940 100644 --- a/configs/lpc4330-xplorer/nsh/defconfig +++ b/configs/lpc4330-xplorer/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/lpc4337-ws/nsh/defconfig b/configs/lpc4337-ws/nsh/defconfig index 31c1ac48fe..f4f3a256a3 100644 --- a/configs/lpc4337-ws/nsh/defconfig +++ b/configs/lpc4337-ws/nsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/lpc4357-evb/nsh/defconfig b/configs/lpc4357-evb/nsh/defconfig index 7b59831c7b..a4aeb12c63 100644 --- a/configs/lpc4357-evb/nsh/defconfig +++ b/configs/lpc4357-evb/nsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/lpc4370-link2/nsh/defconfig b/configs/lpc4370-link2/nsh/defconfig index a740815531..e6705f3f53 100644 --- a/configs/lpc4370-link2/nsh/defconfig +++ b/configs/lpc4370-link2/nsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/lpcxpresso-lpc1115/nsh/defconfig b/configs/lpcxpresso-lpc1115/nsh/defconfig index 5fbf61f2b8..9f84ad4089 100644 --- a/configs/lpcxpresso-lpc1115/nsh/defconfig +++ b/configs/lpcxpresso-lpc1115/nsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/lpcxpresso-lpc1768/dhcpd/defconfig b/configs/lpcxpresso-lpc1768/dhcpd/defconfig index 8df48ef27e..bba536eb45 100644 --- a/configs/lpcxpresso-lpc1768/dhcpd/defconfig +++ b/configs/lpcxpresso-lpc1768/dhcpd/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/lpcxpresso-lpc1768/nsh/defconfig b/configs/lpcxpresso-lpc1768/nsh/defconfig index 6a6c05e5de..711a813f12 100644 --- a/configs/lpcxpresso-lpc1768/nsh/defconfig +++ b/configs/lpcxpresso-lpc1768/nsh/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/lpcxpresso-lpc1768/nx/defconfig b/configs/lpcxpresso-lpc1768/nx/defconfig index 7085ccd02b..fbfd01860b 100644 --- a/configs/lpcxpresso-lpc1768/nx/defconfig +++ b/configs/lpcxpresso-lpc1768/nx/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/lpcxpresso-lpc1768/thttpd/defconfig b/configs/lpcxpresso-lpc1768/thttpd/defconfig index 4d16ce1734..9b6d1f1642 100644 --- a/configs/lpcxpresso-lpc1768/thttpd/defconfig +++ b/configs/lpcxpresso-lpc1768/thttpd/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/lpcxpresso-lpc1768/usbmsc/defconfig b/configs/lpcxpresso-lpc1768/usbmsc/defconfig index d02c4d951a..b320318150 100644 --- a/configs/lpcxpresso-lpc1768/usbmsc/defconfig +++ b/configs/lpcxpresso-lpc1768/usbmsc/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/maple/nsh/defconfig b/configs/maple/nsh/defconfig index dcf2229582..1b7e1f5ac7 100644 --- a/configs/maple/nsh/defconfig +++ b/configs/maple/nsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/maple/nx/defconfig b/configs/maple/nx/defconfig index 3e75539627..3906da6970 100644 --- a/configs/maple/nx/defconfig +++ b/configs/maple/nx/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/maple/usbnsh/defconfig b/configs/maple/usbnsh/defconfig index 6976bf0eaa..03c4bdf963 100644 --- a/configs/maple/usbnsh/defconfig +++ b/configs/maple/usbnsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/mbed/hidkbd/defconfig b/configs/mbed/hidkbd/defconfig index 5e58e588ae..1543135095 100644 --- a/configs/mbed/hidkbd/defconfig +++ b/configs/mbed/hidkbd/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/mbed/nsh/defconfig b/configs/mbed/nsh/defconfig index 257ca1a75c..094452f385 100644 --- a/configs/mbed/nsh/defconfig +++ b/configs/mbed/nsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/mcu123-lpc214x/composite/defconfig b/configs/mcu123-lpc214x/composite/defconfig index defee1ad92..c201531c3e 100644 --- a/configs/mcu123-lpc214x/composite/defconfig +++ b/configs/mcu123-lpc214x/composite/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/mcu123-lpc214x/nsh/defconfig b/configs/mcu123-lpc214x/nsh/defconfig index ed35e28cf9..ecf4525145 100644 --- a/configs/mcu123-lpc214x/nsh/defconfig +++ b/configs/mcu123-lpc214x/nsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/mcu123-lpc214x/usbmsc/defconfig b/configs/mcu123-lpc214x/usbmsc/defconfig index df52fa03bd..6aa0970854 100644 --- a/configs/mcu123-lpc214x/usbmsc/defconfig +++ b/configs/mcu123-lpc214x/usbmsc/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/mcu123-lpc214x/usbserial/defconfig b/configs/mcu123-lpc214x/usbserial/defconfig index 100d87fe95..c2717e3634 100644 --- a/configs/mcu123-lpc214x/usbserial/defconfig +++ b/configs/mcu123-lpc214x/usbserial/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/mikroe-stm32f4/fulldemo/defconfig b/configs/mikroe-stm32f4/fulldemo/defconfig index 13ff114588..3588440c91 100644 --- a/configs/mikroe-stm32f4/fulldemo/defconfig +++ b/configs/mikroe-stm32f4/fulldemo/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/mikroe-stm32f4/kostest/defconfig b/configs/mikroe-stm32f4/kostest/defconfig index 629d012add..5baa0d7129 100644 --- a/configs/mikroe-stm32f4/kostest/defconfig +++ b/configs/mikroe-stm32f4/kostest/defconfig @@ -78,7 +78,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/mikroe-stm32f4/nsh/defconfig b/configs/mikroe-stm32f4/nsh/defconfig index 9291880ddf..88f1e50141 100644 --- a/configs/mikroe-stm32f4/nsh/defconfig +++ b/configs/mikroe-stm32f4/nsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/mikroe-stm32f4/nx/defconfig b/configs/mikroe-stm32f4/nx/defconfig index 478c440e14..141f06a3f2 100644 --- a/configs/mikroe-stm32f4/nx/defconfig +++ b/configs/mikroe-stm32f4/nx/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/mikroe-stm32f4/nxlines/defconfig b/configs/mikroe-stm32f4/nxlines/defconfig index 67088d6ac0..96e58d2a0e 100644 --- a/configs/mikroe-stm32f4/nxlines/defconfig +++ b/configs/mikroe-stm32f4/nxlines/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/mikroe-stm32f4/nxtext/defconfig b/configs/mikroe-stm32f4/nxtext/defconfig index f6f131b972..511b951270 100644 --- a/configs/mikroe-stm32f4/nxtext/defconfig +++ b/configs/mikroe-stm32f4/nxtext/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/mikroe-stm32f4/usbnsh/defconfig b/configs/mikroe-stm32f4/usbnsh/defconfig index 45102afa4a..5e53200ce8 100644 --- a/configs/mikroe-stm32f4/usbnsh/defconfig +++ b/configs/mikroe-stm32f4/usbnsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/moxa/nsh/defconfig b/configs/moxa/nsh/defconfig index d1cdfc6b40..f1fdbfbda3 100644 --- a/configs/moxa/nsh/defconfig +++ b/configs/moxa/nsh/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/mx1ads/ostest/defconfig b/configs/mx1ads/ostest/defconfig index 6b9443b925..6f911c5a48 100644 --- a/configs/mx1ads/ostest/defconfig +++ b/configs/mx1ads/ostest/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set CONFIG_ARCH_CHIP_IMX1=y diff --git a/configs/ntosd-dm320/nettest/defconfig b/configs/ntosd-dm320/nettest/defconfig index bd68dc951a..8621bd1cba 100644 --- a/configs/ntosd-dm320/nettest/defconfig +++ b/configs/ntosd-dm320/nettest/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set CONFIG_ARCH_CHIP_DM320=y # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/ntosd-dm320/nsh/defconfig b/configs/ntosd-dm320/nsh/defconfig index a2c9d13163..13fba2e95f 100644 --- a/configs/ntosd-dm320/nsh/defconfig +++ b/configs/ntosd-dm320/nsh/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set CONFIG_ARCH_CHIP_DM320=y # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/ntosd-dm320/poll/defconfig b/configs/ntosd-dm320/poll/defconfig index 99ac30997c..504fe1fd77 100644 --- a/configs/ntosd-dm320/poll/defconfig +++ b/configs/ntosd-dm320/poll/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set CONFIG_ARCH_CHIP_DM320=y # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/ntosd-dm320/thttpd/defconfig b/configs/ntosd-dm320/thttpd/defconfig index b9cc758765..e0b5074661 100644 --- a/configs/ntosd-dm320/thttpd/defconfig +++ b/configs/ntosd-dm320/thttpd/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set CONFIG_ARCH_CHIP_DM320=y # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/ntosd-dm320/udp/defconfig b/configs/ntosd-dm320/udp/defconfig index b34efac745..a9713516f4 100644 --- a/configs/ntosd-dm320/udp/defconfig +++ b/configs/ntosd-dm320/udp/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set CONFIG_ARCH_CHIP_DM320=y # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/ntosd-dm320/webserver/defconfig b/configs/ntosd-dm320/webserver/defconfig index 40ff3fe1bf..8cb5e5715c 100644 --- a/configs/ntosd-dm320/webserver/defconfig +++ b/configs/ntosd-dm320/webserver/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set CONFIG_ARCH_CHIP_DM320=y # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/nucleo-144/f746-evalos/defconfig b/configs/nucleo-144/f746-evalos/defconfig index e3ab70c260..8dd40aa090 100644 --- a/configs/nucleo-144/f746-evalos/defconfig +++ b/configs/nucleo-144/f746-evalos/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/nucleo-144/f746-nsh/defconfig b/configs/nucleo-144/f746-nsh/defconfig index 69bc73ac3d..91cc088605 100644 --- a/configs/nucleo-144/f746-nsh/defconfig +++ b/configs/nucleo-144/f746-nsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/nucleo-144/f767-evalos/defconfig b/configs/nucleo-144/f767-evalos/defconfig index 1a9d88032e..90f0a2fa63 100644 --- a/configs/nucleo-144/f767-evalos/defconfig +++ b/configs/nucleo-144/f767-evalos/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/nucleo-144/f767-nsh/defconfig b/configs/nucleo-144/f767-nsh/defconfig index ee1f1ec661..30ea41719a 100644 --- a/configs/nucleo-144/f767-nsh/defconfig +++ b/configs/nucleo-144/f767-nsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/nucleo-f303re/adc/defconfig b/configs/nucleo-f303re/adc/defconfig index c78821676c..6bd903c7b8 100644 --- a/configs/nucleo-f303re/adc/defconfig +++ b/configs/nucleo-f303re/adc/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/nucleo-f303re/can/defconfig b/configs/nucleo-f303re/can/defconfig index 868ad9be6a..957b4d9412 100644 --- a/configs/nucleo-f303re/can/defconfig +++ b/configs/nucleo-f303re/can/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/nucleo-f303re/hello/defconfig b/configs/nucleo-f303re/hello/defconfig index 92ceeb5133..46e78f3399 100644 --- a/configs/nucleo-f303re/hello/defconfig +++ b/configs/nucleo-f303re/hello/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/nucleo-f303re/nxlines/defconfig b/configs/nucleo-f303re/nxlines/defconfig index 0cf525b59c..da112c4350 100644 --- a/configs/nucleo-f303re/nxlines/defconfig +++ b/configs/nucleo-f303re/nxlines/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/nucleo-f303re/pwm/defconfig b/configs/nucleo-f303re/pwm/defconfig index df69cdde82..ba86073959 100644 --- a/configs/nucleo-f303re/pwm/defconfig +++ b/configs/nucleo-f303re/pwm/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/nucleo-f303re/serialrx/defconfig b/configs/nucleo-f303re/serialrx/defconfig index 894a6bcc59..0cbb86fdbf 100644 --- a/configs/nucleo-f303re/serialrx/defconfig +++ b/configs/nucleo-f303re/serialrx/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/nucleo-f303re/uavcan/defconfig b/configs/nucleo-f303re/uavcan/defconfig index 8fa6320578..0d6b7a805a 100644 --- a/configs/nucleo-f303re/uavcan/defconfig +++ b/configs/nucleo-f303re/uavcan/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/nucleo-f4x1re/f401-nsh/defconfig b/configs/nucleo-f4x1re/f401-nsh/defconfig index ce4f3cf3cc..bd6347ccf4 100644 --- a/configs/nucleo-f4x1re/f401-nsh/defconfig +++ b/configs/nucleo-f4x1re/f401-nsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/nucleo-f4x1re/f411-nsh/defconfig b/configs/nucleo-f4x1re/f411-nsh/defconfig index 238cb1564c..93f29a8058 100644 --- a/configs/nucleo-f4x1re/f411-nsh/defconfig +++ b/configs/nucleo-f4x1re/f411-nsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/nucleo-l476rg/nsh/defconfig b/configs/nucleo-l476rg/nsh/defconfig index 730c7bb3a1..293d43a01e 100644 --- a/configs/nucleo-l476rg/nsh/defconfig +++ b/configs/nucleo-l476rg/nsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/nutiny-nuc120/nsh/defconfig b/configs/nutiny-nuc120/nsh/defconfig index d946b02f73..52cd0aa73d 100644 --- a/configs/nutiny-nuc120/nsh/defconfig +++ b/configs/nutiny-nuc120/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-efm32g880f128-stk/nsh/defconfig b/configs/olimex-efm32g880f128-stk/nsh/defconfig index 1facde8362..325b4d39c6 100644 --- a/configs/olimex-efm32g880f128-stk/nsh/defconfig +++ b/configs/olimex-efm32g880f128-stk/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set CONFIG_ARCH_CHIP_EFM32=y # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-lpc-h3131/nsh/defconfig b/configs/olimex-lpc-h3131/nsh/defconfig index 816136a679..aa99aad41a 100644 --- a/configs/olimex-lpc-h3131/nsh/defconfig +++ b/configs/olimex-lpc-h3131/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-lpc1766stk/ftpc/defconfig b/configs/olimex-lpc1766stk/ftpc/defconfig index 37340b18dd..6e4257fabf 100644 --- a/configs/olimex-lpc1766stk/ftpc/defconfig +++ b/configs/olimex-lpc1766stk/ftpc/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-lpc1766stk/hidkbd/defconfig b/configs/olimex-lpc1766stk/hidkbd/defconfig index 438351bf1c..91339c8034 100644 --- a/configs/olimex-lpc1766stk/hidkbd/defconfig +++ b/configs/olimex-lpc1766stk/hidkbd/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-lpc1766stk/hidmouse/defconfig b/configs/olimex-lpc1766stk/hidmouse/defconfig index 7deaf52065..779627451c 100644 --- a/configs/olimex-lpc1766stk/hidmouse/defconfig +++ b/configs/olimex-lpc1766stk/hidmouse/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-lpc1766stk/nettest/defconfig b/configs/olimex-lpc1766stk/nettest/defconfig index 0e78b00259..3b16844a41 100644 --- a/configs/olimex-lpc1766stk/nettest/defconfig +++ b/configs/olimex-lpc1766stk/nettest/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-lpc1766stk/nsh/defconfig b/configs/olimex-lpc1766stk/nsh/defconfig index a391c8b8b6..7f6d655492 100644 --- a/configs/olimex-lpc1766stk/nsh/defconfig +++ b/configs/olimex-lpc1766stk/nsh/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-lpc1766stk/nx/defconfig b/configs/olimex-lpc1766stk/nx/defconfig index 5bfc733710..9eab58ddbb 100644 --- a/configs/olimex-lpc1766stk/nx/defconfig +++ b/configs/olimex-lpc1766stk/nx/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-lpc1766stk/slip-httpd/defconfig b/configs/olimex-lpc1766stk/slip-httpd/defconfig index ad62a7308b..0d5615bac1 100644 --- a/configs/olimex-lpc1766stk/slip-httpd/defconfig +++ b/configs/olimex-lpc1766stk/slip-httpd/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-lpc1766stk/thttpd-binfs/defconfig b/configs/olimex-lpc1766stk/thttpd-binfs/defconfig index 61584a923f..0e6f02065b 100644 --- a/configs/olimex-lpc1766stk/thttpd-binfs/defconfig +++ b/configs/olimex-lpc1766stk/thttpd-binfs/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig b/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig index a3f8045c97..048d75917e 100644 --- a/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig +++ b/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-lpc1766stk/usbmsc/defconfig b/configs/olimex-lpc1766stk/usbmsc/defconfig index ac9781cd82..cac5beabd4 100644 --- a/configs/olimex-lpc1766stk/usbmsc/defconfig +++ b/configs/olimex-lpc1766stk/usbmsc/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-lpc1766stk/usbserial/defconfig b/configs/olimex-lpc1766stk/usbserial/defconfig index 6ae2279fee..82a00f158d 100644 --- a/configs/olimex-lpc1766stk/usbserial/defconfig +++ b/configs/olimex-lpc1766stk/usbserial/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-lpc1766stk/zmodem/defconfig b/configs/olimex-lpc1766stk/zmodem/defconfig index 88aa69be37..4bb500d149 100644 --- a/configs/olimex-lpc1766stk/zmodem/defconfig +++ b/configs/olimex-lpc1766stk/zmodem/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-lpc2378/nsh/defconfig b/configs/olimex-lpc2378/nsh/defconfig index 641e6078f0..0217cd1a89 100644 --- a/configs/olimex-lpc2378/nsh/defconfig +++ b/configs/olimex-lpc2378/nsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-stm32-e407/discover/defconfig b/configs/olimex-stm32-e407/discover/defconfig index 069ce1dcb7..a10f5196cb 100644 --- a/configs/olimex-stm32-e407/discover/defconfig +++ b/configs/olimex-stm32-e407/discover/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-stm32-e407/netnsh/defconfig b/configs/olimex-stm32-e407/netnsh/defconfig index 1ba24512b9..2053901804 100644 --- a/configs/olimex-stm32-e407/netnsh/defconfig +++ b/configs/olimex-stm32-e407/netnsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-stm32-e407/nsh/defconfig b/configs/olimex-stm32-e407/nsh/defconfig index cc0120fbc7..cc1f9c936c 100644 --- a/configs/olimex-stm32-e407/nsh/defconfig +++ b/configs/olimex-stm32-e407/nsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-stm32-e407/telnetd/defconfig b/configs/olimex-stm32-e407/telnetd/defconfig index 7eaea867bf..4867ca74cd 100644 --- a/configs/olimex-stm32-e407/telnetd/defconfig +++ b/configs/olimex-stm32-e407/telnetd/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-stm32-e407/usbnsh/defconfig b/configs/olimex-stm32-e407/usbnsh/defconfig index a0a4084076..937cdcdf9d 100644 --- a/configs/olimex-stm32-e407/usbnsh/defconfig +++ b/configs/olimex-stm32-e407/usbnsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-stm32-e407/webserver/defconfig b/configs/olimex-stm32-e407/webserver/defconfig index 7fd7e60e35..7da7262f19 100644 --- a/configs/olimex-stm32-e407/webserver/defconfig +++ b/configs/olimex-stm32-e407/webserver/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-stm32-h405/usbnsh/defconfig b/configs/olimex-stm32-h405/usbnsh/defconfig index 37de3e0885..4054b5aaa8 100644 --- a/configs/olimex-stm32-h405/usbnsh/defconfig +++ b/configs/olimex-stm32-h405/usbnsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-stm32-h407/nsh/defconfig b/configs/olimex-stm32-h407/nsh/defconfig index 79915a1a72..91f089efaa 100644 --- a/configs/olimex-stm32-h407/nsh/defconfig +++ b/configs/olimex-stm32-h407/nsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-stm32-p107/nsh/defconfig b/configs/olimex-stm32-p107/nsh/defconfig index 962d6ca2d9..e93ce79019 100644 --- a/configs/olimex-stm32-p107/nsh/defconfig +++ b/configs/olimex-stm32-p107/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-stm32-p207/nsh/defconfig b/configs/olimex-stm32-p207/nsh/defconfig index a4d0aa56e1..79ffb43b17 100644 --- a/configs/olimex-stm32-p207/nsh/defconfig +++ b/configs/olimex-stm32-p207/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-strp711/nettest/defconfig b/configs/olimex-strp711/nettest/defconfig index d89e0bf5d3..3d25b1799d 100644 --- a/configs/olimex-strp711/nettest/defconfig +++ b/configs/olimex-strp711/nettest/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimex-strp711/nsh/defconfig b/configs/olimex-strp711/nsh/defconfig index aed99049aa..1a5d097977 100644 --- a/configs/olimex-strp711/nsh/defconfig +++ b/configs/olimex-strp711/nsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimexino-stm32/can/defconfig b/configs/olimexino-stm32/can/defconfig index d83e2a9a93..b2e0ce9159 100644 --- a/configs/olimexino-stm32/can/defconfig +++ b/configs/olimexino-stm32/can/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimexino-stm32/composite/defconfig b/configs/olimexino-stm32/composite/defconfig index 7dc2e5a48b..bd5fb70be0 100644 --- a/configs/olimexino-stm32/composite/defconfig +++ b/configs/olimexino-stm32/composite/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimexino-stm32/nsh/defconfig b/configs/olimexino-stm32/nsh/defconfig index fe7b38e685..c00722b831 100644 --- a/configs/olimexino-stm32/nsh/defconfig +++ b/configs/olimexino-stm32/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimexino-stm32/smallnsh/defconfig b/configs/olimexino-stm32/smallnsh/defconfig index 0eca97c944..6edc98d077 100644 --- a/configs/olimexino-stm32/smallnsh/defconfig +++ b/configs/olimexino-stm32/smallnsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/olimexino-stm32/tiny/defconfig b/configs/olimexino-stm32/tiny/defconfig index b56ff2028e..60ea1b64a7 100644 --- a/configs/olimexino-stm32/tiny/defconfig +++ b/configs/olimexino-stm32/tiny/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/open1788/knsh/defconfig b/configs/open1788/knsh/defconfig index 4878abcb49..42f45c7b05 100644 --- a/configs/open1788/knsh/defconfig +++ b/configs/open1788/knsh/defconfig @@ -77,7 +77,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/open1788/nsh/defconfig b/configs/open1788/nsh/defconfig index 8ed16d5c5e..97b91ad2eb 100644 --- a/configs/open1788/nsh/defconfig +++ b/configs/open1788/nsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/open1788/nxlines/defconfig b/configs/open1788/nxlines/defconfig index 7cb4a4b8bb..4fe9369eff 100644 --- a/configs/open1788/nxlines/defconfig +++ b/configs/open1788/nxlines/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/pcduino-a10/nsh/defconfig b/configs/pcduino-a10/nsh/defconfig index f16a34ab90..c2bcbc0772 100644 --- a/configs/pcduino-a10/nsh/defconfig +++ b/configs/pcduino-a10/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # CONFIG_ARCH_CHIP_A1X=y # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/pirelli_dpl10/Kconfig b/configs/pirelli_dpl10/Kconfig deleted file mode 100644 index f72f3c094c..0000000000 --- a/configs/pirelli_dpl10/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# diff --git a/configs/pirelli_dpl10/README.txt b/configs/pirelli_dpl10/README.txt deleted file mode 100644 index e9f0204df5..0000000000 --- a/configs/pirelli_dpl10/README.txt +++ /dev/null @@ -1,363 +0,0 @@ -pirelli_dpl10 -============= - - This directory contains the board support for Pirelli "Discus" DP-L10 - phones. - -Contents -======== - - * History - * Hardware - * Osmocom-BB Dependencies and Sercomm - * Loading NuttX - * Memory Map - * USB Serial Console - * NuttX OABI "buildroot" Toolchain - * Generic OABI Toolchain - * Configurations - -History -======= - This port is a variant of the compal_e88 configuration with the small - change of enabling the IrDA serial console: - - - CONFIG_SERIAL_IRDA_CONSOLE=y - - This port is based on patches contributed by Denis Carikli for both the - compal e99 and e88. At the time of initial check-in, the following phones - were tested: - - - Pirelli DPL-10 nsh_highram loaded via romload in osmocon - - The patches were made by Alan Carvalho de Assis and Denis Carikli using - the Stefan Richter's patches that can be found here: - - http://cgit.osmocom.org/cgit/nuttx-bb/log/?h=lputt%2Ftesting - -Hardware -======== - - * CPU/DBB: TI Calypso (D751992AZHH) - - See http://bb.osmocom.org/trac/wiki/Hardware/Calypso - - * ABB: TI Iota (TWL3014) - - Analog baseband chip. See http://bb.osmocom.org/trac/wiki/Iota - - * GSM Transceiver: TI Rita (TRF6151) - - GSM Transceiver. See http://bb.osmocom.org/trac/wiki/Rita - - * PA: SKY77328-13 - - Quad-band GSM/GPRS: See http://www.skyworksinc.com/Product.aspx?ProductID=434 - - * Flash/SRAM: Spansion S71PL129NC0 128MBit/64MBit - - Combined FLASH and SDRAM: - FLASH: 128Mbit - SDRAM: 64Mbit - - * Wifi: Marvell 88W8385 802.11 MAC - Marvell 88W8015 802.11b/g transceiver - - * Winbond W56940 ringtone chip - - * Sunplus SPCA552E multimedia controller - - Multimedia processor: integrates CMOS sensor interface, DSC processor, JPEG - codec engine, LCM interface and other peripherals. - - I have not yet been able to find a data sheet for this chip. I believe that - it will be critical to develop drivers for the display. - - * LSI-65194A1 ASIC (seems to be a DSP for VoIP en-/decoding) - - * Silabs CP2102 USB UART (connected to UART_IRDA of the Calypso) - -Osmocom-BB Dependencies and Sercomm -=================================== - - Sercomm is an HDLC protocol used to communicate between a Calypso phone - and the host PC. By default, NuttX will not use sercomm (HDLC protocol) to - communicate with the host system. Sercomm is the transport used by - osmocom-bb that runs on top of serial. See - http://bb.osmocom.org/trac/wiki/nuttx-bb/run for detailed the usage of nuttx - with sercomm. - - If you build with sercomm, you must add support for sercomm in your - configuration (CONFIG_SERCOMM_CONSOLE=y). In this case, the build - environment assumes that you have the osmocom-bb project directory at same - level as the nuttx project: - - |- nuttx - |- apps - `- osmocom-bb - - If you attempt to build a sercomm-enaled configuration without osmocom-bb, - you will get compilation errors in drivers/sercomm due to header files that - are needed from the osmocom-bb directory. - -Loading NuttX -============= - - General - ------- - The osmocom-bb wiki describes how to load NuttX. See - http://bb.osmocom.org/trac/wiki/nuttx-bb for detailed information. - The way that nuttx is loaded depends on the configuration (highram/compalram) - and phone: - - - compalram is for the ramloader(for phone having a bootloader on flash) - - highram is for phones having the romloader(if the phone has a bootrom) - or for loading in the ram trough a special loader(loaded first on ram - by talking to the ramloader) when having a ramloader(which can only - load 64k). - - The Pirelli USB Serial Interface - -------------------------------- - The Pirelli phone is epecially easy to use because you just use the - supplied USB cable. The phone already has an integrated Silabs CP210x - USB-UART, which is supported by Linux. No need for a T191 cable. - - Most of the phones seem to use USB vid:pid 0489:e003, which is mainline - since Linux 2.6.36. You can do the following for Kernels < 2.6.36: - - # modprobe -v cp210x - # echo "0489 e003" > /sys/bus/usb-serial/drivers/cp210x/new_id - - Loading NuttX - ------------- - Here's how I load NuttX into the phone: - - - Take out the battery - - Plug in the USB adapter into the phone then the computer - - Start osmocon like: osmocon -p /dev/ttyUSB0 -m romload nuttx.bin - - Put the battery back in - - This works most of the time. Sometimes I have to take out and put in - the battery a few times or re-start the whole set of steps but it's - generally quite reliable. - -Memory Map -========= - - Internal SRAM and ROM - --------------------- - Calypso has 256KB of internal SRAM (0x800000-0x83ffff, although some of - this is, I believe, actually ROM). Only this internal SRAM is used by - these configurations. The internal SRAM is broken up into two logical - banks. - - LRAM (rw) : ORIGIN = 0x00800000, LENGTH = 0x00020000 - HRAM (rw) : ORIGIN = 0x00820000, LENGTH = 0x00020000 - - Code can be loaded by the CalypsoBootloader only into HRAM beginning at - address 0x00820000 and, hence, is restricted to 128KB (including then - non-loaded sections: Uninitialized data and the NuttX heap). - - SDRAM and NOR FLASH - ------------------- - SDRAM is provided by a Flash/SRAM: Spansion S71PL129NC0 part that provices - 128MBit (16MB) of FLASH and 64MBit (8MB) of SDRAM. - - * SDRAM - - The Pirelli DP-L10 has 8MB of SDRAM beginning at address 0x01000000. - This DRAM appears to be initialized by the Pirelli ROM loader and is - ready for use with no further initialization required. - - * NOR FLASH - - The 16MB FLASH is at address 0x00000000. - -USB Serial Console -================== - - These configurations are set up to use the Calypso IrDA UART as the serial - port. On the Pirelli phone, this port connects to the built-in USB-serial - adaptor so that that NuttX serial console will be available on your PC as - a USB serial device. You should see something this using 'dmesg' when you - plug the Pirelli phone into a PC running Linux: - - usb 5-2: new full speed USB device number 3 using uhci_hcd - usb 5-2: New USB device found, idVendor=0489, idProduct=e003 - usb 5-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3 - usb 5-2: Product: DP-L10 - usb 5-2: Manufacturer: Silicon Labs - usb 5-2: SerialNumber: 0001 - usbcore: registered new interface driver usbserial - USB Serial support registered for generic - usbcore: registered new interface driver usbserial_generic - usbserial: USB Serial Driver core - USB Serial support registered for cp210x - cp210x 5-2:1.0: cp210x converter detected - usb 5-2: reset full speed USB device number 3 using uhci_hcd - usb 5-2: cp210x converter now attached to ttyUSB0 - usbcore: registered new interface driver cp210x - cp210x: v0.09:Silicon Labs CP210x RS232 serial adaptor driver - - - Before you use this port to communicate with Nuttx, make sure that osmocon is - no longer running. Then start a serial terminal such as minicom on your host - PC. Configure the serial terminal so that it uses: - - Port: /dev/ttyUSB0 - Baud: 115,200 8N1 - -JTAG and Alternative Serial Console -=================================== - -JTAG - All JTAG lines, as well as the second uart (UART_MODEM), go to the - unpopulated connector next to the display connector. NOTE: You have - to disassemble the phone to get to this connector. - - - --- --------------------------- - PIN SIGNAL - --- --------------------------- - 1 Vcc - 2 RX_MODEM - 3 TESTRSTz (Iota) - 4 TDI - 5 TMS - 6 TCK - 7 TX_MODEM - 8 TDO - 9 N/C - 10 GND - 11 N/C - 12 N/C - --- --------------------------- - -JTAG Apapter: - - ------- ----------- --------------- -------------------------------------- - JTAG 20-PIN DESCRIPTION NOTES - SIGNAL CONNECTOR - ------- ----------- --------------- -------------------------------------- - Vcc 1, 2 Vcc - nTRST 3 Reset Connect this pin to the (active - low) reset input of the target MCU. - Some JTAG adapters driver nTRST (high - and low). Others can can configure - nTRST as open collector (only drive - low). - GND 4, 6, 8, Ground - 10, 12, 14, - 16, 20 - TDI 5 JTAG Test Data Use 10K-100K Ohm pull-up resistor to - Input VCC - TMS 7 JTAG Test Mode Use 10K-100K Ohm pull-up resistor to - Select VCC - TCK 9 Clock into the Use 10K-100K Ohm pull-down resistor to - core GND - RTCK 11 Return clock Some JTAG adapters have adaptive clocking - using an RTCK signal. - DBGSEL 11 Debug Select Some devices have special pins that - enable the JTAG interface. For example, - on the NXP LPC2129 the signal RTCK must - be driven low during RESET to enable the - JTAG interface. - TDO 13 JTAG Test Data Use 10K-100K Ohm pull-up resistor to VCC - Output - DBGRQ 17 N/C - DGBACK 19 N/C - ISP ?? ISP Most NXP MCU's have an ISP pin which - (when pulled low) can be used to cause - the MCU to enter a bootloader on reset. - Use 10K-100K Ohm pull up resistor. - ------- ----------- --------------- -------------------------------------- - -NuttX OABI "buildroot" Toolchain -================================ - - A GNU GCC-based toolchain is assumed. The files */setenv.sh should - be modified to point to the correct path to the ARM GCC toolchain (if - different from the default in your PATH variable). - - If you have no ARMtoolchain, one can be downloaded from the NuttX - Bitbucket download site (https://bitbucket.org/nuttx/buildroot/downloads/). - This GNU toolchain builds and executes in the Linux or Cygwin environment. - - 1. You must have already configured Nuttx in /nuttx. - - cd tools - ./configure.sh pirelli_dpl10/ - - 2. Download the latest buildroot package into - - 3. unpack the buildroot tarball. The resulting directory may - have versioning information on it like buildroot-x.y.z. If so, - rename /buildroot-x.y.z to /buildroot. - - 4. cd /buildroot - - 5. cp configs/arm7tdmi-defconfig-4.3.3 .config - - 6. make oldconfig - - 7. make - - 8. Edit setenv.h, if necessary, so that the PATH variable includes - the path to the newly built binaries. - - See the file configs/README.txt in the buildroot source tree. That has more - details PLUS some special instructions that you will need to follow if you are - building a Cortex-M3 toolchain for Cygwin under Windows. - -Generic OABI Toolchain -====================== - - The NuttX OABI toolchain is selected with: - - CONFIG_ARM_TOOLCHAIN_BUILDROOT=y - CONFIG_ARM_OABI_TOOLCHAIN=y - - In most cases, OsmocomBB is built with a different OABI toolchain with a - prefix of arm-elf-. To use that toolchain, change the configuration as - follows: - - CONFIG_ARM_TOOLCHAIN_GNU_OABI=y - -Configurations -============== - - nsh: - --- - Configures the NuttShell (nsh) located at apps/examples/nsh. - - NOTES: - - 1. This configuration uses the mconf-based configuration tool. To - change this configuration using that tool, you should: - - a. Build and install the kconfig-mconf tool. See nuttx/README.txt - see additional README.txt files in the NuttX tools repository. - - b. Execute 'make menuconfig' in nuttx/ in order to start the - reconfiguration process. - - 2. This configuration enables the serial interface on IrDA UART which - will appears as a USB serial device. - - CONFIG_SERIAL_IRDA_CONSOLE=y - - 3. By default, this configuration uses the CodeSourcery toolchain - for Windows and builds under Cygwin (or probably MSYS). That - can easily be reconfigured, of course. - - CONFIG_HOST_LINUX=y : Builds under Linux - CONFIG_ARM_TOOLCHAIN_BUILDROOT=y : NuttX buildroot OABI toolchain - CONFIG_ARM_OABI_TOOLCHAIN=y - - You can switch to use the generic arm-elf- GCC toolchain by - setting: - - CONFIG_ARM_TOOLCHAIN_GNU_OABI=y : General arm-elf- toolchain - - 4. Support for builtin applications is enabled. A builtin 'poweroff' - command is supported. diff --git a/configs/pirelli_dpl10/include/board.h b/configs/pirelli_dpl10/include/board.h deleted file mode 100644 index 1426ea7324..0000000000 --- a/configs/pirelli_dpl10/include/board.h +++ /dev/null @@ -1,6 +0,0 @@ -/**************************************************************************** - * configs/pirelli_dpl10/include/board.h - * - * Supposed to be empty - * - ****************************************************************************/ diff --git a/configs/pirelli_dpl10/nsh_highram/Make.defs b/configs/pirelli_dpl10/nsh_highram/Make.defs deleted file mode 100644 index 6adb17f5a6..0000000000 --- a/configs/pirelli_dpl10/nsh_highram/Make.defs +++ /dev/null @@ -1,131 +0,0 @@ -############################################################################ -# configs/pirelli_dpl10/nsh/Make.defs -# -# Copyright (C) 2007, 2008, 2011, 2013 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk -include ${TOPDIR}/arch/arm/src/arm/Toolchain.defs - -LDSCRIPT = highram.ld - -ifeq ($(WINTOOL),y) - # Windows-native toolchains - ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" - ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" - ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" -else - # Linux/Cygwin-native toolchain - ARCHINCLUDES = -I. -isystem $(TOPDIR)/include - ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx - ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) -endif - -CC = $(CROSSDEV)gcc -CXX = $(CROSSDEV)g++ -CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld -AR = $(ARCROSSDEV)ar rcs -NM = $(ARCROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} -ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION = -g -endif - -ifneq ($(CONFIG_DEBUG_NOOPT),y) - ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer -endif - -ARCHCFLAGS = -fno-builtin -ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -ARCHWARNINGSXX = -Wall -Wshadow -Wundef -ARCHDEFINES = -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -AFLAGS = $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -ASMEXT = .S -OBJEXT = .o -LIBEXT = .a -EXEEXT = - -ifneq ($(CROSSDEV),arm-nuttx-elf-) - LDFLAGS += -nostartfiles -nodefaultlibs -endif -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - LDFLAGS += -g -endif - -ifeq ("${CONFIG_SERCOMM_CONSOLE}","y") -OSMODIR = $(TOPDIR)/../../osmocom-bb -EXTRA_LIBS = $(OSMODIR)/src/target/firmware/comm/libcomm.a \ - $(OSMODIR)/src/shared/libosmocore/build-target/src/.libs/libosmocore.a \ - $(OSMODIR)/src/target/firmware/calypso/libcalypso.a \ - $(OSMODIR)/src/target/firmware/comm/libcomm.a - # ^^^ Stupid hack! Why do I have to put it twice??? -endif - -HOSTCC = gcc -HOSTINCLUDES = -I. -HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe -HOSTLDFLAGS = -ifeq ($(CONFIG_HOST_WINDOWS),y) - HOSTEXEEXT = .exe -else - HOSTEXEEXT = -endif - -ifeq ($(WINTOOL),y) - # Windows-native host tools - DIRLINK = $(TOPDIR)/tools/copydir.sh - DIRUNLINK = $(TOPDIR)/tools/unlink.sh - MKDEP = $(TOPDIR)/tools/mkwindeps.sh -else - # Linux/Cygwin-native host tools - MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) -endif diff --git a/configs/pirelli_dpl10/nsh_highram/defconfig b/configs/pirelli_dpl10/nsh_highram/defconfig deleted file mode 100644 index e03349f8ee..0000000000 --- a/configs/pirelli_dpl10/nsh_highram/defconfig +++ /dev/null @@ -1,809 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Nuttx/ Configuration -# - -# -# Build Setup -# -# CONFIG_EXPERIMENTAL is not set -# CONFIG_DEFAULT_SMALL is not set -CONFIG_HOST_LINUX=y -# CONFIG_HOST_OSX is not set -# CONFIG_HOST_WINDOWS is not set -# CONFIG_HOST_OTHER is not set - -# -# Build Configuration -# -# CONFIG_APPS_DIR="../apps" -CONFIG_BUILD_FLAT=y -# CONFIG_BUILD_2PASS is not set - -# -# Binary Output Formats -# -# CONFIG_RRLOAD_BINARY is not set -# CONFIG_INTELHEX_BINARY is not set -# CONFIG_MOTOROLA_SREC is not set -CONFIG_RAW_BINARY=y -# CONFIG_UBOOT_UIMAGE is not set - -# -# Customize Header Files -# -# CONFIG_ARCH_STDINT_H is not set -# CONFIG_ARCH_STDBOOL_H is not set -# CONFIG_ARCH_MATH_H is not set -# CONFIG_ARCH_FLOAT_H is not set -# CONFIG_ARCH_STDARG_H is not set -# CONFIG_ARCH_DEBUG_H is not set - -# -# Debug Options -# -CONFIG_DEBUG_ALERT=y -# CONFIG_DEBUG_FEATURES is not set -CONFIG_ARCH_HAVE_STACKCHECK=y -# CONFIG_STACK_COLORATION is not set -# CONFIG_ARCH_HAVE_HEAPCHECK is not set -# CONFIG_DEBUG_SYMBOLS is not set -CONFIG_ARCH_HAVE_CUSTOMOPT=y -# CONFIG_DEBUG_NOOPT is not set -# CONFIG_DEBUG_CUSTOMOPT is not set -CONFIG_DEBUG_FULLOPT=y - -# -# System Type -# -CONFIG_ARCH_ARM=y -# CONFIG_ARCH_AVR is not set -# CONFIG_ARCH_HC is not set -# CONFIG_ARCH_MIPS is not set -# CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_SIM is not set -# CONFIG_ARCH_X86 is not set -# CONFIG_ARCH_Z16 is not set -# CONFIG_ARCH_Z80 is not set -CONFIG_ARCH="arm" - -# -# ARM Options -# -# CONFIG_ARCH_CHIP_A1X is not set -# CONFIG_ARCH_CHIP_C5471 is not set -CONFIG_ARCH_CHIP_CALYPSO=y -# CONFIG_ARCH_CHIP_DM320 is not set -# CONFIG_ARCH_CHIP_EFM32 is not set -# CONFIG_ARCH_CHIP_IMX1 is not set -# CONFIG_ARCH_CHIP_IMX6 is not set -# CONFIG_ARCH_CHIP_KINETIS is not set -# CONFIG_ARCH_CHIP_KL is not set -# CONFIG_ARCH_CHIP_LM is not set -# CONFIG_ARCH_CHIP_TIVA is not set -# CONFIG_ARCH_CHIP_LPC11XX is not set -# CONFIG_ARCH_CHIP_LPC17XX is not set -# CONFIG_ARCH_CHIP_LPC214X is not set -# CONFIG_ARCH_CHIP_LPC2378 is not set -# CONFIG_ARCH_CHIP_LPC31XX is not set -# CONFIG_ARCH_CHIP_LPC43XX is not set -# CONFIG_ARCH_CHIP_NUC1XX is not set -# CONFIG_ARCH_CHIP_SAMA5 is not set -# CONFIG_ARCH_CHIP_SAMD is not set -# CONFIG_ARCH_CHIP_SAML is not set -# CONFIG_ARCH_CHIP_SAM34 is not set -# CONFIG_ARCH_CHIP_SAMV7 is not set -# CONFIG_ARCH_CHIP_STM32 is not set -# CONFIG_ARCH_CHIP_STM32F7 is not set -# CONFIG_ARCH_CHIP_STM32L4 is not set -# CONFIG_ARCH_CHIP_STR71X is not set -# CONFIG_ARCH_CHIP_TMS570 is not set -# CONFIG_ARCH_CHIP_MOXART is not set -CONFIG_ARCH_ARM7TDMI=y -# CONFIG_ARCH_ARM926EJS is not set -# CONFIG_ARCH_ARM920T is not set -# CONFIG_ARCH_CORTEXM0 is not set -# CONFIG_ARCH_CORTEXM3 is not set -# CONFIG_ARCH_CORTEXM4 is not set -# CONFIG_ARCH_CORTEXM7 is not set -# CONFIG_ARCH_CORTEXA5 is not set -# CONFIG_ARCH_CORTEXA8 is not set -# CONFIG_ARCH_CORTEXA9 is not set -# CONFIG_ARCH_CORTEXR4 is not set -# CONFIG_ARCH_CORTEXR4F is not set -# CONFIG_ARCH_CORTEXR5 is not set -# CONFIG_ARCH_CORTEX5F is not set -# CONFIG_ARCH_CORTEXR7 is not set -# CONFIG_ARCH_CORTEXR7F is not set -CONFIG_ARCH_FAMILY="arm" -CONFIG_ARCH_CHIP="calypso" -# CONFIG_ARM_TOOLCHAIN_IAR is not set -# CONFIG_ARM_TOOLCHAIN_GNU is not set -# CONFIG_ARCH_HAVE_FPU is not set -# CONFIG_ARCH_HAVE_DPFPU is not set -# CONFIG_ARCH_HAVE_TRUSTZONE is not set -# CONFIG_ARM_HAVE_MPU_UNIFIED is not set -CONFIG_ARCH_HAVE_LOWVECTORS=y -# CONFIG_ARCH_LOWVECTORS is not set - -# -# ARM Configuration Options -# -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -# CONFIG_ARM_TOOLCHAIN_CODESOURCERYL is not set -# CONFIG_ARM_TOOLCHAIN_GNU_EABIL is not set -# CONFIG_ARM_TOOLCHAIN_GNU_OABI is not set -CONFIG_ARM_OABI_TOOLCHAIN=y -CONFIG_UART_IRDA_BAUD=115200 -CONFIG_UART_IRDA_PARITY=0 -CONFIG_UART_IRDA_BITS=8 -CONFIG_UART_IRDA_2STOP=0 -CONFIG_UART_IRDA_RXBUFSIZE=256 -CONFIG_UART_IRDA_TXBUFSIZE=256 -CONFIG_UART_MODEM_BAUD=115200 -CONFIG_UART_MODEM_PARITY=0 -CONFIG_UART_MODEM_BITS=8 -CONFIG_UART_MODEM_2STOP=0 -CONFIG_UART_MODEM_RXBUFSIZE=256 -CONFIG_UART_MODEM_TXBUFSIZE=256 - -# -# Calypso Configuration Options -# - -# -# Modem UART Configuration -# -# CONFIG_UART_MODEM_HWFLOWCONTROL is not set - -# -# IrDA UART Configuration -# -# CONFIG_UART_IRDA_HWFLOWCONTROL is not set -# CONFIG_USE_SERCOMM_CONSOLE is not set -# CONFIG_SERIAL_MODEM_CONSOLE is not set -CONFIG_SERIAL_IRDA_CONSOLE=y -# CONFIG_SERIAL_CONSOLE_NONE is not set - -# -# Architecture Options -# -# CONFIG_ARCH_NOINTC is not set -# CONFIG_ARCH_VECNOTIRQ is not set -# CONFIG_ARCH_DMA is not set -# CONFIG_ARCH_HAVE_IRQPRIO is not set -# CONFIG_ARCH_L2CACHE is not set -# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set -# CONFIG_ARCH_HAVE_ADDRENV is not set -# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set -# CONFIG_ARCH_HAVE_MULTICPU is not set -CONFIG_ARCH_HAVE_VFORK=y -# CONFIG_ARCH_HAVE_MMU is not set -# CONFIG_ARCH_HAVE_MPU is not set -# CONFIG_ARCH_NAND_HWECC is not set -# CONFIG_ARCH_HAVE_EXTCLK is not set -CONFIG_ARCH_HAVE_POWEROFF=y -# CONFIG_ARCH_HAVE_RESET is not set -CONFIG_ARCH_STACKDUMP=y -# CONFIG_ENDIAN_BIG is not set -# CONFIG_ARCH_IDLE_CUSTOM is not set -# CONFIG_ARCH_HAVE_RAMFUNCS is not set -# CONFIG_ARCH_HAVE_RAMVECTORS is not set - -# -# Board Settings -# -CONFIG_BOARD_LOOPSPERMSEC=1250 -# CONFIG_ARCH_CALIBRATION is not set - -# -# Interrupt options -# -CONFIG_ARCH_HAVE_INTERRUPTSTACK=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set - -# -# Boot options -# -# CONFIG_BOOT_RUNFROMEXTSRAM is not set -# CONFIG_BOOT_RUNFROMFLASH is not set -CONFIG_BOOT_RUNFROMISRAM=y -# CONFIG_BOOT_RUNFROMSDRAM is not set -# CONFIG_BOOT_COPYTORAM is not set - -# -# Boot Memory Configuration -# -CONFIG_RAM_START=0x00800000 -CONFIG_RAM_SIZE=262144 -# CONFIG_ARCH_HAVE_SDRAM is not set - -# -# Board Selection -# -# CONFIG_ARCH_BOARD_COMPALE86 is not set -# CONFIG_ARCH_BOARD_COMPALE88 is not set -# CONFIG_ARCH_BOARD_COMPALE99 is not set -CONFIG_ARCH_BOARD_PIRELLI_DPL10=y -# CONFIG_ARCH_BOARD_CUSTOM is not set -CONFIG_ARCH_BOARD="pirelli_dpl10" - -# -# Common Board Options -# -CONFIG_NSH_MMCSDMINOR=0 - -# -# Board-Specific Options -# -CONFIG_LIB_BOARDCTL=y -CONFIG_BOARDCTL_POWEROFF=y -# CONFIG_BOARDCTL_UNIQUEID is not set -# CONFIG_BOARDCTL_TSCTEST is not set -# CONFIG_BOARDCTL_GRAPHICS is not set -# CONFIG_BOARDCTL_IOCTL is not set - -# -# RTOS Features -# -CONFIG_DISABLE_OS_API=y -# CONFIG_DISABLE_POSIX_TIMERS is not set -# CONFIG_DISABLE_PTHREAD is not set -# CONFIG_DISABLE_SIGNALS is not set -CONFIG_DISABLE_MQUEUE=y -# CONFIG_DISABLE_ENVIRON is not set - -# -# Clocks and Timers -# -CONFIG_USEC_PER_TICK=10000 -# CONFIG_SYSTEM_TIME64 is not set -# CONFIG_CLOCK_MONOTONIC is not set -# CONFIG_JULIAN_TIME is not set -CONFIG_START_YEAR=2007 -CONFIG_START_MONTH=2 -CONFIG_START_DAY=13 -CONFIG_MAX_WDOGPARMS=4 -CONFIG_PREALLOC_WDOGS=8 -CONFIG_WDOG_INTRESERVE=1 -CONFIG_PREALLOC_TIMERS=8 - -# -# Tasks and Scheduling -# -# CONFIG_INIT_NONE is not set -CONFIG_INIT_ENTRYPOINT=y -# CONFIG_INIT_FILEPATH is not set -CONFIG_USER_ENTRYPOINT="nsh_main" -CONFIG_RR_INTERVAL=200 -# CONFIG_SCHED_SPORADIC is not set -CONFIG_TASK_NAME_SIZE=0 -CONFIG_MAX_TASKS=16 -# CONFIG_SCHED_HAVE_PARENT is not set -# CONFIG_SCHED_WAITPID is not set - -# -# Pthread Options -# -# CONFIG_MUTEX_TYPES is not set -CONFIG_NPTHREAD_KEYS=4 - -# -# Performance Monitoring -# -# CONFIG_SCHED_CPULOAD is not set -# CONFIG_SCHED_INSTRUMENTATION is not set - -# -# Files and I/O -# -CONFIG_DEV_CONSOLE=y -# CONFIG_FDCLONE_DISABLE is not set -# CONFIG_FDCLONE_STDIO is not set -CONFIG_SDCLONE_DISABLE=y -CONFIG_NFILE_DESCRIPTORS=8 -CONFIG_NFILE_STREAMS=8 -CONFIG_NAME_MAX=32 -# CONFIG_PRIORITY_INHERITANCE is not set - -# -# RTOS hooks -# -# CONFIG_BOARD_INITIALIZE is not set -# CONFIG_SCHED_STARTHOOK is not set -# CONFIG_SCHED_ATEXIT is not set -# CONFIG_SCHED_ONEXIT is not set - -# -# Signal Numbers -# -CONFIG_SIG_SIGUSR1=1 -CONFIG_SIG_SIGUSR2=2 -CONFIG_SIG_SIGALARM=3 -CONFIG_SIG_SIGCONDTIMEDOUT=16 -# CONFIG_MODULE is not set - -# -# Work queue support -# -# CONFIG_SCHED_WORKQUEUE is not set -# CONFIG_SCHED_HPWORK is not set -# CONFIG_SCHED_LPWORK is not set - -# -# Stack and heap information -# -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_USERMAIN_STACKSIZE=2048 -CONFIG_PTHREAD_STACK_MIN=256 -CONFIG_PTHREAD_STACK_DEFAULT=2048 -# CONFIG_LIB_SYSCALL is not set - -# -# Device Drivers -# -CONFIG_DISABLE_POLL=y -CONFIG_DEV_NULL=y -# CONFIG_DEV_ZERO is not set -# CONFIG_DEV_LOOP is not set - -# -# Buffering -# -# CONFIG_DRVR_WRITEBUFFER is not set -# CONFIG_DRVR_READAHEAD is not set -# CONFIG_RAMDISK is not set -# CONFIG_CAN is not set -# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set -# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set -# CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set -# CONFIG_I2C is not set -CONFIG_SPI=y -# CONFIG_SPI_SLAVE is not set -CONFIG_SPI_EXCHANGE=y -# CONFIG_SPI_CMDDATA is not set -# CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set -# CONFIG_SPI_CS_DELAY_CONTROL is not set -# CONFIG_I2S is not set - -# -# Timer Driver Support -# -# CONFIG_TIMER is not set -# CONFIG_RTC is not set -# CONFIG_WATCHDOG is not set -# CONFIG_ANALOG is not set -# CONFIG_AUDIO_DEVICES is not set -# CONFIG_VIDEO_DEVICES is not set -# CONFIG_BCH is not set -# CONFIG_INPUT is not set -# CONFIG_IOEXPANDER is not set - -# -# LCD Driver Support -# -# CONFIG_LCD is not set -# CONFIG_SLCD is not set - -# -# LED Support -# -# CONFIG_RGBLED is not set -# CONFIG_PCA9635PW is not set -# CONFIG_NCP5623C is not set -# CONFIG_MMCSD is not set -# CONFIG_MODEM is not set -# CONFIG_MTD is not set -# CONFIG_EEPROM is not set -# CONFIG_PIPES is not set -# CONFIG_PM is not set -# CONFIG_POWER is not set -# CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set -CONFIG_SERIAL=y -# CONFIG_DEV_LOWCONSOLE is not set -# CONFIG_SERIAL_REMOVABLE is not set -CONFIG_SERIAL_CONSOLE=y -# CONFIG_16550_UART is not set -# CONFIG_UART_SERIALDRIVER is not set -# CONFIG_UART0_SERIALDRIVER is not set -# CONFIG_UART1_SERIALDRIVER is not set -# CONFIG_UART2_SERIALDRIVER is not set -# CONFIG_UART3_SERIALDRIVER is not set -# CONFIG_UART4_SERIALDRIVER is not set -# CONFIG_UART5_SERIALDRIVER is not set -# CONFIG_UART6_SERIALDRIVER is not set -# CONFIG_UART7_SERIALDRIVER is not set -# CONFIG_UART8_SERIALDRIVER is not set -# CONFIG_SCI0_SERIALDRIVER is not set -# CONFIG_SCI1_SERIALDRIVER is not set -# CONFIG_USART0_SERIALDRIVER is not set -# CONFIG_USART1_SERIALDRIVER is not set -# CONFIG_USART2_SERIALDRIVER is not set -# CONFIG_USART3_SERIALDRIVER is not set -# CONFIG_USART4_SERIALDRIVER is not set -# CONFIG_USART5_SERIALDRIVER is not set -# CONFIG_USART6_SERIALDRIVER is not set -# CONFIG_USART7_SERIALDRIVER is not set -# CONFIG_USART8_SERIALDRIVER is not set -CONFIG_OTHER_UART_SERIALDRIVER=y -CONFIG_MCU_SERIAL=y -# CONFIG_STANDARD_SERIAL is not set -# CONFIG_SERIAL_IFLOWCONTROL is not set -# CONFIG_SERIAL_OFLOWCONTROL is not set -# CONFIG_SERIAL_DMA is not set -# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set -CONFIG_OTHER_SERIAL_CONSOLE=y -# CONFIG_NO_SERIAL_CONSOLE is not set -# CONFIG_USBDEV is not set -# CONFIG_USBHOST is not set -# CONFIG_DRIVERS_WIRELESS is not set - -# -# System Logging -# -# CONFIG_ARCH_SYSLOG is not set -# CONFIG_RAMLOG is not set -# CONFIG_SYSLOG_INTBUFFER is not set -# CONFIG_SYSLOG_TIMESTAMP is not set -CONFIG_SYSLOG_SERIAL_CONSOLE=y -# CONFIG_SYSLOG_CHAR is not set -CONFIG_SYSLOG_CONSOLE=y -# CONFIG_SYSLOG_NONE is not set -# CONFIG_SYSLOG_FILE is not set - -# -# Networking Support -# -# CONFIG_ARCH_HAVE_NET is not set -# CONFIG_ARCH_HAVE_PHY is not set -# CONFIG_NET is not set - -# -# Crypto API -# -# CONFIG_CRYPTO is not set - -# -# File Systems -# - -# -# File system configuration -# -# CONFIG_DISABLE_MOUNTPOINT is not set -# CONFIG_FS_AUTOMOUNTER is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_FS_READABLE is not set -# CONFIG_FS_WRITABLE is not set -# CONFIG_FS_NAMED_SEMAPHORES is not set -# CONFIG_FS_RAMMAP is not set -# CONFIG_FS_FAT is not set -# CONFIG_FS_NXFFS is not set -# CONFIG_FS_ROMFS is not set -# CONFIG_FS_TMPFS is not set -# CONFIG_FS_SMARTFS is not set -# CONFIG_FS_BINFS is not set -# CONFIG_FS_PROCFS is not set -# CONFIG_FS_UNIONFS is not set - -# -# Graphics Support -# -# CONFIG_NX is not set - -# -# Memory Management -# -# CONFIG_MM_SMALL is not set -CONFIG_MM_REGIONS=1 -CONFIG_ARCH_HAVE_HEAP2=y -CONFIG_HEAP2_BASE=0x00000000 -CONFIG_HEAP2_SIZE=0 -# CONFIG_GRAN is not set - -# -# Audio Support -# -# CONFIG_AUDIO is not set - -# -# Wireless Support -# - -# -# Binary Loader -# -# CONFIG_BINFMT_DISABLE is not set -# CONFIG_BINFMT_EXEPATH is not set -# CONFIG_NXFLAT is not set -# CONFIG_ELF is not set -CONFIG_BUILTIN=y -# CONFIG_PIC is not set -# CONFIG_SYMTAB_ORDEREDBYNAME is not set - -# -# Library Routines -# - -# -# Standard C Library Options -# -CONFIG_STDIO_BUFFER_SIZE=1024 -CONFIG_STDIO_LINEBUFFER=y -CONFIG_NUNGET_CHARS=2 -CONFIG_LIB_HOMEDIR="/" -# CONFIG_LIBM is not set -# CONFIG_NOPRINTF_FIELDWIDTH is not set -# CONFIG_LIBC_FLOATINGPOINT is not set -CONFIG_LIBC_LONG_LONG=y -# CONFIG_LIBC_IOCTL_VARIADIC is not set -CONFIG_LIB_RAND_ORDER=1 -# CONFIG_EOL_IS_CR is not set -# CONFIG_EOL_IS_LF is not set -# CONFIG_EOL_IS_BOTH_CRLF is not set -CONFIG_EOL_IS_EITHER_CRLF=y -# CONFIG_LIBC_EXECFUNCS is not set -CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 -CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 -# CONFIG_LIBC_STRERROR is not set -# CONFIG_LIBC_PERROR_STDOUT is not set -CONFIG_ARCH_LOWPUTC=y -# CONFIG_LIBC_LOCALTIME is not set -# CONFIG_TIME_EXTENDED is not set -CONFIG_LIB_SENDFILE_BUFSIZE=512 -# CONFIG_ARCH_ROMGETC is not set -# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set -CONFIG_ARCH_HAVE_TLS=y -# CONFIG_TLS is not set -# CONFIG_LIBC_NETDB is not set - -# -# Non-standard Library Support -# -# CONFIG_LIB_CRC64_FAST is not set -# CONFIG_LIB_KBDCODEC is not set -# CONFIG_LIB_SLCDCODEC is not set - -# -# Basic CXX Support -# -# CONFIG_C99_BOOL8 is not set -# CONFIG_HAVE_CXX is not set - -# -# Application Configuration -# - -# -# Built-In Applications -# -CONFIG_BUILTIN_PROXY_STACKSIZE=1024 - -# -# CAN Utilities -# - -# -# Examples -# -# CONFIG_EXAMPLES_CHAT is not set -# CONFIG_EXAMPLES_CONFIGDATA is not set -# CONFIG_EXAMPLES_CPUHOG is not set -# CONFIG_EXAMPLES_DHCPD is not set -# CONFIG_EXAMPLES_ELF is not set -# CONFIG_EXAMPLES_FTPC is not set -# CONFIG_EXAMPLES_FTPD is not set -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_HELLO_PRIORITY=100 -CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 -# CONFIG_EXAMPLES_HIDKBD is not set -# CONFIG_EXAMPLES_IGMP is not set -# CONFIG_EXAMPLES_JSON is not set -# CONFIG_EXAMPLES_KEYPADTEST is not set -# CONFIG_EXAMPLES_MEDIA is not set -# CONFIG_EXAMPLES_MM is not set -# CONFIG_EXAMPLES_MODBUS is not set -# CONFIG_EXAMPLES_MOUNT is not set -# CONFIG_EXAMPLES_NRF24L01TERM is not set -CONFIG_EXAMPLES_NSH=y -# CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set -# CONFIG_EXAMPLES_NXFFS is not set -# CONFIG_EXAMPLES_NXHELLO is not set -# CONFIG_EXAMPLES_NXIMAGE is not set -# CONFIG_EXAMPLES_NXLINES is not set -# CONFIG_EXAMPLES_NXTERM is not set -# CONFIG_EXAMPLES_NXTEXT is not set -# CONFIG_EXAMPLES_OSTEST is not set -# CONFIG_EXAMPLES_PCA9635 is not set -# CONFIG_EXAMPLES_PIPE is not set -# CONFIG_EXAMPLES_POSIXSPAWN is not set -# CONFIG_EXAMPLES_PPPD is not set -# CONFIG_EXAMPLES_RGBLED is not set -# CONFIG_EXAMPLES_SENDMAIL is not set -# CONFIG_EXAMPLES_SERIALBLASTER is not set -# CONFIG_EXAMPLES_SERIALRX is not set -# CONFIG_EXAMPLES_SERLOOP is not set -# CONFIG_EXAMPLES_SLCD is not set -# CONFIG_EXAMPLES_SMART is not set -# CONFIG_EXAMPLES_SMART_TEST is not set -# CONFIG_EXAMPLES_SMP is not set -# CONFIG_EXAMPLES_TCPECHO is not set -# CONFIG_EXAMPLES_TELNETD is not set -# CONFIG_EXAMPLES_TIFF is not set -# CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_USBSERIAL is not set -# CONFIG_EXAMPLES_USBTERM is not set -# CONFIG_EXAMPLES_WATCHDOG is not set -# CONFIG_EXAMPLES_WEBSERVER is not set - -# -# File System Utilities -# -# CONFIG_FSUTILS_INIFILE is not set - -# -# GPS Utilities -# -# CONFIG_GPSUTILS_MINMEA_LIB is not set - -# -# Graphics Support -# -# CONFIG_TIFF is not set -# CONFIG_GRAPHICS_TRAVELER is not set - -# -# Interpreters -# -# CONFIG_INTERPRETERS_FICL is not set -# CONFIG_INTERPRETERS_MICROPYTHON is not set -# CONFIG_INTERPRETERS_PCODE is not set - -# -# FreeModBus -# -# CONFIG_MODBUS is not set - -# -# Network Utilities -# -# CONFIG_NETUTILS_CODECS is not set -# CONFIG_NETUTILS_ESP8266 is not set -# CONFIG_NETUTILS_FTPC is not set -# CONFIG_NETUTILS_JSON is not set -# CONFIG_NETUTILS_SMTP is not set - -# -# NSH Library -# -CONFIG_NSH_LIBRARY=y -# CONFIG_NSH_MOTD is not set - -# -# Command Line Configuration -# -CONFIG_NSH_READLINE=y -# CONFIG_NSH_CLE is not set -CONFIG_NSH_LINELEN=64 -# CONFIG_NSH_DISABLE_SEMICOLON is not set -CONFIG_NSH_CMDPARMS=y -CONFIG_NSH_MAXARGUMENTS=6 -CONFIG_NSH_ARGCAT=y -CONFIG_NSH_NESTDEPTH=3 -# CONFIG_NSH_DISABLEBG is not set -CONFIG_NSH_BUILTIN_APPS=y - -# -# Disable Individual commands -# -# CONFIG_NSH_DISABLE_ADDROUTE is not set -# CONFIG_NSH_DISABLE_BASENAME is not set -# CONFIG_NSH_DISABLE_CAT is not set -# CONFIG_NSH_DISABLE_CD is not set -# CONFIG_NSH_DISABLE_CP is not set -# CONFIG_NSH_DISABLE_CMP is not set -CONFIG_NSH_DISABLE_DATE=y -# CONFIG_NSH_DISABLE_DD is not set -# CONFIG_NSH_DISABLE_DF is not set -# CONFIG_NSH_DISABLE_DELROUTE is not set -# CONFIG_NSH_DISABLE_DIRNAME is not set -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HELP is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -CONFIG_NSH_DISABLE_IFUPDOWN=y -# CONFIG_NSH_DISABLE_KILL is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -CONFIG_NSH_DISABLE_LOSMART=y -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_MB is not set -# CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKFIFO is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_MH is not set -# CONFIG_NSH_DISABLE_MOUNT is not set -# CONFIG_NSH_DISABLE_MV is not set -# CONFIG_NSH_DISABLE_MW is not set -# CONFIG_NSH_DISABLE_POWEROFF is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_PWD is not set -# CONFIG_NSH_DISABLE_RM is not set -# CONFIG_NSH_DISABLE_RMDIR is not set -# CONFIG_NSH_DISABLE_SET is not set -# CONFIG_NSH_DISABLE_SH is not set -CONFIG_NSH_DISABLE_SHUTDOWN=y -# CONFIG_NSH_DISABLE_SLEEP is not set -# CONFIG_NSH_DISABLE_TIME is not set -# CONFIG_NSH_DISABLE_TEST is not set -# CONFIG_NSH_DISABLE_UMOUNT is not set -# CONFIG_NSH_DISABLE_UNAME is not set -# CONFIG_NSH_DISABLE_UNSET is not set -# CONFIG_NSH_DISABLE_USLEEP is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set - -# -# Configure Command Options -# -# CONFIG_NSH_CMDOPT_DF_H is not set -CONFIG_NSH_CODECS_BUFSIZE=128 -CONFIG_NSH_CMDOPT_HEXDUMP=y -CONFIG_NSH_FILEIOSIZE=1024 - -# -# Scripting Support -# -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_ITEF is not set -# CONFIG_NSH_DISABLE_LOOPS is not set - -# -# Console Configuration -# -CONFIG_NSH_CONSOLE=y -# CONFIG_NSH_ALTCONDEV is not set -# CONFIG_NSH_ARCHINIT is not set -# CONFIG_NSH_LOGIN is not set -# CONFIG_NSH_CONSOLE_LOGIN is not set - -# -# NxWidgets/NxWM -# - -# -# Platform-specific Support -# -# CONFIG_PLATFORM_CONFIGDATA is not set - -# -# System Libraries and NSH Add-Ons -# -# CONFIG_SYSTEM_CLE is not set -# CONFIG_SYSTEM_CUTERM is not set -# CONFIG_SYSTEM_FREE is not set -# CONFIG_LIB_HEX2BIN is not set -# CONFIG_SYSTEM_HEXED is not set -# CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_RAMTEST is not set -CONFIG_READLINE_HAVE_EXTMATCH=y -CONFIG_SYSTEM_READLINE=y -CONFIG_READLINE_ECHO=y -# CONFIG_READLINE_TABCOMPLETION is not set -# CONFIG_READLINE_CMD_HISTORY is not set -# CONFIG_SYSTEM_SUDOKU is not set -# CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_VI is not set -# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/pirelli_dpl10/nsh_highram/setenv.sh b/configs/pirelli_dpl10/nsh_highram/setenv.sh deleted file mode 100755 index 56d2c4cf94..0000000000 --- a/configs/pirelli_dpl10/nsh_highram/setenv.sh +++ /dev/null @@ -1,62 +0,0 @@ -#!/bin/bash -# configs/pirelli_dpl10/nsh/setenv.sh -# -# Copyright (C) 2007, 2008, 2011, 2013 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -if [ "$_" = "$0" ] ; then - echo "You must source this script, not run it!" 1>&2 - exit 1 -fi - -WD=`pwd` -if [ ! -x "setenv.sh" ]; then - echo "This script must be executed from the top-level NuttX build directory" - exit 1 -fi - -if [ -z "${PATH_ORIG}" ]; then - export PATH_ORIG="${PATH}" -fi - -# This is the Cygwin path to the location where I installed the CodeSourcery -# toolchain under windows. You will also have to edit this if you install -# the CodeSourcery toolchain in any other location -#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" - -# This is the Cygwin path to the location where I build the buildroot -# toolchain. -export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" - -# Add the path to the toolchain to the PATH varialble -export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" - -echo "PATH : ${PATH}" diff --git a/configs/pirelli_dpl10/scripts/highram.ld b/configs/pirelli_dpl10/scripts/highram.ld deleted file mode 100644 index f20a5f89c2..0000000000 --- a/configs/pirelli_dpl10/scripts/highram.ld +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Linker script for running from internal SRAM on Pirelli DP-L10 phones - * - * This script is tailored specifically to the requirements imposed - * on us by the CalypsoRomloader in the Pirelli rom. - * - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(__start) - -MEMORY -{ - /* 0x00800000-0x0082000: Low RAM. Used only for exception vectors */ - - LRAM (rw) : ORIGIN = 0x00800000, LENGTH = 0x00020000 - - /* 0x00820000-0x0084000: High RAM. The CalypsoRomloader loads binary to - * address 0x00820000 */ - - HRAM (rw) : ORIGIN = 0x00820000, LENGTH = 0x00020000 -} - -SECTIONS -{ - . = 0x800000; - - /* romloader data section, contains passthru interrupt vectors */ - .compal.loader (NOLOAD) : { . = 0x100; } > LRAM - - /* image signature (prepended by osmocon according to phone type) */ - .compal.header (NOLOAD) : { . = 4; } > LRAM - - /* initialization code */ - . = ALIGN(4); - .text.start : { - PROVIDE(__start = .); - KEEP(*(.text.start)) - *(.text.start) - } > HRAM - - /* exception vectors from 0x80001c to 0x800034 */ - .text.exceptions 0x80001c : AT (LOADADDR(.text.start) + SIZEOF(.text.start)) { - KEEP(*(.text.exceptions)) - * (.text.exceptions) - . = ALIGN(4); - } > LRAM - PROVIDE(_exceptions = LOADADDR(.text.exceptions)); - - /* code */ - . = ALIGN(4); - .text (LOADADDR(.text.exceptions) + SIZEOF(.text.exceptions)) : - AT (LOADADDR(.text.exceptions) + SIZEOF(.text.exceptions)) { - /* regular code */ - *(.text*) - /* always-in-ram code */ - *(.ramtext*) - /* gcc voodoo */ - *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx) - . = ALIGN(4); - } > HRAM - PROVIDE(_text_start = LOADADDR(.text)); - PROVIDE(_text_end = LOADADDR(.text) + SIZEOF(.text)); - - /* constructor pointers */ - .ctors : { - /* ctor count */ - LONG(SIZEOF(.ctors) / 4 - 2) - /* ctor pointers */ - KEEP(*(SORT(.ctors))) - /* end of list */ - LONG(0) - } > HRAM - PROVIDE(_ctor_start = LOADADDR(.ctors)); - PROVIDE(_ctor_end = LOADADDR(.ctors) + SIZEOF(.ctors)); - - /* destructor pointers */ - .dtors : { - /* dtor count */ - LONG(SIZEOF(.dtors) / 4 - 2) - /* dtor pointers */ - KEEP(*(SORT(.dtors))) - /* end of list */ - LONG(0) - } > HRAM - PROVIDE(_dtor_start = LOADADDR(.dtors)); - PROVIDE(_dtor_end = LOADADDR(.dtors) + SIZEOF(.dtors)); - - /* read-only data */ - . = ALIGN(4); - .rodata : { - *(.rodata*) - } > HRAM - PROVIDE(_rodata_start = LOADADDR(.rodata)); - PROVIDE(_rodata_end = LOADADDR(.rodata) + SIZEOF(.rodata)); - - /* initialized data */ - . = ALIGN(4); - .data : { - *(.data) - } > HRAM - PROVIDE(_data_start = LOADADDR(.data)); - PROVIDE(_data_end = LOADADDR(.data) + SIZEOF(.data)); - - /* pic offset tables */ - . = ALIGN(4); - .got : { - *(.got) - *(.got.plt) *(.igot.plt) *(.got) *(.igot) - } > HRAM - PROVIDE(_got_start = LOADADDR(.got)); - PROVIDE(_got_end = LOADADDR(.got) + SIZEOF(.got)); - - /* uninitialized data */ - .bss (NOLOAD) : { - . = ALIGN(4); - __bss_start = .; - _sbss = ABSOLUTE(.); - *(.bss) - _ebss = ABSOLUTE(.); - } > HRAM - . = ALIGN(4); - __bss_end = .; - PROVIDE(_bss_start = __bss_start); - PROVIDE(_bss_end = __bss_end); - - /* end of image */ - . = ALIGN(4); - _end = .; - PROVIDE(end = .); -} diff --git a/configs/pirelli_dpl10/src/.gitignore b/configs/pirelli_dpl10/src/.gitignore deleted file mode 100644 index 726d936e1e..0000000000 --- a/configs/pirelli_dpl10/src/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -/.depend -/Make.dep diff --git a/configs/pirelli_dpl10/src/Makefile b/configs/pirelli_dpl10/src/Makefile deleted file mode 100644 index 4026b5fb1c..0000000000 --- a/configs/pirelli_dpl10/src/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -############################################################################ -# configs/pirelli_dpl10/src/Makefile -# -# Copyright (C) 2007, 2008, 2013 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Copyright (C) 2011 Stefan Richter. All rights reserved. -# Author: Stefan Richter -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - --include $(TOPDIR)/Make.defs - -ASRCS = -CSRCS = boot.c - -include $(TOPDIR)/configs/Board.mk diff --git a/configs/pirelli_dpl10/src/boot.c b/configs/pirelli_dpl10/src/boot.c deleted file mode 100644 index 38d1fe8ac2..0000000000 --- a/configs/pirelli_dpl10/src/boot.c +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * configs/pirelli_dpl10/boot.c - * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_app_initialize - * - * Description: - * Perform application specific initialization. This function is never - * called directly from application code, but only indirectly via the - * (non-standard) boardctl() interface using the command BOARDIOC_INIT. - * - * Input Parameters: - * arg - The boardctl() argument is passed to the board_app_initialize() - * implementation without modification. The argument has no - * meaning to NuttX; the meaning of the argument is a contract - * between the board-specific initalization logic and the the - * matching application logic. The value cold be such things as a - * mode enumeration value, a set of DIP switch switch settings, a - * pointer to configuration data read from a file or serial FLASH, - * or whatever you would like to do with it. Every implementation - * should accept zero/NULL as a default configuration. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_LIB_BOARDCTL -int board_app_initialize(uintptr_t arg) -{ - return 0; -} -#endif /* CONFIG_LIB_BOARDCTL */ diff --git a/configs/sabre-6quad/nsh/defconfig b/configs/sabre-6quad/nsh/defconfig index 51c987752a..daa1d8b791 100644 --- a/configs/sabre-6quad/nsh/defconfig +++ b/configs/sabre-6quad/nsh/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sabre-6quad/smp/defconfig b/configs/sabre-6quad/smp/defconfig index 7bd54f8c70..3ddf587c09 100644 --- a/configs/sabre-6quad/smp/defconfig +++ b/configs/sabre-6quad/smp/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sam3u-ek/knsh/defconfig b/configs/sam3u-ek/knsh/defconfig index 2fec468447..53f3338fcf 100644 --- a/configs/sam3u-ek/knsh/defconfig +++ b/configs/sam3u-ek/knsh/defconfig @@ -77,7 +77,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sam3u-ek/nsh/defconfig b/configs/sam3u-ek/nsh/defconfig index 4607e053cc..424d740a73 100644 --- a/configs/sam3u-ek/nsh/defconfig +++ b/configs/sam3u-ek/nsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sam3u-ek/nx/defconfig b/configs/sam3u-ek/nx/defconfig index 2b1876e763..1cdcce9d1c 100644 --- a/configs/sam3u-ek/nx/defconfig +++ b/configs/sam3u-ek/nx/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sam3u-ek/nxwm/defconfig b/configs/sam3u-ek/nxwm/defconfig index 5358c385b2..8002fb2885 100644 --- a/configs/sam3u-ek/nxwm/defconfig +++ b/configs/sam3u-ek/nxwm/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sam4cmp-db/nsh/defconfig b/configs/sam4cmp-db/nsh/defconfig index 6eb1691432..9175b32a13 100644 --- a/configs/sam4cmp-db/nsh/defconfig +++ b/configs/sam4cmp-db/nsh/defconfig @@ -104,7 +104,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sam4e-ek/nsh/defconfig b/configs/sam4e-ek/nsh/defconfig index ea0145d431..264bd8063b 100644 --- a/configs/sam4e-ek/nsh/defconfig +++ b/configs/sam4e-ek/nsh/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sam4e-ek/nxwm/defconfig b/configs/sam4e-ek/nxwm/defconfig index 7f1d48a118..e5bf010054 100644 --- a/configs/sam4e-ek/nxwm/defconfig +++ b/configs/sam4e-ek/nxwm/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sam4e-ek/usbnsh/defconfig b/configs/sam4e-ek/usbnsh/defconfig index 095a827bda..717b13c4d2 100644 --- a/configs/sam4e-ek/usbnsh/defconfig +++ b/configs/sam4e-ek/usbnsh/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sam4l-xplained/nsh/defconfig b/configs/sam4l-xplained/nsh/defconfig index def321022b..e08bac68fd 100644 --- a/configs/sam4l-xplained/nsh/defconfig +++ b/configs/sam4l-xplained/nsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sam4s-xplained-pro/nsh/defconfig b/configs/sam4s-xplained-pro/nsh/defconfig index a77d893167..d81f101294 100644 --- a/configs/sam4s-xplained-pro/nsh/defconfig +++ b/configs/sam4s-xplained-pro/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sam4s-xplained/nsh/defconfig b/configs/sam4s-xplained/nsh/defconfig index b7ccf03ad3..87f20e61a7 100644 --- a/configs/sam4s-xplained/nsh/defconfig +++ b/configs/sam4s-xplained/nsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sama5d2-xult/nsh/defconfig b/configs/sama5d2-xult/nsh/defconfig index c524993839..424cc780d1 100644 --- a/configs/sama5d2-xult/nsh/defconfig +++ b/configs/sama5d2-xult/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sama5d3-xplained/bridge/defconfig b/configs/sama5d3-xplained/bridge/defconfig index 51c672c066..5fdf2964d7 100644 --- a/configs/sama5d3-xplained/bridge/defconfig +++ b/configs/sama5d3-xplained/bridge/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sama5d3-xplained/nsh/defconfig b/configs/sama5d3-xplained/nsh/defconfig index f527aefe04..930ffa3db4 100644 --- a/configs/sama5d3-xplained/nsh/defconfig +++ b/configs/sama5d3-xplained/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sama5d3x-ek/demo/defconfig b/configs/sama5d3x-ek/demo/defconfig index 521ace3b80..761e7ae57c 100644 --- a/configs/sama5d3x-ek/demo/defconfig +++ b/configs/sama5d3x-ek/demo/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sama5d3x-ek/hello/defconfig b/configs/sama5d3x-ek/hello/defconfig index 80ad780990..b5127834f8 100644 --- a/configs/sama5d3x-ek/hello/defconfig +++ b/configs/sama5d3x-ek/hello/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sama5d3x-ek/norboot/defconfig b/configs/sama5d3x-ek/norboot/defconfig index 349fff0a1a..29022a34d3 100644 --- a/configs/sama5d3x-ek/norboot/defconfig +++ b/configs/sama5d3x-ek/norboot/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sama5d3x-ek/nsh/defconfig b/configs/sama5d3x-ek/nsh/defconfig index 8c5a5954ae..dbace7c89c 100644 --- a/configs/sama5d3x-ek/nsh/defconfig +++ b/configs/sama5d3x-ek/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sama5d3x-ek/nx/defconfig b/configs/sama5d3x-ek/nx/defconfig index bad74c5af8..3532962812 100644 --- a/configs/sama5d3x-ek/nx/defconfig +++ b/configs/sama5d3x-ek/nx/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sama5d3x-ek/nxplayer/defconfig b/configs/sama5d3x-ek/nxplayer/defconfig index 6d6dfc0d15..c9c7526992 100644 --- a/configs/sama5d3x-ek/nxplayer/defconfig +++ b/configs/sama5d3x-ek/nxplayer/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sama5d3x-ek/nxwm/defconfig b/configs/sama5d3x-ek/nxwm/defconfig index 016756b5c6..a0abcb828d 100644 --- a/configs/sama5d3x-ek/nxwm/defconfig +++ b/configs/sama5d3x-ek/nxwm/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sama5d3x-ek/ov2640/defconfig b/configs/sama5d3x-ek/ov2640/defconfig index 61d48821a6..95ea0ac9ad 100644 --- a/configs/sama5d3x-ek/ov2640/defconfig +++ b/configs/sama5d3x-ek/ov2640/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sama5d4-ek/at25boot/defconfig b/configs/sama5d4-ek/at25boot/defconfig index 2d4c89081f..d7290202de 100644 --- a/configs/sama5d4-ek/at25boot/defconfig +++ b/configs/sama5d4-ek/at25boot/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sama5d4-ek/bridge/defconfig b/configs/sama5d4-ek/bridge/defconfig index a02e653903..ca94b121e1 100644 --- a/configs/sama5d4-ek/bridge/defconfig +++ b/configs/sama5d4-ek/bridge/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sama5d4-ek/dramboot/defconfig b/configs/sama5d4-ek/dramboot/defconfig index f0f68c6855..2fadab3a1c 100644 --- a/configs/sama5d4-ek/dramboot/defconfig +++ b/configs/sama5d4-ek/dramboot/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sama5d4-ek/elf/defconfig b/configs/sama5d4-ek/elf/defconfig index b55fc14606..0c51be98ea 100644 --- a/configs/sama5d4-ek/elf/defconfig +++ b/configs/sama5d4-ek/elf/defconfig @@ -77,7 +77,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sama5d4-ek/ipv6/defconfig b/configs/sama5d4-ek/ipv6/defconfig index a4488a7647..7d2d826b28 100644 --- a/configs/sama5d4-ek/ipv6/defconfig +++ b/configs/sama5d4-ek/ipv6/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sama5d4-ek/knsh/defconfig b/configs/sama5d4-ek/knsh/defconfig index 372200adb0..b0fd035fad 100644 --- a/configs/sama5d4-ek/knsh/defconfig +++ b/configs/sama5d4-ek/knsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sama5d4-ek/knsh/defconfig.ROMFS b/configs/sama5d4-ek/knsh/defconfig.ROMFS index 1e11783700..91d49d841b 100644 --- a/configs/sama5d4-ek/knsh/defconfig.ROMFS +++ b/configs/sama5d4-ek/knsh/defconfig.ROMFS @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_IMX1 is not set # CONFIG_ARCH_CHIP_KINETIS is not set diff --git a/configs/sama5d4-ek/nsh/defconfig b/configs/sama5d4-ek/nsh/defconfig index dff96a156d..22b8c8931e 100644 --- a/configs/sama5d4-ek/nsh/defconfig +++ b/configs/sama5d4-ek/nsh/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sama5d4-ek/nxwm/defconfig b/configs/sama5d4-ek/nxwm/defconfig index e890dab1a6..4f3a2904f7 100644 --- a/configs/sama5d4-ek/nxwm/defconfig +++ b/configs/sama5d4-ek/nxwm/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/sama5d4-ek/ramtest/defconfig b/configs/sama5d4-ek/ramtest/defconfig index 8b7eb08c69..e17821e104 100644 --- a/configs/sama5d4-ek/ramtest/defconfig +++ b/configs/sama5d4-ek/ramtest/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/samd20-xplained/nsh/defconfig b/configs/samd20-xplained/nsh/defconfig index 973d39e7ec..ecb302a397 100644 --- a/configs/samd20-xplained/nsh/defconfig +++ b/configs/samd20-xplained/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/samd21-xplained/nsh/defconfig b/configs/samd21-xplained/nsh/defconfig index 0428f7b746..08e9d330ec 100644 --- a/configs/samd21-xplained/nsh/defconfig +++ b/configs/samd21-xplained/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/same70-xplained/netnsh/defconfig b/configs/same70-xplained/netnsh/defconfig index d46655853d..0069f726ac 100644 --- a/configs/same70-xplained/netnsh/defconfig +++ b/configs/same70-xplained/netnsh/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/same70-xplained/nsh/defconfig b/configs/same70-xplained/nsh/defconfig index 8f45a3dba3..204304f086 100644 --- a/configs/same70-xplained/nsh/defconfig +++ b/configs/same70-xplained/nsh/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/saml21-xplained/nsh/defconfig b/configs/saml21-xplained/nsh/defconfig index 2306bef6b9..17a9dca981 100644 --- a/configs/saml21-xplained/nsh/defconfig +++ b/configs/saml21-xplained/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/samv71-xult/knsh/defconfig b/configs/samv71-xult/knsh/defconfig index 400e510fb0..a405803266 100644 --- a/configs/samv71-xult/knsh/defconfig +++ b/configs/samv71-xult/knsh/defconfig @@ -81,7 +81,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/samv71-xult/module/defconfig b/configs/samv71-xult/module/defconfig index f7457269df..daea087771 100644 --- a/configs/samv71-xult/module/defconfig +++ b/configs/samv71-xult/module/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/samv71-xult/mxtxplnd/defconfig b/configs/samv71-xult/mxtxplnd/defconfig index 4bdce00af1..e55210e0e6 100644 --- a/configs/samv71-xult/mxtxplnd/defconfig +++ b/configs/samv71-xult/mxtxplnd/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/samv71-xult/netnsh/defconfig b/configs/samv71-xult/netnsh/defconfig index e200f8f883..c533a146e1 100644 --- a/configs/samv71-xult/netnsh/defconfig +++ b/configs/samv71-xult/netnsh/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/samv71-xult/nsh/defconfig b/configs/samv71-xult/nsh/defconfig index 43cb4ab172..4d49b5ca61 100644 --- a/configs/samv71-xult/nsh/defconfig +++ b/configs/samv71-xult/nsh/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/samv71-xult/nxwm/defconfig b/configs/samv71-xult/nxwm/defconfig index 7af475dfee..e6d80b7d9a 100644 --- a/configs/samv71-xult/nxwm/defconfig +++ b/configs/samv71-xult/nxwm/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/samv71-xult/vnc/defconfig b/configs/samv71-xult/vnc/defconfig index 762455ee66..c6f2a7aa48 100644 --- a/configs/samv71-xult/vnc/defconfig +++ b/configs/samv71-xult/vnc/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/samv71-xult/vnxwm/defconfig b/configs/samv71-xult/vnxwm/defconfig index 3efe65fb47..e2eea5f424 100644 --- a/configs/samv71-xult/vnxwm/defconfig +++ b/configs/samv71-xult/vnxwm/defconfig @@ -79,7 +79,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/shenzhou/nsh/defconfig b/configs/shenzhou/nsh/defconfig index d41b177dfd..af69c7abfa 100644 --- a/configs/shenzhou/nsh/defconfig +++ b/configs/shenzhou/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/shenzhou/nxwm/defconfig b/configs/shenzhou/nxwm/defconfig index be72bc7d18..e3b6e5d788 100644 --- a/configs/shenzhou/nxwm/defconfig +++ b/configs/shenzhou/nxwm/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/shenzhou/thttpd/defconfig b/configs/shenzhou/thttpd/defconfig index f35fe1526a..f246239d2f 100644 --- a/configs/shenzhou/thttpd/defconfig +++ b/configs/shenzhou/thttpd/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/spark/composite/defconfig b/configs/spark/composite/defconfig index 80fc026185..99da95b423 100644 --- a/configs/spark/composite/defconfig +++ b/configs/spark/composite/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/spark/nsh/defconfig b/configs/spark/nsh/defconfig index 8c480ed1de..c86b4a81bb 100644 --- a/configs/spark/nsh/defconfig +++ b/configs/spark/nsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/spark/usbmsc/defconfig b/configs/spark/usbmsc/defconfig index 524811c2b9..aede0e5bd1 100644 --- a/configs/spark/usbmsc/defconfig +++ b/configs/spark/usbmsc/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/spark/usbnsh/defconfig b/configs/spark/usbnsh/defconfig index 4f0f81059b..bd658acc0f 100644 --- a/configs/spark/usbnsh/defconfig +++ b/configs/spark/usbnsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/spark/usbserial/defconfig b/configs/spark/usbserial/defconfig index dcd7afa1d2..cf1548ef7d 100644 --- a/configs/spark/usbserial/defconfig +++ b/configs/spark/usbserial/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3210e-eval/composite/defconfig b/configs/stm3210e-eval/composite/defconfig index f15376d1b6..e86878eb0b 100644 --- a/configs/stm3210e-eval/composite/defconfig +++ b/configs/stm3210e-eval/composite/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3210e-eval/nsh/defconfig b/configs/stm3210e-eval/nsh/defconfig index 64a89edb98..9cd76a6fcf 100644 --- a/configs/stm3210e-eval/nsh/defconfig +++ b/configs/stm3210e-eval/nsh/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3210e-eval/nsh2/defconfig b/configs/stm3210e-eval/nsh2/defconfig index ebe9ca441f..ed2f9de53a 100644 --- a/configs/stm3210e-eval/nsh2/defconfig +++ b/configs/stm3210e-eval/nsh2/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3210e-eval/nx/defconfig b/configs/stm3210e-eval/nx/defconfig index 39ddbeda89..515abea738 100644 --- a/configs/stm3210e-eval/nx/defconfig +++ b/configs/stm3210e-eval/nx/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3210e-eval/nxterm/defconfig b/configs/stm3210e-eval/nxterm/defconfig index f1c58151c7..f8b261f023 100644 --- a/configs/stm3210e-eval/nxterm/defconfig +++ b/configs/stm3210e-eval/nxterm/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3210e-eval/pm/defconfig b/configs/stm3210e-eval/pm/defconfig index 57fc099163..2ea8dc6299 100644 --- a/configs/stm3210e-eval/pm/defconfig +++ b/configs/stm3210e-eval/pm/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3210e-eval/usbmsc/defconfig b/configs/stm3210e-eval/usbmsc/defconfig index 78e0771998..5afafd6fe6 100644 --- a/configs/stm3210e-eval/usbmsc/defconfig +++ b/configs/stm3210e-eval/usbmsc/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3210e-eval/usbserial/defconfig b/configs/stm3210e-eval/usbserial/defconfig index b7ca54b7c7..db0f50e033 100644 --- a/configs/stm3210e-eval/usbserial/defconfig +++ b/configs/stm3210e-eval/usbserial/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3220g-eval/dhcpd/defconfig b/configs/stm3220g-eval/dhcpd/defconfig index af4f6af931..6c75dfc4de 100644 --- a/configs/stm3220g-eval/dhcpd/defconfig +++ b/configs/stm3220g-eval/dhcpd/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3220g-eval/nettest/defconfig b/configs/stm3220g-eval/nettest/defconfig index 6a21166a9a..cd5e76b2e9 100644 --- a/configs/stm3220g-eval/nettest/defconfig +++ b/configs/stm3220g-eval/nettest/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3220g-eval/nsh/defconfig b/configs/stm3220g-eval/nsh/defconfig index c3e02f4f66..0bf15bd471 100644 --- a/configs/stm3220g-eval/nsh/defconfig +++ b/configs/stm3220g-eval/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3220g-eval/nsh2/defconfig b/configs/stm3220g-eval/nsh2/defconfig index b7bbf116fc..756d46ec97 100644 --- a/configs/stm3220g-eval/nsh2/defconfig +++ b/configs/stm3220g-eval/nsh2/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3220g-eval/nxwm/defconfig b/configs/stm3220g-eval/nxwm/defconfig index bdd33e67b6..00be7789aa 100644 --- a/configs/stm3220g-eval/nxwm/defconfig +++ b/configs/stm3220g-eval/nxwm/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3220g-eval/telnetd/defconfig b/configs/stm3220g-eval/telnetd/defconfig index 5e7c56f25f..8087eefa4c 100644 --- a/configs/stm3220g-eval/telnetd/defconfig +++ b/configs/stm3220g-eval/telnetd/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3240g-eval/dhcpd/defconfig b/configs/stm3240g-eval/dhcpd/defconfig index 89f99ddd5b..e853770ca0 100644 --- a/configs/stm3240g-eval/dhcpd/defconfig +++ b/configs/stm3240g-eval/dhcpd/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3240g-eval/discover/defconfig b/configs/stm3240g-eval/discover/defconfig index f40268a76f..3173ed20d7 100644 --- a/configs/stm3240g-eval/discover/defconfig +++ b/configs/stm3240g-eval/discover/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3240g-eval/knxwm/defconfig b/configs/stm3240g-eval/knxwm/defconfig index e5c07319dc..c5d466cc75 100644 --- a/configs/stm3240g-eval/knxwm/defconfig +++ b/configs/stm3240g-eval/knxwm/defconfig @@ -85,7 +85,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3240g-eval/nettest/defconfig b/configs/stm3240g-eval/nettest/defconfig index ae30475a20..ee8324e9d5 100644 --- a/configs/stm3240g-eval/nettest/defconfig +++ b/configs/stm3240g-eval/nettest/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3240g-eval/nsh/defconfig b/configs/stm3240g-eval/nsh/defconfig index afc9d74ff1..0215da9426 100644 --- a/configs/stm3240g-eval/nsh/defconfig +++ b/configs/stm3240g-eval/nsh/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3240g-eval/nsh2/defconfig b/configs/stm3240g-eval/nsh2/defconfig index 9cb4875f38..47b77ad25e 100644 --- a/configs/stm3240g-eval/nsh2/defconfig +++ b/configs/stm3240g-eval/nsh2/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3240g-eval/nxterm/defconfig b/configs/stm3240g-eval/nxterm/defconfig index 9aed6dd720..c8fa345a86 100644 --- a/configs/stm3240g-eval/nxterm/defconfig +++ b/configs/stm3240g-eval/nxterm/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3240g-eval/nxwm/defconfig b/configs/stm3240g-eval/nxwm/defconfig index 63a4cf23a8..c1e7c78384 100644 --- a/configs/stm3240g-eval/nxwm/defconfig +++ b/configs/stm3240g-eval/nxwm/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3240g-eval/telnetd/defconfig b/configs/stm3240g-eval/telnetd/defconfig index cb4e4b091a..afccc0581a 100644 --- a/configs/stm3240g-eval/telnetd/defconfig +++ b/configs/stm3240g-eval/telnetd/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3240g-eval/webserver/defconfig b/configs/stm3240g-eval/webserver/defconfig index 17e05f9e57..fc5f38129e 100644 --- a/configs/stm3240g-eval/webserver/defconfig +++ b/configs/stm3240g-eval/webserver/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm3240g-eval/xmlrpc/defconfig b/configs/stm3240g-eval/xmlrpc/defconfig index b3db31d930..691149e1cd 100644 --- a/configs/stm3240g-eval/xmlrpc/defconfig +++ b/configs/stm3240g-eval/xmlrpc/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32_tiny/nsh/defconfig b/configs/stm32_tiny/nsh/defconfig index d1c78f0cbd..7c96533b6e 100644 --- a/configs/stm32_tiny/nsh/defconfig +++ b/configs/stm32_tiny/nsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32_tiny/usbnsh/defconfig b/configs/stm32_tiny/usbnsh/defconfig index 6f9342afa8..8a254501e2 100644 --- a/configs/stm32_tiny/usbnsh/defconfig +++ b/configs/stm32_tiny/usbnsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32butterfly2/nsh/defconfig b/configs/stm32butterfly2/nsh/defconfig index 56edadf664..c738c08de3 100644 --- a/configs/stm32butterfly2/nsh/defconfig +++ b/configs/stm32butterfly2/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32butterfly2/nshnet/defconfig b/configs/stm32butterfly2/nshnet/defconfig index b8249473b6..3804ac4ff0 100644 --- a/configs/stm32butterfly2/nshnet/defconfig +++ b/configs/stm32butterfly2/nshnet/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32butterfly2/nshusbdev/defconfig b/configs/stm32butterfly2/nshusbdev/defconfig index 01071e210d..2a27dfaed9 100644 --- a/configs/stm32butterfly2/nshusbdev/defconfig +++ b/configs/stm32butterfly2/nshusbdev/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32butterfly2/nshusbhost/defconfig b/configs/stm32butterfly2/nshusbhost/defconfig index 56edadf664..c738c08de3 100644 --- a/configs/stm32butterfly2/nshusbhost/defconfig +++ b/configs/stm32butterfly2/nshusbhost/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f103-minimum/audio_tone/defconfig b/configs/stm32f103-minimum/audio_tone/defconfig index 42f05f35f1..086dad19f5 100644 --- a/configs/stm32f103-minimum/audio_tone/defconfig +++ b/configs/stm32f103-minimum/audio_tone/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f103-minimum/buttons/defconfig b/configs/stm32f103-minimum/buttons/defconfig index d18846b909..e5fccea096 100644 --- a/configs/stm32f103-minimum/buttons/defconfig +++ b/configs/stm32f103-minimum/buttons/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f103-minimum/jlx12864g/defconfig b/configs/stm32f103-minimum/jlx12864g/defconfig index 7714aa1c45..09a91ef88d 100644 --- a/configs/stm32f103-minimum/jlx12864g/defconfig +++ b/configs/stm32f103-minimum/jlx12864g/defconfig @@ -111,7 +111,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f103-minimum/nsh/defconfig b/configs/stm32f103-minimum/nsh/defconfig index f66dd17b41..f2ce954678 100644 --- a/configs/stm32f103-minimum/nsh/defconfig +++ b/configs/stm32f103-minimum/nsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f103-minimum/pwm/defconfig b/configs/stm32f103-minimum/pwm/defconfig index 971e72ba34..021a9fcbd3 100644 --- a/configs/stm32f103-minimum/pwm/defconfig +++ b/configs/stm32f103-minimum/pwm/defconfig @@ -74,7 +74,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f103-minimum/rfid-rc522/defconfig b/configs/stm32f103-minimum/rfid-rc522/defconfig index d32c6b3008..03e471615c 100644 --- a/configs/stm32f103-minimum/rfid-rc522/defconfig +++ b/configs/stm32f103-minimum/rfid-rc522/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f103-minimum/rgbled/defconfig b/configs/stm32f103-minimum/rgbled/defconfig index 2fd2f2707a..f236ee1a63 100644 --- a/configs/stm32f103-minimum/rgbled/defconfig +++ b/configs/stm32f103-minimum/rgbled/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f103-minimum/usbnsh/defconfig b/configs/stm32f103-minimum/usbnsh/defconfig index 83ca39bb6c..6015311697 100644 --- a/configs/stm32f103-minimum/usbnsh/defconfig +++ b/configs/stm32f103-minimum/usbnsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f103-minimum/userled/defconfig b/configs/stm32f103-minimum/userled/defconfig index 02996a0ab5..fd0a0a857b 100644 --- a/configs/stm32f103-minimum/userled/defconfig +++ b/configs/stm32f103-minimum/userled/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f103-minimum/veml6070/defconfig b/configs/stm32f103-minimum/veml6070/defconfig index 3fd720b90f..7ef17b58be 100644 --- a/configs/stm32f103-minimum/veml6070/defconfig +++ b/configs/stm32f103-minimum/veml6070/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f3discovery/nsh/defconfig b/configs/stm32f3discovery/nsh/defconfig index e3495e5ddb..f0acc39483 100644 --- a/configs/stm32f3discovery/nsh/defconfig +++ b/configs/stm32f3discovery/nsh/defconfig @@ -77,7 +77,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f3discovery/usbnsh/defconfig b/configs/stm32f3discovery/usbnsh/defconfig index b7be381bdd..9da62c72fd 100644 --- a/configs/stm32f3discovery/usbnsh/defconfig +++ b/configs/stm32f3discovery/usbnsh/defconfig @@ -77,7 +77,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f411e-disco/nsh/defconfig b/configs/stm32f411e-disco/nsh/defconfig index fd0aea5e52..6124f39735 100644 --- a/configs/stm32f411e-disco/nsh/defconfig +++ b/configs/stm32f411e-disco/nsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f429i-disco/extflash/defconfig b/configs/stm32f429i-disco/extflash/defconfig index 916011dfe8..b1661bf394 100644 --- a/configs/stm32f429i-disco/extflash/defconfig +++ b/configs/stm32f429i-disco/extflash/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f429i-disco/lcd/defconfig b/configs/stm32f429i-disco/lcd/defconfig index 7f8194d36a..b799f6048d 100644 --- a/configs/stm32f429i-disco/lcd/defconfig +++ b/configs/stm32f429i-disco/lcd/defconfig @@ -77,7 +77,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f429i-disco/ltdc/defconfig b/configs/stm32f429i-disco/ltdc/defconfig index 1c0ccce8c7..2f398c0057 100644 --- a/configs/stm32f429i-disco/ltdc/defconfig +++ b/configs/stm32f429i-disco/ltdc/defconfig @@ -77,7 +77,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f429i-disco/nsh/defconfig b/configs/stm32f429i-disco/nsh/defconfig index b201f021ab..2d15d01d64 100644 --- a/configs/stm32f429i-disco/nsh/defconfig +++ b/configs/stm32f429i-disco/nsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f429i-disco/usbmsc/defconfig b/configs/stm32f429i-disco/usbmsc/defconfig index e67c0af126..6ef99c00e0 100644 --- a/configs/stm32f429i-disco/usbmsc/defconfig +++ b/configs/stm32f429i-disco/usbmsc/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f429i-disco/usbnsh/defconfig b/configs/stm32f429i-disco/usbnsh/defconfig index e7e805b97f..aa93f546d1 100644 --- a/configs/stm32f429i-disco/usbnsh/defconfig +++ b/configs/stm32f429i-disco/usbnsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f4discovery/canard/defconfig b/configs/stm32f4discovery/canard/defconfig index 092eb83b75..339029f3dc 100644 --- a/configs/stm32f4discovery/canard/defconfig +++ b/configs/stm32f4discovery/canard/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f4discovery/cxxtest/defconfig b/configs/stm32f4discovery/cxxtest/defconfig index 17aee26004..fe76de0ff3 100644 --- a/configs/stm32f4discovery/cxxtest/defconfig +++ b/configs/stm32f4discovery/cxxtest/defconfig @@ -77,7 +77,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f4discovery/elf/defconfig b/configs/stm32f4discovery/elf/defconfig index 267a0eb4c9..e2152eff65 100644 --- a/configs/stm32f4discovery/elf/defconfig +++ b/configs/stm32f4discovery/elf/defconfig @@ -77,7 +77,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f4discovery/ipv6/defconfig b/configs/stm32f4discovery/ipv6/defconfig index a0ba73ae9c..6b6a5021fd 100644 --- a/configs/stm32f4discovery/ipv6/defconfig +++ b/configs/stm32f4discovery/ipv6/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f4discovery/kostest/defconfig b/configs/stm32f4discovery/kostest/defconfig index f60c51af13..d0568bac6c 100644 --- a/configs/stm32f4discovery/kostest/defconfig +++ b/configs/stm32f4discovery/kostest/defconfig @@ -82,7 +82,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f4discovery/netnsh/defconfig b/configs/stm32f4discovery/netnsh/defconfig index 24acf42035..93c015c220 100644 --- a/configs/stm32f4discovery/netnsh/defconfig +++ b/configs/stm32f4discovery/netnsh/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f4discovery/nsh/defconfig b/configs/stm32f4discovery/nsh/defconfig index 8fde6da232..45b4d516bd 100644 --- a/configs/stm32f4discovery/nsh/defconfig +++ b/configs/stm32f4discovery/nsh/defconfig @@ -77,7 +77,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f4discovery/nxlines/defconfig b/configs/stm32f4discovery/nxlines/defconfig index 4dc4b3990d..6d0afb67cf 100644 --- a/configs/stm32f4discovery/nxlines/defconfig +++ b/configs/stm32f4discovery/nxlines/defconfig @@ -77,7 +77,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f4discovery/pm/defconfig b/configs/stm32f4discovery/pm/defconfig index b3d5cf6b47..23611818a5 100644 --- a/configs/stm32f4discovery/pm/defconfig +++ b/configs/stm32f4discovery/pm/defconfig @@ -77,7 +77,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f4discovery/posix_spawn/defconfig b/configs/stm32f4discovery/posix_spawn/defconfig index 8ec76f3264..0b50120eef 100644 --- a/configs/stm32f4discovery/posix_spawn/defconfig +++ b/configs/stm32f4discovery/posix_spawn/defconfig @@ -77,7 +77,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f4discovery/pseudoterm/defconfig b/configs/stm32f4discovery/pseudoterm/defconfig index bfbce2da4b..bf893357b4 100644 --- a/configs/stm32f4discovery/pseudoterm/defconfig +++ b/configs/stm32f4discovery/pseudoterm/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f4discovery/rgbled/defconfig b/configs/stm32f4discovery/rgbled/defconfig index 8aadf0ef48..cbdcd8a62b 100644 --- a/configs/stm32f4discovery/rgbled/defconfig +++ b/configs/stm32f4discovery/rgbled/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f4discovery/uavcan/defconfig b/configs/stm32f4discovery/uavcan/defconfig index e1c6805af2..6b16317813 100644 --- a/configs/stm32f4discovery/uavcan/defconfig +++ b/configs/stm32f4discovery/uavcan/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f4discovery/usbnsh/defconfig b/configs/stm32f4discovery/usbnsh/defconfig index 732aff799c..f526a52b11 100644 --- a/configs/stm32f4discovery/usbnsh/defconfig +++ b/configs/stm32f4discovery/usbnsh/defconfig @@ -77,7 +77,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f4discovery/winbuild/defconfig b/configs/stm32f4discovery/winbuild/defconfig index 579f659c5f..32a5be99c5 100644 --- a/configs/stm32f4discovery/winbuild/defconfig +++ b/configs/stm32f4discovery/winbuild/defconfig @@ -74,7 +74,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f4discovery/xen1210/defconfig b/configs/stm32f4discovery/xen1210/defconfig index cd07105569..be43bc8716 100644 --- a/configs/stm32f4discovery/xen1210/defconfig +++ b/configs/stm32f4discovery/xen1210/defconfig @@ -77,7 +77,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig index f49876c5c7..c8b5d79c69 100644 --- a/configs/stm32f746-ws/nsh/defconfig +++ b/configs/stm32f746-ws/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32f746g-disco/nsh/defconfig b/configs/stm32f746g-disco/nsh/defconfig index 2fbb7948a8..aaf5ad642b 100644 --- a/configs/stm32f746g-disco/nsh/defconfig +++ b/configs/stm32f746g-disco/nsh/defconfig @@ -77,7 +77,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32l476-mdk/nsh/defconfig b/configs/stm32l476-mdk/nsh/defconfig index 2d6b19fd7e..bff1aace3e 100644 --- a/configs/stm32l476-mdk/nsh/defconfig +++ b/configs/stm32l476-mdk/nsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32l476vg-disco/nsh/defconfig b/configs/stm32l476vg-disco/nsh/defconfig index 6a25d6e89b..a341d1ba39 100644 --- a/configs/stm32l476vg-disco/nsh/defconfig +++ b/configs/stm32l476vg-disco/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32ldiscovery/nsh/defconfig b/configs/stm32ldiscovery/nsh/defconfig index 5e6fd0b110..ad496c0a98 100644 --- a/configs/stm32ldiscovery/nsh/defconfig +++ b/configs/stm32ldiscovery/nsh/defconfig @@ -77,7 +77,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/stm32vldiscovery/nsh/defconfig b/configs/stm32vldiscovery/nsh/defconfig index 20b009d512..ef516541c4 100644 --- a/configs/stm32vldiscovery/nsh/defconfig +++ b/configs/stm32vldiscovery/nsh/defconfig @@ -77,7 +77,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/teensy-3.x/nsh/defconfig b/configs/teensy-3.x/nsh/defconfig index 5d53034bd9..2297c163a2 100644 --- a/configs/teensy-3.x/nsh/defconfig +++ b/configs/teensy-3.x/nsh/defconfig @@ -76,7 +76,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/teensy-3.x/usbnsh/defconfig b/configs/teensy-3.x/usbnsh/defconfig index 25bb2c87e6..55c2e4509b 100644 --- a/configs/teensy-3.x/usbnsh/defconfig +++ b/configs/teensy-3.x/usbnsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/teensy-lc/nsh/defconfig b/configs/teensy-lc/nsh/defconfig index e00646624c..0b235d0dee 100644 --- a/configs/teensy-lc/nsh/defconfig +++ b/configs/teensy-lc/nsh/defconfig @@ -73,7 +73,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/tm4c123g-launchpad/nsh/defconfig b/configs/tm4c123g-launchpad/nsh/defconfig index 0f871ed23f..6cbee2ee05 100644 --- a/configs/tm4c123g-launchpad/nsh/defconfig +++ b/configs/tm4c123g-launchpad/nsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/tm4c1294-launchpad/ipv6/defconfig b/configs/tm4c1294-launchpad/ipv6/defconfig index 0d05d6b4cb..075d74bce2 100644 --- a/configs/tm4c1294-launchpad/ipv6/defconfig +++ b/configs/tm4c1294-launchpad/ipv6/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/tm4c1294-launchpad/nsh/defconfig b/configs/tm4c1294-launchpad/nsh/defconfig index a4131c7391..d2efadd53b 100644 --- a/configs/tm4c1294-launchpad/nsh/defconfig +++ b/configs/tm4c1294-launchpad/nsh/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/twr-k60n512/nsh/defconfig b/configs/twr-k60n512/nsh/defconfig index 5bea922930..b6d1a57df0 100644 --- a/configs/twr-k60n512/nsh/defconfig +++ b/configs/twr-k60n512/nsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/u-blox-c027/nsh/defconfig b/configs/u-blox-c027/nsh/defconfig index 7e4713c0c9..022c5eec52 100644 --- a/configs/u-blox-c027/nsh/defconfig +++ b/configs/u-blox-c027/nsh/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/viewtool-stm32f107/highpri/defconfig b/configs/viewtool-stm32f107/highpri/defconfig index d05f74d688..fc3a34b4d9 100644 --- a/configs/viewtool-stm32f107/highpri/defconfig +++ b/configs/viewtool-stm32f107/highpri/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/viewtool-stm32f107/netnsh/defconfig b/configs/viewtool-stm32f107/netnsh/defconfig index 466b2d7009..5a0e0bb858 100644 --- a/configs/viewtool-stm32f107/netnsh/defconfig +++ b/configs/viewtool-stm32f107/netnsh/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/viewtool-stm32f107/nsh/defconfig b/configs/viewtool-stm32f107/nsh/defconfig index 2e08d6e3cf..138757c497 100644 --- a/configs/viewtool-stm32f107/nsh/defconfig +++ b/configs/viewtool-stm32f107/nsh/defconfig @@ -80,7 +80,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/zkit-arm-1769/hello/defconfig b/configs/zkit-arm-1769/hello/defconfig index b6b968fe33..dcda1f17fb 100644 --- a/configs/zkit-arm-1769/hello/defconfig +++ b/configs/zkit-arm-1769/hello/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/zkit-arm-1769/nsh/defconfig b/configs/zkit-arm-1769/nsh/defconfig index 19e8ebc26f..1d6cc991c1 100644 --- a/configs/zkit-arm-1769/nsh/defconfig +++ b/configs/zkit-arm-1769/nsh/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/zkit-arm-1769/nxhello/defconfig b/configs/zkit-arm-1769/nxhello/defconfig index 370e8d037c..e2aebc0fed 100644 --- a/configs/zkit-arm-1769/nxhello/defconfig +++ b/configs/zkit-arm-1769/nxhello/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/zkit-arm-1769/thttpd/defconfig b/configs/zkit-arm-1769/thttpd/defconfig index 026d759b45..d30a0e3270 100644 --- a/configs/zkit-arm-1769/thttpd/defconfig +++ b/configs/zkit-arm-1769/thttpd/defconfig @@ -75,7 +75,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/zp214xpa/nsh/defconfig b/configs/zp214xpa/nsh/defconfig index 14e69b3380..dcb8c7e000 100644 --- a/configs/zp214xpa/nsh/defconfig +++ b/configs/zp214xpa/nsh/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/configs/zp214xpa/nxlines/defconfig b/configs/zp214xpa/nxlines/defconfig index cfc2584b66..990185b651 100644 --- a/configs/zp214xpa/nxlines/defconfig +++ b/configs/zp214xpa/nxlines/defconfig @@ -72,7 +72,6 @@ CONFIG_ARCH="arm" # # CONFIG_ARCH_CHIP_A1X is not set # CONFIG_ARCH_CHIP_C5471 is not set -# CONFIG_ARCH_CHIP_CALYPSO is not set # CONFIG_ARCH_CHIP_DM320 is not set # CONFIG_ARCH_CHIP_EFM32 is not set # CONFIG_ARCH_CHIP_IMX1 is not set diff --git a/drivers/lcd/README.txt b/drivers/lcd/README.txt index 85d4f52d71..266a583654 100644 --- a/drivers/lcd/README.txt +++ b/drivers/lcd/README.txt @@ -162,10 +162,6 @@ that support additional LCDs. LCD drivers in the configuration directory if they support some differ LCD interface (such as a parallel interface) that makes then less re-usable: - SSD1783 Drivers: - - configs/compal_e99/src/ssd1783.c - SSD1289 Drivers: configs/hymini-stm32v/src/ssd1289.c. See also drivers/lcd/ssd1298.c -- GitLab From f063e4c5ac041b6edfb1ab07a25f0c3fe9531966 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 13 Dec 2016 18:35:52 -0600 Subject: [PATCH 687/734] Remove Calypso architecture support and support for Calypso SERCOMM driver. --- Documentation/NuttxPortingGuide.html | 6 - Documentation/README.html | 2 - README.txt | 2 - arch/README.txt | 1 - arch/arm/Kconfig | 14 - arch/arm/include/calypso/armio.h | 49 - arch/arm/include/calypso/clock.h | 67 -- arch/arm/include/calypso/debug.h | 31 - arch/arm/include/calypso/defines.h | 17 - arch/arm/include/calypso/irq.h | 81 -- arch/arm/include/calypso/memory.h | 28 - arch/arm/include/calypso/timer.h | 25 - arch/arm/include/calypso/uwire.h | 6 - arch/arm/src/calypso/Kconfig | 115 --- arch/arm/src/calypso/Make.defs | 71 -- arch/arm/src/calypso/calypso_armio.c | 103 -- arch/arm/src/calypso/calypso_head.S | 23 - arch/arm/src/calypso/calypso_heap.c | 101 -- arch/arm/src/calypso/calypso_irq.c | 357 ------- arch/arm/src/calypso/calypso_keypad.c | 385 ------- arch/arm/src/calypso/calypso_lowputc.S | 133 --- arch/arm/src/calypso/calypso_power.c | 50 - arch/arm/src/calypso/calypso_serial.c | 968 ------------------ arch/arm/src/calypso/calypso_spi.c | 314 ------ arch/arm/src/calypso/calypso_spi.h | 59 -- arch/arm/src/calypso/calypso_timer.c | 227 ---- arch/arm/src/calypso/calypso_uwire.c | 161 --- arch/arm/src/calypso/chip.h | 211 ---- arch/arm/src/calypso/clock.c | 230 ----- configs/amber/hello/defconfig | 1 - configs/arduino-due/nsh/defconfig | 1 - configs/arduino-mega2560/hello/defconfig | 1 - configs/arduino-mega2560/nsh/defconfig | 1 - configs/avr32dev1/nsh/defconfig | 1 - configs/avr32dev1/ostest/defconfig | 1 - configs/bambino-200e/nsh/defconfig | 1 - configs/c5471evm/httpd/defconfig | 1 - configs/c5471evm/nettest/defconfig | 1 - configs/c5471evm/nsh/defconfig | 1 - configs/cc3200-launchpad/nsh/defconfig | 1 - configs/cloudctrl/nsh/defconfig | 1 - configs/demo9s12ne64/ostest/defconfig | 1 - configs/dk-tm4c129x/ipv6/defconfig | 1 - configs/dk-tm4c129x/nsh/defconfig | 1 - configs/ea3131/nsh/defconfig | 1 - configs/ea3131/pgnsh/defconfig | 1 - configs/ea3131/usbserial/defconfig | 1 - configs/ea3152/ostest/defconfig | 1 - configs/eagle100/httpd/defconfig | 1 - configs/eagle100/nettest/defconfig | 1 - configs/eagle100/nsh/defconfig | 1 - configs/eagle100/nxflat/defconfig | 1 - configs/eagle100/thttpd/defconfig | 1 - configs/efm32-g8xx-stk/nsh/defconfig | 1 - configs/efm32gg-stk3700/nsh/defconfig | 1 - configs/ekk-lm3s9b96/nsh/defconfig | 1 - configs/esp32-core/nsh/defconfig | 1 - configs/esp32-core/smp/defconfig | 1 - configs/ez80f910200kitg/ostest/defconfig | 1 - configs/ez80f910200zco/dhcpd/defconfig | 1 - configs/ez80f910200zco/httpd/defconfig | 1 - configs/ez80f910200zco/nettest/defconfig | 1 - configs/ez80f910200zco/nsh/defconfig | 1 - configs/ez80f910200zco/poll/defconfig | 1 - configs/fire-stm32v2/nsh/defconfig | 1 - configs/freedom-k64f/netnsh/defconfig | 1 - configs/freedom-k64f/nsh/defconfig | 1 - configs/freedom-kl25z/nsh/defconfig | 1 - configs/freedom-kl26z/nsh/defconfig | 1 - configs/hymini-stm32v/nsh/defconfig | 1 - configs/hymini-stm32v/nsh2/defconfig | 1 - configs/hymini-stm32v/usbmsc/defconfig | 1 - configs/hymini-stm32v/usbnsh/defconfig | 1 - configs/hymini-stm32v/usbserial/defconfig | 1 - configs/kwikstik-k40/ostest/defconfig | 1 - configs/launchxl-tms57004/nsh/defconfig | 1 - configs/lincoln60/netnsh/defconfig | 1 - configs/lincoln60/nsh/defconfig | 1 - configs/lincoln60/thttpd-binfs/defconfig | 1 - configs/lm3s6432-s2e/nsh/defconfig | 1 - configs/lm3s6965-ek/discover/defconfig | 1 - configs/lm3s6965-ek/nsh/defconfig | 1 - configs/lm3s6965-ek/nx/defconfig | 1 - configs/lm3s6965-ek/tcpecho/defconfig | 1 - configs/lm3s8962-ek/nsh/defconfig | 1 - configs/lm3s8962-ek/nx/defconfig | 1 - configs/lm4f120-launchpad/nsh/defconfig | 1 - configs/lpc4330-xplorer/nsh/defconfig | 1 - configs/lpc4337-ws/nsh/defconfig | 1 - configs/lpc4357-evb/nsh/defconfig | 1 - configs/lpc4370-link2/nsh/defconfig | 1 - configs/lpcxpresso-lpc1115/nsh/defconfig | 1 - configs/lpcxpresso-lpc1768/dhcpd/defconfig | 1 - configs/lpcxpresso-lpc1768/nsh/defconfig | 1 - configs/lpcxpresso-lpc1768/nx/defconfig | 1 - configs/lpcxpresso-lpc1768/thttpd/defconfig | 1 - configs/lpcxpresso-lpc1768/usbmsc/defconfig | 1 - configs/maple/nsh/defconfig | 1 - configs/maple/nx/defconfig | 1 - configs/maple/usbnsh/defconfig | 1 - configs/mbed/hidkbd/defconfig | 1 - configs/mbed/nsh/defconfig | 1 - configs/mcu123-lpc214x/composite/defconfig | 1 - configs/mcu123-lpc214x/nsh/defconfig | 1 - configs/mcu123-lpc214x/usbmsc/defconfig | 1 - configs/mcu123-lpc214x/usbserial/defconfig | 1 - configs/micropendous3/hello/defconfig | 1 - configs/mikroe-stm32f4/fulldemo/defconfig | 1 - configs/mikroe-stm32f4/kostest/defconfig | 1 - configs/mikroe-stm32f4/nsh/defconfig | 1 - configs/mikroe-stm32f4/nx/defconfig | 1 - configs/mikroe-stm32f4/nxlines/defconfig | 1 - configs/mikroe-stm32f4/nxtext/defconfig | 1 - configs/mikroe-stm32f4/usbnsh/defconfig | 1 - configs/mirtoo/nsh/defconfig | 1 - configs/mirtoo/nxffs/defconfig | 1 - configs/misoc/hello/defconfig | 1 - configs/misoc/nsh/defconfig | 1 - configs/moteino-mega/hello/defconfig | 1 - configs/moteino-mega/nsh/defconfig | 1 - configs/moxa/nsh/defconfig | 1 - configs/mx1ads/ostest/defconfig | 1 - configs/ne64badge/ostest/defconfig | 1 - configs/nr5m100-nexys4/nsh/defconfig | 1 - configs/ntosd-dm320/nettest/defconfig | 1 - configs/ntosd-dm320/nsh/defconfig | 1 - configs/ntosd-dm320/poll/defconfig | 1 - configs/ntosd-dm320/thttpd/defconfig | 1 - configs/ntosd-dm320/udp/defconfig | 1 - configs/ntosd-dm320/webserver/defconfig | 1 - configs/nucleo-144/f746-evalos/defconfig | 1 - configs/nucleo-144/f746-nsh/defconfig | 1 - configs/nucleo-144/f767-evalos/defconfig | 1 - configs/nucleo-144/f767-nsh/defconfig | 1 - configs/nucleo-f303re/adc/defconfig | 1 - configs/nucleo-f303re/can/defconfig | 1 - configs/nucleo-f303re/hello/defconfig | 1 - configs/nucleo-f303re/nxlines/defconfig | 1 - configs/nucleo-f303re/pwm/defconfig | 1 - configs/nucleo-f303re/serialrx/defconfig | 1 - configs/nucleo-f303re/uavcan/defconfig | 1 - configs/nucleo-f4x1re/f401-nsh/defconfig | 1 - configs/nucleo-f4x1re/f411-nsh/defconfig | 1 - configs/nucleo-l476rg/nsh/defconfig | 1 - configs/nutiny-nuc120/nsh/defconfig | 1 - .../olimex-efm32g880f128-stk/nsh/defconfig | 1 - configs/olimex-lpc-h3131/nsh/defconfig | 1 - configs/olimex-lpc1766stk/ftpc/defconfig | 1 - configs/olimex-lpc1766stk/hidkbd/defconfig | 1 - configs/olimex-lpc1766stk/hidmouse/defconfig | 1 - configs/olimex-lpc1766stk/nettest/defconfig | 1 - configs/olimex-lpc1766stk/nsh/defconfig | 1 - configs/olimex-lpc1766stk/nx/defconfig | 1 - .../olimex-lpc1766stk/slip-httpd/defconfig | 1 - .../olimex-lpc1766stk/thttpd-binfs/defconfig | 1 - .../olimex-lpc1766stk/thttpd-nxflat/defconfig | 1 - configs/olimex-lpc1766stk/usbmsc/defconfig | 1 - configs/olimex-lpc1766stk/usbserial/defconfig | 1 - configs/olimex-lpc1766stk/zmodem/defconfig | 1 - configs/olimex-lpc2378/nsh/defconfig | 1 - configs/olimex-stm32-e407/discover/defconfig | 1 - configs/olimex-stm32-e407/netnsh/defconfig | 1 - configs/olimex-stm32-e407/nsh/defconfig | 1 - configs/olimex-stm32-e407/telnetd/defconfig | 1 - configs/olimex-stm32-e407/usbnsh/defconfig | 1 - configs/olimex-stm32-e407/webserver/defconfig | 1 - configs/olimex-stm32-h405/usbnsh/defconfig | 1 - configs/olimex-stm32-h407/nsh/defconfig | 1 - configs/olimex-stm32-p107/nsh/defconfig | 1 - configs/olimex-stm32-p207/nsh/defconfig | 1 - configs/olimex-strp711/nettest/defconfig | 1 - configs/olimex-strp711/nsh/defconfig | 1 - configs/olimexino-stm32/can/defconfig | 1 - configs/olimexino-stm32/composite/defconfig | 1 - configs/olimexino-stm32/nsh/defconfig | 1 - configs/olimexino-stm32/smallnsh/defconfig | 1 - configs/olimexino-stm32/tiny/defconfig | 1 - configs/open1788/knsh/defconfig | 1 - configs/open1788/nsh/defconfig | 1 - configs/open1788/nxlines/defconfig | 1 - configs/p112/ostest/defconfig | 1 - configs/pcblogic-pic32mx/nsh/defconfig | 1 - configs/pcduino-a10/nsh/defconfig | 1 - configs/pic32mx-starterkit/nsh/defconfig | 1 - configs/pic32mx-starterkit/nsh2/defconfig | 1 - configs/pic32mx7mmb/nsh/defconfig | 1 - configs/pic32mz-starterkit/nsh/defconfig | 1 - configs/qemu-i486/nsh/defconfig | 1 - configs/qemu-i486/ostest/defconfig | 1 - configs/sabre-6quad/nsh/defconfig | 1 - configs/sabre-6quad/smp/defconfig | 1 - configs/sam3u-ek/knsh/defconfig | 1 - configs/sam3u-ek/nsh/defconfig | 1 - configs/sam3u-ek/nx/defconfig | 1 - configs/sam3u-ek/nxwm/defconfig | 1 - configs/sam4cmp-db/nsh/defconfig | 1 - configs/sam4e-ek/nsh/defconfig | 1 - configs/sam4e-ek/nxwm/defconfig | 1 - configs/sam4e-ek/usbnsh/defconfig | 1 - configs/sam4l-xplained/nsh/defconfig | 1 - configs/sam4s-xplained-pro/nsh/defconfig | 1 - configs/sam4s-xplained/nsh/defconfig | 1 - configs/sama5d2-xult/nsh/defconfig | 1 - configs/sama5d3-xplained/bridge/defconfig | 1 - configs/sama5d3-xplained/nsh/defconfig | 1 - configs/sama5d3x-ek/demo/defconfig | 1 - configs/sama5d3x-ek/hello/defconfig | 1 - configs/sama5d3x-ek/norboot/defconfig | 1 - configs/sama5d3x-ek/nsh/defconfig | 1 - configs/sama5d3x-ek/nx/defconfig | 1 - configs/sama5d3x-ek/nxplayer/defconfig | 1 - configs/sama5d3x-ek/nxwm/defconfig | 1 - configs/sama5d3x-ek/ov2640/defconfig | 1 - configs/sama5d4-ek/at25boot/defconfig | 1 - configs/sama5d4-ek/bridge/defconfig | 1 - configs/sama5d4-ek/dramboot/defconfig | 1 - configs/sama5d4-ek/elf/defconfig | 1 - configs/sama5d4-ek/ipv6/defconfig | 1 - configs/sama5d4-ek/knsh/defconfig | 1 - configs/sama5d4-ek/knsh/defconfig.ROMFS | 1 - configs/sama5d4-ek/nsh/defconfig | 1 - configs/sama5d4-ek/nxwm/defconfig | 1 - configs/sama5d4-ek/ramtest/defconfig | 1 - configs/samd20-xplained/nsh/defconfig | 1 - configs/samd21-xplained/nsh/defconfig | 1 - configs/same70-xplained/netnsh/defconfig | 1 - configs/same70-xplained/nsh/defconfig | 1 - configs/saml21-xplained/nsh/defconfig | 1 - configs/samv71-xult/knsh/defconfig | 1 - configs/samv71-xult/module/defconfig | 1 - configs/samv71-xult/mxtxplnd/defconfig | 1 - configs/samv71-xult/netnsh/defconfig | 1 - configs/samv71-xult/nsh/defconfig | 1 - configs/samv71-xult/nxwm/defconfig | 1 - configs/samv71-xult/vnc/defconfig | 1 - configs/samv71-xult/vnxwm/defconfig | 1 - configs/shenzhou/nsh/defconfig | 1 - configs/shenzhou/nxwm/defconfig | 1 - configs/shenzhou/thttpd/defconfig | 1 - configs/sim/bas/defconfig | 1 - configs/sim/configdata/defconfig | 1 - configs/sim/cxxtest/defconfig | 1 - configs/sim/minibasic/defconfig | 1 - configs/sim/mount/defconfig | 1 - configs/sim/mtdpart/defconfig | 1 - configs/sim/mtdrwb/defconfig | 1 - configs/sim/nettest/defconfig | 1 - configs/sim/nsh/defconfig | 1 - configs/sim/nsh2/defconfig | 1 - configs/sim/nx/defconfig | 1 - configs/sim/nx11/defconfig | 1 - configs/sim/nxffs/defconfig | 1 - configs/sim/nxlines/defconfig | 1 - configs/sim/nxwm/defconfig | 1 - configs/sim/ostest/defconfig | 1 - configs/sim/pashello/defconfig | 1 - configs/sim/touchscreen/defconfig | 1 - configs/sim/traveler/defconfig | 1 - configs/sim/udgram/defconfig | 1 - configs/sim/unionfs/defconfig | 1 - configs/sim/ustream/defconfig | 1 - configs/skp16c26/ostest/defconfig | 1 - configs/spark/composite/defconfig | 1 - configs/spark/nsh/defconfig | 1 - configs/spark/usbmsc/defconfig | 1 - configs/spark/usbnsh/defconfig | 1 - configs/spark/usbserial/defconfig | 1 - configs/stm3210e-eval/composite/defconfig | 1 - configs/stm3210e-eval/nsh/defconfig | 1 - configs/stm3210e-eval/nsh2/defconfig | 1 - configs/stm3210e-eval/nx/defconfig | 1 - configs/stm3210e-eval/nxterm/defconfig | 1 - configs/stm3210e-eval/pm/defconfig | 1 - configs/stm3210e-eval/usbmsc/defconfig | 1 - configs/stm3210e-eval/usbserial/defconfig | 1 - configs/stm3220g-eval/dhcpd/defconfig | 1 - configs/stm3220g-eval/nettest/defconfig | 1 - configs/stm3220g-eval/nsh/defconfig | 1 - configs/stm3220g-eval/nsh2/defconfig | 1 - configs/stm3220g-eval/nxwm/defconfig | 1 - configs/stm3220g-eval/telnetd/defconfig | 1 - configs/stm3240g-eval/dhcpd/defconfig | 1 - configs/stm3240g-eval/discover/defconfig | 1 - configs/stm3240g-eval/knxwm/defconfig | 1 - configs/stm3240g-eval/nettest/defconfig | 1 - configs/stm3240g-eval/nsh/defconfig | 1 - configs/stm3240g-eval/nsh2/defconfig | 1 - configs/stm3240g-eval/nxterm/defconfig | 1 - configs/stm3240g-eval/nxwm/defconfig | 1 - configs/stm3240g-eval/telnetd/defconfig | 1 - configs/stm3240g-eval/webserver/defconfig | 1 - configs/stm3240g-eval/xmlrpc/defconfig | 1 - configs/stm32_tiny/nsh/defconfig | 1 - configs/stm32_tiny/usbnsh/defconfig | 1 - configs/stm32butterfly2/nsh/defconfig | 1 - configs/stm32butterfly2/nshnet/defconfig | 1 - configs/stm32butterfly2/nshusbdev/defconfig | 1 - configs/stm32butterfly2/nshusbhost/defconfig | 1 - .../stm32f103-minimum/audio_tone/defconfig | 1 - configs/stm32f103-minimum/buttons/defconfig | 1 - configs/stm32f103-minimum/jlx12864g/defconfig | 1 - configs/stm32f103-minimum/nsh/defconfig | 1 - configs/stm32f103-minimum/pwm/defconfig | 1 - .../stm32f103-minimum/rfid-rc522/defconfig | 1 - configs/stm32f103-minimum/rgbled/defconfig | 1 - configs/stm32f103-minimum/usbnsh/defconfig | 1 - configs/stm32f103-minimum/userled/defconfig | 1 - configs/stm32f103-minimum/veml6070/defconfig | 1 - configs/stm32f3discovery/nsh/defconfig | 1 - configs/stm32f3discovery/usbnsh/defconfig | 1 - configs/stm32f411e-disco/nsh/defconfig | 1 - configs/stm32f429i-disco/extflash/defconfig | 1 - configs/stm32f429i-disco/lcd/defconfig | 1 - configs/stm32f429i-disco/ltdc/defconfig | 1 - configs/stm32f429i-disco/nsh/defconfig | 1 - configs/stm32f429i-disco/usbmsc/defconfig | 1 - configs/stm32f429i-disco/usbnsh/defconfig | 1 - configs/stm32f4discovery/canard/defconfig | 1 - configs/stm32f4discovery/cxxtest/defconfig | 1 - configs/stm32f4discovery/elf/defconfig | 1 - configs/stm32f4discovery/ipv6/defconfig | 1 - configs/stm32f4discovery/kostest/defconfig | 1 - configs/stm32f4discovery/netnsh/defconfig | 1 - configs/stm32f4discovery/nsh/defconfig | 1 - configs/stm32f4discovery/nxlines/defconfig | 1 - configs/stm32f4discovery/pm/defconfig | 1 - .../stm32f4discovery/posix_spawn/defconfig | 1 - configs/stm32f4discovery/pseudoterm/defconfig | 1 - configs/stm32f4discovery/rgbled/defconfig | 1 - configs/stm32f4discovery/uavcan/defconfig | 1 - configs/stm32f4discovery/usbnsh/defconfig | 1 - configs/stm32f4discovery/winbuild/defconfig | 1 - configs/stm32f4discovery/xen1210/defconfig | 1 - configs/stm32f746-ws/nsh/defconfig | 1 - configs/stm32f746g-disco/nsh/defconfig | 1 - configs/stm32l476-mdk/nsh/defconfig | 1 - configs/stm32l476vg-disco/nsh/defconfig | 1 - configs/stm32ldiscovery/nsh/defconfig | 1 - configs/stm32vldiscovery/nsh/defconfig | 1 - configs/sure-pic32mx/nsh/defconfig | 1 - configs/sure-pic32mx/usbnsh/defconfig | 1 - configs/teensy-2.0/hello/defconfig | 1 - configs/teensy-2.0/nsh/defconfig | 1 - configs/teensy-2.0/usbmsc/defconfig | 1 - configs/teensy-3.x/nsh/defconfig | 1 - configs/teensy-3.x/usbnsh/defconfig | 1 - configs/teensy-lc/nsh/defconfig | 1 - configs/tm4c123g-launchpad/nsh/defconfig | 1 - configs/tm4c1294-launchpad/ipv6/defconfig | 1 - configs/tm4c1294-launchpad/nsh/defconfig | 1 - configs/twr-k60n512/nsh/defconfig | 1 - configs/u-blox-c027/nsh/defconfig | 1 - configs/ubw32/nsh/defconfig | 1 - configs/us7032evb1/nsh/defconfig | 1 - configs/us7032evb1/ostest/defconfig | 1 - configs/viewtool-stm32f107/highpri/defconfig | 1 - configs/viewtool-stm32f107/netnsh/defconfig | 1 - configs/viewtool-stm32f107/nsh/defconfig | 1 - configs/xtrs/nsh/defconfig | 1 - configs/xtrs/ostest/defconfig | 1 - configs/xtrs/pashello/defconfig | 1 - configs/z16f2800100zcog/nsh/defconfig | 1 - configs/z16f2800100zcog/ostest/defconfig | 1 - configs/z16f2800100zcog/pashello/defconfig | 1 - configs/z80sim/nsh/defconfig | 1 - configs/z80sim/ostest/defconfig | 1 - configs/z80sim/pashello/defconfig | 1 - configs/z8encore000zco/ostest/defconfig | 1 - configs/z8f64200100kit/ostest/defconfig | 1 - configs/zkit-arm-1769/hello/defconfig | 1 - configs/zkit-arm-1769/nsh/defconfig | 1 - configs/zkit-arm-1769/nxhello/defconfig | 1 - configs/zkit-arm-1769/thttpd/defconfig | 1 - configs/zp214xpa/nsh/defconfig | 1 - configs/zp214xpa/nxlines/defconfig | 1 - drivers/Kconfig | 17 - drivers/Makefile | 1 - drivers/README.txt | 10 - drivers/sercomm/Kconfig | 4 - drivers/sercomm/Make.defs | 55 - drivers/sercomm/README.txt | 19 - drivers/sercomm/console.c | 216 ---- drivers/sercomm/loadwriter.py | 19 - drivers/sercomm/uart.c | 607 ----------- drivers/sercomm/uart.h | 32 - include/nuttx/sercomm/msgb.h | 218 ---- include/nuttx/sercomm/sercomm.h | 57 -- include/nuttx/sercomm/sercomm_cons.h | 10 - 388 files changed, 5448 deletions(-) delete mode 100644 arch/arm/include/calypso/armio.h delete mode 100644 arch/arm/include/calypso/clock.h delete mode 100644 arch/arm/include/calypso/debug.h delete mode 100644 arch/arm/include/calypso/defines.h delete mode 100644 arch/arm/include/calypso/irq.h delete mode 100644 arch/arm/include/calypso/memory.h delete mode 100644 arch/arm/include/calypso/timer.h delete mode 100644 arch/arm/include/calypso/uwire.h delete mode 100644 arch/arm/src/calypso/Kconfig delete mode 100644 arch/arm/src/calypso/Make.defs delete mode 100644 arch/arm/src/calypso/calypso_armio.c delete mode 100644 arch/arm/src/calypso/calypso_head.S delete mode 100644 arch/arm/src/calypso/calypso_heap.c delete mode 100644 arch/arm/src/calypso/calypso_irq.c delete mode 100644 arch/arm/src/calypso/calypso_keypad.c delete mode 100644 arch/arm/src/calypso/calypso_lowputc.S delete mode 100644 arch/arm/src/calypso/calypso_power.c delete mode 100644 arch/arm/src/calypso/calypso_serial.c delete mode 100644 arch/arm/src/calypso/calypso_spi.c delete mode 100644 arch/arm/src/calypso/calypso_spi.h delete mode 100644 arch/arm/src/calypso/calypso_timer.c delete mode 100644 arch/arm/src/calypso/calypso_uwire.c delete mode 100644 arch/arm/src/calypso/chip.h delete mode 100644 arch/arm/src/calypso/clock.c delete mode 100644 drivers/sercomm/Kconfig delete mode 100644 drivers/sercomm/Make.defs delete mode 100644 drivers/sercomm/README.txt delete mode 100644 drivers/sercomm/console.c delete mode 100755 drivers/sercomm/loadwriter.py delete mode 100644 drivers/sercomm/uart.c delete mode 100644 drivers/sercomm/uart.h delete mode 100644 include/nuttx/sercomm/msgb.h delete mode 100644 include/nuttx/sercomm/sercomm.h delete mode 100644 include/nuttx/sercomm/sercomm_cons.h diff --git a/Documentation/NuttxPortingGuide.html b/Documentation/NuttxPortingGuide.html index 8ecbf7abc7..f1007f4992 100644 --- a/Documentation/NuttxPortingGuide.html +++ b/Documentation/NuttxPortingGuide.html @@ -1008,10 +1008,6 @@ drivers/ | |-- Kconfig | |-- Make.defs | `-- (Common sensor driver source files) -|-- sercomm/ -| |-- Kconfig -| |-- Make.defs -| `-- (Files for the Calypso SERCOMM driver) |-- serial/ | |-- Kconfig | |-- Make.defs @@ -1170,8 +1166,6 @@ include/ | | `-- (Power management header files) | |-sensors/ | | `-- (Sensor device driver header files) -| |-sercomm/ -| | `-- (SERCOMM driver header files) | |-serial/ | | `-- (Serial driver header files) | |-spi/ diff --git a/Documentation/README.html b/Documentation/README.html index 6e0d32528e..b7d8330c10 100644 --- a/Documentation/README.html +++ b/Documentation/README.html @@ -320,8 +320,6 @@ nuttx/ | | `- README.txt | |- sensors/ | | `- README.txt - | |- sercomm/ - | | `- README.txt | |- syslog/ | | `- README.txt | `- README.txt diff --git a/README.txt b/README.txt index f09c6dff96..4ea0c51437 100644 --- a/README.txt +++ b/README.txt @@ -1536,8 +1536,6 @@ nuttx/ | | `- README.txt | |- sensors/ | | `- README.txt - | |- sercomm/ - | | `- README.txt | |- syslog/ | | `- README.txt | `- README.txt diff --git a/arch/README.txt b/arch/README.txt index 2e52e95ff0..a0f604e4af 100644 --- a/arch/README.txt +++ b/arch/README.txt @@ -158,7 +158,6 @@ arch/arm - ARM-based micro-controllers MCU support arch/arm/include/a1x and arch/arm/src/a1x arch/arm/include/c5471 and arch/arm/src/c5471 - arch/arm/include/calypso and arch/arm/src/calypso arch/arm/include/dm320 and arch/arm/src/dm320 arch/arm/include/efm32 and arch/arm/src/efm32 arch/arm/include/imx1 and arch/arm/src/imx1 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9b721e2a3e..d56e0a861e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -31,16 +31,6 @@ config ARCH_CHIP_C5471 ---help--- TI TMS320 C5471, A180, or DA180 (ARM7TDMI) -config ARCH_CHIP_CALYPSO - bool "Calypso" - select ARCH_ARM7TDMI - select ARCH_HAVE_HEAP2 - select ARCH_HAVE_LOWVECTORS - select OTHER_UART_SERIALDRIVER - select ARCH_HAVE_POWEROFF - ---help--- - TI Calypso-based cell phones (ARM7TDMI) - config ARCH_CHIP_DM320 bool "TMS320 DM320" select ARCH_ARM926EJS @@ -409,7 +399,6 @@ config ARCH_CHIP string default "a1x" if ARCH_CHIP_A1X default "c5471" if ARCH_CHIP_C5471 - default "calypso" if ARCH_CHIP_CALYPSO default "dm320" if ARCH_CHIP_DM320 default "efm32" if ARCH_CHIP_EFM32 default "imx1" if ARCH_CHIP_IMX1 @@ -625,9 +614,6 @@ endif if ARCH_CHIP_C5471 source arch/arm/src/c5471/Kconfig endif -if ARCH_CHIP_CALYPSO -source arch/arm/src/calypso/Kconfig -endif if ARCH_CHIP_DM320 source arch/arm/src/dm320/Kconfig endif diff --git a/arch/arm/include/calypso/armio.h b/arch/arm/include/calypso/armio.h deleted file mode 100644 index 2f232beb22..0000000000 --- a/arch/arm/include/calypso/armio.h +++ /dev/null @@ -1,49 +0,0 @@ -/**************************************************************************** - * Driver for Calypso ARMIO - * - * Copyright (C) 2011 Stefan Richter. All rights reserved. - * Author: Stefan Richter - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Prototypes for interrupt handling - ****************************************************************************/ - -inline int calypso_kbd_irq(int irq, uint32_t *regs); - -/**************************************************************************** - * Initialize device, add /dev/... nodes - ****************************************************************************/ - -void calypso_armio(void); diff --git a/arch/arm/include/calypso/clock.h b/arch/arm/include/calypso/clock.h deleted file mode 100644 index a10a607a5d..0000000000 --- a/arch/arm/include/calypso/clock.h +++ /dev/null @@ -1,67 +0,0 @@ -#ifndef __ARCH_ARM_INCLUDE_CALYPSO_CLOCK_H -#define __ARCH_ARM_INCLUDE_CALYPSO_CLOCK_H - -#include - -#define CALYPSO_PLL26_52_MHZ ((2 << 8) | 0) -#define CALYPSO_PLL26_86_7_MHZ ((10 << 8) | 2) -#define CALYPSO_PLL26_87_MHZ ((3 << 8) | 0) -#define CALYPSO_PLL13_104_MHZ ((8 << 8) | 0) - -enum mclk_div { - _ARM_MCLK_DIV_1 = 0, - ARM_MCLK_DIV_1 = 1, - ARM_MCLK_DIV_2 = 2, - ARM_MCLK_DIV_3 = 3, - ARM_MCLK_DIV_4 = 4, - ARM_MCLK_DIV_5 = 5, - ARM_MCLK_DIV_6 = 6, - ARM_MCLK_DIV_7 = 7, - ARM_MCLK_DIV_1_5 = 0x80 | 1, - ARM_MCLK_DIV_2_5 = 0x80 | 2, -}; - -void calypso_clock_set(uint8_t vtcxo_div2, uint16_t inp, enum mclk_div mclk_div); -void calypso_pll_set(uint16_t inp); -void calypso_clk_dump(void); - -/* CNTL_RST */ -enum calypso_rst { - RESET_DSP = (1 << 1), - RESET_EXT = (1 << 2), - RESET_WDOG = (1 << 3), -}; - -void calypso_reset_set(enum calypso_rst calypso_rst, int active); -int calypso_reset_get(enum calypso_rst); - -enum calypso_bank { - CALYPSO_nCS0 = 0, - CALYPSO_nCS1 = 2, - CALYPSO_nCS2 = 4, - CALYPSO_nCS3 = 6, - CALYPSO_nCS7 = 8, - CALYPSO_CS4 = 0xa, - CALYPSO_nCS6 = 0xc, -}; - -enum calypso_mem_width { - CALYPSO_MEM_8bit = 0, - CALYPSO_MEM_16bit = 1, - CALYPSO_MEM_32bit = 2, -}; - -void calypso_mem_cfg(enum calypso_bank bank, uint8_t ws, - enum calypso_mem_width width, int we); - -/* Enable or disable the internal bootrom mapped to 0x0000'0000 */ -void calypso_bootrom(int enable); - -/* Enable or disable the debug unit */ -void calypso_debugunit(int enable); - -/* configure the RHEA bus bridge[s] */ -void calypso_rhea_cfg(uint8_t fac0, uint8_t fac1, uint8_t timeout, - uint8_t ws_h, uint8_t ws_l, uint8_t w_en0, uint8_t w_en1); - -#endif /* __ARCH_ARM_INCLUDE_CALYPSO_CLOCK_H */ diff --git a/arch/arm/include/calypso/debug.h b/arch/arm/include/calypso/debug.h deleted file mode 100644 index 9596946775..0000000000 --- a/arch/arm/include/calypso/debug.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef __ARCH_ARM_INCLUDE_CALYPSO_DEBUG_H -#define __ARCH_ARM_INCLUDE_CALYPSO_DEBUG_H - -#ifndef ARRAY_SIZE -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) -#endif - -/* - * Check at compile time that something is of a particular type. - * Always evaluates to 1 so you may use it easily in comparisons. - */ -#define typecheck(type,x) \ -({ type __dummy; \ - typeof(x) __dummy2; \ - (void)(&__dummy == &__dummy2); \ - 1; \ -}) - -#ifdef DEBUG -#define dputchar(x) putchar(x) -#define dputs(x) puts(x) -#define dphex(x,y) phex(x,y) -#define printd(x, ...) printf(x, ##__VA_ARGS__) -#else -#define dputchar(x) -#define dputs(x) -#define dphex(x,y) -#define printd(x, args ...) -#endif - -#endif /* __ARCH_ARM_INCLUDE_CALYPSO_DEBUG_H */ diff --git a/arch/arm/include/calypso/defines.h b/arch/arm/include/calypso/defines.h deleted file mode 100644 index 4f29560c83..0000000000 --- a/arch/arm/include/calypso/defines.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef __ARCH_ARM_INCLUDE_CALYPSO_DEFINES_H -#define __ARCH_ARM_INCLUDE_CALYPSO_DEFINES_H - -#define __attribute_const__ __attribute__((__const__)) - -/* type properties */ -#define __packed __attribute__((packed)) -#define __aligned(alignment) __attribute__((aligned(alignment))) -#define __unused __attribute__((unused)) - -/* linkage */ -#define __section(name) __attribute__((section(name))) - -/* force placement in zero-waitstate memory */ -#define __ramtext __section(".ramtext") - -#endif /* !__ARCH_ARM_INCLUDE_CALYPSO_DEFINES_H */ diff --git a/arch/arm/include/calypso/irq.h b/arch/arm/include/calypso/irq.h deleted file mode 100644 index 0dda3f312f..0000000000 --- a/arch/arm/include/calypso/irq.h +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** - * arch/arm/include/calypso/irq.h - * Driver for Calypso IRQ controller - * - * (C) 2010 by Harald Welte - * (C) 2011 by Stefan Richter - * - * This source code is derivated from Osmocom-BB project and was - * relicensed as BSD with permission from original authors. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __INCLUDE_NUTTX_IRQ_H -#error "This file should never be included directly! Use " -#endif - -#ifndef __ARCH_ARM_INCLUDE_CALYPSO_IRQ_H -#define __ARCH_ARM_INCLUDE_CALYPSO_IRQ_H - -#ifndef __ASSEMBLY__ - -enum irq_nr { - IRQ_WATCHDOG = 0, - IRQ_TIMER1 = 1, - IRQ_TIMER2 = 2, - IRQ_TSP_RX = 3, - IRQ_TPU_FRAME = 4, - IRQ_TPU_PAGE = 5, - IRQ_SIMCARD = 6, - IRQ_UART_MODEM = 7, - IRQ_KEYPAD_GPIO = 8, - IRQ_RTC_TIMER = 9, - IRQ_RTC_ALARM_I2C = 10, - IRQ_ULPD_GAUGING = 11, - IRQ_EXTERNAL = 12, - IRQ_SPI = 13, - IRQ_DMA = 14, - IRQ_API = 15, - IRQ_SIM_DETECT = 16, - IRQ_EXTERNAL_FIQ = 17, - IRQ_UART_IRDA = 18, - IRQ_ULPD_GSM_TIMER = 19, - IRQ_GEA = 20, - _NR_IRQS -}; - -#endif /* __ASSEMBLY__ */ - -/* Don't use _NR_IRQS!!! Won't work in preprocessor... */ -#define NR_IRQS 21 - -#define IRQ_SYSTIMER IRQ_TIMER2 - -#endif /* __ARCH_ARM_INCLUDE_CALYPSO_IRQ_H */ diff --git a/arch/arm/include/calypso/memory.h b/arch/arm/include/calypso/memory.h deleted file mode 100644 index a4ce1e890e..0000000000 --- a/arch/arm/include/calypso/memory.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef __ARCH_ARM_INCLUDE_CALYPSO_MEMORY_H -#define __ARCH_ARM_INCLUDE_CALYPSO_MEMORY_H - -#define __arch_getb(a) (*(volatile unsigned char *)(a)) -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_getl(a) (*(volatile unsigned int *)(a)) - -#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) - -#define __raw_writeb(v,a) __arch_putb(v,a) -#define __raw_writew(v,a) __arch_putw(v,a) -#define __raw_writel(v,a) __arch_putl(v,a) - -#define __raw_readb(a) __arch_getb(a) -#define __raw_readw(a) __arch_getw(a) -#define __raw_readl(a) __arch_getl(a) - -#define writeb(v,a) __arch_putb(v,a) -#define writew(v,a) __arch_putw(v,a) -#define writel(v,a) __arch_putl(v,a) - -#define readb(a) __arch_getb(a) -#define readw(a) __arch_getw(a) -#define readl(a) __arch_getl(a) - -#endif /* __ARCH_ARM_INCLUDE_CALYPSO_MEMORY_H */ diff --git a/arch/arm/include/calypso/timer.h b/arch/arm/include/calypso/timer.h deleted file mode 100644 index 93a1bd1492..0000000000 --- a/arch/arm/include/calypso/timer.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef __ARCH_ARM_INCLUDE_CALYPSO_TIMER_H -#define __ARCH_ARM_INCLUDE_CALYPSO_TIMER_H - -/* Enable or Disable a timer */ -void hwtimer_enable(int num, int on); - -/* Configure pre-scaler and if timer is auto-reload */ -void hwtimer_config(int num, uint8_t pre_scale, int auto_reload); - -/* Load a timer with the given value */ -void hwtimer_load(int num, uint16_t val); - -/* Read the current timer value */ -uint16_t hwtimer_read(int num); - -/* Enable or disable the watchdog */ -void wdog_enable(int on); - -/* Reset cpu using watchdog */ -void wdog_reset(void); - -/* power up the timers */ -void hwtimer_init(void); - -#endif /* __ARCH_ARM_INCLUDE_CALYPSO_TIMER_H */ diff --git a/arch/arm/include/calypso/uwire.h b/arch/arm/include/calypso/uwire.h deleted file mode 100644 index 0ca6c376ca..0000000000 --- a/arch/arm/include/calypso/uwire.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ARCH_ARM_INCLUDE_CALYPSO_UWIRE_H -#define __ARCH_ARM_INCLUDE_CALYPSO_UWIRE_H -void uwire_init(void); -int uwire_xfer(int cs, int bitlen, const void *dout, void *din); -#endif - diff --git a/arch/arm/src/calypso/Kconfig b/arch/arm/src/calypso/Kconfig deleted file mode 100644 index e044280f62..0000000000 --- a/arch/arm/src/calypso/Kconfig +++ /dev/null @@ -1,115 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -comment "Calypso Configuration Options" - -menu "Modem UART Configuration" - -config UART_MODEM_BAUD - int "Modem UART BAUD" - default 115200 - -config UART_MODEM_PARITY - int "Modem UART parity" - default 0 - ---help--- - Modem UART parity. 0=None, 1=Odd, 2=Even. Default: None - -config UART_MODEM_BITS - int "Modem UART number of bits" - default 8 - ---help--- - Modem UART number of bits. Default: 8 - -config UART_MODEM_2STOP - int "Modem UART two stop bits" - default 0 - ---help--- - 0=1 stop bit, 1=Two stop bits. Default: 1 stop bit - -config UART_MODEM_RXBUFSIZE - int "Modem UART Rx buffer size" - default 256 - ---help--- - Modem UART Rx buffer size. Default: 256 - -config UART_MODEM_TXBUFSIZE - int "Modem UART Tx buffer size" - default 256 - ---help--- - Modem UART Tx buffer size. Default: 256 - -config UART_MODEM_HWFLOWCONTROL - bool "Hardware flow control" - default n - ---help--- - Enabled Modem UART hardware flow control. Default: n - -endmenu - -menu "IrDA UART Configuration" - -config UART_IRDA_BAUD - int "IrDA UART BAUD" - default 115200 - -config UART_IRDA_PARITY - int "IrDA UART parity" - default 0 - ---help--- - IrDA UART parity. 0=None, 1=Odd, 2=Even. Default: None - -config UART_IRDA_BITS - int "IrDA UART number of bits" - default 8 - ---help--- - IrDA UART number of bits. Default: 8 - -config UART_IRDA_2STOP - int "IrDA UART two stop bits" - default 0 - ---help--- - 0=1 stop bit, 1=Two stop bits. Default: 1 stop bit - -config UART_IRDA_RXBUFSIZE - int "IrDA UART Rx buffer size" - default 256 - ---help--- - IrDA UART Rx buffer size. Default: 256 - -config UART_IRDA_TXBUFSIZE - int "IrDA UART Tx buffer size" - default 256 - ---help--- - IrDA UART Tx buffer size. Default: 256 - -config UART_IRDA_HWFLOWCONTROL - bool "Hardware flow control" - default n - ---help--- - Enabled IrDA UART hardware flow control. Default: n - -endmenu - -choice - prompt "Serial Console Selection" - default SERIAL_CONSOLE_NONE - depends on DEV_CONSOLE - -# See drivers/Kconfig -config USE_SERCOMM_CONSOLE - bool "SERCOMM console" - select SERCOMM_CONSOLE - -config SERIAL_MODEM_CONSOLE - bool "Serial console on modem UART" - -config SERIAL_IRDA_CONSOLE - bool "Serial console on IrDA UART" - -config SERIAL_CONSOLE_NONE - bool "No serial console" - -endchoice diff --git a/arch/arm/src/calypso/Make.defs b/arch/arm/src/calypso/Make.defs deleted file mode 100644 index c3d6b6b0bb..0000000000 --- a/arch/arm/src/calypso/Make.defs +++ /dev/null @@ -1,71 +0,0 @@ -############################################################################ -# calypso/Make.defs -# -# Copyright (C) 2007, 2013-2015 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Copyright (C) 2011 Stefan Richter. All rights reserved. -# Author: Stefan Richter -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name Gregory Nutt nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -HEAD_ASRC = calypso_head.S - -CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_vectors.S -CMN_ASRCS += up_nommuhead.S vfork.S -CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copyfullstate.c -CMN_CSRCS += up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c -CMN_CSRCS += up_doirq.c up_exit.c up_idle.c up_initialstate.c up_initialize.c -CMN_CSRCS += up_interruptcontext.c up_prefetchabort.c up_releasepending.c -CMN_CSRCS += up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c -CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_syscall.c up_unblocktask.c -CMN_CSRCS += up_undefinedinsn.c up_usestack.c calypso_power.c up_vfork.c - -ifeq ($(CONFIG_ELF),y) -CMN_CSRCS += up_elf.c -else ifeq ($(CONFIG_MODULE),y) -CMN_CSRCS += up_elf.c -endif - -ifeq ($(CONFIG_STACK_COLORATION),y) -CMN_CSRCS += up_checkstack.c -endif - -CHIP_ASRCS = calypso_lowputc.S -CHIP_CSRCS = calypso_irq.c calypso_heap.c calypso_serial.c clock.c -CHIP_CSRCS += calypso_uwire.c calypso_armio.c calypso_keypad.c - -ifeq ($(CONFIG_SPI),y) -CHIP_CSRCS += calypso_spi.c -endif - -ifneq ($(CONFIG_SCHED_TICKLESS),y) -CHIP_CSRCS += calypso_timer.c -endif diff --git a/arch/arm/src/calypso/calypso_armio.c b/arch/arm/src/calypso/calypso_armio.c deleted file mode 100644 index c210fa34dc..0000000000 --- a/arch/arm/src/calypso/calypso_armio.c +++ /dev/null @@ -1,103 +0,0 @@ -/**************************************************************************** - * Driver for shared features of ARMIO modules - * - * Copyright (C) 2011 Stefan Richter. All rights reserved. - * Author: Stefan Richter - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "up_arch.h" - -/**************************************************************************** - * HW access - ****************************************************************************/ - -#define BASE_ADDR_ARMIO 0xfffe4800 -#define ARMIO_REG(x) (BASE_ADDR_ARMIO + (x)) - -enum armio_reg { - LATCH_IN = 0x00, - LATCH_OUT = 0x02, - IO_CNTL = 0x04, - CNTL_REG = 0x06, - LOAD_TIM = 0x08, - KBR_LATCH_REG = 0x0a, - KBC_REG = 0x0c, - BUZZ_LIGHT_REG = 0x0e, - LIGHT_LEVEL = 0x10, - BUZZER_LEVEL = 0x12, - GPIO_EVENT_MODE = 0x14, - KBD_GPIO_INT = 0x16, - KBD_GPIO_MASKIT = 0x18, - GPIO_DEBOUNCING = 0x1a, - GPIO_LATCH = 0x1c, -}; - -#define KBD_INT (1 << 0) -#define GPIO_INT (1 << 1) - -/**************************************************************************** - * ARMIO interrupt handler - * forward keypad events - * forward GPIO events - ****************************************************************************/ - -static int kbd_gpio_irq(int irq, uint32_t *regs) -{ - return calypso_kbd_irq(irq, regs); -} - -/**************************************************************************** - * Initialize ARMIO - ****************************************************************************/ - -void calypso_armio(void) -{ - /* Enable ARMIO clock */ - - putreg16(1 << 5, ARMIO_REG(CNTL_REG)); - - /* Mask GPIO interrupt and keypad interrupt */ - - putreg16(KBD_INT | GPIO_INT, ARMIO_REG(KBD_GPIO_MASKIT)); - - /* Attach and enable the interrupt */ - - irq_attach(IRQ_KEYPAD_GPIO, (xcpt_t)kbd_gpio_irq); - up_enable_irq(IRQ_KEYPAD_GPIO); -} diff --git a/arch/arm/src/calypso/calypso_head.S b/arch/arm/src/calypso/calypso_head.S deleted file mode 100644 index eb83b68516..0000000000 --- a/arch/arm/src/calypso/calypso_head.S +++ /dev/null @@ -1,23 +0,0 @@ -/* Place a branch to the real head at the entry point */ -.section .text.start - b __start - - -/* Exception Vectors like they are needed for the exception vector - indirection of the internal boot ROM. The following section must - be liked to appear at 0x80001c */ -.section .text.exceptions -_undef_instr: - b up_vectorundefinsn -_sw_interr: - b up_vectorswi -_prefetch_abort: - b up_vectorprefetch -_data_abort: - b up_vectordata -_reserved: - b _reserved -_irq: - b up_vectorirq -_fiq: - b up_vectorfiq diff --git a/arch/arm/src/calypso/calypso_heap.c b/arch/arm/src/calypso/calypso_heap.c deleted file mode 100644 index 697e05a8f5..0000000000 --- a/arch/arm/src/calypso/calypso_heap.c +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * arch/arm/src/calypso/calypso_heap.c - * Initialize memory interfaces of Calypso MCU - * - * (C) 2010 by Harald Welte - * (C) 2011 Stefan Richter - * - * This source code is derivated from Osmocom-BB project and was - * relicensed as BSD with permission from original authors. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include - -#include -#include - -#include -#include - -#include "up_arch.h" -#include "up_internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_addregion - * - * Description: - * This function is called right after basics are initialized and right - * before IRQ system setup. - * - ****************************************************************************/ - -#if CONFIG_MM_REGIONS > 1 -void up_addregion(void) -{ -#ifdef CONFIG_ARCH_BOARD_COMPALE99 - /* Disable watchdog in first non-common function */ - wdog_enable(0); -#endif - /* XXX: change to initialization of extern memory with save defaults */ - /* Configure memory interface */ - calypso_mem_cfg(CALYPSO_nCS0, 3, CALYPSO_MEM_16bit, 1); - calypso_mem_cfg(CALYPSO_nCS1, 3, CALYPSO_MEM_16bit, 1); - calypso_mem_cfg(CALYPSO_nCS2, 5, CALYPSO_MEM_16bit, 1); - calypso_mem_cfg(CALYPSO_nCS3, 5, CALYPSO_MEM_16bit, 1); - calypso_mem_cfg(CALYPSO_CS4, 0, CALYPSO_MEM_8bit, 1); - calypso_mem_cfg(CALYPSO_nCS6, 0, CALYPSO_MEM_32bit, 1); - calypso_mem_cfg(CALYPSO_nCS7, 0, CALYPSO_MEM_32bit, 0); - - /* Set VTCXO_DIV2 = 1, configure PLL for 104 MHz and give ARM half of that */ - calypso_clock_set(2, CALYPSO_PLL13_104_MHZ, ARM_MCLK_DIV_2); - - /* Configure the RHEA bridge with some sane default values */ - calypso_rhea_cfg(0, 0, 0xff, 0, 1, 0, 0); - - kmm_addregion((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); -} -#endif diff --git a/arch/arm/src/calypso/calypso_irq.c b/arch/arm/src/calypso/calypso_irq.c deleted file mode 100644 index 85f4f08458..0000000000 --- a/arch/arm/src/calypso/calypso_irq.c +++ /dev/null @@ -1,357 +0,0 @@ -/**************************************************************************** - * arch/arm/src/calypso/calypso_irq.c - * Driver for Calypso IRQ controller - * - * (C) 2010 by Harald Welte - * (C) 2011 by Stefan Richter - * - * This source code is derivated from Osmocom-BB project and was - * relicensed as BSD with permission from original authors. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include -#include - -#include "arm.h" -#include "up_internal.h" -#include "up_arch.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define BASE_ADDR_IRQ 0xfffffa00 -#define BASE_ADDR_IBOOT_EXC 0x0080001C - -enum irq_reg -{ - IT_REG1 = 0x00, - IT_REG2 = 0x02, - MASK_IT_REG1 = 0x08, - MASK_IT_REG2 = 0x0a, - IRQ_NUM = 0x10, - FIQ_NUM = 0x12, - IRQ_CTRL = 0x14, -}; - -#define ILR_IRQ(x) (0x20 + (x*2)) -#define IRQ_REG(x) (BASE_ADDR_IRQ + (x)) - -#ifndef ARRAY_SIZE -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt - * processing. Access to g_current_regs[] must be through the macro - * CURRENT_REGS for portability. - */ - -volatile uint32_t *g_current_regs[1]; -extern uint32_t _exceptions; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static uint8_t default_irq_prio[] = -{ - [IRQ_WATCHDOG] = 0xff, - [IRQ_TIMER1] = 0xff, - [IRQ_TIMER2] = 0xff, - [IRQ_TSP_RX] = 0, - [IRQ_TPU_FRAME] = 3, - [IRQ_TPU_PAGE] = 0xff, - [IRQ_SIMCARD] = 0xff, - [IRQ_UART_MODEM] = 8, - [IRQ_KEYPAD_GPIO] = 4, - [IRQ_RTC_TIMER] = 9, - [IRQ_RTC_ALARM_I2C] = 10, - [IRQ_ULPD_GAUGING] = 2, - [IRQ_EXTERNAL] = 12, - [IRQ_SPI] = 0xff, - [IRQ_DMA] = 0xff, - [IRQ_API] = 0xff, - [IRQ_SIM_DETECT] = 0, - [IRQ_EXTERNAL_FIQ] = 7, - [IRQ_UART_IRDA] = 2, - [IRQ_ULPD_GSM_TIMER] = 1, - [IRQ_GEA] = 0xff, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static void _irq_enable(enum irq_nr nr, int enable) -{ - uintptr_t reg = IRQ_REG(MASK_IT_REG1); - uint16_t val; - - if (nr > 15) - { - reg = IRQ_REG(MASK_IT_REG2); - nr -= 16; - } - - val = getreg16(reg); - if (enable) - { - val &= ~(1 << nr); - } - else - { - val |= (1 << nr); - } - - putreg16(val, reg); -} - -static void set_default_priorities(void) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(default_irq_prio); i++) - { - uint16_t val; - uint8_t prio = default_irq_prio[i]; - - if (prio > 31) - { - prio = 31; - } - - val = getreg16(IRQ_REG(ILR_IRQ(i))); - val &= ~(0x1f << 2); - val |= prio << 2; - - /* Make edge mode default. Hopefully causes less trouble */ - - val |= 0x02; - - putreg16(val, IRQ_REG(ILR_IRQ(i))); - } -} - -/* Install the exception handlers to where the ROM loader jumps */ - -static void calypso_exceptions_install(void) -{ - uint32_t *exceptions_dst = (uint32_t *) BASE_ADDR_IBOOT_EXC; - uint32_t *exceptions_src = &_exceptions; - int i; - - for (i = 0; i < 7; i++) - { - *exceptions_dst++ = *exceptions_src++; - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_irqinitialize - * - * Description: - * Setup the IRQ and FIQ controllers - * - ****************************************************************************/ - -void up_irqinitialize(void) -{ - /* Prepare hardware */ - - calypso_exceptions_install(); - CURRENT_REGS = NULL; - - /* Switch to internal ROM */ - - calypso_bootrom(1); - - /* Set default priorities */ - - set_default_priorities(); - - /* Mask all interrupts off */ - - putreg16(0xffff, IRQ_REG(MASK_IT_REG1)); - putreg16(0xffff, IRQ_REG(MASK_IT_REG2)); - - /* clear all pending interrupts */ - putreg16(0, IRQ_REG(IT_REG1)); - putreg16(0, IRQ_REG(IT_REG2)); - - /* Enable interrupts globally to the ARM core */ - -#ifndef CONFIG_SUPPRESS_INTERRUPTS - up_irq_restore(SVC_MODE | PSR_F_BIT); -#endif -} - -/**************************************************************************** - * Name: up_disable_irq - * - * Description: - * Disable the IRQ specified by 'irq' - * - ****************************************************************************/ - -void up_disable_irq(int irq) -{ - if ((unsigned)irq < NR_IRQS) - { - _irq_enable(irq, 0); - } -} - -/**************************************************************************** - * Name: up_enable_irq - * - * Description: - * Enable the IRQ specified by 'irq' - * - ****************************************************************************/ - -void up_enable_irq(int irq) -{ - if ((unsigned)irq < NR_IRQS) - { - _irq_enable(irq, 1); - } -} - -/**************************************************************************** - * Name: up_prioritize_irq - * - * Description: - * Set the priority of an IRQ. - * - ****************************************************************************/ - -#ifndef CONFIG_ARCH_IRQPRIO -int up_prioritize_irq(int nr, int prio) -{ - uint16_t val; - - if (prio == -1) - { - prio = default_irq_prio[nr]; - } - - if (prio > 31) - { - prio = 31; - } - - val = prio << 2; - putreg16(val, IRQ_REG(ILR_IRQ(nr))); - - return 0; -} -#endif - -/**************************************************************************** - * Entry point for interrupts - ****************************************************************************/ - -void up_decodeirq(uint32_t *regs) -{ - uint8_t num, tmp; - uint32_t *saved_regs; - - /* XXX: What is this??? - * Passed to but ignored in IRQ handlers - * Only valid meaning is apparently non-NULL == IRQ context */ - - saved_regs = (uint32_t *)CURRENT_REGS; - CURRENT_REGS = regs; - - /* Detect & deliver the IRQ */ - - num = getreg8(IRQ_REG(IRQ_NUM)) & 0x1f; - irq_dispatch(num, regs); - - /* Start new IRQ agreement */ - - tmp = getreg8(IRQ_REG(IRQ_CTRL)); - tmp |= 0x01; - putreg8(tmp, IRQ_REG(IRQ_CTRL)); - - CURRENT_REGS = saved_regs; -} - -/**************************************************************************** - * Entry point for FIQs - ****************************************************************************/ - -void calypso_fiq(void) -{ - uint8_t num, tmp; - uint32_t *regs; - - /* XXX: What is this??? - * Passed to but ignored in IRQ handlers - * Only valid meaning is apparently non-NULL == IRQ context */ - - regs = (uint32_t *)CURRENT_REGS; - CURRENT_REGS = (uint32_t *)# - - /* Detect & deliver like an IRQ but we are in FIQ context */ - - num = getreg8(IRQ_REG(FIQ_NUM)) & 0x1f; - irq_dispatch(num, regs); - - /* Start new FIQ agreement */ - - tmp = getreg8(IRQ_REG(IRQ_CTRL)); - tmp |= 0x02; - putreg8(tmp, IRQ_REG(IRQ_CTRL)); - - CURRENT_REGS = regs; -} diff --git a/arch/arm/src/calypso/calypso_keypad.c b/arch/arm/src/calypso/calypso_keypad.c deleted file mode 100644 index 1d9b11b98a..0000000000 --- a/arch/arm/src/calypso/calypso_keypad.c +++ /dev/null @@ -1,385 +0,0 @@ -/**************************************************************************** - * Driver for Calypso keypad hardware - * - * Copyright (C) 2011 Stefan Richter. All rights reserved. - * Author: Stefan Richter - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/**************************************************************************** - * HW access - ****************************************************************************/ - -#define BASE_ADDR_ARMIO 0xfffe4800 -#define ARMIO_REG(x) ((void *)BASE_ADDR_ARMIO + (x)) - -enum armio_reg -{ - LATCH_IN = 0x00, - LATCH_OUT = 0x02, - IO_CNTL = 0x04, - CNTL_REG = 0x06, - LOAD_TIM = 0x08, - KBR_LATCH_REG = 0x0a, - KBC_REG = 0x0c, - BUZZ_LIGHT_REG = 0x0e, - LIGHT_LEVEL = 0x10, - BUZZER_LEVEL = 0x12, - GPIO_EVENT_MODE = 0x14, - KBD_GPIO_INT = 0x16, - KBD_GPIO_MASKIT = 0x18, - GPIO_DEBOUNCING = 0x1a, - GPIO_LATCH = 0x1c, -}; - -#define KBD_INT (1 << 0) -#define GPIO_INT (1 << 1) - -/**************************************************************************** - * Decoder functions for matrix and power button - ****************************************************************************/ - -static int btn_dec(uint32_t * btn_state, uint8_t col, uint8_t reg, - char *buf, size_t buflen, size_t * len) -{ - uint8_t diff = (*btn_state ^ reg) & 0x1f; - - while (diff) - { - uint8_t val = diff & ~(diff - 1); - uint8_t sc = val >> 1; - sc |= sc << 2; - sc += col; - sc += (sc & 0x20) ? 0x26 : 0x3f; - - if (reg & val) - { - sc |= 0x20; - } - - /* Check for space in buffer and dispatch */ - - if (*len < buflen) - { - buf[(*len)++] = sc; - } - else - { - break; - } - - /* Only change diff if dispatched/buffer not full */ - - diff ^= val; - } - - /* Store new state of the buttons (but only if they where dispatch) */ - - *btn_state >>= 5; -#ifdef INCLUDE_ALL_COLS - *btn_state |= (reg ^ diff) << 20; -#else - *btn_state |= (reg ^ diff) << 15; -#endif - return diff; -} - -static int pwr_btn_dec(uint32_t * state, uint8_t reg, char *buf, size_t * len) -{ - if (reg) - { - /* Check for pressed power button. If pressed, ignore other - * buttons since it collides with an entire row. - */ - - if (~*state & 0x80000000) - { - buf[0] = 'z'; - *len = 1; - *state |= 0x80000000; - } - - return 1; /* break loop in caller */ - } - else - { - /* Check for released power button. */ - - if (*state & 0x80000000) - { - buf[0] = 'Z'; - *len = 1; - - *state &= 0x7fffffff; - - /* Don't scan others when released; might trigger - * false keystrokes otherwise - */ - - return 1; - } - } - - return 0; /* Continue with other columns */ -} - -/**************************************************************************** - * Keypad: Fileops Prototypes and Structures - ****************************************************************************/ - -typedef FAR struct file file_t; - -static int keypad_open(file_t * filep); -static int keypad_close(file_t * filep); -static ssize_t keypad_read(file_t * filep, FAR char *buffer, size_t buflen); -#ifndef CONFIG_DISABLE_POLL -static int keypad_poll(file_t * filep, FAR struct pollfd *fds, bool setup); -#endif - -static const struct file_operations keypad_ops = -{ - keypad_open, /* open */ - keypad_close, /* close */ - keypad_read, /* read */ - 0, /* write */ - 0, /* seek */ - 0, /* ioctl */ -#ifndef CONFIG_DISABLE_POLL - keypad_poll /* poll */ -#endif -}; - -static sem_t kbdsem; - -/**************************************************************************** - * Keypad: Fileops - ****************************************************************************/ - -static int keypad_open(file_t * filep) -{ - register uint16_t reg; - - /* Unmask keypad interrupt */ - - reg = readw(ARMIO_REG(KBD_GPIO_MASKIT)); - writew(reg & ~KBD_INT, ARMIO_REG(KBD_GPIO_MASKIT)); - - return OK; -} - -static int keypad_close(file_t * filep) -{ - register uint16_t reg; - - /* Mask keypad interrupt */ - - reg = readw(ARMIO_REG(KBD_GPIO_MASKIT)); - writew(reg | KBD_INT, ARMIO_REG(KBD_GPIO_MASKIT)); - - return OK; -} - -static ssize_t keypad_read(file_t * filep, FAR char *buf, size_t buflen) -{ - static uint32_t btn_state = 0; - register uint16_t reg; - uint16_t col, col_mask; - size_t len = 0; - - if (buf == NULL || buflen < 1) - { - /* Well... nothing to do */ - - return -EINVAL; - } - -retry: - col = 1; - col_mask = 0x1e; - - if (!btn_state) - { - /* Drive all cols low such that all buttons cause events */ - - writew(0, ARMIO_REG(KBC_REG)); - - /* No button currently pressed, use IRQ */ - - reg = readw(ARMIO_REG(KBD_GPIO_MASKIT)); - writew(reg & ~KBD_INT, ARMIO_REG(KBD_GPIO_MASKIT)); - sem_wait(&kbdsem); - } - else - { - writew(0x1f, ARMIO_REG(KBC_REG)); - usleep(80000); - } - - /* Scan columns */ - -#ifdef INCLUDE_ALL_COLS - while (col <= 6) - { -#else - while (col <= 5) - { -#endif - /* Read keypad latch and immediately set new column since - * synchronization takes about 5usec. For the 1st round, the - * interrupt has prepared this and the context switch takes - * long enough to serve as a delay. - */ - - reg = readw(ARMIO_REG(KBR_LATCH_REG)); - writew(col_mask, ARMIO_REG(KBC_REG)); - - /* Turn pressed buttons into 1s */ - - reg = 0x1f & ~reg; - - if (col == 1) - { - /* Power/End switch */ - - if (pwr_btn_dec(&btn_state, reg, buf, &len)) - { - break; - } - } - else - { - /* Non-power switches */ - - if (btn_dec(&btn_state, col, reg, buf, buflen, &len)) - { - break; - } - } - - /* Select next column and respective mask */ - - col_mask = 0x1f & ~(1 << col++); - - /* We have to wait for synchronization of the inputs. The - * processing is too fast if no/few buttons are processed. - */ - - usleep(5); - - /* XXX: usleep seems to suffer hugh overhead. Better this!? - * If nothing else can be done, it's overhead still wastes - * time 'usefully'. - */ - /* sched_yield(); up_udelay(2); */ - } - - /* If we don't have anything to return, retry to avoid EOF */ - - if (!len) - { - goto retry; - } - - return len; -} - -/**************************************************************************** - * Keypad interrupt handler - * mask interrupts - * prepare column drivers for scan - * posts keypad semaphore - ****************************************************************************/ - -int calypso_kbd_irq(int irq, uint32_t * regs) -{ - register uint16_t reg; - - /* Mask keypad interrupt */ - - reg = readw(ARMIO_REG(KBD_GPIO_MASKIT)); - writew(reg | KBD_INT, ARMIO_REG(KBD_GPIO_MASKIT)); - - /* Turn off column drivers */ - - writew(0x1f, ARMIO_REG(KBC_REG)); - - /* Let the userspace know */ - - sem_post(&kbdsem); - - return 0; -} - -/**************************************************************************** - * Initialize device, add /dev/... nodes - ****************************************************************************/ - -void up_keypad(void) -{ - /* kbssem semaphore helps leaving IRQ ctx as soon as possible. This - * semaphore is used for signaling and, hence, should not have priority - * inheritance enabled. - */ - - sem_init(&kbdsem, 0, 0); - sem_setprotocol(&kbdsem, SEM_PRIO_NONE); - - /* Drive cols low in idle state such that all buttons cause events */ - - writew(0, ARMIO_REG(KBC_REG)); - - (void)register_driver("/dev/keypad", &keypad_ops, 0444, NULL); -} - -int keypad_kbdinit(void) -{ - calypso_armio(); - up_keypad(); - - return OK; -} diff --git a/arch/arm/src/calypso/calypso_lowputc.S b/arch/arm/src/calypso/calypso_lowputc.S deleted file mode 100644 index 5556b3baca..0000000000 --- a/arch/arm/src/calypso/calypso_lowputc.S +++ /dev/null @@ -1,133 +0,0 @@ -/************************************************************************** - * calypso/calypso_lowputc.S - * - * Copyright (C) 2011 Stefan Richter. All rights reserved. - * Author: Stefan Richter - * - * based on: c5471/c5471_lowputc.S - * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************/ - -/************************************************************************** - * Included Files - **************************************************************************/ - -#include - -#include "chip.h" -#include "up_arch.h" -#include "up_internal.h" - -/************************************************************************** - * Pre-processor Definitions - **************************************************************************/ - -/************************************************************************** - * Private Types - **************************************************************************/ - -/************************************************************************** - * Private Function Prototypes - **************************************************************************/ - -/************************************************************************** - * Public Data - **************************************************************************/ - -/************************************************************************** - * Private Data - **************************************************************************/ - -/************************************************************************** - * Private Functions - **************************************************************************/ - -/************************************************************************** - * Public Functions - **************************************************************************/ - -/************************************************************************** - * Name: up_lowputc - **************************************************************************/ - -/* This assembly language version has the advantage that it can does not - * require a C stack and uses only r0-r1. Hence it can be used during - * early boot phases. - */ - - .text - .global up_lowputc - .type up_lowputc, function -up_lowputc: - /* On entry, r0 holds the character to be printed */ - -#ifdef CONFIG_SERIAL_IRDA_CONSOLE - ldr r2, =UART_IRDA_BASE /* r2=IRDA UART base */ -#else - ldr r2, =UART_MODEM_BASE /* r2=Modem UART base */ -#endif - - /* Poll bit 0 of the UART_SSR register. When the bit - * is clear, the TX FIFO is no longer full - */ - -1: ldrb r1, [r2, #UART_SSR_OFFS] - tst r1, #UART_SSR_TXFULL - bne 1b - - /* Send the character by writing it into the UART_THR - * register. - */ - - strb r0, [r2, #UART_THR_OFFS] - - /* Wait for the tranmsit holding regiser (THR) to be - * emptied. This is detemined when bit 6 of the LSR - * is set. - */ - -2: ldrb r1, [r2, #UART_LSR_OFFS] - tst r1, #0x00000020 - beq 2b - - /* If the character that we just sent was a linefeed, - * then send a carriage return as well. - */ - - teq r0, #'\n' - moveq r0, #'\r' - beq 1b - - /* And return */ - - mov pc, lr - diff --git a/arch/arm/src/calypso/calypso_power.c b/arch/arm/src/calypso/calypso_power.c deleted file mode 100644 index 11b51a629b..0000000000 --- a/arch/arm/src/calypso/calypso_power.c +++ /dev/null @@ -1,50 +0,0 @@ -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "calypso_spi.h" - -/**************************************************************************** - * Name: board_power_off - * - * Description: - * Power off the board. - * - * If this function returns, then it was not possible to power-off the - * board due to some other constraints. - * - * Input Parameters: - * status - Status information provided with the power off event. - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARDCTL_POWEROFF -int board_power_off(int status) -{ - struct spi_dev_s *spi = calypso_spibus_initialize(0); - uint16_t tx; - - SPI_SETBITS(spi, 16); - (void)SPI_HWFEATURES(spi, 0); - - tx = (1 << 6) | (1 << 1); - SPI_SNDBLOCK(spi, &tx, 1); - - tx = (1 << 6) | (30 << 1); - SPI_SNDBLOCK(spi, &tx, 1); - - return 0; -} -#endif diff --git a/arch/arm/src/calypso/calypso_serial.c b/arch/arm/src/calypso/calypso_serial.c deleted file mode 100644 index 0c4a44c0c1..0000000000 --- a/arch/arm/src/calypso/calypso_serial.c +++ /dev/null @@ -1,968 +0,0 @@ -/**************************************************************************** - * arch/arm/src/calypso/calypso_serial.c - * - * Copyright (C) 2011 Stefan Richter. All rights reserved. - * Author: Stefan Richter - * - * based on c5471/c5471_serial.c - * Copyright (C) 2007-2009, 2013 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "chip.h" -#include "up_arch.h" -#include "up_internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define BASE_BAUD 115200 - -#if defined(CONFIG_UART_IRDA_HWFLOWCONTROL) || defined(CONFIG_UART_MODEM_HWFLOWCONTROL) -# define CONFIG_UART_HWFLOWCONTROL -#endif - -#if UART_FCR_OFFS == UART_EFR_OFFS -# define UART_MULTIPLEX_REGS - -/* HW flow control not supported yet */ - -# undef CONFIG_UART_HWFLOWCONTROL -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct uart_regs_s -{ - uint32_t ier; - uint32_t lcr; - uint32_t fcr; -#ifdef CONFIG_UART_HWFLOWCONTROL - uint32_t efr; - uint32_t tcr; -#endif -}; - -struct up_dev_s -{ - unsigned int uartbase; /* Base address of UART registers */ - unsigned int baud_base; /* Base baud for conversions */ - unsigned int baud; /* Configured baud */ - uint8_t xmit_fifo_size; /* Size of transmit FIFO */ - uint8_t irq; /* IRQ associated with this UART */ - uint8_t parity; /* 0=none, 1=odd, 2=even */ - uint8_t bits; /* Number of bits (7 or 8) */ -#ifdef CONFIG_UART_HWFLOWCONTROL - bool flowcontrol; /* true: Hardware flow control - * is enabled. */ -#endif - bool stopbits2; /* true: Configure with 2 - * stop bits instead of 1 */ - struct uart_regs_s regs; /* Shadow copy of readonly regs */ - -#ifdef CONFIG_SERCOMM_CONSOLE - bool sercomm; /* Call sercomm in interrupt if true */ -#endif -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int up_setup(struct uart_dev_s *dev); -static void up_shutdown(struct uart_dev_s *dev); -static int up_attach(struct uart_dev_s *dev); -static void up_detach(struct uart_dev_s *dev); -static int up_interrupt(int irq, void *context); -static int up_ioctl(struct file *filep, int cmd, unsigned long arg); -static int up_receive(struct uart_dev_s *dev, unsigned int *status); -static void up_rxint(struct uart_dev_s *dev, bool enable); -static bool up_rxavailable(struct uart_dev_s *dev); -static void up_send(struct uart_dev_s *dev, int ch); -static void up_txint(struct uart_dev_s *dev, bool enable); -static bool up_txready(struct uart_dev_s *dev); -static bool up_txempty(struct uart_dev_s *dev); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct uart_ops_s g_uart_ops = -{ - .setup = up_setup, - .shutdown = up_shutdown, - .attach = up_attach, - .detach = up_detach, - .ioctl = up_ioctl, - .receive = up_receive, - .rxint = up_rxint, - .rxavailable = up_rxavailable, -#ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = NULL, -#endif - .send = up_send, - .txint = up_txint, - .txready = up_txready, - .txempty = up_txempty, -}; - -/* I/O buffers */ - -static char g_irdarxbuffer[CONFIG_UART_IRDA_RXBUFSIZE]; -static char g_irdatxbuffer[CONFIG_UART_IRDA_TXBUFSIZE]; -static char g_modemrxbuffer[CONFIG_UART_MODEM_RXBUFSIZE]; -static char g_modemtxbuffer[CONFIG_UART_MODEM_TXBUFSIZE]; - -/* This describes the state of the C5471 serial IRDA port. */ - -static struct up_dev_s g_irdapriv = -{ - .xmit_fifo_size = UART_IRDA_XMIT_FIFO_SIZE, - .baud_base = BASE_BAUD, - .uartbase = UART_IRDA_BASE, - .baud = CONFIG_UART_IRDA_BAUD, - .irq = UART_IRQ_IRDA, - .parity = CONFIG_UART_IRDA_PARITY, - .bits = CONFIG_UART_IRDA_BITS, -#ifdef CONFIG_UART_IRDA_HWFLOWCONTROL - .flowcontrol = true, -#endif - .stopbits2 = CONFIG_UART_IRDA_2STOP, - -#ifdef CONFIG_SERCOMM_CONSOLE - .sercomm = false, -#endif -}; - -static uart_dev_t g_irdaport = -{ - .recv = - { - .size = CONFIG_UART_IRDA_RXBUFSIZE, - .buffer = g_irdarxbuffer, - }, - .xmit = - { - .size = CONFIG_UART_IRDA_TXBUFSIZE, - .buffer = g_irdatxbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_irdapriv, -}; - -/* This describes the state of the C5471 serial Modem port. */ - -static struct up_dev_s g_modempriv = -{ - .xmit_fifo_size = UART_XMIT_FIFO_SIZE, - .baud_base = BASE_BAUD, - .uartbase = UART_MODEM_BASE, - .baud = CONFIG_UART_MODEM_BAUD, - .irq = UART_IRQ_MODEM, - .parity = CONFIG_UART_MODEM_PARITY, - .bits = CONFIG_UART_MODEM_BITS, -#ifdef CONFIG_UART_MODEM_HWFLOWCONTROL - .flowcontrol = true, -#endif - .stopbits2 = CONFIG_UART_MODEM_2STOP, - -#ifdef CONFIG_SERCOMM_CONSOLE - .sercomm = false, -#endif -}; - -static uart_dev_t g_modemport = -{ - .recv = - { - .size = CONFIG_UART_MODEM_RXBUFSIZE, - .buffer = g_modemrxbuffer, - }, - .xmit = - { - .size = CONFIG_UART_MODEM_TXBUFSIZE, - .buffer = g_modemtxbuffer, - }, - .ops = &g_uart_ops, - .priv = &g_modempriv, -}; - -/* Now, which one with be tty0/console and which tty1? */ - -#ifdef CONFIG_SERIAL_IRDA_CONSOLE -# define CONSOLE_DEV g_irdaport -# define TTYS0_DEV g_irdaport -# define TTYS1_DEV g_modemport -#else -# define CONSOLE_DEV g_modemport -# define TTYS0_DEV g_modemport -# define TTYS1_DEV g_irdaport -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_inserial - ****************************************************************************/ - -static inline uint32_t up_inserial(struct up_dev_s *priv, uint32_t offset) -{ -#if UART_REGISTER_BITS == 8 - return getreg8(priv->uartbase + offset); -#elif UART_REGISTER_BITS == 32 - return getreg32(priv->uartbase + offset); -#else -#error Unsupported number of bits set in UART_REGISTER_BITS -#endif -} - -/**************************************************************************** - * Name: up_serialout - ****************************************************************************/ - -static inline void up_serialout(struct up_dev_s *priv, uint32_t offset, uint32_t value) -{ -#if UART_REGISTER_BITS == 8 - putreg8(value & 0xff, priv->uartbase + offset); -#elif UART_REGISTER_BITS == 32 - putreg32(value, priv->uartbase + offset); -#endif -} - -/**************************************************************************** - * Name: up_disableuartint - ****************************************************************************/ - -static inline void up_disableuartint(struct up_dev_s *priv, uint16_t *ier) -{ - if (ier) - { - *ier = priv->regs.ier & UART_IER_INTMASK; - } - priv->regs.ier &= ~UART_IER_INTMASK; - up_serialout(priv, UART_IER_OFFS, priv->regs.ier); -} - -/**************************************************************************** - * Name: up_restoreuartint - ****************************************************************************/ - -static inline void up_restoreuartint(struct up_dev_s *priv, uint16_t ier) -{ - priv->regs.ier |= ier & (UART_IER_RECVINT | UART_IER_XMITINT); - up_serialout(priv, UART_IER_OFFS, priv->regs.ier); -} - -/**************************************************************************** - * Name: up_waittxready - ****************************************************************************/ - -static inline void up_waittxready(struct up_dev_s *priv) -{ - int tmp; - - for (tmp = 1000 ; tmp > 0 ; tmp--) - { - if ((up_inserial(priv, UART_SSR_OFFS) & UART_SSR_TXFULL) == 0) - { - break; - } - } -} -/**************************************************************************** - * Name: up_disablebreaks - ****************************************************************************/ - -static inline void up_disablebreaks(struct up_dev_s *priv) -{ - priv->regs.lcr &= ~UART_LCR_BOC; - up_serialout(priv, UART_LCR_OFFS, priv->regs.lcr); -} - -/**************************************************************************** - * Name: up_enablebreaks - ****************************************************************************/ - -static inline void up_enablebreaks(struct up_dev_s *priv) -{ - priv->regs.lcr |= UART_LCR_BOC; - up_serialout(priv, UART_LCR_OFFS, priv->regs.lcr); -} - -/**************************************************************************** - * Name: up_setrate - ****************************************************************************/ - -static inline void up_setrate(struct up_dev_s *priv, unsigned int rate) -{ - uint32_t div_bit_rate; - - switch (rate) - { - case 115200: - div_bit_rate = BAUD_115200; - break; - case 57600: - div_bit_rate = BAUD_57600; - break; - case 38400: - div_bit_rate = BAUD_38400; - break; - case 19200: - div_bit_rate = BAUD_19200; - break; - case 4800: - div_bit_rate = BAUD_4800; - break; - case 2400: - div_bit_rate = BAUD_2400; - break; - case 1200: - div_bit_rate = BAUD_1200; - break; - case 9600: - default: - div_bit_rate = BAUD_9600; - break; - } - -#ifdef UART_DIV_BIT_RATE_OFFS - up_serialout(priv, UART_DIV_BIT_RATE_OFFS, div_bit_rate); -#else - up_serialout(priv, UART_DIV_LOW_OFFS, div_bit_rate); - up_serialout(priv, UART_DIV_HIGH_OFFS, div_bit_rate >> 8); -#endif -} - -/**************************************************************************** - * Name: up_setup - * - * Description: - * Configure the UART baud, bits, parity, fifos, etc. This - * method is called the first time that the serial port is - * opened. - * - ****************************************************************************/ -#include -static int up_setup(struct uart_dev_s *dev) -{ -#ifndef CONFIG_SUPPRESS_UART_CONFIG - struct up_dev_s *priv = dev->priv; - unsigned int cval; - - if (priv->bits == 7) - { - cval = UART_LCR_7BITS; - } - else - { - cval = UART_LCR_8BITS; - } - - if (priv->stopbits2) - { - cval |= UART_LCR_2STOP; - } - - if (priv->parity == 1) /* Odd parity */ - { - cval |= (UART_LCR_PAREN | UART_LCR_PARODD); - } - else if (priv->parity == 2) /* Even parity */ - { - cval |= (UART_LCR_PAREN | UART_LCR_PAREVEN); - } - - /* Both the IrDA and MODEM UARTs support RESET and UART mode. */ - - up_serialout(priv, UART_MDR_OFFS, MDR_RESET_MODE); - up_serialout(priv, UART_LCR_OFFS, 0xbf); - up_serialout(priv, UART_XON1_OFFS, 0x00); - up_serialout(priv, UART_XON2_OFFS, 0x00); - up_serialout(priv, UART_XOFF1_OFFS, 0x00); - up_serialout(priv, UART_XOFF2_OFFS, 0x00); - up_serialout(priv, UART_EFR_OFFS, 0x00); - up_serialout(priv, UART_LCR_OFFS, 0x00); - up_mdelay(5); - - up_serialout(priv, UART_MDR_OFFS, MDR_UART_MODE); - up_mdelay(5); - - priv->regs.ier = up_inserial(priv, UART_IER_OFFS); - priv->regs.lcr = up_inserial(priv, UART_LCR_OFFS); -#ifdef CONFIG_UART_HWFLOWCONTROL - if (priv->flowcontrol) - { - priv->regs.efr = up_inserial(priv, UART_EFR_OFFS); - priv->regs.tcr = up_inserial(priv, UART_TCR_OFFS); - } -#endif - - up_disableuartint(priv, NULL); - -#ifdef UART_MULTIPLEX_REGS - up_serialout(priv, UART_LCR_OFFS, 0x00bf); -#endif - - up_serialout(priv, UART_EFR_OFFS, 0x0010); /* Unprotect enhanced control */ - -#ifdef UART_MULTIPLEX_REGS - priv->regs.lcr = 0x80; - up_serialout(priv, UART_LCR_OFFS, priv->regs.lcr); - //up_serialout(priv, UART_MCR_OFFS, 1 << 4); /* loopback */ -#endif - - up_serialout(priv, UART_TFCR_OFFS, 0); /* Reset to 0 */ - up_serialout(priv, UART_RFCR_OFFS, UART_FCR_RX_CLR); /* Clear RX fifo */ - up_serialout(priv, UART_TFCR_OFFS, UART_FCR_TX_CLR); /* Clear TX fifo */ - priv->regs.fcr = UART_FCR_FIFO_EN; - up_serialout(priv, UART_TFCR_OFFS, priv->regs.fcr); /* Enable RX/TX fifos */ - - up_disablebreaks(priv); - - /* Set the RX and TX trigger levels to the minimum */ - - priv->regs.fcr = (priv->regs.fcr & 0xffffff0f) | UART_FCR_FTL; - up_serialout(priv, UART_RFCR_OFFS, priv->regs.fcr); - - up_setrate(priv, priv->baud); - -#ifdef UART_MULTIPLEX_REGS - up_serialout(priv, UART_SCR_OFFS, 1); /* Disable DMA */ - priv->regs.lcr = (uint32_t)cval; /* Configure mode, return to THR/RHR */ -#else - priv->regs.lcr &= 0xffffffe0; /* clear original field, and... */ - priv->regs.lcr |= (uint32_t)cval; /* Set new bits in that field. */ -#endif - up_serialout(priv, UART_LCR_OFFS, priv->regs.lcr); - -#ifdef CONFIG_UART_HWFLOWCONTROL - if (priv->flowcontrol) - { - /* Set the FIFO level triggers for flow control - * Halt = 48 bytes, resume = 12 bytes - */ - - priv->regs.tcr = (priv->regs.tcr & 0xffffff00) | 0x0000003c; - up_serialout(priv, UART_TCR_OFFS, priv->regs.tcr); - - /* Enable RTS/CTS flow control */ - - priv->regs.efr |= 0x000000c0; - up_serialout(priv, UART_EFR_OFFS, priv->regs.efr); - } - else - { - /* Disable RTS/CTS flow control */ - - priv->regs.efr &= 0xffffff3f; - up_serialout(priv, UART_EFR_OFFS, priv->regs.efr); - } -#endif -#endif - return OK; -} - -/**************************************************************************** - * Name: up_shutdown - * - * Description: - * Disable the UART. This method is called when the serial port is closed - * - ****************************************************************************/ - -static void up_shutdown(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv; - up_disableuartint(priv, NULL); -} - -/**************************************************************************** - * Name: up_attach - * - * Description: - * Configure the UART to operation in interrupt driven mode. This method is - * called when the serial port is opened. Normally, this is just after the - * the setup() method is called, however, the serial console may operate in - * a non-interrupt driven mode during the boot phase. - * - * RX and TX interrupts are not enabled when by the attach method (unless the - * hardware supports multiple levels of interrupt enabling). The RX and TX - * interrupts are not enabled until the txint() and rxint() methods are called. - * - ****************************************************************************/ - -static int up_attach(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - int ret; - - /* Attach and enable the IRQ */ - - ret = irq_attach(priv->irq, up_interrupt); - if (ret == OK) - { - /* Enable the interrupt (RX and TX interrupts are still disabled - * in the UART - */ - - up_enable_irq(priv->irq); - } - - return ret; -} - -/**************************************************************************** - * Name: up_detach - * - * Description: - * Detach UART interrupts. This method is called when the serial port is - * closed normally just before the shutdown method is called. The exception is - * the serial console which is never shutdown. - * - ****************************************************************************/ - -static void up_detach(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - up_disable_irq(priv->irq); - irq_detach(priv->irq); -} - -/**************************************************************************** - * Name: up_interrupt - * - * Description: - * This is the UART interrupt handler. It will be invoked - * when an interrupt received on the 'irq' It should call - * uart_transmitchars or uart_receivechar to perform the - * appropriate data transfers. The interrupt handling logic\ - * must be able to map the 'irq' number into the approprite - * uart_dev_s structure in order to call these functions. - * - ****************************************************************************/ - -static int up_interrupt(int irq, void *context) -{ - struct uart_dev_s *dev = NULL; - struct up_dev_s *priv; - volatile uint32_t cause; - - if (g_irdapriv.irq == irq) - { - dev = &g_irdaport; - } - else if (g_modempriv.irq == irq) - { - dev = &g_modemport; - } - else - { - PANIC(); - } - priv = (struct up_dev_s *)dev->priv; - - cause = up_inserial(priv, UART_ISR_OFFS) & 0x0000003f; - - if ((cause & 0x0000000c) == 0x0000000c) - { - uint32_t ier_val = 0; - - /* Is this an interrupt from the IrDA UART? */ - - if (irq == UART_IRQ_IRDA) - { - /* Save the currently enabled IrDA UART interrupts - * so that we can restore the IrDA interrupt state - * below. - */ - - ier_val = up_inserial(priv, UART_IER_OFFS); - - /* Then disable all IrDA UART interrupts */ - - up_serialout(priv, UART_IER_OFFS, 0); - } - - /* Receive characters from the RX fifo */ - -#ifdef CONFIG_SERCOMM_CONSOLE - if (priv->sercomm) - { - sercomm_recvchars(dev); - } - else -#endif - { - uart_recvchars(dev); - } - - /* read UART_RHR to clear int condition - * toss = up_inserialchar(priv,&status); - */ - - /* Is this an interrupt from the IrDA UART? */ - - if (irq == UART_IRQ_IRDA) - { - /* Restore the IrDA UART interrupt enables */ - - up_serialout(priv, UART_IER_OFFS, ier_val); - } - } - else if ((cause & 0x0000000c) == 0x00000004) - { -#ifdef CONFIG_SERCOMM_CONSOLE - if (priv->sercomm) - { - sercomm_recvchars(dev); - } - else -#endif - { - uart_recvchars(dev); - } - } - - if ((cause & 0x00000002) != 0) - { -#ifdef CONFIG_SERCOMM_CONSOLE - if (priv->sercomm) - { - sercomm_xmitchars(dev); - } - else -#endif - { - uart_xmitchars(dev); - } - } - - return OK; -} - -/**************************************************************************** - * Name: up_ioctl - * - * Description: - * All ioctl calls will be routed through this method - * - ****************************************************************************/ - -static int up_ioctl(struct file *filep, int cmd, unsigned long arg) -{ - struct inode *inode = filep->f_inode; - struct uart_dev_s *dev = inode->i_private; - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - int ret = OK; - - switch (cmd) - { -#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT - case TIOCSERGSTRUCT: - { - struct up_dev_s *user = (struct up_dev_s *)arg; - if (!user) - { - ret = -EINVAL; - } - else - { - memcpy(user, dev, sizeof(struct up_dev_s)); - } - } - break; -#endif - - case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ - { - irqstate_t flags = enter_critical_section(); - up_enablebreaks(priv); - leave_critical_section(flags); - } - break; - - case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ - { - irqstate_t flags; - flags = enter_critical_section(); - up_disablebreaks(priv); - leave_critical_section(flags); - } - break; - - default: - ret = -ENOTTY; - break; - } - - return ret; -} - -/**************************************************************************** - * Name: up_receive - * - * Description: - * Called (usually) from the interrupt level to receive one character from - * the UART. Error bits associated with the receipt are provided in the - * the return 'status'. - * - ****************************************************************************/ - -static int up_receive(struct uart_dev_s *dev, unsigned int *status) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - uint32_t rhr; - uint32_t lsr; - - /* Construct a 16bit status word that uses the high byte to - * hold the status bits associated with framing,parity,break - * and a low byte that holds error bits of LSR for - * conditions such as overflow, etc. - */ - - rhr = up_inserial(priv, UART_RHR_OFFS); - lsr = up_inserial(priv, UART_LSR_OFFS); - - *status = (unsigned int)((rhr & 0x0000ff00) | (lsr & 0x000000ff)); - - return rhr & 0x000000ff; -} - -/**************************************************************************** - * Name: up_rxint - * - * Description: - * Call to enable or disable RX interrupts - * - ****************************************************************************/ - -static void up_rxint(struct uart_dev_s *dev, bool enable) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - if (enable) - { -#ifndef CONFIG_SUPPRESS_SERIAL_INTS - priv->regs.ier |= UART_IER_RECVINT; - up_serialout(priv, UART_IER_OFFS, priv->regs.ier); -#endif - } - else - { - priv->regs.ier &= ~UART_IER_RECVINT; - up_serialout(priv, UART_IER_OFFS, priv->regs.ier); - } -} - -/**************************************************************************** - * Name: up_rxavailable - * - * Description: - * Return true if the receive fifo is not empty - * - ****************************************************************************/ - -static bool up_rxavailable(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - return up_inserial(priv, UART_LSR_OFFS) & UART_RX_FIFO_NOEMPTY; -} - -/**************************************************************************** - * Name: up_send - * - * Description: - * This method will send one byte on the UART - * - ****************************************************************************/ - -static void up_send(struct uart_dev_s *dev, int ch) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - up_serialout(priv, UART_THR_OFFS, (uint8_t)ch); -} - -/**************************************************************************** - * Name: up_txint - * - * Description: - * Call to enable or disable TX interrupts - * - ****************************************************************************/ - -static void up_txint(struct uart_dev_s *dev, bool enable) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - if (enable) - { -#ifndef CONFIG_SUPPRESS_SERIAL_INTS - priv->regs.ier |= UART_IER_XMITINT; - up_serialout(priv, UART_IER_OFFS, priv->regs.ier); -#endif - } - else - { - priv->regs.ier &= ~UART_IER_XMITINT; - up_serialout(priv, UART_IER_OFFS, priv->regs.ier); - } -} - -/**************************************************************************** - * Name: up_txready - * - * Description: - * Return true if the tranmsit fifo is not full - * - ****************************************************************************/ - -static bool up_txready(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - return (up_inserial(priv, UART_SSR_OFFS) & UART_SSR_TXFULL) == 0; -} - -/**************************************************************************** - * Name: up_txempty - * - * Description: - * Return true if the transmit fifo is empty - * - ****************************************************************************/ - -static bool up_txempty(struct uart_dev_s *dev) -{ - struct up_dev_s *priv = (struct up_dev_s *)dev->priv; - return (up_inserial(priv, UART_LSR_OFFS) & UART_LSR_TREF) != 0; -} - -/**************************************************************************** - * Public Funtions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_earlyserialinit - * - * Description: - * Performs the low level UART initialization early in - * debug so that the serial console will be available - * during bootup. This must be called before up_serialinit. - * - ****************************************************************************/ - -void up_earlyserialinit(void) -{ - up_disableuartint(TTYS0_DEV.priv, NULL); - up_disableuartint(TTYS1_DEV.priv, NULL); - - CONSOLE_DEV.isconsole = true; - up_setup(&CONSOLE_DEV); -} - -/**************************************************************************** - * Name: up_serialinit - * - * Description: - * Register serial console and serial ports. This assumes - * that up_earlyserialinit was called previously. - * - ****************************************************************************/ - -void up_serialinit(void) -{ -#ifdef CONFIG_SERCOMM_CONSOLE - ((struct up_dev_s *)TTYS0_DEV.priv)->sercomm = true; - (void)sercomm_register("/dev/console", &TTYS0_DEV); - (void)uart_register("/dev/ttyS0", &TTYS1_DEV); -#else - (void)uart_register("/dev/console", &CONSOLE_DEV); - (void)uart_register("/dev/ttyS0", &TTYS0_DEV); - (void)uart_register("/dev/ttyS1", &TTYS1_DEV); -#endif -} - -/**************************************************************************** - * Name: up_putc - * - * Description: - * Provide priority, low-level access to support OS debug - * writes - * - ****************************************************************************/ - -int up_putc(int ch) -{ - struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv; - uint16_t ier; - - up_disableuartint(priv, &ier); - up_waittxready(priv); - up_serialout(priv, UART_THR_OFFS, (uint8_t)ch); - - /* Check for LF */ - - if (ch == '\n') - { - /* Add CR */ - - up_waittxready(priv); - up_serialout(priv, UART_THR_OFFS, '\r'); - } - - up_waittxready(priv); - up_restoreuartint(priv, ier); - return ch; -} - diff --git a/arch/arm/src/calypso/calypso_spi.c b/arch/arm/src/calypso/calypso_spi.c deleted file mode 100644 index 36727927c4..0000000000 --- a/arch/arm/src/calypso/calypso_spi.c +++ /dev/null @@ -1,314 +0,0 @@ -/**************************************************************************** - * arch/arm/src/calypso/calypso_spi.c - * SPI driver for TI Calypso - * - * Copyright (C) 2010 Harald Welte - * Copyright (C) 2011 Stefan Richter - * - * Part of this source code is derivated from Osmocom-BB project and was - * relicensed as BSD with permission from original authors. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#include -#include - -#include -#include -#include -#include -#include - -#include "up_arch.h" -#include "calypso_spi.h" - -#warning "MOST OF SPI API IS INCOMPLETE! (Wrapper around Osmocom driver)" -extern void spi_init(void); -extern int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din); - -#ifndef CONFIG_SPI_EXCHANGE -#error "Calypso HW only supports exchange. Enable CONFIG_SPI_EXCHANGE!" -#endif - -struct calypso_spidev_s -{ - struct spi_dev_s spidev; /* External driver interface */ - int nbits; /* Number of transfered bits */ - sem_t exclsem; /* Supports mutually exclusive access */ -}; - -static int spi_lock(FAR struct spi_dev_s *dev, bool lock) -{ - struct calypso_spidev_s *priv = (struct calypso_spidev_s *)dev; - - if (lock) - { - /* Take the semaphore (perhaps waiting) */ - - while (sem_wait(&priv->exclsem) != 0) - { - /* The only case that an error should occur here is if the wait - * was awakened by a signal. - */ - - DEBUGASSERT(errno == EINTR); - } - } - else - { - (void)sem_post(&priv->exclsem); - } - - return OK; -} - -/* STUBS! */ - -static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, - bool selected) -{ -} - -static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) -{ - return frequency; -} - -static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) -{ -} - -/* Osmocom wrapper */ - -static void spi_setbits(FAR struct spi_dev_s *dev, int nbits) -{ - ((FAR struct calypso_spidev_s *)dev)->nbits = nbits; -} - -static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer, - FAR void *rxbuffer, size_t nwords) -{ - FAR struct calypso_spidev_s *priv = (FAR struct calypso_spidev_s *)dev; - size_t i; - - for (i = 0; i < nwords; i++) - { - spi_xfer(0, priv->nbits, txbuffer + i, rxbuffer + i); - } -} - -static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd) -{ - uint16_t buf = wd; - spi_exchange(dev, &buf, &buf, 1); - return buf; -} - -static const struct spi_ops_s g_spiops = -{ - .lock = spi_lock, - .select = spi_select, - .setfrequency = spi_setfrequency, - .setmode = spi_setmode, - .setbits = spi_setbits, -#ifdef CONFIG_SPI_HWFEATURES - .hwfeatures = 0, -#endif - .status = 0, -#ifdef CONFIG_SPI_CMDDATA - .cmddata = 0, -#endif - .send = spi_send, -#ifdef CONFIG_SPI_EXCHANGE - .exchange = spi_exchange, -#else - .sndblock = spi_sndblock, - .recvblock = spi_recvblock, -#endif - .registercallback = 0, -}; - -static struct calypso_spidev_s g_spidev = -{ - .spidev = { &g_spiops }, - .nbits = 0, - .exclsem = SEM_INITIALIZER(1) -}; - -void spi_init(void) -{ - putreg16(SPI_SET1_EN_CLK | SPI_SET1_WR_IRQ_DIS | SPI_SET1_RDWR_IRQ_DIS, - SPI_REG(REG_SET1)); - - putreg16(0x0001, SPI_REG(REG_SET2)); -} - -int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din) -{ - uint8_t bytes_per_xfer; - uint8_t reg_status, reg_ctrl = 0; - uint32_t tmp; - - if (bitlen == 0) - { - return 0; - } - - if (bitlen > 32) - { - return -1; - } - - if (dev_idx > 4) - { - return -1; - } - - bytes_per_xfer = bitlen / 8; - if (bitlen % 8) - { - bytes_per_xfer ++; - } - - reg_ctrl |= (bitlen - 1) << SPI_CTRL_NB_SHIFT; - reg_ctrl |= (dev_idx & 0x7) << SPI_CTRL_AD_SHIFT; - - if (bitlen <= 8) - { - tmp = *(uint8_t *)dout; - tmp <<= 24 + (8-bitlen); /* align to MSB */ - } - else if (bitlen <= 16) - { - tmp = *(uint16_t *)dout; - tmp <<= 16 + (16-bitlen); /* align to MSB */ - } - else - { - tmp = *(uint32_t *)dout; - tmp <<= (32-bitlen); /* align to MSB */ - } - - spiinfo("spi_xfer(dev_idx=%u, bitlen=%u, data_out=0x%08x): ", - dev_idx, bitlen, tmp); - - /* fill transmit registers */ - - putreg16(tmp >> 16, SPI_REG(REG_TX_MSB)); - putreg16(tmp & 0xffff, SPI_REG(REG_TX_LSB)); - - /* initiate transfer */ - - if (din) - { - reg_ctrl |= SPI_CTRL_RDWR; - } - else - { - reg_ctrl |= SPI_CTRL_WR; - } - - putreg16(reg_ctrl, SPI_REG(REG_CTRL)); - spiinfo("reg_ctrl=0x%04x ", reg_ctrl); - - /* wait until the transfer is complete */ - - while (1) - { - reg_status = getreg16(SPI_REG(REG_STATUS)); - spiinfo("status=0x%04x ", reg_status); - if (din && (reg_status & SPI_STATUS_RE)) - { - break; - } - else if (reg_status & SPI_STATUS_WE) - { - break; - } - } - - /* FIXME: calibrate how much delay we really need (seven 13MHz cycles) */ - - usleep(1000); - - if (din) - { - tmp = getreg16(SPI_REG(REG_RX_MSB)) << 16; - tmp |= getreg16(SPI_REG(REG_RX_LSB)); - spiinfo("data_in=0x%08x ", tmp); - - if (bitlen <= 8) - { - *(uint8_t *)din = tmp & 0xff; - } - else if (bitlen <= 16) - { - *(uint16_t *)din = tmp & 0xffff; - } - else - { - *(uint32_t *)din = tmp; - } - } - - spiinfo("\n"); - - return 0; -} - -/**************************************************************************** - * Name: calypso_spibus_initialize - * - * Description: - * Initialize the selected SPI port - * - * Input Parameter: - * Port number (for hardware that has mutiple SPI interfaces) - * - * Returned Value: - * Valid SPI device structure reference on succcess; a NULL on failure - * - ****************************************************************************/ - -FAR struct spi_dev_s *calypso_spibus_initialize(int port) -{ - switch (port) - { - case 0: /* SPI master device */ - spi_init(); - return (FAR struct spi_dev_s *)&g_spidev; - - case 1: /* uWire device */ - return NULL; - - default: - return NULL; - } -} diff --git a/arch/arm/src/calypso/calypso_spi.h b/arch/arm/src/calypso/calypso_spi.h deleted file mode 100644 index 70ca2ad9d0..0000000000 --- a/arch/arm/src/calypso/calypso_spi.h +++ /dev/null @@ -1,59 +0,0 @@ -#ifndef ___ARCH_ARM_SRC_CALYPSO_CALYPSO_SPI_H -#define ___ARCH_ARM_SRC_CALYPSO_CALYPSO_SPI_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define BASE_ADDR_SPI 0xfffe3000 -#define SPI_REG(n) (BASE_ADDR_SPI+(n)) - -#define SPI_SET1_EN_CLK (1 << 0) -#define SPI_SET1_WR_IRQ_DIS (1 << 4) -#define SPI_SET1_RDWR_IRQ_DIS (1 << 5) - -#define SPI_CTRL_RDWR (1 << 0) -#define SPI_CTRL_WR (1 << 1) -#define SPI_CTRL_NB_SHIFT 2 -#define SPI_CTRL_AD_SHIFT 7 - -#define SPI_STATUS_RE (1 << 0) /* Read End */ -#define SPI_STATUS_WE (1 << 1) /* Write End */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -enum spi_regs -{ - REG_SET1 = 0x00, - REG_SET2 = 0x02, - REG_CTRL = 0x04, - REG_STATUS = 0x06, - REG_TX_LSB = 0x08, - REG_TX_MSB = 0x0a, - REG_RX_LSB = 0x0c, - REG_RX_MSB = 0x0e, -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: calypso_spibus_initialize - * - * Description: - * Initialize the selected SPI port - * - * Input Parameter: - * Port number (for hardware that has mutiple SPI interfaces) - * - * Returned Value: - * Valid SPI device structure reference on succcess; a NULL on failure - * - ****************************************************************************/ - -FAR struct spi_dev_s *calypso_spibus_initialize(int port); - -#endif /* ___ARCH_ARM_SRC_CALYPSO_CALYPSO_SPI_H */ diff --git a/arch/arm/src/calypso/calypso_timer.c b/arch/arm/src/calypso/calypso_timer.c deleted file mode 100644 index 86626c5de6..0000000000 --- a/arch/arm/src/calypso/calypso_timer.c +++ /dev/null @@ -1,227 +0,0 @@ -/**************************************************************************** - * arch/arm/src/calypso/calypso_timer.c - * Calypso DBB internal Timer Driver - * - * (C) 2010 by Harald Welte - * (C) 2011 by Stefan Richter - * - * This source code is derivated from Osmocom-BB project and was - * relicensed as BSD with permission from original authors. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include - -#include "up_arch.h" - -#define BASE_ADDR_TIMER 0xfffe3800 -#define TIMER2_OFFSET 0x3000 - -#define TIMER_REG(n, m) (((n)-1) ? (BASE_ADDR_TIMER + TIMER2_OFFSET + (m)) : (BASE_ADDR_TIMER + (m))) - -enum timer_reg -{ - CNTL_TIMER = 0x00, - LOAD_TIMER = 0x02, - READ_TIMER = 0x04, -}; - -enum timer_ctl -{ - CNTL_START = (1 << 0), - CNTL_AUTO_RELOAD = (1 << 1), - CNTL_CLOCK_ENABLE = (1 << 5), -}; - -/* Regular Timers (1 and 2) */ - -void hwtimer_enable(int num, int on) -{ - uint8_t ctl; - - if (num < 1 || num > 2) - { - printf("Unknown timer %d\n", num); - return; - } - - ctl = getreg8(TIMER_REG(num, CNTL_TIMER)); - if (on) - { - ctl |= CNTL_START | CNTL_CLOCK_ENABLE; - } - else - { - ctl &= ~CNTL_START; - } - - putreg8(ctl, TIMER_REG(num, CNTL_TIMER)); -} - -void hwtimer_config(int num, uint8_t pre_scale, int auto_reload) -{ - uint8_t ctl; - - ctl = (pre_scale & 0x7) << 2; - if (auto_reload) - ctl |= CNTL_AUTO_RELOAD; - - putreg8(ctl, TIMER_REG(num, CNTL_TIMER)); -} - -void hwtimer_load(int num, uint16_t val) -{ - putreg16(val, TIMER_REG(num, LOAD_TIMER)); -} - -uint16_t hwtimer_read(int num) -{ - uint8_t ctl = getreg8(TIMER_REG(num, CNTL_TIMER)); - - /* Somehow a read results in an abort */ - - if ((ctl & (CNTL_START | CNTL_CLOCK_ENABLE)) != (CNTL_START | CNTL_CLOCK_ENABLE)) - { - return 0xffff; - } - - return getreg16(TIMER_REG(num, READ_TIMER)); -} - -/**************************************************************************** - * Watchdog Timer - ****************************************************************************/ - -#define BASE_ADDR_WDOG 0xfffff800 -#define WDOG_REG(m) (BASE_ADDR_WDOG + m) - -enum wdog_reg -{ - WD_CNTL_TIMER = CNTL_TIMER, - WD_LOAD_TIMER = LOAD_TIMER, - WD_READ_TIMER = 0x02, - WD_MODE = 0x04, -}; - -enum wdog_ctl -{ - WD_CTL_START = (1 << 7), - WD_CTL_AUTO_RELOAD = (1 << 8) -}; - -enum wdog_mode -{ - WD_MODE_DIS_ARM = 0xF5, - WD_MODE_DIS_CONFIRM = 0xA0, - WD_MODE_ENABLE = (1 << 15) -}; - -#define WD_CTL_PRESCALE(value) (((value)&0x07) << 9) - -static void wdog_irq(__unused enum irq_nr nr) -{ - puts("=> WATCHDOG\n"); -} - -void wdog_enable(int on) -{ - if (!on) - { - putreg16(WD_MODE_DIS_ARM, WDOG_REG(WD_MODE)); - putreg16(WD_MODE_DIS_CONFIRM, WDOG_REG(WD_MODE)); - } -} - -void wdog_reset(void) -{ - /* Enable watchdog */ - - putreg16(WD_MODE_ENABLE, WDOG_REG(WD_MODE)); - - /* Force expiration */ - - putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER)); - putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER)); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: up_timerisr - * - * Description: - * The timer ISR will perform a variety of services for - * various portions of the systems. - * - ****************************************************************************/ - -int up_timerisr(int irq, uint32_t *regs) -{ - /* Process timer interrupt */ - - sched_process_timer(); - return 0; -} - -/**************************************************************************** - * Function: up_timer_initialize - * - * Description: - * Setup Calypso HW timer 2 to cause system ticks. - * - * This function is called during start-up to initialize - * the timer interrupt. - * - ****************************************************************************/ - -void up_timer_initialize(void) -{ - up_disable_irq(IRQ_SYSTIMER); - - /* The timer runs at 13MHz / 32, i.e. 406.25kHz */ - /* 4062 ticks until expiry yields 100Hz interrupt */ - - hwtimer_load(2, 4062); - hwtimer_config(2, 0, 1); - hwtimer_enable(2, 1); - - /* Attach and enable the timer interrupt */ - - irq_attach(IRQ_SYSTIMER, (xcpt_t)up_timerisr); - up_enable_irq(IRQ_SYSTIMER); -} diff --git a/arch/arm/src/calypso/calypso_uwire.c b/arch/arm/src/calypso/calypso_uwire.c deleted file mode 100644 index fe2c33b7cc..0000000000 --- a/arch/arm/src/calypso/calypso_uwire.c +++ /dev/null @@ -1,161 +0,0 @@ -/**************************************************************************** - * arch/arm/src/calypso/calypso_uwire.c - * Driver for Calypso uWire Master Controller - * - * (C) 2010 by Sylvain Munaut - * - * This source code is derivated from Osmocom-BB project and was - * relicensed as BSD with permission from original authors. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include "up_arch.h" - -#define BASE_ADDR_UWIRE 0xfffe4000 -#define UWIRE_REG(n) (BASE_ADDR_UWIRE+(n)) - -enum uwire_regs -{ - REG_DATA = 0x00, - REG_CSR = 0x02, - REG_SR1 = 0x04, - REG_SR2 = 0x06, - REG_SR3 = 0x08, -}; - -#define UWIRE_CSR_BITS_RD(n) (((n) & 0x1f) << 0) -#define UWIRE_CSR_BITS_WR(n) (((n) & 0x1f) << 5) -#define UWIRE_CSR_IDX(n) (((n) & 3) << 10) -#define UWIRE_CSR_CS_CMD (1 << 12) -#define UWIRE_CSR_START (1 << 13) -#define UWIRE_CSR_CSRB (1 << 14) -#define UWIRE_CSR_RDRB (1 << 15) - -#define UWIRE_CSn_EDGE_RD (1 << 0) /* 1=falling 0=rising */ -#define UWIRE_CSn_EDGE_WR (1 << 1) /* 1=falling 0=rising */ -#define UWIRE_CSn_CS_LVL (1 << 2) -#define UWIRE_CSn_FRQ_DIV2 (0 << 3) -#define UWIRE_CSn_FRQ_DIV4 (1 << 3) -#define UWIRE_CSn_FRQ_DIV8 (2 << 3) -#define UWIRE_CSn_CKH - -#define UWIRE_CSn_SHIFT(n) (((n) & 1) ? 6 : 0) -#define UWIRE_CSn_REG(n) (((n) & 2) ? REG_SR2 : REG_SR1) - -#define UWIRE_SR3_CLK_EN (1 << 0) -#define UWIRE_SR3_CLK_DIV2 (0 << 1) -#define UWIRE_SR3_CLK_DIV4 (1 << 1) -#define UWIRE_SR3_CLK_DIV7 (2 << 1) -#define UWIRE_SR3_CLK_DIV10 (3 << 1) - -static inline void _uwire_wait(int mask, int val) -{ - while ((getreg16(UWIRE_REG(REG_CSR)) & mask) != val); -} - -void uwire_init(void) -{ - putreg16(UWIRE_SR3_CLK_EN | UWIRE_SR3_CLK_DIV2, UWIRE_REG(REG_SR3)); - - /* FIXME only init CS0 for now */ - - putreg16(((UWIRE_CSn_CS_LVL | UWIRE_CSn_FRQ_DIV2) << UWIRE_CSn_SHIFT(0)), - UWIRE_REG(UWIRE_CSn_REG(0))); - putreg16(UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD, UWIRE_REG(REG_CSR)); - _uwire_wait(UWIRE_CSR_CSRB, 0); -} - -int uwire_xfer(int cs, int bitlen, const void *dout, void *din) -{ - uint16_t tmp = 0; - - if (bitlen <= 0 || bitlen > 16) - return -1; - - if (cs < 0 || cs > 4) - return -1; - - /* FIXME uwire_init always selects CS0 for now */ - - _info("uwire_xfer(dev_idx=%u, bitlen=%u\n", cs, bitlen); - - /* select the chip */ - - putreg16(UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD, UWIRE_REG(REG_CSR)); - _uwire_wait(UWIRE_CSR_CSRB, 0); - - if (dout) - { - if (bitlen <= 8) - tmp = *(uint8_t *)dout; - else if (bitlen <= 16) - tmp = *(uint16_t *)dout; - - tmp <<= 16 - bitlen; /* align to MSB */ - putreg16(tmp, UWIRE_REG(REG_DATA)); - _info(", data_out=0x%04hx", tmp); - } - - tmp = (dout ? UWIRE_CSR_BITS_WR(bitlen) : 0) | - (din ? UWIRE_CSR_BITS_RD(bitlen) : 0) | - UWIRE_CSR_START; - putreg16(tmp, UWIRE_REG(REG_CSR)); - _uwire_wait(UWIRE_CSR_CSRB, 0); - - if (din) - { - _uwire_wait(UWIRE_CSR_RDRB, UWIRE_CSR_RDRB); - - tmp = getreg16(UWIRE_REG(REG_DATA)); - _info(", data_in=0x%08x", tmp); - - if (bitlen <= 8) - *(uint8_t *)din = tmp & 0xff; - else if (bitlen <= 16) - *(uint16_t *)din = tmp & 0xffff; - } - - /* unselect the chip */ - - putreg16(UWIRE_CSR_IDX(0) | 0, UWIRE_REG(REG_CSR)); - _uwire_wait(UWIRE_CSR_CSRB, 0); - - _info(")\n"); - - return 0; -} diff --git a/arch/arm/src/calypso/chip.h b/arch/arm/src/calypso/chip.h deleted file mode 100644 index bea381cc38..0000000000 --- a/arch/arm/src/calypso/chip.h +++ /dev/null @@ -1,211 +0,0 @@ -/**************************************************************************** - * calypso/chip.h - * - * Copyright (C) 2011 Stefan Richter. All rights reserved. - * Author: Stefan Richter - * - * based on: c5471/chip.h - * Copyright (C) 2007 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name Gregory Nutt nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_CALYPSO_CHIP_H -#define __ARCH_ARM_SRC_CALYPSO_CHIP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* UARTs ********************************************************************/ - -#define UART_IRDA_BASE 0xffff5000 -#define UART_MODEM_BASE 0xffff5800 -#define UART_UIR 0xffff6000 -#define UARTn_IO_RANGE 0x00000800 - -/* Common UART Registers. Expressed as offsets from the BASE address */ - -#define UART_RHR_OFFS 0x00000000 /* Rcv Holding Register */ -#define UART_THR_OFFS 0x00000000 /* Xmit Holding Register */ -#define UART_FCR_OFFS 0x00000002 /* FIFO Control Register */ -#define UART_RFCR_OFFS 0x00000002 /* Rcv FIFO Control Register */ -#define UART_TFCR_OFFS 0x00000002 /* Xmit FIFO Control Register */ -#define UART_SCR_OFFS 0x00000010 /* Status Control Register */ -#define UART_LCR_OFFS 0x00000003 /* Line Control Register */ -#define UART_LSR_OFFS 0x00000005 /* Line Status Register */ -#define UART_SSR_OFFS 0x00000011 /* Supplementary Status Register */ -#define UART_MCR_OFFS 0x00000004 /* Modem Control Register */ -#define UART_MSR_OFFS 0x00000006 /* Modem Status Register */ -#define UART_IER_OFFS 0x00000001 /* Interrupt Enable Register */ -#define UART_ISR_OFFS 0x00000002 /* Interrupt Status Register */ -#define UART_EFR_OFFS 0x00000002 /* Enhanced Feature Register */ -#define UART_XON1_OFFS 0x00000004 /* XON1 Character Register */ -#define UART_XON2_OFFS 0x00000005 /* XON2 Character Register */ -#define UART_XOFF1_OFFS 0x00000006 /* XOFF1 Character Register */ -#define UART_XOFF2_OFFS 0x00000007 /* XOFF2 Character Register */ -#define UART_SPR_OFFS 0x00000007 /* Scratch-pad Register */ -#define UART_DIV_LOW_OFFS 0x00000000 /* Divisor for baud generation */ -#define UART_DIV_HIGH_OFFS 0x00000001 -#define UART_TCR_OFFS 0x00000006 /* Transmission Control Register */ -#define UART_TLR_OFFS 0x00000007 /* Trigger Level Register */ -#define UART_MDR_OFFS 0x00000008 /* Mode Definition Register */ - -/* UART Settings ************************************************************/ - -/* Miscellaneous UART settings. */ - -#define UART_REGISTER_BITS 8 -#define UART_IRQ_MODEM IRQ_UART_MODEM -#define UART_IRQ_IRDA IRQ_UART_IRDA - -#define UART_RX_FIFO_NOEMPTY 0x00000001 -#define UART_SSR_TXFULL 0x00000001 -#define UART_LSR_TREF 0x00000020 - -#define UART_XMIT_FIFO_SIZE 64 -#define UART_IRDA_XMIT_FIFO_SIZE 64 - -/* UART_LCR Register */ - /* Bits 31-7: Reserved */ -#define UART_LCR_BOC 0x00000040 /* Bit 6: Break Control */ - /* Bit 5: Parity Type 2 */ -#define UART_LCR_PAREVEN 0x00000010 /* Bit 4: Parity Type 1 */ -#define UART_LCR_PARODD 0x00000000 -#define UART_LCR_PARMARK 0x00000010 -#define UART_LCR_PARSPACE 0x00000011 -#define UART_LCR_PAREN 0x00000008 /* Bit 3: Paity Enable */ -#define UART_LCR_PARDIS 0x00000000 -#define UART_LCR_2STOP 0x00000004 /* Bit 2: Number of stop bits */ -#define UART_LCR_1STOP 0x00000000 -#define UART_LCR_5BITS 0x00000000 /* Bits 0-1: Word-length */ -#define UART_LCR_6BITS 0x00000001 -#define UART_LCR_7BITS 0x00000002 -#define UART_LCR_8BITS 0x00000003 - -#define UART_FCR_FTL 0x000000f0 -#define UART_FCR_FIFO_EN 0x00000001 -#define UART_FCR_TX_CLR 0x00000002 -#define UART_FCR_RX_CLR 0x00000004 - -#define UART_IER_RECVINT 0x00000001 -#define UART_IER_XMITINT 0x00000002 -#define UART_IER_LINESTSINT 0x00000004 -#define UART_IER_MODEMSTSINT 0x00000008 /* IrDA UART only */ -#define UART_IER_XOFFINT 0x00000020 -#define UART_IER_RTSINT 0x00000040 /* IrDA UART only */ -#define UART_IER_CTSINT 0x00000080 /* IrDA UART only */ -#define UART_IER_INTMASK 0x000000ff - -#define BAUD_115200 0x00000007 -#define BAUD_57600 0x00000014 -#define BAUD_38400 0x00000021 -#define BAUD_19200 0x00000006 -#define BAUD_9600 0x0000000C -#define BAUD_4800 0x00000018 -#define BAUD_2400 0x00000030 -#define BAUD_1200 0x00000060 - -#define MDR_UART_MODE 0x00000000 /* Both IrDA and Modem UARTs */ -#define MDR_SIR_MODE 0x00000001 /* IrDA UART only */ -#define MDR_AUTOBAUDING_MODE 0x00000002 /* Modem UART only */ -#define MDR_RESET_MODE 0x00000007 /* Both IrDA and Modem UARTs */ - -/* SPI **********************************************************************/ - -#define MAX_SPI 3 - -#define SPI_REGISTER_BASE 0xffff2000 - -/* ARMIO ********************************************************************/ -/* Timers / Watchdog ********************************************************/ - -#define C5471_TIMER0_CTRL 0xffff2a00 -#define C5471_TIMER0_CNT 0xffff2a04 -#define C5471_TIMER1_CTRL 0xffff2b00 -#define C5471_TIMER1_CNT 0xffff2b04 -#define C5471_TIMER2_CTRL 0xffff2c00 -#define C5471_TIMER2_CNT 0xffff2c04 - -/* Interrupts ***************************************************************/ - -#define HAVE_SRC_IRQ_BIN_REG 0 - -#define INT_FIRST_IO 0xffff2d00 -#define INT_IO_RANGE 0x5C - -#define IT_REG 0xffff2d00 -#define MASK_IT_REG 0xffff2d04 -#define SRC_IRQ_REG 0xffff2d08 -#define SRC_FIQ_REG 0xffff2d0c -#define SRC_IRQ_BIN_REG 0xffff2d10 -#define INT_CTRL_REG 0xffff2d18 - -#define ILR_IRQ0_REG 0xffff2d1C /* 0-Timer 0 */ -#define ILR_IRQ1_REG 0xffff2d20 /* 1-Timer 1 */ -#define ILR_IRQ2_REG 0xffff2d24 /* 2-Timer 2 */ -#define ILR_IRQ3_REG 0xffff2d28 /* 3-GPIO0 */ -#define ILR_IRQ4_REG 0xffff2d2c /* 4-Ethernet */ -#define ILR_IRQ5_REG 0xffff2d30 /* 5-KBGPIO[7:0] */ -#define ILR_IRQ6_REG 0xffff2d34 /* 6-Uart serial */ -#define ILR_IRQ7_REG 0xffff2d38 /* 7-Uart IRDA */ -#define ILR_IRQ8_REG 0xffff2d3c /* 8-KBGPIO[15:8] */ -#define ILR_IRQ9_REG 0xffff2d40 /* 9-GPIO3 */ -#define ILR_IRQ10_REG 0xffff2d44 /* 10-GPIO2 */ -#define ILR_IRQ11_REG 0xffff2d48 /* 11-I2C */ -#define ILR_IRQ12_REG 0xffff2d4c /* 12-GPIO1 */ -#define ILR_IRQ13_REG 0xffff2d50 /* 13-SPI */ -#define ILR_IRQ14_REG 0xffff2d54 /* 14-GPIO[19:4] */ -#define ILR_IRQ15_REG 0xffff2d58 /* 15-API */ - -/* CLKM *********************************************************************/ - -#define CLKM 0xffff2f00 -#define CLKM_CTL_RST 0xffff2f10 -#define CLKM_RESET 0xffff2f18 - -#define CLKM_RESET_EIM 0x00000008 -#define CLKM_EIM_CLK_STOP 0x00000010 -#define CLKM_CTL_RST_LEAD_RESET 0x00000000 -#define CLKM_CTL_RST_EXT_RESET 0x00000002 - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_CALYPSO_CHIP_H */ diff --git a/arch/arm/src/calypso/clock.c b/arch/arm/src/calypso/clock.c deleted file mode 100644 index 29dc2f8273..0000000000 --- a/arch/arm/src/calypso/clock.c +++ /dev/null @@ -1,230 +0,0 @@ -/**************************************************************************** - * arch/arm/src/calypso/clock.c - * Driver for Calypso clock management - * - * (C) 2010 by Harald Welte - * - * This source code is derivated from Osmocom-BB project and was - * relicensed as BSD with permission from original authors. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#include - -#include -#include - -//#define DEBUG -#include - -#include -#include - -#include "up_arch.h" - -#define REG_DPLL 0xffff9800 -#define DPLL_LOCK (1 << 0) -#define DPLL_BREAKLN (1 << 1) -#define DPLL_BYPASS_DIV_SHIFT 2 /* 2 bits */ -#define DPLL_PLL_ENABLE (1 << 4) -#define DPLL_PLL_DIV_SHIFT 5 /* 2 bits */ -#define DPLL_PLL_MULT_SHIFT 7 /* 5 bits */ -#define DPLL_TEST (1 << 12) -#define DPLL_IOB (1 << 13) /* Initialize on break */ -#define DPLL_IAI (1 << 14) /* Initialize after Idle */ - -#define BASE_ADDR_CLKM 0xfffffd00 -#define CLKM_REG(m) (BASE_ADDR_CLKM+(m)) - -enum clkm_reg -{ - CNTL_ARM_CLK = 0, - CNTL_CLK = 2, - CNTL_RST = 4, - CNTL_ARM_DIV = 8, -}; - -/* CNTL_ARM_CLK */ - -#define ARM_CLK_BIG_SLEEP (1 << 0) /* MCU Master Clock enabled? */ -#define ARM_CLK_CLKIN_SEL0 (1 << 1) /* MCU source clock (0 = DPLL output, 1 = VTCXO or CLKIN */ -#define ARM_CLK_CLKIN_SEL (1 << 2) /* 0 = VTCXO or 1 = CLKIN */ -#define ARM_CLK_MCLK_DIV5 (1 << 3) /* enable 1.5 or 2.5 division factor */ -#define ARM_CLK_MCLK_DIV_SHIFT 4 /* 3 bits */ -#define ARM_CLK_DEEP_POWER_SHIFT 8 -#define ARM_CLK_DEEP_SLEEP 12 - -/* CNTL_CLK */ -#define CLK_IRQ_CLK_DIS (1 << 0) /* IRQ clock control (0 always, 1 according ARM_MCLK_EN) */ -#define CLK_BRIDGE_CLK_DIS (1 << 1) -#define CLK_TIMER_CLK_DIS (1 << 2) -#define CLK_DPLL_DIS (1 << 3) /* 0: DPLL is not stopped during SLEEP */ -#define CLK_CLKOUT_EN (1 << 4) /* Enable CLKOUT output pins */ -#define CLK_EN_IDLE3_FLG (1 << 5) /* DSP idle flag control (1 = - * SAM/HOM register forced to HOM when DSP IDLE3) */ -#define CLK_VCLKOUT_DIV2 (1 << 6) /* 1: VCLKOUT-FR is divided by 2 */ -#define CLK_VTCXO_DIV2 (1 << 7) /* 1: VTCXO is dividied by 2 */ - -#define BASE_ADDR_MEMIF 0xfffffb00 -#define MEMIF_REG(x) (BASE_ADDR_MEMIF+(x)) - -enum memif_reg -{ - API_RHEA_CTL = 0x0e, - EXTRA_CONF = 0x10, -}; - -static void dump_reg16(uint32_t addr, char *name) -{ - printf("%s=0x%04x\n", name, getreg16(addr)); -} - -void calypso_clk_dump(void) -{ - dump_reg16(REG_DPLL, "REG_DPLL"); - dump_reg16(CLKM_REG(CNTL_ARM_CLK), "CNTL_ARM_CLK"); - dump_reg16(CLKM_REG(CNTL_CLK), "CNTL_CLK"); - dump_reg16(CLKM_REG(CNTL_RST), "CNTL_RST"); - dump_reg16(CLKM_REG(CNTL_ARM_DIV), "CNTL_ARM_DIV"); -} - -void calypso_pll_set(uint16_t inp) -{ - uint8_t mult = inp >> 8; - uint8_t div = inp & 0xff; - uint16_t reg = getreg16(REG_DPLL); - - reg &= ~0x0fe0; - reg |= (div & 0x3) << DPLL_PLL_DIV_SHIFT; - reg |= (mult & 0x1f) << DPLL_PLL_MULT_SHIFT; - reg |= DPLL_PLL_ENABLE; - - putreg16(reg, REG_DPLL); -} - -void calypso_reset_set(enum calypso_rst calypso_rst, int active) -{ - uint8_t reg = getreg8(CLKM_REG(CNTL_RST)); - - if (active) - reg |= calypso_rst; - else - reg &= ~calypso_rst; - - putreg8(reg, CLKM_REG(CNTL_RST)); -} - -int calypso_reset_get(enum calypso_rst calypso_rst) -{ - uint8_t reg = getreg8(CLKM_REG(CNTL_RST)); - - if (reg & calypso_rst) - return 1; - else - return 0; -} - -void calypso_clock_set(uint8_t vtcxo_div2, uint16_t inp, enum mclk_div mclk_div) -{ - uint16_t cntl_clock = getreg16(CLKM_REG(CNTL_CLK)); - uint16_t cntl_arm_clk = getreg16(CLKM_REG(CNTL_ARM_CLK)); - - /* First set the vtcxo_div2 */ - - cntl_clock &= ~CLK_VCLKOUT_DIV2; - if (vtcxo_div2) - cntl_clock |= CLK_VTCXO_DIV2; - else - cntl_clock &= ~CLK_VTCXO_DIV2; - - putreg16(cntl_clock, CLKM_REG(CNTL_CLK)); - - /* Then configure the MCLK divider */ - - cntl_arm_clk &= ~ARM_CLK_CLKIN_SEL0; - if (mclk_div & 0x80) - { - mclk_div &= ~0x80; - cntl_arm_clk |= ARM_CLK_MCLK_DIV5; - } - else - cntl_arm_clk &= ~ARM_CLK_MCLK_DIV5; - - cntl_arm_clk &= ~(0x7 << ARM_CLK_MCLK_DIV_SHIFT); - cntl_arm_clk |= (mclk_div << ARM_CLK_MCLK_DIV_SHIFT); - putreg16(cntl_arm_clk, CLKM_REG(CNTL_ARM_CLK)); - - /* Then finally set the PLL */ - - calypso_pll_set(inp); -} - -void calypso_mem_cfg(enum calypso_bank bank, uint8_t ws, - enum calypso_mem_width width, int we) -{ - putreg16((ws & 0x1f) | ((width & 3) << 5) | ((we & 1) << 7), - BASE_ADDR_MEMIF + bank); -} - -void calypso_bootrom(int enable) -{ - uint16_t conf = getreg16(MEMIF_REG(EXTRA_CONF)); - - conf |= (3 << 8); - - if (enable) - conf &= ~(1 << 9); - - putreg16(conf, MEMIF_REG(EXTRA_CONF)); -} - -void calypso_debugunit(int enable) -{ - uint16_t conf = getreg16(MEMIF_REG(EXTRA_CONF)); - - if (enable) - conf &= ~(1 << 11); - else - conf |= (1 << 11); - - putreg16(conf, MEMIF_REG(EXTRA_CONF)); -} - -#define REG_RHEA_CNTL 0xfffff900 -#define REG_API_CNTL 0xfffff902 -#define REG_ARM_RHEA 0xfffff904 - -void calypso_rhea_cfg(uint8_t fac0, uint8_t fac1, uint8_t timeout, - uint8_t ws_h, uint8_t ws_l, uint8_t w_en0, uint8_t w_en1) -{ - putreg16(fac0 | (fac1 << 4) | (timeout << 8), REG_RHEA_CNTL); - putreg16(ws_h | (ws_l << 5), REG_API_CNTL); - putreg16(w_en0 | (w_en1 << 1), REG_ARM_RHEA); -} diff --git a/configs/amber/hello/defconfig b/configs/amber/hello/defconfig index 7292bfeb9d..2dc6a34254 100644 --- a/configs/amber/hello/defconfig +++ b/configs/amber/hello/defconfig @@ -233,7 +233,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_16550_UART is not set diff --git a/configs/arduino-due/nsh/defconfig b/configs/arduino-due/nsh/defconfig index 1d50abd7e9..bc43e12c28 100644 --- a/configs/arduino-due/nsh/defconfig +++ b/configs/arduino-due/nsh/defconfig @@ -500,7 +500,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/arduino-mega2560/hello/defconfig b/configs/arduino-mega2560/hello/defconfig index 8907161516..95e74bd6c9 100644 --- a/configs/arduino-mega2560/hello/defconfig +++ b/configs/arduino-mega2560/hello/defconfig @@ -296,7 +296,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_16550_UART is not set diff --git a/configs/arduino-mega2560/nsh/defconfig b/configs/arduino-mega2560/nsh/defconfig index 6636c1d8ff..40cfb5458a 100644 --- a/configs/arduino-mega2560/nsh/defconfig +++ b/configs/arduino-mega2560/nsh/defconfig @@ -304,7 +304,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set diff --git a/configs/avr32dev1/nsh/defconfig b/configs/avr32dev1/nsh/defconfig index cbd3aa7c1a..5e2bffbca8 100644 --- a/configs/avr32dev1/nsh/defconfig +++ b/configs/avr32dev1/nsh/defconfig @@ -271,7 +271,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set diff --git a/configs/avr32dev1/ostest/defconfig b/configs/avr32dev1/ostest/defconfig index ea66ee4723..600c0191aa 100644 --- a/configs/avr32dev1/ostest/defconfig +++ b/configs/avr32dev1/ostest/defconfig @@ -270,7 +270,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_16550_UART is not set diff --git a/configs/bambino-200e/nsh/defconfig b/configs/bambino-200e/nsh/defconfig index 405b666585..729e7fdc65 100644 --- a/configs/bambino-200e/nsh/defconfig +++ b/configs/bambino-200e/nsh/defconfig @@ -501,7 +501,6 @@ CONFIG_TIMER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set CONFIG_SERIAL_REMOVABLE=y diff --git a/configs/c5471evm/httpd/defconfig b/configs/c5471evm/httpd/defconfig index 2816583ae1..c388a368c8 100644 --- a/configs/c5471evm/httpd/defconfig +++ b/configs/c5471evm/httpd/defconfig @@ -413,7 +413,6 @@ CONFIG_WATCHDOG_DEVPATH="/dev/watchdog0" # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/c5471evm/nettest/defconfig b/configs/c5471evm/nettest/defconfig index 989d3be0e8..729f8df76e 100644 --- a/configs/c5471evm/nettest/defconfig +++ b/configs/c5471evm/nettest/defconfig @@ -406,7 +406,6 @@ CONFIG_WATCHDOG_DEVPATH="/dev/watchdog0" # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/c5471evm/nsh/defconfig b/configs/c5471evm/nsh/defconfig index eae7f1f095..a7d595285f 100644 --- a/configs/c5471evm/nsh/defconfig +++ b/configs/c5471evm/nsh/defconfig @@ -414,7 +414,6 @@ CONFIG_NETDEV_TELNET=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/cc3200-launchpad/nsh/defconfig b/configs/cc3200-launchpad/nsh/defconfig index c0b7945bc2..1de3eee3e2 100644 --- a/configs/cc3200-launchpad/nsh/defconfig +++ b/configs/cc3200-launchpad/nsh/defconfig @@ -461,7 +461,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/cloudctrl/nsh/defconfig b/configs/cloudctrl/nsh/defconfig index a558bd84c1..6da8937d15 100644 --- a/configs/cloudctrl/nsh/defconfig +++ b/configs/cloudctrl/nsh/defconfig @@ -834,7 +834,6 @@ CONFIG_ETH0_PHY_DM9161=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/demo9s12ne64/ostest/defconfig b/configs/demo9s12ne64/ostest/defconfig index b571cf62e8..c5f77d58a5 100644 --- a/configs/demo9s12ne64/ostest/defconfig +++ b/configs/demo9s12ne64/ostest/defconfig @@ -242,7 +242,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set diff --git a/configs/dk-tm4c129x/ipv6/defconfig b/configs/dk-tm4c129x/ipv6/defconfig index 2cdd072895..83644a89c4 100644 --- a/configs/dk-tm4c129x/ipv6/defconfig +++ b/configs/dk-tm4c129x/ipv6/defconfig @@ -596,7 +596,6 @@ CONFIG_LM75_I2C_FREQUENCY=100000 # CONFIG_VEML6070 is not set # CONFIG_XEN1210 is not set # CONFIG_ZEROCROSS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/dk-tm4c129x/nsh/defconfig b/configs/dk-tm4c129x/nsh/defconfig index 085a598e1f..c9a9edac93 100644 --- a/configs/dk-tm4c129x/nsh/defconfig +++ b/configs/dk-tm4c129x/nsh/defconfig @@ -598,7 +598,6 @@ CONFIG_LM75_I2C_FREQUENCY=100000 # CONFIG_VEML6070 is not set # CONFIG_XEN1210 is not set # CONFIG_ZEROCROSS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/ea3131/nsh/defconfig b/configs/ea3131/nsh/defconfig index 3250e05da7..b98a0b0c96 100644 --- a/configs/ea3131/nsh/defconfig +++ b/configs/ea3131/nsh/defconfig @@ -418,7 +418,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/ea3131/pgnsh/defconfig b/configs/ea3131/pgnsh/defconfig index 8d53362269..8bb8ce2903 100644 --- a/configs/ea3131/pgnsh/defconfig +++ b/configs/ea3131/pgnsh/defconfig @@ -494,7 +494,6 @@ CONFIG_M25P_MEMORY_TYPE=0x20 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/ea3131/usbserial/defconfig b/configs/ea3131/usbserial/defconfig index 6c2c68e5db..cf79f1ff54 100644 --- a/configs/ea3131/usbserial/defconfig +++ b/configs/ea3131/usbserial/defconfig @@ -431,7 +431,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y CONFIG_SERIAL_REMOVABLE=y diff --git a/configs/ea3152/ostest/defconfig b/configs/ea3152/ostest/defconfig index 96961e4204..5222be557c 100644 --- a/configs/ea3152/ostest/defconfig +++ b/configs/ea3152/ostest/defconfig @@ -413,7 +413,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/eagle100/httpd/defconfig b/configs/eagle100/httpd/defconfig index b2fbabd77c..10e1481b20 100644 --- a/configs/eagle100/httpd/defconfig +++ b/configs/eagle100/httpd/defconfig @@ -532,7 +532,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/eagle100/nettest/defconfig b/configs/eagle100/nettest/defconfig index a0c3b49b98..2b2d08c871 100644 --- a/configs/eagle100/nettest/defconfig +++ b/configs/eagle100/nettest/defconfig @@ -524,7 +524,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/eagle100/nsh/defconfig b/configs/eagle100/nsh/defconfig index 2a90032891..31736a4493 100644 --- a/configs/eagle100/nsh/defconfig +++ b/configs/eagle100/nsh/defconfig @@ -563,7 +563,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/eagle100/nxflat/defconfig b/configs/eagle100/nxflat/defconfig index d28067ad94..1d55be1648 100644 --- a/configs/eagle100/nxflat/defconfig +++ b/configs/eagle100/nxflat/defconfig @@ -483,7 +483,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/eagle100/thttpd/defconfig b/configs/eagle100/thttpd/defconfig index 579c652513..e0e7a25e9f 100644 --- a/configs/eagle100/thttpd/defconfig +++ b/configs/eagle100/thttpd/defconfig @@ -520,7 +520,6 @@ CONFIG_DEV_FIFO_SIZE=1024 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/efm32-g8xx-stk/nsh/defconfig b/configs/efm32-g8xx-stk/nsh/defconfig index d97369ecf9..4c7b62ce8b 100644 --- a/configs/efm32-g8xx-stk/nsh/defconfig +++ b/configs/efm32-g8xx-stk/nsh/defconfig @@ -457,7 +457,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/efm32gg-stk3700/nsh/defconfig b/configs/efm32gg-stk3700/nsh/defconfig index aef89ed858..db3dbf7aa9 100644 --- a/configs/efm32gg-stk3700/nsh/defconfig +++ b/configs/efm32gg-stk3700/nsh/defconfig @@ -457,7 +457,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/ekk-lm3s9b96/nsh/defconfig b/configs/ekk-lm3s9b96/nsh/defconfig index 9870858ce1..cca7bc60c5 100644 --- a/configs/ekk-lm3s9b96/nsh/defconfig +++ b/configs/ekk-lm3s9b96/nsh/defconfig @@ -552,7 +552,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/esp32-core/nsh/defconfig b/configs/esp32-core/nsh/defconfig index 5c75b76887..ce5088bb99 100644 --- a/configs/esp32-core/nsh/defconfig +++ b/configs/esp32-core/nsh/defconfig @@ -354,7 +354,6 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/esp32-core/smp/defconfig b/configs/esp32-core/smp/defconfig index 9db1561de7..620896ec4f 100644 --- a/configs/esp32-core/smp/defconfig +++ b/configs/esp32-core/smp/defconfig @@ -357,7 +357,6 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/ez80f910200kitg/ostest/defconfig b/configs/ez80f910200kitg/ostest/defconfig index fcfe07a33b..4a79e9765a 100644 --- a/configs/ez80f910200kitg/ostest/defconfig +++ b/configs/ez80f910200kitg/ostest/defconfig @@ -369,7 +369,6 @@ CONFIG_MMCSD_HAVECARDDETECT=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/ez80f910200zco/dhcpd/defconfig b/configs/ez80f910200zco/dhcpd/defconfig index 72dcc5ecfa..d48a15c6f2 100644 --- a/configs/ez80f910200zco/dhcpd/defconfig +++ b/configs/ez80f910200zco/dhcpd/defconfig @@ -424,7 +424,6 @@ CONFIG_ETH0_PHY_AM79C874=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/ez80f910200zco/httpd/defconfig b/configs/ez80f910200zco/httpd/defconfig index b74d62ba78..7ef42bdffa 100644 --- a/configs/ez80f910200zco/httpd/defconfig +++ b/configs/ez80f910200zco/httpd/defconfig @@ -433,7 +433,6 @@ CONFIG_ETH0_PHY_AM79C874=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/ez80f910200zco/nettest/defconfig b/configs/ez80f910200zco/nettest/defconfig index e4fe5af40f..e9b3d8c54f 100644 --- a/configs/ez80f910200zco/nettest/defconfig +++ b/configs/ez80f910200zco/nettest/defconfig @@ -425,7 +425,6 @@ CONFIG_ETH0_PHY_AM79C874=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/ez80f910200zco/nsh/defconfig b/configs/ez80f910200zco/nsh/defconfig index 2b23512921..72a9774dd9 100644 --- a/configs/ez80f910200zco/nsh/defconfig +++ b/configs/ez80f910200zco/nsh/defconfig @@ -435,7 +435,6 @@ CONFIG_ETH0_PHY_AM79C874=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/ez80f910200zco/poll/defconfig b/configs/ez80f910200zco/poll/defconfig index a7b22914de..b806a20f74 100644 --- a/configs/ez80f910200zco/poll/defconfig +++ b/configs/ez80f910200zco/poll/defconfig @@ -435,7 +435,6 @@ CONFIG_DEV_FIFO_SIZE=1024 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/fire-stm32v2/nsh/defconfig b/configs/fire-stm32v2/nsh/defconfig index 50cae46c40..4abebec236 100644 --- a/configs/fire-stm32v2/nsh/defconfig +++ b/configs/fire-stm32v2/nsh/defconfig @@ -842,7 +842,6 @@ CONFIG_ENC28J60_HPWORK=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/freedom-k64f/netnsh/defconfig b/configs/freedom-k64f/netnsh/defconfig index 02ec9f3d77..a16d6eae3f 100644 --- a/configs/freedom-k64f/netnsh/defconfig +++ b/configs/freedom-k64f/netnsh/defconfig @@ -564,7 +564,6 @@ CONFIG_ETH0_PHY_KSZ8081=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/freedom-k64f/nsh/defconfig b/configs/freedom-k64f/nsh/defconfig index 32c412eff7..d32846b642 100644 --- a/configs/freedom-k64f/nsh/defconfig +++ b/configs/freedom-k64f/nsh/defconfig @@ -512,7 +512,6 @@ CONFIG_SDIO_BLOCKSETUP=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/freedom-kl25z/nsh/defconfig b/configs/freedom-kl25z/nsh/defconfig index 7e8e1e499c..4ce766e4e7 100644 --- a/configs/freedom-kl25z/nsh/defconfig +++ b/configs/freedom-kl25z/nsh/defconfig @@ -428,7 +428,6 @@ CONFIG_PWM=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/freedom-kl26z/nsh/defconfig b/configs/freedom-kl26z/nsh/defconfig index 47dd2b666c..34ecf77745 100644 --- a/configs/freedom-kl26z/nsh/defconfig +++ b/configs/freedom-kl26z/nsh/defconfig @@ -422,7 +422,6 @@ CONFIG_PWM=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/hymini-stm32v/nsh/defconfig b/configs/hymini-stm32v/nsh/defconfig index 47f1611dde..54662444e9 100644 --- a/configs/hymini-stm32v/nsh/defconfig +++ b/configs/hymini-stm32v/nsh/defconfig @@ -740,7 +740,6 @@ CONFIG_SDIO_PREFLIGHT=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/hymini-stm32v/nsh2/defconfig b/configs/hymini-stm32v/nsh2/defconfig index 7bc35a4917..6998b185dc 100644 --- a/configs/hymini-stm32v/nsh2/defconfig +++ b/configs/hymini-stm32v/nsh2/defconfig @@ -837,7 +837,6 @@ CONFIG_SDIO_PREFLIGHT=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/hymini-stm32v/usbmsc/defconfig b/configs/hymini-stm32v/usbmsc/defconfig index 504e368db2..9d5759bf6c 100644 --- a/configs/hymini-stm32v/usbmsc/defconfig +++ b/configs/hymini-stm32v/usbmsc/defconfig @@ -746,7 +746,6 @@ CONFIG_SDIO_PREFLIGHT=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/hymini-stm32v/usbnsh/defconfig b/configs/hymini-stm32v/usbnsh/defconfig index 32e61c43d6..2d2497ca47 100644 --- a/configs/hymini-stm32v/usbnsh/defconfig +++ b/configs/hymini-stm32v/usbnsh/defconfig @@ -733,7 +733,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set CONFIG_SERIAL_REMOVABLE=y diff --git a/configs/hymini-stm32v/usbserial/defconfig b/configs/hymini-stm32v/usbserial/defconfig index e60be704c7..13be18558c 100644 --- a/configs/hymini-stm32v/usbserial/defconfig +++ b/configs/hymini-stm32v/usbserial/defconfig @@ -720,7 +720,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set CONFIG_SERIAL_REMOVABLE=y diff --git a/configs/kwikstik-k40/ostest/defconfig b/configs/kwikstik-k40/ostest/defconfig index 3aa09462c5..4ea31a1c0f 100644 --- a/configs/kwikstik-k40/ostest/defconfig +++ b/configs/kwikstik-k40/ostest/defconfig @@ -463,7 +463,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/launchxl-tms57004/nsh/defconfig b/configs/launchxl-tms57004/nsh/defconfig index d80732cc89..d59a2f60f5 100644 --- a/configs/launchxl-tms57004/nsh/defconfig +++ b/configs/launchxl-tms57004/nsh/defconfig @@ -433,7 +433,6 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/lincoln60/netnsh/defconfig b/configs/lincoln60/netnsh/defconfig index d441e274ba..8e9cdf53c6 100644 --- a/configs/lincoln60/netnsh/defconfig +++ b/configs/lincoln60/netnsh/defconfig @@ -543,7 +543,6 @@ CONFIG_ETH0_PHY_KSZ8041=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/lincoln60/nsh/defconfig b/configs/lincoln60/nsh/defconfig index 3fcf92ddc8..31e8eae34a 100644 --- a/configs/lincoln60/nsh/defconfig +++ b/configs/lincoln60/nsh/defconfig @@ -462,7 +462,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/lincoln60/thttpd-binfs/defconfig b/configs/lincoln60/thttpd-binfs/defconfig index 2ca94f7fa3..f1d8ab9bbf 100644 --- a/configs/lincoln60/thttpd-binfs/defconfig +++ b/configs/lincoln60/thttpd-binfs/defconfig @@ -525,7 +525,6 @@ CONFIG_DEV_FIFO_SIZE=1024 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/lm3s6432-s2e/nsh/defconfig b/configs/lm3s6432-s2e/nsh/defconfig index a18a57d4c2..6212b42fab 100644 --- a/configs/lm3s6432-s2e/nsh/defconfig +++ b/configs/lm3s6432-s2e/nsh/defconfig @@ -529,7 +529,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/lm3s6965-ek/discover/defconfig b/configs/lm3s6965-ek/discover/defconfig index 8d96db5491..265299c608 100644 --- a/configs/lm3s6965-ek/discover/defconfig +++ b/configs/lm3s6965-ek/discover/defconfig @@ -557,7 +557,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/lm3s6965-ek/nsh/defconfig b/configs/lm3s6965-ek/nsh/defconfig index 8d96db5491..265299c608 100644 --- a/configs/lm3s6965-ek/nsh/defconfig +++ b/configs/lm3s6965-ek/nsh/defconfig @@ -557,7 +557,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/lm3s6965-ek/nx/defconfig b/configs/lm3s6965-ek/nx/defconfig index 496b2737ea..fdc5c9c632 100644 --- a/configs/lm3s6965-ek/nx/defconfig +++ b/configs/lm3s6965-ek/nx/defconfig @@ -541,7 +541,6 @@ CONFIG_LCD_LANDSCAPE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/lm3s6965-ek/tcpecho/defconfig b/configs/lm3s6965-ek/tcpecho/defconfig index d080e57f55..96af39bd22 100644 --- a/configs/lm3s6965-ek/tcpecho/defconfig +++ b/configs/lm3s6965-ek/tcpecho/defconfig @@ -528,7 +528,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/lm3s8962-ek/nsh/defconfig b/configs/lm3s8962-ek/nsh/defconfig index d707ebe974..d834d65af4 100644 --- a/configs/lm3s8962-ek/nsh/defconfig +++ b/configs/lm3s8962-ek/nsh/defconfig @@ -567,7 +567,6 @@ CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/lm3s8962-ek/nx/defconfig b/configs/lm3s8962-ek/nx/defconfig index 7cfe420286..92d68b951c 100644 --- a/configs/lm3s8962-ek/nx/defconfig +++ b/configs/lm3s8962-ek/nx/defconfig @@ -551,7 +551,6 @@ CONFIG_LCD_LANDSCAPE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/lm4f120-launchpad/nsh/defconfig b/configs/lm4f120-launchpad/nsh/defconfig index 2dd6e821ae..759d63075b 100644 --- a/configs/lm4f120-launchpad/nsh/defconfig +++ b/configs/lm4f120-launchpad/nsh/defconfig @@ -492,7 +492,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/lpc4330-xplorer/nsh/defconfig b/configs/lpc4330-xplorer/nsh/defconfig index ded2899940..6d0df578a2 100644 --- a/configs/lpc4330-xplorer/nsh/defconfig +++ b/configs/lpc4330-xplorer/nsh/defconfig @@ -480,7 +480,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/lpc4337-ws/nsh/defconfig b/configs/lpc4337-ws/nsh/defconfig index f4f3a256a3..a462d6a1e4 100644 --- a/configs/lpc4337-ws/nsh/defconfig +++ b/configs/lpc4337-ws/nsh/defconfig @@ -499,7 +499,6 @@ CONFIG_ADC_FIFOSIZE=8 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set CONFIG_SERIAL_REMOVABLE=y diff --git a/configs/lpc4357-evb/nsh/defconfig b/configs/lpc4357-evb/nsh/defconfig index a4aeb12c63..fda9ffd04c 100644 --- a/configs/lpc4357-evb/nsh/defconfig +++ b/configs/lpc4357-evb/nsh/defconfig @@ -472,7 +472,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/lpc4370-link2/nsh/defconfig b/configs/lpc4370-link2/nsh/defconfig index e6705f3f53..605c816885 100644 --- a/configs/lpc4370-link2/nsh/defconfig +++ b/configs/lpc4370-link2/nsh/defconfig @@ -496,7 +496,6 @@ CONFIG_SPI=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set CONFIG_SERIAL_REMOVABLE=y diff --git a/configs/lpcxpresso-lpc1115/nsh/defconfig b/configs/lpcxpresso-lpc1115/nsh/defconfig index 9f84ad4089..8a66a48cc7 100644 --- a/configs/lpcxpresso-lpc1115/nsh/defconfig +++ b/configs/lpcxpresso-lpc1115/nsh/defconfig @@ -394,7 +394,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/lpcxpresso-lpc1768/dhcpd/defconfig b/configs/lpcxpresso-lpc1768/dhcpd/defconfig index bba536eb45..380604febf 100644 --- a/configs/lpcxpresso-lpc1768/dhcpd/defconfig +++ b/configs/lpcxpresso-lpc1768/dhcpd/defconfig @@ -513,7 +513,6 @@ CONFIG_ETH0_PHY_LAN8720=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/lpcxpresso-lpc1768/nsh/defconfig b/configs/lpcxpresso-lpc1768/nsh/defconfig index 711a813f12..fdbc186bc7 100644 --- a/configs/lpcxpresso-lpc1768/nsh/defconfig +++ b/configs/lpcxpresso-lpc1768/nsh/defconfig @@ -583,7 +583,6 @@ CONFIG_ETH0_PHY_LAN8720=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/lpcxpresso-lpc1768/nx/defconfig b/configs/lpcxpresso-lpc1768/nx/defconfig index fbfd01860b..bb99255c2d 100644 --- a/configs/lpcxpresso-lpc1768/nx/defconfig +++ b/configs/lpcxpresso-lpc1768/nx/defconfig @@ -519,7 +519,6 @@ CONFIG_LCD_LANDSCAPE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/lpcxpresso-lpc1768/thttpd/defconfig b/configs/lpcxpresso-lpc1768/thttpd/defconfig index 9b6d1f1642..0020d90dbf 100644 --- a/configs/lpcxpresso-lpc1768/thttpd/defconfig +++ b/configs/lpcxpresso-lpc1768/thttpd/defconfig @@ -517,7 +517,6 @@ CONFIG_DEV_FIFO_SIZE=1024 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/lpcxpresso-lpc1768/usbmsc/defconfig b/configs/lpcxpresso-lpc1768/usbmsc/defconfig index b320318150..608efd1c81 100644 --- a/configs/lpcxpresso-lpc1768/usbmsc/defconfig +++ b/configs/lpcxpresso-lpc1768/usbmsc/defconfig @@ -492,7 +492,6 @@ CONFIG_MMCSD_SPIMODE=0 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/maple/nsh/defconfig b/configs/maple/nsh/defconfig index 1b7e1f5ac7..3a9c485155 100644 --- a/configs/maple/nsh/defconfig +++ b/configs/maple/nsh/defconfig @@ -704,7 +704,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/maple/nx/defconfig b/configs/maple/nx/defconfig index 3906da6970..9936c99c3d 100644 --- a/configs/maple/nx/defconfig +++ b/configs/maple/nx/defconfig @@ -799,7 +799,6 @@ CONFIG_LCD_LANDSCAPE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_SERIAL_REMOVABLE=y CONFIG_SERIAL_CONSOLE=y diff --git a/configs/maple/usbnsh/defconfig b/configs/maple/usbnsh/defconfig index 03c4bdf963..1a0485d7dc 100644 --- a/configs/maple/usbnsh/defconfig +++ b/configs/maple/usbnsh/defconfig @@ -716,7 +716,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_SERIAL_REMOVABLE=y CONFIG_SERIAL_CONSOLE=y diff --git a/configs/mbed/hidkbd/defconfig b/configs/mbed/hidkbd/defconfig index 1543135095..749e51ef04 100644 --- a/configs/mbed/hidkbd/defconfig +++ b/configs/mbed/hidkbd/defconfig @@ -476,7 +476,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/mbed/nsh/defconfig b/configs/mbed/nsh/defconfig index 094452f385..e58d828f5e 100644 --- a/configs/mbed/nsh/defconfig +++ b/configs/mbed/nsh/defconfig @@ -514,7 +514,6 @@ CONFIG_MTD=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/mcu123-lpc214x/composite/defconfig b/configs/mcu123-lpc214x/composite/defconfig index c201531c3e..cffe65a216 100644 --- a/configs/mcu123-lpc214x/composite/defconfig +++ b/configs/mcu123-lpc214x/composite/defconfig @@ -429,7 +429,6 @@ CONFIG_MMCSD_SPIMODE=0 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set CONFIG_SERIAL_REMOVABLE=y diff --git a/configs/mcu123-lpc214x/nsh/defconfig b/configs/mcu123-lpc214x/nsh/defconfig index ecf4525145..16148fb70a 100644 --- a/configs/mcu123-lpc214x/nsh/defconfig +++ b/configs/mcu123-lpc214x/nsh/defconfig @@ -422,7 +422,6 @@ CONFIG_MMCSD_SPIMODE=0 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/mcu123-lpc214x/usbmsc/defconfig b/configs/mcu123-lpc214x/usbmsc/defconfig index 6aa0970854..902c2e9593 100644 --- a/configs/mcu123-lpc214x/usbmsc/defconfig +++ b/configs/mcu123-lpc214x/usbmsc/defconfig @@ -429,7 +429,6 @@ CONFIG_MMCSD_SPIMODE=0 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/mcu123-lpc214x/usbserial/defconfig b/configs/mcu123-lpc214x/usbserial/defconfig index c2717e3634..d6293bc0cc 100644 --- a/configs/mcu123-lpc214x/usbserial/defconfig +++ b/configs/mcu123-lpc214x/usbserial/defconfig @@ -409,7 +409,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set CONFIG_SERIAL_REMOVABLE=y diff --git a/configs/micropendous3/hello/defconfig b/configs/micropendous3/hello/defconfig index 46d64c660c..c11817790b 100644 --- a/configs/micropendous3/hello/defconfig +++ b/configs/micropendous3/hello/defconfig @@ -241,7 +241,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_16550_UART is not set diff --git a/configs/mikroe-stm32f4/fulldemo/defconfig b/configs/mikroe-stm32f4/fulldemo/defconfig index 3588440c91..ec1f44da76 100644 --- a/configs/mikroe-stm32f4/fulldemo/defconfig +++ b/configs/mikroe-stm32f4/fulldemo/defconfig @@ -901,7 +901,6 @@ CONFIG_MTD_SMART_WEAR_LEVEL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_SERIAL_REMOVABLE=y # CONFIG_SERIAL_CONSOLE is not set diff --git a/configs/mikroe-stm32f4/kostest/defconfig b/configs/mikroe-stm32f4/kostest/defconfig index 5baa0d7129..e8740c395b 100644 --- a/configs/mikroe-stm32f4/kostest/defconfig +++ b/configs/mikroe-stm32f4/kostest/defconfig @@ -845,7 +845,6 @@ CONFIG_MTD_SMART_WEAR_LEVEL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_SERIAL_REMOVABLE=y # CONFIG_SERIAL_CONSOLE is not set diff --git a/configs/mikroe-stm32f4/nsh/defconfig b/configs/mikroe-stm32f4/nsh/defconfig index 88f1e50141..bd189e13d9 100644 --- a/configs/mikroe-stm32f4/nsh/defconfig +++ b/configs/mikroe-stm32f4/nsh/defconfig @@ -812,7 +812,6 @@ CONFIG_MTD_SMART_WEAR_LEVEL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_SERIAL_REMOVABLE is not set CONFIG_SERIAL_CONSOLE=y diff --git a/configs/mikroe-stm32f4/nx/defconfig b/configs/mikroe-stm32f4/nx/defconfig index 141f06a3f2..51f178871d 100644 --- a/configs/mikroe-stm32f4/nx/defconfig +++ b/configs/mikroe-stm32f4/nx/defconfig @@ -758,7 +758,6 @@ CONFIG_LCD_LANDSCAPE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set # CONFIG_SERIAL is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set diff --git a/configs/mikroe-stm32f4/nxlines/defconfig b/configs/mikroe-stm32f4/nxlines/defconfig index 96e58d2a0e..f0c6adcfea 100644 --- a/configs/mikroe-stm32f4/nxlines/defconfig +++ b/configs/mikroe-stm32f4/nxlines/defconfig @@ -745,7 +745,6 @@ CONFIG_LCD_LANDSCAPE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set # CONFIG_SERIAL is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set diff --git a/configs/mikroe-stm32f4/nxtext/defconfig b/configs/mikroe-stm32f4/nxtext/defconfig index 511b951270..52933714d6 100644 --- a/configs/mikroe-stm32f4/nxtext/defconfig +++ b/configs/mikroe-stm32f4/nxtext/defconfig @@ -758,7 +758,6 @@ CONFIG_LCD_LANDSCAPE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set # CONFIG_SERIAL is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set diff --git a/configs/mikroe-stm32f4/usbnsh/defconfig b/configs/mikroe-stm32f4/usbnsh/defconfig index 5e53200ce8..6ebceb9c45 100644 --- a/configs/mikroe-stm32f4/usbnsh/defconfig +++ b/configs/mikroe-stm32f4/usbnsh/defconfig @@ -820,7 +820,6 @@ CONFIG_MTD_SMART_WEAR_LEVEL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_SERIAL_REMOVABLE=y # CONFIG_SERIAL_CONSOLE is not set diff --git a/configs/mirtoo/nsh/defconfig b/configs/mirtoo/nsh/defconfig index 8c8743a9ce..3630f0f223 100644 --- a/configs/mirtoo/nsh/defconfig +++ b/configs/mirtoo/nsh/defconfig @@ -499,7 +499,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/mirtoo/nxffs/defconfig b/configs/mirtoo/nxffs/defconfig index 6dbc62ca2b..627d0b9e7a 100644 --- a/configs/mirtoo/nxffs/defconfig +++ b/configs/mirtoo/nxffs/defconfig @@ -540,7 +540,6 @@ CONFIG_SST25_SPIFREQUENCY=20000000 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/misoc/hello/defconfig b/configs/misoc/hello/defconfig index 3aef6631d1..a9a5dfc138 100644 --- a/configs/misoc/hello/defconfig +++ b/configs/misoc/hello/defconfig @@ -407,7 +407,6 @@ CONFIG_ETH0_PHY_NONE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/misoc/nsh/defconfig b/configs/misoc/nsh/defconfig index 438198545a..75cf732f67 100644 --- a/configs/misoc/nsh/defconfig +++ b/configs/misoc/nsh/defconfig @@ -334,7 +334,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/moteino-mega/hello/defconfig b/configs/moteino-mega/hello/defconfig index 973aac4a8d..ffadd04745 100644 --- a/configs/moteino-mega/hello/defconfig +++ b/configs/moteino-mega/hello/defconfig @@ -269,7 +269,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_16550_UART is not set diff --git a/configs/moteino-mega/nsh/defconfig b/configs/moteino-mega/nsh/defconfig index 97bf0cf3e0..c3021fcbf7 100644 --- a/configs/moteino-mega/nsh/defconfig +++ b/configs/moteino-mega/nsh/defconfig @@ -277,7 +277,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set diff --git a/configs/moxa/nsh/defconfig b/configs/moxa/nsh/defconfig index f1fdbfbda3..fd951b047a 100644 --- a/configs/moxa/nsh/defconfig +++ b/configs/moxa/nsh/defconfig @@ -427,7 +427,6 @@ CONFIG_FTMAC100_HPWORK=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/mx1ads/ostest/defconfig b/configs/mx1ads/ostest/defconfig index 6f911c5a48..04225dad73 100644 --- a/configs/mx1ads/ostest/defconfig +++ b/configs/mx1ads/ostest/defconfig @@ -390,7 +390,6 @@ CONFIG_SPI=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/ne64badge/ostest/defconfig b/configs/ne64badge/ostest/defconfig index 94d4e981c3..2986223f0c 100644 --- a/configs/ne64badge/ostest/defconfig +++ b/configs/ne64badge/ostest/defconfig @@ -242,7 +242,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set diff --git a/configs/nr5m100-nexys4/nsh/defconfig b/configs/nr5m100-nexys4/nsh/defconfig index eacb815a02..e2b6c7f66d 100644 --- a/configs/nr5m100-nexys4/nsh/defconfig +++ b/configs/nr5m100-nexys4/nsh/defconfig @@ -348,7 +348,6 @@ CONFIG_DEV_ZERO=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/ntosd-dm320/nettest/defconfig b/configs/ntosd-dm320/nettest/defconfig index 8621bd1cba..e1f95fe831 100644 --- a/configs/ntosd-dm320/nettest/defconfig +++ b/configs/ntosd-dm320/nettest/defconfig @@ -417,7 +417,6 @@ CONFIG_DM9X_HPWORK=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/ntosd-dm320/nsh/defconfig b/configs/ntosd-dm320/nsh/defconfig index 13fba2e95f..39868b6085 100644 --- a/configs/ntosd-dm320/nsh/defconfig +++ b/configs/ntosd-dm320/nsh/defconfig @@ -433,7 +433,6 @@ CONFIG_DM9X_HPWORK=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/ntosd-dm320/poll/defconfig b/configs/ntosd-dm320/poll/defconfig index 504fe1fd77..16cd6306ee 100644 --- a/configs/ntosd-dm320/poll/defconfig +++ b/configs/ntosd-dm320/poll/defconfig @@ -427,7 +427,6 @@ CONFIG_DEV_FIFO_SIZE=1024 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/ntosd-dm320/thttpd/defconfig b/configs/ntosd-dm320/thttpd/defconfig index e0b5074661..5b9439f577 100644 --- a/configs/ntosd-dm320/thttpd/defconfig +++ b/configs/ntosd-dm320/thttpd/defconfig @@ -420,7 +420,6 @@ CONFIG_DEV_FIFO_SIZE=1024 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/ntosd-dm320/udp/defconfig b/configs/ntosd-dm320/udp/defconfig index a9713516f4..430d9c3d54 100644 --- a/configs/ntosd-dm320/udp/defconfig +++ b/configs/ntosd-dm320/udp/defconfig @@ -416,7 +416,6 @@ CONFIG_DM9X_HPWORK=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/ntosd-dm320/webserver/defconfig b/configs/ntosd-dm320/webserver/defconfig index 8cb5e5715c..5b9e96f8f2 100644 --- a/configs/ntosd-dm320/webserver/defconfig +++ b/configs/ntosd-dm320/webserver/defconfig @@ -424,7 +424,6 @@ CONFIG_DM9X_HPWORK=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/nucleo-144/f746-evalos/defconfig b/configs/nucleo-144/f746-evalos/defconfig index 8dd40aa090..3372db8d00 100644 --- a/configs/nucleo-144/f746-evalos/defconfig +++ b/configs/nucleo-144/f746-evalos/defconfig @@ -628,7 +628,6 @@ CONFIG_USERLED_LOWER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/nucleo-144/f746-nsh/defconfig b/configs/nucleo-144/f746-nsh/defconfig index 91cc088605..d034bff8ac 100644 --- a/configs/nucleo-144/f746-nsh/defconfig +++ b/configs/nucleo-144/f746-nsh/defconfig @@ -616,7 +616,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/nucleo-144/f767-evalos/defconfig b/configs/nucleo-144/f767-evalos/defconfig index 90f0a2fa63..bae0a8f84b 100644 --- a/configs/nucleo-144/f767-evalos/defconfig +++ b/configs/nucleo-144/f767-evalos/defconfig @@ -632,7 +632,6 @@ CONFIG_USERLED_LOWER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/nucleo-144/f767-nsh/defconfig b/configs/nucleo-144/f767-nsh/defconfig index 30ea41719a..36e14b0093 100644 --- a/configs/nucleo-144/f767-nsh/defconfig +++ b/configs/nucleo-144/f767-nsh/defconfig @@ -620,7 +620,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/nucleo-f303re/adc/defconfig b/configs/nucleo-f303re/adc/defconfig index 6bd903c7b8..4fb368517a 100644 --- a/configs/nucleo-f303re/adc/defconfig +++ b/configs/nucleo-f303re/adc/defconfig @@ -723,7 +723,6 @@ CONFIG_ADC_FIFOSIZE=8 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set # CONFIG_SERIAL is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set diff --git a/configs/nucleo-f303re/can/defconfig b/configs/nucleo-f303re/can/defconfig index 957b4d9412..883c9c3668 100644 --- a/configs/nucleo-f303re/can/defconfig +++ b/configs/nucleo-f303re/can/defconfig @@ -724,7 +724,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set # CONFIG_SERIAL is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set diff --git a/configs/nucleo-f303re/hello/defconfig b/configs/nucleo-f303re/hello/defconfig index 46e78f3399..dffa050525 100644 --- a/configs/nucleo-f303re/hello/defconfig +++ b/configs/nucleo-f303re/hello/defconfig @@ -726,7 +726,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/nucleo-f303re/nxlines/defconfig b/configs/nucleo-f303re/nxlines/defconfig index da112c4350..84d948c102 100644 --- a/configs/nucleo-f303re/nxlines/defconfig +++ b/configs/nucleo-f303re/nxlines/defconfig @@ -788,7 +788,6 @@ CONFIG_LCD_LANDSCAPE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set # CONFIG_SERIAL is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set diff --git a/configs/nucleo-f303re/pwm/defconfig b/configs/nucleo-f303re/pwm/defconfig index ba86073959..ca70a10f72 100644 --- a/configs/nucleo-f303re/pwm/defconfig +++ b/configs/nucleo-f303re/pwm/defconfig @@ -723,7 +723,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set # CONFIG_SERIAL is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set diff --git a/configs/nucleo-f303re/serialrx/defconfig b/configs/nucleo-f303re/serialrx/defconfig index 0cbb86fdbf..17f8c5f5e2 100644 --- a/configs/nucleo-f303re/serialrx/defconfig +++ b/configs/nucleo-f303re/serialrx/defconfig @@ -727,7 +727,6 @@ CONFIG_ADC_FIFOSIZE=8 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_SERIAL_REMOVABLE is not set # CONFIG_SERIAL_CONSOLE is not set diff --git a/configs/nucleo-f303re/uavcan/defconfig b/configs/nucleo-f303re/uavcan/defconfig index 0d6b7a805a..21ffa46165 100644 --- a/configs/nucleo-f303re/uavcan/defconfig +++ b/configs/nucleo-f303re/uavcan/defconfig @@ -704,7 +704,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set # CONFIG_SERIAL is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set diff --git a/configs/nucleo-f4x1re/f401-nsh/defconfig b/configs/nucleo-f4x1re/f401-nsh/defconfig index bd6347ccf4..5973a284e1 100644 --- a/configs/nucleo-f4x1re/f401-nsh/defconfig +++ b/configs/nucleo-f4x1re/f401-nsh/defconfig @@ -723,7 +723,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/nucleo-f4x1re/f411-nsh/defconfig b/configs/nucleo-f4x1re/f411-nsh/defconfig index 93f29a8058..a1fafd77d5 100644 --- a/configs/nucleo-f4x1re/f411-nsh/defconfig +++ b/configs/nucleo-f4x1re/f411-nsh/defconfig @@ -725,7 +725,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/nucleo-l476rg/nsh/defconfig b/configs/nucleo-l476rg/nsh/defconfig index 293d43a01e..c8b4ec6900 100644 --- a/configs/nucleo-l476rg/nsh/defconfig +++ b/configs/nucleo-l476rg/nsh/defconfig @@ -556,7 +556,6 @@ CONFIG_RTC_IOCTL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/nutiny-nuc120/nsh/defconfig b/configs/nutiny-nuc120/nsh/defconfig index 52cd0aa73d..a8d566fcc0 100644 --- a/configs/nutiny-nuc120/nsh/defconfig +++ b/configs/nutiny-nuc120/nsh/defconfig @@ -444,7 +444,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-efm32g880f128-stk/nsh/defconfig b/configs/olimex-efm32g880f128-stk/nsh/defconfig index 325b4d39c6..284ccdf97a 100644 --- a/configs/olimex-efm32g880f128-stk/nsh/defconfig +++ b/configs/olimex-efm32g880f128-stk/nsh/defconfig @@ -450,7 +450,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-lpc-h3131/nsh/defconfig b/configs/olimex-lpc-h3131/nsh/defconfig index aa99aad41a..589cbe3c03 100644 --- a/configs/olimex-lpc-h3131/nsh/defconfig +++ b/configs/olimex-lpc-h3131/nsh/defconfig @@ -416,7 +416,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-lpc1766stk/ftpc/defconfig b/configs/olimex-lpc1766stk/ftpc/defconfig index 6e4257fabf..fc0d118c62 100644 --- a/configs/olimex-lpc1766stk/ftpc/defconfig +++ b/configs/olimex-lpc1766stk/ftpc/defconfig @@ -549,7 +549,6 @@ CONFIG_ETH0_PHY_KS8721=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-lpc1766stk/hidkbd/defconfig b/configs/olimex-lpc1766stk/hidkbd/defconfig index 91339c8034..f052dbade6 100644 --- a/configs/olimex-lpc1766stk/hidkbd/defconfig +++ b/configs/olimex-lpc1766stk/hidkbd/defconfig @@ -501,7 +501,6 @@ CONFIG_MMCSD_NSLOTS=1 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-lpc1766stk/hidmouse/defconfig b/configs/olimex-lpc1766stk/hidmouse/defconfig index 779627451c..a87a47d09e 100644 --- a/configs/olimex-lpc1766stk/hidmouse/defconfig +++ b/configs/olimex-lpc1766stk/hidmouse/defconfig @@ -518,7 +518,6 @@ CONFIG_NETDEV_TELNET=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-lpc1766stk/nettest/defconfig b/configs/olimex-lpc1766stk/nettest/defconfig index 3b16844a41..187301717f 100644 --- a/configs/olimex-lpc1766stk/nettest/defconfig +++ b/configs/olimex-lpc1766stk/nettest/defconfig @@ -515,7 +515,6 @@ CONFIG_ETH0_PHY_KS8721=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-lpc1766stk/nsh/defconfig b/configs/olimex-lpc1766stk/nsh/defconfig index 7f6d655492..061eb4cd36 100644 --- a/configs/olimex-lpc1766stk/nsh/defconfig +++ b/configs/olimex-lpc1766stk/nsh/defconfig @@ -551,7 +551,6 @@ CONFIG_ETH0_PHY_KS8721=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-lpc1766stk/nx/defconfig b/configs/olimex-lpc1766stk/nx/defconfig index 9eab58ddbb..498cc7c004 100644 --- a/configs/olimex-lpc1766stk/nx/defconfig +++ b/configs/olimex-lpc1766stk/nx/defconfig @@ -529,7 +529,6 @@ CONFIG_LCD_LANDSCAPE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-lpc1766stk/slip-httpd/defconfig b/configs/olimex-lpc1766stk/slip-httpd/defconfig index 0d5615bac1..6ccd8a93a4 100644 --- a/configs/olimex-lpc1766stk/slip-httpd/defconfig +++ b/configs/olimex-lpc1766stk/slip-httpd/defconfig @@ -465,7 +465,6 @@ CONFIG_DEV_FIFO_SIZE=1024 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-lpc1766stk/thttpd-binfs/defconfig b/configs/olimex-lpc1766stk/thttpd-binfs/defconfig index 0e6f02065b..ee3023b507 100644 --- a/configs/olimex-lpc1766stk/thttpd-binfs/defconfig +++ b/configs/olimex-lpc1766stk/thttpd-binfs/defconfig @@ -525,7 +525,6 @@ CONFIG_DEV_FIFO_SIZE=1024 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig b/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig index 048d75917e..9a9f869082 100644 --- a/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig +++ b/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig @@ -518,7 +518,6 @@ CONFIG_DEV_FIFO_SIZE=1024 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-lpc1766stk/usbmsc/defconfig b/configs/olimex-lpc1766stk/usbmsc/defconfig index cac5beabd4..be389ce940 100644 --- a/configs/olimex-lpc1766stk/usbmsc/defconfig +++ b/configs/olimex-lpc1766stk/usbmsc/defconfig @@ -493,7 +493,6 @@ CONFIG_MMCSD_SPIMODE=0 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-lpc1766stk/usbserial/defconfig b/configs/olimex-lpc1766stk/usbserial/defconfig index 82a00f158d..3941c38d2c 100644 --- a/configs/olimex-lpc1766stk/usbserial/defconfig +++ b/configs/olimex-lpc1766stk/usbserial/defconfig @@ -474,7 +474,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set CONFIG_SERIAL_REMOVABLE=y diff --git a/configs/olimex-lpc1766stk/zmodem/defconfig b/configs/olimex-lpc1766stk/zmodem/defconfig index 4bb500d149..7eca8a61a9 100644 --- a/configs/olimex-lpc1766stk/zmodem/defconfig +++ b/configs/olimex-lpc1766stk/zmodem/defconfig @@ -553,7 +553,6 @@ CONFIG_ETH0_PHY_KS8721=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-lpc2378/nsh/defconfig b/configs/olimex-lpc2378/nsh/defconfig index 0217cd1a89..f5592ef7c9 100644 --- a/configs/olimex-lpc2378/nsh/defconfig +++ b/configs/olimex-lpc2378/nsh/defconfig @@ -388,7 +388,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-stm32-e407/discover/defconfig b/configs/olimex-stm32-e407/discover/defconfig index a10f5196cb..d4f6b116be 100644 --- a/configs/olimex-stm32-e407/discover/defconfig +++ b/configs/olimex-stm32-e407/discover/defconfig @@ -823,7 +823,6 @@ CONFIG_ETH0_PHY_LAN8720=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-stm32-e407/netnsh/defconfig b/configs/olimex-stm32-e407/netnsh/defconfig index 2053901804..5d71e695ec 100644 --- a/configs/olimex-stm32-e407/netnsh/defconfig +++ b/configs/olimex-stm32-e407/netnsh/defconfig @@ -825,7 +825,6 @@ CONFIG_ETH0_PHY_LAN8720=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-stm32-e407/nsh/defconfig b/configs/olimex-stm32-e407/nsh/defconfig index cc1f9c936c..e65e883811 100644 --- a/configs/olimex-stm32-e407/nsh/defconfig +++ b/configs/olimex-stm32-e407/nsh/defconfig @@ -737,7 +737,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-stm32-e407/telnetd/defconfig b/configs/olimex-stm32-e407/telnetd/defconfig index 4867ca74cd..f5410d6391 100644 --- a/configs/olimex-stm32-e407/telnetd/defconfig +++ b/configs/olimex-stm32-e407/telnetd/defconfig @@ -825,7 +825,6 @@ CONFIG_ETH0_PHY_LAN8720=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-stm32-e407/usbnsh/defconfig b/configs/olimex-stm32-e407/usbnsh/defconfig index 937cdcdf9d..2f62bb2803 100644 --- a/configs/olimex-stm32-e407/usbnsh/defconfig +++ b/configs/olimex-stm32-e407/usbnsh/defconfig @@ -754,7 +754,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_SERIAL_REMOVABLE=y # CONFIG_SERIAL_CONSOLE is not set diff --git a/configs/olimex-stm32-e407/webserver/defconfig b/configs/olimex-stm32-e407/webserver/defconfig index 7da7262f19..5066117e88 100644 --- a/configs/olimex-stm32-e407/webserver/defconfig +++ b/configs/olimex-stm32-e407/webserver/defconfig @@ -823,7 +823,6 @@ CONFIG_ETH0_PHY_LAN8720=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-stm32-h405/usbnsh/defconfig b/configs/olimex-stm32-h405/usbnsh/defconfig index 4054b5aaa8..623dc403e6 100644 --- a/configs/olimex-stm32-h405/usbnsh/defconfig +++ b/configs/olimex-stm32-h405/usbnsh/defconfig @@ -792,7 +792,6 @@ CONFIG_ADC_FIFOSIZE=8 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_SERIAL_REMOVABLE=y # CONFIG_SERIAL_CONSOLE is not set diff --git a/configs/olimex-stm32-h407/nsh/defconfig b/configs/olimex-stm32-h407/nsh/defconfig index 91f089efaa..f6134cc73c 100644 --- a/configs/olimex-stm32-h407/nsh/defconfig +++ b/configs/olimex-stm32-h407/nsh/defconfig @@ -747,7 +747,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-stm32-p107/nsh/defconfig b/configs/olimex-stm32-p107/nsh/defconfig index e93ce79019..a35f6c8abd 100644 --- a/configs/olimex-stm32-p107/nsh/defconfig +++ b/configs/olimex-stm32-p107/nsh/defconfig @@ -826,7 +826,6 @@ CONFIG_ETH0_PHY_KS8721=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-stm32-p207/nsh/defconfig b/configs/olimex-stm32-p207/nsh/defconfig index 79ffb43b17..5bb065a98b 100644 --- a/configs/olimex-stm32-p207/nsh/defconfig +++ b/configs/olimex-stm32-p207/nsh/defconfig @@ -857,7 +857,6 @@ CONFIG_ETH0_PHY_KS8721=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-strp711/nettest/defconfig b/configs/olimex-strp711/nettest/defconfig index 3d25b1799d..838239291f 100644 --- a/configs/olimex-strp711/nettest/defconfig +++ b/configs/olimex-strp711/nettest/defconfig @@ -460,7 +460,6 @@ CONFIG_ENC28J60_HPWORK=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimex-strp711/nsh/defconfig b/configs/olimex-strp711/nsh/defconfig index 1a5d097977..d889a22c2e 100644 --- a/configs/olimex-strp711/nsh/defconfig +++ b/configs/olimex-strp711/nsh/defconfig @@ -432,7 +432,6 @@ CONFIG_MMCSD_SPIMODE=0 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimexino-stm32/can/defconfig b/configs/olimexino-stm32/can/defconfig index b2e0ce9159..93c56baffe 100644 --- a/configs/olimexino-stm32/can/defconfig +++ b/configs/olimexino-stm32/can/defconfig @@ -782,7 +782,6 @@ CONFIG_ANALOG=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimexino-stm32/composite/defconfig b/configs/olimexino-stm32/composite/defconfig index bd5fb70be0..8bf9ffffa7 100644 --- a/configs/olimexino-stm32/composite/defconfig +++ b/configs/olimexino-stm32/composite/defconfig @@ -793,7 +793,6 @@ CONFIG_MMCSD_SPIMODE=0 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set CONFIG_SERIAL_REMOVABLE=y diff --git a/configs/olimexino-stm32/nsh/defconfig b/configs/olimexino-stm32/nsh/defconfig index c00722b831..10da4dcdbd 100644 --- a/configs/olimexino-stm32/nsh/defconfig +++ b/configs/olimexino-stm32/nsh/defconfig @@ -792,7 +792,6 @@ CONFIG_MMCSD_SPIMODE=0 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimexino-stm32/smallnsh/defconfig b/configs/olimexino-stm32/smallnsh/defconfig index 6edc98d077..fd206bba45 100644 --- a/configs/olimexino-stm32/smallnsh/defconfig +++ b/configs/olimexino-stm32/smallnsh/defconfig @@ -760,7 +760,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/olimexino-stm32/tiny/defconfig b/configs/olimexino-stm32/tiny/defconfig index 60ea1b64a7..5940eb260c 100644 --- a/configs/olimexino-stm32/tiny/defconfig +++ b/configs/olimexino-stm32/tiny/defconfig @@ -765,7 +765,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/open1788/knsh/defconfig b/configs/open1788/knsh/defconfig index 42f45c7b05..c304ff0464 100644 --- a/configs/open1788/knsh/defconfig +++ b/configs/open1788/knsh/defconfig @@ -494,7 +494,6 @@ CONFIG_PIPES=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/open1788/nsh/defconfig b/configs/open1788/nsh/defconfig index 97b91ad2eb..2f155a49d0 100644 --- a/configs/open1788/nsh/defconfig +++ b/configs/open1788/nsh/defconfig @@ -490,7 +490,6 @@ CONFIG_PIPES=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/open1788/nxlines/defconfig b/configs/open1788/nxlines/defconfig index 4fe9369eff..5abe3e6aa0 100644 --- a/configs/open1788/nxlines/defconfig +++ b/configs/open1788/nxlines/defconfig @@ -522,7 +522,6 @@ CONFIG_PIPES=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/p112/ostest/defconfig b/configs/p112/ostest/defconfig index 7c5b119941..56ea350bf4 100644 --- a/configs/p112/ostest/defconfig +++ b/configs/p112/ostest/defconfig @@ -271,7 +271,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_16550_UART is not set diff --git a/configs/pcblogic-pic32mx/nsh/defconfig b/configs/pcblogic-pic32mx/nsh/defconfig index 32b0908358..8b93eb5cc4 100644 --- a/configs/pcblogic-pic32mx/nsh/defconfig +++ b/configs/pcblogic-pic32mx/nsh/defconfig @@ -495,7 +495,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/pcduino-a10/nsh/defconfig b/configs/pcduino-a10/nsh/defconfig index c2bcbc0772..db630aab6d 100644 --- a/configs/pcduino-a10/nsh/defconfig +++ b/configs/pcduino-a10/nsh/defconfig @@ -474,7 +474,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/pic32mx-starterkit/nsh/defconfig b/configs/pic32mx-starterkit/nsh/defconfig index 7281f362e7..780f215091 100644 --- a/configs/pic32mx-starterkit/nsh/defconfig +++ b/configs/pic32mx-starterkit/nsh/defconfig @@ -539,7 +539,6 @@ CONFIG_MTD=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/pic32mx-starterkit/nsh2/defconfig b/configs/pic32mx-starterkit/nsh2/defconfig index c28f915d1c..1de3487770 100644 --- a/configs/pic32mx-starterkit/nsh2/defconfig +++ b/configs/pic32mx-starterkit/nsh2/defconfig @@ -603,7 +603,6 @@ CONFIG_ETH0_PHY_DP83848C=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/pic32mx7mmb/nsh/defconfig b/configs/pic32mx7mmb/nsh/defconfig index 75ff18d6d0..7b0660e986 100644 --- a/configs/pic32mx7mmb/nsh/defconfig +++ b/configs/pic32mx7mmb/nsh/defconfig @@ -622,7 +622,6 @@ CONFIG_ETH0_PHY_LAN8720=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/pic32mz-starterkit/nsh/defconfig b/configs/pic32mz-starterkit/nsh/defconfig index 9368fa716d..b64f33c262 100644 --- a/configs/pic32mz-starterkit/nsh/defconfig +++ b/configs/pic32mz-starterkit/nsh/defconfig @@ -466,7 +466,6 @@ CONFIG_MTD=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/qemu-i486/nsh/defconfig b/configs/qemu-i486/nsh/defconfig index 36683c23fb..dc240aa19a 100644 --- a/configs/qemu-i486/nsh/defconfig +++ b/configs/qemu-i486/nsh/defconfig @@ -238,7 +238,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set CONFIG_16550_UART=y diff --git a/configs/qemu-i486/ostest/defconfig b/configs/qemu-i486/ostest/defconfig index bddc708e7d..b205650b6c 100644 --- a/configs/qemu-i486/ostest/defconfig +++ b/configs/qemu-i486/ostest/defconfig @@ -237,7 +237,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_16550_UART is not set diff --git a/configs/sabre-6quad/nsh/defconfig b/configs/sabre-6quad/nsh/defconfig index daa1d8b791..41a976f714 100644 --- a/configs/sabre-6quad/nsh/defconfig +++ b/configs/sabre-6quad/nsh/defconfig @@ -448,7 +448,6 @@ CONFIG_DEV_ZERO=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sabre-6quad/smp/defconfig b/configs/sabre-6quad/smp/defconfig index 3ddf587c09..e9e22fc45f 100644 --- a/configs/sabre-6quad/smp/defconfig +++ b/configs/sabre-6quad/smp/defconfig @@ -454,7 +454,6 @@ CONFIG_DEV_ZERO=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sam3u-ek/knsh/defconfig b/configs/sam3u-ek/knsh/defconfig index 53f3338fcf..23349ef9a8 100644 --- a/configs/sam3u-ek/knsh/defconfig +++ b/configs/sam3u-ek/knsh/defconfig @@ -511,7 +511,6 @@ CONFIG_MMCSD_NSLOTS=1 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sam3u-ek/nsh/defconfig b/configs/sam3u-ek/nsh/defconfig index 424d740a73..0de7635260 100644 --- a/configs/sam3u-ek/nsh/defconfig +++ b/configs/sam3u-ek/nsh/defconfig @@ -496,7 +496,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sam3u-ek/nx/defconfig b/configs/sam3u-ek/nx/defconfig index 1cdcce9d1c..87b7722e88 100644 --- a/configs/sam3u-ek/nx/defconfig +++ b/configs/sam3u-ek/nx/defconfig @@ -536,7 +536,6 @@ CONFIG_LCD_PORTRAIT=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sam3u-ek/nxwm/defconfig b/configs/sam3u-ek/nxwm/defconfig index 8002fb2885..c0e70052c1 100644 --- a/configs/sam3u-ek/nxwm/defconfig +++ b/configs/sam3u-ek/nxwm/defconfig @@ -580,7 +580,6 @@ CONFIG_LCD_LANDSCAPE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sam4cmp-db/nsh/defconfig b/configs/sam4cmp-db/nsh/defconfig index 9175b32a13..118b123cef 100644 --- a/configs/sam4cmp-db/nsh/defconfig +++ b/configs/sam4cmp-db/nsh/defconfig @@ -522,7 +522,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sam4e-ek/nsh/defconfig b/configs/sam4e-ek/nsh/defconfig index 264bd8063b..fa0dcfdf16 100644 --- a/configs/sam4e-ek/nsh/defconfig +++ b/configs/sam4e-ek/nsh/defconfig @@ -642,7 +642,6 @@ CONFIG_ETH0_PHY_KSZ8051=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sam4e-ek/nxwm/defconfig b/configs/sam4e-ek/nxwm/defconfig index e5bf010054..e4a4a5a664 100644 --- a/configs/sam4e-ek/nxwm/defconfig +++ b/configs/sam4e-ek/nxwm/defconfig @@ -701,7 +701,6 @@ CONFIG_ETH0_PHY_KSZ8051=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sam4e-ek/usbnsh/defconfig b/configs/sam4e-ek/usbnsh/defconfig index 717b13c4d2..4a65eb790b 100644 --- a/configs/sam4e-ek/usbnsh/defconfig +++ b/configs/sam4e-ek/usbnsh/defconfig @@ -647,7 +647,6 @@ CONFIG_ETH0_PHY_KSZ8051=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_SERIAL_REMOVABLE=y # CONFIG_SERIAL_CONSOLE is not set diff --git a/configs/sam4l-xplained/nsh/defconfig b/configs/sam4l-xplained/nsh/defconfig index e08bac68fd..a4d744bbf5 100644 --- a/configs/sam4l-xplained/nsh/defconfig +++ b/configs/sam4l-xplained/nsh/defconfig @@ -514,7 +514,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sam4s-xplained-pro/nsh/defconfig b/configs/sam4s-xplained-pro/nsh/defconfig index d81f101294..bd98575c00 100644 --- a/configs/sam4s-xplained-pro/nsh/defconfig +++ b/configs/sam4s-xplained-pro/nsh/defconfig @@ -580,7 +580,6 @@ CONFIG_DEV_FIFO_SIZE=1024 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set CONFIG_SERIAL_REMOVABLE=y diff --git a/configs/sam4s-xplained/nsh/defconfig b/configs/sam4s-xplained/nsh/defconfig index 87f20e61a7..5120854680 100644 --- a/configs/sam4s-xplained/nsh/defconfig +++ b/configs/sam4s-xplained/nsh/defconfig @@ -494,7 +494,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sama5d2-xult/nsh/defconfig b/configs/sama5d2-xult/nsh/defconfig index 424cc780d1..bfd5cf964a 100644 --- a/configs/sama5d2-xult/nsh/defconfig +++ b/configs/sama5d2-xult/nsh/defconfig @@ -577,7 +577,6 @@ CONFIG_RTC_DATETIME=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sama5d3-xplained/bridge/defconfig b/configs/sama5d3-xplained/bridge/defconfig index 5fdf2964d7..ca9a6b5b22 100644 --- a/configs/sama5d3-xplained/bridge/defconfig +++ b/configs/sama5d3-xplained/bridge/defconfig @@ -633,7 +633,6 @@ CONFIG_ETH1_PHY_KSZ8081=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sama5d3-xplained/nsh/defconfig b/configs/sama5d3-xplained/nsh/defconfig index 930ffa3db4..8646ca8b03 100644 --- a/configs/sama5d3-xplained/nsh/defconfig +++ b/configs/sama5d3-xplained/nsh/defconfig @@ -532,7 +532,6 @@ CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sama5d3x-ek/demo/defconfig b/configs/sama5d3x-ek/demo/defconfig index 761e7ae57c..b0e5384d27 100644 --- a/configs/sama5d3x-ek/demo/defconfig +++ b/configs/sama5d3x-ek/demo/defconfig @@ -658,7 +658,6 @@ CONFIG_AT25_SPIFREQUENCY=10000000 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sama5d3x-ek/hello/defconfig b/configs/sama5d3x-ek/hello/defconfig index b5127834f8..d4ab562020 100644 --- a/configs/sama5d3x-ek/hello/defconfig +++ b/configs/sama5d3x-ek/hello/defconfig @@ -513,7 +513,6 @@ CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sama5d3x-ek/norboot/defconfig b/configs/sama5d3x-ek/norboot/defconfig index 29022a34d3..11eedfe99a 100644 --- a/configs/sama5d3x-ek/norboot/defconfig +++ b/configs/sama5d3x-ek/norboot/defconfig @@ -527,7 +527,6 @@ CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sama5d3x-ek/nsh/defconfig b/configs/sama5d3x-ek/nsh/defconfig index dbace7c89c..b3140774af 100644 --- a/configs/sama5d3x-ek/nsh/defconfig +++ b/configs/sama5d3x-ek/nsh/defconfig @@ -531,7 +531,6 @@ CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sama5d3x-ek/nx/defconfig b/configs/sama5d3x-ek/nx/defconfig index 3532962812..b67a145dfc 100644 --- a/configs/sama5d3x-ek/nx/defconfig +++ b/configs/sama5d3x-ek/nx/defconfig @@ -587,7 +587,6 @@ CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sama5d3x-ek/nxplayer/defconfig b/configs/sama5d3x-ek/nxplayer/defconfig index c9c7526992..00b2d5479d 100644 --- a/configs/sama5d3x-ek/nxplayer/defconfig +++ b/configs/sama5d3x-ek/nxplayer/defconfig @@ -628,7 +628,6 @@ CONFIG_SDIO_BLOCKSETUP=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sama5d3x-ek/nxwm/defconfig b/configs/sama5d3x-ek/nxwm/defconfig index a0abcb828d..5c873be148 100644 --- a/configs/sama5d3x-ek/nxwm/defconfig +++ b/configs/sama5d3x-ek/nxwm/defconfig @@ -642,7 +642,6 @@ CONFIG_INPUT=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sama5d3x-ek/ov2640/defconfig b/configs/sama5d3x-ek/ov2640/defconfig index 95ea0ac9ad..c0d64cc771 100644 --- a/configs/sama5d3x-ek/ov2640/defconfig +++ b/configs/sama5d3x-ek/ov2640/defconfig @@ -598,7 +598,6 @@ CONFIG_OV2640_SVGA_RESOLUTION=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sama5d4-ek/at25boot/defconfig b/configs/sama5d4-ek/at25boot/defconfig index d7290202de..57b32544cd 100644 --- a/configs/sama5d4-ek/at25boot/defconfig +++ b/configs/sama5d4-ek/at25boot/defconfig @@ -597,7 +597,6 @@ CONFIG_AT25_SPIFREQUENCY=20000000 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sama5d4-ek/bridge/defconfig b/configs/sama5d4-ek/bridge/defconfig index ca94b121e1..d723f24150 100644 --- a/configs/sama5d4-ek/bridge/defconfig +++ b/configs/sama5d4-ek/bridge/defconfig @@ -651,7 +651,6 @@ CONFIG_ETH1_PHY_KSZ8081=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sama5d4-ek/dramboot/defconfig b/configs/sama5d4-ek/dramboot/defconfig index 2fadab3a1c..8ca250d5d3 100644 --- a/configs/sama5d4-ek/dramboot/defconfig +++ b/configs/sama5d4-ek/dramboot/defconfig @@ -549,7 +549,6 @@ CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sama5d4-ek/elf/defconfig b/configs/sama5d4-ek/elf/defconfig index 0c51be98ea..7382750412 100644 --- a/configs/sama5d4-ek/elf/defconfig +++ b/configs/sama5d4-ek/elf/defconfig @@ -576,7 +576,6 @@ CONFIG_AUDIO_DEVICES=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sama5d4-ek/ipv6/defconfig b/configs/sama5d4-ek/ipv6/defconfig index 7d2d826b28..434147e369 100644 --- a/configs/sama5d4-ek/ipv6/defconfig +++ b/configs/sama5d4-ek/ipv6/defconfig @@ -787,7 +787,6 @@ CONFIG_ETH0_PHY_KSZ8081=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sama5d4-ek/knsh/defconfig b/configs/sama5d4-ek/knsh/defconfig index b0fd035fad..feeeb88157 100644 --- a/configs/sama5d4-ek/knsh/defconfig +++ b/configs/sama5d4-ek/knsh/defconfig @@ -605,7 +605,6 @@ CONFIG_SDIO_BLOCKSETUP=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sama5d4-ek/knsh/defconfig.ROMFS b/configs/sama5d4-ek/knsh/defconfig.ROMFS index 91d49d841b..047303d132 100644 --- a/configs/sama5d4-ek/knsh/defconfig.ROMFS +++ b/configs/sama5d4-ek/knsh/defconfig.ROMFS @@ -481,7 +481,6 @@ CONFIG_RTC_DATETIME=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set diff --git a/configs/sama5d4-ek/nsh/defconfig b/configs/sama5d4-ek/nsh/defconfig index 22b8c8931e..a169aa669c 100644 --- a/configs/sama5d4-ek/nsh/defconfig +++ b/configs/sama5d4-ek/nsh/defconfig @@ -789,7 +789,6 @@ CONFIG_ETH0_PHY_KSZ8081=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sama5d4-ek/nxwm/defconfig b/configs/sama5d4-ek/nxwm/defconfig index 4f3a2904f7..a6987f8f8b 100644 --- a/configs/sama5d4-ek/nxwm/defconfig +++ b/configs/sama5d4-ek/nxwm/defconfig @@ -758,7 +758,6 @@ CONFIG_ETH0_PHY_KSZ8081=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sama5d4-ek/ramtest/defconfig b/configs/sama5d4-ek/ramtest/defconfig index e17821e104..e76da62faa 100644 --- a/configs/sama5d4-ek/ramtest/defconfig +++ b/configs/sama5d4-ek/ramtest/defconfig @@ -549,7 +549,6 @@ CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/samd20-xplained/nsh/defconfig b/configs/samd20-xplained/nsh/defconfig index ecb302a397..a91d464767 100644 --- a/configs/samd20-xplained/nsh/defconfig +++ b/configs/samd20-xplained/nsh/defconfig @@ -476,7 +476,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/samd21-xplained/nsh/defconfig b/configs/samd21-xplained/nsh/defconfig index 08e9d330ec..3181a18cfe 100644 --- a/configs/samd21-xplained/nsh/defconfig +++ b/configs/samd21-xplained/nsh/defconfig @@ -474,7 +474,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/same70-xplained/netnsh/defconfig b/configs/same70-xplained/netnsh/defconfig index 0069f726ac..c2d2a2401b 100644 --- a/configs/same70-xplained/netnsh/defconfig +++ b/configs/same70-xplained/netnsh/defconfig @@ -688,7 +688,6 @@ CONFIG_ETH0_PHY_KSZ8081=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/same70-xplained/nsh/defconfig b/configs/same70-xplained/nsh/defconfig index 204304f086..c8dc02ad82 100644 --- a/configs/same70-xplained/nsh/defconfig +++ b/configs/same70-xplained/nsh/defconfig @@ -631,7 +631,6 @@ CONFIG_AT25_SPIFREQUENCY=20000000 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/saml21-xplained/nsh/defconfig b/configs/saml21-xplained/nsh/defconfig index 17a9dca981..9d487c68b0 100644 --- a/configs/saml21-xplained/nsh/defconfig +++ b/configs/saml21-xplained/nsh/defconfig @@ -462,7 +462,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/samv71-xult/knsh/defconfig b/configs/samv71-xult/knsh/defconfig index a405803266..2c7189db7c 100644 --- a/configs/samv71-xult/knsh/defconfig +++ b/configs/samv71-xult/knsh/defconfig @@ -634,7 +634,6 @@ CONFIG_AT25_SPIFREQUENCY=20000000 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/samv71-xult/module/defconfig b/configs/samv71-xult/module/defconfig index daea087771..f4e7afb959 100644 --- a/configs/samv71-xult/module/defconfig +++ b/configs/samv71-xult/module/defconfig @@ -542,7 +542,6 @@ CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/samv71-xult/mxtxplnd/defconfig b/configs/samv71-xult/mxtxplnd/defconfig index e55210e0e6..49cbf5f29f 100644 --- a/configs/samv71-xult/mxtxplnd/defconfig +++ b/configs/samv71-xult/mxtxplnd/defconfig @@ -675,7 +675,6 @@ CONFIG_AT25_SPIFREQUENCY=20000000 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/samv71-xult/netnsh/defconfig b/configs/samv71-xult/netnsh/defconfig index c533a146e1..37be93f688 100644 --- a/configs/samv71-xult/netnsh/defconfig +++ b/configs/samv71-xult/netnsh/defconfig @@ -691,7 +691,6 @@ CONFIG_ETH0_PHY_KSZ8061=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/samv71-xult/nsh/defconfig b/configs/samv71-xult/nsh/defconfig index 4d49b5ca61..e10517c26c 100644 --- a/configs/samv71-xult/nsh/defconfig +++ b/configs/samv71-xult/nsh/defconfig @@ -634,7 +634,6 @@ CONFIG_AT25_SPIFREQUENCY=20000000 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/samv71-xult/nxwm/defconfig b/configs/samv71-xult/nxwm/defconfig index e6d80b7d9a..5ea82c1a85 100644 --- a/configs/samv71-xult/nxwm/defconfig +++ b/configs/samv71-xult/nxwm/defconfig @@ -678,7 +678,6 @@ CONFIG_AT25_SPIFREQUENCY=20000000 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/samv71-xult/vnc/defconfig b/configs/samv71-xult/vnc/defconfig index c6f2a7aa48..d01ad46b86 100644 --- a/configs/samv71-xult/vnc/defconfig +++ b/configs/samv71-xult/vnc/defconfig @@ -692,7 +692,6 @@ CONFIG_ETH0_PHY_KSZ8061=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/samv71-xult/vnxwm/defconfig b/configs/samv71-xult/vnxwm/defconfig index e2eea5f424..87e57d38fb 100644 --- a/configs/samv71-xult/vnxwm/defconfig +++ b/configs/samv71-xult/vnxwm/defconfig @@ -695,7 +695,6 @@ CONFIG_ETH0_PHY_KSZ8061=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/shenzhou/nsh/defconfig b/configs/shenzhou/nsh/defconfig index af69c7abfa..aa0359c9db 100644 --- a/configs/shenzhou/nsh/defconfig +++ b/configs/shenzhou/nsh/defconfig @@ -825,7 +825,6 @@ CONFIG_ETH0_PHY_DM9161=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/shenzhou/nxwm/defconfig b/configs/shenzhou/nxwm/defconfig index e3b6e5d788..ecab569fe4 100644 --- a/configs/shenzhou/nxwm/defconfig +++ b/configs/shenzhou/nxwm/defconfig @@ -888,7 +888,6 @@ CONFIG_ETH0_PHY_DM9161=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/shenzhou/thttpd/defconfig b/configs/shenzhou/thttpd/defconfig index f246239d2f..fcd1ac4074 100644 --- a/configs/shenzhou/thttpd/defconfig +++ b/configs/shenzhou/thttpd/defconfig @@ -855,7 +855,6 @@ CONFIG_DEV_FIFO_SIZE=1024 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sim/bas/defconfig b/configs/sim/bas/defconfig index 9b11ad5947..71c6bf6659 100644 --- a/configs/sim/bas/defconfig +++ b/configs/sim/bas/defconfig @@ -298,7 +298,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set diff --git a/configs/sim/configdata/defconfig b/configs/sim/configdata/defconfig index 6a58a5c9e9..c46b145c61 100644 --- a/configs/sim/configdata/defconfig +++ b/configs/sim/configdata/defconfig @@ -327,7 +327,6 @@ CONFIG_RAMMTD_FLASHSIM=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sim/cxxtest/defconfig b/configs/sim/cxxtest/defconfig index 7ecdc39504..de26a571ac 100644 --- a/configs/sim/cxxtest/defconfig +++ b/configs/sim/cxxtest/defconfig @@ -315,7 +315,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sim/minibasic/defconfig b/configs/sim/minibasic/defconfig index b7a6e11eae..edeba61d18 100644 --- a/configs/sim/minibasic/defconfig +++ b/configs/sim/minibasic/defconfig @@ -352,7 +352,6 @@ CONFIG_DEV_LOOP=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sim/mount/defconfig b/configs/sim/mount/defconfig index 14234058c0..9af8bfff48 100644 --- a/configs/sim/mount/defconfig +++ b/configs/sim/mount/defconfig @@ -314,7 +314,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sim/mtdpart/defconfig b/configs/sim/mtdpart/defconfig index a9e8cb82f9..b594447333 100644 --- a/configs/sim/mtdpart/defconfig +++ b/configs/sim/mtdpart/defconfig @@ -325,7 +325,6 @@ CONFIG_RAMMTD_FLASHSIM=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sim/mtdrwb/defconfig b/configs/sim/mtdrwb/defconfig index 4a24af5075..3716ffcb22 100644 --- a/configs/sim/mtdrwb/defconfig +++ b/configs/sim/mtdrwb/defconfig @@ -357,7 +357,6 @@ CONFIG_RAMMTD_FLASHSIM=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sim/nettest/defconfig b/configs/sim/nettest/defconfig index 7bce3f6cb1..09df2684d6 100644 --- a/configs/sim/nettest/defconfig +++ b/configs/sim/nettest/defconfig @@ -327,7 +327,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sim/nsh/defconfig b/configs/sim/nsh/defconfig index b7b881c136..26c5503422 100644 --- a/configs/sim/nsh/defconfig +++ b/configs/sim/nsh/defconfig @@ -334,7 +334,6 @@ CONFIG_DEV_LOOP=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sim/nsh2/defconfig b/configs/sim/nsh2/defconfig index 320355597b..3101ea4785 100644 --- a/configs/sim/nsh2/defconfig +++ b/configs/sim/nsh2/defconfig @@ -343,7 +343,6 @@ CONFIG_INPUT=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sim/nx/defconfig b/configs/sim/nx/defconfig index b205eadbdc..c596a93fa5 100644 --- a/configs/sim/nx/defconfig +++ b/configs/sim/nx/defconfig @@ -329,7 +329,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sim/nx11/defconfig b/configs/sim/nx11/defconfig index d845ca9349..f6c56ac9ae 100644 --- a/configs/sim/nx11/defconfig +++ b/configs/sim/nx11/defconfig @@ -330,7 +330,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sim/nxffs/defconfig b/configs/sim/nxffs/defconfig index fb1252ac6e..fb70a4df9b 100644 --- a/configs/sim/nxffs/defconfig +++ b/configs/sim/nxffs/defconfig @@ -296,7 +296,6 @@ CONFIG_RAMMTD_FLASHSIM=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set diff --git a/configs/sim/nxlines/defconfig b/configs/sim/nxlines/defconfig index 9b82cf3586..c80c0efaa9 100644 --- a/configs/sim/nxlines/defconfig +++ b/configs/sim/nxlines/defconfig @@ -305,7 +305,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set diff --git a/configs/sim/nxwm/defconfig b/configs/sim/nxwm/defconfig index ab478684c3..0748c0164f 100644 --- a/configs/sim/nxwm/defconfig +++ b/configs/sim/nxwm/defconfig @@ -341,7 +341,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sim/ostest/defconfig b/configs/sim/ostest/defconfig index 089a488da3..e3570e0481 100644 --- a/configs/sim/ostest/defconfig +++ b/configs/sim/ostest/defconfig @@ -327,7 +327,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sim/pashello/defconfig b/configs/sim/pashello/defconfig index ad3b274ceb..b64438c27e 100644 --- a/configs/sim/pashello/defconfig +++ b/configs/sim/pashello/defconfig @@ -288,7 +288,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set diff --git a/configs/sim/touchscreen/defconfig b/configs/sim/touchscreen/defconfig index e5427ff736..66e90503f5 100644 --- a/configs/sim/touchscreen/defconfig +++ b/configs/sim/touchscreen/defconfig @@ -338,7 +338,6 @@ CONFIG_INPUT=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sim/traveler/defconfig b/configs/sim/traveler/defconfig index 14f3aa4719..3a6a75c03c 100644 --- a/configs/sim/traveler/defconfig +++ b/configs/sim/traveler/defconfig @@ -344,7 +344,6 @@ CONFIG_AJOYSTICK=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sim/udgram/defconfig b/configs/sim/udgram/defconfig index 6a41938192..856d330290 100644 --- a/configs/sim/udgram/defconfig +++ b/configs/sim/udgram/defconfig @@ -339,7 +339,6 @@ CONFIG_DEV_FIFO_SIZE=1024 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sim/unionfs/defconfig b/configs/sim/unionfs/defconfig index 77da0ebc32..0fea09b8d3 100644 --- a/configs/sim/unionfs/defconfig +++ b/configs/sim/unionfs/defconfig @@ -298,7 +298,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set diff --git a/configs/sim/ustream/defconfig b/configs/sim/ustream/defconfig index b61d8b04a7..e356f4bbac 100644 --- a/configs/sim/ustream/defconfig +++ b/configs/sim/ustream/defconfig @@ -339,7 +339,6 @@ CONFIG_DEV_FIFO_SIZE=1024 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/skp16c26/ostest/defconfig b/configs/skp16c26/ostest/defconfig index b46a95b90d..61814e3a1c 100644 --- a/configs/skp16c26/ostest/defconfig +++ b/configs/skp16c26/ostest/defconfig @@ -253,7 +253,6 @@ CONFIG_LCD_LANDSCAPE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_16550_UART is not set diff --git a/configs/spark/composite/defconfig b/configs/spark/composite/defconfig index 99da95b423..d192166cef 100644 --- a/configs/spark/composite/defconfig +++ b/configs/spark/composite/defconfig @@ -773,7 +773,6 @@ CONFIG_SST25_SECTOR512=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set CONFIG_SERIAL_REMOVABLE=y diff --git a/configs/spark/nsh/defconfig b/configs/spark/nsh/defconfig index c86b4a81bb..5f8d3daac6 100644 --- a/configs/spark/nsh/defconfig +++ b/configs/spark/nsh/defconfig @@ -773,7 +773,6 @@ CONFIG_SST25_SECTOR512=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set CONFIG_SERIAL_REMOVABLE=y diff --git a/configs/spark/usbmsc/defconfig b/configs/spark/usbmsc/defconfig index aede0e5bd1..dfd2fda659 100644 --- a/configs/spark/usbmsc/defconfig +++ b/configs/spark/usbmsc/defconfig @@ -773,7 +773,6 @@ CONFIG_SST25_SECTOR512=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/spark/usbnsh/defconfig b/configs/spark/usbnsh/defconfig index bd658acc0f..9af591a0f5 100644 --- a/configs/spark/usbnsh/defconfig +++ b/configs/spark/usbnsh/defconfig @@ -774,7 +774,6 @@ CONFIG_SST25_SPIFREQUENCY=20000000 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_SERIAL_REMOVABLE=y # CONFIG_SERIAL_CONSOLE is not set diff --git a/configs/spark/usbserial/defconfig b/configs/spark/usbserial/defconfig index cf1548ef7d..2bbed930a3 100644 --- a/configs/spark/usbserial/defconfig +++ b/configs/spark/usbserial/defconfig @@ -778,7 +778,6 @@ CONFIG_SST25_SECTOR512=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set CONFIG_SERIAL_REMOVABLE=y diff --git a/configs/stm3210e-eval/composite/defconfig b/configs/stm3210e-eval/composite/defconfig index e86878eb0b..0d9c189726 100644 --- a/configs/stm3210e-eval/composite/defconfig +++ b/configs/stm3210e-eval/composite/defconfig @@ -801,7 +801,6 @@ CONFIG_MTD=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set CONFIG_SERIAL_REMOVABLE=y diff --git a/configs/stm3210e-eval/nsh/defconfig b/configs/stm3210e-eval/nsh/defconfig index 9cd76a6fcf..6e963ddd3d 100644 --- a/configs/stm3210e-eval/nsh/defconfig +++ b/configs/stm3210e-eval/nsh/defconfig @@ -802,7 +802,6 @@ CONFIG_MTD=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm3210e-eval/nsh2/defconfig b/configs/stm3210e-eval/nsh2/defconfig index ed2f9de53a..22a4433f22 100644 --- a/configs/stm3210e-eval/nsh2/defconfig +++ b/configs/stm3210e-eval/nsh2/defconfig @@ -855,7 +855,6 @@ CONFIG_MTD=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm3210e-eval/nx/defconfig b/configs/stm3210e-eval/nx/defconfig index 515abea738..d7eb099f52 100644 --- a/configs/stm3210e-eval/nx/defconfig +++ b/configs/stm3210e-eval/nx/defconfig @@ -793,7 +793,6 @@ CONFIG_LCD_RPORTRAIT=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm3210e-eval/nxterm/defconfig b/configs/stm3210e-eval/nxterm/defconfig index f8b261f023..ffb7dc3e2d 100644 --- a/configs/stm3210e-eval/nxterm/defconfig +++ b/configs/stm3210e-eval/nxterm/defconfig @@ -786,7 +786,6 @@ CONFIG_LCD_LANDSCAPE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm3210e-eval/pm/defconfig b/configs/stm3210e-eval/pm/defconfig index 2ea8dc6299..aa84118fb7 100644 --- a/configs/stm3210e-eval/pm/defconfig +++ b/configs/stm3210e-eval/pm/defconfig @@ -828,7 +828,6 @@ CONFIG_PM_SLEEPEXIT_THRESH=2 CONFIG_PM_SLEEPENTER_COUNT=70 # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm3210e-eval/usbmsc/defconfig b/configs/stm3210e-eval/usbmsc/defconfig index 5afafd6fe6..988055ebab 100644 --- a/configs/stm3210e-eval/usbmsc/defconfig +++ b/configs/stm3210e-eval/usbmsc/defconfig @@ -763,7 +763,6 @@ CONFIG_SDIO_PREFLIGHT=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm3210e-eval/usbserial/defconfig b/configs/stm3210e-eval/usbserial/defconfig index db0f50e033..d6cd26bde2 100644 --- a/configs/stm3210e-eval/usbserial/defconfig +++ b/configs/stm3210e-eval/usbserial/defconfig @@ -738,7 +738,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set CONFIG_SERIAL_REMOVABLE=y diff --git a/configs/stm3220g-eval/dhcpd/defconfig b/configs/stm3220g-eval/dhcpd/defconfig index 6c75dfc4de..79a0512054 100644 --- a/configs/stm3220g-eval/dhcpd/defconfig +++ b/configs/stm3220g-eval/dhcpd/defconfig @@ -799,7 +799,6 @@ CONFIG_ETH0_PHY_DP83848C=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm3220g-eval/nettest/defconfig b/configs/stm3220g-eval/nettest/defconfig index cd5e76b2e9..41df74c759 100644 --- a/configs/stm3220g-eval/nettest/defconfig +++ b/configs/stm3220g-eval/nettest/defconfig @@ -800,7 +800,6 @@ CONFIG_ETH0_PHY_DP83848C=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm3220g-eval/nsh/defconfig b/configs/stm3220g-eval/nsh/defconfig index 0bf15bd471..29cbdf4d71 100644 --- a/configs/stm3220g-eval/nsh/defconfig +++ b/configs/stm3220g-eval/nsh/defconfig @@ -866,7 +866,6 @@ CONFIG_ETH0_PHY_DP83848C=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm3220g-eval/nsh2/defconfig b/configs/stm3220g-eval/nsh2/defconfig index 756d46ec97..277d815547 100644 --- a/configs/stm3220g-eval/nsh2/defconfig +++ b/configs/stm3220g-eval/nsh2/defconfig @@ -873,7 +873,6 @@ CONFIG_ETH0_PHY_DP83848C=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_SERIAL_REMOVABLE is not set # CONFIG_SERIAL_CONSOLE is not set diff --git a/configs/stm3220g-eval/nxwm/defconfig b/configs/stm3220g-eval/nxwm/defconfig index 00be7789aa..70f3be0871 100644 --- a/configs/stm3220g-eval/nxwm/defconfig +++ b/configs/stm3220g-eval/nxwm/defconfig @@ -909,7 +909,6 @@ CONFIG_ETH0_PHY_DP83848C=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm3220g-eval/telnetd/defconfig b/configs/stm3220g-eval/telnetd/defconfig index 8087eefa4c..c096d97f0e 100644 --- a/configs/stm3220g-eval/telnetd/defconfig +++ b/configs/stm3220g-eval/telnetd/defconfig @@ -802,7 +802,6 @@ CONFIG_ETH0_PHY_DP83848C=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm3240g-eval/dhcpd/defconfig b/configs/stm3240g-eval/dhcpd/defconfig index e853770ca0..9144444845 100644 --- a/configs/stm3240g-eval/dhcpd/defconfig +++ b/configs/stm3240g-eval/dhcpd/defconfig @@ -803,7 +803,6 @@ CONFIG_ETH0_PHY_DP83848C=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm3240g-eval/discover/defconfig b/configs/stm3240g-eval/discover/defconfig index 3173ed20d7..f51ac02cc1 100644 --- a/configs/stm3240g-eval/discover/defconfig +++ b/configs/stm3240g-eval/discover/defconfig @@ -826,7 +826,6 @@ CONFIG_ETH0_PHY_DP83848C=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm3240g-eval/knxwm/defconfig b/configs/stm3240g-eval/knxwm/defconfig index c5d466cc75..55af319147 100644 --- a/configs/stm3240g-eval/knxwm/defconfig +++ b/configs/stm3240g-eval/knxwm/defconfig @@ -857,7 +857,6 @@ CONFIG_LCD_LANDSCAPE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm3240g-eval/nettest/defconfig b/configs/stm3240g-eval/nettest/defconfig index ee8324e9d5..6ada351475 100644 --- a/configs/stm3240g-eval/nettest/defconfig +++ b/configs/stm3240g-eval/nettest/defconfig @@ -804,7 +804,6 @@ CONFIG_ETH0_PHY_DP83848C=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm3240g-eval/nsh/defconfig b/configs/stm3240g-eval/nsh/defconfig index 0215da9426..52a2e2b6ae 100644 --- a/configs/stm3240g-eval/nsh/defconfig +++ b/configs/stm3240g-eval/nsh/defconfig @@ -844,7 +844,6 @@ CONFIG_ETH0_PHY_DP83848C=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm3240g-eval/nsh2/defconfig b/configs/stm3240g-eval/nsh2/defconfig index 47b77ad25e..e9d10d9490 100644 --- a/configs/stm3240g-eval/nsh2/defconfig +++ b/configs/stm3240g-eval/nsh2/defconfig @@ -877,7 +877,6 @@ CONFIG_ETH0_PHY_DP83848C=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_SERIAL_REMOVABLE is not set # CONFIG_SERIAL_CONSOLE is not set diff --git a/configs/stm3240g-eval/nxterm/defconfig b/configs/stm3240g-eval/nxterm/defconfig index c8fa345a86..a83753f652 100644 --- a/configs/stm3240g-eval/nxterm/defconfig +++ b/configs/stm3240g-eval/nxterm/defconfig @@ -883,7 +883,6 @@ CONFIG_ETH0_PHY_DP83848C=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm3240g-eval/nxwm/defconfig b/configs/stm3240g-eval/nxwm/defconfig index c1e7c78384..f57abc9254 100644 --- a/configs/stm3240g-eval/nxwm/defconfig +++ b/configs/stm3240g-eval/nxwm/defconfig @@ -906,7 +906,6 @@ CONFIG_ETH0_PHY_NONE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm3240g-eval/telnetd/defconfig b/configs/stm3240g-eval/telnetd/defconfig index afccc0581a..23d37a3970 100644 --- a/configs/stm3240g-eval/telnetd/defconfig +++ b/configs/stm3240g-eval/telnetd/defconfig @@ -806,7 +806,6 @@ CONFIG_ETH0_PHY_DP83848C=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm3240g-eval/webserver/defconfig b/configs/stm3240g-eval/webserver/defconfig index fc5f38129e..98c8514caf 100644 --- a/configs/stm3240g-eval/webserver/defconfig +++ b/configs/stm3240g-eval/webserver/defconfig @@ -865,7 +865,6 @@ CONFIG_ETH0_PHY_NONE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm3240g-eval/xmlrpc/defconfig b/configs/stm3240g-eval/xmlrpc/defconfig index 691149e1cd..c305c0cc18 100644 --- a/configs/stm3240g-eval/xmlrpc/defconfig +++ b/configs/stm3240g-eval/xmlrpc/defconfig @@ -821,7 +821,6 @@ CONFIG_ETH0_PHY_DP83848C=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32_tiny/nsh/defconfig b/configs/stm32_tiny/nsh/defconfig index 7c96533b6e..4c75ba7ed6 100644 --- a/configs/stm32_tiny/nsh/defconfig +++ b/configs/stm32_tiny/nsh/defconfig @@ -728,7 +728,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32_tiny/usbnsh/defconfig b/configs/stm32_tiny/usbnsh/defconfig index 8a254501e2..ddc34f64d2 100644 --- a/configs/stm32_tiny/usbnsh/defconfig +++ b/configs/stm32_tiny/usbnsh/defconfig @@ -706,7 +706,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_SERIAL_REMOVABLE=y CONFIG_SERIAL_CONSOLE=y diff --git a/configs/stm32butterfly2/nsh/defconfig b/configs/stm32butterfly2/nsh/defconfig index c738c08de3..ed2275d4a7 100644 --- a/configs/stm32butterfly2/nsh/defconfig +++ b/configs/stm32butterfly2/nsh/defconfig @@ -777,7 +777,6 @@ CONFIG_MMCSD_SPIMODE=0 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32butterfly2/nshnet/defconfig b/configs/stm32butterfly2/nshnet/defconfig index 3804ac4ff0..43d0054ecd 100644 --- a/configs/stm32butterfly2/nshnet/defconfig +++ b/configs/stm32butterfly2/nshnet/defconfig @@ -827,7 +827,6 @@ CONFIG_DEV_FIFO_SIZE=1024 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set CONFIG_SERIAL_REMOVABLE=y diff --git a/configs/stm32butterfly2/nshusbdev/defconfig b/configs/stm32butterfly2/nshusbdev/defconfig index 2a27dfaed9..602e063375 100644 --- a/configs/stm32butterfly2/nshusbdev/defconfig +++ b/configs/stm32butterfly2/nshusbdev/defconfig @@ -770,7 +770,6 @@ CONFIG_MMCSD_SPIMODE=0 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set CONFIG_SERIAL_REMOVABLE=y diff --git a/configs/stm32butterfly2/nshusbhost/defconfig b/configs/stm32butterfly2/nshusbhost/defconfig index c738c08de3..ed2275d4a7 100644 --- a/configs/stm32butterfly2/nshusbhost/defconfig +++ b/configs/stm32butterfly2/nshusbhost/defconfig @@ -777,7 +777,6 @@ CONFIG_MMCSD_SPIMODE=0 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f103-minimum/audio_tone/defconfig b/configs/stm32f103-minimum/audio_tone/defconfig index 086dad19f5..993a61286b 100644 --- a/configs/stm32f103-minimum/audio_tone/defconfig +++ b/configs/stm32f103-minimum/audio_tone/defconfig @@ -729,7 +729,6 @@ CONFIG_AUDIO_TONE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f103-minimum/buttons/defconfig b/configs/stm32f103-minimum/buttons/defconfig index e5fccea096..a37eab30f7 100644 --- a/configs/stm32f103-minimum/buttons/defconfig +++ b/configs/stm32f103-minimum/buttons/defconfig @@ -726,7 +726,6 @@ CONFIG_BUTTONS_NPOLLWAITERS=2 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f103-minimum/jlx12864g/defconfig b/configs/stm32f103-minimum/jlx12864g/defconfig index 09a91ef88d..b9ff3e625f 100644 --- a/configs/stm32f103-minimum/jlx12864g/defconfig +++ b/configs/stm32f103-minimum/jlx12864g/defconfig @@ -815,7 +815,6 @@ CONFIG_LCD_LANDSCAPE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f103-minimum/nsh/defconfig b/configs/stm32f103-minimum/nsh/defconfig index f2ce954678..f7f96edde2 100644 --- a/configs/stm32f103-minimum/nsh/defconfig +++ b/configs/stm32f103-minimum/nsh/defconfig @@ -709,7 +709,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f103-minimum/pwm/defconfig b/configs/stm32f103-minimum/pwm/defconfig index 021a9fcbd3..5c851766af 100644 --- a/configs/stm32f103-minimum/pwm/defconfig +++ b/configs/stm32f103-minimum/pwm/defconfig @@ -723,7 +723,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f103-minimum/rfid-rc522/defconfig b/configs/stm32f103-minimum/rfid-rc522/defconfig index 03e471615c..13b50d89fc 100644 --- a/configs/stm32f103-minimum/rfid-rc522/defconfig +++ b/configs/stm32f103-minimum/rfid-rc522/defconfig @@ -729,7 +729,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f103-minimum/rgbled/defconfig b/configs/stm32f103-minimum/rgbled/defconfig index f236ee1a63..19ef7948ef 100644 --- a/configs/stm32f103-minimum/rgbled/defconfig +++ b/configs/stm32f103-minimum/rgbled/defconfig @@ -750,7 +750,6 @@ CONFIG_RGBLED=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f103-minimum/usbnsh/defconfig b/configs/stm32f103-minimum/usbnsh/defconfig index 6015311697..5425732ae1 100644 --- a/configs/stm32f103-minimum/usbnsh/defconfig +++ b/configs/stm32f103-minimum/usbnsh/defconfig @@ -706,7 +706,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_SERIAL_REMOVABLE=y CONFIG_SERIAL_CONSOLE=y diff --git a/configs/stm32f103-minimum/userled/defconfig b/configs/stm32f103-minimum/userled/defconfig index fd0a0a857b..ba69602cc6 100644 --- a/configs/stm32f103-minimum/userled/defconfig +++ b/configs/stm32f103-minimum/userled/defconfig @@ -712,7 +712,6 @@ CONFIG_USERLED_LOWER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f103-minimum/veml6070/defconfig b/configs/stm32f103-minimum/veml6070/defconfig index 7ef17b58be..2c73508f80 100644 --- a/configs/stm32f103-minimum/veml6070/defconfig +++ b/configs/stm32f103-minimum/veml6070/defconfig @@ -768,7 +768,6 @@ CONFIG_MS58XX_VDD=30 CONFIG_VEML6070=y # CONFIG_XEN1210 is not set # CONFIG_ZEROCROSS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f3discovery/nsh/defconfig b/configs/stm32f3discovery/nsh/defconfig index f0acc39483..0a4c3b350d 100644 --- a/configs/stm32f3discovery/nsh/defconfig +++ b/configs/stm32f3discovery/nsh/defconfig @@ -727,7 +727,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set CONFIG_SERIAL_REMOVABLE=y diff --git a/configs/stm32f3discovery/usbnsh/defconfig b/configs/stm32f3discovery/usbnsh/defconfig index 9da62c72fd..265bb26eeb 100644 --- a/configs/stm32f3discovery/usbnsh/defconfig +++ b/configs/stm32f3discovery/usbnsh/defconfig @@ -745,7 +745,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_SERIAL_REMOVABLE=y # CONFIG_SERIAL_CONSOLE is not set diff --git a/configs/stm32f411e-disco/nsh/defconfig b/configs/stm32f411e-disco/nsh/defconfig index 6124f39735..16b329ad85 100644 --- a/configs/stm32f411e-disco/nsh/defconfig +++ b/configs/stm32f411e-disco/nsh/defconfig @@ -708,7 +708,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f429i-disco/extflash/defconfig b/configs/stm32f429i-disco/extflash/defconfig index b1661bf394..5d05d32227 100644 --- a/configs/stm32f429i-disco/extflash/defconfig +++ b/configs/stm32f429i-disco/extflash/defconfig @@ -826,7 +826,6 @@ CONFIG_SST25XX_MEMORY_TYPE=0x25 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f429i-disco/lcd/defconfig b/configs/stm32f429i-disco/lcd/defconfig index b799f6048d..49d8da93fc 100644 --- a/configs/stm32f429i-disco/lcd/defconfig +++ b/configs/stm32f429i-disco/lcd/defconfig @@ -806,7 +806,6 @@ CONFIG_LCD_ILI9341_IFACE0_RGB565=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f429i-disco/ltdc/defconfig b/configs/stm32f429i-disco/ltdc/defconfig index 2f398c0057..087b0b89ca 100644 --- a/configs/stm32f429i-disco/ltdc/defconfig +++ b/configs/stm32f429i-disco/ltdc/defconfig @@ -823,7 +823,6 @@ CONFIG_SPI_CMDDATA=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f429i-disco/nsh/defconfig b/configs/stm32f429i-disco/nsh/defconfig index 2d15d01d64..90fa62e4f7 100644 --- a/configs/stm32f429i-disco/nsh/defconfig +++ b/configs/stm32f429i-disco/nsh/defconfig @@ -755,7 +755,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f429i-disco/usbmsc/defconfig b/configs/stm32f429i-disco/usbmsc/defconfig index 6ef99c00e0..8f1fbb5583 100644 --- a/configs/stm32f429i-disco/usbmsc/defconfig +++ b/configs/stm32f429i-disco/usbmsc/defconfig @@ -775,7 +775,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f429i-disco/usbnsh/defconfig b/configs/stm32f429i-disco/usbnsh/defconfig index aa93f546d1..99cfa1b985 100644 --- a/configs/stm32f429i-disco/usbnsh/defconfig +++ b/configs/stm32f429i-disco/usbnsh/defconfig @@ -761,7 +761,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_SERIAL_REMOVABLE=y # CONFIG_SERIAL_CONSOLE is not set diff --git a/configs/stm32f4discovery/canard/defconfig b/configs/stm32f4discovery/canard/defconfig index 339029f3dc..606f95268c 100644 --- a/configs/stm32f4discovery/canard/defconfig +++ b/configs/stm32f4discovery/canard/defconfig @@ -777,7 +777,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f4discovery/cxxtest/defconfig b/configs/stm32f4discovery/cxxtest/defconfig index fe76de0ff3..47aa9ad471 100644 --- a/configs/stm32f4discovery/cxxtest/defconfig +++ b/configs/stm32f4discovery/cxxtest/defconfig @@ -746,7 +746,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f4discovery/elf/defconfig b/configs/stm32f4discovery/elf/defconfig index e2152eff65..a7acd95315 100644 --- a/configs/stm32f4discovery/elf/defconfig +++ b/configs/stm32f4discovery/elf/defconfig @@ -746,7 +746,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f4discovery/ipv6/defconfig b/configs/stm32f4discovery/ipv6/defconfig index 6b6a5021fd..964ec83c84 100644 --- a/configs/stm32f4discovery/ipv6/defconfig +++ b/configs/stm32f4discovery/ipv6/defconfig @@ -866,7 +866,6 @@ CONFIG_ETH0_PHY_LAN8720=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f4discovery/kostest/defconfig b/configs/stm32f4discovery/kostest/defconfig index d0568bac6c..e48549911f 100644 --- a/configs/stm32f4discovery/kostest/defconfig +++ b/configs/stm32f4discovery/kostest/defconfig @@ -754,7 +754,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f4discovery/netnsh/defconfig b/configs/stm32f4discovery/netnsh/defconfig index 93c015c220..7798def2d6 100644 --- a/configs/stm32f4discovery/netnsh/defconfig +++ b/configs/stm32f4discovery/netnsh/defconfig @@ -868,7 +868,6 @@ CONFIG_ETH0_PHY_LAN8720=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f4discovery/nsh/defconfig b/configs/stm32f4discovery/nsh/defconfig index 45b4d516bd..ad989a0384 100644 --- a/configs/stm32f4discovery/nsh/defconfig +++ b/configs/stm32f4discovery/nsh/defconfig @@ -764,7 +764,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f4discovery/nxlines/defconfig b/configs/stm32f4discovery/nxlines/defconfig index 6d0afb67cf..3ea55af740 100644 --- a/configs/stm32f4discovery/nxlines/defconfig +++ b/configs/stm32f4discovery/nxlines/defconfig @@ -799,7 +799,6 @@ CONFIG_LCD_LANDSCAPE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f4discovery/pm/defconfig b/configs/stm32f4discovery/pm/defconfig index 23611818a5..9d31f4d16c 100644 --- a/configs/stm32f4discovery/pm/defconfig +++ b/configs/stm32f4discovery/pm/defconfig @@ -785,7 +785,6 @@ CONFIG_PM_SLEEPEXIT_THRESH=2 CONFIG_PM_SLEEPENTER_COUNT=70 # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f4discovery/posix_spawn/defconfig b/configs/stm32f4discovery/posix_spawn/defconfig index 0b50120eef..6244ecf5de 100644 --- a/configs/stm32f4discovery/posix_spawn/defconfig +++ b/configs/stm32f4discovery/posix_spawn/defconfig @@ -746,7 +746,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f4discovery/pseudoterm/defconfig b/configs/stm32f4discovery/pseudoterm/defconfig index bf893357b4..2e888aa40d 100644 --- a/configs/stm32f4discovery/pseudoterm/defconfig +++ b/configs/stm32f4discovery/pseudoterm/defconfig @@ -764,7 +764,6 @@ CONFIG_DEV_FIFO_SIZE=1024 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f4discovery/rgbled/defconfig b/configs/stm32f4discovery/rgbled/defconfig index cbdcd8a62b..60d084552e 100644 --- a/configs/stm32f4discovery/rgbled/defconfig +++ b/configs/stm32f4discovery/rgbled/defconfig @@ -771,7 +771,6 @@ CONFIG_RGBLED=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f4discovery/uavcan/defconfig b/configs/stm32f4discovery/uavcan/defconfig index 6b16317813..c80096bf72 100644 --- a/configs/stm32f4discovery/uavcan/defconfig +++ b/configs/stm32f4discovery/uavcan/defconfig @@ -716,7 +716,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set # CONFIG_SERIAL is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set diff --git a/configs/stm32f4discovery/usbnsh/defconfig b/configs/stm32f4discovery/usbnsh/defconfig index f526a52b11..b6661f5d88 100644 --- a/configs/stm32f4discovery/usbnsh/defconfig +++ b/configs/stm32f4discovery/usbnsh/defconfig @@ -770,7 +770,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_SERIAL_REMOVABLE=y # CONFIG_SERIAL_CONSOLE is not set diff --git a/configs/stm32f4discovery/winbuild/defconfig b/configs/stm32f4discovery/winbuild/defconfig index 32a5be99c5..a5740592a5 100644 --- a/configs/stm32f4discovery/winbuild/defconfig +++ b/configs/stm32f4discovery/winbuild/defconfig @@ -652,7 +652,6 @@ CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_16550_UART is not set diff --git a/configs/stm32f4discovery/xen1210/defconfig b/configs/stm32f4discovery/xen1210/defconfig index be43bc8716..076a4e5a03 100644 --- a/configs/stm32f4discovery/xen1210/defconfig +++ b/configs/stm32f4discovery/xen1210/defconfig @@ -801,7 +801,6 @@ CONFIG_MS58XX_VDD=30 # CONFIG_QENCODER is not set CONFIG_XEN1210=y # CONFIG_ZEROCROSS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig index c8b5d79c69..46aed04635 100644 --- a/configs/stm32f746-ws/nsh/defconfig +++ b/configs/stm32f746-ws/nsh/defconfig @@ -690,7 +690,6 @@ CONFIG_DEV_FIFO_SIZE=1024 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set CONFIG_SERIAL_REMOVABLE=y diff --git a/configs/stm32f746g-disco/nsh/defconfig b/configs/stm32f746g-disco/nsh/defconfig index aaf5ad642b..80155b308a 100644 --- a/configs/stm32f746g-disco/nsh/defconfig +++ b/configs/stm32f746g-disco/nsh/defconfig @@ -618,7 +618,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32l476-mdk/nsh/defconfig b/configs/stm32l476-mdk/nsh/defconfig index bff1aace3e..57b5c9fd47 100644 --- a/configs/stm32l476-mdk/nsh/defconfig +++ b/configs/stm32l476-mdk/nsh/defconfig @@ -561,7 +561,6 @@ CONFIG_RTC_IOCTL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32l476vg-disco/nsh/defconfig b/configs/stm32l476vg-disco/nsh/defconfig index a341d1ba39..a62de0776c 100644 --- a/configs/stm32l476vg-disco/nsh/defconfig +++ b/configs/stm32l476vg-disco/nsh/defconfig @@ -614,7 +614,6 @@ CONFIG_N25QXXX_SECTOR512=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32ldiscovery/nsh/defconfig b/configs/stm32ldiscovery/nsh/defconfig index ad496c0a98..af6dda6e9a 100644 --- a/configs/stm32ldiscovery/nsh/defconfig +++ b/configs/stm32ldiscovery/nsh/defconfig @@ -706,7 +706,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/stm32vldiscovery/nsh/defconfig b/configs/stm32vldiscovery/nsh/defconfig index ef516541c4..c7ca2ef2c5 100644 --- a/configs/stm32vldiscovery/nsh/defconfig +++ b/configs/stm32vldiscovery/nsh/defconfig @@ -724,7 +724,6 @@ CONFIG_RTC=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sure-pic32mx/nsh/defconfig b/configs/sure-pic32mx/nsh/defconfig index 6934ae6970..7cf509a7bf 100644 --- a/configs/sure-pic32mx/nsh/defconfig +++ b/configs/sure-pic32mx/nsh/defconfig @@ -506,7 +506,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/sure-pic32mx/usbnsh/defconfig b/configs/sure-pic32mx/usbnsh/defconfig index b5dd27d3ed..0a5838887e 100644 --- a/configs/sure-pic32mx/usbnsh/defconfig +++ b/configs/sure-pic32mx/usbnsh/defconfig @@ -508,7 +508,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_SERIAL_REMOVABLE=y # CONFIG_SERIAL_CONSOLE is not set diff --git a/configs/teensy-2.0/hello/defconfig b/configs/teensy-2.0/hello/defconfig index 410aba1b5c..cf6bd2ee38 100644 --- a/configs/teensy-2.0/hello/defconfig +++ b/configs/teensy-2.0/hello/defconfig @@ -300,7 +300,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_16550_UART is not set diff --git a/configs/teensy-2.0/nsh/defconfig b/configs/teensy-2.0/nsh/defconfig index 80afdf009b..a947d314ee 100644 --- a/configs/teensy-2.0/nsh/defconfig +++ b/configs/teensy-2.0/nsh/defconfig @@ -311,7 +311,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set diff --git a/configs/teensy-2.0/usbmsc/defconfig b/configs/teensy-2.0/usbmsc/defconfig index 821868dc61..ed35a4ece2 100644 --- a/configs/teensy-2.0/usbmsc/defconfig +++ b/configs/teensy-2.0/usbmsc/defconfig @@ -333,7 +333,6 @@ CONFIG_MMCSD_SPIMODE=0 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_16550_UART is not set diff --git a/configs/teensy-3.x/nsh/defconfig b/configs/teensy-3.x/nsh/defconfig index 2297c163a2..4712175377 100644 --- a/configs/teensy-3.x/nsh/defconfig +++ b/configs/teensy-3.x/nsh/defconfig @@ -478,7 +478,6 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/teensy-3.x/usbnsh/defconfig b/configs/teensy-3.x/usbnsh/defconfig index 55c2e4509b..8b71905cff 100644 --- a/configs/teensy-3.x/usbnsh/defconfig +++ b/configs/teensy-3.x/usbnsh/defconfig @@ -478,7 +478,6 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set CONFIG_SERIAL_REMOVABLE=y diff --git a/configs/teensy-lc/nsh/defconfig b/configs/teensy-lc/nsh/defconfig index 0b235d0dee..e3e77e208a 100644 --- a/configs/teensy-lc/nsh/defconfig +++ b/configs/teensy-lc/nsh/defconfig @@ -441,7 +441,6 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/tm4c123g-launchpad/nsh/defconfig b/configs/tm4c123g-launchpad/nsh/defconfig index 6cbee2ee05..12288ccbfc 100644 --- a/configs/tm4c123g-launchpad/nsh/defconfig +++ b/configs/tm4c123g-launchpad/nsh/defconfig @@ -499,7 +499,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/tm4c1294-launchpad/ipv6/defconfig b/configs/tm4c1294-launchpad/ipv6/defconfig index 075d74bce2..f016e962aa 100644 --- a/configs/tm4c1294-launchpad/ipv6/defconfig +++ b/configs/tm4c1294-launchpad/ipv6/defconfig @@ -560,7 +560,6 @@ CONFIG_ARCH_PHY_INTERRUPT=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/tm4c1294-launchpad/nsh/defconfig b/configs/tm4c1294-launchpad/nsh/defconfig index d2efadd53b..3c4bcce6eb 100644 --- a/configs/tm4c1294-launchpad/nsh/defconfig +++ b/configs/tm4c1294-launchpad/nsh/defconfig @@ -562,7 +562,6 @@ CONFIG_ARCH_PHY_INTERRUPT=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/twr-k60n512/nsh/defconfig b/configs/twr-k60n512/nsh/defconfig index b6d1a57df0..ddafbe24e9 100644 --- a/configs/twr-k60n512/nsh/defconfig +++ b/configs/twr-k60n512/nsh/defconfig @@ -465,7 +465,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/u-blox-c027/nsh/defconfig b/configs/u-blox-c027/nsh/defconfig index 022c5eec52..b1ca48a213 100644 --- a/configs/u-blox-c027/nsh/defconfig +++ b/configs/u-blox-c027/nsh/defconfig @@ -555,7 +555,6 @@ CONFIG_ETH1_PHY_NONE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/ubw32/nsh/defconfig b/configs/ubw32/nsh/defconfig index 59dee9b713..91b77cebc8 100644 --- a/configs/ubw32/nsh/defconfig +++ b/configs/ubw32/nsh/defconfig @@ -512,7 +512,6 @@ CONFIG_MMCSD_NSLOTS=1 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/us7032evb1/nsh/defconfig b/configs/us7032evb1/nsh/defconfig index d8e8df8334..e64dc02107 100644 --- a/configs/us7032evb1/nsh/defconfig +++ b/configs/us7032evb1/nsh/defconfig @@ -238,7 +238,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set diff --git a/configs/us7032evb1/ostest/defconfig b/configs/us7032evb1/ostest/defconfig index 1beac7ba05..0c196b33de 100644 --- a/configs/us7032evb1/ostest/defconfig +++ b/configs/us7032evb1/ostest/defconfig @@ -237,7 +237,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_16550_UART is not set diff --git a/configs/viewtool-stm32f107/highpri/defconfig b/configs/viewtool-stm32f107/highpri/defconfig index fc3a34b4d9..23206b58e0 100644 --- a/configs/viewtool-stm32f107/highpri/defconfig +++ b/configs/viewtool-stm32f107/highpri/defconfig @@ -737,7 +737,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/viewtool-stm32f107/netnsh/defconfig b/configs/viewtool-stm32f107/netnsh/defconfig index 5a0e0bb858..4c9058eef1 100644 --- a/configs/viewtool-stm32f107/netnsh/defconfig +++ b/configs/viewtool-stm32f107/netnsh/defconfig @@ -795,7 +795,6 @@ CONFIG_ETH0_PHY_DP83848C=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/viewtool-stm32f107/nsh/defconfig b/configs/viewtool-stm32f107/nsh/defconfig index 138757c497..5da2fdda70 100644 --- a/configs/viewtool-stm32f107/nsh/defconfig +++ b/configs/viewtool-stm32f107/nsh/defconfig @@ -734,7 +734,6 @@ CONFIG_ARCH_HAVE_SPI_BITORDER=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/xtrs/nsh/defconfig b/configs/xtrs/nsh/defconfig index aa63aa60f0..18cd15188b 100644 --- a/configs/xtrs/nsh/defconfig +++ b/configs/xtrs/nsh/defconfig @@ -192,7 +192,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set diff --git a/configs/xtrs/ostest/defconfig b/configs/xtrs/ostest/defconfig index 39e06ae357..b03cffef6f 100644 --- a/configs/xtrs/ostest/defconfig +++ b/configs/xtrs/ostest/defconfig @@ -191,7 +191,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_16550_UART is not set diff --git a/configs/xtrs/pashello/defconfig b/configs/xtrs/pashello/defconfig index 324ef07f30..b38652e6c0 100644 --- a/configs/xtrs/pashello/defconfig +++ b/configs/xtrs/pashello/defconfig @@ -192,7 +192,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_16550_UART is not set diff --git a/configs/z16f2800100zcog/nsh/defconfig b/configs/z16f2800100zcog/nsh/defconfig index 94b2c6ff7e..781652bd58 100644 --- a/configs/z16f2800100zcog/nsh/defconfig +++ b/configs/z16f2800100zcog/nsh/defconfig @@ -331,7 +331,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/z16f2800100zcog/ostest/defconfig b/configs/z16f2800100zcog/ostest/defconfig index 99ec6fd098..dec05b3b6c 100644 --- a/configs/z16f2800100zcog/ostest/defconfig +++ b/configs/z16f2800100zcog/ostest/defconfig @@ -331,7 +331,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/z16f2800100zcog/pashello/defconfig b/configs/z16f2800100zcog/pashello/defconfig index 0594e40c9a..04d067caa4 100644 --- a/configs/z16f2800100zcog/pashello/defconfig +++ b/configs/z16f2800100zcog/pashello/defconfig @@ -215,7 +215,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_16550_UART is not set diff --git a/configs/z80sim/nsh/defconfig b/configs/z80sim/nsh/defconfig index cdc9ce0d71..7034fccbf9 100644 --- a/configs/z80sim/nsh/defconfig +++ b/configs/z80sim/nsh/defconfig @@ -192,7 +192,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_16550_UART is not set diff --git a/configs/z80sim/ostest/defconfig b/configs/z80sim/ostest/defconfig index 6184bd8397..f7eb3afd2c 100644 --- a/configs/z80sim/ostest/defconfig +++ b/configs/z80sim/ostest/defconfig @@ -191,7 +191,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_16550_UART is not set diff --git a/configs/z80sim/pashello/defconfig b/configs/z80sim/pashello/defconfig index a2b5d7fb12..6945b3c547 100644 --- a/configs/z80sim/pashello/defconfig +++ b/configs/z80sim/pashello/defconfig @@ -191,7 +191,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_16550_UART is not set diff --git a/configs/z8encore000zco/ostest/defconfig b/configs/z8encore000zco/ostest/defconfig index 79a76d1ba5..7b8c2d79c8 100644 --- a/configs/z8encore000zco/ostest/defconfig +++ b/configs/z8encore000zco/ostest/defconfig @@ -345,7 +345,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/z8f64200100kit/ostest/defconfig b/configs/z8f64200100kit/ostest/defconfig index ec1ca29aba..31c730fc47 100644 --- a/configs/z8f64200100kit/ostest/defconfig +++ b/configs/z8f64200100kit/ostest/defconfig @@ -345,7 +345,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/zkit-arm-1769/hello/defconfig b/configs/zkit-arm-1769/hello/defconfig index dcda1f17fb..f3a86fcb98 100644 --- a/configs/zkit-arm-1769/hello/defconfig +++ b/configs/zkit-arm-1769/hello/defconfig @@ -515,7 +515,6 @@ CONFIG_ETH0_PHY_DP83848C=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/zkit-arm-1769/nsh/defconfig b/configs/zkit-arm-1769/nsh/defconfig index 1d6cc991c1..8a675b6180 100644 --- a/configs/zkit-arm-1769/nsh/defconfig +++ b/configs/zkit-arm-1769/nsh/defconfig @@ -552,7 +552,6 @@ CONFIG_ETH0_PHY_DP83848C=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/zkit-arm-1769/nxhello/defconfig b/configs/zkit-arm-1769/nxhello/defconfig index e2aebc0fed..4c7dfae49f 100644 --- a/configs/zkit-arm-1769/nxhello/defconfig +++ b/configs/zkit-arm-1769/nxhello/defconfig @@ -590,7 +590,6 @@ CONFIG_ETH0_PHY_DP83848C=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/zkit-arm-1769/thttpd/defconfig b/configs/zkit-arm-1769/thttpd/defconfig index d30a0e3270..0438660456 100644 --- a/configs/zkit-arm-1769/thttpd/defconfig +++ b/configs/zkit-arm-1769/thttpd/defconfig @@ -518,7 +518,6 @@ CONFIG_DEV_FIFO_SIZE=1024 # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/zp214xpa/nsh/defconfig b/configs/zp214xpa/nsh/defconfig index dcb8c7e000..547c51e58c 100644 --- a/configs/zp214xpa/nsh/defconfig +++ b/configs/zp214xpa/nsh/defconfig @@ -393,7 +393,6 @@ CONFIG_DEV_NULL=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y # CONFIG_DEV_LOWCONSOLE is not set # CONFIG_SERIAL_REMOVABLE is not set diff --git a/configs/zp214xpa/nxlines/defconfig b/configs/zp214xpa/nxlines/defconfig index 990185b651..06f8adea17 100644 --- a/configs/zp214xpa/nxlines/defconfig +++ b/configs/zp214xpa/nxlines/defconfig @@ -439,7 +439,6 @@ CONFIG_LCD_LANDSCAPE=y # CONFIG_PM is not set # CONFIG_POWER is not set # CONFIG_SENSORS is not set -# CONFIG_SERCOMM_CONSOLE is not set CONFIG_SERIAL=y CONFIG_DEV_LOWCONSOLE=y # CONFIG_SERIAL_REMOVABLE is not set diff --git a/drivers/Kconfig b/drivers/Kconfig index 4ac8a9d0c6..740602b9f2 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -519,23 +519,6 @@ if SENSORS source drivers/sensors/Kconfig endif # SENSORS -menuconfig SERCOMM_CONSOLE - bool "Osmocom-bb Sercomm Driver Support" - default n - ---help--- - Sercomm is the transport used by osmocom-bb that runs on top of serial. - See http://bb.osmocom.org/trac/wiki/nuttx-bb/run for detailed the usage - of nuttx with sercomm. - - drivers/sercomm is only built if SERCOMM_CONSOLE in the NuttX - configuration file. If you attempt to build this driver without - osmocom-bb, you will get compilation errors because of header files - that are needed from the osmocom-bb. - -if SERCOMM_CONSOLE -source drivers/sercomm/Kconfig -endif # SERCOMM_CONSOLE - menuconfig SERIAL bool "Serial Driver Support" default y diff --git a/drivers/Makefile b/drivers/Makefile index daac4cd18c..94f027afbb 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -66,7 +66,6 @@ include net$(DELIM)Make.defs include pipes$(DELIM)Make.defs include power$(DELIM)Make.defs include sensors$(DELIM)Make.defs -include sercomm$(DELIM)Make.defs include serial$(DELIM)Make.defs include spi$(DELIM)Make.defs include syslog$(DELIM)Make.defs diff --git a/drivers/README.txt b/drivers/README.txt index fbb13ce25d..f9f23af06f 100644 --- a/drivers/README.txt +++ b/drivers/README.txt @@ -137,16 +137,6 @@ sensors/ measure and convert voltage levels. DACs, however, are retained in the analog/ sub-directory. -sercomm/ - Sercomm is the transport used by osmocom-bb that runs on top of serial. - See http://bb.osmocom.org/trac/wiki/nuttx-bb/run for detailed the usage - of nuttx with sercomm. - - drivers/sercomm is only built if CONFIG_SERCOMM_CONSOLE in the NuttX - configuration file. If you attempt to build this driver without - osmocom-bb, you will get compilation errors because of header files - that are needed from the osmocom-bb. - serial/ Front-end character drivers for chip-specific UARTs. This provide some TTY-like functionality and are commonly used (but not required for) diff --git a/drivers/sercomm/Kconfig b/drivers/sercomm/Kconfig deleted file mode 100644 index f72f3c094c..0000000000 --- a/drivers/sercomm/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# diff --git a/drivers/sercomm/Make.defs b/drivers/sercomm/Make.defs deleted file mode 100644 index 0cf93d4c80..0000000000 --- a/drivers/sercomm/Make.defs +++ /dev/null @@ -1,55 +0,0 @@ -############################################################################ -# drivers/serial/Make.defs -# -# Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. -# Author: Gregory Nutt -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# 3. Neither the name NuttX nor the names of its contributors may be -# used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS -# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED -# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -############################################################################ - -# File descriptor support is needed for this driver - -ifneq ($(CONFIG_NFILE_DESCRIPTORS),0) - -# The sercomm driver should not be build for all platforms. Only build it -# is so configured - -ifeq ($(CONFIG_SERCOMM_CONSOLE),y) - -# Include serial drivers - -CSRCS += console.c uart.c - -# Include sercomm build support - -DEPPATH += --dep-path sercomm -VPATH += :sercomm - -endif -endif diff --git a/drivers/sercomm/README.txt b/drivers/sercomm/README.txt deleted file mode 100644 index 06add26e88..0000000000 --- a/drivers/sercomm/README.txt +++ /dev/null @@ -1,19 +0,0 @@ -drivers/sercomm README -====================== - -If CONFIG_SERCOMM_CONSOLE is defined in the NuttX configuration file, NuttX -will attempt to use sercomm (HDLC protocol) to communicate with the -host system. Sercomm is the transport used by osmocom-bb that runs on top -of serial. See http://bb.osmocom.org/trac/wiki/nuttx-bb/run for detailed -the usage of nuttx with sercomm. - -The drivers/sercomm build that you have the osmocom-bb project directory -at same level as the nuttx project: - - |- nuttx - |- apps - `- osmocom-bb - -If you attempt to build this driver without osmocom-bb, you will get -compilation errors because of header files that are needed from the -osmocom-bb directory. diff --git a/drivers/sercomm/console.c b/drivers/sercomm/console.c deleted file mode 100644 index efd1174ba3..0000000000 --- a/drivers/sercomm/console.c +++ /dev/null @@ -1,216 +0,0 @@ -/**************************************************************************** - * drivers/sercomm/console.c - * Driver for NuttX Console - * - * (C) 2010 by Harald Welte - * (C) 2011 Stefan Richter - * - * This source code is derivated from Osmocom-BB project and was - * relicensed as BSD with permission from original authors. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#include -#include -#include -#include - -#include -#include -#include - -#include "uart.h" -#include -#include - -/************************************************************************************ - * Fileops Prototypes and Structures - ************************************************************************************/ - -typedef FAR struct file file_t; - -static ssize_t sc_console_read(file_t *filep, FAR char *buffer, size_t buflen); -static ssize_t sc_console_write(file_t *filep, FAR const char *buffer, size_t buflen); -static int sc_console_ioctl(file_t *filep, int cmd, unsigned long arg); -#ifndef CONFIG_DISABLE_POLL -static int sc_console_poll(file_t *filep, FAR struct pollfd *fds, bool setup); -#endif - -static const struct file_operations g_sercom_console_ops = -{ - 0, /* open, always opened */ - 0, /* close, stays open */ - sc_console_read, /* read */ - sc_console_write, /* write */ - 0, /* seek, not supported */ - sc_console_ioctl, /* ioctl */ -#ifndef CONFIG_DISABLE_POLL - sc_console_poll /* poll */ -#endif -}; - -static FAR uart_dev_t *readdev = NULL; -static struct msgb *recvmsg = NULL; - -/**************************************************************************** - * Helper functions - ****************************************************************************/ - -static void recv_cb(uint8_t dlci, struct msgb *msg) -{ - sem_post(&readdev->recvsem); - recvmsg = msg; -} - -/**************************************************************************** - * Fileops - ****************************************************************************/ - -/* REVISIT: recvmsg is overwritten when multiple msg arrive! */ - -static ssize_t sc_console_read(file_t *filep, FAR char *buffer, size_t buflen) -{ - size_t len; - struct msgb *tmp; - - /* Wait until data is received */ - - while (recvmsg == NULL) - { - sem_wait(&readdev->recvsem); - } - - len = recvmsg->len > buflen ? buflen : recvmsg->len; - memcpy(buffer, msgb_get(recvmsg, len), len); - - if (recvmsg->len == 0) - { - /* prevent inconsistent msg by first invalidating it, then free it */ - - tmp = recvmsg; - recvmsg = NULL; - msgb_free(tmp); - } - - return len; -} - -/* REVISIT: redirect to old Osmocom-BB comm/sercomm_cons.c -> 2 buffers */ - -extern int sercomm_puts(const char *s); - -static ssize_t sc_console_write(file_t *filep, FAR const char *buffer, size_t buflen) -{ - char dstbuf[32]; - int cnt; - - if (buflen >= 31) - { - cnt = 31; - } - else - { - cnt = buflen; - } - - memcpy(dstbuf, buffer, cnt); - dstbuf[cnt] = '\0'; - - /* print part of our buffer */ - - sercomm_puts(dstbuf); - - /* wait a little bit to get data transfered */ - - up_mdelay(1); - - return cnt; -} - -/* Forward ioctl to uart driver */ - -static int sc_console_ioctl(struct file *filep, int cmd, unsigned long arg) -{ - FAR struct inode *inode = filep->f_inode; - FAR uart_dev_t *dev = inode->i_private; - - return dev->ops->ioctl(filep, cmd, arg); -} - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/* Use sercomm on uart driver, register console driver */ - -int sercomm_register(FAR const char *path, FAR uart_dev_t *dev) -{ - /* REVISIT: initialize MODEMUART to be used for sercomm */ - - uart_init(SERCOMM_UART_NR, 1); - uart_baudrate(SERCOMM_UART_NR, UART_115200); - readdev = dev; - sercomm_register_rx_cb(SC_DLCI_LOADER, &recv_cb); - - sem_init(&dev->xmit.sem, 0, 1); - sem_init(&dev->recv.sem, 0, 1); - sem_init(&dev->closesem, 0, 1); - sem_init(&dev->xmitsem, 0, 0); - sem_init(&dev->recvsem, 0, 0); -#ifndef CONFIG_DISABLE_POLL - sem_init(&dev->pollsem, 0, 1); -#endif - - sem_setprotocol(&dev->xmitsem, SEM_PRIO_NONE); - sem_setprotocol(&dev->recvsem, SEM_PRIO_NONE); - - _info("Registering %s\n", path); - return register_driver(path, &g_sercom_console_ops, 0666, NULL); -} - -/* Stubs to make serial driver happy */ - -void sercomm_recvchars(void *a) -{ -} - -void sercomm_xmitchars(void *a) -{ -} - -/* Stubs to make memory allocator happy */ - -void cons_puts(void *foo) -{ -} - -void delay_ms(int ms) -{ -} diff --git a/drivers/sercomm/loadwriter.py b/drivers/sercomm/loadwriter.py deleted file mode 100755 index 6234d6f0d3..0000000000 --- a/drivers/sercomm/loadwriter.py +++ /dev/null @@ -1,19 +0,0 @@ -#!/usr/bin/python -from socket import * -import time - -SOCKET_NAME = '/tmp/osmocom_loader' - -s = socket(AF_UNIX, SOCK_STREAM) -s.connect(SOCKET_NAME) - -while 1: - try: - x = raw_input(">") - y = len(x) + 1 - s.send(chr(y>>8) + chr(y&255) + x + "\n") - except: - print '' - break - -s.close() diff --git a/drivers/sercomm/uart.c b/drivers/sercomm/uart.c deleted file mode 100644 index 9e257455a8..0000000000 --- a/drivers/sercomm/uart.c +++ /dev/null @@ -1,607 +0,0 @@ -/**************************************************************************** - * drivers/sercomm/uart.c - * Calypso DBB internal UART Driver - * - * (C) 2010 by Harald Welte - * (C) 2010 by Ingo Albrecht - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include -#include - -#include "uart.h" - -#define BASE_ADDR_UART_MODEM 0xffff5000 -#define OFFSET_IRDA 0x800 - -#define UART_REG(n,m) (BASE_ADDR_UART_MODEM + ((n)*OFFSET_IRDA)+(m)) - -#define LCR7BIT 0x80 -#define LCRBFBIT 0x40 -#define MCR6BIT 0x20 -#define REG_OFFS(m) ((m) & ~(LCR7BIT|LCRBFBIT|MCR6BIT)) - -/* read access LCR[7] = 0 */ - -enum uart_reg -{ - RHR = 0, - IER = 1, - IIR = 2, - LCR = 3, - MCR = 4, - LSR = 5, - MSR = 6, - SPR = 7, - MDR1 = 8, - DMR2 = 9, - SFLSR = 0x0a, - RESUME = 0x0b, - SFREGL = 0x0c, - SFREGH = 0x0d, - BLR = 0x0e, - ACREG = 0x0f, - SCR = 0x10, - SSR = 0x11, - EBLR = 0x12, - - /* read access LCR[7] = 1 */ - - DLL = RHR | LCR7BIT, - DLH = IER | LCR7BIT, - DIV1_6 = ACREG | LCR7BIT, - - /* read/write access LCR[7:0] = 0xbf */ - - EFR = IIR | LCRBFBIT, - XON1 = MCR | LCRBFBIT, - XON2 = LSR | LCRBFBIT, - XOFF1 = MSR | LCRBFBIT, - XOFF2 = SPR | LCRBFBIT, - - /* read/write access if EFR[4] = 1 and MCR[6] = 1 */ - - TCR = MSR | MCR6BIT, - TLR = SPR | MCR6BIT, -}; - -/* write access LCR[7] = 0 */ - -#define THR RHR -#define FCR IIR /* only if EFR[4] = 1 */ -#define TXFLL SFLSR -#define TXFLH RESUME -#define RXFLL SFREGL -#define RXFLH SFREGH - -enum fcr_bits -{ - FIFO_EN = (1 << 0), - RX_FIFO_CLEAR = (1 << 1), - TX_FIFO_CLEAR = (1 << 2), - DMA_MODE = (1 << 3), -}; - -#define TX_FIFO_TRIG_SHIFT 4 -#define RX_FIFO_TRIG_SHIFT 6 - -enum iir_bits -{ - IIR_INT_PENDING = 0x01, - IIR_INT_TYPE = 0x3E, - IIR_INT_TYPE_RX_STATUS_ERROR = 0x06, - IIR_INT_TYPE_RX_TIMEOUT = 0x0C, - IIR_INT_TYPE_RHR = 0x04, - IIR_INT_TYPE_THR = 0x02, - IIR_INT_TYPE_MSR = 0x00, - IIR_INT_TYPE_XOFF = 0x10, - IIR_INT_TYPE_FLOW = 0x20, - IIR_FCR0_MIRROR = 0xC0, -}; - -#define UART_REG_UIR 0xffff6000 - -/* enable or disable the divisor latch for access to DLL, DLH */ - -static void uart_set_lcr7bit(int uart, int on) -{ - uint8_t reg; - - reg = readb(UART_REG(uart, LCR)); - if (on) - { - reg |= (1 << 7); - } - else - { - reg &= ~(1 << 7); - } - - writeb(reg, UART_REG(uart, LCR)); -} - -static uint8_t old_lcr; -static void uart_set_lcr_bf(int uart, int on) -{ - if (on) - { - old_lcr = readb(UART_REG(uart, LCR)); - writeb(0xBF, UART_REG(uart, LCR)); - } - else - { - writeb(old_lcr, UART_REG(uart, LCR)); - } -} - -/* Enable or disable the TCR_TLR latch bit in MCR[6] */ - -static void uart_set_mcr6bit(int uart, int on) -{ - uint8_t mcr; - - /* we assume EFR[4] is always set to 1 */ - - mcr = readb(UART_REG(uart, MCR)); - if (on) - { - mcr |= (1 << 6); - } - else - { - mcr &= ~(1 << 6); - } - - writeb(mcr, UART_REG(uart, MCR)); -} - -static void uart_reg_write(int uart, enum uart_reg reg, uint8_t val) -{ - if (reg & LCRBFBIT) - { - uart_set_lcr_bf(uart, 1); - } - else if (reg & LCR7BIT) - { - uart_set_lcr7bit(uart, 1); - } - else if (reg & MCR6BIT) - { - uart_set_mcr6bit(uart, 1); - } - - writeb(val, UART_REG(uart, REG_OFFS(reg))); - - if (reg & LCRBFBIT) - { - uart_set_lcr_bf(uart, 0); - } - else if (reg & LCR7BIT) - { - uart_set_lcr7bit(uart, 0); - } - else if (reg & MCR6BIT) - { - uart_set_mcr6bit(uart, 0); - } -} - -/* read from a UART register, applying any required latch bits */ - -static uint8_t uart_reg_read(int uart, enum uart_reg reg) -{ - uint8_t ret; - - if (reg & LCRBFBIT) - { - uart_set_lcr_bf(uart, 1); - } - else if (reg & LCR7BIT) - { - uart_set_lcr7bit(uart, 1); - } - else if (reg & MCR6BIT) - { - uart_set_mcr6bit(uart, 1); - } - - ret = readb(UART_REG(uart, REG_OFFS(reg))); - - if (reg & LCRBFBIT) - { - uart_set_lcr_bf(uart, 0); - } - else if (reg & LCR7BIT) - { - uart_set_lcr7bit(uart, 0); - } - else if (reg & MCR6BIT) - { - uart_set_mcr6bit(uart, 0); - } - - return ret; -} - -#if 0 -static void uart_irq_handler_cons(__unused enum irq_nr irqnr) -{ - const uint8_t uart = CONS_UART_NR; - uint8_t iir; - - iir = uart_reg_read(uart, IIR); - if (iir & IIR_INT_PENDING) - { - return; - } - - switch (iir & IIR_INT_TYPE) - { - case IIR_INT_TYPE_RHR: - break; - - case IIR_INT_TYPE_THR: - if (cons_rb_flush() == 1) - { - /* everything was flushed, disable THR IRQ */ - - uint8_t ier = uart_reg_read(uart, IER); - ier &= ~(1 << 1); - uart_reg_write(uart, IER, ier); - } - break; - - case IIR_INT_TYPE_MSR: - break; - - case IIR_INT_TYPE_RX_STATUS_ERROR: - break; - - case IIR_INT_TYPE_RX_TIMEOUT: - break; - - case IIR_INT_TYPE_XOFF: - break; - } -} -#endif - -static void uart_irq_handler_sercomm(__unused enum irq_nr irqnr, __unused void *context) -{ - const uint8_t uart = SERCOMM_UART_NR; - uint8_t iir, ch; - - iir = uart_reg_read(uart, IIR); - if (iir & IIR_INT_PENDING) - { - return; - } - - switch (iir & IIR_INT_TYPE) - { - case IIR_INT_TYPE_RX_TIMEOUT: - case IIR_INT_TYPE_RHR: - /* as long as we have rx data available */ - - while (uart_getchar_nb(uart, &ch)) - { - if (sercomm_drv_rx_char(ch) < 0) - { - /* sercomm cannot receive more data right now */ - - uart_irq_enable(uart, UART_IRQ_RX_CHAR, 0); - } - } - break; - - case IIR_INT_TYPE_THR: - /* as long as we have space in the FIFO */ - - while (!uart_tx_busy(uart)) - { - /* get a byte from sercomm */ - - if (!sercomm_drv_pull(&ch)) - { - /* no more bytes in sercomm, stop TX interrupts */ - - uart_irq_enable(uart, UART_IRQ_TX_EMPTY, 0); - break; - } - - /* write the byte into the TX FIFO */ - - uart_putchar_nb(uart, ch); - } - break; - - case IIR_INT_TYPE_MSR: - printf("UART IRQ MSR\n"); - break; - - case IIR_INT_TYPE_RX_STATUS_ERROR: - printf("UART IRQ RX_SE\n"); - break; - - case IIR_INT_TYPE_XOFF: - printf("UART IRQXOFF\n"); - break; - } -} - -static const uint8_t uart2irq[] = -{ - [0] = IRQ_UART_IRDA, - [1] = IRQ_UART_MODEM, -}; - -void uart_init(uint8_t uart, uint8_t interrupts) -{ -#if 0 - uint8_t irq = uart2irq[uart]; -#endif - - uart_reg_write(uart, IER, 0x00); - - if (uart == SERCOMM_UART_NR) - { - sercomm_init(); - irq_attach(IRQ_UART_MODEM, (xcpt_t)uart_irq_handler_sercomm); - up_enable_irq(IRQ_UART_MODEM); - uart_irq_enable(uart, UART_IRQ_RX_CHAR, 1); - } - -#if 0 - if (uart == CONS_UART_NR) - { - cons_init(); - if (interrupts) - { - irq_register_handler(irq, &uart_irq_handler_cons); - irq_config(irq, 0, 0, 0xff); - irq_enable(irq); - } - } - else - { - sercomm_init(); - if (interrupts) - { - irq_register_handler(irq, &uart_irq_handler_sercomm); - irq_config(irq, 0, 0, 0xff); - irq_enable(irq); - } - - uart_irq_enable(uart, UART_IRQ_RX_CHAR, 1); - } -#endif -#if 0 - if (uart == 1) - { - /* assign UART to MCU and unmask interrupts */ - - writeb(UART_REG_UIR, 0x00); - } -#endif - - /* if we don't initialize these, we get strange corruptions in the - * received data... :-( - */ - - uart_reg_write(uart, MDR1, 0x07); /* turn off UART */ - uart_reg_write(uart, XON1, 0x00); /* Xon1/Addr Register */ - uart_reg_write(uart, XON2, 0x00); /* Xon2/Addr Register */ - uart_reg_write(uart, XOFF1, 0x00); /* Xoff1 Register */ - uart_reg_write(uart, XOFF2, 0x00); /* Xoff2 Register */ - uart_reg_write(uart, EFR, 0x00); /* Enhanced Features Register */ - - /* select UART mode */ - - uart_reg_write(uart, MDR1, 0); - - /* no XON/XOFF flow control, ENHANCED_EN, no auto-RTS/CTS */ - - uart_reg_write(uart, EFR, (1 << 4)); - - /* enable Tx/Rx FIFO, Tx trigger at 56 spaces, Rx trigger at 60 chars */ - - uart_reg_write(uart, FCR, FIFO_EN | RX_FIFO_CLEAR | TX_FIFO_CLEAR | - (3 << TX_FIFO_TRIG_SHIFT) | (3 << RX_FIFO_TRIG_SHIFT)); - - /* THR interrupt only when TX FIFO and TX shift register are empty */ - - uart_reg_write(uart, SCR, (1 << 0)); /* | (1 << 3)); */ - - /* 8 bit, 1 stop bit, no parity, no break */ - - uart_reg_write(uart, LCR, 0x03); - - uart_set_lcr7bit(uart, 0); -} - -void uart_poll(uint8_t uart) -{ -#if 0 - if (uart == CONS_UART_NR) - { - uart_irq_handler_cons(0); - } - else -#endif - { - uart_irq_handler_sercomm(0, NULL); - } -} - -void uart_irq_enable(uint8_t uart, enum uart_irq irq, int on) -{ - uint8_t ier = uart_reg_read(uart, IER); - uint8_t mask = 0; - - switch (irq) - { - case UART_IRQ_TX_EMPTY: - mask = (1 << 1); - break; - - case UART_IRQ_RX_CHAR: - mask = (1 << 0); - break; - } - - if (on) - { - ier |= mask; - } - else - { - ier &= ~mask; - } - - uart_reg_write(uart, IER, ier); -} - -void uart_putchar_wait(uint8_t uart, int c) -{ - /* wait while TX FIFO indicates full */ - - while (readb(UART_REG(uart, SSR)) & 0x01) { } - - /* put character in TX FIFO */ - - writeb(c, UART_REG(uart, THR)); -} - -int uart_putchar_nb(uint8_t uart, int c) -{ - /* if TX FIFO indicates full, abort */ - - if (readb(UART_REG(uart, SSR)) & 0x01) - { - return 0; - } - - writeb(c, UART_REG(uart, THR)); - return 1; -} - -int uart_getchar_nb(uint8_t uart, uint8_t *ch) -{ - uint8_t lsr; - - lsr = readb(UART_REG(uart, LSR)); - - /* something strange happened */ - - if (lsr & 0x02) - { - printf("LSR RX_OE\n"); - } - - if (lsr & 0x04) - { - printf("LSR RX_PE\n"); - } - - if (lsr & 0x08) - { - printf("LSR RX_FE\n"); - } - - if (lsr & 0x10) - { - printf("LSR RX_BI\n"); - } - - if (lsr & 0x80) - { - printf("LSR RX_FIFO_STS\n"); - } - - /* is the Rx FIFO empty? */ - - if (!(lsr & 0x01)) - { - return 0; - } - - *ch = readb(UART_REG(uart, RHR)); - return 1; -} - -int uart_tx_busy(uint8_t uart) -{ - if (readb(UART_REG(uart, SSR)) & 0x01) - { - return 1; - } - - return 0; -} - -static const uint16_t divider[] = -{ - [UART_38400] = 21, /* 38,690 */ - [UART_57600] = 14, /* 58,035 */ - [UART_115200] = 7, /* 116,071 */ - [UART_230400] = 4, /* 203,125! (-3% would be 223,488) */ - [UART_460800] = 2, /* 406,250! (-3% would be 446,976) */ - [UART_921600] = 1, /* 812,500! (-3% would be 893,952) */ -}; - -int uart_baudrate(uint8_t uart, enum uart_baudrate bdrt) -{ - uint16_t div; - - if (bdrt > ARRAY_SIZE(divider)) - { - return -1; - } - - div = divider[bdrt]; - uart_set_lcr7bit(uart, 1); - writeb(div & 0xff, UART_REG(uart, DLL)); - writeb(div >> 8, UART_REG(uart, DLH)); - uart_set_lcr7bit(uart, 0); - - return 0; -} diff --git a/drivers/sercomm/uart.h b/drivers/sercomm/uart.h deleted file mode 100644 index 81d7a15609..0000000000 --- a/drivers/sercomm/uart.h +++ /dev/null @@ -1,32 +0,0 @@ -#ifndef _UART_H -#define _UART_H - -#include - -enum uart_baudrate { - UART_38400, - UART_57600, - UART_115200, - UART_230400, - UART_460800, - UART_614400, - UART_921600, -}; - -void uart_init(uint8_t uart, uint8_t interrupts); -void uart_putchar_wait(uint8_t uart, int c); -int uart_putchar_nb(uint8_t uart, int c); -int uart_getchar_nb(uint8_t uart, uint8_t *ch); -int uart_tx_busy(uint8_t uart); -int uart_baudrate(uint8_t uart, enum uart_baudrate bdrt); - -enum uart_irq { - UART_IRQ_TX_EMPTY, - UART_IRQ_RX_CHAR, -}; - -void uart_irq_enable(uint8_t uart, enum uart_irq irq, int on); - -void uart_poll(uint8_t uart); - -#endif /* _UART_H */ diff --git a/include/nuttx/sercomm/msgb.h b/include/nuttx/sercomm/msgb.h deleted file mode 100644 index 39067c3ba3..0000000000 --- a/include/nuttx/sercomm/msgb.h +++ /dev/null @@ -1,218 +0,0 @@ -/**************************************************************************** - * (C) 2008-2010 by Harald Welte - * - * This source code is derivated from Osmocom-BB project and was - * relicensed as BSD with permission from original authors. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __INCLUDE_NUTTX_SERCOM_MSGB_H -#define __INCLUDE_NUTTX_SERCOM_MSGB_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -struct msgb -{ - struct llist_head list; - - /* the layer 1 header, if any */ - - unsigned char *l1h; - - /* the A-bis layer 2 header: OML, RSL(RLL), NS */ - - unsigned char *l2h; - - /* the layer 3 header. For OML: FOM; RSL: 04.08; GPRS: BSSGP */ - - unsigned char *l3h; - - uint16_t data_len; - uint16_t len; - - unsigned char *head; /* start of buffer */ - unsigned char *tail; /* end of message */ - unsigned char *data; /* start of message */ - unsigned char _data[0]; -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -struct msgb *msgb_alloc(uint16_t size, const char *name); -void msgb_free(struct msgb *m); -void msgb_enqueue(struct llist_head *queue, struct msgb *msg); -struct msgb *msgb_dequeue(struct llist_head *queue); -void msgb_reset(struct msgb *m); - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -#define msgb_l1(m) ((void *)(m->l1h)) -#define msgb_l2(m) ((void *)(m->l2h)) -#define msgb_l3(m) ((void *)(m->l3h)) - -static inline unsigned int msgb_l1len(const struct msgb *msgb) -{ - return msgb->tail - (uint8_t *)msgb_l1(msgb); -} - -static inline unsigned int msgb_l2len(const struct msgb *msgb) -{ - return msgb->tail - (uint8_t *)msgb_l2(msgb); -} - -static inline unsigned int msgb_l3len(const struct msgb *msgb) -{ - return msgb->tail - (uint8_t *)msgb_l3(msgb); -} - -static inline unsigned int msgb_headlen(const struct msgb *msgb) -{ - return msgb->len - msgb->data_len; -} - -static inline int msgb_tailroom(const struct msgb *msgb) -{ - return (msgb->head + msgb->data_len) - msgb->tail; -} - -static inline unsigned char *msgb_put(struct msgb *msgb, unsigned int len) -{ - unsigned char *tmp = msgb->tail; - - /* we intentionally call cons_puts() here to display an allocation - * failure on the _other_ serial port (i.e. the one that doesn't - * have the HDLC layer on it - */ - - if (msgb_tailroom(msgb) < len) - { - cons_puts("msgb_tailroom insufficient!\n"); - } - - msgb->tail += len; - msgb->len += len; - return tmp; -} - -static inline void msgb_put_u8(struct msgb *msgb, uint8_t word) -{ - uint8_t *space = msgb_put(msgb, 1); - space[0] = word & 0xFF; -} - -static inline void msgb_put_u16(struct msgb *msgb, uint16_t word) -{ - uint8_t *space = msgb_put(msgb, 2); - space[0] = word >> 8 & 0xFF; - space[1] = word & 0xFF; -} - -static inline void msgb_put_u32(struct msgb *msgb, uint32_t word) -{ - uint8_t *space = msgb_put(msgb, 4); - space[0] = word >> 24 & 0xFF; - space[1] = word >> 16 & 0xFF; - space[2] = word >> 8 & 0xFF; - space[3] = word & 0xFF; -} - -static inline unsigned char *msgb_get(struct msgb *msgb, unsigned int len) -{ - unsigned char *tmp = msgb->data; - msgb->data += len; - msgb->len -= len; - return tmp; -} - -static inline uint8_t msgb_get_u8(struct msgb *msgb) -{ - uint8_t *space = msgb_get(msgb, 1); - return space[0]; -} - -static inline uint16_t msgb_get_u16(struct msgb *msgb) -{ - uint8_t *space = msgb_get(msgb, 2); - return space[0] << 8 | space[1]; -} - -static inline uint32_t msgb_get_u32(struct msgb *msgb) -{ - uint8_t *space = msgb_get(msgb, 4); - return space[0] << 24 | space[1] << 16 | space[2] << 8 | space[3]; -} - -static inline unsigned char *msgb_push(struct msgb *msgb, unsigned int len) -{ - msgb->data -= len; - msgb->len += len; - return msgb->data; -} - -static inline unsigned char *msgb_pull(struct msgb *msgb, unsigned int len) -{ - msgb->len -= len; - return msgb->data += len; -} - -/* increase the headroom of an empty msgb, reducing the tailroom */ - -static inline void msgb_reserve(struct msgb *msg, int len) -{ - msg->data += len; - msg->tail += len; -} - -static inline struct msgb *msgb_alloc_headroom(int size, int headroom, - const char *name) -{ - struct msgb *msg = msgb_alloc(size, name); - if (msg) - { - msgb_reserve(msg, headroom); - } - - return msg; -} - -#endif /* __INCLUDE_NUTTX_SERCOM_MSGB_H */ diff --git a/include/nuttx/sercomm/sercomm.h b/include/nuttx/sercomm/sercomm.h deleted file mode 100644 index 260f1be57b..0000000000 --- a/include/nuttx/sercomm/sercomm.h +++ /dev/null @@ -1,57 +0,0 @@ -#ifndef __INCLUDE_NUTTX_SERCOMM_SERCOMM_H -#define __INCLUDE_NUTTX_SERCOMM_SERCOMM_H - -/* SERCOMM layer on UART1 (modem UART) */ - -#include - -#define SERCOMM_UART_NR 1 - -#define HDLC_FLAG 0x7E -#define HDLC_ESCAPE 0x7D - -#define HDLC_C_UI 0x03 -#define HDLC_C_P_BIT (1 << 4) -#define HDLC_C_F_BIT (1 << 4) - -/* a low sercomm_dlci means high priority. A high DLCI means low priority */ -enum sercomm_dlci { - SC_DLCI_HIGHEST = 0, - SC_DLCI_DEBUG = 4, - SC_DLCI_L1A_L23 = 5, - SC_DLCI_LOADER = 9, - SC_DLCI_CONSOLE = 10, - SC_DLCI_ECHO = 128, - _SC_DLCI_MAX -}; - -void sercomm_init(void); -int sercomm_initialized(void); - -/* User Interface: Tx */ - -/* user interface for transmitting messages for a given DLCI */ -void sercomm_sendmsg(uint8_t dlci, struct msgb *msg); -/* how deep is the Tx queue for a given DLCI */ -unsigned int sercomm_tx_queue_depth(uint8_t dlci); - -/* User Interface: Rx */ - -/* receiving messages for a given DLCI */ -typedef void (*dlci_cb_t)(uint8_t dlci, struct msgb *msg); -int sercomm_register_rx_cb(uint8_t dlci, dlci_cb_t cb); - -/* Driver Interface */ - -/* fetch one octet of to-be-transmitted serial data. returns 0 if no more data */ -int sercomm_drv_pull(uint8_t *ch); -/* the driver has received one byte, pass it into sercomm layer. - returns 1 in case of success, 0 in case of unrecognized char */ -int sercomm_drv_rx_char(uint8_t ch); - -static inline struct msgb *sercomm_alloc_msgb(unsigned int len) -{ - return msgb_alloc_headroom(len+4, 4, "sercomm_tx"); -} - -#endif /* __INCLUDE_NUTTX_SERCOMM_SERCOMM_H */ diff --git a/include/nuttx/sercomm/sercomm_cons.h b/include/nuttx/sercomm/sercomm_cons.h deleted file mode 100644 index eb8e7fa12b..0000000000 --- a/include/nuttx/sercomm/sercomm_cons.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef __INCLUDE_NUTTX_SERCOMM_SERCOMM_CONS_H -#define __INCLUDE_NUTTX_SERCOMM_SERCOMM_CONS_H - -/* how large buffers do we allocate? */ -#define SERCOMM_CONS_ALLOC 256 - -int sercomm_puts(const char *s); -int sercomm_putchar(int c); - -#endif /* __INCLUDE_NUTTX_SERCOMM_SERCOMM_CONS_H */ -- GitLab From dd5e47a4184ff6f586eff0dd3a495359302fb79d Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Wed, 14 Dec 2016 08:15:03 -0600 Subject: [PATCH 688/734] ESP32 core v2: Two changes (1) flushes the UART TX buffer in the esp32 serial shutdown routine. The ROM bootloader does not flush the FIFO before handing over to user code, so some of this output is not currently seen when the UART is reconfigured in early stages of startup. And changes the openocd config file's default flash voltage from 1.8V to 3.3V. This is not necessary right now, but may save some hard-to-debug moments down the track (3.3V-only flash running at 1.8V often half-works and does weird things...) --- arch/xtensa/src/esp32/esp32_serial.c | 13 +++++++++++++ configs/esp32-core/scripts/esp32.cfg | 6 ++---- configs/esp32-core/scripts/esp32_iram.ld | 4 ---- 3 files changed, 15 insertions(+), 8 deletions(-) diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c index f48b06e304..34846e89e8 100644 --- a/arch/xtensa/src/esp32/esp32_serial.c +++ b/arch/xtensa/src/esp32/esp32_serial.c @@ -586,6 +586,19 @@ static int esp32_setup(struct uart_dev_s *dev) static void esp32_shutdown(struct uart_dev_s *dev) { struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; + uint32_t status; + + /* Wait for outgoing FIFO to clear. The ROM bootloader does not flush + * the FIFO before handing over to user code, so some of this output is + * not currently seen when the UART is reconfigured in early stages of + * startup. + */ + + do + { + status = esp32_serialin(priv, UART_STATUS_OFFSET); + } + while ((status & UART_TXFIFO_CNT_M) != 0); /* Disable all UART interrupts */ diff --git a/configs/esp32-core/scripts/esp32.cfg b/configs/esp32-core/scripts/esp32.cfg index 0bd581f40a..a9f94d37dc 100644 --- a/configs/esp32-core/scripts/esp32.cfg +++ b/configs/esp32-core/scripts/esp32.cfg @@ -44,8 +44,6 @@ source [find target/esp32.cfg] # voltage greatly. # Enable this for 1.8V SPI flash -esp108 flashbootstrap 1.8 +# esp108 flashbootstrap 1.8 # Enable this for 3.3V SPI flash -#esp108 flashbootstrap 3.3 - - +esp108 flashbootstrap 3.3 diff --git a/configs/esp32-core/scripts/esp32_iram.ld b/configs/esp32-core/scripts/esp32_iram.ld index 605ea54e5a..62ed31380b 100644 --- a/configs/esp32-core/scripts/esp32_iram.ld +++ b/configs/esp32-core/scripts/esp32_iram.ld @@ -173,10 +173,6 @@ SECTIONS _sheap = ABSOLUTE(.); } >dram0_0_seg - .flash.rodata : - { - } >drom0_0_seg - .rtc.text : { . = ALIGN(4); -- GitLab From a560d70e7a778c1dbbdff4710cc3cc84292e2afa Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 14 Dec 2016 08:19:35 -0600 Subject: [PATCH 689/734] Add some comments from Angus Gratton to a Kconfig file for future reference. --- configs/esp32-core/Kconfig | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/configs/esp32-core/Kconfig b/configs/esp32-core/Kconfig index 3f73b4052a..79656051e9 100644 --- a/configs/esp32-core/Kconfig +++ b/configs/esp32-core/Kconfig @@ -23,8 +23,19 @@ config ESP32CORE_RUN_IRAM ---help--- The default configuration is set up run from IRAM. However, the current (2016-11-14) OpenOCD for ESP32 does not support writing to - FLASH. This option sets up the liner scripts to support execution + FLASH. This option sets up the linker scripts to support execution from IRAM. In this case, OpenOCD can be used to load directly into IRAM. + At this stage the nuttx image is small enough to be entirely memory- + resident. Once board support is more mature you can add flash cache + mapping code to run from SPI flash after initial boot. There are at + least two possible approaches you could take: You can add the flash + cache mapping code into nuttx directly, so it is self-contained - + early nuttx initialisation runs from IRAM and enables flash cache, + and then off you go. Or you can use the esp-idf software bootloader + and partition table scheme and have nuttx be an esp-idf "app" which + allows interoperability with the esp-idf system but makes you + reliant on the esp-idf design for these parts. Both are possible. + endif # ARCH_BOARD_ESP32CORE -- GitLab From 730ca4ce411f521e6896dbaef18d18a6ff80bc70 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 14 Dec 2016 09:06:09 -0600 Subject: [PATCH 690/734] Fix missing semicolons in DEBUGASSERT statements --- arch/xtensa/src/esp32/esp32_cpuint.c | 4 ++-- arch/xtensa/src/esp32/esp32_timerisr.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/xtensa/src/esp32/esp32_cpuint.c b/arch/xtensa/src/esp32/esp32_cpuint.c index 7d62e6bd77..571c7fd074 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.c +++ b/arch/xtensa/src/esp32/esp32_cpuint.c @@ -327,7 +327,7 @@ int esp32_alloc_levelint(int priority) uint32_t intmask; DEBUGASSERT(priority >= ESP32_MIN_PRIORITY && - priority <= ESP32_MAX_PRIORITY) + priority <= ESP32_MAX_PRIORITY); /* Check if there are any level CPU interrupts available at the requested * interrupt priority. @@ -359,7 +359,7 @@ int esp32_alloc_edgeint(int priority) uint32_t intmask; DEBUGASSERT(priority >= ESP32_MIN_PRIORITY && - priority <= ESP32_MAX_PRIORITY) + priority <= ESP32_MAX_PRIORITY); /* Check if there are any edge CPU interrupts available at the requested * interrupt priority. diff --git a/arch/xtensa/src/esp32/esp32_timerisr.c b/arch/xtensa/src/esp32/esp32_timerisr.c index 90ba8ecaae..14f8a1cdfe 100644 --- a/arch/xtensa/src/esp32/esp32_timerisr.c +++ b/arch/xtensa/src/esp32/esp32_timerisr.c @@ -183,7 +183,7 @@ void xtensa_timer_initialize(void) */ divisor = (1000000ull * (uint64_t)BOARD_CLOCK_FREQUENCY) / CONFIG_USEC_PER_TICK; - DEBUGASSERT(divisor <= UINT32_MAX) + DEBUGASSERT(divisor <= UINT32_MAX); g_tick_divisor = divisor; /* Set up periodic timer */ -- GitLab From 4052ec2d9000c1db4efe9ca87eca40b25492b1af Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 14 Dec 2016 12:14:51 -0600 Subject: [PATCH 691/734] Add missing ENTRY() and RET() macros in C callable assembly language. At one time I though the that the ESP32 support the CALL0 ABI. I was mistaken so there may be a few more like this. --- arch/xtensa/src/common/xtensa_cpuint.S | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_cpuint.S b/arch/xtensa/src/common/xtensa_cpuint.S index 6ea46d71d4..9c7e28260b 100644 --- a/arch/xtensa/src/common/xtensa_cpuint.S +++ b/arch/xtensa/src/common/xtensa_cpuint.S @@ -40,6 +40,8 @@ #include #include +#include "xtensa_abi.h" + #if XCHAL_HAVE_INTERRUPTS /**************************************************************************** @@ -69,6 +71,7 @@ .align 4 xtensa_enable_cpuint: + ENTRY(16) movi a4, 0 xsr a4, INTENABLE /* Disables all interrupts */ @@ -80,7 +83,7 @@ xtensa_enable_cpuint: wsr a5, INTENABLE /* Set CPU INTENABLE to shadow */ mov a3, a4 /* Return previous shadow content */ - ret + RET(16) .size xtensa_enable_cpuint, . - xtensa_enable_cpuint @@ -107,6 +110,7 @@ xtensa_enable_cpuint: .align 4 xtensa_disable_cpuint: + ENTRY(16) movi a4, 0 xsr a4, INTENABLE /* Disables all interrupts */ @@ -119,7 +123,7 @@ xtensa_disable_cpuint: wsr a5, INTENABLE /* Set CPU INTENABLE to shadow */ mov a3, a4 /* Return previous shadow content */ - ret + RET(16) .size xtensa_disable_cpuint, . - xtensa_disable_cpuint -- GitLab From b504b8daff64c37f795e1834c128e81f035d346a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 14 Dec 2016 12:34:11 -0600 Subject: [PATCH 692/734] Update README --- configs/esp32-core/README.txt | 56 ++++++++++++++++++++++++++++++++++- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index 0688c2aad7..8b10ffc6f0 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -172,6 +172,9 @@ Serial Console UART0 is, by default, the serial console. It connects to the on-board CP2102 converter and is available on the USB connector USB CON8 (J1). + It will show up as /dev/ttypUSB[n] where [n] will probably be 0 (is it 1 + on my PC because I have a another device at ttyUSB0). + Buttons and LEDs ================ @@ -223,7 +226,8 @@ SMP 3. Assertions. On a fatal assertions, other CPUs need to be stopped. -OpenOCD for the ESP32 + + for the ESP32 ===================== First you in need some debug environment which would be a JTAG emulator @@ -506,6 +510,56 @@ OpenOCD for the ESP32 would I be able to run directly out of IRAM without a bootloader? That might be a simpler bring-up. + Sample Debug Steps + ------------------ + I did the initial bring-up using the IRAM configuration and OpenOCD. Here + is a synopsis of my debug steps: + + configs/esp32-core/nsh with + + CONFIG_DEBUG_ASSERTIONS=y + CONFIG_DEBUG_FEATURES=y + CONFIG_DEBUG_SYMBOLS=y + CONFIG_ESP32CORE_RUN_IRAM=y + + I also made this change which will eliminate all attempts to re-configure serial. It will just use the serial settings as they were left by the bootloader: + + diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h + index 422ec0b..8707d7c 100644 + --- a/arch/xtensa/src/common/xtensa.h + +++ b/arch/xtensa/src/common/xtensa.h + @@ -60,7 +60,7 @@ + #undef CONFIG_SUPPRESS_INTERRUPTS /* DEFINED: Do not enable interrupts */ + #undef CONFIG_SUPPRESS_TIMER_INTS /* DEFINED: No timer */ + #undef CONFIG_SUPPRESS_SERIAL_INTS /* DEFINED: Console will poll */ + -#undef CONFIG_SUPPRESS_UART_CONFIG /* DEFINED: Do not reconfigure UART */ + +#define CONFIG_SUPPRESS_UART_CONFIG 1 /* DEFINED: Do not reconfigure UART */ + #define CONFIG_SUPPRESS_CLOCK_CONFIG 1 /* DEFINED: Do not reconfigure clocking */ + #undef CONFIG_DUMP_ON_EXIT /* DEFINED: Dump task state on exit */ + + Start OpenOCD: + + cd ../openocde-esp32 + cp ../nuttx/configs/esp32-core/scripts/esp32.cfg . + sudo ./src/openocd -s ./tcl/ -f tcl/interface/ftdi/olimex-arm-usb-ocd.cfg -f ./esp32.cfg + + Start GDB and load code: + + cd ../nuttx + xtensa-esp32-elf-gdb -ex 'target remote localhost:3333' nuttx + (gdb) load nuttx + (gdb) mon reg pc [value report by load for entry point] + (gdb) s + + Single stepping works fine for me as do breakpoints. I get quite a way through initialization, into os_start() and into up_initialize(), and through up_irqinitialize() but it fails in xtensa_timer_initialize() immediatly upon enabling interrupts: + + Breakpoint 1, xtensa_timer_initialize () at chip/esp32_timerisr.c:172 + 72 { + (gdb) n + esp32.cpu0: Target halted, pc=0x400835BF + 187 g_tick_divisor = divisor; + (gdb) ... + Configurations ============== -- GitLab From b5e979d58fda80c48e17cd4276432e4885744804 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 14 Dec 2016 13:30:07 -0600 Subject: [PATCH 693/734] ESP32: Fix a couple of bugs associated with handling of CPU interrupts. --- arch/xtensa/include/esp32/irq.h | 8 ++++---- arch/xtensa/src/esp32/esp32_cpuint.c | 12 ++++++++---- arch/xtensa/src/esp32/esp32_serial.c | 6 ++++-- 3 files changed, 16 insertions(+), 10 deletions(-) diff --git a/arch/xtensa/include/esp32/irq.h b/arch/xtensa/include/esp32/irq.h index 4c8e6c47ca..a3cbab72c1 100644 --- a/arch/xtensa/include/esp32/irq.h +++ b/arch/xtensa/include/esp32/irq.h @@ -378,7 +378,7 @@ #define ESP32_CPUINT_NEDGEPERIPHS 4 #define EPS32_CPUINT_EDGESET 0x50400400 -#define ESP32_CPUINT_NNMIPERIPHS 4 +#define ESP32_CPUINT_NNMIPERIPHS 1 #define EPS32_CPUINT_NMISET 0x00004000 #define ESP32_CPUINT_TIMER0 6 @@ -388,11 +388,11 @@ #define ESP32_CPUINT_TIMER2 16 #define ESP32_CPUINT_SOFTWARE1 29 -#define ESP32_CPUINT_NINTERNAL 5 +#define ESP32_CPUINT_NINTERNAL 6 #define ESP32_CPUINT_MAX 31 -#define EPS32_CPUINT_PERIPHSET 0xdffe6f3f -#define EPS32_CPUINT_INTERNALSET 0x200180c0 +#define EPS32_CPUINT_PERIPHSET 0xdffe773f +#define EPS32_CPUINT_INTERNALSET 0x200188c0 /* Priority 1: 0-10, 12-13, 17-18 (15) * Priority 2: 19-21 (3) diff --git a/arch/xtensa/src/esp32/esp32_cpuint.c b/arch/xtensa/src/esp32/esp32_cpuint.c index 571c7fd074..2324e7fe3c 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.c +++ b/arch/xtensa/src/esp32/esp32_cpuint.c @@ -165,9 +165,11 @@ static uint32_t g_intenable[1]; #endif -/* Bitsets for free, unallocated CPU interrupts */ +/* Bitsets for free, unallocated CPU interrupts available to peripheral + * devices. + */ -static uint32_t g_free_cpuints = 0xffffffff; +static uint32_t g_free_cpuints = EPS32_CPUINT_PERIPHSET; /* Bitsets for each interrupt priority 1-5 */ @@ -188,7 +190,9 @@ static const uint32_t g_priority[5] = * Name: esp32_alloc_cpuint * * Description: - * Allocate a CPU interrupt + * Allocate a CPU interrupt for a peripheral device. This function will + * not allocate any of the pre-allocated CPU interrupts for internal + * devices. * * Input Parameters: * intmask - mask of candidate CPU interrupts. The CPU interrupt will be @@ -224,7 +228,7 @@ int esp32_alloc_cpuint(uint32_t intmask) */ for (cpuint = 0, bitmask = 0xff; - cpuint <= ESP32_CPUINT_MAX; + cpuint <= ESP32_CPUINT_MAX && (intset & bitmask) == 0; cpuint += 8, bitmask <<= 8); /* Search for an unallocated CPU interrupt number in the remaining diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c index 34846e89e8..36c66dcc09 100644 --- a/arch/xtensa/src/esp32/esp32_serial.c +++ b/arch/xtensa/src/esp32/esp32_serial.c @@ -455,8 +455,8 @@ static void esp32_disableallints(struct esp32_dev_s *priv, uint32_t *intena) static int esp32_setup(struct uart_dev_s *dev) { - struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; #ifndef CONFIG_SUPPRESS_UART_CONFIG + struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; uint32_t clkdiv; uint32_t regval; uint32_t conf0; @@ -655,7 +655,9 @@ static int esp32_attach(struct uart_dev_s *dev) priv->cpuint = esp32_alloc_levelint(1); if (priv->cpuint < 0) { - ret = priv->cpuint; + /* Failed to allocate a CPU interrupt of this type */ + + return priv->cpuint; } /* Set up to receive peripheral interrupts on the current CPU */ -- GitLab From 3c4a8d05b0f8c9e19e7bcfbaa0d6ef8eba18de68 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Wed, 14 Dec 2016 14:17:52 -0600 Subject: [PATCH 694/734] MMC/SD SDIO driver: Change the endianess order to read the return of long response command --- drivers/mmcsd/mmcsd_sdio.c | 118 ++++++++++++++++++------------------- 1 file changed, 59 insertions(+), 59 deletions(-) diff --git a/drivers/mmcsd/mmcsd_sdio.c b/drivers/mmcsd/mmcsd_sdio.c index dbdf4e98ca..13f86102e4 100644 --- a/drivers/mmcsd/mmcsd_sdio.c +++ b/drivers/mmcsd/mmcsd_sdio.c @@ -580,13 +580,13 @@ static void mmcsd_decodeCSD(FAR struct mmcsd_state_s *priv, uint32_t csd[4]) #ifdef CONFIG_DEBUG_FS_INFO memset(&decoded, 0, sizeof(struct mmcsd_csd_s)); - decoded.csdstructure = csd[0] >> 30; - decoded.mmcspecvers = (csd[0] >> 26) & 0x0f; - decoded.taac.timevalue = (csd[0] >> 19) & 0x0f; - decoded.taac.timeunit = (csd[0] >> 16) & 7; - decoded.nsac = (csd[0] >> 8) & 0xff; - decoded.transpeed.timevalue = (csd[0] >> 3) & 0x0f; - decoded.transpeed.transferrateunit = csd[0] & 7; + decoded.csdstructure = csd[3] >> 30; + decoded.mmcspecvers = (csd[3] >> 26) & 0x0f; + decoded.taac.timevalue = (csd[3] >> 19) & 0x0f; + decoded.taac.timeunit = (csd[3] >> 16) & 7; + decoded.nsac = (csd[3] >> 8) & 0xff; + decoded.transpeed.timevalue = (csd[3] >> 3) & 0x0f; + decoded.transpeed.transferrateunit = csd[3] & 7; #endif /* Word 2: Bits 64:95 @@ -603,15 +603,15 @@ static void mmcsd_decodeCSD(FAR struct mmcsd_state_s *priv, uint32_t csd[4]) * C_SIZE 48:69 Device size */ - priv->dsrimp = (csd[1] >> 12) & 1; - readbllen = (csd[1] >> 16) & 0x0f; + priv->dsrimp = (csd[2] >> 12) & 1; + readbllen = (csd[2] >> 16) & 0x0f; #ifdef CONFIG_DEBUG_FS_INFO - decoded.ccc = (csd[1] >> 20) & 0x0fff; - decoded.readbllen = (csd[1] >> 16) & 0x0f; - decoded.readblpartial = (csd[1] >> 15) & 1; - decoded.writeblkmisalign = (csd[1] >> 14) & 1; - decoded.readblkmisalign = (csd[1] >> 13) & 1; + decoded.ccc = (csd[2] >> 20) & 0x0fff; + decoded.readbllen = (csd[2] >> 16) & 0x0f; + decoded.readblpartial = (csd[2] >> 15) & 1; + decoded.writeblkmisalign = (csd[2] >> 14) & 1; + decoded.readblkmisalign = (csd[2] >> 13) & 1; decoded.dsrimp = priv->dsrimp; #endif @@ -657,7 +657,7 @@ static void mmcsd_decodeCSD(FAR struct mmcsd_state_s *priv, uint32_t csd[4]) * 512*1024 = (1 << 19) */ - uint32_t csize = ((csd[1] & 0x3f) << 16) | (csd[2] >> 16); + uint32_t csize = ((csd[2] & 0x3f) << 16) | (csd[1] >> 16); #ifdef CONFIG_HAVE_LONG_LONG priv->capacity = ((uint64_t)(csize + 1)) << 19; #else @@ -669,9 +669,9 @@ static void mmcsd_decodeCSD(FAR struct mmcsd_state_s *priv, uint32_t csd[4]) #ifdef CONFIG_DEBUG_FS_INFO decoded.u.sdblock.csize = csize; - decoded.u.sdblock.sderblen = (csd[2] >> 14) & 1; - decoded.u.sdblock.sdsectorsize = (csd[2] >> 7) & 0x7f; - decoded.u.sdblock.sdwpgrpsize = csd[2] & 0x7f; + decoded.u.sdblock.sderblen = (csd[1] >> 14) & 1; + decoded.u.sdblock.sdsectorsize = (csd[1] >> 7) & 0x7f; + decoded.u.sdblock.sdwpgrpsize = csd[1] & 0x7f; #endif } else @@ -681,8 +681,8 @@ static void mmcsd_decodeCSD(FAR struct mmcsd_state_s *priv, uint32_t csd[4]) * C_SIZE: 73:64 from Word 2 and 63:62 from Word 3 */ - uint16_t csize = ((csd[1] & 0x03ff) << 2) | ((csd[2] >> 30) & 3); - uint8_t csizemult = (csd[2] >> 15) & 7; + uint16_t csize = ((csd[2] & 0x03ff) << 2) | ((csd[1] >> 30) & 3); + uint8_t csizemult = (csd[1] >> 15) & 7; priv->nblocks = ((uint32_t)csize + 1) * (1 << (csizemult + 2)); priv->blockshift = readbllen; @@ -707,27 +707,27 @@ static void mmcsd_decodeCSD(FAR struct mmcsd_state_s *priv, uint32_t csd[4]) if (IS_SD(priv->type)) { decoded.u.sdbyte.csize = csize; - decoded.u.sdbyte.vddrcurrmin = (csd[2] >> 27) & 7; - decoded.u.sdbyte.vddrcurrmax = (csd[2] >> 24) & 7; - decoded.u.sdbyte.vddwcurrmin = (csd[2] >> 21) & 7; - decoded.u.sdbyte.vddwcurrmax = (csd[2] >> 18) & 7; + decoded.u.sdbyte.vddrcurrmin = (csd[1] >> 27) & 7; + decoded.u.sdbyte.vddrcurrmax = (csd[1] >> 24) & 7; + decoded.u.sdbyte.vddwcurrmin = (csd[1] >> 21) & 7; + decoded.u.sdbyte.vddwcurrmax = (csd[1] >> 18) & 7; decoded.u.sdbyte.csizemult = csizemult; - decoded.u.sdbyte.sderblen = (csd[2] >> 14) & 1; - decoded.u.sdbyte.sdsectorsize = (csd[2] >> 7) & 0x7f; - decoded.u.sdbyte.sdwpgrpsize = csd[2] & 0x7f; + decoded.u.sdbyte.sderblen = (csd[1] >> 14) & 1; + decoded.u.sdbyte.sdsectorsize = (csd[1] >> 7) & 0x7f; + decoded.u.sdbyte.sdwpgrpsize = csd[1] & 0x7f; } #ifdef CONFIG_MMCSD_MMCSUPPORT else if (IS_MMC(priv->type)) { decoded.u.mmc.csize = csize; - decoded.u.mmc.vddrcurrmin = (csd[2] >> 27) & 7; - decoded.u.mmc.vddrcurrmax = (csd[2] >> 24) & 7; - decoded.u.mmc.vddwcurrmin = (csd[2] >> 21) & 7; - decoded.u.mmc.vddwcurrmax = (csd[2] >> 18) & 7; + decoded.u.mmc.vddrcurrmin = (csd[1] >> 27) & 7; + decoded.u.mmc.vddrcurrmax = (csd[1] >> 24) & 7; + decoded.u.mmc.vddwcurrmin = (csd[1] >> 21) & 7; + decoded.u.mmc.vddwcurrmax = (csd[1] >> 18) & 7; decoded.u.mmc.csizemult = csizemult; - decoded.u.mmc.er.mmc22.sectorsize = (csd[2] >> 10) & 0x1f; - decoded.u.mmc.er.mmc22.ergrpsize = (csd[2] >> 5) & 0x1f; - decoded.u.mmc.mmcwpgrpsize = csd[2] & 0x1f; + decoded.u.mmc.er.mmc22.sectorsize = (csd[1] >> 10) & 0x1f; + decoded.u.mmc.er.mmc22.ergrpsize = (csd[1] >> 5) & 0x1f; + decoded.u.mmc.mmcwpgrpsize = csd[1] & 0x1f; } #endif #endif @@ -749,23 +749,23 @@ static void mmcsd_decodeCSD(FAR struct mmcsd_state_s *priv, uint32_t csd[4]) * Not used 0:0 */ - permwriteprotect = (csd[3] >> 13) & 1; - tmpwriteprotect = (csd[3] >> 12) & 1; + permwriteprotect = (csd[0] >> 13) & 1; + tmpwriteprotect = (csd[0] >> 12) & 1; priv->wrprotect = (permwriteprotect || tmpwriteprotect); #ifdef CONFIG_DEBUG_FS_INFO - decoded.wpgrpen = csd[3] >> 31; - decoded.mmcdfltecc = (csd[3] >> 29) & 3; - decoded.r2wfactor = (csd[3] >> 26) & 7; - decoded.writebllen = (csd[3] >> 22) & 0x0f; - decoded.writeblpartial = (csd[3] >> 21) & 1; - decoded.fileformatgrp = (csd[3] >> 15) & 1; - decoded.copy = (csd[3] >> 14) & 1; + decoded.wpgrpen = csd[0] >> 31; + decoded.mmcdfltecc = (csd[0] >> 29) & 3; + decoded.r2wfactor = (csd[0] >> 26) & 7; + decoded.writebllen = (csd[0] >> 22) & 0x0f; + decoded.writeblpartial = (csd[0] >> 21) & 1; + decoded.fileformatgrp = (csd[0] >> 15) & 1; + decoded.copy = (csd[0] >> 14) & 1; decoded.permwriteprotect = permwriteprotect; decoded.tmpwriteprotect = tmpwriteprotect; - decoded.fileformat = (csd[3] >> 10) & 3; - decoded.mmcecc = (csd[3] >> 8) & 3; - decoded.crc = (csd[3] >> 1) & 0x7f; + decoded.fileformat = (csd[0] >> 10) & 3; + decoded.mmcecc = (csd[0] >> 8) & 3; + decoded.crc = (csd[0] >> 1) & 0x7f; finfo("CSD:\n"); finfo(" CSD_STRUCTURE: %d SPEC_VERS: %d (MMC)\n", @@ -856,9 +856,9 @@ static void mmcsd_decodeCID(FAR struct mmcsd_state_s *priv, uint32_t cid[4]) * pnm[0] 103:96 */ - decoded.mid = cid[0] >> 24; - decoded.oid = (cid[0] >> 16) & 0xffff; - decoded.pnm[0] = cid[0] & 0xff; + decoded.mid = cid[3] >> 24; + decoded.oid = (cid[3] >> 8) & 0xffff; + decoded.pnm[0] = cid[3] & 0xff; /* Word 2: Bits 64:95 * pnm - 103-64 40-bit Product Name (ascii) + null terminator @@ -868,10 +868,10 @@ static void mmcsd_decodeCID(FAR struct mmcsd_state_s *priv, uint32_t cid[4]) * pnm[4] 71:64 */ - decoded.pnm[1] = cid[1] >> 24; - decoded.pnm[2] = (cid[1] >> 16) & 0xff; - decoded.pnm[3] = (cid[1] >> 8) & 0xff; - decoded.pnm[4] = cid[1] & 0xff; + decoded.pnm[1] = cid[2] >> 24; + decoded.pnm[2] = (cid[2] >> 16) & 0xff; + decoded.pnm[3] = (cid[2] >> 8) & 0xff; + decoded.pnm[4] = cid[2] & 0xff; decoded.pnm[5] = '\0'; /* Word 3: Bits 32-63 @@ -879,8 +879,8 @@ static void mmcsd_decodeCID(FAR struct mmcsd_state_s *priv, uint32_t cid[4]) * psn - 55-24 32-bit Product serial number */ - decoded.prv = cid[2] >> 24; - decoded.psn = cid[2] << 8; + decoded.prv = cid[1] >> 24; + decoded.psn = cid[1] << 8; /* Word 4: Bits 0-31 * psn - 55-24 32-bit Product serial number @@ -889,11 +889,11 @@ static void mmcsd_decodeCID(FAR struct mmcsd_state_s *priv, uint32_t cid[4]) * crc - 7:1 7-bit CRC7 */ - decoded.psn |= cid[3] >> 24; - decoded.mdt = (cid[3] >> 8) & 0x0fff; - decoded.crc = (cid[3] >> 1) & 0x7f; + decoded.psn |= cid[0] >> 24; + decoded.mdt = (cid[0] >> 8) & 0x0fff; + decoded.crc = (cid[0] >> 1) & 0x7f; - finfo("mid: %02x oid: %04x pnm: %s prv: %d psn: %d mdt: %02x crc: %02x\n", + finfo("mid: %02x oid: %04x pnm: %s prv: %d psn: %lu mdt: %02x crc: %02x\n", decoded.mid, decoded.oid, decoded.pnm, decoded.prv, decoded.psn, decoded.mdt, decoded.crc); } -- GitLab From 5755f2348c9dced599c7ce9e89b1e5d9e263d0b2 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 14 Dec 2016 14:57:43 -0600 Subject: [PATCH 695/734] Fix some crap left in README from copy and paste. --- configs/esp32-core/README.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index 8b10ffc6f0..5e6df6662f 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -522,7 +522,9 @@ SMP CONFIG_DEBUG_SYMBOLS=y CONFIG_ESP32CORE_RUN_IRAM=y - I also made this change which will eliminate all attempts to re-configure serial. It will just use the serial settings as they were left by the bootloader: + I also made this change which will eliminate all attempts to re-configure + serial. It will just use the serial settings as they were left by the + bootloader: diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index 422ec0b..8707d7c 100644 @@ -551,7 +553,7 @@ SMP (gdb) mon reg pc [value report by load for entry point] (gdb) s - Single stepping works fine for me as do breakpoints. I get quite a way through initialization, into os_start() and into up_initialize(), and through up_irqinitialize() but it fails in xtensa_timer_initialize() immediatly upon enabling interrupts: + Single stepping works fine for me as do breakpoints: Breakpoint 1, xtensa_timer_initialize () at chip/esp32_timerisr.c:172 72 { -- GitLab From f4f32bc740cf0973714025a3bebcaadc26a080e9 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 14 Dec 2016 17:04:27 -0600 Subject: [PATCH 696/734] MMC/SD SDIO (again): This is really an endian-ness issue. Behavior should be different on big- vs little-endian machines. --- drivers/mmcsd/mmcsd_sdio.c | 152 ++++++++++++++++++++----------------- 1 file changed, 83 insertions(+), 69 deletions(-) diff --git a/drivers/mmcsd/mmcsd_sdio.c b/drivers/mmcsd/mmcsd_sdio.c index 13f86102e4..5c6df6874b 100644 --- a/drivers/mmcsd/mmcsd_sdio.c +++ b/drivers/mmcsd/mmcsd_sdio.c @@ -100,6 +100,20 @@ #define IS_EMPTY(priv) (priv->type == MMCSD_CARDTYPE_UNKNOWN) +/* Handle endian-ness */ + +#ifdef CONFIG_ENDIAN_BIG +# define NDXA 3 /* Bits n through n+7 */ +# define NDXB 2 /* Bits n+8 through n+15 */ +# define NDXC 1 /* Bits n+16 through n+23 */ +# define NDXD 0 /* Bits n+24 through n+31 */ +#else +# define NDXA 0 /* Bits n through n+7 */ +# define NDXB 1 /* Bits n+8 through n+15 */ +# define NDXC 2 /* Bits n+16 through n+23 */ +# define NDXD 3 /* Bits n+24 through n+31 */ +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -580,13 +594,13 @@ static void mmcsd_decodeCSD(FAR struct mmcsd_state_s *priv, uint32_t csd[4]) #ifdef CONFIG_DEBUG_FS_INFO memset(&decoded, 0, sizeof(struct mmcsd_csd_s)); - decoded.csdstructure = csd[3] >> 30; - decoded.mmcspecvers = (csd[3] >> 26) & 0x0f; - decoded.taac.timevalue = (csd[3] >> 19) & 0x0f; - decoded.taac.timeunit = (csd[3] >> 16) & 7; - decoded.nsac = (csd[3] >> 8) & 0xff; - decoded.transpeed.timevalue = (csd[3] >> 3) & 0x0f; - decoded.transpeed.transferrateunit = csd[3] & 7; + decoded.csdstructure = csd[NDXD] >> 30; + decoded.mmcspecvers = (csd[NDXD] >> 26) & 0x0f; + decoded.taac.timevalue = (csd[NDXD] >> 19) & 0x0f; + decoded.taac.timeunit = (csd[NDXD] >> 16) & 7; + decoded.nsac = (csd[NDXD] >> 8) & 0xff; + decoded.transpeed.timevalue = (csd[NDXD] >> 3) & 0x0f; + decoded.transpeed.transferrateunit = csd[NDXD] & 7; #endif /* Word 2: Bits 64:95 @@ -603,15 +617,15 @@ static void mmcsd_decodeCSD(FAR struct mmcsd_state_s *priv, uint32_t csd[4]) * C_SIZE 48:69 Device size */ - priv->dsrimp = (csd[2] >> 12) & 1; - readbllen = (csd[2] >> 16) & 0x0f; + priv->dsrimp = (csd[NDXC] >> 12) & 1; + readbllen = (csd[NDXC] >> 16) & 0x0f; #ifdef CONFIG_DEBUG_FS_INFO - decoded.ccc = (csd[2] >> 20) & 0x0fff; - decoded.readbllen = (csd[2] >> 16) & 0x0f; - decoded.readblpartial = (csd[2] >> 15) & 1; - decoded.writeblkmisalign = (csd[2] >> 14) & 1; - decoded.readblkmisalign = (csd[2] >> 13) & 1; + decoded.ccc = (csd[NDXC] >> 20) & 0x0fff; + decoded.readbllen = (csd[NDXC] >> 16) & 0x0f; + decoded.readblpartial = (csd[NDXC] >> 15) & 1; + decoded.writeblkmisalign = (csd[NDXC] >> 14) & 1; + decoded.readblkmisalign = (csd[NDXC] >> 13) & 1; decoded.dsrimp = priv->dsrimp; #endif @@ -657,7 +671,7 @@ static void mmcsd_decodeCSD(FAR struct mmcsd_state_s *priv, uint32_t csd[4]) * 512*1024 = (1 << 19) */ - uint32_t csize = ((csd[2] & 0x3f) << 16) | (csd[1] >> 16); + uint32_t csize = ((csd[NDXC] & 0x3f) << 16) | (csd[NDXB] >> 16); #ifdef CONFIG_HAVE_LONG_LONG priv->capacity = ((uint64_t)(csize + 1)) << 19; #else @@ -669,9 +683,9 @@ static void mmcsd_decodeCSD(FAR struct mmcsd_state_s *priv, uint32_t csd[4]) #ifdef CONFIG_DEBUG_FS_INFO decoded.u.sdblock.csize = csize; - decoded.u.sdblock.sderblen = (csd[1] >> 14) & 1; - decoded.u.sdblock.sdsectorsize = (csd[1] >> 7) & 0x7f; - decoded.u.sdblock.sdwpgrpsize = csd[1] & 0x7f; + decoded.u.sdblock.sderblen = (csd[NDXB] >> 14) & 1; + decoded.u.sdblock.sdsectorsize = (csd[NDXB] >> 7) & 0x7f; + decoded.u.sdblock.sdwpgrpsize = csd[NDXB] & 0x7f; #endif } else @@ -681,8 +695,8 @@ static void mmcsd_decodeCSD(FAR struct mmcsd_state_s *priv, uint32_t csd[4]) * C_SIZE: 73:64 from Word 2 and 63:62 from Word 3 */ - uint16_t csize = ((csd[2] & 0x03ff) << 2) | ((csd[1] >> 30) & 3); - uint8_t csizemult = (csd[1] >> 15) & 7; + uint16_t csize = ((csd[NDXC] & 0x03ff) << 2) | ((csd[NDXB] >> 30) & 3); + uint8_t csizemult = (csd[NDXB] >> 15) & 7; priv->nblocks = ((uint32_t)csize + 1) * (1 << (csizemult + 2)); priv->blockshift = readbllen; @@ -707,27 +721,27 @@ static void mmcsd_decodeCSD(FAR struct mmcsd_state_s *priv, uint32_t csd[4]) if (IS_SD(priv->type)) { decoded.u.sdbyte.csize = csize; - decoded.u.sdbyte.vddrcurrmin = (csd[1] >> 27) & 7; - decoded.u.sdbyte.vddrcurrmax = (csd[1] >> 24) & 7; - decoded.u.sdbyte.vddwcurrmin = (csd[1] >> 21) & 7; - decoded.u.sdbyte.vddwcurrmax = (csd[1] >> 18) & 7; + decoded.u.sdbyte.vddrcurrmin = (csd[NDXB] >> 27) & 7; + decoded.u.sdbyte.vddrcurrmax = (csd[NDXB] >> 24) & 7; + decoded.u.sdbyte.vddwcurrmin = (csd[NDXB] >> 21) & 7; + decoded.u.sdbyte.vddwcurrmax = (csd[NDXB] >> 18) & 7; decoded.u.sdbyte.csizemult = csizemult; - decoded.u.sdbyte.sderblen = (csd[1] >> 14) & 1; - decoded.u.sdbyte.sdsectorsize = (csd[1] >> 7) & 0x7f; - decoded.u.sdbyte.sdwpgrpsize = csd[1] & 0x7f; + decoded.u.sdbyte.sderblen = (csd[NDXB] >> 14) & 1; + decoded.u.sdbyte.sdsectorsize = (csd[NDXB] >> 7) & 0x7f; + decoded.u.sdbyte.sdwpgrpsize = csd[NDXB] & 0x7f; } #ifdef CONFIG_MMCSD_MMCSUPPORT else if (IS_MMC(priv->type)) { decoded.u.mmc.csize = csize; - decoded.u.mmc.vddrcurrmin = (csd[1] >> 27) & 7; - decoded.u.mmc.vddrcurrmax = (csd[1] >> 24) & 7; - decoded.u.mmc.vddwcurrmin = (csd[1] >> 21) & 7; - decoded.u.mmc.vddwcurrmax = (csd[1] >> 18) & 7; + decoded.u.mmc.vddrcurrmin = (csd[NDXB] >> 27) & 7; + decoded.u.mmc.vddrcurrmax = (csd[NDXB] >> 24) & 7; + decoded.u.mmc.vddwcurrmin = (csd[NDXB] >> 21) & 7; + decoded.u.mmc.vddwcurrmax = (csd[NDXB] >> 18) & 7; decoded.u.mmc.csizemult = csizemult; - decoded.u.mmc.er.mmc22.sectorsize = (csd[1] >> 10) & 0x1f; - decoded.u.mmc.er.mmc22.ergrpsize = (csd[1] >> 5) & 0x1f; - decoded.u.mmc.mmcwpgrpsize = csd[1] & 0x1f; + decoded.u.mmc.er.mmc22.sectorsize = (csd[NDXB] >> 10) & 0x1f; + decoded.u.mmc.er.mmc22.ergrpsize = (csd[NDXB] >> 5) & 0x1f; + decoded.u.mmc.mmcwpgrpsize = csd[NDXB] & 0x1f; } #endif #endif @@ -749,23 +763,23 @@ static void mmcsd_decodeCSD(FAR struct mmcsd_state_s *priv, uint32_t csd[4]) * Not used 0:0 */ - permwriteprotect = (csd[0] >> 13) & 1; - tmpwriteprotect = (csd[0] >> 12) & 1; + permwriteprotect = (csd[NDXA] >> 13) & 1; + tmpwriteprotect = (csd[NDXA] >> 12) & 1; priv->wrprotect = (permwriteprotect || tmpwriteprotect); #ifdef CONFIG_DEBUG_FS_INFO - decoded.wpgrpen = csd[0] >> 31; - decoded.mmcdfltecc = (csd[0] >> 29) & 3; - decoded.r2wfactor = (csd[0] >> 26) & 7; - decoded.writebllen = (csd[0] >> 22) & 0x0f; - decoded.writeblpartial = (csd[0] >> 21) & 1; - decoded.fileformatgrp = (csd[0] >> 15) & 1; - decoded.copy = (csd[0] >> 14) & 1; + decoded.wpgrpen = csd[NDXA] >> 31; + decoded.mmcdfltecc = (csd[NDXA] >> 29) & 3; + decoded.r2wfactor = (csd[NDXA] >> 26) & 7; + decoded.writebllen = (csd[NDXA] >> 22) & 0x0f; + decoded.writeblpartial = (csd[NDXA] >> 21) & 1; + decoded.fileformatgrp = (csd[NDXA] >> 15) & 1; + decoded.copy = (csd[NDXA] >> 14) & 1; decoded.permwriteprotect = permwriteprotect; decoded.tmpwriteprotect = tmpwriteprotect; - decoded.fileformat = (csd[0] >> 10) & 3; - decoded.mmcecc = (csd[0] >> 8) & 3; - decoded.crc = (csd[0] >> 1) & 0x7f; + decoded.fileformat = (csd[NDXA] >> 10) & 3; + decoded.mmcecc = (csd[NDXA] >> 8) & 3; + decoded.crc = (csd[NDXA] >> 1) & 0x7f; finfo("CSD:\n"); finfo(" CSD_STRUCTURE: %d SPEC_VERS: %d (MMC)\n", @@ -856,9 +870,9 @@ static void mmcsd_decodeCID(FAR struct mmcsd_state_s *priv, uint32_t cid[4]) * pnm[0] 103:96 */ - decoded.mid = cid[3] >> 24; - decoded.oid = (cid[3] >> 8) & 0xffff; - decoded.pnm[0] = cid[3] & 0xff; + decoded.mid = cid[NDXD] >> 24; + decoded.oid = (cid[NDXD] >> 8) & 0xffff; + decoded.pnm[0] = cid[NDXD] & 0xff; /* Word 2: Bits 64:95 * pnm - 103-64 40-bit Product Name (ascii) + null terminator @@ -868,10 +882,10 @@ static void mmcsd_decodeCID(FAR struct mmcsd_state_s *priv, uint32_t cid[4]) * pnm[4] 71:64 */ - decoded.pnm[1] = cid[2] >> 24; - decoded.pnm[2] = (cid[2] >> 16) & 0xff; - decoded.pnm[3] = (cid[2] >> 8) & 0xff; - decoded.pnm[4] = cid[2] & 0xff; + decoded.pnm[1] = cid[NDXC] >> 24; + decoded.pnm[2] = (cid[NDXC] >> 16) & 0xff; + decoded.pnm[3] = (cid[NDXC] >> 8) & 0xff; + decoded.pnm[4] = cid[NDXC] & 0xff; decoded.pnm[5] = '\0'; /* Word 3: Bits 32-63 @@ -879,8 +893,8 @@ static void mmcsd_decodeCID(FAR struct mmcsd_state_s *priv, uint32_t cid[4]) * psn - 55-24 32-bit Product serial number */ - decoded.prv = cid[1] >> 24; - decoded.psn = cid[1] << 8; + decoded.prv = cid[NDXB] >> 24; + decoded.psn = cid[NDXB] << 8; /* Word 4: Bits 0-31 * psn - 55-24 32-bit Product serial number @@ -889,9 +903,9 @@ static void mmcsd_decodeCID(FAR struct mmcsd_state_s *priv, uint32_t cid[4]) * crc - 7:1 7-bit CRC7 */ - decoded.psn |= cid[0] >> 24; - decoded.mdt = (cid[0] >> 8) & 0x0fff; - decoded.crc = (cid[0] >> 1) & 0x7f; + decoded.psn |= cid[NDXA] >> 24; + decoded.mdt = (cid[NDXA] >> 8) & 0x0fff; + decoded.crc = (cid[NDXA] >> 1) & 0x7f; finfo("mid: %02x oid: %04x pnm: %s prv: %d psn: %lu mdt: %02x crc: %02x\n", decoded.mid, decoded.oid, decoded.pnm, decoded.prv, @@ -924,26 +938,26 @@ struct mmcsd_scr_s decoded; */ #ifdef CONFIG_ENDIAN_BIG /* Card transfers SCR in big-endian order */ - priv->buswidth = (scr[0] >> 16) & 15; + priv->buswidth = (scr[NDXA] >> 16) & 15; #else - priv->buswidth = (scr[0] >> 8) & 15; + priv->buswidth = (scr[NDXA] >> 8) & 15; #endif #ifdef CONFIG_DEBUG_FS_INFO #ifdef CONFIG_ENDIAN_BIG /* Card SCR is big-endian order / CPU also big-endian * 60 56 52 48 44 40 36 32 * VVVV SSSS ESSS BBBB RRRR RRRR RRRR RRRR */ - decoded.scrversion = scr[0] >> 28; - decoded.sdversion = (scr[0] >> 24) & 15; - decoded.erasestate = (scr[0] >> 23) & 1; - decoded.security = (scr[0] >> 20) & 7; + decoded.scrversion = scr[NDXA] >> 28; + decoded.sdversion = (scr[NDXA] >> 24) & 15; + decoded.erasestate = (scr[NDXA] >> 23) & 1; + decoded.security = (scr[NDXA] >> 20) & 7; #else /* Card SCR is big-endian order / CPU is little-endian * 36 32 44 40 52 48 60 56 * RRRR RRRR RRRR RRRR ESSS BBBB VVVV SSSS */ - decoded.scrversion = (scr[0] >> 4) & 15; - decoded.sdversion = scr[0] & 15; - decoded.erasestate = (scr[0] >> 15) & 1; - decoded.security = (scr[0] >> 12) & 7; + decoded.scrversion = (scr[NDXA] >> 4) & 15; + decoded.sdversion = scr[NDXA] & 15; + decoded.erasestate = (scr[NDXA] >> 15) & 1; + decoded.security = (scr[NDXA] >> 12) & 7; #endif decoded.buswidth = priv->buswidth; #endif @@ -953,7 +967,7 @@ struct mmcsd_scr_s decoded; */ #ifdef CONFIG_DEBUG_FS_INFO - decoded.mfgdata = scr[1]; /* Might be byte reversed! */ + decoded.mfgdata = scr[NDXB]; /* Might be byte reversed! */ finfo("SCR:\n"); finfo(" SCR_STRUCTURE: %d SD_VERSION: %d\n", -- GitLab From ca92ecafa7b2c619caaf598c35cff10298bcf62a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 14 Dec 2016 17:44:12 -0600 Subject: [PATCH 697/734] MMC/SD: Format changed from %d to %lu. Must cast argument to unsigned long to avoid crash on 64-bit machine. --- drivers/mmcsd/mmcsd_sdio.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/mmcsd/mmcsd_sdio.c b/drivers/mmcsd/mmcsd_sdio.c index 5c6df6874b..ae4bb7a0d1 100644 --- a/drivers/mmcsd/mmcsd_sdio.c +++ b/drivers/mmcsd/mmcsd_sdio.c @@ -909,7 +909,7 @@ static void mmcsd_decodeCID(FAR struct mmcsd_state_s *priv, uint32_t cid[4]) finfo("mid: %02x oid: %04x pnm: %s prv: %d psn: %lu mdt: %02x crc: %02x\n", decoded.mid, decoded.oid, decoded.pnm, decoded.prv, - decoded.psn, decoded.mdt, decoded.crc); + (unsigned long)decoded.psn, decoded.mdt, decoded.crc); } #endif @@ -2248,7 +2248,8 @@ static int mmcsd_geometry(FAR struct inode *inode, struct geometry *geometry) geometry->geo_mediachanged ? "true" : "false", geometry->geo_writeenabled ? "true" : "false"); finfo("nsectors: %lu sectorsize: %d\n", - (long)geometry->geo_nsectors, geometry->geo_sectorsize); + ((unsigned long))geometry->geo_nsectors, + geometry->geo_sectorsize); priv->mediachanged = false; ret = OK; -- GitLab From 4795d58e03040b927d6e5b5f5177980dd0f45d84 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 15 Dec 2016 07:16:24 -0600 Subject: [PATCH 698/734] Back out most of 46dbbe837e745d9d43cc9d9963ae52954f694f54. The order is correct -- or, rather, the order is the same as the order that response data is provided. Change the order will break all other drivers. --- arch/arm/src/lpc17xx/lpc17_sdcard.c | 1 + arch/arm/src/stm32/stm32_sdio.c | 1 + drivers/mmcsd/mmcsd_sdio.c | 152 +++++++++++++--------------- 3 files changed, 71 insertions(+), 83 deletions(-) diff --git a/arch/arm/src/lpc17xx/lpc17_sdcard.c b/arch/arm/src/lpc17xx/lpc17_sdcard.c index 532c8ed35d..b4b555f5de 100644 --- a/arch/arm/src/lpc17xx/lpc17_sdcard.c +++ b/arch/arm/src/lpc17xx/lpc17_sdcard.c @@ -2086,6 +2086,7 @@ static int lpc17_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlo rlong[2] = getreg32(LPC17_SDCARD_RESP2); rlong[3] = getreg32(LPC17_SDCARD_RESP3); } + return ret; } diff --git a/arch/arm/src/stm32/stm32_sdio.c b/arch/arm/src/stm32/stm32_sdio.c index 9d93a432c0..f4b6b6ce87 100644 --- a/arch/arm/src/stm32/stm32_sdio.c +++ b/arch/arm/src/stm32/stm32_sdio.c @@ -2209,6 +2209,7 @@ static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlo rlong[2] = getreg32(STM32_SDIO_RESP3); rlong[3] = getreg32(STM32_SDIO_RESP4); } + return ret; } diff --git a/drivers/mmcsd/mmcsd_sdio.c b/drivers/mmcsd/mmcsd_sdio.c index ae4bb7a0d1..9c93cefd4b 100644 --- a/drivers/mmcsd/mmcsd_sdio.c +++ b/drivers/mmcsd/mmcsd_sdio.c @@ -100,20 +100,6 @@ #define IS_EMPTY(priv) (priv->type == MMCSD_CARDTYPE_UNKNOWN) -/* Handle endian-ness */ - -#ifdef CONFIG_ENDIAN_BIG -# define NDXA 3 /* Bits n through n+7 */ -# define NDXB 2 /* Bits n+8 through n+15 */ -# define NDXC 1 /* Bits n+16 through n+23 */ -# define NDXD 0 /* Bits n+24 through n+31 */ -#else -# define NDXA 0 /* Bits n through n+7 */ -# define NDXB 1 /* Bits n+8 through n+15 */ -# define NDXC 2 /* Bits n+16 through n+23 */ -# define NDXD 3 /* Bits n+24 through n+31 */ -#endif - /**************************************************************************** * Private Types ****************************************************************************/ @@ -594,13 +580,13 @@ static void mmcsd_decodeCSD(FAR struct mmcsd_state_s *priv, uint32_t csd[4]) #ifdef CONFIG_DEBUG_FS_INFO memset(&decoded, 0, sizeof(struct mmcsd_csd_s)); - decoded.csdstructure = csd[NDXD] >> 30; - decoded.mmcspecvers = (csd[NDXD] >> 26) & 0x0f; - decoded.taac.timevalue = (csd[NDXD] >> 19) & 0x0f; - decoded.taac.timeunit = (csd[NDXD] >> 16) & 7; - decoded.nsac = (csd[NDXD] >> 8) & 0xff; - decoded.transpeed.timevalue = (csd[NDXD] >> 3) & 0x0f; - decoded.transpeed.transferrateunit = csd[NDXD] & 7; + decoded.csdstructure = csd[0] >> 30; + decoded.mmcspecvers = (csd[0] >> 26) & 0x0f; + decoded.taac.timevalue = (csd[0] >> 19) & 0x0f; + decoded.taac.timeunit = (csd[0] >> 16) & 7; + decoded.nsac = (csd[0] >> 8) & 0xff; + decoded.transpeed.timevalue = (csd[0] >> 3) & 0x0f; + decoded.transpeed.transferrateunit = csd[0] & 7; #endif /* Word 2: Bits 64:95 @@ -617,15 +603,15 @@ static void mmcsd_decodeCSD(FAR struct mmcsd_state_s *priv, uint32_t csd[4]) * C_SIZE 48:69 Device size */ - priv->dsrimp = (csd[NDXC] >> 12) & 1; - readbllen = (csd[NDXC] >> 16) & 0x0f; + priv->dsrimp = (csd[1] >> 12) & 1; + readbllen = (csd[1] >> 16) & 0x0f; #ifdef CONFIG_DEBUG_FS_INFO - decoded.ccc = (csd[NDXC] >> 20) & 0x0fff; - decoded.readbllen = (csd[NDXC] >> 16) & 0x0f; - decoded.readblpartial = (csd[NDXC] >> 15) & 1; - decoded.writeblkmisalign = (csd[NDXC] >> 14) & 1; - decoded.readblkmisalign = (csd[NDXC] >> 13) & 1; + decoded.ccc = (csd[1] >> 20) & 0x0fff; + decoded.readbllen = (csd[1] >> 16) & 0x0f; + decoded.readblpartial = (csd[1] >> 15) & 1; + decoded.writeblkmisalign = (csd[1] >> 14) & 1; + decoded.readblkmisalign = (csd[1] >> 13) & 1; decoded.dsrimp = priv->dsrimp; #endif @@ -671,7 +657,7 @@ static void mmcsd_decodeCSD(FAR struct mmcsd_state_s *priv, uint32_t csd[4]) * 512*1024 = (1 << 19) */ - uint32_t csize = ((csd[NDXC] & 0x3f) << 16) | (csd[NDXB] >> 16); + uint32_t csize = ((csd[1] & 0x3f) << 16) | (csd[2] >> 16); #ifdef CONFIG_HAVE_LONG_LONG priv->capacity = ((uint64_t)(csize + 1)) << 19; #else @@ -683,9 +669,9 @@ static void mmcsd_decodeCSD(FAR struct mmcsd_state_s *priv, uint32_t csd[4]) #ifdef CONFIG_DEBUG_FS_INFO decoded.u.sdblock.csize = csize; - decoded.u.sdblock.sderblen = (csd[NDXB] >> 14) & 1; - decoded.u.sdblock.sdsectorsize = (csd[NDXB] >> 7) & 0x7f; - decoded.u.sdblock.sdwpgrpsize = csd[NDXB] & 0x7f; + decoded.u.sdblock.sderblen = (csd[2] >> 14) & 1; + decoded.u.sdblock.sdsectorsize = (csd[2] >> 7) & 0x7f; + decoded.u.sdblock.sdwpgrpsize = csd[2] & 0x7f; #endif } else @@ -695,8 +681,8 @@ static void mmcsd_decodeCSD(FAR struct mmcsd_state_s *priv, uint32_t csd[4]) * C_SIZE: 73:64 from Word 2 and 63:62 from Word 3 */ - uint16_t csize = ((csd[NDXC] & 0x03ff) << 2) | ((csd[NDXB] >> 30) & 3); - uint8_t csizemult = (csd[NDXB] >> 15) & 7; + uint16_t csize = ((csd[1] & 0x03ff) << 2) | ((csd[2] >> 30) & 3); + uint8_t csizemult = (csd[2] >> 15) & 7; priv->nblocks = ((uint32_t)csize + 1) * (1 << (csizemult + 2)); priv->blockshift = readbllen; @@ -721,27 +707,27 @@ static void mmcsd_decodeCSD(FAR struct mmcsd_state_s *priv, uint32_t csd[4]) if (IS_SD(priv->type)) { decoded.u.sdbyte.csize = csize; - decoded.u.sdbyte.vddrcurrmin = (csd[NDXB] >> 27) & 7; - decoded.u.sdbyte.vddrcurrmax = (csd[NDXB] >> 24) & 7; - decoded.u.sdbyte.vddwcurrmin = (csd[NDXB] >> 21) & 7; - decoded.u.sdbyte.vddwcurrmax = (csd[NDXB] >> 18) & 7; + decoded.u.sdbyte.vddrcurrmin = (csd[2] >> 27) & 7; + decoded.u.sdbyte.vddrcurrmax = (csd[2] >> 24) & 7; + decoded.u.sdbyte.vddwcurrmin = (csd[2] >> 21) & 7; + decoded.u.sdbyte.vddwcurrmax = (csd[2] >> 18) & 7; decoded.u.sdbyte.csizemult = csizemult; - decoded.u.sdbyte.sderblen = (csd[NDXB] >> 14) & 1; - decoded.u.sdbyte.sdsectorsize = (csd[NDXB] >> 7) & 0x7f; - decoded.u.sdbyte.sdwpgrpsize = csd[NDXB] & 0x7f; + decoded.u.sdbyte.sderblen = (csd[2] >> 14) & 1; + decoded.u.sdbyte.sdsectorsize = (csd[2] >> 7) & 0x7f; + decoded.u.sdbyte.sdwpgrpsize = csd[2] & 0x7f; } #ifdef CONFIG_MMCSD_MMCSUPPORT else if (IS_MMC(priv->type)) { decoded.u.mmc.csize = csize; - decoded.u.mmc.vddrcurrmin = (csd[NDXB] >> 27) & 7; - decoded.u.mmc.vddrcurrmax = (csd[NDXB] >> 24) & 7; - decoded.u.mmc.vddwcurrmin = (csd[NDXB] >> 21) & 7; - decoded.u.mmc.vddwcurrmax = (csd[NDXB] >> 18) & 7; + decoded.u.mmc.vddrcurrmin = (csd[2] >> 27) & 7; + decoded.u.mmc.vddrcurrmax = (csd[2] >> 24) & 7; + decoded.u.mmc.vddwcurrmin = (csd[2] >> 21) & 7; + decoded.u.mmc.vddwcurrmax = (csd[2] >> 18) & 7; decoded.u.mmc.csizemult = csizemult; - decoded.u.mmc.er.mmc22.sectorsize = (csd[NDXB] >> 10) & 0x1f; - decoded.u.mmc.er.mmc22.ergrpsize = (csd[NDXB] >> 5) & 0x1f; - decoded.u.mmc.mmcwpgrpsize = csd[NDXB] & 0x1f; + decoded.u.mmc.er.mmc22.sectorsize = (csd[2] >> 10) & 0x1f; + decoded.u.mmc.er.mmc22.ergrpsize = (csd[2] >> 5) & 0x1f; + decoded.u.mmc.mmcwpgrpsize = csd[2] & 0x1f; } #endif #endif @@ -763,23 +749,23 @@ static void mmcsd_decodeCSD(FAR struct mmcsd_state_s *priv, uint32_t csd[4]) * Not used 0:0 */ - permwriteprotect = (csd[NDXA] >> 13) & 1; - tmpwriteprotect = (csd[NDXA] >> 12) & 1; + permwriteprotect = (csd[3] >> 13) & 1; + tmpwriteprotect = (csd[3] >> 12) & 1; priv->wrprotect = (permwriteprotect || tmpwriteprotect); #ifdef CONFIG_DEBUG_FS_INFO - decoded.wpgrpen = csd[NDXA] >> 31; - decoded.mmcdfltecc = (csd[NDXA] >> 29) & 3; - decoded.r2wfactor = (csd[NDXA] >> 26) & 7; - decoded.writebllen = (csd[NDXA] >> 22) & 0x0f; - decoded.writeblpartial = (csd[NDXA] >> 21) & 1; - decoded.fileformatgrp = (csd[NDXA] >> 15) & 1; - decoded.copy = (csd[NDXA] >> 14) & 1; + decoded.wpgrpen = csd[3] >> 31; + decoded.mmcdfltecc = (csd[3] >> 29) & 3; + decoded.r2wfactor = (csd[3] >> 26) & 7; + decoded.writebllen = (csd[3] >> 22) & 0x0f; + decoded.writeblpartial = (csd[3] >> 21) & 1; + decoded.fileformatgrp = (csd[3] >> 15) & 1; + decoded.copy = (csd[3] >> 14) & 1; decoded.permwriteprotect = permwriteprotect; decoded.tmpwriteprotect = tmpwriteprotect; - decoded.fileformat = (csd[NDXA] >> 10) & 3; - decoded.mmcecc = (csd[NDXA] >> 8) & 3; - decoded.crc = (csd[NDXA] >> 1) & 0x7f; + decoded.fileformat = (csd[3] >> 10) & 3; + decoded.mmcecc = (csd[3] >> 8) & 3; + decoded.crc = (csd[3] >> 1) & 0x7f; finfo("CSD:\n"); finfo(" CSD_STRUCTURE: %d SPEC_VERS: %d (MMC)\n", @@ -870,9 +856,9 @@ static void mmcsd_decodeCID(FAR struct mmcsd_state_s *priv, uint32_t cid[4]) * pnm[0] 103:96 */ - decoded.mid = cid[NDXD] >> 24; - decoded.oid = (cid[NDXD] >> 8) & 0xffff; - decoded.pnm[0] = cid[NDXD] & 0xff; + decoded.mid = cid[0] >> 24; + decoded.oid = (cid[0] >> 8) & 0xffff; + decoded.pnm[0] = cid[0] & 0xff; /* Word 2: Bits 64:95 * pnm - 103-64 40-bit Product Name (ascii) + null terminator @@ -882,10 +868,10 @@ static void mmcsd_decodeCID(FAR struct mmcsd_state_s *priv, uint32_t cid[4]) * pnm[4] 71:64 */ - decoded.pnm[1] = cid[NDXC] >> 24; - decoded.pnm[2] = (cid[NDXC] >> 16) & 0xff; - decoded.pnm[3] = (cid[NDXC] >> 8) & 0xff; - decoded.pnm[4] = cid[NDXC] & 0xff; + decoded.pnm[1] = cid[1] >> 24; + decoded.pnm[2] = (cid[1] >> 16) & 0xff; + decoded.pnm[3] = (cid[1] >> 8) & 0xff; + decoded.pnm[4] = cid[1] & 0xff; decoded.pnm[5] = '\0'; /* Word 3: Bits 32-63 @@ -893,8 +879,8 @@ static void mmcsd_decodeCID(FAR struct mmcsd_state_s *priv, uint32_t cid[4]) * psn - 55-24 32-bit Product serial number */ - decoded.prv = cid[NDXB] >> 24; - decoded.psn = cid[NDXB] << 8; + decoded.prv = cid[2] >> 24; + decoded.psn = cid[2] << 8; /* Word 4: Bits 0-31 * psn - 55-24 32-bit Product serial number @@ -903,9 +889,9 @@ static void mmcsd_decodeCID(FAR struct mmcsd_state_s *priv, uint32_t cid[4]) * crc - 7:1 7-bit CRC7 */ - decoded.psn |= cid[NDXA] >> 24; - decoded.mdt = (cid[NDXA] >> 8) & 0x0fff; - decoded.crc = (cid[NDXA] >> 1) & 0x7f; + decoded.psn |= cid[3] >> 24; + decoded.mdt = (cid[3] >> 8) & 0x0fff; + decoded.crc = (cid[3] >> 1) & 0x7f; finfo("mid: %02x oid: %04x pnm: %s prv: %d psn: %lu mdt: %02x crc: %02x\n", decoded.mid, decoded.oid, decoded.pnm, decoded.prv, @@ -938,26 +924,26 @@ struct mmcsd_scr_s decoded; */ #ifdef CONFIG_ENDIAN_BIG /* Card transfers SCR in big-endian order */ - priv->buswidth = (scr[NDXA] >> 16) & 15; + priv->buswidth = (scr[0] >> 16) & 15; #else - priv->buswidth = (scr[NDXA] >> 8) & 15; + priv->buswidth = (scr[0] >> 8) & 15; #endif #ifdef CONFIG_DEBUG_FS_INFO #ifdef CONFIG_ENDIAN_BIG /* Card SCR is big-endian order / CPU also big-endian * 60 56 52 48 44 40 36 32 * VVVV SSSS ESSS BBBB RRRR RRRR RRRR RRRR */ - decoded.scrversion = scr[NDXA] >> 28; - decoded.sdversion = (scr[NDXA] >> 24) & 15; - decoded.erasestate = (scr[NDXA] >> 23) & 1; - decoded.security = (scr[NDXA] >> 20) & 7; + decoded.scrversion = scr[0] >> 28; + decoded.sdversion = (scr[0] >> 24) & 15; + decoded.erasestate = (scr[0] >> 23) & 1; + decoded.security = (scr[0] >> 20) & 7; #else /* Card SCR is big-endian order / CPU is little-endian * 36 32 44 40 52 48 60 56 * RRRR RRRR RRRR RRRR ESSS BBBB VVVV SSSS */ - decoded.scrversion = (scr[NDXA] >> 4) & 15; - decoded.sdversion = scr[NDXA] & 15; - decoded.erasestate = (scr[NDXA] >> 15) & 1; - decoded.security = (scr[NDXA] >> 12) & 7; + decoded.scrversion = (scr[0] >> 4) & 15; + decoded.sdversion = scr[0] & 15; + decoded.erasestate = (scr[0] >> 15) & 1; + decoded.security = (scr[0] >> 12) & 7; #endif decoded.buswidth = priv->buswidth; #endif @@ -967,7 +953,7 @@ struct mmcsd_scr_s decoded; */ #ifdef CONFIG_DEBUG_FS_INFO - decoded.mfgdata = scr[NDXB]; /* Might be byte reversed! */ + decoded.mfgdata = scr[1]; /* Might be byte reversed! */ finfo("SCR:\n"); finfo(" SCR_STRUCTURE: %d SD_VERSION: %d\n", -- GitLab From 10b9a10d2f8e8ff1652c1bf57a9f19c5ce2eb1ee Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 15 Dec 2016 10:08:26 -0600 Subject: [PATCH 699/734] Xtensa ESP32: Fix several build-related issues associated with vector section --- arch/xtensa/src/common/xtensa_int_handlers.S | 25 ++++++++++- arch/xtensa/src/common/xtensa_panic.S | 3 ++ arch/xtensa/src/common/xtensa_user_handler.S | 5 +++ arch/xtensa/src/common/xtensa_vectors.S | 39 ++++++++--------- arch/xtensa/src/esp32/Make.defs | 9 ++-- configs/esp32-core/scripts/esp32_flash.ld | 44 ++++++++++---------- configs/esp32-core/scripts/esp32_iram.ld | 44 ++++++++++---------- 7 files changed, 100 insertions(+), 69 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_int_handlers.S b/arch/xtensa/src/common/xtensa_int_handlers.S index 0cf3c2f129..647223cf07 100644 --- a/arch/xtensa/src/common/xtensa_int_handlers.S +++ b/arch/xtensa/src/common/xtensa_int_handlers.S @@ -63,6 +63,7 @@ #include #include +#include "xtensa.h" #include "xtensa_abi.h" #include "chip_macros.h" #include "xtensa_timer.h" @@ -142,6 +143,13 @@ extract_msb a4, a2 /* a4 = MSB of a2, a2 trashed */ + /* Check for a timer interrupt. + * + * REVISIT: XT_TIMER_INTEN will be only one of the configured timers + * (see xtensa_timer.h). There is no mechanism here to detect other + * timer interrupts. + */ + movi a3, XT_TIMER_INTEN /* a3 = timer interrupt bit */ wsr a4, INTCLEAR /* Clear sw or edge-triggered interrupt */ beq a3, a4, 4f /* If timer interrupt then skip table */ @@ -182,9 +190,13 @@ * We'll be reading the interrupt state again after this call * so no need to preserve any registers except a7 (pointer to * state save area). + * + * REVISIT: Here we explicitly assume that the INTERRUPT XT_TIMER_INTEN + * corresponds to TIMER0. That is probably that case, but not necessarily + * so. */ - movi a2, XTENSA_IRQ_TIMER&level& /* Argument 1: IRQ number */ + movi a2, XTENSA_IRQ_TIMER0 /* Argument 1: Timer0 IRQ number */ mov a3, a12 /* Argument 2: Top of stack = register save area */ #ifdef __XTENSA_CALL0_ABI__ call0 xtensa_irq_dispatch /* Call xtensa_int_decode */ @@ -270,6 +282,7 @@ .section HANDLER_SECTION, "ax" .type _xtensa_level1_handler, @function + .global _xtensa_level1_handler .align 4 _xtensa_level1_handler: @@ -354,6 +367,7 @@ _xtensa_level1_handler: #if XCHAL_EXCM_LEVEL >= 2 .section HANDLER_SECTION, "ax" .type _xtensa_level2_handler, @function + .global _xtensa_level2_handler .align 4 _xtensa_level2_handler: @@ -414,6 +428,7 @@ _xtensa_level2_handler: #if XCHAL_EXCM_LEVEL >= 3 .section HANDLER_SECTION, "ax" .type _xtensa_level3_handler, @function + .global _xtensa_level3_handler .align 4 _xtensa_level3_handler: @@ -474,6 +489,7 @@ _xtensa_level3_handler: #if XCHAL_EXCM_LEVEL >= 4 .section HANDLER_SECTION, "ax" .type _xtensa_level4_handler, @function + .global _xtensa_level4_handler .align 4 _xtensa_level4_handler: @@ -534,6 +550,7 @@ _xtensa_level4_handler: #if XCHAL_EXCM_LEVEL >= 5 .section HANDLER_SECTION, "ax" .type _xtensa_level5_handler, @function + .global _xtensa_level5_handler .align 4 _xtensa_level5_handler: @@ -594,6 +611,7 @@ _xtensa_level5_handler: #if XCHAL_EXCM_LEVEL >= 6 .section HANDLER_SECTION, "ax" .type _xtensa_level6_handler, @function + .global _xtensa_level6_handler .align 4 _xtensa_level6_handler: @@ -690,6 +708,7 @@ _xtensa_level6_handler: #if XCHAL_INT_NLEVELS >=2 && XCHAL_EXCM_LEVEL < 2 && XCHAL_DEBUGLEVEL !=2 .section HANDLER_SECTION, "ax" .type _xtensa_level2_handler, @function + .global _xtensa_level2_handler .align 4 _xtensa_level2_handler: @@ -723,6 +742,7 @@ _xtensa_level2_handler: #if XCHAL_INT_NLEVELS >=3 && XCHAL_EXCM_LEVEL < 3 && XCHAL_DEBUGLEVEL !=3 .section HANDLER_SECTION, "ax" .type _xtensa_level3_handler, @function + .global _xtensa_level3_handler .align 4 _xtensa_level3_handler: @@ -758,6 +778,7 @@ _xtensa_level3_handler: #if XCHAL_INT_NLEVELS >=4 && XCHAL_EXCM_LEVEL < 4 && XCHAL_DEBUGLEVEL !=4 .section HANDLER_SECTION, "ax" .type _xtensa_level4_handler, @function + .global _xtensa_level4_handler .align 4 _xtensa_level4_handler: @@ -793,6 +814,7 @@ _xtensa_level4_handler: #if XCHAL_INT_NLEVELS >=5 && XCHAL_EXCM_LEVEL < 5 && XCHAL_DEBUGLEVEL !=5 .section HANDLER_SECTION, "ax" .type _xtensa_level5_handler, @function + .global _xtensa_level5_handler .align 4 _xtensa_level5_handler: @@ -828,6 +850,7 @@ _xtensa_level5_handler: #if XCHAL_INT_NLEVELS >=6 && XCHAL_EXCM_LEVEL < 6 && XCHAL_DEBUGLEVEL !=6 .section HANDLER_SECTION, "ax" .type _xtensa_level6_handler, @function + .global _xtensa_level6_handler .align 4 _xtensa_level6_handler: diff --git a/arch/xtensa/src/common/xtensa_panic.S b/arch/xtensa/src/common/xtensa_panic.S index e24acc12fa..46036395c6 100644 --- a/arch/xtensa/src/common/xtensa_panic.S +++ b/arch/xtensa/src/common/xtensa_panic.S @@ -59,10 +59,13 @@ ****************************************************************************/ #include + #include #include #include +#include "chip_macros.h" + /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/xtensa/src/common/xtensa_user_handler.S b/arch/xtensa/src/common/xtensa_user_handler.S index fc789ccb5a..9c9c80bc59 100644 --- a/arch/xtensa/src/common/xtensa_user_handler.S +++ b/arch/xtensa/src/common/xtensa_user_handler.S @@ -59,10 +59,13 @@ ****************************************************************************/ #include + #include #include #include +#include "chip_macros.h" + /**************************************************************************** * Assembly Language Macros ****************************************************************************/ @@ -158,6 +161,7 @@ _xtensa_to_coproc_handler: ****************************************************************************/ .type _xtensa_user_handler, @function + .global _xtensa_user_handler .align 4 _xtensa_user_handler: @@ -254,6 +258,7 @@ _xtensa_user_handler: .section HANDLER_SECTION, "ax" .type _xtensa_syscall_handler, @function .align 4 + _xtensa_syscall_handler: /* Allocate stack frame and save A0, A1, and PS */ diff --git a/arch/xtensa/src/common/xtensa_vectors.S b/arch/xtensa/src/common/xtensa_vectors.S index 726824f058..015e778c74 100644 --- a/arch/xtensa/src/common/xtensa_vectors.S +++ b/arch/xtensa/src/common/xtensa_vectors.S @@ -42,6 +42,7 @@ #include #include +#include "xtensa.h" #include "xtensa_abi.h" /**************************************************************************** @@ -226,10 +227,10 @@ _xtensa_nmi_vector: ****************************************************************************/ #if XCHAL_HAVE_DEBUG - .begin literal_prefix .debug_exception_vector - .section .debug_exception_vector.text, "ax" - .global _debug_exception_vector - .align 4 + .begin literal_prefix .debug_exception_vector + .section .debug_exception_vector.text, "ax" + .global _debug_exception_vector + .align 4 _debug_exception_vector: @@ -261,10 +262,10 @@ _debug_exception_vector: ****************************************************************************/ #ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR - .begin literal_prefix .double_exception_vector - .section .double_exception_vector.text, "ax" - .global _double_exception_vector - .align 4 + .begin literal_prefix .double_exception_vector + .section .double_exception_vector.text, "ax" + .global _double_exception_vector + .align 4 _double_exception_vector: @@ -286,7 +287,7 @@ _double_exception_vector: movi a2, XTENSA_DOUBLE_EXCEPTION /* Address of state save on stack */ call0 _xtensa_panic /* Does not return */ - .end literal_prefix + .end literal_prefix #endif /* XCHAL_DOUBLEEXC_VECTOR_VADDR */ @@ -298,10 +299,10 @@ _double_exception_vector: * ****************************************************************************/ - .begin literal_prefix .kernel_exception_vector - .section .kernel_exception_vector.text, "ax" - .global _kernel_exception_vector - .align 4 + .begin literal_prefix .kernel_exception_vector + .section .kernel_exception_vector.text, "ax" + .global _kernel_exception_vector + .align 4 _kernel_exception_vector: @@ -333,15 +334,15 @@ _kernel_exception_vector: * ****************************************************************************/ - .begin literal_prefix .user_exception_vector - .section .user_exception_vector.text, "ax" - .global _user_exception_vector - .type _user_exception_vector, @function - .align 4 + .begin literal_prefix .user_exception_vector + .section .user_exception_vector.text, "ax" + .global _user_exception_vector + .type _user_exception_vector, @function + .align 4 _user_exception_vector: wsr a0, EXCSAVE_1 /* Preserve a0 */ - call0 xtensa_user_handler /* And jump to user exception handler */ + call0 _xtensa_user_handler /* And jump to user exception handler */ .end literal_prefix diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 39a67813c6..c9797d51ab 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -35,14 +35,13 @@ # The start-up, "head", file. May be either a .S or a .c file. -HEAD_ASRC = -HEAD_CSRC = esp32_start.c +HEAD_ASRC = xtensa_vectors.S xtensa_window_vector.S xtensa_windowspill.S +HEAD_ASRC += xtensa_int_handlers.S xtensa_user_handler.S +HEAD_CSRC = esp32_start.c # Common XTENSA files (arch/xtensa/src/common) -CMN_ASRCS = xtensa_context.S xtensa_coproc.S xtensa_cpuint.S -CMN_ASRCS += xtensa_int_handlers.S xtensa_panic.S xtensa_user_handler.S -CMN_ASRCS += xtensa_vectors.S xtensa_windowspill.S +CMN_ASRCS = xtensa_context.S xtensa_coproc.S xtensa_cpuint.S xtensa_panic.S CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c CMN_CSRCS += xtensa_cpenable.c xtensa_createstack.c xtensa_exit.c xtensa_idle.c diff --git a/configs/esp32-core/scripts/esp32_flash.ld b/configs/esp32-core/scripts/esp32_flash.ld index 5a1ffe0562..e11f2f954a 100644 --- a/configs/esp32-core/scripts/esp32_flash.ld +++ b/configs/esp32-core/scripts/esp32_flash.ld @@ -19,25 +19,25 @@ SECTIONS /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ . = 0x0; - KEEP(*(.window_vectors.text)); + KEEP (*(.window_vectors.text)); . = 0x180; - KEEP(*(.xtensa_level2_vector.text)); + KEEP (*(.xtensa_level2_vector.text)); . = 0x1c0; - KEEP(*(.xtensa_level3_vector.text)); + KEEP (*(.xtensa_level3_vector.text)); . = 0x200; - KEEP(*(.xtensa_level4_vector.text)); + KEEP (*(.xtensa_level4_vector.text)); . = 0x240; - KEEP(*(.xtensa_level5_vector.text)); + KEEP (*(.xtensa_level5_vector.text)); . = 0x280; - KEEP(*(.debug_exception_vector.text)); + KEEP (*(.debug_exception_vector.text)); . = 0x2c0; - KEEP(*(.nmi_vector.text)); + KEEP (*(.nmi_vector.text)); . = 0x300; - KEEP(*(.kernel_exception_vector.text)); + KEEP (*(.kernel_exception_vector.text)); . = 0x340; - KEEP(*(.user_exception_vector.text)); + KEEP (*(.user_exception_vector.text)); . = 0x3c0; - KEEP(*(.double_exception_vector.text)); + KEEP (*(.double_exception_vector.text)); . = 0x400; *(.*_vector.literal) @@ -78,7 +78,7 @@ SECTIONS *(.sbss2.*) *(.gnu.linkonce.sb2.*) *(.dynbss) - KEEP(*(.bss)) + KEEP (*(.bss)) *(.bss.*) *(.share.mem) *(.gnu.linkonce.b.*) @@ -96,17 +96,17 @@ SECTIONS /* .data initialized on power-up in ROMed configurations. */ _sdata = ABSOLUTE(.); - KEEP(*(.data)) - KEEP(*(.data.*)) - KEEP(*(.gnu.linkonce.d.*)) - KEEP(*(.data1)) - KEEP(*(.sdata)) - KEEP(*(.sdata.*)) - KEEP(*(.gnu.linkonce.s.*)) - KEEP(*(.sdata2)) - KEEP(*(.sdata2.*)) - KEEP(*(.gnu.linkonce.s2.*)) - KEEP(*(.jcr)) + KEEP (*(.data)) + KEEP (*(.data.*)) + KEEP (*(.gnu.linkonce.d.*)) + KEEP (*(.data1)) + KEEP (*(.sdata)) + KEEP (*(.sdata.*)) + KEEP (*(.gnu.linkonce.s.*)) + KEEP (*(.sdata2)) + KEEP (*(.sdata2.*)) + KEEP (*(.gnu.linkonce.s2.*)) + KEEP (*(.jcr)) *(.dram1 .dram1.*) _edata = ABSOLUTE(.); . = ALIGN(4); diff --git a/configs/esp32-core/scripts/esp32_iram.ld b/configs/esp32-core/scripts/esp32_iram.ld index 62ed31380b..2df0a5355a 100644 --- a/configs/esp32-core/scripts/esp32_iram.ld +++ b/configs/esp32-core/scripts/esp32_iram.ld @@ -19,25 +19,25 @@ SECTIONS /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ . = 0x0; - KEEP(*(.window_vectors.text)); + KEEP (*(.window_vectors.text)); . = 0x180; - KEEP(*(.xtensa_level2_vector.text)); + KEEP (*(.xtensa_level2_vector.text)); . = 0x1c0; - KEEP(*(.xtensa_level3_vector.text)); + KEEP (*(.xtensa_level3_vector.text)); . = 0x200; - KEEP(*(.xtensa_level4_vector.text)); + KEEP (*(.xtensa_level4_vector.text)); . = 0x240; - KEEP(*(.xtensa_level5_vector.text)); + KEEP (*(.xtensa_level5_vector.text)); . = 0x280; - KEEP(*(.debug_exception_vector.text)); + KEEP (*(.debug_exception_vector.text)); . = 0x2c0; - KEEP(*(.nmi_vector.text)); + KEEP (*(.nmi_vector.text)); . = 0x300; - KEEP(*(.kernel_exception_vector.text)); + KEEP (*(.kernel_exception_vector.text)); . = 0x340; - KEEP(*(.user_exception_vector.text)); + KEEP (*(.user_exception_vector.text)); . = 0x3c0; - KEEP(*(.double_exception_vector.text)); + KEEP (*(.double_exception_vector.text)); . = 0x400; *(.*_vector.literal) @@ -89,7 +89,7 @@ SECTIONS *(.sbss2.*) *(.gnu.linkonce.sb2.*) *(.dynbss) - KEEP(*(.bss)) + KEEP (*(.bss)) *(.bss.*) *(.share.mem) *(.gnu.linkonce.b.*) @@ -107,17 +107,17 @@ SECTIONS /* .data initialized on power-up in ROMed configurations. */ _sdata = ABSOLUTE(.); - KEEP(*(.data)) - KEEP(*(.data.*)) - KEEP(*(.gnu.linkonce.d.*)) - KEEP(*(.data1)) - KEEP(*(.sdata)) - KEEP(*(.sdata.*)) - KEEP(*(.gnu.linkonce.s.*)) - KEEP(*(.sdata2)) - KEEP(*(.sdata2.*)) - KEEP(*(.gnu.linkonce.s2.*)) - KEEP(*(.jcr)) + KEEP (*(.data)) + KEEP (*(.data.*)) + KEEP (*(.gnu.linkonce.d.*)) + KEEP (*(.data1)) + KEEP (*(.sdata)) + KEEP (*(.sdata.*)) + KEEP (*(.gnu.linkonce.s.*)) + KEEP (*(.sdata2)) + KEEP (*(.sdata2.*)) + KEEP (*(.gnu.linkonce.s2.*)) + KEEP (*(.jcr)) *(.dram1 .dram1.*) _edata = ABSOLUTE(.); . = ALIGN(4); -- GitLab From ea9e6c48e4b98ba4a38dbd73a99d56ae6a86c19d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 15 Dec 2016 10:43:34 -0600 Subject: [PATCH 700/734] Cosmetic update to comments. --- arch/xtensa/src/common/xtensa_int_handlers.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_int_handlers.S b/arch/xtensa/src/common/xtensa_int_handlers.S index 647223cf07..f20e1568c9 100644 --- a/arch/xtensa/src/common/xtensa_int_handlers.S +++ b/arch/xtensa/src/common/xtensa_int_handlers.S @@ -146,13 +146,13 @@ /* Check for a timer interrupt. * * REVISIT: XT_TIMER_INTEN will be only one of the configured timers - * (see xtensa_timer.h). There is no mechanism here to detect other - * timer interrupts. + * selected as the system periodic timer (see xtensa_timer.h). There + * is no mechanism here to detect other timer interrupts. */ movi a3, XT_TIMER_INTEN /* a3 = timer interrupt bit */ wsr a4, INTCLEAR /* Clear sw or edge-triggered interrupt */ - beq a3, a4, 4f /* If timer interrupt then skip table */ + beq a3, a4, 4f /* If timer interrupt then skip decode */ /* Call xtensa_int_decode with, passing that address of the register save * area as a parameter (A2). @@ -171,7 +171,7 @@ * register save area. This may or may not reside on a stack. */ - beq a2, a12, 3f /* If timer interrupt then skip table */ + beq a2, a12, 3f /* If timer interrupt then keep stack */ /* Switch stacks */ -- GitLab From c56268b41614c0e4f286938fb793f66860eba65d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 15 Dec 2016 11:06:41 -0600 Subject: [PATCH 701/734] Fix missing CALL0 ABI condition. --- arch/xtensa/src/common/xtensa_panic.S | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/xtensa/src/common/xtensa_panic.S b/arch/xtensa/src/common/xtensa_panic.S index 46036395c6..9e300190a1 100644 --- a/arch/xtensa/src/common/xtensa_panic.S +++ b/arch/xtensa/src/common/xtensa_panic.S @@ -114,7 +114,12 @@ _xtensa_panic: /* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */ +#ifdef __XTENSA_CALL0_ABI__ + movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM +#else movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE +#endif + wsr a0, PS /* Call C panic handler: Arg1 (A2) = Exception code; Arg 2 (A3) = start @@ -122,6 +127,7 @@ _xtensa_panic: */ mov a3, sp + #ifdef __XTENSA_CALL0_ABI__ call0 xtensa_panic /* Call xtensa_panic. Should not return */ #else -- GitLab From aa5a8b0ca2c04e748f9aa3f9b511429f23187b2b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 15 Dec 2016 14:02:19 -0600 Subject: [PATCH 702/734] Xtensa: Make sure that all C callable assembly functions includes ENTRY prologue and RET epilogue. --- arch/xtensa/src/common/xtensa_context.S | 4 +++- arch/xtensa/src/esp32/esp32_cpuhead.S | 5 +++++ arch/xtensa/src/esp32/esp32_irq.c | 2 +- 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index 8d9462e5a6..eb4324f901 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -227,6 +227,7 @@ _xtensa_context_save: .align 4 xtensa_context_save: + ENTRY(16) /* Set up for call to _xtensa_context_save() */ @@ -248,7 +249,7 @@ xtensa_context_save: l32i a0, a2, (4 * REG_A0) /* Recover return addess */ movi a2, 0 /* Return zero */ - ret + RET(16) .size xtensa_context_save, . - xtensa_context_save @@ -372,6 +373,7 @@ _xtensa_context_restore: .align 4 xtensa_context_restore: + ENTRY(16) /* REVISIT */ /* Restore the processor state */ diff --git a/arch/xtensa/src/esp32/esp32_cpuhead.S b/arch/xtensa/src/esp32/esp32_cpuhead.S index 40cbf2e85d..a33a8a05ac 100644 --- a/arch/xtensa/src/esp32/esp32_cpuhead.S +++ b/arch/xtensa/src/esp32/esp32_cpuhead.S @@ -139,7 +139,12 @@ __cpu1_start: /* Finish initialization in C */ movi a2, 1 /* Argument 1: CPU ID */ + +#ifdef __XTENSA_CALL0_ABI__ call0 xtensa_start_handler +#else + call4 xtensa_start_handler +#endif /* xtensa_start_handler() does not return */ diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c index 4c1d15008f..7e84758813 100644 --- a/arch/xtensa/src/esp32/esp32_irq.c +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -187,7 +187,7 @@ void xtensa_irq_initialize(void) #endif #ifndef CONFIG_SUPPRESS_INTERRUPTS - /* And finally, enable interrupts */ + /* And finally, enable interrupts. Also clears PS.EXCM */ up_irq_enable(); #endif -- GitLab From 41cf32a20eb62214d7551b3dbc21c1940b0059b0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 16 Dec 2016 09:20:36 -0600 Subject: [PATCH 703/734] Fix windowspill register handling + Use r6, not r2 when passing paramters with call4 --- arch/xtensa/include/irq.h | 17 ++++++----- arch/xtensa/src/common/xtensa_context.S | 36 ++++++++--------------- arch/xtensa/src/common/xtensa_dumpstate.c | 5 ++-- 3 files changed, 24 insertions(+), 34 deletions(-) diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index 0e8f7c33b0..aee6625dde 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -108,20 +108,21 @@ # define REG_LBEG (_REG_LOOPS_START + 0) # define REG_LEND (_REG_LOOPS_START + 1) # define REG_LCOUNT (_REG_LOOPS_START + 2) -# define _REG_CALL0_START (_REG_LOOPS_START + 3) +# define _REG_WINDOW_TMPS (_REG_LOOPS_START + 3) #else -# define _REG_CALL0_START _REG_LOOPS_START +# define _REG_WINDOW_TMPS _REG_LOOPS_START #endif #ifndef __XTENSA_CALL0_ABI__ - /* Temporary space for saving stuff during window spill */ + /* Temporary space for saving stuff during window spill. + * REVISIT: I don't think that we need so many temporaries. + */ -# define REG_TMP0 (_REG_CALL0_START + 0) -# define REG_TMP1 (_REG_CALL0_START + 1) -# define REG_TMP2 (_REG_CALL0_START + 2) -# define _REG_OVLY_START (_REG_CALL0_START + 3) +# define REG_TMP0 (_REG_WINDOW_TMPS + 0) +# define REG_TMP1 (_REG_WINDOW_TMPS + 1) +# define _REG_OVLY_START (_REG_WINDOW_TMPS + 2) #else -# define _REG_OVLY_START _REG_CALL0_START +# define _REG_OVLY_START _REG_WINDOW_TMPS #endif #ifdef CONFIG_XTENSA_USE_OVLY diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index eb4324f901..c3e7030b02 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -146,22 +146,13 @@ _xtensa_context_save: s32i a3, a2, (4 * REG_LCOUNT) #endif -#ifndef __XTENSA_CALL0_ABI__ - mov a9, a0 /* Preserve ret addr */ -#endif - #ifndef __XTENSA_CALL0_ABI__ /* To spill the reg windows, temp. need pre-interrupt stack ptr and - * a4-15. Need to save a9,12,13 temporarily (in frame temps) and - * recover originals. Interrupts need to be disabled below - * XCHAL_EXCM_LEVEL and window overflow and underflow exceptions - * disabled (assured by PS.EXCM == 1). + * a4-15. Interrupts need to be disabled below XCHAL_EXCM_LEVEL and + * window overflow and underflow exceptions disabled (assured by + * PS.EXCM == 1). */ - s32i a12, a2, (4 * REG_TMP0) /* Temp. save stuff in stack frame */ - s32i a13, a2, (4 * REG_TMP1) - s32i a9, a2, (4 * REG_TMP2) - #ifdef CONFIG_XTENSA_USE_OVLY /* Save the overlay state if we are supporting overlays. Since we just * saved three registers, we can conveniently use them here. Note that @@ -171,17 +162,16 @@ _xtensa_context_save: #error Overly support is not implemented #endif - l32i a12, a2, (4 * REG_A12) /* Recover original a9,12,13 */ - l32i a13, a2, (4 * REG_A13) - l32i a9, a2, (4 * REG_A9) - -#warning REVISIT: The following is probably not correct due to changes in registers - addi sp, sp, (4 * XCPTCONTEXT_SIZE) /* Restore the interruptee's SP */ - call0 _xtensa_window_spill /* Preserves only a4,5,8,9,12,13 */ - addi sp, sp, -(4 * XCPTCONTEXT_SIZE) - l32i a12, sp, (4 * REG_TMP0) /* Recover stuff from stack frame */ - l32i a13, sp, (4 * REG_TMP1) - l32i a9, sp, (4 * REG_TMP2) + s32i a0, a2, (4 * REG_TMP0) /* Save return address */ + s32i sp, a2, (4 * REG_TMP1) /* Save current stack pointer */ + wsr a2, EXCSAVE_1 /* Preserve register save area */ + + l32i sp, a2, (4 * REG_A1) /* Restore the interruptee's SP */ + call0 _xtensa_window_spill /* Preserves only a4-a5, a8-a9, a12-a13 */ + + rsr a2, EXCSAVE_1 /* Save interruptee's a0 */ + l32i a0, a2, (4 * REG_TMP0) /* Save return address */ + l32i sp, a2, (4 * REG_TMP1) /* Save current stack pointer */ #endif ret diff --git a/arch/xtensa/src/common/xtensa_dumpstate.c b/arch/xtensa/src/common/xtensa_dumpstate.c index 975993af62..4a9eaa3b0d 100644 --- a/arch/xtensa/src/common/xtensa_dumpstate.c +++ b/arch/xtensa/src/common/xtensa_dumpstate.c @@ -130,9 +130,8 @@ static inline void xtensa_registerdump(void) (unsigned long)regs[REG_LCOUNT]); #endif #ifndef __XTENSA_CALL0_ABI__ - _alert(" TMP0: %08lx TMP1: %08lx TMP2: %08lx\n", - (unsigned long)regs[REG_TMP0], (unsigned long)regs[REG_TMP1], - (unsigned long)regs[REG_TMP2]); + _alert(" TMP0: %08lx TMP1: %08lx\n", + (unsigned long)regs[REG_TMP0], (unsigned long)regs[REG_TMP1]); #endif } } -- GitLab From f1a5b91cd897a4f8a9628ec3c3df859393ca1e1b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 16 Dec 2016 09:21:44 -0600 Subject: [PATCH 704/734] Use r6, not r2 when passing paramters with call4 --- arch/xtensa/src/common/xtensa_int_handlers.S | 9 ++++++--- arch/xtensa/src/common/xtensa_panic.S | 10 ++++++++-- arch/xtensa/src/common/xtensa_user_handler.S | 14 +++++++++----- arch/xtensa/src/esp32/esp32_cpuhead.S | 4 ++-- 4 files changed, 25 insertions(+), 12 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_int_handlers.S b/arch/xtensa/src/common/xtensa_int_handlers.S index f20e1568c9..bf83f0cb09 100644 --- a/arch/xtensa/src/common/xtensa_int_handlers.S +++ b/arch/xtensa/src/common/xtensa_int_handlers.S @@ -158,10 +158,11 @@ * area as a parameter (A2). */ - mov a2, a12 /* Argument: Top of stack = register save area */ #ifdef __XTENSA_CALL0_ABI__ + mov a2, a12 /* Argument: Top of stack = register save area */ call0 xtensa_int_decode /* Call xtensa_int_decode */ #else + mov a6, a12 /* Argument: Top of stack = register save area */ call4 xtensa_int_decode /* Call xtensa_int_decode */ #endif @@ -193,14 +194,16 @@ * * REVISIT: Here we explicitly assume that the INTERRUPT XT_TIMER_INTEN * corresponds to TIMER0. That is probably that case, but not necessarily - * so. + * so. xtensa_timer.h should probably select the IRQ number as well. */ +#ifdef __XTENSA_CALL0_ABI__ movi a2, XTENSA_IRQ_TIMER0 /* Argument 1: Timer0 IRQ number */ mov a3, a12 /* Argument 2: Top of stack = register save area */ -#ifdef __XTENSA_CALL0_ABI__ call0 xtensa_irq_dispatch /* Call xtensa_int_decode */ #else + movi a6, XTENSA_IRQ_TIMER0 /* Argument 1: Timer0 IRQ number */ + mov a7, a12 /* Argument 2: Top of stack = register save area */ call4 xtensa_irq_dispatch /* Call xtensa_int_decode */ #endif diff --git a/arch/xtensa/src/common/xtensa_panic.S b/arch/xtensa/src/common/xtensa_panic.S index 9e300190a1..c526eab6d4 100644 --- a/arch/xtensa/src/common/xtensa_panic.S +++ b/arch/xtensa/src/common/xtensa_panic.S @@ -98,6 +98,10 @@ .align 4 _xtensa_panic: + /* Save the exception code */ + + wsr a2, EXCSAVE_1 + /* Save rest of interrupt context (A2=address of state save area on * stack. */ @@ -126,11 +130,13 @@ _xtensa_panic: * of the register save area. */ - mov a3, sp - #ifdef __XTENSA_CALL0_ABI__ + rsr a2, EXCSAVE_1 + mov a3, sp call0 xtensa_panic /* Call xtensa_panic. Should not return */ #else + rsr a6, EXCSAVE_1 + mov a7, sp call4 xtensa_panic /* Call xtensa_panic. Should not return */ #endif diff --git a/arch/xtensa/src/common/xtensa_user_handler.S b/arch/xtensa/src/common/xtensa_user_handler.S index 9c9c80bc59..924cb2554a 100644 --- a/arch/xtensa/src/common/xtensa_user_handler.S +++ b/arch/xtensa/src/common/xtensa_user_handler.S @@ -229,12 +229,13 @@ _xtensa_user_handler: * beginning of the register save area. */ +#ifdef __XTENSA_CALL0_ABI__ rsr a2, EXCCAUSE /* Argument 1 (a2) = EXCCAUSE */ mov a3, sp /* Argument 2 (a2) = pointer to register save area */ - -#ifdef __XTENSA_CALL0_ABI__ calx0 xtensa_user /* Call xtensa_user */ #else + rsr a6, EXCCAUSE /* Argument 1 (a2) = EXCCAUSE */ + mov a7, sp /* Argument 2 (a2) = pointer to register save area */ call4 xtensa_user /* Call xtensa_user */ #endif @@ -333,11 +334,13 @@ _xtensa_syscall_handler: */ mov a12, sp /* a12 = address of register save area */ +#ifdef __XTENSA_CALL0_ABI__ movi a2, XTENSA_IRQ_SYSCALL /* Argument 1: IRQ number */ mov a3, a12 /* Argument 2: Top of stack = register save area */ -#ifdef __XTENSA_CALL0_ABI__ call0 xtensa_irq_dispatch /* Call xtensa_int_decode */ #else + movi a6, XTENSA_IRQ_SYSCALL /* Argument 1: IRQ number */ + mov a7, a12 /* Argument 2: Top of stack = register save area */ call4 xtensa_irq_dispatch /* Call xtensa_int_decode */ #endif @@ -468,12 +471,13 @@ _xtensa_coproc_handler: * beginning of the register save area. */ +#ifdef __XTENSA_CALL0_ABI__ rsr a2, EXCCAUSE /* Argument 1 (a2) = EXCCAUSE */ mov a3, sp /* Argument 2 (a2) = pointer to register save area */ - -#ifdef __XTENSA_CALL0_ABI__ calx0 xtensa_user /* Call xtensa_user */ #else + rsr a6, EXCCAUSE /* Argument 1 (a2) = EXCCAUSE */ + mov a7, sp /* Argument 2 (a2) = pointer to register save area */ call4 xtensa_user /* Call xtensa_user */ #endif diff --git a/arch/xtensa/src/esp32/esp32_cpuhead.S b/arch/xtensa/src/esp32/esp32_cpuhead.S index a33a8a05ac..03132fd8b1 100644 --- a/arch/xtensa/src/esp32/esp32_cpuhead.S +++ b/arch/xtensa/src/esp32/esp32_cpuhead.S @@ -138,11 +138,11 @@ __cpu1_start: /* Finish initialization in C */ - movi a2, 1 /* Argument 1: CPU ID */ - #ifdef __XTENSA_CALL0_ABI__ + movi a2, 1 /* Argument 1: CPU ID */ call0 xtensa_start_handler #else + movi a6, 1 /* Argument 1: CPU ID */ call4 xtensa_start_handler #endif -- GitLab From 935e49f5bbb0f77897550e9e8e040a31c12d083f Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 16 Dec 2016 09:38:08 -0600 Subject: [PATCH 705/734] Update some comments --- arch/xtensa/src/common/xtensa_abi.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/xtensa/src/common/xtensa_abi.h b/arch/xtensa/src/common/xtensa_abi.h index 63e53f26c5..8c740d49db 100644 --- a/arch/xtensa/src/common/xtensa_abi.h +++ b/arch/xtensa/src/common/xtensa_abi.h @@ -58,6 +58,27 @@ * CALL8, or CALL12 instructions to save 4, 8, or 12 live registers. Calls * to routines that use a2..a7 for parameters may use only CALL8 or CALL12. * + * Arguments are passed in both registers and memory. The first six incoming + * arguments are stored in registers a2 through a7, and additional arguments + * are stored on the stack starting at the current stack pointer a1. Because + * Xtensa uses register windows that rotate during a function call, outgoing + * arguments that will become the incoming arguments must be stored to + * different register numbers. Depending on the call instruction and, thus, + * the rotation of the register window, the arguments are passed starting + * starting with register a(2+N), where N is the size of the window rotation. + * Therefore, the first argument in case of a call4 instruction is placed into + * a6, and for a call8 instruction into a10. Large arguments (8-bytes) are + * always passed in an even/odd register pair even if that means to omit a + * register for alignment. The return values are stored in a2 through a7. + * + * return addr stack ptr arg0, arg1, arg2, arg3, arg4, arg5 + * ----------- --------- ---------------------------------- + * a0 a1 a2, a3, a4, a5, a6, a7 + * + * call4 a4 a5 a6, a7, a8, a9, a10, a11 + * call8 a8 a9 a10, a11, a12, a13, a14, a15 + * call12 a12 a13 a14, a15 --- --- --- --- + * * The stack pointer SP should only be modified by ENTRY and MOVSP * instructions (except for initialization and restoration). If some other * instruction modifies SP, any values in the register-spill area will not -- GitLab From 6337fadd8cbe6079fabb802ece8d03832b94869d Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 16 Dec 2016 10:49:42 -0600 Subject: [PATCH 706/734] Missing escape character on CR of CR-LF expansion. --- arch/xtensa/src/common/xtensa_abi.h | 12 ++++++------ arch/xtensa/src/esp32/esp32_serial.c | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_abi.h b/arch/xtensa/src/common/xtensa_abi.h index 8c740d49db..db5ab5d552 100644 --- a/arch/xtensa/src/common/xtensa_abi.h +++ b/arch/xtensa/src/common/xtensa_abi.h @@ -71,13 +71,13 @@ * always passed in an even/odd register pair even if that means to omit a * register for alignment. The return values are stored in a2 through a7. * - * return addr stack ptr arg0, arg1, arg2, arg3, arg4, arg5 - * ----------- --------- ---------------------------------- - * a0 a1 a2, a3, a4, a5, a6, a7 + * return addr stack ptr arg0, arg1, arg2, arg3, arg4, arg5 + * ----------- --------- ---------------------------------- + * a0 a1 a2, a3, a4, a5, a6, a7 * - * call4 a4 a5 a6, a7, a8, a9, a10, a11 - * call8 a8 a9 a10, a11, a12, a13, a14, a15 - * call12 a12 a13 a14, a15 --- --- --- --- + * call4 a4 a5 a6, a7, a8, a9, a10, a11 + * call8 a8 a9 a10, a11, a12, a13, a14, a15 + * call12 a12 a13 a14, a15 --- --- --- --- * * The stack pointer SP should only be modified by ENTRY and MOVSP * instructions (except for initialization and restoration). If some other diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c index 36c66dcc09..415dd102bb 100644 --- a/arch/xtensa/src/esp32/esp32_serial.c +++ b/arch/xtensa/src/esp32/esp32_serial.c @@ -1268,7 +1268,7 @@ int up_putc(int ch) /* Add CR */ while(!esp32_txready(&CONSOLE_DEV)); - esp32_send(&CONSOLE_DEV, 'r'); + esp32_send(&CONSOLE_DEV, '\r'); } while(!esp32_txready(&CONSOLE_DEV)); -- GitLab From 34a994b0f60ac2a2e77bf28f9a3c93ded07c1944 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 16 Dec 2016 13:21:01 -0600 Subject: [PATCH 707/734] Correct a logic problem the prevented dumping the IDLE thread's stack on an assertion --- arch/xtensa/src/common/xtensa_dumpstate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/xtensa/src/common/xtensa_dumpstate.c b/arch/xtensa/src/common/xtensa_dumpstate.c index 4a9eaa3b0d..9e0af50e81 100644 --- a/arch/xtensa/src/common/xtensa_dumpstate.c +++ b/arch/xtensa/src/common/xtensa_dumpstate.c @@ -171,7 +171,7 @@ void xtensa_dumpstate(void) ustacksize = CONFIG_IDLETHREAD_STACKSIZE; #else ustackbase = sp + 128; - ustacksize = 128; + ustacksize = 256; #endif } else -- GitLab From cd3d414ba2d9dfc620cca913d56826b1b0796285 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 16 Dec 2016 13:37:28 -0600 Subject: [PATCH 708/734] Xtensa: Fix some missing SMP logic --- arch/xtensa/src/esp32/esp32_cpuint.c | 41 ++++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 5 deletions(-) diff --git a/arch/xtensa/src/esp32/esp32_cpuint.c b/arch/xtensa/src/esp32/esp32_cpuint.c index 2324e7fe3c..7e003d1676 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.c +++ b/arch/xtensa/src/esp32/esp32_cpuint.c @@ -169,7 +169,13 @@ static uint32_t g_intenable[1]; * devices. */ -static uint32_t g_free_cpuints = EPS32_CPUINT_PERIPHSET; +static uint32_t g_cpu0_freeints = EPS32_CPUINT_PERIPHSET; + +#ifdef CONFIG_SMP + +static uint32_t g_cpu1_freeints = EPS32_CPUINT_PERIPHSET; + +#endif /* Bitsets for each interrupt priority 1-5 */ @@ -209,6 +215,7 @@ static const uint32_t g_priority[5] = int esp32_alloc_cpuint(uint32_t intmask) { irqstate_t flags; + uint32_t *freeints; uint32_t bitmask; uint32_t intset; int cpuint; @@ -220,7 +227,18 @@ int esp32_alloc_cpuint(uint32_t intmask) flags = enter_critical_section(); - intset = g_free_cpuints & intmask; +#ifdef CONFIG_SMP + if (this_cpu() != 0) + { + freeints = &g_cpu1_freeints; + } + else +#endif + { + freeints = &g_cpu0_freeints; + } + + intset = *freeints & intmask; if (intset != 0) { /* Skip over initial unavailable CPU interrupts quickly in groups @@ -246,7 +264,7 @@ int esp32_alloc_cpuint(uint32_t intmask) { /* Got it! */ - g_free_cpuints &= ~bitmask; + *freeints &= ~bitmask; ret = cpuint; break; } @@ -390,6 +408,7 @@ int esp32_alloc_edgeint(int priority) void esp32_free_cpuint(int cpuint) { irqstate_t flags; + uint32_t *freeints; uint32_t bitmask; DEBUGASSERT(cpuint >= 0 && cpuint < ESP32_CPUINT_NEDGEPERIPHS); @@ -398,8 +417,20 @@ void esp32_free_cpuint(int cpuint) bitmask = (1ul << cpuint); flags = enter_critical_section(); - DEBUGASSERT((g_free_cpuints & bitmask) == 0); - g_free_cpuints |= bitmask; + +#ifdef CONFIG_SMP + if (this_cpu() != 0) + { + freeints = &g_cpu1_freeints; + } + else +#endif + { + freeints = &g_cpu0_freeints; + } + + DEBUGASSERT((*freeints & bitmask) == 0); + *freeints |= bitmask; leave_critical_section(flags); } -- GitLab From d4ad5f04d3d33a54827eb653d5d7fde016e85bc0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 16 Dec 2016 14:13:09 -0600 Subject: [PATCH 709/734] Xtensa ESP32: Minor rearchitecting of how CPU interrupts are enabled. MOre to come. --- arch/xtensa/src/esp32/esp32_cpuint.c | 82 ++++++++++++++++++++++++-- arch/xtensa/src/esp32/esp32_cpuint.h | 30 ++++++++-- arch/xtensa/src/esp32/esp32_cpustart.c | 26 +------- arch/xtensa/src/esp32/esp32_irq.c | 27 +-------- arch/xtensa/src/esp32/esp32_serial.c | 2 +- 5 files changed, 109 insertions(+), 58 deletions(-) diff --git a/arch/xtensa/src/esp32/esp32_cpuint.c b/arch/xtensa/src/esp32/esp32_cpuint.c index 7e003d1676..84a1f9abd9 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.c +++ b/arch/xtensa/src/esp32/esp32_cpuint.c @@ -192,6 +192,20 @@ static const uint32_t g_priority[5] = * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: xtensa_disable_all + ****************************************************************************/ + +static inline void xtensa_disable_all(void) +{ + __asm__ __volatile__ + ( + "movi a2, 0\n" + "xsr a2, INTENABLE\n" + : : : "a2" + ); +} + /**************************************************************************** * Name: esp32_alloc_cpuint * @@ -279,6 +293,61 @@ int esp32_alloc_cpuint(uint32_t intmask) * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: esp32_cpuint_initialize + * + * Description: + * Initialize CPU interrupts + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failre. + * + ****************************************************************************/ + +int esp32_cpuint_initialize(void) +{ + uintptr_t regaddr; +#ifdef CONFIG_SMP + int cpu; +#endif + int i; + +#ifdef CONFIG_SMP + /* Which CPU are we initializing */ + + cpu = up_cpu_index(); + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); +#endif + + /* Disable all CPU interrupts on this CPU */ + + xtensa_disable_all(); + + /* Detach all peripheral sources PRO CPU interrupts */ + + for (i = 0; i < ESP32_NPERIPHERALS; i++) + { +#ifdef CONFIG_SMP + if (cpu != 0) + { + regaddr = DPORT_APP_MAP_REGADDR(i); + } + else +#endif + { + regaddr = DPORT_PRO_MAP_REGADDR(i); + } + + putreg32(NO_CPUINT, regaddr); + } + + return OK; +} + /**************************************************************************** * Name: up_disable_irq * @@ -442,8 +511,10 @@ void esp32_free_cpuint(int cpuint) * * Input Parameters: * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * periphid - The peripheral number from ira.h to be assigned. + * periphid - The peripheral number from ira.h to be assigned to + * a CPU interrupt. * cpuint - The CPU interrupt to receive the peripheral interrupt + * assignment. * * Returned Value: * None @@ -479,15 +550,18 @@ void esp32_attach_peripheral(int cpu, int periphid, int cpuint) * Detach a peripheral interupt from a CPU interrupt. * * Input Parameters: - * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * periphid - The peripheral number from ira.h to be assigned. + * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU + * periphid - The peripheral number from irq.h to be detached from the + * CPU interrupt. + * cpuint - The CPU interrupt from which the peripheral interrupt will + * be detached. * * Returned Value: * None * ****************************************************************************/ -void esp32_detach_peripheral(int cpu, int periphid) +void esp32_detach_peripheral(int cpu, int periphid, int cpuint) { uintptr_t regaddr; diff --git a/arch/xtensa/src/esp32/esp32_cpuint.h b/arch/xtensa/src/esp32/esp32_cpuint.h index a3b599cf54..eab06bf197 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.h +++ b/arch/xtensa/src/esp32/esp32_cpuint.h @@ -46,6 +46,23 @@ * Public Function Prototypes ****************************************************************************/ +/**************************************************************************** + * Name: esp32_cpuint_initialize + * + * Description: + * Initialize CPU interrupts + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failre. + * + ****************************************************************************/ + +int esp32_cpuint_initialize(void); + /**************************************************************************** * Name: esp32_alloc_levelint * @@ -108,8 +125,10 @@ void esp32_free_cpuint(int cpuint); * * Input Parameters: * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * periphid - The peripheral number from ira.h to be attached. + * periphid - The peripheral number from ira.h to be assigned to + * a CPU interrupt. * cpuint - The CPU interrupt to receive the peripheral interrupt + * assignment. * * Returned Value: * None @@ -125,14 +144,17 @@ void esp32_attach_peripheral(int cpu, int periphid, int cpuint); * Detach a peripheral interupt from a CPU interrupt. * * Input Parameters: - * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * periphid - The peripheral number from ira.h to be detached. + * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU + * periphid - The peripheral number from irq.h to be detached from the + * CPU interrupt. + * cpuint - The CPU interrupt from which the peripheral interrupt will + * be detached. * * Returned Value: * None * ****************************************************************************/ -void esp32_detach_peripheral(int cpu, int periphid); +void esp32_detach_peripheral(int cpu, int periphid, int cpuint); #endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_CPUINT_H */ diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c index 90998f107c..fbed36350b 100644 --- a/arch/xtensa/src/esp32/esp32_cpustart.c +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -88,20 +88,6 @@ static inline void xtensa_registerdump(FAR struct tcb_s *tcb) # define xtensa_registerdump(tcb) #endif -/**************************************************************************** - * Name: xtensa_disable_all - ****************************************************************************/ - -static inline void xtensa_disable_all(void) -{ - __asm__ __volatile__ - ( - "movi a2, 0\n" - "xsr a2, INTENABLE\n" - : : : "a2" - ); -} - /**************************************************************************** * Name: xtensa_attach_fromcpu0_interrupt ****************************************************************************/ @@ -154,7 +140,6 @@ static inline void xtensa_attach_fromcpu0_interrupt(void) int xtensa_start_handler(int irq, FAR void *context) { FAR struct tcb_s *tcb = this_task(); - int i; sinfo("CPU%d Started\n", up_cpu_index()); @@ -181,9 +166,9 @@ int xtensa_start_handler(int irq, FAR void *context) esp32_region_protection(); - /* Disable all PRO CPU interrupts */ + /* Initialize CPU interrupts */ - xtensa_disable_all(); + (void)esp32_cpuint_initialize(); /* Attach and emable internal interrupts */ @@ -193,13 +178,6 @@ int xtensa_start_handler(int irq, FAR void *context) xtensa_attach_fromcpu0_interrupt(); #endif - /* Detach all peripheral sources APP CPU interrupts */ - - for (i = 0; i < ESP32_NPERIPHERALS; i++) - { - esp32_detach_peripheral(1, i);; - } - #if 0 /* Does it make since to have co-processors enabled on the IDLE thread? */ #if XTENSA_CP_ALLSET != 0 /* Set initial co-processor state */ diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c index 7e84758813..351e50b568 100644 --- a/arch/xtensa/src/esp32/esp32_irq.c +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -98,20 +98,6 @@ static void esp32_irq_dump(const char *msg, int irq) # define esp32_irq_dump(msg, irq) #endif -/**************************************************************************** - * Name: xtensa_disable_all - ****************************************************************************/ - -static inline void xtensa_disable_all(void) -{ - __asm__ __volatile__ - ( - "movi a2, 0\n" - "xsr a2, INTENABLE\n" - : : : "a2" - ); -} - /**************************************************************************** * Name: xtensa_attach_fromcpu1_interrupt ****************************************************************************/ @@ -151,18 +137,9 @@ static inline void xtensa_attach_fromcpu1_interrupt(void) void xtensa_irq_initialize(void) { - int i; - - /* Disable all PRO CPU interrupts */ - - xtensa_disable_all(); - - /* Detach all peripheral sources PRO CPU interrupts */ + /* Initialize CPU interrupts */ - for (i = 0; i < ESP32_NPERIPHERALS; i++) - { - esp32_detach_peripheral(0, i); - } + (void)esp32_cpuint_initialize(); #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 /* Colorize the interrupt stack for debug purposes */ diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c index 415dd102bb..8d1069cb03 100644 --- a/arch/xtensa/src/esp32/esp32_serial.c +++ b/arch/xtensa/src/esp32/esp32_serial.c @@ -716,7 +716,7 @@ static void esp32_detach(struct uart_dev_s *dev) cpu = 0; #endif - esp32_detach_peripheral(cpu, priv->config->periph); + esp32_detach_peripheral(cpu, priv->config->periph, priv->cpuint); /* And release the CPU interrupt */ -- GitLab From cdd8dc72a5cdfae4faba63e7059f8e51ee261749 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 16 Dec 2016 15:36:52 -0600 Subject: [PATCH 710/734] Xtensa ESP32: Basically a redesign of the interrupt dispatch logic. --- arch/xtensa/include/esp32/irq.h | 3 +- arch/xtensa/src/common/xtensa_int_handlers.S | 87 +++++---------- arch/xtensa/src/esp32/esp32_cpuint.c | 64 +++++++++-- arch/xtensa/src/esp32/esp32_cpuint.h | 19 ++++ arch/xtensa/src/esp32/esp32_intdecode.c | 111 +++++++++---------- 5 files changed, 160 insertions(+), 124 deletions(-) diff --git a/arch/xtensa/include/esp32/irq.h b/arch/xtensa/include/esp32/irq.h index a3cbab72c1..6c0373856d 100644 --- a/arch/xtensa/include/esp32/irq.h +++ b/arch/xtensa/include/esp32/irq.h @@ -390,7 +390,8 @@ #define ESP32_CPUINT_NINTERNAL 6 -#define ESP32_CPUINT_MAX 31 +#define ESP32_NCPUINTS 32 +#define ESP32_CPUINT_MAX (ESP32_NCPUINTS - 1) #define EPS32_CPUINT_PERIPHSET 0xdffe773f #define EPS32_CPUINT_INTERNALSET 0x200188c0 diff --git a/arch/xtensa/src/common/xtensa_int_handlers.S b/arch/xtensa/src/common/xtensa_int_handlers.S index bf83f0cb09..91c673b07e 100644 --- a/arch/xtensa/src/common/xtensa_int_handlers.S +++ b/arch/xtensa/src/common/xtensa_int_handlers.S @@ -126,45 +126,25 @@ * a consequence of context switching. */ - mov a12, sp /* a12 = address of save area */ - -._xtensa_dispatch_level&level&: + mov a12, sp /* Address of save area */ +#ifdef __XTENSA_CALL0_ABI__ /* Get mask of pending, enabled interrupts at this level into a2. */ rsr a2, INTENABLE rsr a3, INTERRUPT movi a4, \mask and a2, a2, a3 - and a2, a2, a4 - beqz a2, 5f /* Nothing to do */ - - /* If multiple bits are set then MSB has highest priority. */ - - extract_msb a4, a2 /* a4 = MSB of a2, a2 trashed */ - - /* Check for a timer interrupt. - * - * REVISIT: XT_TIMER_INTEN will be only one of the configured timers - * selected as the system periodic timer (see xtensa_timer.h). There - * is no mechanism here to detect other timer interrupts. - */ - - movi a3, XT_TIMER_INTEN /* a3 = timer interrupt bit */ - wsr a4, INTCLEAR /* Clear sw or edge-triggered interrupt */ - beq a3, a4, 4f /* If timer interrupt then skip decode */ + and a2, a2, a4 /* a2 = Set of pending, enabled interrupts for this level */ + beqz a2, 3f /* Nothing to do */ /* Call xtensa_int_decode with, passing that address of the register save * area as a parameter (A2). */ -#ifdef __XTENSA_CALL0_ABI__ - mov a2, a12 /* Argument: Top of stack = register save area */ + /* Argument 1: Set of CPU interrupt to dispatch */ + mov a3, sp /* Argument 2: Top of stack = register save area */ call0 xtensa_int_decode /* Call xtensa_int_decode */ -#else - mov a6, a12 /* Argument: Top of stack = register save area */ - call4 xtensa_int_decode /* Call xtensa_int_decode */ -#endif /* On return from xtensa_int_decode, a2 will contain the address of the new * register save area. Usually this would be the same as the current SP. @@ -172,7 +152,7 @@ * register save area. This may or may not reside on a stack. */ - beq a2, a12, 3f /* If timer interrupt then keep stack */ + beq a2, sp, 3f /* If no context switch then keep stack */ /* Switch stacks */ @@ -180,53 +160,42 @@ l32i a2, a12, (4 * REG_A1) /* Retrieve stack ptr and replace */ addi sp, a2, -(4 * XCPTCONTEXT_SIZE) -3: - j ._xtensa_dispatch_level&level& /* Check for more interrupts */ - -4: +#else + /* Get mask of pending, enabled interrupts at this level into a2. */ - .ifeq XT_TIMER_INTPRI - \level + rsr a6, INTENABLE + rsr a2, INTERRUPT + movi a3, \mask + and a6, a6, a2 + and a6, a6, a3 /* a6 = Set of pending, enabled interrupts for this level */ + beqz a6, 3f /* Nothing to do */ - /* Interrupt handler for the NuttX system timer if at this level. - * We'll be reading the interrupt state again after this call - * so no need to preserve any registers except a7 (pointer to - * state save area). - * - * REVISIT: Here we explicitly assume that the INTERRUPT XT_TIMER_INTEN - * corresponds to TIMER0. That is probably that case, but not necessarily - * so. xtensa_timer.h should probably select the IRQ number as well. + /* Call xtensa_int_decode with, passing that address of the register save + * area as a parameter (A2). */ -#ifdef __XTENSA_CALL0_ABI__ - movi a2, XTENSA_IRQ_TIMER0 /* Argument 1: Timer0 IRQ number */ - mov a3, a12 /* Argument 2: Top of stack = register save area */ - call0 xtensa_irq_dispatch /* Call xtensa_int_decode */ -#else - movi a6, XTENSA_IRQ_TIMER0 /* Argument 1: Timer0 IRQ number */ - mov a7, a12 /* Argument 2: Top of stack = register save area */ - call4 xtensa_irq_dispatch /* Call xtensa_int_decode */ -#endif + /* Argument 1: Set of CPU interrupt to dispatch */ + mov a7, sp /* Argument 2: Top of stack = register save area */ + call4 xtensa_int_decode /* Call xtensa_int_decode */ - /* On return from xtensa_irq_dispatch, A2 will contain the address of the new + /* On return from xtensa_int_decode, a2 will contain the address of the new * register save area. Usually this would be the same as the current SP. - * But in the event of a context switch, A2 will instead refer to the TCB - * register save area. + * But in the event of a context switch, a2 will instead refer to the TCB + * register save area. This may or may not reside on a stack. */ - beq a2, a12, 5f /* If timer interrupt then skip table */ + beq a4, sp, 3f /* If no context switch then keep stack */ /* Switch stacks */ - mov a12, a2 /* Switch to the save area of the new thread */ + mov a12, a4 /* Switch to the save area of the new thread */ l32i a2, a12, (4 * REG_A1) /* Retrieve stack ptr and replace */ addi sp, a2, -(4 * XCPTCONTEXT_SIZE) - .endif - - j ._xtensa_dispatch_level&level& /* Check for more interrupts */ +#endif -5: - /* done */ + /* Done */ +3: .endm /**************************************************************************** diff --git a/arch/xtensa/src/esp32/esp32_cpuint.c b/arch/xtensa/src/esp32/esp32_cpuint.c index 84a1f9abd9..d3cb0ef634 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.c +++ b/arch/xtensa/src/esp32/esp32_cpuint.c @@ -40,6 +40,7 @@ #include #include +#include #include #include #include @@ -147,6 +148,17 @@ #define ESP32_MAX_PRIORITY 5 #define ESP32_PRIO_INDEX(p) ((p) - ESP32_MIN_PRIORITY) +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Maps a CPU interrupt to the attached peripheral interrupt */ + +uint8_t g_cpu0_intmap[ESP32_NCPUINTS]; +#ifdef CONFIG_SMP +uint8_t g_cpu1_intmap[ESP32_NCPUINTS]; +#endif + /**************************************************************************** * Private Data ****************************************************************************/ @@ -156,13 +168,9 @@ */ #ifdef CONFIG_SMP - static uint32_t g_intenable[CONFIG_SMP_NCPUS]; - #else - static uint32_t g_intenable[1]; - #endif /* Bitsets for free, unallocated CPU interrupts available to peripheral @@ -170,11 +178,8 @@ static uint32_t g_intenable[1]; */ static uint32_t g_cpu0_freeints = EPS32_CPUINT_PERIPHSET; - #ifdef CONFIG_SMP - static uint32_t g_cpu1_freeints = EPS32_CPUINT_PERIPHSET; - #endif /* Bitsets for each interrupt priority 1-5 */ @@ -311,6 +316,7 @@ int esp32_alloc_cpuint(uint32_t intmask) int esp32_cpuint_initialize(void) { uintptr_t regaddr; + uint8_t *intmap; #ifdef CONFIG_SMP int cpu; #endif @@ -345,6 +351,38 @@ int esp32_cpuint_initialize(void) putreg32(NO_CPUINT, regaddr); } + /* Initialize CPU0-to-peripheral mapping table */ + +#ifdef CONFIG_SMP + if (cpu != 0) + { + intmap = g_cpu1_intmap; + } + else +#endif + { + intmap = g_cpu0_intmap; + } + + /* Indiate that no peripheral interrupts are assigned to CPU interrupts */ + + memset(intmap, CPUINT_UNASSIGNED, ESP32_NCPUINTS); + + /* Special case the 6 internal interrupts. + * + * CPU interrupt bit IRQ number + * --------------------------- --------------------- + * ESP32_CPUINT_TIMER0 6 XTENSA_IRQ_TIMER0 0 + * SP32_CPUINT_SOFTWARE0 7 Not yet defined + * ESP32_CPUINT_PROFILING 11 Not yet defined + * ESP32_CPUINT_TIMER1 15 XTENSA_IRQ_TIMER1 1 + * ESP32_CPUINT_TIMER2 16 XTENSA_IRQ_TIMER2 2 + * ESP32_CPUINT_SOFTWARE1 29 Not yet defined + */ + + intmap[ESP32_CPUINT_TIMER0] = XTENSA_IRQ_TIMER0; + intmap[ESP32_CPUINT_TIMER1] = XTENSA_IRQ_TIMER1; + intmap[ESP32_CPUINT_TIMER2] = XTENSA_IRQ_TIMER2; return OK; } @@ -524,6 +562,7 @@ void esp32_free_cpuint(int cpuint) void esp32_attach_peripheral(int cpu, int periphid, int cpuint) { uintptr_t regaddr; + uint8_t *intmap; DEBUGASSERT(periphid >= 0 && periphid < ESP32_NPERIPHERALS); DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32_CPUINT_MAX); @@ -533,13 +572,18 @@ void esp32_attach_peripheral(int cpu, int periphid, int cpuint) if (cpu != 0) { regaddr = DPORT_APP_MAP_REGADDR(periphid); + intmap = g_cpu1_intmap; } else #endif { regaddr = DPORT_PRO_MAP_REGADDR(periphid); + intmap = g_cpu0_intmap; } + DEBUGASSERT(intmap[cpuint] == CPUINT_UNASSIGNED); + intmap[cpuint] = periphid + XTENSA_IRQ_FIRSTPERIPH; + putreg32(cpuint, regaddr); } @@ -564,6 +608,7 @@ void esp32_attach_peripheral(int cpu, int periphid, int cpuint) void esp32_detach_peripheral(int cpu, int periphid, int cpuint) { uintptr_t regaddr; + uint8_t *intmap; DEBUGASSERT(periphid >= 0 && periphid < ESP32_NPERIPHERALS); #ifdef CONFIG_SMP @@ -572,12 +617,17 @@ void esp32_detach_peripheral(int cpu, int periphid, int cpuint) if (cpu != 0) { regaddr = DPORT_APP_MAP_REGADDR(periphid); + intmap = g_cpu1_intmap; } else #endif { regaddr = DPORT_PRO_MAP_REGADDR(periphid); + intmap = g_cpu0_intmap; } + DEBUGASSERT(intmap[cpuint] != CPUINT_UNASSIGNED); + intmap[cpuint] = CPUINT_UNASSIGNED; + putreg32(NO_CPUINT, regaddr); } diff --git a/arch/xtensa/src/esp32/esp32_cpuint.h b/arch/xtensa/src/esp32/esp32_cpuint.h index eab06bf197..9d825476aa 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.h +++ b/arch/xtensa/src/esp32/esp32_cpuint.h @@ -42,6 +42,25 @@ #include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CPUINT_UNASSIGNED 0xff /* No peripheral assigned to this CPU interrupt */ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Maps a CPU interrupt to the attached peripheral interrupt */ + +extern uint8_t g_cpu0_intmap[ESP32_NCPUINTS]; +#ifdef CONFIG_SMP +extern uint8_t g_cpu1_intmap[ESP32_NCPUINTS]; +#endif + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ diff --git a/arch/xtensa/src/esp32/esp32_intdecode.c b/arch/xtensa/src/esp32/esp32_intdecode.c index 675c5327e6..0bc4041524 100644 --- a/arch/xtensa/src/esp32/esp32_intdecode.c +++ b/arch/xtensa/src/esp32/esp32_intdecode.c @@ -39,29 +39,32 @@ #include -#include -#include +#include +#include + +#include +#include -#include "chip/esp32_dport.h" #include "xtensa.h" +#include "esp32_cpuint.h" /**************************************************************************** - * Private Data + * Private Functions ****************************************************************************/ -static const uint8_t g_baseirq[3] = -{ - ESP32_IRQ_SREG0, - ESP32_IRQ_SREG1, - ESP32_IRQ_SREG2 -}; +/**************************************************************************** + * Name: xtensa_intclear + ****************************************************************************/ -static const uint8_t g_nirqs[3] = +static inline void xtensa_intclear(uint32_t mask) { - ESP32_NIRQS_SREG0, - ESP32_NIRQS_SREG1, - ESP32_NIRQS_SREG2 -}; + __asm__ __volatile__ + ( + "movi a2, 0\n" + "wsr %0, INTCLEAR\n" + : "=r"(mask) : : + ); +} /**************************************************************************** * Public Functions @@ -75,80 +78,74 @@ static const uint8_t g_nirqs[3] = * handling to the registered interrupt handler via xtensa_irq_dispatch(). * * Input Parameters: - * regs - Saves processor state on the stack + * cpuints - Set of pending interrupts valid for this level + * regs - Saves processor state on the stack * * Returned Value: - * Normally the same vale as regs is returned. But, in the event of an + * Normally the same value as regs is returned. But, in the event of an * interrupt level context switch, the returned value will, instead point * to the saved processor state in the TCB of the newly started task. * ****************************************************************************/ -uint32_t *xtensa_int_decode(uint32_t *regs) +uint32_t *xtensa_int_decode(uint32_t cpuints, uint32_t *regs) { - uintptr_t regaddr; - uint32_t regval; + uint8_t *intmap; uint32_t mask; - int regndx; int bit; - int baseirq; - int nirqs; - #ifdef CONFIG_SMP int cpu; +#endif - /* Select PRO or APP interrupt status registers */ +#ifdef CONFIG_SMP + /* Select PRO or APP CPU interrupt mapping table */ cpu = up_cpu_index(); - if (cpu == 0) + if (cpu != 0) { - regaddr = DPORT_PRO_INTR_STATUS_0_REG; + intmap = g_cpu1_intmap; } else #endif { - regaddr = DPORT_APP_INTR_STATUS_0_REG; + intmap = g_cpu0_intmap; } - /* Process each pending interrupt in each of the three interrupt status - * registers. - */ + /* Skip over zero bits, eight at a time */ - for (regndx = 0; regndx < 3; regndx++) - { - /* Fetch the next register status register */ + for (bit = 0, mask = 0xff; + bit < ESP32_NCPUINTS && (cpuints & mask) == 0; + bit += 8, mask <<= 8); - regval = getreg32(regaddr); - regaddr += sizeof(uint32_t); + /* Process each pending CPU interrupt */ - /* Set up the search */ + for (; bit < ESP32_NCPUINTS && cpuints != 0; bit++) + { + mask = (1 << bit); + if ((cpuints & mask) != 0) + { + /* Extract the IRQ number from the mapping table */ - baseirq = g_baseirq[regndx]; - nirqs = g_nirqs[regndx]; + uint8_t irq = intmap[bit]; + DEBUGASSERT(irq != CPUINT_UNASSIGNED); - /* Decode and dispatch each pending bit in the interrupt status - * register. - */ + /* Clear software or edge-triggered interrupt */ - for (bit = 0; regval != 0 && bit < nirqs; bit++) - { - /* Check if this interrupt is pending */ + xtensa_intclear(mask); - mask = (1 << bit); - if ((regval & mask) != 0) - { - /* Yes.. Dispatch the interrupt. Note that regs may be - * altered in the case of an interrupt level context switch. - */ + /* Dispatch the CPU interrupt. + * + * NOTE that regs may be altered in the case of an interrupt + * level context switch. + */ - regs = xtensa_irq_dispatch(baseirq + bit, regs); + regs = xtensa_irq_dispatch((int)irq, regs); - /* Clear this bit in the sampled status register so that - * perhaps we can exit this loop sooner. - */ + /* Clear the bit in the pending interrupt so that perhaps + * we can exit the look early. + */ - regval &= ~mask; - } + cpuints &= ~mask; } } -- GitLab From 6599feb310021d1a38bc5191b1219b0a750a96b6 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 16 Dec 2016 17:56:22 -0600 Subject: [PATCH 711/734] Xtensa ESP32: Fixes a few issue with restoring registers on interrupt return, but there is still a problem --- arch/xtensa/src/common/xtensa_context.S | 27 +++--- arch/xtensa/src/common/xtensa_int_handlers.S | 94 +++++++++----------- arch/xtensa/src/common/xtensa_user_handler.S | 42 ++++----- arch/xtensa/src/common/xtensa_vectors.S | 10 +-- arch/xtensa/src/esp32/esp32_cpuint.c | 4 +- arch/xtensa/src/esp32/esp32_cpuint.h | 2 +- 6 files changed, 80 insertions(+), 99 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index c3e7030b02..bbe68ede20 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -170,8 +170,8 @@ _xtensa_context_save: call0 _xtensa_window_spill /* Preserves only a4-a5, a8-a9, a12-a13 */ rsr a2, EXCSAVE_1 /* Save interruptee's a0 */ - l32i a0, a2, (4 * REG_TMP0) /* Save return address */ - l32i sp, a2, (4 * REG_TMP1) /* Save current stack pointer */ + l32i a0, a2, (4 * REG_TMP0) /* Save return address */ + l32i sp, a2, (4 * REG_TMP1) /* Save current stack pointer */ #endif ret @@ -189,7 +189,7 @@ _xtensa_context_save: * called from user code (with interrupts disabled) to save the current * state of the running thread. This function always returns zero. * However, it sets the saved value of the return address (A2) to 1. - * If the thread is restarted via _xtensa_contest_restore or + * If the thread is s via _xtensa_context_restore or * xtensa_context_restore, it will appear as a second return from * xtensa_context_save but with the returned value of 1 to distinguish * the two cases. @@ -264,12 +264,13 @@ xtensa_context_save: * * Exit conditions: * - A0 = Return address in caller. - * - Other registers are restored as detailed above (including A1 and A2). + * - Other registers are restored as detailed above + * - A2 is preserved * ****************************************************************************/ .global _xtensa_context_restore - .type _xtensa_context_restore,@function + .type xtensa_context_restore,@function .align 4 .literal_position @@ -278,12 +279,12 @@ xtensa_context_save: _xtensa_context_restore: #ifdef XCHAL_HAVE_LOOPS - l32i a2, a2, (4 * REG_LBEG) - l32i a3, a2, (4 * REG_LEND) - wsr a2, LBEG - l32i a2, a2, (4 * REG_LCOUNT) - wsr a3, LEND - wsr a2, LCOUNT + l32i a3, a2, (4 * REG_LBEG) + l32i a4, a2, (4 * REG_LEND) + wsr a3, LBEG + l32i a3, a2, (4 * REG_LCOUNT) + wsr a4, LEND + wsr a3, LCOUNT #endif #ifdef CONFIG_XTENSA_USE_OVLY @@ -317,10 +318,6 @@ _xtensa_context_restore: l32i a14, a2, (4 * REG_A14) l32i a15, a2, (4 * REG_A15) - /* Finally, restore A2 with the correct value */ - - l32i a2, a2, (4 * REG_A2) - ret .size _xtensa_context_restore, . - _xtensa_context_restore diff --git a/arch/xtensa/src/common/xtensa_int_handlers.S b/arch/xtensa/src/common/xtensa_int_handlers.S index 91c673b07e..5b59ac8774 100644 --- a/arch/xtensa/src/common/xtensa_int_handlers.S +++ b/arch/xtensa/src/common/xtensa_int_handlers.S @@ -136,7 +136,7 @@ movi a4, \mask and a2, a2, a3 and a2, a2, a4 /* a2 = Set of pending, enabled interrupts for this level */ - beqz a2, 3f /* Nothing to do */ + beqz a2, 1f /* Nothing to do */ /* Call xtensa_int_decode with, passing that address of the register save * area as a parameter (A2). @@ -152,13 +152,7 @@ * register save area. This may or may not reside on a stack. */ - beq a2, sp, 3f /* If no context switch then keep stack */ - - /* Switch stacks */ - mov a12, a2 /* Switch to the save area of the new thread */ - l32i a2, a12, (4 * REG_A1) /* Retrieve stack ptr and replace */ - addi sp, a2, -(4 * XCPTCONTEXT_SIZE) #else /* Get mask of pending, enabled interrupts at this level into a2. */ @@ -168,7 +162,7 @@ movi a3, \mask and a6, a6, a2 and a6, a6, a3 /* a6 = Set of pending, enabled interrupts for this level */ - beqz a6, 3f /* Nothing to do */ + beqz a6, 1f /* Nothing to do */ /* Call xtensa_int_decode with, passing that address of the register save * area as a parameter (A2). @@ -178,24 +172,18 @@ mov a7, sp /* Argument 2: Top of stack = register save area */ call4 xtensa_int_decode /* Call xtensa_int_decode */ - /* On return from xtensa_int_decode, a2 will contain the address of the new + /* On return from xtensa_int_decode, a6 will contain the address of the new * register save area. Usually this would be the same as the current SP. * But in the event of a context switch, a2 will instead refer to the TCB * register save area. This may or may not reside on a stack. */ - beq a4, sp, 3f /* If no context switch then keep stack */ - - /* Switch stacks */ - - mov a12, a4 /* Switch to the save area of the new thread */ - l32i a2, a12, (4 * REG_A1) /* Retrieve stack ptr and replace */ - addi sp, a2, -(4 * XCPTCONTEXT_SIZE) + mov a12, a6 /* Switch to the save area of the new thread */ #endif /* Done */ -3: +1: .endm /**************************************************************************** @@ -291,17 +279,17 @@ _xtensa_level1_handler: /* Restore registers in preparation to return from interrupt */ mov a2, a12 /* a2 = address of new state save area */ - call0 _xtensa_context_restore + call0 _xtensa_context_restore /* (preserves a2) */ /* Restore only level-specific regs (the rest were already restored) */ - l32i a0, sp, (4 * REG_PS) /* Retrieve interruptee's PS */ + l32i a0, a2, (4 * REG_PS) /* Retrieve interruptee's PS */ wsr a0, PS - l32i a0, sp, (4 * REG_PC) /* Retrieve interruptee's PC */ + l32i a0, a2, (4 * REG_PC) /* Retrieve interruptee's PC */ wsr a0, EPC_1 - l32i a0, sp, (4 * REG_A0) /* Retrieve interruptee's A0 */ - l32i a2, sp, (4 * REG_A2) /* Retrieve interruptee's A2 */ - l32i sp, sp, (4 * REG_A1) /* Remove interrupt stack frame */ + l32i a0, a2, (4 * REG_A0) /* Retrieve interruptee's A0 */ + l32i sp, a2, (4 * REG_A1) /* Remove interrupt stack frame */ + l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2 */ rsync /* Ensure EPS and EPC written */ /* Return from interrupt. RFI restores the PS from EPS_1 and jumps to @@ -376,17 +364,17 @@ _xtensa_level2_handler: /* Restore registers in preparation to return from interrupt */ mov a2, a12 /* a2 = address of new state save area */ - call0 _xtensa_context_restore + call0 _xtensa_context_restore /* (preserves a2) */ /* Restore only level-specific regs (the rest were already restored) */ - l32i a0, sp, (4 * REG_PS) /* Retrieve interruptee's PS */ + l32i a0, a2, (4 * REG_PS) /* Retrieve interruptee's PS */ wsr a0, EPS_2 - l32i a0, sp, (4 * REG_PC) /* Retrieve interruptee's PC */ + l32i a0, a2, (4 * REG_PC) /* Retrieve interruptee's PC */ wsr a0, EPC_2 - l32i a0, sp, (4 * REG_A0) /* Retrieve interruptee's A0 */ - l32i a2, sp, (4 * REG_A2) /* Retrieve interruptee's A2 */ - l32i sp, sp, (4 * REG_A1) /* Remove interrupt stack frame */ + l32i a0, a2, (4 * REG_A0) /* Retrieve interruptee's A0 */ + l32i sp, a2, (4 * REG_A1) /* Remove interrupt stack frame */ + l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2 */ rsync /* Ensure EPS and EPC written */ /* Return from interrupt. RFI restores the PS from EPS_2 and jumps to @@ -437,17 +425,17 @@ _xtensa_level3_handler: /* Restore registers in preparation to return from interrupt */ mov a2, a12 /* a2 = address of new state save area */ - call0 _xtensa_context_restore + call0 _xtensa_context_restore /* (preserves a2) */ /* Restore only level-specific regs (the rest were already restored) */ - l32i a0, sp, (4 * REG_PS) /* Retrieve interruptee's PS */ + l32i a0, a2, (4 * REG_PS) /* Retrieve interruptee's PS */ wsr a0, EPS_3 - l32i a0, sp, (4 * REG_PC) /* Retrieve interruptee's PC */ + l32i a0, a2, (4 * REG_PC) /* Retrieve interruptee's PC */ wsr a0, EPC_3 - l32i a0, sp, (4 * REG_A0) /* Retrieve interruptee's A0 */ - l32i a2, sp, (4 * REG_A2) /* Retrieve interruptee's A2 */ - l32i sp, sp, (4 * REG_A1) /* Remove interrupt stack frame */ + l32i a0, a2, (4 * REG_A0) /* Retrieve interruptee's A0 */ + l32i sp, a2, (4 * REG_A1) /* Remove interrupt stack frame */ + l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2 */ rsync /* Ensure EPS and EPC written */ /* Return from interrupt. RFI restores the PS from EPS_3 and jumps to @@ -498,17 +486,17 @@ _xtensa_level4_handler: /* Restore registers in preparation to return from interrupt */ mov a2, a12 /* a2 = address of new state save area */ - call0 _xtensa_context_restore + call0 _xtensa_context_restore /* (presevers a2) */ /* Restore only level-specific regs (the rest were already restored) */ - l32i a0, sp, (4 * REG_PS) /* Retrieve interruptee's PS */ + l32i a0, a2, (4 * REG_PS) /* Retrieve interruptee's PS */ wsr a0, EPS_4 - l32i a0, sp, (4 * REG_PC) /* Retrieve interruptee's PC */ + l32i a0, a2, (4 * REG_PC) /* Retrieve interruptee's PC */ wsr a0, EPC_4 - l32i a0, sp, (4 * REG_A0) /* Retrieve interruptee's A0 */ - l32i a2, sp, (4 * REG_A2) /* Retrieve interruptee's A2 */ - l32i sp, sp, (4 * REG_A1) /* Remove interrupt stack frame */ + l32i a0, a2, (4 * REG_A0) /* Retrieve interruptee's A0 */ + l32i sp, a2, (4 * REG_A1) /* Remove interrupt stack frame */ + l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2 */ rsync /* Ensure EPS and EPC written */ /* Return from interrupt. RFI restores the PS from EPS_4 and jumps to @@ -559,17 +547,17 @@ _xtensa_level5_handler: /* Restore registers in preparation to return from interrupt */ mov a2, a12 /* a2 = address of new state save area */ - call0 _xtensa_context_restore + call0 _xtensa_context_restore /* (preserves a2) */ /* Restore only level-specific regs (the rest were already restored) */ - l32i a0, sp, (4 * REG_PS) /* Retrieve interruptee's PS */ + l32i a0, a2, (4 * REG_PS) /* Retrieve interruptee's PS */ wsr a0, EPS_5 - l32i a0, sp, (4 * REG_PC) /* Retrieve interruptee's PC */ + l32i a0, a2, (4 * REG_PC) /* Retrieve interruptee's PC */ wsr a0, EPC_5 - l32i a0, sp, (4 * REG_A0) /* Retrieve interruptee's A0 */ - l32i a2, sp, (4 * REG_A2) /* Retrieve interruptee's A2 */ - l32i sp, sp, (4 * REG_A1) /* Remove interrupt stack frame */ + l32i a0, a2, (4 * REG_A0) /* Retrieve interruptee's A0 */ + l32i sp, a2, (4 * REG_A1) /* Remove interrupt stack frame */ + l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2 */ rsync /* Ensure EPS and EPC written */ /* Return from interrupt. RFI restores the PS from EPS_5 and jumps to @@ -620,17 +608,17 @@ _xtensa_level6_handler: /* Restore registers in preparation to return from interrupt */ mov a2, a12 /* a2 = address of new state save area */ - call0 _xtensa_context_restore + call0 _xtensa_context_restore /* (preserves a2) */ /* Restore only level-specific regs (the rest were already restored) */ - l32i a0, sp, (4 * REG_PS) /* Retrieve interruptee's PS */ + l32i a0, a2, (4 * REG_PS) /* Retrieve interruptee's PS */ wsr a0, EPS_6 - l32i a0, sp, (4 * REG_PC) /* Retrieve interruptee's PC */ + l32i a0, a2, (4 * REG_PC) /* Retrieve interruptee's PC */ wsr a0, EPC_6 - l32i a0, sp, (4 * REG_A0) /* Retrieve interruptee's A0 */ - l32i a2, sp, (4 * REG_A2) /* Retrieve interruptee's A2 */ - l32i sp, sp, (4 * REG_A1) /* Remove interrupt stack frame */ + l32i a0, a2, (4 * REG_A0) /* Retrieve interruptee's A0 */ + l32i sp, a2, (4 * REG_A1) /* Remove interrupt stack frame */ + l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2 */ rsync /* Ensure EPS and EPC written */ /* Return from interrupt. RFI restores the PS from EPS_6 and jumps to diff --git a/arch/xtensa/src/common/xtensa_user_handler.S b/arch/xtensa/src/common/xtensa_user_handler.S index 924cb2554a..ca118aae80 100644 --- a/arch/xtensa/src/common/xtensa_user_handler.S +++ b/arch/xtensa/src/common/xtensa_user_handler.S @@ -329,51 +329,47 @@ _xtensa_syscall_handler: ps_setup 1 a0 /* Dispatch the sycall as with other interrupts. */ - /* At this point, sp holds the pointer to the register save area. That, - * however, may change as a consequence of context switching. - */ mov a12, sp /* a12 = address of register save area */ + #ifdef __XTENSA_CALL0_ABI__ movi a2, XTENSA_IRQ_SYSCALL /* Argument 1: IRQ number */ - mov a3, a12 /* Argument 2: Top of stack = register save area */ + mov a3, sp /* Argument 2: Top of stack = register save area */ call0 xtensa_irq_dispatch /* Call xtensa_int_decode */ + + /* On return from xtensa_irq_dispatch, a2 will contain the address of the new + * register save area. Usually this would be the same as the current SP. + * But in the event of a context switch, A2 will instead refer to the TCB + * register save area. + */ + #else movi a6, XTENSA_IRQ_SYSCALL /* Argument 1: IRQ number */ - mov a7, a12 /* Argument 2: Top of stack = register save area */ + mov a7, sp /* Argument 2: Top of stack = register save area */ call4 xtensa_irq_dispatch /* Call xtensa_int_decode */ -#endif - /* On return from xtensa_irq_dispatch, A2 will contain the address of the new + /* On return from xtensa_irq_dispatch, a5 will contain the address of the new * register save area. Usually this would be the same as the current SP. * But in the event of a context switch, A2 will instead refer to the TCB * register save area. */ - beq a2, a12, 2f /* If timer interrupt then skip table */ - - /* Switch stacks */ - - mov a12, a2 /* Switch to the save area of the new thread */ - l32i a2, a12, (4 * REG_A1) /* Retrieve stack ptr and replace */ - addi sp, a2, -(4 * XCPTCONTEXT_SIZE) - -2: + mov a2, a6 /* Switch to the new register save area */ +#endif /* Restore registers in preparation to return from interrupt */ - mov a2, a12 /* a2 = address of new state save area */ - call0 _xtensa_context_restore + call0 _xtensa_context_restore /* (Preserves a2) */ /* Restore only level-specific regs (the rest were already restored) */ - l32i a0, sp, (4 * REG_PS) /* Retrieve interruptee's PS */ + l32i a0, a2, (4 * REG_PS) /* Retrieve interruptee's PS */ wsr a0, PS - l32i a0, sp, (4 * REG_PC) /* Retrieve interruptee's PC */ + l32i a0, a2, (4 * REG_PC) /* Retrieve interruptee's PC */ wsr a0, EPC_1 - l32i a0, sp, (4 * REG_A0) /* Retrieve interruptee's A0 */ - l32i a2, sp, (4 * REG_A2) /* Retrieve interruptee's A2 */ - l32i sp, sp, (4 * REG_A1) /* Remove interrupt stack frame */ + l32i a0, a2, (4 * REG_A0) /* Retrieve interruptee's A0 */ + l32i sp, a2, (4 * REG_A1) /* Remove interrupt stack frame */ + l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2 */ rsync /* Ensure EPS and EPC written */ /* Return from exception. RFE returns from either the UserExceptionVector diff --git a/arch/xtensa/src/common/xtensa_vectors.S b/arch/xtensa/src/common/xtensa_vectors.S index 015e778c74..39ccf8ac67 100644 --- a/arch/xtensa/src/common/xtensa_vectors.S +++ b/arch/xtensa/src/common/xtensa_vectors.S @@ -75,7 +75,7 @@ _xtensa_level2_vector: /* Never returns here - call0 is used as a jump */ - .end literal_prefix + .end literal_prefix .size _xtensa_level2_vector, . - _xtensa_level2_vector #endif @@ -94,7 +94,7 @@ _xtensa_level3_vector: /* Never returns here - call0 is used as a jump */ - .end literal_prefix + .end literal_prefix .size _xtensa_level3_vector, . - _xtensa_level3_vector #endif @@ -113,7 +113,7 @@ _xtensa_level4_vector: /* Never returns here - call0 is used as a jump */ - .end literal_prefix + .end literal_prefix .size _xtensa_level5_vector, . - _xtensa_level5_vector #endif @@ -132,8 +132,8 @@ _xtensa_level5_vector: /* Never returns here - call0 is used as a jump */ - .size _xtensa_level5_vector, . - _xtensa_level5_vector - .end literal_prefix + .size _xtensa_level5_vector, . - _xtensa_level5_vector + .end literal_prefix #endif #if XCHAL_EXCM_LEVEL >= 6 diff --git a/arch/xtensa/src/esp32/esp32_cpuint.c b/arch/xtensa/src/esp32/esp32_cpuint.c index d3cb0ef634..4fba5b3e31 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.c +++ b/arch/xtensa/src/esp32/esp32_cpuint.c @@ -152,7 +152,7 @@ * Public Data ****************************************************************************/ -/* Maps a CPU interrupt to the attached peripheral interrupt */ +/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */ uint8_t g_cpu0_intmap[ESP32_NCPUINTS]; #ifdef CONFIG_SMP @@ -351,7 +351,7 @@ int esp32_cpuint_initialize(void) putreg32(NO_CPUINT, regaddr); } - /* Initialize CPU0-to-peripheral mapping table */ + /* Initialize CPU interrupt-to-IRQ mapping table */ #ifdef CONFIG_SMP if (cpu != 0) diff --git a/arch/xtensa/src/esp32/esp32_cpuint.h b/arch/xtensa/src/esp32/esp32_cpuint.h index 9d825476aa..0132ce8071 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.h +++ b/arch/xtensa/src/esp32/esp32_cpuint.h @@ -54,7 +54,7 @@ * Public Data ****************************************************************************/ -/* Maps a CPU interrupt to the attached peripheral interrupt */ +/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */ extern uint8_t g_cpu0_intmap[ESP32_NCPUINTS]; #ifdef CONFIG_SMP -- GitLab From d9c01052d9b2df011abed79c74997601be3609fe Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Sat, 17 Dec 2016 02:20:10 -1000 Subject: [PATCH 712/734] C&P error from F7 --- arch/arm/src/stm32/stm32_serial.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c index 644c810817..10919e878b 100644 --- a/arch/arm/src/stm32/stm32_serial.c +++ b/arch/arm/src/stm32/stm32_serial.c @@ -1945,11 +1945,11 @@ static int up_interrupt_common(struct up_dev_s *priv) static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { #if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \ - || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT) + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; #endif -#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT) +#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #endif int ret = OK; -- GitLab From adbacfc42ce986a06a63f0a9b7aab6ed37d48b0b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 17 Dec 2016 07:07:33 -0600 Subject: [PATCH 713/734] Xtensa ESP32: Fix a duplicate in Kconfig files. Level 1 should return via RFE. --- arch/xtensa/Kconfig | 4 ++++ arch/xtensa/src/common/xtensa_context.S | 7 +++++- arch/xtensa/src/common/xtensa_int_handlers.S | 7 +++--- arch/xtensa/src/common/xtensa_user_handler.S | 6 ++--- arch/xtensa/src/lx6/Kconfig | 23 -------------------- 5 files changed, 17 insertions(+), 30 deletions(-) diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 5c051980e6..b00d8f0d23 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -22,6 +22,10 @@ config ARCH_CHIP_ESP32 of two CPUs is symmetric, meaning they use the same addresses to access the same memory. + The two CPUs are named "PRO_CPU" and "APP_CPU" (for "protocol" and + "application"), however for most purposes the two CPUs are + interchangeable. + endchoice # XTENSA chip selection config ARCH_FAMILY_LX6 diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index bbe68ede20..f927f99c05 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -371,10 +371,15 @@ xtensa_context_restore: l32i a0, a2, (4 * REG_PS) /* Restore PS */ wsr a0, PS l32i a0, a2, (4 * REG_PC) /* Set up for RFE */ - rsr a0, EPC + rsr a0, EPC_1 l32i a0, a2, (4 * REG_A0) /* Restore a0 */ l32i a2, a2, (4 * REG_A2) /* Restore A2 */ + /* Return from exception. RFE returns from either the UserExceptionVector + * or the KernelExceptionVector. RFE sets PS.EXCM back to 0, and then + * jumps to the address in EPC[1]. PS.UM and PS.WOE are left unchanged. + */ + rfe /* And return from "exception" */ .size xtensa_context_restore, . - xtensa_context_restore diff --git a/arch/xtensa/src/common/xtensa_int_handlers.S b/arch/xtensa/src/common/xtensa_int_handlers.S index 5b59ac8774..a7d12e5940 100644 --- a/arch/xtensa/src/common/xtensa_int_handlers.S +++ b/arch/xtensa/src/common/xtensa_int_handlers.S @@ -292,11 +292,12 @@ _xtensa_level1_handler: l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2 */ rsync /* Ensure EPS and EPC written */ - /* Return from interrupt. RFI restores the PS from EPS_1 and jumps to - * the address in EPC_1. + /* Return from exception. RFE returns from either the UserExceptionVector + * or the KernelExceptionVector. RFE sets PS.EXCM back to 0, and then + * jumps to the address in EPC[1]. PS.UM and PS.WOE are left unchanged. */ - rfi 1 + rfe /* And return from "exception" */ /**************************************************************************** * MEDIUM PRIORITY (LEVEL 2+) INTERRUPT LOW LEVEL HANDLERS. diff --git a/arch/xtensa/src/common/xtensa_user_handler.S b/arch/xtensa/src/common/xtensa_user_handler.S index ca118aae80..39c9eb1c7f 100644 --- a/arch/xtensa/src/common/xtensa_user_handler.S +++ b/arch/xtensa/src/common/xtensa_user_handler.S @@ -372,9 +372,9 @@ _xtensa_syscall_handler: l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2 */ rsync /* Ensure EPS and EPC written */ - /* Return from exception. RFE returns from either the UserExceptionVector - * or the KernelExceptionVector. RFE sets PS.EXCM back to 0 and then jumps - * to the address in EPC[1]. + /* Return from exception. RFE returns from either the UserExceptionVector + * or the KernelExceptionVector. RFE sets PS.EXCM back to 0, and then + * jumps to the address in EPC[1]. PS.UM and PS.WOE are left unchanged. */ rfe diff --git a/arch/xtensa/src/lx6/Kconfig b/arch/xtensa/src/lx6/Kconfig index 073954b7d6..9edff0ce33 100644 --- a/arch/xtensa/src/lx6/Kconfig +++ b/arch/xtensa/src/lx6/Kconfig @@ -5,27 +5,4 @@ if ARCH_CHIP_LX6 -choice - prompt "LX6 implementation" - default ARCH_CHIP_ESP32 - -config ARCH_CHIP_ESP32 - bool "Expressif ESP32" - ---help--- - The ESP32 is a dual-core system with two Harvard Architecture Xtensa - LX6 CPUs. All embedded memory, external memory and peripherals are - located on the data bus and/or the instruction bus of these CPUs. - With some minor exceptions the address mapping of two CPUs is - symmetric, meaning they use the same addresses to access the same - memory. Multiple peripherals in the system can access embedded - memory via DMA. - - The two CPUs are named "PRO_CPU" and "APP_CPU" (for "protocol" and - "application"), however for most purposes the two CPUs are - interchangeable. - -endchoice # LX6 implementation - -source arch/xtensa/src/esp32/Kconfig - endif # ARCH_CHIP_LX6 -- GitLab From 05e798488baad93bbcf011e3e97c2550ea1b4c3a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 17 Dec 2016 08:10:10 -0600 Subject: [PATCH 714/734] One register getting clobber on context save --- arch/xtensa/src/common/xtensa_context.S | 1 - arch/xtensa/src/common/xtensa_int_handlers.S | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index f927f99c05..10d772c12d 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -116,7 +116,6 @@ _xtensa_context_save: - s32i a2, a2, (4 * REG_A2) s32i a3, a2, (4 * REG_A3) s32i a4, a2, (4 * REG_A4) s32i a5, a2, (4 * REG_A5) diff --git a/arch/xtensa/src/common/xtensa_int_handlers.S b/arch/xtensa/src/common/xtensa_int_handlers.S index a7d12e5940..f84992d212 100644 --- a/arch/xtensa/src/common/xtensa_int_handlers.S +++ b/arch/xtensa/src/common/xtensa_int_handlers.S @@ -290,7 +290,7 @@ _xtensa_level1_handler: l32i a0, a2, (4 * REG_A0) /* Retrieve interruptee's A0 */ l32i sp, a2, (4 * REG_A1) /* Remove interrupt stack frame */ l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2 */ - rsync /* Ensure EPS and EPC written */ + rsync /* Ensure PS and EPC written */ /* Return from exception. RFE returns from either the UserExceptionVector * or the KernelExceptionVector. RFE sets PS.EXCM back to 0, and then -- GitLab From 38ebe6c13f3053788a8c22c4b074c0a228d4b8ff Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 17 Dec 2016 08:11:32 -0600 Subject: [PATCH 715/734] Xtensa ESP32: Change that should have been included in a previous commit was not. --- arch/xtensa/src/common/xtensa.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index 422ec0b96f..9cf4778e54 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -266,7 +266,7 @@ void xtensa_coproc_disable(struct xtensa_cpstate_s *cpstate, int cpset); /* IRQs */ -uint32_t *xtensa_int_decode(uint32_t *regs); +uint32_t *xtensa_int_decode(uint32_t cpuints, uint32_t *regs); uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs); uint32_t xtensa_enable_cpuint(uint32_t *shadow, uint32_t intmask); uint32_t xtensa_disable_cpuint(uint32_t *shadow, uint32_t intmask); -- GitLab From 548108764a9dbdfdcec52e2a172d0a581deb2ae9 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Sat, 17 Dec 2016 04:29:41 -1000 Subject: [PATCH 716/734] BugFix:uart_ops_s portion of cdcacm will not be initalized with correct functions if CONFIG_SERIAL_DMA is lit. This fixes the issses in a C99 compatible way --- drivers/usbdev/cdcacm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/usbdev/cdcacm.c b/drivers/usbdev/cdcacm.c index 64e2e68075..15f92dd9ae 100644 --- a/drivers/usbdev/cdcacm.c +++ b/drivers/usbdev/cdcacm.c @@ -242,6 +242,12 @@ static const struct uart_ops_s g_uartops = NULL, /* rxavailable */ #ifdef CONFIG_SERIAL_IFLOWCONTROL cdcuart_rxflowcontrol, /* rxflowcontrol */ +#endif +#ifdef CONFIG_SERIAL_DMA + NULL, /* dmasend */ + NULL, /* dmareceive */ + NULL, /* dmarxfree */ + NULL, /* dmatxavail */ #endif NULL, /* send */ cdcuart_txint, /* txinit */ -- GitLab From ec85425041396c87f636a3c4db4ca973d0ad1f38 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Sat, 17 Dec 2016 08:31:12 -0600 Subject: [PATCH 717/734] STM32: Fix some STM32F7 copy paste errors --- arch/arm/src/stm32/stm32_serial.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c index 644c810817..10919e878b 100644 --- a/arch/arm/src/stm32/stm32_serial.c +++ b/arch/arm/src/stm32/stm32_serial.c @@ -1945,11 +1945,11 @@ static int up_interrupt_common(struct up_dev_s *priv) static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { #if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \ - || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT) + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; #endif -#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT) +#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #endif int ret = OK; -- GitLab From 8de11278992a196589af689c88fe1495015a1f35 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 17 Dec 2016 09:07:24 -0600 Subject: [PATCH 718/734] Xtensa ESP32: Using wrong register to disable interrupts. --- arch/Kconfig | 1 + arch/xtensa/src/common/xtensa_vectors.S | 8 ++++---- arch/xtensa/src/esp32/esp32_serial.c | 20 +++++++++++++------- 3 files changed, 18 insertions(+), 11 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index 1e26db617f..7685a2182d 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -77,6 +77,7 @@ config ARCH_X86 config ARCH_XTENSA bool "Xtensa" + select ARCH_HAVE_CUSTOMOPT ---help--- Cadence® Tensilica® Xtensa® actictures. diff --git a/arch/xtensa/src/common/xtensa_vectors.S b/arch/xtensa/src/common/xtensa_vectors.S index 39ccf8ac67..e0c462e7e1 100644 --- a/arch/xtensa/src/common/xtensa_vectors.S +++ b/arch/xtensa/src/common/xtensa_vectors.S @@ -203,7 +203,7 @@ _xtensa_nmi_vector: s32i a0, sp, (4 * REG_A0) s32i a2, sp, (4 * REG_A2) - movi a2, XTENSA_NMI_EXCEPTION /* Address of state save on stack */ + movi a2, XTENSA_NMI_EXCEPTION /* Argument 1: Error code */ call0 _xtensa_panic /* Does not return */ #else @@ -245,7 +245,7 @@ _debug_exception_vector: s32i a0, sp, (4 * REG_A0) s32i a2, sp, (4 * REG_A2) - movi a2, XTENSA_DEBUG_EXCEPTION /* Address of state save on stack */ + movi a2, XTENSA_DEBUG_EXCEPTION /* Argument 1: Error code */ call0 _xtensa_panic /* Does not return */ .end literal_prefix @@ -284,7 +284,7 @@ _double_exception_vector: s32i a0, sp, (4 * REG_A0) s32i a2, sp, (4 * REG_A2) - movi a2, XTENSA_DOUBLE_EXCEPTION /* Address of state save on stack */ + movi a2, XTENSA_DOUBLE_EXCEPTION /* Argument 1: Error code */ call0 _xtensa_panic /* Does not return */ .end literal_prefix @@ -321,7 +321,7 @@ _kernel_exception_vector: s32i a0, sp, (4 * REG_A0) s32i a2, sp, (4 * REG_A2) - movi a2, XTENSA_KERNEL_EXCEPTION /* Address of state save on stack */ + movi a2, XTENSA_KERNEL_EXCEPTION /* Argument 1: Error code */ call0 _xtensa_panic /* Does not return */ .end literal_prefix diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c index 8d1069cb03..936f161da2 100644 --- a/arch/xtensa/src/esp32/esp32_serial.c +++ b/arch/xtensa/src/esp32/esp32_serial.c @@ -1047,8 +1047,11 @@ static int esp32_receive(struct uart_dev_s *dev, unsigned int *status) static void esp32_rxint(struct uart_dev_s *dev, bool enable) { struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; + irqstate_t flags; int regval; + flags = enter_critical_section(); + if (enable) { /* Receive an interrupt when their is anything in the Rx data register (or an Rx @@ -1066,10 +1069,13 @@ static void esp32_rxint(struct uart_dev_s *dev, bool enable) { /* Disable the RX interrupts */ - esp32_serialout(priv, UART_INT_CLR_OFFSET, - (UART_RXFIFO_FULL_INT_CLR_S | UART_FRM_ERR_INT_CLR_S | - UART_RXFIFO_TOUT_INT_CLR_S)); + regval = esp32_serialin(priv, UART_INT_ENA_OFFSET); + regval &= ~(UART_RXFIFO_FULL_INT_CLR_S | UART_FRM_ERR_INT_CLR_S | + UART_RXFIFO_TOUT_INT_CLR_S); + esp32_serialout(priv, UART_INT_ENA_OFFSET, regval); } + + leave_critical_section(flags); } /**************************************************************************** @@ -1114,13 +1120,12 @@ static void esp32_txint(struct uart_dev_s *dev, bool enable) { struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; irqstate_t flags; + int regval; flags = enter_critical_section(); if (enable) { - uint32_t regval; - /* Set to receive an interrupt when the TX holding register register * is empty */ @@ -1141,8 +1146,9 @@ static void esp32_txint(struct uart_dev_s *dev, bool enable) { /* Disable the TX interrupt */ - esp32_serialout(priv, UART_INT_CLR_OFFSET, - (UART_TX_DONE_INT_CLR_S | UART_TXFIFO_EMPTY_INT_CLR_S)); + regval = esp32_serialin(priv, UART_INT_ENA_OFFSET); + regval &= ~(UART_TX_DONE_INT_ENA_S | UART_TXFIFO_EMPTY_INT_ENA_S); + esp32_serialout(priv, UART_INT_ENA_OFFSET, regval); } leave_critical_section(flags); -- GitLab From 6b80e5f15fbe86a4d923ef29be45e6bead9092f9 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 17 Dec 2016 10:50:00 -0600 Subject: [PATCH 719/734] Xtensa ESP32: Fix clobbered a9 in co-processor context save/restore --- arch/xtensa/src/common/xtensa_coproc.S | 46 ++++++++++++++++---------- 1 file changed, 28 insertions(+), 18 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_coproc.S b/arch/xtensa/src/common/xtensa_coproc.S index 8b01063bf3..0e7b3bafa4 100644 --- a/arch/xtensa/src/common/xtensa_coproc.S +++ b/arch/xtensa/src/common/xtensa_coproc.S @@ -229,12 +229,15 @@ xtensa_coproc_savestate: */ ENTRY(16) + s32i a0, sp, LOCAL_OFFSET(1) /* Save return address */ /* Call _xtensa_coproc_savestate() with A2=address of co-processor * save area. */ call0 _xtensa_coproc_savestate + + l32i a0, sp, LOCAL_OFFSET(1) /* Recover return address */ RET(16) #else @@ -243,10 +246,11 @@ xtensa_coproc_savestate: * a13-a15. So only a13-a15 need be preserved. */ - ENTRY(16) - s32i a13, sp, LOCAL_OFFSET(1) - s32i a14, sp, LOCAL_OFFSET(2) - s32i a15, sp, LOCAL_OFFSET(3) + ENTRY(24) + s32i a0, sp, LOCAL_OFFSET(1) /* Save return address */ + s32i a13, sp, LOCAL_OFFSET(2) + s32i a14, sp, LOCAL_OFFSET(3) + s32i a15, sp, LOCAL_OFFSET(4) /* Call _xtensa_coproc_savestate() with A2=address of co-processor * save area. @@ -256,11 +260,12 @@ xtensa_coproc_savestate: /* Restore a13-15 and return */ - l32i a13, sp, LOCAL_OFFSET(1) - l32i a14, sp, LOCAL_OFFSET(2) - l32i a15, sp, LOCAL_OFFSET(3) + l32i a0, sp, LOCAL_OFFSET(1) /* Recover return address */ + l32i a13, sp, LOCAL_OFFSET(2) + l32i a14, sp, LOCAL_OFFSET(3) + l32i a15, sp, LOCAL_OFFSET(4) - RET(16) + RET(24) #endif @@ -424,12 +429,15 @@ xtensa_coproc_restorestate: */ ENTRY(16) + s32i a0, sp, LOCAL_OFFSET(1) /* Save return address */ /* Call _xtensa_coproc_restorestate() with A2=address of co-processor - * save area. + * save area. Registers a0, a2-a7, a13-a15 have been trashed. */ call0 _xtensa_coproc_restorestate + + l32i a0, sp, LOCAL_OFFSET(1) /* Recover return address */ RET(16) #else @@ -438,24 +446,26 @@ xtensa_coproc_restorestate: * a13-a15. So only a13-a15 need be preserved. */ - ENTRY(16) - s32i a13, sp, LOCAL_OFFSET(1) - s32i a14, sp, LOCAL_OFFSET(2) - s32i a15, sp, LOCAL_OFFSET(3) + ENTRY(24) + s32i a0, sp, LOCAL_OFFSET(1) /* Save return address */ + s32i a13, sp, LOCAL_OFFSET(2) + s32i a14, sp, LOCAL_OFFSET(3) + s32i a15, sp, LOCAL_OFFSET(4) /* Call _xtensa_coproc_restorestate() with A2=address of co-processor - * save area. + * save area. Registers a0, a2-a7, a13-a15 have been trashed. */ call0 _xtensa_coproc_restorestate /* Restore a13-15 and return */ - l32i a13, sp, LOCAL_OFFSET(1) - l32i a14, sp, LOCAL_OFFSET(2) - l32i a15, sp, LOCAL_OFFSET(3) + l32i a0, sp, LOCAL_OFFSET(1) /* Recover return address */ + l32i a13, sp, LOCAL_OFFSET(2) + l32i a14, sp, LOCAL_OFFSET(3) + l32i a15, sp, LOCAL_OFFSET(4) - RET(16) + RET(24) #endif -- GitLab From a88c50d366423bdfa13e69d7329130628984b465 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 17 Dec 2016 10:51:04 -0600 Subject: [PATCH 720/734] Xtensa ESP32: Need to clone some logic for syncrhonous context switch. Window spill logic in the conmon restores logic is inappropriate in this context --- arch/xtensa/src/common/xtensa_context.S | 59 ++++++++++++++++++++++--- 1 file changed, 52 insertions(+), 7 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index 10d772c12d..2a74173864 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -218,26 +218,71 @@ _xtensa_context_save: xtensa_context_save: ENTRY(16) - /* Set up for call to _xtensa_context_save() */ - rsr a12, PS /* Save callee's PS */ - s32i a12, a2, (4 * REG_PS) + /* Set up for (potential) call to _xtensa_context_save() */ + + s32i a3, a2, (4 * REG_A3) /* Get scratch register */ + rsr a3, PS /* Save callee's PS */ + s32i a3, a2, (4 * REG_PS) s32i a0, a2, (4 * REG_PC) /* Save Return address as PC */ s32i a0, a2, (4 * REG_A0) /* Save callee's a0 */ s32i sp, a2, (4 * REG_A1) /* Save callee's SP */ - movi a12, 1 /* Set saved A2 to 1 */ - s32i a12, a2, (4 * REG_A2) + movi a3, 1 /* Set saved A2 to 1 */ + s32i a3, a2, (4 * REG_A2) - /* Save the rest of the processor state */ + /* Save the rest of the processor state. For the CALL0 ABI, we can user + * _xtensa_context_save(), Otherwise we duplicate the context save here + * to avoid the window spill. + */ +#ifdef __XTENSA_CALL0_ABI__ + l32i r3, a2, (4 * REG_A3) /* Recover original a3 */ call0 _xtensa_context_save /* Save full register state */ /* Recover the return address and return zero */ l32i a0, a2, (4 * REG_A0) /* Recover return addess */ - movi a2, 0 /* Return zero */ +#else + /* REVISIT: We could save a lot here. It should not be necessary to + * preserve all of these registers. The ABI permits volatile, callee- + * saved, registers to be clobbered on function calls. We save the + * whole tamale here mostly for debug purposes. + * + * NOTE that PS, PC and registers 0-3 were saved above. a0 is not + * modified. + */ + + s32i a4, a2, (4 * REG_A4) + s32i a5, a2, (4 * REG_A5) + s32i a6, a2, (4 * REG_A6) + s32i a7, a2, (4 * REG_A7) + s32i a8, a2, (4 * REG_A8) + s32i a9, a2, (4 * REG_A9) + s32i a10, a2, (4 * REG_A10) + s32i a11, a2, (4 * REG_A11) + + /* Call0 ABI callee-saved regs a12-15 */ + + s32i a12, a2, (4 * REG_A12) + s32i a13, a2, (4 * REG_A13) + s32i a14, a2, (4 * REG_A14) + s32i a15, a2, (4 * REG_A15) + rsr a3, SAR + s32i a3, a2, (4 * REG_SAR) + +#ifdef XCHAL_HAVE_LOOPS + rsr a3, LBEG + s32i a3, a2, (4 * REG_LBEG) + rsr a3, LEND + s32i a3, a2, (4 * REG_LEND) + rsr a3, LCOUNT + s32i a3, a2, (4 * REG_LCOUNT) +#endif +#endif + + movi a2, 0 /* Return zero */ RET(16) .size xtensa_context_save, . - xtensa_context_save -- GitLab From 93e6d16f756fbab42b856368a3a16567f2b9139b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 17 Dec 2016 11:23:10 -0600 Subject: [PATCH 721/734] Xtensa ESP32: wsr, not rsr. --- arch/xtensa/src/common/xtensa_context.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index 2a74173864..0eb9a468a2 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -415,7 +415,7 @@ xtensa_context_restore: l32i a0, a2, (4 * REG_PS) /* Restore PS */ wsr a0, PS l32i a0, a2, (4 * REG_PC) /* Set up for RFE */ - rsr a0, EPC_1 + wsr a0, EPC_1 l32i a0, a2, (4 * REG_A0) /* Restore a0 */ l32i a2, a2, (4 * REG_A2) /* Restore A2 */ -- GitLab From 7be1b86a81a2b875f70f33ae8b6b8751d264f125 Mon Sep 17 00:00:00 2001 From: "Author: Aleksandr Vyhovanec" Date: Sat, 17 Dec 2016 14:39:19 -0600 Subject: [PATCH 722/734] Add scansets to the scanf function. Enabled CONFIG_LIBC_SCANSET option. --- libc/Kconfig | 6 ++ libc/stdio/lib_sscanf.c | 220 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 226 insertions(+) diff --git a/libc/Kconfig b/libc/Kconfig index 757b115d81..c33aa553e5 100644 --- a/libc/Kconfig +++ b/libc/Kconfig @@ -61,6 +61,12 @@ config LIBC_LONG_LONG libraries that will be drawn into the build if long long support is enabled. +config LIBC_SCANSET + default "Scanset support" + default n + ---help--- + Add scanset support to sscanf(). + config LIBC_IOCTL_VARIADIC bool "Enable variadic ioctl()" default n diff --git a/libc/stdio/lib_sscanf.c b/libc/stdio/lib_sscanf.c index 0bc413295b..fcbdb941b8 100644 --- a/libc/stdio/lib_sscanf.c +++ b/libc/stdio/lib_sscanf.c @@ -134,6 +134,153 @@ static int findwidth(FAR const char *buf, FAR const char *fmt) return strcspn(buf, spaces); } +/**************************************************************************** + * Function: findscanset + * + * Description: + * Fill in the given table from the scanset at the given format. + * Return a pointer to the character the closing ']'. + * The table has a 1 wherever characters should be considered part of the + * scanset. + ****************************************************************************/ + +#ifdef CONFIG_LIBC_SCANSET +static FAR const char *findscanset(FAR const char *fmt, + FAR unsigned char set[32]) +{ + int c; + int n; + int v; + + fmt++; /* Skip '[' */ + + /* first `clear' the whole table */ + + c = *fmt++; /* First char hat => negated scanset */ + if (c == '^') + { + v = 1; /* Default => accept */ + c = *fmt++; /* Get new first char */ + } + else + { + v = 0; /* Default => reject */ + } + + memset(set, 0, 32); + if (c == 0) + { + goto doexit; + } + + /* Now set the entries corresponding to the actual scanset + * to the opposite of the above. + * + * The first character may be ']' (or '-') without being special; + * the last character may be '-'. + */ + + for (;;) + { + set[c / 8] |= (1 << (c % 8)); /* take character c */ + +doswitch: + n = *fmt++; /* and examine the next */ + switch (n) + { + case 0: /* format ended too soon */ + case ']': /* end of scanset */ + goto doexit; + + case '-': + /* A scanset of the form + * + * [01+-] + * + * is defined as "the digit 0, the digit 1, the character +, the + * character -", but the effect of a scanset such as + * + * [a-zA-Z0-9] + * + * is implementation defined. The V7 Unix scanf treats "a-z" as + * "the letters a through z", but treats "a-a" as "the letter a, + * the character -, and the letter a". + * + * For compatibility, the `-' is not considerd to define a range + * if the character following it is either a close bracket + * (required by ANSI) or is not numerically greater than the + * character* we just stored in the table (c). + */ + + n = *fmt; + if (n == ']' || n < c) + { + c = '-'; + break; /* resume the for(;;) */ + } + + fmt++; + do + { + /* Fill in the range */ + + c++; + set[c / 8] |= (1 << (c % 8)); /* Take character c */ + } + while (c < n); + + /* Alas, the V7 Unix scanf also treats formats such as [a-c-e] as + * "the letters a through e". This too is permitted by the + * standard. + */ + + goto doswitch; + + default: /* just another character */ + c = n; + break; + } + } + +doexit: + if (v) /* default => accept */ + { + for (int i = 0; i < 32; i++) /* invert all */ + { + set[i] ^= 0xFF; + } + } + + return (fmt - 1); +} +#endif + +/**************************************************************************** + * Function: scansetwidth + ****************************************************************************/ + +#ifdef CONFIG_LIBC_SCANSET +static int scansetwidth(FAR const char *buf, + FAR const unsigned char set[32]) +{ + FAR const char *next = buf; + int c; + + while (*next) + { + c = *next; + if ((set[c / 8] & (1 << (c % 8))) == 0) + { + break; + } + + next++; + } + + return (next - buf); +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -177,6 +324,9 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) int fwidth; int base = 10; char tmp[MAXLN]; +#ifdef CONFIG_LIBC_SCANSET + unsigned char set[32]; /* Bit field (256 / 8) */ +#endif linfo("vsscanf: buf=\"%s\" fmt=\"%s\"\n", buf, fmt); @@ -220,7 +370,11 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) { linfo("vsscanf: Processing %c\n", *fmt); +#ifdef CONFIG_LIBC_SCANSET + if (strchr("dibouxcsefgn[%", *fmt)) +#else if (strchr("dibouxcsefgn%", *fmt)) +#endif { break; } @@ -307,6 +461,72 @@ int vsscanf(FAR const char *buf, FAR const char *fmt, va_list ap) } } +#ifdef CONFIG_LIBC_SCANSET + /* Process %[: Scanset conversion */ + + if (*fmt == '[') + { + linfo("vsscanf: Performing scanset conversion\n"); + + fmt = findscanset(fmt, set); /* find scanset */ + + /* Get a pointer to the char * value. We need to do this even + * if we have reached the end of the input data in order to + * update the 'ap' variable. + */ + + tv = NULL; /* To avoid warnings about begin uninitialized */ + if (!noassign) + { + tv = va_arg(ap, FAR char *); + tv[0] = '\0'; + } + + /* But we only perform the data conversion is we still have + * bytes remaining in the input data stream. + */ + + if (*buf) + { + /* Skip over white space */ + + while (isspace(*buf)) + { + buf++; + } + + /* Guess a field width using some heuristics */ + + fwidth = scansetwidth(buf, set); + + /* Use the actual field's width if 1) no fieldwidth + * specified or 2) the actual field's width is smaller + * than fieldwidth specified + */ + + if (!width || fwidth < width) + { + width = fwidth; + } + + width = MIN(sizeof(tmp) - 1, width); + + /* Copy the string (if we are making an assignment) */ + + if (!noassign) + { + strncpy(tv, buf, width); + tv[width] = '\0'; + count++; + } + + /* Update the buffer pointer past the string in the input */ + + buf += width; + } + } +#endif + /* Process %c: Character conversion */ else if (*fmt == 'c') -- GitLab From 8ce1fdaab026e4555303c74c125870562f2570e2 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 17 Dec 2016 16:18:04 -0600 Subject: [PATCH 723/734] Add an attribution to the scanset addition to sscanf() --- libc/stdio/lib_sscanf.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/libc/stdio/lib_sscanf.c b/libc/stdio/lib_sscanf.c index fcbdb941b8..24d3c6d184 100644 --- a/libc/stdio/lib_sscanf.c +++ b/libc/stdio/lib_sscanf.c @@ -142,6 +142,10 @@ static int findwidth(FAR const char *buf, FAR const char *fmt) * Return a pointer to the character the closing ']'. * The table has a 1 wherever characters should be considered part of the * scanset. + * + * Function findscanset based on source function __sccl of FreeBSD + * (https://github.com/lattera/freebsd/blob/master/sys/kern/subr_scanf.c) + * ****************************************************************************/ #ifdef CONFIG_LIBC_SCANSET -- GitLab From 586f0aab503b9bfc7a464158ce81371965f99148 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 18 Dec 2016 10:07:34 -0600 Subject: [PATCH 724/734] Fix context save logic when called in window ABI configuration. Add an IDLE stack. Don't depend on the mystery stack received from the bootloader. --- arch/xtensa/src/common/xtensa.h | 34 ++++- arch/xtensa/src/common/xtensa_context.S | 149 ++++++++++++++++++++-- arch/xtensa/src/common/xtensa_dumpstate.c | 22 ++-- arch/xtensa/src/esp32/esp32_irq.c | 2 +- arch/xtensa/src/esp32/esp32_start.c | 23 +++- 5 files changed, 196 insertions(+), 34 deletions(-) diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index 9cf4778e54..20c67fc6d0 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -104,10 +104,30 @@ /* Check if an interrupt stack size is configured */ -#ifndef CONFIG_ARCH_INTERRUPTSTACK -# define CONFIG_ARCH_INTERRUPTSTACK 0 +#define HAVE_INTERRUPTSTACK 1 + +#if !defined(CONFIG_ARCH_INTERRUPTSTACK) +# define CONFIG_ARCH_INTERRUPTSTACK 0 +# undef HAVE_INTERRUPTSTACK +#elif CONFIG_ARCH_INTERRUPTSTACK < 16 +# warning CONFIG_ARCH_INTERRUPTSTACK is to small +# undef HAVE_INTERRUPTSTACK #endif +#define INTERRUPTSTACK_SIZE ((CONFIG_ARCH_INTERRUPTSTACK + 15) & ~15) +#define INTERRUPT_STACKWORDS (INTERRUPTSTACK_SIZE >> 2) + +/* An IDLE thread stack size for CPU0 must be defined */ + +#if !defined(CONFIG_IDLETHREAD_STACKSIZE) +# error CONFIG_IDLETHREAD_STACKSIZE is not defined +#elif CONFIG_IDLETHREAD_STACKSIZE < 16 +# error CONFIG_IDLETHREAD_STACKSIZE is to small +#endif + +#define IDLETHREAD_STACKSIZE ((CONFIG_IDLETHREAD_STACKSIZE + 15) & ~15) +#define IDLETHREAD_STACKWORDS (IDLETHREAD_STACKSIZE >> 2) + /* Used for stack usage measurements */ #define STACK_COLOR 0xdeadbeef @@ -180,12 +200,16 @@ extern volatile uint32_t *g_current_regs[1]; #endif -/* Address of the saved user stack pointer */ +#ifdef HAVE_INTERRUPTSTACK +/* The (optional) interrupt stack */ -#if CONFIG_ARCH_INTERRUPTSTACK > 3 -extern void g_intstackbase; +extern uint32_t g_intstack[INTERRUPT_STACKWORDS]; #endif +/* Address of the CPU0 IDLE thread */ + +extern uint32_t g_idlestack[IDLETHREAD_STACKWORDS]; + /* These 'addresses' of these values are setup by the linker script. They are * not actual uint32_t storage locations! They are only used meaningfully in the * following way: diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index 0eb9a468a2..7f6d074d6d 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -182,8 +182,6 @@ _xtensa_context_save: * * Description: * - * NOTE: MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION! - * * This functions implements the moral equivalent of setjmp(). It is * called from user code (with interrupts disabled) to save the current * state of the running thread. This function always returns zero. @@ -206,6 +204,24 @@ _xtensa_context_save: * Assumptions: * - Interrupts are disabled. * + ****************************************************************************/ + +#ifdef __XTENSA_CALL0_ABI__ + +/**************************************************************************** + * Name: xtensa_context_save: + * + * Description: + * This implementation of xtensa_context_save for the case of the CALL0 ABI + * + * Input State: + * a0 = The return value to the caller. + * a2 = The address of the register state state structure + * + * Return state: + * a0 = The return value to the caller. + * a2, a12-a15 preserved as at entry + * ****************************************************************************/ .global xtensa_context_save @@ -218,7 +234,6 @@ _xtensa_context_save: xtensa_context_save: ENTRY(16) - /* Set up for (potential) call to _xtensa_context_save() */ s32i a3, a2, (4 * REG_A3) /* Get scratch register */ @@ -236,24 +251,79 @@ xtensa_context_save: * to avoid the window spill. */ -#ifdef __XTENSA_CALL0_ABI__ l32i r3, a2, (4 * REG_A3) /* Recover original a3 */ call0 _xtensa_context_save /* Save full register state */ /* Recover the return address and return zero */ l32i a0, a2, (4 * REG_A0) /* Recover return addess */ -#else - /* REVISIT: We could save a lot here. It should not be necessary to + movi a2, 0 /* Return zero */ + RET(16) + + .size xtensa_context_save, . - xtensa_context_save +#endif + +/**************************************************************************** + * This implementation of xtensa_context_save for the case of the window ABI. + * This case is more complex. For the Window ABI, there is a "hook" that + * performs the low level state state. xtensa_context_save() is a simply + * trampoline function that performs the window oeprations in that + * configuration. + ****************************************************************************/ + +#ifndef __XTENSA_CALL0_ABI__ + +/**************************************************************************** + * Name: _xtensa_save_hook: + * + * Input State: + * True return value has already been saved + * a0 = The return value into xtensa_context_save() + * a2 = The address of the register state state structure + * + * Return state: + * a0, a3 modified. + * Other values as on entry + * Returned value is in a3 (non-stanadard) + * + ****************************************************************************/ + + .type _xtensa_save_hook, @function + + .align 4 + .literal_position + .align 4 + +_xtensa_save_hook: + + /* Save the return value of 1 that will be used when returning from a + * context switch. NOTE that the returned value from this function is + * expected in a3 (not the usual a2). This also frees up a3 for a use + * as a scratch register. + */ + + movi a3, 1 /* Set saved a3 to 1 */ + s32i a3, a2, (4 * REG_A3) + + /* Save the rest of the processor state. + * + * REVISIT: We could save a lot here. It should not be necessary to * preserve all of these registers. The ABI permits volatile, callee- * saved, registers to be clobbered on function calls. We save the * whole tamale here mostly for debug purposes. * - * NOTE that PS, PC and registers 0-3 were saved above. a0 is not - * modified. + * NOTE that a3 was saved above. The true a0 return value was saved + * in xtensa_context_save. The a0 value saved below is the return into + * xtensa_context_save. */ - s32i a4, a2, (4 * REG_A4) + rsr a3, PS /* Save callee's PS */ + s32i a3, a2, (4 * REG_PS) + s32i a0, a2, (4 * REG_PC) /* Save Return address as PC */ + + s32i sp, a2, (4 * REG_A1) /* Save callee's SP */ + s32i a2, a2, (4 * REG_A2) + s32i a4, a2, (4 * REG_A4) /* Save remaining registers */ s32i a5, a2, (4 * REG_A5) s32i a6, a2, (4 * REG_A6) s32i a7, a2, (4 * REG_A7) @@ -279,13 +349,68 @@ xtensa_context_save: s32i a3, a2, (4 * REG_LEND) rsr a3, LCOUNT s32i a3, a2, (4 * REG_LCOUNT) -#endif #endif - movi a2, 0 /* Return zero */ + /* NOTE that the returned value is through a3 */ + + movi a3, 0 /* Return zero, no context switch */ + ret + + .size _xtensa_save_hook, . - _xtensa_save_hook + +/**************************************************************************** + * Name: xtensa_context_save: + * + * Description: + * This is the implementation of xtensa_context_save for the case of the + * window ABI. In the window ABI configuration, xtensa_context_save is a + * thin "trampoline" layer. It performs the ENTRY window operations on + * entry and the exit. A call0 is used to force the retun from the context + * switch to the window return within this trampoline. + * + * Input State: + * a0 = The true return value to the caller. + * a2 = The address of the register state state structure + * + * Return state: + * a0, a2, and a3 modified. + * Returned value is in a2 + * + ****************************************************************************/ + + .global xtensa_context_save + .type xtensa_context_save, @function + + .align 4 + .literal_position + .align 4 + +xtensa_context_save: + ENTRY(16) + + /* Save the true return address in the register save structure (a0). */ + + s32i a0, a2, (4 * REG_A0) /* Save true return address (a0) */ + + /* Then perform the actual state save in _xtensa_save_hook. The saved + * EPC will be set to the return from this function then we will do the + * RET(16) window fix-up. + */ + + call0 _xtensa_save_hook /* Save full register state */ + + /* a0 and a2 will be automatically restored in the context switch case + * with a3=1. In the non-context switch return with a2=0, a2 will still + * be valid, but we have to restore a0 ourself. The following should + * work in either case. + */ + + l32i a0, a2, (4 * REG_A0) /* Recover the true return address (a0) */ + mov a2, a3 /* Move a3 to the correct register for return */ RET(16) .size xtensa_context_save, . - xtensa_context_save +#endif /**************************************************************************** * Name: _xtensa_context_restore @@ -371,8 +496,6 @@ _xtensa_context_restore: * * Description: * - * NOTE: MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION! - * * This functions implements the moral equivalent of longjmp(). It is * called from user code (with interrupts disabled) to restor the current * state of the running thread. This function always appears to be a diff --git a/arch/xtensa/src/common/xtensa_dumpstate.c b/arch/xtensa/src/common/xtensa_dumpstate.c index 9e0af50e81..d470c937ea 100644 --- a/arch/xtensa/src/common/xtensa_dumpstate.c +++ b/arch/xtensa/src/common/xtensa_dumpstate.c @@ -150,7 +150,7 @@ void xtensa_dumpstate(void) uint32_t sp = xtensa_getsp(); uint32_t ustackbase; uint32_t ustacksize; -#if CONFIG_ARCH_INTERRUPTSTACK > 3 +#ifdef HAVE_INTERRUPTSTACK uint32_t istackbase; uint32_t istacksize; #endif @@ -165,14 +165,8 @@ void xtensa_dumpstate(void) if (rtcb->pid == 0) { -#warning REVISIT: Need top of IDLE stack -#if 0 - ustackbase = g_idle_topstack - 4; - ustacksize = CONFIG_IDLETHREAD_STACKSIZE; -#else - ustackbase = sp + 128; - ustacksize = 256; -#endif + ustackbase = (uint32_t)&g_idlestack[IDLETHREAD_STACKWORDS-1]; + ustacksize = IDLETHREAD_STACKSIZE; } else { @@ -183,9 +177,9 @@ void xtensa_dumpstate(void) /* Get the limits on the interrupt stack memory */ #warning REVISIT interrupt stack -#if CONFIG_ARCH_INTERRUPTSTACK > 3 - istackbase = (uint32_t)&g_intstackbase; - istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4; +#ifdef HAVE_INTERRUPTSTACK + istackbase = (uint32_t)&g_intstack[INTERRUPT_STACKWORDS-1]; + istacksize = INTERRUPTSTACK_SIZE; /* Show interrupt stack info */ @@ -208,7 +202,7 @@ void xtensa_dumpstate(void) * at the base of the interrupt stack. */ - sp = g_intstackbase; + sp = &g_instack[INTERRUPTSTACK_SIZE - sizeof(uint32_t)]; _alert("sp: %08x\n", sp); } @@ -229,7 +223,7 @@ void xtensa_dumpstate(void) if (sp > ustackbase || sp <= ustackbase - ustacksize) { -#if !defined(CONFIG_ARCH_INTERRUPTSTACK) || CONFIG_ARCH_INTERRUPTSTACK < 4 +#ifdef HAVE_INTERRUPTSTACK _alert("ERROR: Stack pointer is not within allocated stack\n"); #endif } diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c index 351e50b568..11c43a4a1c 100644 --- a/arch/xtensa/src/esp32/esp32_irq.c +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -141,7 +141,7 @@ void xtensa_irq_initialize(void) (void)esp32_cpuint_initialize(); -#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 +#if defined(CONFIG_STACK_COLORATION) && defined(HAVE_INTERRUPTSTACK) /* Colorize the interrupt stack for debug purposes */ #warning Missing logic diff --git a/arch/xtensa/src/esp32/esp32_start.c b/arch/xtensa/src/esp32/esp32_start.c index a468e83a9c..0bf47460d6 100644 --- a/arch/xtensa/src/esp32/esp32_start.c +++ b/arch/xtensa/src/esp32/esp32_start.c @@ -34,13 +34,23 @@ #include +#include "xtensa.h" #include "xtensa_attr.h" + #include "chip/esp32_dport.h" #include "chip/esp32_rtccntl.h" #include "esp32_clockconfig.h" #include "esp32_region.h" #include "esp32_start.h" -#include "xtensa.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Address of the CPU0 IDLE thread */ + +uint32_t g_idlestack[IDLETHREAD_STACKWORDS] + __attribute__((aligned(16) section(".noinit"))); /**************************************************************************** * Public Functions @@ -62,6 +72,7 @@ void IRAM_ATTR __start(void) { uint32_t regval; + uint32_t sp; /* Kill the watchdog timer */ @@ -73,6 +84,15 @@ void IRAM_ATTR __start(void) regval &= ~(1 << 14); putreg32(regval, 0x6001f048); + /* Move the stack to a known location. Although we were give a stack + * pointer at start-up, we don't know where that stack pointer is positioned + * respect to our memory map. The only safe option is to switch to a well- + * known IDLE thread stack. + */ + + sp = (uint32_t)g_idlestack + IDLETHREAD_STACKSIZE; + __asm__ __volatile__("mov sp, %0\n" : : "r"(sp)); + /* Make page 0 access raise an exception */ esp32_region_protection(); @@ -108,4 +128,5 @@ void IRAM_ATTR __start(void) /* Bring up NuttX */ os_start(); + for(; ; ); /* Should not return */ } -- GitLab From 665c1647b5bd909e21524c656cd794c87a99771b Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 18 Dec 2016 12:54:47 -0600 Subject: [PATCH 725/734] Xtensa ESP32: Need to spill registers to memory as the last dying action before switching to a new thread. --- arch/xtensa/src/common/xtensa_context.S | 31 ++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index 7f6d074d6d..9084f9bf31 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -529,7 +529,36 @@ _xtensa_context_restore: xtensa_context_restore: ENTRY(16) /* REVISIT */ - /* Restore the processor state */ + /* Force a spill of the live registers of the thread that has been + * suspended. + * + * _xtensa_window_spill return state: + * a2, a3: clobbered + * a4,a5,a8,a9,a12,a13: preserved + * a6,a7,a10,a11,a14,a15 clobbered if they were part of window(s) + * to be spilled, otherwise they are the same as on entry + * loop registers: Perserved + * SAR: clobbered + * + * We need to preserve only a2 for _xtensa_context_restore + */ + + mov a4, a2 /* Save a2 in a preserved register */ + rsr a5, PS /* Save PS in preserved register */ + + movi a3, ~(PS_WOE_MASK | PS_INTLEVEL_MASK) + and a2, a5, a3 /* Clear WOE, INTLEVEL */ + addi a2, a2, XCHAL_EXCM_LEVEL /* Set INTLEVEL = XCHAL_EXCM_LEVEL */ + wsr a2, PS /* Apply to PS */ + rsync + + call0 _xtensa_window_spill + wsr a5, PS /* Restore PS */ + rsync + + mov a2, a4 /* Recover a2 */ + + /* Restore the processor state for the newly started thread */ call0 _xtensa_context_restore /* Restore full register state */ -- GitLab From 4bd530d026c0dc8af0c20371aac993b881c81fbc Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 18 Dec 2016 13:17:31 -0600 Subject: [PATCH 726/734] Xtensa ESP32: Last change should be conditioned on the window ABI. --- arch/xtensa/src/common/xtensa_context.S | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index 9084f9bf31..aa0306cb5a 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -527,8 +527,9 @@ _xtensa_context_restore: .align 4 xtensa_context_restore: - ENTRY(16) /* REVISIT */ + ENTRY(16) +#ifndef __XTENSA_CALL0_ABI__ /* Force a spill of the live registers of the thread that has been * suspended. * @@ -557,6 +558,7 @@ xtensa_context_restore: rsync mov a2, a4 /* Recover a2 */ +#endif /* Restore the processor state for the newly started thread */ -- GitLab From 71bb79a6c7449c0590dfcc7f1564c4fae6759a51 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 18 Dec 2016 15:11:34 -0600 Subject: [PATCH 727/734] ESP32 Serial: Fix some register bit definitions. --- arch/xtensa/src/esp32/esp32_serial.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c index 936f161da2..9848783e6e 100644 --- a/arch/xtensa/src/esp32/esp32_serial.c +++ b/arch/xtensa/src/esp32/esp32_serial.c @@ -759,9 +759,9 @@ static int esp32_interrupt(struct uart_dev_s *dev) /* Clear pending interrupts */ - regval = (UART_RXFIFO_FULL_INT_CLR_S | UART_FRM_ERR_INT_CLR_S | - UART_RXFIFO_TOUT_INT_CLR_S | UART_TX_DONE_INT_CLR_S | - UART_TXFIFO_EMPTY_INT_CLR_S); + regval = (UART_RXFIFO_FULL_INT_CLR | UART_FRM_ERR_INT_CLR | + UART_RXFIFO_TOUT_INT_CLR | UART_TX_DONE_INT_CLR | + UART_TXFIFO_EMPTY_INT_CLR); esp32_serialout(priv, UART_INT_CLR_OFFSET, regval); if ((status & UART_RXFIFO_CNT_M) > 0) @@ -1060,8 +1060,8 @@ static void esp32_rxint(struct uart_dev_s *dev, bool enable) #ifndef CONFIG_SUPPRESS_SERIAL_INTS regval = esp32_serialin(priv, UART_INT_ENA_OFFSET); - regval |= (UART_RXFIFO_FULL_INT_CLR_S | UART_FRM_ERR_INT_CLR_S | - UART_RXFIFO_TOUT_INT_CLR_S); + regval |= (UART_RXFIFO_FULL_INT_ENA | UART_FRM_ERR_INT_ENA | + UART_RXFIFO_TOUT_INT_ENA); esp32_serialout(priv, UART_INT_ENA_OFFSET, regval); #endif } @@ -1070,8 +1070,8 @@ static void esp32_rxint(struct uart_dev_s *dev, bool enable) /* Disable the RX interrupts */ regval = esp32_serialin(priv, UART_INT_ENA_OFFSET); - regval &= ~(UART_RXFIFO_FULL_INT_CLR_S | UART_FRM_ERR_INT_CLR_S | - UART_RXFIFO_TOUT_INT_CLR_S); + regval &= ~(UART_RXFIFO_FULL_INT_ENA | UART_FRM_ERR_INT_ENA | + UART_RXFIFO_TOUT_INT_ENA); esp32_serialout(priv, UART_INT_ENA_OFFSET, regval); } @@ -1132,7 +1132,7 @@ static void esp32_txint(struct uart_dev_s *dev, bool enable) #ifndef CONFIG_SUPPRESS_SERIAL_INTS regval = esp32_serialin(priv, UART_INT_ENA_OFFSET); - regval |= (UART_TX_DONE_INT_ENA_S | UART_TXFIFO_EMPTY_INT_ENA_S); + regval |= (UART_TX_DONE_INT_ENA | UART_TXFIFO_EMPTY_INT_ENA); esp32_serialout(priv, UART_INT_ENA_OFFSET, regval); /* Fake a TX interrupt here by just calling uart_xmitchars() with @@ -1147,7 +1147,7 @@ static void esp32_txint(struct uart_dev_s *dev, bool enable) /* Disable the TX interrupt */ regval = esp32_serialin(priv, UART_INT_ENA_OFFSET); - regval &= ~(UART_TX_DONE_INT_ENA_S | UART_TXFIFO_EMPTY_INT_ENA_S); + regval &= ~(UART_TX_DONE_INT_ENA | UART_TXFIFO_EMPTY_INT_ENA); esp32_serialout(priv, UART_INT_ENA_OFFSET, regval); } -- GitLab From 2b0b698d729346b4545bbab120dcefe7b74fe4ae Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 18 Dec 2016 16:04:25 -0600 Subject: [PATCH 728/734] ESP32 Serial: Add logic to prevent infinite loops in interrupt handler. --- arch/xtensa/src/esp32/esp32_serial.c | 46 ++++++++++++++++++++-------- 1 file changed, 34 insertions(+), 12 deletions(-) diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c index 9848783e6e..3226895de7 100644 --- a/arch/xtensa/src/esp32/esp32_serial.c +++ b/arch/xtensa/src/esp32/esp32_serial.c @@ -146,7 +146,7 @@ struct esp32_config_s { - const uint32_t uartbase; /* Base address of UART registers */ + const uint32_t uartbase; /* Base address of UART registers */ xcpt_t handler; /* Interrupt handler */ uint8_t periph; /* UART peripheral ID */ uint8_t irq; /* IRQ number assigned to the peripheral */ @@ -740,6 +740,8 @@ static int esp32_interrupt(struct uart_dev_s *dev) struct esp32_dev_s *priv; uint32_t regval; uint32_t status; + uint32_t enabled; + unsigned int nfifo; int passes; bool handled; @@ -756,6 +758,7 @@ static int esp32_interrupt(struct uart_dev_s *dev) handled = false; priv->status = esp32_serialin(priv, UART_INT_RAW_OFFSET); status = esp32_serialin(priv, UART_STATUS_OFFSET); + enabled = esp32_serialin(priv, UART_INT_ENA_OFFSET); /* Clear pending interrupts */ @@ -764,20 +767,39 @@ static int esp32_interrupt(struct uart_dev_s *dev) UART_TXFIFO_EMPTY_INT_CLR); esp32_serialout(priv, UART_INT_CLR_OFFSET, regval); - if ((status & UART_RXFIFO_CNT_M) > 0) - { - /* Received data in the RXFIFO ... process incoming bytes */ + /* Are Rx interrupts enabled? The upper layer may hold off Rx input + * by disabling the Rx interrupts if there is no place to saved the + * data, possibly resulting in an overrun error. + */ - uart_recvchars(dev); - handled = true; - } + if ((enabled & (UART_RXFIFO_FULL_INT_ENA | UART_RXFIFO_TOUT_INT_ENA)) != 0) + { + /* Is there any data waiting in the Rx FIFO? */ - if ((status & UART_TXFIFO_CNT_M) < 0x7f) - { - /* The TXFIFO is not full ... process outgoing bytes */ + nfifo = (status & UART_RXFIFO_CNT_M) >> UART_RXFIFO_CNT_S; + if (nfifo > 0) + { + /* Received data in the RXFIFO! ... Process incoming bytes */ - uart_xmitchars(dev); - handled = true; + uart_recvchars(dev); + handled = true; + } + } + + /* Are Tx interrupts enabled? The upper layer will disable Tx interrupts + * when it has nothing to send. + */ + + if ((enabled & (UART_TX_DONE_INT_ENA | UART_TXFIFO_EMPTY_INT_ENA)) != 0) + { + nfifo = (status & UART_TXFIFO_CNT_M) >> UART_TXFIFO_CNT_S; + if (nfifo < 0x7f) + { + /* The TXFIFO is not full ... process outgoing bytes */ + + uart_xmitchars(dev); + handled = true; + } } } -- GitLab From b47255a6def3145c1e8f7104f79217ad8ad1599e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 18 Dec 2016 17:30:30 -0600 Subject: [PATCH 729/734] Update README. --- configs/esp32-core/README.txt | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/configs/esp32-core/README.txt b/configs/esp32-core/README.txt index 5e6df6662f..e7fe71aef4 100644 --- a/configs/esp32-core/README.txt +++ b/configs/esp32-core/README.txt @@ -226,8 +226,7 @@ SMP 3. Assertions. On a fatal assertions, other CPUs need to be stopped. - - for the ESP32 +OpenOCD for the ESP32 ===================== First you in need some debug environment which would be a JTAG emulator @@ -471,7 +470,13 @@ SMP Running from IRAM ----------------- - Running from IRAM is a good debug option. You should be able to load the ELF directly via JTAG in this case, and you may not need the bootloader. The one "gotcha" for needing the bootloader is disabling the initial watchdog, there is code in bootloader_start.c that does this. + *** SKIP this Section. It is not useful information and will take you down the wrong path. *** + *** See instead "Sample Debug Steps" below which is a really usale procedure. *** + + Running from IRAM is a good debug option. You should be able to load the + ELF directly via JTAG in this case, and you may not need the bootloader. The + one "gotcha" for needing the bootloader is disabling the initial watchdog, = + there is code in bootloader_start.c that does this. It is possible to skip the secondary bootloader and run out of IRAM using only the primary bootloader if your application of small enough (< 128KiB code, -- GitLab From 886ce88b4f0a932d1f25672b39440c353c6c0ba0 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 19 Dec 2016 09:43:16 -0600 Subject: [PATCH 730/734] Xtensa ESP32: Automatically mount /proc at start-up. --- arch/xtensa/src/common/xtensa_irqdispatch.c | 16 ++++----- arch/xtensa/src/common/xtensa_vectors.S | 7 +++- configs/esp32-core/nsh/defconfig | 39 +++++++++++++-------- configs/esp32-core/smp/defconfig | 38 ++++++++++++-------- configs/esp32-core/src/esp32_bringup.c | 22 ++++++++++++ 5 files changed, 85 insertions(+), 37 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_irqdispatch.c b/arch/xtensa/src/common/xtensa_irqdispatch.c index 2f05eab152..813846e76e 100644 --- a/arch/xtensa/src/common/xtensa_irqdispatch.c +++ b/arch/xtensa/src/common/xtensa_irqdispatch.c @@ -99,14 +99,14 @@ uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs) if (regs != CURRENT_REGS) { #if XCHAL_CP_NUM > 0 - /* If an interrupt level context switch has occurred, then save the - * co-processor state in in the suspended thread's co-processor save - * area. - * - * NOTE 1. The state of the co-processor has not been altered and - * still represents the to-be-suspended thread. - * NOTE 2. We saved a reference TCB of the original thread on entry. - */ + /* If an interrupt level context switch has occurred, then save the + * co-processor state in in the suspended thread's co-processor save + * area. + * + * NOTE 1. The state of the co-processor has not been altered and + * still represents the to-be-suspended thread. + * NOTE 2. We saved a reference TCB of the original thread on entry. + */ xtensa_coproc_savestate(&tcb->xcp.cpstate); diff --git a/arch/xtensa/src/common/xtensa_vectors.S b/arch/xtensa/src/common/xtensa_vectors.S index e0c462e7e1..9dfc4869f6 100644 --- a/arch/xtensa/src/common/xtensa_vectors.S +++ b/arch/xtensa/src/common/xtensa_vectors.S @@ -280,9 +280,14 @@ _double_exception_vector: s32i a0, sp, (4 * REG_PS) rsr a0, DEPC /* Save interruptee's PC */ s32i a0, sp, (4 * REG_PC) - rsr a0, EXCSAVE_1 /* Save interruptee's a0 -- REVISIT */ + rsr a0, EXCSAVE /* Save interruptee's a0 -- REVISIT */ s32i a0, sp, (4 * REG_A0) + rsr a0, EXCCAUSE /* Save the EXCCAUSE register */ + s32i a0, sp, (4 * REG_EXCCAUSE) + rsr a0, EXCVADDR /* Save the EXCVADDR register */ + s32i a0, sp, (4 * REG_EXCVADDR) + s32i a2, sp, (4 * REG_A2) movi a2, XTENSA_DOUBLE_EXCEPTION /* Argument 1: Error code */ call0 _xtensa_panic /* Does not return */ diff --git a/configs/esp32-core/nsh/defconfig b/configs/esp32-core/nsh/defconfig index ce5088bb99..deac6be6b6 100644 --- a/configs/esp32-core/nsh/defconfig +++ b/configs/esp32-core/nsh/defconfig @@ -51,8 +51,9 @@ CONFIG_DEBUG_ALERT=y # CONFIG_ARCH_HAVE_STACKCHECK is not set # CONFIG_ARCH_HAVE_HEAPCHECK is not set # CONFIG_DEBUG_SYMBOLS is not set -# CONFIG_ARCH_HAVE_CUSTOMOPT is not set +CONFIG_ARCH_HAVE_CUSTOMOPT=y # CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set CONFIG_DEBUG_FULLOPT=y # @@ -77,6 +78,10 @@ CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_FAMILY_LX6=y # CONFIG_XTENSA_USE_OVLY is not set CONFIG_XTENSA_CP_INITSET=0x0001 + +# +# ESP32 Peripheral Selection +# CONFIG_ESP32_UART=y # CONFIG_ESP32_SPI2 is not set # CONFIG_XTENSA_TIMER1 is not set @@ -84,24 +89,20 @@ CONFIG_ESP32_UART=y CONFIG_ESP32_UART0=y # CONFIG_ESP32_UART1 is not set # CONFIG_ESP32_UART2 is not set -CONFIG_ESP32_BT_RESERVE_DRAM=0 -CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0 -CONFIG_ESP32_ULP_COPROC_RESERVE_MEM=0 -# CONFIG_ESP32_GPIO_IRQ is not set -CONFIG_ESP32_UART0_TXPIN=0 -CONFIG_ESP32_UART0_RXPIN=0 - -# -# ESP32 Peripheral Selection -# # # Memory Configuration # +CONFIG_ESP32_BT_RESERVE_DRAM=0 +CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0 +CONFIG_ESP32_ULP_COPROC_RESERVE_MEM=0 +# CONFIG_ESP32_GPIO_IRQ is not set # # UART configuration # +CONFIG_ESP32_UART0_TXPIN=0 +CONFIG_ESP32_UART0_RXPIN=0 # # Architecture Options @@ -174,7 +175,11 @@ CONFIG_ESP32CORE_XTAL_40MZ=y # CONFIG_ESP32CORE_XTAL_26MHz is not set # CONFIG_ESP32CORE_RUN_IRAM is not set # CONFIG_BOARD_CRASHDUMP is not set -# CONFIG_LIB_BOARDCTL is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set # # RTOS Features @@ -205,6 +210,7 @@ CONFIG_PREALLOC_TIMERS=4 # # Tasks and Scheduling # +# CONFIG_SPINLOCK is not set # CONFIG_SMP is not set # CONFIG_INIT_NONE is not set CONFIG_INIT_ENTRYPOINT=y @@ -222,6 +228,8 @@ CONFIG_SCHED_WAITPID=y # # CONFIG_MUTEX_TYPES is not set CONFIG_NPTHREAD_KEYS=4 +# CONFIG_PTHREAD_CLEANUP is not set +# CONFIG_CANCELLATION_POINTS is not set # # Performance Monitoring @@ -536,6 +544,8 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_ARCH_ROMGETC is not set # CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set # CONFIG_ARCH_HAVE_TLS is not set +# CONFIG_LIBC_IPv4_ADDRCONV is not set +# CONFIG_LIBC_IPv6_ADDRCONV is not set # CONFIG_LIBC_NETDB is not set # CONFIG_NETDB_HOSTFILE is not set @@ -598,10 +608,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set @@ -623,6 +633,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_TIFF is not set # CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBSERIAL is not set # CONFIG_EXAMPLES_USBTERM is not set # CONFIG_EXAMPLES_WATCHDOG is not set # CONFIG_EXAMPLES_WEBSERVER is not set @@ -761,7 +772,7 @@ CONFIG_NSH_FILEIOSIZE=512 # CONFIG_NSH_CONSOLE=y # CONFIG_NSH_ALTCONDEV is not set -# CONFIG_NSH_ARCHINIT is not set +CONFIG_NSH_ARCHINIT=y # CONFIG_NSH_LOGIN is not set # CONFIG_NSH_CONSOLE_LOGIN is not set diff --git a/configs/esp32-core/smp/defconfig b/configs/esp32-core/smp/defconfig index 620896ec4f..145e67cfe1 100644 --- a/configs/esp32-core/smp/defconfig +++ b/configs/esp32-core/smp/defconfig @@ -51,8 +51,9 @@ CONFIG_DEBUG_ALERT=y # CONFIG_ARCH_HAVE_STACKCHECK is not set # CONFIG_ARCH_HAVE_HEAPCHECK is not set # CONFIG_DEBUG_SYMBOLS is not set -# CONFIG_ARCH_HAVE_CUSTOMOPT is not set +CONFIG_ARCH_HAVE_CUSTOMOPT=y # CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set CONFIG_DEBUG_FULLOPT=y # @@ -77,6 +78,10 @@ CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_FAMILY_LX6=y # CONFIG_XTENSA_USE_OVLY is not set CONFIG_XTENSA_CP_INITSET=0x0001 + +# +# ESP32 Peripheral Selection +# CONFIG_ESP32_UART=y # CONFIG_ESP32_SPI2 is not set # CONFIG_XTENSA_TIMER1 is not set @@ -84,24 +89,20 @@ CONFIG_ESP32_UART=y CONFIG_ESP32_UART0=y # CONFIG_ESP32_UART1 is not set # CONFIG_ESP32_UART2 is not set -CONFIG_ESP32_BT_RESERVE_DRAM=0 -CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0 -CONFIG_ESP32_ULP_COPROC_RESERVE_MEM=0 -# CONFIG_ESP32_GPIO_IRQ is not set -CONFIG_ESP32_UART0_TXPIN=0 -CONFIG_ESP32_UART0_RXPIN=0 - -# -# ESP32 Peripheral Selection -# # # Memory Configuration # +CONFIG_ESP32_BT_RESERVE_DRAM=0 +CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0 +CONFIG_ESP32_ULP_COPROC_RESERVE_MEM=0 +# CONFIG_ESP32_GPIO_IRQ is not set # # UART configuration # +CONFIG_ESP32_UART0_TXPIN=0 +CONFIG_ESP32_UART0_RXPIN=0 # # Architecture Options @@ -174,7 +175,11 @@ CONFIG_ESP32CORE_XTAL_40MZ=y # CONFIG_ESP32CORE_XTAL_26MHz is not set # CONFIG_ESP32CORE_RUN_IRAM is not set # CONFIG_BOARD_CRASHDUMP is not set -# CONFIG_LIB_BOARDCTL is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set # # RTOS Features @@ -225,6 +230,8 @@ CONFIG_SCHED_WAITPID=y # # CONFIG_MUTEX_TYPES is not set CONFIG_NPTHREAD_KEYS=4 +# CONFIG_PTHREAD_CLEANUP is not set +# CONFIG_CANCELLATION_POINTS is not set # # Performance Monitoring @@ -539,6 +546,8 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_ARCH_ROMGETC is not set # CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set # CONFIG_ARCH_HAVE_TLS is not set +# CONFIG_LIBC_IPv4_ADDRCONV is not set +# CONFIG_LIBC_IPv6_ADDRCONV is not set # CONFIG_LIBC_NETDB is not set # CONFIG_NETDB_HOSTFILE is not set @@ -601,10 +610,10 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_NULL is not set -# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXFFS is not set # CONFIG_EXAMPLES_NXHELLO is not set # CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set # CONFIG_EXAMPLES_NXLINES is not set # CONFIG_EXAMPLES_NXTERM is not set # CONFIG_EXAMPLES_NXTEXT is not set @@ -629,6 +638,7 @@ CONFIG_EXAMPLES_SMP_STACKSIZE=2048 # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_TIFF is not set # CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBSERIAL is not set # CONFIG_EXAMPLES_USBTERM is not set # CONFIG_EXAMPLES_WATCHDOG is not set # CONFIG_EXAMPLES_WEBSERVER is not set @@ -767,7 +777,7 @@ CONFIG_NSH_FILEIOSIZE=512 # CONFIG_NSH_CONSOLE=y # CONFIG_NSH_ALTCONDEV is not set -# CONFIG_NSH_ARCHINIT is not set +CONFIG_NSH_ARCHINIT=y # CONFIG_NSH_LOGIN is not set # CONFIG_NSH_CONSOLE_LOGIN is not set diff --git a/configs/esp32-core/src/esp32_bringup.c b/configs/esp32-core/src/esp32_bringup.c index 0267217785..b5121b2a4d 100644 --- a/configs/esp32-core/src/esp32_bringup.c +++ b/configs/esp32-core/src/esp32_bringup.c @@ -38,7 +38,11 @@ ****************************************************************************/ #include + #include +#include +#include + #include "esp32-core.h" /**************************************************************************** @@ -65,5 +69,23 @@ int esp32_bringup(void) { + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + + /* If we got here then perhaps not all initialization was successful, but + * at least enough succeeded to bring-up NSH with perhaps reduced + * capabilities. + */ + + UNUSED(ret); return OK; } -- GitLab From a9a39800a43b66e92373ede8415bb1d1b7d018db Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 19 Dec 2016 11:14:08 -0600 Subject: [PATCH 731/734] Xtensa ESP32: Fixes some double faults and user errors, but I do not fully understand why. --- arch/xtensa/src/common/xtensa_coproc.S | 28 +++++++++++++++++--------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_coproc.S b/arch/xtensa/src/common/xtensa_coproc.S index 0e7b3bafa4..c6ae294193 100644 --- a/arch/xtensa/src/common/xtensa_coproc.S +++ b/arch/xtensa/src/common/xtensa_coproc.S @@ -241,16 +241,18 @@ xtensa_coproc_savestate: RET(16) #else + ENTRY(32) /* Need to preserve a8-15. _xtensa_coproc_savestate modifies a2-a7, - * a13-a15. So only a13-a15 need be preserved. + * a13-a15. So a13-a15 may need to be preserved. */ - ENTRY(24) s32i a0, sp, LOCAL_OFFSET(1) /* Save return address */ - s32i a13, sp, LOCAL_OFFSET(2) +#if 0 + s32i a13, sp, LOCAL_OFFSET(2) /* Save clobbered registers */ s32i a14, sp, LOCAL_OFFSET(3) s32i a15, sp, LOCAL_OFFSET(4) +#endif /* Call _xtensa_coproc_savestate() with A2=address of co-processor * save area. @@ -261,11 +263,13 @@ xtensa_coproc_savestate: /* Restore a13-15 and return */ l32i a0, sp, LOCAL_OFFSET(1) /* Recover return address */ - l32i a13, sp, LOCAL_OFFSET(2) +#if 0 + l32i a13, sp, LOCAL_OFFSET(2) /* Restore clobbered registers */ l32i a14, sp, LOCAL_OFFSET(3) l32i a15, sp, LOCAL_OFFSET(4) +#endif - RET(24) + RET(32) #endif @@ -441,16 +445,18 @@ xtensa_coproc_restorestate: RET(16) #else + ENTRY(32) /* Need to preserve a8-15. _xtensa_coproc_savestate modifies a2-a7, - * a13-a15. So only a13-a15 need be preserved. + * a13-a15. So a13-a15 may need to be preserved. */ - ENTRY(24) s32i a0, sp, LOCAL_OFFSET(1) /* Save return address */ - s32i a13, sp, LOCAL_OFFSET(2) +#if 0 + s32i a13, sp, LOCAL_OFFSET(2) /* Save clobbered values */ s32i a14, sp, LOCAL_OFFSET(3) s32i a15, sp, LOCAL_OFFSET(4) +#endif /* Call _xtensa_coproc_restorestate() with A2=address of co-processor * save area. Registers a0, a2-a7, a13-a15 have been trashed. @@ -461,11 +467,13 @@ xtensa_coproc_restorestate: /* Restore a13-15 and return */ l32i a0, sp, LOCAL_OFFSET(1) /* Recover return address */ - l32i a13, sp, LOCAL_OFFSET(2) +#if 0 + l32i a13, sp, LOCAL_OFFSET(2) /* Restore clobbered registers */ l32i a14, sp, LOCAL_OFFSET(3) l32i a15, sp, LOCAL_OFFSET(4) +#endif - RET(24) + RET(32) #endif -- GitLab From 097f09cb0208f246e4c20a79bc459b78bc0f8ed2 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 19 Dec 2016 11:50:28 -0600 Subject: [PATCH 732/734] Xtensa ESP32: Corrects timer initialization and timer input frequency. --- arch/xtensa/src/esp32/esp32_timerisr.c | 11 +++-------- configs/esp32-core/include/board.h | 4 +++- 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/arch/xtensa/src/esp32/esp32_timerisr.c b/arch/xtensa/src/esp32/esp32_timerisr.c index 14f8a1cdfe..09653a582f 100644 --- a/arch/xtensa/src/esp32/esp32_timerisr.c +++ b/arch/xtensa/src/esp32/esp32_timerisr.c @@ -170,20 +170,15 @@ static int esp32_timerisr(int irq, uint32_t *regs) void xtensa_timer_initialize(void) { - uint64_t divisor; + uint32_t divisor; uint32_t count; /* Configured the timer0 as the system timer. * - * divisor = BOARD_CLOCK_FREQUENCY / ticks_per_sec - * = BOARD_CLOCK_FREQUENCY / (ticks_per_usec * 1000000) - * = (1000000 * BOARD_CLOCK_FREQUENCY) / ticks_per_usec - * - * A long long calculation is used to preserve accuracy in all cases. + * divisor = BOARD_CLOCK_FREQUENCY / ticks_per_sec */ - divisor = (1000000ull * (uint64_t)BOARD_CLOCK_FREQUENCY) / CONFIG_USEC_PER_TICK; - DEBUGASSERT(divisor <= UINT32_MAX); + divisor = BOARD_CLOCK_FREQUENCY / CLOCKS_PER_SEC; g_tick_divisor = divisor; /* Set up periodic timer */ diff --git a/configs/esp32-core/include/board.h b/configs/esp32-core/include/board.h index e3b2e85a87..fb0c327482 100644 --- a/configs/esp32-core/include/board.h +++ b/configs/esp32-core/include/board.h @@ -56,7 +56,9 @@ #if 0 # define BOARD_CLOCK_FREQUENCY 80000000 #else -# define BOARD_CLOCK_FREQUENCY BOARD_XTAL_FREQUENCY + /* Hmmm... actually appears to be running at about 2 x the XTAL frequency */ + +# define BOARD_CLOCK_FREQUENCY (2 * BOARD_XTAL_FREQUENCY) #endif #endif /* __CONFIGS_ESP32_CORE_INCLUDE_BOARD_H */ -- GitLab From e61549d8b91c069aed09f37609f0f26003c15206 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 19 Dec 2016 13:57:37 -0600 Subject: [PATCH 733/734] Xtensa ESP32: Clean-up and fixes from last commits --- arch/xtensa/src/common/xtensa_coproc.S | 62 +++++++++++--------------- configs/esp32-core/src/Makefile | 2 +- configs/esp32-core/src/esp32_appinit.c | 2 +- 3 files changed, 28 insertions(+), 38 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_coproc.S b/arch/xtensa/src/common/xtensa_coproc.S index c6ae294193..6af4849cee 100644 --- a/arch/xtensa/src/common/xtensa_coproc.S +++ b/arch/xtensa/src/common/xtensa_coproc.S @@ -225,11 +225,14 @@ xtensa_coproc_savestate: #ifdef __XTENSA_CALL0_ABI__ /* Need to preserve a8-11. _xtensa_coproc_savestate modifies a2-a7, - * a13-a15. So no registers need be saved. + * a13-a15. a12-a15 are callee saved registers so a13-a14 must be + * preserved. */ ENTRY(16) - s32i a0, sp, LOCAL_OFFSET(1) /* Save return address */ + s32i a13, sp, LOCAL_OFFSET(1) /* Save clobbered registers */ + s32i a14, sp, LOCAL_OFFSET(2) + s32i a15, sp, LOCAL_OFFSET(3) /* Call _xtensa_coproc_savestate() with A2=address of co-processor * save area. @@ -237,22 +240,20 @@ xtensa_coproc_savestate: call0 _xtensa_coproc_savestate - l32i a0, sp, LOCAL_OFFSET(1) /* Recover return address */ + /* Restore a13-15 and return */ + + l32i a13, sp, LOCAL_OFFSET(1) /* Restore clobbered registers */ + l32i a14, sp, LOCAL_OFFSET(2) + l32i a15, sp, LOCAL_OFFSET(3) RET(16) #else - ENTRY(32) - /* Need to preserve a8-15. _xtensa_coproc_savestate modifies a2-a7, * a13-a15. So a13-a15 may need to be preserved. */ + ENTRY(32 /*16*/) /* REVISIT: Why 32? */ s32i a0, sp, LOCAL_OFFSET(1) /* Save return address */ -#if 0 - s32i a13, sp, LOCAL_OFFSET(2) /* Save clobbered registers */ - s32i a14, sp, LOCAL_OFFSET(3) - s32i a15, sp, LOCAL_OFFSET(4) -#endif /* Call _xtensa_coproc_savestate() with A2=address of co-processor * save area. @@ -260,16 +261,10 @@ xtensa_coproc_savestate: call0 _xtensa_coproc_savestate - /* Restore a13-15 and return */ + /* Restore a0 and return */ l32i a0, sp, LOCAL_OFFSET(1) /* Recover return address */ -#if 0 - l32i a13, sp, LOCAL_OFFSET(2) /* Restore clobbered registers */ - l32i a14, sp, LOCAL_OFFSET(3) - l32i a15, sp, LOCAL_OFFSET(4) -#endif - - RET(32) + RET(32 /*16*/) /* REVISIT: Why 32? */ #endif @@ -429,11 +424,14 @@ xtensa_coproc_restorestate: #ifdef __XTENSA_CALL0_ABI__ /* Need to preserve a8-11. _xtensa_coproc_restorestate modifies a2-a7, - * a13-a15. So no registers need be saved. + * a13-a15. a12-a15 are callee saved registers so a13-a14 must be + * preserved. */ ENTRY(16) - s32i a0, sp, LOCAL_OFFSET(1) /* Save return address */ + s32i a13, sp, LOCAL_OFFSET(1) /* Save clobbered values */ + s32i a14, sp, LOCAL_OFFSET(2) + s32i a15, sp, LOCAL_OFFSET(3) /* Call _xtensa_coproc_restorestate() with A2=address of co-processor * save area. Registers a0, a2-a7, a13-a15 have been trashed. @@ -441,22 +439,20 @@ xtensa_coproc_restorestate: call0 _xtensa_coproc_restorestate - l32i a0, sp, LOCAL_OFFSET(1) /* Recover return address */ + /* Restore a13-a15 and return */ + + l32i a13, sp, LOCAL_OFFSET(1) /* Restore clobbered registers */ + l32i a14, sp, LOCAL_OFFSET(2) + l32i a15, sp, LOCAL_OFFSET(3) RET(16) #else - ENTRY(32) - /* Need to preserve a8-15. _xtensa_coproc_savestate modifies a2-a7, * a13-a15. So a13-a15 may need to be preserved. */ + ENTRY(32 /*16*/) /* REVISIT: Why 32? */ s32i a0, sp, LOCAL_OFFSET(1) /* Save return address */ -#if 0 - s32i a13, sp, LOCAL_OFFSET(2) /* Save clobbered values */ - s32i a14, sp, LOCAL_OFFSET(3) - s32i a15, sp, LOCAL_OFFSET(4) -#endif /* Call _xtensa_coproc_restorestate() with A2=address of co-processor * save area. Registers a0, a2-a7, a13-a15 have been trashed. @@ -464,16 +460,10 @@ xtensa_coproc_restorestate: call0 _xtensa_coproc_restorestate - /* Restore a13-15 and return */ + /* Restore a0 and return */ l32i a0, sp, LOCAL_OFFSET(1) /* Recover return address */ -#if 0 - l32i a13, sp, LOCAL_OFFSET(2) /* Restore clobbered registers */ - l32i a14, sp, LOCAL_OFFSET(3) - l32i a15, sp, LOCAL_OFFSET(4) -#endif - - RET(32) + RET(32 /*16*/) /* REVISIT: Why 32? */ #endif diff --git a/configs/esp32-core/src/Makefile b/configs/esp32-core/src/Makefile index 2e23d2db4b..46ed73e5c3 100644 --- a/configs/esp32-core/src/Makefile +++ b/configs/esp32-core/src/Makefile @@ -42,7 +42,7 @@ ASRCS = CSRCS = esp32_boot.c esp32_bringup.c ifeq ($(CONFIG_LIB_BOARDCTL),y) -CONFIG_CSRCS += esp32_appinit.c +CSRCS += esp32_appinit.c endif SCRIPTIN = $(SCRIPTDIR)$(DELIM)esp32.template diff --git a/configs/esp32-core/src/esp32_appinit.c b/configs/esp32-core/src/esp32_appinit.c index b352aa2fd2..ff8d1eb957 100644 --- a/configs/esp32-core/src/esp32_appinit.c +++ b/configs/esp32-core/src/esp32_appinit.c @@ -42,7 +42,7 @@ #include #include -#include "esp32_core.h" +#include "esp32-core.h" #ifdef CONFIG_LIB_BOARDCTL -- GitLab From e5182acbe3ffff55763e28394b85e43d38db6b0a Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 19 Dec 2016 14:12:19 -0600 Subject: [PATCH 734/734] Xtensa ESP32: Make sure that SMP configuratin still builds without errors. --- arch/xtensa/src/common/xtensa_cpupause.c | 1 + arch/xtensa/src/esp32/esp32_cpuint.c | 2 ++ arch/xtensa/src/esp32/esp32_cpustart.c | 1 + arch/xtensa/src/esp32/esp32_intercpu_interrupt.c | 6 +++--- 4 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/xtensa/src/common/xtensa_cpupause.c b/arch/xtensa/src/common/xtensa_cpupause.c index 8d1fcd0371..370054d5c7 100644 --- a/arch/xtensa/src/common/xtensa_cpupause.c +++ b/arch/xtensa/src/common/xtensa_cpupause.c @@ -164,6 +164,7 @@ int up_cpu_paused(int cpu) } spin_unlock(&g_cpu_wait[cpu]); + return OK; } /**************************************************************************** diff --git a/arch/xtensa/src/esp32/esp32_cpuint.c b/arch/xtensa/src/esp32/esp32_cpuint.c index 4fba5b3e31..8d43741ac0 100644 --- a/arch/xtensa/src/esp32/esp32_cpuint.c +++ b/arch/xtensa/src/esp32/esp32_cpuint.c @@ -53,6 +53,8 @@ #include "esp32_cpuint.h" #include "xtensa.h" +#include "sched/sched.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c index fbed36350b..5c44837efb 100644 --- a/arch/xtensa/src/esp32/esp32_cpustart.c +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -42,6 +42,7 @@ #include #include #include +#include #include #include diff --git a/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c b/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c index ccbe9de4e5..da7d70aaf9 100644 --- a/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c +++ b/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c @@ -86,7 +86,7 @@ static int esp32_fromcpu_interrupt(int fromcpu) int intcode; int tocpu; - DEBUGASSERT(regs != NULL); + DEBUGASSERT((unsigned)fromcpu < CONFIG_SMP_NCPUS); /* Clear the interrupt from the other CPU */ @@ -155,8 +155,8 @@ int xtensa_intercpu_interrupt(int tocpu, int intcode) { int fromcpu; - DEBUGASSERT((unsigned)cpu < CONFIG_SMP_NCPUS && - (unsigned)incode <= UINT8_MAX); + DEBUGASSERT((unsigned)tocpu < CONFIG_SMP_NCPUS && + (unsigned)intcode <= UINT8_MAX); /* Disable context switching so that some other thread does not attempt to * take the spinlock on the same CPU. -- GitLab